--- /dev/null	Mon Aug  5 17:29:49 2019
+++ new/usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h	Mon Aug  5 17:29:49 2019
@@ -0,0 +1,84442 @@
+/*
+* CDDL HEADER START
+*
+* The contents of this file are subject to the terms of the
+* Common Development and Distribution License, v.1,  (the "License").
+* You may not use this file except in compliance with the License.
+*
+* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+* or http://opensource.org/licenses/CDDL-1.0.
+* See the License for the specific language governing permissions
+* and limitations under the License.
+*
+* When distributing Covered Code, include this CDDL HEADER in each
+* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+* If applicable, add the following below this CDDL HEADER, with the
+* fields enclosed by brackets "[]" replaced with your own identifying
+* information: Portions Copyright [yyyy] [name of copyright owner]
+*
+* CDDL HEADER END
+*/
+
+/*
+* Copyright 2014-2017 Cavium, Inc. 
+* The contents of this file are subject to the terms of the Common Development 
+* and Distribution License, v.1,  (the "License").
+
+* You may not use this file except in compliance with the License.
+
+* You can obtain a copy of the License at available 
+* at http://opensource.org/licenses/CDDL-1.0
+
+* See the License for the specific language governing permissions and 
+* limitations under the License.
+*/
+
+#ifndef REG_ADDR_H
+#define REG_ADDR_H
+
+#define PGLCS_REG_INT_STS                                                                                    0x001d00UL //Access:R    DataWidth:0x2    // Multi Field Register.
+  #define PGLCS_REG_INT_STS_ADDRESS_ERROR                                                                    (0x1<<0) // Signals an unknown address to the rf module.
+  #define PGLCS_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                              0
+  #define PGLCS_REG_INT_STS_RASDP_ERROR_K2_E5                                                                (0x1<<1) // It indicates rasdp error
+  #define PGLCS_REG_INT_STS_RASDP_ERROR_K2_E5_SHIFT                                                          1
+#define PGLCS_REG_INT_MASK                                                                                   0x001d04UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PGLCS_REG_INT_MASK_ADDRESS_ERROR                                                                   (0x1<<0) // This bit masks, when set, the Interrupt bit: PGLCS_REG_INT_STS.ADDRESS_ERROR .
+  #define PGLCS_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                             0
+  #define PGLCS_REG_INT_MASK_RASDP_ERROR_K2_E5                                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: PGLCS_REG_INT_STS.RASDP_ERROR .
+  #define PGLCS_REG_INT_MASK_RASDP_ERROR_K2_E5_SHIFT                                                         1
+#define PGLCS_REG_INT_STS_WR                                                                                 0x001d08UL //Access:WR   DataWidth:0x2    // Multi Field Register.
+  #define PGLCS_REG_INT_STS_WR_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define PGLCS_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                           0
+  #define PGLCS_REG_INT_STS_WR_RASDP_ERROR_K2_E5                                                             (0x1<<1) // It indicates rasdp error
+  #define PGLCS_REG_INT_STS_WR_RASDP_ERROR_K2_E5_SHIFT                                                       1
+#define PGLCS_REG_INT_STS_CLR                                                                                0x001d0cUL //Access:RC   DataWidth:0x2    // Multi Field Register.
+  #define PGLCS_REG_INT_STS_CLR_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define PGLCS_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                          0
+  #define PGLCS_REG_INT_STS_CLR_RASDP_ERROR_K2_E5                                                            (0x1<<1) // It indicates rasdp error
+  #define PGLCS_REG_INT_STS_CLR_RASDP_ERROR_K2_E5_SHIFT                                                      1
+#define PGLCS_REG_RASDP_ERROR_MODE_EN_OFF_K2_E5                                                              0x001d10UL //Access:RW   DataWidth:0x1    // Disable rasdp error mode check
+#define PGLCS_REG_DBG_SELECT_K2_E5                                                                           0x001d14UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PGLCS_REG_DBG_DWORD_ENABLE_K2_E5                                                                     0x001d18UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PGLCS_REG_DBG_SHIFT_K2_E5                                                                            0x001d1cUL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PGLCS_REG_DBG_FORCE_VALID_K2_E5                                                                      0x001d20UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PGLCS_REG_DBG_FORCE_FRAME_K2_E5                                                                      0x001d24UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PGLCS_REG_PGL_CS                                                                                     0x002000UL //Access:RW   DataWidth:0x20   // Control and status interface for PCIE IP.
+#define PGLCS_REG_PGL_CS_SIZE_BB                                                                             2048
+#define PGLCS_REG_PGL_CS_SIZE_K2_E5                                                                          1024
+#define PGLCS_REG_PGL_CS_VF_1_K2_E5                                                                          0x003000UL //Access:RW   DataWidth:0x20   // 
+#define PGLCS_REG_PGL_CS_VF_1_SIZE                                                                           256
+#define PGLCS_REG_PGL_CS_SHADOW_K2_E5                                                                        0x003400UL //Access:RW   DataWidth:0x20   // 
+#define PGLCS_REG_PGL_CS_SHADOW_SIZE                                                                         128
+#define PGLCS_REG_PGL_CS_SHADOW_VF_K2_E5                                                                     0x003600UL //Access:RW   DataWidth:0x20   // 
+#define PGLCS_REG_PGL_CS_SHADOW_VF_SIZE                                                                      128
+#define PGLCS_REG_FIRST_VF_K2_E5                                                                             0x003800UL //Access:RW   DataWidth:0x8    // First VF
+#define PGLCS_REG_DISCARD_POISONED_MCTP_TGTWR_K2_E5                                                          0x003804UL //Access:RW   DataWidth:0x2    // Discard when poisoned
+#define PGLCS_REG_RX_HDR_ALMOST_FULL_THR_HIGH_K2_E5                                                          0x003808UL //Access:RW   DataWidth:0x8    // rx_hdr_almost_full_thr_high
+#define PGLCS_REG_RX_HDR_ALMOST_FULL_THR_LOW_K2_E5                                                           0x00380cUL //Access:RW   DataWidth:0x8    // rx_hdr_almost_full_thr_low
+#define PGLCS_REG_RX_DATA_ALMOST_FULL_THR_HIGH_K2_E5                                                         0x003810UL //Access:RW   DataWidth:0x8    // rx_data_almost_full_thr_high
+#define PGLCS_REG_RX_DATA_ALMOST_FULL_THR_LOW_K2_E5                                                          0x003814UL //Access:RW   DataWidth:0x8    // rx_data_almost_full_thr_low
+#define PGLCS_REG_STATISTIC_MASK_K2_E5                                                                       0x003818UL //Access:RW   DataWidth:0x6    // Statistic mask enable Bit5 :  Mask Message VDM Bit4 :  Mask memory read Bit3 :  Mask memory write Bit2 :  Mask Completion Bit1 :  Mask TX Bit0 :  Mask RX
+#define PGLCS_REG_RX_TLP_NUM_K2_E5                                                                           0x00381cUL //Access:R    DataWidth:0x20   // Number of RX tlp  are received
+#define PGLCS_REG_RX_TLP_BYTE_NUM_K2_E5                                                                      0x003820UL //Access:R    DataWidth:0x20   // Byte number of RX are received
+#define PGLCS_REG_TX_TLP_NUM_K2_E5                                                                           0x003824UL //Access:R    DataWidth:0x20   // tx number of tlp  sent
+#define PGLCS_REG_TX_TLP_BYTE_NUM_K2_E5                                                                      0x003828UL //Access:R    DataWidth:0x20   // byte number of tlp sent
+#define PGLCS_REG_ECO_RESERVED_K2_E5                                                                         0x00382cUL //Access:RW   DataWidth:0x20   // Debug only: Reserved bits for ECO. Bit 0 - For ending "endless completion". 0 - When receiving a completion timeout while receiving a completion on the same tag, terminate the received completion. 1 - don't terminate (ignore this case). Bit 1 - For CQ83850. 0 - Add the fix for CQ83850 - continue 1cycle delay when we have a new 'hv'. 1 - Do not add the fix. Bit 2 - For CQ84726 - RW ordering. Should be the same as bit 1 in PGLUE_B eco_reserved. 0 - Add the fix. 1 - Do not add the fix.
+#define PGLCS_REG_SYNCFIFO_POP_UNDERFLOW_K2_E5                                                               0x003830UL //Access:R    DataWidth:0x4    // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW header sync fifo pop underflow 3 - TXW data sync fifo pop underflow
+#define PGLCS_REG_SYNCFIFO_PUSH_OVERFLOW_K2_E5                                                               0x003834UL //Access:R    DataWidth:0x6    // 0 - RX target read and config sync fifo push overflow 1 - RX header sync fifo push overflow 5:2 - RX data sync fifo push overflow (1 bit per each 128b instance)
+#define PGLCS_REG_TX_SYNCFIFO_POP_STATUS_K2_E5                                                               0x003838UL //Access:R    DataWidth:0x14   // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW header sync fifo pop status 19:15 - TXW data sync fifo pop status
+#define PCIEIP_REG_DEVICE_ID_VENDOR_ID_REG_K2_E5                                                             0x000000UL //Access:RW   DataWidth:0x20   // Device ID and Vendor ID Register.
+  #define PCIEIP_REG_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_K2_E5                                       (0xffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_K2_E5_SHIFT                                 0
+  #define PCIEIP_REG_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_K2_E5                                       (0xffff<<16) // Device ID. Vendor Assigned Device Identifier.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_K2_E5_SHIFT                                 16
+#define PCIEIP_REG_DEVICE_VENDOR_ID_BB                                                                       0x000000UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DEVICE_VENDOR_ID_VENDOR_ID_BB                                                           (0xffff<<0) // This register identifies the PCI adapter. This value can be written by firmware through the PCIE private register space VENDOR_ID to modify this read value to the host. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_DEVICE_VENDOR_ID_VENDOR_ID_BB_SHIFT                                                     0
+  #define PCIEIP_REG_DEVICE_VENDOR_ID_DEVICE_ID_BB                                                           (0xffff<<16) // This register identifies the device on the PCIE adapter. This value can be written by firmware through the PCIE private register space DEVICE_ID, which modifes the value read by host. The default value reflects the value of DEVICE_ID in version.v or strap pins user_device_id depending on build options chosen by user. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_DEVICE_VENDOR_ID_DEVICE_ID_BB_SHIFT                                                     16
+#define PCIEIP_REG_STATUS_COMMAND_REG_K2_E5                                                                  0x000004UL //Access:RW   DataWidth:0x20   // Command and Status Register.
+  #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_K2_E5                                                (0x1<<0) // Enables IO Access Response.   You cannot write to this register if your configuration has no IO bars; that is, the internal signal has_io_bar=0.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
+  #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_K2_E5_SHIFT                                          0
+  #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_K2_E5                                         (0x1<<1) // Enables Memory Access Response.   You cannot write to this register if your configuration has no MEM bars; that is, the internal signal has_mem_bar=0.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
+  #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_K2_E5_SHIFT                                   1
+  #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_K2_E5                                        (0x1<<2) // Bus Master Enable. Controls Issuing of Memory and I/O Requests.
+  #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_K2_E5_SHIFT                                  2
+  #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_K2_E5                              (0x1<<3) // Special Cycle Enable.
+  #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_K2_E5_SHIFT                        3
+  #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_K2_E5                                            (0x1<<4) // Memory Write and Invalidate.
+  #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_K2_E5_SHIFT                                      4
+  #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_K2_E5                                     (0x1<<5) // VGA Palette Snoop.
+  #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_K2_E5_SHIFT                               5
+  #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_K2_E5                                        (0x1<<6) // Controls Logging of Poisoned TLPs.
+  #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_K2_E5_SHIFT                                  6
+  #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_K2_E5                                        (0x1<<7) // IDSEL Stepping.
+  #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_K2_E5_SHIFT                                  7
+  #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_K2_E5                                               (0x1<<8) // Enables Error Reporting.
+  #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_K2_E5_SHIFT                                         8
+  #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_K2_E5                                               (0x1<<10) // Controls generation of interrupts by a function.
+  #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_K2_E5_SHIFT                                         10
+  #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_RESERV_K2_E5                                                (0x1f<<11) // Reserved.
+  #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_RESERV_K2_E5_SHIFT                                          11
+  #define PCIEIP_REG_STATUS_COMMAND_REG_INT_STATUS_K2_E5                                                     (0x1<<19) // Emulation interrupt pending.
+  #define PCIEIP_REG_STATUS_COMMAND_REG_INT_STATUS_K2_E5_SHIFT                                               19
+  #define PCIEIP_REG_STATUS_COMMAND_REG_CAP_LIST_K2_E5                                                       (0x1<<20) // Extended Capability.
+  #define PCIEIP_REG_STATUS_COMMAND_REG_CAP_LIST_K2_E5_SHIFT                                                 20
+  #define PCIEIP_REG_STATUS_COMMAND_REG_FAST_66MHZ_CAP_K2_E5                                                 (0x1<<21) // PCI 66MHz Capability.
+  #define PCIEIP_REG_STATUS_COMMAND_REG_FAST_66MHZ_CAP_K2_E5_SHIFT                                           21
+  #define PCIEIP_REG_STATUS_COMMAND_REG_FAST_B2B_CAP_K2_E5                                                   (0x1<<23) // Fast Back to Back Transaction Capable and Enable.
+  #define PCIEIP_REG_STATUS_COMMAND_REG_FAST_B2B_CAP_K2_E5_SHIFT                                             23
+  #define PCIEIP_REG_STATUS_COMMAND_REG_MASTER_DPE_K2_E5                                                     (0x1<<24) // Controls poisoned Completion and Request error reporting.
+  #define PCIEIP_REG_STATUS_COMMAND_REG_MASTER_DPE_K2_E5_SHIFT                                               24
+  #define PCIEIP_REG_STATUS_COMMAND_REG_DEV_SEL_TIMING_K2_E5                                                 (0x3<<25) // Device Select Timing.
+  #define PCIEIP_REG_STATUS_COMMAND_REG_DEV_SEL_TIMING_K2_E5_SHIFT                                           25
+  #define PCIEIP_REG_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_K2_E5                                          (0x1<<27) // Completer Abort Error.
+  #define PCIEIP_REG_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_K2_E5_SHIFT                                    27
+  #define PCIEIP_REG_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_K2_E5                                              (0x1<<28) // Completer Abort received.
+  #define PCIEIP_REG_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_K2_E5_SHIFT                                        28
+  #define PCIEIP_REG_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_K2_E5                                              (0x1<<29) // Unsupported request completion status received.
+  #define PCIEIP_REG_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_K2_E5_SHIFT                                        29
+  #define PCIEIP_REG_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_K2_E5                                               (0x1<<30) // Fatal or Non-Fatal Error Message sent by function.
+  #define PCIEIP_REG_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_K2_E5_SHIFT                                         30
+  #define PCIEIP_REG_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_K2_E5                                            (0x1<<31) // Poisoned TLP received by function.
+  #define PCIEIP_REG_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_K2_E5_SHIFT                                      31
+#define PCIEIP_REG_STATUS_COMMAND_BB                                                                         0x000004UL //Access:RW   DataWidth:0x20   // This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)
+  #define PCIEIP_REG_STATUS_COMMAND_IO_SPACE_BB                                                              (0x1<<0) // This bit indicates that the device does not support I/O space access because it is zero and can not be modified. IO transactions targeting this device return completion with UR status . Path = i_cfg_func.i_cfg_public.i_cfg_dec
+  #define PCIEIP_REG_STATUS_COMMAND_IO_SPACE_BB_SHIFT                                                        0
+  #define PCIEIP_REG_STATUS_COMMAND_MEM_SPACE_BB                                                             (0x1<<1) // This bit controls the enabling of the memory space. When disabled, memory transactions targeting this device return completion with UR status Path = i_cfg_func.i_cfg_public.i_cfg_dec
+  #define PCIEIP_REG_STATUS_COMMAND_MEM_SPACE_BB_SHIFT                                                       1
+  #define PCIEIP_REG_STATUS_COMMAND_BUS_MASTER_BB                                                            (0x1<<2) // This bit controls the enabling of the bus master activity by this device. When low, it disables an Endpoint function from issuing memory or IO requests. Also disables the ability to issue MSI messages. Path = i_cfg_func.i_cfg_public.i_cfg_dec
+  #define PCIEIP_REG_STATUS_COMMAND_BUS_MASTER_BB_SHIFT                                                      2
+  #define PCIEIP_REG_STATUS_COMMAND_SPECIAL_CYCLES_BB                                                        (0x1<<3) // Does not apply to PCIE Path = i_cfg_func.i_cfg_public.i_cfg_dec
+  #define PCIEIP_REG_STATUS_COMMAND_SPECIAL_CYCLES_BB_SHIFT                                                  3
+  #define PCIEIP_REG_STATUS_COMMAND_MWI_CYCLES_BB                                                            (0x1<<4) // Does not apply to PCIE Path = i_cfg_func.i_cfg_public.i_cfg_dec
+  #define PCIEIP_REG_STATUS_COMMAND_MWI_CYCLES_BB_SHIFT                                                      4
+  #define PCIEIP_REG_STATUS_COMMAND_VGA_SNOOP_BB                                                             (0x1<<5) // Does not apply to PCIE Path = i_cfg_func.i_cfg_public.i_cfg_dec
+  #define PCIEIP_REG_STATUS_COMMAND_VGA_SNOOP_BB_SHIFT                                                       5
+  #define PCIEIP_REG_STATUS_COMMAND_PERR_ENA_BB                                                              (0x1<<6) // This bit enables the write to the Master data parity error status bit. If this bit is cleared , the master data parity error status bit will never be set. Path = i_cfg_func.i_cfg_public.i_cfg_dec
+  #define PCIEIP_REG_STATUS_COMMAND_PERR_ENA_BB_SHIFT                                                        6
+  #define PCIEIP_REG_STATUS_COMMAND_STEPPING_BB                                                              (0x1<<7) // Does not apply to PCIE Path = i_cfg_func.i_cfg_public.i_cfg_dec
+  #define PCIEIP_REG_STATUS_COMMAND_STEPPING_BB_SHIFT                                                        7
+  #define PCIEIP_REG_STATUS_COMMAND_SERR_ENA_BB                                                              (0x1<<8) // When set, this bit enables the non fatal and fatal errors detected by the function to be reported to the Root Complex. The function reports such errors to the Root Complex if it is enabled to do so either through this bit or though PCI express specific bits in DCR Path = i_cfg_func.i_cfg_public.i_cfg_dec
+  #define PCIEIP_REG_STATUS_COMMAND_SERR_ENA_BB_SHIFT                                                        8
+  #define PCIEIP_REG_STATUS_COMMAND_FAST_B2B_BB                                                              (0x1<<9) // Does not apply to PCIE Path = i_cfg_func.i_cfg_public.i_cfg_dec
+  #define PCIEIP_REG_STATUS_COMMAND_FAST_B2B_BB_SHIFT                                                        9
+  #define PCIEIP_REG_STATUS_COMMAND_INT_DISABLE_BB                                                           (0x1<<10) // When this bit is set, function is not permitted to generate IntX interrupt messages (de-asserted) regardless of any internal chip logic. Setting this bit has no effect on the INT_STATUS bit below. Writing this bit to '0' will un-mask the interrupt and let it run normally. Path = i_cfg_func.i_cfg_public.i_cfg_dec
+  #define PCIEIP_REG_STATUS_COMMAND_INT_DISABLE_BB_SHIFT                                                     10
+  #define PCIEIP_REG_STATUS_COMMAND_RESERVED_BB                                                              (0x1f<<11) // These bits are reserved and tied low per the PCIE specification. Path = i_cfg_func.i_cfg_public.i_cfg_dec
+  #define PCIEIP_REG_STATUS_COMMAND_RESERVED_BB_SHIFT                                                        11
+  #define PCIEIP_REG_STATUS_COMMAND_RESERVED1_BB                                                             (0x7<<16) // These bits are reserved and tied low per the PCIE specification. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_STATUS_COMMAND_RESERVED1_BB_SHIFT                                                       16
+  #define PCIEIP_REG_STATUS_COMMAND_INT_STATUS_BB                                                            (0x1<<19) // This bit indicates the internal interrupt request state (before being masked by INT_DISABLE. A '0' indicates that no interrupt is pending. A '1' indicates that there is an interrupt pending. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_STATUS_COMMAND_INT_STATUS_BB_SHIFT                                                      19
+  #define PCIEIP_REG_STATUS_COMMAND_CAP_LIST_BB                                                              (0x1<<20) // This bit is tied high to indicate that the device supports a capability list. The list starts at address 0x40. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_STATUS_COMMAND_CAP_LIST_BB_SHIFT                                                        20
+  #define PCIEIP_REG_STATUS_COMMAND_CAP_66MHZ_BB                                                             (0x1<<21) // Does not apply to PCIE Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_STATUS_COMMAND_CAP_66MHZ_BB_SHIFT                                                       21
+  #define PCIEIP_REG_STATUS_COMMAND_RESERVED2_BB                                                             (0x1<<22) // These bits are reserved and tied low per the PCI specification. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_STATUS_COMMAND_RESERVED2_BB_SHIFT                                                       22
+  #define PCIEIP_REG_STATUS_COMMAND_FAST_B2B_CAP_BB                                                          (0x1<<23) // Does not apply to PCIE. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_STATUS_COMMAND_FAST_B2B_CAP_BB_SHIFT                                                    23
+  #define PCIEIP_REG_STATUS_COMMAND_PRI_MSTR_PERR_BB                                                         (0x1<<24) // The master data parity error bit is set by a requester if the parity error enable bit is set in its command register and either of the following 2 conditions occur. If the requester receives a poisoned completion if the requester poisons a write request If the parity Error enable bit is cleared , the master data parity error status bit is never set Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_STATUS_COMMAND_PRI_MSTR_PERR_BB_SHIFT                                                   24
+  #define PCIEIP_REG_STATUS_COMMAND_DEVSEL_TIMING_BB                                                         (0x3<<25) // Does not apply to PCIE Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_STATUS_COMMAND_DEVSEL_TIMING_BB_SHIFT                                                   25
+  #define PCIEIP_REG_STATUS_COMMAND_PRI_SIG_TGT_ABT_BB                                                       (0x1<<27) // This bit is set when a function acting as a completer terminates a request by issuing Completer abort completion status to the requester Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_STATUS_COMMAND_PRI_SIG_TGT_ABT_BB_SHIFT                                                 27
+  #define PCIEIP_REG_STATUS_COMMAND_PRI_RCV_TGT_ABT_BB                                                       (0x1<<28) // This bit is set when a requester receives a completion with completer abort completion status. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_STATUS_COMMAND_PRI_RCV_TGT_ABT_BB_SHIFT                                                 28
+  #define PCIEIP_REG_STATUS_COMMAND_PRI_RCV_MSTR_ABT_BB                                                      (0x1<<29) // This bit is set when a requester receives a completion with UR completion status Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_STATUS_COMMAND_PRI_RCV_MSTR_ABT_BB_SHIFT                                                29
+  #define PCIEIP_REG_STATUS_COMMAND_PRI_SIG_SERR_BB                                                          (0x1<<30) // This bit is set when a function sends an ERR_FATAL or ERR_NONFATAL message and the SERR enable bit in the command register is set Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_STATUS_COMMAND_PRI_SIG_SERR_BB_SHIFT                                                    30
+  #define PCIEIP_REG_STATUS_COMMAND_PRI_PAR_ERR_BB                                                           (0x1<<31) // When this bit is set, it indicates that the function has received a poisoned TLP Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_STATUS_COMMAND_PRI_PAR_ERR_BB_SHIFT                                                     31
+#define PCIEIP_REG_CLASS_CODE_REVISION_ID_K2_E5                                                              0x000008UL //Access:RW   DataWidth:0x20   // Class Code and Revision ID Register.
+  #define PCIEIP_REG_CLASS_CODE_REVISION_ID_REVISION_ID_K2_E5                                                (0xff<<0) // Vendor chosen Revision ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_CLASS_CODE_REVISION_ID_REVISION_ID_K2_E5_SHIFT                                          0
+  #define PCIEIP_REG_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_K2_E5                                          (0xff<<8) // Class Code Programming Interface.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_K2_E5_SHIFT                                    8
+  #define PCIEIP_REG_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_K2_E5                                              (0xff<<16) // Subclass Code to represent Device Type.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_K2_E5_SHIFT                                        16
+  #define PCIEIP_REG_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_K2_E5                                            (0xff<<24) // Base Class Code to represent Device Type.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_K2_E5_SHIFT                                      24
+#define PCIEIP_REG_REV_ID_CLASS_CODE_BB                                                                      0x000008UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REV_ID_CLASS_CODE_REV_ID_BB                                                             (0xff<<0) // This register identifies the revision of the PCI adapter. This value is written by firmware through the PCI register space REVISION_ID value to modify the read value to the host. The default value is provided by user_revision_id strap pins.
+  #define PCIEIP_REG_REV_ID_CLASS_CODE_REV_ID_BB_SHIFT                                                       0
+  #define PCIEIP_REG_REV_ID_CLASS_CODE_CLASS_CODE_BB                                                         (0xffffff<<8) // The 24-bit Class Code register identifies the generic function of the device. All of the legal values are specified in the PCI specification. This read value is controlled by the CLASS_CODE valid value in the PCI register space. The default value reflects the value of CLASS_CODE in version.v defined by user. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_REV_ID_CLASS_CODE_CLASS_CODE_BB_SHIFT                                                   8
+#define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_K2_E5                                        0x00000cUL //Access:RW   DataWidth:0x20   // BIST, Header Type, Cache Line Size, and Latency Timer Registers.
+  #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_K2_E5                      (0xff<<0) // Cache Line Size. Has no effect on PCIe device behavior.
+  #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_K2_E5_SHIFT                0
+  #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_K2_E5                 (0xff<<8) // Does not apply to PCI Express.
+  #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_K2_E5_SHIFT           8
+  #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_K2_E5                          (0x7f<<16) // Specifies Header Type.
+  #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_K2_E5_SHIFT                    16
+  #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_K2_E5                           (0x1<<23) // Specifies whether device is multifunction.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_K2_E5_SHIFT                     23
+  #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_K2_E5                                 (0xff<<24) // Optional for BIST support.
+  #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_K2_E5_SHIFT                           24
+#define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_BB                                                           0x00000cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_CACHE_LINE_SIZE_BB                                         (0xff<<0) // This field is implemented by PCIE device as a read/write field for legacy compatibility purposes. Path = i_cfg_func.i_cfg_public.i_cfg_dec
+  #define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_CACHE_LINE_SIZE_BB_SHIFT                                   0
+  #define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_LATENCY_TIMER_BB                                           (0xff<<8) // This register does not apply to PCI express and must be hardwired to zero Path = i_cfg_func.i_cfg_public.i_cfg_rd_mux
+  #define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_LATENCY_TIMER_BB_SHIFT                                     8
+  #define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_HEADER_TYPE_BB                                             (0xff<<16) // The 8-bit Header Type register identifies both the layout of bytes 10h through 3Fh of the Configuration space, as well as whether this adapter contains multiple functions. A value of 0x80 indicates a multi function device (Type 0) using the format specified in the PCI specification, while a value of 0x0 indicates a single function Type 0 device. Path = i_cfg_func.i_cfg_public.i_cfg_rd_mux
+  #define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_HEADER_TYPE_BB_SHIFT                                       16
+  #define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_BIST_BB                                                    (0xff<<24) // The 8-bit BIST register is used to initiate and report the results of any Built-In-Self-Test. This value can be written by firmware through the PCI register space BIST register to modify the read value to the host. Path = i_cfg_func.i_cfg_public.i_cfg_dec
+  #define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_BIST_BB_SHIFT                                              24
+#define PCIEIP_REG_BAR0_REG_K2_E5                                                                            0x000010UL //Access:RW   DataWidth:0x20   // BAR0 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_REG_BAR0_REG_BAR0_MEM_IO_K2_E5                                                              (0x1<<0) // BAR0 Memory Space Indicator.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
+  #define PCIEIP_REG_BAR0_REG_BAR0_MEM_IO_K2_E5_SHIFT                                                        0
+  #define PCIEIP_REG_BAR0_REG_BAR0_TYPE_K2_E5                                                                (0x3<<1) // BAR0 32-bit or 64-bit.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
+  #define PCIEIP_REG_BAR0_REG_BAR0_TYPE_K2_E5_SHIFT                                                          1
+  #define PCIEIP_REG_BAR0_REG_BAR0_PREFETCH_K2_E5                                                            (0x1<<3) // BAR0 Prefetchable.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
+  #define PCIEIP_REG_BAR0_REG_BAR0_PREFETCH_K2_E5_SHIFT                                                      3
+  #define PCIEIP_REG_BAR0_REG_BAR0_START_K2_E5                                                               (0xfffffff<<4) // BAR0 Base Address.   Note: The access attributes of this field are as follows:  - Dbi: R/W if enabled else R
+  #define PCIEIP_REG_BAR0_REG_BAR0_START_K2_E5_SHIFT                                                         4
+#define PCIEIP_REG_BAR_1_BB                                                                                  0x000010UL //Access:RW   DataWidth:0x20   // The 32-bit BAR_1 register programs the base address for the memory space mapped by the card onto the PCI bus. This register can be combined with BAR_2 to make a 64-bit address for supporting Dual Address cycles systems. Path = i_cfg_func.i_cfg_public.i_cfg_dec
+  #define PCIEIP_REG_BAR_1_MEM_SPACE_BB                                                                      (0x1<<0) // This bit indicates that BAR_1 maps a memory space and is always read as 0. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_BAR_1_MEM_SPACE_BB_SHIFT                                                                0
+  #define PCIEIP_REG_BAR_1_SPACE_TYPE_BB                                                                     (0x3<<1) // These bits indicate that BAR_1 may be programmed to map this adapter to anywhere in the 64-bit address space. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_BAR_1_SPACE_TYPE_BB_SHIFT                                                               1
+  #define PCIEIP_REG_BAR_1_PREFETCH_BB                                                                       (0x1<<3) // This bit indicates that the area mapped by BAR_1 may be pre-fetched or cached by the system without side effects. Bit can be programmed from shadow register. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_BAR_1_PREFETCH_BB_SHIFT                                                                 3
+  #define PCIEIP_REG_BAR_1_ADDRESS_BB                                                                        (0xfffffff<<4) // These bits set the address within a 32-bit address space that will be card will respond in. These bits may be combined with the bits in BAR_2 to create a full 64 bit address decode. Only the bits that address blocks bigger than the setting in the BAR1_SIZE value are RW. All lower bits are RO with a value of zero. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_BAR_1_ADDRESS_BB_SHIFT                                                                  4
+#define PCIEIP_REG_BAR1_REG_K2_E5                                                                            0x000014UL //Access:RW   DataWidth:0x20   // BAR1 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_REG_BAR1_REG_BAR1_MEM_IO_K2_E5                                                              (0x1<<0) // BAR1 Memory Space Indicator.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
+  #define PCIEIP_REG_BAR1_REG_BAR1_MEM_IO_K2_E5_SHIFT                                                        0
+  #define PCIEIP_REG_BAR1_REG_BAR1_TYPE_K2_E5                                                                (0x3<<1) // BAR1 32-bit or 64-bit.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
+  #define PCIEIP_REG_BAR1_REG_BAR1_TYPE_K2_E5_SHIFT                                                          1
+  #define PCIEIP_REG_BAR1_REG_BAR1_PREFETCH_K2_E5                                                            (0x1<<3) // BAR1 Prefetchable.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
+  #define PCIEIP_REG_BAR1_REG_BAR1_PREFETCH_K2_E5_SHIFT                                                      3
+  #define PCIEIP_REG_BAR1_REG_BAR1_START_K2_E5                                                               (0xfffffff<<4) // BAR1 Base Address.   Note: The access attributes of this field are as follows:  - Dbi: R/W if enabled else R
+  #define PCIEIP_REG_BAR1_REG_BAR1_START_K2_E5_SHIFT                                                         4
+#define PCIEIP_REG_BAR_2_BB                                                                                  0x000014UL //Access:RW   DataWidth:0x20   // The 32-bit BAR_2 register programs the upper half of the base address for the memory space mapped by the card onto the PCI bus. Path = i_cfg_func.i_cfg_public.i_cfg_dec
+#define PCIEIP_REG_BAR2_REG_K2_E5                                                                            0x000018UL //Access:RW   DataWidth:0x20   // BAR2 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_REG_BAR2_REG_BAR2_MEM_IO_K2_E5                                                              (0x1<<0) // BAR2 Memory Space Indicator.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
+  #define PCIEIP_REG_BAR2_REG_BAR2_MEM_IO_K2_E5_SHIFT                                                        0
+  #define PCIEIP_REG_BAR2_REG_BAR2_TYPE_K2_E5                                                                (0x3<<1) // BAR2 32-bit or 64-bit.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
+  #define PCIEIP_REG_BAR2_REG_BAR2_TYPE_K2_E5_SHIFT                                                          1
+  #define PCIEIP_REG_BAR2_REG_BAR2_PREFETCH_K2_E5                                                            (0x1<<3) // BAR2 Prefetchable.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
+  #define PCIEIP_REG_BAR2_REG_BAR2_PREFETCH_K2_E5_SHIFT                                                      3
+  #define PCIEIP_REG_BAR2_REG_BAR2_START_K2_E5                                                               (0xfffffff<<4) // BAR2 Base Address.   Note: The access attributes of this field are as follows:  - Dbi: R/W if enabled else R
+  #define PCIEIP_REG_BAR2_REG_BAR2_START_K2_E5_SHIFT                                                         4
+#define PCIEIP_REG_BAR_3_BB                                                                                  0x000018UL //Access:RW   DataWidth:0x20   // The 32-bit BAR_3 register programs the 2nd base address for the memory space mapped by the card onto the PCI bus. This register can be combined with BAR_4 to make a 64-bit address for supporting Dual Address cycles systems.
+  #define PCIEIP_REG_BAR_3_MEM_SPACE_BB                                                                      (0x1<<0) // This bit indicates that BAR_2 maps a memory space and is always read as 0. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_BAR_3_MEM_SPACE_BB_SHIFT                                                                0
+  #define PCIEIP_REG_BAR_3_SPACE_TYPE_BB                                                                     (0x3<<1) // These bits indicate that BAR_2 may be programmed to map this adapter to anywhere in the 64-bit address space. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_BAR_3_SPACE_TYPE_BB_SHIFT                                                               1
+  #define PCIEIP_REG_BAR_3_PREFETCH_BB                                                                       (0x1<<3) // This bit indicates that the area mapped by BAR_2 may be pre-fetched or cached by the system without side effects. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_BAR_3_PREFETCH_BB_SHIFT                                                                 3
+  #define PCIEIP_REG_BAR_3_ADDRESS_BB                                                                        (0xfffffff<<4) // These bits set the address within a 32-bit address space that will be card will respond in. These bits may be combined with the bits in BAR_4 to create a full 64 bit address decode. Only the bits that address blocks bigger than the setting in the BAR2_SIZE value are RW. All lower bits are RO with a value of zero. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_BAR_3_ADDRESS_BB_SHIFT                                                                  4
+#define PCIEIP_REG_BAR3_REG_K2_E5                                                                            0x00001cUL //Access:RW   DataWidth:0x20   // BAR3 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_REG_BAR3_REG_BAR3_MEM_IO_K2_E5                                                              (0x1<<0) // BAR3 Memory Space Indicator.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
+  #define PCIEIP_REG_BAR3_REG_BAR3_MEM_IO_K2_E5_SHIFT                                                        0
+  #define PCIEIP_REG_BAR3_REG_BAR3_TYPE_K2_E5                                                                (0x3<<1) // BAR3 32-bit or 64-bit.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
+  #define PCIEIP_REG_BAR3_REG_BAR3_TYPE_K2_E5_SHIFT                                                          1
+  #define PCIEIP_REG_BAR3_REG_BAR3_PREFETCH_K2_E5                                                            (0x1<<3) // BAR3 Prefetchable.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
+  #define PCIEIP_REG_BAR3_REG_BAR3_PREFETCH_K2_E5_SHIFT                                                      3
+  #define PCIEIP_REG_BAR3_REG_BAR3_START_K2_E5                                                               (0xfffffff<<4) // BAR3 Base Address.   Note: The access attributes of this field are as follows:  - Dbi: R/W if enabled else R
+  #define PCIEIP_REG_BAR3_REG_BAR3_START_K2_E5_SHIFT                                                         4
+#define PCIEIP_REG_BAR_4_BB                                                                                  0x00001cUL //Access:RW   DataWidth:0x20   // The 32-bit BAR_4 register programs the upper half of the 2nd base address for the memory space mapped by the card onto the PCI bus. Path = i_cfg_func.i_cfg_public.i_cfg_dec
+#define PCIEIP_REG_BAR4_REG_K2_E5                                                                            0x000020UL //Access:RW   DataWidth:0x20   // BAR4 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_REG_BAR4_REG_BAR4_MEM_IO_K2_E5                                                              (0x1<<0) // BAR4 Memory Space Indicator.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
+  #define PCIEIP_REG_BAR4_REG_BAR4_MEM_IO_K2_E5_SHIFT                                                        0
+  #define PCIEIP_REG_BAR4_REG_BAR4_TYPE_K2_E5                                                                (0x3<<1) // BAR4 32-bit or 64-bit.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
+  #define PCIEIP_REG_BAR4_REG_BAR4_TYPE_K2_E5_SHIFT                                                          1
+  #define PCIEIP_REG_BAR4_REG_BAR4_PREFETCH_K2_E5                                                            (0x1<<3) // BAR4 Prefetchable.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
+  #define PCIEIP_REG_BAR4_REG_BAR4_PREFETCH_K2_E5_SHIFT                                                      3
+  #define PCIEIP_REG_BAR4_REG_BAR4_START_K2_E5                                                               (0xfffffff<<4) // BAR4 Base Address.   Note: The access attributes of this field are as follows:  - Dbi: R/W if enabled else R
+  #define PCIEIP_REG_BAR4_REG_BAR4_START_K2_E5_SHIFT                                                         4
+#define PCIEIP_REG_BAR_5_BB                                                                                  0x000020UL //Access:RW   DataWidth:0x20   // The 32-bit BAR_5 register programs the 3rd base address for the memory space mapped by the card onto the PCI bus. This register can be combined with BAR_4 to make a 64-bit address for supporting Dual Address cycles systems. Path = i_cfg_func.i_cfg_public.i_cfg_dec
+  #define PCIEIP_REG_BAR_5_MEM_SPACE_BB                                                                      (0x1<<0) // This bit indicates that BAR_3 maps a memory space and is always read as 0. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_BAR_5_MEM_SPACE_BB_SHIFT                                                                0
+  #define PCIEIP_REG_BAR_5_SPACE_TYPE_BB                                                                     (0x3<<1) // These bits indicate that BAR_3 may be programmed to map this adapter to anywhere in the 64-bit address space. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_BAR_5_SPACE_TYPE_BB_SHIFT                                                               1
+  #define PCIEIP_REG_BAR_5_PREFETCH_BB                                                                       (0x1<<3) // This bit indicates that the area mapped by BAR_3 may be pre-fetched or cached by the system without side effects. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_BAR_5_PREFETCH_BB_SHIFT                                                                 3
+  #define PCIEIP_REG_BAR_5_ADDRESS_BB                                                                        (0xfffffff<<4) // These bits set the address within a 32-bit address space that will be card will respond in. These bits may be combined with the bits in BAR_6 to create a full 64 bit address decode. Only the bits that address blocks bigger than the setting in the BAR3_SIZE value are RW. All lower bits are RO with a value of zero. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_BAR_5_ADDRESS_BB_SHIFT                                                                  4
+#define PCIEIP_REG_BAR5_REG_K2_E5                                                                            0x000024UL //Access:RW   DataWidth:0x20   // BAR5 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_REG_BAR5_REG_BAR5_MEM_IO_K2_E5                                                              (0x1<<0) // BAR5 Memory Space Indicator.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
+  #define PCIEIP_REG_BAR5_REG_BAR5_MEM_IO_K2_E5_SHIFT                                                        0
+  #define PCIEIP_REG_BAR5_REG_BAR5_TYPE_K2_E5                                                                (0x3<<1) // BAR5 32-bit or 64-bit.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
+  #define PCIEIP_REG_BAR5_REG_BAR5_TYPE_K2_E5_SHIFT                                                          1
+  #define PCIEIP_REG_BAR5_REG_BAR5_PREFETCH_K2_E5                                                            (0x1<<3) // BAR5 Prefetchable.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
+  #define PCIEIP_REG_BAR5_REG_BAR5_PREFETCH_K2_E5_SHIFT                                                      3
+  #define PCIEIP_REG_BAR5_REG_BAR5_START_K2_E5                                                               (0xfffffff<<4) // BAR5 Base Address.   Note: The access attributes of this field are as follows:  - Dbi: R/W if enabled else R
+  #define PCIEIP_REG_BAR5_REG_BAR5_START_K2_E5_SHIFT                                                         4
+#define PCIEIP_REG_BAR_6_BB                                                                                  0x000024UL //Access:RW   DataWidth:0x20   // The 32-bit BAR_4 register programs the upper half of the 3nd base address for the memory space mapped by the card onto the PCI bus.
+#define PCIEIP_REG_CARDBUS_CIS_PTR_REG_K2_E5                                                                 0x000028UL //Access:RW   DataWidth:0x20   // CardBus CIS Pointer Register.
+#define PCIEIP_REG_CARDBUS_CIS_BB                                                                            0x000028UL //Access:R    DataWidth:0x20   // This register is not supported. Path = i_cfg_func.i_cfg_public.i_cfg_rd_mux
+#define PCIEIP_REG_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_K2_E5                                                0x00002cUL //Access:RW   DataWidth:0x20   // Subsystem ID and Subsystem Vendor ID Register.
+  #define PCIEIP_REG_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_K2_E5                             (0xffff<<0) // Subsystem Vendor ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_K2_E5_SHIFT                       0
+  #define PCIEIP_REG_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_K2_E5                                (0xffff<<16) // Subsystem Device ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_K2_E5_SHIFT                          16
+#define PCIEIP_REG_SUBSYSTEM_ID_VENDOR_ID_BB                                                                 0x00002cUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_SUBSYSTEM_ID_VENDOR_ID_SUBSYSTEM_VENDOR_ID_BB                                           (0xffff<<0) // The 16-bit Subsystem Vendor ID register is used by the adapter manufacturer for identification. This value can be written by firmware through the PCI register space SUBSYSTEM_VENDOR_ID value to modify the read value to the host. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_SUBSYSTEM_ID_VENDOR_ID_SUBSYSTEM_VENDOR_ID_BB_SHIFT                                     0
+  #define PCIEIP_REG_SUBSYSTEM_ID_VENDOR_ID_SUBSYSTEM_ID_BB                                                  (0xffff<<16) // The 16-bit Subsystem ID register is used by the adapter manufacturer for identification. This value can be written by firmware through the PCI register space SUBSYSTEM_ID value to modify the read value to the host. Default values are the same as the DEVICE_ID register. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_SUBSYSTEM_ID_VENDOR_ID_SUBSYSTEM_ID_BB_SHIFT                                            16
+#define PCIEIP_REG_EXP_ROM_BASE_ADDR_REG_K2_E5                                                               0x000030UL //Access:RW   DataWidth:0x20   // Expansion ROM BAR and Mask Register.  The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_REG_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_K2_E5                                              (0x1<<0) // Expansion ROM Enable.   Note: The access attributes of this field are as follows:  - Dbi: R
+  #define PCIEIP_REG_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_K2_E5_SHIFT                                        0
+  #define PCIEIP_REG_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_K2_E5                                        (0x1fffff<<11) // Expansion ROM Base Address.   Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_K2_E5_SHIFT                                  11
+#define PCIEIP_REG_EXP_ROM_BAR_BB                                                                            0x000030UL //Access:RW   DataWidth:0x20   // The 32-bit Expansion ROM BAR register programs the base address for the memory space mapped by the chip for use as the expansion ROM. For more information on the operation of Expansion ROM, see the Theory of Ops specification. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_EXP_ROM_BAR_BAR_ENA_BB                                                                  (0x1<<0) // This bit indicates that the Expansion ROM BAR is valid when set to one. If it is zero, the expansion BAR should not be programmed or used. This bit will only be RW if it is enabled by the EXP_ROM_ENA bit which defaults to 0. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_EXP_ROM_BAR_BAR_ENA_BB_SHIFT                                                            0
+  #define PCIEIP_REG_EXP_ROM_BAR_LOW_BB                                                                      (0x3ff<<1) // These bits indicate that the Expansion ROM area is at least 2k bytes. They always read as zero. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_EXP_ROM_BAR_LOW_BB_SHIFT                                                                1
+  #define PCIEIP_REG_EXP_ROM_BAR_SIZE_BB                                                                     (0x1fff<<11) // These bits indicate the size of the Expansion ROM area or the address of it. The boundary form RO bits to RW bits is controlled by the EXP_ROM_SIZE bits. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_EXP_ROM_BAR_SIZE_BB_SHIFT                                                               11
+  #define PCIEIP_REG_EXP_ROM_BAR_ADDRESS_BB                                                                  (0xff<<24) // These bits indicate the address of the Expansion ROM area.
+  #define PCIEIP_REG_EXP_ROM_BAR_ADDRESS_BB_SHIFT                                                            24
+#define PCIEIP_REG_PCI_CAP_PTR_REG_K2_E5                                                                     0x000034UL //Access:RW   DataWidth:0x20   // Capability Pointer Register.
+  #define PCIEIP_REG_PCI_CAP_PTR_REG_CAP_POINTER_K2_E5                                                       (0xff<<0) // Pointer to first item in the PCI Capability Structure.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_PCI_CAP_PTR_REG_CAP_POINTER_K2_E5_SHIFT                                                 0
+#define PCIEIP_REG_CAP_POINTER_BB                                                                            0x000034UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_CAP_POINTER_CAP_POINTER_BB                                                              (0xff<<0) // The 8-bit Capabilities Pointer register specifies an offset in the PCI address space of a linked list of new capabilities. The capabilities are PCI-X, PCI Power Management, Vital Product Data (VPD), and Message Signaled Interrupts (MSI) is supported. The read-only value of this register is controlled by the CAP_ENA register in the PCI register space. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_CAP_POINTER_CAP_POINTER_BB_SHIFT                                                        0
+#define PCIEIP_REG_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_K2_E5                              0x00003cUL //Access:RW   DataWidth:0x20   // Interrupt Line and Pin Register.
+  #define PCIEIP_REG_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_K2_E5                   (0xff<<0) // PCI Compatible Interrupt Line Routing Register Field.
+  #define PCIEIP_REG_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_K2_E5_SHIFT             0
+  #define PCIEIP_REG_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_K2_E5                    (0xff<<8) // PCI Compatible Interrupt Pin Register Field.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_K2_E5_SHIFT              8
+#define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_BB                                                         0x00003cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_INT_LINE_BB                                              (0xff<<0) // The 8-bit Interrupt Line register is used to communicate interrupt line routing information. This field is set by the host and later used by any driver which needs to know which physical interrupt on the system interrupt controller is assigned to this device. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_INT_LINE_BB_SHIFT                                        0
+  #define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_INT_PIN_BB                                               (0xff<<8) // The 8-bit Interrupt Pin register is used to indicate which interrupt pin the device uses. Path = i_cfg_multi
+  #define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_INT_PIN_BB_SHIFT                                         8
+  #define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_MIN_GRANT_BB                                             (0xff<<16) // Hardwired to zero Path = i_cfg_func.i_cfg_public.i_cfg_rd_mux
+  #define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_MIN_GRANT_BB_SHIFT                                       16
+  #define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_MAXIMUM_LATENCY_BB                                       (0xff<<24) // Hardwired to zero Path = i_cfg_func.i_cfg_public.i_cfg_rd_mux
+  #define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_MAXIMUM_LATENCY_BB_SHIFT                                 24
+#define PCIEIP_REG_CAP_ID_NXT_PTR_REG_K2_E5                                                                  0x000040UL //Access:RW   DataWidth:0x20   // Power Management Capabilities Register.
+  #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PM_CAP_ID_K2_E5                                                      (0xff<<0) // Power Management Capability ID.
+  #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PM_CAP_ID_K2_E5_SHIFT                                                0
+  #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_K2_E5                                                (0xff<<8) // Next Capability Pointer.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_K2_E5_SHIFT                                          8
+  #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_K2_E5                                                    (0x7<<16) // Power Management Spec Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_K2_E5_SHIFT                                              16
+  #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_CLK_K2_E5                                                        (0x1<<19) // PCI Clock Requirement.
+  #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_CLK_K2_E5_SHIFT                                                  19
+  #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_IMM_READI_RETURN_DO_K2_E5                                        (0x1<<20) // Immediate Readiness on Return to D0.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_IMM_READI_RETURN_DO_K2_E5_SHIFT                                  20
+  #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_DSI_K2_E5                                                            (0x1<<21) // Device Specific Initialization Bit.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_DSI_K2_E5_SHIFT                                                      21
+  #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_AUX_CURR_K2_E5                                                       (0x7<<22) // Auxiliary Current Requirements.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_AUX_CURR_K2_E5_SHIFT                                                 22
+  #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_D1_SUPPORT_K2_E5                                                     (0x1<<25) // D1 State Support.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_D1_SUPPORT_K2_E5_SHIFT                                               25
+  #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_D2_SUPPORT_K2_E5                                                     (0x1<<26) // D2 State Support.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_D2_SUPPORT_K2_E5_SHIFT                                               26
+  #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_SUPPORT_K2_E5                                                    (0x1f<<27) // Power Management Event Support.   The read value from this field is the write value && {sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1}, where D1_SUPPORT and D2_SUPPORT are fields in this register.  The reset value PME_SUPPORT_n && {sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1}, where PME_SUPPORT_n is a configuration parameter.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_SUPPORT_K2_E5_SHIFT                                              27
+#define PCIEIP_REG_CON_STATUS_REG_K2_E5                                                                      0x000044UL //Access:RW   DataWidth:0x20   // Power Management Control and Status Register.
+  #define PCIEIP_REG_CON_STATUS_REG_POWER_STATE_K2_E5                                                        (0x3<<0) // Power State.   You can write to this register. However, the read-back value is the actual power state, not the write value.  Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_CON_STATUS_REG_POWER_STATE_K2_E5_SHIFT                                                  0
+  #define PCIEIP_REG_CON_STATUS_REG_NO_SOFT_RST_K2_E5                                                        (0x1<<3) // No soft Reset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_CON_STATUS_REG_NO_SOFT_RST_K2_E5_SHIFT                                                  3
+  #define PCIEIP_REG_CON_STATUS_REG_PME_ENABLE_K2_E5                                                         (0x1<<8) // PME Enable.   The PMC registers this value under aux power. Sometimes it might remember the old value, even if you try to clear it by writing '0'.  Note: This register field is sticky.
+  #define PCIEIP_REG_CON_STATUS_REG_PME_ENABLE_K2_E5_SHIFT                                                   8
+  #define PCIEIP_REG_CON_STATUS_REG_DATA_SELECT_K2_E5                                                        (0xf<<9) // Data Select.
+  #define PCIEIP_REG_CON_STATUS_REG_DATA_SELECT_K2_E5_SHIFT                                                  9
+  #define PCIEIP_REG_CON_STATUS_REG_DATA_SCALE_K2_E5                                                         (0x3<<13) // Data Scaling Factor.
+  #define PCIEIP_REG_CON_STATUS_REG_DATA_SCALE_K2_E5_SHIFT                                                   13
+  #define PCIEIP_REG_CON_STATUS_REG_PME_STATUS_K2_E5                                                         (0x1<<15) // PME Status.
+  #define PCIEIP_REG_CON_STATUS_REG_PME_STATUS_K2_E5_SHIFT                                                   15
+  #define PCIEIP_REG_CON_STATUS_REG_B2_B3_SUPPORT_K2_E5                                                      (0x1<<22) // B2B3 Support for D3hot.
+  #define PCIEIP_REG_CON_STATUS_REG_B2_B3_SUPPORT_K2_E5_SHIFT                                                22
+  #define PCIEIP_REG_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_K2_E5                                                 (0x1<<23) // Bus Power/Clock Control Enable.
+  #define PCIEIP_REG_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_K2_E5_SHIFT                                           23
+  #define PCIEIP_REG_CON_STATUS_REG_DATA_REG_ADD_INFO_K2_E5                                                  (0xff<<24) // Power Data Information Register.
+  #define PCIEIP_REG_CON_STATUS_REG_DATA_REG_ADD_INFO_K2_E5_SHIFT                                            24
+#define PCIEIP_REG_PM_CAP_BB                                                                                 0x000048UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PM_CAP_PM_CAP_ID_BB                                                                     (0xff<<0) // The 8-bit Power Management Capability ID is set to 1 to indicate that the next 8 bytes are a Power Management capability block. Hardwired to 1. Path = cfg_defs
+  #define PCIEIP_REG_PM_CAP_PM_CAP_ID_BB_SHIFT                                                               0
+  #define PCIEIP_REG_PM_CAP_PM_NEXT_CAP_PTR_BB                                                               (0xff<<8) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability. The read-only value of this register is controlled by the CAP_ENA register in the PCI register space. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_PM_CAP_PM_NEXT_CAP_PTR_BB_SHIFT                                                         8
+  #define PCIEIP_REG_PM_CAP_VERSION_BB                                                                       (0x3<<16) // These bits indicate that this device complies with revision 1.2 of the PCI Power Management Interface Specification. Bit is programmable through register space. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_PM_CAP_VERSION_BB_SHIFT                                                                 16
+  #define PCIEIP_REG_PM_CAP_UNUSED0_BB                                                                       (0x1<<18) // 
+  #define PCIEIP_REG_PM_CAP_UNUSED0_BB_SHIFT                                                                 18
+  #define PCIEIP_REG_PM_CAP_CLOCK_BB                                                                         (0x1<<19) // This bit indicates that the device relies on the presence of the PCI clock for PME# operation. This chip does not require the PCI clock to generate PME#, therefore this bit is hardwired to '0'. Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
+  #define PCIEIP_REG_PM_CAP_CLOCK_BB_SHIFT                                                                   19
+  #define PCIEIP_REG_PM_CAP_RESERVED_BB                                                                      (0x1<<20) // Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
+  #define PCIEIP_REG_PM_CAP_RESERVED_BB_SHIFT                                                                20
+  #define PCIEIP_REG_PM_CAP_DSI_BB                                                                           (0x1<<21) // This bit indicates that the device requires a specific initialization (DSI) sequence following a transition to the D0 un-initialized state. This device does not need this support, so the bit is hardwired to '0'. Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
+  #define PCIEIP_REG_PM_CAP_DSI_BB_SHIFT                                                                     21
+  #define PCIEIP_REG_PM_CAP_AUX_CURRENT_BB                                                                   (0x7<<22) // These bits report the 3.3Vaux auxiliary current requirements for the device. This chip uses the Data Register feature for this so this field is hardwired to '0'. Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
+  #define PCIEIP_REG_PM_CAP_AUX_CURRENT_BB_SHIFT                                                             22
+  #define PCIEIP_REG_PM_CAP_D1_SUPPORT_BB                                                                    (0x1<<25) // This bit indicates whether the device supports the D1 power management state. This bit is controlled by the D1_SUPPORT bit in the PCI register space. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_PM_CAP_D1_SUPPORT_BB_SHIFT                                                              25
+  #define PCIEIP_REG_PM_CAP_D2_SUPPORT_BB                                                                    (0x1<<26) // This bit indicates whether the device supports the D2 power management state. This bit is controlled by the D2_SUPPORT bit in the PCI register space. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_PM_CAP_D2_SUPPORT_BB_SHIFT                                                              26
+  #define PCIEIP_REG_PM_CAP_PME_IN_D0_BB                                                                     (0x1<<27) // This bit indicates whether the device supports transmiting PME message from the D0 power state. This bit is controlled by the PME_IN_D0 bit in the PCI register space. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_PM_CAP_PME_IN_D0_BB_SHIFT                                                               27
+  #define PCIEIP_REG_PM_CAP_PME_IN_D1_BB                                                                     (0x1<<28) // This bit indicates whether the device supports transmiting PME message from the D1 power state. This bit is controlled by the PME_IN_D1 bit in the PCI register space. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_PM_CAP_PME_IN_D1_BB_SHIFT                                                               28
+  #define PCIEIP_REG_PM_CAP_PME_IN_D2_BB                                                                     (0x1<<29) // This bit indicates whether the device supports transmiting PME message from the D2 power state. This bit is controlled by the PME_IN_D2 bit in the PCI register space. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_PM_CAP_PME_IN_D2_BB_SHIFT                                                               29
+  #define PCIEIP_REG_PM_CAP_PME_IN_D3_HOT_BB                                                                 (0x1<<30) // This bit indicates whether the device supports transmiting PME message from the D3hot power state. This bit is controlled by the PME_IN_D3_HOT bit in the PCI register space. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_PM_CAP_PME_IN_D3_HOT_BB_SHIFT                                                           30
+  #define PCIEIP_REG_PM_CAP_PME_IN_D3_COLD_BB                                                                (0x1<<31) // This bit indicates whether the device supports transmiting PME message from the D3cold power state. This is supported if the VAUX_PRESENT input pin is high. This bit reflects the input value of the VAUX_PRESENT input pin. Path = input pins to pcie_vaux
+  #define PCIEIP_REG_PM_CAP_PME_IN_D3_COLD_BB_SHIFT                                                          31
+#define PCIEIP_REG_PM_CSR_BB                                                                                 0x00004cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PM_CSR_STATE_BB                                                                         (0x3<<0) // These bits may be used by the system to set the power state. The register is implemented as two banks of two bits each. Can be written from both configuration space and from the PCI register space as the PM_STATE bits. When written from the PCI bus, only values of 0 and 3 will be accepted. This is the register returned on reads of this register from configuration space. The second bank catches all writes values. The value of the second register is returned when the PM_STATE bits are read from register space. The idea of these registers is to a) Provide compatible operation to 5701 b) Allow implementation of other power states though firmware. Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
+  #define PCIEIP_REG_PM_CSR_STATE_BB_SHIFT                                                                   0
+  #define PCIEIP_REG_PM_CSR_RESERVED0_BB                                                                     (0x1<<2) // Reserved Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
+  #define PCIEIP_REG_PM_CSR_RESERVED0_BB_SHIFT                                                               2
+  #define PCIEIP_REG_PM_CSR_NO_SOFT_RESET_BB                                                                 (0x1<<3) // When device transitions from D3 to D0, device does not perform an internal reset. This bit can be programmed through reg space Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_PM_CSR_NO_SOFT_RESET_BB_SHIFT                                                           3
+  #define PCIEIP_REG_PM_CSR_RESERVED1_BB                                                                     (0xf<<4) // Reserved Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
+  #define PCIEIP_REG_PM_CSR_RESERVED1_BB_SHIFT                                                               4
+  #define PCIEIP_REG_PM_CSR_PME_ENABLE_BB                                                                    (0x1<<8) // This bit enables the device to transmit PME messages. On HARD reset, this bit resets to '1'. this bit is sticky and is not modified by PERST_B. Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
+  #define PCIEIP_REG_PM_CSR_PME_ENABLE_BB_SHIFT                                                              8
+  #define PCIEIP_REG_PM_CSR_DATA_SEL_BB                                                                      (0xf<<9) // These bits select which data is to be reported through the pm_data register. (Offset 0x4f) Select values other than those listed cause the pm_data register to return zero. Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
+  #define PCIEIP_REG_PM_CSR_DATA_SEL_BB_SHIFT                                                                9
+  #define PCIEIP_REG_PM_CSR_DATA_SCALE_BB                                                                    (0x3<<13) // These bits indicate the scaling factor to be used when interpreting the values in the PM data register. The hardware default value for this field is 0x1, but this value can be written by firmware through the PCI register space (SCALE_PRG) to modify the read value to the host. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_PM_CSR_DATA_SCALE_BB_SHIFT                                                              13
+  #define PCIEIP_REG_PM_CSR_PME_STATUS_BB                                                                    (0x1<<15) // This bit is set when a PME is asserted from the MAC or RX Parser blocks, regardless of the state of the PME_ENABLE bit. If both this bit and the PME_ENABLE bit are high, then the PME output will be asserted low. This bit is cleared by writing a 1 in this bit position. At power-up, the chip must clear this bit, but on assertions of PCI_RST# after that, this bit is sticky and not modified. Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
+  #define PCIEIP_REG_PM_CSR_PME_STATUS_BB_SHIFT                                                              15
+  #define PCIEIP_REG_PM_CSR_PM_CSR_BSE_BB                                                                    (0xff<<16) // This register (PMCSR PCI to PCI Bridge Support Extensions) is not supported and always reads as zero. Path = i_cfg_func.i_cfg_public.i_cfg_rd_mux
+  #define PCIEIP_REG_PM_CSR_PM_CSR_BSE_BB_SHIFT                                                              16
+  #define PCIEIP_REG_PM_CSR_PM_DATA_BB                                                                       (0xff<<24) // The value for this register is selected from one of eight values by the DATA_SEL bits of the PM_CSR register. The reset value of all 9 of the register values is zero. These values can be written by firmware through the PCI register space (PM_Data_0_prg to PM_Data_8_prg) to modify the read values to the host. Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap (for pm_data_select) Path = i_cfg_func.i_cfg_private (pm_data)
+  #define PCIEIP_REG_PM_CSR_PM_DATA_BB_SHIFT                                                                 24
+#define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_K2_E5                                                        0x000050UL //Access:RW   DataWidth:0x20   // MSI Capability ID, Next Pointer, Capability/Control Registers.
+  #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_K2_E5                                       (0xff<<0) // MSI Capability ID.
+  #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_K2_E5_SHIFT                                 0
+  #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_K2_E5                              (0xff<<8) // MSI Capability Next Pointer.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_K2_E5_SHIFT                        8
+  #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_K2_E5                                       (0x1<<16) // MSI Enable.
+  #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_K2_E5_SHIFT                                 16
+  #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_K2_E5                             (0x7<<17) // MSI Multiple Message Capable.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_K2_E5_SHIFT                       17
+  #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_K2_E5                              (0x7<<20) // MSI Multiple Message Enable.
+  #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_K2_E5_SHIFT                        20
+  #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_K2_E5                              (0x1<<23) // MSI 64-bit Address Capable.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_K2_E5_SHIFT                        23
+  #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_K2_E5                                      (0x1<<24) // MSI Per Vector Masking Capable.
+  #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_K2_E5_SHIFT                                24
+#define PCIEIP_REG_VPD_CAP_BB                                                                                0x000050UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_VPD_CAP_VPD_CAP_ID_BB                                                                   (0xff<<0) // The 8-bit VPD Capability ID is set to 3 to indicate that the next 8 bytes are a Vital Product Data capability block. Path = cfg_defs
+  #define PCIEIP_REG_VPD_CAP_VPD_CAP_ID_BB_SHIFT                                                             0
+  #define PCIEIP_REG_VPD_CAP_VPD_NEXT_CAP_PTR_BB                                                             (0xff<<8) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability. The read-only value of this register is controlled by the CAP_ENA register in the PCI register space. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_VPD_CAP_VPD_NEXT_CAP_PTR_BB_SHIFT                                                       8
+  #define PCIEIP_REG_VPD_CAP_UNUSED0_BB                                                                      (0x3<<16) // 
+  #define PCIEIP_REG_VPD_CAP_UNUSED0_BB_SHIFT                                                                16
+  #define PCIEIP_REG_VPD_CAP_ADDRESS_BB                                                                      (0x1fff<<18) // This value is the 32-bit word address of the VPD value being accessed in the vpd_data register. Since the data register is 32-bits wide. Path = i_cfg_func.i_cfg_public.i_cfg_vpd_cap
+  #define PCIEIP_REG_VPD_CAP_ADDRESS_BB_SHIFT                                                                18
+  #define PCIEIP_REG_VPD_CAP_FLAG_BB                                                                         (0x1<<31) // This bit is used to control passing of data between the vpd_data register and Non-Volatile memory. To read a value, this bit is written as zero when the address is written. When the data is available to read, this bit will read as a one. To write data, this bit must written as a one when the address is written. When the bit reads as a zero the write has completed. Path = i_cfg_func.i_cfg_public.i_cfg_vpd_cap
+  #define PCIEIP_REG_VPD_CAP_FLAG_BB_SHIFT                                                                   31
+#define PCIEIP_REG_MSI_CAP_OFF_04H_REG_K2_E5                                                                 0x000054UL //Access:RW   DataWidth:0x20   // MSI Message Lower Address Register.
+  #define PCIEIP_REG_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_K2_E5                                           (0x3fffffff<<2) // MSI Message Lower Address Field.   Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_K2_E5_SHIFT                                     2
+#define PCIEIP_REG_VPD_DATA_BB                                                                               0x000054UL //Access:RW   DataWidth:0x20   // This is the VPD data transfer register. See the instructions for the FLAG bit above for usage of this register. Path = i_cfg_func.i_cfg_public.i_cfg_vpd_cap
+#define PCIEIP_REG_MSI_CAP_OFF_08H_REG_K2_E5                                                                 0x000058UL //Access:RW   DataWidth:0x20   // For a 32 bit MSI Message, this register contains Data. For 64 bit it contains the Upper Address.
+  #define PCIEIP_REG_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_K2_E5                                           (0xffff<<0) // For a 32-bit MSI Message, this field contains Data. For 64-bit it contains lower 16 bits of the Upper Address.   Note: The access attributes of this field are as follows:  - Dbi: PCI_MSI_64_BIT_ADDR_CAP ? R/W : R
+  #define PCIEIP_REG_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_K2_E5_SHIFT                                     0
+  #define PCIEIP_REG_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_K2_E5                                           (0xffff<<16) // For a 32 bit MSI Message, this is reserved. For 64-bit it contains upper 16 bits of the Upper Address.  Note: The access attributes of this field are as follows:  - Dbi: PCI_MSI_64_BIT_ADDR_CAP ? R/W : R
+  #define PCIEIP_REG_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_K2_E5_SHIFT                                     16
+#define PCIEIP_REG_MSI_CAP_BB                                                                                0x000058UL //Access:RW   DataWidth:0x20   // The device driver is prohibited from writing to this register.
+  #define PCIEIP_REG_MSI_CAP_MSI_CAP_ID_BB                                                                   (0xff<<0) // The 8-bit MSI Capability ID is set to 5 to indicate that the next 8 bytes are a Message Signaled Interrupt capability block. Path = cfg_defs
+  #define PCIEIP_REG_MSI_CAP_MSI_CAP_ID_BB_SHIFT                                                             0
+  #define PCIEIP_REG_MSI_CAP_MSI_NEXT_CAP_PTR_BB                                                             (0xff<<8) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability. The read-only value of this register is controlled by the CAP_ENA register in the PCI register space. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_MSI_CAP_MSI_NEXT_CAP_PTR_BB_SHIFT                                                       8
+  #define PCIEIP_REG_MSI_CAP_MSI_ENABLE_BB                                                                   (0x1<<16) // When this bit is set, the chip will generate MSI cycles to indicate interrupts instead of asserting the INTA# pin. When this bit is zero, the INTA# pin will be used. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap
+  #define PCIEIP_REG_MSI_CAP_MSI_ENABLE_BB_SHIFT                                                             16
+  #define PCIEIP_REG_MSI_CAP_MULTI_MSG_CAP_BB                                                                (0x7<<17) // These bits indicate the number of messages that the chip is capable of generating. This value comes from the Path = i_cfg_func.i_cfg_private MULTI_MSG_CAP bit in the register space.
+  #define PCIEIP_REG_MSI_CAP_MULTI_MSG_CAP_BB_SHIFT                                                          17
+  #define PCIEIP_REG_MSI_CAP_MULTI_MSG_EN_BB                                                                 (0x7<<20) // These bits indicate the number of message that the chip is configured (allowed) to generate. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap
+  #define PCIEIP_REG_MSI_CAP_MULTI_MSG_EN_BB_SHIFT                                                           20
+  #define PCIEIP_REG_MSI_CAP_CAP_64BIT_BB                                                                    (0x1<<23) // This bit indicates that the chip is capable of generating 64 bit MSI messages. Path = cfg_defs
+  #define PCIEIP_REG_MSI_CAP_CAP_64BIT_BB_SHIFT                                                              23
+  #define PCIEIP_REG_MSI_CAP_MSI_PVMASK_CAPABLE_BB                                                           (0x1<<24) // This bit indicates if the function supports per vector masking. This value comes from the MSI_PV_MASK_CAP bit in the register space. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap
+  #define PCIEIP_REG_MSI_CAP_MSI_PVMASK_CAPABLE_BB_SHIFT                                                     24
+#define PCIEIP_REG_MSI_CAP_OFF_0CH_REG_K2_E5                                                                 0x00005cUL //Access:RW   DataWidth:0x20   // For a 64 bit MSI Message, this register contains Data. For 32 bit, it contains Mask Bits if PVM enabled.
+  #define PCIEIP_REG_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_K2_E5                                           (0xffff<<0) // For a 64-bit MSI Message, this field contains Data. For 32-bit, it contains the lower Mask Bits if PVM is enabled.  Note: The access attributes of this field are as follows:  - Dbi: PCI_MSI_64_BIT_ADDR_CAP || MSI_PVM_EN ? R/W : R
+  #define PCIEIP_REG_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_K2_E5_SHIFT                                     0
+  #define PCIEIP_REG_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_K2_E5                                           (0xffff<<16) // For a 64-bit MSI Message, this field contains Data. For 32-bit, it contains the upper Mask Bits if PVM is enabled.  Note: The access attributes of this field are as follows:  - Dbi: !PCI_MSI_64_BIT_ADDR_CAP && MSI_PVM_EN ? R/W : R
+  #define PCIEIP_REG_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_K2_E5_SHIFT                                     16
+#define PCIEIP_REG_MSI_ADDR_L_BB                                                                             0x00005cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_MSI_ADDR_L_UNUSED0_BB                                                                   (0x3<<0) // 
+  #define PCIEIP_REG_MSI_ADDR_L_UNUSED0_BB_SHIFT                                                             0
+  #define PCIEIP_REG_MSI_ADDR_L_VAL_BB                                                                       (0x3fffffff<<2) // This register controls the lower half of the address of the MSI message that are generated. This register is readable in the pci register space. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap
+  #define PCIEIP_REG_MSI_ADDR_L_VAL_BB_SHIFT                                                                 2
+#define PCIEIP_REG_MSI_CAP_OFF_10H_REG_K2_E5                                                                 0x000060UL //Access:RW   DataWidth:0x20   // Used for MSI when Vector Masking Capable. For 32 bit contains Pending Bits. For 64 bit, contains Mask Bits.
+#define PCIEIP_REG_MSI_ADDR_H_BB                                                                             0x000060UL //Access:RW   DataWidth:0x20   // This register controls the upper half of the address of the MSI message that are generated. This register is readable in the pci register space. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap
+#define PCIEIP_REG_MSI_CAP_OFF_14H_REG_K2_E5                                                                 0x000064UL //Access:R    DataWidth:0x20   // Used for MSI 64 bit messaging when Vector Masking Capable. Contains Pending Bits.
+#define PCIEIP_REG_MSI_DATA_BB                                                                               0x000064UL //Access:RW   DataWidth:0x20   // This register controls the data value that will be presented on the lower 16 bits of the data bus during MSI messages. The MENA value from the MSI Control register allows a specific number of the lower bits (up to 6) to be modified to indicate different interrupt conditions. This register is readable in the pci register space. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap
+  #define PCIEIP_REG_MSI_DATA_MSI_DATA_BB                                                                    (0xffff<<0) // 
+  #define PCIEIP_REG_MSI_DATA_MSI_DATA_BB_SHIFT                                                              0
+#define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_K2_E5                                          0x000070UL //Access:RW   DataWidth:0x20   // PCI Express Capabilities, ID, Next Pointer Register.
+  #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_K2_E5                            (0xff<<0) // PCIE Capability ID.
+  #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_K2_E5_SHIFT                      0
+  #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_K2_E5                      (0xff<<8) // PCIE Next Capability Pointer.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_K2_E5_SHIFT                8
+  #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_K2_E5                           (0xf<<16) // PCIE Capability Version Number.
+  #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_K2_E5_SHIFT                     16
+  #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_K2_E5                     (0xf<<20) // PCIE Device/PortType.
+  #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_K2_E5_SHIFT               20
+  #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_K2_E5                          (0x1<<24) // PCIe Slot Implemented Valid.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_K2_E5_SHIFT                    24
+  #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_K2_E5                       (0x1f<<25) // PCIE Interrupt Message Number.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_K2_E5_SHIFT                 25
+  #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_K2_E5                                   (0x1<<30) // Reserved.
+  #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_K2_E5_SHIFT                             30
+#define PCIEIP_REG_DEVICE_CAPABILITIES_REG_K2_E5                                                             0x000074UL //Access:RW   DataWidth:0x20   // Device Capabilities Register.
+  #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_K2_E5                                 (0x7<<0) // Max Payload Size Supported.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_K2_E5_SHIFT                           0
+  #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_K2_E5                             (0x3<<3) // Phantom Functions Supported.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_K2_E5_SHIFT                       3
+  #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_K2_E5                                     (0x1<<5) // Extended Tag Field Supported.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_K2_E5_SHIFT                               5
+  #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_K2_E5                             (0x7<<6) // Applies to endpoints only L0s acceptable latency.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_K2_E5_SHIFT                       6
+  #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_K2_E5                              (0x7<<9) // Applies to endpoints only L1 acceptable latency.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_K2_E5_SHIFT                        9
+  #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_K2_E5                            (0x1<<15) // Role-based Error Reporting Implemented.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_K2_E5_SHIFT                      15
+  #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_K2_E5                           (0xff<<18) // Captured Slot Power Limit Value.
+  #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_K2_E5_SHIFT                     18
+  #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_K2_E5                           (0x3<<26) // Captured Slot Power Limit Scale.
+  #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_K2_E5_SHIFT                     26
+  #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_K2_E5                                          (0x1<<28) // Function Level Reset Capability (endpoints only).   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_K2_E5_SHIFT                                    28
+#define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_K2_E5                                                        0x000078UL //Access:RW   DataWidth:0x20   // Device Control and Status Register.
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_K2_E5                          (0x1<<0) // Correctable Error Reporting Enable.
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_K2_E5_SHIFT                    0
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2_E5                     (0x1<<1) // Non-fatal Error Reporting Enable.
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2_E5_SHIFT               1
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_K2_E5                         (0x1<<2) // Fatal Error Reporting Enable.
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_K2_E5_SHIFT                   2
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_K2_E5                        (0x1<<3) // Unsupported Request Reporting Enable.
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_K2_E5_SHIFT                  3
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_K2_E5                                (0x1<<4) // Enable Relaxed Ordering.
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_K2_E5_SHIFT                          4
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_K2_E5                         (0x7<<5) // Max Payload Size. Max_Payload_Size . This field sets maximum TLP payload size for the Function. Permissible values that can be programmed are indicated by the Max_Payload_Size Supported field (PCIE_CAP_MAX_PAYLOAD_SIZE) in the Device Capabilities register (DEVICE_CAPABILITIES_REG).
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_K2_E5_SHIFT                   5
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_K2_E5                                  (0x1<<8) // Extended Tag Field Enable.   The write value is gated with the PCIE_CAP_EXT_TAG_SUPP field of DEVICE_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_EXT_TAG_SUPP ? RW : RO
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_K2_E5_SHIFT                            8
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_K2_E5                             (0x1<<9) // Phantom Functions Enable.   The write value is gated with the PCIE_CAP_PHANTOM_FUNC_SUPPORT field of DEVICE_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_PHANTOM_FUNC_SUPPORT ? RW : RO
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_K2_E5_SHIFT                       9
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_K2_E5                             (0x1<<10) // Aux Power PM Enable.   This bit is derived by sampling the sys_aux_pwr_det input.  Note: This register field is sticky.
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_K2_E5_SHIFT                       10
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_K2_E5                                 (0x1<<11) // Enable No Snoop.   Note: The access attributes of this field are as follows:  - Dbi: R
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_K2_E5_SHIFT                           11
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_K2_E5                           (0x7<<12) // Max Read Request Size.
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_K2_E5_SHIFT                     12
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_K2_E5                                (0x1<<15) // Initiate Function Level Reset (for endpoints).
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_K2_E5_SHIFT                          15
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_K2_E5                           (0x1<<16) // Correctable Error Detected Status.
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_K2_E5_SHIFT                     16
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2_E5                      (0x1<<17) // Non-Fatal Error Detected Status.
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2_E5_SHIFT                17
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_K2_E5                          (0x1<<18) // Fatal Error Detected Status.
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_K2_E5_SHIFT                    18
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_K2_E5                    (0x1<<19) // Unsupported Request Detected Status.
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_K2_E5_SHIFT              19
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_K2_E5                          (0x1<<20) // Aux Power Detected Status.   This bit is derived by sampling the sys_aux_pwr_det input.
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_K2_E5_SHIFT                    20
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_K2_E5                               (0x1<<21) // Transactions Pending Status.
+  #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_K2_E5_SHIFT                         21
+#define PCIEIP_REG_LINK_CAPABILITIES_REG_K2_E5                                                               0x00007cUL //Access:RW   DataWidth:0x20   // Link Capabilities Register.
+  #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_K2_E5                                     (0xf<<0) // Maximum Link Speed.   In M-PCIe mode, the reset and dynamic values of this field are calculated by the core.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_K2_E5_SHIFT                               0
+  #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_K2_E5                                     (0x3f<<4) // Maximum Link Width.   In M-PCIe mode, the reset and dynamic values of this field are calculated by the core.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_K2_E5_SHIFT                               4
+  #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_K2_E5                       (0x3<<10) // Level of ASPM (Active State Power Management) Support.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_K2_E5_SHIFT                 10
+  #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_K2_E5                                   (0x7<<12) // LOs Exit Latency.  There are two each of these register fields, this one and a shadow one at the same address. The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the core and which one is accessed by a read request. Common Clock operation is supported (possible) in the core when one or more of the following expressions is true:  - CX_NFTS !=CX_COMM_NFTS  - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY  - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY Common Clock operation is enabled in the core when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_K2_E5_SHIFT                             12
+  #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_K2_E5                                    (0x7<<15) // L1 Exit Latency.  There are two each of these register fields, this one and a shadow one at the same address. The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the core and which one is accessed by a read request. Common Clock operation is supported (possible) in the core when one or more of the following expressions is true:  - CX_NFTS !=CX_COMM_NFTS  - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY  - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY Common Clock operation is enabled in the core when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_K2_E5_SHIFT                              15
+  #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_K2_E5                                    (0x1<<18) // Clock Power Management.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_K2_E5_SHIFT                              18
+  #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_K2_E5                          (0x1<<19) // Surprise Down Error Reporting Capable.
+  #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_K2_E5_SHIFT                    19
+  #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_K2_E5                                 (0x1<<20) // Data Link Layer Link Active Reporting Capable.
+  #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_K2_E5_SHIFT                           20
+  #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_K2_E5                                    (0x1<<21) // Link Bandwidth Notification Capable.
+  #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_K2_E5_SHIFT                              21
+  #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_K2_E5                                (0x1<<22) // ASPM Optionality Compliance.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_K2_E5_SHIFT                          22
+  #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_K2_E5                                           (0xff<<24) // Port Number.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_K2_E5_SHIFT                                     24
+#define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_K2_E5                                                        0x000080UL //Access:RW   DataWidth:0x20   // Link Control and Status Register.
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_K2_E5                (0x3<<0) // Active State Power Management (ASPM) Control.
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_K2_E5_SHIFT          0
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_K2_E5                                         (0x1<<3) // Read Completion Boundary (RCB).  Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_K2_E5_SHIFT                                   3
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_K2_E5                                (0x1<<4) // Initiate Link Disable.   In a DSP that supports crosslink, the core gates the write value with the CROSS_LINK_EN field in PORT_LINK_CTRL_OFF.  Note: The access attributes of this field are as follows:  - Dbi: CX_CROSSLINK_ENABLE=1 && PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_CROSSLINK_ENABLE=0 && dsp=1? RW : RO
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_K2_E5_SHIFT                          4
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_K2_E5                                (0x1<<5) // Initiate Link Retrain.   Note: The access attributes of this field are as follows:  - Dbi: see description
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_K2_E5_SHIFT                          5
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_K2_E5                           (0x1<<6) // Common Clock Configuration.
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_K2_E5_SHIFT                     6
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_K2_E5                              (0x1<<7) // Extended Synch.
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_K2_E5_SHIFT                        7
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_K2_E5                            (0x1<<8) // Enable Clock Power Management.   The write value is gated with the PCIE_CAP_CLOCK_POWER_MAN field in LINK_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_CLOCK_POWER_MAN ? RW : RO
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_K2_E5_SHIFT                      8
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_K2_E5                       (0x1<<9) // Hardware Autonomous Width Disable.   Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_K2_E5_SHIFT                 9
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_K2_E5                          (0x1<<10) // Link Bandwidth Management Interrupt Enable.   The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_K2_E5_SHIFT                    10
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_K2_E5                         (0x1<<11) // Link Autonomous Bandwidth Management Interrupt Enable.   The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_K2_E5_SHIFT                   11
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_K2_E5                       (0x3<<14) // DRS Signaling Control.
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_K2_E5_SHIFT                 14
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_K2_E5                                  (0xf<<16) // Current Link Speed.
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_K2_E5_SHIFT                            16
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_K2_E5                             (0x3f<<20) // Negotiated Link Width.
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_K2_E5_SHIFT                       20
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_K2_E5                               (0x1<<27) // LTSSM is in Configuration or Recovery State.   Note: The access attributes of this field are as follows:  - Dbi: R
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_K2_E5_SHIFT                         27
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_K2_E5                             (0x1<<28) // Slot Clock Configuration.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_K2_E5_SHIFT                       28
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_K2_E5                                  (0x1<<29) // Data Link Layer Active.
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_K2_E5_SHIFT                            29
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_K2_E5                          (0x1<<30) // Link Bandwidth Management Status.   The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW1C : RO
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_K2_E5_SHIFT                    30
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_K2_E5                         (0x1<<31) // Link Autonomous Bandwidth Status.   The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW1C : RO
+  #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_K2_E5_SHIFT                   31
+#define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_K2_E5                                                            0x000094UL //Access:R    DataWidth:0x20   // Device Capabilities 2 Register.
+  #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_K2_E5                               (0xf<<0) // Completion Timeout Ranges Supported.
+  #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_K2_E5_SHIFT                         0
+  #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_K2_E5                     (0x1<<4) // Completion Timeout Disable Supported.
+  #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_K2_E5_SHIFT               4
+  #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_K2_E5                             (0x1<<5) // ARI Forwarding Supported.
+  #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_K2_E5_SHIFT                       5
+  #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_K2_E5                             (0x1<<6) // Atomic Operation Routing Supported.
+  #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_K2_E5_SHIFT                       6
+  #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_K2_E5                              (0x1<<7) // 32 Bit AtomicOp Completer Supported.
+  #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_K2_E5_SHIFT                        7
+  #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_K2_E5                              (0x1<<8) // 64 Bit AtomicOp Completer Supported.
+  #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_K2_E5_SHIFT                        8
+  #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_K2_E5                                (0x1<<9) // 128 Bit CAS Completer Supported.
+  #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_K2_E5_SHIFT                          9
+  #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_K2_E5                              (0x1<<10) // No Relaxed Ordering Enabled PR-PR Passing.
+  #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_K2_E5_SHIFT                        10
+  #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_K2_E5                                        (0x1<<11) // LTR Mechanism Supported.
+  #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_K2_E5_SHIFT                                  11
+  #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_K2_E5                             (0x1<<12) // TPH Completer Supported Bit 0.
+  #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_K2_E5_SHIFT                       12
+  #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_K2_E5                             (0x1<<13) // TPH Completer Supported Bit 1.
+  #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_K2_E5_SHIFT                       13
+  #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT_K2_E5                                    (0x3<<18) // (OBFF) Optimized Buffer Flush/fill Supported.
+  #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT_K2_E5_SHIFT                              18
+#define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_K2_E5                                                  0x000098UL //Access:RW   DataWidth:0x20   // Device Control 2 and Status 2 Register.
+  #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_K2_E5                     (0xf<<0) // Completion Timeout Value.   Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_K2_E5_SHIFT               0
+  #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_K2_E5                   (0x1<<4) // Completion Timeout Disable.
+  #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_K2_E5_SHIFT             4
+  #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_K2_E5                (0x1<<5) // ARI Forwarding Enable.
+  #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_K2_E5_SHIFT          5
+  #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_REQ_EN_K2_E5                         (0x1<<6) // AtomicOp Requester Enable.
+  #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_REQ_EN_K2_E5_SHIFT                   6
+  #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_EGRESS_BLK_K2_E5                     (0x1<<7) // AtomicOp Egress Blocking.
+  #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_EGRESS_BLK_K2_E5_SHIFT               7
+  #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_REQ_EN_K2_E5                            (0x1<<8) // IDO Request Enable.
+  #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_REQ_EN_K2_E5_SHIFT                      8
+  #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_CPL_EN_K2_E5                            (0x1<<9) // IDO Completion Enable.
+  #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_CPL_EN_K2_E5_SHIFT                      9
+  #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_K2_E5                                (0x1<<10) // LTR Mechanism Enable.   The write value is gated with the PCIE_CAP_LTR_SUPP field of DEVICE_CAPABILITIES2_REG.  Note: RW for function #0 and RsdvP for all other functions
+  #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_K2_E5_SHIFT                          10
+  #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_OBFF_EN_K2_E5                               (0x3<<13) // OBFF Enable.   Note: RW for function #0 and RsdvP for all other functions
+  #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_OBFF_EN_K2_E5_SHIFT                         13
+#define PCIEIP_REG_LINK_CAPABILITIES2_REG_K2_E5                                                              0x00009cUL //Access:RW   DataWidth:0x20   // Link Capabilities 2 Register.
+  #define PCIEIP_REG_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_K2_E5                         (0x7f<<1) // Supported Link Speeds Vector.   This field has a default of (PCIE_CAP_MAX_LINK_SPEED == 0100) ? 0001111 : (PCIE_CAP_MAX_LINK_SPEED == 0011) ? 0000111 : (PCIE_CAP_MAX_LINK_SPEED == 0010) ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in the LINK_CAPABILITIES_REG register.
+  #define PCIEIP_REG_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_K2_E5_SHIFT                   1
+  #define PCIEIP_REG_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_K2_E5                                (0x1<<8) // Cross Link Supported.
+  #define PCIEIP_REG_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_K2_E5_SHIFT                          8
+  #define PCIEIP_REG_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_K2_E5                                              (0x1<<31) // DRS Supported.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_K2_E5_SHIFT                                        31
+#define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_K2_E5                                                      0x0000a0UL //Access:RW   DataWidth:0x20   // Link Control 2 and Status 2 Register.
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_K2_E5                         (0xf<<0) // Target Link Speed.    In M-PCIe mode, the contents of this field are derived from other registers.  Note: This register field is sticky.
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_K2_E5_SHIFT                   0
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_K2_E5                          (0x1<<4) // Enter Compliance Mode.   Note: This register field is sticky.
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_K2_E5_SHIFT                    4
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_K2_E5                     (0x1<<5) // Hardware Autonomous Speed Disable.   Note: The access attributes of this field are as follows:  - Dbi: R (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_K2_E5_SHIFT               5
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_K2_E5                            (0x1<<6) // Controls Selectable De-emphasis for 5 GT/s.   Note: This register field is sticky.
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_K2_E5_SHIFT                      6
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_K2_E5                                 (0x7<<7) // Controls Transmit Margin for Debug or Compliance.   Note: This register field is sticky.
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_K2_E5_SHIFT                           7
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_K2_E5                 (0x1<<10) // Enter Modified Compliance.   Note: The access attributes of this field are as follows:  - Dbi: R (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_K2_E5_SHIFT           10
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_K2_E5                            (0x1<<11) // Sets Compliance Skip Ordered Sets transmission.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_K2_E5_SHIFT                      11
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_K2_E5                         (0xf<<12) // Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_K2_E5_SHIFT                   12
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_K2_E5                           (0x1<<16) // Current De-emphasis Level.    In M-PCIe mode this register is always 0x0. In C-PCIe mode, its contents are derived by sampling the PIPE
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_K2_E5_SHIFT                     16
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_K2_E5                                    (0x1<<17) // Equalization 8.0GT/s Complete.   Note: This register field is sticky.
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_K2_E5_SHIFT                              17
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_K2_E5                                 (0x1<<18) // Equalization 8.0GT/s Phase 1 Successful.   Note: This register field is sticky.
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_K2_E5_SHIFT                           18
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_K2_E5                                 (0x1<<19) // Equalization 8.0GT/s Phase 2 Successful.   Note: This register field is sticky.
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_K2_E5_SHIFT                           19
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_K2_E5                                 (0x1<<20) // Equalization 8.0GT/s Phase 3 Successful.   Note: This register field is sticky.
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_K2_E5_SHIFT                           20
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_K2_E5                               (0x1<<21) // Link Equalization Request 8.0GT/s.
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_K2_E5_SHIFT                         21
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_K2_E5                          (0x7<<28) // Downstream Component Presence. For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_K2_E5_SHIFT                    28
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_K2_E5                               (0x1<<31) // DRS Message Received. For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.
+  #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_K2_E5_SHIFT                         31
+#define PCIEIP_REG_MSIX_CAP_BB                                                                               0x0000a0UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_MSIX_CAP_MSIX_CAP_ID_BB                                                                 (0xff<<0) // Capability ID for MSIX Path = cfg_defs
+  #define PCIEIP_REG_MSIX_CAP_MSIX_CAP_ID_BB_SHIFT                                                           0
+  #define PCIEIP_REG_MSIX_CAP_MSIX_NEXT_CAP_PTR_BB                                                           (0xff<<8) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability. The read-only value of this register is controlled by the CAP_ENA register in the PCI register space. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_MSIX_CAP_MSIX_NEXT_CAP_PTR_BB_SHIFT                                                     8
+  #define PCIEIP_REG_MSIX_CAP_TABLE_SIZE_BB                                                                  (0x7ff<<16) // System sw reads this field to determine the MSI-X table size N, which is encoded as N-1 Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_MSIX_CAP_TABLE_SIZE_BB_SHIFT                                                            16
+  #define PCIEIP_REG_MSIX_CAP_RESERVED_BB                                                                    (0x7<<27) // Reserved
+  #define PCIEIP_REG_MSIX_CAP_RESERVED_BB_SHIFT                                                              27
+  #define PCIEIP_REG_MSIX_CAP_FUNC_MASK_BB                                                                   (0x1<<30) // If 1, all of the vectors associated with the function are masked regardless of their per vector Mask bit. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap
+  #define PCIEIP_REG_MSIX_CAP_FUNC_MASK_BB_SHIFT                                                             30
+  #define PCIEIP_REG_MSIX_CAP_MSIX_ENABLE_BB                                                                 (0x1<<31) // If 1, and the MSI enable bit in the MSI message control register is 0, the function is permitted to use MSIX request service and profited from using INTx# messages. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap
+  #define PCIEIP_REG_MSIX_CAP_MSIX_ENABLE_BB_SHIFT                                                           31
+#define PCIEIP_REG_MSIX_TBL_OFF_BIR_BB                                                                       0x0000a4UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_MSIX_TBL_OFF_BIR_TABLE_BIR_BB                                                           (0x7<<0) // Indicates which one of functions BAR is used to map MSI-X table into memory space. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_MSIX_TBL_OFF_BIR_TABLE_BIR_BB_SHIFT                                                     0
+  #define PCIEIP_REG_MSIX_TBL_OFF_BIR_TABLE_OFFSET_BB                                                        (0x1fffffff<<3) // Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_MSIX_TBL_OFF_BIR_TABLE_OFFSET_BB_SHIFT                                                  3
+#define PCIEIP_REG_MSIX_PBA_BIR_OFF_BB                                                                       0x0000a8UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_MSIX_PBA_BIR_OFF_PBA_BIR_BB                                                             (0x7<<0) // Indicates which one of functions BAR is used to map MSI-X PBA into memory space. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_MSIX_PBA_BIR_OFF_PBA_BIR_BB_SHIFT                                                       0
+  #define PCIEIP_REG_MSIX_PBA_BIR_OFF_PBA_OFFSET_BB                                                          (0x1fffffff<<3) // Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_MSIX_PBA_BIR_OFF_PBA_OFFSET_BB_SHIFT                                                    3
+#define PCIEIP_REG_PCIE_CAPABILITY_BB                                                                        0x0000acUL //Access:R    DataWidth:0x20   // Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_PCIE_CAPABILITY_PCIE_CAP_ID_BB                                                          (0xff<<0) // This register contains the PCIExpress Capability ID. Path= i_cfg_func.i_cfg_public.i_cfg_rd_mux
+  #define PCIEIP_REG_PCIE_CAPABILITY_PCIE_CAP_ID_BB_SHIFT                                                    0
+  #define PCIEIP_REG_PCIE_CAPABILITY_PCIE_NEXT_CAP_PTR_BB                                                    (0xff<<8) // This registers contains the pointer to the next PCI capability structure. Path= i_cfg_func.i_cfg_public.i_cfg_rd_mux
+  #define PCIEIP_REG_PCIE_CAPABILITY_PCIE_NEXT_CAP_PTR_BB_SHIFT                                              8
+  #define PCIEIP_REG_PCIE_CAPABILITY_VER_BB                                                                  (0xf<<16) // Capability Version. PCI Express Capability structure version number. These bits are hardwired to 2h. Path= cfg_defs
+  #define PCIEIP_REG_PCIE_CAPABILITY_VER_BB_SHIFT                                                            16
+  #define PCIEIP_REG_PCIE_CAPABILITY_TYPE_BB                                                                 (0xf<<20) // Device/Port Type. Device is an End Point. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_PCIE_CAPABILITY_TYPE_BB_SHIFT                                                           20
+  #define PCIEIP_REG_PCIE_CAPABILITY_SLOT_IMPLEMENTED_BB                                                     (0x1<<24) // Slot Implemented. This register is not supported. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_PCIE_CAPABILITY_SLOT_IMPLEMENTED_BB_SHIFT                                               24
+  #define PCIEIP_REG_PCIE_CAPABILITY_MSG_NUM_BB                                                              (0x1f<<25) // Interrupt Message Number:indicate which MSI/MSI-X vector is used for the interrupt message generated in association with any of the status bits of this capability structure. For MSI, the value in this register indicates the offset between the base Message Data and the interrupt message that is generated. For MSI-X, the value in this register indicates which MSI-X Table entry is used to generate the interrupt message. The entry must be one of the first 32 entries even if the function implements more than 32 entries. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_PCIE_CAPABILITY_MSG_NUM_BB_SHIFT                                                        25
+#define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_K2_E5                                                       0x0000b0UL //Access:RW   DataWidth:0x20   // MSI-X Capability ID, Next Pointer, Control Registers.
+  #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_K2_E5                                     (0xff<<0) // MSI-X Capability ID.
+  #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_K2_E5_SHIFT                               0
+  #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_K2_E5                            (0xff<<8) // MSI-X Next Capability Pointer.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_K2_E5_SHIFT                      8
+  #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_K2_E5                                 (0x7ff<<16) // MSI-X Table Size.   SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PCI_MSIX_TABLE_SIZE field in VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG). To write this common value, you must perform a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_TABLE_SIZE field in the PF PCI_MSIX_CAP_ID_NEXT_CTRL_REG register.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_K2_E5_SHIFT                           16
+  #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_K2_E5                              (0x1<<30) // Function Mask.   Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_K2_E5_SHIFT                        30
+  #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_K2_E5                                     (0x1<<31) // MSI-X Enable.   Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_K2_E5_SHIFT                               31
+#define PCIEIP_REG_DEVICE_CAPABILITY_BB                                                                      0x0000b0UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED_BB                                              (0x7<<0) // Max Payload Size Supported. These bits are programmable from the register space and default value is based on define in version.v file. Path= i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED_BB_SHIFT                                        0
+  #define PCIEIP_REG_DEVICE_CAPABILITY_UNUSED0_BB                                                            (0x3<<3) // 
+  #define PCIEIP_REG_DEVICE_CAPABILITY_UNUSED0_BB_SHIFT                                                      3
+  #define PCIEIP_REG_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT_BB                                               (0x1<<5) // Extended Tag Field Support. This bit is programmable through register space. Path= i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT_BB_SHIFT                                         5
+  #define PCIEIP_REG_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY_BB                                             (0x7<<6) // Endpoint L0s Acceptable Latency. These bits are programmable through register space. The value should be 0 for root ports. Path= i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY_BB_SHIFT                                       6
+  #define PCIEIP_REG_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY_BB                                              (0x7<<9) // Endpoint L1 Acceptable Latency. These bits are programmable through register space. The bits should be 0 for Root ports Path= i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY_BB_SHIFT                                        9
+  #define PCIEIP_REG_DEVICE_CAPABILITY_UNUSED1_BB                                                            (0x7<<12) // 
+  #define PCIEIP_REG_DEVICE_CAPABILITY_UNUSED1_BB_SHIFT                                                      12
+  #define PCIEIP_REG_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT_BB                                                 (0x1<<15) // Indicate device is conforming to the ECN, PCI Express Base Specification, Revision 1.1., or subsequent PCI Express Base Specification revisions Path= i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT_BB_SHIFT                                           15
+  #define PCIEIP_REG_DEVICE_CAPABILITY_UNUSED2_BB                                                            (0x3<<16) // 
+  #define PCIEIP_REG_DEVICE_CAPABILITY_UNUSED2_BB_SHIFT                                                      16
+  #define PCIEIP_REG_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_VAL_BB                                              (0xff<<18) // Specifies the upper limit on power supplied by slot. It is set by the Set_Slot_Power_Limit Message. This field is not set for Root ports. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_VAL_BB_SHIFT                                        18
+  #define PCIEIP_REG_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_SCALE_BB                                            (0x3<<26) // Specifies the scale used for the Slot Power Limit Value. It is set by the Set_Slot_Power_Limit Message. This field is not set for Root ports Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_SCALE_BB_SHIFT                                      26
+  #define PCIEIP_REG_DEVICE_CAPABILITY_FLR_CAP_SUPPORTED_BB                                                  (0x1<<28) // FLR capability is advertized when flr_supported bit in private device_capability register space is set.
+  #define PCIEIP_REG_DEVICE_CAPABILITY_FLR_CAP_SUPPORTED_BB_SHIFT                                            28
+#define PCIEIP_REG_MSIX_TABLE_OFFSET_REG_K2_E5                                                               0x0000b4UL //Access:RW   DataWidth:0x20   // MSI-X Table Offset and BIR Register.
+  #define PCIEIP_REG_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_K2_E5                                                (0x7<<0) // MSI-X Table Bar Indicator Register Field.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_K2_E5_SHIFT                                          0
+  #define PCIEIP_REG_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_K2_E5                                       (0x1fffffff<<3) // MSI-X Table Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_K2_E5_SHIFT                                 3
+#define PCIEIP_REG_DEVICE_STATUS_CONTROL_BB                                                                  0x0000b4UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_CORR_ERR_REPORT_EN_BB                                             (0x1<<0) // Correctable Error Reporting Enable. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_CORR_ERR_REPORT_EN_BB_SHIFT                                       0
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_NFATAL_ERR_REPORT_EN_BB                                           (0x1<<1) // Non-Fatal Error Reporting Enable. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_NFATAL_ERR_REPORT_EN_BB_SHIFT                                     1
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_FATAL_ERR_REPORT_EN_BB                                            (0x1<<2) // Fatal Error Reporting Enable. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_FATAL_ERR_REPORT_EN_BB_SHIFT                                      2
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_U_REQ_REPORT_EN_BB                                                (0x1<<3) // Unsupported Request Reporting Enable. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_U_REQ_REPORT_EN_BB_SHIFT                                          3
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_RELAX_ORDERING_ENABLE_BB                                          (0x1<<4) // Relax Ordering Enable. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_RELAX_ORDERING_ENABLE_BB_SHIFT                                    4
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_BB                                               (0x7<<5) // Max Payload Size. Depending on the spec, internal logic uses either the min or the max of the value of the two functions. For ARI devices max payload size is determined solely by setting in Function 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_BB_SHIFT                                         5
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_EN_BB                                                (0x1<<8) // Extended Tag Field Enable. This capability when set allows DUT to generate more than 32 tags. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_EN_BB_SHIFT                                          8
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_UNUSED0_BB                                                        (0x1<<9) // 
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_UNUSED0_BB_SHIFT                                                  9
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_AUX_PWR_PM_ENA_BB                                                 (0x1<<10) // This bit when set enables device to draw aux power independent of PME AUX power Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_AUX_PWR_PM_ENA_BB_SHIFT                                           10
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_NO_SNOOP_ENABLE_BB                                                (0x1<<11) // Enable No Snoop. When this bit is set to 1, PCIE initiates a read request with the No Snoop bit in the attribute field set for the transactions that request the No Snoop attribute. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_NO_SNOOP_ENABLE_BB_SHIFT                                          11
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_MAX_READ_REQ_SIZ_BB                                               (0x7<<12) // Maximum Read Request Size. Depending on the spec, internal logic uses either the min or the max of the value of the two functions. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_MAX_READ_REQ_SIZ_BB_SHIFT                                         12
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_FLR_INITIATED_BB                                                  (0x1<<15) // Initiate Function Level reset. This bit is writeable only if flr_supported bit in private device_capability register is set. A write of 1 to this bit initiates Function Level Reset. The value read by s/w from this bit is always 0.
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_FLR_INITIATED_BB_SHIFT                                            15
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_CORR_ERR_DET_BB                                                   (0x1<<16) // Correctable Error Detected. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_CORR_ERR_DET_BB_SHIFT                                             16
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_NON_FATAL_ERR_DET_BB                                              (0x1<<17) // Non-Fatal Error Detected. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_NON_FATAL_ERR_DET_BB_SHIFT                                        17
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_FATAL_ERR_DET_BB                                                  (0x1<<18) // Fatal Error Detected. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_FATAL_ERR_DET_BB_SHIFT                                            18
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_UNSUP_REQ_DET_BB                                                  (0x1<<19) // UnSupported Request Detected. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_UNSUP_REQ_DET_BB_SHIFT                                            19
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_AUX_PWR_DET_BB                                                    (0x1<<20) // This bit is the current state of the VAUX_PRSNT pin of the device. When it is '1', it is indicating that part needs VAUX and detects the VAUX is present. Path= input to pcie_vaux_pipe
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_AUX_PWR_DET_BB_SHIFT                                              20
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_NP_TRANSACTION_PEND_BB                                            (0x1<<21) // This is bit is read back a 1, whenever a non-posted request initiated by PCIE core is pending to be completed. Path= i_tl_top
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_NP_TRANSACTION_PEND_BB_SHIFT                                      21
+#define PCIEIP_REG_MSIX_PBA_OFFSET_REG_K2_E5                                                                 0x0000b8UL //Access:RW   DataWidth:0x20   // MSI-X PBA Offset and BIR Register.
+  #define PCIEIP_REG_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_K2_E5                                                  (0x7<<0) // MSI-X PBA BIR.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_K2_E5_SHIFT                                            0
+  #define PCIEIP_REG_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_K2_E5                                           (0x1fffffff<<3) // MSI-X PBA Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_K2_E5_SHIFT                                     3
+#define PCIEIP_REG_LINK_CAPABILITY_BB                                                                        0x0000b8UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_LINK_CAPABILITY_MAX_LINK_SPEED_BB                                                       (0xf<<0) // Path= i_cfg_func.i_cfg_private Value used by internal logic is the smaller of the value programmed for each function
+  #define PCIEIP_REG_LINK_CAPABILITY_MAX_LINK_SPEED_BB_SHIFT                                                 0
+  #define PCIEIP_REG_LINK_CAPABILITY_MAX_LINK_WIDTH_BB                                                       (0x3f<<4) // Maximum Link Width. These are programmable through reg space.Bit 9 is always 0 and is not programmable. Default value is based on numLanes field in version.v Path= i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_LINK_CAPABILITY_MAX_LINK_WIDTH_BB_SHIFT                                                 4
+  #define PCIEIP_REG_LINK_CAPABILITY_ASPM_SUPT_BB                                                            (0x3<<10) // ASPM Support. These bits are programmable through reg space. Path= i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_LINK_CAPABILITY_ASPM_SUPT_BB_SHIFT                                                      10
+  #define PCIEIP_REG_LINK_CAPABILITY_L0S_EXIT_LAT_BB                                                         (0x7<<12) // L0s Exit Latency. These bits are programmable through register space. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap Depending on whether device is in common clock mode or not, the value reflected by these bits is one of the following.
+  #define PCIEIP_REG_LINK_CAPABILITY_L0S_EXIT_LAT_BB_SHIFT                                                   12
+  #define PCIEIP_REG_LINK_CAPABILITY_L1_EXIT_LAT_BB                                                          (0x7<<15) // L1 Exit Latency. These bits are programmable through register space. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap Depending on whether device is in common clock mode or not, the value reflected by these bits is one of the following.
+  #define PCIEIP_REG_LINK_CAPABILITY_L1_EXIT_LAT_BB_SHIFT                                                    15
+  #define PCIEIP_REG_LINK_CAPABILITY_CLK_PWR_MGMT_BB                                                         (0x1<<18) // Clock Power Management. These bits are programmable through register. The feature itself has to be enabled in version.v Path= i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_LINK_CAPABILITY_CLK_PWR_MGMT_BB_SHIFT                                                   18
+  #define PCIEIP_REG_LINK_CAPABILITY_SUR_DWN_ERR_REP_BB                                                      (0x1<<19) // Surprise Down Error Reporting Capable: RC: this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition. RC: Not supported and hardwired to 0. EP: Not supported and hardwired to 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_LINK_CAPABILITY_SUR_DWN_ERR_REP_BB_SHIFT                                                19
+  #define PCIEIP_REG_LINK_CAPABILITY_DL_ACTIVE_REP_BB                                                        (0x1<<20) // Data Link Layer Link Active Reporting Capable: RC: this bit must be hardwired to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine. RC: Implemented (RW) for RC. Default to 0. EP: Not supported and hardwired to 0. Path= i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_LINK_CAPABILITY_DL_ACTIVE_REP_BB_SHIFT                                                  20
+  #define PCIEIP_REG_LINK_CAPABILITY_LINK_BW_NOTIFY_BB                                                       (0x1<<21) // Link Bandwidth Notification Capability: RC: A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting Links wider than x1 and/or multiple Link speeds. RC: Field is implemented. EP: Not supported and hardwired to 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_LINK_CAPABILITY_LINK_BW_NOTIFY_BB_SHIFT                                                 21
+  #define PCIEIP_REG_LINK_CAPABILITY_UNUSED0_BB                                                              (0x3<<22) // 
+  #define PCIEIP_REG_LINK_CAPABILITY_UNUSED0_BB_SHIFT                                                        22
+  #define PCIEIP_REG_LINK_CAPABILITY_PORT_NUMBER_BB                                                          (0xff<<24) // PCIE Port Number. These bits are programmable through register. Path= i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_LINK_CAPABILITY_PORT_NUMBER_BB_SHIFT                                                    24
+#define PCIEIP_REG_LINK_STATUS_CONTROL_BB                                                                    0x0000bcUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_ASPM_CTRL_BB                                                        (0x3<<0) // ASPM Control. Value used by logic is dependent on the value of this bit for each enabled function and also on the programmed powerstate of each function. For ARI devices, ASPM setting is determined solely by the setting in Function 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_ASPM_CTRL_BB_SHIFT                                                  0
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_UNUSED0_BB                                                          (0x1<<2) // 
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_UNUSED0_BB_SHIFT                                                    2
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_RCB_BB                                                              (0x1<<3) // Read Completion Boundary. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_RCB_BB_SHIFT                                                        3
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_CFG_PSM_LINK_DISABLE_BB                                             (0x1<<4) // Requesting PHY to disable the link. This bit is only applicable to RC. So for EP it is read only bit. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_CFG_PSM_LINK_DISABLE_BB_SHIFT                                       4
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_CFG_PSM_RETRAIN_LINK_BB                                             (0x1<<5) // Requesting PHY to retrain the link. This bit is only applicable to RC. So for EP it is read only bit. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_CFG_PSM_RETRAIN_LINK_BB_SHIFT                                       5
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_CR_COMMON_CLK_BB                                               (0x1<<6) // Common Clock Configuration. Value used by logic is resolved to 1 only if all functions (when enabled) have this bit set. For ARI devices, only Function 0 determines the value used. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_CR_COMMON_CLK_BB_SHIFT                                         6
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_CR_EXT_SYNC_BB                                                 (0x1<<7) // Extended Synch. This bit when set forces the transmission of 4096 FTS ordered sets in the L0s state followed by a single SKP ordered set prior to entering the L0 state, and the transmission of 1024 TS1 ordered sets in the L1 state prior to entering the Recovery state. Value used by logic is resolved to 1 if either function has this bit set. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_CR_EXT_SYNC_BB_SHIFT                                           7
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_EN_CLK_PW_MGMT_BB                                                   (0x1<<8) // Enable Clock Power Management: RC: N/A and hardwired to 0. EP: When this bit is set, the device is permitted to use CLKREQ# signal to power management. Feature is enabled through version.v define Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_EN_CLK_PW_MGMT_BB_SHIFT                                             8
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_HW_AUTO_WIDTH_DIS_BB                                                (0x1<<9) // Hardware Autonomous Width Disable: When Set, this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width. Other functions are reserved. RC: Not applicable and hardwire to 0 EP: If supported, only apply to function0. Not implemented and hardwire to 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_HW_AUTO_WIDTH_DIS_BB_SHIFT                                          9
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_BW_MGMT_INT_EN_BB                                              (0x1<<10) // Link Bandwidth Management Interrupt Enable: when Set, this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been Set. RC: N/A and hardwired to 0. EP: Not implemented and hardwired to 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_BW_MGMT_INT_EN_BB_SHIFT                                        10
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_BW_INT_EN_BB                                                   (0x1<<11) // Link Autonomous Bandwidth Interrupt Enable: When Set, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been Set. RC: Not implemented and hardwired to 0. EP: N/A and hardwired to 0 Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_BW_INT_EN_BB_SHIFT                                             11
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_UNUSED1_BB                                                          (0xf<<12) // 
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_UNUSED1_BB_SHIFT                                                    12
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_NEG_LINK_SPEED_BB                                                   (0xf<<16) // Link Speed. These bits indicate the negotiated link speed of the PCI Express link. These bits are undefined if the link is not up (L0, L0s, L1). Path= i_pl_top.i_pl_ltssm
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_NEG_LINK_SPEED_BB_SHIFT                                             16
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_NEG_LINK_WIDTH_BB                                                   (0x3f<<20) // Negotiated Link Width. These bits indicate the negotiated link width of the PCI Express link. Path= i_pl_top.i_pl_ltssm
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_NEG_LINK_WIDTH_BB_SHIFT                                             20
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_UNUSED2_BB                                                          (0x1<<26) // 
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_UNUSED2_BB_SHIFT                                                    26
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_TRAINING_BB                                                    (0x1<<27) // EP: This bit is N/A and is hardwired to 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_TRAINING_BB_SHIFT                                              27
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_SLOT_CLK_CONFIG_BB                                                  (0x1<<28) // Slot Clock configuration. This bit is read-only by host, but read/write via backdoor CS bus. Path= i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_SLOT_CLK_CONFIG_BB_SHIFT                                            28
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_DL_ACTIVE_BB                                                        (0x1<<29) // Data Link Layer Link Active: returns a 1b to indicate the DL_Active state, 0b otherwise. Not implemented and hardwire to 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_DL_ACTIVE_BB_SHIFT                                                  29
+#define PCIEIP_REG_SLOT_CAPABILITY_BB                                                                        0x0000c0UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_SLOT_CAPABILITY_UNUSED_2_BB                                                             (0x7f<<0) // Not implemented
+  #define PCIEIP_REG_SLOT_CAPABILITY_UNUSED_2_BB_SHIFT                                                       0
+  #define PCIEIP_REG_SLOT_CAPABILITY_SLOT_POWER_LIMIT_VALUE_BB                                               (0xff<<7) // Not implemented
+  #define PCIEIP_REG_SLOT_CAPABILITY_SLOT_POWER_LIMIT_VALUE_BB_SHIFT                                         7
+  #define PCIEIP_REG_SLOT_CAPABILITY_SLOT_POWER_LIMIT_SCALE_BB                                               (0x3<<15) // Not implemented
+  #define PCIEIP_REG_SLOT_CAPABILITY_SLOT_POWER_LIMIT_SCALE_BB_SHIFT                                         15
+  #define PCIEIP_REG_SLOT_CAPABILITY_UNUSED_BB                                                               (0x3<<17) // Not implemented
+  #define PCIEIP_REG_SLOT_CAPABILITY_UNUSED_BB_SHIFT                                                         17
+  #define PCIEIP_REG_SLOT_CAPABILITY_PHYSICAL_SLOT_NUMBER_BB                                                 (0x1fff<<19) // Not implemented
+  #define PCIEIP_REG_SLOT_CAPABILITY_PHYSICAL_SLOT_NUMBER_BB_SHIFT                                           19
+#define PCIEIP_REG_SLOT_CONTROL_STATUS_BB                                                                    0x0000c4UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_SLOT_CONTROL_STATUS_SLOT_CONTROL_BB                                                     (0xffff<<0) // Not implemented
+  #define PCIEIP_REG_SLOT_CONTROL_STATUS_SLOT_CONTROL_BB_SHIFT                                               0
+  #define PCIEIP_REG_SLOT_CONTROL_STATUS_UNUSED_1_BB                                                         (0x3f<<16) // Not implemented
+  #define PCIEIP_REG_SLOT_CONTROL_STATUS_UNUSED_1_BB_SHIFT                                                   16
+  #define PCIEIP_REG_SLOT_CONTROL_STATUS_PRESENCE_DETECT_BB                                                  (0x1<<22) // Not implemented
+  #define PCIEIP_REG_SLOT_CONTROL_STATUS_PRESENCE_DETECT_BB_SHIFT                                            22
+  #define PCIEIP_REG_SLOT_CONTROL_STATUS_SLOT_STATUS_BB                                                      (0x1ff<<23) // Not implemented
+  #define PCIEIP_REG_SLOT_CONTROL_STATUS_SLOT_STATUS_BB_SHIFT                                                23
+#define PCIEIP_REG_ROOT_CAP_CONTROL_BB                                                                       0x0000c8UL //Access:R    DataWidth:0x20   // For EP this register is not applicable and hardwired to 0.
+#define PCIEIP_REG_ROOT_STATUS_BB                                                                            0x0000ccUL //Access:R    DataWidth:0x20   // For EP this register is not applicable and hardwired to 0.
+#define PCIEIP_REG_VPD_BASE_K2_E5                                                                            0x0000d0UL //Access:RW   DataWidth:0x20   // VPD Control and Capabilities Register.
+  #define PCIEIP_REG_VPD_BASE_VPD_PCIE_EXTENDED_CAP_ID_K2_E5                                                 (0xff<<0) // VPD Extended Capability ID.
+  #define PCIEIP_REG_VPD_BASE_VPD_PCIE_EXTENDED_CAP_ID_K2_E5_SHIFT                                           0
+  #define PCIEIP_REG_VPD_BASE_VPD_NEXT_OFFSET_K2_E5                                                          (0xff<<8) // VPD Pointer to Next Capability.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_VPD_BASE_VPD_NEXT_OFFSET_K2_E5_SHIFT                                                    8
+  #define PCIEIP_REG_VPD_BASE_VPD_ADDRESS_K2_E5                                                              (0x7fff<<16) // VPD Address.   Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_VPD_BASE_VPD_ADDRESS_K2_E5_SHIFT                                                        16
+  #define PCIEIP_REG_VPD_BASE_VPD_FLAG_K2_E5                                                                 (0x1<<31) // VPD Flag.   Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_VPD_BASE_VPD_FLAG_K2_E5_SHIFT                                                           31
+#define PCIEIP_REG_DEVICE_CAPABILITY_2_BB                                                                    0x0000d0UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_RANGES_SUPPORTED_BB                                    (0xf<<0) // Completion Timeout Ranges Supported. Programmable through register space Path= i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_RANGES_SUPPORTED_BB_SHIFT                              0
+  #define PCIEIP_REG_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_DISABL_SUPPORTED_BB                                    (0x1<<4) // Completion Timeout Disable Supported, Programmable through register space Path= i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_DISABL_SUPPORTED_BB_SHIFT                              4
+  #define PCIEIP_REG_DEVICE_CAPABILITY_2_UNUSED0_BB                                                          (0x3f<<5) // 
+  #define PCIEIP_REG_DEVICE_CAPABILITY_2_UNUSED0_BB_SHIFT                                                    5
+  #define PCIEIP_REG_DEVICE_CAPABILITY_2_LTR_MECHANISM_SUPPORTED_BB                                          (0x1<<11) // Latency Tolerance Reporting Mechanism Supported, Programmable through register space. This field will read 1, when bit 5 of ext_cap_ena field in private register space is set.
+  #define PCIEIP_REG_DEVICE_CAPABILITY_2_LTR_MECHANISM_SUPPORTED_BB_SHIFT                                    11
+  #define PCIEIP_REG_DEVICE_CAPABILITY_2_TPH_COMPLETER_SUPPORTED_BB                                          (0x3<<12) // TPH and Extended TPH completer not supported.
+  #define PCIEIP_REG_DEVICE_CAPABILITY_2_TPH_COMPLETER_SUPPORTED_BB_SHIFT                                    12
+  #define PCIEIP_REG_DEVICE_CAPABILITY_2_UNUSED1_BB                                                          (0xf<<14) // 
+  #define PCIEIP_REG_DEVICE_CAPABILITY_2_UNUSED1_BB_SHIFT                                                    14
+  #define PCIEIP_REG_DEVICE_CAPABILITY_2_OBFF_SUPORTED_BB                                                    (0x3<<18) // OBFF Supported using WAKE# signaling only. Value is programmable through private register space in Device_cap2.
+  #define PCIEIP_REG_DEVICE_CAPABILITY_2_OBFF_SUPORTED_BB_SHIFT                                              18
+#define PCIEIP_REG_DATA_REG_K2_E5                                                                            0x0000d4UL //Access:RW   DataWidth:0x20   // VPD Data Register.
+#define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_BB                                                                0x0000d4UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_VALUE_BB                                           (0xf<<0) // Completion timeout value. The spec specifies a range, the device uses the max value in the range. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_VALUE_BB_SHIFT                                     0
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_DISABLE_BB                                         (0x1<<4) // Completion Timeout Disable Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_DISABLE_BB_SHIFT                                   4
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_UNUSED0_BB                                                      (0x1<<5) // 
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_UNUSED0_BB_SHIFT                                                5
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_ATOMIC_REQ_ENABLE_BB                                            (0x1<<6) // Atomic requester Enable. When this bit is set, function and associated VF's are enabled to make Atomic Op requests.
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_ATOMIC_REQ_ENABLE_BB_SHIFT                                      6
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_UNUSED1_BB                                                      (0x1<<7) // 
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_UNUSED1_BB_SHIFT                                                7
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_IDO_REQ_ENABLE_BB                                               (0x1<<8) // IDO Request Enable, This field is writeable, when bit ido_supported bit of private device_capability_2 register is set. When this bit is set, function is permitted to set ID based Ordering Attribute of Requests it initiates.
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_IDO_REQ_ENABLE_BB_SHIFT                                         8
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_IDO_CPL_ENABLE_BB                                               (0x1<<9) // IDO Completion Enable, This field is writeable, when bit ido_supported bit of private device_capability_2 register is set. When this bit is set, function is permitted to set ID based Ordering Attribute of Completions it returns.
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_IDO_CPL_ENABLE_BB_SHIFT                                         9
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_LTR_MECHANISM_ENABLE_BB                                         (0x1<<10) // Latency Tolerance Reporting Mechanism Enable, This field is writeable, when bit 5 of ext_cap_ena field in private register space is set. This bit is RW only in function 0 and is RsvdP for all other functions.
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_LTR_MECHANISM_ENABLE_BB_SHIFT                                   10
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_UNUSED2_BB                                                      (0x3<<11) // 
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_UNUSED2_BB_SHIFT                                                11
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_OBFF_ENABLE_BB                                                  (0x3<<13) // Enable OBFF mechanism and select signaling method. This field is writeable, when bit 5 of ext_cap_ena field in private register space is set. This bit is RW only in function 0 and is RsvdP for all other functions.
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_OBFF_ENABLE_BB_SHIFT                                            13
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_UNUSED3_BB                                                      (0x1<<15) // 
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_UNUSED3_BB_SHIFT                                                15
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_DEVICE_STATUS_2_BB                                              (0xffff<<16) // Placeholder for Gen2 Path= i_cfg_func.i_cfg_public.i_cfg_rd_mux
+  #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_DEVICE_STATUS_2_BB_SHIFT                                        16
+#define PCIEIP_REG_LINK_CAPABILITY_2_BB                                                                      0x0000d8UL //Access:R    DataWidth:0x20   // Placeholder for Gen2 Path= i_cfg_func.i_cfg_private
+#define PCIEIP_REG_LINK_STATUS_CONTROL_2_BB                                                                  0x0000dcUL //Access:RW   DataWidth:0x20   // This register will be Read only by default, and will read all 0's to allow compliance with PCIE spec 1.1. To enable this register, reset comply_pcie_1_1 bit in the register space to 0.
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED_BB                                              (0xf<<0) // Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED_BB_SHIFT                                        0
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_ENTER_COMPLIANCE_BB                                               (0x1<<4) // 
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_ENTER_COMPLIANCE_BB_SHIFT                                         4
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_HW_AUTO_SPEED_DISABLE_BB                                          (0x1<<5) // 
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_HW_AUTO_SPEED_DISABLE_BB_SHIFT                                    5
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_SEL_DEEMPHASIS_BB                                                 (0x1<<6) // When link is operating at Gen2 rates, this bit selects the level of de-emphasis. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap Value used by logic is resolved to 1 if either function has this bit set.
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_SEL_DEEMPHASIS_BB_SHIFT                                           6
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_TX_MARGIN_BB                                                  (0x7<<7) // Value used by logic is resolved to the smaller binary value, if two functions have different values.
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_TX_MARGIN_BB_SHIFT                                            7
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_ENTER_MOD_COMPLIANCE_BB                                       (0x1<<10) // 
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_ENTER_MOD_COMPLIANCE_BB_SHIFT                                 10
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_SOS_BB                                             (0x1<<11) // 
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_SOS_BB_SHIFT                                       11
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_DEEMPH_BB                                          (0x1<<12) // 
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_DEEMPH_BB_SHIFT                                    12
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_UNUSED0_BB                                                        (0x7<<13) // 
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_UNUSED0_BB_SHIFT                                                  13
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CURR_DEEMPH_LEVEL_BB                                              (0x1<<16) // curr_deemph_level Path = pl_top
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CURR_DEEMPH_LEVEL_BB_SHIFT                                        16
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_EQ_COMPLETE_BB                                                (0x1<<17) // Equalization Complete - when set, this indicates that the Transmitter equalization procedure has completed. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_EQ_COMPLETE_BB_SHIFT                                          17
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_EQ_PHASE1_SUCCESS_BB                                          (0x1<<18) // Equalization Phase 1 Successful - when set, this indicates that Phase 1 of the Transmitter equalization procedure has successfully completed. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_EQ_PHASE1_SUCCESS_BB_SHIFT                                    18
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_EQ_PHASE2_SUCCESS_BB                                          (0x1<<19) // Equalization Phase 2 Successful - when set, this indicates that Phase 2 of the Transmitter equalization procedure has successfully completed. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_EQ_PHASE2_SUCCESS_BB_SHIFT                                    19
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_EQ_PHASE3_SUCCESS_BB                                          (0x1<<20) // Equalization Phase 3 Successful - when set, this indicates that Phase 3 of the Transmitter equalization procedure has successfully completed. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_EQ_PHASE3_SUCCESS_BB_SHIFT                                    20
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_LINK_EQ_REQUEST_BB                                            (0x1<<21) // This bit is set by hardware to request the link equalization process to be performed on the link. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_LINK_EQ_REQUEST_BB_SHIFT                                      21
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_LINK_STATUS_2_UNUSED_BB                                           (0x3ff<<22) // Placeholder
+  #define PCIEIP_REG_LINK_STATUS_CONTROL_2_LINK_STATUS_2_UNUSED_BB_SHIFT                                     22
+#define PCIEIP_REG_SLOT_CAPABILITY_2_BB                                                                      0x0000e0UL //Access:R    DataWidth:0x20   // Not implemented
+#define PCIEIP_REG_SLOT_STATUS_CONTROL_2_BB                                                                  0x0000e4UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_SLOT_STATUS_CONTROL_2_SLOT_CONTROL_2_BB                                                 (0xffff<<0) // Not implemented
+  #define PCIEIP_REG_SLOT_STATUS_CONTROL_2_SLOT_CONTROL_2_BB_SHIFT                                           0
+  #define PCIEIP_REG_SLOT_STATUS_CONTROL_2_SLOT_STATUS_2_BB                                                  (0xffff<<16) // Not implemented
+  #define PCIEIP_REG_SLOT_STATUS_CONTROL_2_SLOT_STATUS_2_BB_SHIFT                                            16
+#define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_K2_E5                                                                 0x000100UL //Access:RW   DataWidth:0x20   // Advanced Error Reporting Extended Capability Header.
+  #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_CAP_ID_K2_E5                                                        (0xffff<<0) // AER Extended Capability ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_CAP_ID_K2_E5_SHIFT                                                  0
+  #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_CAP_VERSION_K2_E5                                                   (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_CAP_VERSION_K2_E5_SHIFT                                             16
+  #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_K2_E5                                                   (0xfff<<20) // Next Capability Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_K2_E5_SHIFT                                             20
+#define PCIEIP_REG_ADV_ERR_CAP_BB                                                                            0x000100UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_ADV_ERR_CAP_ADV_ERR_CAP_ID_BB                                                           (0xffff<<0) // PCI Express Extended Capability ID. These bits are hardwired to 0001h indicating the presence of PCI Express Advanced Error Capability. Path= cfg_defs
+  #define PCIEIP_REG_ADV_ERR_CAP_ADV_ERR_CAP_ID_BB_SHIFT                                                     0
+  #define PCIEIP_REG_ADV_ERR_CAP_VER_BB                                                                      (0xf<<16) // Capability ID Version. These bits are hardwired to 1h indicating the version of the capability ID. Path= cfg_defs.v
+  #define PCIEIP_REG_ADV_ERR_CAP_VER_BB_SHIFT                                                                16
+  #define PCIEIP_REG_ADV_ERR_CAP_NEXT_BB                                                                     (0xfff<<20) // Next Capabilities Pointer is 0x13C which is Power Budget. Path= i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_ADV_ERR_CAP_NEXT_BB_SHIFT                                                               20
+#define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_K2_E5                                                               0x000104UL //Access:RW   DataWidth:0x20   // Uncorrectable Error Status Register.
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_K2_E5                                      (0x1<<4) // Data Link Protocol Error Status.
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_K2_E5_SHIFT                                4
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_SUR_DWN_ERR_STATUS_K2_E5                                          (0x1<<5) // Surprise Down Error Status (Optional).   Note: Not supported.
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_SUR_DWN_ERR_STATUS_K2_E5_SHIFT                                    5
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_K2_E5                                         (0x1<<12) // Poisoned TLP Status.
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_K2_E5_SHIFT                                   12
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_K2_E5                                      (0x1<<13) // Flow Control Protocol Error Status.
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_K2_E5_SHIFT                                13
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_K2_E5                                    (0x1<<14) // Completion Timeout Status.
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_K2_E5_SHIFT                              14
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_K2_E5                                      (0x1<<15) // Completer Abort Status.
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_K2_E5_SHIFT                                15
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_K2_E5                                      (0x1<<16) // Unexpected Completion Status.
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_K2_E5_SHIFT                                16
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_K2_E5                                     (0x1<<17) // Receiver Overflow Status.
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_K2_E5_SHIFT                               17
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_K2_E5                                         (0x1<<18) // Malformed TLP Status.
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_K2_E5_SHIFT                                   18
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_K2_E5                                             (0x1<<19) // ECRC Error Status.
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_K2_E5_SHIFT                                       19
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_K2_E5                                  (0x1<<20) // Unsupported Request Error Status.
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_K2_E5_SHIFT                            20
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_K2_E5                                         (0x1<<22) // Uncorrectable Internal Error Status.    The core sets this bit when your application asserts app_err_bus[9]. It does not set this bit when it detects internal uncorrectable internal errors such as parity and ECC failures. You should use the outputs from these errors to drive the app_err_bus[9] input. For more details, see the "Data Integrity (Wire, Datapath, and RAM Protection)" section in the Databook.
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_K2_E5_SHIFT                                   22
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_TLP_PRFX_BLOCKED_ERR_STATUS_K2_E5                                 (0x1<<25) // TLP Prefix Blocked Error Status.   Note: Not supported.
+  #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_TLP_PRFX_BLOCKED_ERR_STATUS_K2_E5_SHIFT                           25
+#define PCIEIP_REG_UC_ERR_STATUS_BB                                                                          0x000104UL //Access:RW   DataWidth:0x20   // Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap
+  #define PCIEIP_REG_UC_ERR_STATUS_UNUSED0_BB                                                                (0xf<<0) // 
+  #define PCIEIP_REG_UC_ERR_STATUS_UNUSED0_BB_SHIFT                                                          0
+  #define PCIEIP_REG_UC_ERR_STATUS_DLPES_BB                                                                  (0x1<<4) // Data Link Protocol Error Status
+  #define PCIEIP_REG_UC_ERR_STATUS_DLPES_BB_SHIFT                                                            4
+  #define PCIEIP_REG_UC_ERR_STATUS_UNUSED1_BB                                                                (0x7f<<5) // 
+  #define PCIEIP_REG_UC_ERR_STATUS_UNUSED1_BB_SHIFT                                                          5
+  #define PCIEIP_REG_UC_ERR_STATUS_PTLPS_BB                                                                  (0x1<<12) // Poisoned TLP Status.
+  #define PCIEIP_REG_UC_ERR_STATUS_PTLPS_BB_SHIFT                                                            12
+  #define PCIEIP_REG_UC_ERR_STATUS_FCPES_BB                                                                  (0x1<<13) // Flow Control Protocol Error Status.
+  #define PCIEIP_REG_UC_ERR_STATUS_FCPES_BB_SHIFT                                                            13
+  #define PCIEIP_REG_UC_ERR_STATUS_CTS_BB                                                                    (0x1<<14) // Completer Timeout Status.
+  #define PCIEIP_REG_UC_ERR_STATUS_CTS_BB_SHIFT                                                              14
+  #define PCIEIP_REG_UC_ERR_STATUS_CAS_BB                                                                    (0x1<<15) // Completer Abort Status.
+  #define PCIEIP_REG_UC_ERR_STATUS_CAS_BB_SHIFT                                                              15
+  #define PCIEIP_REG_UC_ERR_STATUS_UCS_BB                                                                    (0x1<<16) // Unexpected Completion Status.
+  #define PCIEIP_REG_UC_ERR_STATUS_UCS_BB_SHIFT                                                              16
+  #define PCIEIP_REG_UC_ERR_STATUS_ROS_BB                                                                    (0x1<<17) // Receiver Overflow Status.
+  #define PCIEIP_REG_UC_ERR_STATUS_ROS_BB_SHIFT                                                              17
+  #define PCIEIP_REG_UC_ERR_STATUS_MTLPS_BB                                                                  (0x1<<18) // Malformed TLP Status.
+  #define PCIEIP_REG_UC_ERR_STATUS_MTLPS_BB_SHIFT                                                            18
+  #define PCIEIP_REG_UC_ERR_STATUS_ECRCS_BB                                                                  (0x1<<19) // ECRC Error Status
+  #define PCIEIP_REG_UC_ERR_STATUS_ECRCS_BB_SHIFT                                                            19
+  #define PCIEIP_REG_UC_ERR_STATUS_URES_BB                                                                   (0x1<<20) // Unsupported Request Error Status.
+  #define PCIEIP_REG_UC_ERR_STATUS_URES_BB_SHIFT                                                             20
+#define PCIEIP_REG_UNCORR_ERR_MASK_OFF_K2_E5                                                                 0x000108UL //Access:RW   DataWidth:0x20   // Uncorrectable Error Mask Register.
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_K2_E5                                          (0x1<<4) // Data Link Protocol Error Mask.   Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_K2_E5_SHIFT                                    4
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_SUR_DWN_ERR_MASK_K2_E5                                              (0x1<<5) // Surprise Down Error Mask.   Note: Not supported.  Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_SUR_DWN_ERR_MASK_K2_E5_SHIFT                                        5
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_K2_E5                                             (0x1<<12) // Poisoned TLP Error Mask.   Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_K2_E5_SHIFT                                       12
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_K2_E5                                          (0x1<<13) // Flow Control Protocol Error Mask.   Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_K2_E5_SHIFT                                    13
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_K2_E5                                        (0x1<<14) // Completion Timeout Error Mask.   Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_K2_E5_SHIFT                                  14
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_K2_E5                                          (0x1<<15) // Completer Abort Error Mask (Optional).   Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_K2_E5_SHIFT                                    15
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_K2_E5                                          (0x1<<16) // Unexpected Completion Mask.   Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_K2_E5_SHIFT                                    16
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_K2_E5                                         (0x1<<17) // Receiver Overflow Mask (Optional).   Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_K2_E5_SHIFT                                   17
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_K2_E5                                             (0x1<<18) // Malformed TLP Mask.   Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_K2_E5_SHIFT                                       18
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_K2_E5                                                 (0x1<<19) // ECRC Error Mask (Optional).   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_K2_E5_SHIFT                                           19
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_K2_E5                                      (0x1<<20) // Unsupported Request Error Mask.   Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_K2_E5_SHIFT                                20
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_K2_E5                                             (0x1<<22) // Uncorrectable Internal Error Mask (Optional).   Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_K2_E5_SHIFT                                       22
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_K2_E5                                (0x1<<24) // AtomicOp Egress Block Mask (Optional).   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_K2_E5_SHIFT                          24
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_TLP_PRFX_BLOCKED_ERR_MASK_K2_E5                                     (0x1<<25) // TLP Prefix Blocked Error Mask.   Note: Not supported.  Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_TLP_PRFX_BLOCKED_ERR_MASK_K2_E5_SHIFT                               25
+#define PCIEIP_REG_UCORR_ERR_MASK_BB                                                                         0x000108UL //Access:RW   DataWidth:0x20   // Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap
+  #define PCIEIP_REG_UCORR_ERR_MASK_UNUSED0_BB                                                               (0xf<<0) // 
+  #define PCIEIP_REG_UCORR_ERR_MASK_UNUSED0_BB_SHIFT                                                         0
+  #define PCIEIP_REG_UCORR_ERR_MASK_DLPEM_BB                                                                 (0x1<<4) // Data Link Protocol Error Mask.
+  #define PCIEIP_REG_UCORR_ERR_MASK_DLPEM_BB_SHIFT                                                           4
+  #define PCIEIP_REG_UCORR_ERR_MASK_SDEM_BB                                                                  (0x1<<5) // Surprise Down Error Mask
+  #define PCIEIP_REG_UCORR_ERR_MASK_SDEM_BB_SHIFT                                                            5
+  #define PCIEIP_REG_UCORR_ERR_MASK_UNUSED1_BB                                                               (0x3f<<6) // 
+  #define PCIEIP_REG_UCORR_ERR_MASK_UNUSED1_BB_SHIFT                                                         6
+  #define PCIEIP_REG_UCORR_ERR_MASK_PTLPM_BB                                                                 (0x1<<12) // Poisoned TLP Mask.
+  #define PCIEIP_REG_UCORR_ERR_MASK_PTLPM_BB_SHIFT                                                           12
+  #define PCIEIP_REG_UCORR_ERR_MASK_FCPEM_BB                                                                 (0x1<<13) // Flow Control Protocol Error Mask.
+  #define PCIEIP_REG_UCORR_ERR_MASK_FCPEM_BB_SHIFT                                                           13
+  #define PCIEIP_REG_UCORR_ERR_MASK_CTM_BB                                                                   (0x1<<14) // Completer Timeout Mask.
+  #define PCIEIP_REG_UCORR_ERR_MASK_CTM_BB_SHIFT                                                             14
+  #define PCIEIP_REG_UCORR_ERR_MASK_CAM_BB                                                                   (0x1<<15) // Completer Abort Mask.
+  #define PCIEIP_REG_UCORR_ERR_MASK_CAM_BB_SHIFT                                                             15
+  #define PCIEIP_REG_UCORR_ERR_MASK_UCM_BB                                                                   (0x1<<16) // Unexpected Completion Mask.
+  #define PCIEIP_REG_UCORR_ERR_MASK_UCM_BB_SHIFT                                                             16
+  #define PCIEIP_REG_UCORR_ERR_MASK_ROM_BB                                                                   (0x1<<17) // Receiver Overflow Mask.
+  #define PCIEIP_REG_UCORR_ERR_MASK_ROM_BB_SHIFT                                                             17
+  #define PCIEIP_REG_UCORR_ERR_MASK_MTLPM_BB                                                                 (0x1<<18) // Malformed TLP Mask.
+  #define PCIEIP_REG_UCORR_ERR_MASK_MTLPM_BB_SHIFT                                                           18
+  #define PCIEIP_REG_UCORR_ERR_MASK_ECRCEM_BB                                                                (0x1<<19) // ECRC Error Mask
+  #define PCIEIP_REG_UCORR_ERR_MASK_ECRCEM_BB_SHIFT                                                          19
+  #define PCIEIP_REG_UCORR_ERR_MASK_UREM_BB                                                                  (0x1<<20) // Unsupported Request Error Mask.
+  #define PCIEIP_REG_UCORR_ERR_MASK_UREM_BB_SHIFT                                                            20
+#define PCIEIP_REG_UNCORR_ERR_SEV_OFF_K2_E5                                                                  0x00010cUL //Access:RW   DataWidth:0x20   // Uncorrectable Error Severity Register.
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_K2_E5                                       (0x1<<4) // Data Link Protocol Error Severity.   Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_K2_E5_SHIFT                                 4
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_SUR_DWN_ERR_SEVERITY_K2_E5                                           (0x1<<5) // Surprise Down Error Severity (Optional).   Note: Not supported.  Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_SUR_DWN_ERR_SEVERITY_K2_E5_SHIFT                                     5
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_K2_E5                                          (0x1<<12) // Poisoned TLP Severity.   Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_K2_E5_SHIFT                                    12
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_K2_E5                                       (0x1<<13) // Flow Control Protocol Error Severity (Optional).   Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_K2_E5_SHIFT                                 13
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_K2_E5                                     (0x1<<14) // Completion Timeout Error Severity.   Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_K2_E5_SHIFT                               14
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_K2_E5                                       (0x1<<15) // Completer Abort Error Severity (Optional).   Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_K2_E5_SHIFT                                 15
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_K2_E5                                       (0x1<<16) // Unexpected Completion Error Severity.   Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_K2_E5_SHIFT                                 16
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_K2_E5                                      (0x1<<17) // Receiver Overflow Error Severity (Optional).   Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_K2_E5_SHIFT                                17
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_K2_E5                                          (0x1<<18) // Malformed TLP Severity.   Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_K2_E5_SHIFT                                    18
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_K2_E5                                              (0x1<<19) // ECRC Error Severity (Optional).   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_K2_E5_SHIFT                                        19
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_K2_E5                                   (0x1<<20) // Unsupported Request Error Severity.   Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_K2_E5_SHIFT                             20
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_K2_E5                                          (0x1<<22) // Uncorrectable Internal Error Severity (Optional).   Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_K2_E5_SHIFT                                    22
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_K2_E5                             (0x1<<24) // AtomicOp Egress Blocked Severity (Optional).   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_K2_E5_SHIFT                       24
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_TLP_PRFX_BLOCKED_ERR_SEVERITY_K2_E5                                  (0x1<<25) // TLP Prefix Blocked Error Severity (Optional).   Note: Not supported.  Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_TLP_PRFX_BLOCKED_ERR_SEVERITY_K2_E5_SHIFT                            25
+#define PCIEIP_REG_UCORR_ERR_SEVR_BB                                                                         0x00010cUL //Access:RW   DataWidth:0x20   // Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap
+  #define PCIEIP_REG_UCORR_ERR_SEVR_UNUSED0_BB                                                               (0xf<<0) // 
+  #define PCIEIP_REG_UCORR_ERR_SEVR_UNUSED0_BB_SHIFT                                                         0
+  #define PCIEIP_REG_UCORR_ERR_SEVR_DLPES_BB                                                                 (0x1<<4) // Data Link Protocol Error Severity.
+  #define PCIEIP_REG_UCORR_ERR_SEVR_DLPES_BB_SHIFT                                                           4
+  #define PCIEIP_REG_UCORR_ERR_SEVR_SDES_BB                                                                  (0x1<<5) // Surprise Down Error Severity. Hardwire to 1'b1.
+  #define PCIEIP_REG_UCORR_ERR_SEVR_SDES_BB_SHIFT                                                            5
+  #define PCIEIP_REG_UCORR_ERR_SEVR_UNUSED1_BB                                                               (0x3f<<6) // 
+  #define PCIEIP_REG_UCORR_ERR_SEVR_UNUSED1_BB_SHIFT                                                         6
+  #define PCIEIP_REG_UCORR_ERR_SEVR_PTLPS_BB                                                                 (0x1<<12) // Poisoned TLP Severity.
+  #define PCIEIP_REG_UCORR_ERR_SEVR_PTLPS_BB_SHIFT                                                           12
+  #define PCIEIP_REG_UCORR_ERR_SEVR_FCPES_BB                                                                 (0x1<<13) // Flow Control Protocol Error Severity.
+  #define PCIEIP_REG_UCORR_ERR_SEVR_FCPES_BB_SHIFT                                                           13
+  #define PCIEIP_REG_UCORR_ERR_SEVR_CTS_BB                                                                   (0x1<<14) // Completer Timeout Severity.
+  #define PCIEIP_REG_UCORR_ERR_SEVR_CTS_BB_SHIFT                                                             14
+  #define PCIEIP_REG_UCORR_ERR_SEVR_CAS_BB                                                                   (0x1<<15) // Completer Abort Severity.
+  #define PCIEIP_REG_UCORR_ERR_SEVR_CAS_BB_SHIFT                                                             15
+  #define PCIEIP_REG_UCORR_ERR_SEVR_UCS_BB                                                                   (0x1<<16) // Unexpected Completion Severity.
+  #define PCIEIP_REG_UCORR_ERR_SEVR_UCS_BB_SHIFT                                                             16
+  #define PCIEIP_REG_UCORR_ERR_SEVR_ROS_BB                                                                   (0x1<<17) // Receiver Overflow Severity.
+  #define PCIEIP_REG_UCORR_ERR_SEVR_ROS_BB_SHIFT                                                             17
+  #define PCIEIP_REG_UCORR_ERR_SEVR_MTLPS_BB                                                                 (0x1<<18) // Malformed TLP Severity.
+  #define PCIEIP_REG_UCORR_ERR_SEVR_MTLPS_BB_SHIFT                                                           18
+  #define PCIEIP_REG_UCORR_ERR_SEVR_ECRCES_BB                                                                (0x1<<19) // Ecrc error Severity
+  #define PCIEIP_REG_UCORR_ERR_SEVR_ECRCES_BB_SHIFT                                                          19
+  #define PCIEIP_REG_UCORR_ERR_SEVR_URES_BB                                                                  (0x1<<20) // Unsupported Request Error Severity.
+  #define PCIEIP_REG_UCORR_ERR_SEVR_URES_BB_SHIFT                                                            20
+#define PCIEIP_REG_CORR_ERR_STATUS_OFF_K2_E5                                                                 0x000110UL //Access:RW   DataWidth:0x20   // Correctable Error Status Register.
+  #define PCIEIP_REG_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_K2_E5                                                 (0x1<<0) // Receiver Error Status (Optional).
+  #define PCIEIP_REG_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_K2_E5_SHIFT                                           0
+  #define PCIEIP_REG_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_K2_E5                                                (0x1<<6) // Bad TLP Status.
+  #define PCIEIP_REG_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_K2_E5_SHIFT                                          6
+  #define PCIEIP_REG_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_K2_E5                                               (0x1<<7) // Bad DLLP Status.
+  #define PCIEIP_REG_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_K2_E5_SHIFT                                         7
+  #define PCIEIP_REG_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_K2_E5                                     (0x1<<8) // REPLAY_NUM Rollover Status.
+  #define PCIEIP_REG_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_K2_E5_SHIFT                               8
+  #define PCIEIP_REG_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_K2_E5                                      (0x1<<12) // Replay Timer Timeout Status.
+  #define PCIEIP_REG_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_K2_E5_SHIFT                                12
+  #define PCIEIP_REG_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_K2_E5                                 (0x1<<13) // Advisory Non-Fatal Error Status.
+  #define PCIEIP_REG_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_K2_E5_SHIFT                           13
+  #define PCIEIP_REG_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_K2_E5                                      (0x1<<14) // Corrected Internal Error Status (Optional).
+  #define PCIEIP_REG_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_K2_E5_SHIFT                                14
+  #define PCIEIP_REG_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_K2_E5                                    (0x1<<15) // Header Log Overflow Error Status (Optional).
+  #define PCIEIP_REG_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_K2_E5_SHIFT                              15
+#define PCIEIP_REG_CORR_ERR_STATUS_BB                                                                        0x000110UL //Access:RW   DataWidth:0x20   // Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap
+  #define PCIEIP_REG_CORR_ERR_STATUS_RX_ERR_STATUS_BB                                                        (0x1<<0) // Receiver Error Status.
+  #define PCIEIP_REG_CORR_ERR_STATUS_RX_ERR_STATUS_BB_SHIFT                                                  0
+  #define PCIEIP_REG_CORR_ERR_STATUS_UNUSED0_BB                                                              (0x1f<<1) // 
+  #define PCIEIP_REG_CORR_ERR_STATUS_UNUSED0_BB_SHIFT                                                        1
+  #define PCIEIP_REG_CORR_ERR_STATUS_BAD_TLP_STATUS_BB                                                       (0x1<<6) // Bad TLP Status.
+  #define PCIEIP_REG_CORR_ERR_STATUS_BAD_TLP_STATUS_BB_SHIFT                                                 6
+  #define PCIEIP_REG_CORR_ERR_STATUS_BAD_DLLP_STATUS_BB                                                      (0x1<<7) // Bad DLLP Status.
+  #define PCIEIP_REG_CORR_ERR_STATUS_BAD_DLLP_STATUS_BB_SHIFT                                                7
+  #define PCIEIP_REG_CORR_ERR_STATUS_RPLAY_NUM_RO_STATUS_BB                                                  (0x1<<8) // REPLAY_NUM Rollover Status.
+  #define PCIEIP_REG_CORR_ERR_STATUS_RPLAY_NUM_RO_STATUS_BB_SHIFT                                            8
+  #define PCIEIP_REG_CORR_ERR_STATUS_UNUSED1_BB                                                              (0x7<<9) // 
+  #define PCIEIP_REG_CORR_ERR_STATUS_UNUSED1_BB_SHIFT                                                        9
+  #define PCIEIP_REG_CORR_ERR_STATUS_RPLAY_TMR_TO_STATUS_BB                                                  (0x1<<12) // Replay Timer Timeout Status.
+  #define PCIEIP_REG_CORR_ERR_STATUS_RPLAY_TMR_TO_STATUS_BB_SHIFT                                            12
+  #define PCIEIP_REG_CORR_ERR_STATUS_ADVSRY_ERR_STATUS_BB                                                    (0x1<<13) // Advisory Non fatal Error Status. Only set if role_based_err_rpt is asserted.
+  #define PCIEIP_REG_CORR_ERR_STATUS_ADVSRY_ERR_STATUS_BB_SHIFT                                              13
+#define PCIEIP_REG_CORR_ERR_MASK_OFF_K2_E5                                                                   0x000114UL //Access:RW   DataWidth:0x20   // Correctable Error Mask Register.
+  #define PCIEIP_REG_CORR_ERR_MASK_OFF_RX_ERR_MASK_K2_E5                                                     (0x1<<0) // Receiver Error Mask (Optional).   Note: This register field is sticky.
+  #define PCIEIP_REG_CORR_ERR_MASK_OFF_RX_ERR_MASK_K2_E5_SHIFT                                               0
+  #define PCIEIP_REG_CORR_ERR_MASK_OFF_BAD_TLP_MASK_K2_E5                                                    (0x1<<6) // Bad TLP Mask.   Note: This register field is sticky.
+  #define PCIEIP_REG_CORR_ERR_MASK_OFF_BAD_TLP_MASK_K2_E5_SHIFT                                              6
+  #define PCIEIP_REG_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_K2_E5                                                   (0x1<<7) // Bad DLLP Mask.   Note: This register field is sticky.
+  #define PCIEIP_REG_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_K2_E5_SHIFT                                             7
+  #define PCIEIP_REG_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_K2_E5                                         (0x1<<8) // REPLAY_NUM Rollover Mask.   Note: This register field is sticky.
+  #define PCIEIP_REG_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_K2_E5_SHIFT                                   8
+  #define PCIEIP_REG_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_K2_E5                                          (0x1<<12) // Replay Timer Timeout Mask.   Note: This register field is sticky.
+  #define PCIEIP_REG_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_K2_E5_SHIFT                                    12
+  #define PCIEIP_REG_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_K2_E5                                     (0x1<<13) // Advisory Non-Fatal Error Mask.   Note: This register field is sticky.
+  #define PCIEIP_REG_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_K2_E5_SHIFT                               13
+  #define PCIEIP_REG_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_K2_E5                                          (0x1<<14) // Corrected Internal Error Mask (Optional).   Note: This register field is sticky.
+  #define PCIEIP_REG_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_K2_E5_SHIFT                                    14
+  #define PCIEIP_REG_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_K2_E5                                        (0x1<<15) // Header Log Overflow Error Mask (Optional).   Note: This register field is sticky.
+  #define PCIEIP_REG_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_K2_E5_SHIFT                                  15
+#define PCIEIP_REG_CORR_ERR_MASK_BB                                                                          0x000114UL //Access:RW   DataWidth:0x20   // Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap
+  #define PCIEIP_REG_CORR_ERR_MASK_RES_BB                                                                    (0x1<<0) // Receiver Error Mask.
+  #define PCIEIP_REG_CORR_ERR_MASK_RES_BB_SHIFT                                                              0
+  #define PCIEIP_REG_CORR_ERR_MASK_UNUSED0_BB                                                                (0x1f<<1) // 
+  #define PCIEIP_REG_CORR_ERR_MASK_UNUSED0_BB_SHIFT                                                          1
+  #define PCIEIP_REG_CORR_ERR_MASK_BTLPS_BB                                                                  (0x1<<6) // Bad TLP Mask.
+  #define PCIEIP_REG_CORR_ERR_MASK_BTLPS_BB_SHIFT                                                            6
+  #define PCIEIP_REG_CORR_ERR_MASK_BDLLPS_BB                                                                 (0x1<<7) // Bad DLLP Mask.
+  #define PCIEIP_REG_CORR_ERR_MASK_BDLLPS_BB_SHIFT                                                           7
+  #define PCIEIP_REG_CORR_ERR_MASK_RNRS_BB                                                                   (0x1<<8) // REPLAY_NUM Rollover Mask.
+  #define PCIEIP_REG_CORR_ERR_MASK_RNRS_BB_SHIFT                                                             8
+  #define PCIEIP_REG_CORR_ERR_MASK_UNUSED1_BB                                                                (0x7<<9) // 
+  #define PCIEIP_REG_CORR_ERR_MASK_UNUSED1_BB_SHIFT                                                          9
+  #define PCIEIP_REG_CORR_ERR_MASK_RTTS_BB                                                                   (0x1<<12) // Replay Timer Timeout Mask.
+  #define PCIEIP_REG_CORR_ERR_MASK_RTTS_BB_SHIFT                                                             12
+  #define PCIEIP_REG_CORR_ERR_MASK_ANFM_BB                                                                   (0x1<<13) // Advisory Non fatal Error Mask
+  #define PCIEIP_REG_CORR_ERR_MASK_ANFM_BB_SHIFT                                                             13
+#define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_K2_E5                                                                0x000118UL //Access:RW   DataWidth:0x20   // Advanced Error Capabilities and Control Register.
+  #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_K2_E5                                            (0x1f<<0) // First Error Pointer.   Note: This register field is sticky.
+  #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_K2_E5_SHIFT                                      0
+  #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_K2_E5                                                 (0x1<<5) // ECRC Generation Capable.   Note: This register field is sticky.
+  #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_K2_E5_SHIFT                                           5
+  #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_K2_E5                                                  (0x1<<6) // ECRC Generation Enable.   Note: This register field is sticky.
+  #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_K2_E5_SHIFT                                            6
+  #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_K2_E5                                               (0x1<<7) // ECRC Check Capable.   Note: This register field is sticky.
+  #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_K2_E5_SHIFT                                         7
+  #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_K2_E5                                                (0x1<<8) // ECRC Check Enable.   Note: This register field is sticky.
+  #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_K2_E5_SHIFT                                          8
+  #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_K2_E5                                          (0x1<<9) // Multiple Header Recording Capable.   Note: This register field is sticky.
+  #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_K2_E5_SHIFT                                    9
+  #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_K2_E5                                           (0x1<<10) // Multiple Header Recording Enable.   Note: This register field is sticky.
+  #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_K2_E5_SHIFT                                     10
+#define PCIEIP_REG_ADV_ERR_CAP_CONTROL_BB                                                                    0x000118UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_FIRST_UERR_PTR_BB                                                   (0x1f<<0) // First Error Pointer - These bits correspond to the bit position in which the first error occurred.
+  #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_FIRST_UERR_PTR_BB_SHIFT                                             0
+  #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCGCAP_BB                                                         (0x1<<5) // ECRC generation capable, programmable through register space
+  #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCGCAP_BB_SHIFT                                                   5
+  #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCGEN_BB                                                          (0x1<<6) // ECRC generate Enable
+  #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCGEN_BB_SHIFT                                                    6
+  #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCCAP_BB                                                          (0x1<<7) // ECRC Check Capable, programmable through register space
+  #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCCAP_BB_SHIFT                                                    7
+  #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCEN_BB                                                           (0x1<<8) // ECRC Check Enable
+  #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCEN_BB_SHIFT                                                     8
+#define PCIEIP_REG_HDR_LOG_0_OFF_K2_E5                                                                       0x00011cUL //Access:R    DataWidth:0x20   // Header Log Register 0.
+  #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_K2_E5                                              (0xff<<0) // Byte 0 of Header log register of First 32 bit Data Word.   Note: This register field is sticky.
+  #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_K2_E5_SHIFT                                        0
+  #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_K2_E5                                             (0xff<<8) // Byte 1 of Header log register of First 32 bit Data Word.   Note: This register field is sticky.
+  #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_K2_E5_SHIFT                                       8
+  #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_K2_E5                                              (0xff<<16) // Byte 2 of Header log register of First 32 bit Data Word.   Note: This register field is sticky.
+  #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_K2_E5_SHIFT                                        16
+  #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_K2_E5                                             (0xff<<24) // Byte 3 of Header log register of First 32 bit Data Word.   Note: This register field is sticky.
+  #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_K2_E5_SHIFT                                       24
+#define PCIEIP_REG_HEADER_LOG1_BB                                                                            0x00011cUL //Access:R    DataWidth:0x20   // Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap
+#define PCIEIP_REG_HDR_LOG_1_OFF_K2_E5                                                                       0x000120UL //Access:R    DataWidth:0x20   // Header Log Register 1.
+  #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_K2_E5                                             (0xff<<0) // Byte 0 of Header log register of Second 32 bit Data Word.   Note: This register field is sticky.
+  #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_K2_E5_SHIFT                                       0
+  #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_K2_E5                                            (0xff<<8) // Byte 1 of Header log register of Second 32 bit Data Word.   Note: This register field is sticky.
+  #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_K2_E5_SHIFT                                      8
+  #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_K2_E5                                             (0xff<<16) // Byte 2 of Header log register of Second 32 bit Data Word.   Note: This register field is sticky.
+  #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_K2_E5_SHIFT                                       16
+  #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_K2_E5                                            (0xff<<24) // Byte 3 of Header log register of Second 32 bit Data Word.   Note: This register field is sticky.
+  #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_K2_E5_SHIFT                                      24
+#define PCIEIP_REG_HEADER_LOG2_BB                                                                            0x000120UL //Access:R    DataWidth:0x20   // Second DW of TLP header associated with Error. Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap
+#define PCIEIP_REG_HDR_LOG_2_OFF_K2_E5                                                                       0x000124UL //Access:R    DataWidth:0x20   // Header Log Register 2.
+  #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_K2_E5                                              (0xff<<0) // Byte 0 of Header log register of Third 32 bit Data Word.   Note: This register field is sticky.
+  #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_K2_E5_SHIFT                                        0
+  #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_K2_E5                                             (0xff<<8) // Byte 1 of Header log register of Third 32 bit Data Word.   Note: This register field is sticky.
+  #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_K2_E5_SHIFT                                       8
+  #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_K2_E5                                              (0xff<<16) // Byte 2 of Header log register of Third 32 bit Data Word.   Note: This register field is sticky.
+  #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_K2_E5_SHIFT                                        16
+  #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_K2_E5                                             (0xff<<24) // Byte 3 of Header log register of Third 32 bit Data Word.   Note: This register field is sticky.
+  #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_K2_E5_SHIFT                                       24
+#define PCIEIP_REG_HEADER_LOG3_BB                                                                            0x000124UL //Access:R    DataWidth:0x20   // Third DW of TLP header associated with Error. Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap
+#define PCIEIP_REG_HDR_LOG_3_OFF_K2_E5                                                                       0x000128UL //Access:R    DataWidth:0x20   // Header Log Register 3.
+  #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_K2_E5                                             (0xff<<0) // Byte 0 of Header log register of Fourth 32 bit Data Word.   Note: This register field is sticky.
+  #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_K2_E5_SHIFT                                       0
+  #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_K2_E5                                            (0xff<<8) // Byte 1 of Header log register of Fourth 32 bit Data Word.   Note: This register field is sticky.
+  #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_K2_E5_SHIFT                                      8
+  #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_K2_E5                                             (0xff<<16) // Byte 2 of Header log register of Fourth 32 bit Data Word.   Note: This register field is sticky.
+  #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_K2_E5_SHIFT                                       16
+  #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_K2_E5                                            (0xff<<24) // Byte 3 of Header log register of Fourth 32 bit Data Word.   Note: This register field is sticky.
+  #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_K2_E5_SHIFT                                      24
+#define PCIEIP_REG_HEADER_LOG4_BB                                                                            0x000128UL //Access:R    DataWidth:0x20   // Fourth DW of TLP header associated with Error. Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap
+#define PCIEIP_REG_ROOT_ERROR_COMMAND_BB                                                                     0x00012cUL //Access:R    DataWidth:0x20   // For EP this register is not applicable and hardwired to 0.
+#define PCIEIP_REG_ROOT_ERROR_STATUS_BB                                                                      0x000130UL //Access:R    DataWidth:0x20   // For EP this register is not applicable and hardwired to 0.
+#define PCIEIP_REG_ROOT_ERR_ID_BB                                                                            0x000134UL //Access:R    DataWidth:0x20   // For EP this register is not applicable and hardwired to 0.
+#define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_K2_E5                                                                0x000138UL //Access:R    DataWidth:0x20   // TLP Prefix Log Register 1.
+  #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_K2_E5                                 (0xff<<0) // Byte 0 of Error TLP Prefix Log 1.   Note: This register field is sticky.
+  #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_K2_E5_SHIFT                           0
+  #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_K2_E5                                (0xff<<8) // Byte 1 of Error TLP Prefix Log 1.   Note: This register field is sticky.
+  #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_K2_E5_SHIFT                          8
+  #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_K2_E5                                 (0xff<<16) // Byte 2 of Error TLP Prefix Log 1.   Note: This register field is sticky.
+  #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_K2_E5_SHIFT                           16
+  #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_K2_E5                                (0xff<<24) // Byte 3 of Error TLP Prefix Log 1.   Note: This register field is sticky.
+  #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_K2_E5_SHIFT                          24
+#define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_K2_E5                                                                0x00013cUL //Access:R    DataWidth:0x20   // TLP Prefix Log Register 2.
+  #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_K2_E5                                 (0xff<<0) // Byte 0 Error TLP Prefix Log 2.   Note: This register field is sticky.
+  #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_K2_E5_SHIFT                           0
+  #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_K2_E5                                (0xff<<8) // Byte 1 Error TLP Prefix Log 2.   Note: This register field is sticky.
+  #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_K2_E5_SHIFT                          8
+  #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_K2_E5                                 (0xff<<16) // Byte 2 Error TLP Prefix Log 2.   Note: This register field is sticky.
+  #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_K2_E5_SHIFT                           16
+  #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_K2_E5                                (0xff<<24) // Byte 3 Error TLP Prefix Log 2.   Note: This register field is sticky.
+  #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_K2_E5_SHIFT                          24
+#define PCIEIP_REG_DEVICE_SER_NUM_CAP_BB                                                                     0x00013cUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DEVICE_SER_NUM_CAP_DEVICE_SER_NUM_CAP_ID_BB                                             (0xffff<<0) // Device Serial Number Extended Capability ID. These bits are programmable through register space. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_DEVICE_SER_NUM_CAP_DEVICE_SER_NUM_CAP_ID_BB_SHIFT                                       0
+  #define PCIEIP_REG_DEVICE_SER_NUM_CAP_VER_BB                                                               (0xf<<16) // Capability ID Version. These bits are programmable through register space. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_DEVICE_SER_NUM_CAP_VER_BB_SHIFT                                                         16
+  #define PCIEIP_REG_DEVICE_SER_NUM_CAP_NEXT_BB                                                              (0xfff<<20) // Next Capabilities Pointer. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_DEVICE_SER_NUM_CAP_NEXT_BB_SHIFT                                                        20
+#define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_K2_E5                                                                0x000140UL //Access:R    DataWidth:0x20   // TLP Prefix Log Register 3.
+  #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_K2_E5                                 (0xff<<0) // Byte 0 Error TLP Prefix Log 3.   Note: This register field is sticky.
+  #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_K2_E5_SHIFT                           0
+  #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_K2_E5                                (0xff<<8) // Byte 1 Error TLP Prefix Log 3.   Note: This register field is sticky.
+  #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_K2_E5_SHIFT                          8
+  #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_K2_E5                                 (0xff<<16) // Byte 2 Error TLP Prefix Log 3.   Note: This register field is sticky.
+  #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_K2_E5_SHIFT                           16
+  #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_K2_E5                                (0xff<<24) // Byte 3 Error TLP Prefix Log 3.   Note: This register field is sticky.
+  #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_K2_E5_SHIFT                          24
+#define PCIEIP_REG_LOWER_SER_NUM_BB                                                                          0x000140UL //Access:R    DataWidth:0x20   // This register has the PCIE Device Serial Number bits [31:0]. This register will contain the data written in the Device Serial Number Access Lower Register (Offset 504h). Path = i_cfg_func.i_cfg_private
+#define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_K2_E5                                                                0x000144UL //Access:R    DataWidth:0x20   // TLP Prefix Log Register 4.
+  #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_K2_E5                                 (0xff<<0) // Byte 0 Error TLP Prefix Log 4.   Note: This register field is sticky.
+  #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_K2_E5_SHIFT                           0
+  #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_K2_E5                                (0xff<<8) // Byte 1 Error TLP Prefix Log 4.   Note: This register field is sticky.
+  #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_K2_E5_SHIFT                          8
+  #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_K2_E5                                 (0xff<<16) // Byte 2 Error TLP Prefix Log 4.   Note: This register field is sticky.
+  #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_K2_E5_SHIFT                           16
+  #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_K2_E5                                (0xff<<24) // Byte 3 Error TLP Prefix Log 4.   Note: This register field is sticky.
+  #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_K2_E5_SHIFT                          24
+#define PCIEIP_REG_UPPER_SER_NUM_BB                                                                          0x000144UL //Access:R    DataWidth:0x20   // This register has the PCIE Device Serial Number bits [63:32]. This register will contain the data written in the Device Serial Number Access Upper Register (Offset 508h). Path = i_cfg_func.i_cfg_private
+#define PCIEIP_REG_VC_BASE_K2_E5                                                                             0x000148UL //Access:RW   DataWidth:0x20   // VC Extended Capability Header.
+  #define PCIEIP_REG_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_K2_E5                                                   (0xffff<<0) // VC Extended Capability ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_K2_E5_SHIFT                                             0
+  #define PCIEIP_REG_VC_BASE_VC_CAP_VERSION_K2_E5                                                            (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_VC_BASE_VC_CAP_VERSION_K2_E5_SHIFT                                                      16
+  #define PCIEIP_REG_VC_BASE_VC_NEXT_OFFSET_K2_E5                                                            (0xfff<<20) // Next Capability Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_VC_BASE_VC_NEXT_OFFSET_K2_E5_SHIFT                                                      20
+#define PCIEIP_REG_VC_CAPABILITIES_REG_1_K2_E5                                                               0x00014cUL //Access:RW   DataWidth:0x20   // Port VC Capability Register 1.
+  #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_K2_E5                                               (0x7<<0) // Extended VC Count.
+  #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_K2_E5_SHIFT                                         0
+  #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_K2_E5                                       (0x7<<4) // Low Priority Extended VC Count.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_K2_E5_SHIFT                                 4
+  #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_K2_E5                                          (0x3<<8) // Reference Clock.
+  #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_K2_E5_SHIFT                                    8
+  #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_K2_E5                                 (0x3<<10) // Port Arbitration Table Entry Size.
+  #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_K2_E5_SHIFT                           10
+#define PCIEIP_REG_VC_CAPABILITIES_REG_2_K2_E5                                                               0x000150UL //Access:RW   DataWidth:0x20   // Port VC Capability Register 2.
+  #define PCIEIP_REG_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_K2_E5                                                 (0xf<<0) // VC Arbitration Capability.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_K2_E5_SHIFT                                           0
+  #define PCIEIP_REG_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_K2_E5                                        (0xff<<24) // VC Arbitration Table Offset.
+  #define PCIEIP_REG_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_K2_E5_SHIFT                                  24
+#define PCIEIP_REG_PWR_BDGT_CAP_BB                                                                           0x000150UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PWR_BDGT_CAP_PWR_BDGT_CAP_ID_BB                                                         (0xffff<<0) // Power Budgeting Extended Capability ID. Hardwired to 4. Path = cfg_defs
+  #define PCIEIP_REG_PWR_BDGT_CAP_PWR_BDGT_CAP_ID_BB_SHIFT                                                   0
+  #define PCIEIP_REG_PWR_BDGT_CAP_VER_BB                                                                     (0xf<<16) // Capability ID Version. These bits are hardwired to 1h indicating the version of the capability ID. Hardwire to 1. Path = cfg_defs
+  #define PCIEIP_REG_PWR_BDGT_CAP_VER_BB_SHIFT                                                               16
+  #define PCIEIP_REG_PWR_BDGT_CAP_NEXT_BB                                                                    (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability. The read-only value of this register is controlled by the EXT_CAP_ENA register in the PCI register space. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_PWR_BDGT_CAP_NEXT_BB_SHIFT                                                              20
+#define PCIEIP_REG_VC_STATUS_CONTROL_REG_K2_E5                                                               0x000154UL //Access:RW   DataWidth:0x20   // Port VC Control and Status Register.
+  #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_K2_E5                                       (0x1<<0) // Requests Hardware to Load VC Arbitration Table.
+  #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_K2_E5_SHIFT                                 0
+  #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_K2_E5                                              (0x7<<1) // VC Arbitration Select.
+  #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_K2_E5_SHIFT                                        1
+  #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_K2_E5                                        (0x1<<16) // VC Arbitration Table Status.
+  #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_K2_E5_SHIFT                                  16
+#define PCIEIP_REG_PWR_BDGT_DATA_SEL_BB                                                                      0x000154UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PWR_BDGT_DATA_SEL_DS_VALUE_BB                                                           (0xff<<0) // This value selects the value visible in the pb_dr. Path = i_cfg_func.i_cfg_public.i_cfg_pw_budget_cap
+  #define PCIEIP_REG_PWR_BDGT_DATA_SEL_DS_VALUE_BB_SHIFT                                                     0
+#define PCIEIP_REG_RESOURCE_CAP_REG_VC0_K2_E5                                                                0x000158UL //Access:R    DataWidth:0x20   // VC Resource Capability Register (0).
+  #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_K2_E5                                         (0xff<<0) // Port Arbitration Capability.
+  #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_K2_E5_SHIFT                                   0
+  #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_K2_E5                                    (0x1<<15) // Reject Snoop Transactions.   Note: The access attributes of this field are as follows:  - Dbi: R
+  #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_K2_E5_SHIFT                              15
+  #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_K2_E5                                         (0x3f<<16) // Maximum Time Slots-1 supported.   Note: The access attributes of this field are as follows:  - Dbi: R
+  #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_K2_E5_SHIFT                                   16
+  #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_K2_E5                                       (0xff<<24) // Port Arbitration Table Offset.
+  #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_K2_E5_SHIFT                                 24
+#define PCIEIP_REG_PWR_BDGT_DATA_BB                                                                          0x000158UL //Access:R    DataWidth:0x20   // This register provides the power budgeting data for the entry number specified by the pwr_bdgt_data_sel register. The data present in this register is selected from one of the POWER BUDGET DATA ACCESS Registers from offset 510h through 52Ch, based on the value written in Power Budget Data Select register. The field definitions for each selected value are the same. Path = i_cfg_func.i_cfg_public.i_cfg_pw_budget_cap
+  #define PCIEIP_REG_PWR_BDGT_DATA_BASE_PWR_BB                                                               (0xff<<0) // Base Power
+  #define PCIEIP_REG_PWR_BDGT_DATA_BASE_PWR_BB_SHIFT                                                         0
+  #define PCIEIP_REG_PWR_BDGT_DATA_DSCALE_BB                                                                 (0x3<<8) // Data Scale
+  #define PCIEIP_REG_PWR_BDGT_DATA_DSCALE_BB_SHIFT                                                           8
+  #define PCIEIP_REG_PWR_BDGT_DATA_UNUSED0_BB                                                                (0x7<<10) // 
+  #define PCIEIP_REG_PWR_BDGT_DATA_UNUSED0_BB_SHIFT                                                          10
+  #define PCIEIP_REG_PWR_BDGT_DATA_PM_STATE_BB                                                               (0x3<<13) // PM State
+  #define PCIEIP_REG_PWR_BDGT_DATA_PM_STATE_BB_SHIFT                                                         13
+  #define PCIEIP_REG_PWR_BDGT_DATA_TYPE_BB                                                                   (0x7<<15) // Type
+  #define PCIEIP_REG_PWR_BDGT_DATA_TYPE_BB_SHIFT                                                             15
+  #define PCIEIP_REG_PWR_BDGT_DATA_RAIL_BB                                                                   (0x7<<18) // Power rail
+  #define PCIEIP_REG_PWR_BDGT_DATA_RAIL_BB_SHIFT                                                             18
+#define PCIEIP_REG_RESOURCE_CON_REG_VC0_K2_E5                                                                0x00015cUL //Access:RW   DataWidth:0x20   // VC Resource Control Register (0).
+  #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_K2_E5                                                (0x1<<0) // Bit 0 of TC to VC Mapping.
+  #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_K2_E5_SHIFT                                          0
+  #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_K2_E5                                           (0x7f<<1) // Bits 7:1 of TC to VC Mapping.
+  #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_K2_E5_SHIFT                                     1
+  #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_K2_E5                                  (0x1<<16) // Load Port Arbitration Table.
+  #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_K2_E5_SHIFT                            16
+  #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_K2_E5                                      (0x1<<17) // Port Arbitration Select.
+  #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_K2_E5_SHIFT                                17
+  #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_ID_VC_K2_E5                                                     (0x7<<24) // VC ID.
+  #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_ID_VC_K2_E5_SHIFT                                               24
+  #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_K2_E5                                                (0x1<<31) // VC Enable.
+  #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_K2_E5_SHIFT                                          31
+#define PCIEIP_REG_PWR_BDGT_CAPABILITY_BB                                                                    0x00015cUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PWR_BDGT_CAPABILITY_PCIE_CFG_PB_CAP_SYS_ALLOC_BB                                        (0x1<<0) // The "System Allocated" bit when set indicates that the power budget for the device is included within the system power budget. Reported Power Budgeting Data for this device should be ignored by software for power budgeting decisions if this bit is set. This register is Read Only. The value can be written indirectly by writing into Power Budget Capability Register (0x550[0]) Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_PWR_BDGT_CAPABILITY_PCIE_CFG_PB_CAP_SYS_ALLOC_BB_SHIFT                                  0
+#define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_K2_E5                                                             0x000160UL //Access:R    DataWidth:0x20   // VC Resource Status Register (0).
+  #define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_K2_E5                             (0x1<<16) // Port Arbitration Table Status.
+  #define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_K2_E5_SHIFT                       16
+  #define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_K2_E5                                       (0x1<<17) // VC Negotiation Pending.
+  #define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_K2_E5_SHIFT                                 17
+#define PCIEIP_REG_VC_CAP_BB                                                                                 0x000160UL //Access:R    DataWidth:0x20   // The read-back value of this register is controlled by the EXT_CAP_ENA register in the PCI register space.
+  #define PCIEIP_REG_VC_CAP_VC_CAP_ID_BB                                                                     (0xffff<<0) // Virtual channel Capability ID. Hardwired to 2. Path = cfg_defs
+  #define PCIEIP_REG_VC_CAP_VC_CAP_ID_BB_SHIFT                                                               0
+  #define PCIEIP_REG_VC_CAP_VC_CAP_VER_BB                                                                    (0xf<<16) // Capability ID Version. These bits are hardwired to 1h indicating the version of the capability ID. Hardwire to 1. Path = cfg_defs
+  #define PCIEIP_REG_VC_CAP_VC_CAP_VER_BB_SHIFT                                                              16
+  #define PCIEIP_REG_VC_CAP_VC_NEXT_CAP_OFF_BB                                                               (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_VC_CAP_VC_NEXT_CAP_OFF_BB_SHIFT                                                         20
+#define PCIEIP_REG_PORT_VC_CAPABILITY_BB                                                                     0x000164UL //Access:R    DataWidth:0x20   // Not implemented.
+#define PCIEIP_REG_SN_BASE_K2_E5                                                                             0x000168UL //Access:RW   DataWidth:0x20   // Device Serial Number Extended Capability Header.
+  #define PCIEIP_REG_SN_BASE_SN_PCIE_EXTENDED_CAP_ID_K2_E5                                                   (0xffff<<0) // Serial Number Extended Capability ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_SN_BASE_SN_PCIE_EXTENDED_CAP_ID_K2_E5_SHIFT                                             0
+  #define PCIEIP_REG_SN_BASE_SN_CAP_VERSION_K2_E5                                                            (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_SN_BASE_SN_CAP_VERSION_K2_E5_SHIFT                                                      16
+  #define PCIEIP_REG_SN_BASE_SN_NEXT_OFFSET_K2_E5                                                            (0xfff<<20) // Next Capability Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_SN_BASE_SN_NEXT_OFFSET_K2_E5_SHIFT                                                      20
+#define PCIEIP_REG_PORT_VC_CAPABILITY2_BB                                                                    0x000168UL //Access:R    DataWidth:0x20   // Not implemented.
+#define PCIEIP_REG_SER_NUM_REG_DW_1_K2_E5                                                                    0x00016cUL //Access:RW   DataWidth:0x20   // Serial Number 1 Register.
+#define PCIEIP_REG_PORT_VC_STATUS_CONTROL_BB                                                                 0x00016cUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PORT_VC_STATUS_CONTROL_PORT_VC_CONTROL_BB                                               (0xffff<<0) // Not implemented.
+  #define PCIEIP_REG_PORT_VC_STATUS_CONTROL_PORT_VC_CONTROL_BB_SHIFT                                         0
+  #define PCIEIP_REG_PORT_VC_STATUS_CONTROL_PORT_VC_STATUS_BB                                                (0xffff<<16) // Not implemented.
+  #define PCIEIP_REG_PORT_VC_STATUS_CONTROL_PORT_VC_STATUS_BB_SHIFT                                          16
+#define PCIEIP_REG_SER_NUM_REG_DW_2_K2_E5                                                                    0x000170UL //Access:RW   DataWidth:0x20   // Serial Number 2 Register.
+#define PCIEIP_REG_PORT_ARB_TABLE_BB                                                                         0x000170UL //Access:R    DataWidth:0x20   // Not implemented.
+#define PCIEIP_REG_VC_RSRC_CONTROL_BB                                                                        0x000174UL //Access:RW   DataWidth:0x20   // The read-back value of this register is controlled by the EXT_CAP_ENA register in the PCI register space.
+  #define PCIEIP_REG_VC_RSRC_CONTROL_DEFAULT_VC0_BB                                                          (0x1<<0) // This bit is hardwired to one because DUT is only support VC0. Path = i_cfg_func.i_cfg_public.i_cfg_vc_cap
+  #define PCIEIP_REG_VC_RSRC_CONTROL_DEFAULT_VC0_BB_SHIFT                                                    0
+  #define PCIEIP_REG_VC_RSRC_CONTROL_TC_VC_MAP_BB                                                            (0x7f<<1) // This field indicates the TCs that are mapped to the VC resource. This field is valid for all devices. Note: Bit 0 of this field is read only. It is set to 1 for the default VC0. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_VC_RSRC_CONTROL_TC_VC_MAP_BB_SHIFT                                                      1
+  #define PCIEIP_REG_VC_RSRC_CONTROL_UNUSED0_BB                                                              (0x7fffff<<8) // 
+  #define PCIEIP_REG_VC_RSRC_CONTROL_UNUSED0_BB_SHIFT                                                        8
+  #define PCIEIP_REG_VC_RSRC_CONTROL_VC_ENABLE_BB                                                            (0x1<<31) // Enables virtual channel. This bit is hardwired to 1 for the default VC0 and writing to this filed has no effect. Path = i_cfg_func.i_cfg_public.i_cfg_vc_cap
+  #define PCIEIP_REG_VC_RSRC_CONTROL_VC_ENABLE_BB_SHIFT                                                      31
+#define PCIEIP_REG_PB_BASE_K2_E5                                                                             0x000178UL //Access:RW   DataWidth:0x20   // Power Budgeting Extended Capability Header.
+  #define PCIEIP_REG_PB_BASE_PB_PCIE_EXTENDED_CAP_ID_K2_E5                                                   (0xffff<<0) // PB Extended Capability ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_PB_BASE_PB_PCIE_EXTENDED_CAP_ID_K2_E5_SHIFT                                             0
+  #define PCIEIP_REG_PB_BASE_PB_CAP_VERSION_K2_E5                                                            (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_PB_BASE_PB_CAP_VERSION_K2_E5_SHIFT                                                      16
+  #define PCIEIP_REG_PB_BASE_PB_NEXT_OFFSET_K2_E5                                                            (0xfff<<20) // Next Capability Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_PB_BASE_PB_NEXT_OFFSET_K2_E5_SHIFT                                                      20
+#define PCIEIP_REG_VC_RSRC_STATUS_BB                                                                         0x000178UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_VC_RSRC_STATUS_UNUSED0_BB                                                               (0xffff<<0) // 
+  #define PCIEIP_REG_VC_RSRC_STATUS_UNUSED0_BB_SHIFT                                                         0
+  #define PCIEIP_REG_VC_RSRC_STATUS_VC_RSRC_STATUS_BB                                                        (0xffff<<16) // Not implemented.
+  #define PCIEIP_REG_VC_RSRC_STATUS_VC_RSRC_STATUS_BB_SHIFT                                                  16
+#define PCIEIP_REG_PB_DATA_SELECT_K2_E5                                                                      0x00017cUL //Access:RW   DataWidth:0x20   // Data select Register.
+  #define PCIEIP_REG_PB_DATA_SELECT_PB_DATA_SEL_K2_E5                                                        (0xff<<0) // Data Select Register.
+  #define PCIEIP_REG_PB_DATA_SELECT_PB_DATA_SEL_K2_E5_SHIFT                                                  0
+#define PCIEIP_REG_DATA_REG_PB_K2_E5                                                                         0x000180UL //Access:R    DataWidth:0x20   // Data Register.
+  #define PCIEIP_REG_DATA_REG_PB_PB_BASE_POWER_K2_E5                                                         (0xff<<0) // Base Power.
+  #define PCIEIP_REG_DATA_REG_PB_PB_BASE_POWER_K2_E5_SHIFT                                                   0
+  #define PCIEIP_REG_DATA_REG_PB_PB_DATA_SCALE_K2_E5                                                         (0x3<<8) // Data Scale.
+  #define PCIEIP_REG_DATA_REG_PB_PB_DATA_SCALE_K2_E5_SHIFT                                                   8
+  #define PCIEIP_REG_DATA_REG_PB_PB_PM_SUB_STATE_K2_E5                                                       (0x7<<10) // PM Sub State.
+  #define PCIEIP_REG_DATA_REG_PB_PB_PM_SUB_STATE_K2_E5_SHIFT                                                 10
+  #define PCIEIP_REG_DATA_REG_PB_PB_PM_STATE_K2_E5                                                           (0x3<<13) // PM State.
+  #define PCIEIP_REG_DATA_REG_PB_PB_PM_STATE_K2_E5_SHIFT                                                     13
+  #define PCIEIP_REG_DATA_REG_PB_PB_TYPE_K2_E5                                                               (0x7<<15) // Type of Operating Condition.
+  #define PCIEIP_REG_DATA_REG_PB_PB_TYPE_K2_E5_SHIFT                                                         15
+  #define PCIEIP_REG_DATA_REG_PB_PB_POWER_RAIL_STATE_K2_E5                                                   (0x7<<18) // Power Rail State.
+  #define PCIEIP_REG_DATA_REG_PB_PB_POWER_RAIL_STATE_K2_E5_SHIFT                                             18
+#define PCIEIP_REG_VENDOR_CAP_BB                                                                             0x000180UL //Access:R    DataWidth:0x20   // The read-only value of this register is controlled by setting bit 0 of the EXT_CAP_ENA for EP, or setting bit 0 of RC_EXT_CAP_ENA for RC. By default, this capability is disabled (i.e. reading this register will return zeroes). The capability can be enabled by default by defining VendorCapOn in version.v. When supporting SRIOV, this capability is enabled if PCIE_VF_BAR_STRIDE is defined in version.v
+  #define PCIEIP_REG_VENDOR_CAP_VENDOR_SPEC_CAP_ID_BB                                                        (0xffff<<0) // Vendor Specific Extended Capability ID. Hardwired to 0xB. Path = cfg_defs
+  #define PCIEIP_REG_VENDOR_CAP_VENDOR_SPEC_CAP_ID_BB_SHIFT                                                  0
+  #define PCIEIP_REG_VENDOR_CAP_CAP_VER_BB                                                                   (0xf<<16) // Vendor Specific Extended Capability version. Hardwired to 0x1. Path = cfg_defs
+  #define PCIEIP_REG_VENDOR_CAP_CAP_VER_BB_SHIFT                                                             16
+  #define PCIEIP_REG_VENDOR_CAP_NEXT_BB                                                                      (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
+  #define PCIEIP_REG_VENDOR_CAP_NEXT_BB_SHIFT                                                                20
+#define PCIEIP_REG_CAP_REG_PB_K2_E5                                                                          0x000184UL //Access:RW   DataWidth:0x20   // Power Budget Capability Register.
+  #define PCIEIP_REG_CAP_REG_PB_PB_SYS_ALLOC_K2_E5                                                           (0x1<<0) // System Allocated PB.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_CAP_REG_PB_PB_SYS_ALLOC_K2_E5_SHIFT                                                     0
+#define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_BB                                                                 0x000184UL //Access:R    DataWidth:0x20   // The read-only value of this register is controlled by setting bit 0 of the EXT_CAP_ENA for EP, or setting bit 0 of RC_EXT_CAP_ENA for RC. By default, this capability is disabled (i.e. reading this register will return zeroes). The capability can be enabled by default by defining VendorCapOn in version.v
+  #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_VSEC_ID_BB                                                       (0xffff<<0) // VSEC ID. This field is a vendor-defined ID number that indicates the nature and format of the VSEC structure. Software must qualify the Vendor ID before interpreting this field. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_VSEC_ID_BB_SHIFT                                                 0
+  #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_VSEC_REV_BB                                                      (0xf<<16) // VSEC Rev. This field is a vendor-defined version number that indicates the version of the VSEC structure. Software must qualify the Vendor ID and VSEC ID before interpreting this field. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_VSEC_REV_BB_SHIFT                                                16
+  #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_VSEC_LENGTH_BB                                                   (0xfff<<20) // VSEC Length. This field indicates the number of bytes in the entire VSEC structure, including the PCI Express Enhanced Capability header, the Vendor-Specific header, and the Vendor-Specific Registers. Path = i_cfg_func.i_cfg_private
+  #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_VSEC_LENGTH_BB_SHIFT                                             20
+#define PCIEIP_REG_ARI_BASE_K2_E5                                                                            0x000188UL //Access:RW   DataWidth:0x20   // ARI Capability Header.
+  #define PCIEIP_REG_ARI_BASE_ARI_PCIE_EXTENDED_CAP_ID_K2_E5                                                 (0xffff<<0) // ARI Extended Capability ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_ARI_BASE_ARI_PCIE_EXTENDED_CAP_ID_K2_E5_SHIFT                                           0
+  #define PCIEIP_REG_ARI_BASE_ARI_CAP_VERSION_K2_E5                                                          (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_ARI_BASE_ARI_CAP_VERSION_K2_E5_SHIFT                                                    16
+  #define PCIEIP_REG_ARI_BASE_ARI_NEXT_OFFSET_K2_E5                                                          (0xfff<<20) // Next Capability Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_ARI_BASE_ARI_NEXT_OFFSET_K2_E5_SHIFT                                                    20
+#define PCIEIP_REG_VENDOR_SPECIFIC_REG1_BB                                                                   0x000188UL //Access:RW   DataWidth:0x20   // If bit 0 of the EXT_CAP_ENA for EP or bit 0 of RC_EXT_CAP_ENA for RC is reset to '0', reading this register will return all 0's. By default, this capability is disabled (i.e. reading this register will return zeroes). The capability can be enabled by default by defining VendorCapOn or PCIE_VF_BAR_STRIDE in version.v
+  #define PCIEIP_REG_VENDOR_SPECIFIC_REG1_VF_BAR0_STRIDE_BITS_BB                                             (0x7fffffff<<0) // This field defines alignment and stride of VF BAR0 address space. The bits are a power of 2 value that multiplies the PF VF Bar0 value to compute the starting address and alignment of the BAR0 for each VF. This field may only have 1 bit set.This field is ignored when bit 31 is 0.
+  #define PCIEIP_REG_VENDOR_SPECIFIC_REG1_VF_BAR0_STRIDE_BITS_BB_SHIFT                                       0
+  #define PCIEIP_REG_VENDOR_SPECIFIC_REG1_VF_BAR0_STRIDE_EN_BB                                               (0x1<<31) // Enable VF Bar0 Stride. When this bit bit is clear, computation of the VF BAR0 offset from the PF SRIOV capability structure is unchanged.
+  #define PCIEIP_REG_VENDOR_SPECIFIC_REG1_VF_BAR0_STRIDE_EN_BB_SHIFT                                         31
+#define PCIEIP_REG_CAP_REG_K2_E5                                                                             0x00018cUL //Access:R    DataWidth:0x20   // ARI Capability and Control Register.
+  #define PCIEIP_REG_CAP_REG_ARI_MFVC_FUN_GRP_CAP_K2_E5                                                      (0x1<<0) // Multi Functional Virtual Channel (MFVC) Function Groups Capability.
+  #define PCIEIP_REG_CAP_REG_ARI_MFVC_FUN_GRP_CAP_K2_E5_SHIFT                                                0
+  #define PCIEIP_REG_CAP_REG_ARI_ACS_FUN_GRP_CAP_K2_E5                                                       (0x1<<1) // ACS Function Groups Capability.
+  #define PCIEIP_REG_CAP_REG_ARI_ACS_FUN_GRP_CAP_K2_E5_SHIFT                                                 1
+  #define PCIEIP_REG_CAP_REG_ARI_NEXT_FUN_NUM_K2_E5                                                          (0xff<<8) // Next Function Number.
+  #define PCIEIP_REG_CAP_REG_ARI_NEXT_FUN_NUM_K2_E5_SHIFT                                                    8
+  #define PCIEIP_REG_CAP_REG_ARI_MFVC_FUN_GRP_EN_K2_E5                                                       (0x1<<16) // MFVC Function Groups Enable.
+  #define PCIEIP_REG_CAP_REG_ARI_MFVC_FUN_GRP_EN_K2_E5_SHIFT                                                 16
+  #define PCIEIP_REG_CAP_REG_ARI_ACS_FUN_GRP_EN_K2_E5                                                        (0x1<<17) // ACS Function Groups Enable.
+  #define PCIEIP_REG_CAP_REG_ARI_ACS_FUN_GRP_EN_K2_E5_SHIFT                                                  17
+  #define PCIEIP_REG_CAP_REG_ARI_FUN_GRP_K2_E5                                                               (0x7<<20) // Function Group.
+  #define PCIEIP_REG_CAP_REG_ARI_FUN_GRP_K2_E5_SHIFT                                                         20
+#define PCIEIP_REG_VENDOR_SPECIFIC_REG2_BB                                                                   0x00018cUL //Access:R    DataWidth:0x20   // 
+#define PCIEIP_REG_VENDOR_SPECIFIC_REG3_BB                                                                   0x000190UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_VENDOR_SPECIFIC_REG3_VF_BAR2_STRIDE_BITS_BB                                             (0x7fffffff<<0) // This field defines alignment and stride of VF BAR2 address space. The bits are a power of 2 value that multiplies the PF VF Bar2 value to compute the starting address and alignment of the BAR2 for each VF. This field may only have 1 bit set.This field is ignored when bit 31 is 0.
+  #define PCIEIP_REG_VENDOR_SPECIFIC_REG3_VF_BAR2_STRIDE_BITS_BB_SHIFT                                       0
+  #define PCIEIP_REG_VENDOR_SPECIFIC_REG3_VF_BAR2_STRIDE_EN_BB                                               (0x1<<31) // Enable VF Bar2 Stride. When this bit bit is clear, computation of the VF BAR2 offset from the PF SRIOV capability structure is unchanged.
+  #define PCIEIP_REG_VENDOR_SPECIFIC_REG3_VF_BAR2_STRIDE_EN_BB_SHIFT                                         31
+#define PCIEIP_REG_VENDOR_SPECIFIC_REG4_BB                                                                   0x000194UL //Access:R    DataWidth:0x20   // 
+#define PCIEIP_REG_SPCIE_CAP_HEADER_REG_K2_E5                                                                0x000198UL //Access:RW   DataWidth:0x20   // SPCIE Capability Header.
+  #define PCIEIP_REG_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_K2_E5                                              (0xffff<<0) // Secondary PCI Express Extended Capability ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_K2_E5_SHIFT                                        0
+  #define PCIEIP_REG_SPCIE_CAP_HEADER_REG_CAP_VERSION_K2_E5                                                  (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_SPCIE_CAP_HEADER_REG_CAP_VERSION_K2_E5_SHIFT                                            16
+  #define PCIEIP_REG_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_K2_E5                                                  (0xfff<<20) // Next Capability Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_K2_E5_SHIFT                                            20
+#define PCIEIP_REG_VENDOR_SPECIFIC_REG5_BB                                                                   0x000198UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_VENDOR_SPECIFIC_REG5_VF_BAR4_STRIDE_BITS_BB                                             (0x7fffffff<<0) // This field defines alignment and stride of VF BAR4 address space. The bits are a power of 2 value that multiplies the PF VF Bar4 value to compute the starting address and alignment of the BAR4 for each VF. This field may only have 1 bit set.This field is ignored when bit 31 is 0.
+  #define PCIEIP_REG_VENDOR_SPECIFIC_REG5_VF_BAR4_STRIDE_BITS_BB_SHIFT                                       0
+  #define PCIEIP_REG_VENDOR_SPECIFIC_REG5_VF_BAR4_STRIDE_EN_BB                                               (0x1<<31) // Enable VF Bar4 Stride. When this bit bit is clear, computation of the VF BAR4 offset from the PF SRIOV capability structure is unchanged.
+  #define PCIEIP_REG_VENDOR_SPECIFIC_REG5_VF_BAR4_STRIDE_EN_BB_SHIFT                                         31
+#define PCIEIP_REG_LINK_CONTROL3_REG_K2_E5                                                                   0x00019cUL //Access:R    DataWidth:0x20   // Link Control 3 Register.
+  #define PCIEIP_REG_LINK_CONTROL3_REG_PERFORM_EQ_K2_E5                                                      (0x1<<0) // Perform Equalization.   Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_LINK_CONTROL3_REG_PERFORM_EQ_K2_E5_SHIFT                                                0
+  #define PCIEIP_REG_LINK_CONTROL3_REG_EQ_REQ_INT_EN_K2_E5                                                   (0x1<<1) // Link Equalization Request Interrupt Enable.   Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_LINK_CONTROL3_REG_EQ_REQ_INT_EN_K2_E5_SHIFT                                             1
+#define PCIEIP_REG_LANE_ERR_STATUS_REG_K2_E5                                                                 0x0001a0UL //Access:RW   DataWidth:0x20   // Lane Error Status Register.
+  #define PCIEIP_REG_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_K2_E5                                               (0xff<<0) // Lane Error Status Bits per Lane.
+  #define PCIEIP_REG_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_K2_E5_SHIFT                                         0
+#define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_K2_E5                                                               0x0001a4UL //Access:R    DataWidth:0x20   // Lane Equalization Control Register for lanes 1 and 0.
+  #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_K2_E5                                              (0xf<<0) // Downstream Port 8.0 GT/s Transmitter Preset 0.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_K2_E5_SHIFT                                        0
+  #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_K2_E5                                         (0x7<<4) // Downstream Port 8.0 GT/s Receiver Preset Hint 0.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_K2_E5_SHIFT                                   4
+  #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_K2_E5                                              (0xf<<8) // Upstream Port 8.0 GT/s Transmitter Preset 0.  The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.   Note: The access attributes of this field are as follows:  - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS
+  #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_K2_E5_SHIFT                                        8
+  #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_K2_E5                                         (0x7<<12) // Upstream Port 8.0 GT/s Receiver Preset Hint 0.  The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.   Note: The access attributes of this field are as follows:  - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS
+  #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_K2_E5_SHIFT                                   12
+  #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_K2_E5                                              (0xf<<16) // Downstream Port 8.0 GT/s Transmitter Preset 1.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_K2_E5_SHIFT                                        16
+  #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_K2_E5                                         (0x7<<20) // Downstream Port 8.0 GT/s Receiver Preset Hint 1.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_K2_E5_SHIFT                                   20
+  #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_K2_E5                                              (0xf<<24) // Upstream Port 8.0 GT/s Transmitter Preset 1.  The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.   Note: The access attributes of this field are as follows:  - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS
+  #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_K2_E5_SHIFT                                        24
+  #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_K2_E5                                         (0x7<<28) // Upstream Port 8.0 GT/s Receiver Preset Hint 1.  The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.   Note: The access attributes of this field are as follows:  - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS
+  #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_K2_E5_SHIFT                                   28
+#define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_K2_E5                                                               0x0001a8UL //Access:R    DataWidth:0x20   // Lane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #2. The function of this register is dependent on your actual configuration.  - Gen3: LEC or RSVD depending on the value of CX_NL.  - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.
+  #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_K2_E5                                              (0xf<<0) // Downstream Port 8.0 GT/s Transmitter Preset2.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_K2_E5_SHIFT                                        0
+  #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_K2_E5                                         (0x7<<4) // Downstream Port 8.0 GT/s Receiver Preset Hint2.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_K2_E5_SHIFT                                   4
+  #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_K2_E5                                              (0xf<<8) // Upstream Port 8.0 GT/s Transmitter Preset2.  The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.   Note: The access attributes of this field are as follows:  - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS
+  #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_K2_E5_SHIFT                                        8
+  #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_K2_E5                                         (0x7<<12) // Upstream Port 8.0 GT/s Receiver Preset Hint2.  The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.   Note: The access attributes of this field are as follows:  - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS
+  #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_K2_E5_SHIFT                                   12
+  #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_K2_E5                                              (0xf<<16) // Downstream Port 8.0 GT/s Transmitter Preset3.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_K2_E5_SHIFT                                        16
+  #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_K2_E5                                         (0x7<<20) // Downstream Port 8.0 GT/s Receiver Preset Hint3.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_K2_E5_SHIFT                                   20
+  #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_K2_E5                                              (0xf<<24) // Upstream Port 8.0 GT/s Transmitter Preset3.  The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.   Note: The access attributes of this field are as follows:  - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS
+  #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_K2_E5_SHIFT                                        24
+  #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_K2_E5                                         (0x7<<28) // Upstream Port 8.0 GT/s Receiver Preset Hint3.  The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.   Note: The access attributes of this field are as follows:  - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS
+  #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_K2_E5_SHIFT                                   28
+#define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_K2_E5                                                               0x0001acUL //Access:R    DataWidth:0x20   // Lane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #4. The function of this register is dependent on your actual configuration.  - Gen3: LEC or RSVD depending on the value of CX_NL.  - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.
+  #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_K2_E5                                              (0xf<<0) // Downstream Port 8.0 GT/s Transmitter Preset4.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_K2_E5_SHIFT                                        0
+  #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_K2_E5                                         (0x7<<4) // Downstream Port 8.0 GT/s Receiver Preset Hint4.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_K2_E5_SHIFT                                   4
+  #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_K2_E5                                              (0xf<<8) // Upstream Port 8.0 GT/s Transmitter Preset4.  The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.   Note: The access attributes of this field are as follows:  - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS
+  #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_K2_E5_SHIFT                                        8
+  #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_K2_E5                                         (0x7<<12) // Upstream Port 8.0 GT/s Receiver Preset Hint4.  The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.   Note: The access attributes of this field are as follows:  - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS
+  #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_K2_E5_SHIFT                                   12
+  #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_K2_E5                                              (0xf<<16) // Downstream Port 8.0 GT/s Transmitter Preset5.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_K2_E5_SHIFT                                        16
+  #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_K2_E5                                         (0x7<<20) // Downstream Port 8.0 GT/s Receiver Preset Hint5.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_K2_E5_SHIFT                                   20
+  #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_K2_E5                                              (0xf<<24) // Upstream Port 8.0 GT/s Transmitter Preset5.  The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.   Note: The access attributes of this field are as follows:  - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS
+  #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_K2_E5_SHIFT                                        24
+  #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_K2_E5                                         (0x7<<28) // Upstream Port 8.0 GT/s Receiver Preset Hint5.  The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.   Note: The access attributes of this field are as follows:  - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS
+  #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_K2_E5_SHIFT                                   28
+#define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_K2_E5                                                               0x0001b0UL //Access:R    DataWidth:0x20   // Lane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #6. The function of this register is dependent on your actual configuration.  - Gen3: LEC or RSVD depending on the value of CX_NL.  - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.
+  #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_K2_E5                                              (0xf<<0) // Downstream Port 8.0 GT/s Transmitter Preset6.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_K2_E5_SHIFT                                        0
+  #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_K2_E5                                         (0x7<<4) // Downstream Port 8.0 GT/s Receiver Preset Hint6.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_K2_E5_SHIFT                                   4
+  #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_K2_E5                                              (0xf<<8) // Upstream Port 8.0 GT/s Transmitter Preset6.  The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.   Note: The access attributes of this field are as follows:  - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS
+  #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_K2_E5_SHIFT                                        8
+  #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_K2_E5                                         (0x7<<12) // Upstream Port 8.0 GT/s Receiver Preset Hint6.  The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.   Note: The access attributes of this field are as follows:  - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS
+  #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_K2_E5_SHIFT                                   12
+  #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_K2_E5                                              (0xf<<16) // Downstream Port 8.0 GT/s Transmitter Preset7.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_K2_E5_SHIFT                                        16
+  #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_K2_E5                                         (0x7<<20) // Downstream Port 8.0 GT/s Receiver Preset Hint7.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_K2_E5_SHIFT                                   20
+  #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_K2_E5                                              (0xf<<24) // Upstream Port 8.0 GT/s Transmitter Preset7.  The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.   Note: The access attributes of this field are as follows:  - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS
+  #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_K2_E5_SHIFT                                        24
+  #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_K2_E5                                         (0x7<<28) // Upstream Port 8.0 GT/s Receiver Preset Hint7.  The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.   Note: The access attributes of this field are as follows:  - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS
+  #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_K2_E5_SHIFT                                   28
+#define PCIEIP_REG_LTR_CAP_BB                                                                                0x0001b0UL //Access:R    DataWidth:0x20   // The read-only value of this register is controlled by setting bit 5 of the EXT_CAP_ENA for EP, By default, this capability is disabled (i.e. reading this register will return zeroes). The capability can be enabled by default by defining LTR_ENABLED in version.v and setting bit 5 of EXT_CAP_ENA. This capability when present , will only exist in function 0 of a multi-function device.
+  #define PCIEIP_REG_LTR_CAP_LTR_EXT_CAP_ID_BB                                                               (0xffff<<0) // Vendor Specific Extended Capability ID.
+  #define PCIEIP_REG_LTR_CAP_LTR_EXT_CAP_ID_BB_SHIFT                                                         0
+  #define PCIEIP_REG_LTR_CAP_CAP_VER_BB                                                                      (0xf<<16) // LTR Capability version. Hardwired to 0x1.
+  #define PCIEIP_REG_LTR_CAP_CAP_VER_BB_SHIFT                                                                16
+  #define PCIEIP_REG_LTR_CAP_NEXT_BB                                                                         (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability.
+  #define PCIEIP_REG_LTR_CAP_NEXT_BB_SHIFT                                                                   20
+#define PCIEIP_REG_LATENCY_REGISTER_BB                                                                       0x0001b4UL //Access:RW   DataWidth:0x20   // The RW value of this register is controlled by setting bit 5 of the EXT_CAP_ENA for EP. By default, this capability is disabled (i.e. reading this register will return zeroes).
+  #define PCIEIP_REG_LATENCY_REGISTER_MAX_SNOOP_LATE_VALUE_BB                                                (0x3ff<<0) // Max Snoop Latency Value. Along with Max snoop latency scale field, this register specifies the maximum no-snoop latency that a device is premitted to request. Software should set this to the platforms max supported latency or less.
+  #define PCIEIP_REG_LATENCY_REGISTER_MAX_SNOOP_LATE_VALUE_BB_SHIFT                                          0
+  #define PCIEIP_REG_LATENCY_REGISTER_MAX_SNOOP_LATE_SCALE_BB                                                (0x7<<10) // Max Snoop Latency Scale. This register provides a scale for the value contained within the max_snoop_late_value field.
+  #define PCIEIP_REG_LATENCY_REGISTER_MAX_SNOOP_LATE_SCALE_BB_SHIFT                                          10
+  #define PCIEIP_REG_LATENCY_REGISTER_UNUSED0_BB                                                             (0x7<<13) // 
+  #define PCIEIP_REG_LATENCY_REGISTER_UNUSED0_BB_SHIFT                                                       13
+  #define PCIEIP_REG_LATENCY_REGISTER_MAX_NO_SNOOP_LATE_VALUE_BB                                             (0x3ff<<16) // Max No Snoop Latency Value. Along with Max No snoop latency scale field, this register specifies the maximum no-snoop latency that a device is premitted to request. Software should set this to the platforms max supported latency or less.
+  #define PCIEIP_REG_LATENCY_REGISTER_MAX_NO_SNOOP_LATE_VALUE_BB_SHIFT                                       16
+  #define PCIEIP_REG_LATENCY_REGISTER_MAX_NO_SNOOP_LATE_SCALE_BB                                             (0x7<<26) // Max No Snoop Latency Scale. This register provides a scale for the value contained within the max_no_snoop_late_value field.
+  #define PCIEIP_REG_LATENCY_REGISTER_MAX_NO_SNOOP_LATE_SCALE_BB_SHIFT                                       26
+#define PCIEIP_REG_SRIOV_BASE_REG_K2_E5                                                                      0x0001b8UL //Access:RW   DataWidth:0x20   // SR-IOV Capability Header. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
+  #define PCIEIP_REG_SRIOV_BASE_REG_SRIOV_PCIE_EXTENDED_CAP_ID_K2_E5                                         (0xffff<<0) // SRIOV Extended Capability ID. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_SRIOV_BASE_REG_SRIOV_PCIE_EXTENDED_CAP_ID_K2_E5_SHIFT                                   0
+  #define PCIEIP_REG_SRIOV_BASE_REG_SRIOV_CAP_VERSION_K2_E5                                                  (0xf<<16) // Capability Version. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_SRIOV_BASE_REG_SRIOV_CAP_VERSION_K2_E5_SHIFT                                            16
+  #define PCIEIP_REG_SRIOV_BASE_REG_SRIOV_NEXT_OFFSET_K2_E5                                                  (0xfff<<20) // Next Capability Offset. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_SRIOV_BASE_REG_SRIOV_NEXT_OFFSET_K2_E5_SHIFT                                            20
+#define PCIEIP_REG_ARI_CAP_BB                                                                                0x0001b8UL //Access:R    DataWidth:0x20   // The read-only value of this register is controlled by setting bit 6 of the EXT_CAP_ENA for EP, The capability can be enabled by default by defining SRIOV in version.v .
+  #define PCIEIP_REG_ARI_CAP_ARI_EXT_CAP_ID_BB                                                               (0xffff<<0) // ARI Extended Capability ID. Hardwired to 0xE.
+  #define PCIEIP_REG_ARI_CAP_ARI_EXT_CAP_ID_BB_SHIFT                                                         0
+  #define PCIEIP_REG_ARI_CAP_CAP_VER_BB                                                                      (0xf<<16) // ARI Capability version. Hardwired to 0x1.
+  #define PCIEIP_REG_ARI_CAP_CAP_VER_BB_SHIFT                                                                16
+  #define PCIEIP_REG_ARI_CAP_NEXT_BB                                                                         (0xfff<<20) // 
+  #define PCIEIP_REG_ARI_CAP_NEXT_BB_SHIFT                                                                   20
+#define PCIEIP_REG_CAPABILITIES_REG_K2_E5                                                                    0x0001bcUL //Access:RW   DataWidth:0x20   // SR-IOV Capability Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
+  #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_VF_MIGRATION_CAP_K2_E5                                           (0x1<<0) // VF Migration Capable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
+  #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_VF_MIGRATION_CAP_K2_E5_SHIFT                                     0
+  #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_ARI_CAP_HIER_PRESERVED_K2_E5                                     (0x1<<1) // ARI Capable Hierarchy Preserved. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_ARI_CAP_HIER_PRESERVED_K2_E5_SHIFT                               1
+  #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_VF_MIGRATION_INT_MSG_NUM_K2_E5                                   (0x3ff<<21) // VF Migration Interrupt Message Number. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
+  #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_VF_MIGRATION_INT_MSG_NUM_K2_E5_SHIFT                             21
+#define PCIEIP_REG_ARI_CONTROL_REGISTER_BB                                                                   0x0001bcUL //Access:R    DataWidth:0x20   // The RW value of this register is controlled by setting bit 6 of the EXT_CAP_ENA for EP. By default, this capability is disabled (i.e. reading this register will return zeroes).
+  #define PCIEIP_REG_ARI_CONTROL_REGISTER_MFVC_FUNC_GROUP_CAP_BB                                             (0x1<<0) // Hardwired to 0
+  #define PCIEIP_REG_ARI_CONTROL_REGISTER_MFVC_FUNC_GROUP_CAP_BB_SHIFT                                       0
+  #define PCIEIP_REG_ARI_CONTROL_REGISTER_ACS_FUNC_GROUP_CAP_BB                                              (0x1<<1) // Hardwired to 0
+  #define PCIEIP_REG_ARI_CONTROL_REGISTER_ACS_FUNC_GROUP_CAP_BB_SHIFT                                        1
+  #define PCIEIP_REG_ARI_CONTROL_REGISTER_UNUSED0_BB                                                         (0x3f<<2) // 
+  #define PCIEIP_REG_ARI_CONTROL_REGISTER_UNUSED0_BB_SHIFT                                                   2
+  #define PCIEIP_REG_ARI_CONTROL_REGISTER_NEXT_FUNCTION_NUMBER_BB                                            (0xff<<8) // Next Function Number. This field indicates the function number of the next higher numbered function in device. Value reflects programming in ARI_CAP(0x5FC) private register.
+  #define PCIEIP_REG_ARI_CONTROL_REGISTER_NEXT_FUNCTION_NUMBER_BB_SHIFT                                      8
+  #define PCIEIP_REG_ARI_CONTROL_REGISTER_ARI_CTRL_BB                                                        (0xffff<<16) // Field is unused and is hardwired to 0.
+  #define PCIEIP_REG_ARI_CONTROL_REGISTER_ARI_CTRL_BB_SHIFT                                                  16
+#define PCIEIP_REG_STATUS_CONTROL_REG_K2_E5                                                                  0x0001c0UL //Access:RW   DataWidth:0x20   // SR-IOV Control and Status Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
+  #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_ENABLE_K2_E5                                                (0x1<<0) // VF Enable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
+  #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_ENABLE_K2_E5_SHIFT                                          0
+  #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MIGRATION_ENABLE_K2_E5                                      (0x1<<1) // VF Migration Enable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
+  #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MIGRATION_ENABLE_K2_E5_SHIFT                                1
+  #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MIGRATION_INT_ENABLE_K2_E5                                  (0x1<<2) // VF Migration Interrupt Enable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
+  #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MIGRATION_INT_ENABLE_K2_E5_SHIFT                            2
+  #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MSE_K2_E5                                                   (0x1<<3) // VF Memory Space Enable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
+  #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MSE_K2_E5_SHIFT                                             3
+  #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_ARI_CAPABLE_HIER_K2_E5                                         (0x1<<4) // ARI Capable Hierarchy (Applies to endpoint only). For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: R/W but read-value is not always same as write-value
+  #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_ARI_CAPABLE_HIER_K2_E5_SHIFT                                   4
+#define PCIEIP_REG_SRIOV_CAP_BB                                                                              0x0001c0UL //Access:R    DataWidth:0x20   // The read-only value of this register is controlled by setting bit 7 of the EXT_CAP_ENA for EP, The capability can be enabled by default by defining SRIOV in version.v .
+  #define PCIEIP_REG_SRIOV_CAP_SRIOV_EXT_CAP_ID_BB                                                           (0xffff<<0) // SRIOV Extended Capability ID. Hardwired to 0xE.
+  #define PCIEIP_REG_SRIOV_CAP_SRIOV_EXT_CAP_ID_BB_SHIFT                                                     0
+  #define PCIEIP_REG_SRIOV_CAP_SRCAP_VER_BB                                                                  (0xf<<16) // SRIOV Capability version. Hardwired to 0x1.
+  #define PCIEIP_REG_SRIOV_CAP_SRCAP_VER_BB_SHIFT                                                            16
+  #define PCIEIP_REG_SRIOV_CAP_NEXT_BB                                                                       (0xfff<<20) // 
+  #define PCIEIP_REG_SRIOV_CAP_NEXT_BB_SHIFT                                                                 20
+#define PCIEIP_REG_SRIOV_INITIAL_VFS_K2_E5                                                                   0x0001c4UL //Access:RW   DataWidth:0x20   // TotalVFs InitialVFs Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
+  #define PCIEIP_REG_SRIOV_INITIAL_VFS_SRIOV_INITIAL_VFS_K2_E5                                               (0xffff<<0) // InitialVFs. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two InitialVFs registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_SRIOV_INITIAL_VFS_SRIOV_INITIAL_VFS_K2_E5_SHIFT                                         0
+  #define PCIEIP_REG_SRIOV_INITIAL_VFS_SRIOV_TOTAL_VFS_K2_E5                                                 (0xffff<<16) // Total VFs (Max Number of VFs). For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
+  #define PCIEIP_REG_SRIOV_INITIAL_VFS_SRIOV_TOTAL_VFS_K2_E5_SHIFT                                           16
+#define PCIEIP_REG_SRIOV_CAPABILITIES_BB                                                                     0x0001c4UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_SRIOV_CAPABILITIES_UNUSED_1A_BB                                                         (0x1<<0) // The capability is hardwired to 0.
+  #define PCIEIP_REG_SRIOV_CAPABILITIES_UNUSED_1A_BB_SHIFT                                                   0
+  #define PCIEIP_REG_SRIOV_CAPABILITIES_ARI_CAP_HIER_PRESERVED_BB                                            (0x1<<1) // This field is only present in PF0. This bet when set indicates that the ARI capable hierarchy is preserved across certain power state transitions.
+  #define PCIEIP_REG_SRIOV_CAPABILITIES_ARI_CAP_HIER_PRESERVED_BB_SHIFT                                      1
+  #define PCIEIP_REG_SRIOV_CAPABILITIES_UNUSED_1_BB                                                          (0x3fffffff<<2) // The capability is hardwired to 0.
+  #define PCIEIP_REG_SRIOV_CAPABILITIES_UNUSED_1_BB_SHIFT                                                    2
+#define PCIEIP_REG_SRIOV_NUM_VFS_K2_E5                                                                       0x0001c8UL //Access:RW   DataWidth:0x20   // NumVFs and Function Dependency Link Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two of these registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address.
+  #define PCIEIP_REG_SRIOV_NUM_VFS_SRIOV_NUM_VFS_K2_E5                                                       (0xffff<<0) // Number of Visible VFs. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: STATUS_CONTROL_REG.SRIOV_VF_ENABLE ? RW : RO
+  #define PCIEIP_REG_SRIOV_NUM_VFS_SRIOV_NUM_VFS_K2_E5_SHIFT                                                 0
+  #define PCIEIP_REG_SRIOV_NUM_VFS_SRIOV_FDL_K2_E5                                                           (0xff<<16) // Functional Dependency Link. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
+  #define PCIEIP_REG_SRIOV_NUM_VFS_SRIOV_FDL_K2_E5_SHIFT                                                     16
+#define PCIEIP_REG_SRIOV_CONTROL_BB                                                                          0x0001c8UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_SRIOV_CONTROL_VF_ENABLE_BB                                                              (0x1<<0) // Enables/Disables VFs.
+  #define PCIEIP_REG_SRIOV_CONTROL_VF_ENABLE_BB_SHIFT                                                        0
+  #define PCIEIP_REG_SRIOV_CONTROL_VF_MIG_EN_BB                                                              (0x1<<1) // 
+  #define PCIEIP_REG_SRIOV_CONTROL_VF_MIG_EN_BB_SHIFT                                                        1
+  #define PCIEIP_REG_SRIOV_CONTROL_VF_MIG_INTERR_EN_BB                                                       (0x1<<2) // This bit has no effect in IP. However spec has defined it to be RW.
+  #define PCIEIP_REG_SRIOV_CONTROL_VF_MIG_INTERR_EN_BB_SHIFT                                                 2
+  #define PCIEIP_REG_SRIOV_CONTROL_VF_MSE_BB                                                                 (0x1<<3) // When set, memory space is enabled for VFs.
+  #define PCIEIP_REG_SRIOV_CONTROL_VF_MSE_BB_SHIFT                                                           3
+  #define PCIEIP_REG_SRIOV_CONTROL_ARI_CAPABLE_HIER_BB                                                       (0x1<<4) // When set, the device is permitted to locate VF in Func Number 8 to 255. This field is RW only in PF0 and is RO in all other PFs.
+  #define PCIEIP_REG_SRIOV_CONTROL_ARI_CAPABLE_HIER_BB_SHIFT                                                 4
+  #define PCIEIP_REG_SRIOV_CONTROL_UNUSED_2_BB                                                               (0x7ff<<5) // The Status is hardwired to 0.
+  #define PCIEIP_REG_SRIOV_CONTROL_UNUSED_2_BB_SHIFT                                                         5
+  #define PCIEIP_REG_SRIOV_CONTROL_SRIOV_STATUS_BB                                                           (0xffff<<16) // The Status is hardwired to 0.
+  #define PCIEIP_REG_SRIOV_CONTROL_SRIOV_STATUS_BB_SHIFT                                                     16
+#define PCIEIP_REG_SRIOV_VF_OFFSET_POSITION_K2_E5                                                            0x0001ccUL //Access:RW   DataWidth:0x20   // VF Stride and Offset Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
+  #define PCIEIP_REG_SRIOV_VF_OFFSET_POSITION_SRIOV_VF_OFFSET_K2_E5                                          (0xffff<<0) // First VF Offset. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two First VF Offset registers at this address location; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit of the PF0 "SR-IOV Control Register" determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_SRIOV_VF_OFFSET_POSITION_SRIOV_VF_OFFSET_K2_E5_SHIFT                                    0
+  #define PCIEIP_REG_SRIOV_VF_OFFSET_POSITION_SRIOV_VF_STRIDE_K2_E5                                          (0xffff<<16) // VF Stride. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two VF Stride registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit of the PF0 "SR-IOV Control Register". determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_SRIOV_VF_OFFSET_POSITION_SRIOV_VF_STRIDE_K2_E5_SHIFT                                    16
+#define PCIEIP_REG_SRIOV_INITIALVF_BB                                                                        0x0001ccUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_SRIOV_INITIALVF_INITIALVF_BB                                                            (0xffff<<0) // The Value in this register is based on programming in the private space at 0x600. This field indicates the number of VFs that are initially associated with the PF.
+  #define PCIEIP_REG_SRIOV_INITIALVF_INITIALVF_BB_SHIFT                                                      0
+  #define PCIEIP_REG_SRIOV_INITIALVF_TOTALVF_BB                                                              (0xffff<<16) // The Value in this register is based on programming in the private space at 0x600. This field indicates the maximum number of VFs that could be associated with PF.
+  #define PCIEIP_REG_SRIOV_INITIALVF_TOTALVF_BB_SHIFT                                                        16
+#define PCIEIP_REG_VF_DEVICE_ID_REG_K2_E5                                                                    0x0001d0UL //Access:RW   DataWidth:0x20   // VF Device ID For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
+  #define PCIEIP_REG_VF_DEVICE_ID_REG_SRIOV_VF_DEVICE_ID_K2_E5                                               (0xffff<<16) // VF Device ID. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_VF_DEVICE_ID_REG_SRIOV_VF_DEVICE_ID_K2_E5_SHIFT                                         16
+#define PCIEIP_REG_SRIOV_NUMVF_BB                                                                            0x0001d0UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_SRIOV_NUMVF_NUMVF_BB                                                                    (0xffff<<0) // This field controls the number of VFs that are available. S/W sets this as part of creating VF.
+  #define PCIEIP_REG_SRIOV_NUMVF_NUMVF_BB_SHIFT                                                              0
+  #define PCIEIP_REG_SRIOV_NUMVF_FUNC_DEPENDENCY_LINK_BB                                                     (0xff<<16) // The Value in this register is based on programming in the private space at 0x608.
+  #define PCIEIP_REG_SRIOV_NUMVF_FUNC_DEPENDENCY_LINK_BB_SHIFT                                               16
+  #define PCIEIP_REG_SRIOV_NUMVF_RSVD_1_BB                                                                   (0xff<<24) // 
+  #define PCIEIP_REG_SRIOV_NUMVF_RSVD_1_BB_SHIFT                                                             24
+#define PCIEIP_REG_SUP_PAGE_SIZES_REG_K2_E5                                                                  0x0001d4UL //Access:RW   DataWidth:0x20   // Supported Page Sizes.
+#define PCIEIP_REG_SRIOV_VFOFFSET_BB                                                                         0x0001d4UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_SRIOV_VFOFFSET_VF_OFFSET_BB                                                             (0xffff<<0) // The value in this register is based on programming in private space at 0x604. This field defines the Routing ID offset of the first VF associated with the PF. The First VFs RID is calculated by adding this field to the RID of the PF.
+  #define PCIEIP_REG_SRIOV_VFOFFSET_VF_OFFSET_BB_SHIFT                                                       0
+  #define PCIEIP_REG_SRIOV_VFOFFSET_VF_STRIDE_BB                                                             (0xffff<<16) // This field is hardwired to 1.
+  #define PCIEIP_REG_SRIOV_VFOFFSET_VF_STRIDE_BB_SHIFT                                                       16
+#define PCIEIP_REG_SYSTEM_PAGE_SIZE_REG_K2_E5                                                                0x0001d8UL //Access:RW   DataWidth:0x20   // System Page Size.
+#define PCIEIP_REG_SRIOV_VF_DEVICEID_BB                                                                      0x0001d8UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_SRIOV_VF_DEVICEID_RESERVED_BB                                                           (0xffff<<0) // 
+  #define PCIEIP_REG_SRIOV_VF_DEVICEID_RESERVED_BB_SHIFT                                                     0
+  #define PCIEIP_REG_SRIOV_VF_DEVICEID_VF_DEVICEID_BB                                                        (0xffff<<16) // The value in this register is based on programming in private space at 0x604. This field contains Device ID for every VF belonging to this PF.
+  #define PCIEIP_REG_SRIOV_VF_DEVICEID_VF_DEVICEID_BB_SHIFT                                                  16
+#define PCIEIP_REG_SRIOV_BAR0_REG_K2_E5                                                                      0x0001dcUL //Access:RW   DataWidth:0x20   // VF BAR0. This register is used to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the core from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. For a fuller description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_TYPE_K2_E5                                                 (0x3<<1) // VF BAR0 32 or 64 bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_TYPE_K2_E5_SHIFT                                           1
+  #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_PREFETCH_K2_E5                                             (0x1<<3) // VF BAR0 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_PREFETCH_K2_E5_SHIFT                                       3
+  #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_START_K2_E5                                                (0xfffffff<<4) // VF BAR0 Base Address. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_START_K2_E5_SHIFT                                          4
+#define PCIEIP_REG_SRIOV_SUPPORTEDPAGESIZE_BB                                                                0x0001dcUL //Access:R    DataWidth:0x20   // This value in this register is based on programming in private space at 0x60C. Default indicates support from 4K to 4M.
+#define PCIEIP_REG_SRIOV_BAR1_REG_K2_E5                                                                      0x0001e0UL //Access:RW   DataWidth:0x20   // VF BAR1. This register is used to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the core from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. For a fuller description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_TYPE_K2_E5                                                 (0x3<<1) // VF BAR1 32 or 64 bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_TYPE_K2_E5_SHIFT                                           1
+  #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_PREFETCH_K2_E5                                             (0x1<<3) // VF BAR1 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_PREFETCH_K2_E5_SHIFT                                       3
+  #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_START_K2_E5                                                (0xfffffff<<4) // VF BAR1 Base Address. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_START_K2_E5_SHIFT                                          4
+#define PCIEIP_REG_SRIOV_SYSTEMPAGESIZE_BB                                                                   0x0001e0UL //Access:RW   DataWidth:0x20   // Default value is 4K . This field defines the page size system will use to map VFs mem address.
+#define PCIEIP_REG_SRIOV_BAR2_REG_K2_E5                                                                      0x0001e4UL //Access:RW   DataWidth:0x20   // VF BAR2. This register is used to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the core from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. For a fuller description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_TYPE_K2_E5                                                 (0x3<<1) // VF BAR2 32 or 64 bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_TYPE_K2_E5_SHIFT                                           1
+  #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_PREFETCH_K2_E5                                             (0x1<<3) // VF BAR2 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_PREFETCH_K2_E5_SHIFT                                       3
+  #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_START_K2_E5                                                (0xfffffff<<4) // VF BAR2 Base Address. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_START_K2_E5_SHIFT                                          4
+#define PCIEIP_REG_VF_BAR0_BB                                                                                0x0001e4UL //Access:RW   DataWidth:0x20   // The 32-bit VF_BAR0 register programs the base address for the memory space mapped by the VFs belonging to this PF. This register can be combined with VF_BAR2 to make a 64-bit address. Each VF BAR describes the amount of address space consumed by a single VF. Path = i_cfg_func.i_cfg_public.i_cfg_dec
+  #define PCIEIP_REG_VF_BAR0_MEM_SPACE_BB                                                                    (0x1<<0) // This bit indicates that VF_BAR0 maps a memory space and is always read as 0.
+  #define PCIEIP_REG_VF_BAR0_MEM_SPACE_BB_SHIFT                                                              0
+  #define PCIEIP_REG_VF_BAR0_SPACE_TYPE_BB                                                                   (0x3<<1) // These bits indicate that VF_BAR0 may be programmed to map this adapter to anywhere in the 64-bit address space. Bit can be programmed from shadow register(reg 0x608).
+  #define PCIEIP_REG_VF_BAR0_SPACE_TYPE_BB_SHIFT                                                             1
+  #define PCIEIP_REG_VF_BAR0_VF_PREFETCH_BB                                                                  (0x1<<3) // This bit indicates that the area mapped by VF_BAR0 may be pre-fetched or cached by the system without side effects. Bit can be programmed from shadow register(reg 0x608).
+  #define PCIEIP_REG_VF_BAR0_VF_PREFETCH_BB_SHIFT                                                            3
+  #define PCIEIP_REG_VF_BAR0_UNUSED0_BB                                                                      (0xff<<4) // 
+  #define PCIEIP_REG_VF_BAR0_UNUSED0_BB_SHIFT                                                                4
+  #define PCIEIP_REG_VF_BAR0_ADDRESS_BB                                                                      (0xfffff<<12) // These bits set the address within a 32-bit address space that device will respond in. These bits may be combined with the bits in VF_BAR1 to create a full 64 bit address decode. Only the bits that addresses blocks bigger than the setting in the VFBAR0_SIZE(reg 0x608) value are RW. All lower bits are RO with a value of zero. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_VF_BAR0_ADDRESS_BB_SHIFT                                                                12
+#define PCIEIP_REG_SRIOV_BAR3_REG_K2_E5                                                                      0x0001e8UL //Access:RW   DataWidth:0x20   // VF BAR3. This register is used to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the core from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. For a fuller description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_TYPE_K2_E5                                                 (0x3<<1) // VF BAR3 32 or 64 bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_TYPE_K2_E5_SHIFT                                           1
+  #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_PREFETCH_K2_E5                                             (0x1<<3) // VF BAR3 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_PREFETCH_K2_E5_SHIFT                                       3
+  #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_START_K2_E5                                                (0xfffffff<<4) // VF BAR3 Base Address. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_START_K2_E5_SHIFT                                          4
+#define PCIEIP_REG_VF_BAR1_BB                                                                                0x0001e8UL //Access:RW   DataWidth:0x20   // The 32-bit VF_BAR1 register programs the upper half of the base address for the memory space mapped by the card onto the PCI bus.
+#define PCIEIP_REG_SRIOV_BAR4_REG_K2_E5                                                                      0x0001ecUL //Access:RW   DataWidth:0x20   // VF BAR4. This register is used to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the core from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. For a fuller description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_TYPE_K2_E5                                                 (0x3<<1) // VF BAR4 32 or 64 bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_TYPE_K2_E5_SHIFT                                           1
+  #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_PREFETCH_K2_E5                                             (0x1<<3) // VF BAR4 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_PREFETCH_K2_E5_SHIFT                                       3
+  #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_START_K2_E5                                                (0xfffff<<4) // VF BAR4 Base Address. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_START_K2_E5_SHIFT                                          4
+#define PCIEIP_REG_VF_BAR2_BB                                                                                0x0001ecUL //Access:RW   DataWidth:0x20   // The 32-bit VF_BAR2 register programs the base address for the memory space mapped by the VFs belonging to this PF. This register can be combined with VF_BAR3 to make a 64-bit address. Each VF BAR describes the amount of address space consumed by a single VF. Path = i_cfg_func.i_cfg_public.i_cfg_dec
+  #define PCIEIP_REG_VF_BAR2_MEM_SPACE_BB                                                                    (0x1<<0) // This bit indicates that VF_BAR2 maps a memory space and is always read as 0.
+  #define PCIEIP_REG_VF_BAR2_MEM_SPACE_BB_SHIFT                                                              0
+  #define PCIEIP_REG_VF_BAR2_SPACE_TYPE_BB                                                                   (0x3<<1) // These bits indicate that VF_BAR2 may be programmed to map this adapter to anywhere in the 64-bit address space(reg 0x608).
+  #define PCIEIP_REG_VF_BAR2_SPACE_TYPE_BB_SHIFT                                                             1
+  #define PCIEIP_REG_VF_BAR2_VF_PREFETCH_BB                                                                  (0x1<<3) // This bit indicates that the area mapped by VF_BAR2 may be pre-fetched or cached by the system without side effects. Bit can be programmed from shadow register(reg 0x608).
+  #define PCIEIP_REG_VF_BAR2_VF_PREFETCH_BB_SHIFT                                                            3
+  #define PCIEIP_REG_VF_BAR2_UNUSED0_BB                                                                      (0xff<<4) // 
+  #define PCIEIP_REG_VF_BAR2_UNUSED0_BB_SHIFT                                                                4
+  #define PCIEIP_REG_VF_BAR2_ADDRESS_BB                                                                      (0xfffff<<12) // These bits set the address within a 32-bit address space that device will respond in. These bits may be combined with the bits in VF_BAR3 to create a full 64 bit address decode. Only the bits that addresses blocks bigger than the setting in the VFBAR2_SIZE(reg 0x608) value are RW. All lower bits are RO with a value of zero. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_VF_BAR2_ADDRESS_BB_SHIFT                                                                12
+#define PCIEIP_REG_SRIOV_BAR5_REG_K2_E5                                                                      0x0001f0UL //Access:RW   DataWidth:0x20   // VF BAR5. This register is used to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the core from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. For a fuller description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_TYPE_K2_E5                                                 (0x3<<1) // VF BAR5 32 or 64 bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_TYPE_K2_E5_SHIFT                                           1
+  #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_PREFETCH_K2_E5                                             (0x1<<3) // VF BAR5 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_PREFETCH_K2_E5_SHIFT                                       3
+  #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_START_K2_E5                                                (0xfffffff<<4) // VF BAR5 Base Address. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_START_K2_E5_SHIFT                                          4
+#define PCIEIP_REG_VF_BAR3_BB                                                                                0x0001f0UL //Access:RW   DataWidth:0x20   // The 32-bit VF_BAR3 register programs the upper half of the base address for the memory space mapped by the card onto the PCI bus.
+#define PCIEIP_REG_VF_MIGRATION_STATE_ARRAY_REG_K2_E5                                                        0x0001f4UL //Access:R    DataWidth:0x20   // VF Migration State Array Offset For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
+  #define PCIEIP_REG_VF_MIGRATION_STATE_ARRAY_REG_SRIOV_VF_MIGRATION_STATE_BIR_K2_E5                         (0x7<<0) // VF Migration State BIR. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
+  #define PCIEIP_REG_VF_MIGRATION_STATE_ARRAY_REG_SRIOV_VF_MIGRATION_STATE_BIR_K2_E5_SHIFT                   0
+  #define PCIEIP_REG_VF_MIGRATION_STATE_ARRAY_REG_SRIOV_VF_MIGRATION_STATE_OFFSET_K2_E5                      (0x1fffffff<<3) // VF Migration State Offset. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
+  #define PCIEIP_REG_VF_MIGRATION_STATE_ARRAY_REG_SRIOV_VF_MIGRATION_STATE_OFFSET_K2_E5_SHIFT                3
+#define PCIEIP_REG_VF_BAR4_BB                                                                                0x0001f4UL //Access:RW   DataWidth:0x20   // The 32-bit VF_BAR4 register programs the base address for the memory space mapped by the VFs belonging to this PF. This register can be combined with VF_BAR5 to make a 64-bit address. Each VF BAR describes the amount of address space consumed by a single VF. Path = i_cfg_func.i_cfg_public.i_cfg_dec
+  #define PCIEIP_REG_VF_BAR4_MEM_SPACE_BB                                                                    (0x1<<0) // This bit indicates that VF_BAR4 maps a memory space and is always read as 0.
+  #define PCIEIP_REG_VF_BAR4_MEM_SPACE_BB_SHIFT                                                              0
+  #define PCIEIP_REG_VF_BAR4_SPACE_TYPE_BB                                                                   (0x3<<1) // These bits indicate that VF_BAR4 may be programmed to map this adapter to anywhere in the 64-bit address space(reg 0x620).
+  #define PCIEIP_REG_VF_BAR4_SPACE_TYPE_BB_SHIFT                                                             1
+  #define PCIEIP_REG_VF_BAR4_VF_PREFETCH_BB                                                                  (0x1<<3) // This bit indicates that the area mapped by VF_BAR4 may be pre-fetched or cached by the system without side effects. Bit can be programmed from shadow register(reg 0x620).
+  #define PCIEIP_REG_VF_BAR4_VF_PREFETCH_BB_SHIFT                                                            3
+  #define PCIEIP_REG_VF_BAR4_UNUSED0_BB                                                                      (0xff<<4) // 
+  #define PCIEIP_REG_VF_BAR4_UNUSED0_BB_SHIFT                                                                4
+  #define PCIEIP_REG_VF_BAR4_ADDRESS_BB                                                                      (0xfffff<<12) // These bits set the address within a 32-bit address space that device will respond in. These bits may be combined with the bits in VF_BAR5 to create a full 64 bit address decode. Only the bits that addresses blocks bigger than the setting in the VFBAR4_SIZE(reg 0x620) value are RW. All lower bits are RO with a value of zero. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_VF_BAR4_ADDRESS_BB_SHIFT                                                                12
+#define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_K2_E5                                                                 0x0001f8UL //Access:RW   DataWidth:0x20   // TPH Extended Capability Header.
+  #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_K2_E5                                               (0xffff<<0) // TPH Extended Capability ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_K2_E5_SHIFT                                         0
+  #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_K2_E5                                               (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_K2_E5_SHIFT                                         16
+  #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_K2_E5                                              (0xfff<<20) // Next Capability Pointer.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_K2_E5_SHIFT                                        20
+#define PCIEIP_REG_VF_BAR5_BB                                                                                0x0001f8UL //Access:RW   DataWidth:0x20   // The 32-bit VF_BAR5 register programs the upper half of the base address for the memory space mapped by the card onto the PCI bus.
+#define PCIEIP_REG_TPH_REQ_CAP_REG_REG_K2_E5                                                                 0x0001fcUL //Access:RW   DataWidth:0x20   // TPH Requestor Capability Register.   SRIOV Note: All VFs in a single PF have the same values for VF_TPH_REQ_CAP_REG_REG. To write this common register, you must perform a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PF TPH_REQ_CAP_REG_REG register.
+  #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_K2_E5                                            (0x1<<0) // No ST Mode Supported.
+  #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_K2_E5_SHIFT                                      0
+  #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_K2_E5                                           (0x1<<1) // Interrupt Vector Mode Supported.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_K2_E5_SHIFT                                     1
+  #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_K2_E5                                           (0x1<<2) // Device Specific Mode Supported.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_K2_E5_SHIFT                                     2
+  #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_K2_E5                                          (0x1<<8) // Extended TPH Requester Supported.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_K2_E5_SHIFT                                    8
+  #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_K2_E5                                    (0x1<<9) // ST Table Location Bit 0.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_K2_E5_SHIFT                              9
+  #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_K2_E5                                    (0x1<<10) // ST Table Location Bit 1.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_K2_E5_SHIFT                              10
+  #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_K2_E5                                     (0x7ff<<16) // ST Table Size.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R  Note: This register field is sticky.
+  #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_K2_E5_SHIFT                               16
+#define PCIEIP_REG_TPH_REQ_CONTROL_REG_REG_K2_E5                                                             0x000200UL //Access:RW   DataWidth:0x20   // TPH Requestor Control Register.
+  #define PCIEIP_REG_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_K2_E5                                    (0x7<<0) // ST Mode Select.   Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_K2_E5_SHIFT                              0
+  #define PCIEIP_REG_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_K2_E5                                       (0x3<<8) // TPH Requester Enable Bit.
+  #define PCIEIP_REG_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_K2_E5_SHIFT                                 8
+#define PCIEIP_REG_PTM_EXTENDED_CAP_BB                                                                       0x000200UL //Access:R    DataWidth:0x20   // The read-only value of this register is controlled by setting bit 0 of the EXT3_CAP_ENA for EP, The capability can be enabled by default by defining PCIE_PTM_SUPP in version.v and setting bit 0 of EXT3_CAP_ENA.
+  #define PCIEIP_REG_PTM_EXTENDED_CAP_PTM_EXT_CAP_ID_BB                                                      (0xffff<<0) // Vendor Specific Extended Capability ID.
+  #define PCIEIP_REG_PTM_EXTENDED_CAP_PTM_EXT_CAP_ID_BB_SHIFT                                                0
+  #define PCIEIP_REG_PTM_EXTENDED_CAP_CAP_VER_BB                                                             (0xf<<16) // PTM Capability version. Hardwired to 0x1.
+  #define PCIEIP_REG_PTM_EXTENDED_CAP_CAP_VER_BB_SHIFT                                                       16
+  #define PCIEIP_REG_PTM_EXTENDED_CAP_NEXT_BB                                                                (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability.
+  #define PCIEIP_REG_PTM_EXTENDED_CAP_NEXT_BB_SHIFT                                                          20
+#define PCIEIP_REG_TPH_ST_TABLE_REG_0_K2_E5                                                                  0x000204UL //Access:RW   DataWidth:0x20   // TPH ST Table Register 0.
+  #define PCIEIP_REG_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_K2_E5                                       (0xff<<0) // ST Table 0 Lower Byte.   Note: The access attributes of this field are as follows:  - Dbi: this field is RW or Tie to 0 by table size configure
+  #define PCIEIP_REG_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_K2_E5_SHIFT                                 0
+  #define PCIEIP_REG_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_K2_E5                                      (0xff<<8) // ST Table 0 Upper Byte.   Note: The access attributes of this field are as follows:  - Dbi: this field is RW or Tie to 0 by table size configure
+  #define PCIEIP_REG_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_K2_E5_SHIFT                                8
+#define PCIEIP_REG_PTM_CAP_REG_BB                                                                            0x000204UL //Access:R    DataWidth:0x20   // The RW value of this register is controlled by setting bit 0 of the EXT3_CAP_ENA for EP.
+  #define PCIEIP_REG_PTM_CAP_REG_PTM_REQUESTER_CAPABLE_BB                                                    (0x1<<0) // Device implements the PTM Requester role.
+  #define PCIEIP_REG_PTM_CAP_REG_PTM_REQUESTER_CAPABLE_BB_SHIFT                                              0
+#define PCIEIP_REG_PTM_CTRL_REG_BB                                                                           0x000208UL //Access:RW   DataWidth:0x20   // The RW value of this register is controlled by setting bit 0 of the EXT3_CAP_ENA for EP.
+  #define PCIEIP_REG_PTM_CTRL_REG_PTM_ENABLED_BB                                                             (0x1<<0) // When Set, Function is permitted to participate in PTM mechanism
+  #define PCIEIP_REG_PTM_CTRL_REG_PTM_ENABLED_BB_SHIFT                                                       0
+  #define PCIEIP_REG_PTM_CTRL_REG_ROOT_SELECT_BB                                                             (0x1<<1) // If Set, device is the PTM Root.
+  #define PCIEIP_REG_PTM_CTRL_REG_ROOT_SELECT_BB_SHIFT                                                       1
+  #define PCIEIP_REG_PTM_CTRL_REG_UNUSED0_BB                                                                 (0x3f<<2) // 
+  #define PCIEIP_REG_PTM_CTRL_REG_UNUSED0_BB_SHIFT                                                           2
+  #define PCIEIP_REG_PTM_CTRL_REG_PTM_EFFECTIVE_GRANULARITY_BB                                               (0xff<<8) // Field provides information on the expected accuracy of the PTM clock. For endpoints, system software programs this field to the value representing the max Local Clock granularity reported by the PTM Root.
+  #define PCIEIP_REG_PTM_CTRL_REG_PTM_EFFECTIVE_GRANULARITY_BB_SHIFT                                         8
+#define PCIEIP_REG_ATS_CAP_BB                                                                                0x000210UL //Access:R    DataWidth:0x20   // The read-only value of this register is controlled by setting bit 9 of the EXT_CAP_ENA for EP, The capability can be enabled by default by defining ATS_ON in version.v .
+  #define PCIEIP_REG_ATS_CAP_ATS_EXT_CAP_ID_BB                                                               (0xffff<<0) // ATS Extended Capability ID. Hardwired to 0xF.
+  #define PCIEIP_REG_ATS_CAP_ATS_EXT_CAP_ID_BB_SHIFT                                                         0
+  #define PCIEIP_REG_ATS_CAP_ATSCAP_VER_BB                                                                   (0xf<<16) // ATS Capability version. Hardwired to 0x1.
+  #define PCIEIP_REG_ATS_CAP_ATSCAP_VER_BB_SHIFT                                                             16
+  #define PCIEIP_REG_ATS_CAP_ATS_NEXT_BB                                                                     (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability.
+  #define PCIEIP_REG_ATS_CAP_ATS_NEXT_BB_SHIFT                                                               20
+#define PCIEIP_REG_ATS_CONTROL_BB                                                                            0x000214UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_ATS_CONTROL_ATS_INVLD_QDEPTH_BB                                                         (0x1f<<0) // The number of Invalidate Requests that the function can accept before putting backpressure on the upstream request. the value in this field is controlled by programming in private register at 0x630
+  #define PCIEIP_REG_ATS_CONTROL_ATS_INVLD_QDEPTH_BB_SHIFT                                                   0
+  #define PCIEIP_REG_ATS_CONTROL_ATS_PAGE_ALIGNED_REQ_BB                                                     (0x1<<5) // This bit when set indicates Untranslated Address is always aligned to 4K boundary. the value in this field is controlled by programming in private register at 0x630
+  #define PCIEIP_REG_ATS_CONTROL_ATS_PAGE_ALIGNED_REQ_BB_SHIFT                                               5
+  #define PCIEIP_REG_ATS_CONTROL_RSVD_Z_BB                                                                   (0x3ff<<6) // 
+  #define PCIEIP_REG_ATS_CONTROL_RSVD_Z_BB_SHIFT                                                             6
+  #define PCIEIP_REG_ATS_CONTROL_ATS_STU_BB                                                                  (0x1f<<16) // The value indicates to the Function, the minimum of 4K byte blocks that is indicated in a Translation Completion or Invalidate Requests. A value of 0 indicates 1 block and a value of 31 indicates 2^31 blocks.
+  #define PCIEIP_REG_ATS_CONTROL_ATS_STU_BB_SHIFT                                                            16
+  #define PCIEIP_REG_ATS_CONTROL_RESERVED_Z_BB                                                               (0x3ff<<21) // 
+  #define PCIEIP_REG_ATS_CONTROL_RESERVED_Z_BB_SHIFT                                                         21
+  #define PCIEIP_REG_ATS_CONTROL_ATS_ENABLE_BB                                                               (0x1<<31) // When set, function is enabled to cache translations.
+  #define PCIEIP_REG_ATS_CONTROL_ATS_ENABLE_BB_SHIFT                                                         31
+#define PCIEIP_REG_RBAR_EXT_CAP_BB                                                                           0x000220UL //Access:R    DataWidth:0x20   // The read-only value of this register is controlled by setting bit 8 of the EXT_CAP_ENA for EP, The capability can be enabled by default by defining RESIZE_BAR in version.v .
+  #define PCIEIP_REG_RBAR_EXT_CAP_RBAR_EXT_CAP_ID_BB                                                         (0xffff<<0) // RBAR Extended Capability ID. Hardwired to 0x15.
+  #define PCIEIP_REG_RBAR_EXT_CAP_RBAR_EXT_CAP_ID_BB_SHIFT                                                   0
+  #define PCIEIP_REG_RBAR_EXT_CAP_RBARCAP_VER_BB                                                             (0xf<<16) // RBAR Capability version. Hardwired to 0x1.
+  #define PCIEIP_REG_RBAR_EXT_CAP_RBARCAP_VER_BB_SHIFT                                                       16
+  #define PCIEIP_REG_RBAR_EXT_CAP_RBAR_NEXT_BB                                                               (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability.
+  #define PCIEIP_REG_RBAR_EXT_CAP_RBAR_NEXT_BB_SHIFT                                                         20
+#define PCIEIP_REG_RBAR_CAP_BB                                                                               0x000224UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_RBAR_CAP_SIZE_CAPABILITY_BB                                                             (0xf<<0) // unused
+  #define PCIEIP_REG_RBAR_CAP_SIZE_CAPABILITY_BB_SHIFT                                                       0
+  #define PCIEIP_REG_RBAR_CAP_SIZE_1M_CAPABILITY_BB                                                          (0x1<<4) // when Set, it indicates function will operate with Bar sized to 1M. Value reflected here is from corresponding bit in private register.
+  #define PCIEIP_REG_RBAR_CAP_SIZE_1M_CAPABILITY_BB_SHIFT                                                    4
+  #define PCIEIP_REG_RBAR_CAP_SIZE_2M_CAPABILITY_BB                                                          (0x1<<5) // when Set, it indicates function will operate with Bar sized to 2M. Value reflected here is from corresponding bit in private register.
+  #define PCIEIP_REG_RBAR_CAP_SIZE_2M_CAPABILITY_BB_SHIFT                                                    5
+  #define PCIEIP_REG_RBAR_CAP_SIZE_4M_CAPABILITY_BB                                                          (0x1<<6) // when Set, it indicates function will operate with Bar sized to 4M. Value reflected here is from corresponding bit in private register.
+  #define PCIEIP_REG_RBAR_CAP_SIZE_4M_CAPABILITY_BB_SHIFT                                                    6
+  #define PCIEIP_REG_RBAR_CAP_SIZE_8M_CAPABILITY_BB                                                          (0x1<<7) // when Set, it indicates function will operate with Bar sized to 8M. Value reflected here is from corresponding bit in private register.
+  #define PCIEIP_REG_RBAR_CAP_SIZE_8M_CAPABILITY_BB_SHIFT                                                    7
+  #define PCIEIP_REG_RBAR_CAP_SIZE_16M_CAPABILITY_BB                                                         (0x1<<8) // when Set, it indicates function will operate with Bar sized to 16M. Value reflected here is from corresponding bit in private register.
+  #define PCIEIP_REG_RBAR_CAP_SIZE_16M_CAPABILITY_BB_SHIFT                                                   8
+  #define PCIEIP_REG_RBAR_CAP_SIZE_32M_CAPABILITY_BB                                                         (0x1<<9) // when Set, it indicates function will operate with Bar sized to 32M. Value reflected here is from corresponding bit in private register.
+  #define PCIEIP_REG_RBAR_CAP_SIZE_32M_CAPABILITY_BB_SHIFT                                                   9
+  #define PCIEIP_REG_RBAR_CAP_SIZE_64M_CAPABILITY_BB                                                         (0x1<<10) // when Set, it indicates function will operate with Bar sized to 64M. Value reflected here is from corresponding bit in private register.
+  #define PCIEIP_REG_RBAR_CAP_SIZE_64M_CAPABILITY_BB_SHIFT                                                   10
+  #define PCIEIP_REG_RBAR_CAP_SIZE_128M_CAPABILITY_BB                                                        (0x1<<11) // when Set, it indicates function will operate with Bar sized to 128M. Value reflected here is from corresponding bit in private register.
+  #define PCIEIP_REG_RBAR_CAP_SIZE_128M_CAPABILITY_BB_SHIFT                                                  11
+  #define PCIEIP_REG_RBAR_CAP_SIZE_256M_CAPABILITY_BB                                                        (0x1<<12) // when Set, it indicates function will operate with Bar sized to 256M. Value reflected here is from corresponding bit in private register.
+  #define PCIEIP_REG_RBAR_CAP_SIZE_256M_CAPABILITY_BB_SHIFT                                                  12
+  #define PCIEIP_REG_RBAR_CAP_SIZE_512M_CAPABILITY_BB                                                        (0x1<<13) // when Set, it indicates function will operate with Bar sized to 512M. Value reflected here is from corresponding bit in private register.
+  #define PCIEIP_REG_RBAR_CAP_SIZE_512M_CAPABILITY_BB_SHIFT                                                  13
+  #define PCIEIP_REG_RBAR_CAP_SIZE_1G_CAPABILITY_BB                                                          (0x1<<14) // when Set, it indicates function will operate with Bar sized to 1G. Value reflected here is from corresponding bit in private register.
+  #define PCIEIP_REG_RBAR_CAP_SIZE_1G_CAPABILITY_BB_SHIFT                                                    14
+  #define PCIEIP_REG_RBAR_CAP_SIZE_512G_TO_2G_CAPABILITY_BB                                                  (0x1ff<<15) // unsupported.
+  #define PCIEIP_REG_RBAR_CAP_SIZE_512G_TO_2G_CAPABILITY_BB_SHIFT                                            15
+#define PCIEIP_REG_RBAR_CTRL_BB                                                                              0x000228UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_RBAR_CTRL_RBAR_INDX_BB                                                                  (0x7<<0) // Indicates which BAR supports a negotiable size.
+  #define PCIEIP_REG_RBAR_CTRL_RBAR_INDX_BB_SHIFT                                                            0
+  #define PCIEIP_REG_RBAR_CTRL_RSVD_BB                                                                       (0x3<<3) // Unused
+  #define PCIEIP_REG_RBAR_CTRL_RSVD_BB_SHIFT                                                                 3
+  #define PCIEIP_REG_RBAR_CTRL_NUM_RBAR_BB                                                                   (0x7<<5) // Indicates number of resizeable BARs in capability.
+  #define PCIEIP_REG_RBAR_CTRL_NUM_RBAR_BB_SHIFT                                                             5
+  #define PCIEIP_REG_RBAR_CTRL_BAR_SIZE_BB                                                                   (0x1f<<8) // When this reg is programmed, value is immediately reflected in the size of the resource, as encoded in the number of RO bits in BAR.
+  #define PCIEIP_REG_RBAR_CTRL_BAR_SIZE_BB_SHIFT                                                             8
+#define PCIEIP_REG_TPH_EXTENDED_CAP_BB                                                                       0x000230UL //Access:R    DataWidth:0x20   // The read-only value of this register is controlled by setting bit 0 of the EXT2_CAP_ENA for EP, By default, this capability is enabled The capability can be enabled by default by defining TPH_ON in version.v and setting bit 0 of EXT2_CAP_ENA.
+  #define PCIEIP_REG_TPH_EXTENDED_CAP_TPH_EXT_CAP_ID_BB                                                      (0xffff<<0) // Vendor Specific Extended Capability ID.
+  #define PCIEIP_REG_TPH_EXTENDED_CAP_TPH_EXT_CAP_ID_BB_SHIFT                                                0
+  #define PCIEIP_REG_TPH_EXTENDED_CAP_CAP_VER_BB                                                             (0xf<<16) // LTR Capability version. Hardwired to 0x1.
+  #define PCIEIP_REG_TPH_EXTENDED_CAP_CAP_VER_BB_SHIFT                                                       16
+  #define PCIEIP_REG_TPH_EXTENDED_CAP_NEXT_BB                                                                (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability.
+  #define PCIEIP_REG_TPH_EXTENDED_CAP_NEXT_BB_SHIFT                                                          20
+#define PCIEIP_REG_TPH_REQ_CAPABILITY_BB                                                                     0x000234UL //Access:R    DataWidth:0x20   // The RW value of this register is controlled by setting bit 0 of the EXT2_CAP_ENA for EP. By default, this capability is disabled (i.e. reading this register will return zeroes).
+  #define PCIEIP_REG_TPH_REQ_CAPABILITY_NO_ST_MODE_SUPPORTED_BB                                              (0x1<<0) // Function supports NO ST mode of operation. This mode is required to be supported.
+  #define PCIEIP_REG_TPH_REQ_CAPABILITY_NO_ST_MODE_SUPPORTED_BB_SHIFT                                        0
+  #define PCIEIP_REG_TPH_REQ_CAPABILITY_INT_VECTOR_MODE_SUPPORTED_BB                                         (0x1<<1) // If Set function supports Interrupt Vector mode of operation. Value in this field can be programmed through TPH_CAP register in private space.
+  #define PCIEIP_REG_TPH_REQ_CAPABILITY_INT_VECTOR_MODE_SUPPORTED_BB_SHIFT                                   1
+  #define PCIEIP_REG_TPH_REQ_CAPABILITY_DEVICE_MODE_SUPPORTED_BB                                             (0x1<<2) // If Set function supports device mode of operation.
+  #define PCIEIP_REG_TPH_REQ_CAPABILITY_DEVICE_MODE_SUPPORTED_BB_SHIFT                                       2
+  #define PCIEIP_REG_TPH_REQ_CAPABILITY_UNUSED0_BB                                                           (0x1f<<3) // 
+  #define PCIEIP_REG_TPH_REQ_CAPABILITY_UNUSED0_BB_SHIFT                                                     3
+  #define PCIEIP_REG_TPH_REQ_CAPABILITY_EXTENDED_TPH_REQ_SUPP_BB                                             (0x1<<8) // If Set function is capable of generating Req's with TPH TLP prefix.
+  #define PCIEIP_REG_TPH_REQ_CAPABILITY_EXTENDED_TPH_REQ_SUPP_BB_SHIFT                                       8
+  #define PCIEIP_REG_TPH_REQ_CAPABILITY_ST_TABLE_LOCATION_BB                                                 (0x3<<9) // Value indicates if and where the ST table is located. Value in this field can be programmed through TPH_CAP register in private space.
+  #define PCIEIP_REG_TPH_REQ_CAPABILITY_ST_TABLE_LOCATION_BB_SHIFT                                           9
+  #define PCIEIP_REG_TPH_REQ_CAPABILITY_UNUSED1_BB                                                           (0x1f<<11) // 
+  #define PCIEIP_REG_TPH_REQ_CAPABILITY_UNUSED1_BB_SHIFT                                                     11
+  #define PCIEIP_REG_TPH_REQ_CAPABILITY_ST_TABLE_SIZE_BB                                                     (0x7ff<<16) // Software reads this field to determine the STTable Size N, whihc is encoded as N-1. So a returned value of 16, indicates a table size of 17. The value in this field can be programmed by programming the TPH_CAP register in the private space.
+  #define PCIEIP_REG_TPH_REQ_CAPABILITY_ST_TABLE_SIZE_BB_SHIFT                                               16
+#define PCIEIP_REG_TPH_REQ_CONTROL_BB                                                                        0x000238UL //Access:RW   DataWidth:0x20   // The RW value of this register is controlled by setting bit 0 of the EXT2_CAP_ENA for EP.
+  #define PCIEIP_REG_TPH_REQ_CONTROL_ST_MODE_SELECT_BB                                                       (0x7<<0) // Value indicates ST mode of operation
+  #define PCIEIP_REG_TPH_REQ_CONTROL_ST_MODE_SELECT_BB_SHIFT                                                 0
+  #define PCIEIP_REG_TPH_REQ_CONTROL_UNUSED0_BB                                                              (0x1f<<3) // 
+  #define PCIEIP_REG_TPH_REQ_CONTROL_UNUSED0_BB_SHIFT                                                        3
+  #define PCIEIP_REG_TPH_REQ_CONTROL_TPH_REQUESTER_ENABLE_BB                                                 (0x3<<8) // Value indicates if and how TPH is enabled
+  #define PCIEIP_REG_TPH_REQ_CONTROL_TPH_REQUESTER_ENABLE_BB_SHIFT                                           8
+#define PCIEIP_REG_PML1SUB_CAPID_BB                                                                          0x000240UL //Access:R    DataWidth:0x20   // The read-only value of this register is controlled by setting bit 2 of the EXT2_CAP_ENA for EP, By default, this capability is disabled (i.e. reading this register will return zeroes). The capability can be enabled by default by defining PMCR_L1_SUBSTATES_ENA in version.v and setting bit 2 of EXT2_CAP_ENA. This capability when present , will only exist in function 0 of a multi-function device.
+  #define PCIEIP_REG_PML1SUB_CAPID_L1SUB_EXT_CAP_ID_BB                                                       (0xffff<<0) // Vendor Specific Extended Capability ID. Value is from corresponding field in private register.
+  #define PCIEIP_REG_PML1SUB_CAPID_L1SUB_EXT_CAP_ID_BB_SHIFT                                                 0
+  #define PCIEIP_REG_PML1SUB_CAPID_CAP_VER_BB                                                                (0xf<<16) // PM L1 substates Capability version. Value is from corresponding field in private register.
+  #define PCIEIP_REG_PML1SUB_CAPID_CAP_VER_BB_SHIFT                                                          16
+  #define PCIEIP_REG_PML1SUB_CAPID_NEXT_BB                                                                   (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability.
+  #define PCIEIP_REG_PML1SUB_CAPID_NEXT_BB_SHIFT                                                             20
+#define PCIEIP_REG_PML1_SUB_CAP_REG_BB                                                                       0x000244UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PML1_SUB_CAP_REG_PM_L1_2_SUPP_BB                                                        (0x1<<0) // Advertize L1_2 capability support for PM
+  #define PCIEIP_REG_PML1_SUB_CAP_REG_PM_L1_2_SUPP_BB_SHIFT                                                  0
+  #define PCIEIP_REG_PML1_SUB_CAP_REG_PM_L1_1_SUPP_BB                                                        (0x1<<1) // Advertize L1_1 capability support for PM
+  #define PCIEIP_REG_PML1_SUB_CAP_REG_PM_L1_1_SUPP_BB_SHIFT                                                  1
+  #define PCIEIP_REG_PML1_SUB_CAP_REG_ASPM_L1_2_SUPP_BB                                                      (0x1<<2) // Advertize L1_2 capability support for ASPM
+  #define PCIEIP_REG_PML1_SUB_CAP_REG_ASPM_L1_2_SUPP_BB_SHIFT                                                2
+  #define PCIEIP_REG_PML1_SUB_CAP_REG_ASPM_L1_1_SUPP_BB                                                      (0x1<<3) // Advertize L1_1 capability support for ASPM
+  #define PCIEIP_REG_PML1_SUB_CAP_REG_ASPM_L1_1_SUPP_BB_SHIFT                                                3
+  #define PCIEIP_REG_PML1_SUB_CAP_REG_CLKREQ_L1SUB_SUPP_BB                                                   (0x1<<4) // Clkreq based L1 substates is supported.
+  #define PCIEIP_REG_PML1_SUB_CAP_REG_CLKREQ_L1SUB_SUPP_BB_SHIFT                                             4
+  #define PCIEIP_REG_PML1_SUB_CAP_REG_RESERVED_1_BB                                                          (0x7<<5) // 
+  #define PCIEIP_REG_PML1_SUB_CAP_REG_RESERVED_1_BB_SHIFT                                                    5
+  #define PCIEIP_REG_PML1_SUB_CAP_REG_L1SUB_CMN_MODE_UP_TIME_BB                                              (0xff<<8) // Time in us that device advertizes that it requires to re-establish common mode.
+  #define PCIEIP_REG_PML1_SUB_CAP_REG_L1SUB_CMN_MODE_UP_TIME_BB_SHIFT                                        8
+  #define PCIEIP_REG_PML1_SUB_CAP_REG_L1SUB_PWR_ON_SCALE_BB                                                  (0x3<<16) // Along with the value field, this field advertizes the tpower_on time in us, that the link partner must wait when exiting from L1_2 state due to driving CLKREQ#, before actively driving the interface.
+  #define PCIEIP_REG_PML1_SUB_CAP_REG_L1SUB_PWR_ON_SCALE_BB_SHIFT                                            16
+  #define PCIEIP_REG_PML1_SUB_CAP_REG_RESERVED_0_BB                                                          (0x1<<18) // 
+  #define PCIEIP_REG_PML1_SUB_CAP_REG_RESERVED_0_BB_SHIFT                                                    18
+  #define PCIEIP_REG_PML1_SUB_CAP_REG_L1SUB_PWR_ON_VALUE_BB                                                  (0x1f<<19) // Along with the scale field, this field advertizes the tpower_on time in us, that the link partner must wait when exiting from L1_2 state due to driving CLKREQ#, before actively driving the interface.
+  #define PCIEIP_REG_PML1_SUB_CAP_REG_L1SUB_PWR_ON_VALUE_BB_SHIFT                                            19
+  #define PCIEIP_REG_PML1_SUB_CAP_REG_RESERVED_BB                                                            (0xff<<24) // 
+  #define PCIEIP_REG_PML1_SUB_CAP_REG_RESERVED_BB_SHIFT                                                      24
+#define PCIEIP_REG_PML1_SUB_CONTROL1_BB                                                                      0x000248UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PML1_SUB_CONTROL1_PM_L1_2_ENABLE_BB                                                     (0x1<<0) // When set, PM L1.2 is enabled.
+  #define PCIEIP_REG_PML1_SUB_CONTROL1_PM_L1_2_ENABLE_BB_SHIFT                                               0
+  #define PCIEIP_REG_PML1_SUB_CONTROL1_PM_L1_1_ENABLE_BB                                                     (0x1<<1) // When set, PM L1.1 is enabled.
+  #define PCIEIP_REG_PML1_SUB_CONTROL1_PM_L1_1_ENABLE_BB_SHIFT                                               1
+  #define PCIEIP_REG_PML1_SUB_CONTROL1_ASPM_L1_2_ENABLE_BB                                                   (0x1<<2) // When set, ASPM L1.2 is enabled.
+  #define PCIEIP_REG_PML1_SUB_CONTROL1_ASPM_L1_2_ENABLE_BB_SHIFT                                             2
+  #define PCIEIP_REG_PML1_SUB_CONTROL1_ASPM_L1_1_ENABLE_BB                                                   (0x1<<3) // When set, ASPM L1.1 is enabled.
+  #define PCIEIP_REG_PML1_SUB_CONTROL1_ASPM_L1_1_ENABLE_BB_SHIFT                                             3
+  #define PCIEIP_REG_PML1_SUB_CONTROL1_L1PM_SUB_MECH_BB                                                      (0x1<<4) // Value of 0 is hardwired indicating support for only CLKREQ based PM mechanism.
+  #define PCIEIP_REG_PML1_SUB_CONTROL1_L1PM_SUB_MECH_BB_SHIFT                                                4
+  #define PCIEIP_REG_PML1_SUB_CONTROL1_RESERVED_1_BB                                                         (0x7<<5) // 
+  #define PCIEIP_REG_PML1_SUB_CONTROL1_RESERVED_1_BB_SHIFT                                                   5
+  #define PCIEIP_REG_PML1_SUB_CONTROL1_COMMON_MODE_RESTORE_TIME_BB                                           (0xff<<8) // For downstream port only.
+  #define PCIEIP_REG_PML1_SUB_CONTROL1_COMMON_MODE_RESTORE_TIME_BB_SHIFT                                     8
+  #define PCIEIP_REG_PML1_SUB_CONTROL1_LTR_L1_2_THRESHOLD_VALUE_BB                                           (0x3ff<<16) // Provides a value for the L1_2 LTR threshold
+  #define PCIEIP_REG_PML1_SUB_CONTROL1_LTR_L1_2_THRESHOLD_VALUE_BB_SHIFT                                     16
+  #define PCIEIP_REG_PML1_SUB_CONTROL1_RESERVED_BB                                                           (0x7<<26) // Reserved
+  #define PCIEIP_REG_PML1_SUB_CONTROL1_RESERVED_BB_SHIFT                                                     26
+  #define PCIEIP_REG_PML1_SUB_CONTROL1_LTR_L1_2_THRESHOLD_SCALE_BB                                           (0x7<<29) // Provides a scale for the L1_2 LTR threshold value
+  #define PCIEIP_REG_PML1_SUB_CONTROL1_LTR_L1_2_THRESHOLD_SCALE_BB_SHIFT                                     29
+#define PCIEIP_REG_PML1_SUB_CONTROL2_BB                                                                      0x00024cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PML1_SUB_CONTROL2_T_POWER_ON_SCALE_BB                                                   (0x3<<0) // This field along with value sets the min amount of time that the Port must wait in L1.2 exit after sampling CLKREQ# asserted before actively driving the interface. This field specifies the scale used
+  #define PCIEIP_REG_PML1_SUB_CONTROL2_T_POWER_ON_SCALE_BB_SHIFT                                             0
+  #define PCIEIP_REG_PML1_SUB_CONTROL2_RSVD_A_BB                                                             (0x1<<2) // 
+  #define PCIEIP_REG_PML1_SUB_CONTROL2_RSVD_A_BB_SHIFT                                                       2
+  #define PCIEIP_REG_PML1_SUB_CONTROL2_T_POWER_ON_VALUE_BB                                                   (0x1f<<3) // This field along with scale sets the min amount of time that the Port must wait in L1.2 exit after sampling CLKREQ# asserted before actively driving the interface.
+  #define PCIEIP_REG_PML1_SUB_CONTROL2_T_POWER_ON_VALUE_BB_SHIFT                                             3
+  #define PCIEIP_REG_PML1_SUB_CONTROL2_RSVD_BB                                                               (0xffffff<<8) // 
+  #define PCIEIP_REG_PML1_SUB_CONTROL2_RSVD_BB_SHIFT                                                         8
+#define PCIEIP_REG_LTR_CAP_HDR_REG_K2_E5                                                                     0x000284UL //Access:RW   DataWidth:0x20   // LTR Extended Capability Header.
+  #define PCIEIP_REG_LTR_CAP_HDR_REG_CAP_ID_K2_E5                                                            (0xffff<<0) // LTR Extended Capacity ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_LTR_CAP_HDR_REG_CAP_ID_K2_E5_SHIFT                                                      0
+  #define PCIEIP_REG_LTR_CAP_HDR_REG_CAP_VERSION_K2_E5                                                       (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_LTR_CAP_HDR_REG_CAP_VERSION_K2_E5_SHIFT                                                 16
+  #define PCIEIP_REG_LTR_CAP_HDR_REG_NEXT_OFFSET_K2_E5                                                       (0xfff<<20) // Next Capability Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_LTR_CAP_HDR_REG_NEXT_OFFSET_K2_E5_SHIFT                                                 20
+#define PCIEIP_REG_LTR_LATENCY_REG_K2_E5                                                                     0x000288UL //Access:RW   DataWidth:0x20   // LTR Max Snoop and No-Snoop Latency Register.
+  #define PCIEIP_REG_LTR_LATENCY_REG_MAX_SNOOP_LAT_K2_E5                                                     (0x3ff<<0) // Max Snoop Latency Value.
+  #define PCIEIP_REG_LTR_LATENCY_REG_MAX_SNOOP_LAT_K2_E5_SHIFT                                               0
+  #define PCIEIP_REG_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_K2_E5                                               (0x7<<10) // Max Snoop Latency Scale.
+  #define PCIEIP_REG_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_K2_E5_SHIFT                                         10
+  #define PCIEIP_REG_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_K2_E5                                                  (0x3ff<<16) // Max No-Snoop Latency Value.
+  #define PCIEIP_REG_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_K2_E5_SHIFT                                            16
+  #define PCIEIP_REG_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_K2_E5                                            (0x7<<26) // Max No-Snoop Latency Scale.
+  #define PCIEIP_REG_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_K2_E5_SHIFT                                      26
+#define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_K2_E5                                                              0x00028cUL //Access:RW   DataWidth:0x20   // Vendor-Specific Extended Capability Header.
+  #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_K2_E5                                            (0xffff<<0) // PCI Express Extended Capability ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_K2_E5_SHIFT                                      0
+  #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_CAP_VERSION_K2_E5                                                (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_CAP_VERSION_K2_E5_SHIFT                                          16
+  #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_K2_E5                                                (0xfff<<20) // Next Capability Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_K2_E5_SHIFT                                          20
+#define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_K2_E5                                                          0x000290UL //Access:R    DataWidth:0x20   // Vendor-Specific Header.
+  #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_K2_E5                                                (0xffff<<0) // VSEC ID.
+  #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_K2_E5_SHIFT                                          0
+  #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_K2_E5                                               (0xf<<16) // VSEC Rev.
+  #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_K2_E5_SHIFT                                         16
+  #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_K2_E5                                            (0xfff<<20) // VSEC Length.
+  #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_K2_E5_SHIFT                                      20
+#define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_K2_E5                                                           0x000294UL //Access:RW   DataWidth:0x20   // Event Counter Control. This is a viewport control register.  - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG viewport register.  - Setting the EVENT_COUNTER_ENABLE field in this register enables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.  - Setting the EVENT_COUNTER_CLEAR field in this register clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.  - Reading the EVENT_COUNTER_STATUS field in this register returns the Enable status of the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.
+  #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_K2_E5                                     (0x3<<0) // Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and you can clear all event counters at once by writing the 'all clear' code. The read value is always '0'.  - 00: no change  - 01: per clear  - 10: no change  - 11: all clear  - Other: reserved
+  #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_K2_E5_SHIFT                               0
+  #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_K2_E5                                    (0x7<<2) // Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default, all event counters are disabled. You can enable/disable a specific Event Counter by writing the 'per event off' or 'per event on' codes. You can enable/disable all event counters by writing the 'all on' or 'all off' codes. The read value is always '0'.  - 000: no change  - 001: per event off  - 010: no change  - 011: per event on  - 100: no change  - 101: all off  - 110: no change  - 111: all on
+  #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_K2_E5_SHIFT                              2
+  #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_K2_E5                                    (0x1<<7) // Event Counter Status. This register returns the current value of the Event Counter selected by the following fields:  - EVENT_COUNTER_EVENT_SELECT  - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky.
+  #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_K2_E5_SHIFT                              7
+  #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_K2_E5                               (0xf<<8) // Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register.  - 0x0: Lane0  - 0x1: Lane1  - 0x2: Lane2  - ..  - 0xF: Lane15 Note: This register field is sticky.
+  #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_K2_E5_SHIFT                         8
+  #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_K2_E5                              (0xfff<<16) // Event Counter Data Select. This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register.  - 27-24: Group number(4-bit: 0..0x7)  - 23-16: Event number(8-bit: 0..0x13) within the Group For example:  - 0x000: Ebuf Overflow  - 0x001: Ebuf Underrun  - ..  - 0x700: Tx Memory Write  - 0x713: Rx Message TLP For detailed definitions of Group number and Event number, see the RAS DES chapter in the Databook.  Note: This register field is sticky.
+  #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_K2_E5_SHIFT                        16
+#define PCIEIP_REG_EVENT_COUNTER_DATA_REG_K2_E5                                                              0x000298UL //Access:R    DataWidth:0x20   // Event Counter Data. This viewport register returns the data selected by the following fields:  - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG  - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG For more details, see the RAS DES section in the Core Operations chapter of the Databook.
+#define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_K2_E5                                                     0x00029cUL //Access:RW   DataWidth:0x20   // Time-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state. For more details, see the RAS DES section in the Core Operations chapter of the Databook.
+  #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_K2_E5                                       (0x1<<0) // Timer Start.  - 0: Start/Restart  - 1: Stop This bit will be cleared automatically when the measurement is finished. Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop.  Note: This register field is sticky.
+  #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_K2_E5_SHIFT                                 0
+  #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_K2_E5                        (0xff<<8) // Time-based Duration Select. Selects the duration of time-based analysis. When "manual control" is selected and TIMER_START is set to '1', this analysis never stops until TIMER_STOP is set to '0'.  - 0x0: Manual control  - 0x1: 1ms  - 0x2: 10ms  - 0x3: 100ms  - 0x4: 1s  - 0x5: 2s  - 0x6: 4s  - Else: Reserved Note: This register field is sticky.
+  #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_K2_E5_SHIFT                  8
+  #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_K2_E5                          (0xff<<24) // Time-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT), and returned in TIME_BASED_ANALYSIS_DATA. Each type of data is measured using one of three types of units:  - Core_clk Cycles. Total time in ps is [Value of TIME_BASED_ANALYSIS_DATA returned when TIME_BASED_REPORT_SELECT=0x00] * TIME_BASED_ANALYSIS_DATA  - Aux_clk Cycles. Total time in ps is [Period of platform specific clock] * TIME_BASED_ANALYSIS_DATA  - Data Bytes. Actual amount of bytes is 16 * TIME_BASED_ANALYSIS_DATA Core_clk Cycles  - 0x00: Duration of 1 cycle  - 0x01: TxL0s  - 0x02: RxL0s  - 0x03: L0  - 0x04: L1 (Rsvd when aux_clk is supplied from the platform specific clock during L1, L1.1 or L1.2)  - 0x07: Configuration/Recovery Aux_clk Cycles  - 0x05: L1.1  - 0x06: L1.2 Data Bytes  - 0x20: Tx TLP Bytes  - 0x21: Rx TLP Bytes  - Else: Rsvd Note: This register field is sticky.
+  #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_K2_E5_SHIFT                    24
+#define PCIEIP_REG_TIME_BASED_ANALYSIS_DATA_REG_K2_E5                                                        0x0002a0UL //Access:R    DataWidth:0x20   // Time-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG For more details, see the RAS DES section in the Core Operations chapter of the Databook.
+#define PCIEIP_REG_EINJ_ENABLE_REG_K2_E5                                                                     0x0002bcUL //Access:RW   DataWidth:0x20   // Error Injection Enable. Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers:  - 0: CRC Error: EINJ0_CRC_REG  - 1: Sequence Number Error: EINJ1_SEQNUM_REG  - 2: DLLP Error: EINJ2_DLLP_REG   - 3: Symbol DataK Mask Error or Sync Header Error: EINJ3_SYMBOL_REG  - 4: FC Credit Update Error: EINJ4_FC_REG  - 5: TLP Duplicate/Nullify Error: EINJ5_SP_TLP_REG  - 6: Specific TLP Error: EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REG After the errors have been inserted by core, it will clear each bit here. For more details, see the RAS DES section in the Core Operations chapter of the Databook.
+  #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_K2_E5                                           (0x1<<0) // Error Injection0 Enable (CRC Error).  Enables insertion of errors into various CRC.  For more details, see the EINJ0_CRC_REG register.  Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_K2_E5_SHIFT                                     0
+  #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_K2_E5                                           (0x1<<1) // Error Injection1 Enable (Sequence Number Error).  Enables insertion of errors into sequence numbers.  For more details, see the EINJ1_SEQNUM_REG register.  Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_K2_E5_SHIFT                                     1
+  #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_K2_E5                                           (0x1<<2) // Error Injection2 Enable (DLLP Error).  Enables insertion of DLLP errors.  For more details, see the EINJ2_DLLP_REG register.  Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_K2_E5_SHIFT                                     2
+  #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_K2_E5                                           (0x1<<3) // Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error).  Enables DataK masking of special symbols or the breaking of the sync header.  For more details, see the EINJ3_SYMBOL_REG register.  Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_K2_E5_SHIFT                                     3
+  #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_K2_E5                                           (0x1<<4) // Error Injection4 Enable (FC Credit Update Error).  Enables insertion of errors into UpdateFCs.  For more details, see the EINJ4_FC_REG register.  Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_K2_E5_SHIFT                                     4
+  #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_K2_E5                                           (0x1<<5) // Error Injection5 Enable (TLP Duplicate/Nullify Error).  Enables insertion of duplicate/nullified TLPs.  For more details, see the EINJ5_SP_TLP_REG register.  Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_K2_E5_SHIFT                                     5
+  #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_K2_E5                                           (0x1<<6) // Error Injection6 Enable (Specific TLP Error). Enables insertion of errors into the packets that you select.  You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT =0.  You can set this bit to '1' when you have disabled the address translation by setting ADDR_TRANSLATION_SUPPORT_EN=0. For more details, see the EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REG registers.  Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_K2_E5_SHIFT                                     6
+#define PCIEIP_REG_EINJ0_CRC_REG_K2_E5                                                                       0x0002c0UL //Access:RW   DataWidth:0x20   // Error Injection Control 0 (CRC Error). Controls the insertion of errors into the CRC, and parity of ordered sets for the selected type of the packets as follows:  - LCRC. Bad TLP will be detected at the receiver side; receiver responds with NAK DLLP; Data Link Retry starts.  - 16-bit CRC of ACK/NAK DLLPs. Bad DLLP occurs at the receiver side; Replay NUM Rollover occurs.  - 16-bit CRC of UpdateFC DLLPs. Error insertion continues for the specific time; LTSSM transitions to the Recovery state because of the UpdateFC timeout (if the timeout is implemented at the receiver of the UpdateFCs).  - ECRC. If ECRC check is enabled, ECRC error is detected at the receiver side.  - FCRC. Framing error will be detected, TLP is discarded, and the LTSSM transitions to Recovery state.  - Parity of TSOS. Error insertion continues for the specific time; LTSSM Recovery/Configuration timeout will occur.  - Parity of SKPOS. Lane error will be detected at the receiver side.
+  #define PCIEIP_REG_EINJ0_CRC_REG_EINJ0_COUNT_K2_E5                                                         (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted.  - If the counter value is 0x01 and error is inserted, ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b.  - If the counter value is 0x00 and ERROR_INJECTION0_ENABLE=1, the errors are inserted until ERROR_INJECTION0_ENABLE is set to '0'.  Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ0_CRC_REG_EINJ0_COUNT_K2_E5_SHIFT                                                   0
+  #define PCIEIP_REG_EINJ0_CRC_REG_EINJ0_CRC_TYPE_K2_E5                                                      (0xf<<8) // Error injection type. Selects the type of CRC error to be inserted.  Tx Path  - 0000b: New TLP's LCRC error injection  - 0001b: 16bCRC error injection of ACK/NAK DLLP  - 0010b: 16bCRC error injection of Update-FC DLLP  - 0011b: New TLP's ECRC error injection  - 0100b: TLP's FCRC error injection (128b/130b)  - 0101b: Parity error of TSOS (128b/130b)  - 0110b: Parity error of SKPOS (128b/130b) Rx Path  - 1000b: LCRC error injection  - 1011b: ECRC error injection  - Others: Reserved Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ0_CRC_REG_EINJ0_CRC_TYPE_K2_E5_SHIFT                                                8
+#define PCIEIP_REG_EINJ1_SEQNUM_REG_K2_E5                                                                    0x0002c4UL //Access:RW   DataWidth:0x20   // Error Injection Control 1 (Sequence Number Error).  Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true:  - ((NEXT_TRANSMIT_SEQ -1) - AckNak_Seq_Num) mod 4096 > 2048  - (AckNak_Seq_Num - ACKD_SEQ) mod 4096 >= 2048 TLP is treated as Duplicate TLP at the Rx side when all these conditions are true:  - Sequence Number != NEXT_RCV_SEQ  - (NEXT_RCV_SEQ - Sequence Number) mod 4096 <= 2048 TLP is treated as Bad TLP at the Rx side when all these conditions are true:  - Sequence Number != NEXT_RCV_SEQ and  - (NEXT_RCV_SEQ - Sequence Number) mod 4096 > 2048
+  #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_COUNT_K2_E5                                                      (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted.  - If the counter value is 0x01 and error is inserted, ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'.  - If the counter value is 0x00 and ERROR_INJECTION1_ENABLE=1, the errors are inserted until ERROR_INJECTION1_ENABLE is set to '0'.  Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_COUNT_K2_E5_SHIFT                                                0
+  #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_K2_E5                                                (0x1<<8) // Sequence number type. Selects the type of sequence number.  - 0b: Insertion of New TLP's SEQ# error  - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_K2_E5_SHIFT                                          8
+  #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_K2_E5                                                 (0x1fff<<16) // Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement.  - 0x0FFF: +4095  - ..  - 0x0002: +2  - 0x0001: +1  - 0x0000: 0  - 0x1FFF: -1  - 0x1FFE: -2  - ..  - 0x1001: -4095 For example:  - Set Type, SEQ# and Count  -- EINJ1_SEQNUM_TYPE =0 (Insert errors into new TLPs)  -- EINJ1_BAD_SEQNUM =0x1FFD (represents -3)  -- EINJ1_COUNT =1  - Enable Error Injection  -- ERROR_INJECTION1_ENABLE =1  - Send a TLP From the Core's Application Interface  -- Assume SEQ#5 is given to the TLP.  - The SEQ# is Changed to #2 by the Error Injection Function in Layer2.  -- 5 + (-3) = 2  - The TLP with SEQ#2 is Transmitted to PCIe Link. Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_K2_E5_SHIFT                                           16
+#define PCIEIP_REG_EINJ2_DLLP_REG_K2_E5                                                                      0x0002c8UL //Access:RW   DataWidth:0x20   // Error Injection Control 2 (DLLP Error). Controls the transmission of DLLPs and inserts the following errors:  - If "ACK/NAK DLLP's transmission block" is selected, replay timeout error will occur at the transmitter of the TLPs and then Data Link Retry will occur.  - If "Update FC DLLP's transmission block" is selected, LTSSM will transition to the Recovery state because of the UpdateFC timeout (if the timeout is implemented at the receiver of the UpdateFCs).  - If "Always Transmission for NAK DLLP" is selected, Data Link Retry will occur at the transmitter of the TLPs. Furthermore, Replay NUM Rollover will occur when the transmitter has been requested four times to send the TLP with the same sequence number.
+  #define PCIEIP_REG_EINJ2_DLLP_REG_EINJ2_COUNT_K2_E5                                                        (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted.  - If the counter value is 0x01 and the error is inserted, ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'.  - If the counter value is 0x00 and ERROR_INJECTION2_ENABLE =1, the errors are inserted until ERROR_INJECTION2_ENABLE is set to '0'. This register is affected only when EINJ2_DLLP_TYPE =2'10b.  Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ2_DLLP_REG_EINJ2_COUNT_K2_E5_SHIFT                                                  0
+  #define PCIEIP_REG_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_K2_E5                                                    (0x3<<8) // DLLP Type. Selects the type of DLLP errors to be inserted.  - 00b: ACK/NAK DLLP's transmission block  - 01b: Update FC DLLP's transmission block  - 10b: Always Transmission for NAK DLLP  - 11b: Reserved Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_K2_E5_SHIFT                                              8
+#define PCIEIP_REG_EINJ3_SYMBOL_REG_K2_E5                                                                    0x0002ccUL //Access:RW   DataWidth:0x20   // Error Injection Control 3 (Symbol Error). When 8b/10b encoding is used, this register controls error insertion into the special (K code) symbols.  - If TS1/TS2/FTS/E-Idle/SKP is selected, it affects whole of the ordered set. It might cause timeout of the LTSSM.  - If END/EDB/STP/SDP is selected, TLP/DLLP will be discarded at the receiver side. When 128b/130b encoding is used, this register controls error insertion into the sync-header.
+  #define PCIEIP_REG_EINJ3_SYMBOL_REG_EINJ3_COUNT_K2_E5                                                      (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted.  - If the counter value is 0x01 and error is inserted, ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'.  - If the counter value is 0x00 and ERROR_INJECTION3_ENABLE =1, the errors are inserted until ERROR_INJECTION3_ENABLE is set to '0'.  Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ3_SYMBOL_REG_EINJ3_COUNT_K2_E5_SHIFT                                                0
+  #define PCIEIP_REG_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_K2_E5                                                (0x7<<8) // Error Type. 8b/10b encoding - Mask K symbol.  - 000b: Reserved  - 001b: COM/PAD(TS1 Order set)  - 010b: COM/PAD(TS2 Order set)  - 011b: COM/FTS(FTS Order set)  - 100b: COM/IDL(E-Idle Order set)  - 101b: END/EDB Symbol  - 110b: STP/SDP Symbol  - 111b: COM/SKP(SKP Order set) 128b/130b encoding - Change sync header.  - 000b: Invert sync header  - Others: Reserved Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_K2_E5_SHIFT                                          8
+#define PCIEIP_REG_EINJ4_FC_REG_K2_E5                                                                        0x0002d0UL //Access:RW   DataWidth:0x20   // Error Injection Control 4 (FC Credit Error). Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types:  - Posted TLP Header credit  - Non-Posted TLP Header credit  - Completion TLP Header credit  - Posted TLP Data credit  - Non-Posted TLP Data credit  - Completion TLP Data credit These errors are not correctable while error insertion is enabled. Receiver buffer overflow error might occur.
+  #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_COUNT_K2_E5                                                          (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted.  - If the counter value is 0x01 and error is inserted, ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'.  - If the counter value is 0x00 and ERROR_INJECTION4_ENABLE =1, the errors are inserted until ERROR_INJECTION4_ENABLE is set to '0'.  Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_COUNT_K2_E5_SHIFT                                                    0
+  #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_K2_E5                                                     (0x7<<8) // Update-FC type. Selects the credit type.  - 000b: Posted TLP Header Credit value control  - 001b: Non-Posted TLP Header Credit value control  - 010b: Completion TLP Header Credit value control  - 011b: Reserved  - 100b: Posted TLP Data Credit value control  - 101b: Non-Posted TLP Data Credit value control  - 110b: Completion TLP Data Credit value control  - 111b: Reserved Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_K2_E5_SHIFT                                               8
+  #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_VC_NUMBER_K2_E5                                                      (0x7<<12) // VC Number. Indicates target VC Number.  Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_VC_NUMBER_K2_E5_SHIFT                                                12
+  #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_K2_E5                                                (0x1fff<<16) // Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement.  - 0x0FFF: +4095  - ..  - 0x0002: +2  - 0x0001: +1  - 0x0000: 0  - 0x1FFF: -1  - 0x1FFE: -2  - ..  - 0x1001: -4095 Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_K2_E5_SHIFT                                          16
+#define PCIEIP_REG_EINJ5_SP_TLP_REG_K2_E5                                                                    0x0002d4UL //Access:RW   DataWidth:0x20   // Error Injection Control 5 (Specific TLP Error). Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol.  - For Duplicate TLP, the core initiates Data Link Retry by handling ACK DLLP as NAK DLLP. These TLPs will be duplicate TLPs at the receiver side.  - For Nullified TLP, the TLPs that the core transmits are changed into nullified TLPs and the original TLPs are stored in the retry buffer. The receiver of these TLPs will detect the lack of seq# and send NAK DLLP at the next TLP. Then the original TLPs are sent from retry buffer and the data controls are recovered. For 128 bit core or more than 128 bit, the core inserts errors the number of times of EINJ5_COUNT but doesn't ensure that the errors are continuously inserted into TLPs.
+  #define PCIEIP_REG_EINJ5_SP_TLP_REG_EINJ5_COUNT_K2_E5                                                      (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted.  - If the counter value is 0x01 and error is inserted, ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'.  - If the counter value is 0x00 and ERROR_INJECTION5_ENABLE =1, the errors are inserted until ERROR_INJECTION5_ENABLE is set to '0'.  Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ5_SP_TLP_REG_EINJ5_COUNT_K2_E5_SHIFT                                                0
+  #define PCIEIP_REG_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_K2_E5                                              (0x1<<8) // Specified TLP. Selects the specified TLP to be inserted.  - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP.  - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_K2_E5_SHIFT                                        8
+#define PCIEIP_REG_EINJ6_COMPARE_POINT_H0_REG_K2_E5                                                          0x0002d8UL //Access:RW   DataWidth:0x20   // Error Injection Control 6 (Compare Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]  The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).  When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register.
+#define PCIEIP_REG_EINJ6_COMPARE_POINT_H1_REG_K2_E5                                                          0x0002dcUL //Access:RW   DataWidth:0x20   // Error Injection Control 6 (Compare Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]  The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).  When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register.
+#define PCIEIP_REG_EINJ6_COMPARE_POINT_H2_REG_K2_E5                                                          0x0002e0UL //Access:RW   DataWidth:0x20   // Error Injection Control 6 (Compare Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]  The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).  When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register.
+#define PCIEIP_REG_EINJ6_COMPARE_POINT_H3_REG_K2_E5                                                          0x0002e4UL //Access:RW   DataWidth:0x20   // Error Injection Control 6 (Compare Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]  The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).  When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register.
+#define PCIEIP_REG_EINJ6_COMPARE_VALUE_H0_REG_K2_E5                                                          0x0002e8UL //Access:RW   DataWidth:0x20   // Error Injection Control 6 (Compare Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]  The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).  When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register.
+#define PCIEIP_REG_EINJ6_COMPARE_VALUE_H1_REG_K2_E5                                                          0x0002ecUL //Access:RW   DataWidth:0x20   // Error Injection Control 6 (Compare Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]  The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).  When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register.
+#define PCIEIP_REG_EINJ6_COMPARE_VALUE_H2_REG_K2_E5                                                          0x0002f0UL //Access:RW   DataWidth:0x20   // Error Injection Control 6 (Compare Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]  The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).  When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register.
+#define PCIEIP_REG_EINJ6_COMPARE_VALUE_H3_REG_K2_E5                                                          0x0002f4UL //Access:RW   DataWidth:0x20   // Error Injection Control 6 (Compare Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]  The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).  When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register.
+#define PCIEIP_REG_EINJ6_CHANGE_POINT_H0_REG_K2_E5                                                           0x0002f8UL //Access:RW   DataWidth:0x20   // Error Injection Control 6 (Change Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]  The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).  The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.
+#define PCIEIP_REG_EINJ6_CHANGE_POINT_H1_REG_K2_E5                                                           0x0002fcUL //Access:RW   DataWidth:0x20   // Error Injection Control 6 (Change Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]  The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).  The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.
+#define PCIEIP_REG_EINJ6_CHANGE_POINT_H2_REG_K2_E5                                                           0x000300UL //Access:RW   DataWidth:0x20   // Error Injection Control 6 (Change Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]  The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).  The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.
+#define PCIEIP_REG_SECONDARY_PCIE_EXTENDED_CAP_BB                                                            0x000300UL //Access:R    DataWidth:0x20   // The read-only value of this register is controlled by setting bit 1 of the EXT2_CAP_ENA for EP, The capability can be enabled by default by defining pcieGen3Rate in version.v and setting bit 1 of EXT2_CAP_ENA.
+  #define PCIEIP_REG_SECONDARY_PCIE_EXTENDED_CAP_SECPCIE_EXT_CAP_ID_BB                                       (0xffff<<0) // Secondary PCIE Extended Capability ID.
+  #define PCIEIP_REG_SECONDARY_PCIE_EXTENDED_CAP_SECPCIE_EXT_CAP_ID_BB_SHIFT                                 0
+  #define PCIEIP_REG_SECONDARY_PCIE_EXTENDED_CAP_CAP_VER_BB                                                  (0xf<<16) // Capability version. Hardwired to 0x1.
+  #define PCIEIP_REG_SECONDARY_PCIE_EXTENDED_CAP_CAP_VER_BB_SHIFT                                            16
+  #define PCIEIP_REG_SECONDARY_PCIE_EXTENDED_CAP_NEXT_BB                                                     (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability.
+  #define PCIEIP_REG_SECONDARY_PCIE_EXTENDED_CAP_NEXT_BB_SHIFT                                               20
+#define PCIEIP_REG_EINJ6_CHANGE_POINT_H3_REG_K2_E5                                                           0x000304UL //Access:RW   DataWidth:0x20   // Error Injection Control 6 (Change Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]  The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).  The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.
+#define PCIEIP_REG_LINK_CONTROL3_BB                                                                          0x000304UL //Access:R    DataWidth:0x20   // The RW value of this register is controlled by setting bit 1 of the EXT2_CAP_ENA for EP.
+  #define PCIEIP_REG_LINK_CONTROL3_PERFORM_EQ_BB                                                             (0x1<<0) // N/A to endpoints
+  #define PCIEIP_REG_LINK_CONTROL3_PERFORM_EQ_BB_SHIFT                                                       0
+  #define PCIEIP_REG_LINK_CONTROL3_LINK_EQ_REQ_INT_EN_BB                                                     (0x1<<1) // N/A to endpoints
+  #define PCIEIP_REG_LINK_CONTROL3_LINK_EQ_REQ_INT_EN_BB_SHIFT                                               1
+#define PCIEIP_REG_EINJ6_CHANGE_VALUE_H0_REG_K2_E5                                                           0x000308UL //Access:RW   DataWidth:0x20   // Error Injection Control 6 (Change Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]  The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).  The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.
+#define PCIEIP_REG_LANE_ERROR_STATUS_BB                                                                      0x000308UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_LANE_ERROR_STATUS_LANE_ERR_STATUS_BITS_BB                                               (0xffff<<0) // Each bit indicates if corresponding PCIE lane detected a lane based error.
+  #define PCIEIP_REG_LANE_ERROR_STATUS_LANE_ERR_STATUS_BITS_BB_SHIFT                                         0
+#define PCIEIP_REG_EINJ6_CHANGE_VALUE_H1_REG_K2_E5                                                           0x00030cUL //Access:RW   DataWidth:0x20   // Error Injection Control 6 (Change Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]  The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).  The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.
+#define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_BB                                                              0x00030cUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS0_BB                                     (0xff<<0) // Applicable only to Upstream component.
+  #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS0_BB_SHIFT                               0
+  #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS0_BB                                  (0xf<<8) // Latest Transmitter Preset Requested from Upstream Component on Lane0
+  #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS0_BB_SHIFT                            8
+  #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS0_BB                                  (0x7<<12) // Latest Receiver Preset Requested from Upstream Component on Lane0
+  #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS0_BB_SHIFT                            12
+  #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_RESERVED0_BB                                                  (0x1<<15) // Reserved
+  #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_RESERVED0_BB_SHIFT                                            15
+  #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS1_BB                                     (0xff<<16) // Applicable only to Upstream component.
+  #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS1_BB_SHIFT                               16
+  #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS1_BB                                  (0xf<<24) // Latest Transmitter Preset Requested from Upstream Component on Lane1
+  #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS1_BB_SHIFT                            24
+  #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS1_BB                                  (0x7<<28) // Latest Receiver Preset Requested from Upstream Component on Lane1
+  #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS1_BB_SHIFT                            28
+  #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_RESERVED1_BB                                                  (0x1<<31) // Reserved
+  #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_RESERVED1_BB_SHIFT                                            31
+#define PCIEIP_REG_EINJ6_CHANGE_VALUE_H2_REG_K2_E5                                                           0x000310UL //Access:RW   DataWidth:0x20   // Error Injection Control 6 (Change Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]  The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).  The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.
+#define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_BB                                                              0x000310UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS2_BB                                     (0xff<<0) // Applicable only to Upstream component.
+  #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS2_BB_SHIFT                               0
+  #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS2_BB                                  (0xf<<8) // Latest Transmitter Preset Requested from Upstream Component on Lane2
+  #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS2_BB_SHIFT                            8
+  #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS2_BB                                  (0x7<<12) // Latest Receiver Preset Requested from Upstream Component on Lane2
+  #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS2_BB_SHIFT                            12
+  #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_RESERVED2_BB                                                  (0x1<<15) // Reserved
+  #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_RESERVED2_BB_SHIFT                                            15
+  #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS3_BB                                     (0xff<<16) // Applicable only to Upstream component.
+  #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS3_BB_SHIFT                               16
+  #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS3_BB                                  (0xf<<24) // Latest Transmitter Preset Requested from Upstream Component on Lane3
+  #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS3_BB_SHIFT                            24
+  #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS3_BB                                  (0x7<<28) // Latest Receiver Preset Requested from Upstream Component on Lane3
+  #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS3_BB_SHIFT                            28
+  #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_RESERVED3_BB                                                  (0x1<<31) // Reserved
+  #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_RESERVED3_BB_SHIFT                                            31
+#define PCIEIP_REG_EINJ6_CHANGE_VALUE_H3_REG_K2_E5                                                           0x000314UL //Access:RW   DataWidth:0x20   // Error Injection Control 6 (Change Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]  The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).  The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.
+#define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_BB                                                              0x000314UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS4_BB                                     (0xff<<0) // Applicable only to Upstream component.
+  #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS4_BB_SHIFT                               0
+  #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS4_BB                                  (0xf<<8) // Latest Transmitter Preset Requested from Upstream Component on Lane4
+  #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS4_BB_SHIFT                            8
+  #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS4_BB                                  (0x7<<12) // Latest Receiver Preset Requested from Upstream Component on Lane4
+  #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS4_BB_SHIFT                            12
+  #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_RESERVED4_BB                                                  (0x1<<15) // Reserved
+  #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_RESERVED4_BB_SHIFT                                            15
+  #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS5_BB                                     (0xff<<16) // Applicable only to Upstream component.
+  #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS5_BB_SHIFT                               16
+  #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS5_BB                                  (0xf<<24) // Latest Transmitter Preset Requested from Upstream Component on Lane5
+  #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS5_BB_SHIFT                            24
+  #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS5_BB                                  (0x7<<28) // Latest Receiver Preset Requested from Upstream Component on Lane5
+  #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS5_BB_SHIFT                            28
+  #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_RESERVED5_BB                                                  (0x1<<31) // Reserved
+  #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_RESERVED5_BB_SHIFT                                            31
+#define PCIEIP_REG_EINJ6_TLP_REG_K2_E5                                                                       0x000318UL //Access:RW   DataWidth:0x20   // Error Injection Control 6 (Packet Error).  The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).  When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the this register.  The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).  The type and number of errors are specified by the this register. Only applies when EINJ6_INVERTED_CONTROL in this register =0. The TLP into that errors are injected will not arrive at the transaction layer of the remote device when all of the following conditions are true.  - Using 128b/130b encoding  - Injecting errors into TLP Length field / TLP digest bit
+  #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_COUNT_K2_E5                                                         (0xff<<0) // Error Injection Count.  Indicates the number of errors to insert. This counter is decremented while errors are been inserted.  - If the counter value is 0x01 and error is inserted, ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'.  - If the counter value is 0x00 and ERROR_INJECTION6_ENABLE=1, errors are inserted until ERROR_INJECTION6_ENABLE is set to '0'.  Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_COUNT_K2_E5_SHIFT                                                   0
+  #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_K2_E5                                              (0x1<<8) // Inverted Error Injection Control.  - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3].  - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_K2_E5_SHIFT                                        8
+  #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_K2_E5                                                   (0x7<<9) // Packet type.  Selects the TLP packets to inject errors into.  - 0: TLP Header  - 1: TLP Prefix 1st 4-DWORDs  - 2: TLP Prefix 2nd -DWORDs  - Else: Reserved Note: This register field is sticky.
+  #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_K2_E5_SHIFT                                             9
+#define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_BB                                                              0x000318UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS6_BB                                     (0xff<<0) // Applicable only to Upstream component.
+  #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS6_BB_SHIFT                               0
+  #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS6_BB                                  (0xf<<8) // Latest Transmitter Preset Requested from Upstream Component on Lane6
+  #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS6_BB_SHIFT                            8
+  #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS6_BB                                  (0x7<<12) // Latest Receiver Preset Requested from Upstream Component on Lane6
+  #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS6_BB_SHIFT                            12
+  #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_RESERVED6_BB                                                  (0x1<<15) // Reserved
+  #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_RESERVED6_BB_SHIFT                                            15
+  #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS7_BB                                     (0xff<<16) // Applicable only to Upstream component.
+  #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS7_BB_SHIFT                               16
+  #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS7_BB                                  (0xf<<24) // Latest Transmitter Preset Requested from Upstream Component on Lane7
+  #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS7_BB_SHIFT                            24
+  #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS7_BB                                  (0x7<<28) // Latest Receiver Preset Requested from Upstream Component on Lane7
+  #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS7_BB_SHIFT                            28
+  #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_RESERVED7_BB                                                  (0x1<<31) // Reserved
+  #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_RESERVED7_BB_SHIFT                                            31
+#define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_BB                                                              0x00031cUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS8_BB                                     (0xff<<0) // Applicable only to Upstream component.
+  #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS8_BB_SHIFT                               0
+  #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS8_BB                                  (0xf<<8) // Latest Transmitter Preset Requested from Upstream Component on Lane8
+  #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS8_BB_SHIFT                            8
+  #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS8_BB                                  (0x7<<12) // Latest Receiver Preset Requested from Upstream Component on Lane8
+  #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS8_BB_SHIFT                            12
+  #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_RESERVED6_BB                                                  (0x1<<15) // Reserved
+  #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_RESERVED6_BB_SHIFT                                            15
+  #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS9_BB                                     (0xff<<16) // Applicable only to Upstream component.
+  #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS9_BB_SHIFT                               16
+  #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS9_BB                                  (0xf<<24) // Latest Transmitter Preset Requested from Upstream Component on Lane9
+  #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS9_BB_SHIFT                            24
+  #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS9_BB                                  (0x7<<28) // Latest Receiver Preset Requested from Upstream Component on Lane9
+  #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS9_BB_SHIFT                            28
+  #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_RESERVED7_BB                                                  (0x1<<31) // Reserved
+  #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_RESERVED7_BB_SHIFT                                            31
+#define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_BB                                                            0x000320UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS10_BB                                  (0xff<<0) // Applicable only to Upstream component.
+  #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS10_BB_SHIFT                            0
+  #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS10_BB                               (0xf<<8) // Latest Transmitter Preset Requested from Upstream Component on Lane10
+  #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS10_BB_SHIFT                         8
+  #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS10_BB                               (0x7<<12) // Latest Receiver Preset Requested from Upstream Component on Lane10
+  #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS10_BB_SHIFT                         12
+  #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_RESERVED10_BB                                               (0x1<<15) // Reserved
+  #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_RESERVED10_BB_SHIFT                                         15
+  #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS11_BB                                  (0xff<<16) // Applicable only to Upstream component.
+  #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS11_BB_SHIFT                            16
+  #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS11_BB                               (0xf<<24) // Latest Transmitter Preset Requested from Upstream Component on Lane11
+  #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS11_BB_SHIFT                         24
+  #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS11_BB                               (0x7<<28) // Latest Receiver Preset Requested from Upstream Component on Lane11
+  #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS11_BB_SHIFT                         28
+  #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_RESERVED11_BB                                               (0x1<<31) // Reserved
+  #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_RESERVED11_BB_SHIFT                                         31
+#define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_BB                                                            0x000324UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS12_BB                                  (0xff<<0) // Applicable only to Upstream component.
+  #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS12_BB_SHIFT                            0
+  #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS12_BB                               (0xf<<8) // Latest Transmitter Preset Requested from Upstream Component on Lane12
+  #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS12_BB_SHIFT                         8
+  #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS12_BB                               (0x7<<12) // Latest Receiver Preset Requested from Upstream Component on Lane12
+  #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS12_BB_SHIFT                         12
+  #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_RESERVED12_BB                                               (0x1<<15) // Reserved
+  #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_RESERVED12_BB_SHIFT                                         15
+  #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS13_BB                                  (0xff<<16) // Applicable only to Upstream component.
+  #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS13_BB_SHIFT                            16
+  #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS13_BB                               (0xf<<24) // Latest Transmitter Preset Requested from Upstream Component on Lane13
+  #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS13_BB_SHIFT                         24
+  #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS13_BB                               (0x7<<28) // Latest Receiver Preset Requested from Upstream Component on Lane13
+  #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS13_BB_SHIFT                         28
+  #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_RESERVED13_BB                                               (0x1<<31) // Reserved
+  #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_RESERVED13_BB_SHIFT                                         31
+#define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_BB                                                            0x000328UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS14_BB                                  (0xff<<0) // Applicable only to Upstream component.
+  #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS14_BB_SHIFT                            0
+  #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS14_BB                               (0xf<<8) // Latest Transmitter Preset Requested from Upstream Component on Lane14
+  #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS14_BB_SHIFT                         8
+  #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS14_BB                               (0x7<<12) // Latest Receiver Preset Requested from Upstream Component on Lane14
+  #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS14_BB_SHIFT                         12
+  #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_RESERVED14_BB                                               (0x1<<15) // Reserved
+  #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_RESERVED14_BB_SHIFT                                         15
+  #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS15_BB                                  (0xff<<16) // Applicable only to Upstream component.
+  #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS15_BB_SHIFT                            16
+  #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS15_BB                               (0xf<<24) // Latest Transmitter Preset Requested from Upstream Component on Lane15
+  #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS15_BB_SHIFT                         24
+  #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS15_BB                               (0x7<<28) // Latest Receiver Preset Requested from Upstream Component on Lane15
+  #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS15_BB_SHIFT                         28
+  #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_RESERVED15_BB                                               (0x1<<31) // Reserved
+  #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_RESERVED15_BB_SHIFT                                         31
+#define PCIEIP_REG_SD_CONTROL1_REG_K2_E5                                                                     0x00032cUL //Access:RW   DataWidth:0x20   // Silicon Debug Control 1. For more details, see the RAS DES section in the Core Operations chapter of the Databook.
+  #define PCIEIP_REG_SD_CONTROL1_REG_FORCE_DETECT_LANE_K2_E5                                                 (0xffff<<0) // Force Detect Lane.  When the FORCE_DETECT_LANE_EN field is set, the core ignores receiver detection from PHY during LTSSM Detect state and uses this value instead.  - 0: Lane0  - 1: Lane1  - 2: Lane2  - ..  - 15: Lane15 Note: This register field is sticky.
+  #define PCIEIP_REG_SD_CONTROL1_REG_FORCE_DETECT_LANE_K2_E5_SHIFT                                           0
+  #define PCIEIP_REG_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_K2_E5                                              (0x1<<16) // Force Detect Lane Enable.  When this bit is set, the core ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_K2_E5_SHIFT                                        16
+  #define PCIEIP_REG_SD_CONTROL1_REG_TX_EIOS_NUM_K2_E5                                                       (0x3<<20) // Number of Tx EIOS.  This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The core selects the greater value between this register and the value defined by the PCI-SIG specification.  2.5GT/s, 8.0GT/s or higher:  - 0x0: 1  - 0x1: 4  - 0x2: 8  - 0x3: 16 5.0GT/s:  - 0x0: 2  - 0x1: 8  - 0x2: 16  - 0x3: 32 Note: This register field is sticky.
+  #define PCIEIP_REG_SD_CONTROL1_REG_TX_EIOS_NUM_K2_E5_SHIFT                                                 20
+  #define PCIEIP_REG_SD_CONTROL1_REG_LOW_POWER_INTERVAL_K2_E5                                                (0x3<<22) // Low Power Entry Interval Time.  Interval Time that the core starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to, RXELECIDLE assertion at the PHY.  - 0x0: 40ns  - 0x1: 160ns  - 0x2: 320ns  - 0x3: 640ns Note: This register field is sticky.
+  #define PCIEIP_REG_SD_CONTROL1_REG_LOW_POWER_INTERVAL_K2_E5_SHIFT                                          22
+#define PCIEIP_REG_SD_CONTROL2_REG_K2_E5                                                                     0x000330UL //Access:RW   DataWidth:0x20   // Silicon Debug Control 2. For more details, see the RAS DES section in the Core Operations chapter of the Databook.
+  #define PCIEIP_REG_SD_CONTROL2_REG_HOLD_LTSSM_K2_E5                                                        (0x1<<0) // Hold and Release LTSSM.  For as long as this register is '1', the core stays in the current LTSSM.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_CONTROL2_REG_HOLD_LTSSM_K2_E5_SHIFT                                                  0
+  #define PCIEIP_REG_SD_CONTROL2_REG_RECOVERY_REQUEST_K2_E5                                                  (0x1<<1) // Recovery Request.  When this bit is set to '1' in L0 or L0s, the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization.
+  #define PCIEIP_REG_SD_CONTROL2_REG_RECOVERY_REQUEST_K2_E5_SHIFT                                            1
+  #define PCIEIP_REG_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_K2_E5                                              (0x1<<2) // Force LinkDown.  When this bit is set and the core detects REPLY_NUM rolling over 4 times, the LTSSM transitions to Detect State.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_K2_E5_SHIFT                                        2
+  #define PCIEIP_REG_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_K2_E5                                          (0x1<<8) // Direct Recovery.Idle to Configuration.  When this bit is set and the LTSSM is in Recovery Idle State, the LTSSM transitions to Configuration state.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_K2_E5_SHIFT                                    8
+  #define PCIEIP_REG_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_K2_E5                                          (0x1<<9) // Direct Polling.Compliance to Detect.  When this bit is set and the LTSSM is in Polling Compliance State, the LTSSM transitions to Detect state.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_K2_E5_SHIFT                                    9
+  #define PCIEIP_REG_SD_CONTROL2_REG_DETECT_LPBKSLV_TO_EXIT_K2_E5                                            (0x1<<10) // Detect Loopback Slave To Exit.  When this bit is set and the LTSSM is in Loopback Slave Active State, the LTSSM transitions to Loopback Slave Exit state.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_CONTROL2_REG_DETECT_LPBKSLV_TO_EXIT_K2_E5_SHIFT                                      10
+  #define PCIEIP_REG_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_K2_E5                                      (0x1<<16) // Framing Error Recovery Disable.  This bit forces a transition to Recovery state when a Framing Error is occurred.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_K2_E5_SHIFT                                16
+#define PCIEIP_REG_SD_STATUS_L1LANE_REG_K2_E5                                                                0x00033cUL //Access:RW   DataWidth:0x20   // Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the following field:  - LANE_SELECT in SD_CONTROL1_REG For more details, see the RAS DES section in the Core Operations chapter of the Databook.
+  #define PCIEIP_REG_SD_STATUS_L1LANE_REG_LANE_SELECT_K2_E5                                                  (0xf<<0) // Lane Select.  Lane Select register for Silicon Debug Status Register of Layer1-PerLane.  - 0x0: Lane0  - 0x1: Lane1  - 0x2: Lane2  - ..  - 0xF: Lane15 Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_L1LANE_REG_LANE_SELECT_K2_E5_SHIFT                                            0
+  #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_K2_E5                                              (0x1<<16) // PIPE:RxPolarity.  Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT).  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_K2_E5_SHIFT                                        16
+  #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_K2_E5                                             (0x1<<17) // PIPE:Detect Lane.  Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT).  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_K2_E5_SHIFT                                       17
+  #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXVALID_K2_E5                                                 (0x1<<18) // PIPE:RxValid.  Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT).  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXVALID_K2_E5_SHIFT                                           18
+  #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_K2_E5                                              (0x1<<19) // PIPE:RxElecIdle.  Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT).  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_K2_E5_SHIFT                                        19
+  #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_K2_E5                                              (0x1<<20) // PIPE:TxElecIdle.  Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT).  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_K2_E5_SHIFT                                        20
+  #define PCIEIP_REG_SD_STATUS_L1LANE_REG_DESKEW_POINTER_K2_E5                                               (0xff<<24) // Deskew Pointer.  Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT).  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_L1LANE_REG_DESKEW_POINTER_K2_E5_SHIFT                                         24
+#define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_K2_E5                                                               0x000340UL //Access:RW   DataWidth:0x20   // Silicon Debug Status(Layer1 LTSSM). For more details, see the RAS DES section in the Core Operations chapter of the Databook.
+  #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_K2_E5                                             (0x7f<<0) // First Framing Error Pointer.  Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1.  Received Unexpected Framing Token  - 01h: When non- STP/SDP/IDL Token was received and it was not in TLP/DLLP reception  - 02h: When current token was not a valid EDB token and previous token was an EDB. (128/256 bit core only)  - 03h: When SDP token was received but not expected. (128 bit & (x8 | x16) core only)  - 04h: When STP token was received but not expected. (128 bit & (x8 | x16) core only)  - 05h: When EDS token was expected but not received or whenever an EDS token was received but not expected.  - 06h: When a framing error was detected in the deskew block while a packet has been in progress in token_finder. Received Unexpected STP Token  - 11h: When Framing CRC in STP token did not match  - 12h: When Framing Parity in STP token did not match.  - 13h: When Framing TLP Length in STP token was smaller than 5 DWORDs. Received Unexpected Block  - 21h: When Receiving an OS Block following SDS in Datastream state  - 22h: When Data Block followed by OS Block different from SKP, EI, EIE in Datastream state  - 23h: When Block with an undefined Block Type in Datastream state  - 24h: When Data Stream without data over three cycles in Datastream state  - 25h: When OS Block during Data Stream in Datastream state  - 26h: When RxStatus Error was detected in Datastream state  - 27h: When Not all active lanes receiving SKP OS starting at same cycle time in SKPOS state  - 28h: When a 2-Block timeout occurs for SKP OS in SKPOS state  - 29h: When Receiving consecutive OS Blocks within a Data Stream in SKPOS state  - 2Ah: When Phy status error was detected in SKPOS state  - 2Bh: When Not all active lanes receiving EIOS starting at same cycle time in EIOS state  - 2Ch: When At least one Symbol from the first 4 Symbols is not EIOS Symbol in EIOS state (CX_NB=2 only)  - 2Dh: When Not all active lanes receiving EIEOS starting at same cycle time in EIEOS state  - 2Eh: When Not full 16 eieos symbols are received in EIEOS state All other values not listed above are Reserved.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_K2_E5_SHIFT                                       0
+  #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_K2_E5                                                 (0x1<<7) // Framing Error.  Indicates Framing Error detection status.
+  #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_K2_E5_SHIFT                                           7
+  #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_K2_E5                                             (0x7<<8) // PIPE:PowerDown.  Indicates PIPE PowerDown signal.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_K2_E5_SHIFT                                       8
+  #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_K2_E5                                               (0x1<<15) // Lane Reversal Operation.  Receiver detected lane reversal.  This field is only valid in the L0 LTSSM state.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_K2_E5_SHIFT                                         15
+  #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_K2_E5                                              (0xffff<<16) // LTSSM Variable.  Indicates internal LTSSM variables defined in the PCI Express base specification.  C-PCIe Mode:  - 0: directed_speed_change  - 1: changed_speed_recovery  - 2: successful_speed_negotiation  - 3: upconfigure_capable; Set to '1' if both ports advertised the UpConfigure capability in the last Config.Complete.  - 4: select_deemphasis  - 5: start_equalization_w_preset  - 6: equalization_done_8GT_data_rate  - 7: equalization_done_16GT_data_rate  - 15:8: idle_to_rlock_transitioned M-PCIe Mode:  - 0: idle_to_recovery  - 1: recovery_to_configuration Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_K2_E5_SHIFT                                        16
+#define PCIEIP_REG_SD_STATUS_PM_REG_K2_E5                                                                    0x000344UL //Access:RW   DataWidth:0x20   // Silicon Debug Status(PM). For more details, see the RAS DES section in the Core Operations chapter of the Databook.
+  #define PCIEIP_REG_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_K2_E5                                               (0x1f<<0) // Internal PM State(Master).  Indicates internal state machine of Power Management Master controller.  - 0h: S_IDLE  - 1h: S_RESPOND_NAK  - 2h: S_BLOCK_TLP  - 3h: S_WAIT_LAST_TLP_ACK  - 4h: S_WAIT_EIDLE  - 5h: S_LINK_ENTR_L1  - 6h: S_L1  - 7h: S_L1_EXIT  - 8h: S_L23RDY  - 9h: S_LINK_ENTR_L23  - Ah: S_L23RDY_WAIT4ALIVE  - Bh: S_ACK_WAIT4IDLE Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_K2_E5_SHIFT                                         0
+  #define PCIEIP_REG_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_K2_E5                                               (0xf<<8) // Internal PM State(Slave).  Indicates internal state machine of Power Management Slave controller.  - 00h: IDLE  - 01h: L0  - 02h: L0S  - 03h: ENTER_L0S  - 04h: L0S_EXIT  - 08h: L1  - 09h: L1_BLOCK_TLP  - 0Ah: L1_WAIT_LAST_TLP_ACK  - 0Bh: L1_WAIT_PMDLLP_ACK  - 0Ch: L1_LINK_ENTR_L1  - 0Dh: L1_EXIT  - 0Fh: PREP_4L1  - 10h: L23_BLOCK_TLP  - 11h: L23_WAIT_LAST_TLP_ACK  - 12h: L23_WAIT_PMDLLP_ACK  - 13h: L23_ENTR_L23  - 14h: L23RDY  - 15h: PREP_4L23  - 16h: L23RDY_WAIT4ALIVE  - 17h: L0S_BLOCK_TLP Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_K2_E5_SHIFT                                         8
+  #define PCIEIP_REG_SD_STATUS_PM_REG_PME_RESEND_FLAG_K2_E5                                                  (0x1<<12) // PME Re-send flag.  When the DUT sends a PM_PME message TLP, the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%), the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent.
+  #define PCIEIP_REG_SD_STATUS_PM_REG_PME_RESEND_FLAG_K2_E5_SHIFT                                            12
+  #define PCIEIP_REG_SD_STATUS_PM_REG_LATCHED_NFTS_K2_E5                                                     (0xff<<16) // Latched N_FTS.  Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_PM_REG_LATCHED_NFTS_K2_E5_SHIFT                                               16
+#define PCIEIP_REG_SD_STATUS_L2_REG_K2_E5                                                                    0x000348UL //Access:R    DataWidth:0x20   // Silicon Debug Status(Layer2). For more details, see the RAS DES section in the Core Operations chapter of the Databook.
+  #define PCIEIP_REG_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_K2_E5                                                    (0xfff<<0) // Tx Tlp Sequence Number.  Indicates next transmit sequence number for transmit TLP.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_K2_E5_SHIFT                                              0
+  #define PCIEIP_REG_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_K2_E5                                                    (0xfff<<12) // Tx Ack Sequence Number.  Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_K2_E5_SHIFT                                              12
+  #define PCIEIP_REG_SD_STATUS_L2_REG_DLCMSM_K2_E5                                                           (0x3<<24) // DLCMSM.  Indicates the current DLCMSM.  - 00b: DL_INACTIVE  - 01b: DL_FC_INIT  - 11b: DL_ACTIVE Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_L2_REG_DLCMSM_K2_E5_SHIFT                                                     24
+  #define PCIEIP_REG_SD_STATUS_L2_REG_FC_INIT1_K2_E5                                                         (0x1<<26) // FC_INIT1.  Indicates the core is in FC_INIT1(VC0) state.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_L2_REG_FC_INIT1_K2_E5_SHIFT                                                   26
+  #define PCIEIP_REG_SD_STATUS_L2_REG_FC_INIT2_K2_E5                                                         (0x1<<27) // FC_INIT2. Indicates the core is in FC_INIT2(VC0) state.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_L2_REG_FC_INIT2_K2_E5_SHIFT                                                   27
+#define PCIEIP_REG_SD_STATUS_L3FC_REG_K2_E5                                                                  0x00034cUL //Access:RW   DataWidth:0x20   // Silicon Debug Status(Layer3 FC). The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields:  - CREDIT_SEL_VC  - CREDIT_SEL_CREDIT_TYPE  - CREDIT_SEL_TLP_TYPE  - CREDIT_SEL_HD For more details, see the RAS DES section in the Core Operations chapter of the Databook.
+  #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_K2_E5                                                  (0x7<<0) // Credit Select(VC).  This field in conjunction with the CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields.  - 0x0: VC0  - 0x1: VC1  - 0x2: VC2  - ..  - 0x7: VC7 Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_K2_E5_SHIFT                                            0
+  #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_K2_E5                                         (0x1<<3) // Credit Select(Credit Type).  This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields.  - 0x0: Rx  - 0x1: Tx Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_K2_E5_SHIFT                                   3
+  #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_K2_E5                                            (0x3<<4) // Credit Select(TLP Type).  This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields.  - 0x0: Posted  - 0x1: Non-Posted  - 0x2: Completion Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_K2_E5_SHIFT                                      4
+  #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_K2_E5                                                  (0x1<<6) // Credit Select(HeaderData).  This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields.  - 0x0: Header Credit  - 0x1: Data Credit Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_K2_E5_SHIFT                                            6
+  #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_DATA0_K2_E5                                                   (0xfff<<8) // Credit Data0.  Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields.  - Rx: Credit Received Value  - Tx: Credit Consumed Value Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_DATA0_K2_E5_SHIFT                                             8
+  #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_DATA1_K2_E5                                                   (0xfff<<20) // Credit Data1.  Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields.  - Rx: Credit Allocated Value  - Tx: Credit Limit Value. This value is valid when DLCMSM=0x3(DL_ACTIVE). Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_DATA1_K2_E5_SHIFT                                             20
+#define PCIEIP_REG_SD_STATUS_L3_REG_K2_E5                                                                    0x000350UL //Access:RW   DataWidth:0x20   // Silicon Debug Status(Layer3). For more details, see the RAS DES section in the Core Operations chapter of the Databook.
+  #define PCIEIP_REG_SD_STATUS_L3_REG_MFTLP_POINTER_K2_E5                                                    (0x7f<<0) // First Malformed TLP Error Pointer.  Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS.  - 01h: AtomicOp address alignment  - 02h: AtomicOp operand  - 03h: AtomicOp  byte enable  - 04h: TLP length miss match  - 05h: Max payload size  - 06h: Message TLP without TC0  - 07h: Invalid TC  - 08h: Unexpected route bit in Message TLP  - 09h: Unexpected CRS status in Completion TLP  - 0Ah: Byte enable  - 0Bh: Memory Address 4KB boundary  - 0Ch: TLP prefix rules  - 0Dh: Translation request rules  - 0Eh: Invalid TLP type  - 0Fh: Completion rules  - 7Fh: Application  - Else: Reserved Note: This register field is sticky.
+  #define PCIEIP_REG_SD_STATUS_L3_REG_MFTLP_POINTER_K2_E5_SHIFT                                              0
+  #define PCIEIP_REG_SD_STATUS_L3_REG_MFTLP_STATUS_K2_E5                                                     (0x1<<7) // Malformed TLP Status.  Indicates malformed TLP has occurred.
+  #define PCIEIP_REG_SD_STATUS_L3_REG_MFTLP_STATUS_K2_E5_SHIFT                                               7
+#define PCIEIP_REG_SD_EQ_CONTROL1_REG_K2_E5                                                                  0x00035cUL //Access:RW   DataWidth:0x20   // Silicon Debug EQ Control 1. This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport registers. For more details, see the RAS DES section in the Core Operations chapter of the Databook.
+  #define PCIEIP_REG_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_K2_E5                                                    (0xf<<0) // EQ Status Lane Select.  Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers.  - 0x0: Lane0  - 0x1: Lane1  - 0x2: Lane2  - ..  - 0xF: Lane15 Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_K2_E5_SHIFT                                              0
+  #define PCIEIP_REG_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_K2_E5                                                    (0x1<<4) // EQ Status Rate Select.  Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers.  - 0x0: 8.0GT/s Speed  - 0x1: 16.0GT/s Speed Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_K2_E5_SHIFT                                              4
+  #define PCIEIP_REG_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_K2_E5                                             (0x3<<16) // Eval Interval Time.  Indicates interval time of RxEqEval assertion.  - 00: 500ns  - 01: 1us  - 10: 2us  - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2).  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_K2_E5_SHIFT                                       16
+  #define PCIEIP_REG_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_K2_E5                                              (0x1<<23) // FOM Target Enable.  Enables the FOM_TARGET fields.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_K2_E5_SHIFT                                        23
+  #define PCIEIP_REG_SD_EQ_CONTROL1_REG_FOM_TARGET_K2_E5                                                     (0xff<<24) // FOM Target.  Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2).  This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit).  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_CONTROL1_REG_FOM_TARGET_K2_E5_SHIFT                                               24
+#define PCIEIP_REG_SD_EQ_CONTROL2_REG_K2_E5                                                                  0x000360UL //Access:RW   DataWidth:0x20   // Silicon Debug EQ Control 2. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details, see the RAS DES section in the Core Operations chapter of the Databook.
+  #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_K2_E5                                      (0x3f<<0) // Force Local Transmitter Pre-cursor.  Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_K2_E5_SHIFT                                0
+  #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_K2_E5                                          (0x3f<<6) // Force Local Transmitter Cursor.  Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_K2_E5_SHIFT                                    6
+  #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_K2_E5                                     (0x3f<<12) // Force Local Transmitter Post-Cursor.  Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_K2_E5_SHIFT                               12
+  #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_K2_E5                                            (0x7<<18) // Force Local Receiver Preset Hint.  Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of received or set value.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_K2_E5_SHIFT                                      18
+  #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_K2_E5                                          (0xf<<24) // Force Local Transmitter Preset.  Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_K2_E5_SHIFT                                    24
+  #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_K2_E5                                     (0x1<<28) // Force Local Transmitter Coefficient Enable.  Enables the following fields:  - FORCE_LOCAL_TX_PRE_CURSOR  - FORCE_LOCAL_TX_CURSOR  - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_K2_E5_SHIFT                               28
+  #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_K2_E5                                     (0x1<<29) // Force Local Receiver Preset Hint Enable.  Enables the FORCE_LOCAL_RX_HINT field.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_K2_E5_SHIFT                               29
+  #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_K2_E5                                   (0x1<<30) // Force Local Transmitter Preset Enable.  Enables the FORCE_LOCAL_TX_PRESET field.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_K2_E5_SHIFT                             30
+#define PCIEIP_REG_SD_EQ_CONTROL3_REG_K2_E5                                                                  0x000364UL //Access:RW   DataWidth:0x20   // Silicon Debug EQ Control 3. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details, see the RAS DES section in the Core Operations chapter of the Databook.
+  #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_K2_E5                                     (0x3f<<0) // Force Remote Transmitter Pre-Cursor.  Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from link partner.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_K2_E5_SHIFT                               0
+  #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_K2_E5                                         (0x3f<<6) // Force Remote Transmitter Cursor.  Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from link partner.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_K2_E5_SHIFT                                   6
+  #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_K2_E5                                    (0x3f<<12) // Force Remote Transmitter Post-Cursor.  Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from link partner.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_K2_E5_SHIFT                              12
+  #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_K2_E5                                    (0x1<<28) // Force Remote Transmitter Coefficient Enable.  Enables the following fields:  - FORCE_REMOTE_TX_PRE_CURSOR  - FORCE_REMOTE_TX_CURSOR  - FORCE_REMOTE_TX_POST_CURSOR Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_K2_E5_SHIFT                              28
+#define PCIEIP_REG_SD_EQ_STATUS1_REG_K2_E5                                                                   0x00036cUL //Access:R    DataWidth:0x20   // Silicon Debug EQ Status 1. This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. The following fields are available when Equalization finished unsuccessfully(EQ_CONVERGENCE_INFO=2).  - EQ_RULEA_VIOLATION  - EQ_RULEB_VIOLATION  - EQ_RULEC_VIOLATION  - EQ_REJECT_EVENT For more details, see the RAS DES section in the Core Operations chapter of the Databook.
+  #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_SEQUENCE_K2_E5                                                     (0x1<<0) // EQ Sequence.  Indicates that the core is starting the equalization sequence.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_SEQUENCE_K2_E5_SHIFT                                               0
+  #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_K2_E5                                             (0x3<<1) // EQ Convergence Info.  Indicates equalization convergence information.  - 0x0: Equalization is not attempted  - 0x1: Equalization finished successfully  - 0x2: Equalization finished unsuccessfully  - 0x3: Reserved This bit is automatically cleared when the core starts EQ Master phase again.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_K2_E5_SHIFT                                       1
+  #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_K2_E5                                              (0x1<<4) // EQ Rule A Violation.  Indicates that coefficient rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2).  This bit is automatically cleared when the core starts EQ Master phase again.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_K2_E5_SHIFT                                        4
+  #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_K2_E5                                              (0x1<<5) // EQ Rule B Violation.  Indicates that coefficient rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2).  This bit is automatically cleared when the core starts EQ Master phase again.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_K2_E5_SHIFT                                        5
+  #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_K2_E5                                              (0x1<<6) // EQ Rule C Violation.  Indicates that coefficient rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2).  This bit is automatically cleared when the core starts EQ Master phase again.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_K2_E5_SHIFT                                        6
+  #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_K2_E5                                                 (0x1<<7) // EQ Reject Event.  Indicates that the core receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the core starts EQ Master phase again.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_K2_E5_SHIFT                                           7
+#define PCIEIP_REG_SD_EQ_STATUS2_REG_K2_E5                                                                   0x000370UL //Access:R    DataWidth:0x20   // Silicon Debug EQ Status 2. This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field is available when Equalization finished successfully(EQ_CONVERGENCE_INFO=1). For more details, see the RAS DES section in the Core Operations chapter of the Databook.
+  #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_K2_E5                                             (0x3f<<0) // EQ Local Pre-Cursor.  Indicates Local pre cursor coefficient value.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_K2_E5_SHIFT                                       0
+  #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_K2_E5                                                 (0x3f<<6) // EQ Local Cursor.  Indicates Local cursor coefficient value.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_K2_E5_SHIFT                                           6
+  #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_K2_E5                                            (0x3f<<12) // EQ Local Post-Cursor.  Indicates Local post cursor coefficient value.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_K2_E5_SHIFT                                      12
+  #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_K2_E5                                                (0x7<<18) // EQ Local Receiver Preset Hint.  Indicates Local Receiver Preset Hint value.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_K2_E5_SHIFT                                          18
+  #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_K2_E5                                              (0xff<<24) // EQ Local Figure of Merit.  Indicates Local maximum Figure of Merit value.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_K2_E5_SHIFT                                        24
+#define PCIEIP_REG_SD_EQ_STATUS3_REG_K2_E5                                                                   0x000374UL //Access:R    DataWidth:0x20   // Silicon Debug EQ Status 3. This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field is available when Equalization finished successfully(EQ_CONVERGENCE_INFO=1). For more details, see the RAS DES section in the Core Operations chapter of the Databook.
+  #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_K2_E5                                            (0x3f<<0) // EQ Remote Pre-Cursor.  Indicates Remote pre cursor coefficient value.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_K2_E5_SHIFT                                      0
+  #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_K2_E5                                                (0x3f<<6) // EQ Remote Cursor.  Indicates Remote cursor coefficient value.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_K2_E5_SHIFT                                          6
+  #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_K2_E5                                           (0x3f<<12) // EQ Remote Post-Cursor.  Indicates Remote post cursor coefficient value.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_K2_E5_SHIFT                                     12
+  #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_K2_E5                                                    (0x3f<<18) // EQ Remote LF.  Indicates Remote LF value.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_K2_E5_SHIFT                                              18
+  #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_K2_E5                                                    (0x3f<<24) // EQ Remote FS.  Indicates Remote FS value.  Note: This register field is sticky.
+  #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_K2_E5_SHIFT                                              24
+#define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_K2_E5                                                               0x00038cUL //Access:RW   DataWidth:0x20   // PCIe Extended capability ID, Capability version and Next capability offset.
+  #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_ID_K2_E5                                                          (0xffff<<0) // PCI Express Extended Capability ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_ID_K2_E5_SHIFT                                                    0
+  #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_CAP_K2_E5                                                         (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_CAP_K2_E5_SHIFT                                                   16
+  #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_K2_E5                                                 (0xfff<<20) // Next Capability Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_K2_E5_SHIFT                                           20
+#define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_K2_E5                                                       0x000390UL //Access:R    DataWidth:0x20   // Vendor Specific Header.
+  #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_K2_E5                                             (0xffff<<0) // VSEC ID.   Note: This register field is sticky.
+  #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_K2_E5_SHIFT                                       0
+  #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_K2_E5                                            (0xf<<16) // VSEC Rev.   Note: This register field is sticky.
+  #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_K2_E5_SHIFT                                      16
+  #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_K2_E5                                         (0xfff<<20) // VSEC Length.   Note: This register field is sticky.
+  #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_K2_E5_SHIFT                                   20
+#define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_K2_E5                                                           0x000394UL //Access:RW   DataWidth:0x20   // ECC error correction control. Allows you to disable ECC error correction for RAMs and datapath.  When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native core clock (core_clk), you must not write this register while operations are in progress in the AXI master / slave interface.
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_K2_E5                                   (0x1<<0) // Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors.  Note: This register field is sticky.
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_K2_E5_SHIFT                             0
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_K2_E5                    (0x1<<1) // Error correction disable for AXI bridge master completion buffer.  Note: This register field is sticky.
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_K2_E5_SHIFT              1
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_K2_E5                  (0x1<<2) // Error correction disable for AXI bridge outbound request path.  Note: This register field is sticky.
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_K2_E5_SHIFT            2
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_K2_E5                            (0x1<<3) // Error correction disable for DMA write engine.  Note: This register field is sticky.
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_K2_E5_SHIFT                      3
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_K2_E5                            (0x1<<4) // Error correction disable for layer 2 Tx path.  Note: This register field is sticky.
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_K2_E5_SHIFT                      4
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_K2_E5                            (0x1<<5) // Error correction disable for layer 3 Tx path.  Note: This register field is sticky.
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_K2_E5_SHIFT                      5
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_K2_E5                               (0x1<<6) // Error correction disable for Adm Tx path.  Note: This register field is sticky.
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_K2_E5_SHIFT                         6
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_K2_E5                                   (0x1<<16) // Global error correction disable for all Rx layers.  Note: This register field is sticky.
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_K2_E5_SHIFT                             16
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_K2_E5        (0x1<<17) // Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors.  Note: This register field is sticky.
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_K2_E5_SHIFT  17
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_K2_E5           (0x1<<18) // Error correction disable for AXI bridge inbound request path.  Note: This register field is sticky.
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_K2_E5_SHIFT     18
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_K2_E5                             (0x1<<19) // Error correction disable for DMA read engine.  Note: This register field is sticky.
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_K2_E5_SHIFT                       19
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_K2_E5                            (0x1<<20) // Error correction disable for layer 2 Rx path.  Note: This register field is sticky.
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_K2_E5_SHIFT                      20
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_K2_E5                            (0x1<<21) // Error correction disable for layer 3 Rx path.  Note: This register field is sticky.
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_K2_E5_SHIFT                      21
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_K2_E5                               (0x1<<22) // Error correction disable for ADM Rx path.  Note: This register field is sticky.
+  #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_K2_E5_SHIFT                         22
+#define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_K2_E5                                                         0x000398UL //Access:RW   DataWidth:0x20   // Corrected error (1-bit ECC) counter selection and control. This is a viewport control register. Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned by the RASDP_CORR_COUNT_REPORT_OFF viewport data register.
+  #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_K2_E5                                   (0x1<<0) // Clear all correctable error counters.
+  #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_K2_E5_SHIFT                             0
+  #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_K2_E5                                      (0x1<<4) // Enable correctable errors counters.  - 1: counters increment when the core detects a correctable error  - 0: counters are frozen The counters are enabled by default.
+  #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_K2_E5_SHIFT                                4
+  #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_K2_E5                         (0xf<<20) // Select correctable counter region:  - 0x0: Region select for Adm Rx path  - 0x1: Region select for layer 3 Rx path  - 0x2: Region select for layer 2 Rx path  - 0x3: Region select for DMA inbound path  - 0x4: Region select for AXI bridge inbound request path  - 0x5: Region select for AXI bridge inbound completion composer path  - 0x6: Region select for Adm Tx path  - 0x7: Region select for layer 3 Tx path  - 0x8: Region select for layer 2 Tx path  - 0x9: Region select for DMA outbound path  - 0xa: Region select for AXI bridge outbound request path  - 0xb: Region select for AXI bridge outbound master completion buffer path  - 0xc: Reserved  - 0xf: Reserved
+  #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_K2_E5_SHIFT                   20
+  #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_K2_E5                                (0xff<<24) // Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
+  #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_K2_E5_SHIFT                          24
+#define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_K2_E5                                                         0x00039cUL //Access:R    DataWidth:0x20   // Corrected error (1-bit ECC) counter data. This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register.
+  #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_K2_E5                                          (0xff<<0) // Current corrected error count for the selected counter.
+  #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_K2_E5_SHIFT                                    0
+  #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_K2_E5                          (0xf<<20) // Selected correctable counter region:  - 0x0: Region select for Adm Rx path  - 0x1: Region select for layer 3 Rx path  - 0x2: Region select for layer 2 Rx path  - 0x3: Region select for DMA inbound path  - 0x4: Region select for AXI bridge inbound request path  - 0x5: Region select for AXI bridge inbound completion composer path  - 0x6: Region select for Adm Tx path  - 0x7: Region select for layer 3 Tx path  - 0x8: Region select for layer 2 Tx path  - 0x9: Region select for DMA outbound path  - 0xa: Region select for AXI bridge outbound request path  - 0xb: Region select for AXI bridge outbound master completion buffer path  - 0xc: Reserved  - 0xf: Reserved
+  #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_K2_E5_SHIFT                    20
+  #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_K2_E5                                 (0xff<<24) // Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register.
+  #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_K2_E5_SHIFT                           24
+#define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_K2_E5                                                       0x0003a0UL //Access:RW   DataWidth:0x20   // Uncorrected error (2-bit ECC and parity) counter selection and control. This is a viewport control register. Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the counter data returned by the RASDP_UNCORR_COUNT_REPORT_OFF viewport data register.
+  #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_K2_E5                               (0x1<<0) // Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared.
+  #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_K2_E5_SHIFT                         0
+  #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_K2_E5                                  (0x1<<4) // Enable uncorrectable errors counters.  - 1: enables the counters to increment on detected correctable errors  - 0: counters are frozen The counters are enabled by default.
+  #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_K2_E5_SHIFT                            4
+  #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_K2_E5                     (0xf<<20) // Select uncorrectable counter region:  - 0x0: Region select for Adm Rx path  - 0x1: Region select for layer 3 Rx path  - 0x2: Region select for layer 2 Rx path  - 0x3: Region select for DMA inbound path  - 0x4: Region select for AXI bridge inbound request path  - 0x5: Region select for AXI bridge inbound completion composer path  - 0x6: Region select for Adm Tx path  - 0x7: Region select for layer 3 Tx path  - 0x8: Region select for layer 2 Tx path  - 0x9: Region select for DMA outbound path  - 0xa: Region select for AXI bridge outbound request path  - 0xb: Region select for AXI bridge outbound master completion buffer path  - 0xc: Reserved  - 0xf: Reserved
+  #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_K2_E5_SHIFT               20
+  #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_K2_E5                            (0xff<<24) // Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
+  #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_K2_E5_SHIFT                      24
+#define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_K2_E5                                                       0x0003a4UL //Access:R    DataWidth:0x20   // Uncorrected error (2-bit ECC and parity) counter data. This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF register.
+  #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_K2_E5                                      (0xff<<0) // Current uncorrected error count for the selected counter
+  #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_K2_E5_SHIFT                                0
+  #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_K2_E5                      (0xf<<20) // Selected uncorrectable counter region:  - 0x0: Region select for Adm Rx path  - 0x1: Region select for layer 3 Rx path  - 0x2: Region select for layer 2 Rx path  - 0x3: Region select for DMA inbound path  - 0x4: Region select for AXI bridge inbound request path  - 0x5: Region select for AXI bridge inbound completion composer path  - 0x6: Region select for Adm Tx path  - 0x7: Region select for layer 3 Tx path  - 0x8: Region select for layer 2 Tx path  - 0x9: Region select for DMA outbound path  - 0xa: Region select for AXI bridge outbound request path  - 0xb: Region select for AXI bridge outbound master completion buffer path  - 0xc: Reserved  - 0xf: Reserved
+  #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_K2_E5_SHIFT                20
+  #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_K2_E5                             (0xff<<24) // Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register.
+  #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_K2_E5_SHIFT                       24
+#define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_K2_E5                                                            0x0003a8UL //Access:RW   DataWidth:0x20   // Error injection control for the following features:  - 1-bit or 2-bit injection  - Continuous or fixed-number (n) injection modes  - Global enable/disable  - Selectable location where injection occurs
+  #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_K2_E5                                             (0x1<<0) // Error injection global enable. When set enables the error insertion logic.
+  #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_K2_E5_SHIFT                                       0
+  #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_K2_E5                                           (0x3<<4) // Error injection type:  - 0: none  - 1: 1-bit  - 2: 2-bit
+  #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_K2_E5_SHIFT                                     4
+  #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_K2_E5                                          (0xff<<8) // Error injection count.  - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN.  - 1: one errors injected
+  #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_K2_E5_SHIFT                                    8
+  #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_K2_E5                                            (0xff<<16) // Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
+  #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_K2_E5_SHIFT                                      16
+#define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_K2_E5                                                       0x0003acUL //Access:R    DataWidth:0x20   // Corrected errors locations. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.
+  #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_K2_E5                                (0xf<<4) // Region of the first corrected error:  - 0x0: Region select for Adm Rx path  - 0x1: Region select for layer 3 Rx path  - 0x2: Region select for layer 2 Rx path  - 0x3: Region select for DMA inbound path  - 0x4: Region select for AXI bridge inbound request path  - 0x5: Region select for AXI bridge inbound completion composer path  - 0x6: Region select for Adm Tx path  - 0x7: Region select for layer 3 Tx path  - 0x8: Region select for layer 2 Tx path  - 0x9: Region select for DMA outbound path  - 0xa: Region select for AXI bridge outbound request path  - 0xb: Region select for AXI bridge outbound master completion buffer path  - 0xc: Reserved  - 0xf: Reserved
+  #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_K2_E5_SHIFT                          4
+  #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_K2_E5                                (0xff<<8) // Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR.  You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
+  #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_K2_E5_SHIFT                          8
+  #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_K2_E5                                 (0xf<<20) // Region of the last corrected error:  - 0x0: Region select for Adm Rx path  - 0x1: Region select for layer 3 Rx path  - 0x2: Region select for layer 2 Rx path  - 0x3: Region select for DMA inbound path  - 0x4: Region select for AXI bridge inbound request path  - 0x5: Region select for AXI bridge inbound completion composer path  - 0x6: Region select for Adm Tx path  - 0x7: Region select for layer 3 Tx path  - 0x8: Region select for layer 2 Tx path  - 0x9: Region select for DMA outbound path  - 0xa: Region select for AXI bridge outbound request path  - 0xb: Region select for AXI bridge outbound master completion buffer path  - 0xc: Reserved  - 0xf: Reserved
+  #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_K2_E5_SHIFT                           20
+  #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_K2_E5                                 (0xff<<24) // Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR.  You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
+  #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_K2_E5_SHIFT                           24
+#define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_K2_E5                                                     0x0003b0UL //Access:R    DataWidth:0x20   // Uncorrected errors locations. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.
+  #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_K2_E5                            (0xf<<4) // Region of the first uncorrected error:  - 0x0: Region select for Adm Rx path  - 0x1: Region select for layer 3 Rx path  - 0x2: Region select for layer 2 Rx path  - 0x3: Region select for DMA inbound path  - 0x4: Region select for AXI bridge inbound request path  - 0x5: Region select for AXI bridge inbound completion composer path  - 0x6: Region select for Adm Tx path  - 0x7: Region select for layer 3 Tx path  - 0x8: Region select for layer 2 Tx path  - 0x9: Region select for DMA outbound path  - 0xa: Region select for AXI bridge outbound request path  - 0xb: Region select for AXI bridge outbound master completion buffer path  - 0xc: Reserved  - 0xf: Reserved
+  #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_K2_E5_SHIFT                      4
+  #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_K2_E5                            (0xff<<8) // Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR.  You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
+  #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_K2_E5_SHIFT                      8
+  #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_K2_E5                             (0xf<<20) // Region of the last uncorrected error:  - 0x0: Region select for Adm Rx path  - 0x1: Region select for layer 3 Rx path  - 0x2: Region select for layer 2 Rx path  - 0x3: Region select for DMA inbound path  - 0x4: Region select for AXI bridge inbound request path  - 0x5: Region select for AXI bridge inbound completion composer path  - 0x6: Region select for Adm Tx path  - 0x7: Region select for layer 3 Tx path  - 0x8: Region select for layer 2 Tx path  - 0x9: Region select for DMA outbound path  - 0xa: Region select for AXI bridge outbound request path  - 0xb: Region select for AXI bridge outbound master completion buffer path  - 0xc: Reserved  - 0xf: Reserved
+  #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_K2_E5_SHIFT                       20
+  #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_K2_E5                             (0xff<<24) // Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR.  You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
+  #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_K2_E5_SHIFT                       24
+#define PCIEIP_REG_RASDP_ERROR_MODE_EN_OFF_K2_E5                                                             0x0003b4UL //Access:RW   DataWidth:0x20   // RASDP error mode enable. The core enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode:  - Rx TLPs that are forwarded to your application are not guaranteed to be correct; you must discard them. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.
+  #define PCIEIP_REG_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_K2_E5                                             (0x1<<0) // Write '1' to enable the core enter RASDP error mode when it detects an uncorrectable error.  Note: This register field is sticky.
+  #define PCIEIP_REG_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_K2_E5_SHIFT                                       0
+  #define PCIEIP_REG_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_K2_E5                                         (0x1<<1) // Write '1' to enable the core to bring the link down when the core enters RASDP error mode.  Note: This register field is sticky.
+  #define PCIEIP_REG_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_K2_E5_SHIFT                                   1
+#define PCIEIP_REG_RASDP_ERROR_MODE_CLEAR_OFF_K2_E5                                                          0x0003b8UL //Access:RW   DataWidth:0x20   // Exit RASDP error mode. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.
+  #define PCIEIP_REG_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_K2_E5                                       (0x1<<0) // Write '1' to take the core out of RASDP error mode. The core will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs.
+  #define PCIEIP_REG_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_K2_E5_SHIFT                                 0
+#define PCIEIP_REG_RASDP_RAM_ADDR_CORR_ERROR_OFF_K2_E5                                                       0x0003bcUL //Access:R    DataWidth:0x20   // RAM Address where a corrected error (1-bit ECC) has been detected. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.
+  #define PCIEIP_REG_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_K2_E5                                 (0x7ffffff<<0) // RAM Address where a corrected error (1-bit ECC) has been detected.
+  #define PCIEIP_REG_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_K2_E5_SHIFT                           0
+  #define PCIEIP_REG_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_K2_E5                                (0xf<<28) // RAM index where a corrected error (1-bit ECC) has been detected.
+  #define PCIEIP_REG_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_K2_E5_SHIFT                          28
+#define PCIEIP_REG_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_K2_E5                                                     0x0003c0UL //Access:R    DataWidth:0x20   // RAM Address where an uncorrected error (2-bit ECC) has been detected. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.
+  #define PCIEIP_REG_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_K2_E5                             (0x7ffffff<<0) // RAM Address where an uncorrected error (2-bit ECC) has been detected.
+  #define PCIEIP_REG_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_K2_E5_SHIFT                       0
+  #define PCIEIP_REG_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_K2_E5                            (0xf<<28) // RAM index where an uncorrected error (2-bit ECC) has been detected.
+  #define PCIEIP_REG_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_K2_E5_SHIFT                      28
+#define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_K2_E5                                                                 0x0003c4UL //Access:RW   DataWidth:0x20   // Precision Time Measurement Capability Header. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.
+  #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_PTM_CAP_ID_K2_E5                                                    (0xffff<<0) // Precision Time Measurement PCI Express Extended Capability ID. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_PTM_CAP_ID_K2_E5_SHIFT                                              0
+  #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_PTM_CAP_VERSION_K2_E5                                               (0xf<<16) // Precision Time Measurement PCI Express Extended Capability Version. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_PTM_CAP_VERSION_K2_E5_SHIFT                                         16
+  #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_PTM_NEXT_OFFSET_K2_E5                                               (0xfff<<20) // Precision Time Measurement PCI Express Extended Capability Next Offset. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_PTM_NEXT_OFFSET_K2_E5_SHIFT                                         20
+#define PCIEIP_REG_PTM_CAP_OFF_K2_E5                                                                         0x0003c8UL //Access:RW   DataWidth:0x20   // PTM Capability Register. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.
+  #define PCIEIP_REG_PTM_CAP_OFF_PTM_REQ_CAPABLE_K2_E5                                                       (0x1<<0) // PTM Requester Capable. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_PTM_CAP_OFF_PTM_REQ_CAPABLE_K2_E5_SHIFT                                                 0
+  #define PCIEIP_REG_PTM_CAP_OFF_PTM_RES_CAPABLE_K2_E5                                                       (0x1<<1) // PTM Responder Capable. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_PTM_CAP_OFF_PTM_RES_CAPABLE_K2_E5_SHIFT                                                 1
+  #define PCIEIP_REG_PTM_CAP_OFF_PTM_ROOT_CAPABLE_K2_E5                                                      (0x1<<2) // PTM Root Capable. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_PTM_CAP_OFF_PTM_ROOT_CAPABLE_K2_E5_SHIFT                                                2
+  #define PCIEIP_REG_PTM_CAP_OFF_PTM_CLK_GRAN_K2_E5                                                          (0xff<<8) // PTM Local Clock Granularity. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
+  #define PCIEIP_REG_PTM_CAP_OFF_PTM_CLK_GRAN_K2_E5_SHIFT                                                    8
+#define PCIEIP_REG_PTM_CONTROL_OFF_K2_E5                                                                     0x0003ccUL //Access:RW   DataWidth:0x20   // PTM Control Register. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.
+  #define PCIEIP_REG_PTM_CONTROL_OFF_PTM_ENABLE_K2_E5                                                        (0x1<<0) // PTM Enable. When set, this function is permitted to participate in the PTM mechanism. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.
+  #define PCIEIP_REG_PTM_CONTROL_OFF_PTM_ENABLE_K2_E5_SHIFT                                                  0
+  #define PCIEIP_REG_PTM_CONTROL_OFF_ROOT_SELECT_K2_E5                                                       (0x1<<1) // PTM Root Select. When set this Time Source is the PTM Root. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.  Note: The access attributes of this field are as follows:  - Dbi: HWINIT
+  #define PCIEIP_REG_PTM_CONTROL_OFF_ROOT_SELECT_K2_E5_SHIFT                                                 1
+  #define PCIEIP_REG_PTM_CONTROL_OFF_EFF_GRAN_K2_E5                                                          (0xff<<8) // PTM Effective Granularity. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.  Note: The access attributes of this field are as follows:  - Dbi: HWINIT
+  #define PCIEIP_REG_PTM_CONTROL_OFF_EFF_GRAN_K2_E5_SHIFT                                                    8
+#define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_K2_E5                                                                 0x0003d0UL //Access:RW   DataWidth:0x20   // Precision Time Measurement Requester Capability Header (VSEC). For more details, see the PTM section in the Databook.
+  #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_PTM_REQ_EXT_CAP_ID_K2_E5                                            (0xffff<<0) // Precision Time Measurement Requester VSEC ID. For more details, see the PTM section in the Databook.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_PTM_REQ_EXT_CAP_ID_K2_E5_SHIFT                                      0
+  #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_PTM_REQ_EXT_CAP_VER_K2_E5                                           (0xf<<16) // Precision Time Measurement Requester VSEC Version. For more details, see the PTM section in the Databook.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_PTM_REQ_EXT_CAP_VER_K2_E5_SHIFT                                     16
+  #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_PTM_REQ_EXT_CAP_NEXT_OFFS_K2_E5                                     (0xfff<<20) // Precision Time Measurement Requester VSEC Next Pointer. For more details, see the PTM section in the Databook.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_PTM_REQ_EXT_CAP_NEXT_OFFS_K2_E5_SHIFT                               20
+#define PCIEIP_REG_PTM_REQ_HDR_OFF_K2_E5                                                                     0x0003d4UL //Access:RW   DataWidth:0x20   // Precision Time Measurement Requester Vendor Specific Header. For more details, see the PTM section in the Databook.
+  #define PCIEIP_REG_PTM_REQ_HDR_OFF_PTM_REQ_VSEC_ID_K2_E5                                                   (0xffff<<0) // PTM Requester VSEC ID. For more details, see the PTM section in the Databook.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_PTM_REQ_HDR_OFF_PTM_REQ_VSEC_ID_K2_E5_SHIFT                                             0
+  #define PCIEIP_REG_PTM_REQ_HDR_OFF_PTM_REQ_VSEC_REV_K2_E5                                                  (0xf<<16) // PTM Requester VSEC Revision. For more details, see the PTM section in the Databook.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_PTM_REQ_HDR_OFF_PTM_REQ_VSEC_REV_K2_E5_SHIFT                                            16
+  #define PCIEIP_REG_PTM_REQ_HDR_OFF_PTM_REQ_VSEC_LENGTH_K2_E5                                               (0xfff<<20) // PTM Requester VSEC Length. For more details, see the PTM section in the Databook.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_PTM_REQ_HDR_OFF_PTM_REQ_VSEC_LENGTH_K2_E5_SHIFT                                         20
+#define PCIEIP_REG_PTM_REQ_CONTROL_OFF_K2_E5                                                                 0x0003d8UL //Access:RW   DataWidth:0x20   // PTM Requester Vendor Specific Control Register. For more details, see the PTM section in the Databook.
+  #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_AUTO_UPDATE_ENABLED_K2_E5                                   (0x1<<0) // PTM Requester Auto Update Enabled - When enabled PTM Requester will automatically atempt to update it's context every 10ms. For more details, see the PTM section in the Databook.  Note: This register field is sticky.
+  #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_AUTO_UPDATE_ENABLED_K2_E5_SHIFT                             0
+  #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_START_UPDATE_K2_E5                                          (0x1<<1) // PTM Requester Start Update - When set the PTM Requester will attempt a PTM Dialogue to update it's context; This bit is self clearing. For more details, see the PTM section in the Databook.
+  #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_START_UPDATE_K2_E5_SHIFT                                    1
+  #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_FAST_TIMERS_K2_E5                                           (0x1<<2) // PTM Fast Timers - Debug mode for PTM Timers. The 100us timer output will go high at 30us and the 10ms timer output will go high at 100us (The Long Timer Value is ignored). There is no change to the 1us timer. The requester operation will otherwise remain the same. For more details, see the PTM section in the Databook.  Note: This register field is sticky.
+  #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_FAST_TIMERS_K2_E5_SHIFT                                     2
+  #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_LONG_TIMER_K2_E5                                            (0xff<<8) // PTM Requester Long Timer - Determines the period between each auto update PTM Dialogue in miliseconds. Update period is the register value +1 milisecond. For the Switch product this value must not be set larger than 0x9 for spec compliance. For more details, see the PTM section in the Databook.  Note: This register field is sticky.
+  #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_LONG_TIMER_K2_E5_SHIFT                                      8
+#define PCIEIP_REG_PTM_REQ_STATUS_OFF_K2_E5                                                                  0x0003dcUL //Access:R    DataWidth:0x20   // PTM Requester Vendor Specific Status Register. For more details, see the PTM section in the Databook.
+  #define PCIEIP_REG_PTM_REQ_STATUS_OFF_PTM_REQ_CONTEXT_VALID_K2_E5                                          (0x1<<0) // PTM Requester Context Valid - Indicate that the Timing Context is valid. For more details, see the PTM section in the Databook.
+  #define PCIEIP_REG_PTM_REQ_STATUS_OFF_PTM_REQ_CONTEXT_VALID_K2_E5_SHIFT                                    0
+  #define PCIEIP_REG_PTM_REQ_STATUS_OFF_PTM_REQ_MANUAL_UPDATE_ALLOWED_K2_E5                                  (0x1<<1) // PTM Requester Manual Update Allowed - Indicates whether or not a Manual Update can be signalled. For more details, see the PTM section in the Databook.
+  #define PCIEIP_REG_PTM_REQ_STATUS_OFF_PTM_REQ_MANUAL_UPDATE_ALLOWED_K2_E5_SHIFT                            1
+#define PCIEIP_REG_PTM_REQ_LOCAL_LSB_OFF_K2_E5                                                               0x0003e0UL //Access:RW   DataWidth:0x20   // PTM Requester Local Clock LSB  For more details, see the PTM section in the Databook.
+#define PCIEIP_REG_PTM_REQ_LOCAL_MSB_OFF_K2_E5                                                               0x0003e4UL //Access:RW   DataWidth:0x20   // PTM Requester Local Clock MSB. For more details, see the PTM section in the Databook.
+#define PCIEIP_REG_PTM_REQ_T1_LSB_OFF_K2_E5                                                                  0x0003e8UL //Access:R    DataWidth:0x20   // PTM Requester T1 Timestamp LSB. For more details, see the PTM section in the Databook.
+#define PCIEIP_REG_PTM_REQ_T1_MSB_OFF_K2_E5                                                                  0x0003ecUL //Access:R    DataWidth:0x20   // PTM Requester T1 Timestamp MSB. For more details, see the PTM section in the Databook.
+#define PCIEIP_REG_PTM_REQ_T1P_LSB_OFF_K2_E5                                                                 0x0003f0UL //Access:R    DataWidth:0x20   // PTM Requester T1 Previous Timestamp LSB. For more details, see the PTM section in the Databook.
+#define PCIEIP_REG_PTM_REQ_T1P_MSB_OFF_K2_E5                                                                 0x0003f4UL //Access:R    DataWidth:0x20   // PTM Requester T1 Previous Timestamp MSB. For more details, see the PTM section in the Databook.
+#define PCIEIP_REG_PTM_REQ_T4_LSB_OFF_K2_E5                                                                  0x0003f8UL //Access:R    DataWidth:0x20   // PTM Requester T4 Timestamp LSB. For more details, see the PTM section in the Databook.
+#define PCIEIP_REG_PTM_REQ_T4_MSB_OFF_K2_E5                                                                  0x0003fcUL //Access:R    DataWidth:0x20   // PTM Requester T4 Timestamp MSB. For more details, see the PTM section in the Databook.
+#define PCIEIP_REG_PTM_REQ_T4P_LSB_OFF_K2_E5                                                                 0x000400UL //Access:R    DataWidth:0x20   // PTM Requester T4 Previous Timestamp LSB. For more details, see the PTM section in the Databook.
+#define PCIEIP_REG_PTM_REQ_T4P_MSB_OFF_K2_E5                                                                 0x000404UL //Access:R    DataWidth:0x20   // PTM Requester T4 Previous Timestamp MSB. For more details, see the PTM section in the Databook.
+#define PCIEIP_REG_PTM_REQ_MASTER_LSB_OFF_K2_E5                                                              0x000408UL //Access:R    DataWidth:0x20   // PTM Requester Master Time LSB. For more details, see the PTM section in the Databook.
+#define PCIEIP_REG_CONFIG_2_BB                                                                               0x000408UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_CONFIG_2_BAR1_SIZE_BB                                                                   (0xf<<0) // These bits control the size of the BAR1 area advertised in the bar_1 register of the PCI configuration space. This value is sticky and only reset by HARD Reset. Default is 64K
+  #define PCIEIP_REG_CONFIG_2_BAR1_SIZE_BB_SHIFT                                                             0
+  #define PCIEIP_REG_CONFIG_2_BAR1_64ENA_BB                                                                  (0x1<<4) // This bit enables the advertisement of bar_1 as a 32-bit address. The value of this bit maps directly to bit 2 of bar_1. This value is sticky and only reset by HARD Reset. If set it is 64bit addressing.
+  #define PCIEIP_REG_CONFIG_2_BAR1_64ENA_BB_SHIFT                                                            4
+  #define PCIEIP_REG_CONFIG_2_EXP_ROM_RETRY_BB                                                               (0x1<<5) // This bit will force the PCI bus to re-try all cycles to the current Expansion ROM BAR area. When this bit is set, then no Expansion ROM interrupt will be generated. This bit must be cleared to allow the interrupt to be generated.
+  #define PCIEIP_REG_CONFIG_2_EXP_ROM_RETRY_BB_SHIFT                                                         5
+  #define PCIEIP_REG_CONFIG_2_CFG_CYCLE_RETRY_BB                                                             (0x1<<6) // This bit will force the PCI bus to re-try all cycles to the configuration space until it is cleared. This is used to block the host from accessing context if needed to prevent reading of false data. This bit may be used in combination with the FIRST_CFG_DONE bit below to prevent changing of the configuration space values after they have be read by the system. Normally this bit will be set by the firmware while the configuration space is programmed. This bit also exists in each VF and can be used to control individual VF.
+  #define PCIEIP_REG_CONFIG_2_CFG_CYCLE_RETRY_BB_SHIFT                                                       6
+  #define PCIEIP_REG_CONFIG_2_FIRST_CFG_DONE_BB                                                              (0x1<<7) // This bit will be set the first time since PCI reset that a configuration cycle hass been done by the PCI block. This may be used by firmware to detect if the host already has the reset values of the configuration space. this may happen if the NVM system is much slower than expected. Tn this case, the firmware can choose to not exist or show an error on LEDs, etc. instead of changing the configuratio space values that the host ahas already read.
+  #define PCIEIP_REG_CONFIG_2_FIRST_CFG_DONE_BB_SHIFT                                                        7
+  #define PCIEIP_REG_CONFIG_2_ROM_BAR_SIZE_BB                                                                (0xff<<8) // These bits control the size of the Expansion ROM area advertised in the Exp_ROM_BAR register of the PCI configuration space. When this value is non-zero, the Expansion ROM attention must be handled by an internal processor to move data between the Serial Non-Volatile Memory and the Expansion ROM interface. When the value is zero, the expansion ROM BAR will not advertize the presence of an expansion ROM.
+  #define PCIEIP_REG_CONFIG_2_ROM_BAR_SIZE_BB_SHIFT                                                          8
+  #define PCIEIP_REG_CONFIG_2_BAR_PREFETCH_BB                                                                (0x1<<16) // This bit when set is reflected in bit 3 of bar_1 and indicates that the BAR is pre-fetchable
+  #define PCIEIP_REG_CONFIG_2_BAR_PREFETCH_BB_SHIFT                                                          16
+  #define PCIEIP_REG_CONFIG_2_RESERVED0_BB                                                                   (0x7fff<<17) // 
+  #define PCIEIP_REG_CONFIG_2_RESERVED0_BB_SHIFT                                                             17
+#define PCIEIP_REG_PTM_REQ_MASTER_MSB_OFF_K2_E5                                                              0x00040cUL //Access:R    DataWidth:0x20   // PTM Requester Master Time MSB. For more details, see the PTM section in the Databook.
+#define PCIEIP_REG_CONFIG_3_BB                                                                               0x00040cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_CONFIG_3_STICKY_BYTE_BB                                                                 (0xff<<0) // This value is reset only reset by HARD Reset such that it can be used to detect initial power up if a non-zero value is written by the firmware after initialization. It has not hardware function other than reset type detection. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_CONFIG_3_STICKY_BYTE_BB_SHIFT                                                           0
+  #define PCIEIP_REG_CONFIG_3_REG_STICKY_BYTE_BB                                                             (0xff<<8) // This value is reset only by REG_HARD_RST.
+  #define PCIEIP_REG_CONFIG_3_REG_STICKY_BYTE_BB_SHIFT                                                       8
+  #define PCIEIP_REG_CONFIG_3_VF_MEM_DSICARD_BB                                                              (0x1<<16) // This bits exists in VF only Setting this bit to '1' forces the VF to drop any mem request that it receives. UR completion will be returned for mem read requests. This bit along with the CRS bit can be used by software to control when VF is up.
+  #define PCIEIP_REG_CONFIG_3_VF_MEM_DSICARD_BB_SHIFT                                                        16
+  #define PCIEIP_REG_CONFIG_3_UNUSED0_BB                                                                     (0x7f<<17) // 
+  #define PCIEIP_REG_CONFIG_3_UNUSED0_BB_SHIFT                                                               17
+  #define PCIEIP_REG_CONFIG_3_FORCE_PME_BB                                                                   (0x1<<24) // Setting this bit to '1' forces the PME message to be send This simulates the PME event. The PME control bits in the configuration space still control the output normally. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_CONFIG_3_FORCE_PME_BB_SHIFT                                                             24
+  #define PCIEIP_REG_CONFIG_3_PME_STATUS_BB                                                                  (0x1<<25) // This bit indicates the current state of the PME_STATUS bit in configuration space. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_CONFIG_3_PME_STATUS_BB_SHIFT                                                            25
+  #define PCIEIP_REG_CONFIG_3_PME_ENABLE_BB                                                                  (0x1<<26) // This is the current state of the PME_ENABLE bit in configuration space. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_CONFIG_3_PME_ENABLE_BB_SHIFT                                                            26
+  #define PCIEIP_REG_CONFIG_3_PM_STATE_BB                                                                    (0x3<<27) // This value interfaces to the PM_STATE value in the Power Management configuration space. Reads of this register return the last value written to the PM_STATE value in configuration space.
+  #define PCIEIP_REG_CONFIG_3_PM_STATE_BB_SHIFT                                                              27
+  #define PCIEIP_REG_CONFIG_3_UNUSED1_BB                                                                     (0x1<<29) // 
+  #define PCIEIP_REG_CONFIG_3_UNUSED1_BB_SHIFT                                                               29
+  #define PCIEIP_REG_CONFIG_3_VAUX_PRESENT_BB                                                                (0x1<<30) // This bit indicates the input level on the VAUX_PRESENT pin. This indicates if the VAUX supply is available in the current configuration. The value also controls the value of the Power Management PME_SUPPORT register in configuration space. Field is local in each PF
+  #define PCIEIP_REG_CONFIG_3_VAUX_PRESENT_BB_SHIFT                                                          30
+  #define PCIEIP_REG_CONFIG_3_PCI_POWER_BB                                                                   (0x1<<31) // PCI_POWER This bit indicates the current state of power on the PCI bus. If this bit is '1', it indicates that the PCI padring has power. If this bit is '0', it indicates that the PCI padring does not have power (D3 Cold).
+  #define PCIEIP_REG_CONFIG_3_PCI_POWER_BB_SHIFT                                                             31
+#define PCIEIP_REG_PTM_REQ_PROP_DELAY_OFF_K2_E5                                                              0x000410UL //Access:R    DataWidth:0x20   // PTM Requester Propagation Delay. For more details, see the PTM section in the Databook.
+#define PCIEIP_REG_PM_DATA_A_BB                                                                              0x000410UL //Access:RW   DataWidth:0x20   // This register controls the first 4 power management PM_Data read values
+  #define PCIEIP_REG_PM_DATA_A_PM_DATA_0_PRG_BB                                                              (0xff<<0) // This is the value read from the pm_data register when the DATA_SEL value in the PM_CSR register is 0. This is the power consumed in D0 state. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_PM_DATA_A_PM_DATA_0_PRG_BB_SHIFT                                                        0
+  #define PCIEIP_REG_PM_DATA_A_PM_DATA_1_PRG_BB                                                              (0xff<<8) // This is the value read from the pm_data register when the DATA_SEL value in the PM_CSR register is 1. This is the power consumed in D1 state. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_PM_DATA_A_PM_DATA_1_PRG_BB_SHIFT                                                        8
+  #define PCIEIP_REG_PM_DATA_A_PM_DATA_2_PRG_BB                                                              (0xff<<16) // This is the value read from the pm_data register when the DATA_SEL value in the PM_CSR register is 2. This is the power consumed in D2 state. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_PM_DATA_A_PM_DATA_2_PRG_BB_SHIFT                                                        16
+  #define PCIEIP_REG_PM_DATA_A_PM_DATA_3_PRG_BB                                                              (0xff<<24) // This is the value read from the pm_data register when the DATA_SEL value in the PM_CSR register is 3. This is the power consumed in D3 state. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_PM_DATA_A_PM_DATA_3_PRG_BB_SHIFT                                                        24
+#define PCIEIP_REG_PTM_REQ_MASTERT1_LSB_OFF_K2_E5                                                            0x000414UL //Access:R    DataWidth:0x20   // PTM Requester Master Time at T1 LSB. For more details, see the PTM section in the Databook.
+#define PCIEIP_REG_PM_DATA_B_BB                                                                              0x000414UL //Access:RW   DataWidth:0x20   // This register controls the second 4 power management PM_Data read values
+  #define PCIEIP_REG_PM_DATA_B_PM_DATA_4_PRG_BB                                                              (0xff<<0) // This is the value read from the pm_data register when the DATA_SEL value in the PM_CSR register is 4. This is the power dissipated in D0 state. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_PM_DATA_B_PM_DATA_4_PRG_BB_SHIFT                                                        0
+  #define PCIEIP_REG_PM_DATA_B_PM_DATA_5_PRG_BB                                                              (0xff<<8) // This is the value read from the pm_data register when the DATA_SEL value in the PM_CSR register is 5. This is the power dissipated in D1 state. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_PM_DATA_B_PM_DATA_5_PRG_BB_SHIFT                                                        8
+  #define PCIEIP_REG_PM_DATA_B_PM_DATA_6_PRG_BB                                                              (0xff<<16) // This is the value read from the pm_data register when the DATA_SEL value in the PM_CSR register is 6. This is the power dissipated in D2 state. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_PM_DATA_B_PM_DATA_6_PRG_BB_SHIFT                                                        16
+  #define PCIEIP_REG_PM_DATA_B_PM_DATA_7_PRG_BB                                                              (0xff<<24) // This is the value read from the pm_data register when the DATA_SEL value in the PM_CSR register is 7. This is the power dissipated in D3 state. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_PM_DATA_B_PM_DATA_7_PRG_BB_SHIFT                                                        24
+#define PCIEIP_REG_PTM_REQ_MASTERT1_MSB_OFF_K2_E5                                                            0x000418UL //Access:R    DataWidth:0x20   // PTM Requester Master Time at T1 MSB. For more details, see the PTM section in the Databook.
+#define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BB                                                                   0x000418UL //Access:RW   DataWidth:0x20   // This register controls the higher bar size advertizements, when a bar size greater than 1G is desired.
+  #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR1_SIZE_HIEXT_BB                                                 (0xf<<0) // These bits control the size of the BAR1 area advertised in the bar_1 register of the PCI configuration space. This value is sticky and only reset by HARD Reset. These bits are programmed when a BAR size greater than 1GB is desired. When requiring a BAR size greater than 1 GB, the corresponding bar1_size bits should be programmed to 0xF.
+  #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR1_SIZE_HIEXT_BB_SHIFT                                           0
+  #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR2_SIZE_HIEXT_BB                                                 (0xf<<4) // These bits control the size of the BAR2 area advertised in the bar_3 register of the PCI configuration space. This value is sticky and only reset by HARD Reset. These bits are programmed when a BAR size greater than 1GB is desired. When requiring a BAR size greater than 1 GB, the corresponding bar2_size bits should be programmed to 0xF.
+  #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR2_SIZE_HIEXT_BB_SHIFT                                           4
+  #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR3_SIZE_HIEXT_BB                                                 (0xf<<8) // These bits control the size of the BAR3 area advertised in the bar_5 register of the PCI configuration space. This value is sticky and only reset by HARD Reset. These bits are programmed when a BAR size greater than 1GB is desired. When requiring a BAR size greater than 1 GB, the corresponding bar3_size bits should be programmed to 0xF.
+  #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR3_SIZE_HIEXT_BB_SHIFT                                           8
+  #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR1_SIZE_LOEXT_BB                                                 (0x7<<12) // These bits control the size of the BAR1 area advertised in the bar_1 register of the PCI configuration space. This value is sticky and only reset by HARD Reset. These bits are programmed when a BAR size lower than 64K is desired. When requiring a BAR size smaller than 64K , the corresponding bar_size bits should be programmed to 0x0, as also the bar1_size_hiext bits. If desiring a bar size greater than 32K, then the bar1_size_loext bits need to be 0.
+  #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR1_SIZE_LOEXT_BB_SHIFT                                           12
+  #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_UNUSED0_BB                                                         (0x1<<15) // 
+  #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_UNUSED0_BB_SHIFT                                                   15
+  #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR2_SIZE_LOEXT_BB                                                 (0x7<<16) // These bits control the size of the BAR2 area advertised in the bar_3 register of the PCI configuration space. This value is sticky and only reset by HARD Reset. These bits are programmed when a BAR size lower than 64K is desired. When requiring a BAR size smaller than 64K , the corresponding bar2_size bits should be programmed to 0x0, as also the bar1_size_hiext bits. If desiring a bar size greater than 32K, then the bar1_size_loext bits need to be 0.
+  #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR2_SIZE_LOEXT_BB_SHIFT                                           16
+  #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR3_SIZE_LOEXT_BB                                                 (0x7<<19) // These bits control the size of the BAR3 area advertised in the bar_5 register of the PCI configuration space. This value is sticky and only reset by HARD Reset. These bits are programmed when a BAR size lower than 64K is desired. When requiring a BAR size smaller than 64K , the corresponding bar3_size bits should be programmed to 0x0, as also the bar1_size_hiext bits. If desiring a bar size greater than 32K, then the bar1_size_loext bits need to be 0.
+  #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR3_SIZE_LOEXT_BB_SHIFT                                           19
+#define PCIEIP_REG_PTM_REQ_TX_LATENCY_OFF_K2_E5                                                              0x00041cUL //Access:RW   DataWidth:0x20   // PTM Requester TX Latency. For more details, see the PTM section in the Databook.
+  #define PCIEIP_REG_PTM_REQ_TX_LATENCY_OFF_PTM_REQ_TX_LATENCY_K2_E5                                         (0xfff<<0) // PTM Requester TX Latency - Requester Transmit path latency (12 bit wide). For more details, see the PTM section in the Databook.  Note: This register field is sticky.
+  #define PCIEIP_REG_PTM_REQ_TX_LATENCY_OFF_PTM_REQ_TX_LATENCY_K2_E5_SHIFT                                   0
+#define PCIEIP_REG_PTM_REQ_RX_LATENCY_OFF_K2_E5                                                              0x000420UL //Access:RW   DataWidth:0x20   // PTM Requester RX Latency. For more details, see the PTM section in the Databook.
+  #define PCIEIP_REG_PTM_REQ_RX_LATENCY_OFF_PTM_REQ_RX_LATENCY_K2_E5                                         (0xfff<<0) // PTM Requester RX Latency - Requester Receive path latency (12 bit wide). For more details, see the PTM section in the Databook.  Note: This register field is sticky.
+  #define PCIEIP_REG_PTM_REQ_RX_LATENCY_OFF_PTM_REQ_RX_LATENCY_K2_E5_SHIFT                                   0
+#define PCIEIP_REG_RESBAR_CAP_HDR_REG_K2_E5                                                                  0x000424UL //Access:RW   DataWidth:0x20   // Resizable BAR Capability Header.
+  #define PCIEIP_REG_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_K2_E5                                              (0xffff<<0) // Resizable BAR Extended Capability ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_K2_E5_SHIFT                                        0
+  #define PCIEIP_REG_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_K2_E5                                             (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_K2_E5_SHIFT                                       16
+  #define PCIEIP_REG_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_K2_E5                                         (0xfff<<20) // Next Capability Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_K2_E5_SHIFT                                   20
+#define PCIEIP_REG_RESBAR_CAP_REG_0_REG_K2_E5                                                                0x000428UL //Access:RW   DataWidth:0x20   // Resizable BAR0 Capability Register.
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_K2_E5                                         (0x1<<4) // Up to 1MB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_K2_E5_SHIFT                                   4
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_K2_E5                                         (0x1<<5) // Up to 2MB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_K2_E5_SHIFT                                   5
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_K2_E5                                         (0x1<<6) // Up to 4MB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_K2_E5_SHIFT                                   6
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_K2_E5                                         (0x1<<7) // Up to 8MB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_K2_E5_SHIFT                                   7
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_K2_E5                                        (0x1<<8) // Up to 16MB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_K2_E5_SHIFT                                  8
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_K2_E5                                        (0x1<<9) // Up to 32MB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_K2_E5_SHIFT                                  9
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_K2_E5                                        (0x1<<10) // Up to 64MB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_K2_E5_SHIFT                                  10
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_K2_E5                                       (0x1<<11) // Up to 128MB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_K2_E5_SHIFT                                 11
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_K2_E5                                       (0x1<<12) // Up to 256MB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_K2_E5_SHIFT                                 12
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_K2_E5                                       (0x1<<13) // Up to 512MB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_K2_E5_SHIFT                                 13
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_K2_E5                                         (0x1<<14) // Up to 1GB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_K2_E5_SHIFT                                   14
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_K2_E5                                         (0x1<<15) // Up to 2GB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_K2_E5_SHIFT                                   15
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_K2_E5                                         (0x1<<16) // Up to 4GB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_K2_E5_SHIFT                                   16
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_K2_E5                                         (0x1<<17) // Up to 8GB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_K2_E5_SHIFT                                   17
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_K2_E5                                        (0x1<<18) // Up to 16GB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_K2_E5_SHIFT                                  18
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_K2_E5                                        (0x1<<19) // Up to 32GB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_K2_E5_SHIFT                                  19
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_K2_E5                                        (0x1<<20) // Up to 64GB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_K2_E5_SHIFT                                  20
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_K2_E5                                       (0x1<<21) // Up to 128GB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_K2_E5_SHIFT                                 21
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_K2_E5                                       (0x1<<22) // Up to 256GB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_K2_E5_SHIFT                                 22
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_K2_E5                                       (0x1<<23) // Up to 512GB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_K2_E5_SHIFT                                 23
+#define PCIEIP_REG_REG_VPD_INTF_BB                                                                           0x000428UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_VPD_INTF_INTF_REQ_BB                                                                (0x1<<0) // This bit will be set if there is a pending request for action by the firmware to handle a Vital Product Data interface. This bit is set when the vpd_flag_addr register in configuation space is written. This bit is cleared when the vpd_data register below is written.
+  #define PCIEIP_REG_REG_VPD_INTF_INTF_REQ_BB_SHIFT                                                          0
+#define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_K2_E5                                                               0x00042cUL //Access:RW   DataWidth:0x20   // Resizable BAR0 Control Register.
+  #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_K2_E5                                       (0x7<<0) // BAR Index.   Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_K2_E5_SHIFT                                 0
+  #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_K2_E5                                    (0x7<<5) // Number of Resizeable BARs.   Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_K2_E5_SHIFT                              5
+  #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_K2_E5                                    (0x1f<<8) // BAR Size.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_K2_E5_SHIFT                              8
+#define PCIEIP_REG_REG_VPD_ADDR_FLAG_BB                                                                      0x00042cUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_VPD_ADDR_FLAG_UNUSED0_BB                                                            (0x3ffff<<0) // 
+  #define PCIEIP_REG_REG_VPD_ADDR_FLAG_UNUSED0_BB_SHIFT                                                      0
+  #define PCIEIP_REG_REG_VPD_ADDR_FLAG_ADDRESS_BB                                                            (0x1fff<<18) // This value is the byte address of the VPD value being requested by the host in the vpd_flag_addr register of the configuration space.
+  #define PCIEIP_REG_REG_VPD_ADDR_FLAG_ADDRESS_BB_SHIFT                                                      18
+  #define PCIEIP_REG_REG_VPD_ADDR_FLAG_WR_BB                                                                 (0x1<<31) // This bit indicates if the host is requesting a read or a write cycle. If this bit is set, then the host has requested the data in the vpd_data register to be passed to the NVM interface. If the value is clear, then the host has requested the data to be passed from the NVM interface to the vpd_data register. The value of this bit is only valid if the INTF_REQ bit is set. This bit is a RO copy of the flag bit in the vpd_flag_addr register in configuration space.
+  #define PCIEIP_REG_REG_VPD_ADDR_FLAG_WR_BB_SHIFT                                                           31
+#define PCIEIP_REG_REG_VPD_DATA_BB                                                                           0x000430UL //Access:RW   DataWidth:0x20   // This is the data register for passing values between the NVM interface and the vpd_data register in the configuration space. When INTF_REQ is '1' and the WR bit is clear, this word should be written with the NVM data requested in the ADDRESS value to clear the INTF_REQ bit. When INTF_REQ is '1' and the WR bit is set, this word should be read and written to the NVM interface. After the NVM interface write is complete, this value should be written with the same value to clear the INTF_REQ bit. When this value is written and the INTF_REQ bit is set, the FLAG bit in the vpd_flag_addr register in configurationspace will be complemented.
+#define PCIEIP_REG_REG_ID_VAL1_BB                                                                            0x000434UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_ID_VAL1_DEVICE_ID_BB                                                                (0xffff<<0) // This register programs the read value of the device_id register of the configuration space. The hardware default value is the Broadcom vendor ID. This value is sticky and only reset by HARD Reset. The default value reflects the value of DEVICE_ID in version.v defined by user or the strap pins user_device_id if user relies on straps.
+  #define PCIEIP_REG_REG_ID_VAL1_DEVICE_ID_BB_SHIFT                                                          0
+  #define PCIEIP_REG_REG_ID_VAL1_VENDOR_ID_BB                                                                (0xffff<<16) // This register programs the read value of the vendor_id register of the configuration space. The hardware default value is the Broadcom vendor ID. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_REG_ID_VAL1_VENDOR_ID_BB_SHIFT                                                          16
+#define PCIEIP_REG_REG_ID_VAL2_BB                                                                            0x000438UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_ID_VAL2_SUBSYSTEM_VENDOR_ID_BB                                                      (0xffff<<0) // This value controls the read value of the subsystem_vendor_id value in the configuration space. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_REG_ID_VAL2_SUBSYSTEM_VENDOR_ID_BB_SHIFT                                                0
+  #define PCIEIP_REG_REG_ID_VAL2_SUBSYSTEM_ID_BB                                                             (0xffff<<16) // This value controls the read value of the subsystem_id value in the configuration space. This value is sticky and only reset by HARD Reset. The default value reflects the value of DEVICE_ID in version.v defined by user or the strap pins user_device_id if user relies on straps.
+  #define PCIEIP_REG_REG_ID_VAL2_SUBSYSTEM_ID_BB_SHIFT                                                       16
+#define PCIEIP_REG_REG_ID_VAL3_BB                                                                            0x00043cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_ID_VAL3_CLASS_CODE_BB                                                               (0xffffff<<0) // This register programs the read value of the class_code register of the configuration space. The 24-bit Class Code register identifies the generic function of the device. All of the legal values are specific in the PCI specification. The default value for this register is the class code for an Ethernet interface (0x020000). This value is sticky and only reset by HARD Reset. The default value reflects the value of CLASS_CODE in version.v defined by user.
+  #define PCIEIP_REG_REG_ID_VAL3_CLASS_CODE_BB_SHIFT                                                         0
+  #define PCIEIP_REG_REG_ID_VAL3_REVISION_ID_BB                                                              (0xff<<24) // This register programs the read value of the revision_id register of the configuration space. The default value is provided by user_revision_id strap pins. This field also exists in VF register space
+  #define PCIEIP_REG_REG_ID_VAL3_REVISION_ID_BB_SHIFT                                                        24
+#define PCIEIP_REG_REG_ID_VAL4_BB                                                                            0x000440UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_ID_VAL4_CAP_ENA_BB                                                                  (0xf<<0) // This value controls the read value of the next capability pointers in the PCIE configuration space and allows each extra capability to be independently disabled by manipulation of the next pointer values. The read values for each enable combination is shown below. PCIE capability is always enabled. Bit 0 enables the Power Management capability. Bit 1 enables the VPD capability, and Bit 2 enables the MSI capability and Bit3 is MSIX capability This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_REG_ID_VAL4_CAP_ENA_BB_SHIFT                                                            0
+  #define PCIEIP_REG_REG_ID_VAL4_UNUSED0_BB                                                                  (0x3<<4) // 
+  #define PCIEIP_REG_REG_ID_VAL4_UNUSED0_BB_SHIFT                                                            4
+  #define PCIEIP_REG_REG_ID_VAL4_PM_DATA_SCALE_BB                                                            (0x3<<6) // This value is read as the DATA_SCALE value in the Power Management CSR register in the PCI Configuration address space. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_REG_ID_VAL4_PM_DATA_SCALE_BB_SHIFT                                                      6
+  #define PCIEIP_REG_REG_ID_VAL4_MSI_PV_MASK_CAPABLE_BB                                                      (0x1<<8) // This value controls the per vector masking capability in the MSI control field
+  #define PCIEIP_REG_REG_ID_VAL4_MSI_PV_MASK_CAPABLE_BB_SHIFT                                                8
+  #define PCIEIP_REG_REG_ID_VAL4_MSI_LIMIT_BB                                                                (0x7<<9) // This value reports the MSI value that is programmed in the PCI configuration space. This value will always be equal or less than what was advertised. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_REG_ID_VAL4_MSI_LIMIT_BB_SHIFT                                                          9
+  #define PCIEIP_REG_REG_ID_VAL4_MULTI_MSG_CAP_BB                                                            (0x7<<12) // This value controls the read value of the MSI_CTRL_MCAP value in the PCI configuration space. The default is 0, which is one MSI. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_REG_ID_VAL4_MULTI_MSG_CAP_BB_SHIFT                                                      12
+  #define PCIEIP_REG_REG_ID_VAL4_MSI_ENABLE_BB                                                               (0x1<<15) // This bit indicates the programming of the MSI Enable bit in PCI configuration space. If this bit is set, it means that the interrupt output is masked and all interrupts must be indicated with MSI cycles.
+  #define PCIEIP_REG_REG_ID_VAL4_MSI_ENABLE_BB_SHIFT                                                         15
+  #define PCIEIP_REG_REG_ID_VAL4_RESERVED3_BB                                                                (0xffff<<16) // 
+  #define PCIEIP_REG_REG_ID_VAL4_RESERVED3_BB_SHIFT                                                          16
+#define PCIEIP_REG_REG_ID_VAL5_BB                                                                            0x000444UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_ID_VAL5_D1_SUPPORT_BB                                                               (0x1<<0) // This bit indicates whether the device supports the D1 power management state. It is reflected in the D1_SUPPORT bit in the configuration space. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_REG_ID_VAL5_D1_SUPPORT_BB_SHIFT                                                         0
+  #define PCIEIP_REG_REG_ID_VAL5_D2_SUPPORT_BB                                                               (0x1<<1) // This bit indicates whether the device supports the D2 power management state. It is reflected in the D2_SUPPORT bit in the configuration space. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_REG_ID_VAL5_D2_SUPPORT_BB_SHIFT                                                         1
+  #define PCIEIP_REG_REG_ID_VAL5_PME_IN_D0_BB                                                                (0x1<<2) // This bit indicates whether the device supports transmiting PME message from the D0 power state. It is reflected in the PME_IN_D0 bit in the configuration space. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_REG_ID_VAL5_PME_IN_D0_BB_SHIFT                                                          2
+  #define PCIEIP_REG_REG_ID_VAL5_PME_IN_D1_BB                                                                (0x1<<3) // This bit indicates whether the device supports transmiting PME message from the D1 power state. It is reflected in the PME_IN_D1 bit in the configuration space. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_REG_ID_VAL5_PME_IN_D1_BB_SHIFT                                                          3
+  #define PCIEIP_REG_REG_ID_VAL5_PME_IN_D2_BB                                                                (0x1<<4) // This bit indicates whether the device supports transmiting PME message from the D2 power state. It is reflected in the PME_IN_D2 bit in the configuration space. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_REG_ID_VAL5_PME_IN_D2_BB_SHIFT                                                          4
+  #define PCIEIP_REG_REG_ID_VAL5_PME_IN_D3_HOT_BB                                                            (0x1<<5) // This bit indicates whether the device supports transmiting PME message from the D3hot power state. It is reflected in the PME_IN_D3_HOT bit in the configuration space. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_REG_ID_VAL5_PME_IN_D3_HOT_BB_SHIFT                                                      5
+  #define PCIEIP_REG_REG_ID_VAL5_PM_VERSION_BB                                                               (0x7<<6) // The value indicates the function complies with which revision of PCI PM spec. This value is reflected in corresponding field in PM capabilities register
+  #define PCIEIP_REG_REG_ID_VAL5_PM_VERSION_BB_SHIFT                                                         6
+  #define PCIEIP_REG_REG_ID_VAL5_NO_SOFT_RESET_BB                                                            (0x1<<9) // This indicates function does not perform an internal reset when transitioning from D3 to D0. the value is reflected in corresponding field in PM CSR.
+  #define PCIEIP_REG_REG_ID_VAL5_NO_SOFT_RESET_BB_SHIFT                                                      9
+  #define PCIEIP_REG_REG_ID_VAL5_RESERVED0_BB                                                                (0x3fffff<<10) // 
+  #define PCIEIP_REG_REG_ID_VAL5_RESERVED0_BB_SHIFT                                                          10
+#define PCIEIP_REG_REG_ID_VAL6_BB                                                                            0x00044cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_ID_VAL6_UNUSED0_BB                                                                  (0xffff<<0) // 
+  #define PCIEIP_REG_REG_ID_VAL6_UNUSED0_BB_SHIFT                                                            0
+  #define PCIEIP_REG_REG_ID_VAL6_BIST_BB                                                                     (0xff<<16) // This register controls the read value of the bist register in the configuration space. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_REG_ID_VAL6_BIST_BB_SHIFT                                                               16
+#define PCIEIP_REG_REG_MSI_DATA_BB                                                                           0x000450UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_MSI_DATA_MSI_DATA_BB                                                                (0xffff<<0) // This register reflects the MSI data register value in the configuration space. This value may be used by the completion processor to determine the data value it will use for vectored MSI cycles.
+  #define PCIEIP_REG_REG_MSI_DATA_MSI_DATA_BB_SHIFT                                                          0
+#define PCIEIP_REG_REG_MSI_ADDR_H_BB                                                                         0x000454UL //Access:R    DataWidth:0x20   // This register reflects the upper half of the MSI address register value in the configuration space. This value may be used by the completion processor to determine the address value it will use for vectored MSI cycles.
+#define PCIEIP_REG_REG_MSI_ADDR_L_BB                                                                         0x000458UL //Access:R    DataWidth:0x20   // This register reflects the lower half of the MSI address bit[31:2] value in the configuration space. The lower two bits [1:0] are hard wired to zero. This value may be used by the completion processor to determine the address value it will use for vectored MSI cycles.
+#define PCIEIP_REG_REG_MSI_MASK_BB                                                                           0x000464UL //Access:R    DataWidth:0x20   // This register reflects the MSI mask register value in the configuration space
+#define PCIEIP_REG_REG_MSI_PEND_BB                                                                           0x000468UL //Access:RW   DataWidth:0x20   // Each pending bit that is set , the function has a pending associated message. This register gets reflected in the configuration space.
+#define PCIEIP_REG_REG_PM_DATA_C_BB                                                                          0x00046cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PM_DATA_C_PM_DATA_8_PRG_BB                                                          (0xff<<0) // This is the value read from the pm_data register when the DATA_SEL value in the PM_CSR register is 8. This is the power dissipated by common logic in case of multi function devices. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_REG_PM_DATA_C_PM_DATA_8_PRG_BB_SHIFT                                                    0
+  #define PCIEIP_REG_REG_PM_DATA_C_RESERVED0_BB                                                              (0xffffff<<8) // 
+  #define PCIEIP_REG_REG_PM_DATA_C_RESERVED0_BB_SHIFT                                                        8
+#define PCIEIP_REG_REG_MSIX_CONTROL_BB                                                                       0x0004c0UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_MSIX_CONTROL_MSIX_TBL_SIZ_BB                                                        (0x7ff<<0) // This register controls the read value of the MSIX_CONTROL[10:0] register in the configuration space. A value of "00000000011" indicates a table size of 4 Lower 6 bits of this field also exists in VF register space
+  #define PCIEIP_REG_REG_MSIX_CONTROL_MSIX_TBL_SIZ_BB_SHIFT                                                  0
+  #define PCIEIP_REG_REG_MSIX_CONTROL_RESERVED0_BB                                                           (0x1fffff<<11) // 
+  #define PCIEIP_REG_REG_MSIX_CONTROL_RESERVED0_BB_SHIFT                                                     11
+#define PCIEIP_REG_REG_MSIX_TBL_OFF_BIR_BB                                                                   0x0004c4UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR_BB                                                    (0x7<<0) // This register controls the read value of the MSIX_TBL_OFF_BIR[2:0] register. This indicates which one of the function's Base address registers located at 10h in configuration space is used to map the function's MSI-X table into memory space. Value is controlled by PCIE_MSIX_TBL_OFF field in version.v
+  #define PCIEIP_REG_REG_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR_BB_SHIFT                                              0
+  #define PCIEIP_REG_REG_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF_BB                                                    (0x1fffffff<<3) // This register controls the read value of the MSIX_TBL_OFF_BIR[31:3] register. This is used as an offset from the address contained by one of the functions Base address registers to point to the base of the MSI-X table. Value is controlled by PCIE_MSIX_TBL_OFF field in version.v
+  #define PCIEIP_REG_REG_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF_BB_SHIFT                                              3
+#define PCIEIP_REG_REG_MSIX_PBA_OFF_BIR_BB                                                                   0x0004c8UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_MSIX_PBA_OFF_BIR_MSIX_PBA_BIR_BB                                                    (0x7<<0) // This register controls the read value of the MSIX_PBA_OFF_BIR[2:0] register. This indicates which one of the function's Base address registers located at 10h in configuration space is used to map the function's MSI-X PBA into memory space. Value is controlled by PCIE_MSIX_PBA_OFF field in version.v
+  #define PCIEIP_REG_REG_MSIX_PBA_OFF_BIR_MSIX_PBA_BIR_BB_SHIFT                                              0
+  #define PCIEIP_REG_REG_MSIX_PBA_OFF_BIR_MSIX_PBA_OFF_BB                                                    (0x1fffffff<<3) // This register controls the read value of the MSIX_PBA_OFF_BIR[31:3] register. This is used as an offset from the address contained by one of the functions Base address registers to point to the base of the MSI-X PBA Value is controlled by PCIE_MSIX_PBA_OFF field in version.v
+  #define PCIEIP_REG_REG_MSIX_PBA_OFF_BIR_MSIX_PBA_OFF_BB_SHIFT                                              3
+#define PCIEIP_REG_REG_PCIE_CAPABILITY_BB                                                                    0x0004d0UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PCIE_CAPABILITY_INTERRUPT_MSG_NUM_BB                                                (0x1f<<0) // This controls the value in configuration space
+  #define PCIEIP_REG_REG_PCIE_CAPABILITY_INTERRUPT_MSG_NUM_BB_SHIFT                                          0
+  #define PCIEIP_REG_REG_PCIE_CAPABILITY_COMPLY_PCIE_1_1_BB                                                  (0x1<<5) // This bit when set, hides any PCIE spec 2.0 defined registers (bits) and enables design to be 1.1 compliant
+  #define PCIEIP_REG_REG_PCIE_CAPABILITY_COMPLY_PCIE_1_1_BB_SHIFT                                            5
+  #define PCIEIP_REG_REG_PCIE_CAPABILITY_ASPM_OPTIONALITY_BB                                                 (0x1<<6) // This bit when set, sets the ASPM optionality bit in the Link cap register. This bit is recommended to be set for newer PCIe devices and required for 3.0 compliant devices
+  #define PCIEIP_REG_REG_PCIE_CAPABILITY_ASPM_OPTIONALITY_BB_SHIFT                                           6
+#define PCIEIP_REG_REG_DEVICE_CAPABILITY_BB                                                                  0x0004d4UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED_BB                                          (0x7<<0) // This controls the value of this field in the DEVICE_CAP register in the configuration space
+  #define PCIEIP_REG_REG_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED_BB_SHIFT                                    0
+  #define PCIEIP_REG_REG_DEVICE_CAPABILITY_UNUSED0_BB                                                        (0x3<<3) // 
+  #define PCIEIP_REG_REG_DEVICE_CAPABILITY_UNUSED0_BB_SHIFT                                                  3
+  #define PCIEIP_REG_REG_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT_BB                                           (0x1<<5) // This controls the value of this field in the DEVICE_CAP register in the configuration field
+  #define PCIEIP_REG_REG_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT_BB_SHIFT                                     5
+  #define PCIEIP_REG_REG_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY_BB                                         (0x7<<6) // This controls the value of this field in the configuration space
+  #define PCIEIP_REG_REG_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY_BB_SHIFT                                   6
+  #define PCIEIP_REG_REG_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY_BB                                          (0x7<<9) // This controls the value in the configuration space
+  #define PCIEIP_REG_REG_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY_BB_SHIFT                                    9
+  #define PCIEIP_REG_REG_DEVICE_CAPABILITY_UNUSED1_BB                                                        (0x7<<12) // 
+  #define PCIEIP_REG_REG_DEVICE_CAPABILITY_UNUSED1_BB_SHIFT                                                  12
+  #define PCIEIP_REG_REG_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT_BB                                             (0x1<<15) // This controls value in configuration space
+  #define PCIEIP_REG_REG_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT_BB_SHIFT                                       15
+  #define PCIEIP_REG_REG_DEVICE_CAPABILITY_UNUSED2_BB                                                        (0xfff<<16) // 
+  #define PCIEIP_REG_REG_DEVICE_CAPABILITY_UNUSED2_BB_SHIFT                                                  16
+  #define PCIEIP_REG_REG_DEVICE_CAPABILITY_FLR_SUPPORTED_BB                                                  (0x1<<28) // This controls value in configuration space and allows FLR capability to be advertized by DUT.
+  #define PCIEIP_REG_REG_DEVICE_CAPABILITY_FLR_SUPPORTED_BB_SHIFT                                            28
+#define PCIEIP_REG_REG_DEVICE_CONTROL_BB                                                                     0x0004d8UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_DEVICE_CONTROL_UNUSED0_BB                                                           (0x7ffffff<<0) // 
+  #define PCIEIP_REG_REG_DEVICE_CONTROL_UNUSED0_BB_SHIFT                                                     0
+  #define PCIEIP_REG_REG_DEVICE_CONTROL_FLR_IN_PROGRESS_BB                                                   (0x1<<27) // When FLR is initiated, this register will read a value of 1 indicating that the Function is in FLR state. Func can be brought out of FLR state either by writing 1 to this register (at least 50 ms after FLR was initiated), or it can also be cleared automatically after 55 ms if auto_clear bit in private reg space is set. This bit also exists in VF register space
+  #define PCIEIP_REG_REG_DEVICE_CONTROL_FLR_IN_PROGRESS_BB_SHIFT                                             27
+  #define PCIEIP_REG_REG_DEVICE_CONTROL_UNUSED1_BB                                                           (0x1<<28) // 
+  #define PCIEIP_REG_REG_DEVICE_CONTROL_UNUSED1_BB_SHIFT                                                     28
+  #define PCIEIP_REG_REG_DEVICE_CONTROL_SRIOV_DISABLE_IN_PROGRESS_BB                                         (0x1<<29) // When VF Enable is cleared(after it was previously set), this register will read a value of 1, indicating that all the VFs that belong to this PF should be flushed. Software should clear this bit within 1 second of VF Enable being set by writing a 1 to it, so that VFs are visible to the system again.
+  #define PCIEIP_REG_REG_DEVICE_CONTROL_SRIOV_DISABLE_IN_PROGRESS_BB_SHIFT                                   29
+#define PCIEIP_REG_REG_LINK_CAPABILITY_BB                                                                    0x0004dcUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_LINK_CAPABILITY_MAX_LINK_SPEED_BB                                                   (0xf<<0) // This controls the value of the same field in the link_capability register in configuration space.This also controls the variables advertised by the PHY such as FTS ordered sets etc.
+  #define PCIEIP_REG_REG_LINK_CAPABILITY_MAX_LINK_SPEED_BB_SHIFT                                             0
+  #define PCIEIP_REG_REG_LINK_CAPABILITY_MAX_LINK_WIDTH_BB                                                   (0x1f<<4) // This controls the value of the same field in the link_capability register in configuration space
+  #define PCIEIP_REG_REG_LINK_CAPABILITY_MAX_LINK_WIDTH_BB_SHIFT                                             4
+  #define PCIEIP_REG_REG_LINK_CAPABILITY_CLK_POWER_MGMT_BB                                                   (0x1<<9) // This controls the value of the same field in the link_capability register in configuration space
+  #define PCIEIP_REG_REG_LINK_CAPABILITY_CLK_POWER_MGMT_BB_SHIFT                                             9
+  #define PCIEIP_REG_REG_LINK_CAPABILITY_ASPM_SUPPORT_BB                                                     (0x3<<10) // This controls the value of the same field in the link_capability register in configuration space
+  #define PCIEIP_REG_REG_LINK_CAPABILITY_ASPM_SUPPORT_BB_SHIFT                                               10
+  #define PCIEIP_REG_REG_LINK_CAPABILITY_L0S_EXIT_LAT_BB                                                     (0x7<<12) // This controls the value of the same field in the link_capability register in configuration space
+  #define PCIEIP_REG_REG_LINK_CAPABILITY_L0S_EXIT_LAT_BB_SHIFT                                               12
+  #define PCIEIP_REG_REG_LINK_CAPABILITY_L1_EXIT_LAT_BB                                                      (0x7<<15) // This controls the value of the same field in the link_capability register in configuration space
+  #define PCIEIP_REG_REG_LINK_CAPABILITY_L1_EXIT_LAT_BB_SHIFT                                                15
+  #define PCIEIP_REG_REG_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_BB                                                (0x7<<18) // This controls the value of the same field in the link_capability register in configuration space
+  #define PCIEIP_REG_REG_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_BB_SHIFT                                          18
+  #define PCIEIP_REG_REG_LINK_CAPABILITY_L1_EXIT_COMM_LAT_BB                                                 (0x7<<21) // This controls the value of the same field in the link_capability register in configuration space
+  #define PCIEIP_REG_REG_LINK_CAPABILITY_L1_EXIT_COMM_LAT_BB_SHIFT                                           21
+  #define PCIEIP_REG_REG_LINK_CAPABILITY_PORT_NUM_BB                                                         (0xff<<24) // This controls the value of the same field in the link_capability register in configuration space
+  #define PCIEIP_REG_REG_LINK_CAPABILITY_PORT_NUM_BB_SHIFT                                                   24
+#define PCIEIP_REG_REG_BAR2_CONFIG_BB                                                                        0x0004e0UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_BAR2_CONFIG_BAR2_SIZE_BB                                                            (0xf<<0) // These bits control the size of the BAR2 area advertised in the bar_3 register of the PCI configuration space. This value is sticky and only reset by HARD Reset. Default is 64K bytes.
+  #define PCIEIP_REG_REG_BAR2_CONFIG_BAR2_SIZE_BB_SHIFT                                                      0
+  #define PCIEIP_REG_REG_BAR2_CONFIG_BAR2_64ENA_BB                                                           (0x1<<4) // This bit enables the advertisement of bar_3 as a 32-bit address. The value of this bit maps directly to bit 2 of bar_3. This value is sticky and only reset by HARD Reset. Default is 64bit addressing.
+  #define PCIEIP_REG_REG_BAR2_CONFIG_BAR2_64ENA_BB_SHIFT                                                     4
+  #define PCIEIP_REG_REG_BAR2_CONFIG_BAR2_PREFETCH_BB                                                        (0x1<<5) // This bit when set is reflected in bit 3 of bar_3 and indicates that the BAR is pre-fetchable
+  #define PCIEIP_REG_REG_BAR2_CONFIG_BAR2_PREFETCH_BB_SHIFT                                                  5
+  #define PCIEIP_REG_REG_BAR2_CONFIG_RESERVED_BB                                                             (0x3ffffff<<6) // 
+  #define PCIEIP_REG_REG_BAR2_CONFIG_RESERVED_BB_SHIFT                                                       6
+#define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_BB                                                           0x0004e4UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP_BB                                      (0xf<<0) // Completion Timeout Ranges Supported. Controls value in same field in the config space 0xF- Ranges A,B,C and D
+  #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP_BB_SHIFT                                0
+  #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP_BB                                     (0x1<<4) // Completion Timeout Disable Supported, Controls value in same field in the config space
+  #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP_BB_SHIFT                               4
+  #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_RESERVED1_BB                                               (0x1f<<5) // unused
+  #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_RESERVED1_BB_SHIFT                                         5
+  #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_IDO_SUPPORTED_BB                                           (0x1<<10) // This bit is valid only if IDO_Enabled is defined in version.v. When this bit is set, IDO feature is made visible to external config access.
+  #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_IDO_SUPPORTED_BB_SHIFT                                     10
+  #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_UNUSED0_BB                                                 (0x7f<<11) // 
+  #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_UNUSED0_BB_SHIFT                                           11
+  #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_OBFF_SUPPORTED_BB                                          (0x3<<18) // This indicates that OBFF is supported using WAKE# signalling only. It is recommended to set this value to 2 or 3(also supported using Messages) This bit is valid only if PCIE_OBFF_SUPP is defined in version.v. When this bit is set, OBFF feature is made visible to external config access.
+  #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_OBFF_SUPPORTED_BB_SHIFT                                    18
+  #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_RESERVED_BB                                                (0xfff<<20) // unused
+  #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_RESERVED_BB_SHIFT                                          20
+#define PCIEIP_REG_REG_PCIE_LINK_CAPABILITY_2_BB                                                             0x0004e8UL //Access:RW   DataWidth:0x20   // Place holder for now
+#define PCIEIP_REG_REG_PCIE_LINK_CONTROL_BB                                                                  0x0004ecUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PCIE_LINK_CONTROL_RC_RCB_BB                                                         (0x1<<0) // Not supported for EP
+  #define PCIEIP_REG_REG_PCIE_LINK_CONTROL_RC_RCB_BB_SHIFT                                                   0
+#define PCIEIP_REG_REG_PCIE_LINK_CAPABILITY_RC_BB                                                            0x0004f0UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PCIE_LINK_CAPABILITY_RC_RC_DL_ACTIVE_CAP_BB                                         (0x1<<0) // RC only. If set, indicates dl_active capability at bit 20 of link_capability register. For EP, this field will not has any effect in link_capability register.
+  #define PCIEIP_REG_REG_PCIE_LINK_CAPABILITY_RC_RC_DL_ACTIVE_CAP_BB_SHIFT                                   0
+  #define PCIEIP_REG_REG_PCIE_LINK_CAPABILITY_RC_SLOT_CLK_CONFIG_BB                                          (0x1<<1) // If set, indicates device use the same reference clock that the platform provides on the connector.
+  #define PCIEIP_REG_REG_PCIE_LINK_CAPABILITY_RC_SLOT_CLK_CONFIG_BB_SHIFT                                    1
+#define PCIEIP_REG_REG_BAR3_CONFIG_BB                                                                        0x0004f4UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_BAR3_CONFIG_BAR3_SIZE_BB                                                            (0xf<<0) // These bits control the size of the BAR3 area advertised in the bar_5 register of the PCI configuration space. This value is sticky and only reset by HARD Reset. This register is only applicable for EP.
+  #define PCIEIP_REG_REG_BAR3_CONFIG_BAR3_SIZE_BB_SHIFT                                                      0
+  #define PCIEIP_REG_REG_BAR3_CONFIG_BAR3_64ENA_BB                                                           (0x1<<4) // This bit enables the advertisement of bar_5 as a 32-bit address. The value of this bit maps directly to bit 2 of bar_5. This value is sticky and only reset by HARD Reset. This register is only applicable for EP.
+  #define PCIEIP_REG_REG_BAR3_CONFIG_BAR3_64ENA_BB_SHIFT                                                     4
+  #define PCIEIP_REG_REG_BAR3_CONFIG_BAR3_PREFETCH_BB                                                        (0x1<<5) // This bit when set is reflected in bit 3 of bar_5 and indicates that the BAR is pre-fetchable. This register is only applicable for EP.
+  #define PCIEIP_REG_REG_BAR3_CONFIG_BAR3_PREFETCH_BB_SHIFT                                                  5
+  #define PCIEIP_REG_REG_BAR3_CONFIG_RESERVED_BB                                                             (0x3ffffff<<6) // 
+  #define PCIEIP_REG_REG_BAR3_CONFIG_RESERVED_BB_SHIFT                                                       6
+#define PCIEIP_REG_REG_ROOT_CAP_BB                                                                           0x0004f8UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_ROOT_CAP_RC_CRS_CAP_BB                                                              (0x1<<0) // This register is reserved for RC only. It is not applicable for EP.
+  #define PCIEIP_REG_REG_ROOT_CAP_RC_CRS_CAP_BB_SHIFT                                                        0
+  #define PCIEIP_REG_REG_ROOT_CAP_RC_LTR_SUPPORTED_BB                                                        (0x1<<1) // This register is reserved for RC only. It is not applicable for EP.
+  #define PCIEIP_REG_REG_ROOT_CAP_RC_LTR_SUPPORTED_BB_SHIFT                                                  1
+  #define PCIEIP_REG_REG_ROOT_CAP_RC_CLKREQ_SUPPORTED_BB                                                     (0x1<<2) // This register is reserved for RC only. It is not applicable for EP.
+  #define PCIEIP_REG_REG_ROOT_CAP_RC_CLKREQ_SUPPORTED_BB_SHIFT                                               2
+  #define PCIEIP_REG_REG_ROOT_CAP_RC_EXT2_CAP_ENA_BB                                                         (0x1f<<3) // If it is set, indicates RC supports CLKREQ Enable for the RC extended capability structures. Basic extended capability structure is defined in bits 31:30 of RC_EXT_CAP_ENA field . AER in bits 31:30 is always enabled, so that extended capability structure will follow the requirement of starting at 0x100. L1Sub capability will be present only if PMCR_RC_L1_SUBSTATES_ENA is defined in version.v Secondary PCIE extended capability will be present only if pcieGen3Rate is defined in version.v
+  #define PCIEIP_REG_REG_ROOT_CAP_RC_EXT2_CAP_ENA_BB_SHIFT                                                   3
+#define PCIEIP_REG_REG_ROOT_CONTROL_BB                                                                       0x0004fcUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_ROOT_CONTROL_RC_CLKREQ_ENABLED_BB                                                   (0x1<<0) // This register is reserved for RC only. It is not applicable for EP.
+  #define PCIEIP_REG_REG_ROOT_CONTROL_RC_CLKREQ_ENABLED_BB_SHIFT                                             0
+#define PCIEIP_REG_REG_DEV_SER_NUM_CAP_ID_BB                                                                 0x000500UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_DEV_SER_NUM_CAP_ID_DEV_SER_NUM_CAP_ID_BB                                            (0xffff<<0) // This register controls the value of CAP_ID in the DEV_SER_NUM_CAP_ID (0x13C) register in the configuration space.
+  #define PCIEIP_REG_REG_DEV_SER_NUM_CAP_ID_DEV_SER_NUM_CAP_ID_BB_SHIFT                                      0
+  #define PCIEIP_REG_REG_DEV_SER_NUM_CAP_ID_DEV_SER_NUM_CAP_VER_BB                                           (0xf<<16) // This register controls the value of CAP_VER in the DEV_SER_NUM_CAP_ID (0x13C) register in the configuration space.
+  #define PCIEIP_REG_REG_DEV_SER_NUM_CAP_ID_DEV_SER_NUM_CAP_VER_BB_SHIFT                                     16
+  #define PCIEIP_REG_REG_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_BB                                                   (0x3f<<20) // Enable for the EP extended capability structures. Default the link list is adv err, dev serial, pwr budget, virtual channel LTR capability will be present only if LTR_ENABLED is defined in version.v
+  #define PCIEIP_REG_REG_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_BB_SHIFT                                             20
+  #define PCIEIP_REG_REG_DEV_SER_NUM_CAP_ID_EXT_REG_CAP_ENA_BB                                               (0xf<<26) // Reserved Enable for the EP extended capability structures. Basic extended capability structure is defined in bits 25:20. AER in bits 25:20 should always be enabled, so that extended capability structure will follow the requirement of starting at 0x100. ARI, SRIOV capability will be present only if SRIOV is defined in version.v SRIOV capability should not be enabled without enabling ARI capability. ATS capability will be present only if ATS_ON is defined in version.v
+  #define PCIEIP_REG_REG_DEV_SER_NUM_CAP_ID_EXT_REG_CAP_ENA_BB_SHIFT                                         26
+  #define PCIEIP_REG_REG_DEV_SER_NUM_CAP_ID_RC_EXT_CAP_ENA_BB                                                (0x3<<30) // Enable for the RC extended capability structures
+  #define PCIEIP_REG_REG_DEV_SER_NUM_CAP_ID_RC_EXT_CAP_ENA_BB_SHIFT                                          30
+#define PCIEIP_REG_REG_LOWER_SER_NUM_BB                                                                      0x000504UL //Access:RW   DataWidth:0x20   // This register controls the value in the LOWER_SER_NUM (0x104) in the configuration space.
+#define PCIEIP_REG_REG_UPPER_SER_NUM_BB                                                                      0x000508UL //Access:RW   DataWidth:0x20   // This register controls the value in the UPPER_SER_NUM (0x108) in the configuration space.
+#define PCIEIP_REG_REG_ADV_ERR_CAP_BB                                                                        0x00050cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_ADV_ERR_CAP_ECRC_CHK_CAP_BB                                                         (0x1<<0) // This value controls the corresponding bit in the ADV_ERR_CAP _CONTROL (0x128)
+  #define PCIEIP_REG_REG_ADV_ERR_CAP_ECRC_CHK_CAP_BB_SHIFT                                                   0
+  #define PCIEIP_REG_REG_ADV_ERR_CAP_ECRC_GEN_CAP_BB                                                         (0x1<<1) // This value controls the corresponding bit in the ADV_ERR_CAP _CONTROL (0x128)
+  #define PCIEIP_REG_REG_ADV_ERR_CAP_ECRC_GEN_CAP_BB_SHIFT                                                   1
+#define PCIEIP_REG_REG_PWR_BDGT_DATA_0_BB                                                                    0x000510UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_0_PWR_BDGT_DATA_0_BB                                                  (0x1fffff<<0) // This is the value read from the pwr_bdgt_data register (0x158) when the pwr_bdgt_data_sel register (0x154) value is 0. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_0_PWR_BDGT_DATA_0_BB_SHIFT                                            0
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_0_RESERVED_BB                                                         (0x7ff<<21) // 
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_0_RESERVED_BB_SHIFT                                                   21
+#define PCIEIP_REG_REG_PWR_BDGT_DATA_1_BB                                                                    0x000514UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_1_PWR_BDGT_DATA_1_BB                                                  (0x1fffff<<0) // This is the value read from the pwr_bdgt_data register (0x158) when the pwr_bdgt_data_sel register (0x154) value is 1. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_1_PWR_BDGT_DATA_1_BB_SHIFT                                            0
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_1_RW_BB                                                               (0x7ff<<21) // 
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_1_RW_BB_SHIFT                                                         21
+#define PCIEIP_REG_REG_PWR_BDGT_DATA_2_BB                                                                    0x000518UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_2_PWR_BDGT_DATA_2_BB                                                  (0x1fffff<<0) // This is the value read from the pwr_bdgt_data register (0x158) when the pwr_bdgt_data_sel register (0x154) value is 2. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_2_PWR_BDGT_DATA_2_BB_SHIFT                                            0
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_2_RW_BB                                                               (0x7ff<<21) // 
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_2_RW_BB_SHIFT                                                         21
+#define PCIEIP_REG_REG_PWD_BDGT_DATA_3_BB                                                                    0x00051cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PWD_BDGT_DATA_3_PWR_BDGT_DATA_3_BB                                                  (0x1fffff<<0) // This is the value read from the pwr_bdgt_data register (0x158) when the pwr_bdgt_data_sel register (0x154) value is 3. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_REG_PWD_BDGT_DATA_3_PWR_BDGT_DATA_3_BB_SHIFT                                            0
+  #define PCIEIP_REG_REG_PWD_BDGT_DATA_3_RW_BB                                                               (0x7ff<<21) // 
+  #define PCIEIP_REG_REG_PWD_BDGT_DATA_3_RW_BB_SHIFT                                                         21
+#define PCIEIP_REG_REG_PWR_BDGT_DATA_4_BB                                                                    0x000520UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_4_PWR_BDGT_DATA_4_BB                                                  (0x1fffff<<0) // This is the value read from the pwr_bdgt_data register (0x158) when the pwr_bdgt_data_sel register (0x154) value is 4. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_4_PWR_BDGT_DATA_4_BB_SHIFT                                            0
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_4_RW_BB                                                               (0x7ff<<21) // 
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_4_RW_BB_SHIFT                                                         21
+#define PCIEIP_REG_REG_PWR_BDGT_DATA_5_BB                                                                    0x000524UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_5_PWR_BDGT_DATA_5_BB                                                  (0x1fffff<<0) // This is the value read from the pwr_bdgt_data register (0x158) when the pwr_bdgt_data_sel register (0x154) value is 5. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_5_PWR_BDGT_DATA_5_BB_SHIFT                                            0
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_5_RW_BB                                                               (0x7ff<<21) // 
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_5_RW_BB_SHIFT                                                         21
+#define PCIEIP_REG_REG_PWR_BDGT_DATA_6_BB                                                                    0x000528UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_6_PWR_BDGT_DATA_6_BB                                                  (0x1fffff<<0) // This is the value read from the pwr_bdgt_data register (0x158) when the pwr_bdgt_data_sel register (0x154) value is 6. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_6_PWR_BDGT_DATA_6_BB_SHIFT                                            0
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_6_RW_BB                                                               (0x7ff<<21) // 
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_6_RW_BB_SHIFT                                                         21
+#define PCIEIP_REG_REG_PWR_BDGT_DATA_7_BB                                                                    0x00052cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_7_PWR_BDGT_DATA_7_BB                                                  (0x1fffff<<0) // This is the value read from the pwr_bdgt_data register (0x158) when the pwr_bdgt_data_sel register (0x154) value is 7. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_7_PWR_BDGT_DATA_7_BB_SHIFT                                            0
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_7_RW_BB                                                               (0x7ff<<21) // 
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_7_RW_BB_SHIFT                                                         21
+#define PCIEIP_REG_REG_EXT2_CAP_ADDR_BB                                                                      0x000530UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_EXT2_CAP_ADDR_EXT2_CAP_ENA_BB                                                       (0xf<<0) // Enable for the EP extended capability structures. Basic extended capability structure is defined in bits 25:20 and additional extended capability is in 29:26 in dev_ser_num_cap_id register. AER in bits 25:20 should always be enabled, so that extended capability structure will follow the requirement of starting at 0x100. TPH capability will be present only if TPH_ON is defined in version.v SRIOV capability should not be enabled without enabling ARI capability. Secondary PCIE extended capability will be present only if pcieGen3Rate is defined in version.v
+  #define PCIEIP_REG_REG_EXT2_CAP_ADDR_EXT2_CAP_ENA_BB_SHIFT                                                 0
+  #define PCIEIP_REG_REG_EXT2_CAP_ADDR_EXT3_CAP_ENA_BB                                                       (0xf<<4) // Enable for the EP extended capability structures. Basic extended capability structure is defined in bits 25:20 and additional extended capability is in 29:26 in dev_ser_num_cap_id register. The next set of capabilities are defined in etx2_cap_ena in bits 3:0 of this register. This register enables the PTM capability which will be present PCIE_PTM_SUPP is defined in version.v
+  #define PCIEIP_REG_REG_EXT2_CAP_ADDR_EXT3_CAP_ENA_BB_SHIFT                                                 4
+  #define PCIEIP_REG_REG_EXT2_CAP_ADDR_RW_BB                                                                 (0xffffff<<8) // 
+  #define PCIEIP_REG_REG_EXT2_CAP_ADDR_RW_BB_SHIFT                                                           8
+#define PCIEIP_REG_REG_PWR_BDGT_DATA_8_BB                                                                    0x000534UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_8_PWR_BDGT_DATA_8_BB                                                  (0x1fffff<<0) // This is the value read from the pwr_bdgt_data register (0x158) when the pwr_bdgt_data_sel register (0x154) value is 7. This value is sticky and only reset by HARD Reset.
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_8_PWR_BDGT_DATA_8_BB_SHIFT                                            0
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_8_RESERVED_BB                                                         (0x7ff<<21) // 
+  #define PCIEIP_REG_REG_PWR_BDGT_DATA_8_RESERVED_BB_SHIFT                                                   21
+#define PCIEIP_REG_REG_L1SUB_CAP_BB                                                                          0x000540UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_L1SUB_CAP_PM_L1_2_SUPP_BB                                                           (0x1<<0) // Advertize L1_2 capability support for PM
+  #define PCIEIP_REG_REG_L1SUB_CAP_PM_L1_2_SUPP_BB_SHIFT                                                     0
+  #define PCIEIP_REG_REG_L1SUB_CAP_PM_L1_1_SUPP_BB                                                           (0x1<<1) // Advertize L1_1 capability support for PM
+  #define PCIEIP_REG_REG_L1SUB_CAP_PM_L1_1_SUPP_BB_SHIFT                                                     1
+  #define PCIEIP_REG_REG_L1SUB_CAP_ASPM_L1_2_SUPP_BB                                                         (0x1<<2) // Advertize L1_2 capability support for ASPM
+  #define PCIEIP_REG_REG_L1SUB_CAP_ASPM_L1_2_SUPP_BB_SHIFT                                                   2
+  #define PCIEIP_REG_REG_L1SUB_CAP_ASPM_L1_1_SUPP_BB                                                         (0x1<<3) // Advertize L1_1 capability support for ASPM
+  #define PCIEIP_REG_REG_L1SUB_CAP_ASPM_L1_1_SUPP_BB_SHIFT                                                   3
+  #define PCIEIP_REG_REG_L1SUB_CAP_CLKREQ_L1SUB_SUPP_BB                                                      (0x1<<4) // Clkreq based L1 substates is supported.
+  #define PCIEIP_REG_REG_L1SUB_CAP_CLKREQ_L1SUB_SUPP_BB_SHIFT                                                4
+  #define PCIEIP_REG_REG_L1SUB_CAP_RESERVED_1_BB                                                             (0x7<<5) // 
+  #define PCIEIP_REG_REG_L1SUB_CAP_RESERVED_1_BB_SHIFT                                                       5
+  #define PCIEIP_REG_REG_L1SUB_CAP_L1SUB_CMN_MODE_UP_TIME_BB                                                 (0xff<<8) // Time in us that device advertizes that it requires to re-establish common mode.
+  #define PCIEIP_REG_REG_L1SUB_CAP_L1SUB_CMN_MODE_UP_TIME_BB_SHIFT                                           8
+  #define PCIEIP_REG_REG_L1SUB_CAP_L1SUB_PWR_ON_SCALE_BB                                                     (0x3<<16) // Along with the value field, this field advertizes the tpower_on time in us, that the link partner must wait when exiting from L1_2 state due to driving CLKREQ#, before actively driving the interface.
+  #define PCIEIP_REG_REG_L1SUB_CAP_L1SUB_PWR_ON_SCALE_BB_SHIFT                                               16
+  #define PCIEIP_REG_REG_L1SUB_CAP_RESERVED_0_BB                                                             (0x1<<18) // 
+  #define PCIEIP_REG_REG_L1SUB_CAP_RESERVED_0_BB_SHIFT                                                       18
+  #define PCIEIP_REG_REG_L1SUB_CAP_L1SUB_PWR_ON_VALUE_BB                                                     (0x1f<<19) // Along with the scale field, this field advertizes the tpower_on time in us, that the link partner must wait when exiting from L1_2 state due to driving CLKREQ#, before actively driving the interface.
+  #define PCIEIP_REG_REG_L1SUB_CAP_L1SUB_PWR_ON_VALUE_BB_SHIFT                                               19
+  #define PCIEIP_REG_REG_L1SUB_CAP_RESERVED_BB                                                               (0xff<<24) // 
+  #define PCIEIP_REG_REG_L1SUB_CAP_RESERVED_BB_SHIFT                                                         24
+#define PCIEIP_REG_REG_L1SUB_EXT_CAP_BB                                                                      0x000544UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_L1SUB_EXT_CAP_L1SUB_VERSION_CAPID_BB                                                (0xfffff<<0) // This field is provided to program the cap ID and version number for L1 substates capability structure. The field was not finalized as of time of implementation and so is programmable.
+  #define PCIEIP_REG_REG_L1SUB_EXT_CAP_L1SUB_VERSION_CAPID_BB_SHIFT                                          0
+  #define PCIEIP_REG_REG_L1SUB_EXT_CAP_RESERVED_BB                                                           (0xfff<<20) // 
+  #define PCIEIP_REG_REG_L1SUB_EXT_CAP_RESERVED_BB_SHIFT                                                     20
+#define PCIEIP_REG_REG_PWR_BDGT_CAPABILITY_BB                                                                0x000550UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PWR_BDGT_CAPABILITY_PWR_SYSTEM_ALLOC_BB                                             (0x1<<0) // This bit controls the system alloc bit in the PWR_BDGT_CAP (0x15c) in the configuration space
+  #define PCIEIP_REG_REG_PWR_BDGT_CAPABILITY_PWR_SYSTEM_ALLOC_BB_SHIFT                                       0
+  #define PCIEIP_REG_REG_PWR_BDGT_CAPABILITY_RESERVED_BB                                                     (0x7fffffff<<1) // 
+  #define PCIEIP_REG_REG_PWR_BDGT_CAPABILITY_RESERVED_BB_SHIFT                                               1
+#define PCIEIP_REG_REG_VSEC_HDR_BB                                                                           0x000554UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_VSEC_HDR_VSEC_ID_BB                                                                 (0xffff<<0) // Vendor defined ID of VSEC structure. Software must qualify the Vendor ID and VSEC ID before interpreting this field.
+  #define PCIEIP_REG_REG_VSEC_HDR_VSEC_ID_BB_SHIFT                                                           0
+  #define PCIEIP_REG_REG_VSEC_HDR_VSEC_REV_BB                                                                (0xf<<16) // Vendor defined version number of VSEC structure.
+  #define PCIEIP_REG_REG_VSEC_HDR_VSEC_REV_BB_SHIFT                                                          16
+  #define PCIEIP_REG_REG_VSEC_HDR_VSEC_LENGTH_BB                                                             (0xfff<<20) // VSEC Length: Indicates the number of bytes in the entire VSEC structure, including the PCI Express Enhanced Capacbility Header, Vendor Specific Header, and the Vendor Specific Registers.
+  #define PCIEIP_REG_REG_VSEC_HDR_VSEC_LENGTH_BB_SHIFT                                                       20
+#define PCIEIP_REG_REG_RC_USER_MEM_LO1_BB                                                                    0x000558UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_RC_USER_MEM_LO1_RC_USER_SIZE1_BB                                                    (0xf<<0) // These bits control the size of the user BAR1 area. This value is sticky and only reset by HARD Reset. This register is only applicable for RC.
+  #define PCIEIP_REG_REG_RC_USER_MEM_LO1_RC_USER_SIZE1_BB_SHIFT                                              0
+  #define PCIEIP_REG_REG_RC_USER_MEM_LO1_UNUSED_2_BB                                                         (0x7<<4) // 
+  #define PCIEIP_REG_REG_RC_USER_MEM_LO1_UNUSED_2_BB_SHIFT                                                   4
+  #define PCIEIP_REG_REG_RC_USER_MEM_LO1_RC_USER_MEM_EN1_BB                                                  (0x1<<7) // Enable User Defined Mem area in RC mode. If this bit is set, then memory transactions received in Rx direction are compared against the user defined address range before it is forwarded to user. If requests do not fall in this USer BAR area, the request is target aborted.
+  #define PCIEIP_REG_REG_RC_USER_MEM_LO1_RC_USER_MEM_EN1_BB_SHIFT                                            7
+  #define PCIEIP_REG_REG_RC_USER_MEM_LO1_UNUSED_1_BB                                                         (0xff<<8) // 
+  #define PCIEIP_REG_REG_RC_USER_MEM_LO1_UNUSED_1_BB_SHIFT                                                   8
+  #define PCIEIP_REG_REG_RC_USER_MEM_LO1_RC_USER_MEM_ADDR_LO1_BB                                             (0xffff<<16) // USER_BAR_LOWER_ADDRESS: Lower 16 bits of BAR for user in RC mode. This is not the PCI standard compliant BAR, but is instead a mechanism for user to provide a mem range restriction over and above that specified by the PCI Base and Limit registers.
+  #define PCIEIP_REG_REG_RC_USER_MEM_LO1_RC_USER_MEM_ADDR_LO1_BB_SHIFT                                       16
+#define PCIEIP_REG_REG_RC_USER_MEM_HI1_BB                                                                    0x00055cUL //Access:R    DataWidth:0x20   // USER_BAR_HIGHER_ADDRESS: Higher 32 bits of BAR for user in RC mode. This is not the PCI standard compliant BAR, but is instead a mechanism for user to provide a mem range restriction over and above that specified by the PCI Base and Limit registers.
+#define PCIEIP_REG_REG_RC_USER_MEM_LO2_BB                                                                    0x000560UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_RC_USER_MEM_LO2_RC_USER_SIZE2_BB                                                    (0xf<<0) // These bits control the size of the user BAR1 area. This value is sticky and only reset by HARD Reset. This register is only applicable for RC.
+  #define PCIEIP_REG_REG_RC_USER_MEM_LO2_RC_USER_SIZE2_BB_SHIFT                                              0
+  #define PCIEIP_REG_REG_RC_USER_MEM_LO2_UNUSED_2_BB                                                         (0x7<<4) // 
+  #define PCIEIP_REG_REG_RC_USER_MEM_LO2_UNUSED_2_BB_SHIFT                                                   4
+  #define PCIEIP_REG_REG_RC_USER_MEM_LO2_RC_USER_MEM_EN2_BB                                                  (0x1<<7) // Enable User Defined Mem area in RC mode. If this bit is set, then memory transactions received in Rx direction are compared against the user defined address range before it is forwarded to user. If requests do not fall in this USer BAR area, the request is target aborted.
+  #define PCIEIP_REG_REG_RC_USER_MEM_LO2_RC_USER_MEM_EN2_BB_SHIFT                                            7
+  #define PCIEIP_REG_REG_RC_USER_MEM_LO2_UNUSED_1_BB                                                         (0xff<<8) // 
+  #define PCIEIP_REG_REG_RC_USER_MEM_LO2_UNUSED_1_BB_SHIFT                                                   8
+  #define PCIEIP_REG_REG_RC_USER_MEM_LO2_RC_USER_MEM_ADDR_LO2_BB                                             (0xffff<<16) // USER_BAR_LOWER_ADDRESS: Lower 16 bits of BAR for user in RC mode. This is not the PCI standard compliant BAR, but is instead a mechanism for user to provide a mem range restriction over and above that specified by the PCI Base and Limit registers.
+  #define PCIEIP_REG_REG_RC_USER_MEM_LO2_RC_USER_MEM_ADDR_LO2_BB_SHIFT                                       16
+#define PCIEIP_REG_REG_RC_USER_MEM_HI2_BB                                                                    0x000564UL //Access:R    DataWidth:0x20   // USER_BAR_HIGHER_ADDRESS: Higher 32 bits of BAR for user in RC mode. This is not the PCI standard compliant BAR, but is instead a mechanism for user to provide a mem range restriction over and above that specified by the PCI Base and Limit registers.
+#define PCIEIP_REG_REG_PCIER_MC_WINDOW_SIZE_REQ_BB                                                           0x0005ecUL //Access:RW   DataWidth:0x20   // This register is visible only if PCIE_EP_MC_SUPP is defined in version.v
+  #define PCIEIP_REG_REG_PCIER_MC_WINDOW_SIZE_REQ_MC_WINDOW_SIZE_REQ_BB                                      (0x3f<<0) // Default value of this field is 64KB. This field will be reflected in the MC Capability register.
+  #define PCIEIP_REG_REG_PCIER_MC_WINDOW_SIZE_REQ_MC_WINDOW_SIZE_REQ_BB_SHIFT                                0
+#define PCIEIP_REG_REG_PTM_CAP_BB                                                                            0x0005f0UL //Access:RW   DataWidth:0x20   // This register is visible only if PCIE_PTM_SUPP is defined in version.v
+  #define PCIEIP_REG_REG_PTM_CAP_PTM_REQ_CAPABLE_BB                                                          (0x1<<0) // This field will be reflected in the PTM capability register.
+  #define PCIEIP_REG_REG_PTM_CAP_PTM_REQ_CAPABLE_BB_SHIFT                                                    0
+  #define PCIEIP_REG_REG_PTM_CAP_PTM_CAP_SUPP_BB                                                             (0x1<<1) // This field will be reflected in the PTM capability register. Field indicates device is capable of generating PTM requests.
+  #define PCIEIP_REG_REG_PTM_CAP_PTM_CAP_SUPP_BB_SHIFT                                                       1
+#define PCIEIP_REG_REG_TPH_CAP_BB                                                                            0x0005f4UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_TPH_CAP_TPH_INT_VEC_MODE_SUPP_BB                                                    (0x1<<0) // when Set, it indicates function supports Interrupt vector mode of op. Value programmed here is reflected in the corresponding bits in the TPH CAP register.
+  #define PCIEIP_REG_REG_TPH_CAP_TPH_INT_VEC_MODE_SUPP_BB_SHIFT                                              0
+  #define PCIEIP_REG_REG_TPH_CAP_TPH_DEV_SPEC_MODE_BB                                                        (0x1<<1) // When Set, it indicates function suports device specific mode of operation. Value programmed here is reflected in the corresponding bits in the TPH CAP register.
+  #define PCIEIP_REG_REG_TPH_CAP_TPH_DEV_SPEC_MODE_BB_SHIFT                                                  1
+  #define PCIEIP_REG_REG_TPH_CAP_TPH_ST_TABLE_LOCATION_BB                                                    (0x3<<2) // The IP supports only a value of 0, which would indicate ST Table is not present, or a value of 2, which indicates ST table is located in MSI-X Table structure. All other values should not be programmed. The value programmed here is reflected in the corresponding field of the PCIE defined TPH Capability register.
+  #define PCIEIP_REG_REG_TPH_CAP_TPH_ST_TABLE_LOCATION_BB_SHIFT                                              2
+  #define PCIEIP_REG_REG_TPH_CAP_TPH_ST_TABLE_SIZE_BB                                                        (0x7ff<<4) // This field will be reflected in the ST Table Size field of the PCIE defined TPH capability register. The value programmed here indicates a table size of value + 1.
+  #define PCIEIP_REG_REG_TPH_CAP_TPH_ST_TABLE_SIZE_BB_SHIFT                                                  4
+#define PCIEIP_REG_REG_RESIZEBAR_CAP_BB                                                                      0x0005f8UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_CAPABILITY_BB                                                    (0xf<<0) // unused
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_CAPABILITY_BB_SHIFT                                              0
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_1M_CAPABILITY_BB                                                 (0x1<<4) // when Set, it indicates function will operate with Bar sized to 1M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_1M_CAPABILITY_BB_SHIFT                                           4
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_2M_CAPABILITY_BB                                                 (0x1<<5) // when Set, it indicates function will operate with Bar sized to 2M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_2M_CAPABILITY_BB_SHIFT                                           5
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_4M_CAPABILITY_BB                                                 (0x1<<6) // when Set, it indicates function will operate with Bar sized to 4M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_4M_CAPABILITY_BB_SHIFT                                           6
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_8M_CAPABILITY_BB                                                 (0x1<<7) // when Set, it indicates function will operate with Bar sized to 8M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_8M_CAPABILITY_BB_SHIFT                                           7
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_16M_CAPABILITY_BB                                                (0x1<<8) // when Set, it indicates function will operate with Bar sized to 16M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_16M_CAPABILITY_BB_SHIFT                                          8
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_32M_CAPABILITY_BB                                                (0x1<<9) // when Set, it indicates function will operate with Bar sized to 32M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_32M_CAPABILITY_BB_SHIFT                                          9
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_64M_CAPABILITY_BB                                                (0x1<<10) // when Set, it indicates function will operate with Bar sized to 64M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_64M_CAPABILITY_BB_SHIFT                                          10
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_128M_CAPABILITY_BB                                               (0x1<<11) // when Set, it indicates function will operate with Bar sized to 128M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_128M_CAPABILITY_BB_SHIFT                                         11
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_256M_CAPABILITY_BB                                               (0x1<<12) // when Set, it indicates function will operate with Bar sized to 256M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_256M_CAPABILITY_BB_SHIFT                                         12
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_512M_CAPABILITY_BB                                               (0x1<<13) // when Set, it indicates function will operate with Bar sized to 512M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_512M_CAPABILITY_BB_SHIFT                                         13
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_1G_CAPABILITY_BB                                                 (0x1<<14) // when Set, it indicates function will operate with Bar sized to 1G. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_1G_CAPABILITY_BB_SHIFT                                           14
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_512G_TO_2G_CAPABILITY_BB                                         (0x1ff<<15) // unsupported.
+  #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_512G_TO_2G_CAPABILITY_BB_SHIFT                                   15
+#define PCIEIP_REG_REG_ARI_CAP_BB                                                                            0x0005fcUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_ARI_CAP_NEXT_FUNCTION_NUMBER_BB                                                     (0xff<<0) // Value programmed here is reflected in the corresponding bits in the ari_control_register. This field should be programmed to indicate the next function number of the next higher numbered function in the device or 00h, if there are no higher numbered functions.
+  #define PCIEIP_REG_REG_ARI_CAP_NEXT_FUNCTION_NUMBER_BB_SHIFT                                               0
+#define PCIEIP_REG_REG_INITVF_BB                                                                             0x000600UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_INITVF_INITIALVF_BB                                                                 (0xffff<<0) // Value programmed here is reflected in the corresponding bits in the SRIOV_InitialVF register. This field indicates maximum number of VFs initially associated with the PF. This value should be the same as TotalVF field.
+  #define PCIEIP_REG_REG_INITVF_INITIALVF_BB_SHIFT                                                           0
+  #define PCIEIP_REG_REG_INITVF_TOTALVF_BB                                                                   (0xffff<<16) // Value programmed here is reflected in the corresponding bits in the SRIOV_TotalVF Cfg register. This field indicates maximum number of VFs associated with the PF.
+  #define PCIEIP_REG_REG_INITVF_TOTALVF_BB_SHIFT                                                             16
+#define PCIEIP_REG_REG_VF_OFFSET_BB                                                                          0x000604UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_VF_OFFSET_VF_OFFSET_BB                                                              (0xffff<<0) // Value programmed here is reflected in the corresponding bits in the SRIOV_VFOffset cfg register. This field defines the Routing ID of the first VF that is associated with the PF. The first VF's routing ID is calculated by adding the RID of the PF with the contents of this field. This field should be programmed based on the programming in the FIRST_VF_NUM register in the tl_reg private register space. Each PF is expected to have a multiple of 8 VFs and so this field should be programmed accordingly.
+  #define PCIEIP_REG_REG_VF_OFFSET_VF_OFFSET_BB_SHIFT                                                        0
+  #define PCIEIP_REG_REG_VF_OFFSET_DEVICEID_BB                                                               (0xffff<<16) // Value programmed here is reflected in the corresponding bits in the SRIOV_VFOffset Cfg register. This field indicates device ID for all VFs associated with this PF. Reset value is based on VFDEVICE_ID field in version.v
+  #define PCIEIP_REG_REG_VF_OFFSET_DEVICEID_BB_SHIFT                                                         16
+#define PCIEIP_REG_REG_VF_BAR_REG_BB                                                                         0x000608UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_VF_BAR_REG_BAR0_SIZE_OF_VF_BB                                                       (0xf<<0) // This field influences the size of the VFs BAR register, advertized in the VF BAR0 register in the PCIE config space. This register is only applicable for EP.
+  #define PCIEIP_REG_REG_VF_BAR_REG_BAR0_SIZE_OF_VF_BB_SHIFT                                                 0
+  #define PCIEIP_REG_REG_VF_BAR_REG_VFBAR0_64ENA_BB                                                          (0x1<<4) // This bit enables the advertisement of VF BAR0 as a 64-bit address. The value of this bit maps directly to bit 2 of VF BAR0. This value is sticky and only reset by HARD Reset. This register is only applicable for EP.
+  #define PCIEIP_REG_REG_VF_BAR_REG_VFBAR0_64ENA_BB_SHIFT                                                    4
+  #define PCIEIP_REG_REG_VF_BAR_REG_VFBAR0_PREFETCH_BB                                                       (0x1<<5) // This bit when set is reflected in bit 3 of VF BAR0 and indicates that the BAR is pre-fetchable. This register is only applicable for EP.
+  #define PCIEIP_REG_REG_VF_BAR_REG_VFBAR0_PREFETCH_BB_SHIFT                                                 5
+  #define PCIEIP_REG_REG_VF_BAR_REG_UNUSED0_BB                                                               (0x3<<6) // 
+  #define PCIEIP_REG_REG_VF_BAR_REG_UNUSED0_BB_SHIFT                                                         6
+  #define PCIEIP_REG_REG_VF_BAR_REG_BAR2_SIZE_OF_VF_BB                                                       (0xf<<8) // This field influences the size of the VFs BAR register, advertized in the VF BAR2 register in the PCIE config space. This register is only applicable for EP.
+  #define PCIEIP_REG_REG_VF_BAR_REG_BAR2_SIZE_OF_VF_BB_SHIFT                                                 8
+  #define PCIEIP_REG_REG_VF_BAR_REG_VFBAR2_64ENA_BB                                                          (0x1<<12) // This bit enables the advertisement of VF BAR2 as a 64-bit address. The value of this bit maps directly to bit 2 of VF BAR2. This value is sticky and only reset by HARD Reset. This register is only applicable for EP.
+  #define PCIEIP_REG_REG_VF_BAR_REG_VFBAR2_64ENA_BB_SHIFT                                                    12
+  #define PCIEIP_REG_REG_VF_BAR_REG_VFBAR2_PREFETCH_BB                                                       (0x1<<13) // This bit when set is reflected in bit 3 of VF BAR2 and indicates that the BAR is pre-fetchable. This register is only applicable for EP.
+  #define PCIEIP_REG_REG_VF_BAR_REG_VFBAR2_PREFETCH_BB_SHIFT                                                 13
+  #define PCIEIP_REG_REG_VF_BAR_REG_UNUSED1_BB                                                               (0x3<<14) // 
+  #define PCIEIP_REG_REG_VF_BAR_REG_UNUSED1_BB_SHIFT                                                         14
+  #define PCIEIP_REG_REG_VF_BAR_REG_SRIOV_CAP_VERSION_BB                                                     (0xf<<16) // Value programmed here is reflected in the corresponding bits in the SRIOV Capability Cfg register. This field is PCI_SIG defined version number that indicates version of capability structure present .
+  #define PCIEIP_REG_REG_VF_BAR_REG_SRIOV_CAP_VERSION_BB_SHIFT                                               16
+  #define PCIEIP_REG_REG_VF_BAR_REG_UNUSED2_BB                                                               (0xf<<20) // 
+  #define PCIEIP_REG_REG_VF_BAR_REG_UNUSED2_BB_SHIFT                                                         20
+  #define PCIEIP_REG_REG_VF_BAR_REG_FUNC_DEPENDENCY_LINK_BB                                                  (0xff<<24) // Value programmed here is reflected in the corresponding bits in the SRIOV Extended Capability Cfg register. This field is used to describe vendor specific dependencies between sets of functions.
+  #define PCIEIP_REG_REG_VF_BAR_REG_FUNC_DEPENDENCY_LINK_BB_SHIFT                                            24
+#define PCIEIP_REG_REG_VF_SUPP_PAGE_SIZE_BB                                                                  0x00060cUL //Access:RW   DataWidth:0x20   // Value programmed here is reflected in the corresponding bits in the SRIOV_SupportedPageSize Cfg register. This field indicates page sizes supported by the PF. PFs are required to support 4k, 8K, 64K, 256K, 1MB and 4MB page sizes. This PF supports a page size of 2^n+12 if bit n is set. For eg, if bit 0 is set, PF supports 4K page sizes.
+#define PCIEIP_REG_REG_VF_CAP_EN_BB                                                                          0x000610UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_VF_CAP_EN_VF_CAP_EN_BB                                                              (0x1<<0) // This value controls the read value of the next capability pointers in the VF configuration space and allows each extra capability to be independently disabled by manipulation of the next pointer values. The read values for each enable combination is shown below. PCIE capability is always enabled. Bit 0 enables the MSIX capability. This value is sticky and only reset by HARD Reset. Value affects only the VF's that belong to the PF.
+  #define PCIEIP_REG_REG_VF_CAP_EN_VF_CAP_EN_BB_SHIFT                                                        0
+  #define PCIEIP_REG_REG_VF_CAP_EN_UNUSED0_BB                                                                (0x7f<<1) // 
+  #define PCIEIP_REG_REG_VF_CAP_EN_UNUSED0_BB_SHIFT                                                          1
+  #define PCIEIP_REG_REG_VF_CAP_EN_VF_EXT_CAP_EN_BB                                                          (0x3f<<8) // Enable for the VF extended capability structures in the VF config space. Value programmed here only affects the VF cfg space belonging to the PF Default value of the link list is adv err, which has to be present always to allow extended config space to start at 0x100. Also ARI cap needs to always be present.
+  #define PCIEIP_REG_REG_VF_CAP_EN_VF_EXT_CAP_EN_BB_SHIFT                                                    8
+#define PCIEIP_REG_REG_VF_MSIX_TBL_BIR_OFF_BB                                                                0x000614UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_VF_MSIX_TBL_BIR_OFF_VF_MSIX_TBL_BIR_BB                                              (0x7<<0) // This register controls the read value of the MSIX_TBL_OFF_BIR[2:0] register in the VF Cfg space. This indicates which one of the function's Base address registers located in SRIOV capability structure of PF configuration space is used to map the function's MSI-X table into memory space. All the VFs that belong to this PF use the same BIR value.
+  #define PCIEIP_REG_REG_VF_MSIX_TBL_BIR_OFF_VF_MSIX_TBL_BIR_BB_SHIFT                                        0
+  #define PCIEIP_REG_REG_VF_MSIX_TBL_BIR_OFF_VF_MSIX_TBL_BIR_OFF_BB                                          (0x1fffffff<<3) // This register controls the read value of the MSIX_TBL_OFF_BIR[31:3] register in the VF cfg space. This is used as an offset from the address contained by one of the functions Base address registers to point to the base of the MSI-X table . All the VF's that belong to this PF use the same offset value.
+  #define PCIEIP_REG_REG_VF_MSIX_TBL_BIR_OFF_VF_MSIX_TBL_BIR_OFF_BB_SHIFT                                    3
+#define PCIEIP_REG_REG_VF_MSIX_PBA_OFF_BIT_BB                                                                0x000618UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_VF_MSIX_PBA_OFF_BIT_VF_MSIX_PBA_BIR_BB                                              (0x7<<0) // This register controls the read value of the MSIX_PBA_OFF_BIR[2:0] register in the VF Cfg space. This indicates which one of the function's Base address registers located in SRIOV capability structure in PF configuration space is used to map the VF's's MSI-X PBA into memory space. All the VF's that belong to the PF use the same BIT value. The value is controlled by IOV_MSIX_PBA_OFF define in version.v
+  #define PCIEIP_REG_REG_VF_MSIX_PBA_OFF_BIT_VF_MSIX_PBA_BIR_BB_SHIFT                                        0
+  #define PCIEIP_REG_REG_VF_MSIX_PBA_OFF_BIT_VF_MSIX_PBA_OFF_BB                                              (0x1fffffff<<3) // This register controls the read value of the MSIX_PBA_OFF_BIR[31:3] registern the VF Cfg space. This is used as an offset from the address contained by one of the functions Base address registers to point to the base of the MSI-X PBA
+  #define PCIEIP_REG_REG_VF_MSIX_PBA_OFF_BIT_VF_MSIX_PBA_OFF_BB_SHIFT                                        3
+#define PCIEIP_REG_REG_VF_MSIX_CONTROL_BB                                                                    0x00061cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_VF_MSIX_CONTROL_VF_MSIX_TBL_SIZ_BB                                                  (0x3f<<0) // This field resides in VF only and does not exist in PF. This register controls the read value of the MSIX_CONTROL[10:0] register in the VF configuration space. A value of "00000000011" indicates a table size of 4. The value is controlled by IOV_MSIX_TBL_SIZ define in version.v
+  #define PCIEIP_REG_REG_VF_MSIX_CONTROL_VF_MSIX_TBL_SIZ_BB_SHIFT                                            0
+  #define PCIEIP_REG_REG_VF_MSIX_CONTROL_RESERVEDVF_0_BB                                                     (0x3ffffff<<6) // 
+  #define PCIEIP_REG_REG_VF_MSIX_CONTROL_RESERVEDVF_0_BB_SHIFT                                               6
+#define PCIEIP_REG_REG_VF_BAR4_REG_BB                                                                        0x000620UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_VF_BAR4_REG_BAR4_SIZE_OF_VF_BB                                                      (0xf<<0) // This field influences the size of the VFs BAR register, advertized in the VF BAR4 register in the PCIE config space. This register is only applicable for EP.
+  #define PCIEIP_REG_REG_VF_BAR4_REG_BAR4_SIZE_OF_VF_BB_SHIFT                                                0
+  #define PCIEIP_REG_REG_VF_BAR4_REG_VFBAR4_64ENA_BB                                                         (0x1<<4) // This bit enables the advertisement of VF BAR4 as a 64-bit address. The value of this bit maps directly to bit 2 of VF BAR4. This value is sticky and only reset by HARD Reset. This register is only applicable for EP.
+  #define PCIEIP_REG_REG_VF_BAR4_REG_VFBAR4_64ENA_BB_SHIFT                                                   4
+  #define PCIEIP_REG_REG_VF_BAR4_REG_VFBAR4_PREFETCH_BB                                                      (0x1<<5) // This bit when set is reflected in bit 3 of VF BAR4 and indicates that the BAR is pre-fetchable. This register is only applicable for EP.
+  #define PCIEIP_REG_REG_VF_BAR4_REG_VFBAR4_PREFETCH_BB_SHIFT                                                5
+#define PCIEIP_REG_REG_PF_INITVF_BB                                                                          0x000624UL //Access:RW   DataWidth:0x20   // Register programs the first VF allocation for a PF. All the VFs within IP are assumed to reside in a contiguous space starting at VFNUM =0. This register identifies the first VFNUM location for a PF. This register exists only in a PF
+  #define PCIEIP_REG_REG_PF_INITVF_PF_FIRST_VF_NUM_BB                                                        (0x1f<<0) // First VF_NUM for PF is encoded in this register. The number of VFs assigned to a PF is assumed to be a multiple of 8. Software should program these bits based on Total Number of VFs programmed for each PF.
+  #define PCIEIP_REG_REG_PF_INITVF_PF_FIRST_VF_NUM_BB_SHIFT                                                  0
+#define PCIEIP_REG_REG_VF_NSP_BB                                                                             0x000628UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_VF_NSP_PF_VFBAR0_NSP_BB                                                             (0xf<<0) // This field describes the number of System pages needed by VF BAR0 belonging to PF. User Page Size(UPS) is determined by UABS &gt;&gt; NSP, where UABS is the User Advertized Bar Size and NSP is this field. BAR Size advertized is changed if SPS &gt; UPS, where SPS is System Page Size. Programming should ensure that resulting BAR size will not be bigger than 2G, so value of this field should be kept small if SPS is large.
+  #define PCIEIP_REG_REG_VF_NSP_PF_VFBAR0_NSP_BB_SHIFT                                                       0
+  #define PCIEIP_REG_REG_VF_NSP_PF_VFBAR2_NSP_BB                                                             (0xf<<4) // This field describes the number of System pages needed by VF BAR2 belonging to PF. User Page Size(UPS) is determined by UABS &gt;&gt; NSP, where UABS is the User Advertized Bar Size and NSP is this field. BAR Size advertized is changed if SPS &gt; UPS, where SPS is System Page Size. Programming should ensure that resulting BAR size will not be bigger than 2G, so value of this field should be kept small if SPS is large.
+  #define PCIEIP_REG_REG_VF_NSP_PF_VFBAR2_NSP_BB_SHIFT                                                       4
+  #define PCIEIP_REG_REG_VF_NSP_PF_VFBAR4_NSP_BB                                                             (0xf<<8) // This field describes the number of System pages needed by VF BAR4 belonging to PF. User Page Size(UPS) is determined by UABS &gt;&gt; NSP, where UABS is the User Advertized Bar Size and NSP is this field. BAR Size advertized is changed if SPS &gt; UPS, where SPS is System Page Size. Programming should ensure that resulting BAR size will not be bigger than 2G, so value of this field should be kept small if SPS is large.
+  #define PCIEIP_REG_REG_VF_NSP_PF_VFBAR4_NSP_BB_SHIFT                                                       8
+#define PCIEIP_REG_REG_ATS_INLD_QUEUE_DEPTH_BB                                                               0x000630UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_ATS_INLD_QUEUE_DEPTH_ATS_INVLD_QDEPTH_BB                                            (0x1f<<0) // This register controls the corresponding value in the ATS capability register. This field advertizes the number of Invalidate requests the Function can accept before putting backpressure on the upstream connection.
+  #define PCIEIP_REG_REG_ATS_INLD_QUEUE_DEPTH_ATS_INVLD_QDEPTH_BB_SHIFT                                      0
+  #define PCIEIP_REG_REG_ATS_INLD_QUEUE_DEPTH_ATS_PAGE_ALIGNED_REQ_BB                                        (0x1<<5) // This register controls the corresponding value in the ATS capability register. This field qhen Set, indicates the Untranslated Address always aligns to a 4K byte boundary. Setting this bit is recommended.
+  #define PCIEIP_REG_REG_ATS_INLD_QUEUE_DEPTH_ATS_PAGE_ALIGNED_REQ_BB_SHIFT                                  5
+  #define PCIEIP_REG_REG_ATS_INLD_QUEUE_DEPTH_RESERVEDVF_0_BB                                                (0x3ffffff<<6) // 
+  #define PCIEIP_REG_REG_ATS_INLD_QUEUE_DEPTH_RESERVEDVF_0_BB_SHIFT                                          6
+#define PCIEIP_REG_REG_VFTPH_CAP_BB                                                                          0x000634UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_VFTPH_CAP_VFTPH_INT_VEC_MODE_SUPP_BB                                                (0x1<<0) // when Set, it indicates function supports Interrupt vector mode of op. Value programmed here is reflected in the corresponding bits in the TPH CAP register.
+  #define PCIEIP_REG_REG_VFTPH_CAP_VFTPH_INT_VEC_MODE_SUPP_BB_SHIFT                                          0
+  #define PCIEIP_REG_REG_VFTPH_CAP_VFTPH_DEV_SPEC_MODE_BB                                                    (0x1<<1) // When Set, it indicates function suports device specific mode of operation. Value programmed here is reflected in the corresponding bits in the TPH CAP register.
+  #define PCIEIP_REG_REG_VFTPH_CAP_VFTPH_DEV_SPEC_MODE_BB_SHIFT                                              1
+  #define PCIEIP_REG_REG_VFTPH_CAP_VFTPH_ST_TABLE_LOCATION_BB                                                (0x3<<2) // The IP supports only a value of 0, which would indicate ST Table is not present, or a value of 2, which indicates ST table is located in MSI-X Table structure. All other values should not be programmed. The value programmed here is reflected in the corresponding field of the PCIE defined TPH Capability register in VF.
+  #define PCIEIP_REG_REG_VFTPH_CAP_VFTPH_ST_TABLE_LOCATION_BB_SHIFT                                          2
+  #define PCIEIP_REG_REG_VFTPH_CAP_VFTPH_ST_TABLE_SIZE_BB                                                    (0x7ff<<4) // This field will be reflected in the ST Table Size field of the PCIE defined TPH capability register in the VF. The value programmed here indicates a table size of value + 1.
+  #define PCIEIP_REG_REG_VFTPH_CAP_VFTPH_ST_TABLE_SIZE_BB_SHIFT                                              4
+  #define PCIEIP_REG_REG_VFTPH_CAP_UNUSED0_BB                                                                (0xffff<<15) // 
+  #define PCIEIP_REG_REG_VFTPH_CAP_UNUSED0_BB_SHIFT                                                          15
+  #define PCIEIP_REG_REG_VFTPH_CAP_TPH_SUPP_INVF_BB                                                          (0x1<<31) // This field when set enables TPH capability in all the VF's.
+  #define PCIEIP_REG_REG_VFTPH_CAP_TPH_SUPP_INVF_BB_SHIFT                                                    31
+#define PCIEIP_REG_ACK_LATENCY_TIMER_OFF_K2_E5                                                               0x000700UL //Access:RW   DataWidth:0x20   // Ack Latency Timer and Replay Timer Register.
+  #define PCIEIP_REG_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_K2_E5                               (0xffff<<0) // Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details, see "Ack Scheduling". You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register. After reset, the core updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed. The value is determined from Tables 3-7, 3-8, and 3-9 of the PCIe 3.0 specification. The limit must reflect the round trip latency from requester to completer. If there is a change in the payload size or link width, the core will override any value that you have written to this register field, and reset the field back to the specification-defined value. It will not change the value in the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.
+  #define PCIEIP_REG_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_K2_E5_SHIFT                         0
+  #define PCIEIP_REG_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_K2_E5                                           (0xffff<<16) // Replay Timer Limit. The replay timer expires when it reaches this limit. The core initiates a replay upon reception of a NAK or when the replay timer expires. For more details, see "Transmit Replay". You can modify the effective timer limit with the TIMER_MOD_REPLAY_TIMER field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register. After reset, the core updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed. The value is determined from Tables 3-4, 3-5, and 3-6 of the PCIe 3.0 specification. If there is a change in the payload size or link speed, the core will override any value that you have written to this register field, and reset the field back to the specification-defined value. It will not change the value in the TIMER_MOD_REPLAY_TIMER field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.
+  #define PCIEIP_REG_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_K2_E5_SHIFT                                     16
+#define PCIEIP_REG_VENDOR_SPEC_DLLP_OFF_K2_E5                                                                0x000704UL //Access:RW   DataWidth:0x20   // Vendor Specific DLLP Register.
+#define PCIEIP_REG_PORT_FORCE_OFF_K2_E5                                                                      0x000708UL //Access:RW   DataWidth:0x20   // Port Force Link Register.
+  #define PCIEIP_REG_PORT_FORCE_OFF_LINK_NUM_K2_E5                                                           (0xff<<0) // Link Number. Not used for endpoint. Not used for M-PCIe.  Note: This register field is sticky.
+  #define PCIEIP_REG_PORT_FORCE_OFF_LINK_NUM_K2_E5_SHIFT                                                     0
+  #define PCIEIP_REG_PORT_FORCE_OFF_FORCED_LTSSM_K2_E5                                                       (0xf<<8) // Forced Link Command. The link command that the core is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v.  Note: This register field is sticky.
+  #define PCIEIP_REG_PORT_FORCE_OFF_FORCED_LTSSM_K2_E5_SHIFT                                                 8
+  #define PCIEIP_REG_PORT_FORCE_OFF_FORCE_EN_K2_E5                                                           (0x1<<15) // Force Link. The core supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state, and to force the core to transmit a specific Link Command. Asserting this bit triggers the following actions:  - Forces the LTSSM to the state specified by the Forced LTSSM State field.  - Forces the core to transmit the command specified by the Forced Link Command field. This is a self-clearing register field. Reading from this register field always returns a "0".
+  #define PCIEIP_REG_PORT_FORCE_OFF_FORCE_EN_K2_E5_SHIFT                                                     15
+  #define PCIEIP_REG_PORT_FORCE_OFF_LINK_STATE_K2_E5                                                         (0x3f<<16) // Forced LTSSM State. The LTSSM state that the core is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v.  Note: This register field is sticky.
+  #define PCIEIP_REG_PORT_FORCE_OFF_LINK_STATE_K2_E5_SHIFT                                                   16
+  #define PCIEIP_REG_PORT_FORCE_OFF_CPL_SENT_COUNT_K2_E5                                                     (0xff<<24) // Low Power Entrance Count. The Power Management state waits for this many clock cycles for the associated completion of a CfgWr to D-state register to go low-power. This register is intended for applications that do not let the core handle a completion for configuration request to the PMCSCR register. Not used in downstream ports.  Note: This register field is sticky.
+  #define PCIEIP_REG_PORT_FORCE_OFF_CPL_SENT_COUNT_K2_E5_SHIFT                                               24
+#define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_K2_E5                                                                 0x00070cUL //Access:RW   DataWidth:0x20   // Ack Frequency and L0-L1 ASPM Control Register.
+  #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_K2_E5                                                      (0xff<<0) // Ack Frequency. The core accumulates the number of pending ACKs specified here (up to 255) before sending an ACK DLLP.  - 0: Indicates that this Ack frequency control feature is turned off. The core schedules a low-priority ACK DLLP for every TLP that it receives.  - 1-255: Indicates that the core will schedule a high-priority ACK after receiving this number of TLPs. It might schedule the ACK before receiving this number of TLPs, but never later. For a typical system, you do not have to modify the default setting. For more details, see "ACK/NAK Scheduling".  Note: This register field is sticky.
+  #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_K2_E5_SHIFT                                                0
+  #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_K2_E5                                                     (0xff<<8) // N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The core does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s. This field is reserved (fixed to '0') for M-PCIe.  Note: This register field is sticky.
+  #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_K2_E5_SHIFT                                               8
+  #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_K2_E5                                              (0xff<<16) // Common Clock N_FTS. This is the N_FTS when common clock is used. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. This field is only writable (sticky) when all of the following configuration parameter equations are true:  - CX_NFTS !=CX_COMM_NFTS  - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY  - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY The core does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s. This field is reserved (fixed to '0') for M-PCIe.  Note: The access attributes of this field are as follows:  - Dbi: R
+  #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_K2_E5_SHIFT                                        16
+  #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_K2_E5                                          (0x7<<24) // L0s Entrance Latency. Values correspond to:  - 000: 1 us  - 001: 2 us  - 010: 3 us  - 011: 4 us  - 100: 5 us  - 101: 6 us  - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe.  Note: This register field is sticky.
+  #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_K2_E5_SHIFT                                    24
+  #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_K2_E5                                           (0x7<<27) // L1 Entrance Latency. Value range is:  - 000: 1 us  - 001: 2 us  - 010: 4 us  - 011: 8 us  - 100: 16 us  - 101: 32 us  - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used, or all of the credits are infinite.  Note: This register field is sticky.
+  #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_K2_E5_SHIFT                                     27
+  #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_K2_E5                                                    (0x1<<30) // ASPM L1 Entry Control.  - 1: Core enters ASPM L1 after a period in which it has been idle.  - 0: Core enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky.
+  #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_K2_E5_SHIFT                                              30
+#define PCIEIP_REG_PORT_LINK_CTRL_OFF_K2_E5                                                                  0x000710UL //Access:RW   DataWidth:0x20   // Port Link Control Register.
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_K2_E5                                       (0x1<<0) // Vendor Specific DLLP Request. When software writes a '1' to this bit, the core transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF.  Reading from this self-clearing register field always returns a '0'.
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_K2_E5_SHIFT                                 0
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_K2_E5                                               (0x1<<1) // Scramble Disable. Turns off data scrambling.  Note: This register field is sticky.
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_K2_E5_SHIFT                                         1
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_K2_E5                                                (0x1<<2) // Loopback Enable. Turns on loopback. For more details, see "Loopback". For M-PCIe, to force the master to enter Digital Loopback mode, you must set this field to "1" during Configuration.start state(initial discovery/configuration). M-PCIe doesn't support loopback mode from L0 state - only from Configuration.start.  Note: This register field is sticky.
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_K2_E5_SHIFT                                          2
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_RESET_ASSERT_K2_E5                                                   (0x1<<3) // Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only).  Note: This register field is sticky.
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_RESET_ASSERT_K2_E5_SHIFT                                             3
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_DLL_LINK_EN_K2_E5                                                    (0x1<<5) // DLL Link Enable. Enables link initialization. When DLL Link Enable =0, the core does not transmit InitFC DLLPs and does not establish a link.  Note: This register field is sticky.
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_DLL_LINK_EN_K2_E5_SHIFT                                              5
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_DISABLE_K2_E5                                                   (0x1<<6) // LINK_DISABLE is an internally reserved field. Do not use.  Note: This register field is sticky.
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_DISABLE_K2_E5_SHIFT                                             6
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_K2_E5                                                 (0x1<<7) // Fast Link Mode. Sets all internal timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The scaling factor is selected in FAST_LINK_SCALING_FACTOR(default : 1024) for all internal timers. Fast Link Mode can also be activated by setting the diag_ctrl_bus[2] pin to "1". For more details, see "SII Signals: Diagnostic Control". For M-PCIe, this field also affects Remain Hibern8 Time, Minimum Activate Time, and RRAP timeout. If this bit is set to '1', tRRAPInitiatorResponse is set to 1.88 ms(60 ms/32).  Note: This register field is sticky.
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_K2_E5_SHIFT                                           7
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_RATE_K2_E5                                                      (0xf<<8) // LINK_RATE is an internally reserved field. Do not use.  Note: This register field is sticky.
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_RATE_K2_E5_SHIFT                                                8
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_CAPABLE_K2_E5                                                   (0x3f<<16) // Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes. You must also change the value in the "Predetermined Number of Lanes" field of the "Link Width and Speed Change Control Register". For more information, see "How to Tie Off Unused Lanes". For information on upsizing and downsizing the link width, see "Link Establishment".  - 000001: x1  - 000011: x2  - 000111: x4  - 001111: x8  - 011111: x16  - 111111: x32 (not supported) This field is reserved (fixed to '0') for M-PCIe.  Note: This register field is sticky.
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_CAPABLE_K2_E5_SHIFT                                             16
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_BEACON_ENABLE_K2_E5                                                  (0x1<<24) // BEACON_ENABLE is an internally reserved field. Do not use.  Note: This register field is sticky.
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_BEACON_ENABLE_K2_E5_SHIFT                                            24
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_K2_E5                                            (0x1<<25) // CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use.  Note: This register field is sticky.
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_K2_E5_SHIFT                                      25
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_K2_E5                                                 (0x1<<26) // EXTENDED_SYNCH is an internally reserved field. Do not use.  Note: This register field is sticky.
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_K2_E5_SHIFT                                           26
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_K2_E5                                 (0x1<<27) // TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use.  Note: This register field is sticky.
+  #define PCIEIP_REG_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_K2_E5_SHIFT                           27
+#define PCIEIP_REG_LANE_SKEW_OFF_K2_E5                                                                       0x000714UL //Access:RW   DataWidth:0x20   // Lane Skew Register.
+  #define PCIEIP_REG_LANE_SKEW_OFF_INSERT_LANE_SKEW_K2_E5                                                    (0xffffff<<0) // Insert Lane Skew for Transmit (not supported for x16). Optional feature that causes the core to insert skew between Lanes for test purposes. There are three bits per Lane. The value is in units of one symbol time. For example, the value 010b for a Lane forces a skew of two symbol times for that Lane. The maximum skew value for any Lane is 5 symbol times.  Note: This register field is sticky.
+  #define PCIEIP_REG_LANE_SKEW_OFF_INSERT_LANE_SKEW_K2_E5_SHIFT                                              0
+  #define PCIEIP_REG_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_K2_E5                                                   (0x1<<24) // Flow Control Disable. Prevents the core from sending FC DLLPs.  Note: This register field is sticky.
+  #define PCIEIP_REG_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_K2_E5_SHIFT                                             24
+  #define PCIEIP_REG_LANE_SKEW_OFF_ACK_NAK_DISABLE_K2_E5                                                     (0x1<<25) // Ack/Nak Disable. Prevents the core from sending ACK and NAK DLLPs.  Note: This register field is sticky.
+  #define PCIEIP_REG_LANE_SKEW_OFF_ACK_NAK_DISABLE_K2_E5_SHIFT                                               25
+  #define PCIEIP_REG_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_K2_E5                                         (0x1<<31) // Disable Lane-to-Lane Deskew. Causes the core to disable the internal Lane-to-Lane deskew logic.  Note: This register field is sticky.
+  #define PCIEIP_REG_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_K2_E5_SHIFT                                   31
+#define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_K2_E5                                                         0x000718UL //Access:RW   DataWidth:0x20   // Timer Control and Max Function Number Register.
+  #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_K2_E5                                          (0xff<<0) // Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request).  Note: This register field is sticky.
+  #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_K2_E5_SHIFT                                    0
+  #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_K2_E5                                (0x1f<<14) // Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed, and in increments of 256 clock cycles at Gen3 speed. A value of "0" represents no modification to the timer limit. For more details, see the REPLAY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register. At Gen3 speed, the core automatically changes the value of this field to DEFAULT_GEN3_REPLAY_ADJ. For M-PCIe, this field increases the time-out value for the replay timer in increments of 64 clock cycles at HS-Gear1, HS-Gear2, or HS-Gear3 speed.  Note: This register field is sticky.
+  #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_K2_E5_SHIFT                          14
+  #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_K2_E5                                     (0x1f<<19) // Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of "0" represents no modification to the timer value. For more details, see the ROUND_TRIP_LATENCY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register.  Note: This register field is sticky.
+  #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_K2_E5_SHIFT                               19
+  #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_K2_E5                                     (0x1f<<24) // UPDATE_FREQ_TIMER is an internally reserved field. Do not use.  Note: This register field is sticky.
+  #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_K2_E5_SHIFT                               24
+  #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_K2_E5                              (0x3<<29) // Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE is set to 1b.  - 0: Scaling Factor is 1024 (1ms is 1us)  - 1: Scaling Factor is 256 (1ms is 4us)  - 2: Scaling Factor is 64 (1ms is 16us)  - 3: Scaling Factor is 16 (1ms is 64us) Not used for M-PCIe.  Note: This register field is sticky.
+  #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_K2_E5_SHIFT                        29
+#define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_K2_E5                                                           0x00071cUL //Access:RW   DataWidth:0x20   // Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.
+  #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_K2_E5                                             (0x7ff<<0) // SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the core actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application must program this register accordingly. For example, if 1536 were programmed into this register (in a 250 MHz core), then the core actually transmits SKP ordered sets once every 1537 symbol times. The value programmed to this register is actually clock ticks and not symbol times. In a 125 MHz core, programming the value programmed to this register should be scaled down by a factor of 2 (because one clock tick = two symbol times in this case).  Note: This value is not used at Gen3 speed; the skip interval is hardcoded to 370 blocks.  Note: This register field is sticky.
+  #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_K2_E5_SHIFT                                       0
+  #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_K2_E5                                             (0xf<<11) // EIDLE_TIMER is an internally reserved field. Do not use.  Note: This register field is sticky.
+  #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_K2_E5_SHIFT                                       11
+  #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_K2_E5                                     (0x1<<15) // Disable FC Watchdog Timer.  Note: This register field is sticky.
+  #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_K2_E5_SHIFT                               15
+  #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_K2_E5                                             (0xffff<<16) // Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.  [31]: CX_FLT_MASK_RC_CFG_DISCARD  - 0: For RADM RC filter to not allow CFG transaction being received  - 1: For RADM RC filter to allow CFG transaction being received [30]: CX_FLT_MASK_RC_IO_DISCARD  - 0: For RADM RC filter to not allow IO transaction being received  - 1: For RADM RC filter to allow IO transaction being received [29]: CX_FLT_MASK_MSG_DROP  - 0: Drop MSG TLP (except for Vendor MSG). Send decoded message on the SII.  - 1: Do not Drop MSG (except for Vendor MSG). Send message TLPs to your application on TRGT1 and send decoded message on the SII.  - The default for this bit is the inverse of FLT_DROP_MSG. That is, if FLT_DROP_MSG =1, then the default of this bit is "0" (drop message TLPs). This bit only controls message TLPs other than Vendor MSGs. Vendor MSGs are controlled by Filter Mask Register 2, bits [1:0].  The core never passes ATS Invalidate messages to the SII interface regardless of this filter rule setting. The core passes all ATS Invalidate messages to TRGT1 (or AXI bridge master), as they are too big for the SII. [28]: CX_FLT_MASK_CPL_ECRC_DISCARD  - Only used when completion queue is advertised with infinite credits and is in store-and-forward mode.  - 0: Discard completions with ECRC errors  - 1: Allow completions with ECRC errors to be passed up  - Reserved field for SW. [27]: CX_FLT_MASK_ECRC_DISCARD  - 0: Discard TLPs with ECRC errors  - 1: Allow TLPs with ECRC errors to be passed up [26]: CX_FLT_MASK_CPL_LEN_MATCH  - 0: Enforce length match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err  - 1: MASK length match for completions [25]: CX_FLT_MASK_CPL_ATTR_MATCH  - 0: Enforce attribute match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca  - 1: Mask attribute match for completions [24]: CX_FLT_MASK_CPL_TC_MATCH  - 0: Enforce Traffic Class match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca  - 1: Mask Traffic Class match for completions [23]: CX_FLT_MASK_CPL_FUNC_MATCH  - 0: Enforce function match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca  - 1: Mask function match for completions [22]: CX_FLT_MASK_CPL_REQID_MATCH  - 0: Enforce Req. Id match for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca  - 1: Mask Req. Id match for completions [21]: CX_FLT_MASK_CPL_TAGERR_MATCH  - 0: Enforce Tag Error Rules for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca  - 1: Mask Tag Error Rules for completions [20]: CX_FLT_MASK_LOCKED_RD_AS_UR  - 0: Treat locked Read TLPs as UR for EP; Supported for RC  - 1: Treat locked Read TLPs as Supported for EP; UR for RC [19]: CX_FLT_MASK_CFG_TYPE1_RE_AS_UR  - 0: Treat CFG type1 TLPs as UR for EP; Supported for RC  - 1: Treat CFG type1 TLPs as Supported for EP; UR for RC  - When CX_SRIOV_ENABLE is set then this bit is set to allow the filter to process Type 1 Config requests if the EP consumes more than one bus number. [18]: CX_FLT_MASK_UR_OUTSIDE_BAR  - 0: Treat out-of-bar TLPs as UR  - 1: Do not treat out-of-bar TLPs as UR [17]: CX_FLT_MASK_UR_POIS  - 0: Treat poisoned request TLPs as UR  - 1: Do not treat poisoned request TLPs as UR  - The native core always passes poisoned completions to your application except when you are using the DMA read channel. [16]: CX_FLT_MASK_UR_FUNC_MISMATCH  - 0: Treat Function MisMatched TLPs as UR  - 1: Do not treat Function MisMatched TLPs as UR Note: This register field is sticky.
+  #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_K2_E5_SHIFT                                       16
+#define PCIEIP_REG_FILTER_MASK_2_OFF_K2_E5                                                                   0x000720UL //Access:RW   DataWidth:0x20   // Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.
+#define PCIEIP_REG_PL_DEBUG0_OFF_K2_E5                                                                       0x000728UL //Access:R    DataWidth:0x20   // Debug Register 0
+#define PCIEIP_REG_PL_DEBUG1_OFF_K2_E5                                                                       0x00072cUL //Access:R    DataWidth:0x20   // Debug Register 1
+#define PCIEIP_REG_TX_P_FC_CREDIT_STATUS_OFF_K2_E5                                                           0x000730UL //Access:R    DataWidth:0x20   // Transmit Posted FC Credit Status
+  #define PCIEIP_REG_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_K2_E5                                     (0xfff<<0) // Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
+  #define PCIEIP_REG_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_K2_E5_SHIFT                               0
+  #define PCIEIP_REG_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_K2_E5                                   (0xff<<12) // Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
+  #define PCIEIP_REG_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_K2_E5_SHIFT                             12
+#define PCIEIP_REG_TX_NP_FC_CREDIT_STATUS_OFF_K2_E5                                                          0x000734UL //Access:R    DataWidth:0x20   // Transmit Non-Posted FC Credit Status
+  #define PCIEIP_REG_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_K2_E5                                   (0xfff<<0) // Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
+  #define PCIEIP_REG_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_K2_E5_SHIFT                             0
+  #define PCIEIP_REG_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_K2_E5                                 (0xff<<12) // Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
+  #define PCIEIP_REG_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_K2_E5_SHIFT                           12
+#define PCIEIP_REG_TX_CPL_FC_CREDIT_STATUS_OFF_K2_E5                                                         0x000738UL //Access:R    DataWidth:0x20   // Transmit Completion FC Credit Status
+  #define PCIEIP_REG_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_K2_E5                                 (0xfff<<0) // Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
+  #define PCIEIP_REG_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_K2_E5_SHIFT                           0
+  #define PCIEIP_REG_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_K2_E5                               (0xff<<12) // Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
+  #define PCIEIP_REG_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_K2_E5_SHIFT                         12
+#define PCIEIP_REG_QUEUE_STATUS_OFF_K2_E5                                                                    0x00073cUL //Access:RW   DataWidth:0x20   // Queue Status
+  #define PCIEIP_REG_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_K2_E5                                      (0x1<<0) // Received TLP FC Credits Not Returned. Indicates that the core has sent a TLP but has not yet received an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the link.
+  #define PCIEIP_REG_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_K2_E5_SHIFT                                0
+  #define PCIEIP_REG_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_K2_E5                                               (0x1<<1) // Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer.
+  #define PCIEIP_REG_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_K2_E5_SHIFT                                         1
+  #define PCIEIP_REG_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_K2_E5                                               (0x1<<2) // Received Queue Not Empty. Indicates there is data in one or more of the receive buffers.
+  #define PCIEIP_REG_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_K2_E5_SHIFT                                         2
+  #define PCIEIP_REG_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_K2_E5                                           (0x1fff<<16) // FC Latency Timer Override Value. When you set the "FC Latency Timer Override Enable" in this register, the value in this field will override the FC latency timer value that the core calculates according to the PCIe specification. For more details, see "Flow Control".  Note: This register field is sticky.
+  #define PCIEIP_REG_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_K2_E5_SHIFT                                     16
+  #define PCIEIP_REG_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_K2_E5                                        (0x1<<31) // FC Latency Timer Override Enable. When this bit is set, the value from the "FC Latency Timer Override Value" field in this register will override the FC latency timer value that the core calculates according to the PCIe specification.  Note: This register field is sticky.
+  #define PCIEIP_REG_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_K2_E5_SHIFT                                  31
+#define PCIEIP_REG_VC_TX_ARBI_1_OFF_K2_E5                                                                    0x000740UL //Access:R    DataWidth:0x20   // VC Transmit Arbitration Register 1
+  #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_K2_E5                                                  (0xff<<0) // WRR Weight for VC0.  Note: The access attributes of this field are as follows:  - Dbi: R
+  #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_K2_E5_SHIFT                                            0
+  #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_K2_E5                                                  (0xff<<8) // WRR Weight for VC1.  Note: The access attributes of this field are as follows:  - Dbi: R
+  #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_K2_E5_SHIFT                                            8
+  #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_K2_E5                                                  (0xff<<16) // WRR Weight for VC2.  Note: The access attributes of this field are as follows:  - Dbi: R
+  #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_K2_E5_SHIFT                                            16
+  #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_K2_E5                                                  (0xff<<24) // WRR Weight for VC3.  Note: The access attributes of this field are as follows:  - Dbi: R
+  #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_K2_E5_SHIFT                                            24
+#define PCIEIP_REG_VC_TX_ARBI_2_OFF_K2_E5                                                                    0x000744UL //Access:R    DataWidth:0x20   // VC Transmit Arbitration Register 2
+  #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_K2_E5                                                  (0xff<<0) // WRR Weight for VC4.  Note: The access attributes of this field are as follows:  - Dbi: R
+  #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_K2_E5_SHIFT                                            0
+  #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_K2_E5                                                  (0xff<<8) // WRR Weight for VC5.  Note: The access attributes of this field are as follows:  - Dbi: R
+  #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_K2_E5_SHIFT                                            8
+  #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_K2_E5                                                  (0xff<<16) // WRR Weight for VC6.  Note: The access attributes of this field are as follows:  - Dbi: R
+  #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_K2_E5_SHIFT                                            16
+  #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_K2_E5                                                  (0xff<<24) // WRR Weight for VC7.  Note: The access attributes of this field are as follows:  - Dbi: R
+  #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_K2_E5_SHIFT                                            24
+#define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_K2_E5                                                                 0x000748UL //Access:RW   DataWidth:0x20   // Segmented-Buffer VC0 Posted Receive Queue Control.
+  #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_K2_E5                                             (0xfff<<0) // VC0 Posted Data Credits. The number of initial posted data credits for VC0, used only in the segmented-buffer configuration.  Note: The access attributes of this field are as follows:  - Dbi: R (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_K2_E5_SHIFT                                       0
+  #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_K2_E5                                           (0xff<<12) // VC0 Posted Header Credits. The number of initial posted header credits for VC0, used only in the segmented-buffer configuration.  Note: The access attributes of this field are as follows:  - Dbi: R (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_K2_E5_SHIFT                                     12
+  #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_RESERVED4_K2_E5                                                     (0x1<<20) // Reserved.  Note: This register field is sticky.
+  #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_RESERVED4_K2_E5_SHIFT                                               20
+  #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_K2_E5                                              (0x7<<21) // Reserved.  Note: This register field is sticky.
+  #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_K2_E5_SHIFT                                        21
+  #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_RESERVED5_K2_E5                                                     (0x3f<<24) // Reserved.  Note: This register field is sticky.
+  #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_RESERVED5_K2_E5_SHIFT                                               24
+  #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_K2_E5                                         (0x1<<30) // TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues, used only in the segmented-buffer configuration:  - 1: PCIe ordering rules (recommended)  - 0: Strict ordering: posted, completion, then non-posted Note: This register field is sticky.
+  #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_K2_E5_SHIFT                                   30
+  #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_K2_E5                                              (0x1<<31) // VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues, used only in the segmented-buffer configuration:  - 1: Strict ordering, higher numbered VCs have higher priority  - 0: Round robin Note: This register field is sticky.
+  #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_K2_E5_SHIFT                                        31
+#define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_K2_E5                                                                0x00074cUL //Access:RW   DataWidth:0x20   // Segmented-Buffer VC0 Non-Posted Receive Queue Control.
+  #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_K2_E5                                           (0xfff<<0) // VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0, used only in the segmented-buffer configuration.  Note: The access attributes of this field are as follows:  - Dbi: R (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_K2_E5_SHIFT                                     0
+  #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_K2_E5                                         (0xff<<12) // VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0, used only in the segmented-buffer configuration.  Note: The access attributes of this field are as follows:  - Dbi: R (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_K2_E5_SHIFT                                   12
+  #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_K2_E5                                                    (0x1<<20) // Reserved.  Note: This register field is sticky.
+  #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_K2_E5_SHIFT                                              20
+  #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_K2_E5                                            (0x7<<21) // Reserved.  Note: This register field is sticky.
+  #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_K2_E5_SHIFT                                      21
+  #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_K2_E5                                                    (0xff<<24) // Reserved.  Note: This register field is sticky.
+  #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_K2_E5_SHIFT                                              24
+#define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_K2_E5                                                               0x000750UL //Access:RW   DataWidth:0x20   // Segmented-Buffer VC0 Completion Receive Queue Control.
+  #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_K2_E5                                         (0xfff<<0) // VC0 Completion Data Credits. The number of initial Completion data credits for VC0, used only in the segmented-buffer configuration.  Note: The access attributes of this field are as follows:  - Dbi: R (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_K2_E5_SHIFT                                   0
+  #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_K2_E5                                       (0xff<<12) // VC0 Completion Header Credits. The number of initial Completion header credits for VC0, used only in the segmented-buffer configuration.  Note: The access attributes of this field are as follows:  - Dbi: R (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_K2_E5_SHIFT                                 12
+  #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_K2_E5                                                   (0x1<<20) // Reserved.  Note: This register field is sticky.
+  #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_K2_E5_SHIFT                                             20
+  #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_K2_E5                                          (0x7<<21) // Reserved.  Note: This register field is sticky.
+  #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_K2_E5_SHIFT                                    21
+  #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_K2_E5                                                   (0xff<<24) // Reserved.  Note: This register field is sticky.
+  #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_K2_E5_SHIFT                                             24
+#define PCIEIP_REG_TL_CONTROL_0_BB                                                                           0x000800UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_TL_CONTROL_0_PM_TL_IGNORE_REQS_BB                                                       (0x1<<0) // When set the TL TX does not send out pending requests if PM requests to block TLPS. By default TL will send all pending dma requests and completions when PM requests it to prepare for leaving L0 before asserting tlp blocked. When this bit is set , if min credits are available, TL indicates to PM that TLP is blocked and does not send out any pending dma requests or completions.
+  #define PCIEIP_REG_TL_CONTROL_0_PM_TL_IGNORE_REQS_BB_SHIFT                                                 0
+  #define PCIEIP_REG_TL_CONTROL_0_MEMRD_1DW_CHK_BB                                                           (0x1<<1) // Target mem Rd should not be greater than 1 DW if set.
+  #define PCIEIP_REG_TL_CONTROL_0_MEMRD_1DW_CHK_BB_SHIFT                                                     1
+  #define PCIEIP_REG_TL_CONTROL_0_MEMRD_3DW_CHK_BB                                                           (0x1<<2) // Target mem Rd should not be greater than 3 DW if set.
+  #define PCIEIP_REG_TL_CONTROL_0_MEMRD_3DW_CHK_BB_SHIFT                                                     2
+  #define PCIEIP_REG_TL_CONTROL_0_MEMWR_1DW_CHK_BB                                                           (0x1<<3) // Target mem Wr should not be greater than 1 DW if set.
+  #define PCIEIP_REG_TL_CONTROL_0_MEMWR_1DW_CHK_BB_SHIFT                                                     3
+  #define PCIEIP_REG_TL_CONTROL_0_EXPROM_3DW_CHK_BB                                                          (0x1<<4) // Target Expansion ROM should not be greater than 3 DW if set.
+  #define PCIEIP_REG_TL_CONTROL_0_EXPROM_3DW_CHK_BB_SHIFT                                                    4
+  #define PCIEIP_REG_TL_CONTROL_0_MEMRD_16DW_CHK_BB                                                          (0x1<<5) // Target mem Rd should not be greater than 16 DW if set .
+  #define PCIEIP_REG_TL_CONTROL_0_MEMRD_16DW_CHK_BB_SHIFT                                                    5
+  #define PCIEIP_REG_TL_CONTROL_0_MEMRD_4DW_CHK_BB                                                           (0x1<<6) // Target mem Rd should not be greater than 4 DW if set .
+  #define PCIEIP_REG_TL_CONTROL_0_MEMRD_4DW_CHK_BB_SHIFT                                                     6
+  #define PCIEIP_REG_TL_CONTROL_0_MEMWR_4DW_CHK_BB                                                           (0x1<<7) // Target mem Wr should not be greater than 4 DW if set .
+  #define PCIEIP_REG_TL_CONTROL_0_MEMWR_4DW_CHK_BB_SHIFT                                                     7
+  #define PCIEIP_REG_TL_CONTROL_0_MEMWR_32DW_CHK_BB                                                          (0x1<<8) // Target mem Wr should not be greater than 32 DW if set .
+  #define PCIEIP_REG_TL_CONTROL_0_MEMWR_32DW_CHK_BB_SHIFT                                                    8
+  #define PCIEIP_REG_TL_CONTROL_0_MEMRD_32DW_CHK_BB                                                          (0x1<<9) // Target mem Rd should not be greater than 32 DW if set .
+  #define PCIEIP_REG_TL_CONTROL_0_MEMRD_32DW_CHK_BB_SHIFT                                                    9
+  #define PCIEIP_REG_TL_CONTROL_0_UNUSED_3_BB                                                                (0x3<<10) // 
+  #define PCIEIP_REG_TL_CONTROL_0_UNUSED_3_BB_SHIFT                                                          10
+  #define PCIEIP_REG_TL_CONTROL_0_RETAIN_RID_BB                                                              (0x1<<12) // This bit if set will force DUT to not reset its RID after an FLR.
+  #define PCIEIP_REG_TL_CONTROL_0_RETAIN_RID_BB_SHIFT                                                        12
+  #define PCIEIP_REG_TL_CONTROL_0_AUTO_CLR_FLR_AFTER_55MS_BB                                                 (0x1<<13) // If set, DUT will automatically exit FLR state after a 55ms timer expires.
+  #define PCIEIP_REG_TL_CONTROL_0_AUTO_CLR_FLR_AFTER_55MS_BB_SHIFT                                           13
+  #define PCIEIP_REG_TL_CONTROL_0_AUTO_CLR_CRS_POST_FLR_BB                                                   (0x1<<14) // If set, DUT will automatically return Successful completion when it has completed FLR.
+  #define PCIEIP_REG_TL_CONTROL_0_AUTO_CLR_CRS_POST_FLR_BB_SHIFT                                             14
+  #define PCIEIP_REG_TL_CONTROL_0_NO_CMPL_IN_FLR_BB                                                          (0x1<<15) // If set, completions received for a function which is in FLR will not be directed to user.
+  #define PCIEIP_REG_TL_CONTROL_0_NO_CMPL_IN_FLR_BB_SHIFT                                                    15
+  #define PCIEIP_REG_TL_CONTROL_0_CFG_FUNC_EN0_BB                                                            (0x1<<16) // If set, this causes func0 to be hidden
+  #define PCIEIP_REG_TL_CONTROL_0_CFG_FUNC_EN0_BB_SHIFT                                                      16
+  #define PCIEIP_REG_TL_CONTROL_0_UNUSED_2_BB                                                                (0x1<<17) // 
+  #define PCIEIP_REG_TL_CONTROL_0_UNUSED_2_BB_SHIFT                                                          17
+  #define PCIEIP_REG_TL_CONTROL_0_CFG_MSI_LOW_MODE_BB                                                        (0x1<<18) // when set, forces MSI_En to low.
+  #define PCIEIP_REG_TL_CONTROL_0_CFG_MSI_LOW_MODE_BB_SHIFT                                                  18
+  #define PCIEIP_REG_TL_CONTROL_0_BEACON_MULTI_EN_BB                                                         (0x1<<19) // When set Beacon is enabled for all lanes
+  #define PCIEIP_REG_TL_CONTROL_0_BEACON_MULTI_EN_BB_SHIFT                                                   19
+  #define PCIEIP_REG_TL_CONTROL_0_BEACON_DIS_BB                                                              (0x1<<20) // When set, Beacon generation is disabled
+  #define PCIEIP_REG_TL_CONTROL_0_BEACON_DIS_BB_SHIFT                                                        20
+  #define PCIEIP_REG_TL_CONTROL_0_WAKE_L0_L1_EN_BB                                                           (0x1<<21) // When set, it enables WAKE generation in any L-state, when PME_EN bit is set and corresponding status is enabled
+  #define PCIEIP_REG_TL_CONTROL_0_WAKE_L0_L1_EN_BB_SHIFT                                                     21
+  #define PCIEIP_REG_TL_CONTROL_0_UNUSED_4_BB                                                                (0x1<<22) // 
+  #define PCIEIP_REG_TL_CONTROL_0_UNUSED_4_BB_SHIFT                                                          22
+  #define PCIEIP_REG_TL_CONTROL_0_RST_IGNORE_DLPDOWN_BB                                                      (0x1<<23) // When set, TL does not get reset on DLPDOWN and Pcie_rst_b does not get asserted on DLPDOWN
+  #define PCIEIP_REG_TL_CONTROL_0_RST_IGNORE_DLPDOWN_BB_SHIFT                                                23
+  #define PCIEIP_REG_TL_CONTROL_0_PM_DIS_L1_REENTRY_BB                                                       (0x1<<24) // When set, it prevents PM from re-entering L1 when programmed to non-D0 power state
+  #define PCIEIP_REG_TL_CONTROL_0_PM_DIS_L1_REENTRY_BB_SHIFT                                                 24
+  #define PCIEIP_REG_TL_CONTROL_0_PCIE_PHY_TX_SWING_BB                                                       (0x1<<25) // This bit is used by PCIE SERDES to determine source of tx margin signals
+  #define PCIEIP_REG_TL_CONTROL_0_PCIE_PHY_TX_SWING_BB_SHIFT                                                 25
+  #define PCIEIP_REG_TL_CONTROL_0_PERST_B_80USSEL_BB                                                         (0x1<<26) // Select the 150us delayed perst_b instead of the raw perst_b
+  #define PCIEIP_REG_TL_CONTROL_0_PERST_B_80USSEL_BB_SHIFT                                                   26
+  #define PCIEIP_REG_TL_CONTROL_0_REG_PERST_B_10MSSEL_BB                                                     (0x1<<27) // Select the 10ms delayed perst_b instead of the raw perst_b
+  #define PCIEIP_REG_TL_CONTROL_0_REG_PERST_B_10MSSEL_BB_SHIFT                                               27
+  #define PCIEIP_REG_TL_CONTROL_0_REG_SCND_RST_ON_HOT_BB                                                     (0x1<<28) // In RC mode, when set, it enables pcie_scnd_rst_b to be asserted when Secondary reset bit in BridgeControl register is set.
+  #define PCIEIP_REG_TL_CONTROL_0_REG_SCND_RST_ON_HOT_BB_SHIFT                                               28
+  #define PCIEIP_REG_TL_CONTROL_0_REG_FORCE_SCND_RST_BB                                                      (0x1<<29) // In RC mode, when set, it forces pcie_scnd_rst_b to be asserted
+  #define PCIEIP_REG_TL_CONTROL_0_REG_FORCE_SCND_RST_BB_SHIFT                                                29
+  #define PCIEIP_REG_TL_CONTROL_0_UNUSED_1_BB                                                                (0x3<<30) // 
+  #define PCIEIP_REG_TL_CONTROL_0_UNUSED_1_BB_SHIFT                                                          30
+#define PCIEIP_REG_TL_CONTROL_1_BB                                                                           0x000804UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_TL_CONTROL_1_EN_4G_CHK_BB                                                               (0x1<<0) // Enable check to determine if mem requests do not have upper 32 bits of address to be all 0
+  #define PCIEIP_REG_TL_CONTROL_1_EN_4G_CHK_BB_SHIFT                                                         0
+  #define PCIEIP_REG_TL_CONTROL_1_EN_4K_CHK_BB                                                               (0x1<<1) // Enable checks to determine TLP doesn not cross 4k boundary
+  #define PCIEIP_REG_TL_CONTROL_1_EN_4K_CHK_BB_SHIFT                                                         1
+  #define PCIEIP_REG_TL_CONTROL_1_EN_BC_CHK_BB                                                               (0x1<<2) // Enable check to determine if the length field and bytecount field are in sync
+  #define PCIEIP_REG_TL_CONTROL_1_EN_BC_CHK_BB_SHIFT                                                         2
+  #define PCIEIP_REG_TL_CONTROL_1_EN_BE_CHK_BB                                                               (0x1<<3) // Enable check to determine if received TLP follows all the Byte enable rules
+  #define PCIEIP_REG_TL_CONTROL_1_EN_BE_CHK_BB_SHIFT                                                         3
+  #define PCIEIP_REG_TL_CONTROL_1_EN_EP_CHK_BB                                                               (0x1<<4) // Enable check for Poisoned TLP
+  #define PCIEIP_REG_TL_CONTROL_1_EN_EP_CHK_BB_SHIFT                                                         4
+  #define PCIEIP_REG_TL_CONTROL_1_EN_MPS_CHECK_BB                                                            (0x1<<5) // Enable Check for max payload size Violation
+  #define PCIEIP_REG_TL_CONTROL_1_EN_MPS_CHECK_BB_SHIFT                                                      5
+  #define PCIEIP_REG_TL_CONTROL_1_EN_RCB_CHK_BB                                                              (0x1<<6) // Enable checks to determine completion TLPs do not violate RCB
+  #define PCIEIP_REG_TL_CONTROL_1_EN_RCB_CHK_BB_SHIFT                                                        6
+  #define PCIEIP_REG_TL_CONTROL_1_EN_RTE_CHK_BB                                                              (0x1<<7) // Enable Check to determine if the routing type is correct when receiving message TLP
+  #define PCIEIP_REG_TL_CONTROL_1_EN_RTE_CHK_BB_SHIFT                                                        7
+  #define PCIEIP_REG_TL_CONTROL_1_EN_TAC_CHK_BB                                                              (0x1<<8) // Enable Configuration attribute and class check
+  #define PCIEIP_REG_TL_CONTROL_1_EN_TAC_CHK_BB_SHIFT                                                        8
+  #define PCIEIP_REG_TL_CONTROL_1_EN_FC_CHK_BB                                                               (0x1<<9) // Enable Flow Control Check
+  #define PCIEIP_REG_TL_CONTROL_1_EN_FC_CHK_BB_SHIFT                                                         9
+  #define PCIEIP_REG_TL_CONTROL_1_EN_TO_CHK_BB                                                               (0x1<<10) // Enable Completion Timeout Check( This bit is no longer used, instead bit defined by ECN 1.1 is used)
+  #define PCIEIP_REG_TL_CONTROL_1_EN_TO_CHK_BB_SHIFT                                                         10
+  #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_1_BB                                                             (0x1<<11) // This bit is used to disable function 1. Bit 17 of 800 can also be used. That bit is retained for software compatibility purpose.
+  #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_1_BB_SHIFT                                                       11
+  #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_2_BB                                                             (0x1<<12) // This bit is used to disable function 2.
+  #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_2_BB_SHIFT                                                       12
+  #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_3_BB                                                             (0x1<<13) // This bit is used to disable function 3.
+  #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_3_BB_SHIFT                                                       13
+  #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_4_BB                                                             (0x1<<14) // This bit is used to disable function 4.
+  #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_4_BB_SHIFT                                                       14
+  #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_5_BB                                                             (0x1<<15) // This bit is used to disable function 5.
+  #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_5_BB_SHIFT                                                       15
+  #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_6_BB                                                             (0x1<<16) // This bit is used to disable function 6.
+  #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_6_BB_SHIFT                                                       16
+  #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_7_BB                                                             (0x1<<17) // This bit is used to disable function 7.
+  #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_7_BB_SHIFT                                                       17
+  #define PCIEIP_REG_TL_CONTROL_1_RESERVED_BB                                                                (0x1<<18) // 
+  #define PCIEIP_REG_TL_CONTROL_1_RESERVED_BB_SHIFT                                                          18
+  #define PCIEIP_REG_TL_CONTROL_1_REG_IGNORE_LTRWT_REQMT_BB                                                  (0x1<<19) // When set, hardware will return completions and not wait for LTR message to be sent first even though device state may have changed to non-D0.
+  #define PCIEIP_REG_TL_CONTROL_1_REG_IGNORE_LTRWT_REQMT_BB_SHIFT                                            19
+  #define PCIEIP_REG_TL_CONTROL_1_REG_REL_NPHCRDT_ECRCERR_BB                                                 (0x1<<20) // Release NPH credit even if ECRC error is detected on NPH TLP.
+  #define PCIEIP_REG_TL_CONTROL_1_REG_REL_NPHCRDT_ECRCERR_BB_SHIFT                                           20
+  #define PCIEIP_REG_TL_CONTROL_1_REG_UCOR_INT_ERR_EN_BB                                                     (0x1<<21) // Enables uncorrectable Internal Error Reporting if feature is implemented in h/w
+  #define PCIEIP_REG_TL_CONTROL_1_REG_UCOR_INT_ERR_EN_BB_SHIFT                                               21
+  #define PCIEIP_REG_TL_CONTROL_1_REG_EN_BYTCNT_CHK_BB                                                       (0x1<<22) // When enabled, hardware checks the bytecount field in completion headers.
+  #define PCIEIP_REG_TL_CONTROL_1_REG_EN_BYTCNT_CHK_BB_SHIFT                                                 22
+  #define PCIEIP_REG_TL_CONTROL_1_REG_EN_LTR1_BB                                                             (0x1<<23) // This bit instructs h/w to send an LTR message with LTR values programmed in 'h848 whenever the h/w asserts the user_send_ltr1 port. This bit is used only if LTR_ENABLED is defined in version.v and if h/w supports 3 LTR states.
+  #define PCIEIP_REG_TL_CONTROL_1_REG_EN_LTR1_BB_SHIFT                                                       23
+  #define PCIEIP_REG_TL_CONTROL_1_EN_AUTOCRSCLR_BB                                                           (0x1<<24) // This bit enables CRS status to be automatically cleared when internal timer is equal to either 1 second or a programmable value(which ever is smaller). This bit is used only if AutoCRSClrOn is defined in version.v
+  #define PCIEIP_REG_TL_CONTROL_1_EN_AUTOCRSCLR_BB_SHIFT                                                     24
+  #define PCIEIP_REG_TL_CONTROL_1_EN_LTR2_BB                                                                 (0x1<<25) // This bit instructs h/w to send an LTR message with LTR values programmed in 'h84c whenever the h/w asserts the user_send_ltr2 port. This bit is used only if LTR_ENABLED is defined in version.v
+  #define PCIEIP_REG_TL_CONTROL_1_EN_LTR2_BB_SHIFT                                                           25
+  #define PCIEIP_REG_TL_CONTROL_1_WT_LTR_ASPM_VAL_BB                                                         (0xf<<26) // This programs a timer which indicates the amount of time DUT will wait before requesting entry to ASPM L1 when ASPM LTR is enabled. The unit of this timer is us. This time is in addition to the time that DL waits for bus to be idle. This timer is required to allow DUT to send ASPM LTR message and wait for FC to be returned before entering L1. This bit is used only if LTR_ENABLED is defined in version.v
+  #define PCIEIP_REG_TL_CONTROL_1_WT_LTR_ASPM_VAL_BB_SHIFT                                                   26
+  #define PCIEIP_REG_TL_CONTROL_1_EN_ASPM_LTR_BB                                                             (0x1<<30) // This bit instructs h/w to send an LTR message with LTR values programmed in 'h844 and 'h848 whenever the DUT enters or leaves ASPM L1. This bit is used only if LTR_ENABLED is defined in version.v
+  #define PCIEIP_REG_TL_CONTROL_1_EN_ASPM_LTR_BB_SHIFT                                                       30
+  #define PCIEIP_REG_TL_CONTROL_1_SEND_IMMED_LTR_BB                                                          (0x1<<31) // This bit instructs h/w to immediately send an LTR message with LTR values programmed in 'h840. This state has highest priority and when this bit is set, no other LTR message (other than those required by PCIE spec) will be sent. This bit is used only if LTR_ENABLED is defined in version.v
+  #define PCIEIP_REG_TL_CONTROL_1_SEND_IMMED_LTR_BB_SHIFT                                                    31
+#define PCIEIP_REG_TL_CONTROL_2_BB                                                                           0x000808UL //Access:RW   DataWidth:0x20   // This register masks the generation of pcie_err_attn signal when errors are detected by hardware.
+  #define PCIEIP_REG_TL_CONTROL_2_PES0_MASK_BB                                                               (0x1<<0) // Poisoned Error Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_CONTROL_2_PES0_MASK_BB_SHIFT                                                         0
+  #define PCIEIP_REG_TL_CONTROL_2_FCPES0_MASK_BB                                                             (0x1<<1) // Flow Control Protocol Error Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_CONTROL_2_FCPES0_MASK_BB_SHIFT                                                       1
+  #define PCIEIP_REG_TL_CONTROL_2_CTS0_MASK_BB                                                               (0x1<<2) // Completer Timeout Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_CONTROL_2_CTS0_MASK_BB_SHIFT                                                         2
+  #define PCIEIP_REG_TL_CONTROL_2_RX_UR0_MASK_BB                                                             (0x1<<3) // Received UR Status, Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_CONTROL_2_RX_UR0_MASK_BB_SHIFT                                                       3
+  #define PCIEIP_REG_TL_CONTROL_2_UCS0_MASK_BB                                                               (0x1<<4) // Unexpected Completion Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_CONTROL_2_UCS0_MASK_BB_SHIFT                                                         4
+  #define PCIEIP_REG_TL_CONTROL_2_ROS0_MASK_BB                                                               (0x1<<5) // Receiver Overflow Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_CONTROL_2_ROS0_MASK_BB_SHIFT                                                         5
+  #define PCIEIP_REG_TL_CONTROL_2_MTLPS0_MASK_BB                                                             (0x1<<6) // Malformed TLP Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_CONTROL_2_MTLPS0_MASK_BB_SHIFT                                                       6
+  #define PCIEIP_REG_TL_CONTROL_2_ECRCS0_MASK_BB                                                             (0x1<<7) // ECRC Error TLP Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_CONTROL_2_ECRCS0_MASK_BB_SHIFT                                                       7
+  #define PCIEIP_REG_TL_CONTROL_2_URES0_MASK_BB                                                              (0x1<<8) // Unsupported Request Error Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_CONTROL_2_URES0_MASK_BB_SHIFT                                                        8
+  #define PCIEIP_REG_TL_CONTROL_2_RXTABRT0_MASK_BB                                                           (0x1<<9) // Received target Abort Error Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_CONTROL_2_RXTABRT0_MASK_BB_SHIFT                                                     9
+  #define PCIEIP_REG_TL_CONTROL_2_PES1_MASK_BB                                                               (0x1<<10) // Poisoned Error Status Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_CONTROL_2_PES1_MASK_BB_SHIFT                                                         10
+  #define PCIEIP_REG_TL_CONTROL_2_FCPES1_MASK_BB                                                             (0x1<<11) // Flow Control Protocol Error Status Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_CONTROL_2_FCPES1_MASK_BB_SHIFT                                                       11
+  #define PCIEIP_REG_TL_CONTROL_2_CTS1_MASK_BB                                                               (0x1<<12) // Completer Timeout Status Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_CONTROL_2_CTS1_MASK_BB_SHIFT                                                         12
+  #define PCIEIP_REG_TL_CONTROL_2_RX_UR1_MASK_BB                                                             (0x1<<13) // Received UR Status, Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_CONTROL_2_RX_UR1_MASK_BB_SHIFT                                                       13
+  #define PCIEIP_REG_TL_CONTROL_2_UCS1_MASK_BB                                                               (0x1<<14) // Unexpected Completion Status Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_CONTROL_2_UCS1_MASK_BB_SHIFT                                                         14
+  #define PCIEIP_REG_TL_CONTROL_2_ROS1_MASK_BB                                                               (0x1<<15) // Receiver Overflow Status Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_CONTROL_2_ROS1_MASK_BB_SHIFT                                                         15
+  #define PCIEIP_REG_TL_CONTROL_2_MTLPS1_MASK_BB                                                             (0x1<<16) // Malformed TLP Status Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_CONTROL_2_MTLPS1_MASK_BB_SHIFT                                                       16
+  #define PCIEIP_REG_TL_CONTROL_2_ECRCS1_MASK_BB                                                             (0x1<<17) // ECRC Error TLP Status Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_CONTROL_2_ECRCS1_MASK_BB_SHIFT                                                       17
+  #define PCIEIP_REG_TL_CONTROL_2_URES1_MASK_BB                                                              (0x1<<18) // Unsupported Request Error Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_CONTROL_2_URES1_MASK_BB_SHIFT                                                        18
+  #define PCIEIP_REG_TL_CONTROL_2_RXTABRT1_MASK_BB                                                           (0x1<<19) // Received target Abort Error Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_CONTROL_2_RXTABRT1_MASK_BB_SHIFT                                                     19
+  #define PCIEIP_REG_TL_CONTROL_2_RTAG_VAL_UNEXP_ATTN_MASK_BB                                                (0x1<<20) // rtag_val_unexp_attn Mask. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_CONTROL_2_RTAG_VAL_UNEXP_ATTN_MASK_BB_SHIFT                                          20
+  #define PCIEIP_REG_TL_CONTROL_2_TX_TAG_IN_USE_ATTN_MASK_BB                                                 (0x1<<21) // tx_tag_in_use_attn Mask. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_CONTROL_2_TX_TAG_IN_USE_ATTN_MASK_BB_SHIFT                                           21
+  #define PCIEIP_REG_TL_CONTROL_2_DL_ERR_ATTN_MASK_BB                                                        (0x1<<22) // DL Error Status Mask. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_CONTROL_2_DL_ERR_ATTN_MASK_BB_SHIFT                                                  22
+  #define PCIEIP_REG_TL_CONTROL_2_PHY_ERR_ATTN_MASK_BB                                                       (0x1<<23) // PHY Error Status Mask. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_CONTROL_2_PHY_ERR_ATTN_MASK_BB_SHIFT                                                 23
+  #define PCIEIP_REG_TL_CONTROL_2_TXINTF_OVERFLOW_ATTN_MASK_BB                                               (0x1<<24) // 
+  #define PCIEIP_REG_TL_CONTROL_2_TXINTF_OVERFLOW_ATTN_MASK_BB_SHIFT                                         24
+  #define PCIEIP_REG_TL_CONTROL_2_BRIDGE_FORWARD_ERR_ATTN_MASK_BB                                            (0x1<<25) // If set, TX reports user interface violation
+  #define PCIEIP_REG_TL_CONTROL_2_BRIDGE_FORWARD_ERR_ATTN_MASK_BB_SHIFT                                      25
+  #define PCIEIP_REG_TL_CONTROL_2_TTX_MPS_ERR_MASK_BB                                                        (0x1<<26) // 
+  #define PCIEIP_REG_TL_CONTROL_2_TTX_MPS_ERR_MASK_BB_SHIFT                                                  26
+  #define PCIEIP_REG_TL_CONTROL_2_TTX_MRRS_ERR_MASK_BB                                                       (0x1<<27) // 
+  #define PCIEIP_REG_TL_CONTROL_2_TTX_MRRS_ERR_MASK_BB_SHIFT                                                 27
+  #define PCIEIP_REG_TL_CONTROL_2_TTX_4KBOUND_ERR_MASK_BB                                                    (0x1<<28) // 
+  #define PCIEIP_REG_TL_CONTROL_2_TTX_4KBOUND_ERR_MASK_BB_SHIFT                                              28
+  #define PCIEIP_REG_TL_CONTROL_2_TTX_UNKNOWNTYPE_ERR_MASK_BB                                                (0x1<<29) // 
+  #define PCIEIP_REG_TL_CONTROL_2_TTX_UNKNOWNTYPE_ERR_MASK_BB_SHIFT                                          29
+  #define PCIEIP_REG_TL_CONTROL_2_UNUSED_1_BB                                                                (0x3<<30) // 
+  #define PCIEIP_REG_TL_CONTROL_2_UNUSED_1_BB_SHIFT                                                          30
+#define PCIEIP_REG_GEN2_CTRL_OFF_K2_E5                                                                       0x00080cUL //Access:RW   DataWidth:0x20   // Link Width and Speed Change Control Register.
+  #define PCIEIP_REG_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_K2_E5                                                   (0xff<<0) // Sets the Number of Fast Training Sequences (N_FTS) that the core advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a low power state. The number should be provided by the PHY vendor. Do not set N_FTS to zero; doing so can cause the LTSSM to go into the recovery state when exiting from L0s. This field is reserved (fixed to '0') for M-PCIe.  Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_K2_E5_SHIFT                                             0
+  #define PCIEIP_REG_GEN2_CTRL_OFF_NUM_OF_LANES_K2_E5                                                        (0x1f<<8) // Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken" or "unused" lanes that detect a receiver. Indicates the number of lanes to check for exit from Electrical Idle in Polling.Active and L2.Idle. It is possible that the LTSSM might detect a receiver on a bad or broken lane during the Detect Substate. However, it is also possible that such a lane might also fail to exit Electrical Idle and therefore prevent a valid link from being configured. This value is referred to as the "Predetermined Number of Lanes" in section 4.2.6.2.1 of the PCI Express Base 3.0 Specification, revision 1.0. Encoding is as follows:  - 0x01: 1 lane  - 0x02: 2 lanes  - 0x03: 3 lanes  - .. When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes. You must also change the value in the "Link Mode Enable" field of PORT_LINK_CTRL_OFF. The value in this register is normally the same as the encoded value in PORT_LINK_CTRL_OFF. If you find that one of your used lanes is bad then you must reduce the value in this register. For more information, see "How to Tie Off Unused Lanes." For information on upsizing and downsizing the link width, see "Link Establishment." This field is reserved (fixed to '0') for M-PCIe.  Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN2_CTRL_OFF_NUM_OF_LANES_K2_E5_SHIFT                                                  8
+  #define PCIEIP_REG_GEN2_CTRL_OFF_PRE_DET_LANE_K2_E5                                                        (0x7<<13) // Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect. Allowed values are:  - 3'b000: Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/2-1 or CX_NL/4-1 or CX_NL/8-1, depending on which lane is detected  - 3'b001: Connect logical Lane0 to physical lane 1  - 3'b010: Connect logical Lane0 to physical lane 3  - 3'b011: Connect logical Lane0 to physical lane 7  - 3'b100: Connect logical Lane0 to physical lane 15 This field is used to restrict the receiver detect procedure to a particular lane when the default detect and polling procedure performed on all lanes cannot be successful. A notable example of when it is useful to program this field to a value different from the default, is when a lane is asymmetrically broken, that is, it is detected in Detect LTSSM state but it cannot exit Electrical Idle in Polling LTSSM state.  Note: This field is reserved (fixed to '0') for M-PCIe.  Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN2_CTRL_OFF_PRE_DET_LANE_K2_E5_SHIFT                                                  13
+  #define PCIEIP_REG_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_K2_E5                                              (0x1<<16) // Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the core. For more details, see the 'Lane Reversal' appendix in the Databook. This field is reserved (fixed to '0') for M-PCIe.  Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_K2_E5_SHIFT                                        16
+  #define PCIEIP_REG_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_K2_E5                                                 (0x1<<17) // Directed Speed Change. Writing "1" to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs, the core will clear the contents of this field; and a read to this field by your software will return a "0". To manually initiate the speed change:  - Write to LINK_CONTROL2_LINK_STATUS2_REG . PCIE_CAP_TARGET_LINK_SPEED in the local device  - Deassert this field  - Assert this field If you set the default of this field using the DEFAULT_GEN2_SPEED_CHANGE configuration parameter to "1", then the speed change is initiated automatically after link up, and the core clears the contents of this field. If you want to prevent this automatic speed change, then write a lower speed value to the Target Link Speed field of the Link Control 2 register (LINK_CONTROL2_LINK_STATUS2_OFF . PCIE_CAP_TARGET_LINK_SPEED) through the DBI before link up. This field is reserved (fixed to '0') for M-PCIe.  Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_K2_E5_SHIFT                                           17
+  #define PCIEIP_REG_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_K2_E5                                                (0x1<<18) // Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The core drives the mac_phy_txswing output from this register bit field.  - 0: Full Swing  - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe.  Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_K2_E5_SHIFT                                          18
+  #define PCIEIP_REG_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_K2_E5                                                   (0x1<<19) // Config Tx Compliance Receive Bit. When set to 1, signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to "1"). This field is reserved (fixed to '0') for M-PCIe.  Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_K2_E5_SHIFT                                             19
+  #define PCIEIP_REG_GEN2_CTRL_OFF_SEL_DEEMPHASIS_K2_E5                                                      (0x1<<20) // Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at.  - 0: -6 dB  - 1: -3.5 dB This field is reserved (fixed to '0') for M-PCIe.  Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN2_CTRL_OFF_SEL_DEEMPHASIS_K2_E5_SHIFT                                                20
+  #define PCIEIP_REG_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_K2_E5                                                   (0x1<<21) // Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a "1" value on RxElecIdle instead of looking for a "0" on RxValid. If the PHY fails to deassert the RxValid signal in Recovery.Speed or Loopback.Active (because of corrupted EIOS for example), then EI cannot be inferred successfully in the core by just detecting the condition RxValid=0.  - 0: Use RxElecIdle signal to infer Electrical Idle  - 1: Use RxValid signal to infer Electrical Idle Note: This register field is sticky.
+  #define PCIEIP_REG_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_K2_E5_SHIFT                                             21
+#define PCIEIP_REG_TL_CONTROL_3_BB                                                                           0x00080cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_TL_CONTROL_3_EN_CMPL_RETRY_BB                                                           (0x1<<0) // Enable Completion retry upon completion timeout. (feature is not supported, but bit is defined for posterity.)
+  #define PCIEIP_REG_TL_CONTROL_3_EN_CMPL_RETRY_BB_SHIFT                                                     0
+  #define PCIEIP_REG_TL_CONTROL_3_EN_PSND_RETRY_BB                                                           (0x1<<1) // Enable Poisoned completions retry. (feature is not supported but bit is defined for posterity.)
+  #define PCIEIP_REG_TL_CONTROL_3_EN_PSND_RETRY_BB_SHIFT                                                     1
+  #define PCIEIP_REG_TL_CONTROL_3_EN_HOLD_PHCRDT_BB                                                          (0x1<<2) // Hold releasing of Posted header credit. When this bit is set, PH credits are not released by IP if FIFO at the DL-TL boundary reaches a critical threshold. This feature allows the FIFO to unload without overflowing
+  #define PCIEIP_REG_TL_CONTROL_3_EN_HOLD_PHCRDT_BB_SHIFT                                                    2
+  #define PCIEIP_REG_TL_CONTROL_3_EN_HOLD_DMACRDT_BB                                                         (0x1<<3) // Indicates no non-posted credit is available to user when bit is set. The credits to user are artificially reduced to 0, when FIFO at DL_TL boundary has reached a critical threshold and is in danger of overflowing. This feature allows the FIFO to unload without overflowing
+  #define PCIEIP_REG_TL_CONTROL_3_EN_HOLD_DMACRDT_BB_SHIFT                                                   3
+  #define PCIEIP_REG_TL_CONTROL_3_REG_EN_ADVERR_RX_ERR_BB                                                    (0x1<<4) // Enable the reporting of receiver errors in the advanced error reporting structure.
+  #define PCIEIP_REG_TL_CONTROL_3_REG_EN_ADVERR_RX_ERR_BB_SHIFT                                              4
+  #define PCIEIP_REG_TL_CONTROL_3_REG_DIS_D0STATE_L1_BB                                                      (0x1<<5) // When set , disables entry into L1, due to function being in D0unint state. When set, it would require all enabled functions to be in D3hot to request L1 entry.
+  #define PCIEIP_REG_TL_CONTROL_3_REG_DIS_D0STATE_L1_BB_SHIFT                                                5
+  #define PCIEIP_REG_TL_CONTROL_3_REG_EN_ASPM_L0L1_BB                                                        (0x3<<6) // When clear, field overrides the values in the ASPm Control field and disables it.
+  #define PCIEIP_REG_TL_CONTROL_3_REG_EN_ASPM_L0L1_BB_SHIFT                                                  6
+  #define PCIEIP_REG_TL_CONTROL_3_TL_REG_TXCTRL_BB                                                           (0xff<<8) // 
+  #define PCIEIP_REG_TL_CONTROL_3_TL_REG_TXCTRL_BB_SHIFT                                                     8
+  #define PCIEIP_REG_TL_CONTROL_3_OVERRIDE_L1_ENTRY_BB                                                       (0x1<<16) // This bit when set prevents DUT from entering L1 due to being in non-d0 state.
+  #define PCIEIP_REG_TL_CONTROL_3_OVERRIDE_L1_ENTRY_BB_SHIFT                                                 16
+  #define PCIEIP_REG_TL_CONTROL_3_MAX_INTER_L1_GAP_BB                                                        (0x7fff<<17) // Programmable delay to prevent link from re-entering L1, when link comes out of L1 into L0 due to PM_PME. The default value corresponds to 8 us and uses pulse_1us signal to count this value
+  #define PCIEIP_REG_TL_CONTROL_3_MAX_INTER_L1_GAP_BB_SHIFT                                                  17
+#define PCIEIP_REG_PHY_STATUS_OFF_K2_E5                                                                      0x000810UL //Access:R    DataWidth:0x20   // PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins.
+#define PCIEIP_REG_TL_CONTROL_4_BB                                                                           0x000810UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_TL_CONTROL_4_RESERVED2_BB                                                               (0xffff<<0) // For ECO/CTRL bits are reset o hard_reset
+  #define PCIEIP_REG_TL_CONTROL_4_RESERVED2_BB_SHIFT                                                         0
+  #define PCIEIP_REG_TL_CONTROL_4_RESERVED1_BB                                                               (0xffff<<16) // For ECO/Control bits are reset on perst_b
+  #define PCIEIP_REG_TL_CONTROL_4_RESERVED1_BB_SHIFT                                                         16
+#define PCIEIP_REG_PHY_CONTROL_OFF_K2_E5                                                                     0x000814UL //Access:RW   DataWidth:0x20   // PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins.
+#define PCIEIP_REG_TL_CTRLSTAT_5_BB                                                                          0x000814UL //Access:RW   DataWidth:0x20   // This register stores the status of errors to generate pcie_err_attn.
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_PSND_TLP_BB                                                           (0x1<<0) // This bit is set when h/w detects Poisoned Error Status . If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_PSND_TLP_BB_SHIFT                                                     0
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_FC_PRTL_BB                                                            (0x1<<1) // This bit is set when h/w detects Flow Control Protocol Error Status . If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_FC_PRTL_BB_SHIFT                                                      1
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_CPL_TIMEOUT_BB                                                        (0x1<<2) // This bit is set when h/w detects Completer Timeout Status . If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_CPL_TIMEOUT_BB_SHIFT                                                  2
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_MASTER_ABRT_BB                                                        (0x1<<3) // This bit is set when h/w detects Receive UR Status. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_MASTER_ABRT_BB_SHIFT                                                  3
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_UNEXP_CPL_BB                                                          (0x1<<4) // This bit is set when h/w detects Unexpected Completion Status . If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_UNEXP_CPL_BB_SHIFT                                                    4
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_RX_OFLOW_BB                                                           (0x1<<5) // This bit is set when h/w detects Receiver Overflow Status . If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_RX_OFLOW_BB_SHIFT                                                     5
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_MALF_TLP_BB                                                           (0x1<<6) // This bit is set when h/w detects Malformed TLP Status . If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_MALF_TLP_BB_SHIFT                                                     6
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_ECRC_BB                                                               (0x1<<7) // This bit is set when h/w detects ECRC Error TLP Status , If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_ECRC_BB_SHIFT                                                         7
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_UNSPPORT_BB                                                           (0x1<<8) // This bit is set when h/w detects Unsupported Request Error Status . If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_UNSPPORT_BB_SHIFT                                                     8
+  #define PCIEIP_REG_TL_CTRLSTAT_5_PRI_SIG_TARGET_ABORT_BB                                                   (0x1<<9) // 
+  #define PCIEIP_REG_TL_CTRLSTAT_5_PRI_SIG_TARGET_ABORT_BB_SHIFT                                             9
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_PSND_TLP1_BB                                                          (0x1<<10) // This bit is set when h/w detects Poisoned Error Status in function 1. If set, h/w generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_PSND_TLP1_BB_SHIFT                                                    10
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_FC_PRTL1_BB                                                           (0x1<<11) // This bit is set when h/w detects Flow Control Protocol Error Status in function 1. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_FC_PRTL1_BB_SHIFT                                                     11
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_CPL_TIMEOUT1_BB                                                       (0x1<<12) // This bit is set when h/w detects Completer Timeout Status in function 1. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_CPL_TIMEOUT1_BB_SHIFT                                                 12
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_MASTER_ABRT1_BB                                                       (0x1<<13) // This bits is set when h/w detects Receive UR Status in function 1. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_MASTER_ABRT1_BB_SHIFT                                                 13
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_UNEXP_CPL1_BB                                                         (0x1<<14) // This bit is set when h/w detects Unexpected Completion Status in function 1. If set, h/w generates pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_UNEXP_CPL1_BB_SHIFT                                                   14
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_RX_OFLOW1_BB                                                          (0x1<<15) // This bit is set when h/w detects Receiver Overflow Status in function 1. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_RX_OFLOW1_BB_SHIFT                                                    15
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_MALF_TLP1_BB                                                          (0x1<<16) // This bit is set when h/w detects Malformed TLP Status in function 1. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_MALF_TLP1_BB_SHIFT                                                    16
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_ECRC1_BB                                                              (0x1<<17) // This bit is set when h/w detects ECRC Error TLP Status in function 1. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_ECRC1_BB_SHIFT                                                        17
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_UNSPPORT1_BB                                                          (0x1<<18) // This bit is set when h/w detects Unsupported Request Error Status in function1. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_UNSPPORT1_BB_SHIFT                                                    18
+  #define PCIEIP_REG_TL_CTRLSTAT_5_PRI_SIG_TARGET_ABORT1_BB                                                  (0x1<<19) // 
+  #define PCIEIP_REG_TL_CTRLSTAT_5_PRI_SIG_TARGET_ABORT1_BB_SHIFT                                            19
+  #define PCIEIP_REG_TL_CTRLSTAT_5_TRX_ERR_UNEXP_RTAG_BB                                                     (0x1<<20) // 
+  #define PCIEIP_REG_TL_CTRLSTAT_5_TRX_ERR_UNEXP_RTAG_BB_SHIFT                                               20
+  #define PCIEIP_REG_TL_CTRLSTAT_5_TTX_ERR_NP_TAG_IN_USE_BB                                                  (0x1<<21) // 
+  #define PCIEIP_REG_TL_CTRLSTAT_5_TTX_ERR_NP_TAG_IN_USE_BB_SHIFT                                            21
+  #define PCIEIP_REG_TL_CTRLSTAT_5_DL_ERR_ATTN_BB                                                            (0x1<<22) // 
+  #define PCIEIP_REG_TL_CTRLSTAT_5_DL_ERR_ATTN_BB_SHIFT                                                      22
+  #define PCIEIP_REG_TL_CTRLSTAT_5_PHY_ERR_ATTN_BB                                                           (0x1<<23) // 
+  #define PCIEIP_REG_TL_CTRLSTAT_5_PHY_ERR_ATTN_BB_SHIFT                                                     23
+  #define PCIEIP_REG_TL_CTRLSTAT_5_TTX_TXINTF_OVERFLOW_BB                                                    (0x1<<24) // 
+  #define PCIEIP_REG_TL_CTRLSTAT_5_TTX_TXINTF_OVERFLOW_BB_SHIFT                                              24
+  #define PCIEIP_REG_TL_CTRLSTAT_5_TTX_BRIDGE_FORWARD_ERR_BB                                                 (0x1<<25) // 
+  #define PCIEIP_REG_TL_CTRLSTAT_5_TTX_BRIDGE_FORWARD_ERR_BB_SHIFT                                           25
+  #define PCIEIP_REG_TL_CTRLSTAT_5_MPS_ERR_ATTN_BB                                                           (0x1<<26) // 
+  #define PCIEIP_REG_TL_CTRLSTAT_5_MPS_ERR_ATTN_BB_SHIFT                                                     26
+  #define PCIEIP_REG_TL_CTRLSTAT_5_MRRS_ERR_ATTN_BB                                                          (0x1<<27) // 
+  #define PCIEIP_REG_TL_CTRLSTAT_5_MRRS_ERR_ATTN_BB_SHIFT                                                    27
+  #define PCIEIP_REG_TL_CTRLSTAT_5_BOUNDARY4K_ERR_ATTN_BB                                                    (0x1<<28) // 
+  #define PCIEIP_REG_TL_CTRLSTAT_5_BOUNDARY4K_ERR_ATTN_BB_SHIFT                                              28
+  #define PCIEIP_REG_TL_CTRLSTAT_5_UNKNOWNTYPE_ERR_ATTN_BB                                                   (0x1<<29) // 
+  #define PCIEIP_REG_TL_CTRLSTAT_5_UNKNOWNTYPE_ERR_ATTN_BB_SHIFT                                             29
+  #define PCIEIP_REG_TL_CTRLSTAT_5_UNUSED_1_BB                                                               (0x3<<30) // 
+  #define PCIEIP_REG_TL_CTRLSTAT_5_UNUSED_1_BB_SHIFT                                                         30
+#define PCIEIP_REG_USER_CONTROL_1_BB                                                                         0x000818UL //Access:RW   DataWidth:0x20   // This register is for use by the user. User can snoop these registers and use it for their own control.
+#define PCIEIP_REG_USER_CONTROL_2_BB                                                                         0x00081cUL //Access:RW   DataWidth:0x20   // This register is for use by the user. User can snoop these registers and use it for their own control.
+#define PCIEIP_REG_USER_CONTROL_3_BB                                                                         0x000820UL //Access:RW   DataWidth:0x20   // This register is for use by the user. User can snoop these registers and use it for their own control.
+#define PCIEIP_REG_USER_CONTROL_4_BB                                                                         0x000824UL //Access:RW   DataWidth:0x20   // This register is for use by the user. User can snoop these registers and use it for their own control.
+#define PCIEIP_REG_USER_CONTROL_5_BB                                                                         0x000828UL //Access:RW   DataWidth:0x20   // This register is for use by the user. User can snoop these registers and use it for their own control.
+#define PCIEIP_REG_USER_CONTROL_6_BB                                                                         0x00082cUL //Access:RW   DataWidth:0x20   // This register is for use by the user. User can snoop these registers and use it for their own control.
+#define PCIEIP_REG_USER_CONTROL_7_BB                                                                         0x000830UL //Access:RW   DataWidth:0x20   // This register is for use by the user. User can snoop these registers and use it for their own control.
+#define PCIEIP_REG_USER_CONTROL_8_BB                                                                         0x000834UL //Access:RW   DataWidth:0x20   // This register is for use by the user. User can snoop these registers and use it for their own control.
+#define PCIEIP_REG_TL_CONTROL_6_BB                                                                           0x00083cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_8_BB                                                             (0x1<<0) // This bit is used to disable function 8.
+  #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_8_BB_SHIFT                                                       0
+  #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_9_BB                                                             (0x1<<1) // This bit is used to disable function 9.
+  #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_9_BB_SHIFT                                                       1
+  #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_10_BB                                                            (0x1<<2) // This bit is used to disable function 10.
+  #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_10_BB_SHIFT                                                      2
+  #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_11_BB                                                            (0x1<<3) // This bit is used to disable function 11.
+  #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_11_BB_SHIFT                                                      3
+  #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_12_BB                                                            (0x1<<4) // This bit is used to disable function 12.
+  #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_12_BB_SHIFT                                                      4
+  #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_13_BB                                                            (0x1<<5) // This bit is used to disable function 13.
+  #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_13_BB_SHIFT                                                      5
+  #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_14_BB                                                            (0x1<<6) // This bit is used to disable function 14.
+  #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_14_BB_SHIFT                                                      6
+  #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_15_BB                                                            (0x1<<7) // This bit is used to disable function 15.
+  #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_15_BB_SHIFT                                                      7
+  #define PCIEIP_REG_TL_CONTROL_6_UNUSED_BB                                                                  (0xffffff<<8) // 
+  #define PCIEIP_REG_TL_CONTROL_6_UNUSED_BB_SHIFT                                                            8
+#define PCIEIP_REG_SW_LTR_VAL_BB                                                                             0x000840UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_SW_LTR_VAL_SW_SNOOP_LAT_VALUE_BB                                                        (0x3ff<<0) // Snoop latency Value.
+  #define PCIEIP_REG_SW_LTR_VAL_SW_SNOOP_LAT_VALUE_BB_SHIFT                                                  0
+  #define PCIEIP_REG_SW_LTR_VAL_SW_SNOOP_LAT_SCALE_BB                                                        (0x7<<10) // Each LTR message has a value and scale field. Values are multiplied by this scale field to yield an absolute time value expressable in a range from 1ns to 34,326,183,936ns
+  #define PCIEIP_REG_SW_LTR_VAL_SW_SNOOP_LAT_SCALE_BB_SHIFT                                                  10
+  #define PCIEIP_REG_SW_LTR_VAL_RESERVED_0_BB                                                                (0x3<<13) // 
+  #define PCIEIP_REG_SW_LTR_VAL_RESERVED_0_BB_SHIFT                                                          13
+  #define PCIEIP_REG_SW_LTR_VAL_SW_SNOOP_REQ_BB                                                              (0x1<<15) // Requirement bit indicates if device has a latency requirement for a snoop request.
+  #define PCIEIP_REG_SW_LTR_VAL_SW_SNOOP_REQ_BB_SHIFT                                                        15
+  #define PCIEIP_REG_SW_LTR_VAL_SW_NO_SNOOP_LAT_VALUE_BB                                                     (0x3ff<<16) // No_Snoop latency Value.
+  #define PCIEIP_REG_SW_LTR_VAL_SW_NO_SNOOP_LAT_VALUE_BB_SHIFT                                               16
+  #define PCIEIP_REG_SW_LTR_VAL_SW_NO_SNOOP_LAT_SCALE_BB                                                     (0x7<<26) // Each LTR message has a value and scale field. Values are multiplied by this scale field to yield an absolute time value expressable in a range from 1ns to 34,326,183,936ns
+  #define PCIEIP_REG_SW_LTR_VAL_SW_NO_SNOOP_LAT_SCALE_BB_SHIFT                                               26
+  #define PCIEIP_REG_SW_LTR_VAL_RESERVED_BB                                                                  (0x3<<29) // 
+  #define PCIEIP_REG_SW_LTR_VAL_RESERVED_BB_SHIFT                                                            29
+  #define PCIEIP_REG_SW_LTR_VAL_SW_NO_SNOOP_REQ_BB                                                           (0x1<<31) // Requirement bit indicates if device has a latency requirement for a no snoop request.
+  #define PCIEIP_REG_SW_LTR_VAL_SW_NO_SNOOP_REQ_BB_SHIFT                                                     31
+#define PCIEIP_REG_LTR0_REG_BB                                                                               0x000844UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_LTR0_REG_LTR0_SNOOP_LAT_VALUE_BB                                                        (0x3ff<<0) // Snoop latency Value.
+  #define PCIEIP_REG_LTR0_REG_LTR0_SNOOP_LAT_VALUE_BB_SHIFT                                                  0
+  #define PCIEIP_REG_LTR0_REG_LTR0_SNOOP_LAT_SCALE_BB                                                        (0x7<<10) // Each LTR message has a value and scale field. Values are multiplied by this scale field to yield an absolute time value expressable in a range from 1ns to 34,326,183,936ns
+  #define PCIEIP_REG_LTR0_REG_LTR0_SNOOP_LAT_SCALE_BB_SHIFT                                                  10
+  #define PCIEIP_REG_LTR0_REG_RESERVED_1_BB                                                                  (0x3<<13) // 
+  #define PCIEIP_REG_LTR0_REG_RESERVED_1_BB_SHIFT                                                            13
+  #define PCIEIP_REG_LTR0_REG_LTR0_SNOOP_REQ_BB                                                              (0x1<<15) // Requirement bit indicates if device has a latency requirement for a snoop request.
+  #define PCIEIP_REG_LTR0_REG_LTR0_SNOOP_REQ_BB_SHIFT                                                        15
+  #define PCIEIP_REG_LTR0_REG_LTR0_NO_SNOOP_LAT_VALUE_BB                                                     (0x3ff<<16) // No_Snoop latency Value.
+  #define PCIEIP_REG_LTR0_REG_LTR0_NO_SNOOP_LAT_VALUE_BB_SHIFT                                               16
+  #define PCIEIP_REG_LTR0_REG_LTR0_NO_SNOOP_LAT_SCALE_BB                                                     (0x7<<26) // Each LTR message has a value and scale field. Values are multiplied by this scale field to yield an absolute time value expressable in a range from 1ns to 34,326,183,936ns
+  #define PCIEIP_REG_LTR0_REG_LTR0_NO_SNOOP_LAT_SCALE_BB_SHIFT                                               26
+  #define PCIEIP_REG_LTR0_REG_RESERVED_BB                                                                    (0x3<<29) // 
+  #define PCIEIP_REG_LTR0_REG_RESERVED_BB_SHIFT                                                              29
+  #define PCIEIP_REG_LTR0_REG_LTR0_NO_SNOOP_REQ_BB                                                           (0x1<<31) // Requirement bit indicates if device has a latency requirement for a no snoop request.
+  #define PCIEIP_REG_LTR0_REG_LTR0_NO_SNOOP_REQ_BB_SHIFT                                                     31
+#define PCIEIP_REG_LTR1_REG_BB                                                                               0x000848UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_LTR1_REG_LTR1_SNOOP_LAT_VALUE_BB                                                        (0x3ff<<0) // Snoop latency Value.
+  #define PCIEIP_REG_LTR1_REG_LTR1_SNOOP_LAT_VALUE_BB_SHIFT                                                  0
+  #define PCIEIP_REG_LTR1_REG_LTR1_SNOOP_LAT_SCALE_BB                                                        (0x7<<10) // Each LTR message has a value and scale field. Values are multiplied by this scale field to yield an absolute time value expressable in a range from 1ns to 34,326,183,936ns
+  #define PCIEIP_REG_LTR1_REG_LTR1_SNOOP_LAT_SCALE_BB_SHIFT                                                  10
+  #define PCIEIP_REG_LTR1_REG_RESERVED_2_BB                                                                  (0x3<<13) // 
+  #define PCIEIP_REG_LTR1_REG_RESERVED_2_BB_SHIFT                                                            13
+  #define PCIEIP_REG_LTR1_REG_LTR1_SNOOP_REQ_BB                                                              (0x1<<15) // Requirement bit indicates if device has a latency requirement for a snoop request.
+  #define PCIEIP_REG_LTR1_REG_LTR1_SNOOP_REQ_BB_SHIFT                                                        15
+  #define PCIEIP_REG_LTR1_REG_LTR1_NO_SNOOP_LAT_VALUE_BB                                                     (0x3ff<<16) // No_Snoop latency Value.
+  #define PCIEIP_REG_LTR1_REG_LTR1_NO_SNOOP_LAT_VALUE_BB_SHIFT                                               16
+  #define PCIEIP_REG_LTR1_REG_LTR1_NO_SNOOP_LAT_SCALE_BB                                                     (0x7<<26) // Each LTR message has a value and scale field. Values are multiplied by this scale field to yield an absolute time value expressable in a range from 1ns to 34,326,183,936ns
+  #define PCIEIP_REG_LTR1_REG_LTR1_NO_SNOOP_LAT_SCALE_BB_SHIFT                                               26
+  #define PCIEIP_REG_LTR1_REG_RESERVED_BB                                                                    (0x3<<29) // 
+  #define PCIEIP_REG_LTR1_REG_RESERVED_BB_SHIFT                                                              29
+  #define PCIEIP_REG_LTR1_REG_LTR1_NO_SNOOP_REQ_BB                                                           (0x1<<31) // Requirement bit indicates if device has a latency requirement for a no snoop request.
+  #define PCIEIP_REG_LTR1_REG_LTR1_NO_SNOOP_REQ_BB_SHIFT                                                     31
+#define PCIEIP_REG_LTR2_REG_BB                                                                               0x00084cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_LTR2_REG_LTR2_SNOOP_LAT_VALUE_BB                                                        (0x3ff<<0) // Snoop latency Value.
+  #define PCIEIP_REG_LTR2_REG_LTR2_SNOOP_LAT_VALUE_BB_SHIFT                                                  0
+  #define PCIEIP_REG_LTR2_REG_LTR2_SNOOP_LAT_SCALE_BB                                                        (0x7<<10) // Each LTR message has a value and scale field. Values are multiplied by this scale field to yield an absolute time value expressable in a range from 1ns to 34,326,183,936ns
+  #define PCIEIP_REG_LTR2_REG_LTR2_SNOOP_LAT_SCALE_BB_SHIFT                                                  10
+  #define PCIEIP_REG_LTR2_REG_RESERVED_3_BB                                                                  (0x3<<13) // 
+  #define PCIEIP_REG_LTR2_REG_RESERVED_3_BB_SHIFT                                                            13
+  #define PCIEIP_REG_LTR2_REG_LTR2_SNOOP_REQ_BB                                                              (0x1<<15) // Requirement bit indicates if device has a latency requirement for a snoop request.
+  #define PCIEIP_REG_LTR2_REG_LTR2_SNOOP_REQ_BB_SHIFT                                                        15
+  #define PCIEIP_REG_LTR2_REG_LTR2_NO_SNOOP_LAT_VALUE_BB                                                     (0x3ff<<16) // No_Snoop latency Value.
+  #define PCIEIP_REG_LTR2_REG_LTR2_NO_SNOOP_LAT_VALUE_BB_SHIFT                                               16
+  #define PCIEIP_REG_LTR2_REG_LTR2_NO_SNOOP_LAT_SCALE_BB                                                     (0x7<<26) // Each LTR message has a value and scale field. Values are multiplied by this scale field to yield an absolute time value expressable in a range from 1ns to 34,326,183,936ns
+  #define PCIEIP_REG_LTR2_REG_LTR2_NO_SNOOP_LAT_SCALE_BB_SHIFT                                               26
+  #define PCIEIP_REG_LTR2_REG_RESERVED_BB                                                                    (0x3<<29) // 
+  #define PCIEIP_REG_LTR2_REG_RESERVED_BB_SHIFT                                                              29
+  #define PCIEIP_REG_LTR2_REG_LTR2_NO_SNOOP_REQ_BB                                                           (0x1<<31) // Requirement bit indicates if device has a latency requirement for a no snoop request.
+  #define PCIEIP_REG_LTR2_REG_LTR2_NO_SNOOP_REQ_BB_SHIFT                                                     31
+#define PCIEIP_REG_TL_FUNC345_MASK_BB                                                                        0x000850UL //Access:RW   DataWidth:0x20   // This register masks specific errors from setting pcie_err_attn.
+  #define PCIEIP_REG_TL_FUNC345_MASK_PES2_MASK_BB                                                            (0x1<<0) // Poisoned Error Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_FUNC345_MASK_PES2_MASK_BB_SHIFT                                                      0
+  #define PCIEIP_REG_TL_FUNC345_MASK_FCPES2_MASK_BB                                                          (0x1<<1) // Flow Control Protocol Error Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC345_MASK_FCPES2_MASK_BB_SHIFT                                                    1
+  #define PCIEIP_REG_TL_FUNC345_MASK_CTS2_MASK_BB                                                            (0x1<<2) // Completer Timeout Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC345_MASK_CTS2_MASK_BB_SHIFT                                                      2
+  #define PCIEIP_REG_TL_FUNC345_MASK_RX_UR2_MASK_BB                                                          (0x1<<3) // Received UR Status, Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC345_MASK_RX_UR2_MASK_BB_SHIFT                                                    3
+  #define PCIEIP_REG_TL_FUNC345_MASK_UCS2_MASK_BB                                                            (0x1<<4) // Unexpected Completion Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC345_MASK_UCS2_MASK_BB_SHIFT                                                      4
+  #define PCIEIP_REG_TL_FUNC345_MASK_ROS2_MASK_BB                                                            (0x1<<5) // Receiver Overflow Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_FUNC345_MASK_ROS2_MASK_BB_SHIFT                                                      5
+  #define PCIEIP_REG_TL_FUNC345_MASK_MTLPS2_MASK_BB                                                          (0x1<<6) // Malformed TLP Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_FUNC345_MASK_MTLPS2_MASK_BB_SHIFT                                                    6
+  #define PCIEIP_REG_TL_FUNC345_MASK_ECRCS2_MASK_BB                                                          (0x1<<7) // ECRC Error TLP Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_FUNC345_MASK_ECRCS2_MASK_BB_SHIFT                                                    7
+  #define PCIEIP_REG_TL_FUNC345_MASK_URES2_MASK_BB                                                           (0x1<<8) // Unsupported Request Error Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC345_MASK_URES2_MASK_BB_SHIFT                                                     8
+  #define PCIEIP_REG_TL_FUNC345_MASK_RXTABRT2_MASK_BB                                                        (0x1<<9) // Received target Abort Error Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC345_MASK_RXTABRT2_MASK_BB_SHIFT                                                  9
+  #define PCIEIP_REG_TL_FUNC345_MASK_PES3_MASK_BB                                                            (0x1<<10) // Poisoned Error Status Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_FUNC345_MASK_PES3_MASK_BB_SHIFT                                                      10
+  #define PCIEIP_REG_TL_FUNC345_MASK_FCPES3_MASK_BB                                                          (0x1<<11) // Flow Control Protocol Error Status Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC345_MASK_FCPES3_MASK_BB_SHIFT                                                    11
+  #define PCIEIP_REG_TL_FUNC345_MASK_CTS3_MASK_BB                                                            (0x1<<12) // Completer Timeout Status Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC345_MASK_CTS3_MASK_BB_SHIFT                                                      12
+  #define PCIEIP_REG_TL_FUNC345_MASK_RX_UR3_MASK_BB                                                          (0x1<<13) // Received UR Status, Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC345_MASK_RX_UR3_MASK_BB_SHIFT                                                    13
+  #define PCIEIP_REG_TL_FUNC345_MASK_UCS3_MASK_BB                                                            (0x1<<14) // Unexpected Completion Status Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC345_MASK_UCS3_MASK_BB_SHIFT                                                      14
+  #define PCIEIP_REG_TL_FUNC345_MASK_ROS3_MASK_BB                                                            (0x1<<15) // Receiver Overflow Status Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_FUNC345_MASK_ROS3_MASK_BB_SHIFT                                                      15
+  #define PCIEIP_REG_TL_FUNC345_MASK_MTLPS3_MASK_BB                                                          (0x1<<16) // Malformed TLP Status Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_FUNC345_MASK_MTLPS3_MASK_BB_SHIFT                                                    16
+  #define PCIEIP_REG_TL_FUNC345_MASK_ECRCS3_MASK_BB                                                          (0x1<<17) // ECRC Error TLP Status Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_FUNC345_MASK_ECRCS3_MASK_BB_SHIFT                                                    17
+  #define PCIEIP_REG_TL_FUNC345_MASK_URES3_MASK_BB                                                           (0x1<<18) // Unsupported Request Error Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC345_MASK_URES3_MASK_BB_SHIFT                                                     18
+  #define PCIEIP_REG_TL_FUNC345_MASK_RXTABRT3_MASK_BB                                                        (0x1<<19) // Received target Abort Error Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC345_MASK_RXTABRT3_MASK_BB_SHIFT                                                  19
+  #define PCIEIP_REG_TL_FUNC345_MASK_PES4_MASK_BB                                                            (0x1<<20) // Poisoned Error Status Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_FUNC345_MASK_PES4_MASK_BB_SHIFT                                                      20
+  #define PCIEIP_REG_TL_FUNC345_MASK_FCPES4_MASK_BB                                                          (0x1<<21) // Flow Control Protocol Error Status Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC345_MASK_FCPES4_MASK_BB_SHIFT                                                    21
+  #define PCIEIP_REG_TL_FUNC345_MASK_CTS4_MASK_BB                                                            (0x1<<22) // Completer Timeout Status Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC345_MASK_CTS4_MASK_BB_SHIFT                                                      22
+  #define PCIEIP_REG_TL_FUNC345_MASK_RX_UR4_MASK_BB                                                          (0x1<<23) // Received UR Status, Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC345_MASK_RX_UR4_MASK_BB_SHIFT                                                    23
+  #define PCIEIP_REG_TL_FUNC345_MASK_UCS4_MASK_BB                                                            (0x1<<24) // Unexpected Completion Status Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC345_MASK_UCS4_MASK_BB_SHIFT                                                      24
+  #define PCIEIP_REG_TL_FUNC345_MASK_ROS4_MASK_BB                                                            (0x1<<25) // Receiver Overflow Status Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_FUNC345_MASK_ROS4_MASK_BB_SHIFT                                                      25
+  #define PCIEIP_REG_TL_FUNC345_MASK_MTLPS4_MASK_BB                                                          (0x1<<26) // Malformed TLP Status Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_FUNC345_MASK_MTLPS4_MASK_BB_SHIFT                                                    26
+  #define PCIEIP_REG_TL_FUNC345_MASK_ECRCS4_MASK_BB                                                          (0x1<<27) // ECRC Error TLP Status Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_FUNC345_MASK_ECRCS4_MASK_BB_SHIFT                                                    27
+  #define PCIEIP_REG_TL_FUNC345_MASK_URES4_MASK_BB                                                           (0x1<<28) // Unsupported Request Error Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC345_MASK_URES4_MASK_BB_SHIFT                                                     28
+  #define PCIEIP_REG_TL_FUNC345_MASK_RXTABRT4_MASK_BB                                                        (0x1<<29) // Received target Abort Error Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC345_MASK_RXTABRT4_MASK_BB_SHIFT                                                  29
+  #define PCIEIP_REG_TL_FUNC345_MASK_UNUSED_1_BB                                                             (0x3<<30) // 
+  #define PCIEIP_REG_TL_FUNC345_MASK_UNUSED_1_BB_SHIFT                                                       30
+#define PCIEIP_REG_TL_FUNC345_STAT_BB                                                                        0x000854UL //Access:RW   DataWidth:0x20   // This register stores the status of errors to generate pcie_err_attn.
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_PSND_TLP2_BB                                                        (0x1<<0) // This bit is set when h/w detects Poisoned Error Status for Function 2. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_PSND_TLP2_BB_SHIFT                                                  0
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_FC_PRTL2_BB                                                         (0x1<<1) // This bit is set when h/w detects Flow Control Protocol Error Status for Function 2. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_FC_PRTL2_BB_SHIFT                                                   1
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2_BB                                                     (0x1<<2) // This bit is set when h/w detects Completer Timeout Status for Function 2. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2_BB_SHIFT                                               2
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MASTER_ABRT2_BB                                                     (0x1<<3) // This bit is set when h/w detects Receive UR Status in Function 2. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MASTER_ABRT2_BB_SHIFT                                               3
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNEXP_CPL2_BB                                                       (0x1<<4) // This bit is set when h/w detects Unexpected Completion Status for Function 2. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNEXP_CPL2_BB_SHIFT                                                 4
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_RX_OFLOW2_BB                                                        (0x1<<5) // This bit is set when h/w detects Receiver Overflow Status for Function 2. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_RX_OFLOW2_BB_SHIFT                                                  5
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MALF_TLP2_BB                                                        (0x1<<6) // This bit is set when h/w detects Malformed TLP Status for Function 2. If set, h/w generates pcie_err_attn output
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MALF_TLP2_BB_SHIFT                                                  6
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_ECRC2_BB                                                            (0x1<<7) // This bit is set when h/w detects ECRC Error TLP Status for Function 2. If set, h/w generates pcie_err_attn output
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_ECRC2_BB_SHIFT                                                      7
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNSPPORT2_BB                                                        (0x1<<8) // This bit is set when h/w detects Unsupported Request Error Status for Function 2. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNSPPORT2_BB_SHIFT                                                  8
+  #define PCIEIP_REG_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2_BB                                                (0x1<<9) // 
+  #define PCIEIP_REG_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2_BB_SHIFT                                          9
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_PSND_TLP3_BB                                                        (0x1<<10) // This bit is set when h/w detects Poisoned Error Status in function 3. If set, h/w generates pcie_err_attn output
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_PSND_TLP3_BB_SHIFT                                                  10
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_FC_PRTL3_BB                                                         (0x1<<11) // This bit is set when h/w detects Flow Control Protocol Error Status in function 3. If set, h/w generates pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_FC_PRTL3_BB_SHIFT                                                   11
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3_BB                                                     (0x1<<12) // This bit is set when h/w detects Completer Timeout Status in function 3. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3_BB_SHIFT                                               12
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MASTER_ABRT3_BB                                                     (0x1<<13) // This bit is set when h/w detects Receive UR Status in function 3. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MASTER_ABRT3_BB_SHIFT                                               13
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNEXP_CPL3_BB                                                       (0x1<<14) // This bit is set when h/w detects Unexpected Completion Status in function 3. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNEXP_CPL3_BB_SHIFT                                                 14
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_RX_OFLOW3_BB                                                        (0x1<<15) // This bit is set when h/w detects Receiver Overflow Status in function 3. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_RX_OFLOW3_BB_SHIFT                                                  15
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MALF_TLP3_BB                                                        (0x1<<16) // s bit is set when h/w detects Malformed TLP Status Status in function 3. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MALF_TLP3_BB_SHIFT                                                  16
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_ECRC3_BB                                                            (0x1<<17) // This bit is set when h/w detects ECRC Error TLP Status in function 3. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_ECRC3_BB_SHIFT                                                      17
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNSPPORT3_BB                                                        (0x1<<18) // This bit is set when h/w detects Unsupported Request Error Status in function3. If set, h/w generates pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNSPPORT3_BB_SHIFT                                                  18
+  #define PCIEIP_REG_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3_BB                                                (0x1<<19) // 
+  #define PCIEIP_REG_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3_BB_SHIFT                                          19
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_PSND_TLP4_BB                                                        (0x1<<20) // This bit is set when h/w detects Poisoned Error Status Status in function 4. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_PSND_TLP4_BB_SHIFT                                                  20
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_FC_PRTL4_BB                                                         (0x1<<21) // This bit is set when h/w detects Flow Control Protocol Error Status in function 4. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_FC_PRTL4_BB_SHIFT                                                   21
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4_BB                                                     (0x1<<22) // This bit is set when h/w detects Completer Timeout Status in function 4. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4_BB_SHIFT                                               22
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MASTER_ABRT4_BB                                                     (0x1<<23) // This bit is set when h/w detects Receive UR Statusin function 4. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MASTER_ABRT4_BB_SHIFT                                               23
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNEXP_CPL4_BB                                                       (0x1<<24) // This bit is set when h/w detects Unexpected Completion Status in function 4. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNEXP_CPL4_BB_SHIFT                                                 24
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_RX_OFLOW4_BB                                                        (0x1<<25) // This bit is set when h/w detects Receiver Overflow Status in function 4. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_RX_OFLOW4_BB_SHIFT                                                  25
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MALF_TLP4_BB                                                        (0x1<<26) // This bit is set when h/w detects Malformed TLP Status in function 4. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MALF_TLP4_BB_SHIFT                                                  26
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_ECRC4_BB                                                            (0x1<<27) // This bit is set when h/w detects ECRC Error TLP Status in function 4. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_ECRC4_BB_SHIFT                                                      27
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNSPPORT4_BB                                                        (0x1<<28) // This bit is set when h/w detects Unsupported Request Error Status in function4. If set, h/w generates pcie_err_attn output .
+  #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNSPPORT4_BB_SHIFT                                                  28
+  #define PCIEIP_REG_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4_BB                                                (0x1<<29) // 
+  #define PCIEIP_REG_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4_BB_SHIFT                                          29
+  #define PCIEIP_REG_TL_FUNC345_STAT_UNUSED_1_BB                                                             (0x3<<30) // 
+  #define PCIEIP_REG_TL_FUNC345_STAT_UNUSED_1_BB_SHIFT                                                       30
+#define PCIEIP_REG_TL_FUNC678_MASK_BB                                                                        0x000858UL //Access:RW   DataWidth:0x20   // This register masks specific errors from setting pcie_err_attn.
+  #define PCIEIP_REG_TL_FUNC678_MASK_PES5_MASK_BB                                                            (0x1<<0) // Poisoned Error Status Status Mask. If set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_FUNC678_MASK_PES5_MASK_BB_SHIFT                                                      0
+  #define PCIEIP_REG_TL_FUNC678_MASK_FCPES5_MASK_BB                                                          (0x1<<1) // Flow Control Protocol Error Status Status Mask. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC678_MASK_FCPES5_MASK_BB_SHIFT                                                    1
+  #define PCIEIP_REG_TL_FUNC678_MASK_CTS5_MASK_BB                                                            (0x1<<2) // Completer Timeout Status Status Mask. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC678_MASK_CTS5_MASK_BB_SHIFT                                                      2
+  #define PCIEIP_REG_TL_FUNC678_MASK_RX_UR5_MASK_BB                                                          (0x1<<3) // Received UR Status, Status Mask. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC678_MASK_RX_UR5_MASK_BB_SHIFT                                                    3
+  #define PCIEIP_REG_TL_FUNC678_MASK_UCS5_MASK_BB                                                            (0x1<<4) // Unexpected Completion Status Status Mask. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC678_MASK_UCS5_MASK_BB_SHIFT                                                      4
+  #define PCIEIP_REG_TL_FUNC678_MASK_ROS5_MASK_BB                                                            (0x1<<5) // Receiver Overflow Status Status Mask. If set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_FUNC678_MASK_ROS5_MASK_BB_SHIFT                                                      5
+  #define PCIEIP_REG_TL_FUNC678_MASK_MTLPS5_MASK_BB                                                          (0x1<<6) // Malformed TLP Status Status Mask. If set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_FUNC678_MASK_MTLPS5_MASK_BB_SHIFT                                                    6
+  #define PCIEIP_REG_TL_FUNC678_MASK_ECRCS5_MASK_BB                                                          (0x1<<7) // ECRC Error TLP Status Status Mask. If set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_FUNC678_MASK_ECRCS5_MASK_BB_SHIFT                                                    7
+  #define PCIEIP_REG_TL_FUNC678_MASK_URES5_MASK_BB                                                           (0x1<<8) // Unsupported Request Error Status Mask. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC678_MASK_URES5_MASK_BB_SHIFT                                                     8
+  #define PCIEIP_REG_TL_FUNC678_MASK_RXTABRT5_MASK_BB                                                        (0x1<<9) // Received target Abort Error Status Mask. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC678_MASK_RXTABRT5_MASK_BB_SHIFT                                                  9
+  #define PCIEIP_REG_TL_FUNC678_MASK_PES6_MASK_BB                                                            (0x1<<10) // Poisoned Error Status Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_FUNC678_MASK_PES6_MASK_BB_SHIFT                                                      10
+  #define PCIEIP_REG_TL_FUNC678_MASK_FCPES6_MASK_BB                                                          (0x1<<11) // Flow Control Protocol Error Status Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC678_MASK_FCPES6_MASK_BB_SHIFT                                                    11
+  #define PCIEIP_REG_TL_FUNC678_MASK_CTS6_MASK_BB                                                            (0x1<<12) // Completer Timeout Status Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC678_MASK_CTS6_MASK_BB_SHIFT                                                      12
+  #define PCIEIP_REG_TL_FUNC678_MASK_RX_UR6_MASK_BB                                                          (0x1<<13) // Received UR Status, Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC678_MASK_RX_UR6_MASK_BB_SHIFT                                                    13
+  #define PCIEIP_REG_TL_FUNC678_MASK_UCS6_MASK_BB                                                            (0x1<<14) // Unexpected Completion Status Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC678_MASK_UCS6_MASK_BB_SHIFT                                                      14
+  #define PCIEIP_REG_TL_FUNC678_MASK_ROS6_MASK_BB                                                            (0x1<<15) // Receiver Overflow Status Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_FUNC678_MASK_ROS6_MASK_BB_SHIFT                                                      15
+  #define PCIEIP_REG_TL_FUNC678_MASK_MTLPS6_MASK_BB                                                          (0x1<<16) // Malformed TLP Status Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_FUNC678_MASK_MTLPS6_MASK_BB_SHIFT                                                    16
+  #define PCIEIP_REG_TL_FUNC678_MASK_ECRCS6_MASK_BB                                                          (0x1<<17) // ECRC Error TLP Status Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_FUNC678_MASK_ECRCS6_MASK_BB_SHIFT                                                    17
+  #define PCIEIP_REG_TL_FUNC678_MASK_URES6_MASK_BB                                                           (0x1<<18) // Unsupported Request Error Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC678_MASK_URES6_MASK_BB_SHIFT                                                     18
+  #define PCIEIP_REG_TL_FUNC678_MASK_RXTABRT6_MASK_BB                                                        (0x1<<19) // Received target Abort Error Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC678_MASK_RXTABRT6_MASK_BB_SHIFT                                                  19
+  #define PCIEIP_REG_TL_FUNC678_MASK_PES7_MASK_BB                                                            (0x1<<20) // Poisoned Error Status Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_FUNC678_MASK_PES7_MASK_BB_SHIFT                                                      20
+  #define PCIEIP_REG_TL_FUNC678_MASK_FCPES7_MASK_BB                                                          (0x1<<21) // Flow Control Protocol Error Status Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC678_MASK_FCPES7_MASK_BB_SHIFT                                                    21
+  #define PCIEIP_REG_TL_FUNC678_MASK_CTS7_MASK_BB                                                            (0x1<<22) // Completer Timeout Status Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC678_MASK_CTS7_MASK_BB_SHIFT                                                      22
+  #define PCIEIP_REG_TL_FUNC678_MASK_RX_UR7_MASK_BB                                                          (0x1<<23) // Received UR Status, Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC678_MASK_RX_UR7_MASK_BB_SHIFT                                                    23
+  #define PCIEIP_REG_TL_FUNC678_MASK_UCS7_MASK_BB                                                            (0x1<<24) // Unexpected Completion Status Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC678_MASK_UCS7_MASK_BB_SHIFT                                                      24
+  #define PCIEIP_REG_TL_FUNC678_MASK_ROS7_MASK_BB                                                            (0x1<<25) // Receiver Overflow Status Status Mask for Function7, if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_FUNC678_MASK_ROS7_MASK_BB_SHIFT                                                      25
+  #define PCIEIP_REG_TL_FUNC678_MASK_MTLPS7_MASK_BB                                                          (0x1<<26) // Malformed TLP Status Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_FUNC678_MASK_MTLPS7_MASK_BB_SHIFT                                                    26
+  #define PCIEIP_REG_TL_FUNC678_MASK_ECRCS7_MASK_BB                                                          (0x1<<27) // ECRC Error TLP Status Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen..
+  #define PCIEIP_REG_TL_FUNC678_MASK_ECRCS7_MASK_BB_SHIFT                                                    27
+  #define PCIEIP_REG_TL_FUNC678_MASK_URES7_MASK_BB                                                           (0x1<<28) // Unsupported Request Error Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC678_MASK_URES7_MASK_BB_SHIFT                                                     28
+  #define PCIEIP_REG_TL_FUNC678_MASK_RXTABRT7_MASK_BB                                                        (0x1<<29) // Received target Abort Error Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC678_MASK_RXTABRT7_MASK_BB_SHIFT                                                  29
+  #define PCIEIP_REG_TL_FUNC678_MASK_UNUSED_1_BB                                                             (0x3<<30) // 
+  #define PCIEIP_REG_TL_FUNC678_MASK_UNUSED_1_BB_SHIFT                                                       30
+#define PCIEIP_REG_TL_FUNC678_STAT_BB                                                                        0x00085cUL //Access:RW   DataWidth:0x20   // This register stores the status of errors to generate pcie_err_attn.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_PSND_TLP5_BB                                                        (0x1<<0) // Poisoned Error Status detected for Function 5. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_PSND_TLP5_BB_SHIFT                                                  0
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_FC_PRTL5_BB                                                         (0x1<<1) // Flow Control Protocol Error Status detected for Function 5, if set, generate pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_FC_PRTL5_BB_SHIFT                                                   1
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5_BB                                                     (0x1<<2) // Completer Timeout Status detected for Function 5. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5_BB_SHIFT                                               2
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MASTER_ABRT5_BB                                                     (0x1<<3) // Receive UR Status detectedfor Function 5. If set, generate pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MASTER_ABRT5_BB_SHIFT                                               3
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNEXP_CPL5_BB                                                       (0x1<<4) // Unexpected Completion Status detected for Function 5, if set, generate pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNEXP_CPL5_BB_SHIFT                                                 4
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_RX_OFLOW5_BB                                                        (0x1<<5) // Receiver Overflow Status detected for Function 5. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_RX_OFLOW5_BB_SHIFT                                                  5
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MALF_TLP5_BB                                                        (0x1<<6) // Malformed TLP Status detected for Function 5. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MALF_TLP5_BB_SHIFT                                                  6
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_ECRC5_BB                                                            (0x1<<7) // ECRC Error TLP Status detected for Function 5. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_ECRC5_BB_SHIFT                                                      7
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNSPPORT5_BB                                                        (0x1<<8) // Unsupported Request Error Status detected for Function 5. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNSPPORT5_BB_SHIFT                                                  8
+  #define PCIEIP_REG_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5_BB                                                (0x1<<9) // 
+  #define PCIEIP_REG_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5_BB_SHIFT                                          9
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_PSND_TLP6_BB                                                        (0x1<<10) // Poisoned Error Status detected in function 6. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_PSND_TLP6_BB_SHIFT                                                  10
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_FC_PRTL6_BB                                                         (0x1<<11) // Flow Control Protocol Error Status detected in function 6, if set, generate pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_FC_PRTL6_BB_SHIFT                                                   11
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6_BB                                                     (0x1<<12) // Completer Timeout Status detected in function 6. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6_BB_SHIFT                                               12
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MASTER_ABRT6_BB                                                     (0x1<<13) // Receive UR Status detectedin function 6. If set, generate pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MASTER_ABRT6_BB_SHIFT                                               13
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNEXP_CPL6_BB                                                       (0x1<<14) // Unexpected Completion Status detected in function 6, if set, generate pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNEXP_CPL6_BB_SHIFT                                                 14
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_RX_OFLOW6_BB                                                        (0x1<<15) // Receiver Overflow Status detected in function 6. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_RX_OFLOW6_BB_SHIFT                                                  15
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MALF_TLP6_BB                                                        (0x1<<16) // Malformed TLP Status detected in function 6. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MALF_TLP6_BB_SHIFT                                                  16
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_ECRC6_BB                                                            (0x1<<17) // ECRC Error TLP Status detected in function 6. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_ECRC6_BB_SHIFT                                                      17
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNSPPORT6_BB                                                        (0x1<<18) // Unsupported Request Error Status detected in function6. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNSPPORT6_BB_SHIFT                                                  18
+  #define PCIEIP_REG_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6_BB                                                (0x1<<19) // 
+  #define PCIEIP_REG_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6_BB_SHIFT                                          19
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_PSND_TLP7_BB                                                        (0x1<<20) // Poisoned Error Status detected in function 7. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_PSND_TLP7_BB_SHIFT                                                  20
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_FC_PRTL7_BB                                                         (0x1<<21) // Flow Control Protocol Error Status detected in function 7, if set, generate pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_FC_PRTL7_BB_SHIFT                                                   21
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7_BB                                                     (0x1<<22) // Completer Timeout Status detected in function 7. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7_BB_SHIFT                                               22
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MASTER_ABRT7_BB                                                     (0x1<<23) // Receive UR Status detectedin function 7. If set, generate pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MASTER_ABRT7_BB_SHIFT                                               23
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNEXP_CPL7_BB                                                       (0x1<<24) // Unexpected Completion Status detected in function 7, if set, generate pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNEXP_CPL7_BB_SHIFT                                                 24
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_RX_OFLOW7_BB                                                        (0x1<<25) // Receiver Overflow Status detected in function 7. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_RX_OFLOW7_BB_SHIFT                                                  25
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MALF_TLP7_BB                                                        (0x1<<26) // Malformed TLP Status detected in function 7. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MALF_TLP7_BB_SHIFT                                                  26
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_ECRC7_BB                                                            (0x1<<27) // ECRC Error TLP Status detected in function 7. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_ECRC7_BB_SHIFT                                                      27
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNSPPORT7_BB                                                        (0x1<<28) // Unsupported Request Error Status detected in function7. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNSPPORT7_BB_SHIFT                                                  28
+  #define PCIEIP_REG_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7_BB                                                (0x1<<29) // 
+  #define PCIEIP_REG_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7_BB_SHIFT                                          29
+  #define PCIEIP_REG_TL_FUNC678_STAT_UNUSED_1_BB                                                             (0x3<<30) // 
+  #define PCIEIP_REG_TL_FUNC678_STAT_UNUSED_1_BB_SHIFT                                                       30
+#define PCIEIP_REG_FUNC_INT_SEL_BB                                                                           0x000860UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_FUNC_INT_SEL_FUNC0_INT_SEL_BB                                                           (0x7<<0) // Route the interrupt pin for Function 0 to any of INTA to INTD or no interrupt.
+  #define PCIEIP_REG_FUNC_INT_SEL_FUNC0_INT_SEL_BB_SHIFT                                                     0
+  #define PCIEIP_REG_FUNC_INT_SEL_FUNC1_INT_SEL_BB                                                           (0x7<<3) // Route the interrupt pin for Function 1 to any of INTA to INTD or no interrupt.
+  #define PCIEIP_REG_FUNC_INT_SEL_FUNC1_INT_SEL_BB_SHIFT                                                     3
+  #define PCIEIP_REG_FUNC_INT_SEL_FUNC2_INT_SEL_BB                                                           (0x7<<6) // Route the interrupt pin for Function 2 to any of INTA to INTD or no interrupt.
+  #define PCIEIP_REG_FUNC_INT_SEL_FUNC2_INT_SEL_BB_SHIFT                                                     6
+  #define PCIEIP_REG_FUNC_INT_SEL_FUNC3_INT_SEL_BB                                                           (0x7<<9) // Route the interrupt pin for Function 3 to any of INTA to INTD or no interrupt.
+  #define PCIEIP_REG_FUNC_INT_SEL_FUNC3_INT_SEL_BB_SHIFT                                                     9
+  #define PCIEIP_REG_FUNC_INT_SEL_FUNC4_INT_SEL_BB                                                           (0x7<<12) // Route the interrupt pin for Function 4 to any of INTA to INTD or no interrupt.
+  #define PCIEIP_REG_FUNC_INT_SEL_FUNC4_INT_SEL_BB_SHIFT                                                     12
+  #define PCIEIP_REG_FUNC_INT_SEL_FUNC5_INT_SEL_BB                                                           (0x7<<15) // Route the interrupt pin for Function 5 to any of INTA to INTD or no interrupt.
+  #define PCIEIP_REG_FUNC_INT_SEL_FUNC5_INT_SEL_BB_SHIFT                                                     15
+  #define PCIEIP_REG_FUNC_INT_SEL_FUNC6_INT_SEL_BB                                                           (0x7<<18) // Route the interrupt pin for Function 6 to any of INTA to INTD or no interrupt.
+  #define PCIEIP_REG_FUNC_INT_SEL_FUNC6_INT_SEL_BB_SHIFT                                                     18
+  #define PCIEIP_REG_FUNC_INT_SEL_FUNC7_INT_SEL_BB                                                           (0x7<<21) // Route the interrupt pin for Function 7 to any of INTA to INTD or no interrupt.
+  #define PCIEIP_REG_FUNC_INT_SEL_FUNC7_INT_SEL_BB_SHIFT                                                     21
+  #define PCIEIP_REG_FUNC_INT_SEL_UNUSED0_BB                                                                 (0xff<<24) // 
+  #define PCIEIP_REG_FUNC_INT_SEL_UNUSED0_BB_SHIFT                                                           24
+#define PCIEIP_REG_FUNC_INT_SEL2_BB                                                                          0x000864UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_FUNC_INT_SEL2_FUNC8_INT_SEL_BB                                                          (0x7<<0) // Route the interrupt pin for Function 0 8o any of INTA to INTD or no interrupt.
+  #define PCIEIP_REG_FUNC_INT_SEL2_FUNC8_INT_SEL_BB_SHIFT                                                    0
+  #define PCIEIP_REG_FUNC_INT_SEL2_FUNC9_INT_SEL_BB                                                          (0x7<<3) // Route the interrupt pin for Function 9 to any of INTA to INTD or no interrupt.
+  #define PCIEIP_REG_FUNC_INT_SEL2_FUNC9_INT_SEL_BB_SHIFT                                                    3
+  #define PCIEIP_REG_FUNC_INT_SEL2_FUNC10_INT_SEL_BB                                                         (0x7<<6) // Route the interrupt pin for Function 10 to any of INTA to INTD or no interrupt.
+  #define PCIEIP_REG_FUNC_INT_SEL2_FUNC10_INT_SEL_BB_SHIFT                                                   6
+  #define PCIEIP_REG_FUNC_INT_SEL2_FUNC11_INT_SEL_BB                                                         (0x7<<9) // Route the interrupt pin for Function 11 to any of INTA to INTD or no interrupt.
+  #define PCIEIP_REG_FUNC_INT_SEL2_FUNC11_INT_SEL_BB_SHIFT                                                   9
+  #define PCIEIP_REG_FUNC_INT_SEL2_FUNC12_INT_SEL_BB                                                         (0x7<<12) // Route the interrupt pin for Function 12 to any of INTA to INTD or no interrupt.
+  #define PCIEIP_REG_FUNC_INT_SEL2_FUNC12_INT_SEL_BB_SHIFT                                                   12
+  #define PCIEIP_REG_FUNC_INT_SEL2_FUNC13_INT_SEL_BB                                                         (0x7<<15) // Route the interrupt pin for Function 13 to any of INTA to INTD or no interrupt.
+  #define PCIEIP_REG_FUNC_INT_SEL2_FUNC13_INT_SEL_BB_SHIFT                                                   15
+  #define PCIEIP_REG_FUNC_INT_SEL2_FUNC14_INT_SEL_BB                                                         (0x7<<18) // Route the interrupt pin for Function 14 to any of INTA to INTD or no interrupt.
+  #define PCIEIP_REG_FUNC_INT_SEL2_FUNC14_INT_SEL_BB_SHIFT                                                   18
+  #define PCIEIP_REG_FUNC_INT_SEL2_FUNC15_INT_SEL_BB                                                         (0x7<<21) // Route the interrupt pin for Function 15 to any of INTA to INTD or no interrupt.
+  #define PCIEIP_REG_FUNC_INT_SEL2_FUNC15_INT_SEL_BB_SHIFT                                                   21
+  #define PCIEIP_REG_FUNC_INT_SEL2_UNUSED0_BB                                                                (0xff<<24) // 
+  #define PCIEIP_REG_FUNC_INT_SEL2_UNUSED0_BB_SHIFT                                                          24
+#define PCIEIP_REG_TL_RST_CTRL_BB                                                                            0x000868UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_TL_RST_CTRL_SEL_DIS_MDIO_PERST_BB                                                       (0x1<<0) // This bit when cleared will keep the Serdes MDIO regs in reset till PERST_N is released. Default behavior is to release Serdes MDIO from reset on Vaux power being present.
+  #define PCIEIP_REG_TL_RST_CTRL_SEL_DIS_MDIO_PERST_BB_SHIFT                                                 0
+  #define PCIEIP_REG_TL_RST_CTRL_SEL_DIS_UC_PERST_BB                                                         (0x1<<1) // This bit when cleared will keep the micro in reset till PERST_N is released. Default behavior is to release micro from reset on Vaux power being present.
+  #define PCIEIP_REG_TL_RST_CTRL_SEL_DIS_UC_PERST_BB_SHIFT                                                   1
+  #define PCIEIP_REG_TL_RST_CTRL_SOFT_MDIO_RST_BB                                                            (0x1<<2) // This bit when set will reset the Serdes register space, provided bit 3 is also set.
+  #define PCIEIP_REG_TL_RST_CTRL_SOFT_MDIO_RST_BB_SHIFT                                                      2
+  #define PCIEIP_REG_TL_RST_CTRL_SEL_SOFT_MDIO_RST_BB                                                        (0x1<<3) // Tthis bit when set will allow bit 2 value to propogate to Serdes. This bit acts as the mux sel for a soft MDIO reset.
+  #define PCIEIP_REG_TL_RST_CTRL_SEL_SOFT_MDIO_RST_BB_SHIFT                                                  3
+  #define PCIEIP_REG_TL_RST_CTRL_SOFT_UC_RST_BB                                                              (0x1<<4) // This bit when set will reset the micro, provided bit 5 is also set.
+  #define PCIEIP_REG_TL_RST_CTRL_SOFT_UC_RST_BB_SHIFT                                                        4
+  #define PCIEIP_REG_TL_RST_CTRL_SEL_SOFT_UC_RST_BB                                                          (0x1<<5) // For gen3 serdes, this bit when set will allow bit 4 value to propogate to uc reset. This bit acts as the mux sel for a soft micro reset.
+  #define PCIEIP_REG_TL_RST_CTRL_SEL_SOFT_UC_RST_BB_SHIFT                                                    5
+  #define PCIEIP_REG_TL_RST_CTRL_UNUSED0_BB                                                                  (0x3<<6) // 
+  #define PCIEIP_REG_TL_RST_CTRL_UNUSED0_BB_SHIFT                                                            6
+  #define PCIEIP_REG_TL_RST_CTRL_ENABLE_ALT_MSG_ERROR_BB                                                     (0x1<<8) // Based on 3.0 errata, allows interpreting Rx messages with routing errors or hdr type errors to be UR instead of malformed.
+  #define PCIEIP_REG_TL_RST_CTRL_ENABLE_ALT_MSG_ERROR_BB_SHIFT                                               8
+  #define PCIEIP_REG_TL_RST_CTRL_RESERVED_BB                                                                 (0x7fffff<<9) // 
+  #define PCIEIP_REG_TL_RST_CTRL_RESERVED_BB_SHIFT                                                           9
+#define PCIEIP_REG_TL_OBFF_CTRL_BB                                                                           0x000870UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_TL_OBFF_CTRL_MIN_OBFF_PULSE_BB                                                          (0x7f<<0) // Min number of PM clocks to wait after WAKE# signal transition, so that it is throughly debounced.
+  #define PCIEIP_REG_TL_OBFF_CTRL_MIN_OBFF_PULSE_BB_SHIFT                                                    0
+  #define PCIEIP_REG_TL_OBFF_CTRL_UNUSED0_BB                                                                 (0x1<<7) // 
+  #define PCIEIP_REG_TL_OBFF_CTRL_UNUSED0_BB_SHIFT                                                           7
+  #define PCIEIP_REG_TL_OBFF_CTRL_MAX_OBFF_PULSE_BB                                                          (0x7f<<8) // Max number of PM clocks to wait after WAKE# signal transition to declare OBFF state
+  #define PCIEIP_REG_TL_OBFF_CTRL_MAX_OBFF_PULSE_BB_SHIFT                                                    8
+  #define PCIEIP_REG_TL_OBFF_CTRL_UNUSED1_BB                                                                 (0x1<<15) // 
+  #define PCIEIP_REG_TL_OBFF_CTRL_UNUSED1_BB_SHIFT                                                           15
+  #define PCIEIP_REG_TL_OBFF_CTRL_RESERVED_BB                                                                (0xffff<<16) // 
+  #define PCIEIP_REG_TL_OBFF_CTRL_RESERVED_BB_SHIFT                                                          16
+#define PCIEIP_REG_TL_CTLSTAT_0_BB                                                                           0x000874UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_1_HIDDEN_BB                                                      (0x1<<0) // Set if func1 is hidden either due to hide_func_1 pad being driven high or due to programming bit in TL reg This bit is tied to 0, if IP does not support multiple functions.
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_1_HIDDEN_BB_SHIFT                                                0
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_2_HIDDEN_BB                                                      (0x1<<1) // Set if func2 is hidden either due to hide_func_2 pad being driven high or due to programming bit in TL reg
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_2_HIDDEN_BB_SHIFT                                                1
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_3_HIDDEN_BB                                                      (0x1<<2) // Set if func3 is hidden either due to hide_func_3 pad being driven high or due to programming bit in TL reg
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_3_HIDDEN_BB_SHIFT                                                2
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_4_HIDDEN_BB                                                      (0x1<<3) // Set if func4 is hidden either due to hide_func_4 pad being driven high or due to programming bit in TL reg
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_4_HIDDEN_BB_SHIFT                                                3
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_5_HIDDEN_BB                                                      (0x1<<4) // Set if func5 is hidden either due to hide_func_5 pad being driven high or due to programming bit in TL reg
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_5_HIDDEN_BB_SHIFT                                                4
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_6_HIDDEN_BB                                                      (0x1<<5) // Set if func6 is hidden either due to hide_func_6 pad being driven high or due to programming bit in TL reg
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_6_HIDDEN_BB_SHIFT                                                5
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_7_HIDDEN_BB                                                      (0x1<<6) // Set if func7 is hidden either due to hide_func_7 pad being driven high or due to programming bit in TL reg
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_7_HIDDEN_BB_SHIFT                                                6
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_8_HIDDEN_BB                                                      (0x1<<7) // Set if func8 is hidden either due to hide_func_8 pad being driven high or due to programming bit in TL reg
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_8_HIDDEN_BB_SHIFT                                                7
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_9_HIDDEN_BB                                                      (0x1<<8) // Set if func9 is hidden either due to hide_func_9 pad being driven high or due to programming bit in TL reg
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_9_HIDDEN_BB_SHIFT                                                8
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_10_HIDDEN_BB                                                     (0x1<<9) // Set if func10 is hidden either due to hide_func_10 pad being driven high or due to programming bit in TL reg
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_10_HIDDEN_BB_SHIFT                                               9
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_11_HIDDEN_BB                                                     (0x1<<10) // Set if func11 is hidden either due to hide_func_11 pad being driven high or due to programming bit in TL reg
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_11_HIDDEN_BB_SHIFT                                               10
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_12_HIDDEN_BB                                                     (0x1<<11) // Set if func12 is hidden either due to hide_func_12 pad being driven high or due to programming bit in TL reg
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_12_HIDDEN_BB_SHIFT                                               11
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_13_HIDDEN_BB                                                     (0x1<<12) // Set if func13 is hidden either due to hide_func_13 pad being driven high or due to programming bit in TL reg
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_13_HIDDEN_BB_SHIFT                                               12
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_14_HIDDEN_BB                                                     (0x1<<13) // Set if func14 is hidden either due to hide_func_14 pad being driven high or due to programming bit in TL reg
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_14_HIDDEN_BB_SHIFT                                               13
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_15_HIDDEN_BB                                                     (0x1<<14) // Set if func15 is hidden either due to hide_func_15 pad being driven high or due to programming bit in TL reg
+  #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_15_HIDDEN_BB_SHIFT                                               14
+  #define PCIEIP_REG_TL_CTLSTAT_0_UNUSED0_BB                                                                 (0x7<<15) // 
+  #define PCIEIP_REG_TL_CTLSTAT_0_UNUSED0_BB_SHIFT                                                           15
+  #define PCIEIP_REG_TL_CTLSTAT_0_TL_DBG_MALF_ERR_BB                                                         (0x3fff<<18) // debug status for sources of malformed TLP error.
+  #define PCIEIP_REG_TL_CTLSTAT_0_TL_DBG_MALF_ERR_BB_SHIFT                                                   18
+#define PCIEIP_REG_PM_STATUS_0_BB                                                                            0x000878UL //Access:R    DataWidth:0x20   // For Debug.
+  #define PCIEIP_REG_PM_STATUS_0_PME_SENT_SM0_BB                                                             (0x1f<<0) // State machine that handles PME for Function
+  #define PCIEIP_REG_PM_STATUS_0_PME_SENT_SM0_BB_SHIFT                                                       0
+  #define PCIEIP_REG_PM_STATUS_0_UNUSED0_BB                                                                  (0x7ff<<5) // 
+  #define PCIEIP_REG_PM_STATUS_0_UNUSED0_BB_SHIFT                                                            5
+  #define PCIEIP_REG_PM_STATUS_0_OBFF_CURR_STATE_BB                                                          (0xf<<16) // State machine that handles OBFF for Function
+  #define PCIEIP_REG_PM_STATUS_0_OBFF_CURR_STATE_BB_SHIFT                                                    16
+  #define PCIEIP_REG_PM_STATUS_0_PCIE_OBFF_STATE_BB                                                          (0xf<<20) // Current OBFF state Indication from DUT.
+  #define PCIEIP_REG_PM_STATUS_0_PCIE_OBFF_STATE_BB_SHIFT                                                    20
+  #define PCIEIP_REG_PM_STATUS_0_PM_LINK_STATE_SM_BB                                                         (0xff<<24) // State machine that controls current PM Link state.
+  #define PCIEIP_REG_PM_STATUS_0_PM_LINK_STATE_SM_BB_SHIFT                                                   24
+#define PCIEIP_REG_PM_STATUS_1_BB                                                                            0x00087cUL //Access:R    DataWidth:0x20   // For Debug.
+  #define PCIEIP_REG_PM_STATUS_1_CFG_PME_ENABLE0_BB                                                          (0x1<<0) // Direct reflection of Config PM PME enable bit for function 0.
+  #define PCIEIP_REG_PM_STATUS_1_CFG_PME_ENABLE0_BB_SHIFT                                                    0
+  #define PCIEIP_REG_PM_STATUS_1_CFG_PME_STATUS0_BB                                                          (0x1<<1) // Direct reflection of config PM PME status bit for function 0.
+  #define PCIEIP_REG_PM_STATUS_1_CFG_PME_STATUS0_BB_SHIFT                                                    1
+  #define PCIEIP_REG_PM_STATUS_1_CFG_AUX_PWR_PM_EN0_BB                                                       (0x1<<2) // Direct reflection of CFG link control, Aux power PM enabled.
+  #define PCIEIP_REG_PM_STATUS_1_CFG_AUX_PWR_PM_EN0_BB_SHIFT                                                 2
+  #define PCIEIP_REG_PM_STATUS_1_CFG_PME_ENABLE1_BB                                                          (0x1<<3) // Direct reflection of Config PM PME enable bit for function 1.
+  #define PCIEIP_REG_PM_STATUS_1_CFG_PME_ENABLE1_BB_SHIFT                                                    3
+  #define PCIEIP_REG_PM_STATUS_1_CFG_PME_STATUS1_BB                                                          (0x1<<4) // Direct reflection of config PM PME status bit for function 1.
+  #define PCIEIP_REG_PM_STATUS_1_CFG_PME_STATUS1_BB_SHIFT                                                    4
+  #define PCIEIP_REG_PM_STATUS_1_CFG_AUX_PWR_PM_EN1_BB                                                       (0x1<<5) // Direct reflection of CFG link control, Aux power PM enabled.
+  #define PCIEIP_REG_PM_STATUS_1_CFG_AUX_PWR_PM_EN1_BB_SHIFT                                                 5
+  #define PCIEIP_REG_PM_STATUS_1_UNUSED0_BB                                                                  (0x3ffff<<6) // 
+  #define PCIEIP_REG_PM_STATUS_1_UNUSED0_BB_SHIFT                                                            6
+  #define PCIEIP_REG_PM_STATUS_1_REG_BUS_NUM_BB                                                              (0xff<<24) // Current Bus Number Latched by device.
+  #define PCIEIP_REG_PM_STATUS_1_REG_BUS_NUM_BB_SHIFT                                                        24
+#define PCIEIP_REG_TL_FUNC8TO10_MASK_BB                                                                      0x000880UL //Access:RW   DataWidth:0x20   // This register masks specific errors from setting pcie_err_attn for functions 8, 9, and 10.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_PES8_MASK_BB                                                          (0x1<<0) // Poisoned Error Status Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_PES8_MASK_BB_SHIFT                                                    0
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_FCPES8_MASK_BB                                                        (0x1<<1) // Flow Control Protocol Error Status Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_FCPES8_MASK_BB_SHIFT                                                  1
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_CTS8_MASK_BB                                                          (0x1<<2) // Completer Timeout Status Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_CTS8_MASK_BB_SHIFT                                                    2
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_RX_UR8_MASK_BB                                                        (0x1<<3) // Received UR Status, Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_RX_UR8_MASK_BB_SHIFT                                                  3
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_UCS8_MASK_BB                                                          (0x1<<4) // Unexpected Completion Status Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_UCS8_MASK_BB_SHIFT                                                    4
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_ROS8_MASK_BB                                                          (0x1<<5) // Receiver Overflow Status Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_ROS8_MASK_BB_SHIFT                                                    5
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_MTLPS8_MASK_BB                                                        (0x1<<6) // Malformed TLP Status Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_MTLPS8_MASK_BB_SHIFT                                                  6
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_ECRCS8_MASK_BB                                                        (0x1<<7) // ECRC Error TLP Status Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_ECRCS8_MASK_BB_SHIFT                                                  7
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_URES8_MASK_BB                                                         (0x1<<8) // Unsupported Request Error Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_URES8_MASK_BB_SHIFT                                                   8
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_RXTABRT8_MASK_BB                                                      (0x1<<9) // Received target Abort Error Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_RXTABRT8_MASK_BB_SHIFT                                                9
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_PES9_MASK_BB                                                          (0x1<<10) // Poisoned Error Status Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_PES9_MASK_BB_SHIFT                                                    10
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_FCPES9_MASK_BB                                                        (0x1<<11) // Flow Control Protocol Error Status Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_FCPES9_MASK_BB_SHIFT                                                  11
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_CTS9_MASK_BB                                                          (0x1<<12) // Completer Timeout Status Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_CTS9_MASK_BB_SHIFT                                                    12
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_RX_UR9_MASK_BB                                                        (0x1<<13) // Received UR Status, Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_RX_UR9_MASK_BB_SHIFT                                                  13
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_UCS9_MASK_BB                                                          (0x1<<14) // Unexpected Completion Status Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_UCS9_MASK_BB_SHIFT                                                    14
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_ROS9_MASK_BB                                                          (0x1<<15) // Receiver Overflow Status Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_ROS9_MASK_BB_SHIFT                                                    15
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_MTLPS9_MASK_BB                                                        (0x1<<16) // Malformed TLP Status Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_MTLPS9_MASK_BB_SHIFT                                                  16
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_ECRCS9_MASK_BB                                                        (0x1<<17) // ECRC Error TLP Status Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_ECRCS9_MASK_BB_SHIFT                                                  17
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_URES9_MASK_BB                                                         (0x1<<18) // Unsupported Request Error Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_URES9_MASK_BB_SHIFT                                                   18
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_RXTABRT9_MASK_BB                                                      (0x1<<19) // Received target Abort Error Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_RXTABRT9_MASK_BB_SHIFT                                                19
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_PES10_MASK_BB                                                         (0x1<<20) // Poisoned Error Status Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_PES10_MASK_BB_SHIFT                                                   20
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_FCPES10_MASK_BB                                                       (0x1<<21) // Flow Control Protocol Error Status Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_FCPES10_MASK_BB_SHIFT                                                 21
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_CTS10_MASK_BB                                                         (0x1<<22) // Completer Timeout Status Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_CTS10_MASK_BB_SHIFT                                                   22
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_RX_UR10_MASK_BB                                                       (0x1<<23) // Received UR Status, Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_RX_UR10_MASK_BB_SHIFT                                                 23
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_UCS10_MASK_BB                                                         (0x1<<24) // Unexpected Completion Status Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_UCS10_MASK_BB_SHIFT                                                   24
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_ROS10_MASK_BB                                                         (0x1<<25) // Receiver Overflow Status Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_ROS10_MASK_BB_SHIFT                                                   25
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_MTLPS10_MASK_BB                                                       (0x1<<26) // Malformed TLP Status Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_MTLPS10_MASK_BB_SHIFT                                                 26
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_ECRCS10_MASK_BB                                                       (0x1<<27) // ECRC Error TLP Status Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_ECRCS10_MASK_BB_SHIFT                                                 27
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_URES10_MASK_BB                                                        (0x1<<28) // Unsupported Request Error Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_URES10_MASK_BB_SHIFT                                                  28
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_RXTABRT10_MASK_BB                                                     (0x1<<29) // Received target Abort Error Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_RXTABRT10_MASK_BB_SHIFT                                               29
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_UNUSED_1_BB                                                           (0x3<<30) // 
+  #define PCIEIP_REG_TL_FUNC8TO10_MASK_UNUSED_1_BB_SHIFT                                                     30
+#define PCIEIP_REG_TL_FUNC8TO10_STAT_BB                                                                      0x000884UL //Access:RW   DataWidth:0x20   // This register stores the status of errors to generate pcie_err_attn for functions 8, 9, and 10.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_PSND_TLP8_BB                                                      (0x1<<0) // Poisoned Error Status detected for Function 8. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_PSND_TLP8_BB_SHIFT                                                0
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_FC_PRTL8_BB                                                       (0x1<<1) // Flow Control Protocol Error Status detected for Function 8, if set, generate pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_FC_PRTL8_BB_SHIFT                                                 1
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_CPL_TIMEOUT8_BB                                                   (0x1<<2) // Completer Timeout Status detected for Function 8. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_CPL_TIMEOUT8_BB_SHIFT                                             2
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MASTER_ABRT8_BB                                                   (0x1<<3) // Receive UR Status detectedfor Function 8. If set, generate pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MASTER_ABRT8_BB_SHIFT                                             3
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNEXP_CPL8_BB                                                     (0x1<<4) // Unexpected Completion Status detected for Function 8, if set, generate pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNEXP_CPL8_BB_SHIFT                                               4
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_RX_OFLOW8_BB                                                      (0x1<<5) // Receiver Overflow Status detected for Function 8. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_RX_OFLOW8_BB_SHIFT                                                5
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MALF_TLP8_BB                                                      (0x1<<6) // Malformed TLP Status detected for Function 8. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MALF_TLP8_BB_SHIFT                                                6
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_ECRC8_BB                                                          (0x1<<7) // ECRC Error TLP Status detected for Function 8. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_ECRC8_BB_SHIFT                                                    7
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNSPPORT8_BB                                                      (0x1<<8) // Unsupported Request Error Status detected for Function 8. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNSPPORT8_BB_SHIFT                                                8
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_PRI_SIG_TARGET_ABORT8_BB                                              (0x1<<9) // 
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_PRI_SIG_TARGET_ABORT8_BB_SHIFT                                        9
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_PSND_TLP9_BB                                                      (0x1<<10) // Poisoned Error Status detected in function 9. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_PSND_TLP9_BB_SHIFT                                                10
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_FC_PRTL9_BB                                                       (0x1<<11) // Flow Control Protocol Error Status detected in function 9, if set, generate pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_FC_PRTL9_BB_SHIFT                                                 11
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_CPL_TIMEOUT9_BB                                                   (0x1<<12) // Completer Timeout Status detected in function 9. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_CPL_TIMEOUT9_BB_SHIFT                                             12
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MASTER_ABRT9_BB                                                   (0x1<<13) // Receive UR Status detectedin function 9. If set, generate pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MASTER_ABRT9_BB_SHIFT                                             13
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNEXP_CPL9_BB                                                     (0x1<<14) // Unexpected Completion Status detected in function 9, if set, generate pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNEXP_CPL9_BB_SHIFT                                               14
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_RX_OFLOW9_BB                                                      (0x1<<15) // Receiver Overflow Status detected in function 9. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_RX_OFLOW9_BB_SHIFT                                                15
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MALF_TLP9_BB                                                      (0x1<<16) // Malformed TLP Status detected in function 9. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MALF_TLP9_BB_SHIFT                                                16
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_ECRC9_BB                                                          (0x1<<17) // ECRC Error TLP Status detected in function 9. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_ECRC9_BB_SHIFT                                                    17
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNSPPORT9_BB                                                      (0x1<<18) // Unsupported Request Error Status detected in function9. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNSPPORT9_BB_SHIFT                                                18
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_PRI_SIG_TARGET_ABORT9_BB                                              (0x1<<19) // 
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_PRI_SIG_TARGET_ABORT9_BB_SHIFT                                        19
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_PSND_TLP10_BB                                                     (0x1<<20) // Poisoned Error Status detected in function 10. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_PSND_TLP10_BB_SHIFT                                               20
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_FC_PRTL10_BB                                                      (0x1<<21) // Flow Control Protocol Error Status detected in function 10, if set, generate pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_FC_PRTL10_BB_SHIFT                                                21
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_CPL_TIMEOUT10_BB                                                  (0x1<<22) // Completer Timeout Status detected in function 10. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_CPL_TIMEOUT10_BB_SHIFT                                            22
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MASTER_ABRT10_BB                                                  (0x1<<23) // Receive UR Status detectedin function 10. If set, generate pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MASTER_ABRT10_BB_SHIFT                                            23
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNEXP_CPL10_BB                                                    (0x1<<24) // Unexpected Completion Status detected in function 10, if set, generate pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNEXP_CPL10_BB_SHIFT                                              24
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_RX_OFLOW10_BB                                                     (0x1<<25) // Receiver Overflow Status detected in function 10. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_RX_OFLOW10_BB_SHIFT                                               25
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MALF_TLP10_BB                                                     (0x1<<26) // Malformed TLP Status detected in function 10. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MALF_TLP10_BB_SHIFT                                               26
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_ECRC10_BB                                                         (0x1<<27) // ECRC Error TLP Status detected in function 10. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_ECRC10_BB_SHIFT                                                   27
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNSPPORT10_BB                                                     (0x1<<28) // Unsupported Request Error Status detected in function10. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNSPPORT10_BB_SHIFT                                               28
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_PRI_SIG_TARGET_ABORT10_BB                                             (0x1<<29) // 
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_PRI_SIG_TARGET_ABORT10_BB_SHIFT                                       29
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_UNUSED_1_BB                                                           (0x3<<30) // 
+  #define PCIEIP_REG_TL_FUNC8TO10_STAT_UNUSED_1_BB_SHIFT                                                     30
+#define PCIEIP_REG_TL_FUNC11TO13_MASK_BB                                                                     0x000888UL //Access:RW   DataWidth:0x20   // This register masks specific errors from setting pcie_err_attn for functions 11, 12, and 13.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_PES11_MASK_BB                                                        (0x1<<0) // Poisoned Error Status Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_PES11_MASK_BB_SHIFT                                                  0
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_FCPES11_MASK_BB                                                      (0x1<<1) // Flow Control Protocol Error Status Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_FCPES11_MASK_BB_SHIFT                                                1
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_CTS11_MASK_BB                                                        (0x1<<2) // Completer Timeout Status Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_CTS11_MASK_BB_SHIFT                                                  2
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_RX_UR11_MASK_BB                                                      (0x1<<3) // Received UR Status, Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_RX_UR11_MASK_BB_SHIFT                                                3
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_UCS11_MASK_BB                                                        (0x1<<4) // Unexpected Completion Status Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_UCS11_MASK_BB_SHIFT                                                  4
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_ROS11_MASK_BB                                                        (0x1<<5) // Receiver Overflow Status Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_ROS11_MASK_BB_SHIFT                                                  5
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_MTLPS11_MASK_BB                                                      (0x1<<6) // Malformed TLP Status Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_MTLPS11_MASK_BB_SHIFT                                                6
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_ECRCS11_MASK_BB                                                      (0x1<<7) // ECRC Error TLP Status Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_ECRCS11_MASK_BB_SHIFT                                                7
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_URES11_MASK_BB                                                       (0x1<<8) // Unsupported Request Error Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_URES11_MASK_BB_SHIFT                                                 8
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_RXTABRT11_MASK_BB                                                    (0x1<<9) // Received target Abort Error Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_RXTABRT11_MASK_BB_SHIFT                                              9
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_PES12_MASK_BB                                                        (0x1<<10) // Poisoned Error Status Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_PES12_MASK_BB_SHIFT                                                  10
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_FCPES12_MASK_BB                                                      (0x1<<11) // Flow Control Protocol Error Status Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_FCPES12_MASK_BB_SHIFT                                                11
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_CTS12_MASK_BB                                                        (0x1<<12) // Completer Timeout Status Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_CTS12_MASK_BB_SHIFT                                                  12
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_RX_UR12_MASK_BB                                                      (0x1<<13) // Received UR Status, Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_RX_UR12_MASK_BB_SHIFT                                                13
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_UCS12_MASK_BB                                                        (0x1<<14) // Unexpected Completion Status Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_UCS12_MASK_BB_SHIFT                                                  14
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_ROS12_MASK_BB                                                        (0x1<<15) // Receiver Overflow Status Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_ROS12_MASK_BB_SHIFT                                                  15
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_MTLPS12_MASK_BB                                                      (0x1<<16) // Malformed TLP Status Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_MTLPS12_MASK_BB_SHIFT                                                16
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_ECRCS12_MASK_BB                                                      (0x1<<17) // ECRC Error TLP Status Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_ECRCS12_MASK_BB_SHIFT                                                17
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_URES12_MASK_BB                                                       (0x1<<18) // Unsupported Request Error Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_URES12_MASK_BB_SHIFT                                                 18
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_RXTABRT12_MASK_BB                                                    (0x1<<19) // Received target Abort Error Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_RXTABRT12_MASK_BB_SHIFT                                              19
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_PES13_MASK_BB                                                        (0x1<<20) // Poisoned Error Status Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_PES13_MASK_BB_SHIFT                                                  20
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_FCPES13_MASK_BB                                                      (0x1<<21) // Flow Control Protocol Error Status Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_FCPES13_MASK_BB_SHIFT                                                21
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_CTS13_MASK_BB                                                        (0x1<<22) // Completer Timeout Status Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_CTS13_MASK_BB_SHIFT                                                  22
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_RX_UR13_MASK_BB                                                      (0x1<<23) // Received UR Status, Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_RX_UR13_MASK_BB_SHIFT                                                23
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_UCS13_MASK_BB                                                        (0x1<<24) // Unexpected Completion Status Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_UCS13_MASK_BB_SHIFT                                                  24
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_ROS13_MASK_BB                                                        (0x1<<25) // Receiver Overflow Status Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_ROS13_MASK_BB_SHIFT                                                  25
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_MTLPS13_MASK_BB                                                      (0x1<<26) // Malformed TLP Status Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_MTLPS13_MASK_BB_SHIFT                                                26
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_ECRCS13_MASK_BB                                                      (0x1<<27) // ECRC Error TLP Status Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_ECRCS13_MASK_BB_SHIFT                                                27
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_URES13_MASK_BB                                                       (0x1<<28) // Unsupported Request Error Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_URES13_MASK_BB_SHIFT                                                 28
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_RXTABRT13_MASK_BB                                                    (0x1<<29) // Received target Abort Error Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_RXTABRT13_MASK_BB_SHIFT                                              29
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_UNUSED_1_BB                                                          (0x3<<30) // 
+  #define PCIEIP_REG_TL_FUNC11TO13_MASK_UNUSED_1_BB_SHIFT                                                    30
+#define PCIEIP_REG_TL_FUNC11TO13_STAT_BB                                                                     0x00088cUL //Access:RW   DataWidth:0x20   // This register stores the status of errors to generate pcie_err_attn for functions 11, 12, and 13.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_PSND_TLP11_BB                                                    (0x1<<0) // Poisoned Error Status detected for Function 11. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_PSND_TLP11_BB_SHIFT                                              0
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_FC_PRTL11_BB                                                     (0x1<<1) // Flow Control Protocol Error Status detected for Function 11. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_FC_PRTL11_BB_SHIFT                                               1
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_CPL_TIMEOUT11_BB                                                 (0x1<<2) // Completer Timeout Status detected for Function 11. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_CPL_TIMEOUT11_BB_SHIFT                                           2
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MASTER_ABRT11_BB                                                 (0x1<<3) // Receive UR Status detectedfor Function 11. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MASTER_ABRT11_BB_SHIFT                                           3
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNEXP_CPL11_BB                                                   (0x1<<4) // Unexpected Completion Status detected for Function 11. If set, hw generates, generate pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNEXP_CPL11_BB_SHIFT                                             4
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_RX_OFLOW11_BB                                                    (0x1<<5) // Receiver Overflow Status detected for Function 11. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_RX_OFLOW11_BB_SHIFT                                              5
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MALF_TLP11_BB                                                    (0x1<<6) // Malformed TLP Status detected for Function 11. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MALF_TLP11_BB_SHIFT                                              6
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_ECRC11_BB                                                        (0x1<<7) // ECRC Error TLP Status detected for Function 11. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_ECRC11_BB_SHIFT                                                  7
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNSPPORT11_BB                                                    (0x1<<8) // Unsupported Request Error Status detected for Function 11. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNSPPORT11_BB_SHIFT                                              8
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_PRI_SIG_TARGET_ABORT11_BB                                            (0x1<<9) // 
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_PRI_SIG_TARGET_ABORT11_BB_SHIFT                                      9
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_PSND_TLP12_BB                                                    (0x1<<10) // Poisoned Error Status detected in function 12. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_PSND_TLP12_BB_SHIFT                                              10
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_FC_PRTL12_BB                                                     (0x1<<11) // Flow Control Protocol Error Status detected in function 12. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_FC_PRTL12_BB_SHIFT                                               11
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_CPL_TIMEOUT12_BB                                                 (0x1<<12) // Completer Timeout Status detected in function 12. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_CPL_TIMEOUT12_BB_SHIFT                                           12
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MASTER_ABRT12_BB                                                 (0x1<<13) // Receive UR Status detectedin function 12. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MASTER_ABRT12_BB_SHIFT                                           13
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNEXP_CPL12_BB                                                   (0x1<<14) // Unexpected Completion Status detected in function 12. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNEXP_CPL12_BB_SHIFT                                             14
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_RX_OFLOW12_BB                                                    (0x1<<15) // Receiver Overflow Status detected in function 12. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_RX_OFLOW12_BB_SHIFT                                              15
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MALF_TLP12_BB                                                    (0x1<<16) // Malformed TLP Status detected in function 12. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MALF_TLP12_BB_SHIFT                                              16
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_ECRC12_BB                                                        (0x1<<17) // ECRC Error TLP Status detected in function 12. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_ECRC12_BB_SHIFT                                                  17
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNSPPORT12_BB                                                    (0x1<<18) // Unsupported Request Error Status detected in function12. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNSPPORT12_BB_SHIFT                                              18
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_PRI_SIG_TARGET_ABORT12_BB                                            (0x1<<19) // 
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_PRI_SIG_TARGET_ABORT12_BB_SHIFT                                      19
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_PSND_TLP13_BB                                                    (0x1<<20) // Poisoned Error Status detected in function 13. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_PSND_TLP13_BB_SHIFT                                              20
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_FC_PRTL13_BB                                                     (0x1<<21) // Flow Control Protocol Error Status detected in function 13. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_FC_PRTL13_BB_SHIFT                                               21
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_CPL_TIMEOUT13_BB                                                 (0x1<<22) // Completer Timeout Status detected in function 13. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_CPL_TIMEOUT13_BB_SHIFT                                           22
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MASTER_ABRT13_BB                                                 (0x1<<23) // Receive UR Status detectedin function 13. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MASTER_ABRT13_BB_SHIFT                                           23
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNEXP_CPL13_BB                                                   (0x1<<24) // Unexpected Completion Status detected in function 13. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNEXP_CPL13_BB_SHIFT                                             24
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_RX_OFLOW13_BB                                                    (0x1<<25) // Receiver Overflow Status detected in function 13. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_RX_OFLOW13_BB_SHIFT                                              25
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MALF_TLP13_BB                                                    (0x1<<26) // Malformed TLP Status detected in function 13. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MALF_TLP13_BB_SHIFT                                              26
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_ECRC13_BB                                                        (0x1<<27) // ECRC Error TLP Status detected in function 13. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_ECRC13_BB_SHIFT                                                  27
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNSPPORT13_BB                                                    (0x1<<28) // Unsupported Request Error Status detected in function13. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNSPPORT13_BB_SHIFT                                              28
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_PRI_SIG_TARGET_ABORT13_BB                                            (0x1<<29) // 
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_PRI_SIG_TARGET_ABORT13_BB_SHIFT                                      29
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_UNUSED_1_BB                                                          (0x3<<30) // 
+  #define PCIEIP_REG_TL_FUNC11TO13_STAT_UNUSED_1_BB_SHIFT                                                    30
+#define PCIEIP_REG_GEN3_RELATED_OFF_K2_E5                                                                    0x000890UL //Access:RW   DataWidth:0x20   // Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the "Link Width and Speed Change Control Register" is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific "Directed Speed Change" field. The "Directed Speed Change" field in the "Link Width and Speed Change Control Register" is used to change to Gen2 or Gen3 speed. A speed change to Gen3 occurs if (1) the "Directed Speed Change" field is set to "1" and (2) the "Target Link Speed" field in the Link Control 2 Register is set to Gen3. Gen3 support is advertised by both sides of the link during link training. M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist.
+  #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_K2_E5                                              (0x1<<0) // Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the following LTSSM states: Polling, Rx_L0s, L1, L2, and Disabled.  - 0: The receiver complies with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher.  - 1: The receiver does not comply with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher. Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rates.  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_K2_E5_SHIFT                                        0
+  #define PCIEIP_REG_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_K2_E5                                          (0x1<<8) // Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the core needs to be disabled when the scrambling function is implemented outside of the core (for example within the PHY).  Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate.  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_K2_E5_SHIFT                                    8
+  #define PCIEIP_REG_GEN3_RELATED_OFF_EQ_PHASE_2_3_K2_E5                                                     (0x1<<9) // Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only.  Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate.  Note: The access attributes of this field are as follows:  - Dbi: see description  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN3_RELATED_OFF_EQ_PHASE_2_3_K2_E5_SHIFT                                               9
+  #define PCIEIP_REG_GEN3_RELATED_OFF_EQ_EIEOS_CNT_K2_E5                                                     (0x1<<10) // Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization.  Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate.  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN3_RELATED_OFF_EQ_EIEOS_CNT_K2_E5_SHIFT                                               10
+  #define PCIEIP_REG_GEN3_RELATED_OFF_EQ_REDO_K2_E5                                                          (0x1<<11) // Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process.  Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate.  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN3_RELATED_OFF_EQ_REDO_K2_E5_SHIFT                                                    11
+  #define PCIEIP_REG_GEN3_RELATED_OFF_RXEQ_PH01_EN_K2_E5                                                     (0x1<<12) // Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be performed by the PHY. This bit is used during Virtex-7 Gen3 equalization. The programmable bits [RXEQ_PH01_EN, EQ_PHASE_2_3] can be used to obtain the following variations of the equalization procedure:  - 00: Tx equalization only in phase 2/3  - 01: No Tx equalization, no Rx equalization  - 10: Tx equalization in phase 2/3, Rx equalization in phase 0/1  - 11: No Tx equalization, Rx equalization in phase 0/1 Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate.  Note: The access attributes of this field are as follows:  - Dbi: see description  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN3_RELATED_OFF_RXEQ_PH01_EN_K2_E5_SHIFT                                               12
+  #define PCIEIP_REG_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_K2_E5                                               (0x1<<13) // When set to '1', the core as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request.  - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from remote partner.  - 1: mac_phy_rxeqeval asserts after 500ns regardless of TS's received or not. Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate.  Note: The access attributes of this field are as follows:  - Dbi: see description  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_K2_E5_SHIFT                                         13
+  #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_K2_E5                                        (0x1<<16) // Equalization Disable. Disable equalization feature.  Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate.  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_K2_E5_SHIFT                                  16
+  #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_K2_E5                                      (0x1<<17) // DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization.  Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate.  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_K2_E5_SHIFT                                17
+  #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_K2_E5                                          (0x1<<18) // DC Balance Disable. Disable DC Balance feature.  Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate.  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_K2_E5_SHIFT                                    18
+  #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_K2_E5                                 (0x1<<23) // Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time.  Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate.  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_K2_E5_SHIFT                           23
+#define PCIEIP_REG_TL_FUNC14TO15_MASK_BB                                                                     0x000890UL //Access:RW   DataWidth:0x20   // This register masks specific errors from setting pcie_err_attn for functions 14 and 15.
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_PES14_MASK_BB                                                        (0x1<<0) // Poisoned Error Status Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_PES14_MASK_BB_SHIFT                                                  0
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_FCPES14_MASK_BB                                                      (0x1<<1) // Flow Control Protocol Error Status Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_FCPES14_MASK_BB_SHIFT                                                1
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_CTS14_MASK_BB                                                        (0x1<<2) // Completer Timeout Status Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_CTS14_MASK_BB_SHIFT                                                  2
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_RX_UR14_MASK_BB                                                      (0x1<<3) // Received UR Status, Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_RX_UR14_MASK_BB_SHIFT                                                3
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_UCS14_MASK_BB                                                        (0x1<<4) // Unexpected Completion Status Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_UCS14_MASK_BB_SHIFT                                                  4
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_ROS14_MASK_BB                                                        (0x1<<5) // Receiver Overflow Status Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_ROS14_MASK_BB_SHIFT                                                  5
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_MTLPS14_MASK_BB                                                      (0x1<<6) // Malformed TLP Status Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_MTLPS14_MASK_BB_SHIFT                                                6
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_ECRCS14_MASK_BB                                                      (0x1<<7) // ECRC Error TLP Status Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_ECRCS14_MASK_BB_SHIFT                                                7
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_URES14_MASK_BB                                                       (0x1<<8) // Unsupported Request Error Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_URES14_MASK_BB_SHIFT                                                 8
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_RXTABRT14_MASK_BB                                                    (0x1<<9) // Received target Abort Error Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_RXTABRT14_MASK_BB_SHIFT                                              9
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_PES15_MASK_BB                                                        (0x1<<10) // Poisoned Error Status Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_PES15_MASK_BB_SHIFT                                                  10
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_FCPES15_MASK_BB                                                      (0x1<<11) // Flow Control Protocol Error Status Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_FCPES15_MASK_BB_SHIFT                                                11
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_CTS15_MASK_BB                                                        (0x1<<12) // Completer Timeout Status Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_CTS15_MASK_BB_SHIFT                                                  12
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_RX_UR15_MASK_BB                                                      (0x1<<13) // Received UR Status, Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_RX_UR15_MASK_BB_SHIFT                                                13
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_UCS15_MASK_BB                                                        (0x1<<14) // Unexpected Completion Status Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_UCS15_MASK_BB_SHIFT                                                  14
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_ROS15_MASK_BB                                                        (0x1<<15) // Receiver Overflow Status Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_ROS15_MASK_BB_SHIFT                                                  15
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_MTLPS15_MASK_BB                                                      (0x1<<16) // Malformed TLP Status Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_MTLPS15_MASK_BB_SHIFT                                                16
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_ECRCS15_MASK_BB                                                      (0x1<<17) // ECRC Error TLP Status Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_ECRCS15_MASK_BB_SHIFT                                                17
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_URES15_MASK_BB                                                       (0x1<<18) // Unsupported Request Error Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_URES15_MASK_BB_SHIFT                                                 18
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_RXTABRT15_MASK_BB                                                    (0x1<<19) // Received target Abort Error Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_RXTABRT15_MASK_BB_SHIFT                                              19
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_UNUSED_1_BB                                                          (0xfff<<20) // 
+  #define PCIEIP_REG_TL_FUNC14TO15_MASK_UNUSED_1_BB_SHIFT                                                    20
+#define PCIEIP_REG_TL_FUNC14TO15_STAT_BB                                                                     0x000894UL //Access:RW   DataWidth:0x20   // This register stores the status of errors to generate pcie_err_attn for functions 14 and 15.
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_PSND_TLP14_BB                                                    (0x1<<0) // Poisoned Error Status detected for Function 14. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_PSND_TLP14_BB_SHIFT                                              0
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_FC_PRTL14_BB                                                     (0x1<<1) // Flow Control Protocol Error Status detected for Function 14. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_FC_PRTL14_BB_SHIFT                                               1
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_CPL_TIMEOUT14_BB                                                 (0x1<<2) // Completer Timeout Status detected for Function 14. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_CPL_TIMEOUT14_BB_SHIFT                                           2
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_MASTER_ABRT14_BB                                                 (0x1<<3) // Receive UR Status detectedfor Function 14. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_MASTER_ABRT14_BB_SHIFT                                           3
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_UNEXP_CPL14_BB                                                   (0x1<<4) // Unexpected Completion Status detected for Function 14. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_UNEXP_CPL14_BB_SHIFT                                             4
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_RX_OFLOW14_BB                                                    (0x1<<5) // Receiver Overflow Status detected for Function 14. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_RX_OFLOW14_BB_SHIFT                                              5
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_MALF_TLP14_BB                                                    (0x1<<6) // Malformed TLP Status detected for Function 14. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_MALF_TLP14_BB_SHIFT                                              6
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_ECRC14_BB                                                        (0x1<<7) // ECRC Error TLP Status detected for Function 14. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_ECRC14_BB_SHIFT                                                  7
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_UNSPPORT14_BB                                                    (0x1<<8) // Unsupported Request Error Status detected for Function 14. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_UNSPPORT14_BB_SHIFT                                              8
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_PRI_SIG_TARGET_ABORT14_BB                                            (0x1<<9) // 
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_PRI_SIG_TARGET_ABORT14_BB_SHIFT                                      9
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_PSND_TLP15_BB                                                    (0x1<<10) // Poisoned Error Status detected in function 15. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_PSND_TLP15_BB_SHIFT                                              10
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_FC_PRTL15_BB                                                     (0x1<<11) // Flow Control Protocol Error Status detected in function 15. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_FC_PRTL15_BB_SHIFT                                               11
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_CPL_TIMEOUT15_BB                                                 (0x1<<12) // Completer Timeout Status detected in function 15. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_CPL_TIMEOUT15_BB_SHIFT                                           12
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_MASTER_ABRT15_BB                                                 (0x1<<13) // Receive UR Status detectedin function 15. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_MASTER_ABRT15_BB_SHIFT                                           13
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_UNEXP_CPL15_BB                                                   (0x1<<14) // Unexpected Completion Status detected in function 15. If set, hw geneartes pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_UNEXP_CPL15_BB_SHIFT                                             14
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_RX_OFLOW15_BB                                                    (0x1<<15) // Receiver Overflow Status detected in function 15. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_RX_OFLOW15_BB_SHIFT                                              15
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_MALF_TLP15_BB                                                    (0x1<<16) // Malformed TLP Status detected in function 15. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_MALF_TLP15_BB_SHIFT                                              16
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_ECRC15_BB                                                        (0x1<<17) // ECRC Error TLP Status detected in function 15. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_ECRC15_BB_SHIFT                                                  17
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_UNSPPORT15_BB                                                    (0x1<<18) // Unsupported Request Error Status detected in function15. If set, hw generates pcie_err_attn output.
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_UNSPPORT15_BB_SHIFT                                              18
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_PRI_SIG_TARGET_ABORT15_BB                                            (0x1<<19) // 
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_PRI_SIG_TARGET_ABORT15_BB_SHIFT                                      19
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_UNUSED_1_BB                                                          (0xfff<<20) // 
+  #define PCIEIP_REG_TL_FUNC14TO15_STAT_UNUSED_1_BB_SHIFT                                                    20
+#define PCIEIP_REG_PF_HIDE_CONTROL_K2_E5                                                                     0x0008a0UL //Access:RW   DataWidth:0x20   // The core supports the hiding of implemented physical functions. To enable this feature, you must set the CX_HIDE_PF_EN hidden configuration parameter.
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF0_HIDE_CONTROL_K2_E5                                                  (0x3<<0) // 0x00: PF is Visible, 0x01:Reserved, 0x10:PF is hidden. All CFG accesses to this function will receive UR. 0x11: PF is Partially Hidden. CfgWr accesses to this funciton will receive UR. CfgRd accesses to this function will receive SC, with a data payload of 0xFFFFFFFF.
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF0_HIDE_CONTROL_K2_E5_SHIFT                                            0
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF1_HIDE_CONTROL_K2_E5                                                  (0x3<<2) // Operates in the same way as PF0.
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF1_HIDE_CONTROL_K2_E5_SHIFT                                            2
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF2_HIDE_CONTROL_K2_E5                                                  (0x3<<4) // Operates in the same way as PF0.
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF2_HIDE_CONTROL_K2_E5_SHIFT                                            4
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF3_HIDE_CONTROL_K2_E5                                                  (0x3<<6) // Operates in the same way as PF0.
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF3_HIDE_CONTROL_K2_E5_SHIFT                                            6
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF4_HIDE_CONTROL_K2_E5                                                  (0x3<<8) // Operates in the same way as PF0.
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF4_HIDE_CONTROL_K2_E5_SHIFT                                            8
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF5_HIDE_CONTROL_K2_E5                                                  (0x3<<10) // Operates in the same way as PF0.
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF5_HIDE_CONTROL_K2_E5_SHIFT                                            10
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF6_HIDE_CONTROL_K2_E5                                                  (0x3<<12) // Operates in the same way as PF0.
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF6_HIDE_CONTROL_K2_E5_SHIFT                                            12
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF7_HIDE_CONTROL_K2_E5                                                  (0x3<<14) // Operates in the same way as PF0.
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF7_HIDE_CONTROL_K2_E5_SHIFT                                            14
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF8_HIDE_CONTROL_K2_E5                                                  (0x3<<16) // Operates in the same way as PF0.
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF8_HIDE_CONTROL_K2_E5_SHIFT                                            16
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF9_HIDE_CONTROL_K2_E5                                                  (0x3<<18) // Operates in the same way as PF0.
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF9_HIDE_CONTROL_K2_E5_SHIFT                                            18
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF10_HIDE_CONTROL_K2_E5                                                 (0x3<<20) // Operates in the same way as PF0.
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF10_HIDE_CONTROL_K2_E5_SHIFT                                           20
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF11_HIDE_CONTROL_K2_E5                                                 (0x3<<22) // Operates in the same way as PF0.
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF11_HIDE_CONTROL_K2_E5_SHIFT                                           22
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF12_HIDE_CONTROL_K2_E5                                                 (0x3<<24) // Operates in the same way as PF0.
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF12_HIDE_CONTROL_K2_E5_SHIFT                                           24
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF13_HIDE_CONTROL_K2_E5                                                 (0x3<<26) // Operates in the same way as PF0.
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF13_HIDE_CONTROL_K2_E5_SHIFT                                           26
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF14_HIDE_CONTROL_K2_E5                                                 (0x3<<28) // Operates in the same way as PF0.
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF14_HIDE_CONTROL_K2_E5_SHIFT                                           28
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF15_HIDE_CONTROL_K2_E5                                                 (0x3<<30) // Operates in the same way as PF0.
+  #define PCIEIP_REG_PF_HIDE_CONTROL_PF15_HIDE_CONTROL_K2_E5_SHIFT                                           30
+#define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_K2_E5                                                                 0x0008a8UL //Access:RW   DataWidth:0x20   // Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP), or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist.
+  #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_K2_E5                                               (0xf<<0) // Feedback Mode.  - 0000b: Direction Change  - 0001b: Figure Of Merit  - 0010b: Reserved  - .....: Reserved  - 1111b: Reserved Note: When CX_GEN4_SPEED, this register is a shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate.  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_K2_E5_SHIFT                                         0
+  #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_K2_E5                                     (0x1<<4) // Behavior After 24 ms Timeout (when optimal settings are not found).   For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout  - 0: Recovery.Speed  - 1: Recovery.Equalization.Phase3 When optimal settings are not found then:  - Equalization Phase 2 Successful status bit is not set in the "Link Status Register 2"  - Equalization Phase 2 Complete status bit is set in the "Link Status Register 2" For a DSP: Determine next LTSSM state from Phase3 after 24ms Timeout  - 0: Recovery.Speed  - 1: Recovery.Equalization.RcvrLock When optimal settings are not found then:  - Equalization Phase 3 Successful status bit is not set in the "Link Status Register 2"  - Equalization Phase 3 Complete status bit is set in the "Link Status Register 2" Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate.  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_K2_E5_SHIFT                               4
+  #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_K2_E5                                      (0x1<<5) // Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval:  - 0: abort the current evaluation, stop any attempt to modify the remote transmitter settings, Phase2 is terminated by the 24ms timeout  - 1: ignore the 2ms timeout and continue as normal. This is used to support PHYs that require more than 2ms to respond to the assertion of RxEqEval. Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate.  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_K2_E5_SHIFT                                5
+  #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_K2_E5                                          (0xffff<<8) // Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows:   Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase.   Bit [i] =1: "Preset=i" is requested and evaluated in EQ Master Phase.  - 0000000000000000: No preset be requested and evaluated in EQ Master Phase  - 000000xxxxxxxxx1: Preset 0 is requested and evaluated in EQ Master Phase  - 000000xxxxxxxx1x: Preset 1 is requested and evaluated in EQ Master Phase  - 000000xxxxxxx1xx: Preset 2 is requested and evaluated in EQ Master Phase  - 000000xxxxxx1xxx: Preset 3 is requested and evaluated in EQ Master Phase  - 000000xxxxx1xxxx: Preset 4 is requested and evaluated in EQ Master Phase  - 000000xxxx1xxxxx: Preset 5 is requested and evaluated in EQ Master Phase  - 000000xxx1xxxxxx: Preset 6 is requested and evaluated in EQ Master Phase  - 000000xx1xxxxxxx: Preset 7 is requested and evaluated in EQ Master Phase  - 000000x1xxxxxxxx: Preset 8 is requested and evaluated in EQ Master Phase  - 00000x1xxxxxxxxx: Preset 9 is requested and evaluated in EQ Master Phase  - 000001xxxxxxxxxx: Preset 10 is requested and evaluated in EQ Master Phase  - All other encodings: Reserved Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate.  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_K2_E5_SHIFT                                    8
+  #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_K2_E5                                  (0x1<<24) // Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master, when finding the highest FOM among all preset evaluations.  - 0: Do not include  - 1: Include Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate.  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_K2_E5_SHIFT                            24
+  #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_K2_E5                                      (0x1<<25) // GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use.  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_K2_E5_SHIFT                                25
+  #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_K2_E5                       (0x1<<26) // Request core to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete.  - 0: Do not request  - 1: request Note: Gen3 and Gen4 share the same register bit and have the same feature.  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_K2_E5_SHIFT                 26
+#define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_K2_E5                                                      0x0008acUL //Access:RW   DataWidth:0x20   // Gen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP), when you set the Feedback Mode in "Gen3 EQ Control Register" to "Direction Change." These fields allow control over the initial starting point for the search of optimal coefficient settings, and allow control over the criteria used to determine when the optimal settings have been achieved. The values are applied to all the lanes.
+  #define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_K2_E5                         (0x1f<<0) // Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time, before starting to check for convergence of the coefficients. Allowed values 0,1,...,24.  Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate.  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_K2_E5_SHIFT                   0
+  #define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_K2_E5                               (0x1f<<5) // Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found. Allowed range: 0,1,2,..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH.  When set to 0, EQ Master is performed without sending any requests to the remote partner in Phase 2 for USP and Phase 3 for DSP. Therefore, the remote partner will not change its transmitter coefficients and will move to the next state.  Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate.  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_K2_E5_SHIFT                         5
+  #define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_K2_E5                  (0xf<<10) // Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0,1,2,..15.  Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate.  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_K2_E5_SHIFT            10
+  #define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_K2_E5                 (0xf<<14) // Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0,1,2,..15.  Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate.  Note: This register field is sticky.
+  #define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_K2_E5_SHIFT           14
+#define PCIEIP_REG_ORDER_RULE_CTRL_OFF_K2_E5                                                                 0x0008b4UL //Access:RW   DataWidth:0x20   // Order Rule Control Register.
+  #define PCIEIP_REG_ORDER_RULE_CTRL_OFF_NP_PASS_P_K2_E5                                                     (0xff<<0) // Non-Posted Passing Posted Ordering Rule Control.   Determines if NP can pass halted P queue.  - 0 : NP can not pass P (recommended).  - 1 : NP can pass P
+  #define PCIEIP_REG_ORDER_RULE_CTRL_OFF_NP_PASS_P_K2_E5_SHIFT                                               0
+  #define PCIEIP_REG_ORDER_RULE_CTRL_OFF_CPL_PASS_P_K2_E5                                                    (0xff<<8) // Completion Passing Posted Ordering Rule Control.   Determines if CPL can pass halted P queue.  - 0: CPL can not pass P (recommended)  - 1: CPL can pass P
+  #define PCIEIP_REG_ORDER_RULE_CTRL_OFF_CPL_PASS_P_K2_E5_SHIFT                                              8
+#define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_K2_E5                                                           0x0008b8UL //Access:RW   DataWidth:0x20   // PIPE Loopback Control Register.
+  #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_K2_E5                                            (0xffff<<0) // LPBK_RXVALID is an internally reserved field. Do not use.  Note: This register field is sticky.
+  #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_K2_E5_SHIFT                                      0
+  #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_K2_E5                                           (0x3f<<16) // RXSTATUS_LANE is an internally reserved field. Do not use.  Note: This register field is sticky.
+  #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_K2_E5_SHIFT                                     16
+  #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_K2_E5                                          (0x7<<24) // RXSTATUS_VALUE is an internally reserved field. Do not use.
+  #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_K2_E5_SHIFT                                    24
+  #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_K2_E5                                           (0x1<<31) // PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe.  Note: This register field is sticky.
+  #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_K2_E5_SHIFT                                     31
+#define PCIEIP_REG_MISC_CONTROL_1_OFF_K2_E5                                                                  0x0008bcUL //Access:RW   DataWidth:0x20   // DBI Read-Only Write Enable Register.
+  #define PCIEIP_REG_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_K2_E5                                                   (0x1<<0) // Write to RO Registers Using DBI. When you set this field to "1", then some RO and HwInit bits are writable from the local application through the DBI. For more details, see "Writing to Read-Only Registers."  Note: This register field is sticky.
+  #define PCIEIP_REG_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_K2_E5_SHIFT                                             0
+#define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_K2_E5                                                              0x0008c0UL //Access:RW   DataWidth:0x20   // UpConfigure Multi-lane Control Register.  Used when upsizing or downsizing the link width through Configuration state without bringing the link down. For more details, see the "Link Establishment" section in the Core Operations chapter of the Databook.
+  #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_K2_E5                                          (0x3f<<0) // Target Link Width.  Values correspond to:  - 6'b000000: Core does not start upconfigure or autonomous width downsizing in the Configuration state.  - 6'b000001: x1  - 6'b000010: x2  - 6'b000100: x4  - 6'b001000: x8  - 6'b010000: x16  - 6'b100000: x32 This field is reserved (fixed to '0') for M-PCIe.
+  #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_K2_E5_SHIFT                                    0
+  #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_K2_E5                                   (0x1<<6) // Directed Link Width Change.  The core always moves to Configuration state through Recovery state when this bit is set to '1'.  - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in LINK_CONTROL_LINK_STATUS_REG is '0', the core starts upconfigure or autonomous width downsizing (to the TARGET_LINK_WIDTH value) in the Configuration state.  - If TARGET_LINK_WIDTH value is 0x0, the core does not start upconfigure or autonomous width downsizing in the Configuration state. The core self-clears this field when the core accepts this request.  This field is reserved (fixed to '0') for M-PCIe.
+  #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_K2_E5_SHIFT                             6
+  #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_K2_E5                                        (0x1<<7) // Upconfigure Support.  The core sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state.  This field is reserved (fixed to '0') for M-PCIe.  Note: This register field is sticky.
+  #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_K2_E5_SHIFT                                  7
+#define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_K2_E5                                                                0x0008c4UL //Access:RW   DataWidth:0x20   // PHY Interoperability Control Register.   This register is reserved for internal use.  You should not write to this register and change the default unless specifically instructed by Synopsys support.
+  #define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_K2_E5                                            (0x7f<<0) // Rxstandby Control. Bits 0..5 determine if the core asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake.  - [0]: Rx EIOS and subsequent T TX-IDLE-MIN  - [1]: Rate Change  - [2]: Inactive lane for upconfigure/downconfigure  - [3]: PowerDown=P1orP2  - [4]: RxL0s.Idle  - [5]: EI Infer in L0  - [6]: Execute RxStandby/RxStandbyStatus Handshake This field is reserved (fixed to '0') for M-PCIe.  Note: This register field is sticky.
+  #define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_K2_E5_SHIFT                                      0
+  #define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_K2_E5                                                 (0x1<<9) // L1 entry control bit.  - 1: Core does not wait for PHY to acknowledge transition to P1 before entering L1.  - 0: Core waits for the PHY to acknowledge transition to P1 before entering L1. Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
+  #define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_K2_E5_SHIFT                                           9
+#define PCIEIP_REG_TRGT_CPL_LUT_DELETE_ENTRY_OFF_K2_E5                                                       0x0008c8UL //Access:RW   DataWidth:0x20   // TRGT_CPL_LUT Delete Entry Control register.   Using this register you can delete one entry in the target completion LUT.  Note:: The target completion LUT (and associated target completion timeout event) is watching for received application completions (on XALI0/1/2) corresponding to previously received non-posted requests from the PCIe wire.
+  #define PCIEIP_REG_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_K2_E5                                          (0x7fffffff<<0) // This number selects one entry to delete of the TRGT_CPL_LUT.
+  #define PCIEIP_REG_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_K2_E5_SHIFT                                    0
+  #define PCIEIP_REG_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_K2_E5                                           (0x1<<31) // This is a one shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'.
+  #define PCIEIP_REG_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_K2_E5_SHIFT                                     31
+#define PCIEIP_REG_PL_LAST_OFF_K2_E5                                                                         0x0008fcUL //Access:R    DataWidth:0x20   // PL_LAST_OFF is an internally reserved register. Do not use.
+  #define PCIEIP_REG_PL_LAST_OFF_PL_LAST_K2_E5                                                               (0x1<<0) // PL_LAST is an internally reserved field. Do not use.
+  #define PCIEIP_REG_PL_LAST_OFF_PL_LAST_K2_E5_SHIFT                                                         0
+#define PCIEIP_REG_TL_STATUS_0_BB                                                                            0x000900UL //Access:R    DataWidth:0x20   // Split completion table entry. For Debug.
+  #define PCIEIP_REG_TL_STATUS_0_DEVICE_NO_BB                                                                (0xf<<0) // Split table contents for tag0. this corresponds to Device_no[4:1] of PCIE header.
+  #define PCIEIP_REG_TL_STATUS_0_DEVICE_NO_BB_SHIFT                                                          0
+  #define PCIEIP_REG_TL_STATUS_0_FUNC_NO_BB                                                                  (0x7<<4) // Split table contents for tag0. This is the Function number of the request made.
+  #define PCIEIP_REG_TL_STATUS_0_FUNC_NO_BB_SHIFT                                                            4
+  #define PCIEIP_REG_TL_STATUS_0_TC_BB                                                                       (0x7<<7) // Split table contents for tag0. This is the Traffic class field.
+  #define PCIEIP_REG_TL_STATUS_0_TC_BB_SHIFT                                                                 7
+  #define PCIEIP_REG_TL_STATUS_0_ATTR_BB                                                                     (0x3<<10) // Split table Contents for tag0. This corresponds to attr field in PCIE header.
+  #define PCIEIP_REG_TL_STATUS_0_ATTR_BB_SHIFT                                                               10
+  #define PCIEIP_REG_TL_STATUS_0_BYTE_COUNT_BB                                                               (0x1fff<<12) // Split table contents for tag0. This corresponds to the Byte count field.
+  #define PCIEIP_REG_TL_STATUS_0_BYTE_COUNT_BB_SHIFT                                                         12
+  #define PCIEIP_REG_TL_STATUS_0_LWR_ADDR_BB                                                                 (0x7f<<25) // Split table contents for tag0. This corresponds to the Lower address field.
+  #define PCIEIP_REG_TL_STATUS_0_LWR_ADDR_BB_SHIFT                                                           25
+#define PCIEIP_REG_TL_STATUS_1_BB                                                                            0x000904UL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 01.
+#define PCIEIP_REG_TL_STATUS_2_BB                                                                            0x000908UL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 02.
+#define PCIEIP_REG_TL_STATUS_3_BB                                                                            0x00090cUL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 03.
+#define PCIEIP_REG_TL_STATUS_4_BB                                                                            0x000910UL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 04.
+#define PCIEIP_REG_TL_STATUS_5_BB                                                                            0x000914UL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 05.
+#define PCIEIP_REG_TL_STATUS_6_BB                                                                            0x000918UL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 06.
+#define PCIEIP_REG_TL_STATUS_7_BB                                                                            0x00091cUL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 07.
+#define PCIEIP_REG_TL_STATUS_8_BB                                                                            0x000920UL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 08.
+#define PCIEIP_REG_TL_STATUS_9_BB                                                                            0x000924UL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 09.
+#define PCIEIP_REG_TL_STATUS_10_BB                                                                           0x000928UL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 10.
+#define PCIEIP_REG_TL_STATUS_11_BB                                                                           0x00092cUL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 11.
+#define PCIEIP_REG_TL_STATUS_12_BB                                                                           0x000930UL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 12.
+#define PCIEIP_REG_TL_STATUS_13_BB                                                                           0x000934UL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 13.
+#define PCIEIP_REG_TL_STATUS_14_BB                                                                           0x000938UL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 14.
+#define PCIEIP_REG_TL_STATUS_15_BB                                                                           0x00093cUL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 15.
+#define PCIEIP_REG_TL_STATUS_16_BB                                                                           0x000940UL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 16.
+#define PCIEIP_REG_TL_STATUS_17_BB                                                                           0x000944UL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 17.
+#define PCIEIP_REG_TL_STATUS_18_BB                                                                           0x000948UL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 18.
+#define PCIEIP_REG_TL_STATUS_19_BB                                                                           0x00094cUL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 19.
+#define PCIEIP_REG_TL_STATUS_20_BB                                                                           0x000950UL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 20.
+#define PCIEIP_REG_TL_STATUS_21_BB                                                                           0x000954UL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 21.
+#define PCIEIP_REG_TL_STATUS_22_BB                                                                           0x000958UL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 22.
+#define PCIEIP_REG_TL_STATUS_23_BB                                                                           0x00095cUL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 23.
+#define PCIEIP_REG_TL_STATUS_24_BB                                                                           0x000960UL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 24.
+#define PCIEIP_REG_TL_STATUS_25_BB                                                                           0x000964UL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 25.
+#define PCIEIP_REG_TL_STATUS_26_BB                                                                           0x000968UL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 26.
+#define PCIEIP_REG_TL_STATUS_27_BB                                                                           0x00096cUL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 27.
+#define PCIEIP_REG_TL_STATUS_28_BB                                                                           0x000970UL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 28.
+#define PCIEIP_REG_TL_STATUS_29_BB                                                                           0x000974UL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 29.
+#define PCIEIP_REG_TL_STATUS_30_BB                                                                           0x000978UL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 30.
+#define PCIEIP_REG_TL_STATUS_31_BB                                                                           0x00097cUL //Access:R    DataWidth:0x20   // This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 31.
+#define PCIEIP_REG_TL_HDR_FC_ST_BB                                                                           0x000980UL //Access:R    DataWidth:0x20   // Header Flow Control. For Debug.
+  #define PCIEIP_REG_TL_HDR_FC_ST_NPH_AVAIL_BB                                                               (0xff<<0) // Non Posted Header credits available.
+  #define PCIEIP_REG_TL_HDR_FC_ST_NPH_AVAIL_BB_SHIFT                                                         0
+  #define PCIEIP_REG_TL_HDR_FC_ST_PH_AVAIL_BB                                                                (0xff<<8) // Posted Header Credits Available.
+  #define PCIEIP_REG_TL_HDR_FC_ST_PH_AVAIL_BB_SHIFT                                                          8
+  #define PCIEIP_REG_TL_HDR_FC_ST_CPLH_AVAIL_BB                                                              (0xff<<16) // Completion Header credits available.
+  #define PCIEIP_REG_TL_HDR_FC_ST_CPLH_AVAIL_BB_SHIFT                                                        16
+  #define PCIEIP_REG_TL_HDR_FC_ST_NPD_AVAIL_7_0_BB                                                           (0xff<<24) // Non-Posted Data credits available: bit[7:0].
+  #define PCIEIP_REG_TL_HDR_FC_ST_NPD_AVAIL_7_0_BB_SHIFT                                                     24
+#define PCIEIP_REG_TL_DAT_FC_ST_BB                                                                           0x000984UL //Access:R    DataWidth:0x20   // Data Flow Control. For Debug.
+  #define PCIEIP_REG_TL_DAT_FC_ST_PD_AVAIL_BB                                                                (0xfff<<0) // Posted Data credits available.
+  #define PCIEIP_REG_TL_DAT_FC_ST_PD_AVAIL_BB_SHIFT                                                          0
+  #define PCIEIP_REG_TL_DAT_FC_ST_UNUSED0_BB                                                                 (0xf<<12) // 
+  #define PCIEIP_REG_TL_DAT_FC_ST_UNUSED0_BB_SHIFT                                                           12
+  #define PCIEIP_REG_TL_DAT_FC_ST_CPLD_AVAIL_BB                                                              (0xfff<<16) // Completion Data credits available.
+  #define PCIEIP_REG_TL_DAT_FC_ST_CPLD_AVAIL_BB_SHIFT                                                        16
+  #define PCIEIP_REG_TL_DAT_FC_ST_NPD_AVAIL_11_8_BB                                                          (0xf<<28) // Non-Posted Data credits available: bit[11:8].
+  #define PCIEIP_REG_TL_DAT_FC_ST_NPD_AVAIL_11_8_BB_SHIFT                                                    28
+#define PCIEIP_REG_TL_HDR_FCCON_ST_BB                                                                        0x000988UL //Access:R    DataWidth:0x20   // Header Flow Control. For Debug.
+  #define PCIEIP_REG_TL_HDR_FCCON_ST_NPH_CC_BB                                                               (0xff<<0) // Non Posted Header credits consumed.
+  #define PCIEIP_REG_TL_HDR_FCCON_ST_NPH_CC_BB_SHIFT                                                         0
+  #define PCIEIP_REG_TL_HDR_FCCON_ST_PH_CC_BB                                                                (0xff<<8) // Posted Header Credits consumed.
+  #define PCIEIP_REG_TL_HDR_FCCON_ST_PH_CC_BB_SHIFT                                                          8
+  #define PCIEIP_REG_TL_HDR_FCCON_ST_CPLH_CC_BB                                                              (0xff<<16) // Completion Header credits consumed.
+  #define PCIEIP_REG_TL_HDR_FCCON_ST_CPLH_CC_BB_SHIFT                                                        16
+  #define PCIEIP_REG_TL_HDR_FCCON_ST_NPD_CC_7_0_BB                                                           (0xff<<24) // Non-Posted Data credits consumed: bit[7:0].
+  #define PCIEIP_REG_TL_HDR_FCCON_ST_NPD_CC_7_0_BB_SHIFT                                                     24
+#define PCIEIP_REG_TL_DAT_FCCON_ST_BB                                                                        0x00098cUL //Access:R    DataWidth:0x20   // Data Flow Control. For Debug.
+  #define PCIEIP_REG_TL_DAT_FCCON_ST_PD_CC_BB                                                                (0xfff<<0) // Posted Data credits consumed.
+  #define PCIEIP_REG_TL_DAT_FCCON_ST_PD_CC_BB_SHIFT                                                          0
+  #define PCIEIP_REG_TL_DAT_FCCON_ST_UNUSED0_BB                                                              (0xf<<12) // 
+  #define PCIEIP_REG_TL_DAT_FCCON_ST_UNUSED0_BB_SHIFT                                                        12
+  #define PCIEIP_REG_TL_DAT_FCCON_ST_CPLD_CC_BB                                                              (0xfff<<16) // Completion Data credits consumed.
+  #define PCIEIP_REG_TL_DAT_FCCON_ST_CPLD_CC_BB_SHIFT                                                        16
+  #define PCIEIP_REG_TL_DAT_FCCON_ST_NPD_CC_11_8_BB                                                          (0xf<<28) // Non-Posted Data credits consumed: bit[11:8].
+  #define PCIEIP_REG_TL_DAT_FCCON_ST_NPD_CC_11_8_BB_SHIFT                                                    28
+#define PCIEIP_REG_TL_TGT_CRDT_ST_BB                                                                         0x000990UL //Access:R    DataWidth:0x20   // Target Flow Control. For Debug.
+  #define PCIEIP_REG_TL_TGT_CRDT_ST_PH_CRDT_CNTR_BB                                                          (0x7f<<0) // Available Posted header credits for target writes.
+  #define PCIEIP_REG_TL_TGT_CRDT_ST_PH_CRDT_CNTR_BB_SHIFT                                                    0
+  #define PCIEIP_REG_TL_TGT_CRDT_ST_UNUSED0_BB                                                               (0x1<<7) // 
+  #define PCIEIP_REG_TL_TGT_CRDT_ST_UNUSED0_BB_SHIFT                                                         7
+  #define PCIEIP_REG_TL_TGT_CRDT_ST_PD_CRDT_CNTR_BB                                                          (0x7f<<8) // Available Posted data credits for target writes.
+  #define PCIEIP_REG_TL_TGT_CRDT_ST_PD_CRDT_CNTR_BB_SHIFT                                                    8
+  #define PCIEIP_REG_TL_TGT_CRDT_ST_UNUSED1_BB                                                               (0x1<<15) // 
+  #define PCIEIP_REG_TL_TGT_CRDT_ST_UNUSED1_BB_SHIFT                                                         15
+  #define PCIEIP_REG_TL_TGT_CRDT_ST_NP_CRDT_CNTR_BB                                                          (0x1<<16) // Available Non-posted credit for target reads or config.
+  #define PCIEIP_REG_TL_TGT_CRDT_ST_NP_CRDT_CNTR_BB_SHIFT                                                    16
+#define PCIEIP_REG_TL_CRDT_ALLOC_ST_BB                                                                       0x000994UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_TL_CRDT_ALLOC_ST_NPH_ALLOC_BB                                                           (0xff<<0) // Non-Posted header credits allocated.
+  #define PCIEIP_REG_TL_CRDT_ALLOC_ST_NPH_ALLOC_BB_SHIFT                                                     0
+  #define PCIEIP_REG_TL_CRDT_ALLOC_ST_NPD_ALLOC_BB                                                           (0xff<<8) // Non-Posted data credits allocated.
+  #define PCIEIP_REG_TL_CRDT_ALLOC_ST_NPD_ALLOC_BB_SHIFT                                                     8
+  #define PCIEIP_REG_TL_CRDT_ALLOC_ST_PH_ALLOC_BB                                                            (0xff<<16) // Posted header credits allocated.
+  #define PCIEIP_REG_TL_CRDT_ALLOC_ST_PH_ALLOC_BB_SHIFT                                                      16
+  #define PCIEIP_REG_TL_CRDT_ALLOC_ST_PD_ALLOC_BB                                                            (0xff<<24) // Posted Data credits allocated.
+  #define PCIEIP_REG_TL_CRDT_ALLOC_ST_PD_ALLOC_BB_SHIFT                                                      24
+#define PCIEIP_REG_TL_SMLOGIC_ST_BB                                                                          0x000998UL //Access:R    DataWidth:0x20   // State machines in TL status for debug.
+  #define PCIEIP_REG_TL_SMLOGIC_ST_NP_CURR_STATE_BB                                                          (0xf<<0) // Target Non-Posted request State machine.
+  #define PCIEIP_REG_TL_SMLOGIC_ST_NP_CURR_STATE_BB_SHIFT                                                    0
+  #define PCIEIP_REG_TL_SMLOGIC_ST_PH_CURR_STATE_BB                                                          (0xf<<4) // Target posted request state machine.
+  #define PCIEIP_REG_TL_SMLOGIC_ST_PH_CURR_STATE_BB_SHIFT                                                    4
+  #define PCIEIP_REG_TL_SMLOGIC_ST_CPL_CURR_STATE_BB                                                         (0x3<<8) // CPL_CURR_STATE Read Completions State machine.
+  #define PCIEIP_REG_TL_SMLOGIC_ST_CPL_CURR_STATE_BB_SHIFT                                                   8
+  #define PCIEIP_REG_TL_SMLOGIC_ST_UNUSED0_BB                                                                (0x3f<<10) // 
+  #define PCIEIP_REG_TL_SMLOGIC_ST_UNUSED0_BB_SHIFT                                                          10
+  #define PCIEIP_REG_TL_SMLOGIC_ST_TX_SM_BB                                                                  (0x7<<16) // Transmit State machine.
+  #define PCIEIP_REG_TL_SMLOGIC_ST_TX_SM_BB_SHIFT                                                            16
+#define PCIEIP_REG_TL_PM_DEBUG_BB                                                                            0x00099cUL //Access:R    DataWidth:0x20   // Different OBFF Related Debug Signals.
+#define PCIEIP_REG_TL_RST_DEBUG_BB                                                                           0x0009a0UL //Access:R    DataWidth:0x20   // Different Reset Related Debug Signals.
+  #define PCIEIP_REG_TL_RST_DEBUG_AUX_DBG_SIGS_0_BB                                                          (0x7ff<<0) // 
+  #define PCIEIP_REG_TL_RST_DEBUG_AUX_DBG_SIGS_0_BB_SHIFT                                                    0
+  #define PCIEIP_REG_TL_RST_DEBUG_PCIE_LNK_PHY_RESET_MDIO_N_BB                                               (0x1<<11) // 
+  #define PCIEIP_REG_TL_RST_DEBUG_PCIE_LNK_PHY_RESET_MDIO_N_BB_SHIFT                                         11
+  #define PCIEIP_REG_TL_RST_DEBUG_PCIE_LNK_PHY_RESET_UC_N_BB                                                 (0x1<<12) // 
+  #define PCIEIP_REG_TL_RST_DEBUG_PCIE_LNK_PHY_RESET_UC_N_BB_SHIFT                                           12
+  #define PCIEIP_REG_TL_RST_DEBUG_HARD_RST_CFG_B_BB                                                          (0x1<<13) // 
+  #define PCIEIP_REG_TL_RST_DEBUG_HARD_RST_CFG_B_BB_SHIFT                                                    13
+  #define PCIEIP_REG_TL_RST_DEBUG_PERST_CFG_B_BB                                                             (0x1<<14) // 
+  #define PCIEIP_REG_TL_RST_DEBUG_PERST_CFG_B_BB_SHIFT                                                       14
+  #define PCIEIP_REG_TL_RST_DEBUG_RESERVED_BB                                                                (0x1<<15) // 
+  #define PCIEIP_REG_TL_RST_DEBUG_RESERVED_BB_SHIFT                                                          15
+  #define PCIEIP_REG_TL_RST_DEBUG_AUX_DBG_SIGS_1_BB                                                          (0x7ff<<16) // 
+  #define PCIEIP_REG_TL_RST_DEBUG_AUX_DBG_SIGS_1_BB_SHIFT                                                    16
+  #define PCIEIP_REG_TL_RST_DEBUG_RESERVED_1_BB                                                              (0x1f<<27) // 
+  #define PCIEIP_REG_TL_RST_DEBUG_RESERVED_1_BB_SHIFT                                                        27
+#define PCIEIP_REG_TL_IOV_VFCTL_0_BB                                                                         0x000a04UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_TL_IOV_VFCTL_0_VF_NEXTBUS_BB                                                            (0x1<<0) // This bit when set enables the DUT to assume that VFs are residing on a bus number that is different than the one on which the PFs reside. When this bit is enabled, VF_offset is automatically set to be greater than 256. So VFs reside on the next bus number and PCIE IP will consume multiple bus numbers. In this case VFs are accessed using Cfg Type 1 Transactions. This bit should be set if ARI is not supported in the hierarchy.
+  #define PCIEIP_REG_TL_IOV_VFCTL_0_VF_NEXTBUS_BB_SHIFT                                                      0
+  #define PCIEIP_REG_TL_IOV_VFCTL_0_VF_OFFSET_VETO_BB                                                        (0x1<<1) // This bit when set, prevents DUT from automatically setting VF offset to be greater than 256(when vf_nextbus, bit 0 is set). User would have to set the offset bit on their own in this case.
+  #define PCIEIP_REG_TL_IOV_VFCTL_0_VF_OFFSET_VETO_BB_SHIFT                                                  1
+  #define PCIEIP_REG_TL_IOV_VFCTL_0_VF_EN_BAR_ADJUST_BB                                                      (0x1<<2) // This bit when set, enables DUT to automatically adjust the VF BAR size based on the System Page Size programming. When system Page size is programmed to be greater than User Page Size, DUT will change the VF BAR size advertized to be the new Effective system Page Size.
+  #define PCIEIP_REG_TL_IOV_VFCTL_0_VF_EN_BAR_ADJUST_BB_SHIFT                                                2
+#define PCIEIP_REG_TL_FCIMM_NP_LIMIT_BB                                                                      0x000a10UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_TL_FCIMM_NP_LIMIT_REG_FC_NPD_IMM_LIMIT_BB                                               (0xfff<<0) // The number of accumulated non-posted data credits since the last request for immediate update that are needed to force an immediate update. The default is 0 since infinite non-posted data credits are advertised.
+  #define PCIEIP_REG_TL_FCIMM_NP_LIMIT_REG_FC_NPD_IMM_LIMIT_BB_SHIFT                                         0
+  #define PCIEIP_REG_TL_FCIMM_NP_LIMIT_REG_FC_NPH_IMM_LIMIT_BB                                               (0xff<<12) // The number of accumulated non-posted header credits since the last request for immediate update that are needed to force an immediate update. The default is (NPH_INIT_CREDIT &gt;&gt; 1). A value of 0 means always force an update (if infinite credits are not advertised).
+  #define PCIEIP_REG_TL_FCIMM_NP_LIMIT_REG_FC_NPH_IMM_LIMIT_BB_SHIFT                                         12
+  #define PCIEIP_REG_TL_FCIMM_NP_LIMIT_REG_ENA_FC_NP_IMMEDIATE_BB                                            (0x1<<20) // When set, released non-posted credits are flagged for immediate update. When clear, the credits may or not be updated until one or more of the accumulated credit thresholds for non-posted header or non-posted data is reached. (If clear and infinite credits are advertised, the thresholds are not used to force immediate updates.)
+  #define PCIEIP_REG_TL_FCIMM_NP_LIMIT_REG_ENA_FC_NP_IMMEDIATE_BB_SHIFT                                      20
+  #define PCIEIP_REG_TL_FCIMM_NP_LIMIT_REG_FC_NP_USCNT_BB                                                    (0xf<<21) // The number of microseconds between the last update and the forced update if there are outstanding non-posted credits to update. The resolution on the timer is +/- 1 us.
+  #define PCIEIP_REG_TL_FCIMM_NP_LIMIT_REG_FC_NP_USCNT_BB_SHIFT                                              21
+  #define PCIEIP_REG_TL_FCIMM_NP_LIMIT_REG_ENA_FC_NP_UPD_10US_BB                                             (0x1<<25) // When set, outstanding non-posted credit updates are forwarded to the DLL as immediate updates after a given number of microseconds (see below) elapses since the last update. This is typically used with non-immediate (threshold-based) updates.
+  #define PCIEIP_REG_TL_FCIMM_NP_LIMIT_REG_ENA_FC_NP_UPD_10US_BB_SHIFT                                       25
+#define PCIEIP_REG_TL_FCIMM_P_LIMIT_BB                                                                       0x000a14UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_TL_FCIMM_P_LIMIT_REG_FC_PD_IMM_LIMIT_BB                                                 (0xfff<<0) // The number of accumulated posted data credits since the last request for immediate update that are needed to force an immediate update. The default is (PD_INIT_CREDIT &gt;&gt; 1). A value of 0 means always force an update (if infinite credits are not advertised).
+  #define PCIEIP_REG_TL_FCIMM_P_LIMIT_REG_FC_PD_IMM_LIMIT_BB_SHIFT                                           0
+  #define PCIEIP_REG_TL_FCIMM_P_LIMIT_REG_FC_PH_IMM_LIMIT_BB                                                 (0xff<<12) // The number of accumulated posted header credits since the last request for immediate update that are needed to force an immediate update. The default is (PH_INIT_CREDIT &gt;&gt; 1). A value of 0 means always force an update (if infinite credits are not advertised).
+  #define PCIEIP_REG_TL_FCIMM_P_LIMIT_REG_FC_PH_IMM_LIMIT_BB_SHIFT                                           12
+  #define PCIEIP_REG_TL_FCIMM_P_LIMIT_REG_ENA_FC_P_IMMEDIATE_BB                                              (0x1<<20) // When set, released posted credits are flagged for immediate update. When clear, the credits may or not be updated until one or more of the accumulated credit thresholds for posted header or posted data is reached. (If clear and infinite credits are advertised, the thresholds are not used to force immediate updates.)
+  #define PCIEIP_REG_TL_FCIMM_P_LIMIT_REG_ENA_FC_P_IMMEDIATE_BB_SHIFT                                        20
+  #define PCIEIP_REG_TL_FCIMM_P_LIMIT_REG_FC_P_USCNT_BB                                                      (0xf<<21) // The number of microseconds between the last update and the forced update if there are outstanding posted credits to update. The resolution on the timer is +/- 1 us.
+  #define PCIEIP_REG_TL_FCIMM_P_LIMIT_REG_FC_P_USCNT_BB_SHIFT                                                21
+  #define PCIEIP_REG_TL_FCIMM_P_LIMIT_REG_ENA_FC_P_UPD_10US_BB                                               (0x1<<25) // When set, outstanding posted credit updates are forwarded to the DLL as immediate updates after a given number of microseconds (see below) elapses since the last update. This is typically used with non-immediate (threshold-based) updates.
+  #define PCIEIP_REG_TL_FCIMM_P_LIMIT_REG_ENA_FC_P_UPD_10US_BB_SHIFT                                         25
+#define PCIEIP_REG_REG_CAPENA_FN0_MASK_BB                                                                    0x000a1cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_CAPENA_FN0_MASK_CAP_ENA_FN0_MASK_BB                                                 (0xf<<0) // Each bit, when set, indicates that the corresponding capability available in cap_ena is valid only for function 0 and the the corresponding capability for other physical functions are disabled.
+  #define PCIEIP_REG_REG_CAPENA_FN0_MASK_CAP_ENA_FN0_MASK_BB_SHIFT                                           0
+  #define PCIEIP_REG_REG_CAPENA_FN0_MASK_EXT_CAP_ENA_FN0_MASK_BB                                             (0x3ff<<4) // Each bit, when set, indicates that the corresponding capability available in ext_cap_ena is valid only for function 0 and the the corresponding capability for other physical functions are disabled.
+  #define PCIEIP_REG_REG_CAPENA_FN0_MASK_EXT_CAP_ENA_FN0_MASK_BB_SHIFT                                       4
+  #define PCIEIP_REG_REG_CAPENA_FN0_MASK_RC_EXT_CAP_ENA_FN0_MASK_BB                                          (0x3<<14) // Each bit, when set, indicates that the corresponding capability available in rc_ext_cap_ena is valid only for function 0 and the the corresponding capability for other physical functions are disabled.
+  #define PCIEIP_REG_REG_CAPENA_FN0_MASK_RC_EXT_CAP_ENA_FN0_MASK_BB_SHIFT                                    14
+  #define PCIEIP_REG_REG_CAPENA_FN0_MASK_EXT2_CAP_ENA_FN0_MASK_BB                                            (0xf<<16) // Each bit, when set, indicates that the corresponding capability available in ext2_cap_ena is valid only for function 0 and the the corresponding capability for other physical functions are disabled.
+  #define PCIEIP_REG_REG_CAPENA_FN0_MASK_EXT2_CAP_ENA_FN0_MASK_BB_SHIFT                                      16
+  #define PCIEIP_REG_REG_CAPENA_FN0_MASK_EXT3_CAP_ENA_FN0_MASK_BB                                            (0xf<<20) // Each bit, when set, indicates that the corresponding capability available in ext3_cap_ena is valid only for function 0 and the the corresponding capability for other physical functions are disabled.
+  #define PCIEIP_REG_REG_CAPENA_FN0_MASK_EXT3_CAP_ENA_FN0_MASK_BB_SHIFT                                      20
+  #define PCIEIP_REG_REG_CAPENA_FN0_MASK_UNUSED0_BB                                                          (0x3<<24) // 
+  #define PCIEIP_REG_REG_CAPENA_FN0_MASK_UNUSED0_BB_SHIFT                                                    24
+  #define PCIEIP_REG_REG_CAPENA_FN0_MASK_RC_EXT2_CAP_ENA_FN0_MASK_BB                                         (0x1f<<26) // Each bit, when set, indicates that the corresponding capability available in rc_ext2_cap_ena is valid only for function 0 and the the corresponding capability for other physical functions are disabled.
+  #define PCIEIP_REG_REG_CAPENA_FN0_MASK_RC_EXT2_CAP_ENA_FN0_MASK_BB_SHIFT                                   26
+#define PCIEIP_REG_VDM_CTL0_BB                                                                               0x000a20UL //Access:RW   DataWidth:0x20   // This register is present if PCIE_VDM_SUPP is defined in version.v
+  #define PCIEIP_REG_VDM_CTL0_REG_VDM_LENGTH_BB                                                              (0x3ff<<0) // Length in bytes to which VDM messages are restricted to
+  #define PCIEIP_REG_VDM_CTL0_REG_VDM_LENGTH_BB_SHIFT                                                        0
+  #define PCIEIP_REG_VDM_CTL0_UNUSED0_BB                                                                     (0x3f<<10) // 
+  #define PCIEIP_REG_VDM_CTL0_UNUSED0_BB_SHIFT                                                               10
+  #define PCIEIP_REG_VDM_CTL0_REG_VDM_ENABLED_BB                                                             (0x1<<16) // VDM is enabled when this bit is set. PCIe will pass VDM messgaes to user interface when this bit is enabled, else it will be silently dropped.
+  #define PCIEIP_REG_VDM_CTL0_REG_VDM_ENABLED_BB_SHIFT                                                       16
+#define PCIEIP_REG_PTM_CTL0_BB                                                                               0x000a24UL //Access:RW   DataWidth:0x20   // This register is present if PCIE_PTM_SUPP is defined in version.v
+  #define PCIEIP_REG_PTM_CTL0_REG_PTM_REQ_START_BB                                                           (0x1<<0) // This bit when set, forces hardware to generate a PTM Request message. Hardware automatically clears this bit, when the PTM response is received.
+  #define PCIEIP_REG_PTM_CTL0_REG_PTM_REQ_START_BB_SHIFT                                                     0
+  #define PCIEIP_REG_PTM_CTL0_REG_PTM_ATTN_MASK_BB                                                           (0x1<<1) // This field when set will prevent hardware from generating attention when PTM req- response handshake has completed.
+  #define PCIEIP_REG_PTM_CTL0_REG_PTM_ATTN_MASK_BB_SHIFT                                                     1
+  #define PCIEIP_REG_PTM_CTL0_UNUSED0_BB                                                                     (0xfffffff<<2) // 
+  #define PCIEIP_REG_PTM_CTL0_UNUSED0_BB_SHIFT                                                               2
+  #define PCIEIP_REG_PTM_CTL0_REG_PTM_ATTN_STAT_BB                                                           (0x1<<30) // This field when set inidcates that the PTM req-response handshake initiated by software has completed. This bit is cleared by writing to it.
+  #define PCIEIP_REG_PTM_CTL0_REG_PTM_ATTN_STAT_BB_SHIFT                                                     30
+  #define PCIEIP_REG_PTM_CTL0_REG_PTM_REQ_STATUS_BB                                                          (0x1<<31) // This field when set inidcates that the PTM req-response handshake completed successfully. This field is valid only when bit 30 is set.
+  #define PCIEIP_REG_PTM_CTL0_REG_PTM_REQ_STATUS_BB_SHIFT                                                    31
+#define PCIEIP_REG_PTM_PMSTR_HI_BB                                                                           0x000a28UL //Access:R    DataWidth:0x20   // This register is present if PCIE_PTM_SUPP is defined in version.v
+#define PCIEIP_REG_PTM_PMSTR_LO_BB                                                                           0x000a2cUL //Access:R    DataWidth:0x20   // This register is present if PCIE_PTM_SUPP is defined in version.v
+#define PCIEIP_REG_PTM_LOCAL_HI_BB                                                                           0x000a30UL //Access:R    DataWidth:0x20   // This register is present if PCIE_PTM_SUPP is defined in version.v
+#define PCIEIP_REG_PTM_LOCAL_LO_BB                                                                           0x000a34UL //Access:R    DataWidth:0x20   // This register is present if PCIE_PTM_SUPP is defined in version.v
+#define PCIEIP_REG_PTM_RES_LOCAL_HI_BB                                                                       0x000a38UL //Access:R    DataWidth:0x20   // This register is present if PCIE_PTM_SUPP is defined in version.v
+#define PCIEIP_REG_PTM_RES_LOCAL_LO_BB                                                                       0x000a3cUL //Access:R    DataWidth:0x20   // This register is present if PCIE_PTM_SUPP is defined in version.v
+#define PCIEIP_REG_PTM_MSTR_PROP_DLY_BB                                                                      0x000a40UL //Access:R    DataWidth:0x20   // This register is present if PCIE_PTM_SUPP is defined in version.v
+#define PCIEIP_REG_PCIER_TL_STAT_TX_CTL_BB                                                                   0x000a50UL //Access:RW   DataWidth:0x20   // Control register for tx tlp statistics
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_CTL_REG_TTX_TLP_STAT_EN_BB                                             (0x1<<0) // TLP Statistics Enable. Setting this bit to '1' enables the tx TLP statistics collection. Hardware will count various types of TLPs in the TX direction, as programmed in the reg_ttx_det_tlp_type register. When this bit is reset to '0', the counting stops and software can read the results. This bit is automatically cleared after the specified time if reg_ttx_tlp_stat_len is non-zero. All statistic read-back registers are cleared when this transitions from '0' to '1'.
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_CTL_REG_TTX_TLP_STAT_EN_BB_SHIFT                                       0
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_CTL_UNUSED0_BB                                                         (0x7f<<1) // 
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_CTL_UNUSED0_BB_SHIFT                                                   1
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_CTL_REG_TTX_TLP_STAT_LEN_BB                                            (0xffffff<<8) // TLP Statistics Length. This field specifies the TLP statistics collection time in microseconds. When it is set to '0', software has to clear the reg_ttx_tlp_stat_en bit to stop the operation. When it is set to a non-zero value, hardware automatically clears the enable bit after the specified time.
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_CTL_REG_TTX_TLP_STAT_LEN_BB_SHIFT                                      8
+#define PCIEIP_REG_PCIER_TL_STAT_TX_TYPE_BB                                                                  0x000a54UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_TYPE_REG_TTX_DET_TLP_TYPE_0_BB                                         (0xff<<0) // This register contains Enable bit and the TLP type that hardware can detect. Bit[7] is enable bit. If this bit is set to 1, then hardware will detect the TLP type indicated by bits[6:0] Bits[6:0] indicate TLP type. TLP type can be masked using reg_ttx_det_tlp_type_mask[6:0].
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_TYPE_REG_TTX_DET_TLP_TYPE_0_BB_SHIFT                                   0
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_TYPE_REG_TTX_DET_TLP_TYPE_1_BB                                         (0xff<<8) // This register contains Enable bit and the TLP type that hardware can detect. Bit[15] is enable bit. If this bit is set to 1, then hardware will detect the TLP type indicated by bits[14:8] Bits[14:8] indicate TLP type. TLP type can be masked using reg_ttx_det_tlp_type_mask[14:8].
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_TYPE_REG_TTX_DET_TLP_TYPE_1_BB_SHIFT                                   8
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_TYPE_REG_TTX_DET_TLP_TYPE_2_BB                                         (0xff<<16) // This register contains Enable bit and the TLP type that hardware can detect. Bit[23] is enable bit. If this bit is set to 1, then hardware will detect the TLP type indicated by bits[22:16] Bits[22:16] indicate TLP type. TLP type can be masked using reg_ttx_det_tlp_type_mask[22:16].
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_TYPE_REG_TTX_DET_TLP_TYPE_2_BB_SHIFT                                   16
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_TYPE_REG_TTX_DET_TLP_TYPE_3_BB                                         (0xff<<24) // This register contains Enable bit and the TLP type that hardware can detect. Bit[31] is enable bit. If this bit is set to 1, then hardware will detect the TLP type indicated by bits[30:24] Bits[30:24] indicate TLP type. TLP type can be masked using reg_ttx_det_tlp_type_mask[30:24].
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_TYPE_REG_TTX_DET_TLP_TYPE_3_BB_SHIFT                                   24
+#define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_BB                                                                  0x000a58UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_REG_TTX_DET_TLP_TYPE_MASK_0_BB                                    (0x7f<<0) // This register contains the mask bits for reg_ttx_det_tlp_type_0. Bits[7:0] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding bit of reg_ttx_det_tlp_type_0 will be masked. Masking works only if Enable bit (bit [7] of reg_ttx_det_tlp_type_0) is true.
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_REG_TTX_DET_TLP_TYPE_MASK_0_BB_SHIFT                              0
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_UNUSED0_BB                                                        (0x1<<7) // 
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_UNUSED0_BB_SHIFT                                                  7
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_REG_TTX_DET_TLP_TYPE_MASK_1_BB                                    (0x7f<<8) // This register contains the mask bits for reg_ttx_det_tlp_type_1. Bits[14:8] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding bit of reg_ttx_det_tlp_type_1 will be masked. Masking works only if Enable bit (bit [15] of reg_ttx_det_tlp_type_1) is true.
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_REG_TTX_DET_TLP_TYPE_MASK_1_BB_SHIFT                              8
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_UNUSED1_BB                                                        (0x1<<15) // 
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_UNUSED1_BB_SHIFT                                                  15
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_REG_TTX_DET_TLP_TYPE_MASK_2_BB                                    (0x7f<<16) // This register contains the mask bits for reg_ttx_det_tlp_type_2. Bits[22:16] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding bit of reg_ttx_det_tlp_type_2 will be masked. Masking works only if Enable bit (bit [7] of reg_ttx_det_tlp_type_2) is true.
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_REG_TTX_DET_TLP_TYPE_MASK_2_BB_SHIFT                              16
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_UNUSED2_BB                                                        (0x1<<23) // 
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_UNUSED2_BB_SHIFT                                                  23
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_REG_TTX_DET_TLP_TYPE_MASK_3_BB                                    (0x7f<<24) // This register contains the mask bits for reg_ttx_det_tlp_type_3. Bits[30:24] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding bit of reg_ttx_det_tlp_type_3 will be masked. Masking works only if Enable bit (bit [7] of reg_ttx_det_tlp_type_3) is true.
+  #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_REG_TTX_DET_TLP_TYPE_MASK_3_BB_SHIFT                              24
+#define PCIEIP_REG_PCIER_TL_STAT_TX_CTR_LO_BB                                                                0x000a5cUL //Access:R    DataWidth:0x20   // TX TLP Statistics Low 32 bits. This register indicates the number of TLPs that have been trasmitted. It is cleared when reg_ttx_tlp_stat_en goes from '0' to '1'.
+#define PCIEIP_REG_PCIER_TL_STAT_TX_CTR_HI_BB                                                                0x000a60UL //Access:R    DataWidth:0x20   // TX TLP Statistics High 32 bits. This register indicates the number of TLPs that have been trasmitted. It is cleared when reg_ttx_tlp_stat_en goes from '0' to '1'.
+#define PCIEIP_REG_PCIER_TL_STAT_RX_CTL_BB                                                                   0x000a64UL //Access:RW   DataWidth:0x20   // Control register for rx tlp statistics
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_CTL_REG_TRX_TLP_STAT_EN_BB                                             (0x1<<0) // TLP Statistics Enable. Setting this bit to '1' enables the rx TLP statistics collection. Hardware will count various types of TLPs programmed in the reg_trx_det_tlp_type register in RX direction. When this bit is reset to '0', the counting stops and software can read the results. This bit is automatically cleared after the specified time if reg_trx_tlp_stat_len is non-zero. All statistic read-back registers are cleared when this transitions from '0' to '1'.
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_CTL_REG_TRX_TLP_STAT_EN_BB_SHIFT                                       0
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_CTL_UNUSED0_BB                                                         (0x7f<<1) // 
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_CTL_UNUSED0_BB_SHIFT                                                   1
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_CTL_REG_TRX_TLP_STAT_LEN_BB                                            (0xffffff<<8) // TLP Statistics Length. This field specifies the TLP statistics collection time in microseconds. When it is set to '0', software has to clear the reg_trx_tlp_stat_en bit to stop the operation. When it is set to a non-zero value, hardware automatically clears the enable bit after the specified time.
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_CTL_REG_TRX_TLP_STAT_LEN_BB_SHIFT                                      8
+#define PCIEIP_REG_PCIER_TL_STAT_RX_TYPE_BB                                                                  0x000a68UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_TYPE_REG_TRX_DET_TLP_TYPE_0_BB                                         (0xff<<0) // This register contains Enable bit and the TLP type that hardware can detect. Bit[7] is enable bit. If this bit is set to 1, then hardware will detect the TLP type indicated by bits[6:0] Bits[6:0] indicate TLP type. TLP type can be masked using reg_trx_det_tlp_type_mask[6:0].
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_TYPE_REG_TRX_DET_TLP_TYPE_0_BB_SHIFT                                   0
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_TYPE_REG_TRX_DET_TLP_TYPE_1_BB                                         (0xff<<8) // This register contains Enable bit and the TLP type that hardware can detect. Bit[15] is enable bit. If this bit is set to 1, then hardware will detect the TLP type indicated by bits[14:8] Bits[14:8] indicate TLP type. TLP type can be masked using reg_trx_det_tlp_type_mask[14:8].
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_TYPE_REG_TRX_DET_TLP_TYPE_1_BB_SHIFT                                   8
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_TYPE_REG_TRX_DET_TLP_TYPE_2_BB                                         (0xff<<16) // This register contains Enable bit and the TLP type that hardware can detect. Bit[23] is enable bit. If this bit is set to 1, then hardware will detect the TLP type indicated by bits[22:16] Bits[22:16] indicate TLP type. TLP type can be masked using reg_trx_det_tlp_type_mask[22:16].
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_TYPE_REG_TRX_DET_TLP_TYPE_2_BB_SHIFT                                   16
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_TYPE_REG_TRX_DET_TLP_TYPE_3_BB                                         (0xff<<24) // This register contains Enable bit and the TLP type that hardware can detect. Bit[31] is enable bit. If this bit is set to 1, then hardware will detect the TLP type indicated by bits[30:24] Bits[30:24] indicate TLP type. TLP type can be masked using reg_trx_det_tlp_type_mask[30:24].
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_TYPE_REG_TRX_DET_TLP_TYPE_3_BB_SHIFT                                   24
+#define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_BB                                                                  0x000a6cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_REG_TRX_DET_TLP_TYPE_MASK_0_BB                                    (0x7f<<0) // This register contains the mask bits for reg_trx_det_tlp_type_0. Bits[7:0] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding bit of reg_trx_det_tlp_type_0 will be masked. Masking works only if Enable bit (bit [7] of reg_trx_det_tlp_type_0) is true.
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_REG_TRX_DET_TLP_TYPE_MASK_0_BB_SHIFT                              0
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_UNUSED0_BB                                                        (0x1<<7) // 
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_UNUSED0_BB_SHIFT                                                  7
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_REG_TRX_DET_TLP_TYPE_MASK_1_BB                                    (0x7f<<8) // This register contains the mask bits for reg_trx_det_tlp_type_1. Bits[14:8] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding bit of reg_trx_det_tlp_type_1 will be masked. Masking works only if Enable bit (bit [15] of reg_trx_det_tlp_type_1) is true.
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_REG_TRX_DET_TLP_TYPE_MASK_1_BB_SHIFT                              8
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_UNUSED1_BB                                                        (0x1<<15) // 
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_UNUSED1_BB_SHIFT                                                  15
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_REG_TRX_DET_TLP_TYPE_MASK_2_BB                                    (0x7f<<16) // This register contains the mask bits for reg_trx_det_tlp_type_2. Bits[22:16] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding bit of reg_trx_det_tlp_type_2 will be masked. Masking works only if Enable bit (bit [7] of reg_trx_det_tlp_type_2) is true.
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_REG_TRX_DET_TLP_TYPE_MASK_2_BB_SHIFT                              16
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_UNUSED2_BB                                                        (0x1<<23) // 
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_UNUSED2_BB_SHIFT                                                  23
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_REG_TRX_DET_TLP_TYPE_MASK_3_BB                                    (0x7f<<24) // This register contains the mask bits for reg_trx_det_tlp_type_3. Bits[30:24] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding bit of reg_trx_det_tlp_type_3 will be masked. Masking works only if Enable bit (bit [7] of reg_trx_det_tlp_type_3) is true.
+  #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_REG_TRX_DET_TLP_TYPE_MASK_3_BB_SHIFT                              24
+#define PCIEIP_REG_PCIER_TL_STAT_RX_CTR_LO_BB                                                                0x000a70UL //Access:R    DataWidth:0x20   // RX TLP Statistics Low 32 bits. This register indicates the number of TLPs that have been trasmitted. It is cleared when reg_trx_tlp_stat_en goes from '0' to '1'.
+#define PCIEIP_REG_PCIER_TL_STAT_RX_CTR_HI_BB                                                                0x000a74UL //Access:R    DataWidth:0x20   // RX TLP Statistics High 32 bits. This register indicates the number of TLPs that have been trasmitted. It is cleared when reg_trx_tlp_stat_en goes from '0' to '1'.
+#define PCIEIP_REG_PL_LTR_LATENCY_OFF_K2_E5                                                                  0x000b30UL //Access:RW   DataWidth:0x20   // LTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port, the register fields capture the corresponding fields in the LTR messages that are transmitted by the port. For a downstream port, the register fields capture the corresponding fields in the LTR messages that are received by the port. The full content of the register is reflected on the app_ltr_latency[31:0] output.
+  #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_K2_E5                                            (0x3ff<<0) // Snoop Latency Value.  Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_K2_E5_SHIFT                                      0
+  #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_K2_E5                                            (0x7<<10) // Snoop Latency Scale.  Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_K2_E5_SHIFT                                      10
+  #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_K2_E5                                          (0x1<<15) // Snoop Latency Requirement.  Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_K2_E5_SHIFT                                    15
+  #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_K2_E5                                         (0x3ff<<16) // No Snoop Latency Value.  Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_K2_E5_SHIFT                                   16
+  #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_K2_E5                                         (0x7<<26) // No Snoop Latency Scale.  Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_K2_E5_SHIFT                                   26
+  #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_K2_E5                                       (0x1<<31) // No Snoop Latency Requirement.  Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_K2_E5_SHIFT                                 31
+#define PCIEIP_REG_AUX_CLK_FREQ_OFF_K2_E5                                                                    0x000b40UL //Access:RW   DataWidth:0x20   // Auxiliary Clock Frequency Control Register.
+  #define PCIEIP_REG_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_K2_E5                                                     (0x3ff<<0) // The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy in the time counted. If the actual frequency (f) of aux_clk does not exactly match the programmed frequency (f_prog), then there is an error in the time counted by the core that can be expressed in percentage as: err% = (f_prog/f-1)*100. For example if f=2.5 MHz and f_prog=3 MHz, then err% =(3/2.5-1)*100 =20%, meaning that the time counted by the core on aux_clk will be 20% greater than the time in us programmed in the corresponding time register (for example T_POWER_ON).  Note: This register field is sticky.
+  #define PCIEIP_REG_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_K2_E5_SHIFT                                               0
+#define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_BB                                                                 0x000c00UL //Access:RW   DataWidth:0x20   // Main status and control register for the PL DL Debug FIFO. Trigger and status shown in this register. For the above two bits, 0b10 is ready but not triggered, 0b11 is actively collecting and triggered, and 0b01 is that the DBG FIFO has collected all needed data.
+  #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_PRETRIG_CNT_BB                                          (0xff<<0) // When non-zero, indicates the maximum number of entries collected and saved prior to the trigger.
+  #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_PRETRIG_CNT_BB_SHIFT                                    0
+  #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_FIFO_RD_CTRL_CSRD_USER_B_BB                                      (0x1<<8) // When cleared, indicates that the DBG FIFO is read by user interface. When set, indicates that the DBG FIFO is read by CS registers only.
+  #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_FIFO_RD_CTRL_CSRD_USER_B_BB_SHIFT                                8
+  #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_TRIG_ADDR_BB                                            (0x1ff<<9) // When DBG FIFO is triggered, this indicates the FIFO address of the trigger location (where data corresponding to the trigger cycle is collected). Bit 17 is a wrap condition in the FIFO
+  #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_TRIG_ADDR_BB_SHIFT                                      9
+  #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_RADDR_BB                                                (0xff<<18) // Current dbg fifo read pointer on write side.
+  #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_RADDR_BB_SHIFT                                          18
+  #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_ATTN_ST_BB                                              (0x1<<26) // Asserted when attn signal is generated and active. Write 1 to clear the attn.
+  #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_ATTN_ST_BB_SHIFT                                        26
+  #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_ATTN_BB                                                 (0x1<<27) // Enables to generate attention to trigger external logic analyzers.
+  #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_ATTN_BB_SHIFT                                           27
+  #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_RESERVED_28_BB                                                   (0x1<<28) // 
+  #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_RESERVED_28_BB_SHIFT                                             28
+  #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_FIFO_PRETRIG_FULL_BB                                             (0x1<<29) // Indicates that DBG FIFO has filled the pretrigger buffer before the trigger occurred. If the trigger occurs before the pretrigger buffer is filled, the trig_addr field is used to determine the amount of pre-trigger data collected
+  #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_FIFO_PRETRIG_FULL_BB_SHIFT                                       29
+  #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_TRIGGERED_BB                                            (0x1<<30) // Indicates that the DBG FIFO is triggered.
+  #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_TRIGGERED_BB_SHIFT                                      30
+  #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_ACTIVE_BB                                               (0x1<<31) // When set by write, activates the DBG FIFO logic. To retrigger, this must be cleared then set again.  When read, this indicates that the DBG FIFO is active (waiting for a trigger).
+  #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_ACTIVE_BB_SHIFT                                         31
+#define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_BB                                                             0x000c04UL //Access:RW   DataWidth:0x20   // Control and Status for accesses to DBG FIFO indirect registers.
+  #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_IND_WADDR_REG_BB                                             (0x1ff<<0) // The indirect write address register.
+  #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_IND_WADDR_REG_BB_SHIFT                                       0
+  #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_IND_WADDR_AUTOINC_BB                                         (0x1<<9) // When set, the indirect write address register is incremented on writes and, if ind_no_rd_addr is set, it is also incremented on reads.
+  #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_IND_WADDR_AUTOINC_BB_SHIFT                                   9
+  #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_IND_RADDR_REG_BB                                             (0x1ff<<10) // The indirect read address register.
+  #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_IND_RADDR_REG_BB_SHIFT                                       10
+  #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_IND_RADDR_AUTOINC_BB                                         (0x1<<19) // When set, the indirect read address register is incremented on reads.
+  #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_IND_RADDR_AUTOINC_BB_SHIFT                                   19
+  #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_IND_NO_RADDR_BB                                              (0x1<<20) // When set, the indirect write address register is used for indirect reads as well.
+  #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_IND_NO_RADDR_BB_SHIFT                                        20
+  #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_RESERVED_22_BB                                               (0x3<<21) // 
+  #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_RESERVED_22_BB_SHIFT                                         21
+  #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_DBG_FIFO_WADDR_BB                                            (0x1ff<<23) // Current write address to the external FIFO. Bit 31 is a wrap condition in the FIFO
+  #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_DBG_FIFO_WADDR_BB_SHIFT                                      23
+#define PCIEIP_REG_PCIER_DBG_FIFO_IND_DATA_BB                                                                0x000c08UL //Access:RW   DataWidth:0x20   // Access to the currently referenced indirect register via ind_raddr_reg or ind_waddr_reg. The registers are:  Register 0 :: IND_PCIE_DBG_TRIG0_0TO1_MASK - mask bits [319:0] for 0to1 trigger0 Register 10 :: IND_PCIE_DBG_TRIG0_1TO0_MASK - mask bits [319:0] for 1to0 trigger0 Register 20 :: IND_PCIE_DBG_TRIG0_MATCH_MASK - mask bits [319:0] for match trigger0 Register 30 :: IND_PCIE_DBG_TRIG0_MATCH_VALUE - match value bits[319:0] for trigger0  Register 40 :: IND_PCIE_DBG_TRIG0_DATA_SELECT - [127:0] Trigger0 signals each group is selected with 8 bits among the 256 32 bit signals Register 50 :: IND_PCIE_DBG_TRIG1_0TO1_MASK - mask bits [319:0] for 0to1 trigger1 Register 60 :: IND_PCIE_DBG_TRIG1_1TO0_MASK - mask bits [319:0] for 1to0 trigger1 Register 70 :: IND_PCIE_DBG_TRIG1_MATCH_MASK - mask bits [319:0] for match trigger1 Register 80 :: IND_PCIE_DBG_TRIG1_MATCH_VALUE - match value bits[319:0] for trigger1  Register 90 :: IND_PCIE_DBG_TRIG1_DATA_SELECT - [127:0] Trigger1 signals each group is selected with 8 bits among the 256 32 bit signals Register 100 :: IND_PCIE_DBG_TRIG2_0TO1_MASK - mask bits [319:0] for 0to1 trigger2 Register 110 :: IND_PCIE_DBG_TRIG2_1TO0_MASK - mask bits [319:0] for 1to0 trigger2 Register 120 :: IND_PCIE_DBG_TRIG2_MATCH_MASK - mask bits [319:0] for match trigger2 Register 130 :: IND_PCIE_DBG_TRIG2_MATCH_VALUE - match value bits[319:0] for trigger2  Register 140 :: IND_PCIE_DBG_TRIG2_DATA_SELECT - [127:0] Trigger2 signals each group is selected with 8 bits among the 256 32 bit signals Register 150 :: IND_PCIE_DBG_TRIG_SELECT - Trigger condition selecta Register 151 :: IND_PCIE_DBG_TRIG_TIMEOUT - Timeout select for Trigger sm Register 160 :: IND_PCIE_DBG_FILTER_0TO1_MASK - mask bits [319:0] for 0to1 data filtering Register 170 :: IND_PCIE_DBG_FILTER_1TO0_MASK - mask bits [319:0] for 1to0 data filtering Register 180 :: IND_PCIE_DBG_FILTER_MATCH0_MASK - mask bits [319:0] for match0 data filtering Register 190 :: IND_PCIE_DBG_FILTER_MATCH0_VALUE - match0 value bits[319:0] for data filtering Register 200 :: IND_PCIE_DBG_FILTER_MATCH1_MASK - mask bits [319:0] for match1 data filtering Register 210 :: IND_PCIE_DBG_FILTER_MATCH1_VALUE - match1 value bits[319:0] for data filtering Register 220 :: IND_PCIE_DBG_FILTER_SELECT - select the advanced filtering mechanism Register 228 :: IND_PCIE_DBG_ATTN_CTRL - Controls the attention generating state machine Register 229 :: IND_PCIE_DBG_ATTN_SELECT - Select which attention to go out Register 230 :: IND_PCIE_DBG_ATTN_0TO1_MASK - mask bits [319:0] for 0to1 attention signal group Register 240 :: IND_PCIE_DBG_ATTN_1TO0_MASK - mask bits [319:0] for 1to0 attention signal group Register 250 :: IND_PCIE_DBG_ATTN_MATCH_MASK - mask bits [319:0] for match attention signal group Register 260 :: IND_PCIE_DBG_ATTN_MATCH_VALUE - match value bits [319:0] for attention signal group Register 270 :: IND_PCIE_DBG_FIFO_DATA_SELECT - bits [127:0] selects the group of signals to store in the fifo each group is selected with 8 bits among the 256 32 bit signals Register 274 :: IND_PCIE_DBG_FIFO_TIME_SELECT - not used in debug fifo mode  Register 275 :: IND_DBG_FIFO_EVENT_SELECT - select which events to count for each of the two event counters. In addition, either level or rising edge sensitivity is selectable Register 276 :: IND_DBG_FIFO_EVENT_CFG0 - event config0 Register 277 :: IND_DBG_FIFO_EVENT_CFG1 - event config1  If accessing an unimplemented register, the value 0xbadaddee will be returned.
+#define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_BB                                                                 0x000c0cUL //Access:RW   DataWidth:0x20   // Debug Control for PL DL DEBUG FIFO
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_TRIGSM_BB                                                        (0xf<<0) // Debug fifo trigger state machine status
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_TRIGSM_BB_SHIFT                                                  0
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_TRIGGER_OUT_BB                                                   (0x7<<4) // Trigger_out[2:0] status
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_TRIGGER_OUT_BB_SHIFT                                             4
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RESERVED_7_BB                                                    (0x1<<7) // 
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RESERVED_7_BB_SHIFT                                              7
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_ATTNSM_BB                                                        (0x3<<8) // Debug fifo attn state machine status
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_ATTNSM_BB_SHIFT                                                  8
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_DBG_FIFO_ATTN_BB                                                 (0x1<<10) // Debug fifo attn signal status
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_DBG_FIFO_ATTN_BB_SHIFT                                           10
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RESERVED_23_BB                                                   (0x1fff<<11) // 
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RESERVED_23_BB_SHIFT                                             11
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_CTRL_ATTN_BB                                             (0x1<<24) // When set, asserts attn signal irrespective of attnsm state
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_CTRL_ATTN_BB_SHIFT                                       24
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RD_SIDE_SOFT_RST_25_BB                                           (0x1<<25) // When set, resets user side interface for tlda2 fifo
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RD_SIDE_SOFT_RST_25_BB_SHIFT                                     25
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RD_SIDE_SOFT_RST_26_BB                                           (0x1<<26) // When set, resets user side interface for tlda fifo
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RD_SIDE_SOFT_RST_26_BB_SHIFT                                     26
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RD_SIDE_SOFT_RST_27_BB                                           (0x1<<27) // When set, resets user side interface for dbg fifo
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RD_SIDE_SOFT_RST_27_BB_SHIFT                                     27
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_FIFO_CTL_28_BB                                           (0x1<<28) // When set, clears the debug fifo active also enables user side flush for debug fifo
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_FIFO_CTL_28_BB_SHIFT                                     28
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_FIFO_CTL_29_BB                                           (0x1<<29) // When set, activates debug fifo
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_FIFO_CTL_29_BB_SHIFT                                     29
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_FIFO_CTL_30_BB                                           (0x1<<30) // When set, resets notrig_cnt and trigsm
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_FIFO_CTL_30_BB_SHIFT                                     30
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_FIFO_CTL_31_BB                                           (0x1<<31) // When set, dbg_fifo_triggered will get asserted irrespective of trigsm state
+  #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_FIFO_CTL_31_BB_SHIFT                                     31
+#define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_BB                                                                0x000c10UL //Access:RW   DataWidth:0x20   // Control for TL PL/DL debug FIFO's
+  #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_USER_RD_FIFO_SEL_BB                                             (0x7<<0) // 000 - no FIFO selected to read by user if  001 - PL/DL FIFO is selected to read by user if  010 - TLDA-0 FIFO is selected to read by user if  100 - TLDA-1 FIFO is selected to read by user if  All other encodings are reserved and un-expected results would come if selected.
+  #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_USER_RD_FIFO_SEL_BB_SHIFT                                       0
+  #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_UNUSED0_BB                                                      (0x1ff<<3) // 
+  #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_UNUSED0_BB_SHIFT                                                3
+  #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_DBG_FIFO_SEL_BB                                                 (0x7<<12) // 000 - generic lane is selected  001 - predefined lane 1  010 - predefined lane 2  .  .  .  111 - Serdes data seleted
+  #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_DBG_FIFO_SEL_BB_SHIFT                                           12
+  #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_RESERVED_15_BB                                                  (0x1<<15) // 
+  #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_RESERVED_15_BB_SHIFT                                            15
+  #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_TLDA_FIFO_MUX_SEL_BB                                            (0xf<<16) // TLDA mux will be selected
+  #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_TLDA_FIFO_MUX_SEL_BB_SHIFT                                      16
+  #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_TLDA_FIFO2_MUX_SEL_BB                                           (0xf<<20) // TLDA2 mux will be selected
+  #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_TLDA_FIFO2_MUX_SEL_BB_SHIFT                                     20
+  #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_RESERVED_31_BB                                                  (0xff<<24) // 
+  #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_RESERVED_31_BB_SHIFT                                            24
+#define PCIEIP_REG_PCIER_DBG_FIFO_RD_9_BB                                                                    0x000c18UL //Access:R    DataWidth:0x20   // The ten read registers give a total of 320 bits of data from the DBG FIFO. The DBG FIFO is read when PCIER_DBG_FIFO_RD_0 is read every time.  If the DBG FIFO location is not used, each register will read 0xFFFFFFFF.
+#define PCIEIP_REG_PCIER_DBG_FIFO_RD_8_BB                                                                    0x000c1cUL //Access:R    DataWidth:0x20   // Bits [287:256] of the current DBG FIFO location
+#define PCIEIP_REG_PCIER_DBG_FIFO_RD_7_BB                                                                    0x000c20UL //Access:R    DataWidth:0x20   // Bits [255:224] of the current DBG FIFO location
+#define PCIEIP_REG_PCIER_DBG_FIFO_RD_6_BB                                                                    0x000c24UL //Access:R    DataWidth:0x20   // Bits [223:192] of the current DBG FIFO location
+#define PCIEIP_REG_PCIER_DBG_FIFO_RD_5_BB                                                                    0x000c28UL //Access:R    DataWidth:0x20   // Bits [191:160] of the current DBG FIFO location
+#define PCIEIP_REG_PCIER_DBG_FIFO_RD_4_BB                                                                    0x000c2cUL //Access:R    DataWidth:0x20   // Bits [159:128] of the current DBG FIFO location
+#define PCIEIP_REG_PCIER_DBG_FIFO_RD_3_BB                                                                    0x000c30UL //Access:R    DataWidth:0x20   // Bits [127:96] of the current DBG FIFO location
+#define PCIEIP_REG_PCIER_DBG_FIFO_RD_2_BB                                                                    0x000c34UL //Access:R    DataWidth:0x20   // Bits [95:64] of the current DBG FIFO location
+#define PCIEIP_REG_PCIER_DBG_FIFO_RD_1_BB                                                                    0x000c38UL //Access:R    DataWidth:0x20   // Bits [63:32] of the current DBG FIFO location
+#define PCIEIP_REG_PCIER_DBG_FIFO_RD_0_BB                                                                    0x000c3cUL //Access:R    DataWidth:0x20   // Bits [31:0] of the current DBG FIFO location
+#define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_BB                                                                    0x000c40UL //Access:RW   DataWidth:0x20   // Main status and control register for the Transaction Layer Data Analyzer. Trigger and status shown in this register. If both of the above two bits are set, the results are undefined.
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_TL_TLDAFIFO_RADDR_BB                                                (0x7f<<0) // The current read address for the external FIFO
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_TL_TLDAFIFO_RADDR_BB_SHIFT                                          0
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_FIFO_RADDR_DWSEL_BB                                                 (0x1<<7) // When set, indicates that the lower 160 bits from the current FIFO read address are in the RDFIFO registers.
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_FIFO_RADDR_DWSEL_BB_SHIFT                                           7
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_FIFO_RDAUTOINC_BB                                                   (0x1<<8) // When set and in local mode, reads to PCIER_TLDA_RDFIFO_4 will automatically increment the read address.
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_FIFO_RDAUTOINC_BB_SHIFT                                             8
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LINK_SERIES_BB                                                      (0x1<<9) // When set, the FIFOs are linked in series to increase the depth of the FIFO.
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LINK_SERIES_BB_SHIFT                                                9
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LINK_PARA_BB                                                        (0x1<<10) // When set, the FIFOs are linked in parallel to increase the width of the FIFO.
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LINK_PARA_BB_SHIFT                                                  10
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_UI_PRETRIG_ALL_BB                                                   (0x1<<11) // Valid only when reading FIFOs from the user interface. When set, all pretrigger data is considered valid and will be present on the interface. Note that there is a bug in earlier versions of the TLDA that make this a write-only bit.
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_UI_PRETRIG_ALL_BB_SHIFT                                             11
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_UNUSED0_BB                                                          (0x1<<12) // 
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_UNUSED0_BB_SHIFT                                                    12
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_DATA_AT_TRIG_BB                                                     (0x1<<13) // When set after FIFO has triggered, indicates that data at the trigger has been collected (as opposed to filtered out based on indirect register settings).
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_DATA_AT_TRIG_BB_SHIFT                                               13
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LOCAL_MODE_BB                                                       (0x1<<14) // When set, indicates that the FIFO is operating in local mode - FIFO will be read from the registers. When cleared, indicates that the FIFO is operating through reads from the user interface.
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LOCAL_MODE_BB_SHIFT                                                 14
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_PRETRIG_CNT_BB                                                      (0x7f<<15) // The number of pre-trigger samples to keep. pretrig_cnt[6] is only valid when if there are two TLDA blocks and they are linked serially (extending the FIFO depth).
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_PRETRIG_CNT_BB_SHIFT                                                15
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_TRIG_ADDR_BB                                                        (0x7f<<22) // The FIFO write address at the time of the trigger. Use bit 13 of this register to determine if there was data collected at the time of the trigger.
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_TRIG_ADDR_BB_SHIFT                                                  22
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_PRETRIG_FULL_BB                                                     (0x1<<29) // Set if pretrigger data was expected and enough data samples were collected prior to the trigger
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_PRETRIG_FULL_BB_SHIFT                                               29
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LOCAL_TLDA_TRIGGERED_BB                                             (0x1<<30) // Indicates that the TLDA is triggered.   For the above two bits, 0b10 is ready but not triggered, 0b11 is actively collecting and triggered, and 0b01 is that the TLDA has collected all needed data.
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LOCAL_TLDA_TRIGGERED_BB_SHIFT                                       30
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LOCAL_TLDA_ACTIVE_BB                                                (0x1<<31) // When set by write, activates the TLDA logic. To retrigger, this must be cleared then set again.  When read, this indicates that the TLDA is active (waiting for a trigger).
+  #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LOCAL_TLDA_ACTIVE_BB_SHIFT                                          31
+#define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_BB                                                                0x000c44UL //Access:RW   DataWidth:0x20   // Control and status register for indirect accesses.
+  #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_IND_WADDR_REG_BB                                                (0xff<<0) // The indirect write address register.
+  #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_IND_WADDR_REG_BB_SHIFT                                          0
+  #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_IND_WADDR_AUTOINC_BB                                            (0x1<<8) // When set, the indirect write address register is incremented on writes and, if ind_no_rd_addr is set, it is also incremented on reads.
+  #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_IND_WADDR_AUTOINC_BB_SHIFT                                      8
+  #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_IND_RADDR_REG_BB                                                (0xff<<9) // The indirect read address register.
+  #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_IND_RADDR_REG_BB_SHIFT                                          9
+  #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_IND_RADDR_AUTOINC_BB                                            (0x1<<17) // When set, the indirect read address register is incremented on reads.
+  #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_IND_RADDR_AUTOINC_BB_SHIFT                                      17
+  #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_IND_NO_RD_ADDR_BB                                               (0x1<<18) // When set, the indirect write address register (below) is used for indirect reads as well.
+  #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_IND_NO_RD_ADDR_BB_SHIFT                                         18
+  #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_UNUSED0_BB                                                      (0x1f<<19) // 
+  #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_UNUSED0_BB_SHIFT                                                19
+  #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_TL_TLDAFIFO_WADDR_BB                                            (0x7f<<24) // Current write address to the external FIFO.
+  #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_TL_TLDAFIFO_WADDR_BB_SHIFT                                      24
+#define PCIEIP_REG_PCIER_TLDA0_IND_DATA_BB                                                                   0x000c48UL //Access:RW   DataWidth:0x20   // Access to the currently referenced indirect register via ind_raddr_reg or ind_waddr_reg. Registers are more fully described in the TLDA docs. The registers are:  -- First trigger configuration registers Register 0 :: IND_TLDA_TRIG0_0TO1_MASK0 -- Trigger 0 rising edge mask bits [31:0]  Register 1 :: IND_TLDA_TRIG0_0TO1_MASK1 -- Trigger 0 rising edge mask bits [63:32]  Register 2 :: IND_TLDA_TRIG0_0TO1_MASK2 -- Trigger 0 rising edge mask bits [95:64]  Register 3 :: IND_TLDA_TRIG0_0TO1_MASK3 -- Trigger 0 rising edge mask bits [127:96]  Register 4 :: IND_TLDA_TRIG0_0TO1_MASK4 -- Trigger 0 rising edge mask bits [159:128]  Register 5 :: IND_TLDA_TRIG0_0TO1_MASK5 -- Trigger 0 rising edge mask bits [191:160]  Register 6 :: IND_TLDA_TRIG0_1TO0_MASK0 -- Trigger 0 falling edge mask bits [31:0]  Register 7 :: IND_TLDA_TRIG0_1TO0_MASK1 -- Trigger 0 falling edge mask bits [63:32]  Register 8 :: IND_TLDA_TRIG0_1TO0_MASK2 -- Trigger 0 falling edge mask bits [95:64]  Register 9 :: IND_TLDA_TRIG0_1TO0_MASK3 -- Trigger 0 falling edge mask bits [127:96]  Register 10 :: IND_TLDA_TRIG0_1TO0_MASK4 -- Trigger 0 falling edge mask bits [159:128]  Register 11 :: IND_TLDA_TRIG0_1TO0_MASK5 -- Trigger 0 falling edge mask bits [191:160]  Register 12 :: IND_TLDA_TRIG0_MATCH_MASK0 -- Trigger 0 bit match mask bits [31:0]  Register 13 :: IND_TLDA_TRIG0_MATCH_MASK1 -- Trigger 0 bit match mask bits [63:32]  Register 14 :: IND_TLDA_TRIG0_MATCH_MASK2 -- Trigger 0 bit match mask bits [95:64]  Register 15 :: IND_TLDA_TRIG0_MATCH_MASK3 -- Trigger 0 bit match mask bits [127:96]  Register 16 :: IND_TLDA_TRIG0_MATCH_MASK4 -- Trigger 0 bit match mask bits [159:128]  Register 17 :: IND_TLDA_TRIG0_MATCH_MASK5 -- Trigger 0 bit match mask bits [191:160]  Register 18 :: IND_TLDA_TRIG0_MATCH_VALUE0 -- Trigger 0 bit match value bits [31:0]  Register 19 :: IND_TLDA_TRIG0_MATCH_VALUE1 -- Trigger 0 bit match value bits [63:32]  Register 20 :: IND_TLDA_TRIG0_MATCH_VALUE2 -- Trigger 0 bit match value bits [95:64]  Register 21 :: IND_TLDA_TRIG0_MATCH_VALUE3 -- Trigger 0 bit match value bits [127:96]  Register 22 :: IND_TLDA_TRIG0_MATCH_VALUE4 -- Trigger 0 bit match value bits [159:128]  Register 23 :: IND_TLDA_TRIG0_MATCH_VALUE5 -- Trigger 0 bit match value bits [191:160]  Register 24 :: IND_TLDA_TRIG0_DATA_SELECT0 -- Bits [31:0] to select the data source for trigger 0  Register 25 :: IND_TLDA_TRIG0_DATA_SELECT1 -- Bits [63:32] to select the data source for trigger 0  Register 26 :: IND_TLDA_TRIG0_DATA_SELECT2 -- Bits [95:64] to select the data source for trigger 0  Register 27 :: IND_TLDA_TRIG0_DATA_SELECT3 -- Bits [127:96] to select the data source for trigger 0  Register 28 :: IND_TLDA_TRIG0_DATA_SELECT4 -- Bits [159:128] to select the data source for trigger 0  Register 29 :: IND_TLDA_TRIG0_DATA_SELECT5 -- Bits [191:160] to select the data source for trigger 0   -- Second trigger configuration registers Register 32 :: IND_TLDA_TRIG1_0TO1_MASK0 -- Trigger 1 rising edge mask bits [31:0]  Register 33 :: IND_TLDA_TRIG1_0TO1_MASK1 -- Trigger 1 rising edge mask bits [63:32]  Register 34 :: IND_TLDA_TRIG1_0TO1_MASK2 -- Trigger 1 rising edge mask bits [95:64]  Register 35 :: IND_TLDA_TRIG1_0TO1_MASK3 -- Trigger 1 rising edge mask bits [127:96]  Register 36 :: IND_TLDA_TRIG1_0TO1_MASK4 -- Trigger 1 rising edge mask bits [159:128]  Register 37 :: IND_TLDA_TRIG1_0TO1_MASK5 -- Trigger 1 rising edge mask bits [191:160]  Register 38 :: IND_TLDA_TRIG1_1TO0_MASK0 -- Trigger 1 falling edge mask bits [31:0]  Register 39 :: IND_TLDA_TRIG1_1TO0_MASK1 -- Trigger 1 falling edge mask bits [63:32]  Register 40 :: IND_TLDA_TRIG1_1TO0_MASK2 -- Trigger 1 falling edge mask bits [95:64]  Register 41 :: IND_TLDA_TRIG1_1TO0_MASK3 -- Trigger 1 falling edge mask bits [127:96]  Register 42 :: IND_TLDA_TRIG1_1TO0_MASK4 -- Trigger 1 falling edge mask bits [159:128]  Register 43 :: IND_TLDA_TRIG1_1TO0_MASK5 -- Trigger 1 falling edge mask bits [191:160]  Register 44 :: IND_TLDA_TRIG1_MATCH_MASK0 -- Trigger 1 bit match mask bits [31:0]  Register 45 :: IND_TLDA_TRIG1_MATCH_MASK1 -- Trigger 1 bit match mask bits [63:32]  Register 46 :: IND_TLDA_TRIG1_MATCH_MASK2 -- Trigger 1 bit match mask bits [95:64]  Register 47 :: IND_TLDA_TRIG1_MATCH_MASK3 -- Trigger 1 bit match mask bits [127:96]  Register 48 :: IND_TLDA_TRIG1_MATCH_MASK4 -- Trigger 1 bit match mask bits [159:128]  Register 49 :: IND_TLDA_TRIG1_MATCH_MASK5 -- Trigger 1 bit match mask bits [191:160]  Register 50 :: IND_TLDA_TRIG1_MATCH_VALUE0 -- Trigger 1 bit match value bits [31:0]  Register 51 :: IND_TLDA_TRIG1_MATCH_VALUE1 -- Trigger 1 bit match value bits [63:32]  Register 52 :: IND_TLDA_TRIG1_MATCH_VALUE2 -- Trigger 1 bit match value bits [95:64]  Register 53 :: IND_TLDA_TRIG1_MATCH_VALUE3 -- Trigger 1 bit match value bits [127:96]  Register 54 :: IND_TLDA_TRIG1_MATCH_VALUE4 -- Trigger 1 bit match value bits [159:128]  Register 55 :: IND_TLDA_TRIG1_MATCH_VALUE5 -- Trigger 1 bit match value bits [191:160]  Register 56 :: IND_TLDA_TRIG1_DATA_SELECT0 -- Bits [31:0] to select the data source for trigger 1  Register 57 :: IND_TLDA_TRIG1_DATA_SELECT1 -- Bits [63:32] to select the data source for trigger 1  Register 58 :: IND_TLDA_TRIG1_DATA_SELECT2 -- Bits [95:64] to select the data source for trigger 1  Register 59 :: IND_TLDA_TRIG1_DATA_SELECT3 -- Bits [127:96] to select the data source for trigger 1  Register 60 :: IND_TLDA_TRIG1_DATA_SELECT4 -- Bits [159:128] to select the data source for trigger 1  Register 61 :: IND_TLDA_TRIG1_DATA_SELECT5 -- Bits [191:160] to select the data source for trigger 1   -- Third trigger configuration registers Register 64 :: IND_TLDA_TRIG2_0TO1_MASK0 -- Trigger 2 rising edge mask bits [31:0]  Register 65 :: IND_TLDA_TRIG2_0TO1_MASK1 -- Trigger 2 rising edge mask bits [63:32]  Register 66 :: IND_TLDA_TRIG2_0TO1_MASK2 -- Trigger 2 rising edge mask bits [95:64]  Register 67 :: IND_TLDA_TRIG2_0TO1_MASK3 -- Trigger 2 rising edge mask bits [127:96]  Register 68 :: IND_TLDA_TRIG2_0TO1_MASK4 -- Trigger 2 rising edge mask bits [159:128]  Register 69 :: IND_TLDA_TRIG2_0TO1_MASK5 -- Trigger 2 rising edge mask bits [191:160]  Register 70 :: IND_TLDA_TRIG2_1TO0_MASK0 -- Trigger 2 falling edge mask bits [31:0]  Register 71 :: IND_TLDA_TRIG2_1TO0_MASK1 -- Trigger 2 falling edge mask bits [63:32]  Register 72 :: IND_TLDA_TRIG2_1TO0_MASK2 -- Trigger 2 falling edge mask bits [95:64]  Register 73 :: IND_TLDA_TRIG2_1TO0_MASK3 -- Trigger 2 falling edge mask bits [127:96]  Register 74 :: IND_TLDA_TRIG2_1TO0_MASK4 -- Trigger 2 falling edge mask bits [159:128]  Register 75 :: IND_TLDA_TRIG2_1TO0_MASK5 -- Trigger 2 falling edge mask bits [191:160]  Register 76 :: IND_TLDA_TRIG2_MATCH_MASK0 -- Trigger 2 bit match mask bits [31:0]  Register 77 :: IND_TLDA_TRIG2_MATCH_MASK1 -- Trigger 2 bit match mask bits [63:32]  Register 78 :: IND_TLDA_TRIG2_MATCH_MASK2 -- Trigger 2 bit match mask bits [95:64]  Register 79 :: IND_TLDA_TRIG2_MATCH_MASK3 -- Trigger 2 bit match mask bits [127:96]  Register 80 :: IND_TLDA_TRIG2_MATCH_MASK4 -- Trigger 2 bit match mask bits [159:128]  Register 81 :: IND_TLDA_TRIG2_MATCH_MASK5 -- Trigger 2 bit match mask bits [191:160]  Register 82 :: IND_TLDA_TRIG2_MATCH_VALUE0 -- Trigger 2 bit match value bits [31:0]  Register 83 :: IND_TLDA_TRIG2_MATCH_VALUE1 -- Trigger 2 bit match value bits [63:32]  Register 84 :: IND_TLDA_TRIG2_MATCH_VALUE2 -- Trigger 2 bit match value bits [95:64]  Register 85 :: IND_TLDA_TRIG2_MATCH_VALUE3 -- Trigger 2 bit match value bits [127:96]  Register 86 :: IND_TLDA_TRIG2_MATCH_VALUE4 -- Trigger 2 bit match value bits [159:128]  Register 87 :: IND_TLDA_TRIG2_MATCH_VALUE5 -- Trigger 2 bit match value bits [191:160]  Register 88 :: IND_TLDA_TRIG2_DATA_SELECT0 -- Bits [31:0] to select the data source for trigger 2  Register 89 :: IND_TLDA_TRIG2_DATA_SELECT1 -- Bits [63:32] to select the data source for trigger 2  Register 90 :: IND_TLDA_TRIG2_DATA_SELECT2 -- Bits [95:64] to select the data source for trigger 2  Register 91 :: IND_TLDA_TRIG2_DATA_SELECT3 -- Bits [127:96] to select the data source for trigger 2  Register 92 :: IND_TLDA_TRIG2_DATA_SELECT4 -- Bits [159:128] to select the data source for trigger 2  Register 93 :: IND_TLDA_TRIG2_DATA_SELECT5 -- Bits [191:160] to select the data source for trigger 2   -- Trigger selection and timeout configuration registers Register 96 :: IND_TLDA_TRIG_SELECT -- Selects which triggers or combination of triggers to use  Register 97 :: IND_TLDA_TRIG_TIMEOUT -- Configures timeouts for trigger actions  Register 98 :: IND_TLDA_TRIG_COMBINED_TRIG -- Selects how triggers from two TLDAs are combined   -- Data filtering based on rising edge in the data Register 100 :: IND_TLDA_FILTER_0TO1_MASK0 -- Data path filter rising edge mask bits [31:0]  Register 101 :: IND_TLDA_FILTER_0TO1_MASK1 -- Data path filter rising edga mask bits [63:32]  Register 102 :: IND_TLDA_FILTER_0TO1_MASK2 -- Data path filter rising edge mask bits [95:64]  Register 103 :: IND_TLDA_FILTER_0TO1_MASK3 -- Data path filter rising edge mask bits [127:96]  Register 104 :: IND_TLDA_FILTER_0TO1_MASK4 -- Data path filter rising edge mask bits [159:128]  Register 105 :: IND_TLDA_FILTER_0TO1_MASK5 -- Data path filter rising edge mask bits [191:160]  Register 106 :: IND_TLDA_FILTER_0TO1_MASK6 -- Data path filter rising edge mask bits [223:192]  Register 107 :: IND_TLDA_FILTER_0TO1_MASK7 -- Data path filter rising edge mask bits [255:224]  Register 108 :: IND_TLDA_FILTER_0TO1_MASK8 -- Data path filter rising edge mask bits [287:256]  Register 109 :: IND_TLDA_FILTER_0TO1_MASK9 -- Data path filter rising edge mask bits [319:288]   -- Data filtering based on faling edge in the data Register 110 :: IND_TLDA_FILTER_1TO0_MASK0 -- Data path filter falling edge mask bits [31:0]  Register 111 :: IND_TLDA_FILTER_1TO0_MASK1 -- Data path filter falling edga mask bits [63:32]  Register 112 :: IND_TLDA_FILTER_1TO0_MASK2 -- Data path filter falling edge mask bits [95:64]  Register 113 :: IND_TLDA_FILTER_1TO0_MASK3 -- Data path filter falling edge mask bits [127:96]  Register 114 :: IND_TLDA_FILTER_1TO0_MASK4 -- Data path filter falling edge mask bits [159:128]  Register 115 :: IND_TLDA_FILTER_1TO0_MASK5 -- Data path filter falling edge mask bits [191:160]  Register 116 :: IND_TLDA_FILTER_1TO0_MASK6 -- Data path filter falling edge mask bits [223:192]  Register 117 :: IND_TLDA_FILTER_1TO0_MASK7 -- Data path filter falling edge mask bits [255:224]  Register 118 :: IND_TLDA_FILTER_1TO0_MASK8 -- Data path filter falling edge mask bits [287:256]  Register 119 :: IND_TLDA_FILTER_1TO0_MASK9 -- Data path filter falling edge mask bits [319:288]   -- Data filtering based on matching (masked) value in the data Register 120 :: IND_TLDA_FILTER_MATCH0_MASK0 -- Data path filter match-0 mask bits [31:0]  Register 121 :: IND_TLDA_FILTER_MATCH0_MASK1 -- Data path filter match-0 mask bits [63:32]  Register 122 :: IND_TLDA_FILTER_MATCH0_MASK2 -- Data path filter match-0 mask bits [95:64]  Register 123 :: IND_TLDA_FILTER_MATCH0_MASK3 -- Data path filter match-0 mask bits [127:96]  Register 124 :: IND_TLDA_FILTER_MATCH0_MASK4 -- Data path filter match-0 mask bits [159:128]  Register 125 :: IND_TLDA_FILTER_MATCH0_MASK5 -- Data path filter match-0 mask bits [191:160]  Register 126 :: IND_TLDA_FILTER_MATCH0_MASK6 -- Data path filter match-0 mask bits [223:192]  Register 127 :: IND_TLDA_FILTER_MATCH0_MASK7 -- Data path filter match-0 mask bits [255:224]  Register 128 :: IND_TLDA_FILTER_MATCH0_MASK8 -- Data path filter match-0 mask bits [287:256]  Register 129 :: IND_TLDA_FILTER_MATCH0_MASK9 -- Data path filter match-0 mask bits [319:288]  Register 130 :: IND_TLDA_FILTER_MATCH0_VALUE0 -- Data path filter match-0 value bits [31:0]  Register 131 :: IND_TLDA_FILTER_MATCH0_VALUE1 -- Data path filter match-0 value bits [63:32]  Register 132 :: IND_TLDA_FILTER_MATCH0_VALUE2 -- Data path filter match-0 value bits [95:64]  Register 133 :: IND_TLDA_FILTER_MATCH0_VALUE3 -- Data path filter match-0 value bits [127:96]  Register 134 :: IND_TLDA_FILTER_MATCH0_VALUE4 -- Data path filter match-0 value bits [159:128]  Register 135 :: IND_TLDA_FILTER_MATCH0_VALUE5 -- Data path filter match-0 value bits [191:160]  Register 136 :: IND_TLDA_FILTER_MATCH0_VALUE6 -- Data path filter match-0 value bits [223:192]  Register 137 :: IND_TLDA_FILTER_MATCH0_VALUE7 -- Data path filter match-0 value bits [255:224]  Register 138 :: IND_TLDA_FILTER_MATCH0_VALUE8 -- Data path filter match-0 value bits [287:256]  Register 139 :: IND_TLDA_FILTER_MATCH0_VALUE9 -- Data path filter match-0 value bits [319:288]  Register 140 :: IND_TLDA_FILTER_MATCH1_MASK0 -- Data path filter match-1 mask bits [31:0]  Register 141 :: IND_TLDA_FILTER_MATCH1_MASK1 -- Data path filter match-1 mask bits [63:32]  Register 142 :: IND_TLDA_FILTER_MATCH1_MASK2 -- Data path filter match-1 mask bits [95:64]  Register 143 :: IND_TLDA_FILTER_MATCH1_MASK3 -- Data path filter match-1 mask bits [127:96]  Register 144 :: IND_TLDA_FILTER_MATCH1_MASK4 -- Data path filter match-1 mask bits [159:128]  Register 145 :: IND_TLDA_FILTER_MATCH1_MASK5 -- Data path filter match-1 mask bits [191:160]  Register 146 :: IND_TLDA_FILTER_MATCH1_MASK6 -- Data path filter match-1 mask bits [223:192]  Register 147 :: IND_TLDA_FILTER_MATCH1_MASK7 -- Data path filter match-1 mask bits [255:224]  Register 148 :: IND_TLDA_FILTER_MATCH1_MASK8 -- Data path filter match-1 mask bits [287:256]  Register 149 :: IND_TLDA_FILTER_MATCH1_MASK9 -- Data path filter match-1 mask bits [319:288]  Register 150 :: IND_TLDA_FILTER_MATCH1_VALUE0 -- Data path filter match-1 value bits [31:0]  Register 151 :: IND_TLDA_FILTER_MATCH1_VALUE1 -- Data path filter match-1 value bits [63:32]  Register 152 :: IND_TLDA_FILTER_MATCH1_VALUE2 -- Data path filter match-1 value bits [95:64]  Register 153 :: IND_TLDA_FILTER_MATCH1_VALUE3 -- Data path filter match-1 value bits [127:96]  Register 154 :: IND_TLDA_FILTER_MATCH1_VALUE4 -- Data path filter match-1 value bits [159:128]  Register 155 :: IND_TLDA_FILTER_MATCH1_VALUE5 -- Data path filter match-1 value bits [191:160]  Register 156 :: IND_TLDA_FILTER_MATCH1_VALUE6 -- Data path filter match-1 value bits [223:192]  Register 157 :: IND_TLDA_FILTER_MATCH1_VALUE7 -- Data path filter match-1 value bits [255:224]  Register 158 :: IND_TLDA_FILTER_MATCH1_VALUE8 -- Data path filter match-1 value bits [287:256]  Register 159 :: IND_TLDA_FILTER_MATCH1_VALUE9 -- Data path filter match-1 value bits [319:288]   Register 160 :: IND_TLDA_FILTER_SELECT -- Select the combinations of data filtering to use  Register 161 :: IND_TLDA_DATA_SELECT0 -- Bits [31:0] to select the data source  Register 162 :: IND_TLDA_DATA_SELECT1 -- Bits [63:32] to select the data source  Register 163 :: IND_TLDA_DATA_SELECT2 -- Bits [95:64] to select the data source  Register 164 :: IND_TLDA_DATA_SELECT3 -- Bits [127:96] to select the data source  Register 165 :: IND_TLDA_DATA_SELECT4 -- Bits [159:128] to select the data source  Register 166 :: IND_TLDA_DATA_SELECT5 -- Bits [191:160] to select the data source   Register 169 :: IND_TLDA_TIME_SELECT -- Select the time stamp to include in the data   Register 170 :: IND_TLDA_PREDEF_DATASEL -- Configure on of the preselected data source combinations   Register 171 :: IND_TLDA_EVENT_SEL -- Select the events to watch  Register 172 :: IND_TLDA_EVENT_CFG0 -- Configure the first set of event actions (counting, thresholds, etc)  Register 173 :: IND_TLDA_EVENT_CFG1 -- Configure the second set of event actions (counting, thresholds, etc)   Register 192 :: IND_TLDA_SPARE_DBG0 -- Spare debug register  Register 193 :: IND_TLDA_SPARE_DBG1 -- Spare debug register   If accessing an unimplemented register, the value 0xbadaddee will be returned.
+#define PCIEIP_REG_PCIER_TLDA0_RDFIFO_4_BB                                                                   0x000c4cUL //Access:R    DataWidth:0x20   // The five read registers give a total of 160 bits of data from the FIFO. The FIFO is read when PCIER_TLDA0_RDFIFO_4 is read every other time. Also, on the opposite reads of PCIER_TLDA0_RDFIFO_4, the data in these registers is advanced to the next half of the FIFO data. So when the first PCIER_TLDA0_RDFIFO_4 read occurs, data is read from the FIFO and bits [159:0] are in these registers. Next read of PCIER_TLDA0_RDFIFO_4, bits [319:160] are in these registers. If the FIFO location is not used, each register will read 0xbaddf1f0.
+#define PCIEIP_REG_PCIER_TLDA0_RDFIFO_3_BB                                                                   0x000c50UL //Access:R    DataWidth:0x20   // Bits [127:96] of the current half-data from the FIFO
+#define PCIEIP_REG_PCIER_TLDA0_RDFIFO_2_BB                                                                   0x000c54UL //Access:R    DataWidth:0x20   // Bits [95:64] of the current half-data from the FIFO
+#define PCIEIP_REG_PCIER_TLDA0_RDFIFO_1_BB                                                                   0x000c58UL //Access:R    DataWidth:0x20   // Bits [63:32] of the current half-data from the FIFO
+#define PCIEIP_REG_PCIER_TLDA0_RDFIFO_0_BB                                                                   0x000c5cUL //Access:R    DataWidth:0x20   // Bits [31:0] of the current half-data from the FIFO
+#define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_BB                                                                    0x000c60UL //Access:RW   DataWidth:0x20   // Main status and control register for the second Transaction Layer Data Analyzer. Trigger and status shown in this register.
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_TL_TLDAFIFO_RADDR_BB                                                (0x7f<<0) // The current read address for the external FIFO
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_TL_TLDAFIFO_RADDR_BB_SHIFT                                          0
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_FIFO_RADDR_DWSEL_BB                                                 (0x1<<7) // When set, indicates that the lower 160 bits from the current FIFO read address are in the RDFIFO registers.
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_FIFO_RADDR_DWSEL_BB_SHIFT                                           7
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_FIFO_RDAUTOINC_BB                                                   (0x1<<8) // When set and in local mode, reads to PCIER_TLDA_RDFIFO_4 will automatically increment the read address.
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_FIFO_RDAUTOINC_BB_SHIFT                                             8
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LINK_SERIES_BB                                                      (0x1<<9) // When set, this indicates the FIFOs are linked in series to increase the depth of the FIFO.
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LINK_SERIES_BB_SHIFT                                                9
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LINK_PARA_BB                                                        (0x1<<10) // When set, this indicates the FIFOs are linked in parallel to increase the width of the FIFO.
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LINK_PARA_BB_SHIFT                                                  10
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_UI_PRETRIG_ALL_BB                                                   (0x1<<11) // Valid only when reading FIFOs from the user interface. When set, all pretrigger data is considered valid and will be present on the interface. Note that there is a bug in earlier versions of the TLDA that make this a write-only bit.
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_UI_PRETRIG_ALL_BB_SHIFT                                             11
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_UNUSED0_BB                                                          (0x1<<12) // 
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_UNUSED0_BB_SHIFT                                                    12
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_DATA_AT_TRIG_BB                                                     (0x1<<13) // When set after FIFO has triggered, indicates that data at the trigger has been collected (as opposed to filtered out based on indirect register settings).
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_DATA_AT_TRIG_BB_SHIFT                                               13
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LOCAL_MODE_BB                                                       (0x1<<14) // When set, indicates that the FIFO is operating in local mode - FIFO will be read from the registers. When cleared, indicates that the FIFO is operating through reads from the user interface.
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LOCAL_MODE_BB_SHIFT                                                 14
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_PRETRIG_CNT_BB                                                      (0x7f<<15) // The number of pre-trigger samples to keep. pretrig_cnt[6] is only valid when if there are two TLDA blocks and they are linked serially (extending the FIFO depth).
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_PRETRIG_CNT_BB_SHIFT                                                15
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_TRIG_ADDR_BB                                                        (0x7f<<22) // The FIFO write address at the time of the trigger. Use bit 13 of this register to determine if there was data collected at the time of the trigger.
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_TRIG_ADDR_BB_SHIFT                                                  22
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_PRETRIG_FULL_BB                                                     (0x1<<29) // Set if pretrigger data was expected and enough data samples were collected prior to the trigger
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_PRETRIG_FULL_BB_SHIFT                                               29
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LOCAL_TLDA_TRIGGERED_BB                                             (0x1<<30) // Indicates that the TLDA is triggered.  For the above two bits, 0b10 is ready but not triggered, 0b11 is actively collecting and triggered, and 0b01 is that the TLDA has collected all needed data.
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LOCAL_TLDA_TRIGGERED_BB_SHIFT                                       30
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LOCAL_TLDA_ACTIVE_BB                                                (0x1<<31) // When set by write, activates the TLDA logic. To retrigger, this must be cleared then set again.  When read, this indicates that the TLDA is active (waiting for a trigger).
+  #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LOCAL_TLDA_ACTIVE_BB_SHIFT                                          31
+#define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_BB                                                                0x000c64UL //Access:RW   DataWidth:0x20   // Control and status register for indirect accesses.
+  #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_IND_WADDR_REG_BB                                                (0xff<<0) // The indirect write address register.
+  #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_IND_WADDR_REG_BB_SHIFT                                          0
+  #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_IND_WADDR_AUTOINC_BB                                            (0x1<<8) // When set, the indirect write address register is incremented on writes and, if ind_no_rd_addr is set, it is also incremented on reads.
+  #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_IND_WADDR_AUTOINC_BB_SHIFT                                      8
+  #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_IND_RADDR_REG_BB                                                (0xff<<9) // The indirect read address register.
+  #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_IND_RADDR_REG_BB_SHIFT                                          9
+  #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_IND_RADDR_AUTOINC_BB                                            (0x1<<17) // When set, the indirect read address register is incremented on reads.
+  #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_IND_RADDR_AUTOINC_BB_SHIFT                                      17
+  #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_IND_NO_RD_ADDR_BB                                               (0x1<<18) // When set, the indirect write address register (below) is used for indirect reads as well.
+  #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_IND_NO_RD_ADDR_BB_SHIFT                                         18
+  #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_UNUSED0_BB                                                      (0x1f<<19) // 
+  #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_UNUSED0_BB_SHIFT                                                19
+  #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_TL_TLDAFIFO_WADDR_BB                                            (0x3f<<24) // Current write address to the external FIFO.
+  #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_TL_TLDAFIFO_WADDR_BB_SHIFT                                      24
+#define PCIEIP_REG_PCIER_TLDA1_IND_DATA_BB                                                                   0x000c68UL //Access:RW   DataWidth:0x20   // Access to the currently referenced indirect register via ind_raddr_reg or ind_waddr_reg. Registers are more fully described in the TLDA docs. The registers are:  -- First trigger configuration registers Register 0 :: IND_TLDA_TRIG0_0TO1_MASK0 -- Trigger 0 rising edge mask bits [31:0]  Register 1 :: IND_TLDA_TRIG0_0TO1_MASK1 -- Trigger 0 rising edge mask bits [63:32]  Register 2 :: IND_TLDA_TRIG0_0TO1_MASK2 -- Trigger 0 rising edge mask bits [95:64]  Register 3 :: IND_TLDA_TRIG0_0TO1_MASK3 -- Trigger 0 rising edge mask bits [127:96]  Register 4 :: IND_TLDA_TRIG0_0TO1_MASK4 -- Trigger 0 rising edge mask bits [159:128]  Register 5 :: IND_TLDA_TRIG0_0TO1_MASK5 -- Trigger 0 rising edge mask bits [191:160]  Register 6 :: IND_TLDA_TRIG0_1TO0_MASK0 -- Trigger 0 falling edge mask bits [31:0]  Register 7 :: IND_TLDA_TRIG0_1TO0_MASK1 -- Trigger 0 falling edge mask bits [63:32]  Register 8 :: IND_TLDA_TRIG0_1TO0_MASK2 -- Trigger 0 falling edge mask bits [95:64]  Register 9 :: IND_TLDA_TRIG0_1TO0_MASK3 -- Trigger 0 falling edge mask bits [127:96]  Register 10 :: IND_TLDA_TRIG0_1TO0_MASK4 -- Trigger 0 falling edge mask bits [159:128]  Register 11 :: IND_TLDA_TRIG0_1TO0_MASK5 -- Trigger 0 falling edge mask bits [191:160]  Register 12 :: IND_TLDA_TRIG0_MATCH_MASK0 -- Trigger 0 bit match mask bits [31:0]  Register 13 :: IND_TLDA_TRIG0_MATCH_MASK1 -- Trigger 0 bit match mask bits [63:32]  Register 14 :: IND_TLDA_TRIG0_MATCH_MASK2 -- Trigger 0 bit match mask bits [95:64]  Register 15 :: IND_TLDA_TRIG0_MATCH_MASK3 -- Trigger 0 bit match mask bits [127:96]  Register 16 :: IND_TLDA_TRIG0_MATCH_MASK4 -- Trigger 0 bit match mask bits [159:128]  Register 17 :: IND_TLDA_TRIG0_MATCH_MASK5 -- Trigger 0 bit match mask bits [191:160]  Register 18 :: IND_TLDA_TRIG0_MATCH_VALUE0 -- Trigger 0 bit match value bits [31:0]  Register 19 :: IND_TLDA_TRIG0_MATCH_VALUE1 -- Trigger 0 bit match value bits [63:32]  Register 20 :: IND_TLDA_TRIG0_MATCH_VALUE2 -- Trigger 0 bit match value bits [95:64]  Register 21 :: IND_TLDA_TRIG0_MATCH_VALUE3 -- Trigger 0 bit match value bits [127:96]  Register 22 :: IND_TLDA_TRIG0_MATCH_VALUE4 -- Trigger 0 bit match value bits [159:128]  Register 23 :: IND_TLDA_TRIG0_MATCH_VALUE5 -- Trigger 0 bit match value bits [191:160]  Register 24 :: IND_TLDA_TRIG0_DATA_SELECT0 -- Bits [31:0] to select the data source for trigger 0  Register 25 :: IND_TLDA_TRIG0_DATA_SELECT1 -- Bits [63:32] to select the data source for trigger 0  Register 26 :: IND_TLDA_TRIG0_DATA_SELECT2 -- Bits [95:64] to select the data source for trigger 0  Register 27 :: IND_TLDA_TRIG0_DATA_SELECT3 -- Bits [127:96] to select the data source for trigger 0  Register 28 :: IND_TLDA_TRIG0_DATA_SELECT4 -- Bits [159:128] to select the data source for trigger 0  Register 29 :: IND_TLDA_TRIG0_DATA_SELECT5 -- Bits [191:160] to select the data source for trigger 0   -- Second trigger configuration registers Register 32 :: IND_TLDA_TRIG1_0TO1_MASK0 -- Trigger 1 rising edge mask bits [31:0]  Register 33 :: IND_TLDA_TRIG1_0TO1_MASK1 -- Trigger 1 rising edge mask bits [63:32]  Register 34 :: IND_TLDA_TRIG1_0TO1_MASK2 -- Trigger 1 rising edge mask bits [95:64]  Register 35 :: IND_TLDA_TRIG1_0TO1_MASK3 -- Trigger 1 rising edge mask bits [127:96]  Register 36 :: IND_TLDA_TRIG1_0TO1_MASK4 -- Trigger 1 rising edge mask bits [159:128]  Register 37 :: IND_TLDA_TRIG1_0TO1_MASK5 -- Trigger 1 rising edge mask bits [191:160]  Register 38 :: IND_TLDA_TRIG1_1TO0_MASK0 -- Trigger 1 falling edge mask bits [31:0]  Register 39 :: IND_TLDA_TRIG1_1TO0_MASK1 -- Trigger 1 falling edge mask bits [63:32]  Register 40 :: IND_TLDA_TRIG1_1TO0_MASK2 -- Trigger 1 falling edge mask bits [95:64]  Register 41 :: IND_TLDA_TRIG1_1TO0_MASK3 -- Trigger 1 falling edge mask bits [127:96]  Register 42 :: IND_TLDA_TRIG1_1TO0_MASK4 -- Trigger 1 falling edge mask bits [159:128]  Register 43 :: IND_TLDA_TRIG1_1TO0_MASK5 -- Trigger 1 falling edge mask bits [191:160]  Register 44 :: IND_TLDA_TRIG1_MATCH_MASK0 -- Trigger 1 bit match mask bits [31:0]  Register 45 :: IND_TLDA_TRIG1_MATCH_MASK1 -- Trigger 1 bit match mask bits [63:32]  Register 46 :: IND_TLDA_TRIG1_MATCH_MASK2 -- Trigger 1 bit match mask bits [95:64]  Register 47 :: IND_TLDA_TRIG1_MATCH_MASK3 -- Trigger 1 bit match mask bits [127:96]  Register 48 :: IND_TLDA_TRIG1_MATCH_MASK4 -- Trigger 1 bit match mask bits [159:128]  Register 49 :: IND_TLDA_TRIG1_MATCH_MASK5 -- Trigger 1 bit match mask bits [191:160]  Register 50 :: IND_TLDA_TRIG1_MATCH_VALUE0 -- Trigger 1 bit match value bits [31:0]  Register 51 :: IND_TLDA_TRIG1_MATCH_VALUE1 -- Trigger 1 bit match value bits [63:32]  Register 52 :: IND_TLDA_TRIG1_MATCH_VALUE2 -- Trigger 1 bit match value bits [95:64]  Register 53 :: IND_TLDA_TRIG1_MATCH_VALUE3 -- Trigger 1 bit match value bits [127:96]  Register 54 :: IND_TLDA_TRIG1_MATCH_VALUE4 -- Trigger 1 bit match value bits [159:128]  Register 55 :: IND_TLDA_TRIG1_MATCH_VALUE5 -- Trigger 1 bit match value bits [191:160]  Register 56 :: IND_TLDA_TRIG1_DATA_SELECT0 -- Bits [31:0] to select the data source for trigger 1  Register 57 :: IND_TLDA_TRIG1_DATA_SELECT1 -- Bits [63:32] to select the data source for trigger 1  Register 58 :: IND_TLDA_TRIG1_DATA_SELECT2 -- Bits [95:64] to select the data source for trigger 1  Register 59 :: IND_TLDA_TRIG1_DATA_SELECT3 -- Bits [127:96] to select the data source for trigger 1  Register 60 :: IND_TLDA_TRIG1_DATA_SELECT4 -- Bits [159:128] to select the data source for trigger 1  Register 61 :: IND_TLDA_TRIG1_DATA_SELECT5 -- Bits [191:160] to select the data source for trigger 1   -- Third trigger configuration registers Register 64 :: IND_TLDA_TRIG2_0TO1_MASK0 -- Trigger 2 rising edge mask bits [31:0]  Register 65 :: IND_TLDA_TRIG2_0TO1_MASK1 -- Trigger 2 rising edge mask bits [63:32]  Register 66 :: IND_TLDA_TRIG2_0TO1_MASK2 -- Trigger 2 rising edge mask bits [95:64]  Register 67 :: IND_TLDA_TRIG2_0TO1_MASK3 -- Trigger 2 rising edge mask bits [127:96]  Register 68 :: IND_TLDA_TRIG2_0TO1_MASK4 -- Trigger 2 rising edge mask bits [159:128]  Register 69 :: IND_TLDA_TRIG2_0TO1_MASK5 -- Trigger 2 rising edge mask bits [191:160]  Register 70 :: IND_TLDA_TRIG2_1TO0_MASK0 -- Trigger 2 falling edge mask bits [31:0]  Register 71 :: IND_TLDA_TRIG2_1TO0_MASK1 -- Trigger 2 falling edge mask bits [63:32]  Register 72 :: IND_TLDA_TRIG2_1TO0_MASK2 -- Trigger 2 falling edge mask bits [95:64]  Register 73 :: IND_TLDA_TRIG2_1TO0_MASK3 -- Trigger 2 falling edge mask bits [127:96]  Register 74 :: IND_TLDA_TRIG2_1TO0_MASK4 -- Trigger 2 falling edge mask bits [159:128]  Register 75 :: IND_TLDA_TRIG2_1TO0_MASK5 -- Trigger 2 falling edge mask bits [191:160]  Register 76 :: IND_TLDA_TRIG2_MATCH_MASK0 -- Trigger 2 bit match mask bits [31:0]  Register 77 :: IND_TLDA_TRIG2_MATCH_MASK1 -- Trigger 2 bit match mask bits [63:32]  Register 78 :: IND_TLDA_TRIG2_MATCH_MASK2 -- Trigger 2 bit match mask bits [95:64]  Register 79 :: IND_TLDA_TRIG2_MATCH_MASK3 -- Trigger 2 bit match mask bits [127:96]  Register 80 :: IND_TLDA_TRIG2_MATCH_MASK4 -- Trigger 2 bit match mask bits [159:128]  Register 81 :: IND_TLDA_TRIG2_MATCH_MASK5 -- Trigger 2 bit match mask bits [191:160]  Register 82 :: IND_TLDA_TRIG2_MATCH_VALUE0 -- Trigger 2 bit match value bits [31:0]  Register 83 :: IND_TLDA_TRIG2_MATCH_VALUE1 -- Trigger 2 bit match value bits [63:32]  Register 84 :: IND_TLDA_TRIG2_MATCH_VALUE2 -- Trigger 2 bit match value bits [95:64]  Register 85 :: IND_TLDA_TRIG2_MATCH_VALUE3 -- Trigger 2 bit match value bits [127:96]  Register 86 :: IND_TLDA_TRIG2_MATCH_VALUE4 -- Trigger 2 bit match value bits [159:128]  Register 87 :: IND_TLDA_TRIG2_MATCH_VALUE5 -- Trigger 2 bit match value bits [191:160]  Register 88 :: IND_TLDA_TRIG2_DATA_SELECT0 -- Bits [31:0] to select the data source for trigger 2  Register 89 :: IND_TLDA_TRIG2_DATA_SELECT1 -- Bits [63:32] to select the data source for trigger 2  Register 90 :: IND_TLDA_TRIG2_DATA_SELECT2 -- Bits [95:64] to select the data source for trigger 2  Register 91 :: IND_TLDA_TRIG2_DATA_SELECT3 -- Bits [127:96] to select the data source for trigger 2  Register 92 :: IND_TLDA_TRIG2_DATA_SELECT4 -- Bits [159:128] to select the data source for trigger 2  Register 93 :: IND_TLDA_TRIG2_DATA_SELECT5 -- Bits [191:160] to select the data source for trigger 2   -- Trigger selection and timeout configuration registers Register 96 :: IND_TLDA_TRIG_SELECT -- Selects which triggers or combination of triggers to use  Register 97 :: IND_TLDA_TRIG_TIMEOUT -- Configures timeouts for trigger actions   -- Data filtering based on rising edge in the data Register 100 :: IND_TLDA_FILTER_0TO1_MASK0 -- Data path filter rising edge mask bits [31:0]  Register 101 :: IND_TLDA_FILTER_0TO1_MASK1 -- Data path filter rising edga mask bits [63:32]  Register 102 :: IND_TLDA_FILTER_0TO1_MASK2 -- Data path filter rising edge mask bits [95:64]  Register 103 :: IND_TLDA_FILTER_0TO1_MASK3 -- Data path filter rising edge mask bits [127:96]  Register 104 :: IND_TLDA_FILTER_0TO1_MASK4 -- Data path filter rising edge mask bits [159:128]  Register 105 :: IND_TLDA_FILTER_0TO1_MASK5 -- Data path filter rising edge mask bits [191:160]  Register 106 :: IND_TLDA_FILTER_0TO1_MASK6 -- Data path filter rising edge mask bits [223:192]  Register 107 :: IND_TLDA_FILTER_0TO1_MASK7 -- Data path filter rising edge mask bits [255:224]  Register 108 :: IND_TLDA_FILTER_0TO1_MASK8 -- Data path filter rising edge mask bits [287:256]  Register 109 :: IND_TLDA_FILTER_0TO1_MASK9 -- Data path filter rising edge mask bits [319:288]   -- Data filtering based on faling edge in the data Register 110 :: IND_TLDA_FILTER_1TO0_MASK0 -- Data path filter falling edge mask bits [31:0]  Register 111 :: IND_TLDA_FILTER_1TO0_MASK1 -- Data path filter falling edga mask bits [63:32]  Register 112 :: IND_TLDA_FILTER_1TO0_MASK2 -- Data path filter falling edge mask bits [95:64]  Register 113 :: IND_TLDA_FILTER_1TO0_MASK3 -- Data path filter falling edge mask bits [127:96]  Register 114 :: IND_TLDA_FILTER_1TO0_MASK4 -- Data path filter falling edge mask bits [159:128]  Register 115 :: IND_TLDA_FILTER_1TO0_MASK5 -- Data path filter falling edge mask bits [191:160]  Register 116 :: IND_TLDA_FILTER_1TO0_MASK6 -- Data path filter falling edge mask bits [223:192]  Register 117 :: IND_TLDA_FILTER_1TO0_MASK7 -- Data path filter falling edge mask bits [255:224]  Register 118 :: IND_TLDA_FILTER_1TO0_MASK8 -- Data path filter falling edge mask bits [287:256]  Register 119 :: IND_TLDA_FILTER_1TO0_MASK9 -- Data path filter falling edge mask bits [319:288]   -- Data filtering based on matching (masked) value in the data Register 120 :: IND_TLDA_FILTER_MATCH0_MASK0 -- Data path filter match-0 mask bits [31:0]  Register 121 :: IND_TLDA_FILTER_MATCH0_MASK1 -- Data path filter match-0 mask bits [63:32]  Register 122 :: IND_TLDA_FILTER_MATCH0_MASK2 -- Data path filter match-0 mask bits [95:64]  Register 123 :: IND_TLDA_FILTER_MATCH0_MASK3 -- Data path filter match-0 mask bits [127:96]  Register 124 :: IND_TLDA_FILTER_MATCH0_MASK4 -- Data path filter match-0 mask bits [159:128]  Register 125 :: IND_TLDA_FILTER_MATCH0_MASK5 -- Data path filter match-0 mask bits [191:160]  Register 126 :: IND_TLDA_FILTER_MATCH0_MASK6 -- Data path filter match-0 mask bits [223:192]  Register 127 :: IND_TLDA_FILTER_MATCH0_MASK7 -- Data path filter match-0 mask bits [255:224]  Register 128 :: IND_TLDA_FILTER_MATCH0_MASK8 -- Data path filter match-0 mask bits [287:256]  Register 129 :: IND_TLDA_FILTER_MATCH0_MASK9 -- Data path filter match-0 mask bits [319:288]  Register 130 :: IND_TLDA_FILTER_MATCH0_VALUE0 -- Data path filter match-0 value bits [31:0]  Register 131 :: IND_TLDA_FILTER_MATCH0_VALUE1 -- Data path filter match-0 value bits [63:32]  Register 132 :: IND_TLDA_FILTER_MATCH0_VALUE2 -- Data path filter match-0 value bits [95:64]  Register 133 :: IND_TLDA_FILTER_MATCH0_VALUE3 -- Data path filter match-0 value bits [127:96]  Register 134 :: IND_TLDA_FILTER_MATCH0_VALUE4 -- Data path filter match-0 value bits [159:128]  Register 135 :: IND_TLDA_FILTER_MATCH0_VALUE5 -- Data path filter match-0 value bits [191:160]  Register 136 :: IND_TLDA_FILTER_MATCH0_VALUE6 -- Data path filter match-0 value bits [223:192]  Register 137 :: IND_TLDA_FILTER_MATCH0_VALUE7 -- Data path filter match-0 value bits [255:224]  Register 138 :: IND_TLDA_FILTER_MATCH0_VALUE8 -- Data path filter match-0 value bits [287:256]  Register 139 :: IND_TLDA_FILTER_MATCH0_VALUE9 -- Data path filter match-0 value bits [319:288]  Register 140 :: IND_TLDA_FILTER_MATCH1_MASK0 -- Data path filter match-1 mask bits [31:0]  Register 141 :: IND_TLDA_FILTER_MATCH1_MASK1 -- Data path filter match-1 mask bits [63:32]  Register 142 :: IND_TLDA_FILTER_MATCH1_MASK2 -- Data path filter match-1 mask bits [95:64]  Register 143 :: IND_TLDA_FILTER_MATCH1_MASK3 -- Data path filter match-1 mask bits [127:96]  Register 144 :: IND_TLDA_FILTER_MATCH1_MASK4 -- Data path filter match-1 mask bits [159:128]  Register 145 :: IND_TLDA_FILTER_MATCH1_MASK5 -- Data path filter match-1 mask bits [191:160]  Register 146 :: IND_TLDA_FILTER_MATCH1_MASK6 -- Data path filter match-1 mask bits [223:192]  Register 147 :: IND_TLDA_FILTER_MATCH1_MASK7 -- Data path filter match-1 mask bits [255:224]  Register 148 :: IND_TLDA_FILTER_MATCH1_MASK8 -- Data path filter match-1 mask bits [287:256]  Register 149 :: IND_TLDA_FILTER_MATCH1_MASK9 -- Data path filter match-1 mask bits [319:288]  Register 150 :: IND_TLDA_FILTER_MATCH1_VALUE0 -- Data path filter match-1 value bits [31:0]  Register 151 :: IND_TLDA_FILTER_MATCH1_VALUE1 -- Data path filter match-1 value bits [63:32]  Register 152 :: IND_TLDA_FILTER_MATCH1_VALUE2 -- Data path filter match-1 value bits [95:64]  Register 153 :: IND_TLDA_FILTER_MATCH1_VALUE3 -- Data path filter match-1 value bits [127:96]  Register 154 :: IND_TLDA_FILTER_MATCH1_VALUE4 -- Data path filter match-1 value bits [159:128]  Register 155 :: IND_TLDA_FILTER_MATCH1_VALUE5 -- Data path filter match-1 value bits [191:160]  Register 156 :: IND_TLDA_FILTER_MATCH1_VALUE6 -- Data path filter match-1 value bits [223:192]  Register 157 :: IND_TLDA_FILTER_MATCH1_VALUE7 -- Data path filter match-1 value bits [255:224]  Register 158 :: IND_TLDA_FILTER_MATCH1_VALUE8 -- Data path filter match-1 value bits [287:256]  Register 159 :: IND_TLDA_FILTER_MATCH1_VALUE9 -- Data path filter match-1 value bits [319:288]   Register 160 :: IND_TLDA_FILTER_SELECT -- Select the combinations of data filtering to use  Register 161 :: IND_TLDA_DATA_SELECT0 -- Bits [31:0] to select the data source  Register 162 :: IND_TLDA_DATA_SELECT1 -- Bits [63:32] to select the data source  Register 163 :: IND_TLDA_DATA_SELECT2 -- Bits [95:64] to select the data source  Register 164 :: IND_TLDA_DATA_SELECT3 -- Bits [127:96] to select the data source  Register 165 :: IND_TLDA_DATA_SELECT4 -- Bits [159:128] to select the data source  Register 166 :: IND_TLDA_DATA_SELECT5 -- Bits [191:160] to select the data source   Register 169 :: IND_TLDA_TIME_SELECT -- Select the time stamp to include in the data   Register 170 :: IND_TLDA_PREDEF_DATASEL -- Configure on of the preselected data source combinations   Register 171 :: IND_TLDA_EVENT_SEL -- Select the events to watch  Register 172 :: IND_TLDA_EVENT_CFG0 -- Configure the first set of event actions (counting, thresholds, etc)  Register 173 :: IND_TLDA_EVENT_CFG1 -- Configure the second set of event actions (counting, thresholds, etc)   Register 192 :: IND_TLDA_SPARE_DBG0 -- Spare debug register  Register 193 :: IND_TLDA_SPARE_DBG1 -- Spare debug register   If accessing an unimplemented register, the value 0xbadaddee will be returned.
+#define PCIEIP_REG_PCIER_TLDA1_RDFIFO_4_BB                                                                   0x000c6cUL //Access:R    DataWidth:0x20   // The five read registers give a total of 160 bits of data from the FIFO. The FIFO is read when PCIER_TLDA1_RDFIFO_4 is read every other time. Also, on the opposite reads of PCIER_TLDA1_RDFIFO_4, the data in these registers is advanced to the next half of the FIFO data. So when the first PCIER_TLDA1_RDFIFO_4 read occurs, data is read from the FIFO and bits [159:0] are in these registers. Next read of PCIER_TLDA1_RDFIFO_4, bits [319:160] are in these registers. If the FIFO location is not used, each register will read 0xbaddf1f0.
+#define PCIEIP_REG_PCIER_TLDA1_RDFIFO_3_BB                                                                   0x000c70UL //Access:R    DataWidth:0x20   // Bits [127:96] of the current half-data from the second FIFO
+#define PCIEIP_REG_PCIER_TLDA1_RDFIFO_2_BB                                                                   0x000c74UL //Access:R    DataWidth:0x20   // Bits [95:64] of the current half-data from the second FIFO
+#define PCIEIP_REG_PCIER_TLDA1_RDFIFO_1_BB                                                                   0x000c78UL //Access:R    DataWidth:0x20   // Bits [63:32] of the current half-data from the second FIFO
+#define PCIEIP_REG_PCIER_TLDA1_RDFIFO_0_BB                                                                   0x000c7cUL //Access:R    DataWidth:0x20   // Bits [31:0] of the current half-data from the second FIFO
+#define PCIEIP_REG_PDL_CONTROL_0_BB                                                                          0x001000UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PDL_CONTROL_0_ENA_SCRAM_BB                                                              (0x1<<0) // PHY: Enable Scrambler. Default for FPGA is 0
+  #define PCIEIP_REG_PDL_CONTROL_0_ENA_SCRAM_BB_SHIFT                                                        0
+  #define PCIEIP_REG_PDL_CONTROL_0_DIS_INV_POLARITY_BB                                                       (0x1<<1) // PHY: Disable Inverse Polarity. Setting this bit to '1' disables the polarity inversion regardless of what hardware detects during the training.
+  #define PCIEIP_REG_PDL_CONTROL_0_DIS_INV_POLARITY_BB_SHIFT                                                 1
+  #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_REPLAY_TIMER_BB                                                   (0x1<<2) // DL: Disable Replay Timer. In effect, REPLAY only occurs when NACK DLLP is received.
+  #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_REPLAY_TIMER_BB_SHIFT                                             2
+  #define PCIEIP_REG_PDL_CONTROL_0_RESERVED_3_BB                                                             (0x1<<3) // 
+  #define PCIEIP_REG_PDL_CONTROL_0_RESERVED_3_BB_SHIFT                                                       3
+  #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_CRC_DLL_BB                                                        (0x1<<4) // DL: Disable CRC check for incoming DLLP packets
+  #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_CRC_DLL_BB_SHIFT                                                  4
+  #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_CRC_DLP_BB                                                        (0x1<<5) // DL: Disable CRC check for incoming TLP packets
+  #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_CRC_DLP_BB_SHIFT                                                  5
+  #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_REPLAY_BUFF_BB                                                    (0x1<<6) // DL: If set, REPLAY EMPTY will be asserted.
+  #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_REPLAY_BUFF_BB_SHIFT                                              6
+  #define PCIEIP_REG_PDL_CONTROL_0_RESERVED_9_7_BB                                                           (0x7<<7) // 
+  #define PCIEIP_REG_PDL_CONTROL_0_RESERVED_9_7_BB_SHIFT                                                     7
+  #define PCIEIP_REG_PDL_CONTROL_0_DIS_ELECIDLE_RETRAIN_BB                                                   (0x1<<10) // PHY: Disable Electrical Idle Retrain. Setting this bit to '1' prevents link from doing retrain if either inferred electrical idle occurs or signal is not detected on all lanes while in L0 or RxL0s.
+  #define PCIEIP_REG_PDL_CONTROL_0_DIS_ELECIDLE_RETRAIN_BB_SHIFT                                             10
+  #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_AUTO_CRDUPD_BB                                                    (0x1<<11) // DL: Disable Auto Credit Update. If this bit is set to '1', DL will not automatically generate UpdateFC every 30us (or 120 us if Ext Sync is set)
+  #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_AUTO_CRDUPD_BB_SHIFT                                              11
+  #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_RETRAIN_REQ_BB                                                    (0x1<<12) // DL:Disable hardware from triggering link retraining due to Replay timer roll over, Replay timeout, or detecting maximum number of correctable errors.
+  #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_RETRAIN_REQ_BB_SHIFT                                              12
+  #define PCIEIP_REG_PDL_CONTROL_0_FORCE_L0TOL1_BB                                                           (0x1<<13) // DL: Force L0 to L1. When this bit is set to '1', DL will send PM_Enter_L1 DLLP to link partner.
+  #define PCIEIP_REG_PDL_CONTROL_0_FORCE_L0TOL1_BB_SHIFT                                                     13
+  #define PCIEIP_REG_PDL_CONTROL_0_RESERVED_22_14_BB                                                         (0x1ff<<14) // 
+  #define PCIEIP_REG_PDL_CONTROL_0_RESERVED_22_14_BB_SHIFT                                                   14
+  #define PCIEIP_REG_PDL_CONTROL_0_FORCE_RCVR_DETECT_ALL_BB                                                  (0x1<<23) // PHY: Force Receiver Detect All. When this bit is set to '1', internal Receiver Detected signals are forced to '1' as if link partner receiver has been detected for all lanes.
+  #define PCIEIP_REG_PDL_CONTROL_0_FORCE_RCVR_DETECT_ALL_BB_SHIFT                                            23
+  #define PCIEIP_REG_PDL_CONTROL_0_RESERVED_26_24_BB                                                         (0x7<<24) // 
+  #define PCIEIP_REG_PDL_CONTROL_0_RESERVED_26_24_BB_SHIFT                                                   24
+  #define PCIEIP_REG_PDL_CONTROL_0_FORCE_L0TOL2_BB                                                           (0x1<<27) // DL: Force L0 to L2. When this bit is set to '1', DL will send PM_Enter_L23 DLLP to link partner.
+  #define PCIEIP_REG_PDL_CONTROL_0_FORCE_L0TOL2_BB_SHIFT                                                     27
+  #define PCIEIP_REG_PDL_CONTROL_0_DIS_HOT_RESET_BB                                                          (0x1<<28) // PHY: Disable Hot Reset.
+  #define PCIEIP_REG_PDL_CONTROL_0_DIS_HOT_RESET_BB_SHIFT                                                    28
+  #define PCIEIP_REG_PDL_CONTROL_0_RESERVED_30_29_BB                                                         (0x3<<29) // 
+  #define PCIEIP_REG_PDL_CONTROL_0_RESERVED_30_29_BB_SHIFT                                                   29
+  #define PCIEIP_REG_PDL_CONTROL_0_DIRECT_RECOV_TO_CONFIG_BB                                                 (0x1<<31) // PHY: Direct Recovery to Configuration State. When this bit is set to '1', LTSSM is directed to transition from Recovery.Idle to Configuration state.
+  #define PCIEIP_REG_PDL_CONTROL_0_DIRECT_RECOV_TO_CONFIG_BB_SHIFT                                           31
+#define PCIEIP_REG_PDL_CONTROL_1_BB                                                                          0x001004UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PDL_CONTROL_1_MAX_DLP_IDLE_CNT_BB                                                       (0x7f<<0) // DL: This field specifies the time that DL doesn't have any TLP/DLLP to transmit before DL requests PL to enter L0s. The actual time is equal to (MAX_DLP_IDLE_CNT * 128ns).
+  #define PCIEIP_REG_PDL_CONTROL_1_MAX_DLP_IDLE_CNT_BB_SHIFT                                                 0
+  #define PCIEIP_REG_PDL_CONTROL_1_SW_UPDFC_P_LAT_SEL_BB                                                     (0x1<<7) // When this bit is set, the software value will be used for UpdateFC Latency of Posted credit.
+  #define PCIEIP_REG_PDL_CONTROL_1_SW_UPDFC_P_LAT_SEL_BB_SHIFT                                               7
+  #define PCIEIP_REG_PDL_CONTROL_1_UNUSED_3_BB                                                               (0x1<<8) // Reserved
+  #define PCIEIP_REG_PDL_CONTROL_1_UNUSED_3_BB_SHIFT                                                         8
+  #define PCIEIP_REG_PDL_CONTROL_1_SW_UPDFC_NP_LAT_SEL_BB                                                    (0x1<<9) // When this bit is set, the software value will be used for UpdateFC Latency of Non-Posted credit.
+  #define PCIEIP_REG_PDL_CONTROL_1_SW_UPDFC_NP_LAT_SEL_BB_SHIFT                                              9
+  #define PCIEIP_REG_PDL_CONTROL_1_DIS_NAK_RST_TMR_BB                                                        (0x1<<10) // DL: When this bit is set to '1', Replay Timer will not be reset if a NAK is received during a Replay operation. While not in Replay, a NAK always resets the timer regardless of the setting of this bit.
+  #define PCIEIP_REG_PDL_CONTROL_1_DIS_NAK_RST_TMR_BB_SHIFT                                                  10
+  #define PCIEIP_REG_PDL_CONTROL_1_FORCE_TX_L0S_BB                                                           (0x1<<11) // PHY: Force to TX L0s. Setting this bit to '1' forces LTSSM to enter TX L0s state.
+  #define PCIEIP_REG_PDL_CONTROL_1_FORCE_TX_L0S_BB_SHIFT                                                     11
+  #define PCIEIP_REG_PDL_CONTROL_1_MAX_REPLAY_NUM_BB                                                         (0x3<<12) // DL: Maximum times Replay must be repeated before DL triggers link retrains
+  #define PCIEIP_REG_PDL_CONTROL_1_MAX_REPLAY_NUM_BB_SHIFT                                                   12
+  #define PCIEIP_REG_PDL_CONTROL_1_RETRAIN_REQ_BB                                                            (0x1<<14) // This initiates Link re-training by directing PHY LTSSM to recovery state. It is a pulse, so reading this bit always returns '0'.
+  #define PCIEIP_REG_PDL_CONTROL_1_RETRAIN_REQ_BB_SHIFT                                                      14
+  #define PCIEIP_REG_PDL_CONTROL_1_UNUSED_1_BB                                                               (0x1<<15) // Reserved
+  #define PCIEIP_REG_PDL_CONTROL_1_UNUSED_1_BB_SHIFT                                                         15
+  #define PCIEIP_REG_PDL_CONTROL_1_MAX_DLP_L1_ENTRANCE_BB                                                    (0x7f<<16) // DL: This field specifies the time DL must wait before initiating ASPM L1 request. If L0s is enabled, it is the time link is in L0s. If L0s is not enabled, it is the time link doesn't have any activity. The actual time is equal to (MAX_DLP_L1_ENTRANCE * 256ns).
+  #define PCIEIP_REG_PDL_CONTROL_1_MAX_DLP_L1_ENTRANCE_BB_SHIFT                                              16
+  #define PCIEIP_REG_PDL_CONTROL_1_ASPM_L1_GAP_BB                                                            (0x7f<<23) // DL: After an ASPM L1 request is rejected by RC, if EP doesn't enter L0s, this field specifies the gap time before EP can initiate the next ASPM L1 request. The actual time is equal to (ASPM_L1_GAP * 256ns).
+  #define PCIEIP_REG_PDL_CONTROL_1_ASPM_L1_GAP_BB_SHIFT                                                      23
+  #define PCIEIP_REG_PDL_CONTROL_1_INT_ASPM_L1_ENA_BB                                                        (0x1<<30) // Internal ASPM L1 Enable. When this bit is set to '1', hardware autonomously control ASPM L1 by monitoring link activities. Signal user_early_l1_exit also works in this mode.
+  #define PCIEIP_REG_PDL_CONTROL_1_INT_ASPM_L1_ENA_BB_SHIFT                                                  30
+  #define PCIEIP_REG_PDL_CONTROL_1_EXT_ASPM_L1_ENA_BB                                                        (0x1<<31) // External ASPM L1 Enable. When this bit is set to '1', user can directly control when to enter ASPM L1 using signal user_l1_enter. Actual L1 entering is contingent to link activities. If user_early_l1_exit is also set, it overrides user_l1_enter signal.
+  #define PCIEIP_REG_PDL_CONTROL_1_EXT_ASPM_L1_ENA_BB_SHIFT                                                  31
+#define PCIEIP_REG_PDL_CONTROL_2_BB                                                                          0x001008UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PDL_CONTROL_2_SEL_SOS_INTERVAL_BB                                                       (0x3<<0) // PHY: Select SKP OS interval. This field selects the interval for SKP ordered set transmitting.
+  #define PCIEIP_REG_PDL_CONTROL_2_SEL_SOS_INTERVAL_BB_SHIFT                                                 0
+  #define PCIEIP_REG_PDL_CONTROL_2_DIS_SOS_INTERVAL_BB                                                       (0x1<<2) // PHY: Disable SKP OS. When this bit is set to '1', periodic SKP OS transmitting is disabled.
+  #define PCIEIP_REG_PDL_CONTROL_2_DIS_SOS_INTERVAL_BB_SHIFT                                                 2
+  #define PCIEIP_REG_PDL_CONTROL_2_ENABLE_ACK_LAT_TIMER_BB                                                   (0x1<<3) // DL: If set, it will enable ACK Latency Timer. In this case, DL ACK or NACK requests are only sent out when timer reaches MAX_ACK_LAT_TIMER. When this timer is disabled, ACK/NACK requests will be sent to PCIE bus as soon as they are asserted.
+  #define PCIEIP_REG_PDL_CONTROL_2_ENABLE_ACK_LAT_TIMER_BB_SHIFT                                             3
+  #define PCIEIP_REG_PDL_CONTROL_2_SW_ACK_LAT_SEL_BB                                                         (0x1<<4) // If set, override hardwired value with the programmable ACK Latency timer. HW will select programmable value depending on whether PHY operates in gen 1or gen2. The programmable register for ACK LAT is at address 0x1034
+  #define PCIEIP_REG_PDL_CONTROL_2_SW_ACK_LAT_SEL_BB_SHIFT                                                   4
+  #define PCIEIP_REG_PDL_CONTROL_2_SW_REPLAY_TIMER_SEL_BB                                                    (0x1<<5) // If set, override hardwired value with programmable REPLAY timer. HW will select programmable value depending on whether PHY operates in gen 1or gen2. The programmable REPLAY register is at address 0x102C
+  #define PCIEIP_REG_PDL_CONTROL_2_SW_REPLAY_TIMER_SEL_BB_SHIFT                                              5
+  #define PCIEIP_REG_PDL_CONTROL_2_RESERVED_7_6_BB                                                           (0x3<<6) // 
+  #define PCIEIP_REG_PDL_CONTROL_2_RESERVED_7_6_BB_SHIFT                                                     6
+  #define PCIEIP_REG_PDL_CONTROL_2_L0SL1L2_WAIT_FOR_IDLE_BB                                                  (0xf<<8) // PHY: RxL0s, L1, L2 Wait For Idle. This field specifies the minimum number of clock cycles that LTSSM will stay in RxL0s, L1, L2 Idle state before exiting because of signal detection.
+  #define PCIEIP_REG_PDL_CONTROL_2_L0SL1L2_WAIT_FOR_IDLE_BB_SHIFT                                            8
+  #define PCIEIP_REG_PDL_CONTROL_2_RESERVED_15_12_BB                                                         (0xf<<12) // 
+  #define PCIEIP_REG_PDL_CONTROL_2_RESERVED_15_12_BB_SHIFT                                                   12
+  #define PCIEIP_REG_PDL_CONTROL_2_ENABLE_CRD_LAT_P_BB                                                       (0x1<<16) // DL: Enable Posted Latency Timer. If this timer reaches MAX_ACK_LAT_TIMER value, DL will send out FC update for Posted
+  #define PCIEIP_REG_PDL_CONTROL_2_ENABLE_CRD_LAT_P_BB_SHIFT                                                 16
+  #define PCIEIP_REG_PDL_CONTROL_2_ENABLE_CRD_LAT_N_BB                                                       (0x1<<17) // DL: Enable Non-Posted Latency Timer. If this timer reaches MAX_ACK_LAT_TIMER value, DL will send out FC update for Non-Posted
+  #define PCIEIP_REG_PDL_CONTROL_2_ENABLE_CRD_LAT_N_BB_SHIFT                                                 17
+  #define PCIEIP_REG_PDL_CONTROL_2_CORR_ERR_REG_MAX_BB                                                       (0x3ff<<18) // DL: Maximum Correctable Errors that DL must detect within an 256us interval before asserting Correctable Error flag in DLATTN_VEC register.
+  #define PCIEIP_REG_PDL_CONTROL_2_CORR_ERR_REG_MAX_BB_SHIFT                                                 18
+#define PCIEIP_REG_PDL_CONTROL_3_BB                                                                          0x00100cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PDL_CONTROL_3_MAX_TX_FTS_LIMIT_BB                                                       (0xff<<0) // PHY
+  #define PCIEIP_REG_PDL_CONTROL_3_MAX_TX_FTS_LIMIT_BB_SHIFT                                                 0
+  #define PCIEIP_REG_PDL_CONTROL_3_MAX_TX_FTS_LIMIT_LONG_BB                                                  (0xff<<8) // PHY
+  #define PCIEIP_REG_PDL_CONTROL_3_MAX_TX_FTS_LIMIT_LONG_BB_SHIFT                                            8
+  #define PCIEIP_REG_PDL_CONTROL_3_MAX_TX_FTS_LIMIT_GEN2_BB                                                  (0xff<<16) // PHY
+  #define PCIEIP_REG_PDL_CONTROL_3_MAX_TX_FTS_LIMIT_GEN2_BB_SHIFT                                            16
+  #define PCIEIP_REG_PDL_CONTROL_3_MAX_TX_FTS_LIMIT_LONG_GEN2_BB                                             (0xff<<24) // PHY
+  #define PCIEIP_REG_PDL_CONTROL_3_MAX_TX_FTS_LIMIT_LONG_GEN2_BB_SHIFT                                       24
+#define PCIEIP_REG_PDL_CONTROL_4_BB                                                                          0x001010UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PDL_CONTROL_4_NPD_FC_INIT_BB                                                            (0xfff<<0) // DL: Non-Posted Data for INITFC
+  #define PCIEIP_REG_PDL_CONTROL_4_NPD_FC_INIT_BB_SHIFT                                                      0
+  #define PCIEIP_REG_PDL_CONTROL_4_PD_FC_INIT_BB                                                             (0xfff<<12) // DL: Posted Data for INITFC
+  #define PCIEIP_REG_PDL_CONTROL_4_PD_FC_INIT_BB_SHIFT                                                       12
+  #define PCIEIP_REG_PDL_CONTROL_4_NPH_FC_INIT_BB                                                            (0xff<<24) // DL: Non Posted Header for INITFC
+  #define PCIEIP_REG_PDL_CONTROL_4_NPH_FC_INIT_BB_SHIFT                                                      24
+#define PCIEIP_REG_PDL_CONTROL_5_BB                                                                          0x001014UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PDL_CONTROL_5_PH_INIT_BB                                                                (0xff<<0) // DL: Posted Header for INITFC
+  #define PCIEIP_REG_PDL_CONTROL_5_PH_INIT_BB_SHIFT                                                          0
+  #define PCIEIP_REG_PDL_CONTROL_5_DOWNSTREAM_PORT_BB                                                        (0x1<<8) // This bit is set to '1' if IP is configured as a Downstream Port.
+  #define PCIEIP_REG_PDL_CONTROL_5_DOWNSTREAM_PORT_BB_SHIFT                                                  8
+  #define PCIEIP_REG_PDL_CONTROL_5_GLOOPBACK_BB                                                              (0x1<<9) // 
+  #define PCIEIP_REG_PDL_CONTROL_5_GLOOPBACK_BB_SHIFT                                                        9
+  #define PCIEIP_REG_PDL_CONTROL_5_MIN_INITFC1_BB                                                            (0xf<<10) // DL: Minimum number of InitFC1 sets (i.e. P, NP, CPL) that DL will send before switching to InitFC2.
+  #define PCIEIP_REG_PDL_CONTROL_5_MIN_INITFC1_BB_SHIFT                                                      10
+  #define PCIEIP_REG_PDL_CONTROL_5_UNUSED_1_BB                                                               (0x3ffff<<14) // Reserved
+  #define PCIEIP_REG_PDL_CONTROL_5_UNUSED_1_BB_SHIFT                                                         14
+#define PCIEIP_REG_PDL_CONTROL_6_BB                                                                          0x001018UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PDL_CONTROL_6_REG_ADV_NFTS_COMNCLK_GEN3_BB                                              (0xff<<0) // Gen3 N_FTS value advertised when in common clock mode.
+  #define PCIEIP_REG_PDL_CONTROL_6_REG_ADV_NFTS_COMNCLK_GEN3_BB_SHIFT                                        0
+  #define PCIEIP_REG_PDL_CONTROL_6_REG_ADV_NFTS_DIFFCLK_GEN3_BB                                              (0xff<<8) // Gen3 N_FTS value advertised when not in common clock mode.
+  #define PCIEIP_REG_PDL_CONTROL_6_REG_ADV_NFTS_DIFFCLK_GEN3_BB_SHIFT                                        8
+  #define PCIEIP_REG_PDL_CONTROL_6_UNUSED_1_BB                                                               (0xffff<<16) // Reserved - always write 0
+  #define PCIEIP_REG_PDL_CONTROL_6_UNUSED_1_BB_SHIFT                                                         16
+#define PCIEIP_REG_DL_REPLAY_TIMER_GEN3_BB                                                                   0x00101cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DL_REPLAY_TIMER_GEN3_SW_REPLAY_TIMER_GEN3_BB                                            (0xfff<<0) // Software Gen3 value for the replay timeout in symbol time. It is selected if bit sw_replay_timer_sel is set to '1'; otherwise, the hardware-calculated value is selected.
+  #define PCIEIP_REG_DL_REPLAY_TIMER_GEN3_SW_REPLAY_TIMER_GEN3_BB_SHIFT                                      0
+  #define PCIEIP_REG_DL_REPLAY_TIMER_GEN3_HW_REPLAY_INTDEL_GEN3_BB                                           (0x1ff<<12) // Hardware Gen3 internal delay for the replay timeout in symbol time. This delay is only applied to the hardware-calculated replay timeout.
+  #define PCIEIP_REG_DL_REPLAY_TIMER_GEN3_HW_REPLAY_INTDEL_GEN3_BB_SHIFT                                     12
+  #define PCIEIP_REG_DL_REPLAY_TIMER_GEN3_UNUSED_1_BB                                                        (0x7ff<<21) // Reserved - always write 0
+  #define PCIEIP_REG_DL_REPLAY_TIMER_GEN3_UNUSED_1_BB_SHIFT                                                  21
+#define PCIEIP_REG_DL_ACK_LAT_GEN3_BB                                                                        0x001020UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DL_ACK_LAT_GEN3_SW_ACK_LAT_GEN3_BB                                                      (0xfff<<0) // Software Gen3 AckNak latency timer value in symbol time.
+  #define PCIEIP_REG_DL_ACK_LAT_GEN3_SW_ACK_LAT_GEN3_BB_SHIFT                                                0
+  #define PCIEIP_REG_DL_ACK_LAT_GEN3_HW_ACK_LAT_ADJ_GEN3_BB                                                  (0xff<<12) // Hardware Gen3 AckNak latency adjustment in symbol time. Depending on speed and Max Packet Size (MPS), hardware automatically generates an ACK latency according to the table in PCIE spec. Since the actual internal delay of the design is larger than the spec internal delay, this adjustment is subtracted out from the hardware-calculated value so that the real Ack latency is close to the value in spec.
+  #define PCIEIP_REG_DL_ACK_LAT_GEN3_HW_ACK_LAT_ADJ_GEN3_BB_SHIFT                                            12
+  #define PCIEIP_REG_DL_ACK_LAT_GEN3_SW_UPDFC_LAT_GEN3_BB                                                    (0xfff<<20) // Software Gen3 UpdateFC latency value in symbol time.
+  #define PCIEIP_REG_DL_ACK_LAT_GEN3_SW_UPDFC_LAT_GEN3_BB_SHIFT                                              20
+#define PCIEIP_REG_DL_REPLAY_TIMER_GEN1_BB                                                                   0x001024UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DL_REPLAY_TIMER_GEN1_SW_REPLAY_TIMER_GEN1_BB                                            (0xfff<<0) // Software Gen1 value for the replay timeout in symbol time. It is selected if bit sw_replay_timer_sel is set to '1'; otherwise, the hardware-calculated value is selected.
+  #define PCIEIP_REG_DL_REPLAY_TIMER_GEN1_SW_REPLAY_TIMER_GEN1_BB_SHIFT                                      0
+  #define PCIEIP_REG_DL_REPLAY_TIMER_GEN1_HW_REPLAY_INTDEL_GEN1_BB                                           (0x1ff<<12) // Hardware Gen1 internal delay for the replay timeout in symbol time. This delay is only applied to the hardware-calculated replay timeout.
+  #define PCIEIP_REG_DL_REPLAY_TIMER_GEN1_HW_REPLAY_INTDEL_GEN1_BB_SHIFT                                     12
+#define PCIEIP_REG_PDL_CONTROL_10_BB                                                                         0x001028UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PDL_CONTROL_10_UNUSED0_BB                                                               (0xff<<0) // 
+  #define PCIEIP_REG_PDL_CONTROL_10_UNUSED0_BB_SHIFT                                                         0
+  #define PCIEIP_REG_PDL_CONTROL_10_DL_CS_RXENABLE_BB                                                        (0x1<<8) // Enable checksum feature on receiving side
+  #define PCIEIP_REG_PDL_CONTROL_10_DL_CS_RXENABLE_BB_SHIFT                                                  8
+  #define PCIEIP_REG_PDL_CONTROL_10_DL_CS_ENABLE_BB                                                          (0x1<<9) // Enable checksum feature on transmit side
+  #define PCIEIP_REG_PDL_CONTROL_10_DL_CS_ENABLE_BB_SHIFT                                                    9
+  #define PCIEIP_REG_PDL_CONTROL_10_DL_CS_WRITE_NULLIFY_BB                                                   (0x1<<10) // DL: If set and DL has detected checksum error earlier, DL will nullify all subsequence memory write request whose pcie_cksum_err bit is not set.
+  #define PCIEIP_REG_PDL_CONTROL_10_DL_CS_WRITE_NULLIFY_BB_SHIFT                                             10
+  #define PCIEIP_REG_PDL_CONTROL_10_DL_CS_NULLIFY_BB                                                         (0x1<<11) // If set DL will nullify the first packet with bad checksum. Subsequent MWR packets will get nullified if DL_CS_WRITE_NULLIFY is set, regardless if they have bad or good checksum If this bit is clear and checksum mismatch occurs, Error attention will be set, but no packet will get nullified.
+  #define PCIEIP_REG_PDL_CONTROL_10_DL_CS_NULLIFY_BB_SHIFT                                                   11
+  #define PCIEIP_REG_PDL_CONTROL_10_DL_LO_WATERMARK_BB                                                       (0x3ff<<12) // If DLP2TLP buffer fills up to the high water mark value, DL will send a flag to TL restraining it from sending more Posted FC updates, potentially stall DMA requests, until the buffer falls below the Low watermark level.
+  #define PCIEIP_REG_PDL_CONTROL_10_DL_LO_WATERMARK_BB_SHIFT                                                 12
+  #define PCIEIP_REG_PDL_CONTROL_10_DL_HI_WATERMARK_BB                                                       (0x3ff<<22) // If DLP2TLP buffer fills up to this high water mark value, DL will send a flag to TL restraining it from sending more Posted FC updates , potentially stall DMA requests, until the flag de-asserted.
+  #define PCIEIP_REG_PDL_CONTROL_10_DL_HI_WATERMARK_BB_SHIFT                                                 22
+#define PCIEIP_REG_DL_REPLAY_TIMER_GEN2_BB                                                                   0x00102cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DL_REPLAY_TIMER_GEN2_SW_REPLAY_TIMER_GEN2_BB                                            (0xfff<<0) // Software Gen2 value for the replay timeout in symbol time. It is selected if bit sw_replay_timer_sel is set to '1'; otherwise, the hardware-calculated value is selected.
+  #define PCIEIP_REG_DL_REPLAY_TIMER_GEN2_SW_REPLAY_TIMER_GEN2_BB_SHIFT                                      0
+  #define PCIEIP_REG_DL_REPLAY_TIMER_GEN2_HW_REPLAY_INTDEL_GEN2_BB                                           (0x1ff<<12) // Hardware Gen2 internal delay for the replay timeout in symbol time. This delay is only applied to the hardware-calculated replay timeout.
+  #define PCIEIP_REG_DL_REPLAY_TIMER_GEN2_HW_REPLAY_INTDEL_GEN2_BB_SHIFT                                     12
+#define PCIEIP_REG_DL_ACK_LAT_GEN1_BB                                                                        0x001030UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DL_ACK_LAT_GEN1_SW_ACK_LAT_GEN1_BB                                                      (0xfff<<0) // Software Gen1 AckNak latency timer value in symbol time.
+  #define PCIEIP_REG_DL_ACK_LAT_GEN1_SW_ACK_LAT_GEN1_BB_SHIFT                                                0
+  #define PCIEIP_REG_DL_ACK_LAT_GEN1_HW_ACK_LAT_ADJ_GEN1_BB                                                  (0xff<<12) // Hardware Gen1 AckNak latency adjustment in symbol time. Depending on speed and Max Packet Size (MPS), hardware automatically generates an ACK latency according to the table in PCIE spec. Since the actual internal delay of the design is larger than the spec internal delay, this adjustment is subtracted out from the hardware-calculated value so that the real Ack latency is close to the value in spec.
+  #define PCIEIP_REG_DL_ACK_LAT_GEN1_HW_ACK_LAT_ADJ_GEN1_BB_SHIFT                                            12
+  #define PCIEIP_REG_DL_ACK_LAT_GEN1_SW_UPDFC_LAT_GEN1_BB                                                    (0xfff<<20) // Software Gen1 UpdateFC latency value in symbol time.
+  #define PCIEIP_REG_DL_ACK_LAT_GEN1_SW_UPDFC_LAT_GEN1_BB_SHIFT                                              20
+#define PCIEIP_REG_DL_ACK_LAT_GEN2_BB                                                                        0x001034UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DL_ACK_LAT_GEN2_SW_ACK_LAT_GEN2_BB                                                      (0xfff<<0) // Software Gen2 AckNak latency timer value in symbol time.
+  #define PCIEIP_REG_DL_ACK_LAT_GEN2_SW_ACK_LAT_GEN2_BB_SHIFT                                                0
+  #define PCIEIP_REG_DL_ACK_LAT_GEN2_HW_ACK_LAT_ADJ_GEN2_BB                                                  (0xff<<12) // Hardware Gen2 AckNak latency adjustment in symbol time. Depending on speed and Max Packet Size (MPS), hardware automatically generates an ACK latency according to the table in PCIE spec. Since the actual internal delay of the design is larger than the spec internal delay, this adjustment is subtracted out from the hardware-calculated value so that the real Ack latency is close to the value in spec.
+  #define PCIEIP_REG_DL_ACK_LAT_GEN2_HW_ACK_LAT_ADJ_GEN2_BB_SHIFT                                            12
+  #define PCIEIP_REG_DL_ACK_LAT_GEN2_SW_UPDFC_LAT_GEN2_BB                                                    (0xfff<<20) // Software Gen2 UpdateFC latency value in symbol time.
+  #define PCIEIP_REG_DL_ACK_LAT_GEN2_SW_UPDFC_LAT_GEN2_BB_SHIFT                                              20
+#define PCIEIP_REG_PDL_CONTROL_14_BB                                                                         0x001038UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PDL_CONTROL_14_DEBUG_EXT_SEL_0_BB                                                       (0x1fff<<0) // This maps 8k of addresses that can be used to extend the debug bus0. First 2k belongs to PHY Second 2K belongs to Dl Third 2K belongs to TL The last 2k is left for Vaux
+  #define PCIEIP_REG_PDL_CONTROL_14_DEBUG_EXT_SEL_0_BB_SHIFT                                                 0
+  #define PCIEIP_REG_PDL_CONTROL_14_DEBUG_EXT_SEL_1_BB                                                       (0x1fff<<13) // This maps 8k of addresses that can be used to extend the debug bus1. First 2k belongs to PHY Second 2K belongs to Dl Third 2K belongs to TL The last 2k is left for Vaux
+  #define PCIEIP_REG_PDL_CONTROL_14_DEBUG_EXT_SEL_1_BB_SHIFT                                                 13
+  #define PCIEIP_REG_PDL_CONTROL_14_UNUSED_1_BB                                                              (0x1<<26) // 
+  #define PCIEIP_REG_PDL_CONTROL_14_UNUSED_1_BB_SHIFT                                                        26
+  #define PCIEIP_REG_PDL_CONTROL_14_DEBUG_GRC_SEL_0_BB                                                       (0x3<<27) // This selects the source that drives the debug bus 1 when debug access is controlled by grc
+  #define PCIEIP_REG_PDL_CONTROL_14_DEBUG_GRC_SEL_0_BB_SHIFT                                                 27
+  #define PCIEIP_REG_PDL_CONTROL_14_DEBUG_GRC_SEL_1_BB                                                       (0x3<<29) // This selects the source that drives the debug bus 1 when debug access is controlled by grc
+  #define PCIEIP_REG_PDL_CONTROL_14_DEBUG_GRC_SEL_1_BB_SHIFT                                                 29
+  #define PCIEIP_REG_PDL_CONTROL_14_DEBUG_GRC_ENA_BB                                                         (0x1<<31) // Enable GRC to control the driving of the debug bus. When this bit is set, it provides the capability to expand the debug bus
+  #define PCIEIP_REG_PDL_CONTROL_14_DEBUG_GRC_ENA_BB_SHIFT                                                   31
+#define PCIEIP_REG_DLATTN_VEC_BB                                                                             0x001040UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DLATTN_VEC_DL_CHKSUM_ERR_BB                                                             (0x1<<0) // DL: Assert when DL detects checksum error while transmitting a TLP. Generates pcie_err_att status to chip. This status is not cleared till a 1 is written to it.
+  #define PCIEIP_REG_DLATTN_VEC_DL_CHKSUM_ERR_BB_SHIFT                                                       0
+  #define PCIEIP_REG_DLATTN_VEC_DL_D2TBUF_OFLOW_ERR_BB                                                       (0x1<<1) // Signal DLP2TLP buffer on receive side is overflow.
+  #define PCIEIP_REG_DLATTN_VEC_DL_D2TBUF_OFLOW_ERR_BB_SHIFT                                                 1
+  #define PCIEIP_REG_DLATTN_VEC_DLP2TLP_PARITY_ERROR_BB                                                      (0x1<<2) // Set if DLP2TLP buffer detects parity error
+  #define PCIEIP_REG_DLATTN_VEC_DLP2TLP_PARITY_ERROR_BB_SHIFT                                                2
+  #define PCIEIP_REG_DLATTN_VEC_REPLAY_ADDRESS_PARITY_ERROR_BB                                               (0x1<<3) // Set if Replay Address buffer detects parity error
+  #define PCIEIP_REG_DLATTN_VEC_REPLAY_ADDRESS_PARITY_ERROR_BB_SHIFT                                         3
+  #define PCIEIP_REG_DLATTN_VEC_REPLAY_WRAPPER_PARITY_ERROR_BB                                               (0x1<<4) // Set if Replay Wrapper has parity error
+  #define PCIEIP_REG_DLATTN_VEC_REPLAY_WRAPPER_PARITY_ERROR_BB_SHIFT                                         4
+  #define PCIEIP_REG_DLATTN_VEC_DL_CORRECTABLE_ERROR_BB                                                      (0x1<<5) // Assert when Correctable Error counter reach max CORR_ERR_REG_MAX value defined at bit [27:18] of reg 0x1008. The counter is incremented if there is any error associate with LCRC mismatch in DLP, DLL, PHY on receiving side.
+  #define PCIEIP_REG_DLATTN_VEC_DL_CORRECTABLE_ERROR_BB_SHIFT                                                5
+  #define PCIEIP_REG_DLATTN_VEC_DE_FRAMING_ERROR_BB                                                          (0x1<<6) // Indicate un-decoded condition in de-framing logic
+  #define PCIEIP_REG_DLATTN_VEC_DE_FRAMING_ERROR_BB_SHIFT                                                    6
+  #define PCIEIP_REG_DLATTN_VEC_DLP_ERROR_STATUS_BB                                                          (0x1<<7) // Assert when LCRC mismatch and sequence number is correct
+  #define PCIEIP_REG_DLATTN_VEC_DLP_ERROR_STATUS_BB_SHIFT                                                    7
+  #define PCIEIP_REG_DLATTN_VEC_DLP_INCORRECT_BB                                                             (0x1<<8) // RX: Indicate DLP is too long or TLP dataphases is more than max payload.
+  #define PCIEIP_REG_DLATTN_VEC_DLP_INCORRECT_BB_SHIFT                                                       8
+  #define PCIEIP_REG_DLATTN_VEC_TLPBUFRDERR_BB                                                               (0x1<<9) // RX: Asserted when one or more TLP does have either incorrect LCRC, sequence number, or ending with EDB
+  #define PCIEIP_REG_DLATTN_VEC_TLPBUFRDERR_BB_SHIFT                                                         9
+  #define PCIEIP_REG_DLATTN_VEC_REPLAY_SEQUENCE_OVERRUN_BB                                                   (0x1<<10) // REPLAY SEQUENCE is overrun
+  #define PCIEIP_REG_DLATTN_VEC_REPLAY_SEQUENCE_OVERRUN_BB_SHIFT                                             10
+  #define PCIEIP_REG_DLATTN_VEC_DLL_ERROR_ACK_BB                                                             (0x1<<11) // Set if DL detects impossible condition to de-allocate entries in Replay Buffer.
+  #define PCIEIP_REG_DLATTN_VEC_DLL_ERROR_ACK_BB_SHIFT                                                       11
+  #define PCIEIP_REG_DLATTN_VEC_REPLAY_BUFFER_OVERRUN_BB                                                     (0x1<<12) // Set if Replay buffer is overwritten
+  #define PCIEIP_REG_DLATTN_VEC_REPLAY_BUFFER_OVERRUN_BB_SHIFT                                               12
+  #define PCIEIP_REG_DLATTN_VEC_REPLAY_NUMBER_ROLL_OVER_BB                                                   (0x1<<13) // Set if number of Replay reaches max value. Default of this value is 4 times.
+  #define PCIEIP_REG_DLATTN_VEC_REPLAY_NUMBER_ROLL_OVER_BB_SHIFT                                             13
+  #define PCIEIP_REG_DLATTN_VEC_REPLAY_TIMEOUT_BB                                                            (0x1<<14) // Set if Replay Timer expired without receiving any ACK or NACK from RC
+  #define PCIEIP_REG_DLATTN_VEC_REPLAY_TIMEOUT_BB_SHIFT                                                      14
+  #define PCIEIP_REG_DLATTN_VEC_DL_TX_UNDRUN_BB                                                              (0x1<<15) // DL TX Underrun. This bit is set to '1' if underrun occurs at the DL/PL TX interface.
+  #define PCIEIP_REG_DLATTN_VEC_DL_TX_UNDRUN_BB_SHIFT                                                        15
+  #define PCIEIP_REG_DLATTN_VEC_DLL_ERROR_STATUS_BB                                                          (0x1<<16) // Detect DLLP with mismatched CRC-16 on receiving side.
+  #define PCIEIP_REG_DLATTN_VEC_DLL_ERROR_STATUS_BB_SHIFT                                                    16
+  #define PCIEIP_REG_DLATTN_VEC_DLL_PE_INIT_STATUS_BB                                                        (0x1<<17) // Receive UPDATEFC DLLP when DL has not completed FC_INIT1 state, or receive INITFC1 DLLP when DL has already finished the FC initialization.
+  #define PCIEIP_REG_DLATTN_VEC_DLL_PE_INIT_STATUS_BB_SHIFT                                                  17
+  #define PCIEIP_REG_DLATTN_VEC_UNUSED_3_BB                                                                  (0x1<<18) // 
+  #define PCIEIP_REG_DLATTN_VEC_UNUSED_3_BB_SHIFT                                                            18
+  #define PCIEIP_REG_DLATTN_VEC_TLP_INCORRECT_BB                                                             (0x1<<19) // This signal is set to '1' when the TLP length that TL indicates to DL does not match to the actual length of the TLP transmitted across the TL/DL TX interface.
+  #define PCIEIP_REG_DLATTN_VEC_TLP_INCORRECT_BB_SHIFT                                                       19
+  #define PCIEIP_REG_DLATTN_VEC_TLP_2_DLPBUF_PARITY_ERROR_BB                                                 (0x1<<20) // Set if TLP2DLP Buf has parity error
+  #define PCIEIP_REG_DLATTN_VEC_TLP_2_DLPBUF_PARITY_ERROR_BB_SHIFT                                           20
+#define PCIEIP_REG_DL_ATTN_MASK_BB                                                                           0x001044UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DL_ATTN_MASK_MASK_FOR_DL_ATTENTIONS_BB                                                  (0x1fffff<<0) // If set mask out DL attentions specified in register 0x1040
+  #define PCIEIP_REG_DL_ATTN_MASK_MASK_FOR_DL_ATTENTIONS_BB_SHIFT                                            0
+  #define PCIEIP_REG_DL_ATTN_MASK_UNUSED_1_BB                                                                (0x7ff<<21) // 
+  #define PCIEIP_REG_DL_ATTN_MASK_UNUSED_1_BB_SHIFT                                                          21
+#define PCIEIP_REG_DL_STATUS_BB                                                                              0x001048UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DL_STATUS_CORR_ERR_REG_BB                                                               (0x3ff<<0) // Total number of errors within 256us due to CRC16, LCRC, sequence number, or PL RX error.
+  #define PCIEIP_REG_DL_STATUS_CORR_ERR_REG_BB_SHIFT                                                         0
+  #define PCIEIP_REG_DL_STATUS_REPLAY_ALM_FULL_BB                                                            (0x1<<10) // If set, indicates Replay buffer is almost full. Replay available entries are two or less than two
+  #define PCIEIP_REG_DL_STATUS_REPLAY_ALM_FULL_BB_SHIFT                                                      10
+  #define PCIEIP_REG_DL_STATUS_UNUSED0_BB                                                                    (0x3<<11) // 
+  #define PCIEIP_REG_DL_STATUS_UNUSED0_BB_SHIFT                                                              11
+  #define PCIEIP_REG_DL_STATUS_PHYLINKUP_BB                                                                  (0x1<<13) // If set, indicates link is trained
+  #define PCIEIP_REG_DL_STATUS_PHYLINKUP_BB_SHIFT                                                            13
+  #define PCIEIP_REG_DL_STATUS_DL_ACTIVE_BB                                                                  (0x1<<14) // If set, signal DL finishes both INITFC1 and INITFC2
+  #define PCIEIP_REG_DL_STATUS_DL_ACTIVE_BB_SHIFT                                                            14
+  #define PCIEIP_REG_DL_STATUS_DL_INIT_BB                                                                    (0x1<<15) // If set, DL is doing VC0 FC initialization
+  #define PCIEIP_REG_DL_STATUS_DL_INIT_BB_SHIFT                                                              15
+  #define PCIEIP_REG_DL_STATUS_RESERVED_BB                                                                   (0xffff<<16) // 
+  #define PCIEIP_REG_DL_STATUS_RESERVED_BB_SHIFT                                                             16
+#define PCIEIP_REG_DL_TX_CHECKSUM_BB                                                                         0x00104cUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DL_TX_CHECKSUM_EXPECTED_TX_CHECKSUM_BB                                                  (0xffff<<0) // This field holds the checksum calculated by hardware when checksum error is detected.
+  #define PCIEIP_REG_DL_TX_CHECKSUM_EXPECTED_TX_CHECKSUM_BB_SHIFT                                            0
+  #define PCIEIP_REG_DL_TX_CHECKSUM_ACTUAL_TX_CHECKSUM_BB                                                    (0xffff<<16) // This field holds the checksum received from User Interface when checksum error is detected.
+  #define PCIEIP_REG_DL_TX_CHECKSUM_ACTUAL_TX_CHECKSUM_BB_SHIFT                                              16
+#define PCIEIP_REG_DL_MAX_UPDFC_BB                                                                           0x001050UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DL_MAX_UPDFC_MAX_UPDFC_NORMAL_BB                                                        (0x3f<<0) // DL: Maximum time in microseconds that DL has to send at least one UpdateFC DLLP for each FC credit type when Extended Sync bit is '0'.
+  #define PCIEIP_REG_DL_MAX_UPDFC_MAX_UPDFC_NORMAL_BB_SHIFT                                                  0
+  #define PCIEIP_REG_DL_MAX_UPDFC_MAX_UPDFC_EXT_BB                                                           (0xff<<6) // DL: Maximum time in microseconds that DL has to send at least one UpdateFC DLLP for each FC credit type when Extended Sync bit is '1'.
+  #define PCIEIP_REG_DL_MAX_UPDFC_MAX_UPDFC_EXT_BB_SHIFT                                                     6
+  #define PCIEIP_REG_DL_MAX_UPDFC_RESERVED_BB                                                                (0x3ffff<<14) // 
+  #define PCIEIP_REG_DL_MAX_UPDFC_RESERVED_BB_SHIFT                                                          14
+#define PCIEIP_REG_DL_T2D_THRS_BB                                                                            0x001054UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DL_T2D_THRS_DL_T2D_THRS_ENA_BB                                                          (0x1<<0) // T2D FIFO Threshold Enable. This bit is set to '1' to enable the T2D FIFO threshold feature. Depending on TL, DL bus width and clock relationship, after the first data in T2D FIFO becomes available, next data may not be available as fast as DL can retrieve. This can cause data underrun at the DL/PL TX interface. To prevent this underrun issue, when this bit is set, DL will start reading data out of T2D FIFO when one of below conditions occurs: - TLP ends in one entry. - The number of valid entries in T2D FIFO is greater than or equal to dl_t2d_count_thrs. - DL has waited at least dl_t2d_time_thrs clock cycles. This is neccessary in case the TLP size is smaller than the count threshold.
+  #define PCIEIP_REG_DL_T2D_THRS_DL_T2D_THRS_ENA_BB_SHIFT                                                    0
+  #define PCIEIP_REG_DL_T2D_THRS_DL_T2D_COUNT_THRS_BB                                                        (0x7<<1) // T2D FIFO Count Threshold. This is the number of valid data in T2D FIFO before DL state machine starts TLP transfer.
+  #define PCIEIP_REG_DL_T2D_THRS_DL_T2D_COUNT_THRS_BB_SHIFT                                                  1
+  #define PCIEIP_REG_DL_T2D_THRS_DL_T2D_TIME_THRS_BB                                                         (0xf<<4) // T2D FIFO Time Threshold. When T2D FIFO data becomes available, this is the number of clock cycles that DL state machine will wait before starting TLP transfer.
+  #define PCIEIP_REG_DL_T2D_THRS_DL_T2D_TIME_THRS_BB_SHIFT                                                   4
+  #define PCIEIP_REG_DL_T2D_THRS_RESERVED_BB                                                                 (0xffffff<<8) // 
+  #define PCIEIP_REG_DL_T2D_THRS_RESERVED_BB_SHIFT                                                           8
+#define PCIEIP_REG_DL_FIFO_TEST_BB                                                                           0x001058UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DL_FIFO_TEST_REPLAYFIFO_TESTSIZE_BB                                                     (0x3ff<<0) // Replay FIFO Test Size. When bit replayfifo_testsize_sel is set to '1', this value is used as the Replay FIFO size. This value must be set to less than or equal to the actual FIFO size. It is for simulation purpose only.
+  #define PCIEIP_REG_DL_FIFO_TEST_REPLAYFIFO_TESTSIZE_BB_SHIFT                                               0
+  #define PCIEIP_REG_DL_FIFO_TEST_D2TFIFO_TESTSIZE_BB                                                        (0x3ff<<10) // D2T FIFO Test Size. When bit d2tfifo_testsize_sel is set to '1', this value is used as the D2T FIFO size. This value must be set to less than or equal to the actual FIFO size. Furthermore, if DL and TL are asynchronous, this value must be a power of 2. It is for simulation purpose only.
+  #define PCIEIP_REG_DL_FIFO_TEST_D2TFIFO_TESTSIZE_BB_SHIFT                                                  10
+  #define PCIEIP_REG_DL_FIFO_TEST_RESERVED_BB                                                                (0x3ff<<20) // 
+  #define PCIEIP_REG_DL_FIFO_TEST_RESERVED_BB_SHIFT                                                          20
+  #define PCIEIP_REG_DL_FIFO_TEST_REPLAYFIFO_TESTSIZE_SEL_BB                                                 (0x1<<30) // Replay FIFO Test Size Select. When this bit is set to '1', the value in replayfifo_testsize will be used as Replay FIFO size. This is for simulation purpose only.
+  #define PCIEIP_REG_DL_FIFO_TEST_REPLAYFIFO_TESTSIZE_SEL_BB_SHIFT                                           30
+  #define PCIEIP_REG_DL_FIFO_TEST_D2TFIFO_TESTSIZE_SEL_BB                                                    (0x1<<31) // D2T FIFO Test Size Select. When this bit is set to '1', the value in d2tfifo_testsize will be used as D2T FIFO size. This is for simulation purpose only.
+  #define PCIEIP_REG_DL_FIFO_TEST_D2TFIFO_TESTSIZE_SEL_BB_SHIFT                                              31
+#define PCIEIP_REG_DL_SPARE0_BB                                                                              0x00105cUL //Access:RW   DataWidth:0x20   // 
+#define PCIEIP_REG_MDIO_ADDR_BB                                                                              0x001100UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_MDIO_ADDR_ADR_BB                                                                        (0xffff<<0) // This value controls the register index sent to on the MDIO bus connected to the PCIE Serdes block.
+  #define PCIEIP_REG_MDIO_ADDR_ADR_BB_SHIFT                                                                  0
+  #define PCIEIP_REG_MDIO_ADDR_PORT_BB                                                                       (0xf<<16) // This value controls port address sent to on the MDIO bus connected to the PCIE Serdes block.
+  #define PCIEIP_REG_MDIO_ADDR_PORT_BB_SHIFT                                                                 16
+  #define PCIEIP_REG_MDIO_ADDR_CMD_BB                                                                        (0xfff<<20) // A write of '0' to these bits causes no action and allows the address to be programmed in preparation for a write. A write of '1' on these bits initiates a read at the address and port specified.
+  #define PCIEIP_REG_MDIO_ADDR_CMD_BB_SHIFT                                                                  20
+#define PCIEIP_REG_MDIO_WR_DATA_BB                                                                           0x001104UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_MDIO_WR_DATA_WDATA_REG_BB                                                               (0x7fffffff<<0) // This value will be the register data for write cycles.
+  #define PCIEIP_REG_MDIO_WR_DATA_WDATA_REG_BB_SHIFT                                                         0
+  #define PCIEIP_REG_MDIO_WR_DATA_CMD_BB                                                                     (0x1<<31) // This bit must be written as a '1' to initiate write cycle based ont the data in bits [15:0] and the mdio_addr value. When the write has completed, this bit will read as '0'.
+  #define PCIEIP_REG_MDIO_WR_DATA_CMD_BB_SHIFT                                                               31
+#define PCIEIP_REG_MDIO_RD_DATA_BB                                                                           0x001108UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_MDIO_RD_DATA_RDATA_REG_BB                                                               (0x7fffffff<<0) // After a read has been requested in the mdio_addr register, this area will return the MDIO data. This field is only valid if the CMD field is '1'.
+  #define PCIEIP_REG_MDIO_RD_DATA_RDATA_REG_BB_SHIFT                                                         0
+  #define PCIEIP_REG_MDIO_RD_DATA_CMD_BB                                                                     (0x1<<31) // This bit will read as '0' until a requested read of the PCIE serdes has completed, in which case, this bit will read as '1'. This bit is automatically cleared by a write to the mdio_addr register.
+  #define PCIEIP_REG_MDIO_RD_DATA_CMD_BB_SHIFT                                                               31
+#define PCIEIP_REG_ATE_TLP_HDR_0_BB                                                                          0x00110cUL //Access:RW   DataWidth:0x20   // In ATE test mode this register together with ate_tlp_hdr_1, ate_tlp_hdr_2, and ate_tlp_hdr_3 form the 128-bit header information that is sent to TL logic to build a TLP. The header information is passed to TL as is except the TAG (i.e. bits 47:40 in a non-posted request) and RTAG (i.e. bits 79:72 in a Completion request), which are incremented by one after each packet transfer.
+#define PCIEIP_REG_ATE_TLP_HDR_1_BB                                                                          0x001110UL //Access:RW   DataWidth:0x20   // When a TLP is generated in ATE test mode, this register holds bits [63:32] of the header bus.
+#define PCIEIP_REG_ATE_TLP_HDR_2_BB                                                                          0x001114UL //Access:RW   DataWidth:0x20   // When a TLP is generated in ATE test mode, this register holds bits [95:64] of the header bus.
+#define PCIEIP_REG_ATE_TLP_HDR_3_BB                                                                          0x001118UL //Access:RW   DataWidth:0x20   // When a TLP is generated in ATE test mode, this register holds bits [127:96] of the header bus.
+#define PCIEIP_REG_ATE_TLP_CFG_BB                                                                            0x00111cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_ATE_TLP_CFG_ATE_TLP_CNT_BB                                                              (0xff<<0) // ATE TLP Count. Specify the number of TLP's to be transferred. When ate_tlp_go is set to '1', the value in this field is loaded into an internal counter that is decremented by one as each TLP is completed. Reading this register always returns the internal counter.
+  #define PCIEIP_REG_ATE_TLP_CFG_ATE_TLP_CNT_BB_SHIFT                                                        0
+  #define PCIEIP_REG_ATE_TLP_CFG_ATE_NULLIFY_BB                                                              (0x1<<8) // ATE TLP Nullify. When this bit is set to '1', an internal signal is asserted together with the last data word to nullify the transaction (i.e. emulate user_tx_nullify).
+  #define PCIEIP_REG_ATE_TLP_CFG_ATE_NULLIFY_BB_SHIFT                                                        8
+  #define PCIEIP_REG_ATE_TLP_CFG_ATE_PAT_SEL_BB                                                              (0x7<<9) // ATE Pattern Select.
+  #define PCIEIP_REG_ATE_TLP_CFG_ATE_PAT_SEL_BB_SHIFT                                                        9
+  #define PCIEIP_REG_ATE_TLP_CFG_UNUSED0_BB                                                                  (0xf<<12) // 
+  #define PCIEIP_REG_ATE_TLP_CFG_UNUSED0_BB_SHIFT                                                            12
+  #define PCIEIP_REG_ATE_TLP_CFG_ATE_PAT_SEED_BB                                                             (0xff<<16) // ATE Pattern Seed. This field holds the first data byte of the first TLP payload generated in ATE test mode. The remaining data bytes are generated based on the setting of ate_pat_sel.
+  #define PCIEIP_REG_ATE_TLP_CFG_ATE_PAT_SEED_BB_SHIFT                                                       16
+#define PCIEIP_REG_ATE_TLP_CTL_BB                                                                            0x001120UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_ATE_TLP_CTL_ATE_TLP_GO_BB                                                               (0x1<<0) // ATE TLP Go bit. When this bit is set to '1', the TX User Interface is bypassed and internal logic generates packets to TL logic. After all packets are transferred, this bit is reset to '0' by hardware.
+  #define PCIEIP_REG_ATE_TLP_CTL_ATE_TLP_GO_BB_SHIFT                                                         0
+  #define PCIEIP_REG_ATE_TLP_CTL_UNUSED0_BB                                                                  (0x7<<1) // 
+  #define PCIEIP_REG_ATE_TLP_CTL_UNUSED0_BB_SHIFT                                                            1
+  #define PCIEIP_REG_ATE_TLP_CTL_REG_TRX_CLR_RX_TLP_SB_BB                                                    (0x1<<4) // Clear RX TLP scoreboard logic bit. SW needs to read trx_reg_sb_op_done (bit[31]). If trx_reg_sb_op_done register value is 1, it indicates that HW is done comparing RX TLPs. SW needs to write reg_trx_clr_rx_tlp_sb to '1' which will clear trx_reg_sb_op_done (bit[31]), trx_reg_err_tlp_num(bits[27:20]), trx_reg_data_mismatch (bit[17]) and trx_reg_hdr_mismatch (bit[16]) registers. It is a self clearing bit.
+  #define PCIEIP_REG_ATE_TLP_CTL_REG_TRX_CLR_RX_TLP_SB_BB_SHIFT                                              4
+  #define PCIEIP_REG_ATE_TLP_CTL_UNUSED1_BB                                                                  (0x7ff<<5) // 
+  #define PCIEIP_REG_ATE_TLP_CTL_UNUSED1_BB_SHIFT                                                            5
+  #define PCIEIP_REG_ATE_TLP_CTL_TRX_REG_HDR_MISMATCH_BB                                                     (0x1<<16) // Header Mismatch. A value of '1' indicates that transmitted TLP header does not match with received TLP header. This bit can be cleared by writing '1' to reg_trx_clr_rx_tlp_sb (bit[4]).
+  #define PCIEIP_REG_ATE_TLP_CTL_TRX_REG_HDR_MISMATCH_BB_SHIFT                                               16
+  #define PCIEIP_REG_ATE_TLP_CTL_TRX_REG_DATA_MISMATCH_BB                                                    (0x1<<17) // Data Mismatch. A value of '1' indicates that transmitted TLP data do not match with received TLP data. This bit can be cleared by writing '1' to reg_trx_clr_rx_tlp_sb (bit[4]).
+  #define PCIEIP_REG_ATE_TLP_CTL_TRX_REG_DATA_MISMATCH_BB_SHIFT                                              17
+  #define PCIEIP_REG_ATE_TLP_CTL_UNUSED2_BB                                                                  (0x3<<18) // 
+  #define PCIEIP_REG_ATE_TLP_CTL_UNUSED2_BB_SHIFT                                                            18
+  #define PCIEIP_REG_ATE_TLP_CTL_TRX_REG_ERR_TLP_NUM_BB                                                      (0xff<<20) // Indicates erroneous (header/ data mismatch) TLP number. If more than one TLP has an error, value will be 0xF. When an ATE TLP packet transmission is initiated, HW transmits number of TLPs equal to ATE_TLP_CNT (bits[7:0] of ate_tlp_cfg - offset 0x111c). trx_reg_err_tlp_num indicates the number of TLP that has error. This register is cleared by writing '1' to reg_trx_clr_rx_tlp_sb (bit[4]).
+  #define PCIEIP_REG_ATE_TLP_CTL_TRX_REG_ERR_TLP_NUM_BB_SHIFT                                                20
+  #define PCIEIP_REG_ATE_TLP_CTL_UNUSED3_BB                                                                  (0x7<<28) // 
+  #define PCIEIP_REG_ATE_TLP_CTL_UNUSED3_BB_SHIFT                                                            28
+  #define PCIEIP_REG_ATE_TLP_CTL_TRX_REG_SB_OP_DONE_BB                                                       (0x1<<31) // Value of '1' indicates that number of TLPs received is equal to number of TLPs transmitted (ATE_TLP_CNT (bits[7:0] of ate_tlp_cfg - offset 0x111c). This register value needs to be ignored until user writes '1' to ATE_TLP_GO (bit[0] of ate_tlp_ctl - offset 0x1120) register.
+  #define PCIEIP_REG_ATE_TLP_CTL_TRX_REG_SB_OP_DONE_BB_SHIFT                                                 31
+#define PCIEIP_REG_SERDES_PMI_ADDR_BB                                                                        0x001130UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_SERDES_PMI_ADDR_SERDES_REG_ADDR_BB                                                      (0xf<<0) // Register Addr
+  #define PCIEIP_REG_SERDES_PMI_ADDR_SERDES_REG_ADDR_BB_SHIFT                                                0
+  #define PCIEIP_REG_SERDES_PMI_ADDR_SERDES_BLOCK_ADDR_BB                                                    (0xfff<<4) // Block Addr
+  #define PCIEIP_REG_SERDES_PMI_ADDR_SERDES_BLOCK_ADDR_BB_SHIFT                                              4
+  #define PCIEIP_REG_SERDES_PMI_ADDR_SERDES_LANE_NUM_BB                                                      (0x3<<16) // Lane Number
+  #define PCIEIP_REG_SERDES_PMI_ADDR_SERDES_LANE_NUM_BB_SHIFT                                                16
+  #define PCIEIP_REG_SERDES_PMI_ADDR_SERDES_LANE_OFFSET_BB                                                   (0x7<<18) // Offset into each set of 4 lanes
+  #define PCIEIP_REG_SERDES_PMI_ADDR_SERDES_LANE_OFFSET_BB_SHIFT                                             18
+  #define PCIEIP_REG_SERDES_PMI_ADDR_SERDES_UNICAST_BCAST_BB                                                 (0x3f<<21) // Value of 0 indicates unicast and write is per lane. Value 0xF indicates broadcast.
+  #define PCIEIP_REG_SERDES_PMI_ADDR_SERDES_UNICAST_BCAST_BB_SHIFT                                           21
+  #define PCIEIP_REG_SERDES_PMI_ADDR_SERDES_DEV_ID_BB                                                        (0x1f<<27) // Device ID. Value of 1 for this device.
+  #define PCIEIP_REG_SERDES_PMI_ADDR_SERDES_DEV_ID_BB_SHIFT                                                  27
+#define PCIEIP_REG_SERDES_PMI_WDATA_BB                                                                       0x001134UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_SERDES_PMI_WDATA_PMI_WDATA_REG_BB                                                       (0xffff<<0) // This value will be the register data for write cycles.
+  #define PCIEIP_REG_SERDES_PMI_WDATA_PMI_WDATA_REG_BB_SHIFT                                                 0
+  #define PCIEIP_REG_SERDES_PMI_WDATA_RESERVED_BB                                                            (0x3fff<<16) // This value will be ignored.
+  #define PCIEIP_REG_SERDES_PMI_WDATA_RESERVED_BB_SHIFT                                                      16
+  #define PCIEIP_REG_SERDES_PMI_WDATA_RCMD_BB                                                                (0x1<<30) // This bit must be written as a '1' to initiate read cycle to the pmi_addr value. When the read has completed, this bit will read as '0'. If both bit 31 and 30 set at the same time this operation is unpredictable.
+  #define PCIEIP_REG_SERDES_PMI_WDATA_RCMD_BB_SHIFT                                                          30
+  #define PCIEIP_REG_SERDES_PMI_WDATA_WCMD_BB                                                                (0x1<<31) // This bit must be written as a '1' to initiate write cycle based on the data in bits [15:0] and the pmi_addr value. When the write has completed, this bit will read as '0'. If both bit 31 and 30 set at the same time this operation is unpredictable.
+  #define PCIEIP_REG_SERDES_PMI_WDATA_WCMD_BB_SHIFT                                                          31
+#define PCIEIP_REG_SERDES_PMI_RDATA_BB                                                                       0x001138UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_SERDES_PMI_RDATA_PMI_RDATA_REG_BB                                                       (0xffff<<0) // After a read has been requested in the pmi_addr register, this area will return the MDIO data. This field is only valid if the CMD field is '1'.
+  #define PCIEIP_REG_SERDES_PMI_RDATA_PMI_RDATA_REG_BB_SHIFT                                                 0
+  #define PCIEIP_REG_SERDES_PMI_RDATA_RESERVED_BB                                                            (0x7fff<<16) // Not used.
+  #define PCIEIP_REG_SERDES_PMI_RDATA_RESERVED_BB_SHIFT                                                      16
+  #define PCIEIP_REG_SERDES_PMI_RDATA_VALID_BB                                                               (0x1<<31) // This bit will read as '0' until a requested read of the PCIE serdes has completed, in which case, this bit will read as '1'. This bit is automatically cleared by a write to the serdes_pmi_wdata register.
+  #define PCIEIP_REG_SERDES_PMI_RDATA_VALID_BB_SHIFT                                                         31
+#define PCIEIP_REG_DL_DBG_0_BB                                                                               0x001400UL //Access:R    DataWidth:0x20   // DL debug signals.
+#define PCIEIP_REG_DL_DBG_1_BB                                                                               0x001404UL //Access:R    DataWidth:0x20   // DL debug signals.
+#define PCIEIP_REG_DL_DBG_2_BB                                                                               0x001408UL //Access:R    DataWidth:0x20   // DL debug signals.
+#define PCIEIP_REG_DL_DBG_3_BB                                                                               0x00140cUL //Access:R    DataWidth:0x20   // DL debug signals.
+#define PCIEIP_REG_DL_DBG_4_BB                                                                               0x001410UL //Access:R    DataWidth:0x20   // DL debug signals.
+#define PCIEIP_REG_DL_DBG_5_BB                                                                               0x001414UL //Access:R    DataWidth:0x20   // DL debug signals.
+#define PCIEIP_REG_DL_DBG_6_BB                                                                               0x001418UL //Access:R    DataWidth:0x20   // DL debug signals.
+#define PCIEIP_REG_DL_DBG_7_BB                                                                               0x00141cUL //Access:R    DataWidth:0x20   // DL debug signals.
+#define PCIEIP_REG_DL_DBG_8_BB                                                                               0x001420UL //Access:R    DataWidth:0x20   // DL debug signals.
+#define PCIEIP_REG_DL_DBG_9_BB                                                                               0x001424UL //Access:R    DataWidth:0x20   // DL debug signals.
+#define PCIEIP_REG_DL_DBG_10_BB                                                                              0x001428UL //Access:R    DataWidth:0x20   // DL debug signals.
+#define PCIEIP_REG_DL_DBG_11_BB                                                                              0x00142cUL //Access:R    DataWidth:0x20   // DL debug signals.
+#define PCIEIP_REG_DL_DBG_12_BB                                                                              0x001430UL //Access:R    DataWidth:0x20   // DL debug signals.
+#define PCIEIP_REG_DL_DBG_13_BB                                                                              0x001434UL //Access:R    DataWidth:0x20   // DL debug signals.
+#define PCIEIP_REG_DL_DBG_14_BB                                                                              0x001438UL //Access:R    DataWidth:0x20   // DL debug signals.
+#define PCIEIP_REG_DL_DBG_15_BB                                                                              0x00143cUL //Access:R    DataWidth:0x20   // DL debug signals.
+#define PCIEIP_REG_DL_DBG_16_BB                                                                              0x001440UL //Access:R    DataWidth:0x20   // DL debug signals.
+#define PCIEIP_REG_DL_DBG_17_BB                                                                              0x001444UL //Access:R    DataWidth:0x20   // DL debug signals.
+#define PCIEIP_REG_DL_DBG_18_BB                                                                              0x001448UL //Access:R    DataWidth:0x20   // DL debug signals.
+#define PCIEIP_REG_DL_DBG_19_BB                                                                              0x00144cUL //Access:R    DataWidth:0x20   // DL debug signals.
+#define PCIEIP_REG_REG_PHY_CTL_0_BB                                                                          0x001800UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PHY_CTL_0_DIRECTED_WIDTH_CHANGE_REQ_BB                                              (0x1<<0) // Request a width change (ie -make the link wider, if possible). Do not assert if the "other side" is not capable of upconfiguration.
+  #define PCIEIP_REG_REG_PHY_CTL_0_DIRECTED_WIDTH_CHANGE_REQ_BB_SHIFT                                        0
+  #define PCIEIP_REG_REG_PHY_CTL_0_DIRECTED_SPEED_CHANGE_REQ_BB                                              (0x1<<1) // Request a speed change (ie -make the link fast or slower, depending on the advertised speeds).
+  #define PCIEIP_REG_REG_PHY_CTL_0_DIRECTED_SPEED_CHANGE_REQ_BB_SHIFT                                        1
+  #define PCIEIP_REG_REG_PHY_CTL_0_UNUSED_3_BB                                                               (0x7<<2) // Some of these bits have obsolete uses and should always be written as 0
+  #define PCIEIP_REG_REG_PHY_CTL_0_UNUSED_3_BB_SHIFT                                                         2
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_IDLE_TO_RLOCK_ENA_BB                                                  (0x1<<5) // Enable the shortcut transition from Config.Complete to Recovery.RcvrLock Software should not change this field while the PCIE link is active.
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_IDLE_TO_RLOCK_ENA_BB_SHIFT                                            5
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_UPCONFIG_ENA_BB                                                       (0x1<<6) // For multi-lane links on a 2.0 compliant core, enable advertisement of the capability to upconfigure the number of lanes in the link.
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_UPCONFIG_ENA_BB_SHIFT                                                 6
+  #define PCIEIP_REG_REG_PHY_CTL_0_UNUSED_2_BB                                                               (0x1<<7) // 
+  #define PCIEIP_REG_REG_PHY_CTL_0_UNUSED_2_BB_SHIFT                                                         7
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_FRAMERR_BB                                                   (0x1<<8) // Consider DLLP and TLP framing errors as errors when reporting physical layer errors
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_FRAMERR_BB_SHIFT                                             8
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_NOLOCK_BB                                                    (0x1<<9) // Consider loss of bit and symbol lock from the PCIe Serdes as errors reporting physical layer errors
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_NOLOCK_BB_SHIFT                                              9
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_SKEW_BB                                                      (0x1<<10) // Consider link skew errors as errors when reporting physical layer errors
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_SKEW_BB_SHIFT                                                10
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_BUFOVER_BB                                                   (0x1<<11) // Consider buffer overrun errors from the PCIe Serdes as errors when processing ordered sets, DLLPs, and TLPs BUG: do not use in EP/RC Ax cores
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_BUFOVER_BB_SHIFT                                             11
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_BUFUNDER_BB                                                  (0x1<<12) // Consider buffer underrun errors from the PCIe Serdes as errors when processing ordered sets, DLLPs, and TLPs BUG: do not use in EP/RC Ax cores
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_BUFUNDER_BB_SHIFT                                            12
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_DECODE_BB                                                    (0x1<<13) // Consider decode errors from the PCIe Serdes as errors when processing ordered sets, DLLPs, and TLPs BUG: do not use in EP/RC Ax cores
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_DECODE_BB_SHIFT                                              13
+  #define PCIEIP_REG_REG_PHY_CTL_0_UNUSED_1_BB                                                               (0x3<<14) // 
+  #define PCIEIP_REG_REG_PHY_CTL_0_UNUSED_1_BB_SHIFT                                                         14
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_MATCH_POL_BB                                                      (0x1<<16) // If set, all symbols of the Modified Compliance Pattern must be of the same polarity (no mixed polarity) for the receiver to lock
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_MATCH_POL_BB_SHIFT                                                16
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_MATCH_ERR_BB                                                      (0x1<<17) // If set, both error symbols must match in the received Modified Compliance Pattern before the value is reported
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_MATCH_ERR_BB_SHIFT                                                17
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_EXIT_BB                                                           (0x1<<18) // Directed exit from generating the Modified Compliance Pattern in Polling.Compliance if the Enter Compliance bit of the Link Control 2 register is not set
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_EXIT_BB_SHIFT                                                     18
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_SIGDET_EXIT_BB                                                    (0x1<<19) // Allows exit from Polling.Compliance when generating the Modified Compliance pattern and at least one lane goes to electrical idle
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_SIGDET_EXIT_BB_SHIFT                                              19
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_FORCE_ENTRY_BB                                                    (0x1<<20) // Forces entry to Polling.Compliance from Polling.Active. This also causes the Compliance Receive bit in the outgoing TS1s to be set in Polling.Active. After entry to Polling.Compliance, the Modified Compliance Pattern is generated instead of the legacy compliance pattern
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_FORCE_ENTRY_BB_SHIFT                                              20
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_TX_DEEMPH_BB                                                          (0x1<<21) // The value for the Selectable Deemphasis bit set in TS1s in Polling.Active, Loopback, Recovery, and some Configuration states and set in TS2s in Polling.Configuration
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_TX_DEEMPH_BB_SHIFT                                                    21
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_LOCAL_DEEMPH_LO_BB                                                    (0x1<<22) // The initial value of the local deemphasis set in the Detect state (this propagates to the PCIe Serdes via the TxDeemph signal. 0 == -6 dB, 1 == -3.5 dB (For Gen3, this is the low bit of the local Tx preset if none received in EQ TS2s.)
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_LOCAL_DEEMPH_LO_BB_SHIFT                                              22
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_AUTONOMOUS_CHANGE_BB                                                  (0x1<<23) // The value for the Autonomous Change bit set in TS1s in the Configuration state when PhyLinkUp is set and set in TS2s in the Recovery state
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_AUTONOMOUS_CHANGE_BB_SHIFT                                            23
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_DIRECT_TO_DETECT_BB                                                   (0x1<<24) // Directed transition from Loopback or Polling.Compliance states to Detect state
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_DIRECT_TO_DETECT_BB_SHIFT                                             24
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_DIRECT_TO_L0_BB                                                       (0x1<<25) // Directed transition from L1 state to Recovery or L2 state to Detect.
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_DIRECT_TO_L0_BB_SHIFT                                                 25
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_LPBK_EXIT_ON_ELECIDLE_BB                                              (0x1<<26) // Optionally enable the use of electrical idle or inferred electrical ide as a condition for exiting loopback in 2.0 compliant cores.
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_LPBK_EXIT_ON_ELECIDLE_BB_SHIFT                                        26
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_DISABLE_SPEED_EI_BB                                                   (0x1<<27) // Disable use of electrical idle in Recovery.Speed - only use inferred electrical idle
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_DISABLE_SPEED_EI_BB_SHIFT                                             27
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_LPBK_EXIT_ON_IEI_BB                                                   (0x1<<28) // For 2.0 compliant systems, default to the optional behavior of exiting Loopback on inferred electrical idle at 2.5 GT/s.
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_LPBK_EXIT_ON_IEI_BB_SHIFT                                             28
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_DIS_LANE_REVERSAL_BB                                                  (0x1<<29) // Disable the ability to compensate for lane reversal in multi-lane links.
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_DIS_LANE_REVERSAL_BB_SHIFT                                            29
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_ENABLE_RIDLE_SPD_CLR_BB                                               (0x1<<30) // Enable the clearing of directed_speed_change on the transition to Recovery.Idle. This is newly specified for the 2.1 spec in cases where no speed change occurs even though it is directed.
+  #define PCIEIP_REG_REG_PHY_CTL_0_REG_ENABLE_RIDLE_SPD_CLR_BB_SHIFT                                         30
+  #define PCIEIP_REG_REG_PHY_CTL_0_GEN2_FEATURES_ENA_BB                                                      (0x1<<31) // Enable gen2 features when in 1.1 compliance mode (register 0x4d0, bit 5 is set)
+  #define PCIEIP_REG_REG_PHY_CTL_0_GEN2_FEATURES_ENA_BB_SHIFT                                                31
+#define PCIEIP_REG_REG_PHY_CTL_1_BB                                                                          0x001804UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_FORCE_GEN2_16BIT_BB                                                   (0x1<<0) // Force the PIPE interface to be 16-bit, even in Gen 1 Software should not change this field while the PCIE link is active.
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_FORCE_GEN2_16BIT_BB_SHIFT                                             0
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_DISABLE_COMPLIANCE_BB                                                 (0x1<<1) // Disable entry to Polling.Compliance
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_DISABLE_COMPLIANCE_BB_SHIFT                                           1
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_LANE_POWERDOWN_ENA_BB                                                 (0x1<<2) // Enable the PIPE-style powerdown of unused lanes in a multi-lane link.
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_LANE_POWERDOWN_ENA_BB_SHIFT                                           2
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_P2_POWERDOWN_ENA_NOSYNC_BB                                            (0x1<<3) // Enable the auxilliary powerdown of unused lanes in a multi-lane link.
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_P2_POWERDOWN_ENA_NOSYNC_BB_SHIFT                                      3
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_FAREND_LPBK_REQ_BB                                                    (0x1<<4) // Initiate PL changes required for a far-end loopback
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_FAREND_LPBK_REQ_BB_SHIFT                                              4
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_COMPL_CFG_DETECT_RST_BB                                               (0x1<<5) // If set, when Detect is entered the compliance configuration that cycles through the rates, deemphasis, and presets is reset back to the first configuration (Gen1).
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_COMPL_CFG_DETECT_RST_BB_SHIFT                                         5
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_LATE_CLR_DESKEW_BUFS_BB                                               (0x1<<6) // When set, clear the statis deskew buffers on assertion of the internal deskew enable signal rather than clearing the buffers on the deassertion. This prevents the transient misalignment of data at the end of L0 (when transitioning to L0s or L1). When clear, the legacy behaviour is enabled where the static deskew buffers are cleared on deassertion of the internal deskew enable signal.
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_LATE_CLR_DESKEW_BUFS_BB_SHIFT                                         6
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_EIDL_DLY_BB                                                           (0x1f<<7) // Tuning field to set the delay in clocks for the electrical idle signal (on the PIPE interface) so that EIDL OS appears first if present (0 = 24 clocks, 1 = 1 clock, 2 = 2 clocks, etc up to 23 clocks) Software should not change this field while the PCIE link is active For Ev3 A0 and B0, this field must be written to a value greater than 16.
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_EIDL_DLY_BB_SHIFT                                                     7
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_POWERDOWN_P1PLL_ENA_BB                                                (0x1<<12) // This signal goes to the PCIe Serdes to enable the PLL to power down when all lanes are in L1 If ClkReq is active, this signal is ignored.
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_POWERDOWN_P1PLL_ENA_BB_SHIFT                                          12
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_COM_FOR_INF_EIDL_BB                                                   (0x1<<13) // Enable using lack of received COM instead of lack of received TS2 in Recovery.RcvrCfg for inferred electrical idle. This is to mimic the "Gen2 0.7 spec" functionality
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_COM_FOR_INF_EIDL_BB_SHIFT                                             13
+  #define PCIEIP_REG_REG_PHY_CTL_1_EIE_FTS_MAX_BB                                                            (0x3<<14) // This field programs the number of EIE symbols to send before the first FTS when exiting Tx_L0s in Gen2  b00 : Four EIE symbols are sent b01 : Six EIE symbols are sent (default) b10 : Eight EIE symbols are sent b11 : Eight EIE symbols are sent
+  #define PCIEIP_REG_REG_PHY_CTL_1_EIE_FTS_MAX_BB_SHIFT                                                      14
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_RXVALID_FOR_EIE_BB                                                    (0x1<<16) // Use valid data as "exit from electrical idle" in the Loopback states
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_RXVALID_FOR_EIE_BB_SHIFT                                              16
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_IEI_ANY_LANES_BB                                                      (0x1<<17) // Declare EIE if any lane has TSx/EIEOS (or IEI if no lane has TSx/EIEOS)
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_IEI_ANY_LANES_BB_SHIFT                                                17
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_IEI_ENA_SOS_BB                                                        (0x1<<18) // Declare an inferred electrical idel in L0 if no Skip Ordered Set (SOS) is received in any 128 us interval. See comments for bit 19 of this register
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_IEI_ENA_SOS_BB_SHIFT                                                  18
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_IEI_ENA_UPDFC_BB                                                      (0x1<<19) // Declare an inferred electrical idle in L0 if no UpdateFC is received in any 128 us interval. Can be combined with bit 18 of this register. In that case, not receiving both an UpdateFC or a Skip Ordered Set within the 128 us interval is considered an inferred electrical idle
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_IEI_ENA_UPDFC_BB_SHIFT                                                19
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_IEI_FILTER_MAX_BB                                                     (0xf<<20) // The depth of the inferred electrical idle filter used to "deskew" the detection of ordered sets.
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_IEI_FILTER_MAX_BB_SHIFT                                               20
+  #define PCIEIP_REG_REG_PHY_CTL_1_UNUSED_1_BB                                                               (0x1<<24) // 
+  #define PCIEIP_REG_REG_PHY_CTL_1_UNUSED_1_BB_SHIFT                                                         24
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_SPDUP_TIMER_1KX_BB                                                    (0x1<<25) // Speed up training by 1000x (1 ms = 1 us)
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_SPDUP_TIMER_1KX_BB_SHIFT                                              25
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_SPDUP_TIMER_2KX_BB                                                    (0x1<<26) // Speed up training by 2000x (1 ms = 500 ns). Do not use with Denali
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_SPDUP_TIMER_2KX_BB_SHIFT                                              26
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_SPDUP_POLL_BB                                                         (0x1<<27) // When training is sped up using bits 25 or 26, extend the timeout for Polling.Active to 72 us
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_SPDUP_POLL_BB_SHIFT                                                   27
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_SPDUP_TS1_BB                                                          (0x1<<28) // Speed up Polling.Active by restricting the number of TS1s to transmit to 32 (instead of 1024)
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_SPDUP_TS1_BB_SHIFT                                                    28
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_CLR_LTSSM_HIST_BB                                                     (0x1<<29) // Clear the LTSSM histogram. Not self-clearing
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_CLR_LTSSM_HIST_BB_SHIFT                                               29
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_CLR_GEN2_HIST_BB                                                      (0x1<<30) // Clear the Gen2 debug histogram. Not self-clearing
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_CLR_GEN2_HIST_BB_SHIFT                                                30
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_CLR_RECOV_HIST_BB                                                     (0x1<<31) // Clear the recovery histogram. Not self-clearing
+  #define PCIEIP_REG_REG_PHY_CTL_1_REG_CLR_RECOV_HIST_BB_SHIFT                                               31
+#define PCIEIP_REG_REG_PHY_CTL_2_BB                                                                          0x001808UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PHY_CTL_2_PRESCALE_CNT_MAX_BB                                                       (0x7f<<0) // Prescaler (using 4 ns clocks) for the inferred electrical idle counters
+  #define PCIEIP_REG_REG_PHY_CTL_2_PRESCALE_CNT_MAX_BB_SHIFT                                                 0
+  #define PCIEIP_REG_REG_PHY_CTL_2_EIDL_TX_GOOD_CNT_MAX_BB                                                   (0x1ff<<7) // Minimum time (in 4 ns clocks) to hold the transmitter in electrical idle when initially changing line rate during Recovery
+  #define PCIEIP_REG_REG_PHY_CTL_2_EIDL_TX_GOOD_CNT_MAX_BB_SHIFT                                             7
+  #define PCIEIP_REG_REG_PHY_CTL_2_EIDL_TX_BAD_CNT_MAX_BB                                                    (0xfff<<16) // Minimum time (in 4 ns clocks) to hold the transmitter in electrical idle when changing line rate after a previous unsuccessful speed change in this retrain
+  #define PCIEIP_REG_REG_PHY_CTL_2_EIDL_TX_BAD_CNT_MAX_BB_SHIFT                                              16
+  #define PCIEIP_REG_REG_PHY_CTL_2_PL_SPARE_IN_10_BB                                                         (0x3<<28) // Reserved - only write 0. Spare flops for the PL - train_ctl_in[1:0]. [29] (PL_FIX_19) Enable Phase 3 local echo delay to allow Serdes time to react  - signal is reg_gen3_ena_ph3_echo_delay.
+  #define PCIEIP_REG_REG_PHY_CTL_2_PL_SPARE_IN_10_BB_SHIFT                                                   28
+  #define PCIEIP_REG_REG_PHY_CTL_2_REG_DIS_SERDES_CLKCOMP_BB                                                 (0x1<<30) // When set, the Serdes elastic buffers will be prevented from adjusting - generating dynamic clock compensation events - prior to the MAC performing static deskew. This is controlled via the pcie_lnk_phy_gpin_0 signal. (Also, this is pl_spare_in[2] or train_ctl_in[2].)
+  #define PCIEIP_REG_REG_PHY_CTL_2_REG_DIS_SERDES_CLKCOMP_BB_SHIFT                                           30
+  #define PCIEIP_REG_REG_PHY_CTL_2_PL_SPARE_IN_3_BB                                                          (0x1<<31) // Reserved - only write 0. Spare flop for the PL - train_ctl_in[3]. Connected to Serdes via pipe_GPin_1.
+  #define PCIEIP_REG_REG_PHY_CTL_2_PL_SPARE_IN_3_BB_SHIFT                                                    31
+#define PCIEIP_REG_REG_PHY_CTL_3_BB                                                                          0x00180cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PHY_CTL_3_EIDL_INF_COM_CNT_MAX_BB                                                   (0x1ff<<0) // The maximum time to wait (using prescaled increments) before declaring an inferred electrical idle in Recovery.RcvrCfg based on no receipt of TS1s/TS2s (or optionally just COM symbols)
+  #define PCIEIP_REG_REG_PHY_CTL_3_EIDL_INF_COM_CNT_MAX_BB_SHIFT                                             0
+  #define PCIEIP_REG_REG_PHY_CTL_3_EIDL_INF_EIE_CNT_MAX_BB                                                   (0x1f<<9) // The maximum time to wait (using prescaled increments) before declaring an inferred electrical idle in Recovery.Speed or Loopback based on no exit from electrical idle. The value is divided by four for Gen1 speeds
+  #define PCIEIP_REG_REG_PHY_CTL_3_EIDL_INF_EIE_CNT_MAX_BB_SHIFT                                             9
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_GLOOPBACK_BB                                                          (0x1<<14) // Enable the "pins" gloopback - assumes an external loopback method
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_GLOOPBACK_BB_SHIFT                                                    14
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_SPEED_CHANGE_WAIT_BB                                                  (0x1<<15) // Wait for the Serdes to indicate speed change using the PhyStatus (otherwise it assumes the rate change was successful).
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_SPEED_CHANGE_WAIT_BB_SHIFT                                            15
+  #define PCIEIP_REG_REG_PHY_CTL_3_UNUSED_2_BB                                                               (0x1<<16) // 
+  #define PCIEIP_REG_REG_PHY_CTL_3_UNUSED_2_BB_SHIFT                                                         16
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_LOSE_DESKEW_ON_SKP_BB                                                 (0x1<<17) // Enable a stronger check at the end of lane deskew and clock compensation to look for aligned SKP symbols and COM symbols rather than just COM symbols.
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_LOSE_DESKEW_ON_SKP_BB_SHIFT                                           17
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_ENA_DLLRX_IN_IDLE_BB                                                  (0x1<<18) // Enable received data to be presented to the DLL in Configuration.Idle or Recovery.Idle if the lane to lane deskew is corrected even if logical idle data symbols have not been received. This is not according to spec but is according to the previous implmentation.
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_ENA_DLLRX_IN_IDLE_BB_SHIFT                                            18
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_IGNORE_RLOCK_PWRDN_ACK_BB                                             (0x1<<19) // Ignore powerdown change ACk for R.Lock timeouts
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_IGNORE_RLOCK_PWRDN_ACK_BB_SHIFT                                       19
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_IGNORE_RLOCK_SPD_ACK_BB                                               (0x1<<20) // Ignore rate change ACk for R.Lock timeouts
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_IGNORE_RLOCK_SPD_ACK_BB_SHIFT                                         20
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_ENA_RXEI_IN_SPEED_BB                                                  (0x1<<21) // Enable requiring Rx EI before speed change
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_ENA_RXEI_IN_SPEED_BB_SHIFT                                            21
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_DIS_P1_RXEI_REQ_BB                                                    (0x1<<22) // Disable requirement for all lanes in EI on transition to P1
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_DIS_P1_RXEI_REQ_BB_SHIFT                                              22
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_ENA_DETECT_P1_BB                                                      (0x1<<23) // Enable requirement for Serdes to be in P1 before receiver detect
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_ENA_DETECT_P1_BB_SHIFT                                                23
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_DIS_P0S_IN_EXIT_L0S_BB                                                (0x1<<24) // Do not wait for P0s before exiting Tx_L0s
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_DIS_P0S_IN_EXIT_L0S_BB_SHIFT                                          24
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_ENA_GEN1_IN_DISABLED_BB                                               (0x1<<25) // Change the rate to the Serdes to Gen1 in the Disabled state rather than waiting until the LTSSM moves to Detect (per PIPE spec) to mask a Serdes bug.
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_ENA_GEN1_IN_DISABLED_BB_SHIFT                                         25
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_SEL_GEN12_CLEAR_DLP_BB                                                (0x7<<26) // Select the delay to gate off data from the PL to the DLL in Gen1 and Gen2 rates.
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_SEL_GEN12_CLEAR_DLP_BB_SHIFT                                          26
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_SEL_GEN3_CLEAR_DLP_BB                                                 (0x7<<29) // Select the delay to gate off data from the PL to the DLL in Gen3 rate.
+  #define PCIEIP_REG_REG_PHY_CTL_3_REG_SEL_GEN3_CLEAR_DLP_BB_SHIFT                                           29
+#define PCIEIP_REG_REG_PHY_CTL_4_BB                                                                          0x001810UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_SEL_RCVD_DEEMPH_BB                                                    (0x1<<0) // For RC only. Select the value to use for the deemphasis set during Recovery from the downstream component instead of from the Link Control 2 register.
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_SEL_RCVD_DEEMPH_BB_SHIFT                                              0
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_ENA_SPEED_MATCH_UP_BB                                                 (0x1<<1) // For RC only. Enale automatic speed match when the link must change to Gen1 (slow down).
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_ENA_SPEED_MATCH_UP_BB_SHIFT                                           1
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_ENA_SPEED_MATCH_DOWN_BB                                               (0x1<<2) // For RC only. Enale automatic speed match when the link must change to Gen2 (speed up).
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_ENA_SPEED_MATCH_DOWN_BB_SHIFT                                         2
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_SPDUP_200MS_50MS_BB                                                   (0x1<<3) // For RC only. For testing/simulation purposes, speed up the timer used to wait after a failed automatic speed up/slow down to 50 ms instead of 200 ms.
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_SPDUP_200MS_50MS_BB_SHIFT                                             3
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_SPDUP_200MS_25MS_BB                                                   (0x1<<4) // For RC only. For testing/simulation purposes, speed up the timer used to wait after a failed automatic speed up/slow down to 25 ms instead of 200 ms.
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_SPDUP_200MS_25MS_BB_SHIFT                                             4
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_SPEED_MATCH_ADV_DETECT_BB                                             (0x1<<5) // For RC only. When the RC is automatically speeding up/slowing down the link to match advertised rates, use the rates from the link partner advertised since Detect rather than those immediately advertised.
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_SPEED_MATCH_ADV_DETECT_BB_SHIFT                                       5
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_REPORT_SPEED_MATCH_BB                                                 (0x1<<6) // For RC only. Report automatic speed up/slow down by the RC in the Autonomous Bandwidth Status bits.
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_REPORT_SPEED_MATCH_BB_SHIFT                                           6
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_ALLOW_LOCAL_SPD_CHG_BB                                                (0x1<<7) // Allow locally initiated speed change (directed_speed_change) even if the link partner has only advertised Gen1 rate since Detect.
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_ALLOW_LOCAL_SPD_CHG_BB_SHIFT                                          7
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_ALLOW_REMOTE_SPD_CHG_BB                                               (0x1<<8) // Allow link partner to initiate speed change (directed_speed_change) even if only Gen1 rate has been advertised since Detect.
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_ALLOW_REMOTE_SPD_CHG_BB_SHIFT                                         8
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_ADV_LINKCAP_RATES_BB                                                  (0x1<<9) // For RC only. Advertise the supported rates from the Link Capabilities register instead of the Link Control 2 register.
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_ADV_LINKCAP_RATES_BB_SHIFT                                            9
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_P2_EI_DELAY_BB                                                        (0x7<<10) // Sets the delay between the assertion of electrical idle to the power state change to P2. The delay is the in clocks and is 4 + the value of this field.
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_P2_EI_DELAY_BB_SHIFT                                                  10
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_P2_EI_DELAY_DIS_BB                                                    (0x1<<13) // If set, disables the delay between the assertion of electrical idle to the power state change to P2. This is needed in Gen2 when entering L2. The minimum time to wait in Detect.Quiet (in 32 ns increments) if the state is entered at non-Gen1 speeds
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_P2_EI_DELAY_DIS_BB_SHIFT                                              13
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_P2_IN_RESET_ENA_BB                                                    (0x1<<14) // Allow lanes to be put into P2 state during reset to save power.
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_P2_IN_RESET_ENA_BB_SHIFT                                              14
+  #define PCIEIP_REG_REG_PHY_CTL_4_UNUSED_2_BB                                                               (0x1<<15) // 
+  #define PCIEIP_REG_REG_PHY_CTL_4_UNUSED_2_BB_SHIFT                                                         15
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_COMPL_EXIT_ON_ANY_BB                                                  (0x1<<16) // Enable exit from Compliance on 1.1-compliant systems on signal detect on any lane (spec says all lanes must have signal detect to exit).
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_COMPL_EXIT_ON_ANY_BB_SHIFT                                            16
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_COMPL_MIN_LANE_DETECT_BB                                              (0x1<<17) // The minimum number of lanes for signal detect to avoid entry to Compliance. 0 means only 1 is needed, 1 means all are needed.
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_COMPL_MIN_LANE_DETECT_BB_SHIFT                                        17
+  #define PCIEIP_REG_REG_PHY_CTL_4_UNUSED_1_BB                                                               (0x1<<18) // 
+  #define PCIEIP_REG_REG_PHY_CTL_4_UNUSED_1_BB_SHIFT                                                         18
+  #define PCIEIP_REG_REG_PHY_CTL_4_UPCFG_LANES_BB                                                            (0x1f<<19) // Mask for indicating lanes to upconfigure (1, 2, 4, 8, or 16)
+  #define PCIEIP_REG_REG_PHY_CTL_4_UPCFG_LANES_BB_SHIFT                                                      19
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_TX_LINKNO_BB                                                          (0xff<<24) // For root complex cores, this indicates the link number for the link
+  #define PCIEIP_REG_REG_PHY_CTL_4_REG_TX_LINKNO_BB_SHIFT                                                    24
+#define PCIEIP_REG_REG_PHY_CTL_5_BB                                                                          0x001814UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_TCRPW_MAX_BB                                                     (0x1f<<0) // Counter of 25 MHz clks for the mininum time to spend with external CLKREQ deasserted.
+  #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_TCRPW_MAX_BB_SHIFT                                               0
+  #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_TREFUP_MAX_HI_BB                                                 (0xf<<5) // High 4 bits of the 10 bit-counter of 25 MHz clks for the minimum time to spend waiting for the reference clock buffers in the Serdes to power up after P2. For Ev3 A0, this field should be set to 4'h2
+  #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_TREFUP_MAX_HI_BB_SHIFT                                           5
+  #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_TCRLON_MAX_BB                                                    (0x1f<<9) // Counter of 25 MHz clks for the maximum time to wait after assertion of external CLKREQ until the reference clock is active.
+  #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_TCRLON_MAX_BB_SHIFT                                              9
+  #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_TEXCR_MAX_BB                                                     (0x7f<<14) // Counter of 25 MHz clks for the minimum time to wait between assertion of clkreq/auxclk to the Serdes and deassertion of external CLKREQ.
+  #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_TEXCR_MAX_BB_SHIFT                                               14
+  #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_DIS_FASTL1EXIT_BB                                                (0x1<<21) // When set, disables the control of the Serdes device type to minimize the PLL lock time (when set, don't reuse the old value - start over).
+  #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_DIS_FASTL1EXIT_BB_SHIFT                                          21
+  #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_L0S_LFCLK_SEL_BB                                                 (0x3<<22) // Selects the low-frequency clock used to advance the L0s exit state machine. Default is from the version.v  b00 : lfclk = 25 MHz (default and compatible with older cores) b01 : lfclk = 50 MHz  b1x : lfclk = 100 MHz (refclk)
+  #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_L0S_LFCLK_SEL_BB_SHIFT                                           22
+  #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_TREFUP_MAX_LO_BB                                                 (0x3f<<24) // Low 6 bits of the 10 bit-counter of 25 MHz clks for the minimum time to spend waiting for the reference clock buffers in the Serdes to power up after P2. For Ev3 A0, this field should be set to 6'h16
+  #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_TREFUP_MAX_LO_BB_SHIFT                                           24
+  #define PCIEIP_REG_REG_PHY_CTL_5_UNUSED_1_BB                                                               (0x1<<30) // Reserved - only write 0
+  #define PCIEIP_REG_REG_PHY_CTL_5_UNUSED_1_BB_SHIFT                                                         30
+  #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_NO_L2_CLKREQ_BB                                                  (0x1<<31) // When set, disables entry to CLKREQ when L2/L23 is requested (ie, only PM L1 and ASPM L1 etner CLKREQ)
+  #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_NO_L2_CLKREQ_BB_SHIFT                                            31
+#define PCIEIP_REG_REG_PHY_CTL_6_BB                                                                          0x001818UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_TP0TOREFCLK_MAX_BB                                               (0x3f<<0) // Number of clocks at 25 MHz to delay between the start of active clkreq (not in the standby state) and the switchover from RefClk to AuxClk. This timer includes waiting for the Serdes response to the P0 to P2 powerdown state change and will eventually advance even if it is not seen.
+  #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_TP0TOREFCLK_MAX_BB_SHIFT                                         0
+  #define PCIEIP_REG_REG_PHY_CTL_6_UNUSED_3_BB                                                               (0x3<<6) // Reserved - only write 0
+  #define PCIEIP_REG_REG_PHY_CTL_6_UNUSED_3_BB_SHIFT                                                         6
+  #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_SERDES_RESET_MAX_BB                                              (0x3f<<8) // Number of clocks at 25 MHz to delay between assertion of reset to the Serdes before deassertion of the Serdes clk switcher reset
+  #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_SERDES_RESET_MAX_BB_SHIFT                                        8
+  #define PCIEIP_REG_REG_PHY_CTL_6_UNUSED_2_BB                                                               (0x3<<14) // Reserved - only write 0
+  #define PCIEIP_REG_REG_PHY_CTL_6_UNUSED_2_BB_SHIFT                                                         14
+  #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_CLR_HIST_BB                                                      (0x1<<16) // Clear the clkreq state history
+  #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_CLR_HIST_BB_SHIFT                                                16
+  #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_ENA_ANY_PHYSTATUS_BB                                             (0x1<<17) // Use any PhyStatus to indicate the P0-&gt;P2 transition. Default is that all active lanes must respond.
+  #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_ENA_ANY_PHYSTATUS_BB_SHIFT                                       17
+  #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_ENA_CLKREQB_ON_BB                                                (0x1<<18) // CLKREQB is always asserted regardless of the clock PM state.
+  #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_ENA_CLKREQB_ON_BB_SHIFT                                          18
+  #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_ENA_CLKRST_PERST_BB                                              (0x1<<19) // Always reset the Serdes clk mux during perstb and keep it asserted while perstb is asserted. Default is to briefly reset on perstb assertion, then deassert the clk mux reset.
+  #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_ENA_CLKRST_PERST_BB_SHIFT                                        19
+  #define PCIEIP_REG_REG_PHY_CTL_6_UNUSED_1_BB                                                               (0xfff<<20) // Reserved - only write 0
+  #define PCIEIP_REG_REG_PHY_CTL_6_UNUSED_1_BB_SHIFT                                                         20
+#define PCIEIP_REG_REG_PHY_CTL_7_BB                                                                          0x00181cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_INTV_BB                                                       (0xf<<0) // b0000: select pseudo-random value between 1 to 15 b0001 to b1111 : specify a fixed value
+  #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_INTV_BB_SHIFT                                                 0
+  #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_PRESCALE_BB                                                   (0x7<<4) // b000 : prescale = 2**2 of clock periods (~16ns) b001 : prescale = 2**3 of clock periods b010 : prescale = 2**8 of clock periods b011 : prescale = 2**12 of clock periods b100 : prescale = 2**15 of clock periods b101 : prescale = 2**18 of clock periods (~1.0ms) b110 : prescale = 2**20 of clock periods b111 : prescale = 2**21 of clock periods (~8.4ms)
+  #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_PRESCALE_BB_SHIFT                                             4
+  #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_LANE_BB                                                       (0x1f<<7) // This field selects the lanes where error is injected to. b1xxxx : random lane is chosen b01111 : lane 15 b01110 : lane 14 .... b00010 : lane 2 b00001 : lane 1 b00000 : lane 0
+  #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_LANE_BB_SHIFT                                                 7
+  #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_LOC_BB                                                        (0x3<<12) // This field has different actions based on the reg_err_inj_type field.  If reg_err_inj_type != b00 (a TLP or DLLP error): b11 : corrupt framing (start of frame or end of frame, whichever is first) b10 : corrupt start of frame (STP or SDP. b01 : corrupt end of frame b00 : corrupt data in frame (second symbol)  If reg_err_inj_type == b00 for transmit errors (ordered sets): b11 : corrupt next logical idle data on the lane rom below b10 : corrupt the last symbol of the ordered set on the lane from below b01 : corrupt the first symbol other than com on the lane from below b00 : corrupt the COM symbol on the lane from below  If reg_err_inj_type == b00 for receive errors (serdes errors): b11 : inject disparity error on the lane from below b10 : inject decode error on the lane from below b01 : inject buffer error on the lane from below b00 : inject data invalid error on the lane from below
+  #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_LOC_BB_SHIFT                                                  12
+  #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_TYPE_BB                                                       (0x3<<14) // b11 : Reserved b10 : DLLP error b01 : TLP error b00 : Ordered set error for TX or Serdes error for RX
+  #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_TYPE_BB_SHIFT                                                 14
+  #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_TX_ENA_BB                                                     (0x1<<16) // Inject transmit DLLP/TLP error or ordered set error.
+  #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_TX_ENA_BB_SHIFT                                               16
+  #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_RX_ENA_BB                                                     (0x1<<17) // Inject receive DLLP/TLP error or serdes error.
+  #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_RX_ENA_BB_SHIFT                                               17
+  #define PCIEIP_REG_REG_PHY_CTL_7_UNUSED_1_BB                                                               (0x1fff<<18) // Reserved - always write 0
+  #define PCIEIP_REG_REG_PHY_CTL_7_UNUSED_1_BB_SHIFT                                                         18
+  #define PCIEIP_REG_REG_PHY_CTL_7_REG_DIS_DESKEW_AFTER_ALIGN_ERR_BB                                         (0x1<<31) // When cleared (the default), Gen3 block alignment errors and invalid data result in the link being declared unusable since data alignment is lost. When set, the legacy behavior is maintained and no retrain will occur, with the possiblity of incorrect training and fall back to lower speeds.
+  #define PCIEIP_REG_REG_PHY_CTL_7_REG_DIS_DESKEW_AFTER_ALIGN_ERR_BB_SHIFT                                   31
+#define PCIEIP_REG_PHY_ERR_ATTN_VEC_BB                                                                       0x001820UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PHY_ERR_ATTN_VEC_ELASTIC_ERR_BB                                                         (0x1<<0) // If set, either an elastic buffer overflow or underflow (in the Serdes)
+  #define PCIEIP_REG_PHY_ERR_ATTN_VEC_ELASTIC_ERR_BB_SHIFT                                                   0
+  #define PCIEIP_REG_PHY_ERR_ATTN_VEC_DISPARITY_ERR_BB                                                       (0x1<<1) // If set, a disparity error occurred in the Serdes WC 0
+  #define PCIEIP_REG_PHY_ERR_ATTN_VEC_DISPARITY_ERR_BB_SHIFT                                                 1
+  #define PCIEIP_REG_PHY_ERR_ATTN_VEC_DECODE_ERR_BB                                                          (0x1<<2) // If set, an 8b10b decode error occurred in the Serdes
+  #define PCIEIP_REG_PHY_ERR_ATTN_VEC_DECODE_ERR_BB_SHIFT                                                    2
+  #define PCIEIP_REG_PHY_ERR_ATTN_VEC_LINK_IS_SKEW_BB                                                        (0x1<<3) // If set, the link needed to be deskewed
+  #define PCIEIP_REG_PHY_ERR_ATTN_VEC_LINK_IS_SKEW_BB_SHIFT                                                  3
+  #define PCIEIP_REG_PHY_ERR_ATTN_VEC_TRAIN_ERR_BB                                                           (0x1<<4) // If set, the link needed to be retrained
+  #define PCIEIP_REG_PHY_ERR_ATTN_VEC_TRAIN_ERR_BB_SHIFT                                                     4
+  #define PCIEIP_REG_PHY_ERR_ATTN_VEC_L0S_MAIN_ERR_BB                                                        (0x1<<5) // Receiver training error in L0S
+  #define PCIEIP_REG_PHY_ERR_ATTN_VEC_L0S_MAIN_ERR_BB_SHIFT                                                  5
+  #define PCIEIP_REG_PHY_ERR_ATTN_VEC_RETRAIN_REQ_BB                                                         (0x1<<6) // Request to retrain received from a higher layer
+  #define PCIEIP_REG_PHY_ERR_ATTN_VEC_RETRAIN_REQ_BB_SHIFT                                                   6
+  #define PCIEIP_REG_PHY_ERR_ATTN_VEC_CC_ERR_STATUS_BB                                                       (0x1<<7) // Clock Compensation deskew error.
+  #define PCIEIP_REG_PHY_ERR_ATTN_VEC_CC_ERR_STATUS_BB_SHIFT                                                 7
+  #define PCIEIP_REG_PHY_ERR_ATTN_VEC_UNUSED_1_BB                                                            (0xf<<8) // Reserved - only write 0
+  #define PCIEIP_REG_PHY_ERR_ATTN_VEC_UNUSED_1_BB_SHIFT                                                      8
+  #define PCIEIP_REG_PHY_ERR_ATTN_VEC_UNUSED_2_BB                                                            (0xfffff<<12) // 
+  #define PCIEIP_REG_PHY_ERR_ATTN_VEC_UNUSED_2_BB_SHIFT                                                      12
+#define PCIEIP_REG_PHY_ERR_ATTN_MASK_BB                                                                      0x001824UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_ELASTIC_ERR_BB                                                   (0x1<<0) // If set, masks ELASTIC_ERR from generating attention. If clear, ELASTIC_ERR generates attention
+  #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_ELASTIC_ERR_BB_SHIFT                                             0
+  #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_DISPARITY_ERR_BB                                                 (0x1<<1) // If set, masks DISPARITY_ERR from generating attention. If clear, DISPARITY_ERR generates attention
+  #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_DISPARITY_ERR_BB_SHIFT                                           1
+  #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_DECODE_ERR_BB                                                    (0x1<<2) // If set, masks DECODE_ERR from generating attention. If clear, DECODE_ERR generates attention
+  #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_DECODE_ERR_BB_SHIFT                                              2
+  #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_LINK_IS_SKEW_BB                                                  (0x1<<3) // If set, masks LINK_IS_SKEW from generating attention. If clear, LINK_IS_SKEW generates attention
+  #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_LINK_IS_SKEW_BB_SHIFT                                            3
+  #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_TRAIN_ERR_BB                                                     (0x1<<4) // If set, masks TRAIN_ERR from generating attention. If clear, TRAIN_ERR generates attention RW 1
+  #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_TRAIN_ERR_BB_SHIFT                                               4
+  #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_L0S_MAIN_ERROR_BB                                                (0x1<<5) // If set, masks L0S_MAIN_ERR from generating attention. If clear, L0S_MAIN_ERR generates attention
+  #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_L0S_MAIN_ERROR_BB_SHIFT                                          5
+  #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_RETRAIN_REQ_BB                                                   (0x1<<6) // If set, masks RETRAIN_REQ from generating attention. If clear, RETRAIN_REQ generates attention
+  #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_RETRAIN_REQ_BB_SHIFT                                             6
+  #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_CC_ERR_STATUS_BB                                                 (0x1<<7) // If set, masks Clock Compensation deskew error from generating attn. If clear, Clock Compensation deskew error generates attn.
+  #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_CC_ERR_STATUS_BB_SHIFT                                           7
+  #define PCIEIP_REG_PHY_ERR_ATTN_MASK_UNUSED_1_BB                                                           (0xf<<8) // Reserved - only write 0
+  #define PCIEIP_REG_PHY_ERR_ATTN_MASK_UNUSED_1_BB_SHIFT                                                     8
+  #define PCIEIP_REG_PHY_ERR_ATTN_MASK_UNUSED_2_BB                                                           (0xfffff<<12) // 
+  #define PCIEIP_REG_PHY_ERR_ATTN_MASK_UNUSED_2_BB_SHIFT                                                     12
+#define PCIEIP_REG_REG_PHY_CTL_8_BB                                                                          0x001830UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_LOSE_DESKEW_ON_FIFO_BB                                                (0x1<<0) // Enable loss of lane alignment on deskew/clkcomp FIFO errors.
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_LOSE_DESKEW_ON_FIFO_BB_SHIFT                                          0
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_BLOCK_REALIGN_BB                                             (0x1<<1) // Enable request to the Serdes to realign blocks.
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_BLOCK_REALIGN_BB_SHIFT                                       1
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_FRAMERR_RETRAIN_BB                                           (0x1<<2) // Enable retraining on any Gen3 framing error.
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_FRAMERR_RETRAIN_BB_SHIFT                                     2
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_DIS_BLOCK_ALIGN_ERR_BB                                           (0x1<<3) // Disable error and retrain for block alignment error from Serdes.
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_DIS_BLOCK_ALIGN_ERR_BB_SHIFT                                     3
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_BLOCK_ALIGN_ERR_DLY_BB                                           (0xf<<4) // Delay value for block alignment error (deassertion of RxValid from the Serdes indicating loss of block alignment) before the link is retrained. This is to allow any EIOS to be seen since EIOS first is not an error.
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_BLOCK_ALIGN_ERR_DLY_BB_SHIFT                                     4
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_FIXED_DATA_WIDTH_BB                                              (0x1<<8) // *** Do not modify!! Enable 16-bit data for all rates.
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_FIXED_DATA_WIDTH_BB_SHIFT                                        8
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_ENA_EIOS_DET_ELECIDLE_BB                                              (0x1<<9) // Enable the EIOS detector to mask out data.
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_ENA_EIOS_DET_ELECIDLE_BB_SHIFT                                        9
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_DIS_SCRAM_BB                                                     (0x1<<10) // Disable scrambling in Gen3.
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_DIS_SCRAM_BB_SHIFT                                               10
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_TX_STALL_BB                                                  (0x1<<11) // *** Do not modify!! Enable transmitting Gen3 stalls (null data or deassertion of the TxDataValid signals periodically).
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_TX_STALL_BB_SHIFT                                            11
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_MCP_G3_ALLOW_DATA_LOCK_BB                                             (0x1<<12) // Allow locking to the data blocks in Gen3 Modified Compliance Pattern
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_MCP_G3_ALLOW_DATA_LOCK_BB_SHIFT                                       12
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_DIS_RESTORE_REVERSAL_BB                                          (0x1<<13) // When retraining to enter compliance, the lane assignments, polarity reversal, and lane reversal information is saved, then restored. This bit disables the restoration of the lane reversal since it wasn't explicitly stated.
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_DIS_RESTORE_REVERSAL_BB_SHIFT                                    13
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_CLR_FREEZE_DESKEW_BB                                                  (0x1<<14) // Clear the block aligner debug information frozen on an aligner error. Set, then clear immediately.
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_CLR_FREEZE_DESKEW_BB_SHIFT                                            14
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_DIS_SKIP_FIX_BB                                                  (0x1<<15) // Disable the logic that corrects for misaligned deassertions of RxDataValid (in other words, null data is inserted on different relative blocks and the logic fixes that to a limited extent).
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_DIS_SKIP_FIX_BB_SHIFT                                            15
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_ENA_RECOV_TSX_BB                                                      (0x1<<16) // Enable mixed consecutive TS1s and TS2s for Recovery.RcvrLock transitions
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_ENA_RECOV_TSX_BB_SHIFT                                                16
+  #define PCIEIP_REG_REG_PHY_CTL_8_UNUSED_1_BB                                                               (0x3<<17) // Reserved - only write 0
+  #define PCIEIP_REG_REG_PHY_CTL_8_UNUSED_1_BB_SHIFT                                                         17
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_071_EQ_TIMEOUTS_BB                                           (0x1<<19) // Enable updated timeouts for Recovery.Equalization phases (now 12 ms for 0 and 1, 32 ms for 3).
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_071_EQ_TIMEOUTS_BB_SHIFT                                     19
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_EIOS_DET_MIN_TIME_BB                                                  (0xf<<20) // Minimum time (in PCLKs) to wait for EI exit using the EIOS detector
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_EIOS_DET_MIN_TIME_BB_SHIFT                                            20
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_071_LOADBOARD_BB                                                 (0x1<<24) // Enable TX preset encoding for value b1010 in CLB/CBB environments
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_071_LOADBOARD_BB_SHIFT                                           24
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_CFG_IEI_4MS_BB                                               (0x1<<25) // Enable 4 ms inferred electrical idle in Recovery.RcvrCfg at 8 GT/s
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_CFG_IEI_4MS_BB_SHIFT                                         25
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_CFGSPEED_128X_TS2_BB                                         (0x1<<26) // Enable transmission of 128 TS2s in Recovery.RcvrCfg prior to transition to Recovery.Speed (instead of 32 TS2s in 0.70 revision).
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_CFGSPEED_128X_TS2_BB_SHIFT                                   26
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_071_COMPLPAT_BB                                              (0x1<<27) // Enable the updated version fo the Gen3 Compliance pattern generation rather than the 0.70 version.
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_071_COMPLPAT_BB_SHIFT                                        27
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_DCBAL_INSERT_BB                                              (0x1<<28) // Enable insertion of DC balance symbols on the transmitted training sequences.
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_DCBAL_INSERT_BB_SHIFT                                        28
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_DCBAL_RESTORE_BB                                             (0x1<<29) // Enable correction of DC balance symbols on the received training sequences.
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_DCBAL_RESTORE_BB_SHIFT                                       29
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_INGORE_USER_ALLOW_GEN3_BB                                        (0x1<<30) // Ignore the "strap" setting for user_allow_gen3.
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_INGORE_USER_ALLOW_GEN3_BB_SHIFT                                  30
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_FORCE_G3_ADV_BB                                                  (0x1<<31) // Force initial setting of Gen3 advertisement.
+  #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_FORCE_G3_ADV_BB_SHIFT                                            31
+#define PCIEIP_REG_REG_PHY_CTL_9_BB                                                                          0x001834UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_CLR_STICKY_ERRS_BB                                               (0xfffff<<0) // Clear the corresponding bits indicating Gen3 errors reported in offset 0x1d34, bits [19:0].
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_CLR_STICKY_ERRS_BB_SHIFT                                         0
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_BAD_EDS_BB                                                   (0x1<<20) // Enable a bad/misplaced End-of-Data-Stream token as a framing/receiver error
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_BAD_EDS_BB_SHIFT                                             20
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_BAD_SYM_CNT_ERR_BB                                           (0x1<<21) // Enable bad block count as a framing/receiver error
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_BAD_SYM_CNT_ERR_BB_SHIFT                                     21
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_SYNCHEADER_ERR_BB                                            (0x1<<22) // Enable invalid sync header as a framing/receiver error
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_SYNCHEADER_ERR_BB_SHIFT                                      22
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_BAD_LEN_ERR_BB                                               (0x1<<23) // Enable the auxilliary bad TLP length to be reported as a framing/receiver error.
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_BAD_LEN_ERR_BB_SHIFT                                         23
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_BADSYNC_ALWAYS_BB                                                (0x1<<24) // Enable the auxilliary bad sync header to be reported as an error in all cases.
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_BADSYNC_ALWAYS_BB_SHIFT                                          24
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_L0_ALIGN_ERR_BB                                                  (0x1<<25) // Enable the auxilliary alignment error to be reported as a framing/receiver error in L0.
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_L0_ALIGN_ERR_BB_SHIFT                                            25
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ALL_ALIGN_ERR_BB                                                 (0x1<<26) // Enable the auxilliary alignment error to be reported as a framing/receiver error in Configuration and Recovery as well as L0.
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ALL_ALIGN_ERR_BB_SHIFT                                           26
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_BLOCK_LANE_ERR_BB                                            (0x1<<27) // Enable bad sync header errors as lane status errors in the Secondary PCIE structure.
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_BLOCK_LANE_ERR_BB_SHIFT                                      27
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_AUX_FRAMERR_RETRAIN_BB                                           (0x1<<28) // Enable auxilliary framing errors to cause a retrain (if framing errors are enabled for retraining).
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_AUX_FRAMERR_RETRAIN_BB_SHIFT                                     28
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_SKIPDATA_ERR_BB                                              (0x1<<29) // Enable generation of an error if the skipped/null data misaligns.
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_SKIPDATA_ERR_BB_SHIFT                                        29
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_DIS_PARITY_ERR_BB                                                (0x1<<30) // Disable reporting Gen3 data parity errors in the Secondary PCIE structure.
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_DIS_PARITY_ERR_BB_SHIFT                                          30
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_IDLE_START_ERR_BB                                            (0x1<<31) // Eanble error when idle symbols appear in the DW before a TLP or DLLP
+  #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_IDLE_START_ERR_BB_SHIFT                                      31
+#define PCIEIP_REG_REG_PHY_CTL_10_BB                                                                         0x001838UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_GEN3_EQ_TSX_BB                                              (0x1<<0) // Disable transmission of the equalization TS1s and TS2s.
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_GEN3_EQ_TSX_BB_SHIFT                                        0
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_LOCAL_DEEMPH_HI_BB                                                   (0x7<<1) // Upper three bits of the local deephasis setting in cases where no presets are received from the link partner.
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_LOCAL_DEEMPH_HI_BB_SHIFT                                             1
+  #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED_5_BB                                                              (0x1<<4) // 
+  #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED_5_BB_SHIFT                                                        4
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_EQ_QUIESCE_GUARANTEE_BB                                         (0x1<<5) // Software sets if it can disable data traffic during re-equalization.
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_EQ_QUIESCE_GUARANTEE_BB_SHIFT                                   5
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_EQ_NO_REDO_BB                                                   (0x1<<6) // Disable redo
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_EQ_NO_REDO_BB_SHIFT                                             6
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DEFAULT_PRESET_BB                                               (0xf<<7) // Default preset for advertisement.
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DEFAULT_PRESET_BB_SHIFT                                         7
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_EQ_REQUEST_ON_REDO_BB                                       (0x1<<11) // Disable equalization request on redo.
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_EQ_REQUEST_ON_REDO_BB_SHIFT                                 11
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_REQUEST_EQUALIZATION_BB                                         (0x1<<12) // Software can request that the link partner initiates equalization.
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_REQUEST_EQUALIZATION_BB_SHIFT                                   12
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_EQ_REQUEST_FROM_PHY_BB                                      (0x1<<13) // Disable requests from the Serdes to request equalization.
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_EQ_REQUEST_FROM_PHY_BB_SHIFT                                13
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_MATCH_SYM6_BB                                                   (0x1<<14) // Enable symbol 6 (TS1 or TS2) matching requirements for consecutive TS1s or TS2s.
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_MATCH_SYM6_BB_SHIFT                                             14
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_MATCH_PARITY_BB                                                 (0x1<<15) // Enable parity matching for Gen3 TS1s, symbols 6 through 9
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_MATCH_PARITY_BB_SHIFT                                           15
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_EQUALIZATION_BB                                             (0x1<<16) // Disable Gen3 equalization.
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_EQUALIZATION_BB_SHIFT                                       16
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_EQ_TIMERS_BB                                                (0x1<<17) // For debug purposes, disable timeouts from Recovery.Equalization phases.
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_EQ_TIMERS_BB_SHIFT                                          17
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_DLP_HOLD_CLEAR_BB                                           (0x1<<18) // Clear indication that a DLP was received on change to Gen3.
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_DLP_HOLD_CLEAR_BB_SHIFT                                     18
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_TX_DLP_HOLDOFF_BB                                           (0x1<<19) // Hold off sending DLPs until equalization is complete
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_TX_DLP_HOLDOFF_BB_SHIFT                                     19
+  #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED_4_BB                                                              (0x1<<20) // 
+  #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED_4_BB_SHIFT                                                        20
+  #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED_2_BB                                                              (0x1<<21) // 
+  #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED_2_BB_SHIFT                                                        21
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_EC3_ECHO_PRESET_BB                                          (0x1<<22) // enable echo preset bit in Phase 3
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_EC3_ECHO_PRESET_BB_SHIFT                                    22
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_CLR_RCFG_PRESETS_BB                                             (0x1<<23) // Clear previously received presets on entry to Recovery.RcvrCfg
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_CLR_RCFG_PRESETS_BB_SHIFT                                       23
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_LPBK_EC23_ENA_BB                                                (0x1<<24) // In Gen3 Loopback Slave shall take the transmitter setting specified by the received TS1 if the EC field is set to 2'b10 or 2'b11 depending on whether Slave is an RC or EP respectively. When this bit is set to '1', Slave takes the settings when EC is either 2'10 or 2'11.
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_LPBK_EC23_ENA_BB_SHIFT                                          24
+  #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED_BB                                                                (0x1<<25) // 
+  #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED_BB_SHIFT                                                          25
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_PH2_PRESETS_BB                                              (0x1<<26) // Disable presets in Phase 2 (raw data to Serdes)
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_PH2_PRESETS_BB_SHIFT                                        26
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_EQ_TS1_BB                                                   (0x1<<27) // Enable transmisssion of EQ TS1s (mainly for RC functionality)
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_EQ_TS1_BB_SHIFT                                             27
+  #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED_1_BB                                                              (0x1<<28) // Reserved - only write 0
+  #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED_1_BB_SHIFT                                                        28
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_TXEC_DELAY_BB                                               (0x1<<29) // Disable timeout counter delay waiting for EC bits to change in equalization
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_TXEC_DELAY_BB_SHIFT                                         29
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_EC2_EXIT_ON_TXEC3_BB                                        (0x1<<30) // Enable exiting Phase 2 only on Tx of EC=2'b11 regardless of what is received
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_EC2_EXIT_ON_TXEC3_BB_SHIFT                                  30
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_PH2_MATCH_PRESETS_BB                                        (0x1<<31) // Enable preset vs ceofficient matching during Phase 2 based on Serdes request
+  #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_PH2_MATCH_PRESETS_BB_SHIFT                                  31
+#define PCIEIP_REG_REG_PHY_CTL_11_BB                                                                         0x00183cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_EIDL_DELAY_G3_BB                                                     (0x1f<<0) // Delay value for raw electrical idle to sig detect in Gen3 mode
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_EIDL_DELAY_G3_BB_SHIFT                                               0
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_SPDUP_TIMER_20X_BB                                              (0x1<<5) // 20x timer speedup for use with Gen3 uC equalization
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_SPDUP_TIMER_20X_BB_SHIFT                                        5
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_SPDUP_TIMER_50X_BB                                              (0x1<<6) // 50x timer speedup for use with Gen3 uC equalization
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_SPDUP_TIMER_50X_BB_SHIFT                                        6
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_MATCH_EQ_SYM1TO5_BB                                             (0x1<<7) // For Gen3 TS1s in Equalization, match symbols 1 to 5 as well
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_MATCH_EQ_SYM1TO5_BB_SHIFT                                       7
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_DCBAL_SOS_BB                                                (0x1<<8) // Enable SOS data DC balance accumulation
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_DCBAL_SOS_BB_SHIFT                                          8
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ALIGN_DESKEW_SERDES_BB                                          (0x1<<9) // Enable Gen3 redo deskew on request from Serdes
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ALIGN_DESKEW_SERDES_BB_SHIFT                                    9
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ALIGN_DESKEW_PIPE_BB                                            (0x1<<10) // Enable Gen3 redo deskew on PIPE misalignment issues
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ALIGN_DESKEW_PIPE_BB_SHIFT                                      10
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ALIGN_DESKEW_FRAME_BB                                           (0x1<<11) // Enable Gen3 redo deskew on framing/post-deskew alignment issues
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ALIGN_DESKEW_FRAME_BB_SHIFT                                     11
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_L0SL1_FAIL_RLOCK_BB                                         (0x1<<12) // Assert signal to PHY when idle_to_rlock transition is taken.
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_L0SL1_FAIL_RLOCK_BB_SHIFT                                   12
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_L0SL1_FAIL_RXL0S_BB                                         (0x1<<13) // Assert signal to PHY when Rx_L0s times out
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_L0SL1_FAIL_RXL0S_BB_SHIFT                                   13
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_L0SL1_FAIL_TMOUT_BB                                         (0x1<<14) // Enable the L1 failure on 24 ms timeout in R.Lock
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_L0SL1_FAIL_TMOUT_BB_SHIFT                                   14
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ONLY_L0SL1_FAIL_BB                                              (0x1<<15) // Use the l0s/l1 failure signal only for Gen3
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ONLY_L0SL1_FAIL_BB_SHIFT                                        15
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ONLY_PHY_L1_ACTIVE_BB                                           (0x1<<16) // Use the phy l1 active signal only for Gen3
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ONLY_PHY_L1_ACTIVE_BB_SHIFT                                     16
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_ANY_EQTS2_BB                                                (0x1<<17) // Select between requiring all EQ TS2s or any EQ TS2 to set start_eq_w_preset
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_ANY_EQTS2_BB_SHIFT                                          17
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_BLOCK_ALIGN_RCFG_RESET_BB                                       (0x1<<18) // Reset needed flops on block align during Recovery.RcvrCfg
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_BLOCK_ALIGN_RCFG_RESET_BB_SHIFT                                 18
+  #define PCIEIP_REG_REG_PHY_CTL_11_UNUSED_BB                                                                (0x1<<19) // 
+  #define PCIEIP_REG_REG_PHY_CTL_11_UNUSED_BB_SHIFT                                                          19
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PRESET_MISMATCH_BB                                          (0x1<<20) // Enable check for mismatch of presets in R.Lock after equalization
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PRESET_MISMATCH_BB_SHIFT                                    20
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PHYLINKUP_HOLDOFF_BB                                        (0x1<<21) // Enable PhyLinkUp holdoff in Gen3 (for InitFC vs UpdateFC issue)
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PHYLINKUP_HOLDOFF_BB_SHIFT                                  21
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PH3_PRESET_COEFF_BB                                         (0x1<<22) // (PL_FIX_05) Enable preset-coefficient lookup for EQ Phase 3
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PH3_PRESET_COEFF_BB_SHIFT                                   22
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PH2_TXRX_PRESET_MATCH_BB                                    (0x1<<23) // (PL_FIX_05) Tx/Rx presets in phase 2 must match before preset signal to Serdes asserted
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PH2_TXRX_PRESET_MATCH_BB_SHIFT                              23
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_DEFAULT_RX_PRESET_BB                                            (0x7<<24) // (PL_FIX_14) Default Rx preset to send to the Serdes if no EQ TS2s
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_DEFAULT_RX_PRESET_BB_SHIFT                                      24
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_EPTX_EQTS2_BB                                                   (0x1<<27) // (PL_FIX_15) For a possible ECN, send EQ TS2s
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_EPTX_EQTS2_BB_SHIFT                                             27
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_EPTX_EQTS2_REDO_BB                                              (0x1<<28) // (PL_FIX_15) For a possible ECN, send EQ TS2s as an endpoint when redoing equalization
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_EPTX_EQTS2_REDO_BB_SHIFT                                        28
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PHYIEI_EIOS_BB                                              (0x1<<29) // Enable Serdes IEI signal on internal EIOS detect
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PHYIEI_EIOS_BB_SHIFT                                        29
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PHYIEI_EI_BB                                                (0x1<<30) // Enable Serdes IEI signal on internal EI detect
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PHYIEI_EI_BB_SHIFT                                          30
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PHYIEI_IEI_BB                                               (0x1<<31) // Enable Serdes IEI signal on internal IEI
+  #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PHYIEI_IEI_BB_SHIFT                                         31
+#define PCIEIP_REG_REG_PHY_CTL_12_BB                                                                         0x001840UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_ADDR_BB                                                       (0x3f<<0) // SED read address start
+  #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_ADDR_BB_SHIFT                                                 0
+  #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_AUTOINC_BB                                                    (0x1<<6) // SED read address auto-increment
+  #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_AUTOINC_BB_SHIFT                                              6
+  #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_CLR_ADDR_BB                                                   (0x1<<7) // SED clear read address to 0
+  #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_CLR_ADDR_BB_SHIFT                                             7
+  #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_SEL_BB                                                        (0xf<<8) // SED fill/write select (Default for LTSSM)
+  #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_SEL_BB_SHIFT                                                  8
+  #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_CLR_BB                                                        (0x1<<12) // Clear SED memory and write address
+  #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_CLR_BB_SHIFT                                                  12
+  #define PCIEIP_REG_REG_PHY_CTL_12_UNUSED_2_BB                                                              (0x7<<13) // 
+  #define PCIEIP_REG_REG_PHY_CTL_12_UNUSED_2_BB_SHIFT                                                        13
+  #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_SEL_CONFIG_BB                                                 (0xff<<16) // SED configuration
+  #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_SEL_CONFIG_BB_SHIFT                                           16
+  #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_SEL_CONFIG_ADDR_BB                                            (0xf<<24) // SED address selection for multiple options for field [23:16]
+  #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_SEL_CONFIG_ADDR_BB_SHIFT                                      24
+  #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_TRIG_HOLD_BB                                                  (0x1<<28) // Hold off SED triggering
+  #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_TRIG_HOLD_BB_SHIFT                                            28
+  #define PCIEIP_REG_REG_PHY_CTL_12_REG_GEN3_ENA_PH1_FS_LF_BB                                                (0x1<<29) // [DEBUG_BIT}: Captures internal defined FS and LF values when receive use preset = 1 in EQ Phase 1
+  #define PCIEIP_REG_REG_PHY_CTL_12_REG_GEN3_ENA_PH1_FS_LF_BB_SHIFT                                          29
+  #define PCIEIP_REG_REG_PHY_CTL_12_UNUSED_1_BB                                                              (0x3<<30) // 
+  #define PCIEIP_REG_REG_PHY_CTL_12_UNUSED_1_BB_SHIFT                                                        30
+#define PCIEIP_REG_REG_PHY_CTL_13_BB                                                                         0x001844UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_LUT_ENTRY_5_TO_0_BB                                      (0x3f<<0) // Pre-cursor for the coefficient set
+  #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_LUT_ENTRY_5_TO_0_BB_SHIFT                                0
+  #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_LUT_ENTRY_11_TO_6_BB                                     (0x3f<<6) // Main cursor for the coefficient set
+  #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_LUT_ENTRY_11_TO_6_BB_SHIFT                               6
+  #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_LUT_ENTRY_17_TO_12_BB                                    (0x3f<<12) // Post-cursor for the coefficient set
+  #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_LUT_ENTRY_17_TO_12_BB_SHIFT                              12
+  #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_LUT_INDEX_BB                                             (0xf<<18) // Index for reading/writing the Preset LUT (number of the preset)
+  #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_LUT_INDEX_BB_SHIFT                                       18
+  #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_LUT_WRSTB_BB                                             (0x1<<22) // Write strobe for Preset LUT
+  #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_LUT_WRSTB_BB_SHIFT                                       22
+  #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_SERDES_PRESET_SEL_BB                                            (0x1<<23) // Conbtrol bit to select the default preset to use in phase2 advertizement provided on pcie_rx_linkevalfm signal from Serdes to MAC
+  #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_SERDES_PRESET_SEL_BB_SHIFT                                      23
+  #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_EQ_REQ_VAL_BB                                            (0xf<<24) // programmable preset value advertized by the EP to the Link partner-RC Transmitter in Phase2 EQ programmable preset value advertized by the RC to the Link partner-EP Transmitter in Phase3 EQ
+  #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_EQ_REQ_VAL_BB_SHIFT                                      24
+  #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_USE_PRESET_EQ2_REQ_BB                                           (0x1<<28) // Use programmable preset Phase2 EQ in EP mode
+  #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_USE_PRESET_EQ2_REQ_BB_SHIFT                                     28
+  #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_USE_COEFF_EQ2_REQ_BB                                            (0x1<<29) // [DEBUG_BIT]: use programmable coefficients in Phase2 EQ
+  #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_USE_COEFF_EQ2_REQ_BB_SHIFT                                      29
+  #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_EN_LP_COEFF_MATCH_BB                                            (0x1<<30) // enable LP coeffcient match checking in default/noraml Phase2 EQ
+  #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_EN_LP_COEFF_MATCH_BB_SHIFT                                      30
+  #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_ENA_PH2_PRESET_COEFF_BB                                         (0x1<<31) // [DEBUG_BIT]: enable conversion of preset to coefficients to serdes when LP is always a preset use Phase2 EQ
+  #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_ENA_PH2_PRESET_COEFF_BB_SHIFT                                   31
+#define PCIEIP_REG_REG_PHY_CTL_14_BB                                                                         0x001848UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EQTS2_PRESET_BB                                                 (0xf<<0) // (PL_FIX_15) Transmitter preset to transmit in EP EQ TS2s
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EQTS2_PRESET_BB_SHIFT                                           0
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EQTS2_RXHINT_BB                                                 (0x7<<4) // (PL_FIX_15) Receiver preset hint to transmit in EP EQ TS2s
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EQTS2_RXHINT_BB_SHIFT                                           4
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_EQ0_TO_BB                                             (0x1<<7) // [SEMI_FUNCTIONAL]: Extend EQ until Phase0 timeout for Normal EQ handshaking
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_EQ0_TO_BB_SHIFT                                       7
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_EQ1_TO_BB                                             (0x1<<8) // [SEMI_FUNCTIONAL]: Extend EQ until Phase1 timeout for Normal EQ handshaking
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_EQ1_TO_BB_SHIFT                                       8
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_EQ2_TO_BB                                             (0x1<<9) // [SEMI_FUNCTIONAL]: Extend EQ until Phase2 timeout for Normal EQ handshaking
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_EQ2_TO_BB_SHIFT                                       9
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_EQ3_TO_BB                                             (0x1<<10) // [SEMI_FUNCTIONAL]: Extend EQ until Phase3 timeout for Normal EQ handshaking
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_EQ3_TO_BB_SHIFT                                       10
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_DIS_EQ_PH0_TIMEOUT_BB                                           (0x1<<11) // Disable timeout for Equalization Phase0
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_DIS_EQ_PH0_TIMEOUT_BB_SHIFT                                     11
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_DIS_EQ_PH1_TIMEOUT_BB                                           (0x1<<12) // Disable timeout for Equalization Phase1
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_DIS_EQ_PH1_TIMEOUT_BB_SHIFT                                     12
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_DIS_EQ_PH2_TIMEOUT_BB                                           (0x1<<13) // Disable timeout for Equalization Phase2
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_DIS_EQ_PH2_TIMEOUT_BB_SHIFT                                     13
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_DIS_EQ_PH3_TIMEOUT_BB                                           (0x1<<14) // Disable timeout for Equalization Phase3
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_DIS_EQ_PH3_TIMEOUT_BB_SHIFT                                     14
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_L1ONLY_RECOVLOCK_TO_BB                                (0x1<<15) // [SEMI_FUNCTIONAL]: Extend timeout in RecovRecvrLock State through L1 exit recovery
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_L1ONLY_RECOVLOCK_TO_BB_SHIFT                          15
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_RECOVLOCK_TO_BB                                       (0x1<<16) // [SEMI_FUNCTIONAL]: Extend timeout in RecovRecvrLock State through any exit recovery
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_RECOVLOCK_TO_BB_SHIFT                                 16
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_PRGM_RECOVLOCK_TO_SEL_BB                              (0x1<<17) // [SEMI_FUNCTIONAL]: Extend programmable timeout select control in RecovRecvrLock State
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_PRGM_RECOVLOCK_TO_SEL_BB_SHIFT                        17
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_PRGM_RECOVLOCK_TO_VALUE_BB                            (0x1f<<18) // [SEMI_FUNCTIONAL]: Extend programmable timeout value in RecovRecvrLock State
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_PRGM_RECOVLOCK_TO_VALUE_BB_SHIFT                      18
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_PH2_EVAL_WAIT_DELAY_BB                                          (0x1ff<<23) // programmable wait delay in Phase2 of equalization
+  #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_PH2_EVAL_WAIT_DELAY_BB_SHIFT                                    23
+#define PCIEIP_REG_REG_PHY_CTL_15_BB                                                                         0x00184cUL //Access:RW   DataWidth:0x20   // 
+#define PCIEIP_REG_REG_PHY_CTL_16_BB                                                                         0x001854UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN12_DEEMPH_ENTRY_BB                                                (0x3ffff<<0) // Gen1/Gen2 deemphasis register control programming of coefficients for preset-0(-6dB) and preset-1(-3.5dB) in the format {C+1[5:0],C0[5:0],C_1[5:0]}
+  #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN12_DEEMPH_ENTRY_BB_SHIFT                                          0
+  #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN12_DEEMPH_INDEX_BB                                                (0x1<<18) // Gen1/Gen2 deemphasis register control programming index for preset 0 and 1 0: points to the preset 0 coefficients(-6dB) 1: points to the preset 1 coefficients(-3.5dB)
+  #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN12_DEEMPH_INDEX_BB_SHIFT                                          18
+  #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN12_DEEMPH_WRSTB_BB                                                (0x1<<19) // Gen1/Gen2 deemphasis register control programming write strobe for Preset 0 and 1
+  #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN12_DEEMPH_WRSTB_BB_SHIFT                                          19
+  #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN12_DEEMPH_SEL_BB                                                  (0x1<<20) // Gen2 deemphasis register select control bit to change from Preset-1(-3.5dB) to preset-0(-6dB)
+  #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN12_DEEMPH_SEL_BB_SHIFT                                            20
+  #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN123_DEEMPH_PRESET_SEL_BB                                          (0x1<<21) // Select control bit for the read status of the gen1/2 and gen2 lut entry 18-bit value poining to the corresponding index. 0: Selects Gen3 read preset lut pointing to the reg_gen3_preset_lut_index value 1: Selects Gen1/2 read preset lut pointing to the reg_gen12_deemph_index value
+  #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN123_DEEMPH_PRESET_SEL_BB_SHIFT                                    21
+  #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN3_IGNORE_SERDES_EVALDC_BB                                         (0x1<<22) // [DEBUG_BIT]: Ignore serdes direction change and controls from the MAC register
+  #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN3_IGNORE_SERDES_EVALDC_BB_SHIFT                                   22
+  #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN3_OVERRIDE_SERDES_EVALDC_VAL_BB                                   (0x3f<<23) // [DEBUG_BITS]: Direction change value for coeff evaluation from the MAC control register
+  #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN3_OVERRIDE_SERDES_EVALDC_VAL_BB_SHIFT                             23
+  #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN3_EC2_EN_COEFFPR_MATCHREJ_TWOTS1_BB                               (0x1<<29) // [DEBUG_BIT]: Phase2: Controls enabling of the two consecutive EQ TS1's for checking preset and coefficient matches
+  #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN3_EC2_EN_COEFFPR_MATCHREJ_TWOTS1_BB_SHIFT                         29
+  #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN3_EC3_EN_COEFFPR_MATCHREJ_TWOTS1_BB                               (0x1<<30) // [DEBUG_BIT]: Phase3: Controls enabling of the two consecutive EQ TS1's for checking preset and coefficient matches
+  #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN3_EC3_EN_COEFFPR_MATCHREJ_TWOTS1_BB_SHIFT                         30
+  #define PCIEIP_REG_REG_PHY_CTL_16_REG_CLR_RECOV_EQ_SM_HIST_BB                                              (0x1<<31) // [DEBUG_BIT]: clears the previous statate transitions captured for recovery eq statemachine in ph2(EP) and ph3(RC)
+  #define PCIEIP_REG_REG_PHY_CTL_16_REG_CLR_RECOV_EQ_SM_HIST_BB_SHIFT                                        31
+#define PCIEIP_REG_REG_PHY_CTL_17_BB                                                                         0x001858UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_PRECTRL_LSB_EN_BB                                   (0x1<<0) // AFE TX deemphasis register override enable control bit for prectrl[1:0] LSB two bits
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_PRECTRL_LSB_EN_BB_SHIFT                             0
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_PRE_CTRL_LSB_VAL_BB                                 (0x3<<1) // AFE TX deemphasis register control two LSB bit value for prectrl[1:0]
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_PRE_CTRL_LSB_VAL_BB_SHIFT                           1
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_MAIN_LSB_EN_BB                                      (0x1<<3) // AFE TX deemphasis register override enable control bit for main[1:0] LSB two bits
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_MAIN_LSB_EN_BB_SHIFT                                3
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_MAIN_LSB_VAL_BB                                     (0x3<<4) // AFE TX deemphasis register control two LSB bit value for main[1:0]
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_MAIN_LSB_VAL_BB_SHIFT                               4
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_POSTCTRL_LSB_EN_BB                                  (0x1<<6) // AFE TX deemphasis register override enable control bit for postctrl[1:0] LSB two bits
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_POSTCTRL_LSB_EN_BB_SHIFT                            6
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_POSTCTRL_LSB_VAL_BB                                 (0x3<<7) // AFE TX deemphasis register control two LSB bit value for postctrl[1:0]
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_POSTCTRL_LSB_VAL_BB_SHIFT                           7
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_PRE_CTRL_UPPER_EN_BB                                          (0x1<<9) // AFE TX deemphasis register override enable control bit for prectrl[4:2] upper three bits
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_PRE_CTRL_UPPER_EN_BB_SHIFT                                    9
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_PRE_CTRL_UPPER_VAL_BB                                         (0x7<<10) // AFE TX deemphasis register control upper three bit value for prectrl[4:2]
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_PRE_CTRL_UPPER_VAL_BB_SHIFT                                   10
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_MAIN_CTRL_UPPER_EN_BB                                         (0x1<<13) // AFE TX deemphasis register override enable control bit for main[4:2] upper five bits
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_MAIN_CTRL_UPPER_EN_BB_SHIFT                                   13
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_MAIN_CTRL_UPPER_VAL_BB                                        (0x1f<<14) // AFE TX deemphasis register control upper five bit value for main[6:2]
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_MAIN_CTRL_UPPER_VAL_BB_SHIFT                                  14
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_POST_CTRL_UPPER_EN_BB                                         (0x1<<19) // AFE TX deemphasis register override enable control bit for postctrl[5:2] upper four bits
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_POST_CTRL_UPPER_EN_BB_SHIFT                                   19
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_POST_CTRL_UPPER_VAL_BB                                        (0xf<<20) // AFE TX deemphasis register control upper four bit value for postctrl[5:2]
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_POST_CTRL_UPPER_VAL_BB_SHIFT                                  20
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_POST2_EN_BB                                         (0x1<<24) // AFE TX deemphasis register override enable control bit for post2[3:0] four bits
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_POST2_EN_BB_SHIFT                                   24
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_POST2_VAL_BB                                        (0xf<<25) // AFE TX deemphasis register control for four bit value for post2[3:0]
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_POST2_VAL_BB_SHIFT                                  25
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN3_SKIP_PH2_RXEVAL_TO_SERDES_BB                                    (0x1<<29) // Phase2: Skips Rx EQ evaluation to Serdes and wait for 22msec extended timeout to occur.
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN3_SKIP_PH2_RXEVAL_TO_SERDES_BB_SHIFT                              29
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN3_SKIP_PH3_RXEVAL_TO_SERDES_BB                                    (0x1<<30) // Phase3: Skips Rx EQ evaluation to Serdes and wait for 22msec extended timeout to occur.
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN3_SKIP_PH3_RXEVAL_TO_SERDES_BB_SHIFT                              30
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN3_RX_RESET_EIEOS_BB                                               (0x1<<31) // RX reset EIEOS control bit for TS1(SYM6-Bit2) in Recovery.Equalizations. Default zero value
+  #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN3_RX_RESET_EIEOS_BB_SHIFT                                         31
+#define PCIEIP_REG_REG_PHY_CTL_18_BB                                                                         0x00185cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EQ_FS_EN_BB                                                     (0x1<<0) // Enable bit to control the registered programmed FULL SWING value in Phase 1 of eualization
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EQ_FS_EN_BB_SHIFT                                               0
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EQ_FS_VAL_BB                                                    (0x3f<<1) // Registered programmed 6-bit FULL SWING value in Phase 1 of eualization. The hardware default value 6'h28(FS=40).
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EQ_FS_VAL_BB_SHIFT                                              1
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EQ_LF_EN_BB                                                     (0x1<<7) // Enable bit to control the registered programmed LOW FREQUENCY value in Phase 1 of eualization
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EQ_LF_EN_BB_SHIFT                                               7
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EQ_LF_VAL_BB                                                    (0x3f<<8) // Registered programmed 6-bit LOW FREQUENCY value in Phase 1 of eualization. The hardware default value 6'hC(LF=12).
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EQ_LF_VAL_BB_SHIFT                                              8
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC2_RX_COEFF_SEL_BB                                             (0x1<<14) // Selects to the received coefficients in the phase 2 of equalization. The default coefficientis a defined value.
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC2_RX_COEFF_SEL_BB_SHIFT                                       14
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC2_DISABLE_REQ_WAIT_1USEC_BB                                   (0x1<<15) // [DEBUG_BIT]: Disables the 1usec wait time for LP to response for preset or coeff req in phase2(EP and phase3(RC) modes..
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC2_DISABLE_REQ_WAIT_1USEC_BB_SHIFT                             15
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_ENA_EC0_ECHO_PRESET_BB                                          (0x1<<16) // Enables EC0 echo use preset bit in EP mode
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_ENA_EC0_ECHO_PRESET_BB_SHIFT                                    16
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_RC_ENA_EC2_ECHO_PRESET_BB                                       (0x1<<17) // Enables EC2 echo use preset bit in RC mode
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_RC_ENA_EC2_ECHO_PRESET_BB_SHIFT                                 17
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_RC_USE_PRESET_EQ3_REQ_BB                                        (0x1<<18) // Use programmable preset Phase3 EQ in RC mode
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_RC_USE_PRESET_EQ3_REQ_BB_SHIFT                                  18
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC2_IGNORE_USE_PRESET_CHECK_BB                                  (0x1<<19) // [DEBUG_BIT]: Ignore the receive ec2 use preset check in phase2 of equalization for the eq eval state machine
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC2_IGNORE_USE_PRESET_CHECK_BB_SHIFT                            19
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_PH3_DIS_RULE_CHECK_BB                                           (0x1<<20) // [DEBUG_BIT]: Disables Preset and coefficient rule check error in phase 3 of equalization in EP mode
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_PH3_DIS_RULE_CHECK_BB_SHIFT                                     20
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_PH2_DIS_RULE_CHECK_BB                                           (0x1<<21) // [DEBUG_BIT]: Disables Preset and coefficient rule check error in phase 2 of equalization in RC mode
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_PH2_DIS_RULE_CHECK_BB_SHIFT                                     21
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_IGNORE_USE_PRESET_REDO_CHECK_BB                                 (0x1<<22) // [DEBUG_BIT]: Ignores the phase 2 received usepreset bit when checking for preset mismatch at the end of equalization
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_IGNORE_USE_PRESET_REDO_CHECK_BB_SHIFT                           22
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_RC_SKIP_EQ_PHASE23_BB                                           (0x1<<23) // RC Mode: Skips equalizationphas 2 and Phase 3.
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_RC_SKIP_EQ_PHASE23_BB_SHIFT                                     23
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC2_DIS_EVAL_COEFF_MATCH_BB                                     (0x1<<24) // [DEBUG_BIT]: EP mode Phase2: Disables the coefficient match reject status in EVAL and Adjust eval states
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC2_DIS_EVAL_COEFF_MATCH_BB_SHIFT                               24
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC3_DIS_EVAL_COEFF_MATCH_BB                                     (0x1<<25) // [DEBUG_BIT]: RC mode Phase3: Disables the coefficient match reject status in EVAL and Adjust eval states
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC3_DIS_EVAL_COEFF_MATCH_BB_SHIFT                               25
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_RC_FORCE_EQ_EVERY_SPDCHG_BB                                     (0x1<<26) // [DEBUG_BIT]: RC mode : Forces Gen3 equalization for every Speed change over from Gen1-Gen3
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_RC_FORCE_EQ_EVERY_SPDCHG_BB_SHIFT                               26
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_EQ_STATIC_DEBUG_ADDR_BB                                              (0x1f<<27) // [DEBUG_BITS]: Equalization static debug 5-bit address control for reading pl_eq_static_debug data at address 0x1d94
+  #define PCIEIP_REG_REG_PHY_CTL_18_REG_EQ_STATIC_DEBUG_ADDR_BB_SHIFT                                        27
+#define PCIEIP_REG_PL_GEN3_ENA_FRMERR_BB                                                                     0x001860UL //Access:RW   DataWidth:0x20   // Notes: There are more Gen3 framing error enable bits in reg_phy_ctl_9 register.
+  #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_ILLEGAL_OS_AFTER_EDS_ERR_BB                                 (0x1<<0) // Enable Illegal Ordered Set After EDS Error. When this bit is set to '1', report Gen3 framing error if an OS other than EIOS, EIEOS, or SKPOS is detected after an EDS token.
+  #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_ILLEGAL_OS_AFTER_EDS_ERR_BB_SHIFT                           0
+  #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_OS_AFTER_SDS_ERR_BB                                         (0x1<<1) // Enable Ordered Set After SDS Error. When this bit is set to '1', report Gen3 framing error if an OS is detected right after an SDS token.
+  #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_OS_AFTER_SDS_ERR_BB_SHIFT                                   1
+  #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_OS_NO_EDS_ERR_BB                                            (0x1<<2) // Enable Ordered Set with No EDS Error. When this bit is set to '1', report Gen3 framing error if an OS is detected without a preceding EDS token while in middle of a data stream.
+  #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_OS_NO_EDS_ERR_BB_SHIFT                                      2
+  #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_BAD_FCRC_ERR_BB                                             (0x1<<3) // Enable Bad Framing CRC Error. When this bit is set to '1', report Gen3 framing error if bad framing CRC is detected in a STP token.
+  #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_BAD_FCRC_ERR_BB_SHIFT                                       3
+  #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_BAD_FP_ERR_BB                                               (0x1<<4) // Enable Bad Framing Parity Error. When this bit is set to '1', report Gen3 framing error if bad framing parity is detected in a STP token.
+  #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_BAD_FP_ERR_BB_SHIFT                                         4
+  #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_BAD_EDB_ERR_BB                                              (0x1<<5) // Enable Bad EDB Error. When this bit is set to '1', report Gen3 framing error if a bad EDB token is detected.
+  #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_BAD_EDB_ERR_BB_SHIFT                                        5
+  #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_BAD_FRAMING_SYM_ERR_BB                                      (0x1<<6) // Enable Bad Framing Symbol Error. When this bit is set to '1', report Gen3 framing error if a framing token is not detected at the expection position.
+  #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_BAD_FRAMING_SYM_ERR_BB_SHIFT                                6
+  #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_DATA_AFTER_EDS_ERR_BB                                       (0x1<<7) // Enable Data After EDS Error. When this bit is set to '1', report Gen3 framing error if a data block is detected after an EDS token.
+  #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_DATA_AFTER_EDS_ERR_BB_SHIFT                                 7
+#define PCIEIP_REG_PL_LPBK_MASTER_CTL0_BB                                                                    0x001900UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_ENA_BB                                                  (0x1<<0) // Loopback Master Enable. Setting this bit to '1' enables the master loopback operation. Normally, if lpbk_master_len is set to '0', software has to clear this bit to stop the operation. Otherwise, hardware automatically clears this bit when the operation is done. In case the loopback operation is timeout during Loopback.Entry state, hardware clears this bit before returning to Detect state regardless of the setting of lpbk_master_len.
+  #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_ENA_BB_SHIFT                                            0
+  #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_ENTRY_BB                                                (0x1<<1) // Loopback Master Entry State. If this bit is set to '1', loopback is entered from Recovery.Idle state; otherwise, loopback is entered from Configuration.Linkwidth.Start state.
+  #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_ENTRY_BB_SHIFT                                          1
+  #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_SET_COMPL_RECV_BB                                       (0x1<<2) // Loopback Master Set Compliance Receive. If this bit is set to '1', the Compliance Receive bit in TS1 is set to '1' when loopback master initiates the loopback operation. This feature allows Loopback Slave to enter Loopback.Active state without achieving symbol lock or block alignment.
+  #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_SET_COMPL_RECV_BB_SHIFT                                 2
+  #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_AUTO_COMPL_RECV_BB                                      (0x1<<3) // Loopback Master Automatically Set Compliance Receive. If this bit is set to '1', hardware automatically sets the Compliance Receive bit in TS1 to '1' during Loopback.Entry state when loopback is entered from Configuration.Linkwidth.Start state and Gen3 is the highest common speed.
+  #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_AUTO_COMPL_RECV_BB_SHIFT                                3
+  #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_FRC_SETTING_BB                                          (0x1<<4) // Loopback Master Force Setting. When loopback is entered from Recov.Idle state and this bit is set to '1', hardware applies the settings specified in lpbk_master_slave_setting and lpbak_master_tx_setting registers.
+  #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_FRC_SETTING_BB_SHIFT                                    4
+  #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_SKPOS_BB                                                (0x1<<5) // Loopback Master Skip Ordered Set. When this bit is set, SKP OS are periodically inserted to loopback data. If data is generated by PHY, MAC provides SKP OS to PHY using a req/ack handshake. If it is Gen3 and data is generated by PHY without framing, this bit is ignored.
+  #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_SKPOS_BB_SHIFT                                          5
+  #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_ONE_SKPOS_BB                                            (0x1<<6) // Loopback Master One Skip Ordered Set. PCIE Spec requires that in Gen3 loopback master inserts two SKIP ordered sets for each SKIP OS interval. For testing purpose, when this bit is set to '1', hardware inserts only one SKP OS for each interval.
+  #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_ONE_SKPOS_BB_SHIFT                                      6
+  #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_UNUSED_2_BB                                                         (0x1<<7) // 
+  #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_UNUSED_2_BB_SHIFT                                                   7
+  #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_PATTERN_BB                                              (0x1f<<8) // Loopback Master Pattern. This field specifies the data pattern to be transmitted during Loopback.Active state. 5'b00000: reserved  5'b00001: Serdes PRBS7 pattern  5'b00010: Serdes PRBS15 pattern  5'b00011: Serdes PRBS23 pattern  5'b00100: Serdes PRBS31 pattern  5'b00101: Serdes 1010 pattern  5'b00110: Serdes 1100 pattern  5'b00111: Serdes low frequency pattern  5'b01000: reserved  5'b01001: Serdes PRBS7 pattern (with framing for Gen3)  5'b01010: Serdes PRBS15 pattern (with framing for Gen3)  5'b01011: Serdes PRBS23 pattern (with framing for Gen3)  5'b01100: Serdes PRBS31 pattern (with framing for Gen3)  5'b01101: Serdes 1010 pattern (with framing for Gen3)  5'b01110: Serdes 1100 pattern (with framing for Gen3)  5'b01111: Serdes low frequency pattern (with framing for Gen3)  5'b10000: MAC Compliance pattern  5'b10001: MAC Modified Compliance pattern  Others : reserved
+  #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_PATTERN_BB_SHIFT                                        8
+  #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_UNUSED_1_BB                                                         (0x7<<13) // 
+  #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_UNUSED_1_BB_SHIFT                                                   13
+  #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_LEN_BB                                                  (0xffff<<16) // Loopback Master Length. This field specifies the length of the loopback operation in milliseconds. When it is set to '0', software has to clear the lpbk_master_ena bit to stop the operation. When it is set to a non-zero value, hardware automatically clears the lpbk_master_ena bit after the specified time.
+  #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_LEN_BB_SHIFT                                            16
+#define PCIEIP_REG_PL_LPBK_MASTER_CTL1_BB                                                                    0x001904UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PL_LPBK_MASTER_CTL1_LPBK_MASTER_ENTRY_TMOUT_BB                                          (0x7f<<0) // Loopback Master Entry Timeout. While in Loopback.Entry state, if Compliance Receive bit was not set in transmitting TS1 and Loopback Master doesn't receive the feedback from Loopback Slave, it will transition to Detect state after a specified time. This field specifies the timeout in milliseconds. The timeout value must be less than 100ms.
+  #define PCIEIP_REG_PL_LPBK_MASTER_CTL1_LPBK_MASTER_ENTRY_TMOUT_BB_SHIFT                                    0
+#define PCIEIP_REG_PL_LPBK_MASTER_STAT_BB                                                                    0x001908UL //Access:R    DataWidth:0x20   // The loopback status register is cleared when lpbk_master_ena goes from '0' to '1'.
+  #define PCIEIP_REG_PL_LPBK_MASTER_STAT_LPBK_MASTER_STAT_BB                                                 (0x1<<0) // Loopback Master Status. This is the status of the last loopback operation. 1'b0: completed normally 1'b1: exited because of timeout during Loopback.Entry state
+  #define PCIEIP_REG_PL_LPBK_MASTER_STAT_LPBK_MASTER_STAT_BB_SHIFT                                           0
+#define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_BB                                                           0x00190cUL //Access:RW   DataWidth:0x20   // This register specifies the Slave's TX settings that Loopback Master will transmit in TS1 during Loopback.Entry state in following cases: 1. Entered from Configuration.Linkwidth.Start and changed to a new speed. 2. Entered from Recovery.Idle and bit lpbk_master_frc_setting is set to '1'. If data rate is Gen3, Loopback Master will automatically set EC field (i.e. TS1, byte6[1:0]) to 2'b10 or 2'b11 depending on whether it is EP or RC respectively.
+  #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_RXPRESET_BB                                (0x7<<0) // Loopback Master TS1 Receiver Preset Hint. This value is sent in TS1, byte6[2:0] if current rate is Gen1/Gen2 and EQ TS1's are sent.
+  #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_RXPRESET_BB_SHIFT                          0
+  #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_TXPRESET_BB                                (0xf<<3) // Loopback Master TS1 Transmitter Preset. This value is sent in TS1, byte6[6:3] if the current rate is Gen3 or current rate is Gen1/2 and EQ TS1's are sent.
+  #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_TXPRESET_BB_SHIFT                          3
+  #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_USEPRESET_BB                               (0x1<<7) // Loopback Master TS1 Use Preset. This value is sent in TS1, byte6[7] if the current rate is Gen3.
+  #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_USEPRESET_BB_SHIFT                         7
+  #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_PRECURSOR_BB                               (0x3f<<8) // Loopback Master TS1 Pre-Cursor Coefficient. This value is sent in TS1, byte7[5:0] if the current rate is Gen3.
+  #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_PRECURSOR_BB_SHIFT                         8
+  #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_CURSOR_BB                                  (0x3f<<14) // Loopback Master TS1 Cursor Coefficient. This value is sent in TS1, byte8[5:0] if the current rate is Gen3.
+  #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_CURSOR_BB_SHIFT                            14
+  #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_POSTCURSOR_BB                              (0x3f<<20) // Loopback Master TS1 Post-cursor Coefficient. This value is sent in TS1, byte9[5:0] if the current rate is Gen3.
+  #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_POSTCURSOR_BB_SHIFT                        20
+  #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_G2_DEEMPH_BB                               (0x1<<26) // Loopback Master TS1 Selectable De-emphasis. This value is sent in TS1, byte4[6] if the highest common rate is Gen2.
+  #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_G2_DEEMPH_BB_SHIFT                         26
+#define PCIEIP_REG_PL_LPBK_MASTER_TX_SETTING_BB                                                              0x001910UL //Access:RW   DataWidth:0x20   // This register specifies the Loopback Master TX settings in following cases: 1. Entered from Configuration.Linkwidth.Start and changed to a new speed. 2. Entered from Recovery.Idle and bit lpbk_master_frc_setting is set to '1'.
+  #define PCIEIP_REG_PL_LPBK_MASTER_TX_SETTING_LPBK_MASTER_G3_TXDEEMPH_BB                                    (0x3ffff<<0) // Loopback Master Gen3 TX Deemphasis. This TX setting is used when loopback is in Gen3 rate.
+  #define PCIEIP_REG_PL_LPBK_MASTER_TX_SETTING_LPBK_MASTER_G3_TXDEEMPH_BB_SHIFT                              0
+  #define PCIEIP_REG_PL_LPBK_MASTER_TX_SETTING_LPBK_MASTER_G2_TXDEEMPH_BB                                    (0x3<<18) // Loopback Master Gen2 Deemphasis. This TX setting is used when loopback is in Gen2 rate. Notes that for Gen1 the TX deemphasis is always set to -3.5db.
+  #define PCIEIP_REG_PL_LPBK_MASTER_TX_SETTING_LPBK_MASTER_G2_TXDEEMPH_BB_SHIFT                              18
+#define PCIEIP_REG_PL_SW_LTSSM_CTL_BB                                                                        0x001930UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_ENA_BB                                                         (0x1<<0) // Software LTSSM Enable. Setting this bit to '1' allows software to take control of the LTSSM.
+  #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_ENA_BB_SHIFT                                                   0
+  #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_DLYSTART_BB                                                    (0x1<<1) // Software LTSSM Delay Start. When this bit is set together with sw_ltssm_ena, hardware continues to operate as normal until LTSSM reaches to the state specified by sw_ltssm_topst and sw_ltssm_subst. Once software starts controlling LTSSM, it continues to do so until sw_ltssm_ena is reset to '0'. This feature allows software to control LTSSM in some certain states but not all.
+  #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_DLYSTART_BB_SHIFT                                              1
+  #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_UPDT_BB                                                        (0x1<<2) // Software LTSSM Update. Writing a '1' to this bit updates the internal software LTSSM state with the state specified by sw_ltssm_topst and sw_ltssm_subst. If software is in control, the new state will be applied to LTSSM. This bit is self-cleared, so reading always retuns '0'.
+  #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_UPDT_BB_SHIFT                                                  2
+  #define PCIEIP_REG_PL_SW_LTSSM_CTL_LTSSM_TMOUT_DIS_BB                                                      (0x1<<3) // LTSSM Timeout Disable. When this bit is set to '1', all LTSSM timeouts are disabled.
+  #define PCIEIP_REG_PL_SW_LTSSM_CTL_LTSSM_TMOUT_DIS_BB_SHIFT                                                3
+  #define PCIEIP_REG_PL_SW_LTSSM_CTL_UNUSED0_BB                                                              (0xf<<4) // 
+  #define PCIEIP_REG_PL_SW_LTSSM_CTL_UNUSED0_BB_SHIFT                                                        4
+  #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_SUBST_BB                                                       (0x1ff<<8) // Software LTSSM Sub-level State. This field specifies the state of the sub-level state machine that software wants LTSSM to enter. The updating sub-level SM is selected based on the top-level state.
+  #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_SUBST_BB_SHIFT                                                 8
+  #define PCIEIP_REG_PL_SW_LTSSM_CTL_UNUSED1_BB                                                              (0x7<<17) // 
+  #define PCIEIP_REG_PL_SW_LTSSM_CTL_UNUSED1_BB_SHIFT                                                        17
+  #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_TOPST_BB                                                       (0x1ff<<20) // Software LTSSM Top-level State. This field specifies the state of the top-level state machine that software wants LTSSM to enter.
+  #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_TOPST_BB_SHIFT                                                 20
+  #define PCIEIP_REG_PL_SW_LTSSM_CTL_UNUSED2_BB                                                              (0x3<<29) // 
+  #define PCIEIP_REG_PL_SW_LTSSM_CTL_UNUSED2_BB_SHIFT                                                        29
+  #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_INT_ENA_BB                                                     (0x1<<31) // Software LTSSM Internal Enable. This bit reflects the internal software LTSSM enable that is set to '1' only when S/W is actually in control of the LTSSM. If sw_ltssm_dlystart is '1', the internal enable is not set until LTSSM reaches the desired state.
+  #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_INT_ENA_BB_SHIFT                                               31
+#define PCIEIP_REG_PCIE_STATIS_CTL_BB                                                                        0x001940UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PCIE_STATIS_CTL_PCIE_STATIS_ENA_BB                                                      (0x1<<0) // PCIE Statistic Enable. Setting this bit to '1' enables the PCIE statistic collection. Hardware will count various things such as the number of TLP, DLLP, OS bytes transferred in both RX and TX direction, the number of detected errors etc. When this bit is reset to '0', the counting stops and software can read the results. This bit can be automatically cleared after the specified time if pcie_statis_len is non-zero. All statistic read-back registers are cleared when this bit transitions from '0' to '1'.
+  #define PCIEIP_REG_PCIE_STATIS_CTL_PCIE_STATIS_ENA_BB_SHIFT                                                0
+  #define PCIEIP_REG_PCIE_STATIS_CTL_UNUSED0_BB                                                              (0x7f<<1) // 
+  #define PCIEIP_REG_PCIE_STATIS_CTL_UNUSED0_BB_SHIFT                                                        1
+  #define PCIEIP_REG_PCIE_STATIS_CTL_PCIE_STATIS_LEN_BB                                                      (0xffffff<<8) // PCIE Statistic Length. This field specifies the PCIE statistic collection time in microseconds. When it is set to '0', software has to clear the pcie_statis_ena bit to stop the operation. When it is set to a non-zero value, hardware automatically clears the enable bit after the specified time.
+  #define PCIEIP_REG_PCIE_STATIS_CTL_PCIE_STATIS_LEN_BB_SHIFT                                                8
+#define PCIEIP_REG_PCIE_TXTLP_STATIS_LO_BB                                                                   0x001944UL //Access:R    DataWidth:0x20   // PCIE TX TLP Statistic Low 32 bits. This is the number of TLP bytes that have been trasmitted. It is cleared when pcie_statis_ena goes from '0' to '1'.
+#define PCIEIP_REG_PCIE_TXTLP_STATIS_HI_BB                                                                   0x001948UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PCIE_TXTLP_STATIS_HI_PCIE_TXTLP_STATIS_HI_BB                                            (0xff<<0) // PCIE TX TLP Statistic High 8 bits. This is the number of TLP bytes that have been trasmitted. It is cleared when pcie_statis_ena goes from '0' to '1'.
+  #define PCIEIP_REG_PCIE_TXTLP_STATIS_HI_PCIE_TXTLP_STATIS_HI_BB_SHIFT                                      0
+#define PCIEIP_REG_PCIE_TXDLLP_STATIS_LO_BB                                                                  0x00194cUL //Access:R    DataWidth:0x20   // PCIE TX DLLP Statistic Low 32 bits. This is the number of DLLP bytes that have been trasmitted. It is cleared when pcie_statis_ena goes from '0' to '1'.
+#define PCIEIP_REG_PCIE_TXDLLP_STATIS_HI_BB                                                                  0x001950UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PCIE_TXDLLP_STATIS_HI_PCIE_TXDLLP_STATIS_HI_BB                                          (0xff<<0) // PCIE TX DLLP Statistic High 8 bits. This is the number of DLLP bytes that have been trasmitted. It is cleared when pcie_statis_ena goes from '0' to '1'.
+  #define PCIEIP_REG_PCIE_TXDLLP_STATIS_HI_PCIE_TXDLLP_STATIS_HI_BB_SHIFT                                    0
+#define PCIEIP_REG_PCIE_TXOS_STATIS_LO_BB                                                                    0x001954UL //Access:R    DataWidth:0x20   // PCIE TX Ordered Set Statistic Low 32 bits. This is the number of ordered set bytes that have been trasmitted. It is cleared when pcie_statis_ena goes from '0' to '1'.
+#define PCIEIP_REG_PCIE_TXOS_STATIS_HI_BB                                                                    0x001958UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PCIE_TXOS_STATIS_HI_PCIE_TXOS_STATIS_HI_BB                                              (0xff<<0) // PCIE TX Ordered Set Statistic High 8 bits. This is the number of ordered set bytes that have been trasmitted. It is cleared when pcie_statis_ena goes from '0' to '1'.
+  #define PCIEIP_REG_PCIE_TXOS_STATIS_HI_PCIE_TXOS_STATIS_HI_BB_SHIFT                                        0
+#define PCIEIP_REG_PCIE_RXTLP_STATIS_LO_BB                                                                   0x00195cUL //Access:R    DataWidth:0x20   // PCIE RX TLP Statistic Low 32 bits. This is the number of TLP bytes that have been received. It is cleared when pcie_statis_ena goes from '0' to '1'.
+#define PCIEIP_REG_PCIE_RXTLP_STATIS_HI_BB                                                                   0x001960UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PCIE_RXTLP_STATIS_HI_PCIE_RXTLP_STATIS_HI_BB                                            (0xff<<0) // PCIE RX TLP Statistic High 8 bits. This is the number of TLP bytes that have been received. It is cleared when pcie_statis_ena goes from '0' to '1'.
+  #define PCIEIP_REG_PCIE_RXTLP_STATIS_HI_PCIE_RXTLP_STATIS_HI_BB_SHIFT                                      0
+#define PCIEIP_REG_PCIE_RXDLLP_STATIS_LO_BB                                                                  0x001964UL //Access:R    DataWidth:0x20   // PCIE RX DLLP Statistic Low 32 bits. This is the number of DLLP bytes that have been received. It is cleared when pcie_statis_ena goes from '0' to '1'.
+#define PCIEIP_REG_PCIE_RXDLLP_STATIS_HI_BB                                                                  0x001968UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PCIE_RXDLLP_STATIS_HI_PCIE_RXDLLP_STATIS_HI_BB                                          (0xff<<0) // PCIE RX DLLP Statistic High 8 bits. This is the number of DLLP bytes that have been received. It is cleared when pcie_statis_ena goes from '0' to '1'.
+  #define PCIEIP_REG_PCIE_RXDLLP_STATIS_HI_PCIE_RXDLLP_STATIS_HI_BB_SHIFT                                    0
+#define PCIEIP_REG_PCIE_RXOS_STATIS_LO_BB                                                                    0x00196cUL //Access:R    DataWidth:0x20   // PCIE RX Ordered Set Statistic Low 32 bits. This is the number of ordered set bytes that have been received. It is cleared when pcie_statis_ena goes from '0' to '1'.
+#define PCIEIP_REG_PCIE_RXOS_STATIS_HI_BB                                                                    0x001970UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PCIE_RXOS_STATIS_HI_PCIE_RXOS_STATIS_HI_BB                                              (0xff<<0) // PCIE RX Ordered Set Statistic High 8 bits. This is the number of ordered set bytes that have been received. It is cleared when pcie_statis_ena goes from '0' to '1'.
+  #define PCIEIP_REG_PCIE_RXOS_STATIS_HI_PCIE_RXOS_STATIS_HI_BB_SHIFT                                        0
+#define PCIEIP_REG_PCIE_PLRXERR_STATIS_BB                                                                    0x001974UL //Access:R    DataWidth:0x20   // PL Receiver Error Statistic. Number of errors detected by Physical Layer Receiver. It is cleared when pcie_statis_ena goes from '0' to '1'.
+#define PCIEIP_REG_PCIE_RXDLLPERR_STATIS_BB                                                                  0x001978UL //Access:R    DataWidth:0x20   // RX DLLP Error Statistic. Number of DLLP CRC errors detected by Data Link Layer. It is cleared when pcie_statis_ena goes from '0' to '1'.
+#define PCIEIP_REG_PCIE_RXTLPERR_STATIS_BB                                                                   0x00197cUL //Access:R    DataWidth:0x20   // RX TLP Error Statistic. Number of TLP LCRC and sequence number errors detected by Data Link Layer. It is cleared when pcie_statis_ena goes from '0' to '1'.
+#define PCIEIP_REG_LTSSM_STATIS_CTL_BB                                                                       0x0019a0UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_LTSSM_STATIS_CTL_LTSSM_STATIS_ENA_BB                                                    (0x1<<0) // LTSSM Statistic Enable. Setting this bit to '1' enables the LTSSM statisic collection. When this bit is reset to '0', information is frozen so S/W can read the results. All statistic registers are reset when this bit transitions from '0' to '1'.
+  #define PCIEIP_REG_LTSSM_STATIS_CTL_LTSSM_STATIS_ENA_BB_SHIFT                                              0
+  #define PCIEIP_REG_LTSSM_STATIS_CTL_LTSSM_STATIS_AUTOINC_BB                                                (0x1<<1) // LTSSM Statistic Auto Increment. When this bit is set to '1', hardware automatically increases the ltssm_statis_rdaddr by 1 after register ltssm_statis_N is read.
+  #define PCIEIP_REG_LTSSM_STATIS_CTL_LTSSM_STATIS_AUTOINC_BB_SHIFT                                          1
+  #define PCIEIP_REG_LTSSM_STATIS_CTL_LTSSM_STATIS_RDADDR_BB                                                 (0x1<<2) // LTSSM Statistic Readback Address. ltssm_statis_0 to ltssm_statis_N are stored in FIFOs. This field indicates the current readback address of the LTSSM Statistic FIFO. Reading ltssm_statis_0 to ltssm_statis_N registers return the values stored at current address. Software writes to this field to specify the starting FIFO offset where it wants to read back LTSSM statistic data.
+  #define PCIEIP_REG_LTSSM_STATIS_CTL_LTSSM_STATIS_RDADDR_BB_SHIFT                                           2
+#define PCIEIP_REG_LTSSM_STATIS_0_BB                                                                         0x0019a4UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_LTSSM_STATIS_0_EQ_PH1_TIME_BB                                                           (0xffff<<0) // Equalization Phase 1 Time. This field contains the time that LTSSM spent in Equalization Phase 1 state. The unit is microsecond.
+  #define PCIEIP_REG_LTSSM_STATIS_0_EQ_PH1_TIME_BB_SHIFT                                                     0
+  #define PCIEIP_REG_LTSSM_STATIS_0_EQ_PH0_TIME_BB                                                           (0xffff<<16) // Equalization Phase 0 Time. This field contains the time that LTSSM spent in Equalization Phase 0 state. The unit is microsecond.
+  #define PCIEIP_REG_LTSSM_STATIS_0_EQ_PH0_TIME_BB_SHIFT                                                     16
+#define PCIEIP_REG_LTSSM_STATIS_1_BB                                                                         0x0019a8UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_LTSSM_STATIS_1_EQ_PH3_TIME_BB                                                           (0xffff<<0) // Equalization Phase 3 Time. This field contains the time that LTSSM spent in Equalization Phase 3 state. The unit is microsecond.
+  #define PCIEIP_REG_LTSSM_STATIS_1_EQ_PH3_TIME_BB_SHIFT                                                     0
+  #define PCIEIP_REG_LTSSM_STATIS_1_EQ_PH2_TIME_BB                                                           (0xffff<<16) // Equalization Phase 2 Time. This field contains the time that LTSSM spent in Equalization Phase 2 state. The unit is microsecond.
+  #define PCIEIP_REG_LTSSM_STATIS_1_EQ_PH2_TIME_BB_SHIFT                                                     16
+#define PCIEIP_REG_LTSSM_STATIS_2_BB                                                                         0x0019acUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_LTSSM_STATIS_2_PWR_ACK_TIME_BB                                                          (0xff<<0) // Power State Acknowledge Time. This field contains the time since power state changed to when Serdes acknowledged. The unit is microsecond.
+  #define PCIEIP_REG_LTSSM_STATIS_2_PWR_ACK_TIME_BB_SHIFT                                                    0
+  #define PCIEIP_REG_LTSSM_STATIS_2_SYM_LOCK_TIME_BB                                                         (0xff<<8) // Symbol Lock Time. This field contains the time it took Serdes to achieve symbol lock after PLL locked. The unit is microsecond.
+  #define PCIEIP_REG_LTSSM_STATIS_2_SYM_LOCK_TIME_BB_SHIFT                                                   8
+  #define PCIEIP_REG_LTSSM_STATIS_2_ELECIDLE_TIME_BB                                                         (0xffff<<16) // Electrical Idle Time. This field contains the time that LTSSM spent in Electrical Idle state. The unit is microsecond.
+  #define PCIEIP_REG_LTSSM_STATIS_2_ELECIDLE_TIME_BB_SHIFT                                                   16
+#define PCIEIP_REG_LTSSM_STATIS_3_BB                                                                         0x0019b0UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_LTSSM_STATIS_3_RECOV_TIME_BB                                                            (0xffff<<0) // Recovery Time. This field contains the time that LTSSM spent in Recovery state. The unit is microsecond.
+  #define PCIEIP_REG_LTSSM_STATIS_3_RECOV_TIME_BB_SHIFT                                                      0
+  #define PCIEIP_REG_LTSSM_STATIS_3_L0S_EXIT_TIME_BB                                                         (0xff<<16) // L0s Exit Time. This field contains the time that LTSSM spent to exit L0s state. The unit is microsecond.
+  #define PCIEIP_REG_LTSSM_STATIS_3_L0S_EXIT_TIME_BB_SHIFT                                                   16
+#define PCIEIP_REG_LTSSM_STATIS_CNT_BB                                                                       0x0019b4UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_LTSSM_STATIS_CNT_RECOV_CNT_BB                                                           (0xffff<<0) // Recovery Entered Count. This field contains the number of times LTSSM entered Recovery state.
+  #define PCIEIP_REG_LTSSM_STATIS_CNT_RECOV_CNT_BB_SHIFT                                                     0
+  #define PCIEIP_REG_LTSSM_STATIS_CNT_L0S_FAIL_CNT_BB                                                        (0xff<<16) // L0s Exit Failure Count. This field contains the number of L0s exit failures (i.e. LTSSM has to transition from L0s to Recovery).
+  #define PCIEIP_REG_LTSSM_STATIS_CNT_L0S_FAIL_CNT_BB_SHIFT                                                  16
+#define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_BB                                                               0x001c00UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_ERRS_12_BB                                                 (0x7f<<0) // For lane 12: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_ERRS_12_BB_SHIFT                                           0
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_LOCK_12_BB                                                 (0x1<<7) // For lane 12: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_LOCK_12_BB_SHIFT                                           7
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_ERRS_13_BB                                                 (0x7f<<8) // For lane 13 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_ERRS_13_BB_SHIFT                                           8
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_LOCK_13_BB                                                 (0x1<<15) // For lane 13 in a multi-lane system: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_LOCK_13_BB_SHIFT                                           15
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_ERRS_14_BB                                                 (0x7f<<16) // For lane 14: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_ERRS_14_BB_SHIFT                                           16
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_LOCK_14_BB                                                 (0x1<<23) // For lane 14: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_LOCK_14_BB_SHIFT                                           23
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_ERRS_15_BB                                                 (0x7f<<24) // For lane 15 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_ERRS_15_BB_SHIFT                                           24
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_LOCK_15_BB                                                 (0x1<<31) // For lane 15 in a multi-lane system: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_LOCK_15_BB_SHIFT                                           31
+#define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_BB                                                                0x001c04UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_ERRS_8_BB                                                   (0x7f<<0) // For lane 8: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_ERRS_8_BB_SHIFT                                             0
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_LOCK_8_BB                                                   (0x1<<7) // For lane 8: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_LOCK_8_BB_SHIFT                                             7
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_ERRS_9_BB                                                   (0x7f<<8) // For lane 9 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_ERRS_9_BB_SHIFT                                             8
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_LOCK_9_BB                                                   (0x1<<15) // For lane 9 in a multi-lane system: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_LOCK_9_BB_SHIFT                                             15
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_ERRS_10_BB                                                  (0x7f<<16) // For lane 10: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_ERRS_10_BB_SHIFT                                            16
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_LOCK_10_BB                                                  (0x1<<23) // For lane 10: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_LOCK_10_BB_SHIFT                                            23
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_ERRS_11_BB                                                  (0x7f<<24) // For lane 11 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_ERRS_11_BB_SHIFT                                            24
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_LOCK_11_BB                                                  (0x1<<31) // For lane 11 in a multi-lane system: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_LOCK_11_BB_SHIFT                                            31
+#define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_BB                                                                 0x001c08UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_ERRS_4_BB                                                    (0x7f<<0) // For lane 4: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_ERRS_4_BB_SHIFT                                              0
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_LOCK_4_BB                                                    (0x1<<7) // For lane 4: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_LOCK_4_BB_SHIFT                                              7
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_ERRS_5_BB                                                    (0x7f<<8) // For lane 5 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_ERRS_5_BB_SHIFT                                              8
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_LOCK_5_BB                                                    (0x1<<15) // For lane 5 in a multi-lane system: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_LOCK_5_BB_SHIFT                                              15
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_ERRS_6_BB                                                    (0x7f<<16) // For lane 6: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_ERRS_6_BB_SHIFT                                              16
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_LOCK_6_BB                                                    (0x1<<23) // For lane 6: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_LOCK_6_BB_SHIFT                                              23
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_ERRS_7_BB                                                    (0x7f<<24) // For lane 7 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_ERRS_7_BB_SHIFT                                              24
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_LOCK_7_BB                                                    (0x1<<31) // For lane 7 in a multi-lane system: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_LOCK_7_BB_SHIFT                                              31
+#define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_BB                                                                 0x001c0cUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_ERRS_0_BB                                                    (0x7f<<0) // For lane 0: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_ERRS_0_BB_SHIFT                                              0
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_LOCK_0_BB                                                    (0x1<<7) // For lane 0: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_LOCK_0_BB_SHIFT                                              7
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_ERRS_1_BB                                                    (0x7f<<8) // For lane 1 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_ERRS_1_BB_SHIFT                                              8
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_LOCK_1_BB                                                    (0x1<<15) // For lane 1 in a multi-lane system: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_LOCK_1_BB_SHIFT                                              15
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_ERRS_2_BB                                                    (0x7f<<16) // For lane 2: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_ERRS_2_BB_SHIFT                                              16
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_LOCK_2_BB                                                    (0x1<<23) // For lane 2: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_LOCK_2_BB_SHIFT                                              23
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_ERRS_3_BB                                                    (0x7f<<24) // For lane 3 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_ERRS_3_BB_SHIFT                                              24
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_LOCK_3_BB                                                    (0x1<<31) // For lane 3 in a multi-lane system: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
+  #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_LOCK_3_BB_SHIFT                                              31
+#define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_BB                                                            0x001c10UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_ERRS_12_BB                                           (0x7f<<0) // For lane 12: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_ERRS_12_BB_SHIFT                                     0
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_LOCK_12_BB                                           (0x1<<7) // For lane 12: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_LOCK_12_BB_SHIFT                                     7
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_ERRS_13_BB                                           (0x7f<<8) // For lane 13 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_ERRS_13_BB_SHIFT                                     8
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_LOCK_13_BB                                           (0x1<<15) // For lane 13 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_LOCK_13_BB_SHIFT                                     15
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_ERRS_14_BB                                           (0x7f<<16) // For lane 14: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_ERRS_14_BB_SHIFT                                     16
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_LOCK_14_BB                                           (0x1<<23) // For lane 14: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_LOCK_14_BB_SHIFT                                     23
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_ERRS_15_BB                                           (0x7f<<24) // For lane 15 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_ERRS_15_BB_SHIFT                                     24
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_LOCK_15_BB                                           (0x1<<31) // For lane 15 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_LOCK_15_BB_SHIFT                                     31
+#define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_BB                                                             0x001c14UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_ERRS_8_BB                                             (0x7f<<0) // For lane 8: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_ERRS_8_BB_SHIFT                                       0
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_LOCK_8_BB                                             (0x1<<7) // For lane 8: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_LOCK_8_BB_SHIFT                                       7
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_ERRS_9_BB                                             (0x7f<<8) // For lane 9 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_ERRS_9_BB_SHIFT                                       8
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_LOCK_9_BB                                             (0x1<<15) // For lane 9 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_LOCK_9_BB_SHIFT                                       15
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_ERRS_10_BB                                            (0x7f<<16) // For lane 10: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_ERRS_10_BB_SHIFT                                      16
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_LOCK_10_BB                                            (0x1<<23) // For lane 10: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_LOCK_10_BB_SHIFT                                      23
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_ERRS_11_BB                                            (0x7f<<24) // For lane 11 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_ERRS_11_BB_SHIFT                                      24
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_LOCK_11_BB                                            (0x1<<31) // For lane 11 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_LOCK_11_BB_SHIFT                                      31
+#define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_BB                                                              0x001c18UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_ERRS_4_BB                                              (0x7f<<0) // For lane 4: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_ERRS_4_BB_SHIFT                                        0
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_LOCK_4_BB                                              (0x1<<7) // For lane 4: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_LOCK_4_BB_SHIFT                                        7
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_ERRS_5_BB                                              (0x7f<<8) // For lane 5 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_ERRS_5_BB_SHIFT                                        8
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_LOCK_5_BB                                              (0x1<<15) // For lane 5 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_LOCK_5_BB_SHIFT                                        15
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_ERRS_6_BB                                              (0x7f<<16) // For lane 6: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_ERRS_6_BB_SHIFT                                        16
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_LOCK_6_BB                                              (0x1<<23) // For lane 6: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_LOCK_6_BB_SHIFT                                        23
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_ERRS_7_BB                                              (0x7f<<24) // For lane 7 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_ERRS_7_BB_SHIFT                                        24
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_LOCK_7_BB                                              (0x1<<31) // For lane 7 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_LOCK_7_BB_SHIFT                                        31
+#define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_BB                                                              0x001c1cUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_ERRS_0_BB                                              (0x7f<<0) // For lane 0: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_ERRS_0_BB_SHIFT                                        0
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_LOCK_0_BB                                              (0x1<<7) // For lane 0: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_LOCK_0_BB_SHIFT                                        7
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_ERRS_1_BB                                              (0x7f<<8) // For lane 1 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_ERRS_1_BB_SHIFT                                        8
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_LOCK_1_BB                                              (0x1<<15) // For lane 1 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_LOCK_1_BB_SHIFT                                        15
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_ERRS_2_BB                                              (0x7f<<16) // For lane 2: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_ERRS_2_BB_SHIFT                                        16
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_LOCK_2_BB                                              (0x1<<23) // For lane 2: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_LOCK_2_BB_SHIFT                                        23
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_ERRS_3_BB                                              (0x7f<<24) // For lane 3 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_ERRS_3_BB_SHIFT                                        24
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_LOCK_3_BB                                              (0x1<<31) // For lane 3 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
+  #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_LOCK_3_BB_SHIFT                                        31
+#define PCIEIP_REG_RX_FTS_LIMIT_BB                                                                           0x001c20UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_RX_FTS_LIMIT_RX_FTS_LIMIT_BB                                                            (0xff<<0) // The N_FTS value advertised by the link partner
+  #define PCIEIP_REG_RX_FTS_LIMIT_RX_FTS_LIMIT_BB_SHIFT                                                      0
+  #define PCIEIP_REG_RX_FTS_LIMIT_UNUSED_1_BB                                                                (0xffffff<<8) // Reserved
+  #define PCIEIP_REG_RX_FTS_LIMIT_UNUSED_1_BB_SHIFT                                                          8
+#define PCIEIP_REG_FTS_HIST_BB                                                                               0x001cd0UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_FTS_HIST_FTS_HIST_0_BB                                                                  (0xff<<0) // Last count of recognized FTSOS
+  #define PCIEIP_REG_FTS_HIST_FTS_HIST_0_BB_SHIFT                                                            0
+  #define PCIEIP_REG_FTS_HIST_FTS_HIST_1_BB                                                                  (0xff<<8) // Count of recognized FTSOS 1 Rx_L0s ago
+  #define PCIEIP_REG_FTS_HIST_FTS_HIST_1_BB_SHIFT                                                            8
+  #define PCIEIP_REG_FTS_HIST_FTS_HIST_2_BB                                                                  (0xff<<16) // Count of recognized FTSOS 2 Rx_L0s ago
+  #define PCIEIP_REG_FTS_HIST_FTS_HIST_2_BB_SHIFT                                                            16
+  #define PCIEIP_REG_FTS_HIST_FTS_HIST_3_BB                                                                  (0xff<<24) // Count of recognized FTSOS 3 Rx_L0s ago
+  #define PCIEIP_REG_FTS_HIST_FTS_HIST_3_BB_SHIFT                                                            24
+#define PCIEIP_REG_GEN2_DEBUG_0_BB                                                                           0x001cd4UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_GEN2_DEBUG_0_GEN2_DEBUG_8_BB                                                            (0xff<<0) // Gen2 Debug History 8 transitions ago (see below for encoding)
+  #define PCIEIP_REG_GEN2_DEBUG_0_GEN2_DEBUG_8_BB_SHIFT                                                      0
+  #define PCIEIP_REG_GEN2_DEBUG_0_GEN2_DEBUG_9_BB                                                            (0xff<<8) // Gen2 Debug History 9 transitions ago (see below for encoding)
+  #define PCIEIP_REG_GEN2_DEBUG_0_GEN2_DEBUG_9_BB_SHIFT                                                      8
+  #define PCIEIP_REG_GEN2_DEBUG_0_GEN2_DEBUG_10_BB                                                           (0xff<<16) // Gen2 Debug History 10 transitions ago (see below for encoding)
+  #define PCIEIP_REG_GEN2_DEBUG_0_GEN2_DEBUG_10_BB_SHIFT                                                     16
+  #define PCIEIP_REG_GEN2_DEBUG_0_GEN2_DEBUG_11_BB                                                           (0xff<<24) // Gen2 Debug History 11 transitions ago (see below for encoding)
+  #define PCIEIP_REG_GEN2_DEBUG_0_GEN2_DEBUG_11_BB_SHIFT                                                     24
+#define PCIEIP_REG_GEN2_DEBUG_1_BB                                                                           0x001cd8UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_GEN2_DEBUG_1_GEN2_DEBUG_4_BB                                                            (0xff<<0) // Gen2 Debug History 4 transitions ago (see below for encoding)
+  #define PCIEIP_REG_GEN2_DEBUG_1_GEN2_DEBUG_4_BB_SHIFT                                                      0
+  #define PCIEIP_REG_GEN2_DEBUG_1_GEN2_DEBUG_5_BB                                                            (0xff<<8) // Gen2 Debug History 5 transitions ago (see below for encoding)
+  #define PCIEIP_REG_GEN2_DEBUG_1_GEN2_DEBUG_5_BB_SHIFT                                                      8
+  #define PCIEIP_REG_GEN2_DEBUG_1_GEN2_DEBUG_6_BB                                                            (0xff<<16) // Gen2 Debug History 6 transitions ago (see below for encoding)
+  #define PCIEIP_REG_GEN2_DEBUG_1_GEN2_DEBUG_6_BB_SHIFT                                                      16
+  #define PCIEIP_REG_GEN2_DEBUG_1_GEN2_DEBUG_7_BB                                                            (0xff<<24) // Gen2 Debug History 7 transitions ago (see below for encoding)
+  #define PCIEIP_REG_GEN2_DEBUG_1_GEN2_DEBUG_7_BB_SHIFT                                                      24
+#define PCIEIP_REG_GEN2_DEBUG_2_BB                                                                           0x001cdcUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_GEN2_DEBUG_2_GEN2_DEBUG_0_BB                                                            (0xff<<0) // Gen2 Debug History - current. Changes are recorded when any of bits [5:0] differ.
+  #define PCIEIP_REG_GEN2_DEBUG_2_GEN2_DEBUG_0_BB_SHIFT                                                      0
+  #define PCIEIP_REG_GEN2_DEBUG_2_GEN2_DEBUG_1_BB                                                            (0xff<<8) // Gen2 Debug History 1 transitions ago (see below for encoding)
+  #define PCIEIP_REG_GEN2_DEBUG_2_GEN2_DEBUG_1_BB_SHIFT                                                      8
+  #define PCIEIP_REG_GEN2_DEBUG_2_GEN2_DEBUG_2_BB                                                            (0xff<<16) // Gen2 Debug History 2 transitions ago (see below for encoding)
+  #define PCIEIP_REG_GEN2_DEBUG_2_GEN2_DEBUG_2_BB_SHIFT                                                      16
+  #define PCIEIP_REG_GEN2_DEBUG_2_GEN2_DEBUG_3_BB                                                            (0xff<<24) // Gen2 Debug History 3 transitions ago (see below for encoding)
+  #define PCIEIP_REG_GEN2_DEBUG_2_GEN2_DEBUG_3_BB_SHIFT                                                      24
+#define PCIEIP_REG_RECOVERY_HIST_0_BB                                                                        0x001ce0UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_RECOVERY_HIST_0_RECOV_HIST_4_BB                                                         (0xff<<0) // Recovery History 4 transitions ago (see below for encoding)
+  #define PCIEIP_REG_RECOVERY_HIST_0_RECOV_HIST_4_BB_SHIFT                                                   0
+  #define PCIEIP_REG_RECOVERY_HIST_0_RECOV_HIST_5_BB                                                         (0xff<<8) // Recovery History 5 transitions ago (see below for encoding)
+  #define PCIEIP_REG_RECOVERY_HIST_0_RECOV_HIST_5_BB_SHIFT                                                   8
+  #define PCIEIP_REG_RECOVERY_HIST_0_RECOV_HIST_6_BB                                                         (0xff<<16) // Recovery History 6 transitions ago (see below for encoding)
+  #define PCIEIP_REG_RECOVERY_HIST_0_RECOV_HIST_6_BB_SHIFT                                                   16
+  #define PCIEIP_REG_RECOVERY_HIST_0_RECOV_HIST_7_BB                                                         (0xff<<24) // Recovery History 7 transitions ago (see below for encoding)
+  #define PCIEIP_REG_RECOVERY_HIST_0_RECOV_HIST_7_BB_SHIFT                                                   24
+#define PCIEIP_REG_RECOVERY_HIST_1_BB                                                                        0x001ce4UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_RECOVERY_HIST_1_RECOV_HIST_0_BB                                                         (0xff<<0) // Recovery History - current. Changes are recorded when any of bits [5:0] differ.
+  #define PCIEIP_REG_RECOVERY_HIST_1_RECOV_HIST_0_BB_SHIFT                                                   0
+  #define PCIEIP_REG_RECOVERY_HIST_1_RECOV_HIST_1_BB                                                         (0xff<<8) // Recovery History 1 transitions ago (see below for encoding)
+  #define PCIEIP_REG_RECOVERY_HIST_1_RECOV_HIST_1_BB_SHIFT                                                   8
+  #define PCIEIP_REG_RECOVERY_HIST_1_RECOV_HIST_2_BB                                                         (0xff<<16) // Recovery History 2 transitions ago (see below for encoding)
+  #define PCIEIP_REG_RECOVERY_HIST_1_RECOV_HIST_2_BB_SHIFT                                                   16
+  #define PCIEIP_REG_RECOVERY_HIST_1_RECOV_HIST_3_BB                                                         (0xff<<24) // Recovery History 3 transitions ago (see below for encoding)
+  #define PCIEIP_REG_RECOVERY_HIST_1_RECOV_HIST_3_BB_SHIFT                                                   24
+#define PCIEIP_REG_PHY_LTSSM_HIST_0_BB                                                                       0x001cecUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PHY_LTSSM_HIST_0_LTSSM_HIST_12_BB                                                       (0xff<<0) // LTSSM state 12 transitions in the past
+  #define PCIEIP_REG_PHY_LTSSM_HIST_0_LTSSM_HIST_12_BB_SHIFT                                                 0
+  #define PCIEIP_REG_PHY_LTSSM_HIST_0_LTSSM_HIST_13_BB                                                       (0xff<<8) // LTSSM state 13 transitions in the past (see encoding below)
+  #define PCIEIP_REG_PHY_LTSSM_HIST_0_LTSSM_HIST_13_BB_SHIFT                                                 8
+  #define PCIEIP_REG_PHY_LTSSM_HIST_0_LTSSM_HIST_14_BB                                                       (0xff<<16) // LTSSM state 14 transitions in the past (see encoding below)
+  #define PCIEIP_REG_PHY_LTSSM_HIST_0_LTSSM_HIST_14_BB_SHIFT                                                 16
+  #define PCIEIP_REG_PHY_LTSSM_HIST_0_LTSSM_HIST_15_BB                                                       (0xff<<24) // LTSSM state 15 transitions in the past (see encoding below)
+  #define PCIEIP_REG_PHY_LTSSM_HIST_0_LTSSM_HIST_15_BB_SHIFT                                                 24
+#define PCIEIP_REG_PHY_LTSSM_HIST_1_BB                                                                       0x001cf0UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PHY_LTSSM_HIST_1_LTSSM_HIST_8_BB                                                        (0xff<<0) // LTSSM state 8 transitions in the past (see encoding above)
+  #define PCIEIP_REG_PHY_LTSSM_HIST_1_LTSSM_HIST_8_BB_SHIFT                                                  0
+  #define PCIEIP_REG_PHY_LTSSM_HIST_1_LTSSM_HIST_9_BB                                                        (0xff<<8) // LTSSM state 9 transitions in the past (see encoding above)
+  #define PCIEIP_REG_PHY_LTSSM_HIST_1_LTSSM_HIST_9_BB_SHIFT                                                  8
+  #define PCIEIP_REG_PHY_LTSSM_HIST_1_LTSSM_HIST_10_BB                                                       (0xff<<16) // LTSSM state 10 transitions in the past (see encoding above)
+  #define PCIEIP_REG_PHY_LTSSM_HIST_1_LTSSM_HIST_10_BB_SHIFT                                                 16
+  #define PCIEIP_REG_PHY_LTSSM_HIST_1_LTSSM_HIST_11_BB                                                       (0xff<<24) // LTSSM state 11 transitions in the past (see encoding above)
+  #define PCIEIP_REG_PHY_LTSSM_HIST_1_LTSSM_HIST_11_BB_SHIFT                                                 24
+#define PCIEIP_REG_PHY_LTSSM_HIST_2_BB                                                                       0x001cf4UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PHY_LTSSM_HIST_2_LTSSM_HIST_4_BB                                                        (0xff<<0) // LTSSM state 4 transitions in the past (see encoding above)
+  #define PCIEIP_REG_PHY_LTSSM_HIST_2_LTSSM_HIST_4_BB_SHIFT                                                  0
+  #define PCIEIP_REG_PHY_LTSSM_HIST_2_LTSSM_HIST_5_BB                                                        (0xff<<8) // LTSSM state 5 transitions in the past (see encoding above)
+  #define PCIEIP_REG_PHY_LTSSM_HIST_2_LTSSM_HIST_5_BB_SHIFT                                                  8
+  #define PCIEIP_REG_PHY_LTSSM_HIST_2_LTSSM_HIST_6_BB                                                        (0xff<<16) // LTSSM state 6 transitions in the past (see encoding above)
+  #define PCIEIP_REG_PHY_LTSSM_HIST_2_LTSSM_HIST_6_BB_SHIFT                                                  16
+  #define PCIEIP_REG_PHY_LTSSM_HIST_2_LTSSM_HIST_7_BB                                                        (0xff<<24) // LTSSM state 7 transitions in the past (see encoding above)
+  #define PCIEIP_REG_PHY_LTSSM_HIST_2_LTSSM_HIST_7_BB_SHIFT                                                  24
+#define PCIEIP_REG_PHY_LTSSM_HIST_3_BB                                                                       0x001cf8UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PHY_LTSSM_HIST_3_LTSSM_HIST_0_BB                                                        (0xff<<0) // Current LTSSM state (see encoding above)
+  #define PCIEIP_REG_PHY_LTSSM_HIST_3_LTSSM_HIST_0_BB_SHIFT                                                  0
+  #define PCIEIP_REG_PHY_LTSSM_HIST_3_LTSSM_HIST_1_BB                                                        (0xff<<8) // LTSSM state last transition/last LTSSM state (see encoding above)
+  #define PCIEIP_REG_PHY_LTSSM_HIST_3_LTSSM_HIST_1_BB_SHIFT                                                  8
+  #define PCIEIP_REG_PHY_LTSSM_HIST_3_LTSSM_HIST_2_BB                                                        (0xff<<16) // LTSSM state 6 transitions in the past (see encoding above)
+  #define PCIEIP_REG_PHY_LTSSM_HIST_3_LTSSM_HIST_2_BB_SHIFT                                                  16
+  #define PCIEIP_REG_PHY_LTSSM_HIST_3_LTSSM_HIST_3_BB                                                        (0xff<<24) // LTSSM state 3 transitions in the past (see encoding above)
+  #define PCIEIP_REG_PHY_LTSSM_HIST_3_LTSSM_HIST_3_BB_SHIFT                                                  24
+#define PCIEIP_REG_PHY_LTSSM_HIST_2_DUP_BB                                                                   0x001cfcUL //Access:R    DataWidth:0x20   // Duplicate of ltssm histogram entries 11, 10, 9, and 8 for compatibility
+#define PCIEIP_REG_PHY_DBG_0_BB                                                                              0x001d00UL //Access:R    DataWidth:0x20   // PHY Debug Signals
+#define PCIEIP_REG_PHY_DBG_1_BB                                                                              0x001d04UL //Access:R    DataWidth:0x20   // PHY Debug Signals
+#define PCIEIP_REG_PHY_DBG_2_BB                                                                              0x001d08UL //Access:R    DataWidth:0x20   // PHY Debug Signals
+#define PCIEIP_REG_PHY_DBG_3_BB                                                                              0x001d0cUL //Access:R    DataWidth:0x20   // PHY Debug Signals
+#define PCIEIP_REG_PHY_DBG_4_BB                                                                              0x001d10UL //Access:R    DataWidth:0x20   // PHY Debug Signals
+#define PCIEIP_REG_PHY_DBG_5_BB                                                                              0x001d14UL //Access:R    DataWidth:0x20   // PHY Debug Signals
+#define PCIEIP_REG_PHY_DBG_6_BB                                                                              0x001d18UL //Access:R    DataWidth:0x20   // PHY Debug Signals
+#define PCIEIP_REG_PHY_DBG_7_BB                                                                              0x001d1cUL //Access:R    DataWidth:0x20   // PHY Debug Signals
+#define PCIEIP_REG_PHY_DBG_8_BB                                                                              0x001d20UL //Access:R    DataWidth:0x20   // PHY Debug Signals
+#define PCIEIP_REG_PHY_DBG_9_BB                                                                              0x001d24UL //Access:R    DataWidth:0x20   // PHY Debug Signals
+#define PCIEIP_REG_PHY_DBG_10_BB                                                                             0x001d28UL //Access:R    DataWidth:0x20   // PHY Debug Signals
+#define PCIEIP_REG_PHY_DBG_11_BB                                                                             0x001d2cUL //Access:R    DataWidth:0x20   // PHY Debug Signals
+#define PCIEIP_REG_ATE_LOOPBACK_INFO_BB                                                                      0x001d30UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_ATE_LOOPBACK_INFO_UNUSED_1_BB                                                           (0x1f<<0) // The current state of the ATE loopback SM tracker:  b00011 : IDLE state - not active b00101 : Waiting for L0 state b00110 : In L0, waiting for L0 at Gen2 b01001 : In L0 at Gen2, waiting for L0s at Gen2 b01010 : In L0s at Gen2, waiting for L0s exit b01100 : Finished without error b10110 : Error while in L0, waiting for L0 at Gen2 b11001 : Error while in L0 at Gen2, waiting for L0s at Gen2 b11010 : Error while in L0s at Gen2, waiting for L0s exit
+  #define PCIEIP_REG_ATE_LOOPBACK_INFO_UNUSED_1_BB_SHIFT                                                     0
+  #define PCIEIP_REG_ATE_LOOPBACK_INFO_PCIE_PHY_GLOOPBACK_BB                                                 (0x1<<5) // Current state of the gloopback signal to the Serdes
+  #define PCIEIP_REG_ATE_LOOPBACK_INFO_PCIE_PHY_GLOOPBACK_BB_SHIFT                                           5
+  #define PCIEIP_REG_ATE_LOOPBACK_INFO_REG_GLOOPBACK_BB                                                      (0x1<<6) // Current state of the "pins" gloopback request
+  #define PCIEIP_REG_ATE_LOOPBACK_INFO_REG_GLOOPBACK_BB_SHIFT                                                6
+  #define PCIEIP_REG_ATE_LOOPBACK_INFO_UNUSED_BB                                                             (0x1ffffff<<7) // 
+  #define PCIEIP_REG_ATE_LOOPBACK_INFO_UNUSED_BB_SHIFT                                                       7
+#define PCIEIP_REG_GEN3_STICKY_ERRORS_BB                                                                     0x001d34UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_FRAMING_ERR_BB                                              (0x1<<0) // A framing error occurred
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_FRAMING_ERR_BB_SHIFT                                        0
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_FCRC_BB                                             (0x1<<1) // FCRC error in the STP token
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_FCRC_BB_SHIFT                                       1
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_FP_BB                                               (0x1<<2) // Parity error in the STP token
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_FP_BB_SHIFT                                         2
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_EDB_BB                                              (0x1<<3) // Badly formed or misplaced EDB token
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_EDB_BB_SHIFT                                        3
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_FRAMING_SYM_BB                                      (0x1<<4) // No valid framing symbol in the data stream
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_FRAMING_SYM_BB_SHIFT                                4
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_BLOCK_TYPE_BB                                       (0x1<<5) // Serdes indicated a bad block type (sync header of 00b or 11b)
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_BLOCK_TYPE_BB_SHIFT                                 5
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_ORDEREDSET_AFTER_SDS_BB                                 (0x1<<6) // An ordered set occurred after an SDS without an EDS first
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_ORDEREDSET_AFTER_SDS_BB_SHIFT                           6
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_DATA_AFTER_EDS_BB                                       (0x1<<7) // Data block occurred immediately after an EDS token
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_DATA_AFTER_EDS_BB_SHIFT                                 7
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_ORDEREDSET_NO_EDS_BB                                    (0x1<<8) // An ordered set occurred in the data stream without a prior EDS
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_ORDEREDSET_NO_EDS_BB_SHIFT                              8
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_MULT_ORDEREDSETS_BB                                     (0x1<<9) // Ordered set follows SKP ordered set after EDS
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_MULT_ORDEREDSETS_BB_SHIFT                               9
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_RETRAIN_ON_GEN3_BLOCKALIGN_BB                               (0x1<<10) // Retraining occurred due to block misalignment
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_RETRAIN_ON_GEN3_BLOCKALIGN_BB_SHIFT                         10
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_BLOCK_ALIGN_ERR_BB                                          (0x1<<11) // Block alignment error from the Serdes
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_BLOCK_ALIGN_ERR_BB_SHIFT                                    11
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_BAD_EDS_BB                                           (0x1<<12) // Misplaced or badly formed EDS token
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_BAD_EDS_BB_SHIFT                                     12
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_BAD_SYM_CNT_BB                                       (0x1<<13) // Incorrect length for a data block
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_BAD_SYM_CNT_BB_SHIFT                                 13
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_SYNCHEADER_BB                                        (0x1<<14) // Mismatch or misalignment in the sync headers
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_SYNCHEADER_BB_SHIFT                                  14
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_BAD_LEN_BB                                           (0x1<<15) // Bad Gen3 TLP length
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_BAD_LEN_BB_SHIFT                                     15
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_SKIPDATA_BB                                          (0x1<<16) // Misalignment in the null/skipped data
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_SKIPDATA_BB_SHIFT                                    16
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_BAD_SKIP_DATA_RATE_BB                                       (0x1<<17) // Too many or too few RxDataValid deassertions in 65 clocks at Gen3.
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_BAD_SKIP_DATA_RATE_BB_SHIFT                                 17
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_IDLE_START_BB                                           (0x1<<18) // Error when in the same symbol time Idle symbols appear in the DW before a TLP or a DLLP.
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_IDLE_START_BB_SHIFT                                     18
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_ILLEGAL_EDSOS_BB                                        (0x1<<19) // This bit is set to '1' when the ordered set following an EDS token is other than SKP OS, EIEOS, or EIOS.
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_ILLEGAL_EDSOS_BB_SHIFT                                  19
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_UNUSED_BB                                                            (0xfff<<20) // 
+  #define PCIEIP_REG_GEN3_STICKY_ERRORS_UNUSED_BB_SHIFT                                                      20
+#define PCIEIP_REG_PHY_DBG_POLLING_COMPL_BB                                                                  0x001d38UL //Access:R    DataWidth:0x20   // PHY Debug - Polling Compliance signals
+#define PCIEIP_REG_PHY_DBG_EQUALIZE_BB                                                                       0x001d3cUL //Access:R    DataWidth:0x20   // PHY Debug - Equalization signals
+#define PCIEIP_REG_DEBUG_DESKEW_0_BB                                                                         0x001d40UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DEBUG_DESKEW_0_DEBUG_DESKEW_LANE_14_BB                                                  (0xffff<<0) // 
+  #define PCIEIP_REG_DEBUG_DESKEW_0_DEBUG_DESKEW_LANE_14_BB_SHIFT                                            0
+  #define PCIEIP_REG_DEBUG_DESKEW_0_DEBUG_DESKEW_LANE_15_BB                                                  (0xffff<<16) // 
+  #define PCIEIP_REG_DEBUG_DESKEW_0_DEBUG_DESKEW_LANE_15_BB_SHIFT                                            16
+#define PCIEIP_REG_DEBUG_DESKEW_1_BB                                                                         0x001d44UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DEBUG_DESKEW_1_DEBUG_DESKEW_LANE_12_BB                                                  (0xffff<<0) // 
+  #define PCIEIP_REG_DEBUG_DESKEW_1_DEBUG_DESKEW_LANE_12_BB_SHIFT                                            0
+  #define PCIEIP_REG_DEBUG_DESKEW_1_DEBUG_DESKEW_LANE_13_BB                                                  (0xffff<<16) // 
+  #define PCIEIP_REG_DEBUG_DESKEW_1_DEBUG_DESKEW_LANE_13_BB_SHIFT                                            16
+#define PCIEIP_REG_DEBUG_DESKEW_2_BB                                                                         0x001d48UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DEBUG_DESKEW_2_DEBUG_DESKEW_LANE_10_BB                                                  (0xffff<<0) // 
+  #define PCIEIP_REG_DEBUG_DESKEW_2_DEBUG_DESKEW_LANE_10_BB_SHIFT                                            0
+  #define PCIEIP_REG_DEBUG_DESKEW_2_DEBUG_DESKEW_LANE_11_BB                                                  (0xffff<<16) // 
+  #define PCIEIP_REG_DEBUG_DESKEW_2_DEBUG_DESKEW_LANE_11_BB_SHIFT                                            16
+#define PCIEIP_REG_DEBUG_DESKEW_3_BB                                                                         0x001d4cUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DEBUG_DESKEW_3_DEBUG_DESKEW_LANE_8_BB                                                   (0xffff<<0) // 
+  #define PCIEIP_REG_DEBUG_DESKEW_3_DEBUG_DESKEW_LANE_8_BB_SHIFT                                             0
+  #define PCIEIP_REG_DEBUG_DESKEW_3_DEBUG_DESKEW_LANE_9_BB                                                   (0xffff<<16) // 
+  #define PCIEIP_REG_DEBUG_DESKEW_3_DEBUG_DESKEW_LANE_9_BB_SHIFT                                             16
+#define PCIEIP_REG_DEBUG_DESKEW_4_BB                                                                         0x001d50UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DEBUG_DESKEW_4_DEBUG_DESKEW_LANE_6_BB                                                   (0xffff<<0) // 
+  #define PCIEIP_REG_DEBUG_DESKEW_4_DEBUG_DESKEW_LANE_6_BB_SHIFT                                             0
+  #define PCIEIP_REG_DEBUG_DESKEW_4_DEBUG_DESKEW_LANE_7_BB                                                   (0xffff<<16) // 
+  #define PCIEIP_REG_DEBUG_DESKEW_4_DEBUG_DESKEW_LANE_7_BB_SHIFT                                             16
+#define PCIEIP_REG_DEBUG_DESKEW_5_BB                                                                         0x001d54UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DEBUG_DESKEW_5_DEBUG_DESKEW_LANE_4_BB                                                   (0xffff<<0) // 
+  #define PCIEIP_REG_DEBUG_DESKEW_5_DEBUG_DESKEW_LANE_4_BB_SHIFT                                             0
+  #define PCIEIP_REG_DEBUG_DESKEW_5_DEBUG_DESKEW_LANE_5_BB                                                   (0xffff<<16) // 
+  #define PCIEIP_REG_DEBUG_DESKEW_5_DEBUG_DESKEW_LANE_5_BB_SHIFT                                             16
+#define PCIEIP_REG_DEBUG_DESKEW_6_BB                                                                         0x001d58UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DEBUG_DESKEW_6_DEBUG_DESKEW_LANE_2_BB                                                   (0xffff<<0) // 
+  #define PCIEIP_REG_DEBUG_DESKEW_6_DEBUG_DESKEW_LANE_2_BB_SHIFT                                             0
+  #define PCIEIP_REG_DEBUG_DESKEW_6_DEBUG_DESKEW_LANE_3_BB                                                   (0xffff<<16) // 
+  #define PCIEIP_REG_DEBUG_DESKEW_6_DEBUG_DESKEW_LANE_3_BB_SHIFT                                             16
+#define PCIEIP_REG_DEBUG_DESKEW_7_BB                                                                         0x001d5cUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_DEBUG_DESKEW_7_DEBUG_DESKEW_LANE_0_BB                                                   (0xffff<<0) // 
+  #define PCIEIP_REG_DEBUG_DESKEW_7_DEBUG_DESKEW_LANE_0_BB_SHIFT                                             0
+  #define PCIEIP_REG_DEBUG_DESKEW_7_DEBUG_DESKEW_LANE_1_BB                                                   (0xffff<<16) // 
+  #define PCIEIP_REG_DEBUG_DESKEW_7_DEBUG_DESKEW_LANE_1_BB_SHIFT                                             16
+#define PCIEIP_REG_FREEZE_DESKEW_0_BB                                                                        0x001d60UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_FREEZE_DESKEW_0_FREEZE_DESKEW_LANE_14_BB                                                (0xffff<<0) // 
+  #define PCIEIP_REG_FREEZE_DESKEW_0_FREEZE_DESKEW_LANE_14_BB_SHIFT                                          0
+  #define PCIEIP_REG_FREEZE_DESKEW_0_FREEZE_DESKEW_LANE_15_BB                                                (0xffff<<16) // 
+  #define PCIEIP_REG_FREEZE_DESKEW_0_FREEZE_DESKEW_LANE_15_BB_SHIFT                                          16
+#define PCIEIP_REG_FREEZE_DESKEW_1_BB                                                                        0x001d64UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_FREEZE_DESKEW_1_FREEZE_DESKEW_LANE_12_BB                                                (0xffff<<0) // 
+  #define PCIEIP_REG_FREEZE_DESKEW_1_FREEZE_DESKEW_LANE_12_BB_SHIFT                                          0
+  #define PCIEIP_REG_FREEZE_DESKEW_1_FREEZE_DESKEW_LANE_13_BB                                                (0xffff<<16) // 
+  #define PCIEIP_REG_FREEZE_DESKEW_1_FREEZE_DESKEW_LANE_13_BB_SHIFT                                          16
+#define PCIEIP_REG_FREEZE_DESKEW_2_BB                                                                        0x001d68UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_FREEZE_DESKEW_2_FREEZE_DESKEW_LANE_10_BB                                                (0xffff<<0) // 
+  #define PCIEIP_REG_FREEZE_DESKEW_2_FREEZE_DESKEW_LANE_10_BB_SHIFT                                          0
+  #define PCIEIP_REG_FREEZE_DESKEW_2_FREEZE_DESKEW_LANE_11_BB                                                (0xffff<<16) // 
+  #define PCIEIP_REG_FREEZE_DESKEW_2_FREEZE_DESKEW_LANE_11_BB_SHIFT                                          16
+#define PCIEIP_REG_FREEZE_DESKEW_3_BB                                                                        0x001d6cUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_FREEZE_DESKEW_3_FREEZE_DESKEW_LANE_8_BB                                                 (0xffff<<0) // 
+  #define PCIEIP_REG_FREEZE_DESKEW_3_FREEZE_DESKEW_LANE_8_BB_SHIFT                                           0
+  #define PCIEIP_REG_FREEZE_DESKEW_3_FREEZE_DESKEW_LANE_9_BB                                                 (0xffff<<16) // 
+  #define PCIEIP_REG_FREEZE_DESKEW_3_FREEZE_DESKEW_LANE_9_BB_SHIFT                                           16
+#define PCIEIP_REG_FREEZE_DESKEW_4_BB                                                                        0x001d70UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_FREEZE_DESKEW_4_FREEZE_DESKEW_LANE_6_BB                                                 (0xffff<<0) // 
+  #define PCIEIP_REG_FREEZE_DESKEW_4_FREEZE_DESKEW_LANE_6_BB_SHIFT                                           0
+  #define PCIEIP_REG_FREEZE_DESKEW_4_FREEZE_DESKEW_LANE_7_BB                                                 (0xffff<<16) // 
+  #define PCIEIP_REG_FREEZE_DESKEW_4_FREEZE_DESKEW_LANE_7_BB_SHIFT                                           16
+#define PCIEIP_REG_FREEZE_DESKEW_5_BB                                                                        0x001d74UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_FREEZE_DESKEW_5_FREEZE_DESKEW_LANE_4_BB                                                 (0xffff<<0) // 
+  #define PCIEIP_REG_FREEZE_DESKEW_5_FREEZE_DESKEW_LANE_4_BB_SHIFT                                           0
+  #define PCIEIP_REG_FREEZE_DESKEW_5_FREEZE_DESKEW_LANE_5_BB                                                 (0xffff<<16) // 
+  #define PCIEIP_REG_FREEZE_DESKEW_5_FREEZE_DESKEW_LANE_5_BB_SHIFT                                           16
+#define PCIEIP_REG_FREEZE_DESKEW_6_BB                                                                        0x001d78UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_FREEZE_DESKEW_6_FREEZE_DESKEW_LANE_2_BB                                                 (0xffff<<0) // 
+  #define PCIEIP_REG_FREEZE_DESKEW_6_FREEZE_DESKEW_LANE_2_BB_SHIFT                                           0
+  #define PCIEIP_REG_FREEZE_DESKEW_6_FREEZE_DESKEW_LANE_3_BB                                                 (0xffff<<16) // 
+  #define PCIEIP_REG_FREEZE_DESKEW_6_FREEZE_DESKEW_LANE_3_BB_SHIFT                                           16
+#define PCIEIP_REG_FREEZE_DESKEW_7_BB                                                                        0x001d7cUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_FREEZE_DESKEW_7_FREEZE_DESKEW_LANE_0_BB                                                 (0xffff<<0) // 
+  #define PCIEIP_REG_FREEZE_DESKEW_7_FREEZE_DESKEW_LANE_0_BB_SHIFT                                           0
+  #define PCIEIP_REG_FREEZE_DESKEW_7_FREEZE_DESKEW_LANE_1_BB                                                 (0xffff<<16) // 
+  #define PCIEIP_REG_FREEZE_DESKEW_7_FREEZE_DESKEW_LANE_1_BB_SHIFT                                           16
+#define PCIEIP_REG_PHY_DBG_SED_RDDATA_BB                                                                     0x001d80UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PHY_DBG_SED_RDDATA_SED_READ_DATA_BB                                                     (0x7ffffff<<0) // SED Read Data. Reading this register returns the contents of SED FIFO at the current read address.
+  #define PCIEIP_REG_PHY_DBG_SED_RDDATA_SED_READ_DATA_BB_SHIFT                                               0
+#define PCIEIP_REG_PHY_DBG_SED_EXTCFG_30_BB                                                                  0x001d84UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_30_SED_EXT_CFG_0_BB                                                  (0xff<<0) // SED Extended Configuration 0.
+  #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_30_SED_EXT_CFG_0_BB_SHIFT                                            0
+  #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_30_SED_EXT_CFG_1_BB                                                  (0xff<<8) // SED Extended Configuration 1.
+  #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_30_SED_EXT_CFG_1_BB_SHIFT                                            8
+  #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_30_SED_EXT_CFG_2_BB                                                  (0xff<<16) // SED Extended Configuration 2.
+  #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_30_SED_EXT_CFG_2_BB_SHIFT                                            16
+  #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_30_SED_EXT_CFG_3_BB                                                  (0xff<<24) // SED Extended Configuration 3.
+  #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_30_SED_EXT_CFG_3_BB_SHIFT                                            24
+#define PCIEIP_REG_PHY_DBG_SED_EXTCFG_74_BB                                                                  0x001d88UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_74_SED_EXT_CFG_4_BB                                                  (0xff<<0) // SED Extended Configuration 4.
+  #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_74_SED_EXT_CFG_4_BB_SHIFT                                            0
+  #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_74_SED_EXT_CFG_5_BB                                                  (0xff<<8) // SED Extended Configuration 5.
+  #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_74_SED_EXT_CFG_5_BB_SHIFT                                            8
+  #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_74_SED_EXT_CFG_6_BB                                                  (0xff<<16) // SED Extended Configuration 6.
+  #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_74_SED_EXT_CFG_6_BB_SHIFT                                            16
+  #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_74_SED_EXT_CFG_7_BB                                                  (0xff<<24) // SED Extended Configuration 7.
+  #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_74_SED_EXT_CFG_7_BB_SHIFT                                            24
+#define PCIEIP_REG_PHY_DBG_PRESET_LUT_BB                                                                     0x001d90UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PHY_DBG_PRESET_LUT_PRESET_LUT_ENTRY_VAL_BB                                              (0x1ffff<<0) // Preset LUT Read Data.
+  #define PCIEIP_REG_PHY_DBG_PRESET_LUT_PRESET_LUT_ENTRY_VAL_BB_SHIFT                                        0
+#define PCIEIP_REG_PHY_DBG_MUXED_SIGS_BB                                                                     0x001e00UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PHY_DBG_MUXED_SIGS_PHY_DBG_SIGS_0_BB                                                    (0x7ff<<0) // Debug signals that are muxed to the debug port 0.
+  #define PCIEIP_REG_PHY_DBG_MUXED_SIGS_PHY_DBG_SIGS_0_BB_SHIFT                                              0
+  #define PCIEIP_REG_PHY_DBG_MUXED_SIGS_UNUSED_BB                                                            (0x1f<<11) // 
+  #define PCIEIP_REG_PHY_DBG_MUXED_SIGS_UNUSED_BB_SHIFT                                                      11
+  #define PCIEIP_REG_PHY_DBG_MUXED_SIGS_PHY_DBG_SIGS_1_BB                                                    (0x7ff<<16) // Debug signals that are muxed to the debug port 1.
+  #define PCIEIP_REG_PHY_DBG_MUXED_SIGS_PHY_DBG_SIGS_1_BB_SHIFT                                              16
+#define PCIEIP_REG_PHY_DBG_CLKREQ_0_BB                                                                       0x001e10UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_7_BB                                                       (0xf<<0) // The state of the clock PM state machine and perstb 7 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_7_BB_SHIFT                                                 0
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_6_BB                                                       (0xf<<4) // The state of the clock PM state machine and perstb 6 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_6_BB_SHIFT                                                 4
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_5_BB                                                       (0xf<<8) // The state of the clock PM state machine and perstb 5 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_5_BB_SHIFT                                                 8
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_4_BB                                                       (0xf<<12) // The state of the clock PM state machine and perstb 4 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_4_BB_SHIFT                                                 12
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_3_BB                                                       (0xf<<16) // The state of the clock PM state machine and perstb 3 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_3_BB_SHIFT                                                 16
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_2_BB                                                       (0xf<<20) // The state of the clock PM state machine and perstb 2 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_2_BB_SHIFT                                                 20
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_1_BB                                                       (0xf<<24) // The state of the clock PM state machine and perstb 1 transition in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_1_BB_SHIFT                                                 24
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_0_BB                                                       (0xf<<28) // The current state of the clock PM state machine and perstb. The encoding is:  b0000 : Unused entry b0001 : State waiting for activation b0010 : State waiting for Serdes to complete P0 to P2 change b0011 : State waiting for Tp0torefclk timer expiry b0100 : State waiting for Texcr timer expiry b0101 : State waiting for Tcrpw timer expiry b0110 : State waiting for reactivation b0111 : State waiting for Tcrlon timer expiry b1000 : State waiting for Trefup timer expiry b1001 : State waiting Serdes to complete PLL lock b1010 : State waiting for clock PM exit conditions to settle b1110 : Unknown state (failure) b1111 : Fundamental reset (perstb) occurred
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_0_BB_SHIFT                                                 28
+#define PCIEIP_REG_PHY_DBG_CLKREQ_1_BB                                                                       0x001e14UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_15_BB                                                      (0xf<<0) // The state of the clock PM state machine and perstb 15 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_15_BB_SHIFT                                                0
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_14_BB                                                      (0xf<<4) // The state of the clock PM state machine and perstb 14 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_14_BB_SHIFT                                                4
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_13_BB                                                      (0xf<<8) // The state of the clock PM state machine and perstb 13 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_13_BB_SHIFT                                                8
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_12_BB                                                      (0xf<<12) // The state of the clock PM state machine and perstb 12 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_12_BB_SHIFT                                                12
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_11_BB                                                      (0xf<<16) // The state of the clock PM state machine and perstb 11 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_11_BB_SHIFT                                                16
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_10_BB                                                      (0xf<<20) // The state of the clock PM state machine and perstb 10 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_10_BB_SHIFT                                                20
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_9_BB                                                       (0xf<<24) // The state of the clock PM state machine and perstb 9 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_9_BB_SHIFT                                                 24
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_8_BB                                                       (0xf<<28) // The state of the clock PM state machine and perstb 8 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_8_BB_SHIFT                                                 28
+#define PCIEIP_REG_PHY_DBG_CLKREQ_2_BB                                                                       0x001e18UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_23_BB                                                      (0xf<<0) // The state of the clock PM state machine and perstb 23 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_23_BB_SHIFT                                                0
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_22_BB                                                      (0xf<<4) // The state of the clock PM state machine and perstb 22 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_22_BB_SHIFT                                                4
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_21_BB                                                      (0xf<<8) // The state of the clock PM state machine and perstb 21 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_21_BB_SHIFT                                                8
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_20_BB                                                      (0xf<<12) // The state of the clock PM state machine and perstb 20 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_20_BB_SHIFT                                                12
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_19_BB                                                      (0xf<<16) // The state of the clock PM state machine and perstb 19 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_19_BB_SHIFT                                                16
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_18_BB                                                      (0xf<<20) // The state of the clock PM state machine and perstb 18 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_18_BB_SHIFT                                                20
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_17_BB                                                      (0xf<<24) // The state of the clock PM state machine and perstb 17 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_17_BB_SHIFT                                                24
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_16_BB                                                      (0xf<<28) // The state of the clock PM state machine and perstb 16 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_16_BB_SHIFT                                                28
+#define PCIEIP_REG_PHY_DBG_CLKREQ_3_BB                                                                       0x001e1cUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_31_BB                                                      (0xf<<0) // The state of the clock PM state machine and perstb 31 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_31_BB_SHIFT                                                0
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_30_BB                                                      (0xf<<4) // The state of the clock PM state machine and perstb 30 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_30_BB_SHIFT                                                4
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_29_BB                                                      (0xf<<8) // The state of the clock PM state machine and perstb 29 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_29_BB_SHIFT                                                8
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_28_BB                                                      (0xf<<12) // The state of the clock PM state machine and perstb 28 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_28_BB_SHIFT                                                12
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_27_BB                                                      (0xf<<16) // The state of the clock PM state machine and perstb 27 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_27_BB_SHIFT                                                16
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_26_BB                                                      (0xf<<20) // The state of the clock PM state machine and perstb 26 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_26_BB_SHIFT                                                20
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_25_BB                                                      (0xf<<24) // The state of the clock PM state machine and perstb 25 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_25_BB_SHIFT                                                24
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_24_BB                                                      (0xf<<28) // The state of the clock PM state machine and perstb 24 transitions in the past. See encoding above.
+  #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_24_BB_SHIFT                                                28
+#define PCIEIP_REG_MISC_DBG_STATUS_BB                                                                        0x001e20UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIEIP_REG_MISC_DBG_STATUS_USER_ALLOW_GEN3_SYNC_BB                                                 (0x1<<0) // Instantaneous value of the top-level user_allow_gen3 signal (sync'd to the cfg_clk domain). The reset value will depend on the environment.
+  #define PCIEIP_REG_MISC_DBG_STATUS_USER_ALLOW_GEN3_SYNC_BB_SHIFT                                           0
+  #define PCIEIP_REG_MISC_DBG_STATUS_UNUSED_BB                                                               (0x7fffffff<<1) // 
+  #define PCIEIP_REG_MISC_DBG_STATUS_UNUSED_BB_SHIFT                                                         1
+#define PCIEIP_VF_REG_VF_DEVICE_ID_VENDOR_ID_REG_K2_E5                                                       0x000000UL //Access:R    DataWidth:0x20   // Device ID and Vendor ID Register.
+  #define PCIEIP_VF_REG_VF_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_K2_E5                                 (0xffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier.
+  #define PCIEIP_VF_REG_VF_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_K2_E5_SHIFT                           0
+  #define PCIEIP_VF_REG_VF_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_K2_E5                                 (0xffff<<16) // Device ID. Vendor Assigned Device Identifier.
+  #define PCIEIP_VF_REG_VF_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_K2_E5_SHIFT                           16
+#define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_K2_E5                                                            0x000004UL //Access:RW   DataWidth:0x20   // Command and Status Register.
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_K2_E5                                          (0x1<<0) // Enables IO Access Response.   You cannot write to this register if your configuration has no IO bars; that is, the internal signal has_io_bar=0.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_K2_E5_SHIFT                                    0
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_K2_E5                                   (0x1<<1) // Enables Memory Access Response.   You cannot write to this register if your configuration has no MEM bars; that is, the internal signal has_mem_bar=0.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_K2_E5_SHIFT                             1
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_K2_E5                                  (0x1<<2) // Bus Master Enable. Controls Issuing of Memory and I/O Requests.
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_K2_E5_SHIFT                            2
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_K2_E5                        (0x1<<3) // Special Cycle Enable.
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_K2_E5_SHIFT                  3
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_K2_E5                                      (0x1<<4) // Memory Write and Invalidate.
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_K2_E5_SHIFT                                4
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_K2_E5                               (0x1<<5) // VGA Palette Snoop.
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_K2_E5_SHIFT                         5
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_K2_E5                                  (0x1<<6) // Controls Logging of Poisoned TLPs.
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_K2_E5_SHIFT                            6
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_K2_E5                                  (0x1<<7) // IDSEL Stepping.
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_K2_E5_SHIFT                            7
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_K2_E5                                         (0x1<<8) // Enables Error Reporting.
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_K2_E5_SHIFT                                   8
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_K2_E5                                         (0x1<<10) // Controls generation of interrupts by a function.
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_K2_E5_SHIFT                                   10
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_RESERV_K2_E5                                          (0x1f<<11) // Reserved.
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_RESERV_K2_E5_SHIFT                                    11
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_INT_STATUS_K2_E5                                               (0x1<<19) // Emulation interrupt pending.
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_INT_STATUS_K2_E5_SHIFT                                         19
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_CAP_LIST_K2_E5                                                 (0x1<<20) // Extended Capability.
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_CAP_LIST_K2_E5_SHIFT                                           20
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_FAST_66MHZ_CAP_K2_E5                                           (0x1<<21) // PCI 66MHz Capability.
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_FAST_66MHZ_CAP_K2_E5_SHIFT                                     21
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_FAST_B2B_CAP_K2_E5                                             (0x1<<23) // Fast Back to Back Transaction Capable and Enable.
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_FAST_B2B_CAP_K2_E5_SHIFT                                       23
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_MASTER_DPE_K2_E5                                               (0x1<<24) // Controls poisoned Completion and Request error reporting.
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_MASTER_DPE_K2_E5_SHIFT                                         24
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_DEV_SEL_TIMING_K2_E5                                           (0x3<<25) // Device Select Timing.
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_DEV_SEL_TIMING_K2_E5_SHIFT                                     25
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_K2_E5                                    (0x1<<27) // Completer Abort Error.
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_K2_E5_SHIFT                              27
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_K2_E5                                        (0x1<<28) // Completer Abort received.
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_K2_E5_SHIFT                                  28
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_K2_E5                                        (0x1<<29) // Unsupported request completion status received.
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_K2_E5_SHIFT                                  29
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_K2_E5                                         (0x1<<30) // Fatal or Non-Fatal Error Message sent by function.
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_K2_E5_SHIFT                                   30
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_K2_E5                                      (0x1<<31) // Poisoned TLP received by function.
+  #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_K2_E5_SHIFT                                31
+#define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_K2_E5                                                        0x000008UL //Access:R    DataWidth:0x20   // Class Code and Revision ID Register.
+  #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_REVISION_ID_K2_E5                                          (0xff<<0) // Vendor chosen Revision ID.   Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_REVISION_ID_K2_E5_SHIFT                                    0
+  #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_K2_E5                                    (0xff<<8) // Class Code Programming Interface.   Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_K2_E5_SHIFT                              8
+  #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_K2_E5                                        (0xff<<16) // Subclass Code to represent Device Type.   Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_K2_E5_SHIFT                                  16
+  #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_K2_E5                                      (0xff<<24) // Base Class Code to represent Device Type.   Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_K2_E5_SHIFT                                24
+#define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_K2_E5                                  0x00000cUL //Access:R    DataWidth:0x20   // BIST, Header Type, Cache Line Size, and Latency Timer Registers.
+  #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_K2_E5                (0xff<<0) // Cache Line Size. Has no effect on PCIe device behavior.
+  #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_K2_E5_SHIFT          0
+  #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_K2_E5           (0xff<<8) // Does not apply to PCI Express.
+  #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_K2_E5_SHIFT     8
+  #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_K2_E5                    (0x7f<<16) // Specifies Header Type.
+  #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_K2_E5_SHIFT              16
+  #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_K2_E5                     (0x1<<23) // Specifies whether device is multifunction.   Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_K2_E5_SHIFT               23
+  #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_K2_E5                           (0xff<<24) // Optional for BIST support.
+  #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_K2_E5_SHIFT                     24
+#define PCIEIP_VF_REG_VF_BAR0_REG_K2_E5                                                                      0x000010UL //Access:R    DataWidth:0x20   // BAR0 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_MEM_IO_K2_E5                                                        (0x1<<0) // BAR0 Memory Space Indicator.
+  #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_MEM_IO_K2_E5_SHIFT                                                  0
+  #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_TYPE_K2_E5                                                          (0x3<<1) // BAR0 32-bit or 64-bit.
+  #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_TYPE_K2_E5_SHIFT                                                    1
+  #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_PREFETCH_K2_E5                                                      (0x1<<3) // BAR0 Prefetchable.
+  #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_PREFETCH_K2_E5_SHIFT                                                3
+  #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_START_K2_E5                                                         (0xfffffff<<4) // BAR0 Base Address.
+  #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_START_K2_E5_SHIFT                                                   4
+#define PCIEIP_VF_REG_VF_BAR1_REG_K2_E5                                                                      0x000014UL //Access:R    DataWidth:0x20   // BAR1 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_MEM_IO_K2_E5                                                        (0x1<<0) // BAR1 Memory Space Indicator.
+  #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_MEM_IO_K2_E5_SHIFT                                                  0
+  #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_TYPE_K2_E5                                                          (0x3<<1) // BAR1 32-bit or 64-bit.
+  #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_TYPE_K2_E5_SHIFT                                                    1
+  #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_PREFETCH_K2_E5                                                      (0x1<<3) // BAR1 Prefetchable.
+  #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_PREFETCH_K2_E5_SHIFT                                                3
+  #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_START_K2_E5                                                         (0xfffffff<<4) // BAR1 Base Address.
+  #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_START_K2_E5_SHIFT                                                   4
+#define PCIEIP_VF_REG_VF_BAR2_REG_K2_E5                                                                      0x000018UL //Access:R    DataWidth:0x20   // BAR2 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_MEM_IO_K2_E5                                                        (0x1<<0) // BAR2 Memory Space Indicator.
+  #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_MEM_IO_K2_E5_SHIFT                                                  0
+  #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_TYPE_K2_E5                                                          (0x3<<1) // BAR2 32-bit or 64-bit.
+  #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_TYPE_K2_E5_SHIFT                                                    1
+  #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_PREFETCH_K2_E5                                                      (0x1<<3) // BAR2 Prefetchable.
+  #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_PREFETCH_K2_E5_SHIFT                                                3
+  #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_START_K2_E5                                                         (0xfffffff<<4) // BAR2 Base Address.
+  #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_START_K2_E5_SHIFT                                                   4
+#define PCIEIP_VF_REG_VF_BAR3_REG_K2_E5                                                                      0x00001cUL //Access:R    DataWidth:0x20   // BAR3 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_MEM_IO_K2_E5                                                        (0x1<<0) // BAR3 Memory Space Indicator.
+  #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_MEM_IO_K2_E5_SHIFT                                                  0
+  #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_TYPE_K2_E5                                                          (0x3<<1) // BAR3 32-bit or 64-bit.
+  #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_TYPE_K2_E5_SHIFT                                                    1
+  #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_PREFETCH_K2_E5                                                      (0x1<<3) // BAR3 Prefetchable.
+  #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_PREFETCH_K2_E5_SHIFT                                                3
+  #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_START_K2_E5                                                         (0xfffffff<<4) // BAR3 Base Address.
+  #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_START_K2_E5_SHIFT                                                   4
+#define PCIEIP_VF_REG_VF_BAR4_REG_K2_E5                                                                      0x000020UL //Access:R    DataWidth:0x20   // BAR4 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_MEM_IO_K2_E5                                                        (0x1<<0) // BAR4 Memory Space Indicator.
+  #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_MEM_IO_K2_E5_SHIFT                                                  0
+  #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_TYPE_K2_E5                                                          (0x3<<1) // BAR4 32-bit or 64-bit.
+  #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_TYPE_K2_E5_SHIFT                                                    1
+  #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_PREFETCH_K2_E5                                                      (0x1<<3) // BAR4 Prefetchable.
+  #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_PREFETCH_K2_E5_SHIFT                                                3
+  #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_START_K2_E5                                                         (0xfffffff<<4) // BAR4 Base Address.
+  #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_START_K2_E5_SHIFT                                                   4
+#define PCIEIP_VF_REG_VF_BAR5_REG_K2_E5                                                                      0x000024UL //Access:R    DataWidth:0x20   // BAR5 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_MEM_IO_K2_E5                                                        (0x1<<0) // BAR5 Memory Space Indicator.
+  #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_MEM_IO_K2_E5_SHIFT                                                  0
+  #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_TYPE_K2_E5                                                          (0x3<<1) // BAR5 32-bit or 64-bit.
+  #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_TYPE_K2_E5_SHIFT                                                    1
+  #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_PREFETCH_K2_E5                                                      (0x1<<3) // BAR5 Prefetchable.
+  #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_PREFETCH_K2_E5_SHIFT                                                3
+  #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_START_K2_E5                                                         (0xfffffff<<4) // BAR5 Base Address.
+  #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_START_K2_E5_SHIFT                                                   4
+#define PCIEIP_VF_REG_VF_CARDBUS_CIS_PTR_REG_K2_E5                                                           0x000028UL //Access:R    DataWidth:0x20   // CardBus CIS Pointer Register.
+#define PCIEIP_VF_REG_VF_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_K2_E5                                          0x00002cUL //Access:RW   DataWidth:0x20   // Subsystem ID and Subsystem Vendor ID Register.
+  #define PCIEIP_VF_REG_VF_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_K2_E5                       (0xffff<<0) // Subsystem Vendor ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_K2_E5_SHIFT                 0
+  #define PCIEIP_VF_REG_VF_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_K2_E5                          (0xffff<<16) // Subsystem Device ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_K2_E5_SHIFT                    16
+#define PCIEIP_VF_REG_VF_PCI_CAP_PTR_REG_K2_E5                                                               0x000034UL //Access:R    DataWidth:0x20   // Capability Pointer Register.
+  #define PCIEIP_VF_REG_VF_PCI_CAP_PTR_REG_CAP_POINTER_K2_E5                                                 (0xff<<0) // Pointer to first item in the PCI Capability Structure.   Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_PCI_CAP_PTR_REG_CAP_POINTER_K2_E5_SHIFT                                           0
+#define PCIEIP_VF_REG_VF_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_K2_E5                        0x00003cUL //Access:R    DataWidth:0x20   // Interrupt Line and Pin Register.
+  #define PCIEIP_VF_REG_VF_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_K2_E5             (0xff<<0) // PCI Compatible Interrupt Line Routing Register Field.
+  #define PCIEIP_VF_REG_VF_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_K2_E5_SHIFT       0
+  #define PCIEIP_VF_REG_VF_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_K2_E5              (0xff<<8) // PCI Compatible Interrupt Pin Register Field.
+  #define PCIEIP_VF_REG_VF_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_K2_E5_SHIFT        8
+#define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_K2_E5                                    0x000070UL //Access:RW   DataWidth:0x20   // PCI Express Capabilities, ID, Next Pointer Register.
+  #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_K2_E5                      (0xff<<0) // PCIE Capability ID.
+  #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_K2_E5_SHIFT                0
+  #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_K2_E5                (0xff<<8) // PCIE Next Capability Pointer.
+  #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_K2_E5_SHIFT          8
+  #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_K2_E5                     (0xf<<16) // PCIE Capability Version Number.
+  #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_K2_E5_SHIFT               16
+  #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_K2_E5               (0xf<<20) // PCIE Device/PortType.
+  #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_K2_E5_SHIFT         20
+  #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_K2_E5                    (0x1<<24) // PCIe Slot Implemented Valid.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_K2_E5_SHIFT              24
+  #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_K2_E5                 (0x1f<<25) // PCIE Interrupt Message Number.
+  #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_K2_E5_SHIFT           25
+  #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_K2_E5                             (0x1<<30) // Reserved.
+  #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_K2_E5_SHIFT                       30
+#define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_K2_E5                                                       0x000074UL //Access:RW   DataWidth:0x20   // Device Capabilities Register.
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_K2_E5                           (0x7<<0) // Max Payload Size Supported.
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_K2_E5_SHIFT                     0
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_K2_E5                       (0x3<<3) // Phantom Functions Supported.
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_K2_E5_SHIFT                 3
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_K2_E5                               (0x1<<5) // Extended Tag Field Supported.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_K2_E5_SHIFT                         5
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_K2_E5                       (0x7<<6) // Applies to endpoints only L0s acceptable latency.
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_K2_E5_SHIFT                 6
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_K2_E5                        (0x7<<9) // Applies to endpoints only L1 acceptable latency.
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_K2_E5_SHIFT                  9
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_K2_E5                      (0x1<<15) // Role-based Error Reporting Implemented.
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_K2_E5_SHIFT                15
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_K2_E5                     (0xff<<18) // Captured Slot Power Limit Value.
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_K2_E5_SHIFT               18
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_K2_E5                     (0x3<<26) // Captured Slot Power Limit Scale.
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_K2_E5_SHIFT               26
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_K2_E5                                    (0x1<<28) // Function Level Reset Capability (endpoints only).
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_K2_E5_SHIFT                              28
+#define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_K2_E5                                                  0x000078UL //Access:RW   DataWidth:0x20   // Device Control and Status Register.
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_K2_E5                    (0x1<<0) // Correctable Error Reporting Enable.
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_K2_E5_SHIFT              0
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2_E5               (0x1<<1) // Non-fatal Error Reporting Enable.
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2_E5_SHIFT         1
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_K2_E5                   (0x1<<2) // Fatal Error Reporting Enable.
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_K2_E5_SHIFT             2
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_K2_E5                  (0x1<<3) // Unsupported Request Reporting Enable.
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_K2_E5_SHIFT            3
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_K2_E5                          (0x1<<4) // Enable Relaxed Ordering.
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_K2_E5_SHIFT                    4
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_K2_E5                   (0x7<<5) // Max Payload Size. Max_Payload_Size . This field sets maximum TLP payload size for the Function. Permissible values that can be programmed are indicated by the Max_Payload_Size Supported field (PCIE_CAP_MAX_PAYLOAD_SIZE) in the Device Capabilities register (DEVICE_CAPABILITIES_REG).
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_K2_E5_SHIFT             5
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_K2_E5                            (0x1<<8) // Extended Tag Field Enable.   The write value is gated with the PCIE_CAP_EXT_TAG_SUPP field of DEVICE_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_EXT_TAG_SUPP ? RW : RO
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_K2_E5_SHIFT                      8
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_K2_E5                       (0x1<<9) // Phantom Functions Enable.   The write value is gated with the PCIE_CAP_PHANTOM_FUNC_SUPPORT field of DEVICE_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_PHANTOM_FUNC_SUPPORT ? RW : RO
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_K2_E5_SHIFT                 9
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_K2_E5                       (0x1<<10) // Aux Power PM Enable.   This bit is derived by sampling the sys_aux_pwr_det input.
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_K2_E5_SHIFT                 10
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_K2_E5                           (0x1<<11) // Enable No Snoop.   Note: The access attributes of this field are as follows:  - Dbi: R
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_K2_E5_SHIFT                     11
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_K2_E5                     (0x7<<12) // Max Read Request Size.
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_K2_E5_SHIFT               12
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_K2_E5                          (0x1<<15) // Initiate Function Level Reset (for endpoints).
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_K2_E5_SHIFT                    15
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_K2_E5                     (0x1<<16) // Correctable Error Detected Status.
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_K2_E5_SHIFT               16
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2_E5                (0x1<<17) // Non-Fatal Error Detected Status.
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2_E5_SHIFT          17
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_K2_E5                    (0x1<<18) // Fatal Error Detected Status.
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_K2_E5_SHIFT              18
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_K2_E5              (0x1<<19) // Unsupported Request Detected Status.
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_K2_E5_SHIFT        19
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_K2_E5                    (0x1<<20) // Aux Power Detected Status.   This bit is derived by sampling the sys_aux_pwr_det input.
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_K2_E5_SHIFT              20
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_K2_E5                         (0x1<<21) // Transactions Pending Status.
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_K2_E5_SHIFT                   21
+#define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_K2_E5                                                         0x00007cUL //Access:RW   DataWidth:0x20   // Link Capabilities Register.
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_K2_E5                               (0xf<<0) // Maximum Link Speed.   In M-PCIe mode, the reset and dynamic values of this field are calculated by the core.
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_K2_E5_SHIFT                         0
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_K2_E5                               (0x3f<<4) // Maximum Link Width.   In M-PCIe mode, the reset and dynamic values of this field are calculated by the core.
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_K2_E5_SHIFT                         4
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_K2_E5                 (0x3<<10) // Level of ASPM (Active State Power Management) Support.
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_K2_E5_SHIFT           10
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_K2_E5                             (0x7<<12) // LOs Exit Latency.  There are two each of these register fields, this one and a shadow one at the same address. The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the core and which one is accessed by a read request. Common Clock operation is supported (possible) in the core when one or more of the following expressions is true:  - CX_NFTS !=CX_COMM_NFTS  - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY  - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY Common Clock operation is enabled in the core when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location.
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_K2_E5_SHIFT                       12
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_K2_E5                              (0x7<<15) // L1 Exit Latency.  There are two each of these register fields, this one and a shadow one at the same address. The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the core and which one is accessed by a read request. Common Clock operation is supported (possible) in the core when one or more of the following expressions is true:  - CX_NFTS !=CX_COMM_NFTS  - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY  - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY Common Clock operation is enabled in the core when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location.
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_K2_E5_SHIFT                        15
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_K2_E5                              (0x1<<18) // Clock Power Management.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_K2_E5_SHIFT                        18
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_K2_E5                    (0x1<<19) // Surprise Down Error Reporting Capable.
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_K2_E5_SHIFT              19
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_K2_E5                           (0x1<<20) // Data Link Layer Link Active Reporting Capable.
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_K2_E5_SHIFT                     20
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_K2_E5                              (0x1<<21) // Link Bandwidth Notification Capable.
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_K2_E5_SHIFT                        21
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_K2_E5                          (0x1<<22) // ASPM Optionality Compliance.   Note: The access attributes of this field are as follows:  - Dbi: R
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_K2_E5_SHIFT                    22
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_K2_E5                                     (0xff<<24) // Port Number.
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_K2_E5_SHIFT                               24
+#define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_K2_E5                                                  0x000080UL //Access:RW   DataWidth:0x20   // Link Control and Status Register.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_K2_E5          (0x3<<0) // Active State Power Management (ASPM) Control.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_K2_E5_SHIFT    0
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_K2_E5                                   (0x1<<3) // Read Completion Boundary (RCB).
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_K2_E5_SHIFT                             3
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_K2_E5                          (0x1<<4) // Initiate Link Disable.   In a DSP that supports crosslink, the core gates the write value with the CROSS_LINK_EN field in PORT_LINK_CTRL_OFF.  Note: The access attributes of this field are as follows:  - Dbi: CX_CROSSLINK_ENABLE=1 && PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_CROSSLINK_ENABLE=0 && dsp=1? RW : RO
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_K2_E5_SHIFT                    4
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_K2_E5                          (0x1<<5) // Initiate Link Retrain.   Note: The access attributes of this field are as follows:  - Dbi: see description
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_K2_E5_SHIFT                    5
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_K2_E5                     (0x1<<6) // Common Clock Configuration.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_K2_E5_SHIFT               6
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_K2_E5                        (0x1<<7) // Extended Synch.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_K2_E5_SHIFT                  7
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_K2_E5                      (0x1<<8) // Enable Clock Power Management.   The write value is gated with the PCIE_CAP_CLOCK_POWER_MAN field in LINK_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_CLOCK_POWER_MAN ? RW : RO
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_K2_E5_SHIFT                8
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_K2_E5                 (0x1<<9) // Hardware Autonomous Width Disable.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_K2_E5_SHIFT           9
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_K2_E5                    (0x1<<10) // Link Bandwidth Management Interrupt Enable.   The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_K2_E5_SHIFT              10
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_K2_E5                   (0x1<<11) // Link Autonomous Bandwidth Management Interrupt Enable.   The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_K2_E5_SHIFT             11
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_K2_E5                 (0x3<<14) // DRS Signaling Control.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_K2_E5_SHIFT           14
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_K2_E5                            (0xf<<16) // Current Link Speed.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_K2_E5_SHIFT                      16
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_K2_E5                       (0x3f<<20) // Negotiated Link Width.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_K2_E5_SHIFT                 20
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_K2_E5                         (0x1<<27) // LTSSM is in Configuration or Recovery State.   Note: The access attributes of this field are as follows:  - Dbi: R
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_K2_E5_SHIFT                   27
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_K2_E5                       (0x1<<28) // Slot Clock Configuration.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_K2_E5_SHIFT                 28
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_K2_E5                            (0x1<<29) // Data Link Layer Active.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_K2_E5_SHIFT                      29
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_K2_E5                    (0x1<<30) // Link Bandwidth Management Status.   The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW1C : RO
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_K2_E5_SHIFT              30
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_K2_E5                   (0x1<<31) // Link Autonomous Bandwidth Status.   The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW1C : RO
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_K2_E5_SHIFT             31
+#define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_K2_E5                                                      0x000094UL //Access:R    DataWidth:0x20   // Device Capabilities 2 Register.
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_K2_E5                         (0xf<<0) // Completion Timeout Ranges Supported.
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_K2_E5_SHIFT                   0
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_K2_E5               (0x1<<4) // Completion Timeout Disable Supported.
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_K2_E5_SHIFT         4
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_K2_E5                       (0x1<<5) // ARI Forwarding Supported.
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_K2_E5_SHIFT                 5
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_K2_E5                       (0x1<<6) // Atomic Operation Routing Supported.
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_K2_E5_SHIFT                 6
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_K2_E5                        (0x1<<7) // 32 Bit AtomicOp Completer Supported.
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_K2_E5_SHIFT                  7
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_K2_E5                        (0x1<<8) // 64 Bit AtomicOp Completer Supported.
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_K2_E5_SHIFT                  8
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_K2_E5                          (0x1<<9) // 128 Bit CAS Completer Supported.
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_K2_E5_SHIFT                    9
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_K2_E5                        (0x1<<10) // No Relaxed Ordering Enabled PR-PR Passing.
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_K2_E5_SHIFT                  10
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_K2_E5                                  (0x1<<11) // LTR Mechanism Supported.
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_K2_E5_SHIFT                            11
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_K2_E5                       (0x1<<12) // TPH Completer Supported Bit 0.
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_K2_E5_SHIFT                 12
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_K2_E5                       (0x1<<13) // TPH Completer Supported Bit 1.
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_K2_E5_SHIFT                 13
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT_K2_E5                              (0x3<<18) // (OBFF) Optimized Buffer Flush/fill Supported.
+  #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT_K2_E5_SHIFT                        18
+#define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_K2_E5                                            0x000098UL //Access:R    DataWidth:0x20   // Device Control 2 and Status 2 Register.
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_K2_E5               (0xf<<0) // Completion Timeout Value.
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_K2_E5_SHIFT         0
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_K2_E5             (0x1<<4) // Completion Timeout Disable.
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_K2_E5_SHIFT       4
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_K2_E5          (0x1<<5) // ARI Forwarding Enable.
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_K2_E5_SHIFT    5
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_REQ_EN_K2_E5                   (0x1<<6) // AtomicOp Requester Enable.
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_REQ_EN_K2_E5_SHIFT             6
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_EGRESS_BLK_K2_E5               (0x1<<7) // AtomicOp Egress Blocking.
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_EGRESS_BLK_K2_E5_SHIFT         7
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_REQ_EN_K2_E5                      (0x1<<8) // IDO Request Enable.
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_REQ_EN_K2_E5_SHIFT                8
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_CPL_EN_K2_E5                      (0x1<<9) // IDO Completion Enable.
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_CPL_EN_K2_E5_SHIFT                9
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_K2_E5                          (0x1<<10) // LTR Mechanism Enable.   The write value is gated with the PCIE_CAP_LTR_SUPP field of DEVICE_CAPABILITIES2_REG.  Note: RW for function #0 and RsdvP for all other functions
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_K2_E5_SHIFT                    10
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_OBFF_EN_K2_E5                         (0x3<<13) // OBFF Enable.   Note: RW for function #0 and RsdvP for all other functions
+  #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_OBFF_EN_K2_E5_SHIFT                   13
+#define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_K2_E5                                                        0x00009cUL //Access:RW   DataWidth:0x20   // Link Capabilities 2 Register.
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_K2_E5                   (0x7f<<1) // Supported Link Speeds Vector.   This field has a default of (PCIE_CAP_MAX_LINK_SPEED == 0100) ? 0001111 : (PCIE_CAP_MAX_LINK_SPEED == 0011) ? 0000111 : (PCIE_CAP_MAX_LINK_SPEED == 0010) ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in the LINK_CAPABILITIES_REG register.
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_K2_E5_SHIFT             1
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_K2_E5                          (0x1<<8) // Cross Link Supported.
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_K2_E5_SHIFT                    8
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_K2_E5                                        (0x1<<31) // DRS Supported.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
+  #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_K2_E5_SHIFT                                  31
+#define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_K2_E5                                                0x0000a0UL //Access:RW   DataWidth:0x20   // Link Control 2 and Status 2 Register.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_K2_E5                   (0xf<<0) // Target Link Speed.    In M-PCIe mode, the contents of this field are derived from other registers.  Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_K2_E5_SHIFT             0
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_K2_E5                    (0x1<<4) // Enter Compliance Mode.   Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_K2_E5_SHIFT              4
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_K2_E5               (0x1<<5) // Hardware Autonomous Speed Disable.   Note: The access attributes of this field are as follows:  - Dbi: R (sticky)  Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_K2_E5_SHIFT         5
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_K2_E5                      (0x1<<6) // Controls Selectable De-emphasis for 5 GT/s.   Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_K2_E5_SHIFT                6
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_K2_E5                           (0x7<<7) // Controls Transmit Margin for Debug or Compliance.   Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_K2_E5_SHIFT                     7
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_K2_E5           (0x1<<10) // Enter Modified Compliance.   Note: The access attributes of this field are as follows:  - Dbi: R (sticky)  Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_K2_E5_SHIFT     10
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_K2_E5                      (0x1<<11) // Sets Compliance Skip Ordered Sets transmission.   Note: The access attributes of this field are as follows:  - Dbi: R (sticky)  Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_K2_E5_SHIFT                11
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_K2_E5                   (0xf<<12) // Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s.   Note: The access attributes of this field are as follows:  - Dbi: R (sticky)  Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_K2_E5_SHIFT             12
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_K2_E5                     (0x1<<16) // Current De-emphasis Level.    In M-PCIe mode this register is always 0x0. In C-PCIe mode, its contents are derived by sampling the PIPE
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_K2_E5_SHIFT               16
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_K2_E5                              (0x1<<17) // Equalization 8.0GT/s Complete.   Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_K2_E5_SHIFT                        17
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_K2_E5                           (0x1<<18) // Equalization 8.0GT/s Phase 1 Successful.   Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_K2_E5_SHIFT                     18
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_K2_E5                           (0x1<<19) // Equalization 8.0GT/s Phase 2 Successful.   Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_K2_E5_SHIFT                     19
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_K2_E5                           (0x1<<20) // Equalization 8.0GT/s Phase 3 Successful.   Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_K2_E5_SHIFT                     20
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_K2_E5                         (0x1<<21) // Link Equalization Request 8.0GT/s.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_K2_E5_SHIFT                   21
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_K2_E5                    (0x7<<28) // Downstream Component Presence. For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_K2_E5_SHIFT              28
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_K2_E5                         (0x1<<31) // DRS Message Received. For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.
+  #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_K2_E5_SHIFT                   31
+#define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_K2_E5                                                 0x0000b0UL //Access:RW   DataWidth:0x20   // MSI-X Capability ID, Next Pointer, Control Registers.
+  #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_K2_E5                               (0xff<<0) // MSI-X Capability ID.
+  #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_K2_E5_SHIFT                         0
+  #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_K2_E5                      (0xff<<8) // MSI-X Next Capability Pointer.
+  #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_K2_E5_SHIFT                8
+  #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_K2_E5                           (0x7ff<<16) // MSI-X Table Size.   SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PCI_MSIX_TABLE_SIZE field in VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG). To write this common value, you must perform a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_TABLE_SIZE field in the PF PCI_MSIX_CAP_ID_NEXT_CTRL_REG register.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R   - Dbi2: R
+  #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_K2_E5_SHIFT                     16
+  #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_K2_E5                        (0x1<<30) // Function Mask.   Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_K2_E5_SHIFT                  30
+  #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_K2_E5                               (0x1<<31) // MSI-X Enable.   Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_K2_E5_SHIFT                         31
+#define PCIEIP_VF_REG_VF_MSIX_TABLE_OFFSET_REG_K2_E5                                                         0x0000b4UL //Access:R    DataWidth:0x20   // MSI-X Table Offset and BIR Register.
+  #define PCIEIP_VF_REG_VF_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_K2_E5                                          (0x7<<0) // MSI-X Table Bar Indicator Register Field.
+  #define PCIEIP_VF_REG_VF_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_K2_E5_SHIFT                                    0
+  #define PCIEIP_VF_REG_VF_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_K2_E5                                 (0x1fffffff<<3) // MSI-X Table Offset.
+  #define PCIEIP_VF_REG_VF_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_K2_E5_SHIFT                           3
+#define PCIEIP_VF_REG_VF_MSIX_PBA_OFFSET_REG_K2_E5                                                           0x0000b8UL //Access:R    DataWidth:0x20   // MSI-X PBA Offset and BIR Register.
+  #define PCIEIP_VF_REG_VF_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_K2_E5                                            (0x7<<0) // MSI-X PBA BIR.
+  #define PCIEIP_VF_REG_VF_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_K2_E5_SHIFT                                      0
+  #define PCIEIP_VF_REG_VF_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_K2_E5                                     (0x1fffffff<<3) // MSI-X PBA Offset.
+  #define PCIEIP_VF_REG_VF_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_K2_E5_SHIFT                               3
+#define PCIEIP_VF_REG_VF_ARI_BASE_K2_E5                                                                      0x000100UL //Access:RW   DataWidth:0x20   // ARI Capability Header.
+  #define PCIEIP_VF_REG_VF_ARI_BASE_ARI_PCIE_EXTENDED_CAP_ID_K2_E5                                           (0xffff<<0) // ARI Extended Capability ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_ARI_BASE_ARI_PCIE_EXTENDED_CAP_ID_K2_E5_SHIFT                                     0
+  #define PCIEIP_VF_REG_VF_ARI_BASE_ARI_CAP_VERSION_K2_E5                                                    (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_ARI_BASE_ARI_CAP_VERSION_K2_E5_SHIFT                                              16
+  #define PCIEIP_VF_REG_VF_ARI_BASE_ARI_NEXT_OFFSET_K2_E5                                                    (0xfff<<20) // Next Capability Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_ARI_BASE_ARI_NEXT_OFFSET_K2_E5_SHIFT                                              20
+#define PCIEIP_VF_REG_VF_CAP_REG_K2_E5                                                                       0x000104UL //Access:R    DataWidth:0x20   // ARI Capability and Control Register.
+  #define PCIEIP_VF_REG_VF_CAP_REG_ARI_MFVC_FUN_GRP_CAP_K2_E5                                                (0x1<<0) // Multi Functional Virtual Channel (MFVC) Function Groups Capability.
+  #define PCIEIP_VF_REG_VF_CAP_REG_ARI_MFVC_FUN_GRP_CAP_K2_E5_SHIFT                                          0
+  #define PCIEIP_VF_REG_VF_CAP_REG_ARI_ACS_FUN_GRP_CAP_K2_E5                                                 (0x1<<1) // ACS Function Groups Capability.
+  #define PCIEIP_VF_REG_VF_CAP_REG_ARI_ACS_FUN_GRP_CAP_K2_E5_SHIFT                                           1
+  #define PCIEIP_VF_REG_VF_CAP_REG_ARI_NEXT_FUN_NUM_K2_E5                                                    (0xff<<8) // Next Function Number.
+  #define PCIEIP_VF_REG_VF_CAP_REG_ARI_NEXT_FUN_NUM_K2_E5_SHIFT                                              8
+  #define PCIEIP_VF_REG_VF_CAP_REG_ARI_MFVC_FUN_GRP_EN_K2_E5                                                 (0x1<<16) // MFVC Function Groups Enable.
+  #define PCIEIP_VF_REG_VF_CAP_REG_ARI_MFVC_FUN_GRP_EN_K2_E5_SHIFT                                           16
+  #define PCIEIP_VF_REG_VF_CAP_REG_ARI_ACS_FUN_GRP_EN_K2_E5                                                  (0x1<<17) // ACS Function Groups Enable.
+  #define PCIEIP_VF_REG_VF_CAP_REG_ARI_ACS_FUN_GRP_EN_K2_E5_SHIFT                                            17
+  #define PCIEIP_VF_REG_VF_CAP_REG_ARI_FUN_GRP_K2_E5                                                         (0x7<<20) // Function Group.
+  #define PCIEIP_VF_REG_VF_CAP_REG_ARI_FUN_GRP_K2_E5_SHIFT                                                   20
+#define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_K2_E5                                                           0x000110UL //Access:RW   DataWidth:0x20   // TPH Extended Capability Header.
+  #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_K2_E5                                         (0xffff<<0) // TPH Extended Capability ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_K2_E5_SHIFT                                   0
+  #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_K2_E5                                         (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_K2_E5_SHIFT                                   16
+  #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_K2_E5                                        (0xfff<<20) // Next Capability Pointer.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_K2_E5_SHIFT                                  20
+#define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_K2_E5                                                           0x000114UL //Access:R    DataWidth:0x20   // TPH Requestor Capability Register.   SRIOV Note: All VFs in a single PF have the same values for VF_TPH_REQ_CAP_REG_REG. To write this common register, you must perform a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PF TPH_REQ_CAP_REG_REG register.
+  #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_K2_E5                                      (0x1<<0) // No ST Mode Supported.
+  #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_K2_E5_SHIFT                                0
+  #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_K2_E5                                     (0x1<<1) // Interrupt Vector Mode Supported.   Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_K2_E5_SHIFT                               1
+  #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_K2_E5                                     (0x1<<2) // Device Specific Mode Supported.   Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_K2_E5_SHIFT                               2
+  #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_K2_E5                                    (0x1<<8) // Extended TPH Requester Supported.   Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_K2_E5_SHIFT                              8
+  #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_K2_E5                              (0x1<<9) // ST Table Location Bit 0.   Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_K2_E5_SHIFT                        9
+  #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_K2_E5                              (0x1<<10) // ST Table Location Bit 1.   Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_K2_E5_SHIFT                        10
+  #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_K2_E5                               (0x7ff<<16) // ST Table Size.   Note: This register field is sticky.
+  #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_K2_E5_SHIFT                         16
+#define PCIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG_K2_E5                                                       0x000118UL //Access:RW   DataWidth:0x20   // TPH Requestor Control Register.
+  #define PCIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_K2_E5                              (0x7<<0) // ST Mode Select.   Note: The access attributes of this field are as follows:  - Dbi: R/W
+  #define PCIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_K2_E5_SHIFT                        0
+  #define PCIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_K2_E5                                 (0x3<<8) // TPH Requester Enable Bit.
+  #define PCIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_K2_E5_SHIFT                           8
+#define PCIEIP_VF_REG_VF_TPH_ST_TABLE_REG_0_K2_E5                                                            0x00011cUL //Access:RW   DataWidth:0x20   // TPH ST Table Register 0.
+  #define PCIEIP_VF_REG_VF_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_K2_E5                                 (0xff<<0) // ST Table 0 Lower Byte.   Note: The access attributes of this field are as follows:  - Dbi: this field is RW or Tie to 0 by table size configure
+  #define PCIEIP_VF_REG_VF_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_K2_E5_SHIFT                           0
+  #define PCIEIP_VF_REG_VF_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_K2_E5                                (0xff<<8) // ST Table 0 Upper Byte.   Note: The access attributes of this field are as follows:  - Dbi: this field is RW or Tie to 0 by table size configure
+  #define PCIEIP_VF_REG_VF_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_K2_E5_SHIFT                          8
+#define PCIEIP_SHADOW_REG_BAR0_MASK_REG_K2_E5                                                                0x000010UL //Access:W    DataWidth:0x20   // BAR0 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_SHADOW_REG_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_K2_E5                                       (0x1<<0) // BAR0 Mask Enabled.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
+  #define PCIEIP_SHADOW_REG_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_K2_E5_SHIFT                                 0
+  #define PCIEIP_SHADOW_REG_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_K2_E5                                          (0x7fffffff<<1) // BAR0 Mask.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
+  #define PCIEIP_SHADOW_REG_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_K2_E5_SHIFT                                    1
+#define PCIEIP_SHADOW_REG_BAR1_MASK_REG_K2_E5                                                                0x000014UL //Access:RW   DataWidth:0x20   // BAR1 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_SHADOW_REG_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_K2_E5                                       (0x1<<0) // BAR1 Mask Enabled.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
+  #define PCIEIP_SHADOW_REG_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_K2_E5_SHIFT                                 0
+  #define PCIEIP_SHADOW_REG_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_K2_E5                                          (0x7fffffff<<1) // BAR1 Mask.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
+  #define PCIEIP_SHADOW_REG_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_K2_E5_SHIFT                                    1
+#define PCIEIP_SHADOW_REG_BAR4_MASK_REG_K2_E5                                                                0x000020UL //Access:W    DataWidth:0x20   // BAR4 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_SHADOW_REG_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_K2_E5                                       (0x1<<0) // BAR4 Mask Enabled.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
+  #define PCIEIP_SHADOW_REG_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_K2_E5_SHIFT                                 0
+  #define PCIEIP_SHADOW_REG_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_K2_E5                                          (0x7fffffff<<1) // BAR4 Mask.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
+  #define PCIEIP_SHADOW_REG_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_K2_E5_SHIFT                                    1
+#define PCIEIP_SHADOW_REG_BAR5_MASK_REG_K2_E5                                                                0x000024UL //Access:W    DataWidth:0x20   // BAR5 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_SHADOW_REG_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_K2_E5                                       (0x1<<0) // BAR5 Mask Enabled.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
+  #define PCIEIP_SHADOW_REG_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_K2_E5_SHIFT                                 0
+  #define PCIEIP_SHADOW_REG_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_K2_E5                                          (0x7fffffff<<1) // BAR5 Mask.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
+  #define PCIEIP_SHADOW_REG_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_K2_E5_SHIFT                                    1
+#define PCIEIP_SHADOW_REG_EXP_ROM_BAR_MASK_REG_K2_E5                                                         0x000030UL //Access:R    DataWidth:0x20   // Expansion ROM BAR and Mask Register.  The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_SHADOW_REG_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_K2_E5                                       (0x1<<0) // Expansion ROM Bar Mask Register Enabled.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: if ROM_BAR_ENABLED then W else R
+  #define PCIEIP_SHADOW_REG_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_K2_E5_SHIFT                                 0
+  #define PCIEIP_SHADOW_REG_EXP_ROM_BAR_MASK_REG_ROM_MASK_K2_E5                                              (0x7fffffff<<1) // Expansion ROM Mask.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: if ROM_BAR_ENABLED then W else R
+  #define PCIEIP_SHADOW_REG_EXP_ROM_BAR_MASK_REG_ROM_MASK_K2_E5_SHIFT                                        1
+#define PCIEIP_SHADOW_REG_SHADOW_SRIOV_INITIAL_VFS_K2_E5                                                     0x0001c4UL //Access:R    DataWidth:0x20   // TotalVFs InitialVFs Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two of these registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address.
+  #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_INITIAL_VFS_SHADOW_SRIOV_INITIAL_VFS_K2_E5                          (0xffff<<0) // InitialVFs. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two InitialVFs registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W
+  #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_INITIAL_VFS_SHADOW_SRIOV_INITIAL_VFS_K2_E5_SHIFT                    0
+  #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_INITIAL_VFS_SHADOW_SRIOV_TOTAL_VFS_K2_E5                            (0xffff<<16) // Total VFs (Max Number of VFs). For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two TotalVFs registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W
+  #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_INITIAL_VFS_SHADOW_SRIOV_TOTAL_VFS_K2_E5_SHIFT                      16
+#define PCIEIP_SHADOW_REG_SHADOW_SRIOV_VF_OFFSET_POSITION_K2_E5                                              0x0001ccUL //Access:R    DataWidth:0x20   // VF Stride and Offset Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
+  #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_VF_OFFSET_POSITION_SHADOW_SRIOV_VF_STRIDE_K2_E5                     (0xffff<<0) // VF Stride. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two VF Stride registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W
+  #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_VF_OFFSET_POSITION_SHADOW_SRIOV_VF_STRIDE_K2_E5_SHIFT               0
+  #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_VF_OFFSET_POSITION_SHADOW_SRIOV_VF_OFFSET_K2_E5                     (0xffff<<16) // First VF Offset. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two First VF Offset registers at this address location; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W
+  #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_VF_OFFSET_POSITION_SHADOW_SRIOV_VF_OFFSET_K2_E5_SHIFT               16
+#define PCIEIP_SHADOW_REG_SRIOV_BAR0_MASK_REG_K2_E5                                                          0x0001dcUL //Access:W    DataWidth:0x20   // BAR0 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_SHADOW_REG_SRIOV_BAR0_MASK_REG_PCI_SRIOV_BAR0_ENABLED_K2_E5                                 (0x1<<0) // BAR0 Mask Enabled.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
+  #define PCIEIP_SHADOW_REG_SRIOV_BAR0_MASK_REG_PCI_SRIOV_BAR0_ENABLED_K2_E5_SHIFT                           0
+  #define PCIEIP_SHADOW_REG_SRIOV_BAR0_MASK_REG_PCI_SRIOV_BAR0_MASK_K2_E5                                    (0x7fffffff<<1) // BAR0 Mask.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
+  #define PCIEIP_SHADOW_REG_SRIOV_BAR0_MASK_REG_PCI_SRIOV_BAR0_MASK_K2_E5_SHIFT                              1
+#define PCIEIP_SHADOW_REG_SRIOV_BAR1_MASK_REG_K2_E5                                                          0x0001e0UL //Access:RW   DataWidth:0x20   // BAR1 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_SHADOW_REG_SRIOV_BAR1_MASK_REG_PCI_SRIOV_BAR1_ENABLED_K2_E5                                 (0x1<<0) // BAR1 Mask Enabled.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
+  #define PCIEIP_SHADOW_REG_SRIOV_BAR1_MASK_REG_PCI_SRIOV_BAR1_ENABLED_K2_E5_SHIFT                           0
+  #define PCIEIP_SHADOW_REG_SRIOV_BAR1_MASK_REG_PCI_SRIOV_BAR1_MASK_K2_E5                                    (0x7fffffff<<1) // BAR1 Mask.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
+  #define PCIEIP_SHADOW_REG_SRIOV_BAR1_MASK_REG_PCI_SRIOV_BAR1_MASK_K2_E5_SHIFT                              1
+#define PCIEIP_SHADOW_REG_SRIOV_BAR2_MASK_REG_K2_E5                                                          0x0001e4UL //Access:W    DataWidth:0x20   // BAR2 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_SHADOW_REG_SRIOV_BAR2_MASK_REG_PCI_SRIOV_BAR2_ENABLED_K2_E5                                 (0x1<<0) // BAR2 Mask Enabled.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
+  #define PCIEIP_SHADOW_REG_SRIOV_BAR2_MASK_REG_PCI_SRIOV_BAR2_ENABLED_K2_E5_SHIFT                           0
+  #define PCIEIP_SHADOW_REG_SRIOV_BAR2_MASK_REG_PCI_SRIOV_BAR2_MASK_K2_E5                                    (0x7fffffff<<1) // BAR2 Mask.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
+  #define PCIEIP_SHADOW_REG_SRIOV_BAR2_MASK_REG_PCI_SRIOV_BAR2_MASK_K2_E5_SHIFT                              1
+#define PCIEIP_SHADOW_REG_SRIOV_BAR3_MASK_REG_K2_E5                                                          0x0001e8UL //Access:RW   DataWidth:0x20   // BAR3 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_SHADOW_REG_SRIOV_BAR3_MASK_REG_PCI_SRIOV_BAR3_ENABLED_K2_E5                                 (0x1<<0) // BAR3 Mask Enabled.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
+  #define PCIEIP_SHADOW_REG_SRIOV_BAR3_MASK_REG_PCI_SRIOV_BAR3_ENABLED_K2_E5_SHIFT                           0
+  #define PCIEIP_SHADOW_REG_SRIOV_BAR3_MASK_REG_PCI_SRIOV_BAR3_MASK_K2_E5                                    (0x7fffffff<<1) // BAR3 Mask.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
+  #define PCIEIP_SHADOW_REG_SRIOV_BAR3_MASK_REG_PCI_SRIOV_BAR3_MASK_K2_E5_SHIFT                              1
+#define PCIEIP_SHADOW_REG_SRIOV_BAR4_MASK_REG_K2_E5                                                          0x0001ecUL //Access:W    DataWidth:0x20   // BAR4 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_SHADOW_REG_SRIOV_BAR4_MASK_REG_PCI_SRIOV_BAR4_ENABLED_K2_E5                                 (0x1<<0) // BAR4 Mask Enabled.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
+  #define PCIEIP_SHADOW_REG_SRIOV_BAR4_MASK_REG_PCI_SRIOV_BAR4_ENABLED_K2_E5_SHIFT                           0
+  #define PCIEIP_SHADOW_REG_SRIOV_BAR4_MASK_REG_PCI_SRIOV_BAR4_MASK_K2_E5                                    (0x7fffffff<<1) // BAR4 Mask.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
+  #define PCIEIP_SHADOW_REG_SRIOV_BAR4_MASK_REG_PCI_SRIOV_BAR4_MASK_K2_E5_SHIFT                              1
+#define PCIEIP_SHADOW_REG_SRIOV_BAR5_MASK_REG_K2_E5                                                          0x0001f0UL //Access:RW   DataWidth:0x20   // BAR5 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".
+  #define PCIEIP_SHADOW_REG_SRIOV_BAR5_MASK_REG_PCI_SRIOV_BAR5_ENABLED_K2_E5                                 (0x1<<0) // BAR5 Mask Enabled.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
+  #define PCIEIP_SHADOW_REG_SRIOV_BAR5_MASK_REG_PCI_SRIOV_BAR5_ENABLED_K2_E5_SHIFT                           0
+  #define PCIEIP_SHADOW_REG_SRIOV_BAR5_MASK_REG_PCI_SRIOV_BAR5_MASK_K2_E5                                    (0x7fffffff<<1) // BAR5 Mask.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
+  #define PCIEIP_SHADOW_REG_SRIOV_BAR5_MASK_REG_PCI_SRIOV_BAR5_MASK_K2_E5_SHIFT                              1
+#define SEM_FAST_REG_RAM_EXT_DISABLE                                                                         0x000004UL //Access:RW   DataWidth:0x1    // Disable for SDM write to int_ram.
+#define SEM_FAST_REG_INT_STS                                                                                 0x000040UL //Access:R    DataWidth:0x1    // Multi Field Register.
+  #define SEM_FAST_REG_INT_STS_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define SEM_FAST_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                           0
+#define SEM_FAST_REG_INT_MASK                                                                                0x000044UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define SEM_FAST_REG_INT_MASK_ADDRESS_ERROR                                                                (0x1<<0) // This bit masks, when set, the Interrupt bit: SEM_FAST_REG_INT_STS.ADDRESS_ERROR .
+  #define SEM_FAST_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                          0
+#define SEM_FAST_REG_INT_STS_WR                                                                              0x000048UL //Access:WR   DataWidth:0x1    // Multi Field Register.
+  #define SEM_FAST_REG_INT_STS_WR_ADDRESS_ERROR                                                              (0x1<<0) // Signals an unknown address to the rf module.
+  #define SEM_FAST_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                        0
+#define SEM_FAST_REG_INT_STS_CLR                                                                             0x00004cUL //Access:RC   DataWidth:0x1    // Multi Field Register.
+  #define SEM_FAST_REG_INT_STS_CLR_ADDRESS_ERROR                                                             (0x1<<0) // Signals an unknown address to the rf module.
+  #define SEM_FAST_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                       0
+#define SEM_FAST_REG_ERROR_RST                                                                               0x000050UL //Access:W    DataWidth:0x1    // Reset to error interrupt.
+#define SEM_FAST_REG_PARITY_RST                                                                              0x000054UL //Access:W    DataWidth:0x1    // Reset to parity interrupt.
+#define SEM_FAST_REG_PRTY_MASK_H_0_K2                                                                        0x000204UL //Access:RW   DataWidth:0x7    // Multi Field Register.
+  #define SEM_FAST_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2                                                    (0x1<<0) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
+  #define SEM_FAST_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2_SHIFT                                              0
+  #define SEM_FAST_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2                                                    (0x1<<1) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
+  #define SEM_FAST_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2_SHIFT                                              1
+  #define SEM_FAST_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_K2                                                    (0x1<<2) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
+  #define SEM_FAST_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_K2_SHIFT                                              2
+  #define SEM_FAST_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2                                                    (0x1<<3) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
+  #define SEM_FAST_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2_SHIFT                                              3
+  #define SEM_FAST_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2                                                    (0x1<<4) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
+  #define SEM_FAST_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2_SHIFT                                              4
+  #define SEM_FAST_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2                                                    (0x1<<5) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
+  #define SEM_FAST_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_SHIFT                                              5
+  #define SEM_FAST_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2                                                    (0x1<<6) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
+  #define SEM_FAST_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2_SHIFT                                              6
+#define SEM_FAST_REG_MEM_ECC_EVENTS_K2                                                                       0x000210UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define SEM_FAST_REG_RESERVED_21C_K2                                                                         0x00021cUL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_228_K2                                                                         0x000228UL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_234_K2                                                                         0x000234UL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_23C_K2                                                                         0x00023cUL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_244_K2                                                                         0x000244UL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_250_K2                                                                         0x000250UL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_258_K2                                                                         0x000258UL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_260_K2                                                                         0x000260UL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_268_K2                                                                         0x000268UL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_270_K2                                                                         0x000270UL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_278_K2                                                                         0x000278UL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_280_K2                                                                         0x000280UL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_288_K2                                                                         0x000288UL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_28C_K2                                                                         0x00028cUL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_290_K2                                                                         0x000290UL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_294_K2                                                                         0x000294UL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_298_K2                                                                         0x000298UL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_29C_K2                                                                         0x00029cUL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_2A0_K2                                                                         0x0002a0UL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_2A4_K2                                                                         0x0002a4UL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_2A8_K2                                                                         0x0002a8UL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_2AC_K2                                                                         0x0002acUL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_2B0_K2                                                                         0x0002b0UL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_2B4_K2                                                                         0x0002b4UL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_2B8_K2                                                                         0x0002b8UL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_2BC_K2                                                                         0x0002bcUL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_2C0_K2                                                                         0x0002c0UL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_2CC_K2                                                                         0x0002ccUL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_RESERVED_2D0_K2                                                                         0x0002d0UL //Access:R    DataWidth:0x20   // Reserved
+#define SEM_FAST_REG_GPRE                                                                                    0x000400UL //Access:R    DataWidth:0x20   // This (indirect) register array of 32 registers provides read-only access of the GPRE registers. Register can be accessed only when storm is stalled. Address bit 5 - select between GPRE of Strom B (when 1) and StromA. Address bits 4:0 - select GPRE index.
+#define SEM_FAST_REG_GPRE_SIZE                                                                               32
+#define SEM_FAST_REG_GPRE0                                                                                   0x000480UL //Access:R    DataWidth:0x20   // 15-0 STORM0 GPRE0 bits 15:0. 31-16 STORM1 GPRE0 bits 15:0.
+#define SEM_FAST_REG_STALL_MASK                                                                              0x000484UL //Access:RW   DataWidth:0x16   // Provides a vector for enabling/masking the various stall sources from asserting stall. Stall source numeration: 21 - misc_local_mux_other_stall, 20 - ram_mux_bkpt_stall, 19 -  mux_lock_stall, 18 - pram_mux_pipe_stall, 17 - rbc_mux_stall_storm, 16 - storm_attn_stall, 15 - pram_mux_prty_stall, 14 - mux_common_mux_iram_stall, 13 - fin_stall, 12 - rbc_mux_stall_common, 11 -  pram_mux_bkpt_stall, 10 - misc_local_mux_int_stall, 9 - misc_local_mux_ext_stall, 8 - misc_local_mux_sel_stall_en, 7 - debug_stall, 6 - common_mux_vfc_load_stall, 5 - common_mux_vfc_store_stall, 4 - ext_ld_stall, 3 - ext_st_stall, 2 - cam_rsp_stall, 1 - cam_req_stall, 0 - mux_common_col_stall
+#define SEM_FAST_REG_STALL_COMMON_E5                                                                         0x000488UL //Access:RW   DataWidth:0x1    // This register is used to define a stall condition towards both STROM.
+#define SEM_FAST_REG_STALL_0_BB_K2                                                                           0x000488UL //Access:RW   DataWidth:0x1    // This register is used to define the state of an independent stall source. This is the first of three provided via the RBC. The value written to the lsb if this register will define the value it is given. This stall source can be masked independently from the other stall sources.
+#define SEM_FAST_REG_STALL_1_BB_K2                                                                           0x00048cUL //Access:RW   DataWidth:0x1    // This register is used to define the state of an independent stall source. This is the second of three provided via the RBC. The value written to the lsb if this register will define the value it is given. This stall source can be masked independently from the other stall sources.
+#define SEM_FAST_REG_STALL_2_BB_K2                                                                           0x000490UL //Access:RW   DataWidth:0x1    // This register is used to define the state of an independent stall source. This is the last of three provided via the RBC. The value written to the lsb if this register will define the value it is given. This stall source can be masked independently from the other stall sources.
+#define SEM_FAST_REG_STALLED                                                                                 0x000494UL //Access:R    DataWidth:0x4    // This register provides a status to indicate whether or not the Storm is currently stalled. bit0- STORM A. bit1- STORM B. bit2- Pram Breakpoint. bit3- IRAM Breakpoint.
+#define SEM_FAST_REG_STALL_RST                                                                               0x000498UL //Access:W    DataWidth:0x1    // Writing this register with any value causes all the internal and external stall sources to be reset, resulting in the negation of the stall signal.
+#define SEM_FAST_REG_STORM_ATTN_STALL_CLR                                                                    0x00049cUL //Access:W    DataWidth:0x1    // Used to clear the latched storm attention stall signal.
+#define SEM_FAST_REG_STORM_STACK_SIZE                                                                        0x0004a0UL //Access:RW   DataWidth:0x4    // Defines the size of the Storm stack.
+#define SEM_FAST_REG_PC_BREAKPOINT                                                                           0x0004a4UL //Access:RW   DataWidth:0x10   // This register defines the PC breakpoint PRAM address. Anytime the Storm reads from this address while it is executing, it will be stalled.
+#define SEM_FAST_REG_PRAM_PRTY_ADDR_LOW                                                                      0x0004a8UL //Access:R    DataWidth:0xf    // This register delivers the PRAM address for the low-word instruction that was being read when the most recent PRAM parity error occurred.
+#define SEM_FAST_REG_PRAM_PRTY_ADDR_HIGH                                                                     0x0004acUL //Access:R    DataWidth:0xf    // This register delivers the PRAM address for the high-word instruction that was being read when the most recent PRAM parity error occurred.
+#define SEM_FAST_REG_PRAM_PRTY_RELEASE                                                                       0x0004b0UL //Access:W    DataWidth:0x1    // Writing this register with any value causes the PRAM ECC replay logic to be executed and the PRAM parity stall to be released following the reload of the PRAM data path.
+#define SEM_FAST_REG_PRAM_PRTY_INT_CLR                                                                       0x0004b4UL //Access:W    DataWidth:0x1    // Writing this register with any value causes the PRAM parity error to be cleared.
+#define SEM_FAST_REG_PORT_ID_WIDTH                                                                           0x0004b8UL //Access:RW   DataWidth:0x2    // from the Opaque FID and presented to the Storm. A value of 1 means that the PortID will be taken as a single bit , a value of 2 means that the PortID will be taken as a 2-bit field. A value of zero means that the PortID is not extracted and is always assumed to be zero.
+#define SEM_FAST_REG_PORT_ID_OFFSET                                                                          0x0004bcUL //Access:RW   DataWidth:0x5    // Defines the offset (in bits) from the lsb of the CID in which to assign to bit-0 of the port ID. I.e. if port_id_wdth is set to 0x1 and port_id_ofset is set to 0x8, then the port ID is assigned from bits [9:8] of the CID.
+#define SEM_FAST_REG_ACTIVE_REG_SET                                                                          0x0004c0UL //Access:R    DataWidth:0x1    // Defines the Storm register file set that is currently active. 0 - STORM A 1 - STORM B
+#define SEM_FAST_REG_STATE_MACHINE                                                                           0x0004c4UL //Access:R    DataWidth:0x19   // State machine bus spelling for debug: 0:2 - DRA WR STM Core_A, 3:5 - DRA WR STM Core_B, 6:8 - DRA RD STM Core_A, 9:11 - DRA RD STM Core_B,                        12:14 - DRA INT STM Core_A, 15:17 - DRA INT STM Core_B, 18:19 - FIN STM Core_A, 20:21 - FIN STM Core_B, 22:24 - VFC FIFO Cnt.
+#define SEM_FAST_REG_PRAM_LAST_ADDR_A_E5                                                                     0x0004c8UL //Access:R    DataWidth:0x20   // Last read address from STORM to pram {add_p_out_high; 1'b0; add_p_out_low}.
+#define SEM_FAST_REG_PRAM_LAST_ADDR_BB_K2                                                                    0x0004c8UL //Access:R    DataWidth:0x20   // Last read address from STORM to pram {add_p_out_high; 1'b0; add_p_out_low}.
+#define SEM_FAST_REG_IRAM_ECC_ERROR_INJ                                                                      0x0004ccUL //Access:RW   DataWidth:0x7    // Writing this register results in internal RAM ECC error injection the next time there is a write to the internal RAM by RBC. For this, any set bit in the data field will result in a corresponding bit inversion in the written data while ECC is calculated according to original data. bit 6 - when set, invert bit on complementary index 4:0. bit 5 - when set, invert bit on index 4:0.                          bits 4:0 - bit inversion index (0-31), Note - When setting only a single bit inversion (only bit 5 or 6 set ), ECC mechanism is expected to fix error. When setting both bit inversion (bits 5 and 6 set), ECC mechanism is expected to only detect error without fix and parity interrupt is expected to be asserted.
+#define SEM_FAST_REG_ECO_RESERVED                                                                            0x0004d0UL //Access:RW   DataWidth:0x20   // Reserved bits for ECO.
+#define SEM_FAST_REG_STORM_PC                                                                                0x0004d4UL //Access:R    DataWidth:0x20   // This register delivers the Storm PC for read-only debug access. 15-0 - STORM A. 31-16  STROM B.
+#define SEM_FAST_REG_DATA_BREAKPOINT_ADDRESS_START_E5                                                        0x0004d8UL //Access:RW   DataWidth:0xf    // the IRAM is accessed in the range between the start address and the end address (which matches the access type defined in data_breakpoint_access_set), the STORMs bits 15:0  - IRAM stall start address.
+#define SEM_FAST_REG_DATA_BREAKPOINT_ADDRESS_END_E5                                                          0x0004dcUL //Access:RW   DataWidth:0xf    // the IRAM is accessed in the range between the start address and the end address (which matches the access type defined in data_breakpoint_access_set), the STORMs will be stalled. bit15:0  - IRAM stall end address.
+#define SEM_FAST_REG_DATA_BREAKPOINT_ACCESS_SET_E5                                                           0x0004e0UL //Access:RW   DataWidth:0x6    // This register defines the data breakpoint conditions in which IRAM breakpoint stall will be initiate. bit0   - stall on read access. bit1   - stall on write access. bit3:2 - stall on write BE (bit2 -to IRAM's 32lsb, bit3 - to IRAM's 32msb). bit4   - stall on SDM/GRC access. bit5   - stall on storm access.
+#define SEM_FAST_REG_DATA_BREAKPOINT_ADDRESS_E5                                                              0x0004e4UL //Access:R    DataWidth:0x10   // This register defines the IRAM address for which the data breakpoint stall was set. bits 0:15 -  IRAM address.
+#define SEM_FAST_REG_PRAM_LAST_ADDR_B_E5                                                                     0x0004e8UL //Access:R    DataWidth:0x20   // Last read address from STORM to pram {add_p_out_high; 1'b0; add_p_out_low}.
+#define SEM_FAST_REG_STALL_STORM_A_E5                                                                        0x0004ecUL //Access:RW   DataWidth:0x1    // This register is used to define a stall condition exclusive towards STORM_A.
+#define SEM_FAST_REG_STALL_STORM_B_E5                                                                        0x0004f0UL //Access:RW   DataWidth:0x1    // This register is used to define a stall condition exclusive towards STORM_B.
+#define SEM_FAST_REG_RT_CLK_TICK_VALUE                                                                       0x000500UL //Access:RW   DataWidth:0x20   // This array of indirect registers defines the modulus (roll-over) values for the corresponding real time clocks. The sub-address for this indirect register is the RTC index.
+#define SEM_FAST_REG_RT_CLK_TICK_VALUE_SIZE_BB_K2                                                            10
+#define SEM_FAST_REG_RT_CLK_TICK_VALUE_SIZE_E5                                                               4
+#define SEM_FAST_REG_RT_CLK_TICK_SRC                                                                         0x000540UL //Access:RW   DataWidth:0x3    // Array of ten registers. These are used to select the Storm which is allowed to update the corresponding real-time clock with regard to the associated RTClkTickValue. The Storm decode assignments used for this register are as follows; T-Storm=0; M-Storm=1; U-Storm=2; X-Storm=3; Y-Storm=4; P-Storm=5. The sub-address for this indirect register is the RTC index.
+#define SEM_FAST_REG_RT_CLK_TICK_SRC_SIZE_BB_K2                                                              10
+#define SEM_FAST_REG_RT_CLK_TICK_SRC_SIZE_E5                                                                 4
+#define SEM_FAST_REG_RT_CLK_INIT_VALUE                                                                       0x000580UL //Access:RW   DataWidth:0x20   // Array of ten registers. These are used to define the initialization value for each of the real-time clocks. This value is assigned to the corresponding real-time clock only when the Storm corresponding to the value stored in the RTClkInitSrc register makes an RTC update assertion. The sub-address for this indirect register is the RTC index.
+#define SEM_FAST_REG_RT_CLK_INIT_VALUE_SIZE_BB_K2                                                            10
+#define SEM_FAST_REG_RT_CLK_INIT_VALUE_SIZE_E5                                                               4
+#define SEM_FAST_REG_RT_CLK_INIT_SRC                                                                         0x0005c0UL //Access:RW   DataWidth:0x3    // Array of ten registers. These are used to select the Storm which is allowed to initialize the corresponding real-time clock with the value provided by the associated RTClkInitValue register. The Storm decode assignments used for this register are as follows; T-Storm=0; M-Storm=1; U-Storm=2; X-Storm=3; Y-Storm=4; P-Storm=5. The sub-address for this indirect register is the RTC index.
+#define SEM_FAST_REG_RT_CLK_INIT_SRC_SIZE_BB_K2                                                              10
+#define SEM_FAST_REG_RT_CLK_INIT_SRC_SIZE_E5                                                                 4
+#define SEM_FAST_REG_REAL_TIME_CNT                                                                           0x000600UL //Access:R    DataWidth:0x20   // This array of indirect registers provides read access to the real time clock values. The sub-address for this indirect register is the RTC index.
+#define SEM_FAST_REG_REAL_TIME_CNT_SIZE                                                                      10
+#define SEM_FAST_REG_RT_CLK_ENABLE                                                                           0x000628UL //Access:RW   DataWidth:0x4    // This register is a vector containing a bit per RTC used to enable each of the ten real-time clocks. The bit index corresponds with the ID of the real-time clock.
+#define SEM_FAST_REG_CAM_MASK_LSB                                                                            0x00062cUL //Access:RW   DataWidth:0x20   // The following register assigns bits 31:0 of the CAM mask in preparation for upcoming RBC requested SEARCH and/or ADD commands.
+#define SEM_FAST_REG_CAM_MASK_MIDDLE                                                                         0x000630UL //Access:RW   DataWidth:0x20   // The following register assigns bits 63:31 of the CAM mask in preparation for upcoming RBC requested SEARCH and/or ADD commands.
+#define SEM_FAST_REG_CAM_MASK_MSB                                                                            0x000634UL //Access:RW   DataWidth:0x4    // The following register assigns bits 67:64 of the CAM mask in preparation for upcoming RBC requested SEARCH and/or ADD commands.
+#define SEM_FAST_REG_CAM_VALUE_LSB                                                                           0x000638UL //Access:RW   DataWidth:0x20   // The following register assigns bits 31:0 of the CAM value in preparation for upcoming RBC requested SEARCH, ADD and/or INVALIDATE commands.
+#define SEM_FAST_REG_CAM_VALUE_MIDDLE                                                                        0x00063cUL //Access:RW   DataWidth:0x20   // The following register assigns bits 63:32 of the CAM value in preparation for upcoming RBC requested SEARCH, ADD and/or INVALIDATE commands.
+#define SEM_FAST_REG_CAM_VALUE_MSB                                                                           0x000640UL //Access:RW   DataWidth:0x4    // The following register assigns bits 67:64 of the CAM value in preparation for upcoming RBC requested SEARCH, ADD and/or INVALIDATE commands.
+#define SEM_FAST_REG_CAM_RD_DATA_LSB                                                                         0x000644UL //Access:R    DataWidth:0x20   // This register delivers the LSB read data from the CAM for the most recent RBC read request issued. The data returned is defined as follows: cam_rd_data_lsb = cam_rd_data[31:0].
+#define SEM_FAST_REG_CAM_RD_DATA_MIDDLE                                                                      0x000648UL //Access:R    DataWidth:0x20   // This register delivers middle read data from the CAM for the most recent RBC read request issued. The data returned is defined as follows: cam_rd_data_middle = cam_read_data[63:32].
+#define SEM_FAST_REG_CAM_RD_DATA_MSB                                                                         0x00064cUL //Access:R    DataWidth:0x4    // This register delivers the MSB read data from the CAM for the most recent RBC read request issued. The data returned is defined as follows: cam_rd_data_msb[3:0] = cam_read_data[67:64].
+#define SEM_FAST_REG_CAM_VALID                                                                               0x000650UL //Access:R    DataWidth:0x1    // This register delivers the valid bit from CAM for the most recent RBC read request issued. The valid bit is returned on bit-0 of the data. All other bits will be zero.
+#define SEM_FAST_REG_CAM_SEARCH                                                                              0x000654UL //Access:R    DataWidth:0x9    // This register delivers CAM search response data from CAM for the most recent RBC search request issued. The data returned is defined as follows: cam_search[8] = match, cam_rd_data_msb[6:0] = search_index.
+#define SEM_FAST_REG_CAM_CONTROL                                                                             0x000658UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define SEM_FAST_REG_CAM_CONTROL_CAM_INIT_EN                                                               (0x1<<0) // Writing a one to this register bit (transition from 0 to 1) causes the entire CAM to be zeroed and all entries to be invalidated.
+  #define SEM_FAST_REG_CAM_CONTROL_CAM_INIT_EN_SHIFT                                                         0
+  #define SEM_FAST_REG_CAM_CONTROL_CAM_SCRUB_HIT_EN                                                          (0x1<<1) // When set, this bit enables hit parity scrubbing on the CAM.
+  #define SEM_FAST_REG_CAM_CONTROL_CAM_SCRUB_HIT_EN_SHIFT                                                    1
+  #define SEM_FAST_REG_CAM_CONTROL_CAM_SCRUB_MISS_EN                                                         (0x1<<2) // When set, this bit enables miss parity scrubbing on the CAM.
+  #define SEM_FAST_REG_CAM_CONTROL_CAM_SCRUB_MISS_EN_SHIFT                                                   2
+#define SEM_FAST_REG_CAM_INIT_IN_PROCESS                                                                     0x00065cUL //Access:R    DataWidth:0x1    // This register is set after the CAM initialization is started (by writing to cam_init) and remains set until the entire CAM initialization is complete.
+#define SEM_FAST_REG_CAM_MATCH_VECTOR                                                                        0x000730UL //Access:R    DataWidth:0x20   // This array of registers returns the 128-bit CAM match vector returned in the most recent RBC-initiaged search request. For this, cam_match_vector[0] returns bits 31:0 of the vector, cam_match_vector[1] returns bits 63:32, and so on.
+#define SEM_FAST_REG_CAM_MATCH_VECTOR_SIZE                                                                   4
+#define SEM_FAST_REG_DEBUG_ACTIVE                                                                            0x000740UL //Access:RW   DataWidth:0x1    // Used to activate/deactivate the SEMI fast debug, based on the mode defined by the DebugMode register; 0=inactive, 1=active.
+#define SEM_FAST_REG_DEBUG_MODE                                                                              0x000744UL //Access:RW   DataWidth:0x3    // Defines the use of the fast debug channel, based on the following enumerations: 0x0-PRINTF; 0x1-PRAM address; 0x2-Reserved; 0x3-DRA read + DRA write; 0x4-load/store address; 0x5-fast DRA state machines; 0x6-recording handler debug; 0x7- Performance monitor. Note: this register is not applicable when DebugActive=0.
+#define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE                                                                  0x000748UL //Access:RW   DataWidth:0x3    // Vector used to disable any of the following debug sources for modes 2 and 3 on the fast debug channel: b0-DRA write disable; b1-DRA read disable; b2-interrupt disable.
+#define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE                                                                   0x00074cUL //Access:RW   DataWidth:0x2    // Vector used to disable any of the following debug sources for mode-4 on the fast debug channel: b0-store data disable; b1-load data disable.
+#define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE                                                                   0x000750UL //Access:RW   DataWidth:0x6    // Vector used to disable any of the following debug sources for mode-6 on the fast debug channel: b0-dra_in disable; b1-fin disable; b2-load disable; b3-thread start disable; b4-store disable; b5-GPRE read data disable.
+#define SEM_FAST_REG_FILTER_CID                                                                              0x000754UL //Access:RW   DataWidth:0x20   // Connection id that should compared with cid field of the data (in Dra-In message); Note: applicable only when FILTER_EN.FILTER_CID_USE_RCVD =0.
+#define SEM_FAST_REG_FILTER_EVENT_ID                                                                         0x000758UL //Access:RW   DataWidth:0x8    // Event id that should compared with event id field of the data (in Dra-In message).
+#define SEM_FAST_REG_EVENT_ID_MASK                                                                           0x00075cUL //Access:RW   DataWidth:0x8    // Mask for event id. 1- specified bit is ignored; 0 - specified bit is checked.
+#define SEM_FAST_REG_EVENT_ID_RANGE_STRT                                                                     0x000760UL //Access:RW   DataWidth:0x8    // Used to provide a starting range for the event ID range filter. A range of event IDs to capture for fast debug mode-6 and for active statistics will start with this value.
+#define SEM_FAST_REG_EVENT_ID_RANGE_END                                                                      0x000764UL //Access:RW   DataWidth:0x8    // Used to provide a ending range for the event ID range filter. A range of event IDs to capture for fast debug mode-6 and for active statistics will end with this value.
+#define SEM_FAST_REG_RECORD_FILTER_ENABLE                                                                    0x000768UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_EN                                                    (0x3<<0) // (a) 00 - Filter off; in that case all data should be transmitted to the DBG block without any filtering implemented (data should bypass filtering machine).; (b) 01 - Filter on prior to trigger event (asserted by the DBG block) only; When off - data should be transmitted to the DBG block without any filtering. ; (c) 10 - Filter on upon trigger event (asserted by the DBG block) only. When off - data should be transmitted to the DBG block without any filtering.; (d) 11 - Filter on - constant filtering; in this case the triggering event (asserted by the DBG block) is irrelevant.
+  #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_EN_SHIFT                                              0
+  #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_CID_RCRD                                              (0x1<<2) // (a) 1 - use the recorded connection id field which arrives from the DBG block (dbg_sem_cid interface) for compariso; NOTE: NA if need to filter connection id prior to trigger event (filter_en=01 OR filter_en=11) as the connection id field which arrives from the DBG block (dbg_sem_cid interface) is valid upon triggering event only; (b) 0 - use the configuration connection id field (filter_cid) for comparison.
+  #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_CID_RCRD_SHIFT                                        2
+  #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_CID_EN                                                (0x1<<3) // Used to enable CID/TID filter for recording handlers, when set.
+  #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_CID_EN_SHIFT                                          3
+  #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_EVNT_ID_EN                                            (0x1<<4) // Used to enable Event ID filter for recording handlers, when set.
+  #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_EVNT_ID_EN_SHIFT                                      4
+  #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_DRA_SRC                                               (0x3<<5) // Used to define the DRA-In source that should be compared for recording handlers. A value of 0 indicates FIC0; a value of 1 indicates FIC1; a value of 2 indicates passive buffer.
+  #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_DRA_SRC_SHIFT                                         5
+  #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_DRA_SRC_EN                                            (0x1<<7) // Used to enable DRA source filter for recording handlers, when set.
+  #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_DRA_SRC_EN_SHIFT                                      7
+  #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_EVENT_ID_RANGE_EN                                     (0x1<<8) // Used to enable filtering based on a range of event IDs rather than "match" filtering. When set, the event ID range is defined by the EventIDRangeStrt and EventIDRangeEnd registers.
+  #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_EVENT_ID_RANGE_EN_SHIFT                               8
+  #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_STORE_EN                                              (0x1<<9) // Used to enable the debug store address filter for fast debug, when set.
+  #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_STORE_EN_SHIFT                                        9
+#define SEM_FAST_REG_DBG_STORE_ADDR_MASK                                                                     0x00076cUL //Access:RW   DataWidth:0x10   // Used in conjunction with dbg_store_addr_value to filter the store data that is sent through the fast debug channel for all debug modes that transmit store transactions. For all the bits of the mask that are set, then only if the corresponding bits of the store address match dbg_store_addr_value, the transaction will be delivered on the debug mux.
+#define SEM_FAST_REG_DBG_STORE_ADDR_VALUE                                                                    0x000770UL //Access:RW   DataWidth:0x10   // Used in conjunction with dbg_store_addr_mask to filter the store data that is sent through the fast debug channel for all debug modes that transmit store transactions. For all the bits of dbg_store_addr_mask that are set, then only if the corresponding bits of the store address match the value of this register, the transaction will be delivered on the debug mux.
+#define SEM_FAST_REG_DBG_GPRE_VECT_E5                                                                        0x000774UL //Access:RW   DataWidth:0x8    // This 8-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug channel when they are accessed for read by the Storm during mode-6 debug (handler trace). For this, bit-0 corresponds with GPRE[0-3] and bit-7 corresponds with GPRE[28-31].
+#define SEM_FAST_REG_SYNC_DRA_RD_ALM_FULL                                                                    0x000840UL //Access:RW   DataWidth:0x3    // Almost full for DRA_RD SYNC FIFO.
+#define SEM_FAST_REG_SYNC_RAM_RD_ALM_FULL                                                                    0x000844UL //Access:RW   DataWidth:0x5    // Almost full for RAM_RD SYNC FIFO.
+#define SEM_FAST_REG_SYNC_EXT_STORE_ALM_FULL                                                                 0x000848UL //Access:RW   DataWidth:0x6    // Almost full for EXT_STORE SYNC FIFO.
+#define SEM_FAST_REG_DBG_ALM_FULL                                                                            0x00084cUL //Access:RW   DataWidth:0x7    // Almost full for DBG SYNC FIFO.
+#define SEM_FAST_REG_SYNC_DRA_WR_ALM_FULL_E5                                                                 0x000850UL //Access:RW   DataWidth:0x3    // Almost full for DRA_WR SYNC FIFO.
+#define SEM_FAST_REG_FULL                                                                                    0x000940UL //Access:R    DataWidth:0x18   // Full data spelling :  {mux_rbc_vfc_fifo_empty, cam_rbc_inp_msb2_empty_sel, sync_rbc_dbg_empty[STORM_B], sync_rbc_dbg_empty[STORM_A], rd_rbc_fast_fin_empty[STORM_B], rd_rbc_fast_fin_empty[STORM_A], sync_wr_fast_pop_empty[STORM_B], sync_wr_fast_pop_empty[STORM_A], sync_misc_dra_rd_push_empty[STORM_B], sync_misc_dra_rd_push_empty[STORM_A], cam_rbc_inp_lsb_empty_sel, cam_rbc_inp_msb_empty_sel, cam_mux_empty[STORM_B], cam_mux_empty[STORM_A], sync_rbc_ram_rd_empty, sync_ram_fast_ext_empty, sync_rbc_ext_empty[STORM_B], sync_rbc_ext_empty[STORM_A]};
+#define SEM_FAST_REG_EMPTY                                                                                   0x000944UL //Access:R    DataWidth:0x18   // Empty data spelling; {mux_rbc_vfc_fifo_empty, cam_rbc_inp_msb2_empty_sel[STORM_B], cam_rbc_inp_msb2_empty_sel[STORM_A], sync_rbc_dbg_empty[STORM_B], sync_rbc_dbg_empty[STORM_A], rd_rbc_fast_fin_empty[STORM_B], rd_rbc_fast_fin_empty[STORM_A], sync_wr_fast_pop_empty[STORM_B], sync_wr_fast_pop_empty[STORM_A], sync_misc_dra_rd_push_empty[STORM_B], sync_misc_dra_rd_push_empty[STORM_A], cam_rbc_inp_lsb_empty_sel[STORM_B], cam_rbc_inp_lsb_empty_sel[STORM_A], cam_rbc_inp_msb_empty_sel[STORM_B], cam_rbc_inp_msb_empty_sel[STORM_A], cam_mux_empty[STORM_B], cam_mux_empty[STORM_A], sync_rbc_ram_rd_empty, sync_ram_fast_ext_empty, sync_rbc_ext_empty[STORM_B], sync_rbc_ext_empty[STORM_A]};
+#define SEM_FAST_REG_ALM_FULL                                                                                0x000948UL //Access:R    DataWidth:0x3    // Alm_full data spelling; {ram_alm_full,ext_alm_full[STORM_B],ext_alm_full[STORM_A]}.
+#define SEM_FAST_REG_ACTIVE_FILTER_ENABLE                                                                    0x000a40UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_CID_EN                                                (0x1<<0) // Used to enable CID/TID filter for Storm active statistics counter, when set.
+  #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_CID_EN_SHIFT                                          0
+  #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_EVNT_ID_EN                                            (0x1<<1) // Used to enable Event ID filter for Storm active statistics counter, when set.
+  #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_EVNT_ID_EN_SHIFT                                      1
+  #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_DRA_SRC                                               (0x3<<2) // Used to define the DRA-In source that should be compared for active statistics counter. A value of 0 indicates FIC0; a value of 1 indicates FIC1; a value of 2 indicates passive buffer.
+  #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_DRA_SRC_SHIFT                                         2
+  #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_DRA_SRC_EN                                            (0x1<<4) // Used to enable DRA source filter for Storm active statistics counter, when set.
+  #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_DRA_SRC_EN_SHIFT                                      4
+  #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_EVENT_ID_RANGE_EN                                     (0x1<<5) // Used to enable active statistics filtering based on a range of event IDs rather than "match" filtering. When set, the event ID range is defined by the EventIDRangeStrt and EventIDRangeEnd registers.
+  #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_EVENT_ID_RANGE_EN_SHIFT                               5
+#define SEM_FAST_REG_STORM_ACTIVE_CYCLES_A_E5                                                                0x000a44UL //Access:R    DataWidth:0x20   // Statistics - The accumulated number of Storm cycles in which the Storm has been active (not idle).
+#define SEM_FAST_REG_STORM_ACTIVE_CYCLES_BB_K2                                                               0x000a44UL //Access:RC   DataWidth:0x20   // Statistics - The accumulated number of Storm cycles in which the Storm has been active (not idle).
+#define SEM_FAST_REG_STALL_CYCLES_MASK                                                                       0x000a48UL //Access:RW   DataWidth:0x16   // Provides a vector for enabling/masking the various stall sources from contributing to the storm_stall_cycles statistics count.
+#define SEM_FAST_REG_STORM_STALL_CYCLES_A_E5                                                                 0x000a4cUL //Access:R    DataWidth:0x20   // Statistics - The accumulated number of Storm cycles in which the Storm has been stalled by the "stall" signal on the load/store bus for STORM A.
+#define SEM_FAST_REG_STORM_STALL_CYCLES_BB_K2                                                                0x000a4cUL //Access:RC   DataWidth:0x20   // Statistics - The accumulated number of Storm cycles in which the Storm has been stalled by the "stall" signal on the load/store bus.
+#define SEM_FAST_REG_IDLE_SLEEPING_CYCLES_A_E5                                                               0x000a50UL //Access:R    DataWidth:0x20   // Statistics - The accumulated number of Storm cycles in which the Storm has been idle due to having no threads to run and one or more threads with Affintiy A or X is in sleep state.
+#define SEM_FAST_REG_IDLE_SLEEPING_CYCLES_BB_K2                                                              0x000a50UL //Access:RC   DataWidth:0x20   // Statistics - The accumulated number of Storm cycles in which the Storm has been idle due to having no threads to run and one or more threads are allocated in the free-threads list, but are sleeping.
+#define SEM_FAST_REG_IDLE_INACTIVE_CYCLES_A_E5                                                               0x000a54UL //Access:R    DataWidth:0x20   // Statistics - The accumulated number of Storm cycles in which the Storm has been idle due to having no threads to run and no threads are allocated.
+#define SEM_FAST_REG_IDLE_INACTIVE_CYCLES_BB_K2                                                              0x000a54UL //Access:RC   DataWidth:0x20   // Statistics - The accumulated number of Storm cycles in which the Storm has been idle due to having no threads to run and no threads are allocated.
+#define SEM_FAST_REG_STORM_ACTIVE_CYCLES_B_E5                                                                0x000a58UL //Access:R    DataWidth:0x20   // Statistics - The accumulated number of Storm cycles in which the Storm has been active (not idle).
+#define SEM_FAST_REG_STORM_STALL_CYCLES_B_E5                                                                 0x000a5cUL //Access:R    DataWidth:0x20   // Statistics - The accumulated number of Storm cycles in which the Storm has been stalled by the "stall" signal on the load/store bus for STORM B.
+#define SEM_FAST_REG_IDLE_SLEEPING_CYCLES_B_E5                                                               0x000a60UL //Access:R    DataWidth:0x20   // Statistics - The accumulated number of Storm cycles in which the Storm has been idle due to having no threads to run and one or more threads with Affintiy B or X is in sleep state.
+#define SEM_FAST_REG_IDLE_INACTIVE_CYCLES_B_E5                                                               0x000a64UL //Access:R    DataWidth:0x20   // Statistics - The accumulated number of Storm cycles in which the Storm has been idle due to having no threads to run and no threads are allocated.
+#define SEM_FAST_REG_LOCK_MAX_CYCLE_STALL_E5                                                                 0x000a68UL //Access:RW   DataWidth:0xd    // This register defines the maximum cycles a Storm may be stalled by Lock block before interrupt assertion.
+#define SEM_FAST_REG_VFC_DATA_WR                                                                             0x000b40UL //Access:RW   DataWidth:0x20   // Command data for VFC. VFC will accumulate all writing to this register till will be done write to vfc_wr_addr.
+#define SEM_FAST_REG_VFC_ADDR                                                                                0x000b44UL //Access:RW   DataWidth:0xc    // Command address for VFC. Write to it should be done when all command data was already written to vfc_data_wr register.
+#define SEM_FAST_REG_VFC_DATA_RD                                                                             0x000b48UL //Access:R    DataWidth:0x20   // Read data from VFC.
+#define SEM_FAST_REG_VFC_STATUS                                                                              0x000b4cUL //Access:R    DataWidth:0x3    // B0 - response is ready. It is set when response cycle of 32 bit is ready from VFC block. It is reset when read is done from vfc_data_rd register; B1 - vfc is busy. It is set when was done write to vfc_addr register. It is reset when last from VFC was received. B2 - sending command is on going. It will be set when was done write to vfc_data_wr register. It will be reset when it was done write to vfc_addr register. New command may be sent from RBC when all 3 bits of this register is reset.
+#define SEM_FAST_REG_CAM_BIST_EN                                                                             0x000c40UL //Access:RW   DataWidth:0x1    // Used to enable/disable BIST mode. When set, BIST testing will be performed and the results will be posted upon completion. When cleared CAM access will be enabled through the CAM BIST mechanism instead.
+#define SEM_FAST_REG_CAM_BIST_SKIP_ERROR_CNT                                                                 0x000c44UL //Access:RW   DataWidth:0x8    // Provides a threshold for the number of CAM BIST errors that are acceptable before reporting CAM BIST failure status.
+#define SEM_FAST_REG_CAM_BIST_STATUS_SEL                                                                     0x000c48UL //Access:RW   DataWidth:0x8    // Used to select the BIST status word to read following the completion of a BIST test. Also used to select the data slice when writing data directly to the CAM using the CAM BIST mechanism.
+#define SEM_FAST_REG_CAM_BIST_STATUS                                                                         0x000c4cUL //Access:R    DataWidth:0x20   // Provides read-only access to the BIST status word selected by cam_bist_status_sel.
+#define SEM_FAST_REG_MEMCTRL_WR_RD_N_BB                                                                      0x000cc0UL //Access:RW   DataWidth:0x1    // wr/rd indication to CPU BIST
+#define SEM_FAST_REG_MEMCTRL_CMD_BB                                                                          0x000cc4UL //Access:RW   DataWidth:0x8    // command to CPU BIST
+#define SEM_FAST_REG_MEMCTRL_ADDRESS_BB                                                                      0x000cc8UL //Access:RW   DataWidth:0x8    // address to CPU BIST
+#define SEM_FAST_REG_MEMCTRL_STATUS_BB                                                                       0x000cccUL //Access:R    DataWidth:0x20   // status from CPU BIST
+#define SEM_FAST_REG_STORM_REG_FILE                                                                          0x008000UL //Access:R    DataWidth:0x20   // Register file memories. If address lsb=0=>read from bits 31:0; otherway from bits 63:32. Upper bit 9 selects the RF. Upper bit 10 selects the STORM. Used only for debugging.
+#define SEM_FAST_REG_STORM_REG_FILE_SIZE_BB_K2                                                               512
+#define SEM_FAST_REG_STORM_REG_FILE_SIZE_E5                                                                  1024
+#define SEM_FAST_REG_CAM_REQUEST                                                                             0x009000UL //Access:RW   DataWidth:0x4    // Writing this indirect register will cause a CAM command to be executed with the CAM offset specified by the indirect register sub-address. Bits [3:0] of the data bus provide the OpCode for the request where the following numerations apply: 0x0=ADD, 0x1=SRCH, 0x2=INVALIDATE, 0x3=READ. Reading this register returns the OpCode of the most recent RBC-initiated CAM request.
+#define SEM_FAST_REG_CAM_REQUEST_SIZE                                                                        256
+#define SEM_FAST_REG_VFC_CONFIG                                                                              0x00a000UL //Access:RW   DataWidth:0x20   // Provides a memory-mapped region for VFC configurations; up to 256 registers.
+#define SEM_FAST_REG_VFC_CONFIG_SIZE                                                                         256
+#define SEM_FAST_REG_LOCKS_KEY_E5                                                                            0x00b000UL //Access:RW   DataWidth:0x20   // Provides a WR/RD access for Locks key and state (Acquired/Reliquished). If lsb bit of addr = 0  => write to lock ID of addr[3:1] LOCK_VAL[31:0] if lsb bit of addr = 1  => write to lock ID of addr[3:1] {LOCK_VALID,STORM_ID,LOCK_VAL[39:32]}
+#define SEM_FAST_REG_LOCKS_KEY_SIZE                                                                          16
+#define SEM_FAST_REG_LOCKS_CNT_E5                                                                            0x00b080UL //Access:RW   DataWidth:0x20   // Provides a Wr/Rd access for Locks counters.
+#define SEM_FAST_REG_LOCKS_CNT_SIZE                                                                          32
+#define SEM_FAST_REG_LOCKS_MON_E5                                                                            0x00b200UL //Access:RW   DataWidth:0x20   // Provides a RD access for all monitor block, {CNT_VAL,CNT_ID,SET}.
+#define SEM_FAST_REG_LOCKS_MON_SIZE                                                                          128
+#define SEM_FAST_REG_INT_RAM                                                                                 0x020000UL //Access:RW   DataWidth:0x20   // Internal RAM (if bit lsb of addr =0 => write to bits[31:0; otherwise to [63:32).
+#define SEM_FAST_REG_INT_RAM_SIZE                                                                            20480
+#define VFC_REG_MASK_LSB_0_LOW                                                                               0x000000UL //Access:RW   DataWidth:0x20   // Bits [31:0] for vector CAM mask that are used for search and add commands. 1 means the corresponding data bit should be compared and 0 means it should be ignored.
+#define VFC_REG_MASK_LSB_0_HIGH                                                                              0x000004UL //Access:RW   DataWidth:0x20   // Bits [63:32] for vector CAM mask that are used for search and add commands. 1 means the corresponding data bit should be compared and 0 means it should be ignored.
+#define VFC_REG_MASK_LSB_1_LOW                                                                               0x000008UL //Access:RW   DataWidth:0x20   // Bits [31:0] for vector CAM mask that are used for search and add commands. 1 means the corresponding data bit should be compared and 0 means it should be ignored.
+#define VFC_REG_MASK_LSB_1_HIGH                                                                              0x00000cUL //Access:RW   DataWidth:0x20   // Bits [63:32] for vector CAM mask that are used for search and add commands. 1 means the corresponding data bit should be compared and 0 means it should be ignored.
+#define VFC_REG_MASK_LSB_2_LOW                                                                               0x000010UL //Access:RW   DataWidth:0x20   // Bits [31:0] for vector CAM mask that are used for search and add commands.1 means the corresponding data bit should be compared and 0 means it should be ignored.
+#define VFC_REG_MASK_LSB_2_HIGH                                                                              0x000014UL //Access:RW   DataWidth:0x20   // Bits [31:0] for vector CAM mask that are used for search and add commands. 1 means the corresponding data bit should be compared and 0 means it should be ignored.
+#define VFC_REG_MASK_LSB_3_LOW                                                                               0x000018UL //Access:RW   DataWidth:0x20   // Bits [111:96] bits for vector CAM mask that are used for search and add commands.1 means the corresponding data bit should be compared and 0 means it should be ignored.
+#define VFC_REG_MASK_LSB_3_HIGH                                                                              0x00001cUL //Access:RW   DataWidth:0x20   // Bits [63:32]  for vector CAM mask that are used for search and add commands. 1 means the corresponding data bit should be compared and 0 means it should be ignored.
+#define VFC_REG_ALU_RST_EN                                                                                   0x000020UL //Access:RW   DataWidth:0x8    // This register includes bit per ALU vector: 0-4 long vectors; 5-11 short vectors. When it is set then appropriate vector will be reset when RST bit is set in request.
+#define VFC_REG_TT_RESULT_EN                                                                                 0x000024UL //Access:RW   DataWidth:0x1    // This register defines value that will be written to DSt vector for analyze operation. If it is set to 1, then row from target table will be rwitten. If it is set to 0, then row from target table OR previous value of DST vector will be written.
+#define VFC_REG_INTERRUPT_IND                                                                                0x000028UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define VFC_REG_INTERRUPT_IND_ADDRESS_INTERRUPT                                                            (0x1<<0) // This is error interrupt. It may be asserted when it was access to not existing address in VFC. Also it will be asserted when there is attempt to write to read only register. It will be de-asserted aftre write 1 to it.
+  #define VFC_REG_INTERRUPT_IND_ADDRESS_INTERRUPT_SHIFT                                                      0
+  #define VFC_REG_INTERRUPT_IND_INP_FIFO_ITERRUPT                                                            (0x1<<1) // This is error interrupt. It may be asserted when it was input FIFO overflow.
+  #define VFC_REG_INTERRUPT_IND_INP_FIFO_ITERRUPT_SHIFT                                                      1
+  #define VFC_REG_INTERRUPT_IND_LEN_FIFO_INTERRUPT                                                           (0x1<<2) // This is error interrupt. It may be asserted when it was length FIFO overflow.
+  #define VFC_REG_INTERRUPT_IND_LEN_FIFO_INTERRUPT_SHIFT                                                     2
+  #define VFC_REG_INTERRUPT_IND_INP_BUF_INTERRUPT                                                            (0x1<<3) // This is error interrupt. It may be asserted when it was input buffers overflow.
+  #define VFC_REG_INTERRUPT_IND_INP_BUF_INTERRUPT_SHIFT                                                      3
+  #define VFC_REG_INTERRUPT_IND_OUT_BUF_INTERRUPT                                                            (0x1<<4) // This is error interrupt. It may be asserted when it was output buffer overflow.
+  #define VFC_REG_INTERRUPT_IND_OUT_BUF_INTERRUPT_SHIFT                                                      4
+  #define VFC_REG_INTERRUPT_IND_RBC_WRITE_INTERRUPT                                                          (0x1<<8) // This is error interrupt. It may be asserted when it was RBC command with address not equal to 12 bit or data cycle not equal 64 bit or number of data cycles bigger than 6.  It will be de-asserted aftre write 1 to it.
+  #define VFC_REG_INTERRUPT_IND_RBC_WRITE_INTERRUPT_SHIFT                                                    8
+  #define VFC_REG_INTERRUPT_IND_DEADLOCK_INTERRUPT                                                           (0x1<<9) // This is error interrupt. It may be asserted when waitp is asserted and output FIFO is also full.  It will be de-asserted aftre write 1 to it.
+  #define VFC_REG_INTERRUPT_IND_DEADLOCK_INTERRUPT_SHIFT                                                     9
+  #define VFC_REG_INTERRUPT_IND_RSS_INFO_INTERRUPT_BB_K2                                                     (0x1<<5) // This is error interrupt. It may be asserted when it was address overflow of INFO part of RSS RAM. It will be de-asserted aftre write 1 to it.
+  #define VFC_REG_INTERRUPT_IND_RSS_INFO_INTERRUPT_BB_K2_SHIFT                                               5
+  #define VFC_REG_INTERRUPT_IND_RSS_KEY_LSB_INTERRUPT_BB_K2                                                  (0x1<<6) // This is error interrupt. It may be asserted when it was address overflow of KEY LSB part of RSS RAM.   It will be de-asserted aftre write 1 to it.
+  #define VFC_REG_INTERRUPT_IND_RSS_KEY_LSB_INTERRUPT_BB_K2_SHIFT                                            6
+  #define VFC_REG_INTERRUPT_IND_RSS_KEY_MSB_INTERRUPT_BB_K2                                                  (0x1<<7) // This is error interrupt. It may be asserted when it was address overflow of KEY MSB part of RSS RAM. It will be de-asserted aftre write 1 to it.
+  #define VFC_REG_INTERRUPT_IND_RSS_KEY_MSB_INTERRUPT_BB_K2_SHIFT                                            7
+#define VFC_REG_PARITY_IND                                                                                   0x00002cUL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define VFC_REG_PARITY_IND_CAM_PARITY                                                                      (0x1<<1) // This is parity interrupt. It may be asserted when it was CAM parity error. It will be de-asserted aftre write 1 to it.
+  #define VFC_REG_PARITY_IND_CAM_PARITY_SHIFT                                                                1
+  #define VFC_REG_PARITY_IND_TT_RAM_PARITY                                                                   (0x1<<2) // This is parity interrupt. It may be asserted when it was parity error inside TT RAM. It will be de-asserted aftre write 1 to it.
+  #define VFC_REG_PARITY_IND_TT_RAM_PARITY_SHIFT                                                             2
+  #define VFC_REG_PARITY_IND_RSS_RAM_PARITY_BB_K2                                                            (0x1<<0) // This is parity interrupt. It may be asserted when it was RSS RAM parity error.  It will be de-asserted aftre write 1 to it.
+  #define VFC_REG_PARITY_IND_RSS_RAM_PARITY_BB_K2_SHIFT                                                      0
+#define VFC_REG_INDICATIONS1                                                                                 0x000030UL //Access:R    DataWidth:0x12   // Multi Field Register.
+  #define VFC_REG_INDICATIONS1_INP_FIFO_EMPTY                                                                (0x1<<0) // Empty indication from input FIFO.
+  #define VFC_REG_INDICATIONS1_INP_FIFO_EMPTY_SHIFT                                                          0
+  #define VFC_REG_INDICATIONS1_LEN_FIFO_EMPTY                                                                (0x1<<1) // Empty indication from length command FIFO.
+  #define VFC_REG_INDICATIONS1_LEN_FIFO_EMPTY_SHIFT                                                          1
+  #define VFC_REG_INDICATIONS1_INP_BUF_EMPTY                                                                 (0x1<<2) // Empty indication from input buffers.
+  #define VFC_REG_INDICATIONS1_INP_BUF_EMPTY_SHIFT                                                           2
+  #define VFC_REG_INDICATIONS1_OUT_FIFO_EMPTY                                                                (0x1<<3) // Empty indication from output FIFO.
+  #define VFC_REG_INDICATIONS1_OUT_FIFO_EMPTY_SHIFT                                                          3
+  #define VFC_REG_INDICATIONS1_SEM_FIFO_EMPTY                                                                (0x1<<4) // Empty indication from SEM output FIFO inside VFC.
+  #define VFC_REG_INDICATIONS1_SEM_FIFO_EMPTY_SHIFT                                                          4
+  #define VFC_REG_INDICATIONS1_RESERVED1_1                                                                   (0x7<<5) // Reserved bits.
+  #define VFC_REG_INDICATIONS1_RESERVED1_1_SHIFT                                                             5
+  #define VFC_REG_INDICATIONS1_INP_FIFO_FULL                                                                 (0x1<<8) // Full indication from input FIFO.
+  #define VFC_REG_INDICATIONS1_INP_FIFO_FULL_SHIFT                                                           8
+  #define VFC_REG_INDICATIONS1_LEN_FIFO_FULL                                                                 (0x1<<9) // Full indication from length command FIFO.
+  #define VFC_REG_INDICATIONS1_LEN_FIFO_FULL_SHIFT                                                           9
+  #define VFC_REG_INDICATIONS1_INP_BUF_FULL                                                                  (0x1<<10) // Full indication from input buffers.
+  #define VFC_REG_INDICATIONS1_INP_BUF_FULL_SHIFT                                                            10
+  #define VFC_REG_INDICATIONS1_OUT_FIFO_FULL                                                                 (0x1<<11) // Full indication from output FIFO.
+  #define VFC_REG_INDICATIONS1_OUT_FIFO_FULL_SHIFT                                                           11
+  #define VFC_REG_INDICATIONS1_SEM_FIFO_FULL                                                                 (0x1<<12) // Full indication from SEM output FIFO inside VFC.
+  #define VFC_REG_INDICATIONS1_SEM_FIFO_FULL_SHIFT                                                           12
+  #define VFC_REG_INDICATIONS1_RESERVED1_2                                                                   (0x7<<13) // Reserved bits.
+  #define VFC_REG_INDICATIONS1_RESERVED1_2_SHIFT                                                             13
+  #define VFC_REG_INDICATIONS1_RBC_RSP_RDY                                                                   (0x1<<16) // Indicates if RBC response is ready.
+  #define VFC_REG_INDICATIONS1_RBC_RSP_RDY_SHIFT                                                             16
+  #define VFC_REG_INDICATIONS1_VFC_WAITP                                                                     (0x1<<17) // Indicates if waitp from VFC to STORM is asserted.
+  #define VFC_REG_INDICATIONS1_VFC_WAITP_SHIFT                                                               17
+#define VFC_REG_INDICATIONS2                                                                                 0x000034UL //Access:R    DataWidth:0x1c   // Multi Field Register.
+  #define VFC_REG_INDICATIONS2_INP_FIFO_CNT                                                                  (0x1f<<0) // Number of entries inside input memory FIFO.
+  #define VFC_REG_INDICATIONS2_INP_FIFO_CNT_SHIFT                                                            0
+  #define VFC_REG_INDICATIONS2_RESERVED2_1                                                                   (0x7<<5) // Reserved bits.
+  #define VFC_REG_INDICATIONS2_RESERVED2_1_SHIFT                                                             5
+  #define VFC_REG_INDICATIONS2_LEN_FIFO_CNT                                                                  (0x1f<<8) // Number of entries inside length command FIFO.
+  #define VFC_REG_INDICATIONS2_LEN_FIFO_CNT_SHIFT                                                            8
+  #define VFC_REG_INDICATIONS2_RESERVED2_2                                                                   (0x7<<13) // Reserved bits.
+  #define VFC_REG_INDICATIONS2_RESERVED2_2_SHIFT                                                             13
+  #define VFC_REG_INDICATIONS2_INP_BUF_CNT                                                                   (0xf<<16) // Number of entries inside buffers of input FIFO.
+  #define VFC_REG_INDICATIONS2_INP_BUF_CNT_SHIFT                                                             16
+  #define VFC_REG_INDICATIONS2_OUT_BUF_CNT                                                                   (0xf<<20) // Number of entries inside output FIFO.
+  #define VFC_REG_INDICATIONS2_OUT_BUF_CNT_SHIFT                                                             20
+  #define VFC_REG_INDICATIONS2_SEM_FIFO_CNT                                                                  (0xf<<24) // Number of entries inside SEMI output FIFO inside VFC.
+  #define VFC_REG_INDICATIONS2_SEM_FIFO_CNT_SHIFT                                                            24
+#define VFC_REG_SW_RST                                                                                       0x000038UL //Access:W    DataWidth:0x1    // Write to this bit will cause to block reset.
+#define VFC_REG_MEMORIES_RST                                                                                 0x00003cUL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define VFC_REG_MEMORIES_RST_CAM_RST                                                                       (0x1<<0) // Write 1 to this bit will cause reset of all CAM rows including valid bit and all bits in a row. Write 0 to it will have no effect. Read 1 from this bit means that CAM reset was finished. Read 0 from this bit means that CAM reset was never done or not finished.
+  #define VFC_REG_MEMORIES_RST_CAM_RST_SHIFT                                                                 0
+  #define VFC_REG_MEMORIES_RST_TT_RST                                                                        (0x1<<2) // Write 1 to this bit will cause reset of all Target tables rows. Write 0 to it will have no effect. Read 1 from this bit means that RAM reset was finished. Read 1 from this bit means that TT RAM reset is in progress. Read 0 from this bit means that TT RAM reset was finished.
+  #define VFC_REG_MEMORIES_RST_TT_RST_SHIFT                                                                  2
+  #define VFC_REG_MEMORIES_RST_RAM_RST_BB_K2                                                                 (0x1<<1) // Write 1 to this bit will cause reset of all RSS RAM rows. Write 0 to it will have no effect. Read 1 from this bit means that RAM reset is in progress. Read 0 from this bit means that RAM reset was finished.
+  #define VFC_REG_MEMORIES_RST_RAM_RST_BB_K2_SHIFT                                                           1
+#define VFC_REG_CAM_PARITY_EN                                                                                0x000040UL //Access:RW   DataWidth:0x1    // REQUIRED -If this bit is set then background mechanism for parity check will be enabled; 0 - disabled. This bit must be disabled in palladium and FPGA. Init value of 1 must be done in a chip mode
+#define VFC_REG_CAM_CLK_DIVIDER                                                                              0x000044UL //Access:RW   DataWidth:0x4    // Cam clock divider : may be equal to 2 only.
+#define VFC_REG_PARITY_MASK                                                                                  0x000048UL //Access:RW   DataWidth:0x3    // REQUIRED - 0 - parity is enabled;1 parity check is disabled.
+#define VFC_REG_INTERRUPT_MASK                                                                               0x00004cUL //Access:RW   DataWidth:0xa    // REQUIRED - 0 - interrupt is enabled;1- interrupt check is disabled.
+#define VFC_REG_RSS_RAM_TM_0_BB_K2                                                                           0x000050UL //Access:RW   DataWidth:0x5    // TM indication for RSS RAM instance 0.
+#define VFC_REG_RSS_RAM_TM_1_BB_K2                                                                           0x000054UL //Access:RW   DataWidth:0x5    // TM indication for RSS RAM instance 1.
+#define VFC_REG_INP_FIFO_TM                                                                                  0x000058UL //Access:RW   DataWidth:0x2    // TM indication for Input fifo.
+#define VFC_REG_CAM_TM                                                                                       0x00005cUL //Access:RW   DataWidth:0x14   // TM indication for CAM.
+#define VFC_REG_VFC_CAM_BIST_EN                                                                              0x000060UL //Access:RW   DataWidth:0x1    // Bist enable bit for Cam.
+#define VFC_REG_VFC_CAM_BIST_DBG_SEL                                                                         0x000064UL //Access:RW   DataWidth:0x8    // This select the type of data present on bist_status bus (slixe or status select).
+#define VFC_REG_VFC_CAM_BIST_STATUS                                                                          0x000068UL //Access:R    DataWidth:0x20   // This returns the bist_status which can be done/go/sX_status.
+#define VFC_REG_KEY_RSS_EXT5_BB_K2                                                                           0x00006cUL //Access:RW   DataWidth:0x8    // Key extension for 5th tuple.
+#define VFC_REG_INP_FIFO_ALM_FULL                                                                            0x000070UL //Access:RW   DataWidth:0x5    // Almost full for input FIFO. When number of entries inside input FIFO is bigger or equal to this number then waitp to STORM will be asserted.
+#define VFC_REG_STORM_CMD_DISABLE                                                                            0x000074UL //Access:RW   DataWidth:0x1    // When set then it disables selecting of commands from STORM. It will allow for RBC to configurate block. STORM command may be executed when this bit will be deasserted.
+#define VFC_REG_WAITP_STAT                                                                                   0x000078UL //Access:RC   DataWidth:0x20   // Statistics for number of cycles when waitp was raised to STORM as a result of full input FIFO. This vector will be reset after reading from it. It is also possible to write to it.
+#define VFC_REG_ECO_RESERVED                                                                                 0x00007cUL //Access:RW   DataWidth:0x20   // Unused bits for future eco.
+#define VFC_REG_CPU_MBIST_MEMCTRL_0_CNTRL_CMD                                                                0x000080UL //Access:RW   DataWidth:0x5    // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.
+#define VFC_REG_CPU_MBIST_MEMCTRL_1_CNTRL_CMD                                                                0x000084UL //Access:RW   DataWidth:0x5    // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.
+#define VFC_REG_DEBUG_DATA                                                                                   0x000090UL //Access:R    DataWidth:0x1e   // Multi Field Register.
+  #define VFC_REG_DEBUG_DATA_CURRENT_MSG_LEN                                                                 (0x7<<0) // Length of VFC command from STORM that is waitinf for arbitration.
+  #define VFC_REG_DEBUG_DATA_CURRENT_MSG_LEN_SHIFT                                                           0
+  #define VFC_REG_DEBUG_DATA_CUR_MSG_EMPTY                                                                   (0x1<<3) // Empty indication for current message that has first cycle from STORM.
+  #define VFC_REG_DEBUG_DATA_CUR_MSG_EMPTY_SHIFT                                                             3
+  #define VFC_REG_DEBUG_DATA_MEXT_MSG_LEN                                                                    (0x7<<4) // Length of next VFC command from STORM that will be selected after current message.
+  #define VFC_REG_DEBUG_DATA_MEXT_MSG_LEN_SHIFT                                                              4
+  #define VFC_REG_DEBUG_DATA_NEXT_MSG_EMPTY                                                                  (0x1<<7) // Next message ready indication that has first cycle fro mSTORM.
+  #define VFC_REG_DEBUG_DATA_NEXT_MSG_EMPTY_SHIFT                                                            7
+  #define VFC_REG_DEBUG_DATA_RBC_CNT                                                                         (0xff<<8) // Number of transactions from SEM_PD for last RBC command.
+  #define VFC_REG_DEBUG_DATA_RBC_CNT_SHIFT                                                                   8
+  #define VFC_REG_DEBUG_DATA_STORM_READY                                                                     (0x1<<16) // Ready indication from STORM to input arbiter.
+  #define VFC_REG_DEBUG_DATA_STORM_READY_SHIFT                                                               16
+  #define VFC_REG_DEBUG_DATA_RBC_READY                                                                       (0x1<<17) // Ready indication from RBC to input arbiter.
+  #define VFC_REG_DEBUG_DATA_RBC_READY_SHIFT                                                                 17
+  #define VFC_REG_DEBUG_DATA_RESERVED2                                                                       (0x3<<18) // This field is set to 0.
+  #define VFC_REG_DEBUG_DATA_RESERVED2_SHIFT                                                                 18
+  #define VFC_REG_DEBUG_DATA_LAST_MATCH_ADDR                                                                 (0x3ff<<20) // Last match address that will be used for analyze operation.
+  #define VFC_REG_DEBUG_DATA_LAST_MATCH_ADDR_SHIFT                                                           20
+#define VFC_REG_STORM_CMD_ADDR                                                                               0x000094UL //Access:R    DataWidth:0xc    // Address of command from STORM that is waiting for arbitration.
+#define VFC_REG_STORM_CMD_DATA_0                                                                             0x000098UL //Access:R    DataWidth:0x20   // Data bits[31:0] of VFC command from STORM that are waiting for arbitration.
+#define VFC_REG_STORM_CMD_DATA_1                                                                             0x00009cUL //Access:R    DataWidth:0x20   // Data bits[63:32] of VFC command from STORM that are waiting for arbitration.
+#define VFC_REG_STORM_CMD_DATA_2                                                                             0x0000a0UL //Access:R    DataWidth:0x20   // Data bits[95:64] of VFC command from STORM that are waiting for arbitration.
+#define VFC_REG_STORM_CMD_DATA_3                                                                             0x0000a4UL //Access:R    DataWidth:0x20   // Data bits[127:96] of VFC command from STORM that are waiting for arbitration.
+#define VFC_REG_STORM_CMD_DATA_4                                                                             0x0000a8UL //Access:R    DataWidth:0x20   // Data bits[159:128] of VFC command from STORM that are waiting for arbitration.
+#define VFC_REG_STORM_CMD_DATA_5                                                                             0x0000acUL //Access:R    DataWidth:0x20   // Data bits[191:160] of VFC command from STORM that are waiting for arbitration.
+#define VFC_REG_STORM_CMD_DATA_6                                                                             0x0000b0UL //Access:R    DataWidth:0x20   // Data bits[223:192] of VFC command from STORM that are waiting for arbitration.
+#define VFC_REG_STORM_CMD_DATA_7                                                                             0x0000b4UL //Access:R    DataWidth:0x20   // Data bits[255:224] of VFC command from STORM that are waiting for arbitration.
+#define VFC_REG_MASK_LSB_4_LOW                                                                               0x0000b8UL //Access:RW   DataWidth:0x20   // Bits [31:0] of data for search optimized operation that will be used when M field equals to 0.
+#define VFC_REG_MASK_LSB_4_HIGH                                                                              0x0000bcUL //Access:RW   DataWidth:0x20   // Bits [63:32] of data for search optimized operation that will be used when M field equals to 0.
+#define VFC_REG_MASK_LSB_5_LOW                                                                               0x0000c0UL //Access:RW   DataWidth:0x20   // Bits [31:0] of data for search optimized operation that will be used when M field equals to 0.
+#define VFC_REG_MASK_LSB_5_HIGH                                                                              0x0000c4UL //Access:RW   DataWidth:0x20   // Bits [63:32] of data for search optimized operation that will be used when M field equals to 0.
+#define VFC_REG_MASK_LSB_6_LOW                                                                               0x0000c8UL //Access:RW   DataWidth:0x20   // Bits [31:0] of data for search optimized operation that will be used when M field equals to 0.
+#define VFC_REG_MASK_LSB_6_HIGH                                                                              0x0000ccUL //Access:RW   DataWidth:0x20   // Bits [63:32] of data for search optimized operation that will be used when M field equals to 0.
+#define VFC_REG_MASK_LSB_7_LOW                                                                               0x0000d0UL //Access:RW   DataWidth:0x20   // Bits [31:0] of data for search optimized operation that will be used when M field equals to 0.
+#define VFC_REG_MASK_LSB_7_HIGH                                                                              0x0000d4UL //Access:RW   DataWidth:0x20   // Bits [63:32] of data for search optimized operation that will be used when M field equals to 0.
+#define VFC_REG_OFFSET_ALU_VECTOR_0                                                                          0x0000f8UL //Access:R    DataWidth:0x9    // Last analyze offset for ALU vector 0.
+#define VFC_REG_OFFSET_ALU_VECTOR_1                                                                          0x0000fcUL //Access:R    DataWidth:0x9    // Last analyze offset for ALU vector 1.
+#define VFC_REG_OFFSET_ALU_VECTOR_2                                                                          0x000100UL //Access:R    DataWidth:0x9    // Last analyze offset for ALU vector 2.
+#define VFC_REG_OFFSET_ALU_VECTOR_3                                                                          0x000104UL //Access:R    DataWidth:0x9    // Last analyze offset for ALU vector 3.
+#define VFC_REG_OFFSET_ALU_VECTOR_4                                                                          0x000108UL //Access:R    DataWidth:0x9    // Last analyze offset for ALU vector 4.
+#define VFC_REG_OFFSET_ALU_VECTOR_5                                                                          0x00010cUL //Access:R    DataWidth:0x9    // Last analyze offset for ALU vector 5.
+#define VFC_REG_OFFSET_ALU_VECTOR_6                                                                          0x000110UL //Access:R    DataWidth:0x9    // Last analyze offset for ALU vector 6.
+#define VFC_REG_OFFSET_ALU_VECTOR_7                                                                          0x000114UL //Access:R    DataWidth:0x9    // Last analyze offset for ALU vector 7.
+#define VFC_REG_PORT4_MODE_EN                                                                                0x000118UL //Access:RW   DataWidth:0x1    // If this bit set to 0 then allows to work with 160 clients. If set to 1 then with 208.
+#define VFC_REG_INP_FIFO_DBG_RD_EN                                                                           0x00011cUL //Access:RW   DataWidth:0x1    // Input FIFO debug enable.
+#define VFC_REG_INP_FIFO_DBG_RD_ADD                                                                          0x000120UL //Access:RW   DataWidth:0x4    // Input FIFO debug address.
+#define VFC_REG_CAM_BIST_SKIP_ERROR_CNT                                                                      0x000124UL //Access:RW   DataWidth:0x8    // Provides a threshold for the number of CAM BIST errors that are acceptable before reporting CAM BIST failure status.
+#define VFC_REG_PRTY_MASK_H_0_BB_K2                                                                          0x000204UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define VFC_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_BB_K2                                                    (0x1<<0) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT .
+  #define VFC_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_BB_K2_SHIFT                                              0
+  #define VFC_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_BB_K2                                                    (0x1<<1) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT .
+  #define VFC_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_BB_K2_SHIFT                                              1
+  #define VFC_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2                                                         (0x1<<2) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define VFC_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_SHIFT                                                   2
+  #define VFC_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                      (0x1<<3) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define VFC_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                                3
+  #define VFC_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                      (0x1<<4) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define VFC_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                                4
+  #define VFC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                      (0x1<<5) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define VFC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                                5
+  #define VFC_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB                                                         (0x1<<2) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define VFC_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_SHIFT                                                   2
+#define VFC_REG_MEM_ECC_ENABLE_0_BB_K2                                                                       0x000210UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define VFC_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_BB_K2                                                     (0x1<<0) // Enable ECC for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_tt1_ram.i_ecc in module vfc_mem_tt1_4port
+  #define VFC_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_BB_K2_SHIFT                                               0
+  #define VFC_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN_BB_K2                                                     (0x1<<1) // Enable ECC for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_mtt2_ram.i_ecc in module vfc_mem_mtt2_4port
+  #define VFC_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN_BB_K2_SHIFT                                               1
+#define VFC_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                  0x000214UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define VFC_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_BB_K2                                              (0x1<<0) // Set parity only for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_tt1_ram.i_ecc in module vfc_mem_tt1_4port
+  #define VFC_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_BB_K2_SHIFT                                        0
+  #define VFC_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY_BB_K2                                              (0x1<<1) // Set parity only for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_mtt2_ram.i_ecc in module vfc_mem_mtt2_4port
+  #define VFC_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY_BB_K2_SHIFT                                        1
+#define VFC_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                              0x000218UL //Access:RC   DataWidth:0x2    // Multi Field Register.
+  #define VFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_BB_K2                                       (0x1<<0) // Record if a correctable error occurred on memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_tt1_ram.i_ecc in module vfc_mem_tt1_4port
+  #define VFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_BB_K2_SHIFT                                 0
+  #define VFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT_BB_K2                                       (0x1<<1) // Record if a correctable error occurred on memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_mtt2_ram.i_ecc in module vfc_mem_mtt2_4port
+  #define VFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT_BB_K2_SHIFT                                 1
+#define VFC_REG_MEM_ECC_EVENTS_BB_K2                                                                         0x00021cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define PB_REG_INT_STS                                                                                       0x000040UL //Access:R    DataWidth:0x9    // Multi Field Register.
+  #define PB_REG_INT_STS_ADDRESS_ERROR                                                                       (0x1<<0) // Signals an unknown address to the rf module.
+  #define PB_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                                 0
+  #define PB_REG_INT_STS_EOP_ERROR                                                                           (0x1<<1) // EOP check error.
+  #define PB_REG_INT_STS_EOP_ERROR_SHIFT                                                                     1
+  #define PB_REG_INT_STS_IFIFO_ERROR                                                                         (0x1<<2) // Instruction FIFO error.
+  #define PB_REG_INT_STS_IFIFO_ERROR_SHIFT                                                                   2
+  #define PB_REG_INT_STS_PFIFO_ERROR                                                                         (0x1<<3) // Parameter FIFO error.
+  #define PB_REG_INT_STS_PFIFO_ERROR_SHIFT                                                                   3
+  #define PB_REG_INT_STS_DB_BUF_ERROR                                                                        (0x1<<4) // DB FIFO error.
+  #define PB_REG_INT_STS_DB_BUF_ERROR_SHIFT                                                                  4
+  #define PB_REG_INT_STS_TH_EXEC_ERROR                                                                       (0x1<<5) // 
+  #define PB_REG_INT_STS_TH_EXEC_ERROR_SHIFT                                                                 5
+  #define PB_REG_INT_STS_TQ_ERROR_WR                                                                         (0x1<<6) // TQ write overflow.
+  #define PB_REG_INT_STS_TQ_ERROR_WR_SHIFT                                                                   6
+  #define PB_REG_INT_STS_TQ_ERROR_RD_TH                                                                      (0x1<<7) // TQ read underflow by task handler.
+  #define PB_REG_INT_STS_TQ_ERROR_RD_TH_SHIFT                                                                7
+  #define PB_REG_INT_STS_TQ_ERROR_RD_IH                                                                      (0x1<<8) // TQ read underflow by instruction handler.
+  #define PB_REG_INT_STS_TQ_ERROR_RD_IH_SHIFT                                                                8
+#define PB_REG_INT_MASK                                                                                      0x000044UL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define PB_REG_INT_MASK_ADDRESS_ERROR                                                                      (0x1<<0) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.ADDRESS_ERROR .
+  #define PB_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                                0
+  #define PB_REG_INT_MASK_EOP_ERROR                                                                          (0x1<<1) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.EOP_ERROR .
+  #define PB_REG_INT_MASK_EOP_ERROR_SHIFT                                                                    1
+  #define PB_REG_INT_MASK_IFIFO_ERROR                                                                        (0x1<<2) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.IFIFO_ERROR .
+  #define PB_REG_INT_MASK_IFIFO_ERROR_SHIFT                                                                  2
+  #define PB_REG_INT_MASK_PFIFO_ERROR                                                                        (0x1<<3) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.PFIFO_ERROR .
+  #define PB_REG_INT_MASK_PFIFO_ERROR_SHIFT                                                                  3
+  #define PB_REG_INT_MASK_DB_BUF_ERROR                                                                       (0x1<<4) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.DB_BUF_ERROR .
+  #define PB_REG_INT_MASK_DB_BUF_ERROR_SHIFT                                                                 4
+  #define PB_REG_INT_MASK_TH_EXEC_ERROR                                                                      (0x1<<5) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TH_EXEC_ERROR .
+  #define PB_REG_INT_MASK_TH_EXEC_ERROR_SHIFT                                                                5
+  #define PB_REG_INT_MASK_TQ_ERROR_WR                                                                        (0x1<<6) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_WR .
+  #define PB_REG_INT_MASK_TQ_ERROR_WR_SHIFT                                                                  6
+  #define PB_REG_INT_MASK_TQ_ERROR_RD_TH                                                                     (0x1<<7) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_RD_TH .
+  #define PB_REG_INT_MASK_TQ_ERROR_RD_TH_SHIFT                                                               7
+  #define PB_REG_INT_MASK_TQ_ERROR_RD_IH                                                                     (0x1<<8) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_RD_IH .
+  #define PB_REG_INT_MASK_TQ_ERROR_RD_IH_SHIFT                                                               8
+#define PB_REG_INT_STS_WR                                                                                    0x000048UL //Access:WR   DataWidth:0x9    // Multi Field Register.
+  #define PB_REG_INT_STS_WR_ADDRESS_ERROR                                                                    (0x1<<0) // Signals an unknown address to the rf module.
+  #define PB_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                              0
+  #define PB_REG_INT_STS_WR_EOP_ERROR                                                                        (0x1<<1) // EOP check error.
+  #define PB_REG_INT_STS_WR_EOP_ERROR_SHIFT                                                                  1
+  #define PB_REG_INT_STS_WR_IFIFO_ERROR                                                                      (0x1<<2) // Instruction FIFO error.
+  #define PB_REG_INT_STS_WR_IFIFO_ERROR_SHIFT                                                                2
+  #define PB_REG_INT_STS_WR_PFIFO_ERROR                                                                      (0x1<<3) // Parameter FIFO error.
+  #define PB_REG_INT_STS_WR_PFIFO_ERROR_SHIFT                                                                3
+  #define PB_REG_INT_STS_WR_DB_BUF_ERROR                                                                     (0x1<<4) // DB FIFO error.
+  #define PB_REG_INT_STS_WR_DB_BUF_ERROR_SHIFT                                                               4
+  #define PB_REG_INT_STS_WR_TH_EXEC_ERROR                                                                    (0x1<<5) // 
+  #define PB_REG_INT_STS_WR_TH_EXEC_ERROR_SHIFT                                                              5
+  #define PB_REG_INT_STS_WR_TQ_ERROR_WR                                                                      (0x1<<6) // TQ write overflow.
+  #define PB_REG_INT_STS_WR_TQ_ERROR_WR_SHIFT                                                                6
+  #define PB_REG_INT_STS_WR_TQ_ERROR_RD_TH                                                                   (0x1<<7) // TQ read underflow by task handler.
+  #define PB_REG_INT_STS_WR_TQ_ERROR_RD_TH_SHIFT                                                             7
+  #define PB_REG_INT_STS_WR_TQ_ERROR_RD_IH                                                                   (0x1<<8) // TQ read underflow by instruction handler.
+  #define PB_REG_INT_STS_WR_TQ_ERROR_RD_IH_SHIFT                                                             8
+#define PB_REG_INT_STS_CLR                                                                                   0x00004cUL //Access:RC   DataWidth:0x9    // Multi Field Register.
+  #define PB_REG_INT_STS_CLR_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define PB_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                             0
+  #define PB_REG_INT_STS_CLR_EOP_ERROR                                                                       (0x1<<1) // EOP check error.
+  #define PB_REG_INT_STS_CLR_EOP_ERROR_SHIFT                                                                 1
+  #define PB_REG_INT_STS_CLR_IFIFO_ERROR                                                                     (0x1<<2) // Instruction FIFO error.
+  #define PB_REG_INT_STS_CLR_IFIFO_ERROR_SHIFT                                                               2
+  #define PB_REG_INT_STS_CLR_PFIFO_ERROR                                                                     (0x1<<3) // Parameter FIFO error.
+  #define PB_REG_INT_STS_CLR_PFIFO_ERROR_SHIFT                                                               3
+  #define PB_REG_INT_STS_CLR_DB_BUF_ERROR                                                                    (0x1<<4) // DB FIFO error.
+  #define PB_REG_INT_STS_CLR_DB_BUF_ERROR_SHIFT                                                              4
+  #define PB_REG_INT_STS_CLR_TH_EXEC_ERROR                                                                   (0x1<<5) // 
+  #define PB_REG_INT_STS_CLR_TH_EXEC_ERROR_SHIFT                                                             5
+  #define PB_REG_INT_STS_CLR_TQ_ERROR_WR                                                                     (0x1<<6) // TQ write overflow.
+  #define PB_REG_INT_STS_CLR_TQ_ERROR_WR_SHIFT                                                               6
+  #define PB_REG_INT_STS_CLR_TQ_ERROR_RD_TH                                                                  (0x1<<7) // TQ read underflow by task handler.
+  #define PB_REG_INT_STS_CLR_TQ_ERROR_RD_TH_SHIFT                                                            7
+  #define PB_REG_INT_STS_CLR_TQ_ERROR_RD_IH                                                                  (0x1<<8) // TQ read underflow by instruction handler.
+  #define PB_REG_INT_STS_CLR_TQ_ERROR_RD_IH_SHIFT                                                            8
+#define PB_REG_PRTY_MASK                                                                                     0x000054UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define PB_REG_PRTY_MASK_DATAPATH_REGISTERS                                                                (0x1<<0) // This bit masks, when set, the Parity bit: PB_REG_PRTY_STS.DATAPATH_REGISTERS .
+  #define PB_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                                          0
+#define PB_REG_CONTROL                                                                                       0x000400UL //Access:RW   DataWidth:0xd    // Multi Field Register.
+  #define PB_REG_CONTROL_BYTE_ORDER_SWITCH                                                                   (0x1<<0) // Indicates if to switch the CRC result byte ordering. 0=don't switch;1=switch.
+  #define PB_REG_CONTROL_BYTE_ORDER_SWITCH_SHIFT                                                             0
+  #define PB_REG_CONTROL_DB_IGNORE_ERROR                                                                     (0x1<<1) // Indicates if to ignore the input error indication.
+  #define PB_REG_CONTROL_DB_IGNORE_ERROR_SHIFT                                                               1
+  #define PB_REG_CONTROL_DONT_PASS_ERROR                                                                     (0x1<<2) // Masks error on output of pb.
+  #define PB_REG_CONTROL_DONT_PASS_ERROR_SHIFT                                                               2
+  #define PB_REG_CONTROL_EOP_CHECK_DISABLE                                                                   (0x1<<3) // Disables EOP check (EOP check verifies that the last Task instruction is accessing a line that has EOP on it. this way one could find mismatches between expected length and actual length on some packet.
+  #define PB_REG_CONTROL_EOP_CHECK_DISABLE_SHIFT                                                             3
+  #define PB_REG_CONTROL_CRC_COMPARE_DISABLE                                                                 (0x1<<4) // Disables CRC2 machine (the machine that is used for comparing actual CRC with a value that is provided to the PB.
+  #define PB_REG_CONTROL_CRC_COMPARE_DISABLE_SHIFT                                                           4
+  #define PB_REG_CONTROL_EN_INPUTS                                                                           (0x1<<5) // Enable inputs.
+  #define PB_REG_CONTROL_EN_INPUTS_SHIFT                                                                     5
+  #define PB_REG_CONTROL_DISABLE_PB                                                                          (0x1<<6) // Debug only: Disable PB.
+  #define PB_REG_CONTROL_DISABLE_PB_SHIFT                                                                    6
+  #define PB_REG_CONTROL_DEBUG_SELECT                                                                        (0xf<<7) // Obsolete.
+  #define PB_REG_CONTROL_DEBUG_SELECT_SHIFT                                                                  7
+  #define PB_REG_CONTROL_RELAX_TH                                                                            (0x1<<11) // Dbug only.
+  #define PB_REG_CONTROL_RELAX_TH_SHIFT                                                                      11
+  #define PB_REG_CONTROL_DUMMY_ERR_ALLOW                                                                     (0x1<<12) // Dummy ingress error allow.  When cleared, an error received on the ingress interface will be masked for instructions in which the "dummy read" bit is set.
+  #define PB_REG_CONTROL_DUMMY_ERR_ALLOW_SHIFT                                                               12
+#define PB_REG_CRC_MASK_1_0                                                                                  0x000404UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PB_REG_CRC_MASK_1_1                                                                                  0x000408UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PB_REG_CRC_MASK_1_2                                                                                  0x00040cUL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PB_REG_CRC_MASK_1_3                                                                                  0x000410UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PB_REG_CRC_MASK_2_0                                                                                  0x000414UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PB_REG_CRC_MASK_2_1                                                                                  0x000418UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PB_REG_CRC_MASK_2_2                                                                                  0x00041cUL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PB_REG_CRC_MASK_2_3                                                                                  0x000420UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PB_REG_CRC_MASK_3_0                                                                                  0x000424UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PB_REG_CRC_MASK_3_1                                                                                  0x000428UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PB_REG_CRC_MASK_3_2                                                                                  0x00042cUL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PB_REG_CRC_MASK_3_3                                                                                  0x000430UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PB_REG_DB_EMPTY                                                                                      0x000500UL //Access:R    DataWidth:0x1    // Data Buffer empty status.
+#define PB_REG_DB_FULL                                                                                       0x000504UL //Access:R    DataWidth:0x1    // Data Buffer full status.
+#define PB_REG_TQ_EMPTY                                                                                      0x000508UL //Access:R    DataWidth:0x1    // Task Queue empty status.
+#define PB_REG_TQ_FULL                                                                                       0x00050cUL //Access:R    DataWidth:0x1    // Task Queue full status.
+#define PB_REG_IFIFO_EMPTY                                                                                   0x000510UL //Access:R    DataWidth:0x1    // Instruction FIFO empty status.
+#define PB_REG_IFIFO_FULL                                                                                    0x000514UL //Access:R    DataWidth:0x1    // Instruction FIFO full status.
+#define PB_REG_PFIFO_EMPTY                                                                                   0x000518UL //Access:R    DataWidth:0x1    // Parameter FIFO empty status.
+#define PB_REG_PFIFO_FULL                                                                                    0x00051cUL //Access:R    DataWidth:0x1    // Parameter FIFO full status.
+#define PB_REG_TQ_TH_EMPTY                                                                                   0x000520UL //Access:R    DataWidth:0x1    // Task Queue empty status for task handler.
+#define PB_REG_ERRORED_CRC                                                                                   0x000600UL //Access:R    DataWidth:0x20   // CRC mismatch debug register.  This register stores the calculated CRC value that resulted in the most recent CRC error event.
+#define PB_REG_ERRORED_INSTR                                                                                 0x000604UL //Access:R    DataWidth:0x20   // EOP mismatch debug register.  Use this address to read the instruction being executed at the time EOP error is detected. The instruction is aligned with the least significant bit of this register.  Bits 31:29 provide additional information about the instruction.  Bit 31 indicates whether the instruction is valid.  Bit 30 indicates if the instruction is the first instruction in the task.  Bit 29 indicates whether the instruction is the last instruction in the task.
+#define PB_REG_ERRORED_HDR_LOW                                                                               0x000608UL //Access:R    DataWidth:0x20   // EOP mismatch debug register.  Use this address to read the lower 32 bits of the task header being executed at the time EOP error is detected.  The instruction length is not kept and is read as 0.
+#define PB_REG_ERRORED_HDR_HIGH                                                                              0x00060cUL //Access:R    DataWidth:0x20   // EOP mismatch debug register.  Use this address to read the upper 32 bits of the task header being executed at the time EOP error is detected.  The task passthrough bit is not kept and is read as 0.
+#define PB_REG_ERRORED_LENGTH                                                                                0x000610UL //Access:R    DataWidth:0x10   // EOP mismatch debug register.  This register provides the number of data bytes remaining to be read from DB at the time of EOP error detection.
+#define PB_REG_ECO_RESERVED                                                                                  0x000614UL //Access:RW   DataWidth:0x8    // For future eco.
+#define PB_REG_DBG_OUT_DATA                                                                                  0x000700UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PB_REG_DBG_OUT_DATA_SIZE                                                                             8
+#define PB_REG_DBG_OUT_VALID                                                                                 0x000720UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define PB_REG_DBG_OUT_FRAME                                                                                 0x000724UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define PB_REG_DBG_SELECT                                                                                    0x000728UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PB_REG_DBG_DWORD_ENABLE                                                                              0x00072cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PB_REG_DBG_SHIFT                                                                                     0x000730UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PB_REG_DBG_FORCE_VALID                                                                               0x000734UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PB_REG_DBG_FORCE_FRAME                                                                               0x000738UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PB_REG_DB_FIFO                                                                                       0x002000UL //Access:WB_R DataWidth:0x108  // Provides read-only access of the data buffer FIFO. Intended for debug purposes.
+#define PB_REG_DB_FIFO_SIZE                                                                                  512
+#define PB_REG_L1                                                                                            0x003000UL //Access:WB   DataWidth:0x40   // L1 CRC memory access.
+#define PB_REG_L1_SIZE                                                                                       640
+#define ETH_MAC_REG_REVISION_K2_E5                                                                           0x000000UL //Access:R    DataWidth:0x20   // Package defined constants
+  #define ETH_MAC_REG_REVISION_CORE_REVISION_K2_E5                                                           (0xff<<0) // 8-bit value from package parameter CORE_REVISION
+  #define ETH_MAC_REG_REVISION_CORE_REVISION_K2_E5_SHIFT                                                     0
+  #define ETH_MAC_REG_REVISION_CORE_VERSION_K2_E5                                                            (0xff<<8) // 8-bit value from package parameter CORE_VERSION
+  #define ETH_MAC_REG_REVISION_CORE_VERSION_K2_E5_SHIFT                                                      8
+  #define ETH_MAC_REG_REVISION_CUSTOMER_REVISION_K2_E5                                                       (0xffff<<16) // Programmable Customer Revision from package parameter CUST_REVISION
+  #define ETH_MAC_REG_REVISION_CUSTOMER_REVISION_K2_E5_SHIFT                                                 16
+#define ETH_MAC_REG_SCRATCH_K2_E5                                                                            0x000004UL //Access:RW   DataWidth:0x20   // General Purpose
+#define ETH_MAC_REG_COMMAND_CONFIG_K2_E5                                                                     0x000008UL //Access:RW   DataWidth:0x20   // Control and Configuration
+  #define ETH_MAC_REG_COMMAND_CONFIG_TX_ENA_K2_E5                                                            (0x1<<0) // MAC Transmit Path Enable. Should be set to '1' to enable the MAC transmit path, should be set to '0' (Reset value) to disable the MAC transmit path.
+  #define ETH_MAC_REG_COMMAND_CONFIG_TX_ENA_K2_E5_SHIFT                                                      0
+  #define ETH_MAC_REG_COMMAND_CONFIG_RX_ENA_K2_E5                                                            (0x1<<1) // MAC Receive Path Enable. Should be set to '1' to enable the MAC receive path, should be set to '0' (Reset value) to disable the MAC receive path.
+  #define ETH_MAC_REG_COMMAND_CONFIG_RX_ENA_K2_E5_SHIFT                                                      1
+  #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV2_K2_E5                                                        (0x1<<2) // reserved
+  #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV2_K2_E5_SHIFT                                                  2
+  #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV3_K2_E5                                                        (0x1<<3) // reserved
+  #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV3_K2_E5_SHIFT                                                  3
+  #define ETH_MAC_REG_COMMAND_CONFIG_PROMIS_EN_K2_E5                                                         (0x1<<4) // Enable MAC Promiscuous Operation. If set to '1', all frames are received without any MAC address filtering. If set to '0' (Reset value), Unicast frames with a destination address not matching the Core MAC address (programmed in registers MAC_ADDR_0 and MAC_ADDR_1) are rejected.
+  #define ETH_MAC_REG_COMMAND_CONFIG_PROMIS_EN_K2_E5_SHIFT                                                   4
+  #define ETH_MAC_REG_COMMAND_CONFIG_PAD_EN_K2_E5                                                            (0x1<<5) // reserved, write 0 always. (MAC never removes padding)
+  #define ETH_MAC_REG_COMMAND_CONFIG_PAD_EN_K2_E5_SHIFT                                                      5
+  #define ETH_MAC_REG_COMMAND_CONFIG_CRC_FWD_K2_E5                                                           (0x1<<6) // Terminate / Forward Received CRC. If set to '1', the CRC field of received frames is forwarded with the frame to the user application. If set to '0' (Reset value), the CRC field is stripped from the frame. Note - If padding (Bit PAD_EN set to ?1?) is enabled, CRC_FWD is ignored.
+  #define ETH_MAC_REG_COMMAND_CONFIG_CRC_FWD_K2_E5_SHIFT                                                     6
+  #define ETH_MAC_REG_COMMAND_CONFIG_PAUSE_FWD_K2_E5                                                         (0x1<<7) // Terminate / Forward Pause Frames. If set to '1', pause frames are forwarded to the user application. If set to '0' (Reset value), pause frames are terminated and discarded within the MAC.
+  #define ETH_MAC_REG_COMMAND_CONFIG_PAUSE_FWD_K2_E5_SHIFT                                                   7
+  #define ETH_MAC_REG_COMMAND_CONFIG_PAUSE_IGNORE_K2_E5                                                      (0x1<<8) // Ignore received Pause frame quanta. If set to '1', received pause frames are ignored by the MAC. If set to '0' (Reset value), the transmit process is stopped for the amount of time specified in the pause quanta received within a pause frame.
+  #define ETH_MAC_REG_COMMAND_CONFIG_PAUSE_IGNORE_K2_E5_SHIFT                                                8
+  #define ETH_MAC_REG_COMMAND_CONFIG_TX_ADDR_INS_K2_E5                                                       (0x1<<9) // Set Source MAC Address on Transmit. If set to '1', the MAC overwrites the source MAC address received from the client interface with the MAC address programmed in registers MAC_ADDR_0 and MAC_ADDR_1 . If set to '0' (Reset value), the source MAC address from the client interface is transmitted unmodified to the line.
+  #define ETH_MAC_REG_COMMAND_CONFIG_TX_ADDR_INS_K2_E5_SHIFT                                                 9
+  #define ETH_MAC_REG_COMMAND_CONFIG_LOOPBACK_EN_K2_E5                                                       (0x1<<10) // Enable PHY Interface loopback. If set to '1', the signal loop_ena is set to '1'. If set to '0' (Reset value), the signal loop_ena is set to '0'.
+  #define ETH_MAC_REG_COMMAND_CONFIG_LOOPBACK_EN_K2_E5_SHIFT                                                 10
+  #define ETH_MAC_REG_COMMAND_CONFIG_TX_PAD_EN_K2_E5                                                         (0x1<<11) // reserved, writable but has no effect. The MAC never appends padding octets; the user application must provide frames of correct minimum size.
+  #define ETH_MAC_REG_COMMAND_CONFIG_TX_PAD_EN_K2_E5_SHIFT                                                   11
+  #define ETH_MAC_REG_COMMAND_CONFIG_SW_RESET_K2_E5                                                          (0x1<<12) // Self-Clearing Software Reset. When written with '1', all Statistics Counters are reset to 0.
+  #define ETH_MAC_REG_COMMAND_CONFIG_SW_RESET_K2_E5_SHIFT                                                    12
+  #define ETH_MAC_REG_COMMAND_CONFIG_CNTL_FRAME_ENA_K2_E5                                                    (0x1<<13) // Enable Reception of all Control Frames. If set to '1', all control frames are accepted. If set to '0', only Pause frames are accepted and all other command frames are rejected.
+  #define ETH_MAC_REG_COMMAND_CONFIG_CNTL_FRAME_ENA_K2_E5_SHIFT                                              13
+  #define ETH_MAC_REG_COMMAND_CONFIG_RX_ERR_DISC_K2_E5                                                       (0x1<<14) // Enable Receive Errored Frame Discard. Use only with RX FIFO Store and Forward. May not be supported by all Core variants.
+  #define ETH_MAC_REG_COMMAND_CONFIG_RX_ERR_DISC_K2_E5_SHIFT                                                 14
+  #define ETH_MAC_REG_COMMAND_CONFIG_PHY_TXENA_K2_E5                                                         (0x1<<15) // Controls toplevel pin phy_txena. No internal function
+  #define ETH_MAC_REG_COMMAND_CONFIG_PHY_TXENA_K2_E5_SHIFT                                                   15
+  #define ETH_MAC_REG_COMMAND_CONFIG_SEND_IDLE_K2_E5                                                         (0x1<<16) // Force Idle Generation. If set to '1', the MAC permanently sends XLGMII Idle sequences even when faults are received.
+  #define ETH_MAC_REG_COMMAND_CONFIG_SEND_IDLE_K2_E5_SHIFT                                                   16
+  #define ETH_MAC_REG_COMMAND_CONFIG_NO_LGTH_CHECK_K2_E5                                                     (0x1<<17) // Disable Payload Length Check. Not supported; write 0 always.
+  #define ETH_MAC_REG_COMMAND_CONFIG_NO_LGTH_CHECK_K2_E5_SHIFT                                               17
+  #define ETH_MAC_REG_COMMAND_CONFIG_RS_COL_CNT_EXT_K2_E5                                                    (0x1<<18) // reserved
+  #define ETH_MAC_REG_COMMAND_CONFIG_RS_COL_CNT_EXT_K2_E5_SHIFT                                              18
+  #define ETH_MAC_REG_COMMAND_CONFIG_PFC_MODE_K2_E5                                                          (0x1<<19) // Priority Flow Control Mode enable. If set to 1, the Core generates and processes PFC control frames according to the Priority Flow Control Interface signals. If set to 0 (Reset Value), the Core operates in legacy Pause Frame mode and generates and processes standard Pause Frames.
+  #define ETH_MAC_REG_COMMAND_CONFIG_PFC_MODE_K2_E5_SHIFT                                                    19
+  #define ETH_MAC_REG_COMMAND_CONFIG_PAUSE_PFC_COMP_K2_E5                                                    (0x1<<20) // Link Pause compatible with PFC mode. Pause is only indicated but does not stop TX.
+  #define ETH_MAC_REG_COMMAND_CONFIG_PAUSE_PFC_COMP_K2_E5_SHIFT                                              20
+  #define ETH_MAC_REG_COMMAND_CONFIG_RX_SFD_ANY_K2_E5                                                        (0x1<<21) // Disable check for SFD (0xd5) and accept frame with any character.
+  #define ETH_MAC_REG_COMMAND_CONFIG_RX_SFD_ANY_K2_E5_SHIFT                                                  21
+  #define ETH_MAC_REG_COMMAND_CONFIG_TX_FLUSH_K2_E5                                                          (0x1<<22) // Egress flush enable.
+  #define ETH_MAC_REG_COMMAND_CONFIG_TX_FLUSH_K2_E5_SHIFT                                                    22
+  #define ETH_MAC_REG_COMMAND_CONFIG_TX_LOWP_ENA_K2_E5                                                       (0x1<<23) // Instruct RS Layer to transmit LPI.
+  #define ETH_MAC_REG_COMMAND_CONFIG_TX_LOWP_ENA_K2_E5_SHIFT                                                 23
+  #define ETH_MAC_REG_COMMAND_CONFIG_LOWP_RXEMPTY_K2_E5                                                      (0x1<<24) // Mask toplevel pin reg_lowp with RX FIFO empty.
+  #define ETH_MAC_REG_COMMAND_CONFIG_LOWP_RXEMPTY_K2_E5_SHIFT                                                24
+  #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV25_K2_E5                                                       (0x1<<25) // reserved
+  #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV25_K2_E5_SHIFT                                                 25
+  #define ETH_MAC_REG_COMMAND_CONFIG_TX_FIFO_RESET_K2_E5                                                     (0x1<<26) // Self-Clearing TX FIFO reset command. May not be supported in all Core variants
+  #define ETH_MAC_REG_COMMAND_CONFIG_TX_FIFO_RESET_K2_E5_SHIFT                                               26
+  #define ETH_MAC_REG_COMMAND_CONFIG_FLT_HDL_DIS_K2_E5                                                       (0x1<<27) // Disable RS fault handling. When set to '0' (default), the MAC automatically inserts remote faults and idles in egress direction on detection of local faults and remote faults, respectively, on ingress direction. When set to '1', this feature is disabled.
+  #define ETH_MAC_REG_COMMAND_CONFIG_FLT_HDL_DIS_K2_E5_SHIFT                                                 27
+  #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV28_K2_E5                                                       (0x1<<28) // reserved
+  #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV28_K2_E5_SHIFT                                                 28
+  #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV29_K2_E5                                                       (0x1<<29) // reserved
+  #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV29_K2_E5_SHIFT                                                 29
+  #define ETH_MAC_REG_COMMAND_CONFIG_SHORT_PREAMBLE_K2_E5                                                    (0x1<<30) // reserved; write 0 always
+  #define ETH_MAC_REG_COMMAND_CONFIG_SHORT_PREAMBLE_K2_E5_SHIFT                                              30
+  #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV31_K2_E5                                                       (0x1<<31) // reserved
+  #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV31_K2_E5_SHIFT                                                 31
+#define ETH_MAC_REG_MAC_ADDR_0_K2_E5                                                                         0x00000cUL //Access:RW   DataWidth:0x20   // First 4 bytes of MAC address
+#define ETH_MAC_REG_MAC_ADDR_1_K2_E5                                                                         0x000010UL //Access:RW   DataWidth:0x20   // Last 2 bytes of MAC address
+  #define ETH_MAC_REG_MAC_ADDR_1_MAC_ADDRESS_1_K2_E5                                                         (0xffff<<0) // Last 2 bytes: 5th is 7:0, 6th is 15:8
+  #define ETH_MAC_REG_MAC_ADDR_1_MAC_ADDRESS_1_K2_E5_SHIFT                                                   0
+#define ETH_MAC_REG_FRM_LENGTH_K2_E5                                                                         0x000014UL //Access:RW   DataWidth:0x20   // Maximum Frame Size
+  #define ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5                                                            (0xffff<<0) // Maximum Frame Size
+  #define ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT                                                      0
+  #define ETH_MAC_REG_FRM_LENGTH_TX_MTU_K2_E5                                                                (0xffff<<16) // Optional maximum frame size setting for transmit statistics use if it should be different from receive statistics. When set to 0 the FRM_LENGTH value is used (i.e. statistics symmetric for TX and RX).
+  #define ETH_MAC_REG_FRM_LENGTH_TX_MTU_K2_E5_SHIFT                                                          16
+#define ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5                                                                   0x00001cUL //Access:RW   DataWidth:0x20   // RX FIFO thresholds
+  #define ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5                                                 (0xffff<<0) // RX section full threshold
+  #define ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT                                           0
+  #define ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_EMPTY_K2_E5                                                (0xffff<<16) // RX section empty threshold
+  #define ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_EMPTY_K2_E5_SHIFT                                          16
+#define ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5                                                                   0x000020UL //Access:RW   DataWidth:0x20   // TX FIFO thresholds
+  #define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5                                                 (0xffff<<0) // TX section full threshold
+  #define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT                                           0
+  #define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5                                                (0xffff<<16) // TX section empty threshold
+  #define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT                                          16
+#define ETH_MAC_REG_RX_FIFO_ALMOST_F_E_K2_E5                                                                 0x000024UL //Access:R    DataWidth:0x20   // Not configurable
+  #define ETH_MAC_REG_RX_FIFO_ALMOST_F_E_RX_FIFO_ALMOST_EMPTY_K2_E5                                          (0xffff<<0) // RX FIFO almost empty threshold
+  #define ETH_MAC_REG_RX_FIFO_ALMOST_F_E_RX_FIFO_ALMOST_EMPTY_K2_E5_SHIFT                                    0
+  #define ETH_MAC_REG_RX_FIFO_ALMOST_F_E_RX_FIFO_ALMOST_FULL_K2_E5                                           (0xffff<<16) // RX FIFO almost full threshold
+  #define ETH_MAC_REG_RX_FIFO_ALMOST_F_E_RX_FIFO_ALMOST_FULL_K2_E5_SHIFT                                     16
+#define ETH_MAC_REG_TX_FIFO_ALMOST_F_E_K2_E5                                                                 0x000028UL //Access:R    DataWidth:0x20   // Not configurable
+  #define ETH_MAC_REG_TX_FIFO_ALMOST_F_E_TX_FIFO_ALMOST_EMPTY_K2_E5                                          (0xffff<<0) // TX FIFO almost empty threshold
+  #define ETH_MAC_REG_TX_FIFO_ALMOST_F_E_TX_FIFO_ALMOST_EMPTY_K2_E5_SHIFT                                    0
+  #define ETH_MAC_REG_TX_FIFO_ALMOST_F_E_TX_FIFO_ALMOST_FULL_K2_E5                                           (0xffff<<16) // TX FIFO almost full threshold
+  #define ETH_MAC_REG_TX_FIFO_ALMOST_F_E_TX_FIFO_ALMOST_FULL_K2_E5_SHIFT                                     16
+#define ETH_MAC_REG_HASHTABLE_LOAD_K2_E5                                                                     0x00002cUL //Access:RW   DataWidth:0x20   // reserved; register is writeable bits 8,4:0 but have no effect.
+  #define ETH_MAC_REG_HASHTABLE_LOAD_HASH_TABLE_ADDRESS_K2_E5                                                (0x1f<<0) // 0 specify the hash table address (code)
+  #define ETH_MAC_REG_HASHTABLE_LOAD_HASH_TABLE_ADDRESS_K2_E5_SHIFT                                          0
+  #define ETH_MAC_REG_HASHTABLE_LOAD_ENABLE_MULTICAST_FRAME_K2_E5                                            (0x1<<8) // enables (1) or disables (0) multicast frame reception for the entry.
+  #define ETH_MAC_REG_HASHTABLE_LOAD_ENABLE_MULTICAST_FRAME_K2_E5_SHIFT                                      8
+#define ETH_MAC_REG_MDIO_CFG_STATUS_K2_E5                                                                    0x000030UL //Access:RW   DataWidth:0x20   // MDIO Configuration and Status
+  #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_BUSY_K2_E5                                                        (0x1<<0) // MDIO busy. If set, a MDIO transaction is currently ongoing. If cleared, the application can access the other registers.
+  #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_BUSY_K2_E5_SHIFT                                                  0
+  #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_READ_ERROR_K2_E5                                                  (0x1<<1) // MDIO read error. If set, the last read transaction had no response from a PHY and the data read could be invalid. This can happen, if the PHY address does not match any PHY that is available on the MDIO bus.
+  #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_READ_ERROR_K2_E5_SHIFT                                            1
+  #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_HOLD_TIME_SETTING_K2_E5                                           (0x7<<2) // MDIO hold time setting (reg_clk cycles).
+  #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_HOLD_TIME_SETTING_K2_E5_SHIFT                                     2
+  #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_DISABLE_PREAMBLE_K2_E5                                            (0x1<<5) // MDIO transaction preamble disable. Shortens transaction but is non-standard.
+  #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_DISABLE_PREAMBLE_K2_E5_SHIFT                                      5
+  #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_CLAUSE45_K2_E5                                                    (0x1<<6) // MDIO transaction use Clause 45 format (1) or Clause 22 format (0).
+  #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_CLAUSE45_K2_E5_SHIFT                                              6
+  #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_CLOCK_DIVISOR_K2_E5                                               (0x1ff<<7) // MDIO clock divisor; A value of 5 to 511. The frequency is reg_clk/(2*divisor+1). The reset default is defined by the synthesis package setting MDIO_CLK_DIV. Setting the divisor to 0 disables MDC.
+  #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_CLOCK_DIVISOR_K2_E5_SHIFT                                         7
+#define ETH_MAC_REG_MDIO_COMMAND_K2_E5                                                                       0x000034UL //Access:RW   DataWidth:0x20   // MDIO Command (PHY and Port Address)
+  #define ETH_MAC_REG_MDIO_COMMAND_DEVICE_ADDRESS_K2_E5                                                      (0x1f<<0) // Device Address
+  #define ETH_MAC_REG_MDIO_COMMAND_DEVICE_ADDRESS_K2_E5_SHIFT                                                0
+  #define ETH_MAC_REG_MDIO_COMMAND_PORT_ADDRESS_K2_E5                                                        (0x1f<<5) // Port Address
+  #define ETH_MAC_REG_MDIO_COMMAND_PORT_ADDRESS_K2_E5_SHIFT                                                  5
+  #define ETH_MAC_REG_MDIO_COMMAND_READ_ADDRESS_POST_INCREMENT_K2_E5                                         (0x1<<14) // If written with 1, a read with address post-increment will be performed. Post-increment will be performed in the PHY internal address register.
+  #define ETH_MAC_REG_MDIO_COMMAND_READ_ADDRESS_POST_INCREMENT_K2_E5_SHIFT                                   14
+  #define ETH_MAC_REG_MDIO_COMMAND_NORMAL_READ_TRANSACTION_K2_E5                                             (0x1<<15) // If written with 1, a normal read transaction is initiated.
+  #define ETH_MAC_REG_MDIO_COMMAND_NORMAL_READ_TRANSACTION_K2_E5_SHIFT                                       15
+#define ETH_MAC_REG_MDIO_DATA_K2_E5                                                                          0x000038UL //Access:RW   DataWidth:0x20   // MDIO Data to write and last Data read
+  #define ETH_MAC_REG_MDIO_DATA_MDIO_DATA_K2_E5                                                              (0xffff<<0) // 16-bit data word. When written- Initiates a write transaction to the PHY. The MDIO_COMMAND register must have been initialized. The busy status bit will be set immediately and cleared when the write transaction has finished. When read - Returns the data read from the PHY register after a read transaction has been completed (initiated by writing a 1 to Bit 15 or Bit 14 of the MDIO_COMMAND register).
+  #define ETH_MAC_REG_MDIO_DATA_MDIO_DATA_K2_E5_SHIFT                                                        0
+#define ETH_MAC_REG_MDIO_REGADDR_K2_E5                                                                       0x00003cUL //Access:W    DataWidth:0x20   // MDIO Register Address. Address of register within the PHY device to read from or write to. After writing this register, an address-write transaction will be initiated to set the PHY internal address register to the value given.
+  #define ETH_MAC_REG_MDIO_REGADDR_MDIO_REGADDR_K2_E5                                                        (0xffff<<0) // The MDIO_COMMAND register must have been initialized before the first write to this register.
+  #define ETH_MAC_REG_MDIO_REGADDR_MDIO_REGADDR_K2_E5_SHIFT                                                  0
+#define ETH_MAC_REG_STATUS_K2_E5                                                                             0x000040UL //Access:RW   DataWidth:0x20   // General Purpose Status
+  #define ETH_MAC_REG_STATUS_RX_LOC_FAULT_K2_E5                                                              (0x1<<0) // Local Fault Status. Set to '1' when the MAC detects Rx Local Fault Sequences on the CGMII receive interface.
+  #define ETH_MAC_REG_STATUS_RX_LOC_FAULT_K2_E5_SHIFT                                                        0
+  #define ETH_MAC_REG_STATUS_RX_REM_FAULT_K2_E5                                                              (0x1<<1) // Remote Fault Status. Set to '1' when the MAC detects Rx Remote Fault Sequences on the CGMII receive interface
+  #define ETH_MAC_REG_STATUS_RX_REM_FAULT_K2_E5_SHIFT                                                        1
+  #define ETH_MAC_REG_STATUS_PHY_LOS_K2_E5                                                                   (0x1<<2) // PHY indicates loss-of-signal. Represents value of pin "phy_los".
+  #define ETH_MAC_REG_STATUS_PHY_LOS_K2_E5_SHIFT                                                             2
+  #define ETH_MAC_REG_STATUS_TS_AVAIL_K2_E5                                                                  (0x1<<3) // Transmit Timestamp Available. Indicates that the timestamp of the last transmitted 1588 event frame is available in the register TS_TIMESTAMP.  To clear TS_AVAIL, the bit must be written with a '1'.
+  #define ETH_MAC_REG_STATUS_TS_AVAIL_K2_E5_SHIFT                                                            3
+  #define ETH_MAC_REG_STATUS_RX_LOWP_K2_E5                                                                   (0x1<<4) // Receiving Low Power Idle (LPI)
+  #define ETH_MAC_REG_STATUS_RX_LOWP_K2_E5_SHIFT                                                             4
+  #define ETH_MAC_REG_STATUS_TX_EMPTY_K2_E5                                                                  (0x1<<5) // TX FIFO is empty
+  #define ETH_MAC_REG_STATUS_TX_EMPTY_K2_E5_SHIFT                                                            5
+  #define ETH_MAC_REG_STATUS_RX_EMPTY_K2_E5                                                                  (0x1<<6) // RX FIFO is empty
+  #define ETH_MAC_REG_STATUS_RX_EMPTY_K2_E5_SHIFT                                                            6
+  #define ETH_MAC_REG_STATUS_RX_LINT_FAULT_K2_E5                                                             (0x1<<7) // Special Link Interruption Fault Sequence detected in receive
+  #define ETH_MAC_REG_STATUS_RX_LINT_FAULT_K2_E5_SHIFT                                                       7
+  #define ETH_MAC_REG_STATUS_TX_IS_IDLE_K2_E5                                                                (0x1<<8) // TX MAC datapath (statemachine) is idle
+  #define ETH_MAC_REG_STATUS_TX_IS_IDLE_K2_E5_SHIFT                                                          8
+#define ETH_MAC_REG_TX_IPG_LENGTH_K2_E5                                                                      0x000044UL //Access:RW   DataWidth:0x20   // TX InterPacketGap configuration
+  #define ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5                                                              (0x7f<<0) // Number of octets in steps of 4 (XGMII) or 8 (XLGMII). Minimum 8. Value 12 should be set for compliant operation.
+  #define ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT                                                        0
+  #define ETH_MAC_REG_TX_IPG_LENGTH_COMPENSATION_K2_E5                                                       (0xffff<<16) // Compensation for PCS inserted markers. Depending on PCS type a value of 16383 (40G) or 20479 (25/50G) must be set.
+  #define ETH_MAC_REG_TX_IPG_LENGTH_COMPENSATION_K2_E5_SHIFT                                                 16
+#define ETH_MAC_REG_CREDIT_TRIGGER_K2_E5                                                                     0x000048UL //Access:RW   DataWidth:0x20   // reserved
+  #define ETH_MAC_REG_CREDIT_TRIGGER_LOADCREDIT_K2_E5                                                        (0x1<<0) // Credit-based FIFO only: When written with a 1, RX FIFO reset occurs and credit counter loaded from the INIT_CREDIT value.
+  #define ETH_MAC_REG_CREDIT_TRIGGER_LOADCREDIT_K2_E5_SHIFT                                                  0
+#define ETH_MAC_REG_INIT_CREDIT_K2_E5                                                                        0x00004cUL //Access:RW   DataWidth:0x20   // reserved
+  #define ETH_MAC_REG_INIT_CREDIT_INITIALCREDIT_K2_E5                                                        (0xff<<0) // Credit-based FIFO only: Specifies the initial credit value to be loaded.
+  #define ETH_MAC_REG_INIT_CREDIT_INITIALCREDIT_K2_E5_SHIFT                                                  0
+#define ETH_MAC_REG_CREDIT_REG_K2_E5                                                                         0x000050UL //Access:R    DataWidth:0x20   // reserved
+  #define ETH_MAC_REG_CREDIT_REG_CREDITS_K2_E5                                                               (0xff<<0) // Current credit register value (for debug purpose only).
+  #define ETH_MAC_REG_CREDIT_REG_CREDITS_K2_E5_SHIFT                                                         0
+#define ETH_MAC_REG_CL01_PAUSE_QUANTA_K2_E5                                                                  0x000054UL //Access:RW   DataWidth:0x20   // Class 0 and 1 pause quanta. When link pause mode is enabled, CL0_PAUSE_QUANTA is used.
+  #define ETH_MAC_REG_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_K2_E5                                               (0xffff<<0) // CL0_PAUSE_QUANTA
+  #define ETH_MAC_REG_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_K2_E5_SHIFT                                         0
+  #define ETH_MAC_REG_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_K2_E5                                               (0xffff<<16) // Value to be sent for the PFC quanta value for that class when a class XOFF is triggered. Each Quanta specifies a 512 bit-time.
+  #define ETH_MAC_REG_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_K2_E5_SHIFT                                         16
+#define ETH_MAC_REG_CL23_PAUSE_QUANTA_K2_E5                                                                  0x000058UL //Access:RW   DataWidth:0x20   // Class 2 and 3 pause quanta
+  #define ETH_MAC_REG_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_K2_E5                                               (0xffff<<0) // CL2_PAUSE_QUANTA
+  #define ETH_MAC_REG_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_K2_E5_SHIFT                                         0
+  #define ETH_MAC_REG_CL23_PAUSE_QUANTA_CL3_PAUSE_QUANTA_K2_E5                                               (0xffff<<16) // CL3_PAUSE_QUANTA; Value to be sent for the PFC quanta value for that class when a class XOFF is triggered.
+  #define ETH_MAC_REG_CL23_PAUSE_QUANTA_CL3_PAUSE_QUANTA_K2_E5_SHIFT                                         16
+#define ETH_MAC_REG_CL45_PAUSE_QUANTA_K2_E5                                                                  0x00005cUL //Access:RW   DataWidth:0x20   // Class 4 and 5 pause quanta
+  #define ETH_MAC_REG_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_K2_E5                                               (0xffff<<0) // CL4_PAUSE_QUANTA
+  #define ETH_MAC_REG_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_K2_E5_SHIFT                                         0
+  #define ETH_MAC_REG_CL45_PAUSE_QUANTA_CL5_PAUSE_QUANTA_K2_E5                                               (0xffff<<16) // CL5_PAUSE_QUANTA; Value to be sent for the PFC quanta value for that class when a class XOFF is triggered.
+  #define ETH_MAC_REG_CL45_PAUSE_QUANTA_CL5_PAUSE_QUANTA_K2_E5_SHIFT                                         16
+#define ETH_MAC_REG_CL67_PAUSE_QUANTA_K2_E5                                                                  0x000060UL //Access:RW   DataWidth:0x20   // Class 6 and 7 pause quanta
+  #define ETH_MAC_REG_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_K2_E5                                               (0xffff<<0) // CL6_PAUSE_QUANTA
+  #define ETH_MAC_REG_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_K2_E5_SHIFT                                         0
+  #define ETH_MAC_REG_CL67_PAUSE_QUANTA_CL7_PAUSE_QUANTA_K2_E5                                               (0xffff<<16) // CL7_PAUSE_QUANTA; Value to be sent for the PFC quanta value for that class when a class XOFF is triggered.
+  #define ETH_MAC_REG_CL67_PAUSE_QUANTA_CL7_PAUSE_QUANTA_K2_E5_SHIFT                                         16
+#define ETH_MAC_REG_CL01_QUANTA_THRESH_K2_E5                                                                 0x000064UL //Access:RW   DataWidth:0x20   // Class 0 and 1 refresh threshold. When link pause mode is enabled, CL0_QUANTA_THRESH is used for refreshing pause frames.
+  #define ETH_MAC_REG_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_K2_E5                                             (0xffff<<0) // CL0_QUANTA_THRESH
+  #define ETH_MAC_REG_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_K2_E5_SHIFT                                       0
+  #define ETH_MAC_REG_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_K2_E5                                             (0xffff<<16) // CL1_QUANTA_THRESH;When a PFC quanta timer counts down and reaches this value, a refresh pause frame should be sent with the programmed full quanta value if the input level indicates that a pause condition still exists.
+  #define ETH_MAC_REG_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_K2_E5_SHIFT                                       16
+#define ETH_MAC_REG_CL23_QUANTA_THRESH_K2_E5                                                                 0x000068UL //Access:RW   DataWidth:0x20   // Class 2 and 3 refresh threshold
+  #define ETH_MAC_REG_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_K2_E5                                             (0xffff<<0) // CL2_QUANTA_THRESH
+  #define ETH_MAC_REG_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_K2_E5_SHIFT                                       0
+  #define ETH_MAC_REG_CL23_QUANTA_THRESH_CL3_QUANTA_THRESH_K2_E5                                             (0xffff<<16) // CL3_QUANTA_THRESH; When a PFC quanta timer counts down and reaches this value, a refresh pause frame should be sent with the programmed full quanta value if the input level indicates that a pause condition still exists.
+  #define ETH_MAC_REG_CL23_QUANTA_THRESH_CL3_QUANTA_THRESH_K2_E5_SHIFT                                       16
+#define ETH_MAC_REG_CL45_QUANTA_THRESH_K2_E5                                                                 0x00006cUL //Access:RW   DataWidth:0x20   // Class 2 and 3 refresh threshold
+  #define ETH_MAC_REG_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_K2_E5                                             (0xffff<<0) // CL4_QUANTA_THRESH
+  #define ETH_MAC_REG_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_K2_E5_SHIFT                                       0
+  #define ETH_MAC_REG_CL45_QUANTA_THRESH_CL5_QUANTA_THRESH_K2_E5                                             (0xffff<<16) // CL5_QUANTA_THRESH
+  #define ETH_MAC_REG_CL45_QUANTA_THRESH_CL5_QUANTA_THRESH_K2_E5_SHIFT                                       16
+#define ETH_MAC_REG_CL67_QUANTA_THRESH_K2_E5                                                                 0x000070UL //Access:RW   DataWidth:0x20   // Class 6 and 7 refresh threshold
+  #define ETH_MAC_REG_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_K2_E5                                             (0xffff<<0) // CL6_QUANTA_THRESH
+  #define ETH_MAC_REG_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_K2_E5_SHIFT                                       0
+  #define ETH_MAC_REG_CL67_QUANTA_THRESH_CL7_QUANTA_THRESH_K2_E5                                             (0xffff<<16) // CL7_QUANTA_THRESH
+  #define ETH_MAC_REG_CL67_QUANTA_THRESH_CL7_QUANTA_THRESH_K2_E5_SHIFT                                       16
+#define ETH_MAC_REG_RX_PAUSE_STATUS_K2_E5                                                                    0x000074UL //Access:R    DataWidth:0x20   // Current per class received pause status. 0 is used for link pause also.
+  #define ETH_MAC_REG_RX_PAUSE_STATUS_PAUSESTATUS_K2_E5                                                      (0xff<<0) // Status bit for software to read the current received pause status. One bit for each of the 8 classes.
+  #define ETH_MAC_REG_RX_PAUSE_STATUS_PAUSESTATUS_K2_E5_SHIFT                                                0
+#define ETH_MAC_REG_TS_TIMESTAMP_K2_E5                                                                       0x00007cUL //Access:R    DataWidth:0x20   // Transmit Timestamp
+#define ETH_MAC_REG_XIF_MODE_K2_E5                                                                           0x000080UL //Access:RW   DataWidth:0x20   // Interface Mode Configuration
+  #define ETH_MAC_REG_XIF_MODE_XGMII_K2_E5                                                                   (0x1<<0) // Enable XGMII-64 (4byte alignment)
+  #define ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT                                                             0
+  #define ETH_MAC_REG_XIF_MODE_PAUSETIMERX8_K2_E5                                                            (0x1<<4) // Enable Pause Timer Compensation when using external XLGMII/GMII Converter
+  #define ETH_MAC_REG_XIF_MODE_PAUSETIMERX8_K2_E5_SHIFT                                                      4
+  #define ETH_MAC_REG_XIF_MODE_ONESTEPENA_K2_E5                                                              (0x1<<5) // Enable 1-step capable datapath (if available)
+  #define ETH_MAC_REG_XIF_MODE_ONESTEPENA_K2_E5_SHIFT                                                        5
+#define ETH_MAC_REG_STATN_CONFIG_K2_E5                                                                       0x0000e0UL //Access:RW   DataWidth:0x20   // statistics configuration options
+  #define ETH_MAC_REG_STATN_CONFIG_SATURATE_K2_E5                                                            (0x1<<0) // Configure saturation behavior. When set to 1, the counters saturate at all-1. Otherwise counters wrap around.
+  #define ETH_MAC_REG_STATN_CONFIG_SATURATE_K2_E5_SHIFT                                                      0
+  #define ETH_MAC_REG_STATN_CONFIG_CLEAR_ON_READ_K2_E5                                                       (0x1<<1) // Configure clear-on-read behavior. When set to 1, the counters are cleared (set to STATN_CLEARVALUE) after having been transferred into the read registers (snapshot captured). When set 0 (default) the counters are not modified when read/captured.
+  #define ETH_MAC_REG_STATN_CONFIG_CLEAR_ON_READ_K2_E5_SHIFT                                                 1
+  #define ETH_MAC_REG_STATN_CONFIG_CLEAR_K2_E5                                                               (0x1<<2) // Clear all counters command (self-clearing). When written with 1 all counters (tx and rx) are cleared (set to STATN_CLEARVALUE).
+  #define ETH_MAC_REG_STATN_CONFIG_CLEAR_K2_E5_SHIFT                                                         2
+#define ETH_MAC_REG_STATN_CLEARVALUE_LO_K2_E5                                                                0x0000e4UL //Access:RW   DataWidth:0x20   // Lower 32bit of 64bit value written into statistics memory when a counter is cleared (testing only, should be 0 normally)
+#define ETH_MAC_REG_STATN_CLEARVALUE_HI_K2_E5                                                                0x0000e8UL //Access:RW   DataWidth:0x20   // Upper 32bit of 64bit value written into statistics memory when a counter is cleared (testing only, should be 0 normally)
+#define ETH_MAC_REG_ETHERSTATSOCTETS_K2_E5                                                                   0x000100UL //Access:R    DataWidth:0x20   // total, good and bad
+#define ETH_MAC_REG_ETHERSTATSOCTETS_H_K2_E5                                                                 0x000104UL //Access:R    DataWidth:0x20   // total, good and bad
+#define ETH_MAC_REG_OCTETSOK_K2_E5                                                                           0x000108UL //Access:R    DataWidth:0x20   // total, good
+#define ETH_MAC_REG_OCTETSOK_H_K2_E5                                                                         0x00010cUL //Access:R    DataWidth:0x20   // total, good
+#define ETH_MAC_REG_AALIGNMENTERRORS_K2_E5                                                                   0x000110UL //Access:R    DataWidth:0x20   // Wrong SFD detected
+#define ETH_MAC_REG_AALIGNMENTERRORS_H_K2_E5                                                                 0x000114UL //Access:R    DataWidth:0x20   // Wrong SFD detected
+#define ETH_MAC_REG_APAUSEMACCTRLFRAMES_K2_E5                                                                0x000118UL //Access:R    DataWidth:0x20   // Good Pause frames received
+#define ETH_MAC_REG_APAUSEMACCTRLFRAMES_H_K2_E5                                                              0x00011cUL //Access:R    DataWidth:0x20   // Good Pause frames received
+#define ETH_MAC_REG_FRAMESOK_K2_E5                                                                           0x000120UL //Access:R    DataWidth:0x20   // Good frames received
+#define ETH_MAC_REG_FRAMESOK_H_K2_E5                                                                         0x000124UL //Access:R    DataWidth:0x20   // Good frames received
+#define ETH_MAC_REG_CRCERRORS_K2_E5                                                                          0x000128UL //Access:R    DataWidth:0x20   // wrong CRC and good length received
+#define ETH_MAC_REG_CRCERRORS_H_K2_E5                                                                        0x00012cUL //Access:R    DataWidth:0x20   // wrong CRC and good length received
+#define ETH_MAC_REG_VLANOK_K2_E5                                                                             0x000130UL //Access:R    DataWidth:0x20   // Good Frames with VLAN tag received
+#define ETH_MAC_REG_VLANOK_H_K2_E5                                                                           0x000134UL //Access:R    DataWidth:0x20   // Good Frames with VLAN tag received
+#define ETH_MAC_REG_IFINERRORS_K2_E5                                                                         0x000138UL //Access:R    DataWidth:0x20   // Errored frames received
+#define ETH_MAC_REG_IFINERRORS_H_K2_E5                                                                       0x00013cUL //Access:R    DataWidth:0x20   // Errored frames received
+#define ETH_MAC_REG_IFINUCASTPKTS_K2_E5                                                                      0x000140UL //Access:R    DataWidth:0x20   // Good Unicast received
+#define ETH_MAC_REG_IFINUCASTPKTS_H_K2_E5                                                                    0x000144UL //Access:R    DataWidth:0x20   // Good Unicast received
+#define ETH_MAC_REG_IFINMCASTPKTS_K2_E5                                                                      0x000148UL //Access:R    DataWidth:0x20   // Good Multicast received
+#define ETH_MAC_REG_IFINMCASTPKTS_H_K2_E5                                                                    0x00014cUL //Access:R    DataWidth:0x20   // Good Multicast received
+#define ETH_MAC_REG_IFINBCASTPKTS_K2_E5                                                                      0x000150UL //Access:R    DataWidth:0x20   // Good Broadcast received
+#define ETH_MAC_REG_IFINBCASTPKTS_H_K2_E5                                                                    0x000154UL //Access:R    DataWidth:0x20   // Good Broadcast received
+#define ETH_MAC_REG_ETHERSTATSDROPEVENTS_K2_E5                                                               0x000158UL //Access:R    DataWidth:0x20   // Dropped frames
+#define ETH_MAC_REG_ETHERSTATSDROPEVENTS_H_K2_E5                                                             0x00015cUL //Access:R    DataWidth:0x20   // Dropped frames
+#define ETH_MAC_REG_ETHERSTATSPKTS_K2_E5                                                                     0x000160UL //Access:R    DataWidth:0x20   // Frames received, good and bad
+#define ETH_MAC_REG_ETHERSTATSPKTS_H_K2_E5                                                                   0x000164UL //Access:R    DataWidth:0x20   // Frames received, good and bad
+#define ETH_MAC_REG_ETHERSTATSUNDERSIZEPKTS_K2_E5                                                            0x000168UL //Access:R    DataWidth:0x20   // Frames received less 64 with good crc
+#define ETH_MAC_REG_ETHERSTATSUNDERSIZEPKTS_H_K2_E5                                                          0x00016cUL //Access:R    DataWidth:0x20   // Frames received less 64 with good crc
+#define ETH_MAC_REG_ETHERSTATSPKTS64_K2_E5                                                                   0x000170UL //Access:R    DataWidth:0x20   // Frames of 64 octets received
+#define ETH_MAC_REG_ETHERSTATSPKTS64_H_K2_E5                                                                 0x000174UL //Access:R    DataWidth:0x20   // Frames of 64 octets received
+#define ETH_MAC_REG_ETHERSTATSPKTS65TO127_K2_E5                                                              0x000178UL //Access:R    DataWidth:0x20   // Frames of 65 to 127 octets received
+#define ETH_MAC_REG_ETHERSTATSPKTS65TO127_H_K2_E5                                                            0x00017cUL //Access:R    DataWidth:0x20   // Frames of 65 to 127 octets received
+#define ETH_MAC_REG_ETHERSTATSPKTS128TO255_K2_E5                                                             0x000180UL //Access:R    DataWidth:0x20   // Frames of 128 to 255 octets received
+#define ETH_MAC_REG_ETHERSTATSPKTS128TO255_H_K2_E5                                                           0x000184UL //Access:R    DataWidth:0x20   // Frames of 128 to 255 octets received
+#define ETH_MAC_REG_ETHERSTATSPKTS256TO511_K2_E5                                                             0x000188UL //Access:R    DataWidth:0x20   // Frames of 256 to 511 octets received
+#define ETH_MAC_REG_ETHERSTATSPKTS256TO511_H_K2_E5                                                           0x00018cUL //Access:R    DataWidth:0x20   // Frames of 256 to 511 octets received
+#define ETH_MAC_REG_ETHERSTATSPKTS512TO1023_K2_E5                                                            0x000190UL //Access:R    DataWidth:0x20   // Frames of 512 to 1023 octets received
+#define ETH_MAC_REG_ETHERSTATSPKTS512TO1023_H_K2_E5                                                          0x000194UL //Access:R    DataWidth:0x20   // Frames of 512 to 1023 octets received
+#define ETH_MAC_REG_ETHERSTATSPKTS1024TO1518_K2_E5                                                           0x000198UL //Access:R    DataWidth:0x20   // Frames of 1024 to 1518 octets received
+#define ETH_MAC_REG_ETHERSTATSPKTS1024TO1518_H_K2_E5                                                         0x00019cUL //Access:R    DataWidth:0x20   // Frames of 1024 to 1518 octets received
+#define ETH_MAC_REG_ETHERSTATSPKTS1519TOMAX_K2_E5                                                            0x0001a0UL //Access:R    DataWidth:0x20   // Frames of 1519 to FRM_LENGTH octets received
+#define ETH_MAC_REG_ETHERSTATSPKTS1519TOMAX_H_K2_E5                                                          0x0001a4UL //Access:R    DataWidth:0x20   // Frames of 1519 to FRM_LENGTH octets received
+#define ETH_MAC_REG_ETHERSTATSPKTSOVERSIZE_K2_E5                                                             0x0001a8UL //Access:R    DataWidth:0x20   // Frames greater FRM_LENGTH and good CRC received
+#define ETH_MAC_REG_ETHERSTATSPKTSOVERSIZE_H_K2_E5                                                           0x0001acUL //Access:R    DataWidth:0x20   // Frames greater FRM_LENGTH and good CRC received
+#define ETH_MAC_REG_ETHERSTATSJABBERS_K2_E5                                                                  0x0001b0UL //Access:R    DataWidth:0x20   // Frames greater FRM_LENGTH and bad CRC received
+#define ETH_MAC_REG_ETHERSTATSJABBERS_H_K2_E5                                                                0x0001b4UL //Access:R    DataWidth:0x20   // Frames greater FRM_LENGTH and bad CRC received
+#define ETH_MAC_REG_ETHERSTATSFRAGMENTS_K2_E5                                                                0x0001b8UL //Access:R    DataWidth:0x20   // Frames less 64 and bad CRC received
+#define ETH_MAC_REG_ETHERSTATSFRAGMENTS_H_K2_E5                                                              0x0001bcUL //Access:R    DataWidth:0x20   // Frames less 64 and bad CRC received
+#define ETH_MAC_REG_AMACCONTROLFRAMES_K2_E5                                                                  0x0001c0UL //Access:R    DataWidth:0x20   // Good frames received of type 0x8808 but not Pause
+#define ETH_MAC_REG_AMACCONTROLFRAMES_H_K2_E5                                                                0x0001c4UL //Access:R    DataWidth:0x20   // Good frames received of type 0x8808 but not Pause
+#define ETH_MAC_REG_AFRAMETOOLONG_K2_E5                                                                      0x0001c8UL //Access:R    DataWidth:0x20   // Good and bad frames exceeding FRM_LENGTH received
+#define ETH_MAC_REG_AFRAMETOOLONG_H_K2_E5                                                                    0x0001ccUL //Access:R    DataWidth:0x20   // Good and bad frames exceeding FRM_LENGTH received
+#define ETH_MAC_REG_AINRANGELENGTHERROR_K2_E5                                                                0x0001d0UL //Access:R    DataWidth:0x20   // Good frames with invalid length field (not supported)
+#define ETH_MAC_REG_AINRANGELENGTHERROR_H_K2_E5                                                              0x0001d4UL //Access:R    DataWidth:0x20   // Good frames with invalid length field (not supported)
+#define ETH_MAC_REG_TXETHERSTATSOCTETS_K2_E5                                                                 0x000200UL //Access:R    DataWidth:0x20   // total, good and bad
+#define ETH_MAC_REG_TXETHERSTATSOCTETS_H_K2_E5                                                               0x000204UL //Access:R    DataWidth:0x20   // total, good and bad
+#define ETH_MAC_REG_TXOCTETSOK_K2_E5                                                                         0x000208UL //Access:R    DataWidth:0x20   // total, good
+#define ETH_MAC_REG_TXOCTETSOK_H_K2_E5                                                                       0x00020cUL //Access:R    DataWidth:0x20   // total, good
+#define ETH_MAC_REG_TXAPAUSEMACCTRLFRAMES_K2_E5                                                              0x000218UL //Access:R    DataWidth:0x20   // Good Pause frames transmitted
+#define ETH_MAC_REG_TXAPAUSEMACCTRLFRAMES_H_K2_E5                                                            0x00021cUL //Access:R    DataWidth:0x20   // Good Pause frames transmitted
+#define ETH_MAC_REG_TXFRAMESOK_K2_E5                                                                         0x000220UL //Access:R    DataWidth:0x20   // Good frames transmitted
+#define ETH_MAC_REG_TXFRAMESOK_H_K2_E5                                                                       0x000224UL //Access:R    DataWidth:0x20   // Good frames transmitted
+#define ETH_MAC_REG_TXCRCERRORS_K2_E5                                                                        0x000228UL //Access:R    DataWidth:0x20   // wrong CRC transmitted
+#define ETH_MAC_REG_TXCRCERRORS_H_K2_E5                                                                      0x00022cUL //Access:R    DataWidth:0x20   // wrong CRC transmitted
+#define ETH_MAC_REG_TXVLANOK_K2_E5                                                                           0x000230UL //Access:R    DataWidth:0x20   // Good Frames with VLAN tag transmitted
+#define ETH_MAC_REG_TXVLANOK_H_K2_E5                                                                         0x000234UL //Access:R    DataWidth:0x20   // Good Frames with VLAN tag transmitted
+#define ETH_MAC_REG_IFOUTERRORS_K2_E5                                                                        0x000238UL //Access:R    DataWidth:0x20   // Errored frames transmitted
+#define ETH_MAC_REG_IFOUTERRORS_H_K2_E5                                                                      0x00023cUL //Access:R    DataWidth:0x20   // Errored frames transmitted
+#define ETH_MAC_REG_IFOUTUCASTPKTS_K2_E5                                                                     0x000240UL //Access:R    DataWidth:0x20   // Good Unicast transmitted
+#define ETH_MAC_REG_IFOUTUCASTPKTS_H_K2_E5                                                                   0x000244UL //Access:R    DataWidth:0x20   // Good Unicast transmitted
+#define ETH_MAC_REG_IFOUTMCASTPKTS_K2_E5                                                                     0x000248UL //Access:R    DataWidth:0x20   // Good Multicast transmitted
+#define ETH_MAC_REG_IFOUTMCASTPKTS_H_K2_E5                                                                   0x00024cUL //Access:R    DataWidth:0x20   // Good Multicast transmitted
+#define ETH_MAC_REG_IFOUTBCASTPKTS_K2_E5                                                                     0x000250UL //Access:R    DataWidth:0x20   // Good Broadcast transmitted
+#define ETH_MAC_REG_IFOUTBCASTPKTS_H_K2_E5                                                                   0x000254UL //Access:R    DataWidth:0x20   // Good Broadcast transmitted
+#define ETH_MAC_REG_TXETHERSTATSDROPEVENTS_K2_E5                                                             0x000258UL //Access:R    DataWidth:0x20   // Dropped frames (unused, reserved)
+#define ETH_MAC_REG_TXETHERSTATSDROPEVENTS_H_K2_E5                                                           0x00025cUL //Access:R    DataWidth:0x20   // Dropped frames (unused, reserved)
+#define ETH_MAC_REG_TXETHERSTATSPKTS_K2_E5                                                                   0x000260UL //Access:R    DataWidth:0x20   // Frames transmitted, good and bad
+#define ETH_MAC_REG_TXETHERSTATSPKTS_H_K2_E5                                                                 0x000264UL //Access:R    DataWidth:0x20   // Frames transmitted, good and bad
+#define ETH_MAC_REG_TXETHERSTATSUNDERSIZEPKTS_K2_E5                                                          0x000268UL //Access:R    DataWidth:0x20   // Frames transmitted less 64
+#define ETH_MAC_REG_TXETHERSTATSUNDERSIZEPKTS_H_K2_E5                                                        0x00026cUL //Access:R    DataWidth:0x20   // Frames transmitted less 64
+#define ETH_MAC_REG_TXETHERSTATSPKTS64_K2_E5                                                                 0x000270UL //Access:R    DataWidth:0x20   // Frames of 64 octets transmitted
+#define ETH_MAC_REG_TXETHERSTATSPKTS64_H_K2_E5                                                               0x000274UL //Access:R    DataWidth:0x20   // Frames of 64 octets transmitted
+#define ETH_MAC_REG_TXETHERSTATSPKTS65TO127_K2_E5                                                            0x000278UL //Access:R    DataWidth:0x20   // Frames of 65 to 127 octets transmitted
+#define ETH_MAC_REG_TXETHERSTATSPKTS65TO127_H_K2_E5                                                          0x00027cUL //Access:R    DataWidth:0x20   // Frames of 65 to 127 octets transmitted
+#define ETH_MAC_REG_TXETHERSTATSPKTS128TO255_K2_E5                                                           0x000280UL //Access:R    DataWidth:0x20   // Frames of 128 to 255 octets transmitted
+#define ETH_MAC_REG_TXETHERSTATSPKTS128TO255_H_K2_E5                                                         0x000284UL //Access:R    DataWidth:0x20   // Frames of 128 to 255 octets transmitted
+#define ETH_MAC_REG_TXETHERSTATSPKTS256TO511_K2_E5                                                           0x000288UL //Access:R    DataWidth:0x20   // Frames of 256 to 511 octets transmitted
+#define ETH_MAC_REG_TXETHERSTATSPKTS256TO511_H_K2_E5                                                         0x00028cUL //Access:R    DataWidth:0x20   // Frames of 256 to 511 octets transmitted
+#define ETH_MAC_REG_TXETHERSTATSPKTS512TO1023_K2_E5                                                          0x000290UL //Access:R    DataWidth:0x20   // Frames of 512 to 1023 octets transmitted
+#define ETH_MAC_REG_TXETHERSTATSPKTS512TO1023_H_K2_E5                                                        0x000294UL //Access:R    DataWidth:0x20   // Frames of 512 to 1023 octets transmitted
+#define ETH_MAC_REG_TXETHERSTATSPKTS1024TO1518_K2_E5                                                         0x000298UL //Access:R    DataWidth:0x20   // Frames of 1024 to 1518 octets transmitted
+#define ETH_MAC_REG_TXETHERSTATSPKTS1024TO1518_H_K2_E5                                                       0x00029cUL //Access:R    DataWidth:0x20   // Frames of 1024 to 1518 octets transmitted
+#define ETH_MAC_REG_TXETHERSTATSPKTS1519TOTX_MTU_K2_E5                                                       0x0002a0UL //Access:R    DataWidth:0x20   // Frames of 1519 to FRM_LENGTH.TX_MTU octets transmitted
+#define ETH_MAC_REG_TXETHERSTATSPKTS1519TOTX_MTU_H_K2_E5                                                     0x0002a4UL //Access:R    DataWidth:0x20   // Frames of 1519 to FRM_LENGTH.TX_MTU octets transmitted
+#define ETH_MAC_REG_TXAMACCONTROLFRAMES_K2_E5                                                                0x0002c0UL //Access:R    DataWidth:0x20   // Good frames transmitted of type 0x8808 but not Pause
+#define ETH_MAC_REG_TXAMACCONTROLFRAMES_H_K2_E5                                                              0x0002c4UL //Access:R    DataWidth:0x20   // Good frames transmitted of type 0x8808 but not Pause
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_0_K2_E5                                                         0x000380UL //Access:R    DataWidth:0x20   // Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames received for each class.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_0_H_K2_E5                                                       0x000384UL //Access:R    DataWidth:0x20   // Upper 32bit of 64bit counter.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_1_K2_E5                                                         0x000388UL //Access:R    DataWidth:0x20   // Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames received for each class.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_1_H_K2_E5                                                       0x00038cUL //Access:R    DataWidth:0x20   // Upper 32bit of 64bit counter.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_2_K2_E5                                                         0x000390UL //Access:R    DataWidth:0x20   // Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames received for each class.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_2_H_K2_E5                                                       0x000394UL //Access:R    DataWidth:0x20   // Upper 32bit of 64bit counter.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_3_K2_E5                                                         0x000398UL //Access:R    DataWidth:0x20   // Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames received for each class.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_3_H_K2_E5                                                       0x00039cUL //Access:R    DataWidth:0x20   // Upper 32bit of 64bit counter.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_4_K2_E5                                                         0x0003a0UL //Access:R    DataWidth:0x20   // Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames received for each class.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_4_H_K2_E5                                                       0x0003a4UL //Access:R    DataWidth:0x20   // Upper 32bit of 64bit counter.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_5_K2_E5                                                         0x0003a8UL //Access:R    DataWidth:0x20   // Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames received for each class.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_5_H_K2_E5                                                       0x0003acUL //Access:R    DataWidth:0x20   // Upper 32bit of 64bit counter.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_6_K2_E5                                                         0x0003b0UL //Access:R    DataWidth:0x20   // Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames received for each class.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_6_H_K2_E5                                                       0x0003b4UL //Access:R    DataWidth:0x20   // Upper 32bit of 64bit counter.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_7_K2_E5                                                         0x0003b8UL //Access:R    DataWidth:0x20   // Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames received for each class.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_7_H_K2_E5                                                       0x0003bcUL //Access:R    DataWidth:0x20   // Upper 32bit of 64bit counter.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_0_K2_E5                                                      0x0003c0UL //Access:R    DataWidth:0x20   // Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames transmitted for each class.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_0_H_K2_E5                                                    0x0003c4UL //Access:R    DataWidth:0x20   // Upper 32bit of 64bit counter.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_1_K2_E5                                                      0x0003c8UL //Access:R    DataWidth:0x20   // Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames transmitted for each class.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_1_H_K2_E5                                                    0x0003ccUL //Access:R    DataWidth:0x20   // Upper 32bit of 64bit counter.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_2_K2_E5                                                      0x0003d0UL //Access:R    DataWidth:0x20   // Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames transmitted for each class.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_2_H_K2_E5                                                    0x0003d4UL //Access:R    DataWidth:0x20   // Upper 32bit of 64bit counter.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_3_K2_E5                                                      0x0003d8UL //Access:R    DataWidth:0x20   // Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames transmitted for each class.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_3_H_K2_E5                                                    0x0003dcUL //Access:R    DataWidth:0x20   // Upper 32bit of 64bit counter.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_4_K2_E5                                                      0x0003e0UL //Access:R    DataWidth:0x20   // Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames transmitted for each class.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_4_H_K2_E5                                                    0x0003e4UL //Access:R    DataWidth:0x20   // Upper 32bit of 64bit counter.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_5_K2_E5                                                      0x0003e8UL //Access:R    DataWidth:0x20   // Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames transmitted for each class.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_5_H_K2_E5                                                    0x0003ecUL //Access:R    DataWidth:0x20   // Upper 32bit of 64bit counter.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_6_K2_E5                                                      0x0003f0UL //Access:R    DataWidth:0x20   // Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames transmitted for each class.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_6_H_K2_E5                                                    0x0003f4UL //Access:R    DataWidth:0x20   // Upper 32bit of 64bit counter.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_7_K2_E5                                                      0x0003f8UL //Access:R    DataWidth:0x20   // Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames transmitted for each class.
+#define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_7_H_K2_E5                                                    0x0003fcUL //Access:R    DataWidth:0x20   // Upper 32bit of 64bit counter.
+#define ETH_RSFEC_REG_RS_FEC_CONTROL_K2_E5                                                                   0x000000UL //Access:RW   DataWidth:0x20   // Control register for enabling FEC functions.
+  #define ETH_RSFEC_REG_RS_FEC_CONTROL_BYPASS_CORRECTION_K2_E5                                               (0x1<<0) // When 1, bypass the decoder's correction function for reduced latency; When  0, normal FEC operation.
+  #define ETH_RSFEC_REG_RS_FEC_CONTROL_BYPASS_CORRECTION_K2_E5_SHIFT                                         0
+  #define ETH_RSFEC_REG_RS_FEC_CONTROL_BYPASS_ERROR_INDICATION_K2_E5                                         (0x1<<1) // When 1, configure the FEC decoder to not indicate errors to the PCS layer; When  0, the FEC decoder indicates errors to the PCS layer.
+  #define ETH_RSFEC_REG_RS_FEC_CONTROL_BYPASS_ERROR_INDICATION_K2_E5_SHIFT                                   1
+#define ETH_RSFEC_REG_RS_FEC_STATUS_K2_E5                                                                    0x000004UL //Access:R    DataWidth:0x20   // RS FEC Status register.
+  #define ETH_RSFEC_REG_RS_FEC_STATUS_BYPASS_CORRECTION_K2_E5                                                (0x1<<0) // Indicates existence of the receive correction bypass option; The bypass function allows a reduced latency operation.
+  #define ETH_RSFEC_REG_RS_FEC_STATUS_BYPASS_CORRECTION_K2_E5_SHIFT                                          0
+  #define ETH_RSFEC_REG_RS_FEC_STATUS_BYPASS_INDICATION_K2_E5                                                (0x1<<1) // Indicates the ability to disable error propagation to the PCS layer.
+  #define ETH_RSFEC_REG_RS_FEC_STATUS_BYPASS_INDICATION_K2_E5_SHIFT                                          1
+  #define ETH_RSFEC_REG_RS_FEC_STATUS_HIGH_SER_K2_E5                                                         (0x1<<2) // Asserts when error indication bypass is enabled and high symbol error rate is found;  Clear on read.
+  #define ETH_RSFEC_REG_RS_FEC_STATUS_HIGH_SER_K2_E5_SHIFT                                                   2
+  #define ETH_RSFEC_REG_RS_FEC_STATUS_AMPS_LOCK_K2_E5                                                        (0xf<<8) // RS-FEC receive lane locked and aligned; One bit per lane: Bit 8 = lane 0, Bit 9 = lane 1, Bit 10= lane 2, Bit 11 = lane 3.
+  #define ETH_RSFEC_REG_RS_FEC_STATUS_AMPS_LOCK_K2_E5_SHIFT                                                  8
+  #define ETH_RSFEC_REG_RS_FEC_STATUS_FEC_ALIGN_STATUS_K2_E5                                                 (0x1<<14) // Indicates, when 1 that the RS-FEC receiver has locked on incoming data and deskew completed.
+  #define ETH_RSFEC_REG_RS_FEC_STATUS_FEC_ALIGN_STATUS_K2_E5_SHIFT                                           14
+  #define ETH_RSFEC_REG_RS_FEC_STATUS_PCS_ALIGN_STATUS_K2_E5                                                 (0x1<<15) // Always 1.
+  #define ETH_RSFEC_REG_RS_FEC_STATUS_PCS_ALIGN_STATUS_K2_E5_SHIFT                                           15
+#define ETH_RSFEC_REG_RS_FEC_CCW_LO_K2_E5                                                                    0x000008UL //Access:R    DataWidth:0x20   // Counts number of corrected FEC codewords lower 16-bits; None roll-over when upper 16-bits are 0xffff.
+  #define ETH_RSFEC_REG_RS_FEC_CCW_LO_COUNTER_K2_E5                                                          (0xffff<<0) // Counts number of corrected FEC codewords lower 16-bits; Must be read before upper 16-bits; None roll-over when upper 16-bits are 0xffff
+  #define ETH_RSFEC_REG_RS_FEC_CCW_LO_COUNTER_K2_E5_SHIFT                                                    0
+#define ETH_RSFEC_REG_RS_FEC_CCW_HI_K2_E5                                                                    0x00000cUL //Access:R    DataWidth:0x20   // Counts number of corrected FEC codewords upper 16-bits; Clears on read; None roll-over.
+  #define ETH_RSFEC_REG_RS_FEC_CCW_HI_COUNTER_HI_K2_E5                                                       (0xffff<<0) // Counts number of corrected FEC codewords upper 16-bits; None roll-over; Clears when read.
+  #define ETH_RSFEC_REG_RS_FEC_CCW_HI_COUNTER_HI_K2_E5_SHIFT                                                 0
+#define ETH_RSFEC_REG_RS_FEC_NCCW_LO_K2_E5                                                                   0x000010UL //Access:R    DataWidth:0x20   // Counts number of uncorrected FEC codewords lower 16-bits; None roll-over when upper 16-bits are 0xffff.
+  #define ETH_RSFEC_REG_RS_FEC_NCCW_LO_COUNTER_K2_E5                                                         (0xffff<<0) // Counts number of uncorrected FEC codewords lower 16-bits; Must be read before upper 16-bits; None roll-over when upper 16-bits are 0xffff
+  #define ETH_RSFEC_REG_RS_FEC_NCCW_LO_COUNTER_K2_E5_SHIFT                                                   0
+#define ETH_RSFEC_REG_RS_FEC_NCCW_HI_K2_E5                                                                   0x000014UL //Access:R    DataWidth:0x20   // Counts number of uncorrected FEC codewords upper 16-bits; Clears on read; None roll-over.
+  #define ETH_RSFEC_REG_RS_FEC_NCCW_HI_COUNTER_HI_K2_E5                                                      (0xffff<<0) // Counts number of uncorrected FEC codewords upper 16-bits; None roll-over; Clears when read.
+  #define ETH_RSFEC_REG_RS_FEC_NCCW_HI_COUNTER_HI_K2_E5_SHIFT                                                0
+#define ETH_RSFEC_REG_RS_FEC_LANEMAP_K2_E5                                                                   0x000018UL //Access:R    DataWidth:0x20   // FEC alignment status and lane mappings.
+  #define ETH_RSFEC_REG_RS_FEC_LANEMAP_PMA_LANE_0_K2_E5                                                      (0x3<<0) // FEC lane mapped to PMA lane 0.
+  #define ETH_RSFEC_REG_RS_FEC_LANEMAP_PMA_LANE_0_K2_E5_SHIFT                                                0
+  #define ETH_RSFEC_REG_RS_FEC_LANEMAP_PMA_LANE_1_K2_E5                                                      (0x3<<2) // FEC lane mapped to PMA lane 1.
+  #define ETH_RSFEC_REG_RS_FEC_LANEMAP_PMA_LANE_1_K2_E5_SHIFT                                                2
+  #define ETH_RSFEC_REG_RS_FEC_LANEMAP_PMA_LANE_2_K2_E5                                                      (0x3<<4) // FEC lane mapped to PMA lane 2.
+  #define ETH_RSFEC_REG_RS_FEC_LANEMAP_PMA_LANE_2_K2_E5_SHIFT                                                4
+  #define ETH_RSFEC_REG_RS_FEC_LANEMAP_PMA_LANE_3_K2_E5                                                      (0x3<<6) // FEC lane mapped to PMA lane 3.
+  #define ETH_RSFEC_REG_RS_FEC_LANEMAP_PMA_LANE_3_K2_E5_SHIFT                                                6
+#define ETH_RSFEC_REG_RS_FEC_SYMBLERR0_LO_K2_E5                                                              0x000028UL //Access:R    DataWidth:0x20   // Counts number of (corrected) 10-bit symbol errors found in lane 0; None roll-over when upper 16-bits are 0xffff.
+  #define ETH_RSFEC_REG_RS_FEC_SYMBLERR0_LO_SYMBOL_ERRORS_K2_E5                                              (0xffff<<0) // Counts number of (corrected) 10-bit symbol errors found in lane 0 for correctable codewords only; Lower 16-bit of counter; Must be read first; None roll-over when upper word is 0xffff.
+  #define ETH_RSFEC_REG_RS_FEC_SYMBLERR0_LO_SYMBOL_ERRORS_K2_E5_SHIFT                                        0
+#define ETH_RSFEC_REG_RS_FEC_SYMBLERR0_HI_K2_E5                                                              0x00002cUL //Access:R    DataWidth:0x20   // Upper 16-bit of counter (with above register); Clears on read; None roll-over.
+  #define ETH_RSFEC_REG_RS_FEC_SYMBLERR0_HI_SYMBOL_ERROR_HI_K2_E5                                            (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 0; Clears on read; None roll-over.
+  #define ETH_RSFEC_REG_RS_FEC_SYMBLERR0_HI_SYMBOL_ERROR_HI_K2_E5_SHIFT                                      0
+#define ETH_RSFEC_REG_RS_FEC_SYMBLERR1_LO_K2_E5                                                              0x000030UL //Access:R    DataWidth:0x20   // Counts number of (corrected) 10-bit symbol errors found in lane 1; None roll-over when upper 16-bits are 0xffff.
+  #define ETH_RSFEC_REG_RS_FEC_SYMBLERR1_LO_SYMBOL_ERRORS_K2_E5                                              (0xffff<<0) // Counts number of (corrected) 10-bit symbol errors found in lane 1 for correctable codewords only; Lower 16-bit of counter; Must be read first; None roll-over when upper word is 0xffff.
+  #define ETH_RSFEC_REG_RS_FEC_SYMBLERR1_LO_SYMBOL_ERRORS_K2_E5_SHIFT                                        0
+#define ETH_RSFEC_REG_RS_FEC_SYMBLERR1_HI_K2_E5                                                              0x000034UL //Access:R    DataWidth:0x20   // Upper 16-bit of counter (with above register); Clears on read; None roll-over.
+  #define ETH_RSFEC_REG_RS_FEC_SYMBLERR1_HI_SYMBOL_ERROR_HI_K2_E5                                            (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 1; Clears on read; None roll-over.
+  #define ETH_RSFEC_REG_RS_FEC_SYMBLERR1_HI_SYMBOL_ERROR_HI_K2_E5_SHIFT                                      0
+#define ETH_RSFEC_REG_RS_FEC_SYMBLERR2_LO_K2_E5                                                              0x000038UL //Access:R    DataWidth:0x20   // Counts number of (corrected) 10-bit symbol errors found in lane 2; None roll-over when upper 16-bits are 0xffff.
+  #define ETH_RSFEC_REG_RS_FEC_SYMBLERR2_LO_SYMBOL_ERRORS_K2_E5                                              (0xffff<<0) // Counts number of (corrected) 10-bit symbol errors found in lane 2 for correctable codewords only; Lower 16-bit of counter; Must be read first; None roll-over when upper word is 0xffff.
+  #define ETH_RSFEC_REG_RS_FEC_SYMBLERR2_LO_SYMBOL_ERRORS_K2_E5_SHIFT                                        0
+#define ETH_RSFEC_REG_RS_FEC_SYMBLERR2_HI_K2_E5                                                              0x00003cUL //Access:R    DataWidth:0x20   // Upper 16-bit of counter (with above register); Clears on read; None roll-over.
+  #define ETH_RSFEC_REG_RS_FEC_SYMBLERR2_HI_SYMBOL_ERROR_HI_K2_E5                                            (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 2; Clears on read; None roll-over.
+  #define ETH_RSFEC_REG_RS_FEC_SYMBLERR2_HI_SYMBOL_ERROR_HI_K2_E5_SHIFT                                      0
+#define ETH_RSFEC_REG_RS_FEC_SYMBLERR3_LO_K2_E5                                                              0x000040UL //Access:R    DataWidth:0x20   // Counts number of (corrected) 10-bit symbol errors found in lane 3; None roll-over when upper 16-bits are 0xffff.
+  #define ETH_RSFEC_REG_RS_FEC_SYMBLERR3_LO_SYMBOL_ERRORS_K2_E5                                              (0xffff<<0) // Counts number of (corrected) 10-bit symbol errors found in lane 3 for correctable codewords only; Lower 16-bit of counter; Must be read first; None roll-over when upper word is 0xffff.
+  #define ETH_RSFEC_REG_RS_FEC_SYMBLERR3_LO_SYMBOL_ERRORS_K2_E5_SHIFT                                        0
+#define ETH_RSFEC_REG_RS_FEC_SYMBLERR3_HI_K2_E5                                                              0x000044UL //Access:R    DataWidth:0x20   // Upper 16 bit of counter (with above register); Clears on read; None roll-over.
+  #define ETH_RSFEC_REG_RS_FEC_SYMBLERR3_HI_SYMBOL_ERROR_HI_K2_E5                                            (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 3; Clears on read; None roll-over.
+  #define ETH_RSFEC_REG_RS_FEC_SYMBLERR3_HI_SYMBOL_ERROR_HI_K2_E5_SHIFT                                      0
+#define ETH_RSFEC_REG_RS_FEC_VENDOR_CONTROL_K2_E5                                                            0x000200UL //Access:RW   DataWidth:0x20   // Additional control to enable RS-FEC operation.
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_CONTROL_RS_FEC_ENABLE_K2_E5                                            (0x1<<2) // When 1, enable RSFEC datapath instead PCS MLD;  When 0, use normal PCS MLD datapath (default).
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_CONTROL_RS_FEC_ENABLE_K2_E5_SHIFT                                      2
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_CONTROL_RS_FEC_STATUS_K2_E5                                            (0x1<<15) // Indicates the operatyional outcome of the (above) enable bit control; When 1 = FEC enabled and 0 = disabled.
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_CONTROL_RS_FEC_STATUS_K2_E5_SHIFT                                      15
+#define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_K2_E5                                                              0x000204UL //Access:R    DataWidth:0x20   // Implementation specific information that may be useful for debugging link problems; Clears on read.
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_AMPS_LOCK_K2_E5                                                  (0xf<<0) // Per PMA lane FEC synchronization status; Bit 0=lane 0 up to Bit 3 = lane 3; Latched high; Clear on read.
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_AMPS_LOCK_K2_E5_SHIFT                                            0
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_FEC_ALIGN_STATUS_LH_K2_E5                                        (0x1<<4) // FEC alignment status; Latched high; Clear on read.
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_FEC_ALIGN_STATUS_LH_K2_E5_SHIFT                                  4
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_MARKER_CHECK_RESTART_K2_E5                                       (0x1<<5) // The marker_check function (PCS sublayer) caused an alignment restart to the FEC; Latched high; Clear on read.
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_MARKER_CHECK_RESTART_K2_E5_SHIFT                                 5
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_RX_DATAPATH_RESTART_K2_E5                                        (0x1<<6) // RX datapath (sync) reset occured; Latched high; Clear on read.
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_RX_DATAPATH_RESTART_K2_E5_SHIFT                                  6
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_TX_DATAPATH_RESTART_K2_E5                                        (0x1<<7) // TX datapath (sync) reset occured; Latched high; Clear on read.
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_TX_DATAPATH_RESTART_K2_E5_SHIFT                                  7
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_RX_DP_OVERFLOW_K2_E5                                             (0x1<<8) // RX datapath 4x66 pacing fifo overflow fatal error; Latched high; Clear on read.
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_RX_DP_OVERFLOW_K2_E5_SHIFT                                       8
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_TX_DP_OVERFLOW_K2_E5                                             (0x1<<9) // TX datapath 4x66 input fifo overflow fatal error; Latched high; Clear on read.
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_TX_DP_OVERFLOW_K2_E5_SHIFT                                       9
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_FEC_ALIGN_STATUS_LL_K2_E5                                        (0x1<<10) // FEC alignment status; Latched high; Sets on read.
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_FEC_ALIGN_STATUS_LL_K2_E5_SHIFT                                  10
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_DESKEW_EMPTY_K2_E5                                               (0xf<<12) // Real-time indication from FEC deskew FIFO per lane; bit 12 = lane 0 upto bit 15 = lane3.
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_DESKEW_EMPTY_K2_E5_SHIFT                                         12
+#define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO2_K2_E5                                                              0x000208UL //Access:R    DataWidth:0x20   // Implementation specific status information; Clears on read.
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO2_AMPS_LOCK_K2_E5                                                  (0xf<<0) // Per PMA lane FEC synchronization status; Realtime updates;  Bit  0 = lane 0 upto bit 3 = lane 3; Clears on read;
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO2_AMPS_LOCK_K2_E5_SHIFT                                            0
+#define ETH_RSFEC_REG_RS_FEC_VENDOR_REVISION_K2_E5                                                           0x00020cUL //Access:R    DataWidth:0x20   // A version information taken from package file parameter FEC91_DEV_VERSION.
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_REVISION_REVISION_K2_E5                                                (0xffff<<0) // A version information taken from package file parameter FEC91_DEV_VERSION.
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_REVISION_REVISION_K2_E5_SHIFT                                          0
+#define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTKEY_K2_E5                                                         0x000210UL //Access:RW   DataWidth:0x20   // Bits 7:0; Must be written with the 8-bit value of 0x57 to enable RS-FEC transmit test error injection capability.
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTKEY_TEST_KEY_K2_E5                                              (0xff<<0) // Bits 7:0; Must be written with 8-bit value 0x57 to enable RS-FEC transmit test error injection capability.
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTKEY_TEST_KEY_K2_E5_SHIFT                                        0
+#define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTSYMBOLS_K2_E5                                                     0x000214UL //Access:RW   DataWidth:0x20   // Bits 15:0. One bit per 10-bit Symbol; Each bit is applied to corresponding 10B symbol after FEC encoding.
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTSYMBOLS_TEST_SYMBOLS_K2_E5                                      (0xffff<<0) // Bits 15:0. One bit per 10-bit Symbol; When a bit is 1 the test pattern is applied to the corresponding 10B symbol after the FEC encoding.
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTSYMBOLS_TEST_SYMBOLS_K2_E5_SHIFT                                0
+#define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTPATTERN_K2_E5                                                     0x000218UL //Access:RW   DataWidth:0x20   // Bits 9:0; A 10-bit value which XORed with a 10B symbol FEC encoder to manipulate transmitted datastream.
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTPATTERN_TEST_PATTERN_K2_E5                                      (0x3ff<<0) // A 10-bit value which will be XORed with a 10B symbol after the FEC encoder to manipulate the transmitted datastream.
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTPATTERN_TEST_PATTERN_K2_E5_SHIFT                                0
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTPATTERN_OVERWRITE_K2_E5                                         (0x1<<10) // If the bit is set the 10B symbol is replaced by the pattern instead using XOR.
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTPATTERN_OVERWRITE_K2_E5_SHIFT                                   10
+#define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTTRIGGER_K2_E5                                                     0x00021cUL //Access:RW   DataWidth:0x20   // Enable register to control the triggers with the error insertion; Bit 0 clears on operation complete.
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTTRIGGER_TEST_TRIGGER_K2_E5                                      (0x1<<0) // For bit 0 only, when written with 1 triggers the error insertion (on one word of 16 symbols); This bit clears automatically.
+  #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTTRIGGER_TEST_TRIGGER_K2_E5_SHIFT                                0
+#define ETH_PCS1G_REG_CONTROL_K2_E5                                                                          0x000000UL //Access:RW   DataWidth:0x20   // Control register
+  #define ETH_PCS1G_REG_CONTROL_SPEED_6_K2_E5                                                                (0x1<<6) // Speed Selection Indication; always 1
+  #define ETH_PCS1G_REG_CONTROL_SPEED_6_K2_E5_SHIFT                                                          6
+  #define ETH_PCS1G_REG_CONTROL_DUPLEX_K2_E5                                                                 (0x1<<8) // Indicate full-duplex operation; always 1
+  #define ETH_PCS1G_REG_CONTROL_DUPLEX_K2_E5_SHIFT                                                           8
+  #define ETH_PCS1G_REG_CONTROL_ANRESTART_K2_E5                                                              (0x1<<9) // Restart Autonegotiation
+  #define ETH_PCS1G_REG_CONTROL_ANRESTART_K2_E5_SHIFT                                                        9
+  #define ETH_PCS1G_REG_CONTROL_ISOLATE_K2_E5                                                                (0x1<<10) // Set PCS isolate mode; Controls toplevel pin only, no internal function.
+  #define ETH_PCS1G_REG_CONTROL_ISOLATE_K2_E5_SHIFT                                                          10
+  #define ETH_PCS1G_REG_CONTROL_POWERDOWN_K2_E5                                                              (0x1<<11) // Enable powerdown state, if supported.
+  #define ETH_PCS1G_REG_CONTROL_POWERDOWN_K2_E5_SHIFT                                                        11
+  #define ETH_PCS1G_REG_CONTROL_ANENABLE_K2_E5                                                               (0x1<<12) // Autonegotiation enable
+  #define ETH_PCS1G_REG_CONTROL_ANENABLE_K2_E5_SHIFT                                                         12
+  #define ETH_PCS1G_REG_CONTROL_SPEED_13_K2_E5                                                               (0x1<<13) // Speed Selection Indication; always 0
+  #define ETH_PCS1G_REG_CONTROL_SPEED_13_K2_E5_SHIFT                                                         13
+  #define ETH_PCS1G_REG_CONTROL_LOOPBACK_K2_E5                                                               (0x1<<14) // Enable loopback
+  #define ETH_PCS1G_REG_CONTROL_LOOPBACK_K2_E5_SHIFT                                                         14
+  #define ETH_PCS1G_REG_CONTROL_RESET_K2_E5                                                                  (0x1<<15) // PCS soft-reset command; self-clearing
+  #define ETH_PCS1G_REG_CONTROL_RESET_K2_E5_SHIFT                                                            15
+#define ETH_PCS1G_REG_STATUS_K2_E5                                                                           0x000004UL //Access:R    DataWidth:0x20   // Status indications
+  #define ETH_PCS1G_REG_STATUS_EXTDCAPABILITY_K2_E5                                                          (0x1<<0) // Indicate extended register support; always 1
+  #define ETH_PCS1G_REG_STATUS_EXTDCAPABILITY_K2_E5_SHIFT                                                    0
+  #define ETH_PCS1G_REG_STATUS_LINKSTATUS_K2_E5                                                              (0x1<<2) // Indicate link status; latch-low
+  #define ETH_PCS1G_REG_STATUS_LINKSTATUS_K2_E5_SHIFT                                                        2
+  #define ETH_PCS1G_REG_STATUS_ANEGABILITY_K2_E5                                                             (0x1<<3) // Autonegotiation ability; always 1
+  #define ETH_PCS1G_REG_STATUS_ANEGABILITY_K2_E5_SHIFT                                                       3
+  #define ETH_PCS1G_REG_STATUS_ANEGCOMPLETE_K2_E5                                                            (0x1<<5) // Autonegotiation completed indication
+  #define ETH_PCS1G_REG_STATUS_ANEGCOMPLETE_K2_E5_SHIFT                                                      5
+#define ETH_PCS1G_REG_PHY_ID_0_K2_E5                                                                         0x000008UL //Access:R    DataWidth:0x20   // PHY Identifier lower 16 bits
+  #define ETH_PCS1G_REG_PHY_ID_0_PHYID_K2_E5                                                                 (0xffff<<0) // PHY Identifier from package file parameter PHY_IDENTIFIER lower 16 bits.
+  #define ETH_PCS1G_REG_PHY_ID_0_PHYID_K2_E5_SHIFT                                                           0
+#define ETH_PCS1G_REG_PHY_ID_1_K2_E5                                                                         0x00000cUL //Access:R    DataWidth:0x20   // PHY Identifier upper 16 bits
+  #define ETH_PCS1G_REG_PHY_ID_1_PHYID_K2_E5                                                                 (0xffff<<0) // PHY Identifier from package file parameter PHY_IDENTIFIER upper 16 bits.
+  #define ETH_PCS1G_REG_PHY_ID_1_PHYID_K2_E5_SHIFT                                                           0
+#define ETH_PCS1G_REG_DEV_ABILITY_K2_E5                                                                      0x000010UL //Access:RW   DataWidth:0x20   // Local Device Abilities for Autonegotiation. Contents differs for 1000Base-X or SGMII mode.
+  #define ETH_PCS1G_REG_DEV_ABILITY_ABILITY_RSV05_K2_E5                                                      (0x1f<<0) // reserved; SGMII:=set to 1 to indicate SGMII to PHY
+  #define ETH_PCS1G_REG_DEV_ABILITY_ABILITY_RSV05_K2_E5_SHIFT                                                0
+  #define ETH_PCS1G_REG_DEV_ABILITY_FD_K2_E5                                                                 (0x1<<5) // Indicate full-duplex support; SGMII:=reserved
+  #define ETH_PCS1G_REG_DEV_ABILITY_FD_K2_E5_SHIFT                                                           5
+  #define ETH_PCS1G_REG_DEV_ABILITY_HD_K2_E5                                                                 (0x1<<6) // Indicate half-duplex support; SGMII:=reserved
+  #define ETH_PCS1G_REG_DEV_ABILITY_HD_K2_E5_SHIFT                                                           6
+  #define ETH_PCS1G_REG_DEV_ABILITY_PS1_K2_E5                                                                (0x1<<7) // Pause Support 1; SGMII:=reserved
+  #define ETH_PCS1G_REG_DEV_ABILITY_PS1_K2_E5_SHIFT                                                          7
+  #define ETH_PCS1G_REG_DEV_ABILITY_PS2_K2_E5                                                                (0x1<<8) // Pause Support 2; SGMII:=EEE clock stop enable to PHY
+  #define ETH_PCS1G_REG_DEV_ABILITY_PS2_K2_E5_SHIFT                                                          8
+  #define ETH_PCS1G_REG_DEV_ABILITY_ABILITY_RSV9_K2_E5                                                       (0x7<<9) // reserved; SGMII:=reserved
+  #define ETH_PCS1G_REG_DEV_ABILITY_ABILITY_RSV9_K2_E5_SHIFT                                                 9
+  #define ETH_PCS1G_REG_DEV_ABILITY_RF1_K2_E5                                                                (0x1<<12) // Remote fault 1; SGMII:=reserved
+  #define ETH_PCS1G_REG_DEV_ABILITY_RF1_K2_E5_SHIFT                                                          12
+  #define ETH_PCS1G_REG_DEV_ABILITY_RF2_K2_E5                                                                (0x1<<13) // Remote fault 2; SGMII:=reserved
+  #define ETH_PCS1G_REG_DEV_ABILITY_RF2_K2_E5_SHIFT                                                          13
+  #define ETH_PCS1G_REG_DEV_ABILITY_ACK_K2_E5                                                                (0x1<<14) // Acknowledge during autonegotiation
+  #define ETH_PCS1G_REG_DEV_ABILITY_ACK_K2_E5_SHIFT                                                          14
+  #define ETH_PCS1G_REG_DEV_ABILITY_NP_K2_E5                                                                 (0x1<<15) // Next Page support; SGMII:=reserved
+  #define ETH_PCS1G_REG_DEV_ABILITY_NP_K2_E5_SHIFT                                                           15
+#define ETH_PCS1G_REG_PARTNER_ABILITY_K2_E5                                                                  0x000014UL //Access:R    DataWidth:0x20   // Received Abilities during Autonegotiation. Contents differ depending on 1000Base-X or SGMII mode.
+  #define ETH_PCS1G_REG_PARTNER_ABILITY_PABILITY_RSV05_K2_E5                                                 (0x1f<<0) // reserved; SGMII:=1
+  #define ETH_PCS1G_REG_PARTNER_ABILITY_PABILITY_RSV05_K2_E5_SHIFT                                           0
+  #define ETH_PCS1G_REG_PARTNER_ABILITY_FD_K2_E5                                                             (0x1<<5) // Indicate full-duplex support; SGMII:=reserved
+  #define ETH_PCS1G_REG_PARTNER_ABILITY_FD_K2_E5_SHIFT                                                       5
+  #define ETH_PCS1G_REG_PARTNER_ABILITY_HD_K2_E5                                                             (0x1<<6) // Indicate half-duplex support; SGMII:=reserved
+  #define ETH_PCS1G_REG_PARTNER_ABILITY_HD_K2_E5_SHIFT                                                       6
+  #define ETH_PCS1G_REG_PARTNER_ABILITY_PS1_K2_E5                                                            (0x1<<7) // Pause Support 1; SGMII:=reserved
+  #define ETH_PCS1G_REG_PARTNER_ABILITY_PS1_K2_E5_SHIFT                                                      7
+  #define ETH_PCS1G_REG_PARTNER_ABILITY_PS2_K2_E5                                                            (0x1<<8) // Pause Support 2; SGMII:=EEE clock stop capability from PHY
+  #define ETH_PCS1G_REG_PARTNER_ABILITY_PS2_K2_E5_SHIFT                                                      8
+  #define ETH_PCS1G_REG_PARTNER_ABILITY_PABILITY_RSV9_K2_E5                                                  (0x1<<9) // reserved; SGMII:=EEE capability from PHY
+  #define ETH_PCS1G_REG_PARTNER_ABILITY_PABILITY_RSV9_K2_E5_SHIFT                                            9
+  #define ETH_PCS1G_REG_PARTNER_ABILITY_PABILITY_RSV10_K2_E5                                                 (0x3<<10) // reserved; SGMII:=Copper Speed indication from PHY
+  #define ETH_PCS1G_REG_PARTNER_ABILITY_PABILITY_RSV10_K2_E5_SHIFT                                           10
+  #define ETH_PCS1G_REG_PARTNER_ABILITY_RF1_K2_E5                                                            (0x1<<12) // Remote fault 1; SGMII:=Copper Duplex status from PHY
+  #define ETH_PCS1G_REG_PARTNER_ABILITY_RF1_K2_E5_SHIFT                                                      12
+  #define ETH_PCS1G_REG_PARTNER_ABILITY_RF2_K2_E5                                                            (0x1<<13) // Remote fault 2; SGMII:=reserved
+  #define ETH_PCS1G_REG_PARTNER_ABILITY_RF2_K2_E5_SHIFT                                                      13
+  #define ETH_PCS1G_REG_PARTNER_ABILITY_ACK_K2_E5                                                            (0x1<<14) // Acknowledge during autonegotiation
+  #define ETH_PCS1G_REG_PARTNER_ABILITY_ACK_K2_E5_SHIFT                                                      14
+  #define ETH_PCS1G_REG_PARTNER_ABILITY_NP_K2_E5                                                             (0x1<<15) // Next Page support; SGMII:=Copper Link Status from PHY
+  #define ETH_PCS1G_REG_PARTNER_ABILITY_NP_K2_E5_SHIFT                                                       15
+#define ETH_PCS1G_REG_AN_EXPANSION_K2_E5                                                                     0x000018UL //Access:R    DataWidth:0x20   // Autonegotiation Expansion Register
+  #define ETH_PCS1G_REG_AN_EXPANSION_PAGERECEIVED_K2_E5                                                      (0x1<<1) // Autoneg page received indication; latch-high
+  #define ETH_PCS1G_REG_AN_EXPANSION_PAGERECEIVED_K2_E5_SHIFT                                                1
+  #define ETH_PCS1G_REG_AN_EXPANSION_NEXTPAGEABLE_K2_E5                                                      (0x1<<2) // Indicate PCS supports next page exchange for autonegotiation
+  #define ETH_PCS1G_REG_AN_EXPANSION_NEXTPAGEABLE_K2_E5_SHIFT                                                2
+#define ETH_PCS1G_REG_NP_TX_K2_E5                                                                            0x00001cUL //Access:RW   DataWidth:0x20   // Next Page data to transmit
+  #define ETH_PCS1G_REG_NP_TX_DATA_K2_E5                                                                     (0x7ff<<0) // Next Page data
+  #define ETH_PCS1G_REG_NP_TX_DATA_K2_E5_SHIFT                                                               0
+  #define ETH_PCS1G_REG_NP_TX_TOGGLE_K2_E5                                                                   (0x1<<11) // Next Page toggle handshaking bit
+  #define ETH_PCS1G_REG_NP_TX_TOGGLE_K2_E5_SHIFT                                                             11
+  #define ETH_PCS1G_REG_NP_TX_ACK2_K2_E5                                                                     (0x1<<12) // Next Page data acknowledge indication
+  #define ETH_PCS1G_REG_NP_TX_ACK2_K2_E5_SHIFT                                                               12
+  #define ETH_PCS1G_REG_NP_TX_MP_K2_E5                                                                       (0x1<<13) // Message Next Page type identification
+  #define ETH_PCS1G_REG_NP_TX_MP_K2_E5_SHIFT                                                                 13
+  #define ETH_PCS1G_REG_NP_TX_ACK_K2_E5                                                                      (0x1<<14) // Acknowledge during page exchange
+  #define ETH_PCS1G_REG_NP_TX_ACK_K2_E5_SHIFT                                                                14
+  #define ETH_PCS1G_REG_NP_TX_NP_K2_E5                                                                       (0x1<<15) // Next Pages to follow indication
+  #define ETH_PCS1G_REG_NP_TX_NP_K2_E5_SHIFT                                                                 15
+#define ETH_PCS1G_REG_LP_NP_RX_K2_E5                                                                         0x000020UL //Access:R    DataWidth:0x20   // Received Next Page data from link partner
+  #define ETH_PCS1G_REG_LP_NP_RX_DATA_K2_E5                                                                  (0x7ff<<0) // Next Page data
+  #define ETH_PCS1G_REG_LP_NP_RX_DATA_K2_E5_SHIFT                                                            0
+  #define ETH_PCS1G_REG_LP_NP_RX_TOGGLE_K2_E5                                                                (0x1<<11) // Next Page toggle handshaking bit
+  #define ETH_PCS1G_REG_LP_NP_RX_TOGGLE_K2_E5_SHIFT                                                          11
+  #define ETH_PCS1G_REG_LP_NP_RX_ACK2_K2_E5                                                                  (0x1<<12) // Next Page data acknowledge indication
+  #define ETH_PCS1G_REG_LP_NP_RX_ACK2_K2_E5_SHIFT                                                            12
+  #define ETH_PCS1G_REG_LP_NP_RX_MP_K2_E5                                                                    (0x1<<13) // Message Next Page type identification
+  #define ETH_PCS1G_REG_LP_NP_RX_MP_K2_E5_SHIFT                                                              13
+  #define ETH_PCS1G_REG_LP_NP_RX_ACK_K2_E5                                                                   (0x1<<14) // Acknowledge during page exchange
+  #define ETH_PCS1G_REG_LP_NP_RX_ACK_K2_E5_SHIFT                                                             14
+  #define ETH_PCS1G_REG_LP_NP_RX_NP_K2_E5                                                                    (0x1<<15) // Next Pages to follow indication
+  #define ETH_PCS1G_REG_LP_NP_RX_NP_K2_E5_SHIFT                                                              15
+#define ETH_PCS1G_REG_SCRATCH_K2_E5                                                                          0x000040UL //Access:RW   DataWidth:0x20   // General Purpose Test register
+  #define ETH_PCS1G_REG_SCRATCH_SCRATCH_K2_E5                                                                (0xffff<<0) // Arbitrary value for read/write test
+  #define ETH_PCS1G_REG_SCRATCH_SCRATCH_K2_E5_SHIFT                                                          0
+#define ETH_PCS1G_REG_REV_K2_E5                                                                              0x000044UL //Access:R    DataWidth:0x20   // Core Revision
+  #define ETH_PCS1G_REG_REV_REVISION_K2_E5                                                                   (0xffff<<0) // from package parameter DEV_VERSION
+  #define ETH_PCS1G_REG_REV_REVISION_K2_E5_SHIFT                                                             0
+#define ETH_PCS1G_REG_LINK_TIMER_0_K2_E5                                                                     0x000048UL //Access:RW   DataWidth:0x20   // Autonegotiation link timer lower 16 bits
+  #define ETH_PCS1G_REG_LINK_TIMER_0_TIMER0_K2_E5                                                            (0x1<<0) // Bit 0 of link timer value; not writeable and always 0
+  #define ETH_PCS1G_REG_LINK_TIMER_0_TIMER0_K2_E5_SHIFT                                                      0
+  #define ETH_PCS1G_REG_LINK_TIMER_0_TIMER15_1_K2_E5                                                         (0x7fff<<1) // Bits 15:1 of link timer value
+  #define ETH_PCS1G_REG_LINK_TIMER_0_TIMER15_1_K2_E5_SHIFT                                                   1
+#define ETH_PCS1G_REG_LINK_TIMER_1_K2_E5                                                                     0x00004cUL //Access:RW   DataWidth:0x20   // Autonegotiation link timer uppest 5 bits
+  #define ETH_PCS1G_REG_LINK_TIMER_1_TIMER20_16_K2_E5                                                        (0x1f<<0) // Link timer uppest 5 bits of 21bit timer
+  #define ETH_PCS1G_REG_LINK_TIMER_1_TIMER20_16_K2_E5_SHIFT                                                  0
+#define ETH_PCS1G_REG_IF_MODE_K2_E5                                                                          0x000050UL //Access:RW   DataWidth:0x20   // SGMII Mode Control
+  #define ETH_PCS1G_REG_IF_MODE_SGMII_ENA_K2_E5                                                              (0x1<<0) // Enable SGMII mode
+  #define ETH_PCS1G_REG_IF_MODE_SGMII_ENA_K2_E5_SHIFT                                                        0
+  #define ETH_PCS1G_REG_IF_MODE_USE_SGMII_AN_K2_E5                                                           (0x1<<1) // Use the SGMII autonegotiation results to set SGMII speed
+  #define ETH_PCS1G_REG_IF_MODE_USE_SGMII_AN_K2_E5_SHIFT                                                     1
+  #define ETH_PCS1G_REG_IF_MODE_SGMII_SPEED_K2_E5                                                            (0x3<<2) // Set SGMII speed when not using autonegotiation
+  #define ETH_PCS1G_REG_IF_MODE_SGMII_SPEED_K2_E5_SHIFT                                                      2
+  #define ETH_PCS1G_REG_IF_MODE_SGMII_DUPLEX_K2_E5                                                           (0x1<<4) // Set SGMII half-duplex mode when not using autonegotiation
+  #define ETH_PCS1G_REG_IF_MODE_SGMII_DUPLEX_K2_E5_SHIFT                                                     4
+  #define ETH_PCS1G_REG_IF_MODE_IFMODE_RSV5_K2_E5                                                            (0x1<<5) // reserved; writeable for backward compatibility; write 0 always
+  #define ETH_PCS1G_REG_IF_MODE_IFMODE_RSV5_K2_E5_SHIFT                                                      5
+#define ETH_PCS1G_REG_DECODE_ERRORS_K2_E5                                                                    0x000054UL //Access:RW   DataWidth:0x20   // 10B decoder error counter for test/debug; May not exist in all Core Variants;
+  #define ETH_PCS1G_REG_DECODE_ERRORS_ERRORS_K2_E5                                                           (0xffff<<0) // RX 10B/8B code errors; May not be supported in all Core variants; Counter is not accurate and intended only to be of help during test/debug; Clears when writing CONTROL.15 or CONTROL.10 with 1.
+  #define ETH_PCS1G_REG_DECODE_ERRORS_ERRORS_K2_E5_SHIFT                                                     0
+#define ETH_PCS10_50G_REG_CONTROL1_K2_E5                                                                     0x000000UL //Access:RW   DataWidth:0x20   // PCS Control.
+  #define ETH_PCS10_50G_REG_CONTROL1_SPEED_SELECTION_K2_E5                                                   (0xf<<2) // 0011 = 40 Gb/s; 0000 = 10Gb/s.
+  #define ETH_PCS10_50G_REG_CONTROL1_SPEED_SELECTION_K2_E5_SHIFT                                             2
+  #define ETH_PCS10_50G_REG_CONTROL1_SPEED_ALWAYS1_K2_E5                                                     (0x1<<6) // Always 1.
+  #define ETH_PCS10_50G_REG_CONTROL1_SPEED_ALWAYS1_K2_E5_SHIFT                                               6
+  #define ETH_PCS10_50G_REG_CONTROL1_LOW_POWER_K2_E5                                                         (0x1<<11) // 0=normal operation (Always 0).
+  #define ETH_PCS10_50G_REG_CONTROL1_LOW_POWER_K2_E5_SHIFT                                                   11
+  #define ETH_PCS10_50G_REG_CONTROL1_SPEED_SELECT_ALWAYS1_K2_E5                                              (0x1<<13) // Always 1.
+  #define ETH_PCS10_50G_REG_CONTROL1_SPEED_SELECT_ALWAYS1_K2_E5_SHIFT                                        13
+  #define ETH_PCS10_50G_REG_CONTROL1_LOOPBACK_K2_E5                                                          (0x1<<14) // 1=Enable loopback, 0=disable loopback.
+  #define ETH_PCS10_50G_REG_CONTROL1_LOOPBACK_K2_E5_SHIFT                                                    14
+  #define ETH_PCS10_50G_REG_CONTROL1_RESET_K2_E5                                                             (0x1<<15) // 1=PCS reset, 0=normal; Self clearing.
+  #define ETH_PCS10_50G_REG_CONTROL1_RESET_K2_E5_SHIFT                                                       15
+#define ETH_PCS10_50G_REG_STATUS1_K2_E5                                                                      0x000004UL //Access:R    DataWidth:0x20   // PCS Status.
+  #define ETH_PCS10_50G_REG_STATUS1_LOW_POWER_ABILITY_K2_E5                                                  (0x1<<1) // Set to 1 to indicate that the PCS implements a low power mode.
+  #define ETH_PCS10_50G_REG_STATUS1_LOW_POWER_ABILITY_K2_E5_SHIFT                                            1
+  #define ETH_PCS10_50G_REG_STATUS1_PCS_RECEIVE_LINK_K2_E5                                                   (0x1<<2) // When 1, indicates PCS receive link up; When 0, indicates PCS receive link is or was down (latching low).
+  #define ETH_PCS10_50G_REG_STATUS1_PCS_RECEIVE_LINK_K2_E5_SHIFT                                             2
+  #define ETH_PCS10_50G_REG_STATUS1_FAULT_K2_E5                                                              (0x1<<7) // When 1, indicates a fault condition idetected; When 0, indicates that no fault condition is detected.
+  #define ETH_PCS10_50G_REG_STATUS1_FAULT_K2_E5_SHIFT                                                        7
+  #define ETH_PCS10_50G_REG_STATUS1_RX_LPI_ACTIVE_K2_E5                                                      (0x1<<8) // 1: receive is currently in LPI state;  0: normal operation.
+  #define ETH_PCS10_50G_REG_STATUS1_RX_LPI_ACTIVE_K2_E5_SHIFT                                                8
+  #define ETH_PCS10_50G_REG_STATUS1_TX_LPI_ACTIVE_K2_E5                                                      (0x1<<9) // 1: transmit is currently in LPI state;  0: normal operation.
+  #define ETH_PCS10_50G_REG_STATUS1_TX_LPI_ACTIVE_K2_E5_SHIFT                                                9
+  #define ETH_PCS10_50G_REG_STATUS1_RX_LPI_K2_E5                                                             (0x1<<10) // 1: receive is or was in LPI state;  0: normal operation; Latching high.
+  #define ETH_PCS10_50G_REG_STATUS1_RX_LPI_K2_E5_SHIFT                                                       10
+  #define ETH_PCS10_50G_REG_STATUS1_TX_LPI_K2_E5                                                             (0x1<<11) // 1: transmit is or was in LPI state;  0: normal operation; Latching high.
+  #define ETH_PCS10_50G_REG_STATUS1_TX_LPI_K2_E5_SHIFT                                                       11
+#define ETH_PCS10_50G_REG_DEVICE_ID0_K2_E5                                                                   0x000008UL //Access:R    DataWidth:0x20   // PHY Identifier constant from package parameter PHY_IDENTIFIER bits 15:4. Bits 3:0 always 0.
+  #define ETH_PCS10_50G_REG_DEVICE_ID0_IDENTIFIER_K2_E5                                                      (0xffff<<0) // Bits 15:0 of Device Identifier defined by parameter PHY_IDENTIFIER in PCS package file.
+  #define ETH_PCS10_50G_REG_DEVICE_ID0_IDENTIFIER_K2_E5_SHIFT                                                0
+#define ETH_PCS10_50G_REG_DEVICE_ID1_K2_E5                                                                   0x00000cUL //Access:R    DataWidth:0x20   // PHY Identifier constant from package parameter PHY_IDENTIFIER bits 31:16.
+  #define ETH_PCS10_50G_REG_DEVICE_ID1_IDENTIFIER_K2_E5                                                      (0xffff<<0) // Bits 31:16 of Device Identifier defined by parameter PHY_IDENTIFIER in PCS package file.
+  #define ETH_PCS10_50G_REG_DEVICE_ID1_IDENTIFIER_K2_E5_SHIFT                                                0
+#define ETH_PCS10_50G_REG_SPEED_ABILITY_K2_E5                                                                0x000010UL //Access:R    DataWidth:0x20   // PCS supported speeds (values as defined by standard only, no proprietary speeds).
+  #define ETH_PCS10_50G_REG_SPEED_ABILITY_C10GETH_K2_E5                                                      (0x1<<0) // When 1, this PCS is 10Geth capable.
+  #define ETH_PCS10_50G_REG_SPEED_ABILITY_C10GETH_K2_E5_SHIFT                                                0
+  #define ETH_PCS10_50G_REG_SPEED_ABILITY_C10PASS_TS_K2_E5                                                   (0x1<<1) // When 1, this PCS is 10PASS-TS/2Base-TL capable.
+  #define ETH_PCS10_50G_REG_SPEED_ABILITY_C10PASS_TS_K2_E5_SHIFT                                             1
+  #define ETH_PCS10_50G_REG_SPEED_ABILITY_C40G_K2_E5                                                         (0x1<<2) // When 1, this PCS is 40G capable.
+  #define ETH_PCS10_50G_REG_SPEED_ABILITY_C40G_K2_E5_SHIFT                                                   2
+  #define ETH_PCS10_50G_REG_SPEED_ABILITY_C100G_K2_E5                                                        (0x1<<3) // When 1, this PCS is 100G capable.
+  #define ETH_PCS10_50G_REG_SPEED_ABILITY_C100G_K2_E5_SHIFT                                                  3
+#define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_K2_E5                                                              0x000014UL //Access:R    DataWidth:0x20   // Constant indicating PCS presence.
+  #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_CLAUSE22_K2_E5                                                   (0x1<<0) // Clause 22 registers present when 1.
+  #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_CLAUSE22_K2_E5_SHIFT                                             0
+  #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_PMD_PMA_K2_E5                                                    (0x1<<1) // PMD/PMA present when 1.
+  #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_PMD_PMA_K2_E5_SHIFT                                              1
+  #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_WIS_PRES_K2_E5                                                   (0x1<<2) // WIS present when 1.
+  #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_WIS_PRES_K2_E5_SHIFT                                             2
+  #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_PCS_PRES_K2_E5                                                   (0x1<<3) // PCS present when 1.
+  #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_PCS_PRES_K2_E5_SHIFT                                             3
+  #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_PHY_XS_K2_E5                                                     (0x1<<4) // PHY XS present when 1.
+  #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_PHY_XS_K2_E5_SHIFT                                               4
+  #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_DTE_XS_K2_E5                                                     (0x1<<5) // DTE XS present when 1.
+  #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_DTE_XS_K2_E5_SHIFT                                               5
+  #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_TC_PRES_K2_E5                                                    (0x1<<6) // TC present when 1.
+  #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_TC_PRES_K2_E5_SHIFT                                              6
+#define ETH_PCS10_50G_REG_DEVICES_IN_PKG2_K2_E5                                                              0x000018UL //Access:R    DataWidth:0x20   // Vendor specific presence.
+  #define ETH_PCS10_50G_REG_DEVICES_IN_PKG2_CLAUSE22_K2_E5                                                   (0x1<<13) // Clause 22 extension present
+  #define ETH_PCS10_50G_REG_DEVICES_IN_PKG2_CLAUSE22_K2_E5_SHIFT                                             13
+  #define ETH_PCS10_50G_REG_DEVICES_IN_PKG2_DEVICE1_K2_E5                                                    (0x1<<14) // Vendor specific device 1 present
+  #define ETH_PCS10_50G_REG_DEVICES_IN_PKG2_DEVICE1_K2_E5_SHIFT                                              14
+  #define ETH_PCS10_50G_REG_DEVICES_IN_PKG2_DEVICE2_K2_E5                                                    (0x1<<15) // Vendor specific device 2 present
+  #define ETH_PCS10_50G_REG_DEVICES_IN_PKG2_DEVICE2_K2_E5_SHIFT                                              15
+#define ETH_PCS10_50G_REG_CONTROL2_K2_E5                                                                     0x00001cUL //Access:RW   DataWidth:0x20   // Operating speed indication/control.
+  #define ETH_PCS10_50G_REG_CONTROL2_PCS_TYPE_K2_E5                                                          (0x7<<0) // PCS type selection; Writing 0 sets PCS_MODE to 0x03 setting Clause 49 mode and disabling MLD.
+  #define ETH_PCS10_50G_REG_CONTROL2_PCS_TYPE_K2_E5_SHIFT                                                    0
+#define ETH_PCS10_50G_REG_STATUS2_K2_E5                                                                      0x000020UL //Access:R    DataWidth:0x20   // Fault status; Device capabilities
+  #define ETH_PCS10_50G_REG_STATUS2_C10GBASE_R_K2_E5                                                         (0x1<<0) // When 1, this PCS is 10GBase-R capable.
+  #define ETH_PCS10_50G_REG_STATUS2_C10GBASE_R_K2_E5_SHIFT                                                   0
+  #define ETH_PCS10_50G_REG_STATUS2_C10GBASE_X_K2_E5                                                         (0x1<<1) // When 1, this PCS is 10GBase-X capable.
+  #define ETH_PCS10_50G_REG_STATUS2_C10GBASE_X_K2_E5_SHIFT                                                   1
+  #define ETH_PCS10_50G_REG_STATUS2_C10GBASE_W_K2_E5                                                         (0x1<<2) // When 1, this PCS is 10GBase-W capable.
+  #define ETH_PCS10_50G_REG_STATUS2_C10GBASE_W_K2_E5_SHIFT                                                   2
+  #define ETH_PCS10_50G_REG_STATUS2_C10GBASE_T_K2_E5                                                         (0x1<<3) // When 1, this PCS is 10GBase-T capable.
+  #define ETH_PCS10_50G_REG_STATUS2_C10GBASE_T_K2_E5_SHIFT                                                   3
+  #define ETH_PCS10_50G_REG_STATUS2_C40GBASE_R_K2_E5                                                         (0x1<<4) // When 1, this PCS is 40GBase-R capable.
+  #define ETH_PCS10_50G_REG_STATUS2_C40GBASE_R_K2_E5_SHIFT                                                   4
+  #define ETH_PCS10_50G_REG_STATUS2_C100GBASE_R_K2_E5                                                        (0x1<<5) // When 1, this PCS is 100GBase-R capable.
+  #define ETH_PCS10_50G_REG_STATUS2_C100GBASE_R_K2_E5_SHIFT                                                  5
+  #define ETH_PCS10_50G_REG_STATUS2_RECEIVE_FAULT_K2_E5                                                      (0x1<<10) // Receive fault. 1=Fault condition on receive path. Latched high
+  #define ETH_PCS10_50G_REG_STATUS2_RECEIVE_FAULT_K2_E5_SHIFT                                                10
+  #define ETH_PCS10_50G_REG_STATUS2_TRANSMIT_FAULT_K2_E5                                                     (0x1<<11) // Transmit fault. 1=Fault condition on transmit path. Latched high
+  #define ETH_PCS10_50G_REG_STATUS2_TRANSMIT_FAULT_K2_E5_SHIFT                                               11
+  #define ETH_PCS10_50G_REG_STATUS2_DEVICE_PRESENT_K2_E5                                                     (0x3<<14) // Device present. When bits are 10 = device responding at this address.
+  #define ETH_PCS10_50G_REG_STATUS2_DEVICE_PRESENT_K2_E5_SHIFT                                               14
+#define ETH_PCS10_50G_REG_PKG_ID0_K2_E5                                                                      0x000038UL //Access:R    DataWidth:0x20   // Constant from package parameter PACK_IDENTIFIER bits 15:0.
+  #define ETH_PCS10_50G_REG_PKG_ID0_IDENTIFIER_K2_E5                                                         (0xffff<<0) // Constant from package parameter PACK_IDENTIFIER bits 15:0.
+  #define ETH_PCS10_50G_REG_PKG_ID0_IDENTIFIER_K2_E5_SHIFT                                                   0
+#define ETH_PCS10_50G_REG_PKG_ID1_K2_E5                                                                      0x00003cUL //Access:R    DataWidth:0x20   // Constant from package parameter PACK_IDENTIFIER bits 31:16.
+  #define ETH_PCS10_50G_REG_PKG_ID1_IDENTIFIER_K2_E5                                                         (0xffff<<0) // Constant from package parameter PACK_IDENTIFIER bits 31:16.
+  #define ETH_PCS10_50G_REG_PKG_ID1_IDENTIFIER_K2_E5_SHIFT                                                   0
+#define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_K2_E5                                                          0x000050UL //Access:RW   DataWidth:0x20   // EEE Control and Capabilities (exists only if EEE is available).
+  #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_LPI_FW_K2_E5                                                 (0x1<<0) // Mode for selecting select 40G EEE mode; 1 = Fast wake mode; 0 = Deep sleep for LPI function.
+  #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_LPI_FW_K2_E5_SHIFT                                           0
+  #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_EEE_10GBASE_KR_K2_E5                                         (0x1<<6) // When 1, EEE is supported for 10GBASE-KR.
+  #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_EEE_10GBASE_KR_K2_E5_SHIFT                                   6
+  #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_EEE_40GBASE_RAWAKE_K2_E5                                     (0x1<<8) // When 1, EEE fast wake is supported for 40GBASE-R.
+  #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_EEE_40GBASE_RAWAKE_K2_E5_SHIFT                               8
+  #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_EEE_40GBASE_RSLEEP_K2_E5                                     (0x1<<9) // When 1, EEE deep sleep is supported for 40GBASE-R.
+  #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_EEE_40GBASE_RSLEEP_K2_E5_SHIFT                               9
+#define ETH_PCS10_50G_REG_WAKE_ERR_COUNTER_K2_E5                                                             0x000058UL //Access:R    DataWidth:0x20   // EEE Wake error counter (exists only if EEE is available); Clears on read.
+  #define ETH_PCS10_50G_REG_WAKE_ERR_COUNTER_COUNTER_K2_E5                                                   (0xffff<<0) // Increments each time the LPI enters the RX_WTF state indicating a wake time fault; None roll-over.
+  #define ETH_PCS10_50G_REG_WAKE_ERR_COUNTER_COUNTER_K2_E5_SHIFT                                             0
+#define ETH_PCS10_50G_REG_BASER_STATUS1_K2_E5                                                                0x000080UL //Access:R    DataWidth:0x20   // Link Status Information.
+  #define ETH_PCS10_50G_REG_BASER_STATUS1_BLOCK_LOCK_K2_E5                                                   (0x1<<0) // 1=PCS locked to received blocks.
+  #define ETH_PCS10_50G_REG_BASER_STATUS1_BLOCK_LOCK_K2_E5_SHIFT                                             0
+  #define ETH_PCS10_50G_REG_BASER_STATUS1_HIGH_BER_K2_E5                                                     (0x1<<1) // 1=PCS reporting a high BER.
+  #define ETH_PCS10_50G_REG_BASER_STATUS1_HIGH_BER_K2_E5_SHIFT                                               1
+  #define ETH_PCS10_50G_REG_BASER_STATUS1_RECEIVE_LINK_K2_E5                                                 (0x1<<12) // Receive link status. 1=Link up; 0=link down.
+  #define ETH_PCS10_50G_REG_BASER_STATUS1_RECEIVE_LINK_K2_E5_SHIFT                                           12
+#define ETH_PCS10_50G_REG_BASER_STATUS2_K2_E5                                                                0x000084UL //Access:R    DataWidth:0x20   // Link Status latches and error counters.
+  #define ETH_PCS10_50G_REG_BASER_STATUS2_ERRORED_CNT_K2_E5                                                  (0xff<<0) // Errored blocks counter; None roll-over.
+  #define ETH_PCS10_50G_REG_BASER_STATUS2_ERRORED_CNT_K2_E5_SHIFT                                            0
+  #define ETH_PCS10_50G_REG_BASER_STATUS2_BER_COUNTER_K2_E5                                                  (0x3f<<8) // BER counter; None roll-over.
+  #define ETH_PCS10_50G_REG_BASER_STATUS2_BER_COUNTER_K2_E5_SHIFT                                            8
+  #define ETH_PCS10_50G_REG_BASER_STATUS2_HIGH_BER_K2_E5                                                     (0x1<<14) // BER flag; Latched high.
+  #define ETH_PCS10_50G_REG_BASER_STATUS2_HIGH_BER_K2_E5_SHIFT                                               14
+  #define ETH_PCS10_50G_REG_BASER_STATUS2_BLOCK_LOCK_K2_E5                                                   (0x1<<15) // Block Lock; Latched low.
+  #define ETH_PCS10_50G_REG_BASER_STATUS2_BLOCK_LOCK_K2_E5_SHIFT                                             15
+#define ETH_PCS10_50G_REG_SEED_A0_K2_E5                                                                      0x000088UL //Access:RW   DataWidth:0x20   // 10G Base-R Test Pattern Seed A bits 15:0.
+  #define ETH_PCS10_50G_REG_SEED_A0_SEED_K2_E5                                                               (0xffff<<0) // 10GBase-R Test Pattern Seed A: Bits 15:0.
+  #define ETH_PCS10_50G_REG_SEED_A0_SEED_K2_E5_SHIFT                                                         0
+#define ETH_PCS10_50G_REG_SEED_A1_K2_E5                                                                      0x00008cUL //Access:RW   DataWidth:0x20   // 10G Base-R Test Pattern Seed A bits 31:16.
+  #define ETH_PCS10_50G_REG_SEED_A1_SEED_K2_E5                                                               (0xffff<<0) // 10GBase-R Test Pattern Seed A: Bits 31:16.
+  #define ETH_PCS10_50G_REG_SEED_A1_SEED_K2_E5_SHIFT                                                         0
+#define ETH_PCS10_50G_REG_SEED_A2_K2_E5                                                                      0x000090UL //Access:RW   DataWidth:0x20   // 10G Base-R Test Pattern Seed A bits 47:32.
+  #define ETH_PCS10_50G_REG_SEED_A2_SEED_K2_E5                                                               (0xffff<<0) // 10GBase-R Test Pattern Seed A: Bits 47:32.
+  #define ETH_PCS10_50G_REG_SEED_A2_SEED_K2_E5_SHIFT                                                         0
+#define ETH_PCS10_50G_REG_SEED_A3_K2_E5                                                                      0x000094UL //Access:RW   DataWidth:0x20   // 10G Base-R Test Pattern Seed A bits 57:48.
+  #define ETH_PCS10_50G_REG_SEED_A3_SEED_K2_E5                                                               (0x3ff<<0) // 10GBase-R Test Pattern Seed A: Bits 57:48.
+  #define ETH_PCS10_50G_REG_SEED_A3_SEED_K2_E5_SHIFT                                                         0
+#define ETH_PCS10_50G_REG_SEED_B0_K2_E5                                                                      0x000098UL //Access:RW   DataWidth:0x20   // 10G Base-R Test Pattern Seed B bits 15:0.
+  #define ETH_PCS10_50G_REG_SEED_B0_SEED_K2_E5                                                               (0xffff<<0) // 10GBase-R Test Pattern Seed B: Bits 15:0.
+  #define ETH_PCS10_50G_REG_SEED_B0_SEED_K2_E5_SHIFT                                                         0
+#define ETH_PCS10_50G_REG_SEED_B1_K2_E5                                                                      0x00009cUL //Access:RW   DataWidth:0x20   // 10G Base-R Test Pattern Seed B bits 31:16.
+  #define ETH_PCS10_50G_REG_SEED_B1_SEED_K2_E5                                                               (0xffff<<0) // 10GBase-R Test Pattern Seed B: Bits 31:16.
+  #define ETH_PCS10_50G_REG_SEED_B1_SEED_K2_E5_SHIFT                                                         0
+#define ETH_PCS10_50G_REG_SEED_B2_K2_E5                                                                      0x0000a0UL //Access:RW   DataWidth:0x20   // 10G Base-R Test Pattern Seed B bits 47:32.
+  #define ETH_PCS10_50G_REG_SEED_B2_SEED_K2_E5                                                               (0xffff<<0) // 10GBase-R Test Pattern Seed B: Bits 47:32.
+  #define ETH_PCS10_50G_REG_SEED_B2_SEED_K2_E5_SHIFT                                                         0
+#define ETH_PCS10_50G_REG_SEED_B3_K2_E5                                                                      0x0000a4UL //Access:RW   DataWidth:0x20   // 10G Base-R Test Pattern Seed B bits 57:48.
+  #define ETH_PCS10_50G_REG_SEED_B3_SEED_K2_E5                                                               (0x3ff<<0) // 10GBase-R Test Pattern Seed B: Bits 57:48.
+  #define ETH_PCS10_50G_REG_SEED_B3_SEED_K2_E5_SHIFT                                                         0
+#define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_K2_E5                                                           0x0000a8UL //Access:RW   DataWidth:0x20   // Test Pattern Generator and Checker controls.
+  #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_DATA_PATTERN_SEL_K2_E5                                        (0x1<<0) // Data Pattern Select: 1=all Zero, 0=2x Local Fault; 10G only.
+  #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_DATA_PATTERN_SEL_K2_E5_SHIFT                                  0
+  #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_SELECT_SQUARE_K2_E5                                           (0x1<<1) // Select Square Wave (1) or Pseudo Random (0) test pattern; 10G only.
+  #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_SELECT_SQUARE_K2_E5_SHIFT                                     1
+  #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_RX_TESTPATTERN_K2_E5                                          (0x1<<2) // Receive test-pattern enable.
+  #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_RX_TESTPATTERN_K2_E5_SHIFT                                    2
+  #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_TX_TESTPATTERN_K2_E5                                          (0x1<<3) // Transmit test-pattern enable.
+  #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_TX_TESTPATTERN_K2_E5_SHIFT                                    3
+  #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_SELECT_RANDOM_K2_E5                                           (0x1<<7) // Select Random Idle test pattern (40G); Overrides bits 1:0 when set.
+  #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_SELECT_RANDOM_K2_E5_SHIFT                                     7
+#define ETH_PCS10_50G_REG_BASER_TEST_ERR_CNT_K2_E5                                                           0x0000acUL //Access:R    DataWidth:0x20   // Test Pattern Error Counter; Clears on read; None roll-over.
+  #define ETH_PCS10_50G_REG_BASER_TEST_ERR_CNT_COUNTER_K2_E5                                                 (0xffff<<0) // Test pattern error counter; Clears on read; None roll-over.
+  #define ETH_PCS10_50G_REG_BASER_TEST_ERR_CNT_COUNTER_K2_E5_SHIFT                                           0
+#define ETH_PCS10_50G_REG_BER_HIGH_ORDER_CNT_K2_E5                                                           0x0000b0UL //Access:R    DataWidth:0x20   // BER High Order Counter of BER bits 21:6; None roll-over.
+  #define ETH_PCS10_50G_REG_BER_HIGH_ORDER_CNT_BER_COUNTER_K2_E5                                             (0xffff<<0) // Bits 21:6 of BER counter; None roll-over.
+  #define ETH_PCS10_50G_REG_BER_HIGH_ORDER_CNT_BER_COUNTER_K2_E5_SHIFT                                       0
+#define ETH_PCS10_50G_REG_ERR_BLK_HIGH_ORDER_CNT_K2_E5                                                       0x0000b4UL //Access:R    DataWidth:0x20   // Error Blocks High Order Counter bits 21:8; None roll-over.
+  #define ETH_PCS10_50G_REG_ERR_BLK_HIGH_ORDER_CNT_ERRORED_BLOCKS_COUNTER_K2_E5                              (0x3fff<<0) // Bits 21:8 of Error Blocks counter; None roll-over.
+  #define ETH_PCS10_50G_REG_ERR_BLK_HIGH_ORDER_CNT_ERRORED_BLOCKS_COUNTER_K2_E5_SHIFT                        0
+  #define ETH_PCS10_50G_REG_ERR_BLK_HIGH_ORDER_CNT_HIGH_ORDER_PRESENT_K2_E5                                  (0x1<<15) // High order counter present; Always 1.
+  #define ETH_PCS10_50G_REG_ERR_BLK_HIGH_ORDER_CNT_HIGH_ORDER_PRESENT_K2_E5_SHIFT                            15
+#define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_K2_E5                                                        0x0000c8UL //Access:R    DataWidth:0x20   // Lane Alignment Status Bits and Block Lock.
+  #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE0_BLOCK_LOCK_K2_E5                                     (0x1<<0) // Lane 0 block lock.
+  #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE0_BLOCK_LOCK_K2_E5_SHIFT                               0
+  #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE1_BLOCK_LOCK_K2_E5                                     (0x1<<1) // Lane 1 block lock.
+  #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE1_BLOCK_LOCK_K2_E5_SHIFT                               1
+  #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE2_BLOCK_LOCK_K2_E5                                     (0x1<<2) // Lane 2 block lock.
+  #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE2_BLOCK_LOCK_K2_E5_SHIFT                               2
+  #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE3_BLOCK_LOCK_K2_E5                                     (0x1<<3) // Lane 3 block lock.
+  #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE3_BLOCK_LOCK_K2_E5_SHIFT                               3
+  #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE_ALIGN_STATUS_K2_E5                                    (0x1<<12) // Lane alignment status; 1=All Receive lanes locked and aligned.
+  #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE_ALIGN_STATUS_K2_E5_SHIFT                              12
+#define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_K2_E5                                                        0x0000d0UL //Access:R    DataWidth:0x20   // Lane Alignment Marker Lock Status bits.
+  #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_LANE0_MARKER_LOCK_K2_E5                                    (0x1<<0) // Lane 0 alignment marker lock
+  #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_LANE0_MARKER_LOCK_K2_E5_SHIFT                              0
+  #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_LANE1_MARKER_LOCK_K2_E5                                    (0x1<<1) // Lane 1 alignment marker lock
+  #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_LANE1_MARKER_LOCK_K2_E5_SHIFT                              1
+  #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_LANE2_MARKER_LOCK_K2_E5                                    (0x1<<2) // Lane 2 alignment marker lock
+  #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_LANE2_MARKER_LOCK_K2_E5_SHIFT                              2
+  #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_LANE3_MARKER_LOCK_K2_E5                                    (0x1<<3) // Lane 3 alignment marker lock
+  #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_LANE3_MARKER_LOCK_K2_E5_SHIFT                              3
+#define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE0_K2_E5                                                            0x000320UL //Access:R    DataWidth:0x20   // BIP Error Counter Lane 0; Clears on read; None roll-over.
+  #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE0_BIP_ERROR_COUNTER_K2_E5                                        (0xffff<<0) // BIP error counter lane 0; None roll-over.
+  #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE0_BIP_ERROR_COUNTER_K2_E5_SHIFT                                  0
+#define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE1_K2_E5                                                            0x000324UL //Access:R    DataWidth:0x20   // BIP Error Counter Lane 1; Clears on read; None roll-over.
+  #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE1_BIP_ERROR_COUNTER_K2_E5                                        (0xffff<<0) // BIP error counter lane 1; None roll-over.
+  #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE1_BIP_ERROR_COUNTER_K2_E5_SHIFT                                  0
+#define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE2_K2_E5                                                            0x000328UL //Access:R    DataWidth:0x20   // BIP Error Counter Lane 2; Clears on read; None roll-over.
+  #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE2_BIP_ERROR_COUNTER_K2_E5                                        (0xffff<<0) // BIP error counter lane 2; None roll-over.
+  #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE2_BIP_ERROR_COUNTER_K2_E5_SHIFT                                  0
+#define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE3_K2_E5                                                            0x00032cUL //Access:R    DataWidth:0x20   // BIP Error Counter Lane 3; Clears on read; None roll-over.
+  #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE3_BIP_ERROR_COUNTER_K2_E5                                        (0xffff<<0) // BIP error counter lane 3; None roll-over.
+  #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE3_BIP_ERROR_COUNTER_K2_E5_SHIFT                                  0
+#define ETH_PCS10_50G_REG_LANE0_MAPPING_K2_E5                                                                0x000640UL //Access:R    DataWidth:0x20   // Lane Channel 0 mapping bits 1:0.
+  #define ETH_PCS10_50G_REG_LANE0_MAPPING_LANE_MAPPING_K2_E5                                                 (0x3<<0) // Lane 0 mapping bits 1:0.
+  #define ETH_PCS10_50G_REG_LANE0_MAPPING_LANE_MAPPING_K2_E5_SHIFT                                           0
+#define ETH_PCS10_50G_REG_LANE1_MAPPING_K2_E5                                                                0x000644UL //Access:R    DataWidth:0x20   // Lane Channel 1 mapping bits 1:0.
+  #define ETH_PCS10_50G_REG_LANE1_MAPPING_LANE_MAPPING_K2_E5                                                 (0x3<<0) // Lane 1 mapping bits 1:0.
+  #define ETH_PCS10_50G_REG_LANE1_MAPPING_LANE_MAPPING_K2_E5_SHIFT                                           0
+#define ETH_PCS10_50G_REG_LANE2_MAPPING_K2_E5                                                                0x000648UL //Access:R    DataWidth:0x20   // Lane Channel 2 mapping bits 1:0.
+  #define ETH_PCS10_50G_REG_LANE2_MAPPING_LANE_MAPPING_K2_E5                                                 (0x3<<0) // Lane 2 mapping bits 1:0.
+  #define ETH_PCS10_50G_REG_LANE2_MAPPING_LANE_MAPPING_K2_E5_SHIFT                                           0
+#define ETH_PCS10_50G_REG_LANE3_MAPPING_K2_E5                                                                0x00064cUL //Access:R    DataWidth:0x20   // Lane Channel 3 mapping bits 1:0.
+  #define ETH_PCS10_50G_REG_LANE3_MAPPING_LANE_MAPPING_K2_E5                                                 (0x3<<0) // Lane 3 mapping bits 1:0.
+  #define ETH_PCS10_50G_REG_LANE3_MAPPING_LANE_MAPPING_K2_E5_SHIFT                                           0
+#define ETH_PCS10_50G_REG_VENDOR_SCRATCH_K2_E5                                                               0x020000UL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Scratch Register.
+  #define ETH_PCS10_50G_REG_VENDOR_SCRATCH_SCRATCH_K2_E5                                                     (0xffff<<0) // Scratch Register; Register address to test read and write operation.
+  #define ETH_PCS10_50G_REG_VENDOR_SCRATCH_SCRATCH_K2_E5_SHIFT                                               0
+#define ETH_PCS10_50G_REG_VENDOR_CORE_REV_K2_E5                                                              0x020004UL //Access:R    DataWidth:0x20   // Vendor Specific Reg; Core Revision derived from DEV_VERSION package parameter.
+  #define ETH_PCS10_50G_REG_VENDOR_CORE_REV_REVISION_K2_E5                                                   (0xffff<<0) // Core Design version as defined by DEV_VERSION parameter in PCS package file.
+  #define ETH_PCS10_50G_REG_VENDOR_CORE_REV_REVISION_K2_E5_SHIFT                                             0
+#define ETH_PCS10_50G_REG_VENDOR_VL_INTVL_K2_E5                                                              0x020008UL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Set the amount of data between markers. (I.e. distance of markers-1).
+  #define ETH_PCS10_50G_REG_VENDOR_VL_INTVL_MARKER_COUNTER_K2_E5                                             (0xffff<<0) // A 16-bit value defining the amount of data between markers; (distance of markers-1).
+  #define ETH_PCS10_50G_REG_VENDOR_VL_INTVL_MARKER_COUNTER_K2_E5_SHIFT                                       0
+#define ETH_PCS10_50G_REG_VENDOR_TXLANE_THRESH_K2_E5                                                         0x02000cUL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Defines the transmit line decoupling FIFOs almost full threshold.
+  #define ETH_PCS10_50G_REG_VENDOR_TXLANE_THRESH_THRESHOLD_K2_E5                                             (0xf<<0) // A 4-bit value to define the transmit line decoupling FIFOs almost full threshold; Valid values are 4..9.
+  #define ETH_PCS10_50G_REG_VENDOR_TXLANE_THRESH_THRESHOLD_K2_E5_SHIFT                                       0
+#define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_K2_E5                                                         0x020010UL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Define Reduced-XLAUI PMA mode using 2 lanes.
+  #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_RXLAUI_ENA_K2_E5                                            (0x1<<0) // Enable Reduced-XLAUI PMA mode using 2 lanes.
+  #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_RXLAUI_ENA_K2_E5_SHIFT                                      0
+  #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_RESERVED_WRITEABLE_BITS_K2_E5                               (0x7<<1) // These bits are writeable but have no effect.
+  #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_RESERVED_WRITEABLE_BITS_K2_E5_SHIFT                         1
+  #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_TX_MAP_LANE0_K2_E5                                          (0xf<<4) // Set VL (0..3) to transmit to RXLAUI lane 0.
+  #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_TX_MAP_LANE0_K2_E5_SHIFT                                    4
+  #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_TX_MAP_LANE1_K2_E5                                          (0xf<<8) // Set VL (0..3) to transmit to RXLAUI lane 1.
+  #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_TX_MAP_LANE1_K2_E5_SHIFT                                    8
+  #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_ENA_STATUS_K2_E5                                            (0x1<<15) // Indicates if currently the RXLAUI mode is enabled.
+  #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_ENA_STATUS_K2_E5_SHIFT                                      15
+#define ETH_PCS10_50G_REG_VENDOR_VL0_0_K2_E5                                                                 0x020020UL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Marker pattern for PCS Virtual Lane 0.
+  #define ETH_PCS10_50G_REG_VENDOR_VL0_0_M0_K2_E5                                                            (0xff<<0) // Lane 0 Marker pattern for m0.
+  #define ETH_PCS10_50G_REG_VENDOR_VL0_0_M0_K2_E5_SHIFT                                                      0
+  #define ETH_PCS10_50G_REG_VENDOR_VL0_0_M1_K2_E5                                                            (0xff<<8) // Lane 0 Marker pattern for m1.
+  #define ETH_PCS10_50G_REG_VENDOR_VL0_0_M1_K2_E5_SHIFT                                                      8
+#define ETH_PCS10_50G_REG_VENDOR_VL0_1_K2_E5                                                                 0x020024UL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Last byte of PCS Virtual Lane 0 marker pattern.
+  #define ETH_PCS10_50G_REG_VENDOR_VL0_1_M2_K2_E5                                                            (0xff<<0) // Lane 0 last btye of Marker pattern for m2.
+  #define ETH_PCS10_50G_REG_VENDOR_VL0_1_M2_K2_E5_SHIFT                                                      0
+#define ETH_PCS10_50G_REG_VENDOR_VL1_0_K2_E5                                                                 0x020028UL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Marker pattern for PCS Virtual Lane 1.
+  #define ETH_PCS10_50G_REG_VENDOR_VL1_0_M0_K2_E5                                                            (0xff<<0) // Lane 1 Marker pattern for m0.
+  #define ETH_PCS10_50G_REG_VENDOR_VL1_0_M0_K2_E5_SHIFT                                                      0
+  #define ETH_PCS10_50G_REG_VENDOR_VL1_0_M1_K2_E5                                                            (0xff<<8) // Lane 1 Marker pattern for m1.
+  #define ETH_PCS10_50G_REG_VENDOR_VL1_0_M1_K2_E5_SHIFT                                                      8
+#define ETH_PCS10_50G_REG_VENDOR_VL1_1_K2_E5                                                                 0x02002cUL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Last byte of PCS Virtual Lane 1 marker pattern.
+  #define ETH_PCS10_50G_REG_VENDOR_VL1_1_M2_K2_E5                                                            (0xff<<0) // Lane 1 last btye of Marker pattern for m2.
+  #define ETH_PCS10_50G_REG_VENDOR_VL1_1_M2_K2_E5_SHIFT                                                      0
+#define ETH_PCS10_50G_REG_VENDOR_VL2_0_K2_E5                                                                 0x020030UL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Marker pattern for PCS Virtual Lane 2.
+  #define ETH_PCS10_50G_REG_VENDOR_VL2_0_M0_K2_E5                                                            (0xff<<0) // Lane 2 Marker pattern for m0.
+  #define ETH_PCS10_50G_REG_VENDOR_VL2_0_M0_K2_E5_SHIFT                                                      0
+  #define ETH_PCS10_50G_REG_VENDOR_VL2_0_M1_K2_E5                                                            (0xff<<8) // Lane 2 Marker pattern for m1.
+  #define ETH_PCS10_50G_REG_VENDOR_VL2_0_M1_K2_E5_SHIFT                                                      8
+#define ETH_PCS10_50G_REG_VENDOR_VL2_1_K2_E5                                                                 0x020034UL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Last byte of PCS Virtual Lane 2 marker pattern.
+  #define ETH_PCS10_50G_REG_VENDOR_VL2_1_M2_K2_E5                                                            (0xff<<0) // Lane 2 last btye of Marker pattern for m2.
+  #define ETH_PCS10_50G_REG_VENDOR_VL2_1_M2_K2_E5_SHIFT                                                      0
+#define ETH_PCS10_50G_REG_VENDOR_VL3_0_K2_E5                                                                 0x020038UL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Marker pattern for PCS Virtual Lane 3.
+  #define ETH_PCS10_50G_REG_VENDOR_VL3_0_M0_K2_E5                                                            (0xff<<0) // Lane 3 Marker pattern for m0.
+  #define ETH_PCS10_50G_REG_VENDOR_VL3_0_M0_K2_E5_SHIFT                                                      0
+  #define ETH_PCS10_50G_REG_VENDOR_VL3_0_M1_K2_E5                                                            (0xff<<8) // Lane 3 Marker pattern for m1.
+  #define ETH_PCS10_50G_REG_VENDOR_VL3_0_M1_K2_E5_SHIFT                                                      8
+#define ETH_PCS10_50G_REG_VENDOR_VL3_1_K2_E5                                                                 0x02003cUL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Last byte of PCS Virtual Lane 3 marker pattern.
+  #define ETH_PCS10_50G_REG_VENDOR_VL3_1_M2_K2_E5                                                            (0xff<<0) // Lane 3 last btye of Marker pattern for m2.
+  #define ETH_PCS10_50G_REG_VENDOR_VL3_1_M2_K2_E5_SHIFT                                                      0
+#define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_K2_E5                                                              0x020040UL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Configure PCS supporting Clause 49 or 82 Encoder/Decoder, MLD.
+  #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_ENA_CLAUSE49_K2_E5                                               (0x1<<0) // When 0 PCS uses Clause 82 encoder/decoder functions; When 1 PCS uses Clause 49 encoder/decoder functions.
+  #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_ENA_CLAUSE49_K2_E5_SHIFT                                         0
+  #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_DISABLE_MLD_K2_E5                                                (0x1<<1) // When 0 PCS 4-lane MLD function is active; When 1 the MLD function is disabled.
+  #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_DISABLE_MLD_K2_E5_SHIFT                                          1
+  #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_ST_ENA_CLAUSE49_K2_E5                                            (0x1<<8) // Current status of Clause 49 setting.
+  #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_ST_ENA_CLAUSE49_K2_E5_SHIFT                                      8
+  #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_ST_DISABLE_MLD_K2_E5                                             (0x1<<9) // Current status of MLD setting.
+  #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_ST_DISABLE_MLD_K2_E5_SHIFT                                       9
+#define ETH_PCS10_25G_REG_CONTROL1_K2_E5                                                                     0x000000UL //Access:RW   DataWidth:0x20   // PCS Control.
+  #define ETH_PCS10_25G_REG_CONTROL1_SPEED_SELECTION_K2_E5                                                   (0xf<<2) // 0011 = 40 Gb/s; 0000 = 10Gb/s.
+  #define ETH_PCS10_25G_REG_CONTROL1_SPEED_SELECTION_K2_E5_SHIFT                                             2
+  #define ETH_PCS10_25G_REG_CONTROL1_SPEED_ALWAYS1_K2_E5                                                     (0x1<<6) // Always 1.
+  #define ETH_PCS10_25G_REG_CONTROL1_SPEED_ALWAYS1_K2_E5_SHIFT                                               6
+  #define ETH_PCS10_25G_REG_CONTROL1_LOW_POWER_K2_E5                                                         (0x1<<11) // 0=normal operation (Always 0).
+  #define ETH_PCS10_25G_REG_CONTROL1_LOW_POWER_K2_E5_SHIFT                                                   11
+  #define ETH_PCS10_25G_REG_CONTROL1_SPEED_SELECT_ALWAYS1_K2_E5                                              (0x1<<13) // Always 1.
+  #define ETH_PCS10_25G_REG_CONTROL1_SPEED_SELECT_ALWAYS1_K2_E5_SHIFT                                        13
+  #define ETH_PCS10_25G_REG_CONTROL1_LOOPBACK_K2_E5                                                          (0x1<<14) // 1=Enable loopback, 0=disable loopback.
+  #define ETH_PCS10_25G_REG_CONTROL1_LOOPBACK_K2_E5_SHIFT                                                    14
+  #define ETH_PCS10_25G_REG_CONTROL1_RESET_K2_E5                                                             (0x1<<15) // 1=PCS reset, 0=normal; Self clearing.
+  #define ETH_PCS10_25G_REG_CONTROL1_RESET_K2_E5_SHIFT                                                       15
+#define ETH_PCS10_25G_REG_STATUS1_K2_E5                                                                      0x000004UL //Access:R    DataWidth:0x20   // PCS Status.
+  #define ETH_PCS10_25G_REG_STATUS1_LOW_POWER_ABILITY_K2_E5                                                  (0x1<<1) // Set to 1 to indicate that the PCS implements a low power mode.
+  #define ETH_PCS10_25G_REG_STATUS1_LOW_POWER_ABILITY_K2_E5_SHIFT                                            1
+  #define ETH_PCS10_25G_REG_STATUS1_PCS_RECEIVE_LINK_K2_E5                                                   (0x1<<2) // When 1, indicates PCS receive link up; When 0, indicates PCS receive link is or was down (latching low).
+  #define ETH_PCS10_25G_REG_STATUS1_PCS_RECEIVE_LINK_K2_E5_SHIFT                                             2
+  #define ETH_PCS10_25G_REG_STATUS1_FAULT_K2_E5                                                              (0x1<<7) // When 1, indicates a fault condition idetected; When 0, indicates that no fault condition is detected.
+  #define ETH_PCS10_25G_REG_STATUS1_FAULT_K2_E5_SHIFT                                                        7
+  #define ETH_PCS10_25G_REG_STATUS1_RX_LPI_ACTIVE_K2_E5                                                      (0x1<<8) // 1: receive is currently in LPI state; 0: normal operation.
+  #define ETH_PCS10_25G_REG_STATUS1_RX_LPI_ACTIVE_K2_E5_SHIFT                                                8
+  #define ETH_PCS10_25G_REG_STATUS1_TX_LPI_ACTIVE_K2_E5                                                      (0x1<<9) // 1: transmit is currently in LPI state; 0: normal operation.
+  #define ETH_PCS10_25G_REG_STATUS1_TX_LPI_ACTIVE_K2_E5_SHIFT                                                9
+  #define ETH_PCS10_25G_REG_STATUS1_RX_LPI_K2_E5                                                             (0x1<<10) // 1: receive is or was in LPI state; 0: normal operation; Latching high.
+  #define ETH_PCS10_25G_REG_STATUS1_RX_LPI_K2_E5_SHIFT                                                       10
+  #define ETH_PCS10_25G_REG_STATUS1_TX_LPI_K2_E5                                                             (0x1<<11) // 1: transmit is or was in LPI state; 0: normal operation; Latching high.
+  #define ETH_PCS10_25G_REG_STATUS1_TX_LPI_K2_E5_SHIFT                                                       11
+#define ETH_PCS10_25G_REG_DEVICE_ID0_K2_E5                                                                   0x000008UL //Access:R    DataWidth:0x20   // PHY Identifier constant from package parameter PHY_IDENTIFIER bits 15:4. Bits 3:0 always 0.
+  #define ETH_PCS10_25G_REG_DEVICE_ID0_IDENTIFIER_K2_E5                                                      (0xffff<<0) // Bits 15:0 of Device Identifier defined by parameter PHY_IDENTIFIER in PCS package file.
+  #define ETH_PCS10_25G_REG_DEVICE_ID0_IDENTIFIER_K2_E5_SHIFT                                                0
+#define ETH_PCS10_25G_REG_DEVICE_ID1_K2_E5                                                                   0x00000cUL //Access:R    DataWidth:0x20   // PHY Identifier constant from package parameter PHY_IDENTIFIER bits 31:16.
+  #define ETH_PCS10_25G_REG_DEVICE_ID1_IDENTIFIER_K2_E5                                                      (0xffff<<0) // Bits 31:16 of Device Identifier defined by parameter PHY_IDENTIFIER in PCS package file.
+  #define ETH_PCS10_25G_REG_DEVICE_ID1_IDENTIFIER_K2_E5_SHIFT                                                0
+#define ETH_PCS10_25G_REG_SPEED_ABILITY_K2_E5                                                                0x000010UL //Access:R    DataWidth:0x20   // PCS supported speeds (values as defined by standard only, no proprietary speeds).
+  #define ETH_PCS10_25G_REG_SPEED_ABILITY_C10GETH_K2_E5                                                      (0x1<<0) // When 1, this PCS is 10Geth capable.
+  #define ETH_PCS10_25G_REG_SPEED_ABILITY_C10GETH_K2_E5_SHIFT                                                0
+  #define ETH_PCS10_25G_REG_SPEED_ABILITY_C10PASS_TS_K2_E5                                                   (0x1<<1) // When 1, this PCS is 10PASS-TS/2Base-TL capable.
+  #define ETH_PCS10_25G_REG_SPEED_ABILITY_C10PASS_TS_K2_E5_SHIFT                                             1
+  #define ETH_PCS10_25G_REG_SPEED_ABILITY_C40G_K2_E5                                                         (0x1<<2) // When 1, this PCS is 40G capable.
+  #define ETH_PCS10_25G_REG_SPEED_ABILITY_C40G_K2_E5_SHIFT                                                   2
+  #define ETH_PCS10_25G_REG_SPEED_ABILITY_C100G_K2_E5                                                        (0x1<<3) // When 1, this PCS is 100G capable.
+  #define ETH_PCS10_25G_REG_SPEED_ABILITY_C100G_K2_E5_SHIFT                                                  3
+#define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_K2_E5                                                              0x000014UL //Access:R    DataWidth:0x20   // Constant indicating PCS presence.
+  #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_CLAUSE22_K2_E5                                                   (0x1<<0) // Clause 22 registers present when 1.
+  #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_CLAUSE22_K2_E5_SHIFT                                             0
+  #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_PMD_PMA_K2_E5                                                    (0x1<<1) // PMD/PMA present when 1.
+  #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_PMD_PMA_K2_E5_SHIFT                                              1
+  #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_WIS_PRES_K2_E5                                                   (0x1<<2) // WIS present when 1.
+  #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_WIS_PRES_K2_E5_SHIFT                                             2
+  #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_PCS_PRES_K2_E5                                                   (0x1<<3) // PCS present when 1.
+  #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_PCS_PRES_K2_E5_SHIFT                                             3
+  #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_PHY_XS_K2_E5                                                     (0x1<<4) // PHY XS present when 1.
+  #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_PHY_XS_K2_E5_SHIFT                                               4
+  #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_DTE_XS_K2_E5                                                     (0x1<<5) // DTE XS present when 1.
+  #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_DTE_XS_K2_E5_SHIFT                                               5
+  #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_TC_PRES_K2_E5                                                    (0x1<<6) // TC present when 1.
+  #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_TC_PRES_K2_E5_SHIFT                                              6
+#define ETH_PCS10_25G_REG_DEVICES_IN_PKG2_K2_E5                                                              0x000018UL //Access:R    DataWidth:0x20   // Vendor specific presence.
+  #define ETH_PCS10_25G_REG_DEVICES_IN_PKG2_CLAUSE22_K2_E5                                                   (0x1<<13) // Clause 22 extension present
+  #define ETH_PCS10_25G_REG_DEVICES_IN_PKG2_CLAUSE22_K2_E5_SHIFT                                             13
+  #define ETH_PCS10_25G_REG_DEVICES_IN_PKG2_DEVICE1_K2_E5                                                    (0x1<<14) // Vendor specific device 1 present
+  #define ETH_PCS10_25G_REG_DEVICES_IN_PKG2_DEVICE1_K2_E5_SHIFT                                              14
+  #define ETH_PCS10_25G_REG_DEVICES_IN_PKG2_DEVICE2_K2_E5                                                    (0x1<<15) // Vendor specific device 2 present
+  #define ETH_PCS10_25G_REG_DEVICES_IN_PKG2_DEVICE2_K2_E5_SHIFT                                              15
+#define ETH_PCS10_25G_REG_CONTROL2_K2_E5                                                                     0x00001cUL //Access:RW   DataWidth:0x20   // Operating speed indication/control.
+  #define ETH_PCS10_25G_REG_CONTROL2_PCS_TYPE_K2_E5                                                          (0x7<<0) // PCS type selection; Writing 0 sets PCS_MODE to 0x03 setting Clause 49 mode and disabling MLD.
+  #define ETH_PCS10_25G_REG_CONTROL2_PCS_TYPE_K2_E5_SHIFT                                                    0
+#define ETH_PCS10_25G_REG_STATUS2_K2_E5                                                                      0x000020UL //Access:R    DataWidth:0x20   // Fault status; Device capabilities
+  #define ETH_PCS10_25G_REG_STATUS2_C10GBASE_R_K2_E5                                                         (0x1<<0) // When 1, this PCS is 10GBase-R capable.
+  #define ETH_PCS10_25G_REG_STATUS2_C10GBASE_R_K2_E5_SHIFT                                                   0
+  #define ETH_PCS10_25G_REG_STATUS2_C10GBASE_X_K2_E5                                                         (0x1<<1) // When 1, this PCS is 10GBase-X capable.
+  #define ETH_PCS10_25G_REG_STATUS2_C10GBASE_X_K2_E5_SHIFT                                                   1
+  #define ETH_PCS10_25G_REG_STATUS2_C10GBASE_W_K2_E5                                                         (0x1<<2) // When 1, this PCS is 10GBase-W capable.
+  #define ETH_PCS10_25G_REG_STATUS2_C10GBASE_W_K2_E5_SHIFT                                                   2
+  #define ETH_PCS10_25G_REG_STATUS2_C10GBASE_T_K2_E5                                                         (0x1<<3) // When 1, this PCS is 10GBase-T capable.
+  #define ETH_PCS10_25G_REG_STATUS2_C10GBASE_T_K2_E5_SHIFT                                                   3
+  #define ETH_PCS10_25G_REG_STATUS2_C40GBASE_R_K2_E5                                                         (0x1<<4) // When 1, this PCS is 40GBase-R capable.
+  #define ETH_PCS10_25G_REG_STATUS2_C40GBASE_R_K2_E5_SHIFT                                                   4
+  #define ETH_PCS10_25G_REG_STATUS2_C100GBASE_R_K2_E5                                                        (0x1<<5) // When 1, this PCS is 100GBase-R capable.
+  #define ETH_PCS10_25G_REG_STATUS2_C100GBASE_R_K2_E5_SHIFT                                                  5
+  #define ETH_PCS10_25G_REG_STATUS2_RECEIVE_FAULT_K2_E5                                                      (0x1<<10) // Receive fault. 1=Fault condition on receive path. Latched high
+  #define ETH_PCS10_25G_REG_STATUS2_RECEIVE_FAULT_K2_E5_SHIFT                                                10
+  #define ETH_PCS10_25G_REG_STATUS2_TRANSMIT_FAULT_K2_E5                                                     (0x1<<11) // Transmit fault. 1=Fault condition on transmit path. Latched high
+  #define ETH_PCS10_25G_REG_STATUS2_TRANSMIT_FAULT_K2_E5_SHIFT                                               11
+  #define ETH_PCS10_25G_REG_STATUS2_DEVICE_PRESENT_K2_E5                                                     (0x3<<14) // Device present. When bits are 10 = device responding at this address.
+  #define ETH_PCS10_25G_REG_STATUS2_DEVICE_PRESENT_K2_E5_SHIFT                                               14
+#define ETH_PCS10_25G_REG_PKG_ID0_K2_E5                                                                      0x000038UL //Access:R    DataWidth:0x20   // Constant from package parameter PACK_IDENTIFIER bits 15:0.
+  #define ETH_PCS10_25G_REG_PKG_ID0_IDENTIFIER_K2_E5                                                         (0xffff<<0) // Constant from package parameter PACK_IDENTIFIER bits 15:0.
+  #define ETH_PCS10_25G_REG_PKG_ID0_IDENTIFIER_K2_E5_SHIFT                                                   0
+#define ETH_PCS10_25G_REG_PKG_ID1_K2_E5                                                                      0x00003cUL //Access:R    DataWidth:0x20   // Constant from package parameter PACK_IDENTIFIER bits 31:16.
+  #define ETH_PCS10_25G_REG_PKG_ID1_IDENTIFIER_K2_E5                                                         (0xffff<<0) // Constant from package parameter PACK_IDENTIFIER bits 31:16.
+  #define ETH_PCS10_25G_REG_PKG_ID1_IDENTIFIER_K2_E5_SHIFT                                                   0
+#define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_K2_E5                                                          0x000050UL //Access:RW   DataWidth:0x20   // EEE Control and Capabilities (exists only if EEE is available).
+  #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_LPI_FW_K2_E5                                                 (0x1<<0) // Mode for selecting select 40G EEE mode; 1 = Fast wake mode; 0 = Deep sleep for LPI function.
+  #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_LPI_FW_K2_E5_SHIFT                                           0
+  #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_EEE_10GBASE_KR_K2_E5                                         (0x1<<6) // When 1, EEE is supported for 10GBASE-KR.
+  #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_EEE_10GBASE_KR_K2_E5_SHIFT                                   6
+  #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_EEE_40GBASE_RAWAKE_K2_E5                                     (0x1<<8) // When 1, EEE fast wake is supported for 40GBASE-R.
+  #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_EEE_40GBASE_RAWAKE_K2_E5_SHIFT                               8
+  #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_EEE_40GBASE_RSLEEP_K2_E5                                     (0x1<<9) // When 1, EEE deep sleep is supported for 40GBASE-R.
+  #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_EEE_40GBASE_RSLEEP_K2_E5_SHIFT                               9
+#define ETH_PCS10_25G_REG_WAKE_ERR_COUNTER_K2_E5                                                             0x000058UL //Access:R    DataWidth:0x20   // EEE Wake error counter (exists only if EEE is available); Clears on read.
+  #define ETH_PCS10_25G_REG_WAKE_ERR_COUNTER_COUNTER_K2_E5                                                   (0xffff<<0) // Increments each time the LPI enters the RX_WTF state indicating a wake time fault; None roll-over.
+  #define ETH_PCS10_25G_REG_WAKE_ERR_COUNTER_COUNTER_K2_E5_SHIFT                                             0
+#define ETH_PCS10_25G_REG_BASER_STATUS1_K2_E5                                                                0x000080UL //Access:R    DataWidth:0x20   // Link Status Information.
+  #define ETH_PCS10_25G_REG_BASER_STATUS1_BLOCK_LOCK_K2_E5                                                   (0x1<<0) // 1=PCS locked to received blocks.
+  #define ETH_PCS10_25G_REG_BASER_STATUS1_BLOCK_LOCK_K2_E5_SHIFT                                             0
+  #define ETH_PCS10_25G_REG_BASER_STATUS1_HIGH_BER_K2_E5                                                     (0x1<<1) // 1=PCS reporting a high BER.
+  #define ETH_PCS10_25G_REG_BASER_STATUS1_HIGH_BER_K2_E5_SHIFT                                               1
+  #define ETH_PCS10_25G_REG_BASER_STATUS1_RECEIVE_LINK_K2_E5                                                 (0x1<<12) // Receive link status. 1=Link up; 0=link down.
+  #define ETH_PCS10_25G_REG_BASER_STATUS1_RECEIVE_LINK_K2_E5_SHIFT                                           12
+#define ETH_PCS10_25G_REG_BASER_STATUS2_K2_E5                                                                0x000084UL //Access:R    DataWidth:0x20   // Link Status latches and error counters.
+  #define ETH_PCS10_25G_REG_BASER_STATUS2_ERRORED_CNT_K2_E5                                                  (0xff<<0) // Errored blocks counter; None roll-over.
+  #define ETH_PCS10_25G_REG_BASER_STATUS2_ERRORED_CNT_K2_E5_SHIFT                                            0
+  #define ETH_PCS10_25G_REG_BASER_STATUS2_BER_COUNTER_K2_E5                                                  (0x3f<<8) // BER counter; None roll-over.
+  #define ETH_PCS10_25G_REG_BASER_STATUS2_BER_COUNTER_K2_E5_SHIFT                                            8
+  #define ETH_PCS10_25G_REG_BASER_STATUS2_HIGH_BER_K2_E5                                                     (0x1<<14) // BER flag; Latched high.
+  #define ETH_PCS10_25G_REG_BASER_STATUS2_HIGH_BER_K2_E5_SHIFT                                               14
+  #define ETH_PCS10_25G_REG_BASER_STATUS2_BLOCK_LOCK_K2_E5                                                   (0x1<<15) // Block Lock; Latched low.
+  #define ETH_PCS10_25G_REG_BASER_STATUS2_BLOCK_LOCK_K2_E5_SHIFT                                             15
+#define ETH_PCS10_25G_REG_SEED_A0_K2_E5                                                                      0x000088UL //Access:RW   DataWidth:0x20   // 10G Base-R Test Pattern Seed A bits 15:0.
+  #define ETH_PCS10_25G_REG_SEED_A0_SEED_K2_E5                                                               (0xffff<<0) // 10GBase-R Test Pattern Seed A: Bits 15:0.
+  #define ETH_PCS10_25G_REG_SEED_A0_SEED_K2_E5_SHIFT                                                         0
+#define ETH_PCS10_25G_REG_SEED_A1_K2_E5                                                                      0x00008cUL //Access:RW   DataWidth:0x20   // 10G Base-R Test Pattern Seed A bits 31:16.
+  #define ETH_PCS10_25G_REG_SEED_A1_SEED_K2_E5                                                               (0xffff<<0) // 10GBase-R Test Pattern Seed A: Bits 31:16.
+  #define ETH_PCS10_25G_REG_SEED_A1_SEED_K2_E5_SHIFT                                                         0
+#define ETH_PCS10_25G_REG_SEED_A2_K2_E5                                                                      0x000090UL //Access:RW   DataWidth:0x20   // 10G Base-R Test Pattern Seed A bits 47:32.
+  #define ETH_PCS10_25G_REG_SEED_A2_SEED_K2_E5                                                               (0xffff<<0) // 10GBase-R Test Pattern Seed A: Bits 47:32.
+  #define ETH_PCS10_25G_REG_SEED_A2_SEED_K2_E5_SHIFT                                                         0
+#define ETH_PCS10_25G_REG_SEED_A3_K2_E5                                                                      0x000094UL //Access:RW   DataWidth:0x20   // 10G Base-R Test Pattern Seed A bits 57:48.
+  #define ETH_PCS10_25G_REG_SEED_A3_SEED_K2_E5                                                               (0x3ff<<0) // 10GBase-R Test Pattern Seed A: Bits 57:48.
+  #define ETH_PCS10_25G_REG_SEED_A3_SEED_K2_E5_SHIFT                                                         0
+#define ETH_PCS10_25G_REG_SEED_B0_K2_E5                                                                      0x000098UL //Access:RW   DataWidth:0x20   // 10G Base-R Test Pattern Seed B bits 15:0.
+  #define ETH_PCS10_25G_REG_SEED_B0_SEED_K2_E5                                                               (0xffff<<0) // 10GBase-R Test Pattern Seed B: Bits 15:0.
+  #define ETH_PCS10_25G_REG_SEED_B0_SEED_K2_E5_SHIFT                                                         0
+#define ETH_PCS10_25G_REG_SEED_B1_K2_E5                                                                      0x00009cUL //Access:RW   DataWidth:0x20   // 10G Base-R Test Pattern Seed B bits 31:16.
+  #define ETH_PCS10_25G_REG_SEED_B1_SEED_K2_E5                                                               (0xffff<<0) // 10GBase-R Test Pattern Seed B: Bits 31:16.
+  #define ETH_PCS10_25G_REG_SEED_B1_SEED_K2_E5_SHIFT                                                         0
+#define ETH_PCS10_25G_REG_SEED_B2_K2_E5                                                                      0x0000a0UL //Access:RW   DataWidth:0x20   // 10G Base-R Test Pattern Seed B bits 47:32.
+  #define ETH_PCS10_25G_REG_SEED_B2_SEED_K2_E5                                                               (0xffff<<0) // 10GBase-R Test Pattern Seed B: Bits 47:32.
+  #define ETH_PCS10_25G_REG_SEED_B2_SEED_K2_E5_SHIFT                                                         0
+#define ETH_PCS10_25G_REG_SEED_B3_K2_E5                                                                      0x0000a4UL //Access:RW   DataWidth:0x20   // 10G Base-R Test Pattern Seed B bits 57:48.
+  #define ETH_PCS10_25G_REG_SEED_B3_SEED_K2_E5                                                               (0x3ff<<0) // 10GBase-R Test Pattern Seed B: Bits 57:48.
+  #define ETH_PCS10_25G_REG_SEED_B3_SEED_K2_E5_SHIFT                                                         0
+#define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_K2_E5                                                           0x0000a8UL //Access:RW   DataWidth:0x20   // Test Pattern Generator and Checker controls.
+  #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_DATA_PATTERN_SEL_K2_E5                                        (0x1<<0) // Data Pattern Select: 1=all Zero, 0=2x Local Fault; 10G only.
+  #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_DATA_PATTERN_SEL_K2_E5_SHIFT                                  0
+  #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_SELECT_SQUARE_K2_E5                                           (0x1<<1) // Select Square Wave (1) or Pseudo Random (0) test pattern; 10G only.
+  #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_SELECT_SQUARE_K2_E5_SHIFT                                     1
+  #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_RX_TESTPATTERN_K2_E5                                          (0x1<<2) // Receive test-pattern enable.
+  #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_RX_TESTPATTERN_K2_E5_SHIFT                                    2
+  #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_TX_TESTPATTERN_K2_E5                                          (0x1<<3) // Transmit test-pattern enable.
+  #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_TX_TESTPATTERN_K2_E5_SHIFT                                    3
+  #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_SELECT_RANDOM_K2_E5                                           (0x1<<7) // Select Random Idle test pattern (40G); Overrides bits 1:0 when set.
+  #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_SELECT_RANDOM_K2_E5_SHIFT                                     7
+#define ETH_PCS10_25G_REG_BASER_TEST_ERR_CNT_K2_E5                                                           0x0000acUL //Access:R    DataWidth:0x20   // Test Pattern Error Counter; Clears on read; None roll-over.
+  #define ETH_PCS10_25G_REG_BASER_TEST_ERR_CNT_COUNTER_K2_E5                                                 (0xffff<<0) // Test pattern error counter; Clears on read; None roll-over.
+  #define ETH_PCS10_25G_REG_BASER_TEST_ERR_CNT_COUNTER_K2_E5_SHIFT                                           0
+#define ETH_PCS10_25G_REG_BER_HIGH_ORDER_CNT_K2_E5                                                           0x0000b0UL //Access:R    DataWidth:0x20   // BER High Order Counter of BER bits 21:6; None roll-over.
+  #define ETH_PCS10_25G_REG_BER_HIGH_ORDER_CNT_BER_COUNTER_K2_E5                                             (0xffff<<0) // Bits 21:6 of BER counter; None roll-over.
+  #define ETH_PCS10_25G_REG_BER_HIGH_ORDER_CNT_BER_COUNTER_K2_E5_SHIFT                                       0
+#define ETH_PCS10_25G_REG_ERR_BLK_HIGH_ORDER_CNT_K2_E5                                                       0x0000b4UL //Access:R    DataWidth:0x20   // Error Blocks High Order Counter bits 21:8; None roll-over.
+  #define ETH_PCS10_25G_REG_ERR_BLK_HIGH_ORDER_CNT_ERRORED_BLOCKS_COUNTER_K2_E5                              (0x3fff<<0) // Bits 21:8 of Error Blocks counter; None roll-over.
+  #define ETH_PCS10_25G_REG_ERR_BLK_HIGH_ORDER_CNT_ERRORED_BLOCKS_COUNTER_K2_E5_SHIFT                        0
+  #define ETH_PCS10_25G_REG_ERR_BLK_HIGH_ORDER_CNT_HIGH_ORDER_PRESENT_K2_E5                                  (0x1<<15) // High order counter present; Always 1.
+  #define ETH_PCS10_25G_REG_ERR_BLK_HIGH_ORDER_CNT_HIGH_ORDER_PRESENT_K2_E5_SHIFT                            15
+#define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT1_K2_E5                                                        0x0000c8UL //Access:R    DataWidth:0x20   // Lane Alignment Status Bits and Block Lock.
+  #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT1_LANE_ALIGN_STATUS_K2_E5                                    (0x1<<12) // Lane alignment status; 1=All Receive lanes locked and aligned.
+  #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT1_LANE_ALIGN_STATUS_K2_E5_SHIFT                              12
+#define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_K2_E5                                                        0x0000d0UL //Access:R    DataWidth:0x20   // Lane Alignment Marker Lock Status bits.
+  #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_LANE0_MARKER_LOCK_K2_E5                                    (0x1<<0) // Lane 0 alignment marker lock.
+  #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_LANE0_MARKER_LOCK_K2_E5_SHIFT                              0
+  #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_LANE1_MARKER_LOCK_K2_E5                                    (0x1<<1) // Lane 1 alignment marker lock.
+  #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_LANE1_MARKER_LOCK_K2_E5_SHIFT                              1
+  #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_LANE2_MARKER_LOCK_K2_E5                                    (0x1<<2) // Lane 2 alignment marker lock.
+  #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_LANE2_MARKER_LOCK_K2_E5_SHIFT                              2
+  #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_LANE3_MARKER_LOCK_K2_E5                                    (0x1<<3) // Lane 3 alignment marker lock.
+  #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_LANE3_MARKER_LOCK_K2_E5_SHIFT                              3
+#define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE0_K2_E5                                                            0x000320UL //Access:R    DataWidth:0x20   // BIP Error Counter Lane 0; Clears on read; None roll-over.
+  #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE0_BIP_ERROR_COUNTER_K2_E5                                        (0xffff<<0) // BIP error counter lane 0; None roll-over.
+  #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE0_BIP_ERROR_COUNTER_K2_E5_SHIFT                                  0
+#define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE1_K2_E5                                                            0x000324UL //Access:R    DataWidth:0x20   // BIP Error Counter Lane 1; Clears on read; None roll-over.
+  #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE1_BIP_ERROR_COUNTER_K2_E5                                        (0xffff<<0) // BIP error counter lane 1; None roll-over.
+  #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE1_BIP_ERROR_COUNTER_K2_E5_SHIFT                                  0
+#define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE2_K2_E5                                                            0x000328UL //Access:R    DataWidth:0x20   // BIP Error Counter Lane 2; Clears on read; None roll-over.
+  #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE2_BIP_ERROR_COUNTER_K2_E5                                        (0xffff<<0) // BIP error counter lane 2; None roll-over.
+  #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE2_BIP_ERROR_COUNTER_K2_E5_SHIFT                                  0
+#define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE3_K2_E5                                                            0x00032cUL //Access:R    DataWidth:0x20   // BIP Error Counter Lane 3; Clears on read; None roll-over.
+  #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE3_BIP_ERROR_COUNTER_K2_E5                                        (0xffff<<0) // BIP error counter lane 3; None roll-over.
+  #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE3_BIP_ERROR_COUNTER_K2_E5_SHIFT                                  0
+#define ETH_PCS10_25G_REG_VENDOR_SCRATCH_K2_E5                                                               0x020000UL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Scratch Register.
+  #define ETH_PCS10_25G_REG_VENDOR_SCRATCH_SCRATCH_K2_E5                                                     (0xffff<<0) // Scratch Register; Register address to test read and write operation.
+  #define ETH_PCS10_25G_REG_VENDOR_SCRATCH_SCRATCH_K2_E5_SHIFT                                               0
+#define ETH_PCS10_25G_REG_VENDOR_CORE_REV_K2_E5                                                              0x020004UL //Access:R    DataWidth:0x20   // Vendor Specific Reg; Core Revision derived from DEV_VERSION package parameter.
+  #define ETH_PCS10_25G_REG_VENDOR_CORE_REV_REVISION_K2_E5                                                   (0xffff<<0) // Core Design version as defined by DEV_VERSION parameter in PCS package file.
+  #define ETH_PCS10_25G_REG_VENDOR_CORE_REV_REVISION_K2_E5_SHIFT                                             0
+#define ETH_PCS10_25G_REG_VENDOR_VL_INTVL_K2_E5                                                              0x020008UL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Set the amount of data between markers. (I.e. distance of markers-1).
+  #define ETH_PCS10_25G_REG_VENDOR_VL_INTVL_MARKER_COUNTER_K2_E5                                             (0xffff<<0) // A 16-bit value defining the amount of data between markers; (distance of markers-1).
+  #define ETH_PCS10_25G_REG_VENDOR_VL_INTVL_MARKER_COUNTER_K2_E5_SHIFT                                       0
+#define ETH_PCS10_25G_REG_VENDOR_TXLANE_THRESH_K2_E5                                                         0x02000cUL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Defines the transmit line decoupling FIFOs almost full threshold.
+  #define ETH_PCS10_25G_REG_VENDOR_TXLANE_THRESH_THRESHOLD_K2_E5                                             (0xf<<0) // A 4-bit value to define the transmit line decoupling FIFOs almost full threshold; Valid values are 4..9.
+  #define ETH_PCS10_25G_REG_VENDOR_TXLANE_THRESH_THRESHOLD_K2_E5_SHIFT                                       0
+#define ETH_PCS10_25G_REG_VENDOR_VL0_0_K2_E5                                                                 0x020020UL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Marker pattern for PCS Virtual Lane 0.
+  #define ETH_PCS10_25G_REG_VENDOR_VL0_0_M0_K2_E5                                                            (0xff<<0) // Lane 0 Marker pattern for m0.
+  #define ETH_PCS10_25G_REG_VENDOR_VL0_0_M0_K2_E5_SHIFT                                                      0
+  #define ETH_PCS10_25G_REG_VENDOR_VL0_0_M1_K2_E5                                                            (0xff<<8) // Lane 0 Marker pattern for m1.
+  #define ETH_PCS10_25G_REG_VENDOR_VL0_0_M1_K2_E5_SHIFT                                                      8
+#define ETH_PCS10_25G_REG_VENDOR_VL0_1_K2_E5                                                                 0x020024UL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Last byte of PCS Virtual Lane 0 marker pattern.
+  #define ETH_PCS10_25G_REG_VENDOR_VL0_1_M2_K2_E5                                                            (0xff<<0) // Lane 0 last btye of Marker pattern for m2.
+  #define ETH_PCS10_25G_REG_VENDOR_VL0_1_M2_K2_E5_SHIFT                                                      0
+#define ETH_PCS10_25G_REG_VENDOR_VL1_0_K2_E5                                                                 0x020028UL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Marker pattern for PCS Virtual Lane 1.
+  #define ETH_PCS10_25G_REG_VENDOR_VL1_0_M0_K2_E5                                                            (0xff<<0) // Lane 1 Marker pattern for m0.
+  #define ETH_PCS10_25G_REG_VENDOR_VL1_0_M0_K2_E5_SHIFT                                                      0
+  #define ETH_PCS10_25G_REG_VENDOR_VL1_0_M1_K2_E5                                                            (0xff<<8) // Lane 1 Marker pattern for m1.
+  #define ETH_PCS10_25G_REG_VENDOR_VL1_0_M1_K2_E5_SHIFT                                                      8
+#define ETH_PCS10_25G_REG_VENDOR_VL1_1_K2_E5                                                                 0x02002cUL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Last byte of PCS Virtual Lane 1 marker pattern.
+  #define ETH_PCS10_25G_REG_VENDOR_VL1_1_M2_K2_E5                                                            (0xff<<0) // Lane 1 last btye of Marker pattern for m2.
+  #define ETH_PCS10_25G_REG_VENDOR_VL1_1_M2_K2_E5_SHIFT                                                      0
+#define ETH_PCS10_25G_REG_VENDOR_VL2_0_K2_E5                                                                 0x020030UL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Marker pattern for PCS Virtual Lane 2.
+  #define ETH_PCS10_25G_REG_VENDOR_VL2_0_M0_K2_E5                                                            (0xff<<0) // Lane 2 Marker pattern for m0.
+  #define ETH_PCS10_25G_REG_VENDOR_VL2_0_M0_K2_E5_SHIFT                                                      0
+  #define ETH_PCS10_25G_REG_VENDOR_VL2_0_M1_K2_E5                                                            (0xff<<8) // Lane 2 Marker pattern for m1.
+  #define ETH_PCS10_25G_REG_VENDOR_VL2_0_M1_K2_E5_SHIFT                                                      8
+#define ETH_PCS10_25G_REG_VENDOR_VL2_1_K2_E5                                                                 0x020034UL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Last byte of PCS Virtual Lane 2 marker pattern.
+  #define ETH_PCS10_25G_REG_VENDOR_VL2_1_M2_K2_E5                                                            (0xff<<0) // Lane 2 last btye of Marker pattern for m2.
+  #define ETH_PCS10_25G_REG_VENDOR_VL2_1_M2_K2_E5_SHIFT                                                      0
+#define ETH_PCS10_25G_REG_VENDOR_VL3_0_K2_E5                                                                 0x020038UL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Marker pattern for PCS Virtual Lane 3.
+  #define ETH_PCS10_25G_REG_VENDOR_VL3_0_M0_K2_E5                                                            (0xff<<0) // Lane 3 Marker pattern for m0.
+  #define ETH_PCS10_25G_REG_VENDOR_VL3_0_M0_K2_E5_SHIFT                                                      0
+  #define ETH_PCS10_25G_REG_VENDOR_VL3_0_M1_K2_E5                                                            (0xff<<8) // Lane 3 Marker pattern for m1.
+  #define ETH_PCS10_25G_REG_VENDOR_VL3_0_M1_K2_E5_SHIFT                                                      8
+#define ETH_PCS10_25G_REG_VENDOR_VL3_1_K2_E5                                                                 0x02003cUL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Last byte of PCS Virtual Lane 3 marker pattern.
+  #define ETH_PCS10_25G_REG_VENDOR_VL3_1_M2_K2_E5                                                            (0xff<<0) // Lane 3 last btye of Marker pattern for m2.
+  #define ETH_PCS10_25G_REG_VENDOR_VL3_1_M2_K2_E5_SHIFT                                                      0
+#define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_K2_E5                                                              0x020040UL //Access:RW   DataWidth:0x20   // Vendor Specific Reg; Configure PCS supporting Clause 49 or 82 Encoder/Decoder, MLD.
+  #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_ENA_CLAUSE49_K2_E5                                               (0x1<<0) // When 0 PCS uses Clause 82 encoder/decoder functions; When 1 PCS uses Clause 49 encoder/decoder functions.
+  #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_ENA_CLAUSE49_K2_E5_SHIFT                                         0
+  #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_DISABLE_MLD_K2_E5                                                (0x1<<1) // When 0 PCS 4-lane MLD function is active; When 1 the MLD function is disabled.
+  #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_DISABLE_MLD_K2_E5_SHIFT                                          1
+  #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_ST_ENA_CLAUSE49_K2_E5                                            (0x1<<8) // Current status of Clause 49 setting.
+  #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_ST_ENA_CLAUSE49_K2_E5_SHIFT                                      8
+  #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_ST_DISABLE_MLD_K2_E5                                             (0x1<<9) // Current status of MLD setting.
+  #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_ST_DISABLE_MLD_K2_E5_SHIFT                                       9
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER0_K2_E5                                                       0x000000UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER0_RESERVEDFIELD0_K2_E5                                      (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER0_RESERVEDFIELD0_K2_E5_SHIFT                                0
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER1_K2_E5                                                       0x000004UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER1_RESERVEDFIELD1_K2_E5                                      (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER1_RESERVEDFIELD1_K2_E5_SHIFT                                0
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER2_K2_E5                                                       0x000008UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER2_RESERVEDFIELD2_K2_E5                                      (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER2_RESERVEDFIELD2_K2_E5_SHIFT                                0
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER3_K2_E5                                                       0x000010UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER3_RESERVEDFIELD3_K2_E5                                      (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER3_RESERVEDFIELD3_K2_E5_SHIFT                                0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER3_RESERVEDFIELD4_K2_E5                                      (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER3_RESERVEDFIELD4_K2_E5_SHIFT                                7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER4_K2_E5                                                       0x000014UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER4_RESERVEDFIELD5_K2_E5                                      (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER4_RESERVEDFIELD5_K2_E5_SHIFT                                0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER4_RESERVEDFIELD6_K2_E5                                      (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER4_RESERVEDFIELD6_K2_E5_SHIFT                                7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER5_K2_E5                                                       0x000018UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER5_RESERVEDFIELD7_K2_E5                                      (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER5_RESERVEDFIELD7_K2_E5_SHIFT                                0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER5_RESERVEDFIELD8_K2_E5                                      (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER5_RESERVEDFIELD8_K2_E5_SHIFT                                7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER6_K2_E5                                                       0x000024UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER7_K2_E5                                                       0x0000c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER7_RESERVEDFIELD10_K2_E5                                     (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER7_RESERVEDFIELD10_K2_E5_SHIFT                               0
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER8_K2_E5                                                       0x0000c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER8_RESERVEDFIELD11_K2_E5                                     (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER8_RESERVEDFIELD11_K2_E5_SHIFT                               0
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER9_K2_E5                                                       0x0000c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER9_RESERVEDFIELD12_K2_E5                                     (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER9_RESERVEDFIELD12_K2_E5_SHIFT                               0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER9_RESERVEDFIELD13_K2_E5                                     (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER9_RESERVEDFIELD13_K2_E5_SHIFT                               1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER9_RESERVEDFIELD14_K2_E5                                     (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER9_RESERVEDFIELD14_K2_E5_SHIFT                               2
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER9_RESERVEDFIELD15_K2_E5                                     (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER9_RESERVEDFIELD15_K2_E5_SHIFT                               4
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER10_K2_E5                                                      0x0000ccUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER10_RESERVEDFIELD16_K2_E5                                    (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER10_RESERVEDFIELD16_K2_E5_SHIFT                              0
+#define PHY_NW_IP_REG_PHY0_TOP_AFE_ATEST_CTRL0_K2_E5                                                         0x0000e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_AFE_ATEST_CTRL0_ATEST_EN_K2_E5                                              (0xf<<0) // Analog test mode enable. Controls the macro that drives the atest1_o/atest2_o bumps located over the CMU macro.  0x0 - off high-impedance 0x1 - CMU 0 0x3 - Lane 0 0x4 - Lane 1 0x5 - Lane 2 0x6 - Lane 3 0x15 - SoC circuitry. PHY input pins soc_atest1_i and soc_atest2_i are shorted to atest1_o and atest2_o respectively. rest - reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_AFE_ATEST_CTRL0_ATEST_EN_K2_E5_SHIFT                                        0
+#define PHY_NW_IP_REG_PHY0_TOP_AFE_ATEST_CTRL1_K2_E5                                                         0x0000e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_AFE_ATEST_CTRL1_ATEST_SEL_K2_E5                                             (0x3f<<0) // Analog test mode select. Controls the internal analog voltage or current from the respective macro sent to the atest1_o/atest2_o bumps located over the CMU macro.  Decoding table is provided in separate documentation.
+  #define PHY_NW_IP_REG_PHY0_TOP_AFE_ATEST_CTRL1_ATEST_SEL_K2_E5_SHIFT                                       0
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER11_K2_E5                                                      0x000100UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER11_RESERVEDFIELD17_K2_E5                                    (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER11_RESERVEDFIELD17_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER11_RESERVEDFIELD18_K2_E5                                    (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER11_RESERVEDFIELD18_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER11_RESERVEDFIELD19_K2_E5                                    (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER11_RESERVEDFIELD19_K2_E5_SHIFT                              2
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER11_RESERVEDFIELD20_K2_E5                                    (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER11_RESERVEDFIELD20_K2_E5_SHIFT                              6
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER12_K2_E5                                                      0x000140UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER12_RESERVEDFIELD21_K2_E5                                    (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER12_RESERVEDFIELD21_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER12_RESERVEDFIELD22_K2_E5                                    (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER12_RESERVEDFIELD22_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER12_RESERVEDFIELD23_K2_E5                                    (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER12_RESERVEDFIELD23_K2_E5_SHIFT                              2
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER12_RESERVEDFIELD24_K2_E5                                    (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER12_RESERVEDFIELD24_K2_E5_SHIFT                              6
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER13_K2_E5                                                      0x000150UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER13_RESERVEDFIELD25_K2_E5                                    (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER13_RESERVEDFIELD25_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER13_RESERVEDFIELD26_K2_E5                                    (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER13_RESERVEDFIELD26_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER13_RESERVEDFIELD27_K2_E5                                    (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER13_RESERVEDFIELD27_K2_E5_SHIFT                              2
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER13_RESERVEDFIELD28_K2_E5                                    (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER13_RESERVEDFIELD28_K2_E5_SHIFT                              3
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER13_RESERVEDFIELD29_K2_E5                                    (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER13_RESERVEDFIELD29_K2_E5_SHIFT                              4
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER13_RESERVEDFIELD30_K2_E5                                    (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER13_RESERVEDFIELD30_K2_E5_SHIFT                              5
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER13_RESERVEDFIELD31_K2_E5                                    (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER13_RESERVEDFIELD31_K2_E5_SHIFT                              6
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER14_K2_E5                                                      0x000154UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER14_RESERVEDFIELD32_K2_E5                                    (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER14_RESERVEDFIELD32_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER14_RESERVEDFIELD33_K2_E5                                    (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER14_RESERVEDFIELD33_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER14_RESERVEDFIELD34_K2_E5                                    (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER14_RESERVEDFIELD34_K2_E5_SHIFT                              2
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER14_RESERVEDFIELD35_K2_E5                                    (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER14_RESERVEDFIELD35_K2_E5_SHIFT                              3
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER14_RESERVEDFIELD36_K2_E5                                    (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER14_RESERVEDFIELD36_K2_E5_SHIFT                              4
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER14_RESERVEDFIELD37_K2_E5                                    (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER14_RESERVEDFIELD37_K2_E5_SHIFT                              5
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER14_RESERVEDFIELD38_K2_E5                                    (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER14_RESERVEDFIELD38_K2_E5_SHIFT                              6
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER15_K2_E5                                                      0x000158UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER15_RESERVEDFIELD39_K2_E5                                    (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER15_RESERVEDFIELD39_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER15_RESERVEDFIELD40_K2_E5                                    (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER15_RESERVEDFIELD40_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER15_RESERVEDFIELD41_K2_E5                                    (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER15_RESERVEDFIELD41_K2_E5_SHIFT                              2
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER15_RESERVEDFIELD42_K2_E5                                    (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER15_RESERVEDFIELD42_K2_E5_SHIFT                              3
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER15_RESERVEDFIELD43_K2_E5                                    (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER15_RESERVEDFIELD43_K2_E5_SHIFT                              4
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER15_RESERVEDFIELD44_K2_E5                                    (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER15_RESERVEDFIELD44_K2_E5_SHIFT                              5
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER15_RESERVEDFIELD45_K2_E5                                    (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER15_RESERVEDFIELD45_K2_E5_SHIFT                              6
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER16_K2_E5                                                      0x00015cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER16_RESERVEDFIELD46_K2_E5                                    (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER16_RESERVEDFIELD46_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER16_RESERVEDFIELD47_K2_E5                                    (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER16_RESERVEDFIELD47_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER16_RESERVEDFIELD48_K2_E5                                    (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER16_RESERVEDFIELD48_K2_E5_SHIFT                              2
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER16_RESERVEDFIELD49_K2_E5                                    (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER16_RESERVEDFIELD49_K2_E5_SHIFT                              3
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER16_RESERVEDFIELD50_K2_E5                                    (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER16_RESERVEDFIELD50_K2_E5_SHIFT                              4
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER16_RESERVEDFIELD51_K2_E5                                    (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER16_RESERVEDFIELD51_K2_E5_SHIFT                              5
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER16_RESERVEDFIELD52_K2_E5                                    (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER16_RESERVEDFIELD52_K2_E5_SHIFT                              6
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER17_K2_E5                                                      0x0003c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER17_RESERVEDFIELD53_K2_E5                                    (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER17_RESERVEDFIELD53_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER17_RESERVEDFIELD54_K2_E5                                    (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER17_RESERVEDFIELD54_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER17_RESERVEDFIELD55_K2_E5                                    (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER17_RESERVEDFIELD55_K2_E5_SHIFT                              2
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER17_RESERVEDFIELD56_K2_E5                                    (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER17_RESERVEDFIELD56_K2_E5_SHIFT                              7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER18_K2_E5                                                      0x0003c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER18_RESERVEDFIELD57_K2_E5                                    (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER18_RESERVEDFIELD57_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER18_RESERVEDFIELD58_K2_E5                                    (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER18_RESERVEDFIELD58_K2_E5_SHIFT                              7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER19_K2_E5                                                      0x0003c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER19_RESERVEDFIELD59_K2_E5                                    (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER19_RESERVEDFIELD59_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER19_RESERVEDFIELD60_K2_E5                                    (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER19_RESERVEDFIELD60_K2_E5_SHIFT                              7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER20_K2_E5                                                      0x0003ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER20_RESERVEDFIELD61_K2_E5                                    (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER20_RESERVEDFIELD61_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER20_RESERVEDFIELD62_K2_E5                                    (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER20_RESERVEDFIELD62_K2_E5_SHIFT                              7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER21_K2_E5                                                      0x0003d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER21_RESERVEDFIELD63_K2_E5                                    (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER21_RESERVEDFIELD63_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER21_RESERVEDFIELD64_K2_E5                                    (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER21_RESERVEDFIELD64_K2_E5_SHIFT                              7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER22_K2_E5                                                      0x0003d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER22_RESERVEDFIELD65_K2_E5                                    (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER22_RESERVEDFIELD65_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER22_RESERVEDFIELD66_K2_E5                                    (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER22_RESERVEDFIELD66_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER22_RESERVEDFIELD67_K2_E5                                    (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER22_RESERVEDFIELD67_K2_E5_SHIFT                              7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER23_K2_E5                                                      0x0003d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER23_RESERVEDFIELD68_K2_E5                                    (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER23_RESERVEDFIELD68_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER23_RESERVEDFIELD69_K2_E5                                    (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER23_RESERVEDFIELD69_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER23_RESERVEDFIELD70_K2_E5                                    (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER23_RESERVEDFIELD70_K2_E5_SHIFT                              3
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER23_RESERVEDFIELD71_K2_E5                                    (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER23_RESERVEDFIELD71_K2_E5_SHIFT                              7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER24_K2_E5                                                      0x0003dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER24_RESERVEDFIELD72_K2_E5                                    (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER24_RESERVEDFIELD72_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER24_RESERVEDFIELD73_K2_E5                                    (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER24_RESERVEDFIELD73_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER24_RESERVEDFIELD74_K2_E5                                    (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER24_RESERVEDFIELD74_K2_E5_SHIFT                              2
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER24_RESERVEDFIELD75_K2_E5                                    (0x1f<<3) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER24_RESERVEDFIELD75_K2_E5_SHIFT                              3
+#define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_LC0_CLK_CMU_CTRL1_K2_E5                                              0x0003e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_LC0_CLK_CMU_CTRL1_TBUS_OUT_CG_EN_K2_E5                             (0x1<<7) // Clock gate enable for the TBUS debug output branch of cm_lc0_clk_cmu.
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_LC0_CLK_CMU_CTRL1_TBUS_OUT_CG_EN_K2_E5_SHIFT                       7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER25_K2_E5                                                      0x0003e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER25_RESERVEDFIELD76_K2_E5                                    (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER25_RESERVEDFIELD76_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER25_RESERVEDFIELD77_K2_E5                                    (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER25_RESERVEDFIELD77_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER25_RESERVEDFIELD78_K2_E5                                    (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER25_RESERVEDFIELD78_K2_E5_SHIFT                              2
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER25_RESERVEDFIELD79_K2_E5                                    (0x1f<<3) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER25_RESERVEDFIELD79_K2_E5_SHIFT                              3
+#define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_LC0_CLK_CMUDIV_CTRL1_K2_E5                                           0x0003e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_LC0_CLK_CMUDIV_CTRL1_TBUS_OUT_CG_EN_K2_E5                          (0x1<<7) // Clock gate enable for the TBUS debug output branch of cm_lc0_clk_cmudiv.
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_LC0_CLK_CMUDIV_CTRL1_TBUS_OUT_CG_EN_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER26_K2_E5                                                      0x000400UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER26_RESERVEDFIELD80_K2_E5                                    (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER26_RESERVEDFIELD80_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER26_RESERVEDFIELD81_K2_E5                                    (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER26_RESERVEDFIELD81_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER26_RESERVEDFIELD82_K2_E5                                    (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER26_RESERVEDFIELD82_K2_E5_SHIFT                              7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER27_K2_E5                                                      0x000404UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER27_RESERVEDFIELD83_K2_E5                                    (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER27_RESERVEDFIELD83_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER27_RESERVEDFIELD84_K2_E5                                    (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER27_RESERVEDFIELD84_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER27_RESERVEDFIELD85_K2_E5                                    (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER27_RESERVEDFIELD85_K2_E5_SHIFT                              3
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER27_RESERVEDFIELD86_K2_E5                                    (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER27_RESERVEDFIELD86_K2_E5_SHIFT                              7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER28_K2_E5                                                      0x000408UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER28_RESERVEDFIELD87_K2_E5                                    (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER28_RESERVEDFIELD87_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER28_RESERVEDFIELD88_K2_E5                                    (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER28_RESERVEDFIELD88_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER28_RESERVEDFIELD89_K2_E5                                    (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER28_RESERVEDFIELD89_K2_E5_SHIFT                              2
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER28_RESERVEDFIELD90_K2_E5                                    (0x1f<<3) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER28_RESERVEDFIELD90_K2_E5_SHIFT                              3
+#define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL2_CTRL1_K2_E5                                              0x00040cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL2_CTRL1_TBUS_OUT_CG_EN_K2_E5                             (0x1<<7) // Clock gate enable for the TBUS debug output branch of cm_r0_clk_pll2.
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL2_CTRL1_TBUS_OUT_CG_EN_K2_E5_SHIFT                       7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER29_K2_E5                                                      0x000410UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER29_RESERVEDFIELD91_K2_E5                                    (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER29_RESERVEDFIELD91_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER29_RESERVEDFIELD92_K2_E5                                    (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER29_RESERVEDFIELD92_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER29_RESERVEDFIELD93_K2_E5                                    (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER29_RESERVEDFIELD93_K2_E5_SHIFT                              2
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER29_RESERVEDFIELD94_K2_E5                                    (0x1f<<3) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER29_RESERVEDFIELD94_K2_E5_SHIFT                              3
+#define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL2DIV_CTRL1_K2_E5                                           0x000414UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL2DIV_CTRL1_TBUS_OUT_CG_EN_K2_E5                          (0x1<<7) // Clock gate enable for the TBUS debug output branch of cm_r0_clk_pll2div.
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL2DIV_CTRL1_TBUS_OUT_CG_EN_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER30_K2_E5                                                      0x000418UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER30_RESERVEDFIELD95_K2_E5                                    (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER30_RESERVEDFIELD95_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER30_RESERVEDFIELD96_K2_E5                                    (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER30_RESERVEDFIELD96_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER30_RESERVEDFIELD97_K2_E5                                    (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER30_RESERVEDFIELD97_K2_E5_SHIFT                              2
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER30_RESERVEDFIELD98_K2_E5                                    (0x1f<<3) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER30_RESERVEDFIELD98_K2_E5_SHIFT                              3
+#define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL3_CTRL1_K2_E5                                              0x00041cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL3_CTRL1_TBUS_OUT_CG_EN_K2_E5                             (0x1<<7) // Clock gate enable for the TBUS debug output branch of cm_r0_clk_pll3.
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL3_CTRL1_TBUS_OUT_CG_EN_K2_E5_SHIFT                       7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER31_K2_E5                                                      0x000420UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER31_RESERVEDFIELD99_K2_E5                                    (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER31_RESERVEDFIELD99_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER31_RESERVEDFIELD100_K2_E5                                   (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER31_RESERVEDFIELD100_K2_E5_SHIFT                             1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER31_RESERVEDFIELD101_K2_E5                                   (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER31_RESERVEDFIELD101_K2_E5_SHIFT                             2
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER31_RESERVEDFIELD102_K2_E5                                   (0x1f<<3) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER31_RESERVEDFIELD102_K2_E5_SHIFT                             3
+#define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL3DIV_CTRL1_K2_E5                                           0x000424UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL3DIV_CTRL1_TBUS_OUT_CG_EN_K2_E5                          (0x1<<7) // Clock gate enable for the TBUS debug output branch of cm_r0_clk_pll3div.
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL3DIV_CTRL1_TBUS_OUT_CG_EN_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_TX_K2_E5                                                        0x000440UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_TX_CTRL_SRC_SEL_K2_E5                                         (0x3<<0) // Clock source select for lane 0 TX clock. 0x0: ln0_txclk_i PHY input clock 0x1: rx clock 0x2: cmu clock 0x3: test clock
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_TX_CTRL_SRC_SEL_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_TX_RESERVEDFIELD103_K2_E5                                     (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_TX_RESERVEDFIELD103_K2_E5_SHIFT                               2
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_TX_CTRL_BIST_CG_EN_K2_E5                                      (0x1<<4) // Clock gate enable for TX bist clock branch
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_TX_CTRL_BIST_CG_EN_K2_E5_SHIFT                                4
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_TX_RESERVEDFIELD104_K2_E5                                     (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_TX_RESERVEDFIELD104_K2_E5_SHIFT                               7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER32_K2_E5                                                      0x000444UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER32_RESERVEDFIELD105_K2_E5                                   (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER32_RESERVEDFIELD105_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER32_RESERVEDFIELD106_K2_E5                                   (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER32_RESERVEDFIELD106_K2_E5_SHIFT                             1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER32_RESERVEDFIELD107_K2_E5                                   (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER32_RESERVEDFIELD107_K2_E5_SHIFT                             2
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER32_RESERVEDFIELD108_K2_E5                                   (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER32_RESERVEDFIELD108_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_RX_K2_E5                                                        0x000448UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_RX_RESERVEDFIELD109_K2_E5                                     (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_RX_RESERVEDFIELD109_K2_E5_SHIFT                               0
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_RX_CTRL_CG_EN_K2_E5                                           (0x1<<4) // Clock gate enable for RX clock output to customer logics
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_RX_CTRL_CG_EN_K2_E5_SHIFT                                     4
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_RX_CTRL_BIST_CG_EN_K2_E5                                      (0x1<<5) // Clock gate enable for RX bist clock branch
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_RX_CTRL_BIST_CG_EN_K2_E5_SHIFT                                5
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_RX_RESERVEDFIELD110_K2_E5                                     (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_RX_RESERVEDFIELD110_K2_E5_SHIFT                               7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER33_K2_E5                                                      0x00044cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER33_RESERVEDFIELD111_K2_E5                                   (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER33_RESERVEDFIELD111_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER33_RESERVEDFIELD112_K2_E5                                   (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER33_RESERVEDFIELD112_K2_E5_SHIFT                             1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER33_RESERVEDFIELD113_K2_E5                                   (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER33_RESERVEDFIELD113_K2_E5_SHIFT                             2
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER33_RESERVEDFIELD114_K2_E5                                   (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER33_RESERVEDFIELD114_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER34_K2_E5                                                      0x000450UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER34_RESERVEDFIELD115_K2_E5                                   (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER34_RESERVEDFIELD115_K2_E5_SHIFT                             4
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER35_K2_E5                                                      0x000454UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER35_RESERVEDFIELD116_K2_E5                                   (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER35_RESERVEDFIELD116_K2_E5_SHIFT                             0
+#define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_TX_K2_E5                                                        0x000460UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_TX_CTRL_SRC_SEL_K2_E5                                         (0x3<<0) // Clock source select for lane 0 TX clock. 0x0: ln1_txclk_i PHY input clock 0x1: rx clock 0x2: cmu clock 0x3: test clock
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_TX_CTRL_SRC_SEL_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_TX_RESERVEDFIELD117_K2_E5                                     (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_TX_RESERVEDFIELD117_K2_E5_SHIFT                               2
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_TX_CTRL_BIST_CG_EN_K2_E5                                      (0x1<<4) // Clock gate enable for TX bist clock branch
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_TX_CTRL_BIST_CG_EN_K2_E5_SHIFT                                4
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_TX_RESERVEDFIELD118_K2_E5                                     (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_TX_RESERVEDFIELD118_K2_E5_SHIFT                               7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER36_K2_E5                                                      0x000464UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER36_RESERVEDFIELD119_K2_E5                                   (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER36_RESERVEDFIELD119_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER36_RESERVEDFIELD120_K2_E5                                   (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER36_RESERVEDFIELD120_K2_E5_SHIFT                             1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER36_RESERVEDFIELD121_K2_E5                                   (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER36_RESERVEDFIELD121_K2_E5_SHIFT                             2
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER36_RESERVEDFIELD122_K2_E5                                   (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER36_RESERVEDFIELD122_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_RX_K2_E5                                                        0x000468UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_RX_RESERVEDFIELD123_K2_E5                                     (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_RX_RESERVEDFIELD123_K2_E5_SHIFT                               0
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_RX_CTRL_CG_EN_K2_E5                                           (0x1<<4) // Clock gate enable for RX clock output to customer logics
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_RX_CTRL_CG_EN_K2_E5_SHIFT                                     4
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_RX_CTRL_BIST_CG_EN_K2_E5                                      (0x1<<5) // Clock gate enable for RX bist clock branch
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_RX_CTRL_BIST_CG_EN_K2_E5_SHIFT                                5
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_RX_RESERVEDFIELD124_K2_E5                                     (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_RX_RESERVEDFIELD124_K2_E5_SHIFT                               7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER37_K2_E5                                                      0x00046cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER37_RESERVEDFIELD125_K2_E5                                   (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER37_RESERVEDFIELD125_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER37_RESERVEDFIELD126_K2_E5                                   (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER37_RESERVEDFIELD126_K2_E5_SHIFT                             1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER37_RESERVEDFIELD127_K2_E5                                   (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER37_RESERVEDFIELD127_K2_E5_SHIFT                             2
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER37_RESERVEDFIELD128_K2_E5                                   (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER37_RESERVEDFIELD128_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER38_K2_E5                                                      0x000470UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER38_RESERVEDFIELD129_K2_E5                                   (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER38_RESERVEDFIELD129_K2_E5_SHIFT                             4
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER39_K2_E5                                                      0x000474UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER39_RESERVEDFIELD130_K2_E5                                   (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER39_RESERVEDFIELD130_K2_E5_SHIFT                             0
+#define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_TX_K2_E5                                                        0x000480UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_TX_CTRL_SRC_SEL_K2_E5                                         (0x3<<0) // Clock source select for lane 0 TX clock. 0x0: ln2_txclk_i PHY input clock 0x1: rx clock 0x2: cmu clock 0x3: test clock
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_TX_CTRL_SRC_SEL_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_TX_RESERVEDFIELD131_K2_E5                                     (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_TX_RESERVEDFIELD131_K2_E5_SHIFT                               2
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_TX_CTRL_BIST_CG_EN_K2_E5                                      (0x1<<4) // Clock gate enable for TX bist clock branch
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_TX_CTRL_BIST_CG_EN_K2_E5_SHIFT                                4
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_TX_RESERVEDFIELD132_K2_E5                                     (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_TX_RESERVEDFIELD132_K2_E5_SHIFT                               7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER40_K2_E5                                                      0x000484UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER40_RESERVEDFIELD133_K2_E5                                   (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER40_RESERVEDFIELD133_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER40_RESERVEDFIELD134_K2_E5                                   (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER40_RESERVEDFIELD134_K2_E5_SHIFT                             1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER40_RESERVEDFIELD135_K2_E5                                   (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER40_RESERVEDFIELD135_K2_E5_SHIFT                             2
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER40_RESERVEDFIELD136_K2_E5                                   (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER40_RESERVEDFIELD136_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_RX_K2_E5                                                        0x000488UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_RX_RESERVEDFIELD137_K2_E5                                     (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_RX_RESERVEDFIELD137_K2_E5_SHIFT                               0
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_RX_CTRL_CG_EN_K2_E5                                           (0x1<<4) // Clock gate enable for RX clock output to customer logics
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_RX_CTRL_CG_EN_K2_E5_SHIFT                                     4
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_RX_CTRL_BIST_CG_EN_K2_E5                                      (0x1<<5) // Clock gate enable for RX bist clock branch
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_RX_CTRL_BIST_CG_EN_K2_E5_SHIFT                                5
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_RX_RESERVEDFIELD138_K2_E5                                     (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_RX_RESERVEDFIELD138_K2_E5_SHIFT                               7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER41_K2_E5                                                      0x00048cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER41_RESERVEDFIELD139_K2_E5                                   (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER41_RESERVEDFIELD139_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER41_RESERVEDFIELD140_K2_E5                                   (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER41_RESERVEDFIELD140_K2_E5_SHIFT                             1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER41_RESERVEDFIELD141_K2_E5                                   (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER41_RESERVEDFIELD141_K2_E5_SHIFT                             2
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER41_RESERVEDFIELD142_K2_E5                                   (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER41_RESERVEDFIELD142_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER42_K2_E5                                                      0x000490UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER42_RESERVEDFIELD143_K2_E5                                   (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER42_RESERVEDFIELD143_K2_E5_SHIFT                             4
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER43_K2_E5                                                      0x000494UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER43_RESERVEDFIELD144_K2_E5                                   (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER43_RESERVEDFIELD144_K2_E5_SHIFT                             0
+#define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_TX_K2_E5                                                        0x0004a0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_TX_CTRL_SRC_SEL_K2_E5                                         (0x3<<0) // Clock source select for lane 0 TX clock. 0x0: ln3_txclk_i PHY input clock 0x1: rx clock 0x2: cmu clock 0x3: test clock
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_TX_CTRL_SRC_SEL_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_TX_RESERVEDFIELD145_K2_E5                                     (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_TX_RESERVEDFIELD145_K2_E5_SHIFT                               2
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_TX_CTRL_BIST_CG_EN_K2_E5                                      (0x1<<4) // Clock gate enable for TX bist clock branch
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_TX_CTRL_BIST_CG_EN_K2_E5_SHIFT                                4
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_TX_RESERVEDFIELD146_K2_E5                                     (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_TX_RESERVEDFIELD146_K2_E5_SHIFT                               7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER44_K2_E5                                                      0x0004a4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER44_RESERVEDFIELD147_K2_E5                                   (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER44_RESERVEDFIELD147_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER44_RESERVEDFIELD148_K2_E5                                   (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER44_RESERVEDFIELD148_K2_E5_SHIFT                             1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER44_RESERVEDFIELD149_K2_E5                                   (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER44_RESERVEDFIELD149_K2_E5_SHIFT                             2
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER44_RESERVEDFIELD150_K2_E5                                   (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER44_RESERVEDFIELD150_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_RX_K2_E5                                                        0x0004a8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_RX_RESERVEDFIELD151_K2_E5                                     (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_RX_RESERVEDFIELD151_K2_E5_SHIFT                               0
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_RX_CTRL_CG_EN_K2_E5                                           (0x1<<4) // Clock gate enable for RX clock output to customer logics
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_RX_CTRL_CG_EN_K2_E5_SHIFT                                     4
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_RX_CTRL_BIST_CG_EN_K2_E5                                      (0x1<<5) // Clock gate enable for RX bist clock branch
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_RX_CTRL_BIST_CG_EN_K2_E5_SHIFT                                5
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_RX_RESERVEDFIELD152_K2_E5                                     (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_RX_RESERVEDFIELD152_K2_E5_SHIFT                               7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER45_K2_E5                                                      0x0004acUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER45_RESERVEDFIELD153_K2_E5                                   (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER45_RESERVEDFIELD153_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER45_RESERVEDFIELD154_K2_E5                                   (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER45_RESERVEDFIELD154_K2_E5_SHIFT                             1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER45_RESERVEDFIELD155_K2_E5                                   (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER45_RESERVEDFIELD155_K2_E5_SHIFT                             2
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER45_RESERVEDFIELD156_K2_E5                                   (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER45_RESERVEDFIELD156_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER46_K2_E5                                                      0x0004b0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER46_RESERVEDFIELD157_K2_E5                                   (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER46_RESERVEDFIELD157_K2_E5_SHIFT                             4
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER47_K2_E5                                                      0x0004b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER47_RESERVEDFIELD158_K2_E5                                   (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER47_RESERVEDFIELD158_K2_E5_SHIFT                             0
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER48_K2_E5                                                      0x0004c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER48_RESERVEDFIELD159_K2_E5                                   (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER48_RESERVEDFIELD159_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER48_RESERVEDFIELD160_K2_E5                                   (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER48_RESERVEDFIELD160_K2_E5_SHIFT                             1
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER48_RESERVEDFIELD161_K2_E5                                   (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER48_RESERVEDFIELD161_K2_E5_SHIFT                             2
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER48_RESERVEDFIELD162_K2_E5                                   (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER48_RESERVEDFIELD162_K2_E5_SHIFT                             3
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER49_K2_E5                                                      0x0004c4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER49_RESERVEDFIELD163_K2_E5                                   (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER49_RESERVEDFIELD163_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER49_RESERVEDFIELD164_K2_E5                                   (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER49_RESERVEDFIELD164_K2_E5_SHIFT                             1
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER50_K2_E5                                                      0x0005c0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_PHY0_TOP_ERR_CTRL0_K2_E5                                                               0x000600UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_ERR_CTRL0_ERR_K2_E5                                                         (0x1<<0) // PHY error status. 0x0 - no error 0x1 - PHY has an internal error detected by firmware. PHY error code can be used to isolate error event.  Decoding table is provided in separate documentation.
+  #define PHY_NW_IP_REG_PHY0_TOP_ERR_CTRL0_ERR_K2_E5_SHIFT                                                   0
+#define PHY_NW_IP_REG_PHY0_TOP_ERR_CTRL1_K2_E5                                                               0x000604UL //Access:RW   DataWidth:0x8    // lower 8-bits of 16-bit PHY error code.  0x0 - indicates that there is no error rest - reserved
+#define PHY_NW_IP_REG_PHY0_TOP_ERR_CTRL2_K2_E5                                                               0x000608UL //Access:RW   DataWidth:0x8    // higher 8-bits of 16-bit PHY error code.  0x0 - indicates that there is no error rest - reserved
+#define PHY_NW_IP_REG_PHY0_TOP_ERR_STATUS0_K2_E5                                                             0x000614UL //Access:W    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_ERR_STATUS0_REGBUS_ERR_K2_E5                                                (0x1<<0) // Rebug error status.  Write 1 to clear.
+  #define PHY_NW_IP_REG_PHY0_TOP_ERR_STATUS0_REGBUS_ERR_K2_E5_SHIFT                                          0
+#define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_CTRL_K2_E5                                                    0x00061cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_CTRL_CLR_K2_E5                                              (0x1<<0) // Clear the debug info presented in REGBUS_ERR_INFO_STATUS* registers.
+  #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_CTRL_CLR_K2_E5_SHIFT                                        0
+#define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS0_K2_E5                                                 0x000620UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS0_ERR_TYPE_K2_E5                                      (0x3<<0) // Type of error: 1 = err ack 2 = timeout
+  #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS0_ERR_TYPE_K2_E5_SHIFT                                0
+  #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS0_TRANSFER_RW_K2_E5                                   (0x1<<2) // Errored register transfer type: 0 = read transfer 1 = write transfer
+  #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS0_TRANSFER_RW_K2_E5_SHIFT                             2
+#define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS1_K2_E5                                                 0x000624UL //Access:R    DataWidth:0x8    // Errored register transfer address low 8 bits
+#define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS2_K2_E5                                                 0x000628UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS2_TRANSFER_ADDR_MSB_K2_E5                             (0x7f<<0) // Errored register transfer address upper bits
+  #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS2_TRANSFER_ADDR_MSB_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS3_K2_E5                                                 0x00062cUL //Access:R    DataWidth:0x8    // Errored register transfer write data
+#define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS4_K2_E5                                                 0x000630UL //Access:R    DataWidth:0x8    // Errored register transfer write data bit enable
+#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2_E5                                                           0x000680UL //Access:RW   DataWidth:0x8    // lower 8-bits of the 16-bit digital test bus tbus address. Decoding table is provided in separate documentation.
+#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2_E5                                                          0x000684UL //Access:RW   DataWidth:0x8    // higher 8-bits of the 16-bit digital test bus tbus address. Decoding table is provided in separate documentation.
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER51_K2_E5                                                      0x000688UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER52_K2_E5                                                      0x00068cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER53_K2_E5                                                      0x000690UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2_E5                                                           0x0006c0UL //Access:R    DataWidth:0x8    // Digital test bus tbus output bits [7:0]
+#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2_E5                                                          0x0006c4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_F3_K2_E5                                                     (0xf<<0) // Digital test bus tbus output bits [11:8]
+  #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_F3_K2_E5_SHIFT                                               0
+#define PHY_NW_IP_REG_PHY0_TOP_SIM_CTRL_K2_E5                                                                0x000700UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_SIM_CTRL_SIM_1B_MODEL_K2_E5                                                 (0x1<<0) // Set if running a 1b simulation.  Firmware may check this field to discover its runtime context.  Do not set on actual silicon.
+  #define PHY_NW_IP_REG_PHY0_TOP_SIM_CTRL_SIM_1B_MODEL_K2_E5_SHIFT                                           0
+#define PHY_NW_IP_REG_PHY0_TOP_FW_CTRL_K2_E5                                                                 0x000704UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_TOP_FW_CTRL_RESERVEDFIELD169_K2_E5                                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_TOP_FW_CTRL_RESERVEDFIELD169_K2_E5_SHIFT                                        0
+  #define PHY_NW_IP_REG_PHY0_TOP_FW_CTRL_CRC_DISABLE_K2_E5                                                   (0x1<<1) // Prevents firmware from running program memory CRC integrity check at boot up. Must be written before releasing cpu_reset_i
+  #define PHY_NW_IP_REG_PHY0_TOP_FW_CTRL_CRC_DISABLE_K2_E5_SHIFT                                             1
+#define PHY_NW_IP_REG_PHY0_MB_CMD_K2_E5                                                                      0x000800UL //Access:RW   DataWidth:0x8    // Command to the PHY firmware. It is expected that only the APB master writes to the command register.  Upon a write to this register, CMD_FLAG is set automatically.
+#define PHY_NW_IP_REG_PHY0_MB_CMD_FLAG_K2_E5                                                                 0x000808UL //Access:W    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_MB_CMD_FLAG_F5_K2_E5                                                            (0x1<<0) // Indicates the presence of a new command to the PHY firmware. It is set automatically when CMD is written. It is expected to be cleared by the PHY firmware by writing 1 to it.
+  #define PHY_NW_IP_REG_PHY0_MB_CMD_FLAG_F5_K2_E5_SHIFT                                                      0
+#define PHY_NW_IP_REG_PHY0_MB_CMD_DATA0_K2_E5                                                                0x00080cUL //Access:RW   DataWidth:0x8    // Command auxiliary data or argument 0
+#define PHY_NW_IP_REG_PHY0_MB_CMD_DATA1_K2_E5                                                                0x000810UL //Access:RW   DataWidth:0x8    // Command auxiliary data or argument 1
+#define PHY_NW_IP_REG_PHY0_MB_CMD_DATA2_K2_E5                                                                0x000814UL //Access:RW   DataWidth:0x8    // Command auxiliary data or argument 2
+#define PHY_NW_IP_REG_PHY0_MB_CMD_DATA3_K2_E5                                                                0x000818UL //Access:RW   DataWidth:0x8    // Command auxiliary data or argument 3
+#define PHY_NW_IP_REG_PHY0_MB_CMD_DATA4_K2_E5                                                                0x00081cUL //Access:RW   DataWidth:0x8    // Command auxiliary data or argument 4
+#define PHY_NW_IP_REG_PHY0_MB_CMD_DATA5_K2_E5                                                                0x000820UL //Access:RW   DataWidth:0x8    // Command auxiliary data or argument 5
+#define PHY_NW_IP_REG_PHY0_MB_CMD_DATA6_K2_E5                                                                0x000824UL //Access:RW   DataWidth:0x8    // Command auxiliary data or argument 6
+#define PHY_NW_IP_REG_PHY0_MB_CMD_DATA7_K2_E5                                                                0x000828UL //Access:RW   DataWidth:0x8    // Command auxiliary data or argument 7
+#define PHY_NW_IP_REG_PHY0_MB_RSP_K2_E5                                                                      0x000840UL //Access:RW   DataWidth:0x8    // Response to the PHY firmware. It is expected that only the APB master writes to the Response register.  Upon a write to this register, RSP_FLAG is set automatically.
+#define PHY_NW_IP_REG_PHY0_MB_RSP_FLAG_K2_E5                                                                 0x000848UL //Access:W    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_MB_RSP_FLAG_F15_K2_E5                                                           (0x1<<0) // Indicates the presence of a new Response to the PHY firmware. It is set automatically when RSP is written. It is expected to be cleared by the PHY firmware by writing 1 to it.
+  #define PHY_NW_IP_REG_PHY0_MB_RSP_FLAG_F15_K2_E5_SHIFT                                                     0
+#define PHY_NW_IP_REG_PHY0_MB_RSP_DATA0_K2_E5                                                                0x00084cUL //Access:RW   DataWidth:0x8    // Response auxiliary data or argument 0
+#define PHY_NW_IP_REG_PHY0_MB_RSP_DATA1_K2_E5                                                                0x000850UL //Access:RW   DataWidth:0x8    // Response auxiliary data or argument 1
+#define PHY_NW_IP_REG_PHY0_MB_RSP_DATA2_K2_E5                                                                0x000854UL //Access:RW   DataWidth:0x8    // Response auxiliary data or argument 2
+#define PHY_NW_IP_REG_PHY0_MB_RSP_DATA3_K2_E5                                                                0x000858UL //Access:RW   DataWidth:0x8    // Response auxiliary data or argument 3
+#define PHY_NW_IP_REG_PHY0_MB_RSP_DATA4_K2_E5                                                                0x00085cUL //Access:RW   DataWidth:0x8    // Response auxiliary data or argument 4
+#define PHY_NW_IP_REG_PHY0_MB_RSP_DATA5_K2_E5                                                                0x000860UL //Access:RW   DataWidth:0x8    // Response auxiliary data or argument 5
+#define PHY_NW_IP_REG_PHY0_MB_RSP_DATA6_K2_E5                                                                0x000864UL //Access:RW   DataWidth:0x8    // Response auxiliary data or argument 6
+#define PHY_NW_IP_REG_PHY0_MB_RSP_DATA7_K2_E5                                                                0x000868UL //Access:RW   DataWidth:0x8    // Response auxiliary data or argument 7
+#define PHY_NW_IP_REG_PHY0_MB_RSP_DATA8_K2_E5                                                                0x00086cUL //Access:RW   DataWidth:0x8    // Response auxiliary data or argument 8
+#define PHY_NW_IP_REG_PHY0_MB_RSP_DATA9_K2_E5                                                                0x000870UL //Access:RW   DataWidth:0x8    // Response auxiliary data or argument 9
+#define PHY_NW_IP_REG_PHY0_MB_RSP_DATA10_K2_E5                                                               0x000874UL //Access:RW   DataWidth:0x8    // Response auxiliary data or argument 10
+#define PHY_NW_IP_REG_PHY0_MB_RSP_DATA11_K2_E5                                                               0x000878UL //Access:RW   DataWidth:0x8    // Response auxiliary data or argument 11
+#define PHY_NW_IP_REG_PHY0_MB_RSP_DATA12_K2_E5                                                               0x00087cUL //Access:RW   DataWidth:0x8    // Response auxiliary data or argument 12
+#define PHY_NW_IP_REG_PHY0_MB_RSP_DATA13_K2_E5                                                               0x000880UL //Access:RW   DataWidth:0x8    // Response auxiliary data or argument 13
+#define PHY_NW_IP_REG_PHY0_MB_RSP_DATA14_K2_E5                                                               0x000884UL //Access:RW   DataWidth:0x8    // Response auxiliary data or argument 14
+#define PHY_NW_IP_REG_PHY0_MB_RSP_DATA15_K2_E5                                                               0x000888UL //Access:RW   DataWidth:0x8    // Response auxiliary data or argument 15
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER54_K2_E5                                               0x000c00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER54_F32_K2_E5                                         (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER54_F32_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER55_K2_E5                                               0x000c04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER55_F33_K2_E5                                         (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER55_F33_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER56_K2_E5                                               0x000c08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER56_F34_K2_E5                                         (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER56_F34_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER57_K2_E5                                               0x000c0cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER57_F35_K2_E5                                         (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER57_F35_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER58_K2_E5                                               0x000c10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER58_F36_K2_E5                                         (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER58_F36_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER59_K2_E5                                               0x000c14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER59_F37_K2_E5                                         (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER59_F37_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER60_K2_E5                                               0x000c18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER60_F38_K2_E5                                         (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER60_F38_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER61_K2_E5                                               0x000c1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER61_F39_K2_E5                                         (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER61_F39_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER62_K2_E5                                               0x000c20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER62_F40_K2_E5                                         (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER62_F40_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER63_K2_E5                                               0x000c24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER63_F41_K2_E5                                         (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER63_F41_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER64_K2_E5                                               0x000c28UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER64_F42_K2_E5                                         (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER64_F42_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER65_K2_E5                                               0x000c2cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER65_F43_K2_E5                                         (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER65_F43_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER66_K2_E5                                               0x000c30UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER66_F44_K2_E5                                         (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER66_F44_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER67_K2_E5                                               0x000c34UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER67_F45_K2_E5                                         (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER67_F45_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER68_K2_E5                                               0x000c38UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER68_F46_K2_E5                                         (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER68_F46_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER69_K2_E5                                               0x000c3cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER69_F47_K2_E5                                         (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER69_F47_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER70_K2_E5                                               0x000c40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER70_F48_K2_E5                                         (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER70_F48_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER71_K2_E5                                               0x000c44UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER72_K2_E5                                               0x000c48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER72_F50_K2_E5                                         (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER72_F50_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER73_K2_E5                                               0x000c4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER73_F51_K2_E5                                         (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER73_F51_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER74_K2_E5                                               0x000c50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER74_F52_K2_E5                                         (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER74_F52_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER75_K2_E5                                               0x000c54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER75_F53_K2_E5                                         (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER75_F53_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER76_K2_E5                                               0x000c58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER76_F54_K2_E5                                         (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER76_F54_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER77_K2_E5                                               0x000c5cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER77_F55_K2_E5                                         (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER77_F55_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER78_K2_E5                                               0x000c60UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER78_F56_K2_E5                                         (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER78_F56_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER79_K2_E5                                               0x000c64UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER79_F57_K2_E5                                         (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER79_F57_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER80_K2_E5                                               0x000c68UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER80_F58_K2_E5                                         (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER80_F58_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER81_K2_E5                                               0x000c6cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER81_F59_K2_E5                                         (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER81_F59_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER82_K2_E5                                               0x000c70UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER82_F60_K2_E5                                         (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER82_F60_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER83_K2_E5                                               0x000c74UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER83_F61_K2_E5                                         (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER83_F61_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER84_K2_E5                                               0x000c78UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER84_F62_K2_E5                                         (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER84_F62_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER85_K2_E5                                               0x000c7cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER85_F63_K2_E5                                         (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER85_F63_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER86_K2_E5                                               0x000c80UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER86_F64_K2_E5                                         (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER86_F64_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER87_K2_E5                                               0x000c84UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER87_F65_K2_E5                                         (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER87_F65_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER88_K2_E5                                                0x000e00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER88_F66_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER88_F66_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER89_K2_E5                                                0x000e04UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER90_K2_E5                                                0x000e08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER90_F68_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER90_F68_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER91_K2_E5                                                0x000e0cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER91_F69_K2_E5                                          (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER91_F69_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER92_K2_E5                                                0x000e10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER92_F70_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER92_F70_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER93_K2_E5                                                0x000e14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER93_F71_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER93_F71_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER94_K2_E5                                                0x000e18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER94_F72_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER94_F72_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER95_K2_E5                                                0x000e1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER95_F73_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER95_F73_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER96_K2_E5                                                0x000e20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER96_F74_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER96_F74_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER97_K2_E5                                                0x000e24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER97_F75_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER97_F75_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER98_K2_E5                                                  0x001000UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER98_F76_K2_E5                                            (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER98_F76_K2_E5_SHIFT                                      0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER99_K2_E5                                                  0x001004UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER99_F77_K2_E5                                            (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER99_F77_K2_E5_SHIFT                                      0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER100_K2_E5                                                 0x001008UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER100_F78_K2_E5                                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER100_F78_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER101_K2_E5                                                 0x00100cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER102_K2_E5                                                 0x001010UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER102_F80_K2_E5                                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER102_F80_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER103_K2_E5                                                 0x001014UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER103_F81_K2_E5                                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER103_F81_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER104_K2_E5                                                 0x001018UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER104_F82_K2_E5                                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER104_F82_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER105_K2_E5                                                 0x00101cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER105_F83_K2_E5                                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER105_F83_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER106_K2_E5                                                 0x001020UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER106_F84_K2_E5                                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER106_F84_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER107_K2_E5                                                 0x001024UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER107_F85_K2_E5                                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER107_F85_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER108_K2_E5                                                 0x001028UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER108_F86_K2_E5                                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER108_F86_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER109_K2_E5                                                 0x00102cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER109_F87_K2_E5                                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER109_F87_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER110_K2_E5                                                 0x001030UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER110_F88_K2_E5                                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER110_F88_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER111_K2_E5                                                 0x001034UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER111_F89_K2_E5                                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER111_F89_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER112_K2_E5                                                 0x001038UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER112_F90_K2_E5                                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER112_F90_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER113_K2_E5                                                 0x00103cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER113_F91_K2_E5                                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER113_F91_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER114_K2_E5                                                 0x001040UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER114_F92_K2_E5                                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER114_F92_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER115_K2_E5                                                 0x001044UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER115_F93_K2_E5                                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER115_F93_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER116_K2_E5                                                 0x001048UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER116_F94_K2_E5                                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER116_F94_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER117_K2_E5                                                 0x00104cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER117_F95_K2_E5                                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER117_F95_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER118_K2_E5                                                 0x001050UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER118_F96_K2_E5                                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER118_F96_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER119_K2_E5                                                 0x001054UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER119_F97_K2_E5                                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER119_F97_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER120_K2_E5                                                 0x001058UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER120_F98_K2_E5                                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER120_F98_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER121_K2_E5                                                 0x00105cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER121_F99_K2_E5                                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER121_F99_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER122_K2_E5                                                 0x001060UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER122_F100_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER122_F100_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER123_K2_E5                                                 0x001064UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER123_F101_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER123_F101_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER124_K2_E5                                                 0x001068UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER124_F102_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER124_F102_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER125_K2_E5                                                 0x00106cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER125_F103_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER125_F103_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER126_K2_E5                                                 0x001070UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER126_F104_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER126_F104_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER127_K2_E5                                                 0x001074UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER127_F105_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER127_F105_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER128_K2_E5                                                 0x001078UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER128_F106_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER128_F106_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER129_K2_E5                                                 0x00107cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER129_F107_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER129_F107_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER130_K2_E5                                                 0x001080UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER130_F108_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER130_F108_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER131_K2_E5                                                 0x001084UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER131_F109_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER131_F109_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER132_K2_E5                                                 0x001088UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER132_F110_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER132_F110_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER133_K2_E5                                                 0x00108cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER133_F111_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER133_F111_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER134_K2_E5                                                 0x001090UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER134_F112_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER134_F112_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER135_K2_E5                                                 0x001094UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER135_F113_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER135_F113_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER136_K2_E5                                                 0x001098UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER136_F114_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER136_F114_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER137_K2_E5                                                 0x00109cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER137_F115_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER137_F115_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER138_K2_E5                                                 0x0010a0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER138_F116_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER138_F116_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER139_K2_E5                                                 0x0010a4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER139_F117_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER139_F117_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER140_K2_E5                                                 0x0010a8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER140_F118_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER140_F118_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER141_K2_E5                                                 0x0010acUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER141_F119_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER141_F119_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER142_K2_E5                                                 0x0010b0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER142_F120_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER142_F120_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER143_K2_E5                                                 0x0010b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER143_F121_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER143_F121_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER144_K2_E5                                                 0x0010b8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER144_F122_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER144_F122_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER145_K2_E5                                                 0x0010bcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER145_F123_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER145_F123_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER146_K2_E5                                                 0x0010c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER146_F124_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER146_F124_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER147_K2_E5                                                 0x0010c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER147_F125_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER147_F125_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER148_K2_E5                                                 0x0010c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER148_F126_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER148_F126_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER149_K2_E5                                                 0x0010ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER149_F127_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER149_F127_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER150_K2_E5                                                 0x0010d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER150_F128_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER150_F128_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER151_K2_E5                                                 0x0010d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER151_F129_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER151_F129_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER152_K2_E5                                                 0x0010d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER152_F130_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER152_F130_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER153_K2_E5                                                 0x0010dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER153_F131_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER153_F131_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER154_K2_E5                                                 0x0010e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER154_F132_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER154_F132_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER155_K2_E5                                                 0x0010e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER155_F133_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER155_F133_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER156_K2_E5                                                 0x0010e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER156_F134_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER156_F134_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER157_K2_E5                                                 0x0010ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER157_F135_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER157_F135_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER158_K2_E5                                                 0x0010f0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER158_F136_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER158_F136_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER159_K2_E5                                                 0x0010f4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER159_F137_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER159_F137_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER160_K2_E5                                                 0x0010f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER160_F138_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER160_F138_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER161_K2_E5                                                 0x0010fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER161_F139_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER161_F139_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER162_K2_E5                                                 0x001100UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER162_F140_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER162_F140_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER163_K2_E5                                                 0x001104UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER163_F141_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER163_F141_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER164_K2_E5                                                 0x001108UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER164_F142_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER164_F142_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER165_K2_E5                                                 0x00110cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER165_F143_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER165_F143_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER166_K2_E5                                                 0x001110UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER166_F144_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER166_F144_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER167_K2_E5                                                 0x001114UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER167_F145_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER167_F145_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER168_K2_E5                                                 0x001118UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER168_F146_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER168_F146_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER169_K2_E5                                                 0x00111cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER169_F147_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER169_F147_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER170_K2_E5                                                 0x001120UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER170_F148_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER170_F148_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER171_K2_E5                                                 0x001124UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER171_F149_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER171_F149_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER172_K2_E5                                                 0x001128UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER172_F150_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER172_F150_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER173_K2_E5                                                 0x00112cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER173_F151_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER173_F151_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER174_K2_E5                                                 0x001130UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER174_F152_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER174_F152_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER175_K2_E5                                                 0x001134UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER175_F153_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER175_F153_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER176_K2_E5                                                 0x001138UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER176_F154_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER176_F154_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER177_K2_E5                                                 0x00113cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER177_F155_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER177_F155_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER178_K2_E5                                                 0x001140UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER178_F156_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER178_F156_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER179_K2_E5                                                 0x001144UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER179_F157_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER179_F157_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER180_K2_E5                                                 0x001148UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER180_F158_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER180_F158_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER181_K2_E5                                                 0x00114cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER181_F159_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER181_F159_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER182_K2_E5                                                 0x001150UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER182_F160_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER182_F160_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER183_K2_E5                                                 0x001154UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER183_F161_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER183_F161_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER184_K2_E5                                                 0x001158UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER184_F162_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER184_F162_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER185_K2_E5                                                 0x00115cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER185_F163_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER185_F163_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER186_K2_E5                                                 0x001160UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER186_F164_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER186_F164_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER187_K2_E5                                                 0x001164UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER187_F165_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER187_F165_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER188_K2_E5                                                 0x001168UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER188_F166_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER188_F166_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER189_K2_E5                                                 0x00116cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER189_F167_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER189_F167_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER190_K2_E5                                                 0x001170UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER190_F168_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER190_F168_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER191_K2_E5                                                 0x001174UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER191_F169_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER191_F169_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER192_K2_E5                                                 0x001178UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER192_F170_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER192_F170_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER193_K2_E5                                                 0x00117cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER193_F171_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER193_F171_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER194_K2_E5                                                 0x001180UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER194_F172_K2_E5                                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER194_F172_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER195_K2_E5                                                 0x001184UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER195_F173_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER195_F173_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER196_K2_E5                                                 0x001188UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER196_F174_K2_E5                                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER196_F174_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER197_K2_E5                                                 0x00118cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER197_F175_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER197_F175_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER198_K2_E5                                                 0x001190UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER198_F176_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER198_F176_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER199_K2_E5                                                 0x001194UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER199_F177_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER199_F177_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER200_K2_E5                                                 0x001198UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER200_F178_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER200_F178_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER201_K2_E5                                                 0x00119cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER201_F179_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER201_F179_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER202_K2_E5                                                 0x0011a0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER202_F180_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER202_F180_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER203_K2_E5                                                 0x0011a4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER203_F181_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER203_F181_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER204_K2_E5                                                 0x0011a8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER204_F182_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER204_F182_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER205_K2_E5                                                 0x0011acUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER205_F183_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER205_F183_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER206_K2_E5                                                 0x0011b0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER206_F184_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER206_F184_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER207_K2_E5                                                 0x0011b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER207_F185_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER207_F185_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER208_K2_E5                                                 0x0011b8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER208_F186_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER208_F186_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER209_K2_E5                                                 0x0011bcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER209_F187_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER209_F187_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER210_K2_E5                                                 0x0011c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER210_F188_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER210_F188_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER211_K2_E5                                                 0x0011c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER211_F189_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER211_F189_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER212_K2_E5                                                 0x0011c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER212_F190_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER212_F190_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER213_K2_E5                                                 0x0011ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER213_F191_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER213_F191_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER214_K2_E5                                                 0x0011d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER214_F192_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER214_F192_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER215_K2_E5                                                 0x0011d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER215_F193_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER215_F193_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER216_K2_E5                                                 0x0011d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER216_F194_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER216_F194_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER217_K2_E5                                                 0x0011dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER217_F195_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER217_F195_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER218_K2_E5                                                 0x0011e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER218_F196_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER218_F196_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER219_K2_E5                                                 0x0011e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER219_F197_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER219_F197_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER220_K2_E5                                                 0x0011e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER220_F198_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER220_F198_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER221_K2_E5                                                 0x0011ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER221_F199_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER221_F199_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER222_K2_E5                                                 0x0011f0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER222_F200_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER222_F200_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER223_K2_E5                                                 0x0011f4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER223_F201_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER223_F201_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER224_K2_E5                                                 0x0011f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER224_F202_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER224_F202_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER225_K2_E5                                                 0x0011fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER225_F203_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER225_F203_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER226_K2_E5                                                 0x001200UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER226_F204_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER226_F204_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER227_K2_E5                                                 0x001204UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER227_F205_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER227_F205_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER228_K2_E5                                                 0x001208UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER228_F206_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER228_F206_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER229_K2_E5                                                 0x00120cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER229_F207_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER229_F207_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER230_K2_E5                                                 0x001210UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER230_F208_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER230_F208_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER231_K2_E5                                                 0x001214UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER231_F209_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER231_F209_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER232_K2_E5                                                 0x001218UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER232_F210_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER232_F210_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER233_K2_E5                                                 0x00121cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER233_F211_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER233_F211_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER234_K2_E5                                                 0x001220UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER234_F212_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER234_F212_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER235_K2_E5                                                 0x001224UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER235_F213_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER235_F213_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER236_K2_E5                                                 0x001228UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER236_F214_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER236_F214_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER237_K2_E5                                                 0x00122cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER237_F215_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER237_F215_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER238_K2_E5                                                 0x001230UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER238_F216_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER238_F216_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER239_K2_E5                                                 0x001234UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER239_F217_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER239_F217_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER240_K2_E5                                                 0x001238UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER240_F218_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER240_F218_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER241_K2_E5                                                 0x00123cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER241_F219_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER241_F219_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER242_K2_E5                                                 0x001240UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER242_F220_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER242_F220_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER243_K2_E5                                                 0x001244UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER243_F221_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER243_F221_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER244_K2_E5                                                 0x001248UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER244_F222_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER244_F222_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER245_K2_E5                                                 0x001400UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER245_F223_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER245_F223_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER246_K2_E5                                                 0x001404UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER246_F224_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER246_F224_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER247_K2_E5                                                 0x001408UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER247_F225_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER247_F225_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER248_K2_E5                                                 0x00140cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER249_K2_E5                                                 0x001410UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER249_F227_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER249_F227_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER250_K2_E5                                                 0x001414UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER250_F228_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER250_F228_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER251_K2_E5                                                 0x001418UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER251_F229_K2_E5                                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER251_F229_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER252_K2_E5                                                 0x00141cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER252_F230_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER252_F230_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER253_K2_E5                                                 0x001420UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER253_F231_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER253_F231_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER254_K2_E5                                                 0x001424UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER254_F232_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER254_F232_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER255_K2_E5                                                 0x001428UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER255_F233_K2_E5                                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER255_F233_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER256_K2_E5                                                 0x00142cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER256_F234_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER256_F234_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER257_K2_E5                                                 0x001430UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER257_F235_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER257_F235_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER258_K2_E5                                                 0x001434UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER258_F236_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER258_F236_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER259_K2_E5                                                 0x001438UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER259_F237_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER259_F237_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER260_K2_E5                                                 0x00143cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER260_F238_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER260_F238_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER261_K2_E5                                                 0x001440UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER261_F239_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER261_F239_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER262_K2_E5                                                 0x001444UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER262_F240_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER262_F240_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER263_K2_E5                                                 0x001448UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER263_F241_K2_E5                                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER263_F241_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER264_K2_E5                                                 0x00144cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER264_F242_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER264_F242_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER265_K2_E5                                                 0x001450UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER265_F243_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER265_F243_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER266_K2_E5                                                 0x001454UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER266_F244_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER266_F244_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER267_K2_E5                                                 0x001458UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER267_F245_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER267_F245_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER268_K2_E5                                                 0x00145cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER268_F246_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER268_F246_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER269_K2_E5                                                 0x001460UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER269_F247_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER269_F247_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER270_K2_E5                                                 0x001464UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER270_F248_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER270_F248_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER271_K2_E5                                                 0x001468UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER271_F249_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER271_F249_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER272_K2_E5                                                 0x00146cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER272_F250_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER272_F250_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER273_K2_E5                                                 0x001470UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER273_F251_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER273_F251_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER274_K2_E5                                                 0x001474UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER274_F252_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER274_F252_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER275_K2_E5                                                 0x001478UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER275_F253_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER275_F253_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER276_K2_E5                                                 0x00147cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER276_F254_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER276_F254_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER277_K2_E5                                                 0x001480UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER277_F255_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER277_F255_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER278_K2_E5                                                 0x001484UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER278_F256_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER278_F256_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER279_K2_E5                                                 0x001488UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER279_F257_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER279_F257_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER280_K2_E5                                                 0x00148cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER280_F258_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER280_F258_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER281_K2_E5                                                 0x001490UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER281_F259_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER281_F259_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER282_K2_E5                                                 0x001494UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER282_F260_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER282_F260_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER283_K2_E5                                                 0x001498UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER283_F261_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER283_F261_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER284_K2_E5                                                 0x00149cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER284_F262_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER284_F262_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER285_K2_E5                                                 0x0014a0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER285_F263_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER285_F263_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER286_K2_E5                                                 0x0014a4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER286_F264_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER286_F264_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER287_K2_E5                                                 0x0014a8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER287_F265_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER287_F265_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER288_K2_E5                                                 0x0014acUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER288_F266_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER288_F266_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER289_K2_E5                                                 0x0014b0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER289_F267_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER289_F267_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER290_K2_E5                                                 0x0014b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER290_F268_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER290_F268_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER291_K2_E5                                                 0x0014b8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER291_F269_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER291_F269_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER292_K2_E5                                                 0x0014bcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER292_F270_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER292_F270_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER293_K2_E5                                                 0x0014c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER293_F271_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER293_F271_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER294_K2_E5                                                 0x0014c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER294_F272_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER294_F272_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER295_K2_E5                                                 0x0014c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER295_F273_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER295_F273_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER296_K2_E5                                                 0x0014ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER296_F274_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER296_F274_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER297_K2_E5                                                 0x0014d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER297_F275_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER297_F275_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER298_K2_E5                                                 0x0014d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER298_F276_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER298_F276_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER299_K2_E5                                                 0x0014d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER299_F277_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER299_F277_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER300_K2_E5                                                 0x0014dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER300_F278_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER300_F278_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER301_K2_E5                                                 0x0014e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER301_F279_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER301_F279_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER302_K2_E5                                                 0x0014e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER302_F280_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER302_F280_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER303_K2_E5                                                 0x0014e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER303_F281_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER303_F281_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER304_K2_E5                                                 0x0014ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER304_F282_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER304_F282_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER305_K2_E5                                                 0x0014f0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER305_F283_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER305_F283_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER306_K2_E5                                                 0x0014f4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER306_F284_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER306_F284_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER307_K2_E5                                                 0x0014f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER307_F285_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER307_F285_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER308_K2_E5                                                 0x0014fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER308_F286_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER308_F286_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER309_K2_E5                                                 0x001500UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER309_F287_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER309_F287_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER310_K2_E5                                                 0x001504UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER310_F288_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER310_F288_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER311_K2_E5                                                 0x001508UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER311_F289_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER311_F289_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER312_K2_E5                                                 0x00150cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER312_F290_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER312_F290_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER313_K2_E5                                                 0x001510UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER313_F291_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER313_F291_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER314_K2_E5                                                 0x001514UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER314_F292_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER314_F292_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER315_K2_E5                                                 0x001518UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER315_F293_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER315_F293_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER316_K2_E5                                                 0x00151cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER316_F294_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER316_F294_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER317_K2_E5                                                 0x001520UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER317_F295_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER317_F295_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER318_K2_E5                                                 0x001524UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER318_F296_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER318_F296_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER319_K2_E5                                                 0x001528UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER319_F297_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER319_F297_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER320_K2_E5                                                 0x00152cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER320_F298_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER320_F298_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER321_K2_E5                                                 0x001530UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER321_F299_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER321_F299_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER322_K2_E5                                                 0x001534UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER322_F300_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER322_F300_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER323_K2_E5                                                 0x001538UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER323_F301_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER323_F301_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER324_K2_E5                                                 0x00153cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER324_F302_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER324_F302_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER325_K2_E5                                                 0x001540UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER325_F303_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER325_F303_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER326_K2_E5                                                 0x001544UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER326_F304_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER326_F304_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER327_K2_E5                                                 0x001548UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER327_F305_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER327_F305_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER328_K2_E5                                                 0x00154cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER328_F306_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER328_F306_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER329_K2_E5                                                 0x001550UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER329_F307_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER329_F307_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER330_K2_E5                                                 0x001554UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER330_F308_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER330_F308_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER331_K2_E5                                                 0x001558UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER331_F309_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER331_F309_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER332_K2_E5                                                 0x00155cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER332_F310_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER332_F310_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER333_K2_E5                                                 0x001560UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER333_F311_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER333_F311_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER334_K2_E5                                                 0x001564UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER334_F312_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER334_F312_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER335_K2_E5                                                 0x001568UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER335_F313_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER335_F313_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER336_K2_E5                                                 0x00156cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER336_F314_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER336_F314_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER337_K2_E5                                                 0x001570UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER337_F315_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER337_F315_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER338_K2_E5                                                 0x001574UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER338_F316_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER338_F316_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER339_K2_E5                                                 0x001578UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER339_F317_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER339_F317_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER340_K2_E5                                                 0x00157cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER340_F318_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER340_F318_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER341_K2_E5                                                 0x001580UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER341_F319_K2_E5                                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER341_F319_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER342_K2_E5                                                 0x001584UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER342_F320_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER342_F320_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER343_K2_E5                                                 0x001588UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER343_F321_K2_E5                                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER343_F321_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER344_K2_E5                                                 0x00158cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER344_F322_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER344_F322_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER345_K2_E5                                                 0x001590UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER345_F323_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER345_F323_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER346_K2_E5                                                 0x001594UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER346_F324_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER346_F324_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER347_K2_E5                                                 0x001598UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER347_F325_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER347_F325_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER348_K2_E5                                                 0x00159cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER348_F326_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER348_F326_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER349_K2_E5                                                 0x0015a0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER349_F327_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER349_F327_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER350_K2_E5                                                 0x0015a4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER350_F328_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER350_F328_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER351_K2_E5                                                 0x0015a8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER351_F329_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER351_F329_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER352_K2_E5                                                 0x0015acUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER352_F330_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER352_F330_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER353_K2_E5                                                 0x0015b0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER353_F331_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER353_F331_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER354_K2_E5                                                 0x0015b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER354_F332_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER354_F332_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER355_K2_E5                                                 0x0015b8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER355_F333_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER355_F333_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER356_K2_E5                                                 0x0015bcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER356_F334_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER356_F334_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER357_K2_E5                                                 0x0015c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER357_F335_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER357_F335_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER358_K2_E5                                                 0x0015c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER358_F336_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER358_F336_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER359_K2_E5                                                 0x0015c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER359_F337_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER359_F337_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER360_K2_E5                                                 0x0015ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER360_F338_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER360_F338_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER361_K2_E5                                                 0x0015d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER361_F339_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER361_F339_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER362_K2_E5                                                 0x0015d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER362_F340_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER362_F340_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER363_K2_E5                                                 0x0015d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER363_F341_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER363_F341_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER364_K2_E5                                                 0x0015dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER364_F342_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER364_F342_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER365_K2_E5                                                 0x0015e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER365_F343_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER365_F343_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER366_K2_E5                                                 0x0015e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER366_F344_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER366_F344_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER367_K2_E5                                                 0x0015e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER367_F345_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER367_F345_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER368_K2_E5                                                 0x0015ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER368_F346_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER368_F346_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER369_K2_E5                                                 0x0015f0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER369_F347_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER369_F347_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER370_K2_E5                                                 0x0015f4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER370_F348_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER370_F348_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER371_K2_E5                                                 0x0015f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER371_F349_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER371_F349_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER372_K2_E5                                                 0x0015fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER372_F350_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER372_F350_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER373_K2_E5                                                 0x001600UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER373_F351_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER373_F351_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER374_K2_E5                                                 0x001604UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER374_F352_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER374_F352_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER375_K2_E5                                                 0x001608UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER375_F353_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER375_F353_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER376_K2_E5                                                 0x00160cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER376_F354_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER376_F354_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER377_K2_E5                                                 0x001610UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER377_F355_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER377_F355_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER378_K2_E5                                                 0x001614UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER378_F356_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER378_F356_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER379_K2_E5                                                 0x001618UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER379_F357_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER379_F357_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER380_K2_E5                                                 0x00161cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER380_F358_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER380_F358_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER381_K2_E5                                                 0x001620UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER381_F359_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER381_F359_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER382_K2_E5                                                 0x001624UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER382_F360_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER382_F360_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER383_K2_E5                                                 0x001628UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER383_F361_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER383_F361_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER384_K2_E5                                                 0x00162cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER384_F362_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER384_F362_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER385_K2_E5                                                 0x001630UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER385_F363_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER385_F363_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER386_K2_E5                                                 0x001634UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER386_F364_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER386_F364_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER387_K2_E5                                                 0x001638UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER387_F365_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER387_F365_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER388_K2_E5                                                 0x00163cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER388_F366_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER388_F366_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER389_K2_E5                                                 0x001640UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER389_F367_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER389_F367_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER390_K2_E5                                                 0x001644UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER390_F368_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER390_F368_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER391_K2_E5                                                 0x001648UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER391_F369_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER391_F369_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER392_K2_E5                                                 0x001800UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER392_F370_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER392_F370_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER393_K2_E5                                                 0x001804UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER393_F371_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER393_F371_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER394_K2_E5                                                 0x001808UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER394_F372_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER394_F372_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER395_K2_E5                                                 0x00180cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER396_K2_E5                                                 0x001810UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER396_F374_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER396_F374_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER397_K2_E5                                                 0x001814UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER397_F375_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER397_F375_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER398_K2_E5                                                 0x001818UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER398_F376_K2_E5                                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER398_F376_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER399_K2_E5                                                 0x00181cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER399_F377_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER399_F377_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER400_K2_E5                                                 0x001820UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER400_F378_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER400_F378_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER401_K2_E5                                                 0x001824UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER401_F379_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER401_F379_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER402_K2_E5                                                 0x001828UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER402_F380_K2_E5                                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER402_F380_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER403_K2_E5                                                 0x00182cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER403_F381_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER403_F381_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER404_K2_E5                                                 0x001830UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER404_F382_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER404_F382_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER405_K2_E5                                                 0x001834UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER405_F383_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER405_F383_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER406_K2_E5                                                 0x001838UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER406_F384_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER406_F384_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER407_K2_E5                                                 0x00183cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER407_F385_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER407_F385_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER408_K2_E5                                                 0x001840UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER408_F386_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER408_F386_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER409_K2_E5                                                 0x001844UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER409_F387_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER409_F387_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER410_K2_E5                                                 0x001848UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER410_F388_K2_E5                                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER410_F388_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER411_K2_E5                                                 0x00184cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER411_F389_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER411_F389_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER412_K2_E5                                                 0x001850UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER412_F390_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER412_F390_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER413_K2_E5                                                 0x001854UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER413_F391_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER413_F391_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER414_K2_E5                                                 0x001858UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER414_F392_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER414_F392_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER415_K2_E5                                                 0x00185cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER415_F393_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER415_F393_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER416_K2_E5                                                 0x001860UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER416_F394_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER416_F394_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER417_K2_E5                                                 0x001864UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER417_F395_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER417_F395_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER418_K2_E5                                                 0x001868UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER418_F396_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER418_F396_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER419_K2_E5                                                 0x00186cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER419_F397_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER419_F397_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER420_K2_E5                                                 0x001870UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER420_F398_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER420_F398_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER421_K2_E5                                                 0x001874UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER421_F399_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER421_F399_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER422_K2_E5                                                 0x001878UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER422_F400_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER422_F400_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER423_K2_E5                                                 0x00187cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER423_F401_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER423_F401_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER424_K2_E5                                                 0x001880UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER424_F402_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER424_F402_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER425_K2_E5                                                 0x001884UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER425_F403_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER425_F403_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER426_K2_E5                                                 0x001888UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER426_F404_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER426_F404_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER427_K2_E5                                                 0x00188cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER427_F405_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER427_F405_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER428_K2_E5                                                 0x001890UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER428_F406_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER428_F406_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER429_K2_E5                                                 0x001894UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER429_F407_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER429_F407_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER430_K2_E5                                                 0x001898UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER430_F408_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER430_F408_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER431_K2_E5                                                 0x00189cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER431_F409_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER431_F409_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER432_K2_E5                                                 0x0018a0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER432_F410_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER432_F410_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER433_K2_E5                                                 0x0018a4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER433_F411_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER433_F411_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER434_K2_E5                                                 0x0018a8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER434_F412_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER434_F412_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER435_K2_E5                                                 0x0018acUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER435_F413_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER435_F413_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER436_K2_E5                                                 0x0018b0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER436_F414_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER436_F414_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER437_K2_E5                                                 0x0018b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER437_F415_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER437_F415_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER438_K2_E5                                                 0x0018b8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER438_F416_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER438_F416_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER439_K2_E5                                                 0x0018bcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER439_F417_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER439_F417_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER440_K2_E5                                                 0x0018c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER440_F418_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER440_F418_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER441_K2_E5                                                 0x0018c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER441_F419_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER441_F419_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER442_K2_E5                                                 0x0018c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER442_F420_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER442_F420_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER443_K2_E5                                                 0x0018ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER443_F421_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER443_F421_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER444_K2_E5                                                 0x0018d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER444_F422_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER444_F422_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER445_K2_E5                                                 0x0018d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER445_F423_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER445_F423_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER446_K2_E5                                                 0x0018d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER446_F424_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER446_F424_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER447_K2_E5                                                 0x0018dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER447_F425_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER447_F425_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER448_K2_E5                                                 0x0018e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER448_F426_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER448_F426_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER449_K2_E5                                                 0x0018e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER449_F427_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER449_F427_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER450_K2_E5                                                 0x0018e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER450_F428_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER450_F428_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER451_K2_E5                                                 0x0018ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER451_F429_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER451_F429_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER452_K2_E5                                                 0x0018f0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER452_F430_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER452_F430_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER453_K2_E5                                                 0x0018f4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER453_F431_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER453_F431_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER454_K2_E5                                                 0x0018f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER454_F432_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER454_F432_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER455_K2_E5                                                 0x0018fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER455_F433_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER455_F433_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER456_K2_E5                                                 0x001900UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER456_F434_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER456_F434_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER457_K2_E5                                                 0x001904UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER457_F435_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER457_F435_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER458_K2_E5                                                 0x001908UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER458_F436_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER458_F436_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER459_K2_E5                                                 0x00190cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER459_F437_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER459_F437_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER460_K2_E5                                                 0x001910UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER460_F438_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER460_F438_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER461_K2_E5                                                 0x001914UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER461_F439_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER461_F439_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER462_K2_E5                                                 0x001918UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER462_F440_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER462_F440_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER463_K2_E5                                                 0x00191cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER463_F441_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER463_F441_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER464_K2_E5                                                 0x001920UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER464_F442_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER464_F442_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER465_K2_E5                                                 0x001924UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER465_F443_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER465_F443_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER466_K2_E5                                                 0x001928UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER466_F444_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER466_F444_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER467_K2_E5                                                 0x00192cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER467_F445_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER467_F445_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER468_K2_E5                                                 0x001930UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER468_F446_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER468_F446_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER469_K2_E5                                                 0x001934UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER469_F447_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER469_F447_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER470_K2_E5                                                 0x001938UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER470_F448_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER470_F448_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER471_K2_E5                                                 0x00193cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER471_F449_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER471_F449_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER472_K2_E5                                                 0x001940UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER472_F450_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER472_F450_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER473_K2_E5                                                 0x001944UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER473_F451_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER473_F451_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER474_K2_E5                                                 0x001948UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER474_F452_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER474_F452_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER475_K2_E5                                                 0x00194cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER475_F453_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER475_F453_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER476_K2_E5                                                 0x001950UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER476_F454_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER476_F454_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER477_K2_E5                                                 0x001954UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER477_F455_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER477_F455_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER478_K2_E5                                                 0x001958UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER478_F456_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER478_F456_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER479_K2_E5                                                 0x00195cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER479_F457_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER479_F457_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER480_K2_E5                                                 0x001960UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER480_F458_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER480_F458_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER481_K2_E5                                                 0x001964UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER481_F459_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER481_F459_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER482_K2_E5                                                 0x001968UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER482_F460_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER482_F460_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER483_K2_E5                                                 0x00196cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER483_F461_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER483_F461_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER484_K2_E5                                                 0x001970UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER484_F462_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER484_F462_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER485_K2_E5                                                 0x001974UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER485_F463_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER485_F463_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER486_K2_E5                                                 0x001978UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER486_F464_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER486_F464_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER487_K2_E5                                                 0x00197cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER487_F465_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER487_F465_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER488_K2_E5                                                 0x001980UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER488_F466_K2_E5                                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER488_F466_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER489_K2_E5                                                 0x001984UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER489_F467_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER489_F467_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER490_K2_E5                                                 0x001988UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER490_F468_K2_E5                                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER490_F468_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER491_K2_E5                                                 0x00198cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER491_F469_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER491_F469_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER492_K2_E5                                                 0x001990UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER492_F470_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER492_F470_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER493_K2_E5                                                 0x001994UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER493_F471_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER493_F471_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER494_K2_E5                                                 0x001998UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER494_F472_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER494_F472_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER495_K2_E5                                                 0x00199cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER495_F473_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER495_F473_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER496_K2_E5                                                 0x0019a0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER496_F474_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER496_F474_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER497_K2_E5                                                 0x0019a4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER497_F475_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER497_F475_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER498_K2_E5                                                 0x0019a8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER498_F476_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER498_F476_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER499_K2_E5                                                 0x0019acUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER499_F477_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER499_F477_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER500_K2_E5                                                 0x0019b0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER500_F478_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER500_F478_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER501_K2_E5                                                 0x0019b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER501_F479_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER501_F479_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER502_K2_E5                                                 0x0019b8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER502_F480_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER502_F480_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER503_K2_E5                                                 0x0019bcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER503_F481_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER503_F481_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER504_K2_E5                                                 0x0019c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER504_F482_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER504_F482_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER505_K2_E5                                                 0x0019c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER505_F483_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER505_F483_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER506_K2_E5                                                 0x0019c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER506_F484_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER506_F484_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER507_K2_E5                                                 0x0019ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER507_F485_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER507_F485_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER508_K2_E5                                                 0x0019d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER508_F486_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER508_F486_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER509_K2_E5                                                 0x0019d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER509_F487_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER509_F487_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER510_K2_E5                                                 0x0019d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER510_F488_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER510_F488_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER511_K2_E5                                                 0x0019dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER511_F489_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER511_F489_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER512_K2_E5                                                 0x0019e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER512_F490_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER512_F490_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER513_K2_E5                                                 0x0019e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER513_F491_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER513_F491_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER514_K2_E5                                                 0x0019e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER514_F492_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER514_F492_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER515_K2_E5                                                 0x0019ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER515_F493_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER515_F493_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER516_K2_E5                                                 0x0019f0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER516_F494_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER516_F494_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER517_K2_E5                                                 0x0019f4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER517_F495_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER517_F495_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER518_K2_E5                                                 0x0019f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER518_F496_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER518_F496_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER519_K2_E5                                                 0x0019fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER519_F497_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER519_F497_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER520_K2_E5                                                 0x001a00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER520_F498_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER520_F498_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER521_K2_E5                                                 0x001a04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER521_F499_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER521_F499_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER522_K2_E5                                                 0x001a08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER522_F500_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER522_F500_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER523_K2_E5                                                 0x001a0cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER523_F501_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER523_F501_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER524_K2_E5                                                 0x001a10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER524_F502_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER524_F502_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER525_K2_E5                                                 0x001a14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER525_F503_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER525_F503_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER526_K2_E5                                                 0x001a18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER526_F504_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER526_F504_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER527_K2_E5                                                 0x001a1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER527_F505_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER527_F505_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER528_K2_E5                                                 0x001a20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER528_F506_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER528_F506_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER529_K2_E5                                                 0x001a24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER529_F507_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER529_F507_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER530_K2_E5                                                 0x001a28UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER530_F508_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER530_F508_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER531_K2_E5                                                 0x001a2cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER531_F509_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER531_F509_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER532_K2_E5                                                 0x001a30UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER532_F510_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER532_F510_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER533_K2_E5                                                 0x001a34UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER533_F511_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER533_F511_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER534_K2_E5                                                 0x001a38UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER534_F512_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER534_F512_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER535_K2_E5                                                 0x001a3cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER535_F513_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER535_F513_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER536_K2_E5                                                 0x001a40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER536_F514_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER536_F514_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER537_K2_E5                                                 0x001a44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER537_F515_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER537_F515_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER538_K2_E5                                                 0x001a48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER538_F516_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER538_F516_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER539_K2_E5                                                 0x001c00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER539_F517_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER539_F517_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER540_K2_E5                                                 0x001c04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER540_F518_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER540_F518_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER541_K2_E5                                                 0x001c08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER541_F519_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER541_F519_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER542_K2_E5                                                 0x001c0cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER543_K2_E5                                                 0x001c10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER543_F521_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER543_F521_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER544_K2_E5                                                 0x001c14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER544_F522_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER544_F522_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER545_K2_E5                                                 0x001c18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER545_F523_K2_E5                                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER545_F523_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER546_K2_E5                                                 0x001c1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER546_F524_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER546_F524_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER547_K2_E5                                                 0x001c20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER547_F525_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER547_F525_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER548_K2_E5                                                 0x001c24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER548_F526_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER548_F526_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER549_K2_E5                                                 0x001c28UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER549_F527_K2_E5                                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER549_F527_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER550_K2_E5                                                 0x001c2cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER550_F528_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER550_F528_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER551_K2_E5                                                 0x001c30UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER551_F529_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER551_F529_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER552_K2_E5                                                 0x001c34UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER552_F530_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER552_F530_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER553_K2_E5                                                 0x001c38UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER553_F531_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER553_F531_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER554_K2_E5                                                 0x001c3cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER554_F532_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER554_F532_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER555_K2_E5                                                 0x001c40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER555_F533_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER555_F533_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER556_K2_E5                                                 0x001c44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER556_F534_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER556_F534_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER557_K2_E5                                                 0x001c48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER557_F535_K2_E5                                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER557_F535_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER558_K2_E5                                                 0x001c4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER558_F536_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER558_F536_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER559_K2_E5                                                 0x001c50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER559_F537_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER559_F537_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER560_K2_E5                                                 0x001c54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER560_F538_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER560_F538_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER561_K2_E5                                                 0x001c58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER561_F539_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER561_F539_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER562_K2_E5                                                 0x001c5cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER562_F540_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER562_F540_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER563_K2_E5                                                 0x001c60UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER563_F541_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER563_F541_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER564_K2_E5                                                 0x001c64UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER564_F542_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER564_F542_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER565_K2_E5                                                 0x001c68UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER565_F543_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER565_F543_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER566_K2_E5                                                 0x001c6cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER566_F544_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER566_F544_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER567_K2_E5                                                 0x001c70UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER567_F545_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER567_F545_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER568_K2_E5                                                 0x001c74UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER568_F546_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER568_F546_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER569_K2_E5                                                 0x001c78UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER569_F547_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER569_F547_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER570_K2_E5                                                 0x001c7cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER570_F548_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER570_F548_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER571_K2_E5                                                 0x001c80UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER571_F549_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER571_F549_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER572_K2_E5                                                 0x001c84UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER572_F550_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER572_F550_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER573_K2_E5                                                 0x001c88UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER573_F551_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER573_F551_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER574_K2_E5                                                 0x001c8cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER574_F552_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER574_F552_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER575_K2_E5                                                 0x001c90UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER575_F553_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER575_F553_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER576_K2_E5                                                 0x001c94UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER576_F554_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER576_F554_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER577_K2_E5                                                 0x001c98UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER577_F555_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER577_F555_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER578_K2_E5                                                 0x001c9cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER578_F556_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER578_F556_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER579_K2_E5                                                 0x001ca0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER579_F557_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER579_F557_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER580_K2_E5                                                 0x001ca4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER580_F558_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER580_F558_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER581_K2_E5                                                 0x001ca8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER581_F559_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER581_F559_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER582_K2_E5                                                 0x001cacUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER582_F560_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER582_F560_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER583_K2_E5                                                 0x001cb0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER583_F561_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER583_F561_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER584_K2_E5                                                 0x001cb4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER584_F562_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER584_F562_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER585_K2_E5                                                 0x001cb8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER585_F563_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER585_F563_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER586_K2_E5                                                 0x001cbcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER586_F564_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER586_F564_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER587_K2_E5                                                 0x001cc0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER587_F565_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER587_F565_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER588_K2_E5                                                 0x001cc4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER588_F566_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER588_F566_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER589_K2_E5                                                 0x001cc8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER589_F567_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER589_F567_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER590_K2_E5                                                 0x001cccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER590_F568_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER590_F568_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER591_K2_E5                                                 0x001cd0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER591_F569_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER591_F569_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER592_K2_E5                                                 0x001cd4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER592_F570_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER592_F570_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER593_K2_E5                                                 0x001cd8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER593_F571_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER593_F571_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER594_K2_E5                                                 0x001cdcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER594_F572_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER594_F572_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER595_K2_E5                                                 0x001ce0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER595_F573_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER595_F573_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER596_K2_E5                                                 0x001ce4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER596_F574_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER596_F574_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER597_K2_E5                                                 0x001ce8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER597_F575_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER597_F575_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER598_K2_E5                                                 0x001cecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER598_F576_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER598_F576_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER599_K2_E5                                                 0x001cf0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER599_F577_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER599_F577_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER600_K2_E5                                                 0x001cf4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER600_F578_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER600_F578_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER601_K2_E5                                                 0x001cf8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER601_F579_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER601_F579_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER602_K2_E5                                                 0x001cfcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER602_F580_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER602_F580_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER603_K2_E5                                                 0x001d00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER603_F581_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER603_F581_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER604_K2_E5                                                 0x001d04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER604_F582_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER604_F582_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER605_K2_E5                                                 0x001d08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER605_F583_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER605_F583_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER606_K2_E5                                                 0x001d0cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER606_F584_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER606_F584_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER607_K2_E5                                                 0x001d10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER607_F585_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER607_F585_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER608_K2_E5                                                 0x001d14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER608_F586_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER608_F586_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER609_K2_E5                                                 0x001d18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER609_F587_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER609_F587_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER610_K2_E5                                                 0x001d1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER610_F588_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER610_F588_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER611_K2_E5                                                 0x001d20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER611_F589_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER611_F589_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER612_K2_E5                                                 0x001d24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER612_F590_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER612_F590_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER613_K2_E5                                                 0x001d28UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER613_F591_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER613_F591_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER614_K2_E5                                                 0x001d2cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER614_F592_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER614_F592_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER615_K2_E5                                                 0x001d30UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER615_F593_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER615_F593_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER616_K2_E5                                                 0x001d34UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER616_F594_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER616_F594_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER617_K2_E5                                                 0x001d38UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER617_F595_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER617_F595_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER618_K2_E5                                                 0x001d3cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER618_F596_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER618_F596_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER619_K2_E5                                                 0x001d40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER619_F597_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER619_F597_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER620_K2_E5                                                 0x001d44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER620_F598_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER620_F598_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER621_K2_E5                                                 0x001d48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER621_F599_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER621_F599_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER622_K2_E5                                                 0x001d4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER622_F600_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER622_F600_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER623_K2_E5                                                 0x001d50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER623_F601_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER623_F601_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER624_K2_E5                                                 0x001d54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER624_F602_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER624_F602_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER625_K2_E5                                                 0x001d58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER625_F603_K2_E5                                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER625_F603_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER626_K2_E5                                                 0x001d5cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER626_F604_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER626_F604_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER627_K2_E5                                                 0x001d60UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER627_F605_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER627_F605_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER628_K2_E5                                                 0x001d64UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER628_F606_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER628_F606_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER629_K2_E5                                                 0x001d68UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER629_F607_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER629_F607_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER630_K2_E5                                                 0x001d6cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER630_F608_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER630_F608_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER631_K2_E5                                                 0x001d70UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER631_F609_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER631_F609_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER632_K2_E5                                                 0x001d74UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER632_F610_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER632_F610_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER633_K2_E5                                                 0x001d78UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER633_F611_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER633_F611_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER634_K2_E5                                                 0x001d7cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER634_F612_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER634_F612_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER635_K2_E5                                                 0x001d80UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER635_F613_K2_E5                                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER635_F613_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER636_K2_E5                                                 0x001d84UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER636_F614_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER636_F614_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER637_K2_E5                                                 0x001d88UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER637_F615_K2_E5                                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER637_F615_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER638_K2_E5                                                 0x001d8cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER638_F616_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER638_F616_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER639_K2_E5                                                 0x001d90UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER639_F617_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER639_F617_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER640_K2_E5                                                 0x001d94UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER640_F618_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER640_F618_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER641_K2_E5                                                 0x001d98UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER641_F619_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER641_F619_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER642_K2_E5                                                 0x001d9cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER642_F620_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER642_F620_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER643_K2_E5                                                 0x001da0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER643_F621_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER643_F621_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER644_K2_E5                                                 0x001da4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER644_F622_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER644_F622_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER645_K2_E5                                                 0x001da8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER645_F623_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER645_F623_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER646_K2_E5                                                 0x001dacUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER646_F624_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER646_F624_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER647_K2_E5                                                 0x001db0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER647_F625_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER647_F625_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER648_K2_E5                                                 0x001db4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER648_F626_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER648_F626_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER649_K2_E5                                                 0x001db8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER649_F627_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER649_F627_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER650_K2_E5                                                 0x001dbcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER650_F628_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER650_F628_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER651_K2_E5                                                 0x001dc0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER651_F629_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER651_F629_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER652_K2_E5                                                 0x001dc4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER652_F630_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER652_F630_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER653_K2_E5                                                 0x001dc8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER653_F631_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER653_F631_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER654_K2_E5                                                 0x001dccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER654_F632_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER654_F632_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER655_K2_E5                                                 0x001dd0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER655_F633_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER655_F633_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER656_K2_E5                                                 0x001dd4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER656_F634_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER656_F634_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER657_K2_E5                                                 0x001dd8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER657_F635_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER657_F635_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER658_K2_E5                                                 0x001ddcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER658_F636_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER658_F636_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER659_K2_E5                                                 0x001de0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER659_F637_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER659_F637_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER660_K2_E5                                                 0x001de4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER660_F638_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER660_F638_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER661_K2_E5                                                 0x001de8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER661_F639_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER661_F639_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER662_K2_E5                                                 0x001decUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER662_F640_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER662_F640_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER663_K2_E5                                                 0x001df0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER663_F641_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER663_F641_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER664_K2_E5                                                 0x001df4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER664_F642_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER664_F642_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER665_K2_E5                                                 0x001df8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER665_F643_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER665_F643_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER666_K2_E5                                                 0x001dfcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER666_F644_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER666_F644_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER667_K2_E5                                                 0x001e00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER667_F645_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER667_F645_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER668_K2_E5                                                 0x001e04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER668_F646_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER668_F646_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER669_K2_E5                                                 0x001e08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER669_F647_K2_E5                                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER669_F647_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER670_K2_E5                                                 0x001e0cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER670_F648_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER670_F648_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER671_K2_E5                                                 0x001e10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER671_F649_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER671_F649_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER672_K2_E5                                                 0x001e14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER672_F650_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER672_F650_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER673_K2_E5                                                 0x001e18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER673_F651_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER673_F651_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER674_K2_E5                                                 0x001e1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER674_F652_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER674_F652_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER675_K2_E5                                                 0x001e20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER675_F653_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER675_F653_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER676_K2_E5                                                 0x001e24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER676_F654_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER676_F654_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER677_K2_E5                                                 0x001e28UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER677_F655_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER677_F655_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER678_K2_E5                                                 0x001e2cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER678_F656_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER678_F656_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER679_K2_E5                                                 0x001e30UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER679_F657_K2_E5                                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER679_F657_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER680_K2_E5                                                 0x001e34UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER680_F658_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER680_F658_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER681_K2_E5                                                 0x001e38UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER681_F659_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER681_F659_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER682_K2_E5                                                 0x001e3cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER682_F660_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER682_F660_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER683_K2_E5                                                 0x001e40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER683_F661_K2_E5                                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER683_F661_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER684_K2_E5                                                 0x001e44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER684_F662_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER684_F662_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER685_K2_E5                                                 0x001e48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER685_F663_K2_E5                                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER685_F663_K2_E5_SHIFT                                    0
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER686_K2_E5                                                  0x002000UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER686_RESERVEDFIELD170_K2_E5                               (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER686_RESERVEDFIELD170_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER686_RESERVEDFIELD171_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER686_RESERVEDFIELD171_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER686_RESERVEDFIELD172_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER686_RESERVEDFIELD172_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER686_RESERVEDFIELD173_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER686_RESERVEDFIELD173_K2_E5_SHIFT                         3
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER686_RESERVEDFIELD174_K2_E5                               (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER686_RESERVEDFIELD174_K2_E5_SHIFT                         4
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER686_RESERVEDFIELD175_K2_E5                               (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER686_RESERVEDFIELD175_K2_E5_SHIFT                         5
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER686_RESERVEDFIELD176_K2_E5                               (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER686_RESERVEDFIELD176_K2_E5_SHIFT                         6
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER687_K2_E5                                                  0x002004UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER687_RESERVEDFIELD177_K2_E5                               (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER687_RESERVEDFIELD177_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER687_RESERVEDFIELD178_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER687_RESERVEDFIELD178_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER687_RESERVEDFIELD179_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER687_RESERVEDFIELD179_K2_E5_SHIFT                         2
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER688_K2_E5                                                  0x00200cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER688_RESERVEDFIELD180_K2_E5                               (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER688_RESERVEDFIELD180_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER688_RESERVEDFIELD181_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER688_RESERVEDFIELD181_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER688_RESERVEDFIELD182_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER688_RESERVEDFIELD182_K2_E5_SHIFT                         2
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER689_K2_E5                                                  0x002014UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER689_RESERVEDFIELD183_K2_E5                               (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER689_RESERVEDFIELD183_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER689_RESERVEDFIELD184_K2_E5                               (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER689_RESERVEDFIELD184_K2_E5_SHIFT                         4
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER690_K2_E5                                                  0x002018UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER690_RESERVEDFIELD185_K2_E5                               (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER690_RESERVEDFIELD185_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER691_K2_E5                                                  0x00201cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER691_RESERVEDFIELD186_K2_E5                               (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER691_RESERVEDFIELD186_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER691_RESERVEDFIELD187_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER691_RESERVEDFIELD187_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER691_RESERVEDFIELD188_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER691_RESERVEDFIELD188_K2_E5_SHIFT                         2
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER692_K2_E5                                                  0x002020UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER692_RESERVEDFIELD189_K2_E5                               (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER692_RESERVEDFIELD189_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER692_RESERVEDFIELD190_K2_E5                               (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER692_RESERVEDFIELD190_K2_E5_SHIFT                         4
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER693_K2_E5                                                  0x002024UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER693_RESERVEDFIELD191_K2_E5                               (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER693_RESERVEDFIELD191_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER694_K2_E5                                                  0x002028UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER694_RESERVEDFIELD192_K2_E5                               (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER694_RESERVEDFIELD192_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER695_K2_E5                                                  0x002030UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER695_RESERVEDFIELD193_K2_E5                               (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER695_RESERVEDFIELD193_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER695_RESERVEDFIELD194_K2_E5                               (0x7<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER695_RESERVEDFIELD194_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER695_RESERVEDFIELD195_K2_E5                               (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER695_RESERVEDFIELD195_K2_E5_SHIFT                         4
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER696_K2_E5                                                  0x002068UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER696_RESERVEDFIELD196_K2_E5                               (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER696_RESERVEDFIELD196_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER696_RESERVEDFIELD197_K2_E5                               (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER696_RESERVEDFIELD197_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER696_RESERVEDFIELD198_K2_E5                               (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER696_RESERVEDFIELD198_K2_E5_SHIFT                         4
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER697_K2_E5                                                  0x00206cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER697_RESERVEDFIELD199_K2_E5                               (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER697_RESERVEDFIELD199_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER698_K2_E5                                                  0x00207cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER698_RESERVEDFIELD200_K2_E5                               (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER698_RESERVEDFIELD200_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_CMCP_CTRL0_K2_E5                                                       0x002080UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_CMCP_CTRL0_RESERVEDFIELD201_K2_E5                                    (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_CMCP_CTRL0_RESERVEDFIELD201_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_CMCP_CTRL0_RESERVEDFIELD202_K2_E5                                    (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_CMCP_CTRL0_RESERVEDFIELD202_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_CMCP_CTRL0_RESERVEDFIELD203_K2_E5                                    (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_CMCP_CTRL0_RESERVEDFIELD203_K2_E5_SHIFT                              2
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_CMCP_CTRL0_CMCP_CMUDIVCLK_DIV_K2_E5                                  (0x7<<5) // Divider control for CMU output clock cm0_clkdiv_o. This is the additional divided CMU clock for SoC logic. A different divider is employed to allow a different clock frequency from cm0_clk_o. This clock can be used in gearbox applications.  0x0 - DIV4 0x1 - DIV8 0x2 - DIV16 0x3 - DIV20 0x4 - DIV32 0x5 - DIV40 0x6 - DIV64 0x7 - DIV80  The output clock frequency is the serial data rate divided by the divider setting. For example, the output clock will be 805.66406MHz for the DIV32 setting at 25.78125Gbps.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_CMCP_CTRL0_CMCP_CMUDIVCLK_DIV_K2_E5_SHIFT                            5
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER699_K2_E5                                                  0x002084UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER699_RESERVEDFIELD204_K2_E5                               (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER699_RESERVEDFIELD204_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER699_RESERVEDFIELD205_K2_E5                               (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER699_RESERVEDFIELD205_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER699_RESERVEDFIELD206_K2_E5                               (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER699_RESERVEDFIELD206_K2_E5_SHIFT                         4
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER700_K2_E5                                                  0x002088UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER700_RESERVEDFIELD207_K2_E5                               (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER700_RESERVEDFIELD207_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER700_RESERVEDFIELD208_K2_E5                               (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER700_RESERVEDFIELD208_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER700_RESERVEDFIELD209_K2_E5                               (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER700_RESERVEDFIELD209_K2_E5_SHIFT                         4
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER700_RESERVEDFIELD210_K2_E5                               (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER700_RESERVEDFIELD210_K2_E5_SHIFT                         7
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER701_K2_E5                                                  0x00208cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER701_RESERVEDFIELD211_K2_E5                               (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER701_RESERVEDFIELD211_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER702_K2_E5                                                  0x002090UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER703_K2_E5                                                  0x002094UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER703_RESERVEDFIELD213_K2_E5                               (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER703_RESERVEDFIELD213_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER704_K2_E5                                                  0x002098UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER704_RESERVEDFIELD214_K2_E5                               (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER704_RESERVEDFIELD214_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER704_RESERVEDFIELD215_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER704_RESERVEDFIELD215_K2_E5_SHIFT                         1
+#define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_TSTCLK_CTRL0_K2_E5                                                     0x0020a0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_MUX_K2_E5                                   (0x3<<0) // Test clock MUX control. This is a test feature that allows certain internal clocks to be muxed into the half-rate TX clock path to provide visibility at the TX driver output.  0x0 - mission mode 0x1 - reference clock 0x2 - life clock 0x3 - CMU PLL word rate clock cm0_clk_o
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_MUX_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_DIV_K2_E5                                   (0x7<<2) // Test clock divider control. This register controls a programmable divider on the test clock path before clock distribution from the CMU macro to all lanes macros.  0x0 - DIV1 0x1 - DIV2 0x2 - DIV4 0x3 - DIV5 0x4 - DIV8 0x5 - DIV10 0x6 - DIV16 0x7 - DIV20
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_DIV_K2_E5_SHIFT                             2
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_TSTCLK_CTRL0_RESERVEDFIELD216_K2_E5                                  (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_TSTCLK_CTRL0_RESERVEDFIELD216_K2_E5_SHIFT                            5
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER705_K2_E5                                                  0x0020c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER705_RESERVEDFIELD217_K2_E5                               (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER705_RESERVEDFIELD217_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER705_RESERVEDFIELD218_K2_E5                               (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER705_RESERVEDFIELD218_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER706_K2_E5                                                  0x0020c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER706_RESERVEDFIELD219_K2_E5                               (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER706_RESERVEDFIELD219_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER706_RESERVEDFIELD220_K2_E5                               (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER706_RESERVEDFIELD220_K2_E5_SHIFT                         5
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER707_K2_E5                                                  0x0020c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER707_RESERVEDFIELD221_K2_E5                               (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER707_RESERVEDFIELD221_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER707_RESERVEDFIELD222_K2_E5                               (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER707_RESERVEDFIELD222_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER708_K2_E5                                                  0x0020ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER708_RESERVEDFIELD223_K2_E5                               (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER708_RESERVEDFIELD223_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER708_RESERVEDFIELD224_K2_E5                               (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER708_RESERVEDFIELD224_K2_E5_SHIFT                         5
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER709_K2_E5                                                  0x0020d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER709_RESERVEDFIELD225_K2_E5                               (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER709_RESERVEDFIELD225_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER709_RESERVEDFIELD226_K2_E5                               (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER709_RESERVEDFIELD226_K2_E5_SHIFT                         4
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER710_K2_E5                                                  0x002140UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER710_RESERVEDFIELD227_K2_E5                               (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER710_RESERVEDFIELD227_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER710_RESERVEDFIELD228_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER710_RESERVEDFIELD228_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER711_K2_E5                                                  0x002144UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER711_RESERVEDFIELD229_K2_E5                               (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER711_RESERVEDFIELD229_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER711_RESERVEDFIELD230_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER711_RESERVEDFIELD230_K2_E5_SHIFT                         3
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER711_RESERVEDFIELD231_K2_E5                               (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER711_RESERVEDFIELD231_K2_E5_SHIFT                         4
+#define PHY_NW_IP_REG_CMU_LC0_TOP_PHY_IF_STATUS_K2_E5                                                        0x002148UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_PHY_IF_STATUS_CMU_OK_K2_E5                                               (0x1<<0) // CMU OK status. 0x0 - CMU PLL is not locked 0x1 - indicates that CMU macro has successfully transitioned into the ACTIVE or PARTIAL power state, the PLL has locked to the reference clock, and all output clocks are at the correct frequency
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_PHY_IF_STATUS_CMU_OK_K2_E5_SHIFT                                         0
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER712_K2_E5                                                  0x002160UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER713_K2_E5                                                  0x002164UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_TOP_ERR_CTRL1_K2_E5                                                            0x002200UL //Access:RW   DataWidth:0x8    // lower 8-bits of 16-bit CMU error code.  0x0 - indicates that there is no error rest - reserved
+#define PHY_NW_IP_REG_CMU_LC0_TOP_ERR_CTRL2_K2_E5                                                            0x002204UL //Access:RW   DataWidth:0x8    // higher 8-bits of 16-bit CMU error code.  0x0 - indicates that there is no error rest - reserved
+#define PHY_NW_IP_REG_CMU_LC0_TOP_ERR_CTRL3_K2_E5                                                            0x002208UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_ERR_CTRL3_CMU_ERR_K2_E5                                                  (0x1<<0) // CMU macro error status. 0x0 - no error 0x1 - PHY CMU macro has an internal error detected by firmware. CMU error code can be used to isolate error event.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_ERR_CTRL3_CMU_ERR_K2_E5_SHIFT                                            0
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER714_K2_E5                                                  0x002228UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER714_RESERVEDFIELD232_K2_E5                               (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER714_RESERVEDFIELD232_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER714_RESERVEDFIELD233_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER714_RESERVEDFIELD233_K2_E5_SHIFT                         1
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER715_K2_E5                                                  0x00222cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER715_RESERVEDFIELD234_K2_E5                               (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER715_RESERVEDFIELD234_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER716_K2_E5                                                  0x002230UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER716_RESERVEDFIELD235_K2_E5                               (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER716_RESERVEDFIELD235_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER716_RESERVEDFIELD236_K2_E5                               (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER716_RESERVEDFIELD236_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER716_RESERVEDFIELD237_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER716_RESERVEDFIELD237_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER717_K2_E5                                                  0x002400UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER717_RESERVEDFIELD238_K2_E5                               (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER717_RESERVEDFIELD238_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER717_RESERVEDFIELD239_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER717_RESERVEDFIELD239_K2_E5_SHIFT                         1
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER718_K2_E5                                                  0x002404UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER718_RESERVEDFIELD240_K2_E5                               (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER718_RESERVEDFIELD240_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER718_RESERVEDFIELD241_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER718_RESERVEDFIELD241_K2_E5_SHIFT                         1
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER719_K2_E5                                                  0x002408UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER719_RESERVEDFIELD242_K2_E5                               (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER719_RESERVEDFIELD242_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER719_RESERVEDFIELD243_K2_E5                               (0x7<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER719_RESERVEDFIELD243_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER719_RESERVEDFIELD244_K2_E5                               (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER719_RESERVEDFIELD244_K2_E5_SHIFT                         4
+#define PHY_NW_IP_REG_CMU_LC0_PLL_AFE_REG_CTRL1_K2_E5                                                        0x00240cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_AFE_REG_CTRL1_CMPLL_V1P8_EN_K2_E5                                        (0x1<<0) // CMU PLL regulator vddha setting.   0x0 - vddha is 1.5V nominal 0x1 - vddha is 1.8V nominal  note: it is important that this register is maintained at the correct value matching the nominal vddha setting for all time following POR.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_AFE_REG_CTRL1_CMPLL_V1P8_EN_K2_E5_SHIFT                                  0
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER720_K2_E5                                                  0x002414UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER720_RESERVEDFIELD245_K2_E5                               (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER720_RESERVEDFIELD245_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER720_RESERVEDFIELD246_K2_E5                               (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER720_RESERVEDFIELD246_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER720_RESERVEDFIELD247_K2_E5                               (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER720_RESERVEDFIELD247_K2_E5_SHIFT                         4
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER721_K2_E5                                                  0x002418UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER721_RESERVEDFIELD248_K2_E5                               (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER721_RESERVEDFIELD248_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER721_RESERVEDFIELD249_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER721_RESERVEDFIELD249_K2_E5_SHIFT                         1
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER722_K2_E5                                                  0x002420UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER722_RESERVEDFIELD250_K2_E5                               (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER722_RESERVEDFIELD250_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER722_RESERVEDFIELD251_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER722_RESERVEDFIELD251_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER722_RESERVEDFIELD252_K2_E5                               (0x7<<5) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER722_RESERVEDFIELD252_K2_E5_SHIFT                         5
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER723_K2_E5                                                  0x002424UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER723_RESERVEDFIELD253_K2_E5                               (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER723_RESERVEDFIELD253_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER723_RESERVEDFIELD254_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER723_RESERVEDFIELD254_K2_E5_SHIFT                         3
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER723_RESERVEDFIELD255_K2_E5                               (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER723_RESERVEDFIELD255_K2_E5_SHIFT                         4
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER723_RESERVEDFIELD256_K2_E5                               (0x7<<5) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER723_RESERVEDFIELD256_K2_E5_SHIFT                         5
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER724_K2_E5                                                  0x002428UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER724_RESERVEDFIELD257_K2_E5                               (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER724_RESERVEDFIELD257_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER725_K2_E5                                                  0x002440UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER725_RESERVEDFIELD258_K2_E5                               (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER725_RESERVEDFIELD258_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER726_K2_E5                                                  0x002444UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER726_RESERVEDFIELD259_K2_E5                               (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER726_RESERVEDFIELD259_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER726_RESERVEDFIELD260_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER726_RESERVEDFIELD260_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER726_RESERVEDFIELD261_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER726_RESERVEDFIELD261_K2_E5_SHIFT                         2
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER727_K2_E5                                                  0x00244cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER727_RESERVEDFIELD262_K2_E5                               (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER727_RESERVEDFIELD262_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER728_K2_E5                                                  0x002450UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER728_RESERVEDFIELD263_K2_E5                               (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER728_RESERVEDFIELD263_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER729_K2_E5                                                  0x002454UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER729_RESERVEDFIELD264_K2_E5                               (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER729_RESERVEDFIELD264_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER729_RESERVEDFIELD265_K2_E5                               (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER729_RESERVEDFIELD265_K2_E5_SHIFT                         4
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER730_K2_E5                                                  0x002458UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER730_RESERVEDFIELD266_K2_E5                               (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER730_RESERVEDFIELD266_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER730_RESERVEDFIELD267_K2_E5                               (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER730_RESERVEDFIELD267_K2_E5_SHIFT                         4
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER731_K2_E5                                                  0x002460UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER731_RESERVEDFIELD268_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER731_RESERVEDFIELD268_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER731_RESERVEDFIELD269_K2_E5                               (0xf<<2) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER731_RESERVEDFIELD269_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER731_RESERVEDFIELD270_K2_E5                               (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER731_RESERVEDFIELD270_K2_E5_SHIFT                         6
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER732_K2_E5                                                  0x002464UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER732_RESERVEDFIELD271_K2_E5                               (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER732_RESERVEDFIELD271_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER732_RESERVEDFIELD272_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER732_RESERVEDFIELD272_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER732_RESERVEDFIELD273_K2_E5                               (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER732_RESERVEDFIELD273_K2_E5_SHIFT                         3
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER732_RESERVEDFIELD274_K2_E5                               (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER732_RESERVEDFIELD274_K2_E5_SHIFT                         6
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER733_K2_E5                                                  0x002468UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER733_RESERVEDFIELD275_K2_E5                               (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER733_RESERVEDFIELD275_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER734_K2_E5                                                  0x00246cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER734_RESERVEDFIELD276_K2_E5                               (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER734_RESERVEDFIELD276_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER735_K2_E5                                                  0x002470UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER736_K2_E5                                                  0x002480UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER737_K2_E5                                                  0x002484UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER738_K2_E5                                                  0x002488UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER739_K2_E5                                                  0x00248cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER739_F669_K2_E5                                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER739_F669_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER740_K2_E5                                                  0x002490UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER741_K2_E5                                                  0x002494UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER741_RESERVEDFIELD278_K2_E5                               (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER741_RESERVEDFIELD278_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER741_RESERVEDFIELD279_K2_E5                               (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER741_RESERVEDFIELD279_K2_E5_SHIFT                         4
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER742_K2_E5                                                  0x002498UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER743_K2_E5                                                  0x00249cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER743_F672_K2_E5                                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER743_F672_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER744_K2_E5                                                  0x0024a0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER745_K2_E5                                                  0x0024a4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER745_F674_K2_E5                                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER745_F674_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER746_K2_E5                                                  0x0024a8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER747_K2_E5                                                  0x0024acUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER747_F676_K2_E5                                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER747_F676_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER748_K2_E5                                                  0x0024b0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER749_K2_E5                                                  0x0024b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER749_F678_K2_E5                                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER749_F678_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER750_K2_E5                                                  0x0024b8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER751_K2_E5                                                  0x0024bcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER751_F680_K2_E5                                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER751_F680_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER752_K2_E5                                                  0x0024c0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER753_K2_E5                                                  0x0024c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER753_F682_K2_E5                                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER753_F682_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER754_K2_E5                                                  0x0024c8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER755_K2_E5                                                  0x0024ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER755_RESERVEDFIELD280_K2_E5                               (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER755_RESERVEDFIELD280_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER755_RESERVEDFIELD281_K2_E5                               (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER755_RESERVEDFIELD281_K2_E5_SHIFT                         4
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER755_RESERVEDFIELD282_K2_E5                               (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER755_RESERVEDFIELD282_K2_E5_SHIFT                         7
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER756_K2_E5                                                  0x0024d0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER757_K2_E5                                                  0x0024d4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER757_F685_K2_E5                                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER757_F685_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER758_K2_E5                                                  0x0024d8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER759_K2_E5                                                  0x0024dcUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER759_F687_K2_E5                                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER759_F687_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER760_K2_E5                                                  0x0024e0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER761_K2_E5                                                  0x0024e4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER761_F689_K2_E5                                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER761_F689_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER762_K2_E5                                                  0x0024e8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER762_RESERVEDFIELD283_K2_E5                               (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER762_RESERVEDFIELD283_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER762_RESERVEDFIELD284_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER762_RESERVEDFIELD284_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER762_RESERVEDFIELD285_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER762_RESERVEDFIELD285_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER763_K2_E5                                                  0x0024f0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER764_K2_E5                                                  0x002510UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER765_K2_E5                                                  0x002514UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER765_RESERVEDFIELD288_K2_E5                               (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER765_RESERVEDFIELD288_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER765_RESERVEDFIELD289_K2_E5                               (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER765_RESERVEDFIELD289_K2_E5_SHIFT                         6
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER765_RESERVEDFIELD290_K2_E5                               (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER765_RESERVEDFIELD290_K2_E5_SHIFT                         7
+#define PHY_NW_IP_REG_CMU_LC0_PLL_LOCKDET_STATUS_K2_E5                                                       0x002518UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_LOCKDET_STATUS_LOCKED_K2_E5                                              (0x1<<0) // CMU PLL lock detector status. 0x0 - CMU PLL is not locked 0x1 - CMU PLL has locked to the reference clock, and all output clocks are at the correct frequency
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_LOCKDET_STATUS_LOCKED_K2_E5_SHIFT                                        0
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER766_K2_E5                                                  0x002524UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER767_K2_E5                                                  0x002528UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER768_K2_E5                                                  0x00252cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER768_RESERVEDFIELD293_K2_E5                               (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER768_RESERVEDFIELD293_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER769_K2_E5                                                  0x002530UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER770_K2_E5                                                  0x002534UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER771_K2_E5                                                  0x002538UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER771_RESERVEDFIELD296_K2_E5                               (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER771_RESERVEDFIELD296_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER771_RESERVEDFIELD297_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER771_RESERVEDFIELD297_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER771_RESERVEDFIELD298_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER771_RESERVEDFIELD298_K2_E5_SHIFT                         2
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER772_K2_E5                                                  0x00253cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER773_K2_E5                                                  0x002540UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER774_K2_E5                                                  0x002544UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER774_RESERVEDFIELD301_K2_E5                               (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER774_RESERVEDFIELD301_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER775_K2_E5                                                  0x002550UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER775_RESERVEDFIELD302_K2_E5                               (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER775_RESERVEDFIELD302_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER775_RESERVEDFIELD303_K2_E5                               (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER775_RESERVEDFIELD303_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER775_RESERVEDFIELD304_K2_E5                               (0xf<<3) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER775_RESERVEDFIELD304_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER776_K2_E5                                                  0x002554UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER776_RESERVEDFIELD305_K2_E5                               (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER776_RESERVEDFIELD305_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER776_RESERVEDFIELD306_K2_E5                               (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER776_RESERVEDFIELD306_K2_E5_SHIFT                         7
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER777_K2_E5                                                  0x002560UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER778_K2_E5                                                  0x002564UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER779_K2_E5                                               0x002800UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER779_RESERVEDFIELD307_K2_E5                            (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER779_RESERVEDFIELD307_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER780_K2_E5                                               0x002804UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER780_RESERVEDFIELD308_K2_E5                            (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER780_RESERVEDFIELD308_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER781_K2_E5                                               0x002808UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER782_K2_E5                                               0x00280cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER782_RESERVEDFIELD310_K2_E5                            (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER782_RESERVEDFIELD310_K2_E5_SHIFT                      0
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER782_RESERVEDFIELD311_K2_E5                            (0xf<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER782_RESERVEDFIELD311_K2_E5_SHIFT                      1
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER783_K2_E5                                               0x002840UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER784_K2_E5                                               0x002844UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER784_RESERVEDFIELD313_K2_E5                            (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER784_RESERVEDFIELD313_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER785_K2_E5                                               0x002848UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER786_K2_E5                                               0x00284cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER786_RESERVEDFIELD315_K2_E5                            (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER786_RESERVEDFIELD315_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER787_K2_E5                                               0x002880UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER787_RESERVEDFIELD316_K2_E5                            (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER787_RESERVEDFIELD316_K2_E5_SHIFT                      0
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER787_RESERVEDFIELD317_K2_E5                            (0xf<<2) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER787_RESERVEDFIELD317_K2_E5_SHIFT                      2
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER788_K2_E5                                               0x002884UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER789_K2_E5                                               0x002888UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER789_RESERVEDFIELD319_K2_E5                            (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER789_RESERVEDFIELD319_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER790_K2_E5                                               0x00288cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER791_K2_E5                                               0x002890UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER791_RESERVEDFIELD321_K2_E5                            (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER791_RESERVEDFIELD321_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER792_K2_E5                                               0x002894UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER793_K2_E5                                               0x002898UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER793_RESERVEDFIELD323_K2_E5                            (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER793_RESERVEDFIELD323_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER794_K2_E5                                               0x0028c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER794_RESERVEDFIELD324_K2_E5                            (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER794_RESERVEDFIELD324_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER795_K2_E5                                               0x0028c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER795_RESERVEDFIELD325_K2_E5                            (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER795_RESERVEDFIELD325_K2_E5_SHIFT                      0
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER795_RESERVEDFIELD326_K2_E5                            (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER795_RESERVEDFIELD326_K2_E5_SHIFT                      4
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER796_K2_E5                                               0x0028c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER796_RESERVEDFIELD327_K2_E5                            (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER796_RESERVEDFIELD327_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER797_K2_E5                                               0x002900UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER797_RESERVEDFIELD328_K2_E5                            (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER797_RESERVEDFIELD328_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER798_K2_E5                                               0x002904UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER799_K2_E5                                               0x002908UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER800_K2_E5                                               0x00290cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER801_K2_E5                                               0x002910UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER802_K2_E5                                               0x002914UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER803_K2_E5                                               0x002918UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER804_K2_E5                                               0x00291cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER805_K2_E5                                               0x002920UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER805_RESERVEDFIELD336_K2_E5                            (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER805_RESERVEDFIELD336_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER806_K2_E5                                               0x002940UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER806_RESERVEDFIELD337_K2_E5                            (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER806_RESERVEDFIELD337_K2_E5_SHIFT                      0
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER806_RESERVEDFIELD338_K2_E5                            (0xf<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER806_RESERVEDFIELD338_K2_E5_SHIFT                      1
+#define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER807_K2_E5                                               0x002944UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER808_K2_E5                                              0x002c00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD340_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD340_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD341_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD341_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD342_K2_E5                           (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD342_K2_E5_SHIFT                     2
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD343_K2_E5                           (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD343_K2_E5_SHIFT                     3
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD344_K2_E5                           (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD344_K2_E5_SHIFT                     4
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD345_K2_E5                           (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD345_K2_E5_SHIFT                     5
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD346_K2_E5                           (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD346_K2_E5_SHIFT                     6
+#define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER809_K2_E5                                              0x002c04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD347_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD347_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD348_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD348_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD349_K2_E5                           (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD349_K2_E5_SHIFT                     2
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD350_K2_E5                           (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD350_K2_E5_SHIFT                     3
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD351_K2_E5                           (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD351_K2_E5_SHIFT                     4
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD352_K2_E5                           (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD352_K2_E5_SHIFT                     5
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD353_K2_E5                           (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD353_K2_E5_SHIFT                     6
+#define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER810_K2_E5                                              0x002c08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER810_RESERVEDFIELD354_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER810_RESERVEDFIELD354_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER810_RESERVEDFIELD355_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER810_RESERVEDFIELD355_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER811_K2_E5                                              0x002c0cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER811_RESERVEDFIELD356_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER811_RESERVEDFIELD356_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER811_RESERVEDFIELD357_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER811_RESERVEDFIELD357_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER812_K2_E5                                              0x002c10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER812_RESERVEDFIELD358_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER812_RESERVEDFIELD358_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER812_RESERVEDFIELD359_K2_E5                           (0x7f<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER812_RESERVEDFIELD359_K2_E5_SHIFT                     1
+#define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER813_K2_E5                                              0x002c14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER813_RESERVEDFIELD360_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER813_RESERVEDFIELD360_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER814_K2_E5                                              0x002c20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER814_RESERVEDFIELD361_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER814_RESERVEDFIELD361_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER815_K2_E5                                              0x002c40UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER816_K2_E5                                              0x002c44UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER817_K2_E5                                              0x002c48UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER818_K2_E5                                              0x002c4cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER819_K2_E5                                              0x002c50UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER820_K2_E5                                              0x002c54UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER821_K2_E5                                              0x002c58UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER822_K2_E5                                              0x002c5cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER823_K2_E5                                                   0x003000UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER823_RESERVEDFIELD362_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER823_RESERVEDFIELD362_K2_E5_SHIFT                          0
+#define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER824_K2_E5                                                   0x003004UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER824_RESERVEDFIELD363_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER824_RESERVEDFIELD363_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER824_RESERVEDFIELD364_K2_E5                                (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER824_RESERVEDFIELD364_K2_E5_SHIFT                          1
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER824_RESERVEDFIELD365_K2_E5                                (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER824_RESERVEDFIELD365_K2_E5_SHIFT                          2
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER824_RESERVEDFIELD366_K2_E5                                (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER824_RESERVEDFIELD366_K2_E5_SHIFT                          3
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER824_RESERVEDFIELD367_K2_E5                                (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER824_RESERVEDFIELD367_K2_E5_SHIFT                          4
+#define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER825_K2_E5                                                   0x00300cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER825_RESERVEDFIELD368_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER825_RESERVEDFIELD368_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER825_RESERVEDFIELD369_K2_E5                                (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER825_RESERVEDFIELD369_K2_E5_SHIFT                          1
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER825_RESERVEDFIELD370_K2_E5                                (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER825_RESERVEDFIELD370_K2_E5_SHIFT                          2
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER825_RESERVEDFIELD371_K2_E5                                (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER825_RESERVEDFIELD371_K2_E5_SHIFT                          3
+#define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER826_K2_E5                                                   0x003040UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER826_RESERVEDFIELD372_K2_E5                                (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER826_RESERVEDFIELD372_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER826_RESERVEDFIELD373_K2_E5                                (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER826_RESERVEDFIELD373_K2_E5_SHIFT                          2
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER826_RESERVEDFIELD374_K2_E5                                (0x7<<5) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER826_RESERVEDFIELD374_K2_E5_SHIFT                          5
+#define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER827_K2_E5                                                   0x003044UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER827_RESERVEDFIELD375_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER827_RESERVEDFIELD375_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER827_RESERVEDFIELD376_K2_E5                                (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER827_RESERVEDFIELD376_K2_E5_SHIFT                          1
+#define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER828_K2_E5                                                   0x003048UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER828_RESERVEDFIELD377_K2_E5                                (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER828_RESERVEDFIELD377_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER828_RESERVEDFIELD378_K2_E5                                (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER828_RESERVEDFIELD378_K2_E5_SHIFT                          2
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER828_RESERVEDFIELD379_K2_E5                                (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER828_RESERVEDFIELD379_K2_E5_SHIFT                          4
+#define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER829_K2_E5                                                   0x00304cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER830_K2_E5                                                   0x003080UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER830_RESERVEDFIELD381_K2_E5                                (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER830_RESERVEDFIELD381_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER830_RESERVEDFIELD382_K2_E5                                (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER830_RESERVEDFIELD382_K2_E5_SHIFT                          3
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER830_RESERVEDFIELD383_K2_E5                                (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER830_RESERVEDFIELD383_K2_E5_SHIFT                          6
+#define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER831_K2_E5                                                   0x003084UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER831_RESERVEDFIELD384_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER831_RESERVEDFIELD384_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER831_RESERVEDFIELD385_K2_E5                                (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER831_RESERVEDFIELD385_K2_E5_SHIFT                          1
+#define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER832_K2_E5                                                   0x003088UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER832_RESERVEDFIELD386_K2_E5                                (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER832_RESERVEDFIELD386_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER832_RESERVEDFIELD387_K2_E5                                (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER832_RESERVEDFIELD387_K2_E5_SHIFT                          2
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER832_RESERVEDFIELD388_K2_E5                                (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER832_RESERVEDFIELD388_K2_E5_SHIFT                          4
+#define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER833_K2_E5                                                   0x00308cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER834_K2_E5                                                   0x0030c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER834_RESERVEDFIELD390_K2_E5                                (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER834_RESERVEDFIELD390_K2_E5_SHIFT                          0
+#define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER835_K2_E5                                                   0x003140UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER835_RESERVEDFIELD391_K2_E5                                (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER835_RESERVEDFIELD391_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER835_RESERVEDFIELD392_K2_E5                                (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER835_RESERVEDFIELD392_K2_E5_SHIFT                          3
+#define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER836_K2_E5                                                   0x003144UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER836_RESERVEDFIELD393_K2_E5                                (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER836_RESERVEDFIELD393_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER836_RESERVEDFIELD394_K2_E5                                (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER836_RESERVEDFIELD394_K2_E5_SHIFT                          3
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER836_RESERVEDFIELD395_K2_E5                                (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER836_RESERVEDFIELD395_K2_E5_SHIFT                          4
+#define PHY_NW_IP_REG_CMU_R0_TOP_PHY_IF_STATUS_K2_E5                                                         0x003148UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_TOP_PHY_IF_STATUS_CMU_OK_K2_E5                                                (0x1<<0) // CMU OK status. 0x0 - CMU PLL is not locked 0x1 - indicates that CMU macro has successfully transitioned into the ACTIVE or PARTIAL power state, the PLL has locked to the reference clock, and all output clocks are at the correct frequency
+  #define PHY_NW_IP_REG_CMU_R0_TOP_PHY_IF_STATUS_CMU_OK_K2_E5_SHIFT                                          0
+#define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER837_K2_E5                                                   0x003160UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER838_K2_E5                                                   0x003164UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_TOP_ERR_CTRL1_K2_E5                                                             0x003200UL //Access:RW   DataWidth:0x8    // lower 8-bits of 16-bit CMU error code.  0x0 - indicates that there is no error rest - reserved
+#define PHY_NW_IP_REG_CMU_R0_TOP_ERR_CTRL2_K2_E5                                                             0x003204UL //Access:RW   DataWidth:0x8    // higher 8-bits of 16-bit CMU error code.  0x0 - indicates that there is no error rest - reserved
+#define PHY_NW_IP_REG_CMU_R0_TOP_ERR_CTRL3_K2_E5                                                             0x003208UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_TOP_ERR_CTRL3_CMU_ERR_K2_E5                                                   (0x1<<0) // CMU macro error status. 0x0 - no error 0x1 - PHY CMU macro has an internal error detected by firmware. CMU error code can be used to isolate error event.
+  #define PHY_NW_IP_REG_CMU_R0_TOP_ERR_CTRL3_CMU_ERR_K2_E5_SHIFT                                             0
+#define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER839_K2_E5                                                   0x003228UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER839_RESERVEDFIELD396_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER839_RESERVEDFIELD396_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER839_RESERVEDFIELD397_K2_E5                                (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER839_RESERVEDFIELD397_K2_E5_SHIFT                          1
+#define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER840_K2_E5                                                   0x00322cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER840_RESERVEDFIELD398_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER840_RESERVEDFIELD398_K2_E5_SHIFT                          0
+#define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER841_K2_E5                                                   0x003230UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER841_RESERVEDFIELD399_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER841_RESERVEDFIELD399_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER841_RESERVEDFIELD400_K2_E5                                (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER841_RESERVEDFIELD400_K2_E5_SHIFT                          1
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER841_RESERVEDFIELD401_K2_E5                                (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER841_RESERVEDFIELD401_K2_E5_SHIFT                          3
+#define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PD_CTRL0_K2_E5                                                         0x003400UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PD_CTRL0_PD_CMPLL2_K2_E5                                             (0x1<<0) // Powerdown for RPLL.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PD_CTRL0_PD_CMPLL2_K2_E5_SHIFT                                       0
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PD_CTRL0_RESERVEDFIELD402_K2_E5                                      (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PD_CTRL0_RESERVEDFIELD402_K2_E5_SHIFT                                1
+#define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_RST_CTRL0_K2_E5                                                        0x003404UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_RST_CTRL0_RST_CMPLL2_FRACN_N_K2_E5                                   (0x1<<0) // Resets the DivN counter in the FracN
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_RST_CTRL0_RST_CMPLL2_FRACN_N_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_RST_CTRL0_RST_CMPLL2_DIV4P125_N_K2_E5                                (0x1<<1) // TBD
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_RST_CTRL0_RST_CMPLL2_DIV4P125_N_K2_E5_SHIFT                          1
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER842_K2_E5                                                  0x003408UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER842_RESERVEDFIELD403_K2_E5                               (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER842_RESERVEDFIELD403_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER842_RESERVEDFIELD404_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER842_RESERVEDFIELD404_K2_E5_SHIFT                         2
+#define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_CLK_CTRL0_K2_E5                                                        0x00340cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_CLK_CTRL0_CMPLL2_REFCLK_SEL_K2_E5                                    (0x1<<0) // Select the reference clock. 0 - clk_ref 1- clk_pllref
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_CLK_CTRL0_CMPLL2_REFCLK_SEL_K2_E5_SHIFT                              0
+#define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_VCO_CTRL0_K2_E5                                                        0x003410UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_VCO_CTRL0_CMPLL2_VCO_KICK_K2_E5                                      (0x1<<0) // TBD
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_VCO_CTRL0_CMPLL2_VCO_KICK_K2_E5_SHIFT                                0
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_VCO_CTRL0_CMPLL2_BIAS_TRIM_K2_E5                                     (0x1f<<1) // TBD
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_VCO_CTRL0_CMPLL2_BIAS_TRIM_K2_E5_SHIFT                               1
+#define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_CLKDIV_CTRL0_K2_E5                                                     0x003418UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_CLKDIV_CTRL0_CMPLL2_FBKCLK_DIV_K2_E5                                 (0x3<<0) // TBD
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_CLKDIV_CTRL0_CMPLL2_FBKCLK_DIV_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER843_K2_E5                                                  0x003420UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER843_RESERVEDFIELD405_K2_E5                               (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER843_RESERVEDFIELD405_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL0_K2_E5                                                        0x003424UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL0_CMPLL2_PFD_PW_K2_E5                                        (0x3<<0) // TBD
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL0_CMPLL2_PFD_PW_K2_E5_SHIFT                                  0
+#define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL1_K2_E5                                                        0x003428UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL1_CMPLL2_MUTE_K2_E5                                          (0x1<<0) // TBD
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL1_CMPLL2_MUTE_K2_E5_SHIFT                                    0
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL1_CMPLL2_PFD_FORCE_UP_K2_E5                                  (0x1<<1) // TBD
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL1_CMPLL2_PFD_FORCE_UP_K2_E5_SHIFT                            1
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL1_CMPLL2_PFD_FORCE_DN_K2_E5                                  (0x1<<2) // TBD
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL1_CMPLL2_PFD_FORCE_DN_K2_E5_SHIFT                            2
+#define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PROP_CTRL0_K2_E5                                                       0x00342cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PROP_CTRL0_CMPLL2_PFILT_K2_E5                                        (0x7<<0) // TBD
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PROP_CTRL0_CMPLL2_PFILT_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PROP_CTRL0_CMPLL2_PCP_TRIM_K2_E5                                     (0x3<<4) // TBD
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PROP_CTRL0_CMPLL2_PCP_TRIM_K2_E5_SHIFT                               4
+#define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PROP_CTRL1_K2_E5                                                       0x003430UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PROP_CTRL1_CMPLL2_PKVCO_K2_E5                                        (0x1f<<0) // TBD
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PROP_CTRL1_CMPLL2_PKVCO_K2_E5_SHIFT                                  0
+#define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL0_K2_E5                                                        0x003434UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL0_CMPLL2_IDROPI_K2_E5                                        (0x1<<0) // TBD
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL0_CMPLL2_IDROPI_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL0_CMPLL2_IHIZ_K2_E5                                          (0x1<<1) // TBD
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL0_CMPLL2_IHIZ_K2_E5_SHIFT                                    1
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL0_CMPLL2_IFILT_K2_E5                                         (0xf<<2) // TBD
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL0_CMPLL2_IFILT_K2_E5_SHIFT                                   2
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL0_CMPLL2_IKVCO_K2_E5                                         (0x3<<6) // TBD
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL0_CMPLL2_IKVCO_K2_E5_SHIFT                                   6
+#define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL1_K2_E5                                                        0x00343cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL1_CMPLL2_IZERO_K2_E5                                         (0x1<<0) // TBD
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL1_CMPLL2_IZERO_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL1_CMPLL2_IFORCE_K2_E5                                        (0x3<<1) // TBD
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL1_CMPLL2_IFORCE_K2_E5_SHIFT                                  1
+#define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL2_K2_E5                                                        0x003440UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL2_CMPLL2_V2I_CAP_K2_E5                                       (0x7<<0) // TBD
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL2_CMPLL2_V2I_CAP_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL2_CMPLL2_V2I_LPF_K2_E5                                       (0x1<<3) // TBD
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL2_CMPLL2_V2I_LPF_K2_E5_SHIFT                                 3
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL2_CMPLL2_V2I_GAIN_K2_E5                                      (0x3<<4) // TBD
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL2_CMPLL2_V2I_GAIN_K2_E5_SHIFT                                4
+#define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL3_K2_E5                                                        0x003444UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL3_CMPLL2_CPCHOP_EN_K2_E5                                     (0x1<<0) // TBD
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL3_CMPLL2_CPCHOP_EN_K2_E5_SHIFT                               0
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL3_CMPLL2_CPCHOP_DIV_K2_E5                                    (0x7<<1) // TBD
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL3_CMPLL2_CPCHOP_DIV_K2_E5_SHIFT                              1
+#define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_FRACN_CTRL0_K2_E5                                                      0x003448UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_FRACN_CTRL0_CMPLL2_FRACDIV_EN_K2_E5                                  (0x1<<0) // Selects between FracN and integer divide modes 0  integer mode 1  FracN/SSC mode
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_FRACN_CTRL0_CMPLL2_FRACDIV_EN_K2_E5_SHIFT                            0
+#define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_MISC_CTRL0_K2_E5                                                       0x003458UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_MISC_CTRL0_CMPLL2_BIAS_LPF_K2_E5                                     (0x1<<0) // TBD
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_MISC_CTRL0_CMPLL2_BIAS_LPF_K2_E5_SHIFT                               0
+#define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_MISC_CTRL1_K2_E5                                                       0x00345cUL //Access:RW   DataWidth:0x8    // TBD
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER844_K2_E5                                                  0x003480UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER845_K2_E5                                                  0x003484UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER846_K2_E5                                                  0x003488UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER847_K2_E5                                                  0x00348cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER847_F705_K2_E5                                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER847_F705_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER848_K2_E5                                                  0x003490UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER849_K2_E5                                                  0x003494UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER849_RESERVEDFIELD406_K2_E5                               (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER849_RESERVEDFIELD406_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER849_RESERVEDFIELD407_K2_E5                               (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER849_RESERVEDFIELD407_K2_E5_SHIFT                         4
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER850_K2_E5                                                  0x003498UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER851_K2_E5                                                  0x00349cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER851_F708_K2_E5                                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER851_F708_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER852_K2_E5                                                  0x0034a0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER853_K2_E5                                                  0x0034a4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER853_F710_K2_E5                                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER853_F710_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER854_K2_E5                                                  0x0034a8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER855_K2_E5                                                  0x0034acUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER855_F712_K2_E5                                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER855_F712_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER856_K2_E5                                                  0x0034b0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER857_K2_E5                                                  0x0034b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER857_F714_K2_E5                                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER857_F714_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER858_K2_E5                                                  0x0034b8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER859_K2_E5                                                  0x0034bcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER859_F716_K2_E5                                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER859_F716_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER860_K2_E5                                                  0x0034c0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER861_K2_E5                                                  0x0034c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER861_F718_K2_E5                                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER861_F718_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER862_K2_E5                                                  0x0034c8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER863_K2_E5                                                  0x0034d0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER864_K2_E5                                                  0x0034d4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER864_F721_K2_E5                                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER864_F721_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER865_K2_E5                                                  0x0034d8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER866_K2_E5                                                  0x0034dcUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER866_F723_K2_E5                                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER866_F723_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER867_K2_E5                                                  0x0034e0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER868_K2_E5                                                  0x0034e4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER868_F725_K2_E5                                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER868_F725_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER869_K2_E5                                                  0x0034e8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER869_RESERVEDFIELD408_K2_E5                               (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER869_RESERVEDFIELD408_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER869_RESERVEDFIELD409_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER869_RESERVEDFIELD409_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER869_RESERVEDFIELD410_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER869_RESERVEDFIELD410_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER870_K2_E5                                                  0x003510UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER871_K2_E5                                                  0x003514UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER871_RESERVEDFIELD412_K2_E5                               (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER871_RESERVEDFIELD412_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER871_RESERVEDFIELD413_K2_E5                               (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER871_RESERVEDFIELD413_K2_E5_SHIFT                         6
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER871_RESERVEDFIELD414_K2_E5                               (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER871_RESERVEDFIELD414_K2_E5_SHIFT                         7
+#define PHY_NW_IP_REG_CMU_R0_RPLL_LOCKDET_STATUS_K2_E5                                                       0x003518UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_LOCKDET_STATUS_LOCKED_K2_E5                                              (0x1<<0) // For lock detection
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_LOCKDET_STATUS_LOCKED_K2_E5_SHIFT                                        0
+#define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL0_K2_E5                                                        0x003524UL //Access:RW   DataWidth:0x8    // Sets maximum spreading frequency in SSC mode.
+#define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL1_K2_E5                                                        0x003528UL //Access:RW   DataWidth:0x8    // Sets maximum spreading frequency in SSC mode.
+#define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL2_K2_E5                                                        0x00352cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL2_MATCH_VAL_19_16_K2_E5                                      (0xf<<0) // Sets maximum spreading frequency in SSC mode.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL2_MATCH_VAL_19_16_K2_E5_SHIFT                                0
+#define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL3_K2_E5                                                        0x003530UL //Access:RW   DataWidth:0x8    // Increment value in SSC mode;Enabled when ssc_gen_en=1.Note: this is an unsigned number
+#define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL4_K2_E5                                                        0x003534UL //Access:RW   DataWidth:0x8    // Increment value in SSC mode;Enabled when ssc_gen_en=1.Note: this is an unsigned number
+#define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL5_K2_E5                                                        0x003538UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL5_UPDOWN_EN_K2_E5                                            (0x1<<0) // Enable for both Upspreading and Downspreading in SSC mode
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL5_UPDOWN_EN_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL5_FRACSYN_EN_K2_E5                                           (0x1<<1) // Enable for loading freq_offset sr as the offset to establish nominal frequency Freq_offset to implement SSC on
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL5_FRACSYN_EN_K2_E5_SHIFT                                     1
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL5_SSC_EN_K2_E5                                               (0x1<<2) // Enables SSC generation
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL5_SSC_EN_K2_E5_SHIFT                                         2
+#define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL0_K2_E5                                                          0x00353cUL //Access:RW   DataWidth:0x8    // Used as frequency offset in SSC when ssc_gen_en=1 or  when fracsyn_en=1
+#define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL1_K2_E5                                                          0x003540UL //Access:RW   DataWidth:0x8    // Used as frequency offset in SSC when ssc_gen_en=1 or  when fracsyn_en=1
+#define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL2_K2_E5                                                          0x003544UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL2_FDIV_19_16_K2_E5                                             (0xf<<0) // Used as frequency offset in SSC when ssc_gen_en=1 or  when fracsyn_en=1
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL2_FDIV_19_16_K2_E5_SHIFT                                       0
+#define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL3_K2_E5                                                          0x003550UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL3_FMODE_EN_K2_E5                                               (0x1<<0) // enable the fracN div mode of the fracn_mod digital control block
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL3_FMODE_EN_K2_E5_SHIFT                                         0
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL3_RESERVEDFIELD415_K2_E5                                       (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL3_RESERVEDFIELD415_K2_E5_SHIFT                                 1
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL3_RESERVEDFIELD416_K2_E5                                       (0xf<<3) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL3_RESERVEDFIELD416_K2_E5_SHIFT                                 3
+#define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL4_K2_E5                                                          0x003554UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL4_NDIV_K2_E5                                                   (0x7f<<0) // ndiv
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL4_NDIV_K2_E5_SHIFT                                             0
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL4_RESERVEDFIELD417_K2_E5                                       (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL4_RESERVEDFIELD417_K2_E5_SHIFT                                 7
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER872_K2_E5                                                  0x003560UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER873_K2_E5                                                  0x003564UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER874_K2_E5                                                0x003800UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER874_RESERVEDFIELD418_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER874_RESERVEDFIELD418_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER875_K2_E5                                                0x003804UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER875_RESERVEDFIELD419_K2_E5                             (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER875_RESERVEDFIELD419_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER876_K2_E5                                                0x003808UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER877_K2_E5                                                0x00380cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER877_RESERVEDFIELD421_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER877_RESERVEDFIELD421_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER877_RESERVEDFIELD422_K2_E5                             (0xf<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER877_RESERVEDFIELD422_K2_E5_SHIFT                       1
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER878_K2_E5                                                0x003840UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER879_K2_E5                                                0x003844UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER879_RESERVEDFIELD424_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER879_RESERVEDFIELD424_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER880_K2_E5                                                0x003848UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER881_K2_E5                                                0x00384cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER881_RESERVEDFIELD426_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER881_RESERVEDFIELD426_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER882_K2_E5                                                0x003880UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER882_RESERVEDFIELD427_K2_E5                             (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER882_RESERVEDFIELD427_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER882_RESERVEDFIELD428_K2_E5                             (0xf<<2) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER882_RESERVEDFIELD428_K2_E5_SHIFT                       2
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER883_K2_E5                                                0x003884UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER884_K2_E5                                                0x003888UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER884_RESERVEDFIELD430_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER884_RESERVEDFIELD430_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER885_K2_E5                                                0x00388cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER886_K2_E5                                                0x003890UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER886_RESERVEDFIELD432_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER886_RESERVEDFIELD432_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER887_K2_E5                                                0x003894UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER888_K2_E5                                                0x003898UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER888_RESERVEDFIELD434_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER888_RESERVEDFIELD434_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER889_K2_E5                                                0x0038c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER889_RESERVEDFIELD435_K2_E5                             (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER889_RESERVEDFIELD435_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER890_K2_E5                                                0x0038c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER890_RESERVEDFIELD436_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER890_RESERVEDFIELD436_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER890_RESERVEDFIELD437_K2_E5                             (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER890_RESERVEDFIELD437_K2_E5_SHIFT                       4
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER891_K2_E5                                                0x0038c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER891_RESERVEDFIELD438_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER891_RESERVEDFIELD438_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER892_K2_E5                                                0x003900UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER892_RESERVEDFIELD439_K2_E5                             (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER892_RESERVEDFIELD439_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER893_K2_E5                                                0x003904UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER894_K2_E5                                                0x003908UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER895_K2_E5                                                0x00390cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER896_K2_E5                                                0x003910UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER897_K2_E5                                                0x003914UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER898_K2_E5                                                0x003918UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER899_K2_E5                                                0x00391cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER900_K2_E5                                                0x003920UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER900_RESERVEDFIELD447_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER900_RESERVEDFIELD447_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER901_K2_E5                                                0x003940UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER901_RESERVEDFIELD448_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER901_RESERVEDFIELD448_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER901_RESERVEDFIELD449_K2_E5                             (0xf<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER901_RESERVEDFIELD449_K2_E5_SHIFT                       1
+#define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER902_K2_E5                                                0x003944UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER903_K2_E5                                               0x003c00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER903_RESERVEDFIELD451_K2_E5                            (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER903_RESERVEDFIELD451_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER904_K2_E5                                               0x003c10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER904_RESERVEDFIELD452_K2_E5                            (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER904_RESERVEDFIELD452_K2_E5_SHIFT                      0
+  #define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER904_RESERVEDFIELD453_K2_E5                            (0x7f<<1) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER904_RESERVEDFIELD453_K2_E5_SHIFT                      1
+#define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER905_K2_E5                                               0x003c14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER905_RESERVEDFIELD454_K2_E5                            (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER905_RESERVEDFIELD454_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER906_K2_E5                                               0x003c20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER906_RESERVEDFIELD455_K2_E5                            (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER906_RESERVEDFIELD455_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER907_K2_E5                                               0x003c40UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER908_K2_E5                                               0x003c44UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER909_K2_E5                                               0x003c48UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER910_K2_E5                                               0x003c4cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER911_K2_E5                                               0x003c50UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER912_K2_E5                                               0x003c54UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER913_K2_E5                                               0x003c58UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER914_K2_E5                                               0x003c5cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_K2_E5                                                        0x006000UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_K2_E5                                    (0x1<<0) // RX clock loopback mode enable.   0x0 - mission mode 0x1 - select recovered clock from CDR as source of half-rate TX clock path.
+  #define PHY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_K2_E5                                    (0x1<<1) // TX clock loopback mode enable.  0x0 - mission mode 0x1 - MUX half-rate TX clock into LEQ gain stage.
+  #define PHY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_K2_E5                                      (0x1<<2) // Far-End Analog FEA loopback mode enable.  0x0 - mission mode 0x1 - loop back parallel data from RX data path to TX data path internal to AFE
+  #define PHY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_K2_E5_SHIFT                                2
+  #define PHY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_K2_E5                                      (0x1<<3) // Near-End Analog NEA loopback mode enable.  0x0 - mission mode 0x1 - loop back quarter rate data from TX data path to RX data path internal to AFE.
+  #define PHY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_K2_E5_SHIFT                                3
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER915_K2_E5                                                      0x006004UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER915_RESERVEDFIELD456_K2_E5                                   (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER915_RESERVEDFIELD456_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER915_RESERVEDFIELD457_K2_E5                                   (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER915_RESERVEDFIELD457_K2_E5_SHIFT                             2
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER915_RESERVEDFIELD458_K2_E5                                   (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER915_RESERVEDFIELD458_K2_E5_SHIFT                             4
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER916_K2_E5                                                      0x006008UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER916_RESERVEDFIELD459_K2_E5                                   (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER916_RESERVEDFIELD459_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER916_RESERVEDFIELD460_K2_E5                                   (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER916_RESERVEDFIELD460_K2_E5_SHIFT                             2
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER916_RESERVEDFIELD461_K2_E5                                   (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER916_RESERVEDFIELD461_K2_E5_SHIFT                             4
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER917_K2_E5                                                      0x00600cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER917_RESERVEDFIELD462_K2_E5                                   (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER917_RESERVEDFIELD462_K2_E5_SHIFT                             0
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER918_K2_E5                                                      0x006010UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER918_RESERVEDFIELD463_K2_E5                                   (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER918_RESERVEDFIELD463_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER918_RESERVEDFIELD464_K2_E5                                   (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER918_RESERVEDFIELD464_K2_E5_SHIFT                             1
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER919_K2_E5                                                      0x006014UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER919_RESERVEDFIELD465_K2_E5                                   (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER919_RESERVEDFIELD465_K2_E5_SHIFT                             2
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER920_K2_E5                                                      0x006018UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER920_RESERVEDFIELD466_K2_E5                                   (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER920_RESERVEDFIELD466_K2_E5_SHIFT                             0
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER921_K2_E5                                                      0x006040UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER921_RESERVEDFIELD467_K2_E5                                   (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER921_RESERVEDFIELD467_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER921_RESERVEDFIELD468_K2_E5                                   (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER921_RESERVEDFIELD468_K2_E5_SHIFT                             4
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER921_RESERVEDFIELD469_K2_E5                                   (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER921_RESERVEDFIELD469_K2_E5_SHIFT                             6
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER922_K2_E5                                                      0x006048UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER922_RESERVEDFIELD470_K2_E5                                   (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER922_RESERVEDFIELD470_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER922_RESERVEDFIELD471_K2_E5                                   (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER922_RESERVEDFIELD471_K2_E5_SHIFT                             2
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER923_K2_E5                                                      0x00604cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER923_RESERVEDFIELD472_K2_E5                                   (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER923_RESERVEDFIELD472_K2_E5_SHIFT                             0
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER924_K2_E5                                                      0x006050UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER924_RESERVEDFIELD473_K2_E5                                   (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER924_RESERVEDFIELD473_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER924_RESERVEDFIELD474_K2_E5                                   (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER924_RESERVEDFIELD474_K2_E5_SHIFT                             2
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER925_K2_E5                                                      0x006058UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER925_RESERVEDFIELD475_K2_E5                                   (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER925_RESERVEDFIELD475_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER925_RESERVEDFIELD476_K2_E5                                   (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER925_RESERVEDFIELD476_K2_E5_SHIFT                             4
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER926_K2_E5                                                      0x006064UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER926_RESERVEDFIELD477_K2_E5                                   (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER926_RESERVEDFIELD477_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER926_RESERVEDFIELD478_K2_E5                                   (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER926_RESERVEDFIELD478_K2_E5_SHIFT                             4
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER927_K2_E5                                                      0x00606cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER927_RESERVEDFIELD479_K2_E5                                   (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER927_RESERVEDFIELD479_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER927_RESERVEDFIELD480_K2_E5                                   (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER927_RESERVEDFIELD480_K2_E5_SHIFT                             3
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER927_RESERVEDFIELD481_K2_E5                                   (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER927_RESERVEDFIELD481_K2_E5_SHIFT                             4
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER928_K2_E5                                                      0x006070UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER928_RESERVEDFIELD482_K2_E5                                   (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER928_RESERVEDFIELD482_K2_E5_SHIFT                             0
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER929_K2_E5                                                      0x006078UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER929_RESERVEDFIELD483_K2_E5                                   (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER929_RESERVEDFIELD483_K2_E5_SHIFT                             0
+#define PHY_NW_IP_REG_LN0_TOP_DPL_TXDP_CTRL1_K2_E5                                                           0x006088UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_EN_K2_E5                                     (0x1<<0) // Enables register control of TX data path mux in DPL
+  #define PHY_NW_IP_REG_LN0_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_EN_K2_E5_SHIFT                               0
+  #define PHY_NW_IP_REG_LN0_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_VAL_K2_E5                                    (0x7<<1) // Select value for TX data path mux in DPL.  The corresponding mux select override enable must also be set. 0 : TX data from customer logics 1: RX data for Far-End-Digital FED loopback 2: BIST generator 3: AN/802.3 4: LT/802.3 5-7: reserved
+  #define PHY_NW_IP_REG_LN0_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_VAL_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_LN0_TOP_DPL_TXDP_CTRL1_TXPOLARITY_K2_E5                                              (0x1<<4) // TX data polarity control
+  #define PHY_NW_IP_REG_LN0_TOP_DPL_TXDP_CTRL1_TXPOLARITY_K2_E5_SHIFT                                        4
+  #define PHY_NW_IP_REG_LN0_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_K2_E5                                   (0x1<<5) // Controls tx_en for Far-End-Digital FED loopback mode.  In FED loopback mode, tx_en will be set when this field is set to 1 and rxvalid is 1.
+  #define PHY_NW_IP_REG_LN0_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_K2_E5_SHIFT                             5
+#define PHY_NW_IP_REG_LN0_TOP_DPL_RXDP_CTRL1_K2_E5                                                           0x006090UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_K2_E5                                             (0x1<<0) // A mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
+  #define PHY_NW_IP_REG_LN0_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_K2_E5_SHIFT                                       0
+  #define PHY_NW_IP_REG_LN0_TOP_DPL_RXDP_CTRL1_BIT_STRIP_EVEN_K2_E5                                          (0x1<<1) // A bit stripping selection for RX data path in the DPL 1: Even bits stripped from RX data 0: Odd bits stripped from Rx data
+  #define PHY_NW_IP_REG_LN0_TOP_DPL_RXDP_CTRL1_BIT_STRIP_EVEN_K2_E5_SHIFT                                    1
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER930_K2_E5                                                      0x006094UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER930_RESERVEDFIELD484_K2_E5                                   (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER930_RESERVEDFIELD484_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER930_RESERVEDFIELD485_K2_E5                                   (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER930_RESERVEDFIELD485_K2_E5_SHIFT                             3
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER931_K2_E5                                                      0x006098UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER931_RESERVEDFIELD486_K2_E5                                   (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER931_RESERVEDFIELD486_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER931_RESERVEDFIELD487_K2_E5                                   (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER931_RESERVEDFIELD487_K2_E5_SHIFT                             3
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER931_RESERVEDFIELD488_K2_E5                                   (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER931_RESERVEDFIELD488_K2_E5_SHIFT                             4
+#define PHY_NW_IP_REG_LN0_TOP_PHY_IF_STATUS_K2_E5                                                            0x00609cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_PHY_IF_STATUS_LN_OK_K2_E5                                                    (0x1<<0) // LANE OK status
+  #define PHY_NW_IP_REG_LN0_TOP_PHY_IF_STATUS_LN_OK_K2_E5_SHIFT                                              0
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER932_K2_E5                                                      0x0060c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER932_RESERVEDFIELD489_K2_E5                                   (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER932_RESERVEDFIELD489_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER932_RESERVEDFIELD490_K2_E5                                   (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER932_RESERVEDFIELD490_K2_E5_SHIFT                             3
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER933_K2_E5                                                      0x0060c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER933_RESERVEDFIELD491_K2_E5                                   (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER933_RESERVEDFIELD491_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER933_RESERVEDFIELD492_K2_E5                                   (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER933_RESERVEDFIELD492_K2_E5_SHIFT                             3
+#define PHY_NW_IP_REG_LN0_TOP_LN_STAT_CTRL0_K2_E5                                                            0x0060e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_LN_STAT_CTRL0_RXVALID_K2_E5                                                  (0x1<<0) // rxvalid status output
+  #define PHY_NW_IP_REG_LN0_TOP_LN_STAT_CTRL0_RXVALID_K2_E5_SHIFT                                            0
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER934_K2_E5                                                      0x0060e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER934_RESERVEDFIELD493_K2_E5                                   (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER934_RESERVEDFIELD493_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER934_RESERVEDFIELD494_K2_E5                                   (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER934_RESERVEDFIELD494_K2_E5_SHIFT                             1
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER935_K2_E5                                                      0x0060e8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER935_RESERVEDFIELD495_K2_E5                                   (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER935_RESERVEDFIELD495_K2_E5_SHIFT                             0
+#define PHY_NW_IP_REG_LN0_TOP_LN_CTRL_OVR0_K2_E5                                                             0x0060ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_LN_CTRL_OVR0_OVR_EN_K2_E5                                                    (0x1<<0) // override enable for lnX_ctrl_*_i signals in this register
+  #define PHY_NW_IP_REG_LN0_TOP_LN_CTRL_OVR0_OVR_EN_K2_E5_SHIFT                                              0
+  #define PHY_NW_IP_REG_LN0_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_K2_E5                                             (0x7<<1) // lnX_data_width_i override value for TX.  It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-quarter width 10b, others, reserved.
+  #define PHY_NW_IP_REG_LN0_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_K2_E5_SHIFT                                       1
+  #define PHY_NW_IP_REG_LN0_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_K2_E5                                             (0x7<<4) // lnX_data_width_i override value for RX.  It takes effect when ovr_en is 1.
+  #define PHY_NW_IP_REG_LN0_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_K2_E5_SHIFT                                       4
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER936_K2_E5                                                      0x0060f0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER936_RESERVEDFIELD496_K2_E5                                   (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER936_RESERVEDFIELD496_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER936_RESERVEDFIELD497_K2_E5                                   (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER936_RESERVEDFIELD497_K2_E5_SHIFT                             3
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER936_RESERVEDFIELD498_K2_E5                                   (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER936_RESERVEDFIELD498_K2_E5_SHIFT                             4
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER936_RESERVEDFIELD499_K2_E5                                   (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER936_RESERVEDFIELD499_K2_E5_SHIFT                             5
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER937_K2_E5                                                      0x0060f4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER937_RESERVEDFIELD500_K2_E5                                   (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER937_RESERVEDFIELD500_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER937_RESERVEDFIELD501_K2_E5                                   (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER937_RESERVEDFIELD501_K2_E5_SHIFT                             4
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER938_K2_E5                                                      0x0060f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER938_RESERVEDFIELD502_K2_E5                                   (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER938_RESERVEDFIELD502_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER938_RESERVEDFIELD503_K2_E5                                   (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER938_RESERVEDFIELD503_K2_E5_SHIFT                             5
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER938_RESERVEDFIELD504_K2_E5                                   (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER938_RESERVEDFIELD504_K2_E5_SHIFT                             6
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER939_K2_E5                                                      0x0060fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER939_RESERVEDFIELD505_K2_E5                                   (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER939_RESERVEDFIELD505_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER939_RESERVEDFIELD506_K2_E5                                   (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER939_RESERVEDFIELD506_K2_E5_SHIFT                             1
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER939_RESERVEDFIELD507_K2_E5                                   (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER939_RESERVEDFIELD507_K2_E5_SHIFT                             3
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER940_K2_E5                                                      0x006100UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER940_RESERVEDFIELD508_K2_E5                                   (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER940_RESERVEDFIELD508_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER940_RESERVEDFIELD509_K2_E5                                   (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER940_RESERVEDFIELD509_K2_E5_SHIFT                             1
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER940_RESERVEDFIELD510_K2_E5                                   (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER940_RESERVEDFIELD510_K2_E5_SHIFT                             2
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER941_K2_E5                                                      0x006108UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER941_RESERVEDFIELD511_K2_E5                                   (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER941_RESERVEDFIELD511_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER941_RESERVEDFIELD512_K2_E5                                   (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER941_RESERVEDFIELD512_K2_E5_SHIFT                             1
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER942_K2_E5                                                      0x00610cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER942_RESERVEDFIELD513_K2_E5                                   (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER942_RESERVEDFIELD513_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER942_RESERVEDFIELD514_K2_E5                                   (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER942_RESERVEDFIELD514_K2_E5_SHIFT                             1
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER943_K2_E5                                                      0x006120UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER943_RESERVEDFIELD515_K2_E5                                   (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER943_RESERVEDFIELD515_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER943_RESERVEDFIELD516_K2_E5                                   (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER943_RESERVEDFIELD516_K2_E5_SHIFT                             3
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER943_RESERVEDFIELD517_K2_E5                                   (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER943_RESERVEDFIELD517_K2_E5_SHIFT                             6
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER943_RESERVEDFIELD518_K2_E5                                   (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER943_RESERVEDFIELD518_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER944_K2_E5                                                      0x006124UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER944_RESERVEDFIELD519_K2_E5                                   (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER944_RESERVEDFIELD519_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER944_RESERVEDFIELD520_K2_E5                                   (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER944_RESERVEDFIELD520_K2_E5_SHIFT                             1
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER944_RESERVEDFIELD521_K2_E5                                   (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER944_RESERVEDFIELD521_K2_E5_SHIFT                             2
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER944_RESERVEDFIELD522_K2_E5                                   (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER944_RESERVEDFIELD522_K2_E5_SHIFT                             4
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER944_RESERVEDFIELD523_K2_E5                                   (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER944_RESERVEDFIELD523_K2_E5_SHIFT                             5
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER944_RESERVEDFIELD524_K2_E5                                   (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER944_RESERVEDFIELD524_K2_E5_SHIFT                             6
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER945_K2_E5                                                      0x006128UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER945_RESERVEDFIELD525_K2_E5                                   (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER945_RESERVEDFIELD525_K2_E5_SHIFT                             0
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER946_K2_E5                                                      0x00612cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER946_RESERVEDFIELD526_K2_E5                                   (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER946_RESERVEDFIELD526_K2_E5_SHIFT                             0
+#define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER947_K2_E5                                                      0x006130UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER947_RESERVEDFIELD527_K2_E5                                   (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER947_RESERVEDFIELD527_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER947_RESERVEDFIELD528_K2_E5                                   (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER947_RESERVEDFIELD528_K2_E5_SHIFT                             1
+#define PHY_NW_IP_REG_LN0_TOP_ERR_CTRL1_K2_E5                                                                0x006140UL //Access:RW   DataWidth:0x8    // lower 8-bits of 16-bit lane error code.  0x0 - indicates that there is no error rest - reserved
+#define PHY_NW_IP_REG_LN0_TOP_ERR_CTRL2_K2_E5                                                                0x006144UL //Access:RW   DataWidth:0x8    // higher 8-bits of 16-bit lane error code.  0x0 - indicates that there is no error rest - reserved
+#define PHY_NW_IP_REG_LN0_TOP_ERR_CTRL3_K2_E5                                                                0x006148UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_TOP_ERR_CTRL3_LANE_ERR_K2_E5                                                     (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macro has an internal error detected by firmware. Lane error code can be used to isolate error event.
+  #define PHY_NW_IP_REG_LN0_TOP_ERR_CTRL3_LANE_ERR_K2_E5_SHIFT                                               0
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER948_K2_E5                                                0x006240UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER948_RESERVEDFIELD529_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER948_RESERVEDFIELD529_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER949_K2_E5                                                0x006244UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER949_RESERVEDFIELD530_K2_E5                             (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER949_RESERVEDFIELD530_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER950_K2_E5                                                0x006284UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER950_RESERVEDFIELD531_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER950_RESERVEDFIELD531_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER950_RESERVEDFIELD532_K2_E5                             (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER950_RESERVEDFIELD532_K2_E5_SHIFT                       4
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER951_K2_E5                                                0x006288UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER951_RESERVEDFIELD533_K2_E5                             (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER951_RESERVEDFIELD533_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER952_K2_E5                                                0x006298UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER953_K2_E5                                                0x00629cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER953_RESERVEDFIELD535_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER953_RESERVEDFIELD535_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER954_K2_E5                                                0x0062a0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER955_K2_E5                                                0x0062a4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER955_RESERVEDFIELD537_K2_E5                             (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER955_RESERVEDFIELD537_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER956_K2_E5                                                0x0062a8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER957_K2_E5                                                0x0062acUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER957_RESERVEDFIELD539_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER957_RESERVEDFIELD539_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER958_K2_E5                                                0x0062b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER958_RESERVEDFIELD540_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER958_RESERVEDFIELD540_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER959_K2_E5                                                0x0062c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER959_RESERVEDFIELD541_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER959_RESERVEDFIELD541_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER960_K2_E5                                                0x0062c4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER961_K2_E5                                                0x0062c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER961_RESERVEDFIELD543_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER961_RESERVEDFIELD543_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER962_K2_E5                                                0x0062d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER962_RESERVEDFIELD544_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER962_RESERVEDFIELD544_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER963_K2_E5                                                0x0062d8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER964_K2_E5                                                0x0062dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER964_RESERVEDFIELD546_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER964_RESERVEDFIELD546_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER965_K2_E5                                                0x0062e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER965_RESERVEDFIELD547_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER965_RESERVEDFIELD547_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER966_K2_E5                                                0x0062e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER966_RESERVEDFIELD548_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER966_RESERVEDFIELD548_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER966_RESERVEDFIELD549_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER966_RESERVEDFIELD549_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER966_RESERVEDFIELD550_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER966_RESERVEDFIELD550_K2_E5_SHIFT                       2
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER966_RESERVEDFIELD551_K2_E5                             (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER966_RESERVEDFIELD551_K2_E5_SHIFT                       3
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER967_K2_E5                                                0x0062ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER967_RESERVEDFIELD552_K2_E5                             (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER967_RESERVEDFIELD552_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER968_K2_E5                                                0x0062f0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER968_RESERVEDFIELD553_K2_E5                             (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER968_RESERVEDFIELD553_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER969_K2_E5                                                0x0062f4UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER970_K2_E5                                                0x0062f8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER970_RESERVEDFIELD555_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER970_RESERVEDFIELD555_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS2_K2_E5                                                       0x0062fcUL //Access:R    DataWidth:0x8    // Binary-coded DLPF control input to the CDR
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS3_K2_E5                                                       0x006300UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8_K2_E5                                        (0x1<<0) // Binary-coded DLPF control input to the CDR
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8_K2_E5_SHIFT                                  0
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS4_K2_E5                                                       0x006304UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH_K2_E5                                       (0x1<<0) // Indicates that DLPF control input to CDR is too high
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW_K2_E5                                        (0x1<<1) // Indicates that DLPF control input to CDR is too low
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW_K2_E5_SHIFT                                  1
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST_K2_E5                                           (0x1<<2) // CDR loss of lock indicator.  1 means lock has been lost. Once lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by setting set lock_en_i to 0.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST_K2_E5_SHIFT                                     2
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS5_K2_E5                                                       0x006310UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS5_LOCKED_K2_E5                                              (0x1<<0) // CDR lock indicator.  1 means lock is achieved. It is cleared when lock detector is disabled by setting set lock_en_i to 0.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS5_LOCKED_K2_E5_SHIFT                                        0
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_INTEGRAL_STATUS0_K2_E5                                                   0x006314UL //Access:R    DataWidth:0x8    // Value of the accumulator in the CDR integral path
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_INTEGRAL_STATUS1_K2_E5                                                   0x006318UL //Access:R    DataWidth:0x8    // Value of the accumulator in the CDR integral path
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_INTEGRAL_STATUS2_K2_E5                                                   0x006320UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_INTEGRAL_STATUS2_ACCUMULATOR_19_16_K2_E5                               (0xf<<0) // Value of the accumulator in the CDR integral path
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_INTEGRAL_STATUS2_ACCUMULATOR_19_16_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER971_K2_E5                                                0x006324UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER971_RESERVEDFIELD556_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER971_RESERVEDFIELD556_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER971_RESERVEDFIELD557_K2_E5                             (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER971_RESERVEDFIELD557_K2_E5_SHIFT                       4
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER972_K2_E5                                                0x006328UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER973_K2_E5                                                0x00632cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER974_K2_E5                                                0x006330UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER975_K2_E5                                                0x006334UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER975_RESERVEDFIELD561_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER975_RESERVEDFIELD561_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER975_RESERVEDFIELD562_K2_E5                             (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER975_RESERVEDFIELD562_K2_E5_SHIFT                       4
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER976_K2_E5                                                0x006338UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER977_K2_E5                                                0x00633cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER978_K2_E5                                                0x006380UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER979_K2_E5                                                0x006384UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER979_RESERVEDFIELD566_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER979_RESERVEDFIELD566_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER980_K2_E5                                                0x006388UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER980_RESERVEDFIELD567_K2_E5                             (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER980_RESERVEDFIELD567_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER980_RESERVEDFIELD568_K2_E5                             (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER980_RESERVEDFIELD568_K2_E5_SHIFT                       4
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER981_K2_E5                                                0x00638cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER982_K2_E5                                                0x0063a0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER983_K2_E5                                                0x0063a4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER983_RESERVEDFIELD571_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER983_RESERVEDFIELD571_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER983_RESERVEDFIELD572_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER983_RESERVEDFIELD572_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER983_RESERVEDFIELD573_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER983_RESERVEDFIELD573_K2_E5_SHIFT                       2
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER984_K2_E5                                                0x0063a8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER985_K2_E5                                                0x0063acUL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER986_K2_E5                                                0x0063b0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER986_RESERVEDFIELD576_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER986_RESERVEDFIELD576_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER987_K2_E5                                                0x0063b4UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER988_K2_E5                                                0x0063b8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER989_K2_E5                                                0x0063bcUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER989_RESERVEDFIELD579_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER989_RESERVEDFIELD579_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER990_K2_E5                                                0x0063c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER990_RESERVEDFIELD580_K2_E5                             (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER990_RESERVEDFIELD580_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER991_K2_E5                                               0x006400UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER991_RESERVEDFIELD581_K2_E5                            (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER991_RESERVEDFIELD581_K2_E5_SHIFT                      0
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER991_RESERVEDFIELD582_K2_E5                            (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER991_RESERVEDFIELD582_K2_E5_SHIFT                      3
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER991_RESERVEDFIELD583_K2_E5                            (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER991_RESERVEDFIELD583_K2_E5_SHIFT                      6
+#define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER992_K2_E5                                               0x006404UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER992_RESERVEDFIELD584_K2_E5                            (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER992_RESERVEDFIELD584_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER993_K2_E5                                               0x006410UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER993_RESERVEDFIELD585_K2_E5                            (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER993_RESERVEDFIELD585_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER994_K2_E5                                               0x006418UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER995_K2_E5                                               0x006428UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER995_RESERVEDFIELD587_K2_E5                            (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER995_RESERVEDFIELD587_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER996_K2_E5                                               0x00642cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER996_RESERVEDFIELD588_K2_E5                            (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER996_RESERVEDFIELD588_K2_E5_SHIFT                      0
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER996_RESERVEDFIELD589_K2_E5                            (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER996_RESERVEDFIELD589_K2_E5_SHIFT                      1
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER996_RESERVEDFIELD590_K2_E5                            (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER996_RESERVEDFIELD590_K2_E5_SHIFT                      2
+#define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER997_K2_E5                                               0x006430UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER997_RESERVEDFIELD591_K2_E5                            (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER997_RESERVEDFIELD591_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER998_K2_E5                                               0x006440UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER998_RESERVEDFIELD592_K2_E5                            (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER998_RESERVEDFIELD592_K2_E5_SHIFT                      0
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER998_RESERVEDFIELD593_K2_E5                            (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER998_RESERVEDFIELD593_K2_E5_SHIFT                      5
+#define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER999_K2_E5                                               0x006444UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER999_RESERVEDFIELD594_K2_E5                            (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER999_RESERVEDFIELD594_K2_E5_SHIFT                      0
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER999_RESERVEDFIELD595_K2_E5                            (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER999_RESERVEDFIELD595_K2_E5_SHIFT                      2
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER999_RESERVEDFIELD596_K2_E5                            (0xf<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER999_RESERVEDFIELD596_K2_E5_SHIFT                      3
+#define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1000_K2_E5                                              0x006460UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1000_RESERVEDFIELD597_K2_E5                           (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1000_RESERVEDFIELD597_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1000_RESERVEDFIELD598_K2_E5                           (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1000_RESERVEDFIELD598_K2_E5_SHIFT                     7
+#define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1001_K2_E5                                              0x006464UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1001_RESERVEDFIELD599_K2_E5                           (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1001_RESERVEDFIELD599_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1001_RESERVEDFIELD600_K2_E5                           (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1001_RESERVEDFIELD600_K2_E5_SHIFT                     7
+#define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1002_K2_E5                                              0x006468UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1002_RESERVEDFIELD601_K2_E5                           (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1002_RESERVEDFIELD601_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1003_K2_E5                                              0x00646cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1003_RESERVEDFIELD602_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1003_RESERVEDFIELD602_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1003_RESERVEDFIELD603_K2_E5                           (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1003_RESERVEDFIELD603_K2_E5_SHIFT                     3
+#define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1004_K2_E5                                              0x006480UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1004_RESERVEDFIELD604_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1004_RESERVEDFIELD604_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1004_RESERVEDFIELD605_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1004_RESERVEDFIELD605_K2_E5_SHIFT                     1
+#define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1005_K2_E5                                              0x006484UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1005_RESERVEDFIELD606_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1005_RESERVEDFIELD606_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1006_K2_E5                                              0x006488UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1007_K2_E5                                              0x00648cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1008_K2_E5                                              0x006490UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1009_K2_E5                                              0x006494UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1009_RESERVEDFIELD610_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1009_RESERVEDFIELD610_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1010_K2_E5                                              0x0064c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1010_RESERVEDFIELD611_K2_E5                           (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1010_RESERVEDFIELD611_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1011_K2_E5                                                    0x006600UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1011_RESERVEDFIELD612_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1011_RESERVEDFIELD612_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1011_RESERVEDFIELD613_K2_E5                                 (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1011_RESERVEDFIELD613_K2_E5_SHIFT                           1
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1012_K2_E5                                                    0x006604UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1013_K2_E5                                                    0x006608UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1014_K2_E5                                                    0x00660cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1014_RESERVEDFIELD616_K2_E5                                 (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1014_RESERVEDFIELD616_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1014_RESERVEDFIELD617_K2_E5                                 (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1014_RESERVEDFIELD617_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1015_K2_E5                                                    0x006610UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1016_K2_E5                                                    0x006614UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1016_RESERVEDFIELD619_K2_E5                                 (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1016_RESERVEDFIELD619_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1017_K2_E5                                                    0x006618UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1017_RESERVEDFIELD620_K2_E5                                 (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1017_RESERVEDFIELD620_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1018_K2_E5                                                    0x00661cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1018_RESERVEDFIELD621_K2_E5                                 (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1018_RESERVEDFIELD621_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1019_K2_E5                                                    0x006620UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1020_K2_E5                                                    0x006624UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1020_RESERVEDFIELD623_K2_E5                                 (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1020_RESERVEDFIELD623_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN0_ANEG_CFG10_K2_E5                                                                   0x006628UL //Access:RW   DataWidth:0x8    // Seed provided to the transmit nonce generator polynomial
+#define PHY_NW_IP_REG_LN0_ANEG_CFG11_K2_E5                                                                   0x00662cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_CFG11_PSEUDO_SEL_K2_E5                                                      (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
+  #define PHY_NW_IP_REG_LN0_ANEG_CFG11_PSEUDO_SEL_K2_E5_SHIFT                                                0
+#define PHY_NW_IP_REG_LN0_ANEG_CTRL0_K2_E5                                                                   0x006630UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_CTRL0_AUTONEG_RESTART_K2_E5                                                 (0x1<<0) // Restarts AN that is already in progress or otherwise completed.  Reset is triggered by rising edge of this signal.  Not self clearing.
+  #define PHY_NW_IP_REG_LN0_ANEG_CTRL0_AUTONEG_RESTART_K2_E5_SHIFT                                           0
+  #define PHY_NW_IP_REG_LN0_ANEG_CTRL0_RESERVEDFIELD624_K2_E5                                                (0x7f<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_CTRL0_RESERVEDFIELD624_K2_E5_SHIFT                                          1
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1021_K2_E5                                                    0x006634UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1021_RESERVEDFIELD625_K2_E5                                 (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1021_RESERVEDFIELD625_K2_E5_SHIFT                           4
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1021_RESERVEDFIELD626_K2_E5                                 (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1021_RESERVEDFIELD626_K2_E5_SHIFT                           5
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1021_RESERVEDFIELD627_K2_E5                                 (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1021_RESERVEDFIELD627_K2_E5_SHIFT                           7
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1022_K2_E5                                                    0x006638UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1022_RESERVEDFIELD628_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1022_RESERVEDFIELD628_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN0_ANEG_STATUS0_K2_E5                                                                 0x006640UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_LP_AUTONEG_ABLE_K2_E5                                               (0x1<<0) // The link partner Auto-Negotiation ability bit shall be set to one to indicate that the link partner is able to participate in the Auto-Negotiation function. This bit shall be reset to zero if the link partner is not Auto- Negotiation able.
+  #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_LP_AUTONEG_ABLE_K2_E5_SHIFT                                         0
+  #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_LINK_STATUS_K2_E5                                                   (0x1<<2) // Local link Status.  When read as a one, it indicates that the PMA/PMD has determined that a valid link has been established i.e. link_status[HDC] equals OK. When read as a zero, it indicates that the link is not valid.
+  #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_LINK_STATUS_K2_E5_SHIFT                                             2
+  #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_AUTONEG_ABILITY_K2_E5                                               (0x1<<3) // Autoneg ability.  When read as a one, it indicates that the PMA/PMD has the ability to perform Auto-Negotiation.  When read as a zero, it indicates that the PMA/PMD lacks the ability to perform Auto-Negotiation.
+  #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_AUTONEG_ABILITY_K2_E5_SHIFT                                         3
+  #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_AUTONEG_REMOTE_FAULT_K2_E5                                          (0x1<<4) // Remote Fault
+  #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_AUTONEG_REMOTE_FAULT_K2_E5_SHIFT                                    4
+  #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_AUTONEG_COMPLETE_K2_E5                                              (0x1<<5) // Autoneg has completed and autoneg arbitration FSM is in AN GOOD state.
+  #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_AUTONEG_COMPLETE_K2_E5_SHIFT                                        5
+#define PHY_NW_IP_REG_LN0_ANEG_STATUS1_K2_E5                                                                 0x006644UL //Access:W    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_PAGE_RX_K2_E5                                                       (0x1<<0) // Page Received.   To clear it, write 1 to it.
+  #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_PAGE_RX_K2_E5_SHIFT                                                 0
+  #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_AN_LINK_GOOD_K2_E5                                                  (0x1<<1) // Autoneg has completed and autoneg arbitration FSM is in either AN GOOD CHECK or AN GOOD state.
+  #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_AN_LINK_GOOD_K2_E5_SHIFT                                            1
+  #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_PARALLEL_DET_FAULT_K2_E5                                            (0x1<<2) // Autoneg Parallel Detection Fault.  Write 1 to clear it.
+  #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_PARALLEL_DET_FAULT_K2_E5_SHIFT                                      2
+  #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_NP_LOADED_K2_E5                                                     (0x1<<3) // mr_np_loaded status.
+  #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_NP_LOADED_K2_E5_SHIFT                                               3
+  #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_RESERVEDFIELD629_K2_E5                                              (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_RESERVEDFIELD629_K2_E5_SHIFT                                        4
+  #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_RESERVEDFIELD630_K2_E5                                              (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_RESERVEDFIELD630_K2_E5_SHIFT                                        5
+#define PHY_NW_IP_REG_LN0_ANEG_STATUS_DBG0_K2_E5                                                             0x006650UL //Access:R    DataWidth:0x8    // One-hot sticky capture of AN FSM states.  Bits 7-0
+#define PHY_NW_IP_REG_LN0_ANEG_STATUS_DBG1_K2_E5                                                             0x006654UL //Access:R    DataWidth:0x8    // One-hot sticky capture of AN FSM states.  Bits 15-8
+#define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE0_K2_E5                                                              0x006660UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE0_SELECTOR_K2_E5                                                   (0x1f<<0) // technology Select Field
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE0_SELECTOR_K2_E5_SHIFT                                             0
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE0_ECHOED_NONCE_2_0_K2_E5                                           (0x7<<5) // Echoed Nonce Field bits 2-0.  AN controller generates it.
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE0_ECHOED_NONCE_2_0_K2_E5_SHIFT                                     5
+#define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_K2_E5                                                              0x006664UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_ECHOED_NONCE_4_3_K2_E5                                           (0x3<<0) // Echoed Nonce Field bits 4-3.    AN controller generates it.
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_ECHOED_NONCE_4_3_K2_E5_SHIFT                                     0
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_PAUSE_K2_E5                                                      (0x1<<2) // Pause advertised ability
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_PAUSE_K2_E5_SHIFT                                                2
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_ASM_DIR_K2_E5                                                    (0x1<<3) // Pause ASM_DIR advertised ability
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_ASM_DIR_K2_E5_SHIFT                                              3
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_C2_K2_E5                                                         (0x1<<4) // Reserved always 0
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_C2_K2_E5_SHIFT                                                   4
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_REMOTE_FAULT_K2_E5                                               (0x1<<5) // Remote Fault Local Device
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_REMOTE_FAULT_K2_E5_SHIFT                                         5
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_NEXT_PAGE_K2_E5                                                  (0x1<<7) // Next Page
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_NEXT_PAGE_K2_E5_SHIFT                                            7
+#define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE2_K2_E5                                                              0x006668UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE2_TX_NONCE_K2_E5                                                   (0x1f<<0) // Transmitted Nonce Field.  It is generated in hardware.
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE2_TX_NONCE_K2_E5_SHIFT                                             0
+#define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_K2_E5                                                         0x00666cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_1G_KX_K2_E5                                         (0x1<<0) // 1000Base-KX technology advertised ability
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_1G_KX_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KX4_K2_E5                                       (0x1<<1) // 10GBase-KX4 technology advertised ability
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KX4_K2_E5_SHIFT                                 1
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KR_K2_E5                                        (0x1<<2) // 10GBase-KR technology advertised ability
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KR_K2_E5_SHIFT                                  2
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_40G_KR4_K2_E5                                       (0x1<<3) // 40GBase-KR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_40G_KR4_K2_E5_SHIFT                                 3
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_40G_CR4_K2_E5                                       (0x1<<4) // 40GBase-CR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_40G_CR4_K2_E5_SHIFT                                 4
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_100G_CR10_K2_E5                                     (0x1<<5) // 100GBase-CR10 technology advertised ability
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_100G_CR10_K2_E5_SHIFT                               5
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KP4_K2_E5                                      (0x1<<6) // 100GBase-KP4 technology advertised ability
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KP4_K2_E5_SHIFT                                6
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KR4_K2_E5                                      (0x1<<7) // 100GBase-KR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KR4_K2_E5_SHIFT                                7
+#define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH1_K2_E5                                                         0x006670UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH1_ABILITY_100G_CR4_K2_E5                                      (0x1<<0) // 100GBase-CR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH1_ABILITY_100G_CR4_K2_E5_SHIFT                                0
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_S_K2_E5                                      (0x1<<1) // 25GBase-GR-S KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A9 in base page.
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_S_K2_E5_SHIFT                                1
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_K2_E5                                        (0x1<<2) // 25GBase-GR KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A10 in base page.
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_K2_E5_SHIFT                                  2
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH1_ABILITY_A15_A11_K2_E5                                       (0x1f<<3) // technology advertised ability Field A15-A11
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH1_ABILITY_A15_A11_K2_E5_SHIFT                                 3
+#define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH2_K2_E5                                                         0x006674UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH2_ABILITY_A22_A16_K2_E5                                       (0x7f<<0) // technology advertised ability Field A22-A16
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH2_ABILITY_A22_A16_K2_E5_SHIFT                                 0
+#define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_K2_E5                                                           0x006678UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_FEC_ABILITY_K2_E5                                             (0x1<<0) // base page bit F0.  It advertises FEC ability
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_FEC_ABILITY_K2_E5_SHIFT                                       0
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_FEC_REQ_K2_E5                                                 (0x1<<1) // base page bit F1.  It requests FEC to be turned on when supported at the both ends of link
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_FEC_REQ_K2_E5_SHIFT                                           1
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_RS_FEC_REQ_25G_K2_E5                                          (0x1<<2) // base page bit F2.  It requests RS-FEC for 25G-GR 25G-KR/-CR link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A23 in base page.
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_RS_FEC_REQ_25G_K2_E5_SHIFT                                    2
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_FC_FEC_REQ_25G_K2_E5                                          (0x1<<3) // base page bit F3.  It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A24 in base page.
+  #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_FC_FEC_REQ_25G_K2_E5_SHIFT                                    3
+#define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_K2_E5                                                               0x00667cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_ABILITY_25G_KR_K2_E5                                              (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_ABILITY_25G_KR_K2_E5_SHIFT                                        0
+  #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_ABILITY_25G_CR_K2_E5                                              (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_ABILITY_25G_CR_K2_E5_SHIFT                                        1
+  #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_ABILITY_50G_KR2_K2_E5                                             (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_ABILITY_50G_KR2_K2_E5_SHIFT                                       2
+  #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_ABILITY_50G_CR2_K2_E5                                             (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_ABILITY_50G_CR2_K2_E5_SHIFT                                       3
+  #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_RS_FEC_ABILITY_K2_E5                                              (0x1<<4) // Extended advertised FEC field 0.  It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_RS_FEC_ABILITY_K2_E5_SHIFT                                        4
+  #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_FC_FEC_ABILITY_K2_E5                                              (0x1<<5) // Extended advertised FEC field 1.  It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_FC_FEC_ABILITY_K2_E5_SHIFT                                        5
+  #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_RS_FEC_REQ_K2_E5                                                  (0x1<<6) // Extended advertised FEC field 2.  It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_RS_FEC_REQ_K2_E5_SHIFT                                            6
+  #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_FC_FEC_REQ_K2_E5                                                  (0x1<<7) // Extended advertised FEC field 3.  It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_FC_FEC_REQ_K2_E5_SHIFT                                            7
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1023_K2_E5                                                    0x006680UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1024_K2_E5                                                    0x006684UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1024_RESERVEDFIELD631_K2_E5                                 (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1024_RESERVEDFIELD631_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1024_RESERVEDFIELD632_K2_E5                                 (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1024_RESERVEDFIELD632_K2_E5_SHIFT                           3
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1024_RESERVEDFIELD633_K2_E5                                 (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1024_RESERVEDFIELD633_K2_E5_SHIFT                           4
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1024_RESERVEDFIELD634_K2_E5                                 (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1024_RESERVEDFIELD634_K2_E5_SHIFT                           5
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1024_RESERVEDFIELD635_K2_E5                                 (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1024_RESERVEDFIELD635_K2_E5_SHIFT                           7
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1025_K2_E5                                                    0x006688UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1026_K2_E5                                                    0x00668cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1027_K2_E5                                                    0x006690UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1028_K2_E5                                                    0x006694UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_K2_E5                                                    0x006698UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD636_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD636_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD637_K2_E5                                 (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD637_K2_E5_SHIFT                           1
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD638_K2_E5                                 (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD638_K2_E5_SHIFT                           2
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD639_K2_E5                                 (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD639_K2_E5_SHIFT                           3
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD640_K2_E5                                 (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD640_K2_E5_SHIFT                           4
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD641_K2_E5                                 (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD641_K2_E5_SHIFT                           5
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD642_K2_E5                                 (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD642_K2_E5_SHIFT                           6
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD643_K2_E5                                 (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD643_K2_E5_SHIFT                           7
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1030_K2_E5                                                    0x00669cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1030_RESERVEDFIELD644_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1030_RESERVEDFIELD644_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1030_RESERVEDFIELD645_K2_E5                                 (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1030_RESERVEDFIELD645_K2_E5_SHIFT                           1
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1030_RESERVEDFIELD646_K2_E5                                 (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1030_RESERVEDFIELD646_K2_E5_SHIFT                           2
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1030_RESERVEDFIELD647_K2_E5                                 (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1030_RESERVEDFIELD647_K2_E5_SHIFT                           3
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1030_RESERVEDFIELD648_K2_E5                                 (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1030_RESERVEDFIELD648_K2_E5_SHIFT                           4
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1030_RESERVEDFIELD649_K2_E5                                 (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1030_RESERVEDFIELD649_K2_E5_SHIFT                           5
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1030_RESERVEDFIELD650_K2_E5                                 (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1030_RESERVEDFIELD650_K2_E5_SHIFT                           6
+#define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE0_K2_E5                                                           0x0066a0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE0_SELECTOR_K2_E5                                                (0x1f<<0) // Link partner technology Select Field
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE0_SELECTOR_K2_E5_SHIFT                                          0
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE0_ECHOED_NONCE_2_0_K2_E5                                        (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE0_ECHOED_NONCE_2_0_K2_E5_SHIFT                                  5
+#define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_K2_E5                                                           0x0066a4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_ECHOED_NONCE_4_3_K2_E5                                        (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_ECHOED_NONCE_4_3_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_PAUSE_K2_E5                                                   (0x1<<2) // Link partner Pause advertised ability
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_PAUSE_K2_E5_SHIFT                                             2
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_ASM_DIR_K2_E5                                                 (0x1<<3) // Link partner Pause ASM_DIR advertised ability
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_ASM_DIR_K2_E5_SHIFT                                           3
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_C2_K2_E5                                                      (0x1<<4) // Link partner C2 field always 0
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_C2_K2_E5_SHIFT                                                4
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_REMOTE_FAULT_K2_E5                                            (0x1<<5) // Link partner Remote Fault
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_REMOTE_FAULT_K2_E5_SHIFT                                      5
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_ACK_K2_E5                                                     (0x1<<6) // Link partner Acknowledge always 0
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_ACK_K2_E5_SHIFT                                               6
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_NEXT_PAGE_K2_E5                                               (0x1<<7) // Link partner Next Page
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_NEXT_PAGE_K2_E5_SHIFT                                         7
+#define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE2_K2_E5                                                           0x0066a8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE2_TX_NONCE_K2_E5                                                (0x1f<<0) // Transmitted Nonce Field from Link partner
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE2_TX_NONCE_K2_E5_SHIFT                                          0
+#define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_K2_E5                                                      0x0066acUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_1G_KX_K2_E5                                      (0x1<<0) // Link partner 1000Base-KX technology advertised ability
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_1G_KX_K2_E5_SHIFT                                0
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KX4_K2_E5                                    (0x1<<1) // Link partner 10GBase-KX4 technology advertised ability
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KX4_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KR_K2_E5                                     (0x1<<2) // Link partner 10GBase-KR technology advertised ability
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KR_K2_E5_SHIFT                               2
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_KR4_K2_E5                                    (0x1<<3) // Link partner 40GBase-KR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_KR4_K2_E5_SHIFT                              3
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_CR4_K2_E5                                    (0x1<<4) // Link partner 40GBase-CR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_CR4_K2_E5_SHIFT                              4
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_CR10_K2_E5                                  (0x1<<5) // Link partner 100GBase-CR10 technology advertised ability
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_CR10_K2_E5_SHIFT                            5
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KP4_K2_E5                                   (0x1<<6) // Link partner 100GBase-KP4 technology advertised ability
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KP4_K2_E5_SHIFT                             6
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KR4_K2_E5                                   (0x1<<7) // Link partner 100GBase-KR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KR4_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH1_K2_E5                                                      0x0066b0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH1_ABILITY_100G_CR4_K2_E5                                   (0x1<<0) // Link partner 100GBase-CR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH1_ABILITY_100G_CR4_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_S_K2_E5                                   (0x1<<1) // Link partner 25GBase-GR-S KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A9 in base page.
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_S_K2_E5_SHIFT                             1
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_K2_E5                                     (0x1<<2) // Link partner 25GBase-GR KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A10 in base page.
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_K2_E5_SHIFT                               2
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH1_ABILITY_A15_A11_K2_E5                                    (0x1f<<3) // Link partner technology advertised ability Field A15-A11
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH1_ABILITY_A15_A11_K2_E5_SHIFT                              3
+#define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH2_K2_E5                                                      0x0066b4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH2_ABILITY_A22_A16_K2_E5                                    (0x7f<<0) // Link partner technology advertised ability Field A22-A16
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH2_ABILITY_A22_A16_K2_E5_SHIFT                              0
+#define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_K2_E5                                                        0x0066b8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_FEC_ABILITY_K2_E5                                          (0x1<<0) // Link partner base page bit F0.  It advertises FEC ability
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_FEC_ABILITY_K2_E5_SHIFT                                    0
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_FEC_REQ_K2_E5                                              (0x1<<1) // Link partner base page bit F1.  It requests FEC to be turned on when supported at the both ends of link
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_FEC_REQ_K2_E5_SHIFT                                        1
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_RS_FEC_REQ_25G_K2_E5                                       (0x1<<2) // Link partner base page bit F2.  It requests RS-FEC for 25G-GR 25G-KR/-CR link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A23 in base page.
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_RS_FEC_REQ_25G_K2_E5_SHIFT                                 2
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_FC_FEC_REQ_25G_K2_E5                                       (0x1<<3) // Link partner base page bit F3.  It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A24 in base page.
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_FC_FEC_REQ_25G_K2_E5_SHIFT                                 3
+#define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_K2_E5                                                            0x0066bcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_ABILITY_25G_KR_K2_E5                                           (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_ABILITY_25G_KR_K2_E5_SHIFT                                     0
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_ABILITY_25G_CR_K2_E5                                           (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_ABILITY_25G_CR_K2_E5_SHIFT                                     1
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_ABILITY_50G_KR2_K2_E5                                          (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_ABILITY_50G_KR2_K2_E5_SHIFT                                    2
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_ABILITY_50G_CR2_K2_E5                                          (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_ABILITY_50G_CR2_K2_E5_SHIFT                                    3
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_RS_FEC_ABILITY_K2_E5                                           (0x1<<4) // Link partner extended advertised FEC field 0.  It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_RS_FEC_ABILITY_K2_E5_SHIFT                                     4
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_FC_FEC_ABILITY_K2_E5                                           (0x1<<5) // Link partner extended advertised FEC field 1.  It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_FC_FEC_ABILITY_K2_E5_SHIFT                                     5
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_RS_FEC_REQ_K2_E5                                               (0x1<<6) // Link partner extended advertised FEC field 2.  It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_RS_FEC_REQ_K2_E5_SHIFT                                         6
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_FC_FEC_REQ_K2_E5                                               (0x1<<7) // Link partner extended advertised FEC field 3.  It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_FC_FEC_REQ_K2_E5_SHIFT                                         7
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1031_K2_E5                                                    0x0066c0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1032_K2_E5                                                    0x0066c4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1032_RESERVEDFIELD651_K2_E5                                 (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1032_RESERVEDFIELD651_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1032_RESERVEDFIELD652_K2_E5                                 (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1032_RESERVEDFIELD652_K2_E5_SHIFT                           3
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1032_RESERVEDFIELD653_K2_E5                                 (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1032_RESERVEDFIELD653_K2_E5_SHIFT                           4
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1032_RESERVEDFIELD654_K2_E5                                 (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1032_RESERVEDFIELD654_K2_E5_SHIFT                           5
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1032_RESERVEDFIELD655_K2_E5                                 (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1032_RESERVEDFIELD655_K2_E5_SHIFT                           7
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1033_K2_E5                                                    0x0066c8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1034_K2_E5                                                    0x0066ccUL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1035_K2_E5                                                    0x0066d0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1036_K2_E5                                                    0x0066d4UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_K2_E5                                                    0x0066d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD656_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD656_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD657_K2_E5                                 (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD657_K2_E5_SHIFT                           1
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD658_K2_E5                                 (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD658_K2_E5_SHIFT                           2
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD659_K2_E5                                 (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD659_K2_E5_SHIFT                           3
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD660_K2_E5                                 (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD660_K2_E5_SHIFT                           4
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD661_K2_E5                                 (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD661_K2_E5_SHIFT                           5
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD662_K2_E5                                 (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD662_K2_E5_SHIFT                           6
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD663_K2_E5                                 (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD663_K2_E5_SHIFT                           7
+#define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1038_K2_E5                                                    0x0066dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1038_RESERVEDFIELD664_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1038_RESERVEDFIELD664_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1038_RESERVEDFIELD665_K2_E5                                 (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1038_RESERVEDFIELD665_K2_E5_SHIFT                           1
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1038_RESERVEDFIELD666_K2_E5                                 (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1038_RESERVEDFIELD666_K2_E5_SHIFT                           2
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1038_RESERVEDFIELD667_K2_E5                                 (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1038_RESERVEDFIELD667_K2_E5_SHIFT                           3
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1038_RESERVEDFIELD668_K2_E5                                 (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1038_RESERVEDFIELD668_K2_E5_SHIFT                           4
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1038_RESERVEDFIELD669_K2_E5                                 (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1038_RESERVEDFIELD669_K2_E5_SHIFT                           5
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1038_RESERVEDFIELD670_K2_E5                                 (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1038_RESERVEDFIELD670_K2_E5_SHIFT                           6
+#define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_K2_E5                                                        0x0066e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_1G_KX_K2_E5                                        (0x1<<0) // Resolution result for 1000Base-KX.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_1G_KX_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_10G_KX4_K2_E5                                      (0x1<<1) // Resolution result for 10GBase-KX4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_10G_KX4_K2_E5_SHIFT                                1
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_10G_KR_K2_E5                                       (0x1<<2) // Resolution result for 10GBase-KR.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_10G_KR_K2_E5_SHIFT                                 2
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_40G_KR4_K2_E5                                      (0x1<<3) // Resolution result for 40GBase-KR4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_40G_KR4_K2_E5_SHIFT                                3
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_40G_CR4_K2_E5                                      (0x1<<4) // Resolution result for 40GBase-CR4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_40G_CR4_K2_E5_SHIFT                                4
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_100G_CR10_K2_E5                                    (0x1<<5) // Resolution result for 100GBase-CR10.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_100G_CR10_K2_E5_SHIFT                              5
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_100G_KP4_K2_E5                                     (0x1<<6) // Resolution result for 100GBase-KP4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_100G_KP4_K2_E5_SHIFT                               6
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_100G_KR4_K2_E5                                     (0x1<<7) // Resolution result for 100GBase-KR4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_100G_KR4_K2_E5_SHIFT                               7
+#define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_K2_E5                                                        0x0066e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_100G_CR4_K2_E5                                     (0x1<<0) // Resolution result for 100GBase-CR4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_100G_CR4_K2_E5_SHIFT                               0
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_S_K2_E5                                     (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_S_K2_E5_SHIFT                               1
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_K2_E5                                       (0x1<<2) // Resolution result for 25GBase-GR KR or CR.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_K2_E5_SHIFT                                 2
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_25G_KR_K2_E5                                       (0x1<<3) // Resolution result for 25GBase-KR.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_25G_KR_K2_E5_SHIFT                                 3
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_25G_CR_K2_E5                                       (0x1<<4) // Resolution result for 25GBase-CR4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_25G_CR_K2_E5_SHIFT                                 4
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_50G_KR2_K2_E5                                      (0x1<<5) // Resolution result for 50GBase-KR2.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_50G_KR2_K2_E5_SHIFT                                5
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_50G_CR2_K2_E5                                      (0x1<<6) // Resolution result for 50GBase-CR2.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_50G_CR2_K2_E5_SHIFT                                6
+#define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_FEC_K2_E5                                                          0x0066e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_FEC_RS_K2_E5                                                     (0x1<<0) // Resolution result for Reed-Solomon FEC.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_FEC_RS_K2_E5_SHIFT                                               0
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_FEC_FC_K2_E5                                                     (0x1<<1) // Resolution result for Firecode base page FEC.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_FEC_FC_K2_E5_SHIFT                                               1
+#define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_PAUSE_K2_E5                                                        0x0066ecUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_PAUSE_RX_K2_E5                                                   (0x1<<0) // Resolution result for RX PAUSE enable.    It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_PAUSE_RX_K2_E5_SHIFT                                             0
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_PAUSE_TX_K2_E5                                                   (0x1<<1) // Resolution result for TX PAUSE enable.    It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_PAUSE_TX_K2_E5_SHIFT                                             1
+#define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_EEE_K2_E5                                                          0x0066f0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_EEE_F746_K2_E5                                                   (0x1<<0) // Resolution result for EEE.  It is 1 if both the local device and the link partner advertise the EEE capability for the resolved PHY type.  It is 0 otherwise.  It is valid when status0.an_link_good is 1. Note that it indicates EEE deep sleep capability.
+  #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_EEE_F746_K2_E5_SHIFT                                             0
+#define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_K2_E5                                                            0x0066f8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_1G_KX_K2_E5                                            (0x1<<0) // link_status for 1000Base-KX
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_1G_KX_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_10G_KX4_K2_E5                                          (0x1<<1) // link_status for 10GBase-KX4
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_10G_KX4_K2_E5_SHIFT                                    1
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_10G_KR_K2_E5                                           (0x1<<2) // link_status for 10GBase-KR
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_10G_KR_K2_E5_SHIFT                                     2
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_40G_KR4_K2_E5                                          (0x1<<3) // link_status for 40GBase-KR4
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_40G_KR4_K2_E5_SHIFT                                    3
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_40G_CR4_K2_E5                                          (0x1<<4) // link_status for 40GBase-CR4
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_40G_CR4_K2_E5_SHIFT                                    4
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_100G_CR10_K2_E5                                        (0x1<<5) // link_status for 100GBase-CR10
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_100G_CR10_K2_E5_SHIFT                                  5
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_100G_KP4_K2_E5                                         (0x1<<6) // link_status for 100GBase-KP4
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_100G_KP4_K2_E5_SHIFT                                   6
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_100G_KR4_K2_E5                                         (0x1<<7) // link_status for 100GBase-KR4
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_100G_KR4_K2_E5_SHIFT                                   7
+#define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_K2_E5                                                            0x0066fcUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_100G_CR4_K2_E5                                         (0x1<<0) // link_status for 100GBase-CR4
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_100G_CR4_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_25G_GR_K2_E5                                           (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_25G_GR_K2_E5_SHIFT                                     1
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_25G_KR_K2_E5                                           (0x1<<3) // link_status for 25GBase-KR
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_25G_KR_K2_E5_SHIFT                                     3
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_25G_CR_K2_E5                                           (0x1<<4) // link_status for 25GBase-CR4
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_25G_CR_K2_E5_SHIFT                                     4
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_50G_KR2_K2_E5                                          (0x1<<5) // link_status for 50GBase-KR2
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_50G_KR2_K2_E5_SHIFT                                    5
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_50G_CR2_K2_E5                                          (0x1<<6) // link_status for 50GBase-CR2
+  #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_50G_CR2_K2_E5_SHIFT                                    6
+#define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1039_K2_E5                                                     0x006704UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1039_RESERVEDFIELD671_K2_E5                                  (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1039_RESERVEDFIELD671_K2_E5_SHIFT                            0
+  #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1039_RESERVEDFIELD672_K2_E5                                  (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1039_RESERVEDFIELD672_K2_E5_SHIFT                            2
+#define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1040_K2_E5                                                     0x006708UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1040_RESERVEDFIELD673_K2_E5                                  (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1040_RESERVEDFIELD673_K2_E5_SHIFT                            0
+#define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1041_K2_E5                                                     0x00670cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1041_RESERVEDFIELD674_K2_E5                                  (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1041_RESERVEDFIELD674_K2_E5_SHIFT                            0
+#define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1042_K2_E5                                                     0x006714UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1042_RESERVEDFIELD675_K2_E5                                  (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1042_RESERVEDFIELD675_K2_E5_SHIFT                            0
+  #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1042_RESERVEDFIELD676_K2_E5                                  (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1042_RESERVEDFIELD676_K2_E5_SHIFT                            1
+  #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1042_RESERVEDFIELD677_K2_E5                                  (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1042_RESERVEDFIELD677_K2_E5_SHIFT                            3
+  #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1042_RESERVEDFIELD678_K2_E5                                  (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1042_RESERVEDFIELD678_K2_E5_SHIFT                            4
+#define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1043_K2_E5                                                     0x006718UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1043_RESERVEDFIELD679_K2_E5                                  (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1043_RESERVEDFIELD679_K2_E5_SHIFT                            0
+#define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1044_K2_E5                                                     0x00671cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1045_K2_E5                                                     0x006720UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1046_K2_E5                                              0x006800UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1046_RESERVEDFIELD682_K2_E5                           (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1046_RESERVEDFIELD682_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1046_RESERVEDFIELD683_K2_E5                           (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1046_RESERVEDFIELD683_K2_E5_SHIFT                     6
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1047_K2_E5                                              0x006808UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1048_K2_E5                                              0x00680cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1048_RESERVEDFIELD685_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1048_RESERVEDFIELD685_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1048_RESERVEDFIELD686_K2_E5                           (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1048_RESERVEDFIELD686_K2_E5_SHIFT                     3
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1049_K2_E5                                              0x006814UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1049_RESERVEDFIELD687_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1049_RESERVEDFIELD687_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1049_RESERVEDFIELD688_K2_E5                           (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1049_RESERVEDFIELD688_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1049_RESERVEDFIELD689_K2_E5                           (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1049_RESERVEDFIELD689_K2_E5_SHIFT                     3
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1050_K2_E5                                              0x00681cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1050_RESERVEDFIELD690_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1050_RESERVEDFIELD690_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1051_K2_E5                                              0x006824UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1051_RESERVEDFIELD691_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1051_RESERVEDFIELD691_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1052_K2_E5                                              0x006828UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1052_RESERVEDFIELD692_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1052_RESERVEDFIELD692_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1052_RESERVEDFIELD693_K2_E5                           (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1052_RESERVEDFIELD693_K2_E5_SHIFT                     3
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1053_K2_E5                                              0x00682cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1053_RESERVEDFIELD694_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1053_RESERVEDFIELD694_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1053_RESERVEDFIELD695_K2_E5                           (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1053_RESERVEDFIELD695_K2_E5_SHIFT                     3
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1054_K2_E5                                              0x006830UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1054_RESERVEDFIELD696_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1054_RESERVEDFIELD696_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1054_RESERVEDFIELD697_K2_E5                           (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1054_RESERVEDFIELD697_K2_E5_SHIFT                     2
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1054_RESERVEDFIELD698_K2_E5                           (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1054_RESERVEDFIELD698_K2_E5_SHIFT                     4
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1054_RESERVEDFIELD699_K2_E5                           (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1054_RESERVEDFIELD699_K2_E5_SHIFT                     6
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1055_K2_E5                                              0x006838UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1055_RESERVEDFIELD700_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1055_RESERVEDFIELD700_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1055_RESERVEDFIELD701_K2_E5                           (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1055_RESERVEDFIELD701_K2_E5_SHIFT                     3
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1056_K2_E5                                              0x00683cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1056_RESERVEDFIELD702_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1056_RESERVEDFIELD702_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1056_RESERVEDFIELD703_K2_E5                           (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1056_RESERVEDFIELD703_K2_E5_SHIFT                     3
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1057_K2_E5                                              0x006840UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1057_RESERVEDFIELD704_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1057_RESERVEDFIELD704_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1057_RESERVEDFIELD705_K2_E5                           (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1057_RESERVEDFIELD705_K2_E5_SHIFT                     3
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1058_K2_E5                                              0x006844UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1058_RESERVEDFIELD706_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1058_RESERVEDFIELD706_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1058_RESERVEDFIELD707_K2_E5                           (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1058_RESERVEDFIELD707_K2_E5_SHIFT                     3
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1059_K2_E5                                              0x006880UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1059_RESERVEDFIELD708_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1059_RESERVEDFIELD708_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1059_RESERVEDFIELD709_K2_E5                           (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1059_RESERVEDFIELD709_K2_E5_SHIFT                     2
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1060_K2_E5                                              0x006884UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1060_RESERVEDFIELD710_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1060_RESERVEDFIELD710_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1060_RESERVEDFIELD711_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1060_RESERVEDFIELD711_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1061_K2_E5                                              0x006888UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1062_K2_E5                                              0x00688cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1063_K2_E5                                              0x006890UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1063_RESERVEDFIELD714_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1063_RESERVEDFIELD714_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1063_RESERVEDFIELD715_K2_E5                           (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1063_RESERVEDFIELD715_K2_E5_SHIFT                     3
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1063_RESERVEDFIELD716_K2_E5                           (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1063_RESERVEDFIELD716_K2_E5_SHIFT                     6
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1063_RESERVEDFIELD717_K2_E5                           (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1063_RESERVEDFIELD717_K2_E5_SHIFT                     7
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1064_K2_E5                                              0x006894UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1064_RESERVEDFIELD718_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1064_RESERVEDFIELD718_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1064_RESERVEDFIELD719_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1064_RESERVEDFIELD719_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1065_K2_E5                                              0x006898UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1066_K2_E5                                              0x00689cUL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1067_K2_E5                                              0x0068a0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1067_RESERVEDFIELD722_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1067_RESERVEDFIELD722_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1067_RESERVEDFIELD723_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1067_RESERVEDFIELD723_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1068_K2_E5                                              0x0068a4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1069_K2_E5                                              0x0068a8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1070_K2_E5                                              0x0068acUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1070_RESERVEDFIELD726_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1070_RESERVEDFIELD726_K2_E5_SHIFT                     1
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1071_K2_E5                                              0x0068b0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1072_K2_E5                                              0x0068b8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_AGCLOS_CTRL0_K2_E5                                                      0x0068c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_AGCLOS_CTRL0_AGCLOS_START_K2_E5                                       (0xf<<0) // AGC LOS Threshold Start Value
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_AGCLOS_CTRL0_AGCLOS_START_K2_E5_SHIFT                                 0
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1073_K2_E5                                              0x0068c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1073_RESERVEDFIELD729_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1073_RESERVEDFIELD729_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1074_K2_E5                                              0x0068c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1074_RESERVEDFIELD730_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1074_RESERVEDFIELD730_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1075_K2_E5                                              0x0068ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1075_RESERVEDFIELD731_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1075_RESERVEDFIELD731_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1075_RESERVEDFIELD732_K2_E5                           (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1075_RESERVEDFIELD732_K2_E5_SHIFT                     6
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1075_RESERVEDFIELD733_K2_E5                           (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1075_RESERVEDFIELD733_K2_E5_SHIFT                     7
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1076_K2_E5                                              0x0068d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1076_RESERVEDFIELD734_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1076_RESERVEDFIELD734_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1076_RESERVEDFIELD735_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1076_RESERVEDFIELD735_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1076_RESERVEDFIELD736_K2_E5                           (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1076_RESERVEDFIELD736_K2_E5_SHIFT                     2
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1077_K2_E5                                              0x0068d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1077_RESERVEDFIELD737_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1077_RESERVEDFIELD737_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1077_RESERVEDFIELD738_K2_E5                           (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1077_RESERVEDFIELD738_K2_E5_SHIFT                     4
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1077_RESERVEDFIELD739_K2_E5                           (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1077_RESERVEDFIELD739_K2_E5_SHIFT                     6
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1078_K2_E5                                              0x0068d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1078_RESERVEDFIELD740_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1078_RESERVEDFIELD740_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1079_K2_E5                                              0x0068dcUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1080_K2_E5                                              0x0068e0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1081_K2_E5                                              0x0068e4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1082_K2_E5                                              0x0068e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1082_RESERVEDFIELD744_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1082_RESERVEDFIELD744_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1083_K2_E5                                              0x0068f4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1083_RESERVEDFIELD745_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1083_RESERVEDFIELD745_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1083_RESERVEDFIELD746_K2_E5                           (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1083_RESERVEDFIELD746_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_PLE_ATT_CTRL1_K2_E5                                                     0x0068f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_PLE_ATT_CTRL1_PLE_ATT_START_K2_E5                                     (0x7<<0) // PLE LFG Start Value
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_PLE_ATT_CTRL1_PLE_ATT_START_K2_E5_SHIFT                               0
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_K2_E5                                                  0x006900UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_EQ_HFG_SQL_START_K2_E5                               (0x1f<<0) // CTLE HFG Start Value
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_EQ_HFG_SQL_START_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1084_K2_E5                                              0x006904UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1084_RESERVEDFIELD747_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1084_RESERVEDFIELD747_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1085_K2_E5                                              0x006908UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1085_RESERVEDFIELD748_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1085_RESERVEDFIELD748_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1086_K2_E5                                              0x00690cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1086_RESERVEDFIELD749_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1086_RESERVEDFIELD749_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1086_RESERVEDFIELD750_K2_E5                           (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1086_RESERVEDFIELD750_K2_E5_SHIFT                     7
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1087_K2_E5                                              0x006910UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1087_RESERVEDFIELD751_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1087_RESERVEDFIELD751_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1087_RESERVEDFIELD752_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1087_RESERVEDFIELD752_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1087_RESERVEDFIELD753_K2_E5                           (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1087_RESERVEDFIELD753_K2_E5_SHIFT                     2
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1088_K2_E5                                              0x006914UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1088_RESERVEDFIELD754_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1088_RESERVEDFIELD754_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1088_RESERVEDFIELD755_K2_E5                           (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1088_RESERVEDFIELD755_K2_E5_SHIFT                     4
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1088_RESERVEDFIELD756_K2_E5                           (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1088_RESERVEDFIELD756_K2_E5_SHIFT                     6
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1089_K2_E5                                              0x006918UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1089_RESERVEDFIELD757_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1089_RESERVEDFIELD757_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1090_K2_E5                                              0x006940UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1090_RESERVEDFIELD758_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1090_RESERVEDFIELD758_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1090_RESERVEDFIELD759_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1090_RESERVEDFIELD759_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1090_RESERVEDFIELD760_K2_E5                           (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1090_RESERVEDFIELD760_K2_E5_SHIFT                     2
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1090_RESERVEDFIELD761_K2_E5                           (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1090_RESERVEDFIELD761_K2_E5_SHIFT                     3
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1091_K2_E5                                              0x006944UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1091_RESERVEDFIELD762_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1091_RESERVEDFIELD762_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1091_RESERVEDFIELD763_K2_E5                           (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1091_RESERVEDFIELD763_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1092_K2_E5                                              0x006948UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1092_RESERVEDFIELD764_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1092_RESERVEDFIELD764_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1092_RESERVEDFIELD765_K2_E5                           (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1092_RESERVEDFIELD765_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1093_K2_E5                                              0x00694cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1093_RESERVEDFIELD766_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1093_RESERVEDFIELD766_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1093_RESERVEDFIELD767_K2_E5                           (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1093_RESERVEDFIELD767_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1094_K2_E5                                              0x006950UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1094_RESERVEDFIELD768_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1094_RESERVEDFIELD768_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1094_RESERVEDFIELD769_K2_E5                           (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1094_RESERVEDFIELD769_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1095_K2_E5                                              0x006954UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1095_RESERVEDFIELD770_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1095_RESERVEDFIELD770_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1095_RESERVEDFIELD771_K2_E5                           (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1095_RESERVEDFIELD771_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1096_K2_E5                                              0x006958UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1096_RESERVEDFIELD772_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1096_RESERVEDFIELD772_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1096_RESERVEDFIELD773_K2_E5                           (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1096_RESERVEDFIELD773_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1097_K2_E5                                              0x00695cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1097_RESERVEDFIELD774_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1097_RESERVEDFIELD774_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1097_RESERVEDFIELD775_K2_E5                           (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1097_RESERVEDFIELD775_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1098_K2_E5                                              0x006960UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1098_RESERVEDFIELD776_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1098_RESERVEDFIELD776_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1098_RESERVEDFIELD777_K2_E5                           (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1098_RESERVEDFIELD777_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1099_K2_E5                                              0x006964UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1099_RESERVEDFIELD778_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1099_RESERVEDFIELD778_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1099_RESERVEDFIELD779_K2_E5                           (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1099_RESERVEDFIELD779_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1100_K2_E5                                              0x006968UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1100_RESERVEDFIELD780_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1100_RESERVEDFIELD780_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1100_RESERVEDFIELD781_K2_E5                           (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1100_RESERVEDFIELD781_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1101_K2_E5                                              0x00696cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1101_RESERVEDFIELD782_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1101_RESERVEDFIELD782_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1101_RESERVEDFIELD783_K2_E5                           (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1101_RESERVEDFIELD783_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1102_K2_E5                                              0x006970UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1102_RESERVEDFIELD784_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1102_RESERVEDFIELD784_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1102_RESERVEDFIELD785_K2_E5                           (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1102_RESERVEDFIELD785_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1103_K2_E5                                              0x006974UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1103_RESERVEDFIELD786_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1103_RESERVEDFIELD786_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1103_RESERVEDFIELD787_K2_E5                           (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1103_RESERVEDFIELD787_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1104_K2_E5                                              0x006978UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1104_RESERVEDFIELD788_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1104_RESERVEDFIELD788_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1104_RESERVEDFIELD789_K2_E5                           (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1104_RESERVEDFIELD789_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1105_K2_E5                                              0x00697cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1105_RESERVEDFIELD790_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1105_RESERVEDFIELD790_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1105_RESERVEDFIELD791_K2_E5                           (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1105_RESERVEDFIELD791_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1106_K2_E5                                              0x006980UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1106_RESERVEDFIELD792_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1106_RESERVEDFIELD792_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1106_RESERVEDFIELD793_K2_E5                           (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1106_RESERVEDFIELD793_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1107_K2_E5                                              0x006984UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1107_RESERVEDFIELD794_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1107_RESERVEDFIELD794_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1107_RESERVEDFIELD795_K2_E5                           (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1107_RESERVEDFIELD795_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1108_K2_E5                                              0x006988UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1108_RESERVEDFIELD796_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1108_RESERVEDFIELD796_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1108_RESERVEDFIELD797_K2_E5                           (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1108_RESERVEDFIELD797_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1109_K2_E5                                              0x00698cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1109_RESERVEDFIELD798_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1109_RESERVEDFIELD798_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1109_RESERVEDFIELD799_K2_E5                           (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1109_RESERVEDFIELD799_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1110_K2_E5                                              0x006990UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1110_RESERVEDFIELD800_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1110_RESERVEDFIELD800_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1110_RESERVEDFIELD801_K2_E5                           (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1110_RESERVEDFIELD801_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1111_K2_E5                                              0x006994UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1111_RESERVEDFIELD802_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1111_RESERVEDFIELD802_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1111_RESERVEDFIELD803_K2_E5                           (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1111_RESERVEDFIELD803_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1112_K2_E5                                              0x006998UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1112_RESERVEDFIELD804_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1112_RESERVEDFIELD804_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1112_RESERVEDFIELD805_K2_E5                           (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1112_RESERVEDFIELD805_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1113_K2_E5                                              0x00699cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1113_RESERVEDFIELD806_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1113_RESERVEDFIELD806_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1113_RESERVEDFIELD807_K2_E5                           (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1113_RESERVEDFIELD807_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1114_K2_E5                                              0x0069a0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1114_RESERVEDFIELD808_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1114_RESERVEDFIELD808_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1114_RESERVEDFIELD809_K2_E5                           (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1114_RESERVEDFIELD809_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_GN_APG_CTRL0_K2_E5                                                      0x0069c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_GN_APG_CTRL0_GN_APG_START_K2_E5                                       (0x3<<0) // GN APG Start Value
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_GN_APG_CTRL0_GN_APG_START_K2_E5_SHIFT                                 0
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1115_K2_E5                                              0x0069c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1115_RESERVEDFIELD810_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1115_RESERVEDFIELD810_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1115_RESERVEDFIELD811_K2_E5                           (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1115_RESERVEDFIELD811_K2_E5_SHIFT                     2
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1116_K2_E5                                              0x0069c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1116_RESERVEDFIELD812_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1116_RESERVEDFIELD812_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1116_RESERVEDFIELD813_K2_E5                           (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1116_RESERVEDFIELD813_K2_E5_SHIFT                     7
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1117_K2_E5                                              0x0069ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1117_RESERVEDFIELD814_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1117_RESERVEDFIELD814_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1117_RESERVEDFIELD815_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1117_RESERVEDFIELD815_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1117_RESERVEDFIELD816_K2_E5                           (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1117_RESERVEDFIELD816_K2_E5_SHIFT                     2
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1118_K2_E5                                              0x0069d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1118_RESERVEDFIELD817_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1118_RESERVEDFIELD817_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1118_RESERVEDFIELD818_K2_E5                           (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1118_RESERVEDFIELD818_K2_E5_SHIFT                     4
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1118_RESERVEDFIELD819_K2_E5                           (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1118_RESERVEDFIELD819_K2_E5_SHIFT                     6
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1119_K2_E5                                              0x0069d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1119_RESERVEDFIELD820_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1119_RESERVEDFIELD820_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1120_K2_E5                                              0x0069d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1120_RESERVEDFIELD821_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1120_RESERVEDFIELD821_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1120_RESERVEDFIELD822_K2_E5                           (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1120_RESERVEDFIELD822_K2_E5_SHIFT                     2
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_LFG_CTRL0_K2_E5                                                      0x006a00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_LFG_CTRL0_EQ_LFG_START_K2_E5                                       (0x1f<<0) // EQ LFG Start Value
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_LFG_CTRL0_EQ_LFG_START_K2_E5_SHIFT                                 0
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_LFG_CTRL1_K2_E5                                                      0x006a04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_LFG_CTRL1_EQ_LFG_VALUE_MAX_K2_E5                                   (0x1f<<0) // EQ LFG Maximum Value, inclusive
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_LFG_CTRL1_EQ_LFG_VALUE_MAX_K2_E5_SHIFT                             0
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_LFG_CTRL2_K2_E5                                                      0x006a08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_LFG_CTRL2_EQ_LFG_VALUE_MIN_K2_E5                                   (0x1f<<0) // EQ LFG Minimum Value, inclusive
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_LFG_CTRL2_EQ_LFG_VALUE_MIN_K2_E5_SHIFT                             0
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1121_K2_E5                                              0x006a0cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1121_RESERVEDFIELD823_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1121_RESERVEDFIELD823_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1121_RESERVEDFIELD824_K2_E5                           (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1121_RESERVEDFIELD824_K2_E5_SHIFT                     7
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1122_K2_E5                                              0x006a10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1122_RESERVEDFIELD825_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1122_RESERVEDFIELD825_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1122_RESERVEDFIELD826_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1122_RESERVEDFIELD826_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1122_RESERVEDFIELD827_K2_E5                           (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1122_RESERVEDFIELD827_K2_E5_SHIFT                     2
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1123_K2_E5                                              0x006a14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1123_RESERVEDFIELD828_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1123_RESERVEDFIELD828_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1123_RESERVEDFIELD829_K2_E5                           (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1123_RESERVEDFIELD829_K2_E5_SHIFT                     4
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1123_RESERVEDFIELD830_K2_E5                           (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1123_RESERVEDFIELD830_K2_E5_SHIFT                     6
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1124_K2_E5                                              0x006a18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1124_RESERVEDFIELD831_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1124_RESERVEDFIELD831_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1125_K2_E5                                              0x006a1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1125_RESERVEDFIELD832_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1125_RESERVEDFIELD832_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1126_K2_E5                                              0x006a20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1126_RESERVEDFIELD833_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1126_RESERVEDFIELD833_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1127_K2_E5                                              0x006a40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1127_RESERVEDFIELD834_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1127_RESERVEDFIELD834_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1128_K2_E5                                              0x006a44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1128_RESERVEDFIELD835_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1128_RESERVEDFIELD835_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1129_K2_E5                                              0x006a48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1129_RESERVEDFIELD836_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1129_RESERVEDFIELD836_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1130_K2_E5                                              0x006a4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1130_RESERVEDFIELD837_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1130_RESERVEDFIELD837_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1130_RESERVEDFIELD838_K2_E5                           (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1130_RESERVEDFIELD838_K2_E5_SHIFT                     7
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1131_K2_E5                                              0x006a50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1131_RESERVEDFIELD839_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1131_RESERVEDFIELD839_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1131_RESERVEDFIELD840_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1131_RESERVEDFIELD840_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1131_RESERVEDFIELD841_K2_E5                           (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1131_RESERVEDFIELD841_K2_E5_SHIFT                     2
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1132_K2_E5                                              0x006a54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1132_RESERVEDFIELD842_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1132_RESERVEDFIELD842_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1132_RESERVEDFIELD843_K2_E5                           (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1132_RESERVEDFIELD843_K2_E5_SHIFT                     4
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1132_RESERVEDFIELD844_K2_E5                           (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1132_RESERVEDFIELD844_K2_E5_SHIFT                     6
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1133_K2_E5                                              0x006a58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1133_RESERVEDFIELD845_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1133_RESERVEDFIELD845_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1134_K2_E5                                              0x006a60UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1134_RESERVEDFIELD846_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1134_RESERVEDFIELD846_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1134_RESERVEDFIELD847_K2_E5                           (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1134_RESERVEDFIELD847_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_MB_CTRL1_K2_E5                                                       0x006a64UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_K2_E5                                        (0xf<<0) // EQ MBF Start Value
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_K2_E5                                        (0xf<<4) // EQ MBG Start Value
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_K2_E5_SHIFT                                  4
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1135_K2_E5                                              0x006a68UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1136_K2_E5                                              0x006a6cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1137_K2_E5                                              0x006a70UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1137_RESERVEDFIELD850_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1137_RESERVEDFIELD850_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1137_RESERVEDFIELD851_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1137_RESERVEDFIELD851_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1137_RESERVEDFIELD852_K2_E5                           (0xf<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1137_RESERVEDFIELD852_K2_E5_SHIFT                     2
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1138_K2_E5                                              0x006a74UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1138_RESERVEDFIELD853_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1138_RESERVEDFIELD853_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1138_RESERVEDFIELD854_K2_E5                           (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1138_RESERVEDFIELD854_K2_E5_SHIFT                     4
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1138_RESERVEDFIELD855_K2_E5                           (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1138_RESERVEDFIELD855_K2_E5_SHIFT                     6
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1139_K2_E5                                              0x006a80UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1140_K2_E5                                              0x006a84UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1141_K2_E5                                              0x006a88UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1141_RESERVEDFIELD858_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1141_RESERVEDFIELD858_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1141_RESERVEDFIELD859_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1141_RESERVEDFIELD859_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1141_RESERVEDFIELD860_K2_E5                           (0xf<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1141_RESERVEDFIELD860_K2_E5_SHIFT                     2
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1142_K2_E5                                              0x006a8cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1142_RESERVEDFIELD861_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1142_RESERVEDFIELD861_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1142_RESERVEDFIELD862_K2_E5                           (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1142_RESERVEDFIELD862_K2_E5_SHIFT                     4
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1142_RESERVEDFIELD863_K2_E5                           (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1142_RESERVEDFIELD863_K2_E5_SHIFT                     6
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1143_K2_E5                                              0x006a98UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1144_K2_E5                                              0x006a9cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1145_K2_E5                                              0x006aa0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1146_K2_E5                                              0x006aa4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1147_K2_E5                                              0x006aacUL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1148_K2_E5                                              0x006ab0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1148_RESERVEDFIELD869_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1148_RESERVEDFIELD869_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1148_RESERVEDFIELD870_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1148_RESERVEDFIELD870_K2_E5_SHIFT                     1
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1149_K2_E5                                              0x006ab8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1149_RESERVEDFIELD871_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1149_RESERVEDFIELD871_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1149_RESERVEDFIELD872_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1149_RESERVEDFIELD872_K2_E5_SHIFT                     1
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1150_K2_E5                                              0x006abcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1150_RESERVEDFIELD873_K2_E5                           (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1150_RESERVEDFIELD873_K2_E5_SHIFT                     6
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1151_K2_E5                                              0x006ae0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1152_K2_E5                                              0x006ae4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1153_K2_E5                                               0x006c00UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1154_K2_E5                                               0x006c04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1154_RESERVEDFIELD875_K2_E5                            (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1154_RESERVEDFIELD875_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1155_K2_E5                                               0x006c08UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1156_K2_E5                                               0x006c0cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1156_RESERVEDFIELD877_K2_E5                            (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1156_RESERVEDFIELD877_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1157_K2_E5                                               0x006c10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1157_RESERVEDFIELD878_K2_E5                            (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1157_RESERVEDFIELD878_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1158_K2_E5                                               0x006c14UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1159_K2_E5                                               0x006c20UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1160_K2_E5                                               0x006c24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1160_RESERVEDFIELD881_K2_E5                            (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1160_RESERVEDFIELD881_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1161_K2_E5                                               0x006c30UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1162_K2_E5                                               0x006c34UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1162_RESERVEDFIELD883_K2_E5                            (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1162_RESERVEDFIELD883_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1163_K2_E5                                               0x006c40UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1164_K2_E5                                               0x006c44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1164_RESERVEDFIELD885_K2_E5                            (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1164_RESERVEDFIELD885_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1165_K2_E5                                               0x006c4cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1166_K2_E5                                               0x006c50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1166_RESERVEDFIELD887_K2_E5                            (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1166_RESERVEDFIELD887_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1167_K2_E5                                               0x006c58UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1168_K2_E5                                               0x006c5cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1168_RESERVEDFIELD889_K2_E5                            (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1168_RESERVEDFIELD889_K2_E5_SHIFT                      0
+#define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1169_K2_E5                                               0x006c80UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LEQ_RXCLK_RESERVEDREGISTER1170_K2_E5                                               0x006c84UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DRV_REFCLK_AFE_PD_CTRL0_K2_E5                                                      0x006e00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_AFE_PD_CTRL0_PD_TXDRV_K2_E5                                           (0xf<<0) // power down TX driver
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_AFE_PD_CTRL0_PD_TXDRV_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1171_K2_E5                                              0x006e04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1171_RESERVEDFIELD890_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1171_RESERVEDFIELD890_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DRV_REFCLK_AFE_CTRL0_K2_E5                                                         0x006e08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_AFE_CTRL0_TXDRV_LP_IDLE_K2_E5                                         (0x3<<0) // When HIGH, TX driver goes into a low power IDLE model. In this mode, the output termination is not guaranteed to be 50 Ohm closer to 200 Ohm
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_AFE_CTRL0_TXDRV_LP_IDLE_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1172_K2_E5                                              0x006e0cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1173_K2_E5                                              0x006e10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1173_RESERVEDFIELD892_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1173_RESERVEDFIELD892_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1173_RESERVEDFIELD893_K2_E5                           (0x1f<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1173_RESERVEDFIELD893_K2_E5_SHIFT                     1
+#define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1174_K2_E5                                              0x006e14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1174_RESERVEDFIELD894_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1174_RESERVEDFIELD894_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1175_K2_E5                                              0x006e18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1175_RESERVEDFIELD895_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1175_RESERVEDFIELD895_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1175_RESERVEDFIELD896_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1175_RESERVEDFIELD896_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1175_RESERVEDFIELD897_K2_E5                           (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1175_RESERVEDFIELD897_K2_E5_SHIFT                     2
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1175_RESERVEDFIELD898_K2_E5                           (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1175_RESERVEDFIELD898_K2_E5_SHIFT                     5
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1175_RESERVEDFIELD899_K2_E5                           (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1175_RESERVEDFIELD899_K2_E5_SHIFT                     6
+#define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1176_K2_E5                                              0x006e20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1176_RESERVEDFIELD900_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1176_RESERVEDFIELD900_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1176_RESERVEDFIELD901_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1176_RESERVEDFIELD901_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1176_RESERVEDFIELD902_K2_E5                           (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1176_RESERVEDFIELD902_K2_E5_SHIFT                     2
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1176_RESERVEDFIELD903_K2_E5                           (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1176_RESERVEDFIELD903_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1177_K2_E5                                              0x006e24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1177_RESERVEDFIELD904_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1177_RESERVEDFIELD904_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1177_RESERVEDFIELD905_K2_E5                           (0x1f<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1177_RESERVEDFIELD905_K2_E5_SHIFT                     3
+#define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1178_K2_E5                                              0x006e28UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1178_RESERVEDFIELD906_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1178_RESERVEDFIELD906_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1178_RESERVEDFIELD907_K2_E5                           (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1178_RESERVEDFIELD907_K2_E5_SHIFT                     3
+#define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1179_K2_E5                                              0x006e2cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1179_RESERVEDFIELD908_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1179_RESERVEDFIELD908_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1179_RESERVEDFIELD909_K2_E5                           (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1179_RESERVEDFIELD909_K2_E5_SHIFT                     5
+#define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1180_K2_E5                                              0x006e30UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1180_RESERVEDFIELD910_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1180_RESERVEDFIELD910_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1180_RESERVEDFIELD911_K2_E5                           (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1180_RESERVEDFIELD911_K2_E5_SHIFT                     3
+#define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1181_K2_E5                                              0x006e34UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1181_RESERVEDFIELD912_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1181_RESERVEDFIELD912_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1181_RESERVEDFIELD913_K2_E5                           (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1181_RESERVEDFIELD913_K2_E5_SHIFT                     5
+#define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL0_K2_E5                                                        0x006e40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL0_REQ_K2_E5                                                  (0x1<<0) // Set to 1 to apply the coefficient settings, and hold until ack is 1.  Set to 0 once ack is 1.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL0_REQ_K2_E5_SHIFT                                            0
+#define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_STATUS0_K2_E5                                                      0x006e44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_STATUS0_ACK_K2_E5                                                (0x1<<0) // Set to 1 by firmware when updates are complete. Cleared when req = 0
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_STATUS0_ACK_K2_E5_SHIFT                                          0
+#define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL1_K2_E5                                                        0x006e48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL1_TXEQ_C1_K2_E5                                              (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL1_TXEQ_C1_K2_E5_SHIFT                                        0
+#define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1182_K2_E5                                              0x006e4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1182_RESERVEDFIELD914_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1182_RESERVEDFIELD914_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL3_K2_E5                                                        0x006e50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL3_TXEQ_CM1_K2_E5                                             (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL3_TXEQ_CM1_K2_E5_SHIFT                                       0
+#define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1183_K2_E5                                              0x006e54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1183_RESERVEDFIELD915_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1183_RESERVEDFIELD915_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1183_RESERVEDFIELD916_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1183_RESERVEDFIELD916_K2_E5_SHIFT                     1
+#define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL5_K2_E5                                                        0x006e58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL5_DRV_SWING_K2_E5                                            (0xf<<0) // Thermometer coded control to adjust the delay between data and clock for the final 2to1 mux. Setting 00000 min delay of clock path and 11111 max delay of clock path.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL5_DRV_SWING_K2_E5_SHIFT                                      0
+#define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1184_K2_E5                                              0x006e5cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1184_RESERVEDFIELD917_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1184_RESERVEDFIELD917_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1184_RESERVEDFIELD918_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1184_RESERVEDFIELD918_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1184_RESERVEDFIELD919_K2_E5                           (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1184_RESERVEDFIELD919_K2_E5_SHIFT                     2
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1184_RESERVEDFIELD920_K2_E5                           (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1184_RESERVEDFIELD920_K2_E5_SHIFT                     5
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1184_RESERVEDFIELD921_K2_E5                           (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1184_RESERVEDFIELD921_K2_E5_SHIFT                     6
+#define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1185_K2_E5                                              0x006e60UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1185_RESERVEDFIELD922_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1185_RESERVEDFIELD922_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1185_RESERVEDFIELD923_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1185_RESERVEDFIELD923_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1185_RESERVEDFIELD924_K2_E5                           (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1185_RESERVEDFIELD924_K2_E5_SHIFT                     2
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1185_RESERVEDFIELD925_K2_E5                           (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1185_RESERVEDFIELD925_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1186_K2_E5                                              0x006e64UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1186_RESERVEDFIELD926_K2_E5                           (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1186_RESERVEDFIELD926_K2_E5_SHIFT                     3
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1186_RESERVEDFIELD927_K2_E5                           (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1186_RESERVEDFIELD927_K2_E5_SHIFT                     5
+#define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1187_K2_E5                                              0x006e6cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1187_RESERVEDFIELD928_K2_E5                           (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1187_RESERVEDFIELD928_K2_E5_SHIFT                     3
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1187_RESERVEDFIELD929_K2_E5                           (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1187_RESERVEDFIELD929_K2_E5_SHIFT                     5
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1188_K2_E5                                              0x007000UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1188_RESERVEDFIELD930_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1188_RESERVEDFIELD930_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1189_K2_E5                                              0x007004UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1189_RESERVEDFIELD931_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1189_RESERVEDFIELD931_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1190_K2_E5                                              0x007008UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1190_RESERVEDFIELD932_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1190_RESERVEDFIELD932_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1190_RESERVEDFIELD933_K2_E5                           (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1190_RESERVEDFIELD933_K2_E5_SHIFT                     2
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1191_K2_E5                                              0x00700cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1191_RESERVEDFIELD934_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1191_RESERVEDFIELD934_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1191_RESERVEDFIELD935_K2_E5                           (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1191_RESERVEDFIELD935_K2_E5_SHIFT                     3
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1192_K2_E5                                              0x007010UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1192_RESERVEDFIELD936_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1192_RESERVEDFIELD936_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1193_K2_E5                                              0x007018UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1193_RESERVEDFIELD937_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1193_RESERVEDFIELD937_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1194_K2_E5                                              0x007028UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1194_RESERVEDFIELD938_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1194_RESERVEDFIELD938_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1194_RESERVEDFIELD939_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1194_RESERVEDFIELD939_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1194_RESERVEDFIELD940_K2_E5                           (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1194_RESERVEDFIELD940_K2_E5_SHIFT                     2
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1195_K2_E5                                              0x007030UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1195_RESERVEDFIELD941_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1195_RESERVEDFIELD941_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1195_RESERVEDFIELD942_K2_E5                           (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1195_RESERVEDFIELD942_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1196_K2_E5                                              0x007038UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1196_RESERVEDFIELD943_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1196_RESERVEDFIELD943_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1196_RESERVEDFIELD944_K2_E5                           (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1196_RESERVEDFIELD944_K2_E5_SHIFT                     4
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1196_RESERVEDFIELD945_K2_E5                           (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1196_RESERVEDFIELD945_K2_E5_SHIFT                     6
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1197_K2_E5                                              0x007040UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1197_RESERVEDFIELD946_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1197_RESERVEDFIELD946_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1197_RESERVEDFIELD947_K2_E5                           (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1197_RESERVEDFIELD947_K2_E5_SHIFT                     4
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1197_RESERVEDFIELD948_K2_E5                           (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1197_RESERVEDFIELD948_K2_E5_SHIFT                     6
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1198_K2_E5                                              0x007048UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1198_RESERVEDFIELD949_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1198_RESERVEDFIELD949_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1198_RESERVEDFIELD950_K2_E5                           (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1198_RESERVEDFIELD950_K2_E5_SHIFT                     1
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1199_K2_E5                                              0x007050UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1200_K2_E5                                              0x007058UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1200_RESERVEDFIELD952_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1200_RESERVEDFIELD952_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1200_RESERVEDFIELD953_K2_E5                           (0xf<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1200_RESERVEDFIELD953_K2_E5_SHIFT                     1
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1201_K2_E5                                              0x007060UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1202_K2_E5                                              0x007064UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1202_RESERVEDFIELD955_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1202_RESERVEDFIELD955_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1203_K2_E5                                              0x00706cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1203_RESERVEDFIELD956_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1203_RESERVEDFIELD956_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1203_RESERVEDFIELD957_K2_E5                           (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1203_RESERVEDFIELD957_K2_E5_SHIFT                     7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_CTRL0_K2_E5                                                         0x007080UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_CTRL0_REQ_K2_E5                                                   (0x1<<0) // Write 1 to request a command CMD execution.  It should be held at 1 until fsm_status0.ack is 1, and then it should be set back to 0.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_CTRL0_REQ_K2_E5_SHIFT                                             0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_CTRL0_CMD_K2_E5                                                   (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_CTRL0_CMD_K2_E5_SHIFT                                             1
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_CTRL0_RESERVEDFIELD958_K2_E5                                      (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_CTRL0_RESERVEDFIELD958_K2_E5_SHIFT                                6
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL_K2_E5                                     (0x1<<7) // Set it to 1 when changing DFE tap values
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL_K2_E5_SHIFT                               7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1204_K2_E5                                              0x007084UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1204_RESERVEDFIELD959_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1204_RESERVEDFIELD959_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1204_RESERVEDFIELD960_K2_E5                           (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1204_RESERVEDFIELD960_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1205_K2_E5                                              0x007088UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1206_K2_E5                                              0x00708cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1206_RESERVEDFIELD962_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1206_RESERVEDFIELD962_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1207_K2_E5                                              0x007090UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1208_K2_E5                                              0x007094UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1208_RESERVEDFIELD964_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1208_RESERVEDFIELD964_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1209_K2_E5                                              0x007098UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1210_K2_E5                                              0x00709cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1210_RESERVEDFIELD966_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1210_RESERVEDFIELD966_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_STATUS0_K2_E5                                                       0x0070a0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_STATUS0_ACK_K2_E5                                                 (0x1<<0) // Acknowledge from DFE after command execution. Will be set to 1 after a command is completed, and will clear to 0 after fsm_status0.req is cleared
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_STATUS0_ACK_K2_E5_SHIFT                                           0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD967_K2_E5                                    (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD967_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD968_K2_E5                                    (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD968_K2_E5_SHIFT                              2
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD969_K2_E5                                    (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD969_K2_E5_SHIFT                              3
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_K2_E5                                                         0x0070a8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN_K2_E5                                         (0x1<<0) // Enables updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN_K2_E5                                         (0x1<<1) // Enables updating Tap 1 Even 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN_K2_E5_SHIFT                                   1
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN_K2_E5                                          (0x1<<2) // Enables updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN_K2_E5_SHIFT                                    2
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN_K2_E5                                          (0x1<<3) // Enables updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN_K2_E5_SHIFT                                    3
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP2_EN_K2_E5                                               (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP2_EN_K2_E5_SHIFT                                         4
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP3_EN_K2_E5                                               (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP3_EN_K2_E5_SHIFT                                         5
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP4_EN_K2_E5                                               (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP4_EN_K2_E5_SHIFT                                         6
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP5_EN_K2_E5                                               (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP5_EN_K2_E5_SHIFT                                         7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL0_K2_E5                                               0x0070acUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_K2_E5                                  (0x1f<<0) // Starting value for Tap 1 Even 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_K2_E5_SHIFT                            0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5                         (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5_SHIFT                   7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL1_K2_E5                                               0x0070b0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_K2_E5                                  (0x1f<<0) // Starting value for Tap 1 Even 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_K2_E5_SHIFT                            0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5                         (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5_SHIFT                   7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL2_K2_E5                                               0x0070b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_K2_E5                                   (0x1f<<0) // Starting value for Tap 1 Odd 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5                          (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL3_K2_E5                                               0x0070b8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_K2_E5                                   (0x1f<<0) // Starting value for Tap 1 Odd 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5                          (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL4_K2_E5                                               0x0070bcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_K2_E5                                        (0xf<<0) // Starting value for Tap 2 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY_K2_E5                               (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY_K2_E5_SHIFT                         7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL5_K2_E5                                               0x0070c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_K2_E5                                        (0x7<<0) // Starting value for Tap 3 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY_K2_E5                               (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY_K2_E5_SHIFT                         7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL6_K2_E5                                               0x0070c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_K2_E5                                        (0x7<<0) // Starting value for Tap 4 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY_K2_E5                               (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY_K2_E5_SHIFT                         7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL7_K2_E5                                               0x0070c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_K2_E5                                        (0x7<<0) // Starting value for Tap 5 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY_K2_E5                               (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY_K2_E5_SHIFT                         7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_K2_E5                                                0x0070ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_K2_E5                                   (0x1f<<0) // Loading value for Tap 1 Even 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5                          (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_K2_E5                                                0x0070d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_K2_E5                                   (0x1f<<0) // Loading value for Tap 1 Even 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5                          (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_K2_E5                                                0x0070d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_K2_E5                                    (0x1f<<0) // Loading value for Tap 1 Odd 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5                           (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5_SHIFT                     7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_K2_E5                                                0x0070d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_K2_E5                                    (0x1f<<0) // Loading value for Tap 1 Odd 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5                           (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5_SHIFT                     7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_K2_E5                                                0x0070dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_K2_E5                                         (0xf<<0) // Loading value for Tap 2 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_K2_E5                                (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_K2_E5                                                0x0070e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_K2_E5                                         (0x7<<0) // Loading value for Tap 3 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_K2_E5                                (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_K2_E5                                                0x0070e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_K2_E5                                         (0x7<<0) // Loading value for Tap 4 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_K2_E5                                (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_K2_E5                                                0x0070e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_K2_E5                                         (0x7<<0) // Loading value for Tap 5 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_K2_E5                                (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS0_K2_E5                                                   0x0070ecUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_K2_E5                                      (0x1f<<0) // binary value for Tap 1 Even 0 Path for Tap Adaptations
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_K2_E5_SHIFT                                0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_K2_E5                             (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_K2_E5_SHIFT                       7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS1_K2_E5                                                   0x0070f0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_K2_E5                                      (0x1f<<0) // binary  value for Tap 1 Even 1 Path for Tap Adaptations
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_K2_E5_SHIFT                                0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_K2_E5                             (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_K2_E5_SHIFT                       7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS2_K2_E5                                                   0x0070f4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_K2_E5                                       (0x1f<<0) // binary  value for Tap 1 Odd 0 Path for Tap Adaptations
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_K2_E5                              (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_K2_E5_SHIFT                        7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS3_K2_E5                                                   0x0070f8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_K2_E5                                       (0x1f<<0) // binary  value for Tap 1 Odd 1 Path for Tap Adaptations
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_K2_E5                              (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_K2_E5_SHIFT                        7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS4_K2_E5                                                   0x0070fcUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_K2_E5                                            (0xf<<0) // binary  value for Tap 2 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY_K2_E5                                   (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS5_K2_E5                                                   0x007100UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_K2_E5                                            (0x7<<0) // binary  value for Tap 3 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY_K2_E5                                   (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS6_K2_E5                                                   0x007104UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_K2_E5                                            (0x7<<0) // binary  value for Tap 4 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY_K2_E5                                   (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS7_K2_E5                                                   0x007108UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_K2_E5                                            (0x7<<0) // binary  value for Tap 5 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY_K2_E5                                   (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_K2_E5                                              0x007140UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD970_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD970_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD971_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD971_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD972_K2_E5                           (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD972_K2_E5_SHIFT                     2
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD973_K2_E5                           (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD973_K2_E5_SHIFT                     3
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD974_K2_E5                           (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD974_K2_E5_SHIFT                     4
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD975_K2_E5                           (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD975_K2_E5_SHIFT                     5
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD976_K2_E5                           (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD976_K2_E5_SHIFT                     6
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD977_K2_E5                           (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD977_K2_E5_SHIFT                     7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1212_K2_E5                                              0x007144UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1212_RESERVEDFIELD978_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1212_RESERVEDFIELD978_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1213_K2_E5                                              0x007148UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1213_RESERVEDFIELD979_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1213_RESERVEDFIELD979_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1214_K2_E5                                              0x00714cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1214_RESERVEDFIELD980_K2_E5                           (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1214_RESERVEDFIELD980_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1215_K2_E5                                              0x007150UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1215_RESERVEDFIELD981_K2_E5                           (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1215_RESERVEDFIELD981_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1216_K2_E5                                              0x007154UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1216_RESERVEDFIELD982_K2_E5                           (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1216_RESERVEDFIELD982_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1217_K2_E5                                              0x007158UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1217_RESERVEDFIELD983_K2_E5                           (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1217_RESERVEDFIELD983_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1218_K2_E5                                              0x00715cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1218_RESERVEDFIELD984_K2_E5                           (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1218_RESERVEDFIELD984_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1219_K2_E5                                              0x007160UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1219_RESERVEDFIELD985_K2_E5                           (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1219_RESERVEDFIELD985_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1220_K2_E5                                              0x007164UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1220_RESERVEDFIELD986_K2_E5                           (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1220_RESERVEDFIELD986_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1221_K2_E5                                              0x007168UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1221_RESERVEDFIELD987_K2_E5                           (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1221_RESERVEDFIELD987_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1222_K2_E5                                              0x00716cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1222_RESERVEDFIELD988_K2_E5                           (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1222_RESERVEDFIELD988_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1223_K2_E5                                              0x007170UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1223_RESERVEDFIELD989_K2_E5                           (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1223_RESERVEDFIELD989_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1224_K2_E5                                              0x007174UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1224_RESERVEDFIELD990_K2_E5                           (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1224_RESERVEDFIELD990_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1225_K2_E5                                              0x007178UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1225_RESERVEDFIELD991_K2_E5                           (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1225_RESERVEDFIELD991_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1226_K2_E5                                              0x00717cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1226_RESERVEDFIELD992_K2_E5                           (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1226_RESERVEDFIELD992_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1227_K2_E5                                              0x007180UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1227_RESERVEDFIELD993_K2_E5                           (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1227_RESERVEDFIELD993_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1228_K2_E5                                              0x007184UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1228_RESERVEDFIELD994_K2_E5                           (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1228_RESERVEDFIELD994_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1229_K2_E5                                              0x007188UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1229_RESERVEDFIELD995_K2_E5                           (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1229_RESERVEDFIELD995_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_K2_E5                                              0x00718cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD996_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD996_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD997_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD997_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD998_K2_E5                           (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD998_K2_E5_SHIFT                     2
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD999_K2_E5                           (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD999_K2_E5_SHIFT                     3
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD1000_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD1000_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD1001_K2_E5                          (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD1001_K2_E5_SHIFT                    5
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD1002_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD1002_K2_E5_SHIFT                    6
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD1003_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD1003_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1231_K2_E5                                              0x007190UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1231_RESERVEDFIELD1004_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1231_RESERVEDFIELD1004_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1231_RESERVEDFIELD1005_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1231_RESERVEDFIELD1005_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1231_RESERVEDFIELD1006_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1231_RESERVEDFIELD1006_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_K2_E5                                              0x007194UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1007_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1007_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1008_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1008_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1009_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1009_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1010_K2_E5                          (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1010_K2_E5_SHIFT                    3
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1011_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1011_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1012_K2_E5                          (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1012_K2_E5_SHIFT                    5
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1013_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1013_K2_E5_SHIFT                    6
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1014_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1014_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1233_K2_E5                                               0x007200UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1234_K2_E5                                               0x007204UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1234_RESERVEDFIELD1016_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1234_RESERVEDFIELD1016_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1235_K2_E5                                               0x007208UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1235_RESERVEDFIELD1017_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1235_RESERVEDFIELD1017_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1235_RESERVEDFIELD1018_K2_E5                           (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1235_RESERVEDFIELD1018_K2_E5_SHIFT                     5
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1235_RESERVEDFIELD1019_K2_E5                           (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1235_RESERVEDFIELD1019_K2_E5_SHIFT                     6
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1236_K2_E5                                               0x007218UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1236_RESERVEDFIELD1020_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1236_RESERVEDFIELD1020_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1236_RESERVEDFIELD1021_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1236_RESERVEDFIELD1021_K2_E5_SHIFT                     1
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1237_K2_E5                                               0x00721cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1238_K2_E5                                               0x007220UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1238_RESERVEDFIELD1023_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1238_RESERVEDFIELD1023_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1239_K2_E5                                               0x007224UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1239_RESERVEDFIELD1024_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1239_RESERVEDFIELD1024_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1239_RESERVEDFIELD1025_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1239_RESERVEDFIELD1025_K2_E5_SHIFT                     1
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1240_K2_E5                                               0x007228UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1241_K2_E5                                               0x00722cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1241_RESERVEDFIELD1027_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1241_RESERVEDFIELD1027_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1242_K2_E5                                               0x007230UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1243_K2_E5                                               0x007234UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1243_RESERVEDFIELD1029_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1243_RESERVEDFIELD1029_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1244_K2_E5                                               0x007240UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1244_RESERVEDFIELD1030_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1244_RESERVEDFIELD1030_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1244_RESERVEDFIELD1031_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1244_RESERVEDFIELD1031_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1244_RESERVEDFIELD1032_K2_E5                           (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1244_RESERVEDFIELD1032_K2_E5_SHIFT                     2
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1245_K2_E5                                               0x007244UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1245_RESERVEDFIELD1033_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1245_RESERVEDFIELD1033_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1246_K2_E5                                               0x007248UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1247_K2_E5                                               0x007258UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1248_K2_E5                                               0x00725cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1248_RESERVEDFIELD1036_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1248_RESERVEDFIELD1036_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1249_K2_E5                                               0x007260UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1250_K2_E5                                               0x007264UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1250_RESERVEDFIELD1038_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1250_RESERVEDFIELD1038_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1251_K2_E5                                               0x007268UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1252_K2_E5                                               0x00726cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1253_K2_E5                                               0x007270UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1254_K2_E5                                               0x007274UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1255_K2_E5                                               0x007278UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1256_K2_E5                                               0x007290UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1256_RESERVEDFIELD1044_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1256_RESERVEDFIELD1044_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1256_RESERVEDFIELD1045_K2_E5                           (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1256_RESERVEDFIELD1045_K2_E5_SHIFT                     2
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1256_RESERVEDFIELD1046_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1256_RESERVEDFIELD1046_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1257_K2_E5                                               0x007294UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1257_RESERVEDFIELD1047_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1257_RESERVEDFIELD1047_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1257_RESERVEDFIELD1048_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1257_RESERVEDFIELD1048_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1258_K2_E5                                               0x007298UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1258_RESERVEDFIELD1049_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1258_RESERVEDFIELD1049_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1258_RESERVEDFIELD1050_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1258_RESERVEDFIELD1050_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1259_K2_E5                                               0x00729cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1259_RESERVEDFIELD1051_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1259_RESERVEDFIELD1051_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1260_K2_E5                                               0x0072a0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1261_K2_E5                                               0x0072a4UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1262_K2_E5                                               0x0072a8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1263_K2_E5                                               0x0072acUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1263_RESERVEDFIELD1055_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1263_RESERVEDFIELD1055_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1264_K2_E5                                               0x0072b0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1265_K2_E5                                               0x0072b4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1265_RESERVEDFIELD1057_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1265_RESERVEDFIELD1057_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1266_K2_E5                                               0x0072b8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1267_K2_E5                                               0x0072bcUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1267_RESERVEDFIELD1059_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1267_RESERVEDFIELD1059_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1268_K2_E5                                               0x0072c0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1269_K2_E5                                               0x0072c4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1269_RESERVEDFIELD1061_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1269_RESERVEDFIELD1061_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1270_K2_E5                                               0x0072c8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1271_K2_E5                                               0x0072ccUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1271_RESERVEDFIELD1063_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1271_RESERVEDFIELD1063_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1272_K2_E5                                               0x0072d0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1273_K2_E5                                               0x0072d4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1273_RESERVEDFIELD1065_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1273_RESERVEDFIELD1065_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1274_K2_E5                                               0x0072d8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1275_K2_E5                                               0x0072dcUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1275_RESERVEDFIELD1067_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1275_RESERVEDFIELD1067_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1276_K2_E5                                               0x0072e0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1277_K2_E5                                               0x0072e4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1277_RESERVEDFIELD1069_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1277_RESERVEDFIELD1069_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1278_K2_E5                                               0x007300UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1279_K2_E5                                               0x007304UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1280_K2_E5                                               0x007308UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1281_K2_E5                                               0x00730cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1281_RESERVEDFIELD1073_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1281_RESERVEDFIELD1073_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1282_K2_E5                                               0x007310UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1283_K2_E5                                               0x007314UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1283_RESERVEDFIELD1075_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1283_RESERVEDFIELD1075_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1284_K2_E5                                               0x007318UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1285_K2_E5                                               0x00731cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1285_RESERVEDFIELD1077_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1285_RESERVEDFIELD1077_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1286_K2_E5                                               0x007320UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1287_K2_E5                                               0x007324UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1287_RESERVEDFIELD1079_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1287_RESERVEDFIELD1079_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1288_K2_E5                                               0x007328UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1289_K2_E5                                               0x00732cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1289_RESERVEDFIELD1081_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1289_RESERVEDFIELD1081_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1290_K2_E5                                               0x007330UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1291_K2_E5                                               0x007334UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1291_RESERVEDFIELD1083_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1291_RESERVEDFIELD1083_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1292_K2_E5                                               0x007338UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1293_K2_E5                                               0x00733cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1293_RESERVEDFIELD1085_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1293_RESERVEDFIELD1085_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1294_K2_E5                                               0x007340UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1295_K2_E5                                               0x007344UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1295_RESERVEDFIELD1087_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1295_RESERVEDFIELD1087_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1296_K2_E5                                               0x007358UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1296_RESERVEDFIELD1088_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1296_RESERVEDFIELD1088_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1296_RESERVEDFIELD1089_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1296_RESERVEDFIELD1089_K2_E5_SHIFT                     1
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1297_K2_E5                                               0x00735cUL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1298_K2_E5                                               0x007360UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1299_K2_E5                                               0x007380UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1299_RESERVEDFIELD1092_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1299_RESERVEDFIELD1092_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1300_K2_E5                                               0x007384UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1301_K2_E5                                               0x007388UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1302_K2_E5                                               0x00738cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1303_K2_E5                                               0x007390UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1304_K2_E5                                               0x007394UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1305_K2_E5                                               0x007398UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1306_K2_E5                                               0x00739cUL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1307_K2_E5                                               0x0073a0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1308_K2_E5                                               0x0073a4UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1309_K2_E5                                               0x0073a8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1310_K2_E5                                               0x0073acUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1310_RESERVEDFIELD1103_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1310_RESERVEDFIELD1103_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_AFE_CAL_CTRL_K2_E5                                                      0x007400UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_AFE_CAL_CTRL_RXLOS_OFFSETCAL_K2_E5                                    (0x1<<0) // Enables analog LOS offset calibration circuits.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_AFE_CAL_CTRL_RXLOS_OFFSETCAL_K2_E5_SHIFT                              0
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1311_K2_E5                                              0x007404UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1311_RESERVEDFIELD1104_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1311_RESERVEDFIELD1104_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1312_K2_E5                                              0x007408UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1312_RESERVEDFIELD1105_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1312_RESERVEDFIELD1105_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_CTRL0_K2_E5                                                  0x00740cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_CTRL0_EN_K2_E5                                             (0x1<<0) // Enables the run-length detection digital LOS filter.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_CTRL0_EN_K2_E5_SHIFT                                       0
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_CTRL1_K2_E5                                                  0x007410UL //Access:RW   DataWidth:0x8    // Value of run-length which will trigger an LOS condition.
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_STATUS0_K2_E5                                                0x007414UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_K2_E5                                       (0x1<<0) // Indicates that the run-length filter is currently exceeding the specified run-length threshold.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY_K2_E5                                (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the specified run-length threshold.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY_K2_E5_SHIFT                          1
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL0_K2_E5                                                      0x007440UL //Access:RW   DataWidth:0x8    // Digital Rx LOS glitch filter assertion threshold.  Determines the number of consecutive clk_i clock cycles that the analog  LOS must remain a logic 1 before the output of the filter will assert.  Can be disabled by writing a value of 0x00.
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL1_K2_E5                                                      0x007444UL //Access:RW   DataWidth:0x8    // Digital Rx LOS glitch filter assertion threshold.  Determines the number of consecutive clk_i clock cycles that the analog  LOS must remain a logic 1 before the output of the filter will assert.  Can be disabled by writing a value of 0x0000.
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL2_K2_E5                                                      0x007448UL //Access:RW   DataWidth:0x8    // Digital Rx LOS glitch filter assertion threshold.  Determines the number of consecutive clk_i clock cycles that the raw analog  LOS must remain a logic 1 before the output of the filter will assert.  Can be disabled by writing a value of 0x000000.
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL3_K2_E5                                                      0x00744cUL //Access:RW   DataWidth:0x8    // Same as above.
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL4_K2_E5                                                      0x007450UL //Access:RW   DataWidth:0x8    // Same as above.
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL5_K2_E5                                                      0x007454UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL5_DEASSERT_THRESHOLD_25_24_K2_E5                           (0x3<<0) // Same as above.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL5_DEASSERT_THRESHOLD_25_24_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL6_K2_E5                                                      0x007458UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL6_EN_K2_E5                                                 (0x1<<0) // Enables the digital deglitching filter.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL6_EN_K2_E5_SHIFT                                           0
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1313_K2_E5                                              0x007480UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1313_RESERVEDFIELD1106_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1313_RESERVEDFIELD1106_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1314_K2_E5                                              0x007484UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1315_K2_E5                                              0x007488UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1316_K2_E5                                              0x00748cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1317_K2_E5                                              0x007490UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1317_RESERVEDFIELD1110_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1317_RESERVEDFIELD1110_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_OVERRIDE_CTRL0_K2_E5                                                    0x0074c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN_K2_E5                                         (0x1<<0) // Override enable for the LOS output of the digital filtering logic.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE_K2_E5                                      (0x1<<4) // Override value for the LOS output of the digital filtering logic.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE_K2_E5_SHIFT                                4
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1318_K2_E5                                              0x0074c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1318_RESERVEDFIELD1111_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1318_RESERVEDFIELD1111_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1318_RESERVEDFIELD1112_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1318_RESERVEDFIELD1112_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1319_K2_E5                                              0x0074c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1319_RESERVEDFIELD1113_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1319_RESERVEDFIELD1113_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1319_RESERVEDFIELD1114_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1319_RESERVEDFIELD1114_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1320_K2_E5                                              0x0074ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1320_RESERVEDFIELD1115_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1320_RESERVEDFIELD1115_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1320_RESERVEDFIELD1116_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1320_RESERVEDFIELD1116_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1321_K2_E5                                              0x007500UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1321_RESERVEDFIELD1117_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1321_RESERVEDFIELD1117_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1321_RESERVEDFIELD1118_K2_E5                          (0x7<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1321_RESERVEDFIELD1118_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1321_RESERVEDFIELD1119_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1321_RESERVEDFIELD1119_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1322_K2_E5                                              0x007504UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1322_RESERVEDFIELD1120_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1322_RESERVEDFIELD1120_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1322_RESERVEDFIELD1121_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1322_RESERVEDFIELD1121_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1322_RESERVEDFIELD1122_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1322_RESERVEDFIELD1122_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1322_RESERVEDFIELD1123_K2_E5                          (0xf<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1322_RESERVEDFIELD1123_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1323_K2_E5                                              0x007508UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1324_K2_E5                                              0x00750cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1325_K2_E5                                              0x007518UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1325_RESERVEDFIELD1126_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1325_RESERVEDFIELD1126_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1326_K2_E5                                              0x007544UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1326_RESERVEDFIELD1127_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1326_RESERVEDFIELD1127_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1326_RESERVEDFIELD1128_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1326_RESERVEDFIELD1128_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1327_K2_E5                                              0x007564UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1327_RESERVEDFIELD1129_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1327_RESERVEDFIELD1129_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1328_K2_E5                                              0x007580UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1328_RESERVEDFIELD1130_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1328_RESERVEDFIELD1130_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1329_K2_E5                                              0x0075c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1329_RESERVEDFIELD1131_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1329_RESERVEDFIELD1131_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1329_RESERVEDFIELD1132_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1329_RESERVEDFIELD1132_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_K2_E5                                                           0x0075c4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_LOS_READY_K2_E5                                               (0x1<<0) // Indicates that digital and analog Rx LOS blocks are in LOS mode.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_LOS_READY_K2_E5_SHIFT                                         0
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_RESERVEDFIELD1133_K2_E5                                       (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_RESERVEDFIELD1133_K2_E5_SHIFT                                 1
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_LOS_K2_E5                                                     (0x1<<2) // The filtered LOS signal value.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_LOS_K2_E5_SHIFT                                               2
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_LOS_RAW_K2_E5                                                 (0x1<<3) // The unfiltered LOS signal value.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_LOS_RAW_K2_E5_SHIFT                                           3
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_LOS_NO_EII_K2_E5                                              (0x1<<4) // The filtered LOS signal value before EII override logic.
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_LOS_NO_EII_K2_E5_SHIFT                                        4
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_RESERVEDFIELD1134_K2_E5                                       (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_RESERVEDFIELD1134_K2_E5_SHIFT                                 5
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1330_K2_E5                                                  0x007600UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1330_RESERVEDFIELD1135_K2_E5                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1330_RESERVEDFIELD1135_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1331_K2_E5                                                  0x007604UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1331_RESERVEDFIELD1136_K2_E5                              (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1331_RESERVEDFIELD1136_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1332_K2_E5                                                  0x007608UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1333_K2_E5                                                  0x00760cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1333_RESERVEDFIELD1138_K2_E5                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1333_RESERVEDFIELD1138_K2_E5_SHIFT                        0
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1333_RESERVEDFIELD1139_K2_E5                              (0xf<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1333_RESERVEDFIELD1139_K2_E5_SHIFT                        1
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1334_K2_E5                                                  0x007640UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1335_K2_E5                                                  0x007644UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1335_RESERVEDFIELD1141_K2_E5                              (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1335_RESERVEDFIELD1141_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1336_K2_E5                                                  0x007648UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1337_K2_E5                                                  0x00764cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1337_RESERVEDFIELD1143_K2_E5                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1337_RESERVEDFIELD1143_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1338_K2_E5                                                  0x007680UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1338_RESERVEDFIELD1144_K2_E5                              (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1338_RESERVEDFIELD1144_K2_E5_SHIFT                        0
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1338_RESERVEDFIELD1145_K2_E5                              (0xf<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1338_RESERVEDFIELD1145_K2_E5_SHIFT                        2
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1339_K2_E5                                                  0x007684UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1340_K2_E5                                                  0x007688UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1340_RESERVEDFIELD1147_K2_E5                              (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1340_RESERVEDFIELD1147_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1341_K2_E5                                                  0x00768cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1342_K2_E5                                                  0x007690UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1342_RESERVEDFIELD1149_K2_E5                              (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1342_RESERVEDFIELD1149_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1343_K2_E5                                                  0x007694UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1344_K2_E5                                                  0x007698UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1344_RESERVEDFIELD1151_K2_E5                              (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1344_RESERVEDFIELD1151_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1345_K2_E5                                                  0x0076c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1345_RESERVEDFIELD1152_K2_E5                              (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1345_RESERVEDFIELD1152_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1346_K2_E5                                                  0x0076c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1346_RESERVEDFIELD1153_K2_E5                              (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1346_RESERVEDFIELD1153_K2_E5_SHIFT                        0
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1346_RESERVEDFIELD1154_K2_E5                              (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1346_RESERVEDFIELD1154_K2_E5_SHIFT                        4
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1347_K2_E5                                                  0x0076c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1347_RESERVEDFIELD1155_K2_E5                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1347_RESERVEDFIELD1155_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1348_K2_E5                                                  0x007700UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1348_RESERVEDFIELD1156_K2_E5                              (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1348_RESERVEDFIELD1156_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1349_K2_E5                                                  0x007704UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1350_K2_E5                                                  0x007708UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1351_K2_E5                                                  0x00770cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1352_K2_E5                                                  0x007710UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1353_K2_E5                                                  0x007714UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1354_K2_E5                                                  0x007718UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1355_K2_E5                                                  0x00771cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1356_K2_E5                                                  0x007720UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1356_RESERVEDFIELD1164_K2_E5                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1356_RESERVEDFIELD1164_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1357_K2_E5                                                  0x007740UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1357_RESERVEDFIELD1165_K2_E5                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1357_RESERVEDFIELD1165_K2_E5_SHIFT                        0
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1357_RESERVEDFIELD1166_K2_E5                              (0xf<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1357_RESERVEDFIELD1166_K2_E5_SHIFT                        1
+#define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1358_K2_E5                                                  0x007744UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_BIST_TX_CTRL_K2_E5                                                                 0x007800UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_BIST_TX_CTRL_EN_K2_E5                                                            (0x1<<0) // Enables BIST Tx data generation.
+  #define PHY_NW_IP_REG_LN0_BIST_TX_CTRL_EN_K2_E5_SHIFT                                                      0
+  #define PHY_NW_IP_REG_LN0_BIST_TX_CTRL_PATTERN_SEL_K2_E5                                                   (0xf<<1) // Selects the pattern to transmitted: 0x1  PRBS 0xC1 0x2  PRBS 0x221 0x3  PRBS 0xA01 0x4  PRBS 0xC001 0x5  PRBS 0x840001 0x6  PRBS 0x90000001 0x7  User defined pattern UDP 0x9  MAC Tx data
+  #define PHY_NW_IP_REG_LN0_BIST_TX_CTRL_PATTERN_SEL_K2_E5_SHIFT                                             1
+#define PHY_NW_IP_REG_LN0_BIST_TX_RESERVEDREGISTER1359_K2_E5                                                 0x007804UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_BIST_TX_RESERVEDREGISTER1360_K2_E5                                                 0x007808UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_BIST_TX_RESERVEDREGISTER1361_K2_E5                                                 0x00780cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_BIST_TX_RESERVEDREGISTER1362_K2_E5                                                 0x007810UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_BIST_TX_BER_CTRL0_K2_E5                                                            0x007818UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_BIST_TX_BER_CTRL0_MODE_K2_E5                                                     (0x3<<0) // Controls what type of error injection is used: 0x0  None 0x1  Single cycle error 0x2  Timer based
+  #define PHY_NW_IP_REG_LN0_BIST_TX_BER_CTRL0_MODE_K2_E5_SHIFT                                               0
+#define PHY_NW_IP_REG_LN0_BIST_TX_BER_CTRL1_K2_E5                                                            0x00781cUL //Access:RW   DataWidth:0x8    // Number of cycles between single bit-error injection
+#define PHY_NW_IP_REG_LN0_BIST_TX_BER_CTRL2_K2_E5                                                            0x007820UL //Access:RW   DataWidth:0x8    // Number of cycles between single bit-error injection
+#define PHY_NW_IP_REG_LN0_BIST_TX_BER_CTRL3_K2_E5                                                            0x007824UL //Access:RW   DataWidth:0x8    // Sets the Tx data bits to be flipped.
+#define PHY_NW_IP_REG_LN0_BIST_TX_BER_CTRL4_K2_E5                                                            0x007828UL //Access:RW   DataWidth:0x8    // Sets the Tx data bits to be flipped.
+#define PHY_NW_IP_REG_LN0_BIST_TX_BER_CTRL5_K2_E5                                                            0x00782cUL //Access:RW   DataWidth:0x8    // Sets the Tx data bits to be flipped.
+#define PHY_NW_IP_REG_LN0_BIST_TX_BER_CTRL6_K2_E5                                                            0x007830UL //Access:RW   DataWidth:0x8    // Sets the Tx data bits to be flipped.
+#define PHY_NW_IP_REG_LN0_BIST_TX_BER_CTRL7_K2_E5                                                            0x007834UL //Access:RW   DataWidth:0x8    // Sets the Tx data bits to be flipped.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_SHIFT_AMOUNT_K2_E5                                                     0x007880UL //Access:RW   DataWidth:0x8    // Determines the length of the UDP.  Must be set to d160 modulus udp_length.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_7_0_K2_E5                                                              0x007890UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_15_8_K2_E5                                                             0x007894UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_23_16_K2_E5                                                            0x007898UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_31_24_K2_E5                                                            0x00789cUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_39_32_K2_E5                                                            0x0078a0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_47_40_K2_E5                                                            0x0078a4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_55_48_K2_E5                                                            0x0078a8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_63_56_K2_E5                                                            0x0078acUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_71_64_K2_E5                                                            0x0078b0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_79_72_K2_E5                                                            0x0078b4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_87_80_K2_E5                                                            0x0078b8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_95_88_K2_E5                                                            0x0078bcUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_103_96_K2_E5                                                           0x0078c0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_111_104_K2_E5                                                          0x0078c4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_119_112_K2_E5                                                          0x0078c8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_127_120_K2_E5                                                          0x0078ccUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_135_128_K2_E5                                                          0x0078d0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_143_136_K2_E5                                                          0x0078d4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_151_144_K2_E5                                                          0x0078d8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_159_152_K2_E5                                                          0x0078dcUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_167_160_K2_E5                                                          0x0078e0UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_175_168_K2_E5                                                          0x0078e4UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_183_176_K2_E5                                                          0x0078e8UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_191_184_K2_E5                                                          0x0078ecUL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN0_BIST_TX_UDP_199_192_K2_E5                                                          0x0078f0UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_K2_E5                                                                 0x007a00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_EN_K2_E5                                                            (0x1<<0) // Enables BIST Rx data checking.
+  #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_EN_K2_E5_SHIFT                                                      0
+  #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_PATTERN_SEL_K2_E5                                                   (0xf<<1) // Selects the pattern to search for: 0x1  PRBS 0xC1 0x2  PRBS 0x221 0x3  PRBS 0xA01 0x4  PRBS 0xC001 0x5  PRBS 0x840001 0x6  PRBS 0x90000001 0x7  User defined pattern UDP 0x8  Auto-detect
+  #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_PATTERN_SEL_K2_E5_SHIFT                                             1
+  #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_CLEAR_BER_K2_E5                                                     (0x1<<5) // Clears the bit error counter.
+  #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_CLEAR_BER_K2_E5_SHIFT                                               5
+  #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_STOP_ERROR_COUNT_K2_E5                                              (0x1<<6) // Stops the error count from incrementing.  Can be used to read back the BER data coherently.
+  #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_STOP_ERROR_COUNT_K2_E5_SHIFT                                        6
+  #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_FORCE_LFSR_WITH_RXDATA_K2_E5                                        (0x1<<7) // Forces the PRBS LFSR to reseed with Rx data every cycle.  This will cause the bit error counter to be inaccurate.
+  #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_FORCE_LFSR_WITH_RXDATA_K2_E5_SHIFT                                  7
+#define PHY_NW_IP_REG_LN0_BIST_RX_STATUS_K2_E5                                                               0x007a10UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_BIST_RX_STATUS_STATE_K2_E5                                                       (0x7<<0) // State of the BIST checker: 0x0  Off 0x1  Searching for pattern 0x2  Waiting for pattern lock conditions 0x3  Pattern lock acquired 0x4  Pattern lock lost
+  #define PHY_NW_IP_REG_LN0_BIST_RX_STATUS_STATE_K2_E5_SHIFT                                                 0
+  #define PHY_NW_IP_REG_LN0_BIST_RX_STATUS_PATTERN_DET_K2_E5                                                 (0xf<<3) // Indicates the pattern  detected: 0x0  No pattern detected 0x1  PRBS 0xC1 0x2  PRBS 0x221 0x3  PRBS 0xA01 0x4  PRBS 0xC001 0x5  PRBS 0x840001 0x6  PRBS 0x90000001 0x7  User defined pattern UDP
+  #define PHY_NW_IP_REG_LN0_BIST_RX_STATUS_PATTERN_DET_K2_E5_SHIFT                                           3
+#define PHY_NW_IP_REG_LN0_BIST_RX_BER_STATUS0_K2_E5                                                          0x007a20UL //Access:R    DataWidth:0x8    // Number of bit errors.
+#define PHY_NW_IP_REG_LN0_BIST_RX_BER_STATUS1_K2_E5                                                          0x007a24UL //Access:R    DataWidth:0x8    // Number of bit errors.
+#define PHY_NW_IP_REG_LN0_BIST_RX_BER_STATUS2_K2_E5                                                          0x007a28UL //Access:R    DataWidth:0x8    // Number of bit errors.
+#define PHY_NW_IP_REG_LN0_BIST_RX_BER_STATUS4_K2_E5                                                          0x007a30UL //Access:R    DataWidth:0x8    // Number of cycles that errors have been counted.
+#define PHY_NW_IP_REG_LN0_BIST_RX_BER_STATUS5_K2_E5                                                          0x007a34UL //Access:R    DataWidth:0x8    // Number of cycles that errors have been counted.
+#define PHY_NW_IP_REG_LN0_BIST_RX_BER_STATUS6_K2_E5                                                          0x007a38UL //Access:R    DataWidth:0x8    // Number of cycles that errors have been counted.
+#define PHY_NW_IP_REG_LN0_BIST_RX_LOCK_CTRL0_K2_E5                                                           0x007a50UL //Access:RW   DataWidth:0x8    // Size of error sampling window to trigger pattern lock.
+#define PHY_NW_IP_REG_LN0_BIST_RX_LOCK_CTRL1_K2_E5                                                           0x007a54UL //Access:RW   DataWidth:0x8    // Size of error sampling window to trigger pattern lock.
+#define PHY_NW_IP_REG_LN0_BIST_RX_LOCK_CTRL2_K2_E5                                                           0x007a58UL //Access:RW   DataWidth:0x8    // Maximum number of errors allowed to trigger pattern lock.
+#define PHY_NW_IP_REG_LN0_BIST_RX_LOCK_CTRL3_K2_E5                                                           0x007a5cUL //Access:RW   DataWidth:0x8    // Maximum number of errors allowed to trigger pattern lock.
+#define PHY_NW_IP_REG_LN0_BIST_RX_LOSS_LOCK_CTRL0_K2_E5                                                      0x007a80UL //Access:RW   DataWidth:0x8    // Size of error sampling window to trigger pattern loss-of-lock.
+#define PHY_NW_IP_REG_LN0_BIST_RX_LOSS_LOCK_CTRL1_K2_E5                                                      0x007a84UL //Access:RW   DataWidth:0x8    // Size of error sampling window to trigger pattern loss-of-lock.
+#define PHY_NW_IP_REG_LN0_BIST_RX_LOSS_LOCK_CTRL2_K2_E5                                                      0x007a88UL //Access:RW   DataWidth:0x8    // Minimum number of errors allowed to trigger pattern loss-of-lock.
+#define PHY_NW_IP_REG_LN0_BIST_RX_LOSS_LOCK_CTRL3_K2_E5                                                      0x007a8cUL //Access:RW   DataWidth:0x8    // Minimum number of errors allowed to trigger pattern loss-of-lock.
+#define PHY_NW_IP_REG_LN0_BIST_RX_LOSS_LOCK_CTRL4_K2_E5                                                      0x007a90UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_BIST_RX_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_K2_E5                                  (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
+  #define PHY_NW_IP_REG_LN0_BIST_RX_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_K2_E5_SHIFT                            0
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_SHIFT_AMOUNT_K2_E5                                                     0x007ac0UL //Access:RW   DataWidth:0x8    // Determines the length of the UDP.  Must be set to d160 modulus udp_length.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_7_0_K2_E5                                                              0x007ad0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_15_8_K2_E5                                                             0x007ad4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_23_16_K2_E5                                                            0x007ad8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_31_24_K2_E5                                                            0x007adcUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_39_32_K2_E5                                                            0x007ae0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_47_40_K2_E5                                                            0x007ae4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_55_48_K2_E5                                                            0x007ae8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_63_56_K2_E5                                                            0x007aecUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_71_64_K2_E5                                                            0x007af0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_79_72_K2_E5                                                            0x007af4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_87_80_K2_E5                                                            0x007af8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_95_88_K2_E5                                                            0x007afcUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_103_96_K2_E5                                                           0x007b00UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_111_104_K2_E5                                                          0x007b04UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_119_112_K2_E5                                                          0x007b08UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_127_120_K2_E5                                                          0x007b0cUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_135_128_K2_E5                                                          0x007b10UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_143_136_K2_E5                                                          0x007b14UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_151_144_K2_E5                                                          0x007b18UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_159_152_K2_E5                                                          0x007b1cUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_167_160_K2_E5                                                          0x007b20UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_175_168_K2_E5                                                          0x007b24UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_183_176_K2_E5                                                          0x007b28UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_191_184_K2_E5                                                          0x007b2cUL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN0_BIST_RX_UDP_199_192_K2_E5                                                          0x007b30UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN0_FEATURE_RXTERM_CFG0_K2_E5                                                          0x007c00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_RXTERM_CFG0_AC_COUPLED_K2_E5                                             (0x1<<0) // Configures AC/DC coupling of the lane 0: DC coupled 1: AC coupled
+  #define PHY_NW_IP_REG_LN0_FEATURE_RXTERM_CFG0_AC_COUPLED_K2_E5_SHIFT                                       0
+#define PHY_NW_IP_REG_LN0_FEATURE_RXCLKDIV_CFG0_K2_E5                                                        0x007c04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_RXCLKDIV_CFG0_EN_K2_E5                                                   (0x1<<0) // Enables turning on the divided rxclk output
+  #define PHY_NW_IP_REG_LN0_FEATURE_RXCLKDIV_CFG0_EN_K2_E5_SHIFT                                             0
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1363_K2_E5                                                 0x007c10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1363_RESERVEDFIELD1172_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1363_RESERVEDFIELD1172_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1363_RESERVEDFIELD1173_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1363_RESERVEDFIELD1173_K2_E5_SHIFT                       1
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1364_K2_E5                                                 0x007c14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1364_RESERVEDFIELD1174_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1364_RESERVEDFIELD1174_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1364_RESERVEDFIELD1175_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1364_RESERVEDFIELD1175_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1364_RESERVEDFIELD1176_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1364_RESERVEDFIELD1176_K2_E5_SHIFT                       2
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1364_RESERVEDFIELD1177_K2_E5                             (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1364_RESERVEDFIELD1177_K2_E5_SHIFT                       3
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1364_RESERVEDFIELD1178_K2_E5                             (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1364_RESERVEDFIELD1178_K2_E5_SHIFT                       4
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1364_RESERVEDFIELD1179_K2_E5                             (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1364_RESERVEDFIELD1179_K2_E5_SHIFT                       5
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1365_K2_E5                                                 0x007c18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1365_RESERVEDFIELD1180_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1365_RESERVEDFIELD1180_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1365_RESERVEDFIELD1181_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1365_RESERVEDFIELD1181_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1365_RESERVEDFIELD1182_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1365_RESERVEDFIELD1182_K2_E5_SHIFT                       2
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1365_RESERVEDFIELD1183_K2_E5                             (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1365_RESERVEDFIELD1183_K2_E5_SHIFT                       3
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_K2_E5                                                 0x007c1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1184_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1184_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1185_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1185_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1186_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1186_K2_E5_SHIFT                       2
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1187_K2_E5                             (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1187_K2_E5_SHIFT                       3
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1188_K2_E5                             (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1188_K2_E5_SHIFT                       4
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1189_K2_E5                             (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1189_K2_E5_SHIFT                       5
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1190_K2_E5                             (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1190_K2_E5_SHIFT                       6
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1191_K2_E5                             (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1191_K2_E5_SHIFT                       7
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1367_K2_E5                                                 0x007c20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1367_RESERVEDFIELD1192_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1367_RESERVEDFIELD1192_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1367_RESERVEDFIELD1193_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1367_RESERVEDFIELD1193_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1367_RESERVEDFIELD1194_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1367_RESERVEDFIELD1194_K2_E5_SHIFT                       2
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1367_RESERVEDFIELD1195_K2_E5                             (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1367_RESERVEDFIELD1195_K2_E5_SHIFT                       3
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1367_RESERVEDFIELD1196_K2_E5                             (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1367_RESERVEDFIELD1196_K2_E5_SHIFT                       4
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1368_K2_E5                                                 0x007c24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1368_RESERVEDFIELD1197_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1368_RESERVEDFIELD1197_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1368_RESERVEDFIELD1198_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1368_RESERVEDFIELD1198_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1368_RESERVEDFIELD1199_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1368_RESERVEDFIELD1199_K2_E5_SHIFT                       2
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1369_K2_E5                                                 0x007c40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1369_RESERVEDFIELD1200_K2_E5                             (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1369_RESERVEDFIELD1200_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1370_K2_E5                                                 0x007c44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1370_RESERVEDFIELD1201_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1370_RESERVEDFIELD1201_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1371_K2_E5                                                 0x007c48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1371_RESERVEDFIELD1202_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1371_RESERVEDFIELD1202_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1371_RESERVEDFIELD1203_K2_E5                             (0x7f<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1371_RESERVEDFIELD1203_K2_E5_SHIFT                       1
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1372_K2_E5                                                 0x007c4cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1373_K2_E5                                                 0x007c50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1373_RESERVEDFIELD1205_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1373_RESERVEDFIELD1205_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1373_RESERVEDFIELD1206_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1373_RESERVEDFIELD1206_K2_E5_SHIFT                       1
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1374_K2_E5                                                 0x007c54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1374_RESERVEDFIELD1207_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1374_RESERVEDFIELD1207_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1374_RESERVEDFIELD1208_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1374_RESERVEDFIELD1208_K2_E5_SHIFT                       1
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1375_K2_E5                                                 0x007c58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1375_RESERVEDFIELD1209_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1375_RESERVEDFIELD1209_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1375_RESERVEDFIELD1210_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1375_RESERVEDFIELD1210_K2_E5_SHIFT                       1
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1376_K2_E5                                                 0x007c80UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1376_RESERVEDFIELD1211_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1376_RESERVEDFIELD1211_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_CFG_K2_E5                                                       0x007c84UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT0_K2_E5                                  (0x3<<0) // How many times to repeat CTLE adaptation sequence for initial adaptation set 0
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT0_K2_E5_SHIFT                            0
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT1_K2_E5                                  (0x3<<2) // How many times to repeat CTLE adaptation sequence for initial adaptation set 1
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT1_K2_E5_SHIFT                            2
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_CFG_RESERVEDFIELD1212_K2_E5                                   (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_CFG_RESERVEDFIELD1212_K2_E5_SHIFT                             4
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_CFG_RESERVEDFIELD1213_K2_E5                                   (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_CFG_RESERVEDFIELD1213_K2_E5_SHIFT                             6
+#define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_AGC_CFG_K2_E5                                                   0x007c88UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN_K2_E5                                        (0x1<<0) // Enables AGC threshold adaptation for initial adaptation
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_AGC_CFG_RESERVEDFIELD1214_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_AGC_CFG_RESERVEDFIELD1214_K2_E5_SHIFT                         2
+#define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_APG_MAP_CFG_K2_E5                                               0x007c8cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN_K2_E5                                    (0x1<<0) // Enables mapping GN_APG setting from AGC threshold for initial adaptation
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_APG_MAP_CFG_RESERVEDFIELD1215_K2_E5                           (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_APG_MAP_CFG_RESERVEDFIELD1215_K2_E5_SHIFT                     2
+#define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_LFG_CFG_K2_E5                                                   0x007c90UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL_K2_E5                                       (0x3<<0) // Selects the CTLE EQ LFG adaptation method for initial adaptation set 0 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loop 0x3: Method 3: GN_APG and EQ_LFG combined closed-loop
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL_K2_E5                                       (0x3<<2) // Selects the CTLE EQ LFG adaptation method for initial adaptation set 1 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loop 0x3: Method 3: GN_APG and EQ_LFG combined closed-loop
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL_K2_E5_SHIFT                                 2
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_LFG_CFG_RESERVEDFIELD1216_K2_E5                               (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_LFG_CFG_RESERVEDFIELD1216_K2_E5_SHIFT                         4
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_LFG_CFG_RESERVEDFIELD1217_K2_E5                               (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_LFG_CFG_RESERVEDFIELD1217_K2_E5_SHIFT                         6
+#define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_K2_E5                                                  0x007c94UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN_K2_E5                                  (0x1<<0) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 0
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN_K2_E5_SHIFT                            0
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN_K2_E5                                  (0x1<<1) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 0
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN_K2_E5_SHIFT                            1
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN_K2_E5                                  (0x1<<2) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 1
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN_K2_E5_SHIFT                            2
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN_K2_E5                                  (0x1<<3) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 1
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN_K2_E5_SHIFT                            3
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD1218_K2_E5                              (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD1218_K2_E5_SHIFT                        4
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD1219_K2_E5                              (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD1219_K2_E5_SHIFT                        5
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD1220_K2_E5                              (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD1220_K2_E5_SHIFT                        6
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD1221_K2_E5                              (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD1221_K2_E5_SHIFT                        7
+#define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG1_K2_E5                                                  0x007c98UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL_K2_E5                               (0x3<<0) // Selects which HFG result to use for the initial adaptation set 0 0x0: Edge Based 0x1: Data Based 0x2: Average of Edge & Data result 0x3: Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL_K2_E5                               (0x3<<2) // Selects which HFG result to use for the initial adaptation set 1 0x0: Edge Based 0x1: Data Based 0x2: Average of Edge & Data result 0x3: Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG1_RESERVEDFIELD1222_K2_E5                              (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG1_RESERVEDFIELD1222_K2_E5_SHIFT                        4
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG1_RESERVEDFIELD1223_K2_E5                              (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG1_RESERVEDFIELD1223_K2_E5_SHIFT                        6
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1377_K2_E5                                                 0x007c9cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1377_RESERVEDFIELD1224_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1377_RESERVEDFIELD1224_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_MBS_CFG_K2_E5                                                   0x007ca0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_K2_E5                                        (0x1<<0) // Enables CTLE midband shaping adaptation for initial adaptation set 0
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN_K2_E5                                        (0x1<<1) // Enables CTLE midband shaping adaptation for initial adaptation set 1
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN_K2_E5_SHIFT                                  1
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD1225_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD1225_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD1226_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD1226_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_K2_E5                                                 0x007ca4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1227_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1227_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1228_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1228_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1229_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1229_K2_E5_SHIFT                       2
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1230_K2_E5                             (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1230_K2_E5_SHIFT                       3
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1231_K2_E5                             (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1231_K2_E5_SHIFT                       4
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1232_K2_E5                             (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1232_K2_E5_SHIFT                       5
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1233_K2_E5                             (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1233_K2_E5_SHIFT                       6
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1234_K2_E5                             (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1234_K2_E5_SHIFT                       7
+#define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_K2_E5                                                              0x007cc0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP1_EN_K2_E5                                                    (0x1<<0) // Enables DFE Tap 1. Tap1 will not be powered up if it is not enabled
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP1_EN_K2_E5_SHIFT                                              0
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP2_EN_K2_E5                                                    (0x1<<1) // Enables DFE Tap 2. Tap2 will not be powered up if it is not enabled
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP2_EN_K2_E5_SHIFT                                              1
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP3_EN_K2_E5                                                    (0x1<<2) // Enables DFE Tap 3. Tap3 will not be powered up if it is not enabled
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP3_EN_K2_E5_SHIFT                                              2
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP4_EN_K2_E5                                                    (0x1<<3) // Enables DFE Tap 4. Tap4 will not be powered up if it is not enabled
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP4_EN_K2_E5_SHIFT                                              3
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP5_EN_K2_E5                                                    (0x1<<4) // Enables DFE Tap 5. Tap5 will not be powered up if it is not enabled
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP5_EN_K2_E5_SHIFT                                              4
+#define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_CFG_K2_E5                                                        0x007cc4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_CFG_METHOD_SEL_K2_E5                                           (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Based Zero Forcing
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_CFG_METHOD_SEL_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP1_CFG_K2_E5                                                   0x007cc8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN_K2_E5                                    (0x1<<0) // Enables initial adaptations for Tap 1
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD1235_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD1235_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD1236_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD1236_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD1237_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD1237_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP2_CFG_K2_E5                                                   0x007cccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN_K2_E5                                    (0x1<<0) // Enables initial adaptations for Tap 2
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD1238_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD1238_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD1239_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD1239_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD1240_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD1240_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP3_CFG_K2_E5                                                   0x007cd0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN_K2_E5                                    (0x1<<0) // Enables initial adaptations for Tap 3
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD1241_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD1241_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD1242_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD1242_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD1243_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD1243_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP4_CFG_K2_E5                                                   0x007cd4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN_K2_E5                                    (0x1<<0) // Enables initial adaptations for Tap 4
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD1244_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD1244_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD1245_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD1245_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD1246_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD1246_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP5_CFG_K2_E5                                                   0x007cd8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN_K2_E5                                    (0x1<<0) // Enables initial adaptations for Tap 5
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD1247_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD1247_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD1248_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD1248_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD1249_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD1249_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_LN0_FEATURE_ADAPT_CONT_CFG0_K2_E5                                                      0x007ce0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_ADAPT_CONT_CFG0_EN_K2_E5                                                 (0x1<<0) // Enables continuous background adaptation
+  #define PHY_NW_IP_REG_LN0_FEATURE_ADAPT_CONT_CFG0_EN_K2_E5_SHIFT                                           0
+  #define PHY_NW_IP_REG_LN0_FEATURE_ADAPT_CONT_CFG0_RESERVEDFIELD1250_K2_E5                                  (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_ADAPT_CONT_CFG0_RESERVEDFIELD1250_K2_E5_SHIFT                            1
+#define PHY_NW_IP_REG_LN0_FEATURE_ADAPT_CONT_CFG1_K2_E5                                                      0x007ce4UL //Access:RW   DataWidth:0x8    // How often in ms to run continuous adaptations 1ms to ~279 mins
+#define PHY_NW_IP_REG_LN0_FEATURE_ADAPT_CONT_CFG2_K2_E5                                                      0x007ce8UL //Access:RW   DataWidth:0x8    // How often in ms to run continuous adaptations 1ms to ~279 mins
+#define PHY_NW_IP_REG_LN0_FEATURE_ADAPT_CONT_CFG3_K2_E5                                                      0x007cecUL //Access:RW   DataWidth:0x8    // How often in ms to run continuous adaptations 1ms to ~279 mins
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1379_K2_E5                                                 0x007cf0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1380_K2_E5                                                 0x007cf4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1381_K2_E5                                                 0x007cf8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1382_K2_E5                                                 0x007cfcUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1383_K2_E5                                                 0x007d00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1383_RESERVEDFIELD1255_K2_E5                             (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1383_RESERVEDFIELD1255_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1383_RESERVEDFIELD1256_K2_E5                             (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1383_RESERVEDFIELD1256_K2_E5_SHIFT                       2
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1384_K2_E5                                                 0x007d04UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1385_K2_E5                                                 0x007d08UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1386_K2_E5                                                 0x007d0cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1387_K2_E5                                                 0x007d10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1387_RESERVEDFIELD1260_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1387_RESERVEDFIELD1260_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1388_K2_E5                                                 0x007d14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1388_RESERVEDFIELD1261_K2_E5                             (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1388_RESERVEDFIELD1261_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1388_RESERVEDFIELD1262_K2_E5                             (0x1f<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1388_RESERVEDFIELD1262_K2_E5_SHIFT                       3
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1389_K2_E5                                                 0x007d18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1389_RESERVEDFIELD1263_K2_E5                             (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1389_RESERVEDFIELD1263_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1389_RESERVEDFIELD1264_K2_E5                             (0x1f<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1389_RESERVEDFIELD1264_K2_E5_SHIFT                       2
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1390_K2_E5                                                 0x007d1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1390_RESERVEDFIELD1265_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1390_RESERVEDFIELD1265_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1390_RESERVEDFIELD1266_K2_E5                             (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1390_RESERVEDFIELD1266_K2_E5_SHIFT                       4
+#define PHY_NW_IP_REG_LN0_FEATURE_TEST_CFG0_K2_E5                                                            0x007d40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_FEATURE_TEST_CFG0_RESERVEDFIELD1267_K2_E5                                        (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_TEST_CFG0_RESERVEDFIELD1267_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN0_FEATURE_TEST_CFG0_RX_CTRL_DIS_K2_E5                                              (0x1<<1) // Disables the firmware rx_ctrl MSM
+  #define PHY_NW_IP_REG_LN0_FEATURE_TEST_CFG0_RX_CTRL_DIS_K2_E5_SHIFT                                        1
+  #define PHY_NW_IP_REG_LN0_FEATURE_TEST_CFG0_RESERVEDFIELD1268_K2_E5                                        (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_TEST_CFG0_RESERVEDFIELD1268_K2_E5_SHIFT                                  2
+  #define PHY_NW_IP_REG_LN0_FEATURE_TEST_CFG0_RESERVEDFIELD1269_K2_E5                                        (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN0_FEATURE_TEST_CFG0_RESERVEDFIELD1269_K2_E5_SHIFT                                  3
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1391_K2_E5                                                 0x007d60UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1392_K2_E5                                                 0x007d64UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1393_K2_E5                                                 0x007d68UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1394_K2_E5                                                 0x007d6cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1395_K2_E5                                                 0x007d70UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1396_K2_E5                                                 0x007d74UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1397_K2_E5                                                 0x007d78UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1398_K2_E5                                                 0x007d7cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_K2_E5                                                              0x007e00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_MR_RESTART_TRAINING_K2_E5                                        (0x1<<0) // Starts link training procedure when asserted.  This is an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_MR_RESTART_TRAINING_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_MR_TRAINING_ENABLE_K2_E5                                         (0x1<<1) // Indicates to LTSM that link training procedure should be run; otherwise procedures skip directly to signal_det assertion.  This is an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_MR_TRAINING_ENABLE_K2_E5_SHIFT                                   1
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_SIGNAL_DETECT_K2_E5                                              (0x1<<2) // Output corresponding to link training signal detect variable.  Should be set when link training has completed successfully.
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_SIGNAL_DETECT_K2_E5_SHIFT                                        2
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_CLEAR_K2_E5                                                      (0x1<<3) // Synchronous reset for LT Tx block.
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_CLEAR_K2_E5_SHIFT                                                3
+#define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL1_K2_E5                                                              0x007e04UL //Access:RW   DataWidth:0x8    // Maximum time allowed for LT procedure.  If this is exceeded then the training_fail status will assert.  This is an 802.defined variable.  Value is encoded as: 39338 * DESIRED_DELAY * 2 ^logdata_width / data_width  Should be set to 500ns for 802.3 compliant timeout.
+#define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL2_K2_E5                                                              0x007e08UL //Access:RW   DataWidth:0x8    // Same as above.
+#define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL3_K2_E5                                                              0x007e0cUL //Access:RW   DataWidth:0x8    // Number of additional frames to send after both receivers have been trained and are ready.  This is an 802.3 defined variable.  Should be set between 100 and 300 for 802.3 compliance.
+#define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL4_K2_E5                                                              0x007e10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL4_WAIT_TIME_8_K2_E5                                                (0x1<<0) // Same as above.
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL4_WAIT_TIME_8_K2_E5_SHIFT                                          0
+#define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL5_K2_E5                                                              0x007e14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL5_FRAME_LOCK_K2_E5                                                 (0x1<<0) // Input to LTSM that receiver has acquired frame lock.  This value should be taken from the corresponding LT Rx register.  This  an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL5_FRAME_LOCK_K2_E5_SHIFT                                           0
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL5_RX_TRAINED_K2_E5                                                 (0x1<<1) // Input to LTSM indicating that the local receiver has completed training.  This is an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL5_RX_TRAINED_K2_E5_SHIFT                                           1
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL5_REMOTE_RX_READY_K2_E5                                            (0x1<<2) // Input to LTSM indicating that the remote receiver is trained and ready.  This value should be taken from the corresponding LT Rx registers.  This is an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL5_REMOTE_RX_READY_K2_E5_SHIFT                                      2
+#define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_K2_E5                                                             0x007e40UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_TRAINING_FAIL_K2_E5                                             (0x1<<0) // Output from LTSM indicating that link training has failed.  This is an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_TRAINING_FAIL_K2_E5_SHIFT                                       0
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_TRAINING_K2_E5                                                  (0x1<<1) // Output from LTSM indicating that link training is in progress.  This is an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_TRAINING_K2_E5_SHIFT                                            1
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_SIGNAL_DETECT_K2_E5                                             (0x1<<2) // Output from LTSM indicating that link training is complete and successful.  This is an 802.3 defined variable.  This value is only visible internally, and is not the signal_det value driven to PHY top-level.
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_SIGNAL_DETECT_K2_E5_SHIFT                                       2
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_FSM_LOCAL_RX_READY_K2_E5                                        (0x1<<4) // Output from LSM corresponding to 802.3 defined local_rx_ready variable. After this is asserted the corresponding frame status report field should be set.
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_FSM_LOCAL_RX_READY_K2_E5_SHIFT                                  4
+#define PHY_NW_IP_REG_LN0_LT_TX_PRBS_CTRL0_K2_E5                                                             0x007e4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LT_TX_PRBS_CTRL0_POLYNOMIAL_K2_E5                                                (0x7<<0) // Selects between CL72 and CL93 PRBS pattern. 0  CL72 1 + x^9 +x^11 1  CL93 1 + x^5 + x^6 + x^10 + x^11 2  CL93 1 + x^5 + x^6 + x^9 + x^11 3  CL93 1 + x^4 + x^6 + x^8 + x^11 4  CL93 1 + x^4 + x^6 + x^7 + x^11
+  #define PHY_NW_IP_REG_LN0_LT_TX_PRBS_CTRL0_POLYNOMIAL_K2_E5_SHIFT                                          0
+#define PHY_NW_IP_REG_LN0_LT_TX_PRBS_CTRL1_K2_E5                                                             0x007e50UL //Access:RW   DataWidth:0x8    // Initial PRBS LFSR seed.  This needs to be set according to the requirements in 802.3 CL72 or CL93 depending on the type of link training and lane bonding being performed.
+#define PHY_NW_IP_REG_LN0_LT_TX_PRBS_CTRL2_K2_E5                                                             0x007e54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LT_TX_PRBS_CTRL2_SEED_10_8_K2_E5                                                 (0x7<<0) // Same as above.
+  #define PHY_NW_IP_REG_LN0_LT_TX_PRBS_CTRL2_SEED_10_8_K2_E5_SHIFT                                           0
+#define PHY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL_K2_E5                                                0x007e80UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL_C_P1_K2_E5                                         (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00  hold 2'b01  increment 2'b10  decrement 2'b11  reserved
+  #define PHY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL_C_P1_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL_C_0_K2_E5                                          (0x3<<2) // Coefficient update request field for cursor tap.
+  #define PHY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL_C_0_K2_E5_SHIFT                                    2
+  #define PHY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL_C_M1_K2_E5                                         (0x3<<4) // Coefficient update request field for pre-cursor tap.
+  #define PHY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL_C_M1_K2_E5_SHIFT                                   4
+  #define PHY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL_INITIALIZE_K2_E5                                   (0x1<<6) // Coefficient update initialize field.
+  #define PHY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL_INITIALIZE_K2_E5_SHIFT                             6
+  #define PHY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL_PRESET_K2_E5                                       (0x1<<7) // Coefficient update preset field.
+  #define PHY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL_PRESET_K2_E5_SHIFT                                 7
+#define PHY_NW_IP_REG_LN0_LT_TX_STATUS_REPORT_CTRL_K2_E5                                                     0x007e88UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LT_TX_STATUS_REPORT_CTRL_C_P1_K2_E5                                              (0x3<<0) // Status report field for post-cursor tap. 2'b00  not updated 2'b01  minimum 2'b10  updated 2'b11  maximum
+  #define PHY_NW_IP_REG_LN0_LT_TX_STATUS_REPORT_CTRL_C_P1_K2_E5_SHIFT                                        0
+  #define PHY_NW_IP_REG_LN0_LT_TX_STATUS_REPORT_CTRL_C_0_K2_E5                                               (0x3<<2) // Status report field for cursor tap.
+  #define PHY_NW_IP_REG_LN0_LT_TX_STATUS_REPORT_CTRL_C_0_K2_E5_SHIFT                                         2
+  #define PHY_NW_IP_REG_LN0_LT_TX_STATUS_REPORT_CTRL_C_M1_K2_E5                                              (0x3<<4) // Status report field for pre-cursor tap.
+  #define PHY_NW_IP_REG_LN0_LT_TX_STATUS_REPORT_CTRL_C_M1_K2_E5_SHIFT                                        4
+  #define PHY_NW_IP_REG_LN0_LT_TX_STATUS_REPORT_CTRL_LOCAL_RX_READY_K2_E5                                    (0x1<<6) // Status report field to indicate local receiver is ready.  Should be set based on LTSM output of corresponding variable.
+  #define PHY_NW_IP_REG_LN0_LT_TX_STATUS_REPORT_CTRL_LOCAL_RX_READY_K2_E5_SHIFT                              6
+#define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS0_K2_E5                                                      0x007ec0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS0_CURRENT_K2_E5                                            (0x7<<0) // Current state of LTSM. 0x0  INITIALIZE 0x1  SEND_TRAINING 0x2  TRAIN_REMOTE 0x3  TRAIN_LOCAL 0x4  S7 0x5  TRAINING_FAILURE 0x6  LINK_READY 0x7  SEND_DATA
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS0_CURRENT_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS0_PREV1_K2_E5                                              (0x7<<4) // One state previous.
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS0_PREV1_K2_E5_SHIFT                                        4
+#define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS1_K2_E5                                                      0x007ec4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS1_PREV2_K2_E5                                              (0x7<<0) // Two states previous.
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS1_PREV2_K2_E5_SHIFT                                        0
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS1_PREV3_K2_E5                                              (0x7<<4) // Three states previous.
+  #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS1_PREV3_K2_E5_SHIFT                                        4
+#define PHY_NW_IP_REG_LN0_LT_RX_CTRL0_K2_E5                                                                  0x007f00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LT_RX_CTRL0_CLEAR_K2_E5                                                          (0x1<<0) // Synchronous reset for LT Rx block.
+  #define PHY_NW_IP_REG_LN0_LT_RX_CTRL0_CLEAR_K2_E5_SHIFT                                                    0
+  #define PHY_NW_IP_REG_LN0_LT_RX_CTRL0_TRAINING_K2_E5                                                       (0x1<<1) // This is the 802.3 defined training variable.  It should be set according to corresponding LTSM output.
+  #define PHY_NW_IP_REG_LN0_LT_RX_CTRL0_TRAINING_K2_E5_SHIFT                                                 1
+#define PHY_NW_IP_REG_LN0_LT_RX_PRBS_CTRL0_K2_E5                                                             0x007f08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_CTRL0_POLYNOMIAL_K2_E5                                                (0x7<<0) // Selects between CL72 and CL93 PRBS patterns. 0  CL72 1 + x^9 + x^11 1  CL93 1 + x^5 + x^6 + x^10 + x^11 2  CL93 1 + x^5 + x^6 + x^9 + x^11 3  CL93 1 + x^4 + x^6 + x^8 + x^11 4  CL93 1 + x^4 + x^6 + x^7 + x^11
+  #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_CTRL0_POLYNOMIAL_K2_E5_SHIFT                                          0
+#define PHY_NW_IP_REG_LN0_LT_RX_PRBS_CTRL1_K2_E5                                                             0x007f0cUL //Access:RW   DataWidth:0x8    // Maximum number  of PRBS bit errors allowed in single LT frame for PRBS lock to be achieved.
+#define PHY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS0_K2_E5                                                           0x007f14UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS0_UPDATE_K2_E5                                                  (0x1<<0) // Assertion indicates that PRBS status information has been updated.
+  #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS0_UPDATE_K2_E5_SHIFT                                            0
+  #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS0_LOCK_K2_E5                                                    (0x1<<1) // Indicates that a valid PRBS pattern has been detected in receiver LT frame.
+  #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS0_LOCK_K2_E5_SHIFT                                              1
+#define PHY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS1_K2_E5                                                           0x007f18UL //Access:R    DataWidth:0x8    // Number of bit errors in PRBS pattern since last lock assertion event.
+#define PHY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS2_K2_E5                                                           0x007f1cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS2_ERROR_COUNT_11_8_K2_E5                                        (0xf<<0) // Same as above.
+  #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS2_ERROR_COUNT_11_8_K2_E5_SHIFT                                  0
+#define PHY_NW_IP_REG_LN0_LT_RX_FRAME_CTRL_K2_E5                                                             0x007f40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LT_RX_FRAME_CTRL_CLEAR_COUNT_K2_E5                                               (0x1<<0) // Clears both the absolute and erroneous frame counters.
+  #define PHY_NW_IP_REG_LN0_LT_RX_FRAME_CTRL_CLEAR_COUNT_K2_E5_SHIFT                                         0
+#define PHY_NW_IP_REG_LN0_LT_RX_FRAME_STATUS0_K2_E5                                                          0x007f4cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LT_RX_FRAME_STATUS0_FRAME_LOCK_K2_E5                                             (0x1<<0) // Indicates that the receiver has locked to incoming LT frames.
+  #define PHY_NW_IP_REG_LN0_LT_RX_FRAME_STATUS0_FRAME_LOCK_K2_E5_SHIFT                                       0
+#define PHY_NW_IP_REG_LN0_LT_RX_FRAME_STATUS1_K2_E5                                                          0x007f50UL //Access:R    DataWidth:0x8    // Total number of received frames since frame lock.
+#define PHY_NW_IP_REG_LN0_LT_RX_FRAME_STATUS2_K2_E5                                                          0x007f54UL //Access:R    DataWidth:0x8    // Same as above.
+#define PHY_NW_IP_REG_LN0_LT_RX_FRAME_STATUS3_K2_E5                                                          0x007f58UL //Access:R    DataWidth:0x8    // Total number of received frames  with a PRBS, DME, or framing error since frame lock.
+#define PHY_NW_IP_REG_LN0_LT_RX_FRAME_STATUS4_K2_E5                                                          0x007f5cUL //Access:R    DataWidth:0x8    // Same as above.
+#define PHY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS_K2_E5                                              0x007f80UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS_C_P1_K2_E5                                       (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00  hold 2'b01  increment 2'b10  decrement 2'b11  reserved
+  #define PHY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS_C_P1_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS_C_0_K2_E5                                        (0x3<<2) // Received coefficient update request field for cursor tap.
+  #define PHY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS_C_0_K2_E5_SHIFT                                  2
+  #define PHY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS_C_M1_K2_E5                                       (0x3<<4) // Received coefficient update request field for pre-cursor tap.
+  #define PHY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS_C_M1_K2_E5_SHIFT                                 4
+  #define PHY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS_INITIALIZE_K2_E5                                 (0x1<<6) // Received coefficient update initialize field.
+  #define PHY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS_INITIALIZE_K2_E5_SHIFT                           6
+  #define PHY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS_PRESET_K2_E5                                     (0x1<<7) // Received coefficient update preset field.
+  #define PHY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS_PRESET_K2_E5_SHIFT                               7
+#define PHY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS_K2_E5                                                          0x007f88UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS_C_P1_K2_E5                                                   (0x3<<0) // Received status report field for post-cursor tap. 2'b00  not updated 2'b01  minimum 2'b10  updated 2'b11  maximum
+  #define PHY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS_C_P1_K2_E5_SHIFT                                             0
+  #define PHY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS_C_0_K2_E5                                                    (0x3<<2) // Received status report field for cursor tap.
+  #define PHY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS_C_0_K2_E5_SHIFT                                              2
+  #define PHY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS_C_M1_K2_E5                                                   (0x3<<4) // Received status report field for pre-cursor tap.
+  #define PHY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS_C_M1_K2_E5_SHIFT                                             4
+  #define PHY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS_LOCAL_RX_READY_K2_E5                                         (0x1<<6) // Received status report field to indicate local receiver is ready.
+  #define PHY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS_LOCAL_RX_READY_K2_E5_SHIFT                                   6
+  #define PHY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS_DME_ERROR_K2_E5                                              (0x1<<7) // Indicates differential manchester decoding error.  Not sticky.
+  #define PHY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS_DME_ERROR_K2_E5_SHIFT                                        7
+#define PHY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_K2_E5                                                        0x008000UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_K2_E5                                    (0x1<<0) // RX clock loopback mode enable.   0x0 - mission mode 0x1 - select recovered clock from CDR as source of half-rate TX clock path.
+  #define PHY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_K2_E5                                    (0x1<<1) // TX clock loopback mode enable.  0x0 - mission mode 0x1 - MUX half-rate TX clock into LEQ gain stage.
+  #define PHY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_K2_E5                                      (0x1<<2) // Far-End Analog FEA loopback mode enable.  0x0 - mission mode 0x1 - loop back parallel data from RX data path to TX data path internal to AFE
+  #define PHY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_K2_E5_SHIFT                                2
+  #define PHY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_K2_E5                                      (0x1<<3) // Near-End Analog NEA loopback mode enable.  0x0 - mission mode 0x1 - loop back quarter rate data from TX data path to RX data path internal to AFE.
+  #define PHY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_K2_E5_SHIFT                                3
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1399_K2_E5                                                     0x008004UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1399_RESERVEDFIELD1270_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1399_RESERVEDFIELD1270_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1399_RESERVEDFIELD1271_K2_E5                                 (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1399_RESERVEDFIELD1271_K2_E5_SHIFT                           2
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1399_RESERVEDFIELD1272_K2_E5                                 (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1399_RESERVEDFIELD1272_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1400_K2_E5                                                     0x008008UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1400_RESERVEDFIELD1273_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1400_RESERVEDFIELD1273_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1400_RESERVEDFIELD1274_K2_E5                                 (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1400_RESERVEDFIELD1274_K2_E5_SHIFT                           2
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1400_RESERVEDFIELD1275_K2_E5                                 (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1400_RESERVEDFIELD1275_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1401_K2_E5                                                     0x00800cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1401_RESERVEDFIELD1276_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1401_RESERVEDFIELD1276_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1402_K2_E5                                                     0x008010UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1402_RESERVEDFIELD1277_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1402_RESERVEDFIELD1277_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1402_RESERVEDFIELD1278_K2_E5                                 (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1402_RESERVEDFIELD1278_K2_E5_SHIFT                           1
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1403_K2_E5                                                     0x008014UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1403_RESERVEDFIELD1279_K2_E5                                 (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1403_RESERVEDFIELD1279_K2_E5_SHIFT                           2
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1404_K2_E5                                                     0x008018UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1404_RESERVEDFIELD1280_K2_E5                                 (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1404_RESERVEDFIELD1280_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1405_K2_E5                                                     0x008040UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1405_RESERVEDFIELD1281_K2_E5                                 (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1405_RESERVEDFIELD1281_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1405_RESERVEDFIELD1282_K2_E5                                 (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1405_RESERVEDFIELD1282_K2_E5_SHIFT                           4
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1405_RESERVEDFIELD1283_K2_E5                                 (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1405_RESERVEDFIELD1283_K2_E5_SHIFT                           6
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1406_K2_E5                                                     0x008048UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1406_RESERVEDFIELD1284_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1406_RESERVEDFIELD1284_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1406_RESERVEDFIELD1285_K2_E5                                 (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1406_RESERVEDFIELD1285_K2_E5_SHIFT                           2
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1407_K2_E5                                                     0x00804cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1407_RESERVEDFIELD1286_K2_E5                                 (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1407_RESERVEDFIELD1286_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1408_K2_E5                                                     0x008050UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1408_RESERVEDFIELD1287_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1408_RESERVEDFIELD1287_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1408_RESERVEDFIELD1288_K2_E5                                 (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1408_RESERVEDFIELD1288_K2_E5_SHIFT                           2
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1409_K2_E5                                                     0x008058UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1409_RESERVEDFIELD1289_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1409_RESERVEDFIELD1289_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1409_RESERVEDFIELD1290_K2_E5                                 (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1409_RESERVEDFIELD1290_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1410_K2_E5                                                     0x008064UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1410_RESERVEDFIELD1291_K2_E5                                 (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1410_RESERVEDFIELD1291_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1410_RESERVEDFIELD1292_K2_E5                                 (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1410_RESERVEDFIELD1292_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1411_K2_E5                                                     0x00806cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1411_RESERVEDFIELD1293_K2_E5                                 (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1411_RESERVEDFIELD1293_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1411_RESERVEDFIELD1294_K2_E5                                 (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1411_RESERVEDFIELD1294_K2_E5_SHIFT                           3
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1411_RESERVEDFIELD1295_K2_E5                                 (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1411_RESERVEDFIELD1295_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1412_K2_E5                                                     0x008070UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1412_RESERVEDFIELD1296_K2_E5                                 (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1412_RESERVEDFIELD1296_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1413_K2_E5                                                     0x008078UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1413_RESERVEDFIELD1297_K2_E5                                 (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1413_RESERVEDFIELD1297_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN1_TOP_DPL_TXDP_CTRL1_K2_E5                                                           0x008088UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_EN_K2_E5                                     (0x1<<0) // Enables register control of TX data path mux in DPL
+  #define PHY_NW_IP_REG_LN1_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_EN_K2_E5_SHIFT                               0
+  #define PHY_NW_IP_REG_LN1_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_VAL_K2_E5                                    (0x7<<1) // Select value for TX data path mux in DPL.  The corresponding mux select override enable must also be set. 0 : TX data from customer logics 1: RX data for Far-End-Digital FED loopback 2: BIST generator 3: AN/802.3 4: LT/802.3 5-7: reserved
+  #define PHY_NW_IP_REG_LN1_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_VAL_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_LN1_TOP_DPL_TXDP_CTRL1_TXPOLARITY_K2_E5                                              (0x1<<4) // TX data polarity control
+  #define PHY_NW_IP_REG_LN1_TOP_DPL_TXDP_CTRL1_TXPOLARITY_K2_E5_SHIFT                                        4
+  #define PHY_NW_IP_REG_LN1_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_K2_E5                                   (0x1<<5) // Controls tx_en for Far-End-Digital FED loopback mode.  In FED loopback mode, tx_en will be set when this field is set to 1 and rxvalid is 1.
+  #define PHY_NW_IP_REG_LN1_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_K2_E5_SHIFT                             5
+#define PHY_NW_IP_REG_LN1_TOP_DPL_RXDP_CTRL1_K2_E5                                                           0x008090UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_K2_E5                                             (0x1<<0) // A mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
+  #define PHY_NW_IP_REG_LN1_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_K2_E5_SHIFT                                       0
+  #define PHY_NW_IP_REG_LN1_TOP_DPL_RXDP_CTRL1_BIT_STRIP_EVEN_K2_E5                                          (0x1<<1) // A bit stripping selection for RX data path in the DPL 1: Even bits stripped from RX data 0: Odd bits stripped from Rx data
+  #define PHY_NW_IP_REG_LN1_TOP_DPL_RXDP_CTRL1_BIT_STRIP_EVEN_K2_E5_SHIFT                                    1
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1414_K2_E5                                                     0x008094UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1414_RESERVEDFIELD1298_K2_E5                                 (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1414_RESERVEDFIELD1298_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1414_RESERVEDFIELD1299_K2_E5                                 (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1414_RESERVEDFIELD1299_K2_E5_SHIFT                           3
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1415_K2_E5                                                     0x008098UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1415_RESERVEDFIELD1300_K2_E5                                 (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1415_RESERVEDFIELD1300_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1415_RESERVEDFIELD1301_K2_E5                                 (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1415_RESERVEDFIELD1301_K2_E5_SHIFT                           3
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1415_RESERVEDFIELD1302_K2_E5                                 (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1415_RESERVEDFIELD1302_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN1_TOP_PHY_IF_STATUS_K2_E5                                                            0x00809cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_PHY_IF_STATUS_LN_OK_K2_E5                                                    (0x1<<0) // LANE OK status
+  #define PHY_NW_IP_REG_LN1_TOP_PHY_IF_STATUS_LN_OK_K2_E5_SHIFT                                              0
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1416_K2_E5                                                     0x0080c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1416_RESERVEDFIELD1303_K2_E5                                 (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1416_RESERVEDFIELD1303_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1416_RESERVEDFIELD1304_K2_E5                                 (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1416_RESERVEDFIELD1304_K2_E5_SHIFT                           3
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1417_K2_E5                                                     0x0080c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1417_RESERVEDFIELD1305_K2_E5                                 (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1417_RESERVEDFIELD1305_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1417_RESERVEDFIELD1306_K2_E5                                 (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1417_RESERVEDFIELD1306_K2_E5_SHIFT                           3
+#define PHY_NW_IP_REG_LN1_TOP_LN_STAT_CTRL0_K2_E5                                                            0x0080e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_LN_STAT_CTRL0_RXVALID_K2_E5                                                  (0x1<<0) // rxvalid status output
+  #define PHY_NW_IP_REG_LN1_TOP_LN_STAT_CTRL0_RXVALID_K2_E5_SHIFT                                            0
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1418_K2_E5                                                     0x0080e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1418_RESERVEDFIELD1307_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1418_RESERVEDFIELD1307_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1418_RESERVEDFIELD1308_K2_E5                                 (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1418_RESERVEDFIELD1308_K2_E5_SHIFT                           1
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1419_K2_E5                                                     0x0080e8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1419_RESERVEDFIELD1309_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1419_RESERVEDFIELD1309_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN1_TOP_LN_CTRL_OVR0_K2_E5                                                             0x0080ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_LN_CTRL_OVR0_OVR_EN_K2_E5                                                    (0x1<<0) // override enable for lnX_ctrl_*_i signals in this register
+  #define PHY_NW_IP_REG_LN1_TOP_LN_CTRL_OVR0_OVR_EN_K2_E5_SHIFT                                              0
+  #define PHY_NW_IP_REG_LN1_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_K2_E5                                             (0x7<<1) // lnX_data_width_i override value for TX.  It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-quarter width 10b, others, reserved.
+  #define PHY_NW_IP_REG_LN1_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_K2_E5_SHIFT                                       1
+  #define PHY_NW_IP_REG_LN1_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_K2_E5                                             (0x7<<4) // lnX_data_width_i override value for RX.  It takes effect when ovr_en is 1.
+  #define PHY_NW_IP_REG_LN1_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_K2_E5_SHIFT                                       4
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1420_K2_E5                                                     0x0080f0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1420_RESERVEDFIELD1310_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1420_RESERVEDFIELD1310_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1420_RESERVEDFIELD1311_K2_E5                                 (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1420_RESERVEDFIELD1311_K2_E5_SHIFT                           3
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1420_RESERVEDFIELD1312_K2_E5                                 (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1420_RESERVEDFIELD1312_K2_E5_SHIFT                           4
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1420_RESERVEDFIELD1313_K2_E5                                 (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1420_RESERVEDFIELD1313_K2_E5_SHIFT                           5
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1421_K2_E5                                                     0x0080f4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1421_RESERVEDFIELD1314_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1421_RESERVEDFIELD1314_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1421_RESERVEDFIELD1315_K2_E5                                 (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1421_RESERVEDFIELD1315_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1422_K2_E5                                                     0x0080f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1422_RESERVEDFIELD1316_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1422_RESERVEDFIELD1316_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1422_RESERVEDFIELD1317_K2_E5                                 (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1422_RESERVEDFIELD1317_K2_E5_SHIFT                           5
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1422_RESERVEDFIELD1318_K2_E5                                 (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1422_RESERVEDFIELD1318_K2_E5_SHIFT                           6
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1423_K2_E5                                                     0x0080fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1423_RESERVEDFIELD1319_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1423_RESERVEDFIELD1319_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1423_RESERVEDFIELD1320_K2_E5                                 (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1423_RESERVEDFIELD1320_K2_E5_SHIFT                           1
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1423_RESERVEDFIELD1321_K2_E5                                 (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1423_RESERVEDFIELD1321_K2_E5_SHIFT                           3
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1424_K2_E5                                                     0x008100UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1424_RESERVEDFIELD1322_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1424_RESERVEDFIELD1322_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1424_RESERVEDFIELD1323_K2_E5                                 (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1424_RESERVEDFIELD1323_K2_E5_SHIFT                           1
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1424_RESERVEDFIELD1324_K2_E5                                 (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1424_RESERVEDFIELD1324_K2_E5_SHIFT                           2
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1425_K2_E5                                                     0x008108UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1425_RESERVEDFIELD1325_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1425_RESERVEDFIELD1325_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1425_RESERVEDFIELD1326_K2_E5                                 (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1425_RESERVEDFIELD1326_K2_E5_SHIFT                           1
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1426_K2_E5                                                     0x00810cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1426_RESERVEDFIELD1327_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1426_RESERVEDFIELD1327_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1426_RESERVEDFIELD1328_K2_E5                                 (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1426_RESERVEDFIELD1328_K2_E5_SHIFT                           1
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1427_K2_E5                                                     0x008120UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1427_RESERVEDFIELD1329_K2_E5                                 (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1427_RESERVEDFIELD1329_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1427_RESERVEDFIELD1330_K2_E5                                 (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1427_RESERVEDFIELD1330_K2_E5_SHIFT                           3
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1427_RESERVEDFIELD1331_K2_E5                                 (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1427_RESERVEDFIELD1331_K2_E5_SHIFT                           6
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1427_RESERVEDFIELD1332_K2_E5                                 (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1427_RESERVEDFIELD1332_K2_E5_SHIFT                           7
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1428_K2_E5                                                     0x008124UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1428_RESERVEDFIELD1333_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1428_RESERVEDFIELD1333_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1428_RESERVEDFIELD1334_K2_E5                                 (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1428_RESERVEDFIELD1334_K2_E5_SHIFT                           1
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1428_RESERVEDFIELD1335_K2_E5                                 (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1428_RESERVEDFIELD1335_K2_E5_SHIFT                           2
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1428_RESERVEDFIELD1336_K2_E5                                 (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1428_RESERVEDFIELD1336_K2_E5_SHIFT                           4
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1428_RESERVEDFIELD1337_K2_E5                                 (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1428_RESERVEDFIELD1337_K2_E5_SHIFT                           5
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1428_RESERVEDFIELD1338_K2_E5                                 (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1428_RESERVEDFIELD1338_K2_E5_SHIFT                           6
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1429_K2_E5                                                     0x008128UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1429_RESERVEDFIELD1339_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1429_RESERVEDFIELD1339_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1430_K2_E5                                                     0x00812cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1430_RESERVEDFIELD1340_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1430_RESERVEDFIELD1340_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1431_K2_E5                                                     0x008130UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1431_RESERVEDFIELD1341_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1431_RESERVEDFIELD1341_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1431_RESERVEDFIELD1342_K2_E5                                 (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1431_RESERVEDFIELD1342_K2_E5_SHIFT                           1
+#define PHY_NW_IP_REG_LN1_TOP_ERR_CTRL1_K2_E5                                                                0x008140UL //Access:RW   DataWidth:0x8    // lower 8-bits of 16-bit lane error code.  0x0 - indicates that there is no error rest - reserved
+#define PHY_NW_IP_REG_LN1_TOP_ERR_CTRL2_K2_E5                                                                0x008144UL //Access:RW   DataWidth:0x8    // higher 8-bits of 16-bit lane error code.  0x0 - indicates that there is no error rest - reserved
+#define PHY_NW_IP_REG_LN1_TOP_ERR_CTRL3_K2_E5                                                                0x008148UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_TOP_ERR_CTRL3_LANE_ERR_K2_E5                                                     (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macro has an internal error detected by firmware. Lane error code can be used to isolate error event.
+  #define PHY_NW_IP_REG_LN1_TOP_ERR_CTRL3_LANE_ERR_K2_E5_SHIFT                                               0
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1432_K2_E5                                               0x008240UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1432_RESERVEDFIELD1343_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1432_RESERVEDFIELD1343_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1433_K2_E5                                               0x008244UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1433_RESERVEDFIELD1344_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1433_RESERVEDFIELD1344_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1434_K2_E5                                               0x008284UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1434_RESERVEDFIELD1345_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1434_RESERVEDFIELD1345_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1434_RESERVEDFIELD1346_K2_E5                           (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1434_RESERVEDFIELD1346_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1435_K2_E5                                               0x008288UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1435_RESERVEDFIELD1347_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1435_RESERVEDFIELD1347_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1436_K2_E5                                               0x008298UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1437_K2_E5                                               0x00829cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1437_RESERVEDFIELD1349_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1437_RESERVEDFIELD1349_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1438_K2_E5                                               0x0082a0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1439_K2_E5                                               0x0082a4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1439_RESERVEDFIELD1351_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1439_RESERVEDFIELD1351_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1440_K2_E5                                               0x0082a8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1441_K2_E5                                               0x0082acUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1441_RESERVEDFIELD1353_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1441_RESERVEDFIELD1353_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1442_K2_E5                                               0x0082b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1442_RESERVEDFIELD1354_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1442_RESERVEDFIELD1354_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1443_K2_E5                                               0x0082c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1443_RESERVEDFIELD1355_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1443_RESERVEDFIELD1355_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1444_K2_E5                                               0x0082c4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1445_K2_E5                                               0x0082c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1445_RESERVEDFIELD1357_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1445_RESERVEDFIELD1357_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1446_K2_E5                                               0x0082d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1446_RESERVEDFIELD1358_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1446_RESERVEDFIELD1358_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1447_K2_E5                                               0x0082d8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1448_K2_E5                                               0x0082dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1448_RESERVEDFIELD1360_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1448_RESERVEDFIELD1360_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1449_K2_E5                                               0x0082e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1449_RESERVEDFIELD1361_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1449_RESERVEDFIELD1361_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1450_K2_E5                                               0x0082e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1450_RESERVEDFIELD1362_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1450_RESERVEDFIELD1362_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1450_RESERVEDFIELD1363_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1450_RESERVEDFIELD1363_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1450_RESERVEDFIELD1364_K2_E5                           (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1450_RESERVEDFIELD1364_K2_E5_SHIFT                     2
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1450_RESERVEDFIELD1365_K2_E5                           (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1450_RESERVEDFIELD1365_K2_E5_SHIFT                     3
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1451_K2_E5                                               0x0082ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1451_RESERVEDFIELD1366_K2_E5                           (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1451_RESERVEDFIELD1366_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1452_K2_E5                                               0x0082f0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1452_RESERVEDFIELD1367_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1452_RESERVEDFIELD1367_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1453_K2_E5                                               0x0082f4UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1454_K2_E5                                               0x0082f8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1454_RESERVEDFIELD1369_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1454_RESERVEDFIELD1369_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS2_K2_E5                                                       0x0082fcUL //Access:R    DataWidth:0x8    // Binary-coded DLPF control input to the CDR
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS3_K2_E5                                                       0x008300UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8_K2_E5                                        (0x1<<0) // Binary-coded DLPF control input to the CDR
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8_K2_E5_SHIFT                                  0
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS4_K2_E5                                                       0x008304UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH_K2_E5                                       (0x1<<0) // Indicates that DLPF control input to CDR is too high
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW_K2_E5                                        (0x1<<1) // Indicates that DLPF control input to CDR is too low
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW_K2_E5_SHIFT                                  1
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST_K2_E5                                           (0x1<<2) // CDR loss of lock indicator.  1 means lock has been lost. Once lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by setting set lock_en_i to 0.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST_K2_E5_SHIFT                                     2
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS5_K2_E5                                                       0x008310UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS5_LOCKED_K2_E5                                              (0x1<<0) // CDR lock indicator.  1 means lock is achieved. It is cleared when lock detector is disabled by setting set lock_en_i to 0.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS5_LOCKED_K2_E5_SHIFT                                        0
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_INTEGRAL_STATUS0_K2_E5                                                   0x008314UL //Access:R    DataWidth:0x8    // Value of the accumulator in the CDR integral path
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_INTEGRAL_STATUS1_K2_E5                                                   0x008318UL //Access:R    DataWidth:0x8    // Value of the accumulator in the CDR integral path
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_INTEGRAL_STATUS2_K2_E5                                                   0x008320UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_INTEGRAL_STATUS2_ACCUMULATOR_19_16_K2_E5                               (0xf<<0) // Value of the accumulator in the CDR integral path
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_INTEGRAL_STATUS2_ACCUMULATOR_19_16_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1455_K2_E5                                               0x008324UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1455_RESERVEDFIELD1370_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1455_RESERVEDFIELD1370_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1455_RESERVEDFIELD1371_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1455_RESERVEDFIELD1371_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1456_K2_E5                                               0x008328UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1457_K2_E5                                               0x00832cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1458_K2_E5                                               0x008330UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1459_K2_E5                                               0x008334UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1459_RESERVEDFIELD1375_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1459_RESERVEDFIELD1375_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1459_RESERVEDFIELD1376_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1459_RESERVEDFIELD1376_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1460_K2_E5                                               0x008338UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1461_K2_E5                                               0x00833cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1462_K2_E5                                               0x008380UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1463_K2_E5                                               0x008384UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1463_RESERVEDFIELD1380_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1463_RESERVEDFIELD1380_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1464_K2_E5                                               0x008388UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1464_RESERVEDFIELD1381_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1464_RESERVEDFIELD1381_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1464_RESERVEDFIELD1382_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1464_RESERVEDFIELD1382_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1465_K2_E5                                               0x00838cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1466_K2_E5                                               0x0083a0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1467_K2_E5                                               0x0083a4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1467_RESERVEDFIELD1385_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1467_RESERVEDFIELD1385_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1467_RESERVEDFIELD1386_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1467_RESERVEDFIELD1386_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1467_RESERVEDFIELD1387_K2_E5                           (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1467_RESERVEDFIELD1387_K2_E5_SHIFT                     2
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1468_K2_E5                                               0x0083a8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1469_K2_E5                                               0x0083acUL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1470_K2_E5                                               0x0083b0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1470_RESERVEDFIELD1390_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1470_RESERVEDFIELD1390_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1471_K2_E5                                               0x0083b4UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1472_K2_E5                                               0x0083b8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1473_K2_E5                                               0x0083bcUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1473_RESERVEDFIELD1393_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1473_RESERVEDFIELD1393_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1474_K2_E5                                               0x0083c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1474_RESERVEDFIELD1394_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1474_RESERVEDFIELD1394_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1475_K2_E5                                              0x008400UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1475_RESERVEDFIELD1395_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1475_RESERVEDFIELD1395_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1475_RESERVEDFIELD1396_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1475_RESERVEDFIELD1396_K2_E5_SHIFT                    3
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1475_RESERVEDFIELD1397_K2_E5                          (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1475_RESERVEDFIELD1397_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1476_K2_E5                                              0x008404UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1476_RESERVEDFIELD1398_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1476_RESERVEDFIELD1398_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1477_K2_E5                                              0x008410UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1477_RESERVEDFIELD1399_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1477_RESERVEDFIELD1399_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1478_K2_E5                                              0x008418UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1479_K2_E5                                              0x008428UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1479_RESERVEDFIELD1401_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1479_RESERVEDFIELD1401_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1480_K2_E5                                              0x00842cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1480_RESERVEDFIELD1402_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1480_RESERVEDFIELD1402_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1480_RESERVEDFIELD1403_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1480_RESERVEDFIELD1403_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1480_RESERVEDFIELD1404_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1480_RESERVEDFIELD1404_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1481_K2_E5                                              0x008430UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1481_RESERVEDFIELD1405_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1481_RESERVEDFIELD1405_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1482_K2_E5                                              0x008440UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1482_RESERVEDFIELD1406_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1482_RESERVEDFIELD1406_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1482_RESERVEDFIELD1407_K2_E5                          (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1482_RESERVEDFIELD1407_K2_E5_SHIFT                    5
+#define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1483_K2_E5                                              0x008444UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1483_RESERVEDFIELD1408_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1483_RESERVEDFIELD1408_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1483_RESERVEDFIELD1409_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1483_RESERVEDFIELD1409_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1483_RESERVEDFIELD1410_K2_E5                          (0xf<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1483_RESERVEDFIELD1410_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1484_K2_E5                                              0x008460UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1484_RESERVEDFIELD1411_K2_E5                          (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1484_RESERVEDFIELD1411_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1484_RESERVEDFIELD1412_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1484_RESERVEDFIELD1412_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1485_K2_E5                                              0x008464UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1485_RESERVEDFIELD1413_K2_E5                          (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1485_RESERVEDFIELD1413_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1485_RESERVEDFIELD1414_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1485_RESERVEDFIELD1414_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1486_K2_E5                                              0x008468UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1486_RESERVEDFIELD1415_K2_E5                          (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1486_RESERVEDFIELD1415_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1487_K2_E5                                              0x00846cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1487_RESERVEDFIELD1416_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1487_RESERVEDFIELD1416_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1487_RESERVEDFIELD1417_K2_E5                          (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1487_RESERVEDFIELD1417_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1488_K2_E5                                              0x008480UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1488_RESERVEDFIELD1418_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1488_RESERVEDFIELD1418_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1488_RESERVEDFIELD1419_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1488_RESERVEDFIELD1419_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1489_K2_E5                                              0x008484UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1489_RESERVEDFIELD1420_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1489_RESERVEDFIELD1420_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1490_K2_E5                                              0x008488UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1491_K2_E5                                              0x00848cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1492_K2_E5                                              0x008490UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1493_K2_E5                                              0x008494UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1493_RESERVEDFIELD1424_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1493_RESERVEDFIELD1424_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1494_K2_E5                                              0x0084c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1494_RESERVEDFIELD1425_K2_E5                          (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1494_RESERVEDFIELD1425_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1495_K2_E5                                                    0x008600UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1495_RESERVEDFIELD1426_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1495_RESERVEDFIELD1426_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1495_RESERVEDFIELD1427_K2_E5                                (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1495_RESERVEDFIELD1427_K2_E5_SHIFT                          1
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1496_K2_E5                                                    0x008604UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1497_K2_E5                                                    0x008608UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1498_K2_E5                                                    0x00860cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1498_RESERVEDFIELD1430_K2_E5                                (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1498_RESERVEDFIELD1430_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1498_RESERVEDFIELD1431_K2_E5                                (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1498_RESERVEDFIELD1431_K2_E5_SHIFT                          4
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1499_K2_E5                                                    0x008610UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1500_K2_E5                                                    0x008614UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1500_RESERVEDFIELD1433_K2_E5                                (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1500_RESERVEDFIELD1433_K2_E5_SHIFT                          0
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1501_K2_E5                                                    0x008618UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1501_RESERVEDFIELD1434_K2_E5                                (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1501_RESERVEDFIELD1434_K2_E5_SHIFT                          0
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1502_K2_E5                                                    0x00861cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1502_RESERVEDFIELD1435_K2_E5                                (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1502_RESERVEDFIELD1435_K2_E5_SHIFT                          0
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1503_K2_E5                                                    0x008620UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1504_K2_E5                                                    0x008624UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1504_RESERVEDFIELD1437_K2_E5                                (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1504_RESERVEDFIELD1437_K2_E5_SHIFT                          0
+#define PHY_NW_IP_REG_LN1_ANEG_CFG10_K2_E5                                                                   0x008628UL //Access:RW   DataWidth:0x8    // Seed provided to the transmit nonce generator polynomial
+#define PHY_NW_IP_REG_LN1_ANEG_CFG11_K2_E5                                                                   0x00862cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_CFG11_PSEUDO_SEL_K2_E5                                                      (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
+  #define PHY_NW_IP_REG_LN1_ANEG_CFG11_PSEUDO_SEL_K2_E5_SHIFT                                                0
+#define PHY_NW_IP_REG_LN1_ANEG_CTRL0_K2_E5                                                                   0x008630UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_CTRL0_AUTONEG_RESTART_K2_E5                                                 (0x1<<0) // Restarts AN that is already in progress or otherwise completed.  Reset is triggered by rising edge of this signal.  Not self clearing.
+  #define PHY_NW_IP_REG_LN1_ANEG_CTRL0_AUTONEG_RESTART_K2_E5_SHIFT                                           0
+  #define PHY_NW_IP_REG_LN1_ANEG_CTRL0_RESERVEDFIELD1438_K2_E5                                               (0x7f<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_CTRL0_RESERVEDFIELD1438_K2_E5_SHIFT                                         1
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1505_K2_E5                                                    0x008634UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1505_RESERVEDFIELD1439_K2_E5                                (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1505_RESERVEDFIELD1439_K2_E5_SHIFT                          4
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1505_RESERVEDFIELD1440_K2_E5                                (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1505_RESERVEDFIELD1440_K2_E5_SHIFT                          5
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1505_RESERVEDFIELD1441_K2_E5                                (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1505_RESERVEDFIELD1441_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1506_K2_E5                                                    0x008638UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1506_RESERVEDFIELD1442_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1506_RESERVEDFIELD1442_K2_E5_SHIFT                          0
+#define PHY_NW_IP_REG_LN1_ANEG_STATUS0_K2_E5                                                                 0x008640UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_LP_AUTONEG_ABLE_K2_E5                                               (0x1<<0) // The link partner Auto-Negotiation ability bit shall be set to one to indicate that the link partner is able to participate in the Auto-Negotiation function. This bit shall be reset to zero if the link partner is not Auto- Negotiation able.
+  #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_LP_AUTONEG_ABLE_K2_E5_SHIFT                                         0
+  #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_LINK_STATUS_K2_E5                                                   (0x1<<2) // Local link Status.  When read as a one, it indicates that the PMA/PMD has determined that a valid link has been established i.e. link_status[HDC] equals OK. When read as a zero, it indicates that the link is not valid.
+  #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_LINK_STATUS_K2_E5_SHIFT                                             2
+  #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_AUTONEG_ABILITY_K2_E5                                               (0x1<<3) // Autoneg ability.  When read as a one, it indicates that the PMA/PMD has the ability to perform Auto-Negotiation.  When read as a zero, it indicates that the PMA/PMD lacks the ability to perform Auto-Negotiation.
+  #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_AUTONEG_ABILITY_K2_E5_SHIFT                                         3
+  #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_AUTONEG_REMOTE_FAULT_K2_E5                                          (0x1<<4) // Remote Fault
+  #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_AUTONEG_REMOTE_FAULT_K2_E5_SHIFT                                    4
+  #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_AUTONEG_COMPLETE_K2_E5                                              (0x1<<5) // Autoneg has completed and autoneg arbitration FSM is in AN GOOD state.
+  #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_AUTONEG_COMPLETE_K2_E5_SHIFT                                        5
+#define PHY_NW_IP_REG_LN1_ANEG_STATUS1_K2_E5                                                                 0x008644UL //Access:W    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_PAGE_RX_K2_E5                                                       (0x1<<0) // Page Received.   To clear it, write 1 to it.
+  #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_PAGE_RX_K2_E5_SHIFT                                                 0
+  #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_AN_LINK_GOOD_K2_E5                                                  (0x1<<1) // Autoneg has completed and autoneg arbitration FSM is in either AN GOOD CHECK or AN GOOD state.
+  #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_AN_LINK_GOOD_K2_E5_SHIFT                                            1
+  #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_PARALLEL_DET_FAULT_K2_E5                                            (0x1<<2) // Autoneg Parallel Detection Fault.  Write 1 to clear it.
+  #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_PARALLEL_DET_FAULT_K2_E5_SHIFT                                      2
+  #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_NP_LOADED_K2_E5                                                     (0x1<<3) // mr_np_loaded status.
+  #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_NP_LOADED_K2_E5_SHIFT                                               3
+  #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_RESERVEDFIELD1443_K2_E5                                             (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_RESERVEDFIELD1443_K2_E5_SHIFT                                       4
+  #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_RESERVEDFIELD1444_K2_E5                                             (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_RESERVEDFIELD1444_K2_E5_SHIFT                                       5
+#define PHY_NW_IP_REG_LN1_ANEG_STATUS_DBG0_K2_E5                                                             0x008650UL //Access:R    DataWidth:0x8    // One-hot sticky capture of AN FSM states.  Bits 7-0
+#define PHY_NW_IP_REG_LN1_ANEG_STATUS_DBG1_K2_E5                                                             0x008654UL //Access:R    DataWidth:0x8    // One-hot sticky capture of AN FSM states.  Bits 15-8
+#define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE0_K2_E5                                                              0x008660UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE0_SELECTOR_K2_E5                                                   (0x1f<<0) // technology Select Field
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE0_SELECTOR_K2_E5_SHIFT                                             0
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE0_ECHOED_NONCE_2_0_K2_E5                                           (0x7<<5) // Echoed Nonce Field bits 2-0.  AN controller generates it.
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE0_ECHOED_NONCE_2_0_K2_E5_SHIFT                                     5
+#define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_K2_E5                                                              0x008664UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_ECHOED_NONCE_4_3_K2_E5                                           (0x3<<0) // Echoed Nonce Field bits 4-3.    AN controller generates it.
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_ECHOED_NONCE_4_3_K2_E5_SHIFT                                     0
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_PAUSE_K2_E5                                                      (0x1<<2) // Pause advertised ability
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_PAUSE_K2_E5_SHIFT                                                2
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_ASM_DIR_K2_E5                                                    (0x1<<3) // Pause ASM_DIR advertised ability
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_ASM_DIR_K2_E5_SHIFT                                              3
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_C2_K2_E5                                                         (0x1<<4) // Reserved always 0
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_C2_K2_E5_SHIFT                                                   4
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_REMOTE_FAULT_K2_E5                                               (0x1<<5) // Remote Fault Local Device
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_REMOTE_FAULT_K2_E5_SHIFT                                         5
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_NEXT_PAGE_K2_E5                                                  (0x1<<7) // Next Page
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_NEXT_PAGE_K2_E5_SHIFT                                            7
+#define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE2_K2_E5                                                              0x008668UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE2_TX_NONCE_K2_E5                                                   (0x1f<<0) // Transmitted Nonce Field.  It is generated in hardware.
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE2_TX_NONCE_K2_E5_SHIFT                                             0
+#define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_K2_E5                                                         0x00866cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_1G_KX_K2_E5                                         (0x1<<0) // 1000Base-KX technology advertised ability
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_1G_KX_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KX4_K2_E5                                       (0x1<<1) // 10GBase-KX4 technology advertised ability
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KX4_K2_E5_SHIFT                                 1
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KR_K2_E5                                        (0x1<<2) // 10GBase-KR technology advertised ability
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KR_K2_E5_SHIFT                                  2
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_40G_KR4_K2_E5                                       (0x1<<3) // 40GBase-KR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_40G_KR4_K2_E5_SHIFT                                 3
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_40G_CR4_K2_E5                                       (0x1<<4) // 40GBase-CR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_40G_CR4_K2_E5_SHIFT                                 4
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_100G_CR10_K2_E5                                     (0x1<<5) // 100GBase-CR10 technology advertised ability
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_100G_CR10_K2_E5_SHIFT                               5
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KP4_K2_E5                                      (0x1<<6) // 100GBase-KP4 technology advertised ability
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KP4_K2_E5_SHIFT                                6
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KR4_K2_E5                                      (0x1<<7) // 100GBase-KR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KR4_K2_E5_SHIFT                                7
+#define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH1_K2_E5                                                         0x008670UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH1_ABILITY_100G_CR4_K2_E5                                      (0x1<<0) // 100GBase-CR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH1_ABILITY_100G_CR4_K2_E5_SHIFT                                0
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_S_K2_E5                                      (0x1<<1) // 25GBase-GR-S KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A9 in base page.
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_S_K2_E5_SHIFT                                1
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_K2_E5                                        (0x1<<2) // 25GBase-GR KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A10 in base page.
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_K2_E5_SHIFT                                  2
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH1_ABILITY_A15_A11_K2_E5                                       (0x1f<<3) // technology advertised ability Field A15-A11
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH1_ABILITY_A15_A11_K2_E5_SHIFT                                 3
+#define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH2_K2_E5                                                         0x008674UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH2_ABILITY_A22_A16_K2_E5                                       (0x7f<<0) // technology advertised ability Field A22-A16
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH2_ABILITY_A22_A16_K2_E5_SHIFT                                 0
+#define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_K2_E5                                                           0x008678UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_FEC_ABILITY_K2_E5                                             (0x1<<0) // base page bit F0.  It advertises FEC ability
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_FEC_ABILITY_K2_E5_SHIFT                                       0
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_FEC_REQ_K2_E5                                                 (0x1<<1) // base page bit F1.  It requests FEC to be turned on when supported at the both ends of link
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_FEC_REQ_K2_E5_SHIFT                                           1
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_RS_FEC_REQ_25G_K2_E5                                          (0x1<<2) // base page bit F2.  It requests RS-FEC for 25G-GR 25G-KR/-CR link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A23 in base page.
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_RS_FEC_REQ_25G_K2_E5_SHIFT                                    2
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_FC_FEC_REQ_25G_K2_E5                                          (0x1<<3) // base page bit F3.  It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A24 in base page.
+  #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_FC_FEC_REQ_25G_K2_E5_SHIFT                                    3
+#define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_K2_E5                                                               0x00867cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_ABILITY_25G_KR_K2_E5                                              (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_ABILITY_25G_KR_K2_E5_SHIFT                                        0
+  #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_ABILITY_25G_CR_K2_E5                                              (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_ABILITY_25G_CR_K2_E5_SHIFT                                        1
+  #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_ABILITY_50G_KR2_K2_E5                                             (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_ABILITY_50G_KR2_K2_E5_SHIFT                                       2
+  #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_ABILITY_50G_CR2_K2_E5                                             (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_ABILITY_50G_CR2_K2_E5_SHIFT                                       3
+  #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_RS_FEC_ABILITY_K2_E5                                              (0x1<<4) // Extended advertised FEC field 0.  It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_RS_FEC_ABILITY_K2_E5_SHIFT                                        4
+  #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_FC_FEC_ABILITY_K2_E5                                              (0x1<<5) // Extended advertised FEC field 1.  It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_FC_FEC_ABILITY_K2_E5_SHIFT                                        5
+  #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_RS_FEC_REQ_K2_E5                                                  (0x1<<6) // Extended advertised FEC field 2.  It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_RS_FEC_REQ_K2_E5_SHIFT                                            6
+  #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_FC_FEC_REQ_K2_E5                                                  (0x1<<7) // Extended advertised FEC field 3.  It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_FC_FEC_REQ_K2_E5_SHIFT                                            7
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1507_K2_E5                                                    0x008680UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1508_K2_E5                                                    0x008684UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1508_RESERVEDFIELD1445_K2_E5                                (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1508_RESERVEDFIELD1445_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1508_RESERVEDFIELD1446_K2_E5                                (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1508_RESERVEDFIELD1446_K2_E5_SHIFT                          3
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1508_RESERVEDFIELD1447_K2_E5                                (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1508_RESERVEDFIELD1447_K2_E5_SHIFT                          4
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1508_RESERVEDFIELD1448_K2_E5                                (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1508_RESERVEDFIELD1448_K2_E5_SHIFT                          5
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1508_RESERVEDFIELD1449_K2_E5                                (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1508_RESERVEDFIELD1449_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1509_K2_E5                                                    0x008688UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1510_K2_E5                                                    0x00868cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1511_K2_E5                                                    0x008690UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1512_K2_E5                                                    0x008694UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_K2_E5                                                    0x008698UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1450_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1450_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1451_K2_E5                                (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1451_K2_E5_SHIFT                          1
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1452_K2_E5                                (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1452_K2_E5_SHIFT                          2
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1453_K2_E5                                (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1453_K2_E5_SHIFT                          3
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1454_K2_E5                                (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1454_K2_E5_SHIFT                          4
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1455_K2_E5                                (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1455_K2_E5_SHIFT                          5
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1456_K2_E5                                (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1456_K2_E5_SHIFT                          6
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1457_K2_E5                                (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1457_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1514_K2_E5                                                    0x00869cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1514_RESERVEDFIELD1458_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1514_RESERVEDFIELD1458_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1514_RESERVEDFIELD1459_K2_E5                                (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1514_RESERVEDFIELD1459_K2_E5_SHIFT                          1
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1514_RESERVEDFIELD1460_K2_E5                                (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1514_RESERVEDFIELD1460_K2_E5_SHIFT                          2
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1514_RESERVEDFIELD1461_K2_E5                                (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1514_RESERVEDFIELD1461_K2_E5_SHIFT                          3
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1514_RESERVEDFIELD1462_K2_E5                                (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1514_RESERVEDFIELD1462_K2_E5_SHIFT                          4
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1514_RESERVEDFIELD1463_K2_E5                                (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1514_RESERVEDFIELD1463_K2_E5_SHIFT                          5
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1514_RESERVEDFIELD1464_K2_E5                                (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1514_RESERVEDFIELD1464_K2_E5_SHIFT                          6
+#define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE0_K2_E5                                                           0x0086a0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE0_SELECTOR_K2_E5                                                (0x1f<<0) // Link partner technology Select Field
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE0_SELECTOR_K2_E5_SHIFT                                          0
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE0_ECHOED_NONCE_2_0_K2_E5                                        (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE0_ECHOED_NONCE_2_0_K2_E5_SHIFT                                  5
+#define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_K2_E5                                                           0x0086a4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_ECHOED_NONCE_4_3_K2_E5                                        (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_ECHOED_NONCE_4_3_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_PAUSE_K2_E5                                                   (0x1<<2) // Link partner Pause advertised ability
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_PAUSE_K2_E5_SHIFT                                             2
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_ASM_DIR_K2_E5                                                 (0x1<<3) // Link partner Pause ASM_DIR advertised ability
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_ASM_DIR_K2_E5_SHIFT                                           3
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_C2_K2_E5                                                      (0x1<<4) // Link partner C2 field always 0
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_C2_K2_E5_SHIFT                                                4
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_REMOTE_FAULT_K2_E5                                            (0x1<<5) // Link partner Remote Fault
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_REMOTE_FAULT_K2_E5_SHIFT                                      5
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_ACK_K2_E5                                                     (0x1<<6) // Link partner Acknowledge always 0
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_ACK_K2_E5_SHIFT                                               6
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_NEXT_PAGE_K2_E5                                               (0x1<<7) // Link partner Next Page
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_NEXT_PAGE_K2_E5_SHIFT                                         7
+#define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE2_K2_E5                                                           0x0086a8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE2_TX_NONCE_K2_E5                                                (0x1f<<0) // Transmitted Nonce Field from Link partner
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE2_TX_NONCE_K2_E5_SHIFT                                          0
+#define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_K2_E5                                                      0x0086acUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_1G_KX_K2_E5                                      (0x1<<0) // Link partner 1000Base-KX technology advertised ability
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_1G_KX_K2_E5_SHIFT                                0
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KX4_K2_E5                                    (0x1<<1) // Link partner 10GBase-KX4 technology advertised ability
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KX4_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KR_K2_E5                                     (0x1<<2) // Link partner 10GBase-KR technology advertised ability
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KR_K2_E5_SHIFT                               2
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_KR4_K2_E5                                    (0x1<<3) // Link partner 40GBase-KR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_KR4_K2_E5_SHIFT                              3
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_CR4_K2_E5                                    (0x1<<4) // Link partner 40GBase-CR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_CR4_K2_E5_SHIFT                              4
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_CR10_K2_E5                                  (0x1<<5) // Link partner 100GBase-CR10 technology advertised ability
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_CR10_K2_E5_SHIFT                            5
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KP4_K2_E5                                   (0x1<<6) // Link partner 100GBase-KP4 technology advertised ability
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KP4_K2_E5_SHIFT                             6
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KR4_K2_E5                                   (0x1<<7) // Link partner 100GBase-KR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KR4_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH1_K2_E5                                                      0x0086b0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH1_ABILITY_100G_CR4_K2_E5                                   (0x1<<0) // Link partner 100GBase-CR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH1_ABILITY_100G_CR4_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_S_K2_E5                                   (0x1<<1) // Link partner 25GBase-GR-S KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A9 in base page.
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_S_K2_E5_SHIFT                             1
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_K2_E5                                     (0x1<<2) // Link partner 25GBase-GR KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A10 in base page.
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_K2_E5_SHIFT                               2
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH1_ABILITY_A15_A11_K2_E5                                    (0x1f<<3) // Link partner technology advertised ability Field A15-A11
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH1_ABILITY_A15_A11_K2_E5_SHIFT                              3
+#define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH2_K2_E5                                                      0x0086b4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH2_ABILITY_A22_A16_K2_E5                                    (0x7f<<0) // Link partner technology advertised ability Field A22-A16
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH2_ABILITY_A22_A16_K2_E5_SHIFT                              0
+#define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_K2_E5                                                        0x0086b8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_FEC_ABILITY_K2_E5                                          (0x1<<0) // Link partner base page bit F0.  It advertises FEC ability
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_FEC_ABILITY_K2_E5_SHIFT                                    0
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_FEC_REQ_K2_E5                                              (0x1<<1) // Link partner base page bit F1.  It requests FEC to be turned on when supported at the both ends of link
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_FEC_REQ_K2_E5_SHIFT                                        1
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_RS_FEC_REQ_25G_K2_E5                                       (0x1<<2) // Link partner base page bit F2.  It requests RS-FEC for 25G-GR 25G-KR/-CR link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A23 in base page.
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_RS_FEC_REQ_25G_K2_E5_SHIFT                                 2
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_FC_FEC_REQ_25G_K2_E5                                       (0x1<<3) // Link partner base page bit F3.  It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A24 in base page.
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_FC_FEC_REQ_25G_K2_E5_SHIFT                                 3
+#define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_K2_E5                                                            0x0086bcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_ABILITY_25G_KR_K2_E5                                           (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_ABILITY_25G_KR_K2_E5_SHIFT                                     0
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_ABILITY_25G_CR_K2_E5                                           (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_ABILITY_25G_CR_K2_E5_SHIFT                                     1
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_ABILITY_50G_KR2_K2_E5                                          (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_ABILITY_50G_KR2_K2_E5_SHIFT                                    2
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_ABILITY_50G_CR2_K2_E5                                          (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_ABILITY_50G_CR2_K2_E5_SHIFT                                    3
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_RS_FEC_ABILITY_K2_E5                                           (0x1<<4) // Link partner extended advertised FEC field 0.  It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_RS_FEC_ABILITY_K2_E5_SHIFT                                     4
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_FC_FEC_ABILITY_K2_E5                                           (0x1<<5) // Link partner extended advertised FEC field 1.  It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_FC_FEC_ABILITY_K2_E5_SHIFT                                     5
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_RS_FEC_REQ_K2_E5                                               (0x1<<6) // Link partner extended advertised FEC field 2.  It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_RS_FEC_REQ_K2_E5_SHIFT                                         6
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_FC_FEC_REQ_K2_E5                                               (0x1<<7) // Link partner extended advertised FEC field 3.  It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_FC_FEC_REQ_K2_E5_SHIFT                                         7
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1515_K2_E5                                                    0x0086c0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1516_K2_E5                                                    0x0086c4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1516_RESERVEDFIELD1465_K2_E5                                (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1516_RESERVEDFIELD1465_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1516_RESERVEDFIELD1466_K2_E5                                (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1516_RESERVEDFIELD1466_K2_E5_SHIFT                          3
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1516_RESERVEDFIELD1467_K2_E5                                (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1516_RESERVEDFIELD1467_K2_E5_SHIFT                          4
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1516_RESERVEDFIELD1468_K2_E5                                (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1516_RESERVEDFIELD1468_K2_E5_SHIFT                          5
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1516_RESERVEDFIELD1469_K2_E5                                (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1516_RESERVEDFIELD1469_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1517_K2_E5                                                    0x0086c8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1518_K2_E5                                                    0x0086ccUL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1519_K2_E5                                                    0x0086d0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1520_K2_E5                                                    0x0086d4UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_K2_E5                                                    0x0086d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1470_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1470_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1471_K2_E5                                (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1471_K2_E5_SHIFT                          1
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1472_K2_E5                                (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1472_K2_E5_SHIFT                          2
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1473_K2_E5                                (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1473_K2_E5_SHIFT                          3
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1474_K2_E5                                (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1474_K2_E5_SHIFT                          4
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1475_K2_E5                                (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1475_K2_E5_SHIFT                          5
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1476_K2_E5                                (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1476_K2_E5_SHIFT                          6
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1477_K2_E5                                (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1477_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1522_K2_E5                                                    0x0086dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1522_RESERVEDFIELD1478_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1522_RESERVEDFIELD1478_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1522_RESERVEDFIELD1479_K2_E5                                (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1522_RESERVEDFIELD1479_K2_E5_SHIFT                          1
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1522_RESERVEDFIELD1480_K2_E5                                (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1522_RESERVEDFIELD1480_K2_E5_SHIFT                          2
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1522_RESERVEDFIELD1481_K2_E5                                (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1522_RESERVEDFIELD1481_K2_E5_SHIFT                          3
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1522_RESERVEDFIELD1482_K2_E5                                (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1522_RESERVEDFIELD1482_K2_E5_SHIFT                          4
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1522_RESERVEDFIELD1483_K2_E5                                (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1522_RESERVEDFIELD1483_K2_E5_SHIFT                          5
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1522_RESERVEDFIELD1484_K2_E5                                (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1522_RESERVEDFIELD1484_K2_E5_SHIFT                          6
+#define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_K2_E5                                                        0x0086e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_1G_KX_K2_E5                                        (0x1<<0) // Resolution result for 1000Base-KX.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_1G_KX_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_10G_KX4_K2_E5                                      (0x1<<1) // Resolution result for 10GBase-KX4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_10G_KX4_K2_E5_SHIFT                                1
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_10G_KR_K2_E5                                       (0x1<<2) // Resolution result for 10GBase-KR.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_10G_KR_K2_E5_SHIFT                                 2
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_40G_KR4_K2_E5                                      (0x1<<3) // Resolution result for 40GBase-KR4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_40G_KR4_K2_E5_SHIFT                                3
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_40G_CR4_K2_E5                                      (0x1<<4) // Resolution result for 40GBase-CR4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_40G_CR4_K2_E5_SHIFT                                4
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_100G_CR10_K2_E5                                    (0x1<<5) // Resolution result for 100GBase-CR10.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_100G_CR10_K2_E5_SHIFT                              5
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_100G_KP4_K2_E5                                     (0x1<<6) // Resolution result for 100GBase-KP4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_100G_KP4_K2_E5_SHIFT                               6
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_100G_KR4_K2_E5                                     (0x1<<7) // Resolution result for 100GBase-KR4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_100G_KR4_K2_E5_SHIFT                               7
+#define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_K2_E5                                                        0x0086e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_100G_CR4_K2_E5                                     (0x1<<0) // Resolution result for 100GBase-CR4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_100G_CR4_K2_E5_SHIFT                               0
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_S_K2_E5                                     (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_S_K2_E5_SHIFT                               1
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_K2_E5                                       (0x1<<2) // Resolution result for 25GBase-GR KR or CR.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_K2_E5_SHIFT                                 2
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_25G_KR_K2_E5                                       (0x1<<3) // Resolution result for 25GBase-KR.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_25G_KR_K2_E5_SHIFT                                 3
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_25G_CR_K2_E5                                       (0x1<<4) // Resolution result for 25GBase-CR4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_25G_CR_K2_E5_SHIFT                                 4
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_50G_KR2_K2_E5                                      (0x1<<5) // Resolution result for 50GBase-KR2.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_50G_KR2_K2_E5_SHIFT                                5
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_50G_CR2_K2_E5                                      (0x1<<6) // Resolution result for 50GBase-CR2.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_50G_CR2_K2_E5_SHIFT                                6
+#define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_FEC_K2_E5                                                          0x0086e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_FEC_RS_K2_E5                                                     (0x1<<0) // Resolution result for Reed-Solomon FEC.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_FEC_RS_K2_E5_SHIFT                                               0
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_FEC_FC_K2_E5                                                     (0x1<<1) // Resolution result for Firecode base page FEC.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_FEC_FC_K2_E5_SHIFT                                               1
+#define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_PAUSE_K2_E5                                                        0x0086ecUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_PAUSE_RX_K2_E5                                                   (0x1<<0) // Resolution result for RX PAUSE enable.    It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_PAUSE_RX_K2_E5_SHIFT                                             0
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_PAUSE_TX_K2_E5                                                   (0x1<<1) // Resolution result for TX PAUSE enable.    It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_PAUSE_TX_K2_E5_SHIFT                                             1
+#define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_EEE_K2_E5                                                          0x0086f0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_EEE_F821_K2_E5                                                   (0x1<<0) // Resolution result for EEE.  It is 1 if both the local device and the link partner advertise the EEE capability for the resolved PHY type.  It is 0 otherwise.  It is valid when status0.an_link_good is 1. Note that it indicates EEE deep sleep capability.
+  #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_EEE_F821_K2_E5_SHIFT                                             0
+#define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_K2_E5                                                            0x0086f8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_1G_KX_K2_E5                                            (0x1<<0) // link_status for 1000Base-KX
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_1G_KX_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_10G_KX4_K2_E5                                          (0x1<<1) // link_status for 10GBase-KX4
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_10G_KX4_K2_E5_SHIFT                                    1
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_10G_KR_K2_E5                                           (0x1<<2) // link_status for 10GBase-KR
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_10G_KR_K2_E5_SHIFT                                     2
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_40G_KR4_K2_E5                                          (0x1<<3) // link_status for 40GBase-KR4
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_40G_KR4_K2_E5_SHIFT                                    3
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_40G_CR4_K2_E5                                          (0x1<<4) // link_status for 40GBase-CR4
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_40G_CR4_K2_E5_SHIFT                                    4
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_100G_CR10_K2_E5                                        (0x1<<5) // link_status for 100GBase-CR10
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_100G_CR10_K2_E5_SHIFT                                  5
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_100G_KP4_K2_E5                                         (0x1<<6) // link_status for 100GBase-KP4
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_100G_KP4_K2_E5_SHIFT                                   6
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_100G_KR4_K2_E5                                         (0x1<<7) // link_status for 100GBase-KR4
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_100G_KR4_K2_E5_SHIFT                                   7
+#define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_K2_E5                                                            0x0086fcUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_100G_CR4_K2_E5                                         (0x1<<0) // link_status for 100GBase-CR4
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_100G_CR4_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_25G_GR_K2_E5                                           (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_25G_GR_K2_E5_SHIFT                                     1
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_25G_KR_K2_E5                                           (0x1<<3) // link_status for 25GBase-KR
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_25G_KR_K2_E5_SHIFT                                     3
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_25G_CR_K2_E5                                           (0x1<<4) // link_status for 25GBase-CR4
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_25G_CR_K2_E5_SHIFT                                     4
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_50G_KR2_K2_E5                                          (0x1<<5) // link_status for 50GBase-KR2
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_50G_KR2_K2_E5_SHIFT                                    5
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_50G_CR2_K2_E5                                          (0x1<<6) // link_status for 50GBase-CR2
+  #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_50G_CR2_K2_E5_SHIFT                                    6
+#define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1523_K2_E5                                                     0x008704UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1523_RESERVEDFIELD1485_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1523_RESERVEDFIELD1485_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1523_RESERVEDFIELD1486_K2_E5                                 (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1523_RESERVEDFIELD1486_K2_E5_SHIFT                           2
+#define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1524_K2_E5                                                     0x008708UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1524_RESERVEDFIELD1487_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1524_RESERVEDFIELD1487_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1525_K2_E5                                                     0x00870cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1525_RESERVEDFIELD1488_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1525_RESERVEDFIELD1488_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1526_K2_E5                                                     0x008714UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1526_RESERVEDFIELD1489_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1526_RESERVEDFIELD1489_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1526_RESERVEDFIELD1490_K2_E5                                 (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1526_RESERVEDFIELD1490_K2_E5_SHIFT                           1
+  #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1526_RESERVEDFIELD1491_K2_E5                                 (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1526_RESERVEDFIELD1491_K2_E5_SHIFT                           3
+  #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1526_RESERVEDFIELD1492_K2_E5                                 (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1526_RESERVEDFIELD1492_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1527_K2_E5                                                     0x008718UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1527_RESERVEDFIELD1493_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1527_RESERVEDFIELD1493_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1528_K2_E5                                                     0x00871cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1529_K2_E5                                                     0x008720UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1530_K2_E5                                              0x008800UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1530_RESERVEDFIELD1496_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1530_RESERVEDFIELD1496_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1530_RESERVEDFIELD1497_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1530_RESERVEDFIELD1497_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1531_K2_E5                                              0x008808UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1532_K2_E5                                              0x00880cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1532_RESERVEDFIELD1499_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1532_RESERVEDFIELD1499_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1532_RESERVEDFIELD1500_K2_E5                          (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1532_RESERVEDFIELD1500_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1533_K2_E5                                              0x008814UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1533_RESERVEDFIELD1501_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1533_RESERVEDFIELD1501_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1533_RESERVEDFIELD1502_K2_E5                          (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1533_RESERVEDFIELD1502_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1533_RESERVEDFIELD1503_K2_E5                          (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1533_RESERVEDFIELD1503_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1534_K2_E5                                              0x00881cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1534_RESERVEDFIELD1504_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1534_RESERVEDFIELD1504_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1535_K2_E5                                              0x008824UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1535_RESERVEDFIELD1505_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1535_RESERVEDFIELD1505_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1536_K2_E5                                              0x008828UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1536_RESERVEDFIELD1506_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1536_RESERVEDFIELD1506_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1536_RESERVEDFIELD1507_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1536_RESERVEDFIELD1507_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1537_K2_E5                                              0x00882cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1537_RESERVEDFIELD1508_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1537_RESERVEDFIELD1508_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1537_RESERVEDFIELD1509_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1537_RESERVEDFIELD1509_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1538_K2_E5                                              0x008830UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1538_RESERVEDFIELD1510_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1538_RESERVEDFIELD1510_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1538_RESERVEDFIELD1511_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1538_RESERVEDFIELD1511_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1538_RESERVEDFIELD1512_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1538_RESERVEDFIELD1512_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1538_RESERVEDFIELD1513_K2_E5                          (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1538_RESERVEDFIELD1513_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1539_K2_E5                                              0x008838UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1539_RESERVEDFIELD1514_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1539_RESERVEDFIELD1514_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1539_RESERVEDFIELD1515_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1539_RESERVEDFIELD1515_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1540_K2_E5                                              0x00883cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1540_RESERVEDFIELD1516_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1540_RESERVEDFIELD1516_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1540_RESERVEDFIELD1517_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1540_RESERVEDFIELD1517_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1541_K2_E5                                              0x008840UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1541_RESERVEDFIELD1518_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1541_RESERVEDFIELD1518_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1541_RESERVEDFIELD1519_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1541_RESERVEDFIELD1519_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1542_K2_E5                                              0x008844UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1542_RESERVEDFIELD1520_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1542_RESERVEDFIELD1520_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1542_RESERVEDFIELD1521_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1542_RESERVEDFIELD1521_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1543_K2_E5                                              0x008880UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1543_RESERVEDFIELD1522_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1543_RESERVEDFIELD1522_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1543_RESERVEDFIELD1523_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1543_RESERVEDFIELD1523_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1544_K2_E5                                              0x008884UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1544_RESERVEDFIELD1524_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1544_RESERVEDFIELD1524_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1544_RESERVEDFIELD1525_K2_E5                          (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1544_RESERVEDFIELD1525_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1545_K2_E5                                              0x008888UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1546_K2_E5                                              0x00888cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1547_K2_E5                                              0x008890UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1547_RESERVEDFIELD1528_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1547_RESERVEDFIELD1528_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1547_RESERVEDFIELD1529_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1547_RESERVEDFIELD1529_K2_E5_SHIFT                    3
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1547_RESERVEDFIELD1530_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1547_RESERVEDFIELD1530_K2_E5_SHIFT                    6
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1547_RESERVEDFIELD1531_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1547_RESERVEDFIELD1531_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1548_K2_E5                                              0x008894UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1548_RESERVEDFIELD1532_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1548_RESERVEDFIELD1532_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1548_RESERVEDFIELD1533_K2_E5                          (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1548_RESERVEDFIELD1533_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1549_K2_E5                                              0x008898UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1550_K2_E5                                              0x00889cUL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1551_K2_E5                                              0x0088a0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1551_RESERVEDFIELD1536_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1551_RESERVEDFIELD1536_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1551_RESERVEDFIELD1537_K2_E5                          (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1551_RESERVEDFIELD1537_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1552_K2_E5                                              0x0088a4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1553_K2_E5                                              0x0088a8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1554_K2_E5                                              0x0088acUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1554_RESERVEDFIELD1540_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1554_RESERVEDFIELD1540_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1555_K2_E5                                              0x0088b0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1556_K2_E5                                              0x0088b8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_AGCLOS_CTRL0_K2_E5                                                      0x0088c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_AGCLOS_CTRL0_AGCLOS_START_K2_E5                                       (0xf<<0) // AGC LOS Threshold Start Value
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_AGCLOS_CTRL0_AGCLOS_START_K2_E5_SHIFT                                 0
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1557_K2_E5                                              0x0088c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1557_RESERVEDFIELD1543_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1557_RESERVEDFIELD1543_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1558_K2_E5                                              0x0088c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1558_RESERVEDFIELD1544_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1558_RESERVEDFIELD1544_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1559_K2_E5                                              0x0088ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1559_RESERVEDFIELD1545_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1559_RESERVEDFIELD1545_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1559_RESERVEDFIELD1546_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1559_RESERVEDFIELD1546_K2_E5_SHIFT                    6
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1559_RESERVEDFIELD1547_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1559_RESERVEDFIELD1547_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1560_K2_E5                                              0x0088d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1560_RESERVEDFIELD1548_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1560_RESERVEDFIELD1548_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1560_RESERVEDFIELD1549_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1560_RESERVEDFIELD1549_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1560_RESERVEDFIELD1550_K2_E5                          (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1560_RESERVEDFIELD1550_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1561_K2_E5                                              0x0088d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1561_RESERVEDFIELD1551_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1561_RESERVEDFIELD1551_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1561_RESERVEDFIELD1552_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1561_RESERVEDFIELD1552_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1561_RESERVEDFIELD1553_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1561_RESERVEDFIELD1553_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1562_K2_E5                                              0x0088d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1562_RESERVEDFIELD1554_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1562_RESERVEDFIELD1554_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1563_K2_E5                                              0x0088dcUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1564_K2_E5                                              0x0088e0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1565_K2_E5                                              0x0088e4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1566_K2_E5                                              0x0088e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1566_RESERVEDFIELD1558_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1566_RESERVEDFIELD1558_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1567_K2_E5                                              0x0088f4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1567_RESERVEDFIELD1559_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1567_RESERVEDFIELD1559_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1567_RESERVEDFIELD1560_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1567_RESERVEDFIELD1560_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_PLE_ATT_CTRL1_K2_E5                                                     0x0088f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_PLE_ATT_CTRL1_PLE_ATT_START_K2_E5                                     (0x7<<0) // PLE LFG Start Value
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_PLE_ATT_CTRL1_PLE_ATT_START_K2_E5_SHIFT                               0
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_K2_E5                                                  0x008900UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_EQ_HFG_SQL_START_K2_E5                               (0x1f<<0) // CTLE HFG Start Value
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_EQ_HFG_SQL_START_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1568_K2_E5                                              0x008904UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1568_RESERVEDFIELD1561_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1568_RESERVEDFIELD1561_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1569_K2_E5                                              0x008908UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1569_RESERVEDFIELD1562_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1569_RESERVEDFIELD1562_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1570_K2_E5                                              0x00890cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1570_RESERVEDFIELD1563_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1570_RESERVEDFIELD1563_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1570_RESERVEDFIELD1564_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1570_RESERVEDFIELD1564_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1571_K2_E5                                              0x008910UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1571_RESERVEDFIELD1565_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1571_RESERVEDFIELD1565_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1571_RESERVEDFIELD1566_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1571_RESERVEDFIELD1566_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1571_RESERVEDFIELD1567_K2_E5                          (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1571_RESERVEDFIELD1567_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1572_K2_E5                                              0x008914UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1572_RESERVEDFIELD1568_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1572_RESERVEDFIELD1568_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1572_RESERVEDFIELD1569_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1572_RESERVEDFIELD1569_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1572_RESERVEDFIELD1570_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1572_RESERVEDFIELD1570_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1573_K2_E5                                              0x008918UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1573_RESERVEDFIELD1571_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1573_RESERVEDFIELD1571_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1574_K2_E5                                              0x008940UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1574_RESERVEDFIELD1572_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1574_RESERVEDFIELD1572_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1574_RESERVEDFIELD1573_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1574_RESERVEDFIELD1573_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1574_RESERVEDFIELD1574_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1574_RESERVEDFIELD1574_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1574_RESERVEDFIELD1575_K2_E5                          (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1574_RESERVEDFIELD1575_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1575_K2_E5                                              0x008944UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1575_RESERVEDFIELD1576_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1575_RESERVEDFIELD1576_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1575_RESERVEDFIELD1577_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1575_RESERVEDFIELD1577_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1576_K2_E5                                              0x008948UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1576_RESERVEDFIELD1578_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1576_RESERVEDFIELD1578_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1576_RESERVEDFIELD1579_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1576_RESERVEDFIELD1579_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1577_K2_E5                                              0x00894cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1577_RESERVEDFIELD1580_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1577_RESERVEDFIELD1580_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1577_RESERVEDFIELD1581_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1577_RESERVEDFIELD1581_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1578_K2_E5                                              0x008950UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1578_RESERVEDFIELD1582_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1578_RESERVEDFIELD1582_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1578_RESERVEDFIELD1583_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1578_RESERVEDFIELD1583_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1579_K2_E5                                              0x008954UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1579_RESERVEDFIELD1584_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1579_RESERVEDFIELD1584_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1579_RESERVEDFIELD1585_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1579_RESERVEDFIELD1585_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1580_K2_E5                                              0x008958UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1580_RESERVEDFIELD1586_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1580_RESERVEDFIELD1586_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1580_RESERVEDFIELD1587_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1580_RESERVEDFIELD1587_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1581_K2_E5                                              0x00895cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1581_RESERVEDFIELD1588_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1581_RESERVEDFIELD1588_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1581_RESERVEDFIELD1589_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1581_RESERVEDFIELD1589_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1582_K2_E5                                              0x008960UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1582_RESERVEDFIELD1590_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1582_RESERVEDFIELD1590_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1582_RESERVEDFIELD1591_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1582_RESERVEDFIELD1591_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1583_K2_E5                                              0x008964UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1583_RESERVEDFIELD1592_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1583_RESERVEDFIELD1592_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1583_RESERVEDFIELD1593_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1583_RESERVEDFIELD1593_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1584_K2_E5                                              0x008968UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1584_RESERVEDFIELD1594_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1584_RESERVEDFIELD1594_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1584_RESERVEDFIELD1595_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1584_RESERVEDFIELD1595_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1585_K2_E5                                              0x00896cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1585_RESERVEDFIELD1596_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1585_RESERVEDFIELD1596_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1585_RESERVEDFIELD1597_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1585_RESERVEDFIELD1597_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1586_K2_E5                                              0x008970UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1586_RESERVEDFIELD1598_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1586_RESERVEDFIELD1598_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1586_RESERVEDFIELD1599_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1586_RESERVEDFIELD1599_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1587_K2_E5                                              0x008974UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1587_RESERVEDFIELD1600_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1587_RESERVEDFIELD1600_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1587_RESERVEDFIELD1601_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1587_RESERVEDFIELD1601_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1588_K2_E5                                              0x008978UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1588_RESERVEDFIELD1602_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1588_RESERVEDFIELD1602_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1588_RESERVEDFIELD1603_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1588_RESERVEDFIELD1603_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1589_K2_E5                                              0x00897cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1589_RESERVEDFIELD1604_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1589_RESERVEDFIELD1604_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1589_RESERVEDFIELD1605_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1589_RESERVEDFIELD1605_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1590_K2_E5                                              0x008980UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1590_RESERVEDFIELD1606_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1590_RESERVEDFIELD1606_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1590_RESERVEDFIELD1607_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1590_RESERVEDFIELD1607_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1591_K2_E5                                              0x008984UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1591_RESERVEDFIELD1608_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1591_RESERVEDFIELD1608_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1591_RESERVEDFIELD1609_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1591_RESERVEDFIELD1609_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1592_K2_E5                                              0x008988UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1592_RESERVEDFIELD1610_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1592_RESERVEDFIELD1610_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1592_RESERVEDFIELD1611_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1592_RESERVEDFIELD1611_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1593_K2_E5                                              0x00898cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1593_RESERVEDFIELD1612_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1593_RESERVEDFIELD1612_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1593_RESERVEDFIELD1613_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1593_RESERVEDFIELD1613_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1594_K2_E5                                              0x008990UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1594_RESERVEDFIELD1614_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1594_RESERVEDFIELD1614_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1594_RESERVEDFIELD1615_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1594_RESERVEDFIELD1615_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1595_K2_E5                                              0x008994UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1595_RESERVEDFIELD1616_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1595_RESERVEDFIELD1616_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1595_RESERVEDFIELD1617_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1595_RESERVEDFIELD1617_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1596_K2_E5                                              0x008998UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1596_RESERVEDFIELD1618_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1596_RESERVEDFIELD1618_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1596_RESERVEDFIELD1619_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1596_RESERVEDFIELD1619_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1597_K2_E5                                              0x00899cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1597_RESERVEDFIELD1620_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1597_RESERVEDFIELD1620_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1597_RESERVEDFIELD1621_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1597_RESERVEDFIELD1621_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1598_K2_E5                                              0x0089a0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1598_RESERVEDFIELD1622_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1598_RESERVEDFIELD1622_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1598_RESERVEDFIELD1623_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1598_RESERVEDFIELD1623_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_GN_APG_CTRL0_K2_E5                                                      0x0089c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_GN_APG_CTRL0_GN_APG_START_K2_E5                                       (0x3<<0) // GN APG Start Value
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_GN_APG_CTRL0_GN_APG_START_K2_E5_SHIFT                                 0
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1599_K2_E5                                              0x0089c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1599_RESERVEDFIELD1624_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1599_RESERVEDFIELD1624_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1599_RESERVEDFIELD1625_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1599_RESERVEDFIELD1625_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1600_K2_E5                                              0x0089c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1600_RESERVEDFIELD1626_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1600_RESERVEDFIELD1626_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1600_RESERVEDFIELD1627_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1600_RESERVEDFIELD1627_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1601_K2_E5                                              0x0089ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1601_RESERVEDFIELD1628_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1601_RESERVEDFIELD1628_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1601_RESERVEDFIELD1629_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1601_RESERVEDFIELD1629_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1601_RESERVEDFIELD1630_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1601_RESERVEDFIELD1630_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1602_K2_E5                                              0x0089d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1602_RESERVEDFIELD1631_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1602_RESERVEDFIELD1631_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1602_RESERVEDFIELD1632_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1602_RESERVEDFIELD1632_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1602_RESERVEDFIELD1633_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1602_RESERVEDFIELD1633_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1603_K2_E5                                              0x0089d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1603_RESERVEDFIELD1634_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1603_RESERVEDFIELD1634_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1604_K2_E5                                              0x0089d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1604_RESERVEDFIELD1635_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1604_RESERVEDFIELD1635_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1604_RESERVEDFIELD1636_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1604_RESERVEDFIELD1636_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_LFG_CTRL0_K2_E5                                                      0x008a00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_LFG_CTRL0_EQ_LFG_START_K2_E5                                       (0x1f<<0) // EQ LFG Start Value
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_LFG_CTRL0_EQ_LFG_START_K2_E5_SHIFT                                 0
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_LFG_CTRL1_K2_E5                                                      0x008a04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_LFG_CTRL1_EQ_LFG_VALUE_MAX_K2_E5                                   (0x1f<<0) // EQ LFG Maximum Value, inclusive
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_LFG_CTRL1_EQ_LFG_VALUE_MAX_K2_E5_SHIFT                             0
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_LFG_CTRL2_K2_E5                                                      0x008a08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_LFG_CTRL2_EQ_LFG_VALUE_MIN_K2_E5                                   (0x1f<<0) // EQ LFG Minimum Value, inclusive
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_LFG_CTRL2_EQ_LFG_VALUE_MIN_K2_E5_SHIFT                             0
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1605_K2_E5                                              0x008a0cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1605_RESERVEDFIELD1637_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1605_RESERVEDFIELD1637_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1605_RESERVEDFIELD1638_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1605_RESERVEDFIELD1638_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1606_K2_E5                                              0x008a10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1606_RESERVEDFIELD1639_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1606_RESERVEDFIELD1639_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1606_RESERVEDFIELD1640_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1606_RESERVEDFIELD1640_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1606_RESERVEDFIELD1641_K2_E5                          (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1606_RESERVEDFIELD1641_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1607_K2_E5                                              0x008a14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1607_RESERVEDFIELD1642_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1607_RESERVEDFIELD1642_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1607_RESERVEDFIELD1643_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1607_RESERVEDFIELD1643_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1607_RESERVEDFIELD1644_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1607_RESERVEDFIELD1644_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1608_K2_E5                                              0x008a18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1608_RESERVEDFIELD1645_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1608_RESERVEDFIELD1645_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1609_K2_E5                                              0x008a1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1609_RESERVEDFIELD1646_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1609_RESERVEDFIELD1646_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1610_K2_E5                                              0x008a20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1610_RESERVEDFIELD1647_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1610_RESERVEDFIELD1647_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1611_K2_E5                                              0x008a40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1611_RESERVEDFIELD1648_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1611_RESERVEDFIELD1648_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1612_K2_E5                                              0x008a44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1612_RESERVEDFIELD1649_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1612_RESERVEDFIELD1649_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1613_K2_E5                                              0x008a48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1613_RESERVEDFIELD1650_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1613_RESERVEDFIELD1650_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1614_K2_E5                                              0x008a4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1614_RESERVEDFIELD1651_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1614_RESERVEDFIELD1651_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1614_RESERVEDFIELD1652_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1614_RESERVEDFIELD1652_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1615_K2_E5                                              0x008a50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1615_RESERVEDFIELD1653_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1615_RESERVEDFIELD1653_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1615_RESERVEDFIELD1654_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1615_RESERVEDFIELD1654_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1615_RESERVEDFIELD1655_K2_E5                          (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1615_RESERVEDFIELD1655_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1616_K2_E5                                              0x008a54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1616_RESERVEDFIELD1656_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1616_RESERVEDFIELD1656_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1616_RESERVEDFIELD1657_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1616_RESERVEDFIELD1657_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1616_RESERVEDFIELD1658_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1616_RESERVEDFIELD1658_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1617_K2_E5                                              0x008a58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1617_RESERVEDFIELD1659_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1617_RESERVEDFIELD1659_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1618_K2_E5                                              0x008a60UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1618_RESERVEDFIELD1660_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1618_RESERVEDFIELD1660_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1618_RESERVEDFIELD1661_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1618_RESERVEDFIELD1661_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_MB_CTRL1_K2_E5                                                       0x008a64UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_K2_E5                                        (0xf<<0) // EQ MBF Start Value
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_K2_E5                                        (0xf<<4) // EQ MBG Start Value
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_K2_E5_SHIFT                                  4
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1619_K2_E5                                              0x008a68UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1620_K2_E5                                              0x008a6cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1621_K2_E5                                              0x008a70UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1621_RESERVEDFIELD1664_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1621_RESERVEDFIELD1664_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1621_RESERVEDFIELD1665_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1621_RESERVEDFIELD1665_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1621_RESERVEDFIELD1666_K2_E5                          (0xf<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1621_RESERVEDFIELD1666_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1622_K2_E5                                              0x008a74UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1622_RESERVEDFIELD1667_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1622_RESERVEDFIELD1667_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1622_RESERVEDFIELD1668_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1622_RESERVEDFIELD1668_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1622_RESERVEDFIELD1669_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1622_RESERVEDFIELD1669_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1623_K2_E5                                              0x008a80UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1624_K2_E5                                              0x008a84UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1625_K2_E5                                              0x008a88UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1625_RESERVEDFIELD1672_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1625_RESERVEDFIELD1672_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1625_RESERVEDFIELD1673_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1625_RESERVEDFIELD1673_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1625_RESERVEDFIELD1674_K2_E5                          (0xf<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1625_RESERVEDFIELD1674_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1626_K2_E5                                              0x008a8cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1626_RESERVEDFIELD1675_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1626_RESERVEDFIELD1675_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1626_RESERVEDFIELD1676_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1626_RESERVEDFIELD1676_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1626_RESERVEDFIELD1677_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1626_RESERVEDFIELD1677_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1627_K2_E5                                              0x008a98UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1628_K2_E5                                              0x008a9cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1629_K2_E5                                              0x008aa0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1630_K2_E5                                              0x008aa4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1631_K2_E5                                              0x008aacUL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1632_K2_E5                                              0x008ab0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1632_RESERVEDFIELD1683_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1632_RESERVEDFIELD1683_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1632_RESERVEDFIELD1684_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1632_RESERVEDFIELD1684_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1633_K2_E5                                              0x008ab8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1633_RESERVEDFIELD1685_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1633_RESERVEDFIELD1685_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1633_RESERVEDFIELD1686_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1633_RESERVEDFIELD1686_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1634_K2_E5                                              0x008abcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1634_RESERVEDFIELD1687_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1634_RESERVEDFIELD1687_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1635_K2_E5                                              0x008ae0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1636_K2_E5                                              0x008ae4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1637_K2_E5                                               0x008c00UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1638_K2_E5                                               0x008c04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1638_RESERVEDFIELD1689_K2_E5                           (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1638_RESERVEDFIELD1689_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1639_K2_E5                                               0x008c08UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1640_K2_E5                                               0x008c0cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1640_RESERVEDFIELD1691_K2_E5                           (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1640_RESERVEDFIELD1691_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1641_K2_E5                                               0x008c10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1641_RESERVEDFIELD1692_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1641_RESERVEDFIELD1692_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1642_K2_E5                                               0x008c14UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1643_K2_E5                                               0x008c20UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1644_K2_E5                                               0x008c24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1644_RESERVEDFIELD1695_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1644_RESERVEDFIELD1695_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1645_K2_E5                                               0x008c30UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1646_K2_E5                                               0x008c34UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1646_RESERVEDFIELD1697_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1646_RESERVEDFIELD1697_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1647_K2_E5                                               0x008c40UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1648_K2_E5                                               0x008c44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1648_RESERVEDFIELD1699_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1648_RESERVEDFIELD1699_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1649_K2_E5                                               0x008c4cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1650_K2_E5                                               0x008c50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1650_RESERVEDFIELD1701_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1650_RESERVEDFIELD1701_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1651_K2_E5                                               0x008c58UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1652_K2_E5                                               0x008c5cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1652_RESERVEDFIELD1703_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1652_RESERVEDFIELD1703_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1653_K2_E5                                               0x008c80UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LEQ_RXCLK_RESERVEDREGISTER1654_K2_E5                                               0x008c84UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DRV_REFCLK_AFE_PD_CTRL0_K2_E5                                                      0x008e00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_AFE_PD_CTRL0_PD_TXDRV_K2_E5                                           (0xf<<0) // power down TX driver
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_AFE_PD_CTRL0_PD_TXDRV_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1655_K2_E5                                              0x008e04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1655_RESERVEDFIELD1704_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1655_RESERVEDFIELD1704_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DRV_REFCLK_AFE_CTRL0_K2_E5                                                         0x008e08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_AFE_CTRL0_TXDRV_LP_IDLE_K2_E5                                         (0x3<<0) // When HIGH, TX driver goes into a low power IDLE model. In this mode, the output termination is not guaranteed to be 50 Ohm closer to 200 Ohm
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_AFE_CTRL0_TXDRV_LP_IDLE_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1656_K2_E5                                              0x008e0cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1657_K2_E5                                              0x008e10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1657_RESERVEDFIELD1706_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1657_RESERVEDFIELD1706_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1657_RESERVEDFIELD1707_K2_E5                          (0x1f<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1657_RESERVEDFIELD1707_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1658_K2_E5                                              0x008e14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1658_RESERVEDFIELD1708_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1658_RESERVEDFIELD1708_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1659_K2_E5                                              0x008e18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1659_RESERVEDFIELD1709_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1659_RESERVEDFIELD1709_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1659_RESERVEDFIELD1710_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1659_RESERVEDFIELD1710_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1659_RESERVEDFIELD1711_K2_E5                          (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1659_RESERVEDFIELD1711_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1659_RESERVEDFIELD1712_K2_E5                          (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1659_RESERVEDFIELD1712_K2_E5_SHIFT                    5
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1659_RESERVEDFIELD1713_K2_E5                          (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1659_RESERVEDFIELD1713_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1660_K2_E5                                              0x008e20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1660_RESERVEDFIELD1714_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1660_RESERVEDFIELD1714_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1660_RESERVEDFIELD1715_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1660_RESERVEDFIELD1715_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1660_RESERVEDFIELD1716_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1660_RESERVEDFIELD1716_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1660_RESERVEDFIELD1717_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1660_RESERVEDFIELD1717_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1661_K2_E5                                              0x008e24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1661_RESERVEDFIELD1718_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1661_RESERVEDFIELD1718_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1661_RESERVEDFIELD1719_K2_E5                          (0x1f<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1661_RESERVEDFIELD1719_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1662_K2_E5                                              0x008e28UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1662_RESERVEDFIELD1720_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1662_RESERVEDFIELD1720_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1662_RESERVEDFIELD1721_K2_E5                          (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1662_RESERVEDFIELD1721_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1663_K2_E5                                              0x008e2cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1663_RESERVEDFIELD1722_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1663_RESERVEDFIELD1722_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1663_RESERVEDFIELD1723_K2_E5                          (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1663_RESERVEDFIELD1723_K2_E5_SHIFT                    5
+#define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1664_K2_E5                                              0x008e30UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1664_RESERVEDFIELD1724_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1664_RESERVEDFIELD1724_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1664_RESERVEDFIELD1725_K2_E5                          (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1664_RESERVEDFIELD1725_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1665_K2_E5                                              0x008e34UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1665_RESERVEDFIELD1726_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1665_RESERVEDFIELD1726_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1665_RESERVEDFIELD1727_K2_E5                          (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1665_RESERVEDFIELD1727_K2_E5_SHIFT                    5
+#define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL0_K2_E5                                                        0x008e40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL0_REQ_K2_E5                                                  (0x1<<0) // Set to 1 to apply the coefficient settings, and hold until ack is 1.  Set to 0 once ack is 1.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL0_REQ_K2_E5_SHIFT                                            0
+#define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_STATUS0_K2_E5                                                      0x008e44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_STATUS0_ACK_K2_E5                                                (0x1<<0) // Set to 1 by firmware when updates are complete. Cleared when req = 0
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_STATUS0_ACK_K2_E5_SHIFT                                          0
+#define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL1_K2_E5                                                        0x008e48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL1_TXEQ_C1_K2_E5                                              (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL1_TXEQ_C1_K2_E5_SHIFT                                        0
+#define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1666_K2_E5                                              0x008e4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1666_RESERVEDFIELD1728_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1666_RESERVEDFIELD1728_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL3_K2_E5                                                        0x008e50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL3_TXEQ_CM1_K2_E5                                             (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL3_TXEQ_CM1_K2_E5_SHIFT                                       0
+#define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1667_K2_E5                                              0x008e54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1667_RESERVEDFIELD1729_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1667_RESERVEDFIELD1729_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1667_RESERVEDFIELD1730_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1667_RESERVEDFIELD1730_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL5_K2_E5                                                        0x008e58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL5_DRV_SWING_K2_E5                                            (0xf<<0) // Thermometer coded control to adjust the delay between data and clock for the final 2to1 mux. Setting 00000 min delay of clock path and 11111 max delay of clock path.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL5_DRV_SWING_K2_E5_SHIFT                                      0
+#define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1668_K2_E5                                              0x008e5cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1668_RESERVEDFIELD1731_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1668_RESERVEDFIELD1731_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1668_RESERVEDFIELD1732_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1668_RESERVEDFIELD1732_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1668_RESERVEDFIELD1733_K2_E5                          (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1668_RESERVEDFIELD1733_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1668_RESERVEDFIELD1734_K2_E5                          (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1668_RESERVEDFIELD1734_K2_E5_SHIFT                    5
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1668_RESERVEDFIELD1735_K2_E5                          (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1668_RESERVEDFIELD1735_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1669_K2_E5                                              0x008e60UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1669_RESERVEDFIELD1736_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1669_RESERVEDFIELD1736_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1669_RESERVEDFIELD1737_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1669_RESERVEDFIELD1737_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1669_RESERVEDFIELD1738_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1669_RESERVEDFIELD1738_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1669_RESERVEDFIELD1739_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1669_RESERVEDFIELD1739_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1670_K2_E5                                              0x008e64UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1670_RESERVEDFIELD1740_K2_E5                          (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1670_RESERVEDFIELD1740_K2_E5_SHIFT                    3
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1670_RESERVEDFIELD1741_K2_E5                          (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1670_RESERVEDFIELD1741_K2_E5_SHIFT                    5
+#define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1671_K2_E5                                              0x008e6cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1671_RESERVEDFIELD1742_K2_E5                          (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1671_RESERVEDFIELD1742_K2_E5_SHIFT                    3
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1671_RESERVEDFIELD1743_K2_E5                          (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1671_RESERVEDFIELD1743_K2_E5_SHIFT                    5
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1672_K2_E5                                              0x009000UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1672_RESERVEDFIELD1744_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1672_RESERVEDFIELD1744_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1673_K2_E5                                              0x009004UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1673_RESERVEDFIELD1745_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1673_RESERVEDFIELD1745_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1674_K2_E5                                              0x009008UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1674_RESERVEDFIELD1746_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1674_RESERVEDFIELD1746_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1674_RESERVEDFIELD1747_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1674_RESERVEDFIELD1747_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1675_K2_E5                                              0x00900cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1675_RESERVEDFIELD1748_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1675_RESERVEDFIELD1748_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1675_RESERVEDFIELD1749_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1675_RESERVEDFIELD1749_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1676_K2_E5                                              0x009010UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1676_RESERVEDFIELD1750_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1676_RESERVEDFIELD1750_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1677_K2_E5                                              0x009018UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1677_RESERVEDFIELD1751_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1677_RESERVEDFIELD1751_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1678_K2_E5                                              0x009028UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1678_RESERVEDFIELD1752_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1678_RESERVEDFIELD1752_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1678_RESERVEDFIELD1753_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1678_RESERVEDFIELD1753_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1678_RESERVEDFIELD1754_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1678_RESERVEDFIELD1754_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1679_K2_E5                                              0x009030UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1679_RESERVEDFIELD1755_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1679_RESERVEDFIELD1755_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1679_RESERVEDFIELD1756_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1679_RESERVEDFIELD1756_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1680_K2_E5                                              0x009038UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1680_RESERVEDFIELD1757_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1680_RESERVEDFIELD1757_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1680_RESERVEDFIELD1758_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1680_RESERVEDFIELD1758_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1680_RESERVEDFIELD1759_K2_E5                          (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1680_RESERVEDFIELD1759_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1681_K2_E5                                              0x009040UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1681_RESERVEDFIELD1760_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1681_RESERVEDFIELD1760_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1681_RESERVEDFIELD1761_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1681_RESERVEDFIELD1761_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1681_RESERVEDFIELD1762_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1681_RESERVEDFIELD1762_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1682_K2_E5                                              0x009048UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1682_RESERVEDFIELD1763_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1682_RESERVEDFIELD1763_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1682_RESERVEDFIELD1764_K2_E5                          (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1682_RESERVEDFIELD1764_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1683_K2_E5                                              0x009050UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1684_K2_E5                                              0x009058UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1684_RESERVEDFIELD1766_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1684_RESERVEDFIELD1766_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1684_RESERVEDFIELD1767_K2_E5                          (0xf<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1684_RESERVEDFIELD1767_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1685_K2_E5                                              0x009060UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1686_K2_E5                                              0x009064UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1686_RESERVEDFIELD1769_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1686_RESERVEDFIELD1769_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1687_K2_E5                                              0x00906cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1687_RESERVEDFIELD1770_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1687_RESERVEDFIELD1770_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1687_RESERVEDFIELD1771_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1687_RESERVEDFIELD1771_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_CTRL0_K2_E5                                                         0x009080UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_CTRL0_REQ_K2_E5                                                   (0x1<<0) // Write 1 to request a command CMD execution.  It should be held at 1 until fsm_status0.ack is 1, and then it should be set back to 0.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_CTRL0_REQ_K2_E5_SHIFT                                             0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_CTRL0_CMD_K2_E5                                                   (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_CTRL0_CMD_K2_E5_SHIFT                                             1
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_CTRL0_RESERVEDFIELD1772_K2_E5                                     (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_CTRL0_RESERVEDFIELD1772_K2_E5_SHIFT                               6
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL_K2_E5                                     (0x1<<7) // Set it to 1 when changing DFE tap values
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL_K2_E5_SHIFT                               7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1688_K2_E5                                              0x009084UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1688_RESERVEDFIELD1773_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1688_RESERVEDFIELD1773_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1688_RESERVEDFIELD1774_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1688_RESERVEDFIELD1774_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1689_K2_E5                                              0x009088UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1690_K2_E5                                              0x00908cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1690_RESERVEDFIELD1776_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1690_RESERVEDFIELD1776_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1691_K2_E5                                              0x009090UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1692_K2_E5                                              0x009094UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1692_RESERVEDFIELD1778_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1692_RESERVEDFIELD1778_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1693_K2_E5                                              0x009098UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1694_K2_E5                                              0x00909cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1694_RESERVEDFIELD1780_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1694_RESERVEDFIELD1780_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_STATUS0_K2_E5                                                       0x0090a0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_STATUS0_ACK_K2_E5                                                 (0x1<<0) // Acknowledge from DFE after command execution. Will be set to 1 after a command is completed, and will clear to 0 after fsm_status0.req is cleared
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_STATUS0_ACK_K2_E5_SHIFT                                           0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD1781_K2_E5                                   (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD1781_K2_E5_SHIFT                             1
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD1782_K2_E5                                   (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD1782_K2_E5_SHIFT                             2
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD1783_K2_E5                                   (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD1783_K2_E5_SHIFT                             3
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_K2_E5                                                         0x0090a8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN_K2_E5                                         (0x1<<0) // Enables updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN_K2_E5                                         (0x1<<1) // Enables updating Tap 1 Even 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN_K2_E5_SHIFT                                   1
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN_K2_E5                                          (0x1<<2) // Enables updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN_K2_E5_SHIFT                                    2
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN_K2_E5                                          (0x1<<3) // Enables updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN_K2_E5_SHIFT                                    3
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP2_EN_K2_E5                                               (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP2_EN_K2_E5_SHIFT                                         4
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP3_EN_K2_E5                                               (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP3_EN_K2_E5_SHIFT                                         5
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP4_EN_K2_E5                                               (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP4_EN_K2_E5_SHIFT                                         6
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP5_EN_K2_E5                                               (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP5_EN_K2_E5_SHIFT                                         7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL0_K2_E5                                               0x0090acUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_K2_E5                                  (0x1f<<0) // Starting value for Tap 1 Even 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_K2_E5_SHIFT                            0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5                         (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5_SHIFT                   7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL1_K2_E5                                               0x0090b0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_K2_E5                                  (0x1f<<0) // Starting value for Tap 1 Even 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_K2_E5_SHIFT                            0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5                         (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5_SHIFT                   7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL2_K2_E5                                               0x0090b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_K2_E5                                   (0x1f<<0) // Starting value for Tap 1 Odd 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5                          (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL3_K2_E5                                               0x0090b8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_K2_E5                                   (0x1f<<0) // Starting value for Tap 1 Odd 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5                          (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL4_K2_E5                                               0x0090bcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_K2_E5                                        (0xf<<0) // Starting value for Tap 2 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY_K2_E5                               (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY_K2_E5_SHIFT                         7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL5_K2_E5                                               0x0090c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_K2_E5                                        (0x7<<0) // Starting value for Tap 3 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY_K2_E5                               (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY_K2_E5_SHIFT                         7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL6_K2_E5                                               0x0090c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_K2_E5                                        (0x7<<0) // Starting value for Tap 4 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY_K2_E5                               (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY_K2_E5_SHIFT                         7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL7_K2_E5                                               0x0090c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_K2_E5                                        (0x7<<0) // Starting value for Tap 5 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY_K2_E5                               (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY_K2_E5_SHIFT                         7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_K2_E5                                                0x0090ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_K2_E5                                   (0x1f<<0) // Loading value for Tap 1 Even 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5                          (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_K2_E5                                                0x0090d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_K2_E5                                   (0x1f<<0) // Loading value for Tap 1 Even 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5                          (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_K2_E5                                                0x0090d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_K2_E5                                    (0x1f<<0) // Loading value for Tap 1 Odd 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5                           (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5_SHIFT                     7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_K2_E5                                                0x0090d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_K2_E5                                    (0x1f<<0) // Loading value for Tap 1 Odd 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5                           (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5_SHIFT                     7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_K2_E5                                                0x0090dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_K2_E5                                         (0xf<<0) // Loading value for Tap 2 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_K2_E5                                (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_K2_E5                                                0x0090e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_K2_E5                                         (0x7<<0) // Loading value for Tap 3 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_K2_E5                                (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_K2_E5                                                0x0090e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_K2_E5                                         (0x7<<0) // Loading value for Tap 4 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_K2_E5                                (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_K2_E5                                                0x0090e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_K2_E5                                         (0x7<<0) // Loading value for Tap 5 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_K2_E5                                (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS0_K2_E5                                                   0x0090ecUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_K2_E5                                      (0x1f<<0) // binary value for Tap 1 Even 0 Path for Tap Adaptations
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_K2_E5_SHIFT                                0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_K2_E5                             (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_K2_E5_SHIFT                       7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS1_K2_E5                                                   0x0090f0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_K2_E5                                      (0x1f<<0) // binary  value for Tap 1 Even 1 Path for Tap Adaptations
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_K2_E5_SHIFT                                0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_K2_E5                             (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_K2_E5_SHIFT                       7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS2_K2_E5                                                   0x0090f4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_K2_E5                                       (0x1f<<0) // binary  value for Tap 1 Odd 0 Path for Tap Adaptations
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_K2_E5                              (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_K2_E5_SHIFT                        7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS3_K2_E5                                                   0x0090f8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_K2_E5                                       (0x1f<<0) // binary  value for Tap 1 Odd 1 Path for Tap Adaptations
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_K2_E5                              (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_K2_E5_SHIFT                        7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS4_K2_E5                                                   0x0090fcUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_K2_E5                                            (0xf<<0) // binary  value for Tap 2 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY_K2_E5                                   (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS5_K2_E5                                                   0x009100UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_K2_E5                                            (0x7<<0) // binary  value for Tap 3 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY_K2_E5                                   (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS6_K2_E5                                                   0x009104UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_K2_E5                                            (0x7<<0) // binary  value for Tap 4 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY_K2_E5                                   (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS7_K2_E5                                                   0x009108UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_K2_E5                                            (0x7<<0) // binary  value for Tap 5 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY_K2_E5                                   (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_K2_E5                                              0x009140UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1784_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1784_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1785_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1785_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1786_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1786_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1787_K2_E5                          (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1787_K2_E5_SHIFT                    3
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1788_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1788_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1789_K2_E5                          (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1789_K2_E5_SHIFT                    5
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1790_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1790_K2_E5_SHIFT                    6
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1791_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1791_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1696_K2_E5                                              0x009144UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1696_RESERVEDFIELD1792_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1696_RESERVEDFIELD1792_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1697_K2_E5                                              0x009148UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1697_RESERVEDFIELD1793_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1697_RESERVEDFIELD1793_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1698_K2_E5                                              0x00914cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1698_RESERVEDFIELD1794_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1698_RESERVEDFIELD1794_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1699_K2_E5                                              0x009150UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1699_RESERVEDFIELD1795_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1699_RESERVEDFIELD1795_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1700_K2_E5                                              0x009154UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1700_RESERVEDFIELD1796_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1700_RESERVEDFIELD1796_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1701_K2_E5                                              0x009158UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1701_RESERVEDFIELD1797_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1701_RESERVEDFIELD1797_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1702_K2_E5                                              0x00915cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1702_RESERVEDFIELD1798_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1702_RESERVEDFIELD1798_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1703_K2_E5                                              0x009160UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1703_RESERVEDFIELD1799_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1703_RESERVEDFIELD1799_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1704_K2_E5                                              0x009164UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1704_RESERVEDFIELD1800_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1704_RESERVEDFIELD1800_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1705_K2_E5                                              0x009168UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1705_RESERVEDFIELD1801_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1705_RESERVEDFIELD1801_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1706_K2_E5                                              0x00916cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1706_RESERVEDFIELD1802_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1706_RESERVEDFIELD1802_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1707_K2_E5                                              0x009170UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1707_RESERVEDFIELD1803_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1707_RESERVEDFIELD1803_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1708_K2_E5                                              0x009174UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1708_RESERVEDFIELD1804_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1708_RESERVEDFIELD1804_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1709_K2_E5                                              0x009178UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1709_RESERVEDFIELD1805_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1709_RESERVEDFIELD1805_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1710_K2_E5                                              0x00917cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1710_RESERVEDFIELD1806_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1710_RESERVEDFIELD1806_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1711_K2_E5                                              0x009180UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1711_RESERVEDFIELD1807_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1711_RESERVEDFIELD1807_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1712_K2_E5                                              0x009184UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1712_RESERVEDFIELD1808_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1712_RESERVEDFIELD1808_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1713_K2_E5                                              0x009188UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1713_RESERVEDFIELD1809_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1713_RESERVEDFIELD1809_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_K2_E5                                              0x00918cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1810_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1810_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1811_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1811_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1812_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1812_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1813_K2_E5                          (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1813_K2_E5_SHIFT                    3
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1814_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1814_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1815_K2_E5                          (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1815_K2_E5_SHIFT                    5
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1816_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1816_K2_E5_SHIFT                    6
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1817_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1817_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1715_K2_E5                                              0x009190UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1715_RESERVEDFIELD1818_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1715_RESERVEDFIELD1818_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1715_RESERVEDFIELD1819_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1715_RESERVEDFIELD1819_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1715_RESERVEDFIELD1820_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1715_RESERVEDFIELD1820_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_K2_E5                                              0x009194UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1821_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1821_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1822_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1822_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1823_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1823_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1824_K2_E5                          (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1824_K2_E5_SHIFT                    3
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1825_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1825_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1826_K2_E5                          (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1826_K2_E5_SHIFT                    5
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1827_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1827_K2_E5_SHIFT                    6
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1828_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1828_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1717_K2_E5                                               0x009200UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1718_K2_E5                                               0x009204UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1718_RESERVEDFIELD1830_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1718_RESERVEDFIELD1830_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1719_K2_E5                                               0x009208UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1719_RESERVEDFIELD1831_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1719_RESERVEDFIELD1831_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1719_RESERVEDFIELD1832_K2_E5                           (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1719_RESERVEDFIELD1832_K2_E5_SHIFT                     5
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1719_RESERVEDFIELD1833_K2_E5                           (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1719_RESERVEDFIELD1833_K2_E5_SHIFT                     6
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1720_K2_E5                                               0x009218UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1720_RESERVEDFIELD1834_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1720_RESERVEDFIELD1834_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1720_RESERVEDFIELD1835_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1720_RESERVEDFIELD1835_K2_E5_SHIFT                     1
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1721_K2_E5                                               0x00921cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1722_K2_E5                                               0x009220UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1722_RESERVEDFIELD1837_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1722_RESERVEDFIELD1837_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1723_K2_E5                                               0x009224UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1723_RESERVEDFIELD1838_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1723_RESERVEDFIELD1838_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1723_RESERVEDFIELD1839_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1723_RESERVEDFIELD1839_K2_E5_SHIFT                     1
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1724_K2_E5                                               0x009228UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1725_K2_E5                                               0x00922cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1725_RESERVEDFIELD1841_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1725_RESERVEDFIELD1841_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1726_K2_E5                                               0x009230UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1727_K2_E5                                               0x009234UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1727_RESERVEDFIELD1843_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1727_RESERVEDFIELD1843_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1728_K2_E5                                               0x009240UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1728_RESERVEDFIELD1844_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1728_RESERVEDFIELD1844_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1728_RESERVEDFIELD1845_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1728_RESERVEDFIELD1845_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1728_RESERVEDFIELD1846_K2_E5                           (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1728_RESERVEDFIELD1846_K2_E5_SHIFT                     2
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1729_K2_E5                                               0x009244UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1729_RESERVEDFIELD1847_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1729_RESERVEDFIELD1847_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1730_K2_E5                                               0x009248UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1731_K2_E5                                               0x009258UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1732_K2_E5                                               0x00925cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1732_RESERVEDFIELD1850_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1732_RESERVEDFIELD1850_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1733_K2_E5                                               0x009260UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1734_K2_E5                                               0x009264UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1734_RESERVEDFIELD1852_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1734_RESERVEDFIELD1852_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1735_K2_E5                                               0x009268UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1736_K2_E5                                               0x00926cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1737_K2_E5                                               0x009270UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1738_K2_E5                                               0x009274UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1739_K2_E5                                               0x009278UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1740_K2_E5                                               0x009290UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1740_RESERVEDFIELD1858_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1740_RESERVEDFIELD1858_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1740_RESERVEDFIELD1859_K2_E5                           (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1740_RESERVEDFIELD1859_K2_E5_SHIFT                     2
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1740_RESERVEDFIELD1860_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1740_RESERVEDFIELD1860_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1741_K2_E5                                               0x009294UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1741_RESERVEDFIELD1861_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1741_RESERVEDFIELD1861_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1741_RESERVEDFIELD1862_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1741_RESERVEDFIELD1862_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1742_K2_E5                                               0x009298UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1742_RESERVEDFIELD1863_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1742_RESERVEDFIELD1863_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1742_RESERVEDFIELD1864_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1742_RESERVEDFIELD1864_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1743_K2_E5                                               0x00929cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1743_RESERVEDFIELD1865_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1743_RESERVEDFIELD1865_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1744_K2_E5                                               0x0092a0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1745_K2_E5                                               0x0092a4UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1746_K2_E5                                               0x0092a8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1747_K2_E5                                               0x0092acUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1747_RESERVEDFIELD1869_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1747_RESERVEDFIELD1869_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1748_K2_E5                                               0x0092b0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1749_K2_E5                                               0x0092b4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1749_RESERVEDFIELD1871_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1749_RESERVEDFIELD1871_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1750_K2_E5                                               0x0092b8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1751_K2_E5                                               0x0092bcUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1751_RESERVEDFIELD1873_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1751_RESERVEDFIELD1873_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1752_K2_E5                                               0x0092c0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1753_K2_E5                                               0x0092c4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1753_RESERVEDFIELD1875_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1753_RESERVEDFIELD1875_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1754_K2_E5                                               0x0092c8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1755_K2_E5                                               0x0092ccUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1755_RESERVEDFIELD1877_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1755_RESERVEDFIELD1877_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1756_K2_E5                                               0x0092d0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1757_K2_E5                                               0x0092d4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1757_RESERVEDFIELD1879_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1757_RESERVEDFIELD1879_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1758_K2_E5                                               0x0092d8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1759_K2_E5                                               0x0092dcUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1759_RESERVEDFIELD1881_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1759_RESERVEDFIELD1881_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1760_K2_E5                                               0x0092e0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1761_K2_E5                                               0x0092e4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1761_RESERVEDFIELD1883_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1761_RESERVEDFIELD1883_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1762_K2_E5                                               0x009300UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1763_K2_E5                                               0x009304UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1764_K2_E5                                               0x009308UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1765_K2_E5                                               0x00930cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1765_RESERVEDFIELD1887_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1765_RESERVEDFIELD1887_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1766_K2_E5                                               0x009310UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1767_K2_E5                                               0x009314UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1767_RESERVEDFIELD1889_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1767_RESERVEDFIELD1889_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1768_K2_E5                                               0x009318UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1769_K2_E5                                               0x00931cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1769_RESERVEDFIELD1891_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1769_RESERVEDFIELD1891_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1770_K2_E5                                               0x009320UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1771_K2_E5                                               0x009324UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1771_RESERVEDFIELD1893_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1771_RESERVEDFIELD1893_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1772_K2_E5                                               0x009328UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1773_K2_E5                                               0x00932cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1773_RESERVEDFIELD1895_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1773_RESERVEDFIELD1895_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1774_K2_E5                                               0x009330UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1775_K2_E5                                               0x009334UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1775_RESERVEDFIELD1897_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1775_RESERVEDFIELD1897_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1776_K2_E5                                               0x009338UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1777_K2_E5                                               0x00933cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1777_RESERVEDFIELD1899_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1777_RESERVEDFIELD1899_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1778_K2_E5                                               0x009340UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1779_K2_E5                                               0x009344UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1779_RESERVEDFIELD1901_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1779_RESERVEDFIELD1901_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1780_K2_E5                                               0x009358UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1780_RESERVEDFIELD1902_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1780_RESERVEDFIELD1902_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1780_RESERVEDFIELD1903_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1780_RESERVEDFIELD1903_K2_E5_SHIFT                     1
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1781_K2_E5                                               0x00935cUL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1782_K2_E5                                               0x009360UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1783_K2_E5                                               0x009380UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1783_RESERVEDFIELD1906_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1783_RESERVEDFIELD1906_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1784_K2_E5                                               0x009384UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1785_K2_E5                                               0x009388UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1786_K2_E5                                               0x00938cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1787_K2_E5                                               0x009390UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1788_K2_E5                                               0x009394UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1789_K2_E5                                               0x009398UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1790_K2_E5                                               0x00939cUL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1791_K2_E5                                               0x0093a0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1792_K2_E5                                               0x0093a4UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1793_K2_E5                                               0x0093a8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1794_K2_E5                                               0x0093acUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1794_RESERVEDFIELD1917_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1794_RESERVEDFIELD1917_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_AFE_CAL_CTRL_K2_E5                                                      0x009400UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_AFE_CAL_CTRL_RXLOS_OFFSETCAL_K2_E5                                    (0x1<<0) // Enables analog LOS offset calibration circuits.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_AFE_CAL_CTRL_RXLOS_OFFSETCAL_K2_E5_SHIFT                              0
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1795_K2_E5                                              0x009404UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1795_RESERVEDFIELD1918_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1795_RESERVEDFIELD1918_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1796_K2_E5                                              0x009408UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1796_RESERVEDFIELD1919_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1796_RESERVEDFIELD1919_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_CTRL0_K2_E5                                                  0x00940cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_CTRL0_EN_K2_E5                                             (0x1<<0) // Enables the run-length detection digital LOS filter.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_CTRL0_EN_K2_E5_SHIFT                                       0
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_CTRL1_K2_E5                                                  0x009410UL //Access:RW   DataWidth:0x8    // Value of run-length which will trigger an LOS condition.
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_STATUS0_K2_E5                                                0x009414UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_K2_E5                                       (0x1<<0) // Indicates that the run-length filter is currently exceeding the specified run-length threshold.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY_K2_E5                                (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the specified run-length threshold.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY_K2_E5_SHIFT                          1
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL0_K2_E5                                                      0x009440UL //Access:RW   DataWidth:0x8    // Digital Rx LOS glitch filter assertion threshold.  Determines the number of consecutive clk_i clock cycles that the analog  LOS must remain a logic 1 before the output of the filter will assert.  Can be disabled by writing a value of 0x00.
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL1_K2_E5                                                      0x009444UL //Access:RW   DataWidth:0x8    // Digital Rx LOS glitch filter assertion threshold.  Determines the number of consecutive clk_i clock cycles that the analog  LOS must remain a logic 1 before the output of the filter will assert.  Can be disabled by writing a value of 0x0000.
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL2_K2_E5                                                      0x009448UL //Access:RW   DataWidth:0x8    // Digital Rx LOS glitch filter assertion threshold.  Determines the number of consecutive clk_i clock cycles that the raw analog  LOS must remain a logic 1 before the output of the filter will assert.  Can be disabled by writing a value of 0x000000.
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL3_K2_E5                                                      0x00944cUL //Access:RW   DataWidth:0x8    // Same as above.
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL4_K2_E5                                                      0x009450UL //Access:RW   DataWidth:0x8    // Same as above.
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL5_K2_E5                                                      0x009454UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL5_DEASSERT_THRESHOLD_25_24_K2_E5                           (0x3<<0) // Same as above.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL5_DEASSERT_THRESHOLD_25_24_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL6_K2_E5                                                      0x009458UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL6_EN_K2_E5                                                 (0x1<<0) // Enables the digital deglitching filter.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL6_EN_K2_E5_SHIFT                                           0
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1797_K2_E5                                              0x009480UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1797_RESERVEDFIELD1920_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1797_RESERVEDFIELD1920_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1798_K2_E5                                              0x009484UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1799_K2_E5                                              0x009488UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1800_K2_E5                                              0x00948cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1801_K2_E5                                              0x009490UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1801_RESERVEDFIELD1924_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1801_RESERVEDFIELD1924_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_OVERRIDE_CTRL0_K2_E5                                                    0x0094c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN_K2_E5                                         (0x1<<0) // Override enable for the LOS output of the digital filtering logic.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE_K2_E5                                      (0x1<<4) // Override value for the LOS output of the digital filtering logic.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE_K2_E5_SHIFT                                4
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1802_K2_E5                                              0x0094c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1802_RESERVEDFIELD1925_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1802_RESERVEDFIELD1925_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1802_RESERVEDFIELD1926_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1802_RESERVEDFIELD1926_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1803_K2_E5                                              0x0094c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1803_RESERVEDFIELD1927_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1803_RESERVEDFIELD1927_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1803_RESERVEDFIELD1928_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1803_RESERVEDFIELD1928_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1804_K2_E5                                              0x0094ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1804_RESERVEDFIELD1929_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1804_RESERVEDFIELD1929_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1804_RESERVEDFIELD1930_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1804_RESERVEDFIELD1930_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1805_K2_E5                                              0x009500UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1805_RESERVEDFIELD1931_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1805_RESERVEDFIELD1931_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1805_RESERVEDFIELD1932_K2_E5                          (0x7<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1805_RESERVEDFIELD1932_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1805_RESERVEDFIELD1933_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1805_RESERVEDFIELD1933_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1806_K2_E5                                              0x009504UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1806_RESERVEDFIELD1934_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1806_RESERVEDFIELD1934_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1806_RESERVEDFIELD1935_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1806_RESERVEDFIELD1935_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1806_RESERVEDFIELD1936_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1806_RESERVEDFIELD1936_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1806_RESERVEDFIELD1937_K2_E5                          (0xf<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1806_RESERVEDFIELD1937_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1807_K2_E5                                              0x009508UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1808_K2_E5                                              0x00950cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1809_K2_E5                                              0x009518UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1809_RESERVEDFIELD1940_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1809_RESERVEDFIELD1940_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1810_K2_E5                                              0x009544UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1810_RESERVEDFIELD1941_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1810_RESERVEDFIELD1941_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1810_RESERVEDFIELD1942_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1810_RESERVEDFIELD1942_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1811_K2_E5                                              0x009564UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1811_RESERVEDFIELD1943_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1811_RESERVEDFIELD1943_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1812_K2_E5                                              0x009580UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1812_RESERVEDFIELD1944_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1812_RESERVEDFIELD1944_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1813_K2_E5                                              0x0095c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1813_RESERVEDFIELD1945_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1813_RESERVEDFIELD1945_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1813_RESERVEDFIELD1946_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1813_RESERVEDFIELD1946_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_K2_E5                                                           0x0095c4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_LOS_READY_K2_E5                                               (0x1<<0) // Indicates that digital and analog Rx LOS blocks are in LOS mode.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_LOS_READY_K2_E5_SHIFT                                         0
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_RESERVEDFIELD1947_K2_E5                                       (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_RESERVEDFIELD1947_K2_E5_SHIFT                                 1
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_LOS_K2_E5                                                     (0x1<<2) // The filtered LOS signal value.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_LOS_K2_E5_SHIFT                                               2
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_LOS_RAW_K2_E5                                                 (0x1<<3) // The unfiltered LOS signal value.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_LOS_RAW_K2_E5_SHIFT                                           3
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_LOS_NO_EII_K2_E5                                              (0x1<<4) // The filtered LOS signal value before EII override logic.
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_LOS_NO_EII_K2_E5_SHIFT                                        4
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_RESERVEDFIELD1948_K2_E5                                       (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_RESERVEDFIELD1948_K2_E5_SHIFT                                 5
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1814_K2_E5                                                  0x009600UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1814_RESERVEDFIELD1949_K2_E5                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1814_RESERVEDFIELD1949_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1815_K2_E5                                                  0x009604UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1815_RESERVEDFIELD1950_K2_E5                              (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1815_RESERVEDFIELD1950_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1816_K2_E5                                                  0x009608UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1817_K2_E5                                                  0x00960cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1817_RESERVEDFIELD1952_K2_E5                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1817_RESERVEDFIELD1952_K2_E5_SHIFT                        0
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1817_RESERVEDFIELD1953_K2_E5                              (0xf<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1817_RESERVEDFIELD1953_K2_E5_SHIFT                        1
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1818_K2_E5                                                  0x009640UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1819_K2_E5                                                  0x009644UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1819_RESERVEDFIELD1955_K2_E5                              (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1819_RESERVEDFIELD1955_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1820_K2_E5                                                  0x009648UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1821_K2_E5                                                  0x00964cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1821_RESERVEDFIELD1957_K2_E5                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1821_RESERVEDFIELD1957_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1822_K2_E5                                                  0x009680UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1822_RESERVEDFIELD1958_K2_E5                              (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1822_RESERVEDFIELD1958_K2_E5_SHIFT                        0
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1822_RESERVEDFIELD1959_K2_E5                              (0xf<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1822_RESERVEDFIELD1959_K2_E5_SHIFT                        2
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1823_K2_E5                                                  0x009684UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1824_K2_E5                                                  0x009688UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1824_RESERVEDFIELD1961_K2_E5                              (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1824_RESERVEDFIELD1961_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1825_K2_E5                                                  0x00968cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1826_K2_E5                                                  0x009690UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1826_RESERVEDFIELD1963_K2_E5                              (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1826_RESERVEDFIELD1963_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1827_K2_E5                                                  0x009694UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1828_K2_E5                                                  0x009698UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1828_RESERVEDFIELD1965_K2_E5                              (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1828_RESERVEDFIELD1965_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1829_K2_E5                                                  0x0096c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1829_RESERVEDFIELD1966_K2_E5                              (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1829_RESERVEDFIELD1966_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1830_K2_E5                                                  0x0096c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1830_RESERVEDFIELD1967_K2_E5                              (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1830_RESERVEDFIELD1967_K2_E5_SHIFT                        0
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1830_RESERVEDFIELD1968_K2_E5                              (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1830_RESERVEDFIELD1968_K2_E5_SHIFT                        4
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1831_K2_E5                                                  0x0096c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1831_RESERVEDFIELD1969_K2_E5                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1831_RESERVEDFIELD1969_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1832_K2_E5                                                  0x009700UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1832_RESERVEDFIELD1970_K2_E5                              (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1832_RESERVEDFIELD1970_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1833_K2_E5                                                  0x009704UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1834_K2_E5                                                  0x009708UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1835_K2_E5                                                  0x00970cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1836_K2_E5                                                  0x009710UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1837_K2_E5                                                  0x009714UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1838_K2_E5                                                  0x009718UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1839_K2_E5                                                  0x00971cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1840_K2_E5                                                  0x009720UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1840_RESERVEDFIELD1978_K2_E5                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1840_RESERVEDFIELD1978_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1841_K2_E5                                                  0x009740UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1841_RESERVEDFIELD1979_K2_E5                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1841_RESERVEDFIELD1979_K2_E5_SHIFT                        0
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1841_RESERVEDFIELD1980_K2_E5                              (0xf<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1841_RESERVEDFIELD1980_K2_E5_SHIFT                        1
+#define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1842_K2_E5                                                  0x009744UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_BIST_TX_CTRL_K2_E5                                                                 0x009800UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_BIST_TX_CTRL_EN_K2_E5                                                            (0x1<<0) // Enables BIST Tx data generation.
+  #define PHY_NW_IP_REG_LN1_BIST_TX_CTRL_EN_K2_E5_SHIFT                                                      0
+  #define PHY_NW_IP_REG_LN1_BIST_TX_CTRL_PATTERN_SEL_K2_E5                                                   (0xf<<1) // Selects the pattern to transmitted: 0x1  PRBS 0xC1 0x2  PRBS 0x221 0x3  PRBS 0xA01 0x4  PRBS 0xC001 0x5  PRBS 0x840001 0x6  PRBS 0x90000001 0x7  User defined pattern UDP 0x9  MAC Tx data
+  #define PHY_NW_IP_REG_LN1_BIST_TX_CTRL_PATTERN_SEL_K2_E5_SHIFT                                             1
+#define PHY_NW_IP_REG_LN1_BIST_TX_RESERVEDREGISTER1843_K2_E5                                                 0x009804UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_BIST_TX_RESERVEDREGISTER1844_K2_E5                                                 0x009808UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_BIST_TX_RESERVEDREGISTER1845_K2_E5                                                 0x00980cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_BIST_TX_RESERVEDREGISTER1846_K2_E5                                                 0x009810UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_BIST_TX_BER_CTRL0_K2_E5                                                            0x009818UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_BIST_TX_BER_CTRL0_MODE_K2_E5                                                     (0x3<<0) // Controls what type of error injection is used: 0x0  None 0x1  Single cycle error 0x2  Timer based
+  #define PHY_NW_IP_REG_LN1_BIST_TX_BER_CTRL0_MODE_K2_E5_SHIFT                                               0
+#define PHY_NW_IP_REG_LN1_BIST_TX_BER_CTRL1_K2_E5                                                            0x00981cUL //Access:RW   DataWidth:0x8    // Number of cycles between single bit-error injection
+#define PHY_NW_IP_REG_LN1_BIST_TX_BER_CTRL2_K2_E5                                                            0x009820UL //Access:RW   DataWidth:0x8    // Number of cycles between single bit-error injection
+#define PHY_NW_IP_REG_LN1_BIST_TX_BER_CTRL3_K2_E5                                                            0x009824UL //Access:RW   DataWidth:0x8    // Sets the Tx data bits to be flipped.
+#define PHY_NW_IP_REG_LN1_BIST_TX_BER_CTRL4_K2_E5                                                            0x009828UL //Access:RW   DataWidth:0x8    // Sets the Tx data bits to be flipped.
+#define PHY_NW_IP_REG_LN1_BIST_TX_BER_CTRL5_K2_E5                                                            0x00982cUL //Access:RW   DataWidth:0x8    // Sets the Tx data bits to be flipped.
+#define PHY_NW_IP_REG_LN1_BIST_TX_BER_CTRL6_K2_E5                                                            0x009830UL //Access:RW   DataWidth:0x8    // Sets the Tx data bits to be flipped.
+#define PHY_NW_IP_REG_LN1_BIST_TX_BER_CTRL7_K2_E5                                                            0x009834UL //Access:RW   DataWidth:0x8    // Sets the Tx data bits to be flipped.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_SHIFT_AMOUNT_K2_E5                                                     0x009880UL //Access:RW   DataWidth:0x8    // Determines the length of the UDP.  Must be set to d160 modulus udp_length.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_7_0_K2_E5                                                              0x009890UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_15_8_K2_E5                                                             0x009894UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_23_16_K2_E5                                                            0x009898UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_31_24_K2_E5                                                            0x00989cUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_39_32_K2_E5                                                            0x0098a0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_47_40_K2_E5                                                            0x0098a4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_55_48_K2_E5                                                            0x0098a8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_63_56_K2_E5                                                            0x0098acUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_71_64_K2_E5                                                            0x0098b0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_79_72_K2_E5                                                            0x0098b4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_87_80_K2_E5                                                            0x0098b8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_95_88_K2_E5                                                            0x0098bcUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_103_96_K2_E5                                                           0x0098c0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_111_104_K2_E5                                                          0x0098c4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_119_112_K2_E5                                                          0x0098c8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_127_120_K2_E5                                                          0x0098ccUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_135_128_K2_E5                                                          0x0098d0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_143_136_K2_E5                                                          0x0098d4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_151_144_K2_E5                                                          0x0098d8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_159_152_K2_E5                                                          0x0098dcUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_167_160_K2_E5                                                          0x0098e0UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_175_168_K2_E5                                                          0x0098e4UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_183_176_K2_E5                                                          0x0098e8UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_191_184_K2_E5                                                          0x0098ecUL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN1_BIST_TX_UDP_199_192_K2_E5                                                          0x0098f0UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_K2_E5                                                                 0x009a00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_EN_K2_E5                                                            (0x1<<0) // Enables BIST Rx data checking.
+  #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_EN_K2_E5_SHIFT                                                      0
+  #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_PATTERN_SEL_K2_E5                                                   (0xf<<1) // Selects the pattern to search for: 0x1  PRBS 0xC1 0x2  PRBS 0x221 0x3  PRBS 0xA01 0x4  PRBS 0xC001 0x5  PRBS 0x840001 0x6  PRBS 0x90000001 0x7  User defined pattern UDP 0x8  Auto-detect
+  #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_PATTERN_SEL_K2_E5_SHIFT                                             1
+  #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_CLEAR_BER_K2_E5                                                     (0x1<<5) // Clears the bit error counter.
+  #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_CLEAR_BER_K2_E5_SHIFT                                               5
+  #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_STOP_ERROR_COUNT_K2_E5                                              (0x1<<6) // Stops the error count from incrementing.  Can be used to read back the BER data coherently.
+  #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_STOP_ERROR_COUNT_K2_E5_SHIFT                                        6
+  #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_FORCE_LFSR_WITH_RXDATA_K2_E5                                        (0x1<<7) // Forces the PRBS LFSR to reseed with Rx data every cycle.  This will cause the bit error counter to be inaccurate.
+  #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_FORCE_LFSR_WITH_RXDATA_K2_E5_SHIFT                                  7
+#define PHY_NW_IP_REG_LN1_BIST_RX_STATUS_K2_E5                                                               0x009a10UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_BIST_RX_STATUS_STATE_K2_E5                                                       (0x7<<0) // State of the BIST checker: 0x0  Off 0x1  Searching for pattern 0x2  Waiting for pattern lock conditions 0x3  Pattern lock acquired 0x4  Pattern lock lost
+  #define PHY_NW_IP_REG_LN1_BIST_RX_STATUS_STATE_K2_E5_SHIFT                                                 0
+  #define PHY_NW_IP_REG_LN1_BIST_RX_STATUS_PATTERN_DET_K2_E5                                                 (0xf<<3) // Indicates the pattern  detected: 0x0  No pattern detected 0x1  PRBS 0xC1 0x2  PRBS 0x221 0x3  PRBS 0xA01 0x4  PRBS 0xC001 0x5  PRBS 0x840001 0x6  PRBS 0x90000001 0x7  User defined pattern UDP
+  #define PHY_NW_IP_REG_LN1_BIST_RX_STATUS_PATTERN_DET_K2_E5_SHIFT                                           3
+#define PHY_NW_IP_REG_LN1_BIST_RX_BER_STATUS0_K2_E5                                                          0x009a20UL //Access:R    DataWidth:0x8    // Number of bit errors.
+#define PHY_NW_IP_REG_LN1_BIST_RX_BER_STATUS1_K2_E5                                                          0x009a24UL //Access:R    DataWidth:0x8    // Number of bit errors.
+#define PHY_NW_IP_REG_LN1_BIST_RX_BER_STATUS2_K2_E5                                                          0x009a28UL //Access:R    DataWidth:0x8    // Number of bit errors.
+#define PHY_NW_IP_REG_LN1_BIST_RX_BER_STATUS4_K2_E5                                                          0x009a30UL //Access:R    DataWidth:0x8    // Number of cycles that errors have been counted.
+#define PHY_NW_IP_REG_LN1_BIST_RX_BER_STATUS5_K2_E5                                                          0x009a34UL //Access:R    DataWidth:0x8    // Number of cycles that errors have been counted.
+#define PHY_NW_IP_REG_LN1_BIST_RX_BER_STATUS6_K2_E5                                                          0x009a38UL //Access:R    DataWidth:0x8    // Number of cycles that errors have been counted.
+#define PHY_NW_IP_REG_LN1_BIST_RX_LOCK_CTRL0_K2_E5                                                           0x009a50UL //Access:RW   DataWidth:0x8    // Size of error sampling window to trigger pattern lock.
+#define PHY_NW_IP_REG_LN1_BIST_RX_LOCK_CTRL1_K2_E5                                                           0x009a54UL //Access:RW   DataWidth:0x8    // Size of error sampling window to trigger pattern lock.
+#define PHY_NW_IP_REG_LN1_BIST_RX_LOCK_CTRL2_K2_E5                                                           0x009a58UL //Access:RW   DataWidth:0x8    // Maximum number of errors allowed to trigger pattern lock.
+#define PHY_NW_IP_REG_LN1_BIST_RX_LOCK_CTRL3_K2_E5                                                           0x009a5cUL //Access:RW   DataWidth:0x8    // Maximum number of errors allowed to trigger pattern lock.
+#define PHY_NW_IP_REG_LN1_BIST_RX_LOSS_LOCK_CTRL0_K2_E5                                                      0x009a80UL //Access:RW   DataWidth:0x8    // Size of error sampling window to trigger pattern loss-of-lock.
+#define PHY_NW_IP_REG_LN1_BIST_RX_LOSS_LOCK_CTRL1_K2_E5                                                      0x009a84UL //Access:RW   DataWidth:0x8    // Size of error sampling window to trigger pattern loss-of-lock.
+#define PHY_NW_IP_REG_LN1_BIST_RX_LOSS_LOCK_CTRL2_K2_E5                                                      0x009a88UL //Access:RW   DataWidth:0x8    // Minimum number of errors allowed to trigger pattern loss-of-lock.
+#define PHY_NW_IP_REG_LN1_BIST_RX_LOSS_LOCK_CTRL3_K2_E5                                                      0x009a8cUL //Access:RW   DataWidth:0x8    // Minimum number of errors allowed to trigger pattern loss-of-lock.
+#define PHY_NW_IP_REG_LN1_BIST_RX_LOSS_LOCK_CTRL4_K2_E5                                                      0x009a90UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_BIST_RX_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_K2_E5                                  (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
+  #define PHY_NW_IP_REG_LN1_BIST_RX_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_K2_E5_SHIFT                            0
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_SHIFT_AMOUNT_K2_E5                                                     0x009ac0UL //Access:RW   DataWidth:0x8    // Determines the length of the UDP.  Must be set to d160 modulus udp_length.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_7_0_K2_E5                                                              0x009ad0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_15_8_K2_E5                                                             0x009ad4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_23_16_K2_E5                                                            0x009ad8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_31_24_K2_E5                                                            0x009adcUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_39_32_K2_E5                                                            0x009ae0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_47_40_K2_E5                                                            0x009ae4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_55_48_K2_E5                                                            0x009ae8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_63_56_K2_E5                                                            0x009aecUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_71_64_K2_E5                                                            0x009af0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_79_72_K2_E5                                                            0x009af4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_87_80_K2_E5                                                            0x009af8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_95_88_K2_E5                                                            0x009afcUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_103_96_K2_E5                                                           0x009b00UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_111_104_K2_E5                                                          0x009b04UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_119_112_K2_E5                                                          0x009b08UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_127_120_K2_E5                                                          0x009b0cUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_135_128_K2_E5                                                          0x009b10UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_143_136_K2_E5                                                          0x009b14UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_151_144_K2_E5                                                          0x009b18UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_159_152_K2_E5                                                          0x009b1cUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_167_160_K2_E5                                                          0x009b20UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_175_168_K2_E5                                                          0x009b24UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_183_176_K2_E5                                                          0x009b28UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_191_184_K2_E5                                                          0x009b2cUL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN1_BIST_RX_UDP_199_192_K2_E5                                                          0x009b30UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN1_FEATURE_RXTERM_CFG0_K2_E5                                                          0x009c00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_RXTERM_CFG0_AC_COUPLED_K2_E5                                             (0x1<<0) // Configures AC/DC coupling of the lane 0: DC coupled 1: AC coupled
+  #define PHY_NW_IP_REG_LN1_FEATURE_RXTERM_CFG0_AC_COUPLED_K2_E5_SHIFT                                       0
+#define PHY_NW_IP_REG_LN1_FEATURE_RXCLKDIV_CFG0_K2_E5                                                        0x009c04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_RXCLKDIV_CFG0_EN_K2_E5                                                   (0x1<<0) // Enables turning on the divided rxclk output
+  #define PHY_NW_IP_REG_LN1_FEATURE_RXCLKDIV_CFG0_EN_K2_E5_SHIFT                                             0
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1847_K2_E5                                                 0x009c10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1847_RESERVEDFIELD1986_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1847_RESERVEDFIELD1986_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1847_RESERVEDFIELD1987_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1847_RESERVEDFIELD1987_K2_E5_SHIFT                       1
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1848_K2_E5                                                 0x009c14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1848_RESERVEDFIELD1988_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1848_RESERVEDFIELD1988_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1848_RESERVEDFIELD1989_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1848_RESERVEDFIELD1989_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1848_RESERVEDFIELD1990_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1848_RESERVEDFIELD1990_K2_E5_SHIFT                       2
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1848_RESERVEDFIELD1991_K2_E5                             (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1848_RESERVEDFIELD1991_K2_E5_SHIFT                       3
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1848_RESERVEDFIELD1992_K2_E5                             (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1848_RESERVEDFIELD1992_K2_E5_SHIFT                       4
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1848_RESERVEDFIELD1993_K2_E5                             (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1848_RESERVEDFIELD1993_K2_E5_SHIFT                       5
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1849_K2_E5                                                 0x009c18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1849_RESERVEDFIELD1994_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1849_RESERVEDFIELD1994_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1849_RESERVEDFIELD1995_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1849_RESERVEDFIELD1995_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1849_RESERVEDFIELD1996_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1849_RESERVEDFIELD1996_K2_E5_SHIFT                       2
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1849_RESERVEDFIELD1997_K2_E5                             (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1849_RESERVEDFIELD1997_K2_E5_SHIFT                       3
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_K2_E5                                                 0x009c1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD1998_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD1998_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD1999_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD1999_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD2000_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD2000_K2_E5_SHIFT                       2
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD2001_K2_E5                             (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD2001_K2_E5_SHIFT                       3
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD2002_K2_E5                             (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD2002_K2_E5_SHIFT                       4
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD2003_K2_E5                             (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD2003_K2_E5_SHIFT                       5
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD2004_K2_E5                             (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD2004_K2_E5_SHIFT                       6
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD2005_K2_E5                             (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD2005_K2_E5_SHIFT                       7
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1851_K2_E5                                                 0x009c20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1851_RESERVEDFIELD2006_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1851_RESERVEDFIELD2006_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1851_RESERVEDFIELD2007_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1851_RESERVEDFIELD2007_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1851_RESERVEDFIELD2008_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1851_RESERVEDFIELD2008_K2_E5_SHIFT                       2
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1851_RESERVEDFIELD2009_K2_E5                             (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1851_RESERVEDFIELD2009_K2_E5_SHIFT                       3
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1851_RESERVEDFIELD2010_K2_E5                             (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1851_RESERVEDFIELD2010_K2_E5_SHIFT                       4
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1852_K2_E5                                                 0x009c24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1852_RESERVEDFIELD2011_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1852_RESERVEDFIELD2011_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1852_RESERVEDFIELD2012_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1852_RESERVEDFIELD2012_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1852_RESERVEDFIELD2013_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1852_RESERVEDFIELD2013_K2_E5_SHIFT                       2
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1853_K2_E5                                                 0x009c40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1853_RESERVEDFIELD2014_K2_E5                             (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1853_RESERVEDFIELD2014_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1854_K2_E5                                                 0x009c44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1854_RESERVEDFIELD2015_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1854_RESERVEDFIELD2015_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1855_K2_E5                                                 0x009c48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1855_RESERVEDFIELD2016_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1855_RESERVEDFIELD2016_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1855_RESERVEDFIELD2017_K2_E5                             (0x7f<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1855_RESERVEDFIELD2017_K2_E5_SHIFT                       1
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1856_K2_E5                                                 0x009c4cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1857_K2_E5                                                 0x009c50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1857_RESERVEDFIELD2019_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1857_RESERVEDFIELD2019_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1857_RESERVEDFIELD2020_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1857_RESERVEDFIELD2020_K2_E5_SHIFT                       1
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1858_K2_E5                                                 0x009c54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1858_RESERVEDFIELD2021_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1858_RESERVEDFIELD2021_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1858_RESERVEDFIELD2022_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1858_RESERVEDFIELD2022_K2_E5_SHIFT                       1
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1859_K2_E5                                                 0x009c58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1859_RESERVEDFIELD2023_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1859_RESERVEDFIELD2023_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1859_RESERVEDFIELD2024_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1859_RESERVEDFIELD2024_K2_E5_SHIFT                       1
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1860_K2_E5                                                 0x009c80UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1860_RESERVEDFIELD2025_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1860_RESERVEDFIELD2025_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_CFG_K2_E5                                                       0x009c84UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT0_K2_E5                                  (0x3<<0) // How many times to repeat CTLE adaptation sequence for initial adaptation set 0
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT0_K2_E5_SHIFT                            0
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT1_K2_E5                                  (0x3<<2) // How many times to repeat CTLE adaptation sequence for initial adaptation set 1
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT1_K2_E5_SHIFT                            2
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_CFG_RESERVEDFIELD2026_K2_E5                                   (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_CFG_RESERVEDFIELD2026_K2_E5_SHIFT                             4
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_CFG_RESERVEDFIELD2027_K2_E5                                   (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_CFG_RESERVEDFIELD2027_K2_E5_SHIFT                             6
+#define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_AGC_CFG_K2_E5                                                   0x009c88UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN_K2_E5                                        (0x1<<0) // Enables AGC threshold adaptation for initial adaptation
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_AGC_CFG_RESERVEDFIELD2028_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_AGC_CFG_RESERVEDFIELD2028_K2_E5_SHIFT                         2
+#define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_APG_MAP_CFG_K2_E5                                               0x009c8cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN_K2_E5                                    (0x1<<0) // Enables mapping GN_APG setting from AGC threshold for initial adaptation
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_APG_MAP_CFG_RESERVEDFIELD2029_K2_E5                           (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_APG_MAP_CFG_RESERVEDFIELD2029_K2_E5_SHIFT                     2
+#define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_LFG_CFG_K2_E5                                                   0x009c90UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL_K2_E5                                       (0x3<<0) // Selects the CTLE EQ LFG adaptation method for initial adaptation set 0 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loop 0x3: Method 3: GN_APG and EQ_LFG combined closed-loop
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL_K2_E5                                       (0x3<<2) // Selects the CTLE EQ LFG adaptation method for initial adaptation set 1 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loop 0x3: Method 3: GN_APG and EQ_LFG combined closed-loop
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL_K2_E5_SHIFT                                 2
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_LFG_CFG_RESERVEDFIELD2030_K2_E5                               (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_LFG_CFG_RESERVEDFIELD2030_K2_E5_SHIFT                         4
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_LFG_CFG_RESERVEDFIELD2031_K2_E5                               (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_LFG_CFG_RESERVEDFIELD2031_K2_E5_SHIFT                         6
+#define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_K2_E5                                                  0x009c94UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN_K2_E5                                  (0x1<<0) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 0
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN_K2_E5_SHIFT                            0
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN_K2_E5                                  (0x1<<1) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 0
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN_K2_E5_SHIFT                            1
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN_K2_E5                                  (0x1<<2) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 1
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN_K2_E5_SHIFT                            2
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN_K2_E5                                  (0x1<<3) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 1
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN_K2_E5_SHIFT                            3
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2032_K2_E5                              (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2032_K2_E5_SHIFT                        4
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2033_K2_E5                              (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2033_K2_E5_SHIFT                        5
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2034_K2_E5                              (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2034_K2_E5_SHIFT                        6
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2035_K2_E5                              (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2035_K2_E5_SHIFT                        7
+#define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG1_K2_E5                                                  0x009c98UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL_K2_E5                               (0x3<<0) // Selects which HFG result to use for the initial adaptation set 0 0x0: Edge Based 0x1: Data Based 0x2: Average of Edge & Data result 0x3: Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL_K2_E5                               (0x3<<2) // Selects which HFG result to use for the initial adaptation set 1 0x0: Edge Based 0x1: Data Based 0x2: Average of Edge & Data result 0x3: Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG1_RESERVEDFIELD2036_K2_E5                              (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG1_RESERVEDFIELD2036_K2_E5_SHIFT                        4
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG1_RESERVEDFIELD2037_K2_E5                              (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG1_RESERVEDFIELD2037_K2_E5_SHIFT                        6
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1861_K2_E5                                                 0x009c9cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1861_RESERVEDFIELD2038_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1861_RESERVEDFIELD2038_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_MBS_CFG_K2_E5                                                   0x009ca0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_K2_E5                                        (0x1<<0) // Enables CTLE midband shaping adaptation for initial adaptation set 0
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN_K2_E5                                        (0x1<<1) // Enables CTLE midband shaping adaptation for initial adaptation set 1
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN_K2_E5_SHIFT                                  1
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD2039_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD2039_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD2040_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD2040_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_K2_E5                                                 0x009ca4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2041_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2041_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2042_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2042_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2043_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2043_K2_E5_SHIFT                       2
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2044_K2_E5                             (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2044_K2_E5_SHIFT                       3
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2045_K2_E5                             (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2045_K2_E5_SHIFT                       4
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2046_K2_E5                             (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2046_K2_E5_SHIFT                       5
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2047_K2_E5                             (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2047_K2_E5_SHIFT                       6
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2048_K2_E5                             (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2048_K2_E5_SHIFT                       7
+#define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_K2_E5                                                              0x009cc0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP1_EN_K2_E5                                                    (0x1<<0) // Enables DFE Tap 1. Tap1 will not be powered up if it is not enabled
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP1_EN_K2_E5_SHIFT                                              0
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP2_EN_K2_E5                                                    (0x1<<1) // Enables DFE Tap 2. Tap2 will not be powered up if it is not enabled
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP2_EN_K2_E5_SHIFT                                              1
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP3_EN_K2_E5                                                    (0x1<<2) // Enables DFE Tap 3. Tap3 will not be powered up if it is not enabled
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP3_EN_K2_E5_SHIFT                                              2
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP4_EN_K2_E5                                                    (0x1<<3) // Enables DFE Tap 4. Tap4 will not be powered up if it is not enabled
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP4_EN_K2_E5_SHIFT                                              3
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP5_EN_K2_E5                                                    (0x1<<4) // Enables DFE Tap 5. Tap5 will not be powered up if it is not enabled
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP5_EN_K2_E5_SHIFT                                              4
+#define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_CFG_K2_E5                                                        0x009cc4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_CFG_METHOD_SEL_K2_E5                                           (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Based Zero Forcing
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_CFG_METHOD_SEL_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP1_CFG_K2_E5                                                   0x009cc8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN_K2_E5                                    (0x1<<0) // Enables initial adaptations for Tap 1
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2049_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2049_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2050_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2050_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2051_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2051_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP2_CFG_K2_E5                                                   0x009cccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN_K2_E5                                    (0x1<<0) // Enables initial adaptations for Tap 2
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2052_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2052_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2053_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2053_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2054_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2054_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP3_CFG_K2_E5                                                   0x009cd0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN_K2_E5                                    (0x1<<0) // Enables initial adaptations for Tap 3
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2055_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2055_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2056_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2056_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2057_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2057_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP4_CFG_K2_E5                                                   0x009cd4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN_K2_E5                                    (0x1<<0) // Enables initial adaptations for Tap 4
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2058_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2058_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2059_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2059_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2060_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2060_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP5_CFG_K2_E5                                                   0x009cd8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN_K2_E5                                    (0x1<<0) // Enables initial adaptations for Tap 5
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2061_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2061_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2062_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2062_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2063_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2063_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_LN1_FEATURE_ADAPT_CONT_CFG0_K2_E5                                                      0x009ce0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_ADAPT_CONT_CFG0_EN_K2_E5                                                 (0x1<<0) // Enables continuous background adaptation
+  #define PHY_NW_IP_REG_LN1_FEATURE_ADAPT_CONT_CFG0_EN_K2_E5_SHIFT                                           0
+  #define PHY_NW_IP_REG_LN1_FEATURE_ADAPT_CONT_CFG0_RESERVEDFIELD2064_K2_E5                                  (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_ADAPT_CONT_CFG0_RESERVEDFIELD2064_K2_E5_SHIFT                            1
+#define PHY_NW_IP_REG_LN1_FEATURE_ADAPT_CONT_CFG1_K2_E5                                                      0x009ce4UL //Access:RW   DataWidth:0x8    // How often in ms to run continuous adaptations 1ms to ~279 mins
+#define PHY_NW_IP_REG_LN1_FEATURE_ADAPT_CONT_CFG2_K2_E5                                                      0x009ce8UL //Access:RW   DataWidth:0x8    // How often in ms to run continuous adaptations 1ms to ~279 mins
+#define PHY_NW_IP_REG_LN1_FEATURE_ADAPT_CONT_CFG3_K2_E5                                                      0x009cecUL //Access:RW   DataWidth:0x8    // How often in ms to run continuous adaptations 1ms to ~279 mins
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1863_K2_E5                                                 0x009cf0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1864_K2_E5                                                 0x009cf4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1865_K2_E5                                                 0x009cf8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1866_K2_E5                                                 0x009cfcUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1867_K2_E5                                                 0x009d00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1867_RESERVEDFIELD2069_K2_E5                             (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1867_RESERVEDFIELD2069_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1867_RESERVEDFIELD2070_K2_E5                             (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1867_RESERVEDFIELD2070_K2_E5_SHIFT                       2
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1868_K2_E5                                                 0x009d04UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1869_K2_E5                                                 0x009d08UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1870_K2_E5                                                 0x009d0cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1871_K2_E5                                                 0x009d10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1871_RESERVEDFIELD2074_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1871_RESERVEDFIELD2074_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1872_K2_E5                                                 0x009d14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1872_RESERVEDFIELD2075_K2_E5                             (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1872_RESERVEDFIELD2075_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1872_RESERVEDFIELD2076_K2_E5                             (0x1f<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1872_RESERVEDFIELD2076_K2_E5_SHIFT                       3
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1873_K2_E5                                                 0x009d18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1873_RESERVEDFIELD2077_K2_E5                             (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1873_RESERVEDFIELD2077_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1873_RESERVEDFIELD2078_K2_E5                             (0x1f<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1873_RESERVEDFIELD2078_K2_E5_SHIFT                       2
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1874_K2_E5                                                 0x009d1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1874_RESERVEDFIELD2079_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1874_RESERVEDFIELD2079_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1874_RESERVEDFIELD2080_K2_E5                             (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1874_RESERVEDFIELD2080_K2_E5_SHIFT                       4
+#define PHY_NW_IP_REG_LN1_FEATURE_TEST_CFG0_K2_E5                                                            0x009d40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_FEATURE_TEST_CFG0_RESERVEDFIELD2081_K2_E5                                        (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_TEST_CFG0_RESERVEDFIELD2081_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN1_FEATURE_TEST_CFG0_RX_CTRL_DIS_K2_E5                                              (0x1<<1) // Disables the firmware rx_ctrl MSM
+  #define PHY_NW_IP_REG_LN1_FEATURE_TEST_CFG0_RX_CTRL_DIS_K2_E5_SHIFT                                        1
+  #define PHY_NW_IP_REG_LN1_FEATURE_TEST_CFG0_RESERVEDFIELD2082_K2_E5                                        (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_TEST_CFG0_RESERVEDFIELD2082_K2_E5_SHIFT                                  2
+  #define PHY_NW_IP_REG_LN1_FEATURE_TEST_CFG0_RESERVEDFIELD2083_K2_E5                                        (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN1_FEATURE_TEST_CFG0_RESERVEDFIELD2083_K2_E5_SHIFT                                  3
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1875_K2_E5                                                 0x009d60UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1876_K2_E5                                                 0x009d64UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1877_K2_E5                                                 0x009d68UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1878_K2_E5                                                 0x009d6cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1879_K2_E5                                                 0x009d70UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1880_K2_E5                                                 0x009d74UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1881_K2_E5                                                 0x009d78UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1882_K2_E5                                                 0x009d7cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_K2_E5                                                              0x009e00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_MR_RESTART_TRAINING_K2_E5                                        (0x1<<0) // Starts link training procedure when asserted.  This is an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_MR_RESTART_TRAINING_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_MR_TRAINING_ENABLE_K2_E5                                         (0x1<<1) // Indicates to LTSM that link training procedure should be run; otherwise procedures skip directly to signal_det assertion.  This is an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_MR_TRAINING_ENABLE_K2_E5_SHIFT                                   1
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_SIGNAL_DETECT_K2_E5                                              (0x1<<2) // Output corresponding to link training signal detect variable.  Should be set when link training has completed successfully.
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_SIGNAL_DETECT_K2_E5_SHIFT                                        2
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_CLEAR_K2_E5                                                      (0x1<<3) // Synchronous reset for LT Tx block.
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_CLEAR_K2_E5_SHIFT                                                3
+#define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL1_K2_E5                                                              0x009e04UL //Access:RW   DataWidth:0x8    // Maximum time allowed for LT procedure.  If this is exceeded then the training_fail status will assert.  This is an 802.defined variable.  Value is encoded as: 39338 * DESIRED_DELAY * 2 ^logdata_width / data_width  Should be set to 500ns for 802.3 compliant timeout.
+#define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL2_K2_E5                                                              0x009e08UL //Access:RW   DataWidth:0x8    // Same as above.
+#define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL3_K2_E5                                                              0x009e0cUL //Access:RW   DataWidth:0x8    // Number of additional frames to send after both receivers have been trained and are ready.  This is an 802.3 defined variable.  Should be set between 100 and 300 for 802.3 compliance.
+#define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL4_K2_E5                                                              0x009e10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL4_WAIT_TIME_8_K2_E5                                                (0x1<<0) // Same as above.
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL4_WAIT_TIME_8_K2_E5_SHIFT                                          0
+#define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL5_K2_E5                                                              0x009e14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL5_FRAME_LOCK_K2_E5                                                 (0x1<<0) // Input to LTSM that receiver has acquired frame lock.  This value should be taken from the corresponding LT Rx register.  This  an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL5_FRAME_LOCK_K2_E5_SHIFT                                           0
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL5_RX_TRAINED_K2_E5                                                 (0x1<<1) // Input to LTSM indicating that the local receiver has completed training.  This is an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL5_RX_TRAINED_K2_E5_SHIFT                                           1
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL5_REMOTE_RX_READY_K2_E5                                            (0x1<<2) // Input to LTSM indicating that the remote receiver is trained and ready.  This value should be taken from the corresponding LT Rx registers.  This is an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL5_REMOTE_RX_READY_K2_E5_SHIFT                                      2
+#define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_K2_E5                                                             0x009e40UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_TRAINING_FAIL_K2_E5                                             (0x1<<0) // Output from LTSM indicating that link training has failed.  This is an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_TRAINING_FAIL_K2_E5_SHIFT                                       0
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_TRAINING_K2_E5                                                  (0x1<<1) // Output from LTSM indicating that link training is in progress.  This is an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_TRAINING_K2_E5_SHIFT                                            1
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_SIGNAL_DETECT_K2_E5                                             (0x1<<2) // Output from LTSM indicating that link training is complete and successful.  This is an 802.3 defined variable.  This value is only visible internally, and is not the signal_det value driven to PHY top-level.
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_SIGNAL_DETECT_K2_E5_SHIFT                                       2
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_FSM_LOCAL_RX_READY_K2_E5                                        (0x1<<4) // Output from LSM corresponding to 802.3 defined local_rx_ready variable. After this is asserted the corresponding frame status report field should be set.
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_FSM_LOCAL_RX_READY_K2_E5_SHIFT                                  4
+#define PHY_NW_IP_REG_LN1_LT_TX_PRBS_CTRL0_K2_E5                                                             0x009e4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LT_TX_PRBS_CTRL0_POLYNOMIAL_K2_E5                                                (0x7<<0) // Selects between CL72 and CL93 PRBS pattern. 0  CL72 1 + x^9 +x^11 1  CL93 1 + x^5 + x^6 + x^10 + x^11 2  CL93 1 + x^5 + x^6 + x^9 + x^11 3  CL93 1 + x^4 + x^6 + x^8 + x^11 4  CL93 1 + x^4 + x^6 + x^7 + x^11
+  #define PHY_NW_IP_REG_LN1_LT_TX_PRBS_CTRL0_POLYNOMIAL_K2_E5_SHIFT                                          0
+#define PHY_NW_IP_REG_LN1_LT_TX_PRBS_CTRL1_K2_E5                                                             0x009e50UL //Access:RW   DataWidth:0x8    // Initial PRBS LFSR seed.  This needs to be set according to the requirements in 802.3 CL72 or CL93 depending on the type of link training and lane bonding being performed.
+#define PHY_NW_IP_REG_LN1_LT_TX_PRBS_CTRL2_K2_E5                                                             0x009e54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LT_TX_PRBS_CTRL2_SEED_10_8_K2_E5                                                 (0x7<<0) // Same as above.
+  #define PHY_NW_IP_REG_LN1_LT_TX_PRBS_CTRL2_SEED_10_8_K2_E5_SHIFT                                           0
+#define PHY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL_K2_E5                                                0x009e80UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL_C_P1_K2_E5                                         (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00  hold 2'b01  increment 2'b10  decrement 2'b11  reserved
+  #define PHY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL_C_P1_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL_C_0_K2_E5                                          (0x3<<2) // Coefficient update request field for cursor tap.
+  #define PHY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL_C_0_K2_E5_SHIFT                                    2
+  #define PHY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL_C_M1_K2_E5                                         (0x3<<4) // Coefficient update request field for pre-cursor tap.
+  #define PHY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL_C_M1_K2_E5_SHIFT                                   4
+  #define PHY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL_INITIALIZE_K2_E5                                   (0x1<<6) // Coefficient update initialize field.
+  #define PHY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL_INITIALIZE_K2_E5_SHIFT                             6
+  #define PHY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL_PRESET_K2_E5                                       (0x1<<7) // Coefficient update preset field.
+  #define PHY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL_PRESET_K2_E5_SHIFT                                 7
+#define PHY_NW_IP_REG_LN1_LT_TX_STATUS_REPORT_CTRL_K2_E5                                                     0x009e88UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LT_TX_STATUS_REPORT_CTRL_C_P1_K2_E5                                              (0x3<<0) // Status report field for post-cursor tap. 2'b00  not updated 2'b01  minimum 2'b10  updated 2'b11  maximum
+  #define PHY_NW_IP_REG_LN1_LT_TX_STATUS_REPORT_CTRL_C_P1_K2_E5_SHIFT                                        0
+  #define PHY_NW_IP_REG_LN1_LT_TX_STATUS_REPORT_CTRL_C_0_K2_E5                                               (0x3<<2) // Status report field for cursor tap.
+  #define PHY_NW_IP_REG_LN1_LT_TX_STATUS_REPORT_CTRL_C_0_K2_E5_SHIFT                                         2
+  #define PHY_NW_IP_REG_LN1_LT_TX_STATUS_REPORT_CTRL_C_M1_K2_E5                                              (0x3<<4) // Status report field for pre-cursor tap.
+  #define PHY_NW_IP_REG_LN1_LT_TX_STATUS_REPORT_CTRL_C_M1_K2_E5_SHIFT                                        4
+  #define PHY_NW_IP_REG_LN1_LT_TX_STATUS_REPORT_CTRL_LOCAL_RX_READY_K2_E5                                    (0x1<<6) // Status report field to indicate local receiver is ready.  Should be set based on LTSM output of corresponding variable.
+  #define PHY_NW_IP_REG_LN1_LT_TX_STATUS_REPORT_CTRL_LOCAL_RX_READY_K2_E5_SHIFT                              6
+#define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS0_K2_E5                                                      0x009ec0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS0_CURRENT_K2_E5                                            (0x7<<0) // Current state of LTSM. 0x0  INITIALIZE 0x1  SEND_TRAINING 0x2  TRAIN_REMOTE 0x3  TRAIN_LOCAL 0x4  S7 0x5  TRAINING_FAILURE 0x6  LINK_READY 0x7  SEND_DATA
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS0_CURRENT_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS0_PREV1_K2_E5                                              (0x7<<4) // One state previous.
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS0_PREV1_K2_E5_SHIFT                                        4
+#define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS1_K2_E5                                                      0x009ec4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS1_PREV2_K2_E5                                              (0x7<<0) // Two states previous.
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS1_PREV2_K2_E5_SHIFT                                        0
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS1_PREV3_K2_E5                                              (0x7<<4) // Three states previous.
+  #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS1_PREV3_K2_E5_SHIFT                                        4
+#define PHY_NW_IP_REG_LN1_LT_RX_CTRL0_K2_E5                                                                  0x009f00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LT_RX_CTRL0_CLEAR_K2_E5                                                          (0x1<<0) // Synchronous reset for LT Rx block.
+  #define PHY_NW_IP_REG_LN1_LT_RX_CTRL0_CLEAR_K2_E5_SHIFT                                                    0
+  #define PHY_NW_IP_REG_LN1_LT_RX_CTRL0_TRAINING_K2_E5                                                       (0x1<<1) // This is the 802.3 defined training variable.  It should be set according to corresponding LTSM output.
+  #define PHY_NW_IP_REG_LN1_LT_RX_CTRL0_TRAINING_K2_E5_SHIFT                                                 1
+#define PHY_NW_IP_REG_LN1_LT_RX_PRBS_CTRL0_K2_E5                                                             0x009f08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_CTRL0_POLYNOMIAL_K2_E5                                                (0x7<<0) // Selects between CL72 and CL93 PRBS patterns. 0  CL72 1 + x^9 + x^11 1  CL93 1 + x^5 + x^6 + x^10 + x^11 2  CL93 1 + x^5 + x^6 + x^9 + x^11 3  CL93 1 + x^4 + x^6 + x^8 + x^11 4  CL93 1 + x^4 + x^6 + x^7 + x^11
+  #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_CTRL0_POLYNOMIAL_K2_E5_SHIFT                                          0
+#define PHY_NW_IP_REG_LN1_LT_RX_PRBS_CTRL1_K2_E5                                                             0x009f0cUL //Access:RW   DataWidth:0x8    // Maximum number  of PRBS bit errors allowed in single LT frame for PRBS lock to be achieved.
+#define PHY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS0_K2_E5                                                           0x009f14UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS0_UPDATE_K2_E5                                                  (0x1<<0) // Assertion indicates that PRBS status information has been updated.
+  #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS0_UPDATE_K2_E5_SHIFT                                            0
+  #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS0_LOCK_K2_E5                                                    (0x1<<1) // Indicates that a valid PRBS pattern has been detected in receiver LT frame.
+  #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS0_LOCK_K2_E5_SHIFT                                              1
+#define PHY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS1_K2_E5                                                           0x009f18UL //Access:R    DataWidth:0x8    // Number of bit errors in PRBS pattern since last lock assertion event.
+#define PHY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS2_K2_E5                                                           0x009f1cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS2_ERROR_COUNT_11_8_K2_E5                                        (0xf<<0) // Same as above.
+  #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS2_ERROR_COUNT_11_8_K2_E5_SHIFT                                  0
+#define PHY_NW_IP_REG_LN1_LT_RX_FRAME_CTRL_K2_E5                                                             0x009f40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LT_RX_FRAME_CTRL_CLEAR_COUNT_K2_E5                                               (0x1<<0) // Clears both the absolute and erroneous frame counters.
+  #define PHY_NW_IP_REG_LN1_LT_RX_FRAME_CTRL_CLEAR_COUNT_K2_E5_SHIFT                                         0
+#define PHY_NW_IP_REG_LN1_LT_RX_FRAME_STATUS0_K2_E5                                                          0x009f4cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LT_RX_FRAME_STATUS0_FRAME_LOCK_K2_E5                                             (0x1<<0) // Indicates that the receiver has locked to incoming LT frames.
+  #define PHY_NW_IP_REG_LN1_LT_RX_FRAME_STATUS0_FRAME_LOCK_K2_E5_SHIFT                                       0
+#define PHY_NW_IP_REG_LN1_LT_RX_FRAME_STATUS1_K2_E5                                                          0x009f50UL //Access:R    DataWidth:0x8    // Total number of received frames since frame lock.
+#define PHY_NW_IP_REG_LN1_LT_RX_FRAME_STATUS2_K2_E5                                                          0x009f54UL //Access:R    DataWidth:0x8    // Same as above.
+#define PHY_NW_IP_REG_LN1_LT_RX_FRAME_STATUS3_K2_E5                                                          0x009f58UL //Access:R    DataWidth:0x8    // Total number of received frames  with a PRBS, DME, or framing error since frame lock.
+#define PHY_NW_IP_REG_LN1_LT_RX_FRAME_STATUS4_K2_E5                                                          0x009f5cUL //Access:R    DataWidth:0x8    // Same as above.
+#define PHY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS_K2_E5                                              0x009f80UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS_C_P1_K2_E5                                       (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00  hold 2'b01  increment 2'b10  decrement 2'b11  reserved
+  #define PHY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS_C_P1_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS_C_0_K2_E5                                        (0x3<<2) // Received coefficient update request field for cursor tap.
+  #define PHY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS_C_0_K2_E5_SHIFT                                  2
+  #define PHY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS_C_M1_K2_E5                                       (0x3<<4) // Received coefficient update request field for pre-cursor tap.
+  #define PHY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS_C_M1_K2_E5_SHIFT                                 4
+  #define PHY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS_INITIALIZE_K2_E5                                 (0x1<<6) // Received coefficient update initialize field.
+  #define PHY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS_INITIALIZE_K2_E5_SHIFT                           6
+  #define PHY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS_PRESET_K2_E5                                     (0x1<<7) // Received coefficient update preset field.
+  #define PHY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS_PRESET_K2_E5_SHIFT                               7
+#define PHY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS_K2_E5                                                          0x009f88UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS_C_P1_K2_E5                                                   (0x3<<0) // Received status report field for post-cursor tap. 2'b00  not updated 2'b01  minimum 2'b10  updated 2'b11  maximum
+  #define PHY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS_C_P1_K2_E5_SHIFT                                             0
+  #define PHY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS_C_0_K2_E5                                                    (0x3<<2) // Received status report field for cursor tap.
+  #define PHY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS_C_0_K2_E5_SHIFT                                              2
+  #define PHY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS_C_M1_K2_E5                                                   (0x3<<4) // Received status report field for pre-cursor tap.
+  #define PHY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS_C_M1_K2_E5_SHIFT                                             4
+  #define PHY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS_LOCAL_RX_READY_K2_E5                                         (0x1<<6) // Received status report field to indicate local receiver is ready.
+  #define PHY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS_LOCAL_RX_READY_K2_E5_SHIFT                                   6
+  #define PHY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS_DME_ERROR_K2_E5                                              (0x1<<7) // Indicates differential manchester decoding error.  Not sticky.
+  #define PHY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS_DME_ERROR_K2_E5_SHIFT                                        7
+#define PHY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_K2_E5                                                        0x00a000UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_K2_E5                                    (0x1<<0) // RX clock loopback mode enable.   0x0 - mission mode 0x1 - select recovered clock from CDR as source of half-rate TX clock path.
+  #define PHY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_K2_E5                                    (0x1<<1) // TX clock loopback mode enable.  0x0 - mission mode 0x1 - MUX half-rate TX clock into LEQ gain stage.
+  #define PHY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_K2_E5                                      (0x1<<2) // Far-End Analog FEA loopback mode enable.  0x0 - mission mode 0x1 - loop back parallel data from RX data path to TX data path internal to AFE
+  #define PHY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_K2_E5_SHIFT                                2
+  #define PHY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_K2_E5                                      (0x1<<3) // Near-End Analog NEA loopback mode enable.  0x0 - mission mode 0x1 - loop back quarter rate data from TX data path to RX data path internal to AFE.
+  #define PHY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_K2_E5_SHIFT                                3
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1883_K2_E5                                                     0x00a004UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1883_RESERVEDFIELD2084_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1883_RESERVEDFIELD2084_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1883_RESERVEDFIELD2085_K2_E5                                 (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1883_RESERVEDFIELD2085_K2_E5_SHIFT                           2
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1883_RESERVEDFIELD2086_K2_E5                                 (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1883_RESERVEDFIELD2086_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1884_K2_E5                                                     0x00a008UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1884_RESERVEDFIELD2087_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1884_RESERVEDFIELD2087_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1884_RESERVEDFIELD2088_K2_E5                                 (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1884_RESERVEDFIELD2088_K2_E5_SHIFT                           2
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1884_RESERVEDFIELD2089_K2_E5                                 (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1884_RESERVEDFIELD2089_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1885_K2_E5                                                     0x00a00cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1885_RESERVEDFIELD2090_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1885_RESERVEDFIELD2090_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1886_K2_E5                                                     0x00a010UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1886_RESERVEDFIELD2091_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1886_RESERVEDFIELD2091_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1886_RESERVEDFIELD2092_K2_E5                                 (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1886_RESERVEDFIELD2092_K2_E5_SHIFT                           1
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1887_K2_E5                                                     0x00a014UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1887_RESERVEDFIELD2093_K2_E5                                 (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1887_RESERVEDFIELD2093_K2_E5_SHIFT                           2
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1888_K2_E5                                                     0x00a018UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1888_RESERVEDFIELD2094_K2_E5                                 (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1888_RESERVEDFIELD2094_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1889_K2_E5                                                     0x00a040UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1889_RESERVEDFIELD2095_K2_E5                                 (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1889_RESERVEDFIELD2095_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1889_RESERVEDFIELD2096_K2_E5                                 (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1889_RESERVEDFIELD2096_K2_E5_SHIFT                           4
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1889_RESERVEDFIELD2097_K2_E5                                 (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1889_RESERVEDFIELD2097_K2_E5_SHIFT                           6
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1890_K2_E5                                                     0x00a048UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1890_RESERVEDFIELD2098_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1890_RESERVEDFIELD2098_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1890_RESERVEDFIELD2099_K2_E5                                 (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1890_RESERVEDFIELD2099_K2_E5_SHIFT                           2
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1891_K2_E5                                                     0x00a04cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1891_RESERVEDFIELD2100_K2_E5                                 (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1891_RESERVEDFIELD2100_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1892_K2_E5                                                     0x00a050UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1892_RESERVEDFIELD2101_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1892_RESERVEDFIELD2101_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1892_RESERVEDFIELD2102_K2_E5                                 (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1892_RESERVEDFIELD2102_K2_E5_SHIFT                           2
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1893_K2_E5                                                     0x00a058UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1893_RESERVEDFIELD2103_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1893_RESERVEDFIELD2103_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1893_RESERVEDFIELD2104_K2_E5                                 (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1893_RESERVEDFIELD2104_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1894_K2_E5                                                     0x00a064UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1894_RESERVEDFIELD2105_K2_E5                                 (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1894_RESERVEDFIELD2105_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1894_RESERVEDFIELD2106_K2_E5                                 (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1894_RESERVEDFIELD2106_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1895_K2_E5                                                     0x00a06cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1895_RESERVEDFIELD2107_K2_E5                                 (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1895_RESERVEDFIELD2107_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1895_RESERVEDFIELD2108_K2_E5                                 (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1895_RESERVEDFIELD2108_K2_E5_SHIFT                           3
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1895_RESERVEDFIELD2109_K2_E5                                 (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1895_RESERVEDFIELD2109_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1896_K2_E5                                                     0x00a070UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1896_RESERVEDFIELD2110_K2_E5                                 (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1896_RESERVEDFIELD2110_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1897_K2_E5                                                     0x00a078UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1897_RESERVEDFIELD2111_K2_E5                                 (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1897_RESERVEDFIELD2111_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN2_TOP_DPL_TXDP_CTRL1_K2_E5                                                           0x00a088UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_EN_K2_E5                                     (0x1<<0) // Enables register control of TX data path mux in DPL
+  #define PHY_NW_IP_REG_LN2_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_EN_K2_E5_SHIFT                               0
+  #define PHY_NW_IP_REG_LN2_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_VAL_K2_E5                                    (0x7<<1) // Select value for TX data path mux in DPL.  The corresponding mux select override enable must also be set. 0 : TX data from customer logics 1: RX data for Far-End-Digital FED loopback 2: BIST generator 3: AN/802.3 4: LT/802.3 5-7: reserved
+  #define PHY_NW_IP_REG_LN2_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_VAL_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_LN2_TOP_DPL_TXDP_CTRL1_TXPOLARITY_K2_E5                                              (0x1<<4) // TX data polarity control
+  #define PHY_NW_IP_REG_LN2_TOP_DPL_TXDP_CTRL1_TXPOLARITY_K2_E5_SHIFT                                        4
+  #define PHY_NW_IP_REG_LN2_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_K2_E5                                   (0x1<<5) // Controls tx_en for Far-End-Digital FED loopback mode.  In FED loopback mode, tx_en will be set when this field is set to 1 and rxvalid is 1.
+  #define PHY_NW_IP_REG_LN2_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_K2_E5_SHIFT                             5
+#define PHY_NW_IP_REG_LN2_TOP_DPL_RXDP_CTRL1_K2_E5                                                           0x00a090UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_K2_E5                                             (0x1<<0) // A mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
+  #define PHY_NW_IP_REG_LN2_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_K2_E5_SHIFT                                       0
+  #define PHY_NW_IP_REG_LN2_TOP_DPL_RXDP_CTRL1_BIT_STRIP_EVEN_K2_E5                                          (0x1<<1) // A bit stripping selection for RX data path in the DPL 1: Even bits stripped from RX data 0: Odd bits stripped from Rx data
+  #define PHY_NW_IP_REG_LN2_TOP_DPL_RXDP_CTRL1_BIT_STRIP_EVEN_K2_E5_SHIFT                                    1
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1898_K2_E5                                                     0x00a094UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1898_RESERVEDFIELD2112_K2_E5                                 (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1898_RESERVEDFIELD2112_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1898_RESERVEDFIELD2113_K2_E5                                 (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1898_RESERVEDFIELD2113_K2_E5_SHIFT                           3
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1899_K2_E5                                                     0x00a098UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1899_RESERVEDFIELD2114_K2_E5                                 (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1899_RESERVEDFIELD2114_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1899_RESERVEDFIELD2115_K2_E5                                 (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1899_RESERVEDFIELD2115_K2_E5_SHIFT                           3
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1899_RESERVEDFIELD2116_K2_E5                                 (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1899_RESERVEDFIELD2116_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN2_TOP_PHY_IF_STATUS_K2_E5                                                            0x00a09cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_PHY_IF_STATUS_LN_OK_K2_E5                                                    (0x1<<0) // LANE OK status
+  #define PHY_NW_IP_REG_LN2_TOP_PHY_IF_STATUS_LN_OK_K2_E5_SHIFT                                              0
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1900_K2_E5                                                     0x00a0c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1900_RESERVEDFIELD2117_K2_E5                                 (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1900_RESERVEDFIELD2117_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1900_RESERVEDFIELD2118_K2_E5                                 (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1900_RESERVEDFIELD2118_K2_E5_SHIFT                           3
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1901_K2_E5                                                     0x00a0c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1901_RESERVEDFIELD2119_K2_E5                                 (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1901_RESERVEDFIELD2119_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1901_RESERVEDFIELD2120_K2_E5                                 (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1901_RESERVEDFIELD2120_K2_E5_SHIFT                           3
+#define PHY_NW_IP_REG_LN2_TOP_LN_STAT_CTRL0_K2_E5                                                            0x00a0e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_LN_STAT_CTRL0_RXVALID_K2_E5                                                  (0x1<<0) // rxvalid status output
+  #define PHY_NW_IP_REG_LN2_TOP_LN_STAT_CTRL0_RXVALID_K2_E5_SHIFT                                            0
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1902_K2_E5                                                     0x00a0e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1902_RESERVEDFIELD2121_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1902_RESERVEDFIELD2121_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1902_RESERVEDFIELD2122_K2_E5                                 (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1902_RESERVEDFIELD2122_K2_E5_SHIFT                           1
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1903_K2_E5                                                     0x00a0e8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1903_RESERVEDFIELD2123_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1903_RESERVEDFIELD2123_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN2_TOP_LN_CTRL_OVR0_K2_E5                                                             0x00a0ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_LN_CTRL_OVR0_OVR_EN_K2_E5                                                    (0x1<<0) // override enable for lnX_ctrl_*_i signals in this register
+  #define PHY_NW_IP_REG_LN2_TOP_LN_CTRL_OVR0_OVR_EN_K2_E5_SHIFT                                              0
+  #define PHY_NW_IP_REG_LN2_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_K2_E5                                             (0x7<<1) // lnX_data_width_i override value for TX.  It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-quarter width 10b, others, reserved.
+  #define PHY_NW_IP_REG_LN2_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_K2_E5_SHIFT                                       1
+  #define PHY_NW_IP_REG_LN2_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_K2_E5                                             (0x7<<4) // lnX_data_width_i override value for RX.  It takes effect when ovr_en is 1.
+  #define PHY_NW_IP_REG_LN2_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_K2_E5_SHIFT                                       4
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1904_K2_E5                                                     0x00a0f0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1904_RESERVEDFIELD2124_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1904_RESERVEDFIELD2124_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1904_RESERVEDFIELD2125_K2_E5                                 (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1904_RESERVEDFIELD2125_K2_E5_SHIFT                           3
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1904_RESERVEDFIELD2126_K2_E5                                 (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1904_RESERVEDFIELD2126_K2_E5_SHIFT                           4
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1904_RESERVEDFIELD2127_K2_E5                                 (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1904_RESERVEDFIELD2127_K2_E5_SHIFT                           5
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1905_K2_E5                                                     0x00a0f4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1905_RESERVEDFIELD2128_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1905_RESERVEDFIELD2128_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1905_RESERVEDFIELD2129_K2_E5                                 (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1905_RESERVEDFIELD2129_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1906_K2_E5                                                     0x00a0f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1906_RESERVEDFIELD2130_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1906_RESERVEDFIELD2130_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1906_RESERVEDFIELD2131_K2_E5                                 (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1906_RESERVEDFIELD2131_K2_E5_SHIFT                           5
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1906_RESERVEDFIELD2132_K2_E5                                 (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1906_RESERVEDFIELD2132_K2_E5_SHIFT                           6
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1907_K2_E5                                                     0x00a0fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1907_RESERVEDFIELD2133_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1907_RESERVEDFIELD2133_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1907_RESERVEDFIELD2134_K2_E5                                 (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1907_RESERVEDFIELD2134_K2_E5_SHIFT                           1
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1907_RESERVEDFIELD2135_K2_E5                                 (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1907_RESERVEDFIELD2135_K2_E5_SHIFT                           3
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1908_K2_E5                                                     0x00a100UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1908_RESERVEDFIELD2136_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1908_RESERVEDFIELD2136_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1908_RESERVEDFIELD2137_K2_E5                                 (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1908_RESERVEDFIELD2137_K2_E5_SHIFT                           1
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1908_RESERVEDFIELD2138_K2_E5                                 (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1908_RESERVEDFIELD2138_K2_E5_SHIFT                           2
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1909_K2_E5                                                     0x00a108UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1909_RESERVEDFIELD2139_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1909_RESERVEDFIELD2139_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1909_RESERVEDFIELD2140_K2_E5                                 (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1909_RESERVEDFIELD2140_K2_E5_SHIFT                           1
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1910_K2_E5                                                     0x00a10cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1910_RESERVEDFIELD2141_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1910_RESERVEDFIELD2141_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1910_RESERVEDFIELD2142_K2_E5                                 (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1910_RESERVEDFIELD2142_K2_E5_SHIFT                           1
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1911_K2_E5                                                     0x00a120UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1911_RESERVEDFIELD2143_K2_E5                                 (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1911_RESERVEDFIELD2143_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1911_RESERVEDFIELD2144_K2_E5                                 (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1911_RESERVEDFIELD2144_K2_E5_SHIFT                           3
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1911_RESERVEDFIELD2145_K2_E5                                 (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1911_RESERVEDFIELD2145_K2_E5_SHIFT                           6
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1911_RESERVEDFIELD2146_K2_E5                                 (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1911_RESERVEDFIELD2146_K2_E5_SHIFT                           7
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1912_K2_E5                                                     0x00a124UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1912_RESERVEDFIELD2147_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1912_RESERVEDFIELD2147_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1912_RESERVEDFIELD2148_K2_E5                                 (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1912_RESERVEDFIELD2148_K2_E5_SHIFT                           1
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1912_RESERVEDFIELD2149_K2_E5                                 (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1912_RESERVEDFIELD2149_K2_E5_SHIFT                           2
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1912_RESERVEDFIELD2150_K2_E5                                 (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1912_RESERVEDFIELD2150_K2_E5_SHIFT                           4
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1912_RESERVEDFIELD2151_K2_E5                                 (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1912_RESERVEDFIELD2151_K2_E5_SHIFT                           5
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1912_RESERVEDFIELD2152_K2_E5                                 (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1912_RESERVEDFIELD2152_K2_E5_SHIFT                           6
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1913_K2_E5                                                     0x00a128UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1913_RESERVEDFIELD2153_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1913_RESERVEDFIELD2153_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1914_K2_E5                                                     0x00a12cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1914_RESERVEDFIELD2154_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1914_RESERVEDFIELD2154_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1915_K2_E5                                                     0x00a130UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1915_RESERVEDFIELD2155_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1915_RESERVEDFIELD2155_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1915_RESERVEDFIELD2156_K2_E5                                 (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1915_RESERVEDFIELD2156_K2_E5_SHIFT                           1
+#define PHY_NW_IP_REG_LN2_TOP_ERR_CTRL1_K2_E5                                                                0x00a140UL //Access:RW   DataWidth:0x8    // lower 8-bits of 16-bit lane error code.  0x0 - indicates that there is no error rest - reserved
+#define PHY_NW_IP_REG_LN2_TOP_ERR_CTRL2_K2_E5                                                                0x00a144UL //Access:RW   DataWidth:0x8    // higher 8-bits of 16-bit lane error code.  0x0 - indicates that there is no error rest - reserved
+#define PHY_NW_IP_REG_LN2_TOP_ERR_CTRL3_K2_E5                                                                0x00a148UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_TOP_ERR_CTRL3_LANE_ERR_K2_E5                                                     (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macro has an internal error detected by firmware. Lane error code can be used to isolate error event.
+  #define PHY_NW_IP_REG_LN2_TOP_ERR_CTRL3_LANE_ERR_K2_E5_SHIFT                                               0
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1916_K2_E5                                               0x00a240UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1916_RESERVEDFIELD2157_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1916_RESERVEDFIELD2157_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1917_K2_E5                                               0x00a244UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1917_RESERVEDFIELD2158_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1917_RESERVEDFIELD2158_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1918_K2_E5                                               0x00a284UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1918_RESERVEDFIELD2159_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1918_RESERVEDFIELD2159_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1918_RESERVEDFIELD2160_K2_E5                           (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1918_RESERVEDFIELD2160_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1919_K2_E5                                               0x00a288UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1919_RESERVEDFIELD2161_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1919_RESERVEDFIELD2161_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1920_K2_E5                                               0x00a298UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1921_K2_E5                                               0x00a29cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1921_RESERVEDFIELD2163_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1921_RESERVEDFIELD2163_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1922_K2_E5                                               0x00a2a0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1923_K2_E5                                               0x00a2a4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1923_RESERVEDFIELD2165_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1923_RESERVEDFIELD2165_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1924_K2_E5                                               0x00a2a8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1925_K2_E5                                               0x00a2acUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1925_RESERVEDFIELD2167_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1925_RESERVEDFIELD2167_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1926_K2_E5                                               0x00a2b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1926_RESERVEDFIELD2168_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1926_RESERVEDFIELD2168_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1927_K2_E5                                               0x00a2c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1927_RESERVEDFIELD2169_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1927_RESERVEDFIELD2169_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1928_K2_E5                                               0x00a2c4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1929_K2_E5                                               0x00a2c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1929_RESERVEDFIELD2171_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1929_RESERVEDFIELD2171_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1930_K2_E5                                               0x00a2d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1930_RESERVEDFIELD2172_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1930_RESERVEDFIELD2172_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1931_K2_E5                                               0x00a2d8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1932_K2_E5                                               0x00a2dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1932_RESERVEDFIELD2174_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1932_RESERVEDFIELD2174_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1933_K2_E5                                               0x00a2e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1933_RESERVEDFIELD2175_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1933_RESERVEDFIELD2175_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1934_K2_E5                                               0x00a2e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1934_RESERVEDFIELD2176_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1934_RESERVEDFIELD2176_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1934_RESERVEDFIELD2177_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1934_RESERVEDFIELD2177_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1934_RESERVEDFIELD2178_K2_E5                           (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1934_RESERVEDFIELD2178_K2_E5_SHIFT                     2
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1934_RESERVEDFIELD2179_K2_E5                           (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1934_RESERVEDFIELD2179_K2_E5_SHIFT                     3
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1935_K2_E5                                               0x00a2ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1935_RESERVEDFIELD2180_K2_E5                           (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1935_RESERVEDFIELD2180_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1936_K2_E5                                               0x00a2f0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1936_RESERVEDFIELD2181_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1936_RESERVEDFIELD2181_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1937_K2_E5                                               0x00a2f4UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1938_K2_E5                                               0x00a2f8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1938_RESERVEDFIELD2183_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1938_RESERVEDFIELD2183_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS2_K2_E5                                                       0x00a2fcUL //Access:R    DataWidth:0x8    // Binary-coded DLPF control input to the CDR
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS3_K2_E5                                                       0x00a300UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8_K2_E5                                        (0x1<<0) // Binary-coded DLPF control input to the CDR
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8_K2_E5_SHIFT                                  0
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS4_K2_E5                                                       0x00a304UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH_K2_E5                                       (0x1<<0) // Indicates that DLPF control input to CDR is too high
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW_K2_E5                                        (0x1<<1) // Indicates that DLPF control input to CDR is too low
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW_K2_E5_SHIFT                                  1
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST_K2_E5                                           (0x1<<2) // CDR loss of lock indicator.  1 means lock has been lost. Once lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by setting set lock_en_i to 0.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST_K2_E5_SHIFT                                     2
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS5_K2_E5                                                       0x00a310UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS5_LOCKED_K2_E5                                              (0x1<<0) // CDR lock indicator.  1 means lock is achieved. It is cleared when lock detector is disabled by setting set lock_en_i to 0.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS5_LOCKED_K2_E5_SHIFT                                        0
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_INTEGRAL_STATUS0_K2_E5                                                   0x00a314UL //Access:R    DataWidth:0x8    // Value of the accumulator in the CDR integral path
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_INTEGRAL_STATUS1_K2_E5                                                   0x00a318UL //Access:R    DataWidth:0x8    // Value of the accumulator in the CDR integral path
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_INTEGRAL_STATUS2_K2_E5                                                   0x00a320UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_INTEGRAL_STATUS2_ACCUMULATOR_19_16_K2_E5                               (0xf<<0) // Value of the accumulator in the CDR integral path
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_INTEGRAL_STATUS2_ACCUMULATOR_19_16_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1939_K2_E5                                               0x00a324UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1939_RESERVEDFIELD2184_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1939_RESERVEDFIELD2184_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1939_RESERVEDFIELD2185_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1939_RESERVEDFIELD2185_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1940_K2_E5                                               0x00a328UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1941_K2_E5                                               0x00a32cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1942_K2_E5                                               0x00a330UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1943_K2_E5                                               0x00a334UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1943_RESERVEDFIELD2189_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1943_RESERVEDFIELD2189_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1943_RESERVEDFIELD2190_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1943_RESERVEDFIELD2190_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1944_K2_E5                                               0x00a338UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1945_K2_E5                                               0x00a33cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1946_K2_E5                                               0x00a380UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1947_K2_E5                                               0x00a384UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1947_RESERVEDFIELD2194_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1947_RESERVEDFIELD2194_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1948_K2_E5                                               0x00a388UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1948_RESERVEDFIELD2195_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1948_RESERVEDFIELD2195_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1948_RESERVEDFIELD2196_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1948_RESERVEDFIELD2196_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1949_K2_E5                                               0x00a38cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1950_K2_E5                                               0x00a3a0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1951_K2_E5                                               0x00a3a4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1951_RESERVEDFIELD2199_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1951_RESERVEDFIELD2199_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1951_RESERVEDFIELD2200_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1951_RESERVEDFIELD2200_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1951_RESERVEDFIELD2201_K2_E5                           (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1951_RESERVEDFIELD2201_K2_E5_SHIFT                     2
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1952_K2_E5                                               0x00a3a8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1953_K2_E5                                               0x00a3acUL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1954_K2_E5                                               0x00a3b0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1954_RESERVEDFIELD2204_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1954_RESERVEDFIELD2204_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1955_K2_E5                                               0x00a3b4UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1956_K2_E5                                               0x00a3b8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1957_K2_E5                                               0x00a3bcUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1957_RESERVEDFIELD2207_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1957_RESERVEDFIELD2207_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1958_K2_E5                                               0x00a3c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1958_RESERVEDFIELD2208_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1958_RESERVEDFIELD2208_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1959_K2_E5                                              0x00a400UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1959_RESERVEDFIELD2209_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1959_RESERVEDFIELD2209_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1959_RESERVEDFIELD2210_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1959_RESERVEDFIELD2210_K2_E5_SHIFT                    3
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1959_RESERVEDFIELD2211_K2_E5                          (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1959_RESERVEDFIELD2211_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1960_K2_E5                                              0x00a404UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1960_RESERVEDFIELD2212_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1960_RESERVEDFIELD2212_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1961_K2_E5                                              0x00a410UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1961_RESERVEDFIELD2213_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1961_RESERVEDFIELD2213_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1962_K2_E5                                              0x00a418UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1963_K2_E5                                              0x00a428UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1963_RESERVEDFIELD2215_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1963_RESERVEDFIELD2215_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1964_K2_E5                                              0x00a42cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1964_RESERVEDFIELD2216_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1964_RESERVEDFIELD2216_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1964_RESERVEDFIELD2217_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1964_RESERVEDFIELD2217_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1964_RESERVEDFIELD2218_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1964_RESERVEDFIELD2218_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1965_K2_E5                                              0x00a430UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1965_RESERVEDFIELD2219_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1965_RESERVEDFIELD2219_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1966_K2_E5                                              0x00a440UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1966_RESERVEDFIELD2220_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1966_RESERVEDFIELD2220_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1966_RESERVEDFIELD2221_K2_E5                          (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1966_RESERVEDFIELD2221_K2_E5_SHIFT                    5
+#define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1967_K2_E5                                              0x00a444UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1967_RESERVEDFIELD2222_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1967_RESERVEDFIELD2222_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1967_RESERVEDFIELD2223_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1967_RESERVEDFIELD2223_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1967_RESERVEDFIELD2224_K2_E5                          (0xf<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1967_RESERVEDFIELD2224_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1968_K2_E5                                              0x00a460UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1968_RESERVEDFIELD2225_K2_E5                          (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1968_RESERVEDFIELD2225_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1968_RESERVEDFIELD2226_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1968_RESERVEDFIELD2226_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1969_K2_E5                                              0x00a464UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1969_RESERVEDFIELD2227_K2_E5                          (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1969_RESERVEDFIELD2227_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1969_RESERVEDFIELD2228_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1969_RESERVEDFIELD2228_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1970_K2_E5                                              0x00a468UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1970_RESERVEDFIELD2229_K2_E5                          (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1970_RESERVEDFIELD2229_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1971_K2_E5                                              0x00a46cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1971_RESERVEDFIELD2230_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1971_RESERVEDFIELD2230_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1971_RESERVEDFIELD2231_K2_E5                          (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1971_RESERVEDFIELD2231_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1972_K2_E5                                              0x00a480UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1972_RESERVEDFIELD2232_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1972_RESERVEDFIELD2232_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1972_RESERVEDFIELD2233_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1972_RESERVEDFIELD2233_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1973_K2_E5                                              0x00a484UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1973_RESERVEDFIELD2234_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1973_RESERVEDFIELD2234_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1974_K2_E5                                              0x00a488UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1975_K2_E5                                              0x00a48cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1976_K2_E5                                              0x00a490UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1977_K2_E5                                              0x00a494UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1977_RESERVEDFIELD2238_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1977_RESERVEDFIELD2238_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1978_K2_E5                                              0x00a4c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1978_RESERVEDFIELD2239_K2_E5                          (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1978_RESERVEDFIELD2239_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1979_K2_E5                                                    0x00a600UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1979_RESERVEDFIELD2240_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1979_RESERVEDFIELD2240_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1979_RESERVEDFIELD2241_K2_E5                                (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1979_RESERVEDFIELD2241_K2_E5_SHIFT                          1
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1980_K2_E5                                                    0x00a604UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1981_K2_E5                                                    0x00a608UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1982_K2_E5                                                    0x00a60cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1982_RESERVEDFIELD2244_K2_E5                                (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1982_RESERVEDFIELD2244_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1982_RESERVEDFIELD2245_K2_E5                                (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1982_RESERVEDFIELD2245_K2_E5_SHIFT                          4
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1983_K2_E5                                                    0x00a610UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1984_K2_E5                                                    0x00a614UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1984_RESERVEDFIELD2247_K2_E5                                (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1984_RESERVEDFIELD2247_K2_E5_SHIFT                          0
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1985_K2_E5                                                    0x00a618UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1985_RESERVEDFIELD2248_K2_E5                                (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1985_RESERVEDFIELD2248_K2_E5_SHIFT                          0
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1986_K2_E5                                                    0x00a61cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1986_RESERVEDFIELD2249_K2_E5                                (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1986_RESERVEDFIELD2249_K2_E5_SHIFT                          0
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1987_K2_E5                                                    0x00a620UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1988_K2_E5                                                    0x00a624UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1988_RESERVEDFIELD2251_K2_E5                                (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1988_RESERVEDFIELD2251_K2_E5_SHIFT                          0
+#define PHY_NW_IP_REG_LN2_ANEG_CFG10_K2_E5                                                                   0x00a628UL //Access:RW   DataWidth:0x8    // Seed provided to the transmit nonce generator polynomial
+#define PHY_NW_IP_REG_LN2_ANEG_CFG11_K2_E5                                                                   0x00a62cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_CFG11_PSEUDO_SEL_K2_E5                                                      (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
+  #define PHY_NW_IP_REG_LN2_ANEG_CFG11_PSEUDO_SEL_K2_E5_SHIFT                                                0
+#define PHY_NW_IP_REG_LN2_ANEG_CTRL0_K2_E5                                                                   0x00a630UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_CTRL0_AUTONEG_RESTART_K2_E5                                                 (0x1<<0) // Restarts AN that is already in progress or otherwise completed.  Reset is triggered by rising edge of this signal.  Not self clearing.
+  #define PHY_NW_IP_REG_LN2_ANEG_CTRL0_AUTONEG_RESTART_K2_E5_SHIFT                                           0
+  #define PHY_NW_IP_REG_LN2_ANEG_CTRL0_RESERVEDFIELD2252_K2_E5                                               (0x7f<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_CTRL0_RESERVEDFIELD2252_K2_E5_SHIFT                                         1
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1989_K2_E5                                                    0x00a634UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1989_RESERVEDFIELD2253_K2_E5                                (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1989_RESERVEDFIELD2253_K2_E5_SHIFT                          4
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1989_RESERVEDFIELD2254_K2_E5                                (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1989_RESERVEDFIELD2254_K2_E5_SHIFT                          5
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1989_RESERVEDFIELD2255_K2_E5                                (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1989_RESERVEDFIELD2255_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1990_K2_E5                                                    0x00a638UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1990_RESERVEDFIELD2256_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1990_RESERVEDFIELD2256_K2_E5_SHIFT                          0
+#define PHY_NW_IP_REG_LN2_ANEG_STATUS0_K2_E5                                                                 0x00a640UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_LP_AUTONEG_ABLE_K2_E5                                               (0x1<<0) // The link partner Auto-Negotiation ability bit shall be set to one to indicate that the link partner is able to participate in the Auto-Negotiation function. This bit shall be reset to zero if the link partner is not Auto- Negotiation able.
+  #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_LP_AUTONEG_ABLE_K2_E5_SHIFT                                         0
+  #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_LINK_STATUS_K2_E5                                                   (0x1<<2) // Local link Status.  When read as a one, it indicates that the PMA/PMD has determined that a valid link has been established i.e. link_status[HDC] equals OK. When read as a zero, it indicates that the link is not valid.
+  #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_LINK_STATUS_K2_E5_SHIFT                                             2
+  #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_AUTONEG_ABILITY_K2_E5                                               (0x1<<3) // Autoneg ability.  When read as a one, it indicates that the PMA/PMD has the ability to perform Auto-Negotiation.  When read as a zero, it indicates that the PMA/PMD lacks the ability to perform Auto-Negotiation.
+  #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_AUTONEG_ABILITY_K2_E5_SHIFT                                         3
+  #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_AUTONEG_REMOTE_FAULT_K2_E5                                          (0x1<<4) // Remote Fault
+  #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_AUTONEG_REMOTE_FAULT_K2_E5_SHIFT                                    4
+  #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_AUTONEG_COMPLETE_K2_E5                                              (0x1<<5) // Autoneg has completed and autoneg arbitration FSM is in AN GOOD state.
+  #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_AUTONEG_COMPLETE_K2_E5_SHIFT                                        5
+#define PHY_NW_IP_REG_LN2_ANEG_STATUS1_K2_E5                                                                 0x00a644UL //Access:W    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_PAGE_RX_K2_E5                                                       (0x1<<0) // Page Received.   To clear it, write 1 to it.
+  #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_PAGE_RX_K2_E5_SHIFT                                                 0
+  #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_AN_LINK_GOOD_K2_E5                                                  (0x1<<1) // Autoneg has completed and autoneg arbitration FSM is in either AN GOOD CHECK or AN GOOD state.
+  #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_AN_LINK_GOOD_K2_E5_SHIFT                                            1
+  #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_PARALLEL_DET_FAULT_K2_E5                                            (0x1<<2) // Autoneg Parallel Detection Fault.  Write 1 to clear it.
+  #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_PARALLEL_DET_FAULT_K2_E5_SHIFT                                      2
+  #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_NP_LOADED_K2_E5                                                     (0x1<<3) // mr_np_loaded status.
+  #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_NP_LOADED_K2_E5_SHIFT                                               3
+  #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_RESERVEDFIELD2257_K2_E5                                             (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_RESERVEDFIELD2257_K2_E5_SHIFT                                       4
+  #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_RESERVEDFIELD2258_K2_E5                                             (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_RESERVEDFIELD2258_K2_E5_SHIFT                                       5
+#define PHY_NW_IP_REG_LN2_ANEG_STATUS_DBG0_K2_E5                                                             0x00a650UL //Access:R    DataWidth:0x8    // One-hot sticky capture of AN FSM states.  Bits 7-0
+#define PHY_NW_IP_REG_LN2_ANEG_STATUS_DBG1_K2_E5                                                             0x00a654UL //Access:R    DataWidth:0x8    // One-hot sticky capture of AN FSM states.  Bits 15-8
+#define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE0_K2_E5                                                              0x00a660UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE0_SELECTOR_K2_E5                                                   (0x1f<<0) // technology Select Field
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE0_SELECTOR_K2_E5_SHIFT                                             0
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE0_ECHOED_NONCE_2_0_K2_E5                                           (0x7<<5) // Echoed Nonce Field bits 2-0.  AN controller generates it.
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE0_ECHOED_NONCE_2_0_K2_E5_SHIFT                                     5
+#define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_K2_E5                                                              0x00a664UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_ECHOED_NONCE_4_3_K2_E5                                           (0x3<<0) // Echoed Nonce Field bits 4-3.    AN controller generates it.
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_ECHOED_NONCE_4_3_K2_E5_SHIFT                                     0
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_PAUSE_K2_E5                                                      (0x1<<2) // Pause advertised ability
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_PAUSE_K2_E5_SHIFT                                                2
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_ASM_DIR_K2_E5                                                    (0x1<<3) // Pause ASM_DIR advertised ability
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_ASM_DIR_K2_E5_SHIFT                                              3
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_C2_K2_E5                                                         (0x1<<4) // Reserved always 0
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_C2_K2_E5_SHIFT                                                   4
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_REMOTE_FAULT_K2_E5                                               (0x1<<5) // Remote Fault Local Device
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_REMOTE_FAULT_K2_E5_SHIFT                                         5
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_NEXT_PAGE_K2_E5                                                  (0x1<<7) // Next Page
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_NEXT_PAGE_K2_E5_SHIFT                                            7
+#define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE2_K2_E5                                                              0x00a668UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE2_TX_NONCE_K2_E5                                                   (0x1f<<0) // Transmitted Nonce Field.  It is generated in hardware.
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE2_TX_NONCE_K2_E5_SHIFT                                             0
+#define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_K2_E5                                                         0x00a66cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_1G_KX_K2_E5                                         (0x1<<0) // 1000Base-KX technology advertised ability
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_1G_KX_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KX4_K2_E5                                       (0x1<<1) // 10GBase-KX4 technology advertised ability
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KX4_K2_E5_SHIFT                                 1
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KR_K2_E5                                        (0x1<<2) // 10GBase-KR technology advertised ability
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KR_K2_E5_SHIFT                                  2
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_40G_KR4_K2_E5                                       (0x1<<3) // 40GBase-KR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_40G_KR4_K2_E5_SHIFT                                 3
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_40G_CR4_K2_E5                                       (0x1<<4) // 40GBase-CR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_40G_CR4_K2_E5_SHIFT                                 4
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_100G_CR10_K2_E5                                     (0x1<<5) // 100GBase-CR10 technology advertised ability
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_100G_CR10_K2_E5_SHIFT                               5
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KP4_K2_E5                                      (0x1<<6) // 100GBase-KP4 technology advertised ability
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KP4_K2_E5_SHIFT                                6
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KR4_K2_E5                                      (0x1<<7) // 100GBase-KR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KR4_K2_E5_SHIFT                                7
+#define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH1_K2_E5                                                         0x00a670UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH1_ABILITY_100G_CR4_K2_E5                                      (0x1<<0) // 100GBase-CR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH1_ABILITY_100G_CR4_K2_E5_SHIFT                                0
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_S_K2_E5                                      (0x1<<1) // 25GBase-GR-S KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A9 in base page.
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_S_K2_E5_SHIFT                                1
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_K2_E5                                        (0x1<<2) // 25GBase-GR KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A10 in base page.
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_K2_E5_SHIFT                                  2
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH1_ABILITY_A15_A11_K2_E5                                       (0x1f<<3) // technology advertised ability Field A15-A11
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH1_ABILITY_A15_A11_K2_E5_SHIFT                                 3
+#define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH2_K2_E5                                                         0x00a674UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH2_ABILITY_A22_A16_K2_E5                                       (0x7f<<0) // technology advertised ability Field A22-A16
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH2_ABILITY_A22_A16_K2_E5_SHIFT                                 0
+#define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_K2_E5                                                           0x00a678UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_FEC_ABILITY_K2_E5                                             (0x1<<0) // base page bit F0.  It advertises FEC ability
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_FEC_ABILITY_K2_E5_SHIFT                                       0
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_FEC_REQ_K2_E5                                                 (0x1<<1) // base page bit F1.  It requests FEC to be turned on when supported at the both ends of link
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_FEC_REQ_K2_E5_SHIFT                                           1
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_RS_FEC_REQ_25G_K2_E5                                          (0x1<<2) // base page bit F2.  It requests RS-FEC for 25G-GR 25G-KR/-CR link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A23 in base page.
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_RS_FEC_REQ_25G_K2_E5_SHIFT                                    2
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_FC_FEC_REQ_25G_K2_E5                                          (0x1<<3) // base page bit F3.  It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A24 in base page.
+  #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_FC_FEC_REQ_25G_K2_E5_SHIFT                                    3
+#define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_K2_E5                                                               0x00a67cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_ABILITY_25G_KR_K2_E5                                              (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_ABILITY_25G_KR_K2_E5_SHIFT                                        0
+  #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_ABILITY_25G_CR_K2_E5                                              (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_ABILITY_25G_CR_K2_E5_SHIFT                                        1
+  #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_ABILITY_50G_KR2_K2_E5                                             (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_ABILITY_50G_KR2_K2_E5_SHIFT                                       2
+  #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_ABILITY_50G_CR2_K2_E5                                             (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_ABILITY_50G_CR2_K2_E5_SHIFT                                       3
+  #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_RS_FEC_ABILITY_K2_E5                                              (0x1<<4) // Extended advertised FEC field 0.  It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_RS_FEC_ABILITY_K2_E5_SHIFT                                        4
+  #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_FC_FEC_ABILITY_K2_E5                                              (0x1<<5) // Extended advertised FEC field 1.  It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_FC_FEC_ABILITY_K2_E5_SHIFT                                        5
+  #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_RS_FEC_REQ_K2_E5                                                  (0x1<<6) // Extended advertised FEC field 2.  It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_RS_FEC_REQ_K2_E5_SHIFT                                            6
+  #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_FC_FEC_REQ_K2_E5                                                  (0x1<<7) // Extended advertised FEC field 3.  It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_FC_FEC_REQ_K2_E5_SHIFT                                            7
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1991_K2_E5                                                    0x00a680UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1992_K2_E5                                                    0x00a684UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1992_RESERVEDFIELD2259_K2_E5                                (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1992_RESERVEDFIELD2259_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1992_RESERVEDFIELD2260_K2_E5                                (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1992_RESERVEDFIELD2260_K2_E5_SHIFT                          3
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1992_RESERVEDFIELD2261_K2_E5                                (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1992_RESERVEDFIELD2261_K2_E5_SHIFT                          4
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1992_RESERVEDFIELD2262_K2_E5                                (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1992_RESERVEDFIELD2262_K2_E5_SHIFT                          5
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1992_RESERVEDFIELD2263_K2_E5                                (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1992_RESERVEDFIELD2263_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1993_K2_E5                                                    0x00a688UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1994_K2_E5                                                    0x00a68cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1995_K2_E5                                                    0x00a690UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1996_K2_E5                                                    0x00a694UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_K2_E5                                                    0x00a698UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2264_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2264_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2265_K2_E5                                (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2265_K2_E5_SHIFT                          1
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2266_K2_E5                                (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2266_K2_E5_SHIFT                          2
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2267_K2_E5                                (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2267_K2_E5_SHIFT                          3
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2268_K2_E5                                (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2268_K2_E5_SHIFT                          4
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2269_K2_E5                                (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2269_K2_E5_SHIFT                          5
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2270_K2_E5                                (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2270_K2_E5_SHIFT                          6
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2271_K2_E5                                (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2271_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1998_K2_E5                                                    0x00a69cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1998_RESERVEDFIELD2272_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1998_RESERVEDFIELD2272_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1998_RESERVEDFIELD2273_K2_E5                                (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1998_RESERVEDFIELD2273_K2_E5_SHIFT                          1
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1998_RESERVEDFIELD2274_K2_E5                                (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1998_RESERVEDFIELD2274_K2_E5_SHIFT                          2
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1998_RESERVEDFIELD2275_K2_E5                                (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1998_RESERVEDFIELD2275_K2_E5_SHIFT                          3
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1998_RESERVEDFIELD2276_K2_E5                                (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1998_RESERVEDFIELD2276_K2_E5_SHIFT                          4
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1998_RESERVEDFIELD2277_K2_E5                                (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1998_RESERVEDFIELD2277_K2_E5_SHIFT                          5
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1998_RESERVEDFIELD2278_K2_E5                                (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1998_RESERVEDFIELD2278_K2_E5_SHIFT                          6
+#define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE0_K2_E5                                                           0x00a6a0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE0_SELECTOR_K2_E5                                                (0x1f<<0) // Link partner technology Select Field
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE0_SELECTOR_K2_E5_SHIFT                                          0
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE0_ECHOED_NONCE_2_0_K2_E5                                        (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE0_ECHOED_NONCE_2_0_K2_E5_SHIFT                                  5
+#define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_K2_E5                                                           0x00a6a4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_ECHOED_NONCE_4_3_K2_E5                                        (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_ECHOED_NONCE_4_3_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_PAUSE_K2_E5                                                   (0x1<<2) // Link partner Pause advertised ability
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_PAUSE_K2_E5_SHIFT                                             2
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_ASM_DIR_K2_E5                                                 (0x1<<3) // Link partner Pause ASM_DIR advertised ability
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_ASM_DIR_K2_E5_SHIFT                                           3
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_C2_K2_E5                                                      (0x1<<4) // Link partner C2 field always 0
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_C2_K2_E5_SHIFT                                                4
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_REMOTE_FAULT_K2_E5                                            (0x1<<5) // Link partner Remote Fault
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_REMOTE_FAULT_K2_E5_SHIFT                                      5
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_ACK_K2_E5                                                     (0x1<<6) // Link partner Acknowledge always 0
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_ACK_K2_E5_SHIFT                                               6
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_NEXT_PAGE_K2_E5                                               (0x1<<7) // Link partner Next Page
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_NEXT_PAGE_K2_E5_SHIFT                                         7
+#define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE2_K2_E5                                                           0x00a6a8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE2_TX_NONCE_K2_E5                                                (0x1f<<0) // Transmitted Nonce Field from Link partner
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE2_TX_NONCE_K2_E5_SHIFT                                          0
+#define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_K2_E5                                                      0x00a6acUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_1G_KX_K2_E5                                      (0x1<<0) // Link partner 1000Base-KX technology advertised ability
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_1G_KX_K2_E5_SHIFT                                0
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KX4_K2_E5                                    (0x1<<1) // Link partner 10GBase-KX4 technology advertised ability
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KX4_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KR_K2_E5                                     (0x1<<2) // Link partner 10GBase-KR technology advertised ability
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KR_K2_E5_SHIFT                               2
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_KR4_K2_E5                                    (0x1<<3) // Link partner 40GBase-KR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_KR4_K2_E5_SHIFT                              3
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_CR4_K2_E5                                    (0x1<<4) // Link partner 40GBase-CR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_CR4_K2_E5_SHIFT                              4
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_CR10_K2_E5                                  (0x1<<5) // Link partner 100GBase-CR10 technology advertised ability
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_CR10_K2_E5_SHIFT                            5
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KP4_K2_E5                                   (0x1<<6) // Link partner 100GBase-KP4 technology advertised ability
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KP4_K2_E5_SHIFT                             6
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KR4_K2_E5                                   (0x1<<7) // Link partner 100GBase-KR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KR4_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH1_K2_E5                                                      0x00a6b0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH1_ABILITY_100G_CR4_K2_E5                                   (0x1<<0) // Link partner 100GBase-CR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH1_ABILITY_100G_CR4_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_S_K2_E5                                   (0x1<<1) // Link partner 25GBase-GR-S KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A9 in base page.
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_S_K2_E5_SHIFT                             1
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_K2_E5                                     (0x1<<2) // Link partner 25GBase-GR KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A10 in base page.
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_K2_E5_SHIFT                               2
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH1_ABILITY_A15_A11_K2_E5                                    (0x1f<<3) // Link partner technology advertised ability Field A15-A11
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH1_ABILITY_A15_A11_K2_E5_SHIFT                              3
+#define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH2_K2_E5                                                      0x00a6b4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH2_ABILITY_A22_A16_K2_E5                                    (0x7f<<0) // Link partner technology advertised ability Field A22-A16
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH2_ABILITY_A22_A16_K2_E5_SHIFT                              0
+#define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_K2_E5                                                        0x00a6b8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_FEC_ABILITY_K2_E5                                          (0x1<<0) // Link partner base page bit F0.  It advertises FEC ability
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_FEC_ABILITY_K2_E5_SHIFT                                    0
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_FEC_REQ_K2_E5                                              (0x1<<1) // Link partner base page bit F1.  It requests FEC to be turned on when supported at the both ends of link
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_FEC_REQ_K2_E5_SHIFT                                        1
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_RS_FEC_REQ_25G_K2_E5                                       (0x1<<2) // Link partner base page bit F2.  It requests RS-FEC for 25G-GR 25G-KR/-CR link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A23 in base page.
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_RS_FEC_REQ_25G_K2_E5_SHIFT                                 2
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_FC_FEC_REQ_25G_K2_E5                                       (0x1<<3) // Link partner base page bit F3.  It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A24 in base page.
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_FC_FEC_REQ_25G_K2_E5_SHIFT                                 3
+#define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_K2_E5                                                            0x00a6bcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_ABILITY_25G_KR_K2_E5                                           (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_ABILITY_25G_KR_K2_E5_SHIFT                                     0
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_ABILITY_25G_CR_K2_E5                                           (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_ABILITY_25G_CR_K2_E5_SHIFT                                     1
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_ABILITY_50G_KR2_K2_E5                                          (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_ABILITY_50G_KR2_K2_E5_SHIFT                                    2
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_ABILITY_50G_CR2_K2_E5                                          (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_ABILITY_50G_CR2_K2_E5_SHIFT                                    3
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_RS_FEC_ABILITY_K2_E5                                           (0x1<<4) // Link partner extended advertised FEC field 0.  It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_RS_FEC_ABILITY_K2_E5_SHIFT                                     4
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_FC_FEC_ABILITY_K2_E5                                           (0x1<<5) // Link partner extended advertised FEC field 1.  It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_FC_FEC_ABILITY_K2_E5_SHIFT                                     5
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_RS_FEC_REQ_K2_E5                                               (0x1<<6) // Link partner extended advertised FEC field 2.  It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_RS_FEC_REQ_K2_E5_SHIFT                                         6
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_FC_FEC_REQ_K2_E5                                               (0x1<<7) // Link partner extended advertised FEC field 3.  It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_FC_FEC_REQ_K2_E5_SHIFT                                         7
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1999_K2_E5                                                    0x00a6c0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2000_K2_E5                                                    0x00a6c4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2000_RESERVEDFIELD2279_K2_E5                                (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2000_RESERVEDFIELD2279_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2000_RESERVEDFIELD2280_K2_E5                                (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2000_RESERVEDFIELD2280_K2_E5_SHIFT                          3
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2000_RESERVEDFIELD2281_K2_E5                                (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2000_RESERVEDFIELD2281_K2_E5_SHIFT                          4
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2000_RESERVEDFIELD2282_K2_E5                                (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2000_RESERVEDFIELD2282_K2_E5_SHIFT                          5
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2000_RESERVEDFIELD2283_K2_E5                                (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2000_RESERVEDFIELD2283_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2001_K2_E5                                                    0x00a6c8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2002_K2_E5                                                    0x00a6ccUL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2003_K2_E5                                                    0x00a6d0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2004_K2_E5                                                    0x00a6d4UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_K2_E5                                                    0x00a6d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2284_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2284_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2285_K2_E5                                (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2285_K2_E5_SHIFT                          1
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2286_K2_E5                                (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2286_K2_E5_SHIFT                          2
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2287_K2_E5                                (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2287_K2_E5_SHIFT                          3
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2288_K2_E5                                (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2288_K2_E5_SHIFT                          4
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2289_K2_E5                                (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2289_K2_E5_SHIFT                          5
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2290_K2_E5                                (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2290_K2_E5_SHIFT                          6
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2291_K2_E5                                (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2291_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2006_K2_E5                                                    0x00a6dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2006_RESERVEDFIELD2292_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2006_RESERVEDFIELD2292_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2006_RESERVEDFIELD2293_K2_E5                                (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2006_RESERVEDFIELD2293_K2_E5_SHIFT                          1
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2006_RESERVEDFIELD2294_K2_E5                                (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2006_RESERVEDFIELD2294_K2_E5_SHIFT                          2
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2006_RESERVEDFIELD2295_K2_E5                                (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2006_RESERVEDFIELD2295_K2_E5_SHIFT                          3
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2006_RESERVEDFIELD2296_K2_E5                                (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2006_RESERVEDFIELD2296_K2_E5_SHIFT                          4
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2006_RESERVEDFIELD2297_K2_E5                                (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2006_RESERVEDFIELD2297_K2_E5_SHIFT                          5
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2006_RESERVEDFIELD2298_K2_E5                                (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2006_RESERVEDFIELD2298_K2_E5_SHIFT                          6
+#define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_K2_E5                                                        0x00a6e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_1G_KX_K2_E5                                        (0x1<<0) // Resolution result for 1000Base-KX.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_1G_KX_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_10G_KX4_K2_E5                                      (0x1<<1) // Resolution result for 10GBase-KX4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_10G_KX4_K2_E5_SHIFT                                1
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_10G_KR_K2_E5                                       (0x1<<2) // Resolution result for 10GBase-KR.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_10G_KR_K2_E5_SHIFT                                 2
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_40G_KR4_K2_E5                                      (0x1<<3) // Resolution result for 40GBase-KR4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_40G_KR4_K2_E5_SHIFT                                3
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_40G_CR4_K2_E5                                      (0x1<<4) // Resolution result for 40GBase-CR4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_40G_CR4_K2_E5_SHIFT                                4
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_100G_CR10_K2_E5                                    (0x1<<5) // Resolution result for 100GBase-CR10.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_100G_CR10_K2_E5_SHIFT                              5
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_100G_KP4_K2_E5                                     (0x1<<6) // Resolution result for 100GBase-KP4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_100G_KP4_K2_E5_SHIFT                               6
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_100G_KR4_K2_E5                                     (0x1<<7) // Resolution result for 100GBase-KR4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_100G_KR4_K2_E5_SHIFT                               7
+#define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_K2_E5                                                        0x00a6e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_100G_CR4_K2_E5                                     (0x1<<0) // Resolution result for 100GBase-CR4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_100G_CR4_K2_E5_SHIFT                               0
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_S_K2_E5                                     (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_S_K2_E5_SHIFT                               1
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_K2_E5                                       (0x1<<2) // Resolution result for 25GBase-GR KR or CR.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_K2_E5_SHIFT                                 2
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_25G_KR_K2_E5                                       (0x1<<3) // Resolution result for 25GBase-KR.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_25G_KR_K2_E5_SHIFT                                 3
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_25G_CR_K2_E5                                       (0x1<<4) // Resolution result for 25GBase-CR4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_25G_CR_K2_E5_SHIFT                                 4
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_50G_KR2_K2_E5                                      (0x1<<5) // Resolution result for 50GBase-KR2.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_50G_KR2_K2_E5_SHIFT                                5
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_50G_CR2_K2_E5                                      (0x1<<6) // Resolution result for 50GBase-CR2.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_50G_CR2_K2_E5_SHIFT                                6
+#define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_FEC_K2_E5                                                          0x00a6e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_FEC_RS_K2_E5                                                     (0x1<<0) // Resolution result for Reed-Solomon FEC.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_FEC_RS_K2_E5_SHIFT                                               0
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_FEC_FC_K2_E5                                                     (0x1<<1) // Resolution result for Firecode base page FEC.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_FEC_FC_K2_E5_SHIFT                                               1
+#define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_PAUSE_K2_E5                                                        0x00a6ecUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_PAUSE_RX_K2_E5                                                   (0x1<<0) // Resolution result for RX PAUSE enable.    It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_PAUSE_RX_K2_E5_SHIFT                                             0
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_PAUSE_TX_K2_E5                                                   (0x1<<1) // Resolution result for TX PAUSE enable.    It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_PAUSE_TX_K2_E5_SHIFT                                             1
+#define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_EEE_K2_E5                                                          0x00a6f0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_EEE_F896_K2_E5                                                   (0x1<<0) // Resolution result for EEE.  It is 1 if both the local device and the link partner advertise the EEE capability for the resolved PHY type.  It is 0 otherwise.  It is valid when status0.an_link_good is 1. Note that it indicates EEE deep sleep capability.
+  #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_EEE_F896_K2_E5_SHIFT                                             0
+#define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_K2_E5                                                            0x00a6f8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_1G_KX_K2_E5                                            (0x1<<0) // link_status for 1000Base-KX
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_1G_KX_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_10G_KX4_K2_E5                                          (0x1<<1) // link_status for 10GBase-KX4
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_10G_KX4_K2_E5_SHIFT                                    1
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_10G_KR_K2_E5                                           (0x1<<2) // link_status for 10GBase-KR
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_10G_KR_K2_E5_SHIFT                                     2
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_40G_KR4_K2_E5                                          (0x1<<3) // link_status for 40GBase-KR4
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_40G_KR4_K2_E5_SHIFT                                    3
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_40G_CR4_K2_E5                                          (0x1<<4) // link_status for 40GBase-CR4
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_40G_CR4_K2_E5_SHIFT                                    4
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_100G_CR10_K2_E5                                        (0x1<<5) // link_status for 100GBase-CR10
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_100G_CR10_K2_E5_SHIFT                                  5
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_100G_KP4_K2_E5                                         (0x1<<6) // link_status for 100GBase-KP4
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_100G_KP4_K2_E5_SHIFT                                   6
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_100G_KR4_K2_E5                                         (0x1<<7) // link_status for 100GBase-KR4
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_100G_KR4_K2_E5_SHIFT                                   7
+#define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_K2_E5                                                            0x00a6fcUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_100G_CR4_K2_E5                                         (0x1<<0) // link_status for 100GBase-CR4
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_100G_CR4_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_25G_GR_K2_E5                                           (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_25G_GR_K2_E5_SHIFT                                     1
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_25G_KR_K2_E5                                           (0x1<<3) // link_status for 25GBase-KR
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_25G_KR_K2_E5_SHIFT                                     3
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_25G_CR_K2_E5                                           (0x1<<4) // link_status for 25GBase-CR4
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_25G_CR_K2_E5_SHIFT                                     4
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_50G_KR2_K2_E5                                          (0x1<<5) // link_status for 50GBase-KR2
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_50G_KR2_K2_E5_SHIFT                                    5
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_50G_CR2_K2_E5                                          (0x1<<6) // link_status for 50GBase-CR2
+  #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_50G_CR2_K2_E5_SHIFT                                    6
+#define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2007_K2_E5                                                     0x00a704UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2007_RESERVEDFIELD2299_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2007_RESERVEDFIELD2299_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2007_RESERVEDFIELD2300_K2_E5                                 (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2007_RESERVEDFIELD2300_K2_E5_SHIFT                           2
+#define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2008_K2_E5                                                     0x00a708UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2008_RESERVEDFIELD2301_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2008_RESERVEDFIELD2301_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2009_K2_E5                                                     0x00a70cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2009_RESERVEDFIELD2302_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2009_RESERVEDFIELD2302_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2010_K2_E5                                                     0x00a714UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2010_RESERVEDFIELD2303_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2010_RESERVEDFIELD2303_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2010_RESERVEDFIELD2304_K2_E5                                 (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2010_RESERVEDFIELD2304_K2_E5_SHIFT                           1
+  #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2010_RESERVEDFIELD2305_K2_E5                                 (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2010_RESERVEDFIELD2305_K2_E5_SHIFT                           3
+  #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2010_RESERVEDFIELD2306_K2_E5                                 (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2010_RESERVEDFIELD2306_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2011_K2_E5                                                     0x00a718UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2011_RESERVEDFIELD2307_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2011_RESERVEDFIELD2307_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2012_K2_E5                                                     0x00a71cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2013_K2_E5                                                     0x00a720UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2014_K2_E5                                              0x00a800UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2014_RESERVEDFIELD2310_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2014_RESERVEDFIELD2310_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2014_RESERVEDFIELD2311_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2014_RESERVEDFIELD2311_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2015_K2_E5                                              0x00a808UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2016_K2_E5                                              0x00a80cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2016_RESERVEDFIELD2313_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2016_RESERVEDFIELD2313_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2016_RESERVEDFIELD2314_K2_E5                          (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2016_RESERVEDFIELD2314_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2017_K2_E5                                              0x00a814UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2017_RESERVEDFIELD2315_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2017_RESERVEDFIELD2315_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2017_RESERVEDFIELD2316_K2_E5                          (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2017_RESERVEDFIELD2316_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2017_RESERVEDFIELD2317_K2_E5                          (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2017_RESERVEDFIELD2317_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2018_K2_E5                                              0x00a81cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2018_RESERVEDFIELD2318_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2018_RESERVEDFIELD2318_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2019_K2_E5                                              0x00a824UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2019_RESERVEDFIELD2319_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2019_RESERVEDFIELD2319_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2020_K2_E5                                              0x00a828UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2020_RESERVEDFIELD2320_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2020_RESERVEDFIELD2320_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2020_RESERVEDFIELD2321_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2020_RESERVEDFIELD2321_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2021_K2_E5                                              0x00a82cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2021_RESERVEDFIELD2322_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2021_RESERVEDFIELD2322_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2021_RESERVEDFIELD2323_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2021_RESERVEDFIELD2323_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2022_K2_E5                                              0x00a830UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2022_RESERVEDFIELD2324_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2022_RESERVEDFIELD2324_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2022_RESERVEDFIELD2325_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2022_RESERVEDFIELD2325_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2022_RESERVEDFIELD2326_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2022_RESERVEDFIELD2326_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2022_RESERVEDFIELD2327_K2_E5                          (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2022_RESERVEDFIELD2327_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2023_K2_E5                                              0x00a838UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2023_RESERVEDFIELD2328_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2023_RESERVEDFIELD2328_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2023_RESERVEDFIELD2329_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2023_RESERVEDFIELD2329_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2024_K2_E5                                              0x00a83cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2024_RESERVEDFIELD2330_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2024_RESERVEDFIELD2330_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2024_RESERVEDFIELD2331_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2024_RESERVEDFIELD2331_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2025_K2_E5                                              0x00a840UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2025_RESERVEDFIELD2332_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2025_RESERVEDFIELD2332_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2025_RESERVEDFIELD2333_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2025_RESERVEDFIELD2333_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2026_K2_E5                                              0x00a844UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2026_RESERVEDFIELD2334_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2026_RESERVEDFIELD2334_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2026_RESERVEDFIELD2335_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2026_RESERVEDFIELD2335_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2027_K2_E5                                              0x00a880UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2027_RESERVEDFIELD2336_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2027_RESERVEDFIELD2336_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2027_RESERVEDFIELD2337_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2027_RESERVEDFIELD2337_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2028_K2_E5                                              0x00a884UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2028_RESERVEDFIELD2338_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2028_RESERVEDFIELD2338_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2028_RESERVEDFIELD2339_K2_E5                          (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2028_RESERVEDFIELD2339_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2029_K2_E5                                              0x00a888UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2030_K2_E5                                              0x00a88cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2031_K2_E5                                              0x00a890UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2031_RESERVEDFIELD2342_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2031_RESERVEDFIELD2342_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2031_RESERVEDFIELD2343_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2031_RESERVEDFIELD2343_K2_E5_SHIFT                    3
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2031_RESERVEDFIELD2344_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2031_RESERVEDFIELD2344_K2_E5_SHIFT                    6
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2031_RESERVEDFIELD2345_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2031_RESERVEDFIELD2345_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2032_K2_E5                                              0x00a894UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2032_RESERVEDFIELD2346_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2032_RESERVEDFIELD2346_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2032_RESERVEDFIELD2347_K2_E5                          (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2032_RESERVEDFIELD2347_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2033_K2_E5                                              0x00a898UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2034_K2_E5                                              0x00a89cUL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2035_K2_E5                                              0x00a8a0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2035_RESERVEDFIELD2350_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2035_RESERVEDFIELD2350_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2035_RESERVEDFIELD2351_K2_E5                          (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2035_RESERVEDFIELD2351_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2036_K2_E5                                              0x00a8a4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2037_K2_E5                                              0x00a8a8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2038_K2_E5                                              0x00a8acUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2038_RESERVEDFIELD2354_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2038_RESERVEDFIELD2354_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2039_K2_E5                                              0x00a8b0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2040_K2_E5                                              0x00a8b8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_AGCLOS_CTRL0_K2_E5                                                      0x00a8c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_AGCLOS_CTRL0_AGCLOS_START_K2_E5                                       (0xf<<0) // AGC LOS Threshold Start Value
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_AGCLOS_CTRL0_AGCLOS_START_K2_E5_SHIFT                                 0
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2041_K2_E5                                              0x00a8c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2041_RESERVEDFIELD2357_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2041_RESERVEDFIELD2357_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2042_K2_E5                                              0x00a8c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2042_RESERVEDFIELD2358_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2042_RESERVEDFIELD2358_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2043_K2_E5                                              0x00a8ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2043_RESERVEDFIELD2359_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2043_RESERVEDFIELD2359_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2043_RESERVEDFIELD2360_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2043_RESERVEDFIELD2360_K2_E5_SHIFT                    6
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2043_RESERVEDFIELD2361_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2043_RESERVEDFIELD2361_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2044_K2_E5                                              0x00a8d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2044_RESERVEDFIELD2362_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2044_RESERVEDFIELD2362_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2044_RESERVEDFIELD2363_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2044_RESERVEDFIELD2363_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2044_RESERVEDFIELD2364_K2_E5                          (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2044_RESERVEDFIELD2364_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2045_K2_E5                                              0x00a8d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2045_RESERVEDFIELD2365_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2045_RESERVEDFIELD2365_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2045_RESERVEDFIELD2366_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2045_RESERVEDFIELD2366_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2045_RESERVEDFIELD2367_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2045_RESERVEDFIELD2367_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2046_K2_E5                                              0x00a8d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2046_RESERVEDFIELD2368_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2046_RESERVEDFIELD2368_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2047_K2_E5                                              0x00a8dcUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2048_K2_E5                                              0x00a8e0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2049_K2_E5                                              0x00a8e4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2050_K2_E5                                              0x00a8e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2050_RESERVEDFIELD2372_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2050_RESERVEDFIELD2372_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2051_K2_E5                                              0x00a8f4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2051_RESERVEDFIELD2373_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2051_RESERVEDFIELD2373_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2051_RESERVEDFIELD2374_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2051_RESERVEDFIELD2374_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_PLE_ATT_CTRL1_K2_E5                                                     0x00a8f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_PLE_ATT_CTRL1_PLE_ATT_START_K2_E5                                     (0x7<<0) // PLE LFG Start Value
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_PLE_ATT_CTRL1_PLE_ATT_START_K2_E5_SHIFT                               0
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_K2_E5                                                  0x00a900UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_EQ_HFG_SQL_START_K2_E5                               (0x1f<<0) // CTLE HFG Start Value
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_EQ_HFG_SQL_START_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2052_K2_E5                                              0x00a904UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2052_RESERVEDFIELD2375_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2052_RESERVEDFIELD2375_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2053_K2_E5                                              0x00a908UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2053_RESERVEDFIELD2376_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2053_RESERVEDFIELD2376_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2054_K2_E5                                              0x00a90cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2054_RESERVEDFIELD2377_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2054_RESERVEDFIELD2377_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2054_RESERVEDFIELD2378_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2054_RESERVEDFIELD2378_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2055_K2_E5                                              0x00a910UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2055_RESERVEDFIELD2379_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2055_RESERVEDFIELD2379_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2055_RESERVEDFIELD2380_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2055_RESERVEDFIELD2380_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2055_RESERVEDFIELD2381_K2_E5                          (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2055_RESERVEDFIELD2381_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2056_K2_E5                                              0x00a914UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2056_RESERVEDFIELD2382_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2056_RESERVEDFIELD2382_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2056_RESERVEDFIELD2383_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2056_RESERVEDFIELD2383_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2056_RESERVEDFIELD2384_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2056_RESERVEDFIELD2384_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2057_K2_E5                                              0x00a918UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2057_RESERVEDFIELD2385_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2057_RESERVEDFIELD2385_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2058_K2_E5                                              0x00a940UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2058_RESERVEDFIELD2386_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2058_RESERVEDFIELD2386_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2058_RESERVEDFIELD2387_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2058_RESERVEDFIELD2387_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2058_RESERVEDFIELD2388_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2058_RESERVEDFIELD2388_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2058_RESERVEDFIELD2389_K2_E5                          (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2058_RESERVEDFIELD2389_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2059_K2_E5                                              0x00a944UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2059_RESERVEDFIELD2390_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2059_RESERVEDFIELD2390_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2059_RESERVEDFIELD2391_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2059_RESERVEDFIELD2391_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2060_K2_E5                                              0x00a948UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2060_RESERVEDFIELD2392_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2060_RESERVEDFIELD2392_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2060_RESERVEDFIELD2393_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2060_RESERVEDFIELD2393_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2061_K2_E5                                              0x00a94cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2061_RESERVEDFIELD2394_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2061_RESERVEDFIELD2394_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2061_RESERVEDFIELD2395_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2061_RESERVEDFIELD2395_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2062_K2_E5                                              0x00a950UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2062_RESERVEDFIELD2396_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2062_RESERVEDFIELD2396_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2062_RESERVEDFIELD2397_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2062_RESERVEDFIELD2397_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2063_K2_E5                                              0x00a954UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2063_RESERVEDFIELD2398_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2063_RESERVEDFIELD2398_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2063_RESERVEDFIELD2399_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2063_RESERVEDFIELD2399_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2064_K2_E5                                              0x00a958UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2064_RESERVEDFIELD2400_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2064_RESERVEDFIELD2400_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2064_RESERVEDFIELD2401_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2064_RESERVEDFIELD2401_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2065_K2_E5                                              0x00a95cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2065_RESERVEDFIELD2402_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2065_RESERVEDFIELD2402_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2065_RESERVEDFIELD2403_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2065_RESERVEDFIELD2403_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2066_K2_E5                                              0x00a960UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2066_RESERVEDFIELD2404_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2066_RESERVEDFIELD2404_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2066_RESERVEDFIELD2405_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2066_RESERVEDFIELD2405_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2067_K2_E5                                              0x00a964UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2067_RESERVEDFIELD2406_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2067_RESERVEDFIELD2406_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2067_RESERVEDFIELD2407_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2067_RESERVEDFIELD2407_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2068_K2_E5                                              0x00a968UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2068_RESERVEDFIELD2408_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2068_RESERVEDFIELD2408_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2068_RESERVEDFIELD2409_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2068_RESERVEDFIELD2409_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2069_K2_E5                                              0x00a96cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2069_RESERVEDFIELD2410_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2069_RESERVEDFIELD2410_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2069_RESERVEDFIELD2411_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2069_RESERVEDFIELD2411_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2070_K2_E5                                              0x00a970UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2070_RESERVEDFIELD2412_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2070_RESERVEDFIELD2412_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2070_RESERVEDFIELD2413_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2070_RESERVEDFIELD2413_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2071_K2_E5                                              0x00a974UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2071_RESERVEDFIELD2414_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2071_RESERVEDFIELD2414_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2071_RESERVEDFIELD2415_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2071_RESERVEDFIELD2415_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2072_K2_E5                                              0x00a978UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2072_RESERVEDFIELD2416_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2072_RESERVEDFIELD2416_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2072_RESERVEDFIELD2417_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2072_RESERVEDFIELD2417_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2073_K2_E5                                              0x00a97cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2073_RESERVEDFIELD2418_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2073_RESERVEDFIELD2418_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2073_RESERVEDFIELD2419_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2073_RESERVEDFIELD2419_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2074_K2_E5                                              0x00a980UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2074_RESERVEDFIELD2420_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2074_RESERVEDFIELD2420_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2074_RESERVEDFIELD2421_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2074_RESERVEDFIELD2421_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2075_K2_E5                                              0x00a984UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2075_RESERVEDFIELD2422_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2075_RESERVEDFIELD2422_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2075_RESERVEDFIELD2423_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2075_RESERVEDFIELD2423_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2076_K2_E5                                              0x00a988UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2076_RESERVEDFIELD2424_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2076_RESERVEDFIELD2424_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2076_RESERVEDFIELD2425_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2076_RESERVEDFIELD2425_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2077_K2_E5                                              0x00a98cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2077_RESERVEDFIELD2426_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2077_RESERVEDFIELD2426_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2077_RESERVEDFIELD2427_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2077_RESERVEDFIELD2427_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2078_K2_E5                                              0x00a990UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2078_RESERVEDFIELD2428_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2078_RESERVEDFIELD2428_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2078_RESERVEDFIELD2429_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2078_RESERVEDFIELD2429_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2079_K2_E5                                              0x00a994UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2079_RESERVEDFIELD2430_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2079_RESERVEDFIELD2430_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2079_RESERVEDFIELD2431_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2079_RESERVEDFIELD2431_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2080_K2_E5                                              0x00a998UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2080_RESERVEDFIELD2432_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2080_RESERVEDFIELD2432_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2080_RESERVEDFIELD2433_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2080_RESERVEDFIELD2433_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2081_K2_E5                                              0x00a99cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2081_RESERVEDFIELD2434_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2081_RESERVEDFIELD2434_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2081_RESERVEDFIELD2435_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2081_RESERVEDFIELD2435_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2082_K2_E5                                              0x00a9a0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2082_RESERVEDFIELD2436_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2082_RESERVEDFIELD2436_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2082_RESERVEDFIELD2437_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2082_RESERVEDFIELD2437_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_GN_APG_CTRL0_K2_E5                                                      0x00a9c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_GN_APG_CTRL0_GN_APG_START_K2_E5                                       (0x3<<0) // GN APG Start Value
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_GN_APG_CTRL0_GN_APG_START_K2_E5_SHIFT                                 0
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2083_K2_E5                                              0x00a9c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2083_RESERVEDFIELD2438_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2083_RESERVEDFIELD2438_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2083_RESERVEDFIELD2439_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2083_RESERVEDFIELD2439_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2084_K2_E5                                              0x00a9c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2084_RESERVEDFIELD2440_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2084_RESERVEDFIELD2440_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2084_RESERVEDFIELD2441_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2084_RESERVEDFIELD2441_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2085_K2_E5                                              0x00a9ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2085_RESERVEDFIELD2442_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2085_RESERVEDFIELD2442_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2085_RESERVEDFIELD2443_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2085_RESERVEDFIELD2443_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2085_RESERVEDFIELD2444_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2085_RESERVEDFIELD2444_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2086_K2_E5                                              0x00a9d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2086_RESERVEDFIELD2445_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2086_RESERVEDFIELD2445_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2086_RESERVEDFIELD2446_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2086_RESERVEDFIELD2446_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2086_RESERVEDFIELD2447_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2086_RESERVEDFIELD2447_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2087_K2_E5                                              0x00a9d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2087_RESERVEDFIELD2448_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2087_RESERVEDFIELD2448_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2088_K2_E5                                              0x00a9d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2088_RESERVEDFIELD2449_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2088_RESERVEDFIELD2449_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2088_RESERVEDFIELD2450_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2088_RESERVEDFIELD2450_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_LFG_CTRL0_K2_E5                                                      0x00aa00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_LFG_CTRL0_EQ_LFG_START_K2_E5                                       (0x1f<<0) // EQ LFG Start Value
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_LFG_CTRL0_EQ_LFG_START_K2_E5_SHIFT                                 0
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_LFG_CTRL1_K2_E5                                                      0x00aa04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_LFG_CTRL1_EQ_LFG_VALUE_MAX_K2_E5                                   (0x1f<<0) // EQ LFG Maximum Value, inclusive
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_LFG_CTRL1_EQ_LFG_VALUE_MAX_K2_E5_SHIFT                             0
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_LFG_CTRL2_K2_E5                                                      0x00aa08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_LFG_CTRL2_EQ_LFG_VALUE_MIN_K2_E5                                   (0x1f<<0) // EQ LFG Minimum Value, inclusive
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_LFG_CTRL2_EQ_LFG_VALUE_MIN_K2_E5_SHIFT                             0
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2089_K2_E5                                              0x00aa0cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2089_RESERVEDFIELD2451_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2089_RESERVEDFIELD2451_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2089_RESERVEDFIELD2452_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2089_RESERVEDFIELD2452_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2090_K2_E5                                              0x00aa10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2090_RESERVEDFIELD2453_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2090_RESERVEDFIELD2453_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2090_RESERVEDFIELD2454_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2090_RESERVEDFIELD2454_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2090_RESERVEDFIELD2455_K2_E5                          (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2090_RESERVEDFIELD2455_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2091_K2_E5                                              0x00aa14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2091_RESERVEDFIELD2456_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2091_RESERVEDFIELD2456_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2091_RESERVEDFIELD2457_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2091_RESERVEDFIELD2457_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2091_RESERVEDFIELD2458_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2091_RESERVEDFIELD2458_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2092_K2_E5                                              0x00aa18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2092_RESERVEDFIELD2459_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2092_RESERVEDFIELD2459_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2093_K2_E5                                              0x00aa1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2093_RESERVEDFIELD2460_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2093_RESERVEDFIELD2460_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2094_K2_E5                                              0x00aa20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2094_RESERVEDFIELD2461_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2094_RESERVEDFIELD2461_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2095_K2_E5                                              0x00aa40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2095_RESERVEDFIELD2462_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2095_RESERVEDFIELD2462_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2096_K2_E5                                              0x00aa44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2096_RESERVEDFIELD2463_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2096_RESERVEDFIELD2463_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2097_K2_E5                                              0x00aa48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2097_RESERVEDFIELD2464_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2097_RESERVEDFIELD2464_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2098_K2_E5                                              0x00aa4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2098_RESERVEDFIELD2465_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2098_RESERVEDFIELD2465_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2098_RESERVEDFIELD2466_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2098_RESERVEDFIELD2466_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2099_K2_E5                                              0x00aa50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2099_RESERVEDFIELD2467_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2099_RESERVEDFIELD2467_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2099_RESERVEDFIELD2468_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2099_RESERVEDFIELD2468_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2099_RESERVEDFIELD2469_K2_E5                          (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2099_RESERVEDFIELD2469_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2100_K2_E5                                              0x00aa54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2100_RESERVEDFIELD2470_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2100_RESERVEDFIELD2470_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2100_RESERVEDFIELD2471_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2100_RESERVEDFIELD2471_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2100_RESERVEDFIELD2472_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2100_RESERVEDFIELD2472_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2101_K2_E5                                              0x00aa58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2101_RESERVEDFIELD2473_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2101_RESERVEDFIELD2473_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2102_K2_E5                                              0x00aa60UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2102_RESERVEDFIELD2474_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2102_RESERVEDFIELD2474_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2102_RESERVEDFIELD2475_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2102_RESERVEDFIELD2475_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_MB_CTRL1_K2_E5                                                       0x00aa64UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_K2_E5                                        (0xf<<0) // EQ MBF Start Value
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_K2_E5                                        (0xf<<4) // EQ MBG Start Value
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_K2_E5_SHIFT                                  4
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2103_K2_E5                                              0x00aa68UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2104_K2_E5                                              0x00aa6cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2105_K2_E5                                              0x00aa70UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2105_RESERVEDFIELD2478_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2105_RESERVEDFIELD2478_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2105_RESERVEDFIELD2479_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2105_RESERVEDFIELD2479_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2105_RESERVEDFIELD2480_K2_E5                          (0xf<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2105_RESERVEDFIELD2480_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2106_K2_E5                                              0x00aa74UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2106_RESERVEDFIELD2481_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2106_RESERVEDFIELD2481_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2106_RESERVEDFIELD2482_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2106_RESERVEDFIELD2482_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2106_RESERVEDFIELD2483_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2106_RESERVEDFIELD2483_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2107_K2_E5                                              0x00aa80UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2108_K2_E5                                              0x00aa84UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2109_K2_E5                                              0x00aa88UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2109_RESERVEDFIELD2486_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2109_RESERVEDFIELD2486_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2109_RESERVEDFIELD2487_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2109_RESERVEDFIELD2487_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2109_RESERVEDFIELD2488_K2_E5                          (0xf<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2109_RESERVEDFIELD2488_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2110_K2_E5                                              0x00aa8cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2110_RESERVEDFIELD2489_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2110_RESERVEDFIELD2489_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2110_RESERVEDFIELD2490_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2110_RESERVEDFIELD2490_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2110_RESERVEDFIELD2491_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2110_RESERVEDFIELD2491_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2111_K2_E5                                              0x00aa98UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2112_K2_E5                                              0x00aa9cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2113_K2_E5                                              0x00aaa0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2114_K2_E5                                              0x00aaa4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2115_K2_E5                                              0x00aaacUL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2116_K2_E5                                              0x00aab0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2116_RESERVEDFIELD2497_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2116_RESERVEDFIELD2497_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2116_RESERVEDFIELD2498_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2116_RESERVEDFIELD2498_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2117_K2_E5                                              0x00aab8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2117_RESERVEDFIELD2499_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2117_RESERVEDFIELD2499_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2117_RESERVEDFIELD2500_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2117_RESERVEDFIELD2500_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2118_K2_E5                                              0x00aabcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2118_RESERVEDFIELD2501_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2118_RESERVEDFIELD2501_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2119_K2_E5                                              0x00aae0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2120_K2_E5                                              0x00aae4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2121_K2_E5                                               0x00ac00UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2122_K2_E5                                               0x00ac04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2122_RESERVEDFIELD2503_K2_E5                           (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2122_RESERVEDFIELD2503_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2123_K2_E5                                               0x00ac08UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2124_K2_E5                                               0x00ac0cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2124_RESERVEDFIELD2505_K2_E5                           (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2124_RESERVEDFIELD2505_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2125_K2_E5                                               0x00ac10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2125_RESERVEDFIELD2506_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2125_RESERVEDFIELD2506_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2126_K2_E5                                               0x00ac14UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2127_K2_E5                                               0x00ac20UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2128_K2_E5                                               0x00ac24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2128_RESERVEDFIELD2509_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2128_RESERVEDFIELD2509_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2129_K2_E5                                               0x00ac30UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2130_K2_E5                                               0x00ac34UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2130_RESERVEDFIELD2511_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2130_RESERVEDFIELD2511_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2131_K2_E5                                               0x00ac40UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2132_K2_E5                                               0x00ac44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2132_RESERVEDFIELD2513_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2132_RESERVEDFIELD2513_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2133_K2_E5                                               0x00ac4cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2134_K2_E5                                               0x00ac50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2134_RESERVEDFIELD2515_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2134_RESERVEDFIELD2515_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2135_K2_E5                                               0x00ac58UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2136_K2_E5                                               0x00ac5cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2136_RESERVEDFIELD2517_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2136_RESERVEDFIELD2517_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2137_K2_E5                                               0x00ac80UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LEQ_RXCLK_RESERVEDREGISTER2138_K2_E5                                               0x00ac84UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DRV_REFCLK_AFE_PD_CTRL0_K2_E5                                                      0x00ae00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_AFE_PD_CTRL0_PD_TXDRV_K2_E5                                           (0xf<<0) // power down TX driver
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_AFE_PD_CTRL0_PD_TXDRV_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2139_K2_E5                                              0x00ae04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2139_RESERVEDFIELD2518_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2139_RESERVEDFIELD2518_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DRV_REFCLK_AFE_CTRL0_K2_E5                                                         0x00ae08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_AFE_CTRL0_TXDRV_LP_IDLE_K2_E5                                         (0x3<<0) // When HIGH, TX driver goes into a low power IDLE model. In this mode, the output termination is not guaranteed to be 50 Ohm closer to 200 Ohm
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_AFE_CTRL0_TXDRV_LP_IDLE_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2140_K2_E5                                              0x00ae0cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2141_K2_E5                                              0x00ae10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2141_RESERVEDFIELD2520_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2141_RESERVEDFIELD2520_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2141_RESERVEDFIELD2521_K2_E5                          (0x1f<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2141_RESERVEDFIELD2521_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2142_K2_E5                                              0x00ae14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2142_RESERVEDFIELD2522_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2142_RESERVEDFIELD2522_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2143_K2_E5                                              0x00ae18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2143_RESERVEDFIELD2523_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2143_RESERVEDFIELD2523_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2143_RESERVEDFIELD2524_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2143_RESERVEDFIELD2524_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2143_RESERVEDFIELD2525_K2_E5                          (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2143_RESERVEDFIELD2525_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2143_RESERVEDFIELD2526_K2_E5                          (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2143_RESERVEDFIELD2526_K2_E5_SHIFT                    5
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2143_RESERVEDFIELD2527_K2_E5                          (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2143_RESERVEDFIELD2527_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2144_K2_E5                                              0x00ae20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2144_RESERVEDFIELD2528_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2144_RESERVEDFIELD2528_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2144_RESERVEDFIELD2529_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2144_RESERVEDFIELD2529_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2144_RESERVEDFIELD2530_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2144_RESERVEDFIELD2530_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2144_RESERVEDFIELD2531_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2144_RESERVEDFIELD2531_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2145_K2_E5                                              0x00ae24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2145_RESERVEDFIELD2532_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2145_RESERVEDFIELD2532_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2145_RESERVEDFIELD2533_K2_E5                          (0x1f<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2145_RESERVEDFIELD2533_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2146_K2_E5                                              0x00ae28UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2146_RESERVEDFIELD2534_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2146_RESERVEDFIELD2534_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2146_RESERVEDFIELD2535_K2_E5                          (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2146_RESERVEDFIELD2535_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2147_K2_E5                                              0x00ae2cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2147_RESERVEDFIELD2536_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2147_RESERVEDFIELD2536_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2147_RESERVEDFIELD2537_K2_E5                          (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2147_RESERVEDFIELD2537_K2_E5_SHIFT                    5
+#define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2148_K2_E5                                              0x00ae30UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2148_RESERVEDFIELD2538_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2148_RESERVEDFIELD2538_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2148_RESERVEDFIELD2539_K2_E5                          (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2148_RESERVEDFIELD2539_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2149_K2_E5                                              0x00ae34UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2149_RESERVEDFIELD2540_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2149_RESERVEDFIELD2540_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2149_RESERVEDFIELD2541_K2_E5                          (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2149_RESERVEDFIELD2541_K2_E5_SHIFT                    5
+#define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL0_K2_E5                                                        0x00ae40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL0_REQ_K2_E5                                                  (0x1<<0) // Set to 1 to apply the coefficient settings, and hold until ack is 1.  Set to 0 once ack is 1.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL0_REQ_K2_E5_SHIFT                                            0
+#define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_STATUS0_K2_E5                                                      0x00ae44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_STATUS0_ACK_K2_E5                                                (0x1<<0) // Set to 1 by firmware when updates are complete. Cleared when req = 0
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_STATUS0_ACK_K2_E5_SHIFT                                          0
+#define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL1_K2_E5                                                        0x00ae48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL1_TXEQ_C1_K2_E5                                              (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL1_TXEQ_C1_K2_E5_SHIFT                                        0
+#define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2150_K2_E5                                              0x00ae4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2150_RESERVEDFIELD2542_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2150_RESERVEDFIELD2542_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL3_K2_E5                                                        0x00ae50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL3_TXEQ_CM1_K2_E5                                             (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL3_TXEQ_CM1_K2_E5_SHIFT                                       0
+#define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2151_K2_E5                                              0x00ae54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2151_RESERVEDFIELD2543_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2151_RESERVEDFIELD2543_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2151_RESERVEDFIELD2544_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2151_RESERVEDFIELD2544_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL5_K2_E5                                                        0x00ae58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL5_DRV_SWING_K2_E5                                            (0xf<<0) // Thermometer coded control to adjust the delay between data and clock for the final 2to1 mux. Setting 00000 min delay of clock path and 11111 max delay of clock path.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL5_DRV_SWING_K2_E5_SHIFT                                      0
+#define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2152_K2_E5                                              0x00ae5cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2152_RESERVEDFIELD2545_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2152_RESERVEDFIELD2545_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2152_RESERVEDFIELD2546_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2152_RESERVEDFIELD2546_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2152_RESERVEDFIELD2547_K2_E5                          (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2152_RESERVEDFIELD2547_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2152_RESERVEDFIELD2548_K2_E5                          (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2152_RESERVEDFIELD2548_K2_E5_SHIFT                    5
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2152_RESERVEDFIELD2549_K2_E5                          (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2152_RESERVEDFIELD2549_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2153_K2_E5                                              0x00ae60UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2153_RESERVEDFIELD2550_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2153_RESERVEDFIELD2550_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2153_RESERVEDFIELD2551_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2153_RESERVEDFIELD2551_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2153_RESERVEDFIELD2552_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2153_RESERVEDFIELD2552_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2153_RESERVEDFIELD2553_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2153_RESERVEDFIELD2553_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2154_K2_E5                                              0x00ae64UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2154_RESERVEDFIELD2554_K2_E5                          (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2154_RESERVEDFIELD2554_K2_E5_SHIFT                    3
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2154_RESERVEDFIELD2555_K2_E5                          (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2154_RESERVEDFIELD2555_K2_E5_SHIFT                    5
+#define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2155_K2_E5                                              0x00ae6cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2155_RESERVEDFIELD2556_K2_E5                          (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2155_RESERVEDFIELD2556_K2_E5_SHIFT                    3
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2155_RESERVEDFIELD2557_K2_E5                          (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2155_RESERVEDFIELD2557_K2_E5_SHIFT                    5
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2156_K2_E5                                              0x00b000UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2156_RESERVEDFIELD2558_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2156_RESERVEDFIELD2558_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2157_K2_E5                                              0x00b004UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2157_RESERVEDFIELD2559_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2157_RESERVEDFIELD2559_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2158_K2_E5                                              0x00b008UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2158_RESERVEDFIELD2560_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2158_RESERVEDFIELD2560_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2158_RESERVEDFIELD2561_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2158_RESERVEDFIELD2561_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2159_K2_E5                                              0x00b00cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2159_RESERVEDFIELD2562_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2159_RESERVEDFIELD2562_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2159_RESERVEDFIELD2563_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2159_RESERVEDFIELD2563_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2160_K2_E5                                              0x00b010UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2160_RESERVEDFIELD2564_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2160_RESERVEDFIELD2564_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2161_K2_E5                                              0x00b018UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2161_RESERVEDFIELD2565_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2161_RESERVEDFIELD2565_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2162_K2_E5                                              0x00b028UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2162_RESERVEDFIELD2566_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2162_RESERVEDFIELD2566_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2162_RESERVEDFIELD2567_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2162_RESERVEDFIELD2567_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2162_RESERVEDFIELD2568_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2162_RESERVEDFIELD2568_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2163_K2_E5                                              0x00b030UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2163_RESERVEDFIELD2569_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2163_RESERVEDFIELD2569_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2163_RESERVEDFIELD2570_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2163_RESERVEDFIELD2570_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2164_K2_E5                                              0x00b038UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2164_RESERVEDFIELD2571_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2164_RESERVEDFIELD2571_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2164_RESERVEDFIELD2572_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2164_RESERVEDFIELD2572_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2164_RESERVEDFIELD2573_K2_E5                          (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2164_RESERVEDFIELD2573_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2165_K2_E5                                              0x00b040UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2165_RESERVEDFIELD2574_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2165_RESERVEDFIELD2574_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2165_RESERVEDFIELD2575_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2165_RESERVEDFIELD2575_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2165_RESERVEDFIELD2576_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2165_RESERVEDFIELD2576_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2166_K2_E5                                              0x00b048UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2166_RESERVEDFIELD2577_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2166_RESERVEDFIELD2577_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2166_RESERVEDFIELD2578_K2_E5                          (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2166_RESERVEDFIELD2578_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2167_K2_E5                                              0x00b050UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2168_K2_E5                                              0x00b058UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2168_RESERVEDFIELD2580_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2168_RESERVEDFIELD2580_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2168_RESERVEDFIELD2581_K2_E5                          (0xf<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2168_RESERVEDFIELD2581_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2169_K2_E5                                              0x00b060UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2170_K2_E5                                              0x00b064UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2170_RESERVEDFIELD2583_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2170_RESERVEDFIELD2583_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2171_K2_E5                                              0x00b06cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2171_RESERVEDFIELD2584_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2171_RESERVEDFIELD2584_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2171_RESERVEDFIELD2585_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2171_RESERVEDFIELD2585_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_CTRL0_K2_E5                                                         0x00b080UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_CTRL0_REQ_K2_E5                                                   (0x1<<0) // Write 1 to request a command CMD execution.  It should be held at 1 until fsm_status0.ack is 1, and then it should be set back to 0.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_CTRL0_REQ_K2_E5_SHIFT                                             0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_CTRL0_CMD_K2_E5                                                   (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_CTRL0_CMD_K2_E5_SHIFT                                             1
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_CTRL0_RESERVEDFIELD2586_K2_E5                                     (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_CTRL0_RESERVEDFIELD2586_K2_E5_SHIFT                               6
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL_K2_E5                                     (0x1<<7) // Set it to 1 when changing DFE tap values
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL_K2_E5_SHIFT                               7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2172_K2_E5                                              0x00b084UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2172_RESERVEDFIELD2587_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2172_RESERVEDFIELD2587_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2172_RESERVEDFIELD2588_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2172_RESERVEDFIELD2588_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2173_K2_E5                                              0x00b088UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2174_K2_E5                                              0x00b08cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2174_RESERVEDFIELD2590_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2174_RESERVEDFIELD2590_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2175_K2_E5                                              0x00b090UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2176_K2_E5                                              0x00b094UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2176_RESERVEDFIELD2592_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2176_RESERVEDFIELD2592_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2177_K2_E5                                              0x00b098UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2178_K2_E5                                              0x00b09cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2178_RESERVEDFIELD2594_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2178_RESERVEDFIELD2594_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_STATUS0_K2_E5                                                       0x00b0a0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_STATUS0_ACK_K2_E5                                                 (0x1<<0) // Acknowledge from DFE after command execution. Will be set to 1 after a command is completed, and will clear to 0 after fsm_status0.req is cleared
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_STATUS0_ACK_K2_E5_SHIFT                                           0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD2595_K2_E5                                   (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD2595_K2_E5_SHIFT                             1
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD2596_K2_E5                                   (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD2596_K2_E5_SHIFT                             2
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD2597_K2_E5                                   (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD2597_K2_E5_SHIFT                             3
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_K2_E5                                                         0x00b0a8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN_K2_E5                                         (0x1<<0) // Enables updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN_K2_E5                                         (0x1<<1) // Enables updating Tap 1 Even 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN_K2_E5_SHIFT                                   1
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN_K2_E5                                          (0x1<<2) // Enables updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN_K2_E5_SHIFT                                    2
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN_K2_E5                                          (0x1<<3) // Enables updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN_K2_E5_SHIFT                                    3
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP2_EN_K2_E5                                               (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP2_EN_K2_E5_SHIFT                                         4
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP3_EN_K2_E5                                               (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP3_EN_K2_E5_SHIFT                                         5
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP4_EN_K2_E5                                               (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP4_EN_K2_E5_SHIFT                                         6
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP5_EN_K2_E5                                               (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP5_EN_K2_E5_SHIFT                                         7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL0_K2_E5                                               0x00b0acUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_K2_E5                                  (0x1f<<0) // Starting value for Tap 1 Even 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_K2_E5_SHIFT                            0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5                         (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5_SHIFT                   7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL1_K2_E5                                               0x00b0b0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_K2_E5                                  (0x1f<<0) // Starting value for Tap 1 Even 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_K2_E5_SHIFT                            0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5                         (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5_SHIFT                   7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL2_K2_E5                                               0x00b0b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_K2_E5                                   (0x1f<<0) // Starting value for Tap 1 Odd 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5                          (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL3_K2_E5                                               0x00b0b8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_K2_E5                                   (0x1f<<0) // Starting value for Tap 1 Odd 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5                          (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL4_K2_E5                                               0x00b0bcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_K2_E5                                        (0xf<<0) // Starting value for Tap 2 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY_K2_E5                               (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY_K2_E5_SHIFT                         7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL5_K2_E5                                               0x00b0c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_K2_E5                                        (0x7<<0) // Starting value for Tap 3 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY_K2_E5                               (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY_K2_E5_SHIFT                         7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL6_K2_E5                                               0x00b0c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_K2_E5                                        (0x7<<0) // Starting value for Tap 4 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY_K2_E5                               (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY_K2_E5_SHIFT                         7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL7_K2_E5                                               0x00b0c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_K2_E5                                        (0x7<<0) // Starting value for Tap 5 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY_K2_E5                               (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY_K2_E5_SHIFT                         7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_K2_E5                                                0x00b0ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_K2_E5                                   (0x1f<<0) // Loading value for Tap 1 Even 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5                          (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_K2_E5                                                0x00b0d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_K2_E5                                   (0x1f<<0) // Loading value for Tap 1 Even 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5                          (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_K2_E5                                                0x00b0d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_K2_E5                                    (0x1f<<0) // Loading value for Tap 1 Odd 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5                           (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5_SHIFT                     7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_K2_E5                                                0x00b0d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_K2_E5                                    (0x1f<<0) // Loading value for Tap 1 Odd 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5                           (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5_SHIFT                     7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_K2_E5                                                0x00b0dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_K2_E5                                         (0xf<<0) // Loading value for Tap 2 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_K2_E5                                (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_K2_E5                                                0x00b0e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_K2_E5                                         (0x7<<0) // Loading value for Tap 3 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_K2_E5                                (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_K2_E5                                                0x00b0e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_K2_E5                                         (0x7<<0) // Loading value for Tap 4 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_K2_E5                                (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_K2_E5                                                0x00b0e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_K2_E5                                         (0x7<<0) // Loading value for Tap 5 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_K2_E5                                (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS0_K2_E5                                                   0x00b0ecUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_K2_E5                                      (0x1f<<0) // binary value for Tap 1 Even 0 Path for Tap Adaptations
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_K2_E5_SHIFT                                0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_K2_E5                             (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_K2_E5_SHIFT                       7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS1_K2_E5                                                   0x00b0f0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_K2_E5                                      (0x1f<<0) // binary  value for Tap 1 Even 1 Path for Tap Adaptations
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_K2_E5_SHIFT                                0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_K2_E5                             (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_K2_E5_SHIFT                       7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS2_K2_E5                                                   0x00b0f4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_K2_E5                                       (0x1f<<0) // binary  value for Tap 1 Odd 0 Path for Tap Adaptations
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_K2_E5                              (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_K2_E5_SHIFT                        7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS3_K2_E5                                                   0x00b0f8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_K2_E5                                       (0x1f<<0) // binary  value for Tap 1 Odd 1 Path for Tap Adaptations
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_K2_E5                              (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_K2_E5_SHIFT                        7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS4_K2_E5                                                   0x00b0fcUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_K2_E5                                            (0xf<<0) // binary  value for Tap 2 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY_K2_E5                                   (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS5_K2_E5                                                   0x00b100UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_K2_E5                                            (0x7<<0) // binary  value for Tap 3 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY_K2_E5                                   (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS6_K2_E5                                                   0x00b104UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_K2_E5                                            (0x7<<0) // binary  value for Tap 4 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY_K2_E5                                   (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS7_K2_E5                                                   0x00b108UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_K2_E5                                            (0x7<<0) // binary  value for Tap 5 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY_K2_E5                                   (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_K2_E5                                              0x00b140UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2598_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2598_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2599_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2599_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2600_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2600_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2601_K2_E5                          (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2601_K2_E5_SHIFT                    3
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2602_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2602_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2603_K2_E5                          (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2603_K2_E5_SHIFT                    5
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2604_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2604_K2_E5_SHIFT                    6
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2605_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2605_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2180_K2_E5                                              0x00b144UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2180_RESERVEDFIELD2606_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2180_RESERVEDFIELD2606_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2181_K2_E5                                              0x00b148UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2181_RESERVEDFIELD2607_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2181_RESERVEDFIELD2607_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2182_K2_E5                                              0x00b14cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2182_RESERVEDFIELD2608_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2182_RESERVEDFIELD2608_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2183_K2_E5                                              0x00b150UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2183_RESERVEDFIELD2609_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2183_RESERVEDFIELD2609_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2184_K2_E5                                              0x00b154UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2184_RESERVEDFIELD2610_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2184_RESERVEDFIELD2610_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2185_K2_E5                                              0x00b158UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2185_RESERVEDFIELD2611_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2185_RESERVEDFIELD2611_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2186_K2_E5                                              0x00b15cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2186_RESERVEDFIELD2612_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2186_RESERVEDFIELD2612_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2187_K2_E5                                              0x00b160UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2187_RESERVEDFIELD2613_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2187_RESERVEDFIELD2613_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2188_K2_E5                                              0x00b164UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2188_RESERVEDFIELD2614_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2188_RESERVEDFIELD2614_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2189_K2_E5                                              0x00b168UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2189_RESERVEDFIELD2615_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2189_RESERVEDFIELD2615_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2190_K2_E5                                              0x00b16cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2190_RESERVEDFIELD2616_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2190_RESERVEDFIELD2616_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2191_K2_E5                                              0x00b170UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2191_RESERVEDFIELD2617_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2191_RESERVEDFIELD2617_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2192_K2_E5                                              0x00b174UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2192_RESERVEDFIELD2618_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2192_RESERVEDFIELD2618_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2193_K2_E5                                              0x00b178UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2193_RESERVEDFIELD2619_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2193_RESERVEDFIELD2619_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2194_K2_E5                                              0x00b17cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2194_RESERVEDFIELD2620_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2194_RESERVEDFIELD2620_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2195_K2_E5                                              0x00b180UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2195_RESERVEDFIELD2621_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2195_RESERVEDFIELD2621_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2196_K2_E5                                              0x00b184UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2196_RESERVEDFIELD2622_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2196_RESERVEDFIELD2622_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2197_K2_E5                                              0x00b188UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2197_RESERVEDFIELD2623_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2197_RESERVEDFIELD2623_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_K2_E5                                              0x00b18cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2624_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2624_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2625_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2625_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2626_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2626_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2627_K2_E5                          (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2627_K2_E5_SHIFT                    3
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2628_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2628_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2629_K2_E5                          (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2629_K2_E5_SHIFT                    5
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2630_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2630_K2_E5_SHIFT                    6
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2631_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2631_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2199_K2_E5                                              0x00b190UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2199_RESERVEDFIELD2632_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2199_RESERVEDFIELD2632_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2199_RESERVEDFIELD2633_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2199_RESERVEDFIELD2633_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2199_RESERVEDFIELD2634_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2199_RESERVEDFIELD2634_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_K2_E5                                              0x00b194UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2635_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2635_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2636_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2636_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2637_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2637_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2638_K2_E5                          (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2638_K2_E5_SHIFT                    3
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2639_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2639_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2640_K2_E5                          (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2640_K2_E5_SHIFT                    5
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2641_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2641_K2_E5_SHIFT                    6
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2642_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2642_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2201_K2_E5                                               0x00b200UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2202_K2_E5                                               0x00b204UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2202_RESERVEDFIELD2644_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2202_RESERVEDFIELD2644_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2203_K2_E5                                               0x00b208UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2203_RESERVEDFIELD2645_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2203_RESERVEDFIELD2645_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2203_RESERVEDFIELD2646_K2_E5                           (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2203_RESERVEDFIELD2646_K2_E5_SHIFT                     5
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2203_RESERVEDFIELD2647_K2_E5                           (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2203_RESERVEDFIELD2647_K2_E5_SHIFT                     6
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2204_K2_E5                                               0x00b218UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2204_RESERVEDFIELD2648_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2204_RESERVEDFIELD2648_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2204_RESERVEDFIELD2649_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2204_RESERVEDFIELD2649_K2_E5_SHIFT                     1
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2205_K2_E5                                               0x00b21cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2206_K2_E5                                               0x00b220UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2206_RESERVEDFIELD2651_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2206_RESERVEDFIELD2651_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2207_K2_E5                                               0x00b224UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2207_RESERVEDFIELD2652_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2207_RESERVEDFIELD2652_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2207_RESERVEDFIELD2653_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2207_RESERVEDFIELD2653_K2_E5_SHIFT                     1
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2208_K2_E5                                               0x00b228UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2209_K2_E5                                               0x00b22cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2209_RESERVEDFIELD2655_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2209_RESERVEDFIELD2655_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2210_K2_E5                                               0x00b230UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2211_K2_E5                                               0x00b234UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2211_RESERVEDFIELD2657_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2211_RESERVEDFIELD2657_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2212_K2_E5                                               0x00b240UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2212_RESERVEDFIELD2658_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2212_RESERVEDFIELD2658_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2212_RESERVEDFIELD2659_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2212_RESERVEDFIELD2659_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2212_RESERVEDFIELD2660_K2_E5                           (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2212_RESERVEDFIELD2660_K2_E5_SHIFT                     2
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2213_K2_E5                                               0x00b244UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2213_RESERVEDFIELD2661_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2213_RESERVEDFIELD2661_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2214_K2_E5                                               0x00b248UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2215_K2_E5                                               0x00b258UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2216_K2_E5                                               0x00b25cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2216_RESERVEDFIELD2664_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2216_RESERVEDFIELD2664_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2217_K2_E5                                               0x00b260UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2218_K2_E5                                               0x00b264UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2218_RESERVEDFIELD2666_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2218_RESERVEDFIELD2666_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2219_K2_E5                                               0x00b268UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2220_K2_E5                                               0x00b26cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2221_K2_E5                                               0x00b270UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2222_K2_E5                                               0x00b274UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2223_K2_E5                                               0x00b278UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2224_K2_E5                                               0x00b290UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2224_RESERVEDFIELD2672_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2224_RESERVEDFIELD2672_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2224_RESERVEDFIELD2673_K2_E5                           (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2224_RESERVEDFIELD2673_K2_E5_SHIFT                     2
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2224_RESERVEDFIELD2674_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2224_RESERVEDFIELD2674_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2225_K2_E5                                               0x00b294UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2225_RESERVEDFIELD2675_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2225_RESERVEDFIELD2675_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2225_RESERVEDFIELD2676_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2225_RESERVEDFIELD2676_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2226_K2_E5                                               0x00b298UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2226_RESERVEDFIELD2677_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2226_RESERVEDFIELD2677_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2226_RESERVEDFIELD2678_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2226_RESERVEDFIELD2678_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2227_K2_E5                                               0x00b29cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2227_RESERVEDFIELD2679_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2227_RESERVEDFIELD2679_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2228_K2_E5                                               0x00b2a0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2229_K2_E5                                               0x00b2a4UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2230_K2_E5                                               0x00b2a8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2231_K2_E5                                               0x00b2acUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2231_RESERVEDFIELD2683_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2231_RESERVEDFIELD2683_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2232_K2_E5                                               0x00b2b0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2233_K2_E5                                               0x00b2b4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2233_RESERVEDFIELD2685_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2233_RESERVEDFIELD2685_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2234_K2_E5                                               0x00b2b8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2235_K2_E5                                               0x00b2bcUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2235_RESERVEDFIELD2687_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2235_RESERVEDFIELD2687_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2236_K2_E5                                               0x00b2c0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2237_K2_E5                                               0x00b2c4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2237_RESERVEDFIELD2689_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2237_RESERVEDFIELD2689_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2238_K2_E5                                               0x00b2c8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2239_K2_E5                                               0x00b2ccUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2239_RESERVEDFIELD2691_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2239_RESERVEDFIELD2691_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2240_K2_E5                                               0x00b2d0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2241_K2_E5                                               0x00b2d4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2241_RESERVEDFIELD2693_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2241_RESERVEDFIELD2693_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2242_K2_E5                                               0x00b2d8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2243_K2_E5                                               0x00b2dcUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2243_RESERVEDFIELD2695_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2243_RESERVEDFIELD2695_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2244_K2_E5                                               0x00b2e0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2245_K2_E5                                               0x00b2e4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2245_RESERVEDFIELD2697_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2245_RESERVEDFIELD2697_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2246_K2_E5                                               0x00b300UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2247_K2_E5                                               0x00b304UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2248_K2_E5                                               0x00b308UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2249_K2_E5                                               0x00b30cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2249_RESERVEDFIELD2701_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2249_RESERVEDFIELD2701_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2250_K2_E5                                               0x00b310UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2251_K2_E5                                               0x00b314UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2251_RESERVEDFIELD2703_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2251_RESERVEDFIELD2703_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2252_K2_E5                                               0x00b318UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2253_K2_E5                                               0x00b31cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2253_RESERVEDFIELD2705_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2253_RESERVEDFIELD2705_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2254_K2_E5                                               0x00b320UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2255_K2_E5                                               0x00b324UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2255_RESERVEDFIELD2707_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2255_RESERVEDFIELD2707_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2256_K2_E5                                               0x00b328UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2257_K2_E5                                               0x00b32cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2257_RESERVEDFIELD2709_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2257_RESERVEDFIELD2709_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2258_K2_E5                                               0x00b330UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2259_K2_E5                                               0x00b334UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2259_RESERVEDFIELD2711_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2259_RESERVEDFIELD2711_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2260_K2_E5                                               0x00b338UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2261_K2_E5                                               0x00b33cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2261_RESERVEDFIELD2713_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2261_RESERVEDFIELD2713_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2262_K2_E5                                               0x00b340UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2263_K2_E5                                               0x00b344UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2263_RESERVEDFIELD2715_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2263_RESERVEDFIELD2715_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2264_K2_E5                                               0x00b358UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2264_RESERVEDFIELD2716_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2264_RESERVEDFIELD2716_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2264_RESERVEDFIELD2717_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2264_RESERVEDFIELD2717_K2_E5_SHIFT                     1
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2265_K2_E5                                               0x00b35cUL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2266_K2_E5                                               0x00b360UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2267_K2_E5                                               0x00b380UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2267_RESERVEDFIELD2720_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2267_RESERVEDFIELD2720_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2268_K2_E5                                               0x00b384UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2269_K2_E5                                               0x00b388UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2270_K2_E5                                               0x00b38cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2271_K2_E5                                               0x00b390UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2272_K2_E5                                               0x00b394UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2273_K2_E5                                               0x00b398UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2274_K2_E5                                               0x00b39cUL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2275_K2_E5                                               0x00b3a0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2276_K2_E5                                               0x00b3a4UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2277_K2_E5                                               0x00b3a8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2278_K2_E5                                               0x00b3acUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2278_RESERVEDFIELD2731_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2278_RESERVEDFIELD2731_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_AFE_CAL_CTRL_K2_E5                                                      0x00b400UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_AFE_CAL_CTRL_RXLOS_OFFSETCAL_K2_E5                                    (0x1<<0) // Enables analog LOS offset calibration circuits.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_AFE_CAL_CTRL_RXLOS_OFFSETCAL_K2_E5_SHIFT                              0
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2279_K2_E5                                              0x00b404UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2279_RESERVEDFIELD2732_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2279_RESERVEDFIELD2732_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2280_K2_E5                                              0x00b408UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2280_RESERVEDFIELD2733_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2280_RESERVEDFIELD2733_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_CTRL0_K2_E5                                                  0x00b40cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_CTRL0_EN_K2_E5                                             (0x1<<0) // Enables the run-length detection digital LOS filter.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_CTRL0_EN_K2_E5_SHIFT                                       0
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_CTRL1_K2_E5                                                  0x00b410UL //Access:RW   DataWidth:0x8    // Value of run-length which will trigger an LOS condition.
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_STATUS0_K2_E5                                                0x00b414UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_K2_E5                                       (0x1<<0) // Indicates that the run-length filter is currently exceeding the specified run-length threshold.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY_K2_E5                                (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the specified run-length threshold.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY_K2_E5_SHIFT                          1
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL0_K2_E5                                                      0x00b440UL //Access:RW   DataWidth:0x8    // Digital Rx LOS glitch filter assertion threshold.  Determines the number of consecutive clk_i clock cycles that the analog  LOS must remain a logic 1 before the output of the filter will assert.  Can be disabled by writing a value of 0x00.
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL1_K2_E5                                                      0x00b444UL //Access:RW   DataWidth:0x8    // Digital Rx LOS glitch filter assertion threshold.  Determines the number of consecutive clk_i clock cycles that the analog  LOS must remain a logic 1 before the output of the filter will assert.  Can be disabled by writing a value of 0x0000.
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL2_K2_E5                                                      0x00b448UL //Access:RW   DataWidth:0x8    // Digital Rx LOS glitch filter assertion threshold.  Determines the number of consecutive clk_i clock cycles that the raw analog  LOS must remain a logic 1 before the output of the filter will assert.  Can be disabled by writing a value of 0x000000.
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL3_K2_E5                                                      0x00b44cUL //Access:RW   DataWidth:0x8    // Same as above.
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL4_K2_E5                                                      0x00b450UL //Access:RW   DataWidth:0x8    // Same as above.
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL5_K2_E5                                                      0x00b454UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL5_DEASSERT_THRESHOLD_25_24_K2_E5                           (0x3<<0) // Same as above.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL5_DEASSERT_THRESHOLD_25_24_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL6_K2_E5                                                      0x00b458UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL6_EN_K2_E5                                                 (0x1<<0) // Enables the digital deglitching filter.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL6_EN_K2_E5_SHIFT                                           0
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2281_K2_E5                                              0x00b480UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2281_RESERVEDFIELD2734_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2281_RESERVEDFIELD2734_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2282_K2_E5                                              0x00b484UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2283_K2_E5                                              0x00b488UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2284_K2_E5                                              0x00b48cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2285_K2_E5                                              0x00b490UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2285_RESERVEDFIELD2738_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2285_RESERVEDFIELD2738_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_OVERRIDE_CTRL0_K2_E5                                                    0x00b4c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN_K2_E5                                         (0x1<<0) // Override enable for the LOS output of the digital filtering logic.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE_K2_E5                                      (0x1<<4) // Override value for the LOS output of the digital filtering logic.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE_K2_E5_SHIFT                                4
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2286_K2_E5                                              0x00b4c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2286_RESERVEDFIELD2739_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2286_RESERVEDFIELD2739_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2286_RESERVEDFIELD2740_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2286_RESERVEDFIELD2740_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2287_K2_E5                                              0x00b4c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2287_RESERVEDFIELD2741_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2287_RESERVEDFIELD2741_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2287_RESERVEDFIELD2742_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2287_RESERVEDFIELD2742_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2288_K2_E5                                              0x00b4ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2288_RESERVEDFIELD2743_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2288_RESERVEDFIELD2743_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2288_RESERVEDFIELD2744_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2288_RESERVEDFIELD2744_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2289_K2_E5                                              0x00b500UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2289_RESERVEDFIELD2745_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2289_RESERVEDFIELD2745_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2289_RESERVEDFIELD2746_K2_E5                          (0x7<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2289_RESERVEDFIELD2746_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2289_RESERVEDFIELD2747_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2289_RESERVEDFIELD2747_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2290_K2_E5                                              0x00b504UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2290_RESERVEDFIELD2748_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2290_RESERVEDFIELD2748_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2290_RESERVEDFIELD2749_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2290_RESERVEDFIELD2749_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2290_RESERVEDFIELD2750_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2290_RESERVEDFIELD2750_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2290_RESERVEDFIELD2751_K2_E5                          (0xf<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2290_RESERVEDFIELD2751_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2291_K2_E5                                              0x00b508UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2292_K2_E5                                              0x00b50cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2293_K2_E5                                              0x00b518UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2293_RESERVEDFIELD2754_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2293_RESERVEDFIELD2754_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2294_K2_E5                                              0x00b544UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2294_RESERVEDFIELD2755_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2294_RESERVEDFIELD2755_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2294_RESERVEDFIELD2756_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2294_RESERVEDFIELD2756_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2295_K2_E5                                              0x00b564UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2295_RESERVEDFIELD2757_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2295_RESERVEDFIELD2757_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2296_K2_E5                                              0x00b580UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2296_RESERVEDFIELD2758_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2296_RESERVEDFIELD2758_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2297_K2_E5                                              0x00b5c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2297_RESERVEDFIELD2759_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2297_RESERVEDFIELD2759_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2297_RESERVEDFIELD2760_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2297_RESERVEDFIELD2760_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_K2_E5                                                           0x00b5c4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_LOS_READY_K2_E5                                               (0x1<<0) // Indicates that digital and analog Rx LOS blocks are in LOS mode.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_LOS_READY_K2_E5_SHIFT                                         0
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_RESERVEDFIELD2761_K2_E5                                       (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_RESERVEDFIELD2761_K2_E5_SHIFT                                 1
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_LOS_K2_E5                                                     (0x1<<2) // The filtered LOS signal value.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_LOS_K2_E5_SHIFT                                               2
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_LOS_RAW_K2_E5                                                 (0x1<<3) // The unfiltered LOS signal value.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_LOS_RAW_K2_E5_SHIFT                                           3
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_LOS_NO_EII_K2_E5                                              (0x1<<4) // The filtered LOS signal value before EII override logic.
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_LOS_NO_EII_K2_E5_SHIFT                                        4
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_RESERVEDFIELD2762_K2_E5                                       (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_RESERVEDFIELD2762_K2_E5_SHIFT                                 5
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2298_K2_E5                                                  0x00b600UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2298_RESERVEDFIELD2763_K2_E5                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2298_RESERVEDFIELD2763_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2299_K2_E5                                                  0x00b604UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2299_RESERVEDFIELD2764_K2_E5                              (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2299_RESERVEDFIELD2764_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2300_K2_E5                                                  0x00b608UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2301_K2_E5                                                  0x00b60cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2301_RESERVEDFIELD2766_K2_E5                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2301_RESERVEDFIELD2766_K2_E5_SHIFT                        0
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2301_RESERVEDFIELD2767_K2_E5                              (0xf<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2301_RESERVEDFIELD2767_K2_E5_SHIFT                        1
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2302_K2_E5                                                  0x00b640UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2303_K2_E5                                                  0x00b644UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2303_RESERVEDFIELD2769_K2_E5                              (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2303_RESERVEDFIELD2769_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2304_K2_E5                                                  0x00b648UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2305_K2_E5                                                  0x00b64cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2305_RESERVEDFIELD2771_K2_E5                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2305_RESERVEDFIELD2771_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2306_K2_E5                                                  0x00b680UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2306_RESERVEDFIELD2772_K2_E5                              (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2306_RESERVEDFIELD2772_K2_E5_SHIFT                        0
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2306_RESERVEDFIELD2773_K2_E5                              (0xf<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2306_RESERVEDFIELD2773_K2_E5_SHIFT                        2
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2307_K2_E5                                                  0x00b684UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2308_K2_E5                                                  0x00b688UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2308_RESERVEDFIELD2775_K2_E5                              (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2308_RESERVEDFIELD2775_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2309_K2_E5                                                  0x00b68cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2310_K2_E5                                                  0x00b690UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2310_RESERVEDFIELD2777_K2_E5                              (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2310_RESERVEDFIELD2777_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2311_K2_E5                                                  0x00b694UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2312_K2_E5                                                  0x00b698UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2312_RESERVEDFIELD2779_K2_E5                              (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2312_RESERVEDFIELD2779_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2313_K2_E5                                                  0x00b6c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2313_RESERVEDFIELD2780_K2_E5                              (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2313_RESERVEDFIELD2780_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2314_K2_E5                                                  0x00b6c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2314_RESERVEDFIELD2781_K2_E5                              (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2314_RESERVEDFIELD2781_K2_E5_SHIFT                        0
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2314_RESERVEDFIELD2782_K2_E5                              (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2314_RESERVEDFIELD2782_K2_E5_SHIFT                        4
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2315_K2_E5                                                  0x00b6c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2315_RESERVEDFIELD2783_K2_E5                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2315_RESERVEDFIELD2783_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2316_K2_E5                                                  0x00b700UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2316_RESERVEDFIELD2784_K2_E5                              (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2316_RESERVEDFIELD2784_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2317_K2_E5                                                  0x00b704UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2318_K2_E5                                                  0x00b708UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2319_K2_E5                                                  0x00b70cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2320_K2_E5                                                  0x00b710UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2321_K2_E5                                                  0x00b714UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2322_K2_E5                                                  0x00b718UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2323_K2_E5                                                  0x00b71cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2324_K2_E5                                                  0x00b720UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2324_RESERVEDFIELD2792_K2_E5                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2324_RESERVEDFIELD2792_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2325_K2_E5                                                  0x00b740UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2325_RESERVEDFIELD2793_K2_E5                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2325_RESERVEDFIELD2793_K2_E5_SHIFT                        0
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2325_RESERVEDFIELD2794_K2_E5                              (0xf<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2325_RESERVEDFIELD2794_K2_E5_SHIFT                        1
+#define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2326_K2_E5                                                  0x00b744UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_BIST_TX_CTRL_K2_E5                                                                 0x00b800UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_BIST_TX_CTRL_EN_K2_E5                                                            (0x1<<0) // Enables BIST Tx data generation.
+  #define PHY_NW_IP_REG_LN2_BIST_TX_CTRL_EN_K2_E5_SHIFT                                                      0
+  #define PHY_NW_IP_REG_LN2_BIST_TX_CTRL_PATTERN_SEL_K2_E5                                                   (0xf<<1) // Selects the pattern to transmitted: 0x1  PRBS 0xC1 0x2  PRBS 0x221 0x3  PRBS 0xA01 0x4  PRBS 0xC001 0x5  PRBS 0x840001 0x6  PRBS 0x90000001 0x7  User defined pattern UDP 0x9  MAC Tx data
+  #define PHY_NW_IP_REG_LN2_BIST_TX_CTRL_PATTERN_SEL_K2_E5_SHIFT                                             1
+#define PHY_NW_IP_REG_LN2_BIST_TX_RESERVEDREGISTER2327_K2_E5                                                 0x00b804UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_BIST_TX_RESERVEDREGISTER2328_K2_E5                                                 0x00b808UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_BIST_TX_RESERVEDREGISTER2329_K2_E5                                                 0x00b80cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_BIST_TX_RESERVEDREGISTER2330_K2_E5                                                 0x00b810UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_BIST_TX_BER_CTRL0_K2_E5                                                            0x00b818UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_BIST_TX_BER_CTRL0_MODE_K2_E5                                                     (0x3<<0) // Controls what type of error injection is used: 0x0  None 0x1  Single cycle error 0x2  Timer based
+  #define PHY_NW_IP_REG_LN2_BIST_TX_BER_CTRL0_MODE_K2_E5_SHIFT                                               0
+#define PHY_NW_IP_REG_LN2_BIST_TX_BER_CTRL1_K2_E5                                                            0x00b81cUL //Access:RW   DataWidth:0x8    // Number of cycles between single bit-error injection
+#define PHY_NW_IP_REG_LN2_BIST_TX_BER_CTRL2_K2_E5                                                            0x00b820UL //Access:RW   DataWidth:0x8    // Number of cycles between single bit-error injection
+#define PHY_NW_IP_REG_LN2_BIST_TX_BER_CTRL3_K2_E5                                                            0x00b824UL //Access:RW   DataWidth:0x8    // Sets the Tx data bits to be flipped.
+#define PHY_NW_IP_REG_LN2_BIST_TX_BER_CTRL4_K2_E5                                                            0x00b828UL //Access:RW   DataWidth:0x8    // Sets the Tx data bits to be flipped.
+#define PHY_NW_IP_REG_LN2_BIST_TX_BER_CTRL5_K2_E5                                                            0x00b82cUL //Access:RW   DataWidth:0x8    // Sets the Tx data bits to be flipped.
+#define PHY_NW_IP_REG_LN2_BIST_TX_BER_CTRL6_K2_E5                                                            0x00b830UL //Access:RW   DataWidth:0x8    // Sets the Tx data bits to be flipped.
+#define PHY_NW_IP_REG_LN2_BIST_TX_BER_CTRL7_K2_E5                                                            0x00b834UL //Access:RW   DataWidth:0x8    // Sets the Tx data bits to be flipped.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_SHIFT_AMOUNT_K2_E5                                                     0x00b880UL //Access:RW   DataWidth:0x8    // Determines the length of the UDP.  Must be set to d160 modulus udp_length.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_7_0_K2_E5                                                              0x00b890UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_15_8_K2_E5                                                             0x00b894UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_23_16_K2_E5                                                            0x00b898UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_31_24_K2_E5                                                            0x00b89cUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_39_32_K2_E5                                                            0x00b8a0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_47_40_K2_E5                                                            0x00b8a4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_55_48_K2_E5                                                            0x00b8a8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_63_56_K2_E5                                                            0x00b8acUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_71_64_K2_E5                                                            0x00b8b0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_79_72_K2_E5                                                            0x00b8b4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_87_80_K2_E5                                                            0x00b8b8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_95_88_K2_E5                                                            0x00b8bcUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_103_96_K2_E5                                                           0x00b8c0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_111_104_K2_E5                                                          0x00b8c4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_119_112_K2_E5                                                          0x00b8c8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_127_120_K2_E5                                                          0x00b8ccUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_135_128_K2_E5                                                          0x00b8d0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_143_136_K2_E5                                                          0x00b8d4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_151_144_K2_E5                                                          0x00b8d8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_159_152_K2_E5                                                          0x00b8dcUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_167_160_K2_E5                                                          0x00b8e0UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_175_168_K2_E5                                                          0x00b8e4UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_183_176_K2_E5                                                          0x00b8e8UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_191_184_K2_E5                                                          0x00b8ecUL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN2_BIST_TX_UDP_199_192_K2_E5                                                          0x00b8f0UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_K2_E5                                                                 0x00ba00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_EN_K2_E5                                                            (0x1<<0) // Enables BIST Rx data checking.
+  #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_EN_K2_E5_SHIFT                                                      0
+  #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_PATTERN_SEL_K2_E5                                                   (0xf<<1) // Selects the pattern to search for: 0x1  PRBS 0xC1 0x2  PRBS 0x221 0x3  PRBS 0xA01 0x4  PRBS 0xC001 0x5  PRBS 0x840001 0x6  PRBS 0x90000001 0x7  User defined pattern UDP 0x8  Auto-detect
+  #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_PATTERN_SEL_K2_E5_SHIFT                                             1
+  #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_CLEAR_BER_K2_E5                                                     (0x1<<5) // Clears the bit error counter.
+  #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_CLEAR_BER_K2_E5_SHIFT                                               5
+  #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_STOP_ERROR_COUNT_K2_E5                                              (0x1<<6) // Stops the error count from incrementing.  Can be used to read back the BER data coherently.
+  #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_STOP_ERROR_COUNT_K2_E5_SHIFT                                        6
+  #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_FORCE_LFSR_WITH_RXDATA_K2_E5                                        (0x1<<7) // Forces the PRBS LFSR to reseed with Rx data every cycle.  This will cause the bit error counter to be inaccurate.
+  #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_FORCE_LFSR_WITH_RXDATA_K2_E5_SHIFT                                  7
+#define PHY_NW_IP_REG_LN2_BIST_RX_STATUS_K2_E5                                                               0x00ba10UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_BIST_RX_STATUS_STATE_K2_E5                                                       (0x7<<0) // State of the BIST checker: 0x0  Off 0x1  Searching for pattern 0x2  Waiting for pattern lock conditions 0x3  Pattern lock acquired 0x4  Pattern lock lost
+  #define PHY_NW_IP_REG_LN2_BIST_RX_STATUS_STATE_K2_E5_SHIFT                                                 0
+  #define PHY_NW_IP_REG_LN2_BIST_RX_STATUS_PATTERN_DET_K2_E5                                                 (0xf<<3) // Indicates the pattern  detected: 0x0  No pattern detected 0x1  PRBS 0xC1 0x2  PRBS 0x221 0x3  PRBS 0xA01 0x4  PRBS 0xC001 0x5  PRBS 0x840001 0x6  PRBS 0x90000001 0x7  User defined pattern UDP
+  #define PHY_NW_IP_REG_LN2_BIST_RX_STATUS_PATTERN_DET_K2_E5_SHIFT                                           3
+#define PHY_NW_IP_REG_LN2_BIST_RX_BER_STATUS0_K2_E5                                                          0x00ba20UL //Access:R    DataWidth:0x8    // Number of bit errors.
+#define PHY_NW_IP_REG_LN2_BIST_RX_BER_STATUS1_K2_E5                                                          0x00ba24UL //Access:R    DataWidth:0x8    // Number of bit errors.
+#define PHY_NW_IP_REG_LN2_BIST_RX_BER_STATUS2_K2_E5                                                          0x00ba28UL //Access:R    DataWidth:0x8    // Number of bit errors.
+#define PHY_NW_IP_REG_LN2_BIST_RX_BER_STATUS4_K2_E5                                                          0x00ba30UL //Access:R    DataWidth:0x8    // Number of cycles that errors have been counted.
+#define PHY_NW_IP_REG_LN2_BIST_RX_BER_STATUS5_K2_E5                                                          0x00ba34UL //Access:R    DataWidth:0x8    // Number of cycles that errors have been counted.
+#define PHY_NW_IP_REG_LN2_BIST_RX_BER_STATUS6_K2_E5                                                          0x00ba38UL //Access:R    DataWidth:0x8    // Number of cycles that errors have been counted.
+#define PHY_NW_IP_REG_LN2_BIST_RX_LOCK_CTRL0_K2_E5                                                           0x00ba50UL //Access:RW   DataWidth:0x8    // Size of error sampling window to trigger pattern lock.
+#define PHY_NW_IP_REG_LN2_BIST_RX_LOCK_CTRL1_K2_E5                                                           0x00ba54UL //Access:RW   DataWidth:0x8    // Size of error sampling window to trigger pattern lock.
+#define PHY_NW_IP_REG_LN2_BIST_RX_LOCK_CTRL2_K2_E5                                                           0x00ba58UL //Access:RW   DataWidth:0x8    // Maximum number of errors allowed to trigger pattern lock.
+#define PHY_NW_IP_REG_LN2_BIST_RX_LOCK_CTRL3_K2_E5                                                           0x00ba5cUL //Access:RW   DataWidth:0x8    // Maximum number of errors allowed to trigger pattern lock.
+#define PHY_NW_IP_REG_LN2_BIST_RX_LOSS_LOCK_CTRL0_K2_E5                                                      0x00ba80UL //Access:RW   DataWidth:0x8    // Size of error sampling window to trigger pattern loss-of-lock.
+#define PHY_NW_IP_REG_LN2_BIST_RX_LOSS_LOCK_CTRL1_K2_E5                                                      0x00ba84UL //Access:RW   DataWidth:0x8    // Size of error sampling window to trigger pattern loss-of-lock.
+#define PHY_NW_IP_REG_LN2_BIST_RX_LOSS_LOCK_CTRL2_K2_E5                                                      0x00ba88UL //Access:RW   DataWidth:0x8    // Minimum number of errors allowed to trigger pattern loss-of-lock.
+#define PHY_NW_IP_REG_LN2_BIST_RX_LOSS_LOCK_CTRL3_K2_E5                                                      0x00ba8cUL //Access:RW   DataWidth:0x8    // Minimum number of errors allowed to trigger pattern loss-of-lock.
+#define PHY_NW_IP_REG_LN2_BIST_RX_LOSS_LOCK_CTRL4_K2_E5                                                      0x00ba90UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_BIST_RX_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_K2_E5                                  (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
+  #define PHY_NW_IP_REG_LN2_BIST_RX_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_K2_E5_SHIFT                            0
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_SHIFT_AMOUNT_K2_E5                                                     0x00bac0UL //Access:RW   DataWidth:0x8    // Determines the length of the UDP.  Must be set to d160 modulus udp_length.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_7_0_K2_E5                                                              0x00bad0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_15_8_K2_E5                                                             0x00bad4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_23_16_K2_E5                                                            0x00bad8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_31_24_K2_E5                                                            0x00badcUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_39_32_K2_E5                                                            0x00bae0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_47_40_K2_E5                                                            0x00bae4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_55_48_K2_E5                                                            0x00bae8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_63_56_K2_E5                                                            0x00baecUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_71_64_K2_E5                                                            0x00baf0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_79_72_K2_E5                                                            0x00baf4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_87_80_K2_E5                                                            0x00baf8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_95_88_K2_E5                                                            0x00bafcUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_103_96_K2_E5                                                           0x00bb00UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_111_104_K2_E5                                                          0x00bb04UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_119_112_K2_E5                                                          0x00bb08UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_127_120_K2_E5                                                          0x00bb0cUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_135_128_K2_E5                                                          0x00bb10UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_143_136_K2_E5                                                          0x00bb14UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_151_144_K2_E5                                                          0x00bb18UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_159_152_K2_E5                                                          0x00bb1cUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_167_160_K2_E5                                                          0x00bb20UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_175_168_K2_E5                                                          0x00bb24UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_183_176_K2_E5                                                          0x00bb28UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_191_184_K2_E5                                                          0x00bb2cUL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN2_BIST_RX_UDP_199_192_K2_E5                                                          0x00bb30UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN2_FEATURE_RXTERM_CFG0_K2_E5                                                          0x00bc00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_RXTERM_CFG0_AC_COUPLED_K2_E5                                             (0x1<<0) // Configures AC/DC coupling of the lane 0: DC coupled 1: AC coupled
+  #define PHY_NW_IP_REG_LN2_FEATURE_RXTERM_CFG0_AC_COUPLED_K2_E5_SHIFT                                       0
+#define PHY_NW_IP_REG_LN2_FEATURE_RXCLKDIV_CFG0_K2_E5                                                        0x00bc04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_RXCLKDIV_CFG0_EN_K2_E5                                                   (0x1<<0) // Enables turning on the divided rxclk output
+  #define PHY_NW_IP_REG_LN2_FEATURE_RXCLKDIV_CFG0_EN_K2_E5_SHIFT                                             0
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2331_K2_E5                                                 0x00bc10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2331_RESERVEDFIELD2800_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2331_RESERVEDFIELD2800_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2331_RESERVEDFIELD2801_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2331_RESERVEDFIELD2801_K2_E5_SHIFT                       1
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2332_K2_E5                                                 0x00bc14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2332_RESERVEDFIELD2802_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2332_RESERVEDFIELD2802_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2332_RESERVEDFIELD2803_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2332_RESERVEDFIELD2803_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2332_RESERVEDFIELD2804_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2332_RESERVEDFIELD2804_K2_E5_SHIFT                       2
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2332_RESERVEDFIELD2805_K2_E5                             (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2332_RESERVEDFIELD2805_K2_E5_SHIFT                       3
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2332_RESERVEDFIELD2806_K2_E5                             (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2332_RESERVEDFIELD2806_K2_E5_SHIFT                       4
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2332_RESERVEDFIELD2807_K2_E5                             (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2332_RESERVEDFIELD2807_K2_E5_SHIFT                       5
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2333_K2_E5                                                 0x00bc18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2333_RESERVEDFIELD2808_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2333_RESERVEDFIELD2808_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2333_RESERVEDFIELD2809_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2333_RESERVEDFIELD2809_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2333_RESERVEDFIELD2810_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2333_RESERVEDFIELD2810_K2_E5_SHIFT                       2
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2333_RESERVEDFIELD2811_K2_E5                             (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2333_RESERVEDFIELD2811_K2_E5_SHIFT                       3
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_K2_E5                                                 0x00bc1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2812_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2812_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2813_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2813_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2814_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2814_K2_E5_SHIFT                       2
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2815_K2_E5                             (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2815_K2_E5_SHIFT                       3
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2816_K2_E5                             (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2816_K2_E5_SHIFT                       4
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2817_K2_E5                             (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2817_K2_E5_SHIFT                       5
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2818_K2_E5                             (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2818_K2_E5_SHIFT                       6
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2819_K2_E5                             (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2819_K2_E5_SHIFT                       7
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2335_K2_E5                                                 0x00bc20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2335_RESERVEDFIELD2820_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2335_RESERVEDFIELD2820_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2335_RESERVEDFIELD2821_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2335_RESERVEDFIELD2821_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2335_RESERVEDFIELD2822_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2335_RESERVEDFIELD2822_K2_E5_SHIFT                       2
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2335_RESERVEDFIELD2823_K2_E5                             (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2335_RESERVEDFIELD2823_K2_E5_SHIFT                       3
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2335_RESERVEDFIELD2824_K2_E5                             (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2335_RESERVEDFIELD2824_K2_E5_SHIFT                       4
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2336_K2_E5                                                 0x00bc24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2336_RESERVEDFIELD2825_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2336_RESERVEDFIELD2825_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2336_RESERVEDFIELD2826_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2336_RESERVEDFIELD2826_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2336_RESERVEDFIELD2827_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2336_RESERVEDFIELD2827_K2_E5_SHIFT                       2
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2337_K2_E5                                                 0x00bc40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2337_RESERVEDFIELD2828_K2_E5                             (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2337_RESERVEDFIELD2828_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2338_K2_E5                                                 0x00bc44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2338_RESERVEDFIELD2829_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2338_RESERVEDFIELD2829_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2339_K2_E5                                                 0x00bc48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2339_RESERVEDFIELD2830_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2339_RESERVEDFIELD2830_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2339_RESERVEDFIELD2831_K2_E5                             (0x7f<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2339_RESERVEDFIELD2831_K2_E5_SHIFT                       1
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2340_K2_E5                                                 0x00bc4cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2341_K2_E5                                                 0x00bc50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2341_RESERVEDFIELD2833_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2341_RESERVEDFIELD2833_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2341_RESERVEDFIELD2834_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2341_RESERVEDFIELD2834_K2_E5_SHIFT                       1
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2342_K2_E5                                                 0x00bc54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2342_RESERVEDFIELD2835_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2342_RESERVEDFIELD2835_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2342_RESERVEDFIELD2836_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2342_RESERVEDFIELD2836_K2_E5_SHIFT                       1
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2343_K2_E5                                                 0x00bc58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2343_RESERVEDFIELD2837_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2343_RESERVEDFIELD2837_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2343_RESERVEDFIELD2838_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2343_RESERVEDFIELD2838_K2_E5_SHIFT                       1
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2344_K2_E5                                                 0x00bc80UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2344_RESERVEDFIELD2839_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2344_RESERVEDFIELD2839_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_CFG_K2_E5                                                       0x00bc84UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT0_K2_E5                                  (0x3<<0) // How many times to repeat CTLE adaptation sequence for initial adaptation set 0
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT0_K2_E5_SHIFT                            0
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT1_K2_E5                                  (0x3<<2) // How many times to repeat CTLE adaptation sequence for initial adaptation set 1
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT1_K2_E5_SHIFT                            2
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_CFG_RESERVEDFIELD2840_K2_E5                                   (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_CFG_RESERVEDFIELD2840_K2_E5_SHIFT                             4
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_CFG_RESERVEDFIELD2841_K2_E5                                   (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_CFG_RESERVEDFIELD2841_K2_E5_SHIFT                             6
+#define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_AGC_CFG_K2_E5                                                   0x00bc88UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN_K2_E5                                        (0x1<<0) // Enables AGC threshold adaptation for initial adaptation
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_AGC_CFG_RESERVEDFIELD2842_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_AGC_CFG_RESERVEDFIELD2842_K2_E5_SHIFT                         2
+#define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_APG_MAP_CFG_K2_E5                                               0x00bc8cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN_K2_E5                                    (0x1<<0) // Enables mapping GN_APG setting from AGC threshold for initial adaptation
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_APG_MAP_CFG_RESERVEDFIELD2843_K2_E5                           (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_APG_MAP_CFG_RESERVEDFIELD2843_K2_E5_SHIFT                     2
+#define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_LFG_CFG_K2_E5                                                   0x00bc90UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL_K2_E5                                       (0x3<<0) // Selects the CTLE EQ LFG adaptation method for initial adaptation set 0 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loop 0x3: Method 3: GN_APG and EQ_LFG combined closed-loop
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL_K2_E5                                       (0x3<<2) // Selects the CTLE EQ LFG adaptation method for initial adaptation set 1 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loop 0x3: Method 3: GN_APG and EQ_LFG combined closed-loop
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL_K2_E5_SHIFT                                 2
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_LFG_CFG_RESERVEDFIELD2844_K2_E5                               (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_LFG_CFG_RESERVEDFIELD2844_K2_E5_SHIFT                         4
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_LFG_CFG_RESERVEDFIELD2845_K2_E5                               (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_LFG_CFG_RESERVEDFIELD2845_K2_E5_SHIFT                         6
+#define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_K2_E5                                                  0x00bc94UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN_K2_E5                                  (0x1<<0) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 0
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN_K2_E5_SHIFT                            0
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN_K2_E5                                  (0x1<<1) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 0
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN_K2_E5_SHIFT                            1
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN_K2_E5                                  (0x1<<2) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 1
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN_K2_E5_SHIFT                            2
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN_K2_E5                                  (0x1<<3) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 1
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN_K2_E5_SHIFT                            3
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2846_K2_E5                              (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2846_K2_E5_SHIFT                        4
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2847_K2_E5                              (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2847_K2_E5_SHIFT                        5
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2848_K2_E5                              (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2848_K2_E5_SHIFT                        6
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2849_K2_E5                              (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2849_K2_E5_SHIFT                        7
+#define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG1_K2_E5                                                  0x00bc98UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL_K2_E5                               (0x3<<0) // Selects which HFG result to use for the initial adaptation set 0 0x0: Edge Based 0x1: Data Based 0x2: Average of Edge & Data result 0x3: Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL_K2_E5                               (0x3<<2) // Selects which HFG result to use for the initial adaptation set 1 0x0: Edge Based 0x1: Data Based 0x2: Average of Edge & Data result 0x3: Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG1_RESERVEDFIELD2850_K2_E5                              (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG1_RESERVEDFIELD2850_K2_E5_SHIFT                        4
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG1_RESERVEDFIELD2851_K2_E5                              (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG1_RESERVEDFIELD2851_K2_E5_SHIFT                        6
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2345_K2_E5                                                 0x00bc9cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2345_RESERVEDFIELD2852_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2345_RESERVEDFIELD2852_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_MBS_CFG_K2_E5                                                   0x00bca0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_K2_E5                                        (0x1<<0) // Enables CTLE midband shaping adaptation for initial adaptation set 0
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN_K2_E5                                        (0x1<<1) // Enables CTLE midband shaping adaptation for initial adaptation set 1
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN_K2_E5_SHIFT                                  1
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD2853_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD2853_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD2854_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD2854_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_K2_E5                                                 0x00bca4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2855_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2855_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2856_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2856_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2857_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2857_K2_E5_SHIFT                       2
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2858_K2_E5                             (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2858_K2_E5_SHIFT                       3
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2859_K2_E5                             (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2859_K2_E5_SHIFT                       4
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2860_K2_E5                             (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2860_K2_E5_SHIFT                       5
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2861_K2_E5                             (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2861_K2_E5_SHIFT                       6
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2862_K2_E5                             (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2862_K2_E5_SHIFT                       7
+#define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_K2_E5                                                              0x00bcc0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP1_EN_K2_E5                                                    (0x1<<0) // Enables DFE Tap 1. Tap1 will not be powered up if it is not enabled
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP1_EN_K2_E5_SHIFT                                              0
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP2_EN_K2_E5                                                    (0x1<<1) // Enables DFE Tap 2. Tap2 will not be powered up if it is not enabled
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP2_EN_K2_E5_SHIFT                                              1
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP3_EN_K2_E5                                                    (0x1<<2) // Enables DFE Tap 3. Tap3 will not be powered up if it is not enabled
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP3_EN_K2_E5_SHIFT                                              2
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP4_EN_K2_E5                                                    (0x1<<3) // Enables DFE Tap 4. Tap4 will not be powered up if it is not enabled
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP4_EN_K2_E5_SHIFT                                              3
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP5_EN_K2_E5                                                    (0x1<<4) // Enables DFE Tap 5. Tap5 will not be powered up if it is not enabled
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP5_EN_K2_E5_SHIFT                                              4
+#define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_CFG_K2_E5                                                        0x00bcc4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_CFG_METHOD_SEL_K2_E5                                           (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Based Zero Forcing
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_CFG_METHOD_SEL_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP1_CFG_K2_E5                                                   0x00bcc8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN_K2_E5                                    (0x1<<0) // Enables initial adaptations for Tap 1
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2863_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2863_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2864_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2864_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2865_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2865_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP2_CFG_K2_E5                                                   0x00bcccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN_K2_E5                                    (0x1<<0) // Enables initial adaptations for Tap 2
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2866_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2866_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2867_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2867_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2868_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2868_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP3_CFG_K2_E5                                                   0x00bcd0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN_K2_E5                                    (0x1<<0) // Enables initial adaptations for Tap 3
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2869_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2869_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2870_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2870_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2871_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2871_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP4_CFG_K2_E5                                                   0x00bcd4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN_K2_E5                                    (0x1<<0) // Enables initial adaptations for Tap 4
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2872_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2872_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2873_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2873_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2874_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2874_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP5_CFG_K2_E5                                                   0x00bcd8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN_K2_E5                                    (0x1<<0) // Enables initial adaptations for Tap 5
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2875_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2875_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2876_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2876_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2877_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2877_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_LN2_FEATURE_ADAPT_CONT_CFG0_K2_E5                                                      0x00bce0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_ADAPT_CONT_CFG0_EN_K2_E5                                                 (0x1<<0) // Enables continuous background adaptation
+  #define PHY_NW_IP_REG_LN2_FEATURE_ADAPT_CONT_CFG0_EN_K2_E5_SHIFT                                           0
+  #define PHY_NW_IP_REG_LN2_FEATURE_ADAPT_CONT_CFG0_RESERVEDFIELD2878_K2_E5                                  (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_ADAPT_CONT_CFG0_RESERVEDFIELD2878_K2_E5_SHIFT                            1
+#define PHY_NW_IP_REG_LN2_FEATURE_ADAPT_CONT_CFG1_K2_E5                                                      0x00bce4UL //Access:RW   DataWidth:0x8    // How often in ms to run continuous adaptations 1ms to ~279 mins
+#define PHY_NW_IP_REG_LN2_FEATURE_ADAPT_CONT_CFG2_K2_E5                                                      0x00bce8UL //Access:RW   DataWidth:0x8    // How often in ms to run continuous adaptations 1ms to ~279 mins
+#define PHY_NW_IP_REG_LN2_FEATURE_ADAPT_CONT_CFG3_K2_E5                                                      0x00bcecUL //Access:RW   DataWidth:0x8    // How often in ms to run continuous adaptations 1ms to ~279 mins
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2347_K2_E5                                                 0x00bcf0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2348_K2_E5                                                 0x00bcf4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2349_K2_E5                                                 0x00bcf8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2350_K2_E5                                                 0x00bcfcUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2351_K2_E5                                                 0x00bd00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2351_RESERVEDFIELD2883_K2_E5                             (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2351_RESERVEDFIELD2883_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2351_RESERVEDFIELD2884_K2_E5                             (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2351_RESERVEDFIELD2884_K2_E5_SHIFT                       2
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2352_K2_E5                                                 0x00bd04UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2353_K2_E5                                                 0x00bd08UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2354_K2_E5                                                 0x00bd0cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2355_K2_E5                                                 0x00bd10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2355_RESERVEDFIELD2888_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2355_RESERVEDFIELD2888_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2356_K2_E5                                                 0x00bd14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2356_RESERVEDFIELD2889_K2_E5                             (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2356_RESERVEDFIELD2889_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2356_RESERVEDFIELD2890_K2_E5                             (0x1f<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2356_RESERVEDFIELD2890_K2_E5_SHIFT                       3
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2357_K2_E5                                                 0x00bd18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2357_RESERVEDFIELD2891_K2_E5                             (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2357_RESERVEDFIELD2891_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2357_RESERVEDFIELD2892_K2_E5                             (0x1f<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2357_RESERVEDFIELD2892_K2_E5_SHIFT                       2
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2358_K2_E5                                                 0x00bd1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2358_RESERVEDFIELD2893_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2358_RESERVEDFIELD2893_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2358_RESERVEDFIELD2894_K2_E5                             (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2358_RESERVEDFIELD2894_K2_E5_SHIFT                       4
+#define PHY_NW_IP_REG_LN2_FEATURE_TEST_CFG0_K2_E5                                                            0x00bd40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_FEATURE_TEST_CFG0_RESERVEDFIELD2895_K2_E5                                        (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_TEST_CFG0_RESERVEDFIELD2895_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN2_FEATURE_TEST_CFG0_RX_CTRL_DIS_K2_E5                                              (0x1<<1) // Disables the firmware rx_ctrl MSM
+  #define PHY_NW_IP_REG_LN2_FEATURE_TEST_CFG0_RX_CTRL_DIS_K2_E5_SHIFT                                        1
+  #define PHY_NW_IP_REG_LN2_FEATURE_TEST_CFG0_RESERVEDFIELD2896_K2_E5                                        (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_TEST_CFG0_RESERVEDFIELD2896_K2_E5_SHIFT                                  2
+  #define PHY_NW_IP_REG_LN2_FEATURE_TEST_CFG0_RESERVEDFIELD2897_K2_E5                                        (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN2_FEATURE_TEST_CFG0_RESERVEDFIELD2897_K2_E5_SHIFT                                  3
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2359_K2_E5                                                 0x00bd60UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2360_K2_E5                                                 0x00bd64UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2361_K2_E5                                                 0x00bd68UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2362_K2_E5                                                 0x00bd6cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2363_K2_E5                                                 0x00bd70UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2364_K2_E5                                                 0x00bd74UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2365_K2_E5                                                 0x00bd78UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2366_K2_E5                                                 0x00bd7cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_K2_E5                                                              0x00be00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_MR_RESTART_TRAINING_K2_E5                                        (0x1<<0) // Starts link training procedure when asserted.  This is an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_MR_RESTART_TRAINING_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_MR_TRAINING_ENABLE_K2_E5                                         (0x1<<1) // Indicates to LTSM that link training procedure should be run; otherwise procedures skip directly to signal_det assertion.  This is an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_MR_TRAINING_ENABLE_K2_E5_SHIFT                                   1
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_SIGNAL_DETECT_K2_E5                                              (0x1<<2) // Output corresponding to link training signal detect variable.  Should be set when link training has completed successfully.
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_SIGNAL_DETECT_K2_E5_SHIFT                                        2
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_CLEAR_K2_E5                                                      (0x1<<3) // Synchronous reset for LT Tx block.
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_CLEAR_K2_E5_SHIFT                                                3
+#define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL1_K2_E5                                                              0x00be04UL //Access:RW   DataWidth:0x8    // Maximum time allowed for LT procedure.  If this is exceeded then the training_fail status will assert.  This is an 802.defined variable.  Value is encoded as: 39338 * DESIRED_DELAY * 2 ^logdata_width / data_width  Should be set to 500ns for 802.3 compliant timeout.
+#define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL2_K2_E5                                                              0x00be08UL //Access:RW   DataWidth:0x8    // Same as above.
+#define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL3_K2_E5                                                              0x00be0cUL //Access:RW   DataWidth:0x8    // Number of additional frames to send after both receivers have been trained and are ready.  This is an 802.3 defined variable.  Should be set between 100 and 300 for 802.3 compliance.
+#define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL4_K2_E5                                                              0x00be10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL4_WAIT_TIME_8_K2_E5                                                (0x1<<0) // Same as above.
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL4_WAIT_TIME_8_K2_E5_SHIFT                                          0
+#define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL5_K2_E5                                                              0x00be14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL5_FRAME_LOCK_K2_E5                                                 (0x1<<0) // Input to LTSM that receiver has acquired frame lock.  This value should be taken from the corresponding LT Rx register.  This  an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL5_FRAME_LOCK_K2_E5_SHIFT                                           0
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL5_RX_TRAINED_K2_E5                                                 (0x1<<1) // Input to LTSM indicating that the local receiver has completed training.  This is an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL5_RX_TRAINED_K2_E5_SHIFT                                           1
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL5_REMOTE_RX_READY_K2_E5                                            (0x1<<2) // Input to LTSM indicating that the remote receiver is trained and ready.  This value should be taken from the corresponding LT Rx registers.  This is an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL5_REMOTE_RX_READY_K2_E5_SHIFT                                      2
+#define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_K2_E5                                                             0x00be40UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_TRAINING_FAIL_K2_E5                                             (0x1<<0) // Output from LTSM indicating that link training has failed.  This is an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_TRAINING_FAIL_K2_E5_SHIFT                                       0
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_TRAINING_K2_E5                                                  (0x1<<1) // Output from LTSM indicating that link training is in progress.  This is an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_TRAINING_K2_E5_SHIFT                                            1
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_SIGNAL_DETECT_K2_E5                                             (0x1<<2) // Output from LTSM indicating that link training is complete and successful.  This is an 802.3 defined variable.  This value is only visible internally, and is not the signal_det value driven to PHY top-level.
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_SIGNAL_DETECT_K2_E5_SHIFT                                       2
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_FSM_LOCAL_RX_READY_K2_E5                                        (0x1<<4) // Output from LSM corresponding to 802.3 defined local_rx_ready variable. After this is asserted the corresponding frame status report field should be set.
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_FSM_LOCAL_RX_READY_K2_E5_SHIFT                                  4
+#define PHY_NW_IP_REG_LN2_LT_TX_PRBS_CTRL0_K2_E5                                                             0x00be4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LT_TX_PRBS_CTRL0_POLYNOMIAL_K2_E5                                                (0x7<<0) // Selects between CL72 and CL93 PRBS pattern. 0  CL72 1 + x^9 +x^11 1  CL93 1 + x^5 + x^6 + x^10 + x^11 2  CL93 1 + x^5 + x^6 + x^9 + x^11 3  CL93 1 + x^4 + x^6 + x^8 + x^11 4  CL93 1 + x^4 + x^6 + x^7 + x^11
+  #define PHY_NW_IP_REG_LN2_LT_TX_PRBS_CTRL0_POLYNOMIAL_K2_E5_SHIFT                                          0
+#define PHY_NW_IP_REG_LN2_LT_TX_PRBS_CTRL1_K2_E5                                                             0x00be50UL //Access:RW   DataWidth:0x8    // Initial PRBS LFSR seed.  This needs to be set according to the requirements in 802.3 CL72 or CL93 depending on the type of link training and lane bonding being performed.
+#define PHY_NW_IP_REG_LN2_LT_TX_PRBS_CTRL2_K2_E5                                                             0x00be54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LT_TX_PRBS_CTRL2_SEED_10_8_K2_E5                                                 (0x7<<0) // Same as above.
+  #define PHY_NW_IP_REG_LN2_LT_TX_PRBS_CTRL2_SEED_10_8_K2_E5_SHIFT                                           0
+#define PHY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL_K2_E5                                                0x00be80UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL_C_P1_K2_E5                                         (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00  hold 2'b01  increment 2'b10  decrement 2'b11  reserved
+  #define PHY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL_C_P1_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL_C_0_K2_E5                                          (0x3<<2) // Coefficient update request field for cursor tap.
+  #define PHY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL_C_0_K2_E5_SHIFT                                    2
+  #define PHY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL_C_M1_K2_E5                                         (0x3<<4) // Coefficient update request field for pre-cursor tap.
+  #define PHY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL_C_M1_K2_E5_SHIFT                                   4
+  #define PHY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL_INITIALIZE_K2_E5                                   (0x1<<6) // Coefficient update initialize field.
+  #define PHY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL_INITIALIZE_K2_E5_SHIFT                             6
+  #define PHY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL_PRESET_K2_E5                                       (0x1<<7) // Coefficient update preset field.
+  #define PHY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL_PRESET_K2_E5_SHIFT                                 7
+#define PHY_NW_IP_REG_LN2_LT_TX_STATUS_REPORT_CTRL_K2_E5                                                     0x00be88UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LT_TX_STATUS_REPORT_CTRL_C_P1_K2_E5                                              (0x3<<0) // Status report field for post-cursor tap. 2'b00  not updated 2'b01  minimum 2'b10  updated 2'b11  maximum
+  #define PHY_NW_IP_REG_LN2_LT_TX_STATUS_REPORT_CTRL_C_P1_K2_E5_SHIFT                                        0
+  #define PHY_NW_IP_REG_LN2_LT_TX_STATUS_REPORT_CTRL_C_0_K2_E5                                               (0x3<<2) // Status report field for cursor tap.
+  #define PHY_NW_IP_REG_LN2_LT_TX_STATUS_REPORT_CTRL_C_0_K2_E5_SHIFT                                         2
+  #define PHY_NW_IP_REG_LN2_LT_TX_STATUS_REPORT_CTRL_C_M1_K2_E5                                              (0x3<<4) // Status report field for pre-cursor tap.
+  #define PHY_NW_IP_REG_LN2_LT_TX_STATUS_REPORT_CTRL_C_M1_K2_E5_SHIFT                                        4
+  #define PHY_NW_IP_REG_LN2_LT_TX_STATUS_REPORT_CTRL_LOCAL_RX_READY_K2_E5                                    (0x1<<6) // Status report field to indicate local receiver is ready.  Should be set based on LTSM output of corresponding variable.
+  #define PHY_NW_IP_REG_LN2_LT_TX_STATUS_REPORT_CTRL_LOCAL_RX_READY_K2_E5_SHIFT                              6
+#define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS0_K2_E5                                                      0x00bec0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS0_CURRENT_K2_E5                                            (0x7<<0) // Current state of LTSM. 0x0  INITIALIZE 0x1  SEND_TRAINING 0x2  TRAIN_REMOTE 0x3  TRAIN_LOCAL 0x4  S7 0x5  TRAINING_FAILURE 0x6  LINK_READY 0x7  SEND_DATA
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS0_CURRENT_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS0_PREV1_K2_E5                                              (0x7<<4) // One state previous.
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS0_PREV1_K2_E5_SHIFT                                        4
+#define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS1_K2_E5                                                      0x00bec4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS1_PREV2_K2_E5                                              (0x7<<0) // Two states previous.
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS1_PREV2_K2_E5_SHIFT                                        0
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS1_PREV3_K2_E5                                              (0x7<<4) // Three states previous.
+  #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS1_PREV3_K2_E5_SHIFT                                        4
+#define PHY_NW_IP_REG_LN2_LT_RX_CTRL0_K2_E5                                                                  0x00bf00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LT_RX_CTRL0_CLEAR_K2_E5                                                          (0x1<<0) // Synchronous reset for LT Rx block.
+  #define PHY_NW_IP_REG_LN2_LT_RX_CTRL0_CLEAR_K2_E5_SHIFT                                                    0
+  #define PHY_NW_IP_REG_LN2_LT_RX_CTRL0_TRAINING_K2_E5                                                       (0x1<<1) // This is the 802.3 defined training variable.  It should be set according to corresponding LTSM output.
+  #define PHY_NW_IP_REG_LN2_LT_RX_CTRL0_TRAINING_K2_E5_SHIFT                                                 1
+#define PHY_NW_IP_REG_LN2_LT_RX_PRBS_CTRL0_K2_E5                                                             0x00bf08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_CTRL0_POLYNOMIAL_K2_E5                                                (0x7<<0) // Selects between CL72 and CL93 PRBS patterns. 0  CL72 1 + x^9 + x^11 1  CL93 1 + x^5 + x^6 + x^10 + x^11 2  CL93 1 + x^5 + x^6 + x^9 + x^11 3  CL93 1 + x^4 + x^6 + x^8 + x^11 4  CL93 1 + x^4 + x^6 + x^7 + x^11
+  #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_CTRL0_POLYNOMIAL_K2_E5_SHIFT                                          0
+#define PHY_NW_IP_REG_LN2_LT_RX_PRBS_CTRL1_K2_E5                                                             0x00bf0cUL //Access:RW   DataWidth:0x8    // Maximum number  of PRBS bit errors allowed in single LT frame for PRBS lock to be achieved.
+#define PHY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS0_K2_E5                                                           0x00bf14UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS0_UPDATE_K2_E5                                                  (0x1<<0) // Assertion indicates that PRBS status information has been updated.
+  #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS0_UPDATE_K2_E5_SHIFT                                            0
+  #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS0_LOCK_K2_E5                                                    (0x1<<1) // Indicates that a valid PRBS pattern has been detected in receiver LT frame.
+  #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS0_LOCK_K2_E5_SHIFT                                              1
+#define PHY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS1_K2_E5                                                           0x00bf18UL //Access:R    DataWidth:0x8    // Number of bit errors in PRBS pattern since last lock assertion event.
+#define PHY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS2_K2_E5                                                           0x00bf1cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS2_ERROR_COUNT_11_8_K2_E5                                        (0xf<<0) // Same as above.
+  #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS2_ERROR_COUNT_11_8_K2_E5_SHIFT                                  0
+#define PHY_NW_IP_REG_LN2_LT_RX_FRAME_CTRL_K2_E5                                                             0x00bf40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LT_RX_FRAME_CTRL_CLEAR_COUNT_K2_E5                                               (0x1<<0) // Clears both the absolute and erroneous frame counters.
+  #define PHY_NW_IP_REG_LN2_LT_RX_FRAME_CTRL_CLEAR_COUNT_K2_E5_SHIFT                                         0
+#define PHY_NW_IP_REG_LN2_LT_RX_FRAME_STATUS0_K2_E5                                                          0x00bf4cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LT_RX_FRAME_STATUS0_FRAME_LOCK_K2_E5                                             (0x1<<0) // Indicates that the receiver has locked to incoming LT frames.
+  #define PHY_NW_IP_REG_LN2_LT_RX_FRAME_STATUS0_FRAME_LOCK_K2_E5_SHIFT                                       0
+#define PHY_NW_IP_REG_LN2_LT_RX_FRAME_STATUS1_K2_E5                                                          0x00bf50UL //Access:R    DataWidth:0x8    // Total number of received frames since frame lock.
+#define PHY_NW_IP_REG_LN2_LT_RX_FRAME_STATUS2_K2_E5                                                          0x00bf54UL //Access:R    DataWidth:0x8    // Same as above.
+#define PHY_NW_IP_REG_LN2_LT_RX_FRAME_STATUS3_K2_E5                                                          0x00bf58UL //Access:R    DataWidth:0x8    // Total number of received frames  with a PRBS, DME, or framing error since frame lock.
+#define PHY_NW_IP_REG_LN2_LT_RX_FRAME_STATUS4_K2_E5                                                          0x00bf5cUL //Access:R    DataWidth:0x8    // Same as above.
+#define PHY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS_K2_E5                                              0x00bf80UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS_C_P1_K2_E5                                       (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00  hold 2'b01  increment 2'b10  decrement 2'b11  reserved
+  #define PHY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS_C_P1_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS_C_0_K2_E5                                        (0x3<<2) // Received coefficient update request field for cursor tap.
+  #define PHY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS_C_0_K2_E5_SHIFT                                  2
+  #define PHY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS_C_M1_K2_E5                                       (0x3<<4) // Received coefficient update request field for pre-cursor tap.
+  #define PHY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS_C_M1_K2_E5_SHIFT                                 4
+  #define PHY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS_INITIALIZE_K2_E5                                 (0x1<<6) // Received coefficient update initialize field.
+  #define PHY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS_INITIALIZE_K2_E5_SHIFT                           6
+  #define PHY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS_PRESET_K2_E5                                     (0x1<<7) // Received coefficient update preset field.
+  #define PHY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS_PRESET_K2_E5_SHIFT                               7
+#define PHY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS_K2_E5                                                          0x00bf88UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS_C_P1_K2_E5                                                   (0x3<<0) // Received status report field for post-cursor tap. 2'b00  not updated 2'b01  minimum 2'b10  updated 2'b11  maximum
+  #define PHY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS_C_P1_K2_E5_SHIFT                                             0
+  #define PHY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS_C_0_K2_E5                                                    (0x3<<2) // Received status report field for cursor tap.
+  #define PHY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS_C_0_K2_E5_SHIFT                                              2
+  #define PHY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS_C_M1_K2_E5                                                   (0x3<<4) // Received status report field for pre-cursor tap.
+  #define PHY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS_C_M1_K2_E5_SHIFT                                             4
+  #define PHY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS_LOCAL_RX_READY_K2_E5                                         (0x1<<6) // Received status report field to indicate local receiver is ready.
+  #define PHY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS_LOCAL_RX_READY_K2_E5_SHIFT                                   6
+  #define PHY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS_DME_ERROR_K2_E5                                              (0x1<<7) // Indicates differential manchester decoding error.  Not sticky.
+  #define PHY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS_DME_ERROR_K2_E5_SHIFT                                        7
+#define PHY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_K2_E5                                                        0x00c000UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_K2_E5                                    (0x1<<0) // RX clock loopback mode enable.   0x0 - mission mode 0x1 - select recovered clock from CDR as source of half-rate TX clock path.
+  #define PHY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_K2_E5                                    (0x1<<1) // TX clock loopback mode enable.  0x0 - mission mode 0x1 - MUX half-rate TX clock into LEQ gain stage.
+  #define PHY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_K2_E5                                      (0x1<<2) // Far-End Analog FEA loopback mode enable.  0x0 - mission mode 0x1 - loop back parallel data from RX data path to TX data path internal to AFE
+  #define PHY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_K2_E5_SHIFT                                2
+  #define PHY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_K2_E5                                      (0x1<<3) // Near-End Analog NEA loopback mode enable.  0x0 - mission mode 0x1 - loop back quarter rate data from TX data path to RX data path internal to AFE.
+  #define PHY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_K2_E5_SHIFT                                3
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2367_K2_E5                                                     0x00c004UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2367_RESERVEDFIELD2898_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2367_RESERVEDFIELD2898_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2367_RESERVEDFIELD2899_K2_E5                                 (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2367_RESERVEDFIELD2899_K2_E5_SHIFT                           2
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2367_RESERVEDFIELD2900_K2_E5                                 (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2367_RESERVEDFIELD2900_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2368_K2_E5                                                     0x00c008UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2368_RESERVEDFIELD2901_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2368_RESERVEDFIELD2901_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2368_RESERVEDFIELD2902_K2_E5                                 (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2368_RESERVEDFIELD2902_K2_E5_SHIFT                           2
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2368_RESERVEDFIELD2903_K2_E5                                 (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2368_RESERVEDFIELD2903_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2369_K2_E5                                                     0x00c00cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2369_RESERVEDFIELD2904_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2369_RESERVEDFIELD2904_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2370_K2_E5                                                     0x00c010UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2370_RESERVEDFIELD2905_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2370_RESERVEDFIELD2905_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2370_RESERVEDFIELD2906_K2_E5                                 (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2370_RESERVEDFIELD2906_K2_E5_SHIFT                           1
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2371_K2_E5                                                     0x00c014UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2371_RESERVEDFIELD2907_K2_E5                                 (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2371_RESERVEDFIELD2907_K2_E5_SHIFT                           2
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2372_K2_E5                                                     0x00c018UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2372_RESERVEDFIELD2908_K2_E5                                 (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2372_RESERVEDFIELD2908_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2373_K2_E5                                                     0x00c040UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2373_RESERVEDFIELD2909_K2_E5                                 (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2373_RESERVEDFIELD2909_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2373_RESERVEDFIELD2910_K2_E5                                 (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2373_RESERVEDFIELD2910_K2_E5_SHIFT                           4
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2373_RESERVEDFIELD2911_K2_E5                                 (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2373_RESERVEDFIELD2911_K2_E5_SHIFT                           6
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2374_K2_E5                                                     0x00c048UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2374_RESERVEDFIELD2912_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2374_RESERVEDFIELD2912_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2374_RESERVEDFIELD2913_K2_E5                                 (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2374_RESERVEDFIELD2913_K2_E5_SHIFT                           2
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2375_K2_E5                                                     0x00c04cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2375_RESERVEDFIELD2914_K2_E5                                 (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2375_RESERVEDFIELD2914_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2376_K2_E5                                                     0x00c050UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2376_RESERVEDFIELD2915_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2376_RESERVEDFIELD2915_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2376_RESERVEDFIELD2916_K2_E5                                 (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2376_RESERVEDFIELD2916_K2_E5_SHIFT                           2
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2377_K2_E5                                                     0x00c058UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2377_RESERVEDFIELD2917_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2377_RESERVEDFIELD2917_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2377_RESERVEDFIELD2918_K2_E5                                 (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2377_RESERVEDFIELD2918_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2378_K2_E5                                                     0x00c064UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2378_RESERVEDFIELD2919_K2_E5                                 (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2378_RESERVEDFIELD2919_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2378_RESERVEDFIELD2920_K2_E5                                 (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2378_RESERVEDFIELD2920_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2379_K2_E5                                                     0x00c06cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2379_RESERVEDFIELD2921_K2_E5                                 (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2379_RESERVEDFIELD2921_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2379_RESERVEDFIELD2922_K2_E5                                 (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2379_RESERVEDFIELD2922_K2_E5_SHIFT                           3
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2379_RESERVEDFIELD2923_K2_E5                                 (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2379_RESERVEDFIELD2923_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2380_K2_E5                                                     0x00c070UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2380_RESERVEDFIELD2924_K2_E5                                 (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2380_RESERVEDFIELD2924_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2381_K2_E5                                                     0x00c078UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2381_RESERVEDFIELD2925_K2_E5                                 (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2381_RESERVEDFIELD2925_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN3_TOP_DPL_TXDP_CTRL1_K2_E5                                                           0x00c088UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_EN_K2_E5                                     (0x1<<0) // Enables register control of TX data path mux in DPL
+  #define PHY_NW_IP_REG_LN3_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_EN_K2_E5_SHIFT                               0
+  #define PHY_NW_IP_REG_LN3_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_VAL_K2_E5                                    (0x7<<1) // Select value for TX data path mux in DPL.  The corresponding mux select override enable must also be set. 0 : TX data from customer logics 1: RX data for Far-End-Digital FED loopback 2: BIST generator 3: AN/802.3 4: LT/802.3 5-7: reserved
+  #define PHY_NW_IP_REG_LN3_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_VAL_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_LN3_TOP_DPL_TXDP_CTRL1_TXPOLARITY_K2_E5                                              (0x1<<4) // TX data polarity control
+  #define PHY_NW_IP_REG_LN3_TOP_DPL_TXDP_CTRL1_TXPOLARITY_K2_E5_SHIFT                                        4
+  #define PHY_NW_IP_REG_LN3_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_K2_E5                                   (0x1<<5) // Controls tx_en for Far-End-Digital FED loopback mode.  In FED loopback mode, tx_en will be set when this field is set to 1 and rxvalid is 1.
+  #define PHY_NW_IP_REG_LN3_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_K2_E5_SHIFT                             5
+#define PHY_NW_IP_REG_LN3_TOP_DPL_RXDP_CTRL1_K2_E5                                                           0x00c090UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_K2_E5                                             (0x1<<0) // A mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
+  #define PHY_NW_IP_REG_LN3_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_K2_E5_SHIFT                                       0
+  #define PHY_NW_IP_REG_LN3_TOP_DPL_RXDP_CTRL1_BIT_STRIP_EVEN_K2_E5                                          (0x1<<1) // A bit stripping selection for RX data path in the DPL 1: Even bits stripped from RX data 0: Odd bits stripped from Rx data
+  #define PHY_NW_IP_REG_LN3_TOP_DPL_RXDP_CTRL1_BIT_STRIP_EVEN_K2_E5_SHIFT                                    1
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2382_K2_E5                                                     0x00c094UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2382_RESERVEDFIELD2926_K2_E5                                 (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2382_RESERVEDFIELD2926_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2382_RESERVEDFIELD2927_K2_E5                                 (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2382_RESERVEDFIELD2927_K2_E5_SHIFT                           3
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2383_K2_E5                                                     0x00c098UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2383_RESERVEDFIELD2928_K2_E5                                 (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2383_RESERVEDFIELD2928_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2383_RESERVEDFIELD2929_K2_E5                                 (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2383_RESERVEDFIELD2929_K2_E5_SHIFT                           3
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2383_RESERVEDFIELD2930_K2_E5                                 (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2383_RESERVEDFIELD2930_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN3_TOP_PHY_IF_STATUS_K2_E5                                                            0x00c09cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_PHY_IF_STATUS_LN_OK_K2_E5                                                    (0x1<<0) // LANE OK status
+  #define PHY_NW_IP_REG_LN3_TOP_PHY_IF_STATUS_LN_OK_K2_E5_SHIFT                                              0
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2384_K2_E5                                                     0x00c0c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2384_RESERVEDFIELD2931_K2_E5                                 (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2384_RESERVEDFIELD2931_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2384_RESERVEDFIELD2932_K2_E5                                 (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2384_RESERVEDFIELD2932_K2_E5_SHIFT                           3
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2385_K2_E5                                                     0x00c0c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2385_RESERVEDFIELD2933_K2_E5                                 (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2385_RESERVEDFIELD2933_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2385_RESERVEDFIELD2934_K2_E5                                 (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2385_RESERVEDFIELD2934_K2_E5_SHIFT                           3
+#define PHY_NW_IP_REG_LN3_TOP_LN_STAT_CTRL0_K2_E5                                                            0x00c0e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_LN_STAT_CTRL0_RXVALID_K2_E5                                                  (0x1<<0) // rxvalid status output
+  #define PHY_NW_IP_REG_LN3_TOP_LN_STAT_CTRL0_RXVALID_K2_E5_SHIFT                                            0
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2386_K2_E5                                                     0x00c0e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2386_RESERVEDFIELD2935_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2386_RESERVEDFIELD2935_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2386_RESERVEDFIELD2936_K2_E5                                 (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2386_RESERVEDFIELD2936_K2_E5_SHIFT                           1
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2387_K2_E5                                                     0x00c0e8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2387_RESERVEDFIELD2937_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2387_RESERVEDFIELD2937_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN3_TOP_LN_CTRL_OVR0_K2_E5                                                             0x00c0ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_LN_CTRL_OVR0_OVR_EN_K2_E5                                                    (0x1<<0) // override enable for lnX_ctrl_*_i signals in this register
+  #define PHY_NW_IP_REG_LN3_TOP_LN_CTRL_OVR0_OVR_EN_K2_E5_SHIFT                                              0
+  #define PHY_NW_IP_REG_LN3_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_K2_E5                                             (0x7<<1) // lnX_data_width_i override value for TX.  It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-quarter width 10b, others, reserved.
+  #define PHY_NW_IP_REG_LN3_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_K2_E5_SHIFT                                       1
+  #define PHY_NW_IP_REG_LN3_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_K2_E5                                             (0x7<<4) // lnX_data_width_i override value for RX.  It takes effect when ovr_en is 1.
+  #define PHY_NW_IP_REG_LN3_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_K2_E5_SHIFT                                       4
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2388_K2_E5                                                     0x00c0f0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2388_RESERVEDFIELD2938_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2388_RESERVEDFIELD2938_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2388_RESERVEDFIELD2939_K2_E5                                 (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2388_RESERVEDFIELD2939_K2_E5_SHIFT                           3
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2388_RESERVEDFIELD2940_K2_E5                                 (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2388_RESERVEDFIELD2940_K2_E5_SHIFT                           4
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2388_RESERVEDFIELD2941_K2_E5                                 (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2388_RESERVEDFIELD2941_K2_E5_SHIFT                           5
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2389_K2_E5                                                     0x00c0f4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2389_RESERVEDFIELD2942_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2389_RESERVEDFIELD2942_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2389_RESERVEDFIELD2943_K2_E5                                 (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2389_RESERVEDFIELD2943_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2390_K2_E5                                                     0x00c0f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2390_RESERVEDFIELD2944_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2390_RESERVEDFIELD2944_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2390_RESERVEDFIELD2945_K2_E5                                 (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2390_RESERVEDFIELD2945_K2_E5_SHIFT                           5
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2390_RESERVEDFIELD2946_K2_E5                                 (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2390_RESERVEDFIELD2946_K2_E5_SHIFT                           6
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2391_K2_E5                                                     0x00c0fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2391_RESERVEDFIELD2947_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2391_RESERVEDFIELD2947_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2391_RESERVEDFIELD2948_K2_E5                                 (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2391_RESERVEDFIELD2948_K2_E5_SHIFT                           1
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2391_RESERVEDFIELD2949_K2_E5                                 (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2391_RESERVEDFIELD2949_K2_E5_SHIFT                           3
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2392_K2_E5                                                     0x00c100UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2392_RESERVEDFIELD2950_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2392_RESERVEDFIELD2950_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2392_RESERVEDFIELD2951_K2_E5                                 (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2392_RESERVEDFIELD2951_K2_E5_SHIFT                           1
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2392_RESERVEDFIELD2952_K2_E5                                 (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2392_RESERVEDFIELD2952_K2_E5_SHIFT                           2
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2393_K2_E5                                                     0x00c108UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2393_RESERVEDFIELD2953_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2393_RESERVEDFIELD2953_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2393_RESERVEDFIELD2954_K2_E5                                 (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2393_RESERVEDFIELD2954_K2_E5_SHIFT                           1
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2394_K2_E5                                                     0x00c10cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2394_RESERVEDFIELD2955_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2394_RESERVEDFIELD2955_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2394_RESERVEDFIELD2956_K2_E5                                 (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2394_RESERVEDFIELD2956_K2_E5_SHIFT                           1
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2395_K2_E5                                                     0x00c120UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2395_RESERVEDFIELD2957_K2_E5                                 (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2395_RESERVEDFIELD2957_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2395_RESERVEDFIELD2958_K2_E5                                 (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2395_RESERVEDFIELD2958_K2_E5_SHIFT                           3
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2395_RESERVEDFIELD2959_K2_E5                                 (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2395_RESERVEDFIELD2959_K2_E5_SHIFT                           6
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2395_RESERVEDFIELD2960_K2_E5                                 (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2395_RESERVEDFIELD2960_K2_E5_SHIFT                           7
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2396_K2_E5                                                     0x00c124UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2396_RESERVEDFIELD2961_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2396_RESERVEDFIELD2961_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2396_RESERVEDFIELD2962_K2_E5                                 (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2396_RESERVEDFIELD2962_K2_E5_SHIFT                           1
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2396_RESERVEDFIELD2963_K2_E5                                 (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2396_RESERVEDFIELD2963_K2_E5_SHIFT                           2
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2396_RESERVEDFIELD2964_K2_E5                                 (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2396_RESERVEDFIELD2964_K2_E5_SHIFT                           4
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2396_RESERVEDFIELD2965_K2_E5                                 (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2396_RESERVEDFIELD2965_K2_E5_SHIFT                           5
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2396_RESERVEDFIELD2966_K2_E5                                 (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2396_RESERVEDFIELD2966_K2_E5_SHIFT                           6
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2397_K2_E5                                                     0x00c128UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2397_RESERVEDFIELD2967_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2397_RESERVEDFIELD2967_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2398_K2_E5                                                     0x00c12cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2398_RESERVEDFIELD2968_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2398_RESERVEDFIELD2968_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2399_K2_E5                                                     0x00c130UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2399_RESERVEDFIELD2969_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2399_RESERVEDFIELD2969_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2399_RESERVEDFIELD2970_K2_E5                                 (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2399_RESERVEDFIELD2970_K2_E5_SHIFT                           1
+#define PHY_NW_IP_REG_LN3_TOP_ERR_CTRL1_K2_E5                                                                0x00c140UL //Access:RW   DataWidth:0x8    // lower 8-bits of 16-bit lane error code.  0x0 - indicates that there is no error rest - reserved
+#define PHY_NW_IP_REG_LN3_TOP_ERR_CTRL2_K2_E5                                                                0x00c144UL //Access:RW   DataWidth:0x8    // higher 8-bits of 16-bit lane error code.  0x0 - indicates that there is no error rest - reserved
+#define PHY_NW_IP_REG_LN3_TOP_ERR_CTRL3_K2_E5                                                                0x00c148UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_TOP_ERR_CTRL3_LANE_ERR_K2_E5                                                     (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macro has an internal error detected by firmware. Lane error code can be used to isolate error event.
+  #define PHY_NW_IP_REG_LN3_TOP_ERR_CTRL3_LANE_ERR_K2_E5_SHIFT                                               0
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2400_K2_E5                                               0x00c240UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2400_RESERVEDFIELD2971_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2400_RESERVEDFIELD2971_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2401_K2_E5                                               0x00c244UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2401_RESERVEDFIELD2972_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2401_RESERVEDFIELD2972_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2402_K2_E5                                               0x00c284UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2402_RESERVEDFIELD2973_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2402_RESERVEDFIELD2973_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2402_RESERVEDFIELD2974_K2_E5                           (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2402_RESERVEDFIELD2974_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2403_K2_E5                                               0x00c288UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2403_RESERVEDFIELD2975_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2403_RESERVEDFIELD2975_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2404_K2_E5                                               0x00c298UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2405_K2_E5                                               0x00c29cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2405_RESERVEDFIELD2977_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2405_RESERVEDFIELD2977_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2406_K2_E5                                               0x00c2a0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2407_K2_E5                                               0x00c2a4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2407_RESERVEDFIELD2979_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2407_RESERVEDFIELD2979_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2408_K2_E5                                               0x00c2a8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2409_K2_E5                                               0x00c2acUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2409_RESERVEDFIELD2981_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2409_RESERVEDFIELD2981_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2410_K2_E5                                               0x00c2b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2410_RESERVEDFIELD2982_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2410_RESERVEDFIELD2982_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2411_K2_E5                                               0x00c2c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2411_RESERVEDFIELD2983_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2411_RESERVEDFIELD2983_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2412_K2_E5                                               0x00c2c4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2413_K2_E5                                               0x00c2c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2413_RESERVEDFIELD2985_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2413_RESERVEDFIELD2985_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2414_K2_E5                                               0x00c2d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2414_RESERVEDFIELD2986_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2414_RESERVEDFIELD2986_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2415_K2_E5                                               0x00c2d8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2416_K2_E5                                               0x00c2dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2416_RESERVEDFIELD2988_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2416_RESERVEDFIELD2988_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2417_K2_E5                                               0x00c2e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2417_RESERVEDFIELD2989_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2417_RESERVEDFIELD2989_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2418_K2_E5                                               0x00c2e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2418_RESERVEDFIELD2990_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2418_RESERVEDFIELD2990_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2418_RESERVEDFIELD2991_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2418_RESERVEDFIELD2991_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2418_RESERVEDFIELD2992_K2_E5                           (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2418_RESERVEDFIELD2992_K2_E5_SHIFT                     2
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2418_RESERVEDFIELD2993_K2_E5                           (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2418_RESERVEDFIELD2993_K2_E5_SHIFT                     3
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2419_K2_E5                                               0x00c2ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2419_RESERVEDFIELD2994_K2_E5                           (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2419_RESERVEDFIELD2994_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2420_K2_E5                                               0x00c2f0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2420_RESERVEDFIELD2995_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2420_RESERVEDFIELD2995_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2421_K2_E5                                               0x00c2f4UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2422_K2_E5                                               0x00c2f8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2422_RESERVEDFIELD2997_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2422_RESERVEDFIELD2997_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS2_K2_E5                                                       0x00c2fcUL //Access:R    DataWidth:0x8    // Binary-coded DLPF control input to the CDR
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS3_K2_E5                                                       0x00c300UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8_K2_E5                                        (0x1<<0) // Binary-coded DLPF control input to the CDR
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8_K2_E5_SHIFT                                  0
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS4_K2_E5                                                       0x00c304UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH_K2_E5                                       (0x1<<0) // Indicates that DLPF control input to CDR is too high
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW_K2_E5                                        (0x1<<1) // Indicates that DLPF control input to CDR is too low
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW_K2_E5_SHIFT                                  1
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST_K2_E5                                           (0x1<<2) // CDR loss of lock indicator.  1 means lock has been lost. Once lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by setting set lock_en_i to 0.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST_K2_E5_SHIFT                                     2
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS5_K2_E5                                                       0x00c310UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS5_LOCKED_K2_E5                                              (0x1<<0) // CDR lock indicator.  1 means lock is achieved. It is cleared when lock detector is disabled by setting set lock_en_i to 0.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS5_LOCKED_K2_E5_SHIFT                                        0
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_INTEGRAL_STATUS0_K2_E5                                                   0x00c314UL //Access:R    DataWidth:0x8    // Value of the accumulator in the CDR integral path
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_INTEGRAL_STATUS1_K2_E5                                                   0x00c318UL //Access:R    DataWidth:0x8    // Value of the accumulator in the CDR integral path
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_INTEGRAL_STATUS2_K2_E5                                                   0x00c320UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_INTEGRAL_STATUS2_ACCUMULATOR_19_16_K2_E5                               (0xf<<0) // Value of the accumulator in the CDR integral path
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_INTEGRAL_STATUS2_ACCUMULATOR_19_16_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2423_K2_E5                                               0x00c324UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2423_RESERVEDFIELD2998_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2423_RESERVEDFIELD2998_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2423_RESERVEDFIELD2999_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2423_RESERVEDFIELD2999_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2424_K2_E5                                               0x00c328UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2425_K2_E5                                               0x00c32cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2426_K2_E5                                               0x00c330UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2427_K2_E5                                               0x00c334UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2427_RESERVEDFIELD3003_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2427_RESERVEDFIELD3003_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2427_RESERVEDFIELD3004_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2427_RESERVEDFIELD3004_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2428_K2_E5                                               0x00c338UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2429_K2_E5                                               0x00c33cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2430_K2_E5                                               0x00c380UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2431_K2_E5                                               0x00c384UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2431_RESERVEDFIELD3008_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2431_RESERVEDFIELD3008_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2432_K2_E5                                               0x00c388UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2432_RESERVEDFIELD3009_K2_E5                           (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2432_RESERVEDFIELD3009_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2432_RESERVEDFIELD3010_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2432_RESERVEDFIELD3010_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2433_K2_E5                                               0x00c38cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2434_K2_E5                                               0x00c3a0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2435_K2_E5                                               0x00c3a4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2435_RESERVEDFIELD3013_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2435_RESERVEDFIELD3013_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2435_RESERVEDFIELD3014_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2435_RESERVEDFIELD3014_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2435_RESERVEDFIELD3015_K2_E5                           (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2435_RESERVEDFIELD3015_K2_E5_SHIFT                     2
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2436_K2_E5                                               0x00c3a8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2437_K2_E5                                               0x00c3acUL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2438_K2_E5                                               0x00c3b0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2438_RESERVEDFIELD3018_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2438_RESERVEDFIELD3018_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2439_K2_E5                                               0x00c3b4UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2440_K2_E5                                               0x00c3b8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2441_K2_E5                                               0x00c3bcUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2441_RESERVEDFIELD3021_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2441_RESERVEDFIELD3021_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2442_K2_E5                                               0x00c3c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2442_RESERVEDFIELD3022_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2442_RESERVEDFIELD3022_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2443_K2_E5                                              0x00c400UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2443_RESERVEDFIELD3023_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2443_RESERVEDFIELD3023_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2443_RESERVEDFIELD3024_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2443_RESERVEDFIELD3024_K2_E5_SHIFT                    3
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2443_RESERVEDFIELD3025_K2_E5                          (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2443_RESERVEDFIELD3025_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2444_K2_E5                                              0x00c404UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2444_RESERVEDFIELD3026_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2444_RESERVEDFIELD3026_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2445_K2_E5                                              0x00c410UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2445_RESERVEDFIELD3027_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2445_RESERVEDFIELD3027_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2446_K2_E5                                              0x00c418UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2447_K2_E5                                              0x00c428UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2447_RESERVEDFIELD3029_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2447_RESERVEDFIELD3029_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2448_K2_E5                                              0x00c42cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2448_RESERVEDFIELD3030_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2448_RESERVEDFIELD3030_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2448_RESERVEDFIELD3031_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2448_RESERVEDFIELD3031_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2448_RESERVEDFIELD3032_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2448_RESERVEDFIELD3032_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2449_K2_E5                                              0x00c430UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2449_RESERVEDFIELD3033_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2449_RESERVEDFIELD3033_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2450_K2_E5                                              0x00c440UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2450_RESERVEDFIELD3034_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2450_RESERVEDFIELD3034_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2450_RESERVEDFIELD3035_K2_E5                          (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2450_RESERVEDFIELD3035_K2_E5_SHIFT                    5
+#define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2451_K2_E5                                              0x00c444UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2451_RESERVEDFIELD3036_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2451_RESERVEDFIELD3036_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2451_RESERVEDFIELD3037_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2451_RESERVEDFIELD3037_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2451_RESERVEDFIELD3038_K2_E5                          (0xf<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2451_RESERVEDFIELD3038_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2452_K2_E5                                              0x00c460UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2452_RESERVEDFIELD3039_K2_E5                          (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2452_RESERVEDFIELD3039_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2452_RESERVEDFIELD3040_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2452_RESERVEDFIELD3040_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2453_K2_E5                                              0x00c464UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2453_RESERVEDFIELD3041_K2_E5                          (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2453_RESERVEDFIELD3041_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2453_RESERVEDFIELD3042_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2453_RESERVEDFIELD3042_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2454_K2_E5                                              0x00c468UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2454_RESERVEDFIELD3043_K2_E5                          (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2454_RESERVEDFIELD3043_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2455_K2_E5                                              0x00c46cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2455_RESERVEDFIELD3044_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2455_RESERVEDFIELD3044_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2455_RESERVEDFIELD3045_K2_E5                          (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2455_RESERVEDFIELD3045_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2456_K2_E5                                              0x00c480UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2456_RESERVEDFIELD3046_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2456_RESERVEDFIELD3046_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2456_RESERVEDFIELD3047_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2456_RESERVEDFIELD3047_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2457_K2_E5                                              0x00c484UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2457_RESERVEDFIELD3048_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2457_RESERVEDFIELD3048_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2458_K2_E5                                              0x00c488UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2459_K2_E5                                              0x00c48cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2460_K2_E5                                              0x00c490UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2461_K2_E5                                              0x00c494UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2461_RESERVEDFIELD3052_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2461_RESERVEDFIELD3052_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2462_K2_E5                                              0x00c4c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2462_RESERVEDFIELD3053_K2_E5                          (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2462_RESERVEDFIELD3053_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2463_K2_E5                                                    0x00c600UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2463_RESERVEDFIELD3054_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2463_RESERVEDFIELD3054_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2463_RESERVEDFIELD3055_K2_E5                                (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2463_RESERVEDFIELD3055_K2_E5_SHIFT                          1
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2464_K2_E5                                                    0x00c604UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2465_K2_E5                                                    0x00c608UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2466_K2_E5                                                    0x00c60cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2466_RESERVEDFIELD3058_K2_E5                                (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2466_RESERVEDFIELD3058_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2466_RESERVEDFIELD3059_K2_E5                                (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2466_RESERVEDFIELD3059_K2_E5_SHIFT                          4
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2467_K2_E5                                                    0x00c610UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2468_K2_E5                                                    0x00c614UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2468_RESERVEDFIELD3061_K2_E5                                (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2468_RESERVEDFIELD3061_K2_E5_SHIFT                          0
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2469_K2_E5                                                    0x00c618UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2469_RESERVEDFIELD3062_K2_E5                                (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2469_RESERVEDFIELD3062_K2_E5_SHIFT                          0
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2470_K2_E5                                                    0x00c61cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2470_RESERVEDFIELD3063_K2_E5                                (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2470_RESERVEDFIELD3063_K2_E5_SHIFT                          0
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2471_K2_E5                                                    0x00c620UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2472_K2_E5                                                    0x00c624UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2472_RESERVEDFIELD3065_K2_E5                                (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2472_RESERVEDFIELD3065_K2_E5_SHIFT                          0
+#define PHY_NW_IP_REG_LN3_ANEG_CFG10_K2_E5                                                                   0x00c628UL //Access:RW   DataWidth:0x8    // Seed provided to the transmit nonce generator polynomial
+#define PHY_NW_IP_REG_LN3_ANEG_CFG11_K2_E5                                                                   0x00c62cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_CFG11_PSEUDO_SEL_K2_E5                                                      (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
+  #define PHY_NW_IP_REG_LN3_ANEG_CFG11_PSEUDO_SEL_K2_E5_SHIFT                                                0
+#define PHY_NW_IP_REG_LN3_ANEG_CTRL0_K2_E5                                                                   0x00c630UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_CTRL0_AUTONEG_RESTART_K2_E5                                                 (0x1<<0) // Restarts AN that is already in progress or otherwise completed.  Reset is triggered by rising edge of this signal.  Not self clearing.
+  #define PHY_NW_IP_REG_LN3_ANEG_CTRL0_AUTONEG_RESTART_K2_E5_SHIFT                                           0
+  #define PHY_NW_IP_REG_LN3_ANEG_CTRL0_RESERVEDFIELD3066_K2_E5                                               (0x7f<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_CTRL0_RESERVEDFIELD3066_K2_E5_SHIFT                                         1
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2473_K2_E5                                                    0x00c634UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2473_RESERVEDFIELD3067_K2_E5                                (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2473_RESERVEDFIELD3067_K2_E5_SHIFT                          4
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2473_RESERVEDFIELD3068_K2_E5                                (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2473_RESERVEDFIELD3068_K2_E5_SHIFT                          5
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2473_RESERVEDFIELD3069_K2_E5                                (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2473_RESERVEDFIELD3069_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2474_K2_E5                                                    0x00c638UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2474_RESERVEDFIELD3070_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2474_RESERVEDFIELD3070_K2_E5_SHIFT                          0
+#define PHY_NW_IP_REG_LN3_ANEG_STATUS0_K2_E5                                                                 0x00c640UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_LP_AUTONEG_ABLE_K2_E5                                               (0x1<<0) // The link partner Auto-Negotiation ability bit shall be set to one to indicate that the link partner is able to participate in the Auto-Negotiation function. This bit shall be reset to zero if the link partner is not Auto- Negotiation able.
+  #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_LP_AUTONEG_ABLE_K2_E5_SHIFT                                         0
+  #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_LINK_STATUS_K2_E5                                                   (0x1<<2) // Local link Status.  When read as a one, it indicates that the PMA/PMD has determined that a valid link has been established i.e. link_status[HDC] equals OK. When read as a zero, it indicates that the link is not valid.
+  #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_LINK_STATUS_K2_E5_SHIFT                                             2
+  #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_AUTONEG_ABILITY_K2_E5                                               (0x1<<3) // Autoneg ability.  When read as a one, it indicates that the PMA/PMD has the ability to perform Auto-Negotiation.  When read as a zero, it indicates that the PMA/PMD lacks the ability to perform Auto-Negotiation.
+  #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_AUTONEG_ABILITY_K2_E5_SHIFT                                         3
+  #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_AUTONEG_REMOTE_FAULT_K2_E5                                          (0x1<<4) // Remote Fault
+  #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_AUTONEG_REMOTE_FAULT_K2_E5_SHIFT                                    4
+  #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_AUTONEG_COMPLETE_K2_E5                                              (0x1<<5) // Autoneg has completed and autoneg arbitration FSM is in AN GOOD state.
+  #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_AUTONEG_COMPLETE_K2_E5_SHIFT                                        5
+#define PHY_NW_IP_REG_LN3_ANEG_STATUS1_K2_E5                                                                 0x00c644UL //Access:W    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_PAGE_RX_K2_E5                                                       (0x1<<0) // Page Received.   To clear it, write 1 to it.
+  #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_PAGE_RX_K2_E5_SHIFT                                                 0
+  #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_AN_LINK_GOOD_K2_E5                                                  (0x1<<1) // Autoneg has completed and autoneg arbitration FSM is in either AN GOOD CHECK or AN GOOD state.
+  #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_AN_LINK_GOOD_K2_E5_SHIFT                                            1
+  #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_PARALLEL_DET_FAULT_K2_E5                                            (0x1<<2) // Autoneg Parallel Detection Fault.  Write 1 to clear it.
+  #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_PARALLEL_DET_FAULT_K2_E5_SHIFT                                      2
+  #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_NP_LOADED_K2_E5                                                     (0x1<<3) // mr_np_loaded status.
+  #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_NP_LOADED_K2_E5_SHIFT                                               3
+  #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_RESERVEDFIELD3071_K2_E5                                             (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_RESERVEDFIELD3071_K2_E5_SHIFT                                       4
+  #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_RESERVEDFIELD3072_K2_E5                                             (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_RESERVEDFIELD3072_K2_E5_SHIFT                                       5
+#define PHY_NW_IP_REG_LN3_ANEG_STATUS_DBG0_K2_E5                                                             0x00c650UL //Access:R    DataWidth:0x8    // One-hot sticky capture of AN FSM states.  Bits 7-0
+#define PHY_NW_IP_REG_LN3_ANEG_STATUS_DBG1_K2_E5                                                             0x00c654UL //Access:R    DataWidth:0x8    // One-hot sticky capture of AN FSM states.  Bits 15-8
+#define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE0_K2_E5                                                              0x00c660UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE0_SELECTOR_K2_E5                                                   (0x1f<<0) // technology Select Field
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE0_SELECTOR_K2_E5_SHIFT                                             0
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE0_ECHOED_NONCE_2_0_K2_E5                                           (0x7<<5) // Echoed Nonce Field bits 2-0.  AN controller generates it.
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE0_ECHOED_NONCE_2_0_K2_E5_SHIFT                                     5
+#define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_K2_E5                                                              0x00c664UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_ECHOED_NONCE_4_3_K2_E5                                           (0x3<<0) // Echoed Nonce Field bits 4-3.    AN controller generates it.
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_ECHOED_NONCE_4_3_K2_E5_SHIFT                                     0
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_PAUSE_K2_E5                                                      (0x1<<2) // Pause advertised ability
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_PAUSE_K2_E5_SHIFT                                                2
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_ASM_DIR_K2_E5                                                    (0x1<<3) // Pause ASM_DIR advertised ability
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_ASM_DIR_K2_E5_SHIFT                                              3
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_C2_K2_E5                                                         (0x1<<4) // Reserved always 0
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_C2_K2_E5_SHIFT                                                   4
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_REMOTE_FAULT_K2_E5                                               (0x1<<5) // Remote Fault Local Device
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_REMOTE_FAULT_K2_E5_SHIFT                                         5
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_NEXT_PAGE_K2_E5                                                  (0x1<<7) // Next Page
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_NEXT_PAGE_K2_E5_SHIFT                                            7
+#define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE2_K2_E5                                                              0x00c668UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE2_TX_NONCE_K2_E5                                                   (0x1f<<0) // Transmitted Nonce Field.  It is generated in hardware.
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE2_TX_NONCE_K2_E5_SHIFT                                             0
+#define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_K2_E5                                                         0x00c66cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_1G_KX_K2_E5                                         (0x1<<0) // 1000Base-KX technology advertised ability
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_1G_KX_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KX4_K2_E5                                       (0x1<<1) // 10GBase-KX4 technology advertised ability
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KX4_K2_E5_SHIFT                                 1
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KR_K2_E5                                        (0x1<<2) // 10GBase-KR technology advertised ability
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KR_K2_E5_SHIFT                                  2
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_40G_KR4_K2_E5                                       (0x1<<3) // 40GBase-KR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_40G_KR4_K2_E5_SHIFT                                 3
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_40G_CR4_K2_E5                                       (0x1<<4) // 40GBase-CR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_40G_CR4_K2_E5_SHIFT                                 4
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_100G_CR10_K2_E5                                     (0x1<<5) // 100GBase-CR10 technology advertised ability
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_100G_CR10_K2_E5_SHIFT                               5
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KP4_K2_E5                                      (0x1<<6) // 100GBase-KP4 technology advertised ability
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KP4_K2_E5_SHIFT                                6
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KR4_K2_E5                                      (0x1<<7) // 100GBase-KR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KR4_K2_E5_SHIFT                                7
+#define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH1_K2_E5                                                         0x00c670UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH1_ABILITY_100G_CR4_K2_E5                                      (0x1<<0) // 100GBase-CR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH1_ABILITY_100G_CR4_K2_E5_SHIFT                                0
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_S_K2_E5                                      (0x1<<1) // 25GBase-GR-S KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A9 in base page.
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_S_K2_E5_SHIFT                                1
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_K2_E5                                        (0x1<<2) // 25GBase-GR KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A10 in base page.
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_K2_E5_SHIFT                                  2
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH1_ABILITY_A15_A11_K2_E5                                       (0x1f<<3) // technology advertised ability Field A15-A11
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH1_ABILITY_A15_A11_K2_E5_SHIFT                                 3
+#define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH2_K2_E5                                                         0x00c674UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH2_ABILITY_A22_A16_K2_E5                                       (0x7f<<0) // technology advertised ability Field A22-A16
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH2_ABILITY_A22_A16_K2_E5_SHIFT                                 0
+#define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_K2_E5                                                           0x00c678UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_FEC_ABILITY_K2_E5                                             (0x1<<0) // base page bit F0.  It advertises FEC ability
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_FEC_ABILITY_K2_E5_SHIFT                                       0
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_FEC_REQ_K2_E5                                                 (0x1<<1) // base page bit F1.  It requests FEC to be turned on when supported at the both ends of link
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_FEC_REQ_K2_E5_SHIFT                                           1
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_RS_FEC_REQ_25G_K2_E5                                          (0x1<<2) // base page bit F2.  It requests RS-FEC for 25G-GR 25G-KR/-CR link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A23 in base page.
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_RS_FEC_REQ_25G_K2_E5_SHIFT                                    2
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_FC_FEC_REQ_25G_K2_E5                                          (0x1<<3) // base page bit F3.  It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A24 in base page.
+  #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_FC_FEC_REQ_25G_K2_E5_SHIFT                                    3
+#define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_K2_E5                                                               0x00c67cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_ABILITY_25G_KR_K2_E5                                              (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_ABILITY_25G_KR_K2_E5_SHIFT                                        0
+  #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_ABILITY_25G_CR_K2_E5                                              (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_ABILITY_25G_CR_K2_E5_SHIFT                                        1
+  #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_ABILITY_50G_KR2_K2_E5                                             (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_ABILITY_50G_KR2_K2_E5_SHIFT                                       2
+  #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_ABILITY_50G_CR2_K2_E5                                             (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_ABILITY_50G_CR2_K2_E5_SHIFT                                       3
+  #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_RS_FEC_ABILITY_K2_E5                                              (0x1<<4) // Extended advertised FEC field 0.  It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_RS_FEC_ABILITY_K2_E5_SHIFT                                        4
+  #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_FC_FEC_ABILITY_K2_E5                                              (0x1<<5) // Extended advertised FEC field 1.  It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_FC_FEC_ABILITY_K2_E5_SHIFT                                        5
+  #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_RS_FEC_REQ_K2_E5                                                  (0x1<<6) // Extended advertised FEC field 2.  It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_RS_FEC_REQ_K2_E5_SHIFT                                            6
+  #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_FC_FEC_REQ_K2_E5                                                  (0x1<<7) // Extended advertised FEC field 3.  It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_FC_FEC_REQ_K2_E5_SHIFT                                            7
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2475_K2_E5                                                    0x00c680UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2476_K2_E5                                                    0x00c684UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2476_RESERVEDFIELD3073_K2_E5                                (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2476_RESERVEDFIELD3073_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2476_RESERVEDFIELD3074_K2_E5                                (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2476_RESERVEDFIELD3074_K2_E5_SHIFT                          3
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2476_RESERVEDFIELD3075_K2_E5                                (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2476_RESERVEDFIELD3075_K2_E5_SHIFT                          4
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2476_RESERVEDFIELD3076_K2_E5                                (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2476_RESERVEDFIELD3076_K2_E5_SHIFT                          5
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2476_RESERVEDFIELD3077_K2_E5                                (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2476_RESERVEDFIELD3077_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2477_K2_E5                                                    0x00c688UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2478_K2_E5                                                    0x00c68cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2479_K2_E5                                                    0x00c690UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2480_K2_E5                                                    0x00c694UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_K2_E5                                                    0x00c698UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3078_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3078_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3079_K2_E5                                (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3079_K2_E5_SHIFT                          1
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3080_K2_E5                                (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3080_K2_E5_SHIFT                          2
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3081_K2_E5                                (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3081_K2_E5_SHIFT                          3
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3082_K2_E5                                (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3082_K2_E5_SHIFT                          4
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3083_K2_E5                                (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3083_K2_E5_SHIFT                          5
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3084_K2_E5                                (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3084_K2_E5_SHIFT                          6
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3085_K2_E5                                (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3085_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2482_K2_E5                                                    0x00c69cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2482_RESERVEDFIELD3086_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2482_RESERVEDFIELD3086_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2482_RESERVEDFIELD3087_K2_E5                                (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2482_RESERVEDFIELD3087_K2_E5_SHIFT                          1
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2482_RESERVEDFIELD3088_K2_E5                                (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2482_RESERVEDFIELD3088_K2_E5_SHIFT                          2
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2482_RESERVEDFIELD3089_K2_E5                                (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2482_RESERVEDFIELD3089_K2_E5_SHIFT                          3
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2482_RESERVEDFIELD3090_K2_E5                                (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2482_RESERVEDFIELD3090_K2_E5_SHIFT                          4
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2482_RESERVEDFIELD3091_K2_E5                                (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2482_RESERVEDFIELD3091_K2_E5_SHIFT                          5
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2482_RESERVEDFIELD3092_K2_E5                                (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2482_RESERVEDFIELD3092_K2_E5_SHIFT                          6
+#define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE0_K2_E5                                                           0x00c6a0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE0_SELECTOR_K2_E5                                                (0x1f<<0) // Link partner technology Select Field
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE0_SELECTOR_K2_E5_SHIFT                                          0
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE0_ECHOED_NONCE_2_0_K2_E5                                        (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE0_ECHOED_NONCE_2_0_K2_E5_SHIFT                                  5
+#define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_K2_E5                                                           0x00c6a4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_ECHOED_NONCE_4_3_K2_E5                                        (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_ECHOED_NONCE_4_3_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_PAUSE_K2_E5                                                   (0x1<<2) // Link partner Pause advertised ability
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_PAUSE_K2_E5_SHIFT                                             2
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_ASM_DIR_K2_E5                                                 (0x1<<3) // Link partner Pause ASM_DIR advertised ability
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_ASM_DIR_K2_E5_SHIFT                                           3
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_C2_K2_E5                                                      (0x1<<4) // Link partner C2 field always 0
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_C2_K2_E5_SHIFT                                                4
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_REMOTE_FAULT_K2_E5                                            (0x1<<5) // Link partner Remote Fault
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_REMOTE_FAULT_K2_E5_SHIFT                                      5
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_ACK_K2_E5                                                     (0x1<<6) // Link partner Acknowledge always 0
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_ACK_K2_E5_SHIFT                                               6
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_NEXT_PAGE_K2_E5                                               (0x1<<7) // Link partner Next Page
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_NEXT_PAGE_K2_E5_SHIFT                                         7
+#define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE2_K2_E5                                                           0x00c6a8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE2_TX_NONCE_K2_E5                                                (0x1f<<0) // Transmitted Nonce Field from Link partner
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE2_TX_NONCE_K2_E5_SHIFT                                          0
+#define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_K2_E5                                                      0x00c6acUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_1G_KX_K2_E5                                      (0x1<<0) // Link partner 1000Base-KX technology advertised ability
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_1G_KX_K2_E5_SHIFT                                0
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KX4_K2_E5                                    (0x1<<1) // Link partner 10GBase-KX4 technology advertised ability
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KX4_K2_E5_SHIFT                              1
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KR_K2_E5                                     (0x1<<2) // Link partner 10GBase-KR technology advertised ability
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KR_K2_E5_SHIFT                               2
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_KR4_K2_E5                                    (0x1<<3) // Link partner 40GBase-KR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_KR4_K2_E5_SHIFT                              3
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_CR4_K2_E5                                    (0x1<<4) // Link partner 40GBase-CR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_CR4_K2_E5_SHIFT                              4
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_CR10_K2_E5                                  (0x1<<5) // Link partner 100GBase-CR10 technology advertised ability
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_CR10_K2_E5_SHIFT                            5
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KP4_K2_E5                                   (0x1<<6) // Link partner 100GBase-KP4 technology advertised ability
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KP4_K2_E5_SHIFT                             6
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KR4_K2_E5                                   (0x1<<7) // Link partner 100GBase-KR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KR4_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH1_K2_E5                                                      0x00c6b0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH1_ABILITY_100G_CR4_K2_E5                                   (0x1<<0) // Link partner 100GBase-CR4 technology advertised ability
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH1_ABILITY_100G_CR4_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_S_K2_E5                                   (0x1<<1) // Link partner 25GBase-GR-S KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A9 in base page.
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_S_K2_E5_SHIFT                             1
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_K2_E5                                     (0x1<<2) // Link partner 25GBase-GR KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A10 in base page.
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_K2_E5_SHIFT                               2
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH1_ABILITY_A15_A11_K2_E5                                    (0x1f<<3) // Link partner technology advertised ability Field A15-A11
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH1_ABILITY_A15_A11_K2_E5_SHIFT                              3
+#define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH2_K2_E5                                                      0x00c6b4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH2_ABILITY_A22_A16_K2_E5                                    (0x7f<<0) // Link partner technology advertised ability Field A22-A16
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH2_ABILITY_A22_A16_K2_E5_SHIFT                              0
+#define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_K2_E5                                                        0x00c6b8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_FEC_ABILITY_K2_E5                                          (0x1<<0) // Link partner base page bit F0.  It advertises FEC ability
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_FEC_ABILITY_K2_E5_SHIFT                                    0
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_FEC_REQ_K2_E5                                              (0x1<<1) // Link partner base page bit F1.  It requests FEC to be turned on when supported at the both ends of link
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_FEC_REQ_K2_E5_SHIFT                                        1
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_RS_FEC_REQ_25G_K2_E5                                       (0x1<<2) // Link partner base page bit F2.  It requests RS-FEC for 25G-GR 25G-KR/-CR link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A23 in base page.
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_RS_FEC_REQ_25G_K2_E5_SHIFT                                 2
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_FC_FEC_REQ_25G_K2_E5                                       (0x1<<3) // Link partner base page bit F3.  It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A24 in base page.
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_FC_FEC_REQ_25G_K2_E5_SHIFT                                 3
+#define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_K2_E5                                                            0x00c6bcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_ABILITY_25G_KR_K2_E5                                           (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_ABILITY_25G_KR_K2_E5_SHIFT                                     0
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_ABILITY_25G_CR_K2_E5                                           (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_ABILITY_25G_CR_K2_E5_SHIFT                                     1
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_ABILITY_50G_KR2_K2_E5                                          (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_ABILITY_50G_KR2_K2_E5_SHIFT                                    2
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_ABILITY_50G_CR2_K2_E5                                          (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_ABILITY_50G_CR2_K2_E5_SHIFT                                    3
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_RS_FEC_ABILITY_K2_E5                                           (0x1<<4) // Link partner extended advertised FEC field 0.  It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_RS_FEC_ABILITY_K2_E5_SHIFT                                     4
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_FC_FEC_ABILITY_K2_E5                                           (0x1<<5) // Link partner extended advertised FEC field 1.  It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_FC_FEC_ABILITY_K2_E5_SHIFT                                     5
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_RS_FEC_REQ_K2_E5                                               (0x1<<6) // Link partner extended advertised FEC field 2.  It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_RS_FEC_REQ_K2_E5_SHIFT                                         6
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_FC_FEC_REQ_K2_E5                                               (0x1<<7) // Link partner extended advertised FEC field 3.  It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
+  #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_FC_FEC_REQ_K2_E5_SHIFT                                         7
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2483_K2_E5                                                    0x00c6c0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2484_K2_E5                                                    0x00c6c4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2484_RESERVEDFIELD3093_K2_E5                                (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2484_RESERVEDFIELD3093_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2484_RESERVEDFIELD3094_K2_E5                                (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2484_RESERVEDFIELD3094_K2_E5_SHIFT                          3
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2484_RESERVEDFIELD3095_K2_E5                                (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2484_RESERVEDFIELD3095_K2_E5_SHIFT                          4
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2484_RESERVEDFIELD3096_K2_E5                                (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2484_RESERVEDFIELD3096_K2_E5_SHIFT                          5
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2484_RESERVEDFIELD3097_K2_E5                                (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2484_RESERVEDFIELD3097_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2485_K2_E5                                                    0x00c6c8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2486_K2_E5                                                    0x00c6ccUL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2487_K2_E5                                                    0x00c6d0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2488_K2_E5                                                    0x00c6d4UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_K2_E5                                                    0x00c6d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3098_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3098_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3099_K2_E5                                (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3099_K2_E5_SHIFT                          1
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3100_K2_E5                                (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3100_K2_E5_SHIFT                          2
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3101_K2_E5                                (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3101_K2_E5_SHIFT                          3
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3102_K2_E5                                (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3102_K2_E5_SHIFT                          4
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3103_K2_E5                                (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3103_K2_E5_SHIFT                          5
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3104_K2_E5                                (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3104_K2_E5_SHIFT                          6
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3105_K2_E5                                (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3105_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2490_K2_E5                                                    0x00c6dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2490_RESERVEDFIELD3106_K2_E5                                (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2490_RESERVEDFIELD3106_K2_E5_SHIFT                          0
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2490_RESERVEDFIELD3107_K2_E5                                (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2490_RESERVEDFIELD3107_K2_E5_SHIFT                          1
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2490_RESERVEDFIELD3108_K2_E5                                (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2490_RESERVEDFIELD3108_K2_E5_SHIFT                          2
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2490_RESERVEDFIELD3109_K2_E5                                (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2490_RESERVEDFIELD3109_K2_E5_SHIFT                          3
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2490_RESERVEDFIELD3110_K2_E5                                (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2490_RESERVEDFIELD3110_K2_E5_SHIFT                          4
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2490_RESERVEDFIELD3111_K2_E5                                (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2490_RESERVEDFIELD3111_K2_E5_SHIFT                          5
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2490_RESERVEDFIELD3112_K2_E5                                (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2490_RESERVEDFIELD3112_K2_E5_SHIFT                          6
+#define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_K2_E5                                                        0x00c6e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_1G_KX_K2_E5                                        (0x1<<0) // Resolution result for 1000Base-KX.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_1G_KX_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_10G_KX4_K2_E5                                      (0x1<<1) // Resolution result for 10GBase-KX4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_10G_KX4_K2_E5_SHIFT                                1
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_10G_KR_K2_E5                                       (0x1<<2) // Resolution result for 10GBase-KR.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_10G_KR_K2_E5_SHIFT                                 2
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_40G_KR4_K2_E5                                      (0x1<<3) // Resolution result for 40GBase-KR4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_40G_KR4_K2_E5_SHIFT                                3
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_40G_CR4_K2_E5                                      (0x1<<4) // Resolution result for 40GBase-CR4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_40G_CR4_K2_E5_SHIFT                                4
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_100G_CR10_K2_E5                                    (0x1<<5) // Resolution result for 100GBase-CR10.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_100G_CR10_K2_E5_SHIFT                              5
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_100G_KP4_K2_E5                                     (0x1<<6) // Resolution result for 100GBase-KP4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_100G_KP4_K2_E5_SHIFT                               6
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_100G_KR4_K2_E5                                     (0x1<<7) // Resolution result for 100GBase-KR4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_100G_KR4_K2_E5_SHIFT                               7
+#define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_K2_E5                                                        0x00c6e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_100G_CR4_K2_E5                                     (0x1<<0) // Resolution result for 100GBase-CR4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_100G_CR4_K2_E5_SHIFT                               0
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_S_K2_E5                                     (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_S_K2_E5_SHIFT                               1
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_K2_E5                                       (0x1<<2) // Resolution result for 25GBase-GR KR or CR.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_K2_E5_SHIFT                                 2
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_25G_KR_K2_E5                                       (0x1<<3) // Resolution result for 25GBase-KR.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_25G_KR_K2_E5_SHIFT                                 3
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_25G_CR_K2_E5                                       (0x1<<4) // Resolution result for 25GBase-CR4.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_25G_CR_K2_E5_SHIFT                                 4
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_50G_KR2_K2_E5                                      (0x1<<5) // Resolution result for 50GBase-KR2.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_50G_KR2_K2_E5_SHIFT                                5
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_50G_CR2_K2_E5                                      (0x1<<6) // Resolution result for 50GBase-CR2.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_50G_CR2_K2_E5_SHIFT                                6
+#define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_FEC_K2_E5                                                          0x00c6e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_FEC_RS_K2_E5                                                     (0x1<<0) // Resolution result for Reed-Solomon FEC.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_FEC_RS_K2_E5_SHIFT                                               0
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_FEC_FC_K2_E5                                                     (0x1<<1) // Resolution result for Firecode base page FEC.  It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_FEC_FC_K2_E5_SHIFT                                               1
+#define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_PAUSE_K2_E5                                                        0x00c6ecUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_PAUSE_RX_K2_E5                                                   (0x1<<0) // Resolution result for RX PAUSE enable.    It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_PAUSE_RX_K2_E5_SHIFT                                             0
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_PAUSE_TX_K2_E5                                                   (0x1<<1) // Resolution result for TX PAUSE enable.    It is valid when status0.an_link_good is 1.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_PAUSE_TX_K2_E5_SHIFT                                             1
+#define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_EEE_K2_E5                                                          0x00c6f0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_EEE_F971_K2_E5                                                   (0x1<<0) // Resolution result for EEE.  It is 1 if both the local device and the link partner advertise the EEE capability for the resolved PHY type.  It is 0 otherwise.  It is valid when status0.an_link_good is 1. Note that it indicates EEE deep sleep capability.
+  #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_EEE_F971_K2_E5_SHIFT                                             0
+#define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_K2_E5                                                            0x00c6f8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_1G_KX_K2_E5                                            (0x1<<0) // link_status for 1000Base-KX
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_1G_KX_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_10G_KX4_K2_E5                                          (0x1<<1) // link_status for 10GBase-KX4
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_10G_KX4_K2_E5_SHIFT                                    1
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_10G_KR_K2_E5                                           (0x1<<2) // link_status for 10GBase-KR
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_10G_KR_K2_E5_SHIFT                                     2
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_40G_KR4_K2_E5                                          (0x1<<3) // link_status for 40GBase-KR4
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_40G_KR4_K2_E5_SHIFT                                    3
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_40G_CR4_K2_E5                                          (0x1<<4) // link_status for 40GBase-CR4
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_40G_CR4_K2_E5_SHIFT                                    4
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_100G_CR10_K2_E5                                        (0x1<<5) // link_status for 100GBase-CR10
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_100G_CR10_K2_E5_SHIFT                                  5
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_100G_KP4_K2_E5                                         (0x1<<6) // link_status for 100GBase-KP4
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_100G_KP4_K2_E5_SHIFT                                   6
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_100G_KR4_K2_E5                                         (0x1<<7) // link_status for 100GBase-KR4
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_100G_KR4_K2_E5_SHIFT                                   7
+#define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_K2_E5                                                            0x00c6fcUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_100G_CR4_K2_E5                                         (0x1<<0) // link_status for 100GBase-CR4
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_100G_CR4_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_25G_GR_K2_E5                                           (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_25G_GR_K2_E5_SHIFT                                     1
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_25G_KR_K2_E5                                           (0x1<<3) // link_status for 25GBase-KR
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_25G_KR_K2_E5_SHIFT                                     3
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_25G_CR_K2_E5                                           (0x1<<4) // link_status for 25GBase-CR4
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_25G_CR_K2_E5_SHIFT                                     4
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_50G_KR2_K2_E5                                          (0x1<<5) // link_status for 50GBase-KR2
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_50G_KR2_K2_E5_SHIFT                                    5
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_50G_CR2_K2_E5                                          (0x1<<6) // link_status for 50GBase-CR2
+  #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_50G_CR2_K2_E5_SHIFT                                    6
+#define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2491_K2_E5                                                     0x00c704UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2491_RESERVEDFIELD3113_K2_E5                                 (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2491_RESERVEDFIELD3113_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2491_RESERVEDFIELD3114_K2_E5                                 (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2491_RESERVEDFIELD3114_K2_E5_SHIFT                           2
+#define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2492_K2_E5                                                     0x00c708UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2492_RESERVEDFIELD3115_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2492_RESERVEDFIELD3115_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2493_K2_E5                                                     0x00c70cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2493_RESERVEDFIELD3116_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2493_RESERVEDFIELD3116_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2494_K2_E5                                                     0x00c714UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2494_RESERVEDFIELD3117_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2494_RESERVEDFIELD3117_K2_E5_SHIFT                           0
+  #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2494_RESERVEDFIELD3118_K2_E5                                 (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2494_RESERVEDFIELD3118_K2_E5_SHIFT                           1
+  #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2494_RESERVEDFIELD3119_K2_E5                                 (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2494_RESERVEDFIELD3119_K2_E5_SHIFT                           3
+  #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2494_RESERVEDFIELD3120_K2_E5                                 (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2494_RESERVEDFIELD3120_K2_E5_SHIFT                           4
+#define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2495_K2_E5                                                     0x00c718UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2495_RESERVEDFIELD3121_K2_E5                                 (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2495_RESERVEDFIELD3121_K2_E5_SHIFT                           0
+#define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2496_K2_E5                                                     0x00c71cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2497_K2_E5                                                     0x00c720UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2498_K2_E5                                              0x00c800UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2498_RESERVEDFIELD3124_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2498_RESERVEDFIELD3124_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2498_RESERVEDFIELD3125_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2498_RESERVEDFIELD3125_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2499_K2_E5                                              0x00c808UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2500_K2_E5                                              0x00c80cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2500_RESERVEDFIELD3127_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2500_RESERVEDFIELD3127_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2500_RESERVEDFIELD3128_K2_E5                          (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2500_RESERVEDFIELD3128_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2501_K2_E5                                              0x00c814UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2501_RESERVEDFIELD3129_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2501_RESERVEDFIELD3129_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2501_RESERVEDFIELD3130_K2_E5                          (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2501_RESERVEDFIELD3130_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2501_RESERVEDFIELD3131_K2_E5                          (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2501_RESERVEDFIELD3131_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2502_K2_E5                                              0x00c81cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2502_RESERVEDFIELD3132_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2502_RESERVEDFIELD3132_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2503_K2_E5                                              0x00c824UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2503_RESERVEDFIELD3133_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2503_RESERVEDFIELD3133_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2504_K2_E5                                              0x00c828UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2504_RESERVEDFIELD3134_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2504_RESERVEDFIELD3134_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2504_RESERVEDFIELD3135_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2504_RESERVEDFIELD3135_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2505_K2_E5                                              0x00c82cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2505_RESERVEDFIELD3136_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2505_RESERVEDFIELD3136_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2505_RESERVEDFIELD3137_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2505_RESERVEDFIELD3137_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2506_K2_E5                                              0x00c830UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2506_RESERVEDFIELD3138_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2506_RESERVEDFIELD3138_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2506_RESERVEDFIELD3139_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2506_RESERVEDFIELD3139_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2506_RESERVEDFIELD3140_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2506_RESERVEDFIELD3140_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2506_RESERVEDFIELD3141_K2_E5                          (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2506_RESERVEDFIELD3141_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2507_K2_E5                                              0x00c838UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2507_RESERVEDFIELD3142_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2507_RESERVEDFIELD3142_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2507_RESERVEDFIELD3143_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2507_RESERVEDFIELD3143_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2508_K2_E5                                              0x00c83cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2508_RESERVEDFIELD3144_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2508_RESERVEDFIELD3144_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2508_RESERVEDFIELD3145_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2508_RESERVEDFIELD3145_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2509_K2_E5                                              0x00c840UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2509_RESERVEDFIELD3146_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2509_RESERVEDFIELD3146_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2509_RESERVEDFIELD3147_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2509_RESERVEDFIELD3147_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2510_K2_E5                                              0x00c844UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2510_RESERVEDFIELD3148_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2510_RESERVEDFIELD3148_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2510_RESERVEDFIELD3149_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2510_RESERVEDFIELD3149_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2511_K2_E5                                              0x00c880UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2511_RESERVEDFIELD3150_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2511_RESERVEDFIELD3150_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2511_RESERVEDFIELD3151_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2511_RESERVEDFIELD3151_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2512_K2_E5                                              0x00c884UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2512_RESERVEDFIELD3152_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2512_RESERVEDFIELD3152_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2512_RESERVEDFIELD3153_K2_E5                          (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2512_RESERVEDFIELD3153_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2513_K2_E5                                              0x00c888UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2514_K2_E5                                              0x00c88cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2515_K2_E5                                              0x00c890UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2515_RESERVEDFIELD3156_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2515_RESERVEDFIELD3156_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2515_RESERVEDFIELD3157_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2515_RESERVEDFIELD3157_K2_E5_SHIFT                    3
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2515_RESERVEDFIELD3158_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2515_RESERVEDFIELD3158_K2_E5_SHIFT                    6
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2515_RESERVEDFIELD3159_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2515_RESERVEDFIELD3159_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2516_K2_E5                                              0x00c894UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2516_RESERVEDFIELD3160_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2516_RESERVEDFIELD3160_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2516_RESERVEDFIELD3161_K2_E5                          (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2516_RESERVEDFIELD3161_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2517_K2_E5                                              0x00c898UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2518_K2_E5                                              0x00c89cUL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2519_K2_E5                                              0x00c8a0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2519_RESERVEDFIELD3164_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2519_RESERVEDFIELD3164_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2519_RESERVEDFIELD3165_K2_E5                          (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2519_RESERVEDFIELD3165_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2520_K2_E5                                              0x00c8a4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2521_K2_E5                                              0x00c8a8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2522_K2_E5                                              0x00c8acUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2522_RESERVEDFIELD3168_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2522_RESERVEDFIELD3168_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2523_K2_E5                                              0x00c8b0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2524_K2_E5                                              0x00c8b8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_AGCLOS_CTRL0_K2_E5                                                      0x00c8c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_AGCLOS_CTRL0_AGCLOS_START_K2_E5                                       (0xf<<0) // AGC LOS Threshold Start Value
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_AGCLOS_CTRL0_AGCLOS_START_K2_E5_SHIFT                                 0
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2525_K2_E5                                              0x00c8c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2525_RESERVEDFIELD3171_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2525_RESERVEDFIELD3171_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2526_K2_E5                                              0x00c8c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2526_RESERVEDFIELD3172_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2526_RESERVEDFIELD3172_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2527_K2_E5                                              0x00c8ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2527_RESERVEDFIELD3173_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2527_RESERVEDFIELD3173_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2527_RESERVEDFIELD3174_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2527_RESERVEDFIELD3174_K2_E5_SHIFT                    6
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2527_RESERVEDFIELD3175_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2527_RESERVEDFIELD3175_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2528_K2_E5                                              0x00c8d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2528_RESERVEDFIELD3176_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2528_RESERVEDFIELD3176_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2528_RESERVEDFIELD3177_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2528_RESERVEDFIELD3177_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2528_RESERVEDFIELD3178_K2_E5                          (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2528_RESERVEDFIELD3178_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2529_K2_E5                                              0x00c8d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2529_RESERVEDFIELD3179_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2529_RESERVEDFIELD3179_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2529_RESERVEDFIELD3180_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2529_RESERVEDFIELD3180_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2529_RESERVEDFIELD3181_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2529_RESERVEDFIELD3181_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2530_K2_E5                                              0x00c8d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2530_RESERVEDFIELD3182_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2530_RESERVEDFIELD3182_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2531_K2_E5                                              0x00c8dcUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2532_K2_E5                                              0x00c8e0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2533_K2_E5                                              0x00c8e4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2534_K2_E5                                              0x00c8e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2534_RESERVEDFIELD3186_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2534_RESERVEDFIELD3186_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2535_K2_E5                                              0x00c8f4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2535_RESERVEDFIELD3187_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2535_RESERVEDFIELD3187_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2535_RESERVEDFIELD3188_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2535_RESERVEDFIELD3188_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_PLE_ATT_CTRL1_K2_E5                                                     0x00c8f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_PLE_ATT_CTRL1_PLE_ATT_START_K2_E5                                     (0x7<<0) // PLE LFG Start Value
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_PLE_ATT_CTRL1_PLE_ATT_START_K2_E5_SHIFT                               0
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_K2_E5                                                  0x00c900UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_EQ_HFG_SQL_START_K2_E5                               (0x1f<<0) // CTLE HFG Start Value
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_EQ_HFG_SQL_START_K2_E5_SHIFT                         0
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2536_K2_E5                                              0x00c904UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2536_RESERVEDFIELD3189_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2536_RESERVEDFIELD3189_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2537_K2_E5                                              0x00c908UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2537_RESERVEDFIELD3190_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2537_RESERVEDFIELD3190_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2538_K2_E5                                              0x00c90cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2538_RESERVEDFIELD3191_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2538_RESERVEDFIELD3191_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2538_RESERVEDFIELD3192_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2538_RESERVEDFIELD3192_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2539_K2_E5                                              0x00c910UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2539_RESERVEDFIELD3193_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2539_RESERVEDFIELD3193_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2539_RESERVEDFIELD3194_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2539_RESERVEDFIELD3194_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2539_RESERVEDFIELD3195_K2_E5                          (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2539_RESERVEDFIELD3195_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2540_K2_E5                                              0x00c914UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2540_RESERVEDFIELD3196_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2540_RESERVEDFIELD3196_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2540_RESERVEDFIELD3197_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2540_RESERVEDFIELD3197_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2540_RESERVEDFIELD3198_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2540_RESERVEDFIELD3198_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2541_K2_E5                                              0x00c918UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2541_RESERVEDFIELD3199_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2541_RESERVEDFIELD3199_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2542_K2_E5                                              0x00c940UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2542_RESERVEDFIELD3200_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2542_RESERVEDFIELD3200_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2542_RESERVEDFIELD3201_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2542_RESERVEDFIELD3201_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2542_RESERVEDFIELD3202_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2542_RESERVEDFIELD3202_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2542_RESERVEDFIELD3203_K2_E5                          (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2542_RESERVEDFIELD3203_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2543_K2_E5                                              0x00c944UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2543_RESERVEDFIELD3204_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2543_RESERVEDFIELD3204_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2543_RESERVEDFIELD3205_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2543_RESERVEDFIELD3205_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2544_K2_E5                                              0x00c948UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2544_RESERVEDFIELD3206_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2544_RESERVEDFIELD3206_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2544_RESERVEDFIELD3207_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2544_RESERVEDFIELD3207_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2545_K2_E5                                              0x00c94cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2545_RESERVEDFIELD3208_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2545_RESERVEDFIELD3208_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2545_RESERVEDFIELD3209_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2545_RESERVEDFIELD3209_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2546_K2_E5                                              0x00c950UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2546_RESERVEDFIELD3210_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2546_RESERVEDFIELD3210_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2546_RESERVEDFIELD3211_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2546_RESERVEDFIELD3211_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2547_K2_E5                                              0x00c954UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2547_RESERVEDFIELD3212_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2547_RESERVEDFIELD3212_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2547_RESERVEDFIELD3213_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2547_RESERVEDFIELD3213_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2548_K2_E5                                              0x00c958UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2548_RESERVEDFIELD3214_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2548_RESERVEDFIELD3214_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2548_RESERVEDFIELD3215_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2548_RESERVEDFIELD3215_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2549_K2_E5                                              0x00c95cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2549_RESERVEDFIELD3216_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2549_RESERVEDFIELD3216_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2549_RESERVEDFIELD3217_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2549_RESERVEDFIELD3217_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2550_K2_E5                                              0x00c960UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2550_RESERVEDFIELD3218_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2550_RESERVEDFIELD3218_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2550_RESERVEDFIELD3219_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2550_RESERVEDFIELD3219_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2551_K2_E5                                              0x00c964UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2551_RESERVEDFIELD3220_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2551_RESERVEDFIELD3220_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2551_RESERVEDFIELD3221_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2551_RESERVEDFIELD3221_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2552_K2_E5                                              0x00c968UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2552_RESERVEDFIELD3222_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2552_RESERVEDFIELD3222_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2552_RESERVEDFIELD3223_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2552_RESERVEDFIELD3223_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2553_K2_E5                                              0x00c96cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2553_RESERVEDFIELD3224_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2553_RESERVEDFIELD3224_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2553_RESERVEDFIELD3225_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2553_RESERVEDFIELD3225_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2554_K2_E5                                              0x00c970UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2554_RESERVEDFIELD3226_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2554_RESERVEDFIELD3226_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2554_RESERVEDFIELD3227_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2554_RESERVEDFIELD3227_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2555_K2_E5                                              0x00c974UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2555_RESERVEDFIELD3228_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2555_RESERVEDFIELD3228_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2555_RESERVEDFIELD3229_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2555_RESERVEDFIELD3229_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2556_K2_E5                                              0x00c978UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2556_RESERVEDFIELD3230_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2556_RESERVEDFIELD3230_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2556_RESERVEDFIELD3231_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2556_RESERVEDFIELD3231_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2557_K2_E5                                              0x00c97cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2557_RESERVEDFIELD3232_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2557_RESERVEDFIELD3232_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2557_RESERVEDFIELD3233_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2557_RESERVEDFIELD3233_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2558_K2_E5                                              0x00c980UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2558_RESERVEDFIELD3234_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2558_RESERVEDFIELD3234_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2558_RESERVEDFIELD3235_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2558_RESERVEDFIELD3235_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2559_K2_E5                                              0x00c984UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2559_RESERVEDFIELD3236_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2559_RESERVEDFIELD3236_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2559_RESERVEDFIELD3237_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2559_RESERVEDFIELD3237_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2560_K2_E5                                              0x00c988UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2560_RESERVEDFIELD3238_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2560_RESERVEDFIELD3238_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2560_RESERVEDFIELD3239_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2560_RESERVEDFIELD3239_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2561_K2_E5                                              0x00c98cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2561_RESERVEDFIELD3240_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2561_RESERVEDFIELD3240_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2561_RESERVEDFIELD3241_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2561_RESERVEDFIELD3241_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2562_K2_E5                                              0x00c990UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2562_RESERVEDFIELD3242_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2562_RESERVEDFIELD3242_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2562_RESERVEDFIELD3243_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2562_RESERVEDFIELD3243_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2563_K2_E5                                              0x00c994UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2563_RESERVEDFIELD3244_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2563_RESERVEDFIELD3244_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2563_RESERVEDFIELD3245_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2563_RESERVEDFIELD3245_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2564_K2_E5                                              0x00c998UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2564_RESERVEDFIELD3246_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2564_RESERVEDFIELD3246_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2564_RESERVEDFIELD3247_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2564_RESERVEDFIELD3247_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2565_K2_E5                                              0x00c99cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2565_RESERVEDFIELD3248_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2565_RESERVEDFIELD3248_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2565_RESERVEDFIELD3249_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2565_RESERVEDFIELD3249_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2566_K2_E5                                              0x00c9a0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2566_RESERVEDFIELD3250_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2566_RESERVEDFIELD3250_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2566_RESERVEDFIELD3251_K2_E5                          (0x7<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2566_RESERVEDFIELD3251_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_GN_APG_CTRL0_K2_E5                                                      0x00c9c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_GN_APG_CTRL0_GN_APG_START_K2_E5                                       (0x3<<0) // GN APG Start Value
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_GN_APG_CTRL0_GN_APG_START_K2_E5_SHIFT                                 0
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2567_K2_E5                                              0x00c9c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2567_RESERVEDFIELD3252_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2567_RESERVEDFIELD3252_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2567_RESERVEDFIELD3253_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2567_RESERVEDFIELD3253_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2568_K2_E5                                              0x00c9c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2568_RESERVEDFIELD3254_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2568_RESERVEDFIELD3254_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2568_RESERVEDFIELD3255_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2568_RESERVEDFIELD3255_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2569_K2_E5                                              0x00c9ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2569_RESERVEDFIELD3256_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2569_RESERVEDFIELD3256_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2569_RESERVEDFIELD3257_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2569_RESERVEDFIELD3257_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2569_RESERVEDFIELD3258_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2569_RESERVEDFIELD3258_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2570_K2_E5                                              0x00c9d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2570_RESERVEDFIELD3259_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2570_RESERVEDFIELD3259_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2570_RESERVEDFIELD3260_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2570_RESERVEDFIELD3260_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2570_RESERVEDFIELD3261_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2570_RESERVEDFIELD3261_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2571_K2_E5                                              0x00c9d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2571_RESERVEDFIELD3262_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2571_RESERVEDFIELD3262_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2572_K2_E5                                              0x00c9d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2572_RESERVEDFIELD3263_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2572_RESERVEDFIELD3263_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2572_RESERVEDFIELD3264_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2572_RESERVEDFIELD3264_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_LFG_CTRL0_K2_E5                                                      0x00ca00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_LFG_CTRL0_EQ_LFG_START_K2_E5                                       (0x1f<<0) // EQ LFG Start Value
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_LFG_CTRL0_EQ_LFG_START_K2_E5_SHIFT                                 0
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_LFG_CTRL1_K2_E5                                                      0x00ca04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_LFG_CTRL1_EQ_LFG_VALUE_MAX_K2_E5                                   (0x1f<<0) // EQ LFG Maximum Value, inclusive
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_LFG_CTRL1_EQ_LFG_VALUE_MAX_K2_E5_SHIFT                             0
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_LFG_CTRL2_K2_E5                                                      0x00ca08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_LFG_CTRL2_EQ_LFG_VALUE_MIN_K2_E5                                   (0x1f<<0) // EQ LFG Minimum Value, inclusive
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_LFG_CTRL2_EQ_LFG_VALUE_MIN_K2_E5_SHIFT                             0
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2573_K2_E5                                              0x00ca0cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2573_RESERVEDFIELD3265_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2573_RESERVEDFIELD3265_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2573_RESERVEDFIELD3266_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2573_RESERVEDFIELD3266_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2574_K2_E5                                              0x00ca10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2574_RESERVEDFIELD3267_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2574_RESERVEDFIELD3267_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2574_RESERVEDFIELD3268_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2574_RESERVEDFIELD3268_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2574_RESERVEDFIELD3269_K2_E5                          (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2574_RESERVEDFIELD3269_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2575_K2_E5                                              0x00ca14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2575_RESERVEDFIELD3270_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2575_RESERVEDFIELD3270_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2575_RESERVEDFIELD3271_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2575_RESERVEDFIELD3271_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2575_RESERVEDFIELD3272_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2575_RESERVEDFIELD3272_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2576_K2_E5                                              0x00ca18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2576_RESERVEDFIELD3273_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2576_RESERVEDFIELD3273_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2577_K2_E5                                              0x00ca1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2577_RESERVEDFIELD3274_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2577_RESERVEDFIELD3274_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2578_K2_E5                                              0x00ca20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2578_RESERVEDFIELD3275_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2578_RESERVEDFIELD3275_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2579_K2_E5                                              0x00ca40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2579_RESERVEDFIELD3276_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2579_RESERVEDFIELD3276_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2580_K2_E5                                              0x00ca44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2580_RESERVEDFIELD3277_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2580_RESERVEDFIELD3277_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2581_K2_E5                                              0x00ca48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2581_RESERVEDFIELD3278_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2581_RESERVEDFIELD3278_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2582_K2_E5                                              0x00ca4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2582_RESERVEDFIELD3279_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2582_RESERVEDFIELD3279_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2582_RESERVEDFIELD3280_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2582_RESERVEDFIELD3280_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2583_K2_E5                                              0x00ca50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2583_RESERVEDFIELD3281_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2583_RESERVEDFIELD3281_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2583_RESERVEDFIELD3282_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2583_RESERVEDFIELD3282_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2583_RESERVEDFIELD3283_K2_E5                          (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2583_RESERVEDFIELD3283_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2584_K2_E5                                              0x00ca54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2584_RESERVEDFIELD3284_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2584_RESERVEDFIELD3284_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2584_RESERVEDFIELD3285_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2584_RESERVEDFIELD3285_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2584_RESERVEDFIELD3286_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2584_RESERVEDFIELD3286_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2585_K2_E5                                              0x00ca58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2585_RESERVEDFIELD3287_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2585_RESERVEDFIELD3287_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2586_K2_E5                                              0x00ca60UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2586_RESERVEDFIELD3288_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2586_RESERVEDFIELD3288_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2586_RESERVEDFIELD3289_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2586_RESERVEDFIELD3289_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_MB_CTRL1_K2_E5                                                       0x00ca64UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_K2_E5                                        (0xf<<0) // EQ MBF Start Value
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_K2_E5                                        (0xf<<4) // EQ MBG Start Value
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_K2_E5_SHIFT                                  4
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2587_K2_E5                                              0x00ca68UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2588_K2_E5                                              0x00ca6cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2589_K2_E5                                              0x00ca70UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2589_RESERVEDFIELD3292_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2589_RESERVEDFIELD3292_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2589_RESERVEDFIELD3293_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2589_RESERVEDFIELD3293_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2589_RESERVEDFIELD3294_K2_E5                          (0xf<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2589_RESERVEDFIELD3294_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2590_K2_E5                                              0x00ca74UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2590_RESERVEDFIELD3295_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2590_RESERVEDFIELD3295_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2590_RESERVEDFIELD3296_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2590_RESERVEDFIELD3296_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2590_RESERVEDFIELD3297_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2590_RESERVEDFIELD3297_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2591_K2_E5                                              0x00ca80UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2592_K2_E5                                              0x00ca84UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2593_K2_E5                                              0x00ca88UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2593_RESERVEDFIELD3300_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2593_RESERVEDFIELD3300_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2593_RESERVEDFIELD3301_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2593_RESERVEDFIELD3301_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2593_RESERVEDFIELD3302_K2_E5                          (0xf<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2593_RESERVEDFIELD3302_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2594_K2_E5                                              0x00ca8cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2594_RESERVEDFIELD3303_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2594_RESERVEDFIELD3303_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2594_RESERVEDFIELD3304_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2594_RESERVEDFIELD3304_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2594_RESERVEDFIELD3305_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2594_RESERVEDFIELD3305_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2595_K2_E5                                              0x00ca98UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2596_K2_E5                                              0x00ca9cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2597_K2_E5                                              0x00caa0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2598_K2_E5                                              0x00caa4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2599_K2_E5                                              0x00caacUL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2600_K2_E5                                              0x00cab0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2600_RESERVEDFIELD3311_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2600_RESERVEDFIELD3311_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2600_RESERVEDFIELD3312_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2600_RESERVEDFIELD3312_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2601_K2_E5                                              0x00cab8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2601_RESERVEDFIELD3313_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2601_RESERVEDFIELD3313_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2601_RESERVEDFIELD3314_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2601_RESERVEDFIELD3314_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2602_K2_E5                                              0x00cabcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2602_RESERVEDFIELD3315_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2602_RESERVEDFIELD3315_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2603_K2_E5                                              0x00cae0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2604_K2_E5                                              0x00cae4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2605_K2_E5                                               0x00cc00UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2606_K2_E5                                               0x00cc04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2606_RESERVEDFIELD3317_K2_E5                           (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2606_RESERVEDFIELD3317_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2607_K2_E5                                               0x00cc08UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2608_K2_E5                                               0x00cc0cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2608_RESERVEDFIELD3319_K2_E5                           (0x7f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2608_RESERVEDFIELD3319_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2609_K2_E5                                               0x00cc10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2609_RESERVEDFIELD3320_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2609_RESERVEDFIELD3320_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2610_K2_E5                                               0x00cc14UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2611_K2_E5                                               0x00cc20UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2612_K2_E5                                               0x00cc24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2612_RESERVEDFIELD3323_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2612_RESERVEDFIELD3323_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2613_K2_E5                                               0x00cc30UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2614_K2_E5                                               0x00cc34UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2614_RESERVEDFIELD3325_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2614_RESERVEDFIELD3325_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2615_K2_E5                                               0x00cc40UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2616_K2_E5                                               0x00cc44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2616_RESERVEDFIELD3327_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2616_RESERVEDFIELD3327_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2617_K2_E5                                               0x00cc4cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2618_K2_E5                                               0x00cc50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2618_RESERVEDFIELD3329_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2618_RESERVEDFIELD3329_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2619_K2_E5                                               0x00cc58UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2620_K2_E5                                               0x00cc5cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2620_RESERVEDFIELD3331_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2620_RESERVEDFIELD3331_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2621_K2_E5                                               0x00cc80UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LEQ_RXCLK_RESERVEDREGISTER2622_K2_E5                                               0x00cc84UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DRV_REFCLK_AFE_PD_CTRL0_K2_E5                                                      0x00ce00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_AFE_PD_CTRL0_PD_TXDRV_K2_E5                                           (0xf<<0) // power down TX driver
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_AFE_PD_CTRL0_PD_TXDRV_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2623_K2_E5                                              0x00ce04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2623_RESERVEDFIELD3332_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2623_RESERVEDFIELD3332_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DRV_REFCLK_AFE_CTRL0_K2_E5                                                         0x00ce08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_AFE_CTRL0_TXDRV_LP_IDLE_K2_E5                                         (0x3<<0) // When HIGH, TX driver goes into a low power IDLE model. In this mode, the output termination is not guaranteed to be 50 Ohm closer to 200 Ohm
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_AFE_CTRL0_TXDRV_LP_IDLE_K2_E5_SHIFT                                   0
+#define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2624_K2_E5                                              0x00ce0cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2625_K2_E5                                              0x00ce10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2625_RESERVEDFIELD3334_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2625_RESERVEDFIELD3334_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2625_RESERVEDFIELD3335_K2_E5                          (0x1f<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2625_RESERVEDFIELD3335_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2626_K2_E5                                              0x00ce14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2626_RESERVEDFIELD3336_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2626_RESERVEDFIELD3336_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2627_K2_E5                                              0x00ce18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2627_RESERVEDFIELD3337_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2627_RESERVEDFIELD3337_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2627_RESERVEDFIELD3338_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2627_RESERVEDFIELD3338_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2627_RESERVEDFIELD3339_K2_E5                          (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2627_RESERVEDFIELD3339_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2627_RESERVEDFIELD3340_K2_E5                          (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2627_RESERVEDFIELD3340_K2_E5_SHIFT                    5
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2627_RESERVEDFIELD3341_K2_E5                          (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2627_RESERVEDFIELD3341_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2628_K2_E5                                              0x00ce20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2628_RESERVEDFIELD3342_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2628_RESERVEDFIELD3342_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2628_RESERVEDFIELD3343_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2628_RESERVEDFIELD3343_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2628_RESERVEDFIELD3344_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2628_RESERVEDFIELD3344_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2628_RESERVEDFIELD3345_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2628_RESERVEDFIELD3345_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2629_K2_E5                                              0x00ce24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2629_RESERVEDFIELD3346_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2629_RESERVEDFIELD3346_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2629_RESERVEDFIELD3347_K2_E5                          (0x1f<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2629_RESERVEDFIELD3347_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2630_K2_E5                                              0x00ce28UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2630_RESERVEDFIELD3348_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2630_RESERVEDFIELD3348_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2630_RESERVEDFIELD3349_K2_E5                          (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2630_RESERVEDFIELD3349_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2631_K2_E5                                              0x00ce2cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2631_RESERVEDFIELD3350_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2631_RESERVEDFIELD3350_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2631_RESERVEDFIELD3351_K2_E5                          (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2631_RESERVEDFIELD3351_K2_E5_SHIFT                    5
+#define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2632_K2_E5                                              0x00ce30UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2632_RESERVEDFIELD3352_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2632_RESERVEDFIELD3352_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2632_RESERVEDFIELD3353_K2_E5                          (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2632_RESERVEDFIELD3353_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2633_K2_E5                                              0x00ce34UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2633_RESERVEDFIELD3354_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2633_RESERVEDFIELD3354_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2633_RESERVEDFIELD3355_K2_E5                          (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2633_RESERVEDFIELD3355_K2_E5_SHIFT                    5
+#define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL0_K2_E5                                                        0x00ce40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL0_REQ_K2_E5                                                  (0x1<<0) // Set to 1 to apply the coefficient settings, and hold until ack is 1.  Set to 0 once ack is 1.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL0_REQ_K2_E5_SHIFT                                            0
+#define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_STATUS0_K2_E5                                                      0x00ce44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_STATUS0_ACK_K2_E5                                                (0x1<<0) // Set to 1 by firmware when updates are complete. Cleared when req = 0
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_STATUS0_ACK_K2_E5_SHIFT                                          0
+#define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL1_K2_E5                                                        0x00ce48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL1_TXEQ_C1_K2_E5                                              (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL1_TXEQ_C1_K2_E5_SHIFT                                        0
+#define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2634_K2_E5                                              0x00ce4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2634_RESERVEDFIELD3356_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2634_RESERVEDFIELD3356_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL3_K2_E5                                                        0x00ce50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL3_TXEQ_CM1_K2_E5                                             (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL3_TXEQ_CM1_K2_E5_SHIFT                                       0
+#define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2635_K2_E5                                              0x00ce54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2635_RESERVEDFIELD3357_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2635_RESERVEDFIELD3357_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2635_RESERVEDFIELD3358_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2635_RESERVEDFIELD3358_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL5_K2_E5                                                        0x00ce58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL5_DRV_SWING_K2_E5                                            (0xf<<0) // Thermometer coded control to adjust the delay between data and clock for the final 2to1 mux. Setting 00000 min delay of clock path and 11111 max delay of clock path.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL5_DRV_SWING_K2_E5_SHIFT                                      0
+#define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2636_K2_E5                                              0x00ce5cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2636_RESERVEDFIELD3359_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2636_RESERVEDFIELD3359_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2636_RESERVEDFIELD3360_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2636_RESERVEDFIELD3360_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2636_RESERVEDFIELD3361_K2_E5                          (0x7<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2636_RESERVEDFIELD3361_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2636_RESERVEDFIELD3362_K2_E5                          (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2636_RESERVEDFIELD3362_K2_E5_SHIFT                    5
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2636_RESERVEDFIELD3363_K2_E5                          (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2636_RESERVEDFIELD3363_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2637_K2_E5                                              0x00ce60UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2637_RESERVEDFIELD3364_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2637_RESERVEDFIELD3364_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2637_RESERVEDFIELD3365_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2637_RESERVEDFIELD3365_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2637_RESERVEDFIELD3366_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2637_RESERVEDFIELD3366_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2637_RESERVEDFIELD3367_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2637_RESERVEDFIELD3367_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2638_K2_E5                                              0x00ce64UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2638_RESERVEDFIELD3368_K2_E5                          (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2638_RESERVEDFIELD3368_K2_E5_SHIFT                    3
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2638_RESERVEDFIELD3369_K2_E5                          (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2638_RESERVEDFIELD3369_K2_E5_SHIFT                    5
+#define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2639_K2_E5                                              0x00ce6cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2639_RESERVEDFIELD3370_K2_E5                          (0x3<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2639_RESERVEDFIELD3370_K2_E5_SHIFT                    3
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2639_RESERVEDFIELD3371_K2_E5                          (0x3<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2639_RESERVEDFIELD3371_K2_E5_SHIFT                    5
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2640_K2_E5                                              0x00d000UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2640_RESERVEDFIELD3372_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2640_RESERVEDFIELD3372_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2641_K2_E5                                              0x00d004UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2641_RESERVEDFIELD3373_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2641_RESERVEDFIELD3373_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2642_K2_E5                                              0x00d008UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2642_RESERVEDFIELD3374_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2642_RESERVEDFIELD3374_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2642_RESERVEDFIELD3375_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2642_RESERVEDFIELD3375_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2643_K2_E5                                              0x00d00cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2643_RESERVEDFIELD3376_K2_E5                          (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2643_RESERVEDFIELD3376_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2643_RESERVEDFIELD3377_K2_E5                          (0x7<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2643_RESERVEDFIELD3377_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2644_K2_E5                                              0x00d010UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2644_RESERVEDFIELD3378_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2644_RESERVEDFIELD3378_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2645_K2_E5                                              0x00d018UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2645_RESERVEDFIELD3379_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2645_RESERVEDFIELD3379_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2646_K2_E5                                              0x00d028UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2646_RESERVEDFIELD3380_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2646_RESERVEDFIELD3380_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2646_RESERVEDFIELD3381_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2646_RESERVEDFIELD3381_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2646_RESERVEDFIELD3382_K2_E5                          (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2646_RESERVEDFIELD3382_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2647_K2_E5                                              0x00d030UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2647_RESERVEDFIELD3383_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2647_RESERVEDFIELD3383_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2647_RESERVEDFIELD3384_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2647_RESERVEDFIELD3384_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2648_K2_E5                                              0x00d038UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2648_RESERVEDFIELD3385_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2648_RESERVEDFIELD3385_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2648_RESERVEDFIELD3386_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2648_RESERVEDFIELD3386_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2648_RESERVEDFIELD3387_K2_E5                          (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2648_RESERVEDFIELD3387_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2649_K2_E5                                              0x00d040UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2649_RESERVEDFIELD3388_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2649_RESERVEDFIELD3388_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2649_RESERVEDFIELD3389_K2_E5                          (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2649_RESERVEDFIELD3389_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2649_RESERVEDFIELD3390_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2649_RESERVEDFIELD3390_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2650_K2_E5                                              0x00d048UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2650_RESERVEDFIELD3391_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2650_RESERVEDFIELD3391_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2650_RESERVEDFIELD3392_K2_E5                          (0x3<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2650_RESERVEDFIELD3392_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2651_K2_E5                                              0x00d050UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2652_K2_E5                                              0x00d058UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2652_RESERVEDFIELD3394_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2652_RESERVEDFIELD3394_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2652_RESERVEDFIELD3395_K2_E5                          (0xf<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2652_RESERVEDFIELD3395_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2653_K2_E5                                              0x00d060UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2654_K2_E5                                              0x00d064UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2654_RESERVEDFIELD3397_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2654_RESERVEDFIELD3397_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2655_K2_E5                                              0x00d06cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2655_RESERVEDFIELD3398_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2655_RESERVEDFIELD3398_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2655_RESERVEDFIELD3399_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2655_RESERVEDFIELD3399_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_CTRL0_K2_E5                                                         0x00d080UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_CTRL0_REQ_K2_E5                                                   (0x1<<0) // Write 1 to request a command CMD execution.  It should be held at 1 until fsm_status0.ack is 1, and then it should be set back to 0.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_CTRL0_REQ_K2_E5_SHIFT                                             0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_CTRL0_CMD_K2_E5                                                   (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_CTRL0_CMD_K2_E5_SHIFT                                             1
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_CTRL0_RESERVEDFIELD3400_K2_E5                                     (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_CTRL0_RESERVEDFIELD3400_K2_E5_SHIFT                               6
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL_K2_E5                                     (0x1<<7) // Set it to 1 when changing DFE tap values
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL_K2_E5_SHIFT                               7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2656_K2_E5                                              0x00d084UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2656_RESERVEDFIELD3401_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2656_RESERVEDFIELD3401_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2656_RESERVEDFIELD3402_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2656_RESERVEDFIELD3402_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2657_K2_E5                                              0x00d088UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2658_K2_E5                                              0x00d08cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2658_RESERVEDFIELD3404_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2658_RESERVEDFIELD3404_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2659_K2_E5                                              0x00d090UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2660_K2_E5                                              0x00d094UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2660_RESERVEDFIELD3406_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2660_RESERVEDFIELD3406_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2661_K2_E5                                              0x00d098UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2662_K2_E5                                              0x00d09cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2662_RESERVEDFIELD3408_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2662_RESERVEDFIELD3408_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_STATUS0_K2_E5                                                       0x00d0a0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_STATUS0_ACK_K2_E5                                                 (0x1<<0) // Acknowledge from DFE after command execution. Will be set to 1 after a command is completed, and will clear to 0 after fsm_status0.req is cleared
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_STATUS0_ACK_K2_E5_SHIFT                                           0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD3409_K2_E5                                   (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD3409_K2_E5_SHIFT                             1
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD3410_K2_E5                                   (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD3410_K2_E5_SHIFT                             2
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD3411_K2_E5                                   (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD3411_K2_E5_SHIFT                             3
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_K2_E5                                                         0x00d0a8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN_K2_E5                                         (0x1<<0) // Enables updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN_K2_E5                                         (0x1<<1) // Enables updating Tap 1 Even 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN_K2_E5_SHIFT                                   1
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN_K2_E5                                          (0x1<<2) // Enables updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN_K2_E5_SHIFT                                    2
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN_K2_E5                                          (0x1<<3) // Enables updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN_K2_E5_SHIFT                                    3
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP2_EN_K2_E5                                               (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP2_EN_K2_E5_SHIFT                                         4
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP3_EN_K2_E5                                               (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP3_EN_K2_E5_SHIFT                                         5
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP4_EN_K2_E5                                               (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP4_EN_K2_E5_SHIFT                                         6
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP5_EN_K2_E5                                               (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP5_EN_K2_E5_SHIFT                                         7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL0_K2_E5                                               0x00d0acUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_K2_E5                                  (0x1f<<0) // Starting value for Tap 1 Even 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_K2_E5_SHIFT                            0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5                         (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5_SHIFT                   7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL1_K2_E5                                               0x00d0b0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_K2_E5                                  (0x1f<<0) // Starting value for Tap 1 Even 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_K2_E5_SHIFT                            0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5                         (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5_SHIFT                   7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL2_K2_E5                                               0x00d0b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_K2_E5                                   (0x1f<<0) // Starting value for Tap 1 Odd 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5                          (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL3_K2_E5                                               0x00d0b8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_K2_E5                                   (0x1f<<0) // Starting value for Tap 1 Odd 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5                          (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL4_K2_E5                                               0x00d0bcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_K2_E5                                        (0xf<<0) // Starting value for Tap 2 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY_K2_E5                               (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY_K2_E5_SHIFT                         7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL5_K2_E5                                               0x00d0c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_K2_E5                                        (0x7<<0) // Starting value for Tap 3 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY_K2_E5                               (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY_K2_E5_SHIFT                         7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL6_K2_E5                                               0x00d0c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_K2_E5                                        (0x7<<0) // Starting value for Tap 4 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY_K2_E5                               (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY_K2_E5_SHIFT                         7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL7_K2_E5                                               0x00d0c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_K2_E5                                        (0x7<<0) // Starting value for Tap 5 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY_K2_E5                               (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY_K2_E5_SHIFT                         7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_K2_E5                                                0x00d0ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_K2_E5                                   (0x1f<<0) // Loading value for Tap 1 Even 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5                          (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_K2_E5                                                0x00d0d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_K2_E5                                   (0x1f<<0) // Loading value for Tap 1 Even 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_K2_E5_SHIFT                             0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5                          (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_K2_E5                                                0x00d0d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_K2_E5                                    (0x1f<<0) // Loading value for Tap 1 Odd 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5                           (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5_SHIFT                     7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_K2_E5                                                0x00d0d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_K2_E5                                    (0x1f<<0) // Loading value for Tap 1 Odd 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5                           (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5_SHIFT                     7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_K2_E5                                                0x00d0dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_K2_E5                                         (0xf<<0) // Loading value for Tap 2 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_K2_E5                                (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_K2_E5                                                0x00d0e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_K2_E5                                         (0x7<<0) // Loading value for Tap 3 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_K2_E5                                (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_K2_E5                                                0x00d0e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_K2_E5                                         (0x7<<0) // Loading value for Tap 4 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_K2_E5                                (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_K2_E5                                                0x00d0e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_K2_E5                                         (0x7<<0) // Loading value for Tap 5 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_K2_E5                                (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_K2_E5_SHIFT                          7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS0_K2_E5                                                   0x00d0ecUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_K2_E5                                      (0x1f<<0) // binary value for Tap 1 Even 0 Path for Tap Adaptations
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_K2_E5_SHIFT                                0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_K2_E5                             (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_K2_E5_SHIFT                       7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS1_K2_E5                                                   0x00d0f0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_K2_E5                                      (0x1f<<0) // binary  value for Tap 1 Even 1 Path for Tap Adaptations
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_K2_E5_SHIFT                                0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_K2_E5                             (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_K2_E5_SHIFT                       7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS2_K2_E5                                                   0x00d0f4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_K2_E5                                       (0x1f<<0) // binary  value for Tap 1 Odd 0 Path for Tap Adaptations
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_K2_E5                              (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_K2_E5_SHIFT                        7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS3_K2_E5                                                   0x00d0f8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_K2_E5                                       (0x1f<<0) // binary  value for Tap 1 Odd 1 Path for Tap Adaptations
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_K2_E5                              (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_K2_E5_SHIFT                        7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS4_K2_E5                                                   0x00d0fcUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_K2_E5                                            (0xf<<0) // binary  value for Tap 2 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY_K2_E5                                   (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS5_K2_E5                                                   0x00d100UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_K2_E5                                            (0x7<<0) // binary  value for Tap 3 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY_K2_E5                                   (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS6_K2_E5                                                   0x00d104UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_K2_E5                                            (0x7<<0) // binary  value for Tap 4 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY_K2_E5                                   (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS7_K2_E5                                                   0x00d108UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_K2_E5                                            (0x7<<0) // binary  value for Tap 5 for Tap Adaptations
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY_K2_E5                                   (0x1<<7) // polarity 0 = negative, 1 = positive
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY_K2_E5_SHIFT                             7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_K2_E5                                              0x00d140UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3412_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3412_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3413_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3413_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3414_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3414_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3415_K2_E5                          (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3415_K2_E5_SHIFT                    3
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3416_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3416_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3417_K2_E5                          (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3417_K2_E5_SHIFT                    5
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3418_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3418_K2_E5_SHIFT                    6
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3419_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3419_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2664_K2_E5                                              0x00d144UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2664_RESERVEDFIELD3420_K2_E5                          (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2664_RESERVEDFIELD3420_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2665_K2_E5                                              0x00d148UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2665_RESERVEDFIELD3421_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2665_RESERVEDFIELD3421_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2666_K2_E5                                              0x00d14cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2666_RESERVEDFIELD3422_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2666_RESERVEDFIELD3422_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2667_K2_E5                                              0x00d150UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2667_RESERVEDFIELD3423_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2667_RESERVEDFIELD3423_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2668_K2_E5                                              0x00d154UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2668_RESERVEDFIELD3424_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2668_RESERVEDFIELD3424_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2669_K2_E5                                              0x00d158UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2669_RESERVEDFIELD3425_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2669_RESERVEDFIELD3425_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2670_K2_E5                                              0x00d15cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2670_RESERVEDFIELD3426_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2670_RESERVEDFIELD3426_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2671_K2_E5                                              0x00d160UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2671_RESERVEDFIELD3427_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2671_RESERVEDFIELD3427_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2672_K2_E5                                              0x00d164UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2672_RESERVEDFIELD3428_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2672_RESERVEDFIELD3428_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2673_K2_E5                                              0x00d168UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2673_RESERVEDFIELD3429_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2673_RESERVEDFIELD3429_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2674_K2_E5                                              0x00d16cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2674_RESERVEDFIELD3430_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2674_RESERVEDFIELD3430_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2675_K2_E5                                              0x00d170UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2675_RESERVEDFIELD3431_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2675_RESERVEDFIELD3431_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2676_K2_E5                                              0x00d174UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2676_RESERVEDFIELD3432_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2676_RESERVEDFIELD3432_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2677_K2_E5                                              0x00d178UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2677_RESERVEDFIELD3433_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2677_RESERVEDFIELD3433_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2678_K2_E5                                              0x00d17cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2678_RESERVEDFIELD3434_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2678_RESERVEDFIELD3434_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2679_K2_E5                                              0x00d180UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2679_RESERVEDFIELD3435_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2679_RESERVEDFIELD3435_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2680_K2_E5                                              0x00d184UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2680_RESERVEDFIELD3436_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2680_RESERVEDFIELD3436_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2681_K2_E5                                              0x00d188UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2681_RESERVEDFIELD3437_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2681_RESERVEDFIELD3437_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_K2_E5                                              0x00d18cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3438_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3438_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3439_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3439_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3440_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3440_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3441_K2_E5                          (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3441_K2_E5_SHIFT                    3
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3442_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3442_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3443_K2_E5                          (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3443_K2_E5_SHIFT                    5
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3444_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3444_K2_E5_SHIFT                    6
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3445_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3445_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2683_K2_E5                                              0x00d190UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2683_RESERVEDFIELD3446_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2683_RESERVEDFIELD3446_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2683_RESERVEDFIELD3447_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2683_RESERVEDFIELD3447_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2683_RESERVEDFIELD3448_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2683_RESERVEDFIELD3448_K2_E5_SHIFT                    2
+#define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_K2_E5                                              0x00d194UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3449_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3449_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3450_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3450_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3451_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3451_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3452_K2_E5                          (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3452_K2_E5_SHIFT                    3
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3453_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3453_K2_E5_SHIFT                    4
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3454_K2_E5                          (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3454_K2_E5_SHIFT                    5
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3455_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3455_K2_E5_SHIFT                    6
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3456_K2_E5                          (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3456_K2_E5_SHIFT                    7
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2685_K2_E5                                               0x00d200UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2686_K2_E5                                               0x00d204UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2686_RESERVEDFIELD3458_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2686_RESERVEDFIELD3458_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2687_K2_E5                                               0x00d208UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2687_RESERVEDFIELD3459_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2687_RESERVEDFIELD3459_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2687_RESERVEDFIELD3460_K2_E5                           (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2687_RESERVEDFIELD3460_K2_E5_SHIFT                     5
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2687_RESERVEDFIELD3461_K2_E5                           (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2687_RESERVEDFIELD3461_K2_E5_SHIFT                     6
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2688_K2_E5                                               0x00d218UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2688_RESERVEDFIELD3462_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2688_RESERVEDFIELD3462_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2688_RESERVEDFIELD3463_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2688_RESERVEDFIELD3463_K2_E5_SHIFT                     1
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2689_K2_E5                                               0x00d21cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2690_K2_E5                                               0x00d220UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2690_RESERVEDFIELD3465_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2690_RESERVEDFIELD3465_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2691_K2_E5                                               0x00d224UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2691_RESERVEDFIELD3466_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2691_RESERVEDFIELD3466_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2691_RESERVEDFIELD3467_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2691_RESERVEDFIELD3467_K2_E5_SHIFT                     1
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2692_K2_E5                                               0x00d228UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2693_K2_E5                                               0x00d22cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2693_RESERVEDFIELD3469_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2693_RESERVEDFIELD3469_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2694_K2_E5                                               0x00d230UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2695_K2_E5                                               0x00d234UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2695_RESERVEDFIELD3471_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2695_RESERVEDFIELD3471_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2696_K2_E5                                               0x00d240UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2696_RESERVEDFIELD3472_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2696_RESERVEDFIELD3472_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2696_RESERVEDFIELD3473_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2696_RESERVEDFIELD3473_K2_E5_SHIFT                     1
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2696_RESERVEDFIELD3474_K2_E5                           (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2696_RESERVEDFIELD3474_K2_E5_SHIFT                     2
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2697_K2_E5                                               0x00d244UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2697_RESERVEDFIELD3475_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2697_RESERVEDFIELD3475_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2698_K2_E5                                               0x00d248UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2699_K2_E5                                               0x00d258UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2700_K2_E5                                               0x00d25cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2700_RESERVEDFIELD3478_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2700_RESERVEDFIELD3478_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2701_K2_E5                                               0x00d260UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2702_K2_E5                                               0x00d264UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2702_RESERVEDFIELD3480_K2_E5                           (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2702_RESERVEDFIELD3480_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2703_K2_E5                                               0x00d268UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2704_K2_E5                                               0x00d26cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2705_K2_E5                                               0x00d270UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2706_K2_E5                                               0x00d274UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2707_K2_E5                                               0x00d278UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2708_K2_E5                                               0x00d290UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2708_RESERVEDFIELD3486_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2708_RESERVEDFIELD3486_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2708_RESERVEDFIELD3487_K2_E5                           (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2708_RESERVEDFIELD3487_K2_E5_SHIFT                     2
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2708_RESERVEDFIELD3488_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2708_RESERVEDFIELD3488_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2709_K2_E5                                               0x00d294UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2709_RESERVEDFIELD3489_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2709_RESERVEDFIELD3489_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2709_RESERVEDFIELD3490_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2709_RESERVEDFIELD3490_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2710_K2_E5                                               0x00d298UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2710_RESERVEDFIELD3491_K2_E5                           (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2710_RESERVEDFIELD3491_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2710_RESERVEDFIELD3492_K2_E5                           (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2710_RESERVEDFIELD3492_K2_E5_SHIFT                     4
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2711_K2_E5                                               0x00d29cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2711_RESERVEDFIELD3493_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2711_RESERVEDFIELD3493_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2712_K2_E5                                               0x00d2a0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2713_K2_E5                                               0x00d2a4UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2714_K2_E5                                               0x00d2a8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2715_K2_E5                                               0x00d2acUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2715_RESERVEDFIELD3497_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2715_RESERVEDFIELD3497_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2716_K2_E5                                               0x00d2b0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2717_K2_E5                                               0x00d2b4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2717_RESERVEDFIELD3499_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2717_RESERVEDFIELD3499_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2718_K2_E5                                               0x00d2b8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2719_K2_E5                                               0x00d2bcUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2719_RESERVEDFIELD3501_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2719_RESERVEDFIELD3501_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2720_K2_E5                                               0x00d2c0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2721_K2_E5                                               0x00d2c4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2721_RESERVEDFIELD3503_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2721_RESERVEDFIELD3503_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2722_K2_E5                                               0x00d2c8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2723_K2_E5                                               0x00d2ccUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2723_RESERVEDFIELD3505_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2723_RESERVEDFIELD3505_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2724_K2_E5                                               0x00d2d0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2725_K2_E5                                               0x00d2d4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2725_RESERVEDFIELD3507_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2725_RESERVEDFIELD3507_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2726_K2_E5                                               0x00d2d8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2727_K2_E5                                               0x00d2dcUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2727_RESERVEDFIELD3509_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2727_RESERVEDFIELD3509_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2728_K2_E5                                               0x00d2e0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2729_K2_E5                                               0x00d2e4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2729_RESERVEDFIELD3511_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2729_RESERVEDFIELD3511_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2730_K2_E5                                               0x00d300UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2731_K2_E5                                               0x00d304UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2732_K2_E5                                               0x00d308UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2733_K2_E5                                               0x00d30cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2733_RESERVEDFIELD3515_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2733_RESERVEDFIELD3515_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2734_K2_E5                                               0x00d310UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2735_K2_E5                                               0x00d314UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2735_RESERVEDFIELD3517_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2735_RESERVEDFIELD3517_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2736_K2_E5                                               0x00d318UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2737_K2_E5                                               0x00d31cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2737_RESERVEDFIELD3519_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2737_RESERVEDFIELD3519_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2738_K2_E5                                               0x00d320UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2739_K2_E5                                               0x00d324UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2739_RESERVEDFIELD3521_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2739_RESERVEDFIELD3521_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2740_K2_E5                                               0x00d328UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2741_K2_E5                                               0x00d32cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2741_RESERVEDFIELD3523_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2741_RESERVEDFIELD3523_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2742_K2_E5                                               0x00d330UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2743_K2_E5                                               0x00d334UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2743_RESERVEDFIELD3525_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2743_RESERVEDFIELD3525_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2744_K2_E5                                               0x00d338UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2745_K2_E5                                               0x00d33cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2745_RESERVEDFIELD3527_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2745_RESERVEDFIELD3527_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2746_K2_E5                                               0x00d340UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2747_K2_E5                                               0x00d344UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2747_RESERVEDFIELD3529_K2_E5                           (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2747_RESERVEDFIELD3529_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2748_K2_E5                                               0x00d358UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2748_RESERVEDFIELD3530_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2748_RESERVEDFIELD3530_K2_E5_SHIFT                     0
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2748_RESERVEDFIELD3531_K2_E5                           (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2748_RESERVEDFIELD3531_K2_E5_SHIFT                     1
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2749_K2_E5                                               0x00d35cUL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2750_K2_E5                                               0x00d360UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2751_K2_E5                                               0x00d380UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2751_RESERVEDFIELD3534_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2751_RESERVEDFIELD3534_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2752_K2_E5                                               0x00d384UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2753_K2_E5                                               0x00d388UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2754_K2_E5                                               0x00d38cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2755_K2_E5                                               0x00d390UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2756_K2_E5                                               0x00d394UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2757_K2_E5                                               0x00d398UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2758_K2_E5                                               0x00d39cUL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2759_K2_E5                                               0x00d3a0UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2760_K2_E5                                               0x00d3a4UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2761_K2_E5                                               0x00d3a8UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2762_K2_E5                                               0x00d3acUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2762_RESERVEDFIELD3545_K2_E5                           (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2762_RESERVEDFIELD3545_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_AFE_CAL_CTRL_K2_E5                                                      0x00d400UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_AFE_CAL_CTRL_RXLOS_OFFSETCAL_K2_E5                                    (0x1<<0) // Enables analog LOS offset calibration circuits.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_AFE_CAL_CTRL_RXLOS_OFFSETCAL_K2_E5_SHIFT                              0
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2763_K2_E5                                              0x00d404UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2763_RESERVEDFIELD3546_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2763_RESERVEDFIELD3546_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2764_K2_E5                                              0x00d408UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2764_RESERVEDFIELD3547_K2_E5                          (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2764_RESERVEDFIELD3547_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_CTRL0_K2_E5                                                  0x00d40cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_CTRL0_EN_K2_E5                                             (0x1<<0) // Enables the run-length detection digital LOS filter.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_CTRL0_EN_K2_E5_SHIFT                                       0
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_CTRL1_K2_E5                                                  0x00d410UL //Access:RW   DataWidth:0x8    // Value of run-length which will trigger an LOS condition.
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_STATUS0_K2_E5                                                0x00d414UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_K2_E5                                       (0x1<<0) // Indicates that the run-length filter is currently exceeding the specified run-length threshold.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY_K2_E5                                (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the specified run-length threshold.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY_K2_E5_SHIFT                          1
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL0_K2_E5                                                      0x00d440UL //Access:RW   DataWidth:0x8    // Digital Rx LOS glitch filter assertion threshold.  Determines the number of consecutive clk_i clock cycles that the analog  LOS must remain a logic 1 before the output of the filter will assert.  Can be disabled by writing a value of 0x00.
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL1_K2_E5                                                      0x00d444UL //Access:RW   DataWidth:0x8    // Digital Rx LOS glitch filter assertion threshold.  Determines the number of consecutive clk_i clock cycles that the analog  LOS must remain a logic 1 before the output of the filter will assert.  Can be disabled by writing a value of 0x0000.
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL2_K2_E5                                                      0x00d448UL //Access:RW   DataWidth:0x8    // Digital Rx LOS glitch filter assertion threshold.  Determines the number of consecutive clk_i clock cycles that the raw analog  LOS must remain a logic 1 before the output of the filter will assert.  Can be disabled by writing a value of 0x000000.
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL3_K2_E5                                                      0x00d44cUL //Access:RW   DataWidth:0x8    // Same as above.
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL4_K2_E5                                                      0x00d450UL //Access:RW   DataWidth:0x8    // Same as above.
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL5_K2_E5                                                      0x00d454UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL5_DEASSERT_THRESHOLD_25_24_K2_E5                           (0x3<<0) // Same as above.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL5_DEASSERT_THRESHOLD_25_24_K2_E5_SHIFT                     0
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL6_K2_E5                                                      0x00d458UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL6_EN_K2_E5                                                 (0x1<<0) // Enables the digital deglitching filter.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL6_EN_K2_E5_SHIFT                                           0
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2765_K2_E5                                              0x00d480UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2765_RESERVEDFIELD3548_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2765_RESERVEDFIELD3548_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2766_K2_E5                                              0x00d484UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2767_K2_E5                                              0x00d488UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2768_K2_E5                                              0x00d48cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2769_K2_E5                                              0x00d490UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2769_RESERVEDFIELD3552_K2_E5                          (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2769_RESERVEDFIELD3552_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_OVERRIDE_CTRL0_K2_E5                                                    0x00d4c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN_K2_E5                                         (0x1<<0) // Override enable for the LOS output of the digital filtering logic.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE_K2_E5                                      (0x1<<4) // Override value for the LOS output of the digital filtering logic.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE_K2_E5_SHIFT                                4
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2770_K2_E5                                              0x00d4c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2770_RESERVEDFIELD3553_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2770_RESERVEDFIELD3553_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2770_RESERVEDFIELD3554_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2770_RESERVEDFIELD3554_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2771_K2_E5                                              0x00d4c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2771_RESERVEDFIELD3555_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2771_RESERVEDFIELD3555_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2771_RESERVEDFIELD3556_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2771_RESERVEDFIELD3556_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2772_K2_E5                                              0x00d4ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2772_RESERVEDFIELD3557_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2772_RESERVEDFIELD3557_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2772_RESERVEDFIELD3558_K2_E5                          (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2772_RESERVEDFIELD3558_K2_E5_SHIFT                    6
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2773_K2_E5                                              0x00d500UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2773_RESERVEDFIELD3559_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2773_RESERVEDFIELD3559_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2773_RESERVEDFIELD3560_K2_E5                          (0x7<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2773_RESERVEDFIELD3560_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2773_RESERVEDFIELD3561_K2_E5                          (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2773_RESERVEDFIELD3561_K2_E5_SHIFT                    4
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2774_K2_E5                                              0x00d504UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2774_RESERVEDFIELD3562_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2774_RESERVEDFIELD3562_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2774_RESERVEDFIELD3563_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2774_RESERVEDFIELD3563_K2_E5_SHIFT                    1
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2774_RESERVEDFIELD3564_K2_E5                          (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2774_RESERVEDFIELD3564_K2_E5_SHIFT                    2
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2774_RESERVEDFIELD3565_K2_E5                          (0xf<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2774_RESERVEDFIELD3565_K2_E5_SHIFT                    3
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2775_K2_E5                                              0x00d508UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2776_K2_E5                                              0x00d50cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2777_K2_E5                                              0x00d518UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2777_RESERVEDFIELD3568_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2777_RESERVEDFIELD3568_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2778_K2_E5                                              0x00d544UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2778_RESERVEDFIELD3569_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2778_RESERVEDFIELD3569_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2778_RESERVEDFIELD3570_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2778_RESERVEDFIELD3570_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2779_K2_E5                                              0x00d564UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2779_RESERVEDFIELD3571_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2779_RESERVEDFIELD3571_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2780_K2_E5                                              0x00d580UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2780_RESERVEDFIELD3572_K2_E5                          (0x3f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2780_RESERVEDFIELD3572_K2_E5_SHIFT                    0
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2781_K2_E5                                              0x00d5c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2781_RESERVEDFIELD3573_K2_E5                          (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2781_RESERVEDFIELD3573_K2_E5_SHIFT                    0
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2781_RESERVEDFIELD3574_K2_E5                          (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2781_RESERVEDFIELD3574_K2_E5_SHIFT                    1
+#define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_K2_E5                                                           0x00d5c4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_LOS_READY_K2_E5                                               (0x1<<0) // Indicates that digital and analog Rx LOS blocks are in LOS mode.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_LOS_READY_K2_E5_SHIFT                                         0
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_RESERVEDFIELD3575_K2_E5                                       (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_RESERVEDFIELD3575_K2_E5_SHIFT                                 1
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_LOS_K2_E5                                                     (0x1<<2) // The filtered LOS signal value.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_LOS_K2_E5_SHIFT                                               2
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_LOS_RAW_K2_E5                                                 (0x1<<3) // The unfiltered LOS signal value.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_LOS_RAW_K2_E5_SHIFT                                           3
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_LOS_NO_EII_K2_E5                                              (0x1<<4) // The filtered LOS signal value before EII override logic.
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_LOS_NO_EII_K2_E5_SHIFT                                        4
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_RESERVEDFIELD3576_K2_E5                                       (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_RESERVEDFIELD3576_K2_E5_SHIFT                                 5
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2782_K2_E5                                                  0x00d600UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2782_RESERVEDFIELD3577_K2_E5                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2782_RESERVEDFIELD3577_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2783_K2_E5                                                  0x00d604UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2783_RESERVEDFIELD3578_K2_E5                              (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2783_RESERVEDFIELD3578_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2784_K2_E5                                                  0x00d608UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2785_K2_E5                                                  0x00d60cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2785_RESERVEDFIELD3580_K2_E5                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2785_RESERVEDFIELD3580_K2_E5_SHIFT                        0
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2785_RESERVEDFIELD3581_K2_E5                              (0xf<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2785_RESERVEDFIELD3581_K2_E5_SHIFT                        1
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2786_K2_E5                                                  0x00d640UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2787_K2_E5                                                  0x00d644UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2787_RESERVEDFIELD3583_K2_E5                              (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2787_RESERVEDFIELD3583_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2788_K2_E5                                                  0x00d648UL //Access:R    DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2789_K2_E5                                                  0x00d64cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2789_RESERVEDFIELD3585_K2_E5                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2789_RESERVEDFIELD3585_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2790_K2_E5                                                  0x00d680UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2790_RESERVEDFIELD3586_K2_E5                              (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2790_RESERVEDFIELD3586_K2_E5_SHIFT                        0
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2790_RESERVEDFIELD3587_K2_E5                              (0xf<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2790_RESERVEDFIELD3587_K2_E5_SHIFT                        2
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2791_K2_E5                                                  0x00d684UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2792_K2_E5                                                  0x00d688UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2792_RESERVEDFIELD3589_K2_E5                              (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2792_RESERVEDFIELD3589_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2793_K2_E5                                                  0x00d68cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2794_K2_E5                                                  0x00d690UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2794_RESERVEDFIELD3591_K2_E5                              (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2794_RESERVEDFIELD3591_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2795_K2_E5                                                  0x00d694UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2796_K2_E5                                                  0x00d698UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2796_RESERVEDFIELD3593_K2_E5                              (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2796_RESERVEDFIELD3593_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2797_K2_E5                                                  0x00d6c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2797_RESERVEDFIELD3594_K2_E5                              (0x1f<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2797_RESERVEDFIELD3594_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2798_K2_E5                                                  0x00d6c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2798_RESERVEDFIELD3595_K2_E5                              (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2798_RESERVEDFIELD3595_K2_E5_SHIFT                        0
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2798_RESERVEDFIELD3596_K2_E5                              (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2798_RESERVEDFIELD3596_K2_E5_SHIFT                        4
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2799_K2_E5                                                  0x00d6c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2799_RESERVEDFIELD3597_K2_E5                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2799_RESERVEDFIELD3597_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2800_K2_E5                                                  0x00d700UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2800_RESERVEDFIELD3598_K2_E5                              (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2800_RESERVEDFIELD3598_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2801_K2_E5                                                  0x00d704UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2802_K2_E5                                                  0x00d708UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2803_K2_E5                                                  0x00d70cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2804_K2_E5                                                  0x00d710UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2805_K2_E5                                                  0x00d714UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2806_K2_E5                                                  0x00d718UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2807_K2_E5                                                  0x00d71cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2808_K2_E5                                                  0x00d720UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2808_RESERVEDFIELD3606_K2_E5                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2808_RESERVEDFIELD3606_K2_E5_SHIFT                        0
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2809_K2_E5                                                  0x00d740UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2809_RESERVEDFIELD3607_K2_E5                              (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2809_RESERVEDFIELD3607_K2_E5_SHIFT                        0
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2809_RESERVEDFIELD3608_K2_E5                              (0xf<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2809_RESERVEDFIELD3608_K2_E5_SHIFT                        1
+#define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2810_K2_E5                                                  0x00d744UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_BIST_TX_CTRL_K2_E5                                                                 0x00d800UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_BIST_TX_CTRL_EN_K2_E5                                                            (0x1<<0) // Enables BIST Tx data generation.
+  #define PHY_NW_IP_REG_LN3_BIST_TX_CTRL_EN_K2_E5_SHIFT                                                      0
+  #define PHY_NW_IP_REG_LN3_BIST_TX_CTRL_PATTERN_SEL_K2_E5                                                   (0xf<<1) // Selects the pattern to transmitted: 0x1  PRBS 0xC1 0x2  PRBS 0x221 0x3  PRBS 0xA01 0x4  PRBS 0xC001 0x5  PRBS 0x840001 0x6  PRBS 0x90000001 0x7  User defined pattern UDP 0x9  MAC Tx data
+  #define PHY_NW_IP_REG_LN3_BIST_TX_CTRL_PATTERN_SEL_K2_E5_SHIFT                                             1
+#define PHY_NW_IP_REG_LN3_BIST_TX_RESERVEDREGISTER2811_K2_E5                                                 0x00d804UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_BIST_TX_RESERVEDREGISTER2812_K2_E5                                                 0x00d808UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_BIST_TX_RESERVEDREGISTER2813_K2_E5                                                 0x00d80cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_BIST_TX_RESERVEDREGISTER2814_K2_E5                                                 0x00d810UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_BIST_TX_BER_CTRL0_K2_E5                                                            0x00d818UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_BIST_TX_BER_CTRL0_MODE_K2_E5                                                     (0x3<<0) // Controls what type of error injection is used: 0x0  None 0x1  Single cycle error 0x2  Timer based
+  #define PHY_NW_IP_REG_LN3_BIST_TX_BER_CTRL0_MODE_K2_E5_SHIFT                                               0
+#define PHY_NW_IP_REG_LN3_BIST_TX_BER_CTRL1_K2_E5                                                            0x00d81cUL //Access:RW   DataWidth:0x8    // Number of cycles between single bit-error injection
+#define PHY_NW_IP_REG_LN3_BIST_TX_BER_CTRL2_K2_E5                                                            0x00d820UL //Access:RW   DataWidth:0x8    // Number of cycles between single bit-error injection
+#define PHY_NW_IP_REG_LN3_BIST_TX_BER_CTRL3_K2_E5                                                            0x00d824UL //Access:RW   DataWidth:0x8    // Sets the Tx data bits to be flipped.
+#define PHY_NW_IP_REG_LN3_BIST_TX_BER_CTRL4_K2_E5                                                            0x00d828UL //Access:RW   DataWidth:0x8    // Sets the Tx data bits to be flipped.
+#define PHY_NW_IP_REG_LN3_BIST_TX_BER_CTRL5_K2_E5                                                            0x00d82cUL //Access:RW   DataWidth:0x8    // Sets the Tx data bits to be flipped.
+#define PHY_NW_IP_REG_LN3_BIST_TX_BER_CTRL6_K2_E5                                                            0x00d830UL //Access:RW   DataWidth:0x8    // Sets the Tx data bits to be flipped.
+#define PHY_NW_IP_REG_LN3_BIST_TX_BER_CTRL7_K2_E5                                                            0x00d834UL //Access:RW   DataWidth:0x8    // Sets the Tx data bits to be flipped.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_SHIFT_AMOUNT_K2_E5                                                     0x00d880UL //Access:RW   DataWidth:0x8    // Determines the length of the UDP.  Must be set to d160 modulus udp_length.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_7_0_K2_E5                                                              0x00d890UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_15_8_K2_E5                                                             0x00d894UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_23_16_K2_E5                                                            0x00d898UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_31_24_K2_E5                                                            0x00d89cUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_39_32_K2_E5                                                            0x00d8a0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_47_40_K2_E5                                                            0x00d8a4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_55_48_K2_E5                                                            0x00d8a8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_63_56_K2_E5                                                            0x00d8acUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_71_64_K2_E5                                                            0x00d8b0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_79_72_K2_E5                                                            0x00d8b4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_87_80_K2_E5                                                            0x00d8b8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_95_88_K2_E5                                                            0x00d8bcUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_103_96_K2_E5                                                           0x00d8c0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_111_104_K2_E5                                                          0x00d8c4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_119_112_K2_E5                                                          0x00d8c8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_127_120_K2_E5                                                          0x00d8ccUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_135_128_K2_E5                                                          0x00d8d0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_143_136_K2_E5                                                          0x00d8d4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_151_144_K2_E5                                                          0x00d8d8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_159_152_K2_E5                                                          0x00d8dcUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_167_160_K2_E5                                                          0x00d8e0UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_175_168_K2_E5                                                          0x00d8e4UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_183_176_K2_E5                                                          0x00d8e8UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_191_184_K2_E5                                                          0x00d8ecUL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN3_BIST_TX_UDP_199_192_K2_E5                                                          0x00d8f0UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_K2_E5                                                                 0x00da00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_EN_K2_E5                                                            (0x1<<0) // Enables BIST Rx data checking.
+  #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_EN_K2_E5_SHIFT                                                      0
+  #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_PATTERN_SEL_K2_E5                                                   (0xf<<1) // Selects the pattern to search for: 0x1  PRBS 0xC1 0x2  PRBS 0x221 0x3  PRBS 0xA01 0x4  PRBS 0xC001 0x5  PRBS 0x840001 0x6  PRBS 0x90000001 0x7  User defined pattern UDP 0x8  Auto-detect
+  #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_PATTERN_SEL_K2_E5_SHIFT                                             1
+  #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_CLEAR_BER_K2_E5                                                     (0x1<<5) // Clears the bit error counter.
+  #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_CLEAR_BER_K2_E5_SHIFT                                               5
+  #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_STOP_ERROR_COUNT_K2_E5                                              (0x1<<6) // Stops the error count from incrementing.  Can be used to read back the BER data coherently.
+  #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_STOP_ERROR_COUNT_K2_E5_SHIFT                                        6
+  #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_FORCE_LFSR_WITH_RXDATA_K2_E5                                        (0x1<<7) // Forces the PRBS LFSR to reseed with Rx data every cycle.  This will cause the bit error counter to be inaccurate.
+  #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_FORCE_LFSR_WITH_RXDATA_K2_E5_SHIFT                                  7
+#define PHY_NW_IP_REG_LN3_BIST_RX_STATUS_K2_E5                                                               0x00da10UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_BIST_RX_STATUS_STATE_K2_E5                                                       (0x7<<0) // State of the BIST checker: 0x0  Off 0x1  Searching for pattern 0x2  Waiting for pattern lock conditions 0x3  Pattern lock acquired 0x4  Pattern lock lost
+  #define PHY_NW_IP_REG_LN3_BIST_RX_STATUS_STATE_K2_E5_SHIFT                                                 0
+  #define PHY_NW_IP_REG_LN3_BIST_RX_STATUS_PATTERN_DET_K2_E5                                                 (0xf<<3) // Indicates the pattern  detected: 0x0  No pattern detected 0x1  PRBS 0xC1 0x2  PRBS 0x221 0x3  PRBS 0xA01 0x4  PRBS 0xC001 0x5  PRBS 0x840001 0x6  PRBS 0x90000001 0x7  User defined pattern UDP
+  #define PHY_NW_IP_REG_LN3_BIST_RX_STATUS_PATTERN_DET_K2_E5_SHIFT                                           3
+#define PHY_NW_IP_REG_LN3_BIST_RX_BER_STATUS0_K2_E5                                                          0x00da20UL //Access:R    DataWidth:0x8    // Number of bit errors.
+#define PHY_NW_IP_REG_LN3_BIST_RX_BER_STATUS1_K2_E5                                                          0x00da24UL //Access:R    DataWidth:0x8    // Number of bit errors.
+#define PHY_NW_IP_REG_LN3_BIST_RX_BER_STATUS2_K2_E5                                                          0x00da28UL //Access:R    DataWidth:0x8    // Number of bit errors.
+#define PHY_NW_IP_REG_LN3_BIST_RX_BER_STATUS4_K2_E5                                                          0x00da30UL //Access:R    DataWidth:0x8    // Number of cycles that errors have been counted.
+#define PHY_NW_IP_REG_LN3_BIST_RX_BER_STATUS5_K2_E5                                                          0x00da34UL //Access:R    DataWidth:0x8    // Number of cycles that errors have been counted.
+#define PHY_NW_IP_REG_LN3_BIST_RX_BER_STATUS6_K2_E5                                                          0x00da38UL //Access:R    DataWidth:0x8    // Number of cycles that errors have been counted.
+#define PHY_NW_IP_REG_LN3_BIST_RX_LOCK_CTRL0_K2_E5                                                           0x00da50UL //Access:RW   DataWidth:0x8    // Size of error sampling window to trigger pattern lock.
+#define PHY_NW_IP_REG_LN3_BIST_RX_LOCK_CTRL1_K2_E5                                                           0x00da54UL //Access:RW   DataWidth:0x8    // Size of error sampling window to trigger pattern lock.
+#define PHY_NW_IP_REG_LN3_BIST_RX_LOCK_CTRL2_K2_E5                                                           0x00da58UL //Access:RW   DataWidth:0x8    // Maximum number of errors allowed to trigger pattern lock.
+#define PHY_NW_IP_REG_LN3_BIST_RX_LOCK_CTRL3_K2_E5                                                           0x00da5cUL //Access:RW   DataWidth:0x8    // Maximum number of errors allowed to trigger pattern lock.
+#define PHY_NW_IP_REG_LN3_BIST_RX_LOSS_LOCK_CTRL0_K2_E5                                                      0x00da80UL //Access:RW   DataWidth:0x8    // Size of error sampling window to trigger pattern loss-of-lock.
+#define PHY_NW_IP_REG_LN3_BIST_RX_LOSS_LOCK_CTRL1_K2_E5                                                      0x00da84UL //Access:RW   DataWidth:0x8    // Size of error sampling window to trigger pattern loss-of-lock.
+#define PHY_NW_IP_REG_LN3_BIST_RX_LOSS_LOCK_CTRL2_K2_E5                                                      0x00da88UL //Access:RW   DataWidth:0x8    // Minimum number of errors allowed to trigger pattern loss-of-lock.
+#define PHY_NW_IP_REG_LN3_BIST_RX_LOSS_LOCK_CTRL3_K2_E5                                                      0x00da8cUL //Access:RW   DataWidth:0x8    // Minimum number of errors allowed to trigger pattern loss-of-lock.
+#define PHY_NW_IP_REG_LN3_BIST_RX_LOSS_LOCK_CTRL4_K2_E5                                                      0x00da90UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_BIST_RX_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_K2_E5                                  (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
+  #define PHY_NW_IP_REG_LN3_BIST_RX_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_K2_E5_SHIFT                            0
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_SHIFT_AMOUNT_K2_E5                                                     0x00dac0UL //Access:RW   DataWidth:0x8    // Determines the length of the UDP.  Must be set to d160 modulus udp_length.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_7_0_K2_E5                                                              0x00dad0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_15_8_K2_E5                                                             0x00dad4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_23_16_K2_E5                                                            0x00dad8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_31_24_K2_E5                                                            0x00dadcUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_39_32_K2_E5                                                            0x00dae0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_47_40_K2_E5                                                            0x00dae4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_55_48_K2_E5                                                            0x00dae8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_63_56_K2_E5                                                            0x00daecUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_71_64_K2_E5                                                            0x00daf0UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_79_72_K2_E5                                                            0x00daf4UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_87_80_K2_E5                                                            0x00daf8UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_95_88_K2_E5                                                            0x00dafcUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_103_96_K2_E5                                                           0x00db00UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_111_104_K2_E5                                                          0x00db04UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_119_112_K2_E5                                                          0x00db08UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_127_120_K2_E5                                                          0x00db0cUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_135_128_K2_E5                                                          0x00db10UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_143_136_K2_E5                                                          0x00db14UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_151_144_K2_E5                                                          0x00db18UL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_159_152_K2_E5                                                          0x00db1cUL //Access:RW   DataWidth:0x8    // User defined pattern.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_167_160_K2_E5                                                          0x00db20UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_175_168_K2_E5                                                          0x00db24UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_183_176_K2_E5                                                          0x00db28UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_191_184_K2_E5                                                          0x00db2cUL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN3_BIST_RX_UDP_199_192_K2_E5                                                          0x00db30UL //Access:RW   DataWidth:0x8    // User defined pattern extension bits.
+#define PHY_NW_IP_REG_LN3_FEATURE_RXTERM_CFG0_K2_E5                                                          0x00dc00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_RXTERM_CFG0_AC_COUPLED_K2_E5                                             (0x1<<0) // Configures AC/DC coupling of the lane 0: DC coupled 1: AC coupled
+  #define PHY_NW_IP_REG_LN3_FEATURE_RXTERM_CFG0_AC_COUPLED_K2_E5_SHIFT                                       0
+#define PHY_NW_IP_REG_LN3_FEATURE_RXCLKDIV_CFG0_K2_E5                                                        0x00dc04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_RXCLKDIV_CFG0_EN_K2_E5                                                   (0x1<<0) // Enables turning on the divided rxclk output
+  #define PHY_NW_IP_REG_LN3_FEATURE_RXCLKDIV_CFG0_EN_K2_E5_SHIFT                                             0
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2815_K2_E5                                                 0x00dc10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2815_RESERVEDFIELD3614_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2815_RESERVEDFIELD3614_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2815_RESERVEDFIELD3615_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2815_RESERVEDFIELD3615_K2_E5_SHIFT                       1
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2816_K2_E5                                                 0x00dc14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2816_RESERVEDFIELD3616_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2816_RESERVEDFIELD3616_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2816_RESERVEDFIELD3617_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2816_RESERVEDFIELD3617_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2816_RESERVEDFIELD3618_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2816_RESERVEDFIELD3618_K2_E5_SHIFT                       2
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2816_RESERVEDFIELD3619_K2_E5                             (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2816_RESERVEDFIELD3619_K2_E5_SHIFT                       3
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2816_RESERVEDFIELD3620_K2_E5                             (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2816_RESERVEDFIELD3620_K2_E5_SHIFT                       4
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2816_RESERVEDFIELD3621_K2_E5                             (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2816_RESERVEDFIELD3621_K2_E5_SHIFT                       5
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2817_K2_E5                                                 0x00dc18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2817_RESERVEDFIELD3622_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2817_RESERVEDFIELD3622_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2817_RESERVEDFIELD3623_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2817_RESERVEDFIELD3623_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2817_RESERVEDFIELD3624_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2817_RESERVEDFIELD3624_K2_E5_SHIFT                       2
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2817_RESERVEDFIELD3625_K2_E5                             (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2817_RESERVEDFIELD3625_K2_E5_SHIFT                       3
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_K2_E5                                                 0x00dc1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3626_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3626_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3627_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3627_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3628_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3628_K2_E5_SHIFT                       2
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3629_K2_E5                             (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3629_K2_E5_SHIFT                       3
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3630_K2_E5                             (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3630_K2_E5_SHIFT                       4
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3631_K2_E5                             (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3631_K2_E5_SHIFT                       5
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3632_K2_E5                             (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3632_K2_E5_SHIFT                       6
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3633_K2_E5                             (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3633_K2_E5_SHIFT                       7
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2819_K2_E5                                                 0x00dc20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2819_RESERVEDFIELD3634_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2819_RESERVEDFIELD3634_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2819_RESERVEDFIELD3635_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2819_RESERVEDFIELD3635_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2819_RESERVEDFIELD3636_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2819_RESERVEDFIELD3636_K2_E5_SHIFT                       2
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2819_RESERVEDFIELD3637_K2_E5                             (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2819_RESERVEDFIELD3637_K2_E5_SHIFT                       3
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2819_RESERVEDFIELD3638_K2_E5                             (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2819_RESERVEDFIELD3638_K2_E5_SHIFT                       4
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2820_K2_E5                                                 0x00dc24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2820_RESERVEDFIELD3639_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2820_RESERVEDFIELD3639_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2820_RESERVEDFIELD3640_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2820_RESERVEDFIELD3640_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2820_RESERVEDFIELD3641_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2820_RESERVEDFIELD3641_K2_E5_SHIFT                       2
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2821_K2_E5                                                 0x00dc40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2821_RESERVEDFIELD3642_K2_E5                             (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2821_RESERVEDFIELD3642_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2822_K2_E5                                                 0x00dc44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2822_RESERVEDFIELD3643_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2822_RESERVEDFIELD3643_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2823_K2_E5                                                 0x00dc48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2823_RESERVEDFIELD3644_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2823_RESERVEDFIELD3644_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2823_RESERVEDFIELD3645_K2_E5                             (0x7f<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2823_RESERVEDFIELD3645_K2_E5_SHIFT                       1
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2824_K2_E5                                                 0x00dc4cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2825_K2_E5                                                 0x00dc50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2825_RESERVEDFIELD3647_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2825_RESERVEDFIELD3647_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2825_RESERVEDFIELD3648_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2825_RESERVEDFIELD3648_K2_E5_SHIFT                       1
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2826_K2_E5                                                 0x00dc54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2826_RESERVEDFIELD3649_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2826_RESERVEDFIELD3649_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2826_RESERVEDFIELD3650_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2826_RESERVEDFIELD3650_K2_E5_SHIFT                       1
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2827_K2_E5                                                 0x00dc58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2827_RESERVEDFIELD3651_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2827_RESERVEDFIELD3651_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2827_RESERVEDFIELD3652_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2827_RESERVEDFIELD3652_K2_E5_SHIFT                       1
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2828_K2_E5                                                 0x00dc80UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2828_RESERVEDFIELD3653_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2828_RESERVEDFIELD3653_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_CFG_K2_E5                                                       0x00dc84UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT0_K2_E5                                  (0x3<<0) // How many times to repeat CTLE adaptation sequence for initial adaptation set 0
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT0_K2_E5_SHIFT                            0
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT1_K2_E5                                  (0x3<<2) // How many times to repeat CTLE adaptation sequence for initial adaptation set 1
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT1_K2_E5_SHIFT                            2
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_CFG_RESERVEDFIELD3654_K2_E5                                   (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_CFG_RESERVEDFIELD3654_K2_E5_SHIFT                             4
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_CFG_RESERVEDFIELD3655_K2_E5                                   (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_CFG_RESERVEDFIELD3655_K2_E5_SHIFT                             6
+#define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_AGC_CFG_K2_E5                                                   0x00dc88UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN_K2_E5                                        (0x1<<0) // Enables AGC threshold adaptation for initial adaptation
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_AGC_CFG_RESERVEDFIELD3656_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_AGC_CFG_RESERVEDFIELD3656_K2_E5_SHIFT                         2
+#define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_APG_MAP_CFG_K2_E5                                               0x00dc8cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN_K2_E5                                    (0x1<<0) // Enables mapping GN_APG setting from AGC threshold for initial adaptation
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_APG_MAP_CFG_RESERVEDFIELD3657_K2_E5                           (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_APG_MAP_CFG_RESERVEDFIELD3657_K2_E5_SHIFT                     2
+#define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_LFG_CFG_K2_E5                                                   0x00dc90UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL_K2_E5                                       (0x3<<0) // Selects the CTLE EQ LFG adaptation method for initial adaptation set 0 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loop 0x3: Method 3: GN_APG and EQ_LFG combined closed-loop
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL_K2_E5                                       (0x3<<2) // Selects the CTLE EQ LFG adaptation method for initial adaptation set 1 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loop 0x3: Method 3: GN_APG and EQ_LFG combined closed-loop
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL_K2_E5_SHIFT                                 2
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_LFG_CFG_RESERVEDFIELD3658_K2_E5                               (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_LFG_CFG_RESERVEDFIELD3658_K2_E5_SHIFT                         4
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_LFG_CFG_RESERVEDFIELD3659_K2_E5                               (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_LFG_CFG_RESERVEDFIELD3659_K2_E5_SHIFT                         6
+#define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_K2_E5                                                  0x00dc94UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN_K2_E5                                  (0x1<<0) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 0
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN_K2_E5_SHIFT                            0
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN_K2_E5                                  (0x1<<1) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 0
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN_K2_E5_SHIFT                            1
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN_K2_E5                                  (0x1<<2) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 1
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN_K2_E5_SHIFT                            2
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN_K2_E5                                  (0x1<<3) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 1
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN_K2_E5_SHIFT                            3
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD3660_K2_E5                              (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD3660_K2_E5_SHIFT                        4
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD3661_K2_E5                              (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD3661_K2_E5_SHIFT                        5
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD3662_K2_E5                              (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD3662_K2_E5_SHIFT                        6
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD3663_K2_E5                              (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD3663_K2_E5_SHIFT                        7
+#define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG1_K2_E5                                                  0x00dc98UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL_K2_E5                               (0x3<<0) // Selects which HFG result to use for the initial adaptation set 0 0x0: Edge Based 0x1: Data Based 0x2: Average of Edge & Data result 0x3: Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL_K2_E5_SHIFT                         0
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL_K2_E5                               (0x3<<2) // Selects which HFG result to use for the initial adaptation set 1 0x0: Edge Based 0x1: Data Based 0x2: Average of Edge & Data result 0x3: Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG1_RESERVEDFIELD3664_K2_E5                              (0x3<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG1_RESERVEDFIELD3664_K2_E5_SHIFT                        4
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG1_RESERVEDFIELD3665_K2_E5                              (0x3<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG1_RESERVEDFIELD3665_K2_E5_SHIFT                        6
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2829_K2_E5                                                 0x00dc9cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2829_RESERVEDFIELD3666_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2829_RESERVEDFIELD3666_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_MBS_CFG_K2_E5                                                   0x00dca0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_K2_E5                                        (0x1<<0) // Enables CTLE midband shaping adaptation for initial adaptation set 0
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN_K2_E5                                        (0x1<<1) // Enables CTLE midband shaping adaptation for initial adaptation set 1
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN_K2_E5_SHIFT                                  1
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD3667_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD3667_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD3668_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD3668_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_K2_E5                                                 0x00dca4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3669_K2_E5                             (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3669_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3670_K2_E5                             (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3670_K2_E5_SHIFT                       1
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3671_K2_E5                             (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3671_K2_E5_SHIFT                       2
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3672_K2_E5                             (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3672_K2_E5_SHIFT                       3
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3673_K2_E5                             (0x1<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3673_K2_E5_SHIFT                       4
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3674_K2_E5                             (0x1<<5) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3674_K2_E5_SHIFT                       5
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3675_K2_E5                             (0x1<<6) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3675_K2_E5_SHIFT                       6
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3676_K2_E5                             (0x1<<7) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3676_K2_E5_SHIFT                       7
+#define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_K2_E5                                                              0x00dcc0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP1_EN_K2_E5                                                    (0x1<<0) // Enables DFE Tap 1. Tap1 will not be powered up if it is not enabled
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP1_EN_K2_E5_SHIFT                                              0
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP2_EN_K2_E5                                                    (0x1<<1) // Enables DFE Tap 2. Tap2 will not be powered up if it is not enabled
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP2_EN_K2_E5_SHIFT                                              1
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP3_EN_K2_E5                                                    (0x1<<2) // Enables DFE Tap 3. Tap3 will not be powered up if it is not enabled
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP3_EN_K2_E5_SHIFT                                              2
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP4_EN_K2_E5                                                    (0x1<<3) // Enables DFE Tap 4. Tap4 will not be powered up if it is not enabled
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP4_EN_K2_E5_SHIFT                                              3
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP5_EN_K2_E5                                                    (0x1<<4) // Enables DFE Tap 5. Tap5 will not be powered up if it is not enabled
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP5_EN_K2_E5_SHIFT                                              4
+#define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_CFG_K2_E5                                                        0x00dcc4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_CFG_METHOD_SEL_K2_E5                                           (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Based Zero Forcing
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_CFG_METHOD_SEL_K2_E5_SHIFT                                     0
+#define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP1_CFG_K2_E5                                                   0x00dcc8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN_K2_E5                                    (0x1<<0) // Enables initial adaptations for Tap 1
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD3677_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD3677_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD3678_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD3678_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD3679_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD3679_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP2_CFG_K2_E5                                                   0x00dcccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN_K2_E5                                    (0x1<<0) // Enables initial adaptations for Tap 2
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD3680_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD3680_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD3681_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD3681_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD3682_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD3682_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP3_CFG_K2_E5                                                   0x00dcd0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN_K2_E5                                    (0x1<<0) // Enables initial adaptations for Tap 3
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD3683_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD3683_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD3684_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD3684_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD3685_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD3685_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP4_CFG_K2_E5                                                   0x00dcd4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN_K2_E5                                    (0x1<<0) // Enables initial adaptations for Tap 4
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD3686_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD3686_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD3687_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD3687_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD3688_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD3688_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP5_CFG_K2_E5                                                   0x00dcd8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN_K2_E5                                    (0x1<<0) // Enables initial adaptations for Tap 5
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN_K2_E5_SHIFT                              0
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD3689_K2_E5                               (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD3689_K2_E5_SHIFT                         1
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD3690_K2_E5                               (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD3690_K2_E5_SHIFT                         2
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD3691_K2_E5                               (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD3691_K2_E5_SHIFT                         3
+#define PHY_NW_IP_REG_LN3_FEATURE_ADAPT_CONT_CFG0_K2_E5                                                      0x00dce0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_ADAPT_CONT_CFG0_EN_K2_E5                                                 (0x1<<0) // Enables continuous background adaptation
+  #define PHY_NW_IP_REG_LN3_FEATURE_ADAPT_CONT_CFG0_EN_K2_E5_SHIFT                                           0
+  #define PHY_NW_IP_REG_LN3_FEATURE_ADAPT_CONT_CFG0_RESERVEDFIELD3692_K2_E5                                  (0x1<<1) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_ADAPT_CONT_CFG0_RESERVEDFIELD3692_K2_E5_SHIFT                            1
+#define PHY_NW_IP_REG_LN3_FEATURE_ADAPT_CONT_CFG1_K2_E5                                                      0x00dce4UL //Access:RW   DataWidth:0x8    // How often in ms to run continuous adaptations 1ms to ~279 mins
+#define PHY_NW_IP_REG_LN3_FEATURE_ADAPT_CONT_CFG2_K2_E5                                                      0x00dce8UL //Access:RW   DataWidth:0x8    // How often in ms to run continuous adaptations 1ms to ~279 mins
+#define PHY_NW_IP_REG_LN3_FEATURE_ADAPT_CONT_CFG3_K2_E5                                                      0x00dcecUL //Access:RW   DataWidth:0x8    // How often in ms to run continuous adaptations 1ms to ~279 mins
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2831_K2_E5                                                 0x00dcf0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2832_K2_E5                                                 0x00dcf4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2833_K2_E5                                                 0x00dcf8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2834_K2_E5                                                 0x00dcfcUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2835_K2_E5                                                 0x00dd00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2835_RESERVEDFIELD3697_K2_E5                             (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2835_RESERVEDFIELD3697_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2835_RESERVEDFIELD3698_K2_E5                             (0x3<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2835_RESERVEDFIELD3698_K2_E5_SHIFT                       2
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2836_K2_E5                                                 0x00dd04UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2837_K2_E5                                                 0x00dd08UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2838_K2_E5                                                 0x00dd0cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2839_K2_E5                                                 0x00dd10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2839_RESERVEDFIELD3702_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2839_RESERVEDFIELD3702_K2_E5_SHIFT                       0
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2840_K2_E5                                                 0x00dd14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2840_RESERVEDFIELD3703_K2_E5                             (0x7<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2840_RESERVEDFIELD3703_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2840_RESERVEDFIELD3704_K2_E5                             (0x1f<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2840_RESERVEDFIELD3704_K2_E5_SHIFT                       3
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2841_K2_E5                                                 0x00dd18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2841_RESERVEDFIELD3705_K2_E5                             (0x3<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2841_RESERVEDFIELD3705_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2841_RESERVEDFIELD3706_K2_E5                             (0x1f<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2841_RESERVEDFIELD3706_K2_E5_SHIFT                       2
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2842_K2_E5                                                 0x00dd1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2842_RESERVEDFIELD3707_K2_E5                             (0xf<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2842_RESERVEDFIELD3707_K2_E5_SHIFT                       0
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2842_RESERVEDFIELD3708_K2_E5                             (0xf<<4) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2842_RESERVEDFIELD3708_K2_E5_SHIFT                       4
+#define PHY_NW_IP_REG_LN3_FEATURE_TEST_CFG0_K2_E5                                                            0x00dd40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_FEATURE_TEST_CFG0_RESERVEDFIELD3709_K2_E5                                        (0x1<<0) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_TEST_CFG0_RESERVEDFIELD3709_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN3_FEATURE_TEST_CFG0_RX_CTRL_DIS_K2_E5                                              (0x1<<1) // Disables the firmware rx_ctrl MSM
+  #define PHY_NW_IP_REG_LN3_FEATURE_TEST_CFG0_RX_CTRL_DIS_K2_E5_SHIFT                                        1
+  #define PHY_NW_IP_REG_LN3_FEATURE_TEST_CFG0_RESERVEDFIELD3710_K2_E5                                        (0x1<<2) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_TEST_CFG0_RESERVEDFIELD3710_K2_E5_SHIFT                                  2
+  #define PHY_NW_IP_REG_LN3_FEATURE_TEST_CFG0_RESERVEDFIELD3711_K2_E5                                        (0x1<<3) // Reserved
+  #define PHY_NW_IP_REG_LN3_FEATURE_TEST_CFG0_RESERVEDFIELD3711_K2_E5_SHIFT                                  3
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2843_K2_E5                                                 0x00dd60UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2844_K2_E5                                                 0x00dd64UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2845_K2_E5                                                 0x00dd68UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2846_K2_E5                                                 0x00dd6cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2847_K2_E5                                                 0x00dd70UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2848_K2_E5                                                 0x00dd74UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2849_K2_E5                                                 0x00dd78UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2850_K2_E5                                                 0x00dd7cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_K2_E5                                                              0x00de00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_MR_RESTART_TRAINING_K2_E5                                        (0x1<<0) // Starts link training procedure when asserted.  This is an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_MR_RESTART_TRAINING_K2_E5_SHIFT                                  0
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_MR_TRAINING_ENABLE_K2_E5                                         (0x1<<1) // Indicates to LTSM that link training procedure should be run; otherwise procedures skip directly to signal_det assertion.  This is an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_MR_TRAINING_ENABLE_K2_E5_SHIFT                                   1
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_SIGNAL_DETECT_K2_E5                                              (0x1<<2) // Output corresponding to link training signal detect variable.  Should be set when link training has completed successfully.
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_SIGNAL_DETECT_K2_E5_SHIFT                                        2
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_CLEAR_K2_E5                                                      (0x1<<3) // Synchronous reset for LT Tx block.
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_CLEAR_K2_E5_SHIFT                                                3
+#define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL1_K2_E5                                                              0x00de04UL //Access:RW   DataWidth:0x8    // Maximum time allowed for LT procedure.  If this is exceeded then the training_fail status will assert.  This is an 802.defined variable.  Value is encoded as: 39338 * DESIRED_DELAY * 2 ^logdata_width / data_width  Should be set to 500ns for 802.3 compliant timeout.
+#define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL2_K2_E5                                                              0x00de08UL //Access:RW   DataWidth:0x8    // Same as above.
+#define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL3_K2_E5                                                              0x00de0cUL //Access:RW   DataWidth:0x8    // Number of additional frames to send after both receivers have been trained and are ready.  This is an 802.3 defined variable.  Should be set between 100 and 300 for 802.3 compliance.
+#define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL4_K2_E5                                                              0x00de10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL4_WAIT_TIME_8_K2_E5                                                (0x1<<0) // Same as above.
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL4_WAIT_TIME_8_K2_E5_SHIFT                                          0
+#define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL5_K2_E5                                                              0x00de14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL5_FRAME_LOCK_K2_E5                                                 (0x1<<0) // Input to LTSM that receiver has acquired frame lock.  This value should be taken from the corresponding LT Rx register.  This  an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL5_FRAME_LOCK_K2_E5_SHIFT                                           0
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL5_RX_TRAINED_K2_E5                                                 (0x1<<1) // Input to LTSM indicating that the local receiver has completed training.  This is an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL5_RX_TRAINED_K2_E5_SHIFT                                           1
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL5_REMOTE_RX_READY_K2_E5                                            (0x1<<2) // Input to LTSM indicating that the remote receiver is trained and ready.  This value should be taken from the corresponding LT Rx registers.  This is an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL5_REMOTE_RX_READY_K2_E5_SHIFT                                      2
+#define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_K2_E5                                                             0x00de40UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_TRAINING_FAIL_K2_E5                                             (0x1<<0) // Output from LTSM indicating that link training has failed.  This is an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_TRAINING_FAIL_K2_E5_SHIFT                                       0
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_TRAINING_K2_E5                                                  (0x1<<1) // Output from LTSM indicating that link training is in progress.  This is an 802.3 defined variable.
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_TRAINING_K2_E5_SHIFT                                            1
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_SIGNAL_DETECT_K2_E5                                             (0x1<<2) // Output from LTSM indicating that link training is complete and successful.  This is an 802.3 defined variable.  This value is only visible internally, and is not the signal_det value driven to PHY top-level.
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_SIGNAL_DETECT_K2_E5_SHIFT                                       2
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_FSM_LOCAL_RX_READY_K2_E5                                        (0x1<<4) // Output from LSM corresponding to 802.3 defined local_rx_ready variable. After this is asserted the corresponding frame status report field should be set.
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_FSM_LOCAL_RX_READY_K2_E5_SHIFT                                  4
+#define PHY_NW_IP_REG_LN3_LT_TX_PRBS_CTRL0_K2_E5                                                             0x00de4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LT_TX_PRBS_CTRL0_POLYNOMIAL_K2_E5                                                (0x7<<0) // Selects between CL72 and CL93 PRBS pattern. 0  CL72 1 + x^9 +x^11 1  CL93 1 + x^5 + x^6 + x^10 + x^11 2  CL93 1 + x^5 + x^6 + x^9 + x^11 3  CL93 1 + x^4 + x^6 + x^8 + x^11 4  CL93 1 + x^4 + x^6 + x^7 + x^11
+  #define PHY_NW_IP_REG_LN3_LT_TX_PRBS_CTRL0_POLYNOMIAL_K2_E5_SHIFT                                          0
+#define PHY_NW_IP_REG_LN3_LT_TX_PRBS_CTRL1_K2_E5                                                             0x00de50UL //Access:RW   DataWidth:0x8    // Initial PRBS LFSR seed.  This needs to be set according to the requirements in 802.3 CL72 or CL93 depending on the type of link training and lane bonding being performed.
+#define PHY_NW_IP_REG_LN3_LT_TX_PRBS_CTRL2_K2_E5                                                             0x00de54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LT_TX_PRBS_CTRL2_SEED_10_8_K2_E5                                                 (0x7<<0) // Same as above.
+  #define PHY_NW_IP_REG_LN3_LT_TX_PRBS_CTRL2_SEED_10_8_K2_E5_SHIFT                                           0
+#define PHY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL_K2_E5                                                0x00de80UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL_C_P1_K2_E5                                         (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00  hold 2'b01  increment 2'b10  decrement 2'b11  reserved
+  #define PHY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL_C_P1_K2_E5_SHIFT                                   0
+  #define PHY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL_C_0_K2_E5                                          (0x3<<2) // Coefficient update request field for cursor tap.
+  #define PHY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL_C_0_K2_E5_SHIFT                                    2
+  #define PHY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL_C_M1_K2_E5                                         (0x3<<4) // Coefficient update request field for pre-cursor tap.
+  #define PHY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL_C_M1_K2_E5_SHIFT                                   4
+  #define PHY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL_INITIALIZE_K2_E5                                   (0x1<<6) // Coefficient update initialize field.
+  #define PHY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL_INITIALIZE_K2_E5_SHIFT                             6
+  #define PHY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL_PRESET_K2_E5                                       (0x1<<7) // Coefficient update preset field.
+  #define PHY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL_PRESET_K2_E5_SHIFT                                 7
+#define PHY_NW_IP_REG_LN3_LT_TX_STATUS_REPORT_CTRL_K2_E5                                                     0x00de88UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LT_TX_STATUS_REPORT_CTRL_C_P1_K2_E5                                              (0x3<<0) // Status report field for post-cursor tap. 2'b00  not updated 2'b01  minimum 2'b10  updated 2'b11  maximum
+  #define PHY_NW_IP_REG_LN3_LT_TX_STATUS_REPORT_CTRL_C_P1_K2_E5_SHIFT                                        0
+  #define PHY_NW_IP_REG_LN3_LT_TX_STATUS_REPORT_CTRL_C_0_K2_E5                                               (0x3<<2) // Status report field for cursor tap.
+  #define PHY_NW_IP_REG_LN3_LT_TX_STATUS_REPORT_CTRL_C_0_K2_E5_SHIFT                                         2
+  #define PHY_NW_IP_REG_LN3_LT_TX_STATUS_REPORT_CTRL_C_M1_K2_E5                                              (0x3<<4) // Status report field for pre-cursor tap.
+  #define PHY_NW_IP_REG_LN3_LT_TX_STATUS_REPORT_CTRL_C_M1_K2_E5_SHIFT                                        4
+  #define PHY_NW_IP_REG_LN3_LT_TX_STATUS_REPORT_CTRL_LOCAL_RX_READY_K2_E5                                    (0x1<<6) // Status report field to indicate local receiver is ready.  Should be set based on LTSM output of corresponding variable.
+  #define PHY_NW_IP_REG_LN3_LT_TX_STATUS_REPORT_CTRL_LOCAL_RX_READY_K2_E5_SHIFT                              6
+#define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS0_K2_E5                                                      0x00dec0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS0_CURRENT_K2_E5                                            (0x7<<0) // Current state of LTSM. 0x0  INITIALIZE 0x1  SEND_TRAINING 0x2  TRAIN_REMOTE 0x3  TRAIN_LOCAL 0x4  S7 0x5  TRAINING_FAILURE 0x6  LINK_READY 0x7  SEND_DATA
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS0_CURRENT_K2_E5_SHIFT                                      0
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS0_PREV1_K2_E5                                              (0x7<<4) // One state previous.
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS0_PREV1_K2_E5_SHIFT                                        4
+#define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS1_K2_E5                                                      0x00dec4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS1_PREV2_K2_E5                                              (0x7<<0) // Two states previous.
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS1_PREV2_K2_E5_SHIFT                                        0
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS1_PREV3_K2_E5                                              (0x7<<4) // Three states previous.
+  #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS1_PREV3_K2_E5_SHIFT                                        4
+#define PHY_NW_IP_REG_LN3_LT_RX_CTRL0_K2_E5                                                                  0x00df00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LT_RX_CTRL0_CLEAR_K2_E5                                                          (0x1<<0) // Synchronous reset for LT Rx block.
+  #define PHY_NW_IP_REG_LN3_LT_RX_CTRL0_CLEAR_K2_E5_SHIFT                                                    0
+  #define PHY_NW_IP_REG_LN3_LT_RX_CTRL0_TRAINING_K2_E5                                                       (0x1<<1) // This is the 802.3 defined training variable.  It should be set according to corresponding LTSM output.
+  #define PHY_NW_IP_REG_LN3_LT_RX_CTRL0_TRAINING_K2_E5_SHIFT                                                 1
+#define PHY_NW_IP_REG_LN3_LT_RX_PRBS_CTRL0_K2_E5                                                             0x00df08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_CTRL0_POLYNOMIAL_K2_E5                                                (0x7<<0) // Selects between CL72 and CL93 PRBS patterns. 0  CL72 1 + x^9 + x^11 1  CL93 1 + x^5 + x^6 + x^10 + x^11 2  CL93 1 + x^5 + x^6 + x^9 + x^11 3  CL93 1 + x^4 + x^6 + x^8 + x^11 4  CL93 1 + x^4 + x^6 + x^7 + x^11
+  #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_CTRL0_POLYNOMIAL_K2_E5_SHIFT                                          0
+#define PHY_NW_IP_REG_LN3_LT_RX_PRBS_CTRL1_K2_E5                                                             0x00df0cUL //Access:RW   DataWidth:0x8    // Maximum number  of PRBS bit errors allowed in single LT frame for PRBS lock to be achieved.
+#define PHY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS0_K2_E5                                                           0x00df14UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS0_UPDATE_K2_E5                                                  (0x1<<0) // Assertion indicates that PRBS status information has been updated.
+  #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS0_UPDATE_K2_E5_SHIFT                                            0
+  #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS0_LOCK_K2_E5                                                    (0x1<<1) // Indicates that a valid PRBS pattern has been detected in receiver LT frame.
+  #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS0_LOCK_K2_E5_SHIFT                                              1
+#define PHY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS1_K2_E5                                                           0x00df18UL //Access:R    DataWidth:0x8    // Number of bit errors in PRBS pattern since last lock assertion event.
+#define PHY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS2_K2_E5                                                           0x00df1cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS2_ERROR_COUNT_11_8_K2_E5                                        (0xf<<0) // Same as above.
+  #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS2_ERROR_COUNT_11_8_K2_E5_SHIFT                                  0
+#define PHY_NW_IP_REG_LN3_LT_RX_FRAME_CTRL_K2_E5                                                             0x00df40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LT_RX_FRAME_CTRL_CLEAR_COUNT_K2_E5                                               (0x1<<0) // Clears both the absolute and erroneous frame counters.
+  #define PHY_NW_IP_REG_LN3_LT_RX_FRAME_CTRL_CLEAR_COUNT_K2_E5_SHIFT                                         0
+#define PHY_NW_IP_REG_LN3_LT_RX_FRAME_STATUS0_K2_E5                                                          0x00df4cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LT_RX_FRAME_STATUS0_FRAME_LOCK_K2_E5                                             (0x1<<0) // Indicates that the receiver has locked to incoming LT frames.
+  #define PHY_NW_IP_REG_LN3_LT_RX_FRAME_STATUS0_FRAME_LOCK_K2_E5_SHIFT                                       0
+#define PHY_NW_IP_REG_LN3_LT_RX_FRAME_STATUS1_K2_E5                                                          0x00df50UL //Access:R    DataWidth:0x8    // Total number of received frames since frame lock.
+#define PHY_NW_IP_REG_LN3_LT_RX_FRAME_STATUS2_K2_E5                                                          0x00df54UL //Access:R    DataWidth:0x8    // Same as above.
+#define PHY_NW_IP_REG_LN3_LT_RX_FRAME_STATUS3_K2_E5                                                          0x00df58UL //Access:R    DataWidth:0x8    // Total number of received frames  with a PRBS, DME, or framing error since frame lock.
+#define PHY_NW_IP_REG_LN3_LT_RX_FRAME_STATUS4_K2_E5                                                          0x00df5cUL //Access:R    DataWidth:0x8    // Same as above.
+#define PHY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS_K2_E5                                              0x00df80UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS_C_P1_K2_E5                                       (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00  hold 2'b01  increment 2'b10  decrement 2'b11  reserved
+  #define PHY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS_C_P1_K2_E5_SHIFT                                 0
+  #define PHY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS_C_0_K2_E5                                        (0x3<<2) // Received coefficient update request field for cursor tap.
+  #define PHY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS_C_0_K2_E5_SHIFT                                  2
+  #define PHY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS_C_M1_K2_E5                                       (0x3<<4) // Received coefficient update request field for pre-cursor tap.
+  #define PHY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS_C_M1_K2_E5_SHIFT                                 4
+  #define PHY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS_INITIALIZE_K2_E5                                 (0x1<<6) // Received coefficient update initialize field.
+  #define PHY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS_INITIALIZE_K2_E5_SHIFT                           6
+  #define PHY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS_PRESET_K2_E5                                     (0x1<<7) // Received coefficient update preset field.
+  #define PHY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS_PRESET_K2_E5_SHIFT                               7
+#define PHY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS_K2_E5                                                          0x00df88UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS_C_P1_K2_E5                                                   (0x3<<0) // Received status report field for post-cursor tap. 2'b00  not updated 2'b01  minimum 2'b10  updated 2'b11  maximum
+  #define PHY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS_C_P1_K2_E5_SHIFT                                             0
+  #define PHY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS_C_0_K2_E5                                                    (0x3<<2) // Received status report field for cursor tap.
+  #define PHY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS_C_0_K2_E5_SHIFT                                              2
+  #define PHY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS_C_M1_K2_E5                                                   (0x3<<4) // Received status report field for pre-cursor tap.
+  #define PHY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS_C_M1_K2_E5_SHIFT                                             4
+  #define PHY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS_LOCAL_RX_READY_K2_E5                                         (0x1<<6) // Received status report field to indicate local receiver is ready.
+  #define PHY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS_LOCAL_RX_READY_K2_E5_SHIFT                                   6
+  #define PHY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS_DME_ERROR_K2_E5                                              (0x1<<7) // Indicates differential manchester decoding error.  Not sticky.
+  #define PHY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS_DME_ERROR_K2_E5_SHIFT                                        7
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X0_K2_E5                                                              0x000000UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X0_SOC0_DIV_O_K2_E5                                                 (0xf<<0) // Static divider control for SOC0 The only access to this divider. Not an override
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X0_SOC0_DIV_O_K2_E5_SHIFT                                           0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X0_SOC1_DIV_O_K2_E5                                                 (0xf<<4) // Static divider control for SOC1 The only access to this divider. Not an override
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X0_SOC1_DIV_O_K2_E5_SHIFT                                           4
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X1_K2_E5                                                              0x000004UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X1_CK_SOC_DIV_OVR_O_2_0_K2_E5                                       (0x7<<0) // Override for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Enable [1:0] - Override for pins ck_soc_div_i [1:0]
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X1_CK_SOC_DIV_OVR_O_2_0_K2_E5_SHIFT                                 0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X1_PMA_CM_REF_CLK_DIV_O_K2_E5                                       (0x3<<3) // Divider for pma_cm_ref_clk
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X1_PMA_CM_REF_CLK_DIV_O_K2_E5_SHIFT                                 3
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X1_GCFSM_CLK_DIV_O_K2_E5                                            (0x3<<5) // Static divider control for CMU GCFSM clock The only access to this divider. Not an override 4d0:  No division  4d1:  /2 4d2:  /2 4d3:  /4:
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X1_GCFSM_CLK_DIV_O_K2_E5_SHIFT                                      5
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X1_BURNIN_REF_LIFE_CLK_SEL_O_K2_E5                                  (0x1<<7) // Reference clock select override value for burn_in mode. This override is enabled by primary input pin burn_in_i
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X1_BURNIN_REF_LIFE_CLK_SEL_O_K2_E5_SHIFT                            7
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X2_K2_E5                                                              0x000008UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X2_SSC_CLK_DIV_O_K2_E5                                              (0x7<<0) // Static divider control for the SSC block The only access to this divider. Not an override 4d0:  No division  4d1:  /2 4d2:  /4 4d3:  /8:
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X2_SSC_CLK_DIV_O_K2_E5_SHIFT                                        0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X2_CDR_REFCLK_SEL_O_2_0_K2_E5                                       (0x7<<3) // Selects one lane's recovered byte clock of all existing lanes, which goes to refclk buffer.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X2_CDR_REFCLK_SEL_O_2_0_K2_E5_SHIFT                                 3
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X2_CDR_REFDIV_O_1_0_K2_E5                                           (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by 4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X2_CDR_REFDIV_O_1_0_K2_E5_SHIFT                                     6
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X3_K2_E5                                                              0x00000cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X3_AHB_PMA_CM_DIVNSEL_O_6_0_K2_E5                                   (0x7f<<0) // CMU N-divider setting
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X3_AHB_PMA_CM_DIVNSEL_O_6_0_K2_E5_SHIFT                             0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X4_K2_E5                                                              0x000010UL //Access:RW   DataWidth:0x8    // CMU FL LDHS count value
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X5_K2_E5                                                              0x000014UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_FL_LDHS_O_9_8_K2_E5                                   (0x3<<0) // CMU FL LDHS count value
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_FL_LDHS_O_9_8_K2_E5_SHIFT                             0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_PLL_REFDIV2_ENA_O_K2_E5                               (0x1<<2) // CMU reference div2 enable
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_PLL_REFDIV2_ENA_O_K2_E5_SHIFT                         2
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_PREDIV4_ENA_O_K2_E5                                   (0x1<<3) // CMU FL prediv4 enable
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_PREDIV4_ENA_O_K2_E5_SHIFT                             3
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_REFCLK_DEGLITCH_DIS_O_K2_E5                           (0x1<<4) // Reference clock startup deglitch circuit disable
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_REFCLK_DEGLITCH_DIS_O_K2_E5_SHIFT                     4
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X6_K2_E5                                                              0x000018UL //Access:RW   DataWidth:0x8    // CMU GCFSM Output Overrides for the following functions: [27] - active high, Override Enable [26]  - GCFSM Request flag [25:24] - GCFSM Function [23:0] - GCFSM Control Signal
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X7_K2_E5                                                              0x00001cUL //Access:RW   DataWidth:0x8    // CMU GCFSM Output Overrides for the following functions: [27] - active high, Override Enable [26]  - GCFSM Request flag [25:24] - GCFSM Function [23:0] - GCFSM Control Signal
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X8_K2_E5                                                              0x000020UL //Access:RW   DataWidth:0x8    // CMU GCFSM Output Overrides for the following functions: [27] - active high, Override Enable [26]  - GCFSM Request flag [25:24] - GCFSM Function [23:0] - GCFSM Control Signal
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X9_K2_E5                                                              0x000024UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X9_GCFSM_OVR_O_27_24_K2_E5                                          (0xf<<0) // CMU GCFSM Output Overrides for the following functions: [27] - active high, Override Enable [26]  - GCFSM Request flag [25:24] - GCFSM Function [23:0] - GCFSM Control Signal
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X9_GCFSM_OVR_O_27_24_K2_E5_SHIFT                                    0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X10_K2_E5                                                             0x000028UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 7-0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X11_K2_E5                                                             0x00002cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 15-8
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X12_K2_E5                                                             0x000030UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 23-16
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X13_K2_E5                                                             0x000034UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 31-24
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X14_K2_E5                                                             0x000038UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 39-32
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X15_K2_E5                                                             0x00003cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 47-40
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X16_K2_E5                                                             0x000040UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 55-48
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X17_K2_E5                                                             0x000044UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 63-56
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X18_K2_E5                                                             0x000048UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 71-64
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X19_K2_E5                                                             0x00004cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 79-72
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X20_K2_E5                                                             0x000050UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 87-80
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X21_K2_E5                                                             0x000054UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 95-88
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X22_K2_E5                                                             0x000058UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 103-96
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X23_K2_E5                                                             0x00005cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 111-104
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X24_K2_E5                                                             0x000060UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 119-112
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X25_K2_E5                                                             0x000064UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 127-120
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X26_K2_E5                                                             0x000068UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X26_GCFSM_CMU_OUT_OVR_EN_O_K2_E5                                    (0x1<<0) // GCFSM output override enable
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X26_GCFSM_CMU_OUT_OVR_EN_O_K2_E5_SHIFT                              0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X26_GCFSM_CMU_PMA_DATA_OVR_O_6_0_K2_E5                              (0x7f<<1) // GCFSM pma_data_o override
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X26_GCFSM_CMU_PMA_DATA_OVR_O_6_0_K2_E5_SHIFT                        1
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X27_K2_E5                                                             0x00006cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_DATA_OVR_O_11_7_K2_E5                             (0x1f<<0) // GCFSM pma_data_o override
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_DATA_OVR_O_11_7_K2_E5_SHIFT                       0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_LATCH_OVR_O_K2_E5                                 (0x1<<5) // GCFSM pma_latch_o override
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_LATCH_OVR_O_K2_E5_SHIFT                           5
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_GO_OVR_O_K2_E5                                    (0x1<<6) // GCFSM pma_go_o override
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_GO_OVR_O_K2_E5_SHIFT                              6
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_READ_OVR_O_K2_E5                                  (0x1<<7) // GCFSM pma_read_o override
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_READ_OVR_O_K2_E5_SHIFT                            7
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X28_K2_E5                                                             0x000070UL //Access:RW   DataWidth:0x8    // GCFSM pma_cal_o override
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X29_K2_E5                                                             0x000074UL //Access:RW   DataWidth:0x8    // GCFSM pma_cal_o override
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X30_K2_E5                                                             0x000078UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_SOC_CLK_EN_OUT_OVR_O_K2_E5                              (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - SOC clock output enable
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_SOC_CLK_EN_OUT_OVR_O_K2_E5_SHIFT                        0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_REF_CLK_EN_OUT_OVR_O_K2_E5                              (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - REF clock output enable
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_REF_CLK_EN_OUT_OVR_O_K2_E5_SHIFT                        2
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_LOCK_EN_OUT_OVR_O_K2_E5                                 (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - LOCK output enable
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_LOCK_EN_OUT_OVR_O_K2_E5_SHIFT                           4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_PMA_RST_CMU_OUT_OVR_O_K2_E5                             (0x3<<6) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_PMA_RST_CMU_OUT_OVR_O_K2_E5_SHIFT                       6
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X31_K2_E5                                                             0x00007cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_RST_CMUREG_OUT_OVR_O_K2_E5                          (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - SOC clock output enable - switches to SOC from life clock
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_RST_CMUREG_OUT_OVR_O_K2_E5_SHIFT                    0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_RST_CMUSYNTH_OUT_OVR_O_K2_E5                        (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU SYNTH
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_RST_CMUSYNTH_OUT_OVR_O_K2_E5_SHIFT                  2
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_RST_CMUVCO_OUT_OVR_O_K2_E5                          (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU VC0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_RST_CMUVCO_OUT_OVR_O_K2_E5_SHIFT                    4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_IDDQ_BIAS_OUT_OVR_O_K2_E5                           (0x3<<6) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - IDDQ BIAS
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_IDDQ_BIAS_OUT_OVR_O_K2_E5_SHIFT                     6
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X32_K2_E5                                                             0x000080UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_BIAS_OUT_OVR_O_K2_E5                             (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD BIAS
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_BIAS_OUT_OVR_O_K2_E5_SHIFT                       0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_CMU_OUT_OVR_O_K2_E5                              (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD CMU
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_CMU_OUT_OVR_O_K2_E5_SHIFT                        2
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_CMUREG_OUT_OVR_O_K2_E5                           (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD CMU REG
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_CMUREG_OUT_OVR_O_K2_E5_SHIFT                     4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_REF_OUT_OVR_O_K2_E5                              (0x3<<6) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD REF OUT
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_REF_OUT_OVR_O_K2_E5_SHIFT                        6
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X33_K2_E5                                                             0x000084UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X33_MSM_CMU_PMA_RESET_TXCLK_PCS_CLK_OVR_O_K2_E5                     (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PCS CLK ENA
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X33_MSM_CMU_PMA_RESET_TXCLK_PCS_CLK_OVR_O_K2_E5_SHIFT               0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X33_MSM_CMU_PMA_RST_CMU_FL_OUT_OVR_O_K2_E5                          (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU FL
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X33_MSM_CMU_PMA_RST_CMU_FL_OUT_OVR_O_K2_E5_SHIFT                    2
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X33_MSM_CMU_PMA_RST_CMU_GCRX_OUT_OVR_O_K2_E5                        (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU GCRX
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X33_MSM_CMU_PMA_RST_CMU_GCRX_OUT_OVR_O_K2_E5_SHIFT                  4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X33_MSM_PMA_LF_EXTZERO_ENA_OUT_OVR_O_K2_E5                          (0x3<<6) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - LF EXTZERO ENA
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X33_MSM_PMA_LF_EXTZERO_ENA_OUT_OVR_O_K2_E5_SHIFT                    6
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X34_K2_E5                                                             0x000088UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X34_MSM_CMU_PMA_LFI_EXTZERO_OUT_OVR_O_K2_E5                         (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - LFI EXTZERO ENA
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X34_MSM_CMU_PMA_LFI_EXTZERO_OUT_OVR_O_K2_E5_SHIFT                   0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X34_MSM_CMU_PMA_PD_CMUREGREF_OUT_OVR_O_K2_E5                        (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD CMU REGREF
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X34_MSM_CMU_PMA_PD_CMUREGREF_OUT_OVR_O_K2_E5_SHIFT                  2
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X34_MSM_PMA_RESET_CMUREGREF_OUT_OVR_O_K2_E5                         (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU REGREF
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X34_MSM_PMA_RESET_CMUREGREF_OUT_OVR_O_K2_E5_SHIFT                   4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X34_MSM_PMA_RESET_TXCLK_OVR_O_K2_E5                                 (0x3<<6) // Override register for reset_txclk
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X34_MSM_PMA_RESET_TXCLK_OVR_O_K2_E5_SHIFT                           6
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X35_K2_E5                                                             0x00008cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X35_MSM_PMA_RESET_CLKDIV_OVR_O_K2_E5                                (0x3<<0) // Override register for reset_clkdiv_ovr
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X35_MSM_PMA_RESET_CLKDIV_OVR_O_K2_E5_SHIFT                          0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X35_MSM_PMA_PD_CLKDIV_OVR_O_K2_E5                                   (0x3<<2) // Override register for pd_clkdiv_ovr
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X35_MSM_PMA_PD_CLKDIV_OVR_O_K2_E5_SHIFT                             2
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X35_MSM_PMA_PD_CLKDIV_REFCLK_LEFT_OVR_O_K2_E5                       (0x3<<4) // Override register for pd_clkdiv_refclk_left_ovr
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X35_MSM_PMA_PD_CLKDIV_REFCLK_LEFT_OVR_O_K2_E5_SHIFT                 4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X35_MSM_PMA_PD_CLKDIV_REFCLK_RIGHT_OVR_O_K2_E5                      (0x3<<6) // Override register for pd_clkdiv_refclk_right_ovr
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X35_MSM_PMA_PD_CLKDIV_REFCLK_RIGHT_OVR_O_K2_E5_SHIFT                6
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X56_K2_E5                                                             0x0000e0UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X57_K2_E5                                                             0x0000e4UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X58_K2_E5                                                             0x0000e8UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X59_K2_E5                                                             0x0000ecUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X60_K2_E5                                                             0x0000f0UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X61_K2_E5                                                             0x0000f4UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X62_K2_E5                                                             0x0000f8UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X63_K2_E5                                                             0x0000fcUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X64_K2_E5                                                             0x000100UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X65_K2_E5                                                             0x000104UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X66_K2_E5                                                             0x000108UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X67_K2_E5                                                             0x00010cUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X68_K2_E5                                                             0x000110UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X69_K2_E5                                                             0x000114UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X70_K2_E5                                                             0x000118UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X71_K2_E5                                                             0x00011cUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X72_K2_E5                                                             0x000120UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X73_K2_E5                                                             0x000124UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X74_K2_E5                                                             0x000128UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X75_K2_E5                                                             0x00012cUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X76_K2_E5                                                             0x000130UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X77_K2_E5                                                             0x000134UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X78_K2_E5                                                             0x000138UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X79_K2_E5                                                             0x00013cUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X80_K2_E5                                                             0x000140UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X81_K2_E5                                                             0x000144UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X82_K2_E5                                                             0x000148UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X83_K2_E5                                                             0x00014cUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X84_K2_E5                                                             0x000150UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X85_K2_E5                                                             0x000154UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X86_K2_E5                                                             0x000158UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X87_K2_E5                                                             0x00015cUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X88_K2_E5                                                             0x000160UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X89_K2_E5                                                             0x000164UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X90_K2_E5                                                             0x000168UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X91_K2_E5                                                             0x00016cUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X92_K2_E5                                                             0x000170UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X92_MSM_FUNC_DATA_O_289_288_K2_E5                                   (0x3<<0) // MSM Function Data Bus slice
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X92_MSM_FUNC_DATA_O_289_288_K2_E5_SHIFT                             0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X92_MSM_IN_OVR_O_5_0_K2_E5                                          (0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag override [3:0] - MFSM function override
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X92_MSM_IN_OVR_O_5_0_K2_E5_SHIFT                                    2
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X93_K2_E5                                                             0x000174UL //Access:RW   DataWidth:0x8    // Number of reference clock cycles to count after qsample is ok, before PLL is declared locked
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X94_K2_E5                                                             0x000178UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_NUM_CYCLES_O_9_8_K2_E5                                 (0x3<<0) // Number of reference clock cycles to count after qsample is ok, before PLL is declared locked
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_NUM_CYCLES_O_9_8_K2_E5_SHIFT                           0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_GOOD_STATE_O_K2_E5                                     (0x1<<2) // State of qsample for PLL to be considered locked
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_GOOD_STATE_O_K2_E5_SHIFT                               2
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_OVR_O_K2_E5                                            (0x7<<3) // Overrides for PLL lock signals [2] - Active high, override enable [1] - PLL ok override, bypasses ref clock cycle count after qsample is ok [0] - Qsample override
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_OVR_O_K2_E5_SHIFT                                      3
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X95_K2_E5                                                             0x00017cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_KVCO_SEL_O_K2_E5                                   (0x3<<0) // CMU VCO integral path gain
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_KVCO_SEL_O_K2_E5_SHIFT                             0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_FORCE_ILF_O_K2_E5                                    (0x3<<2) // CMU loop filter force to common mode
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_FORCE_ILF_O_K2_E5_SHIFT                              2
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_CP_SEL_O_K2_E5                                     (0x3<<4) // Charge pump current gain select.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_CP_SEL_O_K2_E5_SHIFT                               4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_HIZ_O_K2_E5                                        (0x1<<6) // CMU PLL HIZ setting
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_HIZ_O_K2_E5_SHIFT                                  6
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_C1_SEL_O_K2_E5                                       (0x1<<7) // CMU LF C1 cap select. Enabling increases C1 cap.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_C1_SEL_O_K2_E5_SHIFT                                 7
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X96_K2_E5                                                             0x000180UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_P_CAP_SEL_O_K2_E5                                    (0x7<<0) // CMU VCO proportional path cap select
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_P_CAP_SEL_O_K2_E5_SHIFT                              0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_CHPMP_CHOP_ENAN_O_K2_E5                              (0x1<<3) // Charge pump chop enable
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_CHPMP_CHOP_ENAN_O_K2_E5_SHIFT                        3
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_I_CAP_SEL_O_K2_E5                                    (0x7<<4) // CMU VCO integral path cap select
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_I_CAP_SEL_O_K2_E5_SHIFT                              4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_BGSTART_BYP_O_K2_E5                                  (0x1<<7) // Bandgap startup circuit bypass
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_BGSTART_BYP_O_K2_E5_SHIFT                            7
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X97_K2_E5                                                             0x000184UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X97_AHB_PMA_CM_VCO_BIAS_O_K2_E5                                     (0xf<<0) // CMU VCO bias current setting.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X97_AHB_PMA_CM_VCO_BIAS_O_K2_E5_SHIFT                               0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X97_AHB_PMA_CM_VREG_O_K2_E5                                         (0x3<<4) // CMU VREG setting
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X97_AHB_PMA_CM_VREG_O_K2_E5_SHIFT                                   4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X97_AHB_PMA_CM_VREGH_O_K2_E5                                        (0x3<<6) // CMU VREGH setting
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X97_AHB_PMA_CM_VREGH_O_K2_E5_SHIFT                                  6
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_K2_E5                                                             0x000188UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PFD_FORCE_DN_O_K2_E5                                 (0x1<<0) // Force PFD to output down
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PFD_FORCE_DN_O_K2_E5_SHIFT                           0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PFD_FORCE_UP_O_K2_E5                                 (0x1<<1) // Force PFD to output up
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PFD_FORCE_UP_O_K2_E5_SHIFT                           1
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_SR_NDIV_OVR_ENA_O_K2_E5                                         (0x1<<2) // Override enable for overriding N-div value
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_SR_NDIV_OVR_ENA_O_K2_E5_SHIFT                                   2
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_V2I_FILTER_SW_ON_O_K2_E5                             (0x1<<3) // CMU V2I filter enable
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_V2I_FILTER_SW_ON_O_K2_E5_SHIFT                       3
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_O_K2_E5                       (0x1<<4) // CMU VCO PMOS proportional current increase
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_O_K2_E5_SHIFT                 4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_LESS_EN_O_K2_E5                       (0x1<<5) // CMU VCO PMOS proportional current decrease
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_LESS_EN_O_K2_E5_SHIFT                 5
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_VREGREF_O_K2_E5                                      (0x3<<6) // CMU reference clock regulator setting
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_VREGREF_O_K2_E5_SHIFT                                6
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X99_K2_E5                                                             0x00018cUL //Access:RW   DataWidth:0x8    // CMU AFE spares
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X100_K2_E5                                                            0x000190UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_PFD_PW_O_K2_E5                                      (0x3<<0) // PFD pulse width setting
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_PFD_PW_O_K2_E5_SHIFT                                0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_I_DROPI_O_K2_E5                                     (0x1<<2) // Enable to reduce charge pump reference current
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_I_DROPI_O_K2_E5_SHIFT                               2
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_P_KVCO_SEL_O_K2_E5                                  (0x1f<<3) // CMU PLL KVCO setting
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_P_KVCO_SEL_O_K2_E5_SHIFT                            3
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X101_K2_E5                                                            0x000194UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X101_AHB_PMA_CM_DIVPSEL_O_K2_E5                                     (0x7f<<0) // CMU P-divider setting
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X101_AHB_PMA_CM_DIVPSEL_O_K2_E5_SHIFT                               0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X102_K2_E5                                                            0x000198UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X102_AHB_PMA_CM_VCOFR_O_K2_E5                                       (0x7<<0) // AHB override for calibrated VCOFR value.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X102_AHB_PMA_CM_VCOFR_O_K2_E5_SHIFT                                 0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X102_AHB_PMA_CM_VCOFR_SEL_O_K2_E5                                   (0x1<<3) // Override enable for overriding VCOFR value
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X102_AHB_PMA_CM_VCOFR_SEL_O_K2_E5_SHIFT                             3
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_RESERVEDREG0_K2_E5                                                    0x00019cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_RESERVEDREG1_K2_E5                                                    0x0001a0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_RESERVEDREG2_K2_E5                                                    0x0001a4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_RESERVEDREG3_K2_E5                                                    0x0001a8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_RESERVEDREG4_K2_E5                                                    0x0001acUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X108_K2_E5                                                            0x0001b0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X108_PMA_REFCLK_OUTPUT_SEL_O_3_0_K2_E5                              (0xf<<3) // Reference clock output select
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X108_PMA_REFCLK_OUTPUT_SEL_O_3_0_K2_E5_SHIFT                        3
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X108_PMA_REFCLK_SEL_OVR_O_K2_E5                                     (0x1<<7) // Reference clock select override
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X108_PMA_REFCLK_SEL_OVR_O_K2_E5_SHIFT                               7
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_K2_E5                                                            0x0001b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_OE_L_O_K2_E5                                        (0x1<<0) // Override for primary IO: refclk_oe_l_i Enabled by pma_refclk_sel_ovr_o
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_OE_L_O_K2_E5_SHIFT                                  0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_OE_R_O_K2_E5                                        (0x1<<1) // "Override for primary IO: refclk_oe_r_i Enabled by pma_refclk_sel_ovr_o"
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_OE_R_O_K2_E5_SHIFT                                  1
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_RXCLK_OE_L_O_K2_E5                                         (0x1<<2) // "Override for primary IO: rxclk_oe_l_i Enabled by pma_refclk_sel_ovr_o"
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_RXCLK_OE_L_O_K2_E5_SHIFT                                   2
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_RXCLK_OE_R_O_K2_E5                                         (0x1<<3) // Override for primary IO: rxclk_oe_l_i Enabled by pma_refclk_sel_ovr_o
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_RXCLK_OE_R_O_K2_E5_SHIFT                                   3
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_CM_HV2P5SEL_O_K2_E5                                        (0x1<<4) // Enable additonal LF cap for 2.5V/3.3V process
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_CM_HV2P5SEL_O_K2_E5_SHIFT                                  4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_QFWD_L_O_K2_E5                                      (0x1<<6) // Override for primary IO: refclk_qfwd_l_i Enabled by pma_refclk_sel_ovr_o
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_QFWD_L_O_K2_E5_SHIFT                                6
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_QFWD_R_O_K2_E5                                      (0x1<<7) // Override for primary IO: refclk_qfwd_r_i Enabled by pma_refclk_sel_ovr_o
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_QFWD_R_O_K2_E5_SHIFT                                7
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X110_K2_E5                                                            0x0001b8UL //Access:RW   DataWidth:0x8    // Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X111_K2_E5                                                            0x0001bcUL //Access:RW   DataWidth:0x8    // Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X112_K2_E5                                                            0x0001c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X112_SSC_FCNTL_O_19_16_K2_E5                                        (0xf<<0) // Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X112_SSC_FCNTL_O_19_16_K2_E5_SHIFT                                  0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X112_SSC_GEN_EN_O_K2_E5                                             (0x1<<4) // Active high Enable for SSC generator SSC mode
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X112_SSC_GEN_EN_O_K2_E5_SHIFT                                       4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X112_SSC_EN_O_K2_E5                                                 (0x1<<5) // Active high Enable for SSC block synth or SSC mode
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X112_SSC_EN_O_K2_E5_SHIFT                                           5
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X113_K2_E5                                                            0x0001c4UL //Access:RW   DataWidth:0x8    // SSC match value for Spread Spectrum Generation mode. Represents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X114_K2_E5                                                            0x0001c8UL //Access:RW   DataWidth:0x8    // SSC match value for Spread Spectrum Generation mode. Represents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X115_K2_E5                                                            0x0001ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_MATCH_VAL_O_19_16_K2_E5                                (0xf<<0) // SSC match value for Spread Spectrum Generation mode. Represents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_MATCH_VAL_O_19_16_K2_E5_SHIFT                          0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_FRACSYN_EN_O_K2_E5                                     (0x1<<4) // Enable for SSC generator with Fractional Synthesis
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_FRACSYN_EN_O_K2_E5_SHIFT                               4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X115_EN_FRACN_FRCDIV_MODE_O_K2_E5                                   (0x1<<5) // Enable fractional division mode and SSC mode
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X115_EN_FRACN_FRCDIV_MODE_O_K2_E5_SHIFT                             5
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_UPDOWN_EN_O_K2_E5                                      (0x1<<6) // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down spreading
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_UPDOWN_EN_O_K2_E5_SHIFT                                6
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X116_K2_E5                                                            0x0001d0UL //Access:RW   DataWidth:0x8    // In Spread Spectrum Generation mode, represents the magnitude of the incremental step in the SSC word
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X117_K2_E5                                                            0x0001d4UL //Access:RW   DataWidth:0x8    // In Spread Spectrum Generation mode, represents the magnitude of the incremental step in the SSC word
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X118_K2_E5                                                            0x0001d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X118_FRACN_MOD_TST_IN_O_K2_E5                                       (0xf<<0) // Test input bus
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X118_FRACN_MOD_TST_IN_O_K2_E5_SHIFT                                 0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X118_FRACN_MOD_TST_CTRL_O_K2_E5                                     (0x3<<4) // Test i/p control source :  0-modulator  1-bypass modulator  2-modulator  3-sr_txt_in_i
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X118_FRACN_MOD_TST_CTRL_O_K2_E5_SHIFT                               4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X118_FRACN_FBK_CLK_SRC_SEL_O_K2_E5                                  (0x1<<6) // Clock Select for High Speed clock source :  0-clk_hs_fbk  1-clk_hs_refout
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X118_FRACN_FBK_CLK_SRC_SEL_O_K2_E5_SHIFT                            6
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X118_FRACN_FBK_CLK_DIV_SEL_O_K2_E5                                  (0x1<<7) // Clock divider for High Speed clock source
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X118_FRACN_FBK_CLK_DIV_SEL_O_K2_E5_SHIFT                            7
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X119_K2_E5                                                            0x0001dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_OVR_O_4_0_K2_E5                               (0x1f<<0) // override for the counter value
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_OVR_O_4_0_K2_E5_SHIFT                         0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_POLL_EN_O_K2_E5                               (0x1<<5) // CMU Temperature Calibration Polling Enable: enables the periodic polling and counter adjustment
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_POLL_EN_O_K2_E5_SHIFT                         5
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_POLARITY_O_K2_E5                              (0x1<<6) // chicken bit for counter polarity
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_POLARITY_O_K2_E5_SHIFT                        6
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_OVR_EN_O_K2_E5                                (0x1<<7) // override enable to use above value
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_OVR_EN_O_K2_E5_SHIFT                          7
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X120_K2_E5                                                            0x0001e0UL //Access:RW   DataWidth:0x8    // Divider input for Div-by-N counter
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X121_K2_E5                                                            0x0001e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X121_AHB_CMU_TEMP_CAL_CLK_DIV_O_14_8_K2_E5                          (0x7f<<0) // Divider input for Div-by-N counter
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X121_AHB_CMU_TEMP_CAL_CLK_DIV_O_14_8_K2_E5_SHIFT                    0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X122_K2_E5                                                            0x0001e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X122_PMA_CM_REFCLK_TERM_OVR_O_K2_E5                                 (0x1f<<0) // Refclk Termination override value
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X122_PMA_CM_REFCLK_TERM_OVR_O_K2_E5_SHIFT                           0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X122_PMA_CM_REFCLK_TERM_OVR_EN_O_K2_E5                              (0x1<<5) // Refclk Termination override enable
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X122_PMA_CM_REFCLK_TERM_OVR_EN_O_K2_E5_SHIFT                        5
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X123_K2_E5                                                            0x0001ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X123_PMA_CM_RX_TERM_OVR_O_K2_E5                                     (0x1f<<0) // Rx Termination override value, every rx lane gets the same value
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X123_PMA_CM_RX_TERM_OVR_O_K2_E5_SHIFT                               0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X123_PMA_CM_RX_TERM_OVR_EN_O_K2_E5                                  (0x1<<5) // Rx Termination override enable
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X123_PMA_CM_RX_TERM_OVR_EN_O_K2_E5_SHIFT                            5
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X124_K2_E5                                                            0x0001f0UL //Access:RW   DataWidth:0x8    // In txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X125_K2_E5                                                            0x0001f4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_WAIT_NEXT_UP_8_K2_E5                                 (0x1<<0) // In txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_WAIT_NEXT_UP_8_K2_E5_SHIFT                           0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_WAIT_NEXT_SAMPLE_K2_E5                               (0x7<<1) // in txterm calibration, the number refclk cycles to wait before sampling the up from the same comparator
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_WAIT_NEXT_SAMPLE_K2_E5_SHIFT                         1
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_UP_NUM_SAMPLES_K2_E5                                 (0xf<<4) // in txterm calibration, the number of samples to take from the same comparator
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_UP_NUM_SAMPLES_K2_E5_SHIFT                           4
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X126_K2_E5                                                            0x0001f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X126_AHB_GC_TCCAL_ENA_OVR_K2_E5                                     (0x1<<0) // Debug feature, when set forces circuit RX termination calibration circuit to be enabled allowing ahb_tx_tc_bias_ovr to take effect
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X126_AHB_GC_TCCAL_ENA_OVR_K2_E5_SHIFT                               0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X126_AHB_RX_TC_BIAS_OVR_K2_E5                                       (0x7<<1) // Bit 3:1 RX termination calibration DAC override setting
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X126_AHB_RX_TC_BIAS_OVR_K2_E5_SHIFT                                 1
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X127_K2_E5                                                            0x0001fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X127_CMU_MASTER_CDN_O_K2_E5                                         (0x1<<0) // Master reset for CMU
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X127_CMU_MASTER_CDN_O_K2_E5_SHIFT                                   0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X127_PCS_RATE_O_K2_E5                                               (0x3<<1) // Determines rate for PLL clock pcs_rate_o[0] :      0: VCO clock untouched      1: VCO clock divided by 2                                                 pcs_rate_o[1] :      0: PMA operates in 10b/20b mode Enables %5 circuit      1: PMA operates in 8b/16b mode   Enables %4 circuit
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X127_PCS_RATE_O_K2_E5_SHIFT                                         1
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X128_K2_E5                                                            0x000200UL //Access:RW   DataWidth:0x8    // Bit 7:5 amux_ena[2:0] Bit 4:0 amux_sel_o[4:0] For detailed description please refer to Phy User manual.
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X129_K2_E5                                                            0x000204UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X129_CMU_IN_OVR_O_3_0_K2_E5                                         (0xf<<0) // Override for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pin IO [0] - CMU Reset Pin IO
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X129_CMU_IN_OVR_O_3_0_K2_E5_SHIFT                                   0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X129_CMU_OUT_OVR_O_1_0_K2_E5                                        (0x3<<4) // Override for Reset_smu_fl
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X129_CMU_OUT_OVR_O_1_0_K2_E5_SHIFT                                  4
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2_E5                                                            0x000208UL //Access:R    DataWidth:0x8    // Snapshot of digital test bus data [7:0]
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2_E5                                                            0x00020cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_TBUS_DATA_SMPL_11_8_K2_E5                                      (0xf<<0) // Snapshot of digital test bus data [11:8]
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_TBUS_DATA_SMPL_11_8_K2_E5_SHIFT                                0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2_E5                                                            0x000210UL //Access:RW   DataWidth:0x8    // CMU Test Bus address 7-0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2_E5                                                            0x000214UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_TBUS_ADDR_OVR_O_10_8_K2_E5                                     (0x7<<0) // CMU Test Bus address 10-8
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_TBUS_ADDR_OVR_O_10_8_K2_E5_SHIFT                               0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X134_K2_E5                                                            0x000218UL //Access:RW   DataWidth:0x8    // Not used
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X144_K2_E5                                                            0x000240UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X146_K2_E5                                                            0x000248UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X147_K2_E5                                                            0x00024cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X147_AHB_CMU_PROG_MULT_REF_CLK_WAIT_O_K2_E5                         (0x7<<0) // wait multiplication factor for msm_cmu_databank
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X147_AHB_CMU_PROG_MULT_REF_CLK_WAIT_O_K2_E5_SHIFT                   0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_RESERVEDREG5_K2_E5                                                    0x000250UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X149_K2_E5                                                            0x000254UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X149_AHB_PMA_CM_EN_REGLN_O_K2_E5                                    (0xf<<0) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X149_AHB_PMA_CM_EN_REGLN_O_K2_E5_SHIFT                              0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X153_K2_E5                                                            0x000264UL //Access:RW   DataWidth:0x8    // Inverts up_i when set to 1
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X154_K2_E5                                                            0x000268UL //Access:RW   DataWidth:0x8    // Inverts up_i when set to 1
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X161_K2_E5                                                            0x000284UL //Access:RW   DataWidth:0x8    // Function info for each MSM function. Varies depending on function number. _13:06 - Address of first command to run _05:00 - Number of commands to run
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X162_K2_E5                                                            0x000288UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X163_K2_E5                                                            0x00028cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X164_K2_E5                                                            0x000290UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X165_K2_E5                                                            0x000294UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X166_K2_E5                                                            0x000298UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X167_K2_E5                                                            0x00029cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X168_K2_E5                                                            0x0002a0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X169_K2_E5                                                            0x0002a4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X170_K2_E5                                                            0x0002a8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X171_K2_E5                                                            0x0002acUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X172_K2_E5                                                            0x0002b0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X173_K2_E5                                                            0x0002b4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X174_K2_E5                                                            0x0002b8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X175_K2_E5                                                            0x0002bcUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X176_K2_E5                                                            0x0002c0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X177_K2_E5                                                            0x0002c4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X178_K2_E5                                                            0x0002c8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X179_K2_E5                                                            0x0002ccUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X180_K2_E5                                                            0x0002d0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X181_K2_E5                                                            0x0002d4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X182_K2_E5                                                            0x0002d8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X183_K2_E5                                                            0x0002dcUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X184_K2_E5                                                            0x0002e0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X185_K2_E5                                                            0x0002e4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X186_K2_E5                                                            0x0002e8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X187_K2_E5                                                            0x0002ecUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X188_K2_E5                                                            0x0002f0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_RESERVEDREG6_K2_E5                                                    0x0002f4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_RESERVEDREG7_K2_E5                                                    0x0002f8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_K2_E5                                                            0x0002fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_IDDQ_BIAS_IDDQ_SETVAL_O_K2_E5                                  (0x1<<0) // MSM Function IDDQ mode default value for iddq_bias
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_IDDQ_BIAS_IDDQ_SETVAL_O_K2_E5_SHIFT                            0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_BIAS_IDDQ_SETVAL_O_K2_E5                                    (0x1<<1) // MSM Function IDDQ mode default value for pd_bias
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_BIAS_IDDQ_SETVAL_O_K2_E5_SHIFT                              1
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_RESET_TXCLK_PCS_CLK_IDDQ_SETVAL_O_K2_E5                        (0x1<<2) // MSM Function IDDQ mode default value for pcs_clk_ena
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_RESET_TXCLK_PCS_CLK_IDDQ_SETVAL_O_K2_E5_SHIFT                  2
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_CMU_IDDQ_SETVAL_O_K2_E5                                     (0x1<<3) // MSM Function IDDQ mode default value for pd_cmu
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_CMU_IDDQ_SETVAL_O_K2_E5_SHIFT                               3
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_CMUREG_IDDQ_SETVAL_O_K2_E5                                  (0x1<<4) // MSM Function IDDQ mode default value for pd_cmureg
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_CMUREG_IDDQ_SETVAL_O_K2_E5_SHIFT                            4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_CMUREGREF_IDDQ_SETVAL_O_K2_E5                               (0x1<<5) // MSM Function IDDQ mode default value for pd_cmuregref
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_CMUREGREF_IDDQ_SETVAL_O_K2_E5_SHIFT                         5
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_REF_IDDQ_SETVAL_O_K2_E5                                     (0x1<<6) // MSM Function IDDQ mode default value for pd_ref
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_REF_IDDQ_SETVAL_O_K2_E5_SHIFT                               6
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_RESET_CMU_FL_IDDQ_SETVAL_O_K2_E5                               (0x1<<7) // MSM Function IDDQ mode default value for reset_cmu_fl
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_RESET_CMU_FL_IDDQ_SETVAL_O_K2_E5_SHIFT                         7
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_K2_E5                                                            0x000300UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMU_IDDQ_SETVAL_O_K2_E5                                  (0x1<<0) // MSM Function IDDQ mode default value for reset_cmu
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMU_IDDQ_SETVAL_O_K2_E5_SHIFT                            0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMU_GCRX_IDDQ_SETVAL_O_K2_E5                             (0x1<<1) // MSM Function IDDQ mode default value for reset_cmu_gcrx
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMU_GCRX_IDDQ_SETVAL_O_K2_E5_SHIFT                       1
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUREG_IDDQ_SETVAL_O_K2_E5                               (0x1<<2) // MSM Function IDDQ mode default value for reset_cmureg
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUREG_IDDQ_SETVAL_O_K2_E5_SHIFT                         2
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUREGREF_IDDQ_SETVAL_O_K2_E5                            (0x1<<3) // MSM Function IDDQ mode default value for reset_cmuregref
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUREGREF_IDDQ_SETVAL_O_K2_E5_SHIFT                      3
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUSYNTH_IDDQ_SETVAL_O_K2_E5                             (0x1<<4) // MSM Function IDDQ mode default value for reset_cmusynth
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUSYNTH_IDDQ_SETVAL_O_K2_E5_SHIFT                       4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUVCO_IDDQ_SETVAL_O_K2_E5                               (0x1<<5) // MSM Function IDDQ mode default value for reset_cmuvco
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUVCO_IDDQ_SETVAL_O_K2_E5_SHIFT                         5
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_LF_EXTZERO_ENA_IDDQ_SETVAL_O_K2_E5                             (0x1<<6) // MSM Function IDDQ mode default value for lf_extzero_ena
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_LF_EXTZERO_ENA_IDDQ_SETVAL_O_K2_E5_SHIFT                       6
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_LFI_EXTZERO_IDDQ_SETVAL_O_K2_E5                                (0x1<<7) // MSM Function IDDQ mode default value for lfi_extzero
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_LFI_EXTZERO_IDDQ_SETVAL_O_K2_E5_SHIFT                          7
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_K2_E5                                                            0x000304UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_SOC_CLK_EN_IDDQ_SETVAL_O_K2_E5                                 (0x1<<0) // MSM Function IDDQ mode default value for soc_clk_en
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_SOC_CLK_EN_IDDQ_SETVAL_O_K2_E5_SHIFT                           0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_REFCLK_EN_IDDQ_SETVAL_O_K2_E5                                  (0x1<<1) // MSM Function IDDQ mode default value for refclk_en
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_REFCLK_EN_IDDQ_SETVAL_O_K2_E5_SHIFT                            1
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_PLL_LOCK_EN_IDDQ_SETVAL_O_K2_E5                                (0x1<<2) // MSM Function IDDQ mode default value for pll_lock_en
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_PLL_LOCK_EN_IDDQ_SETVAL_O_K2_E5_SHIFT                          2
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_RESET_TXCLK_IDDQ_SETVAL_O_K2_E5                                (0x1<<3) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_RESET_TXCLK_IDDQ_SETVAL_O_K2_E5_SHIFT                          3
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_RESET_CLKDIV_IDDQ_SETVAL_O_K2_E5                               (0x1<<4) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_RESET_CLKDIV_IDDQ_SETVAL_O_K2_E5_SHIFT                         4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_IDDQ_SETVAL_O_K2_E5                                  (0x1<<5) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_IDDQ_SETVAL_O_K2_E5_SHIFT                            5
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_REFCLK_LEFT_IDDQ_SETVAL_O_K2_E5                      (0x1<<6) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_REFCLK_LEFT_IDDQ_SETVAL_O_K2_E5_SHIFT                6
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_REFCLK_RIGHT_IDDQ_SETVAL_O_K2_E5                     (0x1<<7) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_REFCLK_RIGHT_IDDQ_SETVAL_O_K2_E5_SHIFT               7
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_K2_E5                                                            0x000308UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_IDDQ_BIAS_RST_SETVAL_O_K2_E5                                   (0x1<<0) // MSM Function RST mode default value for iddq_bias
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_IDDQ_BIAS_RST_SETVAL_O_K2_E5_SHIFT                             0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_BIAS_RST_SETVAL_O_K2_E5                                     (0x1<<1) // MSM Function RST mode default value for pd_bias
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_BIAS_RST_SETVAL_O_K2_E5_SHIFT                               1
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_RESET_TXCLK_PCS_CLK_RST_SETVAL_O_K2_E5                         (0x1<<2) // MSM Function RST mode default value for pcs_clk_ena
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_RESET_TXCLK_PCS_CLK_RST_SETVAL_O_K2_E5_SHIFT                   2
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_CMU_RST_SETVAL_O_K2_E5                                      (0x1<<3) // MSM Function RST mode default value for pd_cmu
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_CMU_RST_SETVAL_O_K2_E5_SHIFT                                3
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_CMUREG_RST_SETVAL_O_K2_E5                                   (0x1<<4) // MSM Function RST mode default value for pd_cmureg
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_CMUREG_RST_SETVAL_O_K2_E5_SHIFT                             4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_CMUREGREF_RST_SETVAL_O_K2_E5                                (0x1<<5) // MSM Function RST mode default value for pd_cmuregref
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_CMUREGREF_RST_SETVAL_O_K2_E5_SHIFT                          5
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_REF_RST_SETVAL_O_K2_E5                                      (0x1<<6) // MSM Function RST mode default value for pd_ref
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_REF_RST_SETVAL_O_K2_E5_SHIFT                                6
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_RESET_CMU_FL_RST_SETVAL_O_K2_E5                                (0x1<<7) // MSM Function RST mode default value for reset_cmu_fl
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_RESET_CMU_FL_RST_SETVAL_O_K2_E5_SHIFT                          7
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_K2_E5                                                            0x00030cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMU_RST_SETVAL_O_K2_E5                                   (0x1<<0) // MSM Function RST mode default value for reset_cmu
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMU_RST_SETVAL_O_K2_E5_SHIFT                             0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMU_GCRX_RST_SETVAL_O_K2_E5                              (0x1<<1) // MSM Function RST mode default value for reset_cmu_gcrx
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMU_GCRX_RST_SETVAL_O_K2_E5_SHIFT                        1
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUREG_RST_SETVAL_O_K2_E5                                (0x1<<2) // MSM Function RST mode default value for reset_cmureg
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUREG_RST_SETVAL_O_K2_E5_SHIFT                          2
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUREGREF_RST_SETVAL_O_K2_E5                             (0x1<<3) // MSM Function RST mode default value for reset_cmuregref
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUREGREF_RST_SETVAL_O_K2_E5_SHIFT                       3
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUSYNTH_RST_SETVAL_O_K2_E5                              (0x1<<4) // MSM Function RST mode default value for reset_cmusynth
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUSYNTH_RST_SETVAL_O_K2_E5_SHIFT                        4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUVCO_RST_SETVAL_O_K2_E5                                (0x1<<5) // MSM Function RST mode default value for reset_cmuvco
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUVCO_RST_SETVAL_O_K2_E5_SHIFT                          5
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_LF_EXTZERO_ENA_RST_SETVAL_O_K2_E5                              (0x1<<6) // MSM Function RST mode default value for lf_extzero_ena
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_LF_EXTZERO_ENA_RST_SETVAL_O_K2_E5_SHIFT                        6
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_LFI_EXTZERO_RST_SETVAL_O_K2_E5                                 (0x1<<7) // MSM Function RST mode default value for lfi_extzero
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_LFI_EXTZERO_RST_SETVAL_O_K2_E5_SHIFT                           7
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_K2_E5                                                            0x000310UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_SOC_CLK_EN_RST_SETVAL_O_K2_E5                                  (0x1<<0) // MSM Function RST mode default value for soc_clk_en
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_SOC_CLK_EN_RST_SETVAL_O_K2_E5_SHIFT                            0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_REFCLK_EN_RST_SETVAL_O_K2_E5                                   (0x1<<1) // MSM Function RST mode default value for refclk_en
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_REFCLK_EN_RST_SETVAL_O_K2_E5_SHIFT                             1
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_PLL_LOCK_EN_RST_SETVAL_O_K2_E5                                 (0x1<<2) // MSM Function RST mode default value for pll_lock_en
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_PLL_LOCK_EN_RST_SETVAL_O_K2_E5_SHIFT                           2
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_RESET_TXCLK_RST_SETVAL_O_K2_E5                                 (0x1<<3) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_RESET_TXCLK_RST_SETVAL_O_K2_E5_SHIFT                           3
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_RESET_CLKDIV_RST_SETVAL_O_K2_E5                                (0x1<<4) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_RESET_CLKDIV_RST_SETVAL_O_K2_E5_SHIFT                          4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_RST_SETVAL_O_K2_E5                                   (0x1<<5) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_RST_SETVAL_O_K2_E5_SHIFT                             5
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_REFCLK_LEFT_RST_SETVAL_O_K2_E5                       (0x1<<6) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_REFCLK_LEFT_RST_SETVAL_O_K2_E5_SHIFT                 6
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_REFCLK_RIGHT_RST_SETVAL_O_K2_E5                      (0x1<<7) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_REFCLK_RIGHT_RST_SETVAL_O_K2_E5_SHIFT                7
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_K2_E5                                                            0x000314UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_IDDQ_BIAS_NORM_SETVAL_O_K2_E5                                  (0x1<<0) // MSM Function NORMAL mode default value for iddq_bias
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_IDDQ_BIAS_NORM_SETVAL_O_K2_E5_SHIFT                            0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_BIAS_NORM_SETVAL_O_K2_E5                                    (0x1<<1) // MSM Function NORMAL mode default value for pd_bias
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_BIAS_NORM_SETVAL_O_K2_E5_SHIFT                              1
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_RESET_TXCLK_PCS_CLK_NORM_SETVAL_O_K2_E5                        (0x1<<2) // MSM Function NORMAL mode default value for pcs_clk_ena
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_RESET_TXCLK_PCS_CLK_NORM_SETVAL_O_K2_E5_SHIFT                  2
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_CMU_NORM_SETVAL_O_K2_E5                                     (0x1<<3) // MSM Function NORMAL mode default value for pd_cmu
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_CMU_NORM_SETVAL_O_K2_E5_SHIFT                               3
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_CMUREG_NORM_SETVAL_O_K2_E5                                  (0x1<<4) // MSM Function NORMAL mode default value for pd_cmureg
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_CMUREG_NORM_SETVAL_O_K2_E5_SHIFT                            4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_CMUREGREF_NORM_SETVAL_O_K2_E5                               (0x1<<5) // MSM Function NORMAL mode default value for pd_cmuregref
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_CMUREGREF_NORM_SETVAL_O_K2_E5_SHIFT                         5
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_REF_NORM_SETVAL_O_K2_E5                                     (0x1<<6) // MSM Function NORMAL mode default value for pd_ref
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_REF_NORM_SETVAL_O_K2_E5_SHIFT                               6
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_RESET_CMU_FL_NORM_SETVAL_O_K2_E5                               (0x1<<7) // MSM Function NORMAL mode default value for reset_cmu_fl
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_RESET_CMU_FL_NORM_SETVAL_O_K2_E5_SHIFT                         7
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_K2_E5                                                            0x000318UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMU_NORM_SETVAL_O_K2_E5                                  (0x1<<0) // MSM Function NORMAL mode default value for reset_cmu
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMU_NORM_SETVAL_O_K2_E5_SHIFT                            0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMU_GCRX_NORM_SETVAL_O_K2_E5                             (0x1<<1) // MSM Function NORMAL mode default value for reset_cmu_gcrx
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMU_GCRX_NORM_SETVAL_O_K2_E5_SHIFT                       1
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUREG_NORM_SETVAL_O_K2_E5                               (0x1<<2) // MSM Function NORMAL mode default value for reset_cmureg
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUREG_NORM_SETVAL_O_K2_E5_SHIFT                         2
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUREGREF_NORM_SETVAL_O_K2_E5                            (0x1<<3) // MSM Function NORMAL mode default value for reset_cmuregref
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUREGREF_NORM_SETVAL_O_K2_E5_SHIFT                      3
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUSYNTH_NORM_SETVAL_O_K2_E5                             (0x1<<4) // MSM Function NORMAL mode default value for reset_cmusynth
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUSYNTH_NORM_SETVAL_O_K2_E5_SHIFT                       4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUVCO_NORM_SETVAL_O_K2_E5                               (0x1<<5) // MSM Function NORMAL mode default value for reset_cmuvco
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUVCO_NORM_SETVAL_O_K2_E5_SHIFT                         5
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_LF_EXTZERO_ENA_NORM_SETVAL_O_K2_E5                             (0x1<<6) // MSM Function NORMAL mode default value for lf_extzero_ena
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_LF_EXTZERO_ENA_NORM_SETVAL_O_K2_E5_SHIFT                       6
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_LFI_EXTZERO_NORM_SETVAL_O_K2_E5                                (0x1<<7) // MSM Function NORMAL mode default value for lfi_extzero
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_LFI_EXTZERO_NORM_SETVAL_O_K2_E5_SHIFT                          7
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_K2_E5                                                            0x00031cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_SOC_CLK_EN_NORM_SETVAL_O_K2_E5                                 (0x1<<0) // MSM Function NORMAL mode default value for soc_clk_en
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_SOC_CLK_EN_NORM_SETVAL_O_K2_E5_SHIFT                           0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_REFCLK_EN_NORM_SETVAL_O_K2_E5                                  (0x1<<1) // MSM Function NORMAL mode default value for refclk_en
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_REFCLK_EN_NORM_SETVAL_O_K2_E5_SHIFT                            1
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_PLL_LOCK_EN_NORM_SETVAL_O_K2_E5                                (0x1<<2) // MSM Function NORMAL mode default value for pll_lock_en
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_PLL_LOCK_EN_NORM_SETVAL_O_K2_E5_SHIFT                          2
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_RESET_TXCLK_NORM_SETVAL_O_K2_E5                                (0x1<<3) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_RESET_TXCLK_NORM_SETVAL_O_K2_E5_SHIFT                          3
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_RESET_CLKDIV_NORM_SETVAL_O_K2_E5                               (0x1<<4) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_RESET_CLKDIV_NORM_SETVAL_O_K2_E5_SHIFT                         4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_NORM_SETVAL_O_K2_E5                                  (0x1<<5) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_NORM_SETVAL_O_K2_E5_SHIFT                            5
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_REFCLK_LEFT_NORM_SETVAL_O_K2_E5                      (0x1<<6) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_REFCLK_LEFT_NORM_SETVAL_O_K2_E5_SHIFT                6
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_REFCLK_RIGHT_NORM_SETVAL_O_K2_E5                     (0x1<<7) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_REFCLK_RIGHT_NORM_SETVAL_O_K2_E5_SHIFT               7
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_K2_E5                                                            0x000320UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_IDDQ_BIAS_PD_SETVAL_O_K2_E5                                    (0x1<<0) // MSM Function POWER DOWN mode default value for iddq_bias
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_IDDQ_BIAS_PD_SETVAL_O_K2_E5_SHIFT                              0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_BIAS_PD_SETVAL_O_K2_E5                                      (0x1<<1) // MSM Function POWER DOWN mode default value for pd_bias
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_BIAS_PD_SETVAL_O_K2_E5_SHIFT                                1
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_RESET_TXCLK_PCS_CLK_PD_SETVAL_O_K2_E5                          (0x1<<2) // MSM Function POWER DOWN mode default value for pcs_clk_ena
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_RESET_TXCLK_PCS_CLK_PD_SETVAL_O_K2_E5_SHIFT                    2
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_CMU_PD_SETVAL_O_K2_E5                                       (0x1<<3) // MSM Function POWER DOWN mode default value for pd_cmu
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_CMU_PD_SETVAL_O_K2_E5_SHIFT                                 3
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_CMUREG_PD_SETVAL_O_K2_E5                                    (0x1<<4) // MSM Function POWER DOWN mode default value for pd_cmureg
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_CMUREG_PD_SETVAL_O_K2_E5_SHIFT                              4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_CMUREGREF_PD_SETVAL_O_K2_E5                                 (0x1<<5) // MSM Function POWER DOWN mode default value for pd_cmuregref
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_CMUREGREF_PD_SETVAL_O_K2_E5_SHIFT                           5
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_REF_PD_SETVAL_O_K2_E5                                       (0x1<<6) // MSM Function POWER DOWN mode default value for pd_ref
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_REF_PD_SETVAL_O_K2_E5_SHIFT                                 6
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_RESET_CMU_FL_PD_SETVAL_O_K2_E5                                 (0x1<<7) // MSM Function POWER DOWN mode default value for reset_cmu_fl
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_RESET_CMU_FL_PD_SETVAL_O_K2_E5_SHIFT                           7
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_K2_E5                                                            0x000324UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMU_PD_SETVAL_O_K2_E5                                    (0x1<<0) // MSM Function POWER DOWN mode default value for reset_cmu
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMU_PD_SETVAL_O_K2_E5_SHIFT                              0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMU_GCRX_PD_SETVAL_O_K2_E5                               (0x1<<1) // MSM Function POWER DOWN mode default value for reset_cmu_gcrx
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMU_GCRX_PD_SETVAL_O_K2_E5_SHIFT                         1
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUREG_PD_SETVAL_O_K2_E5                                 (0x1<<2) // MSM Function POWER DOWN mode default value for reset_cmureg
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUREG_PD_SETVAL_O_K2_E5_SHIFT                           2
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUREGREF_PD_SETVAL_O_K2_E5                              (0x1<<3) // MSM Function POWER DOWN mode default value for reset_cmuregref
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUREGREF_PD_SETVAL_O_K2_E5_SHIFT                        3
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUSYNTH_PD_SETVAL_O_K2_E5                               (0x1<<4) // MSM Function POWER DOWN mode default value for reset_cmusynth
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUSYNTH_PD_SETVAL_O_K2_E5_SHIFT                         4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUVCO_PD_SETVAL_O_K2_E5                                 (0x1<<5) // MSM Function POWER DOWN mode default value for reset_cmuvco
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUVCO_PD_SETVAL_O_K2_E5_SHIFT                           5
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_LF_EXTZERO_ENA_PD_SETVAL_O_K2_E5                               (0x1<<6) // MSM Function POWER DOWN mode default value for lf_extzero_ena
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_LF_EXTZERO_ENA_PD_SETVAL_O_K2_E5_SHIFT                         6
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_LFI_EXTZERO_PD_SETVAL_O_K2_E5                                  (0x1<<7) // MSM Function POWER DOWN mode default value for lfi_extzero
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_LFI_EXTZERO_PD_SETVAL_O_K2_E5_SHIFT                            7
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_K2_E5                                                            0x000328UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_SOC_CLK_EN_PD_SETVAL_O_K2_E5                                   (0x1<<0) // MSM Function POWER DOWN mode default value for soc_clk_en
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_SOC_CLK_EN_PD_SETVAL_O_K2_E5_SHIFT                             0
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_REFCLK_EN_PD_SETVAL_O_K2_E5                                    (0x1<<1) // MSM Function POWER DOWN mode default value for refclk_en
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_REFCLK_EN_PD_SETVAL_O_K2_E5_SHIFT                              1
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_PLL_LOCK_EN_PD_SETVAL_O_K2_E5                                  (0x1<<2) // MSM Function POWER DOWN mode default value for pll_lock_en
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_PLL_LOCK_EN_PD_SETVAL_O_K2_E5_SHIFT                            2
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_RESET_TXCLK_PD_SETVAL_O_K2_E5                                  (0x1<<3) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_RESET_TXCLK_PD_SETVAL_O_K2_E5_SHIFT                            3
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_RESET_CLKDIV_PD_SETVAL_O_K2_E5                                 (0x1<<4) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_RESET_CLKDIV_PD_SETVAL_O_K2_E5_SHIFT                           4
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_PD_SETVAL_O_K2_E5                                    (0x1<<5) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_PD_SETVAL_O_K2_E5_SHIFT                              5
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_REFCLK_LEFT_PD_SETVAL_O_K2_E5                        (0x1<<6) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_REFCLK_LEFT_PD_SETVAL_O_K2_E5_SHIFT                  6
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_REFCLK_RIGHT_PD_SETVAL_O_K2_E5                       (0x1<<7) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_REFCLK_RIGHT_PD_SETVAL_O_K2_E5_SHIFT                 7
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X210_K2_E5                                                            0x000348UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X0_K2_E5                                                             0x001000UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH1_SRC_SEL_O_K2_E5                                (0x7<<0) // Clock source select for TX path branch 1 clock :  3'b000 - lnX_clk_i 3'b001- qd_ck_i 3'b010 - pma_lX_rxb_iRecovered byte clock 3'b011 - ck_soc1_int_root 3'b100,3'b101,3'b110 - Reserved 3'b111 - test_clk_0_i
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH1_SRC_SEL_O_K2_E5_SHIFT                          0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH1_DIV_SEL_O_K2_E5                                (0x1<<3) // Clock divider for TX path branch 1 : 0-No division, 1- Divide by 2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH1_DIV_SEL_O_K2_E5_SHIFT                          3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH2_SRC_SEL_O_K2_E5                                (0x7<<4) // Clock source select for TX path branch 2 clock : 3'b000 - lnX_clk_i 3'b001- qd_ck_i 3'b011 - ck_soc1_int_root 3'b010,3'b100,3'b101,3'b110 - Reserved 3'b111 - test_clk_0_i
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH2_SRC_SEL_O_K2_E5_SHIFT                          4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O_K2_E5                                (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O_K2_E5_SHIFT                          7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X1_K2_E5                                                             0x001004UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH1_SRC_SEL_O_K2_E5                                (0x7<<0) // Clock source select for RX path branch 1 clock : 3'b000 - pma_lX_rxb_iRecovered byte clock 3'b001- pma_lX_txb_iTransmit byte clock 3'b010,3'b011,3'b100,3'b101,3'b110 - Reserved 3'b111 - test_clk_1_i
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH1_SRC_SEL_O_K2_E5_SHIFT                          0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O_K2_E5                                (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O_K2_E5_SHIFT                          3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH2_SRC_SEL_O_K2_E5                                (0x7<<4) // Clock source select for RX path branch 2 clock : 3'b000 - pma_lX_rxb_iRecovered byte clock 3'b001- pma_lX_txb_iTransmit byte clock 3'b010,3'b011,3'b100,3'b101,3'b110 - Reserved 3'b111 - test_clk_1_i
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH2_SRC_SEL_O_K2_E5_SHIFT                          4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O_K2_E5                                (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O_K2_E5_SHIFT                          7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X2_K2_E5                                                             0x001008UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH3_SRC_SEL_O_K2_E5                                (0x7<<0) // Clock source select for RX path branch 3 clock : 3'b000 - qd_ck_i 3'b001- pma_lX_rxb_iRecovered byte clock 3'b010 - lnX_clk_i 3'b011 - pma_lX_txb_iTransmit byte clock 3'b100 - ck_soc1_int_root 3'b101,3'b110 - Reserved 3'b111 - test_clk_1_i
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH3_SRC_SEL_O_K2_E5_SHIFT                          0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH3_DIV_SEL_O_K2_E5                                (0x1<<3) // Clock divider for RX path branch 3 : 0-No division, 1- Divide by 2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH3_DIV_SEL_O_K2_E5_SHIFT                          3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH4_SRC_SEL_O_K2_E5                                (0x7<<4) // Clock source select for RX path branch 4 clock : 3'b000 - qd_ck_i 3'b001- pma_lX_rxb_iRecovered byte clock 3'b010 - lnX_clk_i 3'b011 - pma_lX_txb_iTransmit byte clock 3'b100 - ck_soc1_int_root 3'b101,3'b110 - Reserved 3'b111 - test_clk_1_i
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH4_SRC_SEL_O_K2_E5_SHIFT                          4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O_K2_E5                                (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O_K2_E5_SHIFT                          7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X3_K2_E5                                                             0x00100cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X3_PMA_CMU_SEL_O_0_K2_E5                                           (0x1<<0) // CMU Select for lane  0 -	 Select CMU0  1 -	 Select CMU1
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X3_PMA_CMU_SEL_O_0_K2_E5_SHIFT                                     0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X3_PMA_TXCLK_SEL_O_1_K2_E5                                         (0x1<<1) // PMA TX Clock Select for TX CDR VCO  0 -	 CMU0 Clock  1 -	 CMU1 Clock
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X3_PMA_TXCLK_SEL_O_1_K2_E5_SHIFT                                   1
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X4_K2_E5                                                             0x001010UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X4_CDRCTRL_DIV_EN_O_1_0_K2_E5                                      (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Divide by 4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X4_CDRCTRL_DIV_EN_O_1_0_K2_E5_SHIFT                                0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X4_GCFSM_DIV_EN_O_1_0_K2_E5                                        (0x3<<2) // Static divider control for Lane GCFSM clock The only access to this divider. Not an override 4d0:  No division  4d1:  /2 4d2:  /2 4d3:  /4:
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X4_GCFSM_DIV_EN_O_1_0_K2_E5_SHIFT                                  2
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X5_K2_E5                                                             0x001014UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X5_REF_CLK_DIV_EN_O_1_0_K2_E5                                      (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X5_REF_CLK_DIV_EN_O_1_0_K2_E5_SHIFT                                0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X5_OOB_CLK_DIV_EN_O_1_0_K2_E5                                      (0x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X5_OOB_CLK_DIV_EN_O_1_0_K2_E5_SHIFT                                2
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_K2_E5                                                             0x00101cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_RATE_O_K2_E5                                               (0x3<<0) // Rate control for BIST
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_RATE_O_K2_E5_SHIFT                                         0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_MODE8B_O_K2_E5                                         (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Generated data word is 8 bits
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_MODE8B_O_K2_E5_SHIFT                                   2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_ERR_O_K2_E5                                            (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 - BIST generator outputs erroneous pattern.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_ERR_O_K2_E5_SHIFT                                      3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_TX_CLOCK_ENABLE_K2_E5                                      (0x1<<4) // Active HIGH clock enable signal for the BIST transmit clock
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_TX_CLOCK_ENABLE_K2_E5_SHIFT                                4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_CDN_O_K2_E5                                            (0x1<<5) // Bist generator master reset.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_CDN_O_K2_E5_SHIFT                                      5
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_WORD_O_K2_E5                                           (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 1 - Bist generator generates double word 16 or 20
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_WORD_O_K2_E5_SHIFT                                     6
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_EN_O_K2_E5                                             (0x1<<7) // Bist generator enable.  0 - Bist generator idle. 1 - Bist generator generates data
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_EN_O_K2_E5_SHIFT                                       7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X8_K2_E5                                                             0x001020UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_CLK_SEL_O_2_0_K2_E5                                    (0x7<<0) // BIST Generation Clock Selection
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_CLK_SEL_O_2_0_K2_E5_SHIFT                              0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_SEND_PREAM_O_K2_E5                                     (0x1<<3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - Bist generator sends preamble.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_SEND_PREAM_O_K2_E5_SHIFT                               3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_INSERT_COUNT_O_2_0_K2_E5                               (0x7<<4) // Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is ever inserted into the stream. In 20-bit mode, the product of bist_gen_insert_length x bist_gen_insert_count must be even.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_INSERT_COUNT_O_2_0_K2_E5_SHIFT                         4
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X9_K2_E5                                                             0x001024UL //Access:RW   DataWidth:0x8    // Bist generator low-period control. If not 0, output data enable will be low for this number of words, and then high for en_high_i_X:0 number of words, repeating. If 0, data output enable will be asserted for entire test.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X10_K2_E5                                                            0x001028UL //Access:RW   DataWidth:0x8    // Bist generator low-period control. If not 0, output data enable will be low for this number of words, and then high for en_high_i_X:0 number of words, repeating. If 0, data output enable will be asserted for entire test.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X11_K2_E5                                                            0x00102cUL //Access:RW   DataWidth:0x8    // Bist generator high-period control. Refer to bist_gen_en_low_o and BIST documentation for further information.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X12_K2_E5                                                            0x001030UL //Access:RW   DataWidth:0x8    // Bist generator high-period control. Refer to bist_gen_en_low_o and BIST documentation for further information.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X13_K2_E5                                                            0x001034UL //Access:RW   DataWidth:0x8    // Bist generator - Number of words between insert word insertions. Insertions are done in both pream and data transmission. In 20-bit mode, this number must be even.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X14_K2_E5                                                            0x001038UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X14_BIST_GEN_INSERT_DELAY_O_11_8_K2_E5                             (0xf<<0) // Bist generator - Number of words between insert word insertions. Insertions are done in both pream and data transmission. In 20-bit mode, this number must be even.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X14_BIST_GEN_INSERT_DELAY_O_11_8_K2_E5_SHIFT                       0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X14_BCHK_EN_O_K2_E5                                                (0x1<<5) // BIST checker enable Enables BIST RX Control block, which enables the actual BIST RX block when appropriate
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X14_BCHK_EN_O_K2_E5_SHIFT                                          5
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X14_BCHK_CLR_O_K2_E5                                               (0x1<<6) // BIST checker clear signal. Zeroes error counter output. Does NOT go through the RX BIST control block
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X14_BCHK_CLR_O_K2_E5_SHIFT                                         6
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_K2_E5                                                            0x00103cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_BCHK_SRC_O_1_0_K2_E5                                           (0x3<<0) // BIST checker source. 0 - BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Aligner before Elastic Buffer 2 - BIST uses output of RX loopback mux before Decoder and Polbits 3 - BIST uses output of reg1 flop bank before Interface blocks
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_BCHK_SRC_O_1_0_K2_E5_SHIFT                                     0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_BIST_CHK_DATA_MODE_O_K2_E5                                     (0x1<<3) // Bist checker mode select. 0X0  UDP pattern. 0x1  PRBS pattern
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_BIST_CHK_DATA_MODE_O_K2_E5_SHIFT                               3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_BIST_CHK_LFSR_LENGTH_O_1_0_K2_E5                               (0x3<<4) // BIST PRBS pattern selector.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_BIST_CHK_LFSR_LENGTH_O_1_0_K2_E5_SHIFT                         4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_BIST_RX_CLOCK_ENABLE_K2_E5                                     (0x1<<7) // Active HIGH clock enable signal for the BIST receive clock
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_BIST_RX_CLOCK_ENABLE_K2_E5_SHIFT                               7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X16_K2_E5                                                            0x001040UL //Access:RW   DataWidth:0x8    // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This word should correspond to the alignment character used for the symbol alignment block.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X17_K2_E5                                                            0x001044UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_PREAM0_O_9_8_K2_E5                                    (0x3<<0) // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This word should correspond to the alignment character used for the symbol alignment block.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_PREAM0_O_9_8_K2_E5_SHIFT                              0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_INSERT_LENGTH_O_2_0_K2_E5                             (0x7<<2) // BIST Checker Insert word length.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_INSERT_LENGTH_O_2_0_K2_E5_SHIFT                       2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_SYNC_ON_ZEROS_K2_E5                                   (0x1<<5) // Setting this bit allows BIST to sync to RX value of zero
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_SYNC_ON_ZEROS_K2_E5_SHIFT                             5
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X18_K2_E5                                                            0x001048UL //Access:RW   DataWidth:0x8    // BIST Check Preamble
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X19_K2_E5                                                            0x00104cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X19_BIST_CHK_PREAM1_O_9_8_K2_E5                                    (0x3<<0) // BIST Check Preamble
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X19_BIST_CHK_PREAM1_O_9_8_K2_E5_SHIFT                              0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X20_K2_E5                                                            0x001050UL //Access:RW   DataWidth:0x8    // Bist checker 40-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corresponds to 5 8-bit words. K code is assumed to be 0 in 8-bit mode.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X21_K2_E5                                                            0x001054UL //Access:RW   DataWidth:0x8    // BIST Check User-defined pattern
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X22_K2_E5                                                            0x001058UL //Access:RW   DataWidth:0x8    // BIST Check User-defined pattern
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X23_K2_E5                                                            0x00105cUL //Access:RW   DataWidth:0x8    // BIST Check User-defined pattern
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X24_K2_E5                                                            0x001060UL //Access:RW   DataWidth:0x8    // BIST Check User-defined pattern
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X25_K2_E5                                                            0x001064UL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X26_K2_E5                                                            0x001068UL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X27_K2_E5                                                            0x00106cUL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X28_K2_E5                                                            0x001070UL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X29_K2_E5                                                            0x001074UL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X30_K2_E5                                                            0x001078UL //Access:R    DataWidth:0x8    // Bist errors detected
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X31_K2_E5                                                            0x00107cUL //Access:R    DataWidth:0x8    // Bist errors detected
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X32_K2_E5                                                            0x001080UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 7-0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X33_K2_E5                                                            0x001084UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 15-8
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X34_K2_E5                                                            0x001088UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 23-16
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X35_K2_E5                                                            0x00108cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 31-24
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X36_K2_E5                                                            0x001090UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 39-32
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X37_K2_E5                                                            0x001094UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 47-40
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X38_K2_E5                                                            0x001098UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 55-48
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X39_K2_E5                                                            0x00109cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 63-56
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X40_K2_E5                                                            0x0010a0UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 71-64
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X41_K2_E5                                                            0x0010a4UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 79-72
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X42_K2_E5                                                            0x0010a8UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 87-80
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X43_K2_E5                                                            0x0010acUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 95-88
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X44_K2_E5                                                            0x0010b0UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 103-96
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X45_K2_E5                                                            0x0010b4UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 111-104
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X46_K2_E5                                                            0x0010b8UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 119-112
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X47_K2_E5                                                            0x0010bcUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 127-120
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X48_K2_E5                                                            0x0010c0UL //Access:RW   DataWidth:0x8    // Timing Window length for GCFSM for Gen 1/2 - for the new ICA method
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X49_K2_E5                                                            0x0010c4UL //Access:RW   DataWidth:0x8    // Timing Window length for GCFSM for Gen 3 - for the new ICA method
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X50_K2_E5                                                            0x0010c8UL //Access:RW   DataWidth:0x8    // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA method
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X51_K2_E5                                                            0x0010ccUL //Access:RW   DataWidth:0x8    // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA method
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X52_K2_E5                                                            0x0010d0UL //Access:RW   DataWidth:0x8    // The start length of DFE offset calibration's first cycle is the value of this register multiplied by 4.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X53_K2_E5                                                            0x0010d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_DFE_OFFSET_CAL_START_LEN_O_4_0_K2_E5                     (0x1f<<0) // The start length of DFE offset calibration, except for the 1st cycle.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_DFE_OFFSET_CAL_START_LEN_O_4_0_K2_E5_SHIFT               0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2_K2_E5                              (0x1<<5) // COMLANE or LANE CSR Select for GCFSM Cycle Length registers  0 -	 Select COMLANE registers  1 -	 Select LANE registers
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2_K2_E5_SHIFT                        5
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_LANE_TW_METHOD_EN_K2_E5                                  (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_LANE_TW_METHOD_EN_K2_E5_SHIFT                            6
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_LANE_PMA_LOAD_OVR_K2_E5                                  (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_LANE_PMA_LOAD_OVR_K2_E5_SHIFT                            7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X54_K2_E5                                                            0x0010d8UL //Access:RW   DataWidth:0x8    // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X55_K2_E5                                                            0x0010dcUL //Access:RW   DataWidth:0x8    // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X56_K2_E5                                                            0x0010e0UL //Access:RW   DataWidth:0x8    // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_K2_E5                                                            0x0010e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_OVR_O_27_24_K2_E5                                        (0xf<<0) // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_OVR_O_27_24_K2_E5_SHIFT                                  0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_OUT_OVR_EN_O_K2_E5                                  (0x1<<4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes data stored in gcfsm_lane_pma_data_ovr_o to override calibration values for the block selected by gcfsm_lane_pma_cal_ovr_o.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_OUT_OVR_EN_O_K2_E5_SHIFT                            4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_LATCH_OVR_O_K2_E5                               (0x1<<5) // GCFSM pma_latch_o override
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_LATCH_OVR_O_K2_E5_SHIFT                         5
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_GO_OVR_O_K2_E5                                  (0x1<<6) // GCFSM pma_go_o override
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_GO_OVR_O_K2_E5_SHIFT                            6
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_READ_OVR_O_K2_E5                                (0x1<<7) // GCFSM pma_read_o override.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_READ_OVR_O_K2_E5_SHIFT                          7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X58_K2_E5                                                            0x0010e8UL //Access:RW   DataWidth:0x8    // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X59_K2_E5                                                            0x0010ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X59_GCFSM_LANE_PMA_DATA_OVR_O_11_8_K2_E5                           (0xf<<0) // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X59_GCFSM_LANE_PMA_DATA_OVR_O_11_8_K2_E5_SHIFT                     0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X60_K2_E5                                                            0x0010f0UL //Access:RW   DataWidth:0x8    // General Calibration Finite State Machine GCFSM overide select, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA compone
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X61_K2_E5                                                            0x0010f4UL //Access:RW   DataWidth:0x8    // General Calibration Finite State Machine GCFSM overide select, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA compone
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X62_K2_E5                                                            0x0010f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X62_LN_MSM_REQ_IN_OVR_O_K2_E5                                      (0x3<<0) // Bit 0:  Override enable for msm_ln_req Bit 1 : Override msm_ln_req
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X62_LN_MSM_REQ_IN_OVR_O_K2_E5_SHIFT                                0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X62_LN_MSM_FUNC_IN_OVR_O_K2_E5                                     (0x3f<<2) // Bit 2:  Override enable for msm_func Bits [7:3] : Override msm_func
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X62_LN_MSM_FUNC_IN_OVR_O_K2_E5_SHIFT                               2
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG41_K2_E5                                                  0x0010fcUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG42_K2_E5                                                  0x001100UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X65_K2_E5                                                            0x001104UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X65_GCFSM_OVR_O_28_K2_E5                                           (0x1<<0) // Not currently used
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X65_GCFSM_OVR_O_28_K2_E5_SHIFT                                     0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X66_K2_E5                                                            0x001108UL //Access:RW   DataWidth:0x8    // Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X67_K2_E5                                                            0x00110cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X67_CDR_CTRL_DLY_CDR_O_6_0_K2_E5                                   (0x7f<<0) // Number of clock cycles between signal detect indicator
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X67_CDR_CTRL_DLY_CDR_O_6_0_K2_E5_SHIFT                             0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_K2_E5                              (0x1<<7) // Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_K2_E5_SHIFT                        7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X68_K2_E5                                                            0x001110UL //Access:RW   DataWidth:0x8    // Number of clock cycles between CISEL assertion
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X69_K2_E5                                                            0x001114UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X69_CDR_CTRL_DLY_LANE_O_9_8_K2_E5                                  (0x3<<0) // Number of clock cycles between CISEL assertion
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X69_CDR_CTRL_DLY_LANE_O_9_8_K2_E5_SHIFT                            0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X69_CDR_CTRL_START_LEN_O_3_0_K2_E5                                 (0xf<<2) // Number of clock cycles between when CDR control block
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X69_CDR_CTRL_START_LEN_O_3_0_K2_E5_SHIFT                           2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X69_CDR_CTRL_INT_FIL_O_1_0_K2_E5                                   (0x3<<6) // CDR control DLPF positioning control.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X69_CDR_CTRL_INT_FIL_O_1_0_K2_E5_SHIFT                             6
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X70_K2_E5                                                            0x001118UL //Access:RW   DataWidth:0x8    // CDR control block cycle length When not in PCIe Gen3.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X72_K2_E5                                                            0x001120UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X72_CDR_CTRL_MAX_DIFF_O_4_0_K2_E5                                  (0x1f<<0) // Maximum difference from DLPF center point.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X72_CDR_CTRL_MAX_DIFF_O_4_0_K2_E5_SHIFT                            0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X72_CDR_CTRL_MIN_BOUNCE_O_2_0_K2_E5                                (0x7<<5) // Maximum difference from DLPF center point.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X72_CDR_CTRL_MIN_BOUNCE_O_2_0_K2_E5_SHIFT                          5
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X73_K2_E5                                                            0x001124UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X73_CDR_CTRL_TW_METHOD_EN_K2_E5                                    (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X73_CDR_CTRL_TW_METHOD_EN_K2_E5_SHIFT                              0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X73_CDR_CONTROL_ATT_CTRL_O_K2_E5                                   (0x1<<1) // ATT wait control. Upon detection of signal, DFE ATT calibration is enabled, without CISEL being asserted to the CDR.  0 - CDR control block will wait for ATT calibration before proceeding 1 - CDR control block will not wait for ATT calibration
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X73_CDR_CONTROL_ATT_CTRL_O_K2_E5_SHIFT                             1
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X73_RXEQ_WAIT_EN_O_K2_E5                                           (0x1<<2) // CDR control block wait for DFE signal.  0 - Do not wait for DFE calibration before enabling rx data 1 - Wait for DFE calibration before enabling rx data
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X73_RXEQ_WAIT_EN_O_K2_E5_SHIFT                                     2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X73_CDR_CTRL_DLY_CDR_O_9_7_K2_E5                                   (0x7<<3) // Number of clock cycles between signal detect indicator
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X73_CDR_CTRL_DLY_CDR_O_9_7_K2_E5_SHIFT                             3
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X74_K2_E5                                                            0x001128UL //Access:RW   DataWidth:0x8    // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X75_K2_E5                                                            0x00112cUL //Access:RW   DataWidth:0x8    // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X76_K2_E5                                                            0x001130UL //Access:RW   DataWidth:0x8    // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X77_K2_E5                                                            0x001134UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X77_CDR_CTRL_OUT_OVR_O_29_24_K2_E5                                 (0x3f<<0) // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X77_CDR_CTRL_OUT_OVR_O_29_24_K2_E5_SHIFT                           0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X77_CDR_CTRL_CAL_LOAD_OVR_K2_E5                                    (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X77_CDR_CTRL_CAL_LOAD_OVR_K2_E5_SHIFT                              6
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X78_K2_E5                                                            0x001138UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X78_SYM_ALIGN_ALIGN_POS_O_5_0_K2_E5                                (0x3f<<0) // Symbol aligner position override enable.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X78_SYM_ALIGN_ALIGN_POS_O_5_0_K2_E5_SHIFT                          0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X78_SYM_ALIGN_MODE_O_1_0_K2_E5                                     (0x3<<6) // Symbol aligner mode select.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X78_SYM_ALIGN_MODE_O_1_0_K2_E5_SHIFT                               6
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X79_K2_E5                                                            0x00113cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X79_SYM_ALIGN_BYPASS_O_K2_E5                                       (0x1<<0) // Asserting this register will bypass the symbol aligner
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X79_SYM_ALIGN_BYPASS_O_K2_E5_SHIFT                                 0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X80_K2_E5                                                            0x001140UL //Access:RW   DataWidth:0x8    // Number of cycles to wait before forcing exit form EI
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_K2_E5                                                            0x001144UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EXIT_TIMER_LEN_O_9_8_K2_E5                       (0x3<<0) // Number of cycles to wait before forcing exit form EI
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EXIT_TIMER_LEN_O_9_8_K2_E5_SHIFT                 0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_CLR_ERR_O_K2_E5                                  (0x1<<2) // Clears the elec idle control error flag
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_CLR_ERR_O_K2_E5_SHIFT                            2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EI_INFERRED_O_K2_E5                              (0x1<<3) // Override for ei_inferred signal
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EI_INFERRED_O_K2_E5_SHIFT                        3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O_K2_E5                           (0x1<<4) // Override for ei_mask signal
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O_K2_E5_SHIFT                     4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O_K2_E5                            (0x1<<5) // Override for ei_exit_type signal
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O_K2_E5_SHIFT                      5
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_OVR_O_K2_E5                                      (0x1<<6) // EI control override enable
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_OVR_O_K2_E5_SHIFT                                6
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X82_K2_E5                                                            0x001148UL //Access:RW   DataWidth:0x8    // Number of cycles to wait before entering back into EI
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X83_K2_E5                                                            0x00114cUL //Access:RW   DataWidth:0x8    // Electrical Idle Control signal detect glitch filter counter
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X84_K2_E5                                                            0x001150UL //Access:RW   DataWidth:0x8    // Electrical Idle Control signal detect low filter min value
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X85_K2_E5                                                            0x001154UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X85_ELECIDLE_CTRL_LOCK_TIMER_LEN_O_9_8_K2_E5                       (0x3<<0) // Number of cycles to wait before entering back into EI
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X85_ELECIDLE_CTRL_LOCK_TIMER_LEN_O_9_8_K2_E5_SHIFT                 0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X85_ELECIDLE_CTRL_TIMER_LEN_SEL_O_1_0_K2_E5                        (0x3<<2) // EI Exit time cycles = timer_len_sel[1:0]+1*exit_timer_len_i[9:0]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X85_ELECIDLE_CTRL_TIMER_LEN_SEL_O_1_0_K2_E5_SHIFT                  2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X85_LOOPBACK_EN_O_K2_E5                                            (0x1<<4) // Control signal to force decoder into loopback mode
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X85_LOOPBACK_EN_O_K2_E5_SHIFT                                      4
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X86_K2_E5                                                            0x001158UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X86_FES_LB_ENA_O_K2_E5                                             (0x1<<0) // FES loopback enable.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X86_FES_LB_ENA_O_K2_E5_SHIFT                                       0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X86_NES_LB_ENA_O_K2_E5                                             (0x1<<1) // NES loopback enable.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X86_NES_LB_ENA_O_K2_E5_SHIFT                                       1
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X86_RXCLK_LB_ENA_O_K2_E5                                           (0x1<<2) // HS recovered clock to transmit loopback enable.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X86_RXCLK_LB_ENA_O_K2_E5_SHIFT                                     2
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X87_K2_E5                                                            0x00115cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X87_AHB_PMA_LN_RX_BOOST_OVR_O_K2_E5                                (0x1<<0) // RX boost override enable
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X87_AHB_PMA_LN_RX_BOOST_OVR_O_K2_E5_SHIFT                          0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_K2_E5                             (0x7f<<1) // RX boost override setting. Thermometer coded.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_K2_E5_SHIFT                       1
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X88_K2_E5                                                            0x001160UL //Access:RW   DataWidth:0x8    // RX boost override setting. Thermometer coded.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X89_K2_E5                                                            0x001164UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_SD_THSEL_DIV1_O_K2_E5                               (0x7<<0) // Signal detect threshold select for Full rate
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_SD_THSEL_DIV1_O_K2_E5_SHIFT                         0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_SD_THSEL_DIV2_O_K2_E5                               (0x7<<3) // Signal detect threshold select for div-by-2 rate
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_SD_THSEL_DIV2_O_K2_E5_SHIFT                         3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_RXUP_O_K2_E5                                        (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_RXUP_O_K2_E5_SHIFT                                  6
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_K2_E5                               (0x1<<7) // RX FL calibration clock DIV4 enable
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_K2_E5_SHIFT                         7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X90_K2_E5                                                            0x001168UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_SD_THSEL_DIV4_O_K2_E5                               (0x7<<0) // Signal detect threshold select for div-by-4 rate
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_SD_THSEL_DIV4_O_K2_E5_SHIFT                         0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_AGC_THSEL_O_K2_E5                                   (0x7<<3) // AGC threshold select
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_AGC_THSEL_O_K2_E5_SHIFT                             3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_VREGH_O_K2_E5                                       (0x3<<6) // Regulator VREGH setting
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_VREGH_O_K2_E5_SHIFT                                 6
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X91_K2_E5                                                            0x00116cUL //Access:RW   DataWidth:0x8    // RX FL calibration LDHS
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X92_K2_E5                                                            0x001170UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_RXFL_LDHS_O_9_8_K2_E5                               (0x3<<0) // RX FL calibration LDHS
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_RXFL_LDHS_O_9_8_K2_E5_SHIFT                         0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_RXVCO_BIAS_O_K2_E5                                  (0xf<<2) // CDR VCO bias setting.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_RXVCO_BIAS_O_K2_E5_SHIFT                            2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O_K2_E5                               (0x1<<6) // DLPF DIV2 enable
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O_K2_E5_SHIFT                         6
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_K2_E5                                (0x1<<7) // CDR DivN clock divider enable.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_K2_E5_SHIFT                          7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X93_K2_E5                                                            0x001174UL //Access:RW   DataWidth:0x8    // AFE spare controls
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X94_K2_E5                                                            0x001178UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X94_AHB_PMA_LN_CDR_DVDR_O_K2_E5                                    (0x3f<<0) // CDR DivN clock division ratio.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X94_AHB_PMA_LN_CDR_DVDR_O_K2_E5_SHIFT                              0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X94_AHB_PMA_LN_VREG_O_K2_E5                                        (0x3<<6) // Regulator VREG setting
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X94_AHB_PMA_LN_VREG_O_K2_E5_SHIFT                                  6
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X95_K2_E5                                                            0x00117cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_BB_STEP_O_K2_E5                                     (0xf<<0) // CDR bb_step
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_BB_STEP_O_K2_E5_SHIFT                               0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_INT_STEP_O_K2_E5                                    (0x7<<4) // CDR int step
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_INT_STEP_O_K2_E5_SHIFT                              4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_RXDWN_O_K2_E5                                       (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_RXDWN_O_K2_E5_SHIFT                                 7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X96_K2_E5                                                            0x001180UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RXVCOFR_O_K2_E5                                     (0x7<<0) // RXVCOFR override value Enabled by pma_ln_dr_rxvcofr_sel_o
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RXVCOFR_O_K2_E5_SHIFT                               0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RXVCOFR_SEL_O_K2_E5                                 (0x1<<3) // Override enable for RXVCOFR override vakue
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RXVCOFR_SEL_O_K2_E5_SHIFT                           3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RX_SELR_O_K2_E5                                     (0x7<<4) // CTLE R degeneration select
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RX_SELR_O_K2_E5_SHIFT                               4
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X97_K2_E5                                                            0x001184UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X97_AHB_PMA_LN_RX_SELC_O_K2_E5                                     (0x7<<0) // CTLE C degeneration select
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X97_AHB_PMA_LN_RX_SELC_O_K2_E5_SHIFT                               0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG43_K2_E5                                                  0x001188UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X99_K2_E5                                                            0x00118cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X99_PMA_LN_DFE_BW_SCALE_K2_E5                                      (0x3<<4) // DFE Bandwidth Selection
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X99_PMA_LN_DFE_BW_SCALE_K2_E5_SHIFT                                4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X99_PMA_LN_PHD_ENA_O_1_0_K2_E5                                     (0x3<<6) // CDR phase detector proportional path enable bit 0: enables D4/D3 data/edge samplers bit 1: enables D1/D2 data/edge samplers
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X99_PMA_LN_PHD_ENA_O_1_0_K2_E5_SHIFT                               6
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X100_K2_E5                                                           0x001190UL //Access:RW   DataWidth:0x8    // On-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 3-9: Fine x-direction offset, note bit reversal
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_K2_E5                                                           0x001194UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_DLY_O_8_8_K2_E5                                    (0x1<<0) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 2-8: Fine x-direction offset, note bit reversal
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_DLY_O_8_8_K2_E5_SHIFT                              0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_SGN_RST_O_K2_E5                                    (0x1<<2) // Reset signal for eye alignment mechanism.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_SGN_RST_O_K2_E5_SHIFT                              2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_SD_BWSEL_K2_E5                                         (0x1<<3) // RX signal detector bandwidth select. 0: Nominal bandwidth 1: 10% higher bandwidth
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_SD_BWSEL_K2_E5_SHIFT                                   3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_ENA270_O_K2_E5                                     (0x1<<4) // In eye diagram generation mode, assertion overrides the ck_270 DFE clock "right" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_ENA270_O_K2_E5_SHIFT                               4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_ENA90_O_K2_E5                                      (0x1<<5) // In eye diagram generation mode, assertion overrides the ck_90 DFE clock "left" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_ENA90_O_K2_E5_SHIFT                                5
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X102_K2_E5                                                           0x001198UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X102_PMA_LN_DFE_BIAS_O_3_0_K2_E5                                   (0xf<<0) // DFE bias setting.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X102_PMA_LN_DFE_BIAS_O_3_0_K2_E5_SHIFT                             0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X103_K2_E5                                                           0x00119cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X103_PMA_LN_TX_SR_FASTCAP_O_3_0_K2_E5                              (0xf<<0) // TX driver capacitive slew rate control.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X103_PMA_LN_TX_SR_FASTCAP_O_3_0_K2_E5_SHIFT                        0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X103_PMA_LN_TXEQ_POLARITY_O_3_0_K2_E5                              (0xf<<4) // TX coefficient polarity enable. Set to "1" for negative polarity. bit 0: Cm bit 1: C0 bit 2: C1
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X103_PMA_LN_TXEQ_POLARITY_O_3_0_K2_E5_SHIFT                        4
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X104_K2_E5                                                           0x0011a0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X104_PMA_LN_TX_SR_DAC_O_3_0_K2_E5                                  (0xf<<0) // TX slew rate DAC bias current control
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X104_PMA_LN_TX_SR_DAC_O_3_0_K2_E5_SHIFT                            0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X104_PMA_LN_HSCLK_SEL_O_K2_E5                                      (0x1<<4) // CDR clock divider bypass enable.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X104_PMA_LN_HSCLK_SEL_O_K2_E5_SHIFT                                4
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X105_K2_E5                                                           0x0011a4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X105_PMA_LN_TX_VREG_LEV_O_4_0_K2_E5                                (0x1f<<0) // TX driver regulator voltage setting.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X105_PMA_LN_TX_VREG_LEV_O_4_0_K2_E5_SHIFT                          0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X105_PMA_LN_TXDRV_BLEED_ENA_O_K2_E5                                (0x1<<5) // TX bleed enable
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X105_PMA_LN_TXDRV_BLEED_ENA_O_K2_E5_SHIFT                          5
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X115_K2_E5                                                           0x0011ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG44_K2_E5                                                  0x0011d0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG45_K2_E5                                                  0x0011d4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG46_K2_E5                                                  0x0011d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X119_K2_E5                                                           0x0011dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X119_AHB_TX_CXP_MARGIN_K2_E5                                       (0xf<<0) // Value to minus/add from the calibrated txterm value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X119_AHB_TX_CXP_MARGIN_K2_E5_SHIFT                                 0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X119_AHB_TX_CXN_MARGIN_K2_E5                                       (0xf<<4) // Value to minus/add from the calibrated txterm value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X119_AHB_TX_CXN_MARGIN_K2_E5_SHIFT                                 4
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X120_K2_E5                                                           0x0011e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X120_AHB_TX_TC_WAIT_NEXT_CMP_K2_E5                                 (0xf<<0) // in txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator  the register ix X2 is the actual number of wait cycle
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X120_AHB_TX_TC_WAIT_NEXT_CMP_K2_E5_SHIFT                           0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X120_AHB_TX_TC_WAIT_NEXT_SAMPLE_K2_E5                              (0x7<<4) // in txterm calibration, the number refclk cycles to wait before sampling the up from the same comparator
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X120_AHB_TX_TC_WAIT_NEXT_SAMPLE_K2_E5_SHIFT                        4
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_K2_E5                                                           0x0011e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_TC_CMP_OUT_NUM_SAMPLES_K2_E5                           (0xf<<0) // in txterm calibration, the number of samples to take from the same comparator
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_TC_CMP_OUT_NUM_SAMPLES_K2_E5_SHIFT                     0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CXP_MARGIN_ADD_0_K2_E5                                 (0x1<<4) // when 1, the final tx term value is calibrated txterm value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CXP_MARGIN_ADD_0_K2_E5_SHIFT                           4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CXN_MARGIN_ADD_0_K2_E5                                 (0x1<<5) // when 1, the final tx term value is calibrated txterm value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CXN_MARGIN_ADD_0_K2_E5_SHIFT                           5
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CX_OVR_ENA_K2_E5                                       (0x1<<6) // enable override calibrated txterm value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CX_OVR_ENA_K2_E5_SHIFT                                 6
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_TERM_EN_CAL_OVR_K2_E5                                  (0x1<<7) // Debug feature, when set forces circuit to be affected by ahb_tx_cdac_ovr
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_TERM_EN_CAL_OVR_K2_E5_SHIFT                            7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X122_K2_E5                                                           0x0011e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X122_AHB_TX_CXP_OVR_K2_E5                                          (0xf<<0) // override calibrated txterm value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X122_AHB_TX_CXP_OVR_K2_E5_SHIFT                                    0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X122_AHB_TX_CXN_OVR_K2_E5                                          (0xf<<4) // override calibrated txterm value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X122_AHB_TX_CXN_OVR_K2_E5_SHIFT                                    4
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X123_K2_E5                                                           0x0011ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X123_TX_CTRL_O_0_K2_E5                                             (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not currently used
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X123_TX_CTRL_O_0_K2_E5_SHIFT                                       0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X123_TX_CTRL_O_7_2_K2_E5                                           (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_slew_sld[1:0]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X123_TX_CTRL_O_7_2_K2_E5_SHIFT                                     2
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X124_K2_E5                                                           0x0011f0UL //Access:RW   DataWidth:0x8    // Bits 12:8: txdrv_c1_in[4:0] Bits 15:13: txdrv_c2_in[2:0]
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X125_K2_E5                                                           0x0011f4UL //Access:RW   DataWidth:0x8    // Bits 19-16: txdrv_cm_in[3:0]  Bits 22-20: tx_slew_sld3f[2:0] Bit 23: txdrv_preem_1lsb_mode
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_K2_E5                                                           0x0011f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_EN_O_K2_E5                                               (0x1<<0) // DFE block enable signal.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_EN_O_K2_E5_SHIFT                                         0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE_OW_O_2_0_K2_E5                                   (0x7<<1) // These bits have similar functionality as rxeq_rate_ow_o_2_0 bits in COMLANE CSR. These are used mainly in COMBINATION modes of operation. They are logically OR'ed with the bits in COMLANE.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE_OW_O_2_0_K2_E5_SHIFT                             1
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE1_CAL_EN_O_3_K2_E5                                (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE1_CAL_EN_O_3_K2_E5_SHIFT                          4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE2_CAL_EN_O_4_K2_E5                                (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE2_CAL_EN_O_4_K2_E5_SHIFT                          5
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE3_CAL_EN_O_5_K2_E5                                (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE3_CAL_EN_O_5_K2_E5_SHIFT                          6
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_FORCE_CAL_O_6_K2_E5                                   (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_FORCE_CAL_O_6_K2_E5_SHIFT                             7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X127_K2_E5                                                           0x0011fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X127_RXEQ_CONT_CAL_O_6_0_K2_E5                                     (0x7f<<0) // 0 : enables att calibration 1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6: enables tap5 dfe calibration This register Is not bit reversed
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X127_RXEQ_CONT_CAL_O_6_0_K2_E5_SHIFT                               0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X128_K2_E5                                                           0x001200UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X128_RXEQ_INIT_CAL_O_6_0_K2_E5                                     (0x7f<<0) // 0 : enables att calibration 1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6: enables tap5 dfe calibration This register Is not bit reversed
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X128_RXEQ_INIT_CAL_O_6_0_K2_E5_SHIFT                               0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X130_K2_E5                                                           0x001208UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X130_RXEQ_RATE1_ATT_START_O_3_0_K2_E5                              (0xf<<0) // ATT start value for rate1
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X130_RXEQ_RATE1_ATT_START_O_3_0_K2_E5_SHIFT                        0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X130_RXEQ_RATE1_BOOST_START_O_3_0_K2_E5                            (0xf<<4) // Boost start value for rate1
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X130_RXEQ_RATE1_BOOST_START_O_3_0_K2_E5_SHIFT                      4
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X131_K2_E5                                                           0x00120cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X131_RXEQ_RATE2_ATT_START_O_3_0_K2_E5                              (0xf<<0) // ATT start value for rate2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X131_RXEQ_RATE2_ATT_START_O_3_0_K2_E5_SHIFT                        0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X131_RXEQ_RATE2_BOOST_START_O_3_0_K2_E5                            (0xf<<4) // Boost start value for rate2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X131_RXEQ_RATE2_BOOST_START_O_3_0_K2_E5_SHIFT                      4
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X132_K2_E5                                                           0x001210UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X132_RXEQ_RATE2_TAP1_START_O_6_0_K2_E5                             (0x7f<<0) // DFE Tap1 start value for rate2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X132_RXEQ_RATE2_TAP1_START_O_6_0_K2_E5_SHIFT                       0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X133_K2_E5                                                           0x001214UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X133_RXEQ_RATE2_TAP2_START_O_5_0_K2_E5                             (0x3f<<0) // DFE Tap2 start value for rate2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X133_RXEQ_RATE2_TAP2_START_O_5_0_K2_E5_SHIFT                       0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X134_K2_E5                                                           0x001218UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X134_RXEQ_RATE2_TAP3_START_O_5_0_K2_E5                             (0x3f<<0) // DFE Tap3 start value for rate2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X134_RXEQ_RATE2_TAP3_START_O_5_0_K2_E5_SHIFT                       0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X135_K2_E5                                                           0x00121cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X135_RXEQ_RATE2_TAP4_START_O_5_0_K2_E5                             (0x3f<<0) // DFE Tap4 start value for rate2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X135_RXEQ_RATE2_TAP4_START_O_5_0_K2_E5_SHIFT                       0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X136_K2_E5                                                           0x001220UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X136_RXEQ_RATE2_TAP5_START_O_5_0_K2_E5                             (0x3f<<0) // DFE Tap5 start value for rate2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X136_RXEQ_RATE2_TAP5_START_O_5_0_K2_E5_SHIFT                       0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X137_K2_E5                                                           0x001224UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X137_RXEQ_RATE3_ATT_START_O_3_0_K2_E5                              (0xf<<0) // ATT start value for rate3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X137_RXEQ_RATE3_ATT_START_O_3_0_K2_E5_SHIFT                        0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X137_RXEQ_RATE3_BOOST_START_O_3_0_K2_E5                            (0xf<<4) // Boost start value for rate3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X137_RXEQ_RATE3_BOOST_START_O_3_0_K2_E5_SHIFT                      4
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X138_K2_E5                                                           0x001228UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X138_RXEQ_RATE3_TAP1_START_O_6_0_K2_E5                             (0x7f<<0) // DFE Tap1 start value for rate3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X138_RXEQ_RATE3_TAP1_START_O_6_0_K2_E5_SHIFT                       0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X139_K2_E5                                                           0x00122cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X139_RXEQ_RATE3_TAP2_START_O_5_0_K2_E5                             (0x3f<<0) // DFE Tap2 start value for rate3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X139_RXEQ_RATE3_TAP2_START_O_5_0_K2_E5_SHIFT                       0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X140_K2_E5                                                           0x001230UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X140_RXEQ_RATE3_TAP3_START_O_5_0_K2_E5                             (0x3f<<0) // DFE Tap3 start value for rate3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X140_RXEQ_RATE3_TAP3_START_O_5_0_K2_E5_SHIFT                       0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X141_K2_E5                                                           0x001234UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X141_RXEQ_RATE3_TAP4_START_O_5_0_K2_E5                             (0x3f<<0) // DFE Tap4 start value for rate3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X141_RXEQ_RATE3_TAP4_START_O_5_0_K2_E5_SHIFT                       0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X142_K2_E5                                                           0x001238UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X142_RXEQ_RATE3_TAP5_START_O_5_0_K2_E5                             (0x3f<<0) // DFE Tap5 start value for rate3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X142_RXEQ_RATE3_TAP5_START_O_5_0_K2_E5_SHIFT                       0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X143_K2_E5                                                           0x00123cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X143_RXEQ_SUPERBST_AUTOCAL_DIS_K2_E5                               (0x1<<0) // Disable auto cal w/ rx_superbst
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X143_RXEQ_SUPERBST_AUTOCAL_DIS_K2_E5_SHIFT                         0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X143_BOOST_MAX_LIMIT_O_K2_E5                                       (0xf<<1) // Max limit value for BOOST auto-calibration
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X143_BOOST_MAX_LIMIT_O_K2_E5_SHIFT                                 1
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X143_BOOST_MAX_LIMIT_EN_O_K2_E5                                    (0x1<<5) // Enable Max limiting for BOOST auto-calibration
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X143_BOOST_MAX_LIMIT_EN_O_K2_E5_SHIFT                              5
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X143_RX_ATT_BOOST_CAL_O_1_0_K2_E5                                  (0x3<<6) // rx_att_boost setting used during ATT calibration
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X143_RX_ATT_BOOST_CAL_O_1_0_K2_E5_SHIFT                            6
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X144_K2_E5                                                           0x001240UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X144_RX_ATT_BOOST_NORM_O_1_0_K2_E5                                 (0x3<<0) // rx_att_boost setting used after ATT calibration
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X144_RX_ATT_BOOST_NORM_O_1_0_K2_E5_SHIFT                           0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_EN_O_K2_E5                                     (0x1<<2) // boost_adj_en
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_EN_O_K2_E5_SHIFT                               2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_DIR_O_K2_E5                                    (0x1<<3) // boost_adj_dir
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_DIR_O_K2_E5_SHIFT                              3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_VAL_O_K2_E5                                    (0xf<<4) // boost_adj_val This register Is not bit reversed
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_VAL_O_K2_E5_SHIFT                              4
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X145_K2_E5                                                           0x001244UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X145_CMP_OFFSET_AVG_MAX_NUMSAMPLES_6_0_K2_E5                       (0x7f<<0) // Max number of samples to be used for CMP Offset Noise Averaging
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X145_CMP_OFFSET_AVG_MAX_NUMSAMPLES_6_0_K2_E5_SHIFT                 0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X145_CMP_OFFSET_AVG_EN_O_K2_E5                                     (0x1<<7) // CMP Offset Noise Averaging Enable
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X145_CMP_OFFSET_AVG_EN_O_K2_E5_SHIFT                               7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X146_K2_E5                                                           0x001248UL //Access:RW   DataWidth:0x8    // 
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X147_K2_E5                                                           0x00124cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_DFE_TAP_PD_WAIT_11_8_K2_E5                               (0xf<<0) // 
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_DFE_TAP_PD_WAIT_11_8_K2_E5_SHIFT                         0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X147_PMA_LN_DFE_OFS_CAL_ENA_K2_E5                                  (0x3<<4) // DFE offset calibration enable
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X147_PMA_LN_DFE_OFS_CAL_ENA_K2_E5_SHIFT                            4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS_K2_E5                               (0x1<<6) // Disable auto cal w/ rx_att_gain
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS_K2_E5_SHIFT                         6
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_SUPERBST_EN_INVERT_O_K2_E5                               (0x1<<7) // Inverts the polarity of superboost_en before assigning to PMA
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_SUPERBST_EN_INVERT_O_K2_E5_SHIFT                         7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X148_K2_E5                                                           0x001250UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X148_RXEQ_OVR_LOAD_EN_O_6_0_K2_E5                                  (0x7f<<0) // Override for RXEQ_CTRL output register load enable.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X148_RXEQ_OVR_LOAD_EN_O_6_0_K2_E5_SHIFT                            0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X148_RXEQ_OVR_EN_O_K2_E5                                           (0x1<<7) // Override enable for DFE signals.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X148_RXEQ_OVR_EN_O_K2_E5_SHIFT                                     7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X149_K2_E5                                                           0x001254UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X149_RXEQ_OVR_LOAD_O_6_0_K2_E5                                     (0x7f<<0) // Override for RXEQ_CTRL output register load value.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X149_RXEQ_OVR_LOAD_O_6_0_K2_E5_SHIFT                               0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X149_RXEQ_OVR_LATCH_O_K2_E5                                        (0x1<<7) // Override for DFE latch signal. Negative edge causes AFE to store values of DFE output registers.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X149_RXEQ_OVR_LATCH_O_K2_E5_SHIFT                                  7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_K2_E5                                                           0x001258UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_DFE_CMP_SEL_OVR_O_2_0_K2_E5                              (0x7<<0) // Override value for comparator calibration select. Enabled by rxeq_ovr_en_o: 1: Calibrate DFE comparator 1 2: Calibrate DFE comparator 2 3: Calibrate DFE comparator 3 4: Calibrate DFE comparator 4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_DFE_CMP_SEL_OVR_O_2_0_K2_E5_SHIFT                        0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_ATT_GAIN_OVR_K2_E5                                       (0x3<<3) // Override the value of rx_att_gain output to PMA when rx_att_gain_autocal_dis=1
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_ATT_GAIN_OVR_K2_E5_SHIFT                                 3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_SUPERBST_ENA_OVR_K2_E5                                   (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_autocal_dis=1
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_SUPERBST_ENA_OVR_K2_E5_SHIFT                             5
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6_K2_E5                          (0x1<<6) // DFE TAP CMP no offset override enable
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6_K2_E5_SHIFT                    6
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_DFE_TAP_OVR_EN_O_7_K2_E5                                      (0x1<<7) // DFE TAP override enable
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_DFE_TAP_OVR_EN_O_7_K2_E5_SHIFT                                7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X151_K2_E5                                                           0x00125cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_TAP_EN_OVR_O_7_3_K2_E5                         (0x1f<<0) // DFE offset calibration TAP enable override
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_TAP_EN_OVR_O_7_3_K2_E5_SHIFT                   0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0_K2_E5                           (0x1<<5) // DFE offset calibrated value override enable
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0_K2_E5_SHIFT                     5
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_EN_OVR_O_1_K2_E5                               (0x1<<6) // DFE offset cal enable override
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_EN_OVR_O_1_K2_E5_SHIFT                         6
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X151_DFE_CMP_CAL_EN_OVR_O_2_K2_E5                                  (0x1<<7) // DFE comparator cal enable override
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X151_DFE_CMP_CAL_EN_OVR_O_2_K2_E5_SHIFT                            7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X152_K2_E5                                                           0x001260UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X152_DFE_TAP1_OVR_VAL_O_6_0_K2_E5                                  (0x7f<<0) // DFE Tap 1 Override Value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X152_DFE_TAP1_OVR_VAL_O_6_0_K2_E5_SHIFT                            0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X153_K2_E5                                                           0x001264UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X153_DFE_TAP2_OVR_VAL_O_5_0_K2_E5                                  (0x3f<<0) // DFE Tap 2 Override Value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X153_DFE_TAP2_OVR_VAL_O_5_0_K2_E5_SHIFT                            0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X154_K2_E5                                                           0x001268UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X154_DFE_TAP3_OVR_VAL_O_5_0_K2_E5                                  (0x3f<<0) // DFE Tap 3 Override Value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X154_DFE_TAP3_OVR_VAL_O_5_0_K2_E5_SHIFT                            0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X155_K2_E5                                                           0x00126cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X155_DFE_TAP4_OVR_VAL_O_5_0_K2_E5                                  (0x3f<<0) // DFE Tap 4 Override Value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X155_DFE_TAP4_OVR_VAL_O_5_0_K2_E5_SHIFT                            0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X156_K2_E5                                                           0x001270UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X156_DFE_TAP5_OVR_VAL_O_5_0_K2_E5                                  (0x3f<<0) // DFE Tap 5 Override Value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X156_DFE_TAP5_OVR_VAL_O_5_0_K2_E5_SHIFT                            0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X158_K2_E5                                                           0x001278UL //Access:R    DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X159_K2_E5                                                           0x00127cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X161_K2_E5                                                           0x001284UL //Access:R    DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X167_K2_E5                                                           0x00129cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X167_TXEQ_RXRECAL_INIT_O_7_K2_E5                                   (0x1<<0) // This bit has similar function as txeq_rxrecal_init  in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X167_TXEQ_RXRECAL_INIT_O_7_K2_E5_SHIFT                             0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X201_K2_E5                                                           0x001324UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X201_CDFE_EN_O_0_K2_E5                                             (0x1<<0) // cdfe enable bit.  1: enable cdfe when rate is 2'b01 or 2'b10.  0: disable cdfe.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X201_CDFE_EN_O_0_K2_E5_SHIFT                                       0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X201_CDFE_WORD_OV_O_1_0_K2_E5                                      (0x3<<1) // The cdfe input word_i overwrite.                                                                                                         2'b00: the word_i input for cdfe block is internally generated.                                     2'b10: the word_i input for cdfe block is set to 0 8-bit or 10-bit mode.                                                       2'b11: the word_i input for cdfe block is set to 1 16-bit or 20-bit mode.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X201_CDFE_WORD_OV_O_1_0_K2_E5_SHIFT                                1
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X201_CDFE_MODE_8B_OV_O_1_0_K2_E5                                   (0x3<<3) // The cdfe input mode_8b_i overwrite.                                                                                                         2'b00: the mode_8b_i input for cdfe block is internally generated.                                      2'b01: the mode_8b_i input for cdfe block is set to 0 10-bit or 20-bit mode.                                                      2'b11: the mode_8b_i input for cdfe block is set to 1 8-bit or 16-bit mode.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X201_CDFE_MODE_8B_OV_O_1_0_K2_E5_SHIFT                             3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X201_CDFE_RATE_OV_O_2_0_K2_E5                                      (0x7<<5) // The cdfe input rate_i[1:0] overwrite.                                                                                                         3'b0xx: the rate_i input for cdfe block is internally generated.                                     3'b1xx: the rate_i[1:0] input for cdfe block is set to cdfe_rate_ov_o[1:0]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X201_CDFE_RATE_OV_O_2_0_K2_E5_SHIFT                                5
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X202_K2_E5                                                           0x001328UL //Access:RW   DataWidth:0x8    // 
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X203_K2_E5                                                           0x00132cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X203_CDFE_GO_K2_E5                                                 (0x1<<4) // 
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X203_CDFE_GO_K2_E5_SHIFT                                           4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_FORCE_CAL_K2_E5                                       (0x1<<5) // The cdfe force calibration enable.  1: enable force cdfe calibration.  0: disable force cdfe calibration.  Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_FORCE_CAL_K2_E5_SHIFT                                 5
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_RATE_CHANGE_CAL_K2_E5                                 (0x1<<6) // The cdfe force calibration enable.  1: enable force cdfe calibration.  0: disable force cdfe calibration.  Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_RATE_CHANGE_CAL_K2_E5_SHIFT                           6
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_EI_EXIT_CAL_K2_E5                                     (0x1<<7) // EI exit cdfe calibration enable.                                                                                                   1: the cdfe calibration is enabled when EI exits and when rate is  2'b01 or 2'b10.                                  0: the cdfe calibration is disabled when EI exits.                                                                    Note: EI exit cdfe calibration is only enabled when EI exit edfe calibration is also enabled.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_EI_EXIT_CAL_K2_E5_SHIFT                               7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_K2_E5                                                           0x001330UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_CONT_CAL_K2_E5                                        (0x1<<0) // Continuous cdfe calibration enable.                                                                                            1: the continuous cdfe calibration is enabled when the rate is  2'b01 or 2'b10.                                  0: the continuous cdfe calibration is disabled.                                                                        Note: Continuout cdfe calibration is only enabled when continuous edfe calibration is also enabled.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_CONT_CAL_K2_E5_SHIFT                                  0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL_K2_E5                            (0x1<<1) // Enables cdfe calibration during Txeq adaptation phase.                                                                                            1: the cdfe calibration is enabled when the rate is  2'b10.                                  0: the cdfe calibration is disabled.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL_K2_E5_SHIFT                      1
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL_K2_E5                             (0x1<<2) // Enables cdfe calibration post Txeq adaptation.                                                                                            1: the cdfe calibration is enabled when the rate is  2'b10.                                  0: the cdfe calibration is disabled.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL_K2_E5_SHIFT                       2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_CAL_EN_K2_E5                                    (0x1<<3) // Enables the cdfe calibration in rate3.  1: enables cdfe calibration.  0: disables cdfe calibration.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_CAL_EN_K2_E5_SHIFT                              3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE2_CAL_EN_K2_E5                                    (0x1<<4) // Enables the cdfe calibration in rate2.  1: enables cdfe calibration.  0: disables cdfe calibration.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE2_CAL_EN_K2_E5_SHIFT                              4
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X205_K2_E5                                                           0x001334UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during init cal in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X206_K2_E5                                                           0x001338UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during continuos cal in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X207_K2_E5                                                           0x00133cUL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during re-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X208_K2_E5                                                           0x001340UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X208_AHB_CDFE_COARSE_DLL_OV_EN_K2_E5                               (0x1<<7) // cdfe coarse dll overwrite enable.  1: enable coarse dll overwrite for cdfe.  0: disable coarse dll overwrite for cdfe.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X208_AHB_CDFE_COARSE_DLL_OV_EN_K2_E5_SHIFT                         7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG47_K2_E5                                                  0x001344UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG48_K2_E5                                                  0x001348UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG49_K2_E5                                                  0x00134cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG50_K2_E5                                                  0x001350UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X213_K2_E5                                                           0x001354UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during txeq adaptation phase in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X214_K2_E5                                                           0x001358UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during post  txeq adaptation  in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X215_K2_E5                                                           0x00135cUL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during init cal in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X216_K2_E5                                                           0x001360UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during continuos cal in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X217_K2_E5                                                           0x001364UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during re-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG51_K2_E5                                                  0x001368UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG52_K2_E5                                                  0x00136cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X220_K2_E5                                                           0x001370UL //Access:RW   DataWidth:0x8    // Start value for dlev_ref.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X221_K2_E5                                                           0x001374UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X221_CDFE_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_K2_E5                  (0x1f<<0) // Enables copying of adapted tap values to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enables/disables copying to tap3 bit[3] : enables/disables copying to tap4 bit[4] : enables/disables copying to tap5
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X221_CDFE_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_K2_E5_SHIFT            0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X222_K2_E5                                                           0x001378UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X222_CDFE_NON_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_K2_E5              (0x1f<<0) // Enables copying of adapted tap values to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enables/disables copying to tap3 bit[3] : enables/disables copying to tap4 bit[4] : enables/disables copying to tap5
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X222_CDFE_NON_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_K2_E5_SHIFT        0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X223_K2_E5                                                           0x00137cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X223_AHB_CDFE_CMP1_TAP1_OFFSET_K2_E5                               (0x7f<<0) // Override for CMP1 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[1]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X223_AHB_CDFE_CMP1_TAP1_OFFSET_K2_E5_SHIFT                         0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X224_K2_E5                                                           0x001380UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X224_AHB_CDFE_CMP1_TAP2_OFFSET_5_0_K2_E5                           (0x3f<<0) // Override for CMP1 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[2]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X224_AHB_CDFE_CMP1_TAP2_OFFSET_5_0_K2_E5_SHIFT                     0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X225_K2_E5                                                           0x001384UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X225_AHB_CDFE_CMP1_TAP3_OFFSET_5_0_K2_E5                           (0x3f<<0) // Override for CMP1 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[3]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X225_AHB_CDFE_CMP1_TAP3_OFFSET_5_0_K2_E5_SHIFT                     0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X226_K2_E5                                                           0x001388UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X226_AHB_CDFE_CMP1_TAP4_OFFSET_5_0_K2_E5                           (0x3f<<0) // Override for CMP1 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[4]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X226_AHB_CDFE_CMP1_TAP4_OFFSET_5_0_K2_E5_SHIFT                     0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X227_K2_E5                                                           0x00138cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X227_AHB_CDFE_CMP1_TAP5_OFFSET_K2_E5                               (0x3f<<0) // Override for CMP1 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[5]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X227_AHB_CDFE_CMP1_TAP5_OFFSET_K2_E5_SHIFT                         0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X228_K2_E5                                                           0x001390UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X228_AHB_CDFE_CMP2_TAP1_OFFSET_K2_E5                               (0x7f<<0) // Override for CMP2 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[1]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X228_AHB_CDFE_CMP2_TAP1_OFFSET_K2_E5_SHIFT                         0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X229_K2_E5                                                           0x001394UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X229_AHB_CDFE_CMP2_TAP2_OFFSET_5_0_K2_E5                           (0x3f<<0) // Override for CMP2 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[2]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X229_AHB_CDFE_CMP2_TAP2_OFFSET_5_0_K2_E5_SHIFT                     0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X230_K2_E5                                                           0x001398UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X230_AHB_CDFE_CMP2_TAP3_OFFSET_5_0_K2_E5                           (0x3f<<0) // Override for CMP2 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[3]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X230_AHB_CDFE_CMP2_TAP3_OFFSET_5_0_K2_E5_SHIFT                     0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X231_K2_E5                                                           0x00139cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X231_AHB_CDFE_CMP2_TAP4_OFFSET_5_0_K2_E5                           (0x3f<<0) // Override for CMP2 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[4]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X231_AHB_CDFE_CMP2_TAP4_OFFSET_5_0_K2_E5_SHIFT                     0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X232_K2_E5                                                           0x0013a0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X232_AHB_CDFE_CMP2_TAP5_OFFSET_K2_E5                               (0x3f<<0) // Override for CMP2 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[5]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X232_AHB_CDFE_CMP2_TAP5_OFFSET_K2_E5_SHIFT                         0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X233_K2_E5                                                           0x0013a4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X233_AHB_CDFE_CMP3_TAP1_OFFSET_K2_E5                               (0x7f<<0) // Override for CMP3 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[1]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X233_AHB_CDFE_CMP3_TAP1_OFFSET_K2_E5_SHIFT                         0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X234_K2_E5                                                           0x0013a8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X234_AHB_CDFE_CMP3_TAP2_OFFSET_5_0_K2_E5                           (0x3f<<0) // Override for CMP3 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[2]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X234_AHB_CDFE_CMP3_TAP2_OFFSET_5_0_K2_E5_SHIFT                     0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X235_K2_E5                                                           0x0013acUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X235_AHB_CDFE_CMP3_TAP3_OFFSET_5_0_K2_E5                           (0x3f<<0) // Override for CMP3 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[3]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X235_AHB_CDFE_CMP3_TAP3_OFFSET_5_0_K2_E5_SHIFT                     0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X236_K2_E5                                                           0x0013b0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X236_AHB_CDFE_CMP3_TAP4_OFFSET_5_0_K2_E5                           (0x3f<<0) // Override for CMP3 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[4]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X236_AHB_CDFE_CMP3_TAP4_OFFSET_5_0_K2_E5_SHIFT                     0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X237_K2_E5                                                           0x0013b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X237_AHB_CDFE_CMP3_TAP5_OFFSET_K2_E5                               (0x3f<<0) // Override for CMP3 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[5]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X237_AHB_CDFE_CMP3_TAP5_OFFSET_K2_E5_SHIFT                         0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X238_K2_E5                                                           0x0013b8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X238_AHB_CDFE_CMP4_TAP1_OFFSET_K2_E5                               (0x7f<<0) // Override for CMP4 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[1]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X238_AHB_CDFE_CMP4_TAP1_OFFSET_K2_E5_SHIFT                         0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X239_K2_E5                                                           0x0013bcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X239_AHB_CDFE_CMP4_TAP2_OFFSET_5_0_K2_E5                           (0x3f<<0) // Override for CMP4 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[2]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X239_AHB_CDFE_CMP4_TAP2_OFFSET_5_0_K2_E5_SHIFT                     0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X240_K2_E5                                                           0x0013c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X240_AHB_CDFE_CMP4_TAP3_OFFSET_5_0_K2_E5                           (0x3f<<0) // Override for CMP4 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[3]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X240_AHB_CDFE_CMP4_TAP3_OFFSET_5_0_K2_E5_SHIFT                     0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X241_K2_E5                                                           0x0013c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X241_AHB_CDFE_CMP4_TAP4_OFFSET_5_0_K2_E5                           (0x3f<<0) // Override for CMP4 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[4]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X241_AHB_CDFE_CMP4_TAP4_OFFSET_5_0_K2_E5_SHIFT                     0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X242_K2_E5                                                           0x0013c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X242_AHB_CDFE_CMP4_TAP5_OFFSET_K2_E5                               (0x3f<<0) // Override for CMP4 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[5]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X242_AHB_CDFE_CMP4_TAP5_OFFSET_K2_E5_SHIFT                         0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X243_K2_E5                                                           0x0013ccUL //Access:RW   DataWidth:0x8    // Override for CMP1 main calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[0]
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X244_K2_E5                                                           0x0013d0UL //Access:RW   DataWidth:0x8    // Override for CMP2 main calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[0]
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X245_K2_E5                                                           0x0013d4UL //Access:RW   DataWidth:0x8    // Override for CMP3 main calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[0]
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X246_K2_E5                                                           0x0013d8UL //Access:RW   DataWidth:0x8    // Override for CMP4 main calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[0]
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X247_K2_E5                                                           0x0013dcUL //Access:RW   DataWidth:0x8    // 
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X248_K2_E5                                                           0x0013e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X248_AHB_CDFE_DLL_FINE_MASK_9_8_K2_E5                              (0x3<<0) // 
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X248_AHB_CDFE_DLL_FINE_MASK_9_8_K2_E5_SHIFT                        0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X248_AHB_CDFE_FINE_DLL_EDGE_SHIFT_K2_E5                            (0xf<<2) // 
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X248_AHB_CDFE_FINE_DLL_EDGE_SHIFT_K2_E5_SHIFT                      2
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X249_K2_E5                                                           0x0013e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X249_AHB_CDFE_ERR_SMPL_SHIFT_K2_E5                                 (0xf<<0) // 
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X249_AHB_CDFE_ERR_SMPL_SHIFT_K2_E5_SHIFT                           0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X249_AHB_CDFE_FINE_DLL_OV_EN_K2_E5                                 (0x1<<4) // cdfe fine dll overwrite enable.  1: enable fine dll overwrite for cdfe.  0: disable fine dll overwrite for cdfe.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X249_AHB_CDFE_FINE_DLL_OV_EN_K2_E5_SHIFT                           4
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_K2_E5                                                           0x0013e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8_K2_E5                       (0x1<<0) // 
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8_K2_E5_SHIFT                 0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_K2_E5                      (0x1<<1) // 
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_K2_E5_SHIFT                1
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8_K2_E5                       (0x1<<2) // 
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8_K2_E5_SHIFT                 2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_K2_E5                      (0x1<<3) // 
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_K2_E5_SHIFT                3
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X251_K2_E5                                                           0x0013ecUL //Access:RW   DataWidth:0x8    // 
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X252_K2_E5                                                           0x0013f0UL //Access:RW   DataWidth:0x8    // 
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X253_K2_E5                                                           0x0013f4UL //Access:RW   DataWidth:0x8    // 
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X254_K2_E5                                                           0x0013f8UL //Access:RW   DataWidth:0x8    // 
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_K2_E5                                                           0x0013fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_CDFE_DIR_OV_EN_K2_E5                                          (0x1<<0) // Override enable for CDFE calibration direction
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_CDFE_DIR_OV_EN_K2_E5_SHIFT                                    0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_CDFE_DIR_OV_VAL_K2_E5                                         (0x1<<1) // Override value for CDFE calibration direction
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_CDFE_DIR_OV_VAL_K2_E5_SHIFT                                   1
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_ENA270_OVR_EN_O_K2_E5                              (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed to PMA
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_ENA270_OVR_EN_O_K2_E5_SHIFT                        2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_ENA90_OVR_EN_O_K2_E5                               (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed to PMA
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_ENA90_OVR_EN_O_K2_E5_SHIFT                         3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_PHD_ENA_OVR_EN_O_K2_E5                                 (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed to PMA
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_PHD_ENA_OVR_EN_O_K2_E5_SHIFT                           4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_DLY_OVR_EN_O_K2_E5                                 (0x1<<5) // cdfe eye delay overwrite enable.  1: enable eye delay overwrite for cdfe.  0: disable eye delay overwrite for cdfe.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_DLY_OVR_EN_O_K2_E5_SHIFT                           5
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O_K2_E5                             (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed to PMA
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O_K2_E5_SHIFT                       6
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X256_K2_E5                                                           0x001400UL //Access:RW   DataWidth:0x8    // cdfe eye delay count overwrite value for CLK90.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X257_K2_E5                                                           0x001404UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8_K2_E5                          (0x1<<0) // cdfe eye delay count overwrite value for CLK90.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8_K2_E5_SHIFT                    0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_K2_E5                  (0x7f<<1) // This register represents the maximum comparator offset from the midpoint code 127/128 that must be met for the comparator to be selected as adaptation comparator during dlev and tap adaptation.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_K2_E5_SHIFT            1
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X258_K2_E5                                                           0x001408UL //Access:RW   DataWidth:0x8    // cdfe eye delay count overwrite value for CLK270.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X259_K2_E5                                                           0x00140cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8_K2_E5                         (0x1<<0) // cdfe eye delay count overwrite value for CLK270.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8_K2_E5_SHIFT                   0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X259_AHB_CDFE_DLEV_OV_EN_K2_E5                                     (0x1<<1) // cdfe dlev overwrite enable.  1: enable dlev overwrite for cdfe.  0: disable dlev overwrite for cdfe.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X259_AHB_CDFE_DLEV_OV_EN_K2_E5_SHIFT                               1
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X259_CDFE_DLEV_ADAPT_CMP_SEL_OVR_O_4_0_K2_E5                       (0x1f<<2) // Register override for overriding adaptation comparator select bit [0] : override enable bit [4:1] : override value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X259_CDFE_DLEV_ADAPT_CMP_SEL_OVR_O_4_0_K2_E5_SHIFT                 2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_K2_E5                  (0x1<<7) // Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_K2_E5_SHIFT            7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X260_K2_E5                                                           0x001410UL //Access:RW   DataWidth:0x8    // Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X261_K2_E5                                                           0x001414UL //Access:RW   DataWidth:0x8    // cdfe dlevn overwrite value.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X262_K2_E5                                                           0x001418UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X262_AHB_CDFE_TAP_OV_EN_K2_E5                                      (0x1f<<0) // cdfe tap1~5 overwrite enable.                                                                                                    Bit[0]: enable tap1 overwrite for cdfe. Bit[1]: enable tap2 overwrite for cdfe Bit[2]: enable tap3 overwrite for cdfe.  Bit[3]: enable tap4 overwrite for cdfe. Bit[4]: enable tap5 overwrite for cdfe.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X262_AHB_CDFE_TAP_OV_EN_K2_E5_SHIFT                                0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X263_K2_E5                                                           0x00141cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X263_AHB_CDFE_TAP1_OV_K2_E5                                        (0x7f<<0) // cdfe tap1 overwrite value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X263_AHB_CDFE_TAP1_OV_K2_E5_SHIFT                                  0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X264_K2_E5                                                           0x001420UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X264_AHB_CDFE_TAP2_OV_K2_E5                                        (0x3f<<0) // cdfe tap2 overwrite value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X264_AHB_CDFE_TAP2_OV_K2_E5_SHIFT                                  0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X265_K2_E5                                                           0x001424UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X265_AHB_CDFE_TAP3_OV_K2_E5                                        (0x3f<<0) // cdfe tap3 overwrite value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X265_AHB_CDFE_TAP3_OV_K2_E5_SHIFT                                  0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X266_K2_E5                                                           0x001428UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X266_AHB_CDFE_TAP4_OV_K2_E5                                        (0x3f<<0) // cdfe tap4 overwrite value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X266_AHB_CDFE_TAP4_OV_K2_E5_SHIFT                                  0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X267_K2_E5                                                           0x00142cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X267_AHB_CDFE_TAP5_OV_K2_E5                                        (0x3f<<0) // cdfe tap5 overwrite value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X267_AHB_CDFE_TAP5_OV_K2_E5_SHIFT                                  0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_K2_E5                  (0x1<<7) // Enables FW enable control for TAP adapt using DLEV
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_K2_E5_SHIFT            7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_K2_E5                                                           0x001430UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O_K2_E5                          (0x1<<0) // Instucts to start TAP adapt using DLEV in FW enabled mode
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O_K2_E5_SHIFT                    0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_K2_E5                (0x1<<1) // 
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_K2_E5_SHIFT          1
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O_K2_E5            (0x1<<2) // 
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O_K2_E5_SHIFT      2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_K2_E5                               (0x1<<7) // 
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_K2_E5_SHIFT                         7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X269_K2_E5                                                           0x001434UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O_K2_E5                        (0x1<<0) // 
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O_K2_E5_SHIFT                  0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_STROBE_EN_O_K2_E5                                    (0x1<<1) // 
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_STROBE_EN_O_K2_E5_SHIFT                              1
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_CMP_ENA_O_K2_E5                                      (0xf<<2) // 
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_CMP_ENA_O_K2_E5_SHIFT                                2
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X270_K2_E5                                                           0x001438UL //Access:RW   DataWidth:0x8    // 
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X271_K2_E5                                                           0x00143cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X271_AHB_CDFE_DIV_SIGN_BIT_O_4_0_K2_E5                             (0x1f<<0) // 
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X271_AHB_CDFE_DIV_SIGN_BIT_O_4_0_K2_E5_SHIFT                       0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O_K2_E5                     (0x1<<5) // Forces the positive dlev training pattern to be used
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O_K2_E5_SHIFT               5
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O_K2_E5                     (0x1<<6) // Forces the negative dlev training pattern to be used
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O_K2_E5_SHIFT               6
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X272_K2_E5                                                           0x001440UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X272_CDFE_TAP1_SCALE_O_2_0_K2_E5                                   (0x7<<0) // Scale factor CDFE TAP1 adapted value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X272_CDFE_TAP1_SCALE_O_2_0_K2_E5_SHIFT                             0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X272_CDFE_TAP1_SHIFT_O_4_0_K2_E5                                   (0x1f<<3) // Shift factor CDFE TAP1 adapted value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X272_CDFE_TAP1_SHIFT_O_4_0_K2_E5_SHIFT                             3
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X273_K2_E5                                                           0x001444UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X273_CDFE_TAP2_SCALE_O_2_0_K2_E5                                   (0x7<<0) // Scale factor CDFE TAP2 adapted value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X273_CDFE_TAP2_SCALE_O_2_0_K2_E5_SHIFT                             0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X273_CDFE_TAP2_SHIFT_O_4_0_K2_E5                                   (0x1f<<3) // Shift factor CDFE TAP2 adapted value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X273_CDFE_TAP2_SHIFT_O_4_0_K2_E5_SHIFT                             3
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X274_K2_E5                                                           0x001448UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X274_CDFE_TAP3_SCALE_O_2_0_K2_E5                                   (0x7<<0) // Scale factor CDFE TAP3 adapted value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X274_CDFE_TAP3_SCALE_O_2_0_K2_E5_SHIFT                             0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X274_CDFE_TAP3_SHIFT_O_4_0_K2_E5                                   (0x1f<<3) // Shift factor CDFE TAP3 adapted value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X274_CDFE_TAP3_SHIFT_O_4_0_K2_E5_SHIFT                             3
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X275_K2_E5                                                           0x00144cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X275_CDFE_TAP4_SCALE_O_2_0_K2_E5                                   (0x7<<0) // Scale factor CDFE TAP4 adapted value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X275_CDFE_TAP4_SCALE_O_2_0_K2_E5_SHIFT                             0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X275_CDFE_TAP4_SHIFT_O_4_0_K2_E5                                   (0x1f<<3) // Shift factor CDFE TAP4 adapted value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X275_CDFE_TAP4_SHIFT_O_4_0_K2_E5_SHIFT                             3
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X276_K2_E5                                                           0x001450UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X276_CDFE_TAP5_SCALE_O_2_0_K2_E5                                   (0x7<<0) // Scale factor CDFE TAP5 adapted value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X276_CDFE_TAP5_SCALE_O_2_0_K2_E5_SHIFT                             0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X276_CDFE_TAP5_SHIFT_O_4_0_K2_E5                                   (0x1f<<3) // Shift factor CDFE TAP5 adapted value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X276_CDFE_TAP5_SHIFT_O_4_0_K2_E5_SHIFT                             3
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X277_K2_E5                                                           0x001454UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_RA_OVR_O_K2_E5                                   (0x3<<0) // Bit 0:  Override enable for msm_reset_ra Bit 1: Override msm_reset_ra
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_RA_OVR_O_K2_E5_SHIFT                             0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_P2S_OVR_O_K2_E5                                  (0x3<<2) // Bit 0:  Override enable for msm_reset_p2s Bit 1: Override msm_reset_p2s
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_P2S_OVR_O_K2_E5_SHIFT                            2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_LNREGH_OVR_O_K2_E5                               (0x3<<4) // Bit 0:  Override enable for msm_reset_lnregh Bit 1: Override msm_reset_lnregh
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_LNREGH_OVR_O_K2_E5_SHIFT                         4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_LNREG_OVR_O_K2_E5                                (0x3<<6) // Bit 0:  Override enable for msm_reset_lnreg Bit 1: Override msm_reset_lnreg
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_LNREG_OVR_O_K2_E5_SHIFT                          6
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X278_K2_E5                                                           0x001458UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_RESET_CDR_OVR_O_K2_E5                                  (0x3<<0) // Bit 0:  Override enable for msm_reset_cdr Bit 1: Override msm_reset_cdr
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_RESET_CDR_OVR_O_K2_E5_SHIFT                            0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_RESET_DFE_OVR_O_K2_E5                                  (0x3<<2) // Bit 0:  Override enable for msm_reset_dfe Bit 1: Override msm_reset_dfe
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_RESET_DFE_OVR_O_K2_E5_SHIFT                            2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_PD_LNREGH_OVR_O_K2_E5                                  (0x3<<4) // Bit 0:  Override enable for msm_pd_lnregh Bit 1: Override msm_pd_lnregh
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_PD_LNREGH_OVR_O_K2_E5_SHIFT                            4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_PD_VCO_BUF_OVR_O_K2_E5                                 (0x3<<6) // Bit 0:  Override enable for msm_pd_vco_buf Bit 1: Override msm_pd_vco_buf
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_PD_VCO_BUF_OVR_O_K2_E5_SHIFT                           6
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X279_K2_E5                                                           0x00145cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_RESET_CDR_GCRX_OVR_O_K2_E5                             (0x3<<0) // Bit 0:  Override enable for msm_reset_cdr_gcrx Bit 1: Override msm_reset_cdr_gcrx
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_RESET_CDR_GCRX_OVR_O_K2_E5_SHIFT                       0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_RXGATE_EN_OVR_O_K2_E5                                  (0x3<<2) // Bit 0:  Override enable for msm_rxgate_en Bit 1: Override msm_rxgate_en
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_RXGATE_EN_OVR_O_K2_E5_SHIFT                            2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_RESET_VCO_OVR_O_K2_E5                                  (0x3<<4) // Bit 0:  Override enable for msm_reset_vco Bit 1: Override msm_reset_vco
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_RESET_VCO_OVR_O_K2_E5_SHIFT                            4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_IDDQ_SD_OVR_O_K2_E5                                    (0x3<<6) // Bit 0:  Override enable for msm_iddq_sd Bit 1: Override msm_iddq_sd
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_IDDQ_SD_OVR_O_K2_E5_SHIFT                              6
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X280_K2_E5                                                           0x001460UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_PD_DFE_OVR_O_K2_E5                                     (0x3<<0) // Bit 0:  Override enable for msm_pd_dfe Bit 1: Override msm_pd_dfe
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_PD_DFE_OVR_O_K2_E5_SHIFT                               0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_PD_DFE_BIAS_OVR_O_K2_E5                                (0x3<<2) // Bit 0:  Override enable for msm_pd_dfe_bias Bit 1: Override msm_pd_dfe_bias
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_PD_DFE_BIAS_OVR_O_K2_E5_SHIFT                          2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_TXDRV_LP_IDLE_OVR_O_K2_E5                              (0x3<<4) // Bit 0:  Override enable for msm_txdrv_lp_idle Bit 1: Override msm_txdrv_lp_idle
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_TXDRV_LP_IDLE_OVR_O_K2_E5_SHIFT                        4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_TXREG_BLEED_ENA_OVR_O_K2_E5                            (0x3<<6) // Bit 0:  Override enable for msm_txreg_bleed_ena Bit 1: Override msm_txreg_bleed_ena
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_TXREG_BLEED_ENA_OVR_O_K2_E5_SHIFT                      6
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X281_K2_E5                                                           0x001464UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_TXREG_OVR_O_K2_E5                                   (0x3<<0) // Bit 0:  Override enable for msm_pd_txreg Bit 1: Override msm_pd_txreg
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_TXREG_OVR_O_K2_E5_SHIFT                             0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_LNREG_OVR_O_K2_E5                                   (0x3<<2) // Bit 0:  Override enable for msm_pd_lnreg Bit 1: Override msm_pd_lnreg
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_LNREG_OVR_O_K2_E5_SHIFT                             2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_P2S_OVR_O_K2_E5                                     (0x3<<4) // Bit 0:  Override enable for pd_p2s Bit 1: Override pd_p2s
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_P2S_OVR_O_K2_E5_SHIFT                               4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_RA_OVR_O_K2_E5                                      (0x3<<6) // Bit 0:  Override enable for pd_ra Bit 1: Override pd_ra
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_RA_OVR_O_K2_E5_SHIFT                                6
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X282_K2_E5                                                           0x001468UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X282_LN_MSM_PD_SLV_BIAS_OVR_O_K2_E5                                (0x3<<2) // Bit 0:  Override enable for pd_slv_bias Bit 1: Override pd_slv_bias
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X282_LN_MSM_PD_SLV_BIAS_OVR_O_K2_E5_SHIFT                          2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X282_LN_MSM_PD_TXDRV_OVR_O_K2_E5                                   (0x3<<4) // Bit 0:  Override enable for pd_txdrv Bit 1: Override pd_txdrv
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X282_LN_MSM_PD_TXDRV_OVR_O_K2_E5_SHIFT                             4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X282_LN_MSM_PD_VCO_OVR_O_K2_E5                                     (0x3<<6) // Bit 0:  Override enable for msm_pd_vco Bit 1: Override msm_pd_vco
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X282_LN_MSM_PD_VCO_OVR_O_K2_E5_SHIFT                               6
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X283_K2_E5                                                           0x00146cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_CDR_EN_OVR_O_K2_E5                                     (0x3<<0) // Bit 0:  Override enable for msm_cdr_en Bit 1: Override msm_cdr_en
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_CDR_EN_OVR_O_K2_E5_SHIFT                               0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_RESET_S2P_OVR_O_K2_E5                                  (0x3<<2) // Bit 0:  Override enable for msm_reset_s2p Bit 1: Override msm_reset_s2p
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_RESET_S2P_OVR_O_K2_E5_SHIFT                            2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_RXCLK_EN_OVR_O_K2_E5                                   (0x3<<4) // Bit 0:  Override enable for msm_rxclk_en Bit 1: Override msm_rxclk_en
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_RXCLK_EN_OVR_O_K2_E5_SHIFT                             4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_WORD_OVR_O_K2_E5                                       (0x3<<6) // Bit 0:  Override enable for msm_word Bit 1: Override msm_word
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_WORD_OVR_O_K2_E5_SHIFT                                 6
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X284_K2_E5                                                           0x001470UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RATE_OVR_O_K2_E5                                       (0x7<<0) // Bit 0:  Override enable for msm_rate Bit [2:1] : Override msm_rate
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RATE_OVR_O_K2_E5_SHIFT                                 0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RXVCODIV_OVR_O_K2_E5                                   (0x7<<3) // Bit 0:  Override enable for msm_rxvcodiv Bit [2:1] : Override msm_rxvcodiv
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RXVCODIV_OVR_O_K2_E5_SHIFT                             3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RESET_TX_CLKDIV_OVR_O_K2_E5                            (0x3<<6) // Not currently used
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RESET_TX_CLKDIV_OVR_O_K2_E5_SHIFT                      6
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X285_K2_E5                                                           0x001474UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X285_LN_MSM_TXVCODIV_OVR_O_K2_E5                                   (0x7<<0) // Bit 0:  Override enable for msm_txvcodiv Bit [2:1] : Override msm_txvcodiv
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X285_LN_MSM_TXVCODIV_OVR_O_K2_E5_SHIFT                             0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_K2_E5                                                           0x0014b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_RX_SRC_O_K2_E5                                                (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 - Output of mux is output from 8b/10b encoder.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_RX_SRC_O_K2_E5_SHIFT                                          0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_TREG0_POL_O_K2_E5                                             (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_TREG0_POL_O_K2_E5_SHIFT                                       1
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_TREG0_BIT_O_K2_E5                                             (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_TREG0_BIT_O_K2_E5_SHIFT                                       2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_TREG0_WORD_O_K2_E5                                            (0x1<<3) // TReg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_TREG0_WORD_O_K2_E5_SHIFT                                      3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_DMUX_TXA_SEL_O_1_0_K2_E5                                      (0x3<<4) // Transmit mux A data input select.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_DMUX_TXA_SEL_O_1_0_K2_E5_SHIFT                                4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_P2S_RBUF_AUTOFIX_O_K2_E5                                      (0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / underflows 1 - Ring buffer will reset upon detection of overflow/underflow
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_P2S_RBUF_AUTOFIX_O_K2_E5_SHIFT                                6
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_K2_E5                                                           0x0014b8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_TREG1_POL_O_K2_E5                                             (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_TREG1_POL_O_K2_E5_SHIFT                                       0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_TREG1_BIT_O_K2_E5                                             (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_TREG1_BIT_O_K2_E5_SHIFT                                       1
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_TREG1_WORD_O_K2_E5                                            (0x1<<2) // TReg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_TREG1_WORD_O_K2_E5_SHIFT                                      2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_REG1_POL_O_K2_E5                                              (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_REG1_POL_O_K2_E5_SHIFT                                        3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_REG1_BIT_O_K2_E5                                              (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_REG1_BIT_O_K2_E5_SHIFT                                        4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_REG1_WORD_O_K2_E5                                             (0x1<<5) // Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_REG1_WORD_O_K2_E5_SHIFT                                       5
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_REG0_POL_O_K2_E5                                              (0x1<<6) // Used as Reg0 polarity select
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_REG0_POL_O_K2_E5_SHIFT                                        6
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_K2_E5                                                           0x0014bcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_REG0_BIT_O_K2_E5                                              (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_REG0_BIT_O_K2_E5_SHIFT                                        0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_REG0_WORD_O_K2_E5                                             (0x1<<1) // Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_REG0_WORD_O_K2_E5_SHIFT                                       1
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_DMUX_TXB_SEL_O_2_0_K2_E5                                      (0x7<<2) // Transmit mux B data input select enable.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_DMUX_TXB_SEL_O_2_0_K2_E5_SHIFT                                2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_TX_CTRL_O_24_K2_E5                                            (0x1<<5) // Bit 24: txdrv_c2_in[3]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_TX_CTRL_O_24_K2_E5_SHIFT                                      5
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_WIDTH_CHNG_EN_O_K2_E5                                         (0x1<<6) // Enable bit for width_chng module
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_WIDTH_CHNG_EN_O_K2_E5_SHIFT                                   6
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_TXTERM_CAL_SEQ_EN_O_K2_E5                                     (0x1<<7) // Txterm calibration enable
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_TXTERM_CAL_SEQ_EN_O_K2_E5_SHIFT                               7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X304_K2_E5                                                           0x0014c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X304_TXTERM_CAL_RSEL_K2_E5                                         (0x7<<0) // tx termination calibration comparator threshold select
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X304_TXTERM_CAL_RSEL_K2_E5_SHIFT                                   0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X304_AHB_LN_RXBIT_STRIP_O_K2_E5                                    (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2b00: no bit stripping 2b01: 2x bit stripping 2b10: reserved 2b11: 4x bit stripping
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X304_AHB_LN_RXBIT_STRIP_O_K2_E5_SHIFT                              3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X304_AHB_MAC_WIDTH_O_K2_E5                                         (0x3<<5) // Data width selector for PCS/MAC interface. 2b00: GigE or XAUI 2b01: GigE or XAUI 2b10: RXAUI 2b11: XFI
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X304_AHB_MAC_WIDTH_O_K2_E5_SHIFT                                   5
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X305_K2_E5                                                           0x0014c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X305_AHB_TXMAC_THRESHOLD_O_K2_E5                                   (0x3<<0) // An internal FIFO is included to handle the communication between the external 64-bit data and the internal 20-bit data. The reading operation will begin only when the difference between the write pointer and read pointer for this FIFO reaches ahb_txmac_threshold_o.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X305_AHB_TXMAC_THRESHOLD_O_K2_E5_SHIFT                             0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X305_AHB_LN_TXBIT_REPEAT_O_K2_E5                                   (0x3<<2) // Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to PCS 2b00: no bit stuffing nor stripping 2b01: 2x bit stuffing and stripping 2b10: reserved 2b11: 4x bit stuffing and stripping
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X305_AHB_LN_TXBIT_REPEAT_O_K2_E5_SHIFT                             2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X305_MODE_8B_O_1_0_K2_E5                                           (0x3<<4) // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data word 8 bits
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X305_MODE_8B_O_1_0_K2_E5_SHIFT                                     4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X305_ENC_EN_O_K2_E5                                                (0x1<<6) // 8b/10b encoder enable.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X305_ENC_EN_O_K2_E5_SHIFT                                          6
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X305_DEC_EN_O_K2_E5                                                (0x1<<7) // 8b/10b decoder enable.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X305_DEC_EN_O_K2_E5_SHIFT                                          7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X306_K2_E5                                                           0x0014c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X306_AHB_TX_CDAC_OVR_K2_E5                                         (0xf<<0) // TX termination calibration DAC override. Signal ahb_tx_term_en_cal_ovr must also be asserted to take effect.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X306_AHB_TX_CDAC_OVR_K2_E5_SHIFT                                   0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X307_K2_E5                                                           0x0014ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X307_PIPE_EN_O_K2_E5                                               (0x1<<5) // PIPE interface block enable.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X307_PIPE_EN_O_K2_E5_SHIFT                                         5
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X307_SAPIS_EN_O_K2_E5                                              (0x1<<6) // SAPIS interface block enable.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X307_SAPIS_EN_O_K2_E5_SHIFT                                        6
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X307_USB_MODE_K2_E5                                                (0x1<<7) // Signal Detect USB mode enable
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X307_USB_MODE_K2_E5_SHIFT                                          7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X308_K2_E5                                                           0x0014d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X310_K2_E5                                                           0x0014d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG53_K2_E5                                                  0x0014e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_K2_E5                                                           0x0014e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_GEN1_OLD_RXDATA_SRC_K2_E5                                     (0x1<<0) // Mux select for data input to polbit_reg0  0:pma_ln_dfe_err_i , 1: pma_ln_rxdata_i
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_GEN1_OLD_RXDATA_SRC_K2_E5_SHIFT                               0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_SKIP_CDR_GEN3_O_K2_E5                                         (0x1<<1) // To skip cdr calibration routines for PCIe gen3.  Can be used when PHY is operating in gen1,2 only.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_SKIP_CDR_GEN3_O_K2_E5_SHIFT                                   1
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_SKIP_CDR_GEN12_O_K2_E5                                        (0x1<<2) // To skip cdr calibration routines for PCIe gen1,2.  May not be needed in real scenario.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_SKIP_CDR_GEN12_O_K2_E5_SHIFT                                  2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_K2_E5                              (0x1<<3) // Receive amplifier powerdown override, when cisel is high
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_K2_E5_SHIFT                        3
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X315_K2_E5                                                           0x0014ecUL //Access:RW   DataWidth:0x8    // Delays the beacon_ena propagation to PMA
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X316_K2_E5                                                           0x0014f0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X316_AHB_BEACON_DELAYED_COUNT_NUMBER_O_11_8_K2_E5                  (0xf<<0) // Delays the beacon_ena propagation to PMA
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X316_AHB_BEACON_DELAYED_COUNT_NUMBER_O_11_8_K2_E5_SHIFT            0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_K2_E5                                                           0x0014f4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_AHB_BEACON_ENA_OVR_ENA_O_K2_E5                                (0x1<<0) // Beacon Override Enable
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_AHB_BEACON_ENA_OVR_ENA_O_K2_E5_SHIFT                          0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_AHB_BEACON_ENA_OVR_O_K2_E5                                    (0x1<<1) // Beacon Override
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_AHB_BEACON_ENA_OVR_O_K2_E5_SHIFT                              1
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_DEC_EN_OVR_O_K2_E5                                            (0x1<<2) // Enables 16b/20b decoder
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_DEC_EN_OVR_O_K2_E5_SHIFT                                      2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_ENC_EN_OVR_O_K2_E5                                            (0x1<<3) // Enables 16b/20b encoder
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_ENC_EN_OVR_O_K2_E5_SHIFT                                      3
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_REGP_OVR_3_0_K2_E5                                            (0xf<<4) // Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty  Bit[1]: Overide values for bit reverse  Bit[2]: Overide values for word reverse
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_REGP_OVR_3_0_K2_E5_SHIFT                                      4
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X318_K2_E5                                                           0x0014f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X318_SIGDET_OVR_O_1_0_K2_E5                                        (0x3<<0) // Bit[0]: Overide value. Bit[1] :Override enable for signal detect output
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X318_SIGDET_OVR_O_1_0_K2_E5_SHIFT                                  0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X318_LN_OUT_OVR_1_0_K2_E5                                          (0x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the override, while bit 0 is the override value.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X318_LN_OUT_OVR_1_0_K2_E5_SHIFT                                    2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X318_RXEQ_SIGDET_1_0_K2_E5                                         (0x3<<4) // Override enable for DFE signal detect indicator input. Bit 1 is overide enable , 0 is overide value
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X318_RXEQ_SIGDET_1_0_K2_E5_SHIFT                                   4
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X319_K2_E5                                                           0x0014fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X319_TXDETECTRX_OVR_O_1_0_K2_E5                                    (0x3<<0) // Override signal for txdetectrx input - bit 1 is override enable, bit 0 is override value.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X319_TXDETECTRX_OVR_O_1_0_K2_E5_SHIFT                              0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X319_RXDET_STATUS_OVR_O_1_0_K2_E5                                  (0x3<<2) // Override signal for txdetectrx output - bit 1 is override enable, bit 0 is override value.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X319_RXDET_STATUS_OVR_O_1_0_K2_E5_SHIFT                            2
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X319_LOCKED_OVR_O_1_0_K2_E5                                        (0x3<<4) // Override signal for symbol align locked output. Bit 1 is the override enable, and bit 0 is the override value.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X319_LOCKED_OVR_O_1_0_K2_E5_SHIFT                                  4
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O_K2_E5                        (0x1<<6) // override enable for tx_lowpwr_idle_ena output to PMA
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O_K2_E5_SHIFT                  6
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_K2_E5                            (0x1<<7) // override value for tx_lowpwr_idle_ena output to PMA
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_K2_E5_SHIFT                      7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X320_K2_E5                                                           0x001500UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X321_K2_E5                                                           0x001504UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X322_K2_E5                                                           0x001508UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X323_K2_E5                                                           0x00150cUL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X324_K2_E5                                                           0x001510UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X325_K2_E5                                                           0x001514UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_K2_E5                                                           0x001518UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_LN_IN_OVR_O_48_K2_E5                                          (0x1<<0) // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_LN_IN_OVR_O_48_K2_E5_SHIFT                                    0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_AHB_LN_IN_OVR_CHG_FLAG_O_K2_E5                                (0x1<<1) // Flag to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1' before writing to the corresponding lnX_in_ovr_o_14_1 and set it back to '0' after the write. It is not needed for configuration writes.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_AHB_LN_IN_OVR_CHG_FLAG_O_K2_E5_SHIFT                          1
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_OOB_DET_EN_K2_E5                                              (0x1<<6) // OOB detect enable
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_OOB_DET_EN_K2_E5_SHIFT                                        6
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_LN_IN_OVR_O_49_K2_E5                                          (0x1<<7) // OOB detect enable
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_LN_IN_OVR_O_49_K2_E5_SHIFT                                    7
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X327_K2_E5                                                           0x00151cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X327_CDR_CTRL_DLY_DLPF_EN_O_K2_E5                                  (0x1f<<0) // Delay between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0  R-platform requires 150ns delay
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X327_CDR_CTRL_DLY_DLPF_EN_O_K2_E5_SHIFT                            0
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG54_K2_E5                                                  0x001520UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG55_K2_E5                                                  0x001524UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X330_K2_E5                                                           0x001528UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X330_MSM_LN_RATE_EXTRA_BITS_OVR_O_2_0_K2_E5                        (0x7<<0) // Override signals for lane: msm_ln_rate_ow[4:2]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X330_MSM_LN_RATE_EXTRA_BITS_OVR_O_2_0_K2_E5_SHIFT                  0
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X330_LN_IN_OVR_O_50_K2_E5                                          (0x1<<3) // Override signals for lane: msm_ln_rate_ow[4:2]
+  #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X330_LN_IN_OVR_O_50_K2_E5_SHIFT                                    3
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X0_K2_E5                                                          0x002800UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X0_LN_CMUREF_EN_O_K2_E5                                         (0x1<<0) // Lane Reference Clock Enable.  0 - gcfsm_refmux_clk = pma_cm_ref_clk_i 1 - gcfsm_refmux_clk = lane_ref_clk
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X0_LN_CMUREF_EN_O_K2_E5_SHIFT                                   0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X1_K2_E5                                                          0x002804UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X1_BIST_CHK_INV_PRBS_O_K2_E5                                    (0x1<<0) // Enable/Disable the internal PRBS data pattern inverter. 0x0  Invert the PRBS data pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1  Not invert the PRBS data pattern for PRBS-31 and invert the PRBS data pattern for the other PRBS types.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X1_BIST_CHK_INV_PRBS_O_K2_E5_SHIFT                              0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X1_BIST_GEN_INV_PRBS_O_K2_E5                                    (0x1<<1) // Enable/Disable the internal PRBS data pattern inverter. 0x0  Invert the PRBS data pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1  Not invert the PRBS data pattern for PRBS-31 and invert the PRBS data pattern for the other PRBS types.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X1_BIST_GEN_INV_PRBS_O_K2_E5_SHIFT                              1
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X4_K2_E5                                                          0x002810UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X4_P2S_RBUF_PTR_DIFF_O_2_0_K2_E5                                (0x7<<0) // P2S ring buffer initial startup pointer difference.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X4_P2S_RBUF_PTR_DIFF_O_2_0_K2_E5_SHIFT                          0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG16_K2_E5                                               0x002814UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X6_K2_E5                                                          0x002818UL //Access:RW   DataWidth:0x8    // Symbol aligner alignment word. Expects bit 0 received first
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X7_K2_E5                                                          0x00281cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X7_SYM_ALIGN_WORD_O_9_8_K2_E5                                   (0x3<<0) // Symbol aligner alignment word. Expects bit 0 received first
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X7_SYM_ALIGN_WORD_O_9_8_K2_E5_SHIFT                             0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X8_K2_E5                                                          0x002820UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X8_SYM_LOCK_NUM_O_3_0_K2_E5                                     (0xf<<0) // Number of properly aligned align words that must be detected
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X8_SYM_LOCK_NUM_O_3_0_K2_E5_SHIFT                               0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X8_SYM_UNLOCK_NUM_O_3_0_K2_E5                                   (0xf<<4) // Number of improperly aligned align words that must be detected
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X8_SYM_UNLOCK_NUM_O_3_0_K2_E5_SHIFT                             4
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X31_K2_E5                                                         0x00287cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG17_K2_E5                                               0x0028a8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X43_K2_E5                                                         0x0028acUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X43_CDR_CTRL_DLPF_RAIL_RST_EN_O_K2_E5                           (0x1<<1) // Enable resetting of railed DLPF
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X43_CDR_CTRL_DLPF_RAIL_RST_EN_O_K2_E5_SHIFT                     1
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X44_K2_E5                                                         0x0028b0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_EN_O_K2_E5                      (0x1<<0) // Enable DOSC adjustement for railed DLPF
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_EN_O_K2_E5_SHIFT                0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_VAL_O_K2_E5                     (0x1f<<1) // Default DOSC adjustement value for railed DLPF
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_VAL_O_K2_E5_SHIFT               1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_DIR_O_K2_E5                     (0x1<<6) // Default DOSC adjustement direction for railed DLPF
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_DIR_O_K2_E5_SHIFT               6
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_K2_E5                                                         0x0028c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_COUNTER_EN_O_K2_E5                                 (0x1<<0) // Enable eye scan counter
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_COUNTER_EN_O_K2_E5_SHIFT                           0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_RUN_O_K2_E5                                        (0x1<<1) // Run eye scan counter
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_RUN_O_K2_E5_SHIFT                                  1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_O_K2_E5                                      (0x1<<2) // Shift edge samples
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_O_K2_E5_SHIFT                                2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_DIR_O_K2_E5                                  (0x1<<3) // Determines shift direction of edge samples
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_DIR_O_K2_E5_SHIFT                            3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_2BITS_O_K2_E5                                (0x1<<4) // Shift edge samples by 2 bits
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_2BITS_O_K2_E5_SHIFT                          4
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X50_K2_E5                                                         0x0028c8UL //Access:RW   DataWidth:0x8    // Mask eye scan results
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X51_K2_E5                                                         0x0028ccUL //Access:RW   DataWidth:0x8    // Mask eye scan results
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X52_K2_E5                                                         0x0028d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X52_EYE_SCAN_MASK_O_18_16_K2_E5                                 (0x7<<0) // Mask eye scan results
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X52_EYE_SCAN_MASK_O_18_16_K2_E5_SHIFT                           0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X53_K2_E5                                                         0x0028d4UL //Access:RW   DataWidth:0x8    // Eye scan wait time
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X54_K2_E5                                                         0x0028d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X54_EYE_SCAN_WAIT_LEN_O_11_8_K2_E5                              (0xf<<0) // Eye scan wait time
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X54_EYE_SCAN_WAIT_LEN_O_11_8_K2_E5_SHIFT                        0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X55_K2_E5                                                         0x0028dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X55_GCFSM_DIV_EN_O_1_0_K2_E5                                    (0x3<<0) // Static divider control for Lane GCFSM clock The only access to this divider. Not an override 4d0:  No division  4d1:  /2 4d2:  /2 4d3:  /4:
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X55_GCFSM_DIV_EN_O_1_0_K2_E5_SHIFT                              0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X56_K2_E5                                                         0x0028e0UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 7-0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X57_K2_E5                                                         0x0028e4UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 15-8
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X58_K2_E5                                                         0x0028e8UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 23-16
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X59_K2_E5                                                         0x0028ecUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 31-24
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X60_K2_E5                                                         0x0028f0UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 39-32
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X61_K2_E5                                                         0x0028f4UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 47-40
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X62_K2_E5                                                         0x0028f8UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 55-48
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X63_K2_E5                                                         0x0028fcUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 63-56
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X64_K2_E5                                                         0x002900UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 71-64
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X65_K2_E5                                                         0x002904UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 79-72
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X66_K2_E5                                                         0x002908UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 87-80
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X67_K2_E5                                                         0x00290cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 95-88
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X68_K2_E5                                                         0x002910UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 103-96
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X69_K2_E5                                                         0x002914UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 111-104
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X70_K2_E5                                                         0x002918UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 119-112
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X71_K2_E5                                                         0x00291cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 127-120
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X72_K2_E5                                                         0x002920UL //Access:RW   DataWidth:0x8    // GCFSM calibraton direction
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X73_K2_E5                                                         0x002924UL //Access:RW   DataWidth:0x8    // GCFSM calibraton direction
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X74_K2_E5                                                         0x002928UL //Access:RW   DataWidth:0x8    // Function info for each MSM function. Varies depending on function number.   Bits 15-7: Address of first command to run Bits: 6-0: Number of commands to run
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X75_K2_E5                                                         0x00292cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X76_K2_E5                                                         0x002930UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X77_K2_E5                                                         0x002934UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X78_K2_E5                                                         0x002938UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X79_K2_E5                                                         0x00293cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X80_K2_E5                                                         0x002940UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X81_K2_E5                                                         0x002944UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X82_K2_E5                                                         0x002948UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X83_K2_E5                                                         0x00294cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X84_K2_E5                                                         0x002950UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X85_K2_E5                                                         0x002954UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X86_K2_E5                                                         0x002958UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X87_K2_E5                                                         0x00295cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X88_K2_E5                                                         0x002960UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X89_K2_E5                                                         0x002964UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X90_K2_E5                                                         0x002968UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X91_K2_E5                                                         0x00296cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X92_K2_E5                                                         0x002970UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X93_K2_E5                                                         0x002974UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X94_K2_E5                                                         0x002978UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X95_K2_E5                                                         0x00297cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X96_K2_E5                                                         0x002980UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X97_K2_E5                                                         0x002984UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X98_K2_E5                                                         0x002988UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X99_K2_E5                                                         0x00298cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X100_K2_E5                                                        0x002990UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X101_K2_E5                                                        0x002994UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X102_K2_E5                                                        0x002998UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X103_K2_E5                                                        0x00299cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X104_K2_E5                                                        0x0029a0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X105_K2_E5                                                        0x0029a4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X106_K2_E5                                                        0x0029a8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X107_K2_E5                                                        0x0029acUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X108_K2_E5                                                        0x0029b0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X109_K2_E5                                                        0x0029b4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X110_K2_E5                                                        0x0029b8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X111_K2_E5                                                        0x0029bcUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X112_K2_E5                                                        0x0029c0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X113_K2_E5                                                        0x0029c4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X114_K2_E5                                                        0x0029c8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X115_K2_E5                                                        0x0029ccUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X116_K2_E5                                                        0x0029d0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X117_K2_E5                                                        0x0029d4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X118_K2_E5                                                        0x0029d8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X119_K2_E5                                                        0x0029dcUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X120_K2_E5                                                        0x0029e0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X121_K2_E5                                                        0x0029e4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X122_K2_E5                                                        0x0029e8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X123_K2_E5                                                        0x0029ecUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X124_K2_E5                                                        0x0029f0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X125_K2_E5                                                        0x0029f4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X126_K2_E5                                                        0x0029f8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X127_K2_E5                                                        0x0029fcUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X128_K2_E5                                                        0x002a00UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X129_K2_E5                                                        0x002a04UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X130_K2_E5                                                        0x002a08UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X131_K2_E5                                                        0x002a0cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X132_K2_E5                                                        0x002a10UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X133_K2_E5                                                        0x002a14UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X134_K2_E5                                                        0x002a18UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X135_K2_E5                                                        0x002a1cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X136_K2_E5                                                        0x002a20UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X137_K2_E5                                                        0x002a24UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X138_K2_E5                                                        0x002a28UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X138_QAHB_MSM_PIPE_EN_PROG_TXDETECTRX_PULSE_O_K2_E5             (0x1<<0) // Enables programmable tx det rx pulse
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X138_QAHB_MSM_PIPE_EN_PROG_TXDETECTRX_PULSE_O_K2_E5_SHIFT       0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X139_K2_E5                                                        0x002a2cUL //Access:RW   DataWidth:0x8    // Programmable width of tx det rx pulse
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X140_K2_E5                                                        0x002a30UL //Access:RW   DataWidth:0x8    // Programmable width of tx det rx pulse
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X141_K2_E5                                                        0x002a34UL //Access:RW   DataWidth:0x8    // Delay for MFSM state transition from P2 to P1 in non-PIPE mode.  The MFSM waits for the analog cuircuity to recover from power-down. The actual delay is 4*<reference clock period	*<value of this register	.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X142_K2_E5                                                        0x002a38UL //Access:RW   DataWidth:0x8    // Delay for MFSM state transition from P2 to P1 in non-PIPE mode.  The MFSM waits for the analog cuircuity to recover from power-down. The actual delay is 4*<reference clock period	*<value of this register	.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_K2_E5                                                        0x002a3cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_IDDQ_SD_O_K2_E5                              (0x1<<0) // MSM Function IDDQ state's default value for iddq_sd in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_IDDQ_SD_O_K2_E5_SHIFT                        0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_DFE_O_K2_E5                               (0x1<<1) // MSM Function IDDQ state's default value for pd_dfe in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_DFE_O_K2_E5_SHIFT                         1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_DFE_BIAS_O_K2_E5                          (0x1<<2) // MSM Function IDDQ state's default value for pd_dfe_bias in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_DFE_BIAS_O_K2_E5_SHIFT                    2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_LNREG_O_K2_E5                             (0x1<<3) // MSM Function IDDQ state's default value for pd_lnreg in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_LNREG_O_K2_E5_SHIFT                       3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_LNREGH_O_K2_E5                            (0x1<<4) // MSM Function IDDQ state's default value for pd_lnregh in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_LNREGH_O_K2_E5_SHIFT                      4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_P2S_O_K2_E5                               (0x1<<5) // MSM Function IDDQ state's default value for pd_p2s in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_P2S_O_K2_E5_SHIFT                         5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_RA_O_K2_E5                                (0x1<<6) // MSM Function IDDQ state's default value for pd_ra in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_RA_O_K2_E5_SHIFT                          6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_S2P_O_K2_E5                               (0x1<<7) // MSM Function IDDQ state's default value for pd_s2p in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_S2P_O_K2_E5_SHIFT                         7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_K2_E5                                                        0x002a40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_SLV_BIAS_O_K2_E5                          (0x1<<0) // MSM Function IDDQ state's default value for pd_slv_bias in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_SLV_BIAS_O_K2_E5_SHIFT                    0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_TXDRV_O_K2_E5                             (0x1<<1) // MSM Function IDDQ state's default value for pd_txdrv in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_TXDRV_O_K2_E5_SHIFT                       1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_TXREG_O_K2_E5                             (0x1<<2) // MSM Function IDDQ state's default value for pd_txreg in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_TXREG_O_K2_E5_SHIFT                       2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_VCO_O_K2_E5                               (0x1<<3) // MSM Function IDDQ state's default value for pd_vco in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_VCO_O_K2_E5_SHIFT                         3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_VCO_BUF_O_K2_E5                           (0x1<<4) // MSM Function IDDQ state's default value for pd_vco_buf in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_VCO_BUF_O_K2_E5_SHIFT                     4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_CDR_O_K2_E5                            (0x1<<5) // MSM Function IDDQ state's default value for reset_cdr in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_CDR_O_K2_E5_SHIFT                      5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_CDR_GCRX_O_K2_E5                       (0x1<<6) // MSM Function IDDQ state's default value for reset_cdr_gcrx in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_CDR_GCRX_O_K2_E5_SHIFT                 6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_DFE_O_K2_E5                            (0x1<<7) // MSM Function IDDQ state's default value for reset_dfe in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_DFE_O_K2_E5_SHIFT                      7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_K2_E5                                                        0x002a44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_LNREG_O_K2_E5                          (0x1<<0) // MSM Function IDDQ state's default value for reset_lnreg in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_LNREG_O_K2_E5_SHIFT                    0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_LNREGH_O_K2_E5                         (0x1<<1) // MSM Function IDDQ state's default value for reset_lnregh in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_LNREGH_O_K2_E5_SHIFT                   1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_P2S_O_K2_E5                            (0x1<<2) // MSM Function IDDQ state's default value for reset_p2s in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_P2S_O_K2_E5_SHIFT                      2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_RA_O_K2_E5                             (0x1<<3) // MSM Function IDDQ state's default value for reset_ra in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_RA_O_K2_E5_SHIFT                       3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_S2P_O_K2_E5                            (0x1<<4) // MSM Function IDDQ state's default value for reset_s2p in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_S2P_O_K2_E5_SHIFT                      4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_VCO_O_K2_E5                            (0x1<<5) // MSM Function IDDQ state's default value for reset_vco in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_VCO_O_K2_E5_SHIFT                      5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_TXREG_BLEED_ENA_O_K2_E5                      (0x1<<6) // MSM Function IDDQ state's default value for txreg_bleed_ena in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_TXREG_BLEED_ENA_O_K2_E5_SHIFT                6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_TX_LOWPWR_IDLE_ENA_O_K2_E5                   (0x1<<7) // MSM Function IDDQ state's default value for tx_lowpwr_idle_ena in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT             7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_K2_E5                                                        0x002a48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_CDR_EN_O_K2_E5                               (0x1<<0) // MSM Function IDDQ state's default value for cdr_en in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_CDR_EN_O_K2_E5_SHIFT                         0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RXBCLK_EN_O_K2_E5                            (0x1<<1) // MSM Function IDDQ state's default value for rxbclk_en in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RXBCLK_EN_O_K2_E5_SHIFT                      1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RX_GATE_EN_O_K2_E5                           (0x1<<2) // MSM Function IDDQ state's default value for rx_gate_en in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RX_GATE_EN_O_K2_E5_SHIFT                     2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RESET_TX_CLKDIV_O_K2_E5                      (0x1<<3) // MSM Function IDDQ state's default value for reset_tx_clkdiv in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RESET_TX_CLKDIV_O_K2_E5_SHIFT                3
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_K2_E5                                                        0x002a4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_IDDQ_SD_O_K2_E5                               (0x1<<0) // MSM Function RESET state's default value for iddq_sd in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_IDDQ_SD_O_K2_E5_SHIFT                         0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_DFE_O_K2_E5                                (0x1<<1) // MSM Function RESET state's default value for pd_dfe in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_DFE_O_K2_E5_SHIFT                          1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_DFE_BIAS_O_K2_E5                           (0x1<<2) // MSM Function RESET state's default value for pd_dfe_bias in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_DFE_BIAS_O_K2_E5_SHIFT                     2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_LNREG_O_K2_E5                              (0x1<<3) // MSM Function RESET state's default value for pd_lnreg in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_LNREG_O_K2_E5_SHIFT                        3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_LNREGH_O_K2_E5                             (0x1<<4) // MSM Function RESET state's default value for pd_lnregh in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_LNREGH_O_K2_E5_SHIFT                       4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_P2S_O_K2_E5                                (0x1<<5) // MSM Function RESET state's default value for pd_p2s in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_P2S_O_K2_E5_SHIFT                          5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_RA_O_K2_E5                                 (0x1<<6) // MSM Function RESET state's default value for pd_ra in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_RA_O_K2_E5_SHIFT                           6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_S2P_O_K2_E5                                (0x1<<7) // MSM Function RESET state's default value for pd_s2p in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_S2P_O_K2_E5_SHIFT                          7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_K2_E5                                                        0x002a50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_SLV_BIAS_O_K2_E5                           (0x1<<0) // MSM Function RESET state's default value for pd_slv_bias in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_SLV_BIAS_O_K2_E5_SHIFT                     0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_TXDRV_O_K2_E5                              (0x1<<1) // MSM Function RESET state's default value for pd_txdrv in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_TXDRV_O_K2_E5_SHIFT                        1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_TXREG_O_K2_E5                              (0x1<<2) // MSM Function RESET state's default value for pd_txreg in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_TXREG_O_K2_E5_SHIFT                        2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_VCO_O_K2_E5                                (0x1<<3) // MSM Function RESET state's default value for pd_vco in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_VCO_O_K2_E5_SHIFT                          3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_VCO_BUF_O_K2_E5                            (0x1<<4) // MSM Function RESET state's default value for pd_vco_buf in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_VCO_BUF_O_K2_E5_SHIFT                      4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_CDR_O_K2_E5                             (0x1<<5) // MSM Function RESET state's default value for reset_cdr in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_CDR_O_K2_E5_SHIFT                       5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_CDR_GCRX_O_K2_E5                        (0x1<<6) // MSM Function RESET state's default value for reset_cdr_gcrx in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_CDR_GCRX_O_K2_E5_SHIFT                  6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_DFE_O_K2_E5                             (0x1<<7) // MSM Function RESET state's default value for reset_dfe in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_DFE_O_K2_E5_SHIFT                       7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_K2_E5                                                        0x002a54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_LNREG_O_K2_E5                           (0x1<<0) // MSM Function RESET state's default value for reset_lnreg in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_LNREG_O_K2_E5_SHIFT                     0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_LNREGH_O_K2_E5                          (0x1<<1) // MSM Function RESET state's default value for reset_lnregh in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_LNREGH_O_K2_E5_SHIFT                    1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_P2S_O_K2_E5                             (0x1<<2) // MSM Function RESET state's default value for reset_p2s in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_P2S_O_K2_E5_SHIFT                       2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_RA_O_K2_E5                              (0x1<<3) // MSM Function RESET state's default value for reset_ra in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_RA_O_K2_E5_SHIFT                        3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_S2P_O_K2_E5                             (0x1<<4) // MSM Function RESET state's default value for reset_s2p in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_S2P_O_K2_E5_SHIFT                       4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_VCO_O_K2_E5                             (0x1<<5) // MSM Function RESET state's default value for reset_vco in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_VCO_O_K2_E5_SHIFT                       5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_TXREG_BLEED_ENA_O_K2_E5                       (0x1<<6) // MSM Function RESET state's default value for txreg_bleed_ena in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_TXREG_BLEED_ENA_O_K2_E5_SHIFT                 6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_TX_LOWPWR_IDLE_ENA_O_K2_E5                    (0x1<<7) // MSM Function RESET state's default value for tx_lowpwr_idle_ena in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT              7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_K2_E5                                                        0x002a58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_CDR_EN_O_K2_E5                                (0x1<<0) // MSM Function RESET state's default value for cdr_en in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_CDR_EN_O_K2_E5_SHIFT                          0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RXBCLK_EN_O_K2_E5                             (0x1<<1) // MSM Function RESET state's default value for rxbclk_en in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RXBCLK_EN_O_K2_E5_SHIFT                       1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RX_GATE_EN_O_K2_E5                            (0x1<<2) // MSM Function RESET state's default value for rx_gate_en in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RX_GATE_EN_O_K2_E5_SHIFT                      2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RESET_TX_CLKDIV_O_K2_E5                       (0x1<<3) // MSM Function RESET state's default value for reset_tx_clkdiv in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RESET_TX_CLKDIV_O_K2_E5_SHIFT                 3
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_K2_E5                                                        0x002a5cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_IDDQ_SD_O_K2_E5                              (0x1<<0) // MSM Function NORMAL state's default value for iddq_sd in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_IDDQ_SD_O_K2_E5_SHIFT                        0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_DFE_O_K2_E5                               (0x1<<1) // MSM Function NORMAL state's default value for pd_dfe in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_DFE_O_K2_E5_SHIFT                         1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_DFE_BIAS_O_K2_E5                          (0x1<<2) // MSM Function NORMAL state's default value for pd_dfe_bias in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_DFE_BIAS_O_K2_E5_SHIFT                    2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_LNREG_O_K2_E5                             (0x1<<3) // MSM Function NORMAL state's default value for pd_lnreg in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_LNREG_O_K2_E5_SHIFT                       3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_LNREGH_O_K2_E5                            (0x1<<4) // MSM Function NORMAL state's default value for pd_lnregh in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_LNREGH_O_K2_E5_SHIFT                      4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_P2S_O_K2_E5                               (0x1<<5) // MSM Function NORMAL state's default value for pd_p2s in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_P2S_O_K2_E5_SHIFT                         5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_RA_O_K2_E5                                (0x1<<6) // MSM Function NORMAL state's default value for pd_ra in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_RA_O_K2_E5_SHIFT                          6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_S2P_O_K2_E5                               (0x1<<7) // MSM Function NORMAL state's default value for pd_s2p in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_S2P_O_K2_E5_SHIFT                         7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_K2_E5                                                        0x002a60UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_SLV_BIAS_O_K2_E5                          (0x1<<0) // MSM Function NORMAL state's default value for pd_slv_bias in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_SLV_BIAS_O_K2_E5_SHIFT                    0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_TXDRV_O_K2_E5                             (0x1<<1) // MSM Function NORMAL state's default value for pd_txdrv in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_TXDRV_O_K2_E5_SHIFT                       1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_TXREG_O_K2_E5                             (0x1<<2) // MSM Function NORMAL state's default value for pd_txreg in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_TXREG_O_K2_E5_SHIFT                       2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_VCO_O_K2_E5                               (0x1<<3) // MSM Function NORMAL state's default value for pd_vco in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_VCO_O_K2_E5_SHIFT                         3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_VCO_BUF_O_K2_E5                           (0x1<<4) // MSM Function NORMAL state's default value for pd_vco_buf in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_VCO_BUF_O_K2_E5_SHIFT                     4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_CDR_O_K2_E5                            (0x1<<5) // MSM Function NORMAL state's default value for reset_cdr in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_CDR_O_K2_E5_SHIFT                      5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_CDR_GCRX_O_K2_E5                       (0x1<<6) // MSM Function NORMAL state's default value for reset_cdr_gcrx in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_CDR_GCRX_O_K2_E5_SHIFT                 6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_DFE_O_K2_E5                            (0x1<<7) // MSM Function NORMAL state's default value for reset_dfe in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_DFE_O_K2_E5_SHIFT                      7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_K2_E5                                                        0x002a64UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_LNREG_O_K2_E5                          (0x1<<0) // MSM Function NORMAL state's default value for reset_lnreg in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_LNREG_O_K2_E5_SHIFT                    0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_LNREGH_O_K2_E5                         (0x1<<1) // MSM Function NORMAL state's default value for reset_lnregh in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_LNREGH_O_K2_E5_SHIFT                   1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_P2S_O_K2_E5                            (0x1<<2) // MSM Function NORMAL state's default value for reset_p2s in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_P2S_O_K2_E5_SHIFT                      2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_RA_O_K2_E5                             (0x1<<3) // MSM Function NORMAL state's default value for reset_ra in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_RA_O_K2_E5_SHIFT                       3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_S2P_O_K2_E5                            (0x1<<4) // MSM Function NORMAL state's default value for reset_s2p in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_S2P_O_K2_E5_SHIFT                      4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_VCO_O_K2_E5                            (0x1<<5) // MSM Function NORMAL state's default value for reset_vco in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_VCO_O_K2_E5_SHIFT                      5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_TXREG_BLEED_ENA_O_K2_E5                      (0x1<<6) // MSM Function NORMAL state's default value for txreg_bleed_ena in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_TXREG_BLEED_ENA_O_K2_E5_SHIFT                6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_TX_LOWPWR_IDLE_ENA_O_K2_E5                   (0x1<<7) // MSM Function NORMAL state's default value for tx_lowpwr_idle_ena in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT             7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_K2_E5                                                        0x002a68UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_CDR_EN_O_K2_E5                               (0x1<<0) // MSM Function NORMAL state's default value for cdr_en in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_CDR_EN_O_K2_E5_SHIFT                         0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RXBCLK_EN_O_K2_E5                            (0x1<<1) // MSM Function NORMAL state's default value for rxbclk_en in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RXBCLK_EN_O_K2_E5_SHIFT                      1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RX_GATE_EN_O_K2_E5                           (0x1<<2) // MSM Function NORMAL state's default value for rx_gate_en in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RX_GATE_EN_O_K2_E5_SHIFT                     2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RESET_TX_CLKDIV_O_K2_E5                      (0x1<<3) // MSM Function NORMAL state's default value for reset_tx_clkdiv in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RESET_TX_CLKDIV_O_K2_E5_SHIFT                3
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_K2_E5                                                        0x002a6cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_IDDQ_SD_O_K2_E5                           (0x1<<0) // MSM Function PARTIAL state's default value for iddq_sd in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_IDDQ_SD_O_K2_E5_SHIFT                     0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_DFE_O_K2_E5                            (0x1<<1) // MSM Function PARTIAL state's default value for pd_dfe in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_DFE_O_K2_E5_SHIFT                      1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_DFE_BIAS_O_K2_E5                       (0x1<<2) // MSM Function PARTIAL state's default value for pd_dfe_bias in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_DFE_BIAS_O_K2_E5_SHIFT                 2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_LNREG_O_K2_E5                          (0x1<<3) // MSM Function PARTIAL state's default value for pd_lnreg in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_LNREG_O_K2_E5_SHIFT                    3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_LNREGH_O_K2_E5                         (0x1<<4) // MSM Function PARTIAL state's default value for pd_lnregh in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_LNREGH_O_K2_E5_SHIFT                   4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_P2S_O_K2_E5                            (0x1<<5) // MSM Function PARTIAL state's default value for pd_p2s in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_P2S_O_K2_E5_SHIFT                      5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_RA_O_K2_E5                             (0x1<<6) // MSM Function PARTIAL state's default value for pd_ra in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_RA_O_K2_E5_SHIFT                       6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_S2P_O_K2_E5                            (0x1<<7) // MSM Function PARTIAL state's default value for pd_s2p in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_S2P_O_K2_E5_SHIFT                      7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_K2_E5                                                        0x002a70UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_SLV_BIAS_O_K2_E5                       (0x1<<0) // MSM Function PARTIAL state's default value for pd_slv_bias in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_SLV_BIAS_O_K2_E5_SHIFT                 0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_TXDRV_O_K2_E5                          (0x1<<1) // MSM Function PARTIAL state's default value for pd_txdrv in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_TXDRV_O_K2_E5_SHIFT                    1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_TXREG_O_K2_E5                          (0x1<<2) // MSM Function PARTIAL state's default value for pd_txreg in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_TXREG_O_K2_E5_SHIFT                    2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_VCO_O_K2_E5                            (0x1<<3) // MSM Function PARTIAL state's default value for pd_vco in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_VCO_O_K2_E5_SHIFT                      3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_VCO_BUF_O_K2_E5                        (0x1<<4) // MSM Function PARTIAL state's default value for pd_vco_buf in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_VCO_BUF_O_K2_E5_SHIFT                  4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_CDR_O_K2_E5                         (0x1<<5) // MSM Function PARTIAL state's default value for reset_cdr in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_CDR_O_K2_E5_SHIFT                   5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_CDR_GCRX_O_K2_E5                    (0x1<<6) // MSM Function PARTIAL state's default value for reset_cdr_gcrx in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_CDR_GCRX_O_K2_E5_SHIFT              6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_DFE_O_K2_E5                         (0x1<<7) // MSM Function PARTIAL state's default value for reset_dfe in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_DFE_O_K2_E5_SHIFT                   7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_K2_E5                                                        0x002a74UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_LNREG_O_K2_E5                       (0x1<<0) // MSM Function PARTIAL state's default value for reset_lnreg in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_LNREG_O_K2_E5_SHIFT                 0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_LNREGH_O_K2_E5                      (0x1<<1) // MSM Function PARTIAL state's default value for reset_lnregh in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_LNREGH_O_K2_E5_SHIFT                1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_P2S_O_K2_E5                         (0x1<<2) // MSM Function PARTIAL state's default value for reset_p2s in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_P2S_O_K2_E5_SHIFT                   2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_RA_O_K2_E5                          (0x1<<3) // MSM Function PARTIAL state's default value for reset_ra in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_RA_O_K2_E5_SHIFT                    3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_S2P_O_K2_E5                         (0x1<<4) // MSM Function PARTIAL state's default value for reset_s2p in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_S2P_O_K2_E5_SHIFT                   4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_VCO_O_K2_E5                         (0x1<<5) // MSM Function PARTIAL state's default value for reset_vco in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_VCO_O_K2_E5_SHIFT                   5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_TXREG_BLEED_ENA_O_K2_E5                   (0x1<<6) // MSM Function PARTIAL state's default value for txreg_bleed_ena in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_TXREG_BLEED_ENA_O_K2_E5_SHIFT             6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_TX_LOWPWR_IDLE_ENA_O_K2_E5                (0x1<<7) // MSM Function PARTIAL state's default value for tx_lowpwr_idle_ena in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT          7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_K2_E5                                                        0x002a78UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_CDR_EN_O_K2_E5                            (0x1<<0) // MSM Function PARTIAL state's default value for cdr_en in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_CDR_EN_O_K2_E5_SHIFT                      0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RXBCLK_EN_O_K2_E5                         (0x1<<1) // MSM Function PARTIAL state's default value for rxbclk_en in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RXBCLK_EN_O_K2_E5_SHIFT                   1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RX_GATE_EN_O_K2_E5                        (0x1<<2) // MSM Function PARTIAL state's default value for rx_gate_en in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RX_GATE_EN_O_K2_E5_SHIFT                  2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RESET_TX_CLKDIV_O_K2_E5                   (0x1<<3) // MSM Function PARTIAL state's default value for reset_tx_clkdiv in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RESET_TX_CLKDIV_O_K2_E5_SHIFT             3
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_K2_E5                                                        0x002a7cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_IDDQ_SD_O_K2_E5                           (0x1<<0) // MSM Function SLUMBER state's default value for iddq_sd in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_IDDQ_SD_O_K2_E5_SHIFT                     0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_DFE_O_K2_E5                            (0x1<<1) // MSM Function SLUMBER state's default value for pd_dfe in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_DFE_O_K2_E5_SHIFT                      1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_DFE_BIAS_O_K2_E5                       (0x1<<2) // MSM Function SLUMBER state's default value for pd_dfe_bias in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_DFE_BIAS_O_K2_E5_SHIFT                 2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_LNREG_O_K2_E5                          (0x1<<3) // MSM Function SLUMBER state's default value for pd_lnreg in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_LNREG_O_K2_E5_SHIFT                    3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_LNREGH_O_K2_E5                         (0x1<<4) // MSM Function SLUMBER state's default value for pd_lnregh in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_LNREGH_O_K2_E5_SHIFT                   4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_P2S_O_K2_E5                            (0x1<<5) // MSM Function SLUMBER state's default value for pd_p2s in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_P2S_O_K2_E5_SHIFT                      5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_RA_O_K2_E5                             (0x1<<6) // MSM Function SLUMBER state's default value for pd_ra in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_RA_O_K2_E5_SHIFT                       6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_S2P_O_K2_E5                            (0x1<<7) // MSM Function SLUMBER state's default value for pd_s2p in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_S2P_O_K2_E5_SHIFT                      7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_K2_E5                                                        0x002a80UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_SLV_BIAS_O_K2_E5                       (0x1<<0) // MSM Function SLUMBER state's default value for pd_slv_bias in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_SLV_BIAS_O_K2_E5_SHIFT                 0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_TXDRV_O_K2_E5                          (0x1<<1) // MSM Function SLUMBER state's default value for pd_txdrv in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_TXDRV_O_K2_E5_SHIFT                    1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_TXREG_O_K2_E5                          (0x1<<2) // MSM Function SLUMBER state's default value for pd_txreg in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_TXREG_O_K2_E5_SHIFT                    2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_VCO_O_K2_E5                            (0x1<<3) // MSM Function SLUMBER state's default value for pd_vco in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_VCO_O_K2_E5_SHIFT                      3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_VCO_BUF_O_K2_E5                        (0x1<<4) // MSM Function SLUMBER state's default value for pd_vco_buf in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_VCO_BUF_O_K2_E5_SHIFT                  4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_CDR_O_K2_E5                         (0x1<<5) // MSM Function SLUMBER state's default value for reset_cdr in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_CDR_O_K2_E5_SHIFT                   5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_CDR_GCRX_O_K2_E5                    (0x1<<6) // MSM Function SLUMBER state's default value for reset_cdr_gcrx in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_CDR_GCRX_O_K2_E5_SHIFT              6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_DFE_O_K2_E5                         (0x1<<7) // MSM Function SLUMBER state's default value for reset_dfe in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_DFE_O_K2_E5_SHIFT                   7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_K2_E5                                                        0x002a84UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_LNREG_O_K2_E5                       (0x1<<0) // MSM Function SLUMBER state's default value for reset_lnreg in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_LNREG_O_K2_E5_SHIFT                 0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_LNREGH_O_K2_E5                      (0x1<<1) // MSM Function SLUMBER state's default value for reset_lnregh in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_LNREGH_O_K2_E5_SHIFT                1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_P2S_O_K2_E5                         (0x1<<2) // MSM Function SLUMBER state's default value for reset_p2s in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_P2S_O_K2_E5_SHIFT                   2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_RA_O_K2_E5                          (0x1<<3) // MSM Function SLUMBER state's default value for reset_ra in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_RA_O_K2_E5_SHIFT                    3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_S2P_O_K2_E5                         (0x1<<4) // MSM Function SLUMBER state's default value for reset_s2p in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_S2P_O_K2_E5_SHIFT                   4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_VCO_O_K2_E5                         (0x1<<5) // MSM Function SLUMBER state's default value for reset_vco in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_VCO_O_K2_E5_SHIFT                   5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_TXREG_BLEED_ENA_O_K2_E5                   (0x1<<6) // MSM Function SLUMBER state's default value for txreg_bleed_ena in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_TXREG_BLEED_ENA_O_K2_E5_SHIFT             6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_TX_LOWPWR_IDLE_ENA_O_K2_E5                (0x1<<7) // MSM Function SLUMBER state's default value for tx_lowpwr_idle_ena in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT          7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_K2_E5                                                        0x002a88UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_CDR_EN_O_K2_E5                            (0x1<<0) // MSM Function SLUMBER state's default value for cdr_en in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_CDR_EN_O_K2_E5_SHIFT                      0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RXBCLK_EN_O_K2_E5                         (0x1<<1) // MSM Function SLUMBER state's default value for rxbclk_en in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RXBCLK_EN_O_K2_E5_SHIFT                   1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RX_GATE_EN_O_K2_E5                        (0x1<<2) // MSM Function SLUMBER state's default value for rx_gate_en in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RX_GATE_EN_O_K2_E5_SHIFT                  2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RESET_TX_CLKDIV_O_K2_E5                   (0x1<<3) // MSM Function SLUMBER state's default value for reset_tx_clkdiv in SAPIS mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RESET_TX_CLKDIV_O_K2_E5_SHIFT             3
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG18_K2_E5                                               0x002a8cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG19_K2_E5                                               0x002a90UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG20_K2_E5                                               0x002a94UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG21_K2_E5                                               0x002a98UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG22_K2_E5                                               0x002a9cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X168_K2_E5                                                        0x002aa0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X168_OOB_DET_BLEN_MIN_O_6_0_K2_E5                               (0x7f<<0) // OOB detector minimum burst length.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X168_OOB_DET_BLEN_MIN_O_6_0_K2_E5_SHIFT                         0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X169_K2_E5                                                        0x002aa4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X169_OOB_DET_BLEN_MAX_O_6_0_K2_E5                               (0x7f<<0) // OOB detector maximum burst length.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X169_OOB_DET_BLEN_MAX_O_6_0_K2_E5_SHIFT                         0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X170_K2_E5                                                        0x002aa8UL //Access:RW   DataWidth:0x8    // OOB detector COMINIT maximum idle length.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X171_K2_E5                                                        0x002aacUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X171_OOB_DET_COMINIT_MIN_O_8_K2_E5                              (0x1<<0) // OOB detector COMINIT maximum idle length.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X171_OOB_DET_COMINIT_MIN_O_8_K2_E5_SHIFT                        0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X172_K2_E5                                                        0x002ab0UL //Access:RW   DataWidth:0x8    // OOB detector COMINIT maximum idle length.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X173_K2_E5                                                        0x002ab4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X173_OOB_DET_COMINIT_MAX_O_8_K2_E5                              (0x1<<0) // OOB detector COMINIT maximum idle length.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X173_OOB_DET_COMINIT_MAX_O_8_K2_E5_SHIFT                        0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X174_K2_E5                                                        0x002ab8UL //Access:RW   DataWidth:0x8    // OOB detector COMWAKE minimum idle length.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X175_K2_E5                                                        0x002abcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X175_OOB_DET_COMWAKE_MIN_O_8_K2_E5                              (0x1<<0) // OOB detector COMWAKE minimum idle length.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X175_OOB_DET_COMWAKE_MIN_O_8_K2_E5_SHIFT                        0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X176_K2_E5                                                        0x002ac0UL //Access:RW   DataWidth:0x8    // OOB detector COMWAKE maximum idle length.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X177_K2_E5                                                        0x002ac4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X177_OOB_DET_COMWAKE_MAX_O_8_K2_E5                              (0x1<<0) // OOB detector COMWAKE maximum idle length.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X177_OOB_DET_COMWAKE_MAX_O_8_K2_E5_SHIFT                        0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X178_K2_E5                                                        0x002ac8UL //Access:RW   DataWidth:0x8    // OOB detector COMSAS maximum idle length.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X179_K2_E5                                                        0x002accUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X179_OOB_DET_COMSAS_MIN_O_8_K2_E5                               (0x1<<0) // OOB detector COMSAS maximum idle length.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X179_OOB_DET_COMSAS_MIN_O_8_K2_E5_SHIFT                         0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X180_K2_E5                                                        0x002ad0UL //Access:RW   DataWidth:0x8    // OOB detector COMSAS maximum idle length.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X181_K2_E5                                                        0x002ad4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X181_OOB_DET_COMSAS_MAX_O_8_K2_E5                               (0x1<<0) // OOB detector COMSAS maximum idle length.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X181_OOB_DET_COMSAS_MAX_O_8_K2_E5_SHIFT                         0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X210_K2_E5                                                        0x002b48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X210_TXEQ_CM1_FORCE_LOW_EN_O_K2_E5                              (0x1<<6) // Brings the TxEq pre-cursor down to a programmable value txeq_cm1_min_limit if pre cursor tuning is bypassed
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X210_TXEQ_CM1_FORCE_LOW_EN_O_K2_E5_SHIFT                        6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X210_TXEQ_C1_FORCE_LOW_EN_O_K2_E5                               (0x1<<7) // Brings the TxEq pre-cursor down to a programmable value txeq_c1_min_limit if pre cursor tuning is bypassed
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X210_TXEQ_C1_FORCE_LOW_EN_O_K2_E5_SHIFT                         7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X211_K2_E5                                                        0x002b4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X211_RX_BIAS_00_O_2_0_K2_E5                                     (0x7<<0) // AFE rx_bias setting. Used when rxvcodiv is 00
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X211_RX_BIAS_00_O_2_0_K2_E5_SHIFT                               0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X211_RX_BIAS_01_O_2_0_K2_E5                                     (0x7<<3) // AFE rx_bias setting. Used when rxvcodiv is 01 or 10
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X211_RX_BIAS_01_O_2_0_K2_E5_SHIFT                               3
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X212_K2_E5                                                        0x002b50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X212_RX_BIAS_11_O_2_0_K2_E5                                     (0x7<<0) // AFE rx_bias setting. Used when rxvcodiv is 11
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X212_RX_BIAS_11_O_2_0_K2_E5_SHIFT                               0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X213_K2_E5                                                        0x002b54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X213_QAHB_CDR_VCO_CAL_PHD_ENA_O_K2_E5                           (0x1<<6) // Enable phase detector during CDR VCO calibration
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X213_QAHB_CDR_VCO_CAL_PHD_ENA_O_K2_E5_SHIFT                     6
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X214_K2_E5                                                        0x002b58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_CDR_LOCK_WAIT_O_3_0_K2_E5                             (0xf<<0) // Number of wait cycles for the CDR to lock [3:0] times 64
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_CDR_LOCK_WAIT_O_3_0_K2_E5_SHIFT                       0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_RATE_CHNG_CAL_O_K2_E5                                 (0x1<<4) // Assertion causes repeat of calibration for rate switch or electrical idle exit. Calibrations to be performed are selected by rxeq_recal_o[6:0]/rxeq_rate2_recal_o[6:0].
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_RATE_CHNG_CAL_O_K2_E5_SHIFT                           4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_PRESET_CLR_DFE_O_K2_E5                                (0x1<<6) // Set all DFE calibration values to mid-scale instead of using start values at start of calibration
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_PRESET_CLR_DFE_O_K2_E5_SHIFT                          6
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X215_K2_E5                                                        0x002b5cUL //Access:RW   DataWidth:0x8    // DFE block -continuous calibration wait delay. DFE block will wait this number of cycles between each continuous calibration cycle
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X216_K2_E5                                                        0x002b60UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X216_RXEQ_CONT_LENGTH_O_14_8_K2_E5                              (0x7f<<0) // DFE block -continuous calibration wait delay. DFE block will wait this number of cycles between each continuous calibration cycle
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X216_RXEQ_CONT_LENGTH_O_14_8_K2_E5_SHIFT                        0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X217_K2_E5                                                        0x002b64UL //Access:RW   DataWidth:0x8    // DFE block - ATT calibration cycle length. This is the number of cycles the DFE will wait between changing the ATT value and examining the output.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X218_K2_E5                                                        0x002b68UL //Access:RW   DataWidth:0x8    // DFE block - Boost calibration cycle length. This is the number of cycles the DFE will wait between changing the boost value and examining the output.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X219_K2_E5                                                        0x002b6cUL //Access:RW   DataWidth:0x8    // DFE block - TAP1 calibration cycle length. This is the number of cycles the DFE will wait between changing the TAP1 value and examining the output.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X220_K2_E5                                                        0x002b70UL //Access:RW   DataWidth:0x8    // DFE block - TAP2 calibration cycle length. This is the number of cycles the DFE will wait between changing the TAP2 value and examining the output.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X221_K2_E5                                                        0x002b74UL //Access:RW   DataWidth:0x8    // DFE block - TAP3 calibration cycle length. This is the number of cycles the DFE will wait between changing the TAP2 value and examining the output.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X222_K2_E5                                                        0x002b78UL //Access:RW   DataWidth:0x8    // DFE block - TAP4 calibration cycle length. This is the number of cycles the DFE will wait between changing the TAP2 value and examining the output.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X223_K2_E5                                                        0x002b7cUL //Access:RW   DataWidth:0x8    // DFE block - TAP5 calibration cycle length. This is the number of cycles the DFE will wait between changing the TAP2 value and examining the output.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X224_K2_E5                                                        0x002b80UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X224_RXEQ_EI_EXIT_CAL_O_K2_E5                                   (0x1<<0) // Repeat calibration whenever exiting RX electrical idle. Calibrations performed are selected by rxeq_recal_o[6:0]/rxeq_lane2_recal_o[6:0]
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X224_RXEQ_EI_EXIT_CAL_O_K2_E5_SHIFT                             0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X224_RXEQ_RECAL_O_6_0_K2_E5                                     (0x7f<<1) // Enables re-calibration for { Tap5, Tap4, Tap3, Tap2, Tap1, Boost, ATT} at rate3 after exit from electrical idle when rxeq_ei_exit_cal_o is asserted and after rate change when rxeq_rate_chng_cal_o is asserted.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X224_RXEQ_RECAL_O_6_0_K2_E5_SHIFT                               1
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X225_K2_E5                                                        0x002b84UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X225_RXEQ_RATE2_INIT_CAL_O_6_0_K2_E5                            (0x7f<<0) // Specify which block needs initial calibration upon exit from RX electrical idle state for rate2: bit [0]: Enables ATT calibration when asserted bit [1]: Enables Boost calibration when asserted bit [2]: Enables DFE Tap1 calibration when asserted bit [3]: Enables DFE Tap2 calibration when asserted bit [4]: Enables DFE Tap3 calibration when asserted bit [5]: Enables DFE Tap4 calibration when asserted bit [6]: Enables DFE Tap5 calibration when asserted
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X225_RXEQ_RATE2_INIT_CAL_O_6_0_K2_E5_SHIFT                      0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X226_K2_E5                                                        0x002b88UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X226_RXEQ_RATE2_CONT_CAL_O_6_0_K2_E5                            (0x7f<<0) // Specify which block needs continuous calibration during RX data reception for rate2 bit [0]: Enables ATT calibration when asserted bit [1]: Enables Boost calibration when asserted bit [2]: Enables DFE Tap1 calibration when asserted bit [3]: Enables DFE Tap2 calibration when asserted bit [4]: Enables DFE Tap3 calibration when asserted bit [5]: Enables DFE Tap4 calibration when asserted bit [6]: Enables DFE Tap5 calibration when asserted
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X226_RXEQ_RATE2_CONT_CAL_O_6_0_K2_E5_SHIFT                      0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X227_K2_E5                                                        0x002b8cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X227_RXEQ_RATE2_RECAL_O_6_0_K2_E5                               (0x7f<<0) // Enables re-calibration for { Tap5, Tap4, Tap3, Tap2, Tap1, Boost, ATT} at rate2 after exit from electrical idle when rxeq_ei_exit_cal_o is asserted and after rate change when rxeq_rate_chng_cal_o is asserted.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X227_RXEQ_RATE2_RECAL_O_6_0_K2_E5_SHIFT                         0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X228_K2_E5                                                        0x002b90UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X228_RXEQ_ATT_BOUNCE_O_3_0_K2_E5                                (0xf<<0) // Number of bounces before calibration stops for ATT
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X228_RXEQ_ATT_BOUNCE_O_3_0_K2_E5_SHIFT                          0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X228_RXEQ_BOOST_BOUNCE_O_3_0_K2_E5                              (0xf<<4) // Number of bounces before calibration stops for Boost
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X228_RXEQ_BOOST_BOUNCE_O_3_0_K2_E5_SHIFT                        4
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X229_K2_E5                                                        0x002b94UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X229_RXEQ_TAP1_BOUNCE_O_3_0_K2_E5                               (0xf<<0) // Number of bounces before calibration stops for DFE tap1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X229_RXEQ_TAP1_BOUNCE_O_3_0_K2_E5_SHIFT                         0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X229_RXEQ_TAP2_BOUNCE_O_3_0_K2_E5                               (0xf<<4) // Number of bounces before calibration stops for DFE tap2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X229_RXEQ_TAP2_BOUNCE_O_3_0_K2_E5_SHIFT                         4
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X230_K2_E5                                                        0x002b98UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X230_RXEQ_TAP3_BOUNCE_O_3_0_K2_E5                               (0xf<<0) // Number of bounces before calibration stops for DFE tap3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X230_RXEQ_TAP3_BOUNCE_O_3_0_K2_E5_SHIFT                         0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X230_RXEQ_TAP4_BOUNCE_O_3_0_K2_E5                               (0xf<<4) // Number of bounces before calibration stops for DFE tap4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X230_RXEQ_TAP4_BOUNCE_O_3_0_K2_E5_SHIFT                         4
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X231_K2_E5                                                        0x002b9cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X231_RXEQ_TAP5_BOUNCE_O_3_0_K2_E5                               (0xf<<0) // Number of bounces before calibration stops for DFE tap5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X231_RXEQ_TAP5_BOUNCE_O_3_0_K2_E5_SHIFT                         0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X231_RXEQ_COARSE_STEP_SIZE_O_3_0_K2_E5                          (0xf<<4) // Initial calibration coarse step size
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X231_RXEQ_COARSE_STEP_SIZE_O_3_0_K2_E5_SHIFT                    4
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X232_K2_E5                                                        0x002ba0UL //Access:RW   DataWidth:0x8    // comparator offset override value
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X233_K2_E5                                                        0x002ba4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X233_CMP_OFFSET_OVR_EN_O_K2_E5                                  (0x1<<0) // comparator offset override enable
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X233_CMP_OFFSET_OVR_EN_O_K2_E5_SHIFT                            0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X233_RXEQ_FIN_HIGH_O_6_0_K2_E5                                  (0x7f<<1) // Enable final calibration value plus one for individual blocks
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X233_RXEQ_FIN_HIGH_O_6_0_K2_E5_SHIFT                            1
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X234_K2_E5                                                        0x002ba8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X234_RXEQ_FIN_LOW_O_6_0_K2_E5                                   (0x7f<<0) // Enable final calibration value minus one for individual blocks
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X234_RXEQ_FIN_LOW_O_6_0_K2_E5_SHIFT                             0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X234_QAHB_DFE_RAW_VALUE_O_K2_E5                                 (0x1<<7) // Testbus select for comp_offset and tap_offset 1: Raw output from i_dfe_tap_dc_offset 0: Input to pma
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X234_QAHB_DFE_RAW_VALUE_O_K2_E5_SHIFT                           7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X235_K2_E5                                                        0x002bacUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X235_RXEQ_ERR_SIGN_O_6_0_K2_E5                                  (0x7f<<0) // Controls polarity of RX calibration: bit [0]: Reverses polarity of ATT calibration when asserted bit [1]: Reverses polarity of Boost calibration when asserted bit [2]: Reverses polarity of DFE Tap1 calibration when asserted bit [3]: Reverses polarity of DFE Tap2 calibration when asserted bit [4]: Reverses polarity of DFE Tap3 calibration when asserted bit [5]: Reverses polarity of DFE Tap4 calibration when asserted bit [6]: Reverses polarity of DFE Tap5 calibration when asserted
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X235_RXEQ_ERR_SIGN_O_6_0_K2_E5_SHIFT                            0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X236_K2_E5                                                        0x002bb0UL //Access:RW   DataWidth:0x8    // Training pattern for boost
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X237_K2_E5                                                        0x002bb4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X237_RXEQ_RATE1_BOOST_TRAINING_PATT_O_8_K2_E5                   (0x1<<0) // Training pattern for boost
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X237_RXEQ_RATE1_BOOST_TRAINING_PATT_O_8_K2_E5_SHIFT             0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X238_K2_E5                                                        0x002bb8UL //Access:RW   DataWidth:0x8    // Training pattern for DFE tap1
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X239_K2_E5                                                        0x002bbcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X239_RXEQ_TAP1_TRAINING_PATT_O_8_K2_E5                          (0x1<<0) // Training pattern for DFE tap1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X239_RXEQ_TAP1_TRAINING_PATT_O_8_K2_E5_SHIFT                    0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X240_K2_E5                                                        0x002bc0UL //Access:RW   DataWidth:0x8    // Training pattern for DFE tap2
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X241_K2_E5                                                        0x002bc4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X241_RXEQ_TAP2_TRAINING_PATT_O_8_K2_E5                          (0x1<<0) // Training pattern for DFE tap2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X241_RXEQ_TAP2_TRAINING_PATT_O_8_K2_E5_SHIFT                    0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X242_K2_E5                                                        0x002bc8UL //Access:RW   DataWidth:0x8    // Training pattern for DFE tap3
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X243_K2_E5                                                        0x002bccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X243_RXEQ_TAP3_TRAINING_PATT_O_8_K2_E5                          (0x1<<0) // Training pattern for DFE tap3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X243_RXEQ_TAP3_TRAINING_PATT_O_8_K2_E5_SHIFT                    0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X244_K2_E5                                                        0x002bd0UL //Access:RW   DataWidth:0x8    // Training pattern for DFE tap4
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X245_K2_E5                                                        0x002bd4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X245_RXEQ_TAP4_TRAINING_PATT_O_8_K2_E5                          (0x1<<0) // Training pattern for DFE tap4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X245_RXEQ_TAP4_TRAINING_PATT_O_8_K2_E5_SHIFT                    0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X246_K2_E5                                                        0x002bd8UL //Access:RW   DataWidth:0x8    // Training pattern for DFE tap5
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X247_K2_E5                                                        0x002bdcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X247_RXEQ_TAP5_TRAINING_PATT_O_8_K2_E5                          (0x1<<0) // Training pattern for DFE tap5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X247_RXEQ_TAP5_TRAINING_PATT_O_8_K2_E5_SHIFT                    0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X248_K2_E5                                                        0x002be0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_DONT_CARE_O_5_0_K2_E5                                 (0x3f<<0) // Sets certain bits in training pattern as don't care
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_DONT_CARE_O_5_0_K2_E5_SHIFT                           0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_STEP_MODE_O_K2_E5                                     (0x1<<6) // RXEQ ctrl_test mode enable
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_STEP_MODE_O_K2_E5_SHIFT                               6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_STEP_O_K2_E5                                          (0x1<<7) // Step calibration in test mode, rising edge triggers step
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_STEP_O_K2_E5_SHIFT                                    7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X249_K2_E5                                                        0x002be4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X249_RXEQ_AVG4_O_6_0_K2_E5                                      (0x7f<<0) // Enable average 4 in calibration, otherwise average2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X249_RXEQ_AVG4_O_6_0_K2_E5_SHIFT                                0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X249_RXEQ_FLOOR_O_K2_E5                                         (0x1<<7) // Take the floor of the calibration result
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X249_RXEQ_FLOOR_O_K2_E5_SHIFT                                   7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X250_K2_E5                                                        0x002be8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X250_RXEQ_SHIFT_O_3_0_K2_E5                                     (0xf<<0) // Shift the edge samples in rxeq_ctrl
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X250_RXEQ_SHIFT_O_3_0_K2_E5_SHIFT                               0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X251_K2_E5                                                        0x002becUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X251_RXEQ_RATE3_DFE_TAP_PD_O_4_0_K2_E5                          (0x1f<<0) // DFE tap powerdown for rate3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X251_RXEQ_RATE3_DFE_TAP_PD_O_4_0_K2_E5_SHIFT                    0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X252_K2_E5                                                        0x002bf0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X252_RXEQ_RATE2_DFE_TAP_PD_O_4_0_K2_E5                          (0x1f<<0) // DFE tap powerdown for rate2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X252_RXEQ_RATE2_DFE_TAP_PD_O_4_0_K2_E5_SHIFT                    0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X252_REVERSE_TAP_PD_ORDER_O_K2_E5                               (0x1<<5) // Reverse order of tap power down signals
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X252_REVERSE_TAP_PD_ORDER_O_K2_E5_SHIFT                         5
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X253_K2_E5                                                        0x002bf4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X253_MSM_LN_DFE_TAP_WAIT_O_4_0_K2_E5                            (0x1f<<0) // Wait time between each DFE tap DC offset calibration
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X253_MSM_LN_DFE_TAP_WAIT_O_4_0_K2_E5_SHIFT                      0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X253_SKP_CMP_CAL_O_K2_E5                                        (0x1<<5) // By pass comparator DC offset calibration
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X253_SKP_CMP_CAL_O_K2_E5_SHIFT                                  5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X253_DFE_TAP_OFFSET_CAL_DIR_O_K2_E5                             (0x1<<6) // Changes the dfe tap offset cal direction
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X253_DFE_TAP_OFFSET_CAL_DIR_O_K2_E5_SHIFT                       6
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X254_K2_E5                                                        0x002bf8UL //Access:RW   DataWidth:0x8    // Training pattern for boost in rate2
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X255_K2_E5                                                        0x002bfcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X255_RXEQ_RATE2_BOOST_TRAINING_PATT_O_8_K2_E5                   (0x1<<0) // Training pattern for boost in rate2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X255_RXEQ_RATE2_BOOST_TRAINING_PATT_O_8_K2_E5_SHIFT             0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X256_K2_E5                                                        0x002c00UL //Access:RW   DataWidth:0x8    // Training pattern for boost in rate3
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X257_K2_E5                                                        0x002c04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X257_RXEQ_RATE3_BOOST_TRAINING_PATT_O_8_K2_E5                   (0x1<<0) // Training pattern for boost in rate3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X257_RXEQ_RATE3_BOOST_TRAINING_PATT_O_8_K2_E5_SHIFT             0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X258_K2_E5                                                        0x002c08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X258_RXEQ_RATE1_BOOST_DONT_CARE_O_5_0_K2_E5                     (0x3f<<0) // Sets certain bits in training pattern as don't care in rate1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X258_RXEQ_RATE1_BOOST_DONT_CARE_O_5_0_K2_E5_SHIFT               0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X259_K2_E5                                                        0x002c0cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X259_RXEQ_RATE2_BOOST_DONT_CARE_O_5_0_K2_E5                     (0x3f<<0) // Sets certain bits in training pattern as don't care in rate2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X259_RXEQ_RATE2_BOOST_DONT_CARE_O_5_0_K2_E5_SHIFT               0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X260_K2_E5                                                        0x002c10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X260_RXEQ_RATE3_BOOST_DONT_CARE_O_5_0_K2_E5                     (0x3f<<0) // Sets certain bits in training pattern as don't care in rate3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X260_RXEQ_RATE3_BOOST_DONT_CARE_O_5_0_K2_E5_SHIFT               0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X261_K2_E5                                                        0x002c14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X261_DFE_SHADOW_LANE_SEL_K2_E5                                  (0x3<<5) // DFE TAP shadow register lane select
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X261_DFE_SHADOW_LANE_SEL_K2_E5_SHIFT                            5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X261_DFE_SHADOW_OFST_RD_SEL_K2_E5                               (0x1<<7) // DFE shadow offset read select
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X261_DFE_SHADOW_OFST_RD_SEL_K2_E5_SHIFT                         7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X263_K2_E5                                                        0x002c1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X263_RATE3_RATESWITCH_RXRECAL_CFG_6_0_K2_E5                     (0x7f<<0) // Gen3 rate switch cal elements
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X263_RATE3_RATESWITCH_RXRECAL_CFG_6_0_K2_E5_SHIFT               0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X264_K2_E5                                                        0x002c20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X264_RATE3_TXEQ_RXRECAL_BEGIN_CFG_6_0_K2_E5                     (0x7f<<0) // Gen3 beginning of TxEQ RxEQ cal elements
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X264_RATE3_TXEQ_RXRECAL_BEGIN_CFG_6_0_K2_E5_SHIFT               0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X265_K2_E5                                                        0x002c24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X265_RATE3_TXEQ_RXRECAL_END_CFG_6_0_K2_E5                       (0x7f<<0) // Gen3 end of TxEQ RxEQ cal elements
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X265_RATE3_TXEQ_RXRECAL_END_CFG_6_0_K2_E5_SHIFT                 0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X266_K2_E5                                                        0x002c28UL //Access:R    DataWidth:0x8    // DFE CMP value read
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X267_K2_E5                                                        0x002c2cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X267_DFE_TAP1_VAL_K2_E5                                         (0x7f<<0) // DFE TAP1 value read
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X267_DFE_TAP1_VAL_K2_E5_SHIFT                                   0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X268_K2_E5                                                        0x002c30UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X268_DFE_TAP2_VAL_K2_E5                                         (0x3f<<0) // DFE TAP2 value read
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X268_DFE_TAP2_VAL_K2_E5_SHIFT                                   0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X269_K2_E5                                                        0x002c34UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X269_DFE_TAP3_VAL_K2_E5                                         (0x3f<<0) // DFE TAP3 value read
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X269_DFE_TAP3_VAL_K2_E5_SHIFT                                   0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X270_K2_E5                                                        0x002c38UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X270_DFE_TAP4_VAL_K2_E5                                         (0x3f<<0) // DFE TAP4 value read
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X270_DFE_TAP4_VAL_K2_E5_SHIFT                                   0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X271_K2_E5                                                        0x002c3cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X271_DFE_TAP5_VAL_K2_E5                                         (0x3f<<0) // DFE TAP5 value read
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X271_DFE_TAP5_VAL_K2_E5_SHIFT                                   0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X272_K2_E5                                                        0x002c40UL //Access:RW   DataWidth:0x8    // Training pattern for TxEQ adapt DFE tap1 cm1 [7:0]
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X273_K2_E5                                                        0x002c44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X273_TAP1_CM1_TRAINING_PATT_8_K2_E5                             (0x1<<0) // Training pattern for TxEQ adapt DFE tap1 cm1 [8]
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X273_TAP1_CM1_TRAINING_PATT_8_K2_E5_SHIFT                       0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X273_TXEQ_ADAPT_RUN_1_0_K2_E5                                   (0x3<<1) // TxEQ Adapt 2 TAPs
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X273_TXEQ_ADAPT_RUN_1_0_K2_E5_SHIFT                             1
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X274_K2_E5                                                        0x002c48UL //Access:RW   DataWidth:0x8    // Training pattern for TxEQ adapt DFE tap1 c1 [7:0]
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X275_K2_E5                                                        0x002c4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X275_TAP1_C1_TRAINING_PATT_8_K2_E5                              (0x1<<0) // Training pattern for TxEQ adapt DFE tap1 c1 [8]
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X275_TAP1_C1_TRAINING_PATT_8_K2_E5_SHIFT                        0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X275_TXEQ_ADAPT_INIT_O_1_K2_E5                                  (0x1<<1) // Initiate TXEQ adaptation for Gen3 rate
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X275_TXEQ_ADAPT_INIT_O_1_K2_E5_SHIFT                            1
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X281_K2_E5                                                        0x002c64UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X281_RXEQ_CAL_DONE_I_3_0_K2_E5                                  (0xf<<0) // RXEQ calibration done status - per lane
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X281_RXEQ_CAL_DONE_I_3_0_K2_E5_SHIFT                            0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X281_TXEQ_ADAPT_DONE_I_3_0_K2_E5                                (0xf<<4) // TXEQ Adapt Done status - per lane
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X281_TXEQ_ADAPT_DONE_I_3_0_K2_E5_SHIFT                          4
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X296_K2_E5                                                        0x002ca0UL //Access:RW   DataWidth:0x8    // Txeq CM1 coefficient adpatation error measurment wait time during each iteration
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X297_K2_E5                                                        0x002ca4UL //Access:RW   DataWidth:0x8    // Txeq C1 coefficient adpatation error measurment wait time during each iteration
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X301_K2_E5                                                        0x002cb4UL //Access:RW   DataWidth:0x8    // 
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG23_K2_E5                                               0x002cbcUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X304_K2_E5                                                        0x002cc0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X304_QAHB_CDFE_RATE3_LOAD_EYE_CNT_WAIT_K2_E5                    (0xf<<0) // 
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X304_QAHB_CDFE_RATE3_LOAD_EYE_CNT_WAIT_K2_E5_SHIFT              0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X304_QAHB_CDFE_RATE3_EYE_IN_RST_WAIT_3_0_K2_E5                  (0xf<<4) // 
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X304_QAHB_CDFE_RATE3_EYE_IN_RST_WAIT_3_0_K2_E5_SHIFT            4
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X305_K2_E5                                                        0x002cc4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X305_QAHB_CDFE_RATE3_EXIT_EYE_RST_WAIT_K2_E5                    (0xf<<0) // 
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X305_QAHB_CDFE_RATE3_EXIT_EYE_RST_WAIT_K2_E5_SHIFT              0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X305_QAHB_CDFE_RATE3_DFE_STROBE_REDGE_WAIT_3_0_K2_E5            (0xf<<4) // 
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X305_QAHB_CDFE_RATE3_DFE_STROBE_REDGE_WAIT_3_0_K2_E5_SHIFT      4
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X306_K2_E5                                                        0x002cc8UL //Access:RW   DataWidth:0x8    // 
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X307_K2_E5                                                        0x002cccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X307_QAHB_CDFE_RATE3_MIN_EYE_DLY_K2_E5                          (0x7f<<0) // Minimum eye delay value for rate3 during dll calibration
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X307_QAHB_CDFE_RATE3_MIN_EYE_DLY_K2_E5_SHIFT                    0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X308_K2_E5                                                        0x002cd0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X308_QAHB_CDFE_RATE3_MAX_EYE_DLY_K2_E5                          (0x7f<<0) // Maximum eye delay value for rate3 during dll calibration
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X308_QAHB_CDFE_RATE3_MAX_EYE_DLY_K2_E5_SHIFT                    0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X310_K2_E5                                                        0x002cd8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X310_QAHB_CDFE_RATE3_TAP1_PATT_MASK_6_0_K2_E5                   (0x7f<<0) // cdfe tap1 training pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X310_QAHB_CDFE_RATE3_TAP1_PATT_MASK_6_0_K2_E5_SHIFT             0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X311_K2_E5                                                        0x002cdcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X311_QAHB_CDFE_RATE3_TAP2_PATT_MASK_6_0_K2_E5                   (0x7f<<0) // cdfe tap2 training pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X311_QAHB_CDFE_RATE3_TAP2_PATT_MASK_6_0_K2_E5_SHIFT             0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X312_K2_E5                                                        0x002ce0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X312_QAHB_CDFE_RATE3_TAP3_PATT_MASK_6_0_K2_E5                   (0x7f<<0) // cdfe tap3 training pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X312_QAHB_CDFE_RATE3_TAP3_PATT_MASK_6_0_K2_E5_SHIFT             0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X313_K2_E5                                                        0x002ce4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X313_QAHB_CDFE_RATE3_TAP4_PATT_MASK_6_0_K2_E5                   (0x7f<<0) // cdfe tap4 training pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X313_QAHB_CDFE_RATE3_TAP4_PATT_MASK_6_0_K2_E5_SHIFT             0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X314_K2_E5                                                        0x002ce8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X314_QAHB_CDFE_RATE3_TAP5_PATT_MASK_6_0_K2_E5                   (0x7f<<0) // cdfe tap5 training pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X314_QAHB_CDFE_RATE3_TAP5_PATT_MASK_6_0_K2_E5_SHIFT             0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X315_K2_E5                                                        0x002cecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X315_QAHB_CDFE_RATE3_DLEV_PATT_MASK_6_0_K2_E5                   (0x7f<<0) // cdfe dlev training pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X315_QAHB_CDFE_RATE3_DLEV_PATT_MASK_6_0_K2_E5_SHIFT             0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG24_K2_E5                                               0x002cf4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X318_K2_E5                                                        0x002cf8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X318_QAHB_CDFE_RATE2_LOAD_EYE_CNT_WAIT_K2_E5                    (0xf<<0) // 
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X318_QAHB_CDFE_RATE2_LOAD_EYE_CNT_WAIT_K2_E5_SHIFT              0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X318_QAHB_CDFE_RATE2_EYE_IN_RST_WAIT_3_0_K2_E5                  (0xf<<4) // 
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X318_QAHB_CDFE_RATE2_EYE_IN_RST_WAIT_3_0_K2_E5_SHIFT            4
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X319_K2_E5                                                        0x002cfcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X319_QAHB_CDFE_RATE2_EXIT_EYE_RST_WAIT_K2_E5                    (0xf<<0) // 
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X319_QAHB_CDFE_RATE2_EXIT_EYE_RST_WAIT_K2_E5_SHIFT              0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X319_QAHB_CDFE_RATE2_DFE_STROBE_REDGE_WAIT_3_0_K2_E5            (0xf<<4) // 
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X319_QAHB_CDFE_RATE2_DFE_STROBE_REDGE_WAIT_3_0_K2_E5_SHIFT      4
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X320_K2_E5                                                        0x002d00UL //Access:RW   DataWidth:0x8    // 
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X321_K2_E5                                                        0x002d04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X321_QAHB_CDFE_RATE2_MIN_EYE_DLY_6_0_K2_E5                      (0x7f<<0) // Minimum eye delay value for rate2 during dll calibration
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X321_QAHB_CDFE_RATE2_MIN_EYE_DLY_6_0_K2_E5_SHIFT                0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X322_K2_E5                                                        0x002d08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X322_QAHB_CDFE_RATE2_MAX_EYE_DLY_K2_E5                          (0x7f<<0) // Maximum eye delay value for rate2 during dll calibration
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X322_QAHB_CDFE_RATE2_MAX_EYE_DLY_K2_E5_SHIFT                    0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X324_K2_E5                                                        0x002d10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X324_QAHB_CDFE_RATE2_TAP1_PATT_MASK_K2_E5                       (0x7f<<0) // cdfe tap1 training pattern masking bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X324_QAHB_CDFE_RATE2_TAP1_PATT_MASK_K2_E5_SHIFT                 0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X325_K2_E5                                                        0x002d14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X325_QAHB_CDFE_RATE2_TAP2_PATT_MASK_6_0_K2_E5                   (0x7f<<0) // cdfe tap2 training pattern masking bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X325_QAHB_CDFE_RATE2_TAP2_PATT_MASK_6_0_K2_E5_SHIFT             0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X326_K2_E5                                                        0x002d18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X326_QAHB_CDFE_RATE2_TAP3_PATT_MASK_6_0_K2_E5                   (0x7f<<0) // cdfe tap3 training pattern masking bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X326_QAHB_CDFE_RATE2_TAP3_PATT_MASK_6_0_K2_E5_SHIFT             0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X327_K2_E5                                                        0x002d1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X327_QAHB_CDFE_RATE2_TAP4_PATT_MASK_6_0_K2_E5                   (0x7f<<0) // cdfe tap4 training pattern masking bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X327_QAHB_CDFE_RATE2_TAP4_PATT_MASK_6_0_K2_E5_SHIFT             0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X328_K2_E5                                                        0x002d20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X328_QAHB_CDFE_RATE2_TAP5_PATT_MASK_6_0_K2_E5                   (0x7f<<0) // cdfe tap5 training pattern masking bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X328_QAHB_CDFE_RATE2_TAP5_PATT_MASK_6_0_K2_E5_SHIFT             0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X329_K2_E5                                                        0x002d24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X329_QAHB_CDFE_RATE2_DLEV_PATT_MASK_6_0_K2_E5                   (0x7f<<0) // cdfe dlev training pattern masking bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X329_QAHB_CDFE_RATE2_DLEV_PATT_MASK_6_0_K2_E5_SHIFT             0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X330_K2_E5                                                        0x002d28UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X330_QAHB_CDFE_CMP1_PRESET_OFFSET_5_0_K2_E5                     (0x3f<<0) // cdfe comparator1 offset values ovrride enable bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enables overriding tap2 offset bit[3] : enables overriding tap3 offset bit[4] : enables overriding tap4 offset bit[5] : enables overriding tap5 offset
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X330_QAHB_CDFE_CMP1_PRESET_OFFSET_5_0_K2_E5_SHIFT               0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X331_K2_E5                                                        0x002d2cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X331_QAHB_CDFE_CMP2_PRESET_OFFSET_5_0_K2_E5                     (0x3f<<0) // cdfe comparator2 offset values ovrride enable bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enables overriding tap2 offset bit[3] : enables overriding tap3 offset bit[4] : enables overriding tap4 offset bit[5] : enables overriding tap5 offset
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X331_QAHB_CDFE_CMP2_PRESET_OFFSET_5_0_K2_E5_SHIFT               0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X332_K2_E5                                                        0x002d30UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X332_QAHB_CDFE_CMP3_PRESET_OFFSET_5_0_K2_E5                     (0x3f<<0) // cdfe comparator3 offset values ovrride enable bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enables overriding tap2 offset bit[3] : enables overriding tap3 offset bit[4] : enables overriding tap4 offset bit[5] : enables overriding tap5 offset
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X332_QAHB_CDFE_CMP3_PRESET_OFFSET_5_0_K2_E5_SHIFT               0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X333_K2_E5                                                        0x002d34UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X333_QAHB_CDFE_CMP4_PRESET_OFFSET_5_0_K2_E5                     (0x3f<<0) // cdfe comparator4 offset values ovrride enable bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enables overriding tap2 offset bit[3] : enables overriding tap3 offset bit[4] : enables overriding tap4 offset bit[5] : enables overriding tap5 offset
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X333_QAHB_CDFE_CMP4_PRESET_OFFSET_5_0_K2_E5_SHIFT               0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG25_K2_E5                                               0x002d38UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG26_K2_E5                                               0x002d3cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG27_K2_E5                                               0x002d40UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG28_K2_E5                                               0x002d44UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X338_K2_E5                                                        0x002d48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X338_QAHB_CDFE_COARSE_DLL_ERR_AVG_NUM_6_0_K2_E5                 (0x7f<<0) // 
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X338_QAHB_CDFE_COARSE_DLL_ERR_AVG_NUM_6_0_K2_E5_SHIFT           0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X339_K2_E5                                                        0x002d4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X339_QAHB_CDFE_DLEV_ERR_AVG_NUM_6_0_K2_E5                       (0x7f<<0) // 
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X339_QAHB_CDFE_DLEV_ERR_AVG_NUM_6_0_K2_E5_SHIFT                 0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG29_K2_E5                                               0x002d50UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X341_K2_E5                                                        0x002d54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X341_QAHB_CDFE_COARSE_DLL_ERR_AVG_THRESHOLD_6_0_K2_E5           (0x7f<<0) // 
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X341_QAHB_CDFE_COARSE_DLL_ERR_AVG_THRESHOLD_6_0_K2_E5_SHIFT     0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X342_K2_E5                                                        0x002d58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X342_QAHB_CDFE_DLEV_ERR_AVG_THRESHOLD_K2_E5                     (0x7f<<0) // 
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X342_QAHB_CDFE_DLEV_ERR_AVG_THRESHOLD_K2_E5_SHIFT               0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG30_K2_E5                                               0x002d5cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X344_K2_E5                                                        0x002d60UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X344_QAHB_CDFE_DLL_COARSE_AVG_1_0_K2_E5                         (0x3<<0) // Level of averaging used during cdfe dll coarse calibration 0: last data,  1: avg of last two data,  2: avg of last four data,  3: last data
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X344_QAHB_CDFE_DLL_COARSE_AVG_1_0_K2_E5_SHIFT                   0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X344_QAHB_CDFE_DLL_FINE_AVG_K2_E5                               (0x3<<2) // Level of averaging used during cdfe dll fine calibration 0: last data,  1: avg of last two data,  2: avg of last four data,  3: last data
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X344_QAHB_CDFE_DLL_FINE_AVG_K2_E5_SHIFT                         2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X344_QAHB_CDFE_DLEV_AVG_K2_E5                                   (0x3<<4) // Level of averaging used during cdfe dlev calibration 0: last data,  1: avg of last two data,  2: avg of last four data,  3: last data
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X344_QAHB_CDFE_DLEV_AVG_K2_E5_SHIFT                             4
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG31_K2_E5                                               0x002d64UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X346_K2_E5                                                        0x002d68UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X346_QAHB_CDFE_DLL_FINE_OV_COARSE_EN_K2_E5                      (0x1<<0) // 
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X346_QAHB_CDFE_DLL_FINE_OV_COARSE_EN_K2_E5_SHIFT                0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X346_QAHB_CDFE_DLL_COARSE_OV_FINE_EN_K2_E5                      (0x1<<1) // 
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X346_QAHB_CDFE_DLL_COARSE_OV_FINE_EN_K2_E5_SHIFT                1
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X347_K2_E5                                                        0x002d6cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X347_QAHB_CDFE_DLEV_TRAINING_PATT_K2_E5                         (0x7f<<0) // cdfe dlev training pattern.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X347_QAHB_CDFE_DLEV_TRAINING_PATT_K2_E5_SHIFT                   0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X348_K2_E5                                                        0x002d70UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X348_QAHB_CDFE_TAP1_TRAINING_PATT_6_0_K2_E5                     (0x7f<<0) // cdfe tap1 training pattern.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X348_QAHB_CDFE_TAP1_TRAINING_PATT_6_0_K2_E5_SHIFT               0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X349_K2_E5                                                        0x002d74UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X349_QAHB_CDFE_TAP2_TRAINING_PATT_6_0_K2_E5                     (0x7f<<0) // cdfe tap2 training pattern.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X349_QAHB_CDFE_TAP2_TRAINING_PATT_6_0_K2_E5_SHIFT               0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X350_K2_E5                                                        0x002d78UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X350_QAHB_CDFE_TAP3_TRAINING_PATT_6_0_K2_E5                     (0x7f<<0) // cdfe tap3 training pattern.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X350_QAHB_CDFE_TAP3_TRAINING_PATT_6_0_K2_E5_SHIFT               0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X351_K2_E5                                                        0x002d7cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X351_QAHB_CDFE_TAP4_TRAINING_PATT_6_0_K2_E5                     (0x7f<<0) // cdfe tap4 training pattern.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X351_QAHB_CDFE_TAP4_TRAINING_PATT_6_0_K2_E5_SHIFT               0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X352_K2_E5                                                        0x002d80UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X352_QAHB_CDFE_TAP5_TRAINING_PATT_6_0_K2_E5                     (0x7f<<0) // cdfe tap5 training pattern.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X352_QAHB_CDFE_TAP5_TRAINING_PATT_6_0_K2_E5_SHIFT               0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X353_K2_E5                                                        0x002d84UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X353_QAHB_CDFE_DLL_COARSE_BOUNCE_K2_E5                          (0xf<<0) // Bounce number for cdfe dll coarse calibration
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X353_QAHB_CDFE_DLL_COARSE_BOUNCE_K2_E5_SHIFT                    0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X354_K2_E5                                                        0x002d88UL //Access:RW   DataWidth:0x8    // Bounce number for cdfe dll fine calibration
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X355_K2_E5                                                        0x002d8cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X355_QAHB_CDFE_DLEV_BOUNCE_K2_E5                                (0xf<<0) // Bounce number for cdfe dlev calibration
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X355_QAHB_CDFE_DLEV_BOUNCE_K2_E5_SHIFT                          0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG32_K2_E5                                               0x002d90UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG33_K2_E5                                               0x002d94UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X358_K2_E5                                                        0x002d98UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X358_QAHB_CDFE_DLL_COARSE_STEP_K2_E5                            (0xf<<0) // Calibration step size for cdfe dll coarse calibration
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X358_QAHB_CDFE_DLL_COARSE_STEP_K2_E5_SHIFT                      0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X358_QAHB_CDFE_DLEV_STEP_3_0_K2_E5                              (0xf<<4) // Calibration step size for cdfe dlev calibration
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X358_QAHB_CDFE_DLEV_STEP_3_0_K2_E5_SHIFT                        4
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG34_K2_E5                                               0x002d9cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG35_K2_E5                                               0x002da0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG36_K2_E5                                               0x002da4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X362_K2_E5                                                        0x002da8UL //Access:RW   DataWidth:0x8    // Maximum dlev value for cdfe
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X363_K2_E5                                                        0x002dacUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X363_QAHB_CDFE_TAP1_MAX_6_0_K2_E5                               (0x7f<<0) // Maximum tap1 value for cdfe
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X363_QAHB_CDFE_TAP1_MAX_6_0_K2_E5_SHIFT                         0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X364_K2_E5                                                        0x002db0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X364_QAHB_CDFE_TAP2_MAX_K2_E5                                   (0x3f<<0) // Maximum tap2 value for cdfe
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X364_QAHB_CDFE_TAP2_MAX_K2_E5_SHIFT                             0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X365_K2_E5                                                        0x002db4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X365_QAHB_CDFE_TAP3_MAX_5_0_K2_E5                               (0x3f<<0) // Maximum tap3 value for cdfe
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X365_QAHB_CDFE_TAP3_MAX_5_0_K2_E5_SHIFT                         0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X366_K2_E5                                                        0x002db8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X366_QAHB_CDFE_TAP4_MAX_5_0_K2_E5                               (0x3f<<0) // Maximum tap4 value for cdfe
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X366_QAHB_CDFE_TAP4_MAX_5_0_K2_E5_SHIFT                         0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X367_K2_E5                                                        0x002dbcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X367_QAHB_CDFE_TAP5_MAX_5_0_K2_E5                               (0x3f<<0) // Maximum tap5 value for cdfe
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X367_QAHB_CDFE_TAP5_MAX_5_0_K2_E5_SHIFT                         0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X367_QAHB_CDFE_CLR_BOUNCE_EN_K2_E5                              (0x1<<6) // 
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X367_QAHB_CDFE_CLR_BOUNCE_EN_K2_E5_SHIFT                        6
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X368_K2_E5                                                        0x002dc0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X368_QAHB_CDFE_RATE2_DFE_CMP_DATA_WAIT_K2_E5                    (0xf<<0) // 
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X368_QAHB_CDFE_RATE2_DFE_CMP_DATA_WAIT_K2_E5_SHIFT              0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X368_QAHB_CDFE_RATE3_DFE_CMP_DATA_WAIT_K2_E5                    (0xf<<4) // 
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X368_QAHB_CDFE_RATE3_DFE_CMP_DATA_WAIT_K2_E5_SHIFT              4
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X369_K2_E5                                                        0x002dc4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X369_QAHB_TAP1_CM1_DONT_CARE_O_K2_E5                            (0x3f<<1) // Mask bits for CM1 training pattern
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X369_QAHB_TAP1_CM1_DONT_CARE_O_K2_E5_SHIFT                      1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X369_QAHB_CDFE_SELECT_CLK90_CLK270_ONLY_O_K2_E5                 (0x1<<7) // 
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X369_QAHB_CDFE_SELECT_CLK90_CLK270_ONLY_O_K2_E5_SHIFT           7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X370_K2_E5                                                        0x002dc8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X370_QAHB_TAP1_C1_DONT_CARE_O_K2_E5                             (0x3f<<0) // Mask bits for C1 training pattern
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X370_QAHB_TAP1_C1_DONT_CARE_O_K2_E5_SHIFT                       0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X371_K2_E5                                                        0x002dccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X371_QAHB_CDFE_CMP_SEL_ENA_O_K2_E5                              (0xf<<0) // 
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X371_QAHB_CDFE_CMP_SEL_ENA_O_K2_E5_SHIFT                        0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X371_QAHB_CDFE_DFE_STROBE_CNT_O_K2_E5                           (0x7<<4) // 
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X371_QAHB_CDFE_DFE_STROBE_CNT_O_K2_E5_SHIFT                     4
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X372_K2_E5                                                        0x002dd0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X372_QAHB_CDFE_WAIT_TIMER_1_O_K2_E5                             (0x7<<0) // 
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X372_QAHB_CDFE_WAIT_TIMER_1_O_K2_E5_SHIFT                       0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X372_QAHB_CDFE_FINAL_CMP_WRITE_EN_O_K2_E5                       (0x1<<3) // 
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X372_QAHB_CDFE_FINAL_CMP_WRITE_EN_O_K2_E5_SHIFT                 3
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X373_K2_E5                                                        0x002dd4UL //Access:RW   DataWidth:0x8    // 
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG37_K2_E5                                               0x002dd8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG38_K2_E5                                               0x002ddcUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_K2_E5                                                        0x002de0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_IDDQ_SD_O_K2_E5                               (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_IDDQ_SD_O_K2_E5_SHIFT                         0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_DFE_O_K2_E5                                (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_DFE_O_K2_E5_SHIFT                          1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_DFE_BIAS_O_K2_E5                           (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_DFE_BIAS_O_K2_E5_SHIFT                     2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_LNREG_O_K2_E5                              (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_LNREG_O_K2_E5_SHIFT                        3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_LNREGH_O_K2_E5                             (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_LNREGH_O_K2_E5_SHIFT                       4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_P2S_O_K2_E5                                (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_P2S_O_K2_E5_SHIFT                          5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_RA_O_K2_E5                                 (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_RA_O_K2_E5_SHIFT                           6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_S2P_O_K2_E5                                (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_S2P_O_K2_E5_SHIFT                          7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_K2_E5                                                        0x002de4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_SLV_BIAS_O_K2_E5                           (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_SLV_BIAS_O_K2_E5_SHIFT                     0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_TXDRV_O_K2_E5                              (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_TXDRV_O_K2_E5_SHIFT                        1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_TXREG_O_K2_E5                              (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_TXREG_O_K2_E5_SHIFT                        2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_VCO_O_K2_E5                                (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_VCO_O_K2_E5_SHIFT                          3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_VCO_BUF_O_K2_E5                            (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_VCO_BUF_O_K2_E5_SHIFT                      4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_CDR_O_K2_E5                             (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_CDR_O_K2_E5_SHIFT                       5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_CDR_GCRX_O_K2_E5                        (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_CDR_GCRX_O_K2_E5_SHIFT                  6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_DFE_O_K2_E5                             (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_DFE_O_K2_E5_SHIFT                       7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_K2_E5                                                        0x002de8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_LNREG_O_K2_E5                           (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_LNREG_O_K2_E5_SHIFT                     0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_LNREGH_O_K2_E5                          (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_LNREGH_O_K2_E5_SHIFT                    1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_P2S_O_K2_E5                             (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_P2S_O_K2_E5_SHIFT                       2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_RA_O_K2_E5                              (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_RA_O_K2_E5_SHIFT                        3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_S2P_O_K2_E5                             (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_S2P_O_K2_E5_SHIFT                       4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_VCO_O_K2_E5                             (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_VCO_O_K2_E5_SHIFT                       5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_TXREG_BLEED_ENA_O_K2_E5                       (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_TXREG_BLEED_ENA_O_K2_E5_SHIFT                 6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_TX_LOWPWR_IDLE_ENA_O_K2_E5                    (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT              7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_K2_E5                                                        0x002decUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_CDR_EN_O_K2_E5                                (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_CDR_EN_O_K2_E5_SHIFT                          0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RXBCLK_EN_O_K2_E5                             (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RXBCLK_EN_O_K2_E5_SHIFT                       1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RX_GATE_EN_O_K2_E5                            (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RX_GATE_EN_O_K2_E5_SHIFT                      2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RESET_TX_CLKDIV_O_K2_E5                       (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RESET_TX_CLKDIV_O_K2_E5_SHIFT                 3
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_K2_E5                                                        0x002df0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_IDDQ_SD_O_K2_E5                                (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_IDDQ_SD_O_K2_E5_SHIFT                          0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_DFE_O_K2_E5                                 (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_DFE_O_K2_E5_SHIFT                           1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_DFE_BIAS_O_K2_E5                            (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_DFE_BIAS_O_K2_E5_SHIFT                      2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_LNREG_O_K2_E5                               (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_LNREG_O_K2_E5_SHIFT                         3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_LNREGH_O_K2_E5                              (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_LNREGH_O_K2_E5_SHIFT                        4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_P2S_O_K2_E5                                 (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_P2S_O_K2_E5_SHIFT                           5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_RA_O_K2_E5                                  (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_RA_O_K2_E5_SHIFT                            6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_S2P_O_K2_E5                                 (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_S2P_O_K2_E5_SHIFT                           7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_K2_E5                                                        0x002df4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_SLV_BIAS_O_K2_E5                            (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_SLV_BIAS_O_K2_E5_SHIFT                      0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_TXDRV_O_K2_E5                               (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_TXDRV_O_K2_E5_SHIFT                         1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_TXREG_O_K2_E5                               (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_TXREG_O_K2_E5_SHIFT                         2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_VCO_O_K2_E5                                 (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_VCO_O_K2_E5_SHIFT                           3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_VCO_BUF_O_K2_E5                             (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_VCO_BUF_O_K2_E5_SHIFT                       4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_CDR_O_K2_E5                              (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_CDR_O_K2_E5_SHIFT                        5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_CDR_GCRX_O_K2_E5                         (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_CDR_GCRX_O_K2_E5_SHIFT                   6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_DFE_O_K2_E5                              (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_DFE_O_K2_E5_SHIFT                        7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_K2_E5                                                        0x002df8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_LNREG_O_K2_E5                            (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_LNREG_O_K2_E5_SHIFT                      0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_LNREGH_O_K2_E5                           (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_LNREGH_O_K2_E5_SHIFT                     1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_P2S_O_K2_E5                              (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_P2S_O_K2_E5_SHIFT                        2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_RA_O_K2_E5                               (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_RA_O_K2_E5_SHIFT                         3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_S2P_O_K2_E5                              (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_S2P_O_K2_E5_SHIFT                        4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_VCO_O_K2_E5                              (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_VCO_O_K2_E5_SHIFT                        5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_TXREG_BLEED_ENA_O_K2_E5                        (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_TXREG_BLEED_ENA_O_K2_E5_SHIFT                  6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_TX_LOWPWR_IDLE_ENA_O_K2_E5                     (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT               7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_K2_E5                                                        0x002dfcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_CDR_EN_O_K2_E5                                 (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_CDR_EN_O_K2_E5_SHIFT                           0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RXBCLK_EN_O_K2_E5                              (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RXBCLK_EN_O_K2_E5_SHIFT                        1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RX_GATE_EN_O_K2_E5                             (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RX_GATE_EN_O_K2_E5_SHIFT                       2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RESET_TX_CLKDIV_O_K2_E5                        (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RESET_TX_CLKDIV_O_K2_E5_SHIFT                  3
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_K2_E5                                                        0x002e00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_IDDQ_SD_O_K2_E5                                (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_IDDQ_SD_O_K2_E5_SHIFT                          0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_DFE_O_K2_E5                                 (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_DFE_O_K2_E5_SHIFT                           1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_DFE_BIAS_O_K2_E5                            (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_DFE_BIAS_O_K2_E5_SHIFT                      2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_LNREG_O_K2_E5                               (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_LNREG_O_K2_E5_SHIFT                         3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_LNREGH_O_K2_E5                              (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_LNREGH_O_K2_E5_SHIFT                        4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_P2S_O_K2_E5                                 (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_P2S_O_K2_E5_SHIFT                           5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_RA_O_K2_E5                                  (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_RA_O_K2_E5_SHIFT                            6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_S2P_O_K2_E5                                 (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_S2P_O_K2_E5_SHIFT                           7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_K2_E5                                                        0x002e04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_SLV_BIAS_O_K2_E5                            (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_SLV_BIAS_O_K2_E5_SHIFT                      0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_TXDRV_O_K2_E5                               (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_TXDRV_O_K2_E5_SHIFT                         1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_TXREG_O_K2_E5                               (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_TXREG_O_K2_E5_SHIFT                         2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_VCO_O_K2_E5                                 (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_VCO_O_K2_E5_SHIFT                           3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_VCO_BUF_O_K2_E5                             (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_VCO_BUF_O_K2_E5_SHIFT                       4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_CDR_O_K2_E5                              (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_CDR_O_K2_E5_SHIFT                        5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_CDR_GCRX_O_K2_E5                         (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_CDR_GCRX_O_K2_E5_SHIFT                   6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_DFE_O_K2_E5                              (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_DFE_O_K2_E5_SHIFT                        7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_K2_E5                                                        0x002e08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_LNREG_O_K2_E5                            (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_LNREG_O_K2_E5_SHIFT                      0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_LNREGH_O_K2_E5                           (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_LNREGH_O_K2_E5_SHIFT                     1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_P2S_O_K2_E5                              (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_P2S_O_K2_E5_SHIFT                        2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_RA_O_K2_E5                               (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_RA_O_K2_E5_SHIFT                         3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_S2P_O_K2_E5                              (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_S2P_O_K2_E5_SHIFT                        4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_VCO_O_K2_E5                              (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_VCO_O_K2_E5_SHIFT                        5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_TXREG_BLEED_ENA_O_K2_E5                        (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_TXREG_BLEED_ENA_O_K2_E5_SHIFT                  6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_TX_LOWPWR_IDLE_ENA_O_K2_E5                     (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT               7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_K2_E5                                                        0x002e0cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_CDR_EN_O_K2_E5                                 (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_CDR_EN_O_K2_E5_SHIFT                           0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RXBCLK_EN_O_K2_E5                              (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RXBCLK_EN_O_K2_E5_SHIFT                        1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RX_GATE_EN_O_K2_E5                             (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RX_GATE_EN_O_K2_E5_SHIFT                       2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RESET_TX_CLKDIV_O_K2_E5                        (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RESET_TX_CLKDIV_O_K2_E5_SHIFT                  3
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_K2_E5                                                        0x002e10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_IDDQ_SD_O_K2_E5                                (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_IDDQ_SD_O_K2_E5_SHIFT                          0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_DFE_O_K2_E5                                 (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_DFE_O_K2_E5_SHIFT                           1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_DFE_BIAS_O_K2_E5                            (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_DFE_BIAS_O_K2_E5_SHIFT                      2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_LNREG_O_K2_E5                               (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_LNREG_O_K2_E5_SHIFT                         3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_LNREGH_O_K2_E5                              (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_LNREGH_O_K2_E5_SHIFT                        4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_P2S_O_K2_E5                                 (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_P2S_O_K2_E5_SHIFT                           5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_RA_O_K2_E5                                  (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_RA_O_K2_E5_SHIFT                            6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_S2P_O_K2_E5                                 (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_S2P_O_K2_E5_SHIFT                           7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_K2_E5                                                        0x002e14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_SLV_BIAS_O_K2_E5                            (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_SLV_BIAS_O_K2_E5_SHIFT                      0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_TXDRV_O_K2_E5                               (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_TXDRV_O_K2_E5_SHIFT                         1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_TXREG_O_K2_E5                               (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_TXREG_O_K2_E5_SHIFT                         2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_VCO_O_K2_E5                                 (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_VCO_O_K2_E5_SHIFT                           3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_VCO_BUF_O_K2_E5                             (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_VCO_BUF_O_K2_E5_SHIFT                       4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_CDR_O_K2_E5                              (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_CDR_O_K2_E5_SHIFT                        5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_CDR_GCRX_O_K2_E5                         (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_CDR_GCRX_O_K2_E5_SHIFT                   6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_DFE_O_K2_E5                              (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_DFE_O_K2_E5_SHIFT                        7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_K2_E5                                                        0x002e18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_LNREG_O_K2_E5                            (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_LNREG_O_K2_E5_SHIFT                      0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_LNREGH_O_K2_E5                           (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_LNREGH_O_K2_E5_SHIFT                     1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_P2S_O_K2_E5                              (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_P2S_O_K2_E5_SHIFT                        2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_RA_O_K2_E5                               (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_RA_O_K2_E5_SHIFT                         3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_S2P_O_K2_E5                              (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_S2P_O_K2_E5_SHIFT                        4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_VCO_O_K2_E5                              (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_VCO_O_K2_E5_SHIFT                        5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_TXREG_BLEED_ENA_O_K2_E5                        (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_TXREG_BLEED_ENA_O_K2_E5_SHIFT                  6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_TX_LOWPWR_IDLE_ENA_O_K2_E5                     (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT               7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_K2_E5                                                        0x002e1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_CDR_EN_O_K2_E5                                 (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_CDR_EN_O_K2_E5_SHIFT                           0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RXBCLK_EN_O_K2_E5                              (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RXBCLK_EN_O_K2_E5_SHIFT                        1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RX_GATE_EN_O_K2_E5                             (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RX_GATE_EN_O_K2_E5_SHIFT                       2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RESET_TX_CLKDIV_O_K2_E5                        (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RESET_TX_CLKDIV_O_K2_E5_SHIFT                  3
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X392_K2_E5                                                        0x002e20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X392_MSM_PROG_MULT_DELAY_IDDQ_RESET_1_4_0_K2_E5                 (0x1f<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X392_MSM_PROG_MULT_DELAY_IDDQ_RESET_1_4_0_K2_E5_SHIFT           0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG39_K2_E5                                               0x002e24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X394_K2_E5                                                        0x002e28UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X394_MSM_PROG_MULT_DELAY_IDDQ_RESET_2_4_0_K2_E5                 (0x1f<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X394_MSM_PROG_MULT_DELAY_IDDQ_RESET_2_4_0_K2_E5_SHIFT           0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_K2_E5                                                        0x002e44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_L0_MASTER_CDN_O_K2_E5                                      (0x1<<0) // Lane0 master reset
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_L0_MASTER_CDN_O_K2_E5_SHIFT                                0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_L1_MASTER_CDN_O_K2_E5                                      (0x1<<1) // Lane1 master reset
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_L1_MASTER_CDN_O_K2_E5_SHIFT                                1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_L2_MASTER_CDN_O_K2_E5                                      (0x1<<2) // Lane2 master reset
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_L2_MASTER_CDN_O_K2_E5_SHIFT                                2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_L3_MASTER_CDN_O_K2_E5                                      (0x1<<3) // Lane3 master reset
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_L3_MASTER_CDN_O_K2_E5_SHIFT                                3
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X402_K2_E5                                                        0x002e48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X402_FAST_SIM_O_K2_E5                                           (0x1<<0) // fast_sim_register
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X402_FAST_SIM_O_K2_E5_SHIFT                                     0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X403_K2_E5                                                        0x002e4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X403_TBUS_DFE_CMP_SEL_O_2_0_K2_E5                               (0x7<<0) // Selects which comparator offsets come out on tbus
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X403_TBUS_DFE_CMP_SEL_O_2_0_K2_E5_SHIFT                         0
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X406_K2_E5                                                        0x002e58UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X406_MODE_I_2_0_K2_E5                                           (0x7<<0) // 1000Base-KX Mode status for CPU
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X406_MODE_I_2_0_K2_E5_SHIFT                                     0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X406_CMU_OK_I_0_K2_E5                                           (0x1<<3) // CMU OK Status
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X406_CMU_OK_I_0_K2_E5_SHIFT                                     3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X406_CMU1_OK_I_1_K2_E5                                          (0x1<<4) // CMU1 OK Status
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X406_CMU1_OK_I_1_K2_E5_SHIFT                                    4
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_K2_E5                                                        0x002e5cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN0_SIG_LEVEL_VALID_I_0_K2_E5                              (0x1<<0) // Lane 0 Signal Detect Valid Status
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN0_SIG_LEVEL_VALID_I_0_K2_E5_SHIFT                        0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN1_SIG_LEVEL_VALID_I_1_K2_E5                              (0x1<<1) // Lane 1 Signal Detect Valid Status
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN1_SIG_LEVEL_VALID_I_1_K2_E5_SHIFT                        1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN2_SIG_LEVEL_VALID_I_2_K2_E5                              (0x1<<2) // Lane 2 Signal Detect Valid Status
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN2_SIG_LEVEL_VALID_I_2_K2_E5_SHIFT                        2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN3_SIG_LEVEL_VALID_I_3_K2_E5                              (0x1<<3) // Lane 3 Signal Detect Valid Status
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN3_SIG_LEVEL_VALID_I_3_K2_E5_SHIFT                        3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN0_OK_I_4_K2_E5                                           (0x1<<4) // Lane 0 OK Status
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN0_OK_I_4_K2_E5_SHIFT                                     4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN1_OK_I_5_K2_E5                                           (0x1<<5) // Lane 1 OK Status
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN1_OK_I_5_K2_E5_SHIFT                                     5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN2_OK_I_6_K2_E5                                           (0x1<<6) // Lane 2 OK Status
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN2_OK_I_6_K2_E5_SHIFT                                     6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN3_OK_I_7_K2_E5                                           (0x1<<7) // Lane 3 OK Status
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN3_OK_I_7_K2_E5_SHIFT                                     7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X408_K2_E5                                                        0x002e60UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X408_LN0_RX_LOCKED_I_1_0_K2_E5                                  (0x3<<0) // Lane 0 RX Locked status
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X408_LN0_RX_LOCKED_I_1_0_K2_E5_SHIFT                            0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X408_LN1_RX_LOCKED_I_3_2_K2_E5                                  (0x3<<2) // Lane 1 RX Locked Status
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X408_LN1_RX_LOCKED_I_3_2_K2_E5_SHIFT                            2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X408_LN2_RX_LOCKED_I_5_4_K2_E5                                  (0x3<<4) // Lane 2 RX Locked Status
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X408_LN2_RX_LOCKED_I_5_4_K2_E5_SHIFT                            4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X408_LN3_RX_LOCKED_I_7_6_K2_E5                                  (0x3<<6) // Lane 3 RX Locked Status
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X408_LN3_RX_LOCKED_I_7_6_K2_E5_SHIFT                            6
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X409_K2_E5                                                        0x002e64UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG40_K2_E5                                               0x002e70UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X446_K2_E5                                                        0x002ef8UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X447_K2_E5                                                        0x002efcUL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X448_K2_E5                                                        0x002f00UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X449_K2_E5                                                        0x002f04UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X450_K2_E5                                                        0x002f08UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X451_K2_E5                                                        0x002f0cUL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X452_K2_E5                                                        0x002f10UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X453_K2_E5                                                        0x002f14UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X454_K2_E5                                                        0x002f18UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X455_K2_E5                                                        0x002f1cUL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X456_K2_E5                                                        0x002f20UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X457_K2_E5                                                        0x002f24UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X458_K2_E5                                                        0x002f28UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X459_K2_E5                                                        0x002f2cUL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X460_K2_E5                                                        0x002f30UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X461_K2_E5                                                        0x002f34UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X462_K2_E5                                                        0x002f38UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X463_K2_E5                                                        0x002f3cUL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X464_K2_E5                                                        0x002f40UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X465_K2_E5                                                        0x002f44UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X466_K2_E5                                                        0x002f48UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X467_K2_E5                                                        0x002f4cUL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X468_K2_E5                                                        0x002f50UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X469_K2_E5                                                        0x002f54UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X470_K2_E5                                                        0x002f58UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X471_K2_E5                                                        0x002f5cUL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X472_K2_E5                                                        0x002f60UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X473_K2_E5                                                        0x002f64UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X474_K2_E5                                                        0x002f68UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X475_K2_E5                                                        0x002f6cUL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X476_K2_E5                                                        0x002f70UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X477_K2_E5                                                        0x002f74UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X478_K2_E5                                                        0x002f78UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X479_K2_E5                                                        0x002f7cUL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X480_K2_E5                                                        0x002f80UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X481_K2_E5                                                        0x002f84UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X482_K2_E5                                                        0x002f88UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_K2_E5                                                        0x002f8cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_PD_LNREGH_O_K2_E5                            (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_PD_LNREGH_O_K2_E5_SHIFT                      0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_PD_VCO_BUF_O_K2_E5                           (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_PD_VCO_BUF_O_K2_E5_SHIFT                     1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_CDR_GCRX_O_K2_E5                       (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_CDR_GCRX_O_K2_E5_SHIFT                 2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RX_GATE_EN_O_K2_E5                           (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RX_GATE_EN_O_K2_E5_SHIFT                     3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_LNREG_O_K2_E5                          (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_LNREG_O_K2_E5_SHIFT                    4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_P2S_O_K2_E5                            (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_P2S_O_K2_E5_SHIFT                      5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_S2P_O_K2_E5                            (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_S2P_O_K2_E5_SHIFT                      6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_CDR_O_K2_E5                            (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_CDR_O_K2_E5_SHIFT                      7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_K2_E5                                                        0x002f90UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_DFE_O_K2_E5                            (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_DFE_O_K2_E5_SHIFT                      0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_VCO_O_K2_E5                            (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_VCO_O_K2_E5_SHIFT                      1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_RA_O_K2_E5                             (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_RA_O_K2_E5_SHIFT                       2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_LNREGH_O_K2_E5                         (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_LNREGH_O_K2_E5_SHIFT                   3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_DFE_O_K2_E5                               (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_DFE_O_K2_E5_SHIFT                         4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_LNREG_O_K2_E5                             (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_LNREG_O_K2_E5_SHIFT                       5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_P2S_O_K2_E5                               (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_P2S_O_K2_E5_SHIFT                         6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_RA_O_K2_E5                                (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_RA_O_K2_E5_SHIFT                          7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_K2_E5                                                        0x002f94UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_S2P_O_K2_E5                               (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_S2P_O_K2_E5_SHIFT                         0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_SLV_BIAS_O_K2_E5                          (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_SLV_BIAS_O_K2_E5_SHIFT                    1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_TXDRV_O_K2_E5                             (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_TXDRV_O_K2_E5_SHIFT                       2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_VCO_O_K2_E5                               (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_VCO_O_K2_E5_SHIFT                         3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_DFE_BIAS_O_K2_E5                          (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_DFE_BIAS_O_K2_E5_SHIFT                    4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_IDDQ_SD_O_K2_E5                              (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_IDDQ_SD_O_K2_E5_SHIFT                        5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_CDR_EN_O_K2_E5                               (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_CDR_EN_O_K2_E5_SHIFT                         6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_RXBCLK_EN_O_K2_E5                            (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_RXBCLK_EN_O_K2_E5_SHIFT                      7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_K2_E5                                                        0x002f98UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_TX_LOWPWR_IDLE_ENA_O_K2_E5                   (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT             0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_TXREG_BLEED_ENA_O_K2_E5                      (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_TXREG_BLEED_ENA_O_K2_E5_SHIFT                1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_PD_TXREG_O_K2_E5                             (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_PD_TXREG_O_K2_E5_SHIFT                       2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_RESET_TX_CLKDIV_O_K2_E5                      (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_RESET_TX_CLKDIV_O_K2_E5_SHIFT                3
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_K2_E5                                                        0x002f9cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_PD_LNREGH_O_K2_E5                            (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_PD_LNREGH_O_K2_E5_SHIFT                      0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_PD_VCO_BUF_O_K2_E5                           (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_PD_VCO_BUF_O_K2_E5_SHIFT                     1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_GCRX_O_K2_E5                       (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_GCRX_O_K2_E5_SHIFT                 2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RX_GATE_EN_O_K2_E5                           (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RX_GATE_EN_O_K2_E5_SHIFT                     3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_LNREG_O_K2_E5                          (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_LNREG_O_K2_E5_SHIFT                    4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_P2S_O_K2_E5                            (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_P2S_O_K2_E5_SHIFT                      5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_S2P_O_K2_E5                            (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_S2P_O_K2_E5_SHIFT                      6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_O_K2_E5                            (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_O_K2_E5_SHIFT                      7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_K2_E5                                                        0x002fa0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_DFE_O_K2_E5                            (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_DFE_O_K2_E5_SHIFT                      0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_VCO_O_K2_E5                            (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_VCO_O_K2_E5_SHIFT                      1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_RA_O_K2_E5                             (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_RA_O_K2_E5_SHIFT                       2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_LNREGH_O_K2_E5                         (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_LNREGH_O_K2_E5_SHIFT                   3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_DFE_O_K2_E5                               (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_DFE_O_K2_E5_SHIFT                         4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_LNREG_O_K2_E5                             (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_LNREG_O_K2_E5_SHIFT                       5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_P2S_O_K2_E5                               (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_P2S_O_K2_E5_SHIFT                         6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_RA_O_K2_E5                                (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_RA_O_K2_E5_SHIFT                          7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_K2_E5                                                        0x002fa4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_S2P_O_K2_E5                               (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_S2P_O_K2_E5_SHIFT                         0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_SLV_BIAS_O_K2_E5                          (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_SLV_BIAS_O_K2_E5_SHIFT                    1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_TXDRV_O_K2_E5                             (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_TXDRV_O_K2_E5_SHIFT                       2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_VCO_O_K2_E5                               (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_VCO_O_K2_E5_SHIFT                         3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_DFE_BIAS_O_K2_E5                          (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_DFE_BIAS_O_K2_E5_SHIFT                    4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_IDDQ_SD_O_K2_E5                              (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_IDDQ_SD_O_K2_E5_SHIFT                        5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_CDR_EN_O_K2_E5                               (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_CDR_EN_O_K2_E5_SHIFT                         6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_RESET_TX_CLKDIV_O_K2_E5                      (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_RESET_TX_CLKDIV_O_K2_E5_SHIFT                7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_K2_E5                                                        0x002fa8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_RXBCLK_EN_O_K2_E5                            (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_RXBCLK_EN_O_K2_E5_SHIFT                      0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_TX_LOWPWR_IDLE_ENA_O_K2_E5                   (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT             1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_TXREG_BLEED_ENA_O_K2_E5                      (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_TXREG_BLEED_ENA_O_K2_E5_SHIFT                2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_PD_TXREG_O_K2_E5                             (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_PD_TXREG_O_K2_E5_SHIFT                       3
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_K2_E5                                                        0x002facUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_PD_LNREGH_O_K2_E5                            (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_PD_LNREGH_O_K2_E5_SHIFT                      0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_PD_VCO_BUF_O_K2_E5                           (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_PD_VCO_BUF_O_K2_E5_SHIFT                     1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_CDR_GCRX_O_K2_E5                       (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_CDR_GCRX_O_K2_E5_SHIFT                 2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RX_GATE_EN_O_K2_E5                           (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RX_GATE_EN_O_K2_E5_SHIFT                     3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_LNREG_O_K2_E5                          (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_LNREG_O_K2_E5_SHIFT                    4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_P2S_O_K2_E5                            (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_P2S_O_K2_E5_SHIFT                      5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_S2P_O_K2_E5                            (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_S2P_O_K2_E5_SHIFT                      6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_TX_CLKDIV_O_K2_E5                      (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_TX_CLKDIV_O_K2_E5_SHIFT                7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_K2_E5                                                        0x002fb0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_CDR_O_K2_E5                            (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_CDR_O_K2_E5_SHIFT                      0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_DFE_O_K2_E5                            (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_DFE_O_K2_E5_SHIFT                      1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_VCO_O_K2_E5                            (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_VCO_O_K2_E5_SHIFT                      2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_RA_O_K2_E5                             (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_RA_O_K2_E5_SHIFT                       3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_LNREGH_O_K2_E5                         (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_LNREGH_O_K2_E5_SHIFT                   4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_DFE_O_K2_E5                               (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_DFE_O_K2_E5_SHIFT                         5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_LNREG_O_K2_E5                             (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_LNREG_O_K2_E5_SHIFT                       6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_P2S_O_K2_E5                               (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_P2S_O_K2_E5_SHIFT                         7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_K2_E5                                                        0x002fb4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_RA_O_K2_E5                                (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_RA_O_K2_E5_SHIFT                          0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_S2P_O_K2_E5                               (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_S2P_O_K2_E5_SHIFT                         1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_SLV_BIAS_O_K2_E5                          (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_SLV_BIAS_O_K2_E5_SHIFT                    2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_TXDRV_O_K2_E5                             (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_TXDRV_O_K2_E5_SHIFT                       3
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_VCO_O_K2_E5                               (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_VCO_O_K2_E5_SHIFT                         4
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_DFE_BIAS_O_K2_E5                          (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_DFE_BIAS_O_K2_E5_SHIFT                    5
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_IDDQ_SD_O_K2_E5                              (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_IDDQ_SD_O_K2_E5_SHIFT                        6
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_CDR_EN_O_K2_E5                               (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_CDR_EN_O_K2_E5_SHIFT                         7
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_K2_E5                                                        0x002fb8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_RXBCLK_EN_O_K2_E5                            (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_RXBCLK_EN_O_K2_E5_SHIFT                      0
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_TX_LOWPWR_IDLE_ENA_O_K2_E5                   (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT             1
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_TXREG_BLEED_ENA_O_K2_E5                      (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_TXREG_BLEED_ENA_O_K2_E5_SHIFT                2
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_PD_TXREG_O_K2_E5                             (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_PD_TXREG_O_K2_E5_SHIFT                       3
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X495_K2_E5                                                        0x002fbcUL //Access:RW   DataWidth:0x8    // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X496_K2_E5                                                        0x002fc0UL //Access:RW   DataWidth:0x8    // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X497_K2_E5                                                        0x002fc4UL //Access:RW   DataWidth:0x8    // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X498_K2_E5                                                        0x002fc8UL //Access:RW   DataWidth:0x8    // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+#define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X499_K2_E5                                                        0x002fccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X499_PROG_MULT_REF_CLK_WAIT_O_K2_E5                             (0x7<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X499_PROG_MULT_REF_CLK_WAIT_O_K2_E5_SHIFT                       0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X0_K2_E5                                                             0x003000UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X0_SOC0_DIV_O_K2_E5                                                (0xf<<0) // Static divider control for SOC0 The only access to this divider. Not an override
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X0_SOC0_DIV_O_K2_E5_SHIFT                                          0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X0_SOC1_DIV_O_K2_E5                                                (0xf<<4) // Static divider control for SOC1 The only access to this divider. Not an override
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X0_SOC1_DIV_O_K2_E5_SHIFT                                          4
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X1_K2_E5                                                             0x003004UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X1_CK_SOC_DIV_OVR_O_2_0_K2_E5                                      (0x7<<0) // Override for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Enable [1:0] - Override for pins ck_soc_div_i [1:0]
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X1_CK_SOC_DIV_OVR_O_2_0_K2_E5_SHIFT                                0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X1_PMA_CM_REF_CLK_DIV_O_K2_E5                                      (0x3<<3) // Divider for pma_cm_ref_clk
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X1_PMA_CM_REF_CLK_DIV_O_K2_E5_SHIFT                                3
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X1_GCFSM_CLK_DIV_O_K2_E5                                           (0x3<<5) // Static divider control for CMU GCFSM clock The only access to this divider. Not an override 4d0:  No division  4d1:  /2 4d2:  /2 4d3:  /4:
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X1_GCFSM_CLK_DIV_O_K2_E5_SHIFT                                     5
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X1_BURNIN_REF_LIFE_CLK_SEL_O_K2_E5                                 (0x1<<7) // Reference clock select override value for burn_in mode. This override is enabled by primary input pin burn_in_i
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X1_BURNIN_REF_LIFE_CLK_SEL_O_K2_E5_SHIFT                           7
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X2_K2_E5                                                             0x003008UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X2_SSC_CLK_DIV_O_K2_E5                                             (0x7<<0) // Static divider control for the SSC block The only access to this divider. Not an override 4d0:  No division  4d1:  /2 4d2:  /4 4d3:  /8:
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X2_SSC_CLK_DIV_O_K2_E5_SHIFT                                       0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X2_CDR_REFCLK_SEL_O_2_0_K2_E5                                      (0x7<<3) // Selects one lane's recovered byte clock of all existing lanes, which goes to refclk buffer.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X2_CDR_REFCLK_SEL_O_2_0_K2_E5_SHIFT                                3
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X2_CDR_REFDIV_O_1_0_K2_E5                                          (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by 4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X2_CDR_REFDIV_O_1_0_K2_E5_SHIFT                                    6
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X3_K2_E5                                                             0x00300cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X3_AHB_PMA_CM_DIVNSEL_O_6_0_K2_E5                                  (0x7f<<0) // CMU N-divider setting
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X3_AHB_PMA_CM_DIVNSEL_O_6_0_K2_E5_SHIFT                            0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X4_K2_E5                                                             0x003010UL //Access:RW   DataWidth:0x8    // CMU FL LDHS count value
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X5_K2_E5                                                             0x003014UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X5_AHB_PMA_CM_FL_LDHS_O_9_8_K2_E5                                  (0x3<<0) // CMU FL LDHS count value
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X5_AHB_PMA_CM_FL_LDHS_O_9_8_K2_E5_SHIFT                            0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X5_AHB_PMA_CM_PLL_REFDIV2_ENA_O_K2_E5                              (0x1<<2) // CMU reference div2 enable
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X5_AHB_PMA_CM_PLL_REFDIV2_ENA_O_K2_E5_SHIFT                        2
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X5_AHB_PMA_CM_PREDIV4_ENA_O_K2_E5                                  (0x1<<3) // CMU FL prediv4 enable
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X5_AHB_PMA_CM_PREDIV4_ENA_O_K2_E5_SHIFT                            3
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X5_AHB_PMA_CM_REFCLK_DEGLITCH_DIS_O_K2_E5                          (0x1<<4) // Reference clock startup deglitch circuit disable
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X5_AHB_PMA_CM_REFCLK_DEGLITCH_DIS_O_K2_E5_SHIFT                    4
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X6_K2_E5                                                             0x003018UL //Access:RW   DataWidth:0x8    // CMU GCFSM Output Overrides for the following functions: [27] - active high, Override Enable [26]  - GCFSM Request flag [25:24] - GCFSM Function [23:0] - GCFSM Control Signal
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X7_K2_E5                                                             0x00301cUL //Access:RW   DataWidth:0x8    // CMU GCFSM Output Overrides for the following functions: [27] - active high, Override Enable [26]  - GCFSM Request flag [25:24] - GCFSM Function [23:0] - GCFSM Control Signal
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X8_K2_E5                                                             0x003020UL //Access:RW   DataWidth:0x8    // CMU GCFSM Output Overrides for the following functions: [27] - active high, Override Enable [26]  - GCFSM Request flag [25:24] - GCFSM Function [23:0] - GCFSM Control Signal
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X9_K2_E5                                                             0x003024UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X9_GCFSM_OVR_O_27_24_K2_E5                                         (0xf<<0) // CMU GCFSM Output Overrides for the following functions: [27] - active high, Override Enable [26]  - GCFSM Request flag [25:24] - GCFSM Function [23:0] - GCFSM Control Signal
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X9_GCFSM_OVR_O_27_24_K2_E5_SHIFT                                   0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X10_K2_E5                                                            0x003028UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 7-0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X11_K2_E5                                                            0x00302cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 15-8
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X12_K2_E5                                                            0x003030UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 23-16
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X13_K2_E5                                                            0x003034UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 31-24
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X14_K2_E5                                                            0x003038UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 39-32
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X15_K2_E5                                                            0x00303cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 47-40
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X16_K2_E5                                                            0x003040UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 55-48
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X17_K2_E5                                                            0x003044UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 63-56
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X18_K2_E5                                                            0x003048UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 71-64
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X19_K2_E5                                                            0x00304cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 79-72
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X20_K2_E5                                                            0x003050UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 87-80
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X21_K2_E5                                                            0x003054UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 95-88
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X22_K2_E5                                                            0x003058UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 103-96
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X23_K2_E5                                                            0x00305cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 111-104
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X24_K2_E5                                                            0x003060UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 119-112
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X25_K2_E5                                                            0x003064UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 127-120
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X26_K2_E5                                                            0x003068UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X26_GCFSM_CMU_OUT_OVR_EN_O_K2_E5                                   (0x1<<0) // GCFSM output override enable
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X26_GCFSM_CMU_OUT_OVR_EN_O_K2_E5_SHIFT                             0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X26_GCFSM_CMU_PMA_DATA_OVR_O_6_0_K2_E5                             (0x7f<<1) // GCFSM pma_data_o override
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X26_GCFSM_CMU_PMA_DATA_OVR_O_6_0_K2_E5_SHIFT                       1
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X27_K2_E5                                                            0x00306cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X27_GCFSM_CMU_PMA_DATA_OVR_O_11_7_K2_E5                            (0x1f<<0) // GCFSM pma_data_o override
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X27_GCFSM_CMU_PMA_DATA_OVR_O_11_7_K2_E5_SHIFT                      0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X27_GCFSM_CMU_PMA_LATCH_OVR_O_K2_E5                                (0x1<<5) // GCFSM pma_latch_o override
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X27_GCFSM_CMU_PMA_LATCH_OVR_O_K2_E5_SHIFT                          5
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X27_GCFSM_CMU_PMA_GO_OVR_O_K2_E5                                   (0x1<<6) // GCFSM pma_go_o override
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X27_GCFSM_CMU_PMA_GO_OVR_O_K2_E5_SHIFT                             6
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X27_GCFSM_CMU_PMA_READ_OVR_O_K2_E5                                 (0x1<<7) // GCFSM pma_read_o override
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X27_GCFSM_CMU_PMA_READ_OVR_O_K2_E5_SHIFT                           7
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X28_K2_E5                                                            0x003070UL //Access:RW   DataWidth:0x8    // GCFSM pma_cal_o override
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X29_K2_E5                                                            0x003074UL //Access:RW   DataWidth:0x8    // GCFSM pma_cal_o override
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X30_K2_E5                                                            0x003078UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X30_MSM_CMU_SOC_CLK_EN_OUT_OVR_O_K2_E5                             (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - SOC clock output enable
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X30_MSM_CMU_SOC_CLK_EN_OUT_OVR_O_K2_E5_SHIFT                       0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X30_MSM_CMU_REF_CLK_EN_OUT_OVR_O_K2_E5                             (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - REF clock output enable
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X30_MSM_CMU_REF_CLK_EN_OUT_OVR_O_K2_E5_SHIFT                       2
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X30_MSM_CMU_LOCK_EN_OUT_OVR_O_K2_E5                                (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - LOCK output enable
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X30_MSM_CMU_LOCK_EN_OUT_OVR_O_K2_E5_SHIFT                          4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X30_MSM_CMU_PMA_RST_CMU_OUT_OVR_O_K2_E5                            (0x3<<6) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X30_MSM_CMU_PMA_RST_CMU_OUT_OVR_O_K2_E5_SHIFT                      6
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X31_K2_E5                                                            0x00307cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X31_MSM_CMU_PMA_RST_CMUREG_OUT_OVR_O_K2_E5                         (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - SOC clock output enable - switches to SOC from life clock
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X31_MSM_CMU_PMA_RST_CMUREG_OUT_OVR_O_K2_E5_SHIFT                   0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X31_MSM_CMU_PMA_RST_CMUSYNTH_OUT_OVR_O_K2_E5                       (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU SYNTH
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X31_MSM_CMU_PMA_RST_CMUSYNTH_OUT_OVR_O_K2_E5_SHIFT                 2
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X31_MSM_CMU_PMA_RST_CMUVCO_OUT_OVR_O_K2_E5                         (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU VC0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X31_MSM_CMU_PMA_RST_CMUVCO_OUT_OVR_O_K2_E5_SHIFT                   4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X31_MSM_CMU_PMA_IDDQ_BIAS_OUT_OVR_O_K2_E5                          (0x3<<6) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - IDDQ BIAS
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X31_MSM_CMU_PMA_IDDQ_BIAS_OUT_OVR_O_K2_E5_SHIFT                    6
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X32_K2_E5                                                            0x003080UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X32_MSM_CMU_PMA_PD_BIAS_OUT_OVR_O_K2_E5                            (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD BIAS
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X32_MSM_CMU_PMA_PD_BIAS_OUT_OVR_O_K2_E5_SHIFT                      0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X32_MSM_CMU_PMA_PD_CMU_OUT_OVR_O_K2_E5                             (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD CMU
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X32_MSM_CMU_PMA_PD_CMU_OUT_OVR_O_K2_E5_SHIFT                       2
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X32_MSM_CMU_PMA_PD_CMUREG_OUT_OVR_O_K2_E5                          (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD CMU REG
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X32_MSM_CMU_PMA_PD_CMUREG_OUT_OVR_O_K2_E5_SHIFT                    4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X32_MSM_CMU_PMA_PD_REF_OUT_OVR_O_K2_E5                             (0x3<<6) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD REF OUT
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X32_MSM_CMU_PMA_PD_REF_OUT_OVR_O_K2_E5_SHIFT                       6
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X33_K2_E5                                                            0x003084UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X33_MSM_CMU_PMA_RESET_TXCLK_PCS_CLK_OVR_O_K2_E5                    (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PCS CLK ENA
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X33_MSM_CMU_PMA_RESET_TXCLK_PCS_CLK_OVR_O_K2_E5_SHIFT              0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X33_MSM_CMU_PMA_RST_CMU_FL_OUT_OVR_O_K2_E5                         (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU FL
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X33_MSM_CMU_PMA_RST_CMU_FL_OUT_OVR_O_K2_E5_SHIFT                   2
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X33_MSM_CMU_PMA_RST_CMU_GCRX_OUT_OVR_O_K2_E5                       (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU GCRX
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X33_MSM_CMU_PMA_RST_CMU_GCRX_OUT_OVR_O_K2_E5_SHIFT                 4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X33_MSM_PMA_LF_EXTZERO_ENA_OUT_OVR_O_K2_E5                         (0x3<<6) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - LF EXTZERO ENA
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X33_MSM_PMA_LF_EXTZERO_ENA_OUT_OVR_O_K2_E5_SHIFT                   6
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X34_K2_E5                                                            0x003088UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X34_MSM_CMU_PMA_LFI_EXTZERO_OUT_OVR_O_K2_E5                        (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - LFI EXTZERO ENA
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X34_MSM_CMU_PMA_LFI_EXTZERO_OUT_OVR_O_K2_E5_SHIFT                  0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X34_MSM_CMU_PMA_PD_CMUREGREF_OUT_OVR_O_K2_E5                       (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD CMU REGREF
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X34_MSM_CMU_PMA_PD_CMUREGREF_OUT_OVR_O_K2_E5_SHIFT                 2
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X34_MSM_PMA_RESET_CMUREGREF_OUT_OVR_O_K2_E5                        (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU REGREF
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X34_MSM_PMA_RESET_CMUREGREF_OUT_OVR_O_K2_E5_SHIFT                  4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X34_MSM_PMA_RESET_TXCLK_OVR_O_K2_E5                                (0x3<<6) // Override register for reset_txclk
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X34_MSM_PMA_RESET_TXCLK_OVR_O_K2_E5_SHIFT                          6
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X35_K2_E5                                                            0x00308cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X35_MSM_PMA_RESET_CLKDIV_OVR_O_K2_E5                               (0x3<<0) // Override register for reset_clkdiv_ovr
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X35_MSM_PMA_RESET_CLKDIV_OVR_O_K2_E5_SHIFT                         0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X35_MSM_PMA_PD_CLKDIV_OVR_O_K2_E5                                  (0x3<<2) // Override register for pd_clkdiv_ovr
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X35_MSM_PMA_PD_CLKDIV_OVR_O_K2_E5_SHIFT                            2
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X35_MSM_PMA_PD_CLKDIV_REFCLK_LEFT_OVR_O_K2_E5                      (0x3<<4) // Override register for pd_clkdiv_refclk_left_ovr
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X35_MSM_PMA_PD_CLKDIV_REFCLK_LEFT_OVR_O_K2_E5_SHIFT                4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X35_MSM_PMA_PD_CLKDIV_REFCLK_RIGHT_OVR_O_K2_E5                     (0x3<<6) // Override register for pd_clkdiv_refclk_right_ovr
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X35_MSM_PMA_PD_CLKDIV_REFCLK_RIGHT_OVR_O_K2_E5_SHIFT               6
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X56_K2_E5                                                            0x0030e0UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X57_K2_E5                                                            0x0030e4UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X58_K2_E5                                                            0x0030e8UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X59_K2_E5                                                            0x0030ecUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X60_K2_E5                                                            0x0030f0UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X61_K2_E5                                                            0x0030f4UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X62_K2_E5                                                            0x0030f8UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X63_K2_E5                                                            0x0030fcUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X64_K2_E5                                                            0x003100UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X65_K2_E5                                                            0x003104UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X66_K2_E5                                                            0x003108UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X67_K2_E5                                                            0x00310cUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X68_K2_E5                                                            0x003110UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X69_K2_E5                                                            0x003114UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X70_K2_E5                                                            0x003118UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X71_K2_E5                                                            0x00311cUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X72_K2_E5                                                            0x003120UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X73_K2_E5                                                            0x003124UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X74_K2_E5                                                            0x003128UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X75_K2_E5                                                            0x00312cUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X76_K2_E5                                                            0x003130UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X77_K2_E5                                                            0x003134UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X78_K2_E5                                                            0x003138UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X79_K2_E5                                                            0x00313cUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X80_K2_E5                                                            0x003140UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X81_K2_E5                                                            0x003144UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X82_K2_E5                                                            0x003148UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X83_K2_E5                                                            0x00314cUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X84_K2_E5                                                            0x003150UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X85_K2_E5                                                            0x003154UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X86_K2_E5                                                            0x003158UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X87_K2_E5                                                            0x00315cUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X88_K2_E5                                                            0x003160UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X89_K2_E5                                                            0x003164UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X90_K2_E5                                                            0x003168UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X91_K2_E5                                                            0x00316cUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X92_K2_E5                                                            0x003170UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X92_MSM_FUNC_DATA_O_289_288_K2_E5                                  (0x3<<0) // MSM Function Data Bus slice
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X92_MSM_FUNC_DATA_O_289_288_K2_E5_SHIFT                            0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X92_MSM_IN_OVR_O_5_0_K2_E5                                         (0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag override [3:0] - MFSM function override
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X92_MSM_IN_OVR_O_5_0_K2_E5_SHIFT                                   2
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X93_K2_E5                                                            0x003174UL //Access:RW   DataWidth:0x8    // Number of reference clock cycles to count after qsample is ok, before PLL is declared locked
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X94_K2_E5                                                            0x003178UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X94_PLL_CTRL_NUM_CYCLES_O_9_8_K2_E5                                (0x3<<0) // Number of reference clock cycles to count after qsample is ok, before PLL is declared locked
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X94_PLL_CTRL_NUM_CYCLES_O_9_8_K2_E5_SHIFT                          0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X94_PLL_CTRL_GOOD_STATE_O_K2_E5                                    (0x1<<2) // State of qsample for PLL to be considered locked
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X94_PLL_CTRL_GOOD_STATE_O_K2_E5_SHIFT                              2
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X94_PLL_CTRL_OVR_O_K2_E5                                           (0x7<<3) // Overrides for PLL lock signals [2] - Active high, override enable [1] - PLL ok override, bypasses ref clock cycle count after qsample is ok [0] - Qsample override
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X94_PLL_CTRL_OVR_O_K2_E5_SHIFT                                     3
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95_K2_E5                                                            0x00317cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95_AHB_PMA_CM_I_KVCO_SEL_O_K2_E5                                  (0x3<<0) // CMU VCO integral path gain
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95_AHB_PMA_CM_I_KVCO_SEL_O_K2_E5_SHIFT                            0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95_AHB_PMA_CM_FORCE_ILF_O_K2_E5                                   (0x3<<2) // CMU loop filter force to common mode
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95_AHB_PMA_CM_FORCE_ILF_O_K2_E5_SHIFT                             2
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95_AHB_PMA_CM_I_CP_SEL_O_K2_E5                                    (0x3<<4) // Charge pump current gain select.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95_AHB_PMA_CM_I_CP_SEL_O_K2_E5_SHIFT                              4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95_AHB_PMA_CM_I_HIZ_O_K2_E5                                       (0x1<<6) // CMU PLL HIZ setting
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95_AHB_PMA_CM_I_HIZ_O_K2_E5_SHIFT                                 6
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95_AHB_PMA_CM_C1_SEL_O_K2_E5                                      (0x1<<7) // CMU LF C1 cap select. Enabling increases C1 cap.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95_AHB_PMA_CM_C1_SEL_O_K2_E5_SHIFT                                7
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X96_K2_E5                                                            0x003180UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X96_AHB_PMA_CM_P_CAP_SEL_O_K2_E5                                   (0x7<<0) // CMU VCO proportional path cap select
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X96_AHB_PMA_CM_P_CAP_SEL_O_K2_E5_SHIFT                             0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X96_AHB_PMA_CM_CHPMP_CHOP_ENAN_O_K2_E5                             (0x1<<3) // Charge pump chop enable
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X96_AHB_PMA_CM_CHPMP_CHOP_ENAN_O_K2_E5_SHIFT                       3
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X96_AHB_PMA_CM_I_CAP_SEL_O_K2_E5                                   (0x7<<4) // CMU VCO integral path cap select
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X96_AHB_PMA_CM_I_CAP_SEL_O_K2_E5_SHIFT                             4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X96_AHB_PMA_CM_BGSTART_BYP_O_K2_E5                                 (0x1<<7) // Bandgap startup circuit bypass
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X96_AHB_PMA_CM_BGSTART_BYP_O_K2_E5_SHIFT                           7
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X97_K2_E5                                                            0x003184UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X97_AHB_PMA_CM_VCO_BIAS_O_K2_E5                                    (0xf<<0) // CMU VCO bias current setting.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X97_AHB_PMA_CM_VCO_BIAS_O_K2_E5_SHIFT                              0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X97_AHB_PMA_CM_VREG_O_K2_E5                                        (0x3<<4) // CMU VREG setting
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X97_AHB_PMA_CM_VREG_O_K2_E5_SHIFT                                  4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X97_AHB_PMA_CM_VREGH_O_K2_E5                                       (0x3<<6) // CMU VREGH setting
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X97_AHB_PMA_CM_VREGH_O_K2_E5_SHIFT                                 6
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_K2_E5                                                            0x003188UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_PFD_FORCE_DN_O_K2_E5                                (0x1<<0) // Force PFD to output down
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_PFD_FORCE_DN_O_K2_E5_SHIFT                          0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_PFD_FORCE_UP_O_K2_E5                                (0x1<<1) // Force PFD to output up
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_PFD_FORCE_UP_O_K2_E5_SHIFT                          1
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_SR_NDIV_OVR_ENA_O_K2_E5                                        (0x1<<2) // Override enable for overriding N-div value
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_SR_NDIV_OVR_ENA_O_K2_E5_SHIFT                                  2
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_V2I_FILTER_SW_ON_O_K2_E5                            (0x1<<3) // CMU V2I filter enable
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_V2I_FILTER_SW_ON_O_K2_E5_SHIFT                      3
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_O_K2_E5                      (0x1<<4) // CMU VCO PMOS proportional current increase
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_O_K2_E5_SHIFT                4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_LESS_EN_O_K2_E5                      (0x1<<5) // CMU VCO PMOS proportional current decrease
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_LESS_EN_O_K2_E5_SHIFT                5
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_VREGREF_O_K2_E5                                     (0x3<<6) // CMU reference clock regulator setting
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_VREGREF_O_K2_E5_SHIFT                               6
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X99_K2_E5                                                            0x00318cUL //Access:RW   DataWidth:0x8    // CMU AFE spares
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X100_K2_E5                                                           0x003190UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X100_AHB_PMA_CM_PFD_PW_O_K2_E5                                     (0x3<<0) // PFD pulse width setting
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X100_AHB_PMA_CM_PFD_PW_O_K2_E5_SHIFT                               0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X100_AHB_PMA_CM_I_DROPI_O_K2_E5                                    (0x1<<2) // Enable to reduce charge pump reference current
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X100_AHB_PMA_CM_I_DROPI_O_K2_E5_SHIFT                              2
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X100_AHB_PMA_CM_P_KVCO_SEL_O_K2_E5                                 (0x1f<<3) // CMU PLL KVCO setting
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X100_AHB_PMA_CM_P_KVCO_SEL_O_K2_E5_SHIFT                           3
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X101_K2_E5                                                           0x003194UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X101_AHB_PMA_CM_DIVPSEL_O_K2_E5                                    (0x7f<<0) // CMU P-divider setting
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X101_AHB_PMA_CM_DIVPSEL_O_K2_E5_SHIFT                              0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X102_K2_E5                                                           0x003198UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X102_AHB_PMA_CM_VCOFR_O_K2_E5                                      (0x7<<0) // AHB override for calibrated VCOFR value.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X102_AHB_PMA_CM_VCOFR_O_K2_E5_SHIFT                                0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X102_AHB_PMA_CM_VCOFR_SEL_O_K2_E5                                  (0x1<<3) // Override enable for overriding VCOFR value
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X102_AHB_PMA_CM_VCOFR_SEL_O_K2_E5_SHIFT                            3
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_RESERVEDREG8_K2_E5                                                   0x00319cUL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_RESERVEDREG9_K2_E5                                                   0x0031a0UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_RESERVEDREG10_K2_E5                                                  0x0031a4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_RESERVEDREG11_K2_E5                                                  0x0031a8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_RESERVEDREG12_K2_E5                                                  0x0031acUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X108_K2_E5                                                           0x0031b0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X108_PMA_REFCLK_OUTPUT_SEL_O_3_0_K2_E5                             (0xf<<3) // Reference clock output select
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X108_PMA_REFCLK_OUTPUT_SEL_O_3_0_K2_E5_SHIFT                       3
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X108_PMA_REFCLK_SEL_OVR_O_K2_E5                                    (0x1<<7) // Reference clock select override
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X108_PMA_REFCLK_SEL_OVR_O_K2_E5_SHIFT                              7
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_K2_E5                                                           0x0031b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_REFCLK_OE_L_O_K2_E5                                       (0x1<<0) // Override for primary IO: refclk_oe_l_i Enabled by pma_refclk_sel_ovr_o
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_REFCLK_OE_L_O_K2_E5_SHIFT                                 0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_REFCLK_OE_R_O_K2_E5                                       (0x1<<1) // "Override for primary IO: refclk_oe_r_i Enabled by pma_refclk_sel_ovr_o"
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_REFCLK_OE_R_O_K2_E5_SHIFT                                 1
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_RXCLK_OE_L_O_K2_E5                                        (0x1<<2) // "Override for primary IO: rxclk_oe_l_i Enabled by pma_refclk_sel_ovr_o"
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_RXCLK_OE_L_O_K2_E5_SHIFT                                  2
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_RXCLK_OE_R_O_K2_E5                                        (0x1<<3) // Override for primary IO: rxclk_oe_l_i Enabled by pma_refclk_sel_ovr_o
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_RXCLK_OE_R_O_K2_E5_SHIFT                                  3
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_CM_HV2P5SEL_O_K2_E5                                       (0x1<<4) // Enable additonal LF cap for 2.5V/3.3V process
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_CM_HV2P5SEL_O_K2_E5_SHIFT                                 4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_REFCLK_QFWD_L_O_K2_E5                                     (0x1<<6) // Override for primary IO: refclk_qfwd_l_i Enabled by pma_refclk_sel_ovr_o
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_REFCLK_QFWD_L_O_K2_E5_SHIFT                               6
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_REFCLK_QFWD_R_O_K2_E5                                     (0x1<<7) // Override for primary IO: refclk_qfwd_r_i Enabled by pma_refclk_sel_ovr_o
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_REFCLK_QFWD_R_O_K2_E5_SHIFT                               7
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X110_K2_E5                                                           0x0031b8UL //Access:RW   DataWidth:0x8    // Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X111_K2_E5                                                           0x0031bcUL //Access:RW   DataWidth:0x8    // Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X112_K2_E5                                                           0x0031c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X112_SSC_FCNTL_O_19_16_K2_E5                                       (0xf<<0) // Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X112_SSC_FCNTL_O_19_16_K2_E5_SHIFT                                 0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X112_SSC_GEN_EN_O_K2_E5                                            (0x1<<4) // Active high Enable for SSC generator SSC mode
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X112_SSC_GEN_EN_O_K2_E5_SHIFT                                      4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X112_SSC_EN_O_K2_E5                                                (0x1<<5) // Active high Enable for SSC block synth or SSC mode
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X112_SSC_EN_O_K2_E5_SHIFT                                          5
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X113_K2_E5                                                           0x0031c4UL //Access:RW   DataWidth:0x8    // SSC match value for Spread Spectrum Generation mode. Represents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X114_K2_E5                                                           0x0031c8UL //Access:RW   DataWidth:0x8    // SSC match value for Spread Spectrum Generation mode. Represents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X115_K2_E5                                                           0x0031ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X115_SSC_GEN_MATCH_VAL_O_19_16_K2_E5                               (0xf<<0) // SSC match value for Spread Spectrum Generation mode. Represents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X115_SSC_GEN_MATCH_VAL_O_19_16_K2_E5_SHIFT                         0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X115_SSC_GEN_FRACSYN_EN_O_K2_E5                                    (0x1<<4) // Enable for SSC generator with Fractional Synthesis
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X115_SSC_GEN_FRACSYN_EN_O_K2_E5_SHIFT                              4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X115_EN_FRACN_FRCDIV_MODE_O_K2_E5                                  (0x1<<5) // Enable fractional division mode and SSC mode
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X115_EN_FRACN_FRCDIV_MODE_O_K2_E5_SHIFT                            5
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X115_SSC_GEN_UPDOWN_EN_O_K2_E5                                     (0x1<<6) // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down spreading
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X115_SSC_GEN_UPDOWN_EN_O_K2_E5_SHIFT                               6
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X116_K2_E5                                                           0x0031d0UL //Access:RW   DataWidth:0x8    // In Spread Spectrum Generation mode, represents the magnitude of the incremental step in the SSC word
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X117_K2_E5                                                           0x0031d4UL //Access:RW   DataWidth:0x8    // In Spread Spectrum Generation mode, represents the magnitude of the incremental step in the SSC word
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X118_K2_E5                                                           0x0031d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X118_FRACN_MOD_TST_IN_O_K2_E5                                      (0xf<<0) // Test input bus
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X118_FRACN_MOD_TST_IN_O_K2_E5_SHIFT                                0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X118_FRACN_MOD_TST_CTRL_O_K2_E5                                    (0x3<<4) // Test i/p control source :  0-modulator  1-bypass modulator  2-modulator  3-sr_txt_in_i
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X118_FRACN_MOD_TST_CTRL_O_K2_E5_SHIFT                              4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X118_FRACN_FBK_CLK_SRC_SEL_O_K2_E5                                 (0x1<<6) // Clock Select for High Speed clock source :  0-clk_hs_fbk  1-clk_hs_refout
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X118_FRACN_FBK_CLK_SRC_SEL_O_K2_E5_SHIFT                           6
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X118_FRACN_FBK_CLK_DIV_SEL_O_K2_E5                                 (0x1<<7) // Clock divider for High Speed clock source
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X118_FRACN_FBK_CLK_DIV_SEL_O_K2_E5_SHIFT                           7
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X119_K2_E5                                                           0x0031dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X119_AHB_CMU_TEMP_CAL_OVR_O_4_0_K2_E5                              (0x1f<<0) // override for the counter value
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X119_AHB_CMU_TEMP_CAL_OVR_O_4_0_K2_E5_SHIFT                        0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X119_AHB_CMU_TEMP_CAL_POLL_EN_O_K2_E5                              (0x1<<5) // CMU Temperature Calibration Polling Enable: enables the periodic polling and counter adjustment
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X119_AHB_CMU_TEMP_CAL_POLL_EN_O_K2_E5_SHIFT                        5
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X119_AHB_CMU_TEMP_CAL_POLARITY_O_K2_E5                             (0x1<<6) // chicken bit for counter polarity
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X119_AHB_CMU_TEMP_CAL_POLARITY_O_K2_E5_SHIFT                       6
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X119_AHB_CMU_TEMP_CAL_OVR_EN_O_K2_E5                               (0x1<<7) // override enable to use above value
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X119_AHB_CMU_TEMP_CAL_OVR_EN_O_K2_E5_SHIFT                         7
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X120_K2_E5                                                           0x0031e0UL //Access:RW   DataWidth:0x8    // Divider input for Div-by-N counter
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X121_K2_E5                                                           0x0031e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X121_AHB_CMU_TEMP_CAL_CLK_DIV_O_14_8_K2_E5                         (0x7f<<0) // Divider input for Div-by-N counter
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X121_AHB_CMU_TEMP_CAL_CLK_DIV_O_14_8_K2_E5_SHIFT                   0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X122_K2_E5                                                           0x0031e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X122_PMA_CM_REFCLK_TERM_OVR_O_K2_E5                                (0x1f<<0) // Refclk Termination override value
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X122_PMA_CM_REFCLK_TERM_OVR_O_K2_E5_SHIFT                          0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X122_PMA_CM_REFCLK_TERM_OVR_EN_O_K2_E5                             (0x1<<5) // Refclk Termination override enable
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X122_PMA_CM_REFCLK_TERM_OVR_EN_O_K2_E5_SHIFT                       5
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X123_K2_E5                                                           0x0031ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X123_PMA_CM_RX_TERM_OVR_O_K2_E5                                    (0x1f<<0) // Rx Termination override value, every rx lane gets the same value
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X123_PMA_CM_RX_TERM_OVR_O_K2_E5_SHIFT                              0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X123_PMA_CM_RX_TERM_OVR_EN_O_K2_E5                                 (0x1<<5) // Rx Termination override enable
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X123_PMA_CM_RX_TERM_OVR_EN_O_K2_E5_SHIFT                           5
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X124_K2_E5                                                           0x0031f0UL //Access:RW   DataWidth:0x8    // In txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X125_K2_E5                                                           0x0031f4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X125_AHB_RX_TC_WAIT_NEXT_UP_8_K2_E5                                (0x1<<0) // In txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X125_AHB_RX_TC_WAIT_NEXT_UP_8_K2_E5_SHIFT                          0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X125_AHB_RX_TC_WAIT_NEXT_SAMPLE_K2_E5                              (0x7<<1) // in txterm calibration, the number refclk cycles to wait before sampling the up from the same comparator
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X125_AHB_RX_TC_WAIT_NEXT_SAMPLE_K2_E5_SHIFT                        1
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X125_AHB_RX_TC_UP_NUM_SAMPLES_K2_E5                                (0xf<<4) // in txterm calibration, the number of samples to take from the same comparator
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X125_AHB_RX_TC_UP_NUM_SAMPLES_K2_E5_SHIFT                          4
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X126_K2_E5                                                           0x0031f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X126_AHB_GC_TCCAL_ENA_OVR_K2_E5                                    (0x1<<0) // Debug feature, when set forces circuit RX termination calibration circuit to be enabled allowing ahb_tx_tc_bias_ovr to take effect
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X126_AHB_GC_TCCAL_ENA_OVR_K2_E5_SHIFT                              0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X126_AHB_RX_TC_BIAS_OVR_K2_E5                                      (0x7<<1) // Bit 3:1 RX termination calibration DAC override setting
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X126_AHB_RX_TC_BIAS_OVR_K2_E5_SHIFT                                1
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X127_K2_E5                                                           0x0031fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X127_CMU_MASTER_CDN_O_K2_E5                                        (0x1<<0) // Master reset for CMU
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X127_CMU_MASTER_CDN_O_K2_E5_SHIFT                                  0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X127_PCS_RATE_O_K2_E5                                              (0x3<<1) // Determines rate for PLL clock pcs_rate_o[0] :      0: VCO clock untouched      1: VCO clock divided by 2                                                 pcs_rate_o[1] :      0: PMA operates in 10b/20b mode Enables %5 circuit      1: PMA operates in 8b/16b mode   Enables %4 circuit
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X127_PCS_RATE_O_K2_E5_SHIFT                                        1
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X128_K2_E5                                                           0x003200UL //Access:RW   DataWidth:0x8    // Not used
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X129_K2_E5                                                           0x003204UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X129_CMU_IN_OVR_O_3_0_K2_E5                                        (0xf<<0) // Override for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pin IO [0] - CMU Reset Pin IO
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X129_CMU_IN_OVR_O_3_0_K2_E5_SHIFT                                  0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X129_CMU_OUT_OVR_O_1_0_K2_E5                                       (0x3<<4) // Override for Reset_smu_fl
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X129_CMU_OUT_OVR_O_1_0_K2_E5_SHIFT                                 4
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X130_K2_E5                                                           0x003208UL //Access:R    DataWidth:0x8    // Snapshot of digital test bus data [7:0]
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X131_K2_E5                                                           0x00320cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X131_TBUS_DATA_SMPL_11_8_K2_E5                                     (0xf<<0) // Snapshot of digital test bus data [11:8]
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X131_TBUS_DATA_SMPL_11_8_K2_E5_SHIFT                               0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X132_K2_E5                                                           0x003210UL //Access:RW   DataWidth:0x8    // CMU Test Bus address 7-0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X133_K2_E5                                                           0x003214UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X133_TBUS_ADDR_OVR_O_10_8_K2_E5                                    (0x7<<0) // CMU Test Bus address 10-8
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X133_TBUS_ADDR_OVR_O_10_8_K2_E5_SHIFT                              0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X134_K2_E5                                                           0x003218UL //Access:RW   DataWidth:0x8    // Not used
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X144_K2_E5                                                           0x003240UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X146_K2_E5                                                           0x003248UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X147_K2_E5                                                           0x00324cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X147_AHB_CMU_PROG_MULT_REF_CLK_WAIT_O_K2_E5                        (0x7<<0) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X147_AHB_CMU_PROG_MULT_REF_CLK_WAIT_O_K2_E5_SHIFT                  0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_RESERVEDREG13_K2_E5                                                  0x003250UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X149_K2_E5                                                           0x003254UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X149_AHB_PMA_CM_EN_REGLN_O_K2_E5                                   (0xf<<0) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X149_AHB_PMA_CM_EN_REGLN_O_K2_E5_SHIFT                             0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X153_K2_E5                                                           0x003264UL //Access:RW   DataWidth:0x8    // Inverts up_i when set to 1
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X154_K2_E5                                                           0x003268UL //Access:RW   DataWidth:0x8    // Inverts up_i when set to 1
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X161_K2_E5                                                           0x003284UL //Access:RW   DataWidth:0x8    // Function info for each MSM function. Varies depending on function number. _13:06 - Address of first command to run _05:00 - Number of commands to run
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X162_K2_E5                                                           0x003288UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X163_K2_E5                                                           0x00328cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X164_K2_E5                                                           0x003290UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X165_K2_E5                                                           0x003294UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X166_K2_E5                                                           0x003298UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X167_K2_E5                                                           0x00329cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X168_K2_E5                                                           0x0032a0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X169_K2_E5                                                           0x0032a4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X170_K2_E5                                                           0x0032a8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X171_K2_E5                                                           0x0032acUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X172_K2_E5                                                           0x0032b0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X173_K2_E5                                                           0x0032b4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X174_K2_E5                                                           0x0032b8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X175_K2_E5                                                           0x0032bcUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X176_K2_E5                                                           0x0032c0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X177_K2_E5                                                           0x0032c4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X178_K2_E5                                                           0x0032c8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X179_K2_E5                                                           0x0032ccUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X180_K2_E5                                                           0x0032d0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X181_K2_E5                                                           0x0032d4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X182_K2_E5                                                           0x0032d8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X183_K2_E5                                                           0x0032dcUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X184_K2_E5                                                           0x0032e0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X185_K2_E5                                                           0x0032e4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X186_K2_E5                                                           0x0032e8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X187_K2_E5                                                           0x0032ecUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X188_K2_E5                                                           0x0032f0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_RESERVEDREG14_K2_E5                                                  0x0032f4UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_RESERVEDREG15_K2_E5                                                  0x0032f8UL //Access:RW   DataWidth:0x8    // Reserved
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_K2_E5                                                           0x0032fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_IDDQ_BIAS_IDDQ_SETVAL_O_K2_E5                                 (0x1<<0) // MSM Function IDDQ mode default value for iddq_bias
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_IDDQ_BIAS_IDDQ_SETVAL_O_K2_E5_SHIFT                           0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_BIAS_IDDQ_SETVAL_O_K2_E5                                   (0x1<<1) // MSM Function IDDQ mode default value for pd_bias
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_BIAS_IDDQ_SETVAL_O_K2_E5_SHIFT                             1
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_RESET_TXCLK_PCS_CLK_IDDQ_SETVAL_O_K2_E5                       (0x1<<2) // MSM Function IDDQ mode default value for pcs_clk_ena
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_RESET_TXCLK_PCS_CLK_IDDQ_SETVAL_O_K2_E5_SHIFT                 2
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_CMU_IDDQ_SETVAL_O_K2_E5                                    (0x1<<3) // MSM Function IDDQ mode default value for pd_cmu
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_CMU_IDDQ_SETVAL_O_K2_E5_SHIFT                              3
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_CMUREG_IDDQ_SETVAL_O_K2_E5                                 (0x1<<4) // MSM Function IDDQ mode default value for pd_cmureg
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_CMUREG_IDDQ_SETVAL_O_K2_E5_SHIFT                           4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_CMUREGREF_IDDQ_SETVAL_O_K2_E5                              (0x1<<5) // MSM Function IDDQ mode default value for pd_cmuregref
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_CMUREGREF_IDDQ_SETVAL_O_K2_E5_SHIFT                        5
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_REF_IDDQ_SETVAL_O_K2_E5                                    (0x1<<6) // MSM Function IDDQ mode default value for pd_ref
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_REF_IDDQ_SETVAL_O_K2_E5_SHIFT                              6
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_RESET_CMU_FL_IDDQ_SETVAL_O_K2_E5                              (0x1<<7) // MSM Function IDDQ mode default value for reset_cmu_fl
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_RESET_CMU_FL_IDDQ_SETVAL_O_K2_E5_SHIFT                        7
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_K2_E5                                                           0x003300UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMU_IDDQ_SETVAL_O_K2_E5                                 (0x1<<0) // MSM Function IDDQ mode default value for reset_cmu
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMU_IDDQ_SETVAL_O_K2_E5_SHIFT                           0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMU_GCRX_IDDQ_SETVAL_O_K2_E5                            (0x1<<1) // MSM Function IDDQ mode default value for reset_cmu_gcrx
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMU_GCRX_IDDQ_SETVAL_O_K2_E5_SHIFT                      1
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMUREG_IDDQ_SETVAL_O_K2_E5                              (0x1<<2) // MSM Function IDDQ mode default value for reset_cmureg
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMUREG_IDDQ_SETVAL_O_K2_E5_SHIFT                        2
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMUREGREF_IDDQ_SETVAL_O_K2_E5                           (0x1<<3) // MSM Function IDDQ mode default value for reset_cmuregref
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMUREGREF_IDDQ_SETVAL_O_K2_E5_SHIFT                     3
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMUSYNTH_IDDQ_SETVAL_O_K2_E5                            (0x1<<4) // MSM Function IDDQ mode default value for reset_cmusynth
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMUSYNTH_IDDQ_SETVAL_O_K2_E5_SHIFT                      4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMUVCO_IDDQ_SETVAL_O_K2_E5                              (0x1<<5) // MSM Function IDDQ mode default value for reset_cmuvco
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMUVCO_IDDQ_SETVAL_O_K2_E5_SHIFT                        5
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_LF_EXTZERO_ENA_IDDQ_SETVAL_O_K2_E5                            (0x1<<6) // MSM Function IDDQ mode default value for lf_extzero_ena
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_LF_EXTZERO_ENA_IDDQ_SETVAL_O_K2_E5_SHIFT                      6
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_LFI_EXTZERO_IDDQ_SETVAL_O_K2_E5                               (0x1<<7) // MSM Function IDDQ mode default value for lfi_extzero
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_LFI_EXTZERO_IDDQ_SETVAL_O_K2_E5_SHIFT                         7
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_K2_E5                                                           0x003304UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_SOC_CLK_EN_IDDQ_SETVAL_O_K2_E5                                (0x1<<0) // MSM Function IDDQ mode default value for soc_clk_en
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_SOC_CLK_EN_IDDQ_SETVAL_O_K2_E5_SHIFT                          0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_REFCLK_EN_IDDQ_SETVAL_O_K2_E5                                 (0x1<<1) // MSM Function IDDQ mode default value for refclk_en
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_REFCLK_EN_IDDQ_SETVAL_O_K2_E5_SHIFT                           1
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_PLL_LOCK_EN_IDDQ_SETVAL_O_K2_E5                               (0x1<<2) // MSM Function IDDQ mode default value for pll_lock_en
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_PLL_LOCK_EN_IDDQ_SETVAL_O_K2_E5_SHIFT                         2
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_RESET_TXCLK_IDDQ_SETVAL_O_K2_E5                               (0x1<<3) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_RESET_TXCLK_IDDQ_SETVAL_O_K2_E5_SHIFT                         3
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_RESET_CLKDIV_IDDQ_SETVAL_O_K2_E5                              (0x1<<4) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_RESET_CLKDIV_IDDQ_SETVAL_O_K2_E5_SHIFT                        4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_PD_CLKDIV_IDDQ_SETVAL_O_K2_E5                                 (0x1<<5) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_PD_CLKDIV_IDDQ_SETVAL_O_K2_E5_SHIFT                           5
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_PD_CLKDIV_REFCLK_LEFT_IDDQ_SETVAL_O_K2_E5                     (0x1<<6) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_PD_CLKDIV_REFCLK_LEFT_IDDQ_SETVAL_O_K2_E5_SHIFT               6
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_PD_CLKDIV_REFCLK_RIGHT_IDDQ_SETVAL_O_K2_E5                    (0x1<<7) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_PD_CLKDIV_REFCLK_RIGHT_IDDQ_SETVAL_O_K2_E5_SHIFT              7
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_K2_E5                                                           0x003308UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_IDDQ_BIAS_RST_SETVAL_O_K2_E5                                  (0x1<<0) // MSM Function RST mode default value for iddq_bias
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_IDDQ_BIAS_RST_SETVAL_O_K2_E5_SHIFT                            0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_BIAS_RST_SETVAL_O_K2_E5                                    (0x1<<1) // MSM Function RST mode default value for pd_bias
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_BIAS_RST_SETVAL_O_K2_E5_SHIFT                              1
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_RESET_TXCLK_PCS_CLK_RST_SETVAL_O_K2_E5                        (0x1<<2) // MSM Function RST mode default value for pcs_clk_ena
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_RESET_TXCLK_PCS_CLK_RST_SETVAL_O_K2_E5_SHIFT                  2
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_CMU_RST_SETVAL_O_K2_E5                                     (0x1<<3) // MSM Function RST mode default value for pd_cmu
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_CMU_RST_SETVAL_O_K2_E5_SHIFT                               3
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_CMUREG_RST_SETVAL_O_K2_E5                                  (0x1<<4) // MSM Function RST mode default value for pd_cmureg
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_CMUREG_RST_SETVAL_O_K2_E5_SHIFT                            4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_CMUREGREF_RST_SETVAL_O_K2_E5                               (0x1<<5) // MSM Function RST mode default value for pd_cmuregref
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_CMUREGREF_RST_SETVAL_O_K2_E5_SHIFT                         5
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_REF_RST_SETVAL_O_K2_E5                                     (0x1<<6) // MSM Function RST mode default value for pd_ref
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_REF_RST_SETVAL_O_K2_E5_SHIFT                               6
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_RESET_CMU_FL_RST_SETVAL_O_K2_E5                               (0x1<<7) // MSM Function RST mode default value for reset_cmu_fl
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_RESET_CMU_FL_RST_SETVAL_O_K2_E5_SHIFT                         7
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_K2_E5                                                           0x00330cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMU_RST_SETVAL_O_K2_E5                                  (0x1<<0) // MSM Function RST mode default value for reset_cmu
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMU_RST_SETVAL_O_K2_E5_SHIFT                            0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMU_GCRX_RST_SETVAL_O_K2_E5                             (0x1<<1) // MSM Function RST mode default value for reset_cmu_gcrx
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMU_GCRX_RST_SETVAL_O_K2_E5_SHIFT                       1
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMUREG_RST_SETVAL_O_K2_E5                               (0x1<<2) // MSM Function RST mode default value for reset_cmureg
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMUREG_RST_SETVAL_O_K2_E5_SHIFT                         2
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMUREGREF_RST_SETVAL_O_K2_E5                            (0x1<<3) // MSM Function RST mode default value for reset_cmuregref
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMUREGREF_RST_SETVAL_O_K2_E5_SHIFT                      3
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMUSYNTH_RST_SETVAL_O_K2_E5                             (0x1<<4) // MSM Function RST mode default value for reset_cmusynth
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMUSYNTH_RST_SETVAL_O_K2_E5_SHIFT                       4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMUVCO_RST_SETVAL_O_K2_E5                               (0x1<<5) // MSM Function RST mode default value for reset_cmuvco
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMUVCO_RST_SETVAL_O_K2_E5_SHIFT                         5
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_LF_EXTZERO_ENA_RST_SETVAL_O_K2_E5                             (0x1<<6) // MSM Function RST mode default value for lf_extzero_ena
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_LF_EXTZERO_ENA_RST_SETVAL_O_K2_E5_SHIFT                       6
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_LFI_EXTZERO_RST_SETVAL_O_K2_E5                                (0x1<<7) // MSM Function RST mode default value for lfi_extzero
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_LFI_EXTZERO_RST_SETVAL_O_K2_E5_SHIFT                          7
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_K2_E5                                                           0x003310UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_SOC_CLK_EN_RST_SETVAL_O_K2_E5                                 (0x1<<0) // MSM Function RST mode default value for soc_clk_en
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_SOC_CLK_EN_RST_SETVAL_O_K2_E5_SHIFT                           0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_REFCLK_EN_RST_SETVAL_O_K2_E5                                  (0x1<<1) // MSM Function RST mode default value for refclk_en
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_REFCLK_EN_RST_SETVAL_O_K2_E5_SHIFT                            1
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_PLL_LOCK_EN_RST_SETVAL_O_K2_E5                                (0x1<<2) // MSM Function RST mode default value for pll_lock_en
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_PLL_LOCK_EN_RST_SETVAL_O_K2_E5_SHIFT                          2
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_RESET_TXCLK_RST_SETVAL_O_K2_E5                                (0x1<<3) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_RESET_TXCLK_RST_SETVAL_O_K2_E5_SHIFT                          3
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_RESET_CLKDIV_RST_SETVAL_O_K2_E5                               (0x1<<4) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_RESET_CLKDIV_RST_SETVAL_O_K2_E5_SHIFT                         4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_PD_CLKDIV_RST_SETVAL_O_K2_E5                                  (0x1<<5) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_PD_CLKDIV_RST_SETVAL_O_K2_E5_SHIFT                            5
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_PD_CLKDIV_REFCLK_LEFT_RST_SETVAL_O_K2_E5                      (0x1<<6) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_PD_CLKDIV_REFCLK_LEFT_RST_SETVAL_O_K2_E5_SHIFT                6
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_PD_CLKDIV_REFCLK_RIGHT_RST_SETVAL_O_K2_E5                     (0x1<<7) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_PD_CLKDIV_REFCLK_RIGHT_RST_SETVAL_O_K2_E5_SHIFT               7
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_K2_E5                                                           0x003314UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_IDDQ_BIAS_NORM_SETVAL_O_K2_E5                                 (0x1<<0) // MSM Function NORMAL mode default value for iddq_bias
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_IDDQ_BIAS_NORM_SETVAL_O_K2_E5_SHIFT                           0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_BIAS_NORM_SETVAL_O_K2_E5                                   (0x1<<1) // MSM Function NORMAL mode default value for pd_bias
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_BIAS_NORM_SETVAL_O_K2_E5_SHIFT                             1
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_RESET_TXCLK_PCS_CLK_NORM_SETVAL_O_K2_E5                       (0x1<<2) // MSM Function NORMAL mode default value for pcs_clk_ena
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_RESET_TXCLK_PCS_CLK_NORM_SETVAL_O_K2_E5_SHIFT                 2
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_CMU_NORM_SETVAL_O_K2_E5                                    (0x1<<3) // MSM Function NORMAL mode default value for pd_cmu
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_CMU_NORM_SETVAL_O_K2_E5_SHIFT                              3
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_CMUREG_NORM_SETVAL_O_K2_E5                                 (0x1<<4) // MSM Function NORMAL mode default value for pd_cmureg
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_CMUREG_NORM_SETVAL_O_K2_E5_SHIFT                           4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_CMUREGREF_NORM_SETVAL_O_K2_E5                              (0x1<<5) // MSM Function NORMAL mode default value for pd_cmuregref
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_CMUREGREF_NORM_SETVAL_O_K2_E5_SHIFT                        5
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_REF_NORM_SETVAL_O_K2_E5                                    (0x1<<6) // MSM Function NORMAL mode default value for pd_ref
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_REF_NORM_SETVAL_O_K2_E5_SHIFT                              6
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_RESET_CMU_FL_NORM_SETVAL_O_K2_E5                              (0x1<<7) // MSM Function NORMAL mode default value for reset_cmu_fl
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_RESET_CMU_FL_NORM_SETVAL_O_K2_E5_SHIFT                        7
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_K2_E5                                                           0x003318UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMU_NORM_SETVAL_O_K2_E5                                 (0x1<<0) // MSM Function NORMAL mode default value for reset_cmu
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMU_NORM_SETVAL_O_K2_E5_SHIFT                           0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMU_GCRX_NORM_SETVAL_O_K2_E5                            (0x1<<1) // MSM Function NORMAL mode default value for reset_cmu_gcrx
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMU_GCRX_NORM_SETVAL_O_K2_E5_SHIFT                      1
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMUREG_NORM_SETVAL_O_K2_E5                              (0x1<<2) // MSM Function NORMAL mode default value for reset_cmureg
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMUREG_NORM_SETVAL_O_K2_E5_SHIFT                        2
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMUREGREF_NORM_SETVAL_O_K2_E5                           (0x1<<3) // MSM Function NORMAL mode default value for reset_cmuregref
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMUREGREF_NORM_SETVAL_O_K2_E5_SHIFT                     3
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMUSYNTH_NORM_SETVAL_O_K2_E5                            (0x1<<4) // MSM Function NORMAL mode default value for reset_cmusynth
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMUSYNTH_NORM_SETVAL_O_K2_E5_SHIFT                      4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMUVCO_NORM_SETVAL_O_K2_E5                              (0x1<<5) // MSM Function NORMAL mode default value for reset_cmuvco
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMUVCO_NORM_SETVAL_O_K2_E5_SHIFT                        5
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_LF_EXTZERO_ENA_NORM_SETVAL_O_K2_E5                            (0x1<<6) // MSM Function NORMAL mode default value for lf_extzero_ena
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_LF_EXTZERO_ENA_NORM_SETVAL_O_K2_E5_SHIFT                      6
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_LFI_EXTZERO_NORM_SETVAL_O_K2_E5                               (0x1<<7) // MSM Function NORMAL mode default value for lfi_extzero
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_LFI_EXTZERO_NORM_SETVAL_O_K2_E5_SHIFT                         7
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_K2_E5                                                           0x00331cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_SOC_CLK_EN_NORM_SETVAL_O_K2_E5                                (0x1<<0) // MSM Function NORMAL mode default value for soc_clk_en
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_SOC_CLK_EN_NORM_SETVAL_O_K2_E5_SHIFT                          0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_REFCLK_EN_NORM_SETVAL_O_K2_E5                                 (0x1<<1) // MSM Function NORMAL mode default value for refclk_en
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_REFCLK_EN_NORM_SETVAL_O_K2_E5_SHIFT                           1
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_PLL_LOCK_EN_NORM_SETVAL_O_K2_E5                               (0x1<<2) // MSM Function NORMAL mode default value for pll_lock_en
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_PLL_LOCK_EN_NORM_SETVAL_O_K2_E5_SHIFT                         2
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_RESET_TXCLK_NORM_SETVAL_O_K2_E5                               (0x1<<3) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_RESET_TXCLK_NORM_SETVAL_O_K2_E5_SHIFT                         3
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_RESET_CLKDIV_NORM_SETVAL_O_K2_E5                              (0x1<<4) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_RESET_CLKDIV_NORM_SETVAL_O_K2_E5_SHIFT                        4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_PD_CLKDIV_NORM_SETVAL_O_K2_E5                                 (0x1<<5) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_PD_CLKDIV_NORM_SETVAL_O_K2_E5_SHIFT                           5
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_PD_CLKDIV_REFCLK_LEFT_NORM_SETVAL_O_K2_E5                     (0x1<<6) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_PD_CLKDIV_REFCLK_LEFT_NORM_SETVAL_O_K2_E5_SHIFT               6
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_PD_CLKDIV_REFCLK_RIGHT_NORM_SETVAL_O_K2_E5                    (0x1<<7) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_PD_CLKDIV_REFCLK_RIGHT_NORM_SETVAL_O_K2_E5_SHIFT              7
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_K2_E5                                                           0x003320UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_IDDQ_BIAS_PD_SETVAL_O_K2_E5                                   (0x1<<0) // MSM Function POWER DOWN mode default value for iddq_bias
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_IDDQ_BIAS_PD_SETVAL_O_K2_E5_SHIFT                             0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_BIAS_PD_SETVAL_O_K2_E5                                     (0x1<<1) // MSM Function POWER DOWN mode default value for pd_bias
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_BIAS_PD_SETVAL_O_K2_E5_SHIFT                               1
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_RESET_TXCLK_PCS_CLK_PD_SETVAL_O_K2_E5                         (0x1<<2) // MSM Function POWER DOWN mode default value for pcs_clk_ena
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_RESET_TXCLK_PCS_CLK_PD_SETVAL_O_K2_E5_SHIFT                   2
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_CMU_PD_SETVAL_O_K2_E5                                      (0x1<<3) // MSM Function POWER DOWN mode default value for pd_cmu
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_CMU_PD_SETVAL_O_K2_E5_SHIFT                                3
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_CMUREG_PD_SETVAL_O_K2_E5                                   (0x1<<4) // MSM Function POWER DOWN mode default value for pd_cmureg
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_CMUREG_PD_SETVAL_O_K2_E5_SHIFT                             4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_CMUREGREF_PD_SETVAL_O_K2_E5                                (0x1<<5) // MSM Function POWER DOWN mode default value for pd_cmuregref
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_CMUREGREF_PD_SETVAL_O_K2_E5_SHIFT                          5
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_REF_PD_SETVAL_O_K2_E5                                      (0x1<<6) // MSM Function POWER DOWN mode default value for pd_ref
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_REF_PD_SETVAL_O_K2_E5_SHIFT                                6
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_RESET_CMU_FL_PD_SETVAL_O_K2_E5                                (0x1<<7) // MSM Function POWER DOWN mode default value for reset_cmu_fl
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_RESET_CMU_FL_PD_SETVAL_O_K2_E5_SHIFT                          7
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_K2_E5                                                           0x003324UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMU_PD_SETVAL_O_K2_E5                                   (0x1<<0) // MSM Function POWER DOWN mode default value for reset_cmu
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMU_PD_SETVAL_O_K2_E5_SHIFT                             0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMU_GCRX_PD_SETVAL_O_K2_E5                              (0x1<<1) // MSM Function POWER DOWN mode default value for reset_cmu_gcrx
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMU_GCRX_PD_SETVAL_O_K2_E5_SHIFT                        1
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMUREG_PD_SETVAL_O_K2_E5                                (0x1<<2) // MSM Function POWER DOWN mode default value for reset_cmureg
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMUREG_PD_SETVAL_O_K2_E5_SHIFT                          2
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMUREGREF_PD_SETVAL_O_K2_E5                             (0x1<<3) // MSM Function POWER DOWN mode default value for reset_cmuregref
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMUREGREF_PD_SETVAL_O_K2_E5_SHIFT                       3
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMUSYNTH_PD_SETVAL_O_K2_E5                              (0x1<<4) // MSM Function POWER DOWN mode default value for reset_cmusynth
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMUSYNTH_PD_SETVAL_O_K2_E5_SHIFT                        4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMUVCO_PD_SETVAL_O_K2_E5                                (0x1<<5) // MSM Function POWER DOWN mode default value for reset_cmuvco
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMUVCO_PD_SETVAL_O_K2_E5_SHIFT                          5
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_LF_EXTZERO_ENA_PD_SETVAL_O_K2_E5                              (0x1<<6) // MSM Function POWER DOWN mode default value for lf_extzero_ena
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_LF_EXTZERO_ENA_PD_SETVAL_O_K2_E5_SHIFT                        6
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_LFI_EXTZERO_PD_SETVAL_O_K2_E5                                 (0x1<<7) // MSM Function POWER DOWN mode default value for lfi_extzero
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_LFI_EXTZERO_PD_SETVAL_O_K2_E5_SHIFT                           7
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_K2_E5                                                           0x003328UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_SOC_CLK_EN_PD_SETVAL_O_K2_E5                                  (0x1<<0) // MSM Function POWER DOWN mode default value for soc_clk_en
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_SOC_CLK_EN_PD_SETVAL_O_K2_E5_SHIFT                            0
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_REFCLK_EN_PD_SETVAL_O_K2_E5                                   (0x1<<1) // MSM Function POWER DOWN mode default value for refclk_en
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_REFCLK_EN_PD_SETVAL_O_K2_E5_SHIFT                             1
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_PLL_LOCK_EN_PD_SETVAL_O_K2_E5                                 (0x1<<2) // MSM Function POWER DOWN mode default value for pll_lock_en
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_PLL_LOCK_EN_PD_SETVAL_O_K2_E5_SHIFT                           2
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_RESET_TXCLK_PD_SETVAL_O_K2_E5                                 (0x1<<3) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_RESET_TXCLK_PD_SETVAL_O_K2_E5_SHIFT                           3
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_RESET_CLKDIV_PD_SETVAL_O_K2_E5                                (0x1<<4) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_RESET_CLKDIV_PD_SETVAL_O_K2_E5_SHIFT                          4
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_PD_CLKDIV_PD_SETVAL_O_K2_E5                                   (0x1<<5) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_PD_CLKDIV_PD_SETVAL_O_K2_E5_SHIFT                             5
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_PD_CLKDIV_REFCLK_LEFT_PD_SETVAL_O_K2_E5                       (0x1<<6) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_PD_CLKDIV_REFCLK_LEFT_PD_SETVAL_O_K2_E5_SHIFT                 6
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_PD_CLKDIV_REFCLK_RIGHT_PD_SETVAL_O_K2_E5                      (0x1<<7) // Not used
+  #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_PD_CLKDIV_REFCLK_RIGHT_PD_SETVAL_O_K2_E5_SHIFT                7
+#define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X210_K2_E5                                                           0x003348UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X0_K2_E5                                                               0x000000UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X0_SOC0_DIV_O_K2_E5                                                  (0xf<<0) // Static divider control for SOC0 The only access to this divider. Not an override
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X0_SOC0_DIV_O_K2_E5_SHIFT                                            0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X0_SOC1_DIV_O_K2_E5                                                  (0xf<<4) // Static divider control for SOC1 The only access to this divider. Not an override
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X0_SOC1_DIV_O_K2_E5_SHIFT                                            4
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X1_K2_E5                                                               0x000004UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X1_CK_SOC_DIV_OVR_O_2_0_K2_E5                                        (0x7<<0) // Override for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Enable [1:0] - Override for pins ck_soc_div_i [1:0]
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X1_CK_SOC_DIV_OVR_O_2_0_K2_E5_SHIFT                                  0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X1_PMA_CM_REF_CLK_DIV_O_K2_E5                                        (0x3<<3) // Divider for pma_cm_ref_clk
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X1_PMA_CM_REF_CLK_DIV_O_K2_E5_SHIFT                                  3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X1_GCFSM_CLK_DIV_O_K2_E5                                             (0x3<<5) // Static divider control for CMU GCFSM clock The only access to this divider. Not an override 4d0:  No division  4d1:  /2 4d2:  /2 4d3:  /4:
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X1_GCFSM_CLK_DIV_O_K2_E5_SHIFT                                       5
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X1_BURNIN_REF_LIFE_CLK_SEL_O_K2_E5                                   (0x1<<7) // Reference clock select override value for burn_in mode. This override is enabled by primary input pin burn_in_i
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X1_BURNIN_REF_LIFE_CLK_SEL_O_K2_E5_SHIFT                             7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X2_K2_E5                                                               0x000008UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X2_SSC_CLK_DIV_O_K2_E5                                               (0x7<<0) // Static divider control for the SSC block The only access to this divider. Not an override 4d0:  No division  4d1:  /2 4d2:  /4 4d3:  /8:
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X2_SSC_CLK_DIV_O_K2_E5_SHIFT                                         0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X2_CDR_REFCLK_SEL_O_2_0_K2_E5                                        (0x7<<3) // Selects one lane's recovered byte clock of all existing lanes, which goes to refclk buffer.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X2_CDR_REFCLK_SEL_O_2_0_K2_E5_SHIFT                                  3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X2_CDR_REFDIV_O_1_0_K2_E5                                            (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by 4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X2_CDR_REFDIV_O_1_0_K2_E5_SHIFT                                      6
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X3_K2_E5                                                               0x00000cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X3_AHB_PMA_CM_DIVNSEL_6_0_O_K2_E5                                    (0x7f<<0) // CMU N-divider setting
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X3_AHB_PMA_CM_DIVNSEL_6_0_O_K2_E5_SHIFT                              0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X4_K2_E5                                                               0x000010UL //Access:RW   DataWidth:0x8    // CMU FL LDHS count value
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X5_K2_E5                                                               0x000014UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_FL_LDHS_9_8_O_K2_E5                                    (0x3<<0) // CMU FL LDHS count value
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_FL_LDHS_9_8_O_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_PLL_REFDIV2_ENA_O_K2_E5                                (0x1<<2) // CMU reference div2 enable
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_PLL_REFDIV2_ENA_O_K2_E5_SHIFT                          2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_PREDIV4_ENA_O_K2_E5                                    (0x1<<3) // CMU FL prediv4 enable
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_PREDIV4_ENA_O_K2_E5_SHIFT                              3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_REFCLK_DEGLITCH_DIS_O_K2_E5                            (0x1<<4) // Reference clock startup deglitch circuit disable
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_REFCLK_DEGLITCH_DIS_O_K2_E5_SHIFT                      4
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X6_K2_E5                                                               0x000018UL //Access:RW   DataWidth:0x8    // CMU GCFSM Output Overrides for the following functions: [27] - active high, Override Enable [26]  - GCFSM Request flag [25:24] - GCFSM Function [23:0] - GCFSM Control Signal
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X7_K2_E5                                                               0x00001cUL //Access:RW   DataWidth:0x8    // CMU GCFSM Output Overrides for the following functions: [27] - active high, Override Enable [26]  - GCFSM Request flag [25:24] - GCFSM Function [23:0] - GCFSM Control Signal
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X8_K2_E5                                                               0x000020UL //Access:RW   DataWidth:0x8    // CMU GCFSM Output Overrides for the following functions: [27] - active high, Override Enable [26]  - GCFSM Request flag [25:24] - GCFSM Function [23:0] - GCFSM Control Signal
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X9_K2_E5                                                               0x000024UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X9_GCFSM_OVR_O_27_24_K2_E5                                           (0xf<<0) // CMU GCFSM Output Overrides for the following functions: [27] - active high, Override Enable [26]  - GCFSM Request flag [25:24] - GCFSM Function [23:0] - GCFSM Control Signal
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X9_GCFSM_OVR_O_27_24_K2_E5_SHIFT                                     0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X10_K2_E5                                                              0x000028UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 7-0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X11_K2_E5                                                              0x00002cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 15-8
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X12_K2_E5                                                              0x000030UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 23-16
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X13_K2_E5                                                              0x000034UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 31-24
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X14_K2_E5                                                              0x000038UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 39-32
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X15_K2_E5                                                              0x00003cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 47-40
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X16_K2_E5                                                              0x000040UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 55-48
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X17_K2_E5                                                              0x000044UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 63-56
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X18_K2_E5                                                              0x000048UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 71-64
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X19_K2_E5                                                              0x00004cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 79-72
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X20_K2_E5                                                              0x000050UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 87-80
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X21_K2_E5                                                              0x000054UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 95-88
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X22_K2_E5                                                              0x000058UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 103-96
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X23_K2_E5                                                              0x00005cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 111-104
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X24_K2_E5                                                              0x000060UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 119-112
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X25_K2_E5                                                              0x000064UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 127-120
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X26_K2_E5                                                              0x000068UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X26_GCFSM_CMU_OUT_OVR_EN_O_K2_E5                                     (0x1<<0) // GCFSM output override enable
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X26_GCFSM_CMU_OUT_OVR_EN_O_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X26_GCFSM_CMU_PMA_DATA_OVR_O_6_0_K2_E5                               (0x7f<<1) // GCFSM pma_data_o override
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X26_GCFSM_CMU_PMA_DATA_OVR_O_6_0_K2_E5_SHIFT                         1
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X27_K2_E5                                                              0x00006cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_DATA_OVR_O_11_7_K2_E5                              (0x1f<<0) // GCFSM pma_data_o override
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_DATA_OVR_O_11_7_K2_E5_SHIFT                        0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_LATCH_OVR_O_K2_E5                                  (0x1<<5) // GCFSM pma_latch_o override
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_LATCH_OVR_O_K2_E5_SHIFT                            5
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_GO_OVR_O_K2_E5                                     (0x1<<6) // GCFSM pma_go_o override
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_GO_OVR_O_K2_E5_SHIFT                               6
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_READ_OVR_O_K2_E5                                   (0x1<<7) // GCFSM pma_read_o override
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_READ_OVR_O_K2_E5_SHIFT                             7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X28_K2_E5                                                              0x000070UL //Access:RW   DataWidth:0x8    // GCFSM pma_cal_o override
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X29_K2_E5                                                              0x000074UL //Access:RW   DataWidth:0x8    // GCFSM pma_cal_o override
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X30_K2_E5                                                              0x000078UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_SOC_CLK_EN_OUT_OVR_O_K2_E5                               (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - SOC clock output enable
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_SOC_CLK_EN_OUT_OVR_O_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_REF_CLK_EN_OUT_OVR_O_K2_E5                               (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - REF clock output enable
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_REF_CLK_EN_OUT_OVR_O_K2_E5_SHIFT                         2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_LOCK_EN_OUT_OVR_O_K2_E5                                  (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - LOCK output enable
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_LOCK_EN_OUT_OVR_O_K2_E5_SHIFT                            4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_PMA_RST_CMU_OUT_OVR_O_K2_E5                              (0x3<<6) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_PMA_RST_CMU_OUT_OVR_O_K2_E5_SHIFT                        6
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X31_K2_E5                                                              0x00007cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_RST_CMUREG_OUT_OVR_O_K2_E5                           (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - SOC clock output enable - switches to SOC from life clock
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_RST_CMUREG_OUT_OVR_O_K2_E5_SHIFT                     0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_RST_CMUSYNTH_OUT_OVR_O_K2_E5                         (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU SYNTH
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_RST_CMUSYNTH_OUT_OVR_O_K2_E5_SHIFT                   2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_RST_CMUVCO_OUT_OVR_O_K2_E5                           (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU VC0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_RST_CMUVCO_OUT_OVR_O_K2_E5_SHIFT                     4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_IDDQ_BIAS_OUT_OVR_O_K2_E5                            (0x3<<6) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - IDDQ BIAS
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_IDDQ_BIAS_OUT_OVR_O_K2_E5_SHIFT                      6
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X32_K2_E5                                                              0x000080UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_BIAS_OUT_OVR_O_K2_E5                              (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD BIAS
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_BIAS_OUT_OVR_O_K2_E5_SHIFT                        0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_CMU_OUT_OVR_O_K2_E5                               (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD CMU
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_CMU_OUT_OVR_O_K2_E5_SHIFT                         2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_CMUREG_OUT_OVR_O_K2_E5                            (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD CMU REG
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_CMUREG_OUT_OVR_O_K2_E5_SHIFT                      4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_REF_OUT_OVR_O_K2_E5                               (0x3<<6) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD REF OUT
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_REF_OUT_OVR_O_K2_E5_SHIFT                         6
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X33_K2_E5                                                              0x000084UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X33_MSM_CMU_PMA_RESET_TXCLK_PCS_CLK_OVR_O_K2_E5                      (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PCS CLK ENA
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X33_MSM_CMU_PMA_RESET_TXCLK_PCS_CLK_OVR_O_K2_E5_SHIFT                0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X33_MSM_CMU_PMA_RST_CMU_FL_OUT_OVR_O_K2_E5                           (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU FL
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X33_MSM_CMU_PMA_RST_CMU_FL_OUT_OVR_O_K2_E5_SHIFT                     2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X33_MSM_CMU_PMA_RST_CMU_GCRX_OUT_OVR_O_K2_E5                         (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU GCRX
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X33_MSM_CMU_PMA_RST_CMU_GCRX_OUT_OVR_O_K2_E5_SHIFT                   4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X33_MSM_PMA_LF_EXTZERO_ENA_OUT_OVR_O_K2_E5                           (0x3<<6) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - LF EXTZERO ENA
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X33_MSM_PMA_LF_EXTZERO_ENA_OUT_OVR_O_K2_E5_SHIFT                     6
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X34_K2_E5                                                              0x000088UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X34_MSM_CMU_PMA_LFI_EXTZERO_OUT_OVR_O_K2_E5                          (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - LFI EXTZERO ENA
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X34_MSM_CMU_PMA_LFI_EXTZERO_OUT_OVR_O_K2_E5_SHIFT                    0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X34_MSM_CMU_PMA_PD_CMUREGREF_OUT_OVR_O_K2_E5                         (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD CMU REGREF
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X34_MSM_CMU_PMA_PD_CMUREGREF_OUT_OVR_O_K2_E5_SHIFT                   2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X34_MSM_PMA_RESET_CMUREGREF_OUT_OVR_O_K2_E5                          (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU REGREF
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X34_MSM_PMA_RESET_CMUREGREF_OUT_OVR_O_K2_E5_SHIFT                    4
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X56_K2_E5                                                              0x0000e0UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X57_K2_E5                                                              0x0000e4UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X58_K2_E5                                                              0x0000e8UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X59_K2_E5                                                              0x0000ecUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X60_K2_E5                                                              0x0000f0UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X61_K2_E5                                                              0x0000f4UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X62_K2_E5                                                              0x0000f8UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X63_K2_E5                                                              0x0000fcUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X64_K2_E5                                                              0x000100UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X65_K2_E5                                                              0x000104UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X66_K2_E5                                                              0x000108UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X67_K2_E5                                                              0x00010cUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X68_K2_E5                                                              0x000110UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X69_K2_E5                                                              0x000114UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X70_K2_E5                                                              0x000118UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X71_K2_E5                                                              0x00011cUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X72_K2_E5                                                              0x000120UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X73_K2_E5                                                              0x000124UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X74_K2_E5                                                              0x000128UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X75_K2_E5                                                              0x00012cUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X76_K2_E5                                                              0x000130UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X77_K2_E5                                                              0x000134UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X78_K2_E5                                                              0x000138UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X79_K2_E5                                                              0x00013cUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X80_K2_E5                                                              0x000140UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X81_K2_E5                                                              0x000144UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X82_K2_E5                                                              0x000148UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X83_K2_E5                                                              0x00014cUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X84_K2_E5                                                              0x000150UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X85_K2_E5                                                              0x000154UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X86_K2_E5                                                              0x000158UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X87_K2_E5                                                              0x00015cUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X88_K2_E5                                                              0x000160UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X89_K2_E5                                                              0x000164UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X90_K2_E5                                                              0x000168UL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X91_K2_E5                                                              0x00016cUL //Access:RW   DataWidth:0x8    // MSM Function Data Bus slice
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X92_K2_E5                                                              0x000170UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X92_MSM_FUNC_DATA_O_289_288_K2_E5                                    (0x3<<0) // MSM Function Data Bus slice
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X92_MSM_FUNC_DATA_O_289_288_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X92_MSM_IN_OVR_O_5_0_K2_E5                                           (0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag override [3:0] - MFSM function override
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X92_MSM_IN_OVR_O_5_0_K2_E5_SHIFT                                     2
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X93_K2_E5                                                              0x000174UL //Access:RW   DataWidth:0x8    // Number of reference clock cycles to count after qsample is ok, before PLL is declared locked
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X94_K2_E5                                                              0x000178UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_NUM_CYCLES_O_9_8_K2_E5                                  (0x3<<0) // Number of reference clock cycles to count after qsample is ok, before PLL is declared locked
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_NUM_CYCLES_O_9_8_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_GOOD_STATE_O_K2_E5                                      (0x1<<2) // State of qsample for PLL to be considered locked
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_GOOD_STATE_O_K2_E5_SHIFT                                2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_OVR_O_K2_E5                                             (0x7<<3) // Overrides for PLL lock signals [2] - Active high, override enable [1] - PLL ok override, bypasses ref clock cycle count after qsample is ok [0] - Qsample override
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_OVR_O_K2_E5_SHIFT                                       3
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X95_K2_E5                                                              0x00017cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_KVCO_SEL_O_K2_E5                                    (0x3<<0) // CMU VCO integral path gain
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_KVCO_SEL_O_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_FORCE_ILF_O_K2_E5                                     (0x3<<2) // CMU loop filter force to common mode
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_FORCE_ILF_O_K2_E5_SHIFT                               2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_CP_SEL_O_K2_E5                                      (0x3<<4) // Charge pump current gain select.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_CP_SEL_O_K2_E5_SHIFT                                4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_HIZ_O_K2_E5                                         (0x1<<6) // CMU PLL HIZ setting
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_HIZ_O_K2_E5_SHIFT                                   6
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_C1_SEL_O_K2_E5                                        (0x1<<7) // CMU LF C1 cap select. Enabling increases C1 cap.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_C1_SEL_O_K2_E5_SHIFT                                  7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X96_K2_E5                                                              0x000180UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_P_CAP_SEL_O_K2_E5                                     (0x7<<0) // CMU VCO proportional path cap select
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_P_CAP_SEL_O_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_CHPMP_CHOP_ENAN_O_K2_E5                               (0x1<<3) // Charge pump chop enable
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_CHPMP_CHOP_ENAN_O_K2_E5_SHIFT                         3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_I_CAP_SEL_O_K2_E5                                     (0x7<<4) // CMU VCO integral path cap select
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_I_CAP_SEL_O_K2_E5_SHIFT                               4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_BGSTART_BYP_O_K2_E5                                   (0x1<<7) // Bandgap startup circuit bypass
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_BGSTART_BYP_O_K2_E5_SHIFT                             7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X97_K2_E5                                                              0x000184UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X97_AHB_PMA_CM_VCO_BIAS_O_K2_E5                                      (0xf<<0) // CMU VCO bias current setting.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X97_AHB_PMA_CM_VCO_BIAS_O_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X97_AHB_PMA_CM_VREG_O_K2_E5                                          (0x3<<4) // CMU VREG setting
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X97_AHB_PMA_CM_VREG_O_K2_E5_SHIFT                                    4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X97_AHB_PMA_CM_VREGH_O_K2_E5                                         (0x3<<6) // CMU VREGH setting
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X97_AHB_PMA_CM_VREGH_O_K2_E5_SHIFT                                   6
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_K2_E5                                                              0x000188UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PFD_FORCE_DN_O_K2_E5                                  (0x1<<0) // Force PFD to output down
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PFD_FORCE_DN_O_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PFD_FORCE_UP_O_K2_E5                                  (0x1<<1) // Force PFD to output up
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PFD_FORCE_UP_O_K2_E5_SHIFT                            1
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_SR_NDIV_OVR_ENA_O_K2_E5                                          (0x1<<2) // Override enable for overriding N-div value
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_SR_NDIV_OVR_ENA_O_K2_E5_SHIFT                                    2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_V2I_FILTER_SW_ON_O_K2_E5                              (0x1<<3) // CMU V2I filter enable
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_V2I_FILTER_SW_ON_O_K2_E5_SHIFT                        3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_O_K2_E5                        (0x1<<4) // CMU VCO PMOS proportional current increase
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_O_K2_E5_SHIFT                  4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_LESS_EN_O_K2_E5                        (0x1<<5) // CMU VCO PMOS proportional current decrease
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_LESS_EN_O_K2_E5_SHIFT                  5
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_VREGREF_O_K2_E5                                       (0x3<<6) // CMU reference clock regulator setting
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_VREGREF_O_K2_E5_SHIFT                                 6
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X99_K2_E5                                                              0x00018cUL //Access:RW   DataWidth:0x8    // CMU AFE spares
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X100_K2_E5                                                             0x000190UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_PFD_PW_O_K2_E5                                       (0x3<<0) // PFD pulse width setting
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_PFD_PW_O_K2_E5_SHIFT                                 0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_I_DROPI_O_K2_E5                                      (0x1<<2) // Enable to reduce charge pump reference current
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_I_DROPI_O_K2_E5_SHIFT                                2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_P_KVCO_SEL_O_K2_E5                                   (0x1f<<3) // CMU PLL KVCO setting
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_P_KVCO_SEL_O_K2_E5_SHIFT                             3
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X101_K2_E5                                                             0x000194UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X101_AHB_PMA_CM_DIVPSEL_O_K2_E5                                      (0x7f<<0) // CMU P-divider setting
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X101_AHB_PMA_CM_DIVPSEL_O_K2_E5_SHIFT                                0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X102_K2_E5                                                             0x000198UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X102_AHB_PMA_CM_VCOFR_O_K2_E5                                        (0x7<<0) // AHB override for calibrated VCOFR value.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X102_AHB_PMA_CM_VCOFR_O_K2_E5_SHIFT                                  0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X102_AHB_PMA_CM_VCOFR_SEL_O_K2_E5                                    (0x1<<3) // Override enable for overriding VCOFR value
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X102_AHB_PMA_CM_VCOFR_SEL_O_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X108_K2_E5                                                             0x0001b0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X108_PMA_REFCLK_OUTPUT_SEL_O_3_0_K2_E5                               (0xf<<3) // Reference clock output select
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X108_PMA_REFCLK_OUTPUT_SEL_O_3_0_K2_E5_SHIFT                         3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X108_PMA_REFCLK_SEL_OVR_O_K2_E5                                      (0x1<<7) // Reference clock select override
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X108_PMA_REFCLK_SEL_OVR_O_K2_E5_SHIFT                                7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_K2_E5                                                             0x0001b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_OE_L_O_K2_E5                                         (0x1<<0) // Override for primary IO: refclk_oe_l_i Enabled by pma_refclk_sel_ovr_o
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_OE_L_O_K2_E5_SHIFT                                   0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_OE_R_O_K2_E5                                         (0x1<<1) // "Override for primary IO: refclk_oe_r_i Enabled by pma_refclk_sel_ovr_o"
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_OE_R_O_K2_E5_SHIFT                                   1
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_RXCLK_OE_L_O_K2_E5                                          (0x1<<2) // "Override for primary IO: rxclk_oe_l_i Enabled by pma_refclk_sel_ovr_o"
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_RXCLK_OE_L_O_K2_E5_SHIFT                                    2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_RXCLK_OE_R_O_K2_E5                                          (0x1<<3) // Override for primary IO: rxclk_oe_l_i Enabled by pma_refclk_sel_ovr_o
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_RXCLK_OE_R_O_K2_E5_SHIFT                                    3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_CM_HV2P5SEL_O_K2_E5                                         (0x1<<4) // Enable additonal LF cap for 2.5V/3.3V process
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_CM_HV2P5SEL_O_K2_E5_SHIFT                                   4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_QFWD_L_O_K2_E5                                       (0x1<<6) // Override for primary IO: refclk_qfwd_l_i Enabled by pma_refclk_sel_ovr_o
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_QFWD_L_O_K2_E5_SHIFT                                 6
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_QFWD_R_O_K2_E5                                       (0x1<<7) // Override for primary IO: refclk_qfwd_r_i Enabled by pma_refclk_sel_ovr_o
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_QFWD_R_O_K2_E5_SHIFT                                 7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X110_K2_E5                                                             0x0001b8UL //Access:RW   DataWidth:0x8    // Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X111_K2_E5                                                             0x0001bcUL //Access:RW   DataWidth:0x8    // Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X112_K2_E5                                                             0x0001c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X112_SSC_FCNTL_O_19_16_K2_E5                                         (0xf<<0) // Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X112_SSC_FCNTL_O_19_16_K2_E5_SHIFT                                   0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X112_SSC_GEN_EN_O_K2_E5                                              (0x1<<4) // Active high Enable for SSC generator SSC mode
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X112_SSC_GEN_EN_O_K2_E5_SHIFT                                        4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X112_SSC_EN_O_K2_E5                                                  (0x1<<5) // Active high Enable for SSC block synth or SSC mode
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X112_SSC_EN_O_K2_E5_SHIFT                                            5
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X113_K2_E5                                                             0x0001c4UL //Access:RW   DataWidth:0x8    // SSC match value for Spread Spectrum Generation mode. Represents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X114_K2_E5                                                             0x0001c8UL //Access:RW   DataWidth:0x8    // SSC match value for Spread Spectrum Generation mode. Represents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X115_K2_E5                                                             0x0001ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_MATCH_VAL_O_19_16_K2_E5                                 (0xf<<0) // SSC match value for Spread Spectrum Generation mode. Represents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_MATCH_VAL_O_19_16_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_FRACSYN_EN_O_K2_E5                                      (0x1<<4) // Enable for SSC generator with Fractional Synthesis
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_FRACSYN_EN_O_K2_E5_SHIFT                                4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X115_EN_FRACN_FRCDIV_MODE_O_K2_E5                                    (0x1<<5) // Enable fractional division mode and SSC mode
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X115_EN_FRACN_FRCDIV_MODE_O_K2_E5_SHIFT                              5
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_UPDOWN_EN_O_K2_E5                                       (0x1<<6) // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down spreading
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_UPDOWN_EN_O_K2_E5_SHIFT                                 6
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X116_K2_E5                                                             0x0001d0UL //Access:RW   DataWidth:0x8    // In Spread Spectrum Generation mode, represents the magnitude of the incremental step in the SSC word
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X117_K2_E5                                                             0x0001d4UL //Access:RW   DataWidth:0x8    // In Spread Spectrum Generation mode, represents the magnitude of the incremental step in the SSC word
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X118_K2_E5                                                             0x0001d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X118_FRACN_MOD_TST_IN_O_K2_E5                                        (0xf<<0) // Test input bus
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X118_FRACN_MOD_TST_IN_O_K2_E5_SHIFT                                  0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X118_FRACN_MOD_TST_CTRL_O_K2_E5                                      (0x3<<4) // Test i/p control source :  0-modulator  1-bypass modulator  2-modulator  3-sr_txt_in_i
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X118_FRACN_MOD_TST_CTRL_O_K2_E5_SHIFT                                4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X118_FRACN_FBK_CLK_SRC_SEL_O_K2_E5                                   (0x1<<6) // Clock Select for High Speed clock source :  0-clk_hs_fbk  1-clk_hs_refout
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X118_FRACN_FBK_CLK_SRC_SEL_O_K2_E5_SHIFT                             6
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X118_FRACN_FBK_CLK_DIV_SEL_O_K2_E5                                   (0x1<<7) // Clock divider for High Speed clock source
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X118_FRACN_FBK_CLK_DIV_SEL_O_K2_E5_SHIFT                             7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X119_K2_E5                                                             0x0001dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_OVR_O_4_0_K2_E5                                (0x1f<<0) // override for the counter value
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_OVR_O_4_0_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_POLL_EN_O_K2_E5                                (0x1<<5) // CMU Temperature Calibration Polling Enable: enables the periodic polling and counter adjustment
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_POLL_EN_O_K2_E5_SHIFT                          5
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_POLARITY_O_K2_E5                               (0x1<<6) // chicken bit for counter polarity
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_POLARITY_O_K2_E5_SHIFT                         6
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_OVR_EN_O_K2_E5                                 (0x1<<7) // override enable to use above value
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_OVR_EN_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X120_K2_E5                                                             0x0001e0UL //Access:RW   DataWidth:0x8    // Divider input for Div-by-N counter
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X121_K2_E5                                                             0x0001e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X121_AHB_CMU_TEMP_CAL_CLK_DIV_O_14_8_K2_E5                           (0x7f<<0) // Divider input for Div-by-N counter
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X121_AHB_CMU_TEMP_CAL_CLK_DIV_O_14_8_K2_E5_SHIFT                     0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X122_K2_E5                                                             0x0001e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X122_PMA_CM_REFCLK_TERM_OVR_O_K2_E5                                  (0x1f<<0) // Refclk Termination override value
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X122_PMA_CM_REFCLK_TERM_OVR_O_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X122_PMA_CM_REFCLK_TERM_OVR_EN_O_K2_E5                               (0x1<<5) // Refclk Termination override enable
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X122_PMA_CM_REFCLK_TERM_OVR_EN_O_K2_E5_SHIFT                         5
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X123_K2_E5                                                             0x0001ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X123_PMA_CM_RX_TERM_OVR_O_K2_E5                                      (0x1f<<0) // Rx Termination override value, every rx lane gets the same value
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X123_PMA_CM_RX_TERM_OVR_O_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X123_PMA_CM_RX_TERM_OVR_EN_O_K2_E5                                   (0x1<<5) // Rx Termination override enable
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X123_PMA_CM_RX_TERM_OVR_EN_O_K2_E5_SHIFT                             5
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X124_K2_E5                                                             0x0001f0UL //Access:RW   DataWidth:0x8    // In txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X125_K2_E5                                                             0x0001f4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_WAIT_NEXT_UP_8_K2_E5                                  (0x1<<0) // In txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_WAIT_NEXT_UP_8_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_WAIT_NEXT_SAMPLE_K2_E5                                (0x7<<1) // in txterm calibration, the number refclk cycles to wait before sampling the up from the same comparator
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_WAIT_NEXT_SAMPLE_K2_E5_SHIFT                          1
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_UP_NUM_SAMPLES_K2_E5                                  (0xf<<4) // in txterm calibration, the number of samples to take from the same comparator
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_UP_NUM_SAMPLES_K2_E5_SHIFT                            4
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X126_K2_E5                                                             0x0001f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X126_AHB_GC_TCCAL_ENA_OVR_K2_E5                                      (0x1<<0) // Debug feature, when set forces circuit RX termination calibration circuit to be enabled allowing ahb_tx_tc_bias_ovr to take effect
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X126_AHB_GC_TCCAL_ENA_OVR_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X126_AHB_RX_TC_BIAS_OVR_K2_E5                                        (0x7<<1) // Bit 3:1 RX termination calibration DAC override setting
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X126_AHB_RX_TC_BIAS_OVR_K2_E5_SHIFT                                  1
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X127_K2_E5                                                             0x0001fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X127_CMU_MASTER_CDN_O_K2_E5                                          (0x1<<0) // Master reset for CMU
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X127_CMU_MASTER_CDN_O_K2_E5_SHIFT                                    0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X127_PCS_RATE_O_K2_E5                                                (0x3<<1) // Determines rate for PLL clock pcs_rate_o[0] :      0: VCO clock untouched      1: VCO clock divided by 2                                                 pcs_rate_o[1] :      0: PMA operates in 10b/20b mode Enables %5 circuit      1: PMA operates in 8b/16b mode   Enables %4 circuit
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X127_PCS_RATE_O_K2_E5_SHIFT                                          1
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X128_K2_E5                                                             0x000200UL //Access:RW   DataWidth:0x8    // Not used
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X129_K2_E5                                                             0x000204UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X129_CMU_IN_OVR_O_3_0_K2_E5                                          (0xf<<0) // Override for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pin IO [0] - CMU Reset Pin IO
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X129_CMU_IN_OVR_O_3_0_K2_E5_SHIFT                                    0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X129_CMU_OUT_OVR_O_1_0_K2_E5                                         (0x3<<4) // Override for Reset_smu_fl
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X129_CMU_OUT_OVR_O_1_0_K2_E5_SHIFT                                   4
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5                                                             0x000208UL //Access:R    DataWidth:0x8    // Snapshot of digital test bus data [7:0]
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5                                                             0x00020cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_TBUS_DATA_SMPL_11_8_K2_E5                                       (0xf<<0) // Snapshot of digital test bus data [11:8]
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_TBUS_DATA_SMPL_11_8_K2_E5_SHIFT                                 0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5                                                             0x000210UL //Access:RW   DataWidth:0x8    // CMU Test Bus address 7-0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5                                                             0x000214UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_TBUS_ADDR_OVR_O_10_8_K2_E5                                      (0x7<<0) // CMU Test Bus address 10-8
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_TBUS_ADDR_OVR_O_10_8_K2_E5_SHIFT                                0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X134_K2_E5                                                             0x000218UL //Access:RW   DataWidth:0x8    // Not used
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X135_K2_E5                                                             0x00021cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X135_GEN3_PMA_CM_REF_CLK_DIV_O_K2_E5                                 (0x3<<0) // "Divider for pma_cm_ref_clk in gen3 rate. Used only in PCIe3 1CMU config"
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X135_GEN3_PMA_CM_REF_CLK_DIV_O_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X135_GEN3_GCFSM_CLK_DIV_O_K2_E5                                      (0x3<<2) // Static divider control for CMU GCFSM clock in gen3 rate The only access to this divider. Not an override 4d0:  No division  4d1:  /2 4d2:  /2 4d3:  /4: Used only in PCIe3 1CMU config
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X135_GEN3_GCFSM_CLK_DIV_O_K2_E5_SHIFT                                2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X135_GEN3_SSC_CLK_DIV_O_K2_E5                                        (0x7<<4) // Static divider control for the SSC clock in gen3 rate. The only access to this divider. Not an override 4d0:  No division  4d1:  /2 4d2:  /4 4d3:  /8 Used only in PCIe3 1CMU config
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X135_GEN3_SSC_CLK_DIV_O_K2_E5_SHIFT                                  4
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X136_K2_E5                                                             0x000220UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X136_GEN3_PCS_RATE_O_K2_E5                                           (0x3<<0) // Determines rate for PLL clock in gen3 rate pcs_rate_o[0] :      0: VCO clock untouched      1: VCO clock divided by 2                                                 pcs_rate_o[1] :      0: PMA operates in 10b/20b mode Enables %5 circuit      1: PMA operates in 8b/16b mode   Enables %4 circuit Used only in PCIe3 1CMU config
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X136_GEN3_PCS_RATE_O_K2_E5_SHIFT                                     0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X136_CMU_RATE_IS_GEN3_OVR_EN_O_K2_E5                                 (0x1<<2) // Override enable for overridng internal signal cmu_rate_is_gen3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X136_CMU_RATE_IS_GEN3_OVR_EN_O_K2_E5_SHIFT                           2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X136_CMU_RATE_IS_GEN3_OVR_O_K2_E5                                    (0x1<<3) // Override for internal signal cmu_rate_is_gen3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X136_CMU_RATE_IS_GEN3_OVR_O_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X137_K2_E5                                                             0x000224UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X137_AHB_PMA_CM_I_KVCO_SEL_GEN3_O_K2_E5                              (0x3<<0) // CMU VCO proportional current gain
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X137_AHB_PMA_CM_I_KVCO_SEL_GEN3_O_K2_E5_SHIFT                        0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X137_AHB_PMA_CM_FORCE_ILF_GEN3_O_K2_E5                               (0x3<<2) // CMU LF Force value in gen3 rate Used only in PCIe3 1CMU config
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X137_AHB_PMA_CM_FORCE_ILF_GEN3_O_K2_E5_SHIFT                         2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X137_AHB_PMA_CM_I_CP_SEL_GEN3_O_K2_E5                                (0x3<<4) // Charge pump current gain select.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X137_AHB_PMA_CM_I_CP_SEL_GEN3_O_K2_E5_SHIFT                          4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X137_AHB_PMA_CM_I_HIZ_GEN3_O_K2_E5                                   (0x1<<6) // CMU PLL HIZ setting in gen3 rate Used only in PCIe3 1CMU config
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X137_AHB_PMA_CM_I_HIZ_GEN3_O_K2_E5_SHIFT                             6
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X137_AHB_PMA_CM_C1_SEL_GEN3_O_K2_E5                                  (0x1<<7) // CMU LF C1 cap select. Enabling increases C1 cap.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X137_AHB_PMA_CM_C1_SEL_GEN3_O_K2_E5_SHIFT                            7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X138_K2_E5                                                             0x000228UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X138_AHB_PMA_CM_P_CAP_SEL_GEN3_O_K2_E5                               (0x7<<0) // CMU VCO proportional path cap select
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X138_AHB_PMA_CM_P_CAP_SEL_GEN3_O_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X138_AHB_PMA_CM_CHPMP_CHOP_ENAN_GEN3_O_K2_E5                         (0x1<<3) // Charge pump chop enable in gen3 rate Used only in PCIe3 1CMU config
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X138_AHB_PMA_CM_CHPMP_CHOP_ENAN_GEN3_O_K2_E5_SHIFT                   3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X138_AHB_PMA_CM_I_CAP_SEL_GEN3_O_K2_E5                               (0x7<<4) // CMU VCO integral path cap select
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X138_AHB_PMA_CM_I_CAP_SEL_GEN3_O_K2_E5_SHIFT                         4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X138_AHB_PMA_CM_BGSTART_BYP_GEN3_O_K2_E5                             (0x1<<7) // Bandgap startup circuit bypass
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X138_AHB_PMA_CM_BGSTART_BYP_GEN3_O_K2_E5_SHIFT                       7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X139_K2_E5                                                             0x00022cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X139_AHB_PMA_CM_VCO_BIAS_GEN3_O_K2_E5                                (0xf<<0) // CMU VCO bias current setting
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X139_AHB_PMA_CM_VCO_BIAS_GEN3_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X139_AHB_PMA_CM_VREG_GEN3_O_K2_E5                                    (0x3<<4) // CMU VREG setting in gen3 rate Used only in PCIe3 1CMU config
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X139_AHB_PMA_CM_VREG_GEN3_O_K2_E5_SHIFT                              4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X139_AHB_PMA_CM_VREGH_GEN3_O_K2_E5                                   (0x3<<6) // CMU VREGH setting in gen3 rate Used only in PCIe3 1CMU config
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X139_AHB_PMA_CM_VREGH_GEN3_O_K2_E5_SHIFT                             6
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_K2_E5                                                             0x000230UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_PFD_FORCE_DN_GEN3_O_K2_E5                            (0x1<<0) // Force PFD to output down in gen3 rate Used only in PCIe3 1CMU config
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_PFD_FORCE_DN_GEN3_O_K2_E5_SHIFT                      0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_PFD_FORCE_UP_GEN3_O_K2_E5                            (0x1<<1) // Force PFD to output up in gen3 rate Used only in PCIe3 1CMU config
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_PFD_FORCE_UP_GEN3_O_K2_E5_SHIFT                      1
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_V2I_FILTER_SW_ON_GEN3_O_K2_E5                        (0x1<<2) // CMU V2I filter enable in gen3 rate Used only in PCIe3 1CMU config
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_V2I_FILTER_SW_ON_GEN3_O_K2_E5_SHIFT                  2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_GEN3_O_K2_E5                  (0x1<<3) // CMU VCO PMOS proportional current increase
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_GEN3_O_K2_E5_SHIFT            3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_PRP_DAC_DOWN_I_LESS_EN_GEN3_O_K2_E5                  (0x1<<4) // CMU VCO PMOS proportional current decrease
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_PRP_DAC_DOWN_I_LESS_EN_GEN3_O_K2_E5_SHIFT            4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_VREGREF_GEN3_O_K2_E5                                 (0x3<<5) // CMU VDREGREF setting
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_VREGREF_GEN3_O_K2_E5_SHIFT                           5
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X141_K2_E5                                                             0x000234UL //Access:RW   DataWidth:0x8    // CMU AFE spares in gen3 rate Used only in PCIe3 1CMU config
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X142_K2_E5                                                             0x000238UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X142_AHB_PMA_CM_PFD_PW_GEN3_O_K2_E5                                  (0x3<<0) // PFD pulse width setting in gen3 rate Used only in PCIe3 1CMU config
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X142_AHB_PMA_CM_PFD_PW_GEN3_O_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X142_AHB_PMA_CM_I_DROPI_GEN3_O_K2_E5                                 (0x1<<2) // Enable to reduce charge pump reference current
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X142_AHB_PMA_CM_I_DROPI_GEN3_O_K2_E5_SHIFT                           2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X142_AHB_PMA_CM_P_KVCO_SEL_GEN3_O_K2_E5                              (0x1f<<3) // CMU PLL KVCO setting in gen3 rate Used only in PCIe3 1CMU config
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X142_AHB_PMA_CM_P_KVCO_SEL_GEN3_O_K2_E5_SHIFT                        3
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X143_K2_E5                                                             0x00023cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X143_AHB_PMA_CM_DIVPSEL_GEN3_O_K2_E5                                 (0x7f<<0) // CMU P-divider setting in gen3 rate Used only in PCIe3 1CMU config
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X143_AHB_PMA_CM_DIVPSEL_GEN3_O_K2_E5_SHIFT                           0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X144_K2_E5                                                             0x000240UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X144_AHB_PMA_CM_VCOFR_GEN3_O_K2_E5                                   (0x7<<0) // Override enable for overriding VCOFR value in gen3 rate Used only in PCIe3 1CMU config
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X144_AHB_PMA_CM_VCOFR_GEN3_O_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X144_AHB_PMA_CM_PLL_REFDIV2_ENA_GEN3_O_K2_E5                         (0x1<<3) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X144_AHB_PMA_CM_PLL_REFDIV2_ENA_GEN3_O_K2_E5_SHIFT                   3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X144_AHB_PMA_CM_PREDIV4_ENA_GEN3_O_K2_E5                             (0x1<<4) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X144_AHB_PMA_CM_PREDIV4_ENA_GEN3_O_K2_E5_SHIFT                       4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X144_AHB_PMA_CM_FL_LDHS_GEN3_9_8_O_K2_E5                             (0x3<<6) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X144_AHB_PMA_CM_FL_LDHS_GEN3_9_8_O_K2_E5_SHIFT                       6
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X145_K2_E5                                                             0x000244UL //Access:RW   DataWidth:0x8    // Not used
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X146_K2_E5                                                             0x000248UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X146_AHB_PMA_CM_DIVNSEL_GEN3_O_K2_E5                                 (0x7f<<0) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X146_AHB_PMA_CM_DIVNSEL_GEN3_O_K2_E5_SHIFT                           0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X147_K2_E5                                                             0x00024cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X147_AHB_CMU_PROG_MULT_REF_CLK_WAIT_O_K2_E5                          (0x7<<0) // wait multiplication factor for msm_cmu_databank
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X147_AHB_CMU_PROG_MULT_REF_CLK_WAIT_O_K2_E5_SHIFT                    0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X149_K2_E5                                                             0x000254UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X149_AHB_PMA_CM_EN_REGLN_O_K2_E5                                     (0xf<<0) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X149_AHB_PMA_CM_EN_REGLN_O_K2_E5_SHIFT                               0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X150_K2_E5                                                             0x000258UL //Access:RW   DataWidth:0x8    // Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode in gen3 rate Used only in PCIe3 1CMU config
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X151_K2_E5                                                             0x00025cUL //Access:RW   DataWidth:0x8    // Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode in gen3 rate Used only in PCIe3 1CMU config
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X152_K2_E5                                                             0x000260UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X152_GEN3_SSC_FCNTL_O_19_16_K2_E5                                    (0xf<<0) // Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode in gen3 rate Used only in PCIe3 1CMU config
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X152_GEN3_SSC_FCNTL_O_19_16_K2_E5_SHIFT                              0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X153_K2_E5                                                             0x000264UL //Access:RW   DataWidth:0x8    // Inverts up_i when set to 1
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X154_K2_E5                                                             0x000268UL //Access:RW   DataWidth:0x8    // Inverts up_i when set to 1
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X161_K2_E5                                                             0x000284UL //Access:RW   DataWidth:0x8    // Function info for each MSM function. Varies depending on function number. _13:06 - Address of first command to run _05:00 - Number of commands to run
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X162_K2_E5                                                             0x000288UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X163_K2_E5                                                             0x00028cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X164_K2_E5                                                             0x000290UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X165_K2_E5                                                             0x000294UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X166_K2_E5                                                             0x000298UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X167_K2_E5                                                             0x00029cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X168_K2_E5                                                             0x0002a0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X169_K2_E5                                                             0x0002a4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X170_K2_E5                                                             0x0002a8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X171_K2_E5                                                             0x0002acUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X172_K2_E5                                                             0x0002b0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X173_K2_E5                                                             0x0002b4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X174_K2_E5                                                             0x0002b8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X175_K2_E5                                                             0x0002bcUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X176_K2_E5                                                             0x0002c0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X177_K2_E5                                                             0x0002c4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X178_K2_E5                                                             0x0002c8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X179_K2_E5                                                             0x0002ccUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X180_K2_E5                                                             0x0002d0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X181_K2_E5                                                             0x0002d4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X182_K2_E5                                                             0x0002d8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X183_K2_E5                                                             0x0002dcUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X184_K2_E5                                                             0x0002e0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X185_K2_E5                                                             0x0002e4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X186_K2_E5                                                             0x0002e8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X187_K2_E5                                                             0x0002ecUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X188_K2_E5                                                             0x0002f0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_K2_E5                                                             0x0002fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_IDDQ_BIAS_IDDQ_SETVAL_O_K2_E5                                   (0x1<<0) // MSM Function IDDQ mode default value for iddq_bias
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_IDDQ_BIAS_IDDQ_SETVAL_O_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_BIAS_IDDQ_SETVAL_O_K2_E5                                     (0x1<<1) // MSM Function IDDQ mode default value for pd_bias
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_BIAS_IDDQ_SETVAL_O_K2_E5_SHIFT                               1
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_RESET_TXCLK_PCS_CLK_IDDQ_SETVAL_O_K2_E5                         (0x1<<2) // MSM Function IDDQ mode default value for pcs_clk_ena
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_RESET_TXCLK_PCS_CLK_IDDQ_SETVAL_O_K2_E5_SHIFT                   2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_CMU_IDDQ_SETVAL_O_K2_E5                                      (0x1<<3) // MSM Function IDDQ mode default value for pd_cmu
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_CMU_IDDQ_SETVAL_O_K2_E5_SHIFT                                3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_CMUREG_IDDQ_SETVAL_O_K2_E5                                   (0x1<<4) // MSM Function IDDQ mode default value for pd_cmureg
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_CMUREG_IDDQ_SETVAL_O_K2_E5_SHIFT                             4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_CMUREGREF_IDDQ_SETVAL_O_K2_E5                                (0x1<<5) // MSM Function IDDQ mode default value for pd_cmuregref
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_CMUREGREF_IDDQ_SETVAL_O_K2_E5_SHIFT                          5
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_REF_IDDQ_SETVAL_O_K2_E5                                      (0x1<<6) // MSM Function IDDQ mode default value for pd_ref
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_REF_IDDQ_SETVAL_O_K2_E5_SHIFT                                6
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_RESET_CMU_FL_IDDQ_SETVAL_O_K2_E5                                (0x1<<7) // MSM Function IDDQ mode default value for reset_cmu_fl
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_RESET_CMU_FL_IDDQ_SETVAL_O_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_K2_E5                                                             0x000300UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMU_IDDQ_SETVAL_O_K2_E5                                   (0x1<<0) // MSM Function IDDQ mode default value for reset_cmu
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMU_IDDQ_SETVAL_O_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMU_GCRX_IDDQ_SETVAL_O_K2_E5                              (0x1<<1) // MSM Function IDDQ mode default value for reset_cmu_gcrx
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMU_GCRX_IDDQ_SETVAL_O_K2_E5_SHIFT                        1
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUREG_IDDQ_SETVAL_O_K2_E5                                (0x1<<2) // MSM Function IDDQ mode default value for reset_cmureg
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUREG_IDDQ_SETVAL_O_K2_E5_SHIFT                          2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUREGREF_IDDQ_SETVAL_O_K2_E5                             (0x1<<3) // MSM Function IDDQ mode default value for reset_cmuregref
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUREGREF_IDDQ_SETVAL_O_K2_E5_SHIFT                       3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUSYNTH_IDDQ_SETVAL_O_K2_E5                              (0x1<<4) // MSM Function IDDQ mode default value for reset_cmusynth
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUSYNTH_IDDQ_SETVAL_O_K2_E5_SHIFT                        4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUVCO_IDDQ_SETVAL_O_K2_E5                                (0x1<<5) // MSM Function IDDQ mode default value for reset_cmuvco
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUVCO_IDDQ_SETVAL_O_K2_E5_SHIFT                          5
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_LF_EXTZERO_ENA_IDDQ_SETVAL_O_K2_E5                              (0x1<<6) // MSM Function IDDQ mode default value for lf_extzero_ena
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_LF_EXTZERO_ENA_IDDQ_SETVAL_O_K2_E5_SHIFT                        6
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_LFI_EXTZERO_IDDQ_SETVAL_O_K2_E5                                 (0x1<<7) // MSM Function IDDQ mode default value for lfi_extzero
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_LFI_EXTZERO_IDDQ_SETVAL_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_K2_E5                                                             0x000304UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_SOC_CLK_EN_IDDQ_SETVAL_O_K2_E5                                  (0x1<<0) // MSM Function IDDQ mode default value for soc_clk_en
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_SOC_CLK_EN_IDDQ_SETVAL_O_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_REFCLK_EN_IDDQ_SETVAL_O_K2_E5                                   (0x1<<1) // MSM Function IDDQ mode default value for refclk_en
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_REFCLK_EN_IDDQ_SETVAL_O_K2_E5_SHIFT                             1
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_PLL_LOCK_EN_IDDQ_SETVAL_O_K2_E5                                 (0x1<<2) // MSM Function IDDQ mode default value for pll_lock_en
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_PLL_LOCK_EN_IDDQ_SETVAL_O_K2_E5_SHIFT                           2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_RESET_TXCLK_IDDQ_SETVAL_O_K2_E5                                 (0x1<<3) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_RESET_TXCLK_IDDQ_SETVAL_O_K2_E5_SHIFT                           3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_RESET_CLKDIV_IDDQ_SETVAL_O_K2_E5                                (0x1<<4) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_RESET_CLKDIV_IDDQ_SETVAL_O_K2_E5_SHIFT                          4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_IDDQ_SETVAL_O_K2_E5                                   (0x1<<5) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_IDDQ_SETVAL_O_K2_E5_SHIFT                             5
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_REFCLK_LEFT_IDDQ_SETVAL_O_K2_E5                       (0x1<<6) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_REFCLK_LEFT_IDDQ_SETVAL_O_K2_E5_SHIFT                 6
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_REFCLK_RIGHT_IDDQ_SETVAL_O_K2_E5                      (0x1<<7) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_REFCLK_RIGHT_IDDQ_SETVAL_O_K2_E5_SHIFT                7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_K2_E5                                                             0x000308UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_IDDQ_BIAS_RST_SETVAL_O_K2_E5                                    (0x1<<0) // MSM Function RST mode default value for iddq_bias
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_IDDQ_BIAS_RST_SETVAL_O_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_BIAS_RST_SETVAL_O_K2_E5                                      (0x1<<1) // MSM Function RST mode default value for pd_bias
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_BIAS_RST_SETVAL_O_K2_E5_SHIFT                                1
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_RESET_TXCLK_PCS_CLK_RST_SETVAL_O_K2_E5                          (0x1<<2) // MSM Function RST mode default value for pcs_clk_ena
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_RESET_TXCLK_PCS_CLK_RST_SETVAL_O_K2_E5_SHIFT                    2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_CMU_RST_SETVAL_O_K2_E5                                       (0x1<<3) // MSM Function RST mode default value for pd_cmu
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_CMU_RST_SETVAL_O_K2_E5_SHIFT                                 3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_CMUREG_RST_SETVAL_O_K2_E5                                    (0x1<<4) // MSM Function RST mode default value for pd_cmureg
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_CMUREG_RST_SETVAL_O_K2_E5_SHIFT                              4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_CMUREGREF_RST_SETVAL_O_K2_E5                                 (0x1<<5) // MSM Function RST mode default value for pd_cmuregref
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_CMUREGREF_RST_SETVAL_O_K2_E5_SHIFT                           5
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_REF_RST_SETVAL_O_K2_E5                                       (0x1<<6) // MSM Function RST mode default value for pd_ref
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_REF_RST_SETVAL_O_K2_E5_SHIFT                                 6
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_RESET_CMU_FL_RST_SETVAL_O_K2_E5                                 (0x1<<7) // MSM Function RST mode default value for reset_cmu_fl
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_RESET_CMU_FL_RST_SETVAL_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_K2_E5                                                             0x00030cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMU_RST_SETVAL_O_K2_E5                                    (0x1<<0) // MSM Function RST mode default value for reset_cmu
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMU_RST_SETVAL_O_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMU_GCRX_RST_SETVAL_O_K2_E5                               (0x1<<1) // MSM Function RST mode default value for reset_cmu_gcrx
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMU_GCRX_RST_SETVAL_O_K2_E5_SHIFT                         1
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUREG_RST_SETVAL_O_K2_E5                                 (0x1<<2) // MSM Function RST mode default value for reset_cmureg
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUREG_RST_SETVAL_O_K2_E5_SHIFT                           2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUREGREF_RST_SETVAL_O_K2_E5                              (0x1<<3) // MSM Function RST mode default value for reset_cmuregref
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUREGREF_RST_SETVAL_O_K2_E5_SHIFT                        3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUSYNTH_RST_SETVAL_O_K2_E5                               (0x1<<4) // MSM Function RST mode default value for reset_cmusynth
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUSYNTH_RST_SETVAL_O_K2_E5_SHIFT                         4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUVCO_RST_SETVAL_O_K2_E5                                 (0x1<<5) // MSM Function RST mode default value for reset_cmuvco
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUVCO_RST_SETVAL_O_K2_E5_SHIFT                           5
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_LF_EXTZERO_ENA_RST_SETVAL_O_K2_E5                               (0x1<<6) // MSM Function RST mode default value for lf_extzero_ena
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_LF_EXTZERO_ENA_RST_SETVAL_O_K2_E5_SHIFT                         6
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_LFI_EXTZERO_RST_SETVAL_O_K2_E5                                  (0x1<<7) // MSM Function RST mode default value for lfi_extzero
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_LFI_EXTZERO_RST_SETVAL_O_K2_E5_SHIFT                            7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_K2_E5                                                             0x000310UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_SOC_CLK_EN_RST_SETVAL_O_K2_E5                                   (0x1<<0) // MSM Function RST mode default value for soc_clk_en
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_SOC_CLK_EN_RST_SETVAL_O_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_REFCLK_EN_RST_SETVAL_O_K2_E5                                    (0x1<<1) // MSM Function RST mode default value for refclk_en
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_REFCLK_EN_RST_SETVAL_O_K2_E5_SHIFT                              1
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_PLL_LOCK_EN_RST_SETVAL_O_K2_E5                                  (0x1<<2) // MSM Function RST mode default value for pll_lock_en
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_PLL_LOCK_EN_RST_SETVAL_O_K2_E5_SHIFT                            2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_RESET_TXCLK_RST_SETVAL_O_K2_E5                                  (0x1<<3) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_RESET_TXCLK_RST_SETVAL_O_K2_E5_SHIFT                            3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_RESET_CLKDIV_RST_SETVAL_O_K2_E5                                 (0x1<<4) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_RESET_CLKDIV_RST_SETVAL_O_K2_E5_SHIFT                           4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_RST_SETVAL_O_K2_E5                                    (0x1<<5) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_RST_SETVAL_O_K2_E5_SHIFT                              5
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_REFCLK_LEFT_RST_SETVAL_O_K2_E5                        (0x1<<6) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_REFCLK_LEFT_RST_SETVAL_O_K2_E5_SHIFT                  6
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_REFCLK_RIGHT_RST_SETVAL_O_K2_E5                       (0x1<<7) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_REFCLK_RIGHT_RST_SETVAL_O_K2_E5_SHIFT                 7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_K2_E5                                                             0x000314UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_IDDQ_BIAS_NORM_SETVAL_O_K2_E5                                   (0x1<<0) // MSM Function NORMAL mode default value for iddq_bias
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_IDDQ_BIAS_NORM_SETVAL_O_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_BIAS_NORM_SETVAL_O_K2_E5                                     (0x1<<1) // MSM Function NORMAL mode default value for pd_bias
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_BIAS_NORM_SETVAL_O_K2_E5_SHIFT                               1
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_RESET_TXCLK_PCS_CLK_NORM_SETVAL_O_K2_E5                         (0x1<<2) // MSM Function NORMAL mode default value for pcs_clk_ena
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_RESET_TXCLK_PCS_CLK_NORM_SETVAL_O_K2_E5_SHIFT                   2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_CMU_NORM_SETVAL_O_K2_E5                                      (0x1<<3) // MSM Function NORMAL mode default value for pd_cmu
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_CMU_NORM_SETVAL_O_K2_E5_SHIFT                                3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_CMUREG_NORM_SETVAL_O_K2_E5                                   (0x1<<4) // MSM Function NORMAL mode default value for pd_cmureg
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_CMUREG_NORM_SETVAL_O_K2_E5_SHIFT                             4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_CMUREGREF_NORM_SETVAL_O_K2_E5                                (0x1<<5) // MSM Function NORMAL mode default value for pd_cmuregref
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_CMUREGREF_NORM_SETVAL_O_K2_E5_SHIFT                          5
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_REF_NORM_SETVAL_O_K2_E5                                      (0x1<<6) // MSM Function NORMAL mode default value for pd_ref
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_REF_NORM_SETVAL_O_K2_E5_SHIFT                                6
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_RESET_CMU_FL_NORM_SETVAL_O_K2_E5                                (0x1<<7) // MSM Function NORMAL mode default value for reset_cmu_fl
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_RESET_CMU_FL_NORM_SETVAL_O_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_K2_E5                                                             0x000318UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMU_NORM_SETVAL_O_K2_E5                                   (0x1<<0) // MSM Function NORMAL mode default value for reset_cmu
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMU_NORM_SETVAL_O_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMU_GCRX_NORM_SETVAL_O_K2_E5                              (0x1<<1) // MSM Function NORMAL mode default value for reset_cmu_gcrx
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMU_GCRX_NORM_SETVAL_O_K2_E5_SHIFT                        1
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUREG_NORM_SETVAL_O_K2_E5                                (0x1<<2) // MSM Function NORMAL mode default value for reset_cmureg
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUREG_NORM_SETVAL_O_K2_E5_SHIFT                          2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUREGREF_NORM_SETVAL_O_K2_E5                             (0x1<<3) // MSM Function NORMAL mode default value for reset_cmuregref
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUREGREF_NORM_SETVAL_O_K2_E5_SHIFT                       3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUSYNTH_NORM_SETVAL_O_K2_E5                              (0x1<<4) // MSM Function NORMAL mode default value for reset_cmusynth
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUSYNTH_NORM_SETVAL_O_K2_E5_SHIFT                        4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUVCO_NORM_SETVAL_O_K2_E5                                (0x1<<5) // MSM Function NORMAL mode default value for reset_cmuvco
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUVCO_NORM_SETVAL_O_K2_E5_SHIFT                          5
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_LF_EXTZERO_ENA_NORM_SETVAL_O_K2_E5                              (0x1<<6) // MSM Function NORMAL mode default value for lf_extzero_ena
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_LF_EXTZERO_ENA_NORM_SETVAL_O_K2_E5_SHIFT                        6
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_LFI_EXTZERO_NORM_SETVAL_O_K2_E5                                 (0x1<<7) // MSM Function NORMAL mode default value for lfi_extzero
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_LFI_EXTZERO_NORM_SETVAL_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_K2_E5                                                             0x00031cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_SOC_CLK_EN_NORM_SETVAL_O_K2_E5                                  (0x1<<0) // MSM Function NORMAL mode default value for soc_clk_en
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_SOC_CLK_EN_NORM_SETVAL_O_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_REFCLK_EN_NORM_SETVAL_O_K2_E5                                   (0x1<<1) // MSM Function NORMAL mode default value for refclk_en
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_REFCLK_EN_NORM_SETVAL_O_K2_E5_SHIFT                             1
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_PLL_LOCK_EN_NORM_SETVAL_O_K2_E5                                 (0x1<<2) // MSM Function NORMAL mode default value for pll_lock_en
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_PLL_LOCK_EN_NORM_SETVAL_O_K2_E5_SHIFT                           2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_RESET_TXCLK_NORM_SETVAL_O_K2_E5                                 (0x1<<3) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_RESET_TXCLK_NORM_SETVAL_O_K2_E5_SHIFT                           3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_RESET_CLKDIV_NORM_SETVAL_O_K2_E5                                (0x1<<4) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_RESET_CLKDIV_NORM_SETVAL_O_K2_E5_SHIFT                          4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_NORM_SETVAL_O_K2_E5                                   (0x1<<5) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_NORM_SETVAL_O_K2_E5_SHIFT                             5
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_REFCLK_LEFT_NORM_SETVAL_O_K2_E5                       (0x1<<6) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_REFCLK_LEFT_NORM_SETVAL_O_K2_E5_SHIFT                 6
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_REFCLK_RIGHT_NORM_SETVAL_O_K2_E5                      (0x1<<7) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_REFCLK_RIGHT_NORM_SETVAL_O_K2_E5_SHIFT                7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_K2_E5                                                             0x000320UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_IDDQ_BIAS_PD_SETVAL_O_K2_E5                                     (0x1<<0) // MSM Function POWER DOWN mode default value for iddq_bias
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_IDDQ_BIAS_PD_SETVAL_O_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_BIAS_PD_SETVAL_O_K2_E5                                       (0x1<<1) // MSM Function POWER DOWN mode default value for pd_bias
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_BIAS_PD_SETVAL_O_K2_E5_SHIFT                                 1
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_RESET_TXCLK_PCS_CLK_PD_SETVAL_O_K2_E5                           (0x1<<2) // MSM Function POWER DOWN mode default value for pcs_clk_ena
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_RESET_TXCLK_PCS_CLK_PD_SETVAL_O_K2_E5_SHIFT                     2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_CMU_PD_SETVAL_O_K2_E5                                        (0x1<<3) // MSM Function POWER DOWN mode default value for pd_cmu
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_CMU_PD_SETVAL_O_K2_E5_SHIFT                                  3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_CMUREG_PD_SETVAL_O_K2_E5                                     (0x1<<4) // MSM Function POWER DOWN mode default value for pd_cmureg
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_CMUREG_PD_SETVAL_O_K2_E5_SHIFT                               4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_CMUREGREF_PD_SETVAL_O_K2_E5                                  (0x1<<5) // MSM Function POWER DOWN mode default value for pd_cmuregref
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_CMUREGREF_PD_SETVAL_O_K2_E5_SHIFT                            5
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_REF_PD_SETVAL_O_K2_E5                                        (0x1<<6) // MSM Function POWER DOWN mode default value for pd_ref
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_REF_PD_SETVAL_O_K2_E5_SHIFT                                  6
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_RESET_CMU_FL_PD_SETVAL_O_K2_E5                                  (0x1<<7) // MSM Function POWER DOWN mode default value for reset_cmu_fl
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_RESET_CMU_FL_PD_SETVAL_O_K2_E5_SHIFT                            7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_K2_E5                                                             0x000324UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMU_PD_SETVAL_O_K2_E5                                     (0x1<<0) // MSM Function POWER DOWN mode default value for reset_cmu
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMU_PD_SETVAL_O_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMU_GCRX_PD_SETVAL_O_K2_E5                                (0x1<<1) // MSM Function POWER DOWN mode default value for reset_cmu_gcrx
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMU_GCRX_PD_SETVAL_O_K2_E5_SHIFT                          1
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUREG_PD_SETVAL_O_K2_E5                                  (0x1<<2) // MSM Function POWER DOWN mode default value for reset_cmureg
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUREG_PD_SETVAL_O_K2_E5_SHIFT                            2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUREGREF_PD_SETVAL_O_K2_E5                               (0x1<<3) // MSM Function POWER DOWN mode default value for reset_cmuregref
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUREGREF_PD_SETVAL_O_K2_E5_SHIFT                         3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUSYNTH_PD_SETVAL_O_K2_E5                                (0x1<<4) // MSM Function POWER DOWN mode default value for reset_cmusynth
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUSYNTH_PD_SETVAL_O_K2_E5_SHIFT                          4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUVCO_PD_SETVAL_O_K2_E5                                  (0x1<<5) // MSM Function POWER DOWN mode default value for reset_cmuvco
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUVCO_PD_SETVAL_O_K2_E5_SHIFT                            5
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_LF_EXTZERO_ENA_PD_SETVAL_O_K2_E5                                (0x1<<6) // MSM Function POWER DOWN mode default value for lf_extzero_ena
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_LF_EXTZERO_ENA_PD_SETVAL_O_K2_E5_SHIFT                          6
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_LFI_EXTZERO_PD_SETVAL_O_K2_E5                                   (0x1<<7) // MSM Function POWER DOWN mode default value for lfi_extzero
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_LFI_EXTZERO_PD_SETVAL_O_K2_E5_SHIFT                             7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_K2_E5                                                             0x000328UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_SOC_CLK_EN_PD_SETVAL_O_K2_E5                                    (0x1<<0) // MSM Function POWER DOWN mode default value for soc_clk_en
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_SOC_CLK_EN_PD_SETVAL_O_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_REFCLK_EN_PD_SETVAL_O_K2_E5                                     (0x1<<1) // MSM Function POWER DOWN mode default value for refclk_en
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_REFCLK_EN_PD_SETVAL_O_K2_E5_SHIFT                               1
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_PLL_LOCK_EN_PD_SETVAL_O_K2_E5                                   (0x1<<2) // MSM Function POWER DOWN mode default value for pll_lock_en
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_PLL_LOCK_EN_PD_SETVAL_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_RESET_TXCLK_PD_SETVAL_O_K2_E5                                   (0x1<<3) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_RESET_TXCLK_PD_SETVAL_O_K2_E5_SHIFT                             3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_RESET_CLKDIV_PD_SETVAL_O_K2_E5                                  (0x1<<4) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_RESET_CLKDIV_PD_SETVAL_O_K2_E5_SHIFT                            4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_PD_SETVAL_O_K2_E5                                     (0x1<<5) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_PD_SETVAL_O_K2_E5_SHIFT                               5
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_REFCLK_LEFT_PD_SETVAL_O_K2_E5                         (0x1<<6) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_REFCLK_LEFT_PD_SETVAL_O_K2_E5_SHIFT                   6
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_REFCLK_RIGHT_PD_SETVAL_O_K2_E5                        (0x1<<7) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_REFCLK_RIGHT_PD_SETVAL_O_K2_E5_SHIFT                  7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_K2_E5                                                             0x00032cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_IDDQ_BIAS_NORM_REFCLK_SETVAL_O_K2_E5                            (0x1<<0) // MSM Function NORM REFCLK mode default value for iddq_bias
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_IDDQ_BIAS_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT                      0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_BIAS_NORM_REFCLK_SETVAL_O_K2_E5                              (0x1<<1) // MSM Function NORM REFCLK mode default value for pd_bias
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_BIAS_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT                        1
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_RESET_TXCLK_PCS_CLK_NORM_REFCLK_SETVAL_O_K2_E5                  (0x1<<2) // MSM Function NORM REFCLK mode default value for pcs_clk_ena
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_RESET_TXCLK_PCS_CLK_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT            2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_CMU_NORM_REFCLK_SETVAL_O_K2_E5                               (0x1<<3) // MSM Function NORM REFCLK mode default value for pd_cmu
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_CMU_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT                         3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_CMUREG_NORM_REFCLK_SETVAL_O_K2_E5                            (0x1<<4) // MSM Function NORM REFCLK mode default value for pd_cmureg
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_CMUREG_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT                      4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_CMUREGREF_NORM_REFCLK_SETVAL_O_K2_E5                         (0x1<<5) // MSM Function NORM REFCLK mode default value for pd_cmuregref
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_CMUREGREF_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT                   5
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_REF_NORM_REFCLK_SETVAL_O_K2_E5                               (0x1<<6) // MSM Function NORM REFCLK mode default value for pd_ref
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_REF_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT                         6
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_RESET_CMU_FL_NORM_REFCLK_SETVAL_O_K2_E5                         (0x1<<7) // MSM Function NORM REFCLK mode default value for reset_cmu_fl
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_RESET_CMU_FL_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT                   7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_K2_E5                                                             0x000330UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMU_NORM_REFCLK_SETVAL_O_K2_E5                            (0x1<<0) // MSM Function NORM REFCLK mode default value for reset_cmu
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMU_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT                      0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMU_GCRX_NORM_REFCLK_SETVAL_O_K2_E5                       (0x1<<1) // MSM Function NORM REFCLK mode default value for reset_cmu_gcrx
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMU_GCRX_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT                 1
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMUREG_NORM_REFCLK_SETVAL_O_K2_E5                         (0x1<<2) // MSM Function NORM REFCLK mode default value for reset_cmureg
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMUREG_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT                   2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMUREGREF_NORM_REFCLK_SETVAL_O_K2_E5                      (0x1<<3) // MSM Function NORM REFCLK mode default value for reset_cmuregref
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMUREGREF_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT                3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMUSYNTH_NORM_REFCLK_SETVAL_O_K2_E5                       (0x1<<4) // MSM Function NORM REFCLK mode default value for reset_cmusynth
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMUSYNTH_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT                 4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMUVCO_NORM_REFCLK_SETVAL_O_K2_E5                         (0x1<<5) // MSM Function NORM REFCLK mode default value for reset_cmuvco
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMUVCO_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT                   5
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_LF_EXTZERO_ENA_NORM_REFCLK_SETVAL_O_K2_E5                       (0x1<<6) // MSM Function NORM REFCLK mode default value for lf_extzero_ena
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_LF_EXTZERO_ENA_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT                 6
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_LFI_EXTZERO_NORM_REFCLK_SETVAL_O_K2_E5                          (0x1<<7) // MSM Function NORM REFCLK mode default value for lfi_extzero
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_LFI_EXTZERO_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT                    7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_K2_E5                                                             0x000334UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_SOC_CLK_EN_NORM_REFCLK_SETVAL_O_K2_E5                           (0x1<<0) // MSM Function NORM REFCLK mode default value for soc_clk_en
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_SOC_CLK_EN_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT                     0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_REFCLK_EN_NORM_REFCLK_SETVAL_O_K2_E5                            (0x1<<1) // MSM Function NORM REFCLK mode default value for refclk_en
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_REFCLK_EN_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT                      1
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_PLL_LOCK_EN_NORM_REFCLK_SETVAL_O_K2_E5                          (0x1<<2) // MSM Function NORM REFCLK mode default value for pll_lock_en
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_PLL_LOCK_EN_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT                    2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_RESET_TXCLK_NORM_REFCLK_SETVAL_O_K2_E5                          (0x1<<3) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_RESET_TXCLK_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT                    3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_RESET_CLKDIV_NORM_REFCLK_SETVAL_O_K2_E5                         (0x1<<4) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_RESET_CLKDIV_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT                   4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_PD_CLKDIV_NORM_REFCLK_SETVAL_O_K2_E5                            (0x1<<5) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_PD_CLKDIV_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT                      5
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_PD_CLKDIV_REFCLK_LEFT_NORM_REFCLK_SETVAL_O_K2_E5                (0x1<<6) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_PD_CLKDIV_REFCLK_LEFT_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT          6
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_PD_CLKDIV_REFCLK_RIGHT_NORM_REFCLK_SETVAL_O_K2_E5               (0x1<<7) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_PD_CLKDIV_REFCLK_RIGHT_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT         7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_K2_E5                                                             0x000338UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_IDDQ_BIAS_P1_2_SETVAL_O_K2_E5                                   (0x1<<0) // MSM Function P1_2 mode default value for iddq_bias
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_IDDQ_BIAS_P1_2_SETVAL_O_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_BIAS_P1_2_SETVAL_O_K2_E5                                     (0x1<<1) // MSM Function P1_2 mode default value for pd_bias
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_BIAS_P1_2_SETVAL_O_K2_E5_SHIFT                               1
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_RESET_TXCLK_PCS_CLK_P1_2_SETVAL_O_K2_E5                         (0x1<<2) // MSM Function P1_2 mode default value for pcs_clk_ena
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_RESET_TXCLK_PCS_CLK_P1_2_SETVAL_O_K2_E5_SHIFT                   2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_CMU_P1_2_SETVAL_O_K2_E5                                      (0x1<<3) // MSM Function P1_2 mode default value for pd_cmu
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_CMU_P1_2_SETVAL_O_K2_E5_SHIFT                                3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_CMUREG_P1_2_SETVAL_O_K2_E5                                   (0x1<<4) // MSM Function P1_2 mode default value for pd_cmureg
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_CMUREG_P1_2_SETVAL_O_K2_E5_SHIFT                             4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_CMUREGREF_P1_2_SETVAL_O_K2_E5                                (0x1<<5) // MSM Function P1_2 mode default value for pd_cmuregref
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_CMUREGREF_P1_2_SETVAL_O_K2_E5_SHIFT                          5
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_REF_P1_2_SETVAL_O_K2_E5                                      (0x1<<6) // MSM Function P1_2 mode default value for pd_ref
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_REF_P1_2_SETVAL_O_K2_E5_SHIFT                                6
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_RESET_CMU_FL_P1_2_SETVAL_O_K2_E5                                (0x1<<7) // MSM Function P1_2 mode default value for reset_cmu_fl
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_RESET_CMU_FL_P1_2_SETVAL_O_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_K2_E5                                                             0x00033cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMU_P1_2_SETVAL_O_K2_E5                                   (0x1<<0) // MSM Function P1_2 mode default value for reset_cmu
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMU_P1_2_SETVAL_O_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMU_GCRX_P1_2_SETVAL_O_K2_E5                              (0x1<<1) // MSM Function P1_2 mode default value for reset_cmu_gcrx
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMU_GCRX_P1_2_SETVAL_O_K2_E5_SHIFT                        1
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMUREG_P1_2_SETVAL_O_K2_E5                                (0x1<<2) // MSM Function P1_2 mode default value for reset_cmureg
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMUREG_P1_2_SETVAL_O_K2_E5_SHIFT                          2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMUREGREF_P1_2_SETVAL_O_K2_E5                             (0x1<<3) // MSM Function P1_2 mode default value for reset_cmuregref
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMUREGREF_P1_2_SETVAL_O_K2_E5_SHIFT                       3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMUSYNTH_P1_2_SETVAL_O_K2_E5                              (0x1<<4) // MSM Function P1_2 mode default value for reset_cmusynth
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMUSYNTH_P1_2_SETVAL_O_K2_E5_SHIFT                        4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMUVCO_P1_2_SETVAL_O_K2_E5                                (0x1<<5) // MSM Function P1_2 mode default value for reset_cmuvco
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMUVCO_P1_2_SETVAL_O_K2_E5_SHIFT                          5
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_LF_EXTZERO_ENA_P1_2_SETVAL_O_K2_E5                              (0x1<<6) // MSM Function P1_2 mode default value for lf_extzero_ena
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_LF_EXTZERO_ENA_P1_2_SETVAL_O_K2_E5_SHIFT                        6
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_LFI_EXTZERO_P1_2_SETVAL_O_K2_E5                                 (0x1<<7) // MSM Function P1_2 mode default value for lfi_extzero
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_LFI_EXTZERO_P1_2_SETVAL_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_K2_E5                                                             0x000340UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_SOC_CLK_EN_P1_2_SETVAL_O_K2_E5                                  (0x1<<0) // MSM Function P1_2 mode default value for soc_clk_en
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_SOC_CLK_EN_P1_2_SETVAL_O_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_REFCLK_EN_P1_2_SETVAL_O_K2_E5                                   (0x1<<1) // MSM Function P1_2 mode default value for refclk_en
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_REFCLK_EN_P1_2_SETVAL_O_K2_E5_SHIFT                             1
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_PLL_LOCK_EN_P1_2_SETVAL_O_K2_E5                                 (0x1<<2) // MSM Function P1_2 mode default value for pll_lock_en
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_PLL_LOCK_EN_P1_2_SETVAL_O_K2_E5_SHIFT                           2
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_RESET_TXCLK_P1_2_SETVAL_O_K2_E5                                 (0x1<<3) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_RESET_TXCLK_P1_2_SETVAL_O_K2_E5_SHIFT                           3
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_RESET_CLKDIV_P1_2_SETVAL_O_K2_E5                                (0x1<<4) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_RESET_CLKDIV_P1_2_SETVAL_O_K2_E5_SHIFT                          4
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_PD_CLKDIV_P1_2_SETVAL_O_K2_E5                                   (0x1<<5) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_PD_CLKDIV_P1_2_SETVAL_O_K2_E5_SHIFT                             5
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_PD_CLKDIV_REFCLK_LEFT_P1_2_SETVAL_O_K2_E5                       (0x1<<6) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_PD_CLKDIV_REFCLK_LEFT_P1_2_SETVAL_O_K2_E5_SHIFT                 6
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_PD_CLKDIV_REFCLK_RIGHT_P1_2_SETVAL_O_K2_E5                      (0x1<<7) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_PD_CLKDIV_REFCLK_RIGHT_P1_2_SETVAL_O_K2_E5_SHIFT                7
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X209_K2_E5                                                             0x000344UL //Access:RW   DataWidth:0x8    // Not used
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X210_K2_E5                                                             0x000348UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X210_AHB_P1_2_TO_NORM_REFCLK_GATE_DELAY_O_14_8_K2_E5                 (0x7f<<0) // Not used
+  #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X210_AHB_P1_2_TO_NORM_REFCLK_GATE_DELAY_O_14_8_K2_E5_SHIFT           0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X0_K2_E5                                                              0x000800UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O_K2_E5                                 (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X1_K2_E5                                                              0x000804UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O_K2_E5                                 (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O_K2_E5_SHIFT                           3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O_K2_E5                                 (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X2_K2_E5                                                              0x000808UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O_K2_E5                                 (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X3_K2_E5                                                              0x00080cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X3_PMA_CMU_SEL_O_0_K2_E5                                            (0x1<<0) // CMU Select for lane  0 -	 Select CMU0  1 -	 Select CMU1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X3_PMA_CMU_SEL_O_0_K2_E5_SHIFT                                      0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X3_PMA_TXCLK_SEL_O_1_K2_E5                                          (0x1<<1) // PMA TX Clock Select for TX CDR VCO  0 -	 CMU0 Clock  1 -	 CMU1 Clock
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X3_PMA_TXCLK_SEL_O_1_K2_E5_SHIFT                                    1
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X4_K2_E5                                                              0x000810UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X4_CDRCTRL_DIV_EN_O_1_0_K2_E5                                       (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Divide by 4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X4_CDRCTRL_DIV_EN_O_1_0_K2_E5_SHIFT                                 0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X4_GCFSM_DIV_EN_O_1_0_K2_E5                                         (0x3<<2) // Static divider control for Lane GCFSM clock The only access to this divider. Not an override 4d0:  No division  4d1:  /2 4d2:  /2 4d3:  /4:
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X4_GCFSM_DIV_EN_O_1_0_K2_E5_SHIFT                                   2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X4_LN_CLK_TXB_DIV24OR1_O_K2_E5                                      (0x3<<4) // Divide ratio setting for lnX_ck_txb_o. When ln_common_sync_txclk_en_o is high and in NORM state:                                            2'b00: lnX_ck_txb_o is divided by 1 version of the tx byte clock from PMA.                     2'b01/2'b10: lnX_ck_txb_o is divided by 2 version of the tx byte clock from PMA.                  2'b11: lnX_ck_txb_o is divided by 4 version of the tx byte clock from PMA.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X4_LN_CLK_TXB_DIV24OR1_O_K2_E5_SHIFT                                4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X4_AHB_CHNG_REQ_Z_O_K2_E5                                           (0x1<<6) // Not currently used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X4_AHB_CHNG_REQ_Z_O_K2_E5_SHIFT                                     6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X5_K2_E5                                                              0x000814UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X5_REF_CLK_DIV_EN_O_1_0_K2_E5                                       (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X5_REF_CLK_DIV_EN_O_1_0_K2_E5_SHIFT                                 0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X5_OOB_CLK_DIV_EN_O_1_0_K2_E5                                       (0x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X5_OOB_CLK_DIV_EN_O_1_0_K2_E5_SHIFT                                 2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_K2_E5                                                              0x00081cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_RATE_O_K2_E5                                                (0x3<<0) // Rate control for BIST
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_RATE_O_K2_E5_SHIFT                                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_MODE8B_O_K2_E5                                          (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Generated data word is 8 bits
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_MODE8B_O_K2_E5_SHIFT                                    2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_ERR_O_K2_E5                                             (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 - BIST generator outputs erroneous pattern.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_ERR_O_K2_E5_SHIFT                                       3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_TX_CLOCK_ENABLE_K2_E5                                       (0x1<<4) // Active HIGH clock enable signal for the BIST transmit clock
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_TX_CLOCK_ENABLE_K2_E5_SHIFT                                 4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_CDN_O_K2_E5                                             (0x1<<5) // Bist generator master reset.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_CDN_O_K2_E5_SHIFT                                       5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_WORD_O_K2_E5                                            (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 1 - Bist generator generates double word 16 or 20
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_WORD_O_K2_E5_SHIFT                                      6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_EN_O_K2_E5                                              (0x1<<7) // Bist generator enable.  0 - Bist generator idle. 1 - Bist generator generates data
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_EN_O_K2_E5_SHIFT                                        7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X8_K2_E5                                                              0x000820UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_CLK_SEL_O_2_0_K2_E5                                     (0x7<<0) // BIST Generation Clock Selection
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_CLK_SEL_O_2_0_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_SEND_PREAM_O_K2_E5                                      (0x1<<3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - Bist generator sends preamble.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_SEND_PREAM_O_K2_E5_SHIFT                                3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_INSERT_COUNT_O_2_0_K2_E5                                (0x7<<4) // Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is ever inserted into the stream. In 20-bit mode, the product of bist_gen_insert_length x bist_gen_insert_count must be even.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_INSERT_COUNT_O_2_0_K2_E5_SHIFT                          4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X9_K2_E5                                                              0x000824UL //Access:RW   DataWidth:0x8    // Bist generator low-period control. If not 0, output data enable will be low for this number of words, and then high for en_high_i_X:0 number of words, repeating. If 0, data output enable will be asserted for entire test.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X10_K2_E5                                                             0x000828UL //Access:RW   DataWidth:0x8    // Bist generator low-period control. If not 0, output data enable will be low for this number of words, and then high for en_high_i_X:0 number of words, repeating. If 0, data output enable will be asserted for entire test.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X11_K2_E5                                                             0x00082cUL //Access:RW   DataWidth:0x8    // Bist generator high-period control. Refer to bist_gen_en_low_o and BIST documentation for further information.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X12_K2_E5                                                             0x000830UL //Access:RW   DataWidth:0x8    // Bist generator high-period control. Refer to bist_gen_en_low_o and BIST documentation for further information.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X13_K2_E5                                                             0x000834UL //Access:RW   DataWidth:0x8    // Bist generator - Number of words between insert word insertions. Insertions are done in both pream and data transmission. In 20-bit mode, this number must be even.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X14_K2_E5                                                             0x000838UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X14_BIST_GEN_INSERT_DELAY_O_11_8_K2_E5                              (0xf<<0) // Bist generator - Number of words between insert word insertions. Insertions are done in both pream and data transmission. In 20-bit mode, this number must be even.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X14_BIST_GEN_INSERT_DELAY_O_11_8_K2_E5_SHIFT                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X14_BCHK_EN_O_K2_E5                                                 (0x1<<5) // BIST checker enable Enables BIST RX Control block, which enables the actual BIST RX block when appropriate
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X14_BCHK_EN_O_K2_E5_SHIFT                                           5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X14_BCHK_CLR_O_K2_E5                                                (0x1<<6) // BIST checker clear signal. Zeroes error counter output. Does NOT go through the RX BIST control block
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X14_BCHK_CLR_O_K2_E5_SHIFT                                          6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_K2_E5                                                             0x00083cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_BCHK_SRC_O_1_0_K2_E5                                            (0x3<<0) // BIST checker source. 0 - BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Aligner before Elastic Buffer 2 - BIST uses output of RX loopback mux before Decoder and Polbits 3 - BIST uses output of reg1 flop bank before Interface blocks
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_BCHK_SRC_O_1_0_K2_E5_SHIFT                                      0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_BIST_CHK_DATA_MODE_O_K2_E5                                      (0x1<<3) // Bist checker mode select. 0X0  UDP pattern. 0x1  PRBS pattern
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_BIST_CHK_DATA_MODE_O_K2_E5_SHIFT                                3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_BIST_CHK_LFSR_LENGTH_O_1_0_K2_E5                                (0x3<<4) // BIST PRBS pattern selector.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_BIST_CHK_LFSR_LENGTH_O_1_0_K2_E5_SHIFT                          4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_BIST_RX_CLOCK_ENABLE_K2_E5                                      (0x1<<7) // Active HIGH clock enable signal for the BIST receive clock
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_BIST_RX_CLOCK_ENABLE_K2_E5_SHIFT                                7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X16_K2_E5                                                             0x000840UL //Access:RW   DataWidth:0x8    // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This word should correspond to the alignment character used for the symbol alignment block.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X17_K2_E5                                                             0x000844UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_PREAM0_O_9_8_K2_E5                                     (0x3<<0) // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This word should correspond to the alignment character used for the symbol alignment block.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_PREAM0_O_9_8_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_INSERT_LENGTH_O_2_0_K2_E5                              (0x7<<2) // BIST Checker Insert word length.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_INSERT_LENGTH_O_2_0_K2_E5_SHIFT                        2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_SYNC_ON_ZEROS_K2_E5                                    (0x1<<5) // Setting this bit allows BIST to sync to RX value of zero
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_SYNC_ON_ZEROS_K2_E5_SHIFT                              5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X18_K2_E5                                                             0x000848UL //Access:RW   DataWidth:0x8    // BIST Check Preamble
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X19_K2_E5                                                             0x00084cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X19_BIST_CHK_PREAM1_O_9_8_K2_E5                                     (0x3<<0) // BIST Check Preamble
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X19_BIST_CHK_PREAM1_O_9_8_K2_E5_SHIFT                               0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X20_K2_E5                                                             0x000850UL //Access:RW   DataWidth:0x8    // Bist checker 40-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corresponds to 5 8-bit words. K code is assumed to be 0 in 8-bit mode.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X21_K2_E5                                                             0x000854UL //Access:RW   DataWidth:0x8    // BIST Check User-defined pattern
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X22_K2_E5                                                             0x000858UL //Access:RW   DataWidth:0x8    // BIST Check User-defined pattern
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X23_K2_E5                                                             0x00085cUL //Access:RW   DataWidth:0x8    // BIST Check User-defined pattern
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X24_K2_E5                                                             0x000860UL //Access:RW   DataWidth:0x8    // BIST Check User-defined pattern
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X25_K2_E5                                                             0x000864UL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X26_K2_E5                                                             0x000868UL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X27_K2_E5                                                             0x00086cUL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X28_K2_E5                                                             0x000870UL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X29_K2_E5                                                             0x000874UL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X30_K2_E5                                                             0x000878UL //Access:R    DataWidth:0x8    // Bist errors detected
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X31_K2_E5                                                             0x00087cUL //Access:R    DataWidth:0x8    // Bist errors detected
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X32_K2_E5                                                             0x000880UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 7-0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X33_K2_E5                                                             0x000884UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 15-8
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X34_K2_E5                                                             0x000888UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 23-16
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X35_K2_E5                                                             0x00088cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 31-24
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X36_K2_E5                                                             0x000890UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 39-32
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X37_K2_E5                                                             0x000894UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 47-40
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X38_K2_E5                                                             0x000898UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 55-48
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X39_K2_E5                                                             0x00089cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 63-56
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X40_K2_E5                                                             0x0008a0UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 71-64
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X41_K2_E5                                                             0x0008a4UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 79-72
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X42_K2_E5                                                             0x0008a8UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 87-80
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X43_K2_E5                                                             0x0008acUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 95-88
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X44_K2_E5                                                             0x0008b0UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 103-96
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X45_K2_E5                                                             0x0008b4UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 111-104
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X46_K2_E5                                                             0x0008b8UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 119-112
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X47_K2_E5                                                             0x0008bcUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 127-120
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X48_K2_E5                                                             0x0008c0UL //Access:RW   DataWidth:0x8    // Timing Window length for GCFSM for Gen 1/2 - for the new ICA method
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X49_K2_E5                                                             0x0008c4UL //Access:RW   DataWidth:0x8    // Timing Window length for GCFSM for Gen 3 - for the new ICA method
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X50_K2_E5                                                             0x0008c8UL //Access:RW   DataWidth:0x8    // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA method
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X51_K2_E5                                                             0x0008ccUL //Access:RW   DataWidth:0x8    // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA method
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X52_K2_E5                                                             0x0008d0UL //Access:RW   DataWidth:0x8    // The start length of DFE offset calibration's first cycle is the value of this register multiplied by 4.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X53_K2_E5                                                             0x0008d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_DFE_OFFSET_CAL_START_LEN_O_4_0_K2_E5                      (0x1f<<0) // The start length of DFE offset calibration, except for the 1st cycle.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_DFE_OFFSET_CAL_START_LEN_O_4_0_K2_E5_SHIFT                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2_K2_E5                               (0x1<<5) // COMLANE or LANE CSR Select for GCFSM Cycle Length registers  0 -	 Select COMLANE registers  1 -	 Select LANE registers
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2_K2_E5_SHIFT                         5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_LANE_TW_METHOD_EN_K2_E5                                   (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_LANE_TW_METHOD_EN_K2_E5_SHIFT                             6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_LANE_PMA_LOAD_OVR_K2_E5                                   (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_LANE_PMA_LOAD_OVR_K2_E5_SHIFT                             7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X54_K2_E5                                                             0x0008d8UL //Access:RW   DataWidth:0x8    // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X55_K2_E5                                                             0x0008dcUL //Access:RW   DataWidth:0x8    // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X56_K2_E5                                                             0x0008e0UL //Access:RW   DataWidth:0x8    // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_K2_E5                                                             0x0008e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_OVR_O_27_24_K2_E5                                         (0xf<<0) // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_OVR_O_27_24_K2_E5_SHIFT                                   0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_OUT_OVR_EN_O_K2_E5                                   (0x1<<4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes data stored in gcfsm_lane_pma_data_ovr_o to override calibration values for the block selected by gcfsm_lane_pma_cal_ovr_o.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_OUT_OVR_EN_O_K2_E5_SHIFT                             4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_LATCH_OVR_O_K2_E5                                (0x1<<5) // GCFSM pma_latch_o override
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_LATCH_OVR_O_K2_E5_SHIFT                          5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_GO_OVR_O_K2_E5                                   (0x1<<6) // GCFSM pma_go_o override
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_GO_OVR_O_K2_E5_SHIFT                             6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_READ_OVR_O_K2_E5                                 (0x1<<7) // GCFSM pma_read_o override.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_READ_OVR_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X58_K2_E5                                                             0x0008e8UL //Access:RW   DataWidth:0x8    // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X59_K2_E5                                                             0x0008ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X59_GCFSM_LANE_PMA_DATA_OVR_O_11_8_K2_E5                            (0xf<<0) // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X59_GCFSM_LANE_PMA_DATA_OVR_O_11_8_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X60_K2_E5                                                             0x0008f0UL //Access:RW   DataWidth:0x8    // General Calibration Finite State Machine GCFSM overide select, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA compone
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X61_K2_E5                                                             0x0008f4UL //Access:RW   DataWidth:0x8    // General Calibration Finite State Machine GCFSM overide select, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA compone
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X62_K2_E5                                                             0x0008f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X62_LN_MSM_REQ_IN_OVR_O_K2_E5                                       (0x3<<0) // Bit 0:  Override enable for msm_ln_req Bit 1 : Override msm_ln_req
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X62_LN_MSM_REQ_IN_OVR_O_K2_E5_SHIFT                                 0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X62_LN_MSM_FUNC_IN_OVR_O_K2_E5                                      (0x3f<<2) // Bit 2:  Override enable for msm_func Bits [7:3] : Override msm_func
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X62_LN_MSM_FUNC_IN_OVR_O_K2_E5_SHIFT                                2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X65_K2_E5                                                             0x000904UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X65_GCFSM_OVR_O_28_K2_E5                                            (0x1<<0) // Not currently used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X65_GCFSM_OVR_O_28_K2_E5_SHIFT                                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X66_K2_E5                                                             0x000908UL //Access:RW   DataWidth:0x8    // Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X67_K2_E5                                                             0x00090cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X67_CDR_CTRL_DLY_CDR_O_6_0_K2_E5                                    (0x7f<<0) // Number of clock cycles between signal detect indicator
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X67_CDR_CTRL_DLY_CDR_O_6_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_K2_E5                               (0x1<<7) // Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_K2_E5_SHIFT                         7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X68_K2_E5                                                             0x000910UL //Access:RW   DataWidth:0x8    // Number of clock cycles between CISEL assertion
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X69_K2_E5                                                             0x000914UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X69_CDR_CTRL_DLY_LANE_O_9_8_K2_E5                                   (0x3<<0) // Number of clock cycles between CISEL assertion
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X69_CDR_CTRL_DLY_LANE_O_9_8_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X69_CDR_CTRL_START_LEN_O_3_0_K2_E5                                  (0xf<<2) // Number of clock cycles between when CDR control block
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X69_CDR_CTRL_START_LEN_O_3_0_K2_E5_SHIFT                            2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X69_CDR_CTRL_INT_FIL_O_1_0_K2_E5                                    (0x3<<6) // CDR control DLPF positioning control.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X69_CDR_CTRL_INT_FIL_O_1_0_K2_E5_SHIFT                              6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X70_K2_E5                                                             0x000918UL //Access:RW   DataWidth:0x8    // CDR control block cycle length When not in PCIe Gen3.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X71_K2_E5                                                             0x00091cUL //Access:RW   DataWidth:0x8    // CDR control block cycle length When in PCIe Gen3.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X72_K2_E5                                                             0x000920UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X72_CDR_CTRL_MAX_DIFF_O_4_0_K2_E5                                   (0x1f<<0) // Maximum difference from DLPF center point.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X72_CDR_CTRL_MAX_DIFF_O_4_0_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X72_CDR_CTRL_MIN_BOUNCE_O_2_0_K2_E5                                 (0x7<<5) // Maximum difference from DLPF center point.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X72_CDR_CTRL_MIN_BOUNCE_O_2_0_K2_E5_SHIFT                           5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_K2_E5                                                             0x000924UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_CDR_CTRL_TW_METHOD_EN_K2_E5                                     (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_CDR_CTRL_TW_METHOD_EN_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_CDR_CONTROL_ATT_CTRL_O_K2_E5                                    (0x1<<1) // ATT wait control. Upon detection of signal, DFE ATT calibration is enabled, without CISEL being asserted to the CDR.  0 - CDR control block will wait for ATT calibration before proceeding 1 - CDR control block will not wait for ATT calibration
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_CDR_CONTROL_ATT_CTRL_O_K2_E5_SHIFT                              1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_RXEQ_WAIT_EN_O_K2_E5                                            (0x1<<2) // CDR control block wait for DFE signal.  0 - Do not wait for DFE calibration before enabling rx data 1 - Wait for DFE calibration before enabling rx data
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_RXEQ_WAIT_EN_O_K2_E5_SHIFT                                      2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_CDR_CTRL_DLY_CDR_O_9_7_K2_E5                                    (0x7<<3) // Number of clock cycles between signal detect indicator
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_CDR_CTRL_DLY_CDR_O_9_7_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X74_K2_E5                                                             0x000928UL //Access:RW   DataWidth:0x8    // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X75_K2_E5                                                             0x00092cUL //Access:RW   DataWidth:0x8    // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X76_K2_E5                                                             0x000930UL //Access:RW   DataWidth:0x8    // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X77_K2_E5                                                             0x000934UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X77_CDR_CTRL_OUT_OVR_O_29_24_K2_E5                                  (0x3f<<0) // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X77_CDR_CTRL_OUT_OVR_O_29_24_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X77_CDR_CTRL_CAL_LOAD_OVR_K2_E5                                     (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X77_CDR_CTRL_CAL_LOAD_OVR_K2_E5_SHIFT                               6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X78_K2_E5                                                             0x000938UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X78_SYM_ALIGN_ALIGN_POS_O_5_0_K2_E5                                 (0x3f<<0) // Symbol aligner position override enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X78_SYM_ALIGN_ALIGN_POS_O_5_0_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X78_SYM_ALIGN_MODE_O_1_0_K2_E5                                      (0x3<<6) // Symbol aligner mode select.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X78_SYM_ALIGN_MODE_O_1_0_K2_E5_SHIFT                                6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X79_K2_E5                                                             0x00093cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X79_SYM_ALIGN_BYPASS_O_K2_E5                                        (0x1<<0) // Asserting this register will bypass the symbol aligner
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X79_SYM_ALIGN_BYPASS_O_K2_E5_SHIFT                                  0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X80_K2_E5                                                             0x000940UL //Access:RW   DataWidth:0x8    // Number of cycles to wait before forcing exit form EI
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_K2_E5                                                             0x000944UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EXIT_TIMER_LEN_O_9_8_K2_E5                        (0x3<<0) // Number of cycles to wait before forcing exit form EI
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EXIT_TIMER_LEN_O_9_8_K2_E5_SHIFT                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_CLR_ERR_O_K2_E5                                   (0x1<<2) // Clears the elec idle control error flag
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_CLR_ERR_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EI_INFERRED_O_K2_E5                               (0x1<<3) // Override for ei_inferred signal
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EI_INFERRED_O_K2_E5_SHIFT                         3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O_K2_E5                            (0x1<<4) // Override for ei_mask signal
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O_K2_E5_SHIFT                      4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O_K2_E5                             (0x1<<5) // Override for ei_exit_type signal
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O_K2_E5_SHIFT                       5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_OVR_O_K2_E5                                       (0x1<<6) // EI control override enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_OVR_O_K2_E5_SHIFT                                 6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X82_K2_E5                                                             0x000948UL //Access:RW   DataWidth:0x8    // Number of cycles to wait before entering back into EI
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X83_K2_E5                                                             0x00094cUL //Access:RW   DataWidth:0x8    // Electrical Idle Control signal detect glitch filter counter
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X84_K2_E5                                                             0x000950UL //Access:RW   DataWidth:0x8    // Electrical Idle Control signal detect low filter min value
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X85_K2_E5                                                             0x000954UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X85_ELECIDLE_CTRL_LOCK_TIMER_LEN_O_9_8_K2_E5                        (0x3<<0) // Number of cycles to wait before entering back into EI
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X85_ELECIDLE_CTRL_LOCK_TIMER_LEN_O_9_8_K2_E5_SHIFT                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X85_ELECIDLE_CTRL_TIMER_LEN_SEL_O_1_0_K2_E5                         (0x3<<2) // EI Exit time cycles = timer_len_sel[1:0]+1*exit_timer_len_i[9:0]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X85_ELECIDLE_CTRL_TIMER_LEN_SEL_O_1_0_K2_E5_SHIFT                   2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X85_LOOPBACK_EN_O_K2_E5                                             (0x1<<4) // Control signal to force decoder into loopback mode
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X85_LOOPBACK_EN_O_K2_E5_SHIFT                                       4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X86_K2_E5                                                             0x000958UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X86_FES_LB_ENA_O_K2_E5                                              (0x1<<0) // FES loopback enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X86_FES_LB_ENA_O_K2_E5_SHIFT                                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X86_NES_LB_ENA_O_K2_E5                                              (0x1<<1) // NES loopback enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X86_NES_LB_ENA_O_K2_E5_SHIFT                                        1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X86_RXCLK_LB_ENA_O_K2_E5                                            (0x1<<2) // HS recovered clock to transmit loopback enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X86_RXCLK_LB_ENA_O_K2_E5_SHIFT                                      2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X87_K2_E5                                                             0x00095cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X87_AHB_PMA_LN_RX_BOOST_OVR_O_K2_E5                                 (0x1<<0) // RX boost override enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X87_AHB_PMA_LN_RX_BOOST_OVR_O_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_O_K2_E5                            (0x7f<<1) // RX boost override setting. Thermometer coded.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_O_K2_E5_SHIFT                      1
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X88_K2_E5                                                             0x000960UL //Access:RW   DataWidth:0x8    // RX boost override setting. Thermometer coded.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X89_K2_E5                                                             0x000964UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_SD_THSEL_DIV1_O_K2_E5                                (0x7<<0) // Signal detect threshold select for Full rate
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_SD_THSEL_DIV1_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_SD_THSEL_DIV2_O_K2_E5                                (0x7<<3) // Signal detect threshold select for div-by-2 rate
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_SD_THSEL_DIV2_O_K2_E5_SHIFT                          3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_RXUP_O_K2_E5                                         (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_RXUP_O_K2_E5_SHIFT                                   6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_K2_E5                                (0x1<<7) // RX FL calibration clock DIV4 enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X90_K2_E5                                                             0x000968UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_SD_THSEL_DIV4_O_K2_E5                                (0x7<<0) // Signal detect threshold select for div-by-4 rate
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_SD_THSEL_DIV4_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_AGC_THSEL_O_K2_E5                                    (0x7<<3) // AGC threshold select
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_AGC_THSEL_O_K2_E5_SHIFT                              3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_VREGH_O_K2_E5                                        (0x3<<6) // Regulator VREGH setting
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_VREGH_O_K2_E5_SHIFT                                  6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X91_K2_E5                                                             0x00096cUL //Access:RW   DataWidth:0x8    // RX FL calibration LDHS
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X92_K2_E5                                                             0x000970UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_RXFL_LDHS_9_8_O_K2_E5                                (0x3<<0) // RX FL calibration LDHS
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_RXFL_LDHS_9_8_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_RXVCO_BIAS_O_K2_E5                                   (0xf<<2) // CDR VCO bias setting.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_RXVCO_BIAS_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O_K2_E5                                (0x1<<6) // DLPF DIV2 enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O_K2_E5_SHIFT                          6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_K2_E5                                 (0x1<<7) // CDR DivN clock divider enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X93_K2_E5                                                             0x000974UL //Access:RW   DataWidth:0x8    // AFE spare controls
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X94_K2_E5                                                             0x000978UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X94_AHB_PMA_LN_CDR_DVDR_O_K2_E5                                     (0x3f<<0) // CDR DivN clock division ratio.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X94_AHB_PMA_LN_CDR_DVDR_O_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X94_AHB_PMA_LN_VREG_O_K2_E5                                         (0x3<<6) // Regulator VREG setting
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X94_AHB_PMA_LN_VREG_O_K2_E5_SHIFT                                   6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X95_K2_E5                                                             0x00097cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_BB_STEP_O_K2_E5                                      (0xf<<0) // CDR bb_step
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_BB_STEP_O_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_INT_STEP_O_K2_E5                                     (0x7<<4) // CDR int step
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_INT_STEP_O_K2_E5_SHIFT                               4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_RXDWN_O_K2_E5                                        (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_RXDWN_O_K2_E5_SHIFT                                  7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X96_K2_E5                                                             0x000980UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RXVCOFR_O_K2_E5                                      (0x7<<0) // RXVCOFR override value Enabled by pma_ln_dr_rxvcofr_sel_o
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RXVCOFR_O_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RXVCOFR_SEL_O_K2_E5                                  (0x1<<3) // Override enable for RXVCOFR override vakue
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RXVCOFR_SEL_O_K2_E5_SHIFT                            3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RX_SELR_O_K2_E5                                      (0x7<<4) // CTLE R degeneration select
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RX_SELR_O_K2_E5_SHIFT                                4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X97_K2_E5                                                             0x000984UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X97_AHB_PMA_LN_RX_SELC_O_K2_E5                                      (0x7<<0) // CTLE C degeneration select
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X97_AHB_PMA_LN_RX_SELC_O_K2_E5_SHIFT                                0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X99_K2_E5                                                             0x00098cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X99_PMA_LN_DFE_BW_SCALE_K2_E5                                       (0x3<<4) // DFE Bandwidth Selection
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X99_PMA_LN_DFE_BW_SCALE_K2_E5_SHIFT                                 4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X99_PMA_LN_PHD_ENA_O_1_0_K2_E5                                      (0x3<<6) // CDR phase detector proportional path enable bit 0: enables D4/D3 data/edge samplers bit 1: enables D1/D2 data/edge samplers
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X99_PMA_LN_PHD_ENA_O_1_0_K2_E5_SHIFT                                6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X100_K2_E5                                                            0x000990UL //Access:RW   DataWidth:0x8    // On-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 3-9: Fine x-direction offset, note bit reversal
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_K2_E5                                                            0x000994UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_DLY_O_8_8_K2_E5                                     (0x1<<0) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 2-8: Fine x-direction offset, note bit reversal
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_DLY_O_8_8_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_SGN_RST_O_K2_E5                                     (0x1<<2) // Reset signal for eye alignment mechanism.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_SGN_RST_O_K2_E5_SHIFT                               2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_SD_BWSEL_K2_E5                                          (0x1<<3) // RX signal detector bandwidth select. 0: Nominal bandwidth 1: 10% higher bandwidth
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_SD_BWSEL_K2_E5_SHIFT                                    3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_ENA270_O_K2_E5                                      (0x1<<4) // In eye diagram generation mode, assertion overrides the ck_270 DFE clock "right" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_ENA270_O_K2_E5_SHIFT                                4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_ENA90_O_K2_E5                                       (0x1<<5) // In eye diagram generation mode, assertion overrides the ck_90 DFE clock "left" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_ENA90_O_K2_E5_SHIFT                                 5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X102_K2_E5                                                            0x000998UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X102_PMA_LN_DFE_BIAS_O_3_0_K2_E5                                    (0xf<<0) // DFE bias setting.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X102_PMA_LN_DFE_BIAS_O_3_0_K2_E5_SHIFT                              0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X103_K2_E5                                                            0x00099cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X103_PMA_LN_TX_SR_FASTCAP_O_3_0_K2_E5                               (0xf<<0) // TX driver capacitive slew rate control.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X103_PMA_LN_TX_SR_FASTCAP_O_3_0_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X103_PMA_LN_TXEQ_POLARITY_O_3_0_K2_E5                               (0xf<<4) // TX coefficient polarity enable. Set to "1" for negative polarity. bit 0: Cm bit 1: C0 bit 2: C1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X103_PMA_LN_TXEQ_POLARITY_O_3_0_K2_E5_SHIFT                         4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X104_K2_E5                                                            0x0009a0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X104_PMA_LN_TX_SR_DAC_O_3_0_K2_E5                                   (0xf<<0) // TX slew rate DAC bias current control
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X104_PMA_LN_TX_SR_DAC_O_3_0_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X104_PMA_LN_HSCLK_SEL_O_K2_E5                                       (0x1<<4) // CDR clock divider bypass enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X104_PMA_LN_HSCLK_SEL_O_K2_E5_SHIFT                                 4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X105_K2_E5                                                            0x0009a4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X105_PMA_LN_TX_VREG_LEV_O_4_0_K2_E5                                 (0x1f<<0) // TX driver regulator voltage setting.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X105_PMA_LN_TX_VREG_LEV_O_4_0_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X105_PMA_LN_TXDRV_BLEED_ENA_O_K2_E5                                 (0x1<<5) // TX bleed enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X105_PMA_LN_TXDRV_BLEED_ENA_O_K2_E5_SHIFT                           5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X106_K2_E5                                                            0x0009a8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X106_AHB_PMA_LN_RX_BOOST_OVR_GEN3_O_K2_E5                           (0x1<<0) // RX boost override enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X106_AHB_PMA_LN_RX_BOOST_OVR_GEN3_O_K2_E5_SHIFT                     0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X106_AHB_PMA_LN_RX_BOOSTOVR_GEN3_6_0_O_K2_E5                        (0x7f<<1) // RX boost override setting. Thermometer coded.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X106_AHB_PMA_LN_RX_BOOSTOVR_GEN3_6_0_O_K2_E5_SHIFT                  1
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X107_K2_E5                                                            0x0009acUL //Access:RW   DataWidth:0x8    // RX boost override setting. Thermometer coded.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X108_K2_E5                                                            0x0009b0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X108_AHB_PMA_LN_SD_THSEL_GEN3_O_K2_E5                               (0x7<<0) // Signal detect threshold select for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X108_AHB_PMA_LN_SD_THSEL_GEN3_O_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X108_AHB_PMA_LN_AGC_THSEL_GEN3_O_K2_E5                              (0x7<<3) // AGC threshold select for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X108_AHB_PMA_LN_AGC_THSEL_GEN3_O_K2_E5_SHIFT                        3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X108_AHB_PMA_LN_RXUP_GEN3_O_K2_E5                                   (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X108_AHB_PMA_LN_RXUP_GEN3_O_K2_E5_SHIFT                             6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O_K2_E5                          (0x1<<7) // CDR VCO frequency lock counter divide by 4 enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O_K2_E5_SHIFT                    7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X109_K2_E5                                                            0x0009b4UL //Access:RW   DataWidth:0x8    // RX FL calibration LDHS for Gen3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X110_K2_E5                                                            0x0009b8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X110_AHB_PMA_LN_RXFL_LDHS_GEN3_9_8_O_K2_E5                          (0x3<<0) // RX FL calibration LDHS for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X110_AHB_PMA_LN_RXFL_LDHS_GEN3_9_8_O_K2_E5_SHIFT                    0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X110_AHB_PMA_LN_RXVCO_BIAS_GEN3_O_K2_E5                             (0xf<<2) // CDR VCO bias setting.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X110_AHB_PMA_LN_RXVCO_BIAS_GEN3_O_K2_E5_SHIFT                       2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X110_AHB_PMA_LN_DLPF_DIV2_ENA_GEN3_O_K2_E5                          (0x1<<6) // DLPF DIV2 enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X110_AHB_PMA_LN_DLPF_DIV2_ENA_GEN3_O_K2_E5_SHIFT                    6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O_K2_E5                           (0x1<<7) // CDR DivN clock divider enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O_K2_E5_SHIFT                     7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X111_K2_E5                                                            0x0009bcUL //Access:RW   DataWidth:0x8    // AFE spare controls for Gen3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X112_K2_E5                                                            0x0009c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X112_AHB_PMA_LN_CDR_DVDR_GEN3_O_K2_E5                               (0x3f<<0) // CDR DivN clock divider ratio..
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X112_AHB_PMA_LN_CDR_DVDR_GEN3_O_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X112_AHB_PMA_LN_VREG_GEN3_O_K2_E5                                   (0x3<<6) // Regulator VREG setting for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X112_AHB_PMA_LN_VREG_GEN3_O_K2_E5_SHIFT                             6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X113_K2_E5                                                            0x0009c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X113_AHB_PMA_LN_BB_STEP_GEN3_O_K2_E5                                (0xf<<0) // CDR bb_step for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X113_AHB_PMA_LN_BB_STEP_GEN3_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X113_AHB_PMA_LN_INT_STEP_GEN3_O_K2_E5                               (0x7<<4) // CDR int step for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X113_AHB_PMA_LN_INT_STEP_GEN3_O_K2_E5_SHIFT                         4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X113_AHB_PMA_LN_RXDWN_GEN3_O_K2_E5                                  (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X113_AHB_PMA_LN_RXDWN_GEN3_O_K2_E5_SHIFT                            7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X114_K2_E5                                                            0x0009c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X114_AHB_PMA_LN_RXVCOFR_GEN3_O_K2_E5                                (0x7<<0) // RXVCOFR override value for Gen3 Enabled by pma_ln_dr_rxvcofr_sel_o
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X114_AHB_PMA_LN_RXVCOFR_GEN3_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X114_AHB_PMA_LN_RX_SELR_GEN3_O_K2_E5                                (0x7<<3) // CTLE R degeneration select for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X114_AHB_PMA_LN_RX_SELR_GEN3_O_K2_E5_SHIFT                          3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X114_AHB_PMA_LN_VREGH_GEN3_O_K2_E5                                  (0x3<<6) // Not currently used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X114_AHB_PMA_LN_VREGH_GEN3_O_K2_E5_SHIFT                            6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X115_K2_E5                                                            0x0009ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X115_AHB_PMA_LN_RX_SELC_GEN3_O_K2_E5                                (0x7<<0) // CTLE R degeneration select for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X115_AHB_PMA_LN_RX_SELC_GEN3_O_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X119_K2_E5                                                            0x0009dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X119_AHB_TX_CXP_MARGIN_K2_E5                                        (0xf<<0) // Value to minus/add from the calibrated txterm value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X119_AHB_TX_CXP_MARGIN_K2_E5_SHIFT                                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X119_AHB_TX_CXN_MARGIN_K2_E5                                        (0xf<<4) // Value to minus/add from the calibrated txterm value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X119_AHB_TX_CXN_MARGIN_K2_E5_SHIFT                                  4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X120_K2_E5                                                            0x0009e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X120_AHB_TX_TC_WAIT_NEXT_CMP_K2_E5                                  (0xf<<0) // in txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator  the register ix X2 is the actual number of wait cycle
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X120_AHB_TX_TC_WAIT_NEXT_CMP_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X120_AHB_TX_TC_WAIT_NEXT_SAMPLE_K2_E5                               (0x7<<4) // in txterm calibration, the number refclk cycles to wait before sampling the up from the same comparator
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X120_AHB_TX_TC_WAIT_NEXT_SAMPLE_K2_E5_SHIFT                         4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_K2_E5                                                            0x0009e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_TC_CMP_OUT_NUM_SAMPLES_K2_E5                            (0xf<<0) // in txterm calibration, the number of samples to take from the same comparator
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_TC_CMP_OUT_NUM_SAMPLES_K2_E5_SHIFT                      0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CXP_MARGIN_ADD_0_K2_E5                                  (0x1<<4) // when 1, the final tx term value is calibrated txterm value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CXP_MARGIN_ADD_0_K2_E5_SHIFT                            4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CXN_MARGIN_ADD_0_K2_E5                                  (0x1<<5) // when 1, the final tx term value is calibrated txterm value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CXN_MARGIN_ADD_0_K2_E5_SHIFT                            5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CX_OVR_ENA_K2_E5                                        (0x1<<6) // enable override calibrated txterm value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CX_OVR_ENA_K2_E5_SHIFT                                  6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_TERM_EN_CAL_OVR_K2_E5                                   (0x1<<7) // Debug feature, when set forces circuit to be affected by ahb_tx_cdac_ovr
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_TERM_EN_CAL_OVR_K2_E5_SHIFT                             7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X122_K2_E5                                                            0x0009e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X122_AHB_TX_CXP_OVR_K2_E5                                           (0xf<<0) // override calibrated txterm value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X122_AHB_TX_CXP_OVR_K2_E5_SHIFT                                     0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X122_AHB_TX_CXN_OVR_K2_E5                                           (0xf<<4) // override calibrated txterm value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X122_AHB_TX_CXN_OVR_K2_E5_SHIFT                                     4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X123_K2_E5                                                            0x0009ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X123_TX_CTRL_O_0_K2_E5                                              (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not currently used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X123_TX_CTRL_O_0_K2_E5_SHIFT                                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X123_TX_CTRL_O_7_2_K2_E5                                            (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_slew_sld[1:0]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X123_TX_CTRL_O_7_2_K2_E5_SHIFT                                      2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X124_K2_E5                                                            0x0009f0UL //Access:RW   DataWidth:0x8    // Bits 12:8: txdrv_c1_in[4:0] Bits 15:13: txdrv_c2_in[2:0]
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X125_K2_E5                                                            0x0009f4UL //Access:RW   DataWidth:0x8    // Bits 19-16: txdrv_cm_in[3:0]  Bits 22-20: tx_slew_sld3f[2:0] Bit 23: txdrv_preem_1lsb_mode
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_K2_E5                                                            0x0009f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_EN_O_K2_E5                                                (0x1<<0) // DFE block enable signal.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_EN_O_K2_E5_SHIFT                                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE_OW_O_2_0_K2_E5                                    (0x7<<1) // These bits have similar functionality as rxeq_rate_ow_o_2_0 bits in COMLANE CSR. These are used mainly in COMBINATION modes of operation. They are logically OR'ed with the bits in COMLANE.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE_OW_O_2_0_K2_E5_SHIFT                              1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE1_CAL_EN_O_3_K2_E5                                 (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE1_CAL_EN_O_3_K2_E5_SHIFT                           4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE2_CAL_EN_O_4_K2_E5                                 (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE2_CAL_EN_O_4_K2_E5_SHIFT                           5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE3_CAL_EN_O_5_K2_E5                                 (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE3_CAL_EN_O_5_K2_E5_SHIFT                           6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_FORCE_CAL_O_6_K2_E5                                    (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_FORCE_CAL_O_6_K2_E5_SHIFT                              7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X127_K2_E5                                                            0x0009fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X127_RXEQ_CONT_CAL_O_6_0_K2_E5                                      (0x7f<<0) // 0 : enables att calibration 1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6: enables tap5 dfe calibration This register Is not bit reversed
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X127_RXEQ_CONT_CAL_O_6_0_K2_E5_SHIFT                                0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X128_K2_E5                                                            0x000a00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X128_RXEQ_INIT_CAL_O_6_0_K2_E5                                      (0x7f<<0) // 0 : enables att calibration 1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6: enables tap5 dfe calibration This register Is not bit reversed
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X128_RXEQ_INIT_CAL_O_6_0_K2_E5_SHIFT                                0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X130_K2_E5                                                            0x000a08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X130_RXEQ_RATE1_ATT_START_O_3_0_K2_E5                               (0xf<<0) // ATT start value for rate1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X130_RXEQ_RATE1_ATT_START_O_3_0_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X130_RXEQ_RATE1_BOOST_START_O_3_0_K2_E5                             (0xf<<4) // Boost start value for rate1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X130_RXEQ_RATE1_BOOST_START_O_3_0_K2_E5_SHIFT                       4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X131_K2_E5                                                            0x000a0cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X131_RXEQ_RATE2_ATT_START_O_3_0_K2_E5                               (0xf<<0) // ATT start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X131_RXEQ_RATE2_ATT_START_O_3_0_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X131_RXEQ_RATE2_BOOST_START_O_3_0_K2_E5                             (0xf<<4) // Boost start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X131_RXEQ_RATE2_BOOST_START_O_3_0_K2_E5_SHIFT                       4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X132_K2_E5                                                            0x000a10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X132_RXEQ_RATE2_TAP1_START_O_6_0_K2_E5                              (0x7f<<0) // DFE Tap1 start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X132_RXEQ_RATE2_TAP1_START_O_6_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X133_K2_E5                                                            0x000a14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X133_RXEQ_RATE2_TAP2_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap2 start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X133_RXEQ_RATE2_TAP2_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X134_K2_E5                                                            0x000a18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X134_RXEQ_RATE2_TAP3_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap3 start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X134_RXEQ_RATE2_TAP3_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X135_K2_E5                                                            0x000a1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X135_RXEQ_RATE2_TAP4_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap4 start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X135_RXEQ_RATE2_TAP4_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X136_K2_E5                                                            0x000a20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X136_RXEQ_RATE2_TAP5_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap5 start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X136_RXEQ_RATE2_TAP5_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X137_K2_E5                                                            0x000a24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X137_RXEQ_RATE3_ATT_START_O_3_0_K2_E5                               (0xf<<0) // ATT start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X137_RXEQ_RATE3_ATT_START_O_3_0_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X137_RXEQ_RATE3_BOOST_START_O_3_0_K2_E5                             (0xf<<4) // Boost start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X137_RXEQ_RATE3_BOOST_START_O_3_0_K2_E5_SHIFT                       4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X138_K2_E5                                                            0x000a28UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X138_RXEQ_RATE3_TAP1_START_O_6_0_K2_E5                              (0x7f<<0) // DFE Tap1 start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X138_RXEQ_RATE3_TAP1_START_O_6_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X139_K2_E5                                                            0x000a2cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X139_RXEQ_RATE3_TAP2_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap2 start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X139_RXEQ_RATE3_TAP2_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X140_K2_E5                                                            0x000a30UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X140_RXEQ_RATE3_TAP3_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap3 start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X140_RXEQ_RATE3_TAP3_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X141_K2_E5                                                            0x000a34UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X141_RXEQ_RATE3_TAP4_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap4 start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X141_RXEQ_RATE3_TAP4_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X142_K2_E5                                                            0x000a38UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X142_RXEQ_RATE3_TAP5_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap5 start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X142_RXEQ_RATE3_TAP5_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X143_K2_E5                                                            0x000a3cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X143_RXEQ_SUPERBST_AUTOCAL_DIS_K2_E5                                (0x1<<0) // Disable auto cal w/ rx_superbst
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X143_RXEQ_SUPERBST_AUTOCAL_DIS_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X143_BOOST_MAX_LIMIT_O_K2_E5                                        (0xf<<1) // Max limit value for BOOST auto-calibration
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X143_BOOST_MAX_LIMIT_O_K2_E5_SHIFT                                  1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X143_BOOST_MAX_LIMIT_EN_O_K2_E5                                     (0x1<<5) // Enable Max limiting for BOOST auto-calibration
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X143_BOOST_MAX_LIMIT_EN_O_K2_E5_SHIFT                               5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X143_RX_ATT_BOOST_CAL_O_1_0_K2_E5                                   (0x3<<6) // rx_att_boost setting used during ATT calibration
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X143_RX_ATT_BOOST_CAL_O_1_0_K2_E5_SHIFT                             6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X144_K2_E5                                                            0x000a40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X144_RX_ATT_BOOST_NORM_O_1_0_K2_E5                                  (0x3<<0) // rx_att_boost setting used after ATT calibration
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X144_RX_ATT_BOOST_NORM_O_1_0_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_EN_O_K2_E5                                      (0x1<<2) // boost_adj_en
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_EN_O_K2_E5_SHIFT                                2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_DIR_O_K2_E5                                     (0x1<<3) // boost_adj_dir
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_DIR_O_K2_E5_SHIFT                               3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_VAL_O_K2_E5                                     (0xf<<4) // boost_adj_val This register Is not bit reversed
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_VAL_O_K2_E5_SHIFT                               4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X145_K2_E5                                                            0x000a44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X145_CMP_OFFSET_AVG_MAX_NUMSAMPLES_6_0_K2_E5                        (0x7f<<0) // Max number of samples to be used for CMP Offset Noise Averaging
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X145_CMP_OFFSET_AVG_MAX_NUMSAMPLES_6_0_K2_E5_SHIFT                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X145_CMP_OFFSET_AVG_EN_O_K2_E5                                      (0x1<<7) // CMP Offset Noise Averaging Enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X145_CMP_OFFSET_AVG_EN_O_K2_E5_SHIFT                                7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X146_K2_E5                                                            0x000a48UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X147_K2_E5                                                            0x000a4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_DFE_TAP_PD_WAIT_11_8_K2_E5                                (0xf<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_DFE_TAP_PD_WAIT_11_8_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X147_PMA_LN_DFE_OFS_CAL_ENA_K2_E5                                   (0x3<<4) // DFE offset calibration enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X147_PMA_LN_DFE_OFS_CAL_ENA_K2_E5_SHIFT                             4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS_K2_E5                                (0x1<<6) // Disable auto cal w/ rx_att_gain
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS_K2_E5_SHIFT                          6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_SUPERBST_EN_INVERT_O_K2_E5                                (0x1<<7) // Inverts the polarity of superboost_en before assigning to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_SUPERBST_EN_INVERT_O_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X148_K2_E5                                                            0x000a50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X148_RXEQ_OVR_LOAD_EN_O_6_0_K2_E5                                   (0x7f<<0) // Override for RXEQ_CTRL output register load enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X148_RXEQ_OVR_LOAD_EN_O_6_0_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X148_RXEQ_OVR_EN_O_K2_E5                                            (0x1<<7) // Override enable for DFE signals.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X148_RXEQ_OVR_EN_O_K2_E5_SHIFT                                      7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X149_K2_E5                                                            0x000a54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X149_RXEQ_OVR_LOAD_O_6_0_K2_E5                                      (0x7f<<0) // Override for RXEQ_CTRL output register load value.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X149_RXEQ_OVR_LOAD_O_6_0_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X149_RXEQ_OVR_LATCH_O_K2_E5                                         (0x1<<7) // Override for DFE latch signal. Negative edge causes AFE to store values of DFE output registers.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X149_RXEQ_OVR_LATCH_O_K2_E5_SHIFT                                   7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_K2_E5                                                            0x000a58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_DFE_CMP_SEL_OVR_O_2_0_K2_E5                               (0x7<<0) // Override value for comparator calibration select. Enabled by rxeq_ovr_en_o: 1: Calibrate DFE comparator 1 2: Calibrate DFE comparator 2 3: Calibrate DFE comparator 3 4: Calibrate DFE comparator 4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_DFE_CMP_SEL_OVR_O_2_0_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_ATT_GAIN_OVR_K2_E5                                        (0x3<<3) // Override the value of rx_att_gain output to PMA when rx_att_gain_autocal_dis=1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_ATT_GAIN_OVR_K2_E5_SHIFT                                  3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_SUPERBST_ENA_OVR_K2_E5                                    (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_autocal_dis=1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_SUPERBST_ENA_OVR_K2_E5_SHIFT                              5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6_K2_E5                           (0x1<<6) // DFE TAP CMP no offset override enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6_K2_E5_SHIFT                     6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_DFE_TAP_OVR_EN_O_7_K2_E5                                       (0x1<<7) // DFE TAP override enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_DFE_TAP_OVR_EN_O_7_K2_E5_SHIFT                                 7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X151_K2_E5                                                            0x000a5cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_TAP_EN_OVR_O_7_3_K2_E5                          (0x1f<<0) // DFE offset calibration TAP enable override
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_TAP_EN_OVR_O_7_3_K2_E5_SHIFT                    0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0_K2_E5                            (0x1<<5) // DFE offset calibrated value override enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0_K2_E5_SHIFT                      5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_EN_OVR_O_1_K2_E5                                (0x1<<6) // DFE offset cal enable override
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_EN_OVR_O_1_K2_E5_SHIFT                          6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X151_DFE_CMP_CAL_EN_OVR_O_2_K2_E5                                   (0x1<<7) // DFE comparator cal enable override
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X151_DFE_CMP_CAL_EN_OVR_O_2_K2_E5_SHIFT                             7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X152_K2_E5                                                            0x000a60UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X152_DFE_TAP1_OVR_VAL_O_6_0_K2_E5                                   (0x7f<<0) // DFE Tap 1 Override Value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X152_DFE_TAP1_OVR_VAL_O_6_0_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X153_K2_E5                                                            0x000a64UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X153_DFE_TAP2_OVR_VAL_O_5_0_K2_E5                                   (0x3f<<0) // DFE Tap 2 Override Value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X153_DFE_TAP2_OVR_VAL_O_5_0_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X154_K2_E5                                                            0x000a68UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X154_DFE_TAP3_OVR_VAL_O_5_0_K2_E5                                   (0x3f<<0) // DFE Tap 3 Override Value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X154_DFE_TAP3_OVR_VAL_O_5_0_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X155_K2_E5                                                            0x000a6cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X155_DFE_TAP4_OVR_VAL_O_5_0_K2_E5                                   (0x3f<<0) // DFE Tap 4 Override Value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X155_DFE_TAP4_OVR_VAL_O_5_0_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X156_K2_E5                                                            0x000a70UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X156_DFE_TAP5_OVR_VAL_O_5_0_K2_E5                                   (0x3f<<0) // DFE Tap 5 Override Value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X156_DFE_TAP5_OVR_VAL_O_5_0_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X157_K2_E5                                                            0x000a74UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X157_TXEQ_ADAPT_EN_O_0_K2_E5                                        (0x1<<0) // TX Equalizer adaptation function enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X157_TXEQ_ADAPT_EN_O_0_K2_E5_SHIFT                                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X157_TXEQ_ERR_SIGN_O_1_K2_E5                                        (0x1<<1) // TX Equalizer Error Sign
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X157_TXEQ_ERR_SIGN_O_1_K2_E5_SHIFT                                  1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X157_TXEQ_FW_OVRIDE_O_2_K2_E5                                       (0x1<<2) // TX Equalization Firmware over ride  0 -	 Disable firmware based adaptation  1 -	 Enbale firmware based adaptation
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X157_TXEQ_FW_OVRIDE_O_2_K2_E5_SHIFT                                 2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X158_K2_E5                                                            0x000a78UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X158_TXEQ_ERR_STAT_I_1_0_K2_E5                                      (0x3<<0) // TX Equalization error state
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X158_TXEQ_ERR_STAT_I_1_0_K2_E5_SHIFT                                0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X159_K2_E5                                                            0x000a7cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X159_TXEQ_OVER_EQ_CNT_I_9_8_K2_E5                                   (0x3<<0) // Over equalization count 9-8
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X159_TXEQ_OVER_EQ_CNT_I_9_8_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X160_K2_E5                                                            0x000a80UL //Access:R    DataWidth:0x8    // Over equalization count 7-0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X161_K2_E5                                                            0x000a84UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X161_TXEQ_UNDER_EQ_CNT_I_9_8_K2_E5                                  (0x3<<0) // Under equalization count 9-8
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X161_TXEQ_UNDER_EQ_CNT_I_9_8_K2_E5_SHIFT                            0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X162_K2_E5                                                            0x000a88UL //Access:R    DataWidth:0x8    // Under equalization count 7-0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X163_K2_E5                                                            0x000a8cUL //Access:RW   DataWidth:0x8    // TX Equalizer Training Pattern
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X164_K2_E5                                                            0x000a90UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X164_TXEQ_TRAINING_PATT_O_8_K2_E5                                   (0x1<<0) // TX Equalizer Training Pattern
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X164_TXEQ_TRAINING_PATT_O_8_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X165_K2_E5                                                            0x000a94UL //Access:RW   DataWidth:0x8    // Mask bit for Txeq training pattern
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X166_K2_E5                                                            0x000a98UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X166_TXEQ_DONT_CARE_O_8_K2_E5                                       (0x1<<0) // Mask bit for Txeq training pattern
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X166_TXEQ_DONT_CARE_O_8_K2_E5_SHIFT                                 0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X167_K2_E5                                                            0x000a9cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X167_TXEQ_RXRECAL_INIT_O_7_K2_E5                                    (0x1<<0) // This bit has similar function as txeq_rxrecal_init  in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X167_TXEQ_RXRECAL_INIT_O_7_K2_E5_SHIFT                              0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X168_K2_E5                                                            0x000aa0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X168_INIT_RX_PRESET_HINT_EN_O_K2_E5                                 (0x1<<0) // Enable for primary input lnx_rx_preset_hint during init cal.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X168_INIT_RX_PRESET_HINT_EN_O_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X168_RECAL_RX_PRESET_HINT_EN_O_K2_E5                                (0x1<<1) // Enable for primary input lnx_rx_preset_hint during recal.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X168_RECAL_RX_PRESET_HINT_EN_O_K2_E5_SHIFT                          1
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X169_K2_E5                                                            0x000aa4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X169_TXEQ_RXRECAL_DONE_I_0_K2_E5                                    (0x1<<0) // TX - RECAL RX Equalization status
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X169_TXEQ_RXRECAL_DONE_I_0_K2_E5_SHIFT                              0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X170_K2_E5                                                            0x000aa8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X170_BLOCK_DEC_ERR_K2_E5                                            (0x1<<0) // decoder sync header error
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X170_BLOCK_DEC_ERR_K2_E5_SHIFT                                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X201_K2_E5                                                            0x000b24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X201_CDFE_EN_O_0_K2_E5                                              (0x1<<0) // cdfe enable bit.  1: enable cdfe when rate is 2'b01 or 2'b10.  0: disable cdfe.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X201_CDFE_EN_O_0_K2_E5_SHIFT                                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X201_CDFE_WORD_OV_O_1_0_K2_E5                                       (0x3<<1) // The cdfe input word_i overwrite.                                                                                                         2'b00: the word_i input for cdfe block is internally generated.                                     2'b10: the word_i input for cdfe block is set to 0 8-bit or 10-bit mode.                                                       2'b11: the word_i input for cdfe block is set to 1 16-bit or 20-bit mode.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X201_CDFE_WORD_OV_O_1_0_K2_E5_SHIFT                                 1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X201_CDFE_MODE_8B_OV_O_1_0_K2_E5                                    (0x3<<3) // The cdfe input mode_8b_i overwrite.                                                                                                         2'b00: the mode_8b_i input for cdfe block is internally generated.                                      2'b01: the mode_8b_i input for cdfe block is set to 0 10-bit or 20-bit mode.                                                      2'b11: the mode_8b_i input for cdfe block is set to 1 8-bit or 16-bit mode.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X201_CDFE_MODE_8B_OV_O_1_0_K2_E5_SHIFT                              3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X201_CDFE_RATE_OV_O_2_0_K2_E5                                       (0x7<<5) // The cdfe input rate_i[1:0] overwrite.                                                                                                         3'b0xx: the rate_i input for cdfe block is internally generated.                                     3'b1xx: the rate_i[1:0] input for cdfe block is set to cdfe_rate_ov_o[1:0]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X201_CDFE_RATE_OV_O_2_0_K2_E5_SHIFT                                 5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X202_K2_E5                                                            0x000b28UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X203_K2_E5                                                            0x000b2cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X203_CDFE_GO_K2_E5                                                  (0x1<<4) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X203_CDFE_GO_K2_E5_SHIFT                                            4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_FORCE_CAL_K2_E5                                        (0x1<<5) // The cdfe force calibration enable.  1: enable force cdfe calibration.  0: disable force cdfe calibration.  Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_FORCE_CAL_K2_E5_SHIFT                                  5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_RATE_CHANGE_CAL_K2_E5                                  (0x1<<6) // The cdfe force calibration enable.  1: enable force cdfe calibration.  0: disable force cdfe calibration.  Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_RATE_CHANGE_CAL_K2_E5_SHIFT                            6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_EI_EXIT_CAL_K2_E5                                      (0x1<<7) // EI exit cdfe calibration enable.                                                                                                   1: the cdfe calibration is enabled when EI exits and when rate is  2'b01 or 2'b10.                                  0: the cdfe calibration is disabled when EI exits.                                                                    Note: EI exit cdfe calibration is only enabled when EI exit edfe calibration is also enabled.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_EI_EXIT_CAL_K2_E5_SHIFT                                7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_K2_E5                                                            0x000b30UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_CONT_CAL_K2_E5                                         (0x1<<0) // Continuous cdfe calibration enable.                                                                                            1: the continuous cdfe calibration is enabled when the rate is  2'b01 or 2'b10.                                  0: the continuous cdfe calibration is disabled.                                                                        Note: Continuout cdfe calibration is only enabled when continuous edfe calibration is also enabled.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_CONT_CAL_K2_E5_SHIFT                                   0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL_K2_E5                             (0x1<<1) // Enables cdfe calibration during Txeq adaptation phase.                                                                                            1: the cdfe calibration is enabled when the rate is  2'b10.                                  0: the cdfe calibration is disabled.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL_K2_E5_SHIFT                       1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL_K2_E5                              (0x1<<2) // Enables cdfe calibration post Txeq adaptation.                                                                                            1: the cdfe calibration is enabled when the rate is  2'b10.                                  0: the cdfe calibration is disabled.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL_K2_E5_SHIFT                        2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_CAL_EN_K2_E5                                     (0x1<<3) // Enables the cdfe calibration in rate3.  1: enables cdfe calibration.  0: disables cdfe calibration.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_CAL_EN_K2_E5_SHIFT                               3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE2_CAL_EN_K2_E5                                     (0x1<<4) // Enables the cdfe calibration in rate2.  1: enables cdfe calibration.  0: disables cdfe calibration.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE2_CAL_EN_K2_E5_SHIFT                               4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X205_K2_E5                                                            0x000b34UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during init cal in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X206_K2_E5                                                            0x000b38UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during continuos cal in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X207_K2_E5                                                            0x000b3cUL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during re-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X208_K2_E5                                                            0x000b40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X208_AHB_CDFE_COARSE_DLL_OV_EN_K2_E5                                (0x1<<7) // cdfe coarse dll overwrite enable.  1: enable coarse dll overwrite for cdfe.  0: disable coarse dll overwrite for cdfe.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X208_AHB_CDFE_COARSE_DLL_OV_EN_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X213_K2_E5                                                            0x000b54UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during txeq adaptation phase in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X214_K2_E5                                                            0x000b58UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during post  txeq adaptation  in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X215_K2_E5                                                            0x000b5cUL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during init cal in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X216_K2_E5                                                            0x000b60UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during continuos cal in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X217_K2_E5                                                            0x000b64UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during re-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X220_K2_E5                                                            0x000b70UL //Access:RW   DataWidth:0x8    // Start value for dlev_ref.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X221_K2_E5                                                            0x000b74UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X221_CDFE_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_K2_E5                   (0x1f<<0) // Enables copying of adapted tap values to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enables/disables copying to tap3 bit[3] : enables/disables copying to tap4 bit[4] : enables/disables copying to tap5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X221_CDFE_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_K2_E5_SHIFT             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X222_K2_E5                                                            0x000b78UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X222_CDFE_NON_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_K2_E5               (0x1f<<0) // Enables copying of adapted tap values to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enables/disables copying to tap3 bit[3] : enables/disables copying to tap4 bit[4] : enables/disables copying to tap5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X222_CDFE_NON_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_K2_E5_SHIFT         0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X223_K2_E5                                                            0x000b7cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X223_AHB_CDFE_CMP1_TAP1_OFFSET_K2_E5                                (0x7f<<0) // Override for CMP1 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[1]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X223_AHB_CDFE_CMP1_TAP1_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X224_K2_E5                                                            0x000b80UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X224_AHB_CDFE_CMP1_TAP2_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP1 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[2]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X224_AHB_CDFE_CMP1_TAP2_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X225_K2_E5                                                            0x000b84UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X225_AHB_CDFE_CMP1_TAP3_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP1 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[3]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X225_AHB_CDFE_CMP1_TAP3_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X226_K2_E5                                                            0x000b88UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X226_AHB_CDFE_CMP1_TAP4_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP1 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[4]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X226_AHB_CDFE_CMP1_TAP4_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X227_K2_E5                                                            0x000b8cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X227_AHB_CDFE_CMP1_TAP5_OFFSET_K2_E5                                (0x3f<<0) // Override for CMP1 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[5]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X227_AHB_CDFE_CMP1_TAP5_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X228_K2_E5                                                            0x000b90UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X228_AHB_CDFE_CMP2_TAP1_OFFSET_K2_E5                                (0x7f<<0) // Override for CMP2 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[1]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X228_AHB_CDFE_CMP2_TAP1_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X229_K2_E5                                                            0x000b94UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X229_AHB_CDFE_CMP2_TAP2_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP2 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[2]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X229_AHB_CDFE_CMP2_TAP2_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X230_K2_E5                                                            0x000b98UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X230_AHB_CDFE_CMP2_TAP3_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP2 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[3]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X230_AHB_CDFE_CMP2_TAP3_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X231_K2_E5                                                            0x000b9cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X231_AHB_CDFE_CMP2_TAP4_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP2 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[4]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X231_AHB_CDFE_CMP2_TAP4_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X232_K2_E5                                                            0x000ba0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X232_AHB_CDFE_CMP2_TAP5_OFFSET_K2_E5                                (0x3f<<0) // Override for CMP2 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[5]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X232_AHB_CDFE_CMP2_TAP5_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X233_K2_E5                                                            0x000ba4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X233_AHB_CDFE_CMP3_TAP1_OFFSET_K2_E5                                (0x7f<<0) // Override for CMP3 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[1]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X233_AHB_CDFE_CMP3_TAP1_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X234_K2_E5                                                            0x000ba8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X234_AHB_CDFE_CMP3_TAP2_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP3 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[2]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X234_AHB_CDFE_CMP3_TAP2_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X235_K2_E5                                                            0x000bacUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X235_AHB_CDFE_CMP3_TAP3_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP3 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[3]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X235_AHB_CDFE_CMP3_TAP3_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X236_K2_E5                                                            0x000bb0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X236_AHB_CDFE_CMP3_TAP4_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP3 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[4]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X236_AHB_CDFE_CMP3_TAP4_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X237_K2_E5                                                            0x000bb4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X237_AHB_CDFE_CMP3_TAP5_OFFSET_K2_E5                                (0x3f<<0) // Override for CMP3 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[5]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X237_AHB_CDFE_CMP3_TAP5_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X238_K2_E5                                                            0x000bb8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X238_AHB_CDFE_CMP4_TAP1_OFFSET_K2_E5                                (0x7f<<0) // Override for CMP4 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[1]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X238_AHB_CDFE_CMP4_TAP1_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X239_K2_E5                                                            0x000bbcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X239_AHB_CDFE_CMP4_TAP2_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP4 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[2]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X239_AHB_CDFE_CMP4_TAP2_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X240_K2_E5                                                            0x000bc0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X240_AHB_CDFE_CMP4_TAP3_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP4 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[3]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X240_AHB_CDFE_CMP4_TAP3_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X241_K2_E5                                                            0x000bc4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X241_AHB_CDFE_CMP4_TAP4_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP4 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[4]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X241_AHB_CDFE_CMP4_TAP4_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X242_K2_E5                                                            0x000bc8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X242_AHB_CDFE_CMP4_TAP5_OFFSET_K2_E5                                (0x3f<<0) // Override for CMP4 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[5]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X242_AHB_CDFE_CMP4_TAP5_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X243_K2_E5                                                            0x000bccUL //Access:RW   DataWidth:0x8    // Override for CMP1 main calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[0]
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X244_K2_E5                                                            0x000bd0UL //Access:RW   DataWidth:0x8    // Override for CMP2 main calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[0]
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X245_K2_E5                                                            0x000bd4UL //Access:RW   DataWidth:0x8    // Override for CMP3 main calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[0]
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X246_K2_E5                                                            0x000bd8UL //Access:RW   DataWidth:0x8    // Override for CMP4 main calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[0]
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X247_K2_E5                                                            0x000bdcUL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X248_K2_E5                                                            0x000be0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X248_AHB_CDFE_DLL_FINE_MASK_9_8_K2_E5                               (0x3<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X248_AHB_CDFE_DLL_FINE_MASK_9_8_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X248_AHB_CDFE_FINE_DLL_EDGE_SHIFT_K2_E5                             (0xf<<2) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X248_AHB_CDFE_FINE_DLL_EDGE_SHIFT_K2_E5_SHIFT                       2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X249_K2_E5                                                            0x000be4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X249_AHB_CDFE_ERR_SMPL_SHIFT_K2_E5                                  (0xf<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X249_AHB_CDFE_ERR_SMPL_SHIFT_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X249_AHB_CDFE_FINE_DLL_OV_EN_K2_E5                                  (0x1<<4) // cdfe fine dll overwrite enable.  1: enable fine dll overwrite for cdfe.  0: disable fine dll overwrite for cdfe.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X249_AHB_CDFE_FINE_DLL_OV_EN_K2_E5_SHIFT                            4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_K2_E5                                                            0x000be8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8_K2_E5                        (0x1<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8_K2_E5_SHIFT                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_K2_E5                       (0x1<<1) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_K2_E5_SHIFT                 1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8_K2_E5                        (0x1<<2) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8_K2_E5_SHIFT                  2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_K2_E5                       (0x1<<3) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_K2_E5_SHIFT                 3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X251_K2_E5                                                            0x000becUL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X252_K2_E5                                                            0x000bf0UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X253_K2_E5                                                            0x000bf4UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X254_K2_E5                                                            0x000bf8UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_K2_E5                                                            0x000bfcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_CDFE_DIR_OV_EN_K2_E5                                           (0x1<<0) // Override enable for CDFE calibration direction
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_CDFE_DIR_OV_EN_K2_E5_SHIFT                                     0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_CDFE_DIR_OV_VAL_K2_E5                                          (0x1<<1) // Override value for CDFE calibration direction
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_CDFE_DIR_OV_VAL_K2_E5_SHIFT                                    1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_ENA270_OVR_EN_O_K2_E5                               (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_ENA270_OVR_EN_O_K2_E5_SHIFT                         2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_ENA90_OVR_EN_O_K2_E5                                (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_ENA90_OVR_EN_O_K2_E5_SHIFT                          3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_PHD_ENA_OVR_EN_O_K2_E5                                  (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_PHD_ENA_OVR_EN_O_K2_E5_SHIFT                            4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_DLY_OVR_EN_O_K2_E5                                  (0x1<<5) // cdfe eye delay overwrite enable.  1: enable eye delay overwrite for cdfe.  0: disable eye delay overwrite for cdfe.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_DLY_OVR_EN_O_K2_E5_SHIFT                            5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O_K2_E5                              (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O_K2_E5_SHIFT                        6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X256_K2_E5                                                            0x000c00UL //Access:RW   DataWidth:0x8    // cdfe eye delay count overwrite value for CLK90.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X257_K2_E5                                                            0x000c04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8_K2_E5                           (0x1<<0) // cdfe eye delay count overwrite value for CLK90.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8_K2_E5_SHIFT                     0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_K2_E5                   (0x7f<<1) // This register represents the maximum comparator offset from the midpoint code 127/128 that must be met for the comparator to be selected as adaptation comparator during dlev and tap adaptation.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_K2_E5_SHIFT             1
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X258_K2_E5                                                            0x000c08UL //Access:RW   DataWidth:0x8    // cdfe eye delay count overwrite value for CLK270.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X259_K2_E5                                                            0x000c0cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8_K2_E5                          (0x1<<0) // cdfe eye delay count overwrite value for CLK270.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8_K2_E5_SHIFT                    0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X259_AHB_CDFE_DLEV_OV_EN_K2_E5                                      (0x1<<1) // cdfe dlev overwrite enable.  1: enable dlev overwrite for cdfe.  0: disable dlev overwrite for cdfe.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X259_AHB_CDFE_DLEV_OV_EN_K2_E5_SHIFT                                1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X259_CDFE_DLEV_ADAPT_CMP_SEL_OVR_O_4_0_K2_E5                        (0x1f<<2) // Register override for overriding adaptation comparator select bit [0] : override enable bit [4:1] : override value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X259_CDFE_DLEV_ADAPT_CMP_SEL_OVR_O_4_0_K2_E5_SHIFT                  2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_K2_E5                   (0x1<<7) // Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_K2_E5_SHIFT             7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X260_K2_E5                                                            0x000c10UL //Access:RW   DataWidth:0x8    // Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X261_K2_E5                                                            0x000c14UL //Access:RW   DataWidth:0x8    // cdfe dlevn overwrite value.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X262_K2_E5                                                            0x000c18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X262_AHB_CDFE_TAP_OV_EN_K2_E5                                       (0x1f<<0) // cdfe tap1~5 overwrite enable.                                                                                                    Bit[0]: enable tap1 overwrite for cdfe. Bit[1]: enable tap2 overwrite for cdfe Bit[2]: enable tap3 overwrite for cdfe.  Bit[3]: enable tap4 overwrite for cdfe. Bit[4]: enable tap5 overwrite for cdfe.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X262_AHB_CDFE_TAP_OV_EN_K2_E5_SHIFT                                 0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X263_K2_E5                                                            0x000c1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X263_AHB_CDFE_TAP1_OV_K2_E5                                         (0x7f<<0) // cdfe tap1 overwrite value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X263_AHB_CDFE_TAP1_OV_K2_E5_SHIFT                                   0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X264_K2_E5                                                            0x000c20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X264_AHB_CDFE_TAP2_OV_K2_E5                                         (0x3f<<0) // cdfe tap2 overwrite value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X264_AHB_CDFE_TAP2_OV_K2_E5_SHIFT                                   0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X265_K2_E5                                                            0x000c24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X265_AHB_CDFE_TAP3_OV_K2_E5                                         (0x3f<<0) // cdfe tap3 overwrite value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X265_AHB_CDFE_TAP3_OV_K2_E5_SHIFT                                   0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X266_K2_E5                                                            0x000c28UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X266_AHB_CDFE_TAP4_OV_K2_E5                                         (0x3f<<0) // cdfe tap4 overwrite value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X266_AHB_CDFE_TAP4_OV_K2_E5_SHIFT                                   0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X267_K2_E5                                                            0x000c2cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X267_AHB_CDFE_TAP5_OV_K2_E5                                         (0x3f<<0) // cdfe tap5 overwrite value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X267_AHB_CDFE_TAP5_OV_K2_E5_SHIFT                                   0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_K2_E5                   (0x1<<7) // Enables FW enable control for TAP adapt using DLEV
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_K2_E5_SHIFT             7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_K2_E5                                                            0x000c30UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O_K2_E5                           (0x1<<0) // Instucts to start TAP adapt using DLEV in FW enabled mode
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O_K2_E5_SHIFT                     0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_K2_E5                 (0x1<<1) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_K2_E5_SHIFT           1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O_K2_E5             (0x1<<2) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O_K2_E5_SHIFT       2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_K2_E5                                (0x1<<7) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X269_K2_E5                                                            0x000c34UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O_K2_E5                         (0x1<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O_K2_E5_SHIFT                   0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_STROBE_EN_O_K2_E5                                     (0x1<<1) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_STROBE_EN_O_K2_E5_SHIFT                               1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_CMP_ENA_O_K2_E5                                       (0xf<<2) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_CMP_ENA_O_K2_E5_SHIFT                                 2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X270_K2_E5                                                            0x000c38UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X271_K2_E5                                                            0x000c3cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X271_AHB_CDFE_DIV_SIGN_BIT_O_4_0_K2_E5                              (0x1f<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X271_AHB_CDFE_DIV_SIGN_BIT_O_4_0_K2_E5_SHIFT                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O_K2_E5                      (0x1<<5) // Forces the positive dlev training pattern to be used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O_K2_E5_SHIFT                5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O_K2_E5                      (0x1<<6) // Forces the negative dlev training pattern to be used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O_K2_E5_SHIFT                6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X272_K2_E5                                                            0x000c40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X272_CDFE_TAP1_SCALE_O_2_0_K2_E5                                    (0x7<<0) // Scale factor CDFE TAP1 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X272_CDFE_TAP1_SCALE_O_2_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X272_CDFE_TAP1_SHIFT_O_4_0_K2_E5                                    (0x1f<<3) // Shift factor CDFE TAP1 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X272_CDFE_TAP1_SHIFT_O_4_0_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X273_K2_E5                                                            0x000c44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X273_CDFE_TAP2_SCALE_O_2_0_K2_E5                                    (0x7<<0) // Scale factor CDFE TAP2 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X273_CDFE_TAP2_SCALE_O_2_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X273_CDFE_TAP2_SHIFT_O_4_0_K2_E5                                    (0x1f<<3) // Shift factor CDFE TAP2 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X273_CDFE_TAP2_SHIFT_O_4_0_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X274_K2_E5                                                            0x000c48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X274_CDFE_TAP3_SCALE_O_2_0_K2_E5                                    (0x7<<0) // Scale factor CDFE TAP3 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X274_CDFE_TAP3_SCALE_O_2_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X274_CDFE_TAP3_SHIFT_O_4_0_K2_E5                                    (0x1f<<3) // Shift factor CDFE TAP3 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X274_CDFE_TAP3_SHIFT_O_4_0_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X275_K2_E5                                                            0x000c4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X275_CDFE_TAP4_SCALE_O_2_0_K2_E5                                    (0x7<<0) // Scale factor CDFE TAP4 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X275_CDFE_TAP4_SCALE_O_2_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X275_CDFE_TAP4_SHIFT_O_4_0_K2_E5                                    (0x1f<<3) // Shift factor CDFE TAP4 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X275_CDFE_TAP4_SHIFT_O_4_0_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X276_K2_E5                                                            0x000c50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X276_CDFE_TAP5_SCALE_O_2_0_K2_E5                                    (0x7<<0) // Scale factor CDFE TAP5 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X276_CDFE_TAP5_SCALE_O_2_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X276_CDFE_TAP5_SHIFT_O_4_0_K2_E5                                    (0x1f<<3) // Shift factor CDFE TAP5 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X276_CDFE_TAP5_SHIFT_O_4_0_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X277_K2_E5                                                            0x000c54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_RA_OVR_O_K2_E5                                    (0x3<<0) // Bit 0:  Override enable for msm_reset_ra Bit 1: Override msm_reset_ra
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_RA_OVR_O_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_P2S_OVR_O_K2_E5                                   (0x3<<2) // Bit 0:  Override enable for msm_reset_p2s Bit 1: Override msm_reset_p2s
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_P2S_OVR_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_LNREGH_OVR_O_K2_E5                                (0x3<<4) // Bit 0:  Override enable for msm_reset_lnregh Bit 1: Override msm_reset_lnregh
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_LNREGH_OVR_O_K2_E5_SHIFT                          4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_LNREG_OVR_O_K2_E5                                 (0x3<<6) // Bit 0:  Override enable for msm_reset_lnreg Bit 1: Override msm_reset_lnreg
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_LNREG_OVR_O_K2_E5_SHIFT                           6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X278_K2_E5                                                            0x000c58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_RESET_CDR_OVR_O_K2_E5                                   (0x3<<0) // Bit 0:  Override enable for msm_reset_cdr Bit 1: Override msm_reset_cdr
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_RESET_CDR_OVR_O_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_RESET_DFE_OVR_O_K2_E5                                   (0x3<<2) // Bit 0:  Override enable for msm_reset_dfe Bit 1: Override msm_reset_dfe
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_RESET_DFE_OVR_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_PD_LNREGH_OVR_O_K2_E5                                   (0x3<<4) // Bit 0:  Override enable for msm_pd_lnregh Bit 1: Override msm_pd_lnregh
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_PD_LNREGH_OVR_O_K2_E5_SHIFT                             4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_PD_VCO_BUF_OVR_O_K2_E5                                  (0x3<<6) // Bit 0:  Override enable for msm_pd_vco_buf Bit 1: Override msm_pd_vco_buf
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_PD_VCO_BUF_OVR_O_K2_E5_SHIFT                            6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X279_K2_E5                                                            0x000c5cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_RESET_CDR_GCRX_OVR_O_K2_E5                              (0x3<<0) // Bit 0:  Override enable for msm_reset_cdr_gcrx Bit 1: Override msm_reset_cdr_gcrx
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_RESET_CDR_GCRX_OVR_O_K2_E5_SHIFT                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_RXGATE_EN_OVR_O_K2_E5                                   (0x3<<2) // Bit 0:  Override enable for msm_rxgate_en Bit 1: Override msm_rxgate_en
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_RXGATE_EN_OVR_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_RESET_VCO_OVR_O_K2_E5                                   (0x3<<4) // Bit 0:  Override enable for msm_reset_vco Bit 1: Override msm_reset_vco
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_RESET_VCO_OVR_O_K2_E5_SHIFT                             4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_IDDQ_SD_OVR_O_K2_E5                                     (0x3<<6) // Bit 0:  Override enable for msm_iddq_sd Bit 1: Override msm_iddq_sd
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_IDDQ_SD_OVR_O_K2_E5_SHIFT                               6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X280_K2_E5                                                            0x000c60UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_PD_DFE_OVR_O_K2_E5                                      (0x3<<0) // Bit 0:  Override enable for msm_pd_dfe Bit 1: Override msm_pd_dfe
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_PD_DFE_OVR_O_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_PD_DFE_BIAS_OVR_O_K2_E5                                 (0x3<<2) // Bit 0:  Override enable for msm_pd_dfe_bias Bit 1: Override msm_pd_dfe_bias
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_PD_DFE_BIAS_OVR_O_K2_E5_SHIFT                           2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_TXDRV_LP_IDLE_OVR_O_K2_E5                               (0x3<<4) // Bit 0:  Override enable for msm_txdrv_lp_idle Bit 1: Override msm_txdrv_lp_idle
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_TXDRV_LP_IDLE_OVR_O_K2_E5_SHIFT                         4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_TXREG_BLEED_ENA_OVR_O_K2_E5                             (0x3<<6) // Bit 0:  Override enable for msm_txreg_bleed_ena Bit 1: Override msm_txreg_bleed_ena
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_TXREG_BLEED_ENA_OVR_O_K2_E5_SHIFT                       6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X281_K2_E5                                                            0x000c64UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_TXREG_OVR_O_K2_E5                                    (0x3<<0) // Bit 0:  Override enable for msm_pd_txreg Bit 1: Override msm_pd_txreg
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_TXREG_OVR_O_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_LNREG_OVR_O_K2_E5                                    (0x3<<2) // Bit 0:  Override enable for msm_pd_lnreg Bit 1: Override msm_pd_lnreg
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_LNREG_OVR_O_K2_E5_SHIFT                              2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_P2S_OVR_O_K2_E5                                      (0x3<<4) // Bit 0:  Override enable for pd_p2s Bit 1: Override pd_p2s
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_P2S_OVR_O_K2_E5_SHIFT                                4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_RA_OVR_O_K2_E5                                       (0x3<<6) // Bit 0:  Override enable for pd_ra Bit 1: Override pd_ra
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_RA_OVR_O_K2_E5_SHIFT                                 6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X282_K2_E5                                                            0x000c68UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X282_LN_MSM_PD_SLV_BIAS_OVR_O_K2_E5                                 (0x3<<2) // Bit 0:  Override enable for pd_slv_bias Bit 1: Override pd_slv_bias
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X282_LN_MSM_PD_SLV_BIAS_OVR_O_K2_E5_SHIFT                           2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X282_LN_MSM_PD_TXDRV_OVR_O_K2_E5                                    (0x3<<4) // Bit 0:  Override enable for pd_txdrv Bit 1: Override pd_txdrv
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X282_LN_MSM_PD_TXDRV_OVR_O_K2_E5_SHIFT                              4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X282_LN_MSM_PD_VCO_OVR_O_K2_E5                                      (0x3<<6) // Bit 0:  Override enable for msm_pd_vco Bit 1: Override msm_pd_vco
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X282_LN_MSM_PD_VCO_OVR_O_K2_E5_SHIFT                                6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X283_K2_E5                                                            0x000c6cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_CDR_EN_OVR_O_K2_E5                                      (0x3<<0) // Bit 0:  Override enable for msm_cdr_en Bit 1: Override msm_cdr_en
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_CDR_EN_OVR_O_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_RESET_S2P_OVR_O_K2_E5                                   (0x3<<2) // Bit 0:  Override enable for msm_reset_s2p Bit 1: Override msm_reset_s2p
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_RESET_S2P_OVR_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_RXCLK_EN_OVR_O_K2_E5                                    (0x3<<4) // Bit 0:  Override enable for msm_rxclk_en Bit 1: Override msm_rxclk_en
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_RXCLK_EN_OVR_O_K2_E5_SHIFT                              4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_WORD_OVR_O_K2_E5                                        (0x3<<6) // Bit 0:  Override enable for msm_word Bit 1: Override msm_word
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_WORD_OVR_O_K2_E5_SHIFT                                  6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X284_K2_E5                                                            0x000c70UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RATE_OVR_O_K2_E5                                        (0x7<<0) // Bit 0:  Override enable for msm_rate Bit [2:1] : Override msm_rate
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RATE_OVR_O_K2_E5_SHIFT                                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RXVCODIV_OVR_O_K2_E5                                    (0x7<<3) // Bit 0:  Override enable for msm_rxvcodiv Bit [2:1] : Override msm_rxvcodiv
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RXVCODIV_OVR_O_K2_E5_SHIFT                              3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RESET_TX_CLKDIV_OVR_O_K2_E5                             (0x3<<6) // Not currently used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RESET_TX_CLKDIV_OVR_O_K2_E5_SHIFT                       6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X285_K2_E5                                                            0x000c74UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X285_LN_MSM_TXVCODIV_OVR_O_K2_E5                                    (0x7<<0) // Bit 0:  Override enable for msm_txvcodiv Bit [2:1] : Override msm_txvcodiv
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X285_LN_MSM_TXVCODIV_OVR_O_K2_E5_SHIFT                              0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_K2_E5                                                            0x000cb4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_RX_SRC_O_K2_E5                                                 (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 - Output of mux is output from 8b/10b encoder.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_RX_SRC_O_K2_E5_SHIFT                                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_TREG0_POL_O_K2_E5                                              (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_TREG0_POL_O_K2_E5_SHIFT                                        1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_TREG0_BIT_O_K2_E5                                              (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_TREG0_BIT_O_K2_E5_SHIFT                                        2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_TREG0_WORD_O_K2_E5                                             (0x1<<3) // TReg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_TREG0_WORD_O_K2_E5_SHIFT                                       3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_DMUX_TXA_SEL_O_1_0_K2_E5                                       (0x3<<4) // Transmit mux A data input select.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_DMUX_TXA_SEL_O_1_0_K2_E5_SHIFT                                 4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_P2S_RBUF_AUTOFIX_O_K2_E5                                       (0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / underflows 1 - Ring buffer will reset upon detection of overflow/underflow
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_P2S_RBUF_AUTOFIX_O_K2_E5_SHIFT                                 6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_K2_E5                                                            0x000cb8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_TREG1_POL_O_K2_E5                                              (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_TREG1_POL_O_K2_E5_SHIFT                                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_TREG1_BIT_O_K2_E5                                              (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_TREG1_BIT_O_K2_E5_SHIFT                                        1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_TREG1_WORD_O_K2_E5                                             (0x1<<2) // TReg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_TREG1_WORD_O_K2_E5_SHIFT                                       2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_REG1_POL_O_K2_E5                                               (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_REG1_POL_O_K2_E5_SHIFT                                         3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_REG1_BIT_O_K2_E5                                               (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_REG1_BIT_O_K2_E5_SHIFT                                         4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_REG1_WORD_O_K2_E5                                              (0x1<<5) // Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_REG1_WORD_O_K2_E5_SHIFT                                        5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_REG0_POL_O_K2_E5                                               (0x1<<6) // Used as Reg0 polarity select
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_REG0_POL_O_K2_E5_SHIFT                                         6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_K2_E5                                                            0x000cbcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_REG0_BIT_O_K2_E5                                               (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_REG0_BIT_O_K2_E5_SHIFT                                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_REG0_WORD_O_K2_E5                                              (0x1<<1) // Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_REG0_WORD_O_K2_E5_SHIFT                                        1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_DMUX_TXB_SEL_O_2_0_K2_E5                                       (0x7<<2) // Transmit mux B data input select enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_DMUX_TXB_SEL_O_2_0_K2_E5_SHIFT                                 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_TX_CTRL_O_24_K2_E5                                             (0x1<<5) // Bit 24: txdrv_c2_in[3]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_TX_CTRL_O_24_K2_E5_SHIFT                                       5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_WIDTH_CHNG_EN_O_K2_E5                                          (0x1<<6) // Enable bit for width_chng module
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_WIDTH_CHNG_EN_O_K2_E5_SHIFT                                    6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_TXTERM_CAL_SEQ_EN_O_K2_E5                                      (0x1<<7) // Txterm calibration enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_TXTERM_CAL_SEQ_EN_O_K2_E5_SHIFT                                7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X304_K2_E5                                                            0x000cc0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X304_TXTERM_CAL_RSEL_K2_E5                                          (0x7<<0) // tx termination calibration comparator threshold select
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X304_TXTERM_CAL_RSEL_K2_E5_SHIFT                                    0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X304_AHB_LN_RXBIT_STRIP_O_K2_E5                                     (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2b00: no bit stripping 2b01: 2x bit stripping 2b10: reserved 2b11: 4x bit stripping
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X304_AHB_LN_RXBIT_STRIP_O_K2_E5_SHIFT                               3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X304_AHB_MAC_WIDTH_O_K2_E5                                          (0x3<<5) // Data width selector for PCS/MAC interface. 2b00: GigE or XAUI 2b01: GigE or XAUI 2b10: RXAUI 2b11: XFI
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X304_AHB_MAC_WIDTH_O_K2_E5_SHIFT                                    5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X305_K2_E5                                                            0x000cc4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X305_AHB_TXMAC_THRESHOLD_O_K2_E5                                    (0x3<<0) // An internal FIFO is included to handle the communication between the external 64-bit data and the internal 20-bit data. The reading operation will begin only when the difference between the write pointer and read pointer for this FIFO reaches ahb_txmac_threshold_o.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X305_AHB_TXMAC_THRESHOLD_O_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X305_AHB_LN_TXBIT_REPEAT_O_K2_E5                                    (0x3<<2) // Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to PCS 2b00: no bit stuffing nor stripping 2b01: 2x bit stuffing and stripping 2b10: reserved 2b11: 4x bit stuffing and stripping
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X305_AHB_LN_TXBIT_REPEAT_O_K2_E5_SHIFT                              2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X305_MODE_8B_O_1_0_K2_E5                                            (0x3<<4) // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data word 8 bits
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X305_MODE_8B_O_1_0_K2_E5_SHIFT                                      4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X305_ENC_EN_O_K2_E5                                                 (0x1<<6) // 8b/10b encoder enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X305_ENC_EN_O_K2_E5_SHIFT                                           6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X305_DEC_EN_O_K2_E5                                                 (0x1<<7) // 8b/10b decoder enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X305_DEC_EN_O_K2_E5_SHIFT                                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X306_K2_E5                                                            0x000cc8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X306_AHB_TX_CDAC_OVR_K2_E5                                          (0xf<<0) // TX termination calibration DAC override. Signal ahb_tx_term_en_cal_ovr must also be asserted to take effect.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X306_AHB_TX_CDAC_OVR_K2_E5_SHIFT                                    0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X306_LN_COMMON_SYNC_TXCLK_EN_O_K2_E5                                (0x1<<4) // Per lane common synchronous clock between PMA, PCS and SoC logic enable bit. 1: in NORM state, lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA or its divided down version and this clock can be used as a common synchronous clock between PMA, PCS and SoC logic. In other state, it is switched to cmu_ck_soc_o[1]. 0: lnX_ck_txb_o is swtiched to cmu_ck_soc_o[1].
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X306_LN_COMMON_SYNC_TXCLK_EN_O_K2_E5_SHIFT                          4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X307_K2_E5                                                            0x000cccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X307_LN_TO_CLK_TXB_WAIT_O_K2_E5                                     (0x1f<<0) // In per lane common synchronous clock mode, after the lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA. The lnX_ok_o will get asserted after lnX_to_clk_txb_wait_o lnX_ck_txb_o cycles.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X307_LN_TO_CLK_TXB_WAIT_O_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X307_PIPE_EN_O_K2_E5                                                (0x1<<5) // PIPE interface block enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X307_PIPE_EN_O_K2_E5_SHIFT                                          5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X307_SAPIS_EN_O_K2_E5                                               (0x1<<6) // SAPIS interface block enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X307_SAPIS_EN_O_K2_E5_SHIFT                                         6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X307_USB_MODE_K2_E5                                                 (0x1<<7) // Signal Detect USB mode enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X307_USB_MODE_K2_E5_SHIFT                                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_K2_E5                                                            0x000cd0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_BLOCK_ENC_CLR_ERR_O_K2_E5                                      (0x1<<1) // 128b/130b encoder clear error
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_BLOCK_ENC_CLR_ERR_O_K2_E5_SHIFT                                1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_BLOCK_DEC_EN_ERR_CHK_O_K2_E5                                   (0x1<<3) // 130b/128b error check enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_BLOCK_DEC_EN_ERR_CHK_O_K2_E5_SHIFT                             3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_BLOCK_DEC_CHK_OS_NMBR_O_2_0_K2_E5                              (0x7<<4) // 130b/128b: number of OS indicating end of data
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_BLOCK_DEC_CHK_OS_NMBR_O_2_0_K2_E5_SHIFT                        4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_BLOCK_DEC_CLR_ERR_O_K2_E5                                      (0x1<<7) // 130b/128b: clear error flag
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_BLOCK_DEC_CLR_ERR_O_K2_E5_SHIFT                                7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X309_K2_E5                                                            0x000cd4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X309_BLOCK_DEC_ERR_THRESHOLD_O_3_0_K2_E5                            (0xf<<0) // 130b/128b: number of sync hdr errors before asserting sync error flag
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X309_BLOCK_DEC_ERR_THRESHOLD_O_3_0_K2_E5_SHIFT                      0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X309_BLOCK_DEC_CHK_BLK_NMBR_O_3_0_K2_E5                             (0xf<<4) // 130b/128b: number of continuous blocks checked
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X309_BLOCK_DEC_CHK_BLK_NMBR_O_3_0_K2_E5_SHIFT                       4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_K2_E5                                                            0x000cd8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_EBUF_RSTN_O_K2_E5                                              (0x1<<0) // Synchronous clear for elastic buffer
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_EBUF_RSTN_O_K2_E5_SHIFT                                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_ALIGN_RSTN_O_K2_E5                                             (0x1<<1) // Synchronous clear for block/symbol aligner
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_ALIGN_RSTN_O_K2_E5_SHIFT                                       1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_EBUF_SKP_ADD_EN_O_K2_E5                                        (0x1<<2) // Elastic buffer SKP add enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_EBUF_SKP_ADD_EN_O_K2_E5_SHIFT                                  2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_RBUF_RSTN_O_K2_E5                                              (0x1<<3) // TX FIFO synchronous reset
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_RBUF_RSTN_O_K2_E5_SHIFT                                        3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_EN_SKPOS_ERR_O_K2_E5                                           (0x1<<5) // Enables skpos error status propagation in Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_EN_SKPOS_ERR_O_K2_E5_SHIFT                                     5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X311_K2_E5                                                            0x000cdcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X311_PIPE_LFREQ_K2_E5                                               (0x3f<<0) // LF value for full swing
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X311_PIPE_LFREQ_K2_E5_SHIFT                                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X311_DIS_BLOCK_ALIGN_CTRL_O_K2_E5                                   (0x1<<6) // Disables the primary input lnX_block_align_control
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X311_DIS_BLOCK_ALIGN_CTRL_O_K2_E5_SHIFT                             6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X311_DIS_EIEOS_CHK_IN_LB_O_K2_E5                                    (0x1<<7) // Disables the EIEOS check in loopback
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X311_DIS_EIEOS_CHK_IN_LB_O_K2_E5_SHIFT                              7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X312_K2_E5                                                            0x000ce0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X312_COEF_FE_LIMIT_EN_O_K2_E5                                       (0x1<<0) // FE TxEq Co-efficient Limiting Enable control
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X312_COEF_FE_LIMIT_EN_O_K2_E5_SHIFT                                 0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X312_RXVALID_DIS_AT_RATE_CHG_O_0_K2_E5                              (0x1<<1) // Value 1 forces rxvalid to be deasserted during rate change to gen 3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X312_RXVALID_DIS_AT_RATE_CHG_O_0_K2_E5_SHIFT                        1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X312_P2S_RBUF_BUF_THRESH_O_3_0_K2_E5                                (0xf<<2) // TX FIFO: specifies how far write pointer need to be ahead of read pointer before almost_full_o is asserted
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X312_P2S_RBUF_BUF_THRESH_O_3_0_K2_E5_SHIFT                          2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X313_K2_E5                                                            0x000ce4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X313_AHB_RX_GEARBOX_DISABLE_O_K2_E5                                 (0x1<<0) // 0: enable rx_gearbox, 1: disable rx_gearbox
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X313_AHB_RX_GEARBOX_DISABLE_O_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X313_AHB_TX_GEARBOX_DISABLE_O_K2_E5                                 (0x1<<1) // 0: enable tx_gearbox, 1: disable tx_gearbox
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X313_AHB_TX_GEARBOX_DISABLE_O_K2_E5_SHIFT                           1
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_K2_E5                                                            0x000ce8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_GEN1_OLD_RXDATA_SRC_K2_E5                                      (0x1<<0) // Mux select for data input to polbit_reg0  0:pma_ln_dfe_err_i , 1: pma_ln_rxdata_i
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_GEN1_OLD_RXDATA_SRC_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_SKIP_CDR_GEN3_O_K2_E5                                          (0x1<<1) // To skip cdr calibration routines for PCIe gen3.  Can be used when PHY is operating in gen1,2 only.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_SKIP_CDR_GEN3_O_K2_E5_SHIFT                                    1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_SKIP_CDR_GEN12_O_K2_E5                                         (0x1<<2) // To skip cdr calibration routines for PCIe gen1,2.  May not be needed in real scenario.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_SKIP_CDR_GEN12_O_K2_E5_SHIFT                                   2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_K2_E5                               (0x1<<3) // Receive amplifier powerdown override, when cisel is high
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_K2_E5_SHIFT                         3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_LN_P2S_RBUF_REALIGN_DIFF_O_K2_E5                               (0xf<<4) // In per lane common synchronous clock mode, ln_p2x_rbuf_realign_diff_o defines the starting difference between write pointer and read pointer when re aligning the pointer of TxFIFO.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_LN_P2S_RBUF_REALIGN_DIFF_O_K2_E5_SHIFT                         4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X315_K2_E5                                                            0x000cecUL //Access:RW   DataWidth:0x8    // Delays the beacon_ena propagation to PMA
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X316_K2_E5                                                            0x000cf0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X316_AHB_BEACON_DELAYED_COUNT_NUMBER_11_8_O_K2_E5                   (0xf<<0) // Delays the beacon_ena propagation to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X316_AHB_BEACON_DELAYED_COUNT_NUMBER_11_8_O_K2_E5_SHIFT             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_K2_E5                                                            0x000cf4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_AHB_BEACON_ENA_OVR_ENA_O_K2_E5                                 (0x1<<0) // Beacon Override Enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_AHB_BEACON_ENA_OVR_ENA_O_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_AHB_BEACON_ENA_OVR_O_K2_E5                                     (0x1<<1) // Beacon Override
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_AHB_BEACON_ENA_OVR_O_K2_E5_SHIFT                               1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_DEC_EN_OVR_O_K2_E5                                             (0x1<<2) // Enables 16b/20b decoder
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_DEC_EN_OVR_O_K2_E5_SHIFT                                       2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_ENC_EN_OVR_O_K2_E5                                             (0x1<<3) // Enables 16b/20b encoder
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_ENC_EN_OVR_O_K2_E5_SHIFT                                       3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_REGP_OVR_3_0_K2_E5                                             (0xf<<4) // Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty  Bit[1]: Overide values for bit reverse  Bit[2]: Overide values for word reverse
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_REGP_OVR_3_0_K2_E5_SHIFT                                       4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X318_K2_E5                                                            0x000cf8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X318_SIGDET_OVR_O_1_0_K2_E5                                         (0x3<<0) // Bit[0]: Overide value. Bit[1] :Override enable for signal detect output
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X318_SIGDET_OVR_O_1_0_K2_E5_SHIFT                                   0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X318_LN_OUT_OVR_1_0_K2_E5                                           (0x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the override, while bit 0 is the override value.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X318_LN_OUT_OVR_1_0_K2_E5_SHIFT                                     2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X318_RXEQ_SIGDET_1_0_K2_E5                                          (0x3<<4) // Override enable for DFE signal detect indicator input. Bit 1 is overide enable , 0 is overide value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X318_RXEQ_SIGDET_1_0_K2_E5_SHIFT                                    4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X319_K2_E5                                                            0x000cfcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X319_TXDETECTRX_OVR_O_1_0_K2_E5                                     (0x3<<0) // Override signal for txdetectrx input - bit 1 is override enable, bit 0 is override value.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X319_TXDETECTRX_OVR_O_1_0_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X319_RXDET_STATUS_OVR_O_1_0_K2_E5                                   (0x3<<2) // Override signal for txdetectrx output - bit 1 is override enable, bit 0 is override value.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X319_RXDET_STATUS_OVR_O_1_0_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X319_LOCKED_OVR_O_1_0_K2_E5                                         (0x3<<4) // Override signal for symbol align locked output. Bit 1 is the override enable, and bit 0 is the override value.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X319_LOCKED_OVR_O_1_0_K2_E5_SHIFT                                   4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O_K2_E5                         (0x1<<6) // override enable for tx_lowpwr_idle_ena output to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O_K2_E5_SHIFT                   6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_K2_E5                             (0x1<<7) // override value for tx_lowpwr_idle_ena output to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_K2_E5_SHIFT                       7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X320_K2_E5                                                            0x000d00UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X321_K2_E5                                                            0x000d04UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X322_K2_E5                                                            0x000d08UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X323_K2_E5                                                            0x000d0cUL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X324_K2_E5                                                            0x000d10UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X325_K2_E5                                                            0x000d14UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_K2_E5                                                            0x000d18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_LN_IN_OVR_O_48_K2_E5                                           (0x1<<0) // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_LN_IN_OVR_O_48_K2_E5_SHIFT                                     0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_AHB_LN_IN_OVR_CHG_FLAG_O_K2_E5                                 (0x1<<1) // Flag to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1' before writing to the corresponding lnX_in_ovr_o_14_1 and set it back to '0' after the write. It is not needed for configuration writes.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_AHB_LN_IN_OVR_CHG_FLAG_O_K2_E5_SHIFT                           1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_REGP1_OVR_O_3_0_K2_E5                                          (0xf<<2) // Overrides for polbit block polbit_regp1 Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty  Bit[1]: Overide values for bit reverse  Bit[2]: Overide values for word reverse
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_REGP1_OVR_O_3_0_K2_E5_SHIFT                                    2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_OOB_DET_EN_K2_E5                                               (0x1<<6) // OOB detect enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_OOB_DET_EN_K2_E5_SHIFT                                         6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_LN_IN_OVR_O_49_K2_E5                                           (0x1<<7) // OOB detect enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_LN_IN_OVR_O_49_K2_E5_SHIFT                                     7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X327_K2_E5                                                            0x000d1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X327_CDR_CTRL_DLY_DLPF_EN_O_K2_E5                                   (0x1f<<0) // Delay between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0  R-platform requires 150ns delay
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X327_CDR_CTRL_DLY_DLPF_EN_O_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X330_K2_E5                                                            0x000d28UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X330_MSM_LN_RATE_EXTRA_BITS_OVR_O_2_0_K2_E5                         (0x7<<0) // Override signals for lane: msm_ln_rate_ow[4:2]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X330_MSM_LN_RATE_EXTRA_BITS_OVR_O_2_0_K2_E5_SHIFT                   0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X330_LN_IN_OVR_O_50_K2_E5                                           (0x1<<3) // Override signals for lane: msm_ln_rate_ow[4:2]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X330_LN_IN_OVR_O_50_K2_E5_SHIFT                                     3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X0_K2_E5                                                              0x001000UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O_K2_E5                                 (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X1_K2_E5                                                              0x001004UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O_K2_E5                                 (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O_K2_E5_SHIFT                           3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O_K2_E5                                 (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X2_K2_E5                                                              0x001008UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O_K2_E5                                 (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X3_K2_E5                                                              0x00100cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X3_PMA_CMU_SEL_O_0_K2_E5                                            (0x1<<0) // CMU Select for lane  0 -	 Select CMU0  1 -	 Select CMU1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X3_PMA_CMU_SEL_O_0_K2_E5_SHIFT                                      0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X3_PMA_TXCLK_SEL_O_1_K2_E5                                          (0x1<<1) // PMA TX Clock Select for TX CDR VCO  0 -	 CMU0 Clock  1 -	 CMU1 Clock
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X3_PMA_TXCLK_SEL_O_1_K2_E5_SHIFT                                    1
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X4_K2_E5                                                              0x001010UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X4_CDRCTRL_DIV_EN_O_1_0_K2_E5                                       (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Divide by 4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X4_CDRCTRL_DIV_EN_O_1_0_K2_E5_SHIFT                                 0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X4_GCFSM_DIV_EN_O_1_0_K2_E5                                         (0x3<<2) // Static divider control for Lane GCFSM clock The only access to this divider. Not an override 4d0:  No division  4d1:  /2 4d2:  /2 4d3:  /4:
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X4_GCFSM_DIV_EN_O_1_0_K2_E5_SHIFT                                   2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X4_LN_CLK_TXB_DIV24OR1_O_K2_E5                                      (0x3<<4) // Divide ratio setting for lnX_ck_txb_o. When ln_common_sync_txclk_en_o is high and in NORM state:                                            2'b00: lnX_ck_txb_o is divided by 1 version of the tx byte clock from PMA.                     2'b01/2'b10: lnX_ck_txb_o is divided by 2 version of the tx byte clock from PMA.                  2'b11: lnX_ck_txb_o is divided by 4 version of the tx byte clock from PMA.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X4_LN_CLK_TXB_DIV24OR1_O_K2_E5_SHIFT                                4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X4_AHB_CHNG_REQ_Z_O_K2_E5                                           (0x1<<6) // Not currently used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X4_AHB_CHNG_REQ_Z_O_K2_E5_SHIFT                                     6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X5_K2_E5                                                              0x001014UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X5_REF_CLK_DIV_EN_O_1_0_K2_E5                                       (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X5_REF_CLK_DIV_EN_O_1_0_K2_E5_SHIFT                                 0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X5_OOB_CLK_DIV_EN_O_1_0_K2_E5                                       (0x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X5_OOB_CLK_DIV_EN_O_1_0_K2_E5_SHIFT                                 2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_K2_E5                                                              0x00101cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_RATE_O_K2_E5                                                (0x3<<0) // Rate control for BIST
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_RATE_O_K2_E5_SHIFT                                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_MODE8B_O_K2_E5                                          (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Generated data word is 8 bits
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_MODE8B_O_K2_E5_SHIFT                                    2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_ERR_O_K2_E5                                             (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 - BIST generator outputs erroneous pattern.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_ERR_O_K2_E5_SHIFT                                       3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_TX_CLOCK_ENABLE_K2_E5                                       (0x1<<4) // Active HIGH clock enable signal for the BIST transmit clock
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_TX_CLOCK_ENABLE_K2_E5_SHIFT                                 4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_CDN_O_K2_E5                                             (0x1<<5) // Bist generator master reset.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_CDN_O_K2_E5_SHIFT                                       5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_WORD_O_K2_E5                                            (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 1 - Bist generator generates double word 16 or 20
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_WORD_O_K2_E5_SHIFT                                      6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_EN_O_K2_E5                                              (0x1<<7) // Bist generator enable.  0 - Bist generator idle. 1 - Bist generator generates data
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_EN_O_K2_E5_SHIFT                                        7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X8_K2_E5                                                              0x001020UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X8_BIST_GEN_CLK_SEL_O_2_0_K2_E5                                     (0x7<<0) // BIST Generation Clock Selection
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X8_BIST_GEN_CLK_SEL_O_2_0_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X8_BIST_GEN_SEND_PREAM_O_K2_E5                                      (0x1<<3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - Bist generator sends preamble.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X8_BIST_GEN_SEND_PREAM_O_K2_E5_SHIFT                                3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X8_BIST_GEN_INSERT_COUNT_O_2_0_K2_E5                                (0x7<<4) // Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is ever inserted into the stream. In 20-bit mode, the product of bist_gen_insert_length x bist_gen_insert_count must be even.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X8_BIST_GEN_INSERT_COUNT_O_2_0_K2_E5_SHIFT                          4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X9_K2_E5                                                              0x001024UL //Access:RW   DataWidth:0x8    // Bist generator low-period control. If not 0, output data enable will be low for this number of words, and then high for en_high_i_X:0 number of words, repeating. If 0, data output enable will be asserted for entire test.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X10_K2_E5                                                             0x001028UL //Access:RW   DataWidth:0x8    // Bist generator low-period control. If not 0, output data enable will be low for this number of words, and then high for en_high_i_X:0 number of words, repeating. If 0, data output enable will be asserted for entire test.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X11_K2_E5                                                             0x00102cUL //Access:RW   DataWidth:0x8    // Bist generator high-period control. Refer to bist_gen_en_low_o and BIST documentation for further information.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X12_K2_E5                                                             0x001030UL //Access:RW   DataWidth:0x8    // Bist generator high-period control. Refer to bist_gen_en_low_o and BIST documentation for further information.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X13_K2_E5                                                             0x001034UL //Access:RW   DataWidth:0x8    // Bist generator - Number of words between insert word insertions. Insertions are done in both pream and data transmission. In 20-bit mode, this number must be even.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X14_K2_E5                                                             0x001038UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X14_BIST_GEN_INSERT_DELAY_O_11_8_K2_E5                              (0xf<<0) // Bist generator - Number of words between insert word insertions. Insertions are done in both pream and data transmission. In 20-bit mode, this number must be even.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X14_BIST_GEN_INSERT_DELAY_O_11_8_K2_E5_SHIFT                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X14_BCHK_EN_O_K2_E5                                                 (0x1<<5) // BIST checker enable Enables BIST RX Control block, which enables the actual BIST RX block when appropriate
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X14_BCHK_EN_O_K2_E5_SHIFT                                           5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X14_BCHK_CLR_O_K2_E5                                                (0x1<<6) // BIST checker clear signal. Zeroes error counter output. Does NOT go through the RX BIST control block
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X14_BCHK_CLR_O_K2_E5_SHIFT                                          6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_K2_E5                                                             0x00103cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_BCHK_SRC_O_1_0_K2_E5                                            (0x3<<0) // BIST checker source. 0 - BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Aligner before Elastic Buffer 2 - BIST uses output of RX loopback mux before Decoder and Polbits 3 - BIST uses output of reg1 flop bank before Interface blocks
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_BCHK_SRC_O_1_0_K2_E5_SHIFT                                      0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_BIST_CHK_DATA_MODE_O_K2_E5                                      (0x1<<3) // Bist checker mode select. 0X0  UDP pattern. 0x1  PRBS pattern
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_BIST_CHK_DATA_MODE_O_K2_E5_SHIFT                                3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_BIST_CHK_LFSR_LENGTH_O_1_0_K2_E5                                (0x3<<4) // BIST PRBS pattern selector.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_BIST_CHK_LFSR_LENGTH_O_1_0_K2_E5_SHIFT                          4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_BIST_RX_CLOCK_ENABLE_K2_E5                                      (0x1<<7) // Active HIGH clock enable signal for the BIST receive clock
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_BIST_RX_CLOCK_ENABLE_K2_E5_SHIFT                                7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X16_K2_E5                                                             0x001040UL //Access:RW   DataWidth:0x8    // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This word should correspond to the alignment character used for the symbol alignment block.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X17_K2_E5                                                             0x001044UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X17_BIST_CHK_PREAM0_O_9_8_K2_E5                                     (0x3<<0) // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This word should correspond to the alignment character used for the symbol alignment block.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X17_BIST_CHK_PREAM0_O_9_8_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X17_BIST_CHK_INSERT_LENGTH_O_2_0_K2_E5                              (0x7<<2) // BIST Checker Insert word length.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X17_BIST_CHK_INSERT_LENGTH_O_2_0_K2_E5_SHIFT                        2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X17_BIST_CHK_SYNC_ON_ZEROS_K2_E5                                    (0x1<<5) // Setting this bit allows BIST to sync to RX value of zero
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X17_BIST_CHK_SYNC_ON_ZEROS_K2_E5_SHIFT                              5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X18_K2_E5                                                             0x001048UL //Access:RW   DataWidth:0x8    // BIST Check Preamble
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X19_K2_E5                                                             0x00104cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X19_BIST_CHK_PREAM1_O_9_8_K2_E5                                     (0x3<<0) // BIST Check Preamble
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X19_BIST_CHK_PREAM1_O_9_8_K2_E5_SHIFT                               0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X20_K2_E5                                                             0x001050UL //Access:RW   DataWidth:0x8    // Bist checker 40-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corresponds to 5 8-bit words. K code is assumed to be 0 in 8-bit mode.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X21_K2_E5                                                             0x001054UL //Access:RW   DataWidth:0x8    // BIST Check User-defined pattern
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X22_K2_E5                                                             0x001058UL //Access:RW   DataWidth:0x8    // BIST Check User-defined pattern
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X23_K2_E5                                                             0x00105cUL //Access:RW   DataWidth:0x8    // BIST Check User-defined pattern
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X24_K2_E5                                                             0x001060UL //Access:RW   DataWidth:0x8    // BIST Check User-defined pattern
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X25_K2_E5                                                             0x001064UL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X26_K2_E5                                                             0x001068UL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X27_K2_E5                                                             0x00106cUL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X28_K2_E5                                                             0x001070UL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X29_K2_E5                                                             0x001074UL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X30_K2_E5                                                             0x001078UL //Access:R    DataWidth:0x8    // Bist errors detected
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X31_K2_E5                                                             0x00107cUL //Access:R    DataWidth:0x8    // Bist errors detected
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X32_K2_E5                                                             0x001080UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 7-0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X33_K2_E5                                                             0x001084UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 15-8
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X34_K2_E5                                                             0x001088UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 23-16
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X35_K2_E5                                                             0x00108cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 31-24
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X36_K2_E5                                                             0x001090UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 39-32
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X37_K2_E5                                                             0x001094UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 47-40
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X38_K2_E5                                                             0x001098UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 55-48
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X39_K2_E5                                                             0x00109cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 63-56
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X40_K2_E5                                                             0x0010a0UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 71-64
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X41_K2_E5                                                             0x0010a4UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 79-72
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X42_K2_E5                                                             0x0010a8UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 87-80
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X43_K2_E5                                                             0x0010acUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 95-88
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X44_K2_E5                                                             0x0010b0UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 103-96
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X45_K2_E5                                                             0x0010b4UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 111-104
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X46_K2_E5                                                             0x0010b8UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 119-112
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X47_K2_E5                                                             0x0010bcUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 127-120
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X48_K2_E5                                                             0x0010c0UL //Access:RW   DataWidth:0x8    // Timing Window length for GCFSM for Gen 1/2 - for the new ICA method
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X49_K2_E5                                                             0x0010c4UL //Access:RW   DataWidth:0x8    // Timing Window length for GCFSM for Gen 3 - for the new ICA method
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X50_K2_E5                                                             0x0010c8UL //Access:RW   DataWidth:0x8    // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA method
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X51_K2_E5                                                             0x0010ccUL //Access:RW   DataWidth:0x8    // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA method
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X52_K2_E5                                                             0x0010d0UL //Access:RW   DataWidth:0x8    // The start length of DFE offset calibration's first cycle is the value of this register multiplied by 4.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X53_K2_E5                                                             0x0010d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X53_GCFSM_DFE_OFFSET_CAL_START_LEN_O_4_0_K2_E5                      (0x1f<<0) // The start length of DFE offset calibration, except for the 1st cycle.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X53_GCFSM_DFE_OFFSET_CAL_START_LEN_O_4_0_K2_E5_SHIFT                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2_K2_E5                               (0x1<<5) // COMLANE or LANE CSR Select for GCFSM Cycle Length registers  0 -	 Select COMLANE registers  1 -	 Select LANE registers
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2_K2_E5_SHIFT                         5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X53_GCFSM_LANE_TW_METHOD_EN_K2_E5                                   (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X53_GCFSM_LANE_TW_METHOD_EN_K2_E5_SHIFT                             6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X53_GCFSM_LANE_PMA_LOAD_OVR_K2_E5                                   (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X53_GCFSM_LANE_PMA_LOAD_OVR_K2_E5_SHIFT                             7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X54_K2_E5                                                             0x0010d8UL //Access:RW   DataWidth:0x8    // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X55_K2_E5                                                             0x0010dcUL //Access:RW   DataWidth:0x8    // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X56_K2_E5                                                             0x0010e0UL //Access:RW   DataWidth:0x8    // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_K2_E5                                                             0x0010e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_OVR_O_27_24_K2_E5                                         (0xf<<0) // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_OVR_O_27_24_K2_E5_SHIFT                                   0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_LANE_OUT_OVR_EN_O_K2_E5                                   (0x1<<4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes data stored in gcfsm_lane_pma_data_ovr_o to override calibration values for the block selected by gcfsm_lane_pma_cal_ovr_o.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_LANE_OUT_OVR_EN_O_K2_E5_SHIFT                             4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_LANE_PMA_LATCH_OVR_O_K2_E5                                (0x1<<5) // GCFSM pma_latch_o override
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_LANE_PMA_LATCH_OVR_O_K2_E5_SHIFT                          5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_LANE_PMA_GO_OVR_O_K2_E5                                   (0x1<<6) // GCFSM pma_go_o override
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_LANE_PMA_GO_OVR_O_K2_E5_SHIFT                             6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_LANE_PMA_READ_OVR_O_K2_E5                                 (0x1<<7) // GCFSM pma_read_o override.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_LANE_PMA_READ_OVR_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X58_K2_E5                                                             0x0010e8UL //Access:RW   DataWidth:0x8    // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X59_K2_E5                                                             0x0010ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X59_GCFSM_LANE_PMA_DATA_OVR_O_11_8_K2_E5                            (0xf<<0) // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X59_GCFSM_LANE_PMA_DATA_OVR_O_11_8_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X60_K2_E5                                                             0x0010f0UL //Access:RW   DataWidth:0x8    // General Calibration Finite State Machine GCFSM overide select, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA compone
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X61_K2_E5                                                             0x0010f4UL //Access:RW   DataWidth:0x8    // General Calibration Finite State Machine GCFSM overide select, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA compone
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X62_K2_E5                                                             0x0010f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X62_LN_MSM_REQ_IN_OVR_O_K2_E5                                       (0x3<<0) // Bit 0:  Override enable for msm_ln_req Bit 1 : Override msm_ln_req
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X62_LN_MSM_REQ_IN_OVR_O_K2_E5_SHIFT                                 0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X62_LN_MSM_FUNC_IN_OVR_O_K2_E5                                      (0x3f<<2) // Bit 2:  Override enable for msm_func Bits [7:3] : Override msm_func
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X62_LN_MSM_FUNC_IN_OVR_O_K2_E5_SHIFT                                2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X65_K2_E5                                                             0x001104UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X65_GCFSM_OVR_O_28_K2_E5                                            (0x1<<0) // Not currently used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X65_GCFSM_OVR_O_28_K2_E5_SHIFT                                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X66_K2_E5                                                             0x001108UL //Access:RW   DataWidth:0x8    // Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X67_K2_E5                                                             0x00110cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X67_CDR_CTRL_DLY_CDR_O_6_0_K2_E5                                    (0x7f<<0) // Number of clock cycles between signal detect indicator
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X67_CDR_CTRL_DLY_CDR_O_6_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_K2_E5                               (0x1<<7) // Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_K2_E5_SHIFT                         7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X68_K2_E5                                                             0x001110UL //Access:RW   DataWidth:0x8    // Number of clock cycles between CISEL assertion
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X69_K2_E5                                                             0x001114UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X69_CDR_CTRL_DLY_LANE_O_9_8_K2_E5                                   (0x3<<0) // Number of clock cycles between CISEL assertion
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X69_CDR_CTRL_DLY_LANE_O_9_8_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X69_CDR_CTRL_START_LEN_O_3_0_K2_E5                                  (0xf<<2) // Number of clock cycles between when CDR control block
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X69_CDR_CTRL_START_LEN_O_3_0_K2_E5_SHIFT                            2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X69_CDR_CTRL_INT_FIL_O_1_0_K2_E5                                    (0x3<<6) // CDR control DLPF positioning control.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X69_CDR_CTRL_INT_FIL_O_1_0_K2_E5_SHIFT                              6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X70_K2_E5                                                             0x001118UL //Access:RW   DataWidth:0x8    // CDR control block cycle length When not in PCIe Gen3.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X71_K2_E5                                                             0x00111cUL //Access:RW   DataWidth:0x8    // CDR control block cycle length When in PCIe Gen3.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X72_K2_E5                                                             0x001120UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X72_CDR_CTRL_MAX_DIFF_O_4_0_K2_E5                                   (0x1f<<0) // Maximum difference from DLPF center point.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X72_CDR_CTRL_MAX_DIFF_O_4_0_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X72_CDR_CTRL_MIN_BOUNCE_O_2_0_K2_E5                                 (0x7<<5) // Maximum difference from DLPF center point.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X72_CDR_CTRL_MIN_BOUNCE_O_2_0_K2_E5_SHIFT                           5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X73_K2_E5                                                             0x001124UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X73_CDR_CTRL_TW_METHOD_EN_K2_E5                                     (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X73_CDR_CTRL_TW_METHOD_EN_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X73_CDR_CONTROL_ATT_CTRL_O_K2_E5                                    (0x1<<1) // ATT wait control. Upon detection of signal, DFE ATT calibration is enabled, without CISEL being asserted to the CDR.  0 - CDR control block will wait for ATT calibration before proceeding 1 - CDR control block will not wait for ATT calibration
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X73_CDR_CONTROL_ATT_CTRL_O_K2_E5_SHIFT                              1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X73_RXEQ_WAIT_EN_O_K2_E5                                            (0x1<<2) // CDR control block wait for DFE signal.  0 - Do not wait for DFE calibration before enabling rx data 1 - Wait for DFE calibration before enabling rx data
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X73_RXEQ_WAIT_EN_O_K2_E5_SHIFT                                      2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X73_CDR_CTRL_DLY_CDR_O_9_7_K2_E5                                    (0x7<<3) // Number of clock cycles between signal detect indicator
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X73_CDR_CTRL_DLY_CDR_O_9_7_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X74_K2_E5                                                             0x001128UL //Access:RW   DataWidth:0x8    // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X75_K2_E5                                                             0x00112cUL //Access:RW   DataWidth:0x8    // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X76_K2_E5                                                             0x001130UL //Access:RW   DataWidth:0x8    // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X77_K2_E5                                                             0x001134UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X77_CDR_CTRL_OUT_OVR_O_29_24_K2_E5                                  (0x3f<<0) // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X77_CDR_CTRL_OUT_OVR_O_29_24_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X77_CDR_CTRL_CAL_LOAD_OVR_K2_E5                                     (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X77_CDR_CTRL_CAL_LOAD_OVR_K2_E5_SHIFT                               6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X78_K2_E5                                                             0x001138UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X78_SYM_ALIGN_ALIGN_POS_O_5_0_K2_E5                                 (0x3f<<0) // Symbol aligner position override enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X78_SYM_ALIGN_ALIGN_POS_O_5_0_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X78_SYM_ALIGN_MODE_O_1_0_K2_E5                                      (0x3<<6) // Symbol aligner mode select.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X78_SYM_ALIGN_MODE_O_1_0_K2_E5_SHIFT                                6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X79_K2_E5                                                             0x00113cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X79_SYM_ALIGN_BYPASS_O_K2_E5                                        (0x1<<0) // Asserting this register will bypass the symbol aligner
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X79_SYM_ALIGN_BYPASS_O_K2_E5_SHIFT                                  0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X80_K2_E5                                                             0x001140UL //Access:RW   DataWidth:0x8    // Number of cycles to wait before forcing exit form EI
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_K2_E5                                                             0x001144UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_EXIT_TIMER_LEN_O_9_8_K2_E5                        (0x3<<0) // Number of cycles to wait before forcing exit form EI
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_EXIT_TIMER_LEN_O_9_8_K2_E5_SHIFT                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_CLR_ERR_O_K2_E5                                   (0x1<<2) // Clears the elec idle control error flag
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_CLR_ERR_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_EI_INFERRED_O_K2_E5                               (0x1<<3) // Override for ei_inferred signal
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_EI_INFERRED_O_K2_E5_SHIFT                         3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O_K2_E5                            (0x1<<4) // Override for ei_mask signal
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O_K2_E5_SHIFT                      4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O_K2_E5                             (0x1<<5) // Override for ei_exit_type signal
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O_K2_E5_SHIFT                       5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_OVR_O_K2_E5                                       (0x1<<6) // EI control override enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_OVR_O_K2_E5_SHIFT                                 6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X82_K2_E5                                                             0x001148UL //Access:RW   DataWidth:0x8    // Number of cycles to wait before entering back into EI
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X83_K2_E5                                                             0x00114cUL //Access:RW   DataWidth:0x8    // Electrical Idle Control signal detect glitch filter counter
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X84_K2_E5                                                             0x001150UL //Access:RW   DataWidth:0x8    // Electrical Idle Control signal detect low filter min value
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X85_K2_E5                                                             0x001154UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X85_ELECIDLE_CTRL_LOCK_TIMER_LEN_O_9_8_K2_E5                        (0x3<<0) // Number of cycles to wait before entering back into EI
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X85_ELECIDLE_CTRL_LOCK_TIMER_LEN_O_9_8_K2_E5_SHIFT                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X85_ELECIDLE_CTRL_TIMER_LEN_SEL_O_1_0_K2_E5                         (0x3<<2) // EI Exit time cycles = timer_len_sel[1:0]+1*exit_timer_len_i[9:0]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X85_ELECIDLE_CTRL_TIMER_LEN_SEL_O_1_0_K2_E5_SHIFT                   2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X85_LOOPBACK_EN_O_K2_E5                                             (0x1<<4) // Control signal to force decoder into loopback mode
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X85_LOOPBACK_EN_O_K2_E5_SHIFT                                       4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X86_K2_E5                                                             0x001158UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X86_FES_LB_ENA_O_K2_E5                                              (0x1<<0) // FES loopback enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X86_FES_LB_ENA_O_K2_E5_SHIFT                                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X86_NES_LB_ENA_O_K2_E5                                              (0x1<<1) // NES loopback enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X86_NES_LB_ENA_O_K2_E5_SHIFT                                        1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X86_RXCLK_LB_ENA_O_K2_E5                                            (0x1<<2) // HS recovered clock to transmit loopback enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X86_RXCLK_LB_ENA_O_K2_E5_SHIFT                                      2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X87_K2_E5                                                             0x00115cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X87_AHB_PMA_LN_RX_BOOST_OVR_O_K2_E5                                 (0x1<<0) // RX boost override enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X87_AHB_PMA_LN_RX_BOOST_OVR_O_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_O_K2_E5                            (0x7f<<1) // RX boost override setting. Thermometer coded.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_O_K2_E5_SHIFT                      1
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X88_K2_E5                                                             0x001160UL //Access:RW   DataWidth:0x8    // RX boost override setting. Thermometer coded.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X89_K2_E5                                                             0x001164UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X89_AHB_PMA_LN_SD_THSEL_DIV1_O_K2_E5                                (0x7<<0) // Signal detect threshold select for Full rate
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X89_AHB_PMA_LN_SD_THSEL_DIV1_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X89_AHB_PMA_LN_SD_THSEL_DIV2_O_K2_E5                                (0x7<<3) // Signal detect threshold select for div-by-2 rate
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X89_AHB_PMA_LN_SD_THSEL_DIV2_O_K2_E5_SHIFT                          3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X89_AHB_PMA_LN_RXUP_O_K2_E5                                         (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X89_AHB_PMA_LN_RXUP_O_K2_E5_SHIFT                                   6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_K2_E5                                (0x1<<7) // RX FL calibration clock DIV4 enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X90_K2_E5                                                             0x001168UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X90_AHB_PMA_LN_SD_THSEL_DIV4_O_K2_E5                                (0x7<<0) // Signal detect threshold select for div-by-4 rate
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X90_AHB_PMA_LN_SD_THSEL_DIV4_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X90_AHB_PMA_LN_AGC_THSEL_O_K2_E5                                    (0x7<<3) // AGC threshold select
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X90_AHB_PMA_LN_AGC_THSEL_O_K2_E5_SHIFT                              3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X90_AHB_PMA_LN_VREGH_O_K2_E5                                        (0x3<<6) // Regulator VREGH setting
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X90_AHB_PMA_LN_VREGH_O_K2_E5_SHIFT                                  6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X91_K2_E5                                                             0x00116cUL //Access:RW   DataWidth:0x8    // RX FL calibration LDHS
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X92_K2_E5                                                             0x001170UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X92_AHB_PMA_LN_RXFL_LDHS_9_8_O_K2_E5                                (0x3<<0) // RX FL calibration LDHS
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X92_AHB_PMA_LN_RXFL_LDHS_9_8_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X92_AHB_PMA_LN_RXVCO_BIAS_O_K2_E5                                   (0xf<<2) // CDR VCO bias setting.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X92_AHB_PMA_LN_RXVCO_BIAS_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O_K2_E5                                (0x1<<6) // DLPF DIV2 enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O_K2_E5_SHIFT                          6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_K2_E5                                 (0x1<<7) // CDR DivN clock divider enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X93_K2_E5                                                             0x001174UL //Access:RW   DataWidth:0x8    // AFE spare controls
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X94_K2_E5                                                             0x001178UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X94_AHB_PMA_LN_CDR_DVDR_O_K2_E5                                     (0x3f<<0) // CDR DivN clock division ratio.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X94_AHB_PMA_LN_CDR_DVDR_O_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X94_AHB_PMA_LN_VREG_O_K2_E5                                         (0x3<<6) // Regulator VREG setting
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X94_AHB_PMA_LN_VREG_O_K2_E5_SHIFT                                   6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X95_K2_E5                                                             0x00117cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X95_AHB_PMA_LN_BB_STEP_O_K2_E5                                      (0xf<<0) // CDR bb_step
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X95_AHB_PMA_LN_BB_STEP_O_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X95_AHB_PMA_LN_INT_STEP_O_K2_E5                                     (0x7<<4) // CDR int step
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X95_AHB_PMA_LN_INT_STEP_O_K2_E5_SHIFT                               4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X95_AHB_PMA_LN_RXDWN_O_K2_E5                                        (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X95_AHB_PMA_LN_RXDWN_O_K2_E5_SHIFT                                  7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X96_K2_E5                                                             0x001180UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X96_AHB_PMA_LN_RXVCOFR_O_K2_E5                                      (0x7<<0) // RXVCOFR override value Enabled by pma_ln_dr_rxvcofr_sel_o
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X96_AHB_PMA_LN_RXVCOFR_O_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X96_AHB_PMA_LN_RXVCOFR_SEL_O_K2_E5                                  (0x1<<3) // Override enable for RXVCOFR override vakue
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X96_AHB_PMA_LN_RXVCOFR_SEL_O_K2_E5_SHIFT                            3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X96_AHB_PMA_LN_RX_SELR_O_K2_E5                                      (0x7<<4) // CTLE R degeneration select
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X96_AHB_PMA_LN_RX_SELR_O_K2_E5_SHIFT                                4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X97_K2_E5                                                             0x001184UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X97_AHB_PMA_LN_RX_SELC_O_K2_E5                                      (0x7<<0) // CTLE C degeneration select
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X97_AHB_PMA_LN_RX_SELC_O_K2_E5_SHIFT                                0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X99_K2_E5                                                             0x00118cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X99_PMA_LN_DFE_BW_SCALE_K2_E5                                       (0x3<<4) // DFE Bandwidth Selection
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X99_PMA_LN_DFE_BW_SCALE_K2_E5_SHIFT                                 4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X99_PMA_LN_PHD_ENA_O_1_0_K2_E5                                      (0x3<<6) // CDR phase detector proportional path enable bit 0: enables D4/D3 data/edge samplers bit 1: enables D1/D2 data/edge samplers
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X99_PMA_LN_PHD_ENA_O_1_0_K2_E5_SHIFT                                6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X100_K2_E5                                                            0x001190UL //Access:RW   DataWidth:0x8    // On-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 3-9: Fine x-direction offset, note bit reversal
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_K2_E5                                                            0x001194UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_EYE_DLY_O_8_8_K2_E5                                     (0x1<<0) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 2-8: Fine x-direction offset, note bit reversal
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_EYE_DLY_O_8_8_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_EYE_SGN_RST_O_K2_E5                                     (0x1<<2) // Reset signal for eye alignment mechanism.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_EYE_SGN_RST_O_K2_E5_SHIFT                               2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_SD_BWSEL_K2_E5                                          (0x1<<3) // RX signal detector bandwidth select. 0: Nominal bandwidth 1: 10% higher bandwidth
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_SD_BWSEL_K2_E5_SHIFT                                    3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_EYE_ENA270_O_K2_E5                                      (0x1<<4) // In eye diagram generation mode, assertion overrides the ck_270 DFE clock "right" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_EYE_ENA270_O_K2_E5_SHIFT                                4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_EYE_ENA90_O_K2_E5                                       (0x1<<5) // In eye diagram generation mode, assertion overrides the ck_90 DFE clock "left" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_EYE_ENA90_O_K2_E5_SHIFT                                 5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X102_K2_E5                                                            0x001198UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X102_PMA_LN_DFE_BIAS_O_3_0_K2_E5                                    (0xf<<0) // DFE bias setting.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X102_PMA_LN_DFE_BIAS_O_3_0_K2_E5_SHIFT                              0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X103_K2_E5                                                            0x00119cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X103_PMA_LN_TX_SR_FASTCAP_O_3_0_K2_E5                               (0xf<<0) // TX driver capacitive slew rate control.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X103_PMA_LN_TX_SR_FASTCAP_O_3_0_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X103_PMA_LN_TXEQ_POLARITY_O_3_0_K2_E5                               (0xf<<4) // TX coefficient polarity enable. Set to "1" for negative polarity. bit 0: Cm bit 1: C0 bit 2: C1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X103_PMA_LN_TXEQ_POLARITY_O_3_0_K2_E5_SHIFT                         4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X104_K2_E5                                                            0x0011a0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X104_PMA_LN_TX_SR_DAC_O_3_0_K2_E5                                   (0xf<<0) // TX slew rate DAC bias current control
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X104_PMA_LN_TX_SR_DAC_O_3_0_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X104_PMA_LN_HSCLK_SEL_O_K2_E5                                       (0x1<<4) // CDR clock divider bypass enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X104_PMA_LN_HSCLK_SEL_O_K2_E5_SHIFT                                 4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X105_K2_E5                                                            0x0011a4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X105_PMA_LN_TX_VREG_LEV_O_4_0_K2_E5                                 (0x1f<<0) // TX driver regulator voltage setting.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X105_PMA_LN_TX_VREG_LEV_O_4_0_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X105_PMA_LN_TXDRV_BLEED_ENA_O_K2_E5                                 (0x1<<5) // TX bleed enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X105_PMA_LN_TXDRV_BLEED_ENA_O_K2_E5_SHIFT                           5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X106_K2_E5                                                            0x0011a8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X106_AHB_PMA_LN_RX_BOOST_OVR_GEN3_O_K2_E5                           (0x1<<0) // RX boost override enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X106_AHB_PMA_LN_RX_BOOST_OVR_GEN3_O_K2_E5_SHIFT                     0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X106_AHB_PMA_LN_RX_BOOSTOVR_GEN3_6_0_O_K2_E5                        (0x7f<<1) // RX boost override setting. Thermometer coded.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X106_AHB_PMA_LN_RX_BOOSTOVR_GEN3_6_0_O_K2_E5_SHIFT                  1
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X107_K2_E5                                                            0x0011acUL //Access:RW   DataWidth:0x8    // RX boost override setting. Thermometer coded.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X108_K2_E5                                                            0x0011b0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X108_AHB_PMA_LN_SD_THSEL_GEN3_O_K2_E5                               (0x7<<0) // Signal detect threshold select for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X108_AHB_PMA_LN_SD_THSEL_GEN3_O_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X108_AHB_PMA_LN_AGC_THSEL_GEN3_O_K2_E5                              (0x7<<3) // AGC threshold select for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X108_AHB_PMA_LN_AGC_THSEL_GEN3_O_K2_E5_SHIFT                        3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X108_AHB_PMA_LN_RXUP_GEN3_O_K2_E5                                   (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X108_AHB_PMA_LN_RXUP_GEN3_O_K2_E5_SHIFT                             6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O_K2_E5                          (0x1<<7) // CDR VCO frequency lock counter divide by 4 enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O_K2_E5_SHIFT                    7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X109_K2_E5                                                            0x0011b4UL //Access:RW   DataWidth:0x8    // RX FL calibration LDHS for Gen3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X110_K2_E5                                                            0x0011b8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X110_AHB_PMA_LN_RXFL_LDHS_GEN3_9_8_O_K2_E5                          (0x3<<0) // RX FL calibration LDHS for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X110_AHB_PMA_LN_RXFL_LDHS_GEN3_9_8_O_K2_E5_SHIFT                    0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X110_AHB_PMA_LN_RXVCO_BIAS_GEN3_O_K2_E5                             (0xf<<2) // CDR VCO bias setting.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X110_AHB_PMA_LN_RXVCO_BIAS_GEN3_O_K2_E5_SHIFT                       2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X110_AHB_PMA_LN_DLPF_DIV2_ENA_GEN3_O_K2_E5                          (0x1<<6) // DLPF DIV2 enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X110_AHB_PMA_LN_DLPF_DIV2_ENA_GEN3_O_K2_E5_SHIFT                    6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O_K2_E5                           (0x1<<7) // CDR DivN clock divider enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O_K2_E5_SHIFT                     7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X111_K2_E5                                                            0x0011bcUL //Access:RW   DataWidth:0x8    // AFE spare controls for Gen3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X112_K2_E5                                                            0x0011c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X112_AHB_PMA_LN_CDR_DVDR_GEN3_O_K2_E5                               (0x3f<<0) // CDR DivN clock divider ratio..
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X112_AHB_PMA_LN_CDR_DVDR_GEN3_O_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X112_AHB_PMA_LN_VREG_GEN3_O_K2_E5                                   (0x3<<6) // Regulator VREG setting for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X112_AHB_PMA_LN_VREG_GEN3_O_K2_E5_SHIFT                             6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X113_K2_E5                                                            0x0011c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X113_AHB_PMA_LN_BB_STEP_GEN3_O_K2_E5                                (0xf<<0) // CDR bb_step for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X113_AHB_PMA_LN_BB_STEP_GEN3_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X113_AHB_PMA_LN_INT_STEP_GEN3_O_K2_E5                               (0x7<<4) // CDR int step for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X113_AHB_PMA_LN_INT_STEP_GEN3_O_K2_E5_SHIFT                         4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X113_AHB_PMA_LN_RXDWN_GEN3_O_K2_E5                                  (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X113_AHB_PMA_LN_RXDWN_GEN3_O_K2_E5_SHIFT                            7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X114_K2_E5                                                            0x0011c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X114_AHB_PMA_LN_RXVCOFR_GEN3_O_K2_E5                                (0x7<<0) // RXVCOFR override value for Gen3 Enabled by pma_ln_dr_rxvcofr_sel_o
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X114_AHB_PMA_LN_RXVCOFR_GEN3_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X114_AHB_PMA_LN_RX_SELR_GEN3_O_K2_E5                                (0x7<<3) // CTLE R degeneration select for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X114_AHB_PMA_LN_RX_SELR_GEN3_O_K2_E5_SHIFT                          3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X114_AHB_PMA_LN_VREGH_GEN3_O_K2_E5                                  (0x3<<6) // Not currently used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X114_AHB_PMA_LN_VREGH_GEN3_O_K2_E5_SHIFT                            6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X115_K2_E5                                                            0x0011ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X115_AHB_PMA_LN_RX_SELC_GEN3_O_K2_E5                                (0x7<<0) // CTLE R degeneration select for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X115_AHB_PMA_LN_RX_SELC_GEN3_O_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X119_K2_E5                                                            0x0011dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X119_AHB_TX_CXP_MARGIN_K2_E5                                        (0xf<<0) // Value to minus/add from the calibrated txterm value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X119_AHB_TX_CXP_MARGIN_K2_E5_SHIFT                                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X119_AHB_TX_CXN_MARGIN_K2_E5                                        (0xf<<4) // Value to minus/add from the calibrated txterm value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X119_AHB_TX_CXN_MARGIN_K2_E5_SHIFT                                  4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X120_K2_E5                                                            0x0011e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X120_AHB_TX_TC_WAIT_NEXT_CMP_K2_E5                                  (0xf<<0) // in txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator  the register ix X2 is the actual number of wait cycle
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X120_AHB_TX_TC_WAIT_NEXT_CMP_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X120_AHB_TX_TC_WAIT_NEXT_SAMPLE_K2_E5                               (0x7<<4) // in txterm calibration, the number refclk cycles to wait before sampling the up from the same comparator
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X120_AHB_TX_TC_WAIT_NEXT_SAMPLE_K2_E5_SHIFT                         4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_K2_E5                                                            0x0011e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_TC_CMP_OUT_NUM_SAMPLES_K2_E5                            (0xf<<0) // in txterm calibration, the number of samples to take from the same comparator
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_TC_CMP_OUT_NUM_SAMPLES_K2_E5_SHIFT                      0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_CXP_MARGIN_ADD_0_K2_E5                                  (0x1<<4) // when 1, the final tx term value is calibrated txterm value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_CXP_MARGIN_ADD_0_K2_E5_SHIFT                            4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_CXN_MARGIN_ADD_0_K2_E5                                  (0x1<<5) // when 1, the final tx term value is calibrated txterm value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_CXN_MARGIN_ADD_0_K2_E5_SHIFT                            5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_CX_OVR_ENA_K2_E5                                        (0x1<<6) // enable override calibrated txterm value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_CX_OVR_ENA_K2_E5_SHIFT                                  6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_TERM_EN_CAL_OVR_K2_E5                                   (0x1<<7) // Debug feature, when set forces circuit to be affected by ahb_tx_cdac_ovr
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_TERM_EN_CAL_OVR_K2_E5_SHIFT                             7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X122_K2_E5                                                            0x0011e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X122_AHB_TX_CXP_OVR_K2_E5                                           (0xf<<0) // override calibrated txterm value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X122_AHB_TX_CXP_OVR_K2_E5_SHIFT                                     0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X122_AHB_TX_CXN_OVR_K2_E5                                           (0xf<<4) // override calibrated txterm value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X122_AHB_TX_CXN_OVR_K2_E5_SHIFT                                     4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X123_K2_E5                                                            0x0011ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X123_TX_CTRL_O_0_K2_E5                                              (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not currently used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X123_TX_CTRL_O_0_K2_E5_SHIFT                                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X123_TX_CTRL_O_7_2_K2_E5                                            (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_slew_sld[1:0]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X123_TX_CTRL_O_7_2_K2_E5_SHIFT                                      2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X124_K2_E5                                                            0x0011f0UL //Access:RW   DataWidth:0x8    // Bits 12:8: txdrv_c1_in[4:0] Bits 15:13: txdrv_c2_in[2:0]
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X125_K2_E5                                                            0x0011f4UL //Access:RW   DataWidth:0x8    // Bits 19-16: txdrv_cm_in[3:0]  Bits 22-20: tx_slew_sld3f[2:0] Bit 23: txdrv_preem_1lsb_mode
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_K2_E5                                                            0x0011f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_EN_O_K2_E5                                                (0x1<<0) // DFE block enable signal.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_EN_O_K2_E5_SHIFT                                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_RATE_OW_O_2_0_K2_E5                                    (0x7<<1) // These bits have similar functionality as rxeq_rate_ow_o_2_0 bits in COMLANE CSR. These are used mainly in COMBINATION modes of operation. They are logically OR'ed with the bits in COMLANE.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_RATE_OW_O_2_0_K2_E5_SHIFT                              1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_RATE1_CAL_EN_O_3_K2_E5                                 (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_RATE1_CAL_EN_O_3_K2_E5_SHIFT                           4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_RATE2_CAL_EN_O_4_K2_E5                                 (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_RATE2_CAL_EN_O_4_K2_E5_SHIFT                           5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_RATE3_CAL_EN_O_5_K2_E5                                 (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_RATE3_CAL_EN_O_5_K2_E5_SHIFT                           6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_FORCE_CAL_O_6_K2_E5                                    (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_FORCE_CAL_O_6_K2_E5_SHIFT                              7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X127_K2_E5                                                            0x0011fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X127_RXEQ_CONT_CAL_O_6_0_K2_E5                                      (0x7f<<0) // 0 : enables att calibration 1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6: enables tap5 dfe calibration This register Is not bit reversed
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X127_RXEQ_CONT_CAL_O_6_0_K2_E5_SHIFT                                0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X128_K2_E5                                                            0x001200UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X128_RXEQ_INIT_CAL_O_6_0_K2_E5                                      (0x7f<<0) // 0 : enables att calibration 1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6: enables tap5 dfe calibration This register Is not bit reversed
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X128_RXEQ_INIT_CAL_O_6_0_K2_E5_SHIFT                                0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X130_K2_E5                                                            0x001208UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X130_RXEQ_RATE1_ATT_START_O_3_0_K2_E5                               (0xf<<0) // ATT start value for rate1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X130_RXEQ_RATE1_ATT_START_O_3_0_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X130_RXEQ_RATE1_BOOST_START_O_3_0_K2_E5                             (0xf<<4) // Boost start value for rate1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X130_RXEQ_RATE1_BOOST_START_O_3_0_K2_E5_SHIFT                       4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X131_K2_E5                                                            0x00120cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X131_RXEQ_RATE2_ATT_START_O_3_0_K2_E5                               (0xf<<0) // ATT start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X131_RXEQ_RATE2_ATT_START_O_3_0_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X131_RXEQ_RATE2_BOOST_START_O_3_0_K2_E5                             (0xf<<4) // Boost start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X131_RXEQ_RATE2_BOOST_START_O_3_0_K2_E5_SHIFT                       4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X132_K2_E5                                                            0x001210UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X132_RXEQ_RATE2_TAP1_START_O_6_0_K2_E5                              (0x7f<<0) // DFE Tap1 start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X132_RXEQ_RATE2_TAP1_START_O_6_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X133_K2_E5                                                            0x001214UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X133_RXEQ_RATE2_TAP2_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap2 start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X133_RXEQ_RATE2_TAP2_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X134_K2_E5                                                            0x001218UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X134_RXEQ_RATE2_TAP3_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap3 start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X134_RXEQ_RATE2_TAP3_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X135_K2_E5                                                            0x00121cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X135_RXEQ_RATE2_TAP4_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap4 start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X135_RXEQ_RATE2_TAP4_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X136_K2_E5                                                            0x001220UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X136_RXEQ_RATE2_TAP5_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap5 start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X136_RXEQ_RATE2_TAP5_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X137_K2_E5                                                            0x001224UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X137_RXEQ_RATE3_ATT_START_O_3_0_K2_E5                               (0xf<<0) // ATT start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X137_RXEQ_RATE3_ATT_START_O_3_0_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X137_RXEQ_RATE3_BOOST_START_O_3_0_K2_E5                             (0xf<<4) // Boost start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X137_RXEQ_RATE3_BOOST_START_O_3_0_K2_E5_SHIFT                       4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X138_K2_E5                                                            0x001228UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X138_RXEQ_RATE3_TAP1_START_O_6_0_K2_E5                              (0x7f<<0) // DFE Tap1 start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X138_RXEQ_RATE3_TAP1_START_O_6_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X139_K2_E5                                                            0x00122cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X139_RXEQ_RATE3_TAP2_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap2 start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X139_RXEQ_RATE3_TAP2_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X140_K2_E5                                                            0x001230UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X140_RXEQ_RATE3_TAP3_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap3 start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X140_RXEQ_RATE3_TAP3_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X141_K2_E5                                                            0x001234UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X141_RXEQ_RATE3_TAP4_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap4 start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X141_RXEQ_RATE3_TAP4_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X142_K2_E5                                                            0x001238UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X142_RXEQ_RATE3_TAP5_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap5 start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X142_RXEQ_RATE3_TAP5_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X143_K2_E5                                                            0x00123cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X143_RXEQ_SUPERBST_AUTOCAL_DIS_K2_E5                                (0x1<<0) // Disable auto cal w/ rx_superbst
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X143_RXEQ_SUPERBST_AUTOCAL_DIS_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X143_BOOST_MAX_LIMIT_O_K2_E5                                        (0xf<<1) // Max limit value for BOOST auto-calibration
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X143_BOOST_MAX_LIMIT_O_K2_E5_SHIFT                                  1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X143_BOOST_MAX_LIMIT_EN_O_K2_E5                                     (0x1<<5) // Enable Max limiting for BOOST auto-calibration
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X143_BOOST_MAX_LIMIT_EN_O_K2_E5_SHIFT                               5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X143_RX_ATT_BOOST_CAL_O_1_0_K2_E5                                   (0x3<<6) // rx_att_boost setting used during ATT calibration
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X143_RX_ATT_BOOST_CAL_O_1_0_K2_E5_SHIFT                             6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X144_K2_E5                                                            0x001240UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X144_RX_ATT_BOOST_NORM_O_1_0_K2_E5                                  (0x3<<0) // rx_att_boost setting used after ATT calibration
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X144_RX_ATT_BOOST_NORM_O_1_0_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X144_RXEQ_BOOST_ADJ_EN_O_K2_E5                                      (0x1<<2) // boost_adj_en
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X144_RXEQ_BOOST_ADJ_EN_O_K2_E5_SHIFT                                2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X144_RXEQ_BOOST_ADJ_DIR_O_K2_E5                                     (0x1<<3) // boost_adj_dir
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X144_RXEQ_BOOST_ADJ_DIR_O_K2_E5_SHIFT                               3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X144_RXEQ_BOOST_ADJ_VAL_O_K2_E5                                     (0xf<<4) // boost_adj_val This register Is not bit reversed
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X144_RXEQ_BOOST_ADJ_VAL_O_K2_E5_SHIFT                               4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X145_K2_E5                                                            0x001244UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X145_CMP_OFFSET_AVG_MAX_NUMSAMPLES_6_0_K2_E5                        (0x7f<<0) // Max number of samples to be used for CMP Offset Noise Averaging
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X145_CMP_OFFSET_AVG_MAX_NUMSAMPLES_6_0_K2_E5_SHIFT                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X145_CMP_OFFSET_AVG_EN_O_K2_E5                                      (0x1<<7) // CMP Offset Noise Averaging Enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X145_CMP_OFFSET_AVG_EN_O_K2_E5_SHIFT                                7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X146_K2_E5                                                            0x001248UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X147_K2_E5                                                            0x00124cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X147_RXEQ_DFE_TAP_PD_WAIT_11_8_K2_E5                                (0xf<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X147_RXEQ_DFE_TAP_PD_WAIT_11_8_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X147_PMA_LN_DFE_OFS_CAL_ENA_K2_E5                                   (0x3<<4) // DFE offset calibration enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X147_PMA_LN_DFE_OFS_CAL_ENA_K2_E5_SHIFT                             4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS_K2_E5                                (0x1<<6) // Disable auto cal w/ rx_att_gain
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS_K2_E5_SHIFT                          6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X147_RXEQ_SUPERBST_EN_INVERT_O_K2_E5                                (0x1<<7) // Inverts the polarity of superboost_en before assigning to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X147_RXEQ_SUPERBST_EN_INVERT_O_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X148_K2_E5                                                            0x001250UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X148_RXEQ_OVR_LOAD_EN_O_6_0_K2_E5                                   (0x7f<<0) // Override for RXEQ_CTRL output register load enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X148_RXEQ_OVR_LOAD_EN_O_6_0_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X148_RXEQ_OVR_EN_O_K2_E5                                            (0x1<<7) // Override enable for DFE signals.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X148_RXEQ_OVR_EN_O_K2_E5_SHIFT                                      7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X149_K2_E5                                                            0x001254UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X149_RXEQ_OVR_LOAD_O_6_0_K2_E5                                      (0x7f<<0) // Override for RXEQ_CTRL output register load value.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X149_RXEQ_OVR_LOAD_O_6_0_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X149_RXEQ_OVR_LATCH_O_K2_E5                                         (0x1<<7) // Override for DFE latch signal. Negative edge causes AFE to store values of DFE output registers.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X149_RXEQ_OVR_LATCH_O_K2_E5_SHIFT                                   7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_K2_E5                                                            0x001258UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_RXEQ_DFE_CMP_SEL_OVR_O_2_0_K2_E5                               (0x7<<0) // Override value for comparator calibration select. Enabled by rxeq_ovr_en_o: 1: Calibrate DFE comparator 1 2: Calibrate DFE comparator 2 3: Calibrate DFE comparator 3 4: Calibrate DFE comparator 4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_RXEQ_DFE_CMP_SEL_OVR_O_2_0_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_RXEQ_ATT_GAIN_OVR_K2_E5                                        (0x3<<3) // Override the value of rx_att_gain output to PMA when rx_att_gain_autocal_dis=1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_RXEQ_ATT_GAIN_OVR_K2_E5_SHIFT                                  3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_RXEQ_SUPERBST_ENA_OVR_K2_E5                                    (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_autocal_dis=1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_RXEQ_SUPERBST_ENA_OVR_K2_E5_SHIFT                              5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6_K2_E5                           (0x1<<6) // DFE TAP CMP no offset override enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6_K2_E5_SHIFT                     6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_DFE_TAP_OVR_EN_O_7_K2_E5                                       (0x1<<7) // DFE TAP override enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_DFE_TAP_OVR_EN_O_7_K2_E5_SHIFT                                 7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X151_K2_E5                                                            0x00125cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X151_DFE_OFFSET_CAL_TAP_EN_OVR_O_7_3_K2_E5                          (0x1f<<0) // DFE offset calibration TAP enable override
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X151_DFE_OFFSET_CAL_TAP_EN_OVR_O_7_3_K2_E5_SHIFT                    0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0_K2_E5                            (0x1<<5) // DFE offset calibrated value override enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0_K2_E5_SHIFT                      5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X151_DFE_OFFSET_CAL_EN_OVR_O_1_K2_E5                                (0x1<<6) // DFE offset cal enable override
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X151_DFE_OFFSET_CAL_EN_OVR_O_1_K2_E5_SHIFT                          6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X151_DFE_CMP_CAL_EN_OVR_O_2_K2_E5                                   (0x1<<7) // DFE comparator cal enable override
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X151_DFE_CMP_CAL_EN_OVR_O_2_K2_E5_SHIFT                             7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X152_K2_E5                                                            0x001260UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X152_DFE_TAP1_OVR_VAL_O_6_0_K2_E5                                   (0x7f<<0) // DFE Tap 1 Override Value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X152_DFE_TAP1_OVR_VAL_O_6_0_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X153_K2_E5                                                            0x001264UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X153_DFE_TAP2_OVR_VAL_O_5_0_K2_E5                                   (0x3f<<0) // DFE Tap 2 Override Value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X153_DFE_TAP2_OVR_VAL_O_5_0_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X154_K2_E5                                                            0x001268UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X154_DFE_TAP3_OVR_VAL_O_5_0_K2_E5                                   (0x3f<<0) // DFE Tap 3 Override Value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X154_DFE_TAP3_OVR_VAL_O_5_0_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X155_K2_E5                                                            0x00126cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X155_DFE_TAP4_OVR_VAL_O_5_0_K2_E5                                   (0x3f<<0) // DFE Tap 4 Override Value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X155_DFE_TAP4_OVR_VAL_O_5_0_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X156_K2_E5                                                            0x001270UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X156_DFE_TAP5_OVR_VAL_O_5_0_K2_E5                                   (0x3f<<0) // DFE Tap 5 Override Value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X156_DFE_TAP5_OVR_VAL_O_5_0_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X157_K2_E5                                                            0x001274UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X157_TXEQ_ADAPT_EN_O_0_K2_E5                                        (0x1<<0) // TX Equalizer adaptation function enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X157_TXEQ_ADAPT_EN_O_0_K2_E5_SHIFT                                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X157_TXEQ_ERR_SIGN_O_1_K2_E5                                        (0x1<<1) // TX Equalizer Error Sign
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X157_TXEQ_ERR_SIGN_O_1_K2_E5_SHIFT                                  1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X157_TXEQ_FW_OVRIDE_O_2_K2_E5                                       (0x1<<2) // TX Equalization Firmware over ride  0 -	 Disable firmware based adaptation  1 -	 Enbale firmware based adaptation
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X157_TXEQ_FW_OVRIDE_O_2_K2_E5_SHIFT                                 2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X158_K2_E5                                                            0x001278UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X158_TXEQ_ERR_STAT_I_1_0_K2_E5                                      (0x3<<0) // TX Equalization error state
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X158_TXEQ_ERR_STAT_I_1_0_K2_E5_SHIFT                                0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X159_K2_E5                                                            0x00127cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X159_TXEQ_OVER_EQ_CNT_I_9_8_K2_E5                                   (0x3<<0) // Over equalization count 9-8
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X159_TXEQ_OVER_EQ_CNT_I_9_8_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X160_K2_E5                                                            0x001280UL //Access:R    DataWidth:0x8    // Over equalization count 7-0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X161_K2_E5                                                            0x001284UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X161_TXEQ_UNDER_EQ_CNT_I_9_8_K2_E5                                  (0x3<<0) // Under equalization count 9-8
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X161_TXEQ_UNDER_EQ_CNT_I_9_8_K2_E5_SHIFT                            0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X162_K2_E5                                                            0x001288UL //Access:R    DataWidth:0x8    // Under equalization count 7-0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X163_K2_E5                                                            0x00128cUL //Access:RW   DataWidth:0x8    // TX Equalizer Training Pattern
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X164_K2_E5                                                            0x001290UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X164_TXEQ_TRAINING_PATT_O_8_K2_E5                                   (0x1<<0) // TX Equalizer Training Pattern
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X164_TXEQ_TRAINING_PATT_O_8_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X165_K2_E5                                                            0x001294UL //Access:RW   DataWidth:0x8    // Mask bit for Txeq training pattern
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X166_K2_E5                                                            0x001298UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X166_TXEQ_DONT_CARE_O_8_K2_E5                                       (0x1<<0) // Mask bit for Txeq training pattern
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X166_TXEQ_DONT_CARE_O_8_K2_E5_SHIFT                                 0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X167_K2_E5                                                            0x00129cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X167_TXEQ_RXRECAL_INIT_O_7_K2_E5                                    (0x1<<0) // This bit has similar function as txeq_rxrecal_init  in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X167_TXEQ_RXRECAL_INIT_O_7_K2_E5_SHIFT                              0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X168_K2_E5                                                            0x0012a0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X168_INIT_RX_PRESET_HINT_EN_O_K2_E5                                 (0x1<<0) // Enable for primary input lnx_rx_preset_hint during init cal.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X168_INIT_RX_PRESET_HINT_EN_O_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X168_RECAL_RX_PRESET_HINT_EN_O_K2_E5                                (0x1<<1) // Enable for primary input lnx_rx_preset_hint during recal.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X168_RECAL_RX_PRESET_HINT_EN_O_K2_E5_SHIFT                          1
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X169_K2_E5                                                            0x0012a4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X169_TXEQ_RXRECAL_DONE_I_0_K2_E5                                    (0x1<<0) // TX - RECAL RX Equalization status
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X169_TXEQ_RXRECAL_DONE_I_0_K2_E5_SHIFT                              0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X170_K2_E5                                                            0x0012a8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X170_BLOCK_DEC_ERR_K2_E5                                            (0x1<<0) // decoder sync header error
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X170_BLOCK_DEC_ERR_K2_E5_SHIFT                                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X201_K2_E5                                                            0x001324UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X201_CDFE_EN_O_0_K2_E5                                              (0x1<<0) // cdfe enable bit.  1: enable cdfe when rate is 2'b01 or 2'b10.  0: disable cdfe.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X201_CDFE_EN_O_0_K2_E5_SHIFT                                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X201_CDFE_WORD_OV_O_1_0_K2_E5                                       (0x3<<1) // The cdfe input word_i overwrite.                                                                                                         2'b00: the word_i input for cdfe block is internally generated.                                     2'b10: the word_i input for cdfe block is set to 0 8-bit or 10-bit mode.                                                       2'b11: the word_i input for cdfe block is set to 1 16-bit or 20-bit mode.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X201_CDFE_WORD_OV_O_1_0_K2_E5_SHIFT                                 1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X201_CDFE_MODE_8B_OV_O_1_0_K2_E5                                    (0x3<<3) // The cdfe input mode_8b_i overwrite.                                                                                                         2'b00: the mode_8b_i input for cdfe block is internally generated.                                      2'b01: the mode_8b_i input for cdfe block is set to 0 10-bit or 20-bit mode.                                                      2'b11: the mode_8b_i input for cdfe block is set to 1 8-bit or 16-bit mode.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X201_CDFE_MODE_8B_OV_O_1_0_K2_E5_SHIFT                              3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X201_CDFE_RATE_OV_O_2_0_K2_E5                                       (0x7<<5) // The cdfe input rate_i[1:0] overwrite.                                                                                                         3'b0xx: the rate_i input for cdfe block is internally generated.                                     3'b1xx: the rate_i[1:0] input for cdfe block is set to cdfe_rate_ov_o[1:0]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X201_CDFE_RATE_OV_O_2_0_K2_E5_SHIFT                                 5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X202_K2_E5                                                            0x001328UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X203_K2_E5                                                            0x00132cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X203_CDFE_GO_K2_E5                                                  (0x1<<4) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X203_CDFE_GO_K2_E5_SHIFT                                            4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X203_CDFE_LN_FORCE_CAL_K2_E5                                        (0x1<<5) // The cdfe force calibration enable.  1: enable force cdfe calibration.  0: disable force cdfe calibration.  Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X203_CDFE_LN_FORCE_CAL_K2_E5_SHIFT                                  5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X203_CDFE_LN_RATE_CHANGE_CAL_K2_E5                                  (0x1<<6) // The cdfe force calibration enable.  1: enable force cdfe calibration.  0: disable force cdfe calibration.  Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X203_CDFE_LN_RATE_CHANGE_CAL_K2_E5_SHIFT                            6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X203_CDFE_LN_EI_EXIT_CAL_K2_E5                                      (0x1<<7) // EI exit cdfe calibration enable.                                                                                                   1: the cdfe calibration is enabled when EI exits and when rate is  2'b01 or 2'b10.                                  0: the cdfe calibration is disabled when EI exits.                                                                    Note: EI exit cdfe calibration is only enabled when EI exit edfe calibration is also enabled.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X203_CDFE_LN_EI_EXIT_CAL_K2_E5_SHIFT                                7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_K2_E5                                                            0x001330UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_CONT_CAL_K2_E5                                         (0x1<<0) // Continuous cdfe calibration enable.                                                                                            1: the continuous cdfe calibration is enabled when the rate is  2'b01 or 2'b10.                                  0: the continuous cdfe calibration is disabled.                                                                        Note: Continuout cdfe calibration is only enabled when continuous edfe calibration is also enabled.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_CONT_CAL_K2_E5_SHIFT                                   0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL_K2_E5                             (0x1<<1) // Enables cdfe calibration during Txeq adaptation phase.                                                                                            1: the cdfe calibration is enabled when the rate is  2'b10.                                  0: the cdfe calibration is disabled.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL_K2_E5_SHIFT                       1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL_K2_E5                              (0x1<<2) // Enables cdfe calibration post Txeq adaptation.                                                                                            1: the cdfe calibration is enabled when the rate is  2'b10.                                  0: the cdfe calibration is disabled.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL_K2_E5_SHIFT                        2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_RATE3_CAL_EN_K2_E5                                     (0x1<<3) // Enables the cdfe calibration in rate3.  1: enables cdfe calibration.  0: disables cdfe calibration.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_RATE3_CAL_EN_K2_E5_SHIFT                               3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_RATE2_CAL_EN_K2_E5                                     (0x1<<4) // Enables the cdfe calibration in rate2.  1: enables cdfe calibration.  0: disables cdfe calibration.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_RATE2_CAL_EN_K2_E5_SHIFT                               4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X205_K2_E5                                                            0x001334UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during init cal in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X206_K2_E5                                                            0x001338UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during continuos cal in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X207_K2_E5                                                            0x00133cUL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during re-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X208_K2_E5                                                            0x001340UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X208_AHB_CDFE_COARSE_DLL_OV_EN_K2_E5                                (0x1<<7) // cdfe coarse dll overwrite enable.  1: enable coarse dll overwrite for cdfe.  0: disable coarse dll overwrite for cdfe.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X208_AHB_CDFE_COARSE_DLL_OV_EN_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X213_K2_E5                                                            0x001354UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during txeq adaptation phase in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X214_K2_E5                                                            0x001358UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during post  txeq adaptation  in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X215_K2_E5                                                            0x00135cUL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during init cal in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X216_K2_E5                                                            0x001360UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during continuos cal in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X217_K2_E5                                                            0x001364UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during re-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X220_K2_E5                                                            0x001370UL //Access:RW   DataWidth:0x8    // Start value for dlev_ref.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X221_K2_E5                                                            0x001374UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X221_CDFE_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_K2_E5                   (0x1f<<0) // Enables copying of adapted tap values to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enables/disables copying to tap3 bit[3] : enables/disables copying to tap4 bit[4] : enables/disables copying to tap5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X221_CDFE_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_K2_E5_SHIFT             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X222_K2_E5                                                            0x001378UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X222_CDFE_NON_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_K2_E5               (0x1f<<0) // Enables copying of adapted tap values to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enables/disables copying to tap3 bit[3] : enables/disables copying to tap4 bit[4] : enables/disables copying to tap5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X222_CDFE_NON_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_K2_E5_SHIFT         0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X223_K2_E5                                                            0x00137cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X223_AHB_CDFE_CMP1_TAP1_OFFSET_K2_E5                                (0x7f<<0) // Override for CMP1 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[1]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X223_AHB_CDFE_CMP1_TAP1_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X224_K2_E5                                                            0x001380UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X224_AHB_CDFE_CMP1_TAP2_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP1 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[2]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X224_AHB_CDFE_CMP1_TAP2_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X225_K2_E5                                                            0x001384UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X225_AHB_CDFE_CMP1_TAP3_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP1 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[3]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X225_AHB_CDFE_CMP1_TAP3_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X226_K2_E5                                                            0x001388UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X226_AHB_CDFE_CMP1_TAP4_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP1 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[4]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X226_AHB_CDFE_CMP1_TAP4_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X227_K2_E5                                                            0x00138cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X227_AHB_CDFE_CMP1_TAP5_OFFSET_K2_E5                                (0x3f<<0) // Override for CMP1 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[5]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X227_AHB_CDFE_CMP1_TAP5_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X228_K2_E5                                                            0x001390UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X228_AHB_CDFE_CMP2_TAP1_OFFSET_K2_E5                                (0x7f<<0) // Override for CMP2 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[1]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X228_AHB_CDFE_CMP2_TAP1_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X229_K2_E5                                                            0x001394UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X229_AHB_CDFE_CMP2_TAP2_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP2 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[2]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X229_AHB_CDFE_CMP2_TAP2_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X230_K2_E5                                                            0x001398UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X230_AHB_CDFE_CMP2_TAP3_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP2 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[3]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X230_AHB_CDFE_CMP2_TAP3_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X231_K2_E5                                                            0x00139cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X231_AHB_CDFE_CMP2_TAP4_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP2 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[4]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X231_AHB_CDFE_CMP2_TAP4_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X232_K2_E5                                                            0x0013a0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X232_AHB_CDFE_CMP2_TAP5_OFFSET_K2_E5                                (0x3f<<0) // Override for CMP2 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[5]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X232_AHB_CDFE_CMP2_TAP5_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X233_K2_E5                                                            0x0013a4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X233_AHB_CDFE_CMP3_TAP1_OFFSET_K2_E5                                (0x7f<<0) // Override for CMP3 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[1]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X233_AHB_CDFE_CMP3_TAP1_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X234_K2_E5                                                            0x0013a8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X234_AHB_CDFE_CMP3_TAP2_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP3 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[2]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X234_AHB_CDFE_CMP3_TAP2_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X235_K2_E5                                                            0x0013acUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X235_AHB_CDFE_CMP3_TAP3_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP3 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[3]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X235_AHB_CDFE_CMP3_TAP3_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X236_K2_E5                                                            0x0013b0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X236_AHB_CDFE_CMP3_TAP4_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP3 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[4]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X236_AHB_CDFE_CMP3_TAP4_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X237_K2_E5                                                            0x0013b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X237_AHB_CDFE_CMP3_TAP5_OFFSET_K2_E5                                (0x3f<<0) // Override for CMP3 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[5]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X237_AHB_CDFE_CMP3_TAP5_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X238_K2_E5                                                            0x0013b8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X238_AHB_CDFE_CMP4_TAP1_OFFSET_K2_E5                                (0x7f<<0) // Override for CMP4 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[1]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X238_AHB_CDFE_CMP4_TAP1_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X239_K2_E5                                                            0x0013bcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X239_AHB_CDFE_CMP4_TAP2_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP4 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[2]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X239_AHB_CDFE_CMP4_TAP2_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X240_K2_E5                                                            0x0013c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X240_AHB_CDFE_CMP4_TAP3_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP4 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[3]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X240_AHB_CDFE_CMP4_TAP3_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X241_K2_E5                                                            0x0013c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X241_AHB_CDFE_CMP4_TAP4_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP4 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[4]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X241_AHB_CDFE_CMP4_TAP4_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X242_K2_E5                                                            0x0013c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X242_AHB_CDFE_CMP4_TAP5_OFFSET_K2_E5                                (0x3f<<0) // Override for CMP4 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[5]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X242_AHB_CDFE_CMP4_TAP5_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X243_K2_E5                                                            0x0013ccUL //Access:RW   DataWidth:0x8    // Override for CMP1 main calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[0]
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X244_K2_E5                                                            0x0013d0UL //Access:RW   DataWidth:0x8    // Override for CMP2 main calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[0]
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X245_K2_E5                                                            0x0013d4UL //Access:RW   DataWidth:0x8    // Override for CMP3 main calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[0]
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X246_K2_E5                                                            0x0013d8UL //Access:RW   DataWidth:0x8    // Override for CMP4 main calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[0]
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X247_K2_E5                                                            0x0013dcUL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X248_K2_E5                                                            0x0013e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X248_AHB_CDFE_DLL_FINE_MASK_9_8_K2_E5                               (0x3<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X248_AHB_CDFE_DLL_FINE_MASK_9_8_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X248_AHB_CDFE_FINE_DLL_EDGE_SHIFT_K2_E5                             (0xf<<2) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X248_AHB_CDFE_FINE_DLL_EDGE_SHIFT_K2_E5_SHIFT                       2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X249_K2_E5                                                            0x0013e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X249_AHB_CDFE_ERR_SMPL_SHIFT_K2_E5                                  (0xf<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X249_AHB_CDFE_ERR_SMPL_SHIFT_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X249_AHB_CDFE_FINE_DLL_OV_EN_K2_E5                                  (0x1<<4) // cdfe fine dll overwrite enable.  1: enable fine dll overwrite for cdfe.  0: disable fine dll overwrite for cdfe.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X249_AHB_CDFE_FINE_DLL_OV_EN_K2_E5_SHIFT                            4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_K2_E5                                                            0x0013e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8_K2_E5                        (0x1<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8_K2_E5_SHIFT                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_K2_E5                       (0x1<<1) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_K2_E5_SHIFT                 1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8_K2_E5                        (0x1<<2) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8_K2_E5_SHIFT                  2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_K2_E5                       (0x1<<3) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_K2_E5_SHIFT                 3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X251_K2_E5                                                            0x0013ecUL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X252_K2_E5                                                            0x0013f0UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X253_K2_E5                                                            0x0013f4UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X254_K2_E5                                                            0x0013f8UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_K2_E5                                                            0x0013fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_CDFE_DIR_OV_EN_K2_E5                                           (0x1<<0) // Override enable for CDFE calibration direction
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_CDFE_DIR_OV_EN_K2_E5_SHIFT                                     0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_CDFE_DIR_OV_VAL_K2_E5                                          (0x1<<1) // Override value for CDFE calibration direction
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_CDFE_DIR_OV_VAL_K2_E5_SHIFT                                    1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_EYE_ENA270_OVR_EN_O_K2_E5                               (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_EYE_ENA270_OVR_EN_O_K2_E5_SHIFT                         2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_EYE_ENA90_OVR_EN_O_K2_E5                                (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_EYE_ENA90_OVR_EN_O_K2_E5_SHIFT                          3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_PHD_ENA_OVR_EN_O_K2_E5                                  (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_PHD_ENA_OVR_EN_O_K2_E5_SHIFT                            4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_EYE_DLY_OVR_EN_O_K2_E5                                  (0x1<<5) // cdfe eye delay overwrite enable.  1: enable eye delay overwrite for cdfe.  0: disable eye delay overwrite for cdfe.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_EYE_DLY_OVR_EN_O_K2_E5_SHIFT                            5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O_K2_E5                              (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O_K2_E5_SHIFT                        6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X256_K2_E5                                                            0x001400UL //Access:RW   DataWidth:0x8    // cdfe eye delay count overwrite value for CLK90.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X257_K2_E5                                                            0x001404UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8_K2_E5                           (0x1<<0) // cdfe eye delay count overwrite value for CLK90.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8_K2_E5_SHIFT                     0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_K2_E5                   (0x7f<<1) // This register represents the maximum comparator offset from the midpoint code 127/128 that must be met for the comparator to be selected as adaptation comparator during dlev and tap adaptation.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_K2_E5_SHIFT             1
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X258_K2_E5                                                            0x001408UL //Access:RW   DataWidth:0x8    // cdfe eye delay count overwrite value for CLK270.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X259_K2_E5                                                            0x00140cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8_K2_E5                          (0x1<<0) // cdfe eye delay count overwrite value for CLK270.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8_K2_E5_SHIFT                    0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X259_AHB_CDFE_DLEV_OV_EN_K2_E5                                      (0x1<<1) // cdfe dlev overwrite enable.  1: enable dlev overwrite for cdfe.  0: disable dlev overwrite for cdfe.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X259_AHB_CDFE_DLEV_OV_EN_K2_E5_SHIFT                                1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X259_CDFE_DLEV_ADAPT_CMP_SEL_OVR_O_4_0_K2_E5                        (0x1f<<2) // Register override for overriding adaptation comparator select bit [0] : override enable bit [4:1] : override value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X259_CDFE_DLEV_ADAPT_CMP_SEL_OVR_O_4_0_K2_E5_SHIFT                  2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_K2_E5                   (0x1<<7) // Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_K2_E5_SHIFT             7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X260_K2_E5                                                            0x001410UL //Access:RW   DataWidth:0x8    // Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X261_K2_E5                                                            0x001414UL //Access:RW   DataWidth:0x8    // cdfe dlevn overwrite value.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X262_K2_E5                                                            0x001418UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X262_AHB_CDFE_TAP_OV_EN_K2_E5                                       (0x1f<<0) // cdfe tap1~5 overwrite enable.                                                                                                    Bit[0]: enable tap1 overwrite for cdfe. Bit[1]: enable tap2 overwrite for cdfe Bit[2]: enable tap3 overwrite for cdfe.  Bit[3]: enable tap4 overwrite for cdfe. Bit[4]: enable tap5 overwrite for cdfe.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X262_AHB_CDFE_TAP_OV_EN_K2_E5_SHIFT                                 0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X263_K2_E5                                                            0x00141cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X263_AHB_CDFE_TAP1_OV_K2_E5                                         (0x7f<<0) // cdfe tap1 overwrite value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X263_AHB_CDFE_TAP1_OV_K2_E5_SHIFT                                   0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X264_K2_E5                                                            0x001420UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X264_AHB_CDFE_TAP2_OV_K2_E5                                         (0x3f<<0) // cdfe tap2 overwrite value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X264_AHB_CDFE_TAP2_OV_K2_E5_SHIFT                                   0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X265_K2_E5                                                            0x001424UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X265_AHB_CDFE_TAP3_OV_K2_E5                                         (0x3f<<0) // cdfe tap3 overwrite value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X265_AHB_CDFE_TAP3_OV_K2_E5_SHIFT                                   0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X266_K2_E5                                                            0x001428UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X266_AHB_CDFE_TAP4_OV_K2_E5                                         (0x3f<<0) // cdfe tap4 overwrite value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X266_AHB_CDFE_TAP4_OV_K2_E5_SHIFT                                   0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X267_K2_E5                                                            0x00142cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X267_AHB_CDFE_TAP5_OV_K2_E5                                         (0x3f<<0) // cdfe tap5 overwrite value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X267_AHB_CDFE_TAP5_OV_K2_E5_SHIFT                                   0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_K2_E5                   (0x1<<7) // Enables FW enable control for TAP adapt using DLEV
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_K2_E5_SHIFT             7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_K2_E5                                                            0x001430UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O_K2_E5                           (0x1<<0) // Instucts to start TAP adapt using DLEV in FW enabled mode
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O_K2_E5_SHIFT                     0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_K2_E5                 (0x1<<1) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_K2_E5_SHIFT           1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O_K2_E5             (0x1<<2) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O_K2_E5_SHIFT       2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_K2_E5                                (0x1<<7) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X269_K2_E5                                                            0x001434UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O_K2_E5                         (0x1<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O_K2_E5_SHIFT                   0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X269_AHB_CDFE_STROBE_EN_O_K2_E5                                     (0x1<<1) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X269_AHB_CDFE_STROBE_EN_O_K2_E5_SHIFT                               1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X269_AHB_CDFE_CMP_ENA_O_K2_E5                                       (0xf<<2) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X269_AHB_CDFE_CMP_ENA_O_K2_E5_SHIFT                                 2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X270_K2_E5                                                            0x001438UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X271_K2_E5                                                            0x00143cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X271_AHB_CDFE_DIV_SIGN_BIT_O_4_0_K2_E5                              (0x1f<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X271_AHB_CDFE_DIV_SIGN_BIT_O_4_0_K2_E5_SHIFT                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O_K2_E5                      (0x1<<5) // Forces the positive dlev training pattern to be used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O_K2_E5_SHIFT                5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O_K2_E5                      (0x1<<6) // Forces the negative dlev training pattern to be used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O_K2_E5_SHIFT                6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X272_K2_E5                                                            0x001440UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X272_CDFE_TAP1_SCALE_O_2_0_K2_E5                                    (0x7<<0) // Scale factor CDFE TAP1 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X272_CDFE_TAP1_SCALE_O_2_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X272_CDFE_TAP1_SHIFT_O_4_0_K2_E5                                    (0x1f<<3) // Shift factor CDFE TAP1 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X272_CDFE_TAP1_SHIFT_O_4_0_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X273_K2_E5                                                            0x001444UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X273_CDFE_TAP2_SCALE_O_2_0_K2_E5                                    (0x7<<0) // Scale factor CDFE TAP2 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X273_CDFE_TAP2_SCALE_O_2_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X273_CDFE_TAP2_SHIFT_O_4_0_K2_E5                                    (0x1f<<3) // Shift factor CDFE TAP2 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X273_CDFE_TAP2_SHIFT_O_4_0_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X274_K2_E5                                                            0x001448UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X274_CDFE_TAP3_SCALE_O_2_0_K2_E5                                    (0x7<<0) // Scale factor CDFE TAP3 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X274_CDFE_TAP3_SCALE_O_2_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X274_CDFE_TAP3_SHIFT_O_4_0_K2_E5                                    (0x1f<<3) // Shift factor CDFE TAP3 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X274_CDFE_TAP3_SHIFT_O_4_0_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X275_K2_E5                                                            0x00144cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X275_CDFE_TAP4_SCALE_O_2_0_K2_E5                                    (0x7<<0) // Scale factor CDFE TAP4 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X275_CDFE_TAP4_SCALE_O_2_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X275_CDFE_TAP4_SHIFT_O_4_0_K2_E5                                    (0x1f<<3) // Shift factor CDFE TAP4 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X275_CDFE_TAP4_SHIFT_O_4_0_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X276_K2_E5                                                            0x001450UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X276_CDFE_TAP5_SCALE_O_2_0_K2_E5                                    (0x7<<0) // Scale factor CDFE TAP5 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X276_CDFE_TAP5_SCALE_O_2_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X276_CDFE_TAP5_SHIFT_O_4_0_K2_E5                                    (0x1f<<3) // Shift factor CDFE TAP5 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X276_CDFE_TAP5_SHIFT_O_4_0_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X277_K2_E5                                                            0x001454UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X277_LN_MSM_RESET_RA_OVR_O_K2_E5                                    (0x3<<0) // Bit 0:  Override enable for msm_reset_ra Bit 1: Override msm_reset_ra
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X277_LN_MSM_RESET_RA_OVR_O_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X277_LN_MSM_RESET_P2S_OVR_O_K2_E5                                   (0x3<<2) // Bit 0:  Override enable for msm_reset_p2s Bit 1: Override msm_reset_p2s
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X277_LN_MSM_RESET_P2S_OVR_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X277_LN_MSM_RESET_LNREGH_OVR_O_K2_E5                                (0x3<<4) // Bit 0:  Override enable for msm_reset_lnregh Bit 1: Override msm_reset_lnregh
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X277_LN_MSM_RESET_LNREGH_OVR_O_K2_E5_SHIFT                          4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X277_LN_MSM_RESET_LNREG_OVR_O_K2_E5                                 (0x3<<6) // Bit 0:  Override enable for msm_reset_lnreg Bit 1: Override msm_reset_lnreg
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X277_LN_MSM_RESET_LNREG_OVR_O_K2_E5_SHIFT                           6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X278_K2_E5                                                            0x001458UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X278_LN_MSM_RESET_CDR_OVR_O_K2_E5                                   (0x3<<0) // Bit 0:  Override enable for msm_reset_cdr Bit 1: Override msm_reset_cdr
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X278_LN_MSM_RESET_CDR_OVR_O_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X278_LN_MSM_RESET_DFE_OVR_O_K2_E5                                   (0x3<<2) // Bit 0:  Override enable for msm_reset_dfe Bit 1: Override msm_reset_dfe
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X278_LN_MSM_RESET_DFE_OVR_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X278_LN_MSM_PD_LNREGH_OVR_O_K2_E5                                   (0x3<<4) // Bit 0:  Override enable for msm_pd_lnregh Bit 1: Override msm_pd_lnregh
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X278_LN_MSM_PD_LNREGH_OVR_O_K2_E5_SHIFT                             4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X278_LN_MSM_PD_VCO_BUF_OVR_O_K2_E5                                  (0x3<<6) // Bit 0:  Override enable for msm_pd_vco_buf Bit 1: Override msm_pd_vco_buf
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X278_LN_MSM_PD_VCO_BUF_OVR_O_K2_E5_SHIFT                            6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X279_K2_E5                                                            0x00145cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X279_LN_MSM_RESET_CDR_GCRX_OVR_O_K2_E5                              (0x3<<0) // Bit 0:  Override enable for msm_reset_cdr_gcrx Bit 1: Override msm_reset_cdr_gcrx
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X279_LN_MSM_RESET_CDR_GCRX_OVR_O_K2_E5_SHIFT                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X279_LN_MSM_RXGATE_EN_OVR_O_K2_E5                                   (0x3<<2) // Bit 0:  Override enable for msm_rxgate_en Bit 1: Override msm_rxgate_en
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X279_LN_MSM_RXGATE_EN_OVR_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X279_LN_MSM_RESET_VCO_OVR_O_K2_E5                                   (0x3<<4) // Bit 0:  Override enable for msm_reset_vco Bit 1: Override msm_reset_vco
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X279_LN_MSM_RESET_VCO_OVR_O_K2_E5_SHIFT                             4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X279_LN_MSM_IDDQ_SD_OVR_O_K2_E5                                     (0x3<<6) // Bit 0:  Override enable for msm_iddq_sd Bit 1: Override msm_iddq_sd
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X279_LN_MSM_IDDQ_SD_OVR_O_K2_E5_SHIFT                               6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X280_K2_E5                                                            0x001460UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X280_LN_MSM_PD_DFE_OVR_O_K2_E5                                      (0x3<<0) // Bit 0:  Override enable for msm_pd_dfe Bit 1: Override msm_pd_dfe
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X280_LN_MSM_PD_DFE_OVR_O_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X280_LN_MSM_PD_DFE_BIAS_OVR_O_K2_E5                                 (0x3<<2) // Bit 0:  Override enable for msm_pd_dfe_bias Bit 1: Override msm_pd_dfe_bias
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X280_LN_MSM_PD_DFE_BIAS_OVR_O_K2_E5_SHIFT                           2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X280_LN_MSM_TXDRV_LP_IDLE_OVR_O_K2_E5                               (0x3<<4) // Bit 0:  Override enable for msm_txdrv_lp_idle Bit 1: Override msm_txdrv_lp_idle
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X280_LN_MSM_TXDRV_LP_IDLE_OVR_O_K2_E5_SHIFT                         4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X280_LN_MSM_TXREG_BLEED_ENA_OVR_O_K2_E5                             (0x3<<6) // Bit 0:  Override enable for msm_txreg_bleed_ena Bit 1: Override msm_txreg_bleed_ena
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X280_LN_MSM_TXREG_BLEED_ENA_OVR_O_K2_E5_SHIFT                       6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X281_K2_E5                                                            0x001464UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X281_LN_MSM_PD_TXREG_OVR_O_K2_E5                                    (0x3<<0) // Bit 0:  Override enable for msm_pd_txreg Bit 1: Override msm_pd_txreg
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X281_LN_MSM_PD_TXREG_OVR_O_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X281_LN_MSM_PD_LNREG_OVR_O_K2_E5                                    (0x3<<2) // Bit 0:  Override enable for msm_pd_lnreg Bit 1: Override msm_pd_lnreg
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X281_LN_MSM_PD_LNREG_OVR_O_K2_E5_SHIFT                              2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X281_LN_MSM_PD_P2S_OVR_O_K2_E5                                      (0x3<<4) // Bit 0:  Override enable for pd_p2s Bit 1: Override pd_p2s
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X281_LN_MSM_PD_P2S_OVR_O_K2_E5_SHIFT                                4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X281_LN_MSM_PD_RA_OVR_O_K2_E5                                       (0x3<<6) // Bit 0:  Override enable for pd_ra Bit 1: Override pd_ra
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X281_LN_MSM_PD_RA_OVR_O_K2_E5_SHIFT                                 6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X282_K2_E5                                                            0x001468UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X282_LN_MSM_PD_SLV_BIAS_OVR_O_K2_E5                                 (0x3<<2) // Bit 0:  Override enable for pd_slv_bias Bit 1: Override pd_slv_bias
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X282_LN_MSM_PD_SLV_BIAS_OVR_O_K2_E5_SHIFT                           2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X282_LN_MSM_PD_TXDRV_OVR_O_K2_E5                                    (0x3<<4) // Bit 0:  Override enable for pd_txdrv Bit 1: Override pd_txdrv
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X282_LN_MSM_PD_TXDRV_OVR_O_K2_E5_SHIFT                              4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X282_LN_MSM_PD_VCO_OVR_O_K2_E5                                      (0x3<<6) // Bit 0:  Override enable for msm_pd_vco Bit 1: Override msm_pd_vco
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X282_LN_MSM_PD_VCO_OVR_O_K2_E5_SHIFT                                6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X283_K2_E5                                                            0x00146cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X283_LN_MSM_CDR_EN_OVR_O_K2_E5                                      (0x3<<0) // Bit 0:  Override enable for msm_cdr_en Bit 1: Override msm_cdr_en
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X283_LN_MSM_CDR_EN_OVR_O_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X283_LN_MSM_RESET_S2P_OVR_O_K2_E5                                   (0x3<<2) // Bit 0:  Override enable for msm_reset_s2p Bit 1: Override msm_reset_s2p
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X283_LN_MSM_RESET_S2P_OVR_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X283_LN_MSM_RXCLK_EN_OVR_O_K2_E5                                    (0x3<<4) // Bit 0:  Override enable for msm_rxclk_en Bit 1: Override msm_rxclk_en
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X283_LN_MSM_RXCLK_EN_OVR_O_K2_E5_SHIFT                              4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X283_LN_MSM_WORD_OVR_O_K2_E5                                        (0x3<<6) // Bit 0:  Override enable for msm_word Bit 1: Override msm_word
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X283_LN_MSM_WORD_OVR_O_K2_E5_SHIFT                                  6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X284_K2_E5                                                            0x001470UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X284_LN_MSM_RATE_OVR_O_K2_E5                                        (0x7<<0) // Bit 0:  Override enable for msm_rate Bit [2:1] : Override msm_rate
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X284_LN_MSM_RATE_OVR_O_K2_E5_SHIFT                                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X284_LN_MSM_RXVCODIV_OVR_O_K2_E5                                    (0x7<<3) // Bit 0:  Override enable for msm_rxvcodiv Bit [2:1] : Override msm_rxvcodiv
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X284_LN_MSM_RXVCODIV_OVR_O_K2_E5_SHIFT                              3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X284_LN_MSM_RESET_TX_CLKDIV_OVR_O_K2_E5                             (0x3<<6) // Not currently used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X284_LN_MSM_RESET_TX_CLKDIV_OVR_O_K2_E5_SHIFT                       6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X285_K2_E5                                                            0x001474UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X285_LN_MSM_TXVCODIV_OVR_O_K2_E5                                    (0x7<<0) // Bit 0:  Override enable for msm_txvcodiv Bit [2:1] : Override msm_txvcodiv
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X285_LN_MSM_TXVCODIV_OVR_O_K2_E5_SHIFT                              0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_K2_E5                                                            0x0014b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_RX_SRC_O_K2_E5                                                 (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 - Output of mux is output from 8b/10b encoder.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_RX_SRC_O_K2_E5_SHIFT                                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_TREG0_POL_O_K2_E5                                              (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_TREG0_POL_O_K2_E5_SHIFT                                        1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_TREG0_BIT_O_K2_E5                                              (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_TREG0_BIT_O_K2_E5_SHIFT                                        2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_TREG0_WORD_O_K2_E5                                             (0x1<<3) // TReg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_TREG0_WORD_O_K2_E5_SHIFT                                       3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_DMUX_TXA_SEL_O_1_0_K2_E5                                       (0x3<<4) // Transmit mux A data input select.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_DMUX_TXA_SEL_O_1_0_K2_E5_SHIFT                                 4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_P2S_RBUF_AUTOFIX_O_K2_E5                                       (0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / underflows 1 - Ring buffer will reset upon detection of overflow/underflow
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_P2S_RBUF_AUTOFIX_O_K2_E5_SHIFT                                 6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_K2_E5                                                            0x0014b8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_TREG1_POL_O_K2_E5                                              (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_TREG1_POL_O_K2_E5_SHIFT                                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_TREG1_BIT_O_K2_E5                                              (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_TREG1_BIT_O_K2_E5_SHIFT                                        1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_TREG1_WORD_O_K2_E5                                             (0x1<<2) // TReg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_TREG1_WORD_O_K2_E5_SHIFT                                       2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_REG1_POL_O_K2_E5                                               (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_REG1_POL_O_K2_E5_SHIFT                                         3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_REG1_BIT_O_K2_E5                                               (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_REG1_BIT_O_K2_E5_SHIFT                                         4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_REG1_WORD_O_K2_E5                                              (0x1<<5) // Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_REG1_WORD_O_K2_E5_SHIFT                                        5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_REG0_POL_O_K2_E5                                               (0x1<<6) // Used as Reg0 polarity select
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_REG0_POL_O_K2_E5_SHIFT                                         6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_K2_E5                                                            0x0014bcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_REG0_BIT_O_K2_E5                                               (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_REG0_BIT_O_K2_E5_SHIFT                                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_REG0_WORD_O_K2_E5                                              (0x1<<1) // Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_REG0_WORD_O_K2_E5_SHIFT                                        1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_DMUX_TXB_SEL_O_2_0_K2_E5                                       (0x7<<2) // Transmit mux B data input select enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_DMUX_TXB_SEL_O_2_0_K2_E5_SHIFT                                 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_TX_CTRL_O_24_K2_E5                                             (0x1<<5) // Bit 24: txdrv_c2_in[3]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_TX_CTRL_O_24_K2_E5_SHIFT                                       5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_WIDTH_CHNG_EN_O_K2_E5                                          (0x1<<6) // Enable bit for width_chng module
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_WIDTH_CHNG_EN_O_K2_E5_SHIFT                                    6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_TXTERM_CAL_SEQ_EN_O_K2_E5                                      (0x1<<7) // Txterm calibration enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_TXTERM_CAL_SEQ_EN_O_K2_E5_SHIFT                                7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X304_K2_E5                                                            0x0014c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X304_TXTERM_CAL_RSEL_K2_E5                                          (0x7<<0) // tx termination calibration comparator threshold select
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X304_TXTERM_CAL_RSEL_K2_E5_SHIFT                                    0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X304_AHB_LN_RXBIT_STRIP_O_K2_E5                                     (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2b00: no bit stripping 2b01: 2x bit stripping 2b10: reserved 2b11: 4x bit stripping
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X304_AHB_LN_RXBIT_STRIP_O_K2_E5_SHIFT                               3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X304_AHB_MAC_WIDTH_O_K2_E5                                          (0x3<<5) // Data width selector for PCS/MAC interface. 2b00: GigE or XAUI 2b01: GigE or XAUI 2b10: RXAUI 2b11: XFI
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X304_AHB_MAC_WIDTH_O_K2_E5_SHIFT                                    5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X305_K2_E5                                                            0x0014c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X305_AHB_TXMAC_THRESHOLD_O_K2_E5                                    (0x3<<0) // An internal FIFO is included to handle the communication between the external 64-bit data and the internal 20-bit data. The reading operation will begin only when the difference between the write pointer and read pointer for this FIFO reaches ahb_txmac_threshold_o.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X305_AHB_TXMAC_THRESHOLD_O_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X305_AHB_LN_TXBIT_REPEAT_O_K2_E5                                    (0x3<<2) // Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to PCS 2b00: no bit stuffing nor stripping 2b01: 2x bit stuffing and stripping 2b10: reserved 2b11: 4x bit stuffing and stripping
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X305_AHB_LN_TXBIT_REPEAT_O_K2_E5_SHIFT                              2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X305_MODE_8B_O_1_0_K2_E5                                            (0x3<<4) // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data word 8 bits
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X305_MODE_8B_O_1_0_K2_E5_SHIFT                                      4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X305_ENC_EN_O_K2_E5                                                 (0x1<<6) // 8b/10b encoder enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X305_ENC_EN_O_K2_E5_SHIFT                                           6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X305_DEC_EN_O_K2_E5                                                 (0x1<<7) // 8b/10b decoder enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X305_DEC_EN_O_K2_E5_SHIFT                                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X306_K2_E5                                                            0x0014c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X306_AHB_TX_CDAC_OVR_K2_E5                                          (0xf<<0) // TX termination calibration DAC override. Signal ahb_tx_term_en_cal_ovr must also be asserted to take effect.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X306_AHB_TX_CDAC_OVR_K2_E5_SHIFT                                    0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X306_LN_COMMON_SYNC_TXCLK_EN_O_K2_E5                                (0x1<<4) // Per lane common synchronous clock between PMA, PCS and SoC logic enable bit. 1: in NORM state, lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA or its divided down version and this clock can be used as a common synchronous clock between PMA, PCS and SoC logic. In other state, it is switched to cmu_ck_soc_o[1]. 0: lnX_ck_txb_o is swtiched to cmu_ck_soc_o[1].
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X306_LN_COMMON_SYNC_TXCLK_EN_O_K2_E5_SHIFT                          4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X307_K2_E5                                                            0x0014ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X307_LN_TO_CLK_TXB_WAIT_O_K2_E5                                     (0x1f<<0) // In per lane common synchronous clock mode, after the lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA. The lnX_ok_o will get asserted after lnX_to_clk_txb_wait_o lnX_ck_txb_o cycles.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X307_LN_TO_CLK_TXB_WAIT_O_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X307_PIPE_EN_O_K2_E5                                                (0x1<<5) // PIPE interface block enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X307_PIPE_EN_O_K2_E5_SHIFT                                          5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X307_SAPIS_EN_O_K2_E5                                               (0x1<<6) // SAPIS interface block enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X307_SAPIS_EN_O_K2_E5_SHIFT                                         6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X307_USB_MODE_K2_E5                                                 (0x1<<7) // Signal Detect USB mode enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X307_USB_MODE_K2_E5_SHIFT                                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_K2_E5                                                            0x0014d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_BLOCK_ENC_CLR_ERR_O_K2_E5                                      (0x1<<1) // 128b/130b encoder clear error
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_BLOCK_ENC_CLR_ERR_O_K2_E5_SHIFT                                1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_BLOCK_DEC_EN_ERR_CHK_O_K2_E5                                   (0x1<<3) // 130b/128b error check enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_BLOCK_DEC_EN_ERR_CHK_O_K2_E5_SHIFT                             3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_BLOCK_DEC_CHK_OS_NMBR_O_2_0_K2_E5                              (0x7<<4) // 130b/128b: number of OS indicating end of data
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_BLOCK_DEC_CHK_OS_NMBR_O_2_0_K2_E5_SHIFT                        4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_BLOCK_DEC_CLR_ERR_O_K2_E5                                      (0x1<<7) // 130b/128b: clear error flag
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_BLOCK_DEC_CLR_ERR_O_K2_E5_SHIFT                                7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X309_K2_E5                                                            0x0014d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X309_BLOCK_DEC_ERR_THRESHOLD_O_3_0_K2_E5                            (0xf<<0) // 130b/128b: number of sync hdr errors before asserting sync error flag
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X309_BLOCK_DEC_ERR_THRESHOLD_O_3_0_K2_E5_SHIFT                      0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X309_BLOCK_DEC_CHK_BLK_NMBR_O_3_0_K2_E5                             (0xf<<4) // 130b/128b: number of continuous blocks checked
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X309_BLOCK_DEC_CHK_BLK_NMBR_O_3_0_K2_E5_SHIFT                       4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_K2_E5                                                            0x0014d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_EBUF_RSTN_O_K2_E5                                              (0x1<<0) // Synchronous clear for elastic buffer
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_EBUF_RSTN_O_K2_E5_SHIFT                                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_ALIGN_RSTN_O_K2_E5                                             (0x1<<1) // Synchronous clear for block/symbol aligner
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_ALIGN_RSTN_O_K2_E5_SHIFT                                       1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_EBUF_SKP_ADD_EN_O_K2_E5                                        (0x1<<2) // Elastic buffer SKP add enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_EBUF_SKP_ADD_EN_O_K2_E5_SHIFT                                  2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_RBUF_RSTN_O_K2_E5                                              (0x1<<3) // TX FIFO synchronous reset
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_RBUF_RSTN_O_K2_E5_SHIFT                                        3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_EN_SKPOS_ERR_O_K2_E5                                           (0x1<<5) // Enables skpos error status propagation in Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_EN_SKPOS_ERR_O_K2_E5_SHIFT                                     5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X311_K2_E5                                                            0x0014dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X311_PIPE_LFREQ_K2_E5                                               (0x3f<<0) // LF value for full swing
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X311_PIPE_LFREQ_K2_E5_SHIFT                                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X311_DIS_BLOCK_ALIGN_CTRL_O_K2_E5                                   (0x1<<6) // Disables the primary input lnX_block_align_control
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X311_DIS_BLOCK_ALIGN_CTRL_O_K2_E5_SHIFT                             6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X311_DIS_EIEOS_CHK_IN_LB_O_K2_E5                                    (0x1<<7) // Disables the EIEOS check in loopback
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X311_DIS_EIEOS_CHK_IN_LB_O_K2_E5_SHIFT                              7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X312_K2_E5                                                            0x0014e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X312_COEF_FE_LIMIT_EN_O_K2_E5                                       (0x1<<0) // FE TxEq Co-efficient Limiting Enable control
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X312_COEF_FE_LIMIT_EN_O_K2_E5_SHIFT                                 0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X312_RXVALID_DIS_AT_RATE_CHG_O_0_K2_E5                              (0x1<<1) // Value 1 forces rxvalid to be deasserted during rate change to gen 3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X312_RXVALID_DIS_AT_RATE_CHG_O_0_K2_E5_SHIFT                        1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X312_P2S_RBUF_BUF_THRESH_O_3_0_K2_E5                                (0xf<<2) // TX FIFO: specifies how far write pointer need to be ahead of read pointer before almost_full_o is asserted
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X312_P2S_RBUF_BUF_THRESH_O_3_0_K2_E5_SHIFT                          2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X313_K2_E5                                                            0x0014e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X313_AHB_RX_GEARBOX_DISABLE_O_K2_E5                                 (0x1<<0) // 0: enable rx_gearbox, 1: disable rx_gearbox
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X313_AHB_RX_GEARBOX_DISABLE_O_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X313_AHB_TX_GEARBOX_DISABLE_O_K2_E5                                 (0x1<<1) // 0: enable tx_gearbox, 1: disable tx_gearbox
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X313_AHB_TX_GEARBOX_DISABLE_O_K2_E5_SHIFT                           1
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_K2_E5                                                            0x0014e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_GEN1_OLD_RXDATA_SRC_K2_E5                                      (0x1<<0) // Mux select for data input to polbit_reg0  0:pma_ln_dfe_err_i , 1: pma_ln_rxdata_i
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_GEN1_OLD_RXDATA_SRC_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_SKIP_CDR_GEN3_O_K2_E5                                          (0x1<<1) // To skip cdr calibration routines for PCIe gen3.  Can be used when PHY is operating in gen1,2 only.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_SKIP_CDR_GEN3_O_K2_E5_SHIFT                                    1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_SKIP_CDR_GEN12_O_K2_E5                                         (0x1<<2) // To skip cdr calibration routines for PCIe gen1,2.  May not be needed in real scenario.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_SKIP_CDR_GEN12_O_K2_E5_SHIFT                                   2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_K2_E5                               (0x1<<3) // Receive amplifier powerdown override, when cisel is high
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_K2_E5_SHIFT                         3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_LN_P2S_RBUF_REALIGN_DIFF_O_K2_E5                               (0xf<<4) // In per lane common synchronous clock mode, ln_p2x_rbuf_realign_diff_o defines the starting difference between write pointer and read pointer when re aligning the pointer of TxFIFO.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_LN_P2S_RBUF_REALIGN_DIFF_O_K2_E5_SHIFT                         4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X315_K2_E5                                                            0x0014ecUL //Access:RW   DataWidth:0x8    // Delays the beacon_ena propagation to PMA
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X316_K2_E5                                                            0x0014f0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X316_AHB_BEACON_DELAYED_COUNT_NUMBER_11_8_O_K2_E5                   (0xf<<0) // Delays the beacon_ena propagation to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X316_AHB_BEACON_DELAYED_COUNT_NUMBER_11_8_O_K2_E5_SHIFT             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_K2_E5                                                            0x0014f4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_AHB_BEACON_ENA_OVR_ENA_O_K2_E5                                 (0x1<<0) // Beacon Override Enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_AHB_BEACON_ENA_OVR_ENA_O_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_AHB_BEACON_ENA_OVR_O_K2_E5                                     (0x1<<1) // Beacon Override
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_AHB_BEACON_ENA_OVR_O_K2_E5_SHIFT                               1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_DEC_EN_OVR_O_K2_E5                                             (0x1<<2) // Enables 16b/20b decoder
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_DEC_EN_OVR_O_K2_E5_SHIFT                                       2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_ENC_EN_OVR_O_K2_E5                                             (0x1<<3) // Enables 16b/20b encoder
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_ENC_EN_OVR_O_K2_E5_SHIFT                                       3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_REGP_OVR_3_0_K2_E5                                             (0xf<<4) // Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty  Bit[1]: Overide values for bit reverse  Bit[2]: Overide values for word reverse
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_REGP_OVR_3_0_K2_E5_SHIFT                                       4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X318_K2_E5                                                            0x0014f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X318_SIGDET_OVR_O_1_0_K2_E5                                         (0x3<<0) // Bit[0]: Overide value. Bit[1] :Override enable for signal detect output
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X318_SIGDET_OVR_O_1_0_K2_E5_SHIFT                                   0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X318_LN_OUT_OVR_1_0_K2_E5                                           (0x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the override, while bit 0 is the override value.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X318_LN_OUT_OVR_1_0_K2_E5_SHIFT                                     2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X318_RXEQ_SIGDET_1_0_K2_E5                                          (0x3<<4) // Override enable for DFE signal detect indicator input. Bit 1 is overide enable , 0 is overide value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X318_RXEQ_SIGDET_1_0_K2_E5_SHIFT                                    4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X319_K2_E5                                                            0x0014fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X319_TXDETECTRX_OVR_O_1_0_K2_E5                                     (0x3<<0) // Override signal for txdetectrx input - bit 1 is override enable, bit 0 is override value.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X319_TXDETECTRX_OVR_O_1_0_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X319_RXDET_STATUS_OVR_O_1_0_K2_E5                                   (0x3<<2) // Override signal for txdetectrx output - bit 1 is override enable, bit 0 is override value.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X319_RXDET_STATUS_OVR_O_1_0_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X319_LOCKED_OVR_O_1_0_K2_E5                                         (0x3<<4) // Override signal for symbol align locked output. Bit 1 is the override enable, and bit 0 is the override value.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X319_LOCKED_OVR_O_1_0_K2_E5_SHIFT                                   4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O_K2_E5                         (0x1<<6) // override enable for tx_lowpwr_idle_ena output to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O_K2_E5_SHIFT                   6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_K2_E5                             (0x1<<7) // override value for tx_lowpwr_idle_ena output to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_K2_E5_SHIFT                       7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X320_K2_E5                                                            0x001500UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X321_K2_E5                                                            0x001504UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X322_K2_E5                                                            0x001508UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X323_K2_E5                                                            0x00150cUL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X324_K2_E5                                                            0x001510UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X325_K2_E5                                                            0x001514UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_K2_E5                                                            0x001518UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_LN_IN_OVR_O_48_K2_E5                                           (0x1<<0) // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_LN_IN_OVR_O_48_K2_E5_SHIFT                                     0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_AHB_LN_IN_OVR_CHG_FLAG_O_K2_E5                                 (0x1<<1) // Flag to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1' before writing to the corresponding lnX_in_ovr_o_14_1 and set it back to '0' after the write. It is not needed for configuration writes.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_AHB_LN_IN_OVR_CHG_FLAG_O_K2_E5_SHIFT                           1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_REGP1_OVR_O_3_0_K2_E5                                          (0xf<<2) // Overrides for polbit block polbit_regp1 Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty  Bit[1]: Overide values for bit reverse  Bit[2]: Overide values for word reverse
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_REGP1_OVR_O_3_0_K2_E5_SHIFT                                    2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_OOB_DET_EN_K2_E5                                               (0x1<<6) // OOB detect enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_OOB_DET_EN_K2_E5_SHIFT                                         6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_LN_IN_OVR_O_49_K2_E5                                           (0x1<<7) // OOB detect enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_LN_IN_OVR_O_49_K2_E5_SHIFT                                     7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X327_K2_E5                                                            0x00151cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X327_CDR_CTRL_DLY_DLPF_EN_O_K2_E5                                   (0x1f<<0) // Delay between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0  R-platform requires 150ns delay
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X327_CDR_CTRL_DLY_DLPF_EN_O_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X330_K2_E5                                                            0x001528UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X330_MSM_LN_RATE_EXTRA_BITS_OVR_O_2_0_K2_E5                         (0x7<<0) // Override signals for lane: msm_ln_rate_ow[4:2]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X330_MSM_LN_RATE_EXTRA_BITS_OVR_O_2_0_K2_E5_SHIFT                   0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X330_LN_IN_OVR_O_50_K2_E5                                           (0x1<<3) // Override signals for lane: msm_ln_rate_ow[4:2]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X330_LN_IN_OVR_O_50_K2_E5_SHIFT                                     3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X0_K2_E5                                                              0x001800UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O_K2_E5                                 (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X1_K2_E5                                                              0x001804UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O_K2_E5                                 (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O_K2_E5_SHIFT                           3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O_K2_E5                                 (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X2_K2_E5                                                              0x001808UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O_K2_E5                                 (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X3_K2_E5                                                              0x00180cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X3_PMA_CMU_SEL_O_0_K2_E5                                            (0x1<<0) // CMU Select for lane  0 -	 Select CMU0  1 -	 Select CMU1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X3_PMA_CMU_SEL_O_0_K2_E5_SHIFT                                      0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X3_PMA_TXCLK_SEL_O_1_K2_E5                                          (0x1<<1) // PMA TX Clock Select for TX CDR VCO  0 -	 CMU0 Clock  1 -	 CMU1 Clock
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X3_PMA_TXCLK_SEL_O_1_K2_E5_SHIFT                                    1
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X4_K2_E5                                                              0x001810UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X4_CDRCTRL_DIV_EN_O_1_0_K2_E5                                       (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Divide by 4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X4_CDRCTRL_DIV_EN_O_1_0_K2_E5_SHIFT                                 0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X4_GCFSM_DIV_EN_O_1_0_K2_E5                                         (0x3<<2) // Static divider control for Lane GCFSM clock The only access to this divider. Not an override 4d0:  No division  4d1:  /2 4d2:  /2 4d3:  /4:
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X4_GCFSM_DIV_EN_O_1_0_K2_E5_SHIFT                                   2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X4_LN_CLK_TXB_DIV24OR1_O_K2_E5                                      (0x3<<4) // Divide ratio setting for lnX_ck_txb_o. When ln_common_sync_txclk_en_o is high and in NORM state:                                            2'b00: lnX_ck_txb_o is divided by 1 version of the tx byte clock from PMA.                     2'b01/2'b10: lnX_ck_txb_o is divided by 2 version of the tx byte clock from PMA.                  2'b11: lnX_ck_txb_o is divided by 4 version of the tx byte clock from PMA.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X4_LN_CLK_TXB_DIV24OR1_O_K2_E5_SHIFT                                4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X4_AHB_CHNG_REQ_Z_O_K2_E5                                           (0x1<<6) // Not currently used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X4_AHB_CHNG_REQ_Z_O_K2_E5_SHIFT                                     6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X5_K2_E5                                                              0x001814UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X5_REF_CLK_DIV_EN_O_1_0_K2_E5                                       (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X5_REF_CLK_DIV_EN_O_1_0_K2_E5_SHIFT                                 0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X5_OOB_CLK_DIV_EN_O_1_0_K2_E5                                       (0x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X5_OOB_CLK_DIV_EN_O_1_0_K2_E5_SHIFT                                 2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_K2_E5                                                              0x00181cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_RATE_O_K2_E5                                                (0x3<<0) // Rate control for BIST
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_RATE_O_K2_E5_SHIFT                                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_MODE8B_O_K2_E5                                          (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Generated data word is 8 bits
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_MODE8B_O_K2_E5_SHIFT                                    2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_ERR_O_K2_E5                                             (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 - BIST generator outputs erroneous pattern.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_ERR_O_K2_E5_SHIFT                                       3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_TX_CLOCK_ENABLE_K2_E5                                       (0x1<<4) // Active HIGH clock enable signal for the BIST transmit clock
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_TX_CLOCK_ENABLE_K2_E5_SHIFT                                 4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_CDN_O_K2_E5                                             (0x1<<5) // Bist generator master reset.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_CDN_O_K2_E5_SHIFT                                       5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_WORD_O_K2_E5                                            (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 1 - Bist generator generates double word 16 or 20
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_WORD_O_K2_E5_SHIFT                                      6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_EN_O_K2_E5                                              (0x1<<7) // Bist generator enable.  0 - Bist generator idle. 1 - Bist generator generates data
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_EN_O_K2_E5_SHIFT                                        7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X8_K2_E5                                                              0x001820UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X8_BIST_GEN_CLK_SEL_O_2_0_K2_E5                                     (0x7<<0) // BIST Generation Clock Selection
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X8_BIST_GEN_CLK_SEL_O_2_0_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X8_BIST_GEN_SEND_PREAM_O_K2_E5                                      (0x1<<3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - Bist generator sends preamble.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X8_BIST_GEN_SEND_PREAM_O_K2_E5_SHIFT                                3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X8_BIST_GEN_INSERT_COUNT_O_2_0_K2_E5                                (0x7<<4) // Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is ever inserted into the stream. In 20-bit mode, the product of bist_gen_insert_length x bist_gen_insert_count must be even.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X8_BIST_GEN_INSERT_COUNT_O_2_0_K2_E5_SHIFT                          4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X9_K2_E5                                                              0x001824UL //Access:RW   DataWidth:0x8    // Bist generator low-period control. If not 0, output data enable will be low for this number of words, and then high for en_high_i_X:0 number of words, repeating. If 0, data output enable will be asserted for entire test.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X10_K2_E5                                                             0x001828UL //Access:RW   DataWidth:0x8    // Bist generator low-period control. If not 0, output data enable will be low for this number of words, and then high for en_high_i_X:0 number of words, repeating. If 0, data output enable will be asserted for entire test.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X11_K2_E5                                                             0x00182cUL //Access:RW   DataWidth:0x8    // Bist generator high-period control. Refer to bist_gen_en_low_o and BIST documentation for further information.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X12_K2_E5                                                             0x001830UL //Access:RW   DataWidth:0x8    // Bist generator high-period control. Refer to bist_gen_en_low_o and BIST documentation for further information.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X13_K2_E5                                                             0x001834UL //Access:RW   DataWidth:0x8    // Bist generator - Number of words between insert word insertions. Insertions are done in both pream and data transmission. In 20-bit mode, this number must be even.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X14_K2_E5                                                             0x001838UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X14_BIST_GEN_INSERT_DELAY_O_11_8_K2_E5                              (0xf<<0) // Bist generator - Number of words between insert word insertions. Insertions are done in both pream and data transmission. In 20-bit mode, this number must be even.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X14_BIST_GEN_INSERT_DELAY_O_11_8_K2_E5_SHIFT                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X14_BCHK_EN_O_K2_E5                                                 (0x1<<5) // BIST checker enable Enables BIST RX Control block, which enables the actual BIST RX block when appropriate
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X14_BCHK_EN_O_K2_E5_SHIFT                                           5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X14_BCHK_CLR_O_K2_E5                                                (0x1<<6) // BIST checker clear signal. Zeroes error counter output. Does NOT go through the RX BIST control block
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X14_BCHK_CLR_O_K2_E5_SHIFT                                          6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_K2_E5                                                             0x00183cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_BCHK_SRC_O_1_0_K2_E5                                            (0x3<<0) // BIST checker source. 0 - BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Aligner before Elastic Buffer 2 - BIST uses output of RX loopback mux before Decoder and Polbits 3 - BIST uses output of reg1 flop bank before Interface blocks
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_BCHK_SRC_O_1_0_K2_E5_SHIFT                                      0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_BIST_CHK_DATA_MODE_O_K2_E5                                      (0x1<<3) // Bist checker mode select. 0X0  UDP pattern. 0x1  PRBS pattern
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_BIST_CHK_DATA_MODE_O_K2_E5_SHIFT                                3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_BIST_CHK_LFSR_LENGTH_O_1_0_K2_E5                                (0x3<<4) // BIST PRBS pattern selector.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_BIST_CHK_LFSR_LENGTH_O_1_0_K2_E5_SHIFT                          4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_BIST_RX_CLOCK_ENABLE_K2_E5                                      (0x1<<7) // Active HIGH clock enable signal for the BIST receive clock
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_BIST_RX_CLOCK_ENABLE_K2_E5_SHIFT                                7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X16_K2_E5                                                             0x001840UL //Access:RW   DataWidth:0x8    // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This word should correspond to the alignment character used for the symbol alignment block.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X17_K2_E5                                                             0x001844UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X17_BIST_CHK_PREAM0_O_9_8_K2_E5                                     (0x3<<0) // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This word should correspond to the alignment character used for the symbol alignment block.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X17_BIST_CHK_PREAM0_O_9_8_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X17_BIST_CHK_INSERT_LENGTH_O_2_0_K2_E5                              (0x7<<2) // BIST Checker Insert word length.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X17_BIST_CHK_INSERT_LENGTH_O_2_0_K2_E5_SHIFT                        2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X17_BIST_CHK_SYNC_ON_ZEROS_K2_E5                                    (0x1<<5) // Setting this bit allows BIST to sync to RX value of zero
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X17_BIST_CHK_SYNC_ON_ZEROS_K2_E5_SHIFT                              5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X18_K2_E5                                                             0x001848UL //Access:RW   DataWidth:0x8    // BIST Check Preamble
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X19_K2_E5                                                             0x00184cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X19_BIST_CHK_PREAM1_O_9_8_K2_E5                                     (0x3<<0) // BIST Check Preamble
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X19_BIST_CHK_PREAM1_O_9_8_K2_E5_SHIFT                               0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X20_K2_E5                                                             0x001850UL //Access:RW   DataWidth:0x8    // Bist checker 40-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corresponds to 5 8-bit words. K code is assumed to be 0 in 8-bit mode.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X21_K2_E5                                                             0x001854UL //Access:RW   DataWidth:0x8    // BIST Check User-defined pattern
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X22_K2_E5                                                             0x001858UL //Access:RW   DataWidth:0x8    // BIST Check User-defined pattern
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X23_K2_E5                                                             0x00185cUL //Access:RW   DataWidth:0x8    // BIST Check User-defined pattern
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X24_K2_E5                                                             0x001860UL //Access:RW   DataWidth:0x8    // BIST Check User-defined pattern
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X25_K2_E5                                                             0x001864UL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X26_K2_E5                                                             0x001868UL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X27_K2_E5                                                             0x00186cUL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X28_K2_E5                                                             0x001870UL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X29_K2_E5                                                             0x001874UL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X30_K2_E5                                                             0x001878UL //Access:R    DataWidth:0x8    // Bist errors detected
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X31_K2_E5                                                             0x00187cUL //Access:R    DataWidth:0x8    // Bist errors detected
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X32_K2_E5                                                             0x001880UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 7-0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X33_K2_E5                                                             0x001884UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 15-8
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X34_K2_E5                                                             0x001888UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 23-16
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X35_K2_E5                                                             0x00188cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 31-24
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X36_K2_E5                                                             0x001890UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 39-32
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X37_K2_E5                                                             0x001894UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 47-40
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X38_K2_E5                                                             0x001898UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 55-48
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X39_K2_E5                                                             0x00189cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 63-56
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X40_K2_E5                                                             0x0018a0UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 71-64
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X41_K2_E5                                                             0x0018a4UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 79-72
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X42_K2_E5                                                             0x0018a8UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 87-80
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X43_K2_E5                                                             0x0018acUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 95-88
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X44_K2_E5                                                             0x0018b0UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 103-96
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X45_K2_E5                                                             0x0018b4UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 111-104
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X46_K2_E5                                                             0x0018b8UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 119-112
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X47_K2_E5                                                             0x0018bcUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 127-120
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X48_K2_E5                                                             0x0018c0UL //Access:RW   DataWidth:0x8    // Timing Window length for GCFSM for Gen 1/2 - for the new ICA method
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X49_K2_E5                                                             0x0018c4UL //Access:RW   DataWidth:0x8    // Timing Window length for GCFSM for Gen 3 - for the new ICA method
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X50_K2_E5                                                             0x0018c8UL //Access:RW   DataWidth:0x8    // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA method
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X51_K2_E5                                                             0x0018ccUL //Access:RW   DataWidth:0x8    // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA method
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X52_K2_E5                                                             0x0018d0UL //Access:RW   DataWidth:0x8    // The start length of DFE offset calibration's first cycle is the value of this register multiplied by 4.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X53_K2_E5                                                             0x0018d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X53_GCFSM_DFE_OFFSET_CAL_START_LEN_O_4_0_K2_E5                      (0x1f<<0) // The start length of DFE offset calibration, except for the 1st cycle.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X53_GCFSM_DFE_OFFSET_CAL_START_LEN_O_4_0_K2_E5_SHIFT                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2_K2_E5                               (0x1<<5) // COMLANE or LANE CSR Select for GCFSM Cycle Length registers  0 -	 Select COMLANE registers  1 -	 Select LANE registers
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2_K2_E5_SHIFT                         5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X53_GCFSM_LANE_TW_METHOD_EN_K2_E5                                   (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X53_GCFSM_LANE_TW_METHOD_EN_K2_E5_SHIFT                             6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X53_GCFSM_LANE_PMA_LOAD_OVR_K2_E5                                   (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X53_GCFSM_LANE_PMA_LOAD_OVR_K2_E5_SHIFT                             7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X54_K2_E5                                                             0x0018d8UL //Access:RW   DataWidth:0x8    // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X55_K2_E5                                                             0x0018dcUL //Access:RW   DataWidth:0x8    // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X56_K2_E5                                                             0x0018e0UL //Access:RW   DataWidth:0x8    // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_K2_E5                                                             0x0018e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_OVR_O_27_24_K2_E5                                         (0xf<<0) // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_OVR_O_27_24_K2_E5_SHIFT                                   0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_LANE_OUT_OVR_EN_O_K2_E5                                   (0x1<<4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes data stored in gcfsm_lane_pma_data_ovr_o to override calibration values for the block selected by gcfsm_lane_pma_cal_ovr_o.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_LANE_OUT_OVR_EN_O_K2_E5_SHIFT                             4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_LANE_PMA_LATCH_OVR_O_K2_E5                                (0x1<<5) // GCFSM pma_latch_o override
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_LANE_PMA_LATCH_OVR_O_K2_E5_SHIFT                          5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_LANE_PMA_GO_OVR_O_K2_E5                                   (0x1<<6) // GCFSM pma_go_o override
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_LANE_PMA_GO_OVR_O_K2_E5_SHIFT                             6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_LANE_PMA_READ_OVR_O_K2_E5                                 (0x1<<7) // GCFSM pma_read_o override.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_LANE_PMA_READ_OVR_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X58_K2_E5                                                             0x0018e8UL //Access:RW   DataWidth:0x8    // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X59_K2_E5                                                             0x0018ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X59_GCFSM_LANE_PMA_DATA_OVR_O_11_8_K2_E5                            (0xf<<0) // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X59_GCFSM_LANE_PMA_DATA_OVR_O_11_8_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X60_K2_E5                                                             0x0018f0UL //Access:RW   DataWidth:0x8    // General Calibration Finite State Machine GCFSM overide select, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA compone
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X61_K2_E5                                                             0x0018f4UL //Access:RW   DataWidth:0x8    // General Calibration Finite State Machine GCFSM overide select, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA compone
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X62_K2_E5                                                             0x0018f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X62_LN_MSM_REQ_IN_OVR_O_K2_E5                                       (0x3<<0) // Bit 0:  Override enable for msm_ln_req Bit 1 : Override msm_ln_req
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X62_LN_MSM_REQ_IN_OVR_O_K2_E5_SHIFT                                 0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X62_LN_MSM_FUNC_IN_OVR_O_K2_E5                                      (0x3f<<2) // Bit 2:  Override enable for msm_func Bits [7:3] : Override msm_func
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X62_LN_MSM_FUNC_IN_OVR_O_K2_E5_SHIFT                                2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X65_K2_E5                                                             0x001904UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X65_GCFSM_OVR_O_28_K2_E5                                            (0x1<<0) // Not currently used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X65_GCFSM_OVR_O_28_K2_E5_SHIFT                                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X66_K2_E5                                                             0x001908UL //Access:RW   DataWidth:0x8    // Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X67_K2_E5                                                             0x00190cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X67_CDR_CTRL_DLY_CDR_O_6_0_K2_E5                                    (0x7f<<0) // Number of clock cycles between signal detect indicator
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X67_CDR_CTRL_DLY_CDR_O_6_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_K2_E5                               (0x1<<7) // Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_K2_E5_SHIFT                         7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X68_K2_E5                                                             0x001910UL //Access:RW   DataWidth:0x8    // Number of clock cycles between CISEL assertion
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X69_K2_E5                                                             0x001914UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X69_CDR_CTRL_DLY_LANE_O_9_8_K2_E5                                   (0x3<<0) // Number of clock cycles between CISEL assertion
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X69_CDR_CTRL_DLY_LANE_O_9_8_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X69_CDR_CTRL_START_LEN_O_3_0_K2_E5                                  (0xf<<2) // Number of clock cycles between when CDR control block
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X69_CDR_CTRL_START_LEN_O_3_0_K2_E5_SHIFT                            2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X69_CDR_CTRL_INT_FIL_O_1_0_K2_E5                                    (0x3<<6) // CDR control DLPF positioning control.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X69_CDR_CTRL_INT_FIL_O_1_0_K2_E5_SHIFT                              6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X70_K2_E5                                                             0x001918UL //Access:RW   DataWidth:0x8    // CDR control block cycle length When not in PCIe Gen3.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X71_K2_E5                                                             0x00191cUL //Access:RW   DataWidth:0x8    // CDR control block cycle length When in PCIe Gen3.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X72_K2_E5                                                             0x001920UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X72_CDR_CTRL_MAX_DIFF_O_4_0_K2_E5                                   (0x1f<<0) // Maximum difference from DLPF center point.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X72_CDR_CTRL_MAX_DIFF_O_4_0_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X72_CDR_CTRL_MIN_BOUNCE_O_2_0_K2_E5                                 (0x7<<5) // Maximum difference from DLPF center point.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X72_CDR_CTRL_MIN_BOUNCE_O_2_0_K2_E5_SHIFT                           5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X73_K2_E5                                                             0x001924UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X73_CDR_CTRL_TW_METHOD_EN_K2_E5                                     (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X73_CDR_CTRL_TW_METHOD_EN_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X73_CDR_CONTROL_ATT_CTRL_O_K2_E5                                    (0x1<<1) // ATT wait control. Upon detection of signal, DFE ATT calibration is enabled, without CISEL being asserted to the CDR.  0 - CDR control block will wait for ATT calibration before proceeding 1 - CDR control block will not wait for ATT calibration
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X73_CDR_CONTROL_ATT_CTRL_O_K2_E5_SHIFT                              1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X73_RXEQ_WAIT_EN_O_K2_E5                                            (0x1<<2) // CDR control block wait for DFE signal.  0 - Do not wait for DFE calibration before enabling rx data 1 - Wait for DFE calibration before enabling rx data
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X73_RXEQ_WAIT_EN_O_K2_E5_SHIFT                                      2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X73_CDR_CTRL_DLY_CDR_O_9_7_K2_E5                                    (0x7<<3) // Number of clock cycles between signal detect indicator
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X73_CDR_CTRL_DLY_CDR_O_9_7_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X74_K2_E5                                                             0x001928UL //Access:RW   DataWidth:0x8    // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X75_K2_E5                                                             0x00192cUL //Access:RW   DataWidth:0x8    // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X76_K2_E5                                                             0x001930UL //Access:RW   DataWidth:0x8    // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X77_K2_E5                                                             0x001934UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X77_CDR_CTRL_OUT_OVR_O_29_24_K2_E5                                  (0x3f<<0) // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X77_CDR_CTRL_OUT_OVR_O_29_24_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X77_CDR_CTRL_CAL_LOAD_OVR_K2_E5                                     (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X77_CDR_CTRL_CAL_LOAD_OVR_K2_E5_SHIFT                               6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X78_K2_E5                                                             0x001938UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X78_SYM_ALIGN_ALIGN_POS_O_5_0_K2_E5                                 (0x3f<<0) // Symbol aligner position override enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X78_SYM_ALIGN_ALIGN_POS_O_5_0_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X78_SYM_ALIGN_MODE_O_1_0_K2_E5                                      (0x3<<6) // Symbol aligner mode select.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X78_SYM_ALIGN_MODE_O_1_0_K2_E5_SHIFT                                6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X79_K2_E5                                                             0x00193cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X79_SYM_ALIGN_BYPASS_O_K2_E5                                        (0x1<<0) // Asserting this register will bypass the symbol aligner
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X79_SYM_ALIGN_BYPASS_O_K2_E5_SHIFT                                  0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X80_K2_E5                                                             0x001940UL //Access:RW   DataWidth:0x8    // Number of cycles to wait before forcing exit form EI
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_K2_E5                                                             0x001944UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_EXIT_TIMER_LEN_O_9_8_K2_E5                        (0x3<<0) // Number of cycles to wait before forcing exit form EI
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_EXIT_TIMER_LEN_O_9_8_K2_E5_SHIFT                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_CLR_ERR_O_K2_E5                                   (0x1<<2) // Clears the elec idle control error flag
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_CLR_ERR_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_EI_INFERRED_O_K2_E5                               (0x1<<3) // Override for ei_inferred signal
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_EI_INFERRED_O_K2_E5_SHIFT                         3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O_K2_E5                            (0x1<<4) // Override for ei_mask signal
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O_K2_E5_SHIFT                      4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O_K2_E5                             (0x1<<5) // Override for ei_exit_type signal
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O_K2_E5_SHIFT                       5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_OVR_O_K2_E5                                       (0x1<<6) // EI control override enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_OVR_O_K2_E5_SHIFT                                 6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X82_K2_E5                                                             0x001948UL //Access:RW   DataWidth:0x8    // Number of cycles to wait before entering back into EI
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X83_K2_E5                                                             0x00194cUL //Access:RW   DataWidth:0x8    // Electrical Idle Control signal detect glitch filter counter
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X84_K2_E5                                                             0x001950UL //Access:RW   DataWidth:0x8    // Electrical Idle Control signal detect low filter min value
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X85_K2_E5                                                             0x001954UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X85_ELECIDLE_CTRL_LOCK_TIMER_LEN_O_9_8_K2_E5                        (0x3<<0) // Number of cycles to wait before entering back into EI
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X85_ELECIDLE_CTRL_LOCK_TIMER_LEN_O_9_8_K2_E5_SHIFT                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X85_ELECIDLE_CTRL_TIMER_LEN_SEL_O_1_0_K2_E5                         (0x3<<2) // EI Exit time cycles = timer_len_sel[1:0]+1*exit_timer_len_i[9:0]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X85_ELECIDLE_CTRL_TIMER_LEN_SEL_O_1_0_K2_E5_SHIFT                   2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X85_LOOPBACK_EN_O_K2_E5                                             (0x1<<4) // Control signal to force decoder into loopback mode
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X85_LOOPBACK_EN_O_K2_E5_SHIFT                                       4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X86_K2_E5                                                             0x001958UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X86_FES_LB_ENA_O_K2_E5                                              (0x1<<0) // FES loopback enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X86_FES_LB_ENA_O_K2_E5_SHIFT                                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X86_NES_LB_ENA_O_K2_E5                                              (0x1<<1) // NES loopback enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X86_NES_LB_ENA_O_K2_E5_SHIFT                                        1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X86_RXCLK_LB_ENA_O_K2_E5                                            (0x1<<2) // HS recovered clock to transmit loopback enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X86_RXCLK_LB_ENA_O_K2_E5_SHIFT                                      2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X87_K2_E5                                                             0x00195cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X87_AHB_PMA_LN_RX_BOOST_OVR_O_K2_E5                                 (0x1<<0) // RX boost override enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X87_AHB_PMA_LN_RX_BOOST_OVR_O_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_O_K2_E5                            (0x7f<<1) // RX boost override setting. Thermometer coded.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_O_K2_E5_SHIFT                      1
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X88_K2_E5                                                             0x001960UL //Access:RW   DataWidth:0x8    // RX boost override setting. Thermometer coded.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X89_K2_E5                                                             0x001964UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X89_AHB_PMA_LN_SD_THSEL_DIV1_O_K2_E5                                (0x7<<0) // Signal detect threshold select for Full rate
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X89_AHB_PMA_LN_SD_THSEL_DIV1_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X89_AHB_PMA_LN_SD_THSEL_DIV2_O_K2_E5                                (0x7<<3) // Signal detect threshold select for div-by-2 rate
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X89_AHB_PMA_LN_SD_THSEL_DIV2_O_K2_E5_SHIFT                          3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X89_AHB_PMA_LN_RXUP_O_K2_E5                                         (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X89_AHB_PMA_LN_RXUP_O_K2_E5_SHIFT                                   6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_K2_E5                                (0x1<<7) // RX FL calibration clock DIV4 enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X90_K2_E5                                                             0x001968UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X90_AHB_PMA_LN_SD_THSEL_DIV4_O_K2_E5                                (0x7<<0) // Signal detect threshold select for div-by-4 rate
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X90_AHB_PMA_LN_SD_THSEL_DIV4_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X90_AHB_PMA_LN_AGC_THSEL_O_K2_E5                                    (0x7<<3) // AGC threshold select
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X90_AHB_PMA_LN_AGC_THSEL_O_K2_E5_SHIFT                              3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X90_AHB_PMA_LN_VREGH_O_K2_E5                                        (0x3<<6) // Regulator VREGH setting
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X90_AHB_PMA_LN_VREGH_O_K2_E5_SHIFT                                  6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X91_K2_E5                                                             0x00196cUL //Access:RW   DataWidth:0x8    // RX FL calibration LDHS
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X92_K2_E5                                                             0x001970UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X92_AHB_PMA_LN_RXFL_LDHS_9_8_O_K2_E5                                (0x3<<0) // RX FL calibration LDHS
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X92_AHB_PMA_LN_RXFL_LDHS_9_8_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X92_AHB_PMA_LN_RXVCO_BIAS_O_K2_E5                                   (0xf<<2) // CDR VCO bias setting.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X92_AHB_PMA_LN_RXVCO_BIAS_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O_K2_E5                                (0x1<<6) // DLPF DIV2 enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O_K2_E5_SHIFT                          6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_K2_E5                                 (0x1<<7) // CDR DivN clock divider enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X93_K2_E5                                                             0x001974UL //Access:RW   DataWidth:0x8    // AFE spare controls
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X94_K2_E5                                                             0x001978UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X94_AHB_PMA_LN_CDR_DVDR_O_K2_E5                                     (0x3f<<0) // CDR DivN clock division ratio.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X94_AHB_PMA_LN_CDR_DVDR_O_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X94_AHB_PMA_LN_VREG_O_K2_E5                                         (0x3<<6) // Regulator VREG setting
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X94_AHB_PMA_LN_VREG_O_K2_E5_SHIFT                                   6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X95_K2_E5                                                             0x00197cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X95_AHB_PMA_LN_BB_STEP_O_K2_E5                                      (0xf<<0) // CDR bb_step
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X95_AHB_PMA_LN_BB_STEP_O_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X95_AHB_PMA_LN_INT_STEP_O_K2_E5                                     (0x7<<4) // CDR int step
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X95_AHB_PMA_LN_INT_STEP_O_K2_E5_SHIFT                               4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X95_AHB_PMA_LN_RXDWN_O_K2_E5                                        (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X95_AHB_PMA_LN_RXDWN_O_K2_E5_SHIFT                                  7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X96_K2_E5                                                             0x001980UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X96_AHB_PMA_LN_RXVCOFR_O_K2_E5                                      (0x7<<0) // RXVCOFR override value Enabled by pma_ln_dr_rxvcofr_sel_o
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X96_AHB_PMA_LN_RXVCOFR_O_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X96_AHB_PMA_LN_RXVCOFR_SEL_O_K2_E5                                  (0x1<<3) // Override enable for RXVCOFR override vakue
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X96_AHB_PMA_LN_RXVCOFR_SEL_O_K2_E5_SHIFT                            3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X96_AHB_PMA_LN_RX_SELR_O_K2_E5                                      (0x7<<4) // CTLE R degeneration select
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X96_AHB_PMA_LN_RX_SELR_O_K2_E5_SHIFT                                4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X97_K2_E5                                                             0x001984UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X97_AHB_PMA_LN_RX_SELC_O_K2_E5                                      (0x7<<0) // CTLE C degeneration select
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X97_AHB_PMA_LN_RX_SELC_O_K2_E5_SHIFT                                0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X99_K2_E5                                                             0x00198cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X99_PMA_LN_DFE_BW_SCALE_K2_E5                                       (0x3<<4) // DFE Bandwidth Selection
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X99_PMA_LN_DFE_BW_SCALE_K2_E5_SHIFT                                 4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X99_PMA_LN_PHD_ENA_O_1_0_K2_E5                                      (0x3<<6) // CDR phase detector proportional path enable bit 0: enables D4/D3 data/edge samplers bit 1: enables D1/D2 data/edge samplers
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X99_PMA_LN_PHD_ENA_O_1_0_K2_E5_SHIFT                                6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X100_K2_E5                                                            0x001990UL //Access:RW   DataWidth:0x8    // On-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 3-9: Fine x-direction offset, note bit reversal
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_K2_E5                                                            0x001994UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_EYE_DLY_O_8_8_K2_E5                                     (0x1<<0) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 2-8: Fine x-direction offset, note bit reversal
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_EYE_DLY_O_8_8_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_EYE_SGN_RST_O_K2_E5                                     (0x1<<2) // Reset signal for eye alignment mechanism.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_EYE_SGN_RST_O_K2_E5_SHIFT                               2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_SD_BWSEL_K2_E5                                          (0x1<<3) // RX signal detector bandwidth select. 0: Nominal bandwidth 1: 10% higher bandwidth
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_SD_BWSEL_K2_E5_SHIFT                                    3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_EYE_ENA270_O_K2_E5                                      (0x1<<4) // In eye diagram generation mode, assertion overrides the ck_270 DFE clock "right" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_EYE_ENA270_O_K2_E5_SHIFT                                4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_EYE_ENA90_O_K2_E5                                       (0x1<<5) // In eye diagram generation mode, assertion overrides the ck_90 DFE clock "left" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_EYE_ENA90_O_K2_E5_SHIFT                                 5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X102_K2_E5                                                            0x001998UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X102_PMA_LN_DFE_BIAS_O_3_0_K2_E5                                    (0xf<<0) // DFE bias setting.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X102_PMA_LN_DFE_BIAS_O_3_0_K2_E5_SHIFT                              0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X103_K2_E5                                                            0x00199cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X103_PMA_LN_TX_SR_FASTCAP_O_3_0_K2_E5                               (0xf<<0) // TX driver capacitive slew rate control.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X103_PMA_LN_TX_SR_FASTCAP_O_3_0_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X103_PMA_LN_TXEQ_POLARITY_O_3_0_K2_E5                               (0xf<<4) // TX coefficient polarity enable. Set to "1" for negative polarity. bit 0: Cm bit 1: C0 bit 2: C1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X103_PMA_LN_TXEQ_POLARITY_O_3_0_K2_E5_SHIFT                         4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X104_K2_E5                                                            0x0019a0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X104_PMA_LN_TX_SR_DAC_O_3_0_K2_E5                                   (0xf<<0) // TX slew rate DAC bias current control
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X104_PMA_LN_TX_SR_DAC_O_3_0_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X104_PMA_LN_HSCLK_SEL_O_K2_E5                                       (0x1<<4) // CDR clock divider bypass enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X104_PMA_LN_HSCLK_SEL_O_K2_E5_SHIFT                                 4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X105_K2_E5                                                            0x0019a4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X105_PMA_LN_TX_VREG_LEV_O_4_0_K2_E5                                 (0x1f<<0) // TX driver regulator voltage setting.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X105_PMA_LN_TX_VREG_LEV_O_4_0_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X105_PMA_LN_TXDRV_BLEED_ENA_O_K2_E5                                 (0x1<<5) // TX bleed enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X105_PMA_LN_TXDRV_BLEED_ENA_O_K2_E5_SHIFT                           5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X106_K2_E5                                                            0x0019a8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X106_AHB_PMA_LN_RX_BOOST_OVR_GEN3_O_K2_E5                           (0x1<<0) // RX boost override enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X106_AHB_PMA_LN_RX_BOOST_OVR_GEN3_O_K2_E5_SHIFT                     0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X106_AHB_PMA_LN_RX_BOOSTOVR_GEN3_6_0_O_K2_E5                        (0x7f<<1) // RX boost override setting. Thermometer coded.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X106_AHB_PMA_LN_RX_BOOSTOVR_GEN3_6_0_O_K2_E5_SHIFT                  1
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X107_K2_E5                                                            0x0019acUL //Access:RW   DataWidth:0x8    // RX boost override setting. Thermometer coded.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X108_K2_E5                                                            0x0019b0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X108_AHB_PMA_LN_SD_THSEL_GEN3_O_K2_E5                               (0x7<<0) // Signal detect threshold select for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X108_AHB_PMA_LN_SD_THSEL_GEN3_O_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X108_AHB_PMA_LN_AGC_THSEL_GEN3_O_K2_E5                              (0x7<<3) // AGC threshold select for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X108_AHB_PMA_LN_AGC_THSEL_GEN3_O_K2_E5_SHIFT                        3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X108_AHB_PMA_LN_RXUP_GEN3_O_K2_E5                                   (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X108_AHB_PMA_LN_RXUP_GEN3_O_K2_E5_SHIFT                             6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O_K2_E5                          (0x1<<7) // CDR VCO frequency lock counter divide by 4 enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O_K2_E5_SHIFT                    7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X109_K2_E5                                                            0x0019b4UL //Access:RW   DataWidth:0x8    // RX FL calibration LDHS for Gen3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X110_K2_E5                                                            0x0019b8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X110_AHB_PMA_LN_RXFL_LDHS_GEN3_9_8_O_K2_E5                          (0x3<<0) // RX FL calibration LDHS for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X110_AHB_PMA_LN_RXFL_LDHS_GEN3_9_8_O_K2_E5_SHIFT                    0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X110_AHB_PMA_LN_RXVCO_BIAS_GEN3_O_K2_E5                             (0xf<<2) // CDR VCO bias setting.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X110_AHB_PMA_LN_RXVCO_BIAS_GEN3_O_K2_E5_SHIFT                       2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X110_AHB_PMA_LN_DLPF_DIV2_ENA_GEN3_O_K2_E5                          (0x1<<6) // DLPF DIV2 enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X110_AHB_PMA_LN_DLPF_DIV2_ENA_GEN3_O_K2_E5_SHIFT                    6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O_K2_E5                           (0x1<<7) // CDR DivN clock divider enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O_K2_E5_SHIFT                     7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X111_K2_E5                                                            0x0019bcUL //Access:RW   DataWidth:0x8    // AFE spare controls for Gen3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X112_K2_E5                                                            0x0019c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X112_AHB_PMA_LN_CDR_DVDR_GEN3_O_K2_E5                               (0x3f<<0) // CDR DivN clock divider ratio..
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X112_AHB_PMA_LN_CDR_DVDR_GEN3_O_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X112_AHB_PMA_LN_VREG_GEN3_O_K2_E5                                   (0x3<<6) // Regulator VREG setting for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X112_AHB_PMA_LN_VREG_GEN3_O_K2_E5_SHIFT                             6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X113_K2_E5                                                            0x0019c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X113_AHB_PMA_LN_BB_STEP_GEN3_O_K2_E5                                (0xf<<0) // CDR bb_step for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X113_AHB_PMA_LN_BB_STEP_GEN3_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X113_AHB_PMA_LN_INT_STEP_GEN3_O_K2_E5                               (0x7<<4) // CDR int step for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X113_AHB_PMA_LN_INT_STEP_GEN3_O_K2_E5_SHIFT                         4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X113_AHB_PMA_LN_RXDWN_GEN3_O_K2_E5                                  (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X113_AHB_PMA_LN_RXDWN_GEN3_O_K2_E5_SHIFT                            7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X114_K2_E5                                                            0x0019c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X114_AHB_PMA_LN_RXVCOFR_GEN3_O_K2_E5                                (0x7<<0) // RXVCOFR override value for Gen3 Enabled by pma_ln_dr_rxvcofr_sel_o
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X114_AHB_PMA_LN_RXVCOFR_GEN3_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X114_AHB_PMA_LN_RX_SELR_GEN3_O_K2_E5                                (0x7<<3) // CTLE R degeneration select for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X114_AHB_PMA_LN_RX_SELR_GEN3_O_K2_E5_SHIFT                          3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X114_AHB_PMA_LN_VREGH_GEN3_O_K2_E5                                  (0x3<<6) // Not currently used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X114_AHB_PMA_LN_VREGH_GEN3_O_K2_E5_SHIFT                            6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X115_K2_E5                                                            0x0019ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X115_AHB_PMA_LN_RX_SELC_GEN3_O_K2_E5                                (0x7<<0) // CTLE R degeneration select for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X115_AHB_PMA_LN_RX_SELC_GEN3_O_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X119_K2_E5                                                            0x0019dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X119_AHB_TX_CXP_MARGIN_K2_E5                                        (0xf<<0) // Value to minus/add from the calibrated txterm value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X119_AHB_TX_CXP_MARGIN_K2_E5_SHIFT                                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X119_AHB_TX_CXN_MARGIN_K2_E5                                        (0xf<<4) // Value to minus/add from the calibrated txterm value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X119_AHB_TX_CXN_MARGIN_K2_E5_SHIFT                                  4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X120_K2_E5                                                            0x0019e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X120_AHB_TX_TC_WAIT_NEXT_CMP_K2_E5                                  (0xf<<0) // in txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator  the register ix X2 is the actual number of wait cycle
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X120_AHB_TX_TC_WAIT_NEXT_CMP_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X120_AHB_TX_TC_WAIT_NEXT_SAMPLE_K2_E5                               (0x7<<4) // in txterm calibration, the number refclk cycles to wait before sampling the up from the same comparator
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X120_AHB_TX_TC_WAIT_NEXT_SAMPLE_K2_E5_SHIFT                         4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_K2_E5                                                            0x0019e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_TC_CMP_OUT_NUM_SAMPLES_K2_E5                            (0xf<<0) // in txterm calibration, the number of samples to take from the same comparator
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_TC_CMP_OUT_NUM_SAMPLES_K2_E5_SHIFT                      0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_CXP_MARGIN_ADD_0_K2_E5                                  (0x1<<4) // when 1, the final tx term value is calibrated txterm value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_CXP_MARGIN_ADD_0_K2_E5_SHIFT                            4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_CXN_MARGIN_ADD_0_K2_E5                                  (0x1<<5) // when 1, the final tx term value is calibrated txterm value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_CXN_MARGIN_ADD_0_K2_E5_SHIFT                            5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_CX_OVR_ENA_K2_E5                                        (0x1<<6) // enable override calibrated txterm value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_CX_OVR_ENA_K2_E5_SHIFT                                  6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_TERM_EN_CAL_OVR_K2_E5                                   (0x1<<7) // Debug feature, when set forces circuit to be affected by ahb_tx_cdac_ovr
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_TERM_EN_CAL_OVR_K2_E5_SHIFT                             7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X122_K2_E5                                                            0x0019e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X122_AHB_TX_CXP_OVR_K2_E5                                           (0xf<<0) // override calibrated txterm value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X122_AHB_TX_CXP_OVR_K2_E5_SHIFT                                     0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X122_AHB_TX_CXN_OVR_K2_E5                                           (0xf<<4) // override calibrated txterm value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X122_AHB_TX_CXN_OVR_K2_E5_SHIFT                                     4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X123_K2_E5                                                            0x0019ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X123_TX_CTRL_O_0_K2_E5                                              (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not currently used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X123_TX_CTRL_O_0_K2_E5_SHIFT                                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X123_TX_CTRL_O_7_2_K2_E5                                            (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_slew_sld[1:0]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X123_TX_CTRL_O_7_2_K2_E5_SHIFT                                      2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X124_K2_E5                                                            0x0019f0UL //Access:RW   DataWidth:0x8    // Bits 12:8: txdrv_c1_in[4:0] Bits 15:13: txdrv_c2_in[2:0]
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X125_K2_E5                                                            0x0019f4UL //Access:RW   DataWidth:0x8    // Bits 19-16: txdrv_cm_in[3:0]  Bits 22-20: tx_slew_sld3f[2:0] Bit 23: txdrv_preem_1lsb_mode
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_K2_E5                                                            0x0019f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_EN_O_K2_E5                                                (0x1<<0) // DFE block enable signal.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_EN_O_K2_E5_SHIFT                                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_RATE_OW_O_2_0_K2_E5                                    (0x7<<1) // These bits have similar functionality as rxeq_rate_ow_o_2_0 bits in COMLANE CSR. These are used mainly in COMBINATION modes of operation. They are logically OR'ed with the bits in COMLANE.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_RATE_OW_O_2_0_K2_E5_SHIFT                              1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_RATE1_CAL_EN_O_3_K2_E5                                 (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_RATE1_CAL_EN_O_3_K2_E5_SHIFT                           4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_RATE2_CAL_EN_O_4_K2_E5                                 (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_RATE2_CAL_EN_O_4_K2_E5_SHIFT                           5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_RATE3_CAL_EN_O_5_K2_E5                                 (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_RATE3_CAL_EN_O_5_K2_E5_SHIFT                           6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_FORCE_CAL_O_6_K2_E5                                    (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_FORCE_CAL_O_6_K2_E5_SHIFT                              7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X127_K2_E5                                                            0x0019fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X127_RXEQ_CONT_CAL_O_6_0_K2_E5                                      (0x7f<<0) // 0 : enables att calibration 1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6: enables tap5 dfe calibration This register Is not bit reversed
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X127_RXEQ_CONT_CAL_O_6_0_K2_E5_SHIFT                                0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X128_K2_E5                                                            0x001a00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X128_RXEQ_INIT_CAL_O_6_0_K2_E5                                      (0x7f<<0) // 0 : enables att calibration 1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6: enables tap5 dfe calibration This register Is not bit reversed
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X128_RXEQ_INIT_CAL_O_6_0_K2_E5_SHIFT                                0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X130_K2_E5                                                            0x001a08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X130_RXEQ_RATE1_ATT_START_O_3_0_K2_E5                               (0xf<<0) // ATT start value for rate1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X130_RXEQ_RATE1_ATT_START_O_3_0_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X130_RXEQ_RATE1_BOOST_START_O_3_0_K2_E5                             (0xf<<4) // Boost start value for rate1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X130_RXEQ_RATE1_BOOST_START_O_3_0_K2_E5_SHIFT                       4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X131_K2_E5                                                            0x001a0cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X131_RXEQ_RATE2_ATT_START_O_3_0_K2_E5                               (0xf<<0) // ATT start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X131_RXEQ_RATE2_ATT_START_O_3_0_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X131_RXEQ_RATE2_BOOST_START_O_3_0_K2_E5                             (0xf<<4) // Boost start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X131_RXEQ_RATE2_BOOST_START_O_3_0_K2_E5_SHIFT                       4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X132_K2_E5                                                            0x001a10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X132_RXEQ_RATE2_TAP1_START_O_6_0_K2_E5                              (0x7f<<0) // DFE Tap1 start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X132_RXEQ_RATE2_TAP1_START_O_6_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X133_K2_E5                                                            0x001a14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X133_RXEQ_RATE2_TAP2_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap2 start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X133_RXEQ_RATE2_TAP2_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X134_K2_E5                                                            0x001a18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X134_RXEQ_RATE2_TAP3_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap3 start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X134_RXEQ_RATE2_TAP3_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X135_K2_E5                                                            0x001a1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X135_RXEQ_RATE2_TAP4_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap4 start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X135_RXEQ_RATE2_TAP4_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X136_K2_E5                                                            0x001a20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X136_RXEQ_RATE2_TAP5_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap5 start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X136_RXEQ_RATE2_TAP5_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X137_K2_E5                                                            0x001a24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X137_RXEQ_RATE3_ATT_START_O_3_0_K2_E5                               (0xf<<0) // ATT start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X137_RXEQ_RATE3_ATT_START_O_3_0_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X137_RXEQ_RATE3_BOOST_START_O_3_0_K2_E5                             (0xf<<4) // Boost start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X137_RXEQ_RATE3_BOOST_START_O_3_0_K2_E5_SHIFT                       4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X138_K2_E5                                                            0x001a28UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X138_RXEQ_RATE3_TAP1_START_O_6_0_K2_E5                              (0x7f<<0) // DFE Tap1 start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X138_RXEQ_RATE3_TAP1_START_O_6_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X139_K2_E5                                                            0x001a2cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X139_RXEQ_RATE3_TAP2_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap2 start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X139_RXEQ_RATE3_TAP2_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X140_K2_E5                                                            0x001a30UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X140_RXEQ_RATE3_TAP3_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap3 start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X140_RXEQ_RATE3_TAP3_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X141_K2_E5                                                            0x001a34UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X141_RXEQ_RATE3_TAP4_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap4 start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X141_RXEQ_RATE3_TAP4_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X142_K2_E5                                                            0x001a38UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X142_RXEQ_RATE3_TAP5_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap5 start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X142_RXEQ_RATE3_TAP5_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X143_K2_E5                                                            0x001a3cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X143_RXEQ_SUPERBST_AUTOCAL_DIS_K2_E5                                (0x1<<0) // Disable auto cal w/ rx_superbst
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X143_RXEQ_SUPERBST_AUTOCAL_DIS_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X143_BOOST_MAX_LIMIT_O_K2_E5                                        (0xf<<1) // Max limit value for BOOST auto-calibration
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X143_BOOST_MAX_LIMIT_O_K2_E5_SHIFT                                  1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X143_BOOST_MAX_LIMIT_EN_O_K2_E5                                     (0x1<<5) // Enable Max limiting for BOOST auto-calibration
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X143_BOOST_MAX_LIMIT_EN_O_K2_E5_SHIFT                               5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X143_RX_ATT_BOOST_CAL_O_1_0_K2_E5                                   (0x3<<6) // rx_att_boost setting used during ATT calibration
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X143_RX_ATT_BOOST_CAL_O_1_0_K2_E5_SHIFT                             6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X144_K2_E5                                                            0x001a40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X144_RX_ATT_BOOST_NORM_O_1_0_K2_E5                                  (0x3<<0) // rx_att_boost setting used after ATT calibration
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X144_RX_ATT_BOOST_NORM_O_1_0_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X144_RXEQ_BOOST_ADJ_EN_O_K2_E5                                      (0x1<<2) // boost_adj_en
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X144_RXEQ_BOOST_ADJ_EN_O_K2_E5_SHIFT                                2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X144_RXEQ_BOOST_ADJ_DIR_O_K2_E5                                     (0x1<<3) // boost_adj_dir
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X144_RXEQ_BOOST_ADJ_DIR_O_K2_E5_SHIFT                               3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X144_RXEQ_BOOST_ADJ_VAL_O_K2_E5                                     (0xf<<4) // boost_adj_val This register Is not bit reversed
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X144_RXEQ_BOOST_ADJ_VAL_O_K2_E5_SHIFT                               4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X145_K2_E5                                                            0x001a44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X145_CMP_OFFSET_AVG_MAX_NUMSAMPLES_6_0_K2_E5                        (0x7f<<0) // Max number of samples to be used for CMP Offset Noise Averaging
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X145_CMP_OFFSET_AVG_MAX_NUMSAMPLES_6_0_K2_E5_SHIFT                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X145_CMP_OFFSET_AVG_EN_O_K2_E5                                      (0x1<<7) // CMP Offset Noise Averaging Enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X145_CMP_OFFSET_AVG_EN_O_K2_E5_SHIFT                                7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X146_K2_E5                                                            0x001a48UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X147_K2_E5                                                            0x001a4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X147_RXEQ_DFE_TAP_PD_WAIT_11_8_K2_E5                                (0xf<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X147_RXEQ_DFE_TAP_PD_WAIT_11_8_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X147_PMA_LN_DFE_OFS_CAL_ENA_K2_E5                                   (0x3<<4) // DFE offset calibration enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X147_PMA_LN_DFE_OFS_CAL_ENA_K2_E5_SHIFT                             4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS_K2_E5                                (0x1<<6) // Disable auto cal w/ rx_att_gain
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS_K2_E5_SHIFT                          6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X147_RXEQ_SUPERBST_EN_INVERT_O_K2_E5                                (0x1<<7) // Inverts the polarity of superboost_en before assigning to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X147_RXEQ_SUPERBST_EN_INVERT_O_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X148_K2_E5                                                            0x001a50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X148_RXEQ_OVR_LOAD_EN_O_6_0_K2_E5                                   (0x7f<<0) // Override for RXEQ_CTRL output register load enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X148_RXEQ_OVR_LOAD_EN_O_6_0_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X148_RXEQ_OVR_EN_O_K2_E5                                            (0x1<<7) // Override enable for DFE signals.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X148_RXEQ_OVR_EN_O_K2_E5_SHIFT                                      7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X149_K2_E5                                                            0x001a54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X149_RXEQ_OVR_LOAD_O_6_0_K2_E5                                      (0x7f<<0) // Override for RXEQ_CTRL output register load value.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X149_RXEQ_OVR_LOAD_O_6_0_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X149_RXEQ_OVR_LATCH_O_K2_E5                                         (0x1<<7) // Override for DFE latch signal. Negative edge causes AFE to store values of DFE output registers.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X149_RXEQ_OVR_LATCH_O_K2_E5_SHIFT                                   7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_K2_E5                                                            0x001a58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_RXEQ_DFE_CMP_SEL_OVR_O_2_0_K2_E5                               (0x7<<0) // Override value for comparator calibration select. Enabled by rxeq_ovr_en_o: 1: Calibrate DFE comparator 1 2: Calibrate DFE comparator 2 3: Calibrate DFE comparator 3 4: Calibrate DFE comparator 4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_RXEQ_DFE_CMP_SEL_OVR_O_2_0_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_RXEQ_ATT_GAIN_OVR_K2_E5                                        (0x3<<3) // Override the value of rx_att_gain output to PMA when rx_att_gain_autocal_dis=1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_RXEQ_ATT_GAIN_OVR_K2_E5_SHIFT                                  3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_RXEQ_SUPERBST_ENA_OVR_K2_E5                                    (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_autocal_dis=1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_RXEQ_SUPERBST_ENA_OVR_K2_E5_SHIFT                              5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6_K2_E5                           (0x1<<6) // DFE TAP CMP no offset override enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6_K2_E5_SHIFT                     6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_DFE_TAP_OVR_EN_O_7_K2_E5                                       (0x1<<7) // DFE TAP override enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_DFE_TAP_OVR_EN_O_7_K2_E5_SHIFT                                 7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X151_K2_E5                                                            0x001a5cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X151_DFE_OFFSET_CAL_TAP_EN_OVR_O_7_3_K2_E5                          (0x1f<<0) // DFE offset calibration TAP enable override
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X151_DFE_OFFSET_CAL_TAP_EN_OVR_O_7_3_K2_E5_SHIFT                    0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0_K2_E5                            (0x1<<5) // DFE offset calibrated value override enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0_K2_E5_SHIFT                      5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X151_DFE_OFFSET_CAL_EN_OVR_O_1_K2_E5                                (0x1<<6) // DFE offset cal enable override
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X151_DFE_OFFSET_CAL_EN_OVR_O_1_K2_E5_SHIFT                          6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X151_DFE_CMP_CAL_EN_OVR_O_2_K2_E5                                   (0x1<<7) // DFE comparator cal enable override
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X151_DFE_CMP_CAL_EN_OVR_O_2_K2_E5_SHIFT                             7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X152_K2_E5                                                            0x001a60UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X152_DFE_TAP1_OVR_VAL_O_6_0_K2_E5                                   (0x7f<<0) // DFE Tap 1 Override Value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X152_DFE_TAP1_OVR_VAL_O_6_0_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X153_K2_E5                                                            0x001a64UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X153_DFE_TAP2_OVR_VAL_O_5_0_K2_E5                                   (0x3f<<0) // DFE Tap 2 Override Value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X153_DFE_TAP2_OVR_VAL_O_5_0_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X154_K2_E5                                                            0x001a68UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X154_DFE_TAP3_OVR_VAL_O_5_0_K2_E5                                   (0x3f<<0) // DFE Tap 3 Override Value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X154_DFE_TAP3_OVR_VAL_O_5_0_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X155_K2_E5                                                            0x001a6cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X155_DFE_TAP4_OVR_VAL_O_5_0_K2_E5                                   (0x3f<<0) // DFE Tap 4 Override Value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X155_DFE_TAP4_OVR_VAL_O_5_0_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X156_K2_E5                                                            0x001a70UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X156_DFE_TAP5_OVR_VAL_O_5_0_K2_E5                                   (0x3f<<0) // DFE Tap 5 Override Value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X156_DFE_TAP5_OVR_VAL_O_5_0_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X157_K2_E5                                                            0x001a74UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X157_TXEQ_ADAPT_EN_O_0_K2_E5                                        (0x1<<0) // TX Equalizer adaptation function enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X157_TXEQ_ADAPT_EN_O_0_K2_E5_SHIFT                                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X157_TXEQ_ERR_SIGN_O_1_K2_E5                                        (0x1<<1) // TX Equalizer Error Sign
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X157_TXEQ_ERR_SIGN_O_1_K2_E5_SHIFT                                  1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X157_TXEQ_FW_OVRIDE_O_2_K2_E5                                       (0x1<<2) // TX Equalization Firmware over ride  0 -	 Disable firmware based adaptation  1 -	 Enbale firmware based adaptation
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X157_TXEQ_FW_OVRIDE_O_2_K2_E5_SHIFT                                 2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X158_K2_E5                                                            0x001a78UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X158_TXEQ_ERR_STAT_I_1_0_K2_E5                                      (0x3<<0) // TX Equalization error state
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X158_TXEQ_ERR_STAT_I_1_0_K2_E5_SHIFT                                0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X159_K2_E5                                                            0x001a7cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X159_TXEQ_OVER_EQ_CNT_I_9_8_K2_E5                                   (0x3<<0) // Over equalization count 9-8
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X159_TXEQ_OVER_EQ_CNT_I_9_8_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X160_K2_E5                                                            0x001a80UL //Access:R    DataWidth:0x8    // Over equalization count 7-0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X161_K2_E5                                                            0x001a84UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X161_TXEQ_UNDER_EQ_CNT_I_9_8_K2_E5                                  (0x3<<0) // Under equalization count 9-8
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X161_TXEQ_UNDER_EQ_CNT_I_9_8_K2_E5_SHIFT                            0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X162_K2_E5                                                            0x001a88UL //Access:R    DataWidth:0x8    // Under equalization count 7-0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X163_K2_E5                                                            0x001a8cUL //Access:RW   DataWidth:0x8    // TX Equalizer Training Pattern
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X164_K2_E5                                                            0x001a90UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X164_TXEQ_TRAINING_PATT_O_8_K2_E5                                   (0x1<<0) // TX Equalizer Training Pattern
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X164_TXEQ_TRAINING_PATT_O_8_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X165_K2_E5                                                            0x001a94UL //Access:RW   DataWidth:0x8    // Mask bit for Txeq training pattern
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X166_K2_E5                                                            0x001a98UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X166_TXEQ_DONT_CARE_O_8_K2_E5                                       (0x1<<0) // Mask bit for Txeq training pattern
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X166_TXEQ_DONT_CARE_O_8_K2_E5_SHIFT                                 0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X167_K2_E5                                                            0x001a9cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X167_TXEQ_RXRECAL_INIT_O_7_K2_E5                                    (0x1<<0) // This bit has similar function as txeq_rxrecal_init  in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X167_TXEQ_RXRECAL_INIT_O_7_K2_E5_SHIFT                              0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X168_K2_E5                                                            0x001aa0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X168_INIT_RX_PRESET_HINT_EN_O_K2_E5                                 (0x1<<0) // Enable for primary input lnx_rx_preset_hint during init cal.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X168_INIT_RX_PRESET_HINT_EN_O_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X168_RECAL_RX_PRESET_HINT_EN_O_K2_E5                                (0x1<<1) // Enable for primary input lnx_rx_preset_hint during recal.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X168_RECAL_RX_PRESET_HINT_EN_O_K2_E5_SHIFT                          1
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X169_K2_E5                                                            0x001aa4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X169_TXEQ_RXRECAL_DONE_I_0_K2_E5                                    (0x1<<0) // TX - RECAL RX Equalization status
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X169_TXEQ_RXRECAL_DONE_I_0_K2_E5_SHIFT                              0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X170_K2_E5                                                            0x001aa8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X170_BLOCK_DEC_ERR_K2_E5                                            (0x1<<0) // decoder sync header error
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X170_BLOCK_DEC_ERR_K2_E5_SHIFT                                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X201_K2_E5                                                            0x001b24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X201_CDFE_EN_O_0_K2_E5                                              (0x1<<0) // cdfe enable bit.  1: enable cdfe when rate is 2'b01 or 2'b10.  0: disable cdfe.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X201_CDFE_EN_O_0_K2_E5_SHIFT                                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X201_CDFE_WORD_OV_O_1_0_K2_E5                                       (0x3<<1) // The cdfe input word_i overwrite.                                                                                                         2'b00: the word_i input for cdfe block is internally generated.                                     2'b10: the word_i input for cdfe block is set to 0 8-bit or 10-bit mode.                                                       2'b11: the word_i input for cdfe block is set to 1 16-bit or 20-bit mode.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X201_CDFE_WORD_OV_O_1_0_K2_E5_SHIFT                                 1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X201_CDFE_MODE_8B_OV_O_1_0_K2_E5                                    (0x3<<3) // The cdfe input mode_8b_i overwrite.                                                                                                         2'b00: the mode_8b_i input for cdfe block is internally generated.                                      2'b01: the mode_8b_i input for cdfe block is set to 0 10-bit or 20-bit mode.                                                      2'b11: the mode_8b_i input for cdfe block is set to 1 8-bit or 16-bit mode.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X201_CDFE_MODE_8B_OV_O_1_0_K2_E5_SHIFT                              3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X201_CDFE_RATE_OV_O_2_0_K2_E5                                       (0x7<<5) // The cdfe input rate_i[1:0] overwrite.                                                                                                         3'b0xx: the rate_i input for cdfe block is internally generated.                                     3'b1xx: the rate_i[1:0] input for cdfe block is set to cdfe_rate_ov_o[1:0]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X201_CDFE_RATE_OV_O_2_0_K2_E5_SHIFT                                 5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X202_K2_E5                                                            0x001b28UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X203_K2_E5                                                            0x001b2cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X203_CDFE_GO_K2_E5                                                  (0x1<<4) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X203_CDFE_GO_K2_E5_SHIFT                                            4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X203_CDFE_LN_FORCE_CAL_K2_E5                                        (0x1<<5) // The cdfe force calibration enable.  1: enable force cdfe calibration.  0: disable force cdfe calibration.  Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X203_CDFE_LN_FORCE_CAL_K2_E5_SHIFT                                  5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X203_CDFE_LN_RATE_CHANGE_CAL_K2_E5                                  (0x1<<6) // The cdfe force calibration enable.  1: enable force cdfe calibration.  0: disable force cdfe calibration.  Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X203_CDFE_LN_RATE_CHANGE_CAL_K2_E5_SHIFT                            6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X203_CDFE_LN_EI_EXIT_CAL_K2_E5                                      (0x1<<7) // EI exit cdfe calibration enable.                                                                                                   1: the cdfe calibration is enabled when EI exits and when rate is  2'b01 or 2'b10.                                  0: the cdfe calibration is disabled when EI exits.                                                                    Note: EI exit cdfe calibration is only enabled when EI exit edfe calibration is also enabled.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X203_CDFE_LN_EI_EXIT_CAL_K2_E5_SHIFT                                7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_K2_E5                                                            0x001b30UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_CONT_CAL_K2_E5                                         (0x1<<0) // Continuous cdfe calibration enable.                                                                                            1: the continuous cdfe calibration is enabled when the rate is  2'b01 or 2'b10.                                  0: the continuous cdfe calibration is disabled.                                                                        Note: Continuout cdfe calibration is only enabled when continuous edfe calibration is also enabled.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_CONT_CAL_K2_E5_SHIFT                                   0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL_K2_E5                             (0x1<<1) // Enables cdfe calibration during Txeq adaptation phase.                                                                                            1: the cdfe calibration is enabled when the rate is  2'b10.                                  0: the cdfe calibration is disabled.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL_K2_E5_SHIFT                       1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL_K2_E5                              (0x1<<2) // Enables cdfe calibration post Txeq adaptation.                                                                                            1: the cdfe calibration is enabled when the rate is  2'b10.                                  0: the cdfe calibration is disabled.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL_K2_E5_SHIFT                        2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_RATE3_CAL_EN_K2_E5                                     (0x1<<3) // Enables the cdfe calibration in rate3.  1: enables cdfe calibration.  0: disables cdfe calibration.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_RATE3_CAL_EN_K2_E5_SHIFT                               3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_RATE2_CAL_EN_K2_E5                                     (0x1<<4) // Enables the cdfe calibration in rate2.  1: enables cdfe calibration.  0: disables cdfe calibration.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_RATE2_CAL_EN_K2_E5_SHIFT                               4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X205_K2_E5                                                            0x001b34UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during init cal in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X206_K2_E5                                                            0x001b38UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during continuos cal in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X207_K2_E5                                                            0x001b3cUL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during re-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X208_K2_E5                                                            0x001b40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X208_AHB_CDFE_COARSE_DLL_OV_EN_K2_E5                                (0x1<<7) // cdfe coarse dll overwrite enable.  1: enable coarse dll overwrite for cdfe.  0: disable coarse dll overwrite for cdfe.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X208_AHB_CDFE_COARSE_DLL_OV_EN_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X213_K2_E5                                                            0x001b54UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during txeq adaptation phase in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X214_K2_E5                                                            0x001b58UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during post  txeq adaptation  in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X215_K2_E5                                                            0x001b5cUL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during init cal in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X216_K2_E5                                                            0x001b60UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during continuos cal in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X217_K2_E5                                                            0x001b64UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during re-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X220_K2_E5                                                            0x001b70UL //Access:RW   DataWidth:0x8    // Start value for dlev_ref.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X221_K2_E5                                                            0x001b74UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X221_CDFE_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_K2_E5                   (0x1f<<0) // Enables copying of adapted tap values to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enables/disables copying to tap3 bit[3] : enables/disables copying to tap4 bit[4] : enables/disables copying to tap5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X221_CDFE_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_K2_E5_SHIFT             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X222_K2_E5                                                            0x001b78UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X222_CDFE_NON_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_K2_E5               (0x1f<<0) // Enables copying of adapted tap values to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enables/disables copying to tap3 bit[3] : enables/disables copying to tap4 bit[4] : enables/disables copying to tap5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X222_CDFE_NON_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_K2_E5_SHIFT         0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X223_K2_E5                                                            0x001b7cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X223_AHB_CDFE_CMP1_TAP1_OFFSET_K2_E5                                (0x7f<<0) // Override for CMP1 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[1]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X223_AHB_CDFE_CMP1_TAP1_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X224_K2_E5                                                            0x001b80UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X224_AHB_CDFE_CMP1_TAP2_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP1 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[2]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X224_AHB_CDFE_CMP1_TAP2_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X225_K2_E5                                                            0x001b84UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X225_AHB_CDFE_CMP1_TAP3_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP1 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[3]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X225_AHB_CDFE_CMP1_TAP3_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X226_K2_E5                                                            0x001b88UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X226_AHB_CDFE_CMP1_TAP4_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP1 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[4]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X226_AHB_CDFE_CMP1_TAP4_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X227_K2_E5                                                            0x001b8cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X227_AHB_CDFE_CMP1_TAP5_OFFSET_K2_E5                                (0x3f<<0) // Override for CMP1 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[5]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X227_AHB_CDFE_CMP1_TAP5_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X228_K2_E5                                                            0x001b90UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X228_AHB_CDFE_CMP2_TAP1_OFFSET_K2_E5                                (0x7f<<0) // Override for CMP2 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[1]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X228_AHB_CDFE_CMP2_TAP1_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X229_K2_E5                                                            0x001b94UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X229_AHB_CDFE_CMP2_TAP2_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP2 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[2]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X229_AHB_CDFE_CMP2_TAP2_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X230_K2_E5                                                            0x001b98UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X230_AHB_CDFE_CMP2_TAP3_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP2 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[3]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X230_AHB_CDFE_CMP2_TAP3_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X231_K2_E5                                                            0x001b9cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X231_AHB_CDFE_CMP2_TAP4_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP2 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[4]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X231_AHB_CDFE_CMP2_TAP4_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X232_K2_E5                                                            0x001ba0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X232_AHB_CDFE_CMP2_TAP5_OFFSET_K2_E5                                (0x3f<<0) // Override for CMP2 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[5]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X232_AHB_CDFE_CMP2_TAP5_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X233_K2_E5                                                            0x001ba4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X233_AHB_CDFE_CMP3_TAP1_OFFSET_K2_E5                                (0x7f<<0) // Override for CMP3 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[1]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X233_AHB_CDFE_CMP3_TAP1_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X234_K2_E5                                                            0x001ba8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X234_AHB_CDFE_CMP3_TAP2_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP3 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[2]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X234_AHB_CDFE_CMP3_TAP2_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X235_K2_E5                                                            0x001bacUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X235_AHB_CDFE_CMP3_TAP3_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP3 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[3]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X235_AHB_CDFE_CMP3_TAP3_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X236_K2_E5                                                            0x001bb0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X236_AHB_CDFE_CMP3_TAP4_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP3 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[4]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X236_AHB_CDFE_CMP3_TAP4_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X237_K2_E5                                                            0x001bb4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X237_AHB_CDFE_CMP3_TAP5_OFFSET_K2_E5                                (0x3f<<0) // Override for CMP3 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[5]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X237_AHB_CDFE_CMP3_TAP5_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X238_K2_E5                                                            0x001bb8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X238_AHB_CDFE_CMP4_TAP1_OFFSET_K2_E5                                (0x7f<<0) // Override for CMP4 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[1]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X238_AHB_CDFE_CMP4_TAP1_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X239_K2_E5                                                            0x001bbcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X239_AHB_CDFE_CMP4_TAP2_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP4 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[2]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X239_AHB_CDFE_CMP4_TAP2_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X240_K2_E5                                                            0x001bc0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X240_AHB_CDFE_CMP4_TAP3_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP4 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[3]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X240_AHB_CDFE_CMP4_TAP3_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X241_K2_E5                                                            0x001bc4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X241_AHB_CDFE_CMP4_TAP4_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP4 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[4]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X241_AHB_CDFE_CMP4_TAP4_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X242_K2_E5                                                            0x001bc8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X242_AHB_CDFE_CMP4_TAP5_OFFSET_K2_E5                                (0x3f<<0) // Override for CMP4 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[5]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X242_AHB_CDFE_CMP4_TAP5_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X243_K2_E5                                                            0x001bccUL //Access:RW   DataWidth:0x8    // Override for CMP1 main calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[0]
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X244_K2_E5                                                            0x001bd0UL //Access:RW   DataWidth:0x8    // Override for CMP2 main calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[0]
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X245_K2_E5                                                            0x001bd4UL //Access:RW   DataWidth:0x8    // Override for CMP3 main calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[0]
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X246_K2_E5                                                            0x001bd8UL //Access:RW   DataWidth:0x8    // Override for CMP4 main calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[0]
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X247_K2_E5                                                            0x001bdcUL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X248_K2_E5                                                            0x001be0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X248_AHB_CDFE_DLL_FINE_MASK_9_8_K2_E5                               (0x3<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X248_AHB_CDFE_DLL_FINE_MASK_9_8_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X248_AHB_CDFE_FINE_DLL_EDGE_SHIFT_K2_E5                             (0xf<<2) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X248_AHB_CDFE_FINE_DLL_EDGE_SHIFT_K2_E5_SHIFT                       2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X249_K2_E5                                                            0x001be4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X249_AHB_CDFE_ERR_SMPL_SHIFT_K2_E5                                  (0xf<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X249_AHB_CDFE_ERR_SMPL_SHIFT_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X249_AHB_CDFE_FINE_DLL_OV_EN_K2_E5                                  (0x1<<4) // cdfe fine dll overwrite enable.  1: enable fine dll overwrite for cdfe.  0: disable fine dll overwrite for cdfe.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X249_AHB_CDFE_FINE_DLL_OV_EN_K2_E5_SHIFT                            4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_K2_E5                                                            0x001be8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8_K2_E5                        (0x1<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8_K2_E5_SHIFT                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_K2_E5                       (0x1<<1) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_K2_E5_SHIFT                 1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8_K2_E5                        (0x1<<2) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8_K2_E5_SHIFT                  2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_K2_E5                       (0x1<<3) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_K2_E5_SHIFT                 3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X251_K2_E5                                                            0x001becUL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X252_K2_E5                                                            0x001bf0UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X253_K2_E5                                                            0x001bf4UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X254_K2_E5                                                            0x001bf8UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_K2_E5                                                            0x001bfcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_CDFE_DIR_OV_EN_K2_E5                                           (0x1<<0) // Override enable for CDFE calibration direction
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_CDFE_DIR_OV_EN_K2_E5_SHIFT                                     0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_CDFE_DIR_OV_VAL_K2_E5                                          (0x1<<1) // Override value for CDFE calibration direction
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_CDFE_DIR_OV_VAL_K2_E5_SHIFT                                    1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_EYE_ENA270_OVR_EN_O_K2_E5                               (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_EYE_ENA270_OVR_EN_O_K2_E5_SHIFT                         2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_EYE_ENA90_OVR_EN_O_K2_E5                                (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_EYE_ENA90_OVR_EN_O_K2_E5_SHIFT                          3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_PHD_ENA_OVR_EN_O_K2_E5                                  (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_PHD_ENA_OVR_EN_O_K2_E5_SHIFT                            4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_EYE_DLY_OVR_EN_O_K2_E5                                  (0x1<<5) // cdfe eye delay overwrite enable.  1: enable eye delay overwrite for cdfe.  0: disable eye delay overwrite for cdfe.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_EYE_DLY_OVR_EN_O_K2_E5_SHIFT                            5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O_K2_E5                              (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O_K2_E5_SHIFT                        6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X256_K2_E5                                                            0x001c00UL //Access:RW   DataWidth:0x8    // cdfe eye delay count overwrite value for CLK90.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X257_K2_E5                                                            0x001c04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8_K2_E5                           (0x1<<0) // cdfe eye delay count overwrite value for CLK90.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8_K2_E5_SHIFT                     0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_K2_E5                   (0x7f<<1) // This register represents the maximum comparator offset from the midpoint code 127/128 that must be met for the comparator to be selected as adaptation comparator during dlev and tap adaptation.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_K2_E5_SHIFT             1
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X258_K2_E5                                                            0x001c08UL //Access:RW   DataWidth:0x8    // cdfe eye delay count overwrite value for CLK270.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X259_K2_E5                                                            0x001c0cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8_K2_E5                          (0x1<<0) // cdfe eye delay count overwrite value for CLK270.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8_K2_E5_SHIFT                    0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X259_AHB_CDFE_DLEV_OV_EN_K2_E5                                      (0x1<<1) // cdfe dlev overwrite enable.  1: enable dlev overwrite for cdfe.  0: disable dlev overwrite for cdfe.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X259_AHB_CDFE_DLEV_OV_EN_K2_E5_SHIFT                                1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X259_CDFE_DLEV_ADAPT_CMP_SEL_OVR_O_4_0_K2_E5                        (0x1f<<2) // Register override for overriding adaptation comparator select bit [0] : override enable bit [4:1] : override value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X259_CDFE_DLEV_ADAPT_CMP_SEL_OVR_O_4_0_K2_E5_SHIFT                  2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_K2_E5                   (0x1<<7) // Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_K2_E5_SHIFT             7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X260_K2_E5                                                            0x001c10UL //Access:RW   DataWidth:0x8    // Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X261_K2_E5                                                            0x001c14UL //Access:RW   DataWidth:0x8    // cdfe dlevn overwrite value.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X262_K2_E5                                                            0x001c18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X262_AHB_CDFE_TAP_OV_EN_K2_E5                                       (0x1f<<0) // cdfe tap1~5 overwrite enable.                                                                                                    Bit[0]: enable tap1 overwrite for cdfe. Bit[1]: enable tap2 overwrite for cdfe Bit[2]: enable tap3 overwrite for cdfe.  Bit[3]: enable tap4 overwrite for cdfe. Bit[4]: enable tap5 overwrite for cdfe.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X262_AHB_CDFE_TAP_OV_EN_K2_E5_SHIFT                                 0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X263_K2_E5                                                            0x001c1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X263_AHB_CDFE_TAP1_OV_K2_E5                                         (0x7f<<0) // cdfe tap1 overwrite value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X263_AHB_CDFE_TAP1_OV_K2_E5_SHIFT                                   0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X264_K2_E5                                                            0x001c20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X264_AHB_CDFE_TAP2_OV_K2_E5                                         (0x3f<<0) // cdfe tap2 overwrite value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X264_AHB_CDFE_TAP2_OV_K2_E5_SHIFT                                   0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X265_K2_E5                                                            0x001c24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X265_AHB_CDFE_TAP3_OV_K2_E5                                         (0x3f<<0) // cdfe tap3 overwrite value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X265_AHB_CDFE_TAP3_OV_K2_E5_SHIFT                                   0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X266_K2_E5                                                            0x001c28UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X266_AHB_CDFE_TAP4_OV_K2_E5                                         (0x3f<<0) // cdfe tap4 overwrite value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X266_AHB_CDFE_TAP4_OV_K2_E5_SHIFT                                   0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X267_K2_E5                                                            0x001c2cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X267_AHB_CDFE_TAP5_OV_K2_E5                                         (0x3f<<0) // cdfe tap5 overwrite value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X267_AHB_CDFE_TAP5_OV_K2_E5_SHIFT                                   0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_K2_E5                   (0x1<<7) // Enables FW enable control for TAP adapt using DLEV
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_K2_E5_SHIFT             7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_K2_E5                                                            0x001c30UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O_K2_E5                           (0x1<<0) // Instucts to start TAP adapt using DLEV in FW enabled mode
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O_K2_E5_SHIFT                     0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_K2_E5                 (0x1<<1) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_K2_E5_SHIFT           1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O_K2_E5             (0x1<<2) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O_K2_E5_SHIFT       2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_K2_E5                                (0x1<<7) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X269_K2_E5                                                            0x001c34UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O_K2_E5                         (0x1<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O_K2_E5_SHIFT                   0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X269_AHB_CDFE_STROBE_EN_O_K2_E5                                     (0x1<<1) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X269_AHB_CDFE_STROBE_EN_O_K2_E5_SHIFT                               1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X269_AHB_CDFE_CMP_ENA_O_K2_E5                                       (0xf<<2) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X269_AHB_CDFE_CMP_ENA_O_K2_E5_SHIFT                                 2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X270_K2_E5                                                            0x001c38UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X271_K2_E5                                                            0x001c3cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X271_AHB_CDFE_DIV_SIGN_BIT_O_4_0_K2_E5                              (0x1f<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X271_AHB_CDFE_DIV_SIGN_BIT_O_4_0_K2_E5_SHIFT                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O_K2_E5                      (0x1<<5) // Forces the positive dlev training pattern to be used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O_K2_E5_SHIFT                5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O_K2_E5                      (0x1<<6) // Forces the negative dlev training pattern to be used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O_K2_E5_SHIFT                6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X272_K2_E5                                                            0x001c40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X272_CDFE_TAP1_SCALE_O_2_0_K2_E5                                    (0x7<<0) // Scale factor CDFE TAP1 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X272_CDFE_TAP1_SCALE_O_2_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X272_CDFE_TAP1_SHIFT_O_4_0_K2_E5                                    (0x1f<<3) // Shift factor CDFE TAP1 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X272_CDFE_TAP1_SHIFT_O_4_0_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X273_K2_E5                                                            0x001c44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X273_CDFE_TAP2_SCALE_O_2_0_K2_E5                                    (0x7<<0) // Scale factor CDFE TAP2 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X273_CDFE_TAP2_SCALE_O_2_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X273_CDFE_TAP2_SHIFT_O_4_0_K2_E5                                    (0x1f<<3) // Shift factor CDFE TAP2 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X273_CDFE_TAP2_SHIFT_O_4_0_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X274_K2_E5                                                            0x001c48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X274_CDFE_TAP3_SCALE_O_2_0_K2_E5                                    (0x7<<0) // Scale factor CDFE TAP3 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X274_CDFE_TAP3_SCALE_O_2_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X274_CDFE_TAP3_SHIFT_O_4_0_K2_E5                                    (0x1f<<3) // Shift factor CDFE TAP3 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X274_CDFE_TAP3_SHIFT_O_4_0_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X275_K2_E5                                                            0x001c4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X275_CDFE_TAP4_SCALE_O_2_0_K2_E5                                    (0x7<<0) // Scale factor CDFE TAP4 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X275_CDFE_TAP4_SCALE_O_2_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X275_CDFE_TAP4_SHIFT_O_4_0_K2_E5                                    (0x1f<<3) // Shift factor CDFE TAP4 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X275_CDFE_TAP4_SHIFT_O_4_0_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X276_K2_E5                                                            0x001c50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X276_CDFE_TAP5_SCALE_O_2_0_K2_E5                                    (0x7<<0) // Scale factor CDFE TAP5 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X276_CDFE_TAP5_SCALE_O_2_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X276_CDFE_TAP5_SHIFT_O_4_0_K2_E5                                    (0x1f<<3) // Shift factor CDFE TAP5 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X276_CDFE_TAP5_SHIFT_O_4_0_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X277_K2_E5                                                            0x001c54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X277_LN_MSM_RESET_RA_OVR_O_K2_E5                                    (0x3<<0) // Bit 0:  Override enable for msm_reset_ra Bit 1: Override msm_reset_ra
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X277_LN_MSM_RESET_RA_OVR_O_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X277_LN_MSM_RESET_P2S_OVR_O_K2_E5                                   (0x3<<2) // Bit 0:  Override enable for msm_reset_p2s Bit 1: Override msm_reset_p2s
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X277_LN_MSM_RESET_P2S_OVR_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X277_LN_MSM_RESET_LNREGH_OVR_O_K2_E5                                (0x3<<4) // Bit 0:  Override enable for msm_reset_lnregh Bit 1: Override msm_reset_lnregh
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X277_LN_MSM_RESET_LNREGH_OVR_O_K2_E5_SHIFT                          4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X277_LN_MSM_RESET_LNREG_OVR_O_K2_E5                                 (0x3<<6) // Bit 0:  Override enable for msm_reset_lnreg Bit 1: Override msm_reset_lnreg
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X277_LN_MSM_RESET_LNREG_OVR_O_K2_E5_SHIFT                           6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X278_K2_E5                                                            0x001c58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X278_LN_MSM_RESET_CDR_OVR_O_K2_E5                                   (0x3<<0) // Bit 0:  Override enable for msm_reset_cdr Bit 1: Override msm_reset_cdr
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X278_LN_MSM_RESET_CDR_OVR_O_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X278_LN_MSM_RESET_DFE_OVR_O_K2_E5                                   (0x3<<2) // Bit 0:  Override enable for msm_reset_dfe Bit 1: Override msm_reset_dfe
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X278_LN_MSM_RESET_DFE_OVR_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X278_LN_MSM_PD_LNREGH_OVR_O_K2_E5                                   (0x3<<4) // Bit 0:  Override enable for msm_pd_lnregh Bit 1: Override msm_pd_lnregh
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X278_LN_MSM_PD_LNREGH_OVR_O_K2_E5_SHIFT                             4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X278_LN_MSM_PD_VCO_BUF_OVR_O_K2_E5                                  (0x3<<6) // Bit 0:  Override enable for msm_pd_vco_buf Bit 1: Override msm_pd_vco_buf
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X278_LN_MSM_PD_VCO_BUF_OVR_O_K2_E5_SHIFT                            6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X279_K2_E5                                                            0x001c5cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X279_LN_MSM_RESET_CDR_GCRX_OVR_O_K2_E5                              (0x3<<0) // Bit 0:  Override enable for msm_reset_cdr_gcrx Bit 1: Override msm_reset_cdr_gcrx
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X279_LN_MSM_RESET_CDR_GCRX_OVR_O_K2_E5_SHIFT                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X279_LN_MSM_RXGATE_EN_OVR_O_K2_E5                                   (0x3<<2) // Bit 0:  Override enable for msm_rxgate_en Bit 1: Override msm_rxgate_en
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X279_LN_MSM_RXGATE_EN_OVR_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X279_LN_MSM_RESET_VCO_OVR_O_K2_E5                                   (0x3<<4) // Bit 0:  Override enable for msm_reset_vco Bit 1: Override msm_reset_vco
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X279_LN_MSM_RESET_VCO_OVR_O_K2_E5_SHIFT                             4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X279_LN_MSM_IDDQ_SD_OVR_O_K2_E5                                     (0x3<<6) // Bit 0:  Override enable for msm_iddq_sd Bit 1: Override msm_iddq_sd
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X279_LN_MSM_IDDQ_SD_OVR_O_K2_E5_SHIFT                               6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X280_K2_E5                                                            0x001c60UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X280_LN_MSM_PD_DFE_OVR_O_K2_E5                                      (0x3<<0) // Bit 0:  Override enable for msm_pd_dfe Bit 1: Override msm_pd_dfe
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X280_LN_MSM_PD_DFE_OVR_O_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X280_LN_MSM_PD_DFE_BIAS_OVR_O_K2_E5                                 (0x3<<2) // Bit 0:  Override enable for msm_pd_dfe_bias Bit 1: Override msm_pd_dfe_bias
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X280_LN_MSM_PD_DFE_BIAS_OVR_O_K2_E5_SHIFT                           2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X280_LN_MSM_TXDRV_LP_IDLE_OVR_O_K2_E5                               (0x3<<4) // Bit 0:  Override enable for msm_txdrv_lp_idle Bit 1: Override msm_txdrv_lp_idle
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X280_LN_MSM_TXDRV_LP_IDLE_OVR_O_K2_E5_SHIFT                         4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X280_LN_MSM_TXREG_BLEED_ENA_OVR_O_K2_E5                             (0x3<<6) // Bit 0:  Override enable for msm_txreg_bleed_ena Bit 1: Override msm_txreg_bleed_ena
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X280_LN_MSM_TXREG_BLEED_ENA_OVR_O_K2_E5_SHIFT                       6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X281_K2_E5                                                            0x001c64UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X281_LN_MSM_PD_TXREG_OVR_O_K2_E5                                    (0x3<<0) // Bit 0:  Override enable for msm_pd_txreg Bit 1: Override msm_pd_txreg
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X281_LN_MSM_PD_TXREG_OVR_O_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X281_LN_MSM_PD_LNREG_OVR_O_K2_E5                                    (0x3<<2) // Bit 0:  Override enable for msm_pd_lnreg Bit 1: Override msm_pd_lnreg
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X281_LN_MSM_PD_LNREG_OVR_O_K2_E5_SHIFT                              2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X281_LN_MSM_PD_P2S_OVR_O_K2_E5                                      (0x3<<4) // Bit 0:  Override enable for pd_p2s Bit 1: Override pd_p2s
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X281_LN_MSM_PD_P2S_OVR_O_K2_E5_SHIFT                                4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X281_LN_MSM_PD_RA_OVR_O_K2_E5                                       (0x3<<6) // Bit 0:  Override enable for pd_ra Bit 1: Override pd_ra
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X281_LN_MSM_PD_RA_OVR_O_K2_E5_SHIFT                                 6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X282_K2_E5                                                            0x001c68UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X282_LN_MSM_PD_SLV_BIAS_OVR_O_K2_E5                                 (0x3<<2) // Bit 0:  Override enable for pd_slv_bias Bit 1: Override pd_slv_bias
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X282_LN_MSM_PD_SLV_BIAS_OVR_O_K2_E5_SHIFT                           2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X282_LN_MSM_PD_TXDRV_OVR_O_K2_E5                                    (0x3<<4) // Bit 0:  Override enable for pd_txdrv Bit 1: Override pd_txdrv
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X282_LN_MSM_PD_TXDRV_OVR_O_K2_E5_SHIFT                              4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X282_LN_MSM_PD_VCO_OVR_O_K2_E5                                      (0x3<<6) // Bit 0:  Override enable for msm_pd_vco Bit 1: Override msm_pd_vco
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X282_LN_MSM_PD_VCO_OVR_O_K2_E5_SHIFT                                6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X283_K2_E5                                                            0x001c6cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X283_LN_MSM_CDR_EN_OVR_O_K2_E5                                      (0x3<<0) // Bit 0:  Override enable for msm_cdr_en Bit 1: Override msm_cdr_en
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X283_LN_MSM_CDR_EN_OVR_O_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X283_LN_MSM_RESET_S2P_OVR_O_K2_E5                                   (0x3<<2) // Bit 0:  Override enable for msm_reset_s2p Bit 1: Override msm_reset_s2p
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X283_LN_MSM_RESET_S2P_OVR_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X283_LN_MSM_RXCLK_EN_OVR_O_K2_E5                                    (0x3<<4) // Bit 0:  Override enable for msm_rxclk_en Bit 1: Override msm_rxclk_en
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X283_LN_MSM_RXCLK_EN_OVR_O_K2_E5_SHIFT                              4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X283_LN_MSM_WORD_OVR_O_K2_E5                                        (0x3<<6) // Bit 0:  Override enable for msm_word Bit 1: Override msm_word
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X283_LN_MSM_WORD_OVR_O_K2_E5_SHIFT                                  6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X284_K2_E5                                                            0x001c70UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X284_LN_MSM_RATE_OVR_O_K2_E5                                        (0x7<<0) // Bit 0:  Override enable for msm_rate Bit [2:1] : Override msm_rate
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X284_LN_MSM_RATE_OVR_O_K2_E5_SHIFT                                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X284_LN_MSM_RXVCODIV_OVR_O_K2_E5                                    (0x7<<3) // Bit 0:  Override enable for msm_rxvcodiv Bit [2:1] : Override msm_rxvcodiv
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X284_LN_MSM_RXVCODIV_OVR_O_K2_E5_SHIFT                              3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X284_LN_MSM_RESET_TX_CLKDIV_OVR_O_K2_E5                             (0x3<<6) // Not currently used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X284_LN_MSM_RESET_TX_CLKDIV_OVR_O_K2_E5_SHIFT                       6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X285_K2_E5                                                            0x001c74UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X285_LN_MSM_TXVCODIV_OVR_O_K2_E5                                    (0x7<<0) // Bit 0:  Override enable for msm_txvcodiv Bit [2:1] : Override msm_txvcodiv
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X285_LN_MSM_TXVCODIV_OVR_O_K2_E5_SHIFT                              0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_K2_E5                                                            0x001cb4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_RX_SRC_O_K2_E5                                                 (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 - Output of mux is output from 8b/10b encoder.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_RX_SRC_O_K2_E5_SHIFT                                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_TREG0_POL_O_K2_E5                                              (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_TREG0_POL_O_K2_E5_SHIFT                                        1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_TREG0_BIT_O_K2_E5                                              (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_TREG0_BIT_O_K2_E5_SHIFT                                        2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_TREG0_WORD_O_K2_E5                                             (0x1<<3) // TReg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_TREG0_WORD_O_K2_E5_SHIFT                                       3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_DMUX_TXA_SEL_O_1_0_K2_E5                                       (0x3<<4) // Transmit mux A data input select.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_DMUX_TXA_SEL_O_1_0_K2_E5_SHIFT                                 4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_P2S_RBUF_AUTOFIX_O_K2_E5                                       (0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / underflows 1 - Ring buffer will reset upon detection of overflow/underflow
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_P2S_RBUF_AUTOFIX_O_K2_E5_SHIFT                                 6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_K2_E5                                                            0x001cb8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_TREG1_POL_O_K2_E5                                              (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_TREG1_POL_O_K2_E5_SHIFT                                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_TREG1_BIT_O_K2_E5                                              (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_TREG1_BIT_O_K2_E5_SHIFT                                        1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_TREG1_WORD_O_K2_E5                                             (0x1<<2) // TReg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_TREG1_WORD_O_K2_E5_SHIFT                                       2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_REG1_POL_O_K2_E5                                               (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_REG1_POL_O_K2_E5_SHIFT                                         3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_REG1_BIT_O_K2_E5                                               (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_REG1_BIT_O_K2_E5_SHIFT                                         4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_REG1_WORD_O_K2_E5                                              (0x1<<5) // Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_REG1_WORD_O_K2_E5_SHIFT                                        5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_REG0_POL_O_K2_E5                                               (0x1<<6) // Used as Reg0 polarity select
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_REG0_POL_O_K2_E5_SHIFT                                         6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_K2_E5                                                            0x001cbcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_REG0_BIT_O_K2_E5                                               (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_REG0_BIT_O_K2_E5_SHIFT                                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_REG0_WORD_O_K2_E5                                              (0x1<<1) // Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_REG0_WORD_O_K2_E5_SHIFT                                        1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_DMUX_TXB_SEL_O_2_0_K2_E5                                       (0x7<<2) // Transmit mux B data input select enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_DMUX_TXB_SEL_O_2_0_K2_E5_SHIFT                                 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_TX_CTRL_O_24_K2_E5                                             (0x1<<5) // Bit 24: txdrv_c2_in[3]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_TX_CTRL_O_24_K2_E5_SHIFT                                       5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_WIDTH_CHNG_EN_O_K2_E5                                          (0x1<<6) // Enable bit for width_chng module
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_WIDTH_CHNG_EN_O_K2_E5_SHIFT                                    6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_TXTERM_CAL_SEQ_EN_O_K2_E5                                      (0x1<<7) // Txterm calibration enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_TXTERM_CAL_SEQ_EN_O_K2_E5_SHIFT                                7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X304_K2_E5                                                            0x001cc0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X304_TXTERM_CAL_RSEL_K2_E5                                          (0x7<<0) // tx termination calibration comparator threshold select
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X304_TXTERM_CAL_RSEL_K2_E5_SHIFT                                    0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X304_AHB_LN_RXBIT_STRIP_O_K2_E5                                     (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2b00: no bit stripping 2b01: 2x bit stripping 2b10: reserved 2b11: 4x bit stripping
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X304_AHB_LN_RXBIT_STRIP_O_K2_E5_SHIFT                               3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X304_AHB_MAC_WIDTH_O_K2_E5                                          (0x3<<5) // Data width selector for PCS/MAC interface. 2b00: GigE or XAUI 2b01: GigE or XAUI 2b10: RXAUI 2b11: XFI
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X304_AHB_MAC_WIDTH_O_K2_E5_SHIFT                                    5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X305_K2_E5                                                            0x001cc4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X305_AHB_TXMAC_THRESHOLD_O_K2_E5                                    (0x3<<0) // An internal FIFO is included to handle the communication between the external 64-bit data and the internal 20-bit data. The reading operation will begin only when the difference between the write pointer and read pointer for this FIFO reaches ahb_txmac_threshold_o.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X305_AHB_TXMAC_THRESHOLD_O_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X305_AHB_LN_TXBIT_REPEAT_O_K2_E5                                    (0x3<<2) // Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to PCS 2b00: no bit stuffing nor stripping 2b01: 2x bit stuffing and stripping 2b10: reserved 2b11: 4x bit stuffing and stripping
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X305_AHB_LN_TXBIT_REPEAT_O_K2_E5_SHIFT                              2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X305_MODE_8B_O_1_0_K2_E5                                            (0x3<<4) // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data word 8 bits
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X305_MODE_8B_O_1_0_K2_E5_SHIFT                                      4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X305_ENC_EN_O_K2_E5                                                 (0x1<<6) // 8b/10b encoder enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X305_ENC_EN_O_K2_E5_SHIFT                                           6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X305_DEC_EN_O_K2_E5                                                 (0x1<<7) // 8b/10b decoder enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X305_DEC_EN_O_K2_E5_SHIFT                                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X306_K2_E5                                                            0x001cc8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X306_AHB_TX_CDAC_OVR_K2_E5                                          (0xf<<0) // TX termination calibration DAC override. Signal ahb_tx_term_en_cal_ovr must also be asserted to take effect.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X306_AHB_TX_CDAC_OVR_K2_E5_SHIFT                                    0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X306_LN_COMMON_SYNC_TXCLK_EN_O_K2_E5                                (0x1<<4) // Per lane common synchronous clock between PMA, PCS and SoC logic enable bit. 1: in NORM state, lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA or its divided down version and this clock can be used as a common synchronous clock between PMA, PCS and SoC logic. In other state, it is switched to cmu_ck_soc_o[1]. 0: lnX_ck_txb_o is swtiched to cmu_ck_soc_o[1].
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X306_LN_COMMON_SYNC_TXCLK_EN_O_K2_E5_SHIFT                          4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X307_K2_E5                                                            0x001cccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X307_LN_TO_CLK_TXB_WAIT_O_K2_E5                                     (0x1f<<0) // In per lane common synchronous clock mode, after the lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA. The lnX_ok_o will get asserted after lnX_to_clk_txb_wait_o lnX_ck_txb_o cycles.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X307_LN_TO_CLK_TXB_WAIT_O_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X307_PIPE_EN_O_K2_E5                                                (0x1<<5) // PIPE interface block enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X307_PIPE_EN_O_K2_E5_SHIFT                                          5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X307_SAPIS_EN_O_K2_E5                                               (0x1<<6) // SAPIS interface block enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X307_SAPIS_EN_O_K2_E5_SHIFT                                         6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X307_USB_MODE_K2_E5                                                 (0x1<<7) // Signal Detect USB mode enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X307_USB_MODE_K2_E5_SHIFT                                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_K2_E5                                                            0x001cd0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_BLOCK_ENC_CLR_ERR_O_K2_E5                                      (0x1<<1) // 128b/130b encoder clear error
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_BLOCK_ENC_CLR_ERR_O_K2_E5_SHIFT                                1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_BLOCK_DEC_EN_ERR_CHK_O_K2_E5                                   (0x1<<3) // 130b/128b error check enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_BLOCK_DEC_EN_ERR_CHK_O_K2_E5_SHIFT                             3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_BLOCK_DEC_CHK_OS_NMBR_O_2_0_K2_E5                              (0x7<<4) // 130b/128b: number of OS indicating end of data
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_BLOCK_DEC_CHK_OS_NMBR_O_2_0_K2_E5_SHIFT                        4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_BLOCK_DEC_CLR_ERR_O_K2_E5                                      (0x1<<7) // 130b/128b: clear error flag
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_BLOCK_DEC_CLR_ERR_O_K2_E5_SHIFT                                7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X309_K2_E5                                                            0x001cd4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X309_BLOCK_DEC_ERR_THRESHOLD_O_3_0_K2_E5                            (0xf<<0) // 130b/128b: number of sync hdr errors before asserting sync error flag
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X309_BLOCK_DEC_ERR_THRESHOLD_O_3_0_K2_E5_SHIFT                      0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X309_BLOCK_DEC_CHK_BLK_NMBR_O_3_0_K2_E5                             (0xf<<4) // 130b/128b: number of continuous blocks checked
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X309_BLOCK_DEC_CHK_BLK_NMBR_O_3_0_K2_E5_SHIFT                       4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_K2_E5                                                            0x001cd8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_EBUF_RSTN_O_K2_E5                                              (0x1<<0) // Synchronous clear for elastic buffer
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_EBUF_RSTN_O_K2_E5_SHIFT                                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_ALIGN_RSTN_O_K2_E5                                             (0x1<<1) // Synchronous clear for block/symbol aligner
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_ALIGN_RSTN_O_K2_E5_SHIFT                                       1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_EBUF_SKP_ADD_EN_O_K2_E5                                        (0x1<<2) // Elastic buffer SKP add enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_EBUF_SKP_ADD_EN_O_K2_E5_SHIFT                                  2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_RBUF_RSTN_O_K2_E5                                              (0x1<<3) // TX FIFO synchronous reset
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_RBUF_RSTN_O_K2_E5_SHIFT                                        3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_EN_SKPOS_ERR_O_K2_E5                                           (0x1<<5) // Enables skpos error status propagation in Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_EN_SKPOS_ERR_O_K2_E5_SHIFT                                     5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X311_K2_E5                                                            0x001cdcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X311_PIPE_LFREQ_K2_E5                                               (0x3f<<0) // LF value for full swing
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X311_PIPE_LFREQ_K2_E5_SHIFT                                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X311_DIS_BLOCK_ALIGN_CTRL_O_K2_E5                                   (0x1<<6) // Disables the primary input lnX_block_align_control
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X311_DIS_BLOCK_ALIGN_CTRL_O_K2_E5_SHIFT                             6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X311_DIS_EIEOS_CHK_IN_LB_O_K2_E5                                    (0x1<<7) // Disables the EIEOS check in loopback
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X311_DIS_EIEOS_CHK_IN_LB_O_K2_E5_SHIFT                              7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X312_K2_E5                                                            0x001ce0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X312_COEF_FE_LIMIT_EN_O_K2_E5                                       (0x1<<0) // FE TxEq Co-efficient Limiting Enable control
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X312_COEF_FE_LIMIT_EN_O_K2_E5_SHIFT                                 0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X312_RXVALID_DIS_AT_RATE_CHG_O_0_K2_E5                              (0x1<<1) // Value 1 forces rxvalid to be deasserted during rate change to gen 3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X312_RXVALID_DIS_AT_RATE_CHG_O_0_K2_E5_SHIFT                        1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X312_P2S_RBUF_BUF_THRESH_O_3_0_K2_E5                                (0xf<<2) // TX FIFO: specifies how far write pointer need to be ahead of read pointer before almost_full_o is asserted
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X312_P2S_RBUF_BUF_THRESH_O_3_0_K2_E5_SHIFT                          2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X313_K2_E5                                                            0x001ce4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X313_AHB_RX_GEARBOX_DISABLE_O_K2_E5                                 (0x1<<0) // 0: enable rx_gearbox, 1: disable rx_gearbox
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X313_AHB_RX_GEARBOX_DISABLE_O_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X313_AHB_TX_GEARBOX_DISABLE_O_K2_E5                                 (0x1<<1) // 0: enable tx_gearbox, 1: disable tx_gearbox
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X313_AHB_TX_GEARBOX_DISABLE_O_K2_E5_SHIFT                           1
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_K2_E5                                                            0x001ce8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_GEN1_OLD_RXDATA_SRC_K2_E5                                      (0x1<<0) // Mux select for data input to polbit_reg0  0:pma_ln_dfe_err_i , 1: pma_ln_rxdata_i
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_GEN1_OLD_RXDATA_SRC_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_SKIP_CDR_GEN3_O_K2_E5                                          (0x1<<1) // To skip cdr calibration routines for PCIe gen3.  Can be used when PHY is operating in gen1,2 only.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_SKIP_CDR_GEN3_O_K2_E5_SHIFT                                    1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_SKIP_CDR_GEN12_O_K2_E5                                         (0x1<<2) // To skip cdr calibration routines for PCIe gen1,2.  May not be needed in real scenario.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_SKIP_CDR_GEN12_O_K2_E5_SHIFT                                   2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_K2_E5                               (0x1<<3) // Receive amplifier powerdown override, when cisel is high
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_K2_E5_SHIFT                         3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_LN_P2S_RBUF_REALIGN_DIFF_O_K2_E5                               (0xf<<4) // In per lane common synchronous clock mode, ln_p2x_rbuf_realign_diff_o defines the starting difference between write pointer and read pointer when re aligning the pointer of TxFIFO.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_LN_P2S_RBUF_REALIGN_DIFF_O_K2_E5_SHIFT                         4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X315_K2_E5                                                            0x001cecUL //Access:RW   DataWidth:0x8    // Delays the beacon_ena propagation to PMA
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X316_K2_E5                                                            0x001cf0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X316_AHB_BEACON_DELAYED_COUNT_NUMBER_11_8_O_K2_E5                   (0xf<<0) // Delays the beacon_ena propagation to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X316_AHB_BEACON_DELAYED_COUNT_NUMBER_11_8_O_K2_E5_SHIFT             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_K2_E5                                                            0x001cf4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_AHB_BEACON_ENA_OVR_ENA_O_K2_E5                                 (0x1<<0) // Beacon Override Enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_AHB_BEACON_ENA_OVR_ENA_O_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_AHB_BEACON_ENA_OVR_O_K2_E5                                     (0x1<<1) // Beacon Override
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_AHB_BEACON_ENA_OVR_O_K2_E5_SHIFT                               1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_DEC_EN_OVR_O_K2_E5                                             (0x1<<2) // Enables 16b/20b decoder
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_DEC_EN_OVR_O_K2_E5_SHIFT                                       2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_ENC_EN_OVR_O_K2_E5                                             (0x1<<3) // Enables 16b/20b encoder
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_ENC_EN_OVR_O_K2_E5_SHIFT                                       3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_REGP_OVR_3_0_K2_E5                                             (0xf<<4) // Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty  Bit[1]: Overide values for bit reverse  Bit[2]: Overide values for word reverse
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_REGP_OVR_3_0_K2_E5_SHIFT                                       4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X318_K2_E5                                                            0x001cf8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X318_SIGDET_OVR_O_1_0_K2_E5                                         (0x3<<0) // Bit[0]: Overide value. Bit[1] :Override enable for signal detect output
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X318_SIGDET_OVR_O_1_0_K2_E5_SHIFT                                   0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X318_LN_OUT_OVR_1_0_K2_E5                                           (0x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the override, while bit 0 is the override value.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X318_LN_OUT_OVR_1_0_K2_E5_SHIFT                                     2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X318_RXEQ_SIGDET_1_0_K2_E5                                          (0x3<<4) // Override enable for DFE signal detect indicator input. Bit 1 is overide enable , 0 is overide value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X318_RXEQ_SIGDET_1_0_K2_E5_SHIFT                                    4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X319_K2_E5                                                            0x001cfcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X319_TXDETECTRX_OVR_O_1_0_K2_E5                                     (0x3<<0) // Override signal for txdetectrx input - bit 1 is override enable, bit 0 is override value.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X319_TXDETECTRX_OVR_O_1_0_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X319_RXDET_STATUS_OVR_O_1_0_K2_E5                                   (0x3<<2) // Override signal for txdetectrx output - bit 1 is override enable, bit 0 is override value.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X319_RXDET_STATUS_OVR_O_1_0_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X319_LOCKED_OVR_O_1_0_K2_E5                                         (0x3<<4) // Override signal for symbol align locked output. Bit 1 is the override enable, and bit 0 is the override value.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X319_LOCKED_OVR_O_1_0_K2_E5_SHIFT                                   4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O_K2_E5                         (0x1<<6) // override enable for tx_lowpwr_idle_ena output to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O_K2_E5_SHIFT                   6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_K2_E5                             (0x1<<7) // override value for tx_lowpwr_idle_ena output to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_K2_E5_SHIFT                       7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X320_K2_E5                                                            0x001d00UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X321_K2_E5                                                            0x001d04UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X322_K2_E5                                                            0x001d08UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X323_K2_E5                                                            0x001d0cUL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X324_K2_E5                                                            0x001d10UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X325_K2_E5                                                            0x001d14UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_K2_E5                                                            0x001d18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_LN_IN_OVR_O_48_K2_E5                                           (0x1<<0) // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_LN_IN_OVR_O_48_K2_E5_SHIFT                                     0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_AHB_LN_IN_OVR_CHG_FLAG_O_K2_E5                                 (0x1<<1) // Flag to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1' before writing to the corresponding lnX_in_ovr_o_14_1 and set it back to '0' after the write. It is not needed for configuration writes.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_AHB_LN_IN_OVR_CHG_FLAG_O_K2_E5_SHIFT                           1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_REGP1_OVR_O_3_0_K2_E5                                          (0xf<<2) // Overrides for polbit block polbit_regp1 Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty  Bit[1]: Overide values for bit reverse  Bit[2]: Overide values for word reverse
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_REGP1_OVR_O_3_0_K2_E5_SHIFT                                    2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_OOB_DET_EN_K2_E5                                               (0x1<<6) // OOB detect enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_OOB_DET_EN_K2_E5_SHIFT                                         6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_LN_IN_OVR_O_49_K2_E5                                           (0x1<<7) // OOB detect enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_LN_IN_OVR_O_49_K2_E5_SHIFT                                     7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X327_K2_E5                                                            0x001d1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X327_CDR_CTRL_DLY_DLPF_EN_O_K2_E5                                   (0x1f<<0) // Delay between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0  R-platform requires 150ns delay
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X327_CDR_CTRL_DLY_DLPF_EN_O_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X330_K2_E5                                                            0x001d28UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X330_MSM_LN_RATE_EXTRA_BITS_OVR_O_2_0_K2_E5                         (0x7<<0) // Override signals for lane: msm_ln_rate_ow[4:2]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X330_MSM_LN_RATE_EXTRA_BITS_OVR_O_2_0_K2_E5_SHIFT                   0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X330_LN_IN_OVR_O_50_K2_E5                                           (0x1<<3) // Override signals for lane: msm_ln_rate_ow[4:2]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X330_LN_IN_OVR_O_50_K2_E5_SHIFT                                     3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X0_K2_E5                                                              0x002000UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O_K2_E5                                 (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X1_K2_E5                                                              0x002004UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O_K2_E5                                 (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O_K2_E5_SHIFT                           3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O_K2_E5                                 (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X2_K2_E5                                                              0x002008UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O_K2_E5                                 (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X3_K2_E5                                                              0x00200cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X3_PMA_CMU_SEL_O_0_K2_E5                                            (0x1<<0) // CMU Select for lane  0 -	 Select CMU0  1 -	 Select CMU1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X3_PMA_CMU_SEL_O_0_K2_E5_SHIFT                                      0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X3_PMA_TXCLK_SEL_O_1_K2_E5                                          (0x1<<1) // PMA TX Clock Select for TX CDR VCO  0 -	 CMU0 Clock  1 -	 CMU1 Clock
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X3_PMA_TXCLK_SEL_O_1_K2_E5_SHIFT                                    1
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X4_K2_E5                                                              0x002010UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X4_CDRCTRL_DIV_EN_O_1_0_K2_E5                                       (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Divide by 4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X4_CDRCTRL_DIV_EN_O_1_0_K2_E5_SHIFT                                 0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X4_GCFSM_DIV_EN_O_1_0_K2_E5                                         (0x3<<2) // Static divider control for Lane GCFSM clock The only access to this divider. Not an override 4d0:  No division  4d1:  /2 4d2:  /2 4d3:  /4:
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X4_GCFSM_DIV_EN_O_1_0_K2_E5_SHIFT                                   2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X4_LN_CLK_TXB_DIV24OR1_O_K2_E5                                      (0x3<<4) // Divide ratio setting for lnX_ck_txb_o. When ln_common_sync_txclk_en_o is high and in NORM state:                                            2'b00: lnX_ck_txb_o is divided by 1 version of the tx byte clock from PMA.                     2'b01/2'b10: lnX_ck_txb_o is divided by 2 version of the tx byte clock from PMA.                  2'b11: lnX_ck_txb_o is divided by 4 version of the tx byte clock from PMA.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X4_LN_CLK_TXB_DIV24OR1_O_K2_E5_SHIFT                                4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X4_AHB_CHNG_REQ_Z_O_K2_E5                                           (0x1<<6) // Not currently used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X4_AHB_CHNG_REQ_Z_O_K2_E5_SHIFT                                     6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X5_K2_E5                                                              0x002014UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X5_REF_CLK_DIV_EN_O_1_0_K2_E5                                       (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X5_REF_CLK_DIV_EN_O_1_0_K2_E5_SHIFT                                 0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X5_OOB_CLK_DIV_EN_O_1_0_K2_E5                                       (0x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X5_OOB_CLK_DIV_EN_O_1_0_K2_E5_SHIFT                                 2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_K2_E5                                                              0x00201cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_RATE_O_K2_E5                                                (0x3<<0) // Rate control for BIST
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_RATE_O_K2_E5_SHIFT                                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_MODE8B_O_K2_E5                                          (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Generated data word is 8 bits
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_MODE8B_O_K2_E5_SHIFT                                    2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_ERR_O_K2_E5                                             (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 - BIST generator outputs erroneous pattern.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_ERR_O_K2_E5_SHIFT                                       3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_TX_CLOCK_ENABLE_K2_E5                                       (0x1<<4) // Active HIGH clock enable signal for the BIST transmit clock
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_TX_CLOCK_ENABLE_K2_E5_SHIFT                                 4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_CDN_O_K2_E5                                             (0x1<<5) // Bist generator master reset.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_CDN_O_K2_E5_SHIFT                                       5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_WORD_O_K2_E5                                            (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 1 - Bist generator generates double word 16 or 20
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_WORD_O_K2_E5_SHIFT                                      6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_EN_O_K2_E5                                              (0x1<<7) // Bist generator enable.  0 - Bist generator idle. 1 - Bist generator generates data
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_EN_O_K2_E5_SHIFT                                        7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X8_K2_E5                                                              0x002020UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X8_BIST_GEN_CLK_SEL_O_2_0_K2_E5                                     (0x7<<0) // BIST Generation Clock Selection
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X8_BIST_GEN_CLK_SEL_O_2_0_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X8_BIST_GEN_SEND_PREAM_O_K2_E5                                      (0x1<<3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - Bist generator sends preamble.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X8_BIST_GEN_SEND_PREAM_O_K2_E5_SHIFT                                3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X8_BIST_GEN_INSERT_COUNT_O_2_0_K2_E5                                (0x7<<4) // Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is ever inserted into the stream. In 20-bit mode, the product of bist_gen_insert_length x bist_gen_insert_count must be even.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X8_BIST_GEN_INSERT_COUNT_O_2_0_K2_E5_SHIFT                          4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X9_K2_E5                                                              0x002024UL //Access:RW   DataWidth:0x8    // Bist generator low-period control. If not 0, output data enable will be low for this number of words, and then high for en_high_i_X:0 number of words, repeating. If 0, data output enable will be asserted for entire test.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X10_K2_E5                                                             0x002028UL //Access:RW   DataWidth:0x8    // Bist generator low-period control. If not 0, output data enable will be low for this number of words, and then high for en_high_i_X:0 number of words, repeating. If 0, data output enable will be asserted for entire test.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X11_K2_E5                                                             0x00202cUL //Access:RW   DataWidth:0x8    // Bist generator high-period control. Refer to bist_gen_en_low_o and BIST documentation for further information.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X12_K2_E5                                                             0x002030UL //Access:RW   DataWidth:0x8    // Bist generator high-period control. Refer to bist_gen_en_low_o and BIST documentation for further information.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X13_K2_E5                                                             0x002034UL //Access:RW   DataWidth:0x8    // Bist generator - Number of words between insert word insertions. Insertions are done in both pream and data transmission. In 20-bit mode, this number must be even.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X14_K2_E5                                                             0x002038UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X14_BIST_GEN_INSERT_DELAY_O_11_8_K2_E5                              (0xf<<0) // Bist generator - Number of words between insert word insertions. Insertions are done in both pream and data transmission. In 20-bit mode, this number must be even.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X14_BIST_GEN_INSERT_DELAY_O_11_8_K2_E5_SHIFT                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X14_BCHK_EN_O_K2_E5                                                 (0x1<<5) // BIST checker enable Enables BIST RX Control block, which enables the actual BIST RX block when appropriate
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X14_BCHK_EN_O_K2_E5_SHIFT                                           5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X14_BCHK_CLR_O_K2_E5                                                (0x1<<6) // BIST checker clear signal. Zeroes error counter output. Does NOT go through the RX BIST control block
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X14_BCHK_CLR_O_K2_E5_SHIFT                                          6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_K2_E5                                                             0x00203cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_BCHK_SRC_O_1_0_K2_E5                                            (0x3<<0) // BIST checker source. 0 - BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Aligner before Elastic Buffer 2 - BIST uses output of RX loopback mux before Decoder and Polbits 3 - BIST uses output of reg1 flop bank before Interface blocks
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_BCHK_SRC_O_1_0_K2_E5_SHIFT                                      0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_BIST_CHK_DATA_MODE_O_K2_E5                                      (0x1<<3) // Bist checker mode select. 0X0  UDP pattern. 0x1  PRBS pattern
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_BIST_CHK_DATA_MODE_O_K2_E5_SHIFT                                3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_BIST_CHK_LFSR_LENGTH_O_1_0_K2_E5                                (0x3<<4) // BIST PRBS pattern selector.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_BIST_CHK_LFSR_LENGTH_O_1_0_K2_E5_SHIFT                          4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_BIST_RX_CLOCK_ENABLE_K2_E5                                      (0x1<<7) // Active HIGH clock enable signal for the BIST receive clock
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_BIST_RX_CLOCK_ENABLE_K2_E5_SHIFT                                7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X16_K2_E5                                                             0x002040UL //Access:RW   DataWidth:0x8    // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This word should correspond to the alignment character used for the symbol alignment block.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X17_K2_E5                                                             0x002044UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X17_BIST_CHK_PREAM0_O_9_8_K2_E5                                     (0x3<<0) // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This word should correspond to the alignment character used for the symbol alignment block.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X17_BIST_CHK_PREAM0_O_9_8_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X17_BIST_CHK_INSERT_LENGTH_O_2_0_K2_E5                              (0x7<<2) // BIST Checker Insert word length.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X17_BIST_CHK_INSERT_LENGTH_O_2_0_K2_E5_SHIFT                        2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X17_BIST_CHK_SYNC_ON_ZEROS_K2_E5                                    (0x1<<5) // Setting this bit allows BIST to sync to RX value of zero
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X17_BIST_CHK_SYNC_ON_ZEROS_K2_E5_SHIFT                              5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X18_K2_E5                                                             0x002048UL //Access:RW   DataWidth:0x8    // BIST Check Preamble
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X19_K2_E5                                                             0x00204cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X19_BIST_CHK_PREAM1_O_9_8_K2_E5                                     (0x3<<0) // BIST Check Preamble
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X19_BIST_CHK_PREAM1_O_9_8_K2_E5_SHIFT                               0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X20_K2_E5                                                             0x002050UL //Access:RW   DataWidth:0x8    // Bist checker 40-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corresponds to 5 8-bit words. K code is assumed to be 0 in 8-bit mode.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X21_K2_E5                                                             0x002054UL //Access:RW   DataWidth:0x8    // BIST Check User-defined pattern
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X22_K2_E5                                                             0x002058UL //Access:RW   DataWidth:0x8    // BIST Check User-defined pattern
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X23_K2_E5                                                             0x00205cUL //Access:RW   DataWidth:0x8    // BIST Check User-defined pattern
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X24_K2_E5                                                             0x002060UL //Access:RW   DataWidth:0x8    // BIST Check User-defined pattern
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X25_K2_E5                                                             0x002064UL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X26_K2_E5                                                             0x002068UL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X27_K2_E5                                                             0x00206cUL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X28_K2_E5                                                             0x002070UL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X29_K2_E5                                                             0x002074UL //Access:RW   DataWidth:0x8    // Bist checker insertion word.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X30_K2_E5                                                             0x002078UL //Access:R    DataWidth:0x8    // Bist errors detected
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X31_K2_E5                                                             0x00207cUL //Access:R    DataWidth:0x8    // Bist errors detected
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X32_K2_E5                                                             0x002080UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 7-0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X33_K2_E5                                                             0x002084UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 15-8
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X34_K2_E5                                                             0x002088UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 23-16
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X35_K2_E5                                                             0x00208cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 31-24
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X36_K2_E5                                                             0x002090UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 39-32
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X37_K2_E5                                                             0x002094UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 47-40
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X38_K2_E5                                                             0x002098UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 55-48
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X39_K2_E5                                                             0x00209cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 63-56
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X40_K2_E5                                                             0x0020a0UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 71-64
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X41_K2_E5                                                             0x0020a4UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 79-72
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X42_K2_E5                                                             0x0020a8UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 87-80
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X43_K2_E5                                                             0x0020acUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 95-88
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X44_K2_E5                                                             0x0020b0UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 103-96
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X45_K2_E5                                                             0x0020b4UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 111-104
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X46_K2_E5                                                             0x0020b8UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 119-112
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X47_K2_E5                                                             0x0020bcUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 127-120
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X48_K2_E5                                                             0x0020c0UL //Access:RW   DataWidth:0x8    // Timing Window length for GCFSM for Gen 1/2 - for the new ICA method
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X49_K2_E5                                                             0x0020c4UL //Access:RW   DataWidth:0x8    // Timing Window length for GCFSM for Gen 3 - for the new ICA method
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X50_K2_E5                                                             0x0020c8UL //Access:RW   DataWidth:0x8    // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA method
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X51_K2_E5                                                             0x0020ccUL //Access:RW   DataWidth:0x8    // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA method
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X52_K2_E5                                                             0x0020d0UL //Access:RW   DataWidth:0x8    // The start length of DFE offset calibration's first cycle is the value of this register multiplied by 4.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X53_K2_E5                                                             0x0020d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X53_GCFSM_DFE_OFFSET_CAL_START_LEN_O_4_0_K2_E5                      (0x1f<<0) // The start length of DFE offset calibration, except for the 1st cycle.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X53_GCFSM_DFE_OFFSET_CAL_START_LEN_O_4_0_K2_E5_SHIFT                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2_K2_E5                               (0x1<<5) // COMLANE or LANE CSR Select for GCFSM Cycle Length registers  0 -	 Select COMLANE registers  1 -	 Select LANE registers
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2_K2_E5_SHIFT                         5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X53_GCFSM_LANE_TW_METHOD_EN_K2_E5                                   (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X53_GCFSM_LANE_TW_METHOD_EN_K2_E5_SHIFT                             6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X53_GCFSM_LANE_PMA_LOAD_OVR_K2_E5                                   (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X53_GCFSM_LANE_PMA_LOAD_OVR_K2_E5_SHIFT                             7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X54_K2_E5                                                             0x0020d8UL //Access:RW   DataWidth:0x8    // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X55_K2_E5                                                             0x0020dcUL //Access:RW   DataWidth:0x8    // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X56_K2_E5                                                             0x0020e0UL //Access:RW   DataWidth:0x8    // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_K2_E5                                                             0x0020e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_OVR_O_27_24_K2_E5                                         (0xf<<0) // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_OVR_O_27_24_K2_E5_SHIFT                                   0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_LANE_OUT_OVR_EN_O_K2_E5                                   (0x1<<4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes data stored in gcfsm_lane_pma_data_ovr_o to override calibration values for the block selected by gcfsm_lane_pma_cal_ovr_o.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_LANE_OUT_OVR_EN_O_K2_E5_SHIFT                             4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_LANE_PMA_LATCH_OVR_O_K2_E5                                (0x1<<5) // GCFSM pma_latch_o override
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_LANE_PMA_LATCH_OVR_O_K2_E5_SHIFT                          5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_LANE_PMA_GO_OVR_O_K2_E5                                   (0x1<<6) // GCFSM pma_go_o override
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_LANE_PMA_GO_OVR_O_K2_E5_SHIFT                             6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_LANE_PMA_READ_OVR_O_K2_E5                                 (0x1<<7) // GCFSM pma_read_o override.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_LANE_PMA_READ_OVR_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X58_K2_E5                                                             0x0020e8UL //Access:RW   DataWidth:0x8    // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X59_K2_E5                                                             0x0020ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X59_GCFSM_LANE_PMA_DATA_OVR_O_11_8_K2_E5                            (0xf<<0) // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X59_GCFSM_LANE_PMA_DATA_OVR_O_11_8_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X60_K2_E5                                                             0x0020f0UL //Access:RW   DataWidth:0x8    // General Calibration Finite State Machine GCFSM overide select, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA compone
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X61_K2_E5                                                             0x0020f4UL //Access:RW   DataWidth:0x8    // General Calibration Finite State Machine GCFSM overide select, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA compone
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X62_K2_E5                                                             0x0020f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X62_LN_MSM_REQ_IN_OVR_O_K2_E5                                       (0x3<<0) // Bit 0:  Override enable for msm_ln_req Bit 1 : Override msm_ln_req
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X62_LN_MSM_REQ_IN_OVR_O_K2_E5_SHIFT                                 0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X62_LN_MSM_FUNC_IN_OVR_O_K2_E5                                      (0x3f<<2) // Bit 2:  Override enable for msm_func Bits [7:3] : Override msm_func
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X62_LN_MSM_FUNC_IN_OVR_O_K2_E5_SHIFT                                2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X65_K2_E5                                                             0x002104UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X65_GCFSM_OVR_O_28_K2_E5                                            (0x1<<0) // Not currently used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X65_GCFSM_OVR_O_28_K2_E5_SHIFT                                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X66_K2_E5                                                             0x002108UL //Access:RW   DataWidth:0x8    // Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X67_K2_E5                                                             0x00210cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X67_CDR_CTRL_DLY_CDR_O_6_0_K2_E5                                    (0x7f<<0) // Number of clock cycles between signal detect indicator
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X67_CDR_CTRL_DLY_CDR_O_6_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_K2_E5                               (0x1<<7) // Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_K2_E5_SHIFT                         7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X68_K2_E5                                                             0x002110UL //Access:RW   DataWidth:0x8    // Number of clock cycles between CISEL assertion
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X69_K2_E5                                                             0x002114UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X69_CDR_CTRL_DLY_LANE_O_9_8_K2_E5                                   (0x3<<0) // Number of clock cycles between CISEL assertion
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X69_CDR_CTRL_DLY_LANE_O_9_8_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X69_CDR_CTRL_START_LEN_O_3_0_K2_E5                                  (0xf<<2) // Number of clock cycles between when CDR control block
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X69_CDR_CTRL_START_LEN_O_3_0_K2_E5_SHIFT                            2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X69_CDR_CTRL_INT_FIL_O_1_0_K2_E5                                    (0x3<<6) // CDR control DLPF positioning control.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X69_CDR_CTRL_INT_FIL_O_1_0_K2_E5_SHIFT                              6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X70_K2_E5                                                             0x002118UL //Access:RW   DataWidth:0x8    // CDR control block cycle length When not in PCIe Gen3.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X71_K2_E5                                                             0x00211cUL //Access:RW   DataWidth:0x8    // CDR control block cycle length When in PCIe Gen3.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X72_K2_E5                                                             0x002120UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X72_CDR_CTRL_MAX_DIFF_O_4_0_K2_E5                                   (0x1f<<0) // Maximum difference from DLPF center point.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X72_CDR_CTRL_MAX_DIFF_O_4_0_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X72_CDR_CTRL_MIN_BOUNCE_O_2_0_K2_E5                                 (0x7<<5) // Maximum difference from DLPF center point.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X72_CDR_CTRL_MIN_BOUNCE_O_2_0_K2_E5_SHIFT                           5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_K2_E5                                                             0x002124UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_CDR_CTRL_TW_METHOD_EN_K2_E5                                     (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_CDR_CTRL_TW_METHOD_EN_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_CDR_CONTROL_ATT_CTRL_O_K2_E5                                    (0x1<<1) // ATT wait control. Upon detection of signal, DFE ATT calibration is enabled, without CISEL being asserted to the CDR.  0 - CDR control block will wait for ATT calibration before proceeding 1 - CDR control block will not wait for ATT calibration
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_CDR_CONTROL_ATT_CTRL_O_K2_E5_SHIFT                              1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_RXEQ_WAIT_EN_O_K2_E5                                            (0x1<<2) // CDR control block wait for DFE signal.  0 - Do not wait for DFE calibration before enabling rx data 1 - Wait for DFE calibration before enabling rx data
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_RXEQ_WAIT_EN_O_K2_E5_SHIFT                                      2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_CDR_CTRL_DLY_CDR_O_9_7_K2_E5                                    (0x7<<3) // Number of clock cycles between signal detect indicator
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_CDR_CTRL_DLY_CDR_O_9_7_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X74_K2_E5                                                             0x002128UL //Access:RW   DataWidth:0x8    // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X75_K2_E5                                                             0x00212cUL //Access:RW   DataWidth:0x8    // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X76_K2_E5                                                             0x002130UL //Access:RW   DataWidth:0x8    // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X77_K2_E5                                                             0x002134UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X77_CDR_CTRL_OUT_OVR_O_29_24_K2_E5                                  (0x3f<<0) // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X77_CDR_CTRL_OUT_OVR_O_29_24_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X77_CDR_CTRL_CAL_LOAD_OVR_K2_E5                                     (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X77_CDR_CTRL_CAL_LOAD_OVR_K2_E5_SHIFT                               6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X78_K2_E5                                                             0x002138UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X78_SYM_ALIGN_ALIGN_POS_O_5_0_K2_E5                                 (0x3f<<0) // Symbol aligner position override enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X78_SYM_ALIGN_ALIGN_POS_O_5_0_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X78_SYM_ALIGN_MODE_O_1_0_K2_E5                                      (0x3<<6) // Symbol aligner mode select.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X78_SYM_ALIGN_MODE_O_1_0_K2_E5_SHIFT                                6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X79_K2_E5                                                             0x00213cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X79_SYM_ALIGN_BYPASS_O_K2_E5                                        (0x1<<0) // Asserting this register will bypass the symbol aligner
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X79_SYM_ALIGN_BYPASS_O_K2_E5_SHIFT                                  0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X80_K2_E5                                                             0x002140UL //Access:RW   DataWidth:0x8    // Number of cycles to wait before forcing exit form EI
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_K2_E5                                                             0x002144UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_EXIT_TIMER_LEN_O_9_8_K2_E5                        (0x3<<0) // Number of cycles to wait before forcing exit form EI
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_EXIT_TIMER_LEN_O_9_8_K2_E5_SHIFT                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_CLR_ERR_O_K2_E5                                   (0x1<<2) // Clears the elec idle control error flag
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_CLR_ERR_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_EI_INFERRED_O_K2_E5                               (0x1<<3) // Override for ei_inferred signal
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_EI_INFERRED_O_K2_E5_SHIFT                         3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O_K2_E5                            (0x1<<4) // Override for ei_mask signal
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O_K2_E5_SHIFT                      4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O_K2_E5                             (0x1<<5) // Override for ei_exit_type signal
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O_K2_E5_SHIFT                       5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_OVR_O_K2_E5                                       (0x1<<6) // EI control override enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_OVR_O_K2_E5_SHIFT                                 6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X82_K2_E5                                                             0x002148UL //Access:RW   DataWidth:0x8    // Number of cycles to wait before entering back into EI
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X83_K2_E5                                                             0x00214cUL //Access:RW   DataWidth:0x8    // Electrical Idle Control signal detect glitch filter counter
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X84_K2_E5                                                             0x002150UL //Access:RW   DataWidth:0x8    // Electrical Idle Control signal detect low filter min value
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X85_K2_E5                                                             0x002154UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X85_ELECIDLE_CTRL_LOCK_TIMER_LEN_O_9_8_K2_E5                        (0x3<<0) // Number of cycles to wait before entering back into EI
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X85_ELECIDLE_CTRL_LOCK_TIMER_LEN_O_9_8_K2_E5_SHIFT                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X85_ELECIDLE_CTRL_TIMER_LEN_SEL_O_1_0_K2_E5                         (0x3<<2) // EI Exit time cycles = timer_len_sel[1:0]+1*exit_timer_len_i[9:0]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X85_ELECIDLE_CTRL_TIMER_LEN_SEL_O_1_0_K2_E5_SHIFT                   2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X85_LOOPBACK_EN_O_K2_E5                                             (0x1<<4) // Control signal to force decoder into loopback mode
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X85_LOOPBACK_EN_O_K2_E5_SHIFT                                       4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X86_K2_E5                                                             0x002158UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X86_FES_LB_ENA_O_K2_E5                                              (0x1<<0) // FES loopback enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X86_FES_LB_ENA_O_K2_E5_SHIFT                                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X86_NES_LB_ENA_O_K2_E5                                              (0x1<<1) // NES loopback enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X86_NES_LB_ENA_O_K2_E5_SHIFT                                        1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X86_RXCLK_LB_ENA_O_K2_E5                                            (0x1<<2) // HS recovered clock to transmit loopback enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X86_RXCLK_LB_ENA_O_K2_E5_SHIFT                                      2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X87_K2_E5                                                             0x00215cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X87_AHB_PMA_LN_RX_BOOST_OVR_O_K2_E5                                 (0x1<<0) // RX boost override enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X87_AHB_PMA_LN_RX_BOOST_OVR_O_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_O_K2_E5                            (0x7f<<1) // RX boost override setting. Thermometer coded.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_O_K2_E5_SHIFT                      1
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X88_K2_E5                                                             0x002160UL //Access:RW   DataWidth:0x8    // RX boost override setting. Thermometer coded.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X89_K2_E5                                                             0x002164UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X89_AHB_PMA_LN_SD_THSEL_DIV1_O_K2_E5                                (0x7<<0) // Signal detect threshold select for Full rate
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X89_AHB_PMA_LN_SD_THSEL_DIV1_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X89_AHB_PMA_LN_SD_THSEL_DIV2_O_K2_E5                                (0x7<<3) // Signal detect threshold select for div-by-2 rate
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X89_AHB_PMA_LN_SD_THSEL_DIV2_O_K2_E5_SHIFT                          3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X89_AHB_PMA_LN_RXUP_O_K2_E5                                         (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X89_AHB_PMA_LN_RXUP_O_K2_E5_SHIFT                                   6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_K2_E5                                (0x1<<7) // RX FL calibration clock DIV4 enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X90_K2_E5                                                             0x002168UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X90_AHB_PMA_LN_SD_THSEL_DIV4_O_K2_E5                                (0x7<<0) // Signal detect threshold select for div-by-4 rate
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X90_AHB_PMA_LN_SD_THSEL_DIV4_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X90_AHB_PMA_LN_AGC_THSEL_O_K2_E5                                    (0x7<<3) // AGC threshold select
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X90_AHB_PMA_LN_AGC_THSEL_O_K2_E5_SHIFT                              3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X90_AHB_PMA_LN_VREGH_O_K2_E5                                        (0x3<<6) // Regulator VREGH setting
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X90_AHB_PMA_LN_VREGH_O_K2_E5_SHIFT                                  6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X91_K2_E5                                                             0x00216cUL //Access:RW   DataWidth:0x8    // RX FL calibration LDHS
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X92_K2_E5                                                             0x002170UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X92_AHB_PMA_LN_RXFL_LDHS_9_8_O_K2_E5                                (0x3<<0) // RX FL calibration LDHS
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X92_AHB_PMA_LN_RXFL_LDHS_9_8_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X92_AHB_PMA_LN_RXVCO_BIAS_O_K2_E5                                   (0xf<<2) // CDR VCO bias setting.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X92_AHB_PMA_LN_RXVCO_BIAS_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O_K2_E5                                (0x1<<6) // DLPF DIV2 enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O_K2_E5_SHIFT                          6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_K2_E5                                 (0x1<<7) // CDR DivN clock divider enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X93_K2_E5                                                             0x002174UL //Access:RW   DataWidth:0x8    // AFE spare controls
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X94_K2_E5                                                             0x002178UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X94_AHB_PMA_LN_CDR_DVDR_O_K2_E5                                     (0x3f<<0) // CDR DivN clock division ratio.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X94_AHB_PMA_LN_CDR_DVDR_O_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X94_AHB_PMA_LN_VREG_O_K2_E5                                         (0x3<<6) // Regulator VREG setting
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X94_AHB_PMA_LN_VREG_O_K2_E5_SHIFT                                   6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X95_K2_E5                                                             0x00217cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X95_AHB_PMA_LN_BB_STEP_O_K2_E5                                      (0xf<<0) // CDR bb_step
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X95_AHB_PMA_LN_BB_STEP_O_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X95_AHB_PMA_LN_INT_STEP_O_K2_E5                                     (0x7<<4) // CDR int step
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X95_AHB_PMA_LN_INT_STEP_O_K2_E5_SHIFT                               4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X95_AHB_PMA_LN_RXDWN_O_K2_E5                                        (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X95_AHB_PMA_LN_RXDWN_O_K2_E5_SHIFT                                  7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X96_K2_E5                                                             0x002180UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X96_AHB_PMA_LN_RXVCOFR_O_K2_E5                                      (0x7<<0) // RXVCOFR override value Enabled by pma_ln_dr_rxvcofr_sel_o
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X96_AHB_PMA_LN_RXVCOFR_O_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X96_AHB_PMA_LN_RXVCOFR_SEL_O_K2_E5                                  (0x1<<3) // Override enable for RXVCOFR override vakue
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X96_AHB_PMA_LN_RXVCOFR_SEL_O_K2_E5_SHIFT                            3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X96_AHB_PMA_LN_RX_SELR_O_K2_E5                                      (0x7<<4) // CTLE R degeneration select
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X96_AHB_PMA_LN_RX_SELR_O_K2_E5_SHIFT                                4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X97_K2_E5                                                             0x002184UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X97_AHB_PMA_LN_RX_SELC_O_K2_E5                                      (0x7<<0) // CTLE C degeneration select
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X97_AHB_PMA_LN_RX_SELC_O_K2_E5_SHIFT                                0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X99_K2_E5                                                             0x00218cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X99_PMA_LN_DFE_BW_SCALE_K2_E5                                       (0x3<<4) // DFE Bandwidth Selection
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X99_PMA_LN_DFE_BW_SCALE_K2_E5_SHIFT                                 4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X99_PMA_LN_PHD_ENA_O_1_0_K2_E5                                      (0x3<<6) // CDR phase detector proportional path enable bit 0: enables D4/D3 data/edge samplers bit 1: enables D1/D2 data/edge samplers
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X99_PMA_LN_PHD_ENA_O_1_0_K2_E5_SHIFT                                6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X100_K2_E5                                                            0x002190UL //Access:RW   DataWidth:0x8    // On-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 3-9: Fine x-direction offset, note bit reversal
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_K2_E5                                                            0x002194UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_EYE_DLY_O_8_8_K2_E5                                     (0x1<<0) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 2-8: Fine x-direction offset, note bit reversal
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_EYE_DLY_O_8_8_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_EYE_SGN_RST_O_K2_E5                                     (0x1<<2) // Reset signal for eye alignment mechanism.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_EYE_SGN_RST_O_K2_E5_SHIFT                               2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_SD_BWSEL_K2_E5                                          (0x1<<3) // RX signal detector bandwidth select. 0: Nominal bandwidth 1: 10% higher bandwidth
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_SD_BWSEL_K2_E5_SHIFT                                    3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_EYE_ENA270_O_K2_E5                                      (0x1<<4) // In eye diagram generation mode, assertion overrides the ck_270 DFE clock "right" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_EYE_ENA270_O_K2_E5_SHIFT                                4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_EYE_ENA90_O_K2_E5                                       (0x1<<5) // In eye diagram generation mode, assertion overrides the ck_90 DFE clock "left" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_EYE_ENA90_O_K2_E5_SHIFT                                 5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X102_K2_E5                                                            0x002198UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X102_PMA_LN_DFE_BIAS_O_3_0_K2_E5                                    (0xf<<0) // DFE bias setting.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X102_PMA_LN_DFE_BIAS_O_3_0_K2_E5_SHIFT                              0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X103_K2_E5                                                            0x00219cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X103_PMA_LN_TX_SR_FASTCAP_O_3_0_K2_E5                               (0xf<<0) // TX driver capacitive slew rate control.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X103_PMA_LN_TX_SR_FASTCAP_O_3_0_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X103_PMA_LN_TXEQ_POLARITY_O_3_0_K2_E5                               (0xf<<4) // TX coefficient polarity enable. Set to "1" for negative polarity. bit 0: Cm bit 1: C0 bit 2: C1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X103_PMA_LN_TXEQ_POLARITY_O_3_0_K2_E5_SHIFT                         4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X104_K2_E5                                                            0x0021a0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X104_PMA_LN_TX_SR_DAC_O_3_0_K2_E5                                   (0xf<<0) // TX slew rate DAC bias current control
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X104_PMA_LN_TX_SR_DAC_O_3_0_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X104_PMA_LN_HSCLK_SEL_O_K2_E5                                       (0x1<<4) // CDR clock divider bypass enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X104_PMA_LN_HSCLK_SEL_O_K2_E5_SHIFT                                 4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X105_K2_E5                                                            0x0021a4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X105_PMA_LN_TX_VREG_LEV_O_4_0_K2_E5                                 (0x1f<<0) // TX driver regulator voltage setting.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X105_PMA_LN_TX_VREG_LEV_O_4_0_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X105_PMA_LN_TXDRV_BLEED_ENA_O_K2_E5                                 (0x1<<5) // TX bleed enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X105_PMA_LN_TXDRV_BLEED_ENA_O_K2_E5_SHIFT                           5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X106_K2_E5                                                            0x0021a8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X106_AHB_PMA_LN_RX_BOOST_OVR_GEN3_O_K2_E5                           (0x1<<0) // RX boost override enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X106_AHB_PMA_LN_RX_BOOST_OVR_GEN3_O_K2_E5_SHIFT                     0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X106_AHB_PMA_LN_RX_BOOSTOVR_GEN3_6_0_O_K2_E5                        (0x7f<<1) // RX boost override setting. Thermometer coded.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X106_AHB_PMA_LN_RX_BOOSTOVR_GEN3_6_0_O_K2_E5_SHIFT                  1
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X107_K2_E5                                                            0x0021acUL //Access:RW   DataWidth:0x8    // RX boost override setting. Thermometer coded.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X108_K2_E5                                                            0x0021b0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X108_AHB_PMA_LN_SD_THSEL_GEN3_O_K2_E5                               (0x7<<0) // Signal detect threshold select for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X108_AHB_PMA_LN_SD_THSEL_GEN3_O_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X108_AHB_PMA_LN_AGC_THSEL_GEN3_O_K2_E5                              (0x7<<3) // AGC threshold select for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X108_AHB_PMA_LN_AGC_THSEL_GEN3_O_K2_E5_SHIFT                        3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X108_AHB_PMA_LN_RXUP_GEN3_O_K2_E5                                   (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X108_AHB_PMA_LN_RXUP_GEN3_O_K2_E5_SHIFT                             6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O_K2_E5                          (0x1<<7) // CDR VCO frequency lock counter divide by 4 enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O_K2_E5_SHIFT                    7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X109_K2_E5                                                            0x0021b4UL //Access:RW   DataWidth:0x8    // RX FL calibration LDHS for Gen3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X110_K2_E5                                                            0x0021b8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X110_AHB_PMA_LN_RXFL_LDHS_GEN3_9_8_O_K2_E5                          (0x3<<0) // RX FL calibration LDHS for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X110_AHB_PMA_LN_RXFL_LDHS_GEN3_9_8_O_K2_E5_SHIFT                    0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X110_AHB_PMA_LN_RXVCO_BIAS_GEN3_O_K2_E5                             (0xf<<2) // CDR VCO bias setting.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X110_AHB_PMA_LN_RXVCO_BIAS_GEN3_O_K2_E5_SHIFT                       2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X110_AHB_PMA_LN_DLPF_DIV2_ENA_GEN3_O_K2_E5                          (0x1<<6) // DLPF DIV2 enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X110_AHB_PMA_LN_DLPF_DIV2_ENA_GEN3_O_K2_E5_SHIFT                    6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O_K2_E5                           (0x1<<7) // CDR DivN clock divider enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O_K2_E5_SHIFT                     7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X111_K2_E5                                                            0x0021bcUL //Access:RW   DataWidth:0x8    // AFE spare controls for Gen3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X112_K2_E5                                                            0x0021c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X112_AHB_PMA_LN_CDR_DVDR_GEN3_O_K2_E5                               (0x3f<<0) // CDR DivN clock divider ratio..
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X112_AHB_PMA_LN_CDR_DVDR_GEN3_O_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X112_AHB_PMA_LN_VREG_GEN3_O_K2_E5                                   (0x3<<6) // Regulator VREG setting for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X112_AHB_PMA_LN_VREG_GEN3_O_K2_E5_SHIFT                             6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X113_K2_E5                                                            0x0021c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X113_AHB_PMA_LN_BB_STEP_GEN3_O_K2_E5                                (0xf<<0) // CDR bb_step for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X113_AHB_PMA_LN_BB_STEP_GEN3_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X113_AHB_PMA_LN_INT_STEP_GEN3_O_K2_E5                               (0x7<<4) // CDR int step for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X113_AHB_PMA_LN_INT_STEP_GEN3_O_K2_E5_SHIFT                         4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X113_AHB_PMA_LN_RXDWN_GEN3_O_K2_E5                                  (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X113_AHB_PMA_LN_RXDWN_GEN3_O_K2_E5_SHIFT                            7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X114_K2_E5                                                            0x0021c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X114_AHB_PMA_LN_RXVCOFR_GEN3_O_K2_E5                                (0x7<<0) // RXVCOFR override value for Gen3 Enabled by pma_ln_dr_rxvcofr_sel_o
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X114_AHB_PMA_LN_RXVCOFR_GEN3_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X114_AHB_PMA_LN_RX_SELR_GEN3_O_K2_E5                                (0x7<<3) // CTLE R degeneration select for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X114_AHB_PMA_LN_RX_SELR_GEN3_O_K2_E5_SHIFT                          3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X114_AHB_PMA_LN_VREGH_GEN3_O_K2_E5                                  (0x3<<6) // Not currently used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X114_AHB_PMA_LN_VREGH_GEN3_O_K2_E5_SHIFT                            6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X115_K2_E5                                                            0x0021ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X115_AHB_PMA_LN_RX_SELC_GEN3_O_K2_E5                                (0x7<<0) // CTLE R degeneration select for Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X115_AHB_PMA_LN_RX_SELC_GEN3_O_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X119_K2_E5                                                            0x0021dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X119_AHB_TX_CXP_MARGIN_K2_E5                                        (0xf<<0) // Value to minus/add from the calibrated txterm value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X119_AHB_TX_CXP_MARGIN_K2_E5_SHIFT                                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X119_AHB_TX_CXN_MARGIN_K2_E5                                        (0xf<<4) // Value to minus/add from the calibrated txterm value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X119_AHB_TX_CXN_MARGIN_K2_E5_SHIFT                                  4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X120_K2_E5                                                            0x0021e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X120_AHB_TX_TC_WAIT_NEXT_CMP_K2_E5                                  (0xf<<0) // in txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator  the register ix X2 is the actual number of wait cycle
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X120_AHB_TX_TC_WAIT_NEXT_CMP_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X120_AHB_TX_TC_WAIT_NEXT_SAMPLE_K2_E5                               (0x7<<4) // in txterm calibration, the number refclk cycles to wait before sampling the up from the same comparator
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X120_AHB_TX_TC_WAIT_NEXT_SAMPLE_K2_E5_SHIFT                         4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_K2_E5                                                            0x0021e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_TC_CMP_OUT_NUM_SAMPLES_K2_E5                            (0xf<<0) // in txterm calibration, the number of samples to take from the same comparator
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_TC_CMP_OUT_NUM_SAMPLES_K2_E5_SHIFT                      0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_CXP_MARGIN_ADD_0_K2_E5                                  (0x1<<4) // when 1, the final tx term value is calibrated txterm value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_CXP_MARGIN_ADD_0_K2_E5_SHIFT                            4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_CXN_MARGIN_ADD_0_K2_E5                                  (0x1<<5) // when 1, the final tx term value is calibrated txterm value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_CXN_MARGIN_ADD_0_K2_E5_SHIFT                            5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_CX_OVR_ENA_K2_E5                                        (0x1<<6) // enable override calibrated txterm value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_CX_OVR_ENA_K2_E5_SHIFT                                  6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_TERM_EN_CAL_OVR_K2_E5                                   (0x1<<7) // Debug feature, when set forces circuit to be affected by ahb_tx_cdac_ovr
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_TERM_EN_CAL_OVR_K2_E5_SHIFT                             7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X122_K2_E5                                                            0x0021e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X122_AHB_TX_CXP_OVR_K2_E5                                           (0xf<<0) // override calibrated txterm value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X122_AHB_TX_CXP_OVR_K2_E5_SHIFT                                     0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X122_AHB_TX_CXN_OVR_K2_E5                                           (0xf<<4) // override calibrated txterm value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X122_AHB_TX_CXN_OVR_K2_E5_SHIFT                                     4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X123_K2_E5                                                            0x0021ecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X123_TX_CTRL_O_0_K2_E5                                              (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not currently used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X123_TX_CTRL_O_0_K2_E5_SHIFT                                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X123_TX_CTRL_O_7_2_K2_E5                                            (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_slew_sld[1:0]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X123_TX_CTRL_O_7_2_K2_E5_SHIFT                                      2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X124_K2_E5                                                            0x0021f0UL //Access:RW   DataWidth:0x8    // Bits 12:8: txdrv_c1_in[4:0] Bits 15:13: txdrv_c2_in[2:0]
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X125_K2_E5                                                            0x0021f4UL //Access:RW   DataWidth:0x8    // Bits 19-16: txdrv_cm_in[3:0]  Bits 22-20: tx_slew_sld3f[2:0] Bit 23: txdrv_preem_1lsb_mode
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_K2_E5                                                            0x0021f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_EN_O_K2_E5                                                (0x1<<0) // DFE block enable signal.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_EN_O_K2_E5_SHIFT                                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_RATE_OW_O_2_0_K2_E5                                    (0x7<<1) // These bits have similar functionality as rxeq_rate_ow_o_2_0 bits in COMLANE CSR. These are used mainly in COMBINATION modes of operation. They are logically OR'ed with the bits in COMLANE.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_RATE_OW_O_2_0_K2_E5_SHIFT                              1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_RATE1_CAL_EN_O_3_K2_E5                                 (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_RATE1_CAL_EN_O_3_K2_E5_SHIFT                           4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_RATE2_CAL_EN_O_4_K2_E5                                 (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_RATE2_CAL_EN_O_4_K2_E5_SHIFT                           5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_RATE3_CAL_EN_O_5_K2_E5                                 (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_RATE3_CAL_EN_O_5_K2_E5_SHIFT                           6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_FORCE_CAL_O_6_K2_E5                                    (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_FORCE_CAL_O_6_K2_E5_SHIFT                              7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X127_K2_E5                                                            0x0021fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X127_RXEQ_CONT_CAL_O_6_0_K2_E5                                      (0x7f<<0) // 0 : enables att calibration 1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6: enables tap5 dfe calibration This register Is not bit reversed
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X127_RXEQ_CONT_CAL_O_6_0_K2_E5_SHIFT                                0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X128_K2_E5                                                            0x002200UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X128_RXEQ_INIT_CAL_O_6_0_K2_E5                                      (0x7f<<0) // 0 : enables att calibration 1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6: enables tap5 dfe calibration This register Is not bit reversed
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X128_RXEQ_INIT_CAL_O_6_0_K2_E5_SHIFT                                0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X130_K2_E5                                                            0x002208UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X130_RXEQ_RATE1_ATT_START_O_3_0_K2_E5                               (0xf<<0) // ATT start value for rate1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X130_RXEQ_RATE1_ATT_START_O_3_0_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X130_RXEQ_RATE1_BOOST_START_O_3_0_K2_E5                             (0xf<<4) // Boost start value for rate1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X130_RXEQ_RATE1_BOOST_START_O_3_0_K2_E5_SHIFT                       4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X131_K2_E5                                                            0x00220cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X131_RXEQ_RATE2_ATT_START_O_3_0_K2_E5                               (0xf<<0) // ATT start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X131_RXEQ_RATE2_ATT_START_O_3_0_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X131_RXEQ_RATE2_BOOST_START_O_3_0_K2_E5                             (0xf<<4) // Boost start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X131_RXEQ_RATE2_BOOST_START_O_3_0_K2_E5_SHIFT                       4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X132_K2_E5                                                            0x002210UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X132_RXEQ_RATE2_TAP1_START_O_6_0_K2_E5                              (0x7f<<0) // DFE Tap1 start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X132_RXEQ_RATE2_TAP1_START_O_6_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X133_K2_E5                                                            0x002214UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X133_RXEQ_RATE2_TAP2_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap2 start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X133_RXEQ_RATE2_TAP2_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X134_K2_E5                                                            0x002218UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X134_RXEQ_RATE2_TAP3_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap3 start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X134_RXEQ_RATE2_TAP3_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X135_K2_E5                                                            0x00221cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X135_RXEQ_RATE2_TAP4_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap4 start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X135_RXEQ_RATE2_TAP4_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X136_K2_E5                                                            0x002220UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X136_RXEQ_RATE2_TAP5_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap5 start value for rate2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X136_RXEQ_RATE2_TAP5_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X137_K2_E5                                                            0x002224UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X137_RXEQ_RATE3_ATT_START_O_3_0_K2_E5                               (0xf<<0) // ATT start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X137_RXEQ_RATE3_ATT_START_O_3_0_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X137_RXEQ_RATE3_BOOST_START_O_3_0_K2_E5                             (0xf<<4) // Boost start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X137_RXEQ_RATE3_BOOST_START_O_3_0_K2_E5_SHIFT                       4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X138_K2_E5                                                            0x002228UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X138_RXEQ_RATE3_TAP1_START_O_6_0_K2_E5                              (0x7f<<0) // DFE Tap1 start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X138_RXEQ_RATE3_TAP1_START_O_6_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X139_K2_E5                                                            0x00222cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X139_RXEQ_RATE3_TAP2_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap2 start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X139_RXEQ_RATE3_TAP2_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X140_K2_E5                                                            0x002230UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X140_RXEQ_RATE3_TAP3_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap3 start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X140_RXEQ_RATE3_TAP3_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X141_K2_E5                                                            0x002234UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X141_RXEQ_RATE3_TAP4_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap4 start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X141_RXEQ_RATE3_TAP4_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X142_K2_E5                                                            0x002238UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X142_RXEQ_RATE3_TAP5_START_O_5_0_K2_E5                              (0x3f<<0) // DFE Tap5 start value for rate3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X142_RXEQ_RATE3_TAP5_START_O_5_0_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X143_K2_E5                                                            0x00223cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X143_RXEQ_SUPERBST_AUTOCAL_DIS_K2_E5                                (0x1<<0) // Disable auto cal w/ rx_superbst
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X143_RXEQ_SUPERBST_AUTOCAL_DIS_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X143_BOOST_MAX_LIMIT_O_K2_E5                                        (0xf<<1) // Max limit value for BOOST auto-calibration
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X143_BOOST_MAX_LIMIT_O_K2_E5_SHIFT                                  1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X143_BOOST_MAX_LIMIT_EN_O_K2_E5                                     (0x1<<5) // Enable Max limiting for BOOST auto-calibration
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X143_BOOST_MAX_LIMIT_EN_O_K2_E5_SHIFT                               5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X143_RX_ATT_BOOST_CAL_O_1_0_K2_E5                                   (0x3<<6) // rx_att_boost setting used during ATT calibration
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X143_RX_ATT_BOOST_CAL_O_1_0_K2_E5_SHIFT                             6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X144_K2_E5                                                            0x002240UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X144_RX_ATT_BOOST_NORM_O_1_0_K2_E5                                  (0x3<<0) // rx_att_boost setting used after ATT calibration
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X144_RX_ATT_BOOST_NORM_O_1_0_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X144_RXEQ_BOOST_ADJ_EN_O_K2_E5                                      (0x1<<2) // boost_adj_en
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X144_RXEQ_BOOST_ADJ_EN_O_K2_E5_SHIFT                                2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X144_RXEQ_BOOST_ADJ_DIR_O_K2_E5                                     (0x1<<3) // boost_adj_dir
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X144_RXEQ_BOOST_ADJ_DIR_O_K2_E5_SHIFT                               3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X144_RXEQ_BOOST_ADJ_VAL_O_K2_E5                                     (0xf<<4) // boost_adj_val This register Is not bit reversed
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X144_RXEQ_BOOST_ADJ_VAL_O_K2_E5_SHIFT                               4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X145_K2_E5                                                            0x002244UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X145_CMP_OFFSET_AVG_MAX_NUMSAMPLES_6_0_K2_E5                        (0x7f<<0) // Max number of samples to be used for CMP Offset Noise Averaging
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X145_CMP_OFFSET_AVG_MAX_NUMSAMPLES_6_0_K2_E5_SHIFT                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X145_CMP_OFFSET_AVG_EN_O_K2_E5                                      (0x1<<7) // CMP Offset Noise Averaging Enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X145_CMP_OFFSET_AVG_EN_O_K2_E5_SHIFT                                7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X146_K2_E5                                                            0x002248UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X147_K2_E5                                                            0x00224cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X147_RXEQ_DFE_TAP_PD_WAIT_11_8_K2_E5                                (0xf<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X147_RXEQ_DFE_TAP_PD_WAIT_11_8_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X147_PMA_LN_DFE_OFS_CAL_ENA_K2_E5                                   (0x3<<4) // DFE offset calibration enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X147_PMA_LN_DFE_OFS_CAL_ENA_K2_E5_SHIFT                             4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS_K2_E5                                (0x1<<6) // Disable auto cal w/ rx_att_gain
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS_K2_E5_SHIFT                          6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X147_RXEQ_SUPERBST_EN_INVERT_O_K2_E5                                (0x1<<7) // Inverts the polarity of superboost_en before assigning to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X147_RXEQ_SUPERBST_EN_INVERT_O_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X148_K2_E5                                                            0x002250UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X148_RXEQ_OVR_LOAD_EN_O_6_0_K2_E5                                   (0x7f<<0) // Override for RXEQ_CTRL output register load enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X148_RXEQ_OVR_LOAD_EN_O_6_0_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X148_RXEQ_OVR_EN_O_K2_E5                                            (0x1<<7) // Override enable for DFE signals.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X148_RXEQ_OVR_EN_O_K2_E5_SHIFT                                      7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X149_K2_E5                                                            0x002254UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X149_RXEQ_OVR_LOAD_O_6_0_K2_E5                                      (0x7f<<0) // Override for RXEQ_CTRL output register load value.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X149_RXEQ_OVR_LOAD_O_6_0_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X149_RXEQ_OVR_LATCH_O_K2_E5                                         (0x1<<7) // Override for DFE latch signal. Negative edge causes AFE to store values of DFE output registers.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X149_RXEQ_OVR_LATCH_O_K2_E5_SHIFT                                   7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_K2_E5                                                            0x002258UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_RXEQ_DFE_CMP_SEL_OVR_O_2_0_K2_E5                               (0x7<<0) // Override value for comparator calibration select. Enabled by rxeq_ovr_en_o: 1: Calibrate DFE comparator 1 2: Calibrate DFE comparator 2 3: Calibrate DFE comparator 3 4: Calibrate DFE comparator 4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_RXEQ_DFE_CMP_SEL_OVR_O_2_0_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_RXEQ_ATT_GAIN_OVR_K2_E5                                        (0x3<<3) // Override the value of rx_att_gain output to PMA when rx_att_gain_autocal_dis=1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_RXEQ_ATT_GAIN_OVR_K2_E5_SHIFT                                  3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_RXEQ_SUPERBST_ENA_OVR_K2_E5                                    (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_autocal_dis=1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_RXEQ_SUPERBST_ENA_OVR_K2_E5_SHIFT                              5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6_K2_E5                           (0x1<<6) // DFE TAP CMP no offset override enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6_K2_E5_SHIFT                     6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_DFE_TAP_OVR_EN_O_7_K2_E5                                       (0x1<<7) // DFE TAP override enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_DFE_TAP_OVR_EN_O_7_K2_E5_SHIFT                                 7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X151_K2_E5                                                            0x00225cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X151_DFE_OFFSET_CAL_TAP_EN_OVR_O_7_3_K2_E5                          (0x1f<<0) // DFE offset calibration TAP enable override
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X151_DFE_OFFSET_CAL_TAP_EN_OVR_O_7_3_K2_E5_SHIFT                    0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0_K2_E5                            (0x1<<5) // DFE offset calibrated value override enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0_K2_E5_SHIFT                      5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X151_DFE_OFFSET_CAL_EN_OVR_O_1_K2_E5                                (0x1<<6) // DFE offset cal enable override
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X151_DFE_OFFSET_CAL_EN_OVR_O_1_K2_E5_SHIFT                          6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X151_DFE_CMP_CAL_EN_OVR_O_2_K2_E5                                   (0x1<<7) // DFE comparator cal enable override
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X151_DFE_CMP_CAL_EN_OVR_O_2_K2_E5_SHIFT                             7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X152_K2_E5                                                            0x002260UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X152_DFE_TAP1_OVR_VAL_O_6_0_K2_E5                                   (0x7f<<0) // DFE Tap 1 Override Value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X152_DFE_TAP1_OVR_VAL_O_6_0_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X153_K2_E5                                                            0x002264UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X153_DFE_TAP2_OVR_VAL_O_5_0_K2_E5                                   (0x3f<<0) // DFE Tap 2 Override Value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X153_DFE_TAP2_OVR_VAL_O_5_0_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X154_K2_E5                                                            0x002268UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X154_DFE_TAP3_OVR_VAL_O_5_0_K2_E5                                   (0x3f<<0) // DFE Tap 3 Override Value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X154_DFE_TAP3_OVR_VAL_O_5_0_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X155_K2_E5                                                            0x00226cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X155_DFE_TAP4_OVR_VAL_O_5_0_K2_E5                                   (0x3f<<0) // DFE Tap 4 Override Value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X155_DFE_TAP4_OVR_VAL_O_5_0_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X156_K2_E5                                                            0x002270UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X156_DFE_TAP5_OVR_VAL_O_5_0_K2_E5                                   (0x3f<<0) // DFE Tap 5 Override Value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X156_DFE_TAP5_OVR_VAL_O_5_0_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X157_K2_E5                                                            0x002274UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X157_TXEQ_ADAPT_EN_O_0_K2_E5                                        (0x1<<0) // TX Equalizer adaptation function enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X157_TXEQ_ADAPT_EN_O_0_K2_E5_SHIFT                                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X157_TXEQ_ERR_SIGN_O_1_K2_E5                                        (0x1<<1) // TX Equalizer Error Sign
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X157_TXEQ_ERR_SIGN_O_1_K2_E5_SHIFT                                  1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X157_TXEQ_FW_OVRIDE_O_2_K2_E5                                       (0x1<<2) // TX Equalization Firmware over ride  0 -	 Disable firmware based adaptation  1 -	 Enbale firmware based adaptation
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X157_TXEQ_FW_OVRIDE_O_2_K2_E5_SHIFT                                 2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X158_K2_E5                                                            0x002278UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X158_TXEQ_ERR_STAT_I_1_0_K2_E5                                      (0x3<<0) // TX Equalization error state
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X158_TXEQ_ERR_STAT_I_1_0_K2_E5_SHIFT                                0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X159_K2_E5                                                            0x00227cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X159_TXEQ_OVER_EQ_CNT_I_9_8_K2_E5                                   (0x3<<0) // Over equalization count 9-8
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X159_TXEQ_OVER_EQ_CNT_I_9_8_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X160_K2_E5                                                            0x002280UL //Access:R    DataWidth:0x8    // Over equalization count 7-0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X161_K2_E5                                                            0x002284UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X161_TXEQ_UNDER_EQ_CNT_I_9_8_K2_E5                                  (0x3<<0) // Under equalization count 9-8
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X161_TXEQ_UNDER_EQ_CNT_I_9_8_K2_E5_SHIFT                            0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X162_K2_E5                                                            0x002288UL //Access:R    DataWidth:0x8    // Under equalization count 7-0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X163_K2_E5                                                            0x00228cUL //Access:RW   DataWidth:0x8    // TX Equalizer Training Pattern
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X164_K2_E5                                                            0x002290UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X164_TXEQ_TRAINING_PATT_O_8_K2_E5                                   (0x1<<0) // TX Equalizer Training Pattern
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X164_TXEQ_TRAINING_PATT_O_8_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X165_K2_E5                                                            0x002294UL //Access:RW   DataWidth:0x8    // Mask bit for Txeq training pattern
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X166_K2_E5                                                            0x002298UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X166_TXEQ_DONT_CARE_O_8_K2_E5                                       (0x1<<0) // Mask bit for Txeq training pattern
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X166_TXEQ_DONT_CARE_O_8_K2_E5_SHIFT                                 0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X167_K2_E5                                                            0x00229cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X167_TXEQ_RXRECAL_INIT_O_7_K2_E5                                    (0x1<<0) // This bit has similar function as txeq_rxrecal_init  in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X167_TXEQ_RXRECAL_INIT_O_7_K2_E5_SHIFT                              0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X168_K2_E5                                                            0x0022a0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X168_INIT_RX_PRESET_HINT_EN_O_K2_E5                                 (0x1<<0) // Enable for primary input lnx_rx_preset_hint during init cal.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X168_INIT_RX_PRESET_HINT_EN_O_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X168_RECAL_RX_PRESET_HINT_EN_O_K2_E5                                (0x1<<1) // Enable for primary input lnx_rx_preset_hint during recal.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X168_RECAL_RX_PRESET_HINT_EN_O_K2_E5_SHIFT                          1
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X169_K2_E5                                                            0x0022a4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X169_TXEQ_RXRECAL_DONE_I_0_K2_E5                                    (0x1<<0) // TX - RECAL RX Equalization status
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X169_TXEQ_RXRECAL_DONE_I_0_K2_E5_SHIFT                              0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X170_K2_E5                                                            0x0022a8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X170_BLOCK_DEC_ERR_K2_E5                                            (0x1<<0) // decoder sync header error
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X170_BLOCK_DEC_ERR_K2_E5_SHIFT                                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X201_K2_E5                                                            0x002324UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X201_CDFE_EN_O_0_K2_E5                                              (0x1<<0) // cdfe enable bit.  1: enable cdfe when rate is 2'b01 or 2'b10.  0: disable cdfe.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X201_CDFE_EN_O_0_K2_E5_SHIFT                                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X201_CDFE_WORD_OV_O_1_0_K2_E5                                       (0x3<<1) // The cdfe input word_i overwrite.                                                                                                         2'b00: the word_i input for cdfe block is internally generated.                                     2'b10: the word_i input for cdfe block is set to 0 8-bit or 10-bit mode.                                                       2'b11: the word_i input for cdfe block is set to 1 16-bit or 20-bit mode.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X201_CDFE_WORD_OV_O_1_0_K2_E5_SHIFT                                 1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X201_CDFE_MODE_8B_OV_O_1_0_K2_E5                                    (0x3<<3) // The cdfe input mode_8b_i overwrite.                                                                                                         2'b00: the mode_8b_i input for cdfe block is internally generated.                                      2'b01: the mode_8b_i input for cdfe block is set to 0 10-bit or 20-bit mode.                                                      2'b11: the mode_8b_i input for cdfe block is set to 1 8-bit or 16-bit mode.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X201_CDFE_MODE_8B_OV_O_1_0_K2_E5_SHIFT                              3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X201_CDFE_RATE_OV_O_2_0_K2_E5                                       (0x7<<5) // The cdfe input rate_i[1:0] overwrite.                                                                                                         3'b0xx: the rate_i input for cdfe block is internally generated.                                     3'b1xx: the rate_i[1:0] input for cdfe block is set to cdfe_rate_ov_o[1:0]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X201_CDFE_RATE_OV_O_2_0_K2_E5_SHIFT                                 5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X202_K2_E5                                                            0x002328UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X203_K2_E5                                                            0x00232cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X203_CDFE_GO_K2_E5                                                  (0x1<<4) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X203_CDFE_GO_K2_E5_SHIFT                                            4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X203_CDFE_LN_FORCE_CAL_K2_E5                                        (0x1<<5) // The cdfe force calibration enable.  1: enable force cdfe calibration.  0: disable force cdfe calibration.  Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X203_CDFE_LN_FORCE_CAL_K2_E5_SHIFT                                  5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X203_CDFE_LN_RATE_CHANGE_CAL_K2_E5                                  (0x1<<6) // The cdfe force calibration enable.  1: enable force cdfe calibration.  0: disable force cdfe calibration.  Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X203_CDFE_LN_RATE_CHANGE_CAL_K2_E5_SHIFT                            6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X203_CDFE_LN_EI_EXIT_CAL_K2_E5                                      (0x1<<7) // EI exit cdfe calibration enable.                                                                                                   1: the cdfe calibration is enabled when EI exits and when rate is  2'b01 or 2'b10.                                  0: the cdfe calibration is disabled when EI exits.                                                                    Note: EI exit cdfe calibration is only enabled when EI exit edfe calibration is also enabled.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X203_CDFE_LN_EI_EXIT_CAL_K2_E5_SHIFT                                7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_K2_E5                                                            0x002330UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_CONT_CAL_K2_E5                                         (0x1<<0) // Continuous cdfe calibration enable.                                                                                            1: the continuous cdfe calibration is enabled when the rate is  2'b01 or 2'b10.                                  0: the continuous cdfe calibration is disabled.                                                                        Note: Continuout cdfe calibration is only enabled when continuous edfe calibration is also enabled.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_CONT_CAL_K2_E5_SHIFT                                   0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL_K2_E5                             (0x1<<1) // Enables cdfe calibration during Txeq adaptation phase.                                                                                            1: the cdfe calibration is enabled when the rate is  2'b10.                                  0: the cdfe calibration is disabled.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL_K2_E5_SHIFT                       1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL_K2_E5                              (0x1<<2) // Enables cdfe calibration post Txeq adaptation.                                                                                            1: the cdfe calibration is enabled when the rate is  2'b10.                                  0: the cdfe calibration is disabled.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL_K2_E5_SHIFT                        2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_RATE3_CAL_EN_K2_E5                                     (0x1<<3) // Enables the cdfe calibration in rate3.  1: enables cdfe calibration.  0: disables cdfe calibration.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_RATE3_CAL_EN_K2_E5_SHIFT                               3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_RATE2_CAL_EN_K2_E5                                     (0x1<<4) // Enables the cdfe calibration in rate2.  1: enables cdfe calibration.  0: disables cdfe calibration.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_RATE2_CAL_EN_K2_E5_SHIFT                               4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X205_K2_E5                                                            0x002334UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during init cal in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X206_K2_E5                                                            0x002338UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during continuos cal in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X207_K2_E5                                                            0x00233cUL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during re-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X208_K2_E5                                                            0x002340UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X208_AHB_CDFE_COARSE_DLL_OV_EN_K2_E5                                (0x1<<7) // cdfe coarse dll overwrite enable.  1: enable coarse dll overwrite for cdfe.  0: disable coarse dll overwrite for cdfe.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X208_AHB_CDFE_COARSE_DLL_OV_EN_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X213_K2_E5                                                            0x002354UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during txeq adaptation phase in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X214_K2_E5                                                            0x002358UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during post  txeq adaptation  in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X215_K2_E5                                                            0x00235cUL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during init cal in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X216_K2_E5                                                            0x002360UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during continuos cal in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X217_K2_E5                                                            0x002364UL //Access:RW   DataWidth:0x8    // Enables for various cdfe component during re-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X220_K2_E5                                                            0x002370UL //Access:RW   DataWidth:0x8    // Start value for dlev_ref.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X221_K2_E5                                                            0x002374UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X221_CDFE_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_K2_E5                   (0x1f<<0) // Enables copying of adapted tap values to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enables/disables copying to tap3 bit[3] : enables/disables copying to tap4 bit[4] : enables/disables copying to tap5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X221_CDFE_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_K2_E5_SHIFT             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X222_K2_E5                                                            0x002378UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X222_CDFE_NON_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_K2_E5               (0x1f<<0) // Enables copying of adapted tap values to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enables/disables copying to tap3 bit[3] : enables/disables copying to tap4 bit[4] : enables/disables copying to tap5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X222_CDFE_NON_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_K2_E5_SHIFT         0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X223_K2_E5                                                            0x00237cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X223_AHB_CDFE_CMP1_TAP1_OFFSET_K2_E5                                (0x7f<<0) // Override for CMP1 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[1]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X223_AHB_CDFE_CMP1_TAP1_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X224_K2_E5                                                            0x002380UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X224_AHB_CDFE_CMP1_TAP2_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP1 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[2]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X224_AHB_CDFE_CMP1_TAP2_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X225_K2_E5                                                            0x002384UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X225_AHB_CDFE_CMP1_TAP3_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP1 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[3]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X225_AHB_CDFE_CMP1_TAP3_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X226_K2_E5                                                            0x002388UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X226_AHB_CDFE_CMP1_TAP4_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP1 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[4]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X226_AHB_CDFE_CMP1_TAP4_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X227_K2_E5                                                            0x00238cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X227_AHB_CDFE_CMP1_TAP5_OFFSET_K2_E5                                (0x3f<<0) // Override for CMP1 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[5]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X227_AHB_CDFE_CMP1_TAP5_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X228_K2_E5                                                            0x002390UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X228_AHB_CDFE_CMP2_TAP1_OFFSET_K2_E5                                (0x7f<<0) // Override for CMP2 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[1]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X228_AHB_CDFE_CMP2_TAP1_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X229_K2_E5                                                            0x002394UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X229_AHB_CDFE_CMP2_TAP2_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP2 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[2]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X229_AHB_CDFE_CMP2_TAP2_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X230_K2_E5                                                            0x002398UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X230_AHB_CDFE_CMP2_TAP3_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP2 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[3]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X230_AHB_CDFE_CMP2_TAP3_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X231_K2_E5                                                            0x00239cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X231_AHB_CDFE_CMP2_TAP4_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP2 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[4]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X231_AHB_CDFE_CMP2_TAP4_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X232_K2_E5                                                            0x0023a0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X232_AHB_CDFE_CMP2_TAP5_OFFSET_K2_E5                                (0x3f<<0) // Override for CMP2 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[5]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X232_AHB_CDFE_CMP2_TAP5_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X233_K2_E5                                                            0x0023a4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X233_AHB_CDFE_CMP3_TAP1_OFFSET_K2_E5                                (0x7f<<0) // Override for CMP3 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[1]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X233_AHB_CDFE_CMP3_TAP1_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X234_K2_E5                                                            0x0023a8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X234_AHB_CDFE_CMP3_TAP2_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP3 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[2]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X234_AHB_CDFE_CMP3_TAP2_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X235_K2_E5                                                            0x0023acUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X235_AHB_CDFE_CMP3_TAP3_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP3 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[3]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X235_AHB_CDFE_CMP3_TAP3_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X236_K2_E5                                                            0x0023b0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X236_AHB_CDFE_CMP3_TAP4_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP3 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[4]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X236_AHB_CDFE_CMP3_TAP4_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X237_K2_E5                                                            0x0023b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X237_AHB_CDFE_CMP3_TAP5_OFFSET_K2_E5                                (0x3f<<0) // Override for CMP3 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[5]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X237_AHB_CDFE_CMP3_TAP5_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X238_K2_E5                                                            0x0023b8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X238_AHB_CDFE_CMP4_TAP1_OFFSET_K2_E5                                (0x7f<<0) // Override for CMP4 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[1]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X238_AHB_CDFE_CMP4_TAP1_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X239_K2_E5                                                            0x0023bcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X239_AHB_CDFE_CMP4_TAP2_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP4 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[2]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X239_AHB_CDFE_CMP4_TAP2_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X240_K2_E5                                                            0x0023c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X240_AHB_CDFE_CMP4_TAP3_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP4 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[3]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X240_AHB_CDFE_CMP4_TAP3_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X241_K2_E5                                                            0x0023c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X241_AHB_CDFE_CMP4_TAP4_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP4 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[4]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X241_AHB_CDFE_CMP4_TAP4_OFFSET_5_0_K2_E5_SHIFT                      0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X242_K2_E5                                                            0x0023c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X242_AHB_CDFE_CMP4_TAP5_OFFSET_K2_E5                                (0x3f<<0) // Override for CMP4 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[5]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X242_AHB_CDFE_CMP4_TAP5_OFFSET_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X243_K2_E5                                                            0x0023ccUL //Access:RW   DataWidth:0x8    // Override for CMP1 main calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[0]
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X244_K2_E5                                                            0x0023d0UL //Access:RW   DataWidth:0x8    // Override for CMP2 main calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[0]
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X245_K2_E5                                                            0x0023d4UL //Access:RW   DataWidth:0x8    // Override for CMP3 main calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[0]
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X246_K2_E5                                                            0x0023d8UL //Access:RW   DataWidth:0x8    // Override for CMP4 main calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[0]
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X247_K2_E5                                                            0x0023dcUL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X248_K2_E5                                                            0x0023e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X248_AHB_CDFE_DLL_FINE_MASK_9_8_K2_E5                               (0x3<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X248_AHB_CDFE_DLL_FINE_MASK_9_8_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X248_AHB_CDFE_FINE_DLL_EDGE_SHIFT_K2_E5                             (0xf<<2) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X248_AHB_CDFE_FINE_DLL_EDGE_SHIFT_K2_E5_SHIFT                       2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X249_K2_E5                                                            0x0023e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X249_AHB_CDFE_ERR_SMPL_SHIFT_K2_E5                                  (0xf<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X249_AHB_CDFE_ERR_SMPL_SHIFT_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X249_AHB_CDFE_FINE_DLL_OV_EN_K2_E5                                  (0x1<<4) // cdfe fine dll overwrite enable.  1: enable fine dll overwrite for cdfe.  0: disable fine dll overwrite for cdfe.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X249_AHB_CDFE_FINE_DLL_OV_EN_K2_E5_SHIFT                            4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_K2_E5                                                            0x0023e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8_K2_E5                        (0x1<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8_K2_E5_SHIFT                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_K2_E5                       (0x1<<1) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_K2_E5_SHIFT                 1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8_K2_E5                        (0x1<<2) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8_K2_E5_SHIFT                  2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_K2_E5                       (0x1<<3) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_K2_E5_SHIFT                 3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X251_K2_E5                                                            0x0023ecUL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X252_K2_E5                                                            0x0023f0UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X253_K2_E5                                                            0x0023f4UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X254_K2_E5                                                            0x0023f8UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_K2_E5                                                            0x0023fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_CDFE_DIR_OV_EN_K2_E5                                           (0x1<<0) // Override enable for CDFE calibration direction
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_CDFE_DIR_OV_EN_K2_E5_SHIFT                                     0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_CDFE_DIR_OV_VAL_K2_E5                                          (0x1<<1) // Override value for CDFE calibration direction
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_CDFE_DIR_OV_VAL_K2_E5_SHIFT                                    1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_EYE_ENA270_OVR_EN_O_K2_E5                               (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_EYE_ENA270_OVR_EN_O_K2_E5_SHIFT                         2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_EYE_ENA90_OVR_EN_O_K2_E5                                (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_EYE_ENA90_OVR_EN_O_K2_E5_SHIFT                          3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_PHD_ENA_OVR_EN_O_K2_E5                                  (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_PHD_ENA_OVR_EN_O_K2_E5_SHIFT                            4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_EYE_DLY_OVR_EN_O_K2_E5                                  (0x1<<5) // cdfe eye delay overwrite enable.  1: enable eye delay overwrite for cdfe.  0: disable eye delay overwrite for cdfe.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_EYE_DLY_OVR_EN_O_K2_E5_SHIFT                            5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O_K2_E5                              (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O_K2_E5_SHIFT                        6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X256_K2_E5                                                            0x002400UL //Access:RW   DataWidth:0x8    // cdfe eye delay count overwrite value for CLK90.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X257_K2_E5                                                            0x002404UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8_K2_E5                           (0x1<<0) // cdfe eye delay count overwrite value for CLK90.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8_K2_E5_SHIFT                     0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_K2_E5                   (0x7f<<1) // This register represents the maximum comparator offset from the midpoint code 127/128 that must be met for the comparator to be selected as adaptation comparator during dlev and tap adaptation.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_K2_E5_SHIFT             1
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X258_K2_E5                                                            0x002408UL //Access:RW   DataWidth:0x8    // cdfe eye delay count overwrite value for CLK270.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X259_K2_E5                                                            0x00240cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8_K2_E5                          (0x1<<0) // cdfe eye delay count overwrite value for CLK270.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8_K2_E5_SHIFT                    0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X259_AHB_CDFE_DLEV_OV_EN_K2_E5                                      (0x1<<1) // cdfe dlev overwrite enable.  1: enable dlev overwrite for cdfe.  0: disable dlev overwrite for cdfe.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X259_AHB_CDFE_DLEV_OV_EN_K2_E5_SHIFT                                1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X259_CDFE_DLEV_ADAPT_CMP_SEL_OVR_O_4_0_K2_E5                        (0x1f<<2) // Register override for overriding adaptation comparator select bit [0] : override enable bit [4:1] : override value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X259_CDFE_DLEV_ADAPT_CMP_SEL_OVR_O_4_0_K2_E5_SHIFT                  2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_K2_E5                   (0x1<<7) // Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_K2_E5_SHIFT             7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X260_K2_E5                                                            0x002410UL //Access:RW   DataWidth:0x8    // Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X261_K2_E5                                                            0x002414UL //Access:RW   DataWidth:0x8    // cdfe dlevn overwrite value.
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X262_K2_E5                                                            0x002418UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X262_AHB_CDFE_TAP_OV_EN_K2_E5                                       (0x1f<<0) // cdfe tap1~5 overwrite enable.                                                                                                    Bit[0]: enable tap1 overwrite for cdfe. Bit[1]: enable tap2 overwrite for cdfe Bit[2]: enable tap3 overwrite for cdfe.  Bit[3]: enable tap4 overwrite for cdfe. Bit[4]: enable tap5 overwrite for cdfe.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X262_AHB_CDFE_TAP_OV_EN_K2_E5_SHIFT                                 0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X263_K2_E5                                                            0x00241cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X263_AHB_CDFE_TAP1_OV_K2_E5                                         (0x7f<<0) // cdfe tap1 overwrite value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X263_AHB_CDFE_TAP1_OV_K2_E5_SHIFT                                   0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X264_K2_E5                                                            0x002420UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X264_AHB_CDFE_TAP2_OV_K2_E5                                         (0x3f<<0) // cdfe tap2 overwrite value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X264_AHB_CDFE_TAP2_OV_K2_E5_SHIFT                                   0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X265_K2_E5                                                            0x002424UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X265_AHB_CDFE_TAP3_OV_K2_E5                                         (0x3f<<0) // cdfe tap3 overwrite value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X265_AHB_CDFE_TAP3_OV_K2_E5_SHIFT                                   0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X266_K2_E5                                                            0x002428UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X266_AHB_CDFE_TAP4_OV_K2_E5                                         (0x3f<<0) // cdfe tap4 overwrite value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X266_AHB_CDFE_TAP4_OV_K2_E5_SHIFT                                   0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X267_K2_E5                                                            0x00242cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X267_AHB_CDFE_TAP5_OV_K2_E5                                         (0x3f<<0) // cdfe tap5 overwrite value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X267_AHB_CDFE_TAP5_OV_K2_E5_SHIFT                                   0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_K2_E5                   (0x1<<7) // Enables FW enable control for TAP adapt using DLEV
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_K2_E5_SHIFT             7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_K2_E5                                                            0x002430UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O_K2_E5                           (0x1<<0) // Instucts to start TAP adapt using DLEV in FW enabled mode
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O_K2_E5_SHIFT                     0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_K2_E5                 (0x1<<1) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_K2_E5_SHIFT           1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O_K2_E5             (0x1<<2) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O_K2_E5_SHIFT       2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_K2_E5                                (0x1<<7) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X269_K2_E5                                                            0x002434UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O_K2_E5                         (0x1<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O_K2_E5_SHIFT                   0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X269_AHB_CDFE_STROBE_EN_O_K2_E5                                     (0x1<<1) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X269_AHB_CDFE_STROBE_EN_O_K2_E5_SHIFT                               1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X269_AHB_CDFE_CMP_ENA_O_K2_E5                                       (0xf<<2) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X269_AHB_CDFE_CMP_ENA_O_K2_E5_SHIFT                                 2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X270_K2_E5                                                            0x002438UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X271_K2_E5                                                            0x00243cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X271_AHB_CDFE_DIV_SIGN_BIT_O_4_0_K2_E5                              (0x1f<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X271_AHB_CDFE_DIV_SIGN_BIT_O_4_0_K2_E5_SHIFT                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O_K2_E5                      (0x1<<5) // Forces the positive dlev training pattern to be used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O_K2_E5_SHIFT                5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O_K2_E5                      (0x1<<6) // Forces the negative dlev training pattern to be used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O_K2_E5_SHIFT                6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X272_K2_E5                                                            0x002440UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X272_CDFE_TAP1_SCALE_O_2_0_K2_E5                                    (0x7<<0) // Scale factor CDFE TAP1 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X272_CDFE_TAP1_SCALE_O_2_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X272_CDFE_TAP1_SHIFT_O_4_0_K2_E5                                    (0x1f<<3) // Shift factor CDFE TAP1 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X272_CDFE_TAP1_SHIFT_O_4_0_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X273_K2_E5                                                            0x002444UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X273_CDFE_TAP2_SCALE_O_2_0_K2_E5                                    (0x7<<0) // Scale factor CDFE TAP2 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X273_CDFE_TAP2_SCALE_O_2_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X273_CDFE_TAP2_SHIFT_O_4_0_K2_E5                                    (0x1f<<3) // Shift factor CDFE TAP2 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X273_CDFE_TAP2_SHIFT_O_4_0_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X274_K2_E5                                                            0x002448UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X274_CDFE_TAP3_SCALE_O_2_0_K2_E5                                    (0x7<<0) // Scale factor CDFE TAP3 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X274_CDFE_TAP3_SCALE_O_2_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X274_CDFE_TAP3_SHIFT_O_4_0_K2_E5                                    (0x1f<<3) // Shift factor CDFE TAP3 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X274_CDFE_TAP3_SHIFT_O_4_0_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X275_K2_E5                                                            0x00244cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X275_CDFE_TAP4_SCALE_O_2_0_K2_E5                                    (0x7<<0) // Scale factor CDFE TAP4 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X275_CDFE_TAP4_SCALE_O_2_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X275_CDFE_TAP4_SHIFT_O_4_0_K2_E5                                    (0x1f<<3) // Shift factor CDFE TAP4 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X275_CDFE_TAP4_SHIFT_O_4_0_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X276_K2_E5                                                            0x002450UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X276_CDFE_TAP5_SCALE_O_2_0_K2_E5                                    (0x7<<0) // Scale factor CDFE TAP5 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X276_CDFE_TAP5_SCALE_O_2_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X276_CDFE_TAP5_SHIFT_O_4_0_K2_E5                                    (0x1f<<3) // Shift factor CDFE TAP5 adapted value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X276_CDFE_TAP5_SHIFT_O_4_0_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X277_K2_E5                                                            0x002454UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X277_LN_MSM_RESET_RA_OVR_O_K2_E5                                    (0x3<<0) // Bit 0:  Override enable for msm_reset_ra Bit 1: Override msm_reset_ra
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X277_LN_MSM_RESET_RA_OVR_O_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X277_LN_MSM_RESET_P2S_OVR_O_K2_E5                                   (0x3<<2) // Bit 0:  Override enable for msm_reset_p2s Bit 1: Override msm_reset_p2s
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X277_LN_MSM_RESET_P2S_OVR_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X277_LN_MSM_RESET_LNREGH_OVR_O_K2_E5                                (0x3<<4) // Bit 0:  Override enable for msm_reset_lnregh Bit 1: Override msm_reset_lnregh
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X277_LN_MSM_RESET_LNREGH_OVR_O_K2_E5_SHIFT                          4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X277_LN_MSM_RESET_LNREG_OVR_O_K2_E5                                 (0x3<<6) // Bit 0:  Override enable for msm_reset_lnreg Bit 1: Override msm_reset_lnreg
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X277_LN_MSM_RESET_LNREG_OVR_O_K2_E5_SHIFT                           6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X278_K2_E5                                                            0x002458UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X278_LN_MSM_RESET_CDR_OVR_O_K2_E5                                   (0x3<<0) // Bit 0:  Override enable for msm_reset_cdr Bit 1: Override msm_reset_cdr
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X278_LN_MSM_RESET_CDR_OVR_O_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X278_LN_MSM_RESET_DFE_OVR_O_K2_E5                                   (0x3<<2) // Bit 0:  Override enable for msm_reset_dfe Bit 1: Override msm_reset_dfe
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X278_LN_MSM_RESET_DFE_OVR_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X278_LN_MSM_PD_LNREGH_OVR_O_K2_E5                                   (0x3<<4) // Bit 0:  Override enable for msm_pd_lnregh Bit 1: Override msm_pd_lnregh
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X278_LN_MSM_PD_LNREGH_OVR_O_K2_E5_SHIFT                             4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X278_LN_MSM_PD_VCO_BUF_OVR_O_K2_E5                                  (0x3<<6) // Bit 0:  Override enable for msm_pd_vco_buf Bit 1: Override msm_pd_vco_buf
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X278_LN_MSM_PD_VCO_BUF_OVR_O_K2_E5_SHIFT                            6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X279_K2_E5                                                            0x00245cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X279_LN_MSM_RESET_CDR_GCRX_OVR_O_K2_E5                              (0x3<<0) // Bit 0:  Override enable for msm_reset_cdr_gcrx Bit 1: Override msm_reset_cdr_gcrx
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X279_LN_MSM_RESET_CDR_GCRX_OVR_O_K2_E5_SHIFT                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X279_LN_MSM_RXGATE_EN_OVR_O_K2_E5                                   (0x3<<2) // Bit 0:  Override enable for msm_rxgate_en Bit 1: Override msm_rxgate_en
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X279_LN_MSM_RXGATE_EN_OVR_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X279_LN_MSM_RESET_VCO_OVR_O_K2_E5                                   (0x3<<4) // Bit 0:  Override enable for msm_reset_vco Bit 1: Override msm_reset_vco
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X279_LN_MSM_RESET_VCO_OVR_O_K2_E5_SHIFT                             4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X279_LN_MSM_IDDQ_SD_OVR_O_K2_E5                                     (0x3<<6) // Bit 0:  Override enable for msm_iddq_sd Bit 1: Override msm_iddq_sd
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X279_LN_MSM_IDDQ_SD_OVR_O_K2_E5_SHIFT                               6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X280_K2_E5                                                            0x002460UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X280_LN_MSM_PD_DFE_OVR_O_K2_E5                                      (0x3<<0) // Bit 0:  Override enable for msm_pd_dfe Bit 1: Override msm_pd_dfe
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X280_LN_MSM_PD_DFE_OVR_O_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X280_LN_MSM_PD_DFE_BIAS_OVR_O_K2_E5                                 (0x3<<2) // Bit 0:  Override enable for msm_pd_dfe_bias Bit 1: Override msm_pd_dfe_bias
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X280_LN_MSM_PD_DFE_BIAS_OVR_O_K2_E5_SHIFT                           2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X280_LN_MSM_TXDRV_LP_IDLE_OVR_O_K2_E5                               (0x3<<4) // Bit 0:  Override enable for msm_txdrv_lp_idle Bit 1: Override msm_txdrv_lp_idle
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X280_LN_MSM_TXDRV_LP_IDLE_OVR_O_K2_E5_SHIFT                         4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X280_LN_MSM_TXREG_BLEED_ENA_OVR_O_K2_E5                             (0x3<<6) // Bit 0:  Override enable for msm_txreg_bleed_ena Bit 1: Override msm_txreg_bleed_ena
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X280_LN_MSM_TXREG_BLEED_ENA_OVR_O_K2_E5_SHIFT                       6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X281_K2_E5                                                            0x002464UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X281_LN_MSM_PD_TXREG_OVR_O_K2_E5                                    (0x3<<0) // Bit 0:  Override enable for msm_pd_txreg Bit 1: Override msm_pd_txreg
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X281_LN_MSM_PD_TXREG_OVR_O_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X281_LN_MSM_PD_LNREG_OVR_O_K2_E5                                    (0x3<<2) // Bit 0:  Override enable for msm_pd_lnreg Bit 1: Override msm_pd_lnreg
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X281_LN_MSM_PD_LNREG_OVR_O_K2_E5_SHIFT                              2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X281_LN_MSM_PD_P2S_OVR_O_K2_E5                                      (0x3<<4) // Bit 0:  Override enable for pd_p2s Bit 1: Override pd_p2s
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X281_LN_MSM_PD_P2S_OVR_O_K2_E5_SHIFT                                4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X281_LN_MSM_PD_RA_OVR_O_K2_E5                                       (0x3<<6) // Bit 0:  Override enable for pd_ra Bit 1: Override pd_ra
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X281_LN_MSM_PD_RA_OVR_O_K2_E5_SHIFT                                 6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X282_K2_E5                                                            0x002468UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X282_LN_MSM_PD_SLV_BIAS_OVR_O_K2_E5                                 (0x3<<2) // Bit 0:  Override enable for pd_slv_bias Bit 1: Override pd_slv_bias
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X282_LN_MSM_PD_SLV_BIAS_OVR_O_K2_E5_SHIFT                           2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X282_LN_MSM_PD_TXDRV_OVR_O_K2_E5                                    (0x3<<4) // Bit 0:  Override enable for pd_txdrv Bit 1: Override pd_txdrv
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X282_LN_MSM_PD_TXDRV_OVR_O_K2_E5_SHIFT                              4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X282_LN_MSM_PD_VCO_OVR_O_K2_E5                                      (0x3<<6) // Bit 0:  Override enable for msm_pd_vco Bit 1: Override msm_pd_vco
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X282_LN_MSM_PD_VCO_OVR_O_K2_E5_SHIFT                                6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X283_K2_E5                                                            0x00246cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X283_LN_MSM_CDR_EN_OVR_O_K2_E5                                      (0x3<<0) // Bit 0:  Override enable for msm_cdr_en Bit 1: Override msm_cdr_en
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X283_LN_MSM_CDR_EN_OVR_O_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X283_LN_MSM_RESET_S2P_OVR_O_K2_E5                                   (0x3<<2) // Bit 0:  Override enable for msm_reset_s2p Bit 1: Override msm_reset_s2p
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X283_LN_MSM_RESET_S2P_OVR_O_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X283_LN_MSM_RXCLK_EN_OVR_O_K2_E5                                    (0x3<<4) // Bit 0:  Override enable for msm_rxclk_en Bit 1: Override msm_rxclk_en
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X283_LN_MSM_RXCLK_EN_OVR_O_K2_E5_SHIFT                              4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X283_LN_MSM_WORD_OVR_O_K2_E5                                        (0x3<<6) // Bit 0:  Override enable for msm_word Bit 1: Override msm_word
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X283_LN_MSM_WORD_OVR_O_K2_E5_SHIFT                                  6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X284_K2_E5                                                            0x002470UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X284_LN_MSM_RATE_OVR_O_K2_E5                                        (0x7<<0) // Bit 0:  Override enable for msm_rate Bit [2:1] : Override msm_rate
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X284_LN_MSM_RATE_OVR_O_K2_E5_SHIFT                                  0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X284_LN_MSM_RXVCODIV_OVR_O_K2_E5                                    (0x7<<3) // Bit 0:  Override enable for msm_rxvcodiv Bit [2:1] : Override msm_rxvcodiv
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X284_LN_MSM_RXVCODIV_OVR_O_K2_E5_SHIFT                              3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X284_LN_MSM_RESET_TX_CLKDIV_OVR_O_K2_E5                             (0x3<<6) // Not currently used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X284_LN_MSM_RESET_TX_CLKDIV_OVR_O_K2_E5_SHIFT                       6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X285_K2_E5                                                            0x002474UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X285_LN_MSM_TXVCODIV_OVR_O_K2_E5                                    (0x7<<0) // Bit 0:  Override enable for msm_txvcodiv Bit [2:1] : Override msm_txvcodiv
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X285_LN_MSM_TXVCODIV_OVR_O_K2_E5_SHIFT                              0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_K2_E5                                                            0x0024b4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_RX_SRC_O_K2_E5                                                 (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 - Output of mux is output from 8b/10b encoder.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_RX_SRC_O_K2_E5_SHIFT                                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_TREG0_POL_O_K2_E5                                              (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_TREG0_POL_O_K2_E5_SHIFT                                        1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_TREG0_BIT_O_K2_E5                                              (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_TREG0_BIT_O_K2_E5_SHIFT                                        2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_TREG0_WORD_O_K2_E5                                             (0x1<<3) // TReg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_TREG0_WORD_O_K2_E5_SHIFT                                       3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_DMUX_TXA_SEL_O_1_0_K2_E5                                       (0x3<<4) // Transmit mux A data input select.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_DMUX_TXA_SEL_O_1_0_K2_E5_SHIFT                                 4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_P2S_RBUF_AUTOFIX_O_K2_E5                                       (0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / underflows 1 - Ring buffer will reset upon detection of overflow/underflow
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_P2S_RBUF_AUTOFIX_O_K2_E5_SHIFT                                 6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_K2_E5                                                            0x0024b8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_TREG1_POL_O_K2_E5                                              (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_TREG1_POL_O_K2_E5_SHIFT                                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_TREG1_BIT_O_K2_E5                                              (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_TREG1_BIT_O_K2_E5_SHIFT                                        1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_TREG1_WORD_O_K2_E5                                             (0x1<<2) // TReg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_TREG1_WORD_O_K2_E5_SHIFT                                       2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_REG1_POL_O_K2_E5                                               (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_REG1_POL_O_K2_E5_SHIFT                                         3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_REG1_BIT_O_K2_E5                                               (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_REG1_BIT_O_K2_E5_SHIFT                                         4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_REG1_WORD_O_K2_E5                                              (0x1<<5) // Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_REG1_WORD_O_K2_E5_SHIFT                                        5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_REG0_POL_O_K2_E5                                               (0x1<<6) // Used as Reg0 polarity select
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_REG0_POL_O_K2_E5_SHIFT                                         6
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_K2_E5                                                            0x0024bcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_REG0_BIT_O_K2_E5                                               (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_REG0_BIT_O_K2_E5_SHIFT                                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_REG0_WORD_O_K2_E5                                              (0x1<<1) // Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_REG0_WORD_O_K2_E5_SHIFT                                        1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_DMUX_TXB_SEL_O_2_0_K2_E5                                       (0x7<<2) // Transmit mux B data input select enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_DMUX_TXB_SEL_O_2_0_K2_E5_SHIFT                                 2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_TX_CTRL_O_24_K2_E5                                             (0x1<<5) // Bit 24: txdrv_c2_in[3]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_TX_CTRL_O_24_K2_E5_SHIFT                                       5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_WIDTH_CHNG_EN_O_K2_E5                                          (0x1<<6) // Enable bit for width_chng module
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_WIDTH_CHNG_EN_O_K2_E5_SHIFT                                    6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_TXTERM_CAL_SEQ_EN_O_K2_E5                                      (0x1<<7) // Txterm calibration enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_TXTERM_CAL_SEQ_EN_O_K2_E5_SHIFT                                7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X304_K2_E5                                                            0x0024c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X304_TXTERM_CAL_RSEL_K2_E5                                          (0x7<<0) // tx termination calibration comparator threshold select
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X304_TXTERM_CAL_RSEL_K2_E5_SHIFT                                    0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X304_AHB_LN_RXBIT_STRIP_O_K2_E5                                     (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2b00: no bit stripping 2b01: 2x bit stripping 2b10: reserved 2b11: 4x bit stripping
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X304_AHB_LN_RXBIT_STRIP_O_K2_E5_SHIFT                               3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X304_AHB_MAC_WIDTH_O_K2_E5                                          (0x3<<5) // Data width selector for PCS/MAC interface. 2b00: GigE or XAUI 2b01: GigE or XAUI 2b10: RXAUI 2b11: XFI
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X304_AHB_MAC_WIDTH_O_K2_E5_SHIFT                                    5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X305_K2_E5                                                            0x0024c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X305_AHB_TXMAC_THRESHOLD_O_K2_E5                                    (0x3<<0) // An internal FIFO is included to handle the communication between the external 64-bit data and the internal 20-bit data. The reading operation will begin only when the difference between the write pointer and read pointer for this FIFO reaches ahb_txmac_threshold_o.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X305_AHB_TXMAC_THRESHOLD_O_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X305_AHB_LN_TXBIT_REPEAT_O_K2_E5                                    (0x3<<2) // Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to PCS 2b00: no bit stuffing nor stripping 2b01: 2x bit stuffing and stripping 2b10: reserved 2b11: 4x bit stuffing and stripping
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X305_AHB_LN_TXBIT_REPEAT_O_K2_E5_SHIFT                              2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X305_MODE_8B_O_1_0_K2_E5                                            (0x3<<4) // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data word 8 bits
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X305_MODE_8B_O_1_0_K2_E5_SHIFT                                      4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X305_ENC_EN_O_K2_E5                                                 (0x1<<6) // 8b/10b encoder enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X305_ENC_EN_O_K2_E5_SHIFT                                           6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X305_DEC_EN_O_K2_E5                                                 (0x1<<7) // 8b/10b decoder enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X305_DEC_EN_O_K2_E5_SHIFT                                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X306_K2_E5                                                            0x0024c8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X306_AHB_TX_CDAC_OVR_K2_E5                                          (0xf<<0) // TX termination calibration DAC override. Signal ahb_tx_term_en_cal_ovr must also be asserted to take effect.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X306_AHB_TX_CDAC_OVR_K2_E5_SHIFT                                    0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X306_LN_COMMON_SYNC_TXCLK_EN_O_K2_E5                                (0x1<<4) // Per lane common synchronous clock between PMA, PCS and SoC logic enable bit. 1: in NORM state, lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA or its divided down version and this clock can be used as a common synchronous clock between PMA, PCS and SoC logic. In other state, it is switched to cmu_ck_soc_o[1]. 0: lnX_ck_txb_o is swtiched to cmu_ck_soc_o[1].
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X306_LN_COMMON_SYNC_TXCLK_EN_O_K2_E5_SHIFT                          4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X307_K2_E5                                                            0x0024ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X307_LN_TO_CLK_TXB_WAIT_O_K2_E5                                     (0x1f<<0) // In per lane common synchronous clock mode, after the lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA. The lnX_ok_o will get asserted after lnX_to_clk_txb_wait_o lnX_ck_txb_o cycles.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X307_LN_TO_CLK_TXB_WAIT_O_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X307_PIPE_EN_O_K2_E5                                                (0x1<<5) // PIPE interface block enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X307_PIPE_EN_O_K2_E5_SHIFT                                          5
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X307_SAPIS_EN_O_K2_E5                                               (0x1<<6) // SAPIS interface block enable.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X307_SAPIS_EN_O_K2_E5_SHIFT                                         6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X307_USB_MODE_K2_E5                                                 (0x1<<7) // Signal Detect USB mode enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X307_USB_MODE_K2_E5_SHIFT                                           7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_K2_E5                                                            0x0024d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_BLOCK_ENC_CLR_ERR_O_K2_E5                                      (0x1<<1) // 128b/130b encoder clear error
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_BLOCK_ENC_CLR_ERR_O_K2_E5_SHIFT                                1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_BLOCK_DEC_EN_ERR_CHK_O_K2_E5                                   (0x1<<3) // 130b/128b error check enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_BLOCK_DEC_EN_ERR_CHK_O_K2_E5_SHIFT                             3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_BLOCK_DEC_CHK_OS_NMBR_O_2_0_K2_E5                              (0x7<<4) // 130b/128b: number of OS indicating end of data
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_BLOCK_DEC_CHK_OS_NMBR_O_2_0_K2_E5_SHIFT                        4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_BLOCK_DEC_CLR_ERR_O_K2_E5                                      (0x1<<7) // 130b/128b: clear error flag
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_BLOCK_DEC_CLR_ERR_O_K2_E5_SHIFT                                7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X309_K2_E5                                                            0x0024d4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X309_BLOCK_DEC_ERR_THRESHOLD_O_3_0_K2_E5                            (0xf<<0) // 130b/128b: number of sync hdr errors before asserting sync error flag
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X309_BLOCK_DEC_ERR_THRESHOLD_O_3_0_K2_E5_SHIFT                      0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X309_BLOCK_DEC_CHK_BLK_NMBR_O_3_0_K2_E5                             (0xf<<4) // 130b/128b: number of continuous blocks checked
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X309_BLOCK_DEC_CHK_BLK_NMBR_O_3_0_K2_E5_SHIFT                       4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_K2_E5                                                            0x0024d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_EBUF_RSTN_O_K2_E5                                              (0x1<<0) // Synchronous clear for elastic buffer
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_EBUF_RSTN_O_K2_E5_SHIFT                                        0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_ALIGN_RSTN_O_K2_E5                                             (0x1<<1) // Synchronous clear for block/symbol aligner
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_ALIGN_RSTN_O_K2_E5_SHIFT                                       1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_EBUF_SKP_ADD_EN_O_K2_E5                                        (0x1<<2) // Elastic buffer SKP add enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_EBUF_SKP_ADD_EN_O_K2_E5_SHIFT                                  2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_RBUF_RSTN_O_K2_E5                                              (0x1<<3) // TX FIFO synchronous reset
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_RBUF_RSTN_O_K2_E5_SHIFT                                        3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_EN_SKPOS_ERR_O_K2_E5                                           (0x1<<5) // Enables skpos error status propagation in Gen3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_EN_SKPOS_ERR_O_K2_E5_SHIFT                                     5
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X311_K2_E5                                                            0x0024dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X311_PIPE_LFREQ_K2_E5                                               (0x3f<<0) // LF value for full swing
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X311_PIPE_LFREQ_K2_E5_SHIFT                                         0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X311_DIS_BLOCK_ALIGN_CTRL_O_K2_E5                                   (0x1<<6) // Disables the primary input lnX_block_align_control
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X311_DIS_BLOCK_ALIGN_CTRL_O_K2_E5_SHIFT                             6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X311_DIS_EIEOS_CHK_IN_LB_O_K2_E5                                    (0x1<<7) // Disables the EIEOS check in loopback
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X311_DIS_EIEOS_CHK_IN_LB_O_K2_E5_SHIFT                              7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X312_K2_E5                                                            0x0024e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X312_COEF_FE_LIMIT_EN_O_K2_E5                                       (0x1<<0) // FE TxEq Co-efficient Limiting Enable control
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X312_COEF_FE_LIMIT_EN_O_K2_E5_SHIFT                                 0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X312_RXVALID_DIS_AT_RATE_CHG_O_0_K2_E5                              (0x1<<1) // Value 1 forces rxvalid to be deasserted during rate change to gen 3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X312_RXVALID_DIS_AT_RATE_CHG_O_0_K2_E5_SHIFT                        1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X312_P2S_RBUF_BUF_THRESH_O_3_0_K2_E5                                (0xf<<2) // TX FIFO: specifies how far write pointer need to be ahead of read pointer before almost_full_o is asserted
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X312_P2S_RBUF_BUF_THRESH_O_3_0_K2_E5_SHIFT                          2
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X313_K2_E5                                                            0x0024e4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X313_AHB_RX_GEARBOX_DISABLE_O_K2_E5                                 (0x1<<0) // 0: enable rx_gearbox, 1: disable rx_gearbox
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X313_AHB_RX_GEARBOX_DISABLE_O_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X313_AHB_TX_GEARBOX_DISABLE_O_K2_E5                                 (0x1<<1) // 0: enable tx_gearbox, 1: disable tx_gearbox
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X313_AHB_TX_GEARBOX_DISABLE_O_K2_E5_SHIFT                           1
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_K2_E5                                                            0x0024e8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_GEN1_OLD_RXDATA_SRC_K2_E5                                      (0x1<<0) // Mux select for data input to polbit_reg0  0:pma_ln_dfe_err_i , 1: pma_ln_rxdata_i
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_GEN1_OLD_RXDATA_SRC_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_SKIP_CDR_GEN3_O_K2_E5                                          (0x1<<1) // To skip cdr calibration routines for PCIe gen3.  Can be used when PHY is operating in gen1,2 only.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_SKIP_CDR_GEN3_O_K2_E5_SHIFT                                    1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_SKIP_CDR_GEN12_O_K2_E5                                         (0x1<<2) // To skip cdr calibration routines for PCIe gen1,2.  May not be needed in real scenario.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_SKIP_CDR_GEN12_O_K2_E5_SHIFT                                   2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_K2_E5                               (0x1<<3) // Receive amplifier powerdown override, when cisel is high
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_K2_E5_SHIFT                         3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_LN_P2S_RBUF_REALIGN_DIFF_O_K2_E5                               (0xf<<4) // In per lane common synchronous clock mode, ln_p2x_rbuf_realign_diff_o defines the starting difference between write pointer and read pointer when re aligning the pointer of TxFIFO.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_LN_P2S_RBUF_REALIGN_DIFF_O_K2_E5_SHIFT                         4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X315_K2_E5                                                            0x0024ecUL //Access:RW   DataWidth:0x8    // Delays the beacon_ena propagation to PMA
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X316_K2_E5                                                            0x0024f0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X316_AHB_BEACON_DELAYED_COUNT_NUMBER_11_8_O_K2_E5                   (0xf<<0) // Delays the beacon_ena propagation to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X316_AHB_BEACON_DELAYED_COUNT_NUMBER_11_8_O_K2_E5_SHIFT             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_K2_E5                                                            0x0024f4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_AHB_BEACON_ENA_OVR_ENA_O_K2_E5                                 (0x1<<0) // Beacon Override Enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_AHB_BEACON_ENA_OVR_ENA_O_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_AHB_BEACON_ENA_OVR_O_K2_E5                                     (0x1<<1) // Beacon Override
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_AHB_BEACON_ENA_OVR_O_K2_E5_SHIFT                               1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_DEC_EN_OVR_O_K2_E5                                             (0x1<<2) // Enables 16b/20b decoder
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_DEC_EN_OVR_O_K2_E5_SHIFT                                       2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_ENC_EN_OVR_O_K2_E5                                             (0x1<<3) // Enables 16b/20b encoder
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_ENC_EN_OVR_O_K2_E5_SHIFT                                       3
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_REGP_OVR_3_0_K2_E5                                             (0xf<<4) // Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty  Bit[1]: Overide values for bit reverse  Bit[2]: Overide values for word reverse
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_REGP_OVR_3_0_K2_E5_SHIFT                                       4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X318_K2_E5                                                            0x0024f8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X318_SIGDET_OVR_O_1_0_K2_E5                                         (0x3<<0) // Bit[0]: Overide value. Bit[1] :Override enable for signal detect output
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X318_SIGDET_OVR_O_1_0_K2_E5_SHIFT                                   0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X318_LN_OUT_OVR_1_0_K2_E5                                           (0x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the override, while bit 0 is the override value.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X318_LN_OUT_OVR_1_0_K2_E5_SHIFT                                     2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X318_RXEQ_SIGDET_1_0_K2_E5                                          (0x3<<4) // Override enable for DFE signal detect indicator input. Bit 1 is overide enable , 0 is overide value
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X318_RXEQ_SIGDET_1_0_K2_E5_SHIFT                                    4
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X319_K2_E5                                                            0x0024fcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X319_TXDETECTRX_OVR_O_1_0_K2_E5                                     (0x3<<0) // Override signal for txdetectrx input - bit 1 is override enable, bit 0 is override value.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X319_TXDETECTRX_OVR_O_1_0_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X319_RXDET_STATUS_OVR_O_1_0_K2_E5                                   (0x3<<2) // Override signal for txdetectrx output - bit 1 is override enable, bit 0 is override value.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X319_RXDET_STATUS_OVR_O_1_0_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X319_LOCKED_OVR_O_1_0_K2_E5                                         (0x3<<4) // Override signal for symbol align locked output. Bit 1 is the override enable, and bit 0 is the override value.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X319_LOCKED_OVR_O_1_0_K2_E5_SHIFT                                   4
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O_K2_E5                         (0x1<<6) // override enable for tx_lowpwr_idle_ena output to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O_K2_E5_SHIFT                   6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_K2_E5                             (0x1<<7) // override value for tx_lowpwr_idle_ena output to PMA
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_K2_E5_SHIFT                       7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X320_K2_E5                                                            0x002500UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X321_K2_E5                                                            0x002504UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X322_K2_E5                                                            0x002508UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X323_K2_E5                                                            0x00250cUL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X324_K2_E5                                                            0x002510UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X325_K2_E5                                                            0x002514UL //Access:RW   DataWidth:0x8    // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_K2_E5                                                            0x002518UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_LN_IN_OVR_O_48_K2_E5                                           (0x1<<0) // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_LN_IN_OVR_O_48_K2_E5_SHIFT                                     0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_AHB_LN_IN_OVR_CHG_FLAG_O_K2_E5                                 (0x1<<1) // Flag to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1' before writing to the corresponding lnX_in_ovr_o_14_1 and set it back to '0' after the write. It is not needed for configuration writes.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_AHB_LN_IN_OVR_CHG_FLAG_O_K2_E5_SHIFT                           1
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_REGP1_OVR_O_3_0_K2_E5                                          (0xf<<2) // Overrides for polbit block polbit_regp1 Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty  Bit[1]: Overide values for bit reverse  Bit[2]: Overide values for word reverse
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_REGP1_OVR_O_3_0_K2_E5_SHIFT                                    2
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_OOB_DET_EN_K2_E5                                               (0x1<<6) // OOB detect enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_OOB_DET_EN_K2_E5_SHIFT                                         6
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_LN_IN_OVR_O_49_K2_E5                                           (0x1<<7) // OOB detect enable
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_LN_IN_OVR_O_49_K2_E5_SHIFT                                     7
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X327_K2_E5                                                            0x00251cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X327_CDR_CTRL_DLY_DLPF_EN_O_K2_E5                                   (0x1f<<0) // Delay between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0  R-platform requires 150ns delay
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X327_CDR_CTRL_DLY_DLPF_EN_O_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X330_K2_E5                                                            0x002528UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X330_MSM_LN_RATE_EXTRA_BITS_OVR_O_2_0_K2_E5                         (0x7<<0) // Override signals for lane: msm_ln_rate_ow[4:2]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X330_MSM_LN_RATE_EXTRA_BITS_OVR_O_2_0_K2_E5_SHIFT                   0
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X330_LN_IN_OVR_O_50_K2_E5                                           (0x1<<3) // Override signals for lane: msm_ln_rate_ow[4:2]
+  #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X330_LN_IN_OVR_O_50_K2_E5_SHIFT                                     3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X0_K2_E5                                                           0x002800UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X0_LN_CMUREF_EN_O_K2_E5                                          (0x1<<0) // Lane Reference Clock Enable.  0 - gcfsm_refmux_clk = pma_cm_ref_clk_i 1 - gcfsm_refmux_clk = lane_ref_clk
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X0_LN_CMUREF_EN_O_K2_E5_SHIFT                                    0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X1_K2_E5                                                           0x002804UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X1_BIST_CHK_INV_PRBS_O_K2_E5                                     (0x1<<0) // Enable/Disable the internal PRBS data pattern inverter. 0x0  Invert the PRBS data pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1  Not invert the PRBS data pattern for PRBS-31 and invert the PRBS data pattern for the other PRBS types.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X1_BIST_CHK_INV_PRBS_O_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X1_BIST_GEN_INV_PRBS_O_K2_E5                                     (0x1<<1) // Enable/Disable the internal PRBS data pattern inverter. 0x0  Invert the PRBS data pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1  Not invert the PRBS data pattern for PRBS-31 and invert the PRBS data pattern for the other PRBS types.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X1_BIST_GEN_INV_PRBS_O_K2_E5_SHIFT                               1
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X2_K2_E5                                                           0x002808UL //Access:RW   DataWidth:0x8    // BIST alignment pattern for Gen3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X3_K2_E5                                                           0x00280cUL //Access:RW   DataWidth:0x8    // BIST alignment pattern for Gen3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X4_K2_E5                                                           0x002810UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X4_P2S_RBUF_PTR_DIFF_O_2_0_K2_E5                                 (0x7<<0) // P2S ring buffer initial startup pointer difference.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X4_P2S_RBUF_PTR_DIFF_O_2_0_K2_E5_SHIFT                           0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X6_K2_E5                                                           0x002818UL //Access:RW   DataWidth:0x8    // Symbol aligner alignment word. Expects bit 0 received first
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X7_K2_E5                                                           0x00281cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X7_SYM_ALIGN_WORD_O_9_8_K2_E5                                    (0x3<<0) // Symbol aligner alignment word. Expects bit 0 received first
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X7_SYM_ALIGN_WORD_O_9_8_K2_E5_SHIFT                              0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X8_K2_E5                                                           0x002820UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X8_SYM_LOCK_NUM_O_3_0_K2_E5                                      (0xf<<0) // Number of properly aligned align words that must be detected
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X8_SYM_LOCK_NUM_O_3_0_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X8_SYM_UNLOCK_NUM_O_3_0_K2_E5                                    (0xf<<4) // Number of improperly aligned align words that must be detected
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X8_SYM_UNLOCK_NUM_O_3_0_K2_E5_SHIFT                              4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X9_K2_E5                                                           0x002824UL //Access:RW   DataWidth:0x8    // Block aligner skp end word
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X10_K2_E5                                                          0x002828UL //Access:RW   DataWidth:0x8    // The first 16 bits of an encoded EIEOS in Gen3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X11_K2_E5                                                          0x00282cUL //Access:RW   DataWidth:0x8    // The first 16 bits of an encoded EIEOS in Gen3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X12_K2_E5                                                          0x002830UL //Access:RW   DataWidth:0x8    // The remaining 16 bit words of an EIEOS in Gen3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X13_K2_E5                                                          0x002834UL //Access:RW   DataWidth:0x8    // The remaining 16 bit words of an EIEOS in Gen3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X14_K2_E5                                                          0x002838UL //Access:RW   DataWidth:0x8    // The first 16 bits of an encoded SDSOS in Gen3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X15_K2_E5                                                          0x00283cUL //Access:RW   DataWidth:0x8    // The first 16 bits of an encoded SDSOS in Gen3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X16_K2_E5                                                          0x002840UL //Access:RW   DataWidth:0x8    // The remaining 16 bit words of an SDSOS in Gen3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X17_K2_E5                                                          0x002844UL //Access:RW   DataWidth:0x8    // The remaining 16 bit words of an SDSOS in Gen3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X18_K2_E5                                                          0x002848UL //Access:RW   DataWidth:0x8    // The first 16 bits of an encoded SKPOS in Gen3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X19_K2_E5                                                          0x00284cUL //Access:RW   DataWidth:0x8    // The first 16 bits of an encoded SKPOS in Gen3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X20_K2_E5                                                          0x002850UL //Access:RW   DataWidth:0x8    // The remaining 16 bit words of a SKPOS in Gen3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X21_K2_E5                                                          0x002854UL //Access:RW   DataWidth:0x8    // The remaining 16 bit words of a SKPOS in Gen3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X22_K2_E5                                                          0x002858UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X22_SYNC_HDR_QUAL_EN_O_K2_E5                                     (0x1<<0) // Enables block_aligner skpos_hdr_det qualification
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X22_SYNC_HDR_QUAL_EN_O_K2_E5_SHIFT                               0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X23_K2_E5                                                          0x00285cUL //Access:RW   DataWidth:0x8    // Elastic buffer s0 [7:0]
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X24_K2_E5                                                          0x002860UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X24_EBUF_SYMB0_O_9_8_K2_E5                                       (0x3<<0) // Elastic buffer s0 [9:8]
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X24_EBUF_SYMB0_O_9_8_K2_E5_SHIFT                                 0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X25_K2_E5                                                          0x002864UL //Access:RW   DataWidth:0x8    // Elastic buffer s1 [7:0]
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X26_K2_E5                                                          0x002868UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X26_EBUF_SYMB1_O_9_8_K2_E5                                       (0x3<<0) // Elastic buffer s1 [9:8]
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X26_EBUF_SYMB1_O_9_8_K2_E5_SHIFT                                 0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X26_EBUF_EN_O_K2_E5                                              (0x1<<2) // Elastic buffer enable
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X26_EBUF_EN_O_K2_E5_SHIFT                                        2
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X29_K2_E5                                                          0x002874UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X29_EBUF_FIFO_MID_O_5_0_K2_E5                                    (0x3f<<0) // Elastic buffer FIFO mid thershold
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X29_EBUF_FIFO_MID_O_5_0_K2_E5_SHIFT                              0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X30_K2_E5                                                          0x002878UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X30_EBUF_FIFO_FULL_O_5_0_K2_E5                                   (0x3f<<0) // Elastic buffer FIFO full threshold
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X30_EBUF_FIFO_FULL_O_5_0_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X31_K2_E5                                                          0x00287cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X31_EBUF_FIFO_EMPTY_O_5_0_K2_E5                                  (0x3f<<0) // Elastic buffer FIFO empty threshold
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X31_EBUF_FIFO_EMPTY_O_5_0_K2_E5_SHIFT                            0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X32_K2_E5                                                          0x002880UL //Access:RW   DataWidth:0x8    // SKP symbol for PCIe Gen3 SKP OS ---8'hAA
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X33_K2_E5                                                          0x002884UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X33_EBUF_FIFO_ADD_O_5_0_K2_E5                                    (0x3f<<0) // SKP addition threshold value.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X33_EBUF_FIFO_ADD_O_5_0_K2_E5_SHIFT                              0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X34_K2_E5                                                          0x002888UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X34_EBUF_FIFO_RMV_O_5_0_K2_E5                                    (0x3f<<0) // SKP removal threshold value.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X34_EBUF_FIFO_RMV_O_5_0_K2_E5_SHIFT                              0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X35_K2_E5                                                          0x00288cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X35_EBUF_FIFO_DEPTH_O_5_0_K2_E5                                  (0x3f<<0) // FIFO read enable threshold value .
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X35_EBUF_FIFO_DEPTH_O_5_0_K2_E5_SHIFT                            0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X38_K2_E5                                                          0x002898UL //Access:RW   DataWidth:0x8    // 10-bit align symbol for ebuf during PIPE loopback [7:0]
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X39_K2_E5                                                          0x00289cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X39_S0_LB_P_O_9_8_K2_E5                                          (0x3<<0) // 10-bit align symbol for ebuf during PIPE loopback [9:8]
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X39_S0_LB_P_O_9_8_K2_E5_SHIFT                                    0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X40_K2_E5                                                          0x0028a0UL //Access:RW   DataWidth:0x8    // 10-bit align symbol for ebuf during PIPE loopback [7:0]
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X41_K2_E5                                                          0x0028a4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X41_S1_LB_P_O_9_8_K2_E5                                          (0x3<<0) // 10-bit align symbol for ebuf during PIPE loopback [9:8]
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X41_S1_LB_P_O_9_8_K2_E5_SHIFT                                    0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X43_K2_E5                                                          0x0028acUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X43_CDR_CTRL_DLPF_RAIL_RST_EN_O_K2_E5                            (0x1<<1) // Enable resetting of railed DLPF
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X43_CDR_CTRL_DLPF_RAIL_RST_EN_O_K2_E5_SHIFT                      1
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X44_K2_E5                                                          0x0028b0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_EN_O_K2_E5                       (0x1<<0) // Enable DOSC adjustement for railed DLPF
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_EN_O_K2_E5_SHIFT                 0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_VAL_O_K2_E5                      (0x1f<<1) // Default DOSC adjustement value for railed DLPF
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_VAL_O_K2_E5_SHIFT                1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_DIR_O_K2_E5                      (0x1<<6) // Default DOSC adjustement direction for railed DLPF
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_DIR_O_K2_E5_SHIFT                6
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X45_K2_E5                                                          0x0028b4UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X45_CPUCLK_DIV_LATCHED_I_1_0_K2_E5                               (0x3<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X45_CPUCLK_DIV_LATCHED_I_1_0_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X45_CPU_LOS_INT_EN_O_3_0_K2_E5                                   (0xf<<2) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X45_CPU_LOS_INT_EN_O_3_0_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X45_CPUCLK_DIV_O_1_0_K2_E5                                       (0x3<<6) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X45_CPUCLK_DIV_O_1_0_K2_E5_SHIFT                                 6
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X46_K2_E5                                                          0x0028b8UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X46_CPUCLK_DIV_OVRD_O_K2_E5                                      (0x1<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X46_CPUCLK_DIV_OVRD_O_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X46_CPUCLK_SEL_O_K2_E5                                           (0x1<<1) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X46_CPUCLK_SEL_O_K2_E5_SHIFT                                     1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X46_CPU_AHB_CK_RATIO_O_3_0_K2_E5                                 (0xf<<2) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X46_CPU_AHB_CK_RATIO_O_3_0_K2_E5_SHIFT                           2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X46_CPUCLK_EN_O_K2_E5                                            (0x1<<6) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X46_CPUCLK_EN_O_K2_E5_SHIFT                                      6
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X47_K2_E5                                                          0x0028bcUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X47_CPU_LOS_CHANGE_I_3_0_K2_E5                                   (0xf<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X47_CPU_LOS_CHANGE_I_3_0_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X47_CPU_LOS_NEW_I_3_0_K2_E5                                      (0xf<<4) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X47_CPU_LOS_NEW_I_3_0_K2_E5_SHIFT                                4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_K2_E5                                                          0x0028c0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_LOS_LN0_INTRPT_I_0_K2_E5                                     (0x1<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_LOS_LN0_INTRPT_I_0_K2_E5_SHIFT                               0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_LOS_LN1_INTRPT_I_1_K2_E5                                     (0x1<<1) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_LOS_LN1_INTRPT_I_1_K2_E5_SHIFT                               1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_LOS_LN2_INTRPT_I_2_K2_E5                                     (0x1<<2) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_LOS_LN2_INTRPT_I_2_K2_E5_SHIFT                               2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_LOS_LN3_INTRPT_I_3_K2_E5                                     (0x1<<3) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_LOS_LN3_INTRPT_I_3_K2_E5_SHIFT                               3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_K2_E5                                                          0x0028c4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_COUNTER_EN_O_K2_E5                                  (0x1<<0) // Enable eye scan counter
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_COUNTER_EN_O_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_RUN_O_K2_E5                                         (0x1<<1) // Run eye scan counter
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_RUN_O_K2_E5_SHIFT                                   1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_O_K2_E5                                       (0x1<<2) // Shift edge samples
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_O_K2_E5_SHIFT                                 2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_DIR_O_K2_E5                                   (0x1<<3) // Determines shift direction of edge samples
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_DIR_O_K2_E5_SHIFT                             3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_2BITS_O_K2_E5                                 (0x1<<4) // Shift edge samples by 2 bits
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_2BITS_O_K2_E5_SHIFT                           4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X50_K2_E5                                                          0x0028c8UL //Access:RW   DataWidth:0x8    // Mask eye scan results
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X51_K2_E5                                                          0x0028ccUL //Access:RW   DataWidth:0x8    // Mask eye scan results
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X52_K2_E5                                                          0x0028d0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X52_EYE_SCAN_MASK_O_18_16_K2_E5                                  (0x7<<0) // Mask eye scan results
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X52_EYE_SCAN_MASK_O_18_16_K2_E5_SHIFT                            0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X53_K2_E5                                                          0x0028d4UL //Access:RW   DataWidth:0x8    // Eye scan wait time
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X54_K2_E5                                                          0x0028d8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X54_EYE_SCAN_WAIT_LEN_O_11_8_K2_E5                               (0xf<<0) // Eye scan wait time
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X54_EYE_SCAN_WAIT_LEN_O_11_8_K2_E5_SHIFT                         0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X55_K2_E5                                                          0x0028dcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X55_GCFSM_DIV_EN_O_1_0_K2_E5                                     (0x3<<0) // Static divider control for Lane GCFSM clock The only access to this divider. Not an override 4d0:  No division  4d1:  /2 4d2:  /2 4d3:  /4:
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X55_GCFSM_DIV_EN_O_1_0_K2_E5_SHIFT                               0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X56_K2_E5                                                          0x0028e0UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 7-0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X57_K2_E5                                                          0x0028e4UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 15-8
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X58_K2_E5                                                          0x0028e8UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 23-16
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X59_K2_E5                                                          0x0028ecUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 31-24
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X60_K2_E5                                                          0x0028f0UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 39-32
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X61_K2_E5                                                          0x0028f4UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 47-40
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X62_K2_E5                                                          0x0028f8UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 55-48
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X63_K2_E5                                                          0x0028fcUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 63-56
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X64_K2_E5                                                          0x002900UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 71-64
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X65_K2_E5                                                          0x002904UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 79-72
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X66_K2_E5                                                          0x002908UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 87-80
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X67_K2_E5                                                          0x00290cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 95-88
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X68_K2_E5                                                          0x002910UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 103-96
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X69_K2_E5                                                          0x002914UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 111-104
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X70_K2_E5                                                          0x002918UL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 119-112
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X71_K2_E5                                                          0x00291cUL //Access:RW   DataWidth:0x8    // GCFSM Cycle Length Input bits 127-120
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X72_K2_E5                                                          0x002920UL //Access:RW   DataWidth:0x8    // GCFSM calibraton direction
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X73_K2_E5                                                          0x002924UL //Access:RW   DataWidth:0x8    // GCFSM calibraton direction
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X74_K2_E5                                                          0x002928UL //Access:RW   DataWidth:0x8    // Function info for each MSM function. Varies depending on function number.   Bits 15-7: Address of first command to run Bits: 6-0: Number of commands to run
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X75_K2_E5                                                          0x00292cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X76_K2_E5                                                          0x002930UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X77_K2_E5                                                          0x002934UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X78_K2_E5                                                          0x002938UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X79_K2_E5                                                          0x00293cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X80_K2_E5                                                          0x002940UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X81_K2_E5                                                          0x002944UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X82_K2_E5                                                          0x002948UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X83_K2_E5                                                          0x00294cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X84_K2_E5                                                          0x002950UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X85_K2_E5                                                          0x002954UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X86_K2_E5                                                          0x002958UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X87_K2_E5                                                          0x00295cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X88_K2_E5                                                          0x002960UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X89_K2_E5                                                          0x002964UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X90_K2_E5                                                          0x002968UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X91_K2_E5                                                          0x00296cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X92_K2_E5                                                          0x002970UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X93_K2_E5                                                          0x002974UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X94_K2_E5                                                          0x002978UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X95_K2_E5                                                          0x00297cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X96_K2_E5                                                          0x002980UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X97_K2_E5                                                          0x002984UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X98_K2_E5                                                          0x002988UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X99_K2_E5                                                          0x00298cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X100_K2_E5                                                         0x002990UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X101_K2_E5                                                         0x002994UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X102_K2_E5                                                         0x002998UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X103_K2_E5                                                         0x00299cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X104_K2_E5                                                         0x0029a0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X105_K2_E5                                                         0x0029a4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X106_K2_E5                                                         0x0029a8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X107_K2_E5                                                         0x0029acUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X108_K2_E5                                                         0x0029b0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X109_K2_E5                                                         0x0029b4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X110_K2_E5                                                         0x0029b8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X111_K2_E5                                                         0x0029bcUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X112_K2_E5                                                         0x0029c0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X113_K2_E5                                                         0x0029c4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X114_K2_E5                                                         0x0029c8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X115_K2_E5                                                         0x0029ccUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X116_K2_E5                                                         0x0029d0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X117_K2_E5                                                         0x0029d4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X118_K2_E5                                                         0x0029d8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X119_K2_E5                                                         0x0029dcUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X120_K2_E5                                                         0x0029e0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X121_K2_E5                                                         0x0029e4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X122_K2_E5                                                         0x0029e8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X123_K2_E5                                                         0x0029ecUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X124_K2_E5                                                         0x0029f0UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X125_K2_E5                                                         0x0029f4UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X126_K2_E5                                                         0x0029f8UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X127_K2_E5                                                         0x0029fcUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X128_K2_E5                                                         0x002a00UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X129_K2_E5                                                         0x002a04UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X130_K2_E5                                                         0x002a08UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X131_K2_E5                                                         0x002a0cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X132_K2_E5                                                         0x002a10UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X133_K2_E5                                                         0x002a14UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X134_K2_E5                                                         0x002a18UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X135_K2_E5                                                         0x002a1cUL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X136_K2_E5                                                         0x002a20UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X137_K2_E5                                                         0x002a24UL //Access:RW   DataWidth:0x8    // See description for msm_func_info_o_7_0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X138_K2_E5                                                         0x002a28UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X138_QAHB_MSM_PIPE_EN_PROG_TXDETECTRX_PULSE_O_K2_E5              (0x1<<0) // Enables programmable tx det rx pulse
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X138_QAHB_MSM_PIPE_EN_PROG_TXDETECTRX_PULSE_O_K2_E5_SHIFT        0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X139_K2_E5                                                         0x002a2cUL //Access:RW   DataWidth:0x8    // Programmable width of tx det rx pulse
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X140_K2_E5                                                         0x002a30UL //Access:RW   DataWidth:0x8    // Programmable width of tx det rx pulse
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X141_K2_E5                                                         0x002a34UL //Access:RW   DataWidth:0x8    // Delay for MFSM state transition from P2 to P1 in non-PIPE mode.  The MFSM waits for the analog cuircuity to recover from power-down. The actual delay is 4*<reference clock period	*<value of this register	.
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X142_K2_E5                                                         0x002a38UL //Access:RW   DataWidth:0x8    // Delay for MFSM state transition from P2 to P1 in non-PIPE mode.  The MFSM waits for the analog cuircuity to recover from power-down. The actual delay is 4*<reference clock period	*<value of this register	.
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_K2_E5                                                         0x002a3cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_IDDQ_SD_O_K2_E5                               (0x1<<0) // MSM Function IDDQ state's default value for iddq_sd in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_IDDQ_SD_O_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_DFE_O_K2_E5                                (0x1<<1) // MSM Function IDDQ state's default value for pd_dfe in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_DFE_O_K2_E5_SHIFT                          1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_DFE_BIAS_O_K2_E5                           (0x1<<2) // MSM Function IDDQ state's default value for pd_dfe_bias in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_DFE_BIAS_O_K2_E5_SHIFT                     2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_LNREG_O_K2_E5                              (0x1<<3) // MSM Function IDDQ state's default value for pd_lnreg in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_LNREG_O_K2_E5_SHIFT                        3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_LNREGH_O_K2_E5                             (0x1<<4) // MSM Function IDDQ state's default value for pd_lnregh in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_LNREGH_O_K2_E5_SHIFT                       4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_P2S_O_K2_E5                                (0x1<<5) // MSM Function IDDQ state's default value for pd_p2s in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_P2S_O_K2_E5_SHIFT                          5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_RA_O_K2_E5                                 (0x1<<6) // MSM Function IDDQ state's default value for pd_ra in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_RA_O_K2_E5_SHIFT                           6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_S2P_O_K2_E5                                (0x1<<7) // MSM Function IDDQ state's default value for pd_s2p in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_S2P_O_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_K2_E5                                                         0x002a40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_SLV_BIAS_O_K2_E5                           (0x1<<0) // MSM Function IDDQ state's default value for pd_slv_bias in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_SLV_BIAS_O_K2_E5_SHIFT                     0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_TXDRV_O_K2_E5                              (0x1<<1) // MSM Function IDDQ state's default value for pd_txdrv in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_TXDRV_O_K2_E5_SHIFT                        1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_TXREG_O_K2_E5                              (0x1<<2) // MSM Function IDDQ state's default value for pd_txreg in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_TXREG_O_K2_E5_SHIFT                        2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_VCO_O_K2_E5                                (0x1<<3) // MSM Function IDDQ state's default value for pd_vco in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_VCO_O_K2_E5_SHIFT                          3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_VCO_BUF_O_K2_E5                            (0x1<<4) // MSM Function IDDQ state's default value for pd_vco_buf in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_VCO_BUF_O_K2_E5_SHIFT                      4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_CDR_O_K2_E5                             (0x1<<5) // MSM Function IDDQ state's default value for reset_cdr in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_CDR_O_K2_E5_SHIFT                       5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_CDR_GCRX_O_K2_E5                        (0x1<<6) // MSM Function IDDQ state's default value for reset_cdr_gcrx in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_CDR_GCRX_O_K2_E5_SHIFT                  6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_DFE_O_K2_E5                             (0x1<<7) // MSM Function IDDQ state's default value for reset_dfe in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_DFE_O_K2_E5_SHIFT                       7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_K2_E5                                                         0x002a44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_LNREG_O_K2_E5                           (0x1<<0) // MSM Function IDDQ state's default value for reset_lnreg in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_LNREG_O_K2_E5_SHIFT                     0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_LNREGH_O_K2_E5                          (0x1<<1) // MSM Function IDDQ state's default value for reset_lnregh in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_LNREGH_O_K2_E5_SHIFT                    1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_P2S_O_K2_E5                             (0x1<<2) // MSM Function IDDQ state's default value for reset_p2s in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_P2S_O_K2_E5_SHIFT                       2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_RA_O_K2_E5                              (0x1<<3) // MSM Function IDDQ state's default value for reset_ra in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_RA_O_K2_E5_SHIFT                        3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_S2P_O_K2_E5                             (0x1<<4) // MSM Function IDDQ state's default value for reset_s2p in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_S2P_O_K2_E5_SHIFT                       4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_VCO_O_K2_E5                             (0x1<<5) // MSM Function IDDQ state's default value for reset_vco in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_VCO_O_K2_E5_SHIFT                       5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_TXREG_BLEED_ENA_O_K2_E5                       (0x1<<6) // MSM Function IDDQ state's default value for txreg_bleed_ena in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_TXREG_BLEED_ENA_O_K2_E5_SHIFT                 6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_TX_LOWPWR_IDLE_ENA_O_K2_E5                    (0x1<<7) // MSM Function IDDQ state's default value for tx_lowpwr_idle_ena in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT              7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_K2_E5                                                         0x002a48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_CDR_EN_O_K2_E5                                (0x1<<0) // MSM Function IDDQ state's default value for cdr_en in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_CDR_EN_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RXBCLK_EN_O_K2_E5                             (0x1<<1) // MSM Function IDDQ state's default value for rxbclk_en in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RXBCLK_EN_O_K2_E5_SHIFT                       1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RX_GATE_EN_O_K2_E5                            (0x1<<2) // MSM Function IDDQ state's default value for rx_gate_en in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RX_GATE_EN_O_K2_E5_SHIFT                      2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RESET_TX_CLKDIV_O_K2_E5                       (0x1<<3) // MSM Function IDDQ state's default value for reset_tx_clkdiv in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RESET_TX_CLKDIV_O_K2_E5_SHIFT                 3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_K2_E5                                                         0x002a4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_IDDQ_SD_O_K2_E5                                (0x1<<0) // MSM Function RESET state's default value for iddq_sd in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_IDDQ_SD_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_DFE_O_K2_E5                                 (0x1<<1) // MSM Function RESET state's default value for pd_dfe in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_DFE_O_K2_E5_SHIFT                           1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_DFE_BIAS_O_K2_E5                            (0x1<<2) // MSM Function RESET state's default value for pd_dfe_bias in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_DFE_BIAS_O_K2_E5_SHIFT                      2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_LNREG_O_K2_E5                               (0x1<<3) // MSM Function RESET state's default value for pd_lnreg in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_LNREG_O_K2_E5_SHIFT                         3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_LNREGH_O_K2_E5                              (0x1<<4) // MSM Function RESET state's default value for pd_lnregh in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_LNREGH_O_K2_E5_SHIFT                        4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_P2S_O_K2_E5                                 (0x1<<5) // MSM Function RESET state's default value for pd_p2s in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_P2S_O_K2_E5_SHIFT                           5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_RA_O_K2_E5                                  (0x1<<6) // MSM Function RESET state's default value for pd_ra in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_RA_O_K2_E5_SHIFT                            6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_S2P_O_K2_E5                                 (0x1<<7) // MSM Function RESET state's default value for pd_s2p in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_S2P_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_K2_E5                                                         0x002a50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_SLV_BIAS_O_K2_E5                            (0x1<<0) // MSM Function RESET state's default value for pd_slv_bias in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_SLV_BIAS_O_K2_E5_SHIFT                      0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_TXDRV_O_K2_E5                               (0x1<<1) // MSM Function RESET state's default value for pd_txdrv in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_TXDRV_O_K2_E5_SHIFT                         1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_TXREG_O_K2_E5                               (0x1<<2) // MSM Function RESET state's default value for pd_txreg in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_TXREG_O_K2_E5_SHIFT                         2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_VCO_O_K2_E5                                 (0x1<<3) // MSM Function RESET state's default value for pd_vco in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_VCO_O_K2_E5_SHIFT                           3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_VCO_BUF_O_K2_E5                             (0x1<<4) // MSM Function RESET state's default value for pd_vco_buf in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_VCO_BUF_O_K2_E5_SHIFT                       4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_CDR_O_K2_E5                              (0x1<<5) // MSM Function RESET state's default value for reset_cdr in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_CDR_O_K2_E5_SHIFT                        5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_CDR_GCRX_O_K2_E5                         (0x1<<6) // MSM Function RESET state's default value for reset_cdr_gcrx in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_CDR_GCRX_O_K2_E5_SHIFT                   6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_DFE_O_K2_E5                              (0x1<<7) // MSM Function RESET state's default value for reset_dfe in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_DFE_O_K2_E5_SHIFT                        7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_K2_E5                                                         0x002a54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_LNREG_O_K2_E5                            (0x1<<0) // MSM Function RESET state's default value for reset_lnreg in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_LNREG_O_K2_E5_SHIFT                      0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_LNREGH_O_K2_E5                           (0x1<<1) // MSM Function RESET state's default value for reset_lnregh in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_LNREGH_O_K2_E5_SHIFT                     1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_P2S_O_K2_E5                              (0x1<<2) // MSM Function RESET state's default value for reset_p2s in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_P2S_O_K2_E5_SHIFT                        2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_RA_O_K2_E5                               (0x1<<3) // MSM Function RESET state's default value for reset_ra in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_RA_O_K2_E5_SHIFT                         3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_S2P_O_K2_E5                              (0x1<<4) // MSM Function RESET state's default value for reset_s2p in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_S2P_O_K2_E5_SHIFT                        4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_VCO_O_K2_E5                              (0x1<<5) // MSM Function RESET state's default value for reset_vco in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_VCO_O_K2_E5_SHIFT                        5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_TXREG_BLEED_ENA_O_K2_E5                        (0x1<<6) // MSM Function RESET state's default value for txreg_bleed_ena in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_TXREG_BLEED_ENA_O_K2_E5_SHIFT                  6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_TX_LOWPWR_IDLE_ENA_O_K2_E5                     (0x1<<7) // MSM Function RESET state's default value for tx_lowpwr_idle_ena in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT               7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_K2_E5                                                         0x002a58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_CDR_EN_O_K2_E5                                 (0x1<<0) // MSM Function RESET state's default value for cdr_en in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_CDR_EN_O_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RXBCLK_EN_O_K2_E5                              (0x1<<1) // MSM Function RESET state's default value for rxbclk_en in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RXBCLK_EN_O_K2_E5_SHIFT                        1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RX_GATE_EN_O_K2_E5                             (0x1<<2) // MSM Function RESET state's default value for rx_gate_en in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RX_GATE_EN_O_K2_E5_SHIFT                       2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RESET_TX_CLKDIV_O_K2_E5                        (0x1<<3) // MSM Function RESET state's default value for reset_tx_clkdiv in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RESET_TX_CLKDIV_O_K2_E5_SHIFT                  3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_K2_E5                                                         0x002a5cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_IDDQ_SD_O_K2_E5                               (0x1<<0) // MSM Function NORMAL state's default value for iddq_sd in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_IDDQ_SD_O_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_DFE_O_K2_E5                                (0x1<<1) // MSM Function NORMAL state's default value for pd_dfe in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_DFE_O_K2_E5_SHIFT                          1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_DFE_BIAS_O_K2_E5                           (0x1<<2) // MSM Function NORMAL state's default value for pd_dfe_bias in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_DFE_BIAS_O_K2_E5_SHIFT                     2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_LNREG_O_K2_E5                              (0x1<<3) // MSM Function NORMAL state's default value for pd_lnreg in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_LNREG_O_K2_E5_SHIFT                        3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_LNREGH_O_K2_E5                             (0x1<<4) // MSM Function NORMAL state's default value for pd_lnregh in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_LNREGH_O_K2_E5_SHIFT                       4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_P2S_O_K2_E5                                (0x1<<5) // MSM Function NORMAL state's default value for pd_p2s in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_P2S_O_K2_E5_SHIFT                          5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_RA_O_K2_E5                                 (0x1<<6) // MSM Function NORMAL state's default value for pd_ra in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_RA_O_K2_E5_SHIFT                           6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_S2P_O_K2_E5                                (0x1<<7) // MSM Function NORMAL state's default value for pd_s2p in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_S2P_O_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_K2_E5                                                         0x002a60UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_SLV_BIAS_O_K2_E5                           (0x1<<0) // MSM Function NORMAL state's default value for pd_slv_bias in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_SLV_BIAS_O_K2_E5_SHIFT                     0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_TXDRV_O_K2_E5                              (0x1<<1) // MSM Function NORMAL state's default value for pd_txdrv in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_TXDRV_O_K2_E5_SHIFT                        1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_TXREG_O_K2_E5                              (0x1<<2) // MSM Function NORMAL state's default value for pd_txreg in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_TXREG_O_K2_E5_SHIFT                        2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_VCO_O_K2_E5                                (0x1<<3) // MSM Function NORMAL state's default value for pd_vco in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_VCO_O_K2_E5_SHIFT                          3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_VCO_BUF_O_K2_E5                            (0x1<<4) // MSM Function NORMAL state's default value for pd_vco_buf in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_VCO_BUF_O_K2_E5_SHIFT                      4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_CDR_O_K2_E5                             (0x1<<5) // MSM Function NORMAL state's default value for reset_cdr in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_CDR_O_K2_E5_SHIFT                       5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_CDR_GCRX_O_K2_E5                        (0x1<<6) // MSM Function NORMAL state's default value for reset_cdr_gcrx in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_CDR_GCRX_O_K2_E5_SHIFT                  6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_DFE_O_K2_E5                             (0x1<<7) // MSM Function NORMAL state's default value for reset_dfe in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_DFE_O_K2_E5_SHIFT                       7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_K2_E5                                                         0x002a64UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_LNREG_O_K2_E5                           (0x1<<0) // MSM Function NORMAL state's default value for reset_lnreg in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_LNREG_O_K2_E5_SHIFT                     0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_LNREGH_O_K2_E5                          (0x1<<1) // MSM Function NORMAL state's default value for reset_lnregh in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_LNREGH_O_K2_E5_SHIFT                    1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_P2S_O_K2_E5                             (0x1<<2) // MSM Function NORMAL state's default value for reset_p2s in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_P2S_O_K2_E5_SHIFT                       2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_RA_O_K2_E5                              (0x1<<3) // MSM Function NORMAL state's default value for reset_ra in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_RA_O_K2_E5_SHIFT                        3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_S2P_O_K2_E5                             (0x1<<4) // MSM Function NORMAL state's default value for reset_s2p in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_S2P_O_K2_E5_SHIFT                       4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_VCO_O_K2_E5                             (0x1<<5) // MSM Function NORMAL state's default value for reset_vco in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_VCO_O_K2_E5_SHIFT                       5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_TXREG_BLEED_ENA_O_K2_E5                       (0x1<<6) // MSM Function NORMAL state's default value for txreg_bleed_ena in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_TXREG_BLEED_ENA_O_K2_E5_SHIFT                 6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_TX_LOWPWR_IDLE_ENA_O_K2_E5                    (0x1<<7) // MSM Function NORMAL state's default value for tx_lowpwr_idle_ena in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT              7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_K2_E5                                                         0x002a68UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_CDR_EN_O_K2_E5                                (0x1<<0) // MSM Function NORMAL state's default value for cdr_en in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_CDR_EN_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RXBCLK_EN_O_K2_E5                             (0x1<<1) // MSM Function NORMAL state's default value for rxbclk_en in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RXBCLK_EN_O_K2_E5_SHIFT                       1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RX_GATE_EN_O_K2_E5                            (0x1<<2) // MSM Function NORMAL state's default value for rx_gate_en in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RX_GATE_EN_O_K2_E5_SHIFT                      2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RESET_TX_CLKDIV_O_K2_E5                       (0x1<<3) // MSM Function NORMAL state's default value for reset_tx_clkdiv in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RESET_TX_CLKDIV_O_K2_E5_SHIFT                 3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_K2_E5                                                         0x002a6cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_IDDQ_SD_O_K2_E5                            (0x1<<0) // MSM Function PARTIAL state's default value for iddq_sd in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_IDDQ_SD_O_K2_E5_SHIFT                      0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_DFE_O_K2_E5                             (0x1<<1) // MSM Function PARTIAL state's default value for pd_dfe in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_DFE_O_K2_E5_SHIFT                       1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_DFE_BIAS_O_K2_E5                        (0x1<<2) // MSM Function PARTIAL state's default value for pd_dfe_bias in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_DFE_BIAS_O_K2_E5_SHIFT                  2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_LNREG_O_K2_E5                           (0x1<<3) // MSM Function PARTIAL state's default value for pd_lnreg in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_LNREG_O_K2_E5_SHIFT                     3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_LNREGH_O_K2_E5                          (0x1<<4) // MSM Function PARTIAL state's default value for pd_lnregh in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_LNREGH_O_K2_E5_SHIFT                    4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_P2S_O_K2_E5                             (0x1<<5) // MSM Function PARTIAL state's default value for pd_p2s in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_P2S_O_K2_E5_SHIFT                       5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_RA_O_K2_E5                              (0x1<<6) // MSM Function PARTIAL state's default value for pd_ra in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_RA_O_K2_E5_SHIFT                        6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_S2P_O_K2_E5                             (0x1<<7) // MSM Function PARTIAL state's default value for pd_s2p in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_S2P_O_K2_E5_SHIFT                       7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_K2_E5                                                         0x002a70UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_SLV_BIAS_O_K2_E5                        (0x1<<0) // MSM Function PARTIAL state's default value for pd_slv_bias in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_SLV_BIAS_O_K2_E5_SHIFT                  0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_TXDRV_O_K2_E5                           (0x1<<1) // MSM Function PARTIAL state's default value for pd_txdrv in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_TXDRV_O_K2_E5_SHIFT                     1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_TXREG_O_K2_E5                           (0x1<<2) // MSM Function PARTIAL state's default value for pd_txreg in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_TXREG_O_K2_E5_SHIFT                     2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_VCO_O_K2_E5                             (0x1<<3) // MSM Function PARTIAL state's default value for pd_vco in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_VCO_O_K2_E5_SHIFT                       3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_VCO_BUF_O_K2_E5                         (0x1<<4) // MSM Function PARTIAL state's default value for pd_vco_buf in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_VCO_BUF_O_K2_E5_SHIFT                   4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_CDR_O_K2_E5                          (0x1<<5) // MSM Function PARTIAL state's default value for reset_cdr in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_CDR_O_K2_E5_SHIFT                    5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_CDR_GCRX_O_K2_E5                     (0x1<<6) // MSM Function PARTIAL state's default value for reset_cdr_gcrx in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_CDR_GCRX_O_K2_E5_SHIFT               6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_DFE_O_K2_E5                          (0x1<<7) // MSM Function PARTIAL state's default value for reset_dfe in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_DFE_O_K2_E5_SHIFT                    7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_K2_E5                                                         0x002a74UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_LNREG_O_K2_E5                        (0x1<<0) // MSM Function PARTIAL state's default value for reset_lnreg in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_LNREG_O_K2_E5_SHIFT                  0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_LNREGH_O_K2_E5                       (0x1<<1) // MSM Function PARTIAL state's default value for reset_lnregh in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_LNREGH_O_K2_E5_SHIFT                 1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_P2S_O_K2_E5                          (0x1<<2) // MSM Function PARTIAL state's default value for reset_p2s in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_P2S_O_K2_E5_SHIFT                    2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_RA_O_K2_E5                           (0x1<<3) // MSM Function PARTIAL state's default value for reset_ra in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_RA_O_K2_E5_SHIFT                     3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_S2P_O_K2_E5                          (0x1<<4) // MSM Function PARTIAL state's default value for reset_s2p in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_S2P_O_K2_E5_SHIFT                    4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_VCO_O_K2_E5                          (0x1<<5) // MSM Function PARTIAL state's default value for reset_vco in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_VCO_O_K2_E5_SHIFT                    5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_TXREG_BLEED_ENA_O_K2_E5                    (0x1<<6) // MSM Function PARTIAL state's default value for txreg_bleed_ena in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_TXREG_BLEED_ENA_O_K2_E5_SHIFT              6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_TX_LOWPWR_IDLE_ENA_O_K2_E5                 (0x1<<7) // MSM Function PARTIAL state's default value for tx_lowpwr_idle_ena in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT           7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_K2_E5                                                         0x002a78UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_CDR_EN_O_K2_E5                             (0x1<<0) // MSM Function PARTIAL state's default value for cdr_en in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_CDR_EN_O_K2_E5_SHIFT                       0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RXBCLK_EN_O_K2_E5                          (0x1<<1) // MSM Function PARTIAL state's default value for rxbclk_en in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RXBCLK_EN_O_K2_E5_SHIFT                    1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RX_GATE_EN_O_K2_E5                         (0x1<<2) // MSM Function PARTIAL state's default value for rx_gate_en in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RX_GATE_EN_O_K2_E5_SHIFT                   2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RESET_TX_CLKDIV_O_K2_E5                    (0x1<<3) // MSM Function PARTIAL state's default value for reset_tx_clkdiv in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RESET_TX_CLKDIV_O_K2_E5_SHIFT              3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_K2_E5                                                         0x002a7cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_IDDQ_SD_O_K2_E5                            (0x1<<0) // MSM Function SLUMBER state's default value for iddq_sd in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_IDDQ_SD_O_K2_E5_SHIFT                      0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_DFE_O_K2_E5                             (0x1<<1) // MSM Function SLUMBER state's default value for pd_dfe in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_DFE_O_K2_E5_SHIFT                       1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_DFE_BIAS_O_K2_E5                        (0x1<<2) // MSM Function SLUMBER state's default value for pd_dfe_bias in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_DFE_BIAS_O_K2_E5_SHIFT                  2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_LNREG_O_K2_E5                           (0x1<<3) // MSM Function SLUMBER state's default value for pd_lnreg in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_LNREG_O_K2_E5_SHIFT                     3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_LNREGH_O_K2_E5                          (0x1<<4) // MSM Function SLUMBER state's default value for pd_lnregh in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_LNREGH_O_K2_E5_SHIFT                    4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_P2S_O_K2_E5                             (0x1<<5) // MSM Function SLUMBER state's default value for pd_p2s in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_P2S_O_K2_E5_SHIFT                       5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_RA_O_K2_E5                              (0x1<<6) // MSM Function SLUMBER state's default value for pd_ra in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_RA_O_K2_E5_SHIFT                        6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_S2P_O_K2_E5                             (0x1<<7) // MSM Function SLUMBER state's default value for pd_s2p in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_S2P_O_K2_E5_SHIFT                       7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_K2_E5                                                         0x002a80UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_SLV_BIAS_O_K2_E5                        (0x1<<0) // MSM Function SLUMBER state's default value for pd_slv_bias in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_SLV_BIAS_O_K2_E5_SHIFT                  0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_TXDRV_O_K2_E5                           (0x1<<1) // MSM Function SLUMBER state's default value for pd_txdrv in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_TXDRV_O_K2_E5_SHIFT                     1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_TXREG_O_K2_E5                           (0x1<<2) // MSM Function SLUMBER state's default value for pd_txreg in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_TXREG_O_K2_E5_SHIFT                     2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_VCO_O_K2_E5                             (0x1<<3) // MSM Function SLUMBER state's default value for pd_vco in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_VCO_O_K2_E5_SHIFT                       3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_VCO_BUF_O_K2_E5                         (0x1<<4) // MSM Function SLUMBER state's default value for pd_vco_buf in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_VCO_BUF_O_K2_E5_SHIFT                   4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_CDR_O_K2_E5                          (0x1<<5) // MSM Function SLUMBER state's default value for reset_cdr in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_CDR_O_K2_E5_SHIFT                    5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_CDR_GCRX_O_K2_E5                     (0x1<<6) // MSM Function SLUMBER state's default value for reset_cdr_gcrx in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_CDR_GCRX_O_K2_E5_SHIFT               6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_DFE_O_K2_E5                          (0x1<<7) // MSM Function SLUMBER state's default value for reset_dfe in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_DFE_O_K2_E5_SHIFT                    7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_K2_E5                                                         0x002a84UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_LNREG_O_K2_E5                        (0x1<<0) // MSM Function SLUMBER state's default value for reset_lnreg in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_LNREG_O_K2_E5_SHIFT                  0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_LNREGH_O_K2_E5                       (0x1<<1) // MSM Function SLUMBER state's default value for reset_lnregh in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_LNREGH_O_K2_E5_SHIFT                 1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_P2S_O_K2_E5                          (0x1<<2) // MSM Function SLUMBER state's default value for reset_p2s in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_P2S_O_K2_E5_SHIFT                    2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_RA_O_K2_E5                           (0x1<<3) // MSM Function SLUMBER state's default value for reset_ra in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_RA_O_K2_E5_SHIFT                     3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_S2P_O_K2_E5                          (0x1<<4) // MSM Function SLUMBER state's default value for reset_s2p in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_S2P_O_K2_E5_SHIFT                    4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_VCO_O_K2_E5                          (0x1<<5) // MSM Function SLUMBER state's default value for reset_vco in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_VCO_O_K2_E5_SHIFT                    5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_TXREG_BLEED_ENA_O_K2_E5                    (0x1<<6) // MSM Function SLUMBER state's default value for txreg_bleed_ena in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_TXREG_BLEED_ENA_O_K2_E5_SHIFT              6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_TX_LOWPWR_IDLE_ENA_O_K2_E5                 (0x1<<7) // MSM Function SLUMBER state's default value for tx_lowpwr_idle_ena in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT           7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_K2_E5                                                         0x002a88UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_CDR_EN_O_K2_E5                             (0x1<<0) // MSM Function SLUMBER state's default value for cdr_en in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_CDR_EN_O_K2_E5_SHIFT                       0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RXBCLK_EN_O_K2_E5                          (0x1<<1) // MSM Function SLUMBER state's default value for rxbclk_en in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RXBCLK_EN_O_K2_E5_SHIFT                    1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RX_GATE_EN_O_K2_E5                         (0x1<<2) // MSM Function SLUMBER state's default value for rx_gate_en in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RX_GATE_EN_O_K2_E5_SHIFT                   2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RESET_TX_CLKDIV_O_K2_E5                    (0x1<<3) // MSM Function SLUMBER state's default value for reset_tx_clkdiv in SAPIS mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RESET_TX_CLKDIV_O_K2_E5_SHIFT              3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X168_K2_E5                                                         0x002aa0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X168_OOB_DET_BLEN_MIN_O_6_0_K2_E5                                (0x7f<<0) // OOB detector minimum burst length.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X168_OOB_DET_BLEN_MIN_O_6_0_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X169_K2_E5                                                         0x002aa4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X169_OOB_DET_BLEN_MAX_O_6_0_K2_E5                                (0x7f<<0) // OOB detector maximum burst length.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X169_OOB_DET_BLEN_MAX_O_6_0_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X170_K2_E5                                                         0x002aa8UL //Access:RW   DataWidth:0x8    // OOB detector COMINIT maximum idle length.
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X171_K2_E5                                                         0x002aacUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X171_OOB_DET_COMINIT_MIN_O_8_K2_E5                               (0x1<<0) // OOB detector COMINIT maximum idle length.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X171_OOB_DET_COMINIT_MIN_O_8_K2_E5_SHIFT                         0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X172_K2_E5                                                         0x002ab0UL //Access:RW   DataWidth:0x8    // OOB detector COMINIT maximum idle length.
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X173_K2_E5                                                         0x002ab4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X173_OOB_DET_COMINIT_MAX_O_8_K2_E5                               (0x1<<0) // OOB detector COMINIT maximum idle length.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X173_OOB_DET_COMINIT_MAX_O_8_K2_E5_SHIFT                         0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X174_K2_E5                                                         0x002ab8UL //Access:RW   DataWidth:0x8    // OOB detector COMWAKE minimum idle length.
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X175_K2_E5                                                         0x002abcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X175_OOB_DET_COMWAKE_MIN_O_8_K2_E5                               (0x1<<0) // OOB detector COMWAKE minimum idle length.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X175_OOB_DET_COMWAKE_MIN_O_8_K2_E5_SHIFT                         0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X176_K2_E5                                                         0x002ac0UL //Access:RW   DataWidth:0x8    // OOB detector COMWAKE maximum idle length.
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X177_K2_E5                                                         0x002ac4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X177_OOB_DET_COMWAKE_MAX_O_8_K2_E5                               (0x1<<0) // OOB detector COMWAKE maximum idle length.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X177_OOB_DET_COMWAKE_MAX_O_8_K2_E5_SHIFT                         0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X178_K2_E5                                                         0x002ac8UL //Access:RW   DataWidth:0x8    // OOB detector COMSAS maximum idle length.
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X179_K2_E5                                                         0x002accUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X179_OOB_DET_COMSAS_MIN_O_8_K2_E5                                (0x1<<0) // OOB detector COMSAS maximum idle length.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X179_OOB_DET_COMSAS_MIN_O_8_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X180_K2_E5                                                         0x002ad0UL //Access:RW   DataWidth:0x8    // OOB detector COMSAS maximum idle length.
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X181_K2_E5                                                         0x002ad4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X181_OOB_DET_COMSAS_MAX_O_8_K2_E5                                (0x1<<0) // OOB detector COMSAS maximum idle length.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X181_OOB_DET_COMSAS_MAX_O_8_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X182_K2_E5                                                         0x002ad8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X182_TXCTRL_FASTCAP_3_0_K2_E5                                    (0xf<<0) // TX fastcap slew rate adjust
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X182_TXCTRL_FASTCAP_3_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X182_TXCTRL_FASTCAP_OVR_3_0_K2_E5                                (0xf<<4) // Override  value for Fastcap.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X182_TXCTRL_FASTCAP_OVR_3_0_K2_E5_SHIFT                          4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X183_K2_E5                                                         0x002adcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X183_TXCTRL_RATE1_TX_SR_DAC_3_0_K2_E5                            (0xf<<0) // TX rate1 slew rate DAC setting
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X183_TXCTRL_RATE1_TX_SR_DAC_3_0_K2_E5_SHIFT                      0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X183_TXCTRL_RATE2_TX_SR_DAC_3_0_K2_E5                            (0xf<<4) // TX rate2 slew rate DAC setting
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X183_TXCTRL_RATE2_TX_SR_DAC_3_0_K2_E5_SHIFT                      4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X184_K2_E5                                                         0x002ae0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X184_TXCTRL_RATE3_TX_SR_DAC_3_0_K2_E5                            (0xf<<0) // TX rate3 slew rate DAC setting
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X184_TXCTRL_RATE3_TX_SR_DAC_3_0_K2_E5_SHIFT                      0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X184_TXCTRL_MASTER_TX_SR_DAC_OVR_3_0_K2_E5                       (0xf<<4) // TX master slew rate DAC overrides
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X184_TXCTRL_MASTER_TX_SR_DAC_OVR_3_0_K2_E5_SHIFT                 4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X185_K2_E5                                                         0x002ae4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X185_TXCTRL_RATE1_TXEQ_POLARITY_3_0_K2_E5                        (0xf<<0) // TX rate1 coefficent polarity
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X185_TXCTRL_RATE1_TXEQ_POLARITY_3_0_K2_E5_SHIFT                  0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X185_TXCTRL_RATE2_TXEQ_POLARITY_3_0_K2_E5                        (0xf<<4) // TX rate2 coefficent polarity
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X185_TXCTRL_RATE2_TXEQ_POLARITY_3_0_K2_E5_SHIFT                  4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X186_K2_E5                                                         0x002ae8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X186_TXCTRL_RATE3_TXEQ_POLARITY_3_0_K2_E5                        (0xf<<0) // TX rate3 coefficent polarity
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X186_TXCTRL_RATE3_TXEQ_POLARITY_3_0_K2_E5_SHIFT                  0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X186_TXCTRL_MASTER_TXEQ_POLARITY_OVR_3_0_K2_E5                   (0xf<<4) // TX master coefficient polarity overrides.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X186_TXCTRL_MASTER_TXEQ_POLARITY_OVR_3_0_K2_E5_SHIFT             4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X187_K2_E5                                                         0x002aecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X187_TXCTRL_TX_MARGIN_000_LOWSWG_ATT_IN_RATE12_3_0_K2_E5         (0xf<<0) // PIPE tx_margin low swing setting
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X187_TXCTRL_TX_MARGIN_000_LOWSWG_ATT_IN_RATE12_3_0_K2_E5_SHIFT   0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X187_TXCTRL_TX_MARGIN_001_LOWSWG_ATT_IN_RATE12_3_0_K2_E5         (0xf<<4) // PIPE tx_margin low swing setting
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X187_TXCTRL_TX_MARGIN_001_LOWSWG_ATT_IN_RATE12_3_0_K2_E5_SHIFT   4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X188_K2_E5                                                         0x002af0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X188_TXCTRL_TX_MARGIN_010_LOWSWG_ATT_IN_RATE12_3_0_K2_E5         (0xf<<0) // PIPE tx_margin low swing setting
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X188_TXCTRL_TX_MARGIN_010_LOWSWG_ATT_IN_RATE12_3_0_K2_E5_SHIFT   0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X188_TXCTRL_TX_MARGIN_011_LOWSWG_ATT_IN_RATE12_3_0_K2_E5         (0xf<<4) // PIPE tx_margin low swing setting
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X188_TXCTRL_TX_MARGIN_011_LOWSWG_ATT_IN_RATE12_3_0_K2_E5_SHIFT   4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X189_K2_E5                                                         0x002af4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X189_TXCTRL_TX_MARGIN_100_LOWSWG_ATT_IN_RATE12_3_0_K2_E5         (0xf<<0) // PIPE tx_margin low swing setting
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X189_TXCTRL_TX_MARGIN_100_LOWSWG_ATT_IN_RATE12_3_0_K2_E5_SHIFT   0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X189_TXCTRL_TX_MARGIN_101_LOWSWG_ATT_IN_RATE12_3_0_K2_E5         (0xf<<4) // PIPE tx_margin low swing setting
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X189_TXCTRL_TX_MARGIN_101_LOWSWG_ATT_IN_RATE12_3_0_K2_E5_SHIFT   4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X190_K2_E5                                                         0x002af8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X190_TXCTRL_TX_MARGIN_110_LOWSWG_ATT_IN_RATE12_3_0_K2_E5         (0xf<<0) // PIPE tx_margin low swing setting
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X190_TXCTRL_TX_MARGIN_110_LOWSWG_ATT_IN_RATE12_3_0_K2_E5_SHIFT   0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X190_TXCTRL_TX_MARGIN_111_LOWSWG_ATT_IN_RATE12_3_0_K2_E5         (0xf<<4) // PIPE tx_margin low swing setting
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X190_TXCTRL_TX_MARGIN_111_LOWSWG_ATT_IN_RATE12_3_0_K2_E5_SHIFT   4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X191_K2_E5                                                         0x002afcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X191_TXCTRL_TX_MARGIN_000_FULLSWG_ATT_IN_RATE12_3_0_K2_E5        (0xf<<0) // PIPE tx_margin full swing setting
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X191_TXCTRL_TX_MARGIN_000_FULLSWG_ATT_IN_RATE12_3_0_K2_E5_SHIFT  0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X191_TXCTRL_TX_MARGIN_001_FULLSWG_ATT_IN_RATE12_3_0_K2_E5        (0xf<<4) // PIPE tx_margin full swing setting
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X191_TXCTRL_TX_MARGIN_001_FULLSWG_ATT_IN_RATE12_3_0_K2_E5_SHIFT  4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X192_K2_E5                                                         0x002b00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X192_TXCTRL_TX_MARGIN_010_FULLSWG_ATT_IN_RATE12_3_0_K2_E5        (0xf<<0) // PIPE tx_margin full swing setting
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X192_TXCTRL_TX_MARGIN_010_FULLSWG_ATT_IN_RATE12_3_0_K2_E5_SHIFT  0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X192_TXCTRL_TX_MARGIN_011_FULLSWG_ATT_IN_RATE12_3_0_K2_E5        (0xf<<4) // PIPE tx_margin full swing setting
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X192_TXCTRL_TX_MARGIN_011_FULLSWG_ATT_IN_RATE12_3_0_K2_E5_SHIFT  4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X193_K2_E5                                                         0x002b04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X193_TXCTRL_TX_MARGIN_100_FULLSWG_ATT_IN_RATE12_3_0_K2_E5        (0xf<<0) // PIPE tx_margin full swing setting
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X193_TXCTRL_TX_MARGIN_100_FULLSWG_ATT_IN_RATE12_3_0_K2_E5_SHIFT  0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X193_TXCTRL_TX_MARGIN_101_FULLSWG_ATT_IN_RATE12_3_0_K2_E5        (0xf<<4) // PIPE tx_margin full swing setting
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X193_TXCTRL_TX_MARGIN_101_FULLSWG_ATT_IN_RATE12_3_0_K2_E5_SHIFT  4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X194_K2_E5                                                         0x002b08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X194_TXCTRL_TX_MARGIN_110_FULLSWG_ATT_IN_RATE12_3_0_K2_E5        (0xf<<0) // PIPE tx_margin full swing setting
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X194_TXCTRL_TX_MARGIN_110_FULLSWG_ATT_IN_RATE12_3_0_K2_E5_SHIFT  0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X194_TXCTRL_TX_MARGIN_111_FULLSWG_ATT_IN_RATE12_3_0_K2_E5        (0xf<<4) // PIPE tx_margin full swing setting
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X194_TXCTRL_TX_MARGIN_111_FULLSWG_ATT_IN_RATE12_3_0_K2_E5_SHIFT  4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X195_K2_E5                                                         0x002b0cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X195_TXCTRL_MASTER_ATT_IN_OVR_3_0_K2_E5                          (0xf<<0) // Override  value for att in.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X195_TXCTRL_MASTER_ATT_IN_OVR_3_0_K2_E5_SHIFT                    0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X196_K2_E5                                                         0x002b10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X196_TXCTRL_RATE1_TX_SLEW_SLD_1_0_K2_E5                          (0x3<<0) // TX rate1 slew rate setting
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X196_TXCTRL_RATE1_TX_SLEW_SLD_1_0_K2_E5_SHIFT                    0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X196_TXCTRL_RATE2_TX_SLEW_SLD_1_0_K2_E5                          (0x3<<2) // TX rate2 slew rate setting
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X196_TXCTRL_RATE2_TX_SLEW_SLD_1_0_K2_E5_SHIFT                    2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X196_TXCTRL_RATE3_TX_SLEW_SLD_1_0_K2_E5                          (0x3<<4) // TX rate3 slew rate setting
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X196_TXCTRL_RATE3_TX_SLEW_SLD_1_0_K2_E5_SHIFT                    4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X196_TXCTRL_MASTER_TX_SLEW_SLD_OVR_1_0_K2_E5                     (0x3<<6) // TX master slew rate setting overrides.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X196_TXCTRL_MASTER_TX_SLEW_SLD_OVR_1_0_K2_E5_SHIFT               6
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X197_K2_E5                                                         0x002b14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X197_TXCTRL_PREEM_1LSB_MODE_K2_E5                                (0x1<<0) // TX 1lsb mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X197_TXCTRL_PREEM_1LSB_MODE_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X197_TXCTRL_MASTER_PREEM_1LSB_MODE_OVR_K2_E5                     (0x1<<1) // TX master 1lsb mode overrides.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X197_TXCTRL_MASTER_PREEM_1LSB_MODE_OVR_K2_E5_SHIFT               1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X197_TXCTRL_RATE1_TX_SLEW_SLD3F_2_0_K2_E5                        (0x7<<2) // TX enable fastest slew rate set to 1.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X197_TXCTRL_RATE1_TX_SLEW_SLD3F_2_0_K2_E5_SHIFT                  2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X197_TXCTRL_RATE2_TX_SLEW_SLD3F_2_0_K2_E5                        (0x7<<5) // TX enable fastest slew rate set to 1.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X197_TXCTRL_RATE2_TX_SLEW_SLD3F_2_0_K2_E5_SHIFT                  5
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X198_K2_E5                                                         0x002b18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X198_TXCTRL_RATE3_TX_SLEW_SLD3F_2_0_K2_E5                        (0x7<<0) // TX enable fastest slew rate set to 1.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X198_TXCTRL_RATE3_TX_SLEW_SLD3F_2_0_K2_E5_SHIFT                  0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X198_TXCTRL_MASTER_TX_SLEW_SLD3F_OVR_2_0_K2_E5                   (0x7<<3) // TX enable fastest slew rate override.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X198_TXCTRL_MASTER_TX_SLEW_SLD3F_OVR_2_0_K2_E5_SHIFT             3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X198_TXCTRL_MASTER_OVR_EN_O_K2_E5                                (0x1<<6) // Tx control master override enable
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X198_TXCTRL_MASTER_OVR_EN_O_K2_E5_SHIFT                          6
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X199_K2_E5                                                         0x002b1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X199_TXCTRL_RATE1_FULLSWG_C1_IN_4_0_K2_E5                        (0x1f<<0) // TX rate1 full swing C1 coefficient
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X199_TXCTRL_RATE1_FULLSWG_C1_IN_4_0_K2_E5_SHIFT                  0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X200_K2_E5                                                         0x002b20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X200_TXCTRL_RATE1_LOWSWG_C1_IN_4_0_K2_E5                         (0x1f<<0) // TX rate1 low swing C1 coefficient
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X200_TXCTRL_RATE1_LOWSWG_C1_IN_4_0_K2_E5_SHIFT                   0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X201_K2_E5                                                         0x002b24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X201_TXCTRL_RATE1_FULLSWG_C2_IN_3_0_K2_E5                        (0xf<<0) // TX rate1 full swing C2 coefficient
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X201_TXCTRL_RATE1_FULLSWG_C2_IN_3_0_K2_E5_SHIFT                  0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X201_TXCTRL_RATE1_LOWSWG_C2_IN_3_0_K2_E5                         (0xf<<4) // TX rate1 low swing C2 coefficient
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X201_TXCTRL_RATE1_LOWSWG_C2_IN_3_0_K2_E5_SHIFT                   4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X202_K2_E5                                                         0x002b28UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X202_TXCTRL_RATE2_FULLSWG_6DB_C1_IN_4_0_K2_E5                    (0x1f<<0) // TX rate2 full swing C1 coefficient for 6 dB
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X202_TXCTRL_RATE2_FULLSWG_6DB_C1_IN_4_0_K2_E5_SHIFT              0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X203_K2_E5                                                         0x002b2cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X203_TXCTRL_RATE2_FULLSWG_3P5DB_C1_IN_4_0_K2_E5                  (0x1f<<0) // TX rate2 full swing C1 coefficient for 3.5 dB
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X203_TXCTRL_RATE2_FULLSWG_3P5DB_C1_IN_4_0_K2_E5_SHIFT            0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X204_K2_E5                                                         0x002b30UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X204_TXCTRL_RATE2_FULLSWG_6DB_C2_IN_3_0_K2_E5                    (0xf<<0) // TX rate2 full swing C2 coefficient for 6 dB
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X204_TXCTRL_RATE2_FULLSWG_6DB_C2_IN_3_0_K2_E5_SHIFT              0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X204_TXCTRL_RATE2_FULLSWG_3P5DB_C2_IN_3_0_K2_E5                  (0xf<<4) // TX rate2 full swing C2 coefficient for 3.5 dB
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X204_TXCTRL_RATE2_FULLSWG_3P5DB_C2_IN_3_0_K2_E5_SHIFT            4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X205_K2_E5                                                         0x002b34UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X205_TXCTRL_RATE2_LOWSWG_C1_IN_4_0_K2_E5                         (0x1f<<0) // TX rate2 low swing C1 coefficient for 6 dB
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X205_TXCTRL_RATE2_LOWSWG_C1_IN_4_0_K2_E5_SHIFT                   0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X206_K2_E5                                                         0x002b38UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X206_TXCTRL_RATE2_LOWSWG_C2_IN_3_0_K2_E5                         (0xf<<0) // TX rate2 low swing C2 coefficient for 6 dB
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X206_TXCTRL_RATE2_LOWSWG_C2_IN_3_0_K2_E5_SHIFT                   0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X206_TXCTRL_RATE3_C2_IN_3_0_K2_E5                                (0xf<<4) // TX rate3 C2 coefficient
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X206_TXCTRL_RATE3_C2_IN_3_0_K2_E5_SHIFT                          4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X207_K2_E5                                                         0x002b3cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X207_TXCTRL_MASTER_C1_IN_OVR_4_0_K2_E5                           (0x1f<<0) // TX master C1 coefficient overrides.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X207_TXCTRL_MASTER_C1_IN_OVR_4_0_K2_E5_SHIFT                     0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X208_K2_E5                                                         0x002b40UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X208_TXCTRL_MASTER_C2_IN_OVR_3_0_K2_E5                           (0xf<<0) // TX master C2 coefficient overrides.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X208_TXCTRL_MASTER_C2_IN_OVR_3_0_K2_E5_SHIFT                     0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X208_TXCTRL_RATE1_CM_IN_3_0_K2_E5                                (0xf<<4) // TX rate1 CM coefficient
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X208_TXCTRL_RATE1_CM_IN_3_0_K2_E5_SHIFT                          4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X209_K2_E5                                                         0x002b44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X209_TXCTRL_RATE2_CM_IN_3_0_K2_E5                                (0xf<<0) // TX rate2 CM coefficient
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X209_TXCTRL_RATE2_CM_IN_3_0_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X209_TXCTRL_MASTER_CM_IN_OVR_3_0_K2_E5                           (0xf<<4) // TX master CM coefficient overrides.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X209_TXCTRL_MASTER_CM_IN_OVR_3_0_K2_E5_SHIFT                     4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X210_K2_E5                                                         0x002b48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X210_REDUCED_SWING_LF_VAL_O_5_0_K2_E5                            (0x3f<<0) // Reduced swing LowFreq value
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X210_REDUCED_SWING_LF_VAL_O_5_0_K2_E5_SHIFT                      0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X210_TXEQ_CM1_FORCE_LOW_EN_O_K2_E5                               (0x1<<6) // Brings the TxEq pre-cursor down to a programmable value txeq_cm1_min_limit if pre cursor tuning is bypassed
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X210_TXEQ_CM1_FORCE_LOW_EN_O_K2_E5_SHIFT                         6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X210_TXEQ_C1_FORCE_LOW_EN_O_K2_E5                                (0x1<<7) // Brings the TxEq pre-cursor down to a programmable value txeq_c1_min_limit if pre cursor tuning is bypassed
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X210_TXEQ_C1_FORCE_LOW_EN_O_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X211_K2_E5                                                         0x002b4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X211_RX_BIAS_00_O_2_0_K2_E5                                      (0x7<<0) // AFE rx_bias setting. Used when rxvcodiv is 00
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X211_RX_BIAS_00_O_2_0_K2_E5_SHIFT                                0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X211_RX_BIAS_01_O_2_0_K2_E5                                      (0x7<<3) // AFE rx_bias setting. Used when rxvcodiv is 01 or 10
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X211_RX_BIAS_01_O_2_0_K2_E5_SHIFT                                3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X212_K2_E5                                                         0x002b50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X212_RX_BIAS_11_O_2_0_K2_E5                                      (0x7<<0) // AFE rx_bias setting. Used when rxvcodiv is 11
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X212_RX_BIAS_11_O_2_0_K2_E5_SHIFT                                0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X213_K2_E5                                                         0x002b54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X213_QAHB_CDR_VCO_CAL_PHD_ENA_O_K2_E5                            (0x1<<6) // Enable phase detector during CDR VCO calibration
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X213_QAHB_CDR_VCO_CAL_PHD_ENA_O_K2_E5_SHIFT                      6
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X214_K2_E5                                                         0x002b58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_CDR_LOCK_WAIT_O_3_0_K2_E5                              (0xf<<0) // Number of wait cycles for the CDR to lock [3:0] times 64
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_CDR_LOCK_WAIT_O_3_0_K2_E5_SHIFT                        0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_RATE_CHNG_CAL_O_K2_E5                                  (0x1<<4) // Assertion causes repeat of calibration for rate switch or electrical idle exit. Calibrations to be performed are selected by rxeq_recal_o[6:0]/rxeq_rate2_recal_o[6:0].
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_RATE_CHNG_CAL_O_K2_E5_SHIFT                            4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_PRESET_CLR_DFE_O_K2_E5                                 (0x1<<6) // Set all DFE calibration values to mid-scale instead of using start values at start of calibration
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_PRESET_CLR_DFE_O_K2_E5_SHIFT                           6
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X215_K2_E5                                                         0x002b5cUL //Access:RW   DataWidth:0x8    // DFE block -continuous calibration wait delay. DFE block will wait this number of cycles between each continuous calibration cycle
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X216_K2_E5                                                         0x002b60UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X216_RXEQ_CONT_LENGTH_O_14_8_K2_E5                               (0x7f<<0) // DFE block -continuous calibration wait delay. DFE block will wait this number of cycles between each continuous calibration cycle
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X216_RXEQ_CONT_LENGTH_O_14_8_K2_E5_SHIFT                         0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X217_K2_E5                                                         0x002b64UL //Access:RW   DataWidth:0x8    // DFE block - ATT calibration cycle length. This is the number of cycles the DFE will wait between changing the ATT value and examining the output.
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X218_K2_E5                                                         0x002b68UL //Access:RW   DataWidth:0x8    // DFE block - Boost calibration cycle length. This is the number of cycles the DFE will wait between changing the boost value and examining the output.
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X219_K2_E5                                                         0x002b6cUL //Access:RW   DataWidth:0x8    // DFE block - TAP1 calibration cycle length. This is the number of cycles the DFE will wait between changing the TAP1 value and examining the output.
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X220_K2_E5                                                         0x002b70UL //Access:RW   DataWidth:0x8    // DFE block - TAP2 calibration cycle length. This is the number of cycles the DFE will wait between changing the TAP2 value and examining the output.
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X221_K2_E5                                                         0x002b74UL //Access:RW   DataWidth:0x8    // DFE block - TAP3 calibration cycle length. This is the number of cycles the DFE will wait between changing the TAP2 value and examining the output.
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X222_K2_E5                                                         0x002b78UL //Access:RW   DataWidth:0x8    // DFE block - TAP4 calibration cycle length. This is the number of cycles the DFE will wait between changing the TAP2 value and examining the output.
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X223_K2_E5                                                         0x002b7cUL //Access:RW   DataWidth:0x8    // DFE block - TAP5 calibration cycle length. This is the number of cycles the DFE will wait between changing the TAP2 value and examining the output.
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X224_K2_E5                                                         0x002b80UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X224_RXEQ_EI_EXIT_CAL_O_K2_E5                                    (0x1<<0) // Repeat calibration whenever exiting RX electrical idle. Calibrations performed are selected by rxeq_recal_o[6:0]/rxeq_lane2_recal_o[6:0]
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X224_RXEQ_EI_EXIT_CAL_O_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X224_RXEQ_RECAL_O_6_0_K2_E5                                      (0x7f<<1) // Enables re-calibration for { Tap5, Tap4, Tap3, Tap2, Tap1, Boost, ATT} at rate3 after exit from electrical idle when rxeq_ei_exit_cal_o is asserted and after rate change when rxeq_rate_chng_cal_o is asserted.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X224_RXEQ_RECAL_O_6_0_K2_E5_SHIFT                                1
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X225_K2_E5                                                         0x002b84UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X225_RXEQ_RATE2_INIT_CAL_O_6_0_K2_E5                             (0x7f<<0) // Specify which block needs initial calibration upon exit from RX electrical idle state for rate2: bit [0]: Enables ATT calibration when asserted bit [1]: Enables Boost calibration when asserted bit [2]: Enables DFE Tap1 calibration when asserted bit [3]: Enables DFE Tap2 calibration when asserted bit [4]: Enables DFE Tap3 calibration when asserted bit [5]: Enables DFE Tap4 calibration when asserted bit [6]: Enables DFE Tap5 calibration when asserted
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X225_RXEQ_RATE2_INIT_CAL_O_6_0_K2_E5_SHIFT                       0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X226_K2_E5                                                         0x002b88UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X226_RXEQ_RATE2_CONT_CAL_O_6_0_K2_E5                             (0x7f<<0) // Specify which block needs continuous calibration during RX data reception for rate2 bit [0]: Enables ATT calibration when asserted bit [1]: Enables Boost calibration when asserted bit [2]: Enables DFE Tap1 calibration when asserted bit [3]: Enables DFE Tap2 calibration when asserted bit [4]: Enables DFE Tap3 calibration when asserted bit [5]: Enables DFE Tap4 calibration when asserted bit [6]: Enables DFE Tap5 calibration when asserted
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X226_RXEQ_RATE2_CONT_CAL_O_6_0_K2_E5_SHIFT                       0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X227_K2_E5                                                         0x002b8cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X227_RXEQ_RATE2_RECAL_O_6_0_K2_E5                                (0x7f<<0) // Enables re-calibration for { Tap5, Tap4, Tap3, Tap2, Tap1, Boost, ATT} at rate2 after exit from electrical idle when rxeq_ei_exit_cal_o is asserted and after rate change when rxeq_rate_chng_cal_o is asserted.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X227_RXEQ_RATE2_RECAL_O_6_0_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X228_K2_E5                                                         0x002b90UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X228_RXEQ_ATT_BOUNCE_O_3_0_K2_E5                                 (0xf<<0) // Number of bounces before calibration stops for ATT
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X228_RXEQ_ATT_BOUNCE_O_3_0_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X228_RXEQ_BOOST_BOUNCE_O_3_0_K2_E5                               (0xf<<4) // Number of bounces before calibration stops for Boost
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X228_RXEQ_BOOST_BOUNCE_O_3_0_K2_E5_SHIFT                         4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X229_K2_E5                                                         0x002b94UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X229_RXEQ_TAP1_BOUNCE_O_3_0_K2_E5                                (0xf<<0) // Number of bounces before calibration stops for DFE tap1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X229_RXEQ_TAP1_BOUNCE_O_3_0_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X229_RXEQ_TAP2_BOUNCE_O_3_0_K2_E5                                (0xf<<4) // Number of bounces before calibration stops for DFE tap2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X229_RXEQ_TAP2_BOUNCE_O_3_0_K2_E5_SHIFT                          4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X230_K2_E5                                                         0x002b98UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X230_RXEQ_TAP3_BOUNCE_O_3_0_K2_E5                                (0xf<<0) // Number of bounces before calibration stops for DFE tap3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X230_RXEQ_TAP3_BOUNCE_O_3_0_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X230_RXEQ_TAP4_BOUNCE_O_3_0_K2_E5                                (0xf<<4) // Number of bounces before calibration stops for DFE tap4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X230_RXEQ_TAP4_BOUNCE_O_3_0_K2_E5_SHIFT                          4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X231_K2_E5                                                         0x002b9cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X231_RXEQ_TAP5_BOUNCE_O_3_0_K2_E5                                (0xf<<0) // Number of bounces before calibration stops for DFE tap5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X231_RXEQ_TAP5_BOUNCE_O_3_0_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X231_RXEQ_COARSE_STEP_SIZE_O_3_0_K2_E5                           (0xf<<4) // Initial calibration coarse step size
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X231_RXEQ_COARSE_STEP_SIZE_O_3_0_K2_E5_SHIFT                     4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X232_K2_E5                                                         0x002ba0UL //Access:RW   DataWidth:0x8    // comparator offset override value
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X233_K2_E5                                                         0x002ba4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X233_CMP_OFFSET_OVR_EN_O_K2_E5                                   (0x1<<0) // comparator offset override enable
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X233_CMP_OFFSET_OVR_EN_O_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X233_RXEQ_FIN_HIGH_O_6_0_K2_E5                                   (0x7f<<1) // Enable final calibration value plus one for individual blocks
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X233_RXEQ_FIN_HIGH_O_6_0_K2_E5_SHIFT                             1
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X234_K2_E5                                                         0x002ba8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X234_RXEQ_FIN_LOW_O_6_0_K2_E5                                    (0x7f<<0) // Enable final calibration value minus one for individual blocks
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X234_RXEQ_FIN_LOW_O_6_0_K2_E5_SHIFT                              0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X234_QAHB_DFE_RAW_VALUE_O_K2_E5                                  (0x1<<7) // Testbus select for comp_offset and tap_offset 1: Raw output from i_dfe_tap_dc_offset 0: Input to pma
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X234_QAHB_DFE_RAW_VALUE_O_K2_E5_SHIFT                            7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X235_K2_E5                                                         0x002bacUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X235_RXEQ_ERR_SIGN_O_6_0_K2_E5                                   (0x7f<<0) // Controls polarity of RX calibration: bit [0]: Reverses polarity of ATT calibration when asserted bit [1]: Reverses polarity of Boost calibration when asserted bit [2]: Reverses polarity of DFE Tap1 calibration when asserted bit [3]: Reverses polarity of DFE Tap2 calibration when asserted bit [4]: Reverses polarity of DFE Tap3 calibration when asserted bit [5]: Reverses polarity of DFE Tap4 calibration when asserted bit [6]: Reverses polarity of DFE Tap5 calibration when asserted
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X235_RXEQ_ERR_SIGN_O_6_0_K2_E5_SHIFT                             0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X236_K2_E5                                                         0x002bb0UL //Access:RW   DataWidth:0x8    // Training pattern for boost
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X237_K2_E5                                                         0x002bb4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X237_RXEQ_RATE1_BOOST_TRAINING_PATT_O_8_K2_E5                    (0x1<<0) // Training pattern for boost
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X237_RXEQ_RATE1_BOOST_TRAINING_PATT_O_8_K2_E5_SHIFT              0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X238_K2_E5                                                         0x002bb8UL //Access:RW   DataWidth:0x8    // Training pattern for DFE tap1
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X239_K2_E5                                                         0x002bbcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X239_RXEQ_TAP1_TRAINING_PATT_O_8_K2_E5                           (0x1<<0) // Training pattern for DFE tap1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X239_RXEQ_TAP1_TRAINING_PATT_O_8_K2_E5_SHIFT                     0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X240_K2_E5                                                         0x002bc0UL //Access:RW   DataWidth:0x8    // Training pattern for DFE tap2
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X241_K2_E5                                                         0x002bc4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X241_RXEQ_TAP2_TRAINING_PATT_O_8_K2_E5                           (0x1<<0) // Training pattern for DFE tap2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X241_RXEQ_TAP2_TRAINING_PATT_O_8_K2_E5_SHIFT                     0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X242_K2_E5                                                         0x002bc8UL //Access:RW   DataWidth:0x8    // Training pattern for DFE tap3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X243_K2_E5                                                         0x002bccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X243_RXEQ_TAP3_TRAINING_PATT_O_8_K2_E5                           (0x1<<0) // Training pattern for DFE tap3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X243_RXEQ_TAP3_TRAINING_PATT_O_8_K2_E5_SHIFT                     0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X244_K2_E5                                                         0x002bd0UL //Access:RW   DataWidth:0x8    // Training pattern for DFE tap4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X245_K2_E5                                                         0x002bd4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X245_RXEQ_TAP4_TRAINING_PATT_O_8_K2_E5                           (0x1<<0) // Training pattern for DFE tap4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X245_RXEQ_TAP4_TRAINING_PATT_O_8_K2_E5_SHIFT                     0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X246_K2_E5                                                         0x002bd8UL //Access:RW   DataWidth:0x8    // Training pattern for DFE tap5
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X247_K2_E5                                                         0x002bdcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X247_RXEQ_TAP5_TRAINING_PATT_O_8_K2_E5                           (0x1<<0) // Training pattern for DFE tap5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X247_RXEQ_TAP5_TRAINING_PATT_O_8_K2_E5_SHIFT                     0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X248_K2_E5                                                         0x002be0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_DONT_CARE_O_5_0_K2_E5                                  (0x3f<<0) // Sets certain bits in training pattern as don't care
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_DONT_CARE_O_5_0_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_STEP_MODE_O_K2_E5                                      (0x1<<6) // RXEQ ctrl_test mode enable
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_STEP_MODE_O_K2_E5_SHIFT                                6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_STEP_O_K2_E5                                           (0x1<<7) // Step calibration in test mode, rising edge triggers step
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_STEP_O_K2_E5_SHIFT                                     7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X249_K2_E5                                                         0x002be4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X249_RXEQ_AVG4_O_6_0_K2_E5                                       (0x7f<<0) // Enable average 4 in calibration, otherwise average2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X249_RXEQ_AVG4_O_6_0_K2_E5_SHIFT                                 0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X249_RXEQ_FLOOR_O_K2_E5                                          (0x1<<7) // Take the floor of the calibration result
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X249_RXEQ_FLOOR_O_K2_E5_SHIFT                                    7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X250_K2_E5                                                         0x002be8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X250_RXEQ_SHIFT_O_3_0_K2_E5                                      (0xf<<0) // Shift the edge samples in rxeq_ctrl
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X250_RXEQ_SHIFT_O_3_0_K2_E5_SHIFT                                0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X251_K2_E5                                                         0x002becUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X251_RXEQ_RATE3_DFE_TAP_PD_O_4_0_K2_E5                           (0x1f<<0) // DFE tap powerdown for rate3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X251_RXEQ_RATE3_DFE_TAP_PD_O_4_0_K2_E5_SHIFT                     0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X252_K2_E5                                                         0x002bf0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X252_RXEQ_RATE2_DFE_TAP_PD_O_4_0_K2_E5                           (0x1f<<0) // DFE tap powerdown for rate2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X252_RXEQ_RATE2_DFE_TAP_PD_O_4_0_K2_E5_SHIFT                     0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X252_REVERSE_TAP_PD_ORDER_O_K2_E5                                (0x1<<5) // Reverse order of tap power down signals
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X252_REVERSE_TAP_PD_ORDER_O_K2_E5_SHIFT                          5
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X253_K2_E5                                                         0x002bf4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X253_MSM_LN_DFE_TAP_WAIT_O_4_0_K2_E5                             (0x1f<<0) // Wait time between each DFE tap DC offset calibration
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X253_MSM_LN_DFE_TAP_WAIT_O_4_0_K2_E5_SHIFT                       0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X253_SKP_CMP_CAL_O_K2_E5                                         (0x1<<5) // By pass comparator DC offset calibration
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X253_SKP_CMP_CAL_O_K2_E5_SHIFT                                   5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X253_DFE_TAP_OFFSET_CAL_DIR_O_K2_E5                              (0x1<<6) // Changes the dfe tap offset cal direction
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X253_DFE_TAP_OFFSET_CAL_DIR_O_K2_E5_SHIFT                        6
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X254_K2_E5                                                         0x002bf8UL //Access:RW   DataWidth:0x8    // Training pattern for boost in rate2
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X255_K2_E5                                                         0x002bfcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X255_RXEQ_RATE2_BOOST_TRAINING_PATT_O_8_K2_E5                    (0x1<<0) // Training pattern for boost in rate2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X255_RXEQ_RATE2_BOOST_TRAINING_PATT_O_8_K2_E5_SHIFT              0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X256_K2_E5                                                         0x002c00UL //Access:RW   DataWidth:0x8    // Training pattern for boost in rate3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X257_K2_E5                                                         0x002c04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X257_RXEQ_RATE3_BOOST_TRAINING_PATT_O_8_K2_E5                    (0x1<<0) // Training pattern for boost in rate3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X257_RXEQ_RATE3_BOOST_TRAINING_PATT_O_8_K2_E5_SHIFT              0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X258_K2_E5                                                         0x002c08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X258_RXEQ_RATE1_BOOST_DONT_CARE_O_5_0_K2_E5                      (0x3f<<0) // Sets certain bits in training pattern as don't care in rate1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X258_RXEQ_RATE1_BOOST_DONT_CARE_O_5_0_K2_E5_SHIFT                0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X259_K2_E5                                                         0x002c0cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X259_RXEQ_RATE2_BOOST_DONT_CARE_O_5_0_K2_E5                      (0x3f<<0) // Sets certain bits in training pattern as don't care in rate2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X259_RXEQ_RATE2_BOOST_DONT_CARE_O_5_0_K2_E5_SHIFT                0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X260_K2_E5                                                         0x002c10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X260_RXEQ_RATE3_BOOST_DONT_CARE_O_5_0_K2_E5                      (0x3f<<0) // Sets certain bits in training pattern as don't care in rate3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X260_RXEQ_RATE3_BOOST_DONT_CARE_O_5_0_K2_E5_SHIFT                0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X261_K2_E5                                                         0x002c14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X261_DFE_SHADOW_LANE_SEL_K2_E5                                   (0x3<<5) // DFE TAP shadow register lane select
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X261_DFE_SHADOW_LANE_SEL_K2_E5_SHIFT                             5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X261_DFE_SHADOW_OFST_RD_SEL_K2_E5                                (0x1<<7) // DFE shadow offset read select
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X261_DFE_SHADOW_OFST_RD_SEL_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X263_K2_E5                                                         0x002c1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X263_RATE3_RATESWITCH_RXRECAL_CFG_6_0_K2_E5                      (0x7f<<0) // Gen3 rate switch cal elements
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X263_RATE3_RATESWITCH_RXRECAL_CFG_6_0_K2_E5_SHIFT                0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X264_K2_E5                                                         0x002c20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X264_RATE3_TXEQ_RXRECAL_BEGIN_CFG_6_0_K2_E5                      (0x7f<<0) // Gen3 beginning of TxEQ RxEQ cal elements
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X264_RATE3_TXEQ_RXRECAL_BEGIN_CFG_6_0_K2_E5_SHIFT                0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X265_K2_E5                                                         0x002c24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X265_RATE3_TXEQ_RXRECAL_END_CFG_6_0_K2_E5                        (0x7f<<0) // Gen3 end of TxEQ RxEQ cal elements
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X265_RATE3_TXEQ_RXRECAL_END_CFG_6_0_K2_E5_SHIFT                  0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X266_K2_E5                                                         0x002c28UL //Access:R    DataWidth:0x8    // DFE CMP value read
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X267_K2_E5                                                         0x002c2cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X267_DFE_TAP1_VAL_K2_E5                                          (0x7f<<0) // DFE TAP1 value read
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X267_DFE_TAP1_VAL_K2_E5_SHIFT                                    0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X268_K2_E5                                                         0x002c30UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X268_DFE_TAP2_VAL_K2_E5                                          (0x3f<<0) // DFE TAP2 value read
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X268_DFE_TAP2_VAL_K2_E5_SHIFT                                    0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X269_K2_E5                                                         0x002c34UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X269_DFE_TAP3_VAL_K2_E5                                          (0x3f<<0) // DFE TAP3 value read
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X269_DFE_TAP3_VAL_K2_E5_SHIFT                                    0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X270_K2_E5                                                         0x002c38UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X270_DFE_TAP4_VAL_K2_E5                                          (0x3f<<0) // DFE TAP4 value read
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X270_DFE_TAP4_VAL_K2_E5_SHIFT                                    0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X271_K2_E5                                                         0x002c3cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X271_DFE_TAP5_VAL_K2_E5                                          (0x3f<<0) // DFE TAP5 value read
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X271_DFE_TAP5_VAL_K2_E5_SHIFT                                    0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X272_K2_E5                                                         0x002c40UL //Access:RW   DataWidth:0x8    // Training pattern for TxEQ adapt DFE tap1 cm1 [7:0]
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X273_K2_E5                                                         0x002c44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X273_TAP1_CM1_TRAINING_PATT_8_K2_E5                              (0x1<<0) // Training pattern for TxEQ adapt DFE tap1 cm1 [8]
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X273_TAP1_CM1_TRAINING_PATT_8_K2_E5_SHIFT                        0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X273_TXEQ_ADAPT_RUN_1_0_K2_E5                                    (0x3<<1) // TxEQ Adapt 2 TAPs
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X273_TXEQ_ADAPT_RUN_1_0_K2_E5_SHIFT                              1
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X274_K2_E5                                                         0x002c48UL //Access:RW   DataWidth:0x8    // Training pattern for TxEQ adapt DFE tap1 c1 [7:0]
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X275_K2_E5                                                         0x002c4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X275_TAP1_C1_TRAINING_PATT_8_K2_E5                               (0x1<<0) // Training pattern for TxEQ adapt DFE tap1 c1 [8]
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X275_TAP1_C1_TRAINING_PATT_8_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X275_TXEQ_ADAPT_INIT_O_1_K2_E5                                   (0x1<<1) // Initiate TXEQ adaptation for Gen3 rate
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X275_TXEQ_ADAPT_INIT_O_1_K2_E5_SHIFT                             1
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X276_K2_E5                                                         0x002c50UL //Access:RW   DataWidth:0x8    // TX Equalizer Training Pattern select
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X277_K2_E5                                                         0x002c54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X277_TXEQ_TRAINING_PATT_O_8_K2_E5                                (0x1<<0) // TX Equalizer Training Pattern select
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X277_TXEQ_TRAINING_PATT_O_8_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X278_K2_E5                                                         0x002c58UL //Access:RW   DataWidth:0x8    // TX Equalizer Training Pattern mask during Link Training
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X279_K2_E5                                                         0x002c5cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X279_TXEQ_DONT_CARE_O_8_K2_E5                                    (0x1<<0) // TX Equalizer Training Pattern mask during Link Training
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X279_TXEQ_DONT_CARE_O_8_K2_E5_SHIFT                              0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X280_K2_E5                                                         0x002c60UL //Access:RW   DataWidth:0x8    // Number of Link Training frames per TX Equalization Iteration
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X281_K2_E5                                                         0x002c64UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X281_RXEQ_CAL_DONE_I_3_0_K2_E5                                   (0xf<<0) // RXEQ calibration done status - per lane
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X281_RXEQ_CAL_DONE_I_3_0_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X281_TXEQ_ADAPT_DONE_I_3_0_K2_E5                                 (0xf<<4) // TXEQ Adapt Done status - per lane
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X281_TXEQ_ADAPT_DONE_I_3_0_K2_E5_SHIFT                           4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X282_K2_E5                                                         0x002c68UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X282_TXEQ_ADAPT_CM1_CHNG_DIR_SUM_THRESHOLD_O_K2_E5               (0xf<<0) // CM1 coefficient change direction sum threshold value
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X282_TXEQ_ADAPT_CM1_CHNG_DIR_SUM_THRESHOLD_O_K2_E5_SHIFT         0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X282_TXEQ_ADAPT_C1_CHNG_DIR_SUM_THRESHOLD_O_3_0_K2_E5            (0xf<<4) // C1 coefficient change direction sum threshold value
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X282_TXEQ_ADAPT_C1_CHNG_DIR_SUM_THRESHOLD_O_3_0_K2_E5_SHIFT      4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X283_K2_E5                                                         0x002c6cUL //Access:RW   DataWidth:0x8    // Txeq adaptation iteration count threshold
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X284_K2_E5                                                         0x002c70UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X284_LATENCY_CHK_CONTROL_O_K2_E5                                 (0x1f<<0) // Bit 4 - latency check control enable Bit 3:0 - latency counter value
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X284_LATENCY_CHK_CONTROL_O_K2_E5_SHIFT                           0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X285_K2_E5                                                         0x002c74UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X285_TXCTRL_TX_MARGIN_000_LOWSWG_ATT_IN_RATE3_3_0_K2_E5          (0xf<<0) // PIPE tx_margin low swing setting rate3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X285_TXCTRL_TX_MARGIN_000_LOWSWG_ATT_IN_RATE3_3_0_K2_E5_SHIFT    0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X285_TXCTRL_TX_MARGIN_001_LOWSWG_ATT_IN_RATE3_3_0_K2_E5          (0xf<<4) // PIPE tx_margin low swing setting rate3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X285_TXCTRL_TX_MARGIN_001_LOWSWG_ATT_IN_RATE3_3_0_K2_E5_SHIFT    4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X286_K2_E5                                                         0x002c78UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X286_TXCTRL_TX_MARGIN_010_LOWSWG_ATT_IN_RATE3_3_0_K2_E5          (0xf<<0) // PIPE tx_margin low swing setting rate3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X286_TXCTRL_TX_MARGIN_010_LOWSWG_ATT_IN_RATE3_3_0_K2_E5_SHIFT    0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X286_TXCTRL_TX_MARGIN_011_LOWSWG_ATT_IN_RATE3_3_0_K2_E5          (0xf<<4) // PIPE tx_margin low swing setting rate3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X286_TXCTRL_TX_MARGIN_011_LOWSWG_ATT_IN_RATE3_3_0_K2_E5_SHIFT    4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X287_K2_E5                                                         0x002c7cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X287_TXCTRL_TX_MARGIN_100_LOWSWG_ATT_IN_RATE3_3_0_K2_E5          (0xf<<0) // PIPE tx_margin low swing setting rate3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X287_TXCTRL_TX_MARGIN_100_LOWSWG_ATT_IN_RATE3_3_0_K2_E5_SHIFT    0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X287_TXCTRL_TX_MARGIN_101_LOWSWG_ATT_IN_RATE3_3_0_K2_E5          (0xf<<4) // PIPE tx_margin low swing setting rate3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X287_TXCTRL_TX_MARGIN_101_LOWSWG_ATT_IN_RATE3_3_0_K2_E5_SHIFT    4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X288_K2_E5                                                         0x002c80UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X288_TXCTRL_TX_MARGIN_110_LOWSWG_ATT_IN_RATE3_3_0_K2_E5          (0xf<<0) // PIPE tx_margin low swing setting rate3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X288_TXCTRL_TX_MARGIN_110_LOWSWG_ATT_IN_RATE3_3_0_K2_E5_SHIFT    0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X288_TXCTRL_TX_MARGIN_111_LOWSWG_ATT_IN_RATE3_3_0_K2_E5          (0xf<<4) // PIPE tx_margin low swing setting rate3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X288_TXCTRL_TX_MARGIN_111_LOWSWG_ATT_IN_RATE3_3_0_K2_E5_SHIFT    4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X289_K2_E5                                                         0x002c84UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X289_TXCTRL_TX_MARGIN_000_FULLSWG_ATT_IN_RATE3_3_0_K2_E5         (0xf<<0) // PIPE tx_margin full swing setting rate3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X289_TXCTRL_TX_MARGIN_000_FULLSWG_ATT_IN_RATE3_3_0_K2_E5_SHIFT   0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X289_TXCTRL_TX_MARGIN_001_FULLSWG_ATT_IN_RATE3_3_0_K2_E5         (0xf<<4) // PIPE tx_margin full swing setting rate3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X289_TXCTRL_TX_MARGIN_001_FULLSWG_ATT_IN_RATE3_3_0_K2_E5_SHIFT   4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X290_K2_E5                                                         0x002c88UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X290_TXCTRL_TX_MARGIN_010_FULLSWG_ATT_IN_RATE3_3_0_K2_E5         (0xf<<0) // PIPE tx_margin full swing setting rate3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X290_TXCTRL_TX_MARGIN_010_FULLSWG_ATT_IN_RATE3_3_0_K2_E5_SHIFT   0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X290_TXCTRL_TX_MARGIN_011_FULLSWG_ATT_IN_RATE3_3_0_K2_E5         (0xf<<4) // PIPE tx_margin full swing setting rate3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X290_TXCTRL_TX_MARGIN_011_FULLSWG_ATT_IN_RATE3_3_0_K2_E5_SHIFT   4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X291_K2_E5                                                         0x002c8cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X291_TXCTRL_TX_MARGIN_100_FULLSWG_ATT_IN_RATE3_3_0_K2_E5         (0xf<<0) // PIPE tx_margin full swing setting rate3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X291_TXCTRL_TX_MARGIN_100_FULLSWG_ATT_IN_RATE3_3_0_K2_E5_SHIFT   0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X291_TXCTRL_TX_MARGIN_101_FULLSWG_ATT_IN_RATE3_3_0_K2_E5         (0xf<<4) // PIPE tx_margin full swing setting rate3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X291_TXCTRL_TX_MARGIN_101_FULLSWG_ATT_IN_RATE3_3_0_K2_E5_SHIFT   4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X292_K2_E5                                                         0x002c90UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X292_TXCTRL_TX_MARGIN_110_FULLSWG_ATT_IN_RATE3_3_0_K2_E5         (0xf<<0) // PIPE tx_margin full swing setting rate3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X292_TXCTRL_TX_MARGIN_110_FULLSWG_ATT_IN_RATE3_3_0_K2_E5_SHIFT   0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X292_TXCTRL_TX_MARGIN_111_FULLSWG_ATT_IN_RATE3_3_0_K2_E5         (0xf<<4) // PIPE tx_margin full swing setting rate3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X292_TXCTRL_TX_MARGIN_111_FULLSWG_ATT_IN_RATE3_3_0_K2_E5_SHIFT   4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X293_K2_E5                                                         0x002c94UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X293_TXCTRL_RATE12_TX_VREG_LEV_4_0_K2_E5                         (0x1f<<0) // TX driver regulator voltage setting.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X293_TXCTRL_RATE12_TX_VREG_LEV_4_0_K2_E5_SHIFT                   0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X294_K2_E5                                                         0x002c98UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X294_TXCTRL_RATE3_TX_VREG_LEV_4_0_K2_E5                          (0x1f<<0) // TX driver regulator voltage setting.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X294_TXCTRL_RATE3_TX_VREG_LEV_4_0_K2_E5_SHIFT                    0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X295_K2_E5                                                         0x002c9cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X295_TXCTRL_MASTER_VREG_LEV_OVR_4_0_K2_E5                        (0x1f<<0) // Does not exist!
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X295_TXCTRL_MASTER_VREG_LEV_OVR_4_0_K2_E5_SHIFT                  0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X296_K2_E5                                                         0x002ca0UL //Access:RW   DataWidth:0x8    // Txeq CM1 coefficient adpatation error measurment wait time during each iteration
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X297_K2_E5                                                         0x002ca4UL //Access:RW   DataWidth:0x8    // Txeq C1 coefficient adpatation error measurment wait time during each iteration
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X301_K2_E5                                                         0x002cb4UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X304_K2_E5                                                         0x002cc0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X304_QAHB_CDFE_RATE3_LOAD_EYE_CNT_WAIT_K2_E5                     (0xf<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X304_QAHB_CDFE_RATE3_LOAD_EYE_CNT_WAIT_K2_E5_SHIFT               0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X304_QAHB_CDFE_RATE3_EYE_IN_RST_WAIT_3_0_K2_E5                   (0xf<<4) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X304_QAHB_CDFE_RATE3_EYE_IN_RST_WAIT_3_0_K2_E5_SHIFT             4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X305_K2_E5                                                         0x002cc4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X305_QAHB_CDFE_RATE3_EXIT_EYE_RST_WAIT_K2_E5                     (0xf<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X305_QAHB_CDFE_RATE3_EXIT_EYE_RST_WAIT_K2_E5_SHIFT               0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X305_QAHB_CDFE_RATE3_DFE_STROBE_REDGE_WAIT_3_0_K2_E5             (0xf<<4) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X305_QAHB_CDFE_RATE3_DFE_STROBE_REDGE_WAIT_3_0_K2_E5_SHIFT       4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X306_K2_E5                                                         0x002cc8UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X307_K2_E5                                                         0x002cccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X307_QAHB_CDFE_RATE3_MIN_EYE_DLY_K2_E5                           (0x7f<<0) // Minimum eye delay value for rate3 during dll calibration
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X307_QAHB_CDFE_RATE3_MIN_EYE_DLY_K2_E5_SHIFT                     0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X308_K2_E5                                                         0x002cd0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X308_QAHB_CDFE_RATE3_MAX_EYE_DLY_K2_E5                           (0x7f<<0) // Maximum eye delay value for rate3 during dll calibration
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X308_QAHB_CDFE_RATE3_MAX_EYE_DLY_K2_E5_SHIFT                     0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X310_K2_E5                                                         0x002cd8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X310_QAHB_CDFE_RATE3_TAP1_PATT_MASK_6_0_K2_E5                    (0x7f<<0) // cdfe tap1 training pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X310_QAHB_CDFE_RATE3_TAP1_PATT_MASK_6_0_K2_E5_SHIFT              0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X311_K2_E5                                                         0x002cdcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X311_QAHB_CDFE_RATE3_TAP2_PATT_MASK_6_0_K2_E5                    (0x7f<<0) // cdfe tap2 training pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X311_QAHB_CDFE_RATE3_TAP2_PATT_MASK_6_0_K2_E5_SHIFT              0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X312_K2_E5                                                         0x002ce0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X312_QAHB_CDFE_RATE3_TAP3_PATT_MASK_6_0_K2_E5                    (0x7f<<0) // cdfe tap3 training pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X312_QAHB_CDFE_RATE3_TAP3_PATT_MASK_6_0_K2_E5_SHIFT              0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X313_K2_E5                                                         0x002ce4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X313_QAHB_CDFE_RATE3_TAP4_PATT_MASK_6_0_K2_E5                    (0x7f<<0) // cdfe tap4 training pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X313_QAHB_CDFE_RATE3_TAP4_PATT_MASK_6_0_K2_E5_SHIFT              0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X314_K2_E5                                                         0x002ce8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X314_QAHB_CDFE_RATE3_TAP5_PATT_MASK_6_0_K2_E5                    (0x7f<<0) // cdfe tap5 training pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X314_QAHB_CDFE_RATE3_TAP5_PATT_MASK_6_0_K2_E5_SHIFT              0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X315_K2_E5                                                         0x002cecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X315_QAHB_CDFE_RATE3_DLEV_PATT_MASK_6_0_K2_E5                    (0x7f<<0) // cdfe dlev training pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X315_QAHB_CDFE_RATE3_DLEV_PATT_MASK_6_0_K2_E5_SHIFT              0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X318_K2_E5                                                         0x002cf8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X318_QAHB_CDFE_RATE2_LOAD_EYE_CNT_WAIT_K2_E5                     (0xf<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X318_QAHB_CDFE_RATE2_LOAD_EYE_CNT_WAIT_K2_E5_SHIFT               0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X318_QAHB_CDFE_RATE2_EYE_IN_RST_WAIT_3_0_K2_E5                   (0xf<<4) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X318_QAHB_CDFE_RATE2_EYE_IN_RST_WAIT_3_0_K2_E5_SHIFT             4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X319_K2_E5                                                         0x002cfcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X319_QAHB_CDFE_RATE2_EXIT_EYE_RST_WAIT_K2_E5                     (0xf<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X319_QAHB_CDFE_RATE2_EXIT_EYE_RST_WAIT_K2_E5_SHIFT               0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X319_QAHB_CDFE_RATE2_DFE_STROBE_REDGE_WAIT_3_0_K2_E5             (0xf<<4) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X319_QAHB_CDFE_RATE2_DFE_STROBE_REDGE_WAIT_3_0_K2_E5_SHIFT       4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X320_K2_E5                                                         0x002d00UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X321_K2_E5                                                         0x002d04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X321_QAHB_CDFE_RATE2_MIN_EYE_DLY_6_0_K2_E5                       (0x7f<<0) // Minimum eye delay value for rate2 during dll calibration
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X321_QAHB_CDFE_RATE2_MIN_EYE_DLY_6_0_K2_E5_SHIFT                 0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X322_K2_E5                                                         0x002d08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X322_QAHB_CDFE_RATE2_MAX_EYE_DLY_K2_E5                           (0x7f<<0) // Maximum eye delay value for rate2 during dll calibration
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X322_QAHB_CDFE_RATE2_MAX_EYE_DLY_K2_E5_SHIFT                     0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X324_K2_E5                                                         0x002d10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X324_QAHB_CDFE_RATE2_TAP1_PATT_MASK_K2_E5                        (0x7f<<0) // cdfe tap1 training pattern masking bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X324_QAHB_CDFE_RATE2_TAP1_PATT_MASK_K2_E5_SHIFT                  0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X325_K2_E5                                                         0x002d14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X325_QAHB_CDFE_RATE2_TAP2_PATT_MASK_6_0_K2_E5                    (0x7f<<0) // cdfe tap2 training pattern masking bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X325_QAHB_CDFE_RATE2_TAP2_PATT_MASK_6_0_K2_E5_SHIFT              0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X326_K2_E5                                                         0x002d18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X326_QAHB_CDFE_RATE2_TAP3_PATT_MASK_6_0_K2_E5                    (0x7f<<0) // cdfe tap3 training pattern masking bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X326_QAHB_CDFE_RATE2_TAP3_PATT_MASK_6_0_K2_E5_SHIFT              0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X327_K2_E5                                                         0x002d1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X327_QAHB_CDFE_RATE2_TAP4_PATT_MASK_6_0_K2_E5                    (0x7f<<0) // cdfe tap4 training pattern masking bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X327_QAHB_CDFE_RATE2_TAP4_PATT_MASK_6_0_K2_E5_SHIFT              0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X328_K2_E5                                                         0x002d20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X328_QAHB_CDFE_RATE2_TAP5_PATT_MASK_6_0_K2_E5                    (0x7f<<0) // cdfe tap5 training pattern masking bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X328_QAHB_CDFE_RATE2_TAP5_PATT_MASK_6_0_K2_E5_SHIFT              0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X329_K2_E5                                                         0x002d24UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X329_QAHB_CDFE_RATE2_DLEV_PATT_MASK_6_0_K2_E5                    (0x7f<<0) // cdfe dlev training pattern masking bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X329_QAHB_CDFE_RATE2_DLEV_PATT_MASK_6_0_K2_E5_SHIFT              0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X330_K2_E5                                                         0x002d28UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X330_QAHB_CDFE_CMP1_PRESET_OFFSET_5_0_K2_E5                      (0x3f<<0) // cdfe comparator1 offset values ovrride enable bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enables overriding tap2 offset bit[3] : enables overriding tap3 offset bit[4] : enables overriding tap4 offset bit[5] : enables overriding tap5 offset
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X330_QAHB_CDFE_CMP1_PRESET_OFFSET_5_0_K2_E5_SHIFT                0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X331_K2_E5                                                         0x002d2cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X331_QAHB_CDFE_CMP2_PRESET_OFFSET_5_0_K2_E5                      (0x3f<<0) // cdfe comparator2 offset values ovrride enable bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enables overriding tap2 offset bit[3] : enables overriding tap3 offset bit[4] : enables overriding tap4 offset bit[5] : enables overriding tap5 offset
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X331_QAHB_CDFE_CMP2_PRESET_OFFSET_5_0_K2_E5_SHIFT                0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X332_K2_E5                                                         0x002d30UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X332_QAHB_CDFE_CMP3_PRESET_OFFSET_5_0_K2_E5                      (0x3f<<0) // cdfe comparator3 offset values ovrride enable bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enables overriding tap2 offset bit[3] : enables overriding tap3 offset bit[4] : enables overriding tap4 offset bit[5] : enables overriding tap5 offset
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X332_QAHB_CDFE_CMP3_PRESET_OFFSET_5_0_K2_E5_SHIFT                0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X333_K2_E5                                                         0x002d34UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X333_QAHB_CDFE_CMP4_PRESET_OFFSET_5_0_K2_E5                      (0x3f<<0) // cdfe comparator4 offset values ovrride enable bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enables overriding tap2 offset bit[3] : enables overriding tap3 offset bit[4] : enables overriding tap4 offset bit[5] : enables overriding tap5 offset
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X333_QAHB_CDFE_CMP4_PRESET_OFFSET_5_0_K2_E5_SHIFT                0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X338_K2_E5                                                         0x002d48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X338_QAHB_CDFE_COARSE_DLL_ERR_AVG_NUM_6_0_K2_E5                  (0x7f<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X338_QAHB_CDFE_COARSE_DLL_ERR_AVG_NUM_6_0_K2_E5_SHIFT            0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X339_K2_E5                                                         0x002d4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X339_QAHB_CDFE_DLEV_ERR_AVG_NUM_6_0_K2_E5                        (0x7f<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X339_QAHB_CDFE_DLEV_ERR_AVG_NUM_6_0_K2_E5_SHIFT                  0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X341_K2_E5                                                         0x002d54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X341_QAHB_CDFE_COARSE_DLL_ERR_AVG_THRESHOLD_6_0_K2_E5            (0x7f<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X341_QAHB_CDFE_COARSE_DLL_ERR_AVG_THRESHOLD_6_0_K2_E5_SHIFT      0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X342_K2_E5                                                         0x002d58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X342_QAHB_CDFE_DLEV_ERR_AVG_THRESHOLD_K2_E5                      (0x7f<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X342_QAHB_CDFE_DLEV_ERR_AVG_THRESHOLD_K2_E5_SHIFT                0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X344_K2_E5                                                         0x002d60UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X344_QAHB_CDFE_DLL_COARSE_AVG_1_0_K2_E5                          (0x3<<0) // Level of averaging used during cdfe dll coarse calibration 0: last data,  1: avg of last two data,  2: avg of last four data,  3: last data
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X344_QAHB_CDFE_DLL_COARSE_AVG_1_0_K2_E5_SHIFT                    0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X344_QAHB_CDFE_DLL_FINE_AVG_K2_E5                                (0x3<<2) // Level of averaging used during cdfe dll fine calibration 0: last data,  1: avg of last two data,  2: avg of last four data,  3: last data
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X344_QAHB_CDFE_DLL_FINE_AVG_K2_E5_SHIFT                          2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X344_QAHB_CDFE_DLEV_AVG_K2_E5                                    (0x3<<4) // Level of averaging used during cdfe dlev calibration 0: last data,  1: avg of last two data,  2: avg of last four data,  3: last data
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X344_QAHB_CDFE_DLEV_AVG_K2_E5_SHIFT                              4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X346_K2_E5                                                         0x002d68UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X346_QAHB_CDFE_DLL_FINE_OV_COARSE_EN_K2_E5                       (0x1<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X346_QAHB_CDFE_DLL_FINE_OV_COARSE_EN_K2_E5_SHIFT                 0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X346_QAHB_CDFE_DLL_COARSE_OV_FINE_EN_K2_E5                       (0x1<<1) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X346_QAHB_CDFE_DLL_COARSE_OV_FINE_EN_K2_E5_SHIFT                 1
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X347_K2_E5                                                         0x002d6cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X347_QAHB_CDFE_DLEV_TRAINING_PATT_K2_E5                          (0x7f<<0) // cdfe dlev training pattern.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X347_QAHB_CDFE_DLEV_TRAINING_PATT_K2_E5_SHIFT                    0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X348_K2_E5                                                         0x002d70UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X348_QAHB_CDFE_TAP1_TRAINING_PATT_6_0_K2_E5                      (0x7f<<0) // cdfe tap1 training pattern.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X348_QAHB_CDFE_TAP1_TRAINING_PATT_6_0_K2_E5_SHIFT                0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X349_K2_E5                                                         0x002d74UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X349_QAHB_CDFE_TAP2_TRAINING_PATT_6_0_K2_E5                      (0x7f<<0) // cdfe tap2 training pattern.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X349_QAHB_CDFE_TAP2_TRAINING_PATT_6_0_K2_E5_SHIFT                0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X350_K2_E5                                                         0x002d78UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X350_QAHB_CDFE_TAP3_TRAINING_PATT_6_0_K2_E5                      (0x7f<<0) // cdfe tap3 training pattern.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X350_QAHB_CDFE_TAP3_TRAINING_PATT_6_0_K2_E5_SHIFT                0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X351_K2_E5                                                         0x002d7cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X351_QAHB_CDFE_TAP4_TRAINING_PATT_6_0_K2_E5                      (0x7f<<0) // cdfe tap4 training pattern.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X351_QAHB_CDFE_TAP4_TRAINING_PATT_6_0_K2_E5_SHIFT                0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X352_K2_E5                                                         0x002d80UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X352_QAHB_CDFE_TAP5_TRAINING_PATT_6_0_K2_E5                      (0x7f<<0) // cdfe tap5 training pattern.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X352_QAHB_CDFE_TAP5_TRAINING_PATT_6_0_K2_E5_SHIFT                0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X353_K2_E5                                                         0x002d84UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X353_QAHB_CDFE_DLL_COARSE_BOUNCE_K2_E5                           (0xf<<0) // Bounce number for cdfe dll coarse calibration
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X353_QAHB_CDFE_DLL_COARSE_BOUNCE_K2_E5_SHIFT                     0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X354_K2_E5                                                         0x002d88UL //Access:RW   DataWidth:0x8    // Bounce number for cdfe dll fine calibration
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X355_K2_E5                                                         0x002d8cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X355_QAHB_CDFE_DLEV_BOUNCE_K2_E5                                 (0xf<<0) // Bounce number for cdfe dlev calibration
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X355_QAHB_CDFE_DLEV_BOUNCE_K2_E5_SHIFT                           0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X358_K2_E5                                                         0x002d98UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X358_QAHB_CDFE_DLL_COARSE_STEP_K2_E5                             (0xf<<0) // Calibration step size for cdfe dll coarse calibration
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X358_QAHB_CDFE_DLL_COARSE_STEP_K2_E5_SHIFT                       0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X358_QAHB_CDFE_DLEV_STEP_3_0_K2_E5                               (0xf<<4) // Calibration step size for cdfe dlev calibration
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X358_QAHB_CDFE_DLEV_STEP_3_0_K2_E5_SHIFT                         4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X362_K2_E5                                                         0x002da8UL //Access:RW   DataWidth:0x8    // Maximum dlev value for cdfe
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X363_K2_E5                                                         0x002dacUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X363_QAHB_CDFE_TAP1_MAX_6_0_K2_E5                                (0x7f<<0) // Maximum tap1 value for cdfe
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X363_QAHB_CDFE_TAP1_MAX_6_0_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X364_K2_E5                                                         0x002db0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X364_QAHB_CDFE_TAP2_MAX_K2_E5                                    (0x3f<<0) // Maximum tap2 value for cdfe
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X364_QAHB_CDFE_TAP2_MAX_K2_E5_SHIFT                              0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X365_K2_E5                                                         0x002db4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X365_QAHB_CDFE_TAP3_MAX_5_0_K2_E5                                (0x3f<<0) // Maximum tap3 value for cdfe
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X365_QAHB_CDFE_TAP3_MAX_5_0_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X366_K2_E5                                                         0x002db8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X366_QAHB_CDFE_TAP4_MAX_5_0_K2_E5                                (0x3f<<0) // Maximum tap4 value for cdfe
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X366_QAHB_CDFE_TAP4_MAX_5_0_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X367_K2_E5                                                         0x002dbcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X367_QAHB_CDFE_TAP5_MAX_5_0_K2_E5                                (0x3f<<0) // Maximum tap5 value for cdfe
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X367_QAHB_CDFE_TAP5_MAX_5_0_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X367_QAHB_CDFE_CLR_BOUNCE_EN_K2_E5                               (0x1<<6) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X367_QAHB_CDFE_CLR_BOUNCE_EN_K2_E5_SHIFT                         6
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X368_K2_E5                                                         0x002dc0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X368_QAHB_CDFE_RATE2_DFE_CMP_DATA_WAIT_K2_E5                     (0xf<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X368_QAHB_CDFE_RATE2_DFE_CMP_DATA_WAIT_K2_E5_SHIFT               0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X368_QAHB_CDFE_RATE3_DFE_CMP_DATA_WAIT_K2_E5                     (0xf<<4) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X368_QAHB_CDFE_RATE3_DFE_CMP_DATA_WAIT_K2_E5_SHIFT               4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X369_K2_E5                                                         0x002dc4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X369_QAHB_TAP1_CM1_DONT_CARE_O_K2_E5                             (0x3f<<1) // Mask bits for CM1 training pattern
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X369_QAHB_TAP1_CM1_DONT_CARE_O_K2_E5_SHIFT                       1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X369_QAHB_CDFE_SELECT_CLK90_CLK270_ONLY_O_K2_E5                  (0x1<<7) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X369_QAHB_CDFE_SELECT_CLK90_CLK270_ONLY_O_K2_E5_SHIFT            7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X370_K2_E5                                                         0x002dc8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X370_QAHB_TAP1_C1_DONT_CARE_O_K2_E5                              (0x3f<<0) // Mask bits for C1 training pattern
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X370_QAHB_TAP1_C1_DONT_CARE_O_K2_E5_SHIFT                        0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X371_K2_E5                                                         0x002dccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X371_QAHB_CDFE_CMP_SEL_ENA_O_K2_E5                               (0xf<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X371_QAHB_CDFE_CMP_SEL_ENA_O_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X371_QAHB_CDFE_DFE_STROBE_CNT_O_K2_E5                            (0x7<<4) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X371_QAHB_CDFE_DFE_STROBE_CNT_O_K2_E5_SHIFT                      4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X372_K2_E5                                                         0x002dd0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X372_QAHB_CDFE_WAIT_TIMER_1_O_K2_E5                              (0x7<<0) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X372_QAHB_CDFE_WAIT_TIMER_1_O_K2_E5_SHIFT                        0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X372_QAHB_CDFE_FINAL_CMP_WRITE_EN_O_K2_E5                        (0x1<<3) // 
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X372_QAHB_CDFE_FINAL_CMP_WRITE_EN_O_K2_E5_SHIFT                  3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X373_K2_E5                                                         0x002dd4UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_K2_E5                                                         0x002de0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_IDDQ_SD_O_K2_E5                                (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_IDDQ_SD_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_DFE_O_K2_E5                                 (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_DFE_O_K2_E5_SHIFT                           1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_DFE_BIAS_O_K2_E5                            (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_DFE_BIAS_O_K2_E5_SHIFT                      2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_LNREG_O_K2_E5                               (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_LNREG_O_K2_E5_SHIFT                         3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_LNREGH_O_K2_E5                              (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_LNREGH_O_K2_E5_SHIFT                        4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_P2S_O_K2_E5                                 (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_P2S_O_K2_E5_SHIFT                           5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_RA_O_K2_E5                                  (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_RA_O_K2_E5_SHIFT                            6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_S2P_O_K2_E5                                 (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_S2P_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_K2_E5                                                         0x002de4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_SLV_BIAS_O_K2_E5                            (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_SLV_BIAS_O_K2_E5_SHIFT                      0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_TXDRV_O_K2_E5                               (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_TXDRV_O_K2_E5_SHIFT                         1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_TXREG_O_K2_E5                               (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_TXREG_O_K2_E5_SHIFT                         2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_VCO_O_K2_E5                                 (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_VCO_O_K2_E5_SHIFT                           3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_VCO_BUF_O_K2_E5                             (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_VCO_BUF_O_K2_E5_SHIFT                       4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_CDR_O_K2_E5                              (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_CDR_O_K2_E5_SHIFT                        5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_CDR_GCRX_O_K2_E5                         (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_CDR_GCRX_O_K2_E5_SHIFT                   6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_DFE_O_K2_E5                              (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_DFE_O_K2_E5_SHIFT                        7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_K2_E5                                                         0x002de8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_LNREG_O_K2_E5                            (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_LNREG_O_K2_E5_SHIFT                      0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_LNREGH_O_K2_E5                           (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_LNREGH_O_K2_E5_SHIFT                     1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_P2S_O_K2_E5                              (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_P2S_O_K2_E5_SHIFT                        2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_RA_O_K2_E5                               (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_RA_O_K2_E5_SHIFT                         3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_S2P_O_K2_E5                              (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_S2P_O_K2_E5_SHIFT                        4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_VCO_O_K2_E5                              (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_VCO_O_K2_E5_SHIFT                        5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_TXREG_BLEED_ENA_O_K2_E5                        (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_TXREG_BLEED_ENA_O_K2_E5_SHIFT                  6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_TX_LOWPWR_IDLE_ENA_O_K2_E5                     (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT               7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_K2_E5                                                         0x002decUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_CDR_EN_O_K2_E5                                 (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_CDR_EN_O_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RXBCLK_EN_O_K2_E5                              (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RXBCLK_EN_O_K2_E5_SHIFT                        1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RX_GATE_EN_O_K2_E5                             (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RX_GATE_EN_O_K2_E5_SHIFT                       2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RESET_TX_CLKDIV_O_K2_E5                        (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RESET_TX_CLKDIV_O_K2_E5_SHIFT                  3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_K2_E5                                                         0x002df0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_IDDQ_SD_O_K2_E5                                 (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_IDDQ_SD_O_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_DFE_O_K2_E5                                  (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_DFE_O_K2_E5_SHIFT                            1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_DFE_BIAS_O_K2_E5                             (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_DFE_BIAS_O_K2_E5_SHIFT                       2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_LNREG_O_K2_E5                                (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_LNREG_O_K2_E5_SHIFT                          3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_LNREGH_O_K2_E5                               (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_LNREGH_O_K2_E5_SHIFT                         4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_P2S_O_K2_E5                                  (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_P2S_O_K2_E5_SHIFT                            5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_RA_O_K2_E5                                   (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_RA_O_K2_E5_SHIFT                             6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_S2P_O_K2_E5                                  (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_S2P_O_K2_E5_SHIFT                            7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_K2_E5                                                         0x002df4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_SLV_BIAS_O_K2_E5                             (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_SLV_BIAS_O_K2_E5_SHIFT                       0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_TXDRV_O_K2_E5                                (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_TXDRV_O_K2_E5_SHIFT                          1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_TXREG_O_K2_E5                                (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_TXREG_O_K2_E5_SHIFT                          2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_VCO_O_K2_E5                                  (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_VCO_O_K2_E5_SHIFT                            3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_VCO_BUF_O_K2_E5                              (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_VCO_BUF_O_K2_E5_SHIFT                        4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_CDR_O_K2_E5                               (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_CDR_O_K2_E5_SHIFT                         5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_CDR_GCRX_O_K2_E5                          (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_CDR_GCRX_O_K2_E5_SHIFT                    6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_DFE_O_K2_E5                               (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_DFE_O_K2_E5_SHIFT                         7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_K2_E5                                                         0x002df8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_LNREG_O_K2_E5                             (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_LNREG_O_K2_E5_SHIFT                       0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_LNREGH_O_K2_E5                            (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_LNREGH_O_K2_E5_SHIFT                      1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_P2S_O_K2_E5                               (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_P2S_O_K2_E5_SHIFT                         2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_RA_O_K2_E5                                (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_RA_O_K2_E5_SHIFT                          3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_S2P_O_K2_E5                               (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_S2P_O_K2_E5_SHIFT                         4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_VCO_O_K2_E5                               (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_VCO_O_K2_E5_SHIFT                         5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_TXREG_BLEED_ENA_O_K2_E5                         (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_TXREG_BLEED_ENA_O_K2_E5_SHIFT                   6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_TX_LOWPWR_IDLE_ENA_O_K2_E5                      (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT                7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_K2_E5                                                         0x002dfcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_CDR_EN_O_K2_E5                                  (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_CDR_EN_O_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RXBCLK_EN_O_K2_E5                               (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RXBCLK_EN_O_K2_E5_SHIFT                         1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RX_GATE_EN_O_K2_E5                              (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RX_GATE_EN_O_K2_E5_SHIFT                        2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RESET_TX_CLKDIV_O_K2_E5                         (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RESET_TX_CLKDIV_O_K2_E5_SHIFT                   3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_K2_E5                                                         0x002e00UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_IDDQ_SD_O_K2_E5                                 (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_IDDQ_SD_O_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_DFE_O_K2_E5                                  (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_DFE_O_K2_E5_SHIFT                            1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_DFE_BIAS_O_K2_E5                             (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_DFE_BIAS_O_K2_E5_SHIFT                       2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_LNREG_O_K2_E5                                (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_LNREG_O_K2_E5_SHIFT                          3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_LNREGH_O_K2_E5                               (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_LNREGH_O_K2_E5_SHIFT                         4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_P2S_O_K2_E5                                  (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_P2S_O_K2_E5_SHIFT                            5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_RA_O_K2_E5                                   (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_RA_O_K2_E5_SHIFT                             6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_S2P_O_K2_E5                                  (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_S2P_O_K2_E5_SHIFT                            7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_K2_E5                                                         0x002e04UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_SLV_BIAS_O_K2_E5                             (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_SLV_BIAS_O_K2_E5_SHIFT                       0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_TXDRV_O_K2_E5                                (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_TXDRV_O_K2_E5_SHIFT                          1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_TXREG_O_K2_E5                                (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_TXREG_O_K2_E5_SHIFT                          2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_VCO_O_K2_E5                                  (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_VCO_O_K2_E5_SHIFT                            3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_VCO_BUF_O_K2_E5                              (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_VCO_BUF_O_K2_E5_SHIFT                        4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_CDR_O_K2_E5                               (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_CDR_O_K2_E5_SHIFT                         5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_CDR_GCRX_O_K2_E5                          (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_CDR_GCRX_O_K2_E5_SHIFT                    6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_DFE_O_K2_E5                               (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_DFE_O_K2_E5_SHIFT                         7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_K2_E5                                                         0x002e08UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_LNREG_O_K2_E5                             (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_LNREG_O_K2_E5_SHIFT                       0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_LNREGH_O_K2_E5                            (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_LNREGH_O_K2_E5_SHIFT                      1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_P2S_O_K2_E5                               (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_P2S_O_K2_E5_SHIFT                         2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_RA_O_K2_E5                                (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_RA_O_K2_E5_SHIFT                          3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_S2P_O_K2_E5                               (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_S2P_O_K2_E5_SHIFT                         4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_VCO_O_K2_E5                               (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_VCO_O_K2_E5_SHIFT                         5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_TXREG_BLEED_ENA_O_K2_E5                         (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_TXREG_BLEED_ENA_O_K2_E5_SHIFT                   6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_TX_LOWPWR_IDLE_ENA_O_K2_E5                      (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT                7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_K2_E5                                                         0x002e0cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_CDR_EN_O_K2_E5                                  (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_CDR_EN_O_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RXBCLK_EN_O_K2_E5                               (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RXBCLK_EN_O_K2_E5_SHIFT                         1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RX_GATE_EN_O_K2_E5                              (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RX_GATE_EN_O_K2_E5_SHIFT                        2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RESET_TX_CLKDIV_O_K2_E5                         (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RESET_TX_CLKDIV_O_K2_E5_SHIFT                   3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_K2_E5                                                         0x002e10UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_IDDQ_SD_O_K2_E5                                 (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_IDDQ_SD_O_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_DFE_O_K2_E5                                  (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_DFE_O_K2_E5_SHIFT                            1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_DFE_BIAS_O_K2_E5                             (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_DFE_BIAS_O_K2_E5_SHIFT                       2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_LNREG_O_K2_E5                                (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_LNREG_O_K2_E5_SHIFT                          3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_LNREGH_O_K2_E5                               (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_LNREGH_O_K2_E5_SHIFT                         4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_P2S_O_K2_E5                                  (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_P2S_O_K2_E5_SHIFT                            5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_RA_O_K2_E5                                   (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_RA_O_K2_E5_SHIFT                             6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_S2P_O_K2_E5                                  (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_S2P_O_K2_E5_SHIFT                            7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_K2_E5                                                         0x002e14UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_SLV_BIAS_O_K2_E5                             (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_SLV_BIAS_O_K2_E5_SHIFT                       0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_TXDRV_O_K2_E5                                (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_TXDRV_O_K2_E5_SHIFT                          1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_TXREG_O_K2_E5                                (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_TXREG_O_K2_E5_SHIFT                          2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_VCO_O_K2_E5                                  (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_VCO_O_K2_E5_SHIFT                            3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_VCO_BUF_O_K2_E5                              (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_VCO_BUF_O_K2_E5_SHIFT                        4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_CDR_O_K2_E5                               (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_CDR_O_K2_E5_SHIFT                         5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_CDR_GCRX_O_K2_E5                          (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_CDR_GCRX_O_K2_E5_SHIFT                    6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_DFE_O_K2_E5                               (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_DFE_O_K2_E5_SHIFT                         7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_K2_E5                                                         0x002e18UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_LNREG_O_K2_E5                             (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_LNREG_O_K2_E5_SHIFT                       0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_LNREGH_O_K2_E5                            (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_LNREGH_O_K2_E5_SHIFT                      1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_P2S_O_K2_E5                               (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_P2S_O_K2_E5_SHIFT                         2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_RA_O_K2_E5                                (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_RA_O_K2_E5_SHIFT                          3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_S2P_O_K2_E5                               (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_S2P_O_K2_E5_SHIFT                         4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_VCO_O_K2_E5                               (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_VCO_O_K2_E5_SHIFT                         5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_TXREG_BLEED_ENA_O_K2_E5                         (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_TXREG_BLEED_ENA_O_K2_E5_SHIFT                   6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_TX_LOWPWR_IDLE_ENA_O_K2_E5                      (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT                7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_K2_E5                                                         0x002e1cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_CDR_EN_O_K2_E5                                  (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_CDR_EN_O_K2_E5_SHIFT                            0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RXBCLK_EN_O_K2_E5                               (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RXBCLK_EN_O_K2_E5_SHIFT                         1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RX_GATE_EN_O_K2_E5                              (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RX_GATE_EN_O_K2_E5_SHIFT                        2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RESET_TX_CLKDIV_O_K2_E5                         (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RESET_TX_CLKDIV_O_K2_E5_SHIFT                   3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X392_K2_E5                                                         0x002e20UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X392_MSM_PROG_MULT_DELAY_IDDQ_RESET_1_4_0_K2_E5                  (0x1f<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X392_MSM_PROG_MULT_DELAY_IDDQ_RESET_1_4_0_K2_E5_SHIFT            0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X394_K2_E5                                                         0x002e28UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X394_MSM_PROG_MULT_DELAY_IDDQ_RESET_2_4_0_K2_E5                  (0x1f<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X394_MSM_PROG_MULT_DELAY_IDDQ_RESET_2_4_0_K2_E5_SHIFT            0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_K2_E5                                                         0x002e44UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_L0_MASTER_CDN_O_K2_E5                                       (0x1<<0) // Lane0 master reset
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_L0_MASTER_CDN_O_K2_E5_SHIFT                                 0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_L1_MASTER_CDN_O_K2_E5                                       (0x1<<1) // Lane1 master reset
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_L1_MASTER_CDN_O_K2_E5_SHIFT                                 1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_L2_MASTER_CDN_O_K2_E5                                       (0x1<<2) // Lane2 master reset
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_L2_MASTER_CDN_O_K2_E5_SHIFT                                 2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_L3_MASTER_CDN_O_K2_E5                                       (0x1<<3) // Lane3 master reset
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_L3_MASTER_CDN_O_K2_E5_SHIFT                                 3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X402_K2_E5                                                         0x002e48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X402_FAST_SIM_O_K2_E5                                            (0x1<<0) // fast_sim_register
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X402_FAST_SIM_O_K2_E5_SHIFT                                      0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X403_K2_E5                                                         0x002e4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X403_TBUS_DFE_CMP_SEL_O_2_0_K2_E5                                (0x7<<0) // Selects which comparator offsets come out on tbus
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X403_TBUS_DFE_CMP_SEL_O_2_0_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X403_TXDP_IDLE_IN_DELAY_K2_E5                                    (0x3<<3) // Controls the number of clk cycles delay from data_en of p2s_rbuf to propagate to the idle_in of txdp_control_dig 0 is 2 cycles celay, 3 is 5 cycles delay
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X403_TXDP_IDLE_IN_DELAY_K2_E5_SHIFT                              3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X404_K2_E5                                                         0x002e50UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X405_K2_E5                                                         0x002e54UL //Access:RW   DataWidth:0x8    // 
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X406_K2_E5                                                         0x002e58UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X406_MODE_I_2_0_K2_E5                                            (0x7<<0) // 1000Base-KX Mode status for CPU
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X406_MODE_I_2_0_K2_E5_SHIFT                                      0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X406_CMU_OK_I_0_K2_E5                                            (0x1<<3) // CMU OK Status
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X406_CMU_OK_I_0_K2_E5_SHIFT                                      3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X406_CMU1_OK_I_1_K2_E5                                           (0x1<<4) // CMU1 OK Status
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X406_CMU1_OK_I_1_K2_E5_SHIFT                                     4
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_K2_E5                                                         0x002e5cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN0_SIG_LEVEL_VALID_I_0_K2_E5                               (0x1<<0) // Lane 0 Signal Detect Valid Status
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN0_SIG_LEVEL_VALID_I_0_K2_E5_SHIFT                         0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN1_SIG_LEVEL_VALID_I_1_K2_E5                               (0x1<<1) // Lane 1 Signal Detect Valid Status
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN1_SIG_LEVEL_VALID_I_1_K2_E5_SHIFT                         1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN2_SIG_LEVEL_VALID_I_2_K2_E5                               (0x1<<2) // Lane 2 Signal Detect Valid Status
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN2_SIG_LEVEL_VALID_I_2_K2_E5_SHIFT                         2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN3_SIG_LEVEL_VALID_I_3_K2_E5                               (0x1<<3) // Lane 3 Signal Detect Valid Status
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN3_SIG_LEVEL_VALID_I_3_K2_E5_SHIFT                         3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN0_OK_I_4_K2_E5                                            (0x1<<4) // Lane 0 OK Status
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN0_OK_I_4_K2_E5_SHIFT                                      4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN1_OK_I_5_K2_E5                                            (0x1<<5) // Lane 1 OK Status
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN1_OK_I_5_K2_E5_SHIFT                                      5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN2_OK_I_6_K2_E5                                            (0x1<<6) // Lane 2 OK Status
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN2_OK_I_6_K2_E5_SHIFT                                      6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN3_OK_I_7_K2_E5                                            (0x1<<7) // Lane 3 OK Status
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN3_OK_I_7_K2_E5_SHIFT                                      7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X408_K2_E5                                                         0x002e60UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X408_LN0_RX_LOCKED_I_1_0_K2_E5                                   (0x3<<0) // Lane 0 RX Locked status
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X408_LN0_RX_LOCKED_I_1_0_K2_E5_SHIFT                             0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X408_LN1_RX_LOCKED_I_3_2_K2_E5                                   (0x3<<2) // Lane 1 RX Locked Status
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X408_LN1_RX_LOCKED_I_3_2_K2_E5_SHIFT                             2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X408_LN2_RX_LOCKED_I_5_4_K2_E5                                   (0x3<<4) // Lane 2 RX Locked Status
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X408_LN2_RX_LOCKED_I_5_4_K2_E5_SHIFT                             4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X408_LN3_RX_LOCKED_I_7_6_K2_E5                                   (0x3<<6) // Lane 3 RX Locked Status
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X408_LN3_RX_LOCKED_I_7_6_K2_E5_SHIFT                             6
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X409_K2_E5                                                         0x002e64UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X409_EI_GLUE_EN_O_K2_E5                                          (0x1<<0) // Unused
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X409_EI_GLUE_EN_O_K2_E5_SHIFT                                    0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_K2_E5                                                         0x002e68UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_GEN12_ONLY_O_K2_E5                                          (0x1<<0) // Newly added for PCIe3 1CMU
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_GEN12_ONLY_O_K2_E5_SHIFT                                    0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RESETN_RESET_CMU_EN_O_K2_E5                            (0x1<<1) // Newly added for PCIe3 1CMU
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RESETN_RESET_CMU_EN_O_K2_E5_SHIFT                      1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RATE_CHNG_OVR_EN_O_K2_E5                               (0x1<<2) // Newly added for PCIe3 1CMU
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RATE_CHNG_OVR_EN_O_K2_E5_SHIFT                         2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RATE_CHNG_OVR_O_K2_E5                                  (0x1<<3) // Newly added for PCIe3 1CMU
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RATE_CHNG_OVR_O_K2_E5_SHIFT                            3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_GEN3_CAL_DONE_OVR_EN_O_K2_E5                           (0x1<<4) // Newly added for PCIe3 1CMU
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_GEN3_CAL_DONE_OVR_EN_O_K2_E5_SHIFT                     4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_GEN3_CAL_DONE_OVR_O_K2_E5                              (0x1<<5) // Newly added for PCIe3 1CMU
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_GEN3_CAL_DONE_OVR_O_K2_E5_SHIFT                        5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RATE_IS_GEN3_OVR_EN_O_K2_E5                            (0x1<<6) // Newly added for PCIe3 1CMU
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RATE_IS_GEN3_OVR_EN_O_K2_E5_SHIFT                      6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RATE_IS_GEN3_OVR_O_K2_E5                               (0x1<<7) // Newly added for PCIe3 1CMU
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RATE_IS_GEN3_OVR_O_K2_E5_SHIFT                         7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X411_K2_E5                                                         0x002e6cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X411_LANE_EN_O_3_0_K2_E5                                         (0xf<<0) // Newly added for PCIe3 1CMU
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X411_LANE_EN_O_3_0_K2_E5_SHIFT                                   0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X411_LANE_RESETN_OVR_EN_O_K2_E5                                  (0x1<<4) // Newly added for PCIe3 1CMU
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X411_LANE_RESETN_OVR_EN_O_K2_E5_SHIFT                            4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X411_LANE_RESETN_OVR_O_K2_E5                                     (0x1<<5) // Newly added for PCIe3 1CMU
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X411_LANE_RESETN_OVR_O_K2_E5_SHIFT                               5
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X413_K2_E5                                                         0x002e74UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X413_TXPRESET_COEFF_P0C_O_K2_E5                                  (0x3f<<0) // txpreset_coeff P0 C
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X413_TXPRESET_COEFF_P0C_O_K2_E5_SHIFT                            0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X414_K2_E5                                                         0x002e78UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X414_TXPRESET_COEFF_P0CM1_O_K2_E5                                (0x3f<<0) // txpreset_coeff P0 C-1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X414_TXPRESET_COEFF_P0CM1_O_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X415_K2_E5                                                         0x002e7cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X415_TXPRESET_COEFF_P0CP1_O_K2_E5                                (0x3f<<0) // txpreset_coeff P0 C+1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X415_TXPRESET_COEFF_P0CP1_O_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X416_K2_E5                                                         0x002e80UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X416_TXPRESET_COEFF_P1C_O_K2_E5                                  (0x3f<<0) // txpreset_coeff P1 C
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X416_TXPRESET_COEFF_P1C_O_K2_E5_SHIFT                            0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X417_K2_E5                                                         0x002e84UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X417_TXPRESET_COEFF_P1CM1_O_K2_E5                                (0x3f<<0) // txpreset_coeff P1 C-1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X417_TXPRESET_COEFF_P1CM1_O_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X418_K2_E5                                                         0x002e88UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X418_TXPRESET_COEFF_P1CP1_O_K2_E5                                (0x3f<<0) // txpreset_coeff P1 C+1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X418_TXPRESET_COEFF_P1CP1_O_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X419_K2_E5                                                         0x002e8cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X419_TXPRESET_COEFF_P2C_O_K2_E5                                  (0x3f<<0) // txpreset_coeff P2 C
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X419_TXPRESET_COEFF_P2C_O_K2_E5_SHIFT                            0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X420_K2_E5                                                         0x002e90UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X420_TXPRESET_COEFF_P2CM1_O_K2_E5                                (0x3f<<0) // txpreset_coeff P2 C-1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X420_TXPRESET_COEFF_P2CM1_O_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X421_K2_E5                                                         0x002e94UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X421_TXPRESET_COEFF_P2CP1_O_K2_E5                                (0x3f<<0) // txpreset_coeff P2 C+1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X421_TXPRESET_COEFF_P2CP1_O_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X422_K2_E5                                                         0x002e98UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X422_TXPRESET_COEFF_P3C_O_K2_E5                                  (0x3f<<0) // txpreset_coeff P3 C
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X422_TXPRESET_COEFF_P3C_O_K2_E5_SHIFT                            0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X423_K2_E5                                                         0x002e9cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X423_TXPRESET_COEFF_P3CM1_O_K2_E5                                (0x3f<<0) // txpreset_coeff P3 C-1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X423_TXPRESET_COEFF_P3CM1_O_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X424_K2_E5                                                         0x002ea0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X424_TXPRESET_COEFF_P3CP1_O_K2_E5                                (0x3f<<0) // txpreset_coeff P3 C+1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X424_TXPRESET_COEFF_P3CP1_O_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X425_K2_E5                                                         0x002ea4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X425_TXPRESET_COEFF_P4C_O_K2_E5                                  (0x3f<<0) // txpreset_coeff P4 C
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X425_TXPRESET_COEFF_P4C_O_K2_E5_SHIFT                            0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X426_K2_E5                                                         0x002ea8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X426_TXPRESET_COEFF_P4CM1_O_K2_E5                                (0x3f<<0) // txpreset_coeff P4 C-1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X426_TXPRESET_COEFF_P4CM1_O_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X427_K2_E5                                                         0x002eacUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X427_TXPRESET_COEFF_P4CP1_O_K2_E5                                (0x3f<<0) // txpreset_coeff P4 C+1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X427_TXPRESET_COEFF_P4CP1_O_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X428_K2_E5                                                         0x002eb0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X428_TXPRESET_COEFF_P5C_O_K2_E5                                  (0x3f<<0) // txpreset_coeff P5 C
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X428_TXPRESET_COEFF_P5C_O_K2_E5_SHIFT                            0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X429_K2_E5                                                         0x002eb4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X429_TXPRESET_COEFF_P5CM1_O_K2_E5                                (0x3f<<0) // txpreset_coeff P5 C-1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X429_TXPRESET_COEFF_P5CM1_O_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X430_K2_E5                                                         0x002eb8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X430_TXPRESET_COEFF_P5CP1_O_K2_E5                                (0x3f<<0) // txpreset_coeff P5 C+1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X430_TXPRESET_COEFF_P5CP1_O_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X431_K2_E5                                                         0x002ebcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X431_TXPRESET_COEFF_P6C_O_K2_E5                                  (0x3f<<0) // txpreset_coeff P6 C
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X431_TXPRESET_COEFF_P6C_O_K2_E5_SHIFT                            0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X432_K2_E5                                                         0x002ec0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X432_TXPRESET_COEFF_P6CM1_O_K2_E5                                (0x3f<<0) // txpreset_coeff P6 C-1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X432_TXPRESET_COEFF_P6CM1_O_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X433_K2_E5                                                         0x002ec4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X433_TXPRESET_COEFF_P6CP1_O_K2_E5                                (0x3f<<0) // txpreset_coeff P6 C+1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X433_TXPRESET_COEFF_P6CP1_O_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X434_K2_E5                                                         0x002ec8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X434_TXPRESET_COEFF_P7C_O_K2_E5                                  (0x3f<<0) // txpreset_coeff P7 C
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X434_TXPRESET_COEFF_P7C_O_K2_E5_SHIFT                            0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X435_K2_E5                                                         0x002eccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X435_TXPRESET_COEFF_P7CM1_O_K2_E5                                (0x3f<<0) // txpreset_coeff P7 C-1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X435_TXPRESET_COEFF_P7CM1_O_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X436_K2_E5                                                         0x002ed0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X436_TXPRESET_COEFF_P7CP1_O_K2_E5                                (0x3f<<0) // txpreset_coeff P7 C+1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X436_TXPRESET_COEFF_P7CP1_O_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X437_K2_E5                                                         0x002ed4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X437_TXPRESET_COEFF_P8C_O_K2_E5                                  (0x3f<<0) // txpreset_coeff P8 C
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X437_TXPRESET_COEFF_P8C_O_K2_E5_SHIFT                            0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X438_K2_E5                                                         0x002ed8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X438_TXPRESET_COEFF_P8CM1_O_K2_E5                                (0x3f<<0) // txpreset_coeff P8 C-1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X438_TXPRESET_COEFF_P8CM1_O_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X439_K2_E5                                                         0x002edcUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X439_TXPRESET_COEFF_P8CP1_O_K2_E5                                (0x3f<<0) // txpreset_coeff P8 C+1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X439_TXPRESET_COEFF_P8CP1_O_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X440_K2_E5                                                         0x002ee0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X440_TXPRESET_COEFF_P9C_O_K2_E5                                  (0x3f<<0) // txpreset_coeff P9 C
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X440_TXPRESET_COEFF_P9C_O_K2_E5_SHIFT                            0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X441_K2_E5                                                         0x002ee4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X441_TXPRESET_COEFF_P9CM1_O_K2_E5                                (0x3f<<0) // txpreset_coeff P9 C-1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X441_TXPRESET_COEFF_P9CM1_O_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X442_K2_E5                                                         0x002ee8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X442_TXPRESET_COEFF_P9CP1_O_K2_E5                                (0x3f<<0) // txpreset_coeff P9 C+1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X442_TXPRESET_COEFF_P9CP1_O_K2_E5_SHIFT                          0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X443_K2_E5                                                         0x002eecUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X443_TXPRESET_COEFF_P10C_O_K2_E5                                 (0x3f<<0) // txpreset_coeff P10 C
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X443_TXPRESET_COEFF_P10C_O_K2_E5_SHIFT                           0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X444_K2_E5                                                         0x002ef0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X444_TXPRESET_COEFF_P10CM1_O_K2_E5                               (0x3f<<0) // txpreset_coeff P10 C-1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X444_TXPRESET_COEFF_P10CM1_O_K2_E5_SHIFT                         0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X445_K2_E5                                                         0x002ef4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X445_TXPRESET_COEFF_P10CP1_O_K2_E5                               (0x3f<<0) // txpreset_coeff P10 C+1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X445_TXPRESET_COEFF_P10CP1_O_K2_E5_SHIFT                         0
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X446_K2_E5                                                         0x002ef8UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X447_K2_E5                                                         0x002efcUL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X448_K2_E5                                                         0x002f00UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X449_K2_E5                                                         0x002f04UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X450_K2_E5                                                         0x002f08UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X451_K2_E5                                                         0x002f0cUL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X452_K2_E5                                                         0x002f10UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X453_K2_E5                                                         0x002f14UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X454_K2_E5                                                         0x002f18UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X455_K2_E5                                                         0x002f1cUL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X456_K2_E5                                                         0x002f20UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X457_K2_E5                                                         0x002f24UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X458_K2_E5                                                         0x002f28UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X459_K2_E5                                                         0x002f2cUL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X460_K2_E5                                                         0x002f30UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X461_K2_E5                                                         0x002f34UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X462_K2_E5                                                         0x002f38UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X463_K2_E5                                                         0x002f3cUL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X464_K2_E5                                                         0x002f40UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X465_K2_E5                                                         0x002f44UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X466_K2_E5                                                         0x002f48UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X467_K2_E5                                                         0x002f4cUL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X468_K2_E5                                                         0x002f50UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X469_K2_E5                                                         0x002f54UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X470_K2_E5                                                         0x002f58UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X471_K2_E5                                                         0x002f5cUL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X472_K2_E5                                                         0x002f60UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X473_K2_E5                                                         0x002f64UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X474_K2_E5                                                         0x002f68UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X475_K2_E5                                                         0x002f6cUL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X476_K2_E5                                                         0x002f70UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X477_K2_E5                                                         0x002f74UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X478_K2_E5                                                         0x002f78UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X479_K2_E5                                                         0x002f7cUL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X480_K2_E5                                                         0x002f80UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X481_K2_E5                                                         0x002f84UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X482_K2_E5                                                         0x002f88UL //Access:RW   DataWidth:0x8    // MSM Lane Dbank Data
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_K2_E5                                                         0x002f8cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_PD_LNREGH_O_K2_E5                             (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_PD_LNREGH_O_K2_E5_SHIFT                       0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_PD_VCO_BUF_O_K2_E5                            (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_PD_VCO_BUF_O_K2_E5_SHIFT                      1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_CDR_GCRX_O_K2_E5                        (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_CDR_GCRX_O_K2_E5_SHIFT                  2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RX_GATE_EN_O_K2_E5                            (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RX_GATE_EN_O_K2_E5_SHIFT                      3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_LNREG_O_K2_E5                           (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_LNREG_O_K2_E5_SHIFT                     4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_P2S_O_K2_E5                             (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_P2S_O_K2_E5_SHIFT                       5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_S2P_O_K2_E5                             (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_S2P_O_K2_E5_SHIFT                       6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_CDR_O_K2_E5                             (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_CDR_O_K2_E5_SHIFT                       7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_K2_E5                                                         0x002f90UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_DFE_O_K2_E5                             (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_DFE_O_K2_E5_SHIFT                       0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_VCO_O_K2_E5                             (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_VCO_O_K2_E5_SHIFT                       1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_RA_O_K2_E5                              (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_RA_O_K2_E5_SHIFT                        2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_LNREGH_O_K2_E5                          (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_LNREGH_O_K2_E5_SHIFT                    3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_DFE_O_K2_E5                                (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_DFE_O_K2_E5_SHIFT                          4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_LNREG_O_K2_E5                              (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_LNREG_O_K2_E5_SHIFT                        5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_P2S_O_K2_E5                                (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_P2S_O_K2_E5_SHIFT                          6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_RA_O_K2_E5                                 (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_RA_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_K2_E5                                                         0x002f94UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_S2P_O_K2_E5                                (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_S2P_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_SLV_BIAS_O_K2_E5                           (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_SLV_BIAS_O_K2_E5_SHIFT                     1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_TXDRV_O_K2_E5                              (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_TXDRV_O_K2_E5_SHIFT                        2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_VCO_O_K2_E5                                (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_VCO_O_K2_E5_SHIFT                          3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_DFE_BIAS_O_K2_E5                           (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_DFE_BIAS_O_K2_E5_SHIFT                     4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_IDDQ_SD_O_K2_E5                               (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_IDDQ_SD_O_K2_E5_SHIFT                         5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_CDR_EN_O_K2_E5                                (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_CDR_EN_O_K2_E5_SHIFT                          6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_RXBCLK_EN_O_K2_E5                             (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_RXBCLK_EN_O_K2_E5_SHIFT                       7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_K2_E5                                                         0x002f98UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_TX_LOWPWR_IDLE_ENA_O_K2_E5                    (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT              0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_TXREG_BLEED_ENA_O_K2_E5                       (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_TXREG_BLEED_ENA_O_K2_E5_SHIFT                 1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_PD_TXREG_O_K2_E5                              (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_PD_TXREG_O_K2_E5_SHIFT                        2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_RESET_TX_CLKDIV_O_K2_E5                       (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_RESET_TX_CLKDIV_O_K2_E5_SHIFT                 3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_K2_E5                                                         0x002f9cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_PD_LNREGH_O_K2_E5                             (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_PD_LNREGH_O_K2_E5_SHIFT                       0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_PD_VCO_BUF_O_K2_E5                            (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_PD_VCO_BUF_O_K2_E5_SHIFT                      1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_GCRX_O_K2_E5                        (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_GCRX_O_K2_E5_SHIFT                  2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RX_GATE_EN_O_K2_E5                            (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RX_GATE_EN_O_K2_E5_SHIFT                      3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_LNREG_O_K2_E5                           (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_LNREG_O_K2_E5_SHIFT                     4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_P2S_O_K2_E5                             (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_P2S_O_K2_E5_SHIFT                       5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_S2P_O_K2_E5                             (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_S2P_O_K2_E5_SHIFT                       6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_O_K2_E5                             (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_O_K2_E5_SHIFT                       7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_K2_E5                                                         0x002fa0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_DFE_O_K2_E5                             (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_DFE_O_K2_E5_SHIFT                       0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_VCO_O_K2_E5                             (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_VCO_O_K2_E5_SHIFT                       1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_RA_O_K2_E5                              (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_RA_O_K2_E5_SHIFT                        2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_LNREGH_O_K2_E5                          (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_LNREGH_O_K2_E5_SHIFT                    3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_DFE_O_K2_E5                                (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_DFE_O_K2_E5_SHIFT                          4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_LNREG_O_K2_E5                              (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_LNREG_O_K2_E5_SHIFT                        5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_P2S_O_K2_E5                                (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_P2S_O_K2_E5_SHIFT                          6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_RA_O_K2_E5                                 (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_RA_O_K2_E5_SHIFT                           7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_K2_E5                                                         0x002fa4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_S2P_O_K2_E5                                (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_S2P_O_K2_E5_SHIFT                          0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_SLV_BIAS_O_K2_E5                           (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_SLV_BIAS_O_K2_E5_SHIFT                     1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_TXDRV_O_K2_E5                              (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_TXDRV_O_K2_E5_SHIFT                        2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_VCO_O_K2_E5                                (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_VCO_O_K2_E5_SHIFT                          3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_DFE_BIAS_O_K2_E5                           (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_DFE_BIAS_O_K2_E5_SHIFT                     4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_IDDQ_SD_O_K2_E5                               (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_IDDQ_SD_O_K2_E5_SHIFT                         5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_CDR_EN_O_K2_E5                                (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_CDR_EN_O_K2_E5_SHIFT                          6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_RESET_TX_CLKDIV_O_K2_E5                       (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_RESET_TX_CLKDIV_O_K2_E5_SHIFT                 7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_K2_E5                                                         0x002fa8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_RXBCLK_EN_O_K2_E5                             (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_RXBCLK_EN_O_K2_E5_SHIFT                       0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_TX_LOWPWR_IDLE_ENA_O_K2_E5                    (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT              1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_TXREG_BLEED_ENA_O_K2_E5                       (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_TXREG_BLEED_ENA_O_K2_E5_SHIFT                 2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_PD_TXREG_O_K2_E5                              (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_PD_TXREG_O_K2_E5_SHIFT                        3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_K2_E5                                                         0x002facUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_PD_LNREGH_O_K2_E5                             (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_PD_LNREGH_O_K2_E5_SHIFT                       0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_PD_VCO_BUF_O_K2_E5                            (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_PD_VCO_BUF_O_K2_E5_SHIFT                      1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_CDR_GCRX_O_K2_E5                        (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_CDR_GCRX_O_K2_E5_SHIFT                  2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RX_GATE_EN_O_K2_E5                            (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RX_GATE_EN_O_K2_E5_SHIFT                      3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_LNREG_O_K2_E5                           (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_LNREG_O_K2_E5_SHIFT                     4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_P2S_O_K2_E5                             (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_P2S_O_K2_E5_SHIFT                       5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_S2P_O_K2_E5                             (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_S2P_O_K2_E5_SHIFT                       6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_TX_CLKDIV_O_K2_E5                       (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_TX_CLKDIV_O_K2_E5_SHIFT                 7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_K2_E5                                                         0x002fb0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_CDR_O_K2_E5                             (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_CDR_O_K2_E5_SHIFT                       0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_DFE_O_K2_E5                             (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_DFE_O_K2_E5_SHIFT                       1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_VCO_O_K2_E5                             (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_VCO_O_K2_E5_SHIFT                       2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_RA_O_K2_E5                              (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_RA_O_K2_E5_SHIFT                        3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_LNREGH_O_K2_E5                          (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_LNREGH_O_K2_E5_SHIFT                    4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_DFE_O_K2_E5                                (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_DFE_O_K2_E5_SHIFT                          5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_LNREG_O_K2_E5                              (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_LNREG_O_K2_E5_SHIFT                        6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_P2S_O_K2_E5                                (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_P2S_O_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_K2_E5                                                         0x002fb4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_RA_O_K2_E5                                 (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_RA_O_K2_E5_SHIFT                           0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_S2P_O_K2_E5                                (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_S2P_O_K2_E5_SHIFT                          1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_SLV_BIAS_O_K2_E5                           (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_SLV_BIAS_O_K2_E5_SHIFT                     2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_TXDRV_O_K2_E5                              (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_TXDRV_O_K2_E5_SHIFT                        3
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_VCO_O_K2_E5                                (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_VCO_O_K2_E5_SHIFT                          4
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_DFE_BIAS_O_K2_E5                           (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_DFE_BIAS_O_K2_E5_SHIFT                     5
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_IDDQ_SD_O_K2_E5                               (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_IDDQ_SD_O_K2_E5_SHIFT                         6
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_CDR_EN_O_K2_E5                                (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_CDR_EN_O_K2_E5_SHIFT                          7
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_K2_E5                                                         0x002fb8UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_RXBCLK_EN_O_K2_E5                             (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_RXBCLK_EN_O_K2_E5_SHIFT                       0
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_TX_LOWPWR_IDLE_ENA_O_K2_E5                    (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT              1
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_TXREG_BLEED_ENA_O_K2_E5                       (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_TXREG_BLEED_ENA_O_K2_E5_SHIFT                 2
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_PD_TXREG_O_K2_E5                              (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_PD_TXREG_O_K2_E5_SHIFT                        3
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X495_K2_E5                                                         0x002fbcUL //Access:RW   DataWidth:0x8    // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X496_K2_E5                                                         0x002fc0UL //Access:RW   DataWidth:0x8    // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X497_K2_E5                                                         0x002fc4UL //Access:RW   DataWidth:0x8    // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X498_K2_E5                                                         0x002fc8UL //Access:RW   DataWidth:0x8    // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+#define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X499_K2_E5                                                         0x002fccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X499_PROG_MULT_REF_CLK_WAIT_O_K2_E5                              (0x7<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
+  #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X499_PROG_MULT_REF_CLK_WAIT_O_K2_E5_SHIFT                        0
+#define MISC_REG_RESET_CONFIG                                                                                0x008040UL //Access:RW   DataWidth:0x20   // Reset configuration register. inside order of the bits is: [0] rst_pswrq_auto_mode (0- no auto deassertion; 1 - auto deassertion); [1] rst_pswrd_auto_mode (0- no auto deassertion; 1 - auto deassertion); [2] rst_pswwr_auto_mode (0- no auto deassertion; 1 - auto deassertion); [3] rst_pswhst_auto_mode (0- no auto deassertion; 1 - auto deassertion); [4] reserved; [5] rst_rbcp_auto_mode (0- no auto deassertion; 1 - auto deassertion); [6] rst_dmae_assert_on_core_rst(0 - no; 1 - yes); [7-12] reserved; [13] rst_dbg_auto_mode (0- no auto deassertion; 1 - auto deassertion); [14] rst_misc_core_auto_mode (0- no auto deassertion; 1 - auto deassertion); [15] reserved; [16] grc_reset_assert_on_core_rst (0 - no; 1 - yes); [17] reserved; [18] rst_rbcz_assert_on_core_rst(0 - no; 1 - yes); [19] rst_rbc{n|h}_assert_on_core_rst(0 - no; 1 - yes); [20] rst_dbg_assert_on_core_rst (0 - no; 1 - yes); [21] rst_misc_core_assert_on_core_rst (0 - no; 1 - yes); [22] rst_wol_assert_on_core_rst; [23]wrappers_iddq_and_rst_signals_assert_on_core_rst (0 - no; 1 - yes); [24] rst_atc_auto_mode (0- no auto deassertion;1 - auto deassertion); [25] rst_clk_pb_auto_mode (0- no auto deassertion;1 - auto deassertion); [26-31] reserved; Reset on hard reset.
+#define MISC_REG_RESET_PL_UA                                                                                 0x008050UL //Access:RW   DataWidth:0x20   // Reset_reg: Non-shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0"  resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_misc_core; [1] rst_grc; [2] rst_rbcn; [3] rst_rbcz; [4] reserved;
+#define MISC_REG_RESET_PL_UA_SIZE                                                                            3
+#define MISC_REG_RESET_PL_HV                                                                                 0x008060UL //Access:RW   DataWidth:0x20   // Reset_reg: Non-shared blocks which can be reset also by driver in HV (PL=HV); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0"  resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_pswhst; [1] rst_pswrq; [2] rst_pswrd; [3] rst_pswwr; [4] rst_atc; [5] rst_clk_pb;
+#define MISC_REG_RESET_PL_HV_SIZE                                                                            3
+#define MISC_REG_RESET_PL_PDA_VMAIN_1                                                                        0x008070UL //Access:RW   DataWidth:0x20   // Reset_reg: Unprotected non-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers (PL=PDA) Vmain domain; Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0"  resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_brb; [1] rst_prs; [2] rst_src; [3] rst_tsdm; [4] rst_tsem; [5] rst_tcm; [6] rst_rbcr;[7] rst_usdm; [8]rst_ucm; [9] rst_usem; [10] rst_btb; [11] rst_pbf_pb1; [12] rst_pbf_pb2; [13] rst_rpb; [14] rst_rbcu; [15] rst_pbf; [16] rst_qm; [17] rst_tm; [18] rst_dorq; [19] rst_xcm; [20] rst_xsdm; [21] rst_xsem; [22] rst_rbct; [23] rst_cdu; [24] rst_ccfc;[25] rst_tcfc;[26] rst_rbcp; [27] rst_igu; [28] rst_dmae; [29] rst_semi_rtc;.
+#define MISC_REG_RESET_PL_PDA_VMAIN_1_SIZE                                                                   3
+#define MISC_REG_RESET_PL_PDA_VMAIN_2                                                                        0x008080UL //Access:RW   DataWidth:0x20   // Reset_reg: Unprotected non-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers (PL=PDA) Vmain domain; Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0"  resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_rbcf; [1] rst_rbcx; [2] rst_rbcs; [3] rst_mcm; [4] rst_pcm; [5] rst_ycm; [6] rst_msdm; [7] rst_psdm; [8] rst_ysdm;  [9] rst_msem; [10] rst_psem; [11] rst_ysem; [12] rst_xyld; [13] rst_tmld; [14] rst_muld; [15] Reserved; [16] rst_rdif; [17] rst_tdif; [18] rst_rss; [19] rst_cau; [20] rst_ptu; [21] rst_prm; [22] rst_rbcy; [23] rst_rbcq; [24] rst_rbcm; [25] rst_rbcb; [26] rst_rbcv; [26] rst_ypld; [27] rst_ptld; [28] rst_rgfs; [26] rst_tgfs; [31] Reserved.
+#define MISC_REG_RESET_PL_PDA_VMAIN_2_SIZE                                                                   3
+#define MISC_REG_RESET_PL_PDA_VAUX                                                                           0x008090UL //Access:RW   DataWidth:0x20   // Reset_reg: Unprotected non-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers (PL=PDA) Vaux domain; Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0"  resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_nig; [1] rst_rbch; [2] rst_nig_hard; [3] rst_dbg; [6:4] reserved; [7] rst_wol; [8] rst_wol_hard; [9] rst_bmbn;
+#define MISC_REG_RESET_PL_PDA_VAUX_SIZE                                                                      3
+#define MISC_REG_RESET_PL_UA_VMAIN_BB                                                                        0x0080a0UL //Access:RW   DataWidth:0x4    // Reset_reg: Non-shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0"  resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_vmain_pd_ars;
+#define MISC_REG_RESET_PL_UA_VMAIN_SIZE                                                                      3
+#define MISC_REG_INT_STS                                                                                     0x008180UL //Access:R    DataWidth:0x1    // Multi Field Register.
+  #define MISC_REG_INT_STS_ADDRESS_ERROR                                                                     (0x1<<0) // Signals an unknown address to the rf module.
+  #define MISC_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                               0
+#define MISC_REG_INT_MASK                                                                                    0x008184UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define MISC_REG_INT_MASK_ADDRESS_ERROR                                                                    (0x1<<0) // This bit masks, when set, the Interrupt bit: MISC_REG_INT_STS.ADDRESS_ERROR .
+  #define MISC_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                              0
+#define MISC_REG_INT_STS_WR                                                                                  0x008188UL //Access:WR   DataWidth:0x1    // Multi Field Register.
+  #define MISC_REG_INT_STS_WR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define MISC_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                            0
+#define MISC_REG_INT_STS_CLR                                                                                 0x00818cUL //Access:RC   DataWidth:0x1    // Multi Field Register.
+  #define MISC_REG_INT_STS_CLR_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define MISC_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                           0
+#define MISC_REG_AEU_GENERAL_ATTN_0                                                                          0x008400UL //Access:RW   DataWidth:0x1    // Set/clr general attention 0; this will set/clr bit 48 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_1                                                                          0x008404UL //Access:RW   DataWidth:0x1    // Set/clr general attention  1; this will set/clr bit 49 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_2                                                                          0x008408UL //Access:RW   DataWidth:0x1    // Set/clr general attention  2; this will set/clr bit 50 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_3                                                                          0x00840cUL //Access:RW   DataWidth:0x1    // Set/clr general attention  3; this will set/clr bit 51 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_4                                                                          0x008410UL //Access:RW   DataWidth:0x1    // Set/clr general attention 4; this will set/clr bit 52 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_5                                                                          0x008414UL //Access:RW   DataWidth:0x1    // Set/clr general attention 5; this will set/clr bit 53 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_6                                                                          0x008418UL //Access:RW   DataWidth:0x1    // Set/clr general attention 6; this will set/clr bit 54 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_7                                                                          0x00841cUL //Access:RW   DataWidth:0x1    // Set/clr general attention 7; this will set/clr bit 55 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_8                                                                          0x008420UL //Access:RW   DataWidth:0x1    // Set/clr general attention 8; this will set/clr bit 56 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_9                                                                          0x008424UL //Access:RW   DataWidth:0x1    // Set/clr general attention 9; this will set/clr bit 57 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_10                                                                         0x008428UL //Access:RW   DataWidth:0x1    // Set/clr general attention 10; this will set/clr bit 58 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_11                                                                         0x00842cUL //Access:RW   DataWidth:0x1    // Set/clr general attention 11; this will set/clr bit 59 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_12                                                                         0x008430UL //Access:RW   DataWidth:0x1    // Set/clr general attention 12; this will set/clr bit 60 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_13                                                                         0x008434UL //Access:RW   DataWidth:0x1    // Set/clr general attention 13; this will set/clr bit 61 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_14                                                                         0x008438UL //Access:RW   DataWidth:0x1    // Set/clr general attention 14; this will set/clr bit 62 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_15                                                                         0x00843cUL //Access:RW   DataWidth:0x1    // Set/clr general attention 15; this will set/clr bit 63 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_16                                                                         0x008440UL //Access:RW   DataWidth:0x1    // Set/clr general attention 16; this will set/clr bit 64 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_17                                                                         0x008444UL //Access:RW   DataWidth:0x1    // Set/clr general attention 17; this will set/clr bit 65 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_18                                                                         0x008448UL //Access:RW   DataWidth:0x1    // Set/clr general attention 18; this will set/clr bit 66 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_19                                                                         0x00844cUL //Access:RW   DataWidth:0x1    // Set/clr general attention 19; this will set/clr bit 67 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_20                                                                         0x008450UL //Access:RW   DataWidth:0x1    // Set/clr general attention 20; this will set/clr bit 68 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_21                                                                         0x008454UL //Access:RW   DataWidth:0x1    // Set/clr general attention 21; this will set/clr bit 69 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_22                                                                         0x008458UL //Access:RW   DataWidth:0x1    // Set/clr general attention 22; this will set/clr bit 70 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_23                                                                         0x00845cUL //Access:RW   DataWidth:0x1    // Set/clr general attention 23; this will set/clr bit 71 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_24                                                                         0x008460UL //Access:RW   DataWidth:0x1    // Set/clr general attention 24; this will set/clr bit 72 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_25                                                                         0x008464UL //Access:RW   DataWidth:0x1    // Set/clr general attention 25; this will set/clr bit 73 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_26                                                                         0x008468UL //Access:RW   DataWidth:0x1    // Set/clr general attention 26; this will set/clr bit 74 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_27                                                                         0x00846cUL //Access:RW   DataWidth:0x1    // Set/clr general attention 27; this will set/clr bit 75 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_28                                                                         0x008470UL //Access:RW   DataWidth:0x1    // Set/clr general attention 28; this will set/clr bit 76 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_29                                                                         0x008474UL //Access:RW   DataWidth:0x1    // Set/clr general attention 29; this will set/clr bit 77 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_30                                                                         0x008478UL //Access:RW   DataWidth:0x1    // Set/clr general attention 30; this will set/clr bit 78 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_31                                                                         0x00847cUL //Access:RW   DataWidth:0x1    // Set/clr general attention 31; this will set/clr bit 79 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_32                                                                         0x008480UL //Access:RW   DataWidth:0x1    // Set/clr general attention 32; this will set/clr bit 80 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_33                                                                         0x008484UL //Access:RW   DataWidth:0x1    // Set/clr general attention 33; this will set/clr bit 81 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_34                                                                         0x008488UL //Access:RW   DataWidth:0x1    // Set/clr general attention 34; this will set/clr bit 82 in AEU vector.
+#define MISC_REG_AEU_GENERAL_ATTN_35                                                                         0x00848cUL //Access:RW   DataWidth:0x1    // Set/clr general attention 35; this will set/clr bit 83 in AEU vector.
+#define MISC_REG_AEU_EVENT_ENABLE                                                                            0x008490UL //Access:RW   DataWidth:0x1    // Event_enable control; when this bit is clear the event enable toward the MCP is masked.
+#define MISC_REG_AEU_MASK_ATTN_IGU                                                                           0x008494UL //Access:RW   DataWidth:0x8    // [7:0] = mask 8 attention output signals toward IGU; 0 = mask; 1 = unmask.
+#define MISC_REG_AEU_MASK_ATTN_MCP                                                                           0x008498UL //Access:RW   DataWidth:0x8    // Masks 8 attention output signals toward MCP. Zero = mask; one = unmask.
+#define MISC_REG_AEU_ENABLE1_IGU_OUT_0                                                                       0x00849cUL //Access:RW   DataWidth:0x20   // First 32b for enabling the output for output0. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_ENABLE2_IGU_OUT_0                                                                       0x0084a0UL //Access:RW   DataWidth:0x20   // Second 32b for enabling the output for output0. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_ENABLE3_IGU_OUT_0                                                                       0x0084a4UL //Access:RW   DataWidth:0x20   // Third 32b for enabling the output for output0. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_ENABLE4_IGU_OUT_0                                                                       0x0084a8UL //Access:RW   DataWidth:0x20   // Fourth 32b for enabling the output for output0. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_ENABLE5_IGU_OUT_0                                                                       0x0084acUL //Access:RW   DataWidth:0x20   // Fifth 32b for enabling the output for output0. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_ENABLE6_IGU_OUT_0                                                                       0x0084b0UL //Access:RW   DataWidth:0x20   // Sixth 32b for enabling the output for output0. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_ENABLE7_IGU_OUT_0                                                                       0x0084b4UL //Access:RW   DataWidth:0x20   // Seventh 32b for enabling the output for output0. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_ENABLE8_IGU_OUT_0                                                                       0x0084b8UL //Access:RW   DataWidth:0x20   // Eighth 32b for enabling the output for output0. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_ENABLE9_IGU_OUT_0                                                                       0x0084bcUL //Access:RW   DataWidth:0x20   // Nineth 32b for enabling the output for output0. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_ENABLE1_IGU_OUT_1                                                                       0x0084c0UL //Access:RW   DataWidth:0x20   // First 32b for enabling the output for output1. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_ENABLE2_IGU_OUT_1                                                                       0x0084c4UL //Access:RW   DataWidth:0x20   // Second 32b for enabling the output for output1. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_ENABLE3_IGU_OUT_1                                                                       0x0084c8UL //Access:RW   DataWidth:0x20   // Third 32b for enabling the output for output1. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_ENABLE4_IGU_OUT_1                                                                       0x0084ccUL //Access:RW   DataWidth:0x20   // Fourth 32b for enabling the output for output1. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_ENABLE5_IGU_OUT_1                                                                       0x0084d0UL //Access:RW   DataWidth:0x20   // Fifth 32b for enabling the output for output1. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_ENABLE6_IGU_OUT_1                                                                       0x0084d4UL //Access:RW   DataWidth:0x20   // Sixth 32b for enabling the output for output1. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_ENABLE7_IGU_OUT_1                                                                       0x0084d8UL //Access:RW   DataWidth:0x20   // Seventh 32b for enabling the output for output1. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_ENABLE8_IGU_OUT_1                                                                       0x0084dcUL //Access:RW   DataWidth:0x20   // Eighth 32b for enabling the output for output1. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_ENABLE9_IGU_OUT_1                                                                       0x0084e0UL //Access:RW   DataWidth:0x20   // Nineth 32b for enabling the output for output1. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_ENABLE1_IGU_OUT_2                                                                       0x0084e4UL //Access:RW   DataWidth:0x20   // First 32b for enabling the output for output2. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_ENABLE2_IGU_OUT_2                                                                       0x0084e8UL //Access:RW   DataWidth:0x20   // Second 32b for enabling the output for output2. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_ENABLE3_IGU_OUT_2                                                                       0x0084ecUL //Access:RW   DataWidth:0x20   // Third 32b for enabling the output for output2. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_ENABLE4_IGU_OUT_2                                                                       0x0084f0UL //Access:RW   DataWidth:0x20   // Fourth 32b for enabling the output for output2. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_ENABLE5_IGU_OUT_2                                                                       0x0084f4UL //Access:RW   DataWidth:0x20   // Fifth 32b for enabling the output for output2. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_ENABLE6_IGU_OUT_2                                                                       0x0084f8UL //Access:RW   DataWidth:0x20   // Sixth 32b for enabling the output for output2. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_ENABLE7_IGU_OUT_2                                                                       0x0084fcUL //Access:RW   DataWidth:0x20   // Seventh 32b for enabling the output for output2. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_ENABLE8_IGU_OUT_2                                                                       0x008500UL //Access:RW   DataWidth:0x20   // Eighth 32b for enabling the output for output2. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_ENABLE9_IGU_OUT_2                                                                       0x008504UL //Access:RW   DataWidth:0x20   // Nineth 32b for enabling the output for output2. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_ENABLE1_IGU_OUT_3                                                                       0x008508UL //Access:RW   DataWidth:0x20   // First 32b for enabling the output for output3. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_ENABLE2_IGU_OUT_3                                                                       0x00850cUL //Access:RW   DataWidth:0x20   // Second 32b for enabling the output for output3. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_ENABLE3_IGU_OUT_3                                                                       0x008510UL //Access:RW   DataWidth:0x20   // Third 32b for enabling the output for output3. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_ENABLE4_IGU_OUT_3                                                                       0x008514UL //Access:RW   DataWidth:0x20   // Fourth 32b for enabling the output for output3. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_ENABLE5_IGU_OUT_3                                                                       0x008518UL //Access:RW   DataWidth:0x20   // Fifth 32b for enabling the output for output3. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_ENABLE6_IGU_OUT_3                                                                       0x00851cUL //Access:RW   DataWidth:0x20   // Sixth 32b for enabling the output for output3. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_ENABLE7_IGU_OUT_3                                                                       0x008520UL //Access:RW   DataWidth:0x20   // Seventh 32b for enabling the output for output3. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_ENABLE8_IGU_OUT_3                                                                       0x008524UL //Access:RW   DataWidth:0x20   // Eighth 32b for enabling the output for output3. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_ENABLE9_IGU_OUT_3                                                                       0x008528UL //Access:RW   DataWidth:0x20   // Nineth 32b for enabling the output for output3. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_ENABLE1_IGU_OUT_4                                                                       0x00852cUL //Access:RW   DataWidth:0x20   // First 32b for enabling the output for output4. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_ENABLE2_IGU_OUT_4                                                                       0x008530UL //Access:RW   DataWidth:0x20   // Second 32b for enabling the output for output4. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_ENABLE3_IGU_OUT_4                                                                       0x008534UL //Access:RW   DataWidth:0x20   // Third 32b for enabling the output for output4. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_ENABLE4_IGU_OUT_4                                                                       0x008538UL //Access:RW   DataWidth:0x20   // Fourth 32b for enabling the output for output4. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_ENABLE5_IGU_OUT_4                                                                       0x00853cUL //Access:RW   DataWidth:0x20   // Fifth 32b for enabling the output for output4. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_ENABLE6_IGU_OUT_4                                                                       0x008540UL //Access:RW   DataWidth:0x20   // Sixth 32b for enabling the output for output4. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_ENABLE7_IGU_OUT_4                                                                       0x008544UL //Access:RW   DataWidth:0x20   // Seventh 32b for enabling the output for output4. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_ENABLE8_IGU_OUT_4                                                                       0x008548UL //Access:RW   DataWidth:0x20   // Eighth 32b for enabling the output for output4. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_ENABLE9_IGU_OUT_4                                                                       0x00854cUL //Access:RW   DataWidth:0x20   // Nineth 32b for enabling the output for output4. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_ENABLE1_IGU_OUT_5                                                                       0x008550UL //Access:RW   DataWidth:0x20   // First 32b for enabling the output for output5. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_ENABLE2_IGU_OUT_5                                                                       0x008554UL //Access:RW   DataWidth:0x20   // Second 32b for enabling the output for output5. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_ENABLE3_IGU_OUT_5                                                                       0x008558UL //Access:RW   DataWidth:0x20   // Third 32b for enabling the output for output5. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_ENABLE4_IGU_OUT_5                                                                       0x00855cUL //Access:RW   DataWidth:0x20   // Fourth 32b for enabling the output for output5. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_ENABLE5_IGU_OUT_5                                                                       0x008560UL //Access:RW   DataWidth:0x20   // Fifth 32b for enabling the output for output5. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_ENABLE6_IGU_OUT_5                                                                       0x008564UL //Access:RW   DataWidth:0x20   // Sixth 32b for enabling the output for output5. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_ENABLE7_IGU_OUT_5                                                                       0x008568UL //Access:RW   DataWidth:0x20   // Seventh 32b for enabling the output for output5. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_ENABLE8_IGU_OUT_5                                                                       0x00856cUL //Access:RW   DataWidth:0x20   // Eighth 32b for enabling the output for output5. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_ENABLE9_IGU_OUT_5                                                                       0x008570UL //Access:RW   DataWidth:0x20   // Nineth 32b for enabling the output for output5. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_ENABLE1_IGU_OUT_6                                                                       0x008574UL //Access:RW   DataWidth:0x20   // First 32b for enabling the output for output6. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_ENABLE2_IGU_OUT_6                                                                       0x008578UL //Access:RW   DataWidth:0x20   // Second 32b for enabling the output for output6. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_ENABLE3_IGU_OUT_6                                                                       0x00857cUL //Access:RW   DataWidth:0x20   // Third 32b for enabling the output for output6. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_ENABLE4_IGU_OUT_6                                                                       0x008580UL //Access:RW   DataWidth:0x20   // Fourth 32b for enabling the output for output6. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_ENABLE5_IGU_OUT_6                                                                       0x008584UL //Access:RW   DataWidth:0x20   // Fifth 32b for enabling the output for output6. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_ENABLE6_IGU_OUT_6                                                                       0x008588UL //Access:RW   DataWidth:0x20   // Sixth 32b for enabling the output for output6. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_ENABLE7_IGU_OUT_6                                                                       0x00858cUL //Access:RW   DataWidth:0x20   // Seventh 32b for enabling the output for output6. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_ENABLE8_IGU_OUT_6                                                                       0x008590UL //Access:RW   DataWidth:0x20   // Eighth 32b for enabling the output for output6. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_ENABLE9_IGU_OUT_6                                                                       0x008594UL //Access:RW   DataWidth:0x20   // Nineth 32b for enabling the output for output6. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_ENABLE1_IGU_OUT_7                                                                       0x008598UL //Access:RW   DataWidth:0x20   // First 32b for enabling the output for output7. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_ENABLE2_IGU_OUT_7                                                                       0x00859cUL //Access:RW   DataWidth:0x20   // Second 32b for enabling the output for output7. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_ENABLE3_IGU_OUT_7                                                                       0x0085a0UL //Access:RW   DataWidth:0x20   // Third 32b for enabling the output for output7. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_ENABLE4_IGU_OUT_7                                                                       0x0085a4UL //Access:RW   DataWidth:0x20   // Fourth 32b for enabling the output for output7. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_ENABLE5_IGU_OUT_7                                                                       0x0085a8UL //Access:RW   DataWidth:0x20   // Fifth 32b for enabling the output for output7. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_ENABLE6_IGU_OUT_7                                                                       0x0085acUL //Access:RW   DataWidth:0x20   // Sixth 32b for enabling the output for output7. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_ENABLE7_IGU_OUT_7                                                                       0x0085b0UL //Access:RW   DataWidth:0x20   // Seventh 32b for enabling the output for output7. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_ENABLE8_IGU_OUT_7                                                                       0x0085b4UL //Access:RW   DataWidth:0x20   // Eighth 32b for enabling the output for output7. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_ENABLE9_IGU_OUT_7                                                                       0x0085b8UL //Access:RW   DataWidth:0x20   // Nineth 32b for enabling the output for output7. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_ENABLE1_NIG                                                                             0x0085bcUL //Access:RW   DataWidth:0x20   // First 32b for enabling the output for close the gate nig. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_ENABLE2_NIG                                                                             0x0085c0UL //Access:RW   DataWidth:0x20   // Second 32b for enabling the output for close the gate nig. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_ENABLE3_NIG                                                                             0x0085c4UL //Access:RW   DataWidth:0x20   // Third 32b for enabling the output for close the gate nig. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_ENABLE4_NIG                                                                             0x0085c8UL //Access:RW   DataWidth:0x20   // Fourth 32b for enabling the output for close the gate nig. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_ENABLE5_NIG                                                                             0x0085ccUL //Access:RW   DataWidth:0x20   // Fifth 32b for enabling the output for close the gate nig. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_ENABLE6_NIG                                                                             0x0085d0UL //Access:RW   DataWidth:0x20   // Sixth 32b for enabling the output for close the gate nig. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_ENABLE7_NIG                                                                             0x0085d4UL //Access:RW   DataWidth:0x20   // Seventh 32b for enabling the output for close the gate nig. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_ENABLE8_NIG                                                                             0x0085d8UL //Access:RW   DataWidth:0x20   // Eighth 32b for enabling the output for close the gate nig. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_ENABLE9_NIG                                                                             0x0085dcUL //Access:RW   DataWidth:0x20   // Nineth 32b for enabling the output for close the gate nig. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_ENABLE1_PXP                                                                             0x0085e0UL //Access:RW   DataWidth:0x20   // First 32b for enabling the output for close the gate pxp. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_ENABLE2_PXP                                                                             0x0085e4UL //Access:RW   DataWidth:0x20   // Second 32b for enabling the output for close the gate pxp. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_ENABLE3_PXP                                                                             0x0085e8UL //Access:RW   DataWidth:0x20   // Third 32b for enabling the output for close the gate pxp. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_ENABLE4_PXP                                                                             0x0085ecUL //Access:RW   DataWidth:0x20   // Fourth 32b for enabling the output for close the gate pxp. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_ENABLE5_PXP                                                                             0x0085f0UL //Access:RW   DataWidth:0x20   // Fifth 32b for enabling the output for close the gate pxp. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_ENABLE6_PXP                                                                             0x0085f4UL //Access:RW   DataWidth:0x20   // Sixth 32b for enabling the output for close the gate pxp. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_ENABLE7_PXP                                                                             0x0085f8UL //Access:RW   DataWidth:0x20   // Seventh 32b for enabling the output for close the gate pxp. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_ENABLE8_PXP                                                                             0x0085fcUL //Access:RW   DataWidth:0x20   // Eighth 32b for enabling the output for close the gate pxp. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_ENABLE9_PXP                                                                             0x008600UL //Access:RW   DataWidth:0x20   // Nineth 32b for enabling the output for close the gate pxp. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_ENABLE1_SYS_KILL                                                                        0x008604UL //Access:RW   DataWidth:0x20   // First 32b for enabling the output for system kill. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_ENABLE2_SYS_KILL                                                                        0x008608UL //Access:RW   DataWidth:0x20   // Second 32b for enabling the output for system kill. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_ENABLE3_SYS_KILL                                                                        0x00860cUL //Access:RW   DataWidth:0x20   // Third 32b for enabling the output for system kill. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_ENABLE4_SYS_KILL                                                                        0x008610UL //Access:RW   DataWidth:0x20   // Fourth 32b for enabling the output for system kill. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_ENABLE5_SYS_KILL                                                                        0x008614UL //Access:RW   DataWidth:0x20   // Fifth 32b for enabling the output for system kill. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_ENABLE6_SYS_KILL                                                                        0x008618UL //Access:RW   DataWidth:0x20   // Sixth 32b for enabling the output for system kill. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_ENABLE7_SYS_KILL                                                                        0x00861cUL //Access:RW   DataWidth:0x20   // Seventh 32b for enabling the output for system kill. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_ENABLE8_SYS_KILL                                                                        0x008620UL //Access:RW   DataWidth:0x20   // Eighth 32b for enabling the output for system kill. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_ENABLE9_SYS_KILL                                                                        0x008624UL //Access:RW   DataWidth:0x20   // Nineth 32b for enabling the output for system kill. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_ENABLE1_MCP_OUT_0                                                                       0x008628UL //Access:RW   DataWidth:0x20   // First 32b for enabling the output for output0. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_ENABLE2_MCP_OUT_0                                                                       0x00862cUL //Access:RW   DataWidth:0x20   // Second 32b for enabling the output for output0. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_ENABLE3_MCP_OUT_0                                                                       0x008630UL //Access:RW   DataWidth:0x20   // Third 32b for enabling the output for output0. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_ENABLE4_MCP_OUT_0                                                                       0x008634UL //Access:RW   DataWidth:0x20   // Fourth 32b for enabling the output for output0. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_ENABLE5_MCP_OUT_0                                                                       0x008638UL //Access:RW   DataWidth:0x20   // Fifth 32b for enabling the output for output0. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_ENABLE6_MCP_OUT_0                                                                       0x00863cUL //Access:RW   DataWidth:0x20   // Sixth 32b for enabling the output for output0. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_ENABLE7_MCP_OUT_0                                                                       0x008640UL //Access:RW   DataWidth:0x20   // Seventh 32b for enabling the output for output0. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_ENABLE8_MCP_OUT_0                                                                       0x008644UL //Access:RW   DataWidth:0x20   // Eighth 32b for enabling the output for output0. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_ENABLE9_MCP_OUT_0                                                                       0x008648UL //Access:RW   DataWidth:0x20   // Nineth 32b for enabling the output for output0. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_ENABLE1_MCP_OUT_1                                                                       0x00864cUL //Access:RW   DataWidth:0x20   // First 32b for enabling the output for output1. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_ENABLE2_MCP_OUT_1                                                                       0x008650UL //Access:RW   DataWidth:0x20   // Second 32b for enabling the output for output1. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_ENABLE3_MCP_OUT_1                                                                       0x008654UL //Access:RW   DataWidth:0x20   // Third 32b for enabling the output for output1. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_ENABLE4_MCP_OUT_1                                                                       0x008658UL //Access:RW   DataWidth:0x20   // Fourth 32b for enabling the output for output1. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_ENABLE5_MCP_OUT_1                                                                       0x00865cUL //Access:RW   DataWidth:0x20   // Fifth 32b for enabling the output for output1. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_ENABLE6_MCP_OUT_1                                                                       0x008660UL //Access:RW   DataWidth:0x20   // Sixth 32b for enabling the output for output1. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_ENABLE7_MCP_OUT_1                                                                       0x008664UL //Access:RW   DataWidth:0x20   // Seventh 32b for enabling the output for output1. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_ENABLE8_MCP_OUT_1                                                                       0x008668UL //Access:RW   DataWidth:0x20   // Eighth 32b for enabling the output for output1. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_ENABLE9_MCP_OUT_1                                                                       0x00866cUL //Access:RW   DataWidth:0x20   // Nineth 32b for enabling the output for output1. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_ENABLE1_MCP_OUT_2                                                                       0x008670UL //Access:RW   DataWidth:0x20   // First 32b for enabling the output for output2. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_ENABLE2_MCP_OUT_2                                                                       0x008674UL //Access:RW   DataWidth:0x20   // Second 32b for enabling the output for output2. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_ENABLE3_MCP_OUT_2                                                                       0x008678UL //Access:RW   DataWidth:0x20   // Third 32b for enabling the output for output2. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_ENABLE4_MCP_OUT_2                                                                       0x00867cUL //Access:RW   DataWidth:0x20   // Fourth 32b for enabling the output for output2. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_ENABLE5_MCP_OUT_2                                                                       0x008680UL //Access:RW   DataWidth:0x20   // Fifth 32b for enabling the output for output2. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_ENABLE6_MCP_OUT_2                                                                       0x008684UL //Access:RW   DataWidth:0x20   // Sixth 32b for enabling the output for output2. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_ENABLE7_MCP_OUT_2                                                                       0x008688UL //Access:RW   DataWidth:0x20   // Seventh 32b for enabling the output for output2. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_ENABLE8_MCP_OUT_2                                                                       0x00868cUL //Access:RW   DataWidth:0x20   // Eighth 32b for enabling the output for output2. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_ENABLE9_MCP_OUT_2                                                                       0x008690UL //Access:RW   DataWidth:0x20   // Nineth 32b for enabling the output for output2. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_ENABLE1_MCP_OUT_3                                                                       0x008694UL //Access:RW   DataWidth:0x20   // First 32b for enabling the output for output3. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_ENABLE2_MCP_OUT_3                                                                       0x008698UL //Access:RW   DataWidth:0x20   // Second 32b for enabling the output for output3. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_ENABLE3_MCP_OUT_3                                                                       0x00869cUL //Access:RW   DataWidth:0x20   // Third 32b for enabling the output for output3. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_ENABLE4_MCP_OUT_3                                                                       0x0086a0UL //Access:RW   DataWidth:0x20   // Fourth 32b for enabling the output for output3. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_ENABLE5_MCP_OUT_3                                                                       0x0086a4UL //Access:RW   DataWidth:0x20   // Fifth 32b for enabling the output for output3. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_ENABLE6_MCP_OUT_3                                                                       0x0086a8UL //Access:RW   DataWidth:0x20   // Sixth 32b for enabling the output for output3. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_ENABLE7_MCP_OUT_3                                                                       0x0086acUL //Access:RW   DataWidth:0x20   // Seventh 32b for enabling the output for output3. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_ENABLE8_MCP_OUT_3                                                                       0x0086b0UL //Access:RW   DataWidth:0x20   // Eighth 32b for enabling the output for output3. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_ENABLE9_MCP_OUT_3                                                                       0x0086b4UL //Access:RW   DataWidth:0x20   // Nineth 32b for enabling the output for output3. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_ENABLE1_MCP_OUT_4                                                                       0x0086b8UL //Access:RW   DataWidth:0x20   // First 32b for enabling the output for output4. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_ENABLE2_MCP_OUT_4                                                                       0x0086bcUL //Access:RW   DataWidth:0x20   // Second 32b for enabling the output for output4. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_ENABLE3_MCP_OUT_4                                                                       0x0086c0UL //Access:RW   DataWidth:0x20   // Third 32b for enabling the output for output4. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_ENABLE4_MCP_OUT_4                                                                       0x0086c4UL //Access:RW   DataWidth:0x20   // Fourth 32b for enabling the output for output4. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_ENABLE5_MCP_OUT_4                                                                       0x0086c8UL //Access:RW   DataWidth:0x20   // Fifth 32b for enabling the output for output4. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_ENABLE6_MCP_OUT_4                                                                       0x0086ccUL //Access:RW   DataWidth:0x20   // Sixth 32b for enabling the output for output4. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_ENABLE7_MCP_OUT_4                                                                       0x0086d0UL //Access:RW   DataWidth:0x20   // Seventh 32b for enabling the output for output4. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_ENABLE8_MCP_OUT_4                                                                       0x0086d4UL //Access:RW   DataWidth:0x20   // Eighth 32b for enabling the output for output4. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_ENABLE9_MCP_OUT_4                                                                       0x0086d8UL //Access:RW   DataWidth:0x20   // Nineth 32b for enabling the output for output4. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_ENABLE1_MCP_OUT_5                                                                       0x0086dcUL //Access:RW   DataWidth:0x20   // First 32b for enabling the output for output5. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_ENABLE2_MCP_OUT_5                                                                       0x0086e0UL //Access:RW   DataWidth:0x20   // Second 32b for enabling the output for output5. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_ENABLE3_MCP_OUT_5                                                                       0x0086e4UL //Access:RW   DataWidth:0x20   // Third 32b for enabling the output for output5. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_ENABLE4_MCP_OUT_5                                                                       0x0086e8UL //Access:RW   DataWidth:0x20   // Fourth 32b for enabling the output for output5. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_ENABLE5_MCP_OUT_5                                                                       0x0086ecUL //Access:RW   DataWidth:0x20   // Fifth 32b for enabling the output for output5. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_ENABLE6_MCP_OUT_5                                                                       0x0086f0UL //Access:RW   DataWidth:0x20   // Sixth 32b for enabling the output for output5. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_ENABLE7_MCP_OUT_5                                                                       0x0086f4UL //Access:RW   DataWidth:0x20   // Seventh 32b for enabling the output for output5. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_ENABLE8_MCP_OUT_5                                                                       0x0086f8UL //Access:RW   DataWidth:0x20   // Eighth 32b for enabling the output for output5. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_ENABLE9_MCP_OUT_5                                                                       0x0086fcUL //Access:RW   DataWidth:0x20   // Nineth 32b for enabling the output for output5. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_ENABLE1_MCP_OUT_6                                                                       0x008700UL //Access:RW   DataWidth:0x20   // First 32b for enabling the output for output6. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_ENABLE2_MCP_OUT_6                                                                       0x008704UL //Access:RW   DataWidth:0x20   // Second 32b for enabling the output for output6. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_ENABLE3_MCP_OUT_6                                                                       0x008708UL //Access:RW   DataWidth:0x20   // Third 32b for enabling the output for output6. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_ENABLE4_MCP_OUT_6                                                                       0x00870cUL //Access:RW   DataWidth:0x20   // Fourth 32b for enabling the output for output6. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_ENABLE5_MCP_OUT_6                                                                       0x008710UL //Access:RW   DataWidth:0x20   // Fifth 32b for enabling the output for output6. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_ENABLE6_MCP_OUT_6                                                                       0x008714UL //Access:RW   DataWidth:0x20   // Sixth 32b for enabling the output for output6. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_ENABLE7_MCP_OUT_6                                                                       0x008718UL //Access:RW   DataWidth:0x20   // Seventh 32b for enabling the output for output6. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_ENABLE8_MCP_OUT_6                                                                       0x00871cUL //Access:RW   DataWidth:0x20   // Eighth 32b for enabling the output for output6. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_ENABLE9_MCP_OUT_6                                                                       0x008720UL //Access:RW   DataWidth:0x20   // Nineth 32b for enabling the output for output6. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_ENABLE1_MCP_OUT_7                                                                       0x008724UL //Access:RW   DataWidth:0x20   // First 32b for enabling the output for output7. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_ENABLE2_MCP_OUT_7                                                                       0x008728UL //Access:RW   DataWidth:0x20   // Second 32b for enabling the output for output7. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_ENABLE3_MCP_OUT_7                                                                       0x00872cUL //Access:RW   DataWidth:0x20   // Third 32b for enabling the output for output7. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_ENABLE4_MCP_OUT_7                                                                       0x008730UL //Access:RW   DataWidth:0x20   // Fourth 32b for enabling the output for output7. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_ENABLE5_MCP_OUT_7                                                                       0x008734UL //Access:RW   DataWidth:0x20   // Fifth 32b for enabling the output for output7. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_ENABLE6_MCP_OUT_7                                                                       0x008738UL //Access:RW   DataWidth:0x20   // Sixth 32b for enabling the output for output7. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_ENABLE7_MCP_OUT_7                                                                       0x00873cUL //Access:RW   DataWidth:0x20   // Seventh 32b for enabling the output for output7. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_ENABLE8_MCP_OUT_7                                                                       0x008740UL //Access:RW   DataWidth:0x20   // Eighth 32b for enabling the output for output7. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_ENABLE9_MCP_OUT_7                                                                       0x008744UL //Access:RW   DataWidth:0x20   // Nineth 32b for enabling the output for output7. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR                                                                     0x008748UL //Access:RW   DataWidth:0x20   // First 32b for enabling the output for global uncorrectable eror. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_ENABLE2_GLB_UNC_ERR                                                                     0x00874cUL //Access:RW   DataWidth:0x20   // Second 32b for enabling the output for global uncorrectable eror. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_ENABLE3_GLB_UNC_ERR                                                                     0x008750UL //Access:RW   DataWidth:0x20   // Third 32b for enabling the output for global uncorrectable eror. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_ENABLE4_GLB_UNC_ERR                                                                     0x008754UL //Access:RW   DataWidth:0x20   // Fourth 32b for enabling the output for global uncorrectable eror. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_ENABLE5_GLB_UNC_ERR                                                                     0x008758UL //Access:RW   DataWidth:0x20   // Fifth 32b for enabling the output for global uncorrectable eror. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_ENABLE6_GLB_UNC_ERR                                                                     0x00875cUL //Access:RW   DataWidth:0x20   // Sixth 32b for enabling the output for global uncorrectable eror. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_ENABLE7_GLB_UNC_ERR                                                                     0x008760UL //Access:RW   DataWidth:0x20   // Seventh 32b for enabling the output for global uncorrectable eror. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_ENABLE8_GLB_UNC_ERR                                                                     0x008764UL //Access:RW   DataWidth:0x20   // Eighth 32b for enabling the output for global uncorrectable eror. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_ENABLE9_GLB_UNC_ERR                                                                     0x008768UL //Access:RW   DataWidth:0x20   // Nineth 32b for enabling the output for global uncorrectable eror. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_INVERTER_1_IGU                                                                          0x00876cUL //Access:RW   DataWidth:0x20   // First 32b for inverting the input. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_INVERTER_2_IGU                                                                          0x008770UL //Access:RW   DataWidth:0x20   // Second 32b for inverting the input. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_INVERTER_3_IGU                                                                          0x008774UL //Access:RW   DataWidth:0x20   // Third 32b for inverting the input. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_INVERTER_4_IGU                                                                          0x008778UL //Access:RW   DataWidth:0x20   // Fourth 32b for inverting the input. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_INVERTER_5_IGU                                                                          0x00877cUL //Access:RW   DataWidth:0x20   // Fifth 32b for inverting the input. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_INVERTER_6_IGU                                                                          0x008780UL //Access:RW   DataWidth:0x20   // Sixth 32b for inverting the input. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_INVERTER_7_IGU                                                                          0x008784UL //Access:RW   DataWidth:0x20   // Seventh 32b for inverting the input. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_INVERTER_8_IGU                                                                          0x008788UL //Access:RW   DataWidth:0x20   // Eighth 32b for inverting the input. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_INVERTER_9_IGU                                                                          0x00878cUL //Access:RW   DataWidth:0x20   // Nineth 32b for inverting the input. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_INVERTER_1_MCP                                                                          0x008790UL //Access:RW   DataWidth:0x20   // First 32b for inverting the input. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_INVERTER_2_MCP                                                                          0x008794UL //Access:RW   DataWidth:0x20   // Second 32b for inverting the input. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_INVERTER_3_MCP                                                                          0x008798UL //Access:RW   DataWidth:0x20   // Third 32b for inverting the input. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_INVERTER_4_MCP                                                                          0x00879cUL //Access:RW   DataWidth:0x20   // Fourth 32b for inverting the input. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_INVERTER_5_MCP                                                                          0x0087a0UL //Access:RW   DataWidth:0x20   // Fifth 32b for inverting the input. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_INVERTER_6_MCP                                                                          0x0087a4UL //Access:RW   DataWidth:0x20   // Sixth 32b for inverting the input. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_INVERTER_7_MCP                                                                          0x0087a8UL //Access:RW   DataWidth:0x20   // Seventh 32b for inverting the input. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_INVERTER_8_MCP                                                                          0x0087acUL //Access:RW   DataWidth:0x20   // Eighth 32b for inverting the input. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_INVERTER_9_MCP                                                                          0x0087b0UL //Access:RW   DataWidth:0x20   // Nineth 32b for inverting the input. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_AFTER_INVERT_1_IGU                                                                      0x0087b4UL //Access:R    DataWidth:0x20   // First 32b read after invert of input. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_AFTER_INVERT_2_IGU                                                                      0x0087b8UL //Access:R    DataWidth:0x20   // Second 32b read after invert of input. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_AFTER_INVERT_3_IGU                                                                      0x0087bcUL //Access:R    DataWidth:0x20   // Third 32b read after invert of input. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_AFTER_INVERT_4_IGU                                                                      0x0087c0UL //Access:R    DataWidth:0x20   // Fourth 32b read after invert of input. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_AFTER_INVERT_5_IGU                                                                      0x0087c4UL //Access:R    DataWidth:0x20   // Fifth 32b read after invert of input. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_AFTER_INVERT_6_IGU                                                                      0x0087c8UL //Access:R    DataWidth:0x20   // Sixth 32b read after invert of input. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_AFTER_INVERT_7_IGU                                                                      0x0087ccUL //Access:R    DataWidth:0x20   // Seventh 32b read after invert of input. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_AFTER_INVERT_8_IGU                                                                      0x0087d0UL //Access:R    DataWidth:0x20   // Eighth 32b read after invert of input. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_AFTER_INVERT_9_IGU                                                                      0x0087d4UL //Access:R    DataWidth:0x20   // Nineth 32b read after invert of input. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_AFTER_INVERT_1_MCP                                                                      0x0087d8UL //Access:R    DataWidth:0x20   // First 32b read after invert of input. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_AFTER_INVERT_2_MCP                                                                      0x0087dcUL //Access:R    DataWidth:0x20   // Second 32b read after invert of input. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_AFTER_INVERT_3_MCP                                                                      0x0087e0UL //Access:R    DataWidth:0x20   // Third 32b read after invert of input. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_AFTER_INVERT_4_MCP                                                                      0x0087e4UL //Access:R    DataWidth:0x20   // Fourth 32b read after invert of input. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_AFTER_INVERT_5_MCP                                                                      0x0087e8UL //Access:R    DataWidth:0x20   // Fifth 32b read after invert of input. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_AFTER_INVERT_6_MCP                                                                      0x0087ecUL //Access:R    DataWidth:0x20   // Sixth 32b read after invert of input. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_AFTER_INVERT_7_MCP                                                                      0x0087f0UL //Access:R    DataWidth:0x20   // Seventh 32b read after invert of input. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_AFTER_INVERT_8_MCP                                                                      0x0087f4UL //Access:R    DataWidth:0x20   // Eighth 32b read after invert of input. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_AFTER_INVERT_9_MCP                                                                      0x0087f8UL //Access:R    DataWidth:0x20   // Nineth 32b read after invert of input. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_SYS_KILL_OCCURRED                                                                       0x0087fcUL //Access:RW   DataWidth:0x1    // If set a system kill occurred. Reset on POR reset.
+#define MISC_REG_AEU_SYS_KILL_BEHAVIOR                                                                       0x008800UL //Access:RW   DataWidth:0x1    // The System Kill enable: 0 - none; 1 - hard reset. Reset on POR reset.
+#define MISC_REG_AEU_SYS_KILL_STATUS_0                                                                       0x008804UL //Access:RW   DataWidth:0x20   // First 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
+#define MISC_REG_AEU_SYS_KILL_STATUS_1                                                                       0x008808UL //Access:RW   DataWidth:0x20   // Second 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
+#define MISC_REG_AEU_SYS_KILL_STATUS_2                                                                       0x00880cUL //Access:RW   DataWidth:0x20   // Third 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
+#define MISC_REG_AEU_SYS_KILL_STATUS_3                                                                       0x008810UL //Access:RW   DataWidth:0x20   // Fourth 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
+#define MISC_REG_AEU_SYS_KILL_STATUS_4                                                                       0x008814UL //Access:RW   DataWidth:0x20   // Fifth 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;
+#define MISC_REG_AEU_SYS_KILL_STATUS_5                                                                       0x008818UL //Access:RW   DataWidth:0x20   // Sixth 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;
+#define MISC_REG_AEU_SYS_KILL_STATUS_6                                                                       0x00881cUL //Access:RW   DataWidth:0x20   // Seventh 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;
+#define MISC_REG_AEU_SYS_KILL_STATUS_7                                                                       0x008820UL //Access:RW   DataWidth:0x20   // Eighth 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;
+#define MISC_REG_AEU_SYS_KILL_STATUS_8                                                                       0x008824UL //Access:RW   DataWidth:0x20   // Nineth 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [31:15] reserved;
+#define MISC_REG_AEU_GENERAL_MASK                                                                            0x008828UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define MISC_REG_AEU_GENERAL_MASK_AEU_PXP_CLOSE_MASK                                                       (0x1<<0) // Pxp close the gate mask bit; 0 = masked; 1 = unmasked.
+  #define MISC_REG_AEU_GENERAL_MASK_AEU_PXP_CLOSE_MASK_SHIFT                                                 0
+  #define MISC_REG_AEU_GENERAL_MASK_AEU_NIG_CLOSE_MASK                                                       (0x1<<1) // Nig close the gate mask bit; 0 = masked; 1 = unmasked.
+  #define MISC_REG_AEU_GENERAL_MASK_AEU_NIG_CLOSE_MASK_SHIFT                                                 1
+  #define MISC_REG_AEU_GENERAL_MASK_AEU_SYS_KILL_MASK                                                        (0x1<<2) // System kill mask bit; 0 = masked; 1 = unmasked.
+  #define MISC_REG_AEU_GENERAL_MASK_AEU_SYS_KILL_MASK_SHIFT                                                  2
+  #define MISC_REG_AEU_GENERAL_MASK_AEU_GLB_UNC_ERR_MASK                                                     (0x1<<3) // Global uncorrectable error mask bit; 0 = masked; 1 = unmasked.
+  #define MISC_REG_AEU_GENERAL_MASK_AEU_GLB_UNC_ERR_MASK_SHIFT                                               3
+#define MISC_REG_AEU_CLR_LATCH_SIGNAL                                                                        0x00882cUL //Access:W    DataWidth:0xa    // Write to this register results with the clear of the latched signals; [0] one clears Latched MCP memory parity; [1] one clears Latched MCP Scratchpad Cache attention; [3:2] reserved; [4] one clears pglue_misc_mps_attn; [5] one clears pxp_misc_exp_rom_attn; [6] one clears PERST_N assertion (goes 0); [7] one clears PERST_N de-assertion (goes 1). [8] one clears PCIe link up. [9] one clears PCIe hot reset.
+#define MISC_REG_AEU_MASK_ATTN_IGU_MSB                                                                       0x008830UL //Access:RW   DataWidth:0xa    // Mask 10 MSB attention output signals toward IGU; Zero = mask; one = unmask.
+#define MISC_REG_AEU_CLR_VPD_LATCH_SIGNAL                                                                    0x008834UL //Access:W    DataWidth:0x10   // Write to this register results with the clear of the latched signals; [0] - clears pglue_misc_vpd_attn[0], [1] - clears pglue_misc_vpd_attn[1], so forth;  read from this register returns 0.
+#define MISC_REG_AEU_VPD_LATCH_STATUS                                                                        0x008838UL //Access:R    DataWidth:0x10   // Represent the status of pglue_misc_vpd_attn after latching.
+#define MISC_REG_ATTN_NUM_ST                                                                                 0x00883cUL //Access:RW   DataWidth:0x9    // Attention sticky number - latches first attention number within attentions vector. The number is produced as the index of aeu_after_invert_* multiplied by 32 plus index of the attention bit. Should be written to 0x1ff to release latch.
+#define MISC_REG_PORT_MODE                                                                                   0x008c00UL //Access:RW   DataWidth:0x2    // Port mode. 0 - single port; 1 - 2 ports; 2 - 4 ports. 2 is prohibited configuration in 2 path device. Reset on POR reset.
+#define MISC_REG_XMAC_PHY_PORT_MODE_BB                                                                       0x008c04UL //Access:RW   DataWidth:0x2    // XMAC PHY port mode. Indicates the number of ports on the Warp Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the XMAC_MP core; and should be changed only while reset is held low. Reset on Hard reset. Not used.
+#define MISC_REG_XMAC_CORE_PORT_MODE_BB                                                                      0x008c08UL //Access:RW   DataWidth:0x2    // XMAC Core port mode. Indicates the number of ports on the system side. This should be less than or equal to phy_port_mode; if some of the ports are not used. This enables reduction of frequency on the core side. This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 - Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap input for the XMAC_MP core; and should be changed only while reset is held low. Reset on Hard reset. Not used.
+#define MISC_REG_OPTE_MODE                                                                                   0x008c0cUL //Access:RW   DataWidth:0x1    // 0 - disabled, 1 - enabled. When OPTE mode is enabled, it connects two engines to one MAC port.  Port 0 of each engine is used in this configuration, with support for 8 TCs, 1 pure-LB TC, and 8 global PFs.
+#define MISC_REG_CLK_100G_MODE                                                                               0x008c10UL //Access:RW   DataWidth:0x3    // Per bit; 1:  clk_nw and main clk are asynchronous and sync FIFOs should be used. (clk_nw = 425 MHz); 0:  clk_nw and main clk are synchronous and sync FIFOs should be bypassed in latency-critical paths. bit0 - clock mux control (Obsolete), bit1 - BRB/BTB control, bit2 - NIG control. Reset on Hard reset.
+#define MISC_REG_BLOCK_256B_EN                                                                               0x008c14UL //Access:RW   DataWidth:0x2    // This register indicates if BRTB block size is 256 byte (when programmed to 1) or 128 byte (when programmed to 0). In E4 (BigBear) it should be set to 1 in 100G and 50G modes. Reset on Hard reset. [0]- BRB; [1] - BTB, PBF;
+#define MISC_REG_PERST_STATUS                                                                                0x008c18UL //Access:R    DataWidth:0x1    // PERST_B status.
+#define MISC_REG_SEM_STALL                                                                                   0x008c1cUL //Access:RW   DataWidth:0x3    // 0 - Storms stall is disallowed; AEU unifier bit[7] output to MCP is disabled; 1 - All Storms are forced to be stopped; AEU unifier bit[7] output to MCP is disabled; 2 - All Storms will be stopped in case AEU unifier bit[7] is set; AEU unifier bit[7] output to MCP is disabled; 4 - Storms stall is disallowed; AEU unifier bit[7] output to MCP is allowed; 5 - All Storms are forced to be stopped; AEU unifier bit[7] output to MCP is allowed; 6 - All Storms will be stopped in case AEU unifier bit[7] is set; AEU unifier bit[7] output to MCP is allowed; 3, 7 are not defined;
+#define MISC_REG_SHARED_MEM_ADDR                                                                             0x008c20UL //Access:RW   DataWidth:0x17   // 23 bit GRC address where the scratch-pad of the MCP that is shared with the driver resides.
+#define MISC_REG_SW_TIMER_CFG_1                                                                              0x008c24UL //Access:RW   DataWidth:0x6    // SW timer 1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 1 reach zero the register will be reload with MISC_REGISTERS_SW_TIMER_RELOAD_VAL_1.SW_TIMER_RELOAD_VAL_1 )  ; bit2=attn (0-no attention; 1-attention signal will be send to the AEU when the MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 1 reach zero); bit4-5=resolution (00-10us; 01-100us; 10-1ms; 11- 1us).
+#define MISC_REG_SW_TIMER_CFG_2                                                                              0x008c28UL //Access:RW   DataWidth:0x6    // SW timer 1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 2 reach zero the register will be reload with MISC_REGISTERS_SW_TIMER_RELOAD_VAL_2.SW_TIMER_RELOAD_VAL_2 )  ; bit2=attn (0-no attention; 1-attention signal will be send to the AEU when the MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 2 reach zero); bit4-5=resolution (00-10us; 01-100us; 10-1ms; 11- 1us).
+#define MISC_REG_SW_TIMER_CFG_3                                                                              0x008c2cUL //Access:RW   DataWidth:0x6    // SW timer 1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 3 reach zero the register will be reload with MISC_REGISTERS_SW_TIMER_RELOAD_VAL_3.SW_TIMER_RELOAD_VAL_3 )  ; bit2=attn (0-no attention; 1-attention signal will be send to the AEU when the MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 3 reach zero); bit4-5=resolution (00-10us; 01-100us; 10-1ms; 11- 1us).
+#define MISC_REG_SW_TIMER_CFG_4                                                                              0x008c30UL //Access:RW   DataWidth:0x6    // SW timer 1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 4 reach zero the register will be reload with MISC_REGISTERS_SW_TIMER_RELOAD_VAL_4.SW_TIMER_RELOAD_VAL_4 )  ; bit2=attn (0-no attention; 1-attention signal will be send to the AEU when the MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 4 reach zero); bit4-5=resolution (00-10us; 01-100us; 10-1ms; 11- 1us).
+#define MISC_REG_SW_TIMER_CFG_5                                                                              0x008c34UL //Access:RW   DataWidth:0x6    // SW timer 1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 5 reach zero the register will be reload with MISC_REGISTERS_SW_TIMER_RELOAD_VAL_5.SW_TIMER_RELOAD_VAL_5 )  ; bit2=attn (0-no attention; 1-attention signal will be send to the AEU when the MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 5 reach zero); bit4-5=resolution (00-10us; 01-100us; 10-1ms; 11- 1us).
+#define MISC_REG_SW_TIMER_CFG_6                                                                              0x008c38UL //Access:RW   DataWidth:0x6    // SW timer 1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 6 reach zero the register will be reload with MISC_REGISTERS_SW_TIMER_RELOAD_VAL_6.SW_TIMER_RELOAD_VAL_6 )  ; bit2=attn (0-no attention; 1-attention signal will be send to the AEU when the MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 6 reach zero); bit4-5=resolution (00-10us; 01-100us; 10-1ms; 11- 1us).
+#define MISC_REG_SW_TIMER_CFG_7                                                                              0x008c3cUL //Access:RW   DataWidth:0x6    // SW timer 1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 7 reach zero the register will be reload with MISC_REGISTERS_SW_TIMER_RELOAD_VAL_7.SW_TIMER_RELOAD_VAL_7 )  ; bit2=attn (0-no attention; 1-attention signal will be send to the AEU when the MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 7 reach zero); bit4-5=resolution (00-10us; 01-100us; 10-1ms; 11- 1us).
+#define MISC_REG_SW_TIMER_CFG_8                                                                              0x008c40UL //Access:RW   DataWidth:0x6    // SW timer 1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 8 reach zero the register will be reload with MISC_REGISTERS_SW_TIMER_RELOAD_VAL_8.SW_TIMER_RELOAD_VAL_8 )  ; bit2=attn (0-no attention; 1-attention signal will be send to the AEU when the MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 8 reach zero); bit4-5=resolution (00-10us; 01-100us; 10-1ms; 11- 1us).
+#define MISC_REG_SW_TIMER_RELOAD_VAL_1                                                                       0x008c44UL //Access:RW   DataWidth:0x20   // Reload value for counter 1 if reload; the value will be reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_1.SW_TIMER_CFG_1 [1] ) is set.
+#define MISC_REG_SW_TIMER_RELOAD_VAL_2                                                                       0x008c48UL //Access:RW   DataWidth:0x20   // Reload value for counter 2 if reload; the value will be reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_2.SW_TIMER_CFG_2 [1]  ) is set.
+#define MISC_REG_SW_TIMER_RELOAD_VAL_3                                                                       0x008c4cUL //Access:RW   DataWidth:0x20   // Reload value for counter 3 if reload; the value will be reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_3.SW_TIMER_CFG_3 [1]  ) is set.
+#define MISC_REG_SW_TIMER_RELOAD_VAL_4                                                                       0x008c50UL //Access:RW   DataWidth:0x20   // Reload value for counter 4 if reload; the value will be reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_4.SW_TIMER_CFG_4 [1]  ) is set.
+#define MISC_REG_SW_TIMER_RELOAD_VAL_5                                                                       0x008c54UL //Access:RW   DataWidth:0x20   // Reload value for counter 5 if reload; the value will be reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_1.SW_TIMER_CFG_5 [1]  ) is set.
+#define MISC_REG_SW_TIMER_RELOAD_VAL_6                                                                       0x008c58UL //Access:RW   DataWidth:0x20   // Reload value for counter 6 if reload; the value will be reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_1.SW_TIMER_CFG_6 [1]  ) is set.
+#define MISC_REG_SW_TIMER_RELOAD_VAL_7                                                                       0x008c5cUL //Access:RW   DataWidth:0x20   // Reload value for counter 1 if reload; the value will be reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_1.SW_TIMER_CFG_7 [1] ) is set.
+#define MISC_REG_SW_TIMER_RELOAD_VAL_8                                                                       0x008c60UL //Access:RW   DataWidth:0x20   // Reload value for counter 8 if reload; the value will be reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_1.SW_TIMER_CFG_8 [1] ) is set.
+#define MISC_REG_SW_TIMER_EVENT_CLR                                                                          0x008c64UL //Access:W    DataWidth:0x8    // Write one for the appropriate bit will clear the appropriate event to the AEU (if the attn bit (bit 2) in the MISC_REGISTERS_SW_TIMER_CFG_1.SW_TIMER_CFG_1 [2]; MISC_REGISTERS_SW_TIMER_CFG_2.SW_TIMER_CFG_2 [2]; MISC_REGISTERS_SW_TIMER_CFG_3.SW_TIMER_CFG_3 [2]; MISC_REGISTERS_SW_TIMER_CFG_4.SW_TIMER_CFG_4 [2]; MISC_REGISTERS_SW_TIMER_CFG_5.SW_TIMER_CFG_5 [2]; MISC_REGISTERS_SW_TIMER_CFG_6.SW_TIMER_CFG_6 [2]; MISC_REGISTERS_SW_TIMER_CFG_7.SW_TIMER_CFG_7 [2]; MISC_REGISTERS_SW_TIMER_CFG_8.SW_TIMER_CFG_8 [2] is set). [0] timer1; [1] timer2; [2] timer3; [3] timer4; [4] timer5; [5] timer6; [6] timer7; [7] timer8.
+#define MISC_REG_SW_TIMER_EVENT                                                                              0x008c68UL //Access:R    DataWidth:0x8    // The appropriate timer had reach to zero. [0] timer1; [1]timer2; [2] timer3; [3] timer4; [4] timer5; [5] timer6; [6] timer7; [7] timer8.
+#define MISC_REG_SW_TIMER_10US_RESOLUTION                                                                    0x008c6cUL //Access:RW   DataWidth:0xa    // Fine tuning for sw 10us timer; max value=300; min value=200. the 10us timer is the base counter for all the timers.
+#define MISC_REG_GEN_PURP_HW0                                                                                0x008c70UL //Access:RW   DataWidth:0x20   // Debug only: spare RW register reset by hard reset.
+#define MISC_REG_GEN_PURP_HW1                                                                                0x008c74UL //Access:RW   DataWidth:0x20   // Debug only: spare RW register reset by hard reset.
+#define MISC_REG_GEN_PURP_HW2                                                                                0x008c78UL //Access:RW   DataWidth:0x20   // Debug only: spare RW register reset by hard reset.
+#define MISC_REG_GEN_PURP_HW3                                                                                0x008c7cUL //Access:RW   DataWidth:0x20   // Debug only: spare RW register reset by hard reset.
+#define MISC_REG_GEN_PURP_CR0                                                                                0x008c80UL //Access:RW   DataWidth:0x20   // Debug only: spare RW register reset by core reset.
+#define MISC_REG_GEN_PURP_CR1                                                                                0x008c84UL //Access:RW   DataWidth:0x20   // Debug only: spare RW register reset by core reset.
+#define MISC_REG_GEN_PURP_CR2                                                                                0x008c88UL //Access:RW   DataWidth:0x20   // Debug only: spare RW register reset by core reset.
+#define MISC_REG_GEN_PURP_CR3                                                                                0x008c8cUL //Access:RW   DataWidth:0x20   // Debug only: spare RW register reset by core reset.
+#define MISC_REG_GEN_PURP_POR0                                                                               0x008c90UL //Access:RW   DataWidth:0x20   // Debug only: spare RW register reset by por reset.
+#define MISC_REG_GEN_PURP_POR1                                                                               0x008c94UL //Access:RW   DataWidth:0x20   // Debug only: spare RW register reset by por reset.
+#define MISC_REG_GEN_PURP_POR2                                                                               0x008c98UL //Access:RW   DataWidth:0x20   // Debug only: spare RW register reset by por reset.
+#define MISC_REG_GEN_PURP_POR3                                                                               0x008c9cUL //Access:RW   DataWidth:0x20   // Debug only: spare RW register reset by por reset.
+#define MISC_REG_ECO_RESERVED                                                                                0x008ca0UL //Access:RW   DataWidth:0x20   // Eco reserved. Global register.
+#define MISC_REG_SW_TIMER_VAL                                                                                0x008d00UL //Access:RW   DataWidth:0x20   // The value of the counter for sw timers1-8. there are 8 addresses in this register. address 0 - timer 1; address 1 - timer 2; etc ; address 7 - timer 8.
+#define MISC_REG_SW_TIMER_VAL_SIZE                                                                           8
+#define MISCS_REG_RESET_CONFIG                                                                               0x009040UL //Access:RW   DataWidth:0x20   // Reset configuration register. inside order of the bits is: [0] rst_ncsi_on_core_rst (0- no auto deassertion; 1 - auto deassertion); [1] rst_umac_on_core_rst (0- no auto deassertion; 1 - auto deassertion); [2] rst_mstat_on_core_rst (0- no auto deassertion; 1 - auto deassertion); [3] rst_cpmu_auto_mode (0- no auto deassertion; 1 - auto deassertion); [4] rst_pxpv_auto_mode (0- no auto deassertion; 1 - auto deassertion); [5] rst_nwm_mac_core_assert_on_core_rst (0 - no; 1 - yes); [6] reserved; [7] rst_mcp_n_reset_reg_hard_core_auto_mode (0- no auto deassertion; 1 - auto deassertion); [8] rst_mcp_n_hard_core_rst_b_auto_mode (0- no auto deassertion; 1 - auto deassertion); [9] rst_mcp_n_reset_cmn_cpu_auto_mode (0- no auto deassertion; 1 - auto deassertion); [10] rst_mcp_n_reset_cmn_core_auto_mode (0- no auto deassertion; 1 - auto deassertion); [11-13] reserved; [14] rst_misc_core_auto_mode (0- no auto deassertion; 1 - auto deassertion); [15] rst_dbue_auto_mode (0- no auto deassertion; 1 - auto deassertion); [16] grc_reset_assert_on_core_rst (0 - no; 1 - yes); [17] rst_mcp_n_reset_cmn_cpu_assert_on_core_rst (0 - no; 1 - yes); [18] rst_mcp_n_reset_cmn_core_assert_on_core_rst (0 - no; 1 - yes); [19] rst_rbc{n|h}_assert_on_core_rst (0 - no; 1 - yes); [20] rst_nwm_core_assert_on_core_rst (0 - no; 1 - yes); [21] rst_misc_core_assert_on_core_rst (0 - no; 1 - yes); [22] rst_dbue_assert_on_core_rst (0 - no; 1 - yes); [23] wrappers_iddq_and_rst_signals_assert_on_core_rst (0 - no; 1 - yes); [24] rst_rbcw_core_assert_on_core_rst (0 - no; 1 - yes); [25] rst_pglc_auto_mode (0- no auto deassertion; 1 - auto deassertion); [26] rst_bmb_on_core_rst (0- no reset on core reset; 1 - reset on core reset); [27] rst_opte_on_core_rst (0- no reset on core reset; 1 - reset on core reset); [28] rst_opcs_core_assert_on_core_rst (0 - no; 1 - yes); [29] rst_nws_core_assert_on_core_rst (0 - no; 1 - yes); [30] rst_ms_core_assert_on_core_rst (0 - no; 1 - yes); [31] rst_led_core_assert_on_core_rst (0 - no; 1 - yes) Reset on hard reset.
+#define MISCS_REG_RESET_CONFIG_POR                                                                           0x009044UL //Access:RW   DataWidth:0x4    // Reset configuration register. inside order of the bits is: [0] rst_n_reg_hard_misc_rbc_pcie (0 - is not reset on hard reset; 1 - is reset on hard reset); [1] rst_n_hard_misc_rbc_pcie (0 - is not reset on hard reset; 1 - is reset on hard reset); [2] rst_n_hard_misc_erstclk_pcie (0 - is not reset on hard reset; 1 - is reset on hard reset); [3] reserved; Reset on POR reset.
+#define MISCS_REG_RESET_PL_UA                                                                                0x009050UL //Access:RW   DataWidth:0x20   // Reset_reg: Shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0"  resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_cgrc; [1] rst_mcp_n_reset_reg_hard_core; [2] rst_mcp_n_hard_core_rst_b; [3] rst_mcp_n_reset_cmn_cpu; [4] rst_mcp_n_reset_cmn_core; [5] rst_misc_core; [6] rst_dbue (UART); [7] rst_bmb; [8] rst_ipc; [9]rst_crbcn; [10] reserved; [11] rst_avs; [31-10] reserved; Global register.
+#define MISCS_REG_RESET_PL_UA_SIZE                                                                           3
+#define MISCS_REG_RESET_PL_HV                                                                                0x009060UL //Access:RW   DataWidth:0x20   // Reset_reg: Shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0"  resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_cnig; [1] rst_pglc; [2] rst_pxpv; [3] rst_crbch; [4] rst_opte; [5] rst_ncsi; [6] rst_umac; [7] rst_mstat; [8] rst_cpmu; [9] reserved; [10] rst_rbcw; [11] rst_opcs; [12] rst_nws; [13] rst_ms;  [14] rst_led; [31:15] reserved; Global register.
+#define MISCS_REG_RESET_PL_HV_SIZE                                                                           3
+#define MISCS_REG_CLK_100G_MODE                                                                              0x009070UL //Access:RW   DataWidth:0x1    // This register indicates if clk_nw frequency is faster than main clock frequency (when programmed to 1) or is the same as main clock frequency (when programmed to 0). In E4 (BigBear) it should be set to 1 in 100G mode. In AH it control SYNC FIFOs in the BMB.
+#define MISCS_REG_BLOCK_256B_EN                                                                              0x009074UL //Access:RW   DataWidth:0x1    // This register indicates if BMB block size is 256 byte (when programmed to 1) or 128 byte (when programmed to 0). In E4 (BigBear) it should be set to 1 in 100G and 50G modes. Reset on Hard reset.
+#define MISCS_REG_MFW_SECURITY_MODE                                                                          0x009078UL //Access:RW   DataWidth:0x3    // Determines the MFW security mode. [0] - source of privilege level, 0 - the source is external pin, 1 - the source are bits[2:1] of this register. [2:1] - privilege level to override that defined by external pin. 0 - non-secured mode; 1 - secured mode; 2 - fully-secured mode.
+#define MISCS_REG_MFW_SECURITY_MODE_IO                                                                       0x00907cUL //Access:R    DataWidth:0x2    // Privilege level as defined by external pin. 0 - non-secured mode; 1 - secured mode; 2 - fully-secured mode.
+#define MISCS_REG_NVM_WR_EN                                                                                  0x009080UL //Access:RW   DataWidth:0x2    // These bits control how the write-disable to the NVM block is generated. '0' - PROTECT: This value protects the NVM from any writes. '1' - PCI: This value allows writes only when PCI\_RST\ is high.' 2' - ALLOW: This value allows writes to the NVM using normal NVM commands. '3' - ALLOW2: This value allows writes to the NVM using normal NVM commands.
+#define MISCS_REG_DRIVER_CONTROL_0                                                                           0x009088UL //Access:RW   DataWidth:0x20   // These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_CONTROL_0_SIZE                                                                      2
+#define MISCS_REG_DRIVER_CONTROL_1                                                                           0x009090UL //Access:RW   DataWidth:0x20   // These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_CONTROL_1_SIZE                                                                      2
+#define MISCS_REG_DRIVER_CONTROL_2                                                                           0x009098UL //Access:RW   DataWidth:0x20   // These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_CONTROL_2_SIZE                                                                      2
+#define MISCS_REG_DRIVER_CONTROL_3                                                                           0x0090a0UL //Access:RW   DataWidth:0x20   // These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_CONTROL_3_SIZE                                                                      2
+#define MISCS_REG_DRIVER_CONTROL_4                                                                           0x0090a8UL //Access:RW   DataWidth:0x20   // These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_CONTROL_4_SIZE                                                                      2
+#define MISCS_REG_DRIVER_CONTROL_5                                                                           0x0090b0UL //Access:RW   DataWidth:0x20   // These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_CONTROL_5_SIZE                                                                      2
+#define MISCS_REG_DRIVER_CONTROL_6                                                                           0x0090b8UL //Access:RW   DataWidth:0x20   // These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_CONTROL_6_SIZE                                                                      2
+#define MISCS_REG_DRIVER_CONTROL_7                                                                           0x0090c0UL //Access:RW   DataWidth:0x20   // These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_CONTROL_7_SIZE                                                                      2
+#define MISCS_REG_DRIVER_CONTROL_8                                                                           0x0090c8UL //Access:RW   DataWidth:0x20   // These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_CONTROL_8_SIZE                                                                      2
+#define MISCS_REG_DRIVER_CONTROL_9                                                                           0x0090d0UL //Access:RW   DataWidth:0x20   // These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_CONTROL_9_SIZE                                                                      2
+#define MISCS_REG_DRIVER_CONTROL_10                                                                          0x0090d8UL //Access:RW   DataWidth:0x20   // These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_CONTROL_10_SIZE                                                                     2
+#define MISCS_REG_DRIVER_CONTROL_11                                                                          0x0090e0UL //Access:RW   DataWidth:0x20   // These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_CONTROL_11_SIZE                                                                     2
+#define MISCS_REG_DRIVER_CONTROL_12                                                                          0x0090e8UL //Access:RW   DataWidth:0x20   // These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_CONTROL_12_SIZE                                                                     2
+#define MISCS_REG_DRIVER_CONTROL_13                                                                          0x0090f0UL //Access:RW   DataWidth:0x20   // These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_CONTROL_13_SIZE                                                                     2
+#define MISCS_REG_DRIVER_CONTROL_14                                                                          0x0090f8UL //Access:RW   DataWidth:0x20   // These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_CONTROL_14_SIZE                                                                     2
+#define MISCS_REG_DRIVER_CONTROL_15                                                                          0x009100UL //Access:RW   DataWidth:0x20   // These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_CONTROL_15_SIZE                                                                     2
+#define MISCS_REG_DRIVER_K2_CONTROL_0_K2_E5                                                                  0x009108UL //Access:RW   DataWidth:0x20   // These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_K2_CONTROL_0_SIZE                                                                   2
+#define MISCS_REG_DRIVER_K2_CONTROL_1_K2_E5                                                                  0x009110UL //Access:RW   DataWidth:0x20   // These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_K2_CONTROL_1_SIZE                                                                   2
+#define MISCS_REG_DRIVER_K2_CONTROL_2_K2_E5                                                                  0x009118UL //Access:RW   DataWidth:0x20   // These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_K2_CONTROL_2_SIZE                                                                   2
+#define MISCS_REG_DRIVER_K2_CONTROL_3_K2_E5                                                                  0x009120UL //Access:RW   DataWidth:0x20   // These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_K2_CONTROL_3_SIZE                                                                   2
+#define MISCS_REG_DRIVER_K2_CONTROL_4_K2_E5                                                                  0x009128UL //Access:RW   DataWidth:0x20   // These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_K2_CONTROL_4_SIZE                                                                   2
+#define MISCS_REG_DRIVER_K2_CONTROL_5_K2_E5                                                                  0x009130UL //Access:RW   DataWidth:0x20   // These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_K2_CONTROL_5_SIZE                                                                   2
+#define MISCS_REG_DRIVER_K2_CONTROL_6_K2_E5                                                                  0x009138UL //Access:RW   DataWidth:0x20   // These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_K2_CONTROL_6_SIZE                                                                   2
+#define MISCS_REG_DRIVER_K2_CONTROL_7_K2_E5                                                                  0x009140UL //Access:RW   DataWidth:0x20   // These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_K2_CONTROL_7_SIZE                                                                   2
+#define MISCS_REG_RESET_PL_HV_2_K2_E5                                                                        0x009150UL //Access:RW   DataWidth:0x20   // Reset_reg: Shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0"  resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_nwm; [1] rst_nwm_mac0; [2] rst_nwm_mac1; [3] rst_nwm_mac2; [4] rst_nwm_mac3; [5] rst_nwm_gpcs0; [6] rst_nwm_gpcs1; [7] rst_nwm_gpcs2; [8] rst_nwm_gpcs3; [9] rst_nwm_xpcs0; [10] rst_nwm_xpcs1; [11] rst_nwm_xpcs2; [12] rst_nwm_xpcs3; [13] rst_nwm_xpcs4; [14] rst_nwm_xpcs5; [15] rst_nwm_xpcs6; [16] rst_nwm_xpcs7;  [17] rst_nwm_tx_lane0; [18] rst_nwm_tx_lane1; [19] rst_nwm_tx_lane2; [20] rst_nwm_tx_lane3; [21] rst_nwm_rx_lane0; [22] rst_nwm_rx_lane1; [23] rst_nwm_rx_lane2; [24] rst_nwm_rx_lane3; [25] rst_nwm_sdgb; [31:26] reserved; Global register.
+#define MISCS_REG_RESET_PL_HV_2_SIZE                                                                         3
+#define MISCS_REG_MEMCTRL_WR_RD_N_BB                                                                         0x009160UL //Access:RW   DataWidth:0x1    // wr/rd indication to CPU BIST
+#define MISCS_REG_MEMCTRL_CMD_BB                                                                             0x009164UL //Access:RW   DataWidth:0x8    // command to CPU BIST
+#define MISCS_REG_MEMCTRL_ADDRESS_BB                                                                         0x009168UL //Access:RW   DataWidth:0x8    // address to CPU BIST
+#define MISCS_REG_MEMCTRL_STATUS                                                                             0x00916cUL //Access:R    DataWidth:0x20   // status from CPU BIST
+#define MISCS_REG_BSC_SMBIO_ENABLE_GLITCH_FILTER_K2_E5                                                       0x009170UL //Access:RW   DataWidth:0x1    // When set enables the deglitching circuit for the SMBus inputs per I2C requirement.
+#define MISCS_REG_INT_STS_0                                                                                  0x009180UL //Access:R    DataWidth:0x3    // Multi Field Register.
+  #define MISCS_REG_INT_STS_0_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define MISCS_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                            0
+  #define MISCS_REG_INT_STS_0_GENERIC_SW                                                                     (0x1<<1) // Generic sw overrule; request from an occupied source or free to an unoccupied source.
+  #define MISCS_REG_INT_STS_0_GENERIC_SW_SHIFT                                                               1
+  #define MISCS_REG_INT_STS_0_CNIG_INTERRUPT                                                                 (0x1<<2) // CNIG HW interrupt.
+  #define MISCS_REG_INT_STS_0_CNIG_INTERRUPT_SHIFT                                                           2
+#define MISCS_REG_INT_MASK_0                                                                                 0x009184UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define MISCS_REG_INT_MASK_0_ADDRESS_ERROR                                                                 (0x1<<0) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_0.ADDRESS_ERROR .
+  #define MISCS_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                           0
+  #define MISCS_REG_INT_MASK_0_GENERIC_SW                                                                    (0x1<<1) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_0.GENERIC_SW .
+  #define MISCS_REG_INT_MASK_0_GENERIC_SW_SHIFT                                                              1
+  #define MISCS_REG_INT_MASK_0_CNIG_INTERRUPT                                                                (0x1<<2) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_0.CNIG_INTERRUPT .
+  #define MISCS_REG_INT_MASK_0_CNIG_INTERRUPT_SHIFT                                                          2
+#define MISCS_REG_INT_STS_WR_0                                                                               0x009188UL //Access:WR   DataWidth:0x3    // Multi Field Register.
+  #define MISCS_REG_INT_STS_WR_0_ADDRESS_ERROR                                                               (0x1<<0) // Signals an unknown address to the rf module.
+  #define MISCS_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                         0
+  #define MISCS_REG_INT_STS_WR_0_GENERIC_SW                                                                  (0x1<<1) // Generic sw overrule; request from an occupied source or free to an unoccupied source.
+  #define MISCS_REG_INT_STS_WR_0_GENERIC_SW_SHIFT                                                            1
+  #define MISCS_REG_INT_STS_WR_0_CNIG_INTERRUPT                                                              (0x1<<2) // CNIG HW interrupt.
+  #define MISCS_REG_INT_STS_WR_0_CNIG_INTERRUPT_SHIFT                                                        2
+#define MISCS_REG_INT_STS_CLR_0                                                                              0x00918cUL //Access:RC   DataWidth:0x3    // Multi Field Register.
+  #define MISCS_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                              (0x1<<0) // Signals an unknown address to the rf module.
+  #define MISCS_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                        0
+  #define MISCS_REG_INT_STS_CLR_0_GENERIC_SW                                                                 (0x1<<1) // Generic sw overrule; request from an occupied source or free to an unoccupied source.
+  #define MISCS_REG_INT_STS_CLR_0_GENERIC_SW_SHIFT                                                           1
+  #define MISCS_REG_INT_STS_CLR_0_CNIG_INTERRUPT                                                             (0x1<<2) // CNIG HW interrupt.
+  #define MISCS_REG_INT_STS_CLR_0_CNIG_INTERRUPT_SHIFT                                                       2
+#define MISCS_REG_INT_STS_1_BB                                                                               0x009190UL //Access:R    DataWidth:0xb    // Multi Field Register.
+  #define MISCS_REG_INT_STS_1_OPTE_DORQ_FIFO_ERR_ENG1_BB                                                     (0x1<<0) // DORQ FIFO error interrupt for engine 1
+  #define MISCS_REG_INT_STS_1_OPTE_DORQ_FIFO_ERR_ENG1_BB_SHIFT                                               0
+  #define MISCS_REG_INT_STS_1_OPTE_DORQ_FIFO_ERR_ENG0_BB                                                     (0x1<<1) // DORQ FIFO error interrupt for engine 0
+  #define MISCS_REG_INT_STS_1_OPTE_DORQ_FIFO_ERR_ENG0_BB_SHIFT                                               1
+  #define MISCS_REG_INT_STS_1_OPTE_DBG_FIFO_ERR_ENG1_BB                                                      (0x1<<2) // DBG FIFO error interrupt for engine 1
+  #define MISCS_REG_INT_STS_1_OPTE_DBG_FIFO_ERR_ENG1_BB_SHIFT                                                2
+  #define MISCS_REG_INT_STS_1_OPTE_DBG_FIFO_ERR_ENG0_BB                                                      (0x1<<3) // DBG FIFO error interrupt for engine 0
+  #define MISCS_REG_INT_STS_1_OPTE_DBG_FIFO_ERR_ENG0_BB_SHIFT                                                3
+  #define MISCS_REG_INT_STS_1_OPTE_BTB_IF1_FIFO_ERR_ENG1_BB                                                  (0x1<<4) // BTB_IF1 FIFO error interrupt for engine 1
+  #define MISCS_REG_INT_STS_1_OPTE_BTB_IF1_FIFO_ERR_ENG1_BB_SHIFT                                            4
+  #define MISCS_REG_INT_STS_1_OPTE_BTB_IF1_FIFO_ERR_ENG0_BB                                                  (0x1<<5) // BTB_IF1 FIFO error interrupt for engine 0
+  #define MISCS_REG_INT_STS_1_OPTE_BTB_IF1_FIFO_ERR_ENG0_BB_SHIFT                                            5
+  #define MISCS_REG_INT_STS_1_OPTE_BTB_IF0_FIFO_ERR_ENG1_BB                                                  (0x1<<6) // BTB_IF0 FIFO error interrupt for engine 1
+  #define MISCS_REG_INT_STS_1_OPTE_BTB_IF0_FIFO_ERR_ENG1_BB_SHIFT                                            6
+  #define MISCS_REG_INT_STS_1_OPTE_BTB_IF0_FIFO_ERR_ENG0_BB                                                  (0x1<<7) // BTB_IF0 FIFO error interrupt for engine 0
+  #define MISCS_REG_INT_STS_1_OPTE_BTB_IF0_FIFO_ERR_ENG0_BB_SHIFT                                            7
+  #define MISCS_REG_INT_STS_1_OPTE_BTB_SOP_FIFO_ERR_ENG1_BB                                                  (0x1<<8) // BTB_SOP FIFO error interrupt for engine 1
+  #define MISCS_REG_INT_STS_1_OPTE_BTB_SOP_FIFO_ERR_ENG1_BB_SHIFT                                            8
+  #define MISCS_REG_INT_STS_1_OPTE_BTB_SOP_FIFO_ERR_ENG0_BB                                                  (0x1<<9) // BTB_SOP FIFO error interrupt for engine 0
+  #define MISCS_REG_INT_STS_1_OPTE_BTB_SOP_FIFO_ERR_ENG0_BB_SHIFT                                            9
+  #define MISCS_REG_INT_STS_1_OPTE_STORM_FIFO_ERR_ENG0_BB                                                    (0x1<<10) // STORM FIFO error interrupt
+  #define MISCS_REG_INT_STS_1_OPTE_STORM_FIFO_ERR_ENG0_BB_SHIFT                                              10
+#define MISCS_REG_INT_MASK_1_BB                                                                              0x009194UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define MISCS_REG_INT_MASK_1_OPTE_DORQ_FIFO_ERR_ENG1_BB                                                    (0x1<<0) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_DORQ_FIFO_ERR_ENG1 .
+  #define MISCS_REG_INT_MASK_1_OPTE_DORQ_FIFO_ERR_ENG1_BB_SHIFT                                              0
+  #define MISCS_REG_INT_MASK_1_OPTE_DORQ_FIFO_ERR_ENG0_BB                                                    (0x1<<1) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_DORQ_FIFO_ERR_ENG0 .
+  #define MISCS_REG_INT_MASK_1_OPTE_DORQ_FIFO_ERR_ENG0_BB_SHIFT                                              1
+  #define MISCS_REG_INT_MASK_1_OPTE_DBG_FIFO_ERR_ENG1_BB                                                     (0x1<<2) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_DBG_FIFO_ERR_ENG1 .
+  #define MISCS_REG_INT_MASK_1_OPTE_DBG_FIFO_ERR_ENG1_BB_SHIFT                                               2
+  #define MISCS_REG_INT_MASK_1_OPTE_DBG_FIFO_ERR_ENG0_BB                                                     (0x1<<3) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_DBG_FIFO_ERR_ENG0 .
+  #define MISCS_REG_INT_MASK_1_OPTE_DBG_FIFO_ERR_ENG0_BB_SHIFT                                               3
+  #define MISCS_REG_INT_MASK_1_OPTE_BTB_IF1_FIFO_ERR_ENG1_BB                                                 (0x1<<4) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_BTB_IF1_FIFO_ERR_ENG1 .
+  #define MISCS_REG_INT_MASK_1_OPTE_BTB_IF1_FIFO_ERR_ENG1_BB_SHIFT                                           4
+  #define MISCS_REG_INT_MASK_1_OPTE_BTB_IF1_FIFO_ERR_ENG0_BB                                                 (0x1<<5) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_BTB_IF1_FIFO_ERR_ENG0 .
+  #define MISCS_REG_INT_MASK_1_OPTE_BTB_IF1_FIFO_ERR_ENG0_BB_SHIFT                                           5
+  #define MISCS_REG_INT_MASK_1_OPTE_BTB_IF0_FIFO_ERR_ENG1_BB                                                 (0x1<<6) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_BTB_IF0_FIFO_ERR_ENG1 .
+  #define MISCS_REG_INT_MASK_1_OPTE_BTB_IF0_FIFO_ERR_ENG1_BB_SHIFT                                           6
+  #define MISCS_REG_INT_MASK_1_OPTE_BTB_IF0_FIFO_ERR_ENG0_BB                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_BTB_IF0_FIFO_ERR_ENG0 .
+  #define MISCS_REG_INT_MASK_1_OPTE_BTB_IF0_FIFO_ERR_ENG0_BB_SHIFT                                           7
+  #define MISCS_REG_INT_MASK_1_OPTE_BTB_SOP_FIFO_ERR_ENG1_BB                                                 (0x1<<8) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_BTB_SOP_FIFO_ERR_ENG1 .
+  #define MISCS_REG_INT_MASK_1_OPTE_BTB_SOP_FIFO_ERR_ENG1_BB_SHIFT                                           8
+  #define MISCS_REG_INT_MASK_1_OPTE_BTB_SOP_FIFO_ERR_ENG0_BB                                                 (0x1<<9) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_BTB_SOP_FIFO_ERR_ENG0 .
+  #define MISCS_REG_INT_MASK_1_OPTE_BTB_SOP_FIFO_ERR_ENG0_BB_SHIFT                                           9
+  #define MISCS_REG_INT_MASK_1_OPTE_STORM_FIFO_ERR_ENG0_BB                                                   (0x1<<10) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_STORM_FIFO_ERR_ENG0 .
+  #define MISCS_REG_INT_MASK_1_OPTE_STORM_FIFO_ERR_ENG0_BB_SHIFT                                             10
+#define MISCS_REG_INT_STS_WR_1_BB                                                                            0x009198UL //Access:WR   DataWidth:0xb    // Multi Field Register.
+  #define MISCS_REG_INT_STS_WR_1_OPTE_DORQ_FIFO_ERR_ENG1_BB                                                  (0x1<<0) // DORQ FIFO error interrupt for engine 1
+  #define MISCS_REG_INT_STS_WR_1_OPTE_DORQ_FIFO_ERR_ENG1_BB_SHIFT                                            0
+  #define MISCS_REG_INT_STS_WR_1_OPTE_DORQ_FIFO_ERR_ENG0_BB                                                  (0x1<<1) // DORQ FIFO error interrupt for engine 0
+  #define MISCS_REG_INT_STS_WR_1_OPTE_DORQ_FIFO_ERR_ENG0_BB_SHIFT                                            1
+  #define MISCS_REG_INT_STS_WR_1_OPTE_DBG_FIFO_ERR_ENG1_BB                                                   (0x1<<2) // DBG FIFO error interrupt for engine 1
+  #define MISCS_REG_INT_STS_WR_1_OPTE_DBG_FIFO_ERR_ENG1_BB_SHIFT                                             2
+  #define MISCS_REG_INT_STS_WR_1_OPTE_DBG_FIFO_ERR_ENG0_BB                                                   (0x1<<3) // DBG FIFO error interrupt for engine 0
+  #define MISCS_REG_INT_STS_WR_1_OPTE_DBG_FIFO_ERR_ENG0_BB_SHIFT                                             3
+  #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_IF1_FIFO_ERR_ENG1_BB                                               (0x1<<4) // BTB_IF1 FIFO error interrupt for engine 1
+  #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_IF1_FIFO_ERR_ENG1_BB_SHIFT                                         4
+  #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_IF1_FIFO_ERR_ENG0_BB                                               (0x1<<5) // BTB_IF1 FIFO error interrupt for engine 0
+  #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_IF1_FIFO_ERR_ENG0_BB_SHIFT                                         5
+  #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_IF0_FIFO_ERR_ENG1_BB                                               (0x1<<6) // BTB_IF0 FIFO error interrupt for engine 1
+  #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_IF0_FIFO_ERR_ENG1_BB_SHIFT                                         6
+  #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_IF0_FIFO_ERR_ENG0_BB                                               (0x1<<7) // BTB_IF0 FIFO error interrupt for engine 0
+  #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_IF0_FIFO_ERR_ENG0_BB_SHIFT                                         7
+  #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_SOP_FIFO_ERR_ENG1_BB                                               (0x1<<8) // BTB_SOP FIFO error interrupt for engine 1
+  #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_SOP_FIFO_ERR_ENG1_BB_SHIFT                                         8
+  #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_SOP_FIFO_ERR_ENG0_BB                                               (0x1<<9) // BTB_SOP FIFO error interrupt for engine 0
+  #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_SOP_FIFO_ERR_ENG0_BB_SHIFT                                         9
+  #define MISCS_REG_INT_STS_WR_1_OPTE_STORM_FIFO_ERR_ENG0_BB                                                 (0x1<<10) // STORM FIFO error interrupt
+  #define MISCS_REG_INT_STS_WR_1_OPTE_STORM_FIFO_ERR_ENG0_BB_SHIFT                                           10
+#define MISCS_REG_INT_STS_CLR_1_BB                                                                           0x00919cUL //Access:RC   DataWidth:0xb    // Multi Field Register.
+  #define MISCS_REG_INT_STS_CLR_1_OPTE_DORQ_FIFO_ERR_ENG1_BB                                                 (0x1<<0) // DORQ FIFO error interrupt for engine 1
+  #define MISCS_REG_INT_STS_CLR_1_OPTE_DORQ_FIFO_ERR_ENG1_BB_SHIFT                                           0
+  #define MISCS_REG_INT_STS_CLR_1_OPTE_DORQ_FIFO_ERR_ENG0_BB                                                 (0x1<<1) // DORQ FIFO error interrupt for engine 0
+  #define MISCS_REG_INT_STS_CLR_1_OPTE_DORQ_FIFO_ERR_ENG0_BB_SHIFT                                           1
+  #define MISCS_REG_INT_STS_CLR_1_OPTE_DBG_FIFO_ERR_ENG1_BB                                                  (0x1<<2) // DBG FIFO error interrupt for engine 1
+  #define MISCS_REG_INT_STS_CLR_1_OPTE_DBG_FIFO_ERR_ENG1_BB_SHIFT                                            2
+  #define MISCS_REG_INT_STS_CLR_1_OPTE_DBG_FIFO_ERR_ENG0_BB                                                  (0x1<<3) // DBG FIFO error interrupt for engine 0
+  #define MISCS_REG_INT_STS_CLR_1_OPTE_DBG_FIFO_ERR_ENG0_BB_SHIFT                                            3
+  #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_IF1_FIFO_ERR_ENG1_BB                                              (0x1<<4) // BTB_IF1 FIFO error interrupt for engine 1
+  #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_IF1_FIFO_ERR_ENG1_BB_SHIFT                                        4
+  #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_IF1_FIFO_ERR_ENG0_BB                                              (0x1<<5) // BTB_IF1 FIFO error interrupt for engine 0
+  #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_IF1_FIFO_ERR_ENG0_BB_SHIFT                                        5
+  #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_IF0_FIFO_ERR_ENG1_BB                                              (0x1<<6) // BTB_IF0 FIFO error interrupt for engine 1
+  #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_IF0_FIFO_ERR_ENG1_BB_SHIFT                                        6
+  #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_IF0_FIFO_ERR_ENG0_BB                                              (0x1<<7) // BTB_IF0 FIFO error interrupt for engine 0
+  #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_IF0_FIFO_ERR_ENG0_BB_SHIFT                                        7
+  #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_SOP_FIFO_ERR_ENG1_BB                                              (0x1<<8) // BTB_SOP FIFO error interrupt for engine 1
+  #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_SOP_FIFO_ERR_ENG1_BB_SHIFT                                        8
+  #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_SOP_FIFO_ERR_ENG0_BB                                              (0x1<<9) // BTB_SOP FIFO error interrupt for engine 0
+  #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_SOP_FIFO_ERR_ENG0_BB_SHIFT                                        9
+  #define MISCS_REG_INT_STS_CLR_1_OPTE_STORM_FIFO_ERR_ENG0_BB                                                (0x1<<10) // STORM FIFO error interrupt
+  #define MISCS_REG_INT_STS_CLR_1_OPTE_STORM_FIFO_ERR_ENG0_BB_SHIFT                                          10
+#define MISCS_REG_PRTY_MASK_0                                                                                0x0091a4UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define MISCS_REG_PRTY_MASK_0_CNIG_PARITY                                                                  (0x1<<0) // This bit masks, when set, the Parity bit: MISCS_REG_PRTY_STS_0.CNIG_PARITY .
+  #define MISCS_REG_PRTY_MASK_0_CNIG_PARITY_SHIFT                                                            0
+#define MISCS_REG_PCIE_LINK_UP_STATE_K2_E5                                                                   0x0093c0UL //Access:R    DataWidth:0x1    // Indicates the current state of the ptw_miscs_pcie_link_up signal which is driven by the PCIE core - a pulse at the beginning of PCIe link up.
+#define MISCS_REG_PCIE_HOT_RESET_STATE_K2_E5                                                                 0x0093c4UL //Access:R    DataWidth:0x1    // Indicates the current state of the ptw_miscs_pcie_hot_reset signal which is driven by the PCIE core - a pulse at the beginning of PCIe hot reset.
+#define MISCS_REG_HOT_RESET_PREPARED_CNT_K2_E5                                                               0x0093c8UL //Access:RW   DataWidth:0x10   // Accounts for HOT RESET assertion when the chip is in prepared state. Is reset on POR reset.
+#define MISCS_REG_HOT_RESET_UNPREPARED_CNT_K2_E5                                                             0x0093ccUL //Access:RW   DataWidth:0x10   // Accounts for HOT RESET assertion when the chip is in un-prepared state. Is reset on POR reset.
+#define MISCS_REG_PCIE_LINK_UP_CNT_K2_E5                                                                     0x0093d0UL //Access:RW   DataWidth:0x10   // Accounts for PCIE LINK UP assertion. Is reset on POR reset.
+#define MISCS_REG_MAIN_PLL_STATUS_K2_E5                                                                      0x0093d4UL //Access:RW   DataWidth:0x1    // Set to 1 when main PLL lock indication is de-asserted when hard reset is de-asserted. Reset to 0 by FW. Is reset on POR reset.
+#define MISCS_REG_GPIO0_DRIVER                                                                               0x009400UL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO0. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO1_DRIVER                                                                               0x009404UL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO1. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO2_DRIVER                                                                               0x009408UL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO2. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO3_DRIVER                                                                               0x00940cUL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO3. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO4_DRIVER                                                                               0x009410UL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO4. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO5_DRIVER                                                                               0x009414UL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO5. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO6_DRIVER                                                                               0x009418UL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO6. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO7_DRIVER                                                                               0x00941cUL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO7. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO8_DRIVER                                                                               0x009420UL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO8. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO9_DRIVER                                                                               0x009424UL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO9. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO10_DRIVER                                                                              0x009428UL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO10. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO11_DRIVER                                                                              0x00942cUL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO11. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO12_DRIVER                                                                              0x009430UL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO12. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO13_DRIVER                                                                              0x009434UL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO13. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO14_DRIVER                                                                              0x009438UL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO14. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO15_DRIVER                                                                              0x00943cUL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO15. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO16_DRIVER                                                                              0x009440UL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO16. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO17_DRIVER                                                                              0x009444UL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO17. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO18_DRIVER                                                                              0x009448UL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO18. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO19_DRIVER                                                                              0x00944cUL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO19. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO20_DRIVER                                                                              0x009450UL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO20. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO21_DRIVER                                                                              0x009454UL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO21. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO22_DRIVER                                                                              0x009458UL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO22. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO23_DRIVER                                                                              0x00945cUL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO23. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO24_DRIVER                                                                              0x009460UL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO24. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO25_DRIVER                                                                              0x009464UL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO25. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO26_DRIVER                                                                              0x009468UL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO26. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO27_DRIVER                                                                              0x00946cUL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO27. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO28_DRIVER                                                                              0x009470UL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO28. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO29_DRIVER                                                                              0x009474UL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO29. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO30_DRIVER                                                                              0x009478UL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO30. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO31_DRIVER                                                                              0x00947cUL //Access:RW   DataWidth:0x2    // Defines what is the driver of GPIO31. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);
+#define MISCS_REG_GPIO_FLOAT                                                                                 0x009480UL //Access:RW   DataWidth:0x20   // FLOAT: When any of these bits is written as a '1'; the corresponding GPIO bit will turn off it's drivers and become an input. This is the reset state of all GPIO pins.
+#define MISCS_REG_GPIO0_CTRL_SHARED                                                                          0x009484UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO1_CTRL_SHARED                                                                          0x009488UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO2_CTRL_SHARED                                                                          0x00948cUL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO3_CTRL_SHARED                                                                          0x009490UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO4_CTRL_SHARED                                                                          0x009494UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO5_CTRL_SHARED                                                                          0x009498UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO6_CTRL_SHARED                                                                          0x00949cUL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO7_CTRL_SHARED                                                                          0x0094a0UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO8_CTRL_SHARED                                                                          0x0094a4UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO9_CTRL_SHARED                                                                          0x0094a8UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO10_CTRL_SHARED                                                                         0x0094acUL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO11_CTRL_SHARED                                                                         0x0094b0UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO12_CTRL_SHARED                                                                         0x0094b4UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO13_CTRL_SHARED                                                                         0x0094b8UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO14_CTRL_SHARED                                                                         0x0094bcUL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO15_CTRL_SHARED                                                                         0x0094c0UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO16_CTRL_SHARED                                                                         0x0094c4UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO17_CTRL_SHARED                                                                         0x0094c8UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO18_CTRL_SHARED                                                                         0x0094ccUL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO19_CTRL_SHARED                                                                         0x0094d0UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO20_CTRL_SHARED                                                                         0x0094d4UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO21_CTRL_SHARED                                                                         0x0094d8UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO22_CTRL_SHARED                                                                         0x0094dcUL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO23_CTRL_SHARED                                                                         0x0094e0UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO24_CTRL_SHARED                                                                         0x0094e4UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO25_CTRL_SHARED                                                                         0x0094e8UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO26_CTRL_SHARED                                                                         0x0094ecUL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO27_CTRL_SHARED                                                                         0x0094f0UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO28_CTRL_SHARED                                                                         0x0094f4UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO29_CTRL_SHARED                                                                         0x0094f8UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO30_CTRL_SHARED                                                                         0x0094fcUL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO31_CTRL_SHARED                                                                         0x009500UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO0_CTRL_PATH                                                                            0x009504UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO1_CTRL_PATH                                                                            0x009508UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO2_CTRL_PATH                                                                            0x00950cUL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO3_CTRL_PATH                                                                            0x009510UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO4_CTRL_PATH                                                                            0x009514UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO5_CTRL_PATH                                                                            0x009518UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO6_CTRL_PATH                                                                            0x00951cUL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO7_CTRL_PATH                                                                            0x009520UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO8_CTRL_PATH                                                                            0x009524UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO9_CTRL_PATH                                                                            0x009528UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO10_CTRL_PATH                                                                           0x00952cUL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO11_CTRL_PATH                                                                           0x009530UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO12_CTRL_PATH                                                                           0x009534UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO13_CTRL_PATH                                                                           0x009538UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO14_CTRL_PATH                                                                           0x00953cUL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO15_CTRL_PATH                                                                           0x009540UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO16_CTRL_PATH                                                                           0x009544UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO17_CTRL_PATH                                                                           0x009548UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO18_CTRL_PATH                                                                           0x00954cUL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO19_CTRL_PATH                                                                           0x009550UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO20_CTRL_PATH                                                                           0x009554UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO21_CTRL_PATH                                                                           0x009558UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO22_CTRL_PATH                                                                           0x00955cUL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO23_CTRL_PATH                                                                           0x009560UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO24_CTRL_PATH                                                                           0x009564UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO25_CTRL_PATH                                                                           0x009568UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO26_CTRL_PATH                                                                           0x00956cUL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO27_CTRL_PATH                                                                           0x009570UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO28_CTRL_PATH                                                                           0x009574UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO29_CTRL_PATH                                                                           0x009578UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO30_CTRL_PATH                                                                           0x00957cUL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO31_CTRL_PATH                                                                           0x009580UL //Access:RW   DataWidth:0x2    // GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.
+#define MISCS_REG_GPIO_VAL                                                                                   0x009584UL //Access:R    DataWidth:0x20   // These bits indicate the read value of each of the 32 GPIO pins. This is the result value of the pin; not the drive value.
+#define MISCS_REG_GPIO0_INT                                                                                  0x009588UL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO1_INT                                                                                  0x00958cUL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO2_INT                                                                                  0x009590UL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO3_INT                                                                                  0x009594UL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO4_INT                                                                                  0x009598UL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO5_INT                                                                                  0x00959cUL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO6_INT                                                                                  0x0095a0UL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO7_INT                                                                                  0x0095a4UL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO8_INT                                                                                  0x0095a8UL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO9_INT                                                                                  0x0095acUL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO10_INT                                                                                 0x0095b0UL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO11_INT                                                                                 0x0095b4UL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO12_INT                                                                                 0x0095b8UL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO13_INT                                                                                 0x0095bcUL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO14_INT                                                                                 0x0095c0UL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO15_INT                                                                                 0x0095c4UL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO16_INT                                                                                 0x0095c8UL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO17_INT                                                                                 0x0095ccUL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO18_INT                                                                                 0x0095d0UL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO19_INT                                                                                 0x0095d4UL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO20_INT                                                                                 0x0095d8UL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO21_INT                                                                                 0x0095dcUL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO22_INT                                                                                 0x0095e0UL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO23_INT                                                                                 0x0095e4UL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO24_INT                                                                                 0x0095e8UL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO25_INT                                                                                 0x0095ecUL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO26_INT                                                                                 0x0095f0UL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO27_INT                                                                                 0x0095f4UL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO28_INT                                                                                 0x0095f8UL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO29_INT                                                                                 0x0095fcUL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO30_INT                                                                                 0x009600UL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO31_INT                                                                                 0x009604UL //Access:RW   DataWidth:0x4    // GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).
+#define MISCS_REG_GPIO_EVENT_EN                                                                              0x009608UL //Access:RW   DataWidth:0x20   // These bits enable the GPIO_INTs to signals event to the IGU/MCP for GPIO0..31.
+#define MISCS_REG_DRIVER_K2_CONTROL_8_K2_E5                                                                  0x009610UL //Access:RW   DataWidth:0x20   // These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_K2_CONTROL_8_SIZE                                                                   2
+#define MISCS_REG_DRIVER_K2_CONTROL_9_K2_E5                                                                  0x009618UL //Access:RW   DataWidth:0x20   // These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_K2_CONTROL_9_SIZE                                                                   2
+#define MISCS_REG_DRIVER_K2_CONTROL_10_K2_E5                                                                 0x009620UL //Access:RW   DataWidth:0x20   // These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_K2_CONTROL_10_SIZE                                                                  2
+#define MISCS_REG_DRIVER_K2_CONTROL_11_K2_E5                                                                 0x009628UL //Access:RW   DataWidth:0x20   // These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_K2_CONTROL_11_SIZE                                                                  2
+#define MISCS_REG_DRIVER_K2_CONTROL_12_K2_E5                                                                 0x009630UL //Access:RW   DataWidth:0x20   // These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_K2_CONTROL_12_SIZE                                                                  2
+#define MISCS_REG_DRIVER_K2_CONTROL_13_K2_E5                                                                 0x009638UL //Access:RW   DataWidth:0x20   // These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_K2_CONTROL_13_SIZE                                                                  2
+#define MISCS_REG_DRIVER_K2_CONTROL_14_K2_E5                                                                 0x009640UL //Access:RW   DataWidth:0x20   // These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_K2_CONTROL_14_SIZE                                                                  2
+#define MISCS_REG_DRIVER_K2_CONTROL_15_K2_E5                                                                 0x009648UL //Access:RW   DataWidth:0x20   // These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
+#define MISCS_REG_DRIVER_K2_CONTROL_15_SIZE                                                                  2
+#define MISCS_REG_BSC_SDA_SEL_K2_E5                                                                          0x009650UL //Access:RW   DataWidth:0x2    // 00: connect SDA interface to BSC_SDA0 IO. 01: connect SDA interface to BSC_SDA1 IO. 10: connect SDA interface to BSC_SDA2 IO. 11: connect SDA interface to BSC_SDA3 IO.
+#define MISCS_REG_CHIP_CORE_RESET_SOURCE_K2_E5                                                               0x009654UL //Access:RW   DataWidth:0x3    // Bit[0]: PERST# IO de-assertion. If == 1, triggers chip core reset. If == 0, doesn't trigger chip core reset. Bit[1]: PCIE HOT reset. If == 1, triggers chip core reset. If == 0, doesn't trigger chip core reset. Bit[2]: PCIE link is up. If == 1, triggers chip core reset. If == 0, doesn't trigger chip core reset. More than one bit can be set to 1. This register is reset on hard reset event.
+#define MISCS_REG_WOL_CONFIG_K2_E5                                                                           0x009658UL //Access:RW   DataWidth:0x2    // Bit[0]: Out of the Box (OOB) WOL enable. Set to 1 to enable use of NIC magic packet detection to assert WAKE OOB. Reset on POR reset and PERST# de-assert. Bit[1]: WAKE control  direct MFW control of the WAKE# IO. Set to 1 to asserts WAKE# = 0. Reset on POR reset and PERST# de-assert.
+#define MISCS_REG_PCIE_CORE_RST_N_STATUS_K2_E5                                                               0x00965cUL //Access:RW   DataWidth:0x1    // When 0, indicated PCIE EP controller is in reset, except for PMC module. Refer to PCIE EP controller databook.
+#define MISCS_REG_PCIE_PHY_RST_N_STATUS_K2_E5                                                                0x009660UL //Access:RW   DataWidth:0x1    // When 0, indicated PCIE PHY is in reset Refer to PCIE PHY user manual.
+#define MISCS_REG_CORE_RST_N_STATUS_K2_E5                                                                    0x0096b8UL //Access:R    DataWidth:0x1    // Chip core_rst_n status. 0 - asserted; 1 - de-asserted.
+#define MISCS_REG_LINK_HOLDOFF_STATUS                                                                        0x0096bcUL //Access:R    DataWidth:0x2    // Indicates if MISC_REGISTERS_LINK_HOLDOFF_REQ.LINK_HOLDOFF_REQ succeeded or failed. Once MISC_REGISTERS_LINK_HOLDOFF_REQ.LINK_HOLDOFF_REQ is set, this register should be polled till one of the fields is set to 1. Bit 0 : LINK_HOLDOFF_SUCCESS When =1,  indicates the PCIE link is successfully being held from starting training. Used in conjunction with MISC_REGISTERS_LINK_HOLDOFF_REQ.LINK_HOLDOFF_REQ . Bit 1 : LINK_HOLDOFF_FAILURE When =1, indicates the PCIE link is failed to being held from starting training. Used in conjunction with MISC_REGISTERS_LINK_HOLDOFF_REQ.LINK_HOLDOFF_REQ .
+#define MISCS_REG_LINK_HOLDOFF_REQ                                                                           0x0096c0UL //Access:RW   DataWidth:0x1    // This bit is written to a '1' to request that the PCIE link not begin training yet. Software should set this bit; and then check the MISC_REGISTERS_LINK_HOLDOFF_STATUS.LINK_HOLDOFF_STATUS register. Pulling may be required till one of the fields is set: If MISC_REGISTERS_LINK_HOLDOFF_STATUS.LINK_HOLDOFF_SUCCESS is set; configure the PCIE link and then clear this bit. If MISC_REGISTERS_LINK_HOLDOFF_STATUS.LINK_HOLDOFF_FAILURE is set; the PCIE link has already begun training so it's too late to do any configuration. Clear this bit.
+#define MISCS_REG_GENERIC_HW_0                                                                               0x0096c4UL //Access:RW   DataWidth:0x20   // Debug only: spare RW register reset by hard reset. Reset on hard reset.
+#define MISCS_REG_GENERIC_HW_1                                                                               0x0096c8UL //Access:RW   DataWidth:0x20   // Debug only: spare RW register reset by hard reset. Reset on hard reset.
+#define MISCS_REG_GENERIC_CR_0                                                                               0x0096ccUL //Access:RW   DataWidth:0x20   // Debug only: spare RW register reset by core reset. Reset on core reset.
+#define MISCS_REG_GENERIC_CR_1                                                                               0x0096d0UL //Access:RW   DataWidth:0x20   // Debug only: spare RW register reset by core reset. Reset on core reset.
+#define MISCS_REG_GENERIC_POR_0                                                                              0x0096d4UL //Access:RW   DataWidth:0x20   // Debug only: spare RW register reset by por reset. bit 0 is used for Vmain state machine system kill reset. If clear will not reset all the Vmain sm (backward compatible); if set will reset all the Vmain state machine. Reset on POR reset.
+#define MISCS_REG_GENERIC_POR_1                                                                              0x0096d8UL //Access:RW   DataWidth:0x20   // Debug only: spare RW register reset by por reset. Reset on POR reset.
+#define MISCS_REG_GEN_PURP_HWG                                                                               0x0096dcUL //Access:RW   DataWidth:0x20   // Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO can not be configured as an output. Each output has its output enable in the MCP register space; but this bit needs to be set to make use of that. Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON. When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change the i/o to an output and will drive the TimeSync output. Bit[31:7]: spare. Global register. Reset by hard reset.
+#define MISCS_REG_GEN_PURP_CRG                                                                               0x0096e0UL //Access:RW   DataWidth:0x20   // Debug only: spare RW register reset by core reset. Bit[0]: used for VCCMIN control to select 25MHz clock on XMAC; UMAC and PCIE Serdes. Global register.
+#define MISCS_REG_GEN_PURP_PORG                                                                              0x0096e4UL //Access:RW   DataWidth:0x20   // Debug only: [31:11] - spare RW register reset by por reset; [10:8] : PCIe Device Type: 3'b000 - Endpoint mode; 3'b010 - RC mode; 3'b011 - RC mode, with Refclk provided by Serdes. [7:5] - spare RW register reset by por reset; [4] - SW control to the serdes uController reset. When =1 the serdes uController is reset; [3] - when 1 reset the Vmain Switching Regulator Controller PMU registers; [2] - when 1 disable the Vmain Switching Regulator Controller; [1] -  when 1 reset the Vmgmt Switching Regulator Controller PMU registers; [0] - when 1 disable the Vmgmt Switching Regulator Controller. Global register.
+#define MISCS_REG_ISOLATION_LOGIC                                                                            0x0096e8UL //Access:R    DataWidth:0x1    // The isolation between Vaux and Vmain read value.
+#define MISCS_REG_VMAIN_POR                                                                                  0x0096ecUL //Access:RW   DataWidth:0x2    // 0-bypass the Vmain PORBG. for Vmain POR; if sel=1 the output wil be MISC_REGISTERS_VMAIN_POR.VMAIN_POR [1]; 1- bypass the Vmain PORBG. If MISC_REGISTERS_VMAIN_POR.VMAIN_POR [0] is '1' the output of Vmain POR will be this field.
+#define MISCS_REG_FUNCTION_HIDE_BB_K2                                                                        0x0096f0UL //Access:RW   DataWidth:0x10   // Reserved.
+#define MISCS_REG_PWR_ATTN                                                                                   0x0096f4UL //Access:RW   DataWidth:0x1    // This bit indicates that a Vmain powerdown event occurred. Write 0 to clear the event. Reset on hard reset.
+#define MISCS_REG_SMBIO_ENABLE_GLITCH_FILTER                                                                 0x0096f8UL //Access:RW   DataWidth:0x1    // When set enables the deglitching circuit for the SMBus inputs per I2C requirement.
+#define MISCS_REG_PCIE_HOT_RESET                                                                             0x0096fcUL //Access:RC   DataWidth:0x1    // If set indicate that the pcie_rst_b was asserted without perst assertion.
+#define MISCS_REG_FUNC_HIDE_PIN                                                                              0x009700UL //Access:R    DataWidth:0x1    // Synchronised value of ifmux_misc_func_hide.
+#define MISCS_REG_NIG_DBG_VECTOR_BB                                                                          0x009704UL //Access:RW   DataWidth:0x1    // NIG debug mux vector control. 0 - NIG0 debug vector is output to IFMUX; 1 -  NIG1 debug vector is output to IFMUX.
+#define MISCS_REG_FOUR_PORT_SHARED_MDIO_EN                                                                   0x009708UL //Access:RW   DataWidth:0x1    // When set this will allow any of the four emacs MDIO masters to initiate MDIO transactions to access XGXS0 or the four external GPHYs. Drives misc_cnig_mux_4port_shared_mdio_en output. Applicable both in 2-port and 4-port mode. TBD: unconnected in NM. Reserved.
+#define MISCS_REG_SEL_DBG_IFMUX_TEST                                                                         0x00970cUL //Access:RW   DataWidth:0x1    // NIG EMAC debug source selector. If 0 - path0 gmii/mii emac debug outputs are selected by NIG; If 1 - path1 gmii/mii emac debug outputs are selected by NIG. Drives output misc_cnig_sel_dbg_ifmux_test. TBD: unconnected in NM. Reserved.
+#define MISCS_REG_SEL_VAUX                                                                                   0x009710UL //Access:R    DataWidth:0x2    // SEL_VAUX_B - Control to power switching logic. [0] - output value driven by MISC; [1] - RESERVED.
+#define MISCS_REG_PCIE_DIS                                                                                   0x009714UL //Access:RW   DataWidth:0x1    // PCIE disable register bit. PCIE DIS. Has same functionality as the external IO PCIE_DIS: Internal PCIE DIS = external IO PCIE DIS or MISCS_REG_PCIE_DIS.
+#define MISCS_REG_CLK_NW_MAC_FAST_MODE                                                                       0x009718UL //Access:RW   DataWidth:0x1    // When set to 1, HiGig is supported on 40G and the nw mac clock frequency is higher than the main clock frequency. When set to 0, HiGig is not supported on 40G and the nw mac clock frequency is identical to the main clock frequency. Applicable only for K2.
+#define MISCS_REG_CMT_ENABLED_FOR_PAIR                                                                       0x00971cUL //Access:RW   DataWidth:0x8    // For Coupled Mode Teaming. Each bit corresponds to a PF pair i.e. bit 0 for global PFs 0 and 1; bit 1 for global PFs 2 and 3. If the bit is clear then the PFs for that pair are not coupled and the even PF is mapped to path 0 and the odd PF is mapped to path 1. This is the same mapping E2 and E3 have. If the bit is set then those PFs are coupled. In this case the even PF is mapped to both paths and the odd PF is disabled.
+#define MISCS_REG_ISOLATE_PATH                                                                               0x009720UL //Access:RW   DataWidth:0x1    // This bit will be set by the MCP when the device works in PDA mode. The value of this register also drives the isolate_path output of the MISC block.
+#define MISCS_REG_MDIO_OVERRIDE                                                                              0x009724UL //Access:RW   DataWidth:0x1    // MDIO Override. Enables the values on MISC_REGISTERS_MDIO_SUBSCRIPTION.MDIO_SUBSCRIPTION to override the hardware mode defined defaults. Global register. Reset on Hard reset. TBD: unconnected in NM. Reserved.
+#define MISCS_REG_MDIO_SUBSCRIPTION                                                                          0x009728UL //Access:RW   DataWidth:0x20   // MDIO Subscription. Is used to configure the subscriptions of on-chip PHY devices and MAC ports to the four MDIO domains. It is only used when MISC_REGISTERS_MDIO_OVERRIDE.MDIO_OVERRIDE is set. [3:0] - ch0_rr; [7:4] - ch1_rr; [11:8] - ch2_rr; [15:12] - ch3_rr; [19:16] - ch0_phy; [23:20] - ch1_phy; [27:24] - ch2_phy; [31:28] - ch3_phy. Global register. Reset on Hard reset. TBD: unconnected in NM. Reserved.
+#define MISCS_REG_HOT_RESET_UNPREPARED                                                                       0x00972cUL //Access:RW   DataWidth:0x1    // Set to 1 when pcie_hot_reset is asserted (Hot Reset / SBR / Link Down / Link Disable) and the chip is in un-prepared state. Reset to 0 by the FW. Reset on por reset.
+#define MISCS_REG_OTP_MISC_DO                                                                                0x009730UL //Access:R    DataWidth:0x5    // OTP IO 5 msb.
+#define MISCS_REG_PARITY_MODE                                                                                0x009734UL //Access:RW   DataWidth:0x1    // Debug only : parity mode to MCP. Setting this bit changes the parity checking on the memories from even to odd parity. Global register.
+#define MISCS_REG_IPOR_CMD_REG                                                                               0x009738UL //Access:RW   DataWidth:0x1    // Writing this bit as a '1' will cause the chip to do an internal reset exactly like a power-up reset. There is not protection for this request and it may cause any current PCI cycle to lock up. Reset on hard reset.
+#define MISCS_REG_MAIN_SEQ_BYP_SEL                                                                           0x00973cUL //Access:RW   DataWidth:0x5    // Debug only. main_sequencer_bypass select. For each bit; when set; the compatible bit in the MISC_REGISTERS_MAIN_SEQ_BYP_VAL.MAIN_SEQ_BYP_VAL affects the controls; when reset; the SM affects the controls. Bit 0 - Vmain OTP reset; Bit 1 - isolation_logic_b; Bit 2 - unprepared_power_down_detection; Bit 3 - PCIE_reset_b; Bit 4 - sel_vaux_b. Reset on hard reset.
+#define MISCS_REG_MAIN_SEQ_BYP_VAL                                                                           0x009740UL //Access:RW   DataWidth:0x5    // Debug only. main_sequencer_bypass values. For each bit; the written value affects the control only if the compatible bit in the MISC_REGISTERS_MAIN_SEQ_BYP_SEL.MAIN_SEQ_BYP_VAL is set; when reset; the SM affects the controls. Bit 0 - Vmain OTP reset; Bit 1 - isolation_logic_b; Bit 2 - uprepared_power_down_detection; Bit 3 - PCIE_reset_b; Bit 4 - sel_vaux_b. Reset on hard reset.
+#define MISCS_REG_UNCOND_ENTER_PLAY_DEAD                                                                     0x009744UL //Access:RW   DataWidth:0x1    // Writing to this register results in resetting entire chip via the play dead mechanism.
+#define MISCS_REG_COND_ENTER_PLAY_DEAD                                                                       0x009748UL //Access:RW   DataWidth:0x1    // Writing to this register result with resetting entire chip via the play dead mechanism if PERST is asserted.
+#define MISCS_REG_PLL_MAIN_CTRL_4                                                                            0x00974cUL //Access:RW   DataWidth:0x2    // Bit0 = Controls the glitch-less mux control source: 0-management power sequencer output; 1-glich-less mux manual setting (bit 1 in this regitser); reset (to 0) with hard_rst_b. bit1 =Glichless mux manual setting has affect when bit 0 = 1: 0-select USPLL clock; 1-select 25Mhz (ref clock); Reset (to 0) with hard_rst_b. Reset on POR reset.
+#define MISCS_REG_PLL_STORM_CTRL_4                                                                           0x009750UL //Access:RW   DataWidth:0x1    // [0]clock storm bypass: 0-select Storm SPLL clock; 1-select external clock; Reset on POR reset.
+#define MISCS_REG_UNPREPARED                                                                                 0x009754UL //Access:RW   DataWidth:0x1    // Set by the MCP to remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset on hard reset.
+#define MISCS_REG_UNPREPARED_FW                                                                              0x009758UL //Access:RW   DataWidth:0x1    // Set by the MCP to remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset on hard reset.
+#define MISCS_REG_UNPREPARED_DR                                                                              0x00975cUL //Access:RW   DataWidth:0x1    // Set by the Driver to remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset on hard reset.
+#define MISCS_REG_VAUX_PRESENT                                                                               0x009760UL //Access:R    DataWidth:0x1    // 0 - VAUX is not present; 1 - VAUX is present.
+#define MISCS_REG_VAUX_EN_DIS                                                                                0x009764UL //Access:RW   DataWidth:0x8    // VAUX ENABLE Chip IO: when pulsed low enables supply from VAUX. VAUX DISABLE Chip IO: when pulsed low disables supply form VAUX. [7-6] RESERVED (FLOAT: these IOs are outputs only). [5-4] CLR: When any of these bits is written as a '1', the corresponding vaux_enable [bit 4]/ vaux_disable [bit 5] chip IOs will drive low. The read value of these bits will be '1' if the last command ( SET ; CLR ; or FLOAT ) for this bit was a CLR . (Reset value 0). [3-2] SET: When any of these bits is written as a '1', the corresponding vaux_enable [bit 2] / vaux_disable [bit 3] chip IOs will drive high. The read value of these bits will be '1' if the last command ( SET ; CLR ; or FLOAT ) for this bit was a SET . (Reset value 0). [1-0] RESERVED (VALUE RO). Global register.
+#define MISCS_REG_VAUX_EN_DIS_INT                                                                            0x009768UL //Access:RW   DataWidth:0x8    // RESERVED.
+#define MISCS_REG_CHIP_NUM                                                                                   0x00976cUL //Access:R    DataWidth:0x10   // These bits indicate the part number for the chip.
+#define MISCS_REG_CHIP_REV                                                                                   0x009770UL //Access:R    DataWidth:0x4    // These bits indicate the base revision of the chip. This value starts at 0x0 for the A0 tape-out and increments by one for each all-layer tape-out.
+#define MISCS_REG_CHIP_METAL                                                                                 0x009774UL //Access:R    DataWidth:0x8    // These bits indicate the metal revision of the chip. This value starts at 0x00 for each all-layer tape-out and increments by one for each tape-out.
+#define MISCS_REG_CHIP_TEST_REG                                                                              0x009778UL //Access:R    DataWidth:0x8    // These bits indicate the silent revision of the chip.
+#define MISCS_REG_LINK_IN_L23                                                                                0x00977cUL //Access:R    DataWidth:0x1    // When this bit is 1 it indicates that the link is down and PCIE is prepared for operation off of VAUX. TBD: set to 0 in NM. Reserved.
+#define MISCS_REG_PCIE_DIS_IO                                                                                0x009780UL //Access:R    DataWidth:0x1    // This bit reports the current state of the PCIE_DIS pin. If this bit is 1 it means that the LOM design has been strapped to support management only. The PCI power will always read as '0' in this state; as if the chip is in Out-Of-Box WOL mode.
+#define MISCS_REG_INTERNAL_PERST_N                                                                           0x009784UL //Access:R    DataWidth:0x1    // The status of the internal perst_n control (active low) that goes to the PCIE CORE.
+#define MISCS_REG_HRST_ASSERT_CNT                                                                            0x009788UL //Access:RW   DataWidth:0x10   // Accounts for Hard reset assertion. Is reset on POR reset.
+#define MISCS_REG_HRST_DEASSERT_CNT                                                                          0x00978cUL //Access:RW   DataWidth:0x10   // Accounts for Hard reset de-assertion. Is reset on POR reset.
+#define MISCS_REG_CRST_ASSERT_CNT                                                                            0x009790UL //Access:RW   DataWidth:0x10   // Accounts for Core reset assertion. Is reset on POR reset.
+#define MISCS_REG_CRST_DEASSERT_CNT                                                                          0x009794UL //Access:RW   DataWidth:0x10   // Accounts for Core de-reset assertion. Is reset on POR reset.
+#define MISCS_REG_PERST_ASSERT_CNT                                                                           0x009798UL //Access:RW   DataWidth:0x10   // Accounts for PERST_B reset assertion. Is reset on POR reset.
+#define MISCS_REG_PERST_DEASSERT_CNT                                                                         0x00979cUL //Access:RW   DataWidth:0x10   // Accounts for PERST_B reset de-assertion. Is reset on POR reset.
+#define MISCS_REG_PCIE_RST_PREPARED_ASSERT_CNT_BB                                                            0x0097a0UL //Access:RW   DataWidth:0x10   // Accounts for PCI_RST_N assertion when the chip is in prepared state. Is reset on POR reset.
+#define MISCS_REG_PCIE_RST_UNPREPARED_ASSERT_CNT_BB                                                          0x0097a4UL //Access:RW   DataWidth:0x10   // Accounts for PCI_RST_N assertion when the chip is in un-prepared state. Is reset on POR reset.
+#define MISCS_REG_PCIE_RST_DEASSERT_CNT_BB                                                                   0x0097a8UL //Access:RW   DataWidth:0x10   // Accounts for PCI_RST_N de-assertion. Is reset on POR reset.
+#define MISCS_REG_HOT_RESET_EN                                                                               0x0097acUL //Access:RW   DataWidth:0x1    // When =1, when ptw_miscs_pcie_hot_reset is asserted (Hot Reset / SBR / Link Down / Link Disable) and the chip is in un-prepared state, hard reset is asserted. When =0, when ptw_miscs_pcie_hot_reset is asserted (Hot Reset / SBR / Link Down / Link Disable) and the chip is in un-prepared state, hard reset is not asserted. Reset on por reset.
+#define MISCS_REG_PCIE_RST_N_BB                                                                              0x0097b0UL //Access:R    DataWidth:0x1    // Indicates the current state of the pcie_rst_n control which is driven by the PCIE CORE. Active low control.
+#define MISCS_REG_ECO_RESERVED                                                                               0x0097b4UL //Access:RW   DataWidth:0x20   // Eco reserved. Global register. [31:30] - used to programm loopback into Emulation (3\|2\|1\|0 (Enable loopback within the same port\|Enable loopback between ports (0 and 1, 2 and 3) of different engines\|Enable loopback between ports (0 and 2, 1 and 3) of the same engine\|Disable loopback)).
+#define MISCS_REG_MCP_ROM_TM                                                                                 0x0097b8UL //Access:RW   DataWidth:0x20   // Mcp_rom_tm
+#define MISCS_REG_AVS_OTP_SRAM_CTRL_BB                                                                       0x0097bcUL //Access:RW   DataWidth:0x9    // [31:9]  Reserved [8]     OTP_AVS_SRAM_MON_VALID [7:6]   OTP_AVS_SRAM_MON_N_PROCESS [5:4]   OTP_AVS_SRAM_MON_P_PROCESS [3:0]   OTP_ADJUST_VOLTAGE
+#define MISCS_REG_AVS_OTP_CTRL_VMAIN_BB                                                                      0x0097c0UL //Access:RW   DataWidth:0xf    // [31:15]  Reserved [14:12] OTP_VTRAP_TRIM_CODE: BG_adj [11:9]  OTP_VTRAP_TRIM_CODE: MAX0_adj [8:6]   OTP_VTRAP_TRIM_CODE: MIN1_adj [5:2]   OTP_VTRAP_TRIM_CODE: MIN0_adj [1]     OTP_VTRAP_ENABLE [0]     OTP_AVS_DISABLE
+#define MISCS_REG_AVS_OTP_CTRL_VMGMT_BB                                                                      0x0097c4UL //Access:RW   DataWidth:0xf    // [31:15]  Reserved [14:12] OTP_VTRAP_TRIM_CODE: BG_adj [11:9]  OTP_VTRAP_TRIM_CODE: MAX0_adj [8:6]   OTP_VTRAP_TRIM_CODE: MIN1_adj [5:2]   OTP_VTRAP_TRIM_CODE: MIN0_adj [1]     OTP_VTRAP_ENABLE [0]     OTP_AVS_DISABLE
+#define MISCS_REG_AVS_TOP_ADDR_BB                                                                            0x0097c8UL //Access:RW   DataWidth:0x11   // Indirect address.  Used to addrerss a register in avs_top.
+#define MISCS_REG_AVS_TOP_DATA_BB                                                                            0x0097ccUL //Access:RW   DataWidth:0x20   // Indirect data. Reading from this fetches data from top_addr.                          Writing stores data to top_addr.
+#define MISCS_REG_AVS_PVTMON_DACCODE_BB                                                                      0x0097d0UL //Access:RW   DataWidth:0x16   // [31:22] Reserved [21]    VMgmt DAC Over-ride: When set, over-ride DAC code from AVS monitor with on from this register [20:11] VMgmt DAC Codeword [10]    VMain DAC Over-ride: When set, over-ride DAC code from AVS monitor with on from this register [9:0]   VMain DAC Codeword
+#define MISCS_REG_OPTE_EMPTY_STATUS_BB                                                                       0x0097d4UL //Access:R    DataWidth:0x1c   // Packet available and FIFO empty status signals: [27:11] - Per-TC packet available status; [10] -  STORM FIFO; [9] - BTB SOP FIFO for engine 0; [8] - BTB SOP FIFO for engine 1; [7] - BTB IF0 FIFO for engine 0; [6] - BTB IF0 FIFO for engine 1; [5] - BTB IF1 FIFO for engine 0; [4] - BTB IF1 FIFO for engine 1; [3] - DBG FIFO for engine 0; [2] - DBG FIFO for engine 1; [1] - DORQ FIFO for engine 0; [0] - DORQ FIFO for engine 1;
+#define MISCS_REG_OPTE_FULL_STATUS_BB                                                                        0x0097d8UL //Access:R    DataWidth:0xc    // FIFO full status signals: [11] -  STORM FIFO almost full; [10] -  STORM FIFO full; [9] -  BTB SOP FIFO full for engine 0; [8] -  BTB SOP FIFO full for engine 1; [7] -  BTB IF0 FIFO full for engine 0; [6] -  BTB IF0 FIFO full for engine 1; [5] -  BTB IF1 FIFO full for engine 0; [4] -  BTB IF1 FIFO full for engine 1; [3] -  DBG FIFO full for engine 0; [2] -  DBG FIFO full for engine 1; [1] -  DORQ FIFO full for engine 0; [0] -  DORQ FIFO full for engine 1;
+#define MISCS_REG_OPTE_STATS_VECTOR_BB                                                                       0x0097dcUL //Access:R    DataWidth:0x8    // Signals for statistics counters, one bit for each statistics. [7] -  Received packet from BTB IF0 of engine 0; [6] -  Received packet from BTB IF0 of engine 1; [5] -  Received packet from BTB IF1 of engine 0; [4] -  Received packet from BTB IF1 of engine 1; [3] -  Sent packet to BRB IF0 of engine 0; [2] -  Sent packet to BRB IF0 of engine 1; [1] -  Sent packet to BRB IF1 of engine 0; [0] -  Sent packet to BRB IF1 of engine 1;
+#define MISCS_REG_OPTE_CTRL_BB                                                                               0x0097e0UL //Access:RW   DataWidth:0x8    // Opte Control configuration. [7:4] -  storm_init_crd: Credits for the output STORM Packet interface. [3:2] -  storm_pkt_dst: Select the destination engine for STORM packets. Set bit 2 to send STORM packets to engine 0. Set bit 3 to send STORM packets to engine 1. Set both bits to send STORM packets to both engines.  At least one destination has to be selected at any given time. [1:0] -  pxp_msg_dst: Select the destination engine for PXP messages. Set bit 0 to send PXP messages to engine 0. Set bit 1 to send PXP messages to engine 1. Set both bits to send PXP messages to both engines.  At least one destination has to be selected at any given time.
+#define MISCS_REG_OPTE_ALMFULL_THR_BB                                                                        0x0097e4UL //Access:RW   DataWidth:0x1e   // OPTE Almost-full Threshold. [29:25] -  Btb_if0_fifo_almfull_thr: Almost-full threshold for BTB main traffic FIFO. [24:20] -  Btb_if1_fifo_almfull_thr: Almost-full threshold for BTB LB traffic FIFO. [19:15] -  Storm_fifo_almfull_thr: Almost-full threshold for STORM FIFO. While this threshold is met or exceeded, OPTE stops returning credits to NIG since OPTE has to be able to honor the credits that NIG has for the STORM Packet interface.  Note that the actual assertion of the almost full flag is 1-3 entries more than the configured threshold. [14:5] -  reserved. [4:0] - Dbg_fifo_almfull_thr: Almost-full threshold for Debug FIFO.
+#define MISCS_REG_AVS_CLOCK_OBSERVE_BB                                                                       0x0097ecUL //Access:RW   DataWidth:0x6    // [31:6] Reserved [5]    Divide enable [4]    Enable [3:0]  Control
+#define MISCS_REG_AVS_TP_OUT_CTRL_BB                                                                         0x0097f0UL //Access:RW   DataWidth:0x3    // [31:3] Reserved [2]    Enable [1:0]  Select
+#define MISCS_REG_AVS_TP_IN_BB                                                                               0x0097f4UL //Access:RW   DataWidth:0x20   // [31:0] Data
+#define MISCS_REG_AVS_TP_OUT_BB                                                                              0x0097f8UL //Access:R    DataWidth:0x20   // [31:0] Data
+#define DBU_REG_CMD                                                                                          0x00a000UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define DBU_REG_CMD_ENABLE                                                                                 (0x1<<0) // This bit will always read '1', as it is not possible to disable the dbu block.
+  #define DBU_REG_CMD_ENABLE_SHIFT                                                                           0
+  #define DBU_REG_CMD_RX_ERROR                                                                               (0x1<<1) // This bit will read '1' if a byte has been received with a framing error. It will continue to read as a '1' until the command register is written with a '1' in this bit position.
+  #define DBU_REG_CMD_RX_ERROR_SHIFT                                                                         1
+  #define DBU_REG_CMD_RX_OVERFLOW                                                                            (0x1<<2) // This bit will read '1' of a receive overflow has occurred. It will continue to read as a '1' until the command register is written with a '1' in this bit position.
+  #define DBU_REG_CMD_RX_OVERFLOW_SHIFT                                                                      2
+#define DBU_REG_STATUS                                                                                       0x00a004UL //Access:R    DataWidth:0x2    // Multi Field Register.
+  #define DBU_REG_STATUS_RXDATA_VALID                                                                        (0x1<<0) // This bit will read '1' if there is a valid byte to read in dbu_rxdata. Once dbu_rxdata is read, this bit will automatically clear.
+  #define DBU_REG_STATUS_RXDATA_VALID_SHIFT                                                                  0
+  #define DBU_REG_STATUS_TXDATA_OCCUPIED                                                                     (0x1<<1) // This bit will read '1' if there is data pending to be transmitted in the txdata register. The bit will automatically clear when the txdata register is emptied.
+  #define DBU_REG_STATUS_TXDATA_OCCUPIED_SHIFT                                                               1
+#define DBU_REG_CONFIG                                                                                       0x00a008UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define DBU_REG_CONFIG_TIMING_OVERRIDE                                                                     (0x1<<0) // When this bit is set, the UART timing will be determined by the values in the dbu_timing register. When the bit is clear, the UART timing will be determined by the timing_select inputs to the block.
+  #define DBU_REG_CONFIG_TIMING_OVERRIDE_SHIFT                                                               0
+  #define DBU_REG_CONFIG_DEBUGSM_ENABLE                                                                      (0x1<<1) // When this bit is set, the debug state machine shall respond to received characters by performing GRC master transactions and returning received data.
+  #define DBU_REG_CONFIG_DEBUGSM_ENABLE_SHIFT                                                                1
+  #define DBU_REG_CONFIG_CRLF_ENABLE                                                                         (0x1<<2) // When this bit is set, all line feeds shall be preceded by a carriage return. Note that this bit has no impact on carriage returns transmitted by a GRC master via the txdata register.
+  #define DBU_REG_CONFIG_CRLF_ENABLE_SHIFT                                                                   2
+#define DBU_REG_TIMING                                                                                       0x00a00cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define DBU_REG_TIMING_FB_SMPL_OFFSET                                                                      (0xffff<<0) // These bits set the number of core_clock cycles after the falling edge of the rx_data pin that the start bit should be sampled. The default value of 0x6C results in 115200 baud operation with CK25 at 25MHz. Baud Rate 2400     : 0x1458 Baud Rate 4800     : 0x0A2C Baud Rate 9600     : 0x0516 Baud Rate 19200    : 0x028B Baud Rate 38400    : 0x0145 Baud Rate 57600    : 0x00D9 Baud Rate 115200   : 0x006c Baud Rate 230400   : 0x0036 Baud Rate 460800   : 0x001B
+  #define DBU_REG_TIMING_FB_SMPL_OFFSET_SHIFT                                                                0
+  #define DBU_REG_TIMING_BIT_INTERVAL                                                                        (0xffff<<16) // These bits set the number of core_clock cycles in between bits for both rx and tx. The default value of 0xD9 results in 115200 baud operation with CK25 at 25MHz. Baud Rate 2400     : 0x28B0 Baud Rate 4800     : 0x1458 Baud Rate 9600     : 0x0A2C Baud Rate 19200    : 0x0516 Baud Rate 38400    : 0x028B Baud Rate 57600    : 0x0145 Baud Rate 115200   : 0x00D9 Baud Rate 230400   : 0x006c Baud Rate 460800   : 0x0036
+  #define DBU_REG_TIMING_BIT_INTERVAL_SHIFT                                                                  16
+#define DBU_REG_RXDATA                                                                                       0x00a010UL //Access:R    DataWidth:0x8    // This bit indicates that the data currently in bits 7:0 of this register was received in error. This bit is valid only if rx_valid is set in the status register.
+#define DBU_REG_TXDATA                                                                                       0x00a014UL //Access:RW   DataWidth:0x8    // This register can be written to transmit a single byte of data on the serial interface. Firmware should poll the txdata_occupied bit in the status register before writing this register to make sure that a previously written byte has been transmitted. This register will read back the last txdata byte that was written.
+#define DBU_REG_VFID_CFG                                                                                     0x00a018UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define DBU_REG_VFID_CFG_VFID_VALUE                                                                        (0xff<<0) // Set the VF for which the registers need to be accessed
+  #define DBU_REG_VFID_CFG_VFID_VALUE_SHIFT                                                                  0
+  #define DBU_REG_VFID_CFG_PORT_VALUE                                                                        (0xff<<8) // Set the Port for which the registers need to be accessed
+  #define DBU_REG_VFID_CFG_PORT_VALUE_SHIFT                                                                  8
+  #define DBU_REG_VFID_CFG_VFID_VALID                                                                        (0x1<<16) // The vfid_value bits are valid only if this bit is set. If this bit is cleared, PF registers will be accessed
+  #define DBU_REG_VFID_CFG_VFID_VALID_SHIFT                                                                  16
+  #define DBU_REG_VFID_CFG_PATHID                                                                            (0x1<<20) // Set the path ID if the access is forced as indicated by bit 31.
+  #define DBU_REG_VFID_CFG_PATHID_SHIFT                                                                      20
+  #define DBU_REG_VFID_CFG_PATH_FORCE                                                                        (0x1<<31) // When 0, the path selection is done by PFID[0]. When 1,  the path selection is done by the PATHID field in this register.
+  #define DBU_REG_VFID_CFG_PATH_FORCE_SHIFT                                                                  31
+#define DMAE_REG_INIT                                                                                        0x00c000UL //Access:RW   DataWidth:0x1    // Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
+#define DMAE_REG_PCI_IFEN                                                                                    0x00c040UL //Access:RW   DataWidth:0x1    // DMAE PCI Interface (Request;Read;Write) enable. If 0 - the acknowledge input is disregarded; valid is deasserted; full is asserted; all other signals are treated as usual; if 1 - normal activity.
+#define DMAE_REG_GRC_IFEN                                                                                    0x00c044UL //Access:RW   DataWidth:0x1    // DMAE GRC Interface (Target;Master) enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
+#define DMAE_REG_GO_C0                                                                                       0x00c048UL //Access:RW   DataWidth:0x1    // Command 0 go.
+#define DMAE_REG_GO_C1                                                                                       0x00c04cUL //Access:RW   DataWidth:0x1    // Command 1 go.
+#define DMAE_REG_GO_C2                                                                                       0x00c050UL //Access:RW   DataWidth:0x1    // Command 2 go.
+#define DMAE_REG_GO_C3                                                                                       0x00c054UL //Access:RW   DataWidth:0x1    // Command 3 go.
+#define DMAE_REG_GO_C4                                                                                       0x00c058UL //Access:RW   DataWidth:0x1    // Command 4 go.
+#define DMAE_REG_GO_C5                                                                                       0x00c05cUL //Access:RW   DataWidth:0x1    // Command 5 go.
+#define DMAE_REG_GO_C6                                                                                       0x00c060UL //Access:RW   DataWidth:0x1    // Command 6 go.
+#define DMAE_REG_GO_C7                                                                                       0x00c064UL //Access:RW   DataWidth:0x1    // Command 7 go.
+#define DMAE_REG_GO_C8                                                                                       0x00c068UL //Access:RW   DataWidth:0x1    // Command 8 go.
+#define DMAE_REG_GO_C9                                                                                       0x00c06cUL //Access:RW   DataWidth:0x1    // Command 9 go.
+#define DMAE_REG_GO_C10                                                                                      0x00c070UL //Access:RW   DataWidth:0x1    // Command 10 go.
+#define DMAE_REG_GO_C11                                                                                      0x00c074UL //Access:RW   DataWidth:0x1    // Command 11 go.
+#define DMAE_REG_GO_C12                                                                                      0x00c078UL //Access:RW   DataWidth:0x1    // Command 12 go.
+#define DMAE_REG_GO_C13                                                                                      0x00c07cUL //Access:RW   DataWidth:0x1    // Command 13 go.
+#define DMAE_REG_GO_C14                                                                                      0x00c080UL //Access:RW   DataWidth:0x1    // Command 14 go.
+#define DMAE_REG_GO_C15                                                                                      0x00c084UL //Access:RW   DataWidth:0x1    // Command 15 go.
+#define DMAE_REG_GO_C16                                                                                      0x00c088UL //Access:RW   DataWidth:0x1    // Command 16 go.
+#define DMAE_REG_GO_C17                                                                                      0x00c08cUL //Access:RW   DataWidth:0x1    // Command 17 go.
+#define DMAE_REG_GO_C18                                                                                      0x00c090UL //Access:RW   DataWidth:0x1    // Command 18 go.
+#define DMAE_REG_GO_C19                                                                                      0x00c094UL //Access:RW   DataWidth:0x1    // Command 19 go.
+#define DMAE_REG_GO_C20                                                                                      0x00c098UL //Access:RW   DataWidth:0x1    // Command 20 go.
+#define DMAE_REG_GO_C21                                                                                      0x00c09cUL //Access:RW   DataWidth:0x1    // Command 21 go.
+#define DMAE_REG_GO_C22                                                                                      0x00c0a0UL //Access:RW   DataWidth:0x1    // Command 22 go.
+#define DMAE_REG_GO_C23                                                                                      0x00c0a4UL //Access:RW   DataWidth:0x1    // Command 23 go.
+#define DMAE_REG_GO_C24                                                                                      0x00c0a8UL //Access:RW   DataWidth:0x1    // Command 24 go.
+#define DMAE_REG_GO_C25                                                                                      0x00c0acUL //Access:RW   DataWidth:0x1    // Command 25 go.
+#define DMAE_REG_GO_C26                                                                                      0x00c0b0UL //Access:RW   DataWidth:0x1    // Command 26 go.
+#define DMAE_REG_GO_C27                                                                                      0x00c0b4UL //Access:RW   DataWidth:0x1    // Command 27 go.
+#define DMAE_REG_GO_C28                                                                                      0x00c0b8UL //Access:RW   DataWidth:0x1    // Command 28 go.
+#define DMAE_REG_GO_C29                                                                                      0x00c0bcUL //Access:RW   DataWidth:0x1    // Command 29 go.
+#define DMAE_REG_GO_C30                                                                                      0x00c0c0UL //Access:RW   DataWidth:0x1    // Command 30 go.
+#define DMAE_REG_GO_C31                                                                                      0x00c0c4UL //Access:RW   DataWidth:0x1    // Command 31 go.
+#define DMAE_REG_INT_STS                                                                                     0x00c180UL //Access:R    DataWidth:0x2    // Multi Field Register.
+  #define DMAE_REG_INT_STS_ADDRESS_ERROR                                                                     (0x1<<0) // Signals an unknown address to the rf module.
+  #define DMAE_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                               0
+  #define DMAE_REG_INT_STS_PCI_RD_BUF_ERR                                                                    (0x1<<1) // PCI read buffer error.
+  #define DMAE_REG_INT_STS_PCI_RD_BUF_ERR_SHIFT                                                              1
+#define DMAE_REG_INT_MASK                                                                                    0x00c184UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define DMAE_REG_INT_MASK_ADDRESS_ERROR                                                                    (0x1<<0) // This bit masks, when set, the Interrupt bit: DMAE_REG_INT_STS.ADDRESS_ERROR .
+  #define DMAE_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                              0
+  #define DMAE_REG_INT_MASK_PCI_RD_BUF_ERR                                                                   (0x1<<1) // This bit masks, when set, the Interrupt bit: DMAE_REG_INT_STS.PCI_RD_BUF_ERR .
+  #define DMAE_REG_INT_MASK_PCI_RD_BUF_ERR_SHIFT                                                             1
+#define DMAE_REG_INT_STS_WR                                                                                  0x00c188UL //Access:WR   DataWidth:0x2    // Multi Field Register.
+  #define DMAE_REG_INT_STS_WR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define DMAE_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                            0
+  #define DMAE_REG_INT_STS_WR_PCI_RD_BUF_ERR                                                                 (0x1<<1) // PCI read buffer error.
+  #define DMAE_REG_INT_STS_WR_PCI_RD_BUF_ERR_SHIFT                                                           1
+#define DMAE_REG_INT_STS_CLR                                                                                 0x00c18cUL //Access:RC   DataWidth:0x2    // Multi Field Register.
+  #define DMAE_REG_INT_STS_CLR_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define DMAE_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                           0
+  #define DMAE_REG_INT_STS_CLR_PCI_RD_BUF_ERR                                                                (0x1<<1) // PCI read buffer error.
+  #define DMAE_REG_INT_STS_CLR_PCI_RD_BUF_ERR_SHIFT                                                          1
+#define DMAE_REG_PRTY_MASK_H_0_BB_K2                                                                         0x00c204UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define DMAE_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                     (0x1<<0) // This bit masks, when set, the Parity bit: DMAE_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define DMAE_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                               0
+  #define DMAE_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                     (0x1<<1) // This bit masks, when set, the Parity bit: DMAE_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define DMAE_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                               1
+  #define DMAE_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                     (0x1<<2) // This bit masks, when set, the Parity bit: DMAE_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define DMAE_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                               2
+#define DMAE_REG_MEM_ECC_EVENTS_BB_K2                                                                        0x00c210UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define DMAE_REG_PXP_REQ_INIT_CRD                                                                            0x00c400UL //Access:RW   DataWidth:0x4    // DMAE- PCI Request Interface initial credit. Write writes the initial value to the credit counter; related to the address. Read returns the current value of the counter.
+#define DMAE_REG_RLXD_ORDR                                                                                   0x00c404UL //Access:RW   DataWidth:0x1    // Relaxed ordering. 0-strict PCI ordering is used;1-PCI-X relaxed ordering is enabled.
+#define DMAE_REG_NO_SNOOP                                                                                    0x00c408UL //Access:RW   DataWidth:0x1    // 0-PCI type cache snoop protection is required;1-system isn't required to cause processor cache snoop for coherency.
+#define DMAE_REG_CRC16I_INIT                                                                                 0x00c40cUL //Access:RW   DataWidth:0x1    // If 0 - the CRC-16 initial value is all zeroes; if 1 - the CRC-16 initial value is all ones.
+#define DMAE_REG_CRC16_BSWAP                                                                                 0x00c410UL //Access:RW   DataWidth:0x1    // If 0 - the CRC-16 final calculation result isn't byte swapped; if 1 - the CRC-16 final calculation result is byte swapped (byte [7:0] goes to location [31:24];etc).
+#define DMAE_REG_CRC16C_INIT                                                                                 0x00c414UL //Access:RW   DataWidth:0x1    // If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c initial value is all ones.
+#define DMAE_REG_CRC16T10_INIT                                                                               0x00c418UL //Access:RW   DataWidth:0x1    // If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the CRC-16 T10 initial value is all ones.
+#define DMAE_REG_CRC32I_INIT                                                                                 0x00c41cUL //Access:RW   DataWidth:0x1    // If 0 - the CRC-32 initial value is all zeroes; if 1 - the CRC-32 initial value is all ones.
+#define DMAE_REG_CRC32I_BSWAP                                                                                0x00c420UL //Access:RW   DataWidth:0x1    // If 0 - the CRC-32 final calculation result isn't byte swapped; if 1 - the CRC-32 final calculation result is byte swapped (byte [7:0] goes to location [31:24];etc).
+#define DMAE_REG_CRC32C_INIT                                                                                 0x00c424UL //Access:RW   DataWidth:0x1    // If 0 - the CRC-32c initial value is all zeroes; if 1 - the CRC-32c initial value is all ones.
+#define DMAE_REG_CRC32C_BSWAP                                                                                0x00c428UL //Access:RW   DataWidth:0x1    // If 0 - the CRC-32c final calculation result isn't byte swapped; if 1 - the CRC-32c final calculation result is byte swapped (byte [7:0] goes to location [31:24];etc).
+#define DMAE_REG_CHKSUM0_FIX                                                                                 0x00c42cUL //Access:RW   DataWidth:0x1    // If 0 - the final checksum equal 0 won't be changed;if 1 - the final checksum equal 0 will be fixed to all ones.
+#define DMAE_REG_WR_ATC_FLAGS                                                                                0x00c430UL //Access:RW   DataWidth:0x3    // Write request ATC Flags[1:0]: 00 - Do nothing; 01 - Search only; 10 - Search & Cache; 11 - Search & Release; ATC Flags[2]:0 - Low Priority;  - High Priority.
+#define DMAE_REG_RD_ATC_FLAGS                                                                                0x00c434UL //Access:RW   DataWidth:0x3    // Read request ATC Flags[1:0]: 00 - Do nothing; 01 - Search only; 10 - Search & Cache; 11 - Search & Release; ATC Flags[2]:0 - Low Priority;  - High Priority.
+#define DMAE_REG_PCI_ERR_DISCARD_EN                                                                          0x00c438UL //Access:RW   DataWidth:0x1    // When set discards 1- or 2-Dword PCI transaction read in case there is PCI error.
+#define DMAE_REG_PCI_ERR_DISCARD_ADDR                                                                        0x00c43cUL //Access:RW   DataWidth:0x14   // GRC address in case 1- or 2-Dword PCI transaction is discardd due to PCI error and dmae.pci_err_discard set.
+#define DMAE_REG_TPH_FLAGS                                                                                   0x00c440UL //Access:RW   DataWidth:0xc    // Multi Field Register.
+  #define DMAE_REG_TPH_FLAGS_TPH_STR_TAG_INDX                                                                (0x1ff<<0) // Steering Tag Index (value of 0x1FF means no steering tag in which case steering tag will be set to 0).
+  #define DMAE_REG_TPH_FLAGS_TPH_STR_TAG_INDX_SHIFT                                                          0
+  #define DMAE_REG_TPH_FLAGS_TPH_ST_HINT                                                                     (0x3<<9) // ST hint. 00 - Bidirectional shared data structure; 01 - Device writes/reads then device reads/writes soon; 10 - Device writes then host reads soon or Device reads data that the Host is believed to have recently written; 11 - like 10 but with higher priority.
+  #define DMAE_REG_TPH_FLAGS_TPH_ST_HINT_SHIFT                                                               9
+  #define DMAE_REG_TPH_FLAGS_TPH_VALID                                                                       (0x1<<11) // TPH valid.
+  #define DMAE_REG_TPH_FLAGS_TPH_VALID_SHIFT                                                                 11
+#define DMAE_REG_ECO_RESERVED                                                                                0x00c444UL //Access:RW   DataWidth:0x8    // Chicken bits.
+#define DMAE_REG_GRC_PRIVILEGE_LEVEL                                                                         0x00c448UL //Access:RW   DataWidth:0x2    // GRC privilege level: generates PRV field in FID: 0 - VN Virtualized NIC (Used for VF access); 1 - PDA Physical Device Assignment (Assigned to VM-s); 2 - HV HyperVisor (Assigned to HV); 3 - UA Un-restricted Access;
+#define DMAE_REG_FSM_ST                                                                                      0x00c44cUL //Access:R    DataWidth:0x4    // DMAE FSM current state.
+#define DMAE_REG_MEMCTRL_WR_RD_N_BB                                                                          0x00c500UL //Access:RW   DataWidth:0x1    // wr/rd indication to CPU BIST
+#define DMAE_REG_MEMCTRL_CMD_BB                                                                              0x00c504UL //Access:RW   DataWidth:0x8    // command to CPU BIST
+#define DMAE_REG_MEMCTRL_ADDRESS_BB                                                                          0x00c508UL //Access:RW   DataWidth:0x8    // address to CPU BIST
+#define DMAE_REG_MEMCTRL_STATUS                                                                              0x00c50cUL //Access:R    DataWidth:0x20   // status from CPU BIST
+#define DMAE_REG_DBG_SELECT                                                                                  0x00c510UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define DMAE_REG_DBG_DWORD_ENABLE                                                                            0x00c514UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define DMAE_REG_DBG_SHIFT                                                                                   0x00c518UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define DMAE_REG_DBG_FORCE_VALID                                                                             0x00c51cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define DMAE_REG_DBG_FORCE_FRAME                                                                             0x00c520UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define DMAE_REG_DBG_OUT_DATA                                                                                0x00c540UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define DMAE_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define DMAE_REG_DBG_OUT_VALID                                                                               0x00c560UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define DMAE_REG_DBG_OUT_FRAME                                                                               0x00c564UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define DMAE_REG_CMD_MEM                                                                                     0x00c800UL //Access:RW   DataWidth:0x20   // Commands memory. The address to command X; row Y is to calculated as 14*X+Y.
+#define DMAE_REG_CMD_MEM_SIZE                                                                                448
+#define DBG_REG_CLIENT_ENABLE                                                                                0x010004UL //Access:RW   DataWidth:0x13   // Enable to client interfaces: Bits 0- RBCN; 1- RBCP; 2-RBCR; 3- RBCT; 4- RBCU; 5- RBCF; 6- RBCX; 7- RBCS; 8-RBCH; 9-RBCZ; 10 - other engine input (obsolete); 11-Timestamp client; 12-CPU client; 13-RBCY; 14-RBCQ; 15-RBCM; 16-RBCB; 17-RBCW; 18-RBCV;
+#define DBG_REG_OTHER_CLIENT_ENABLE_BB_K2                                                                    0x010008UL //Access:RW   DataWidth:0x13   // Enable to client interfaces for output to other engine: Bits 0- RBCN; 1- RBCP; 2-RBCR; 3- RBCT; 4- RBCU; 5- RBCF; 6- RBCX; 7- RBCS; 8-RBCH; 9-RBCZ; 10 - other engine input (bit 10 should be constnantly 0); 11-Timestamp client; 12-CPU client; 13-RBCY; 14-RBCQ; 15-RBCM; 16-RBCB; 17-RBCW; 18-RBCV;
+#define DBG_REG_OUTPUT_ENABLE                                                                                0x01000cUL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define DBG_REG_OUTPUT_ENABLE_PCI_REQ_ENABLE                                                               (0x1<<0) // Debug only:  This bit is an enable to PCI output request interface; This bit should be enabled/disabled together along with DBG_REGISTERS_OUTPUT_ENABLE.PCI_DATA_ENABLE . When DBG_REGISTERS_OUTPUT_ENABLE.NIG_ENABLE is enabled this register must be disabled.
+  #define DBG_REG_OUTPUT_ENABLE_PCI_REQ_ENABLE_SHIFT                                                         0
+  #define DBG_REG_OUTPUT_ENABLE_PCI_DATA_ENABLE                                                              (0x1<<1) // Debug only:  This bit is an enable to PCI output data interface; This bit should be enabled/disabled together along with DBG_REGISTERS_OUTPUT_ENABLE.PCI_REQ_ENABLE . When DBG_REGISTERS_OUTPUT_ENABLE.NIG_ENABLE is enabled this register must be disabled.
+  #define DBG_REG_OUTPUT_ENABLE_PCI_DATA_ENABLE_SHIFT                                                        1
+  #define DBG_REG_OUTPUT_ENABLE_NIG_ENABLE                                                                   (0x1<<2) // Debug only:  This bit is an enable to NIG output data interface. When DBG_REGISTERS_OUTPUT_ENABLE.PCI_REQ_ENABLE and DBG_REGISTERS_OUTPUT_ENABLE.PCI_DATA_ENABLE are enabled this bit should be disabled.
+  #define DBG_REG_OUTPUT_ENABLE_NIG_ENABLE_SHIFT                                                             2
+#define DBG_REG_OTHER_ENGINE_MODE_BB_K2                                                                      0x010010UL //Access:RW   DataWidth:0x3    // Working mode with the other DBG instance engine as follows: 0-NONE; 1-DoubleBwTx (DoubleBw the TX side); 2-DoubleBwRx (DoubleBw the RX side); 3-CrossEngineTx (CrossEngineTx the TX side);4-CrossEngineRx (CrossEngineRx the RX side).
+#define DBG_REG_CALENDAR_SLOT0                                                                               0x010014UL //Access:RW   DataWidth:0x3    // Debug only: These bits are a client index for slot 0 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.
+#define DBG_REG_CALENDAR_SLOT1                                                                               0x010018UL //Access:RW   DataWidth:0x3    // Debug only: These bits are a client index for slot 1 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.
+#define DBG_REG_CALENDAR_SLOT2                                                                               0x01001cUL //Access:RW   DataWidth:0x3    // Debug only: These bits are a client index for slot 2 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.
+#define DBG_REG_CALENDAR_SLOT3                                                                               0x010020UL //Access:RW   DataWidth:0x3    // Debug only: These bits are a client index for slot 3 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.
+#define DBG_REG_CALENDAR_SLOT4                                                                               0x010024UL //Access:RW   DataWidth:0x3    // Debug only: These bits are a client index for slot 4 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.
+#define DBG_REG_CALENDAR_SLOT5                                                                               0x010028UL //Access:RW   DataWidth:0x3    // Debug only: These bits are a client index for slot 5 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.
+#define DBG_REG_CALENDAR_SLOT6                                                                               0x01002cUL //Access:RW   DataWidth:0x3    // Debug only: These bits are a client index for slot 6 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.
+#define DBG_REG_CALENDAR_SLOT7                                                                               0x010030UL //Access:RW   DataWidth:0x3    // Debug only: These bits are a client index for slot 7 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.
+#define DBG_REG_CALENDAR_SLOT8                                                                               0x010034UL //Access:RW   DataWidth:0x3    // Debug only: These bits are a client index for slot 8 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.
+#define DBG_REG_CALENDAR_SLOT9                                                                               0x010038UL //Access:RW   DataWidth:0x3    // Debug only: These bits are a client index for slot 9 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.
+#define DBG_REG_CALENDAR_SLOT10                                                                              0x01003cUL //Access:RW   DataWidth:0x3    // Debug only: These bits are a client index for slot 10 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.
+#define DBG_REG_CALENDAR_SLOT11                                                                              0x010040UL //Access:RW   DataWidth:0x3    // Debug only: These bits are a client index for slot 11 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.
+#define DBG_REG_CALENDAR_SLOT12                                                                              0x010044UL //Access:RW   DataWidth:0x3    // Debug only: These bits are a client index for slot 12 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.
+#define DBG_REG_CALENDAR_SLOT13                                                                              0x010048UL //Access:RW   DataWidth:0x3    // Debug only: These bits are a client index for slot 13 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.
+#define DBG_REG_CALENDAR_SLOT14                                                                              0x01004cUL //Access:RW   DataWidth:0x3    // Debug only: These bits are a client index for slot 14 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.
+#define DBG_REG_CALENDAR_SLOT15                                                                              0x010050UL //Access:RW   DataWidth:0x3    // Debug only: These bits are a client index for slot 15 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.
+#define DBG_REG_CALENDAR_PACE                                                                                0x010054UL //Access:RW   DataWidth:0x8    // Debug only: This bit indicates the calendar pacing which is the number of cycles the calendar stays on the same slot before moving to the next slot to support lower rates (During the number of cycles configured in the DBG_REGISTERS_CALENDAR_PACE only one cycle can be valid).
+#define DBG_REG_FRAMING_MODE                                                                                 0x010058UL //Access:RW   DataWidth:0x2    // Framing modes: 0 - 128b STORM (A and B) data is logged 1 - 64b STORM (A and B) data + 4 different (in general case) HW blocks are logged 2 - 32b STORM (A and B) data + 6 different (in general case) HW blocks are logged 3 - 8 different (in general case) HW blocks are logged
+#define DBG_REG_DEBUG_TARGET                                                                                 0x01005cUL //Access:RW   DataWidth:0x2    // Debug only:  These bits indicate the target of the debug data:  0 - internal buffer;  1 - NIG;   2 - PCI.
+#define DBG_REG_FULL_MODE                                                                                    0x010060UL //Access:RW   DataWidth:0x1    // Debug only: This bit indicates whether data will be wrapped (oldest data is thrown) or overflowed-one shot (newest data is thrown) as follows: (a) When DBG_REGISTERS_DEBUG_TARGET =0 (internal buffer): 1- wrap internal buffer; 0 - One Shot; b) When DBG_REGISTERS_DEBUG_TARGET =1 (NIG):  1 - constant send; 0 - One Shot; c) When DBG_REGISTERS_DEBUG_TARGET =2 (PXP): 1 - wrap host memory in PXP; 0 - One Shot;.
+#define DBG_REG_INT_STS                                                                                      0x010180UL //Access:R    DataWidth:0x1    // Multi Field Register.
+  #define DBG_REG_INT_STS_ADDRESS_ERROR                                                                      (0x1<<0) // Signals an unknown address to the rf module.
+  #define DBG_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                                0
+#define DBG_REG_INT_MASK                                                                                     0x010184UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define DBG_REG_INT_MASK_ADDRESS_ERROR                                                                     (0x1<<0) // This bit masks, when set, the Interrupt bit: DBG_REG_INT_STS.ADDRESS_ERROR .
+  #define DBG_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                               0
+#define DBG_REG_INT_STS_WR                                                                                   0x010188UL //Access:WR   DataWidth:0x1    // Multi Field Register.
+  #define DBG_REG_INT_STS_WR_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define DBG_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                             0
+#define DBG_REG_INT_STS_CLR                                                                                  0x01018cUL //Access:RC   DataWidth:0x1    // Multi Field Register.
+  #define DBG_REG_INT_STS_CLR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define DBG_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                            0
+#define DBG_REG_PRTY_MASK_H_0_BB_K2                                                                          0x010204UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define DBG_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                      (0x1<<0) // This bit masks, when set, the Parity bit: DBG_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define DBG_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                                0
+#define DBG_REG_MEM_ECC_EVENTS_BB_K2                                                                         0x010210UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define DBG_REG_INTR_BUFFER_RD_PTR                                                                           0x010400UL //Access:R    DataWidth:0x8    // Debug only: These bits indicate the value of the read pointer for the internal buffer; The read pointer describes the next address to be read from the internal buffer.
+#define DBG_REG_INTR_BUFFER_WR_PTR                                                                           0x010404UL //Access:R    DataWidth:0x8    // Debug only:  These bits indicate the value of the write pointer for the internal buffer; The write pointer describes the last address that was written to the internal buffer. An exception exists after reset when DBG_REGISTERS_INTR_BUFFER_WR_PTR is 0 until first data is written.
+#define DBG_REG_EXT_BUFFER_RD_PTR                                                                            0x010408UL //Access:WB_R DataWidth:0x40   // Debug only:   These bits indicate the value of the read pointer for the external pci buffer; relevant only when DBG_REGISTERS_DEBUG_TARGET =2 (PCI); The read pointer describes the next address to be read from the external buffer; WB Read Only (write request will not be acknowledged); (in bytes).
+#define DBG_REG_EXT_BUFFER_RD_PTR_SIZE                                                                       2
+#define DBG_REG_EXT_BUFFER_WR_PTR                                                                            0x010410UL //Access:WB_R DataWidth:0x40   // Debug only:  These bits indicate the value of the write pointer for the external pci buffer when DBG_REGISTERS_DEBUG_TARGET =2 (PCI). It describes the next address to write to the external buffer; TARGET_PACKET_SIZE chunks counter when DBG_REGISTERS_DEBUG_TARGET =1 (NIG) and DBG_REGISTERS_FULL_MODE =0 (one-shot); WB Read Only (write request will not be acknowledged);.
+#define DBG_REG_EXT_BUFFER_WR_PTR_SIZE                                                                       2
+#define DBG_REG_WRAP_ON_INT_BUFFER                                                                           0x010418UL //Access:R    DataWidth:0x1    // Debug only: This bit indicates wheter the internal buffer was wrapped (oldest data was thrown) Relevant only when DBG_REGISTERS_DEBUG_TARGET =0 (internal buffer).
+#define DBG_REG_WRAP_ON_EXT_BUFFER                                                                           0x01041cUL //Access:R    DataWidth:0x1    // Debug only:  This bit indicates wheter  indicates that external buffer was wrapped (oldest data was thrown); Relevant only when DBG_REGISTERS_DEBUG_TARGET =2 (PCI) & DBG_REGISTERS_FULL_MODE =1 (wrap);.
+#define DBG_REG_OVL_ON_INT_BUFFER                                                                            0x010420UL //Access:R    DataWidth:0x1    // Debug only:  This bit indicates that the internal buffer was overflowed (newest data was thrown); Not relevant if DBG_REGISTERS_DEBUG_TARGET =0 (internal buffer) & DBG_REGISTERS_FULL_MODE =1 (wrap);.
+#define DBG_REG_OVL_ON_EXT_BUFFER                                                                            0x010424UL //Access:R    DataWidth:0x1    // Debug only: This bit indicates that the external buffer was overflowed (newest data was thrown); Relevant only for (a) DBG_REGISTERS_DEBUG_TARGET =2 (PCI) & DBG_REGISTERS_FULL_MODE =0 (one shot); or  (b) DBG_REGISTERS_DEBUG_TARGET =1 (NIG) & DBG_REGISTERS_FULL_MODE =0 (one shot).
+#define DBG_REG_FULL_ON_INT_BUFFER                                                                           0x010428UL //Access:R    DataWidth:0x1    // Debug only:  This bit indicates that the internal buffer was filled.
+#define DBG_REG_FULL_ON_EXT_BUFFER                                                                           0x01042cUL //Access:R    DataWidth:0x1    // Debug only: This bit indicates that the external buffer was filled; Relevant only when DBG_REGISTERS_FULL_MODE =0 (one shot).
+#define DBG_REG_PCI_EXT_BUFFER_STRT_ADDR_LSB                                                                 0x010430UL //Access:RW   DataWidth:0x20   // Debug only: LSB of external PCI buffer start address; MUST be configured BEFORE pci_req_credit is configured.
+#define DBG_REG_PCI_EXT_BUFFER_STRT_ADDR_MSB                                                                 0x010434UL //Access:RW   DataWidth:0x20   // Debug only: MSB of external PCI buffer start address; MUST be configured BEFORE pci_req_credit is configured.
+#define DBG_REG_PCI_EXT_BUFFER_SIZE                                                                          0x010438UL //Access:RW   DataWidth:0x18   // Debug only:  These bits indicate the value of the external PCI buffer size in target_packet_size chunks  (The reset value is for 128 Mbyte buffer).
+#define DBG_REG_NIG_DATA_LIMIT_SIZE                                                                          0x01043cUL //Access:RW   DataWidth:0x16   // Debug only: These bits indicate the max value of target_packet_size data chunks sent through the NIG (The reset value is for 4M chunks of target_packet_size data byte each); Relevant only when debug_target=1 (NIG) & full_mode=0 (one-shot).
+#define DBG_REG_PCI_REQ_CREDIT                                                                               0x010440UL //Access:RW   DataWidth:0x2    // Debug only:  These bits indicate the credit  for PCI request type 4 interface; MUST be configured AFTER pci_ext_buffer_strt_addr_lsb/msb are configured.
+#define DBG_REG_PCI_VQ_ID                                                                                    0x010444UL //Access:RW   DataWidth:0x5    // Debug only: This bit is a handle given to the PCI block to refer to this request.
+#define DBG_REG_CPU_DEBUG_DATA                                                                               0x010448UL //Access:RW   DataWidth:0x20   // Debug only:  These bits indicate debug data that arrives from the CPU client.
+#define DBG_REG_CPU_DEBUG_FRAME                                                                              0x01044cUL //Access:RW   DataWidth:0x1    // Debug only: This bit indicate the frame signal of the debug data that arrives from the CPU. Must be configured before cpu_debug_data is configured.
+#define DBG_REG_CPU_TIMEOUT                                                                                  0x010450UL //Access:RW   DataWidth:0x1    // Debug only: Timeout operation initiated by the CPU; prior to initiating a timeout event all inputs must be disabled; Timeout signal must stay high until all data was fully sent to nig or pci and the internal buffer is empty.
+#define DBG_REG_DBG_BLOCK_ON                                                                                 0x010454UL //Access:RW   DataWidth:0x1    // Debug only: This bit enables the operation of the debug block; This bit should be set upon completion of all required configuration for the dbg block and shouldn't be reset during all operational phase of the block;.
+#define DBG_REG_NO_GRANT_ON_FULL                                                                             0x010458UL //Access:RW   DataWidth:0x1    // Debug only: This bit indicate whether grant will be issued by the dbg block towards the storms in case the internal buffer is almost full as follows: (a) 1 -  no grants will be made to the storms when the internal buffer is almost full. When the buffer will be partialy freed (enough for a complete data chunk) then grant is resumed; b) 0 - grant is supplied every time the matching storms's slot is chosen disregarding the volume status of the internal buffer.
+#define DBG_REG_FULL_BUFFER_THR                                                                              0x01045cUL //Access:RW   DataWidth:0x9    // Debug only: These bits indicate the value of the internal buffer almost full threshold used for deciding when dbg_sem_buffer_full output should go high/low; holds the number of 512 bit free lines in the internal buffer under which the full would go high; not applicable when DBG_REGISTERS_DEBUG_TARGET =0 (internal buffer) and DBG_REGISTERS_FULL_MODE =1 (wrap). NOTE: When filter_enable > 0 then this register should be >= 12.
+#define DBG_REG_PCI_LOGIC_ADDR                                                                               0x010460UL //Access:RW   DataWidth:0x1    // Debug only:  This bit indicates logical/physical address in PCI request as follows:  (a) 1 - logical address; (b) 0 - physical address;.
+#define DBG_REG_IFMUX_SELECT_K2_E5                                                                           0x010464UL //Access:RW   DataWidth:0x3    // Debug only: Selects 32b of data, valid and frame from the input stream to internal buffer to be output to IFMUX interface. 0 - bits[31:0] 1 - bits[63:32] 2:6 - etc. 7 - bits[255:224]
+#define DBG_REG_CALENDAR_OUT_DATA                                                                            0x010480UL //Access:WB_R DataWidth:0x115  // Debug only: These bits indicate the value of the sop; data; frame and valid output of the calendar; The concatenation is done as follows: bits 255:0 - data; bits 259:256 - frame; bits 263:260 - valid; bits 275:264 - ID; bits 276 - SOP.
+#define DBG_REG_CALENDAR_OUT_DATA_SIZE                                                                       16
+#define DBG_REG_EXPECTED_PATTERN                                                                             0x0104c0UL //Access:WB   DataWidth:0x131  // Debug only:  For pattern recognition usage:  These bits represent the pattern to be compared with the vector {sop; id[31:0]; valid[7:0];frame[7:0]; data[255:0]}; This vector represent the debug data it's slot number and it's frame signals that are going to stored in the internal buffer; to allow recognize sop the following should be applied: trigger_enable=1 and filter_enable>0.NOTE: In order to take into consideration the SOP value set trigger_enable=1 and filter_enable>0
+#define DBG_REG_EXPECTED_PATTERN_SIZE                                                                        16
+#define DBG_REG_EXPECTED_PATTERN_BIT_MASK                                                                    0x010500UL //Access:WB   DataWidth:0x131  // Debug only: For pattern recognition usage: These bits represent a mask bit vector that refers to the DBG_REGISTERS_EXPECTED_PATTERN vector as follows:  (a) 1 - bit is masked. This bit won't be compared with the DBG_REGISTERS_EXPECTED_PATTERN referred bit;  (b) 0 - bit is enabled. This bit will be compared with the DBG_REGISTERS_EXPECTED_PATTERN reffered bit.
+#define DBG_REG_EXPECTED_PATTERN_BIT_MASK_SIZE                                                               16
+#define DBG_REG_PATTERN_RECOGNITION_DISABLE                                                                  0x010540UL //Access:RW   DataWidth:0x1    // Debug only: For pattern recognition usage: This bit indicates whether the pattern recognition feature is disabled/enabled as follows:   (a) 1 - disabled;  (b) 0 - enabled;.
+#define DBG_REG_PATTERN_RECOGNITION_STORAGE_MODE                                                             0x010544UL //Access:RW   DataWidth:0x1    // Debug only:  For pattern recognition usage: This bit indicates the trigger behavior of the pattern recognition feature as follows:  (a) 1 - stop debug data storgae when the expected pattern is initially recognized; (b) 0 - start debug data storage when the expected pattern is initially recognized. When pattern_recognition_filter=0 then this register must be 0
+#define DBG_REG_PATTERN_RECOGNITION_FILTER                                                                   0x010548UL //Access:RW   DataWidth:0x1    // Debug only: For pattern recognition usage:  This bit indicates whether data is continously stored in the dbg block until/from pattern recognition initial event; or stored only in cycles of a pattern recognition event occurence as follows: (a) 1 - enable continuously data storage after/before first occurence of pattern recognition;  (b) 0 - enable data storage only in cycles of a pttern recognition event occurence.
+#define DBG_REG_TRIGGER_ENABLE                                                                               0x01054cUL //Access:RW   DataWidth:0x1    // (a) 0 - trigger machine is off (all data will bypass the triggering machine);  dbg_sem_trgr_evnt may be asserted in this mode. (b) 1 - trigger machine is on; before AND/OR upon trigger_event assertion data will be recorded according to the configuration of the recording mode before/upon triggering event: rcrd_on_window_pre_trgr_evnt_mode  & rcrd_on_window_post_trgr_evnt_mode.
+#define DBG_REG_TRIGGER_INTERLEAVED_ENABLE                                                                   0x010550UL //Access:RW   DataWidth:0x1    // (a) 0 - triggering interleaved messages is disabled. (b) 1 - triggering interleaved messages is enabled; will be used for triggering on recorded handler messages. NOTE: (1) triggering is possible on one level depth of interleaved messages; i.e. if message B is interleaved within message A then it is ok; However if message C is interleaved within message B and message B is interleaved within message A this scenario is NOT supported. (2) when triggering interleaved messages is enabled, set trigger_enable=1 and filter_enable>0, and trigger_id_num not equal with filter_id_num (because filtering machine does not support interleaving)
+#define DBG_REG_TRIGGER_STATE_ID_0                                                                           0x010554UL //Access:RW   DataWidth:0x4    // Number of ID that should be triggered. For HW block only bits[2:0] are used. Bit[3] should be set to 0. For STORM bit[3] designates what STORM should be triggered (0 - STORM A; 1 - STORM B). Bits[2:0] designate STORM ID.
+#define DBG_REG_TRIGGER_STATE_ID_1                                                                           0x010558UL //Access:RW   DataWidth:0x4    // Number of ID that should be triggered. For HW block only bits[2:0] are used. Bit[3] should be set to 0. For STORM bit[3] designates what STORM should be triggered (0 - STORM A; 1 - STORM B). Bits[2:0] designate STORM ID.
+#define DBG_REG_TRIGGER_STATE_ID_2                                                                           0x01055cUL //Access:RW   DataWidth:0x4    // Number of ID that should be triggered. For HW block only bits[2:0] are used. Bit[3] should be set to 0. For STORM bit[3] designates what STORM should be triggered (0 - STORM A; 1 - STORM B). Bits[2:0] designate STORM ID.
+#define DBG_REG_TRIGGER_STATE_USE_BOTH_SETS_0                                                                0x010560UL //Access:RW   DataWidth:0x1    // (a) 1 - use both constraint set0 and constraint set1 in relevant state. (b) 0 - use only constraint set0 in relevant state.
+#define DBG_REG_TRIGGER_STATE_USE_BOTH_SETS_1                                                                0x010564UL //Access:RW   DataWidth:0x1    // (a) 1 - use both constraint set0 and constraint set1 in relevant state. (b) 0 - use only constraint set0 in relevant state.
+#define DBG_REG_TRIGGER_STATE_USE_BOTH_SETS_2                                                                0x010568UL //Access:RW   DataWidth:0x1    // (a) 1 - use both constraint set0 and constraint set1 in relevant state. (b) 0 - use only constraint set0 in relevant state.
+#define DBG_REG_TRIGGER_STATE_SET_NXT_STATE_0                                                                0x01056cUL //Access:RW   DataWidth:0x2    // Next state in the fsm triggering machine if the referred constraints set in the specified state are met.
+#define DBG_REG_TRIGGER_STATE_SET_NXT_STATE_1                                                                0x010570UL //Access:RW   DataWidth:0x2    // Next state in the fsm triggering machine if the referred constraints set in the specified state are met.
+#define DBG_REG_TRIGGER_STATE_SET_NXT_STATE_2                                                                0x010574UL //Access:RW   DataWidth:0x2    // Next state in the fsm triggering machine if the referred constraints set in the specified state are met.
+#define DBG_REG_TRIGGER_STATE_SET_NXT_STATE_3                                                                0x010578UL //Access:RW   DataWidth:0x2    // Next state in the fsm triggering machine if the referred constraints set in the specified state are met.
+#define DBG_REG_TRIGGER_STATE_SET_NXT_STATE_4                                                                0x01057cUL //Access:RW   DataWidth:0x2    // Next state in the fsm triggering machine if the referred constraints set in the specified state are met.
+#define DBG_REG_TRIGGER_STATE_SET_NXT_STATE_5                                                                0x010580UL //Access:RW   DataWidth:0x2    // Next state in the fsm triggering machine if the referred constraints set in the specified state are met.
+#define DBG_REG_TRIGGER_STATE_SET_COUNT_0                                                                    0x010584UL //Access:RW   DataWidth:0x10   // Number of times that the referred constraints set should be met prior to recognition (moving to next state). NOTE: value of 0 is NA.
+#define DBG_REG_TRIGGER_STATE_SET_COUNT_1                                                                    0x010588UL //Access:RW   DataWidth:0x10   // Number of times that the referred constraints set should be met prior to recognition (moving to next state). NOTE: value of 0 is NA.
+#define DBG_REG_TRIGGER_STATE_SET_COUNT_2                                                                    0x01058cUL //Access:RW   DataWidth:0x10   // Number of times that the referred constraints set should be met prior to recognition (moving to next state). NOTE: value of 0 is NA.
+#define DBG_REG_TRIGGER_STATE_SET_COUNT_3                                                                    0x010590UL //Access:RW   DataWidth:0x10   // Number of times that the referred constraints set should be met prior to recognition (moving to next state). NOTE: value of 0 is NA.
+#define DBG_REG_TRIGGER_STATE_SET_COUNT_4                                                                    0x010594UL //Access:RW   DataWidth:0x10   // Number of times that the referred constraints set should be met prior to recognition (moving to next state). NOTE: value of 0 is NA.
+#define DBG_REG_TRIGGER_STATE_SET_COUNT_5                                                                    0x010598UL //Access:RW   DataWidth:0x10   // Number of times that the referred constraints set should be met prior to recognition (moving to next state). NOTE: value of 0 is NA.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_0                                                               0x01059cUL //Access:RW   DataWidth:0x20   // The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_set_cnstr_offseti[2:0])].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_1                                                               0x0105a0UL //Access:RW   DataWidth:0x20   // The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_set_cnstr_offseti[2:0])].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_2                                                               0x0105a4UL //Access:RW   DataWidth:0x20   // The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_set_cnstr_offseti[2:0])].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_3                                                               0x0105a8UL //Access:RW   DataWidth:0x20   // The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_set_cnstr_offseti[2:0])].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_4                                                               0x0105acUL //Access:RW   DataWidth:0x20   // The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_set_cnstr_offseti[2:0])].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_5                                                               0x0105b0UL //Access:RW   DataWidth:0x20   // The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_set_cnstr_offseti[2:0])].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_6                                                               0x0105b4UL //Access:RW   DataWidth:0x20   // The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_set_cnstr_offseti[2:0])].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_7                                                               0x0105b8UL //Access:RW   DataWidth:0x20   // The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_set_cnstr_offseti[2:0])].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_8                                                               0x0105bcUL //Access:RW   DataWidth:0x20   // The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_set_cnstr_offseti[2:0])].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_9                                                               0x0105c0UL //Access:RW   DataWidth:0x20   // The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_set_cnstr_offseti[2:0])].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_10                                                              0x0105c4UL //Access:RW   DataWidth:0x20   // The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_set_cnstr_offseti[2:0])].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_11                                                              0x0105c8UL //Access:RW   DataWidth:0x20   // The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_set_cnstr_offseti[2:0])].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_12                                                              0x0105ccUL //Access:RW   DataWidth:0x20   // The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_set_cnstr_offseti[2:0])].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_13                                                              0x0105d0UL //Access:RW   DataWidth:0x20   // The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_set_cnstr_offseti[2:0])].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_14                                                              0x0105d4UL //Access:RW   DataWidth:0x20   // The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_set_cnstr_offseti[2:0])].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_15                                                              0x0105d8UL //Access:RW   DataWidth:0x20   // The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_set_cnstr_offseti[2:0])].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_16                                                              0x0105dcUL //Access:RW   DataWidth:0x20   // The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_set_cnstr_offseti[2:0])].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_17                                                              0x0105e0UL //Access:RW   DataWidth:0x20   // The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_set_cnstr_offseti[2:0])].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_18                                                              0x0105e4UL //Access:RW   DataWidth:0x20   // The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_set_cnstr_offseti[2:0])].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_19                                                              0x0105e8UL //Access:RW   DataWidth:0x20   // The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_set_cnstr_offseti[2:0])].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_20                                                              0x0105ecUL //Access:RW   DataWidth:0x20   // The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_set_cnstr_offseti[2:0])].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_21                                                              0x0105f0UL //Access:RW   DataWidth:0x20   // The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_set_cnstr_offseti[2:0])].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_22                                                              0x0105f4UL //Access:RW   DataWidth:0x20   // The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_set_cnstr_offseti[2:0])].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_23                                                              0x0105f8UL //Access:RW   DataWidth:0x20   // The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_set_cnstr_offseti[2:0])].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_0                                                              0x0105fcUL //Access:RW   DataWidth:0x1    // The frame that need to be compared. The 1 bit vector is determined as follows: frame[trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_1                                                              0x010600UL //Access:RW   DataWidth:0x1    // The frame that need to be compared. The 1 bit vector is determined as follows: frame[trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_2                                                              0x010604UL //Access:RW   DataWidth:0x1    // The frame that need to be compared. The 1 bit vector is determined as follows: frame[trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_3                                                              0x010608UL //Access:RW   DataWidth:0x1    // The frame that need to be compared. The 1 bit vector is determined as follows: frame[trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_4                                                              0x01060cUL //Access:RW   DataWidth:0x1    // The frame that need to be compared. The 1 bit vector is determined as follows: frame[trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_5                                                              0x010610UL //Access:RW   DataWidth:0x1    // The frame that need to be compared. The 1 bit vector is determined as follows: frame[trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_6                                                              0x010614UL //Access:RW   DataWidth:0x1    // The frame that need to be compared. The 1 bit vector is determined as follows: frame[trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_7                                                              0x010618UL //Access:RW   DataWidth:0x1    // The frame that need to be compared. The 1 bit vector is determined as follows: frame[trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_8                                                              0x01061cUL //Access:RW   DataWidth:0x1    // The frame that need to be compared. The 1 bit vector is determined as follows: frame[trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_9                                                              0x010620UL //Access:RW   DataWidth:0x1    // The frame that need to be compared. The 1 bit vector is determined as follows: frame[trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_10                                                             0x010624UL //Access:RW   DataWidth:0x1    // The frame that need to be compared. The 1 bit vector is determined as follows: frame[trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_11                                                             0x010628UL //Access:RW   DataWidth:0x1    // The frame that need to be compared. The 1 bit vector is determined as follows: frame[trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_12                                                             0x01062cUL //Access:RW   DataWidth:0x1    // The frame that need to be compared. The 1 bit vector is determined as follows: frame[trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_13                                                             0x010630UL //Access:RW   DataWidth:0x1    // The frame that need to be compared. The 1 bit vector is determined as follows: frame[trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_14                                                             0x010634UL //Access:RW   DataWidth:0x1    // The frame that need to be compared. The 1 bit vector is determined as follows: frame[trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_15                                                             0x010638UL //Access:RW   DataWidth:0x1    // The frame that need to be compared. The 1 bit vector is determined as follows: frame[trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_16                                                             0x01063cUL //Access:RW   DataWidth:0x1    // The frame that need to be compared. The 1 bit vector is determined as follows: frame[trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_17                                                             0x010640UL //Access:RW   DataWidth:0x1    // The frame that need to be compared. The 1 bit vector is determined as follows: frame[trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_18                                                             0x010644UL //Access:RW   DataWidth:0x1    // The frame that need to be compared. The 1 bit vector is determined as follows: frame[trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_19                                                             0x010648UL //Access:RW   DataWidth:0x1    // The frame that need to be compared. The 1 bit vector is determined as follows: frame[trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_20                                                             0x01064cUL //Access:RW   DataWidth:0x1    // The frame that need to be compared. The 1 bit vector is determined as follows: frame[trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_21                                                             0x010650UL //Access:RW   DataWidth:0x1    // The frame that need to be compared. The 1 bit vector is determined as follows: frame[trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_22                                                             0x010654UL //Access:RW   DataWidth:0x1    // The frame that need to be compared. The 1 bit vector is determined as follows: frame[trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_23                                                             0x010658UL //Access:RW   DataWidth:0x1    // The frame that need to be compared. The 1 bit vector is determined as follows: frame[trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_0                                                          0x01065cUL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_1                                                          0x010660UL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_2                                                          0x010664UL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_3                                                          0x010668UL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_4                                                          0x01066cUL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_5                                                          0x010670UL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_6                                                          0x010674UL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_7                                                          0x010678UL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_8                                                          0x01067cUL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_9                                                          0x010680UL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_10                                                         0x010684UL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_11                                                         0x010688UL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_12                                                         0x01068cUL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_13                                                         0x010690UL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_14                                                         0x010694UL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_15                                                         0x010698UL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_16                                                         0x01069cUL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_17                                                         0x0106a0UL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_18                                                         0x0106a4UL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_19                                                         0x0106a8UL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_20                                                         0x0106acUL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_21                                                         0x0106b0UL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_22                                                         0x0106b4UL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_23                                                         0x0106b8UL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_0                                                         0x0106bcUL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_1                                                         0x0106c0UL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_2                                                         0x0106c4UL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_3                                                         0x0106c8UL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_4                                                         0x0106ccUL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_5                                                         0x0106d0UL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_6                                                         0x0106d4UL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_7                                                         0x0106d8UL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_8                                                         0x0106dcUL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_9                                                         0x0106e0UL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_10                                                        0x0106e4UL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_11                                                        0x0106e8UL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_12                                                        0x0106ecUL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_13                                                        0x0106f0UL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_14                                                        0x0106f4UL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_15                                                        0x0106f8UL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_16                                                        0x0106fcUL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_17                                                        0x010700UL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_18                                                        0x010704UL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_19                                                        0x010708UL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_20                                                        0x01070cUL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_21                                                        0x010710UL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_22                                                        0x010714UL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_23                                                        0x010718UL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_0                                                              0x01071cUL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_1                                                              0x010720UL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_2                                                              0x010724UL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_3                                                              0x010728UL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_4                                                              0x01072cUL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_5                                                              0x010730UL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_6                                                              0x010734UL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_7                                                              0x010738UL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_8                                                              0x01073cUL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_9                                                              0x010740UL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_10                                                             0x010744UL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_11                                                             0x010748UL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_12                                                             0x01074cUL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_13                                                             0x010750UL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_14                                                             0x010754UL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_15                                                             0x010758UL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_16                                                             0x01075cUL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_17                                                             0x010760UL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_18                                                             0x010764UL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_19                                                             0x010768UL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_20                                                             0x01076cUL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_21                                                             0x010770UL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_22                                                             0x010774UL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_23                                                             0x010778UL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0                                                              0x01077cUL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_0                      (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_0_SHIFT                0
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_0                        (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_0_SHIFT                  5
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_1                                                              0x010780UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_1_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_1                      (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_1_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_1_SHIFT                0
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_1_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_1                        (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_1_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_1_SHIFT                  5
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_2                                                              0x010784UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_2_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_2                      (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_2_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_2_SHIFT                0
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_2_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_2                        (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_2_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_2_SHIFT                  5
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_3                                                              0x010788UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_3_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_3                      (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_3_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_3_SHIFT                0
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_3_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_3                        (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_3_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_3_SHIFT                  5
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_4                                                              0x01078cUL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_4_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_4                      (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_4_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_4_SHIFT                0
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_4_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_4                        (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_4_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_4_SHIFT                  5
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_5                                                              0x010790UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_5_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_5                      (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_5_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_5_SHIFT                0
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_5_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_5                        (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_5_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_5_SHIFT                  5
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_6                                                              0x010794UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_6_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_6                      (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_6_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_6_SHIFT                0
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_6_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_6                        (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_6_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_6_SHIFT                  5
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_7                                                              0x010798UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_7_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_7                      (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_7_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_7_SHIFT                0
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_7_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_7                        (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_7_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_7_SHIFT                  5
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_8                                                              0x01079cUL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_8_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_8                      (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_8_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_8_SHIFT                0
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_8_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_8                        (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_8_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_8_SHIFT                  5
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_9                                                              0x0107a0UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_9_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_9                      (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_9_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_9_SHIFT                0
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_9_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_9                        (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_9_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_9_SHIFT                  5
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_10                                                             0x0107a4UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_10_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_10                    (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_10_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_10_SHIFT              0
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_10_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_10                      (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_10_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_10_SHIFT                5
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_11                                                             0x0107a8UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_11_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_11                    (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_11_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_11_SHIFT              0
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_11_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_11                      (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_11_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_11_SHIFT                5
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_12                                                             0x0107acUL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_12_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_12                    (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_12_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_12_SHIFT              0
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_12_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_12                      (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_12_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_12_SHIFT                5
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_13                                                             0x0107b0UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_13_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_13                    (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_13_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_13_SHIFT              0
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_13_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_13                      (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_13_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_13_SHIFT                5
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_14                                                             0x0107b4UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_14_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_14                    (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_14_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_14_SHIFT              0
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_14_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_14                      (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_14_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_14_SHIFT                5
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_15                                                             0x0107b8UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_15_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_15                    (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_15_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_15_SHIFT              0
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_15_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_15                      (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_15_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_15_SHIFT                5
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_16                                                             0x0107bcUL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_16_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_16                    (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_16_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_16_SHIFT              0
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_16_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_16                      (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_16_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_16_SHIFT                5
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_17                                                             0x0107c0UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_17_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_17                    (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_17_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_17_SHIFT              0
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_17_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_17                      (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_17_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_17_SHIFT                5
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_18                                                             0x0107c4UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_18_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_18                    (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_18_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_18_SHIFT              0
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_18_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_18                      (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_18_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_18_SHIFT                5
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_19                                                             0x0107c8UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_19_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_19                    (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_19_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_19_SHIFT              0
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_19_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_19                      (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_19_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_19_SHIFT                5
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_20                                                             0x0107ccUL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_20_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_20                    (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_20_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_20_SHIFT              0
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_20_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_20                      (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_20_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_20_SHIFT                5
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_21                                                             0x0107d0UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_21_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_21                    (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_21_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_21_SHIFT              0
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_21_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_21                      (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_21_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_21_SHIFT                5
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_22                                                             0x0107d4UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_22_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_22                    (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_22_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_22_SHIFT              0
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_22_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_22                      (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_22_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_22_SHIFT                5
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_23                                                             0x0107d8UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_23_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_23                    (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_23_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_23_SHIFT              0
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_23_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_23                      (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_23_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_23_SHIFT                5
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_0                                                             0x0107dcUL //Access:RW   DataWidth:0xb    // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_1                                                             0x0107e0UL //Access:RW   DataWidth:0xb    // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_2                                                             0x0107e4UL //Access:RW   DataWidth:0xb    // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_3                                                             0x0107e8UL //Access:RW   DataWidth:0xb    // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_4                                                             0x0107ecUL //Access:RW   DataWidth:0xb    // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_5                                                             0x0107f0UL //Access:RW   DataWidth:0xb    // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_6                                                             0x0107f4UL //Access:RW   DataWidth:0xb    // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_7                                                             0x0107f8UL //Access:RW   DataWidth:0xb    // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_8                                                             0x0107fcUL //Access:RW   DataWidth:0xb    // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_9                                                             0x010800UL //Access:RW   DataWidth:0xb    // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_10                                                            0x010804UL //Access:RW   DataWidth:0xb    // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_11                                                            0x010808UL //Access:RW   DataWidth:0xb    // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_12                                                            0x01080cUL //Access:RW   DataWidth:0xb    // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_13                                                            0x010810UL //Access:RW   DataWidth:0xb    // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_14                                                            0x010814UL //Access:RW   DataWidth:0xb    // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_15                                                            0x010818UL //Access:RW   DataWidth:0xb    // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_16                                                            0x01081cUL //Access:RW   DataWidth:0xb    // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_17                                                            0x010820UL //Access:RW   DataWidth:0xb    // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_18                                                            0x010824UL //Access:RW   DataWidth:0xb    // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_19                                                            0x010828UL //Access:RW   DataWidth:0xb    // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_20                                                            0x01082cUL //Access:RW   DataWidth:0xb    // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_21                                                            0x010830UL //Access:RW   DataWidth:0xb    // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_22                                                            0x010834UL //Access:RW   DataWidth:0xb    // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_23                                                            0x010838UL //Access:RW   DataWidth:0xb    // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_0                                                               0x01083cUL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_1                                                               0x010840UL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_2                                                               0x010844UL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_3                                                               0x010848UL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_4                                                               0x01084cUL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_5                                                               0x010850UL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_6                                                               0x010854UL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_7                                                               0x010858UL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_8                                                               0x01085cUL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_9                                                               0x010860UL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_10                                                              0x010864UL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_11                                                              0x010868UL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_12                                                              0x01086cUL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_13                                                              0x010870UL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_14                                                              0x010874UL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_15                                                              0x010878UL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_16                                                              0x01087cUL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_17                                                              0x010880UL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_18                                                              0x010884UL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_19                                                              0x010888UL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_20                                                              0x01088cUL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_21                                                              0x010890UL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_22                                                              0x010894UL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_23                                                              0x010898UL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_0                                                             0x01089cUL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_1                                                             0x0108a0UL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_2                                                             0x0108a4UL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_3                                                             0x0108a8UL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_4                                                             0x0108acUL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_5                                                             0x0108b0UL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_6                                                             0x0108b4UL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_7                                                             0x0108b8UL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_8                                                             0x0108bcUL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_9                                                             0x0108c0UL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_10                                                            0x0108c4UL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_11                                                            0x0108c8UL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_12                                                            0x0108ccUL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_13                                                            0x0108d0UL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_14                                                            0x0108d4UL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_15                                                            0x0108d8UL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_16                                                            0x0108dcUL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_17                                                            0x0108e0UL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_18                                                            0x0108e4UL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_19                                                            0x0108e8UL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_20                                                            0x0108ecUL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_21                                                            0x0108f0UL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_22                                                            0x0108f4UL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_23                                                            0x0108f8UL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_0                                                             0x0108fcUL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_1                                                             0x010900UL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_2                                                             0x010904UL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_3                                                             0x010908UL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_4                                                             0x01090cUL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_5                                                             0x010910UL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_6                                                             0x010914UL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_7                                                             0x010918UL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_8                                                             0x01091cUL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_9                                                             0x010920UL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_10                                                            0x010924UL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_11                                                            0x010928UL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_12                                                            0x01092cUL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_13                                                            0x010930UL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_14                                                            0x010934UL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_15                                                            0x010938UL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_16                                                            0x01093cUL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_17                                                            0x010940UL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_18                                                            0x010944UL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_19                                                            0x010948UL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_20                                                            0x01094cUL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_21                                                            0x010950UL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_22                                                            0x010954UL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_23                                                            0x010958UL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_TRIGGER_STATE_MSG_LENGTH_ENABLE_0                                                            0x01095cUL //Access:RW   DataWidth:0x1    // (a) 1: use trigger_state_msg_lengthi  to determine message boundary. (b) 0: use masking according to trigger_state_id only.
+#define DBG_REG_TRIGGER_STATE_MSG_LENGTH_ENABLE_1                                                            0x010960UL //Access:RW   DataWidth:0x1    // (a) 1: use trigger_state_msg_lengthi  to determine message boundary. (b) 0: use masking according to trigger_state_id only.
+#define DBG_REG_TRIGGER_STATE_MSG_LENGTH_ENABLE_2                                                            0x010964UL //Access:RW   DataWidth:0x1    // (a) 1: use trigger_state_msg_lengthi  to determine message boundary. (b) 0: use masking according to trigger_state_id only.
+#define DBG_REG_TRIGGER_STATE_MSG_LENGTH_0                                                                   0x010968UL //Access:RW   DataWidth:0x8    // Message length-1  in terms of numbers of 128-bit cycles. NOTE: (a) if for example trigger_state_msg_lengthi=0 then Message length = 1 cycle. (b) if for example trigger_state_msg_lengthi=1 then Message length = 2 cycles. etc.   (c) Applicable only when trigger_state_msg_length_eni = 1.
+#define DBG_REG_TRIGGER_STATE_MSG_LENGTH_1                                                                   0x01096cUL //Access:RW   DataWidth:0x8    // Message length-1  in terms of numbers of 128-bit cycles. NOTE: (a) if for example trigger_state_msg_lengthi=0 then Message length = 1 cycle. (b) if for example trigger_state_msg_lengthi=1 then Message length = 2 cycles. etc.   (c) Applicable only when trigger_state_msg_length_eni = 1.
+#define DBG_REG_TRIGGER_STATE_MSG_LENGTH_2                                                                   0x010970UL //Access:RW   DataWidth:0x8    // Message length-1  in terms of numbers of 128-bit cycles. NOTE: (a) if for example trigger_state_msg_lengthi=0 then Message length = 1 cycle. (b) if for example trigger_state_msg_lengthi=1 then Message length = 2 cycles. etc.   (c) Applicable only when trigger_state_msg_length_eni = 1.
+#define DBG_REG_TRIGGER_EVENT                                                                                0x010974UL //Access:R    DataWidth:0x1    // Configured messages sequencing was identified.
+#define DBG_REG_TRIGGER_INDIRECT0_STATE                                                                      0x010978UL //Access:RW   DataWidth:0x3    // If set then record data in relevant state;  If clear then do not record data in relevant state;    b0: state0; b1: state1; b2: state2;.
+#define DBG_REG_TRIGGER_INDIRECT0_OFFSET_0                                                                   0x01097cUL //Access:RW   DataWidth:0xb    // The offset in relevant state (fsm triggering machine) from beginning of message to the data that should be recorded for indirect value usage. If set of constraints appear more than once (trigger_state_set_counti >1) then data[32*(trigger_indirect0_offseti[2:0]+1)-1:32*trigger_indirect0_offseti[2:0]] in cycle trigger_indirect0_offseti[11:3] from the last message will be recorded. For example offset=0 is for 128-bit cycle 0 for the 32 lsb; offset=1 is for 128-bit cycle 0 for the bits 63:32; offset=4N is for 128-bit cycle N for the 32 lsb; offset=4N+2 is for 128-bit cycle N for the bits 95:64.
+#define DBG_REG_TRIGGER_INDIRECT0_OFFSET_1                                                                   0x010980UL //Access:RW   DataWidth:0xb    // The offset in relevant state (fsm triggering machine) from beginning of message to the data that should be recorded for indirect value usage. If set of constraints appear more than once (trigger_state_set_counti >1) then data[32*(trigger_indirect0_offseti[2:0]+1)-1:32*trigger_indirect0_offseti[2:0]] in cycle trigger_indirect0_offseti[11:3] from the last message will be recorded. For example offset=0 is for 128-bit cycle 0 for the 32 lsb; offset=1 is for 128-bit cycle 0 for the bits 63:32; offset=4N is for 128-bit cycle N for the 32 lsb; offset=4N+2 is for 128-bit cycle N for the bits 95:64.
+#define DBG_REG_TRIGGER_INDIRECT0_OFFSET_2                                                                   0x010984UL //Access:RW   DataWidth:0xb    // The offset in relevant state (fsm triggering machine) from beginning of message to the data that should be recorded for indirect value usage. If set of constraints appear more than once (trigger_state_set_counti >1) then data[32*(trigger_indirect0_offseti[2:0]+1)-1:32*trigger_indirect0_offseti[2:0]] in cycle trigger_indirect0_offseti[11:3] from the last message will be recorded. For example offset=0 is for 128-bit cycle 0 for the 32 lsb; offset=1 is for 128-bit cycle 0 for the bits 63:32; offset=4N is for 128-bit cycle N for the 32 lsb; offset=4N+2 is for 128-bit cycle N for the bits 95:64.
+#define DBG_REG_TRIGGER_INDIRECT0_SHIFT_0                                                                    0x010988UL //Access:RW   DataWidth:0x5    // Shift vector (bit resolution) for the data trigger_indirect0_recorded_data  The shift is implemented after the recording (after the registering) of the indirect register is implemented. The comparison with the actual coming data is implemented on the shifted data.
+#define DBG_REG_TRIGGER_INDIRECT0_SHIFT_1                                                                    0x01098cUL //Access:RW   DataWidth:0x5    // Shift vector (bit resolution) for the data trigger_indirect0_recorded_data  The shift is implemented after the recording (after the registering) of the indirect register is implemented. The comparison with the actual coming data is implemented on the shifted data.
+#define DBG_REG_TRIGGER_INDIRECT0_SHIFT_2                                                                    0x010990UL //Access:RW   DataWidth:0x5    // Shift vector (bit resolution) for the data trigger_indirect0_recorded_data  The shift is implemented after the recording (after the registering) of the indirect register is implemented. The comparison with the actual coming data is implemented on the shifted data.
+#define DBG_REG_TRIGGER_INDIRECT0_MASK_0                                                                     0x010994UL //Access:RW   DataWidth:0x20   // If set then the relevant bit will be zeroed; if clear then the relevant bit will be registered with its exact data. NOTE: (a) Mask is implemented prior to registering the recorded data to trigger_indirect0_recorded_data; (b) The mask is implemented in bit resolution. (c) useful when trigger_state_set_cnstr_oprtni is in (>/</=</=>).
+#define DBG_REG_TRIGGER_INDIRECT0_MASK_1                                                                     0x010998UL //Access:RW   DataWidth:0x20   // If set then the relevant bit will be zeroed; if clear then the relevant bit will be registered with its exact data. NOTE: (a) Mask is implemented prior to registering the recorded data to trigger_indirect0_recorded_data; (b) The mask is implemented in bit resolution. (c) useful when trigger_state_set_cnstr_oprtni is in (>/</=</=>).
+#define DBG_REG_TRIGGER_INDIRECT0_MASK_2                                                                     0x01099cUL //Access:RW   DataWidth:0x20   // If set then the relevant bit will be zeroed; if clear then the relevant bit will be registered with its exact data. NOTE: (a) Mask is implemented prior to registering the recorded data to trigger_indirect0_recorded_data; (b) The mask is implemented in bit resolution. (c) useful when trigger_state_set_cnstr_oprtni is in (>/</=</=>).
+#define DBG_REG_TRIGGER_INDIRECT0_RECORDED_DATA                                                              0x0109a0UL //Access:R    DataWidth:0x20   // The data that was recorded trigger_indirect0_offset cycles after start of message (during triggering machine operation in state trigger_indirect0_state); NOTE: CID recording for filtering purpose within the sem must use this register (and NOT trigger_indirect1_recorded_data register).
+#define DBG_REG_TRIGGER_INDIRECT1_STATE                                                                      0x0109a4UL //Access:RW   DataWidth:0x3    // If set then record data in relevant state;  If clear then do not record data in relevant state; b0: state0; b1: state1; b2: state2;.
+#define DBG_REG_TRIGGER_INDIRECT1_OFFSET_0                                                                   0x0109a8UL //Access:RW   DataWidth:0xb    // The offset in relevant state (fsm triggering machine) from beginning of message to the data that should be recorded for indirect value usage. If set of constraints appear more than once (trigger_state_set_counti >1) then data[32*(trigger_indirect1_offseti[2:0]+1)-1:32*trigger_indirect1_offseti[2:0]] in cycle trigger_indirect1_offseti[11:3] from the last message will be recorded. For example offset=0 is for 128-bit cycle 0 for the 32 lsb; offset=1 is for 128-bit cycle 0 for the bits 63:32; offset=4N is for 128-bit cycle N for the 32 lsb; offset=4N+2 is for 128-bit cycle N for the bits 95:64.
+#define DBG_REG_TRIGGER_INDIRECT1_OFFSET_1                                                                   0x0109acUL //Access:RW   DataWidth:0xb    // The offset in relevant state (fsm triggering machine) from beginning of message to the data that should be recorded for indirect value usage. If set of constraints appear more than once (trigger_state_set_counti >1) then data[32*(trigger_indirect1_offseti[2:0]+1)-1:32*trigger_indirect1_offseti[2:0]] in cycle trigger_indirect1_offseti[11:3] from the last message will be recorded. For example offset=0 is for 128-bit cycle 0 for the 32 lsb; offset=1 is for 128-bit cycle 0 for the bits 63:32; offset=4N is for 128-bit cycle N for the 32 lsb; offset=4N+2 is for 128-bit cycle N for the bits 95:64.
+#define DBG_REG_TRIGGER_INDIRECT1_OFFSET_2                                                                   0x0109b0UL //Access:RW   DataWidth:0xb    // The offset in relevant state (fsm triggering machine) from beginning of message to the data that should be recorded for indirect value usage. If set of constraints appear more than once (trigger_state_set_counti >1) then data[32*(trigger_indirect1_offseti[2:0]+1)-1:32*trigger_indirect1_offseti[2:0]] in cycle trigger_indirect1_offseti[11:3] from the last message will be recorded. For example offset=0 is for 128-bit cycle 0 for the 32 lsb; offset=1 is for 128-bit cycle 0 for the bits 63:32; offset=4N is for 128-bit cycle N for the 32 lsb; offset=4N+2 is for 128-bit cycle N for the bits 95:64.
+#define DBG_REG_TRIGGER_INDIRECT1_SHIFT_0                                                                    0x0109b4UL //Access:RW   DataWidth:0x5    // Shift vector (bit resolution) for the data trigger_indirect1_recorded_data  The shift is implemented after the recording (after the registering) of the indirect register is implemented. The comparison with the actual coming data is implemented on the shifted data.
+#define DBG_REG_TRIGGER_INDIRECT1_SHIFT_1                                                                    0x0109b8UL //Access:RW   DataWidth:0x5    // Shift vector (bit resolution) for the data trigger_indirect1_recorded_data  The shift is implemented after the recording (after the registering) of the indirect register is implemented. The comparison with the actual coming data is implemented on the shifted data.
+#define DBG_REG_TRIGGER_INDIRECT1_SHIFT_2                                                                    0x0109bcUL //Access:RW   DataWidth:0x5    // Shift vector (bit resolution) for the data trigger_indirect1_recorded_data  The shift is implemented after the recording (after the registering) of the indirect register is implemented. The comparison with the actual coming data is implemented on the shifted data.
+#define DBG_REG_TRIGGER_INDIRECT1_MASK_0                                                                     0x0109c0UL //Access:RW   DataWidth:0x20   // If set then the relevant bit will be zeroed; if clear then the relevant bit will be registered with its exact data.  NOTE:  (a) Mask is implemented prior to registering the recorded data to trigger_indirect1_recorded_data; (b) The mask is implemented in bit resolution. (c) useful when trigger_state_set_cnstr_oprtni is in (>/</=</=>).
+#define DBG_REG_TRIGGER_INDIRECT1_MASK_1                                                                     0x0109c4UL //Access:RW   DataWidth:0x20   // If set then the relevant bit will be zeroed; if clear then the relevant bit will be registered with its exact data.  NOTE:  (a) Mask is implemented prior to registering the recorded data to trigger_indirect1_recorded_data; (b) The mask is implemented in bit resolution. (c) useful when trigger_state_set_cnstr_oprtni is in (>/</=</=>).
+#define DBG_REG_TRIGGER_INDIRECT1_MASK_2                                                                     0x0109c8UL //Access:RW   DataWidth:0x20   // If set then the relevant bit will be zeroed; if clear then the relevant bit will be registered with its exact data.  NOTE:  (a) Mask is implemented prior to registering the recorded data to trigger_indirect1_recorded_data; (b) The mask is implemented in bit resolution. (c) useful when trigger_state_set_cnstr_oprtni is in (>/</=</=>).
+#define DBG_REG_TRIGGER_INDIRECT1_RECORDED_DATA                                                              0x0109ccUL //Access:R    DataWidth:0x20   // The data that was recorded trigger_indirect1_offset cycles after start of message (during triggering machine operation in state trigger_indirect0_state);.
+#define DBG_REG_FILTER_ENABLE                                                                                0x0109d0UL //Access:RW   DataWidth:0x2    // (a) 00 - Filter off; in that case all data should be transmitted to the internal buffer without any filtering implemented (data should bypass filtering machine). (b) 01 - Filter on prior (in time domain) to trigger_event (asserted by the triggering machine block) only; When off (after trigger event) - data should be transmitted to the internal buffer without any filtering. in this mode trigger_enable must be set.  (c) 10 - Filter on upon trigger_event (asserted by the triggering machine) only. When off (before trigger event) - data should be transmitted to the internal buffer without any filtering. in this mode trigger_enable must be set. (d) 11 - Filter on - constant filtering; in this case the triggering event (asserted by the triggering machine) is irrelevant.
+#define DBG_REG_FILTER_ID_NUM                                                                                0x0109d4UL //Access:RW   DataWidth:0x4    // Number of ID that should be filtered.Number of ID that should be filtered. For HW block only bits[2:0] are used. Bit[3] should be set to 0. For STORM bit[3] designates what STORM should be triggered (0 - STORM A; 1 - STORM B). Bits[2:0] designate STORM ID.
+#define DBG_REG_FILTER_CNSTR_DATA_0                                                                          0x0109d8UL //Access:RW   DataWidth:0x20   // The value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_offseti[2:0]].
+#define DBG_REG_FILTER_CNSTR_DATA_1                                                                          0x0109dcUL //Access:RW   DataWidth:0x20   // The value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_offseti[2:0]].
+#define DBG_REG_FILTER_CNSTR_DATA_2                                                                          0x0109e0UL //Access:RW   DataWidth:0x20   // The value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_offseti[2:0]].
+#define DBG_REG_FILTER_CNSTR_DATA_3                                                                          0x0109e4UL //Access:RW   DataWidth:0x20   // The value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_offseti[2:0]].
+#define DBG_REG_FILTER_CNSTR_FRAME_0                                                                         0x0109e8UL //Access:RW   DataWidth:0x1    // The value that need to be compared with frame[32*filter_cnstr_offseti[2:0]].
+#define DBG_REG_FILTER_CNSTR_FRAME_1                                                                         0x0109ecUL //Access:RW   DataWidth:0x1    // The value that need to be compared with frame[32*filter_cnstr_offseti[2:0]].
+#define DBG_REG_FILTER_CNSTR_FRAME_2                                                                         0x0109f0UL //Access:RW   DataWidth:0x1    // The value that need to be compared with frame[32*filter_cnstr_offseti[2:0]].
+#define DBG_REG_FILTER_CNSTR_FRAME_3                                                                         0x0109f4UL //Access:RW   DataWidth:0x1    // The value that need to be compared with frame[32*filter_cnstr_offseti[2:0]].
+#define DBG_REG_FILTER_CNSTR_DATA_MASK_0                                                                     0x0109f8UL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not operation (filter_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_FILTER_CNSTR_DATA_MASK_1                                                                     0x0109fcUL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not operation (filter_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_FILTER_CNSTR_DATA_MASK_2                                                                     0x010a00UL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not operation (filter_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_FILTER_CNSTR_DATA_MASK_3                                                                     0x010a04UL //Access:RW   DataWidth:0x20   // If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not operation (filter_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_FILTER_CNSTR_FRAME_MASK_0                                                                    0x010a08UL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 -  the frame is compared; NOTE:  The mask is valid only for the equal and not equal operations (trigger_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_FILTER_CNSTR_FRAME_MASK_1                                                                    0x010a0cUL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 -  the frame is compared; NOTE:  The mask is valid only for the equal and not equal operations (trigger_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_FILTER_CNSTR_FRAME_MASK_2                                                                    0x010a10UL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 -  the frame is compared; NOTE:  The mask is valid only for the equal and not equal operations (trigger_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_FILTER_CNSTR_FRAME_MASK_3                                                                    0x010a14UL //Access:RW   DataWidth:0x1    // (a) 1 - the frame is masked (not compared); (b) 0 -  the frame is compared; NOTE:  The mask is valid only for the equal and not equal operations (trigger_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
+#define DBG_REG_FILTER_CNSTR_OFFSET_0                                                                        0x010a18UL //Access:RW   DataWidth:0x5    // The filtering is implemented according to the data on the first 4 cycles only. The above value vector (data and frame) should be compared filter_cnstr_offseti[4:3] cycles after start of message; filter_cnstr_offseti[2:0] represent the dword offset within a cycle.
+#define DBG_REG_FILTER_CNSTR_OFFSET_1                                                                        0x010a1cUL //Access:RW   DataWidth:0x5    // The filtering is implemented according to the data on the first 4 cycles only. The above value vector (data and frame) should be compared filter_cnstr_offseti[4:3] cycles after start of message; filter_cnstr_offseti[2:0] represent the dword offset within a cycle.
+#define DBG_REG_FILTER_CNSTR_OFFSET_2                                                                        0x010a20UL //Access:RW   DataWidth:0x5    // The filtering is implemented according to the data on the first 4 cycles only. The above value vector (data and frame) should be compared filter_cnstr_offseti[4:3] cycles after start of message; filter_cnstr_offseti[2:0] represent the dword offset within a cycle.
+#define DBG_REG_FILTER_CNSTR_OFFSET_3                                                                        0x010a24UL //Access:RW   DataWidth:0x5    // The filtering is implemented according to the data on the first 4 cycles only. The above value vector (data and frame) should be compared filter_cnstr_offseti[4:3] cycles after start of message; filter_cnstr_offseti[2:0] represent the dword offset within a cycle.
+#define DBG_REG_FILTER_CNSTR_OPRTN_0                                                                         0x010a28UL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>); (f) 101 = not equal (!=);.
+#define DBG_REG_FILTER_CNSTR_OPRTN_1                                                                         0x010a2cUL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>); (f) 101 = not equal (!=);.
+#define DBG_REG_FILTER_CNSTR_OPRTN_2                                                                         0x010a30UL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>); (f) 101 = not equal (!=);.
+#define DBG_REG_FILTER_CNSTR_OPRTN_3                                                                         0x010a34UL //Access:RW   DataWidth:0x3    // The comparison operation that should be implemented between actual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>); (f) 101 = not equal (!=);.
+#define DBG_REG_FILTER_CNSTR_RANGE_0                                                                         0x010a38UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_FILTER_CNSTR_RANGE_0_FILTER_CNSTR_RANGE_WIDTH_0                                            (0x1f<<0) // If the comparison operation is not (equal or not equal) (filter_cnstr_oprtni>000 or 101) than apply the operation on a field of width filter_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit filter_cnstr_range_lsb (values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and filter_cnstr_datai =0x3f and filter_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_FILTER_CNSTR_RANGE_0_FILTER_CNSTR_RANGE_WIDTH_0_SHIFT                                      0
+  #define DBG_REG_FILTER_CNSTR_RANGE_0_FILTER_CNSTR_RANGE_LSB_0                                              (0x1f<<5) // If the comparison operation is not (equal or not equal) (filter_cnstr_oprtni>000 or 101) than apply the operation on a field of width filter_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit filter_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and filter_cnstr_datai =0x3f and filter_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_FILTER_CNSTR_RANGE_0_FILTER_CNSTR_RANGE_LSB_0_SHIFT                                        5
+#define DBG_REG_FILTER_CNSTR_RANGE_1                                                                         0x010a3cUL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_FILTER_CNSTR_RANGE_1_FILTER_CNSTR_RANGE_WIDTH_1                                            (0x1f<<0) // If the comparison operation is not (equal or not equal) (filter_cnstr_oprtni>000 or 101) than apply the operation on a field of width filter_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit filter_cnstr_range_lsb (values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and filter_cnstr_datai =0x3f and filter_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_FILTER_CNSTR_RANGE_1_FILTER_CNSTR_RANGE_WIDTH_1_SHIFT                                      0
+  #define DBG_REG_FILTER_CNSTR_RANGE_1_FILTER_CNSTR_RANGE_LSB_1                                              (0x1f<<5) // If the comparison operation is not (equal or not equal) (filter_cnstr_oprtni>000 or 101) than apply the operation on a field of width filter_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit filter_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and filter_cnstr_datai =0x3f and filter_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_FILTER_CNSTR_RANGE_1_FILTER_CNSTR_RANGE_LSB_1_SHIFT                                        5
+#define DBG_REG_FILTER_CNSTR_RANGE_2                                                                         0x010a40UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_FILTER_CNSTR_RANGE_2_FILTER_CNSTR_RANGE_WIDTH_2                                            (0x1f<<0) // If the comparison operation is not (equal or not equal) (filter_cnstr_oprtni>000 or 101) than apply the operation on a field of width filter_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit filter_cnstr_range_lsb (values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and filter_cnstr_datai =0x3f and filter_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_FILTER_CNSTR_RANGE_2_FILTER_CNSTR_RANGE_WIDTH_2_SHIFT                                      0
+  #define DBG_REG_FILTER_CNSTR_RANGE_2_FILTER_CNSTR_RANGE_LSB_2                                              (0x1f<<5) // If the comparison operation is not (equal or not equal) (filter_cnstr_oprtni>000 or 101) than apply the operation on a field of width filter_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit filter_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and filter_cnstr_datai =0x3f and filter_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_FILTER_CNSTR_RANGE_2_FILTER_CNSTR_RANGE_LSB_2_SHIFT                                        5
+#define DBG_REG_FILTER_CNSTR_RANGE_3                                                                         0x010a44UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define DBG_REG_FILTER_CNSTR_RANGE_3_FILTER_CNSTR_RANGE_WIDTH_3                                            (0x1f<<0) // If the comparison operation is not (equal or not equal) (filter_cnstr_oprtni>000 or 101) than apply the operation on a field of width filter_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit filter_cnstr_range_lsb (values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and filter_cnstr_datai =0x3f and filter_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_FILTER_CNSTR_RANGE_3_FILTER_CNSTR_RANGE_WIDTH_3_SHIFT                                      0
+  #define DBG_REG_FILTER_CNSTR_RANGE_3_FILTER_CNSTR_RANGE_LSB_3                                              (0x1f<<5) // If the comparison operation is not (equal or not equal) (filter_cnstr_oprtni>000 or 101) than apply the operation on a field of width filter_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit filter_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and filter_cnstr_datai =0x3f and filter_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
+  #define DBG_REG_FILTER_CNSTR_RANGE_3_FILTER_CNSTR_RANGE_LSB_3_SHIFT                                        5
+#define DBG_REG_FILTER_CNSTR_MUST_0                                                                          0x010a48UL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector & frame must exist as part of the message.  (b) 0: the above data vector & vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_FILTER_CNSTR_MUST_1                                                                          0x010a4cUL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector & frame must exist as part of the message.  (b) 0: the above data vector & vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_FILTER_CNSTR_MUST_2                                                                          0x010a50UL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector & frame must exist as part of the message.  (b) 0: the above data vector & vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_FILTER_CNSTR_MUST_3                                                                          0x010a54UL //Access:RW   DataWidth:0x1    // (a) 1: the above data vector & frame must exist as part of the message.  (b) 0: the above data vector & vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
+#define DBG_REG_FILTER_CNSTR_INDIRECT_0                                                                      0x010a58UL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the filter_cnstr_datai.(b) 01: indirect: use the recorded value 0 from of fsm triggering machine (trigger_indirect0_recorded_data).   (c) 10: indirect: use the recorded value 1 from of fsm triggering machine (trigger_indirect1_recorded_data). NOTE: if filter_enable=11 OR filter_enable=01 then filter_cnstr_indirecti MUST be all 0 (need to filter prior to triggering machine event and hence cannot use the recorded data from state 0 in triggering machine).
+#define DBG_REG_FILTER_CNSTR_INDIRECT_1                                                                      0x010a5cUL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the filter_cnstr_datai.(b) 01: indirect: use the recorded value 0 from of fsm triggering machine (trigger_indirect0_recorded_data).   (c) 10: indirect: use the recorded value 1 from of fsm triggering machine (trigger_indirect1_recorded_data). NOTE: if filter_enable=11 OR filter_enable=01 then filter_cnstr_indirecti MUST be all 0 (need to filter prior to triggering machine event and hence cannot use the recorded data from state 0 in triggering machine).
+#define DBG_REG_FILTER_CNSTR_INDIRECT_2                                                                      0x010a60UL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the filter_cnstr_datai.(b) 01: indirect: use the recorded value 0 from of fsm triggering machine (trigger_indirect0_recorded_data).   (c) 10: indirect: use the recorded value 1 from of fsm triggering machine (trigger_indirect1_recorded_data). NOTE: if filter_enable=11 OR filter_enable=01 then filter_cnstr_indirecti MUST be all 0 (need to filter prior to triggering machine event and hence cannot use the recorded data from state 0 in triggering machine).
+#define DBG_REG_FILTER_CNSTR_INDIRECT_3                                                                      0x010a64UL //Access:RW   DataWidth:0x2    // (a) 00: direct: use the value which was configured in the filter_cnstr_datai.(b) 01: indirect: use the recorded value 0 from of fsm triggering machine (trigger_indirect0_recorded_data).   (c) 10: indirect: use the recorded value 1 from of fsm triggering machine (trigger_indirect1_recorded_data). NOTE: if filter_enable=11 OR filter_enable=01 then filter_cnstr_indirecti MUST be all 0 (need to filter prior to triggering machine event and hence cannot use the recorded data from state 0 in triggering machine).
+#define DBG_REG_FILTER_CNSTR_CYCLIC_0                                                                        0x010a68UL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal)  (filter_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_FILTER_CNSTR_CYCLIC_1                                                                        0x010a6cUL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal)  (filter_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_FILTER_CNSTR_CYCLIC_2                                                                        0x010a70UL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal)  (filter_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_FILTER_CNSTR_CYCLIC_3                                                                        0x010a74UL //Access:RW   DataWidth:0x1    // Refers the comparison which is implemented in case the operation is NOT (equal or not equal)  (filter_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
+#define DBG_REG_FILTER_MSG_LENGTH_ENABLE                                                                     0x010a78UL //Access:RW   DataWidth:0x1    // (a) 1: use filter_msg_length to determine message boundary. (b) 0: use the frame bit to determine message boundary.
+#define DBG_REG_FILTER_MSG_LENGTH                                                                            0x010a7cUL //Access:RW   DataWidth:0x8    // Message length-1  in terms of numbers of 128-bit cycles.  NOTE: (a) if for example filter_msg_length=0 then Message length = 1 cycle. (b) if for example filter_msg_lengthi=1 then Message length = 2 cycles. etc (c) Applicable only when filter_msg_length_en = 1.
+#define DBG_REG_FILTER_PARTIAL_RECORD_EN                                                                     0x010a80UL //Access:RW   DataWidth:0x1    // When set that enables of partial message record. Other way record is done for whole message (when message is filtered). Note: (a) When filter_enable = 1 (Filter on prior to trigger_event) the messages are partially recorded not only before the trigger_event but also after trigger_event (for the messages that are not filtered). (b) when filter_enable = 2 (Filter on upon trigger_event) the messages are partially recorded not only after the trigger_event, but also before trigger_event (for the messages that are not filtered).
+#define DBG_REG_FILTER_PARTIAL_RECORD_NUM                                                                    0x010a84UL //Access:RW   DataWidth:0x8    // The message length-1 of the recorded part size in terms of numbers of 128-bit cycles: 0 is 1 cycle; 1 is 2 cycles; etc. Applicable only when filter_partial_record_en = 1.
+#define DBG_REG_RCRD_ON_WINDOW_PRE_TRGR_EVNT_MODE                                                            0x010a88UL //Access:RW   DataWidth:0x2    // Recording mode prior to trigger event: (a) 00 - record from time=0;  (b) 01 - record rcrd_on_window_pre_num_chunks chunks to internal buffer prior to triggering event; (c) 10 - Don't record prior to triggering event (drop data).  NOTE: applicable only if trigger_enable=1.
+#define DBG_REG_RCRD_ON_WINDOW_POST_TRGR_EVNT_MODE                                                           0x010a8cUL //Access:RW   DataWidth:0x1    // Recording mode upon trigger event:  (a) 0- enable recording data upon triggering event; in that case record for rcrd_on_window_post_num_cycles valid cycles upon the event;  (b) 1 - disable recording data upon triggering event. NOTE:  applicable only if trigger_enable=1.
+#define DBG_REG_RCRD_ON_WINDOW_PRE_NUM_CHUNKS                                                                0x010a90UL //Access:RW   DataWidth:0x6    // Number of chunks (chunk = 4 lines of 512 bit each within the internal buffer) that should be recorded to the internal buffer prior to triggering event. NOTE:  (1) applicable only when rcrd_on_window_pre_trgr_evnt_mode=01; (2) valid values are 1..47;  (3) the data that will be stored in the internal buffer is the most recent data prior to the triggering event. (4) rcrd_on_window_pre_num_chunks represents the maximum number of chunks that will be written to the internal buffer; if from since time=0 until triggering event the amount of driven data is smaller then the amount of the above value the amount of data stored in the internal buffer will be smaller then the above value.
+#define DBG_REG_RCRD_ON_WINDOW_POST_NUM_CYCLES                                                               0x010a94UL //Access:RW   DataWidth:0x20   // Number of valid cycles that should be recorded upon triggering event.  NOTE: (1) applicable only when rcrd_on_window_post_trgr_evnt_mode=0; (2) value of 0xffffffff (maximum value) result in recording of unlimited amount of cycles (infinite amount of cycles).
+#define DBG_REG_PCI_FUNC_NUM                                                                                 0x010a98UL //Access:RW   DataWidth:0x10   // 16-bit opaque FID for pci request interface.
+#define DBG_REG_INT_BUFFER_WRAP_COUNTER                                                                      0x010a9cUL //Access:R    DataWidth:0x20   // Number of wraps on internal buffer; NOTE: valid only when debug_target=0 (internal buffer) and full_mode=1 (wrap) . Will stuck on all ones.
+#define DBG_REG_DBG_NM_MBIST1_CNTRL_CMD                                                                      0x010aa0UL //Access:RW   DataWidth:0x5    // NA.
+#define DBG_REG_NM_CLK_MBIST1_CNTRL_DBG_STATUS_0                                                             0x010aa4UL //Access:R    DataWidth:0x20   // NA.
+#define DBG_REG_NM_CLK_MBIST1_CNTRL_DBG_STATUS_1                                                             0x010aa8UL //Access:R    DataWidth:0x20   // NA.
+#define DBG_REG_NM_CLK_CP_MBIST1_CNTRL_DBG_STATUS_0                                                          0x010aacUL //Access:R    DataWidth:0x20   // NA.
+#define DBG_REG_INTERNAL_BUFFER_LSB_TM                                                                       0x010ab0UL //Access:RW   DataWidth:0x8    // Tm port for the internal buffer lsb memory instance.
+#define DBG_REG_INTERNAL_BUFFER_MSB_TM                                                                       0x010ab4UL //Access:RW   DataWidth:0x8    // Tm port for the internal buffer msb memory instance.
+#define DBG_REG_ECO_RESERVED                                                                                 0x010ab8UL //Access:RW   DataWidth:0x8    // Eco reserved register.
+#define DBG_REG_DBG_DRIVER_TRIGGER                                                                           0x010abcUL //Access:RW   DataWidth:0x1    // Used for triggering on driver assertions. For example this can be used in Emulation when The driver identifies an error and write to the for triggerig purpose
+#define DBG_REG_CPU_MBIST_MEMCTRL_0_CNTRL_CMD_BB                                                             0x010ac0UL //Access:RW   DataWidth:0x5    // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.
+#define DBG_REG_CPU_MBIST_MEMCTRL_1_CNTRL_CMD_BB                                                             0x010ac4UL //Access:RW   DataWidth:0x5    // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.
+#define DBG_REG_CPU_MBIST_MEMCTRL_2_CNTRL_CMD_BB                                                             0x010ac8UL //Access:RW   DataWidth:0x5    // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.
+#define DBG_REG_CPU_MBIST_MEMCTRL_3_CNTRL_CMD_BB                                                             0x010accUL //Access:RW   DataWidth:0x5    // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.
+#define DBG_REG_CPU_MBIST_MEMCTRL_4_CNTRL_CMD_BB                                                             0x010ad0UL //Access:RW   DataWidth:0x5    // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.
+#define DBG_REG_CPU_MBIST_MEMCTRL_5_CNTRL_CMD_BB                                                             0x010ad4UL //Access:RW   DataWidth:0x5    // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.
+#define DBG_REG_CPU_MBIST_MEMCTRL_6_CNTRL_CMD_BB                                                             0x010ad8UL //Access:RW   DataWidth:0x5    // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.
+#define DBG_REG_CPU_MBIST_MEMCTRL_7_CNTRL_CMD_BB                                                             0x010adcUL //Access:RW   DataWidth:0x5    // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.
+#define DBG_REG_CPU_MBIST_MEMCTRL_8_CNTRL_CMD_BB                                                             0x010ae0UL //Access:RW   DataWidth:0x5    // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.
+#define DBG_REG_CPU_MBIST_MEMCTRL_9_CNTRL_CMD_BB                                                             0x010ae4UL //Access:RW   DataWidth:0x5    // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.
+#define DBG_REG_HW_ID_NUM                                                                                    0x010b10UL //Access:RW   DataWidth:0x18   // ID number for each HW block that will be added to trailer when HW block is selected: [2:0]   - bits[31:0]; [5:3]   - bits[63:32]; [8:6]   - bits[95:64]; [11:9]  - bits[127:96]; [14:12] - bits[159:128]; [17:15] - bits[191:160]; [20:18] - bits[223:192]; [23:21] - bits[255:224];
+#define DBG_REG_STORM_ID_NUM                                                                                 0x010b14UL //Access:RW   DataWidth:0x12   // ID number for each STORM that will be added to trailer when STORM will be selected: B2:0 - TSEM; B5:3- MSEM; B8:6- USEM; B11:9- XSEM; B14:12 is YSEM; B17:15 is PSEM.
+#define DBG_REG_ETHERNET_HDR_0                                                                               0x010b18UL //Access:RW   DataWidth:0x20   // Ethernet header . Its size depends os ethernet_hdr_width register.
+#define DBG_REG_ETHERNET_HDR_1                                                                               0x010b1cUL //Access:RW   DataWidth:0x20   // Ethernet header . Its size depends os ethernet_hdr_width register.
+#define DBG_REG_ETHERNET_HDR_2                                                                               0x010b20UL //Access:RW   DataWidth:0x20   // Ethernet header . Its size depends os ethernet_hdr_width register.
+#define DBG_REG_ETHERNET_HDR_3                                                                               0x010b24UL //Access:RW   DataWidth:0x20   // Ethernet header . Its size depends os ethernet_hdr_width register.
+#define DBG_REG_ETHERNET_HDR_4                                                                               0x010b28UL //Access:RW   DataWidth:0x20   // Ethernet header . Its size depends os ethernet_hdr_width register.
+#define DBG_REG_ETHERNET_HDR_5                                                                               0x010b2cUL //Access:RW   DataWidth:0x20   // Ethernet header . Its size depends os ethernet_hdr_width register.
+#define DBG_REG_ETHERNET_HDR_6                                                                               0x010b30UL //Access:RW   DataWidth:0x20   // Ethernet header . Its size depends os ethernet_hdr_width register.
+#define DBG_REG_ETHERNET_HDR_7                                                                               0x010b34UL //Access:RW   DataWidth:0x20   // Ethernet header . Its size depends os ethernet_hdr_width register.
+#define DBG_REG_ETHERNET_HDR_WIDTH                                                                           0x010b38UL //Access:RW   DataWidth:0x4    // Ethernet header width: 0 - 14 MSB bytes; 1- 16 MSB bytes; .. ; 8 - 30 MSB bytes; 9 -32 MSB bytes. Values 10-15 are not supported.
+#define DBG_REG_TARGET_PACKET_SIZE                                                                           0x010b3cUL //Access:RW   DataWidth:0x6    // The packet size to NIG or PXP target is in granularity of chunks. The allowed range is 1-48 that suits to packet size of 256B-12KB. Values 49-63 are unused.
+#define DBG_REG_NW_PACKET_COUNTER_EN                                                                         0x010b40UL //Access:RW   DataWidth:0x1    // When 1 enables inserting packet counter at the output to NIG between Ethernet header and data.
+#define DBG_REG_NW_PACKET_COUNTER_STATUS                                                                     0x010b44UL //Access:R    DataWidth:0x10   // Packet counter value. Contains number of packets that were sent to NIG.
+#define DBG_REG_NW_PACKET_OVERFLOW_COUNTER                                                                   0x010b48UL //Access:RC   DataWidth:0x10   // Number of overflows for nw_packet_counter. Should stuck on all ones.
+#define DBG_REG_TIMESTAMP                                                                                    0x010b4cUL //Access:RW   DataWidth:0x20   // Timestamp value. This counter will be incremented when tick counter reaches timestamp_tick value. It may be reset from RBC or set to any init value. This counter starts to count immediately after reset.
+#define DBG_REG_TIMESTAMP_TICK                                                                               0x010b50UL //Access:RW   DataWidth:0x20   // Timestamp tick value.
+#define DBG_REG_TIMESTAMP_FRAME_EN                                                                           0x010b54UL //Access:RW   DataWidth:0x7    // Timestamp frame enable. This register enables inserting when bit[0] is set and frame[1] is set or bit[1] is set and frame[2] is set or bit[2] is set and frame[3] is set or bit[3] is set and frame[4] is set or bit[4] is set and frame[5] is set or bit[5] is set and frame[6] is set or bit[6] is set and frame[7] is set.
+#define DBG_REG_TIMESTAMP_VALID_EN                                                                           0x010b58UL //Access:RW   DataWidth:0x7    // Timestamp valid enable. This register enables inserting timestamp to bits 31:0 when bit[0] is set and valid[1] is set or bit[1] is set and valid[2] is set or bit[2] is set and valid[3] is set or bit[3] is set and valid[4] is set or bit[4] is set and valid[5] is set or bit[5] is set and valid[6] is set or bit[6] is set and valid[7] is set.
+#define DBG_REG_TRIGGER_STALL_EN                                                                             0x010b5cUL //Access:RW   DataWidth:0x6    // Stall enable per SEM block. When set enable stall output from DBG to SEM block as result of trigger event: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;.
+#define DBG_REG_TRIGGER_STATUS_CUR_STATE                                                                     0x010b60UL //Access:R    DataWidth:0x2    // Current state machine status of trigger block in dbg_trigger.v: states 0-2 are functional state (comparsion is implemented on the constraints) ; state 3 is triggering event.
+#define DBG_REG_TRIGGER_STATUS_PAUSE_STATE                                                                   0x010b64UL //Access:R    DataWidth:0x2    // Pause state machine status of trigger block in dbg_trigger_state.v: : state 0 - NOT_HNDLR_MSG; state 1- FRST_HNDLR_MSG; state 2- SCND_HNDLR_MSG; state 3 - unused.
+#define DBG_REG_TRIGGER_STATUS_MATCH_COUNTER_SET0                                                            0x010b68UL //Access:R    DataWidth:0x10   // Counter for number of times set 0 appeared in current state in dbg_trigger_state.v.
+#define DBG_REG_TRIGGER_STATUS_MATCH_COUNTER_SET1                                                            0x010b6cUL //Access:R    DataWidth:0x10   // Counter for number of times set 1 appeared in current state in dbg_trigger_state.v.
+#define DBG_REG_TRIGGER_STATUS_MATCH_CNSTR                                                                   0x010b70UL //Access:R    DataWidth:0x8    // Statistics. Match constraint status. B0 - constraint 0 set0; B1 - constraint 1 set0; B2 - constraint 2 set0; B3 - constraint 3 set0; B4 - constraint 0 set1; B5 - constraint 1 set1; B6 - constraint 2 set1; B7 - constraint 3 set1.
+#define DBG_REG_TRIGGER_STATUS_CYCLE_CNT                                                                     0x010b74UL //Access:R    DataWidth:0x8    // Statistics. Cycle counter from beginning of message.
+#define DBG_REG_NUM_OF_CYCLES_SENT                                                                           0x010b78UL //Access:RC   DataWidth:0x20   // Debug only: These bits represent the total number of 128-bit cycles sent from the dbg block to output interface (NIG/PCI).
+#define DBG_REG_TRIGGER_STATUS_STATE_TRANSITIONS_0                                                           0x010b7cUL //Access:R    DataWidth:0x10   // Debug only: Number of transitions per state.
+#define DBG_REG_TRIGGER_STATUS_STATE_TRANSITIONS_1                                                           0x010b80UL //Access:R    DataWidth:0x10   // Debug only: Number of transitions per state.
+#define DBG_REG_TRIGGER_STATUS_STATE_TRANSITIONS_2                                                           0x010b84UL //Access:R    DataWidth:0x10   // Debug only: Number of transitions per state.
+#define DBG_REG_TRAILER_STATUS_CUR_STATE                                                                     0x010b88UL //Access:R    DataWidth:0x2    // Debug only: Current state status in trailer block : 0 - WAIT_FOR_NEW_LINE; 1- END_OF_CHUNK; 2 - SEND_ADDITIONAL_CHUNK; 3 - SEND_ADDITIONAL_LINE.
+#define DBG_REG_TRAILER_STATUS_VALID_DWORDS                                                                  0x010b8cUL //Access:R    DataWidth:0x6    // Debug only: number of valid dwords in trailer block.
+#define DBG_REG_FILTER_STATUS_MATCH_CNSTR                                                                    0x010b90UL //Access:R    DataWidth:0x4    // Statistics. Match constraint status. B0 - constraint 0; B1 - constraint 1; B2 - constraint 2 ; B3 - constraint 3.
+#define DBG_REG_MEMCTRL_WR_RD_N_BB                                                                           0x010b94UL //Access:RW   DataWidth:0x1    // wr/rd indication to CPU BIST
+#define DBG_REG_MEMCTRL_CMD_BB                                                                               0x010b98UL //Access:RW   DataWidth:0x8    // command to CPU BIST
+#define DBG_REG_MEMCTRL_ADDRESS_BB                                                                           0x010b9cUL //Access:RW   DataWidth:0x8    // address to CPU BIST
+#define DBG_REG_MEMCTRL_STATUS                                                                               0x010ba0UL //Access:R    DataWidth:0x20   // status from CPU BIST
+#define DBG_REG_NUM_OF_EMPTY_LINES_IN_INT_BUFFER                                                             0x010ba4UL //Access:R    DataWidth:0x8    // Number of empty lines in internal buffer.
+#define DBG_REG_FILTER_MODE_E5                                                                               0x010ba8UL //Access:RW   DataWidth:0x1    // When set to 0 - only client which HW ID is defined in DBG_REGISTERS_FILTER_ID_NUM.FILTER_ID_NUM is logged. When set to 1 - the client which HW ID is defined in DBG_REGISTERS_FILTER_ID_NUM.FILTER_ID_NUM is filtered, while other clients are passed as as is without filtering.
+#define DBG_REG_INTR_BUFFER                                                                                  0x014000UL //Access:WB   DataWidth:0x200  // Debug only:  Internal buffer of 12KByte buffer.
+#define DBG_REG_INTR_BUFFER_SIZE                                                                             3072
+#define IPC_REG_PLL_MAIN_DIVR_K2_E5                                                                          0x020200UL //Access:RW   DataWidth:0x6    // PLLLOUT = REF / DIVR_Value * DIVF_Value * 2 / DIVQ_Value Reference divider value
+#define IPC_REG_MDIO_VOLTAGE_SEL_BB                                                                          0x020200UL //Access:RW   DataWidth:0x1    // Select line for MDIO Voltage Select 0 : MDIO VDDIO is 1.8V or below. 1 : MDIO VDDIO is 1.8+V or above.
+#define IPC_REG_PLL_MAIN_DIVF_K2_E5                                                                          0x020204UL //Access:RW   DataWidth:0x9    // Feedback divider value
+#define IPC_REG_CPU_OTP_CTRL1_BB                                                                             0x020204UL //Access:RW   DataWidth:0x20   // [0]: cpu_cmd_wr_en: A rising edge of this bit will execute the OTP "command" in the next field.  This bit should be set to Low and high again for the next command execution to start; [5:1]: Command: 0: Read; 1: OTP_ProgEnable (OTP must be put in ProgEnable mode by writing 0xF; 0x4; 0x8; 0xD in sequence with OTP_ProgEnable command before you do any actual  write to OTP. Sequence Data is taken from bitsel bus and therefore word_address and wdata do not play any role during this authentication process; 2: OTP_ProgDisable (Disable OTP with this command once you are done with programming); 3: Verify( vsel and tm are used from control bits); 4: Init (vsel and tm are used from strap module); 5: lock_cmd. used to program the lock bits that can not be programmed by using  regular program bit and program Word cmd. OTP word address 6 and 7 are allocated for lock bits and to program these bits lock command must be used; 6: stby (Not used in this IP); 7: wakeup (Not used in this IP); 9: Prescreen test. Upon getting a prescrn_cmd; word_addr; and bit_sel; otp_controller keeps reading(simple read) the OTP MEMORY SPACE until it reaches the max word_addr or it finds any programmed bit; 10: Program Bit; 11: Program Word; 12: burnin. Upon getting a burnin_cmd; word_addr; and bit_sel; otp_controller keeps reading(simple read) the OTP MEMORY SPACE. It keeps looping until the cmd is changed from burnin to something else; 13: auto_reload; 14: ovst_read; 15: ovst_prog; [17:6]: Address; [18]: cpu_mode: When set, enables command execution through this cpu interface; [19]: cpu_disable_otp_access: When set, disables any command execution through this cpu interface. [31:20]: RESERVED;
+#define IPC_REG_PLL_MAIN_DIVQ_K2_E5                                                                          0x020208UL //Access:RW   DataWidth:0x3    // output divider value, 2^binary value
+#define IPC_REG_CPU_OTP_STATUS_BB                                                                            0x020208UL //Access:R    DataWidth:0x20   // [0]: data_valid: This bit is used to sample READ data in burst mode; [1]: cmd_done: Command Done, This signal indicates the completion of the command; [2]: progok: Program OK, This signal is set when PROG ENABLE sequence is issued correctly; [3]: fdone: This signal is set when fout bits are loaded; [4]: cmd_fail: Command Failure, This bit is set when locked address is accessed using program related commands; [5]: refok: OTP RefOK signal; [6]: debug_mode_set: This bit is set when ctrl_wr_cmd is issued; [7]: mst_fsm_error: An illegal state has executed. This bit is set to '0' in idle state, otherwise '1' in all other states; [8]: debug_mode: This bit is set using ctrl_wr command and indicates the debug mode option; [9]: invalid_addr: This bit is set when Locked address is accessed by program related commands or when address is out of range; [10]: prog_word_fail: This bit is set when Programming fails for a bit during word program; [11]: prog_screen_fail: This bit is set when screening fails for word programming. [12]: prog_block_cmd: Invalid for CPU mode; [13]: prog_en: By default this is set to enable PROG command; [14]: prgm_wd_rp_fail: TBD; [15]: max_rw: TBD; [16]: max_rwp: TBD; [17]: auto_rw_max_set: TBD; [18]: max_sw: TBD; [19]: addr_in_illegal_range: TBD; [31:20]: Reserved;
+#define IPC_REG_PLL_MAIN_RANGE_K2_E5                                                                         0x02020cUL //Access:RW   DataWidth:0x3    // PLL Filter Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 011 = 18-30MHz 111 = 130-200MHz
+#define IPC_REG_CPU_OTP_WRITE_DATA_BB                                                                        0x02020cUL //Access:RW   DataWidth:0x20   // Used to provide write data with burst write command from CPU side.
+#define IPC_REG_PLL_MAIN_BYPASS_K2_E5                                                                        0x020210UL //Access:RW   DataWidth:0x1    // pll bypass signal
+#define IPC_REG_CPU_OTP_READ_DATA_BB                                                                         0x020210UL //Access:R    DataWidth:0x20   // Data output from the OTP read data command.
+#define IPC_REG_PLL_MAIN_LOCK_K2_E5                                                                          0x020214UL //Access:R    DataWidth:0x1    // pll lock signal
+#define IPC_REG_OSC_E28_XCORE_BIAS_BB                                                                        0x020214UL //Access:RW   DataWidth:0x4    // XTAL core current control 4'b0010: 27Mhz 4'b0100: 50Mhz Device will be using 50Mhz crytal, so defaults to a value of 4. Global Register, Reset on POR
+#define IPC_REG_PLL_MAIN_LOCK_DETECT_FILTER_STATUS_K2_E5                                                     0x020218UL //Access:R    DataWidth:0x1    // pll lock detected filter status
+#define IPC_REG_OSC_E28_XCORE_BIAS_OVERRIDE_BB                                                               0x020218UL //Access:RW   DataWidth:0x1    // XCORE_BIAS in normal operation is controlled by straps on the board. This bit allows it SW to override the setting based on register osc_e28_xcore_bias Global Register, Reset on POR
+#define IPC_REG_PLL_MAIN_NEWDIV_K2_E5                                                                        0x02021cUL //Access:RW   DataWidth:0x1    // Divider input control
+#define IPC_REG_OSC_E28_HIPASS_BB                                                                            0x02021cUL //Access:RW   DataWidth:0x1    // XTAL core Highpass Filter Corner Frequency control 0: 27Mhz 1: 50Mhz Device will be using 50Mhz crytal, so defaults to a value of 1. Global Register, Reset on POR
+#define IPC_REG_PLL_MAIN_DIVACK_K2_E5                                                                        0x020220UL //Access:R    DataWidth:0x1    // Divider handshake signal
+#define IPC_REG_OSC_E28_HIPASS_OVERRIDE_BB                                                                   0x020220UL //Access:RW   DataWidth:0x1    // HIPASS in normal operation is controlled by straps on the board. This bit allows it SW to override the setting based on register osc_e28_hipass Global Register, Reset on POR
+#define IPC_REG_PLL_MAIN_RESET_K2_E5                                                                         0x020224UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define IPC_REG_PLL_MAIN_RESET_PLL_MAIN_RESET_K2_E5                                                        (0x1<<0) // 1 : Reset the PLL. The reset is active high.
+  #define IPC_REG_PLL_MAIN_RESET_PLL_MAIN_RESET_K2_E5_SHIFT                                                  0
+  #define IPC_REG_PLL_MAIN_RESET_OVERRIDE_K2_E5                                                              (0x1<<4) // 1 : Override the init state machine and control the PLL reset using bit[0] of the register.
+  #define IPC_REG_PLL_MAIN_RESET_OVERRIDE_K2_E5_SHIFT                                                        4
+#define IPC_REG_OSC_E28_D2C_BIAS_BB                                                                          0x020224UL //Access:RW   DataWidth:0x3    // D2C Bias Current Control Global Register, Reset on POR
+#define IPC_REG_PLL_MAIN_LOCK_DETECT_FILTER_STATUS_WAS_CLEARED_K2_E5                                         0x020228UL //Access:RW   DataWidth:0x1    // Used for debug, will be set when pll_lock_detect_filter_status went from 1 to 0. This scenario shouldn't happen in normal cases.
+#define IPC_REG_OSC_E28_CML_CUR_BB                                                                           0x020228UL //Access:RW   DataWidth:0x1    // CML Current Control Global Register, Reset on POR
+#define IPC_REG_PLL_NWM_DIVR_K2_E5                                                                           0x02022cUL //Access:RW   DataWidth:0x6    // PLLLOUT = REF / DIVR_Value * DIVF_Value * 2 / DIVQ_Value Reference divider value
+#define IPC_REG_OSC_E28_DRV_CUR_BB                                                                           0x02022cUL //Access:RW   DataWidth:0x2    // 50ohm Driver Current Control 00 = 5mA 01 = 10mA 10 = 15mA 11 = 20mA Global Register, Reset on POR
+#define IPC_REG_PLL_NWM_DIVF_K2_E5                                                                           0x020230UL //Access:RW   DataWidth:0x9    // Feedback divider value
+#define IPC_REG_OSC_E28_DIV2_SEL_BB                                                                          0x020230UL //Access:RW   DataWidth:0x1    // Divide by 2 Selection for pad_op/n_cml output 0=XTAL Freq. 1=XTAL Freq. / 2 Global Register, Reset on POR
+#define IPC_REG_PLL_NWM_DIVQ_K2_E5                                                                           0x020234UL //Access:RW   DataWidth:0x3    // output divider value, 2^binary value
+#define IPC_REG_OSC_E28_LDO_CTRL_BB                                                                          0x020234UL //Access:RW   DataWidth:0x4    // [3:2] LDO Output Stage Bias Control [1:0] LDO Output Voltage Level Control 00 = 1.05V 01 = 1.00V 10 = 0.95V 11 = 0.90V Global Register, Reset on POR
+#define IPC_REG_PLL_NWM_RANGE_K2_E5                                                                          0x020238UL //Access:RW   DataWidth:0x3    // PLL Filter Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 011 = 18-30MHz 111 = 130-200MHz
+#define IPC_REG_OSC_E28_CMOS_EN_ALL_BB                                                                       0x020238UL //Access:RW   DataWidth:0x1    // ENABLE All CMOS Outputs 0=o_xtal_ck[5:0] depends on i_resetb and i_cmos_en_ch[5:0] 1=o_xtal_ck[5:0] ALL ON Global Register, Reset on POR
+#define IPC_REG_PLL_NWM_RESET_K2_E5                                                                          0x02023cUL //Access:RW   DataWidth:0x1    // pll reset signal
+#define IPC_REG_OSC_E28_CMOS_EN_CH_BB                                                                        0x02023cUL //Access:RW   DataWidth:0x6    // Enable for CMOS outputs 0=CMOS output DISABLED 1=CMOS output ENABLED Bit[0] = o_xtal_ck0 Bit[1] = o_xtal_ck1 Bit[2] = o_xtal_ck2 Bit[3] = o_xtal_ck3 Bit[4] = o_xtal_ck4 Bit[5] = o_xtal_ck5 Global Register, Reset on POR
+#define IPC_REG_PLL_NWM_BYPASS_K2_E5                                                                         0x020240UL //Access:RW   DataWidth:0x1    // pll bypass signal
+#define IPC_REG_OSC_E28_CML_EN_CH_BB                                                                         0x020240UL //Access:RW   DataWidth:0x4    // CML Output Channel Power Down 0=CML output ON 1=CML output OFF Bit[0] = o_cml_p/n 0 Bit[1] = o_cml_p/n 1 Bit[2] = o_cml_p/n 2 Bit[3] = o_cml_p/n 3 Global Register, Reset on POR
+#define IPC_REG_PLL_NWM_LOCK_K2_E5                                                                           0x020244UL //Access:R    DataWidth:0x1    // pll lock signal
+#define IPC_REG_OSC_E28_PD_DRV_BB                                                                            0x020244UL //Access:RW   DataWidth:0x1    // 50ohm Driver Power Down 0=Driver ENABLED 1=Driver DISABLED Global Register, Reset on POR
+#define IPC_REG_PLL_NWM_LOCK_DETECT_FILTER_STATUS_K2_E5                                                      0x020248UL //Access:R    DataWidth:0x1    // pll lock detected filter status
+#define IPC_REG_OSC_E28_MISC_BB                                                                              0x020248UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define IPC_REG_OSC_E28_MISC_OSC_E28_POWER_SAVE_BB                                                         (0x1<<0) // Future Use
+  #define IPC_REG_OSC_E28_MISC_OSC_E28_POWER_SAVE_BB_SHIFT                                                   0
+  #define IPC_REG_OSC_E28_MISC_OSC_E28_BIAS_BB                                                               (0x7<<1) // Future Use
+  #define IPC_REG_OSC_E28_MISC_OSC_E28_BIAS_BB_SHIFT                                                         1
+  #define IPC_REG_OSC_E28_MISC_OSC_E28_XCORE_CM_SEL_BB                                                       (0x1<<4) // Future Use
+  #define IPC_REG_OSC_E28_MISC_OSC_E28_XCORE_CM_SEL_BB_SHIFT                                                 4
+#define IPC_REG_PLL_NWM_NEWDIV_K2_E5                                                                         0x02024cUL //Access:RW   DataWidth:0x1    // Divider input control
+#define IPC_REG_PLL_MAIN_E28_PWRDN_BB                                                                        0x02024cUL //Access:RW   DataWidth:0x1    // PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR
+#define IPC_REG_PLL_NWM_DIVACK_K2_E5                                                                         0x020250UL //Access:R    DataWidth:0x1    // Divider handshake signal
+#define IPC_REG_PLL_MAIN_E28_RESET_VCO_BB                                                                    0x020250UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define IPC_REG_PLL_MAIN_E28_RESET_VCO_PLL_MAIN_RESET_VCO_BB                                               (0x1<<0) // 1 : Reset the VCO of the PLL. The reset is active high. Global Register, Reset on POR
+  #define IPC_REG_PLL_MAIN_E28_RESET_VCO_PLL_MAIN_RESET_VCO_BB_SHIFT                                         0
+  #define IPC_REG_PLL_MAIN_E28_RESET_VCO_PLL_MAIN_RESET_VCO_OVERRIDE_BB                                      (0x1<<4) // 1 : Override the init state machine and control the PLL reset using bit[0] of the register.
+  #define IPC_REG_PLL_MAIN_E28_RESET_VCO_PLL_MAIN_RESET_VCO_OVERRIDE_BB_SHIFT                                4
+#define IPC_REG_PLL_NWM_LOCK_DETECT_FILTER_STATUS_WAS_CLEARED_K2_E5                                          0x020254UL //Access:RW   DataWidth:0x1    // Used for debug, will be set when pll_lock_detect_filter_status went from 1 to 0. This scenario shouldn't happen in normal cases.
+#define IPC_REG_PLL_MAIN_E28_RESET_POST_BB                                                                   0x020254UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define IPC_REG_PLL_MAIN_E28_RESET_POST_PLL_MAIN_RESET_POST_BB                                             (0x1<<0) // 1 : Reset the Post Divider of the PLL. The reset is active high. Global Register, Reset on POR
+  #define IPC_REG_PLL_MAIN_E28_RESET_POST_PLL_MAIN_RESET_POST_BB_SHIFT                                       0
+  #define IPC_REG_PLL_MAIN_E28_RESET_POST_PLL_MAIN_RESET_POST_OVERRIDE_BB                                    (0x1<<4) // 1 : Override the init state machine and control the PLL reset using bit[0] of the register.
+  #define IPC_REG_PLL_MAIN_E28_RESET_POST_PLL_MAIN_RESET_POST_OVERRIDE_BB_SHIFT                              4
+#define IPC_REG_PLL_STORM_DIVR_K2_E5                                                                         0x020258UL //Access:RW   DataWidth:0x6    // PLLLOUT = REF / DIVR_Value * DIVF_Value * 2 / DIVQ_Value Reference divider value
+#define IPC_REG_PLL_MAIN_E28_PDIV_BB                                                                         0x020258UL //Access:RW   DataWidth:0x4    // Input reference clock pre-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= divide-by-4 0101= divide-by-5 0110= divide-by-6 0111= divide-by-7 1111 = divide-by-15 Global register. Reset on POR reset.
+#define IPC_REG_PLL_STORM_DIVF_K2_E5                                                                         0x02025cUL //Access:RW   DataWidth:0x9    // Feedback divider value
+#define IPC_REG_PLL_MAIN_E28_NDIV_INT_BB                                                                     0x02025cUL //Access:RW   DataWidth:0xa    // Feedback divider control 0000000000= divide-by-1024 0000000001= XXX 0000000010= XXX : 0000001011= XXX 0000001100= divide-by-12 0000001101= divide-by-13 0000001110= divide-by-14 : 1111111110= divide-by-1022 1111111111= divide-by-1023 Global register. Reset on POR reset.
+#define IPC_REG_PLL_STORM_DIVQ_K2_E5                                                                         0x020260UL //Access:RW   DataWidth:0x3    // output divider value, 2^binary value
+#define IPC_REG_PLL_MAIN_E28_NDIV_FRAC_BB                                                                    0x020260UL //Access:RW   DataWidth:0x14   // Fractional feedback divider control. Resolution= 1/(2^20). Global register. Reset on POR reset.
+#define IPC_REG_PLL_STORM_RANGE_K2_E5                                                                        0x020264UL //Access:RW   DataWidth:0x3    // PLL Filter Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 011 = 18-30MHz 111 = 130-200MHz
+#define IPC_REG_PLL_MAIN_E28_CH0_MDIV_BB                                                                     0x020264UL //Access:RW   DataWidth:0x8    // Post-divider ratio for channel-0 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset.
+#define IPC_REG_PLL_STORM_RESET_K2_E5                                                                        0x020268UL //Access:RW   DataWidth:0x1    // pll reset signal
+#define IPC_REG_PLL_MAIN_E28_CH1_MDIV_BB                                                                     0x020268UL //Access:RW   DataWidth:0x8    // Post-divider ratio for channel-1 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset.
+#define IPC_REG_PLL_STORM_BYPASS_K2_E5                                                                       0x02026cUL //Access:RW   DataWidth:0x1    // pll bypass signal
+#define IPC_REG_PLL_MAIN_E28_CH2_MDIV_BB                                                                     0x02026cUL //Access:RW   DataWidth:0x8    // Post-divider ratio for channel-2 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset.
+#define IPC_REG_PLL_STORM_LOCK_K2_E5                                                                         0x020270UL //Access:R    DataWidth:0x1    // pll lock signal
+#define IPC_REG_PLL_MAIN_E28_CH3_MDIV_BB                                                                     0x020270UL //Access:RW   DataWidth:0x8    // Post-divider ratio for channel-3 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset.
+#define IPC_REG_PLL_STORM_LOCK_DETECT_FILTER_STATUS_K2_E5                                                    0x020274UL //Access:R    DataWidth:0x1    // pll lock detected filter status
+#define IPC_REG_PLL_MAIN_E28_CH4_MDIV_BB                                                                     0x020274UL //Access:RW   DataWidth:0x8    // Post-divider ratio for channel-4 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset.
+#define IPC_REG_PLL_STORM_NEWDIV_K2_E5                                                                       0x020278UL //Access:RW   DataWidth:0x1    // Divider input control
+#define IPC_REG_PLL_MAIN_E28_CH5_MDIV_BB                                                                     0x020278UL //Access:RW   DataWidth:0x8    // Post-divider ratio for channel-5 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset.
+#define IPC_REG_PLL_STORM_DIVACK_K2_E5                                                                       0x02027cUL //Access:R    DataWidth:0x1    // Divider handshake signal
+#define IPC_REG_PLL_MAIN_E28_CH2_MDEL_BB                                                                     0x02027cUL //Access:RW   DataWidth:0x10   // Number to VCO clock to delay Channel 2 Global register. Reset on POR reset.
+#define IPC_REG_PLL_STORM_LOCK_DETECT_FILTER_STATUS_WAS_CLEARED_K2_E5                                        0x020280UL //Access:RW   DataWidth:0x1    // Used for debug, will be set when pll_lock_detect_filter_status went from 1 to 0. This scenario shouldn't happen in normal cases.
+#define IPC_REG_PLL_MAIN_E28_CH3_MDEL_BB                                                                     0x020280UL //Access:RW   DataWidth:0x10   // Number to VCO clock to delay Channel 3 Global register. Reset on POR reset.
+#define IPC_REG_MDIO_MODE_BB                                                                                 0x020494UL //Access:RW   DataWidth:0x16   // [21:12] -> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency equal to CORE_CLK/(2*(CLOCK_CNT+1)). A value of 0 is invalid for this register. [11] -> MDC Setting this bit to '1' will cause the MDC pin to high if the BIT_BANG bit is set. . Setting this pin low will cause the MDC pin to drive low if the BIT_BANG bit is set. [10] -> MDIO_OE Setting this bit to '1' will cause the MDIO pin to drive the value written to the MDIO bit if the BIT_BANG bit is set. Setting this bit to zero will make the MDIO pin an input. [9] -> MDIO The write value of this bit controls the drive state of the MDIO pin if the BIT_BANG bit is set. The read value of this bit always reflects the state of the MDIO pin. [8] -> BIT_BANG If this bit is '1', the MDIO interface is controlled by the MDIO, MDIO_OE, and MDC bits in this register. When this bit is '0', the commands in the mdio_cmd register will be executed. [0] -> FREE_DIS 1 -> Diable Free running MDIO clock All other field in the register are reserved
+#define IPC_REG_MDIO_MODE_K2_E5                                                                              0x020284UL //Access:RW   DataWidth:0x16   // [21:12] -> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency equal to CORE_CLK/(2*(CLOCK_CNT+1)). A value of 0 is invalid for this register. [11] -> MDC Setting this bit to '1' will cause the MDC pin to high if the BIT_BANG bit is set. . Setting this pin low will cause the MDC pin to drive low if the BIT_BANG bit is set. [10] -> MDIO_OE Setting this bit to '1' will cause the MDIO pin to drive the value written to the MDIO bit if the BIT_BANG bit is set. Setting this bit to zero will make the MDIO pin an input. [9] -> MDIO The write value of this bit controls the drive state of the MDIO pin if the BIT_BANG bit is set. The read value of this bit always reflects the state of the MDIO pin. [8] -> BIT_BANG If this bit is '1', the MDIO interface is controlled by the MDIO, MDIO_OE, and MDC bits in this register. When this bit is '0', the commands in the mdio_cmd register will be executed. [7:4] RESERVED [3] -> CLAUSE_45/CLAUSE_22 1 -> clause 45 mode 0 -> clause 22 mode [2] -> AUTO_POLL(not verified feature) Setting this bit to 1 will enable the auto poll mode which will constantly read from a specified register address 1. clause 22 the register address is always 1 and the phy addr is programable. Clause 45 the register address is always 1 and the deivce type and phy_addr are configurable [1] -> SHORT_PREAMBLE(not verified feature) setting this bit will cancell the preamble frame of 32 consecutive 1s [0] -> FREE_DIS(not verified feature) 1 -> Disable Free running MDIO clock
+#define IPC_REG_PLL_MAIN_E28_CH4_MDEL_BB                                                                     0x020284UL //Access:RW   DataWidth:0x10   // Number to VCO clock to delay Channel 4 Global register. Reset on POR reset.
+#define IPC_REG_MDIO_COMM_BB                                                                                 0x02048cUL //Access:RW   DataWidth:0x1e   // [29] -> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO transaction will activate. When the operation is complete, this bit will clear and the MI_COMPLETE bit will be set in the status register. Writing this bit as a '0' has no effect. This bit must be read as a '0' before setting to prevent un-predictable results. [28] -> FAIL This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction. [27:26] -> COMMAND 1 -> Write 2 -> Read [25:21] -> PHY_ADDR This value is used to define the PHY address portion of the MDIO transaction 1 -> SWREG VMGMT 2 -> SWREG VMAIN 3 -> SWREG VANALOG 4 -> SWREG V1p8 [20:16] -> REG_ADDR This value is used to define the register address portion of the MDIO transaction [15:0]  -> DATA When this register is read, it returns the results of the last MDIO transaction that was performed. When this register value is written, it updates the value that will be used on the next MDIO write transaction that will be performed.
+#define IPC_REG_MDIO_COMM_K2_E5                                                                              0x020288UL //Access:RW   DataWidth:0x1e   // [29] -> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO transaction will activate. When the operation is complete, this bit will clear and the MI_COMPLETE bit will be set in the status register. Writing this bit as a '0' has no effect. This bit must be read as a '0' before setting to prevent un-predictable results. [28] -> FAIL This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction. [27:26] -> COMMAND 00 -> clause 45 address 01 -> Write 10 -> clause 22 Read, clause 45 read_inc 11 -> clause 45 Read [25:21] -> PHY_ADDR This value is used to define the PHY address portion of the MDIO transaction. [20:16] -> REG_ADDR clause 22 - This value is used to define the register address portion of the MDIO transaction. clause 45 - This value is used to define the device type portion of the MDIO transaction. [15:0]  -> DATA Clause 22: When this register is read, it returns the results of the last MDIO transaction that was performed. When this register value is written, it updates the value that will be used on the next MDIO write transaction that will be performed. Clause 45: for the first frame, this register contain the adsress of the command. for the second frame, it returns the results of the last MDIO transaction that was performed for read operation or the data to be written for write operation.
+#define IPC_REG_PLL_MAIN_E28_CH5_MDEL_BB                                                                     0x020288UL //Access:RW   DataWidth:0x10   // Number to VCO clock to delay Channel 5 Global register. Reset on POR reset.
+#define IPC_REG_MDIO_STATUS_BB                                                                               0x020490UL //Access:R    DataWidth:0x2    // [0] -> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the next transaction starts. [1] -> FAIL This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction.
+#define IPC_REG_MDIO_STATUS_K2_E5                                                                            0x02028cUL //Access:R    DataWidth:0x2    // [0] -> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the next transaction starts. [1] -> FAIL This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction.
+#define IPC_REG_PLL_MAIN_E28_CH_DELAY_DONE_BB                                                                0x02028cUL //Access:R    DataWidth:0x4    // Delay for each channel 2-5 is completed.
+#define IPC_REG_SGMII_MDIO_ADDR_K2_E5                                                                        0x020290UL //Access:RW   DataWidth:0x5    // PHY Address for MDIO Transaction
+#define IPC_REG_PLL_MAIN_E28_CH_ENABLEB_BB                                                                   0x020290UL //Access:RW   DataWidth:0x6    // Active Low Channel Enable. Global register. Reset on POR reset.
+#define IPC_REG_SGMII_RSTB_MDIOREGS_K2_E5                                                                    0x020294UL //Access:RW   DataWidth:0x1    // reset of sgmii mdio registers. This is an active high reset. The name "rstb" is mistakenly suggest an active low reset.
+#define IPC_REG_PLL_MAIN_E28_CTRL_0_BB                                                                       0x020294UL //Access:RW   DataWidth:0x20   // PLL Control Register [11:0] dco_ctrl_bypass[11:0] direct programming of DAC: 00...00 = MIN VCO clock frequency : 11...11 = MAX VCO clock frequency [12] dco_ctrl_bypass_enable enable of direct programming of DAC: 0 =normal mode 1 =DAC programming mode [13] stat_reset reset of phase error measurement: 0 =normal mode 1 =reset [16:14] stat_select[2:0] select of test output: 000 = 000000000000 001 = minimum phase error 010 = maximum phase error 011 = lock_state 100 = dac control word 101 = 000000000000 110 = 000000000000 111 = 000000000000 [17] stat_update On the synchronized rising edge of this control signal the value selected by stat_select[2:0] is clocked into o_statout [19:18] Reserved [21:20] Stat_mode[1:0] Statistics Mode 00 = disabled 01 = phase error stats 10 : period stats 11 : Feedback phase error stats [23:22] Pwm_rate[1:0] Set PWM rate Vco_fb_div2 == 0 00 = 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for VCO gt 800MHz 10 for VCO lt 800MHz [25:24] post_resetb select post channel resetb selection 00 = lock or post_resetb 01 = flock or post_resetb 10 = resetb or post_resetb 11 = post_resetb [26] vco_fb_div2 Divide vco_fdbk clock by 2 0= vco clock 1=vco/2 clock 0 for VCO lt 2.0GHz 1 for VCO gt 2.0GHz [27] fast_lock Reduces the number of refclk cycles of delay between frequency lock and setting o_lock output high. 0 = 256 refclk delay 1 = 32 refclk delay [28] ndiv_relock Forces lock state machine to return to frequency acquisition state when ndiv_int/ndiv_frac changes. 0 = Loop responds to ndiv change. May or may not switch back to frequency acquisition mode. 1 = Re-enter frequency acquisition state, without resetting the initial frequency (starts from current frequency). This produces smoother transition to new frequency for steps greater than 1 percent [29] Reserved [31:30] Vco_range Set VCO frequency range 00 = 800 - 2000 MHz 01 = 500 - 1200 MHz 10 = 1600 - 4000 MHz [33:32] LDO[1:0] LDO output voltage control 00 = 1.05 V 01 = 1.00 V 10 = 0.95 V 11 = 0.90 V [34] testout_en Test output buffer enable 0= normal mode 1= test output buffer enable [37:35] testout_sel Test output clock selection 000 = no clock 001 = o_fref 010 = o_clkout[0] 011 = o_clkout[1] 100 = o_clkout[2] 101 = o_clkout[3] 110 = o_clkout[4] 111 = o_clkout[5] [63:38] Reserved
+#define IPC_REG_FREQ_CAPTURE_BB                                                                              0x0204a4UL //Access:W    DataWidth:0x1    // Setting this bit high will result in the HW to capture the frequency of Main, STORM and NW clocks. This is a self clearing bit.
+#define IPC_REG_FREQ_CAPTURE_K2_E5                                                                           0x020298UL //Access:W    DataWidth:0x1    // Setting this bit high will result in the HW to capture the frequency of Main, STORM and NWM clocks. This is a self clearing bit.
+#define IPC_REG_PLL_MAIN_E28_CTRL_1_BB                                                                       0x020298UL //Access:RW   DataWidth:0x20   // PLL Control Register [11:0] dco_ctrl_bypass[11:0] direct programming of DAC: 00...00 = MIN VCO clock frequency : 11...11 = MAX VCO clock frequency [12] dco_ctrl_bypass_enable enable of direct programming of DAC: 0 =normal mode 1 =DAC programming mode [13] stat_reset reset of phase error measurement: 0 =normal mode 1 =reset [16:14] stat_select[2:0] select of test output: 000 = 000000000000 001 = minimum phase error 010 = maximum phase error 011 = lock_state 100 = dac control word 101 = 000000000000 110 = 000000000000 111 = 000000000000 [17] stat_update On the synchronized rising edge of this control signal the value selected by stat_select[2:0] is clocked into o_statout [19:18] Reserved [21:20] Stat_mode[1:0] Statistics Mode 00 = disabled 01 = phase error stats 10 : period stats 11 : Feedback phase error stats [23:22] Pwm_rate[1:0] Set PWM rate Vco_fb_div2 == 0 00 = 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for VCO gt 800MHz 10 for VCO lt 800MHz [25:24] post_resetb select post channel resetb selection 00 = lock or post_resetb 01 = flock or post_resetb 10 = resetb or post_resetb 11 = post_resetb [26] vco_fb_div2 Divide vco_fdbk clock by 2 0= vco clock 1=vco/2 clock 0 for VCO lt 2.0GHz 1 for VCO gt 2.0GHz [27] fast_lock Reduces the number of refclk cycles of delay between frequency lock and setting o_lock output high. 0 = 256 refclk delay 1 = 32 refclk delay [28] ndiv_relock Forces lock state machine to return to frequency acquisition state when ndiv_int/ndiv_frac changes. 0 = Loop responds to ndiv change. May or may not switch back to frequency acquisition mode. 1 = Re-enter frequency acquisition state, without resetting the initial frequency (starts from current frequency). This produces smoother transition to new frequency for steps greater than 1 percent [29] Reserved [31:30] Vco_range Set VCO frequency range 00 = 800 - 2000 MHz 01 = 500 - 1200 MHz 10 = 1600 - 4000 MHz [33:32] LDO[1:0] LDO output voltage control 00 = 1.05 V 01 = 1.00 V 10 = 0.95 V 11 = 0.90 V [34] testout_en Test output buffer enable 0= normal mode 1= test output buffer enable [37:35] testout_sel Test output clock selection 000 = no clock 001 = o_fref 010 = o_clkout[0] 011 = o_clkout[1] 100 = o_clkout[2] 101 = o_clkout[3] 110 = o_clkout[4] 111 = o_clkout[5] [63:38] Reserved
+#define IPC_REG_FREQ_MAIN_BB                                                                                 0x0204a8UL //Access:R    DataWidth:0x11   // Multi Field Register.
+#define IPC_REG_FREQ_MAIN_K2_E5                                                                              0x02029cUL //Access:R    DataWidth:0x11   // Multi Field Register.
+  #define IPC_REG_FREQ_MAIN_CNT                                                                              (0xffff<<0) // This field shows the frequency counter for main clock over a 10uS interval. Main Clock Frequency = ~(FreqCnt / 10)MHz. This field is not reset between measurements. For example, it shows X MHz in first measurement, 2*X in second measurement, 3*X MHz in third measurement.
+  #define IPC_REG_FREQ_MAIN_CNT_SHIFT                                                                        0
+  #define IPC_REG_FREQ_MAIN_CNT_VALID                                                                        (0x1<<16) // 0: Value in freq_cnt field is not valid 1: Value in freq_cnt field is valid
+  #define IPC_REG_FREQ_MAIN_CNT_VALID_SHIFT                                                                  16
+#define IPC_REG_PLL_MAIN_E28_KA_BB                                                                           0x02029cUL //Access:RW   DataWidth:0x3    // Loop gain in frequency acquisition mode Global register. Reset on POR reset.
+#define IPC_REG_FREQ_STORM_BB                                                                                0x0204acUL //Access:R    DataWidth:0x11   // Multi Field Register.
+#define IPC_REG_FREQ_STORM_K2_E5                                                                             0x0202a0UL //Access:R    DataWidth:0x11   // Multi Field Register.
+  #define IPC_REG_FREQ_STORM_CNT                                                                             (0xffff<<0) // This field shows the frequency counter for main clock over a 10uS interval. Storm Clock Frequency = ~(FreqCnt / 10)MHz. This field is not reset between measurements. For example, it shows X MHz in first measurement, 2*X in second measurement, 3*X MHz in third measurement.
+  #define IPC_REG_FREQ_STORM_CNT_SHIFT                                                                       0
+  #define IPC_REG_FREQ_STORM_CNT_VALID                                                                       (0x1<<16) // 0: Value in freq_cnt field is not valid 1: Value in freq_cnt field is valid
+  #define IPC_REG_FREQ_STORM_CNT_VALID_SHIFT                                                                 16
+#define IPC_REG_PLL_MAIN_E28_KI_BB                                                                           0x0202a0UL //Access:RW   DataWidth:0x3    // Gain of P/I loop filter integrator path during fine phase acquisition mode Global register. Reset on POR reset.
+#define IPC_REG_FREQ_NWM_K2_E5                                                                               0x0202a4UL //Access:R    DataWidth:0x11   // Multi Field Register.
+  #define IPC_REG_FREQ_NWM_CNT_K2_E5                                                                         (0xffff<<0) // This field shows the frequency counter for main clock over a 10uS interval. NW Clock Frequency = ~(FreqCnt / 10)MHz. This field is not reset between measurements. For example, it shows X MHz in first measurement, 2*X in second measurement, 3*X MHz in third measurement.
+  #define IPC_REG_FREQ_NWM_CNT_K2_E5_SHIFT                                                                   0
+  #define IPC_REG_FREQ_NWM_CNT_VALID_K2_E5                                                                   (0x1<<16) // 0: Value in freq_cnt field is not valid 1: Value in freq_cnt field is valid
+  #define IPC_REG_FREQ_NWM_CNT_VALID_K2_E5_SHIFT                                                             16
+#define IPC_REG_PLL_MAIN_E28_KP_BB                                                                           0x0202a4UL //Access:RW   DataWidth:0x4    // Gain of P/I loop filter proportional path during fine phase acquisition mode. SW needs to use the following transformation to program this register. For 0, Write 0 For 1, Write 1 For 2, Write 4 For 3, Write 5 For 4, Write 2 For 5, Write 3 For 6, Write 6 For 7, Write 7 For 8, Write 8 For 9, Write 9 For 10, Write 12 For 11, Write 13 For 12, Write 10 For 13, Write 11 For 14, Write 14 For 15, Write 15 A default of 5 implies that the PLL sees a value of 3. Global register. Reset on POR reset.
+#define IPC_REG_FREE_RUNNING_CNTR_0_BB                                                                       0x0204b4UL //Access:R    DataWidth:0x20   // This is a 32-bit free running counter that has 1us resolution.
+#define IPC_REG_FREE_RUNNING_CNTR_0_K2_E5                                                                    0x0202a8UL //Access:R    DataWidth:0x20   // This is a 32-bit free running counter that has 1us resolution.
+#define IPC_REG_PLL_MAIN_E28_LOCK_BB                                                                         0x0202a8UL //Access:R    DataWidth:0x1    // LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset.
+#define IPC_REG_FREE_RUNNING_CNTR_1_BB                                                                       0x0204b8UL //Access:R    DataWidth:0x20   // This is a 32-bit free running counter that has 16us resolution.
+#define IPC_REG_FREE_RUNNING_CNTR_1_K2_E5                                                                    0x0202acUL //Access:R    DataWidth:0x20   // This is a 32-bit free running counter that has 16us resolution.
+#define IPC_REG_PLL_MAIN_E28_STATUS_BB                                                                       0x0202acUL //Access:R    DataWidth:0xc    // Status Bits from the PLL Global register. Reset on POR reset.
+#define IPC_REG_FREE_RUNNING_CNTR_2_BB                                                                       0x0204bcUL //Access:R    DataWidth:0x20   // This is a 32-bit free running counter that has 256us resolution.
+#define IPC_REG_FREE_RUNNING_CNTR_2_K2_E5                                                                    0x0202b0UL //Access:R    DataWidth:0x20   // This is a 32-bit free running counter that has 256us resolution.
+#define IPC_REG_PLL_NW_E28_PWRDN_BB                                                                          0x0202b0UL //Access:RW   DataWidth:0x1    // PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR
+#define IPC_REG_FREE_RUNNING_CNTR_3_BB                                                                       0x0204c0UL //Access:R    DataWidth:0x20   // This is a 32-bit free running counter that has 4096us resolution.
+#define IPC_REG_FREE_RUNNING_CNTR_3_K2_E5                                                                    0x0202b4UL //Access:R    DataWidth:0x20   // This is a 32-bit free running counter that has 4096us resolution.
+#define IPC_REG_PLL_NW_E28_RESET_VCO_BB                                                                      0x0202b4UL //Access:RW   DataWidth:0x1    // Resets the VCO logic in the PLL. The reset is Active High
+#define IPC_REG_FREE_RUNNING_CNTR_4_BB                                                                       0x0204c4UL //Access:R    DataWidth:0x20   // This is a 32-bit free running counter that has 65536us resolution.
+#define IPC_REG_FREE_RUNNING_CNTR_4_K2_E5                                                                    0x0202b8UL //Access:R    DataWidth:0x20   // This is a 32-bit free running counter that has 65536us resolution.
+#define IPC_REG_PLL_NW_E28_RESET_POST_BB                                                                     0x0202b8UL //Access:RW   DataWidth:0x1    // Resets the Post Divider logic in the PLL. The reset is Active High
+#define IPC_REG_VMAIN_POR_STATUS_BB                                                                          0x0204c8UL //Access:R    DataWidth:0x1    // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up
+#define IPC_REG_VMAIN_POR_STATUS_K2_E5                                                                       0x0202bcUL //Access:R    DataWidth:0x1    // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up
+#define IPC_REG_PLL_NW_E28_PDIV_BB                                                                           0x0202bcUL //Access:RW   DataWidth:0x4    // Input reference clock pre-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= divide-by-4 0101= divide-by-5 0110= divide-by-6 0111= divide-by-7 1111 = divide-by-15 Global register. Reset on POR reset.
+#define IPC_REG_STAT_VMAIN_POR_ASSERTION_BB                                                                  0x0204ccUL //Access:RC   DataWidth:0x8    // This register provides the number of times VMAIN POR was asserted. This would be the count of number of times VMAIN went down.
+#define IPC_REG_STAT_VMAIN_POR_ASSERTION_K2_E5                                                               0x0202c0UL //Access:RC   DataWidth:0x8    // This register provides the number of times VMAIN POR was asserted. This would be the count of number of times VMAIN went down.
+#define IPC_REG_PLL_NW_E28_NDIV_INT_BB                                                                       0x0202c0UL //Access:RW   DataWidth:0xa    // Feedback divider control 0000000000= divide-by-1024 0000000001= XXX 0000000010= XXX : 0000001011= XXX 0000001100= divide-by-12 0000001101= divide-by-13 0000001110= divide-by-14 : 1111111110= divide-by-1022 1111111111= divide-by-1023 Global register. Reset on POR reset.
+#define IPC_REG_STAT_VMAIN_POR_DEASSERTION_BB                                                                0x0204d0UL //Access:RC   DataWidth:0x8    // This register provides the number of times VMAIN POR was de-asserted. This would be the count of number of times VMAIN came up.
+#define IPC_REG_STAT_VMAIN_POR_DEASSERTION_K2_E5                                                             0x0202c4UL //Access:RC   DataWidth:0x8    // This register provides the number of times VMAIN POR was de-asserted. This would be the count of number of times VMAIN came up.
+#define IPC_REG_PLL_NW_E28_NDIV_FRAC_BB                                                                      0x0202c4UL //Access:RW   DataWidth:0x14   // Fractional feedback divider control. Resolution= 1/(2^20). Global register. Reset on POR reset.
+#define IPC_REG_PERST_POR_STATUS_BB                                                                          0x0204d4UL //Access:R    DataWidth:0x1    // This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-asserted
+#define IPC_REG_PERST_POR_STATUS_K2_E5                                                                       0x0202c8UL //Access:R    DataWidth:0x1    // This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-asserted
+#define IPC_REG_PLL_NW_E28_CH0_MDIV_BB                                                                       0x0202c8UL //Access:RW   DataWidth:0x8    // Post-divider ratio for channel-0 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset.
+#define IPC_REG_STAT_PERST_ASSERTION_BB                                                                      0x0204d8UL //Access:RC   DataWidth:0x8    // This register provides the number of times PERST# was asserted
+#define IPC_REG_STAT_PERST_ASSERTION_K2_E5                                                                   0x0202ccUL //Access:RC   DataWidth:0x8    // This register provides the number of times PERST# was asserted
+#define IPC_REG_PLL_NW_E28_CH1_MDIV_BB                                                                       0x0202ccUL //Access:RW   DataWidth:0x8    // Post-divider ratio for channel-1 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset.
+#define IPC_REG_STAT_PERST_DEASSERTION_BB                                                                    0x0204dcUL //Access:RC   DataWidth:0x8    // This register provides the number of times PERST# was de-asserted
+#define IPC_REG_STAT_PERST_DEASSERTION_K2_E5                                                                 0x0202d0UL //Access:RC   DataWidth:0x8    // This register provides the number of times PERST# was de-asserted
+#define IPC_REG_PLL_NW_E28_CH_ENABLEB_BB                                                                     0x0202d0UL //Access:RW   DataWidth:0x6    // Active Low Channel Enable. Global register. Reset on POR reset.
+#define IPC_REG_CHIP_MODE_BB                                                                                 0x0204e0UL //Access:R    DataWidth:0x6    // This register shows the current status of the Mode Pins of the chip. 6'bXX0000 -> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone mode 6'bXX0100 -> MAC SERDES Standalone mode 6'bXX0101 -> IDDQ Mode 6'bXX0110 -> OVSTB Mode 6'bX1XXXX -> Run all the modes in Fast Reset (useful in Simulation/ATE) 6'b1XXXXX -> Run all the modes in POR Bypass mode
+#define IPC_REG_CHIP_MODE_K2_E5                                                                              0x0202d4UL //Access:R    DataWidth:0x6    // This register shows the current status of the Mode Pins of the chip. 6'bXX0000 -> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone mode 6'bXX0100 -> MAC SERDES Standalone mode 6'bXX0101 -> IDDQ Mode 6'bXX0110 -> OVSTB Mode 6'bX1XXXX -> Run all the modes in Fast Reset (useful in Simulation/ATE) 6'b1XXXXX -> Run all the modes in POR Bypass mode
+#define IPC_REG_PLL_NW_E28_CTRL_0_BB                                                                         0x0202d4UL //Access:RW   DataWidth:0x20   // PLL Control Register [11:0] dco_ctrl_bypass[11:0] direct programming of DAC: 00...00 = MIN VCO clock frequency : 11...11 = MAX VCO clock frequency [12] dco_ctrl_bypass_enable enable of direct programming of DAC: 0 =normal mode 1 =DAC programming mode [13] stat_reset reset of phase error measurement: 0 =normal mode 1 =reset [16:14] stat_select[2:0] select of test output: 000 = 000000000000 001 = minimum phase error 010 = maximum phase error 011 = lock_state 100 = dac control word 101 = 000000000000 110 = 000000000000 111 = 000000000000 [17] stat_update On the synchronized rising edge of this control signal the value selected by stat_select[2:0] is clocked into o_statout [19:18] Reserved [21:20] Stat_mode[1:0] Statistics Mode 00 = disabled 01 = phase error stats 10 : period stats 11 : Feedback phase error stats [23:22] Pwm_rate[1:0] Set PWM rate Vco_fb_div2 == 0 00 = 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for VCO gt 800MHz 10 for VCO lt 800MHz [25:24] post_resetb select post channel resetb selection 00 = lock or post_resetb 01 = flock or post_resetb 10 = resetb or post_resetb 11 = post_resetb [26] vco_fb_div2 Divide vco_fdbk clock by 2 0= vco clock 1=vco/2 clock 0 for VCO lt 2.0GHz 1 for VCO gt 2.0GHz [27] fast_lock Reduces the number of refclk cycles of delay between frequency lock and setting o_lock output high. 0 = 256 refclk delay 1 = 32 refclk delay [28] ndiv_relock Forces lock state machine to return to frequency acquisition state when ndiv_int/ndiv_frac changes. 0 = Loop responds to ndiv change. May or may not switch back to frequency acquisition mode. 1 = Re-enter frequency acquisition state, without resetting the initial frequency (starts from current frequency). This produces smoother transition to new frequency for steps greater than 1 percent [29] Reserved [31:30] Vco_range Set VCO frequency range 00 = 800 - 2000 MHz 01 = 500 - 1200 MHz 10 = 1600 - 4000 MHz [33:32] LDO[1:0] LDO output voltage control 00 = 1.05 V 01 = 1.00 V 10 = 0.95 V 11 = 0.90 V [34] testout_en Test output buffer enable 0= normal mode 1= test output buffer enable [37:35] testout_sel Test output clock selection 000 = no clock 001 = o_fref 010 = o_clkout[0] 011 = o_clkout[1] 100 = o_clkout[2] 101 = o_clkout[3] 110 = o_clkout[4] 111 = o_clkout[5] [63:38] Reserved
+#define IPC_REG_HW_STRAPS_BB                                                                                 0x0204e4UL //Access:R    DataWidth:0xc    // Multi Field Register.
+#define IPC_REG_HW_STRAPS_K2_E5                                                                              0x0202d8UL //Access:R    DataWidth:0xc    // Multi Field Register.
+  #define IPC_REG_HW_STRAPS_TESTIN_STRAPS                                                                    (0xff<<0) // Strap value on TEST IN pins
+  #define IPC_REG_HW_STRAPS_TESTIN_STRAPS_SHIFT                                                              0
+  #define IPC_REG_HW_STRAPS_FLASH_STRAPS                                                                     (0xf<<8) // Strap value on FLASH pins
+  #define IPC_REG_HW_STRAPS_FLASH_STRAPS_SHIFT                                                               8
+#define IPC_REG_PLL_NW_E28_CTRL_1_BB                                                                         0x0202d8UL //Access:RW   DataWidth:0x20   // PLL Control Register [11:0] dco_ctrl_bypass[11:0] direct programming of DAC: 00...00 = MIN VCO clock frequency : 11...11 = MAX VCO clock frequency [12] dco_ctrl_bypass_enable enable of direct programming of DAC: 0 =normal mode 1 =DAC programming mode [13] stat_reset reset of phase error measurement: 0 =normal mode 1 =reset [16:14] stat_select[2:0] select of test output: 000 = 000000000000 001 = minimum phase error 010 = maximum phase error 011 = lock_state 100 = dac control word 101 = 000000000000 110 = 000000000000 111 = 000000000000 [17] stat_update On the synchronized rising edge of this control signal the value selected by stat_select[2:0] is clocked into o_statout [19:18] Reserved [21:20] Stat_mode[1:0] Statistics Mode 00 = disabled 01 = phase error stats 10 : period stats 11 : Feedback phase error stats [23:22] Pwm_rate[1:0] Set PWM rate Vco_fb_div2 == 0 00 = 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for VCO gt 800MHz 10 for VCO lt 800MHz [25:24] post_resetb select post channel resetb selection 00 = lock or post_resetb 01 = flock or post_resetb 10 = resetb or post_resetb 11 = post_resetb [26] vco_fb_div2 Divide vco_fdbk clock by 2 0= vco clock 1=vco/2 clock 0 for VCO lt 2.0GHz 1 for VCO gt 2.0GHz [27] fast_lock Reduces the number of refclk cycles of delay between frequency lock and setting o_lock output high. 0 = 256 refclk delay 1 = 32 refclk delay [28] ndiv_relock Forces lock state machine to return to frequency acquisition state when ndiv_int/ndiv_frac changes. 0 = Loop responds to ndiv change. May or may not switch back to frequency acquisition mode. 1 = Re-enter frequency acquisition state, without resetting the initial frequency (starts from current frequency). This produces smoother transition to new frequency for steps greater than 1 percent [29] Reserved [31:30] Vco_range Set VCO frequency range 00 = 800 - 2000 MHz 01 = 500 - 1200 MHz 10 = 1600 - 4000 MHz [33:32] LDO[1:0] LDO output voltage control 00 = 1.05 V 01 = 1.00 V 10 = 0.95 V 11 = 0.90 V [34] testout_en Test output buffer enable 0= normal mode 1= test output buffer enable [37:35] testout_sel Test output clock selection 000 = no clock 001 = o_fref 010 = o_clkout[0] 011 = o_clkout[1] 100 = o_clkout[2] 101 = o_clkout[3] 110 = o_clkout[4] 111 = o_clkout[5] [63:38] Reserved
+#define IPC_REG_INT_STS_0_BB                                                                                 0x02050cUL //Access:R    DataWidth:0x10   // Multi Field Register.
+#define IPC_REG_INT_STS_0_K2_E5                                                                              0x0202dcUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define IPC_REG_INT_STS_0_ADDRESS_ERROR                                                                    (0x1<<0) // Signals an unknown address to the rf module.
+  #define IPC_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                              0
+  #define IPC_REG_INT_STS_0_VMAIN_POR_ASSERT                                                                 (0x1<<4) // This bit generates an interrupt when VMAIN POR is asserted, ie VMAIN goes from high to low
+  #define IPC_REG_INT_STS_0_VMAIN_POR_ASSERT_SHIFT                                                           4
+  #define IPC_REG_INT_STS_0_VMAIN_POR_DEASSERT                                                               (0x1<<5) // This bit generates an interrupt when VMAIN POR is de-asserted, ie VMAIN goes from low to high
+  #define IPC_REG_INT_STS_0_VMAIN_POR_DEASSERT_SHIFT                                                         5
+  #define IPC_REG_INT_STS_0_PERST_ASSERT                                                                     (0x1<<6) // This bit generates an interrupt when PERST# is asserted, ie PERST# goes from high to low
+  #define IPC_REG_INT_STS_0_PERST_ASSERT_SHIFT                                                               6
+  #define IPC_REG_INT_STS_0_PERST_DEASSERT                                                                   (0x1<<7) // This bit generates an interrupt when PERST# is de-asserted, ie PERST# goes from low to high
+  #define IPC_REG_INT_STS_0_PERST_DEASSERT_SHIFT                                                             7
+  #define IPC_REG_INT_STS_0_OTP_ECC_DED_0_BB                                                                 (0x1<<8) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 0 is asserted.
+  #define IPC_REG_INT_STS_0_OTP_ECC_DED_0_BB_SHIFT                                                           8
+  #define IPC_REG_INT_STS_0_OTP_ECC_DED_1_BB                                                                 (0x1<<9) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 1 is asserted.
+  #define IPC_REG_INT_STS_0_OTP_ECC_DED_1_BB_SHIFT                                                           9
+  #define IPC_REG_INT_STS_0_OTP_ECC_DED_2_BB                                                                 (0x1<<10) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 2 is asserted.
+  #define IPC_REG_INT_STS_0_OTP_ECC_DED_2_BB_SHIFT                                                           10
+  #define IPC_REG_INT_STS_0_OTP_ECC_DED_3_BB                                                                 (0x1<<11) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 3 is asserted.
+  #define IPC_REG_INT_STS_0_OTP_ECC_DED_3_BB_SHIFT                                                           11
+  #define IPC_REG_INT_STS_0_OTP_ECC_DED_4_BB                                                                 (0x1<<12) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 4 is asserted.
+  #define IPC_REG_INT_STS_0_OTP_ECC_DED_4_BB_SHIFT                                                           12
+  #define IPC_REG_INT_STS_0_OTP_ECC_DED_5_BB                                                                 (0x1<<13) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 5 is asserted.
+  #define IPC_REG_INT_STS_0_OTP_ECC_DED_5_BB_SHIFT                                                           13
+  #define IPC_REG_INT_STS_0_OTP_ECC_DED_6_BB                                                                 (0x1<<14) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 6 is asserted.
+  #define IPC_REG_INT_STS_0_OTP_ECC_DED_6_BB_SHIFT                                                           14
+  #define IPC_REG_INT_STS_0_OTP_ECC_DED_7_BB                                                                 (0x1<<15) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 0 is asserted.
+  #define IPC_REG_INT_STS_0_OTP_ECC_DED_7_BB_SHIFT                                                           15
+#define IPC_REG_PLL_NW_E28_KA_BB                                                                             0x0202dcUL //Access:RW   DataWidth:0x3    // Loop gain in frequency acquisition mode Global register. Reset on POR reset.
+#define IPC_REG_INT_MASK_0_BB                                                                                0x020510UL //Access:RW   DataWidth:0x10   // Multi Field Register.
+#define IPC_REG_INT_MASK_0_K2_E5                                                                             0x0202e0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define IPC_REG_INT_MASK_0_ADDRESS_ERROR                                                                   (0x1<<0) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.ADDRESS_ERROR .
+  #define IPC_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                             0
+  #define IPC_REG_INT_MASK_0_VMAIN_POR_ASSERT                                                                (0x1<<4) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.VMAIN_POR_ASSERT .
+  #define IPC_REG_INT_MASK_0_VMAIN_POR_ASSERT_SHIFT                                                          4
+  #define IPC_REG_INT_MASK_0_VMAIN_POR_DEASSERT                                                              (0x1<<5) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.VMAIN_POR_DEASSERT .
+  #define IPC_REG_INT_MASK_0_VMAIN_POR_DEASSERT_SHIFT                                                        5
+  #define IPC_REG_INT_MASK_0_PERST_ASSERT                                                                    (0x1<<6) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.PERST_ASSERT .
+  #define IPC_REG_INT_MASK_0_PERST_ASSERT_SHIFT                                                              6
+  #define IPC_REG_INT_MASK_0_PERST_DEASSERT                                                                  (0x1<<7) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.PERST_DEASSERT .
+  #define IPC_REG_INT_MASK_0_PERST_DEASSERT_SHIFT                                                            7
+  #define IPC_REG_INT_MASK_0_OTP_ECC_DED_0_BB                                                                (0x1<<8) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_0 .
+  #define IPC_REG_INT_MASK_0_OTP_ECC_DED_0_BB_SHIFT                                                          8
+  #define IPC_REG_INT_MASK_0_OTP_ECC_DED_1_BB                                                                (0x1<<9) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_1 .
+  #define IPC_REG_INT_MASK_0_OTP_ECC_DED_1_BB_SHIFT                                                          9
+  #define IPC_REG_INT_MASK_0_OTP_ECC_DED_2_BB                                                                (0x1<<10) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_2 .
+  #define IPC_REG_INT_MASK_0_OTP_ECC_DED_2_BB_SHIFT                                                          10
+  #define IPC_REG_INT_MASK_0_OTP_ECC_DED_3_BB                                                                (0x1<<11) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_3 .
+  #define IPC_REG_INT_MASK_0_OTP_ECC_DED_3_BB_SHIFT                                                          11
+  #define IPC_REG_INT_MASK_0_OTP_ECC_DED_4_BB                                                                (0x1<<12) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_4 .
+  #define IPC_REG_INT_MASK_0_OTP_ECC_DED_4_BB_SHIFT                                                          12
+  #define IPC_REG_INT_MASK_0_OTP_ECC_DED_5_BB                                                                (0x1<<13) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_5 .
+  #define IPC_REG_INT_MASK_0_OTP_ECC_DED_5_BB_SHIFT                                                          13
+  #define IPC_REG_INT_MASK_0_OTP_ECC_DED_6_BB                                                                (0x1<<14) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_6 .
+  #define IPC_REG_INT_MASK_0_OTP_ECC_DED_6_BB_SHIFT                                                          14
+  #define IPC_REG_INT_MASK_0_OTP_ECC_DED_7_BB                                                                (0x1<<15) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_7 .
+  #define IPC_REG_INT_MASK_0_OTP_ECC_DED_7_BB_SHIFT                                                          15
+#define IPC_REG_PLL_NW_E28_KI_BB                                                                             0x0202e0UL //Access:RW   DataWidth:0x3    // Gain of P/I loop filter integrator path during fine phase acquisition mode Global register. Reset on POR reset.
+#define IPC_REG_INT_STS_WR_0_BB                                                                              0x020514UL //Access:WR   DataWidth:0x10   // Multi Field Register.
+#define IPC_REG_INT_STS_WR_0_K2_E5                                                                           0x0202e4UL //Access:WR   DataWidth:0x8    // Multi Field Register.
+  #define IPC_REG_INT_STS_WR_0_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define IPC_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                           0
+  #define IPC_REG_INT_STS_WR_0_VMAIN_POR_ASSERT                                                              (0x1<<4) // This bit generates an interrupt when VMAIN POR is asserted, ie VMAIN goes from high to low
+  #define IPC_REG_INT_STS_WR_0_VMAIN_POR_ASSERT_SHIFT                                                        4
+  #define IPC_REG_INT_STS_WR_0_VMAIN_POR_DEASSERT                                                            (0x1<<5) // This bit generates an interrupt when VMAIN POR is de-asserted, ie VMAIN goes from low to high
+  #define IPC_REG_INT_STS_WR_0_VMAIN_POR_DEASSERT_SHIFT                                                      5
+  #define IPC_REG_INT_STS_WR_0_PERST_ASSERT                                                                  (0x1<<6) // This bit generates an interrupt when PERST# is asserted, ie PERST# goes from high to low
+  #define IPC_REG_INT_STS_WR_0_PERST_ASSERT_SHIFT                                                            6
+  #define IPC_REG_INT_STS_WR_0_PERST_DEASSERT                                                                (0x1<<7) // This bit generates an interrupt when PERST# is de-asserted, ie PERST# goes from low to high
+  #define IPC_REG_INT_STS_WR_0_PERST_DEASSERT_SHIFT                                                          7
+  #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_0_BB                                                              (0x1<<8) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 0 is asserted.
+  #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_0_BB_SHIFT                                                        8
+  #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_1_BB                                                              (0x1<<9) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 1 is asserted.
+  #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_1_BB_SHIFT                                                        9
+  #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_2_BB                                                              (0x1<<10) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 2 is asserted.
+  #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_2_BB_SHIFT                                                        10
+  #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_3_BB                                                              (0x1<<11) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 3 is asserted.
+  #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_3_BB_SHIFT                                                        11
+  #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_4_BB                                                              (0x1<<12) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 4 is asserted.
+  #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_4_BB_SHIFT                                                        12
+  #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_5_BB                                                              (0x1<<13) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 5 is asserted.
+  #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_5_BB_SHIFT                                                        13
+  #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_6_BB                                                              (0x1<<14) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 6 is asserted.
+  #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_6_BB_SHIFT                                                        14
+  #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_7_BB                                                              (0x1<<15) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 0 is asserted.
+  #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_7_BB_SHIFT                                                        15
+#define IPC_REG_PLL_NW_E28_KP_BB                                                                             0x0202e4UL //Access:RW   DataWidth:0x4    // Gain of P/I loop filter proportional path during fine phase acquisition mode. SW needs to use the following transformation to program this register. For 0, Write 0 For 1, Write 1 For 2, Write 4 For 3, Write 5 For 4, Write 2 For 5, Write 3 For 6, Write 6 For 7, Write 7 For 8, Write 8 For 9, Write 9 For 10, Write 12 For 11, Write 13 For 12, Write 10 For 13, Write 11 For 14, Write 14 For 15, Write 15 A default of 5 implies that the PLL sees a value of 3. Global register. Reset on POR reset.
+#define IPC_REG_INT_STS_CLR_0_BB                                                                             0x020518UL //Access:RC   DataWidth:0x10   // Multi Field Register.
+#define IPC_REG_INT_STS_CLR_0_K2_E5                                                                          0x0202e8UL //Access:RC   DataWidth:0x8    // Multi Field Register.
+  #define IPC_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define IPC_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                          0
+  #define IPC_REG_INT_STS_CLR_0_VMAIN_POR_ASSERT                                                             (0x1<<4) // This bit generates an interrupt when VMAIN POR is asserted, ie VMAIN goes from high to low
+  #define IPC_REG_INT_STS_CLR_0_VMAIN_POR_ASSERT_SHIFT                                                       4
+  #define IPC_REG_INT_STS_CLR_0_VMAIN_POR_DEASSERT                                                           (0x1<<5) // This bit generates an interrupt when VMAIN POR is de-asserted, ie VMAIN goes from low to high
+  #define IPC_REG_INT_STS_CLR_0_VMAIN_POR_DEASSERT_SHIFT                                                     5
+  #define IPC_REG_INT_STS_CLR_0_PERST_ASSERT                                                                 (0x1<<6) // This bit generates an interrupt when PERST# is asserted, ie PERST# goes from high to low
+  #define IPC_REG_INT_STS_CLR_0_PERST_ASSERT_SHIFT                                                           6
+  #define IPC_REG_INT_STS_CLR_0_PERST_DEASSERT                                                               (0x1<<7) // This bit generates an interrupt when PERST# is de-asserted, ie PERST# goes from low to high
+  #define IPC_REG_INT_STS_CLR_0_PERST_DEASSERT_SHIFT                                                         7
+  #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_0_BB                                                             (0x1<<8) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 0 is asserted.
+  #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_0_BB_SHIFT                                                       8
+  #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_1_BB                                                             (0x1<<9) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 1 is asserted.
+  #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_1_BB_SHIFT                                                       9
+  #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_2_BB                                                             (0x1<<10) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 2 is asserted.
+  #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_2_BB_SHIFT                                                       10
+  #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_3_BB                                                             (0x1<<11) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 3 is asserted.
+  #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_3_BB_SHIFT                                                       11
+  #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_4_BB                                                             (0x1<<12) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 4 is asserted.
+  #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_4_BB_SHIFT                                                       12
+  #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_5_BB                                                             (0x1<<13) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 5 is asserted.
+  #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_5_BB_SHIFT                                                       13
+  #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_6_BB                                                             (0x1<<14) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 6 is asserted.
+  #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_6_BB_SHIFT                                                       14
+  #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_7_BB                                                             (0x1<<15) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 0 is asserted.
+  #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_7_BB_SHIFT                                                       15
+#define IPC_REG_PLL_NW_E28_LOCK_BB                                                                           0x0202e8UL //Access:R    DataWidth:0x1    // LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset.
+#define IPC_REG_JTAG_COMPLIANCE_BB                                                                           0x020508UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+#define IPC_REG_JTAG_COMPLIANCE_K2_E5                                                                        0x0202ecUL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define IPC_REG_JTAG_COMPLIANCE_EN                                                                         (0x3<<0) // These bits set the compliance enable for JTAG pins. the JTAG interface is shared by four masters and there is a dedicated 2-bit compliance enable pins on the ballout. These bits are used to override the pins if needed. 2'b00 --> LV JTAG is selected 2'b01 --> AVS JTAG is selected 2'b10 --> MCP EJTAG is selected 2'b11 --> AVS EJTAG is selected
+  #define IPC_REG_JTAG_COMPLIANCE_EN_SHIFT                                                                   0
+  #define IPC_REG_JTAG_COMPLIANCE_OVERRIDE                                                                   (0x1<<4) // Set this bit to override the pins on the chip with bits[1:0]
+  #define IPC_REG_JTAG_COMPLIANCE_OVERRIDE_SHIFT                                                             4
+#define IPC_REG_PLL_NW_E28_STATUS_BB                                                                         0x0202ecUL //Access:R    DataWidth:0xc    // Status Bits from the PLL Global register. Reset on POR reset.
+#define IPC_REG_TCAM_BIST_REGISTER_OR_EXTERNAL_SELECT_K2_E5                                                  0x0202f0UL //Access:RW   DataWidth:0x1    // 0 - control of the tcam bist is from the IPC register tcam_bist_control and tcam_bist_num. 1 - control of the tcam bist is from the external pins. by default these pins are gurenteed to be zero so tcam bist will not start running.
+#define IPC_REG_PLL_STORM_E28_PWRDN_BB                                                                       0x0202f0UL //Access:RW   DataWidth:0x1    // PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR
+#define IPC_REG_TCAM_BIST_NUM_K2_E5                                                                          0x0202f4UL //Access:RW   DataWidth:0x5    // select the cam instance when reading the status of the cam in tcam_bist_status 0 ccfc_ccam 1 ccfc_scam 2 igu 3 msem 4 prs_gft 5 prs_h 6 prs_l 7 psem 8 psem_vfc 9 qm 10 tcfc_ccam 11 tsem 12 tsem_vfc 13 usem 14 xsem 15 ysem
+#define IPC_REG_PLL_STORM_E28_RESET_VCO_BB                                                                   0x0202f4UL //Access:RW   DataWidth:0x1    // Resets the VCO logic in the PLL. The reset is Active High
+#define IPC_REG_TCAM_BIST_STATUS_K2_E5                                                                       0x0202f8UL //Access:R    DataWidth:0x6    // tcam bist status bus bit 0 - bist_pass bit 1 - bist_failed bit 2 - bist_paused bit 3 - reserved(bist_sho) bit 4 - reserved bit 5 - reserved
+#define IPC_REG_PLL_STORM_E28_RESET_POST_BB                                                                  0x0202f8UL //Access:RW   DataWidth:0x1    // Resets the Post Divider logic in the PLL. The reset is Active High
+#define IPC_REG_TCAM_BIST_CONTROL_CCFC_CCAM_K2_E5                                                            0x0202fcUL //Access:RW   DataWidth:0x6    // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved
+#define IPC_REG_PLL_STORM_E28_PDIV_BB                                                                        0x0202fcUL //Access:RW   DataWidth:0x4    // Input reference clock pre-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= divide-by-4 0101= divide-by-5 0110= divide-by-6 0111= divide-by-7 1111 = divide-by-15 Global register. Reset on POR reset.
+#define IPC_REG_TCAM_BIST_CONTROL_CCFC_SCAM_K2_E5                                                            0x020300UL //Access:RW   DataWidth:0x6    // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved
+#define IPC_REG_PLL_STORM_E28_NDIV_INT_BB                                                                    0x020300UL //Access:RW   DataWidth:0xa    // Feedback divider control 0000000000 = not usable 0000000001 = not usable ... 0000001111 = not usable 0000010000 = 16 ... 1111111111 = 1023 Global register. Reset on POR reset.
+#define IPC_REG_TCAM_BIST_CONTROL_TCFC_CCAM_K2_E5                                                            0x020304UL //Access:RW   DataWidth:0x6    // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved
+#define IPC_REG_PLL_STORM_E28_CH0_MDIV_BB                                                                    0x020304UL //Access:RW   DataWidth:0x8    // Post-divider ratio for channel-0 00000000 = divide by 256 00000001 = divide by 1 00000010 = divide by 2 ... 11111111 = divide by 255 Global register. Reset on POR reset.
+#define IPC_REG_TCAM_BIST_CONTROL_QM_K2_E5                                                                   0x020308UL //Access:RW   DataWidth:0x6    // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved
+#define IPC_REG_PLL_STORM_E28_CH1_MDIV_BB                                                                    0x020308UL //Access:RW   DataWidth:0x8    // Post-divider ratio for channel-1 00000000 = divide by 256 00000001 = divide by 1 00000010 = divide by 2 ... 11111111 = divide by 255 Global register. Reset on POR reset.
+#define IPC_REG_TCAM_BIST_CONTROL_XSEM_K2_E5                                                                 0x02030cUL //Access:RW   DataWidth:0x6    // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved
+#define IPC_REG_PLL_STORM_E28_CH_ENABLEB_BB                                                                  0x02030cUL //Access:RW   DataWidth:0x6    // Active Low Channel Enable. Global register. Reset on POR reset.
+#define IPC_REG_TCAM_BIST_CONTROL_YSEM_K2_E5                                                                 0x020310UL //Access:RW   DataWidth:0x6    // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved
+#define IPC_REG_PLL_STORM_E28_CTRL_0_BB                                                                      0x020310UL //Access:RW   DataWidth:0x20   // PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset.
+#define IPC_REG_TCAM_BIST_CONTROL_PSEM_K2_E5                                                                 0x020314UL //Access:RW   DataWidth:0x6    // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved
+#define IPC_REG_PLL_STORM_E28_CTRL_1_BB                                                                      0x020314UL //Access:RW   DataWidth:0x20   // PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset.
+#define IPC_REG_TCAM_BIST_CONTROL_PSEM_VFC_K2_E5                                                             0x020318UL //Access:RW   DataWidth:0x6    // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved
+#define IPC_REG_PLL_STORM_E28_CTRL_2_BB                                                                      0x020318UL //Access:RW   DataWidth:0x2    // PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset.
+#define IPC_REG_TCAM_BIST_CONTROL_USEM_K2_E5                                                                 0x02031cUL //Access:RW   DataWidth:0x6    // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved
+#define IPC_REG_PLL_STORM_E28_KI_BB                                                                          0x02031cUL //Access:RW   DataWidth:0x3    // Integrator gain control of the PLL digital filter. Global register. Reset on POR reset.
+#define IPC_REG_TCAM_BIST_CONTROL_TSEM_K2_E5                                                                 0x020320UL //Access:RW   DataWidth:0x6    // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved
+#define IPC_REG_PLL_STORM_E28_KP_BB                                                                          0x020320UL //Access:RW   DataWidth:0x4    // Gain of P/I loop filter proportional path during fine phase acquisition mode. Global register. Reset on POR reset.
+#define IPC_REG_TCAM_BIST_CONTROL_TSEM_VFC_K2_E5                                                             0x020324UL //Access:RW   DataWidth:0x6    // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved
+#define IPC_REG_PLL_STORM_E28_KPP_BB                                                                         0x020324UL //Access:RW   DataWidth:0x4    // Control of the non-zero pole in the PLL digital filter. Global register. Reset on POR reset.
+#define IPC_REG_TCAM_BIST_CONTROL_MSEM_K2_E5                                                                 0x020328UL //Access:RW   DataWidth:0x6    // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved
+#define IPC_REG_PLL_STORM_E28_LOCK_BB                                                                        0x020328UL //Access:R    DataWidth:0x1    // LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset.
+#define IPC_REG_TCAM_BIST_CONTROL_PRS_GFT_K2_E5                                                              0x02032cUL //Access:RW   DataWidth:0x6    // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved
+#define IPC_REG_PLL_STORM_E28_STATUS_BB                                                                      0x02032cUL //Access:R    DataWidth:0xc    // Internal Status Bits of the PLL Global register. Reset on POR reset.
+#define IPC_REG_TCAM_BIST_CONTROL_PRS_L_K2_E5                                                                0x020330UL //Access:RW   DataWidth:0x6    // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved
+#define IPC_REG_LCPLL_E28_PWRDN_BB                                                                           0x020330UL //Access:RW   DataWidth:0x1    // PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR
+#define IPC_REG_TCAM_BIST_CONTROL_PRS_H_K2_E5                                                                0x020334UL //Access:RW   DataWidth:0x6    // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved
+#define IPC_REG_LCPLL_E28_RESET_VCO_BB                                                                       0x020334UL //Access:RW   DataWidth:0x1    // Resets the VCO logic in the PLL. The reset is Active High
+#define IPC_REG_TCAM_BIST_CONTROL_IGU_K2_E5                                                                  0x020338UL //Access:RW   DataWidth:0x6    // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved
+#define IPC_REG_LCPLL_E28_RESET_POST_BB                                                                      0x020338UL //Access:RW   DataWidth:0x1    // Resets the Post Divider logic in the PLL. The reset is Active High
+#define IPC_REG_CLK_DFT_MS_125M_DIV_K2_E5                                                                    0x02033cUL //Access:RW   DataWidth:0x8    // divider value for clk_dft_ms_125, the division is 2*value. this value is output at ipc_clkdec_clk_dft_ms_125m_div 0 - no division 1- divide by 2 2- divide by 4
+#define IPC_REG_LCPLL_E28_PDIV_BB                                                                            0x02033cUL //Access:RW   DataWidth:0x4    // Input reference clock pre-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= divide-by-4 0101= divide-by-5 0110= divide-by-6 0111= divide-by-7 1111 = divide-by-15 Global register. Reset on POR reset.
+#define IPC_REG_CLK_DFT_MS_150M_DIV_K2_E5                                                                    0x020340UL //Access:RW   DataWidth:0x8    // 
+#define IPC_REG_LCPLL_E28_NDIV_INT_BB                                                                        0x020340UL //Access:RW   DataWidth:0xa    // Feedback divider control 0000000000 = not usable 0000000001 = not usable ... 0000001111 = not usable 0000010000 = 16 ... 1111111111 = 1023 Global register. Reset on POR reset.
+#define IPC_REG_CLK_DFT_MS_60M_DIV_K2_E5                                                                     0x020344UL //Access:RW   DataWidth:0x8    // 
+#define IPC_REG_LCPLL_E28_CH0_MDIV_BB                                                                        0x020344UL //Access:RW   DataWidth:0x8    // Post-divider ratio for channel-0 00000000 = divide by 256 00000001 = divide by 1 00000010 = divide by 2 ... 11111111 = divide by 255 Global register. Reset on POR reset.
+#define IPC_REG_CLK_DFT_MS_70M_DIV_K2_E5                                                                     0x020348UL //Access:RW   DataWidth:0x8    // 
+#define IPC_REG_LCPLL_E28_CH1_MDIV_BB                                                                        0x020348UL //Access:RW   DataWidth:0x8    // Post-divider ratio for channel-1 00000000 = divide by 256 00000001 = divide by 1 00000010 = divide by 2 ... 11111111 = divide by 255 Global register. Reset on POR reset.
+#define IPC_REG_CLK_DFT_MS_412M_DIV_K2_E5                                                                    0x02034cUL //Access:RW   DataWidth:0x8    // 
+#define IPC_REG_LCPLL_E28_CH_ENABLEB_BB                                                                      0x02034cUL //Access:RW   DataWidth:0x6    // Active Low Channel Enable. Global register. Reset on POR reset.
+#define IPC_REG_CLK_DFT_NWS_644M_DIV_K2_E5                                                                   0x020350UL //Access:RW   DataWidth:0x8    // 
+#define IPC_REG_LCPLL_E28_CTRL_0_BB                                                                          0x020350UL //Access:RW   DataWidth:0x20   // PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset.
+#define IPC_REG_CLK_DFT_NWS_300M_DIV_K2_E5                                                                   0x020354UL //Access:RW   DataWidth:0x8    // 
+#define IPC_REG_LCPLL_E28_CTRL_1_BB                                                                          0x020354UL //Access:RW   DataWidth:0x20   // PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset.
+#define IPC_REG_CLK_DFT_NWS_100M_DIV_K2_E5                                                                   0x020358UL //Access:RW   DataWidth:0x8    // 
+#define IPC_REG_LCPLL_E28_CTRL_2_BB                                                                          0x020358UL //Access:RW   DataWidth:0x2    // PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset.
+#define IPC_REG_CLK_DFT_PCIES_500M_DIV_K2_E5                                                                 0x02035cUL //Access:RW   DataWidth:0x8    // 
+#define IPC_REG_LCPLL_E28_KI_BB                                                                              0x02035cUL //Access:RW   DataWidth:0x3    // Integrator gain control of the PLL digital filter. Global register. Reset on POR reset.
+#define IPC_REG_CLK_DFT_PCIES_100M_DIV_K2_E5                                                                 0x020360UL //Access:RW   DataWidth:0x8    // 
+#define IPC_REG_LCPLL_E28_KP_BB                                                                              0x020360UL //Access:RW   DataWidth:0x4    // Gain of P/I loop filter proportional path during fine phase acquisition mode. Global register. Reset on POR reset.
+#define IPC_REG_CLK_DFT_PCIES_50M_DIV_K2_E5                                                                  0x020364UL //Access:RW   DataWidth:0x8    // 
+#define IPC_REG_LCPLL_E28_KPP_BB                                                                             0x020364UL //Access:RW   DataWidth:0x4    // Control of the non-zero pole in the PLL digital filter. Global register. Reset on POR reset.
+#define IPC_REG_STRENGTH_IO_CONTROL_K2_E5                                                                    0x020368UL //Access:RW   DataWidth:0x6    // Sets the CTL# (# in [0..5]) I/Os of the PADS in non - scan/mbist modes
+#define IPC_REG_LCPLL_E28_LOCK_BB                                                                            0x020368UL //Access:R    DataWidth:0x1    // LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset.
+#define IPC_REG_SLEW_IO_CONTROL_K2_E5                                                                        0x02036cUL //Access:RW   DataWidth:0x2    // Sets the SL# (# in [0..1]) I/Os of the PADS in non - scan/mbist modes
+#define IPC_REG_LCPLL_E28_STATUS_BB                                                                          0x02036cUL //Access:R    DataWidth:0xc    // Internal Status Bits of the PLL Global register. Reset on POR reset.
+#define IPC_REG_BISR_DEBUG_K2_E5                                                                             0x020370UL //Access:R    DataWidth:0x14   // debug from bisr
+#define IPC_REG_PMFC_DVT_EN_BB                                                                               0x020370UL //Access:RW   DataWidth:0x1    // Enable the MAC SERDES
+#define IPC_REG_ECO_RESERVED_K2_E5                                                                           0x020374UL //Access:RW   DataWidth:0x20   // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
+#define IPC_REG_PMFC_DVT_IDDQ_BB                                                                             0x020374UL //Access:RW   DataWidth:0x1    // MAC SERDES IDDQ
+#define IPC_REG_PMFC_DVT_PWRDWN_BB                                                                           0x020378UL //Access:RW   DataWidth:0x1    // MAC SERDES Power Down
+#define IPC_REG_PMFC_DVT_REFIN_EN_BB                                                                         0x02037cUL //Access:RW   DataWidth:0x1    // 
+#define IPC_REG_PMFC_DVT_REFOUT_EN_BB                                                                        0x020380UL //Access:RW   DataWidth:0x1    // 
+#define IPC_REG_PMFC_DVT_TSC_RESET_BB                                                                        0x020384UL //Access:RW   DataWidth:0x1    // 
+#define IPC_REG_PMFC_DVT_MDIO_FAST_MODE_BB                                                                   0x020388UL //Access:RW   DataWidth:0x1    // 
+#define IPC_REG_PMFC_PHY_ADDR_BB                                                                             0x02038cUL //Access:RW   DataWidth:0x5    // MDIO PHY Address. The SERDES uses this address to determine whether or not it is the recipient of the message on the MDIO interface.
+#define IPC_REG_PMFC_TX_DRV_HV_DISABLE_BB                                                                    0x020390UL //Access:RW   DataWidth:0x1    // 1 : Disable high voltage for Tx Driver
+#define IPC_REG_PMFC_BOND_OPTION_BB                                                                          0x020394UL //Access:RW   DataWidth:0x9    // Bonding option for PM Falcon
+#define IPC_REG_PMFC_PLL_LOCK_BB                                                                             0x020398UL //Access:R    DataWidth:0x1    // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global register.
+#define IPC_REG_PMFC_RECOVER_CLOCK_LOCK_BB                                                                   0x02039cUL //Access:R    DataWidth:0x4    // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global register.
+#define IPC_REG_PMEG_DVT_EN_BB                                                                               0x0203a0UL //Access:RW   DataWidth:0x1    // Enable the MAC SERDES
+#define IPC_REG_PMEG_DVT_IDDQ_BB                                                                             0x0203a4UL //Access:RW   DataWidth:0x1    // MAC SERDES IDDQ
+#define IPC_REG_PMEG_DVT_PWRDWN_BB                                                                           0x0203a8UL //Access:RW   DataWidth:0x1    // MAC SERDES Power Down
+#define IPC_REG_PMEG_DVT_REFIN_EN_BB                                                                         0x0203acUL //Access:RW   DataWidth:0x1    // 
+#define IPC_REG_PMEG_DVT_REFOUT_EN_BB                                                                        0x0203b0UL //Access:RW   DataWidth:0x1    // 
+#define IPC_REG_PMEG_DVT_TSC_RESET_BB                                                                        0x0203b4UL //Access:RW   DataWidth:0x1    // 
+#define IPC_REG_PMEG_DVT_MDIO_FAST_MODE_BB                                                                   0x0203b8UL //Access:RW   DataWidth:0x1    // 
+#define IPC_REG_PMEG_PHY_ADDR_BB                                                                             0x0203bcUL //Access:RW   DataWidth:0x5    // MDIO PHY Address. The SERDES uses this address to determine whether or not it is the recipient of the message on the MDIO interface.
+#define IPC_REG_PMEG_BOND_OPTION_BB                                                                          0x0203c0UL //Access:RW   DataWidth:0xd    // Bonding option for PM Eagle
+#define IPC_REG_PMEG_PLL_LOCK_BB                                                                             0x0203c4UL //Access:R    DataWidth:0x1    // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global register.
+#define IPC_REG_PMEG_RECOVER_CLOCK_LOCK_BB                                                                   0x0203c8UL //Access:R    DataWidth:0x4    // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global register.
+#define IPC_REG_PCIE_PIPE_PLL_LOCK_BB                                                                        0x0203ccUL //Access:R    DataWidth:0x8    // PCIe lock signals. 0-unlocked; 1-locked. Global register.
+#define IPC_REG_PCIES_PIPE_IDDQ_BB                                                                           0x0203d0UL //Access:RW   DataWidth:0x1    // 
+#define IPC_REG_PCIES_RESETMDIO_N_BB                                                                         0x0203d4UL //Access:RW   DataWidth:0x1    // 
+#define IPC_REG_PCIES_ALT_CLK_SELECT_BB                                                                      0x0203d8UL //Access:RW   DataWidth:0x1    // 
+#define IPC_REG_SGMII_RESETS_BB                                                                              0x0203dcUL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define IPC_REG_SGMII_RESETS_SGMII_RST_HW_BB                                                               (0x1<<0) // 1 : Reset the entire SGMII Core. Global Register, Reset on POR
+  #define IPC_REG_SGMII_RESETS_SGMII_RST_HW_BB_SHIFT                                                         0
+  #define IPC_REG_SGMII_RESETS_SGMII_RST_MDIO_BB                                                             (0x1<<1) // 1 : Reset the MDIO Registers. Global Register, Reset on POR
+  #define IPC_REG_SGMII_RESETS_SGMII_RST_MDIO_BB_SHIFT                                                       1
+  #define IPC_REG_SGMII_RESETS_SGMII_RST_PLL_BB                                                              (0x1<<2) // 1 : Resets the PLL and digital logic.. Global Register, Reset on POR
+  #define IPC_REG_SGMII_RESETS_SGMII_RST_PLL_BB_SHIFT                                                        2
+#define IPC_REG_SGMII_MD_DEVAD_BB                                                                            0x0203e0UL //Access:RW   DataWidth:0x5    // Device Address Global Register, Reset on POR
+#define IPC_REG_SGMII_MD_ST_BB                                                                               0x0203e4UL //Access:RW   DataWidth:0x1    // 0 : CL22 1 : CL45 Global Register, Reset on POR
+#define IPC_REG_SGMII_PHY_ADDR_BB                                                                            0x0203e8UL //Access:RW   DataWidth:0x5    // PHY Address for MDIO Transaction Global Register, Reset on POR
+#define IPC_REG_SGMII_PWRDWN_BB                                                                              0x0203ecUL //Access:RW   DataWidth:0x1    // 1 : powers down for the analog front end and turns off all clocks except refclk. MDIO is operational Global Register, Reset on POR
+#define IPC_REG_SGMII_IDDQ_BB                                                                                0x0203f0UL //Access:RW   DataWidth:0x1    // 1 : iddq enable, powers down analog and turns off all clocks. MDIO is not operational Global Register, Reset on POR
+#define IPC_REG_SGMII_REFSEL_BB                                                                              0x0203f4UL //Access:RW   DataWidth:0x3    // TBD. Global Register, Reset on POR
+#define IPC_REG_SGMII_STATUS_BB                                                                              0x0203f8UL //Access:R    DataWidth:0xd    // Multi Field Register.
+  #define IPC_REG_SGMII_STATUS_SGMII_LINK_STATUS_BB                                                          (0x1<<0) // Link Status 1: Link has been achieve Global Register, Reset on POR
+  #define IPC_REG_SGMII_STATUS_SGMII_LINK_STATUS_BB_SHIFT                                                    0
+  #define IPC_REG_SGMII_STATUS_SGMII_RX_SIGDET_BB                                                            (0x1<<1) // Signal Detect Global Register, Reset on POR
+  #define IPC_REG_SGMII_STATUS_SGMII_RX_SIGDET_BB_SHIFT                                                      1
+  #define IPC_REG_SGMII_STATUS_SGMII_RX_SEQDONE1G_BB                                                         (0x1<<2) // 1: Bit Alignment Done Global Register, Reset on POR
+  #define IPC_REG_SGMII_STATUS_SGMII_RX_SEQDONE1G_BB_SHIFT                                                   2
+  #define IPC_REG_SGMII_STATUS_SGMII_SYNC_STATUS_BB                                                          (0x1<<3) // 1: Symbol Alignment Global Register, Reset on POR
+  #define IPC_REG_SGMII_STATUS_SGMII_SYNC_STATUS_BB_SHIFT                                                    3
+  #define IPC_REG_SGMII_STATUS_SGMII_SPEED_10_BB                                                             (0x1<<4) // 1: Speed is 10M Global Register, Reset on POR
+  #define IPC_REG_SGMII_STATUS_SGMII_SPEED_10_BB_SHIFT                                                       4
+  #define IPC_REG_SGMII_STATUS_SGMII_SPEED_100_BB                                                            (0x1<<5) // 1: Speed is 100M Global Register, Reset on POR
+  #define IPC_REG_SGMII_STATUS_SGMII_SPEED_100_BB_SHIFT                                                      5
+  #define IPC_REG_SGMII_STATUS_SGMII_SPEED_1000_BB                                                           (0x1<<6) // 1: Speed is 1G Global Register, Reset on POR
+  #define IPC_REG_SGMII_STATUS_SGMII_SPEED_1000_BB_SHIFT                                                     6
+  #define IPC_REG_SGMII_STATUS_SGMII_TXPLL_LOCK_BB                                                           (0x1<<8) // 1: PLL is locked Global Register, Reset on POR
+  #define IPC_REG_SGMII_STATUS_SGMII_TXPLL_LOCK_BB_SHIFT                                                     8
+  #define IPC_REG_SGMII_STATUS_SGMII_MODE_BB                                                                 (0x1<<12) // 1: Running in SGMII mode. Global Register, Reset on POR
+  #define IPC_REG_SGMII_STATUS_SGMII_MODE_BB_SHIFT                                                           12
+#define IPC_REG_PM_TMON_CTRL_BB                                                                              0x0203fcUL //Access:RW   DataWidth:0x3    // Control the Bandgap voltage of the monitor
+#define IPC_REG_PM_TMON_ENA_BB                                                                               0x020400UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define IPC_REG_PM_TMON_ENA_PM_TMON_RESET_BB                                                               (0x1<<0) // 1 : Reset the VTMON registers.
+  #define IPC_REG_PM_TMON_ENA_PM_TMON_RESET_BB_SHIFT                                                         0
+  #define IPC_REG_PM_TMON_ENA_PM_TMON_PWRDN_BB                                                               (0x1<<1) // 1 : Hold the VTMON in powerdown state.
+  #define IPC_REG_PM_TMON_ENA_PM_TMON_PWRDN_BB_SHIFT                                                         1
+#define IPC_REG_PM_TMON_HOLD_BB                                                                              0x020404UL //Access:RW   DataWidth:0x1    // Voltage/Temperature Monitor hold. 0 - update; 1 - hold on to the value forever. Global register. Reset on POR reset.
+#define IPC_REG_PM_TMON_DATA_BB                                                                              0x020408UL //Access:R    DataWidth:0xa    // Voltage/Temperature Monitor output.Global register. Reset on POR reset.
+#define IPC_REG_PCIE_TMON_CTRL_BB                                                                            0x02040cUL //Access:RW   DataWidth:0x3    // Control the Bandgap voltage of the monitor
+#define IPC_REG_PCIE_TMON_ENA_BB                                                                             0x020410UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define IPC_REG_PCIE_TMON_ENA_PCIE_TMON_RESET_BB                                                           (0x1<<0) // 1 : Reset the VTMON registers.
+  #define IPC_REG_PCIE_TMON_ENA_PCIE_TMON_RESET_BB_SHIFT                                                     0
+  #define IPC_REG_PCIE_TMON_ENA_PCIE_TMON_PWRDN_BB                                                           (0x1<<1) // 1 : Hold the VTMON in powerdown state.
+  #define IPC_REG_PCIE_TMON_ENA_PCIE_TMON_PWRDN_BB_SHIFT                                                     1
+#define IPC_REG_PCIE_TMON_HOLD_BB                                                                            0x020414UL //Access:RW   DataWidth:0x1    // Voltage/Temperature Monitor hold. 0 - update; 1 - hold on to the value forever. Global register. Reset on POR reset.
+#define IPC_REG_PCIE_TMON_DATA_BB                                                                            0x020418UL //Access:R    DataWidth:0xa    // Voltage/Temperature Monitor output.Global register. Reset on POR reset.
+#define IPC_REG_RESCAL_E28_PWRDN_BB                                                                          0x02041cUL //Access:RW   DataWidth:0x1    // Powerdown the Rescal 0: Normal Operation Mode 1: Powerdown the RESCAL block Transition from 1->0 to start calibration Global Register, Reset on POR
+#define IPC_REG_RESCAL_E28_RST_BB                                                                            0x020420UL //Access:RW   DataWidth:0x1    // Reset the RESCAL block 0: Normal Operation Mode 1: Reset the RESCAL block Global Register, Reset on POR
+#define IPC_REG_RESCAL_E28_OVERRIDE_BB                                                                       0x020424UL //Access:RW   DataWidth:0x1    // By Setting this bit, FW takes control of the RESCAL block manitpulates the pwrdn and reset signals to start its own calibration. 0: Normal Operation Mode 1: FW override Global Register, Reset on POR
+#define IPC_REG_RESCAL_E28_RESTART_CALIBRATION_BB                                                            0x020428UL //Access:RW   DataWidth:0x1    // Setting this bit starts the HW based calibration engine to recalibrate the rescal block. 0: Normal Operation Mode 1: Restart the calibration Global Register, Reset on POR
+#define IPC_REG_RESCAL_E28_DIAG_ON_BB                                                                        0x02042cUL //Access:RW   DataWidth:0x1    // 0: Normal Operation Mode 1: Freeze Internal Digital ciruit Global Register, Reset on POR
+#define IPC_REG_RESCAL_E28_CTRL_BB                                                                           0x020430UL //Access:RW   DataWidth:0xd    // [12:11] inversion of compcrradj[1:0] to analog [10] inversion of vrefs to analog [9] wait time after increasing pon 1'b0: 8 refclk 1'b1: 16 refclk [8:7] power-up time before starting calibration 2'b00: 32 refclk = 1.28us 2'b01: 128 refclk = 5.12us 2'b10: 256 refclk = 10.24us 2'b11: 8 refclk = 320ns [6:5] resistor comparison accumulation time 2'b00: 16 refclk 2'b01: 32 refclk 2'b10: 8 refclk [4:1] override resistor pon value when [0] is asserted 0000: min resistance -24%~-21% 1111: max resistance +21%~+24% [0] 1: override pon value to analog 0: normal mode Global Register, Reset on POR
+#define IPC_REG_RESCAL_E28_STATUS_BB                                                                         0x020434UL //Access:R    DataWidth:0x2    // Multi Field Register.
+  #define IPC_REG_RESCAL_E28_STATUS_RESCAL_E28_CALIB_DONE_BB                                                 (0x1<<0) // Indicates if the calibraion operation is done. 0: Calibration in progress 1: Calibration Done Global Register, Reset on POR
+  #define IPC_REG_RESCAL_E28_STATUS_RESCAL_E28_CALIB_DONE_BB_SHIFT                                           0
+  #define IPC_REG_RESCAL_E28_STATUS_RESCAL_E28_VALID_BB                                                      (0x1<<1) // Indicates if the pon data is valid when calib_done is set 0: Data is invalid 1: Data is valid Global Register, Reset on POR
+  #define IPC_REG_RESCAL_E28_STATUS_RESCAL_E28_VALID_BB_SHIFT                                                1
+#define IPC_REG_RESCAL_E28_PON_BB                                                                            0x020438UL //Access:R    DataWidth:0x4    // pon value; stable after rescal is done or o_done is asserted Output On-chip Sheet Resistance 0000 -24% ~ -21% 0001 -21% ~ -18% 0010 -18% ~ -15% 0011 -15% ~ -12% 0100 -12% ~ -9% 0101 -9% ~ -6% 0110 -6% ~ -3% 0111    -3% ~ +0% 1000    +0% ~ +3% 1001 +3% ~ +6% 1010 +6% ~ +9% 1011 +9% ~ +12% 1100 +12% ~ +15% 1101 +15% ~ +18% 1110 +18% ~ +21% 1111 +21% ~ +24% Global Register, Reset on POR
+#define IPC_REG_RESCAL_E28_CURR_COMP_CNT_BB                                                                  0x02043cUL //Access:R    DataWidth:0x6    // accumulated comparison for current pon value Global Register, Reset on POR
+#define IPC_REG_RESCAL_E28_PREV_COMP_CNT_BB                                                                  0x020440UL //Access:R    DataWidth:0x4    // accumulated comparison for previous pon value Global Register, Reset on POR
+#define IPC_REG_RESCAL_E28_COMP_BB                                                                           0x020444UL //Access:R    DataWidth:0x1    // RESCAL Comp Value Global Register, Reset on POR
+#define IPC_REG_RESCAL_E28_CTRL_DFS_BB                                                                       0x020448UL //Access:R    DataWidth:0xd    // default values for the rescal control signals. Global Register, Reset on POR
+#define IPC_REG_RESCAL_E28_STATE_BB                                                                          0x02044cUL //Access:R    DataWidth:0x3    // Internal State machine status 0: INIT 1: WAIT_PWRUP 2: COMP_ACC 3: WAIT_PON_INC 4: CAL_DONE Global Register, Reset on POR
+#define IPC_REG_RESCAL_E28_FSM_STATE_BB                                                                      0x020450UL //Access:R    DataWidth:0x3    // External State machine status 0: POR 1: INIT 2: RESET 3: PWRDN 4: CALIB 5: PONVALID 6: RESULT 7: IDLE Global Register, Reset on POR
+#define IPC_REG_SWREG_VMGMT_E28_PWRDN_BB                                                                     0x020454UL //Access:RW   DataWidth:0x1    // Powerdown the VManagement Switching Regulator 0: Normal Operation Mode 1: Powerdown the SWREG block Global Register, Reset on POR
+#define IPC_REG_SWREG_VMGMT_E28_REG_RESET_BB                                                                 0x020458UL //Access:RW   DataWidth:0x1    // Reset the Registers in VManagement Switching Regulator 0: Normal Operation Mode 1: Reset the switchin regulator block Global Register, Reset on POR
+#define IPC_REG_SWREG_VMGMT_E28_STABLE_BB                                                                    0x02045cUL //Access:R    DataWidth:0x1    // 1: PMU is stable Global Register, Reset on POR
+#define IPC_REG_SWREG_VMAIN_E28_PWRDN_BB                                                                     0x020460UL //Access:RW   DataWidth:0x1    // Powerdown the VMain Switching Regulator 0: Normal Operation Mode 1: Powerdown the SWREG block Global Register, Reset on POR
+#define IPC_REG_SWREG_VMAIN_E28_REG_RESET_BB                                                                 0x020464UL //Access:RW   DataWidth:0x1    // Reset the Registers in VMain Switching Regulator 0: Normal Operation Mode 1: Reset the switchin regulator block Global Register, Reset on POR
+#define IPC_REG_SWREG_VMAIN_E28_STABLE_BB                                                                    0x020468UL //Access:R    DataWidth:0x1    // 1: PMU is stable Global Register, Reset on POR
+#define IPC_REG_SWREG_VANALOG_E28_PWRDN_BB                                                                   0x02046cUL //Access:RW   DataWidth:0x1    // Powerdown the VAnalog Switching Regulator 0: Normal Operation Mode 1: Powerdown the SWREG block Global Register, Reset on POR
+#define IPC_REG_SWREG_VANALOG_E28_REG_RESET_BB                                                               0x020470UL //Access:RW   DataWidth:0x1    // Reset the Registers in VAnalog Switching Regulator 0: Normal Operation Mode 1: Reset the switchin regulator block Global Register, Reset on POR
+#define IPC_REG_SWREG_VANALOG_E28_STABLE_BB                                                                  0x020474UL //Access:R    DataWidth:0x1    // 1: PMU is stable Global Register, Reset on POR
+#define IPC_REG_SWREG_V1P8_E28_PWRDN_BB                                                                      0x020478UL //Access:RW   DataWidth:0x1    // Powerdown the V1p8 Switching Regulator 0: Normal Operation Mode 1: Powerdown the SWREG block Global Register, Reset on POR
+#define IPC_REG_SWREG_V1P8_E28_REG_RESET_BB                                                                  0x02047cUL //Access:RW   DataWidth:0x1    // Reset the Registers in V1p8 Switching Regulator 0: Normal Operation Mode 1: Reset the switchin regulator block Global Register, Reset on POR
+#define IPC_REG_SWREG_V1P8_E28_STABLE_BB                                                                     0x020480UL //Access:R    DataWidth:0x1    // 1: PMU is stable Global Register, Reset on POR
+#define IPC_REG_SWREG_SYNC_CLK_SELECT_BB                                                                     0x020484UL //Access:RW   DataWidth:0x1    // All three SWREG with external FETs are sync'ed such that they are running on different phases of alternate clock. This lowers the overall power consumption. 1: Select 1Mhz Clock 0: Select 500Khz Clock Global Register, Reset on POR
+#define IPC_REG_SWREG_SYNC_CLK_EN_BB                                                                         0x020488UL //Access:RW   DataWidth:0x1    // Setting this bit to "1" will enable the phase shift logic betweent the three swreg to start working. Global Register, Reset on POR
+#define IPC_REG_NW_SERDES_MDIO_COMM_BB                                                                       0x020498UL //Access:RW   DataWidth:0x1e   // [29] -> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO transaction will activate. When the operation is complete, this bit will clear and the MI_COMPLETE bit will be set in the status register. Writing this bit as a '0' has no effect. This bit must be read as a '0' before setting to prevent un-predictable results. [28] -> FAIL This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction. [27:26] -> COMMAND 1 -> Write 2 -> Read [25:21] -> PHY_ADDR This value is used to define the PHY address portion of the MDIO transaction 1 -> SWREG VMGMT 2 -> SWREG VMAIN 3 -> SWREG VANALOG 4 -> SWREG V1p8 [20:16] -> REG_ADDR This value is used to define the register address portion of the MDIO transaction [15:0]  -> DATA When this register is read, it returns the results of the last MDIO transaction that was performed. When this register value is written, it updates the value that will be used on the next MDIO write transaction that will be performed.
+#define IPC_REG_NW_SERDES_MDIO_STATUS_BB                                                                     0x02049cUL //Access:R    DataWidth:0x2    // [0] -> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the next transaction starts. [1] -> FAIL This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction.
+#define IPC_REG_NW_SERDES_MDIO_MODE_BB                                                                       0x0204a0UL //Access:RW   DataWidth:0x16   // [21:12] -> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency equal to CORE_CLK/(2*(CLOCK_CNT+1)). A value of 0 is invalid for this register. [11] -> MDC Setting this bit to '1' will cause the MDC pin to high if the BIT_BANG bit is set. . Setting this pin low will cause the MDC pin to drive low if the BIT_BANG bit is set. [10] -> MDIO_OE Setting this bit to '1' will cause the MDIO pin to drive the value written to the MDIO bit if the BIT_BANG bit is set. Setting this bit to zero will make the MDIO pin an input. [9] -> MDIO The write value of this bit controls the drive state of the MDIO pin if the BIT_BANG bit is set. The read value of this bit always reflects the state of the MDIO pin. [8] -> BIT_BANG If this bit is '1', the MDIO interface is controlled by the MDIO, MDIO_OE, and MDC bits in this register. When this bit is '0', the commands in the mdio_cmd register will be executed. [0] -> FREE_DIS 1 -> Diable Free running MDIO clock All other field in the register are reserved
+#define IPC_REG_FREQ_NW_BB                                                                                   0x0204b0UL //Access:R    DataWidth:0x11   // Multi Field Register.
+  #define IPC_REG_FREQ_NW_CNT_BB                                                                             (0xffff<<0) // This field shows the frequency counter for main clock over a 10uS interval. NW Clock Frequency = ~(FreqCnt / 10)MHz. This field is not reset between measurements. For example, it shows X MHz in first measurement, 2*X in second measurement, 3*X MHz in third measurement.
+  #define IPC_REG_FREQ_NW_CNT_BB_SHIFT                                                                       0
+  #define IPC_REG_FREQ_NW_CNT_VALID_BB                                                                       (0x1<<16) // 0: Value in freq_cnt field is not valid 1: Value in freq_cnt field is valid
+  #define IPC_REG_FREQ_NW_CNT_VALID_BB_SHIFT                                                                 16
+#define IPC_REG_OTP_CONFIG_0_BB                                                                              0x0204e8UL //Access:R    DataWidth:0x20   // These bits represent the 256-bits of the configuration space in the OTP that is read out at POR.
+#define IPC_REG_OTP_CONFIG_1_BB                                                                              0x0204ecUL //Access:R    DataWidth:0x20   // These bits represent the 256-bits of the configuration space in the OTP that is read out at POR.
+#define IPC_REG_OTP_CONFIG_2_BB                                                                              0x0204f0UL //Access:R    DataWidth:0x20   // These bits represent the 256-bits of the configuration space in the OTP that is read out at POR.
+#define IPC_REG_OTP_CONFIG_3_BB                                                                              0x0204f4UL //Access:R    DataWidth:0x20   // These bits represent the 256-bits of the configuration space in the OTP that is read out at POR.
+#define IPC_REG_OTP_CONFIG_4_BB                                                                              0x0204f8UL //Access:R    DataWidth:0x20   // These bits represent the 256-bits of the configuration space in the OTP that is read out at POR.
+#define IPC_REG_OTP_CONFIG_5_BB                                                                              0x0204fcUL //Access:R    DataWidth:0x20   // These bits represent the 256-bits of the configuration space in the OTP that is read out at POR.
+#define IPC_REG_OTP_CONFIG_6_BB                                                                              0x020500UL //Access:R    DataWidth:0x20   // These bits represent the 256-bits of the configuration space in the OTP that is read out at POR.
+#define IPC_REG_OTP_CONFIG_7_BB                                                                              0x020504UL //Access:R    DataWidth:0x20   // These bits represent the 256-bits of the configuration space in the OTP that is read out at POR.
+#define IPC_REG_PRTY_MASK_BB                                                                                 0x020520UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define IPC_REG_PRTY_MASK_FAKE_PAR_ERR_BB                                                                  (0x1<<0) // This bit masks, when set, the Parity bit: IPC_REG_PRTY_STS.FAKE_PAR_ERR .
+  #define IPC_REG_PRTY_MASK_FAKE_PAR_ERR_BB_SHIFT                                                            0
+#define IPC_REG_LCPLL_REFCLK_SEL_BB                                                                          0x02052cUL //Access:RW   DataWidth:0x1    // Selects the reference clock for the PLL 0= CMOS Reference clock, output of the differential oscillator 1= CML reference clock, from the chip pins Global register. Reset on POR reset.
+#define IPC_REG_OTP_ECC_DED_FLAG_BB                                                                          0x020530UL //Access:R    DataWidth:0x8    // Fdone Double Error Detection status flag      for each AUTOLOAD word
+#define IPC_REG_OTP_ECC_SEC_FLAG_BB                                                                          0x020534UL //Access:R    DataWidth:0x8    // Fdone Single Error Correction status flag for      each AUTOLOAD word
+#define IPC_REG_OTP_ECC_SEC_LATCH_BB                                                                         0x020538UL //Access:R    DataWidth:0x8    // Fdone Single Error Correction status latch.                         If Single Error Correction status flag was 1, this bit is latched with value 1.
+#define IPC_REG_CPU_OTP_RD_SYNDROME_BB                                                                       0x02053cUL //Access:R    DataWidth:0x7    // Syndrome output from the OTP read data command.
+#define CPMU_REG_LPI_MODE_CONFIG                                                                             0x030200UL //Access:RW   DataWidth:0x1    // 0 : LPI is not enabled. 1 : LPI is enabled, LPI_REQ will be generated by the transmitter.
+#define CPMU_REG_LPI_BNB_MODE                                                                                0x030204UL //Access:RW   DataWidth:0x1    // Setting this bit will enable a special Batch and Burst mode in the LPI request logic. When this mode is enabled, CPMU will not exit LPI at the earliest indication (L1 exit or DORQ event for ex) but rather wait for BTB to be filled with a certain threshold bytes and then exit LPI. This allows for the system to not wake up just to send a single packet for ex and go back to LPI state. In this mode, the LPI exit can also happen after a programmable time tha the first packet is in the Tx Pipeline.
+#define CPMU_REG_LPI_MODE_SLEEP_THRESHOLD                                                                    0x030208UL //Access:RW   DataWidth:0x20   // This register sets the Sleep Threshold for the LPI mode. When the transmitter is IDLE, CPMU will wait for the sleep threshold to expire before setting the LPI request to the map. The resolution of this register is 40ns. Values of 0 and 1 are not supported.
+#define CPMU_REG_LPI_BNB_MODE_SLEEP_THRESHOLD                                                                0x03020cUL //Access:RW   DataWidth:0x20   // This register sets the Sleep Threshold for the LPI mode in the Batch and Burst mode. LPI exit logic will wait for this time before exiting LPI. The resolution of this register is 40ns. Values of 0 and 1 are not supported.
+#define CPMU_REG_LPI_MODE_ENTRY_EN                                                                           0x030210UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_PBF_EMPTY_EN                                                        (0x1<<0) // 0 : PBF Empty is not part of LPI request generation logic. 1 : PBF Empty is part of LPI request generation logic.
+  #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_PBF_EMPTY_EN_SHIFT                                                  0
+  #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_QM_EMPTY_EN                                                         (0x1<<1) // 0 : QM Empty is not part of LPI request generation logic. 1 : QM Empty is part of LPI request generation logic. QM Empty only includes Network traffic for that port. Loopback traffic is not part of the LPI equation.
+  #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_QM_EMPTY_EN_SHIFT                                                   1
+  #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_ALL_SQ_EMPTY_EN                                                     (0x1<<2) // 0 : All Send Queue Empty is not part of LPI request generation logic. 1 : All Send Queue Empty is part of LPI request generation logic.
+  #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_ALL_SQ_EMPTY_EN_SHIFT                                               2
+  #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_MGMT_EMPTY_EN                                                       (0x1<<3) // 0 : Management Traffic is not part of LPI request generation logic. 1 : Management Traffic is part of LPI request generation logic.
+  #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_MGMT_EMPTY_EN_SHIFT                                                 3
+  #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_RX_LPI_STATUS_EN                                                    (0x1<<4) // 0 : LPI receive status is not part of LPI request generation logic. 1 : LPI receive status is part of LPI request generation logic.
+  #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_RX_LPI_STATUS_EN_SHIFT                                              4
+  #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_OBFF_STATE_EN                                                       (0x1<<5) // 0 : OBFF State (non CPU_ACTIVE) is not part of LPI request generation logic. 1 : OBFF State (non CPU_ACTIVE) is part of LPI request generation logic.
+  #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_OBFF_STATE_EN_SHIFT                                                 5
+  #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_PCIE_IN_D3_EN                                                       (0x1<<6) // 0 : PCIe in D3 State is not part of LPI request generation logic. 1 : PCIe in D3 State is part of LPI request generation logic.
+  #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_PCIE_IN_D3_EN_SHIFT                                                 6
+  #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_NIG_TX_EMPTY_EN                                                     (0x1<<7) // 0 : NIG Tx is empty is not part of LPI request generation logic. 1 : NIG Tx is empty is part of LPI request generation logic.
+  #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_NIG_TX_EMPTY_EN_SHIFT                                               7
+#define CPMU_REG_LPI_MODE_EXIT_EN                                                                            0x030214UL //Access:RW   DataWidth:0x7    // Multi Field Register.
+  #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_DORQ_EVENT_EN                                                        (0x1<<0) // 0 : DORQ Event is not part of the equation to exit LPI. 1 : DORQ Event is part of the equation to exit LPI.
+  #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_DORQ_EVENT_EN_SHIFT                                                  0
+  #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_NCSI_EVENT_EN                                                        (0x1<<1) // 0 : NCSI Event is not part of the equation to exit LPI. 1 : NCSI Event is part of the equation to exit LPI.
+  #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_NCSI_EVENT_EN_SHIFT                                                  1
+  #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_PCIE_L1_EXIT_EN                                                      (0x1<<2) // 0 : PCIe L1 exit is not part of the equation to exit LPI. 1 : PCIe L1 exit is part of the equation to exit LPI.
+  #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_PCIE_L1_EXIT_EN_SHIFT                                                2
+  #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_PBF_ALMOST_FULL_EN                                                   (0x1<<3) // This bit will be used in the Batch and Burst mode. In this mode, 0 : pbf almost full is not part of the equation to exit LPI. 1 : pbf almost full is part of the equation to exit LPI.
+  #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_PBF_ALMOST_FULL_EN_SHIFT                                             3
+  #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_BMB_ALMOST_FULL_EN                                                   (0x1<<4) // This bit will be used in the Batch and Burst mode. In this mode, 0 : BMB almost full is not part of the equation to exit LPI. 1 : BMB almost full is part of the equation to exit LPI.
+  #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_BMB_ALMOST_FULL_EN_SHIFT                                             4
+  #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_SQ_EARLY_EXIT_EN                                                     (0x1<<5) // This bit will be used in the Normal mode. In this mode, 0 : Early exit indication from X or USTORM is not part of the LPI exit equation. 1 : When early exit is indicated either by XSTORM or USTORM, LPI will exit.
+  #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_SQ_EARLY_EXIT_EN_SHIFT                                               5
+  #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_RX_LPI_STATUS_EXIT_EN                                                (0x1<<6) // 0 : LPI receive status is not part of LPI request exit logic. 1 : LPI receive status is part of LPI request exit logic.
+  #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_RX_LPI_STATUS_EXIT_EN_SHIFT                                          6
+#define CPMU_REG_SW_FORCE_LPI                                                                                0x030218UL //Access:RW   DataWidth:0x1    // Setting this bit to "1" will allow software to force an LPI request on the interface. Clearing this bit will not automatically guarantee an exit from LPI if other elements in the LPI equation is causing an LPI request to go out. To do a forceful exit, SW needs to assert the sw_lpi_exit register.
+#define CPMU_REG_SW_LPI_EXIT                                                                                 0x03021cUL //Access:W    DataWidth:0x1    // Setting this bit to "1" will allow software to provide an early indication to exit LPI state. HW will generate a pulse on low to high transition of this register. The resultant bit is Self Clearing.
+#define CPMU_REG_OBFF_MODE_CONFIG                                                                            0x030220UL //Access:RW   DataWidth:0x1    // 0 : OBFF is not enabled. 1 : OBFF is enabled, DMA master requests could be stalled based on OBFF state machine.
+#define CPMU_REG_OBFF_MODE_CONTROL                                                                           0x030224UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_FORCE                                                              (0x1<<0) // Reserved.
+  #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_FORCE_SHIFT                                                        0
+  #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_ENGINE_IDLE_EN                                                     (0x1<<1) // 0: Engine IDLE is not part of the OBFF state logic. 1: Engine IDLE is part of the OBFF state logic.
+  #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_ENGINE_IDLE_EN_SHIFT                                               1
+  #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_DEVICE_IDLE_FORCE                                                  (0x1<<2) // Setting this bit forces the CPMU to force the device IDLE condition for OBFF operations.
+  #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_DEVICE_IDLE_FORCE_SHIFT                                            2
+  #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_IGU_PENDING_INTERRUPT_EN                                           (0x1<<3) // 0 : IGU Pending Interrupt is not part of OBFF logic w.r.t. IGU requests. 1 : IGU Pending Interrupt is part of OBFF logic w.r.t. IGU requests.
+  #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_IGU_PENDING_INTERRUPT_EN_SHIFT                                     3
+  #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_VOQ_IGU_REQUESTS_EN                                                (0x1<<4) // 0 : VOQ for IGU requests is not part of OBFF logic w.r.t. IGU requests. 1 : VOQ for IGU requests is part of OBFF logic w.r.t. IGU requests.
+  #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_VOQ_IGU_REQUESTS_EN_SHIFT                                          4
+  #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_INTERRUPTS_EN                                                      (0x1<<5) // 0 : Interrupts are not part of OBFF logic w.r.t. IGU requests. 1 : Interrupts are part of OBFF logic w.r.t. IGU requests.
+  #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_INTERRUPTS_EN_SHIFT                                                5
+  #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_OVERRIDE                                                           (0x3<<6) // 00 : OBFF state that was received from the CPU is applicable. 01 : Forces the CPMU to override the OBFF state that was received from the CPU. The override state is OBFF. 10 : Forces the CPMU to override the OBFF state that was received from the CPU. The override state is IDLE. 11:  Reserved.
+  #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_OVERRIDE_SHIFT                                                     6
+  #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_STALL_MEM_SET_VQ_EN                                                (0x1<<8) // 0 : For the FSM that drives stall_mem control, the control set logic is not conditioned with VOQ empty. 1 : For the FSM that drives stall_mem control, the control set logic is conditioned with VOQ empty.
+  #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_STALL_MEM_SET_VQ_EN_SHIFT                                          8
+  #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_STALL_INT_SET_INT_EN                                               (0x1<<9) // 0 : For the FSM that drives stall_int control, the control set logic is not conditioned with VOQ empty / Interrupt Deasserted / No Pending Interrupt. 1 : For the FSM that drives stall_int control, the control set logic is conditioned with VOQ empty / Interrupt Deasserted / No Pending Interrupt.
+  #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_STALL_INT_SET_INT_EN_SHIFT                                         9
+#define CPMU_REG_SW_OBFF_EXIT                                                                                0x030228UL //Access:W    DataWidth:0x1    // Setting this bit to "1" will allow software to force an exit from the OBFF related stalls. HW will generate a pulse on low to high transition of this register. The resultant bit is Self Clearing.
+#define CPMU_REG_OBFF_MEM_TIMER_SHORT_THRESHOLD                                                              0x03022cUL //Access:RW   DataWidth:0x20   // This register sets the short timer threshold for OBFF operation w.r.t memory requests in 40ns resolution. The OBFF state machine will launch a timer when memory requests are stalled. The Timer expires when it reaches this threshold and stall state is exited. Values of 0 and 1 are not supported
+#define CPMU_REG_OBFF_MEM_TIMER_LONG_THRESHOLD                                                               0x030230UL //Access:RW   DataWidth:0x20   // This register sets the long timer threshold for OBFF operation w.r.t memory requests in 40ns resolution. The OBFF state machine will launch a timer when memory requests are stalled. The Timer expires when it reaches this threshold and stall state is exited. Values of 0 and 1 are not supported.
+#define CPMU_REG_OBFF_INT_TIMER_SHORT_THRESHOLD                                                              0x030234UL //Access:RW   DataWidth:0x20   // This register sets the short timer threshold for OBFF operation w.r.t IGU requests in 40ns resolution. The OBFF state machine will launch a timer when IGU requests are stalled. The Timer expires when it reaches this threshold and stall state is exited. Values of 0 and 1 are not supported.
+#define CPMU_REG_OBFF_INT_TIMER_LONG_THRESHOLD                                                               0x030238UL //Access:RW   DataWidth:0x20   // This register sets the long timer threshold for OBFF operation w.r.t IGU requests in 40ns resolution. The OBFF state machine will launch a timer when IGU requests are stalled. The Timer expires when it reaches this threshold and stall state is exited. Values of 0 and 1 are not supported.
+#define CPMU_REG_OBFF_STALL_ON_OBFF_STATE_0                                                                  0x03023cUL //Access:RW   DataWidth:0x20   // Setting each bit in this register to "1" will cause the CPMU to launch a timer when the corresponding VOQ is not empty and the system in the "OBFF" state. If a bit is not set and the corresponding VOQ is not empty, the stall state is removed immediately. This register correcponds to bits [31:0] of the VOQ bus.
+#define CPMU_REG_OBFF_STALL_ON_OBFF_STATE_1                                                                  0x030240UL //Access:RW   DataWidth:0x2    // Setting each bit in this register to "1" will cause the CPMU to launch a timer when the corresponding VOQ is not empty and the system in the "OBFF" state. If a bit is not set and the corresponding VOQ is not empty, the stall state is removed immediatelyempty. This register correcponds to bits [33:32] of the VOQ bus.
+#define CPMU_REG_OBFF_STALL_ON_IDLE_STATE_0                                                                  0x030244UL //Access:RW   DataWidth:0x20   // Setting each bit in this register to "1" will cause the CPMU to launch a timer when the corresponding VOQ is not empty and the system in the "IDLE" state. If a bit is not set and the corresponding VOQ is not empty, the stall state is removed immediately. This register correcponds to bits [31:0] of the VOQ bus.
+#define CPMU_REG_OBFF_STALL_ON_IDLE_STATE_1                                                                  0x030248UL //Access:RW   DataWidth:0x2    // Setting each bit in this register to "1" will cause the CPMU to launch a timer when the corresponding VOQ is not empty and the system in the "IDLE" state. If a bit is not set and the corresponding VOQ is not empty, the stall state is removed immediately. This register correcponds to bits [33:32] of the VOQ bus.
+#define CPMU_REG_OBFF_MODE_SLEEP_THRESHOLD                                                                   0x03024cUL //Access:RW   DataWidth:0x20   // This register sets the Sleep Threshold for entry to OBFF state. The resolution of this register is 40ns. Values of 0 and 1 are not supported.
+#define CPMU_REG_OBFF_MODE_ENTRY_EN                                                                          0x030250UL //Access:RW   DataWidth:0x15   // Multi Field Register.
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_PBF_EMPTY_EN                                                      (0x1<<0) // 0 : PBF Empty is not part of OBFF logic. 1 : PBF Empty is not part of OBFF logic.
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_PBF_EMPTY_EN_SHIFT                                                0
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_QM_EMPTY_TX_EN                                                    (0x1<<1) // 0 : QM Tx Empty is not part of OBFF logic. 1 : QM Tx Empty is part of OBFF logic.
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_QM_EMPTY_TX_EN_SHIFT                                              1
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_QM_EMPTY_GLOBAL_EN                                                (0x1<<2) // 0 : QM Global Empty is not part of main clock slowdown generation logic. 1 : QM Global Empty is part of main clock slowdown generation logic.
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_QM_EMPTY_GLOBAL_EN_SHIFT                                          2
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_ALL_SQ_EMPTY_EN                                                   (0x1<<3) // 0 : All Send Queue Empty is not part of OBFF logic. 1 : All Send Queue Empty is part of OBFF logic.
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_ALL_SQ_EMPTY_EN_SHIFT                                             3
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_MGMT_EMPTY_EN                                                     (0x1<<4) // 0 : Management Traffic is not part of OBFF logic. 1 : Management Traffic is part of OBFF logic.
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_MGMT_EMPTY_EN_SHIFT                                               4
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_BRB_EMPTY_EN                                                      (0x1<<5) // 0 : BRB empty is not part of OBFF logic. 1 : BRB empty is part of OBFF logic.
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_BRB_EMPTY_EN_SHIFT                                                5
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_PXP_EMPTY_EN                                                      (0x1<<6) // 0 : PXP empty is not part of OBFF logic. 1 : PXP empty is part of OBFF logic.
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_PXP_EMPTY_EN_SHIFT                                                6
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_CAU_IDLE_EN                                                       (0x1<<7) // 0 : CAU IDLE is not part of OBFF logic. 1 : CAU IDLE is part of OBFF logic.
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_CAU_IDLE_EN_SHIFT                                                 7
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_TM_SCAN_EN                                                        (0x1<<8) // 0 : Timer Scan status is not part of OBFF logic. 1 : Timer Scan status is part of OBFF logic.
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_TM_SCAN_EN_SHIFT                                                  8
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_OBFF_STATE_EN                                                     (0x1<<9) // 0 : OBFF State (non CPU_ACTIVE) is not part of OBFF logic. 1 : OBFF State (non CPU_ACTIVE) is part of OBFF logic.
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_OBFF_STATE_EN_SHIFT                                               9
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_TSEM_IDLE_EN                                                      (0x1<<10) // 0 : TSEM IDLE is not part of OBFF logic. 1 : TSEM IDLE is part of OBFF logic.
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_TSEM_IDLE_EN_SHIFT                                                10
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_MSEM_IDLE_EN                                                      (0x1<<11) // 0 : MSEM IDLE is not part of OBFF logic. 1 : MSEM IDLE is part of OBFF logic.
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_MSEM_IDLE_EN_SHIFT                                                11
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_USEM_IDLE_EN                                                      (0x1<<12) // 0 : USEM IDLE is not part of OBFF logic. 1 : USEM IDLE is part of OBFF logic.
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_USEM_IDLE_EN_SHIFT                                                12
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_XSEM_IDLE_EN                                                      (0x1<<13) // 0 : XSEM IDLE is not part of OBFF logic. 1 : XSEM IDLE is part of OBFF logic.
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_XSEM_IDLE_EN_SHIFT                                                13
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_YSEM_IDLE_EN                                                      (0x1<<14) // 0 : YSEM IDLE is not part of OBFF logic. 1 : YSEM IDLE is part of OBFF logic.
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_YSEM_IDLE_EN_SHIFT                                                14
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_PSEM_IDLE_EN                                                      (0x1<<15) // 0 : PSEM IDLE is not part of OBFF logic. 1 : PSEM IDLE is part of OBFF logic.
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_PSEM_IDLE_EN_SHIFT                                                15
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_RX_LPI_STATUS_EN                                                  (0x1<<16) // 0 : LPI receive status is not part of OBFF logic. 1 : LPI receive status is part of OBFF logic.
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_RX_LPI_STATUS_EN_SHIFT                                            16
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_NW_LINKDOWN_EN                                                    (0x1<<17) // 0 : Network Link Down is not part of OBFF logic. 1 : Network Link Down is part of OBFF logic.
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_NW_LINKDOWN_EN_SHIFT                                              17
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_NIG_RX_EMPTY_EN                                                   (0x1<<18) // 0 : NIG Rx Empty is not part of OBFF logic. 1 : NIG Rx Empty is part of OBFF logic.
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_NIG_RX_EMPTY_EN_SHIFT                                             18
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_NIG_TX_EMPTY_EN                                                   (0x1<<19) // 0 : NIG Tx Empty is not part of OBFF logic. 1 : NIG Tx Empty is part of OBFF logic.
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_NIG_TX_EMPTY_EN_SHIFT                                             19
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_NIG_LB_EMPTY_EN                                                   (0x1<<20) // 0 : NIG lb Empty is not part of OBFF logic. 1 : NIG lb Empty is part of OBFF logic.
+  #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_NIG_LB_EMPTY_EN_SHIFT                                             20
+#define CPMU_REG_OBFF_MODE_EXIT_EN                                                                           0x030254UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define CPMU_REG_OBFF_MODE_EXIT_EN_OBFF_PCIE_L1_EXIT_EN                                                    (0x1<<0) // 0 : PCIe L1 exit is not part of exit from OBFF logic 1 : PCIe L1 exit is part of exit from OBFF logic
+  #define CPMU_REG_OBFF_MODE_EXIT_EN_OBFF_PCIE_L1_EXIT_EN_SHIFT                                              0
+  #define CPMU_REG_OBFF_MODE_EXIT_EN_OBFF_DORQ_EVENT_EN                                                      (0x1<<1) // 0 : DORQ Event is not part of exit from OBFF logic 1 : DORQ Event is part of exit from OBFF logic
+  #define CPMU_REG_OBFF_MODE_EXIT_EN_OBFF_DORQ_EVENT_EN_SHIFT                                                1
+  #define CPMU_REG_OBFF_MODE_EXIT_EN_OBFF_SQ_EARLY_EXIT_EN                                                   (0x1<<2) // This bit will be used in the Normal mode. In this mode, 0 : Early exit indication from X or USTORM is not part of the OBFF exit equation. 1 : When early exit is indicated either by XSTORM or USTORM, OBFF will exit.
+  #define CPMU_REG_OBFF_MODE_EXIT_EN_OBFF_SQ_EARLY_EXIT_EN_SHIFT                                             2
+#define CPMU_REG_OBFF_IGU_VOQ_NUM                                                                            0x030258UL //Access:RW   DataWidth:0x6    // This register sets the VOQ number for IGU request. This is used to distinguish between memory and interrupt transactions.
+#define CPMU_REG_OBFF_VOQ_TIMEOUT_TYPE_0                                                                     0x03025cUL //Access:RW   DataWidth:0x20   // 0 : use the short timer threshold for the corresponding VOQ. 1 : use the long timer threshold for the corresponding VOQ. This register correcponds to bits [31:0] of the VOQ bus.
+#define CPMU_REG_OBFF_VOQ_TIMEOUT_TYPE_1                                                                     0x030260UL //Access:RW   DataWidth:0x2    // 0 : use the short timer threshold for the corresponding VOQ. 1 : use the long timer threshold for the corresponding VOQ. This register correcponds to bits [33:32] of the VOQ bus.
+#define CPMU_REG_L1_MODE_CONFIG                                                                              0x030264UL //Access:RW   DataWidth:0x1    // 0 : Entry to PCIe L1 is not enabled. 1 : Entry to PCIe L1 is enabled. This reflects the CPMU output and it is in addition to PCIE CORE register which controls entry to L1.
+#define CPMU_REG_L1_MODE_SLEEP_THRESHOLD                                                                     0x030268UL //Access:RW   DataWidth:0x20   // This register sets the Sleep Threshold for the L1 mode. The resolution of this register is 40ns. Value of 0 and 1 are not supported.
+#define CPMU_REG_L1_MODE_ENTRY_EN                                                                            0x03026cUL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define CPMU_REG_L1_MODE_ENTRY_EN_L1_PBF_EMPTY_EN                                                          (0x1<<0) // 0 : PBF Empty is not part of L1 request generation logic. 1 : PBF Empty is part of L1 request generation logic.
+  #define CPMU_REG_L1_MODE_ENTRY_EN_L1_PBF_EMPTY_EN_SHIFT                                                    0
+  #define CPMU_REG_L1_MODE_ENTRY_EN_L1_QM_EMPTY_TX_EN                                                        (0x1<<1) // 0 : QM Tx Empty is not part of L1 request generation logic. 1 : QM Tx Empty is part of L1 request generation logic.
+  #define CPMU_REG_L1_MODE_ENTRY_EN_L1_QM_EMPTY_TX_EN_SHIFT                                                  1
+  #define CPMU_REG_L1_MODE_ENTRY_EN_L1_QM_EMPTY_GLOBAL_EN                                                    (0x1<<2) // 0 : QM Global Empty is not part of L1 request generation logic. 1 : QM Global Empty is part of L1 request generation logic.
+  #define CPMU_REG_L1_MODE_ENTRY_EN_L1_QM_EMPTY_GLOBAL_EN_SHIFT                                              2
+  #define CPMU_REG_L1_MODE_ENTRY_EN_L1_ALL_SQ_EMPTY_EN                                                       (0x1<<3) // 0 : All Send Queue Empty is not part of L1 request generation logic. 1 : All Send Queue Empty is part of L1 request generation logic.
+  #define CPMU_REG_L1_MODE_ENTRY_EN_L1_ALL_SQ_EMPTY_EN_SHIFT                                                 3
+  #define CPMU_REG_L1_MODE_ENTRY_EN_L1_MGMT_EMPTY_EN                                                         (0x1<<4) // 0 : Management Traffic is not part of L1 request generation logic. 1 : Management Traffic is part of L1 request generation logic.
+  #define CPMU_REG_L1_MODE_ENTRY_EN_L1_MGMT_EMPTY_EN_SHIFT                                                   4
+  #define CPMU_REG_L1_MODE_ENTRY_EN_L1_BRB_EMPTY_EN                                                          (0x1<<5) // 0 : BRB empty is not part of L1 request generation logic. 1 : BRB empty is part of L1 request generation logic.
+  #define CPMU_REG_L1_MODE_ENTRY_EN_L1_BRB_EMPTY_EN_SHIFT                                                    5
+  #define CPMU_REG_L1_MODE_ENTRY_EN_L1_PXP_EMPTY_EN                                                          (0x1<<6) // 0 : PXP empty is not part of L1 request generation logic. 1 : PXP empty is part of L1 request generation logic.
+  #define CPMU_REG_L1_MODE_ENTRY_EN_L1_PXP_EMPTY_EN_SHIFT                                                    6
+  #define CPMU_REG_L1_MODE_ENTRY_EN_L1_PGL_EMPTY_EN                                                          (0x1<<7) // 0 : PGL empty is not part of L1 request generation logic. 1 : PGL empty is part of L1 request generation logic.
+  #define CPMU_REG_L1_MODE_ENTRY_EN_L1_PGL_EMPTY_EN_SHIFT                                                    7
+  #define CPMU_REG_L1_MODE_ENTRY_EN_L1_CAU_IDLE_EN                                                           (0x1<<8) // 0 : CAU IDLE is not part of L1 request generation logic. 1 : CAU IDLE is part of L1 request generation logic.
+  #define CPMU_REG_L1_MODE_ENTRY_EN_L1_CAU_IDLE_EN_SHIFT                                                     8
+  #define CPMU_REG_L1_MODE_ENTRY_EN_L1_TM_SCAN_EN                                                            (0x1<<9) // 0 : Timer Scan status is not part of L1 request generation logic. 1 : Timer Scan status is part of L1 request generation logic.
+  #define CPMU_REG_L1_MODE_ENTRY_EN_L1_TM_SCAN_EN_SHIFT                                                      9
+  #define CPMU_REG_L1_MODE_ENTRY_EN_L1_RX_LPI_STATUS_EN                                                      (0x1<<10) // 0 : LPI receive status is not part of L1 request generation logic. 1 : LPI receive status is part of L1 request generation logic.
+  #define CPMU_REG_L1_MODE_ENTRY_EN_L1_RX_LPI_STATUS_EN_SHIFT                                                10
+#define CPMU_REG_L1_MODE_EXIT_EN                                                                             0x030270UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define CPMU_REG_L1_MODE_EXIT_EN_L1_RX_LPI_STATUS_EXIT_EN                                                  (0x1<<0) // 0 : LPI recive status is not part of the L1 exit. 1 : LPI recive status is part of the L1 exit.
+  #define CPMU_REG_L1_MODE_EXIT_EN_L1_RX_LPI_STATUS_EXIT_EN_SHIFT                                            0
+  #define CPMU_REG_L1_MODE_EXIT_EN_L1_SQ_EARLY_EXIT_EN                                                       (0x1<<1) // This bit will be used in the Normal mode. In this mode, 0 : Early exit indication from X or USTORM is not part of the L1 exit equation. 1 : When early exit is indicated either by XSTORM or USTORM, L1 will exit.
+  #define CPMU_REG_L1_MODE_EXIT_EN_L1_SQ_EARLY_EXIT_EN_SHIFT                                                 1
+#define CPMU_REG_SW_FORCE_L1                                                                                 0x030274UL //Access:RW   DataWidth:0x1    // Setting this bit to "1" will allow software to force an L1 request on the interface. Clearing this bit will not automatically guarantee an exit from L1 if other elements in the L1 equation is causing an L1 request to go out. To do a forceful exit, SW needs to assert the sw_l1_exit register.
+#define CPMU_REG_SW_L1_EXIT                                                                                  0x030278UL //Access:W    DataWidth:0x1    // Setting this bit to "1" will allow software to provide an early indication to exit L1 state. HW will generate a pulse on low to high transition of this register. The resultant bit is Self Clearing.
+#define CPMU_REG_LTR_MODE_CONFIG                                                                             0x03027cUL //Access:RW   DataWidth:0x1    // 0 : Entry to PCIe LTR is not enabled. 1 : Entry to PCIe LTR is enabled
+#define CPMU_REG_LTR_MODE_SLEEP_THRESHOLD                                                                    0x030280UL //Access:RW   DataWidth:0x20   // This register sets the Sleep Threshold for the LTR mode. The resolution of this register is 40ns. Values of 0 and 1 are not supported.
+#define CPMU_REG_LTR_MODE_ENTRY_EN                                                                           0x030284UL //Access:RW   DataWidth:0xd    // Multi Field Register.
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_PBF_EMPTY_EN                                                        (0x1<<0) // 0 : PBF Empty is not part of LTR request generation logic. 1 : PBF Empty is part of LTR request generation logic.
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_PBF_EMPTY_EN_SHIFT                                                  0
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_QM_EMPTY_TX_EN                                                      (0x1<<1) // 0 : QM Tx Empty is not part of LTR request generation logic. 1 : QM Tx Empty is part of LTR request generation logic.
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_QM_EMPTY_TX_EN_SHIFT                                                1
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_QM_EMPTY_GLOBAL_EN                                                  (0x1<<2) // 0 : QM Global Empty is not part of LTR request generation logic. 1 : QM Global Empty is part of LTR request generation logic.
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_QM_EMPTY_GLOBAL_EN_SHIFT                                            2
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_ALL_SQ_EMPTY_EN                                                     (0x1<<3) // 0 : All Send Queue Empty is not part of LTR request generation logic. 1 : All Send Queue Empty is part of LTR request generation logic.
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_ALL_SQ_EMPTY_EN_SHIFT                                               3
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_MGMT_EMPTY_EN                                                       (0x1<<4) // 0 : Management Traffic is not part of LTR request generation logic. 1 : Management Traffic is part of LTR request generation logic.
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_MGMT_EMPTY_EN_SHIFT                                                 4
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_BRB_CHECK_EN                                                        (0x1<<5) // 0 : BRB above threshold is not part of LTR request generation logic. 1 : BRB above threshold is part of LTR request generation logic.
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_BRB_CHECK_EN_SHIFT                                                  5
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_PXP_EMPTY_EN                                                        (0x1<<6) // 0 : PXP empty is not part of LTR request generation logic. 1 : PXP empty is part of LTR request generation logic.
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_PXP_EMPTY_EN_SHIFT                                                  6
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_PGL_EMPTY_EN                                                        (0x1<<7) // 0 : PGL empty is not part of LTR request generation logic. 1 : PGL empty is part of LTR request generation logic.
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_PGL_EMPTY_EN_SHIFT                                                  7
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_CAU_IDLE_EN                                                         (0x1<<8) // 0 : CAU IDLE is not part of LTR request generation logic. 1 : CAU IDLE is part of LTR request generation logic.
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_CAU_IDLE_EN_SHIFT                                                   8
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_TM_SCAN_EN                                                          (0x1<<9) // 0 : Timer Scan status is not part of LTR request generation logic. 1 : Timer Scan status is part of LTR request generation logic.
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_TM_SCAN_EN_SHIFT                                                    9
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_RX_LPI_STATUS_EN                                                    (0x1<<10) // 0 : LPI receive status is not part of LTR request generation logic. 1 : LPI receive status is part of LTR request generation logic.
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_RX_LPI_STATUS_EN_SHIFT                                              10
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_OBFF_MEM_STALL_EN                                                   (0x1<<11) // 0 : OBFF Memory access stall is not part of LTR request generation logic. 1 : OBFF Memory access stall is part of LTR request generation logic.
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_OBFF_MEM_STALL_EN_SHIFT                                             11
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_OBFF_INT_STALL_EN                                                   (0x1<<12) // 0 : OBFF interrupt access stall is not part of LTR request generation logic. 1 : OBFF interrupt access stall is part of LTR request generation logic.
+  #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_OBFF_INT_STALL_EN_SHIFT                                             12
+#define CPMU_REG_LTR_MODE_EXIT_EN                                                                            0x030288UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define CPMU_REG_LTR_MODE_EXIT_EN_LTR_RX_LPI_STATUS_EXIT_EN                                                (0x1<<0) // 0 : LPI recive status is not part of the LTR exit. 1 : LPI recive status is part of the LTR exit.
+  #define CPMU_REG_LTR_MODE_EXIT_EN_LTR_RX_LPI_STATUS_EXIT_EN_SHIFT                                          0
+  #define CPMU_REG_LTR_MODE_EXIT_EN_LTR_SQ_EARLY_EXIT_EN                                                     (0x1<<1) // This bit will be used in the Normal mode. In this mode, 0 : Early exit indication from X or USTORM is not part of the LTR exit equation. 1 : When early exit is indicated either by XSTORM or USTORM, LTR will exit.
+  #define CPMU_REG_LTR_MODE_EXIT_EN_LTR_SQ_EARLY_EXIT_EN_SHIFT                                               1
+#define CPMU_REG_SW_FORCE_LTR                                                                                0x03028cUL //Access:RW   DataWidth:0x1    // Setting this bit to "1" will allow software to force an LTR request on the interface. Clearing this bit will not automatically guarantee an exit from LTR if other elements in the LTR equation is causing an LTR request to go out. To do a forceful exit, SW needs to assert the sw_ltr_exit register.
+#define CPMU_REG_SW_LTR_EXIT                                                                                 0x030290UL //Access:W    DataWidth:0x1    // Setting this bit to "1" will allow software to provide an early indication to exit LTR state. HW will generate a pulse on low to high transition of this register. The resultant bit is Self Clearing.
+#define CPMU_REG_CLK_EN_CONFIG                                                                               0x030294UL //Access:RW   DataWidth:0x19   // Multi Field Register.
+  #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_E0_EN                                                              (0x1<<0) // 0 : Shutdown Main Clock to Path 0 1 : Enable Main Clock to Path 0
+  #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_E0_EN_SHIFT                                                        0
+  #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_E1_EN                                                              (0x1<<1) // 0 : Shutdown Main Clock to Path 1 1 : Enable Main Clock to Path 1
+  #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_E1_EN_SHIFT                                                        1
+  #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_NM_E0_EN                                                           (0x1<<2) // 0 : Shutdown Main Clock to Path 0 on the Network side 1 : Enable Main Clock to Path 0 on the Network side
+  #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_NM_E0_EN_SHIFT                                                     2
+  #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_NM_E1_EN                                                           (0x1<<3) // 0 : Shutdown Main Clock to Path 1 on the Network side 1 : Enable Main Clock to Path 1 on the Network side
+  #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_NM_E1_EN_SHIFT                                                     3
+  #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_NMC_EN                                                             (0x1<<4) // 0 : Shutdown Main Clock to Common Logic on the Network side 1 : Enable Main Clock to Common Logic on the Network side
+  #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_NMC_EN_SHIFT                                                       4
+  #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_HOST_EN                                                            (0x1<<5) // 0 : Shutdown Main Clock to Common Logic on the Host side 1 : Enable Main Clock to Common Logic on the Host side
+  #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_HOST_EN_SHIFT                                                      5
+  #define CPMU_REG_CLK_EN_CONFIG_STORM_CLK_E0_EN                                                             (0x1<<6) // 0 : Shutdown STORM Clock to Path 0 1 : Enable STORM Clock to Path 0
+  #define CPMU_REG_CLK_EN_CONFIG_STORM_CLK_E0_EN_SHIFT                                                       6
+  #define CPMU_REG_CLK_EN_CONFIG_STORM_CLK_E1_EN                                                             (0x1<<7) // 0 : Shutdown STORM Clock to Path 1 1 : Enable STORM Clock to Path 1
+  #define CPMU_REG_CLK_EN_CONFIG_STORM_CLK_E1_EN_SHIFT                                                       7
+  #define CPMU_REG_CLK_EN_CONFIG_NW_CLK_E0_EN                                                                (0x1<<8) // 0 : Shutdown Network Clock to Path 0 1 : Enable Network Clock to Path 0
+  #define CPMU_REG_CLK_EN_CONFIG_NW_CLK_E0_EN_SHIFT                                                          8
+  #define CPMU_REG_CLK_EN_CONFIG_NW_CLK_E1_EN                                                                (0x1<<9) // 0 : Shutdown Network Clock to Path 1 1 : Enable Network Clock to Path 1
+  #define CPMU_REG_CLK_EN_CONFIG_NW_CLK_E1_EN_SHIFT                                                          9
+  #define CPMU_REG_CLK_EN_CONFIG_NW_CLK_CMN_EN                                                               (0x1<<10) // 0 : Shutdown Network Clock to Common logic 1 : Enable Network Clock to Common logic
+  #define CPMU_REG_CLK_EN_CONFIG_NW_CLK_CMN_EN_SHIFT                                                         10
+  #define CPMU_REG_CLK_EN_CONFIG_CFG_CLK_EN                                                                  (0x1<<11) // 0 : Shutdown Configuration Clock to PCIe Core 1 : Enable Configuration Clock to PCIe Core
+  #define CPMU_REG_CLK_EN_CONFIG_CFG_CLK_EN_SHIFT                                                            11
+  #define CPMU_REG_CLK_EN_CONFIG_PCI_CLK_E0_EN                                                               (0x1<<12) // 0 : Shutdown PCI Clock to Path 0 1 : Enable PCI clock to Path 0
+  #define CPMU_REG_CLK_EN_CONFIG_PCI_CLK_E0_EN_SHIFT                                                         12
+  #define CPMU_REG_CLK_EN_CONFIG_PCI_CLK_E1_EN                                                               (0x1<<13) // 0 : Shutdown PCI Clock to Path 1 1 : Enable PCI clock to Path 1
+  #define CPMU_REG_CLK_EN_CONFIG_PCI_CLK_E1_EN_SHIFT                                                         13
+  #define CPMU_REG_CLK_EN_CONFIG_PCI_CLK_HOST_EN                                                             (0x1<<14) // 0 : Shutdown PCI Clock to Common logic on the host side 1 : Enable PCI clock to Common logic on the host side
+  #define CPMU_REG_CLK_EN_CONFIG_PCI_CLK_HOST_EN_SHIFT                                                       14
+  #define CPMU_REG_CLK_EN_CONFIG_PMFC_CLK_EN                                                                 (0x1<<15) // 0 : Shutdown all clocks to the Falcon based Port Macro 1 : Enable all clocks to the Falcon based Port Macro
+  #define CPMU_REG_CLK_EN_CONFIG_PMFC_CLK_EN_SHIFT                                                           15
+  #define CPMU_REG_CLK_EN_CONFIG_PMEG_CLK_EN                                                                 (0x1<<16) // 0 : Shutdown all clocks to the Eagle based Port Macro 1 : Enable all clocks to the Eagle based Port Macro
+  #define CPMU_REG_CLK_EN_CONFIG_PMEG_CLK_EN_SHIFT                                                           16
+  #define CPMU_REG_CLK_EN_CONFIG_NWM_CLK_EN_K2_E5                                                            (0x1<<17) // 0 : Shutdown NWM clock to the NW MAC 1 : Enable NWM clock to the NW MAC
+  #define CPMU_REG_CLK_EN_CONFIG_NWM_CLK_EN_K2_E5_SHIFT                                                      17
+  #define CPMU_REG_CLK_EN_CONFIG_BMB_CLK_EN_K2_E5                                                            (0x1<<18) // 0 : Shutdown Main Clock to the BMB PD 1 : Enable Main Clock to the BMB PD
+  #define CPMU_REG_CLK_EN_CONFIG_BMB_CLK_EN_K2_E5_SHIFT                                                      18
+  #define CPMU_REG_CLK_EN_CONFIG_BMB_NW_CLK_EN_K2_E5                                                         (0x1<<19) // 0 : Shutdown Network Clock to the BMB PD 1 : Enable Network Clock to the BMB PD
+  #define CPMU_REG_CLK_EN_CONFIG_BMB_NW_CLK_EN_K2_E5_SHIFT                                                   19
+  #define CPMU_REG_CLK_EN_CONFIG_NW_CLK_EN_K2_E5                                                             (0x1<<20) // 0 : Shutdown Main Clock to the NW PD 1 : Enable Main Clock to the NW PD
+  #define CPMU_REG_CLK_EN_CONFIG_NW_CLK_EN_K2_E5_SHIFT                                                       20
+  #define CPMU_REG_CLK_EN_CONFIG_NMC_ONLY_CLK_EN_K2_E5                                                       (0x1<<21) // 0 : Shutdown Main Clock to the NMC PD 1 : Enable Main Clock to the NMC PD
+  #define CPMU_REG_CLK_EN_CONFIG_NMC_ONLY_CLK_EN_K2_E5_SHIFT                                                 21
+  #define CPMU_REG_CLK_EN_CONFIG_NMC_ONLY_NW_CLK_EN_K2_E5                                                    (0x1<<22) // 0 : Shutdown Network Clock to the NMC PD 1 : Enable Network Clock to the NMC PD
+  #define CPMU_REG_CLK_EN_CONFIG_NMC_ONLY_NW_CLK_EN_K2_E5_SHIFT                                              22
+  #define CPMU_REG_CLK_EN_CONFIG_NMC_AHB_CLK_EN_K2_E5                                                        (0x1<<23) // 0 : Shutdown AHB Clock to the NMC PD 1 : Enable AHB Clock to the NMC PD
+  #define CPMU_REG_CLK_EN_CONFIG_NMC_AHB_CLK_EN_K2_E5_SHIFT                                                  23
+  #define CPMU_REG_CLK_EN_CONFIG_TOP_CLK_EN_K2_E5                                                            (0x1<<24) // 0 : Shutdown Main Clock to the TOP 1 : Enable Main Clock to the TOP
+  #define CPMU_REG_CLK_EN_CONFIG_TOP_CLK_EN_K2_E5_SHIFT                                                      24
+#define CPMU_REG_CLK_PM_CONFIG                                                                               0x030298UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define CPMU_REG_CLK_PM_CONFIG_SLOWDOWN_MAIN_CLK_EN                                                        (0x1<<0) // 0 : Slowdown of Main Clock is not enabled. 1 : Slowdown of Main Clock is enabled
+  #define CPMU_REG_CLK_PM_CONFIG_SLOWDOWN_MAIN_CLK_EN_SHIFT                                                  0
+  #define CPMU_REG_CLK_PM_CONFIG_SLOWDOWN_STORM_CLK_EN                                                       (0x1<<1) // 0 : Slowdown of STORM Clock is not enabled. 1 : Slowdown of STORM Clock is enabled
+  #define CPMU_REG_CLK_PM_CONFIG_SLOWDOWN_STORM_CLK_EN_SHIFT                                                 1
+  #define CPMU_REG_CLK_PM_CONFIG_SLOWDOWN_NW_CLK_EN                                                          (0x1<<2) // 0 : Slowdown of Network Clock is not enabled. 1 : Slowdown of Network Clock is enabled
+  #define CPMU_REG_CLK_PM_CONFIG_SLOWDOWN_NW_CLK_EN_SHIFT                                                    2
+  #define CPMU_REG_CLK_PM_CONFIG_SLOWDOWN_PCI_CLK_EN                                                         (0x1<<3) // 0 : Slowdown of PCI Clock is not enabled. 1 : Slowdown of PCI Clock is enabled
+  #define CPMU_REG_CLK_PM_CONFIG_SLOWDOWN_PCI_CLK_EN_SHIFT                                                   3
+#define CPMU_REG_CLK_PM_CMN_CONFIG                                                                           0x03029cUL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define CPMU_REG_CLK_PM_CMN_CONFIG_SLOWDOWN_MAIN_CLK_CMN_EN                                                (0x1<<0) // 0 : Slowdown of Main Clock for common logic is not enabled. 1 : Slowdown of Main Clock for common logic is enabled
+  #define CPMU_REG_CLK_PM_CMN_CONFIG_SLOWDOWN_MAIN_CLK_CMN_EN_SHIFT                                          0
+  #define CPMU_REG_CLK_PM_CMN_CONFIG_SLOWDOWN_NW_CLK_CMN_EN                                                  (0x1<<1) // 0 : Slowdown of Network Clock for common logic is not enabled. 1 : Slowdown of Network Clock for common logic is enabled
+  #define CPMU_REG_CLK_PM_CMN_CONFIG_SLOWDOWN_NW_CLK_CMN_EN_SHIFT                                            1
+  #define CPMU_REG_CLK_PM_CMN_CONFIG_SLOWDOWN_PCI_CLK_CMN_EN                                                 (0x1<<2) // 0 : Slowdown of PCI Clock for common logic is not enabled. 1 : Slowdown of PCI Clock for common logic is enabled
+  #define CPMU_REG_CLK_PM_CMN_CONFIG_SLOWDOWN_PCI_CLK_CMN_EN_SHIFT                                           2
+#define CPMU_REG_MAIN_CLK_MODE_SLEEP_THRESHOLD                                                               0x0302a0UL //Access:RW   DataWidth:0x20   // This register sets the Sleep Threshold for the Main Clock slowdown mode. The resolution of this register is 40ns. Values of 0 and 1 are not supported.
+#define CPMU_REG_STORM_CLK_MODE_SLEEP_THRESHOLD                                                              0x0302a4UL //Access:RW   DataWidth:0x20   // This register sets the Sleep Threshold for the storm Clock slowdown mode. The resolution of this register is 40ns. Values of 0 and 1 are not supported.
+#define CPMU_REG_NW_CLK_MODE_SLEEP_THRESHOLD                                                                 0x0302a8UL //Access:RW   DataWidth:0x20   // This register sets the Sleep Threshold for the storm Clock slowdown mode. The resolution of this register is 40ns. Values of 0 and 1 are not supported.
+#define CPMU_REG_PCI_CLK_MODE_SLEEP_THRESHOLD                                                                0x0302acUL //Access:RW   DataWidth:0x20   // This register sets the Sleep Threshold for the storm Clock slowdown mode. The resolution of this register is 40ns. Values of 0 and 1 are not supported.
+#define CPMU_REG_SLOWDOWN_MAIN_CLK_RATIO                                                                     0x0302b0UL //Access:RW   DataWidth:0x6    // This register sets the ratio of how many MAIN clock pulses to ignore before letting one clock pulse through. For ex a value of 15 in the register will result in the clock generation logic to send 1 clock pulse through for every 15 clock pulses. So for a clock rate of 375Mhz, the effective frequency will be 25Mhz. A value >= 2 should be set when using this feature. This register should be written when the CPMU is not enabled. In other words, SW/FW should ensure that this register is not programmed dynamically.
+#define CPMU_REG_SLOWDOWN_STORM_CLK_RATIO                                                                    0x0302b4UL //Access:RW   DataWidth:0x6    // This register sets the ratio of how many STORM clock pulses to ignore before letting one clock pulse through. For ex a value of 15 in the register will result in the clock generation logic to send 1 clock pulse through for every 15 clock pulses. So for a clock rate of 375Mhz, the effective frequency will be 25Mhz. A value >= 2 should be set when using this feature. This register should be written when the CPMU is not enabled. In other words, SW/FW should ensure that this register is not programmed dynamically.
+#define CPMU_REG_SLOWDOWN_NW_CLK_RATIO                                                                       0x0302b8UL //Access:RW   DataWidth:0x6    // This register sets the ratio of how many NW clock pulses to ignore before letting one clock pulse through. For ex a value of 15 in the register will result in the clock generation logic to send 1 clock pulse through for every 15 clock pulses. So for a clock rate of 375Mhz, the effective frequency will be 25Mhz. A value >= 2 should be set when using this feature. This register should be written when the CPMU is not enabled. In other words, SW/FW should ensure that this register is not programmed dynamically.
+#define CPMU_REG_SLOWDOWN_PCI_CLK_RATIO                                                                      0x0302bcUL //Access:RW   DataWidth:0x6    // This register sets the ratio of how many PCI clock pulses to ignore before letting one clock pulse through. For ex a value of 15 in the register will result in the clock generation logic to send 1 clock pulse through for every 15 clock pulses. So for a clock rate of 375Mhz, the effective frequency will be 25Mhz. A value >= 2 should be set when using this feature. This register should be written when the CPMU is not enabled. In other words, SW/FW should ensure that this register is not programmed dynamically.
+#define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN                                                                  0x0302c0UL //Access:RW   DataWidth:0x16   // Multi Field Register.
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_PBF_EMPTY_EN                                               (0x1<<0) // 0 : PBF Empty is not part of main clock slowdown logic. 1 : PBF Empty is not part of main clock slowdown logic.
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_PBF_EMPTY_EN_SHIFT                                         0
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_QM_EMPTY_TX_EN                                             (0x1<<1) // 0 : QM Tx Empty is not part of main clock slowdown generation logic. 1 : QM Tx Empty is part of main clock slowdown generation logic.
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_QM_EMPTY_TX_EN_SHIFT                                       1
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_QM_EMPTY_GLOBAL_EN                                         (0x1<<2) // 0 : QM Global Empty is not part of main clock slowdown generation logic. 1 : QM Global Empty is part of main clock slowdown generation logic.
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_QM_EMPTY_GLOBAL_EN_SHIFT                                   2
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_ALL_SQ_EMPTY_EN                                            (0x1<<3) // 0 : All Send Queue Empty is not part of Main Clock slowdown logic. 1 : All Send Queue Empty is part of Main Clock slowdown logic.
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_ALL_SQ_EMPTY_EN_SHIFT                                      3
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_MGMT_EMPTY_EN                                              (0x1<<4) // 0 : Management Traffic is not part of Main Clock slowdown logic. 1 : Management Traffic is part of Main Clock slowdown logic.
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_MGMT_EMPTY_EN_SHIFT                                        4
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_BRB_EMPTY_EN                                               (0x1<<5) // 0 : BRB empty is not part of Main Clock slowdown logic. 1 : BRB empty is part of Main Clock slowdown logic.
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_BRB_EMPTY_EN_SHIFT                                         5
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_PXP_EMPTY_EN                                               (0x1<<6) // 0 : PXP empty is not part of Main Clock slowdown logic. 1 : PXP empty is part of Main Clock slowdown logic.
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_PXP_EMPTY_EN_SHIFT                                         6
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_CAU_IDLE_EN                                                (0x1<<7) // 0 : CAU IDLE is not part of Main Clock slowdown logic. 1 : CAU IDLE is part of Main Clock slowdown logic.
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_CAU_IDLE_EN_SHIFT                                          7
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_TM_SCAN_EN                                                 (0x1<<8) // 0 : Timer Scan status is not part of Main Clock slowdown logic. 1 : Timer Scan status is part of Main Clock slowdown logic.
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_TM_SCAN_EN_SHIFT                                           8
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_OBFF_STATE_EN                                              (0x1<<9) // 0 : OBFF State (non CPU_ACTIVE) is not part of Main Clock slowdown logic. 1 : OBFF State (non CPU_ACTIVE) is part of Main Clock slowdown logic.
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_OBFF_STATE_EN_SHIFT                                        9
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_TSEM_IDLE_EN                                               (0x1<<10) // 0 : TSEM IDLE is not part of Main Clock slowdown logic. 1 : TSEM IDLE is part of Main Clock slowdown logic.
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_TSEM_IDLE_EN_SHIFT                                         10
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_MSEM_IDLE_EN                                               (0x1<<11) // 0 : MSEM IDLE is not part of Main Clock slowdown logic. 1 : MSEM IDLE is part of Main Clock slowdown logic.
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_MSEM_IDLE_EN_SHIFT                                         11
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_USEM_IDLE_EN                                               (0x1<<12) // 0 : USEM IDLE is not part of Main Clock slowdown logic. 1 : USEM IDLE is part of Main Clock slowdown logic.
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_USEM_IDLE_EN_SHIFT                                         12
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_XSEM_IDLE_EN                                               (0x1<<13) // 0 : XSEM IDLE is not part of Main Clock slowdown logic. 1 : XSEM IDLE is part of Main Clock slowdown logic.
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_XSEM_IDLE_EN_SHIFT                                         13
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_YSEM_IDLE_EN                                               (0x1<<14) // 0 : YSEM IDLE is not part of Main Clock slowdown logic. 1 : YSEM IDLE is part of Main Clock slowdown logic.
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_YSEM_IDLE_EN_SHIFT                                         14
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_PSEM_IDLE_EN                                               (0x1<<15) // 0 : PSEM IDLE is not part of Main Clock slowdown logic. 1 : PSEM IDLE is part of Main Clock slowdown logic.
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_PSEM_IDLE_EN_SHIFT                                         15
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_RX_LPI_STATUS_EN                                           (0x1<<16) // 0 : LPI receive status is not part of Main Clock slowdown logic. 1 : LPI receive status is part of Main Clock slowdown logic.
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_RX_LPI_STATUS_EN_SHIFT                                     16
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_NW_LINKDOWN_EN                                             (0x1<<17) // 0 : Network Link Down is not part of Main Clock slowdown logic. 1 : Network Link Down is part of Main Clock slowdown logic.
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_NW_LINKDOWN_EN_SHIFT                                       17
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_NIG_RX_EMPTY_EN                                            (0x1<<18) // 0 : NIG Rx Empty is not part of Main Clock slowdown logic. 1 : NIG Rx Empty is part of Main Clock slowdown logic.
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_NIG_RX_EMPTY_EN_SHIFT                                      18
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_NIG_TX_EMPTY_EN                                            (0x1<<19) // 0 : NIG Tx Empty is not part of Main Clock slowdown logic. 1 : NIG Tx Empty is part of Main Clock slowdown logic.
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_NIG_TX_EMPTY_EN_SHIFT                                      19
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_NIG_LB_EMPTY_EN                                            (0x1<<20) // 0 : NIG Loopback Empty is not part of Main Clock slowdown logic. 1 : NIG Loopback Empty is part of Main Clock slowdown logic.
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_NIG_LB_EMPTY_EN_SHIFT                                      20
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_PCIE_IN_D3_EN                                              (0x1<<21) // 0 : PCIE in D3 is not part of Main Clock slowdown logic. 1 : PCIE in D3 is part of Main Clock slowdown logic.
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_PCIE_IN_D3_EN_SHIFT                                        21
+#define CPMU_REG_MAIN_CLK_SLOWDOWN_EXIT_EN                                                                   0x0302c4UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_EXIT_EN_MCS_PCIE_L1_EXIT_EN                                             (0x1<<0) // 0 : PCIe L1 exit is not part of exit from main clock slowdown logic 1 : PCIe L1 exit is part of exit from main clock slowdown logic
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_EXIT_EN_MCS_PCIE_L1_EXIT_EN_SHIFT                                       0
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_EXIT_EN_MCS_DORQ_EVENT_EN                                               (0x1<<1) // 0 : DORQ Event is not part of exit from main clock slowdown logic 1 : DORQ Event is part of exit from main clock slowdown logic
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_EXIT_EN_MCS_DORQ_EVENT_EN_SHIFT                                         1
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_EXIT_EN_MCS_NCSI_EVENT_EN                                               (0x1<<2) // 0 : NCSI Event is not part of exit from main clock slowdown logic 1 : NCSI Event is part of exit from main clock slowdown logic
+  #define CPMU_REG_MAIN_CLK_SLOWDOWN_EXIT_EN_MCS_NCSI_EVENT_EN_SHIFT                                         2
+#define CPMU_REG_SW_FORCE_MAIN_CLK_SLOWDOWN                                                                  0x0302c8UL //Access:RW   DataWidth:0x1    // Setting this bit to "1" will allow software to force slowdown of main clock for the corresponding path.
+#define CPMU_REG_SW_FORCE_MAIN_CLK_EXIT                                                                      0x0302ccUL //Access:W    DataWidth:0x1    // Setting this bit to "1" will allow software to provide an early indication to exit main clock slowdown.
+#define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN                                                                 0x0302d0UL //Access:RW   DataWidth:0x16   // Multi Field Register.
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_PBF_EMPTY_EN                                              (0x1<<0) // 0 : PBF Empty is not part of storm clock slowdown logic. 1 : PBF Empty is not part of storm clock slowdown logic.
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_PBF_EMPTY_EN_SHIFT                                        0
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_QM_EMPTY_TX_EN                                            (0x1<<1) // 0 : QM Tx Empty is not part of storm clock slowdown generation logic. 1 : QM Tx Empty is part of storm clock slowdown generation logic.
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_QM_EMPTY_TX_EN_SHIFT                                      1
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_QM_EMPTY_GLOBAL_EN                                        (0x1<<2) // 0 : QM Global Empty is not part of storm clock slowdown generation logic. 1 : QM Global Empty is part of storm clock slowdown generation logic.
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_QM_EMPTY_GLOBAL_EN_SHIFT                                  2
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_ALL_SQ_EMPTY_EN                                           (0x1<<3) // 0 : All Send Queue Empty is not part of Storm Clock slowdown logic. 1 : All Send Queue Empty is part of Storm Clock slowdown logic.
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_ALL_SQ_EMPTY_EN_SHIFT                                     3
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_MGMT_EMPTY_EN                                             (0x1<<4) // 0 : Management Traffic is not part of Storm Clock slowdown logic. 1 : Management Traffic is part of Storm Clock slowdown logic.
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_MGMT_EMPTY_EN_SHIFT                                       4
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_BRB_EMPTY_EN                                              (0x1<<5) // 0 : BRB empty is not part of Storm Clock slowdown logic. 1 : BRB empty is part of Storm Clock slowdown logic.
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_BRB_EMPTY_EN_SHIFT                                        5
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_PXP_EMPTY_EN                                              (0x1<<6) // 0 : PXP empty is not part of Storm Clock slowdown logic. 1 : PXP empty is part of Storm Clock slowdown logic.
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_PXP_EMPTY_EN_SHIFT                                        6
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_CAU_IDLE_EN                                               (0x1<<7) // 0 : CAU IDLE is not part of Storm Clock slowdown logic. 1 : CAU IDLE is part of Storm Clock slowdown logic.
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_CAU_IDLE_EN_SHIFT                                         7
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_TM_SCAN_EN                                                (0x1<<8) // 0 : Timer Scan status is not part of Storm Clock slowdown logic. 1 : Timer Scan status is part of Storm Clock slowdown logic.
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_TM_SCAN_EN_SHIFT                                          8
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_OBFF_STATE_EN                                             (0x1<<9) // 0 : OBFF State (non CPU_ACTIVE) is not part of Storm Clock slowdown logic. 1 : OBFF State (non CPU_ACTIVE) is part of Storm Clock slowdown logic.
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_OBFF_STATE_EN_SHIFT                                       9
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_TSEM_IDLE_EN                                              (0x1<<10) // 0 : TSEM IDLE is not part of Storm Clock slowdown logic. 1 : TSEM IDLE is part of Storm Clock slowdown logic.
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_TSEM_IDLE_EN_SHIFT                                        10
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_MSEM_IDLE_EN                                              (0x1<<11) // 0 : MSEM IDLE is not part of Storm Clock slowdown logic. 1 : MSEM IDLE is part of Storm Clock slowdown logic.
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_MSEM_IDLE_EN_SHIFT                                        11
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_USEM_IDLE_EN                                              (0x1<<12) // 0 : USEM IDLE is not part of Storm Clock slowdown logic. 1 : USEM IDLE is part of Storm Clock slowdown logic.
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_USEM_IDLE_EN_SHIFT                                        12
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_XSEM_IDLE_EN                                              (0x1<<13) // 0 : XSEM IDLE is not part of Storm Clock slowdown logic. 1 : XSEM IDLE is part of Storm Clock slowdown logic.
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_XSEM_IDLE_EN_SHIFT                                        13
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_YSEM_IDLE_EN                                              (0x1<<14) // 0 : YSEM IDLE is not part of Storm Clock slowdown logic. 1 : YSEM IDLE is part of Storm Clock slowdown logic.
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_YSEM_IDLE_EN_SHIFT                                        14
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_PSEM_IDLE_EN                                              (0x1<<15) // 0 : PSEM IDLE is not part of Storm Clock slowdown logic. 1 : PSEM IDLE is part of Storm Clock slowdown logic.
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_PSEM_IDLE_EN_SHIFT                                        15
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_RX_LPI_STATUS_EN                                          (0x1<<16) // 0 : LPI receive status is not part of Storm Clock slowdown logic. 1 : LPI receive status is part of Storm Clock slowdown logic.
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_RX_LPI_STATUS_EN_SHIFT                                    16
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_NW_LINKDOWN_EN                                            (0x1<<17) // 0 : Network Link Down is not part of Storm Clock slowdown logic. 1 : Network Link Down is part of Storm Clock slowdown logic.
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_NW_LINKDOWN_EN_SHIFT                                      17
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_NIG_RX_EMPTY_EN                                           (0x1<<18) // 0 : NIG Rx Empty is not part of Storm Clock slowdown logic. 1 : NIG Rx Empty is part of Storm Clock slowdown logic.
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_NIG_RX_EMPTY_EN_SHIFT                                     18
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_NIG_TX_EMPTY_EN                                           (0x1<<19) // 0 : NIG Tx Empty is not part of Storm Clock slowdown logic. 1 : NIG Tx Empty is part of Storm Clock slowdown logic.
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_NIG_TX_EMPTY_EN_SHIFT                                     19
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_NIG_LB_EMPTY_EN                                           (0x1<<20) // 0 : NIG Loopback Empty is not part of Storm Clock slowdown logic. 1 : NIG Loopback Empty is part of Storm Clock slowdown logic.
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_NIG_LB_EMPTY_EN_SHIFT                                     20
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_PCIE_IN_D3_EN                                             (0x1<<21) // 0 : PCIE in D3 is not part of Storm Clock slowdown logic. 1 : PCIE in D3 is part of Storm Clock slowdown logic.
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_PCIE_IN_D3_EN_SHIFT                                       21
+#define CPMU_REG_STORM_CLK_SLOWDOWN_EXIT_EN                                                                  0x0302d4UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_EXIT_EN_SCS_PCIE_L1_EXIT_EN                                            (0x1<<0) // 0 : PCIe L1 exit is not part of exit from storm clock slowdown logic 1 : PCIe L1 exit is part of exit from storm clock slowdown logic
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_EXIT_EN_SCS_PCIE_L1_EXIT_EN_SHIFT                                      0
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_EXIT_EN_SCS_DORQ_EVENT_EN                                              (0x1<<1) // 0 : DORQ Event is not part of exit from storm clock slowdown logic 1 : DORQ Event is part of exit from storm clock slowdown logic
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_EXIT_EN_SCS_DORQ_EVENT_EN_SHIFT                                        1
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_EXIT_EN_SCS_NCSI_EVENT_EN                                              (0x1<<2) // 0 : NCSI Event is not part of exit from storm clock slowdown logic 1 : NCSI Event is part of exit from storm clock slowdown logic
+  #define CPMU_REG_STORM_CLK_SLOWDOWN_EXIT_EN_SCS_NCSI_EVENT_EN_SHIFT                                        2
+#define CPMU_REG_SW_FORCE_STORM_CLK_SLOWDOWN                                                                 0x0302d8UL //Access:RW   DataWidth:0x1    // Setting this bit to "1" will allow software to force slowdown of storm clock for the corresponding path.
+#define CPMU_REG_SW_FORCE_STORM_CLK_EXIT                                                                     0x0302dcUL //Access:W    DataWidth:0x1    // Setting this bit to "1" will allow software to provide an early indication to exit storm clock slowdown.
+#define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN                                                                    0x0302e0UL //Access:RW   DataWidth:0x16   // Multi Field Register.
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_PBF_EMPTY_EN                                                 (0x1<<0) // 0 : PBF Empty is not part of nw clock slowdown logic. 1 : PBF Empty is not part of nw clock slowdown logic.
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_PBF_EMPTY_EN_SHIFT                                           0
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_QM_EMPTY_TX_EN                                               (0x1<<1) // 0 : QM Tx Empty is not part of nw clock slowdown generation logic. 1 : QM Tx Empty is part of nw clock slowdown generation logic.
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_QM_EMPTY_TX_EN_SHIFT                                         1
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_QM_EMPTY_GLOBAL_EN                                           (0x1<<2) // 0 : QM Global Empty is not part of nw clock slowdown generation logic. 1 : QM Global Empty is part of nw clock slowdown generation logic.
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_QM_EMPTY_GLOBAL_EN_SHIFT                                     2
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_ALL_SQ_EMPTY_EN                                              (0x1<<3) // 0 : All Send Queue Empty is not part of Nw Clock slowdown logic. 1 : All Send Queue Empty is part of Nw Clock slowdown logic.
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_ALL_SQ_EMPTY_EN_SHIFT                                        3
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_MGMT_EMPTY_EN                                                (0x1<<4) // 0 : Management Traffic is not part of Nw Clock slowdown logic. 1 : Management Traffic is part of Nw Clock slowdown logic.
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_MGMT_EMPTY_EN_SHIFT                                          4
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_BRB_EMPTY_EN                                                 (0x1<<5) // 0 : BRB empty is not part of Nw Clock slowdown logic. 1 : BRB empty is part of Nw Clock slowdown logic.
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_BRB_EMPTY_EN_SHIFT                                           5
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_PXP_EMPTY_EN                                                 (0x1<<6) // 0 : PXP empty is not part of Nw Clock slowdown logic. 1 : PXP empty is part of Nw Clock slowdown logic.
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_PXP_EMPTY_EN_SHIFT                                           6
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_CAU_IDLE_EN                                                  (0x1<<7) // 0 : CAU IDLE is not part of Nw Clock slowdown logic. 1 : CAU IDLE is part of Nw Clock slowdown logic.
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_CAU_IDLE_EN_SHIFT                                            7
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_TM_SCAN_EN                                                   (0x1<<8) // 0 : Timer Scan status is not part of Nw Clock slowdown logic. 1 : Timer Scan status is part of Nw Clock slowdown logic.
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_TM_SCAN_EN_SHIFT                                             8
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_OBFF_STATE_EN                                                (0x1<<9) // 0 : OBFF State (non CPU_ACTIVE) is not part of Nw Clock slowdown logic. 1 : OBFF State (non CPU_ACTIVE) is part of Nw Clock slowdown logic.
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_OBFF_STATE_EN_SHIFT                                          9
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_TSEM_IDLE_EN                                                 (0x1<<10) // 0 : TSEM IDLE is not part of Nw Clock slowdown logic. 1 : TSEM IDLE is part of Nw Clock slowdown logic.
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_TSEM_IDLE_EN_SHIFT                                           10
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_MSEM_IDLE_EN                                                 (0x1<<11) // 0 : MSEM IDLE is not part of Nw Clock slowdown logic. 1 : MSEM IDLE is part of Nw Clock slowdown logic.
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_MSEM_IDLE_EN_SHIFT                                           11
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_USEM_IDLE_EN                                                 (0x1<<12) // 0 : USEM IDLE is not part of Nw Clock slowdown logic. 1 : USEM IDLE is part of Nw Clock slowdown logic.
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_USEM_IDLE_EN_SHIFT                                           12
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_XSEM_IDLE_EN                                                 (0x1<<13) // 0 : XSEM IDLE is not part of Nw Clock slowdown logic. 1 : XSEM IDLE is part of Nw Clock slowdown logic.
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_XSEM_IDLE_EN_SHIFT                                           13
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_YSEM_IDLE_EN                                                 (0x1<<14) // 0 : YSEM IDLE is not part of Nw Clock slowdown logic. 1 : YSEM IDLE is part of Nw Clock slowdown logic.
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_YSEM_IDLE_EN_SHIFT                                           14
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_PSEM_IDLE_EN                                                 (0x1<<15) // 0 : PSEM IDLE is not part of Nw Clock slowdown logic. 1 : PSEM IDLE is part of Nw Clock slowdown logic.
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_PSEM_IDLE_EN_SHIFT                                           15
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_RX_LPI_STATUS_EN                                             (0x1<<16) // 0 : LPI receive status is not part of Nw Clock slowdown logic. 1 : LPI receive status is part of Nw Clock slowdown logic.
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_RX_LPI_STATUS_EN_SHIFT                                       16
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_NW_LINKDOWN_EN                                               (0x1<<17) // 0 : Network Link Down is not part of Nw Clock slowdown logic. 1 : Network Link Down is part of Nw Clock slowdown logic.
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_NW_LINKDOWN_EN_SHIFT                                         17
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_NIG_RX_EMPTY_EN                                              (0x1<<18) // 0 : NIG Rx Empty is not part of Nw Clock slowdown logic. 1 : NIG Rx Empty is part of Nw Clock slowdown logic.
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_NIG_RX_EMPTY_EN_SHIFT                                        18
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_NIG_TX_EMPTY_EN                                              (0x1<<19) // 0 : NIG Tx Empty is not part of Nw Clock slowdown logic. 1 : NIG Tx Empty is part of Nw Clock slowdown logic.
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_NIG_TX_EMPTY_EN_SHIFT                                        19
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_NIG_LB_EMPTY_EN                                              (0x1<<20) // 0 : NIG Loopback Empty is not part of Nw Clock slowdown logic. 1 : NIG Loopback Empty is part of Nw Clock slowdown logic.
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_NIG_LB_EMPTY_EN_SHIFT                                        20
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_PCIE_IN_D3_EN                                                (0x1<<21) // 0 : PCIE in D3 is not part of NW Clock slowdown logic. 1 : PCIE in D3 is part of NW Clock slowdown logic.
+  #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_PCIE_IN_D3_EN_SHIFT                                          21
+#define CPMU_REG_NW_CLK_SLOWDOWN_EXIT_EN                                                                     0x0302e4UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define CPMU_REG_NW_CLK_SLOWDOWN_EXIT_EN_NCS_PCIE_L1_EXIT_EN                                               (0x1<<0) // 0 : PCIe L1 exit is not part of exit from nw clock slowdown logic 1 : PCIe L1 exit is part of exit from nw clock slowdown logic
+  #define CPMU_REG_NW_CLK_SLOWDOWN_EXIT_EN_NCS_PCIE_L1_EXIT_EN_SHIFT                                         0
+  #define CPMU_REG_NW_CLK_SLOWDOWN_EXIT_EN_NCS_DORQ_EVENT_EN                                                 (0x1<<1) // 0 : DORQ Event is not part of exit from nw clock slowdown logic 1 : DORQ Event is part of exit from nw clock slowdown logic
+  #define CPMU_REG_NW_CLK_SLOWDOWN_EXIT_EN_NCS_DORQ_EVENT_EN_SHIFT                                           1
+  #define CPMU_REG_NW_CLK_SLOWDOWN_EXIT_EN_NCS_NCSI_EVENT_EN                                                 (0x1<<2) // 0 : NCSI Event is not part of exit from nw clock slowdown logic 1 : NCSI Event is part of exit from nw clock slowdown logic
+  #define CPMU_REG_NW_CLK_SLOWDOWN_EXIT_EN_NCS_NCSI_EVENT_EN_SHIFT                                           2
+#define CPMU_REG_SW_FORCE_NW_CLK_SLOWDOWN                                                                    0x0302e8UL //Access:RW   DataWidth:0x1    // Setting this bit to "1" will allow software to force slowdown of nw clock for the corresponding path.
+#define CPMU_REG_SW_FORCE_NW_CLK_EXIT                                                                        0x0302ecUL //Access:W    DataWidth:0x1    // Setting this bit to "1" will allow software to provide an early indication to exit nw clock slowdown.
+#define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN                                                                   0x0302f0UL //Access:RW   DataWidth:0x16   // Multi Field Register.
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_PBF_EMPTY_EN                                                (0x1<<0) // 0 : PBF Empty is not part of pci clock slowdown logic. 1 : PBF Empty is not part of pci clock slowdown logic.
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_PBF_EMPTY_EN_SHIFT                                          0
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_QM_EMPTY_TX_EN                                              (0x1<<1) // 0 : QM Tx Empty is not part of pci clock slowdown generation logic. 1 : QM Tx Empty is part of pci clock slowdown generation logic.
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_QM_EMPTY_TX_EN_SHIFT                                        1
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_QM_EMPTY_GLOBAL_EN                                          (0x1<<2) // 0 : QM Global Empty is not part of pci clock slowdown generation logic. 1 : QM Global Empty is part of pci clock slowdown generation logic.
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_QM_EMPTY_GLOBAL_EN_SHIFT                                    2
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_ALL_SQ_EMPTY_EN                                             (0x1<<3) // 0 : All Send Queue Empty is not part of PCI Clock slowdown logic. 1 : All Send Queue Empty is part of PCI Clock slowdown logic.
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_ALL_SQ_EMPTY_EN_SHIFT                                       3
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_MGMT_EMPTY_EN                                               (0x1<<4) // 0 : Management Traffic is not part of PCI Clock slowdown logic. 1 : Management Traffic is part of PCI Clock slowdown logic.
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_MGMT_EMPTY_EN_SHIFT                                         4
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_BRB_EMPTY_EN                                                (0x1<<5) // 0 : BRB empty is not part of PCI Clock slowdown logic. 1 : BRB empty is part of PCI Clock slowdown logic.
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_BRB_EMPTY_EN_SHIFT                                          5
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_PXP_EMPTY_EN                                                (0x1<<6) // 0 : PXP empty is not part of PCI Clock slowdown logic. 1 : PXP empty is part of PCI Clock slowdown logic.
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_PXP_EMPTY_EN_SHIFT                                          6
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_CAU_IDLE_EN                                                 (0x1<<7) // 0 : CAU IDLE is not part of PCI Clock slowdown logic. 1 : CAU IDLE is part of PCI Clock slowdown logic.
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_CAU_IDLE_EN_SHIFT                                           7
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_TM_SCAN_EN                                                  (0x1<<8) // 0 : Timer Scan status is not part of PCI Clock slowdown logic. 1 : Timer Scan status is part of PCI Clock slowdown logic.
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_TM_SCAN_EN_SHIFT                                            8
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_OBFF_STATE_EN                                               (0x1<<9) // 0 : OBFF State (non CPU_ACTIVE) is not part of PCI Clock slowdown logic. 1 : OBFF State (non CPU_ACTIVE) is part of PCI Clock slowdown logic.
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_OBFF_STATE_EN_SHIFT                                         9
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_TSEM_IDLE_EN                                                (0x1<<10) // 0 : TSEM IDLE is not part of PCI Clock slowdown logic. 1 : TSEM IDLE is part of PCI Clock slowdown logic.
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_TSEM_IDLE_EN_SHIFT                                          10
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_MSEM_IDLE_EN                                                (0x1<<11) // 0 : MSEM IDLE is not part of PCI Clock slowdown logic. 1 : MSEM IDLE is part of PCI Clock slowdown logic.
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_MSEM_IDLE_EN_SHIFT                                          11
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_USEM_IDLE_EN                                                (0x1<<12) // 0 : USEM IDLE is not part of PCI Clock slowdown logic. 1 : USEM IDLE is part of PCI Clock slowdown logic.
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_USEM_IDLE_EN_SHIFT                                          12
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_XSEM_IDLE_EN                                                (0x1<<13) // 0 : XSEM IDLE is not part of PCI Clock slowdown logic. 1 : XSEM IDLE is part of PCI Clock slowdown logic.
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_XSEM_IDLE_EN_SHIFT                                          13
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_YSEM_IDLE_EN                                                (0x1<<14) // 0 : YSEM IDLE is not part of PCI Clock slowdown logic. 1 : YSEM IDLE is part of PCI Clock slowdown logic.
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_YSEM_IDLE_EN_SHIFT                                          14
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_PSEM_IDLE_EN                                                (0x1<<15) // 0 : PSEM IDLE is not part of PCI Clock slowdown logic. 1 : PSEM IDLE is part of PCI Clock slowdown logic.
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_PSEM_IDLE_EN_SHIFT                                          15
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_RX_LPI_STATUS_EN                                            (0x1<<16) // 0 : LPI receive status is not part of PCI Clock slowdown logic. 1 : LPI receive status is part of PCI Clock slowdown logic.
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_RX_LPI_STATUS_EN_SHIFT                                      16
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_NW_LINKDOWN_EN                                              (0x1<<17) // 0 : Network Link Down is not part of PCI Clock slowdown logic. 1 : Network Link Down is part of PCI Clock slowdown logic.
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_NW_LINKDOWN_EN_SHIFT                                        17
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_NIG_RX_EMPTY_EN                                             (0x1<<18) // 0 : NIG Rx Empty is not part of PCI Clock slowdown logic. 1 : NIG Rx Empty is part of PCI Clock slowdown logic.
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_NIG_RX_EMPTY_EN_SHIFT                                       18
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_NIG_TX_EMPTY_EN                                             (0x1<<19) // 0 : NIG Tx Empty is not part of PCI Clock slowdown logic. 1 : NIG Tx Empty is part of PCI Clock slowdown logic.
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_NIG_TX_EMPTY_EN_SHIFT                                       19
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_NIG_LB_EMPTY_EN                                             (0x1<<20) // 0 : NIG Loopback Empty is not part of PCI Clock slowdown logic. 1 : NIG Loopback Empty is part of PCI Clock slowdown logic.
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_NIG_LB_EMPTY_EN_SHIFT                                       20
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_PCIE_IN_D3_EN                                               (0x1<<21) // 0 : PCIE in D3 is not part of PCI Clock slowdown logic. 1 : PCIE in D3 is part of PCI Clock slowdown logic.
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_PCIE_IN_D3_EN_SHIFT                                         21
+#define CPMU_REG_PCI_CLK_SLOWDOWN_EXIT_EN                                                                    0x0302f4UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_EXIT_EN_PCS_PCIE_L1_EXIT_EN                                              (0x1<<0) // 0 : PCIe L1 exit is not part of exit from pci clock slowdown logic 1 : PCIe L1 exit is part of exit from pci clock slowdown logic
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_EXIT_EN_PCS_PCIE_L1_EXIT_EN_SHIFT                                        0
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_EXIT_EN_PCS_DORQ_EVENT_EN                                                (0x1<<1) // 0 : DORQ Event is not part of exit from pci clock slowdown logic 1 : DORQ Event is part of exit from pci clock slowdown logic
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_EXIT_EN_PCS_DORQ_EVENT_EN_SHIFT                                          1
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_EXIT_EN_PCS_NCSI_EVENT_EN                                                (0x1<<2) // 0 : NCSI Event is not part of exit from pci clock slowdown logic 1 : NCSI Event is part of exit from pci clock slowdown logic
+  #define CPMU_REG_PCI_CLK_SLOWDOWN_EXIT_EN_PCS_NCSI_EVENT_EN_SHIFT                                          2
+#define CPMU_REG_SW_FORCE_PCI_CLK_SLOWDOWN                                                                   0x0302f8UL //Access:RW   DataWidth:0x1    // Setting this bit to "1" will allow software to force slowdown of pci clock for the corresponding path.
+#define CPMU_REG_SW_FORCE_PCI_CLK_EXIT                                                                       0x0302fcUL //Access:W    DataWidth:0x1    // Setting this bit to "1" will allow software to provide an early indication to exit pci clock slowdown.
+#define CPMU_REG_PXP_VQ_EMPTY_STATUS_E0_0                                                                    0x030300UL //Access:R    DataWidth:0x20   // First 32bits of VQ empty for Engine 0
+#define CPMU_REG_PXP_VQ_EMPTY_STATUS_E0_1                                                                    0x030304UL //Access:R    DataWidth:0x2    // Bits [33:32] of VQ empty for engine 0
+#define CPMU_REG_PXP_VQ_EMPTY_STATUS_E1_0                                                                    0x030308UL //Access:R    DataWidth:0x20   // First 32bits of VQ empty for Engine 1
+#define CPMU_REG_PXP_VQ_EMPTY_STATUS_E1_1                                                                    0x03030cUL //Access:R    DataWidth:0x2    // Bits [33:32] of VQ empty for engine 1
+#define CPMU_REG_CPMU_INPUT_SIG_STATUS_0                                                                     0x030310UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BMB_ABOVE_THRESHOLD_PORT_ISIG_STATUS                              (0xf<<0) // Current status of bmb_above_threshold_port
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BMB_ABOVE_THRESHOLD_PORT_ISIG_STATUS_SHIFT                        0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BMB_PATH_EMPTY_ISIG_STATUS                                        (0x1<<4) // Current status of bmb_path_empty
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BMB_PATH_EMPTY_ISIG_STATUS_SHIFT                                  4
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BMB_PORT_EMPTY_ISIG_STATUS                                        (0xf<<5) // Current status of bmb_port_empty
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BMB_PORT_EMPTY_ISIG_STATUS_SHIFT                                  5
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BRB_ABOVE_THRESHOLD_PATH_E0_ISIG_STATUS                           (0x3<<9) // Current status of brb_above_threshold_path_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BRB_ABOVE_THRESHOLD_PATH_E0_ISIG_STATUS_SHIFT                     9
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BRB_ABOVE_THRESHOLD_PATH_E1_ISIG_STATUS                           (0x3<<11) // Current status of brb_above_threshold_path_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BRB_ABOVE_THRESHOLD_PATH_E1_ISIG_STATUS_SHIFT                     11
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BRB_PATH_EMPTY_E0_ISIG_STATUS                                     (0x1<<13) // Current status of brb_path_empty_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BRB_PATH_EMPTY_E0_ISIG_STATUS_SHIFT                               13
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BRB_PATH_EMPTY_E1_ISIG_STATUS                                     (0x1<<14) // Current status of brb_path_empty_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BRB_PATH_EMPTY_E1_ISIG_STATUS_SHIFT                               14
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_PBF_ABOVE_THRESHOLD_PORT_E0_ISIG_STATUS                           (0x3<<15) // Current status of pbf_above_threshold_port_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_PBF_ABOVE_THRESHOLD_PORT_E0_ISIG_STATUS_SHIFT                     15
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_PBF_ABOVE_THRESHOLD_PORT_E1_ISIG_STATUS                           (0x3<<17) // Current status of pbf_above_threshold_port_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_PBF_ABOVE_THRESHOLD_PORT_E1_ISIG_STATUS_SHIFT                     17
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BTB_PATH_EMPTY_E0_ISIG_STATUS                                     (0x1<<19) // Current status of btb_path_empty_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BTB_PATH_EMPTY_E0_ISIG_STATUS_SHIFT                               19
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BTB_PATH_EMPTY_E1_ISIG_STATUS                                     (0x1<<20) // Current status of btb_path_empty_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BTB_PATH_EMPTY_E1_ISIG_STATUS_SHIFT                               20
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BTB_PORT_EMPTY_E0_ISIG_STATUS                                     (0x3<<21) // Current status of btb_port_empty_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BTB_PORT_EMPTY_E0_ISIG_STATUS_SHIFT                               21
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BTB_PORT_EMPTY_E1_ISIG_STATUS                                     (0x3<<23) // Current status of btb_port_empty_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BTB_PORT_EMPTY_E1_ISIG_STATUS_SHIFT                               23
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CAU_PATH_IDLE_E0_ISIG_STATUS                                      (0x1<<25) // Current status of cau_path_idle_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CAU_PATH_IDLE_E0_ISIG_STATUS_SHIFT                                25
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CAU_PATH_IDLE_E1_ISIG_STATUS                                      (0x1<<26) // Current status of cau_path_idle_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CAU_PATH_IDLE_E1_ISIG_STATUS_SHIFT                                26
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_LINK_DOWN_P0_E0_ISIG_STATUS                                  (0x1<<27) // Current status of cnig_link_down_p0_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_LINK_DOWN_P0_E0_ISIG_STATUS_SHIFT                            27
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_LINK_DOWN_P0_E1_ISIG_STATUS                                  (0x1<<28) // Current status of cnig_link_down_p0_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_LINK_DOWN_P0_E1_ISIG_STATUS_SHIFT                            28
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_LINK_DOWN_P1_E0_ISIG_STATUS                                  (0x1<<29) // Current status of cnig_link_down_p1_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_LINK_DOWN_P1_E0_ISIG_STATUS_SHIFT                            29
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_LINK_DOWN_P1_E1_ISIG_STATUS                                  (0x1<<30) // Current status of cnig_link_down_p1_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_LINK_DOWN_P1_E1_ISIG_STATUS_SHIFT                            30
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_RX_LPI_P0_E0_ISIG_STATUS                                     (0x1<<31) // Current status of cnig_rx_lpi_p0_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_RX_LPI_P0_E0_ISIG_STATUS_SHIFT                               31
+#define CPMU_REG_CPMU_INPUT_SIG_STATUS_1                                                                     0x030314UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_CNIG_RX_LPI_P0_E1_ISIG_STATUS                                     (0x1<<0) // Current status of cnig_rx_lpi_p0_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_CNIG_RX_LPI_P0_E1_ISIG_STATUS_SHIFT                               0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_CNIG_RX_LPI_P1_E0_ISIG_STATUS                                     (0x1<<1) // Current status of cnig_rx_lpi_p1_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_CNIG_RX_LPI_P1_E0_ISIG_STATUS_SHIFT                               1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_CNIG_RX_LPI_P1_E1_ISIG_STATUS                                     (0x1<<2) // Current status of cnig_rx_lpi_p1_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_CNIG_RX_LPI_P1_E1_ISIG_STATUS_SHIFT                               2
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_DORQ_TX_WAKEUP_E0_ISIG_STATUS                                     (0x3<<3) // Current status of dorq_tx_wakeup_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_DORQ_TX_WAKEUP_E0_ISIG_STATUS_SHIFT                               3
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_DORQ_TX_WAKEUP_E1_ISIG_STATUS                                     (0x3<<5) // Current status of dorq_tx_wakeup_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_DORQ_TX_WAKEUP_E1_ISIG_STATUS_SHIFT                               5
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_MSEM_SEM_IDLE_E0_ISIG_STATUS                                      (0x1<<7) // Current status of msem_sem_idle_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_MSEM_SEM_IDLE_E0_ISIG_STATUS_SHIFT                                7
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_MSEM_SEM_IDLE_E1_ISIG_STATUS                                      (0x1<<8) // Current status of msem_sem_idle_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_MSEM_SEM_IDLE_E1_ISIG_STATUS_SHIFT                                8
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NCSI_RX_EVENT_ISIG_STATUS                                         (0x1<<9) // Current status of ncsi_rx_event
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NCSI_RX_EVENT_ISIG_STATUS_SHIFT                                   9
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_LB_EMPTY_P0_E0_ISIG_STATUS                                    (0x1<<10) // Current status of nig_lb_empty_p0_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_LB_EMPTY_P0_E0_ISIG_STATUS_SHIFT                              10
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_LB_EMPTY_P0_E1_ISIG_STATUS                                    (0x1<<11) // Current status of nig_lb_empty_p0_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_LB_EMPTY_P0_E1_ISIG_STATUS_SHIFT                              11
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_LB_EMPTY_P1_E0_ISIG_STATUS                                    (0x1<<12) // Current status of nig_lb_empty_p1_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_LB_EMPTY_P1_E0_ISIG_STATUS_SHIFT                              12
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_LB_EMPTY_P1_E1_ISIG_STATUS                                    (0x1<<13) // Current status of nig_lb_empty_p1_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_LB_EMPTY_P1_E1_ISIG_STATUS_SHIFT                              13
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_RX_EMPTY_P0_E0_ISIG_STATUS                                    (0x1<<14) // Current status of nig_rx_empty_p0_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_RX_EMPTY_P0_E0_ISIG_STATUS_SHIFT                              14
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_RX_EMPTY_P0_E1_ISIG_STATUS                                    (0x1<<15) // Current status of nig_rx_empty_p0_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_RX_EMPTY_P0_E1_ISIG_STATUS_SHIFT                              15
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_RX_EMPTY_P1_E0_ISIG_STATUS                                    (0x1<<16) // Current status of nig_rx_empty_p1_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_RX_EMPTY_P1_E0_ISIG_STATUS_SHIFT                              16
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_RX_EMPTY_P1_E1_ISIG_STATUS                                    (0x1<<17) // Current status of nig_rx_empty_p1_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_RX_EMPTY_P1_E1_ISIG_STATUS_SHIFT                              17
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_TX_EMPTY_P0_E0_ISIG_STATUS                                    (0x1<<18) // Current status of nig_tx_empty_p0_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_TX_EMPTY_P0_E0_ISIG_STATUS_SHIFT                              18
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_TX_EMPTY_P0_E1_ISIG_STATUS                                    (0x1<<19) // Current status of nig_tx_empty_p0_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_TX_EMPTY_P0_E1_ISIG_STATUS_SHIFT                              19
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_TX_EMPTY_P1_E0_ISIG_STATUS                                    (0x1<<20) // Current status of nig_tx_empty_p1_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_TX_EMPTY_P1_E0_ISIG_STATUS_SHIFT                              20
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_TX_EMPTY_P1_E1_ISIG_STATUS                                    (0x1<<21) // Current status of nig_tx_empty_p1_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_TX_EMPTY_P1_E1_ISIG_STATUS_SHIFT                              21
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_PBF_PATH_EMPTY_E0_ISIG_STATUS                                     (0x1<<22) // Current status of pbf_path_empty_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_PBF_PATH_EMPTY_E0_ISIG_STATUS_SHIFT                               22
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_PBF_PATH_EMPTY_E1_ISIG_STATUS                                     (0x1<<23) // Current status of pbf_path_empty_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_PBF_PATH_EMPTY_E1_ISIG_STATUS_SHIFT                               23
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_PBF_PORT_EMPTY_E0_ISIG_STATUS                                     (0xf<<24) // Current status of pbf_port_empty_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_PBF_PORT_EMPTY_E0_ISIG_STATUS_SHIFT                               24
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_PBF_PORT_EMPTY_E1_ISIG_STATUS                                     (0xf<<28) // Current status of pbf_port_empty_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_PBF_PORT_EMPTY_E1_ISIG_STATUS_SHIFT                               28
+#define CPMU_REG_CPMU_INPUT_SIG_STATUS_2                                                                     0x030318UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_INT_DEASSERT_E0_ISIG_STATUS                                 (0x1<<0) // Current status of pglue_int_deassert_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_INT_DEASSERT_E0_ISIG_STATUS_SHIFT                           0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_INT_DEASSERT_E1_ISIG_STATUS                                 (0x1<<1) // Current status of pglue_int_deassert_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_INT_DEASSERT_E1_ISIG_STATUS_SHIFT                           1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_OBFF_STATE_ISIG_STATUS                                      (0xf<<2) // Current status of pglue_obff_state
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_OBFF_STATE_ISIG_STATUS_SHIFT                                2
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_PATH_IN_D3_E0_ISIG_STATUS                                   (0x1<<6) // Current status of pglue_path_in_d3_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_PATH_IN_D3_E0_ISIG_STATUS_SHIFT                             6
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_PATH_IN_D3_E1_ISIG_STATUS                                   (0x1<<7) // Current status of pglue_path_in_d3_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_PATH_IN_D3_E1_ISIG_STATUS_SHIFT                             7
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_PGL_EMPTY_ISIG_STATUS                                       (0x1<<8) // Current status of pglue_pgl_empty
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_PGL_EMPTY_ISIG_STATUS_SHIFT                                 8
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PSEM_SEM_IDLE_E0_ISIG_STATUS                                      (0x1<<9) // Current status of psem_sem_idle_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PSEM_SEM_IDLE_E0_ISIG_STATUS_SHIFT                                9
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PSEM_SEM_IDLE_E1_ISIG_STATUS                                      (0x1<<10) // Current status of psem_sem_idle_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PSEM_SEM_IDLE_E1_ISIG_STATUS_SHIFT                                10
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PXP_MASTER_PATH_EMPTY_E0_ISIG_STATUS                              (0x1<<11) // Current status of pxp_master_path_empty_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PXP_MASTER_PATH_EMPTY_E0_ISIG_STATUS_SHIFT                        11
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PXP_MASTER_PATH_EMPTY_E1_ISIG_STATUS                              (0x1<<12) // Current status of pxp_master_path_empty_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PXP_MASTER_PATH_EMPTY_E1_ISIG_STATUS_SHIFT                        12
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PXP_TARGET_PATH_EMPTY_E0_ISIG_STATUS                              (0x1<<13) // Current status of pxp_target_path_empty_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PXP_TARGET_PATH_EMPTY_E0_ISIG_STATUS_SHIFT                        13
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PXP_TARGET_PATH_EMPTY_E1_ISIG_STATUS                              (0x1<<14) // Current status of pxp_target_path_empty_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PXP_TARGET_PATH_EMPTY_E1_ISIG_STATUS_SHIFT                        14
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_GLOBAL_EMPTY_E0_ISIG_STATUS                                    (0x1<<15) // Current status of qm_global_empty_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_GLOBAL_EMPTY_E0_ISIG_STATUS_SHIFT                              15
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_GLOBAL_EMPTY_E1_ISIG_STATUS                                    (0x1<<16) // Current status of qm_global_empty_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_GLOBAL_EMPTY_E1_ISIG_STATUS_SHIFT                              16
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_PORT_EMPTY_E0_ISIG_STATUS                                      (0xf<<17) // Current status of qm_port_empty_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_PORT_EMPTY_E0_ISIG_STATUS_SHIFT                                17
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_PORT_EMPTY_E1_ISIG_STATUS                                      (0xf<<21) // Current status of qm_port_empty_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_PORT_EMPTY_E1_ISIG_STATUS_SHIFT                                21
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_TX_EMPTY_E0_ISIG_STATUS                                        (0x1<<25) // Current status of qm_tx_empty_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_TX_EMPTY_E0_ISIG_STATUS_SHIFT                                  25
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_TX_EMPTY_E1_ISIG_STATUS                                        (0x1<<26) // Current status of qm_tx_empty_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_TX_EMPTY_E1_ISIG_STATUS_SHIFT                                  26
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_TM_DURING_SCAN_E0_ISIG_STATUS                                     (0x1<<27) // Current status of tm_during_scan_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_TM_DURING_SCAN_E0_ISIG_STATUS_SHIFT                               27
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_TM_DURING_SCAN_E1_ISIG_STATUS                                     (0x1<<28) // Current status of tm_during_scan_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_TM_DURING_SCAN_E1_ISIG_STATUS_SHIFT                               28
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_TSEM_SEM_IDLE_E0_ISIG_STATUS                                      (0x1<<29) // Current status of tsem_sem_idle_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_TSEM_SEM_IDLE_E0_ISIG_STATUS_SHIFT                                29
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_TSEM_SEM_IDLE_E1_ISIG_STATUS                                      (0x1<<30) // Current status of tsem_sem_idle_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_TSEM_SEM_IDLE_E1_ISIG_STATUS_SHIFT                                30
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_USEM_SEM_IDLE_E0_ISIG_STATUS                                      (0x1<<31) // Current status of usem_sem_idle_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_USEM_SEM_IDLE_E0_ISIG_STATUS_SHIFT                                31
+#define CPMU_REG_CPMU_INPUT_SIG_STATUS_3                                                                     0x03031cUL //Access:R    DataWidth:0x12   // Multi Field Register.
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_USEM_SEM_IDLE_E1_ISIG_STATUS                                      (0x1<<0) // Current status of usem_sem_idle_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_USEM_SEM_IDLE_E1_ISIG_STATUS_SHIFT                                0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_XSEM_SEM_IDLE_E0_ISIG_STATUS                                      (0x1<<1) // Current status of xsem_sem_idle_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_XSEM_SEM_IDLE_E0_ISIG_STATUS_SHIFT                                1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_XSEM_SEM_IDLE_E1_ISIG_STATUS                                      (0x1<<2) // Current status of xsem_sem_idle_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_XSEM_SEM_IDLE_E1_ISIG_STATUS_SHIFT                                2
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_YSEM_SEM_IDLE_E0_ISIG_STATUS                                      (0x1<<3) // Current status of ysem_sem_idle_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_YSEM_SEM_IDLE_E0_ISIG_STATUS_SHIFT                                3
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_YSEM_SEM_IDLE_E1_ISIG_STATUS                                      (0x1<<4) // Current status of ysem_sem_idle_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_YSEM_SEM_IDLE_E1_ISIG_STATUS_SHIFT                                4
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_PCIE_LINK_IN_L1_ISIG_STATUS                                       (0x1<<5) // Current status of pcie_link_in_l1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_PCIE_LINK_IN_L1_ISIG_STATUS_SHIFT                                 5
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_IGU_CPMU_EEE_PENDING_INTERRUPT_E0_ISIG_STATUS                     (0x1<<6) // Current status of igu_cpmu_eee_pending_interrupt_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_IGU_CPMU_EEE_PENDING_INTERRUPT_E0_ISIG_STATUS_SHIFT               6
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_IGU_CPMU_EEE_PENDING_INTERRUPT_E1_ISIG_STATUS                     (0x1<<7) // Current status of igu_cpmu_eee_pending_interrupt_e1
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_IGU_CPMU_EEE_PENDING_INTERRUPT_E1_ISIG_STATUS_SHIFT               7
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_TX_EMPTY_P2_E0_ISIG_STATUS_K2_E5                              (0x1<<8) // Current status of nig_tx_empty_p2_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_TX_EMPTY_P2_E0_ISIG_STATUS_K2_E5_SHIFT                        8
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_TX_EMPTY_P3_E0_ISIG_STATUS_K2_E5                              (0x1<<9) // Current status of nig_tx_empty_p3_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_TX_EMPTY_P3_E0_ISIG_STATUS_K2_E5_SHIFT                        9
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_RX_EMPTY_P2_E0_ISIG_STATUS_K2_E5                              (0x1<<10) // Current status of nig_rx_empty_p2_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_RX_EMPTY_P2_E0_ISIG_STATUS_K2_E5_SHIFT                        10
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_RX_EMPTY_P3_E0_ISIG_STATUS_K2_E5                              (0x1<<11) // Current status of nig_rx_empty_p3_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_RX_EMPTY_P3_E0_ISIG_STATUS_K2_E5_SHIFT                        11
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_LB_EMPTY_P2_E0_ISIG_STATUS_K2_E5                              (0x1<<12) // Current status of nig_lb_empty_p2_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_LB_EMPTY_P2_E0_ISIG_STATUS_K2_E5_SHIFT                        12
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_LB_EMPTY_P3_E0_ISIG_STATUS_K2_E5                              (0x1<<13) // Current status of nig_lb_empty_p3_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_LB_EMPTY_P3_E0_ISIG_STATUS_K2_E5_SHIFT                        13
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_CNIG_LINK_DOWN_P2_E0_ISIG_STATUS_K2_E5                            (0x1<<14) // Current status of cnig_link_down_p2_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_CNIG_LINK_DOWN_P2_E0_ISIG_STATUS_K2_E5_SHIFT                      14
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_CNIG_LINK_DOWN_P3_E0_ISIG_STATUS_K2_E5                            (0x1<<15) // Current status of cnig_link_down_p3_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_CNIG_LINK_DOWN_P3_E0_ISIG_STATUS_K2_E5_SHIFT                      15
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_CNIG_RX_LPI_P2_E0_ISIG_STATUS_K2_E5                               (0x1<<16) // Current status of cnig_rx_lpi_p2_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_CNIG_RX_LPI_P2_E0_ISIG_STATUS_K2_E5_SHIFT                         16
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_CNIG_RX_LPI_P3_E0_ISIG_STATUS_K2_E5                               (0x1<<17) // Current status of cnig_rx_lpi_p3_e0
+  #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_CNIG_RX_LPI_P3_E0_ISIG_STATUS_K2_E5_SHIFT                         17
+#define CPMU_REG_CPMU_OUTPUT_SIG_STATUS                                                                      0x030320UL //Access:R    DataWidth:0x17   // Multi Field Register.
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P0_E0_OSIG_STATUS                                     (0x1<<0) // Current status of cnig_lpi_req_p0_e0
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P0_E0_OSIG_STATUS_SHIFT                               0
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P0_E1_OSIG_STATUS                                     (0x1<<1) // Current status of cnig_lpi_req_p0_e1
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P0_E1_OSIG_STATUS_SHIFT                               1
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P1_E0_OSIG_STATUS                                     (0x1<<2) // Current status of cnig_lpi_req_p1_e0
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P1_E0_OSIG_STATUS_SHIFT                               2
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P1_E1_OSIG_STATUS                                     (0x1<<3) // Current status of cnig_lpi_req_p1_e1
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P1_E1_OSIG_STATUS_SHIFT                               3
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_MAIN_CLK_SLOWDOWN_CMN_OSIG_STATUS                          (0x1<<4) // Current status of erstclk_main_clk_slowdown_cmn
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_MAIN_CLK_SLOWDOWN_CMN_OSIG_STATUS_SHIFT                    4
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_MAIN_CLK_SLOWDOWN_E0_OSIG_STATUS                           (0x1<<5) // Current status of erstclk_main_clk_slowdown_e0
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_MAIN_CLK_SLOWDOWN_E0_OSIG_STATUS_SHIFT                     5
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_MAIN_CLK_SLOWDOWN_E1_OSIG_STATUS                           (0x1<<6) // Current status of erstclk_main_clk_slowdown_e1
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_MAIN_CLK_SLOWDOWN_E1_OSIG_STATUS_SHIFT                     6
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_NW_CLK_SLOWDOWN_CMN_OSIG_STATUS                            (0x1<<7) // Current status of erstclk_nw_clk_slowdown_cmn
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_NW_CLK_SLOWDOWN_CMN_OSIG_STATUS_SHIFT                      7
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_NW_CLK_SLOWDOWN_E0_OSIG_STATUS                             (0x1<<8) // Current status of erstclk_nw_clk_slowdown_e0
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_NW_CLK_SLOWDOWN_E0_OSIG_STATUS_SHIFT                       8
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_NW_CLK_SLOWDOWN_E1_OSIG_STATUS                             (0x1<<9) // Current status of erstclk_nw_clk_slowdown_e1
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_NW_CLK_SLOWDOWN_E1_OSIG_STATUS_SHIFT                       9
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_PCI_CLK_SLOWDOWN_CMN_OSIG_STATUS                           (0x1<<10) // Current status of erstclk_pci_clk_slowdown_cmn
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_PCI_CLK_SLOWDOWN_CMN_OSIG_STATUS_SHIFT                     10
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_PCI_CLK_SLOWDOWN_E0_OSIG_STATUS                            (0x1<<11) // Current status of erstclk_pci_clk_slowdown_e0
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_PCI_CLK_SLOWDOWN_E0_OSIG_STATUS_SHIFT                      11
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_PCI_CLK_SLOWDOWN_E1_OSIG_STATUS                            (0x1<<12) // Current status of erstclk_pci_clk_slowdown_e1
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_PCI_CLK_SLOWDOWN_E1_OSIG_STATUS_SHIFT                      12
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_STORM_CLK_SLOWDOWN_E0_OSIG_STATUS                          (0x1<<13) // Current status of erstclk_storm_clk_slowdown_e0
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_STORM_CLK_SLOWDOWN_E0_OSIG_STATUS_SHIFT                    13
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_STORM_CLK_SLOWDOWN_E1_OSIG_STATUS                          (0x1<<14) // Current status of erstclk_storm_clk_slowdown_e1
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_STORM_CLK_SLOWDOWN_E1_OSIG_STATUS_SHIFT                    14
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_IGU_STALL_INT_E0_OSIG_STATUS                                       (0x1<<15) // Current status of igu_stall_int_e0
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_IGU_STALL_INT_E0_OSIG_STATUS_SHIFT                                 15
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_IGU_STALL_INT_E1_OSIG_STATUS                                       (0x1<<16) // Current status of igu_stall_int_e1
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_IGU_STALL_INT_E1_OSIG_STATUS_SHIFT                                 16
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_PCIE_EARLY_L1_EXIT_OSIG_STATUS                                     (0x1<<17) // Current status of pcie_early_l1_exit
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_PCIE_EARLY_L1_EXIT_OSIG_STATUS_SHIFT                               17
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_PGLUE_SEND_LTR2_OSIG_STATUS                                        (0x1<<18) // Current status of pglue_send_ltr2
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_PGLUE_SEND_LTR2_OSIG_STATUS_SHIFT                                  18
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_PXP_STALL_MEM_E0_OSIG_STATUS                                       (0x1<<19) // Current status of pxp_stall_mem_e0
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_PXP_STALL_MEM_E0_OSIG_STATUS_SHIFT                                 19
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_PXP_STALL_MEM_E1_OSIG_STATUS                                       (0x1<<20) // Current status of pxp_stall_mem_e1
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_PXP_STALL_MEM_E1_OSIG_STATUS_SHIFT                                 20
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P2_E0_OSIG_STATUS_K2_E5                               (0x1<<21) // Current status of cnig_lpi_req_p2_e0
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P2_E0_OSIG_STATUS_K2_E5_SHIFT                         21
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P3_E0_OSIG_STATUS_K2_E5                               (0x1<<22) // Current status of cnig_lpi_req_p3_e0
+  #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P3_E0_OSIG_STATUS_K2_E5_SHIFT                         22
+#define CPMU_REG_LPI_TX_REQ_STAT_RO                                                                          0x030324UL //Access:R    DataWidth:0x20   // Event Counter: Counts number of times the device has gone into LPI.
+#define CPMU_REG_LPI_TX_DURATION_STAT_RO                                                                     0x030328UL //Access:R    DataWidth:0x20   // Duration Counter: Counts number of ticks the device was in LPI state. this is a cumulative counter and has a 25us resolution.
+#define CPMU_REG_LPI_RX_REQ_STAT_RO                                                                          0x03032cUL //Access:R    DataWidth:0x20   // Event Counter: Counts number of times a Rx LPI was received.
+#define CPMU_REG_LPI_RX_DURATION_STAT_RO                                                                     0x030330UL //Access:R    DataWidth:0x20   // Duration Counter: Counts number of ticks the device was in RX LPI state. this is a cumulative counter and has a 25us resolution.
+#define CPMU_REG_LPI_REQ_STAT_RO                                                                             0x030334UL //Access:R    DataWidth:0x20   // Event Counter: Counts number of times both sides went into LPI state.
+#define CPMU_REG_LPI_DURATION_STAT_RO                                                                        0x030338UL //Access:R    DataWidth:0x20   // Duration Counter: Counts number of ticks the device was in LPI state. this is a cumulative counter and has a 25us resolution.
+#define CPMU_REG_OBFF_STALL_MEM_STAT_RO                                                                      0x03033cUL //Access:R    DataWidth:0x20   // Event Counter: Counts number of times the Stall Memory was asserted for OBFF.
+#define CPMU_REG_OBFF_STALL_MEM_DURATION_STAT_RO                                                             0x030340UL //Access:R    DataWidth:0x20   // Duration Counter: Counts number of ticks the device was in Stall Memory state. this is a cumulative counter and has a 25us resolution.
+#define CPMU_REG_OBFF_STALL_INT_STAT_RO                                                                      0x030344UL //Access:R    DataWidth:0x20   // Event Counter: Counts number of times the Stall Intterupt was asserted for OBFF.
+#define CPMU_REG_OBFF_STALL_INT_DURATION_STAT_RO                                                             0x030348UL //Access:R    DataWidth:0x20   // Duration Counter: Counts number of ticks the device was in Stall Intterupt state. this is a cumulative counter and has a 25us resolution.
+#define CPMU_REG_L1_ENTRY_STAT_RO                                                                            0x03034cUL //Access:R    DataWidth:0x20   // Event Counter: Counts number of times the device has gone into L1
+#define CPMU_REG_L1_ENTRY_DURATION_STAT_RO                                                                   0x030350UL //Access:R    DataWidth:0x20   // Duration Counter: Counts number of ticks the device was in L1 state. this is a cumulative counter and has a 25us resolution.
+#define CPMU_REG_LTR_SEND_STAT_RO                                                                            0x030354UL //Access:R    DataWidth:0x20   // Event Counter: Counts number of times the device has gone into LTR
+#define CPMU_REG_LTR_SEND_DURATION_STAT_RO                                                                   0x030358UL //Access:R    DataWidth:0x20   // Duration Counter: Counts number of ticks the device was in LTR state. this is a cumulative counter and has a 25us resolution.
+#define CPMU_REG_MCS_SLOWDOWN_STAT_RO                                                                        0x03035cUL //Access:R    DataWidth:0x20   // Event Counter:
+#define CPMU_REG_MCS_DURATION_STAT_RO                                                                        0x030360UL //Access:R    DataWidth:0x20   // Duration Counter: counts number of ticks main clock was in slow down state. this is a cumulative counter and has a 25us resolution.
+#define CPMU_REG_SCS_SLOWDOWN_STAT_RO                                                                        0x030364UL //Access:R    DataWidth:0x20   // Event Counter:
+#define CPMU_REG_SCS_DURATION_STAT_RO                                                                        0x030368UL //Access:R    DataWidth:0x20   // Duration Counter:  counts number of ticks storm clock was in slow down state. this is a cumulative counter and has a 25us resolution.
+#define CPMU_REG_NCS_SLOWDOWN_STAT_RO                                                                        0x03036cUL //Access:R    DataWidth:0x20   // Event Counter:
+#define CPMU_REG_NCS_DURATION_STAT_RO                                                                        0x030370UL //Access:R    DataWidth:0x20   // Duration Counter: counts number of ticks network clock was in slow down state. this is a cumulative counter and has a 25us resolution.
+#define CPMU_REG_PCS_SLOWDOWN_STAT_RO                                                                        0x030374UL //Access:R    DataWidth:0x20   // Event Counter:
+#define CPMU_REG_PCS_DURATION_STAT_RO                                                                        0x030378UL //Access:R    DataWidth:0x20   // Duration Counter: counts number of ticks pci clock was in slow down state. this is a cumulative counter and has a 25us resolution.
+#define CPMU_REG_LPI_TX_REQ_STAT                                                                             0x03037cUL //Access:RC   DataWidth:0x20   // Event Counter: Counts number of times the device has gone into LPI.
+#define CPMU_REG_LPI_TX_DURATION_STAT                                                                        0x030380UL //Access:RC   DataWidth:0x20   // Duration Counter: Counts number of ticks the device was in LPI state. this is a cumulative counter and has a 25us resolution.
+#define CPMU_REG_LPI_RX_REQ_STAT                                                                             0x030384UL //Access:RC   DataWidth:0x20   // Event Counter: Counts number of times a Rx LPI was received.
+#define CPMU_REG_LPI_RX_DURATION_STAT                                                                        0x030388UL //Access:RC   DataWidth:0x20   // Duration Counter: Counts number of ticks the device was in RX LPI state. this is a cumulative counter and has a 25us resolution.
+#define CPMU_REG_LPI_REQ_STAT                                                                                0x03038cUL //Access:RC   DataWidth:0x20   // Event Counter: Counts number of times both sides went into LPI state.
+#define CPMU_REG_LPI_DURATION_STAT                                                                           0x030390UL //Access:RC   DataWidth:0x20   // Duration Counter: Counts number of ticks the device was in LPI state. this is a cumulative counter and has a 25us resolution.
+#define CPMU_REG_OBFF_STALL_MEM_STAT                                                                         0x030394UL //Access:RC   DataWidth:0x20   // Event Counter: Counts number of times the Stall Memory was asserted for OBFF.
+#define CPMU_REG_OBFF_STALL_MEM_DURATION_STAT                                                                0x030398UL //Access:RC   DataWidth:0x20   // Duration Counter: Counts number of ticks the device was in Stall Memory state. this is a cumulative counter and has a 25us resolution.
+#define CPMU_REG_OBFF_STALL_INT_STAT                                                                         0x03039cUL //Access:RC   DataWidth:0x20   // Event Counter: Counts number of times the Stall Intterupt was asserted for OBFF.
+#define CPMU_REG_OBFF_STALL_INT_DURATION_STAT                                                                0x0303a0UL //Access:RC   DataWidth:0x20   // Duration Counter: Counts number of ticks the device was in Stall Intterupt state. this is a cumulative counter and has a 25us resolution.
+#define CPMU_REG_L1_ENTRY_STAT                                                                               0x0303a4UL //Access:RC   DataWidth:0x20   // Event Counter: Counts number of times the device has gone into L1
+#define CPMU_REG_L1_ENTRY_DURATION_STAT                                                                      0x0303a8UL //Access:RC   DataWidth:0x20   // Duration Counter: Counts number of ticks the device was in L1 state. this is a cumulative counter and has a 25us resolution.
+#define CPMU_REG_LTR_SEND_STAT                                                                               0x0303acUL //Access:RC   DataWidth:0x20   // Event Counter: Counts number of times the device has gone into LTR
+#define CPMU_REG_LTR_SEND_DURATION_STAT                                                                      0x0303b0UL //Access:RC   DataWidth:0x20   // Duration Counter: Counts number of ticks the device was in LTR state. this is a cumulative counter and has a 25us resolution.
+#define CPMU_REG_MCS_SLOWDOWN_STAT                                                                           0x0303b4UL //Access:RC   DataWidth:0x20   // Event Counter:
+#define CPMU_REG_MCS_DURATION_STAT                                                                           0x0303b8UL //Access:RC   DataWidth:0x20   // Duration Counter: Counts number of ticks main clock was in slow down state. this is a cumulative counter and has a 25us resolution.
+#define CPMU_REG_SCS_SLOWDOWN_STAT                                                                           0x0303bcUL //Access:RC   DataWidth:0x20   // Event Counter:
+#define CPMU_REG_SCS_DURATION_STAT                                                                           0x0303c0UL //Access:RC   DataWidth:0x20   // Duration Counter: counts number of ticks storm clock was in slow down state. this is a cumulative counter and has a 25us resolution.
+#define CPMU_REG_NCS_SLOWDOWN_STAT                                                                           0x0303c4UL //Access:RC   DataWidth:0x20   // Event Counter:
+#define CPMU_REG_NCS_DURATION_STAT                                                                           0x0303c8UL //Access:RC   DataWidth:0x20   // Duration Counter: counts number of ticks network clock was in slow down state. this is a cumulative counter and has a 25us resolution.
+#define CPMU_REG_PCS_SLOWDOWN_STAT                                                                           0x0303ccUL //Access:RC   DataWidth:0x20   // Event Counter:
+#define CPMU_REG_PCS_DURATION_STAT                                                                           0x0303d0UL //Access:RC   DataWidth:0x20   // Duration Counter: counts number of ticks pci clock was in slow down state. this is a cumulative counter and has a 25us resolution.
+#define CPMU_REG_CLK_TO_CLK_ST_CNT_VAL                                                                       0x0303d4UL //Access:RW   DataWidth:0x5    // This register configures the delay for slowing down of STORM clock after main clock is slowed down.
+#define CPMU_REG_CLK_ST_TO_CLK_CNT_VAL                                                                       0x0303d8UL //Access:RW   DataWidth:0x5    // This register configures the delay for waking up of main clock after STORM clock is up and running.
+#define CPMU_REG_ECO_RESERVED                                                                                0x0303dcUL //Access:RW   DataWidth:0x8    // Reserved for future ECOs
+#define CPMU_REG_INT_STS_0                                                                                   0x0303e0UL //Access:R    DataWidth:0x1    // Multi Field Register.
+  #define CPMU_REG_INT_STS_0_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define CPMU_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                             0
+#define CPMU_REG_INT_MASK_0                                                                                  0x0303e4UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define CPMU_REG_INT_MASK_0_ADDRESS_ERROR                                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: CPMU_REG_INT_STS_0.ADDRESS_ERROR .
+  #define CPMU_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                            0
+#define CPMU_REG_INT_STS_WR_0                                                                                0x0303e8UL //Access:WR   DataWidth:0x1    // Multi Field Register.
+  #define CPMU_REG_INT_STS_WR_0_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define CPMU_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                          0
+#define CPMU_REG_INT_STS_CLR_0                                                                               0x0303ecUL //Access:RC   DataWidth:0x1    // Multi Field Register.
+  #define CPMU_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                               (0x1<<0) // Signals an unknown address to the rf module.
+  #define CPMU_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                         0
+#define CPMU_REG_SDM_SQ_COUNTER_E0_P0                                                                        0x0303f0UL //Access:R    DataWidth:0x20   // SDM SQ counter value for Engine 0, port 0.
+#define CPMU_REG_SDM_SQ_COUNTER_E0_P1                                                                        0x0303f4UL //Access:R    DataWidth:0x20   // SDM SQ counter value for Engine 0, port 1.
+#define CPMU_REG_SDM_SQ_COUNTER_E1_P0                                                                        0x0303f8UL //Access:R    DataWidth:0x20   // SDM SQ counter value for Engine 1, port 0.
+#define CPMU_REG_SDM_SQ_COUNTER_E1_P1                                                                        0x0303fcUL //Access:R    DataWidth:0x20   // SDM SQ counter value for Engine 1, port 1.
+#define CPMU_REG_SDM_SQ_COUNTER_E0_P2_K2_E5                                                                  0x030400UL //Access:R    DataWidth:0x20   // SDM SQ counter value for Engine 0, port 2.
+#define CPMU_REG_SDM_SQ_COUNTER_E0_P3_K2_E5                                                                  0x030404UL //Access:R    DataWidth:0x20   // SDM SQ counter value for Engine 0, port 3.
+#define NCSI_REG_PRTY_MASK_H_0_BB_K2                                                                         0x040004UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define NCSI_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                     (0x1<<0) // This bit masks, when set, the Parity bit: NCSI_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define NCSI_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                               0
+#define NCSI_REG_MEM_ECC_EVENTS_BB_K2                                                                        0x040010UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define NCSI_REG_CONFIG                                                                                      0x040200UL //Access:RW   DataWidth:0xe    // Multi Field Register.
+  #define NCSI_REG_CONFIG_PROMISCOUS                                                                         (0x1<<0) // Setting this bit to a '1' will result in all packets received from BMC to be routed to MCP.
+  #define NCSI_REG_CONFIG_PROMISCOUS_SHIFT                                                                   0
+  #define NCSI_REG_CONFIG_ALL_MCP                                                                            (0x1<<1) // Setting this bit to a '1' will result in all packets received from BMC that meet the matching of Source MAC address of the packet to the stored channel MAC address criteria to be routed to MCP.
+  #define NCSI_REG_CONFIG_ALL_MCP_SHIFT                                                                      1
+  #define NCSI_REG_CONFIG_FWD_BCAST_TO_MCP                                                                   (0x1<<2) // 0 -> Send all broadcast packets to the appropriate network port. 1 -> Send all broadcast packets to MCP
+  #define NCSI_REG_CONFIG_FWD_BCAST_TO_MCP_SHIFT                                                             2
+  #define NCSI_REG_CONFIG_FWD_MCAST_TO_MCP                                                                   (0x1<<3) // 0 -> Send all multicast packets to the appropriate network port. 1 -> Send all multicast packets to MCP
+  #define NCSI_REG_CONFIG_FWD_MCAST_TO_MCP_SHIFT                                                             3
+  #define NCSI_REG_CONFIG_USE_VLAN_FOR_COMP                                                                  (0x1<<4) // 0 -> only MAC address is used for comparison to detect Host2BMC traffic. 1 -> MAC and VLAN are used for comparision to detect Host2BMC traffic.
+  #define NCSI_REG_CONFIG_USE_VLAN_FOR_COMP_SHIFT                                                            4
+  #define NCSI_REG_CONFIG_SA_LEARNING_EN                                                                     (0x1<<5) // 0 -> Do not enable source MAC address learning for packets from Host to BMC. 1 -> Enable source MAC address learning for packets from Host to BMC.
+  #define NCSI_REG_CONFIG_SA_LEARNING_EN_SHIFT                                                               5
+  #define NCSI_REG_CONFIG_INVALIDATE_AGED_ENTRIES                                                            (0x1<<6) // 0 -> Entries in SA Learning Cache are valid even after they are aged. 1 -> Entries in SA Learning Cache become invalid after they are aged.
+  #define NCSI_REG_CONFIG_INVALIDATE_AGED_ENTRIES_SHIFT                                                      6
+  #define NCSI_REG_CONFIG_FLOW_CONTROL_EN                                                                    (0x1<<7) // Setting this bit to a '1' will result in enabling flow control towards the BMC.
+  #define NCSI_REG_CONFIG_FLOW_CONTROL_EN_SHIFT                                                              7
+  #define NCSI_REG_CONFIG_SW_PAUSE                                                                           (0x1<<8) // Setting this bit to a '1' will result in XOFF to be sent out to BMC. Clearing this register after it was set to '1' will cause an XON to be sent out.
+  #define NCSI_REG_CONFIG_SW_PAUSE_SHIFT                                                                     8
+  #define NCSI_REG_CONFIG_HOST2BMC_EN                                                                        (0x1<<9) // Setting this bit to a '1' tells the HW that Host2BMC traffic is enabled.
+  #define NCSI_REG_CONFIG_HOST2BMC_EN_SHIFT                                                                  9
+  #define NCSI_REG_CONFIG_MII_SEL                                                                            (0x1<<10) // 0 -> Select NCSI RMII interface as the MII port 1 -> Select SGMII MII interface as the MII port
+  #define NCSI_REG_CONFIG_MII_SEL_SHIFT                                                                      10
+  #define NCSI_REG_CONFIG_MGMT_SRC_SEL                                                                       (0x1<<11) // 0 -> Select NCSI RMII interface as the Management Port 1 -> Select Proprietary SGMII interface as the Management port
+  #define NCSI_REG_CONFIG_MGMT_SRC_SEL_SHIFT                                                                 11
+  #define NCSI_REG_CONFIG_DROP_ALL_PKTS_WHEN_FULL                                                            (0x1<<12) // 1 -> When BMB asserts any full condition, drop all the packets 0 -> Drop packets destined only to the particular TC when the TC specific full is asserted. Note: When global BMB Full condition is asserted, all the packets will be dropped irrespective of the settings of this register.
+  #define NCSI_REG_CONFIG_DROP_ALL_PKTS_WHEN_FULL_SHIFT                                                      12
+  #define NCSI_REG_CONFIG_ALL_PASS_THRU_TO_HOST                                                              (0x1<<13) // 1 -> When this bit is set, all pass through traffic will be directed to host, if HOST2BMC is enabled. 0 -> When not set, packets will follow the normal decision tree.
+  #define NCSI_REG_CONFIG_ALL_PASS_THRU_TO_HOST_SHIFT                                                        13
+#define NCSI_REG_PKT_ETHERTYPE_VALID                                                                         0x040204UL //Access:RW   DataWidth:0x1    // When set, this bit indicates that the value in pkt_ethertype register is valid.
+#define NCSI_REG_PKT_ETHERTYPE                                                                               0x040208UL //Access:RW   DataWidth:0x10   // A packet received from BMC will an ethertype of 0x88F8 will be sent to MCP as these are NCSI control packets as defined in the spec. This register allows SW to program one more ethertype other that 0x88F8, a match of which will result in packets being sent to MCP.
+#define NCSI_REG_BMC_MAC_VALID_FLAG_0                                                                        0x04020cUL //Access:RW   DataWidth:0x1    // This bit shows whether the corresponding entry in the BMC MAC address + VLAN is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_BMC_MAC_VALID_FLAG_1                                                                        0x040210UL //Access:RW   DataWidth:0x1    // This bit shows whether the corresponding entry in the BMC MAC address + VLAN is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_BMC_MAC_VALID_FLAG_2                                                                        0x040214UL //Access:RW   DataWidth:0x1    // This bit shows whether the corresponding entry in the BMC MAC address + VLAN is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_BMC_MAC_VALID_FLAG_3                                                                        0x040218UL //Access:RW   DataWidth:0x1    // This bit shows whether the corresponding entry in the BMC MAC address + VLAN is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_BMC_MAC_ADDR_LO_0                                                                           0x04021cUL //Access:RW   DataWidth:0x20   // When the NCSI interface powers up, BMC communicates with the MCP FW on the number of channels available in the chip. Each channel represents the number of network ports in the chip. BMC will allocate one MAC address for each channel. When BMC wants to send a packet to that channel, it will use the MAC address as the Source MAC address in the packet. This allows the NIC to route the packet to the appropriate channel. MCP FW will write the MAC address to these registers so that HW can do the routing. These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_BMC_MAC_ADDR_HI_0                                                                           0x040220UL //Access:RW   DataWidth:0x10   // When the NCSI interface powers up, BMC communicates with the MCP FW on the number of channels available in the chip. Each channel represents the number of network ports in the chip. BMC will allocate one MAC address for each channel. When BMC wants to send a packet to that channel, it will use the MAC address as the Source MAC address in the packet. This allows the NIC to route the packet to the appropriate channel. MCP FW will write the MAC address to these registers so that HW can do the routing. These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_BMC_MAC_ADDR_LO_1                                                                           0x040224UL //Access:RW   DataWidth:0x20   // When the NCSI interface powers up, BMC communicates with the MCP FW on the number of channels available in the chip. Each channel represents the number of network ports in the chip. BMC will allocate one MAC address for each channel. When BMC wants to send a packet to that channel, it will use the MAC address as the Source MAC address in the packet. This allows the NIC to route the packet to the appropriate channel. MCP FW will write the MAC address to these registers so that HW can do the routing. These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_BMC_MAC_ADDR_HI_1                                                                           0x040228UL //Access:RW   DataWidth:0x10   // When the NCSI interface powers up, BMC communicates with the MCP FW on the number of channels available in the chip. Each channel represents the number of network ports in the chip. BMC will allocate one MAC address for each channel. When BMC wants to send a packet to that channel, it will use the MAC address as the Source MAC address in the packet. This allows the NIC to route the packet to the appropriate channel. MCP FW will write the MAC address to these registers so that HW can do the routing. These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_BMC_MAC_ADDR_LO_2                                                                           0x04022cUL //Access:RW   DataWidth:0x20   // When the NCSI interface powers up, BMC communicates with the MCP FW on the number of channels available in the chip. Each channel represents the number of network ports in the chip. BMC will allocate one MAC address for each channel. When BMC wants to send a packet to that channel, it will use the MAC address as the Source MAC address in the packet. This allows the NIC to route the packet to the appropriate channel. MCP FW will write the MAC address to these registers so that HW can do the routing. These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_BMC_MAC_ADDR_HI_2                                                                           0x040230UL //Access:RW   DataWidth:0x10   // When the NCSI interface powers up, BMC communicates with the MCP FW on the number of channels available in the chip. Each channel represents the number of network ports in the chip. BMC will allocate one MAC address for each channel. When BMC wants to send a packet to that channel, it will use the MAC address as the Source MAC address in the packet. This allows the NIC to route the packet to the appropriate channel. MCP FW will write the MAC address to these registers so that HW can do the routing. These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_BMC_MAC_ADDR_LO_3                                                                           0x040234UL //Access:RW   DataWidth:0x20   // When the NCSI interface powers up, BMC communicates with the MCP FW on the number of channels available in the chip. Each channel represents the number of network ports in the chip. BMC will allocate one MAC address for each channel. When BMC wants to send a packet to that channel, it will use the MAC address as the Source MAC address in the packet. This allows the NIC to route the packet to the appropriate channel. MCP FW will write the MAC address to these registers so that HW can do the routing. These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_BMC_MAC_ADDR_HI_3                                                                           0x040238UL //Access:RW   DataWidth:0x10   // When the NCSI interface powers up, BMC communicates with the MCP FW on the number of channels available in the chip. Each channel represents the number of network ports in the chip. BMC will allocate one MAC address for each channel. When BMC wants to send a packet to that channel, it will use the MAC address as the Source MAC address in the packet. This allows the NIC to route the packet to the appropriate channel. MCP FW will write the MAC address to these registers so that HW can do the routing. These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_BMC_VLAN_ID_0                                                                               0x04023cUL //Access:RW   DataWidth:0xc    // This register stores the VLAN ID associated with the corresponding channel.
+#define NCSI_REG_BMC_VLAN_ID_1                                                                               0x040240UL //Access:RW   DataWidth:0xc    // This register stores the VLAN ID associated with the corresponding channel.
+#define NCSI_REG_BMC_VLAN_ID_2                                                                               0x040244UL //Access:RW   DataWidth:0xc    // This register stores the VLAN ID associated with the corresponding channel.
+#define NCSI_REG_BMC_VLAN_ID_3                                                                               0x040248UL //Access:RW   DataWidth:0xc    // This register stores the VLAN ID associated with the corresponding channel.
+#define NCSI_REG_SA_STATIC_VALID_FLAG_0                                                                      0x04024cUL //Access:RW   DataWidth:0x1    // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_SA_STATIC_VALID_FLAG_1                                                                      0x040250UL //Access:RW   DataWidth:0x1    // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_SA_STATIC_VALID_FLAG_2                                                                      0x040254UL //Access:RW   DataWidth:0x1    // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_SA_STATIC_VALID_FLAG_3                                                                      0x040258UL //Access:RW   DataWidth:0x1    // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_SA_STATIC_VALID_FLAG_4                                                                      0x04025cUL //Access:RW   DataWidth:0x1    // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_SA_STATIC_VALID_FLAG_5                                                                      0x040260UL //Access:RW   DataWidth:0x1    // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_SA_STATIC_VALID_FLAG_6                                                                      0x040264UL //Access:RW   DataWidth:0x1    // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_SA_STATIC_VALID_FLAG_7                                                                      0x040268UL //Access:RW   DataWidth:0x1    // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_SA_STATIC_VALID_FLAG_8                                                                      0x04026cUL //Access:RW   DataWidth:0x1    // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_SA_STATIC_VALID_FLAG_9                                                                      0x040270UL //Access:RW   DataWidth:0x1    // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_SA_STATIC_VALID_FLAG_10                                                                     0x040274UL //Access:RW   DataWidth:0x1    // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_SA_STATIC_VALID_FLAG_11                                                                     0x040278UL //Access:RW   DataWidth:0x1    // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_SA_STATIC_VALID_FLAG_12                                                                     0x04027cUL //Access:RW   DataWidth:0x1    // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_SA_STATIC_VALID_FLAG_13                                                                     0x040280UL //Access:RW   DataWidth:0x1    // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_SA_STATIC_VALID_FLAG_14                                                                     0x040284UL //Access:RW   DataWidth:0x1    // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_SA_STATIC_VALID_FLAG_15                                                                     0x040288UL //Access:RW   DataWidth:0x1    // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_SA_STATIC_MAC_ADDR_LO_0                                                                     0x04028cUL //Access:RW   DataWidth:0x20   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_HI_0                                                                     0x040290UL //Access:RW   DataWidth:0x10   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_LO_1                                                                     0x040294UL //Access:RW   DataWidth:0x20   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_HI_1                                                                     0x040298UL //Access:RW   DataWidth:0x10   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_LO_2                                                                     0x04029cUL //Access:RW   DataWidth:0x20   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_HI_2                                                                     0x0402a0UL //Access:RW   DataWidth:0x10   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_LO_3                                                                     0x0402a4UL //Access:RW   DataWidth:0x20   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_HI_3                                                                     0x0402a8UL //Access:RW   DataWidth:0x10   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_LO_4                                                                     0x0402acUL //Access:RW   DataWidth:0x20   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_HI_4                                                                     0x0402b0UL //Access:RW   DataWidth:0x10   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_LO_5                                                                     0x0402b4UL //Access:RW   DataWidth:0x20   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_HI_5                                                                     0x0402b8UL //Access:RW   DataWidth:0x10   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_LO_6                                                                     0x0402bcUL //Access:RW   DataWidth:0x20   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_HI_6                                                                     0x0402c0UL //Access:RW   DataWidth:0x10   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_LO_7                                                                     0x0402c4UL //Access:RW   DataWidth:0x20   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_HI_7                                                                     0x0402c8UL //Access:RW   DataWidth:0x10   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_LO_8                                                                     0x0402ccUL //Access:RW   DataWidth:0x20   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_HI_8                                                                     0x0402d0UL //Access:RW   DataWidth:0x10   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_LO_9                                                                     0x0402d4UL //Access:RW   DataWidth:0x20   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_HI_9                                                                     0x0402d8UL //Access:RW   DataWidth:0x10   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_LO_10                                                                    0x0402dcUL //Access:RW   DataWidth:0x20   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_HI_10                                                                    0x0402e0UL //Access:RW   DataWidth:0x10   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_LO_11                                                                    0x0402e4UL //Access:RW   DataWidth:0x20   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_HI_11                                                                    0x0402e8UL //Access:RW   DataWidth:0x10   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_LO_12                                                                    0x0402ecUL //Access:RW   DataWidth:0x20   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_HI_12                                                                    0x0402f0UL //Access:RW   DataWidth:0x10   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_LO_13                                                                    0x0402f4UL //Access:RW   DataWidth:0x20   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_HI_13                                                                    0x0402f8UL //Access:RW   DataWidth:0x10   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_LO_14                                                                    0x0402fcUL //Access:RW   DataWidth:0x20   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_HI_14                                                                    0x040300UL //Access:RW   DataWidth:0x10   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_LO_15                                                                    0x040304UL //Access:RW   DataWidth:0x20   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_MAC_ADDR_HI_15                                                                    0x040308UL //Access:RW   DataWidth:0x10   // This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_SA_STATIC_VLAN_ID_0                                                                         0x04030cUL //Access:RW   DataWidth:0xc    // This is the VLAN ID associated with the corresponding MAC address of the static cache.
+#define NCSI_REG_SA_STATIC_VLAN_ID_1                                                                         0x040310UL //Access:RW   DataWidth:0xc    // This is the VLAN ID associated with the corresponding MAC address of the static cache.
+#define NCSI_REG_SA_STATIC_VLAN_ID_2                                                                         0x040314UL //Access:RW   DataWidth:0xc    // This is the VLAN ID associated with the corresponding MAC address of the static cache.
+#define NCSI_REG_SA_STATIC_VLAN_ID_3                                                                         0x040318UL //Access:RW   DataWidth:0xc    // This is the VLAN ID associated with the corresponding MAC address of the static cache.
+#define NCSI_REG_SA_STATIC_VLAN_ID_4                                                                         0x04031cUL //Access:RW   DataWidth:0xc    // This is the VLAN ID associated with the corresponding MAC address of the static cache.
+#define NCSI_REG_SA_STATIC_VLAN_ID_5                                                                         0x040320UL //Access:RW   DataWidth:0xc    // This is the VLAN ID associated with the corresponding MAC address of the static cache.
+#define NCSI_REG_SA_STATIC_VLAN_ID_6                                                                         0x040324UL //Access:RW   DataWidth:0xc    // This is the VLAN ID associated with the corresponding MAC address of the static cache.
+#define NCSI_REG_SA_STATIC_VLAN_ID_7                                                                         0x040328UL //Access:RW   DataWidth:0xc    // This is the VLAN ID associated with the corresponding MAC address of the static cache.
+#define NCSI_REG_SA_STATIC_VLAN_ID_8                                                                         0x04032cUL //Access:RW   DataWidth:0xc    // This is the VLAN ID associated with the corresponding MAC address of the static cache.
+#define NCSI_REG_SA_STATIC_VLAN_ID_9                                                                         0x040330UL //Access:RW   DataWidth:0xc    // This is the VLAN ID associated with the corresponding MAC address of the static cache.
+#define NCSI_REG_SA_STATIC_VLAN_ID_10                                                                        0x040334UL //Access:RW   DataWidth:0xc    // This is the VLAN ID associated with the corresponding MAC address of the static cache.
+#define NCSI_REG_SA_STATIC_VLAN_ID_11                                                                        0x040338UL //Access:RW   DataWidth:0xc    // This is the VLAN ID associated with the corresponding MAC address of the static cache.
+#define NCSI_REG_SA_STATIC_VLAN_ID_12                                                                        0x04033cUL //Access:RW   DataWidth:0xc    // This is the VLAN ID associated with the corresponding MAC address of the static cache.
+#define NCSI_REG_SA_STATIC_VLAN_ID_13                                                                        0x040340UL //Access:RW   DataWidth:0xc    // This is the VLAN ID associated with the corresponding MAC address of the static cache.
+#define NCSI_REG_SA_STATIC_VLAN_ID_14                                                                        0x040344UL //Access:RW   DataWidth:0xc    // This is the VLAN ID associated with the corresponding MAC address of the static cache.
+#define NCSI_REG_SA_STATIC_VLAN_ID_15                                                                        0x040348UL //Access:RW   DataWidth:0xc    // This is the VLAN ID associated with the corresponding MAC address of the static cache.
+#define NCSI_REG_SA_CACHE_VALID_FLAG_0                                                                       0x04034cUL //Access:RW   DataWidth:0x1    // This bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_SA_CACHE_REPLACEMENT_FLAG_0                                                                 0x040350UL //Access:RW   DataWidth:0x1    // This bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replaced. When a entry is logged into the cache, a timer is started. Every time another packet is received on the same entry, the timer is re-started. When the timer expires, the entry is deemed replaceable. Note that the timer doesn't clear the valid flag. So if the entry is not replaced and there is a hit on the entry, the replacement flag is cleared and timer is started again.
+#define NCSI_REG_SA_CACHE_VALID_FLAG_1                                                                       0x040354UL //Access:RW   DataWidth:0x1    // This bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_SA_CACHE_REPLACEMENT_FLAG_1                                                                 0x040358UL //Access:RW   DataWidth:0x1    // This bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replaced. When a entry is logged into the cache, a timer is started. Every time another packet is received on the same entry, the timer is re-started. When the timer expires, the entry is deemed replaceable. Note that the timer doesn't clear the valid flag. So if the entry is not replaced and there is a hit on the entry, the replacement flag is cleared and timer is started again.
+#define NCSI_REG_SA_CACHE_VALID_FLAG_2                                                                       0x04035cUL //Access:RW   DataWidth:0x1    // This bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_SA_CACHE_REPLACEMENT_FLAG_2                                                                 0x040360UL //Access:RW   DataWidth:0x1    // This bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replaced. When a entry is logged into the cache, a timer is started. Every time another packet is received on the same entry, the timer is re-started. When the timer expires, the entry is deemed replaceable. Note that the timer doesn't clear the valid flag. So if the entry is not replaced and there is a hit on the entry, the replacement flag is cleared and timer is started again.
+#define NCSI_REG_SA_CACHE_VALID_FLAG_3                                                                       0x040364UL //Access:RW   DataWidth:0x1    // This bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_SA_CACHE_REPLACEMENT_FLAG_3                                                                 0x040368UL //Access:RW   DataWidth:0x1    // This bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replaced. When a entry is logged into the cache, a timer is started. Every time another packet is received on the same entry, the timer is re-started. When the timer expires, the entry is deemed replaceable. Note that the timer doesn't clear the valid flag. So if the entry is not replaced and there is a hit on the entry, the replacement flag is cleared and timer is started again.
+#define NCSI_REG_SA_CACHE_VALID_FLAG_4                                                                       0x04036cUL //Access:RW   DataWidth:0x1    // This bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_SA_CACHE_REPLACEMENT_FLAG_4                                                                 0x040370UL //Access:RW   DataWidth:0x1    // This bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replaced. When a entry is logged into the cache, a timer is started. Every time another packet is received on the same entry, the timer is re-started. When the timer expires, the entry is deemed replaceable. Note that the timer doesn't clear the valid flag. So if the entry is not replaced and there is a hit on the entry, the replacement flag is cleared and timer is started again.
+#define NCSI_REG_SA_CACHE_VALID_FLAG_5                                                                       0x040374UL //Access:RW   DataWidth:0x1    // This bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_SA_CACHE_REPLACEMENT_FLAG_5                                                                 0x040378UL //Access:RW   DataWidth:0x1    // This bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replaced. When a entry is logged into the cache, a timer is started. Every time another packet is received on the same entry, the timer is re-started. When the timer expires, the entry is deemed replaceable. Note that the timer doesn't clear the valid flag. So if the entry is not replaced and there is a hit on the entry, the replacement flag is cleared and timer is started again.
+#define NCSI_REG_SA_CACHE_VALID_FLAG_6                                                                       0x04037cUL //Access:RW   DataWidth:0x1    // This bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_SA_CACHE_REPLACEMENT_FLAG_6                                                                 0x040380UL //Access:RW   DataWidth:0x1    // This bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replaced. When a entry is logged into the cache, a timer is started. Every time another packet is received on the same entry, the timer is re-started. When the timer expires, the entry is deemed replaceable. Note that the timer doesn't clear the valid flag. So if the entry is not replaced and there is a hit on the entry, the replacement flag is cleared and timer is started again.
+#define NCSI_REG_SA_CACHE_VALID_FLAG_7                                                                       0x040384UL //Access:RW   DataWidth:0x1    // This bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
+#define NCSI_REG_SA_CACHE_REPLACEMENT_FLAG_7                                                                 0x040388UL //Access:RW   DataWidth:0x1    // This bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replaced. When a entry is logged into the cache, a timer is started. Every time another packet is received on the same entry, the timer is re-started. When the timer expires, the entry is deemed replaceable. Note that the timer doesn't clear the valid flag. So if the entry is not replaced and there is a hit on the entry, the replacement flag is cleared and timer is started again.
+#define NCSI_REG_SA_CACHE_MAC_ADDR_LO_0                                                                      0x04038cUL //Access:RW   DataWidth:0x20   // NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_SA_CACHE_MAC_ADDR_HI_0                                                                      0x040390UL //Access:RW   DataWidth:0x10   // NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_SA_CACHE_MAC_ADDR_LO_1                                                                      0x040394UL //Access:RW   DataWidth:0x20   // NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_SA_CACHE_MAC_ADDR_HI_1                                                                      0x040398UL //Access:RW   DataWidth:0x10   // NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_SA_CACHE_MAC_ADDR_LO_2                                                                      0x04039cUL //Access:RW   DataWidth:0x20   // NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_SA_CACHE_MAC_ADDR_HI_2                                                                      0x0403a0UL //Access:RW   DataWidth:0x10   // NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_SA_CACHE_MAC_ADDR_LO_3                                                                      0x0403a4UL //Access:RW   DataWidth:0x20   // NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_SA_CACHE_MAC_ADDR_HI_3                                                                      0x0403a8UL //Access:RW   DataWidth:0x10   // NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_SA_CACHE_MAC_ADDR_LO_4                                                                      0x0403acUL //Access:RW   DataWidth:0x20   // NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_SA_CACHE_MAC_ADDR_HI_4                                                                      0x0403b0UL //Access:RW   DataWidth:0x10   // NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_SA_CACHE_MAC_ADDR_LO_5                                                                      0x0403b4UL //Access:RW   DataWidth:0x20   // NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_SA_CACHE_MAC_ADDR_HI_5                                                                      0x0403b8UL //Access:RW   DataWidth:0x10   // NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_SA_CACHE_MAC_ADDR_LO_6                                                                      0x0403bcUL //Access:RW   DataWidth:0x20   // NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_SA_CACHE_MAC_ADDR_HI_6                                                                      0x0403c0UL //Access:RW   DataWidth:0x10   // NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_SA_CACHE_MAC_ADDR_LO_7                                                                      0x0403c4UL //Access:RW   DataWidth:0x20   // NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [31:0] of the MAC Address[47:0]
+#define NCSI_REG_SA_CACHE_MAC_ADDR_HI_7                                                                      0x0403c8UL //Access:RW   DataWidth:0x10   // NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [47:32] of the MAC Address[47:0]
+#define NCSI_REG_SA_CACHE_DEST_HOST_FUNC_0                                                                   0x0403ccUL //Access:RW   DataWidth:0x2    // This is a debug only register. it captures which of the four channels in the host, the MAC address was learnt from. Note: This will be only 0 or 1. The only reliable value is 1.  If the value is 0, the channel could have been 0, 2 or 3.
+#define NCSI_REG_SA_CACHE_DEST_HOST_FUNC_1                                                                   0x0403d0UL //Access:RW   DataWidth:0x2    // This is a debug only register. it captures which of the four channels in the host, the MAC address was learnt from. Note: This will be only 0 or 1. The only reliable value is 1.  If the value is 0, the channel could have been 0, 2 or 3.
+#define NCSI_REG_SA_CACHE_DEST_HOST_FUNC_2                                                                   0x0403d4UL //Access:RW   DataWidth:0x2    // This is a debug only register. it captures which of the four channels in the host, the MAC address was learnt from. Note: This will be only 0 or 1. The only reliable value is 1.  If the value is 0, the channel could have been 0, 2 or 3.
+#define NCSI_REG_SA_CACHE_DEST_HOST_FUNC_3                                                                   0x0403d8UL //Access:RW   DataWidth:0x2    // This is a debug only register. it captures which of the four channels in the host, the MAC address was learnt from. Note: This will be only 0 or 1. The only reliable value is 1.  If the value is 0, the channel could have been 0, 2 or 3.
+#define NCSI_REG_SA_CACHE_DEST_HOST_FUNC_4                                                                   0x0403dcUL //Access:RW   DataWidth:0x2    // This is a debug only register. it captures which of the four channels in the host, the MAC address was learnt from. Note: This will be only 0 or 1. The only reliable value is 1.  If the value is 0, the channel could have been 0, 2 or 3.
+#define NCSI_REG_SA_CACHE_DEST_HOST_FUNC_5                                                                   0x0403e0UL //Access:RW   DataWidth:0x2    // This is a debug only register. it captures which of the four channels in the host, the MAC address was learnt from. Note: This will be only 0 or 1. The only reliable value is 1.  If the value is 0, the channel could have been 0, 2 or 3.
+#define NCSI_REG_SA_CACHE_DEST_HOST_FUNC_6                                                                   0x0403e4UL //Access:RW   DataWidth:0x2    // This is a debug only register. it captures which of the four channels in the host, the MAC address was learnt from. Note: This will be only 0 or 1. The only reliable value is 1.  If the value is 0, the channel could have been 0, 2 or 3.
+#define NCSI_REG_SA_CACHE_DEST_HOST_FUNC_7                                                                   0x0403e8UL //Access:RW   DataWidth:0x2    // This is a debug only register. it captures which of the four channels in the host, the MAC address was learnt from. Note: This will be only 0 or 1. The only reliable value is 1.  If the value is 0, the channel could have been 0, 2 or 3.
+#define NCSI_REG_SA_CACHE_VLAN_ID_0                                                                          0x0403ecUL //Access:RW   DataWidth:0xc    // This is the VLAN ID associated with the MAC address of the corresponding Learning cache.
+#define NCSI_REG_SA_CACHE_VLAN_ID_1                                                                          0x0403f0UL //Access:RW   DataWidth:0xc    // This is the VLAN ID associated with the MAC address of the corresponding Learning cache.
+#define NCSI_REG_SA_CACHE_VLAN_ID_2                                                                          0x0403f4UL //Access:RW   DataWidth:0xc    // This is the VLAN ID associated with the MAC address of the corresponding Learning cache.
+#define NCSI_REG_SA_CACHE_VLAN_ID_3                                                                          0x0403f8UL //Access:RW   DataWidth:0xc    // This is the VLAN ID associated with the MAC address of the corresponding Learning cache.
+#define NCSI_REG_SA_CACHE_VLAN_ID_4                                                                          0x0403fcUL //Access:RW   DataWidth:0xc    // This is the VLAN ID associated with the MAC address of the corresponding Learning cache.
+#define NCSI_REG_SA_CACHE_VLAN_ID_5                                                                          0x040400UL //Access:RW   DataWidth:0xc    // This is the VLAN ID associated with the MAC address of the corresponding Learning cache.
+#define NCSI_REG_SA_CACHE_VLAN_ID_6                                                                          0x040404UL //Access:RW   DataWidth:0xc    // This is the VLAN ID associated with the MAC address of the corresponding Learning cache.
+#define NCSI_REG_SA_CACHE_VLAN_ID_7                                                                          0x040408UL //Access:RW   DataWidth:0xc    // This is the VLAN ID associated with the MAC address of the corresponding Learning cache.
+#define NCSI_REG_SA_CACHE_AGING_THRESHOLD                                                                    0x04040cUL //Access:RW   DataWidth:0x20   // Provides Aging threshold of Source Address Learning cache entries in seconds. When an entry is written to the cache, a timer is loaded with the aging threshold. When the timer expires, the entry can be replaced. The resolution of the aging timer is 1ms
+#define NCSI_REG_SA_CACHE_CLR                                                                                0x040410UL //Access:RW   DataWidth:0x1    // When this bit is set, all the entries in the cache will be cleared.
+#define NCSI_REG_TAG_RM_CONFIG                                                                               0x040414UL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define NCSI_REG_TAG_RM_CONFIG_PROP_HEADER_RM                                                              (0x1<<0) // Setting this bit to "1" will result in removing proprietary headers from all packets.
+  #define NCSI_REG_TAG_RM_CONFIG_PROP_HEADER_RM_SHIFT                                                        0
+  #define NCSI_REG_TAG_RM_CONFIG_PER_TAG_RM                                                                  (0x3f<<1) // NCSI block has the capability to remove up-to six TAGs present in a packet. This field sets which of the TAGs need to be removed. This field works in conjuction with the TAG_EXIST field in the SOP descriptor. When a TAG exists in the packet and the corresponding bit is set, the TAG is removed.
+  #define NCSI_REG_TAG_RM_CONFIG_PER_TAG_RM_SHIFT                                                            1
+  #define NCSI_REG_TAG_RM_CONFIG_INNER_VLAN_RM                                                               (0x3<<7) // This bits are used to configure how the inner vlan tag needs to be handled. Inner VLAN is always the 2nd tag in a packet. 2'b00 -> Use the configuration bit associated with the Inner VLAN tag to decide whether to remove the tag or not. If the bit is 1, then remove the tag. 2'b01 -> Do not strip the inner VLAN Tag. Pass it on to BMC 2'b10 -> Always remove the inner VLAN Tag regardless of the configuration bit before sending the packet to BMC. 2'b11 -> Conditional Strip VLAN. If the inner VLAN in the packet is equal to a programmable management inner VLAN then remove the VLAN, else leave it in.
+  #define NCSI_REG_TAG_RM_CONFIG_INNER_VLAN_RM_SHIFT                                                         7
+#define NCSI_REG_TAG_RM_PROP_HEADER_LEN                                                                      0x040418UL //Access:RW   DataWidth:0x5    // This register indicates the size of the proprietary header at the beginning of the packet. The Tag removal logic will use this length to remove this header from the packet before sending it out to BMC. it is expected that once a non-zero value is set, all packets destined to BMC will have the proprietary header.
+#define NCSI_REG_TAG_LEN_0                                                                                   0x04041cUL //Access:RW   DataWidth:0x3    // The length of the info field for L2 tag 0.  The length is between 2B and 14B; in 2B granularity.
+#define NCSI_REG_TAG_LEN_1                                                                                   0x040420UL //Access:RW   DataWidth:0x3    // The length of the info field for L2 tag 1.  The length is between 2B and 14B; in 2B granularity.
+#define NCSI_REG_TAG_LEN_2                                                                                   0x040424UL //Access:RW   DataWidth:0x3    // The length of the info field for L2 tag 2.  The length is between 2B and 14B; in 2B granularity.
+#define NCSI_REG_TAG_LEN_3                                                                                   0x040428UL //Access:RW   DataWidth:0x3    // The length of the info field for L2 tag 3.  The length is between 2B and 14B; in 2B granularity.
+#define NCSI_REG_TAG_LEN_4                                                                                   0x04042cUL //Access:RW   DataWidth:0x3    // The length of the info field for L2 tag 4.  The length is between 2B and 14B; in 2B granularity.
+#define NCSI_REG_TAG_LEN_5                                                                                   0x040430UL //Access:RW   DataWidth:0x3    // The length of the info field for L2 tag 5.  The length is between 2B and 14B; in 2B granularity.
+#define NCSI_REG_TAG_INS_CONFIG                                                                              0x040434UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define NCSI_REG_TAG_INS_CONFIG_INSERT_PROP_HEADER                                                         (0x1<<0) // Tells HW to set the INS_PROP_HEADER flag in the SOP descriptor for a BMC to Network packet
+  #define NCSI_REG_TAG_INS_CONFIG_INSERT_PROP_HEADER_SHIFT                                                   0
+  #define NCSI_REG_TAG_INS_CONFIG_INSERT_OUTER_TAG                                                           (0x1<<1) // Tells HW to set the INS_OUTER_TAG flag in the SOP descriptor for a BMC to Network packet
+  #define NCSI_REG_TAG_INS_CONFIG_INSERT_OUTER_TAG_SHIFT                                                     1
+  #define NCSI_REG_TAG_INS_CONFIG_FORCE_INNER_VLAN                                                           (0x1<<2) // Tells HW to set the OVRRIDE_INNER_VLAN flag in the SOP descriptor for a BMC to Network packet if there is a VLAN header in the packet and VLAN ID is non-zero
+  #define NCSI_REG_TAG_INS_CONFIG_FORCE_INNER_VLAN_SHIFT                                                     2
+  #define NCSI_REG_TAG_INS_CONFIG_FORCE_INNER_VLAN_IF_NO_VLAN                                                (0x1<<3) // Tells HW to set the OVRRIDE_INNER_VLAN flag in the SOP descriptor for a BMC to Network packet if there is a VLAN header in the packet and VLAN ID is zero or Set the INS_INNER_VLAN flag if there is no VLAN header in the packet. In this case even the priority is inserted
+  #define NCSI_REG_TAG_INS_CONFIG_FORCE_INNER_VLAN_IF_NO_VLAN_SHIFT                                          3
+  #define NCSI_REG_TAG_INS_CONFIG_FORCE_PRIORITY                                                             (0x1<<4) // Tells HW to set the OVRRIDE_PRIORITY flag in the SOP descriptor for a BMC to Network packet if there is a VLAN header in the packet
+  #define NCSI_REG_TAG_INS_CONFIG_FORCE_PRIORITY_SHIFT                                                       4
+#define NCSI_REG_SIDEBAND_ARB                                                                                0x040438UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define NCSI_REG_SIDEBAND_ARB_ARB_NCSI_ID                                                                  (0x7<<0) // This field is used to set the ID of the current NCSI port. NCSI port with the lowest ID value is the master of the HW based arbitration.
+  #define NCSI_REG_SIDEBAND_ARB_ARB_NCSI_ID_SHIFT                                                            0
+  #define NCSI_REG_SIDEBAND_ARB_UNUSED0                                                                      (0x1<<3) // Unused
+  #define NCSI_REG_SIDEBAND_ARB_UNUSED0_SHIFT                                                                3
+  #define NCSI_REG_SIDEBAND_ARB_ARB_DISABLE                                                                  (0x1<<4) // Setting this field to '1' causes the hardware arbitration scheme to be disabled. This bit should be set when there is only one NCSI port on the board and tokens need not be passed out.
+  #define NCSI_REG_SIDEBAND_ARB_ARB_DISABLE_SHIFT                                                            4
+  #define NCSI_REG_SIDEBAND_ARB_ARB_START                                                                    (0x1<<5) // Setting this field to '1' causes the hardware arbitration scheme to begin. Any NCSI port can re-start the arbitration.
+  #define NCSI_REG_SIDEBAND_ARB_ARB_START_SHIFT                                                              5
+  #define NCSI_REG_SIDEBAND_ARB_ARB_BYPASS                                                                   (0x1<<6) // Setting this field to '1' the HW arbitration logic to function in bypass mode. This allows NCSI ports that don't have the firmware running to be automatically bypassed. Firmware should also set this bit when there is nothing to send. This will reduce the latency of the token around the loop.
+  #define NCSI_REG_SIDEBAND_ARB_ARB_BYPASS_SHIFT                                                             6
+  #define NCSI_REG_SIDEBAND_ARB_ARB_AUTO_BYPASS                                                              (0x1<<7) // Setting this field to '1' causes the NCSI port to cut latency when forwarding a token.
+  #define NCSI_REG_SIDEBAND_ARB_ARB_AUTO_BYPASS_SHIFT                                                        7
+  #define NCSI_REG_SIDEBAND_ARB_ARB_TOKEN_IPG                                                                (0x1f<<8) // This field is a programmable inter-packet gap for when the token is sent out.
+  #define NCSI_REG_SIDEBAND_ARB_ARB_TOKEN_IPG_SHIFT                                                          8
+  #define NCSI_REG_SIDEBAND_ARB_UNUSED1                                                                      (0x1<<13) // unused
+  #define NCSI_REG_SIDEBAND_ARB_UNUSED1_SHIFT                                                                13
+  #define NCSI_REG_SIDEBAND_ARB_ARB_FC_DISABLE                                                               (0x1<<14) // Setting this bit disables the feature to send XOFF/XON ordered sets on the arbiter interface. This feature is enabled by default and allows a NCSI port that wants to send a XOFF/XON frame to use the sideband interface to accelerate sending the command on the MII bus. This helps reducing the size of the Rx FIFO needed when multiple NCSI ports are connected to the BMC.
+  #define NCSI_REG_SIDEBAND_ARB_ARB_FC_DISABLE_SHIFT                                                         14
+  #define NCSI_REG_SIDEBAND_ARB_ARB_UPDATE                                                                   (0x1<<15) // Toggle this bit to update this register. Write "1" and then write "0".
+  #define NCSI_REG_SIDEBAND_ARB_ARB_UPDATE_SHIFT                                                             15
+  #define NCSI_REG_SIDEBAND_ARB_ARB_TIMEOUT                                                                  (0xffff<<16) // This field indicates the value in number of Ingress clock cycles that the arbitration master will wait before re-starting the arbitration process.
+  #define NCSI_REG_SIDEBAND_ARB_ARB_TIMEOUT_SHIFT                                                            16
+#define NCSI_REG_ARB_TOKEN_VALID                                                                             0x04043cUL //Access:R    DataWidth:0x1    // This bit indicates if the arbiter has a valid token.
+#define NCSI_REG_NCSI_PKGID                                                                                  0x040440UL //Access:R    DataWidth:0x2    // These bits indicate the Package ID of the chip as programmed at the I/Os.
+#define NCSI_REG_NCSI_RESET                                                                                  0x040444UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define NCSI_REG_NCSI_RESET_EGRESS_RESET                                                                   (0x1<<0) // Setting this bit will create an asychronous reset to the egress logic. Should be used only incase where the logic is stuck
+  #define NCSI_REG_NCSI_RESET_EGRESS_RESET_SHIFT                                                             0
+  #define NCSI_REG_NCSI_RESET_INGRESS_RESET                                                                  (0x1<<1) // Setting this bit will create an asychronous reset to the ingress logic. Should be used only incase where the logic is stuck
+  #define NCSI_REG_NCSI_RESET_INGRESS_RESET_SHIFT                                                            1
+#define NCSI_REG_STAT_NUM_PACKETS_TO_NETWORK_RO                                                              0x040448UL //Access:R    DataWidth:0x20   // Event Counter: Counts the number of packets sent to Network
+#define NCSI_REG_STAT_NUM_PACKETS_TO_HOST_RO                                                                 0x04044cUL //Access:R    DataWidth:0x20   // Event Counter: Counts the number of packets sent to Host
+#define NCSI_REG_STAT_NUM_PACKETS_TO_MCP_RO                                                                  0x040450UL //Access:R    DataWidth:0x20   // Event Counter: Counts the number of packets sent to mcp
+#define NCSI_REG_STAT_PKT_DROP_SA_MISMATCH_RO                                                                0x040454UL //Access:R    DataWidth:0x20   // Event Counter: Counts the number of packets that were dropped due to source Address mismatch.
+#define NCSI_REG_STAT_PKT_DROP_BMB_FULL_RO                                                                   0x040458UL //Access:R    DataWidth:0x20   // Event Counter: Counts the number of packets that were dropped due to BMB full.
+#define NCSI_REG_STAT_NUM_PACKETS_TO_NETWORK                                                                 0x04045cUL //Access:RC   DataWidth:0x20   // Event Counter: Counts the number of packets sent to Network
+#define NCSI_REG_STAT_NUM_PACKETS_TO_HOST                                                                    0x040460UL //Access:RC   DataWidth:0x20   // Event Counter: Counts the number of packets sent to Host
+#define NCSI_REG_STAT_NUM_PACKETS_TO_MCP                                                                     0x040464UL //Access:RC   DataWidth:0x20   // Event Counter: Counts the number of packets sent to mcp
+#define NCSI_REG_STAT_PKT_DROP_SA_MISMATCH                                                                   0x040468UL //Access:RC   DataWidth:0x20   // Event Counter: Counts the number of packets that were dropped due to source Address mismatch.
+#define NCSI_REG_STAT_PKT_DROP_BMB_FULL                                                                      0x04046cUL //Access:RC   DataWidth:0x20   // Event Counter: Counts the number of packets that were dropped due to BMB full.
+#define NCSI_REG_INGRESS_FIFO_ALMOST_FULL_THRES                                                              0x040470UL //Access:RW   DataWidth:0x6    // This register sets the number for 16byte words need to be accumulated before starting a transfer to the BMC. this register is provided to prevent any underrun that can happen if BMB is too slow to send data to the NCSI module as the data transfer to NCSI has started. Setting a value of all 1s in this register will guarantee a store-and-forward operation. Normally this register needs not be programmed and the default value should suffice.
+#define NCSI_REG_DBG_SELECT                                                                                  0x040474UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define NCSI_REG_DBG_DWORD_ENABLE                                                                            0x040478UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define NCSI_REG_DBG_SHIFT                                                                                   0x04047cUL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define NCSI_REG_DBG_FORCE_VALID                                                                             0x040480UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define NCSI_REG_DBG_FORCE_FRAME                                                                             0x040484UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define NCSI_REG_DBG_OUT_DATA                                                                                0x0404a0UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define NCSI_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define NCSI_REG_DBG_OUT_VALID                                                                               0x0404c0UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define NCSI_REG_DBG_OUT_FRAME                                                                               0x0404c4UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define NCSI_REG_ECO_RESERVED                                                                                0x0404c8UL //Access:RW   DataWidth:0x8    // Reserved for future ECOs
+#define NCSI_REG_INT_STS_0                                                                                   0x0404ccUL //Access:R    DataWidth:0x1    // Multi Field Register.
+  #define NCSI_REG_INT_STS_0_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define NCSI_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                             0
+#define NCSI_REG_INT_MASK_0                                                                                  0x0404d0UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define NCSI_REG_INT_MASK_0_ADDRESS_ERROR                                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: NCSI_REG_INT_STS_0.ADDRESS_ERROR .
+  #define NCSI_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                            0
+#define NCSI_REG_INT_STS_WR_0                                                                                0x0404d4UL //Access:WR   DataWidth:0x1    // Multi Field Register.
+  #define NCSI_REG_INT_STS_WR_0_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define NCSI_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                          0
+#define NCSI_REG_INT_STS_CLR_0                                                                               0x0404d8UL //Access:RC   DataWidth:0x1    // Multi Field Register.
+  #define NCSI_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                               (0x1<<0) // Signals an unknown address to the rf module.
+  #define NCSI_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                         0
+#define GRC_REG_OVERRIDE_WINDOW_MEM_SELF_INIT_START                                                          0x050000UL //Access:RW   DataWidth:0x1    // Reset the protection override window memory. When set to 1, protection override window memory self init starts.
+#define GRC_REG_OVERRIDE_WINDOW_MEM_SELF_INIT_DONE                                                           0x050004UL //Access:R    DataWidth:0x1    // When = 1, the self init for the protection override window memory is done.
+#define GRC_REG_RSV_ATTN_ACCESS_DATA_0                                                                       0x050040UL //Access:R    DataWidth:0x1c   // Holds the data regarding the last access that caused reserved address interrupt. Bits [22:0]:  Address (4 bytes resolution). Bits [23]:    Wr/rd. If = 1 it is write, If = 0 it is read. Bits [27:24]: Master. The decoding: 1 = pxp. 2 = mcp. 3 = msdm. 4 = psdm. 5 = ysdm. 6 = usdm. 7 = tsdm. 8 = xsdm. 9 = dbu. 10 = dmae.
+#define GRC_REG_RSV_ATTN_ACCESS_DATA_1                                                                       0x050044UL //Access:R    DataWidth:0x13   // Holds the data regarding the last access that caused reserved address interrupt. Bits [3:0]: PF. Bits [11:4]: VF. Bit  [13:12]: Port. Bits [15:14]: Privilege. The decoding: 0 - VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s) 2 - HV: HyperVisor (Assigned to HV). 3 - UN: Un-restricted Access. Bits [18:16]: Protection. Contains the value set by the master. The decoding: 3 - 0: Takes the default protection defined by the slave RF block. 4: Over-ride the target slave address attribute to VN PROTECTION. 5: Over-ride the target slave address attribute to VM PROTECTION. 6: Over-ride the target slave address attribute to HV PROTECTION. 7: Over-ride the target slave address attribute to UA PROTECTION.
+#define GRC_REG_RSV_ATTN_ACCESS_VALID                                                                        0x050048UL //Access:RW   DataWidth:0x1    // When asserted, = 1, indicates that the rsv_attn_access_data_0 and rsv_attn_access_data_1 registers contain valid data. While asserted these registers will not latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.
+#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0                                                                   0x05004cUL //Access:R    DataWidth:0x1c   // Holds the data regarding the last access that caused timeout interrupt. Bits [22:0]:  Address (4 bytes resolution). Bit  [23]:    Wr/rd. If = 1 it is write, if = 0 it is read. Bits [27:24]: Master. The decoding: 1 = pxp. 2 = mcp. 3 = msdm. 4 = psdm. 5 = ysdm. 6 = usdm. 7 = tsdm. 8 = xsdm. 9 = dbu. 10 = dmae.
+#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1                                                                   0x050050UL //Access:R    DataWidth:0x13   // Holds the data regarding the last access that caused timeout interrupt. Bits [3:0]: PF. Bits [11:4]: VF. Bit  [13:12]: Port. Bits [15:14]: Privilege. The decoding: 0 - VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s) 2 - HV: HyperVisor (Assigned to HV). 3 - UN: Un-restricted Access. Bits [18:16]: Protection. Contains the value set by the master. The decoding: 3 - 0: Takes the default protection defined by the slave RF block. 4: Over-ride the target slave address attribute to VN PROTECTION. 5: Over-ride the target slave address attribute to VM PROTECTION. 6: Over-ride the target slave address attribute to HV PROTECTION. 7: Over-ride the target slave address attribute to UA PROTECTION.
+#define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID                                                                    0x050054UL //Access:RW   DataWidth:0x1    // When asserted, = 1, indicates that the timeout_attn_access_data_0 and timeout_attn_access_data_1 registers contain valid data. While asserted these registers will not latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.
+#define GRC_REG_PATH_ISOLATION_ERROR_DATA_0                                                                  0x050058UL //Access:R    DataWidth:0x1c   // Holds the data regarding the last access that caused path isolation interrupt. Bits [22:0]:  Address (4 bytes resolution). Bit  [23]:    Wr/rd. If = 1 it is write, if = 0 it is read. Bits [27:24]: Master. The decoding: 1 = pxp. 2 = mcp. 3 = msdm. 4 = psdm. 5 = ysdm. 6 = usdm. 7 = tsdm. 8 = xsdm. 9 = dbu. 10 = dmae.
+#define GRC_REG_PATH_ISOLATION_ERROR_DATA_1                                                                  0x05005cUL //Access:R    DataWidth:0x13   // Holds the data regarding the last access that caused path isolation interrupt. Bits [3:0]: PF. Bits [11:4]: VF. Bit  [13:12]: Port. Bits [15:14]: Privilege. The decoding: 0 - VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s) 2 - HV: HyperVisor (Assigned to HV). 3 - UN: Un-restricted Access. Bits [18:16]: Protection. Contains the value set by the master. The decoding: 3 - 0: Takes the default protection defined by the slave RF block. 4: Over-ride the target slave address attribute to VN PROTECTION. 5: Over-ride the target slave address attribute to VM PROTECTION. 6: Over-ride the target slave address attribute to HV PROTECTION. 7: Over-ride the target slave address attribute to UA PROTECTION.
+#define GRC_REG_PATH_ISOLATION_ERROR_VALID                                                                   0x050060UL //Access:RW   DataWidth:0x1    // When asserted, = 1, indicates that the path_isolation_error_data_0 and path_isolation_error_data_1 registers contain valid data. While asserted these registers will not latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.
+#define GRC_REG_TRACE_FIFO_VALID_DATA                                                                        0x050064UL //Access:R    DataWidth:0x1    // If = 1, indicates that the trace FIFO contains at least one valid data.                           If = 0, indicates that the trace FIFO doeasn't contain any valid data.                          This register should be read before reading the GRC_REGISTERS_TRACE_FIFO,                           and only if the read value is 1, one read from the GRC_REGISTERS_TRACE_FIFO can be done.
+#define GRC_REG_TRACE_FIFO                                                                                   0x050068UL //Access:WB_R DataWidth:0x34   // Each row in the FIFO contains data regarding previous GRC rd/wr access. This FIFO conatins 32 rows. Before each read from this register, the register GRC_REGISTERS_TRACE_FIFO_VALID_DATA should be read, and only if the read value is 1, this FIFO has at least one valid data, and this register can be read once. The data: Bits [22:0]:  Address (4 bytes resolution). Bits [23]:    Wr/rd. If = 1 it is write, if = 0 it is read. Bits [27:24]: PF. Bits [35:28]: VF. Bit  [37:36]: Port. Bits [39:38]: Privilege. The decoding: 0 - VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s) 2 - HV: HyperVisor (Assigned to HV). 3 - UN: Un-restricted Access. Bits [42:40]: Protection. The decoding: 3 - 0: Takes the default protection defined by the slave RF block. 4: Over-ride the target slave address attribute to VN PROTECTION. 5: Over-ride the target slave address attribute to VM PROTECTION. 6: Over-ride the target slave address attribute to HV PROTECTION. 7: Over-ride the target slave address attribute to UA PROTECTION. Bits [46:43]: Master. The decoding: 1 = pxp. 2 = mcp. 3 = msdm. 4 = psdm. 5 = ysdm. 6 = usdm. 7 = tsdm. 8 = xsdm. 9 = dbu. 10 = dmae. Bits [51:47]: Error type. The decoding: 0 = no error (access to the slave block ended successfully). 1 = timeout event. 2 = Reserved address that is acknowledged by the GRC block due to address which doesn't belong to any block address domain. 4 = slave block access to reserved address error or write to read only register which is set by the slave block that the access was targeted for. 8 = slave block privilege (protection) error which is set by the slave block that the access was targeted for.        16 = path isolation error.
+#define GRC_REG_TRACE_FIFO_SIZE                                                                              2
+#define GRC_REG_TRACE_FIFO_ENABLE                                                                            0x050070UL //Access:RW   DataWidth:0x1    // If = 1, the trace fifo feature is enabled and write of GRC wr/rd accesses to the FIFO is done based on the different trace FIFO configurtaions.                          If = 0, the trace fifo feature is disabled and no writes are done to the FIFO.                          It is recommended to disable this feature before reading from the GRC_REGISTERS_TRACE_FIFO.
+#define GRC_REG_TRACE_FIFO_MASTERS_SEL                                                                       0x050074UL //Access:RW   DataWidth:0xa    // Selects the masters that their accesses are written to the trace FIFO. The range can be from one master to all masters, all combinations. If = 1, the master is enabled and its accesses are written to the trace FIFO. If = 0, the master is masked, and its accesses are not written to the trace FIFO. The fields: Bit [0]: pxp. Bit [1]: mcp. Bit [2]: msdm. Bit [3]: psdm. Bit [4]: ysdm. Bit [5]: usdm Bit [6]: tsdm. Bit [7]: xsdm. Bit [8]: dbu. Bit [9]: dmae.
+#define GRC_REG_TRACE_FIFO_ERROR_TYPE_SEL                                                                    0x050078UL //Access:RW   DataWidth:0x6    // Selects the accesses with error types that are written to the trace FIFO. The range can be all combinations. If = 1 the error is enabled, access with applicable error is written to the trace FIFO. If = 0 the error is masked, access with applicable error is not written to the trace FIFO. The fields: Bit [0]: no error. Bit [1]: timeout event. Bit [2]: GRC reserved address. Reserved address that is acknowledged by the GRC block due to address which doesnt belong to any block address domain. Bit [3]: slave block address error. Slave block address error (access to reserved address or write to read only register) which is set by the slave block that the access was targeted for. Bit [4]: slave block privilege (protection) error. Slave block privilege (protection) error which is set by the slave block that the access was targeted for. Bit [5]: path isolation error.
+#define GRC_REG_TRACE_FIFO_WR_RD_SEL                                                                         0x05007cUL //Access:RW   DataWidth:0x2    // Selects if wr/rd type accesses are written to the trace FIFO. One or both types can be enabled. If = 1 the wr/rd access is enabled, wr/rd access is written to the trace FIFO. If = 0 the wr/rd access is masked, wr/rd access is not written to the trace FIFO. The fields: Bit [0]: wr. Bit [1]: rd.
+#define GRC_REG_TRACE_FIFO_PF_SEL                                                                            0x050080UL //Access:RW   DataWidth:0x10   // Selects the PF for the accesses that are written to the trace FIFO. The range is from one PF to all PFs, all combinations. If = 1 the PF is enabled, access with the PF is written to the trace FIFO. If = 0 the PF is masked, access with the PF is not written to the trace FIFO. BB: only bits 0-7 are applicable. The fields: Bit [0]: PF #0. Bit [1]: PF #1.            Bit [2]: PF #2. Bit [3]: PF #3.  Bit [4]: PF #4. Bit [5]: PF #5.            Bit [6]: PF #6. Bit [7]: PF #7. Bit [8]: PF #8. Bit [9]: PF #9.            Bit [10]: PF #10. Bit [11]: PF #11. Bit [12]: PF #12. Bit [13]: PF #13.            Bit [14]: PF #14. Bit [15]: PF #15.
+#define GRC_REG_TRACE_FIFO_VF_SEL                                                                            0x050084UL //Access:RW   DataWidth:0x1    // If = 1, selects only the VF in GRC_REG_TRACE_FIFO_VF for the accesses that are written to the trace FIFO. If = 0, accesses with all VFs are written to the trace FIFO.
+#define GRC_REG_TRACE_FIFO_VF                                                                                0x050088UL //Access:RW   DataWidth:0x8    // The VF for the accesses that are written to the trace FIFO. Applicable only if GRC_REG_TRACE_FIFO_VF_SEL = 1. Value of all 1s is applicable and represents VF not valid. BB: only bits 0-6 are applicable.
+#define GRC_REG_TRACE_FIFO_PORT_SEL                                                                          0x05008cUL //Access:RW   DataWidth:0x4    // Selects the ports for the accesses that are written to the trace FIFO. The range is from one port to all ports, all combinations. If = 1 the port is enabled, access with the port is written to the trace FIFO. If = 0 the port is masked, access with the port is not written to the trace FIFO. BB: only bits 0-1 are applicable. The fields: Bit [0]: port #0. Bit [1]: port #1.            Bit [2]: port #2. Bit [3]: port #3.
+#define GRC_REG_TRACE_FIFO_PRIVILEGE_SEL                                                                     0x050090UL //Access:RW   DataWidth:0x4    // Selects the privilege for the accesses that are written to the trace FIFO. The range is from one privilege to all privileges, all combinations. If = 1 the privilege is enabled, access with the privilege is written to the trace FIFO. If = 0 the privilege is masked, access with the privilege is not written to the trace FIFO. The fields: Bit [0]: VN (0). Bit [1]: PDA (1).            Bit [2]: HV (2). Bit [3]: UA (3).
+#define GRC_REG_TRACE_FIFO_PRIVILEGE_OVERRIDE_SEL                                                            0x050094UL //Access:RW   DataWidth:0x8    // Selects the privilege override for the accesses that are written to the trace FIFO. The range is from one privilege override to all privilege overrides, all combinations. If = 1 the privilege override is enabled, access with the privilege override is written to the trace FIFO. If = 0 the privilege override is masked, access with the privilege overrideis not written to the trace FIFO. The fields: Bit [0]: PRV_DEFAULT. Takes the default protection defined by RF block. Bit [1]: PRV_DEFAULT. Takes the default protection defined by RF block.           Bit [2]: PRV_DEFAULT. Takes the default protection defined by RF block. Bit [3]: PRV_DEFAULT. Takes the default protection defined by RF block. Bit [4]: VN_OV. Over-ride to VN PROTECTION. Bit [5]: PDA_OV. Over-ride to PDA PROTECTION. Bit [6]: HV_OV. Over-ride to HV PROTECTION. Bit [7]: UA_OV. Over-ride to UA PROTECTION.
+#define GRC_REG_TRACE_FIFO_ADDRESS_SEL                                                                       0x050098UL //Access:RW   DataWidth:0x17   // Selects the address for the accesses that are written to the trace FIFO. Selects for each address bit if this bit is enforced. The register GRC_REG_TRACE_FIFO_ADDRESS selects the value for the address bit. This mechanism enables to select or a specific address, or a range of address by enforcing the msbits. In order to select all the addresses of a specific block, need to enforce its base address. In order to select all chip addresses, the required value for this regsiter is 0.
+#define GRC_REG_TRACE_FIFO_ADDRESS                                                                           0x05009cUL //Access:RW   DataWidth:0x17   // Selects the address for the accesses that are written to the trace FIFO. Selects the value for each address bit. The register GRC_REG_TRACE_FIFO_ADDRESS_SEL selects for each address bit if it is enforced the address bit. This mechanism enables to select or a specific address, or a range of address by enforcing the msbits. In order to select all the addresses of a specific block, need to enforce its base address.
+#define GRC_REG_TRACE_FIFO_MODE                                                                              0x0500a0UL //Access:RW   DataWidth:0x1    // Trace FIFO mode. If = 0, keeps the first 32 GRC accesses. When the FIFO is full new accesses are dropped. If = 1, keeps the last 32 GRC accesses. When the FIFO is full a new access overrides the first access.
+#define GRC_REG_DBG_SELECT                                                                                   0x0500a4UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define GRC_REG_DBG_DWORD_ENABLE                                                                             0x0500a8UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define GRC_REG_DBG_SHIFT                                                                                    0x0500acUL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define GRC_REG_DBG_FORCE_VALID                                                                              0x0500b0UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define GRC_REG_DBG_FORCE_FRAME                                                                              0x0500b4UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define GRC_REG_DBG_OUT_DATA                                                                                 0x0500c0UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define GRC_REG_DBG_OUT_DATA_SIZE                                                                            8
+#define GRC_REG_DBG_OUT_VALID                                                                                0x0500e0UL //Access:R    DataWidth:0x4    // Dbgmux output valid
+#define GRC_REG_DBG_OUT_FRAME                                                                                0x0500e4UL //Access:R    DataWidth:0x4    // Dbgmux output frame
+#define GRC_REG_DBGSYN_STATUS                                                                                0x0500e8UL //Access:R    DataWidth:0x5    // Fill level of dbgmux fifo.
+#define GRC_REG_DBGSYN_ALMOST_FULL_THR                                                                       0x0500ecUL //Access:RW   DataWidth:0x4    // Debug only: If more than this Number of entries are occupied in the dbgsyn clock synchronization FIFO, it does not enable writing to the fifo. This value is based on implementation and should not be changed.
+#define GRC_REG_INT_STS_0                                                                                    0x050180UL //Access:R    DataWidth:0x5    // Multi Field Register.
+  #define GRC_REG_INT_STS_0_ADDRESS_ERROR                                                                    (0x1<<0) // Signals an unknown address to the rf module.
+  #define GRC_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                              0
+  #define GRC_REG_INT_STS_0_TIMEOUT_EVENT                                                                    (0x1<<1) // Timeout event
+  #define GRC_REG_INT_STS_0_TIMEOUT_EVENT_SHIFT                                                              1
+  #define GRC_REG_INT_STS_0_GLOBAL_RESERVED_ADDRESS                                                          (0x1<<2) // Reserved address that is acknowledged by the GRC block due to address which doesnt belong to any block address domain.
+  #define GRC_REG_INT_STS_0_GLOBAL_RESERVED_ADDRESS_SHIFT                                                    2
+  #define GRC_REG_INT_STS_0_PATH_ISOLATION_ERROR                                                             (0x1<<3) // Path Isolation error.
+  #define GRC_REG_INT_STS_0_PATH_ISOLATION_ERROR_SHIFT                                                       3
+  #define GRC_REG_INT_STS_0_TRACE_FIFO_VALID_DATA_K2_E5                                                      (0x1<<4) // Trace FIFO contains at least one valid data (GRC rd/wr access).
+  #define GRC_REG_INT_STS_0_TRACE_FIFO_VALID_DATA_K2_E5_SHIFT                                                4
+#define GRC_REG_INT_MASK_0                                                                                   0x050184UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define GRC_REG_INT_MASK_0_ADDRESS_ERROR                                                                   (0x1<<0) // This bit masks, when set, the Interrupt bit: GRC_REG_INT_STS_0.ADDRESS_ERROR .
+  #define GRC_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                             0
+  #define GRC_REG_INT_MASK_0_TIMEOUT_EVENT                                                                   (0x1<<1) // This bit masks, when set, the Interrupt bit: GRC_REG_INT_STS_0.TIMEOUT_EVENT .
+  #define GRC_REG_INT_MASK_0_TIMEOUT_EVENT_SHIFT                                                             1
+  #define GRC_REG_INT_MASK_0_GLOBAL_RESERVED_ADDRESS                                                         (0x1<<2) // This bit masks, when set, the Interrupt bit: GRC_REG_INT_STS_0.GLOBAL_RESERVED_ADDRESS .
+  #define GRC_REG_INT_MASK_0_GLOBAL_RESERVED_ADDRESS_SHIFT                                                   2
+  #define GRC_REG_INT_MASK_0_PATH_ISOLATION_ERROR                                                            (0x1<<3) // This bit masks, when set, the Interrupt bit: GRC_REG_INT_STS_0.PATH_ISOLATION_ERROR .
+  #define GRC_REG_INT_MASK_0_PATH_ISOLATION_ERROR_SHIFT                                                      3
+  #define GRC_REG_INT_MASK_0_TRACE_FIFO_VALID_DATA_K2_E5                                                     (0x1<<4) // This bit masks, when set, the Interrupt bit: GRC_REG_INT_STS_0.TRACE_FIFO_VALID_DATA .
+  #define GRC_REG_INT_MASK_0_TRACE_FIFO_VALID_DATA_K2_E5_SHIFT                                               4
+#define GRC_REG_INT_STS_WR_0                                                                                 0x050188UL //Access:WR   DataWidth:0x5    // Multi Field Register.
+  #define GRC_REG_INT_STS_WR_0_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define GRC_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                           0
+  #define GRC_REG_INT_STS_WR_0_TIMEOUT_EVENT                                                                 (0x1<<1) // Timeout event
+  #define GRC_REG_INT_STS_WR_0_TIMEOUT_EVENT_SHIFT                                                           1
+  #define GRC_REG_INT_STS_WR_0_GLOBAL_RESERVED_ADDRESS                                                       (0x1<<2) // Reserved address that is acknowledged by the GRC block due to address which doesnt belong to any block address domain.
+  #define GRC_REG_INT_STS_WR_0_GLOBAL_RESERVED_ADDRESS_SHIFT                                                 2
+  #define GRC_REG_INT_STS_WR_0_PATH_ISOLATION_ERROR                                                          (0x1<<3) // Path Isolation error.
+  #define GRC_REG_INT_STS_WR_0_PATH_ISOLATION_ERROR_SHIFT                                                    3
+  #define GRC_REG_INT_STS_WR_0_TRACE_FIFO_VALID_DATA_K2_E5                                                   (0x1<<4) // Trace FIFO contains at least one valid data (GRC rd/wr access).
+  #define GRC_REG_INT_STS_WR_0_TRACE_FIFO_VALID_DATA_K2_E5_SHIFT                                             4
+#define GRC_REG_INT_STS_CLR_0                                                                                0x05018cUL //Access:RC   DataWidth:0x5    // Multi Field Register.
+  #define GRC_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define GRC_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                          0
+  #define GRC_REG_INT_STS_CLR_0_TIMEOUT_EVENT                                                                (0x1<<1) // Timeout event
+  #define GRC_REG_INT_STS_CLR_0_TIMEOUT_EVENT_SHIFT                                                          1
+  #define GRC_REG_INT_STS_CLR_0_GLOBAL_RESERVED_ADDRESS                                                      (0x1<<2) // Reserved address that is acknowledged by the GRC block due to address which doesnt belong to any block address domain.
+  #define GRC_REG_INT_STS_CLR_0_GLOBAL_RESERVED_ADDRESS_SHIFT                                                2
+  #define GRC_REG_INT_STS_CLR_0_PATH_ISOLATION_ERROR                                                         (0x1<<3) // Path Isolation error.
+  #define GRC_REG_INT_STS_CLR_0_PATH_ISOLATION_ERROR_SHIFT                                                   3
+  #define GRC_REG_INT_STS_CLR_0_TRACE_FIFO_VALID_DATA_K2_E5                                                  (0x1<<4) // Trace FIFO contains at least one valid data (GRC rd/wr access).
+  #define GRC_REG_INT_STS_CLR_0_TRACE_FIFO_VALID_DATA_K2_E5_SHIFT                                            4
+#define GRC_REG_PRTY_MASK_H_0                                                                                0x050204UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define GRC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                            (0x1<<0) // This bit masks, when set, the Parity bit: GRC_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define GRC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                                      0
+  #define GRC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                            (0x1<<1) // This bit masks, when set, the Parity bit: GRC_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define GRC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                                      1
+#define GRC_REG_MEM_ECC_EVENTS                                                                               0x050210UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define GRC_REG_TIMEOUT_VAL                                                                                  0x050400UL //Access:RW   DataWidth:0x20   // The count value for the timeout timer. The count is done in common main clock domain.
+#define GRC_REG_TIMEOUT_EN                                                                                   0x050404UL //Access:RW   DataWidth:0x1    // Setting this bit enables a timer in the GRC block to timeout any access that does not finish within GRC_REGISTERS_TIMOUT_VAL.TIMEOUT_VAL cycles. When this bit is cleared the timeout is disabled.
+#define GRC_REG_ECO_RESERVED                                                                                 0x050408UL //Access:RW   DataWidth:0x8    // For ECOs.
+#define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW                                                                 0x05040cUL //Access:RW   DataWidth:0x5    // Number of valid windows in the GRC_REG_PROTECTION_OVERRIDE_WINDOW memory. The number can be from 0 (no valid window) to 20 (20 valid windows). The valid windows should be consecutive. Each valid window can be applicable for rd access, wr access, or both.
+#define GRC_REG_PROTECTION_OVERRIDE_WINDOW                                                                   0x050500UL //Access:WB   DataWidth:0x37   // A protection override window that enables to override the protection levels of a range of GRC addresses. There are 20 windows. Each valid window can be applicable for rd access, wr access, or both. Each window contains the following fields: Bits [22:0]:  Base address 4 bytes resolution). The GRC address which the window starts at. Bits [46:23]: Window size. The size of the window in the GRC space (for a window of one address needs to write value of 0x1). Bit  [47]: Rd access. If = 1, the window is applicable for rd access. If = 0, the window is not applicable for rd access. Bit  [48]: Wr access. If = 1, the window is applicable for wr access. If = 1, the window is not applicable for wr access. Bits [51:49]: Protection value rd access. The new protection value assigned to the range in rd access (if Rd access = 1). Bits [54:52]: Protection value wr access. The new protection value assigned to the range in wr access (if Wr access = 1).
+#define GRC_REG_PROTECTION_OVERRIDE_WINDOW_SIZE                                                              40
+#define UMAC_REG_IPG_HD_BKP_CNTL                                                                             0x051004UL //Access:RW   DataWidth:0x8    // Programmable field representing the minimum number of bits of IFG to enforce between frames.  A frame whose IFG is less than that programmed is dropped.  The default setting is 0x50 (80d).
+#define UMAC_REG_COMMAND_CONFIG                                                                              0x051008UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define UMAC_REG_COMMAND_CONFIG_PORT_ENB_SYS_K2_E5                                                         (0x1<<0) // Enable/Disable MAC path for data packets.
+  #define UMAC_REG_COMMAND_CONFIG_PORT_ENB_SYS_K2_E5_SHIFT                                                   0
+  #define UMAC_REG_COMMAND_CONFIG_PORT_SPEED_K2_E5                                                           (0x7<<2) // Set MAC speed. used to set the core mode of operation: 000: Enable 10Mbps  Ethernet mode (SGMII) 001: Enable 100Mbps Ethernet mode (SGMII) 010: Enable Gigabit Ethernet mode (SGMII) 101: Enable RMII mode
+  #define UMAC_REG_COMMAND_CONFIG_PORT_SPEED_K2_E5_SHIFT                                                     2
+  #define UMAC_REG_COMMAND_CONFIG_PCRCE_K2_E5                                                                (0x1<<5) // globally pad frame, and append CRC.
+  #define UMAC_REG_COMMAND_CONFIG_PCRCE_K2_E5_SHIFT                                                          5
+  #define UMAC_REG_COMMAND_CONFIG_CRCE_K2_E5                                                                 (0x1<<6) // globally append CRC.
+  #define UMAC_REG_COMMAND_CONFIG_CRCE_K2_E5_SHIFT                                                           6
+  #define UMAC_REG_COMMAND_CONFIG_LOOPBACK_TX_K2_E5                                                          (0x1<<16) // Transmit packets to PHY while in MAC local loopback; when set to '1'; otherwise transmit to PHY is disabled (normal operation); when set to '0' (Reset value).
+  #define UMAC_REG_COMMAND_CONFIG_LOOPBACK_TX_K2_E5_SHIFT                                                    16
+  #define UMAC_REG_COMMAND_CONFIG_LOOPBACK_RX_K2_E5                                                          (0x1<<19) // When set, frames received by the PHY are transmitted. Received packet by the PHY are Transmitted by the PHY (remote  loopback); when set to '1'; otherwise transmit to PHY is disabled (normal operation); when set to '0' (Reset value).
+  #define UMAC_REG_COMMAND_CONFIG_LOOPBACK_RX_K2_E5_SHIFT                                                    19
+  #define UMAC_REG_COMMAND_CONFIG_TX_ENA_BB                                                                  (0x1<<0) // Enable/Disable MAC transmit path for data packets & pause/pfc packets sent in the normal data path. Pause/pfc packets generated internally are allowed if ignore_tx_pause is not set. When set to '0' (Reset value); the MAC transmit function is disable. When set to '1'; the MAC transmit function is enabled.
+  #define UMAC_REG_COMMAND_CONFIG_TX_ENA_BB_SHIFT                                                            0
+  #define UMAC_REG_COMMAND_CONFIG_RX_ENA_BB                                                                  (0x1<<1) // Enable/Disable MAC receive path. When set to '0' (Reset value); the MAC receive function is disable. When set to '1'; the MAC receive function is enabled.
+  #define UMAC_REG_COMMAND_CONFIG_RX_ENA_BB_SHIFT                                                            1
+  #define UMAC_REG_COMMAND_CONFIG_ETH_SPEED_BB                                                               (0x3<<2) // Set MAC speed. Ignored when the register bit ENA_EXT_CONFIG is set to '1'. When the Register bit ENA_EXT_CONFIG is set to '0'; used to set the core mode of operation: 00: Enable 10Mbps Ethernet mode 01: Enable 100Mbps Ethernet mode 10: Enable Gigabit Ethernet mode 11: Enable 2.5Gigabit Ethernet mode.
+  #define UMAC_REG_COMMAND_CONFIG_ETH_SPEED_BB_SHIFT                                                         2
+  #define UMAC_REG_COMMAND_CONFIG_PROMIS_EN_BB                                                               (0x1<<4) // Enable/Disable MAC promiscuous operation. When asserted (Set to '1'); all frames are received without Unicast address filtering.
+  #define UMAC_REG_COMMAND_CONFIG_PROMIS_EN_BB_SHIFT                                                         4
+  #define UMAC_REG_COMMAND_CONFIG_PAD_EN_BB                                                                  (0x1<<5) // Enable/Disable Frame Padding. If enabled (Set to '1'); then padding is removed from the received frame before it is transmitted to the user application. If disabled (set to reset value '0'); then no padding is removed on receive by the MAC. This bit has no effect on Tx padding and hence Transmit always pad runts to guarantee a minimum frame size of 64 octets.
+  #define UMAC_REG_COMMAND_CONFIG_PAD_EN_BB_SHIFT                                                            5
+  #define UMAC_REG_COMMAND_CONFIG_CRC_FWD_BB                                                                 (0x1<<6) // Terminate/Forward Received CRC. If enabled (1) the CRC field of received frames are transmitted to the user application. If disabled (Set to reset value '0') the CRC field is stripped from the frame. Note: If padding function (Bit PAD_EN set to '1') is enabled. CRC_FWD is ignored and the CRC field is checked and always terminated and removed.
+  #define UMAC_REG_COMMAND_CONFIG_CRC_FWD_BB_SHIFT                                                           6
+  #define UMAC_REG_COMMAND_CONFIG_PAUSE_FWD_BB                                                               (0x1<<7) // Terminate/Forward Pause Frames. If enabled (Set to '1') pause frames are forwarded to the user application. If disabled (Set to reset value '0'); pause frames are terminated and discarded in the MAC.
+  #define UMAC_REG_COMMAND_CONFIG_PAUSE_FWD_BB_SHIFT                                                         7
+  #define UMAC_REG_COMMAND_CONFIG_PAUSE_IGNORE_BB                                                            (0x1<<8) // Ignore Pause Frame Quanta. If enabled (Set to '1') received pause frames are ignored by the MAC. When disabled (Set to reset value '0') the transmit process is stopped for the amount of time specified in the pause quanta received within the pause frame.
+  #define UMAC_REG_COMMAND_CONFIG_PAUSE_IGNORE_BB_SHIFT                                                      8
+  #define UMAC_REG_COMMAND_CONFIG_TX_ADDR_INS_BB                                                             (0x1<<9) // Set MAC address on transmit. If enabled (Set to '1') the MAC overwrites the source MAC address with the programmed MAC address in registers MAC_0 and MAC_1. If disabled (Set to reset value '0'); the source MAC address received from the transmit application transmitted is not modified by the MAC.
+  #define UMAC_REG_COMMAND_CONFIG_TX_ADDR_INS_BB_SHIFT                                                       9
+  #define UMAC_REG_COMMAND_CONFIG_HD_ENA_BB                                                                  (0x1<<10) // Half duplex enable. When set to '1'; enables half duplex mode; when set to '0'; the MAC operates in full duplex mode. Ignored at ethernet speeds 1G/2.5G or when the register ENA_EXT_CONFIG is set to '1'.
+  #define UMAC_REG_COMMAND_CONFIG_HD_ENA_BB_SHIFT                                                            10
+  #define UMAC_REG_COMMAND_CONFIG_RX_LOW_LATENCY_EN_BB                                                       (0x1<<11) // This works only when runt filter is disabled. It reduces the receive latency by 48 MAC clock time.
+  #define UMAC_REG_COMMAND_CONFIG_RX_LOW_LATENCY_EN_BB_SHIFT                                                 11
+  #define UMAC_REG_COMMAND_CONFIG_OVERFLOW_EN_BB                                                             (0x1<<12) // If set; enables Rx FIFO overflow logic. In this case; the RXFIFO_STAT[1] register bit is not operational (always set to 0). If cleared; disables RX FIFO overflow logic. In this case; the RXFIFO_STAT[1] register bit is operational (Sticky set when overrun occurs; clearable only by SW_Reset).
+  #define UMAC_REG_COMMAND_CONFIG_OVERFLOW_EN_BB_SHIFT                                                       12
+  #define UMAC_REG_COMMAND_CONFIG_SW_RESET_BB                                                                (0x1<<13) // Software Reset Command. When asserted; the TX and RX are disabled. Config registers are not affected by sw reset. Write a 0 to de-assert the sw reset.
+  #define UMAC_REG_COMMAND_CONFIG_SW_RESET_BB_SHIFT                                                          13
+  #define UMAC_REG_COMMAND_CONFIG_FCS_CORRUPT_URUN_EN_BB                                                     (0x1<<14) // Corrupt Tx FCS; on underrun; when set to '1'; No FCS corruption when set to '0' (Reset value).
+  #define UMAC_REG_COMMAND_CONFIG_FCS_CORRUPT_URUN_EN_BB_SHIFT                                               14
+  #define UMAC_REG_COMMAND_CONFIG_LOOP_ENA_BB                                                                (0x1<<15) // Enable GMII/MII loopback when set to '1'; normal operation when set to '0' (Reset value).
+  #define UMAC_REG_COMMAND_CONFIG_LOOP_ENA_BB_SHIFT                                                          15
+  #define UMAC_REG_COMMAND_CONFIG_MAC_LOOP_CON_BB                                                            (0x1<<16) // Transmit packets to PHY while in MAC local loopback; when set to '1'; otherwise transmit to PHY is disabled (normal operation); when set to '0' (Reset value).
+  #define UMAC_REG_COMMAND_CONFIG_MAC_LOOP_CON_BB_SHIFT                                                      16
+  #define UMAC_REG_COMMAND_CONFIG_SW_OVERRIDE_TX_BB                                                          (0x1<<17) // If set; enables the SW programmed Tx pause capability config bits to overwrite the auto negotiated Tx pause capabilities when ena_ext_config (autoconfig) is set. If cleared; and when ena_ext_config (autoconfig) is set; then SW programmed Tx pause capability config bits has no effect over auto negotiated capabilities.
+  #define UMAC_REG_COMMAND_CONFIG_SW_OVERRIDE_TX_BB_SHIFT                                                    17
+  #define UMAC_REG_COMMAND_CONFIG_SW_OVERRIDE_RX_BB                                                          (0x1<<18) // If set; enables the SW programmed Rx pause capability config bits to overwrite the auto negotiated Rx pause capabilities when ena_ext_config (autoconfig) is set. If cleared; and when ena_ext_config (autoconfig) is set; then SW programmed Rx pause capability config bits has no effect over auto negotiated capabilities.
+  #define UMAC_REG_COMMAND_CONFIG_SW_OVERRIDE_RX_BB_SHIFT                                                    18
+  #define UMAC_REG_COMMAND_CONFIG_EN_INTERNAL_TX_CRS_BB                                                      (0x1<<21) // If enabled; then CRS input to Unimac is ORed with tds[8] (tx data valid output). This is helpful when TX CRS is disabled inside PHY.
+  #define UMAC_REG_COMMAND_CONFIG_EN_INTERNAL_TX_CRS_BB_SHIFT                                                21
+  #define UMAC_REG_COMMAND_CONFIG_ENA_EXT_CONFIG_BB                                                          (0x1<<22) // Enable Configuration with External Pins. When set to '0' (Reset value) the Core speed and Mode is programmed with the register bits ETH_SPEED(1:0) and HD_ENA. When set to '1'; the Core is configured with the pins set_speed(1:0) and set_duplex.
+  #define UMAC_REG_COMMAND_CONFIG_ENA_EXT_CONFIG_BB_SHIFT                                                    22
+  #define UMAC_REG_COMMAND_CONFIG_CNTL_FRM_ENA_BB                                                            (0x1<<23) // MAC Control Frame Enable. When set to '1'; MAC Control frames with any Opcode other than 0x0001 are accepted and forward to the Client interface. When set to '0' (Reset value); MAC Control frames with any Opcode other than 0x0001 are silently discarded.
+  #define UMAC_REG_COMMAND_CONFIG_CNTL_FRM_ENA_BB_SHIFT                                                      23
+  #define UMAC_REG_COMMAND_CONFIG_NO_LGTH_CHECK_BB                                                           (0x1<<24) // Payload Length Check Disable. When set to '0'; the Core checks the frame's payload length with the Frame Length/Type field; when set to '1'(Reset value); the payload length check is disabled.
+  #define UMAC_REG_COMMAND_CONFIG_NO_LGTH_CHECK_BB_SHIFT                                                     24
+  #define UMAC_REG_COMMAND_CONFIG_LINE_LOOPBACK_BB                                                           (0x1<<25) // Enable Line Loopback i.e. MAC FIFO side loopback; when set to '1'; normal operation when set to '0' (Reset value).
+  #define UMAC_REG_COMMAND_CONFIG_LINE_LOOPBACK_BB_SHIFT                                                     25
+  #define UMAC_REG_COMMAND_CONFIG_RX_ERR_DISC_BB                                                             (0x1<<26) // Receive Errored Frame Discard Enable. When set to '1'; any frame received with an error is discarded in the Core and not forwarded to the Client interface. When set to '0'; errored Frames are forwarded to the Client interface with ff_rx_err asserted. It is recommended to set RX_ERR_DISC to '1' only when Store and Forward operation is enabled on the Core Receive FIFO Receive FIFO Section full threshold set to 0).
+  #define UMAC_REG_COMMAND_CONFIG_RX_ERR_DISC_BB_SHIFT                                                       26
+  #define UMAC_REG_COMMAND_CONFIG_PRBL_ENA_BB                                                                (0x1<<27) // Reserved.
+  #define UMAC_REG_COMMAND_CONFIG_PRBL_ENA_BB_SHIFT                                                          27
+  #define UMAC_REG_COMMAND_CONFIG_IGNORE_TX_PAUSE_BB                                                         (0x1<<28) // Ignores the back pressure signaling from the system and hence no Tx pause generation; when set.
+  #define UMAC_REG_COMMAND_CONFIG_IGNORE_TX_PAUSE_BB_SHIFT                                                   28
+  #define UMAC_REG_COMMAND_CONFIG_OOB_EFC_EN_BB                                                              (0x1<<29) // If set then out-of-band egress flow control is enabled. When this bit is set and input pin ext_tx_flow_control is enabled then data frame trasmission is stopped; whereas Pause & PFC frames are transmitted normally. This operation is similar to halting the transmit datapath due to the reception of a Pause Frame with non-zero timer value; and is used in applications where the flow control information is exchanged out of band. Enabling or disabling this bit has no effect on regular Rx_pause pkt based egress flow control.
+  #define UMAC_REG_COMMAND_CONFIG_OOB_EFC_EN_BB_SHIFT                                                        29
+  #define UMAC_REG_COMMAND_CONFIG_RUNT_FILTER_DIS_BB                                                         (0x1<<30) // When set; disable runt filtering.
+  #define UMAC_REG_COMMAND_CONFIG_RUNT_FILTER_DIS_BB_SHIFT                                                   30
+#define UMAC_REG_MAC_0_BB                                                                                    0x05100cUL //Access:RW   DataWidth:0x20   // Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refers to bit 17 of the MAC address etc.
+#define UMAC_REG_MAC_1_BB                                                                                    0x051010UL //Access:RW   DataWidth:0x10   // Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 1 refers to Bit 1 of the MAC address etc. Bits 16 to 31 are reserved.
+#define UMAC_REG_FRM_LENGTH                                                                                  0x051014UL //Access:RW   DataWidth:0x10   // Defines a 16-Bit maximum frame length used by the MAC receive logic to check frames.
+#define UMAC_REG_PAUSE_QUANT_BB                                                                              0x051018UL //Access:RW   DataWidth:0x10   // 16-Bit value; sets; in increment of 512 Ethernet bit times; the pause quanta used in each Pause Frame sent to the remote Ethernet device.
+#define UMAC_REG_SFD_OFFSET_BB                                                                               0x051040UL //Access:RW   DataWidth:0x4    // Defines the length of the EFM preamble between 5 and 15 Bytes. When set to 0; 1; 2; 3 or 4; the Preamble EFM length is set to 5 Bytes.
+#define UMAC_REG_MAC_MODE                                                                                    0x051044UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define UMAC_REG_MAC_MODE_PAUSE_RX_EN_K2_E5                                                                (0x1<<3) // Rx Flow. Setting this bit will cause the receive MAC control to detect and act on PAUSE flow control frames. Clearing this bit causes the receive MAC control to ignore PAUSE flow control frames.
+  #define UMAC_REG_MAC_MODE_PAUSE_RX_EN_K2_E5_SHIFT                                                          3
+  #define UMAC_REG_MAC_MODE_PAUSE_TX_EN_K2_E5                                                                (0x1<<4) // Tx Flow. Setting this bit will allow the transmit MAC control to send PAUSE flow control frames when requested by the system. Clearing this bit prevents the transmit MAC control from sending flow control frames.
+  #define UMAC_REG_MAC_MODE_PAUSE_TX_EN_K2_E5_SHIFT                                                          4
+  #define UMAC_REG_MAC_MODE_MAC_SPEED_BB                                                                     (0x3<<0) // MAC Speed. 00: 10Mbps Ethernet Mode enabled 01: 100Mbps Ethernet Mode enabled 10: Gigabit Ethernet Mode enabled 11: 2.5Gigabit Ethernet Mode enabled.
+  #define UMAC_REG_MAC_MODE_MAC_SPEED_BB_SHIFT                                                               0
+  #define UMAC_REG_MAC_MODE_MAC_DUPLEX_BB                                                                    (0x1<<2) // MAC Duplex. 0: Full Duplex Mode enabled 1: Half Duplex Mode enabled.
+  #define UMAC_REG_MAC_MODE_MAC_DUPLEX_BB_SHIFT                                                              2
+  #define UMAC_REG_MAC_MODE_MAC_RX_PAUSE_BB                                                                  (0x1<<3) // MAC Pause Enabled in Receive. 0: MAC Pause Disabled in Receive 1: MAC Pause Enabled in Receive.
+  #define UMAC_REG_MAC_MODE_MAC_RX_PAUSE_BB_SHIFT                                                            3
+  #define UMAC_REG_MAC_MODE_MAC_TX_PAUSE_BB                                                                  (0x1<<4) // MAC Pause Enabled in Transmit. 0: MAC Pause Disabled in Transmit 1: MAC Pause Enabled in Transmit.
+  #define UMAC_REG_MAC_MODE_MAC_TX_PAUSE_BB_SHIFT                                                            4
+  #define UMAC_REG_MAC_MODE_LINK_STATUS_BB                                                                   (0x1<<5) // Link Status Indication. Set to '0'; when link_status input is low. Set to '1'; when link_status input is High.
+  #define UMAC_REG_MAC_MODE_LINK_STATUS_BB_SHIFT                                                             5
+#define UMAC_REG_TAG_0_BB                                                                                    0x051048UL //Access:RW   DataWidth:0x11   // Multi Field Register.
+  #define UMAC_REG_TAG_0_FRM_TAG_0_BB                                                                        (0xffff<<0) // Outer tag of the programmable VLAN tag.
+  #define UMAC_REG_TAG_0_FRM_TAG_0_BB_SHIFT                                                                  0
+  #define UMAC_REG_TAG_0_CONFIG_OUTER_TPID_ENABLE_BB                                                         (0x1<<16) // If cleared then disable outer TPID detection.
+  #define UMAC_REG_TAG_0_CONFIG_OUTER_TPID_ENABLE_BB_SHIFT                                                   16
+#define UMAC_REG_TAG_1_BB                                                                                    0x05104cUL //Access:RW   DataWidth:0x11   // Multi Field Register.
+  #define UMAC_REG_TAG_1_FRM_TAG_1_BB                                                                        (0xffff<<0) // inner tag of the programmable VLAN tag.
+  #define UMAC_REG_TAG_1_FRM_TAG_1_BB_SHIFT                                                                  0
+  #define UMAC_REG_TAG_1_CONFIG_INNER_TPID_ENABLE_BB                                                         (0x1<<16) // If cleared then disable inner TPID detection.
+  #define UMAC_REG_TAG_1_CONFIG_INNER_TPID_ENABLE_BB_SHIFT                                                   16
+#define UMAC_REG_RX_PAUSE_QUANTA_SCALE_BB                                                                    0x051050UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define UMAC_REG_RX_PAUSE_QUANTA_SCALE_SCALE_VALUE_BB                                                      (0xffff<<0) // The pause timer is loaded with the value obtained after adding or subtracting the scale_value from the received pause quanta.
+  #define UMAC_REG_RX_PAUSE_QUANTA_SCALE_SCALE_VALUE_BB_SHIFT                                                0
+  #define UMAC_REG_RX_PAUSE_QUANTA_SCALE_SCALE_CONTROL_BB                                                    (0x1<<16) // If clear; then subtract the scale_value from the received pause quanta. If set; then add the scale_value from the received pause quanta.
+  #define UMAC_REG_RX_PAUSE_QUANTA_SCALE_SCALE_CONTROL_BB_SHIFT                                              16
+  #define UMAC_REG_RX_PAUSE_QUANTA_SCALE_SCALE_FIX_BB                                                        (0x1<<17) // If set; then receive pause quanta is ignored and a fixed quanta value programmed in SCALE_VALUE is loaded into the pause timer. If set; then SCALE_CONTROL is ignored. If cleared; then SCALE_CONTROL takes into effect.
+  #define UMAC_REG_RX_PAUSE_QUANTA_SCALE_SCALE_FIX_BB_SHIFT                                                  17
+#define UMAC_REG_TX_PREAMBLE_BB                                                                              0x051054UL //Access:RW   DataWidth:0x3    // Set the transmit preamble excluding SFD to be programmable from min of 2 bytes to the max allowable of 7 bytes; with granularity of 1 byte.
+#define UMAC_REG_TX_IPG_LENGTH                                                                               0x05105cUL //Access:RW   DataWidth:0x8    // Programmable field representing the IPG between Back-to-Back packets. This is the IPG parameter used exclusively in Full-Duplex mode when two transmit packets are sent back-to-back. Set this field to the number of bits of IPG desired. The default setting of 0x60 (96d) represents the minimum IPG of 96 bits.
+#define UMAC_REG_PFC_XOFF_TIMER_BB                                                                           0x051060UL //Access:RW   DataWidth:0x10   // Time value sent in the Timer Field for classes in XOFF state (Unit is 512 bit-times).
+#define UMAC_REG_UMAC_EEE_CTRL_BB                                                                            0x051064UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define UMAC_REG_UMAC_EEE_CTRL_EEE_EN_BB                                                                   (0x1<<3) // If set; the TX LPI policy control engine is enabled and the MAC inserts LPI_idle codes if the link is idle. The rx_lpi_detect assertion is independent of this configuration. Reset default depends on EEE_en_strap input; which if tied to 1; defaults to enabled; otherwise if tied to 0; defaults to disabled.
+  #define UMAC_REG_UMAC_EEE_CTRL_EEE_EN_BB_SHIFT                                                             3
+  #define UMAC_REG_UMAC_EEE_CTRL_RX_FIFO_CHECK_BB                                                            (0x1<<4) // If enabled; lpi_rx_detect is set whenever the LPI_IDLES are being received on the RX line and Unimac Rx FIFO is empty. By default; lpi_rx_detect is set only when whenever the LPI_IDLES are being received on the RX line.
+  #define UMAC_REG_UMAC_EEE_CTRL_RX_FIFO_CHECK_BB_SHIFT                                                      4
+  #define UMAC_REG_UMAC_EEE_CTRL_EEE_TXCLK_DIS_BB                                                            (0x1<<5) // If enabled; UNIMAC will shut down TXCLK to PHY; when in LPI state.
+  #define UMAC_REG_UMAC_EEE_CTRL_EEE_TXCLK_DIS_BB_SHIFT                                                      5
+  #define UMAC_REG_UMAC_EEE_CTRL_DIS_EEE_10M_BB                                                              (0x1<<6) // When this bit is set and link is established at 10Mbps; LPI is not supported (saving is achieved by reduced PHY's output swing). UNIMAC ignores EEE feature on both Tx & Rx in 10Mbps. When cleared; Unimac doesn't differentiate between speeds for EEE feature.
+  #define UMAC_REG_UMAC_EEE_CTRL_DIS_EEE_10M_BB_SHIFT                                                        6
+  #define UMAC_REG_UMAC_EEE_CTRL_LP_IDLE_PREDICTION_MODE_BB                                                  (0x1<<7) // When set to 1; enables LP_IDLE Prediction. When set to 0; disables LP_IDLE Prediction.
+  #define UMAC_REG_UMAC_EEE_CTRL_LP_IDLE_PREDICTION_MODE_BB_SHIFT                                            7
+#define UMAC_REG_MII_EEE_DELAY_ENTRY_TIMER_BB                                                                0x051068UL //Access:RW   DataWidth:0x20   // This is the duration for which condition to move to LPI state must be satisfied; at the end of which MAC transitions to LPI State. The decrement unit is 1 micro-second. This register is meant for 10/100 Mbps speed.
+#define UMAC_REG_GMII_EEE_DELAY_ENTRY_TIMER_BB                                                               0x05106cUL //Access:RW   DataWidth:0x20   // This is the duration for which condition to move to LPI state must be satisfied; at the end of which MAC transitions to LPI State. The decrement unit is 1 micro-second. This register is meant for 1000 Mbps speed.
+#define UMAC_REG_UMAC_EEE_REF_COUNT_BB                                                                       0x051070UL //Access:RW   DataWidth:0x10   // This field controls clock divider used to generate ~1us reference pulses used by EEE timers. It specifies integer number of timer clock cycles contained within 1us. We may consider having 0.5us reference; as timeout values in 802.3az/D1.3 are not always integer number of 1us.
+#define UMAC_REG_UMAC_RX_PKT_DROP_STATUS_BB                                                                  0x051078UL //Access:RW   DataWidth:0x1    // Debug status; set if MAC receives an IPG less than programmed RX IPG or less than four bytes. Sticky bit. Clears when SW writes 0 into the field or by sw_reset.
+#define UMAC_REG_UMAC_SYMMETRIC_IDLE_THRESHOLD_BB                                                            0x05107cUL //Access:RW   DataWidth:0x10   // If LPI_Prediction is enabled then this register defines the number of IDLEs to be received by the UniMAC before allowing LP_IDLE to be sent to Link Partner.
+#define UMAC_REG_MII_EEE_WAKE_TIMER_BB                                                                       0x051080UL //Access:RW   DataWidth:0x10   // This is the duration for which MAC must wait to go back to ACTIVE state from LPI state when it receives packet for transmission. The decrement unit is 1 micro-second. This register is meant for 10/100 Mbps speed.
+#define UMAC_REG_GMII_EEE_WAKE_TIMER_BB                                                                      0x051084UL //Access:RW   DataWidth:0x10   // This is the duration for which MAC must wait to go back to ACTIVE state from LPI state when it receives packet for transmission. The decrement unit is 1 micro-second. This register is meant for 1000 Mbps speed.
+#define UMAC_REG_UMAC_REV_ID_BB                                                                              0x051088UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define UMAC_REG_UMAC_REV_ID_PATCH_BB                                                                      (0xff<<0) // Unimac revision patch number.
+  #define UMAC_REG_UMAC_REV_ID_PATCH_BB_SHIFT                                                                0
+  #define UMAC_REG_UMAC_REV_ID_REVISION_ID_MINOR_BB                                                          (0xff<<8) // Unimac version id field after decimal.
+  #define UMAC_REG_UMAC_REV_ID_REVISION_ID_MINOR_BB_SHIFT                                                    8
+  #define UMAC_REG_UMAC_REV_ID_REVISION_ID_MAJOR_BB                                                          (0xff<<16) // Unimac version id field before decimal.
+  #define UMAC_REG_UMAC_REV_ID_REVISION_ID_MAJOR_BB_SHIFT                                                    16
+#define UMAC_REG_TX_IPG_LENGTH1_K2_E5                                                                        0x05108cUL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define UMAC_REG_TX_IPG_LENGTH1_IPGR1_K2_E5                                                                (0x7f<<16) // Non Back-to-Back Transmit IPG part 1 (carrier sense window).
+  #define UMAC_REG_TX_IPG_LENGTH1_IPGR1_K2_E5_SHIFT                                                          16
+  #define UMAC_REG_TX_IPG_LENGTH1_IPGR2_K2_E5                                                                (0x7f<<24) // Non Back-to-Back Transmit IPG part 2.
+  #define UMAC_REG_TX_IPG_LENGTH1_IPGR2_K2_E5_SHIFT                                                          24
+#define UMAC_REG_ECO_RESERVED_K2_E5                                                                          0x051090UL //Access:RW   DataWidth:0x20   // This is unused register for future ECOs.
+#define UMAC_REG_DBG_SELECT_K2_E5                                                                            0x051094UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define UMAC_REG_DBG_DWORD_ENABLE_K2_E5                                                                      0x051098UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define UMAC_REG_DBG_SHIFT_K2_E5                                                                             0x05109cUL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define UMAC_REG_DBG_FORCE_VALID_K2_E5                                                                       0x0510a0UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define UMAC_REG_DBG_FORCE_FRAME_K2_E5                                                                       0x0510a4UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define UMAC_REG_DBG_OUT_DATA_K2_E5                                                                          0x0510c0UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define UMAC_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define UMAC_REG_DBG_OUT_VALID_K2_E5                                                                         0x0510e0UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define UMAC_REG_DBG_OUT_FRAME_K2_E5                                                                         0x0510e4UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define UMAC_REG_INT_STS_K2_E5                                                                               0x051180UL //Access:R    DataWidth:0x2    // Multi Field Register.
+  #define UMAC_REG_INT_STS_ADDRESS_ERROR_K2_E5                                                               (0x1<<0) // Signals an unknown address to the rf module.
+  #define UMAC_REG_INT_STS_ADDRESS_ERROR_K2_E5_SHIFT                                                         0
+  #define UMAC_REG_INT_STS_TX_OVERFLOW_K2_E5                                                                 (0x1<<1) // TX fifo overflow
+  #define UMAC_REG_INT_STS_TX_OVERFLOW_K2_E5_SHIFT                                                           1
+#define UMAC_REG_INT_MASK_K2_E5                                                                              0x051184UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define UMAC_REG_INT_MASK_ADDRESS_ERROR_K2_E5                                                              (0x1<<0) // This bit masks, when set, the Interrupt bit: UMAC_REG_INT_STS.ADDRESS_ERROR .
+  #define UMAC_REG_INT_MASK_ADDRESS_ERROR_K2_E5_SHIFT                                                        0
+  #define UMAC_REG_INT_MASK_TX_OVERFLOW_K2_E5                                                                (0x1<<1) // This bit masks, when set, the Interrupt bit: UMAC_REG_INT_STS.TX_OVERFLOW .
+  #define UMAC_REG_INT_MASK_TX_OVERFLOW_K2_E5_SHIFT                                                          1
+#define UMAC_REG_INT_STS_WR_K2_E5                                                                            0x051188UL //Access:WR   DataWidth:0x2    // Multi Field Register.
+  #define UMAC_REG_INT_STS_WR_ADDRESS_ERROR_K2_E5                                                            (0x1<<0) // Signals an unknown address to the rf module.
+  #define UMAC_REG_INT_STS_WR_ADDRESS_ERROR_K2_E5_SHIFT                                                      0
+  #define UMAC_REG_INT_STS_WR_TX_OVERFLOW_K2_E5                                                              (0x1<<1) // TX fifo overflow
+  #define UMAC_REG_INT_STS_WR_TX_OVERFLOW_K2_E5_SHIFT                                                        1
+#define UMAC_REG_INT_STS_CLR_K2_E5                                                                           0x05118cUL //Access:RC   DataWidth:0x2    // Multi Field Register.
+  #define UMAC_REG_INT_STS_CLR_ADDRESS_ERROR_K2_E5                                                           (0x1<<0) // Signals an unknown address to the rf module.
+  #define UMAC_REG_INT_STS_CLR_ADDRESS_ERROR_K2_E5_SHIFT                                                     0
+  #define UMAC_REG_INT_STS_CLR_TX_OVERFLOW_K2_E5                                                             (0x1<<1) // TX fifo overflow
+  #define UMAC_REG_INT_STS_CLR_TX_OVERFLOW_K2_E5_SHIFT                                                       1
+#define UMAC_REG_MAC_PFC_TYPE                                                                                0x051300UL //Access:RW   DataWidth:0x10   // Pause Type.  This value is inserted into the Type/Length field of the Pause frames generated by the MAC and used to validate Pause frames received by the MAC.
+#define UMAC_REG_PAUSE_OPCODE_K2_E5                                                                          0x051304UL //Access:RW   DataWidth:0x10   // Pause Frame Opcode.  This value is inserted into the opcode field of the Pause frames generated by the MAC and used to validate Pause frames received by the MAC.  Note; the default value is for standard pause.
+#define UMAC_REG_MAC_PFC_OPCODE_BB                                                                           0x051304UL //Access:RW   DataWidth:0x10   // These 16 bits are for opcode. Since PFC is not standardized yet; the opcode must be programmable to make sure that when it gets standardized; we can be standards compliant.
+#define UMAC_REG_MAC_PAUSE_DA_0_K2_E5                                                                        0x051308UL //Access:RW   DataWidth:0x20   // Pause frame Destination address.  This field is inserted into the destination address field of the MAC generated pause frames and is used to compare against the destination address of received packets.  The remaining 16 bits are contained in the next register.  By default, it contains the reserved multicast address of the MAC control frame.
+#define UMAC_REG_MAC_PFC_DA_0_BB                                                                             0x051308UL //Access:RW   DataWidth:0x20   // Lower 32 bits of programmable DA for PPP. Since PPP is not standardized yet; the DA must be programmable to make sure that when it gets standardized; we can be standards compliant.
+#define UMAC_REG_MAC_PAUSE_DA_1_K2_E5                                                                        0x05130cUL //Access:RW   DataWidth:0x10   // Pause frame Destination address.  This field is inserted into the destination address field of the MAC generated pause frames and is used to compare against the destination address of received packets.  The remaining 32 bits are contained in the previous register.  By default, it contains the reserved multicast address of the MAC control frame.
+#define UMAC_REG_MAC_PFC_DA_1_BB                                                                             0x05130cUL //Access:RW   DataWidth:0x10   // Upper 16 bits of programmable DA for PPP. Since PPP is not standardized yet; the DA must be programmable to make sure that when it gets standardized; we can be standards compliant.
+#define UMAC_REG_MAC_PAUSE_DA1_0_K2_E5                                                                       0x051310UL //Access:RW   DataWidth:0x20   // Pause frame Destination address.  This field is used to compare against the destination address of received packets.  The remaining 16 bits are contained in the next register.  By default, it contains the reserved multicast address of the MAC control frame.
+#define UMAC_REG_MACSEC_PROG_TX_CRC_BB                                                                       0x051310UL //Access:RW   DataWidth:0x20   // The transmitted CRC can be corrupted by replacing the FCS of the transmitted frame by the FCS programmed in this register. This is enabled and controlled by MACSEC_CNTRL register.
+#define UMAC_REG_MAC_PAUSE_DA1_1_K2_E5                                                                       0x051314UL //Access:RW   DataWidth:0x10   // Pause frame Destination address.  This field is used to compare against the destination address of received packets.  The remaining 32 bits are contained in the previous register.  By default, it contains the reserved multicast address of the MAC control frame.
+#define UMAC_REG_MACSEC_CNTRL_BB                                                                             0x051314UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define UMAC_REG_MACSEC_CNTRL_TX_LAUNCH_EN_BB                                                              (0x1<<0) // Set the bit 0 (Tx_Launch_en) logic 0; if the tx_launch function is to be disabled. If set; then the launch_enable signal assertion/deassertion causes the packet transmit enabled/disabled. The launch_enable is per packet basis.
+  #define UMAC_REG_MACSEC_CNTRL_TX_LAUNCH_EN_BB_SHIFT                                                        0
+  #define UMAC_REG_MACSEC_CNTRL_TX_CRC_CORUPT_EN_BB                                                          (0x1<<1) // Setting this field enables the CRC corruption on the transmitted packets. The options of how to corrupt; depends on the field 2 of this register (TX_CRC_PROGRAM). The CRC corruption happens only on the frames for which TXCRCER is asserted by the system.
+  #define UMAC_REG_MACSEC_CNTRL_TX_CRC_CORUPT_EN_BB_SHIFT                                                    1
+  #define UMAC_REG_MACSEC_CNTRL_TX_CRC_PROGRAM_BB                                                            (0x1<<2) // If CRC corruption feature in enabled (TX_CRC_CORUPT_EN set); then in case where this bit when set; replaces the transmitted FCS with the programmed FCS. When cleared; corrupts the CRC of the transmitted packet internally.
+  #define UMAC_REG_MACSEC_CNTRL_TX_CRC_PROGRAM_BB_SHIFT                                                      2
+  #define UMAC_REG_MACSEC_CNTRL_DIS_PAUSE_DATA_VAR_IPG_BB                                                    (0x1<<3) // When this bit is 1; IPG between pause and data frame is as per the original design; i.e.; 13B or 12B; fixed. It should be noted; that as number of preamble bytes reduces from 7; the IPG also increases. When this bit is 0; IPG between pause and data frame is variable and equals programmed IPG or programmed IPG + 1.
+  #define UMAC_REG_MACSEC_CNTRL_DIS_PAUSE_DATA_VAR_IPG_BB_SHIFT                                              3
+#define UMAC_REG_MAC_PAUSE_SA_0_K2_E5                                                                        0x051318UL //Access:RW   DataWidth:0x20   // This register contains the bits [31:0] in the 48-bit MAC address.  The MAC address is used as the SA for automatically generated MAC control pause frames.
+#define UMAC_REG_TS_STATUS_CNTRL_BB                                                                          0x051318UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define UMAC_REG_TS_STATUS_CNTRL_TX_TS_FIFO_FULL_BB                                                        (0x1<<0) // Read-only field assertion shows that the transmit timestamp FIFO is full.
+  #define UMAC_REG_TS_STATUS_CNTRL_TX_TS_FIFO_FULL_BB_SHIFT                                                  0
+  #define UMAC_REG_TS_STATUS_CNTRL_TX_TS_FIFO_EMPTY_BB                                                       (0x1<<1) // Read-only field assertion shows that the transmit timestamp FIFO is empty.
+  #define UMAC_REG_TS_STATUS_CNTRL_TX_TS_FIFO_EMPTY_BB_SHIFT                                                 1
+  #define UMAC_REG_TS_STATUS_CNTRL_WORD_AVAIL_BB                                                             (0x7<<2) // Indicates number of cells filled in the TX timestamp FIFO.
+  #define UMAC_REG_TS_STATUS_CNTRL_WORD_AVAIL_BB_SHIFT                                                       2
+#define UMAC_REG_MAC_PAUSE_SA_1_K2_E5                                                                        0x05131cUL //Access:RW   DataWidth:0x10   // This register contains the bits [47:32] in the 48-bit MAC address.  The MAC address is used as the SA for automatically generated MAC control pause frames.
+#define UMAC_REG_TX_TS_DATA_BB                                                                               0x05131cUL //Access:RW   DataWidth:0x20   // Every read of this register will fetch out one timestamp value corresponding to the preceding seq_id read from the transmit FIFO. Every 49 bit; val_bit + seq_id + timestamp is read in two steps; i.e.; one read from 0x10f (val_bit + seq_id) followed by another read from 0x1c7 (timestamp). Timestamp read without a preceding seq_id read will fetch stale timestamp value.
+#define UMAC_REG_PAUSE_CONTROL                                                                               0x051330UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define UMAC_REG_PAUSE_CONTROL_PAUSE_TIME_K2_E5                                                            (0xffff<<0) // If set and a Pause frame is being forced, send a Pause frame with the Pause Time Field specified in rf_omac_pause_time.  If this bit is cleared send a Pause frame with the zero pause time.
+  #define UMAC_REG_PAUSE_CONTROL_PAUSE_TIME_K2_E5_SHIFT                                                      0
+  #define UMAC_REG_PAUSE_CONTROL_TIME_NRESUME_K2_E5                                                          (0x1<<17) // If set and a Pause frame is being forced, send a Pause frame with the Pause Time Field specified in rf_omac_pause_time.  If this bit is cleared send a Pause frame with the zero pause time.
+  #define UMAC_REG_PAUSE_CONTROL_TIME_NRESUME_K2_E5_SHIFT                                                    17
+  #define UMAC_REG_PAUSE_CONTROL_PAUSE_MODE_K2_E5                                                            (0x1<<18) // Pause mode 0 = Standard Pause, 1 = PFC Pause.
+  #define UMAC_REG_PAUSE_CONTROL_PAUSE_MODE_K2_E5_SHIFT                                                      18
+  #define UMAC_REG_PAUSE_CONTROL_FORCE_STD_PAUSE_K2_E5                                                       (0x1<<23) // Force sending a Standard Pause Frame.  The value of the Pause time is defined by rf_omac_time_nresume.  If rf_omac_time_nresume is set, the chip should continue to send Standard Pause frames at periodic intervals until rf_omac_time_nresume  is cleared.  If rf_omac_time_nresume is cleared, after sending a single Standard Pause frame the internal timer should be cleared.
+  #define UMAC_REG_PAUSE_CONTROL_FORCE_STD_PAUSE_K2_E5_SHIFT                                                 23
+  #define UMAC_REG_PAUSE_CONTROL_FORCE_PP_PAUSE_K2_E5                                                        (0xff<<24) // Force sending a Per Priority Pause Frame.  Each bit in this field corresponds to a priority that should be set in a Per Priority Pause frame.  Bit 2 is priority 0 and so on.  The value of the Pause time is defined by rf_omac_time_nresume .  If rf_omac_time_nresume is set, the chip should continue to send Per Priority Pause frames at periodic intervals until rf_omac_time_nresume is cleared.  If rf_omac_time_nresume is cleared, after sending a single Per Priority Pause frame the internal timers for the selected priorities should be cleared. Note:  After forcing a Pause on a 10G port, a Resume must be forced to return the chip to normal Pause/Resume behavior.
+  #define UMAC_REG_PAUSE_CONTROL_FORCE_PP_PAUSE_K2_E5_SHIFT                                                  24
+  #define UMAC_REG_PAUSE_CONTROL_VALUE_BB                                                                    (0x1ffff<<0) // Each bit in this register represents 512 bit times independent of the port speed. Values of 0 and 1 are illegal.
+  #define UMAC_REG_PAUSE_CONTROL_VALUE_BB_SHIFT                                                              0
+  #define UMAC_REG_PAUSE_CONTROL_ENABLE_BB                                                                   (0x1<<17) // Enable Extra Pause Frames.
+  #define UMAC_REG_PAUSE_CONTROL_ENABLE_BB_SHIFT                                                             17
+#define UMAC_REG_RSV_ERR_MASK_K2_E5                                                                          0x051334UL //Access:RW   DataWidth:0x16   // 0 - skipped (unsupported) 1 - stackvlan (unsupported) 2 - carrerr (on by default) 3 - codeerr (on by default) 4 - crcerr (on by default) 5 - lenerr 6 - oversize (on by default) 7 - rxok 8 - mcast 9 - bcast 10 - dribble (on by default) 11 - control 12 - pause (on by default) 13 - unsupp_op 14 - vlan 15 - unicast 16 - truncate (on by default) 17 - runt (on by default) 18 - ppp (per priority pause) 19 - rxfifooflow (rx fifo overflow (on by default)) [21:20] - unused
+#define UMAC_REG_FLUSH_CONTROL_BB                                                                            0x051334UL //Access:RW   DataWidth:0x1    // Flush enable bit to drop out all packets in Tx FIFO without egressing any packets when set.
+#define UMAC_REG_PROBE_ADDRESS_K2_E5                                                                         0x051338UL //Access:RW   DataWidth:0x8    // probe address bit 7 - U/L bit 6 - GMII/XMGII CLK bits [5:0] mux select
+#define UMAC_REG_RXFIFO_STAT_BB                                                                              0x051338UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define UMAC_REG_RXFIFO_STAT_RXFIFO_UNDERRUN_BB                                                            (0x1<<0) // RXFIFO Underrun occurred. Cleared by only reset.
+  #define UMAC_REG_RXFIFO_STAT_RXFIFO_UNDERRUN_BB_SHIFT                                                      0
+  #define UMAC_REG_RXFIFO_STAT_RXFIFO_OVERRUN_BB                                                             (0x1<<1) // RXFIFO Overrun occurred. Cleared by only reset.
+  #define UMAC_REG_RXFIFO_STAT_RXFIFO_OVERRUN_BB_SHIFT                                                       1
+#define UMAC_REG_PROBE_DATA_K2_E5                                                                            0x05133cUL //Access:R    DataWidth:0x20   // probe data based on probe address
+#define UMAC_REG_TXFIFO_STAT_BB                                                                              0x05133cUL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define UMAC_REG_TXFIFO_STAT_TXFIFO_UNDERRUN_BB                                                            (0x1<<0) // TXFIFO Underrun occurred. Cleared by only reset.
+  #define UMAC_REG_TXFIFO_STAT_TXFIFO_UNDERRUN_BB_SHIFT                                                      0
+  #define UMAC_REG_TXFIFO_STAT_TXFIFO_OVERRUN_BB                                                             (0x1<<1) // TXFIFO Overrun occurred. Cleared by only reset.
+  #define UMAC_REG_TXFIFO_STAT_TXFIFO_OVERRUN_BB_SHIFT                                                       1
+#define UMAC_REG_MAC_PFC_CTRL_BB                                                                             0x051340UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define UMAC_REG_MAC_PFC_CTRL_PFC_TX_ENBL_BB                                                               (0x1<<0) // Enables the PPP-Tx functionality.
+  #define UMAC_REG_MAC_PFC_CTRL_PFC_TX_ENBL_BB_SHIFT                                                         0
+  #define UMAC_REG_MAC_PFC_CTRL_PFC_RX_ENBL_BB                                                               (0x1<<1) // Enables the PPP-Rx functionality.
+  #define UMAC_REG_MAC_PFC_CTRL_PFC_RX_ENBL_BB_SHIFT                                                         1
+  #define UMAC_REG_MAC_PFC_CTRL_FORCE_PFC_XON_BB                                                             (0x1<<2) // Instructs MAC to send Xon message to all classes of service.
+  #define UMAC_REG_MAC_PFC_CTRL_FORCE_PFC_XON_BB_SHIFT                                                       2
+  #define UMAC_REG_MAC_PFC_CTRL_RX_PASS_PFC_FRM_BB                                                           (0x1<<4) // When set; MAC pass PFC frame to the system. Otherwise; PFC frame is discarded.
+  #define UMAC_REG_MAC_PFC_CTRL_RX_PASS_PFC_FRM_BB_SHIFT                                                     4
+  #define UMAC_REG_MAC_PFC_CTRL_PFC_STATS_EN_BB                                                              (0x1<<5) // When clear; none of PFC related counters should increment. Otherwise; PFC counters is in full function. Note: it is programming requirement to set this bit when PFC function is enable.
+  #define UMAC_REG_MAC_PFC_CTRL_PFC_STATS_EN_BB_SHIFT                                                        5
+#define UMAC_REG_MAC_PFC_REFRESH_CTRL_BB                                                                     0x051344UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define UMAC_REG_MAC_PFC_REFRESH_CTRL_PFC_REFRESH_EN_BB                                                    (0x1<<0) // Enables the PPP refresh functionality on the Tx side. When enabled; the MAC sends Xoff message on refresh counter becoming 0.
+  #define UMAC_REG_MAC_PFC_REFRESH_CTRL_PFC_REFRESH_EN_BB_SHIFT                                              0
+  #define UMAC_REG_MAC_PFC_REFRESH_CTRL_PFC_REFRESH_TIMER_BB                                                 (0xffff<<16) // PPP refresh counter value.
+  #define UMAC_REG_MAC_PFC_REFRESH_CTRL_PFC_REFRESH_TIMER_BB_SHIFT                                           16
+#define MCP2_REG_PRTY_MASK                                                                                   0x052044UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define MCP2_REG_PRTY_MASK_ROM_PARITY                                                                      (0x1<<0) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS.ROM_PARITY .
+  #define MCP2_REG_PRTY_MASK_ROM_PARITY_SHIFT                                                                0
+#define MCP2_REG_ECO_RESERVED                                                                                0x052200UL //Access:RW   DataWidth:0x8    // Debug only: Reserved bits for ECO.
+#define MCP2_REG_PRTY_MASK_H_0_BB_K2                                                                         0x052208UL //Access:RW   DataWidth:0xc    // Multi Field Register.
+  #define MCP2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_K2                                                   (0x1<<0) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
+  #define MCP2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_K2_SHIFT                                             0
+  #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT_BB_K2                                                 (0x1<<1) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM006_I_ECC_0_RF_INT .
+  #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT_BB_K2_SHIFT                                           1
+  #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT_BB_K2                                                 (0x1<<2) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM006_I_ECC_1_RF_INT .
+  #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT_BB_K2_SHIFT                                           2
+  #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_2_RF_INT_BB_K2                                                 (0x1<<3) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM006_I_ECC_2_RF_INT .
+  #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_2_RF_INT_BB_K2_SHIFT                                           3
+  #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_3_RF_INT_BB_K2                                                 (0x1<<4) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM006_I_ECC_3_RF_INT .
+  #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_3_RF_INT_BB_K2_SHIFT                                           4
+  #define MCP2_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT_BB_K2                                                   (0x1<<5) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM007_I_ECC_RF_INT .
+  #define MCP2_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT_BB_K2_SHIFT                                             5
+  #define MCP2_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                     (0x1<<6) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define MCP2_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                               6
+  #define MCP2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                     (0x1<<7) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define MCP2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                               7
+  #define MCP2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                     (0x1<<8) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define MCP2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                               8
+  #define MCP2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2                                                     (0x1<<9) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define MCP2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2_SHIFT                                               9
+  #define MCP2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2                                                     (0x1<<10) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define MCP2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2_SHIFT                                               10
+  #define MCP2_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2                                                     (0x1<<11) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define MCP2_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT                                               11
+#define MCP2_REG_MEM006_RF_ECC_ERROR_CONNECT_0_BB_K2                                                         0x052214UL //Access:W    DataWidth:0xa    // Register to generate up to two ECC errors on the next write to memory: mcp.i_mcp_scratchpad_mem_0.rf_ecc_error_connect_0 Includes 2 words of 5 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 8. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define MCP2_REG_MEM006_RF_ECC_ERROR_CONNECT_1_BB_K2                                                         0x052218UL //Access:W    DataWidth:0xa    // Register to generate up to two ECC errors on the next write to memory: mcp.i_mcp_scratchpad_mem_0.rf_ecc_error_connect_1 Includes 2 words of 5 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 8. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define MCP2_REG_MEM006_RF_ECC_ERROR_CONNECT_2_BB_K2                                                         0x05221cUL //Access:W    DataWidth:0xa    // Register to generate up to two ECC errors on the next write to memory: mcp.i_mcp_scratchpad_mem_0.rf_ecc_error_connect_2 Includes 2 words of 5 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 8. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define MCP2_REG_MEM006_RF_ECC_ERROR_CONNECT_3_BB_K2                                                         0x052220UL //Access:W    DataWidth:0xa    // Register to generate up to two ECC errors on the next write to memory: mcp.i_mcp_scratchpad_mem_0.rf_ecc_error_connect_3 Includes 2 words of 5 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 8. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define MCP2_REG_MEM_ECC_ENABLE_0_BB_K2                                                                      0x052224UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define MCP2_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_BB_K2                                                    (0x1<<0) // Enable ECC for memory ecc instance mcp.i_flsh.i_flsh_buffer.i_ecc in module flsh_buffer
+  #define MCP2_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_BB_K2_SHIFT                                              0
+  #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_0_EN_BB_K2                                                  (0x1<<1) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpad_mem
+  #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_0_EN_BB_K2_SHIFT                                            1
+  #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_1_EN_BB_K2                                                  (0x1<<2) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpad_mem
+  #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_1_EN_BB_K2_SHIFT                                            2
+  #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_2_EN_BB_K2                                                  (0x1<<3) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpad_mem
+  #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_2_EN_BB_K2_SHIFT                                            3
+  #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_3_EN_BB_K2                                                  (0x1<<4) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpad_mem
+  #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_3_EN_BB_K2_SHIFT                                            4
+  #define MCP2_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_EN_BB_K2                                                    (0x1<<5) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_1.i_ecc in module mcp_scratchpad_nobe_mem
+  #define MCP2_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_EN_BB_K2_SHIFT                                              5
+#define MCP2_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                 0x052228UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_BB_K2                                             (0x1<<0) // Set parity only for memory ecc instance mcp.i_flsh.i_flsh_buffer.i_ecc in module flsh_buffer
+  #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_BB_K2_SHIFT                                       0
+  #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_0_PRTY_BB_K2                                           (0x1<<1) // Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpad_mem
+  #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_0_PRTY_BB_K2_SHIFT                                     1
+  #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_1_PRTY_BB_K2                                           (0x1<<2) // Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpad_mem
+  #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_1_PRTY_BB_K2_SHIFT                                     2
+  #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_2_PRTY_BB_K2                                           (0x1<<3) // Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpad_mem
+  #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_2_PRTY_BB_K2_SHIFT                                     3
+  #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_3_PRTY_BB_K2                                           (0x1<<4) // Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpad_mem
+  #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_3_PRTY_BB_K2_SHIFT                                     4
+  #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_PRTY_BB_K2                                             (0x1<<5) // Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_1.i_ecc in module mcp_scratchpad_nobe_mem
+  #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_PRTY_BB_K2_SHIFT                                       5
+#define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                             0x05222cUL //Access:RC   DataWidth:0x6    // Multi Field Register.
+  #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_BB_K2                                      (0x1<<0) // Record if a correctable error occurred on memory ecc instance mcp.i_flsh.i_flsh_buffer.i_ecc in module flsh_buffer
+  #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_BB_K2_SHIFT                                0
+  #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_0_CORRECT_BB_K2                                    (0x1<<1) // Record if a correctable error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpad_mem
+  #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_0_CORRECT_BB_K2_SHIFT                              1
+  #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_1_CORRECT_BB_K2                                    (0x1<<2) // Record if a correctable error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpad_mem
+  #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_1_CORRECT_BB_K2_SHIFT                              2
+  #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_2_CORRECT_BB_K2                                    (0x1<<3) // Record if a correctable error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpad_mem
+  #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_2_CORRECT_BB_K2_SHIFT                              3
+  #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_3_CORRECT_BB_K2                                    (0x1<<4) // Record if a correctable error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpad_mem
+  #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_3_CORRECT_BB_K2_SHIFT                              4
+  #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_CORRECT_BB_K2                                      (0x1<<5) // Record if a correctable error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_1.i_ecc in module mcp_scratchpad_nobe_mem
+  #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_CORRECT_BB_K2_SHIFT                                5
+#define MCP2_REG_MEM_ECC_EVENTS_BB_K2                                                                        0x052230UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define MCP2_REG_DBG_SELECT                                                                                  0x052400UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define MCP2_REG_DBG_DWORD_ENABLE                                                                            0x052404UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define MCP2_REG_DBG_SHIFT                                                                                   0x052408UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define MCP2_REG_DBG_OUT_DATA                                                                                0x052420UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define MCP2_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define MCP2_REG_DBG_FORCE_VALID                                                                             0x052440UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define MCP2_REG_DBG_FORCE_FRAME                                                                             0x052444UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define MCP2_REG_DBG_OUT_VALID                                                                               0x052448UL //Access:R    DataWidth:0x4    // Dbgmux output valid
+#define MCP2_REG_DBG_OUT_FRAME                                                                               0x05244cUL //Access:R    DataWidth:0x4    // Dbgmux output frame
+#define OPTE_REG_PRTY_MASK_H_0_BB_K2                                                                         0x053004UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define OPTE_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2                                                     (0x1<<0) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define OPTE_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2_SHIFT                                               0
+  #define OPTE_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2                                                     (0x1<<1) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
+  #define OPTE_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2_SHIFT                                               1
+  #define OPTE_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2                                                     (0x1<<2) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define OPTE_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT                                               2
+  #define OPTE_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2                                                     (0x1<<3) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define OPTE_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2_SHIFT                                               3
+  #define OPTE_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2                                                     (0x1<<4) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define OPTE_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2_SHIFT                                               4
+  #define OPTE_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2                                                     (0x1<<5) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define OPTE_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2_SHIFT                                               5
+  #define OPTE_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                     (0x1<<6) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define OPTE_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                               6
+  #define OPTE_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                     (0x1<<7) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define OPTE_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                               7
+  #define OPTE_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                     (0x1<<8) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define OPTE_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                               8
+  #define OPTE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                     (0x1<<9) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define OPTE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                               9
+  #define OPTE_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_K2                                                     (0x1<<10) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
+  #define OPTE_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_K2_SHIFT                                               10
+#define OPTE_REG_MEM_ECC_EVENTS_BB_K2                                                                        0x053010UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define OPTE_REG_ECO_RESERVED_BB_K2                                                                          0x053200UL //Access:RW   DataWidth:0x8    // Reserved bits for ECO.
+#define OPTE_REG_DORQ_FIFO_ALMOST_FULL_THR_BB_K2                                                             0x053204UL //Access:RW   DataWidth:0x5    // This field defines number of 256 bits data entries in the DORQ FIFO. When the occupancy is more than that number, local edpm_en is de-asserted. It is than combined with edpm_en from NIG to create the global edpm_en
+#define OPTE_REG_PRTY_MASK_BB_K2                                                                             0x05320cUL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define OPTE_REG_PRTY_MASK_DATAPATH_PARITY_ERROR_BB_K2                                                     (0x1<<0) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS.DATAPATH_PARITY_ERROR .
+  #define OPTE_REG_PRTY_MASK_DATAPATH_PARITY_ERROR_BB_K2_SHIFT                                               0
+#define PCIE_REG_PRTY_MASK_H_0                                                                               0x054004UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PCIE_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_BB                                                      (0x1<<4) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_BB_SHIFT                                                4
+  #define PCIE_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_K2_E5                                                   (0x1<<0) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_K2_E5_SHIFT                                             0
+  #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_K2_E5                                                   (0x1<<1) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_K2_E5_SHIFT                                             1
+  #define PCIE_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB                                                        (0x1<<7) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_SHIFT                                                  7
+  #define PCIE_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_E5                                                     (0x1<<2) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_E5_SHIFT                                               2
+  #define PCIE_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_E5                                                     (0x1<<3) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_E5_SHIFT                                               3
+  #define PCIE_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2_E5                                                     (0x1<<4) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2_E5_SHIFT                                               4
+  #define PCIE_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB                                                        (0x1<<16) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_SHIFT                                                  16
+  #define PCIE_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_E5                                                     (0x1<<5) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_E5_SHIFT                                               5
+  #define PCIE_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_K2_E5                                                     (0x1<<6) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_K2_E5_SHIFT                                               6
+  #define PCIE_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB                                                        (0x1<<6) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_SHIFT                                                  6
+  #define PCIE_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_E5                                                     (0x1<<7) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_E5_SHIFT                                               7
+  #define PCIE_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB                                                      (0x1<<0) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_SHIFT                                                0
+  #define PCIE_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_BB                                                      (0x1<<1) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_BB_SHIFT                                                1
+  #define PCIE_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT_BB                                                      (0x1<<2) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM010_I_ECC_RF_INT .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT_BB_SHIFT                                                2
+  #define PCIE_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_BB                                                      (0x1<<3) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM009_I_ECC_RF_INT .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_BB_SHIFT                                                3
+  #define PCIE_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT_BB                                                      (0x1<<5) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM007_I_ECC_RF_INT .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT_BB_SHIFT                                                5
+  #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_0_BB                                                      (0x1<<8) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_0 .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_0_BB_SHIFT                                                8
+  #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_1_BB                                                      (0x1<<9) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_1 .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_1_BB_SHIFT                                                9
+  #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_2_BB                                                      (0x1<<10) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_2 .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_2_BB_SHIFT                                                10
+  #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_3_BB                                                      (0x1<<11) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_3 .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_3_BB_SHIFT                                                11
+  #define PCIE_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_1_BB                                                      (0x1<<12) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY_1 .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_1_BB_SHIFT                                                12
+  #define PCIE_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_2_BB                                                      (0x1<<13) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY_2 .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_2_BB_SHIFT                                                13
+  #define PCIE_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_1_BB                                                      (0x1<<14) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY_1 .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_1_BB_SHIFT                                                14
+  #define PCIE_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_2_BB                                                      (0x1<<15) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY_2 .
+  #define PCIE_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_2_BB_SHIFT                                                15
+#define PCIE_REG_MEM_ECC_ENABLE_0                                                                            0x054010UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PCIE_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_BB                                                       (0x1<<4) // Enable ECC for memory ecc instance pcie_top_wrapper.u_debug_mem.i_ecc in module pcie_debug_mem_e4
+  #define PCIE_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_BB_SHIFT                                                 4
+  #define PCIE_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_K2_E5                                                    (0x1<<0) // Enable ECC for memory ecc instance pcie_top_wrapper.i_ram_1p_rbuf.i_ecc in module ram_1p_rbuf
+  #define PCIE_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_K2_E5_SHIFT                                              0
+  #define PCIE_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_K2_E5                                                    (0x1<<1) // Enable ECC for memory ecc instance pcie_top_wrapper.i_ram_2p_sotbuf.i_ecc in module ram_2p_sotbuf
+  #define PCIE_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_K2_E5_SHIFT                                              1
+  #define PCIE_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_BB                                                       (0x1<<0) // Enable ECC for memory ecc instance pcie_top_wrapper.u_d2t_fifo.i_ecc in module d2t_fifo_e4
+  #define PCIE_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_BB_SHIFT                                                 0
+  #define PCIE_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_BB                                                       (0x1<<1) // Enable ECC for memory ecc instance pcie_top_wrapper.u_header_mem.i_ecc in module header_log_mem_e4
+  #define PCIE_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_BB_SHIFT                                                 1
+  #define PCIE_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_EN_BB                                                       (0x1<<2) // Enable ECC for memory ecc instance pcie_top_wrapper.u_tlda_mem.i_ecc in module pcie_tlda_mem_e4
+  #define PCIE_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_EN_BB_SHIFT                                                 2
+  #define PCIE_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_EN_BB                                                       (0x1<<3) // Enable ECC for memory ecc instance pcie_top_wrapper.u_tlda2_mem.i_ecc in module pcie_tlda_mem_e4
+  #define PCIE_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_EN_BB_SHIFT                                                 3
+  #define PCIE_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_EN_BB                                                       (0x1<<5) // Enable ECC for memory ecc instance pcie_top_wrapper.u_replay_data_mem.i_ecc in module pcie_replay_e4
+  #define PCIE_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_EN_BB_SHIFT                                                 5
+#define PCIE_REG_MEM_ECC_PARITY_ONLY_0                                                                       0x054014UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PCIE_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_BB                                                (0x1<<4) // Set parity only for memory ecc instance pcie_top_wrapper.u_debug_mem.i_ecc in module pcie_debug_mem_e4
+  #define PCIE_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_BB_SHIFT                                          4
+  #define PCIE_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_K2_E5                                             (0x1<<0) // Set parity only for memory ecc instance pcie_top_wrapper.i_ram_1p_rbuf.i_ecc in module ram_1p_rbuf
+  #define PCIE_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_K2_E5_SHIFT                                       0
+  #define PCIE_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_K2_E5                                             (0x1<<1) // Set parity only for memory ecc instance pcie_top_wrapper.i_ram_2p_sotbuf.i_ecc in module ram_2p_sotbuf
+  #define PCIE_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_K2_E5_SHIFT                                       1
+  #define PCIE_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_BB                                                (0x1<<0) // Set parity only for memory ecc instance pcie_top_wrapper.u_d2t_fifo.i_ecc in module d2t_fifo_e4
+  #define PCIE_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_BB_SHIFT                                          0
+  #define PCIE_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_BB                                                (0x1<<1) // Set parity only for memory ecc instance pcie_top_wrapper.u_header_mem.i_ecc in module header_log_mem_e4
+  #define PCIE_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_BB_SHIFT                                          1
+  #define PCIE_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_PRTY_BB                                                (0x1<<2) // Set parity only for memory ecc instance pcie_top_wrapper.u_tlda_mem.i_ecc in module pcie_tlda_mem_e4
+  #define PCIE_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_PRTY_BB_SHIFT                                          2
+  #define PCIE_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_PRTY_BB                                                (0x1<<3) // Set parity only for memory ecc instance pcie_top_wrapper.u_tlda2_mem.i_ecc in module pcie_tlda_mem_e4
+  #define PCIE_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_PRTY_BB_SHIFT                                          3
+  #define PCIE_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_PRTY_BB                                                (0x1<<5) // Set parity only for memory ecc instance pcie_top_wrapper.u_replay_data_mem.i_ecc in module pcie_replay_e4
+  #define PCIE_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_PRTY_BB_SHIFT                                          5
+#define PCIE_REG_MEM_ECC_ERROR_CORRECTED_0                                                                   0x054018UL //Access:RC   DataWidth:0x2    // Multi Field Register.
+  #define PCIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_BB                                         (0x1<<4) // Record if a correctable error occurred on memory ecc instance pcie_top_wrapper.u_debug_mem.i_ecc in module pcie_debug_mem_e4
+  #define PCIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_BB_SHIFT                                   4
+  #define PCIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_K2_E5                                      (0x1<<0) // Record if a correctable error occurred on memory ecc instance pcie_top_wrapper.i_ram_1p_rbuf.i_ecc in module ram_1p_rbuf
+  #define PCIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_K2_E5_SHIFT                                0
+  #define PCIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_K2_E5                                      (0x1<<1) // Record if a correctable error occurred on memory ecc instance pcie_top_wrapper.i_ram_2p_sotbuf.i_ecc in module ram_2p_sotbuf
+  #define PCIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_K2_E5_SHIFT                                1
+  #define PCIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_BB                                         (0x1<<0) // Record if a correctable error occurred on memory ecc instance pcie_top_wrapper.u_d2t_fifo.i_ecc in module d2t_fifo_e4
+  #define PCIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_BB_SHIFT                                   0
+  #define PCIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_BB                                         (0x1<<1) // Record if a correctable error occurred on memory ecc instance pcie_top_wrapper.u_header_mem.i_ecc in module header_log_mem_e4
+  #define PCIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_BB_SHIFT                                   1
+  #define PCIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_CORRECT_BB                                         (0x1<<2) // Record if a correctable error occurred on memory ecc instance pcie_top_wrapper.u_tlda_mem.i_ecc in module pcie_tlda_mem_e4
+  #define PCIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_CORRECT_BB_SHIFT                                   2
+  #define PCIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_CORRECT_BB                                         (0x1<<3) // Record if a correctable error occurred on memory ecc instance pcie_top_wrapper.u_tlda2_mem.i_ecc in module pcie_tlda_mem_e4
+  #define PCIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_CORRECT_BB_SHIFT                                   3
+  #define PCIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_CORRECT_BB                                         (0x1<<5) // Record if a correctable error occurred on memory ecc instance pcie_top_wrapper.u_replay_data_mem.i_ecc in module pcie_replay_e4
+  #define PCIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_CORRECT_BB_SHIFT                                   5
+#define PCIE_REG_MEM_ECC_EVENTS                                                                              0x05401cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define PCIE_REG_ECO_RESERVED                                                                                0x054200UL //Access:RW   DataWidth:0x20   // Eco reserved register.
+#define PCIE_REG_PCIE_CONTROL_BITS                                                                           0x054204UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define PCIE_REG_PCIE_CONTROL_BITS_USER_L1_ENTER                                                           (0x1<<2) // Set to enter L1 state.
+  #define PCIE_REG_PCIE_CONTROL_BITS_USER_L1_ENTER_SHIFT                                                     2
+  #define PCIE_REG_PCIE_CONTROL_BITS_USER_L23_REQ                                                            (0x1<<3) // Set to request entry to L23 state (app_ready_entr_l23).
+  #define PCIE_REG_PCIE_CONTROL_BITS_USER_L23_REQ_SHIFT                                                      3
+  #define PCIE_REG_PCIE_CONTROL_BITS_USER_SEND_LTR1                                                          (0x1<<4) // Set to send LTR1.
+  #define PCIE_REG_PCIE_CONTROL_BITS_USER_SEND_LTR1_SHIFT                                                    4
+  #define PCIE_REG_PCIE_CONTROL_BITS_USER_RC_MODE_BB                                                         (0x1<<0) // Set to enter Root Controller Mode.
+  #define PCIE_REG_PCIE_CONTROL_BITS_USER_RC_MODE_BB_SHIFT                                                   0
+  #define PCIE_REG_PCIE_CONTROL_BITS_USER_ALLOW_GEN3_BB                                                      (0x1<<1) // Set to allow Gen3 mode.
+  #define PCIE_REG_PCIE_CONTROL_BITS_USER_ALLOW_GEN3_BB_SHIFT                                                1
+  #define PCIE_REG_PCIE_CONTROL_BITS_USER_STOP_L1SUB_BB                                                      (0x1<<5) // Stop L1Sub control bit.
+  #define PCIE_REG_PCIE_CONTROL_BITS_USER_STOP_L1SUB_BB_SHIFT                                                5
+#define PCIE_REG_PCIE_STATUS_BITS                                                                            0x054208UL //Access:R    DataWidth:0x9    // Multi Field Register.
+  #define PCIE_REG_PCIE_STATUS_BITS_LINK_IN_L0                                                               (0x1<<1) // Link in L0 Status bit.
+  #define PCIE_REG_PCIE_STATUS_BITS_LINK_IN_L0_SHIFT                                                         1
+  #define PCIE_REG_PCIE_STATUS_BITS_LINK_IN_L23                                                              (0x1<<4) // Link in L23 Status bit.
+  #define PCIE_REG_PCIE_STATUS_BITS_LINK_IN_L23_SHIFT                                                        4
+  #define PCIE_REG_PCIE_STATUS_BITS_PTM_ATTN_BB                                                              (0x1<<0) // Timesynch Data is ready in PCIE FIFO.
+  #define PCIE_REG_PCIE_STATUS_BITS_PTM_ATTN_BB_SHIFT                                                        0
+  #define PCIE_REG_PCIE_STATUS_BITS_LINK_IN_L11_BB                                                           (0x1<<2) // Link in L11 Status bit.
+  #define PCIE_REG_PCIE_STATUS_BITS_LINK_IN_L11_BB_SHIFT                                                     2
+  #define PCIE_REG_PCIE_STATUS_BITS_LINK_IN_L12_BB                                                           (0x1<<3) // Link in L12 Status bit.
+  #define PCIE_REG_PCIE_STATUS_BITS_LINK_IN_L12_BB_SHIFT                                                     3
+  #define PCIE_REG_PCIE_STATUS_BITS_LNK_PHY_DEVICE_TYPE_BB                                                   (0x7<<5) // Phy Device Type.
+  #define PCIE_REG_PCIE_STATUS_BITS_LNK_PHY_DEVICE_TYPE_BB_SHIFT                                             5
+  #define PCIE_REG_PCIE_STATUS_BITS_PHY_PLL_LOCK_BB                                                          (0x1<<8) // PLL Lock status bit.
+  #define PCIE_REG_PCIE_STATUS_BITS_PHY_PLL_LOCK_BB_SHIFT                                                    8
+#define PCIE_REG_PCIE_DEBUG_BITS                                                                             0x05420cUL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PCIE_REG_PCIE_DEBUG_BITS_SPLITTBL_TL_PERR                                                          (0x1<<0) // Force Parity Error on Split Table memory.
+  #define PCIE_REG_PCIE_DEBUG_BITS_SPLITTBL_TL_PERR_SHIFT                                                    0
+  #define PCIE_REG_PCIE_DEBUG_BITS_TIMERTBL_TL_PERR                                                          (0x1<<1) // Force Parity Error on Timer Table memory.
+  #define PCIE_REG_PCIE_DEBUG_BITS_TIMERTBL_TL_PERR_SHIFT                                                    1
+#define PCIE_REG_SOFT_RESET_CONTROL_K2_E5                                                                    0x054210UL //Access:RW   DataWidth:0x7    // Multi Field Register.
+  #define PCIE_REG_SOFT_RESET_CONTROL_APP_INIT_RST_K2_E5                                                     (0x1<<0) // 
+  #define PCIE_REG_SOFT_RESET_CONTROL_APP_INIT_RST_K2_E5_SHIFT                                               0
+  #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_WAKE_REF_RST_N_K2_E5                                              (0x1<<1) // 
+  #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_WAKE_REF_RST_N_K2_E5_SHIFT                                        1
+  #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_SQUELCH_RST_N_K2_E5                                               (0x1<<2) // 
+  #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_SQUELCH_RST_N_K2_E5_SHIFT                                         2
+  #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_STICKY_RST_N_K2_E5                                                (0x1<<3) // 
+  #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_STICKY_RST_N_K2_E5_SHIFT                                          3
+  #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_NON_STICKY_RST_N_K2_E5                                            (0x1<<4) // 
+  #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_NON_STICKY_RST_N_K2_E5_SHIFT                                      4
+  #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_CORE_RST_N_K2_E5                                                  (0x1<<5) // 
+  #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_CORE_RST_N_K2_E5_SHIFT                                            5
+  #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_PIPE_RST_N_K2_E5                                                  (0x1<<6) // 
+  #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_PIPE_RST_N_K2_E5_SHIFT                                            6
+#define PCIE_REG_OBFF_CONTROL_1_K2_E5                                                                        0x054214UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PCIE_REG_OBFF_CONTROL_1_RECEIVEDREQUEST_K2_E5                                                      (0x1<<0) // 
+  #define PCIE_REG_OBFF_CONTROL_1_RECEIVEDREQUEST_K2_E5_SHIFT                                                0
+  #define PCIE_REG_OBFF_CONTROL_1_OBFFSIGNALENABLE_K2_E5                                                     (0x1<<1) // This bit is set by firmware when host system sets OBFF Enable to 2'b11. Firmware must clear this bit when the host changes OBFF Enable from 2'b11 to any other value
+  #define PCIE_REG_OBFF_CONTROL_1_OBFFSIGNALENABLE_K2_E5_SHIFT                                               1
+  #define PCIE_REG_OBFF_CONTROL_1_OBFFWAKEPOLARITY_K2_E5                                                     (0x1<<2) // Set to 1 to indicate that the pcore WakeIn input is active high. This bit should only be set in the event a workaround is required.
+  #define PCIE_REG_OBFF_CONTROL_1_OBFFWAKEPOLARITY_K2_E5_SHIFT                                               2
+  #define PCIE_REG_OBFF_CONTROL_1_DISABLECPUACTIVEFORCING_K2_E5                                              (0x1<<3) // Set to 1 to prevent incoming Request TLPs from forcing the OBFF state to CPU Active.
+  #define PCIE_REG_OBFF_CONTROL_1_DISABLECPUACTIVEFORCING_K2_E5_SHIFT                                        3
+  #define PCIE_REG_OBFF_CONTROL_1_MINIMUMWAKEFALLINGEDGEDELAY_K2_E5                                          (0xffff<<4) // Minimum Wake Falling Edge Delay(this reset value is a count value based on 2ns clock period, for a time value of 700ns)
+  #define PCIE_REG_OBFF_CONTROL_1_MINIMUMWAKEFALLINGEDGEDELAY_K2_E5_SHIFT                                    4
+#define PCIE_REG_OBFF_CONTROL_2_K2_E5                                                                        0x054218UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PCIE_REG_OBFF_CONTROL_2_MINIMUMWAKEPULSEWIDTH_K2_E5                                                (0xffff<<0) // Minimum Wake Pulse Width (this reset value is a count value based on 2ns clock period, for a time value of 200ns)
+  #define PCIE_REG_OBFF_CONTROL_2_MINIMUMWAKEPULSEWIDTH_K2_E5_SHIFT                                          0
+  #define PCIE_REG_OBFF_CONTROL_2_MAXIMUMWAKEPULSEWIDTH_K2_E5                                                (0xffff<<16) // Maximum Wake Pulse Width (this reset value is a count value based on 2ns clock period, for a time value of 600ns)
+  #define PCIE_REG_OBFF_CONTROL_2_MAXIMUMWAKEPULSEWIDTH_K2_E5_SHIFT                                          16
+#define PCIE_REG_OBFF_STATUS_1_K2_E5                                                                         0x05421cUL //Access:R    DataWidth:0x14   // Multi Field Register.
+  #define PCIE_REG_OBFF_STATUS_1_RXOBFFUPDATE_K2_E5                                                          (0x1<<0) // 
+  #define PCIE_REG_OBFF_STATUS_1_RXOBFFUPDATE_K2_E5_SHIFT                                                    0
+  #define PCIE_REG_OBFF_STATUS_1_RXOBFFCODE_K2_E5                                                            (0xf<<1) // 
+  #define PCIE_REG_OBFF_STATUS_1_RXOBFFCODE_K2_E5_SHIFT                                                      1
+  #define PCIE_REG_OBFF_STATUS_1_RXOBFFEXCEPTION_K2_E5                                                       (0x1<<5) // 
+  #define PCIE_REG_OBFF_STATUS_1_RXOBFFEXCEPTION_K2_E5_SHIFT                                                 5
+  #define PCIE_REG_OBFF_STATUS_1_WAKESAMPLESTATE_K2_E5                                                       (0x1f<<6) // 
+  #define PCIE_REG_OBFF_STATUS_1_WAKESAMPLESTATE_K2_E5_SHIFT                                                 6
+  #define PCIE_REG_OBFF_STATUS_1_MINIMUMWAKEFALLINGEDGEVALID_K2_E5                                           (0x1<<11) // 
+  #define PCIE_REG_OBFF_STATUS_1_MINIMUMWAKEFALLINGEDGEVALID_K2_E5_SHIFT                                     11
+  #define PCIE_REG_OBFF_STATUS_1_MAXIMUMPULSEWIDTHEXPIRE_K2_E5                                               (0x1<<12) // 
+  #define PCIE_REG_OBFF_STATUS_1_MAXIMUMPULSEWIDTHEXPIRE_K2_E5_SHIFT                                         12
+  #define PCIE_REG_OBFF_STATUS_1_MINIMUMPULSEWIDTHREADY_K2_E5                                                (0x1<<13) // 
+  #define PCIE_REG_OBFF_STATUS_1_MINIMUMPULSEWIDTHREADY_K2_E5_SHIFT                                          13
+  #define PCIE_REG_OBFF_STATUS_1_RESTARTWAKEPULSEWIDTHTIMER_K2_E5                                            (0x1<<14) // 
+  #define PCIE_REG_OBFF_STATUS_1_RESTARTWAKEPULSEWIDTHTIMER_K2_E5_SHIFT                                      14
+  #define PCIE_REG_OBFF_STATUS_1_WAKEFALLINGEDGE_K2_E5                                                       (0x1<<15) // 
+  #define PCIE_REG_OBFF_STATUS_1_WAKEFALLINGEDGE_K2_E5_SHIFT                                                 15
+  #define PCIE_REG_OBFF_STATUS_1_WAKERISINGEDGE_K2_E5                                                        (0x1<<16) // 
+  #define PCIE_REG_OBFF_STATUS_1_WAKERISINGEDGE_K2_E5_SHIFT                                                  16
+  #define PCIE_REG_OBFF_STATUS_1_WAKEINSYNC_K2_E5                                                            (0x1<<17) // 
+  #define PCIE_REG_OBFF_STATUS_1_WAKEINSYNC_K2_E5_SHIFT                                                      17
+  #define PCIE_REG_OBFF_STATUS_1_WAKEFALLINGEDGECOUNT_K2_E5                                                  (0x3<<18) // 
+  #define PCIE_REG_OBFF_STATUS_1_WAKEFALLINGEDGECOUNT_K2_E5_SHIFT                                            18
+#define PCIE_REG_OBFF_STATUS_2_K2_E5                                                                         0x054220UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIE_REG_OBFF_STATUS_2_WAKEFALLINGEDGETIMER_K2_E5                                                  (0xffff<<0) // 
+  #define PCIE_REG_OBFF_STATUS_2_WAKEFALLINGEDGETIMER_K2_E5_SHIFT                                            0
+  #define PCIE_REG_OBFF_STATUS_2_WAKEPULSEWIDTHTIMER_K2_E5                                                   (0xffff<<16) // 
+  #define PCIE_REG_OBFF_STATUS_2_WAKEPULSEWIDTHTIMER_K2_E5_SHIFT                                             16
+#define PCIE_REG_LTR_CONTROL_LATENCY_0_K2_E5                                                                 0x054224UL //Access:RW   DataWidth:0x20   // 32 bit value to be sent in LTR message
+#define PCIE_REG_LTR_CONTROL_LATENCY_1_K2_E5                                                                 0x054228UL //Access:RW   DataWidth:0x20   // 32 bit value to be sent in LTR message
+#define PCIE_REG_LTR_STATUS_LATENCY_K2_E5                                                                    0x05422cUL //Access:R    DataWidth:0x20   // LTR latency value being sent in LTR messages
+#define PCIE_REG_LTR_CONTROL_K2_E5                                                                           0x054230UL //Access:RW   DataWidth:0x4    // Function number associated with the LTR message
+#define PCIE_REG_LTR_STATUS_K2_E5                                                                            0x054234UL //Access:R    DataWidth:0x1    // 
+#define PCIE_REG_SII_LANE_FLIP_CONTROL_K2_E5                                                                 0x054238UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PCIE_REG_SII_LANE_FLIP_CONTROL_RX_LANE_FLIP_EN_K2_E5                                               (0x1<<0) // Performs manual lane reversal for receive lanes.
+  #define PCIE_REG_SII_LANE_FLIP_CONTROL_RX_LANE_FLIP_EN_K2_E5_SHIFT                                         0
+  #define PCIE_REG_SII_LANE_FLIP_CONTROL_TX_LANE_FLIP_EN_K2_E5                                               (0x1<<1) // Performs manual lane reversal for transmit lanes.
+  #define PCIE_REG_SII_LANE_FLIP_CONTROL_TX_LANE_FLIP_EN_K2_E5_SHIFT                                         1
+#define PCIE_REG_APP_LTSSM_ENABLE_K2_E5                                                                      0x05423cUL //Access:RW   DataWidth:0x1    // Driven low by your application after cold, warm or hot reset to hold the LTSSM in the Detect state until your application is ready for the link training to begin. When your application has finished reprogramming the core configuration registers using the DBI, it asserts app_ltssm_enable to allow the LTSSM to continue link establishment. Can also be used to delay hot resetting of the core until you have read out any register status.
+#define PCIE_REG_HW_INIT_CONFIG_K2_E5                                                                        0x054240UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PCIE_REG_HW_INIT_CONFIG_APP_LTSSM_ENABLE_OVR_K2_E5                                                 (0x1<<0) // When set to 0, HWInit controls app_ltssm_enable
+  #define PCIE_REG_HW_INIT_CONFIG_APP_LTSSM_ENABLE_OVR_K2_E5_SHIFT                                           0
+  #define PCIE_REG_HW_INIT_CONFIG_HOT_RESET_PRE_DELAY_ENABLE_K2_E5                                           (0x1<<1) // When set to 1, HW delay asserting internal reset to allow FW access to internal registers
+  #define PCIE_REG_HW_INIT_CONFIG_HOT_RESET_PRE_DELAY_ENABLE_K2_E5_SHIFT                                     1
+#define PCIE_REG_SII_CORE_CONTROL_K2_E5                                                                      0x054244UL //Access:RW   DataWidth:0x1    // 
+#define PCIE_REG_CLK_RST_APM_CONTROL_K2_E5                                                                   0x054248UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define PCIE_REG_CLK_RST_APM_CONTROL_APP_CLK_REQ_N_K2_E5                                                   (0x1<<0) // Indicates that the application logic is ready to have reference clock removed.
+  #define PCIE_REG_CLK_RST_APM_CONTROL_APP_CLK_REQ_N_K2_E5_SHIFT                                             0
+  #define PCIE_REG_CLK_RST_APM_CONTROL_PHY_CLK_REQ_N_K2_E5                                                   (0x1<<1) // Acknowledge from the PHY that it is ready to have reference clock removed.
+  #define PCIE_REG_CLK_RST_APM_CONTROL_PHY_CLK_REQ_N_K2_E5_SHIFT                                             1
+  #define PCIE_REG_CLK_RST_APM_CONTROL_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN_K2_E5                          (0x1<<2) // While in L1 enable AUX clock to switch from PCLK to free running external clock.
+  #define PCIE_REG_CLK_RST_APM_CONTROL_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN_K2_E5_SHIFT                    2
+#define PCIE_REG_CLK_RST_APM_STATUS_K2_E5                                                                    0x05424cUL //Access:R    DataWidth:0xb    // Multi Field Register.
+  #define PCIE_REG_CLK_RST_APM_STATUS_MAC_PHY_CLK_REQ_N_K2_E5                                                (0x1<<0) // Indicates to the PHY that MAC and application is ready to remove the clock. PHY can decide whether or not it will allow reference clock removal if it supports this feature
+  #define PCIE_REG_CLK_RST_APM_STATUS_MAC_PHY_CLK_REQ_N_K2_E5_SHIFT                                          0
+  #define PCIE_REG_CLK_RST_APM_STATUS_CLK_REQ_N_K2_E5                                                        (0x1<<1) // Clock Turnoff request. Allows your application clock generation module to turn off core_clk based the current power management state
+  #define PCIE_REG_CLK_RST_APM_STATUS_CLK_REQ_N_K2_E5_SHIFT                                                  1
+  #define PCIE_REG_CLK_RST_APM_STATUS_LOCAL_REF_CLK_REQ_N_K2_E5                                              (0x1<<2) // 
+  #define PCIE_REG_CLK_RST_APM_STATUS_LOCAL_REF_CLK_REQ_N_K2_E5_SHIFT                                        2
+  #define PCIE_REG_CLK_RST_APM_STATUS_MAC_PHY_RXSTANDBY_K2_E5                                                (0xff<<3) // Indicates whether the PHY RX is active when the PHY is in P0 or P0s.
+  #define PCIE_REG_CLK_RST_APM_STATUS_MAC_PHY_RXSTANDBY_K2_E5_SHIFT                                          3
+#define PCIE_REG_PTM_CONTROL_K2_E5                                                                           0x054250UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PCIE_REG_PTM_CONTROL_PTM_AUTO_UPDATE_SIGNAL_K2_E5                                                  (0x1<<0) // 
+  #define PCIE_REG_PTM_CONTROL_PTM_AUTO_UPDATE_SIGNAL_K2_E5_SHIFT                                            0
+  #define PCIE_REG_PTM_CONTROL_PTM_MANUAL_UPDATE_PULSE_K2_E5                                                 (0x1<<1) // Indicates that the core should update the PTM Requester Context and Clock now. FW must clear this bit after setting this bit to 1.
+  #define PCIE_REG_PTM_CONTROL_PTM_MANUAL_UPDATE_PULSE_K2_E5_SHIFT                                           1
+#define PCIE_REG_PTM_STATUS_K2_E5                                                                            0x054254UL //Access:R    DataWidth:0x2    // Multi Field Register.
+  #define PCIE_REG_PTM_STATUS_PTM_CONTEXT_VALID_K2_E5                                                        (0x1<<0) // 
+  #define PCIE_REG_PTM_STATUS_PTM_CONTEXT_VALID_K2_E5_SHIFT                                                  0
+  #define PCIE_REG_PTM_STATUS_PTM_CLOCK_UPDATED_K2_E5                                                        (0x1<<1) // 
+  #define PCIE_REG_PTM_STATUS_PTM_CLOCK_UPDATED_K2_E5_SHIFT                                                  1
+#define PCIE_REG_PTM_CLOCK_CORRECTION0_K2_E5                                                                 0x054258UL //Access:R    DataWidth:0x20   // 
+#define PCIE_REG_PTM_CLOCK_CORRECTION1_K2_E5                                                                 0x05425cUL //Access:R    DataWidth:0x20   // 
+#define PCIE_REG_PTM_LOCAL_CLOCK0_K2_E5                                                                      0x054260UL //Access:R    DataWidth:0x20   // 
+#define PCIE_REG_PTM_LOCAL_CLOCK1_K2_E5                                                                      0x054264UL //Access:R    DataWidth:0x20   // 
+#define PCIE_REG_PTM_LOCAL_CLOCK0_LATCHED_K2_E5                                                              0x054268UL //Access:R    DataWidth:0x20   // Latched vlaue during nig_pxp_ptm_latch pulse
+#define PCIE_REG_PTM_LOCAL_CLOCK1_LATCHED_K2_E5                                                              0x05426cUL //Access:R    DataWidth:0x20   // Latched vlaue during nig_pxp_ptm_latch pulse
+#define PCIE_REG_RESET_STATUS_1_K2_E5                                                                        0x054270UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PCIE_REG_RESET_STATUS_1_WAKE_REF_RST_N_K2_E5                                                       (0x1<<0) // 
+  #define PCIE_REG_RESET_STATUS_1_WAKE_REF_RST_N_K2_E5_SHIFT                                                 0
+  #define PCIE_REG_RESET_STATUS_1_SQUELCH_RST_N_K2_E5                                                        (0x1<<1) // 
+  #define PCIE_REG_RESET_STATUS_1_SQUELCH_RST_N_K2_E5_SHIFT                                                  1
+  #define PCIE_REG_RESET_STATUS_1_STICKY_RST_N_K2_E5                                                         (0x1<<2) // 
+  #define PCIE_REG_RESET_STATUS_1_STICKY_RST_N_K2_E5_SHIFT                                                   2
+  #define PCIE_REG_RESET_STATUS_1_NON_STICKY_RST_N_K2_E5                                                     (0x1<<3) // 
+  #define PCIE_REG_RESET_STATUS_1_NON_STICKY_RST_N_K2_E5_SHIFT                                               3
+  #define PCIE_REG_RESET_STATUS_1_PIPE_RST_N_K2_E5                                                           (0x1<<4) // 
+  #define PCIE_REG_RESET_STATUS_1_PIPE_RST_N_K2_E5_SHIFT                                                     4
+  #define PCIE_REG_RESET_STATUS_1_SMLH_REQ_RST_NOT_K2_E5                                                     (0x1<<5) // Early version of the link_req_rst_not signal. For more details, see the 'Warm and Hot Resets' section in the Architecture chapter of the Databook.
+  #define PCIE_REG_RESET_STATUS_1_SMLH_REQ_RST_NOT_K2_E5_SHIFT                                               5
+  #define PCIE_REG_RESET_STATUS_1_LINK_REQ_RST_NOT_K2_E5                                                     (0x1<<6) // 
+  #define PCIE_REG_RESET_STATUS_1_LINK_REQ_RST_NOT_K2_E5_SHIFT                                               6
+  #define PCIE_REG_RESET_STATUS_1_TRAINING_RST_N_K2_E5                                                       (0x1<<7) // 
+  #define PCIE_REG_RESET_STATUS_1_TRAINING_RST_N_K2_E5_SHIFT                                                 7
+#define PCIE_REG_LINK_DEBUG_STATUS_K2_E5                                                                     0x054274UL //Access:R    DataWidth:0x12   // Multi Field Register.
+  #define PCIE_REG_LINK_DEBUG_STATUS_SMLH_LINK_UP_K2_E5                                                      (0x1<<0) // 
+  #define PCIE_REG_LINK_DEBUG_STATUS_SMLH_LINK_UP_K2_E5_SHIFT                                                0
+  #define PCIE_REG_LINK_DEBUG_STATUS_RDLH_LINK_UP_K2_E5                                                      (0x1<<1) // 
+  #define PCIE_REG_LINK_DEBUG_STATUS_RDLH_LINK_UP_K2_E5_SHIFT                                                1
+  #define PCIE_REG_LINK_DEBUG_STATUS_SMLH_LTSSM_STATE_K2_E5                                                  (0x3f<<2) // 
+  #define PCIE_REG_LINK_DEBUG_STATUS_SMLH_LTSSM_STATE_K2_E5_SHIFT                                            2
+  #define PCIE_REG_LINK_DEBUG_STATUS_RADM_Q_NOT_EMPTY_K2_E5                                                  (0x1<<8) // Level indicating that the receive queues contain TLP header/data.There is a 1 bit indication for each virtual channel.
+  #define PCIE_REG_LINK_DEBUG_STATUS_RADM_Q_NOT_EMPTY_K2_E5_SHIFT                                            8
+  #define PCIE_REG_LINK_DEBUG_STATUS_CDM_RAS_DES_TBA_INFO_COMMON_K2_E5                                       (0x7f<<9) // Common event signal status bus used in RAS D.E.S. time based analysis
+  #define PCIE_REG_LINK_DEBUG_STATUS_CDM_RAS_DES_TBA_INFO_COMMON_K2_E5_SHIFT                                 9
+  #define PCIE_REG_LINK_DEBUG_STATUS_SMLH_LTSSM_STATE_RCVRY_EQ_K2_E5                                         (0x1<<16) // This status signal is asserted during all Recovery Equalization states
+  #define PCIE_REG_LINK_DEBUG_STATUS_SMLH_LTSSM_STATE_RCVRY_EQ_K2_E5_SHIFT                                   16
+  #define PCIE_REG_LINK_DEBUG_STATUS_CFG_HW_AUTO_SP_DIS_K2_E5                                                (0x1<<17) // Autonomous speed disable. Used in downstream ports only.
+  #define PCIE_REG_LINK_DEBUG_STATUS_CFG_HW_AUTO_SP_DIS_K2_E5_SHIFT                                          17
+#define PCIE_REG_DEBUG_EI_PM_UNLOCK_ERROR_K2_E5                                                              0x054278UL //Access:R    DataWidth:0x12   // Multi Field Register.
+  #define PCIE_REG_DEBUG_EI_PM_UNLOCK_ERROR_CXPL_DEBUG_INFO_EI_K2_E5                                         (0xffff<<0) // State of selected internal signals in relation to electrical idle (EI) at the receiver
+  #define PCIE_REG_DEBUG_EI_PM_UNLOCK_ERROR_CXPL_DEBUG_INFO_EI_K2_E5_SHIFT                                   0
+  #define PCIE_REG_DEBUG_EI_PM_UNLOCK_ERROR_RADM_MSG_UNLOCK_K2_E5                                            (0x1<<16) // One-cycle pulse that indicates that the core received an Unlock message
+  #define PCIE_REG_DEBUG_EI_PM_UNLOCK_ERROR_RADM_MSG_UNLOCK_K2_E5_SHIFT                                      16
+  #define PCIE_REG_DEBUG_EI_PM_UNLOCK_ERROR_RADM_PM_TURNOFF_K2_E5                                            (0x1<<17) // One-clock-cycle pulse that indicates that the core received a PME Turnoff message
+  #define PCIE_REG_DEBUG_EI_PM_UNLOCK_ERROR_RADM_PM_TURNOFF_K2_E5_SHIFT                                      17
+#define PCIE_REG_PCIE_DIAGNOSTIC_CONTROL_K2_E5                                                               0x05427cUL //Access:RW   DataWidth:0x13   // Multi Field Register.
+  #define PCIE_REG_PCIE_DIAGNOSTIC_CONTROL_DIAG_CTRL_BUS_K2_E5                                               (0x7<<0) // Diagnostic Control Bus
+  #define PCIE_REG_PCIE_DIAGNOSTIC_CONTROL_DIAG_CTRL_BUS_K2_E5_SHIFT                                         0
+  #define PCIE_REG_PCIE_DIAGNOSTIC_CONTROL_OUTBAND_PWRUP_CMD_K2_E5                                           (0xffff<<3) // Wake Up. Used by application logic to wake up the PMC state machine from a D1, D2 or D3 power state. Upon wake-up, the core sends a PM_PME Message
+  #define PCIE_REG_PCIE_DIAGNOSTIC_CONTROL_OUTBAND_PWRUP_CMD_K2_E5_SHIFT                                     3
+#define PCIE_REG_POWER_MGMT_STATUS_K2_E5                                                                     0x054280UL //Access:R    DataWidth:0x13   // Multi Field Register.
+  #define PCIE_REG_POWER_MGMT_STATUS_PM_STATUS_K2_E5                                                         (0xffff<<0) // PME Status bit from the PMCSR. There is 1 bit of pm_status for each configured function
+  #define PCIE_REG_POWER_MGMT_STATUS_PM_STATUS_K2_E5_SHIFT                                                   0
+  #define PCIE_REG_POWER_MGMT_STATUS_PM_CURNT_STATE_K2_E5                                                    (0x7<<16) // Indicates the current power state
+  #define PCIE_REG_POWER_MGMT_STATUS_PM_CURNT_STATE_K2_E5_SHIFT                                              16
+#define PCIE_REG_SII_TRANSMIT_CONTROL_K2_E5                                                                  0x054284UL //Access:R    DataWidth:0x14   // Multi Field Register.
+  #define PCIE_REG_SII_TRANSMIT_CONTROL_PM_XTLH_BLOCK_TLP_K2_E5                                              (0x1<<0) // WARNING: this bit should not be used by firmware due to a bug filed in CQ85027. Indicates that your application must stop generating new outgoing request TLPs due to the current power management state.
+  #define PCIE_REG_SII_TRANSMIT_CONTROL_PM_XTLH_BLOCK_TLP_K2_E5_SHIFT                                        0
+  #define PCIE_REG_SII_TRANSMIT_CONTROL_PM_PME_EN_K2_E5                                                      (0xffff<<1) // PME Enable bit in the PMCSR. There is 1 bit of pm_pme_en for each configured function.
+  #define PCIE_REG_SII_TRANSMIT_CONTROL_PM_PME_EN_K2_E5_SHIFT                                                1
+  #define PCIE_REG_SII_TRANSMIT_CONTROL_PM_LINKST_IN_L0S_K2_E5                                               (0x1<<17) // Power management is in L0s state
+  #define PCIE_REG_SII_TRANSMIT_CONTROL_PM_LINKST_IN_L0S_K2_E5_SHIFT                                         17
+  #define PCIE_REG_SII_TRANSMIT_CONTROL_PM_LINKST_IN_L2_K2_E5                                                (0x1<<18) // Power management is in L2 state.
+  #define PCIE_REG_SII_TRANSMIT_CONTROL_PM_LINKST_IN_L2_K2_E5_SHIFT                                          18
+  #define PCIE_REG_SII_TRANSMIT_CONTROL_PM_LINKST_L2_EXIT_K2_E5                                              (0x1<<19) // Power management is exiting L2 state.
+  #define PCIE_REG_SII_TRANSMIT_CONTROL_PM_LINKST_L2_EXIT_K2_E5_SHIFT                                        19
+#define PCIE_REG_SII_CONFIG_INFO_K2_E5                                                                       0x054288UL //Access:R    DataWidth:0x11   // Multi Field Register.
+  #define PCIE_REG_SII_CONFIG_INFO_CFG_PM_NO_SOFT_RST_K2_E5                                                  (0xffff<<0) // This is the value of the No Soft Reset bit in the Power Management Control and Status Register
+  #define PCIE_REG_SII_CONFIG_INFO_CFG_PM_NO_SOFT_RST_K2_E5_SHIFT                                            0
+  #define PCIE_REG_SII_CONFIG_INFO_CFG_LTR_M_EN_K2_E5                                                        (0x1<<16) // The LTR Mechanism Enable field of the Device Control 2 register of function 0
+  #define PCIE_REG_SII_CONFIG_INFO_CFG_LTR_M_EN_K2_E5_SHIFT                                                  16
+#define PCIE_REG_SII_INTERRUPT_PM_STATUS_K2_E5                                                               0x05428cUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PCIE_REG_SII_INTERRUPT_PM_STATUS_AUX_PM_EN_K2_E5                                                   (0xffff<<0) // Auxiliary Power Enable bit in the Device Control register. There is 1 bit of aux_pm_en for each configured function.
+  #define PCIE_REG_SII_INTERRUPT_PM_STATUS_AUX_PM_EN_K2_E5_SHIFT                                             0
+  #define PCIE_REG_SII_INTERRUPT_PM_STATUS_CFG_INT_DISABLE_K2_E5                                             (0xffff<<16) // When high a functions ability to generate INTx messages is Disabled
+  #define PCIE_REG_SII_INTERRUPT_PM_STATUS_CFG_INT_DISABLE_K2_E5_SHIFT                                       16
+#define PCIE_REG_RAS_DES_TBA_CONTROL_K2_E5                                                                   0x054290UL //Access:RW   DataWidth:0x2    // Controls the start/end of time based analysis. You must only set the pins to the required value for the duration of one clock cycle
+#define PCIE_REG_SII_DEBUG_0_K2_E5                                                                           0x054294UL //Access:R    DataWidth:0x20   // State of selected internal signals, for debugging purposes only
+#define PCIE_REG_SII_DEBUG_1_K2_E5                                                                           0x054298UL //Access:R    DataWidth:0x20   // State of selected internal signals, for debugging purposes only
+#define PCIE_REG_RAS_DES_SILICON_DEBUG_0_K2_E5                                                               0x05429cUL //Access:R    DataWidth:0x20   // Common debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_SILICON_DEBUG_1_K2_E5                                                               0x0542a0UL //Access:R    DataWidth:0x20   // Common debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_SILICON_DEBUG_2_K2_E5                                                               0x0542a4UL //Access:R    DataWidth:0xb    // Common debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_DEBUG_LANE0_0_K2_E5                                                                 0x0542a8UL //Access:R    DataWidth:0x20   // Lane0 debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_DEBUG_LANE0_1_K2_E5                                                                 0x0542acUL //Access:R    DataWidth:0x20   // Lane0 debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_DEBUG_LANE0_2_K2_E5                                                                 0x0542b0UL //Access:R    DataWidth:0xe    // Lane0 debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_DEBUG_LANE1_0_K2_E5                                                                 0x0542b4UL //Access:R    DataWidth:0x20   // Lane1 debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_DEBUG_LANE1_1_K2_E5                                                                 0x0542b8UL //Access:R    DataWidth:0x20   // Lane1 debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_DEBUG_LANE1_2_K2_E5                                                                 0x0542bcUL //Access:R    DataWidth:0xe    // Lane1 debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_DEBUG_LANE2_0_K2_E5                                                                 0x0542c0UL //Access:R    DataWidth:0x20   // Lane2 debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_DEBUG_LANE2_1_K2_E5                                                                 0x0542c4UL //Access:R    DataWidth:0x20   // Lane2 debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_DEBUG_LANE2_2_K2_E5                                                                 0x0542c8UL //Access:R    DataWidth:0xe    // Lane2 debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_DEBUG_LANE3_0_K2_E5                                                                 0x0542ccUL //Access:R    DataWidth:0x20   // Lane3 debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_DEBUG_LANE3_1_K2_E5                                                                 0x0542d0UL //Access:R    DataWidth:0x20   // Lane3 debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_DEBUG_LANE3_2_K2_E5                                                                 0x0542d4UL //Access:R    DataWidth:0xe    // Lane3 debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_DEBUG_LANE4_0_K2_E5                                                                 0x0542d8UL //Access:R    DataWidth:0x20   // Lane4 debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_DEBUG_LANE4_1_K2_E5                                                                 0x0542dcUL //Access:R    DataWidth:0x20   // Lane4 debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_DEBUG_LANE4_2_K2_E5                                                                 0x0542e0UL //Access:R    DataWidth:0xe    // Lane4 debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_DEBUG_LANE5_0_K2_E5                                                                 0x0542e4UL //Access:R    DataWidth:0x20   // Lane5 debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_DEBUG_LANE5_1_K2_E5                                                                 0x0542e8UL //Access:R    DataWidth:0x20   // Lane5 debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_DEBUG_LANE5_2_K2_E5                                                                 0x0542ecUL //Access:R    DataWidth:0xe    // Lane5 debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_DEBUG_LANE6_0_K2_E5                                                                 0x0542f0UL //Access:R    DataWidth:0x20   // Lane6 debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_DEBUG_LANE6_1_K2_E5                                                                 0x0542f4UL //Access:R    DataWidth:0x20   // Lane6 debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_DEBUG_LANE6_2_K2_E5                                                                 0x0542f8UL //Access:R    DataWidth:0xe    // Lane6 debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_DEBUG_LANE7_0_K2_E5                                                                 0x0542fcUL //Access:R    DataWidth:0x20   // Lane7 debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_DEBUG_LANE7_1_K2_E5                                                                 0x054300UL //Access:R    DataWidth:0x20   // Lane7 debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_DEBUG_LANE7_2_K2_E5                                                                 0x054304UL //Access:R    DataWidth:0xe    // Lane7 debug signal bus that is used in RAS D.E.S. silicon debug
+#define PCIE_REG_RAS_DES_SD_INFO_V0_0_K2_E5                                                                  0x054308UL //Access:R    DataWidth:0x20   // VC0 debug signal bus that is used in RAS D.E.S. silicon debug.
+#define PCIE_REG_RAS_DES_SD_INFO_V0_1_K2_E5                                                                  0x05430cUL //Access:R    DataWidth:0x20   // VC0 debug signal bus that is used in RAS D.E.S. silicon debug.
+#define PCIE_REG_RAS_DES_SD_INFO_V0_2_K2_E5                                                                  0x054310UL //Access:R    DataWidth:0x20   // VC0 debug signal bus that is used in RAS D.E.S. silicon debug.
+#define PCIE_REG_RAS_DES_SD_INFO_V0_3_K2_E5                                                                  0x054314UL //Access:R    DataWidth:0x20   // VC0 debug signal bus that is used in RAS D.E.S. silicon debug.
+#define PCIE_REG_RAS_DES_SD_INFO_V0_4_K2_E5                                                                  0x054318UL //Access:R    DataWidth:0x20   // VC0 debug signal bus that is used in RAS D.E.S. silicon debug.
+#define PCIE_REG_RAS_DES_SD_INFO_V0_5_K2_E5                                                                  0x05431cUL //Access:R    DataWidth:0x20   // VC0 debug signal bus that is used in RAS D.E.S. silicon debug.
+#define PCIE_REG_RAS_DES_SD_INFO_V0_6_K2_E5                                                                  0x054320UL //Access:R    DataWidth:0x20   // VC0 debug signal bus that is used in RAS D.E.S. silicon debug.
+#define PCIE_REG_RAS_DES_SD_INFO_V0_7_K2_E5                                                                  0x054324UL //Access:R    DataWidth:0x10   // VC0 debug signal bus that is used in RAS D.E.S. silicon debug.
+#define PCIE_REG_PM_DEV_NUM_K2_E5                                                                            0x054328UL //Access:R    DataWidth:0x5    // pm_dev_num[4:0]- Device number
+#define PCIE_REG_PM_BUS_NUM_K2_E5                                                                            0x05432cUL //Access:R    DataWidth:0x8    // pm_bus_num[7:0]- Bus Number
+#define PCIE_REG_PHY_CFG_STATUS_K2_E5                                                                        0x054330UL //Access:RW   DataWidth:0x20   // SNPS core input bus that can optionally be used to read PHY status. The phy_cfg_status bus maps to the PHY Status register.
+#define PCIE_REG_CFG_PHY_CONTROL_K2_E5                                                                       0x054334UL //Access:R    DataWidth:0x20   // Output bus that can optionally be used for additional PHY control purposes. The cfg_phy_control bus maps to the PHY Control register
+#define PCIE_REG_LTSSM_MATCH_STATE_K2_E5                                                                     0x054338UL //Access:RW   DataWidth:0x6    // Target LTSSM state for the LTSSM State matched event
+#define PCIE_REG_POWER_BUDGET_TABLE_DATA_0_K2_E5                                                             0x05433cUL //Access:RW   DataWidth:0x15   // Power Budget Table entry 0
+#define PCIE_REG_POWER_BUDGET_TABLE_DATA_1_K2_E5                                                             0x054340UL //Access:RW   DataWidth:0x15   // Power Budget Table entry 1
+#define PCIE_REG_POWER_BUDGET_TABLE_DATA_2_K2_E5                                                             0x054344UL //Access:RW   DataWidth:0x15   // Power Budget Table entry 2
+#define PCIE_REG_POWER_BUDGET_TABLE_DATA_3_K2_E5                                                             0x054348UL //Access:RW   DataWidth:0x15   // Power Budget Table entry 3
+#define PCIE_REG_POWER_BUDGET_TABLE_DATA_4_K2_E5                                                             0x05434cUL //Access:RW   DataWidth:0x15   // Power Budget Table entry 4
+#define PCIE_REG_POWER_BUDGET_TABLE_DATA_5_K2_E5                                                             0x054350UL //Access:RW   DataWidth:0x15   // Power Budget Table entry 5
+#define PCIE_REG_POWER_BUDGET_TABLE_DATA_6_K2_E5                                                             0x054354UL //Access:RW   DataWidth:0x15   // Power Budget Table entry 6
+#define PCIE_REG_POWER_BUDGET_TABLE_DATA_7_K2_E5                                                             0x054358UL //Access:RW   DataWidth:0x15   // Power Budget Table entry 7
+#define PCIE_REG_DBG_ALMOST_FULL_THRESHOLD_K2_E5                                                             0x05435cUL //Access:RW   DataWidth:0x4    // 
+#define PCIE_REG_DBG_SAMPLING_INTERVAL_K2_E5                                                                 0x054360UL //Access:RW   DataWidth:0x14   // Sampling interval * pclk, 2ns to 2ms.
+#define PCIE_REG_DBG_REPEAT_THRESHOLD_COUNT_K2_E5                                                            0x054364UL //Access:RW   DataWidth:0x4    // If 0 or 1, trigger on first occurrence. If greater than 1, wait until counter value match to trigger.
+#define PCIE_REG_DBG_POST_TRIGGER_LATENCY_COUNT_K2_E5                                                        0x054368UL //Access:RW   DataWidth:0x18   // If greater than 0, delay trigger count value * pclk, 0 to 32ms
+#define PCIE_REG_DBG_FW_TRIGGER_ENABLE_K2_E5                                                                 0x05436cUL //Access:RW   DataWidth:0x1    // 
+#define PCIE_REG_DBG_LANE_MATCH_ENABLE_K2_E5                                                                 0x054370UL //Access:RW   DataWidth:0x8    // 
+#define PCIE_REG_DBG_AUX_CORE_CLK_SWITCH_TRIGGER_ENABLE_K2_E5                                                0x054374UL //Access:RW   DataWidth:0x1    // 
+#define PCIE_REG_DBG_LTSSM_MATCH_TRIGGER_ENABLE_K2_E5                                                        0x054378UL //Access:RW   DataWidth:0x1    // 
+#define PCIE_REG_DBG_LTSSM_MATCH_VALUE_K2_E5                                                                 0x05437cUL //Access:RW   DataWidth:0x6    // 
+#define PCIE_REG_DBG_RX_ALIGN_LOSS_TRIGGER_ENABLE_K2_E5                                                      0x054380UL //Access:RW   DataWidth:0x1    // 
+#define PCIE_REG_DBG_EI_ENTRY_TRIGGER_ENABLE_K2_E5                                                           0x054384UL //Access:RW   DataWidth:0x1    // 
+#define PCIE_REG_DBG_EI_EXIT_TRIGGER_ENABLE_K2_E5                                                            0x054388UL //Access:RW   DataWidth:0x1    // 
+#define PCIE_REG_DBG_RATE_CHANGE_TRIGGER_ENABLE_K2_E5                                                        0x05438cUL //Access:RW   DataWidth:0x1    // 
+#define PCIE_REG_DBG_LINK_WIDTH_CHANGE_TRIGGER_ENABLE_K2_E5                                                  0x054390UL //Access:RW   DataWidth:0x1    // 
+#define PCIE_REG_DBG_CORRECTABLE_ERROR_TRIGGER_ENABLE_K2_E5                                                  0x054394UL //Access:RW   DataWidth:0x1    // 
+#define PCIE_REG_DBG_COMMON_SELECT_K2_E5                                                                     0x054398UL //Access:RW   DataWidth:0x8    // 
+#define PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5                                                               0x05439cUL //Access:RW   DataWidth:0x4    // 
+#define PCIE_REG_DBG_COMMON_SHIFT_K2_E5                                                                      0x0543a0UL //Access:RW   DataWidth:0x2    // 
+#define PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5                                                                0x0543a4UL //Access:RW   DataWidth:0x4    // 
+#define PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5                                                                0x0543a8UL //Access:RW   DataWidth:0x4    // 
+#define PCIE_REG_DBG_STATUS_K2_E5                                                                            0x0543acUL //Access:R    DataWidth:0x5    // 
+#define PCIE_REG_MSIX_SYNCH_START_K2_E5                                                                      0x0543b0UL //Access:RW   DataWidth:0x1    // Need to write on init to start MSIX synchronization.
+#define PCIE_REG_MSIX_SYNCH_STICKY_K2_E5                                                                     0x0543b4UL //Access:RC   DataWidth:0x1    // Is set to 1 if at least 1 MSIX synchronization was performed completely.
+#define PCIE_REG_INT_STS_K2_E5                                                                               0x0547a0UL //Access:R    DataWidth:0x11   // Multi Field Register.
+  #define PCIE_REG_INT_STS_ADDRESS_ERROR_K2_E5                                                               (0x1<<0) // Signals an unknown address to the rf module.
+  #define PCIE_REG_INT_STS_ADDRESS_ERROR_K2_E5_SHIFT                                                         0
+  #define PCIE_REG_INT_STS_LINK_DOWN_DETECT_K2_E5                                                            (0x1<<1) // Data Link Down detected.
+  #define PCIE_REG_INT_STS_LINK_DOWN_DETECT_K2_E5_SHIFT                                                      1
+  #define PCIE_REG_INT_STS_LINK_UP_DETECT_K2_E5                                                              (0x1<<2) // Data Link Up detected.
+  #define PCIE_REG_INT_STS_LINK_UP_DETECT_K2_E5_SHIFT                                                        2
+  #define PCIE_REG_INT_STS_CFG_LINK_EQ_REQ_INT_K2_E5                                                         (0x1<<3) // Link Equalization requested.
+  #define PCIE_REG_INT_STS_CFG_LINK_EQ_REQ_INT_K2_E5_SHIFT                                                   3
+  #define PCIE_REG_INT_STS_PCIE_BANDWIDTH_CHANGE_DETECT_K2_E5                                                (0x1<<4) // PCIe Bandwidth changed.
+  #define PCIE_REG_INT_STS_PCIE_BANDWIDTH_CHANGE_DETECT_K2_E5_SHIFT                                          4
+  #define PCIE_REG_INT_STS_EARLY_HOT_RESET_DETECT_K2_E5                                                      (0x1<<5) // Early Hot Reset detected.
+  #define PCIE_REG_INT_STS_EARLY_HOT_RESET_DETECT_K2_E5_SHIFT                                                5
+  #define PCIE_REG_INT_STS_HOT_RESET_DETECT_K2_E5                                                            (0x1<<6) // Hot Reset detected.
+  #define PCIE_REG_INT_STS_HOT_RESET_DETECT_K2_E5_SHIFT                                                      6
+  #define PCIE_REG_INT_STS_L1_ENTRY_DETECT_K2_E5                                                             (0x1<<7) // L1 Entry detected.
+  #define PCIE_REG_INT_STS_L1_ENTRY_DETECT_K2_E5_SHIFT                                                       7
+  #define PCIE_REG_INT_STS_L1_EXIT_DETECT_K2_E5                                                              (0x1<<8) // L1 Exit detected.
+  #define PCIE_REG_INT_STS_L1_EXIT_DETECT_K2_E5_SHIFT                                                        8
+  #define PCIE_REG_INT_STS_LTSSM_STATE_MATCH_DETECT_K2_E5                                                    (0x1<<9) // LTSSM State matched.
+  #define PCIE_REG_INT_STS_LTSSM_STATE_MATCH_DETECT_K2_E5_SHIFT                                              9
+  #define PCIE_REG_INT_STS_FC_TIMEOUT_DETECT_K2_E5                                                           (0x1<<10) // Do not use -- keep mask bit set to 1.
+  #define PCIE_REG_INT_STS_FC_TIMEOUT_DETECT_K2_E5_SHIFT                                                     10
+  #define PCIE_REG_INT_STS_PME_TURNOFF_MESSAGE_DETECT_K2_E5                                                  (0x1<<11) // PME Turnoff Message received.
+  #define PCIE_REG_INT_STS_PME_TURNOFF_MESSAGE_DETECT_K2_E5_SHIFT                                            11
+  #define PCIE_REG_INT_STS_CFG_SEND_COR_ERR_K2_E5                                                            (0x1<<12) // Correctable Error Message sent.
+  #define PCIE_REG_INT_STS_CFG_SEND_COR_ERR_K2_E5_SHIFT                                                      12
+  #define PCIE_REG_INT_STS_CFG_SEND_NF_ERR_K2_E5                                                             (0x1<<13) // Non-Fatal Error Message sent.
+  #define PCIE_REG_INT_STS_CFG_SEND_NF_ERR_K2_E5_SHIFT                                                       13
+  #define PCIE_REG_INT_STS_CFG_SEND_F_ERR_K2_E5                                                              (0x1<<14) // Fatal Error Message sent.
+  #define PCIE_REG_INT_STS_CFG_SEND_F_ERR_K2_E5_SHIFT                                                        14
+  #define PCIE_REG_INT_STS_QOVERFLOW_DETECT_K2_E5                                                            (0x1<<15) // Queue Overflow detected.
+  #define PCIE_REG_INT_STS_QOVERFLOW_DETECT_K2_E5_SHIFT                                                      15
+  #define PCIE_REG_INT_STS_VDM_DETECT_K2_E5                                                                  (0x1<<16) // Vendor-Defined Message received.
+  #define PCIE_REG_INT_STS_VDM_DETECT_K2_E5_SHIFT                                                            16
+#define PCIE_REG_INT_MASK_K2_E5                                                                              0x0547a4UL //Access:RW   DataWidth:0x11   // Multi Field Register.
+  #define PCIE_REG_INT_MASK_ADDRESS_ERROR_K2_E5                                                              (0x1<<0) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.ADDRESS_ERROR .
+  #define PCIE_REG_INT_MASK_ADDRESS_ERROR_K2_E5_SHIFT                                                        0
+  #define PCIE_REG_INT_MASK_LINK_DOWN_DETECT_K2_E5                                                           (0x1<<1) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.LINK_DOWN_DETECT .
+  #define PCIE_REG_INT_MASK_LINK_DOWN_DETECT_K2_E5_SHIFT                                                     1
+  #define PCIE_REG_INT_MASK_LINK_UP_DETECT_K2_E5                                                             (0x1<<2) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.LINK_UP_DETECT .
+  #define PCIE_REG_INT_MASK_LINK_UP_DETECT_K2_E5_SHIFT                                                       2
+  #define PCIE_REG_INT_MASK_CFG_LINK_EQ_REQ_INT_K2_E5                                                        (0x1<<3) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.CFG_LINK_EQ_REQ_INT .
+  #define PCIE_REG_INT_MASK_CFG_LINK_EQ_REQ_INT_K2_E5_SHIFT                                                  3
+  #define PCIE_REG_INT_MASK_PCIE_BANDWIDTH_CHANGE_DETECT_K2_E5                                               (0x1<<4) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.PCIE_BANDWIDTH_CHANGE_DETECT .
+  #define PCIE_REG_INT_MASK_PCIE_BANDWIDTH_CHANGE_DETECT_K2_E5_SHIFT                                         4
+  #define PCIE_REG_INT_MASK_EARLY_HOT_RESET_DETECT_K2_E5                                                     (0x1<<5) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.EARLY_HOT_RESET_DETECT .
+  #define PCIE_REG_INT_MASK_EARLY_HOT_RESET_DETECT_K2_E5_SHIFT                                               5
+  #define PCIE_REG_INT_MASK_HOT_RESET_DETECT_K2_E5                                                           (0x1<<6) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.HOT_RESET_DETECT .
+  #define PCIE_REG_INT_MASK_HOT_RESET_DETECT_K2_E5_SHIFT                                                     6
+  #define PCIE_REG_INT_MASK_L1_ENTRY_DETECT_K2_E5                                                            (0x1<<7) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.L1_ENTRY_DETECT .
+  #define PCIE_REG_INT_MASK_L1_ENTRY_DETECT_K2_E5_SHIFT                                                      7
+  #define PCIE_REG_INT_MASK_L1_EXIT_DETECT_K2_E5                                                             (0x1<<8) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.L1_EXIT_DETECT .
+  #define PCIE_REG_INT_MASK_L1_EXIT_DETECT_K2_E5_SHIFT                                                       8
+  #define PCIE_REG_INT_MASK_LTSSM_STATE_MATCH_DETECT_K2_E5                                                   (0x1<<9) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.LTSSM_STATE_MATCH_DETECT .
+  #define PCIE_REG_INT_MASK_LTSSM_STATE_MATCH_DETECT_K2_E5_SHIFT                                             9
+  #define PCIE_REG_INT_MASK_FC_TIMEOUT_DETECT_K2_E5                                                          (0x1<<10) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.FC_TIMEOUT_DETECT .
+  #define PCIE_REG_INT_MASK_FC_TIMEOUT_DETECT_K2_E5_SHIFT                                                    10
+  #define PCIE_REG_INT_MASK_PME_TURNOFF_MESSAGE_DETECT_K2_E5                                                 (0x1<<11) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.PME_TURNOFF_MESSAGE_DETECT .
+  #define PCIE_REG_INT_MASK_PME_TURNOFF_MESSAGE_DETECT_K2_E5_SHIFT                                           11
+  #define PCIE_REG_INT_MASK_CFG_SEND_COR_ERR_K2_E5                                                           (0x1<<12) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.CFG_SEND_COR_ERR .
+  #define PCIE_REG_INT_MASK_CFG_SEND_COR_ERR_K2_E5_SHIFT                                                     12
+  #define PCIE_REG_INT_MASK_CFG_SEND_NF_ERR_K2_E5                                                            (0x1<<13) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.CFG_SEND_NF_ERR .
+  #define PCIE_REG_INT_MASK_CFG_SEND_NF_ERR_K2_E5_SHIFT                                                      13
+  #define PCIE_REG_INT_MASK_CFG_SEND_F_ERR_K2_E5                                                             (0x1<<14) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.CFG_SEND_F_ERR .
+  #define PCIE_REG_INT_MASK_CFG_SEND_F_ERR_K2_E5_SHIFT                                                       14
+  #define PCIE_REG_INT_MASK_QOVERFLOW_DETECT_K2_E5                                                           (0x1<<15) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.QOVERFLOW_DETECT .
+  #define PCIE_REG_INT_MASK_QOVERFLOW_DETECT_K2_E5_SHIFT                                                     15
+  #define PCIE_REG_INT_MASK_VDM_DETECT_K2_E5                                                                 (0x1<<16) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.VDM_DETECT .
+  #define PCIE_REG_INT_MASK_VDM_DETECT_K2_E5_SHIFT                                                           16
+#define PCIE_REG_INT_STS_WR_K2_E5                                                                            0x0547a8UL //Access:WR   DataWidth:0x11   // Multi Field Register.
+  #define PCIE_REG_INT_STS_WR_ADDRESS_ERROR_K2_E5                                                            (0x1<<0) // Signals an unknown address to the rf module.
+  #define PCIE_REG_INT_STS_WR_ADDRESS_ERROR_K2_E5_SHIFT                                                      0
+  #define PCIE_REG_INT_STS_WR_LINK_DOWN_DETECT_K2_E5                                                         (0x1<<1) // Data Link Down detected.
+  #define PCIE_REG_INT_STS_WR_LINK_DOWN_DETECT_K2_E5_SHIFT                                                   1
+  #define PCIE_REG_INT_STS_WR_LINK_UP_DETECT_K2_E5                                                           (0x1<<2) // Data Link Up detected.
+  #define PCIE_REG_INT_STS_WR_LINK_UP_DETECT_K2_E5_SHIFT                                                     2
+  #define PCIE_REG_INT_STS_WR_CFG_LINK_EQ_REQ_INT_K2_E5                                                      (0x1<<3) // Link Equalization requested.
+  #define PCIE_REG_INT_STS_WR_CFG_LINK_EQ_REQ_INT_K2_E5_SHIFT                                                3
+  #define PCIE_REG_INT_STS_WR_PCIE_BANDWIDTH_CHANGE_DETECT_K2_E5                                             (0x1<<4) // PCIe Bandwidth changed.
+  #define PCIE_REG_INT_STS_WR_PCIE_BANDWIDTH_CHANGE_DETECT_K2_E5_SHIFT                                       4
+  #define PCIE_REG_INT_STS_WR_EARLY_HOT_RESET_DETECT_K2_E5                                                   (0x1<<5) // Early Hot Reset detected.
+  #define PCIE_REG_INT_STS_WR_EARLY_HOT_RESET_DETECT_K2_E5_SHIFT                                             5
+  #define PCIE_REG_INT_STS_WR_HOT_RESET_DETECT_K2_E5                                                         (0x1<<6) // Hot Reset detected.
+  #define PCIE_REG_INT_STS_WR_HOT_RESET_DETECT_K2_E5_SHIFT                                                   6
+  #define PCIE_REG_INT_STS_WR_L1_ENTRY_DETECT_K2_E5                                                          (0x1<<7) // L1 Entry detected.
+  #define PCIE_REG_INT_STS_WR_L1_ENTRY_DETECT_K2_E5_SHIFT                                                    7
+  #define PCIE_REG_INT_STS_WR_L1_EXIT_DETECT_K2_E5                                                           (0x1<<8) // L1 Exit detected.
+  #define PCIE_REG_INT_STS_WR_L1_EXIT_DETECT_K2_E5_SHIFT                                                     8
+  #define PCIE_REG_INT_STS_WR_LTSSM_STATE_MATCH_DETECT_K2_E5                                                 (0x1<<9) // LTSSM State matched.
+  #define PCIE_REG_INT_STS_WR_LTSSM_STATE_MATCH_DETECT_K2_E5_SHIFT                                           9
+  #define PCIE_REG_INT_STS_WR_FC_TIMEOUT_DETECT_K2_E5                                                        (0x1<<10) // Do not use -- keep mask bit set to 1.
+  #define PCIE_REG_INT_STS_WR_FC_TIMEOUT_DETECT_K2_E5_SHIFT                                                  10
+  #define PCIE_REG_INT_STS_WR_PME_TURNOFF_MESSAGE_DETECT_K2_E5                                               (0x1<<11) // PME Turnoff Message received.
+  #define PCIE_REG_INT_STS_WR_PME_TURNOFF_MESSAGE_DETECT_K2_E5_SHIFT                                         11
+  #define PCIE_REG_INT_STS_WR_CFG_SEND_COR_ERR_K2_E5                                                         (0x1<<12) // Correctable Error Message sent.
+  #define PCIE_REG_INT_STS_WR_CFG_SEND_COR_ERR_K2_E5_SHIFT                                                   12
+  #define PCIE_REG_INT_STS_WR_CFG_SEND_NF_ERR_K2_E5                                                          (0x1<<13) // Non-Fatal Error Message sent.
+  #define PCIE_REG_INT_STS_WR_CFG_SEND_NF_ERR_K2_E5_SHIFT                                                    13
+  #define PCIE_REG_INT_STS_WR_CFG_SEND_F_ERR_K2_E5                                                           (0x1<<14) // Fatal Error Message sent.
+  #define PCIE_REG_INT_STS_WR_CFG_SEND_F_ERR_K2_E5_SHIFT                                                     14
+  #define PCIE_REG_INT_STS_WR_QOVERFLOW_DETECT_K2_E5                                                         (0x1<<15) // Queue Overflow detected.
+  #define PCIE_REG_INT_STS_WR_QOVERFLOW_DETECT_K2_E5_SHIFT                                                   15
+  #define PCIE_REG_INT_STS_WR_VDM_DETECT_K2_E5                                                               (0x1<<16) // Vendor-Defined Message received.
+  #define PCIE_REG_INT_STS_WR_VDM_DETECT_K2_E5_SHIFT                                                         16
+#define PCIE_REG_INT_STS_CLR_K2_E5                                                                           0x0547acUL //Access:RC   DataWidth:0x11   // Multi Field Register.
+  #define PCIE_REG_INT_STS_CLR_ADDRESS_ERROR_K2_E5                                                           (0x1<<0) // Signals an unknown address to the rf module.
+  #define PCIE_REG_INT_STS_CLR_ADDRESS_ERROR_K2_E5_SHIFT                                                     0
+  #define PCIE_REG_INT_STS_CLR_LINK_DOWN_DETECT_K2_E5                                                        (0x1<<1) // Data Link Down detected.
+  #define PCIE_REG_INT_STS_CLR_LINK_DOWN_DETECT_K2_E5_SHIFT                                                  1
+  #define PCIE_REG_INT_STS_CLR_LINK_UP_DETECT_K2_E5                                                          (0x1<<2) // Data Link Up detected.
+  #define PCIE_REG_INT_STS_CLR_LINK_UP_DETECT_K2_E5_SHIFT                                                    2
+  #define PCIE_REG_INT_STS_CLR_CFG_LINK_EQ_REQ_INT_K2_E5                                                     (0x1<<3) // Link Equalization requested.
+  #define PCIE_REG_INT_STS_CLR_CFG_LINK_EQ_REQ_INT_K2_E5_SHIFT                                               3
+  #define PCIE_REG_INT_STS_CLR_PCIE_BANDWIDTH_CHANGE_DETECT_K2_E5                                            (0x1<<4) // PCIe Bandwidth changed.
+  #define PCIE_REG_INT_STS_CLR_PCIE_BANDWIDTH_CHANGE_DETECT_K2_E5_SHIFT                                      4
+  #define PCIE_REG_INT_STS_CLR_EARLY_HOT_RESET_DETECT_K2_E5                                                  (0x1<<5) // Early Hot Reset detected.
+  #define PCIE_REG_INT_STS_CLR_EARLY_HOT_RESET_DETECT_K2_E5_SHIFT                                            5
+  #define PCIE_REG_INT_STS_CLR_HOT_RESET_DETECT_K2_E5                                                        (0x1<<6) // Hot Reset detected.
+  #define PCIE_REG_INT_STS_CLR_HOT_RESET_DETECT_K2_E5_SHIFT                                                  6
+  #define PCIE_REG_INT_STS_CLR_L1_ENTRY_DETECT_K2_E5                                                         (0x1<<7) // L1 Entry detected.
+  #define PCIE_REG_INT_STS_CLR_L1_ENTRY_DETECT_K2_E5_SHIFT                                                   7
+  #define PCIE_REG_INT_STS_CLR_L1_EXIT_DETECT_K2_E5                                                          (0x1<<8) // L1 Exit detected.
+  #define PCIE_REG_INT_STS_CLR_L1_EXIT_DETECT_K2_E5_SHIFT                                                    8
+  #define PCIE_REG_INT_STS_CLR_LTSSM_STATE_MATCH_DETECT_K2_E5                                                (0x1<<9) // LTSSM State matched.
+  #define PCIE_REG_INT_STS_CLR_LTSSM_STATE_MATCH_DETECT_K2_E5_SHIFT                                          9
+  #define PCIE_REG_INT_STS_CLR_FC_TIMEOUT_DETECT_K2_E5                                                       (0x1<<10) // Do not use -- keep mask bit set to 1.
+  #define PCIE_REG_INT_STS_CLR_FC_TIMEOUT_DETECT_K2_E5_SHIFT                                                 10
+  #define PCIE_REG_INT_STS_CLR_PME_TURNOFF_MESSAGE_DETECT_K2_E5                                              (0x1<<11) // PME Turnoff Message received.
+  #define PCIE_REG_INT_STS_CLR_PME_TURNOFF_MESSAGE_DETECT_K2_E5_SHIFT                                        11
+  #define PCIE_REG_INT_STS_CLR_CFG_SEND_COR_ERR_K2_E5                                                        (0x1<<12) // Correctable Error Message sent.
+  #define PCIE_REG_INT_STS_CLR_CFG_SEND_COR_ERR_K2_E5_SHIFT                                                  12
+  #define PCIE_REG_INT_STS_CLR_CFG_SEND_NF_ERR_K2_E5                                                         (0x1<<13) // Non-Fatal Error Message sent.
+  #define PCIE_REG_INT_STS_CLR_CFG_SEND_NF_ERR_K2_E5_SHIFT                                                   13
+  #define PCIE_REG_INT_STS_CLR_CFG_SEND_F_ERR_K2_E5                                                          (0x1<<14) // Fatal Error Message sent.
+  #define PCIE_REG_INT_STS_CLR_CFG_SEND_F_ERR_K2_E5_SHIFT                                                    14
+  #define PCIE_REG_INT_STS_CLR_QOVERFLOW_DETECT_K2_E5                                                        (0x1<<15) // Queue Overflow detected.
+  #define PCIE_REG_INT_STS_CLR_QOVERFLOW_DETECT_K2_E5_SHIFT                                                  15
+  #define PCIE_REG_INT_STS_CLR_VDM_DETECT_K2_E5                                                              (0x1<<16) // Vendor-Defined Message received.
+  #define PCIE_REG_INT_STS_CLR_VDM_DETECT_K2_E5_SHIFT                                                        16
+#define PCIE_REG_PRTY_MASK_K2_E5                                                                             0x0547b4UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define PCIE_REG_PRTY_MASK_APP_PARITY_ERRS_0_K2_E5                                                         (0x1<<0) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS.APP_PARITY_ERRS_0 .
+  #define PCIE_REG_PRTY_MASK_APP_PARITY_ERRS_0_K2_E5_SHIFT                                                   0
+  #define PCIE_REG_PRTY_MASK_APP_PARITY_ERRS_1_K2_E5                                                         (0x1<<1) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS.APP_PARITY_ERRS_1 .
+  #define PCIE_REG_PRTY_MASK_APP_PARITY_ERRS_1_K2_E5_SHIFT                                                   1
+  #define PCIE_REG_PRTY_MASK_APP_PARITY_ERRS_2_K2_E5                                                         (0x1<<2) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS.APP_PARITY_ERRS_2 .
+  #define PCIE_REG_PRTY_MASK_APP_PARITY_ERRS_2_K2_E5_SHIFT                                                   2
+#define PCIE_REG_DBG_OUT_DATA_K2_E5                                                                          0x0547c0UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PCIE_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define PCIE_REG_DBG_OUT_VALID_K2_E5                                                                         0x0547e0UL //Access:R    DataWidth:0x4    // Dbgmux output valid
+#define PCIE_REG_DBG_OUT_FRAME_K2_E5                                                                         0x0547e4UL //Access:R    DataWidth:0x4    // Dbgmux output frame
+#define PCIE_REG_DBG_SELECT_K2_E5                                                                            0x0547e8UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PCIE_REG_DBG_DWORD_ENABLE_K2_E5                                                                      0x0547ecUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PCIE_REG_DBG_SHIFT_K2_E5                                                                             0x0547f0UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PCIE_REG_DBG_FORCE_VALID_K2_E5                                                                       0x0547f4UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PCIE_REG_DBG_FORCE_FRAME_K2_E5                                                                       0x0547f8UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PCIE_REG_RESET_STATUS_2_K2_E5                                                                        0x054800UL //Access:R    DataWidth:0x18   // Multi Field Register.
+  #define PCIE_REG_RESET_STATUS_2_PWR_RST_2_K2_E5                                                            (0x1<<0) // Power-on reset occurred.
+  #define PCIE_REG_RESET_STATUS_2_PWR_RST_2_K2_E5_SHIFT                                                      0
+  #define PCIE_REG_RESET_STATUS_2_WAKE_REF_RST_2_K2_E5                                                       (0x1<<1) // Wake Ref reset occurred.
+  #define PCIE_REG_RESET_STATUS_2_WAKE_REF_RST_2_K2_E5_SHIFT                                                 1
+  #define PCIE_REG_RESET_STATUS_2_PHY_RST_2_K2_E5                                                            (0x1<<2) // Phy reset occurred.
+  #define PCIE_REG_RESET_STATUS_2_PHY_RST_2_K2_E5_SHIFT                                                      2
+  #define PCIE_REG_RESET_STATUS_2_SQUELCH_RST_2_K2_E5                                                        (0x1<<3) // Squelch reset occurred.
+  #define PCIE_REG_RESET_STATUS_2_SQUELCH_RST_2_K2_E5_SHIFT                                                  3
+  #define PCIE_REG_RESET_STATUS_2_STICKY_RST_2_K2_E5                                                         (0x1<<4) // Sticky register reset occurred.
+  #define PCIE_REG_RESET_STATUS_2_STICKY_RST_2_K2_E5_SHIFT                                                   4
+  #define PCIE_REG_RESET_STATUS_2_NON_STICKY_RST_2_K2_E5                                                     (0x1<<5) // Non-sticky register reset occurred.
+  #define PCIE_REG_RESET_STATUS_2_NON_STICKY_RST_2_K2_E5_SHIFT                                               5
+  #define PCIE_REG_RESET_STATUS_2_CORE_RST_2_K2_E5                                                           (0x1<<6) // Core reset occurred.
+  #define PCIE_REG_RESET_STATUS_2_CORE_RST_2_K2_E5_SHIFT                                                     6
+  #define PCIE_REG_RESET_STATUS_2_PIPE_RST_2_K2_E5                                                           (0x1<<7) // PIPE reset occurred.
+  #define PCIE_REG_RESET_STATUS_2_PIPE_RST_2_K2_E5_SHIFT                                                     7
+  #define PCIE_REG_RESET_STATUS_2_PERST_2_K2_E5                                                              (0x1<<8) // PERST occurred (raw version).
+  #define PCIE_REG_RESET_STATUS_2_PERST_2_K2_E5_SHIFT                                                        8
+  #define PCIE_REG_RESET_STATUS_2_DATA_LINK_DOWN_2_K2_E5                                                     (0x1<<9) // Data Link Down occurred.
+  #define PCIE_REG_RESET_STATUS_2_DATA_LINK_DOWN_2_K2_E5_SHIFT                                               9
+  #define PCIE_REG_RESET_STATUS_2_DELAYED_PERST_2_K2_E5                                                      (0x1<<10) // PERST occurred (delayed version).
+  #define PCIE_REG_RESET_STATUS_2_DELAYED_PERST_2_K2_E5_SHIFT                                                10
+  #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_11_2_K2_E5                                          (0x1<<11) // Spare status bit
+  #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_11_2_K2_E5_SHIFT                                    11
+  #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_12_2_K2_E5                                          (0x1<<12) // Spare status bit
+  #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_12_2_K2_E5_SHIFT                                    12
+  #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_13_2_K2_E5                                          (0x1<<13) // Spare status bit
+  #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_13_2_K2_E5_SHIFT                                    13
+  #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_14_2_K2_E5                                          (0x1<<14) // Spare status bit
+  #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_14_2_K2_E5_SHIFT                                    14
+  #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_15_2_K2_E5                                          (0x1<<15) // Spare status bit
+  #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_15_2_K2_E5_SHIFT                                    15
+  #define PCIE_REG_RESET_STATUS_2_SOFT_PWR_RST_2_K2_E5                                                       (0x1<<16) // Soft power-on reset occurred. NOTE: This bit is unreliable for indication of a soft power-on reset, because it self-clears within a short time following the event.
+  #define PCIE_REG_RESET_STATUS_2_SOFT_PWR_RST_2_K2_E5_SHIFT                                                 16
+  #define PCIE_REG_RESET_STATUS_2_SOFT_WAKE_REF_RST_2_K2_E5                                                  (0x1<<17) // Soft Wake Ref reset occurred.
+  #define PCIE_REG_RESET_STATUS_2_SOFT_WAKE_REF_RST_2_K2_E5_SHIFT                                            17
+  #define PCIE_REG_RESET_STATUS_2_SOFT_PHY_RST_2_K2_E5                                                       (0x1<<18) // Soft phy reset occurred.
+  #define PCIE_REG_RESET_STATUS_2_SOFT_PHY_RST_2_K2_E5_SHIFT                                                 18
+  #define PCIE_REG_RESET_STATUS_2_SOFT_SQUELCH_RST_2_K2_E5                                                   (0x1<<19) // Soft squelch reset occurred.
+  #define PCIE_REG_RESET_STATUS_2_SOFT_SQUELCH_RST_2_K2_E5_SHIFT                                             19
+  #define PCIE_REG_RESET_STATUS_2_SOFT_STICKY_RST_2_K2_E5                                                    (0x1<<20) // Soft sticky register reset occurred.
+  #define PCIE_REG_RESET_STATUS_2_SOFT_STICKY_RST_2_K2_E5_SHIFT                                              20
+  #define PCIE_REG_RESET_STATUS_2_SOFT_NON_STICKY_RST_2_K2_E5                                                (0x1<<21) // Soft non-sticky register reset occurred.
+  #define PCIE_REG_RESET_STATUS_2_SOFT_NON_STICKY_RST_2_K2_E5_SHIFT                                          21
+  #define PCIE_REG_RESET_STATUS_2_SOFT_CORE_RST_2_K2_E5                                                      (0x1<<22) // Soft core reset occurred.
+  #define PCIE_REG_RESET_STATUS_2_SOFT_CORE_RST_2_K2_E5_SHIFT                                                22
+  #define PCIE_REG_RESET_STATUS_2_SOFT_PIPE_RST_2_K2_E5                                                      (0x1<<23) // Soft PIPE reset occurred.
+  #define PCIE_REG_RESET_STATUS_2_SOFT_PIPE_RST_2_K2_E5_SHIFT                                                23
+#define PCIE_REG_RESET_STATUS_3_K2_E5                                                                        0x054804UL //Access:RW   DataWidth:0x18   // Corresponding bits of Reset Status Register 2 will be cleared for bits written with a 1.
+#define DORQ_REG_INIT                                                                                        0x100000UL //Access:RW   DataWidth:0x1    // Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
+#define DORQ_REG_IFEN                                                                                        0x100040UL //Access:RW   DataWidth:0x1    // Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
+#define DORQ_REG_INT_STS                                                                                     0x100180UL //Access:R    DataWidth:0xc    // Multi Field Register.
+  #define DORQ_REG_INT_STS_ADDRESS_ERROR                                                                     (0x1<<0) // Signals an unknown address to the rf module.
+  #define DORQ_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                               0
+  #define DORQ_REG_INT_STS_DB_DROP                                                                           (0x1<<1) // Doorbell drop.
+  #define DORQ_REG_INT_STS_DB_DROP_SHIFT                                                                     1
+  #define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR                                                                (0x1<<2) // DORQ FIFO overflow.
+  #define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR_SHIFT                                                          2
+  #define DORQ_REG_INT_STS_DORQ_FIFO_AFULL                                                                   (0x1<<3) // DORQ FIFO almost full.
+  #define DORQ_REG_INT_STS_DORQ_FIFO_AFULL_SHIFT                                                             3
+  #define DORQ_REG_INT_STS_CFC_BYP_VALIDATION_ERR                                                            (0x1<<4) // After cached LCID value was used for CM message, CCFC load response LCID does not match cached value.
+  #define DORQ_REG_INT_STS_CFC_BYP_VALIDATION_ERR_SHIFT                                                      4
+  #define DORQ_REG_INT_STS_CFC_LD_RESP_ERR                                                                   (0x1<<5) // CCFC load response returnes an error.
+  #define DORQ_REG_INT_STS_CFC_LD_RESP_ERR_SHIFT                                                             5
+  #define DORQ_REG_INT_STS_XCM_DONE_CNT_ERR                                                                  (0x1<<6) // XCM done counter is decremented (done appears), when it is 0.
+  #define DORQ_REG_INT_STS_XCM_DONE_CNT_ERR_SHIFT                                                            6
+  #define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_OVFL_ERR                                                          (0x1<<7) // CFC load request FIFO overflow
+  #define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_OVFL_ERR_SHIFT                                                    7
+  #define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_UNDER_ERR                                                         (0x1<<8) // CFC load request FIFO under-run
+  #define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_UNDER_ERR_SHIFT                                                   8
+  #define DORQ_REG_INT_STS_IEDPM_DROP_E5                                                                     (0x1<<9) // IEDPM doorbell drop
+  #define DORQ_REG_INT_STS_IEDPM_DROP_E5_SHIFT                                                               9
+  #define DORQ_REG_INT_STS_IEDPM_DPM_E5                                                                      (0x1<<10) // IEDPM interrupt on abort of DpmTbl residing IEDPM doorbell, i.e. IEDPM doorbell that will eventually need DPM processing.      IEDPM doorbell abort due to:      a) Non-first payload QWord (offset other than 0) arives on IEDPM buffer which is free or      b) Non-first QWord (offset other than 0) arives on IEDPM buffer which is not free and non-contigious offset or       c) First QWord (offset 0) arives on IEDPM buffer which is not free
+  #define DORQ_REG_INT_STS_IEDPM_DPM_E5_SHIFT                                                                10
+  #define DORQ_REG_INT_STS_H_REQ_BYTE_ENABLE_ERR_E5                                                          (0x1<<11) // byte_enable is not al ones attention
+  #define DORQ_REG_INT_STS_H_REQ_BYTE_ENABLE_ERR_E5_SHIFT                                                    11
+#define DORQ_REG_INT_MASK                                                                                    0x100184UL //Access:RW   DataWidth:0xc    // Multi Field Register.
+  #define DORQ_REG_INT_MASK_ADDRESS_ERROR                                                                    (0x1<<0) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.ADDRESS_ERROR .
+  #define DORQ_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                              0
+  #define DORQ_REG_INT_MASK_DB_DROP                                                                          (0x1<<1) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.DB_DROP .
+  #define DORQ_REG_INT_MASK_DB_DROP_SHIFT                                                                    1
+  #define DORQ_REG_INT_MASK_DORQ_FIFO_OVFL_ERR                                                               (0x1<<2) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.DORQ_FIFO_OVFL_ERR .
+  #define DORQ_REG_INT_MASK_DORQ_FIFO_OVFL_ERR_SHIFT                                                         2
+  #define DORQ_REG_INT_MASK_DORQ_FIFO_AFULL                                                                  (0x1<<3) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.DORQ_FIFO_AFULL .
+  #define DORQ_REG_INT_MASK_DORQ_FIFO_AFULL_SHIFT                                                            3
+  #define DORQ_REG_INT_MASK_CFC_BYP_VALIDATION_ERR                                                           (0x1<<4) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.CFC_BYP_VALIDATION_ERR .
+  #define DORQ_REG_INT_MASK_CFC_BYP_VALIDATION_ERR_SHIFT                                                     4
+  #define DORQ_REG_INT_MASK_CFC_LD_RESP_ERR                                                                  (0x1<<5) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.CFC_LD_RESP_ERR .
+  #define DORQ_REG_INT_MASK_CFC_LD_RESP_ERR_SHIFT                                                            5
+  #define DORQ_REG_INT_MASK_XCM_DONE_CNT_ERR                                                                 (0x1<<6) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.XCM_DONE_CNT_ERR .
+  #define DORQ_REG_INT_MASK_XCM_DONE_CNT_ERR_SHIFT                                                           6
+  #define DORQ_REG_INT_MASK_CFC_LD_REQ_FIFO_OVFL_ERR                                                         (0x1<<7) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.CFC_LD_REQ_FIFO_OVFL_ERR .
+  #define DORQ_REG_INT_MASK_CFC_LD_REQ_FIFO_OVFL_ERR_SHIFT                                                   7
+  #define DORQ_REG_INT_MASK_CFC_LD_REQ_FIFO_UNDER_ERR                                                        (0x1<<8) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.CFC_LD_REQ_FIFO_UNDER_ERR .
+  #define DORQ_REG_INT_MASK_CFC_LD_REQ_FIFO_UNDER_ERR_SHIFT                                                  8
+  #define DORQ_REG_INT_MASK_IEDPM_DROP_E5                                                                    (0x1<<9) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.IEDPM_DROP .
+  #define DORQ_REG_INT_MASK_IEDPM_DROP_E5_SHIFT                                                              9
+  #define DORQ_REG_INT_MASK_IEDPM_DPM_E5                                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.IEDPM_DPM .
+  #define DORQ_REG_INT_MASK_IEDPM_DPM_E5_SHIFT                                                               10
+  #define DORQ_REG_INT_MASK_H_REQ_BYTE_ENABLE_ERR_E5                                                         (0x1<<11) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.H_REQ_BYTE_ENABLE_ERR .
+  #define DORQ_REG_INT_MASK_H_REQ_BYTE_ENABLE_ERR_E5_SHIFT                                                   11
+#define DORQ_REG_INT_STS_WR                                                                                  0x100188UL //Access:WR   DataWidth:0xc    // Multi Field Register.
+  #define DORQ_REG_INT_STS_WR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define DORQ_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                            0
+  #define DORQ_REG_INT_STS_WR_DB_DROP                                                                        (0x1<<1) // Doorbell drop.
+  #define DORQ_REG_INT_STS_WR_DB_DROP_SHIFT                                                                  1
+  #define DORQ_REG_INT_STS_WR_DORQ_FIFO_OVFL_ERR                                                             (0x1<<2) // DORQ FIFO overflow.
+  #define DORQ_REG_INT_STS_WR_DORQ_FIFO_OVFL_ERR_SHIFT                                                       2
+  #define DORQ_REG_INT_STS_WR_DORQ_FIFO_AFULL                                                                (0x1<<3) // DORQ FIFO almost full.
+  #define DORQ_REG_INT_STS_WR_DORQ_FIFO_AFULL_SHIFT                                                          3
+  #define DORQ_REG_INT_STS_WR_CFC_BYP_VALIDATION_ERR                                                         (0x1<<4) // After cached LCID value was used for CM message, CCFC load response LCID does not match cached value.
+  #define DORQ_REG_INT_STS_WR_CFC_BYP_VALIDATION_ERR_SHIFT                                                   4
+  #define DORQ_REG_INT_STS_WR_CFC_LD_RESP_ERR                                                                (0x1<<5) // CCFC load response returnes an error.
+  #define DORQ_REG_INT_STS_WR_CFC_LD_RESP_ERR_SHIFT                                                          5
+  #define DORQ_REG_INT_STS_WR_XCM_DONE_CNT_ERR                                                               (0x1<<6) // XCM done counter is decremented (done appears), when it is 0.
+  #define DORQ_REG_INT_STS_WR_XCM_DONE_CNT_ERR_SHIFT                                                         6
+  #define DORQ_REG_INT_STS_WR_CFC_LD_REQ_FIFO_OVFL_ERR                                                       (0x1<<7) // CFC load request FIFO overflow
+  #define DORQ_REG_INT_STS_WR_CFC_LD_REQ_FIFO_OVFL_ERR_SHIFT                                                 7
+  #define DORQ_REG_INT_STS_WR_CFC_LD_REQ_FIFO_UNDER_ERR                                                      (0x1<<8) // CFC load request FIFO under-run
+  #define DORQ_REG_INT_STS_WR_CFC_LD_REQ_FIFO_UNDER_ERR_SHIFT                                                8
+  #define DORQ_REG_INT_STS_WR_IEDPM_DROP_E5                                                                  (0x1<<9) // IEDPM doorbell drop
+  #define DORQ_REG_INT_STS_WR_IEDPM_DROP_E5_SHIFT                                                            9
+  #define DORQ_REG_INT_STS_WR_IEDPM_DPM_E5                                                                   (0x1<<10) // IEDPM interrupt on abort of DpmTbl residing IEDPM doorbell, i.e. IEDPM doorbell that will eventually need DPM processing.      IEDPM doorbell abort due to:      a) Non-first payload QWord (offset other than 0) arives on IEDPM buffer which is free or      b) Non-first QWord (offset other than 0) arives on IEDPM buffer which is not free and non-contigious offset or       c) First QWord (offset 0) arives on IEDPM buffer which is not free
+  #define DORQ_REG_INT_STS_WR_IEDPM_DPM_E5_SHIFT                                                             10
+  #define DORQ_REG_INT_STS_WR_H_REQ_BYTE_ENABLE_ERR_E5                                                       (0x1<<11) // byte_enable is not al ones attention
+  #define DORQ_REG_INT_STS_WR_H_REQ_BYTE_ENABLE_ERR_E5_SHIFT                                                 11
+#define DORQ_REG_INT_STS_CLR                                                                                 0x10018cUL //Access:RC   DataWidth:0xc    // Multi Field Register.
+  #define DORQ_REG_INT_STS_CLR_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define DORQ_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                           0
+  #define DORQ_REG_INT_STS_CLR_DB_DROP                                                                       (0x1<<1) // Doorbell drop.
+  #define DORQ_REG_INT_STS_CLR_DB_DROP_SHIFT                                                                 1
+  #define DORQ_REG_INT_STS_CLR_DORQ_FIFO_OVFL_ERR                                                            (0x1<<2) // DORQ FIFO overflow.
+  #define DORQ_REG_INT_STS_CLR_DORQ_FIFO_OVFL_ERR_SHIFT                                                      2
+  #define DORQ_REG_INT_STS_CLR_DORQ_FIFO_AFULL                                                               (0x1<<3) // DORQ FIFO almost full.
+  #define DORQ_REG_INT_STS_CLR_DORQ_FIFO_AFULL_SHIFT                                                         3
+  #define DORQ_REG_INT_STS_CLR_CFC_BYP_VALIDATION_ERR                                                        (0x1<<4) // After cached LCID value was used for CM message, CCFC load response LCID does not match cached value.
+  #define DORQ_REG_INT_STS_CLR_CFC_BYP_VALIDATION_ERR_SHIFT                                                  4
+  #define DORQ_REG_INT_STS_CLR_CFC_LD_RESP_ERR                                                               (0x1<<5) // CCFC load response returnes an error.
+  #define DORQ_REG_INT_STS_CLR_CFC_LD_RESP_ERR_SHIFT                                                         5
+  #define DORQ_REG_INT_STS_CLR_XCM_DONE_CNT_ERR                                                              (0x1<<6) // XCM done counter is decremented (done appears), when it is 0.
+  #define DORQ_REG_INT_STS_CLR_XCM_DONE_CNT_ERR_SHIFT                                                        6
+  #define DORQ_REG_INT_STS_CLR_CFC_LD_REQ_FIFO_OVFL_ERR                                                      (0x1<<7) // CFC load request FIFO overflow
+  #define DORQ_REG_INT_STS_CLR_CFC_LD_REQ_FIFO_OVFL_ERR_SHIFT                                                7
+  #define DORQ_REG_INT_STS_CLR_CFC_LD_REQ_FIFO_UNDER_ERR                                                     (0x1<<8) // CFC load request FIFO under-run
+  #define DORQ_REG_INT_STS_CLR_CFC_LD_REQ_FIFO_UNDER_ERR_SHIFT                                               8
+  #define DORQ_REG_INT_STS_CLR_IEDPM_DROP_E5                                                                 (0x1<<9) // IEDPM doorbell drop
+  #define DORQ_REG_INT_STS_CLR_IEDPM_DROP_E5_SHIFT                                                           9
+  #define DORQ_REG_INT_STS_CLR_IEDPM_DPM_E5                                                                  (0x1<<10) // IEDPM interrupt on abort of DpmTbl residing IEDPM doorbell, i.e. IEDPM doorbell that will eventually need DPM processing.      IEDPM doorbell abort due to:      a) Non-first payload QWord (offset other than 0) arives on IEDPM buffer which is free or      b) Non-first QWord (offset other than 0) arives on IEDPM buffer which is not free and non-contigious offset or       c) First QWord (offset 0) arives on IEDPM buffer which is not free
+  #define DORQ_REG_INT_STS_CLR_IEDPM_DPM_E5_SHIFT                                                            10
+  #define DORQ_REG_INT_STS_CLR_H_REQ_BYTE_ENABLE_ERR_E5                                                      (0x1<<11) // byte_enable is not al ones attention
+  #define DORQ_REG_INT_STS_CLR_H_REQ_BYTE_ENABLE_ERR_E5_SHIFT                                                11
+#define DORQ_REG_PRTY_MASK                                                                                   0x100194UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define DORQ_REG_PRTY_MASK_DATAPATH_REGISTERS                                                              (0x1<<0) // This bit masks, when set, the Parity bit: DORQ_REG_PRTY_STS.DATAPATH_REGISTERS .
+  #define DORQ_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                                        0
+#define DORQ_REG_PRTY_MASK_H_0_BB_K2                                                                         0x100204UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define DORQ_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_BB_K2                                                   (0x1<<0) // This bit masks, when set, the Parity bit: DORQ_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT .
+  #define DORQ_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_BB_K2_SHIFT                                             0
+  #define DORQ_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                     (0x1<<1) // This bit masks, when set, the Parity bit: DORQ_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define DORQ_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                               1
+  #define DORQ_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                     (0x1<<2) // This bit masks, when set, the Parity bit: DORQ_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define DORQ_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                               2
+  #define DORQ_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                     (0x1<<3) // This bit masks, when set, the Parity bit: DORQ_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define DORQ_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                               3
+  #define DORQ_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2                                                     (0x1<<4) // This bit masks, when set, the Parity bit: DORQ_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define DORQ_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT                                               4
+  #define DORQ_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2                                                     (0x1<<5) // This bit masks, when set, the Parity bit: DORQ_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define DORQ_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2_SHIFT                                               5
+#define DORQ_REG_MEM_ECC_ENABLE_0_BB_K2                                                                      0x100210UL //Access:RW   DataWidth:0x1    // Enable ECC for memory ecc instance dorq.i_dorq_fifo_mem.i_ecc in module dorq_fifo_mem
+#define DORQ_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                 0x100214UL //Access:RW   DataWidth:0x1    // Set parity only for memory ecc instance dorq.i_dorq_fifo_mem.i_ecc in module dorq_fifo_mem
+#define DORQ_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                             0x100218UL //Access:RC   DataWidth:0x1    // Record if a correctable error occurred on memory ecc instance dorq.i_dorq_fifo_mem.i_ecc in module dorq_fifo_mem
+#define DORQ_REG_MEM_ECC_EVENTS_BB_K2                                                                        0x10021cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define DORQ_REG_PF_MIN_ADDR_REG1                                                                            0x100400UL //Access:RW   DataWidth:0x14   // The offset in units of 4KB from the start of the doorbell space to the start of region 1 (PWM region). This is a per PF configuration.
+#define DORQ_REG_VF_MIN_ADDR_REG1                                                                            0x100404UL //Access:RW   DataWidth:0x14   // The offset in units of 4KB from the start of the doorbell space to the start of region 1 (PWM region). This is a per PF configuration.
+#define DORQ_REG_PF_MAX_ICID_0_BB_K2                                                                         0x100408UL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 0. This is per PF configuration.
+#define DORQ_REG_PF_MAX_ICID_1_BB_K2                                                                         0x10040cUL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 1. This is per PF configuration.
+#define DORQ_REG_PF_MAX_ICID_2_BB_K2                                                                         0x100410UL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 2. This is per PF configuration.
+#define DORQ_REG_PF_MAX_ICID_3_BB_K2                                                                         0x100414UL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 3. This is per PF configuration.
+#define DORQ_REG_PF_MAX_ICID_4_BB_K2                                                                         0x100418UL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 4. This is per PF configuration.
+#define DORQ_REG_PF_MAX_ICID_5_BB_K2                                                                         0x10041cUL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 5. This is per PF configuration.
+#define DORQ_REG_PF_MAX_ICID_6_BB_K2                                                                         0x100420UL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 6. This is per PF configuration.
+#define DORQ_REG_PF_MAX_ICID_7_BB_K2                                                                         0x100424UL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 7. This is per PF configuration.
+#define DORQ_REG_VF_MAX_ICID_0_BB_K2                                                                         0x100428UL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 0. This is per PF configuration.
+#define DORQ_REG_VF_MAX_ICID_1_BB_K2                                                                         0x10042cUL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 1. This is per PF configuration.
+#define DORQ_REG_VF_MAX_ICID_2_BB_K2                                                                         0x100430UL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 2. This is per PF configuration.
+#define DORQ_REG_VF_MAX_ICID_3_BB_K2                                                                         0x100434UL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 3. This is per PF configuration.
+#define DORQ_REG_VF_MAX_ICID_4_BB_K2                                                                         0x100438UL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 4. This is per PF configuration.
+#define DORQ_REG_VF_MAX_ICID_5_BB_K2                                                                         0x10043cUL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 5. This is per PF configuration.
+#define DORQ_REG_VF_MAX_ICID_6_BB_K2                                                                         0x100440UL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 6. This is per PF configuration.
+#define DORQ_REG_VF_MAX_ICID_7_BB_K2                                                                         0x100444UL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 7. This is per PF configuration.
+#define DORQ_REG_PF_ICID_BIT_SHIFT_NORM                                                                      0x100448UL //Access:RW   DataWidth:0x2    // LOG2 of the size of per connection doorbell space footprint in DWORD-s. I.e. value of 0 means 1 DWord (4B) per connection, value of 1 means 2 DWords (8B) and so forth. This is a per PF configuration.
+#define DORQ_REG_VF_ICID_BIT_SHIFT_NORM                                                                      0x10044cUL //Access:RW   DataWidth:0x2    // LOG2 of the size of per connection doorbell space footprint in DWORD-s. I.e. value of 0 means 1 DWord (4B) per connection, value of 1 means 2 DWords (8B) and so forth. This is a per PF configuration.
+#define DORQ_REG_PF_DPI_BIT_SHIFT                                                                            0x100450UL //Access:RW   DataWidth:0x5    // Indicates the size of a page in PWM. This is the LOG2 of PWM page size in units of 4KB, i.e. 0 means 4KB page, 1 means 8KB pages and so forth. This is a per PF configuration.
+#define DORQ_REG_VF_DPI_BIT_SHIFT                                                                            0x100454UL //Access:RW   DataWidth:0x5    // Indicates the size of a page in PWM. This is the LOG2 of PWM page size in units of 4KB, i.e. 0 means 4KB page, 1 means 8KB pages and so forth. This is a per PF configuration.
+#define DORQ_REG_PF_MIN_VAL_DPI                                                                              0x100458UL //Access:RW   DataWidth:0x4    // Indicates the LOG2 of PWM pages at the start of PWM region which doesn't require DPI validation. This is a per PF configuration.
+#define DORQ_REG_VF_MIN_VAL_DPI                                                                              0x10045cUL //Access:RW   DataWidth:0x4    // Indicates the LOG2 of PWM pages at the start of PWM region which doesn't require DPI validation. This is a per PF configuration.
+#define DORQ_REG_DEMS_TARGET_1                                                                               0x100460UL //Access:RW   DataWidth:0x2    // Target value used in DEMS mode for DEMS = 1.
+#define DORQ_REG_DEMS_AGG_VAL_SEL_1                                                                          0x100464UL //Access:RW   DataWidth:0x2    // AggValSel used in DEMS mode for DEMS = 1. Bit 2 of AggValSel is always 1 in DEMS mode.
+#define DORQ_REG_DEMS_AGG_CMD_1                                                                              0x100468UL //Access:RW   DataWidth:0x2    // AggCmd used in DEMS mode for DEMS = 1. Reset value = SET_AG_CMD.
+#define DORQ_REG_DEMS_TARGET_2                                                                               0x10046cUL //Access:RW   DataWidth:0x2    // Target value used in DEMS mode for DEMS = 2.
+#define DORQ_REG_DEMS_AGG_VAL_SEL_2                                                                          0x100470UL //Access:RW   DataWidth:0x2    // AggValSel used in DEMS mode for DEMS = 2. Bit 2 of AggValSel is always 1 in DEMS mode.
+#define DORQ_REG_DEMS_AGG_CMD_2                                                                              0x100474UL //Access:RW   DataWidth:0x2    // AggCmd used in DEMS mode for DEMS = 2. Reset value = SET_AG_CMD.
+#define DORQ_REG_DEMS_TARGET_3                                                                               0x100478UL //Access:RW   DataWidth:0x2    // Target value used in DEMS mode for DEMS = 3.
+#define DORQ_REG_DEMS_AGG_VAL_SEL_3                                                                          0x10047cUL //Access:RW   DataWidth:0x2    // AggValSel used in DEMS mode for DEMS = 3. Bit 2 of AggValSel is always 1 in DEMS mode.
+#define DORQ_REG_DEMS_AGG_CMD_3                                                                              0x100480UL //Access:RW   DataWidth:0x2    // AggCmd used in DEMS mode for DEMS = 3. Reset value = SET_AG_CMD.
+#define DORQ_REG_DEMS_TARGET_4                                                                               0x100484UL //Access:RW   DataWidth:0x2    // Target value used in DEMS mode for DEMS = 4.
+#define DORQ_REG_DEMS_AGG_VAL_SEL_4                                                                          0x100488UL //Access:RW   DataWidth:0x2    // AggValSel used in DEMS mode for DEMS = 4. Bit 2 of AggValSel is always 1 in DEMS mode.
+#define DORQ_REG_DEMS_AGG_CMD_4                                                                              0x10048cUL //Access:RW   DataWidth:0x2    // AggCmd used in DEMS mode for DEMS = 4. Reset value = SET_AG_CMD.
+#define DORQ_REG_DEMS_TARGET_5                                                                               0x100490UL //Access:RW   DataWidth:0x2    // Target value used in DEMS mode for DEMS = 5.
+#define DORQ_REG_DEMS_AGG_VAL_SEL_5                                                                          0x100494UL //Access:RW   DataWidth:0x2    // AggValSel used in DEMS mode for DEMS = 5. Bit 2 of AggValSel is always 1 in DEMS mode.
+#define DORQ_REG_DEMS_AGG_CMD_5                                                                              0x100498UL //Access:RW   DataWidth:0x2    // AggCmd used in DEMS mode for DEMS = 5. Reset value = SET_AG_CMD.
+#define DORQ_REG_DEMS_TARGET_6                                                                               0x10049cUL //Access:RW   DataWidth:0x2    // Target value used in DEMS mode for DEMS = 6.
+#define DORQ_REG_DEMS_AGG_VAL_SEL_6                                                                          0x1004a0UL //Access:RW   DataWidth:0x2    // AggValSel used in DEMS mode for DEMS = 6. Bit 2 of AggValSel is always 1 in DEMS mode.
+#define DORQ_REG_DEMS_AGG_CMD_6                                                                              0x1004a4UL //Access:RW   DataWidth:0x2    // AggCmd used in DEMS mode for DEMS = 6. Reset value = SET_AG_CMD.
+#define DORQ_REG_DEMS_TARGET_7                                                                               0x1004a8UL //Access:RW   DataWidth:0x2    // Target value used in DEMS mode for DEMS = 7.
+#define DORQ_REG_DEMS_AGG_VAL_SEL_7                                                                          0x1004acUL //Access:RW   DataWidth:0x2    // AggValSel used in DEMS mode for DEMS = 7. Bit 2 of AggValSel is always 1 in DEMS mode.
+#define DORQ_REG_DEMS_AGG_CMD_7                                                                              0x1004b0UL //Access:RW   DataWidth:0x2    // AggCmd used in DEMS mode for DEMS = 7. Reset value = SET_AG_CMD.
+#define DORQ_REG_PWM_AGG_CMD                                                                                 0x1004f4UL //Access:RW   DataWidth:0x2    // AGG command value in PWM non-DPM mode.
+#define DORQ_REG_CM_AC_UPD                                                                                   0x1004f8UL //Access:RW   DataWidth:0x8    // The initial value for Agg CM messages in case of DPM L2 or DPM abort.
+#define DORQ_REG_WAKE_MISC_EN                                                                                0x1004fcUL //Access:RW   DataWidth:0x1    // Enables sending early wakeup indication towards MISC. This is per port configuration.
+#define DORQ_REG_PF_NET_PORT_ID                                                                              0x100500UL //Access:RW   DataWidth:0x2    // Indicates network port ID that this PF belongs to. In 2 port mode it is equal to 0 for all PF-s. In 4 port mode, it is equal to 0 for even PF-s and to 1 for off PF-s.
+#define DORQ_REG_PF_WAKE_ALL                                                                                 0x100504UL //Access:RW   DataWidth:0x1    // Indicates that a doorbell on this PF should send wakeup indication on all ports. This is a per PF per configuration. Should be set in case of coupled mode teaming. Otherwise should be clear.
+#define DORQ_REG_PF_DB_ENABLE                                                                                0x100508UL //Access:RW   DataWidth:0x1    // Enable doorbells for this PF. In case not set the doorbell is silently dropped. This is a per PF configuration.
+#define DORQ_REG_VF_DB_ENABLE                                                                                0x10050cUL //Access:RW   DataWidth:0x1    // Enable doorbells for this VF. In case not set the doorbell is silently dropped. This is a per VF configuration.
+#define DORQ_REG_PF_DPM_ENABLE                                                                               0x100510UL //Access:RW   DataWidth:0x1    // Enable DPM doorbells for this PF. In case not set the DPM doorbell is aborted. This is a per PF configuration.
+#define DORQ_REG_VF_DPM_ENABLE                                                                               0x100514UL //Access:RW   DataWidth:0x1    // Enable DPM doorbells for all this PF child VF-s. In case not set the DPM doorbell is aborted. This is a per PF configuration.
+#define DORQ_REG_DPM_L2_SUCC_CFLG_CMD                                                                        0x100600UL //Access:RW   DataWidth:0x8    // The value of the counter flag command for successful L2 EDPM.
+#define DORQ_REG_DPM_L2_ABRT_CFLG_CMD                                                                        0x100604UL //Access:RW   DataWidth:0x8    // The value of the counter flag command for unsuccessful L2 EDPM.
+#define DORQ_REG_DPM_L2_SUCC_AGG_CMD                                                                         0x100608UL //Access:RW   DataWidth:0x10   // Aggregation value command in case of successful L2 EDPM.
+#define DORQ_REG_DPM_LEG_ROCE_AGG_CMD                                                                        0x10060cUL //Access:RW   DataWidth:0x10   // Aggregation value command in case of legacy and RoCE EDPM for both abort and success.
+#define DORQ_REG_DPM_L2_ABRT_AGG_CMD                                                                         0x100610UL //Access:RW   DataWidth:0x10   // Aggregation value command in case of aborted L2 EDPM.
+#define DORQ_REG_XCM_AGG_TYPE                                                                                0x1006f8UL //Access:RW   DataWidth:0x5    // The value of AggDecType in CM header in XCM message in case of no ROCE/legacy DPM.
+#define DORQ_REG_UCM_AGG_TYPE                                                                                0x1006fcUL //Access:RW   DataWidth:0x5    // The value of AggDecType in CM header in UCM message.
+#define DORQ_REG_TCM_AGG_TYPE                                                                                0x100700UL //Access:RW   DataWidth:0x5    // The value of AggDecType in CM header in TCM message.
+#define DORQ_REG_XCM_SM_CTX_LD_ST_FLG_DPM                                                                    0x100708UL //Access:RW   DataWidth:0x1    // The value of the SmCtxLdStFlg in XCM header in case of EDPM and legacy DPM.
+#define DORQ_REG_XCM_CCFC_REGN                                                                               0x100800UL //Access:RW   DataWidth:0x8    // The CCFC regions to be loaded on XCM doorbell which is non DPM and non QM bypass doorbells.
+#define DORQ_REG_XCM_CCFC_REGN_BYP                                                                           0x100804UL //Access:RW   DataWidth:0x8    // The CCFC regions to be loaded on XCM doorbell on bypass or DPM.
+#define DORQ_REG_TCM_CCFC_REGN                                                                               0x100808UL //Access:RW   DataWidth:0x8    // The CCFC regions to be loaded on TCM doorbell.
+#define DORQ_REG_UCM_CCFC_REGN                                                                               0x10080cUL //Access:RW   DataWidth:0x8    // The CCFC regions to be loaded on UCM doorbell.
+#define DORQ_REG_CFC_LOAD_MINI_CACHE_EN                                                                      0x100810UL //Access:RW   DataWidth:0x1    // If set then CCFC mini-cache is enabled.
+#define DORQ_REG_DQ_FIFO_AFULL_TH                                                                            0x100814UL //Access:RW   DataWidth:0xa    // DORQ FIFO almost full threshold (in FIFO entries).
+#define DORQ_REG_DPM_XCM_DB_ABRT_TH                                                                          0x100818UL //Access:RW   DataWidth:0xa    // If XCM doorbell counter is above this threshold and first DPM doorbell appears it is truncated to one entry and aborted; non-first doorbell is dropped. (Measured in FIFO entries).
+#define DORQ_REG_DPM_ENT_ABRT_TH                                                                             0x100820UL //Access:RW   DataWidth:0xa    // If DORQ FIFO fill level is above this threshold and first DPM doorbell appears it is truncated to one entry and DpmAbort flag is set; non-first doorbell is silently dropped. Is calculated in entries.
+#define DORQ_REG_MASK_XCM_EN                                                                                 0x100824UL //Access:RW   DataWidth:0x1    // If set, then XCM bypass enable bit will be masked (XCM bypass considered always asserted).
+#define DORQ_REG_MASK_QM_EN                                                                                  0x100828UL //Access:RW   DataWidth:0x1    // If set, then QM bypass enable bit will be masked (considered always asserted).
+#define DORQ_REG_MASK_PBF_ROCE_EN                                                                            0x10082cUL //Access:RW   DataWidth:0x1    // If set, then PBF bypass enable bit will be masked (considered always asserted) for RDMA (RoCE/iWARP) EDPM.
+#define DORQ_REG_MASK_PBF_L2_EN                                                                              0x100830UL //Access:RW   DataWidth:0x1    // If set, then QM bypass enable bit will be masked (considered always asserted) for L2 for L2 EDPM.
+#define DORQ_REG_DPM_TIMEOUT                                                                                 0x100834UL //Access:RW   DataWidth:0xc    // Timeout (measured in main clock cycles) for DPM operation to complete.
+#define DORQ_REG_EDPM_EXIST_IN_QM_EN_BB_K2                                                                   0x100838UL //Access:RW   DataWidth:0x4    // Indicates which ExistInQm bits are taken into account in the EDPM check. If a bit equals 0 then the corresponding ExistInQm is not used (masked).
+#define DORQ_REG_DQ_PXP_FULL_EN                                                                              0x10083cUL //Access:RW   DataWidth:0x1    // If 1, then full is asserted towards PXP when DORQ FIFO fill level is equal or greater than dq_fifo_full_thr. If 0, then doorbell is discarded when DORQ FIFO is full.
+#define DORQ_REG_DQ_FIFO_FULL_TH                                                                             0x100840UL //Access:RW   DataWidth:0xa    // DORQ FIFO full threshold (in FIFO entries). If DORQ FIFO fill level is equal or greater than it and dq_pxp_full_en is 1, then full is asserted towards PXP. If DORQ FIFO fill level is equal or greater than it and dq_pxp_full_en is 0, then full is not asserted towards PXP and doorbell is dropped or truncated.
+#define DORQ_REG_DQ_FULL_CYCLES                                                                              0x100844UL //Access:RW   DataWidth:0xe    // Number of cycles in which full towards PXP is asserted if DORQ is in almost full state.
+#define DORQ_REG_TAG1_ETHERTYPE                                                                              0x100884UL //Access:RW   DataWidth:0x10   // Tag 1 Ethertype used for packet generation in RoCE EDPM mode. Default is set to SVLAN.
+#define DORQ_REG_TAG2_ETHERTYPE                                                                              0x100888UL //Access:RW   DataWidth:0x10   // Tag 2 Ethertype used for packet generation in RoCE EDPM mode. Default is set to CVLAN.
+#define DORQ_REG_TAG3_ETHERTYPE                                                                              0x10088cUL //Access:RW   DataWidth:0x10   // Tag 3 Ethertype used for packet generation in RoCE EDPM mode. Default is set to TTAG.
+#define DORQ_REG_TAG4_ETHERTYPE                                                                              0x100890UL //Access:RW   DataWidth:0x10   // Tag 4 Ethertype used for packet generation in RoCE EDPM mode. Default is set to CN.
+#define DORQ_REG_TAG1_SIZE                                                                                   0x100894UL //Access:RW   DataWidth:0x2    // Size of the Tag 1 used for packet generation in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - 6 bytes;
+#define DORQ_REG_TAG2_SIZE                                                                                   0x100898UL //Access:RW   DataWidth:0x2    // Size of the Tag 2 used for packet generation in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - 6 bytes;
+#define DORQ_REG_TAG3_SIZE                                                                                   0x10089cUL //Access:RW   DataWidth:0x2    // Size of the Tag 3 used for packet generation in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - 6 bytes;
+#define DORQ_REG_TAG4_SIZE                                                                                   0x1008a0UL //Access:RW   DataWidth:0x2    // Size of the Tag 4 used for packet generation in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - 6 bytes;
+#define DORQ_REG_GRH_NXT_HEADER                                                                              0x1008a4UL //Access:RW   DataWidth:0x8    // GRH Next Header used for packet generation in RoCE EDPM.
+#define DORQ_REG_BTH_TVER                                                                                    0x1008a8UL //Access:RW   DataWidth:0x4    // TVER value in RoCE BTH header.
+#define DORQ_REG_ROCE_OPCODE_EN                                                                              0x1008acUL //Access:RW   DataWidth:0x20   // Enable bit per each RoCE Opcode 5 LSB-s. N-th bit set means corresponding opcode N is enabled, if reset the RoCE DPM with this opcode is aborted.
+#define DORQ_REG_CRC32_BSWAP                                                                                 0x1008b0UL //Access:RW   DataWidth:0x1    // If 0 - the RoCE CRC-32 final calculation result isn't byte swapped; if 1 - the CRC-32 final calculation result is byte swapped (byte [7:0] goes to location [31:24];etc).
+#define DORQ_REG_TAG1_OVRD_MODE                                                                              0x1008b4UL //Access:RW   DataWidth:0x3    // Indicates which type of override of the TAG content read from the PCM context is required. The possible values are: 0  No override 1  External VLAN Id only override 2  External VLAN Id + PCP override 3  Internal VLAN Id only override 4  Internal VLAN Id + PCP override Note that this mode is relevant only if size of the TAG (not including the Ethertype) is 2 bytes. Otherwise there is no override.
+#define DORQ_REG_TAG2_OVRD_MODE                                                                              0x1008b8UL //Access:RW   DataWidth:0x3    // Indicates which type of override of the TAG content read from the PCM context is required. The possible values are: 0  No override 1  External VLAN Id only override 2  External VLAN Id + PCP override 3  Internal VLAN Id only override 4  Internal VLAN Id + PCP override Note that this mode is relevant only if size of the TAG (not including the Ethertype) is 2 bytes. Otherwise there is no override.
+#define DORQ_REG_TAG3_OVRD_MODE                                                                              0x1008bcUL //Access:RW   DataWidth:0x3    // Indicates which type of override of the TAG content read from the PCM context is required. The possible values are: 0  No override 1  External VLAN Id only override 2  External VLAN Id + PCP override 3  Internal VLAN Id only override 4  Internal VLAN Id + PCP override Note that this mode is relevant only if size of the TAG (not including the Ethertype) is 2 bytes. Otherwise there is no override.
+#define DORQ_REG_TAG4_OVRD_MODE                                                                              0x1008c0UL //Access:RW   DataWidth:0x3    // Indicates which type of override of the TAG content read from the PCM context is required. The possible values are: 0  No override 1  External VLAN Id only override 2  External VLAN Id + PCP override 3  Internal VLAN Id only override 4  Internal VLAN Id + PCP override Note that this mode is relevant only if size of the TAG (not including the Ethertype) is 2 bytes. Otherwise there is no override.
+#define DORQ_REG_PF_PCP_BB_K2                                                                                0x1008c4UL //Access:RW   DataWidth:0x4    // The priority value and DEI bit of RoCE frames per PF.
+#define DORQ_REG_PF_EXT_VID_BB_K2                                                                            0x1008c8UL //Access:RW   DataWidth:0xc    // The external VLAN ID per PF.
+#define DORQ_REG_RROCE_DST_UDP_PORT                                                                          0x1008ccUL //Access:RW   DataWidth:0x10   // The content of the destination UDP port of RROCE.
+#define DORQ_REG_ROCE_ETHER_TYPE                                                                             0x1008d0UL //Access:RW   DataWidth:0x10   // RoCE Ethertype used for RoCE packet generation in EDPM mode. addr=0  plain ROCE; addr=1  RROCE (ROCEv2)/iWARP over IPV4;  addr=2  RROCE (ROCEv2)/iWARP over IPV6.
+#define DORQ_REG_ROCE_ETHER_TYPE_SIZE                                                                        3
+#define DORQ_REG_L2_EDPM_NUM_BD_THR                                                                          0x100900UL //Access:RW   DataWidth:0x10   // L2 EDPM BDs threshold. If overcome, the L2 EDPM context check fails.
+#define DORQ_REG_L2_EDPM_EXT_HDR_SIZE_BB_K2                                                                  0x100904UL //Access:RW   DataWidth:0x8    // Size in Words of header extracted by PBF and sent to PSTORM in L2.
+#define DORQ_REG_L2_EDPM_EXT_HDR_OFFS_BB_K2                                                                  0x100908UL //Access:RW   DataWidth:0x8    // Offset in Words of header extracted by PBF and sent to PSTORM in L2.
+#define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN                                                                   0x10090cUL //Access:RW   DataWidth:0x1    // Indicates whether Ethernet over GRE header is expected in packet payload.
+#define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN                                                                    0x100910UL //Access:RW   DataWidth:0x1    // Indicates whether IP over GRE header is expected in packet payload.
+#define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN                                                                     0x100914UL //Access:RW   DataWidth:0x1    // Indicates whether VXLAN header is expected in packet payload.
+#define DORQ_REG_L2_EDPM_ST_HINT                                                                             0x100918UL //Access:RW   DataWidth:0x2    // TPH Hint value in case of non-inline L2 EDPM.
+#define DORQ_REG_L2_EDPM_ATC_FLAGS                                                                           0x10091cUL //Access:RW   DataWidth:0x3    // ATC attribute value of non-inline L2 EDPM.
+#define DORQ_REG_PCM_START_OFFS                                                                              0x100920UL //Access:RW   DataWidth:0x5    // Start offset to read PCM STORM context. Measured in REGQ.
+#define DORQ_REG_MAX_L2_EDPM_PKT_SIZE                                                                        0x100924UL //Access:RW   DataWidth:0xe    // Maximum non-inline L2 EDPM PktSize.
+#define DORQ_REG_L2_EDPM_PKT_HDR_SIZE                                                                        0x100928UL //Access:RW   DataWidth:0x8    // The maximum number of WORD-s which the PBF may add to the L2 packet.
+#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5                                                              0x10092cUL //Access:RW   DataWidth:0x1    // Set to 1 if IP over NGE header is expected in the packet payload.
+#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5                                                             0x100930UL //Access:RW   DataWidth:0x1    // Set to 1 if Ethernet over NGE header is expected in the packet payload.
+#define DORQ_REG_XCM_MSG_INIT_CRD                                                                            0x100980UL //Access:RW   DataWidth:0x3    // XCM message interface initial credit.
+#define DORQ_REG_TCM_MSG_INIT_CRD                                                                            0x100984UL //Access:RW   DataWidth:0x3    // TCM message interface initial credit.
+#define DORQ_REG_UCM_MSG_INIT_CRD                                                                            0x100988UL //Access:RW   DataWidth:0x3    // UCM message interface initial credit.
+#define DORQ_REG_PBF_CMD_INIT_CRD                                                                            0x10098cUL //Access:RW   DataWidth:0x6    // PBF command interface initial credit.
+#define DORQ_REG_PF_USAGE_CNT                                                                                0x1009c0UL //Access:R    DataWidth:0xb    // Counter of DORQ FIFO entries used by corresponding PF or any of its child VF-s.
+#define DORQ_REG_VF_USAGE_CNT                                                                                0x1009c4UL //Access:R    DataWidth:0xb    // Counter of DORQ FIFO entries used by corresponding VF.
+#define DORQ_REG_PF_USAGE_CNT_LIM                                                                            0x1009c8UL //Access:RW   DataWidth:0xb    // Maximum number of DORQ FIFO entries used by corresponding PF or any of its child VF-s. This is a per PF configuration.
+#define DORQ_REG_VF_USAGE_CNT_LIM                                                                            0x1009ccUL //Access:RW   DataWidth:0xb    // Maximum number of DORQ FIFO entries used by a VF which is a child VF of corresponding PF. This is a per PF configuration.
+#define DORQ_REG_PF_OVFL_STICKY                                                                              0x1009d0UL //Access:RW   DataWidth:0x1    // If set, PF doorbell with corresponding PF is silently dropped at the entrance to DORQ FIFO. This is a per PF configuration. Is cleared by write of 0.
+#define DORQ_REG_VF_OVFL_STICKY                                                                              0x1009d4UL //Access:RW   DataWidth:0x1    // If set, VF doorbell with corresponding VF, is silently dropped at the entrance to DORQ FIFO. This is a per VF configuration. Is cleared by write of 0.
+#define DORQ_REG_DPM_FORCE_ABORT                                                                             0x1009d8UL //Access:W    DataWidth:0x1    // Aborts all the current DPM entries which are not FREE.
+#define DORQ_REG_DB_DROP_REASON_MASK                                                                         0x1009dcUL //Access:RW   DataWidth:0x14   // A bit mask per doorbell drop reason. If a bit is set (1), then corresponding drop reason will cause attention be set. If a bit is not set (0), then corresponding drop reason will not cause interrupt.
+#define DORQ_REG_AUTO_FREEZE_EN                                                                              0x1009e0UL //Access:RW   DataWidth:0x1    // If set, DORQ enters freeze mode on the first doorbell drop due to DORQ FIFO overflow. The freeze mode means that DORQ stops sending CFC load requests. The freeze mode will remain until auto_drop_rel (Write Only) register is set.
+#define DORQ_REG_AUTO_FREEZE_ST                                                                              0x1009e4UL //Access:R    DataWidth:0x1    // When set, auto freeze is active and doorbells are not being popped from the FIFO. Cleared when auto_freeze_rel is written.
+#define DORQ_REG_AUTO_FREEZE_REL                                                                             0x1009e8UL //Access:W    DataWidth:0x1    // Release the freeze mode set by auto_freeze_en. Write only.
+#define DORQ_REG_AUTO_DROP_EN                                                                                0x1009ecUL //Access:RW   DataWidth:0x1    // If set, DORQ enters auto drop mode on the first doorbell drop due to DORQ FIFO overflow. In this mode all incoming doorbells will be dropped even if the FIFO is not full anymore. The drop mode will remain until auto_drop_rel (Write Only) register is set.
+#define DORQ_REG_AUTO_DROP_ST                                                                                0x1009f0UL //Access:R    DataWidth:0x1    // When set, auto discard mode is active and all doorbells are dropped at the entrance to DORQ FIFO.  De-asserted when auto_discard_rel is written.
+#define DORQ_REG_AUTO_DROP_REL                                                                               0x1009f4UL //Access:W    DataWidth:0x1    // Releases the auto_drop mode. Write only.
+#define DORQ_REG_PXP_TRANS_SIZE                                                                              0x1009f8UL //Access:RW   DataWidth:0x8    // Size in bytes of the PXP transactions to be counted in the pxp_trans_cnt register (including address cycle).
+#define DORQ_REG_DB_INGRESS_CNT                                                                              0x1009fcUL //Access:R    DataWidth:0x20   // Accounts for any non-DPM doorbell or first DPM doorbell, which are not silently dropped. Will rollover to 0 when incremented above all ones.
+#define DORQ_REG_DB_EGRESS_CNT                                                                               0x100a00UL //Access:R    DataWidth:0x20   // Incremented for each message sent to any one of CMs. Will rollover to 0 when incremented above all ones.
+#define DORQ_REG_CFC_LD_MAX_OUTS_REQ                                                                         0x100a04UL //Access:RW   DataWidth:0x6    // Maximum allowed number of outstanding CFC load requests.
+#define DORQ_REG_CFC_LD_REQ_FIFO_FILL_LVL                                                                    0x100a08UL //Access:R    DataWidth:0x6    // CFC load request FIFO current fill level (in entries).
+#define DORQ_REG_DORQ_FIFO_FILL_LVL                                                                          0x100a0cUL //Access:R    DataWidth:0xb    // DORQ FIFO current fill level (in entries REGQ each).
+#define DORQ_REG_DORQ_FIFO_FILL_LVL_ST                                                                       0x100a10UL //Access:RC   DataWidth:0xb    // DORQ FIFO sticky fill level (in entries REGQ each). Is cleared on read.
+#define DORQ_REG_DORQ_FIFO_NXT_INF_UNIT                                                                      0x100a14UL //Access:R    DataWidth:0x5    // Debug only: read from DORQ FIFO: number of reads to next information unit.
+#define DORQ_REG_DB_DROP_CNT                                                                                 0x100a18UL //Access:R    DataWidth:0x20   // Accounts for number of dropped doorbells. See db_drop_reason for drop reason.  Will rollover to 0 when incremented above all ones.
+#define DORQ_REG_DB_DROP_DETAILS_ADDRESS                                                                     0x100a1cUL //Access:R    DataWidth:0x20   // Stores the details of the first dropped doorbell after logging was re-armed by db_drop_details_rel. The following details of the transaction will be recorded: Doorbell address (in  case of drops from DORQ FIFO DpmOffset is stored)..
+#define DORQ_REG_DB_DROP_DETAILS_REASON                                                                      0x100a20UL //Access:R    DataWidth:0x14   // Stores the details of the first dropped doorbell after logging was re-armed by db_drop_details_rel. The following details of the transaction will be recorded: Doorbell drop reason: 0 - Size of the data is not equal to 4 or to a multiple of 8 bytes; 1 - 2 LSB-s of the address are not zeroes (no DWORD alignment); 2 - The size of the data in the transaction is a multiple of 8 bytes and the 3 LSB-s of the address are not zeroes (not QWORD aligned); 3 - ICID is out of maximum allowed range; 4 - PWM doorbell to reserved register; 5 - Size miss-match: 32b doorbell (non-DPM) written to 64b register (non-DPM or DPM). Will be distinguished as the write with (pxp_dorq_eop_bvalid=4) to 64b PWM register; 6 - DPI check is not supported for this connection/task type and DPI is not zero; 7 - Non-first DPM doorbell and FIFO fill level (in QREG-s) is above a threshold (dpm_ent_abrt_th). 8 - Non-first DPM doorbell and XCM doorbell counter is above the threshold (dpm_xcm_db_abrt_th); 9 - PF doorbell appears and its corresponding PF sticky overflow bit (pf_ovfl_sticky[pf]) is set; 10 - VF doorbell appears and its corresponding VF sticky overflow bit (vf_ovfl_sticky[vf]) is set or its corresponding parent PF sticky overflow bit (pf_ovfl_sticky[pf]) is set (or both); 11 - PF doorbell appears and its corresponding PF is disabled in pf_db_en; 12 - VF doorbell appears and its corresponding PF is disabled in vf_db_en; 13 - Global overflow; 14 - The first byte enable field is not equal to all ones; 15 - The length (in DWORD-s) of the transaction is more than 1 payload DWORD and the last byte enable is not equal to all ones 16 - Auto drop 17 - Non first DPM doorbell arrived and there is no matching DPM entry 18 - Non first DPM doorbell arrived and non-contigious offset in a DPM transaction 19 - Non first DPM doorbell arrived beyond the DPM size
+#define DORQ_REG_DB_DROP_DETAILS                                                                             0x100a24UL //Access:R    DataWidth:0x17   // Stores the details of the first dropped doorbell after logging was re-armed by db_drop_details_rel. The following details of the transaction will be recorded: bits[15:0]   Doorbell opaque FID; bits[22:16]  Doorbell size in in DWords (calculated according to "length");
+#define DORQ_REG_DB_DROP_DETAILS_REL                                                                         0x100a28UL //Access:W    DataWidth:0x1    // Clears db_drop_details and makes it ready for the next details capture. Write only.
+#define DORQ_REG_DB_DROP_REASON                                                                              0x100a2cUL //Access:R    DataWidth:0x14   // Sticky status of drop reason (a bit per reason). It is reset on write to db_drop_details_rel. 0 - Size of the data is not equal to 4 or to a multiple of 8 bytes; 1 - 2 LSB-s of the address are not zeroes (no DWORD alignment); 2 - The size of the data in the transaction is a multiple of 8 bytes and the 3 LSB-s of the address are not zeroes (not QWORD aligned); 3 - ICID is out of maximum allowed range; 4 - PWM doorbell to reserved register; 5 - Size miss-match: 32b doorbell (non-DPM) written to 64b register (non-DPM or DPM). Will be distinguished as the write with (pxp_dorq_eop_bvalid=4) to 64b PWM register; 6 - DPI check is not supported for this connection/task type and DPI is not zero; 7 - Non-first DPM doorbell and FIFO fill level (in QREG-s) is above a threshold (dpm_ent_abrt_th). 8 - Non-first DPM doorbell and XCM doorbell counter is above the threshold (dpm_xcm_db_abrt_th); 9 - PF doorbell appears and its corresponding PF sticky overflow bit (pf_ovfl_sticky[pf]) is set; 10 - VF doorbell appears and its corresponding VF sticky overflow bit (vf_ovfl_sticky[vf]) is set or its corresponding parent PF sticky overflow bit (pf_ovfl_sticky[pf]) is set (or both); 11 - PF doorbell appears and its corresponding PF is disabled in pf_db_en; 12 - VF doorbell appears and its corresponding PF is disabled in pf_db_en or its VF is disabled in vf_db_en; 13 - Global overflow; 14 - The first byte enable field is not equal to all ones; 15 - The length (in DWORD-s) of the transaction is more than 1 payload DWORD and the last byte enable is not equal to all ones 16 - Autodrop 17 - Non first DPM doorbell arrived and there is no matching DPM entry 18 - Non first DPM doorbell arrived and non-contigious offset in a DPM transaction 19 - Non first DPM doorbell arrived beyond the DPM size
+#define DORQ_REG_DPM_ABORT_CNT                                                                               0x100a30UL //Access:R    DataWidth:0x20   // Accounts for number of aborted doorbells. See dpm_abort_reason for abort reason. Will rollover to 0 when incremented above all ones.
+#define DORQ_REG_DPM_ABORT_DETAILS_DB_VAL                                                                    0x100a34UL //Access:R    DataWidth:0x10   // Stores the details of the first aborted doorbell after this register was cleared. It is reset on write to db_abort_details_rel. The following details of the transaction will be recorded: DbVal[15:0].
+#define DORQ_REG_DPM_ABORT_DETAILS_WID                                                                       0x100a38UL //Access:R    DataWidth:0x8    // Stores the details of the first aborted doorbell after this register was cleared. It is reset on write to db_abort_details_rel. The following details of the transaction will be recorded: Doorbell WID;
+#define DORQ_REG_DPM_ABORT_DETAILS_DPI                                                                       0x100a3cUL //Access:R    DataWidth:0x10   // Stores the details of the first aborted doorbell after this register was cleared. It is reset on write to db_abort_details_rel. The following details of the transaction will be recorded: bits[15:0]    Doorbell DPI;
+#define DORQ_REG_DPM_ABORT_DETAILS_CID                                                                       0x100a40UL //Access:R    DataWidth:0x20   // Stores the details of the first aborted doorbell after this register was cleared. It is reset on write to db_abort_details_rel. The following details of the transaction will be recorded: Doorbell CID;
+#define DORQ_REG_DPM_ABORT_DETAILS_REASON                                                                    0x100a44UL //Access:R    DataWidth:0x13   // Stores the details of the first aborted doorbell after this register was cleared. It is reset on write to db_abort_details_rel. The following details of the transaction will be recorded: 0 - DPM doorbell and rewind configuration of DPM timer (dpm_timeout) is 0; 1 - PF DPM doorbell and its corresponding PF is disabled in pf_dpm_en; 2 - VF DPM doorbell and its corresponding PF is disabled in vf_dpm_en; 3 - First DPM doorbell and FIFO fill level (in QREG-s) is above threshold (dpm_ent_abrt_th); 4 - First DPM doorbell and XCM doorbell counter is above threshold (dpm_xcm_db_abrt_th); 5 - First DPM doorbell and illegal DpmSize; 6 - First DPM doorbell and illegal WqeSize/PktSize; 7 - First DPM doorbell and illegal RoCEFlags/SgeNum; 8 - First RoCE EDPM doorbell and opcode[4:0] does not match allowed by roce_opcode_en; 9 - Non-DPM or first DPM doorbell with CID of not fully collected DPM doorbell in WQE buffer; 10 - First DPM doorbell with {fid,dpi,wid} of not fully collected DPM doorbell in WQE buffer; 11 - First DPM doorbell does not match DPM global start conditions; 12 - Non-first DPM doorbell with {fid,dpi,wid} of DPM doorbell in WQE buffer and matched doorbell offset is not contiguous; 13 - CFC load response with error; 14 - EDPM context check fails; 15 - DPM timer expired; 16 - Force abort; 17 - Size mis-match: 32b doorbell (normal region or PWM non-DPM) is written to DpmReg[0]; 18 - First iWARP EDPM doorbell and opcode[4:0] does not match allowed by iwaqrp_opcode_en;
+#define DORQ_REG_DPM_ABORT_DETAILS_REL                                                                       0x100a48UL //Access:W    DataWidth:0x1    // Clears db_abort_details and makes it ready for the next details capture. Write only.
+#define DORQ_REG_DPM_ABORT_REASON                                                                            0x100a4cUL //Access:R    DataWidth:0x13   // Sticky status of abort reason (a bit per reason). It is reset on write to db_abort_details_rel. 0 - DPM doorbell and rewind configuration of DPM timer (dpm_timeout) is 0; 1 - First DPM doorbell and PF DPM doorbell and its corresponding PF is disabled in pf_dpm_en; 2 - First DPM doorbell and VF DPM doorbell and its corresponding PF is disabled in vf_dpm_en; 3 - First DPM doorbell and FIFO fill level (in QREG-s) is above threshold (dpm_ent_abrt_th); 4 - First DPM doorbell and XCM doorbell counter is above threshold (dpm_xcm_db_abrt_th); 5 - First DPM doorbell and illegal DpmSize; 6 - First DPM doorbell and illegal WqeSize/PktSize; 7 - First DPM doorbell and illegal RoCEFlags/SgeNum; 8 - First RoCE EDPM doorbell and opcode[4:0] does not match allowed by roce_opcode_en; 9 - Non-DPM or first DPM doorbell with CID of not fully collected DPM doorbell in WQE buffer; 10 - First DPM doorbell with {fid,dpi,wid} of not fully collected DPM doorbell in WQE buffer; 11 - First DPM doorbell does not match DPM global start conditions; 12 - Non-first DPM doorbell with {fid,dpi,wid} of DPM doorbell in WQE buffer and matched doorbell offset is not contiguous; 13 - CFC load response with error; 14 - EDPM context check fails; 15 - DPM timer expired; 16 - Force abort; 17 - Size mis-match: 32b doorbell (normal region or PWM non-DPM) is written to DpmReg[0]; 18 - First iWARP EDPM doorbell and opcode[4:0] does not match allowed by iwarp_opcode_en;
+#define DORQ_REG_DB_EARLY_TRUNC_CNT                                                                          0x100a50UL //Access:RC   DataWidth:0x20   // Truncation counter. It is reset on read.
+#define DORQ_REG_DPM_EARLY_ABORT_CNT                                                                         0x100a54UL //Access:RC   DataWidth:0x20   // DPM early abort counter. It is reset on read.
+#define DORQ_REG_DPM_TIMER_EXPIR_ABORT_CNT                                                                   0x100a58UL //Access:RC   DataWidth:0x20   // DPM timer expiration abort counter. It is reset on read.
+#define DORQ_REG_DPM_GLB_COND_ABORT_CNT                                                                      0x100a5cUL //Access:RC   DataWidth:0x20   // DPM global condition abort counter for External EDPM doorbell. It is reset on read.
+#define DORQ_REG_DPM_CTX_CHECK_ABORT_CNT                                                                     0x100a60UL //Access:RC   DataWidth:0x20   // DPM context check failure abort counter for External EDPM doorbell. It is reset on read.
+#define DORQ_REG_DPM_UNCOMPL_ABORT_CNT                                                                       0x100a64UL //Access:RC   DataWidth:0x20   // DPM uncompleted (arrival of first DPM first on a CID which already has a DPM entry pending for data) abort counter. It is reset on read.
+#define DORQ_REG_DPM_ILLEG_SIZE_ABORT_CNT                                                                    0x100a68UL //Access:RC   DataWidth:0x20   // DPM Illegal value of DpmSize, WqeSize/PktSize or SgeNum abort counter. It is reset on read.
+#define DORQ_REG_DPM_LEG_SUCCESS_CNT                                                                         0x100a6cUL //Access:RC   DataWidth:0x20   // Number of successfull legacy DPM doorbells. It is reset on read.
+#define DORQ_REG_DPM_ROCE_SUCCESS_CNT                                                                        0x100a70UL //Access:RC   DataWidth:0x20   // Number of successfull RoCE EDPM doorbells. It is reset on read.
+#define DORQ_REG_DPM_L2_SUCCESS_CNT                                                                          0x100a74UL //Access:RC   DataWidth:0x20   // Number of successfull L2 EDPM doorbells. It is reset on read.
+#define DORQ_REG_DPM_DATA_CNT                                                                                0x100a78UL //Access:R    DataWidth:0x20   // Counter for overall number of DPM doorbells data QWords. Will be calculated by accounting for any first DPM doorbell DpmSize indication.
+#define DORQ_REG_DPM_EARLY_ABORT_DATA_CNT                                                                    0x100a7cUL //Access:R    DataWidth:0x20   // Counter for the number of DPM doorbells data QWords which were silently dropped or aborted due to early abort. Only first DPM doorbells, which are silently dropped or early aborted will be considered. The increment will be done at first cycle of first DPM doorbell by the size of DpmSize. No non-first DPM doorbells silent drops or aborts are considered.
+#define DORQ_REG_DPM_FIFO_POP_ABORT_DATA_CNT                                                                 0x100a80UL //Access:R    DataWidth:0x20   // Counter for the number of DPM doorbells data QWords which were discarded or aborted on FIFO pop. Only silent drops and aborts that can be distinguished at the moment of DORQ FIFO pop will be considered and specifically only doorbell that is aborted due to DPM global start conditions.
+#define DORQ_REG_PXP_TRANS_CNT                                                                               0x100a84UL //Access:RC   DataWidth:0x20   // Number of PXP transaction of a selected size (including non DPM). The selected size can be a number which is a power of 2 which is between 4 to 256. It is reset on read.
+#define DORQ_REG_DPM_TBL_FILL_LVL                                                                            0x100a88UL //Access:R    DataWidth:0x4    // DPM Table fill level.
+#define DORQ_REG_CFC_BYPASS_CNT                                                                              0x100a8cUL //Access:RC   DataWidth:0x20   // Counts the number of times CFC bypass occurred.
+#define DORQ_REG_MINI_CACHE_ENTRY                                                                            0x100a90UL //Access:WB_R DataWidth:0x32   // Debug only: In case of LCID validation error or load error, the current value of the single entry in the CID load mini-cache is captured. 49: Valid, 48:40 - LCID, 39:32 - Region, 31:0 - CID
+#define DORQ_REG_MINI_CACHE_ENTRY_SIZE                                                                       2
+#define DORQ_REG_CFC_LCRES_ERR_DETAIL                                                                        0x100a98UL //Access:WB_R DataWidth:0x25   // Debug only: CFC Response error in case mini-cache was used. 36 - CDU Validation Error; 35 - CFC Load Cancel; 34 - CFC Load Error; 33 - CFC LCID validation error; 32 - Doorbell type (0 - non-DPM, 1 - DPM); 31:0 - CID.
+#define DORQ_REG_CFC_LCRES_ERR_DETAIL_SIZE                                                                   2
+#define DORQ_REG_CFC_LD_REQ_CNT                                                                              0x100aa0UL //Access:RC   DataWidth:0x20   // The number of CCFC load requests sent (no bypass).
+#define DORQ_REG_CFC_ERR_CNT                                                                                 0x100aa4UL //Access:RC   DataWidth:0x8    // Counts the number of CFC load errors.
+#define DORQ_REG_ECO_RESERVED                                                                                0x100aa8UL //Access:RW   DataWidth:0x8    // Chicken bits.
+#define DORQ_REG_IEDPM_PAYLOAD_ENDIANITY_E5                                                                  0x100aacUL //Access:RW   DataWidth:0x1    // comment="Selects IEDPM payload endianity. 0 - little endian (lsB first); 1 - big endian (msB first)"
+#define DORQ_REG_MEMCTRL_WR_RD_N_BB                                                                          0x100ac0UL //Access:RW   DataWidth:0x1    // wr/rd indication to CPU BIST
+#define DORQ_REG_MEMCTRL_CMD_BB                                                                              0x100ac4UL //Access:RW   DataWidth:0x8    // command to CPU BIST
+#define DORQ_REG_MEMCTRL_ADDRESS_BB                                                                          0x100ac8UL //Access:RW   DataWidth:0x8    // address to CPU BIST
+#define DORQ_REG_MEMCTRL_STATUS                                                                              0x100accUL //Access:R    DataWidth:0x20   // status from CPU BIST
+#define DORQ_REG_DBG_SELECT                                                                                  0x100ad0UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define DORQ_REG_DBG_DWORD_ENABLE                                                                            0x100ad4UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define DORQ_REG_DBG_SHIFT                                                                                   0x100ad8UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define DORQ_REG_DBG_FORCE_VALID                                                                             0x100adcUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define DORQ_REG_DBG_FORCE_FRAME                                                                             0x100ae0UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define DORQ_REG_DBG_OUT_DATA                                                                                0x100b00UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define DORQ_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define DORQ_REG_DBG_OUT_VALID                                                                               0x100b20UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define DORQ_REG_DBG_OUT_FRAME                                                                               0x100b24UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define DORQ_REG_DPM_TBL                                                                                     0x100c00UL //Access:WB_R DataWidth:0xc7   // Read access to DPM Table. Fields mapping is: [198:195] - DPM FSM state [194:192] - DbAggValSel [191:190] - DbAggCmd [189:182] - DbAggFlgCmd [181] - IEDPM Use message PSN flag [180] - IEDPM done required [179:177] - IEDPM done request ID [176:173] - IEDPM done source client ID [172:161] - IEDPM check enable[11:0] [160] - IEDPM Exist (indicates if it is IEDPM doorbell) [159:144] - ICID [143:128] - FID16 [127:119] - LCID [118:103] - DbVal[15:0] [102:95] - WID (non-IEDPM)/PSN[23:16] (IEDPM) [94:79] - DPI (non-IEDPM)/PSN[15:0] (IEDPM) [78] - DPI validation requested [77:72] - DpmCnt (number of received QWords) [71:66] - DpmSize [65] - Abort [64:63] - DPM Type [62:59] - Connection Type [58:51] - Opcode/Number of BDs [50:40] - WqeSize/PktSize [39:37] - RoCEFlg/NumSge [36] - CFC response happened [35] - DPM global start not fulfilled [34] - CFC CDU error [33] - CFC Load error [32] - CFC Cancel error [31:0]  - DpmReg0(Dw1)
+#define DORQ_REG_DPM_TBL_SIZE_BB_K2                                                                          64
+#define DORQ_REG_DPM_TBL_SIZE_E5                                                                             96
+#define DORQ_REG_WQE_BUF                                                                                     0x101000UL //Access:RW   DataWidth:0x20   // 1) Debug read access to WQE buffer. 2) Initialization write access: write all the addresses modulo 8, i.e. 0, 8, .., 632. The access is allowed only on sleeping block, i.e. when it is guaranteed there is no WQE buffer activity.
+#define DORQ_REG_WQE_BUF_SIZE                                                                                640
+#define DORQ_REG_IEDPM_BUF_E5                                                                                0x102000UL //Access:RW   DataWidth:0x20   // 1) Debug read access to WQE buffer. 2) Initialization write access: write all the addresses modulo 8, i.e. 0, 8, .., 312 to eliminate false parity error of IEDPM buffer 3. The access is allowed only on sleeping block, i.e. when it is guaranteed there is no IEDPM buffer activity.
+#define DORQ_REG_IEDPM_BUF_SIZE                                                                              320
+#define DORQ_REG_GLB_MAX_ICID_0_E5                                                                           0x102800UL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of ICID range 0.
+#define DORQ_REG_GLB_MAX_ICID_1_E5                                                                           0x102804UL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of ICID range 1.
+#define DORQ_REG_GLB_RANGE2CONN_TYPE_0_E5                                                                    0x102808UL //Access:RW   DataWidth:0x4    // Maps range 0 to connection type.
+#define DORQ_REG_GLB_RANGE2CONN_TYPE_1_E5                                                                    0x10280cUL //Access:RW   DataWidth:0x4    // Maps range 1 to connection type.
+#define DORQ_REG_PRV_PF_MAX_ICID_2_E5                                                                        0x102810UL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of range 2. This is per PF per range configuration.
+#define DORQ_REG_PRV_PF_MAX_ICID_3_E5                                                                        0x102814UL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of range 3. This is per PF per range configuration.
+#define DORQ_REG_PRV_PF_MAX_ICID_4_E5                                                                        0x102818UL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of range 4. This is per PF per range configuration.
+#define DORQ_REG_PRV_PF_MAX_ICID_5_E5                                                                        0x10281cUL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of range 5. This is per PF per range configuration.
+#define DORQ_REG_PRV_VF_MAX_ICID_2_E5                                                                        0x102820UL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of range 2. This is per PF per range configuration.
+#define DORQ_REG_PRV_VF_MAX_ICID_3_E5                                                                        0x102824UL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of range 3. This is per PF per range configuration.
+#define DORQ_REG_PRV_VF_MAX_ICID_4_E5                                                                        0x102828UL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of range 4. This is per PF per range configuration.
+#define DORQ_REG_PRV_VF_MAX_ICID_5_E5                                                                        0x10282cUL //Access:RW   DataWidth:0xc    // The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of range 5. This is per PF per range configuration.
+#define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_2_E5                                                                 0x102830UL //Access:RW   DataWidth:0x4    // Maps range 2 to connection type. This is per PF per range configuration.
+#define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_3_E5                                                                 0x102834UL //Access:RW   DataWidth:0x4    // Maps range 3 to connection type. This is per PF per range configuration.
+#define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_4_E5                                                                 0x102838UL //Access:RW   DataWidth:0x4    // Maps range 4 to connection type. This is per PF per range configuration.
+#define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_5_E5                                                                 0x10283cUL //Access:RW   DataWidth:0x4    // Maps range 5 to connection type. This is per PF per range configuration.
+#define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_2_E5                                                                 0x102840UL //Access:RW   DataWidth:0x4    // Mas range 2 to connection type. This is per PF per range configuration.
+#define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_3_E5                                                                 0x102844UL //Access:RW   DataWidth:0x4    // Mas range 3 to connection type. This is per PF per range configuration.
+#define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_4_E5                                                                 0x102848UL //Access:RW   DataWidth:0x4    // Mas range 4 to connection type. This is per PF per range configuration.
+#define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_5_E5                                                                 0x10284cUL //Access:RW   DataWidth:0x4    // Mas range 5 to connection type. This is per PF per range configuration.
+#define DORQ_REG_IEDPM_EXIST_IN_QM_EN_E5                                                                     0x102850UL //Access:RW   DataWidth:0x4    // Indicates which ExistInQm bits are taken into account in the IEDPM check. If a bit equals 0 then the corresponding ExistInQm is not used (masked).
+#define DORQ_REG_IEDPM_AGG_TYPE_E5                                                                           0x102854UL //Access:RW   DataWidth:0x5    // The value of the AggDecType in the XCM message in IEDPM input.
+#define DORQ_REG_EDPM_AGG_TYPE_BB_K2                                                                         0x100704UL //Access:RW   DataWidth:0x5    // The value of the AggDecType in the XCM message in case of legacy DPM and ROCE EDPM and QM bypass.
+#define DORQ_REG_EDPM_AGG_TYPE_E5                                                                            0x102858UL //Access:RW   DataWidth:0x5    // The value of the AggDecType in the XCM message in case of legacy DPM and RDMA EDPM.
+#define DORQ_REG_EDPM_AGG_TYPE_SIZE_E5                                                                       2
+#define DORQ_REG_QM_BYP_AGG_TYPE_E5                                                                          0x102860UL //Access:RW   DataWidth:0x5    // The value of the AggDecType in the XCM message in case QM bypass.
+#define DORQ_REG_QM_BYP_AGG_TYPE_SIZE                                                                        2
+#define DORQ_REG_EDPM_AGG_TYPE_SEL_0_E5                                                                      0x102868UL //Access:RW   DataWidth:0x2    // Value which will select which one of two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for RDMA doorbell. Per connection type 0.
+#define DORQ_REG_EDPM_AGG_TYPE_SEL_1_E5                                                                      0x10286cUL //Access:RW   DataWidth:0x2    // Value which will select which one of two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for RDMA doorbell. Per connection type 1.
+#define DORQ_REG_EDPM_AGG_TYPE_SEL_2_E5                                                                      0x102870UL //Access:RW   DataWidth:0x2    // Value which will select which one of two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for RDMA doorbell. Per connection type 2.
+#define DORQ_REG_EDPM_AGG_TYPE_SEL_3_E5                                                                      0x102874UL //Access:RW   DataWidth:0x2    // Value which will select which one of two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for RDMA doorbell. Per connection type 3.
+#define DORQ_REG_EDPM_AGG_TYPE_SEL_4_E5                                                                      0x102878UL //Access:RW   DataWidth:0x2    // Value which will select which one of two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for RDMA doorbell. Per connection type 4.
+#define DORQ_REG_EDPM_AGG_TYPE_SEL_5_E5                                                                      0x10287cUL //Access:RW   DataWidth:0x2    // Value which will select which one of two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for RDMA doorbell. Per connection type 5.
+#define DORQ_REG_EDPM_AGG_TYPE_SEL_6_E5                                                                      0x102880UL //Access:RW   DataWidth:0x2    // Value which will select which one of two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for RDMA doorbell. Per connection type 6.
+#define DORQ_REG_EDPM_AGG_TYPE_SEL_7_E5                                                                      0x102884UL //Access:RW   DataWidth:0x2    // Value which will select which one of two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for RDMA doorbell. Per connection type 7.
+#define DORQ_REG_EDPM_AGG_TYPE_SEL_8_E5                                                                      0x102888UL //Access:RW   DataWidth:0x2    // Value which will select which one of two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for RDMA doorbell. Per connection type 8.
+#define DORQ_REG_EDPM_AGG_TYPE_SEL_9_E5                                                                      0x10288cUL //Access:RW   DataWidth:0x2    // Value which will select which one of two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for RDMA doorbell. Per connection type 9.
+#define DORQ_REG_EDPM_AGG_TYPE_SEL_10_E5                                                                     0x102890UL //Access:RW   DataWidth:0x2    // Value which will select which one of two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for RDMA doorbell. Per connection type 10.
+#define DORQ_REG_EDPM_AGG_TYPE_SEL_11_E5                                                                     0x102894UL //Access:RW   DataWidth:0x2    // Value which will select which one of two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for RDMA doorbell. Per connection type 11.
+#define DORQ_REG_EDPM_AGG_TYPE_SEL_12_E5                                                                     0x102898UL //Access:RW   DataWidth:0x2    // Value which will select which one of two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for RDMA doorbell. Per connection type 12.
+#define DORQ_REG_EDPM_AGG_TYPE_SEL_13_E5                                                                     0x10289cUL //Access:RW   DataWidth:0x2    // Value which will select which one of two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for RDMA doorbell. Per connection type 13.
+#define DORQ_REG_EDPM_AGG_TYPE_SEL_14_E5                                                                     0x1028a0UL //Access:RW   DataWidth:0x2    // Value which will select which one of two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for RDMA doorbell. Per connection type 14.
+#define DORQ_REG_EDPM_AGG_TYPE_SEL_15_E5                                                                     0x1028a4UL //Access:RW   DataWidth:0x2    // Value which will select which one of two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for RDMA doorbell. Per connection type 15.
+#define DORQ_REG_QM_BYP_AGG_TYPE_SEL_0_E5                                                                    0x1028a8UL //Access:RW   DataWidth:0x1    // Value which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per connection type 0.
+#define DORQ_REG_QM_BYP_AGG_TYPE_SEL_1_E5                                                                    0x1028acUL //Access:RW   DataWidth:0x1    // Value which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per connection type 1.
+#define DORQ_REG_QM_BYP_AGG_TYPE_SEL_2_E5                                                                    0x1028b0UL //Access:RW   DataWidth:0x1    // Value which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per connection type 2.
+#define DORQ_REG_QM_BYP_AGG_TYPE_SEL_3_E5                                                                    0x1028b4UL //Access:RW   DataWidth:0x1    // Value which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per connection type 3.
+#define DORQ_REG_QM_BYP_AGG_TYPE_SEL_4_E5                                                                    0x1028b8UL //Access:RW   DataWidth:0x1    // Value which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per connection type 4.
+#define DORQ_REG_QM_BYP_AGG_TYPE_SEL_5_E5                                                                    0x1028bcUL //Access:RW   DataWidth:0x1    // Value which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per connection type 5.
+#define DORQ_REG_QM_BYP_AGG_TYPE_SEL_6_E5                                                                    0x1028c0UL //Access:RW   DataWidth:0x1    // Value which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per connection type 6.
+#define DORQ_REG_QM_BYP_AGG_TYPE_SEL_7_E5                                                                    0x1028c4UL //Access:RW   DataWidth:0x1    // Value which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per connection type 7.
+#define DORQ_REG_QM_BYP_AGG_TYPE_SEL_8_E5                                                                    0x1028c8UL //Access:RW   DataWidth:0x1    // Value which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per connection type 8.
+#define DORQ_REG_QM_BYP_AGG_TYPE_SEL_9_E5                                                                    0x1028ccUL //Access:RW   DataWidth:0x1    // Value which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per connection type 9.
+#define DORQ_REG_QM_BYP_AGG_TYPE_SEL_10_E5                                                                   0x1028d0UL //Access:RW   DataWidth:0x1    // Value which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per connection type 10.
+#define DORQ_REG_QM_BYP_AGG_TYPE_SEL_11_E5                                                                   0x1028d4UL //Access:RW   DataWidth:0x1    // Value which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per connection type 11.
+#define DORQ_REG_QM_BYP_AGG_TYPE_SEL_12_E5                                                                   0x1028d8UL //Access:RW   DataWidth:0x1    // Value which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per connection type 12.
+#define DORQ_REG_QM_BYP_AGG_TYPE_SEL_13_E5                                                                   0x1028dcUL //Access:RW   DataWidth:0x1    // Value which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per connection type 13.
+#define DORQ_REG_QM_BYP_AGG_TYPE_SEL_14_E5                                                                   0x1028e0UL //Access:RW   DataWidth:0x1    // Value which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per connection type 14.
+#define DORQ_REG_QM_BYP_AGG_TYPE_SEL_15_E5                                                                   0x1028e4UL //Access:RW   DataWidth:0x1    // Value which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per connection type 15.
+#define DORQ_REG_QM_EN_BYP_MASK_0_BB_K2                                                                      0x1004b4UL //Access:RW   DataWidth:0x1    // QM Bypass mode is enabled for XCM messages for connection type 0.
+#define DORQ_REG_QM_EN_BYP_MASK_0_E5                                                                         0x1028e8UL //Access:RW   DataWidth:0x1    // QM Bypass mode is enabled for XCM messages for connection type 0. Per connection type.
+#define DORQ_REG_QM_EN_BYP_MASK_1_BB_K2                                                                      0x1004b8UL //Access:RW   DataWidth:0x1    // QM Bypass mode is enabled for XCM messages for connection type 1.
+#define DORQ_REG_QM_EN_BYP_MASK_1_E5                                                                         0x1028ecUL //Access:RW   DataWidth:0x1    // QM Bypass mode is enabled for XCM messages for connection type 1. Per connection type.
+#define DORQ_REG_QM_EN_BYP_MASK_2_BB_K2                                                                      0x1004bcUL //Access:RW   DataWidth:0x1    // QM Bypass mode is enabled for XCM messages for connection type 2.
+#define DORQ_REG_QM_EN_BYP_MASK_2_E5                                                                         0x1028f0UL //Access:RW   DataWidth:0x1    // QM Bypass mode is enabled for XCM messages for connection type 2. Per connection type.
+#define DORQ_REG_QM_EN_BYP_MASK_3_BB_K2                                                                      0x1004c0UL //Access:RW   DataWidth:0x1    // QM Bypass mode is enabled for XCM messages for connection type 3.
+#define DORQ_REG_QM_EN_BYP_MASK_3_E5                                                                         0x1028f4UL //Access:RW   DataWidth:0x1    // QM Bypass mode is enabled for XCM messages for connection type 3. Per connection type.
+#define DORQ_REG_QM_EN_BYP_MASK_4_BB_K2                                                                      0x1004c4UL //Access:RW   DataWidth:0x1    // QM Bypass mode is enabled for XCM messages for connection type 4.
+#define DORQ_REG_QM_EN_BYP_MASK_4_E5                                                                         0x1028f8UL //Access:RW   DataWidth:0x1    // QM Bypass mode is enabled for XCM messages for connection type 4. Per connection type.
+#define DORQ_REG_QM_EN_BYP_MASK_5_BB_K2                                                                      0x1004c8UL //Access:RW   DataWidth:0x1    // QM Bypass mode is enabled for XCM messages for connection type 5.
+#define DORQ_REG_QM_EN_BYP_MASK_5_E5                                                                         0x1028fcUL //Access:RW   DataWidth:0x1    // QM Bypass mode is enabled for XCM messages for connection type 5. Per connection type.
+#define DORQ_REG_QM_EN_BYP_MASK_6_BB_K2                                                                      0x1004ccUL //Access:RW   DataWidth:0x1    // QM Bypass mode is enabled for XCM messages for connection type 6.
+#define DORQ_REG_QM_EN_BYP_MASK_6_E5                                                                         0x102900UL //Access:RW   DataWidth:0x1    // QM Bypass mode is enabled for XCM messages for connection type 6. Per connection type.
+#define DORQ_REG_QM_EN_BYP_MASK_7_BB_K2                                                                      0x1004d0UL //Access:RW   DataWidth:0x1    // QM Bypass mode is enabled for XCM messages for connection type 7.
+#define DORQ_REG_QM_EN_BYP_MASK_7_E5                                                                         0x102904UL //Access:RW   DataWidth:0x1    // QM Bypass mode is enabled for XCM messages for connection type 7. Per connection type.
+#define DORQ_REG_QM_EN_BYP_MASK_8_E5                                                                         0x102908UL //Access:RW   DataWidth:0x1    // QM Bypass mode is enabled for XCM messages for connection type 8. Per connection type.
+#define DORQ_REG_QM_EN_BYP_MASK_9_E5                                                                         0x10290cUL //Access:RW   DataWidth:0x1    // QM Bypass mode is enabled for XCM messages for connection type 9. Per connection type.
+#define DORQ_REG_QM_EN_BYP_MASK_10_E5                                                                        0x102910UL //Access:RW   DataWidth:0x1    // QM Bypass mode is enabled for XCM messages for connection type 10. Per connection type.
+#define DORQ_REG_QM_EN_BYP_MASK_11_E5                                                                        0x102914UL //Access:RW   DataWidth:0x1    // QM Bypass mode is enabled for XCM messages for connection type 11. Per connection type.
+#define DORQ_REG_QM_EN_BYP_MASK_12_E5                                                                        0x102918UL //Access:RW   DataWidth:0x1    // QM Bypass mode is enabled for XCM messages for connection type 12. Per connection type.
+#define DORQ_REG_QM_EN_BYP_MASK_13_E5                                                                        0x10291cUL //Access:RW   DataWidth:0x1    // QM Bypass mode is enabled for XCM messages for connection type 13. Per connection type.
+#define DORQ_REG_QM_EN_BYP_MASK_14_E5                                                                        0x102920UL //Access:RW   DataWidth:0x1    // QM Bypass mode is enabled for XCM messages for connection type 14. Per connection type.
+#define DORQ_REG_QM_EN_BYP_MASK_15_E5                                                                        0x102924UL //Access:RW   DataWidth:0x1    // QM Bypass mode is enabled for XCM messages for connection type 15. Per connection type.
+#define DORQ_REG_DPI_VAL_SUP_0_BB_K2                                                                         0x1004d4UL //Access:RW   DataWidth:0x1    // Indicates whether DPI validation is supported for connection type 0.
+#define DORQ_REG_DPI_VAL_SUP_0_E5                                                                            0x102928UL //Access:RW   DataWidth:0x1    // Indicates whether DPI validation is supported for connection type 0. Per connection type.
+#define DORQ_REG_DPI_VAL_SUP_1_BB_K2                                                                         0x1004d8UL //Access:RW   DataWidth:0x1    // Indicates whether DPI validation is supported for connection type 1.
+#define DORQ_REG_DPI_VAL_SUP_1_E5                                                                            0x10292cUL //Access:RW   DataWidth:0x1    // Indicates whether DPI validation is supported for connection type 1. Per connection type.
+#define DORQ_REG_DPI_VAL_SUP_2_BB_K2                                                                         0x1004dcUL //Access:RW   DataWidth:0x1    // Indicates whether DPI validation is supported for connection type 2.
+#define DORQ_REG_DPI_VAL_SUP_2_E5                                                                            0x102930UL //Access:RW   DataWidth:0x1    // Indicates whether DPI validation is supported for connection type 2. Per connection type.
+#define DORQ_REG_DPI_VAL_SUP_3_BB_K2                                                                         0x1004e0UL //Access:RW   DataWidth:0x1    // Indicates whether DPI validation is supported for connection type 3.
+#define DORQ_REG_DPI_VAL_SUP_3_E5                                                                            0x102934UL //Access:RW   DataWidth:0x1    // Indicates whether DPI validation is supported for connection type 3. Per connection type.
+#define DORQ_REG_DPI_VAL_SUP_4_BB_K2                                                                         0x1004e4UL //Access:RW   DataWidth:0x1    // Indicates whether DPI validation is supported for connection type 4.
+#define DORQ_REG_DPI_VAL_SUP_4_E5                                                                            0x102938UL //Access:RW   DataWidth:0x1    // Indicates whether DPI validation is supported for connection type 4. Per connection type.
+#define DORQ_REG_DPI_VAL_SUP_5_BB_K2                                                                         0x1004e8UL //Access:RW   DataWidth:0x1    // Indicates whether DPI validation is supported for connection type 5.
+#define DORQ_REG_DPI_VAL_SUP_5_E5                                                                            0x10293cUL //Access:RW   DataWidth:0x1    // Indicates whether DPI validation is supported for connection type 5. Per connection type.
+#define DORQ_REG_DPI_VAL_SUP_6_BB_K2                                                                         0x1004ecUL //Access:RW   DataWidth:0x1    // Indicates whether DPI validation is supported for connection type 6.
+#define DORQ_REG_DPI_VAL_SUP_6_E5                                                                            0x102940UL //Access:RW   DataWidth:0x1    // Indicates whether DPI validation is supported for connection type 6. Per connection type.
+#define DORQ_REG_DPI_VAL_SUP_7_BB_K2                                                                         0x1004f0UL //Access:RW   DataWidth:0x1    // Indicates whether DPI validation is supported for connection type 7.
+#define DORQ_REG_DPI_VAL_SUP_7_E5                                                                            0x102944UL //Access:RW   DataWidth:0x1    // Indicates whether DPI validation is supported for connection type 7. Per connection type.
+#define DORQ_REG_DPI_VAL_SUP_8_E5                                                                            0x102948UL //Access:RW   DataWidth:0x1    // Indicates whether DPI validation is supported for connection type 8. Per connection type.
+#define DORQ_REG_DPI_VAL_SUP_9_E5                                                                            0x10294cUL //Access:RW   DataWidth:0x1    // Indicates whether DPI validation is supported for connection type 9. Per connection type.
+#define DORQ_REG_DPI_VAL_SUP_10_E5                                                                           0x102950UL //Access:RW   DataWidth:0x1    // Indicates whether DPI validation is supported for connection type 10. Per connection type.
+#define DORQ_REG_DPI_VAL_SUP_11_E5                                                                           0x102954UL //Access:RW   DataWidth:0x1    // Indicates whether DPI validation is supported for connection type 11. Per connection type.
+#define DORQ_REG_DPI_VAL_SUP_12_E5                                                                           0x102958UL //Access:RW   DataWidth:0x1    // Indicates whether DPI validation is supported for connection type 12. Per connection type.
+#define DORQ_REG_DPI_VAL_SUP_13_E5                                                                           0x10295cUL //Access:RW   DataWidth:0x1    // Indicates whether DPI validation is supported for connection type 13. Per connection type.
+#define DORQ_REG_DPI_VAL_SUP_14_E5                                                                           0x102960UL //Access:RW   DataWidth:0x1    // Indicates whether DPI validation is supported for connection type 14. Per connection type.
+#define DORQ_REG_DPI_VAL_SUP_15_E5                                                                           0x102964UL //Access:RW   DataWidth:0x1    // Indicates whether DPI validation is supported for connection type 15. Per connection type.
+#define DORQ_REG_DPM_XCM_EVENT_ID_0_BB_K2                                                                    0x1006d4UL //Access:RW   DataWidth:0x8    // Event ID in XCM message in DPM doorbell for connection type 0.
+#define DORQ_REG_DPM_XCM_EVENT_ID_0_E5                                                                       0x102968UL //Access:RW   DataWidth:0x8    // Event ID in XCM message in DPM doorbell for connection type 0.
+#define DORQ_REG_DPM_XCM_EVENT_ID_1_BB_K2                                                                    0x1006d8UL //Access:RW   DataWidth:0x8    // Event ID in XCM message in DPM doorbell for connection type 1.
+#define DORQ_REG_DPM_XCM_EVENT_ID_1_E5                                                                       0x10296cUL //Access:RW   DataWidth:0x8    // Event ID in XCM message in DPM doorbell for connection type 1.
+#define DORQ_REG_DPM_XCM_EVENT_ID_2_BB_K2                                                                    0x1006dcUL //Access:RW   DataWidth:0x8    // Event ID in XCM message in DPM doorbell for connection type 2.
+#define DORQ_REG_DPM_XCM_EVENT_ID_2_E5                                                                       0x102970UL //Access:RW   DataWidth:0x8    // Event ID in XCM message in DPM doorbell for connection type 2.
+#define DORQ_REG_DPM_XCM_EVENT_ID_3_BB_K2                                                                    0x1006e0UL //Access:RW   DataWidth:0x8    // Event ID in XCM message in DPM doorbell for connection type 3.
+#define DORQ_REG_DPM_XCM_EVENT_ID_3_E5                                                                       0x102974UL //Access:RW   DataWidth:0x8    // Event ID in XCM message in DPM doorbell for connection type 3.
+#define DORQ_REG_DPM_XCM_EVENT_ID_4_BB_K2                                                                    0x1006e4UL //Access:RW   DataWidth:0x8    // Event ID in XCM message in DPM doorbell for connection type 4.
+#define DORQ_REG_DPM_XCM_EVENT_ID_4_E5                                                                       0x102978UL //Access:RW   DataWidth:0x8    // Event ID in XCM message in DPM doorbell for connection type 4.
+#define DORQ_REG_DPM_XCM_EVENT_ID_5_BB_K2                                                                    0x1006e8UL //Access:RW   DataWidth:0x8    // Event ID in XCM message in DPM doorbell for connection type 5.
+#define DORQ_REG_DPM_XCM_EVENT_ID_5_E5                                                                       0x10297cUL //Access:RW   DataWidth:0x8    // Event ID in XCM message in DPM doorbell for connection type 5.
+#define DORQ_REG_DPM_XCM_EVENT_ID_6_BB_K2                                                                    0x1006ecUL //Access:RW   DataWidth:0x8    // Event ID in XCM message in DPM doorbell for connection type 6.
+#define DORQ_REG_DPM_XCM_EVENT_ID_6_E5                                                                       0x102980UL //Access:RW   DataWidth:0x8    // Event ID in XCM message in DPM doorbell for connection type 6.
+#define DORQ_REG_DPM_XCM_EVENT_ID_7_BB_K2                                                                    0x1006f0UL //Access:RW   DataWidth:0x8    // Event ID in XCM message in DPM doorbell for connection type 7.
+#define DORQ_REG_DPM_XCM_EVENT_ID_7_E5                                                                       0x102984UL //Access:RW   DataWidth:0x8    // Event ID in XCM message in DPM doorbell for connection type 7.
+#define DORQ_REG_DPM_XCM_EVENT_ID_8_E5                                                                       0x102988UL //Access:RW   DataWidth:0x8    // Event ID in XCM message in DPM doorbell for connection type 8.
+#define DORQ_REG_DPM_XCM_EVENT_ID_9_E5                                                                       0x10298cUL //Access:RW   DataWidth:0x8    // Event ID in XCM message in DPM doorbell for connection type 9.
+#define DORQ_REG_DPM_XCM_EVENT_ID_10_E5                                                                      0x102990UL //Access:RW   DataWidth:0x8    // Event ID in XCM message in DPM doorbell for connection type 10.
+#define DORQ_REG_DPM_XCM_EVENT_ID_11_E5                                                                      0x102994UL //Access:RW   DataWidth:0x8    // Event ID in XCM message in DPM doorbell for connection type 11.
+#define DORQ_REG_DPM_XCM_EVENT_ID_12_E5                                                                      0x102998UL //Access:RW   DataWidth:0x8    // Event ID in XCM message in DPM doorbell for connection type 12.
+#define DORQ_REG_DPM_XCM_EVENT_ID_13_E5                                                                      0x10299cUL //Access:RW   DataWidth:0x8    // Event ID in XCM message in DPM doorbell for connection type 13.
+#define DORQ_REG_DPM_XCM_EVENT_ID_14_E5                                                                      0x1029a0UL //Access:RW   DataWidth:0x8    // Event ID in XCM message in DPM doorbell for connection type 14.
+#define DORQ_REG_DPM_XCM_EVENT_ID_15_E5                                                                      0x1029a4UL //Access:RW   DataWidth:0x8    // Event ID in XCM message in DPM doorbell for connection type 15.
+#define DORQ_REG_QM_BYP_AGG_CTX_SIZE_0_BB_K2                                                                 0x10070cUL //Access:RW   DataWidth:0x4    // The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 0.
+#define DORQ_REG_QM_BYP_AGG_CTX_SIZE_0_E5                                                                    0x1029a8UL //Access:RW   DataWidth:0x4    // The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 0.
+#define DORQ_REG_QM_BYP_AGG_CTX_SIZE_1_BB_K2                                                                 0x100710UL //Access:RW   DataWidth:0x4    // The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 1.
+#define DORQ_REG_QM_BYP_AGG_CTX_SIZE_1_E5                                                                    0x1029acUL //Access:RW   DataWidth:0x4    // The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 1.
+#define DORQ_REG_QM_BYP_AGG_CTX_SIZE_2_BB_K2                                                                 0x100714UL //Access:RW   DataWidth:0x4    // The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 2.
+#define DORQ_REG_QM_BYP_AGG_CTX_SIZE_2_E5                                                                    0x1029b0UL //Access:RW   DataWidth:0x4    // The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 2.
+#define DORQ_REG_QM_BYP_AGG_CTX_SIZE_3_BB_K2                                                                 0x100718UL //Access:RW   DataWidth:0x4    // The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 3.
+#define DORQ_REG_QM_BYP_AGG_CTX_SIZE_3_E5                                                                    0x1029b4UL //Access:RW   DataWidth:0x4    // The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 3.
+#define DORQ_REG_QM_BYP_AGG_CTX_SIZE_4_BB_K2                                                                 0x10071cUL //Access:RW   DataWidth:0x4    // The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 4.
+#define DORQ_REG_QM_BYP_AGG_CTX_SIZE_4_E5                                                                    0x1029b8UL //Access:RW   DataWidth:0x4    // The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 4.
+#define DORQ_REG_QM_BYP_AGG_CTX_SIZE_5_BB_K2                                                                 0x100720UL //Access:RW   DataWidth:0x4    // The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 5.
+#define DORQ_REG_QM_BYP_AGG_CTX_SIZE_5_E5                                                                    0x1029bcUL //Access:RW   DataWidth:0x4    // The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 5.
+#define DORQ_REG_QM_BYP_AGG_CTX_SIZE_6_BB_K2                                                                 0x100724UL //Access:RW   DataWidth:0x4    // The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 6.
+#define DORQ_REG_QM_BYP_AGG_CTX_SIZE_6_E5                                                                    0x1029c0UL //Access:RW   DataWidth:0x4    // The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 6.
+#define DORQ_REG_QM_BYP_AGG_CTX_SIZE_7_BB_K2                                                                 0x100728UL //Access:RW   DataWidth:0x4    // The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 7.
+#define DORQ_REG_QM_BYP_AGG_CTX_SIZE_7_E5                                                                    0x1029c4UL //Access:RW   DataWidth:0x4    // The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 7.
+#define DORQ_REG_QM_BYP_AGG_CTX_SIZE_8_E5                                                                    0x1029c8UL //Access:RW   DataWidth:0x4    // The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 8.
+#define DORQ_REG_QM_BYP_AGG_CTX_SIZE_9_E5                                                                    0x1029ccUL //Access:RW   DataWidth:0x4    // The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 9.
+#define DORQ_REG_QM_BYP_AGG_CTX_SIZE_10_E5                                                                   0x1029d0UL //Access:RW   DataWidth:0x4    // The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 10.
+#define DORQ_REG_QM_BYP_AGG_CTX_SIZE_11_E5                                                                   0x1029d4UL //Access:RW   DataWidth:0x4    // The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 11.
+#define DORQ_REG_QM_BYP_AGG_CTX_SIZE_12_E5                                                                   0x1029d8UL //Access:RW   DataWidth:0x4    // The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 12.
+#define DORQ_REG_QM_BYP_AGG_CTX_SIZE_13_E5                                                                   0x1029dcUL //Access:RW   DataWidth:0x4    // The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 13.
+#define DORQ_REG_QM_BYP_AGG_CTX_SIZE_14_E5                                                                   0x1029e0UL //Access:RW   DataWidth:0x4    // The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 14.
+#define DORQ_REG_QM_BYP_AGG_CTX_SIZE_15_E5                                                                   0x1029e4UL //Access:RW   DataWidth:0x4    // The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 15.
+#define DORQ_REG_XCM_AGG_FLG_MASK_CONN_0_BB_K2                                                               0x100614UL //Access:RW   DataWidth:0x8    // Enable for XCM counter flag command for connection 0.
+#define DORQ_REG_XCM_AGG_FLG_MASK_CONN_0_E5                                                                  0x1029e8UL //Access:RW   DataWidth:0x8    // Enable for XCM counter flag command for connection 0.
+#define DORQ_REG_XCM_AGG_FLG_MASK_CONN_1_BB_K2                                                               0x100618UL //Access:RW   DataWidth:0x8    // Enable for XCM counter flag command for connection 1.
+#define DORQ_REG_XCM_AGG_FLG_MASK_CONN_1_E5                                                                  0x1029ecUL //Access:RW   DataWidth:0x8    // Enable for XCM counter flag command for connection 1.
+#define DORQ_REG_XCM_AGG_FLG_MASK_CONN_2_BB_K2                                                               0x10061cUL //Access:RW   DataWidth:0x8    // Enable for XCM counter flag command for connection 2.
+#define DORQ_REG_XCM_AGG_FLG_MASK_CONN_2_E5                                                                  0x1029f0UL //Access:RW   DataWidth:0x8    // Enable for XCM counter flag command for connection 2.
+#define DORQ_REG_XCM_AGG_FLG_MASK_CONN_3_BB_K2                                                               0x100620UL //Access:RW   DataWidth:0x8    // Enable for XCM counter flag command for connection 3.
+#define DORQ_REG_XCM_AGG_FLG_MASK_CONN_3_E5                                                                  0x1029f4UL //Access:RW   DataWidth:0x8    // Enable for XCM counter flag command for connection 3.
+#define DORQ_REG_XCM_AGG_FLG_MASK_CONN_4_BB_K2                                                               0x100624UL //Access:RW   DataWidth:0x8    // Enable for XCM counter flag command for connection 4.
+#define DORQ_REG_XCM_AGG_FLG_MASK_CONN_4_E5                                                                  0x1029f8UL //Access:RW   DataWidth:0x8    // Enable for XCM counter flag command for connection 4.
+#define DORQ_REG_XCM_AGG_FLG_MASK_CONN_5_BB_K2                                                               0x100628UL //Access:RW   DataWidth:0x8    // Enable for XCM counter flag command for connection 5.
+#define DORQ_REG_XCM_AGG_FLG_MASK_CONN_5_E5                                                                  0x1029fcUL //Access:RW   DataWidth:0x8    // Enable for XCM counter flag command for connection 5.
+#define DORQ_REG_XCM_AGG_FLG_MASK_CONN_6_BB_K2                                                               0x10062cUL //Access:RW   DataWidth:0x8    // Enable for XCM counter flag command for connection 6.
+#define DORQ_REG_XCM_AGG_FLG_MASK_CONN_6_E5                                                                  0x102a00UL //Access:RW   DataWidth:0x8    // Enable for XCM counter flag command for connection 6.
+#define DORQ_REG_XCM_AGG_FLG_MASK_CONN_7_BB_K2                                                               0x100630UL //Access:RW   DataWidth:0x8    // Enable for XCM counter flag command for connection 7.
+#define DORQ_REG_XCM_AGG_FLG_MASK_CONN_7_E5                                                                  0x102a04UL //Access:RW   DataWidth:0x8    // Enable for XCM counter flag command for connection 7.
+#define DORQ_REG_XCM_AGG_FLG_MASK_CONN_8_E5                                                                  0x102a08UL //Access:RW   DataWidth:0x8    // Enable for XCM counter flag command for connection 8.
+#define DORQ_REG_XCM_AGG_FLG_MASK_CONN_9_E5                                                                  0x102a0cUL //Access:RW   DataWidth:0x8    // Enable for XCM counter flag command for connection 9.
+#define DORQ_REG_XCM_AGG_FLG_MASK_CONN_10_E5                                                                 0x102a10UL //Access:RW   DataWidth:0x8    // Enable for XCM counter flag command for connection 10.
+#define DORQ_REG_XCM_AGG_FLG_MASK_CONN_11_E5                                                                 0x102a14UL //Access:RW   DataWidth:0x8    // Enable for XCM counter flag command for connection 11.
+#define DORQ_REG_XCM_AGG_FLG_MASK_CONN_12_E5                                                                 0x102a18UL //Access:RW   DataWidth:0x8    // Enable for XCM counter flag command for connection 12.
+#define DORQ_REG_XCM_AGG_FLG_MASK_CONN_13_E5                                                                 0x102a1cUL //Access:RW   DataWidth:0x8    // Enable for XCM counter flag command for connection 13.
+#define DORQ_REG_XCM_AGG_FLG_MASK_CONN_14_E5                                                                 0x102a20UL //Access:RW   DataWidth:0x8    // Enable for XCM counter flag command for connection 14.
+#define DORQ_REG_XCM_AGG_FLG_MASK_CONN_15_E5                                                                 0x102a24UL //Access:RW   DataWidth:0x8    // Enable for XCM counter flag command for connection 15.
+#define DORQ_REG_TCM_AGG_FLG_MASK_CONN_0_BB_K2                                                               0x100634UL //Access:RW   DataWidth:0x8    // Enable for TCM counter flag command for connection 0.
+#define DORQ_REG_TCM_AGG_FLG_MASK_CONN_0_E5                                                                  0x102a28UL //Access:RW   DataWidth:0x8    // Enable for TCM counter flag command for connection 0.
+#define DORQ_REG_TCM_AGG_FLG_MASK_CONN_1_BB_K2                                                               0x100638UL //Access:RW   DataWidth:0x8    // Enable for TCM counter flag command for connection 1.
+#define DORQ_REG_TCM_AGG_FLG_MASK_CONN_1_E5                                                                  0x102a2cUL //Access:RW   DataWidth:0x8    // Enable for TCM counter flag command for connection 1.
+#define DORQ_REG_TCM_AGG_FLG_MASK_CONN_2_BB_K2                                                               0x10063cUL //Access:RW   DataWidth:0x8    // Enable for TCM counter flag command for connection 2.
+#define DORQ_REG_TCM_AGG_FLG_MASK_CONN_2_E5                                                                  0x102a30UL //Access:RW   DataWidth:0x8    // Enable for TCM counter flag command for connection 2.
+#define DORQ_REG_TCM_AGG_FLG_MASK_CONN_3_BB_K2                                                               0x100640UL //Access:RW   DataWidth:0x8    // Enable for TCM counter flag command for connection 3.
+#define DORQ_REG_TCM_AGG_FLG_MASK_CONN_3_E5                                                                  0x102a34UL //Access:RW   DataWidth:0x8    // Enable for TCM counter flag command for connection 3.
+#define DORQ_REG_TCM_AGG_FLG_MASK_CONN_4_BB_K2                                                               0x100644UL //Access:RW   DataWidth:0x8    // Enable for TCM counter flag command for connection 4.
+#define DORQ_REG_TCM_AGG_FLG_MASK_CONN_4_E5                                                                  0x102a38UL //Access:RW   DataWidth:0x8    // Enable for TCM counter flag command for connection 4.
+#define DORQ_REG_TCM_AGG_FLG_MASK_CONN_5_BB_K2                                                               0x100648UL //Access:RW   DataWidth:0x8    // Enable for TCM counter flag command for connection 5.
+#define DORQ_REG_TCM_AGG_FLG_MASK_CONN_5_E5                                                                  0x102a3cUL //Access:RW   DataWidth:0x8    // Enable for TCM counter flag command for connection 5.
+#define DORQ_REG_TCM_AGG_FLG_MASK_CONN_6_BB_K2                                                               0x10064cUL //Access:RW   DataWidth:0x8    // Enable for TCM counter flag command for connection 6.
+#define DORQ_REG_TCM_AGG_FLG_MASK_CONN_6_E5                                                                  0x102a40UL //Access:RW   DataWidth:0x8    // Enable for TCM counter flag command for connection 6.
+#define DORQ_REG_TCM_AGG_FLG_MASK_CONN_7_BB_K2                                                               0x100650UL //Access:RW   DataWidth:0x8    // Enable for TCM counter flag command for connection 7.
+#define DORQ_REG_TCM_AGG_FLG_MASK_CONN_7_E5                                                                  0x102a44UL //Access:RW   DataWidth:0x8    // Enable for TCM counter flag command for connection 7.
+#define DORQ_REG_TCM_AGG_FLG_MASK_CONN_8_E5                                                                  0x102a48UL //Access:RW   DataWidth:0x8    // Enable for TCM counter flag command for connection 8.
+#define DORQ_REG_TCM_AGG_FLG_MASK_CONN_9_E5                                                                  0x102a4cUL //Access:RW   DataWidth:0x8    // Enable for TCM counter flag command for connection 9.
+#define DORQ_REG_TCM_AGG_FLG_MASK_CONN_10_E5                                                                 0x102a50UL //Access:RW   DataWidth:0x8    // Enable for TCM counter flag command for connection 10.
+#define DORQ_REG_TCM_AGG_FLG_MASK_CONN_11_E5                                                                 0x102a54UL //Access:RW   DataWidth:0x8    // Enable for TCM counter flag command for connection 11.
+#define DORQ_REG_TCM_AGG_FLG_MASK_CONN_12_E5                                                                 0x102a58UL //Access:RW   DataWidth:0x8    // Enable for TCM counter flag command for connection 12.
+#define DORQ_REG_TCM_AGG_FLG_MASK_CONN_13_E5                                                                 0x102a5cUL //Access:RW   DataWidth:0x8    // Enable for TCM counter flag command for connection 13.
+#define DORQ_REG_TCM_AGG_FLG_MASK_CONN_14_E5                                                                 0x102a60UL //Access:RW   DataWidth:0x8    // Enable for TCM counter flag command for connection 14.
+#define DORQ_REG_TCM_AGG_FLG_MASK_CONN_15_E5                                                                 0x102a64UL //Access:RW   DataWidth:0x8    // Enable for TCM counter flag command for connection 15.
+#define DORQ_REG_UCM_AGG_FLG_MASK_CONN_0_BB_K2                                                               0x100654UL //Access:RW   DataWidth:0x8    // Enable for UCM counter flag command for connection 0.
+#define DORQ_REG_UCM_AGG_FLG_MASK_CONN_0_E5                                                                  0x102a68UL //Access:RW   DataWidth:0x8    // Enable for UCM counter flag command for connection 0.
+#define DORQ_REG_UCM_AGG_FLG_MASK_CONN_1_BB_K2                                                               0x100658UL //Access:RW   DataWidth:0x8    // Enable for UCM counter flag command for connection 1.
+#define DORQ_REG_UCM_AGG_FLG_MASK_CONN_1_E5                                                                  0x102a6cUL //Access:RW   DataWidth:0x8    // Enable for UCM counter flag command for connection 1.
+#define DORQ_REG_UCM_AGG_FLG_MASK_CONN_2_BB_K2                                                               0x10065cUL //Access:RW   DataWidth:0x8    // Enable for UCM counter flag command for connection 2.
+#define DORQ_REG_UCM_AGG_FLG_MASK_CONN_2_E5                                                                  0x102a70UL //Access:RW   DataWidth:0x8    // Enable for UCM counter flag command for connection 2.
+#define DORQ_REG_UCM_AGG_FLG_MASK_CONN_3_BB_K2                                                               0x100660UL //Access:RW   DataWidth:0x8    // Enable for UCM counter flag command for connection 3.
+#define DORQ_REG_UCM_AGG_FLG_MASK_CONN_3_E5                                                                  0x102a74UL //Access:RW   DataWidth:0x8    // Enable for UCM counter flag command for connection 3.
+#define DORQ_REG_UCM_AGG_FLG_MASK_CONN_4_BB_K2                                                               0x100664UL //Access:RW   DataWidth:0x8    // Enable for UCM counter flag command for connection 4.
+#define DORQ_REG_UCM_AGG_FLG_MASK_CONN_4_E5                                                                  0x102a78UL //Access:RW   DataWidth:0x8    // Enable for UCM counter flag command for connection 4.
+#define DORQ_REG_UCM_AGG_FLG_MASK_CONN_5_BB_K2                                                               0x100668UL //Access:RW   DataWidth:0x8    // Enable for UCM counter flag command for connection 5.
+#define DORQ_REG_UCM_AGG_FLG_MASK_CONN_5_E5                                                                  0x102a7cUL //Access:RW   DataWidth:0x8    // Enable for UCM counter flag command for connection 5.
+#define DORQ_REG_UCM_AGG_FLG_MASK_CONN_6_BB_K2                                                               0x10066cUL //Access:RW   DataWidth:0x8    // Enable for UCM counter flag command for connection 6.
+#define DORQ_REG_UCM_AGG_FLG_MASK_CONN_6_E5                                                                  0x102a80UL //Access:RW   DataWidth:0x8    // Enable for UCM counter flag command for connection 6.
+#define DORQ_REG_UCM_AGG_FLG_MASK_CONN_7_BB_K2                                                               0x100670UL //Access:RW   DataWidth:0x8    // Enable for UCM counter flag command for connection 7.
+#define DORQ_REG_UCM_AGG_FLG_MASK_CONN_7_E5                                                                  0x102a84UL //Access:RW   DataWidth:0x8    // Enable for UCM counter flag command for connection 7.
+#define DORQ_REG_UCM_AGG_FLG_MASK_CONN_8_E5                                                                  0x102a88UL //Access:RW   DataWidth:0x8    // Enable for UCM counter flag command for connection 8.
+#define DORQ_REG_UCM_AGG_FLG_MASK_CONN_9_E5                                                                  0x102a8cUL //Access:RW   DataWidth:0x8    // Enable for UCM counter flag command for connection 9.
+#define DORQ_REG_UCM_AGG_FLG_MASK_CONN_10_E5                                                                 0x102a90UL //Access:RW   DataWidth:0x8    // Enable for UCM counter flag command for connection 10.
+#define DORQ_REG_UCM_AGG_FLG_MASK_CONN_11_E5                                                                 0x102a94UL //Access:RW   DataWidth:0x8    // Enable for UCM counter flag command for connection 11.
+#define DORQ_REG_UCM_AGG_FLG_MASK_CONN_12_E5                                                                 0x102a98UL //Access:RW   DataWidth:0x8    // Enable for UCM counter flag command for connection 12.
+#define DORQ_REG_UCM_AGG_FLG_MASK_CONN_13_E5                                                                 0x102a9cUL //Access:RW   DataWidth:0x8    // Enable for UCM counter flag command for connection 13.
+#define DORQ_REG_UCM_AGG_FLG_MASK_CONN_14_E5                                                                 0x102aa0UL //Access:RW   DataWidth:0x8    // Enable for UCM counter flag command for connection 14.
+#define DORQ_REG_UCM_AGG_FLG_MASK_CONN_15_E5                                                                 0x102aa4UL //Access:RW   DataWidth:0x8    // Enable for UCM counter flag command for connection 15.
+#define DORQ_REG_XCM_AGG_CMD_MASK_CONN_0_BB_K2                                                               0x100674UL //Access:RW   DataWidth:0x8    // Enable for XCM aggregation value command for connection 0.
+#define DORQ_REG_XCM_AGG_CMD_MASK_CONN_0_E5                                                                  0x102aa8UL //Access:RW   DataWidth:0x8    // Enable for XCM aggregation value command for connection 0.
+#define DORQ_REG_XCM_AGG_CMD_MASK_CONN_1_BB_K2                                                               0x100678UL //Access:RW   DataWidth:0x8    // Enable for XCM aggregation value command for connection 1.
+#define DORQ_REG_XCM_AGG_CMD_MASK_CONN_1_E5                                                                  0x102aacUL //Access:RW   DataWidth:0x8    // Enable for XCM aggregation value command for connection 1.
+#define DORQ_REG_XCM_AGG_CMD_MASK_CONN_2_BB_K2                                                               0x10067cUL //Access:RW   DataWidth:0x8    // Enable for XCM aggregation value command for connection 2.
+#define DORQ_REG_XCM_AGG_CMD_MASK_CONN_2_E5                                                                  0x102ab0UL //Access:RW   DataWidth:0x8    // Enable for XCM aggregation value command for connection 2.
+#define DORQ_REG_XCM_AGG_CMD_MASK_CONN_3_BB_K2                                                               0x100680UL //Access:RW   DataWidth:0x8    // Enable for XCM aggregation value command for connection 3.
+#define DORQ_REG_XCM_AGG_CMD_MASK_CONN_3_E5                                                                  0x102ab4UL //Access:RW   DataWidth:0x8    // Enable for XCM aggregation value command for connection 3.
+#define DORQ_REG_XCM_AGG_CMD_MASK_CONN_4_BB_K2                                                               0x100684UL //Access:RW   DataWidth:0x8    // Enable for XCM aggregation value command for connection 4.
+#define DORQ_REG_XCM_AGG_CMD_MASK_CONN_4_E5                                                                  0x102ab8UL //Access:RW   DataWidth:0x8    // Enable for XCM aggregation value command for connection 4.
+#define DORQ_REG_XCM_AGG_CMD_MASK_CONN_5_BB_K2                                                               0x100688UL //Access:RW   DataWidth:0x8    // Enable for XCM aggregation value command for connection 5.
+#define DORQ_REG_XCM_AGG_CMD_MASK_CONN_5_E5                                                                  0x102abcUL //Access:RW   DataWidth:0x8    // Enable for XCM aggregation value command for connection 5.
+#define DORQ_REG_XCM_AGG_CMD_MASK_CONN_6_BB_K2                                                               0x10068cUL //Access:RW   DataWidth:0x8    // Enable for XCM aggregation value command for connection 6.
+#define DORQ_REG_XCM_AGG_CMD_MASK_CONN_6_E5                                                                  0x102ac0UL //Access:RW   DataWidth:0x8    // Enable for XCM aggregation value command for connection 6.
+#define DORQ_REG_XCM_AGG_CMD_MASK_CONN_7_BB_K2                                                               0x100690UL //Access:RW   DataWidth:0x8    // Enable for XCM aggregation value command for connection 7.
+#define DORQ_REG_XCM_AGG_CMD_MASK_CONN_7_E5                                                                  0x102ac4UL //Access:RW   DataWidth:0x8    // Enable for XCM aggregation value command for connection 7.
+#define DORQ_REG_XCM_AGG_CMD_MASK_CONN_8_E5                                                                  0x102ac8UL //Access:RW   DataWidth:0x8    // Enable for XCM aggregation value command for connection 8.
+#define DORQ_REG_XCM_AGG_CMD_MASK_CONN_9_E5                                                                  0x102accUL //Access:RW   DataWidth:0x8    // Enable for XCM aggregation value command for connection 9.
+#define DORQ_REG_XCM_AGG_CMD_MASK_CONN_10_E5                                                                 0x102ad0UL //Access:RW   DataWidth:0x8    // Enable for XCM aggregation value command for connection 10.
+#define DORQ_REG_XCM_AGG_CMD_MASK_CONN_11_E5                                                                 0x102ad4UL //Access:RW   DataWidth:0x8    // Enable for XCM aggregation value command for connection 11.
+#define DORQ_REG_XCM_AGG_CMD_MASK_CONN_12_E5                                                                 0x102ad8UL //Access:RW   DataWidth:0x8    // Enable for XCM aggregation value command for connection 12.
+#define DORQ_REG_XCM_AGG_CMD_MASK_CONN_13_E5                                                                 0x102adcUL //Access:RW   DataWidth:0x8    // Enable for XCM aggregation value command for connection 13.
+#define DORQ_REG_XCM_AGG_CMD_MASK_CONN_14_E5                                                                 0x102ae0UL //Access:RW   DataWidth:0x8    // Enable for XCM aggregation value command for connection 14.
+#define DORQ_REG_XCM_AGG_CMD_MASK_CONN_15_E5                                                                 0x102ae4UL //Access:RW   DataWidth:0x8    // Enable for XCM aggregation value command for connection 15.
+#define DORQ_REG_TCM_AGG_CMD_MASK_CONN_0_BB_K2                                                               0x100694UL //Access:RW   DataWidth:0x8    // Enable for TCM aggregation value command for connection 0.
+#define DORQ_REG_TCM_AGG_CMD_MASK_CONN_0_E5                                                                  0x102ae8UL //Access:RW   DataWidth:0x8    // Enable for TCM aggregation value command for connection 0.
+#define DORQ_REG_TCM_AGG_CMD_MASK_CONN_1_BB_K2                                                               0x100698UL //Access:RW   DataWidth:0x8    // Enable for TCM aggregation value command for connection 1.
+#define DORQ_REG_TCM_AGG_CMD_MASK_CONN_1_E5                                                                  0x102aecUL //Access:RW   DataWidth:0x8    // Enable for TCM aggregation value command for connection 1.
+#define DORQ_REG_TCM_AGG_CMD_MASK_CONN_2_BB_K2                                                               0x10069cUL //Access:RW   DataWidth:0x8    // Enable for TCM aggregation value command for connection 2.
+#define DORQ_REG_TCM_AGG_CMD_MASK_CONN_2_E5                                                                  0x102af0UL //Access:RW   DataWidth:0x8    // Enable for TCM aggregation value command for connection 2.
+#define DORQ_REG_TCM_AGG_CMD_MASK_CONN_3_BB_K2                                                               0x1006a0UL //Access:RW   DataWidth:0x8    // Enable for TCM aggregation value command for connection 3.
+#define DORQ_REG_TCM_AGG_CMD_MASK_CONN_3_E5                                                                  0x102af4UL //Access:RW   DataWidth:0x8    // Enable for TCM aggregation value command for connection 3.
+#define DORQ_REG_TCM_AGG_CMD_MASK_CONN_4_BB_K2                                                               0x1006a4UL //Access:RW   DataWidth:0x8    // Enable for TCM aggregation value command for connection 4.
+#define DORQ_REG_TCM_AGG_CMD_MASK_CONN_4_E5                                                                  0x102af8UL //Access:RW   DataWidth:0x8    // Enable for TCM aggregation value command for connection 4.
+#define DORQ_REG_TCM_AGG_CMD_MASK_CONN_5_BB_K2                                                               0x1006a8UL //Access:RW   DataWidth:0x8    // Enable for TCM aggregation value command for connection 5.
+#define DORQ_REG_TCM_AGG_CMD_MASK_CONN_5_E5                                                                  0x102afcUL //Access:RW   DataWidth:0x8    // Enable for TCM aggregation value command for connection 5.
+#define DORQ_REG_TCM_AGG_CMD_MASK_CONN_6_BB_K2                                                               0x1006acUL //Access:RW   DataWidth:0x8    // Enable for TCM aggregation value command for connection 6.
+#define DORQ_REG_TCM_AGG_CMD_MASK_CONN_6_E5                                                                  0x102b00UL //Access:RW   DataWidth:0x8    // Enable for TCM aggregation value command for connection 6.
+#define DORQ_REG_TCM_AGG_CMD_MASK_CONN_7_BB_K2                                                               0x1006b0UL //Access:RW   DataWidth:0x8    // Enable for TCM aggregation value command for connection 7.
+#define DORQ_REG_TCM_AGG_CMD_MASK_CONN_7_E5                                                                  0x102b04UL //Access:RW   DataWidth:0x8    // Enable for TCM aggregation value command for connection 7.
+#define DORQ_REG_TCM_AGG_CMD_MASK_CONN_8_E5                                                                  0x102b08UL //Access:RW   DataWidth:0x8    // Enable for TCM aggregation value command for connection 8.
+#define DORQ_REG_TCM_AGG_CMD_MASK_CONN_9_E5                                                                  0x102b0cUL //Access:RW   DataWidth:0x8    // Enable for TCM aggregation value command for connection 9.
+#define DORQ_REG_TCM_AGG_CMD_MASK_CONN_10_E5                                                                 0x102b10UL //Access:RW   DataWidth:0x8    // Enable for TCM aggregation value command for connection 10.
+#define DORQ_REG_TCM_AGG_CMD_MASK_CONN_11_E5                                                                 0x102b14UL //Access:RW   DataWidth:0x8    // Enable for TCM aggregation value command for connection 11.
+#define DORQ_REG_TCM_AGG_CMD_MASK_CONN_12_E5                                                                 0x102b18UL //Access:RW   DataWidth:0x8    // Enable for TCM aggregation value command for connection 12.
+#define DORQ_REG_TCM_AGG_CMD_MASK_CONN_13_E5                                                                 0x102b1cUL //Access:RW   DataWidth:0x8    // Enable for TCM aggregation value command for connection 13.
+#define DORQ_REG_TCM_AGG_CMD_MASK_CONN_14_E5                                                                 0x102b20UL //Access:RW   DataWidth:0x8    // Enable for TCM aggregation value command for connection 14.
+#define DORQ_REG_TCM_AGG_CMD_MASK_CONN_15_E5                                                                 0x102b24UL //Access:RW   DataWidth:0x8    // Enable for TCM aggregation value command for connection 15.
+#define DORQ_REG_UCM_AGG_CMD_MASK_CONN_0_BB_K2                                                               0x1006b4UL //Access:RW   DataWidth:0x8    // Enable for UCM aggregation value command for connection 0.
+#define DORQ_REG_UCM_AGG_CMD_MASK_CONN_0_E5                                                                  0x102b28UL //Access:RW   DataWidth:0x8    // Enable for UCM aggregation value command for connection 0.
+#define DORQ_REG_UCM_AGG_CMD_MASK_CONN_1_BB_K2                                                               0x1006b8UL //Access:RW   DataWidth:0x8    // Enable for UCM aggregation value command for connection 1.
+#define DORQ_REG_UCM_AGG_CMD_MASK_CONN_1_E5                                                                  0x102b2cUL //Access:RW   DataWidth:0x8    // Enable for UCM aggregation value command for connection 1.
+#define DORQ_REG_UCM_AGG_CMD_MASK_CONN_2_BB_K2                                                               0x1006bcUL //Access:RW   DataWidth:0x8    // Enable for UCM aggregation value command for connection 2.
+#define DORQ_REG_UCM_AGG_CMD_MASK_CONN_2_E5                                                                  0x102b30UL //Access:RW   DataWidth:0x8    // Enable for UCM aggregation value command for connection 2.
+#define DORQ_REG_UCM_AGG_CMD_MASK_CONN_3_BB_K2                                                               0x1006c0UL //Access:RW   DataWidth:0x8    // Enable for UCM aggregation value command for connection 3.
+#define DORQ_REG_UCM_AGG_CMD_MASK_CONN_3_E5                                                                  0x102b34UL //Access:RW   DataWidth:0x8    // Enable for UCM aggregation value command for connection 3.
+#define DORQ_REG_UCM_AGG_CMD_MASK_CONN_4_BB_K2                                                               0x1006c4UL //Access:RW   DataWidth:0x8    // Enable for UCM aggregation value command for connection 4.
+#define DORQ_REG_UCM_AGG_CMD_MASK_CONN_4_E5                                                                  0x102b38UL //Access:RW   DataWidth:0x8    // Enable for UCM aggregation value command for connection 4.
+#define DORQ_REG_UCM_AGG_CMD_MASK_CONN_5_BB_K2                                                               0x1006c8UL //Access:RW   DataWidth:0x8    // Enable for UCM aggregation value command for connection 5.
+#define DORQ_REG_UCM_AGG_CMD_MASK_CONN_5_E5                                                                  0x102b3cUL //Access:RW   DataWidth:0x8    // Enable for UCM aggregation value command for connection 5.
+#define DORQ_REG_UCM_AGG_CMD_MASK_CONN_6_BB_K2                                                               0x1006ccUL //Access:RW   DataWidth:0x8    // Enable for UCM aggregation value command for connection 6.
+#define DORQ_REG_UCM_AGG_CMD_MASK_CONN_6_E5                                                                  0x102b40UL //Access:RW   DataWidth:0x8    // Enable for UCM aggregation value command for connection 6.
+#define DORQ_REG_UCM_AGG_CMD_MASK_CONN_7_BB_K2                                                               0x1006d0UL //Access:RW   DataWidth:0x8    // Enable for UCM aggregation value command for connection 7.
+#define DORQ_REG_UCM_AGG_CMD_MASK_CONN_7_E5                                                                  0x102b44UL //Access:RW   DataWidth:0x8    // Enable for UCM aggregation value command for connection 7.
+#define DORQ_REG_UCM_AGG_CMD_MASK_CONN_8_E5                                                                  0x102b48UL //Access:RW   DataWidth:0x8    // Enable for UCM aggregation value command for connection 8.
+#define DORQ_REG_UCM_AGG_CMD_MASK_CONN_9_E5                                                                  0x102b4cUL //Access:RW   DataWidth:0x8    // Enable for UCM aggregation value command for connection 9.
+#define DORQ_REG_UCM_AGG_CMD_MASK_CONN_10_E5                                                                 0x102b50UL //Access:RW   DataWidth:0x8    // Enable for UCM aggregation value command for connection 10.
+#define DORQ_REG_UCM_AGG_CMD_MASK_CONN_11_E5                                                                 0x102b54UL //Access:RW   DataWidth:0x8    // Enable for UCM aggregation value command for connection 11.
+#define DORQ_REG_UCM_AGG_CMD_MASK_CONN_12_E5                                                                 0x102b58UL //Access:RW   DataWidth:0x8    // Enable for UCM aggregation value command for connection 12.
+#define DORQ_REG_UCM_AGG_CMD_MASK_CONN_13_E5                                                                 0x102b5cUL //Access:RW   DataWidth:0x8    // Enable for UCM aggregation value command for connection 13.
+#define DORQ_REG_UCM_AGG_CMD_MASK_CONN_14_E5                                                                 0x102b60UL //Access:RW   DataWidth:0x8    // Enable for UCM aggregation value command for connection 14.
+#define DORQ_REG_UCM_AGG_CMD_MASK_CONN_15_E5                                                                 0x102b64UL //Access:RW   DataWidth:0x8    // Enable for UCM aggregation value command for connection 15.
+#define DORQ_REG_RTC_TICK_SIZE_E5                                                                            0x102b68UL //Access:RW   DataWidth:0x8    // The number of 25MHz clock cycles per TCP RTC tick.
+#define DORQ_REG_RTC_CUR_VAL_E5                                                                              0x102b6cUL //Access:RW   DataWidth:0x20   // Used to set TCP RTC. Debug only.
+#define DORQ_REG_RTC_EN_E5                                                                                   0x102b70UL //Access:RW   DataWidth:0x1    // When set enables RTC increment on each tick.
+#define DORQ_REG_DDP_VERSION_E5                                                                              0x102b74UL //Access:RW   DataWidth:0x2    // DDP version in iWARP.
+#define DORQ_REG_RDMAP_VERSION_E5                                                                            0x102b78UL //Access:RW   DataWidth:0x2    // RDMAP version in iWARP.
+#define DORQ_REG_CRC32C_BSWAP_E5                                                                             0x102b7cUL //Access:RW   DataWidth:0x1    // If 0 - the iWARP CRC-32 final calculation result isn't byte swapped; if 1 - the CRC-32 final calculation result is byte swapped (byte [7:0] goes to location [31:24];etc).
+#define DORQ_REG_IWARP_OPCODE_EN_E5                                                                          0x102b80UL //Access:RW   DataWidth:0x20   // Enable bit per each iWARP Opcode 5 LSB-s. N-th bit set means corresponding opcode N is enabled, if reset the iWARP DPM with this opcode is aborted.
+#define DORQ_REG_PF_EXT_PCP_ROCE_E5                                                                          0x102b84UL //Access:RW   DataWidth:0x4    // The priority value and DEI bit in external VLAN TAG of RoCE frames per PF.
+#define DORQ_REG_PF_EXT_PCP_IWARP_E5                                                                         0x102b88UL //Access:RW   DataWidth:0x4    // The priority value and DEI bit in external VLAN TAG of iWARP frames per PF.
+#define DORQ_REG_PF_INT_PCP_ROCE_E5                                                                          0x102b8cUL //Access:RW   DataWidth:0x4    // The priority value and DEI bit in internal VLAN TAG of RoCE frames per PF.
+#define DORQ_REG_PF_INT_PCP_IWARP_E5                                                                         0x102b90UL //Access:RW   DataWidth:0x4    // The priority value and DEI bit internal VLAN TAG of iWARP frames per PF.
+#define DORQ_REG_PF_EXT_VID_ROCE_E5                                                                          0x102b94UL //Access:RW   DataWidth:0xc    // The external VLAN ID of RoCE frames per PF.
+#define DORQ_REG_PF_EXT_VID_IWARP_E5                                                                         0x102b98UL //Access:RW   DataWidth:0xc    // The external VLAN ID of iWARP frames per PF.
+#define DORQ_REG_PF_INT_VID_ROCE_E5                                                                          0x102b9cUL //Access:RW   DataWidth:0xc    // The internal VLAN ID of RoCE frames per PF.
+#define DORQ_REG_PF_INT_VID_IWARP_E5                                                                         0x102ba0UL //Access:RW   DataWidth:0xc    // The internal VLAN ID of iWARP frames per PF.
+#define DORQ_REG_RDMA_EN_PBF_SPC_ROCE_E5                                                                     0x102ba4UL //Access:RW   DataWidth:0x4    // Enable special flag indications to affect RDMA RoCE EDPM. Enables when set to 1.
+#define DORQ_REG_RDMA_EN_PBF_SPC_IWARP_E5                                                                    0x102ba8UL //Access:RW   DataWidth:0x4    // Enable special flag indications to affect RDMA iWARP EDPM. Enables when set to 1.
+#define DORQ_REG_L2_EN_PBF_SPC_E5                                                                            0x102bacUL //Access:RW   DataWidth:0x4    // Enable special flag indications to affect L2 EDPM. Enables when set to 1.
+#define DORQ_REG_EDPM_ROCE_EXIST_IN_QM_EN_E5                                                                 0x102bb0UL //Access:RW   DataWidth:0x4    // Indicates which ExistInQm bits are taken into account in RoCE EDPM check. If a bit equals 0 then the corresponding ExistInQm is not used (masked).
+#define DORQ_REG_EDPM_IWARP_EXIST_IN_QM_EN_E5                                                                0x102bb4UL //Access:RW   DataWidth:0x4    // Indicates which ExistInQm bits are taken into account in iWARP EDPM check. If a bit equals 0 then the corresponding ExistInQm is not used (masked).
+#define DORQ_REG_EDPM_L2_EXIST_IN_QM_EN_E5                                                                   0x102bb8UL //Access:RW   DataWidth:0x4    // Indicates which ExistInQm bits are taken into account in L2 EDPM check. If a bit equals 0 then the corresponding ExistInQm is not used (masked).
+#define DORQ_REG_DPM_ABORT_DETAILS_DPM_TYPE_E5                                                               0x102bbcUL //Access:R    DataWidth:0x2    // Stores the details of the first aborted doorbell after this register was cleared. It is reset on write to db_abort_details_rel. The following details of the transaction will be recorded: Doorbell DPM type. 0 - Legacy 1 - RDMA 2 - L2 Inline 3 - L2 Non-inline
+#define DORQ_REG_IEDPM_ABORT_DETAILS_BUFFER_E5                                                               0x102bc0UL //Access:R    DataWidth:0x2    // Stores the details of the first aborted IEDPM doorbell after this register was cleared. It is reset on write to db_abort_details_rel. The following details of the transaction will be recorded: IEDPM buffer number.
+#define DORQ_REG_IEDPM_ABORT_DETAILS_CID_E5                                                                  0x102bc4UL //Access:R    DataWidth:0x20   // Stores the details of the first aborted IEDPM doorbell after this register was cleared. It is reset on write to db_abort_details_rel. The following details of the transaction will be recorded: CID.
+#define DORQ_REG_IEDPM_ABORT_DETAILS_DPM_SIZE_E5                                                             0x102bc8UL //Access:R    DataWidth:0x6    // Stores the details of the first aborted IEDPM doorbell after this register was cleared. It is reset on write to db_abort_details_rel. The following details of the transaction will be recorded: Doorbell DPM size.
+#define DORQ_REG_IEDPM_ABORT_DETAILS_SRC_CLN_ID_E5                                                           0x102bccUL //Access:R    DataWidth:0x4    // Stores the details of the first aborted IEDPM doorbell after this register was cleared. It is reset on write to db_abort_details_rel. The following details of the transaction will be recorded: Source client ID.
+#define DORQ_REG_IEDPM_ABORT_DETAILS_REASON_E5                                                               0x102bd0UL //Access:R    DataWidth:0x4    // Stores the details of the first aborted doorbell after this register was cleared. It is reset on write to db_abort_details_rel. The following details of the transaction will be recorded: 0 - First DPM doorbell does not match DPM global start conditions at CFC load response for Internal EDPM doorbell; 1 - First DPM doorbell does not match DPM global start conditions at WAIT_CFC state for Internal EDPM doorbell; 2 - IEDPM context check fail; 3 - IEDPM DbTimer expiration;
+#define DORQ_REG_IEDPM_ABORT_DETAILS_REL_E5                                                                  0x102bd4UL //Access:W    DataWidth:0x1    // Clears iedpm_abort_details and makes it ready for the next details capture. Write only.
+#define DORQ_REG_IEDPM_ABORT_REASON_E5                                                                       0x102bd8UL //Access:R    DataWidth:0x4    // Sticky status of abort reason (a bit per reason). It is reset on write to db_abort_details_rel. 0 - First DPM doorbell does not match DPM global start conditions at CFC load response for Internal EDPM doorbell; 1 - First DPM doorbell does not match DPM global start conditions at WAIT_CFC state for Internal EDPM doorbell; 2 - IEDPM context check fail; 3 - IEDPM DbTimer expiration;
+#define DORQ_REG_IEDPM_DROP_DETAILS_REASON_E5                                                                0x102bdcUL //Access:R    DataWidth:0x5    // Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_details_rel. The following details of the transaction will be recorded: IEDPM doorbell drop reason: 4 - First QWord (offset 0) arives on IEDPM buffer which is not free; 3 - Non-first QWord (offset other than 0) arives on IEDPM buffer which is not free and non-contigious offset; 2 - Non-first QWord (offset other than 0) arives on IEDPM buffer which is free; 1 - Drop prior to being exposed to IEDPM buffer due to first drop doesn't include 2 QWords 0 - Drop prior to being exposed to IEDPM buffer due to ICID is greater or equal to PrvMaxIcid[DbPfid][DbFtype][5];
+#define DORQ_REG_IEDPM_DROP_DETAILS_SRC_CLN_E5                                                               0x102be0UL //Access:R    DataWidth:0x4    // Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_details_rel. The following details of the transaction will be recorded: Source client ID.
+#define DORQ_REG_IEDPM_DROP_DETAILS_DB_ADDR_E5                                                               0x102be4UL //Access:R    DataWidth:0x8    // Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_details_rel. The following details of the transaction will be recorded: Address.
+#define DORQ_REG_IEDPM_DROP_DETAILS_DB_LENGTH_E5                                                             0x102be8UL //Access:R    DataWidth:0x4    // Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_details_rel. The following details of the transaction will be recorded: Doorbell length in QWords (data only).
+#define DORQ_REG_IEDPM_DROP_DETAILS_DB_ICID_E5                                                               0x102becUL //Access:R    DataWidth:0x10   // Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_details_rel. The following details of the transaction will be recorded: Doorbell ICID.
+#define DORQ_REG_IEDPM_DROP_DETAILS_REL_E5                                                                   0x102bf0UL //Access:W    DataWidth:0x1    // Clears iedpm_drop_details and makes it ready for the next details capture. Write only.
+#define DORQ_REG_IEDPM_DROP_REASON_E5                                                                        0x102bf4UL //Access:R    DataWidth:0x5    // Sticky status of drop reason (a bit per reason). It is reset on write to iedpm_drop_details_rel. 4 - First QWord (offset 0) arives on IEDPM buffer which is not free; 3 - Non-first QWord (offset other than 0) arives on IEDPM buffer which is not free and non-contigious offset; 2 - Non-first QWord (offset other than 0) arives on IEDPM buffer which is free; 1 - Drop prior to being exposed to IEDPM buffer due to first drop doesn't include 2 QWords 0 - Drop prior to being exposed to IEDPM buffer due to ICID is greater or equal to PrvMaxIcid[DbPfid][DbFtype][5];
+#define DORQ_REG_IEDPM_DROP_REASON_MASK_E5                                                                   0x102bf8UL //Access:RW   DataWidth:0x5    // A bit mask per doorbell drop reason. If a bit is set (1), then corresponding drop reason will cause attention be set. If a bit is not set (0), then corresponding drop reason will not cause interrupt.
+#define DORQ_REG_IEDPM_GLB_COND_ABORT_CNT_E5                                                                 0x102bfcUL //Access:RC   DataWidth:0x20   // IEDPM global condition abort counter for Internal EDPM doorbell. It is reset on read.
+#define DORQ_REG_IEDPM_CTX_CHECK_ABORT_CNT_E5                                                                0x102c00UL //Access:RC   DataWidth:0x20   // IEDPM context check failure abort counter for Internal EDPM doorbell. It is reset on read.
+#define DORQ_REG_IEDPM_TIMER_EXPIR_ABORT_CNT_E5                                                              0x102c04UL //Access:RC   DataWidth:0x20   // IEDPM timer expiration failure abort counter for Internal EDPM doorbell. It is reset on read.
+#define DORQ_REG_IEDPM_DB_CNT_E5                                                                             0x102c08UL //Access:RC   DataWidth:0x20   // Accounts for number of Internal EDPM doorbells arrived. It is reset on read.
+#define DORQ_REG_L2_UPDATE_STORM_EVENT_ID_E5                                                                 0x102c0cUL //Access:RW   DataWidth:0x1    // The value of UpdPstormEventId flag in PBF command should be set.
+#define DORQ_REG_L2_SAME_AS_LAST_EN_E5                                                                       0x102c10UL //Access:RW   DataWidth:0x1    // Same as last enable flag sent in PBF command.
+#define DORQ_REG_L2_GFS_CMD_EXIST_FLG_E5                                                                     0x102c14UL //Access:RW   DataWidth:0x1    // GFS command exist flag sent in PBF command.
+#define DORQ_REG_ROCE_CONN_TYPE_E5                                                                           0x102c18UL //Access:RW   DataWidth:0x4    // RoCE connection type (used for iWARP/RoCE ICID range sharing).
+#define DORQ_REG_IWARP_CONN_TYPE_E5                                                                          0x102c1cUL //Access:RW   DataWidth:0x4    // iWARP connection type (used for iWARP/RoCE ICID range sharing).
+#define DORQ_REG_L2_PCM_EVENT_ID_E5                                                                          0x102c20UL //Access:RW   DataWidth:0x8    // Event ID, which is sent in the PCM message (part of PBF command) in L2 EDPM.
+#define DORQ_REG_QM_BYP_AFF_TYPE_E5                                                                          0x102c24UL //Access:RW   DataWidth:0x2    // The value of affinity type in CM header sent to XCM in case of QM bypass.
+#define DORQ_REG_QM_BYP_EXCL_FLG_E5                                                                          0x102c28UL //Access:RW   DataWidth:0x1    // The value of exclusive flag in CM header sent to XCM in case of QM bypass.
+#define DORQ_REG_QM_BYP_SRC_AFF_E5                                                                           0x102c2cUL //Access:RW   DataWidth:0x3    // The value of source affinity in CM header sent to XCM in case of QM bypass.
+#define DORQ_REG_DPM_AFF_TYPE_0_E5                                                                           0x102c30UL //Access:RW   DataWidth:0x2    // The value of affinity type in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 0.
+#define DORQ_REG_DPM_AFF_TYPE_1_E5                                                                           0x102c34UL //Access:RW   DataWidth:0x2    // The value of affinity type in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 1.
+#define DORQ_REG_DPM_AFF_TYPE_2_E5                                                                           0x102c38UL //Access:RW   DataWidth:0x2    // The value of affinity type in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 2.
+#define DORQ_REG_DPM_AFF_TYPE_3_E5                                                                           0x102c3cUL //Access:RW   DataWidth:0x2    // The value of affinity type in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 3.
+#define DORQ_REG_DPM_AFF_TYPE_4_E5                                                                           0x102c40UL //Access:RW   DataWidth:0x2    // The value of affinity type in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 4.
+#define DORQ_REG_DPM_AFF_TYPE_5_E5                                                                           0x102c44UL //Access:RW   DataWidth:0x2    // The value of affinity type in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 5.
+#define DORQ_REG_DPM_AFF_TYPE_6_E5                                                                           0x102c48UL //Access:RW   DataWidth:0x2    // The value of affinity type in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 6.
+#define DORQ_REG_DPM_AFF_TYPE_7_E5                                                                           0x102c4cUL //Access:RW   DataWidth:0x2    // The value of affinity type in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 7.
+#define DORQ_REG_DPM_AFF_TYPE_8_E5                                                                           0x102c50UL //Access:RW   DataWidth:0x2    // The value of affinity type in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 8.
+#define DORQ_REG_DPM_AFF_TYPE_9_E5                                                                           0x102c54UL //Access:RW   DataWidth:0x2    // The value of affinity type in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 9.
+#define DORQ_REG_DPM_AFF_TYPE_10_E5                                                                          0x102c58UL //Access:RW   DataWidth:0x2    // The value of affinity type in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 10.
+#define DORQ_REG_DPM_AFF_TYPE_11_E5                                                                          0x102c5cUL //Access:RW   DataWidth:0x2    // The value of affinity type in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 11.
+#define DORQ_REG_DPM_AFF_TYPE_12_E5                                                                          0x102c60UL //Access:RW   DataWidth:0x2    // The value of affinity type in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 12.
+#define DORQ_REG_DPM_AFF_TYPE_13_E5                                                                          0x102c64UL //Access:RW   DataWidth:0x2    // The value of affinity type in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 13.
+#define DORQ_REG_DPM_AFF_TYPE_14_E5                                                                          0x102c68UL //Access:RW   DataWidth:0x2    // The value of affinity type in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 14.
+#define DORQ_REG_DPM_AFF_TYPE_15_E5                                                                          0x102c6cUL //Access:RW   DataWidth:0x2    // The value of affinity type in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 15.
+#define DORQ_REG_DPM_EXCL_FLG_0_E5                                                                           0x102c70UL //Access:RW   DataWidth:0x1    // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 0.
+#define DORQ_REG_DPM_EXCL_FLG_1_E5                                                                           0x102c74UL //Access:RW   DataWidth:0x1    // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 1.
+#define DORQ_REG_DPM_EXCL_FLG_2_E5                                                                           0x102c78UL //Access:RW   DataWidth:0x1    // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 2.
+#define DORQ_REG_DPM_EXCL_FLG_3_E5                                                                           0x102c7cUL //Access:RW   DataWidth:0x1    // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 3.
+#define DORQ_REG_DPM_EXCL_FLG_4_E5                                                                           0x102c80UL //Access:RW   DataWidth:0x1    // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 4.
+#define DORQ_REG_DPM_EXCL_FLG_5_E5                                                                           0x102c84UL //Access:RW   DataWidth:0x1    // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 5.
+#define DORQ_REG_DPM_EXCL_FLG_6_E5                                                                           0x102c88UL //Access:RW   DataWidth:0x1    // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 6.
+#define DORQ_REG_DPM_EXCL_FLG_7_E5                                                                           0x102c8cUL //Access:RW   DataWidth:0x1    // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 7.
+#define DORQ_REG_DPM_EXCL_FLG_8_E5                                                                           0x102c90UL //Access:RW   DataWidth:0x1    // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 8.
+#define DORQ_REG_DPM_EXCL_FLG_9_E5                                                                           0x102c94UL //Access:RW   DataWidth:0x1    // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 9.
+#define DORQ_REG_DPM_EXCL_FLG_10_E5                                                                          0x102c98UL //Access:RW   DataWidth:0x1    // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 10.
+#define DORQ_REG_DPM_EXCL_FLG_11_E5                                                                          0x102c9cUL //Access:RW   DataWidth:0x1    // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 11.
+#define DORQ_REG_DPM_EXCL_FLG_12_E5                                                                          0x102ca0UL //Access:RW   DataWidth:0x1    // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 12.
+#define DORQ_REG_DPM_EXCL_FLG_13_E5                                                                          0x102ca4UL //Access:RW   DataWidth:0x1    // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 13.
+#define DORQ_REG_DPM_EXCL_FLG_14_E5                                                                          0x102ca8UL //Access:RW   DataWidth:0x1    // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 14.
+#define DORQ_REG_DPM_EXCL_FLG_15_E5                                                                          0x102cacUL //Access:RW   DataWidth:0x1    // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 15.
+#define DORQ_REG_DPM_SRC_AFF_0_E5                                                                            0x102cb0UL //Access:RW   DataWidth:0x3    // The value of source affinity in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 0.
+#define DORQ_REG_DPM_SRC_AFF_1_E5                                                                            0x102cb4UL //Access:RW   DataWidth:0x3    // The value of source affinity in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 1.
+#define DORQ_REG_DPM_SRC_AFF_2_E5                                                                            0x102cb8UL //Access:RW   DataWidth:0x3    // The value of source affinity in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 2.
+#define DORQ_REG_DPM_SRC_AFF_3_E5                                                                            0x102cbcUL //Access:RW   DataWidth:0x3    // The value of source affinity in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 3.
+#define DORQ_REG_DPM_SRC_AFF_4_E5                                                                            0x102cc0UL //Access:RW   DataWidth:0x3    // The value of source affinity in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 4.
+#define DORQ_REG_DPM_SRC_AFF_5_E5                                                                            0x102cc4UL //Access:RW   DataWidth:0x3    // The value of source affinity in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 5.
+#define DORQ_REG_DPM_SRC_AFF_6_E5                                                                            0x102cc8UL //Access:RW   DataWidth:0x3    // The value of source affinity in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 6.
+#define DORQ_REG_DPM_SRC_AFF_7_E5                                                                            0x102cccUL //Access:RW   DataWidth:0x3    // The value of source affinity in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 7.
+#define DORQ_REG_DPM_SRC_AFF_8_E5                                                                            0x102cd0UL //Access:RW   DataWidth:0x3    // The value of source affinity in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 8.
+#define DORQ_REG_DPM_SRC_AFF_9_E5                                                                            0x102cd4UL //Access:RW   DataWidth:0x3    // The value of source affinity in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 9.
+#define DORQ_REG_DPM_SRC_AFF_10_E5                                                                           0x102cd8UL //Access:RW   DataWidth:0x3    // The value of source affinity in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 10.
+#define DORQ_REG_DPM_SRC_AFF_11_E5                                                                           0x102cdcUL //Access:RW   DataWidth:0x3    // The value of source affinity in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 11.
+#define DORQ_REG_DPM_SRC_AFF_12_E5                                                                           0x102ce0UL //Access:RW   DataWidth:0x3    // The value of source affinity in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 12.
+#define DORQ_REG_DPM_SRC_AFF_13_E5                                                                           0x102ce4UL //Access:RW   DataWidth:0x3    // The value of source affinity in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 13.
+#define DORQ_REG_DPM_SRC_AFF_14_E5                                                                           0x102ce8UL //Access:RW   DataWidth:0x3    // The value of source affinity in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 14.
+#define DORQ_REG_DPM_SRC_AFF_15_E5                                                                           0x102cecUL //Access:RW   DataWidth:0x3    // The value of source affinity in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 15.
+#define DORQ_REG_DPM_IWARP_SUCCESS_CNT_E5                                                                    0x102cf0UL //Access:RC   DataWidth:0x20   // Number of successfull iWARP EDPM doorbells. It is reset on read.
+#define DORQ_REG_DPM_IEDPM_SUCCESS_CNT_E5                                                                    0x102cf4UL //Access:RC   DataWidth:0x20   // Number of successfull iWARP EDPM doorbells. It is reset on read.
+#define DORQ_REG_DORQ_FIFO                                                                                   0x108000UL //Access:R    DataWidth:0x20   // Debug only: Read access to DQ FIFO.
+#define DORQ_REG_DORQ_FIFO_SIZE                                                                              4100
+#define IGU_REG_RESET_MEMORIES                                                                               0x180000UL //Access:RW   DataWidth:0x7    // Write one for each bit resets the appropriate memory. When the memory reset finished the appropriate bit is cleared. Bit 0 - mapping memory; Bit 1 - SB memory (producer and consumer); Bit 2 - SB interrupt before mask and mask memories; Bit 3 - MSIX memory; Bit 4 - PBA memory; Bit 5 - number of messages sent statistics; Bit 6 - RL memories (variable 0, variable 1 and statistics).
+#define IGU_REG_BLOCK_CONFIGURATION                                                                          0x180040UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN                                                   (0x1<<0) // If enabled the IGU forwards write/read requests to the TPH interface. 1 - enabled; 0 - disabled.
+  #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN_SHIFT                                             0
+  #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN                                                          (0x1<<1) // If enabled the IGU allows to VF to send cleanup commands on the int ack address. 1 - enabled; 0 - disabled.
+  #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN_SHIFT                                                    1
+  #define IGU_REG_BLOCK_CONFIGURATION_RL_BYPASS_EN                                                           (0x1<<2) // If enabled the IGU allows bypass mode of the rate limiter when the system is empty. 1 - enabled; 0 - disabled.
+  #define IGU_REG_BLOCK_CONFIGURATION_RL_BYPASS_EN_SHIFT                                                     2
+#define IGU_REG_PXP_REQUESTER_INITIAL_CREDIT                                                                 0x180050UL //Access:RW   DataWidth:0x2    // PXP req credit. The max number of outstanding messages to the PXP request. The value can be one or two only.
+#define IGU_REG_CAM_BIST_EN_BB                                                                               0x180060UL //Access:RW   DataWidth:0x1    // Used to enable/disable BIST mode. When set, BIST testing will be performed and the results will be posted upon completion. When cleared CAM access will be enabled through the CAM BIST mechanism instead.
+#define IGU_REG_CAM_BIST_SKIP_ERROR_CNT_BB                                                                   0x180064UL //Access:RW   DataWidth:0x8    // Provides a threshold for the number of CAM BIST errors that are acceptable before reporting CAM BIST failure status.
+#define IGU_REG_CAM_BIST_STATUS_SEL_BB                                                                       0x180068UL //Access:RW   DataWidth:0x8    // Used to select the BIST status word to read following the completion of a BIST test. Also used to select the data slice when writing data directly to the CAM using the CAM BIST mechanism.
+#define IGU_REG_CAM_BIST_STATUS_BB                                                                           0x18006cUL //Access:R    DataWidth:0x20   // Provides read-only access to the BIST status word selected by cam_bist_status_sel.
+#define IGU_REG_CAM_BIST_DBG_DATA_BB                                                                         0x180070UL //Access:RW   DataWidth:0x20   // For CAM bist usage.
+#define IGU_REG_CAM_BIST_DBG_DATA_VALID_BB                                                                   0x180074UL //Access:RW   DataWidth:0x1    // For CAM bist usage.
+#define IGU_REG_CAM_BIST_DBG_COMPARE_EN_BB                                                                   0x180078UL //Access:RW   DataWidth:0x1    // For CAM bist usage.
+#define IGU_REG_INT_STS                                                                                      0x180180UL //Access:R    DataWidth:0xb    // Multi Field Register.
+  #define IGU_REG_INT_STS_ADDRESS_ERROR                                                                      (0x1<<0) // Signals an unknown address to the rf module.
+  #define IGU_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                                0
+  #define IGU_REG_INT_STS_CTRL_FIFO_ERROR_ERR                                                                (0x1<<1) // Debug FIFO error. Write to full FIFO or read from empty FIFO.
+  #define IGU_REG_INT_STS_CTRL_FIFO_ERROR_ERR_SHIFT                                                          1
+  #define IGU_REG_INT_STS_PXP_REQ_LENGTH_TOO_BIG                                                             (0x1<<2) // PXP write message length bigger then one.
+  #define IGU_REG_INT_STS_PXP_REQ_LENGTH_TOO_BIG_SHIFT                                                       2
+  #define IGU_REG_INT_STS_HOST_TRIES2ACCESS_PROD_UPD                                                         (0x1<<3) // Host write producer update command.
+  #define IGU_REG_INT_STS_HOST_TRIES2ACCESS_PROD_UPD_SHIFT                                                   3
+  #define IGU_REG_INT_STS_VF_TRIES2ACC_ATTN_CMD                                                              (0x1<<4) // VFID bit is set and the command is to attention bit set/clr/upd.
+  #define IGU_REG_INT_STS_VF_TRIES2ACC_ATTN_CMD_SHIFT                                                        4
+  #define IGU_REG_INT_STS_MME_BIGGER_THEN_5                                                                  (0x1<<5) // MME value in MSI control is bigger than 5.
+  #define IGU_REG_INT_STS_MME_BIGGER_THEN_5_SHIFT                                                            5
+  #define IGU_REG_INT_STS_SB_INDEX_IS_NOT_VALID                                                              (0x1<<6) // Prod / Cons update command to invalid SB index.
+  #define IGU_REG_INT_STS_SB_INDEX_IS_NOT_VALID_SHIFT                                                        6
+  #define IGU_REG_INT_STS_DURIN_INT_READ_WITH_SIMD_DIS                                                       (0x1<<7) // During interrupt read from function that is not in SIMD mode.
+  #define IGU_REG_INT_STS_DURIN_INT_READ_WITH_SIMD_DIS_SHIFT                                                 7
+  #define IGU_REG_INT_STS_CMD_FID_NOT_MATCH                                                                  (0x1<<8) // Command FID not match mapping FID.
+  #define IGU_REG_INT_STS_CMD_FID_NOT_MATCH_SHIFT                                                            8
+  #define IGU_REG_INT_STS_SEGMENT_ACCESS_INVALID                                                             (0x1<<9) // Removed.
+  #define IGU_REG_INT_STS_SEGMENT_ACCESS_INVALID_SHIFT                                                       9
+  #define IGU_REG_INT_STS_ATTN_PROD_ACC                                                                      (0x1<<10) // Update producer command to attention producer.
+  #define IGU_REG_INT_STS_ATTN_PROD_ACC_SHIFT                                                                10
+#define IGU_REG_INT_MASK                                                                                     0x180184UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define IGU_REG_INT_MASK_ADDRESS_ERROR                                                                     (0x1<<0) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.ADDRESS_ERROR .
+  #define IGU_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                               0
+  #define IGU_REG_INT_MASK_CTRL_FIFO_ERROR_ERR                                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.CTRL_FIFO_ERROR_ERR .
+  #define IGU_REG_INT_MASK_CTRL_FIFO_ERROR_ERR_SHIFT                                                         1
+  #define IGU_REG_INT_MASK_PXP_REQ_LENGTH_TOO_BIG                                                            (0x1<<2) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.PXP_REQ_LENGTH_TOO_BIG .
+  #define IGU_REG_INT_MASK_PXP_REQ_LENGTH_TOO_BIG_SHIFT                                                      2
+  #define IGU_REG_INT_MASK_HOST_TRIES2ACCESS_PROD_UPD                                                        (0x1<<3) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.HOST_TRIES2ACCESS_PROD_UPD .
+  #define IGU_REG_INT_MASK_HOST_TRIES2ACCESS_PROD_UPD_SHIFT                                                  3
+  #define IGU_REG_INT_MASK_VF_TRIES2ACC_ATTN_CMD                                                             (0x1<<4) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.VF_TRIES2ACC_ATTN_CMD .
+  #define IGU_REG_INT_MASK_VF_TRIES2ACC_ATTN_CMD_SHIFT                                                       4
+  #define IGU_REG_INT_MASK_MME_BIGGER_THEN_5                                                                 (0x1<<5) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.MME_BIGGER_THEN_5 .
+  #define IGU_REG_INT_MASK_MME_BIGGER_THEN_5_SHIFT                                                           5
+  #define IGU_REG_INT_MASK_SB_INDEX_IS_NOT_VALID                                                             (0x1<<6) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.SB_INDEX_IS_NOT_VALID .
+  #define IGU_REG_INT_MASK_SB_INDEX_IS_NOT_VALID_SHIFT                                                       6
+  #define IGU_REG_INT_MASK_DURIN_INT_READ_WITH_SIMD_DIS                                                      (0x1<<7) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.DURIN_INT_READ_WITH_SIMD_DIS .
+  #define IGU_REG_INT_MASK_DURIN_INT_READ_WITH_SIMD_DIS_SHIFT                                                7
+  #define IGU_REG_INT_MASK_CMD_FID_NOT_MATCH                                                                 (0x1<<8) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.CMD_FID_NOT_MATCH .
+  #define IGU_REG_INT_MASK_CMD_FID_NOT_MATCH_SHIFT                                                           8
+  #define IGU_REG_INT_MASK_SEGMENT_ACCESS_INVALID                                                            (0x1<<9) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.SEGMENT_ACCESS_INVALID .
+  #define IGU_REG_INT_MASK_SEGMENT_ACCESS_INVALID_SHIFT                                                      9
+  #define IGU_REG_INT_MASK_ATTN_PROD_ACC                                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.ATTN_PROD_ACC .
+  #define IGU_REG_INT_MASK_ATTN_PROD_ACC_SHIFT                                                               10
+#define IGU_REG_INT_STS_WR                                                                                   0x180188UL //Access:WR   DataWidth:0xb    // Multi Field Register.
+  #define IGU_REG_INT_STS_WR_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define IGU_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                             0
+  #define IGU_REG_INT_STS_WR_CTRL_FIFO_ERROR_ERR                                                             (0x1<<1) // Debug FIFO error. Write to full FIFO or read from empty FIFO.
+  #define IGU_REG_INT_STS_WR_CTRL_FIFO_ERROR_ERR_SHIFT                                                       1
+  #define IGU_REG_INT_STS_WR_PXP_REQ_LENGTH_TOO_BIG                                                          (0x1<<2) // PXP write message length bigger then one.
+  #define IGU_REG_INT_STS_WR_PXP_REQ_LENGTH_TOO_BIG_SHIFT                                                    2
+  #define IGU_REG_INT_STS_WR_HOST_TRIES2ACCESS_PROD_UPD                                                      (0x1<<3) // Host write producer update command.
+  #define IGU_REG_INT_STS_WR_HOST_TRIES2ACCESS_PROD_UPD_SHIFT                                                3
+  #define IGU_REG_INT_STS_WR_VF_TRIES2ACC_ATTN_CMD                                                           (0x1<<4) // VFID bit is set and the command is to attention bit set/clr/upd.
+  #define IGU_REG_INT_STS_WR_VF_TRIES2ACC_ATTN_CMD_SHIFT                                                     4
+  #define IGU_REG_INT_STS_WR_MME_BIGGER_THEN_5                                                               (0x1<<5) // MME value in MSI control is bigger than 5.
+  #define IGU_REG_INT_STS_WR_MME_BIGGER_THEN_5_SHIFT                                                         5
+  #define IGU_REG_INT_STS_WR_SB_INDEX_IS_NOT_VALID                                                           (0x1<<6) // Prod / Cons update command to invalid SB index.
+  #define IGU_REG_INT_STS_WR_SB_INDEX_IS_NOT_VALID_SHIFT                                                     6
+  #define IGU_REG_INT_STS_WR_DURIN_INT_READ_WITH_SIMD_DIS                                                    (0x1<<7) // During interrupt read from function that is not in SIMD mode.
+  #define IGU_REG_INT_STS_WR_DURIN_INT_READ_WITH_SIMD_DIS_SHIFT                                              7
+  #define IGU_REG_INT_STS_WR_CMD_FID_NOT_MATCH                                                               (0x1<<8) // Command FID not match mapping FID.
+  #define IGU_REG_INT_STS_WR_CMD_FID_NOT_MATCH_SHIFT                                                         8
+  #define IGU_REG_INT_STS_WR_SEGMENT_ACCESS_INVALID                                                          (0x1<<9) // Removed.
+  #define IGU_REG_INT_STS_WR_SEGMENT_ACCESS_INVALID_SHIFT                                                    9
+  #define IGU_REG_INT_STS_WR_ATTN_PROD_ACC                                                                   (0x1<<10) // Update producer command to attention producer.
+  #define IGU_REG_INT_STS_WR_ATTN_PROD_ACC_SHIFT                                                             10
+#define IGU_REG_INT_STS_CLR                                                                                  0x18018cUL //Access:RC   DataWidth:0xb    // Multi Field Register.
+  #define IGU_REG_INT_STS_CLR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define IGU_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                            0
+  #define IGU_REG_INT_STS_CLR_CTRL_FIFO_ERROR_ERR                                                            (0x1<<1) // Debug FIFO error. Write to full FIFO or read from empty FIFO.
+  #define IGU_REG_INT_STS_CLR_CTRL_FIFO_ERROR_ERR_SHIFT                                                      1
+  #define IGU_REG_INT_STS_CLR_PXP_REQ_LENGTH_TOO_BIG                                                         (0x1<<2) // PXP write message length bigger then one.
+  #define IGU_REG_INT_STS_CLR_PXP_REQ_LENGTH_TOO_BIG_SHIFT                                                   2
+  #define IGU_REG_INT_STS_CLR_HOST_TRIES2ACCESS_PROD_UPD                                                     (0x1<<3) // Host write producer update command.
+  #define IGU_REG_INT_STS_CLR_HOST_TRIES2ACCESS_PROD_UPD_SHIFT                                               3
+  #define IGU_REG_INT_STS_CLR_VF_TRIES2ACC_ATTN_CMD                                                          (0x1<<4) // VFID bit is set and the command is to attention bit set/clr/upd.
+  #define IGU_REG_INT_STS_CLR_VF_TRIES2ACC_ATTN_CMD_SHIFT                                                    4
+  #define IGU_REG_INT_STS_CLR_MME_BIGGER_THEN_5                                                              (0x1<<5) // MME value in MSI control is bigger than 5.
+  #define IGU_REG_INT_STS_CLR_MME_BIGGER_THEN_5_SHIFT                                                        5
+  #define IGU_REG_INT_STS_CLR_SB_INDEX_IS_NOT_VALID                                                          (0x1<<6) // Prod / Cons update command to invalid SB index.
+  #define IGU_REG_INT_STS_CLR_SB_INDEX_IS_NOT_VALID_SHIFT                                                    6
+  #define IGU_REG_INT_STS_CLR_DURIN_INT_READ_WITH_SIMD_DIS                                                   (0x1<<7) // During interrupt read from function that is not in SIMD mode.
+  #define IGU_REG_INT_STS_CLR_DURIN_INT_READ_WITH_SIMD_DIS_SHIFT                                             7
+  #define IGU_REG_INT_STS_CLR_CMD_FID_NOT_MATCH                                                              (0x1<<8) // Command FID not match mapping FID.
+  #define IGU_REG_INT_STS_CLR_CMD_FID_NOT_MATCH_SHIFT                                                        8
+  #define IGU_REG_INT_STS_CLR_SEGMENT_ACCESS_INVALID                                                         (0x1<<9) // Removed.
+  #define IGU_REG_INT_STS_CLR_SEGMENT_ACCESS_INVALID_SHIFT                                                   9
+  #define IGU_REG_INT_STS_CLR_ATTN_PROD_ACC                                                                  (0x1<<10) // Update producer command to attention producer.
+  #define IGU_REG_INT_STS_CLR_ATTN_PROD_ACC_SHIFT                                                            10
+#define IGU_REG_PRTY_MASK                                                                                    0x180194UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define IGU_REG_PRTY_MASK_CAM_PARITY                                                                       (0x1<<0) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS.CAM_PARITY .
+  #define IGU_REG_PRTY_MASK_CAM_PARITY_SHIFT                                                                 0
+#define IGU_REG_PRTY_MASK_H_0_BB_K2                                                                          0x180204UL //Access:RW   DataWidth:0x1c   // Multi Field Register.
+  #define IGU_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_BB_K2                                                    (0x1<<0) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM009_I_ECC_RF_INT .
+  #define IGU_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_BB_K2_SHIFT                                              0
+  #define IGU_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2                                                         (0x1<<1) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
+  #define IGU_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2_SHIFT                                                   1
+  #define IGU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB                                                         (0x1<<1) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
+  #define IGU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_SHIFT                                                   1
+  #define IGU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2                                                         (0x1<<2) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
+  #define IGU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2_SHIFT                                                   2
+  #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB                                                         (0x1<<2) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
+  #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_SHIFT                                                   2
+  #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2                                                         (0x1<<3) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
+  #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_SHIFT                                                   3
+  #define IGU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB                                                         (0x1<<3) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
+  #define IGU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_SHIFT                                                   3
+  #define IGU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2                                                         (0x1<<4) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
+  #define IGU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2_SHIFT                                                   4
+  #define IGU_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB                                                         (0x1<<4) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
+  #define IGU_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_SHIFT                                                   4
+  #define IGU_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2                                                         (0x1<<5) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
+  #define IGU_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_SHIFT                                                   5
+  #define IGU_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                      (0x1<<6) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define IGU_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                                6
+  #define IGU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_0_K2                                                       (0x1<<7) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_0 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_0_K2_SHIFT                                                 7
+  #define IGU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_1_K2                                                       (0x1<<8) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_1 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_1_K2_SHIFT                                                 8
+  #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_0_BB                                                       (0x1<<7) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_0 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_0_BB_SHIFT                                                 7
+  #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_0_K2                                                       (0x1<<9) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_0 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_0_K2_SHIFT                                                 9
+  #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_1_BB                                                       (0x1<<8) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_1 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_1_BB_SHIFT                                                 8
+  #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_1_K2                                                       (0x1<<10) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_1 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_1_K2_SHIFT                                                 10
+  #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_2_K2                                                       (0x1<<11) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_2 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_2_K2_SHIFT                                                 11
+  #define IGU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2                                                         (0x1<<12) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define IGU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_SHIFT                                                   12
+  #define IGU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2                                                      (0x1<<13) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define IGU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT                                                13
+  #define IGU_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_0_K2                                                       (0x1<<14) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY_0 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_0_K2_SHIFT                                                 14
+  #define IGU_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_1_K2                                                       (0x1<<15) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY_1 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_1_K2_SHIFT                                                 15
+  #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_0_BB                                                       (0x1<<14) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY_0 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_0_BB_SHIFT                                                 14
+  #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_0_K2                                                       (0x1<<16) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY_0 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_0_K2_SHIFT                                                 16
+  #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_1_BB                                                       (0x1<<15) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY_1 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_1_BB_SHIFT                                                 15
+  #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_1_K2                                                       (0x1<<17) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY_1 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_1_K2_SHIFT                                                 17
+  #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_2_K2                                                       (0x1<<18) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY_2 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_2_K2_SHIFT                                                 18
+  #define IGU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2                                                         (0x1<<19) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define IGU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_SHIFT                                                   19
+  #define IGU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_0_BB_K2                                                    (0x1<<20) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY_0 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_0_BB_K2_SHIFT                                              20
+  #define IGU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_1_BB_K2                                                    (0x1<<21) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY_1 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_1_BB_K2_SHIFT                                              21
+  #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_0_BB                                                       (0x1<<26) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY_0 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_0_BB_SHIFT                                                 26
+  #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_0_K2                                                       (0x1<<22) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY_0 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_0_K2_SHIFT                                                 22
+  #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_1_BB                                                       (0x1<<27) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY_1 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_1_BB_SHIFT                                                 27
+  #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_1_K2                                                       (0x1<<23) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY_1 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_1_K2_SHIFT                                                 23
+  #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_2_BB                                                       (0x1<<28) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY_2 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_2_BB_SHIFT                                                 28
+  #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_2_K2                                                       (0x1<<24) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY_2 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_2_K2_SHIFT                                                 24
+  #define IGU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB                                                         (0x1<<29) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
+  #define IGU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_SHIFT                                                   29
+  #define IGU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2                                                         (0x1<<25) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
+  #define IGU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2_SHIFT                                                   25
+  #define IGU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2                                                         (0x1<<26) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
+  #define IGU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2_SHIFT                                                   26
+  #define IGU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB                                                         (0x1<<30) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
+  #define IGU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_SHIFT                                                   30
+  #define IGU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2                                                         (0x1<<27) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
+  #define IGU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2_SHIFT                                                   27
+  #define IGU_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB                                                         (0x1<<5) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
+  #define IGU_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_SHIFT                                                   5
+  #define IGU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_0_BB                                                       (0x1<<9) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY_0 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_0_BB_SHIFT                                                 9
+  #define IGU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_1_BB                                                       (0x1<<10) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY_1 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_1_BB_SHIFT                                                 10
+  #define IGU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_2_BB                                                       (0x1<<11) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY_2 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_2_BB_SHIFT                                                 11
+  #define IGU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB                                                         (0x1<<12) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define IGU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_SHIFT                                                   12
+  #define IGU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_BB                                                       (0x1<<16) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_0 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_BB_SHIFT                                                 16
+  #define IGU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_BB                                                       (0x1<<17) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_1 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_BB_SHIFT                                                 17
+  #define IGU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_2_BB                                                       (0x1<<18) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_2 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_2_BB_SHIFT                                                 18
+  #define IGU_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB                                                         (0x1<<19) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define IGU_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_SHIFT                                                   19
+  #define IGU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_2_BB                                                       (0x1<<22) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY_2 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_2_BB_SHIFT                                                 22
+  #define IGU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_3_BB                                                       (0x1<<23) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY_3 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_3_BB_SHIFT                                                 23
+  #define IGU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_0_BB                                                       (0x1<<24) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY_0 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_0_BB_SHIFT                                                 24
+  #define IGU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_1_BB                                                       (0x1<<25) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY_1 .
+  #define IGU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_1_BB_SHIFT                                                 25
+#define IGU_REG_MEM_ECC_ENABLE_0_BB                                                                          0x180220UL //Access:RW   DataWidth:0x1    // Enable ECC for memory ecc instance igu.IGU_MSIX_288_SB_IF.i_igu_msix_mem.i_ecc in module igu_msix_288_sb_mem
+#define IGU_REG_MEM_ECC_ENABLE_0_K2                                                                          0x180210UL //Access:RW   DataWidth:0x1    // Enable ECC for memory ecc instance igu.IGU_MSIX_368_SB_IF.i_igu_msix_mem.i_ecc in module igu_msix_368_sb_mem
+#define IGU_REG_MEM_ECC_PARITY_ONLY_0_BB                                                                     0x180224UL //Access:RW   DataWidth:0x1    // Set parity only for memory ecc instance igu.IGU_MSIX_288_SB_IF.i_igu_msix_mem.i_ecc in module igu_msix_288_sb_mem
+#define IGU_REG_MEM_ECC_PARITY_ONLY_0_K2                                                                     0x180214UL //Access:RW   DataWidth:0x1    // Set parity only for memory ecc instance igu.IGU_MSIX_368_SB_IF.i_igu_msix_mem.i_ecc in module igu_msix_368_sb_mem
+#define IGU_REG_PRTY_MASK_H_1_BB                                                                             0x180214UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define IGU_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_BB                                                         (0x1<<0) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY .
+  #define IGU_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_BB_SHIFT                                                   0
+#define IGU_REG_MEM_ECC_ERROR_CORRECTED_0_BB                                                                 0x180228UL //Access:RC   DataWidth:0x1    // Record if a correctable error occurred on memory ecc instance igu.IGU_MSIX_288_SB_IF.i_igu_msix_mem.i_ecc in module igu_msix_288_sb_mem
+#define IGU_REG_MEM_ECC_ERROR_CORRECTED_0_K2                                                                 0x180218UL //Access:RC   DataWidth:0x1    // Record if a correctable error occurred on memory ecc instance igu.IGU_MSIX_368_SB_IF.i_igu_msix_mem.i_ecc in module igu_msix_368_sb_mem
+#define IGU_REG_MEM_ECC_EVENTS_BB                                                                            0x18022cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define IGU_REG_MEM_ECC_EVENTS_K2                                                                            0x18021cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define IGU_REG_STATISTIC_NUM_PF_MSG_SENT                                                                    0x180400UL //Access:RW   DataWidth:0x14   // Debug: Number of MSI/MSIX/ATTN messages sent for the PF: address 0 - number of MSI/MSIX messages; address 1 - number of ATTN messages.
+#define IGU_REG_STATISTIC_NUM_PF_MSG_SENT_SIZE                                                               2
+#define IGU_REG_STATISTIC_NUM_VF_MSG_SENT                                                                    0x180408UL //Access:RW   DataWidth:0x14   // Debug: Number of MSI/MSIX messages sent for VF.
+#define IGU_REG_PXP_REQUEST_COUNTER                                                                          0x18040cUL //Access:R    DataWidth:0x20   // Debug: number of PXP messeges sent (attention, msi and msix).
+#define IGU_REG_PXP_WRITE_DONE_COUNTER                                                                       0x180410UL //Access:R    DataWidth:0x20   // Debug: number of PXP write done received (attention, msi and msix).
+#define IGU_REG_PXP_REQ_COUNTER_CTL                                                                          0x180414UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define IGU_REG_PXP_REQ_COUNTER_CTL_PXP_REQ_COUNTER_SB_NUM                                                 (0x1ff<<0) // Debug: SB index for the counter.
+  #define IGU_REG_PXP_REQ_COUNTER_CTL_PXP_REQ_COUNTER_SB_NUM_SHIFT                                           0
+  #define IGU_REG_PXP_REQ_COUNTER_CTL_PXP_REQ_COUNTER_SB_NUM_MASK_EN                                         (0x1<<9) // Debug: if set the counter is active.
+  #define IGU_REG_PXP_REQ_COUNTER_CTL_PXP_REQ_COUNTER_SB_NUM_MASK_EN_SHIFT                                   9
+#define IGU_REG_PXP_REQ_COUNTER                                                                              0x180418UL //Access:RC   DataWidth:0x20   // Debug: count the number of PXP requests sent on behalf of a specific MSI/MSI-X vector on the SB index in pxp_req_counter_sb_num.
+#define IGU_REG_PROD_UPD_COUNTER_CTL                                                                         0x18041cUL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define IGU_REG_PROD_UPD_COUNTER_CTL_PROD_UPD_COUNTER_SB_NUM                                               (0x1ff<<0) // Debug: SB index for the counter.
+  #define IGU_REG_PROD_UPD_COUNTER_CTL_PROD_UPD_COUNTER_SB_NUM_SHIFT                                         0
+  #define IGU_REG_PROD_UPD_COUNTER_CTL_PROD_UPD_COUNTER_SB_NUM_MASK_EN                                       (0x1<<9) // Debug: if set the counter is active.
+  #define IGU_REG_PROD_UPD_COUNTER_CTL_PROD_UPD_COUNTER_SB_NUM_MASK_EN_SHIFT                                 9
+#define IGU_REG_PROD_UPD_COUNTER                                                                             0x180420UL //Access:RC   DataWidth:0x20   // Debug: count the number of PROD update requests which arrived on a specific SB, on the SB index in prod_upd_counter_sb_num.                   If the SB number in the configuration is all ones the counter counts for all the SB indexes.
+#define IGU_REG_CONS_UPD_COUNTER_CTL                                                                         0x180424UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define IGU_REG_CONS_UPD_COUNTER_CTL_CONS_UPD_COUNTER_SB_NUM                                               (0x1ff<<0) // Debug: SB index for the counter.
+  #define IGU_REG_CONS_UPD_COUNTER_CTL_CONS_UPD_COUNTER_SB_NUM_SHIFT                                         0
+  #define IGU_REG_CONS_UPD_COUNTER_CTL_CONS_UPD_COUNTER_SB_NUM_MASK_EN                                       (0x1<<9) // Debug: if set th counter is active.
+  #define IGU_REG_CONS_UPD_COUNTER_CTL_CONS_UPD_COUNTER_SB_NUM_MASK_EN_SHIFT                                 9
+#define IGU_REG_CONS_UPD_COUNTER                                                                             0x180428UL //Access:RC   DataWidth:0x20   // Debug: count tnumber of CONS update requests which arrived on a specific SB, on the SB index in cons_upd_counter_sb_num. If the SB number in the configuration is all ones the counter counts for all the SB indexes.
+#define IGU_REG_STATISTIC_NUM_OF_INTA_ASSERTED                                                               0x18042cUL //Access:RW   DataWidth:0x14   // Number of interrupt assertion for the PF.
+#define IGU_REG_RATE_LIMITER_STATISTICS                                                                      0x180600UL //Access:RW   DataWidth:0x14   // IPS statistics - number of messages sent for each group.
+#define IGU_REG_RATE_LIMITER_STATISTICS_SIZE                                                                 64
+#define IGU_REG_PF_CONFIGURATION                                                                             0x180800UL //Access:RW   DataWidth:0x6    // b0 - function enable; b1 - MSI/MSIX enable; b2 - INT enable; b3 - attention enable; b4 - single ISR mode enable; b5 - simd all ones mode - If clear (reset value):If the result of SB_before_mask & MASK is 0xFFFF_FFFF then the read result will be 0x7FFF_FFFF and the mask will be also 0x7FFF_FFFF. Therefore the interrupt is not de-asserted (the MSB SB is asserted and unmasked). And on the next read from SIMD with mask the result will be 0x8000_0000 and only now the interrupt will be de-asserted. If set: If the result of SB_before_mask & MASK is 0xFFFF_FFFF then the read result will be 0x7FFF_FFFF but the mask will be 0xFFFF_FFFF. Therefore the interrupt is de-asserted. And on the next read from SIMD with mask the result will be 0x0.
+#define IGU_REG_VF_CONFIGURATION                                                                             0x180804UL //Access:RW   DataWidth:0x9    // d0 - function enable; d1 - MSI/MSIX enable; d3:d2 reserved; d4 - single ISR mode enable; d8:d5 parent PF (BB supports only 0-7 PF).
+#define IGU_REG_MESSAGE_FIELDS                                                                               0x180808UL //Access:RW   DataWidth:0x1c   // Multi Field Register.
+  #define IGU_REG_MESSAGE_FIELDS_MSI_MSIX_VQID                                                               (0x1f<<0) // VQID for MSI and MSIX messages.
+  #define IGU_REG_MESSAGE_FIELDS_MSI_MSIX_VQID_SHIFT                                                         0
+  #define IGU_REG_MESSAGE_FIELDS_MSI_MSIX_ATC                                                                (0x7<<5) // ATC for MSI and MSIX messages.
+  #define IGU_REG_MESSAGE_FIELDS_MSI_MSIX_ATC_SHIFT                                                          5
+  #define IGU_REG_MESSAGE_FIELDS_MSI_MSIX_RO                                                                 (0x1<<8) // RO for MSI and MSIX messages.
+  #define IGU_REG_MESSAGE_FIELDS_MSI_MSIX_RO_SHIFT                                                           8
+  #define IGU_REG_MESSAGE_FIELDS_MSI_MSIX_NS                                                                 (0x1<<9) // NS for MSI and MSIX messages.
+  #define IGU_REG_MESSAGE_FIELDS_MSI_MSIX_NS_SHIFT                                                           9
+  #define IGU_REG_MESSAGE_FIELDS_MSIX_WRITE_DONE_TYPE                                                        (0x1<<10) // Write done type for MSI and MSIX message.
+  #define IGU_REG_MESSAGE_FIELDS_MSIX_WRITE_DONE_TYPE_SHIFT                                                  10
+  #define IGU_REG_MESSAGE_FIELDS_RESEVED                                                                     (0xf<<11) // Reserved.
+  #define IGU_REG_MESSAGE_FIELDS_RESEVED_SHIFT                                                               11
+  #define IGU_REG_MESSAGE_FIELDS_ATTN_VQID                                                                   (0x1f<<15) // VQID for attention messages.
+  #define IGU_REG_MESSAGE_FIELDS_ATTN_VQID_SHIFT                                                             15
+  #define IGU_REG_MESSAGE_FIELDS_ATTN_ATC                                                                    (0x7<<20) // ATC for attention messages.
+  #define IGU_REG_MESSAGE_FIELDS_ATTN_ATC_SHIFT                                                              20
+  #define IGU_REG_MESSAGE_FIELDS_ATTN_RO                                                                     (0x1<<23) // RO for attention messages.
+  #define IGU_REG_MESSAGE_FIELDS_ATTN_RO_SHIFT                                                               23
+  #define IGU_REG_MESSAGE_FIELDS_ATTN_NS                                                                     (0x1<<24) // NS for attention messages.
+  #define IGU_REG_MESSAGE_FIELDS_ATTN_NS_SHIFT                                                               24
+  #define IGU_REG_MESSAGE_FIELDS_ATTN_WRITE_DONE_TYPE                                                        (0x1<<25) // Write done type for attention message.
+  #define IGU_REG_MESSAGE_FIELDS_ATTN_WRITE_DONE_TYPE_SHIFT                                                  25
+  #define IGU_REG_MESSAGE_FIELDS_ENDIANITY_MODE                                                              (0x3<<26) // Endianity mode in MSI/MSIX and attention message.
+  #define IGU_REG_MESSAGE_FIELDS_ENDIANITY_MODE_SHIFT                                                        26
+#define IGU_REG_PCI_PF_MSI_EN_BB                                                                             0x18080cUL //Access:RW   DataWidth:0x1    // PF MSI enable status. Shadow of PCI config register.
+#define IGU_REG_PCI_PF_MSIX_EN_BB                                                                            0x180810UL //Access:RW   DataWidth:0x1    // PF MSIX enable status. Shadow of PCI config register.
+#define IGU_REG_PCI_PF_MSIX_FUNC_MASK_BB                                                                     0x180814UL //Access:RW   DataWidth:0x1    // PF MSIX function mask status. Shadow of PCI config register. 0 - unmasked; 1 - masked.
+#define IGU_REG_PCI_VF_MSIX_EN_BB                                                                            0x180818UL //Access:RW   DataWidth:0x1    // VF MSIX enable status. Shadow of PCI config register.
+#define IGU_REG_PCI_VF_MSIX_FUNC_MASK_BB                                                                     0x18081cUL //Access:RW   DataWidth:0x1    // VF MSIX function mask status. Shadow of PCI config register. 0 - unmasked; 1 - masked.
+#define IGU_REG_ATTN_MSG_ADDR_L                                                                              0x180820UL //Access:RW   DataWidth:0x20   // For attention message: Attention bit destination address 32 LSB. Two Lsbit must be zero.
+#define IGU_REG_ATTN_MSG_ADDR_H                                                                              0x180824UL //Access:RW   DataWidth:0x20   // For attention message: Attention bit destination address 32 MSB.
+#define IGU_REG_ATTENTION_BIT_STATUS_INDEX                                                                   0x180828UL //Access:RW   DataWidth:0x10   // Value of attention bit status index (posted toward the driver as attention bit status index). This is the same value as in the attention message.
+#define IGU_REG_LEADING_EDGE_LATCH                                                                           0x18082cUL //Access:RW   DataWidth:0x20   // Attention signals leading edge. attn bit condition monitoring; each bit that is set will lock a change from 0 to 1 in the corresponding attention signals that comes from the AEU.
+#define IGU_REG_TRAILING_EDGE_LATCH                                                                          0x180830UL //Access:RW   DataWidth:0x20   // Attention signals trailing edge. attn bit condition monitoring; each bit that is set will lock a change from 1 to 0 in the corresponding attention signals that comes from the AEU.
+#define IGU_REG_ATTENTION_BITS                                                                               0x180834UL //Access:RW   DataWidth:0x20   // 32 bit register with the latched attention values. These are the same bits as in the attention message.
+#define IGU_REG_ATTENTION_ACK_BITS                                                                           0x180838UL //Access:RW   DataWidth:0x20   // 32 bit register with the attention ACK values.These are the same bits as in the attention message.
+#define IGU_REG_ATTENTION_ENABLE                                                                             0x18083cUL //Access:RW   DataWidth:0xc    // Attention enable. Each PF attention vector is 12 bit. If the bit is set to 1, the corresponding bit in the attention vector is enabled. If the bit is set to 0, the corresponding bit in the attention vector is disabled.
+#define IGU_REG_COMMAND_REG_32LSB_DATA                                                                       0x180840UL //Access:RW   DataWidth:0x20   // If the last command sent to the command_reg_ctrl was a read command, this register holds the 32LSB read value. If address is PBA: 32LSB of PBA register (one in each bit means PBA message wasnt sent due to mask). If address = SIMD with mask 64b/32LSB: 32 LSB of the during interrupt register (one in each bit means the appropriate SB is asserted. Every bit that is set will be masked in the mask bit register). If address = SIMD with mask 32MSB: this register will return zero. If address = SIMD without mask 64b: 32 LSB of the during interrupt register (one in each bit means the appropriate SB is asserted). If the command sent to the command_reg_ctrl is a write command the data in this register is used as follows:  If address = interrupt acknowledge register or producer update: same as Consumer & Producer update command.  If address = attention update: Attention ack new value = command_reg_32lsb_data. If address = attention set: Attention ack new value = attention ack old value | command_reg_32lsb_data. If address = attention clear: Attention ack new value = attention ack old value  & command_reg_32lsb_data.
+#define IGU_REG_COMMAND_REG_32MSB_DATA                                                                       0x180844UL //Access:RW   DataWidth:0x20   // Read only register. If the last command sent to the command_reg_ctrl was a read command, this register holds the 32MSB read value. If address is PBA: 32 MSB of PBA register (one in each bit means PBA message wasnt sent due to mask).  If address = SIMD with mask 64b/32MSB: 32 MSB of the during interrupt register (one in each bit means the appropriate SB is asserted. Every bit that is set will be masked in the mask bit register). If address = SIMD with mask 32LSB: this register will return zero.  If address = SIMD without mask 64b: 32 MSB of the during interrupt register (one in each bit means the appropriate SB is asserted).
+#define IGU_REG_COMMAND_REG_CTRL                                                                             0x180848UL //Access:W    DataWidth:0x20   // [15:0] - function number: opaque fid. [28:16] - PXP BAR address; [30:29] - Reserved; [31] command type - 0-read; 1-wr. When writing to this register the command will be executed. On write command the 32 LSB command should be written first (to the command_reg_32lsb_data register) and only then this register. PXP BAR address field: same as IGU BAR mapping. The following addresses are write only: interrupt ack register; producer update; Attention bits update register; Attention bits set register; Attention bits clear register. The following addresses are read only: PBA; SIMD with mask 64b; SIMD with mask 32 LSB; SIMD with mask 32 MSB; SIMD without mask 64b. The read data is copied to command_reg_32lsb_data and command_reg_32msb_data registers. On read from reserved addresses the read data will be 0.
+#define IGU_REG_STATISTIC_EN                                                                                 0x18084cUL //Access:RW   DataWidth:0x1    // Enable to collect data in the statistic_num_vf_msg_sent memory and statistic_num_pf_msg_sent memory.
+#define IGU_REG_MSI_MEMORY_BB                                                                                0x180850UL //Access:RW   DataWidth:0x20   // Address 0 - MSI address low (two Lsbit are zero). Address 1 - MSI address high. Address 2 - [15:0] - MSI data; [18:16] MME; [31:19] Reserved.
+#define IGU_REG_MSI_MEMORY_SIZE                                                                              3
+#define IGU_REG_CAM_PARITY_SCRUBBING                                                                         0x180860UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define IGU_REG_CAM_PARITY_SCRUBBING_CAM_SCRUB_HIT_EN                                                      (0x1<<0) // IF = 1, hit scrubbing is enabled.                              When hit scrubbing is enabled, the match address of the hit response is used to perform a two-cycle                              read at the CAM hit location and (as usual) parity is checked during this read.
+  #define IGU_REG_CAM_PARITY_SCRUBBING_CAM_SCRUB_HIT_EN_SHIFT                                                0
+  #define IGU_REG_CAM_PARITY_SCRUBBING_CAM_SCRUB_MISS_EN                                                     (0x1<<1) // IF = 1, miss scrubbing is enabled.                              When miss scrubbing is enabled, each time there is a search that results in a miss, a read of                               the entire CAM will be started (or re-started). This will end when the entire CAM has been read.                              Parity is checked during this read.
+  #define IGU_REG_CAM_PARITY_SCRUBBING_CAM_SCRUB_MISS_EN_SHIFT                                               1
+#define IGU_REG_RATE_LIMITER_STATISTICS_EN                                                                   0x180864UL //Access:RW   DataWidth:0x1    // Enable the RL statistic. 0 - disabled; 1 - enabled.
+#define IGU_REG_ECO_RESERVED                                                                                 0x180868UL //Access:RW   DataWidth:0x8    // Reserved for ECO if needed.
+#define IGU_REG_PENDING_BITS_STATUS                                                                          0x180880UL //Access:R    DataWidth:0x20   // Each bit represents the pending bits status for that SB. 0 = no pending; 1 = pending. Pendings means interrupt was asserted and write done was not received. The array size is 16 rows of 32 bits each (16 * 32bits = 512 SBs).
+#define IGU_REG_PENDING_BITS_STATUS_SIZE_BB                                                                  9
+#define IGU_REG_PENDING_BITS_STATUS_SIZE_K2                                                                  12
+#define IGU_REG_PENDING_BITS_STATUS_SIZE_E5                                                                  16
+#define IGU_REG_WRITE_DONE_PENDING                                                                           0x180900UL //Access:R    DataWidth:0x20   // Each bit represent write done pending bits status for that SB (MSI/MSIX message was sent and write done was not received yet). 0 = clear; 1 = set. The array size is 16 rows of 32 bits each (16 * 32bits = 512 SBs).
+#define IGU_REG_WRITE_DONE_PENDING_SIZE_BB                                                                   9
+#define IGU_REG_WRITE_DONE_PENDING_SIZE_K2                                                                   12
+#define IGU_REG_WRITE_DONE_PENDING_SIZE_E5                                                                   16
+#define IGU_REG_CLEANUP_STATUS_0                                                                             0x180980UL //Access:R    DataWidth:0x20   // Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in these registers are set and clear via the producer and consumer command. The array size is 16 rows of 32 bits each (16 * 32bits = 512 SBs).
+#define IGU_REG_CLEANUP_STATUS_0_SIZE_BB                                                                     9
+#define IGU_REG_CLEANUP_STATUS_0_SIZE_K2                                                                     12
+#define IGU_REG_CLEANUP_STATUS_0_SIZE_E5                                                                     16
+#define IGU_REG_CLEANUP_STATUS_1                                                                             0x180a00UL //Access:R    DataWidth:0x20   // Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this registers are set and clear via the producer and consumer command. The array size is 16 rows of 32 bits each (16 * 32bits = 512 SBs).
+#define IGU_REG_CLEANUP_STATUS_1_SIZE_BB                                                                     9
+#define IGU_REG_CLEANUP_STATUS_1_SIZE_K2                                                                     12
+#define IGU_REG_CLEANUP_STATUS_1_SIZE_E5                                                                     16
+#define IGU_REG_CLEANUP_STATUS_2                                                                             0x180a80UL //Access:R    DataWidth:0x20   // Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this registers are set and clear via the producer and consumer command. The array size is 16 rows of 32 bits each (16 * 32bits = 512 SBs).
+#define IGU_REG_CLEANUP_STATUS_2_SIZE_BB                                                                     9
+#define IGU_REG_CLEANUP_STATUS_2_SIZE_K2                                                                     12
+#define IGU_REG_CLEANUP_STATUS_2_SIZE_E5                                                                     16
+#define IGU_REG_CLEANUP_STATUS_3                                                                             0x180b00UL //Access:R    DataWidth:0x20   // Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this registers are set and clear via the producer and consumer command. The array size is 16 rows of 32 bits each (16 * 32bits = 512 SBs).
+#define IGU_REG_CLEANUP_STATUS_3_SIZE_BB                                                                     9
+#define IGU_REG_CLEANUP_STATUS_3_SIZE_K2                                                                     12
+#define IGU_REG_CLEANUP_STATUS_3_SIZE_E5                                                                     16
+#define IGU_REG_CLEANUP_STATUS_4                                                                             0x180b80UL //Access:R    DataWidth:0x20   // Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this registers are set and clear via the producer and consumer command. The array size is 16 rows of 32 bits each (16 * 32bits = 512 SBs).
+#define IGU_REG_CLEANUP_STATUS_4_SIZE_BB                                                                     9
+#define IGU_REG_CLEANUP_STATUS_4_SIZE_K2                                                                     12
+#define IGU_REG_CLEANUP_STATUS_4_SIZE_E5                                                                     16
+#define IGU_REG_VF_WITH_MORE_16SB_0                                                                          0x180c00UL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_1                                                                          0x180c04UL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_2                                                                          0x180c08UL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_3                                                                          0x180c0cUL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_4                                                                          0x180c10UL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_5                                                                          0x180c14UL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_6                                                                          0x180c18UL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_7                                                                          0x180c1cUL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_8                                                                          0x180c20UL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_9                                                                          0x180c24UL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_10                                                                         0x180c28UL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_11                                                                         0x180c2cUL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_12                                                                         0x180c30UL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_13                                                                         0x180c34UL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_14                                                                         0x180c38UL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_15                                                                         0x180c3cUL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_16_K2_E5                                                                   0x180c40UL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_17_K2_E5                                                                   0x180c44UL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_18_K2_E5                                                                   0x180c48UL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_19_K2_E5                                                                   0x180c4cUL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_20_K2_E5                                                                   0x180c50UL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_21_E5                                                                      0x180c54UL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_22_E5                                                                      0x180c58UL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_23_E5                                                                      0x180c5cUL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_24_E5                                                                      0x180c60UL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_25_E5                                                                      0x180c64UL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_26_E5                                                                      0x180c68UL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_27_E5                                                                      0x180c6cUL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_28_E5                                                                      0x180c70UL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_VF_WITH_MORE_16SB_29_E5                                                                      0x180c74UL //Access:RW   DataWidth:0x9    // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
+#define IGU_REG_MSIX_CLEANUP_CMD                                                                             0x180c80UL //Access:W    DataWidth:0x9    // Writing the absolute SB index to the register will clear the appropriate vector in the MSIX table (write zero to all fields except the mask bit that is set).
+#define IGU_REG_INT_BEFORE_MASK_STS_PF                                                                       0x180ca0UL //Access:RW   DataWidth:0x20   // SB interrupt before mask. 0 - prod equal cons. 1 - prod not equal cons or last command for this SB was prod update. The bits order is according to the vector number of each SB in that function. Only 129b available.
+#define IGU_REG_INT_BEFORE_MASK_STS_PF_SIZE                                                                  5
+#define IGU_REG_INT_BEFORE_MASK_STS_VF_LSB                                                                   0x180cc0UL //Access:RW   DataWidth:0x20   // SB interrupt before mask. 0 - prod equal cons. 1 - prod not equal cons or last command for this SB was prod update. The bits order is according to the vector number of each SB in that function. Bits 31:16 are available for functions that are configured in vf_with_more_16sb only.
+#define IGU_REG_INT_BEFORE_MASK_STS_VF_MSB                                                                   0x180cc4UL //Access:RW   DataWidth:0x20   // SB interrupt before mask. 0 - prod equal cons. 1 - prod not equal cons or last command for this SB was prod update. The bits order is according to the vector number of each SB in that function. Available for functions that are configured in vf_with_more_16sb only.
+#define IGU_REG_INT_MASK_STS_PF                                                                              0x180ce0UL //Access:RW   DataWidth:0x20   // SB interrupt mask. 0 - unmasked. 1 - masked. The bits order is according to the vector number of each SB in that function. Only 129b available.
+#define IGU_REG_INT_MASK_STS_PF_SIZE                                                                         5
+#define IGU_REG_INT_MASK_STS_VF_LSB                                                                          0x180d00UL //Access:RW   DataWidth:0x20   // SB interrupt mask. 0 - unmasked. 1 - masked. The bits order is according to the vector number of each SB in that function. Bits 31:16 are available for functions that are configured in vf_with_more_16sb only.
+#define IGU_REG_INT_MASK_STS_VF_MSB                                                                          0x180d04UL //Access:RW   DataWidth:0x20   // SB interrupt mask. 0 - unmasked. 1 - masked. The bits order is according to the vector number of each SB in that function. Availble for functions that are configured in vf_with_more_16sb only.
+#define IGU_REG_PBA_STS_PF                                                                                   0x180d20UL //Access:RW   DataWidth:0x20   // PBA register. 0 - PBA clear, 1 - PBA set - the appropriate MSIX message was not set due to mask bit (function or vector). The bits order is according to the vector number of each SB in that function. Only 129b availble.
+#define IGU_REG_PBA_STS_PF_SIZE                                                                              5
+#define IGU_REG_PBA_STS_VF_LSB                                                                               0x180d40UL //Access:RW   DataWidth:0x20   // PBA register. 0 - PBA clear, 1 - PBA set - the appropriate MSIX message was not set due to mask bit (function or vector). The bits order is according to the vector number of each SB in that function. Bits 31:16 are available for functions that are configured in vf_with_more_16sb only.
+#define IGU_REG_PBA_STS_VF_MSB                                                                               0x180d44UL //Access:RW   DataWidth:0x20   // PBA register. 0 - PBA clear, 1 - PBA set - the appropriate MSIX message was not set due to mask bit (function or vector). The bits order is according to the vector number of each SB in that function. Availble for functions that are configured in vf_with_more_16sb only.
+#define IGU_REG_GROUP_RL_VARIABLE0                                                                           0x180e00UL //Access:RW   DataWidth:0x18   // [9:0] upper_bound - sets the max value that the rate_counter can reach; [19:10] tick_interval - define the max interrupt rate for the group; [23:20] timer mask value - define the negative value that the tick_value receives when receiving a timer mask command. 0 = 0; 1 = 1; 2 = 2; 3 = 4; 4 = 8; 5 = 16; 6 = 24; 7 = 32; 8 = 48; 9 = 64; 10 = 96; 11 = 128; 12 = 256; 13 = 512; 14 = 750; 15 = 1000.
+#define IGU_REG_GROUP_RL_VARIABLE0_SIZE                                                                      64
+#define IGU_REG_GROUP_RL_VARIABLE1                                                                           0x181000UL //Access:RW   DataWidth:0x15   // [0:9] tick_value - receives the tick_interval value when reaching zero; or when writing to the tick_interval. The tick value is decreased every tick. [20:10] rate_counter - incremented by a one when tick_value reaches zero and decremented whenever a message from that group was sent or when a timer mask command arrived. When rate counter is zero/negative - no messages will be sent on that group. When the positive value reaches upper_bound it will not continue incrementing. Negative value is represented by 2s complement value.
+#define IGU_REG_GROUP_RL_VARIABLE1_SIZE                                                                      64
+#define IGU_REG_GLOBAL_RATE_LIMITER_VARI0                                                                    0x181200UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define IGU_REG_GLOBAL_RATE_LIMITER_VARI0_GLOBAL_RATE_UPPER_BOUND                                          (0x3ff<<0) // Upper bound value of the global rate limiter. Sets the max value that the rate_counter can reach.
+  #define IGU_REG_GLOBAL_RATE_LIMITER_VARI0_GLOBAL_RATE_UPPER_BOUND_SHIFT                                    0
+  #define IGU_REG_GLOBAL_RATE_LIMITER_VARI0_GLOBAL_RATE_TICK_INTERVAL                                        (0x3ff<<10) // Tick interval of the global rate limiter. Define the max interrupt rate for the group.
+  #define IGU_REG_GLOBAL_RATE_LIMITER_VARI0_GLOBAL_RATE_TICK_INTERVAL_SHIFT                                  10
+  #define IGU_REG_GLOBAL_RATE_LIMITER_VARI0_GLOBAL_RATE_INC_VALUE                                            (0xf<<20) // The value that the global rate will be increased on every interval. Zero is not a valid value.
+  #define IGU_REG_GLOBAL_RATE_LIMITER_VARI0_GLOBAL_RATE_INC_VALUE_SHIFT                                      20
+#define IGU_REG_GLOBAL_RATE_TICK_VALUE                                                                       0x181204UL //Access:R    DataWidth:0xa    // This field receives the tick_interval value when reaching zero. The tick value is decreased by one on every tick.
+#define IGU_REG_GLOBAL_RATE_TICK_RATE_COUNTER                                                                0x181208UL //Access:RW   DataWidth:0xb    // Rate counter - incremented by one when Tick_value reaches zero and decremented whenever a message from that group was sent. When rate counter is zero/negative - no messages will be sent on that group. Negative value is represented by 2s complement value. When the positive value reaches Upper_bound it will not continue incrementing.
+#define IGU_REG_VF_FUNCTIONAL_CLEANUP                                                                        0x18120cUL //Access:W    DataWidth:0x1    // Writing 1 to this register will clear the VF statistics.
+#define IGU_REG_PF_FUNCTIONAL_CLEANUP                                                                        0x181210UL //Access:W    DataWidth:0x1    // Writing 1 to this register will clear the PF statistics and clean also attn bit, attn ack and attn index registers.
+#define IGU_REG_CLK25_COUNTER_SENSITIVITY                                                                    0x181214UL //Access:RW   DataWidth:0x10   // Number of clock 25 cycles that generate a tick in the IPS mechanism. The number of cycles multiply by clock 25 cycle time should give 1 usec. In case this configuration should be changed, the change flow is done in several phases of writes while each write is as close as possible to the required configuration and it should keep one of the bits that are set in the previous write (or in the reset value) as set. Each write should be followed by a read. For example to change the reset value of (binary) 11001 (1usec) to (binary) 1100100 (4usec): write (binary) 1101100, read, write (binary) 1100100.
+#define IGU_REG_ATTN_TPH                                                                                     0x181218UL //Access:RW   DataWidth:0x10   // Tph field for attention message. Bits 8:0 - steering tag; bits 12:9 - reserved; bits 14:13 - st hint; bit 15 - tph valid.
+#define IGU_REG_GROUP_RL_EN_0                                                                                0x18121cUL //Access:R    DataWidth:0x20   // Rate Limiter group enable status bit for groups 0-31. For each bit: 0 - the rate limiter of the group is disabled. 1 - the rate limiter of the group is enabled.
+#define IGU_REG_GROUP_RL_EN_1                                                                                0x181220UL //Access:R    DataWidth:0x20   // Rate Limiter group enable status bit for groups 32-63. For each bit: 0 - the rate limiter of the group is disabled. 1 - the rate limiter of the group is enabled.
+#define IGU_REG_GROUP_RL_CREDIT_0                                                                            0x181224UL //Access:R    DataWidth:0x20   // Rate Limiter group credit status bit for groups 0-31. For each bit: 0 - the group has no credit. 1 - the group has credit.
+#define IGU_REG_GROUP_RL_CREDIT_1                                                                            0x181228UL //Access:R    DataWidth:0x20   // Rate Limiter group credit status bit for groups 32-63. For each bit: 0 - the group has no credit. 1 - the group has credit.
+#define IGU_REG_GROUP_RL_PENDING_0                                                                           0x18122cUL //Access:R    DataWidth:0x20   // Rate Limiter group pending status bit for groups 0-31. For each bit: 0 - there are no pending SB in that group. 1 - there are pending SB in that group.
+#define IGU_REG_GROUP_RL_PENDING_1                                                                           0x181230UL //Access:R    DataWidth:0x20   // Rate Limiter group pending status bit for groups 32-63. For each bit: 0 - there are no pending SB in that group. 1 - there are pending SB in that group.
+#define IGU_REG_ATTENTION_SIGNAL_P0_STATUS                                                                   0x181500UL //Access:R    DataWidth:0xc    // Debug: attention signal status. Reflects the current value of the attention signals from the MISC-AEU port0.
+#define IGU_REG_ATTENTION_SIGNAL_P1_STATUS                                                                   0x181504UL //Access:R    DataWidth:0xc    // Debug: attention signal status. Reflects the current value of the attention signals from the MISC-AEU port1.
+#define IGU_REG_ATTENTION_SIGNAL_P2_STATUS                                                                   0x181508UL //Access:R    DataWidth:0xc    // Debug: attention signal status. Reflects the current value of the attention signals from the MISC-AEU port2.
+#define IGU_REG_ATTENTION_SIGNAL_P3_STATUS                                                                   0x18150cUL //Access:R    DataWidth:0xc    // Debug: attention signal status. Reflects the current value of the attention signals from the MISC-AEU port3.
+#define IGU_REG_ATTN_MSG_PENDING                                                                             0x181510UL //Access:R    DataWidth:0x10   // Debug: messages that wait to be sent; but were not sent yet. One bit for each PFID.
+#define IGU_REG_ATTN_WRITE_DONE_PENDING                                                                      0x181514UL //Access:R    DataWidth:0x5    // Debug: [4] - attention write done message is pending (0-no pending; 1-pending). [3:0] = the PFID for the pending attention message. Pending means attention message was sent; but write done was not received.
+#define IGU_REG_COMMAND_DEBUG                                                                                0x181518UL //Access:RW   DataWidth:0x1    // Debug only: 0 - FIFO collects 64 first error messages; 1 - FIFO collects 64 last incoming command.
+#define IGU_REG_INTERRUPT_STATUS                                                                             0x18151cUL //Access:R    DataWidth:0x10   // Debug: Interrupt status (active high). BB: PF0 to PF7.
+#define IGU_REG_ERROR_HANDLING_MEMORY                                                                        0x181520UL //Access:WB_R DataWidth:0x41   // Do not read from this memory if error_handling_data_valid register is zero. The data is collected in according to the command_debug value. If command_debug is clear it holds the first 64 error commands (commands that were dropped), else it stores the last 64 commands according to debug_record_mask registers: If the mask _*_en is clear it will collect all the data regardless of the mask_* value. if it is set it will collect the data that match to the value in the mask_* register. Masking can be done according to: debug_record_mask_source_idx, debug_record_mask_min_sb_idx, debug_record_mask_max_sb_idx, debug_record_mask_fid_num, debug_record_mask_fid_exclude, debug_record_mask_cmd_type_idx. The read data encoding is as follows: [8:0] - fid ([8] - if set - PF; else VF, [7:0] - FID). [12:9] - source (values 0-7 according to PXP sources, 8 - CAU, 9 - ATTN, 10 - GRC command register). [16:13] - error type (value: 0 - no error, 1 - length error, 2 - function disabled, 3 - VF sent command to attnetion address, 4 - host sent prod update command, 5 - read of during interrupt register while in MIMD mode, 6 - access to PXP BAR reserved address, 7 - producer update command to attention index, 9 - SB index not valid, 10 - SB relative index and FID not found, 11 - FID not match, 12 - command with error flag aserted (PCI error or CAU discard) 13 - VF sent cleanup and RF cleanup is disabled, 14 - cleanup command on type bigger than 4). [31:17] - Command address (15 LSBits). [32:32] - Command write or read. 0 - read, 1 - write. [64:33] - 32 LSB Wr data. In case of CAU command the mapping is: [56:33] - CAU command [23:0], [63:57] - reserved, [64] - CAU command [42] (CMD Type). In case of ATTENTION PRODUCER UPDATE command the mapping is: [56:33] - producer value, [64:57] - reserved.
+#define IGU_REG_ERROR_HANDLING_MEMORY_SIZE                                                                   4
+#define IGU_REG_ERROR_HANDLING_DATA_VALID                                                                    0x181530UL //Access:R    DataWidth:0x1    // Data available for error memory. If this bit is clear do not read from error_handling_memory.
+#define IGU_REG_SILENT_DROP                                                                                  0x181534UL //Access:RW   DataWidth:0x10   // Number of command that were dropped.
+#define IGU_REG_MAPPING_FSM                                                                                  0x181538UL //Access:R    DataWidth:0x4    // Debug: mapping_fsm.
+#define IGU_REG_SB_CTRL_FSM                                                                                  0x18153cUL //Access:R    DataWidth:0x4    // Debug: sb_ctrl_fsm.
+#define IGU_REG_INT_HANDLE_FSM                                                                               0x181540UL //Access:R    DataWidth:0x4    // Debug: int_handle_fsm.
+#define IGU_REG_ATTN_FSM                                                                                     0x181544UL //Access:R    DataWidth:0x4    // Debug: attn_fsm.
+#define IGU_REG_PBA_FSM                                                                                      0x181548UL //Access:R    DataWidth:0x4    // Debug: pba_fsm.
+#define IGU_REG_MSIX_MSG_BUILDER_FSM                                                                         0x18154cUL //Access:R    DataWidth:0x5    // Debug: msix_msg_builder_fsm.
+#define IGU_REG_MSIX_MEM_FSM                                                                                 0x181550UL //Access:R    DataWidth:0x3    // Debug: msix_mem_fsm.
+#define IGU_REG_CTRL_FSM                                                                                     0x181554UL //Access:R    DataWidth:0x5    // Debug: ctrl_fsm.
+#define IGU_REG_PXP_ARB_FSM                                                                                  0x181558UL //Access:R    DataWidth:0x3    // Debug: pxp_arb_fsm.
+#define IGU_REG_DEBUG_RECORD_MASK_MIN_SB                                                                     0x18155cUL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define IGU_REG_DEBUG_RECORD_MASK_MIN_SB_IDX                                                               (0x1ff<<0) // Debug: minimun SB index for the debug.
+  #define IGU_REG_DEBUG_RECORD_MASK_MIN_SB_IDX_SHIFT                                                         0
+  #define IGU_REG_DEBUG_RECORD_MASK_MIN_SB_EN                                                                (0x1<<9) // Debug: if set the debug information is collected for SB index equal or above debug_record_mask_min_sb_idx. Applicable for PROD/CONS UPD, CLEANUP, and MSIX RD/WR commands. This field is ignored for error cases and for all other commands.
+  #define IGU_REG_DEBUG_RECORD_MASK_MIN_SB_EN_SHIFT                                                          9
+#define IGU_REG_DEBUG_RECORD_MASK_MAX_SB                                                                     0x181560UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define IGU_REG_DEBUG_RECORD_MASK_MAX_SB_IDX                                                               (0x1ff<<0) // Debug: maximum SB index for the debug.
+  #define IGU_REG_DEBUG_RECORD_MASK_MAX_SB_IDX_SHIFT                                                         0
+  #define IGU_REG_DEBUG_RECORD_MASK_MAX_SB_EN                                                                (0x1<<9) // Debug: if set the debug information is collected for SB index equal or below debug_record_mask_max_sb_idx. Applicable for PROD/CONS UPD, CLEANUP, and MSIX RD/WR commands. This field is ignored for error cases and for all other commands.
+  #define IGU_REG_DEBUG_RECORD_MASK_MAX_SB_EN_SHIFT                                                          9
+#define IGU_REG_DEBUG_RECORD_MASK_FID                                                                        0x181564UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define IGU_REG_DEBUG_RECORD_MASK_FID_NUM                                                                  (0x1ff<<0) // Debug: FID number for debug . if VF - [8] = 0; [7:0] = VF number; if PF - [8] = 1; [7:4] = 0; [3:0] = PF number.
+  #define IGU_REG_DEBUG_RECORD_MASK_FID_NUM_SHIFT                                                            0
+  #define IGU_REG_DEBUG_RECORD_MASK_FID_EN                                                                   (0x1<<9) // Debug: if set the debug information is collected for FID specified in debug_record_mask_fid_num according to debug_record_mask_fid_exclude field.
+  #define IGU_REG_DEBUG_RECORD_MASK_FID_EN_SHIFT                                                             9
+  #define IGU_REG_DEBUG_RECORD_MASK_FID_EXCLUDE                                                              (0x1<<10) // Debug: if clear the debug information is collected for FID equal to debug_record_mask_fid_num. if set the debug information is collected for FID not equal to debug_record_mask_fid_num.
+  #define IGU_REG_DEBUG_RECORD_MASK_FID_EXCLUDE_SHIFT                                                        10
+#define IGU_REG_DEBUG_RECORD_MASK_SOURCE                                                                     0x181568UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define IGU_REG_DEBUG_RECORD_MASK_SOURCE_IDX                                                               (0xf<<0) // Debug: source index for the debug. 0=TSTORM; 1=MSTORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=PSTORM; 6=PCIe; 7=other (PBF/NIG/QM) 8 = CAU; 9 = internal (attention producer update); 10 = GRC.
+  #define IGU_REG_DEBUG_RECORD_MASK_SOURCE_IDX_SHIFT                                                         0
+  #define IGU_REG_DEBUG_RECORD_MASK_SOURCE_EN                                                                (0x1<<4) // Debug: if set the debug information is collected for source equal to debug_record_mask_source_idx.
+  #define IGU_REG_DEBUG_RECORD_MASK_SOURCE_EN_SHIFT                                                          4
+#define IGU_REG_DEBUG_RECORD_MASK_CMD_TYPE                                                                   0x18156cUL //Access:RW   DataWidth:0x7    // Multi Field Register.
+  #define IGU_REG_DEBUG_RECORD_MASK_CMD_TYPE_IDX                                                             (0x3f<<0) // Debug: command type for the debug. Selects the command types to be collected. The fields: Bit [0] - MSIX read/write; Bit [1] - PBA read/write; Bit [2] - Producer update (or cleanup command through producer address space) read/write; Bit [3] - Interrupt acknowledgment - Consumer update (or cleanup command through consumer address space) read/write; Bit [4] - Attn command read/write; Bit [5] - Read during interrupt register read/write.
+  #define IGU_REG_DEBUG_RECORD_MASK_CMD_TYPE_IDX_SHIFT                                                       0
+  #define IGU_REG_DEBUG_RECORD_MASK_CMD_TYPE_EN                                                              (0x1<<6) // Debug: if set the debug information is collected for the marked commands only according to debug_record_mask_cmd_type_idx.
+  #define IGU_REG_DEBUG_RECORD_MASK_CMD_TYPE_EN_SHIFT                                                        6
+#define IGU_REG_MISC_PORT_MODE                                                                               0x181570UL //Access:R    DataWidth:0x2    // The misc port mode signal value. 0 = SPPE; 1 = DPPE; 2 = QPPE; 3 = reserved.
+#define IGU_REG_CAU_DISCARD_STATUS                                                                           0x181574UL //Access:R    DataWidth:0x1    // The discard signal status from the CAU.
+#define IGU_REG_DBG_SELECT                                                                                   0x181578UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define IGU_REG_DBG_DWORD_ENABLE                                                                             0x18157cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define IGU_REG_DBG_SHIFT                                                                                    0x181580UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define IGU_REG_DBG_FORCE_VALID                                                                              0x181584UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define IGU_REG_DBG_FORCE_FRAME                                                                              0x181588UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define IGU_REG_DBG_OUT_DATA                                                                                 0x1815a0UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define IGU_REG_DBG_OUT_DATA_SIZE                                                                            8
+#define IGU_REG_DBG_OUT_VALID                                                                                0x1815c0UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define IGU_REG_DBG_OUT_FRAME                                                                                0x1815c4UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define IGU_REG_PRODUCER_MEMORY                                                                              0x182000UL //Access:RW   DataWidth:0x18   // Producers only. Address 0-511 match to the mapping memory. Address 512-227: PF 0-15 attention producer.
+#define IGU_REG_PRODUCER_MEMORY_SIZE_BB                                                                      296
+#define IGU_REG_PRODUCER_MEMORY_SIZE_K2                                                                      384
+#define IGU_REG_PRODUCER_MEMORY_SIZE_E5                                                                      528
+#define IGU_REG_CONSUMER_MEM                                                                                 0x183000UL //Access:RW   DataWidth:0x18   // Consumers only. Address 0-511 match to the mapping memory. Address 512-227: PF0-15 attention consumer.
+#define IGU_REG_CONSUMER_MEM_SIZE_BB                                                                         296
+#define IGU_REG_CONSUMER_MEM_SIZE_K2                                                                         384
+#define IGU_REG_CONSUMER_MEM_SIZE_E5                                                                         528
+#define IGU_REG_MAPPING_MEMORY                                                                               0x184000UL //Access:RW   DataWidth:0x18   // Mapping CAM. Fields: [0] - valid. [8:1] - vector number (0-128 for PF; 0-63 for VF). [17:9] - FID (if VF: [17] = 0; [16:9] = VF number (0-239); if PF: [17] = 1; [16:9] = PF number (0-15)).                           [23:18] - IPS group ID (0-63). Reset values (the CAM receives these values by writing one to bit zero in the reset_memories register: address 0-16 - PF 0 vectors 0-16; address 17-33 - PF 1 vectors 0-16; address 34-50 - PF 2 vectors 0-16; .. address 119-135 - PF 7 vectors 0-16; .. address 254-271 - PF 15 vectors 0-16; address 272 - VF 0 vector 0; address 137 - VF 1 vector 0; address 138 - VF 2 vector 0; .. address 511 - VF 239 vector 0. All the SBs are associated to group 0 in the IRL mechanism.
+#define IGU_REG_MAPPING_MEMORY_SIZE_BB                                                                       288
+#define IGU_REG_MAPPING_MEMORY_SIZE_K2                                                                       368
+#define IGU_REG_MAPPING_MEMORY_SIZE_E5                                                                       512
+#define IGU_REG_MSIX_MEMORY                                                                                  0x186000UL //Access:WB   DataWidth:0x61   // [63:0] - MSIX message address (bit [1:0] are always zero); [95:64] - MSIX message data; [96] - MSIX mask bit (0 - unmasked; 1 - masked). Reset value (after reset_memories was set) is: MSIX address = 0; MSIX data = 0; MSIX mask bit = 1.
+#define IGU_REG_MSIX_MEMORY_SIZE_BB                                                                          1152
+#define IGU_REG_MSIX_MEMORY_SIZE_K2                                                                          1472
+#define IGU_REG_MSIX_MEMORY_SIZE_E5                                                                          2048
+#define CAU_REG_INT_STS                                                                                      0x1c00d4UL //Access:R    DataWidth:0xb    // Multi Field Register.
+  #define CAU_REG_INT_STS_ADDRESS_ERROR                                                                      (0x1<<0) // Signals an unknown address to the rf module.
+  #define CAU_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                                0
+  #define CAU_REG_INT_STS_UNAUTHORIZED_PXP_RD_CMD                                                            (0x1<<1) // PXP read request arrived.
+  #define CAU_REG_INT_STS_UNAUTHORIZED_PXP_RD_CMD_SHIFT                                                      1
+  #define CAU_REG_INT_STS_UNAUTHORIZED_PXP_LENGTH_CMD                                                        (0x1<<2) // PXP write request without CQA and with length >1 arrived.
+  #define CAU_REG_INT_STS_UNAUTHORIZED_PXP_LENGTH_CMD_SHIFT                                                  2
+  #define CAU_REG_INT_STS_PXP_SB_ADDRESS_ERROR                                                               (0x1<<3) // SB index > CAU_NUM_SB or  SB index > CAU_NUM_PI/num_pi_per_sb. CAU_SB_NUM is 288 in BB and 368 in K2. CAU_PI_NUM is 3456 in BB and 4416 in K2
+  #define CAU_REG_INT_STS_PXP_SB_ADDRESS_ERROR_SHIFT                                                         3
+  #define CAU_REG_INT_STS_PXP_PI_NUMBER_ERROR                                                                (0x1<<4) // PI relative number > num_pi_per_sb.
+  #define CAU_REG_INT_STS_PXP_PI_NUMBER_ERROR_SHIFT                                                          4
+  #define CAU_REG_INT_STS_CLEANUP_REG_SB_IDX_ERROR                                                           (0x1<<5) // SB index > CAU_SB_NUM or  SB index > CAU_PI_NUM/num_pi_per_sb. CAU_SB_NUM is 288 in BB and 368 in K2. CAU_PI_NUM is 3456 in BB and 4416 in K2
+  #define CAU_REG_INT_STS_CLEANUP_REG_SB_IDX_ERROR_SHIFT                                                     5
+  #define CAU_REG_INT_STS_FSM_INVALID_LINE                                                                   (0x1<<6) // The FSM arrived to an invalid line.
+  #define CAU_REG_INT_STS_FSM_INVALID_LINE_SHIFT                                                             6
+  #define CAU_REG_INT_STS_CQE_FIFO_ERR                                                                       (0x1<<7) // Write to full  FIFO or read from empty  FIFO.
+  #define CAU_REG_INT_STS_CQE_FIFO_ERR_SHIFT                                                                 7
+  #define CAU_REG_INT_STS_IGU_WDATA_FIFO_ERR                                                                 (0x1<<8) // Write to full  FIFO or read from empty  FIFO.
+  #define CAU_REG_INT_STS_IGU_WDATA_FIFO_ERR_SHIFT                                                           8
+  #define CAU_REG_INT_STS_IGU_REQ_FIFO_ERR                                                                   (0x1<<9) // Write to full  FIFO or read from empty  FIFO.
+  #define CAU_REG_INT_STS_IGU_REQ_FIFO_ERR_SHIFT                                                             9
+  #define CAU_REG_INT_STS_IGU_CMD_FIFO_ERR                                                                   (0x1<<10) // Write to full  FIFO or read from empty  FIFO.
+  #define CAU_REG_INT_STS_IGU_CMD_FIFO_ERR_SHIFT                                                             10
+#define CAU_REG_INT_STS_CLR                                                                                  0x1c00d8UL //Access:RC   DataWidth:0xb    // Multi Field Register.
+  #define CAU_REG_INT_STS_CLR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define CAU_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                            0
+  #define CAU_REG_INT_STS_CLR_UNAUTHORIZED_PXP_RD_CMD                                                        (0x1<<1) // PXP read request arrived.
+  #define CAU_REG_INT_STS_CLR_UNAUTHORIZED_PXP_RD_CMD_SHIFT                                                  1
+  #define CAU_REG_INT_STS_CLR_UNAUTHORIZED_PXP_LENGTH_CMD                                                    (0x1<<2) // PXP write request without CQA and with length >1 arrived.
+  #define CAU_REG_INT_STS_CLR_UNAUTHORIZED_PXP_LENGTH_CMD_SHIFT                                              2
+  #define CAU_REG_INT_STS_CLR_PXP_SB_ADDRESS_ERROR                                                           (0x1<<3) // SB index > CAU_NUM_SB or  SB index > CAU_NUM_PI/num_pi_per_sb. CAU_SB_NUM is 288 in BB and 368 in K2. CAU_PI_NUM is 3456 in BB and 4416 in K2
+  #define CAU_REG_INT_STS_CLR_PXP_SB_ADDRESS_ERROR_SHIFT                                                     3
+  #define CAU_REG_INT_STS_CLR_PXP_PI_NUMBER_ERROR                                                            (0x1<<4) // PI relative number > num_pi_per_sb.
+  #define CAU_REG_INT_STS_CLR_PXP_PI_NUMBER_ERROR_SHIFT                                                      4
+  #define CAU_REG_INT_STS_CLR_CLEANUP_REG_SB_IDX_ERROR                                                       (0x1<<5) // SB index > CAU_SB_NUM or  SB index > CAU_PI_NUM/num_pi_per_sb. CAU_SB_NUM is 288 in BB and 368 in K2. CAU_PI_NUM is 3456 in BB and 4416 in K2
+  #define CAU_REG_INT_STS_CLR_CLEANUP_REG_SB_IDX_ERROR_SHIFT                                                 5
+  #define CAU_REG_INT_STS_CLR_FSM_INVALID_LINE                                                               (0x1<<6) // The FSM arrived to an invalid line.
+  #define CAU_REG_INT_STS_CLR_FSM_INVALID_LINE_SHIFT                                                         6
+  #define CAU_REG_INT_STS_CLR_CQE_FIFO_ERR                                                                   (0x1<<7) // Write to full  FIFO or read from empty  FIFO.
+  #define CAU_REG_INT_STS_CLR_CQE_FIFO_ERR_SHIFT                                                             7
+  #define CAU_REG_INT_STS_CLR_IGU_WDATA_FIFO_ERR                                                             (0x1<<8) // Write to full  FIFO or read from empty  FIFO.
+  #define CAU_REG_INT_STS_CLR_IGU_WDATA_FIFO_ERR_SHIFT                                                       8
+  #define CAU_REG_INT_STS_CLR_IGU_REQ_FIFO_ERR                                                               (0x1<<9) // Write to full  FIFO or read from empty  FIFO.
+  #define CAU_REG_INT_STS_CLR_IGU_REQ_FIFO_ERR_SHIFT                                                         9
+  #define CAU_REG_INT_STS_CLR_IGU_CMD_FIFO_ERR                                                               (0x1<<10) // Write to full  FIFO or read from empty  FIFO.
+  #define CAU_REG_INT_STS_CLR_IGU_CMD_FIFO_ERR_SHIFT                                                         10
+#define CAU_REG_INT_STS_WR                                                                                   0x1c00dcUL //Access:WR   DataWidth:0xb    // Multi Field Register.
+  #define CAU_REG_INT_STS_WR_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define CAU_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                             0
+  #define CAU_REG_INT_STS_WR_UNAUTHORIZED_PXP_RD_CMD                                                         (0x1<<1) // PXP read request arrived.
+  #define CAU_REG_INT_STS_WR_UNAUTHORIZED_PXP_RD_CMD_SHIFT                                                   1
+  #define CAU_REG_INT_STS_WR_UNAUTHORIZED_PXP_LENGTH_CMD                                                     (0x1<<2) // PXP write request without CQA and with length >1 arrived.
+  #define CAU_REG_INT_STS_WR_UNAUTHORIZED_PXP_LENGTH_CMD_SHIFT                                               2
+  #define CAU_REG_INT_STS_WR_PXP_SB_ADDRESS_ERROR                                                            (0x1<<3) // SB index > CAU_NUM_SB or  SB index > CAU_NUM_PI/num_pi_per_sb. CAU_SB_NUM is 288 in BB and 368 in K2. CAU_PI_NUM is 3456 in BB and 4416 in K2
+  #define CAU_REG_INT_STS_WR_PXP_SB_ADDRESS_ERROR_SHIFT                                                      3
+  #define CAU_REG_INT_STS_WR_PXP_PI_NUMBER_ERROR                                                             (0x1<<4) // PI relative number > num_pi_per_sb.
+  #define CAU_REG_INT_STS_WR_PXP_PI_NUMBER_ERROR_SHIFT                                                       4
+  #define CAU_REG_INT_STS_WR_CLEANUP_REG_SB_IDX_ERROR                                                        (0x1<<5) // SB index > CAU_SB_NUM or  SB index > CAU_PI_NUM/num_pi_per_sb. CAU_SB_NUM is 288 in BB and 368 in K2. CAU_PI_NUM is 3456 in BB and 4416 in K2
+  #define CAU_REG_INT_STS_WR_CLEANUP_REG_SB_IDX_ERROR_SHIFT                                                  5
+  #define CAU_REG_INT_STS_WR_FSM_INVALID_LINE                                                                (0x1<<6) // The FSM arrived to an invalid line.
+  #define CAU_REG_INT_STS_WR_FSM_INVALID_LINE_SHIFT                                                          6
+  #define CAU_REG_INT_STS_WR_CQE_FIFO_ERR                                                                    (0x1<<7) // Write to full  FIFO or read from empty  FIFO.
+  #define CAU_REG_INT_STS_WR_CQE_FIFO_ERR_SHIFT                                                              7
+  #define CAU_REG_INT_STS_WR_IGU_WDATA_FIFO_ERR                                                              (0x1<<8) // Write to full  FIFO or read from empty  FIFO.
+  #define CAU_REG_INT_STS_WR_IGU_WDATA_FIFO_ERR_SHIFT                                                        8
+  #define CAU_REG_INT_STS_WR_IGU_REQ_FIFO_ERR                                                                (0x1<<9) // Write to full  FIFO or read from empty  FIFO.
+  #define CAU_REG_INT_STS_WR_IGU_REQ_FIFO_ERR_SHIFT                                                          9
+  #define CAU_REG_INT_STS_WR_IGU_CMD_FIFO_ERR                                                                (0x1<<10) // Write to full  FIFO or read from empty  FIFO.
+  #define CAU_REG_INT_STS_WR_IGU_CMD_FIFO_ERR_SHIFT                                                          10
+#define CAU_REG_INT_MASK                                                                                     0x1c00e0UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define CAU_REG_INT_MASK_ADDRESS_ERROR                                                                     (0x1<<0) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.ADDRESS_ERROR .
+  #define CAU_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                               0
+  #define CAU_REG_INT_MASK_UNAUTHORIZED_PXP_RD_CMD                                                           (0x1<<1) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.UNAUTHORIZED_PXP_RD_CMD .
+  #define CAU_REG_INT_MASK_UNAUTHORIZED_PXP_RD_CMD_SHIFT                                                     1
+  #define CAU_REG_INT_MASK_UNAUTHORIZED_PXP_LENGTH_CMD                                                       (0x1<<2) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.UNAUTHORIZED_PXP_LENGTH_CMD .
+  #define CAU_REG_INT_MASK_UNAUTHORIZED_PXP_LENGTH_CMD_SHIFT                                                 2
+  #define CAU_REG_INT_MASK_PXP_SB_ADDRESS_ERROR                                                              (0x1<<3) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.PXP_SB_ADDRESS_ERROR .
+  #define CAU_REG_INT_MASK_PXP_SB_ADDRESS_ERROR_SHIFT                                                        3
+  #define CAU_REG_INT_MASK_PXP_PI_NUMBER_ERROR                                                               (0x1<<4) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.PXP_PI_NUMBER_ERROR .
+  #define CAU_REG_INT_MASK_PXP_PI_NUMBER_ERROR_SHIFT                                                         4
+  #define CAU_REG_INT_MASK_CLEANUP_REG_SB_IDX_ERROR                                                          (0x1<<5) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.CLEANUP_REG_SB_IDX_ERROR .
+  #define CAU_REG_INT_MASK_CLEANUP_REG_SB_IDX_ERROR_SHIFT                                                    5
+  #define CAU_REG_INT_MASK_FSM_INVALID_LINE                                                                  (0x1<<6) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.FSM_INVALID_LINE .
+  #define CAU_REG_INT_MASK_FSM_INVALID_LINE_SHIFT                                                            6
+  #define CAU_REG_INT_MASK_CQE_FIFO_ERR                                                                      (0x1<<7) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.CQE_FIFO_ERR .
+  #define CAU_REG_INT_MASK_CQE_FIFO_ERR_SHIFT                                                                7
+  #define CAU_REG_INT_MASK_IGU_WDATA_FIFO_ERR                                                                (0x1<<8) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.IGU_WDATA_FIFO_ERR .
+  #define CAU_REG_INT_MASK_IGU_WDATA_FIFO_ERR_SHIFT                                                          8
+  #define CAU_REG_INT_MASK_IGU_REQ_FIFO_ERR                                                                  (0x1<<9) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.IGU_REQ_FIFO_ERR .
+  #define CAU_REG_INT_MASK_IGU_REQ_FIFO_ERR_SHIFT                                                            9
+  #define CAU_REG_INT_MASK_IGU_CMD_FIFO_ERR                                                                  (0x1<<10) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.IGU_CMD_FIFO_ERR .
+  #define CAU_REG_INT_MASK_IGU_CMD_FIFO_ERR_SHIFT                                                            10
+#define CAU_REG_PRTY_MASK_H_0                                                                                0x1c0204UL //Access:RW   DataWidth:0xd    // Multi Field Register.
+  #define CAU_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT                                                          (0x1<<0) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM006_I_ECC_RF_INT .
+  #define CAU_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_SHIFT                                                    0
+  #define CAU_REG_PRTY_MASK_H_0_MEM001_I_ECC_0_RF_INT                                                        (0x1<<1) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM001_I_ECC_0_RF_INT .
+  #define CAU_REG_PRTY_MASK_H_0_MEM001_I_ECC_0_RF_INT_SHIFT                                                  1
+  #define CAU_REG_PRTY_MASK_H_0_MEM001_I_ECC_1_RF_INT                                                        (0x1<<2) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM001_I_ECC_1_RF_INT .
+  #define CAU_REG_PRTY_MASK_H_0_MEM001_I_ECC_1_RF_INT_SHIFT                                                  2
+  #define CAU_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_K2_E5                                                    (0x1<<3) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT .
+  #define CAU_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_K2_E5_SHIFT                                              3
+  #define CAU_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_K2_E5                                                    (0x1<<4) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT .
+  #define CAU_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_K2_E5_SHIFT                                              4
+  #define CAU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB                                                         (0x1<<3) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define CAU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_SHIFT                                                   3
+  #define CAU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2_E5                                                      (0x1<<5) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define CAU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2_E5_SHIFT                                                5
+  #define CAU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB                                                         (0x1<<4) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define CAU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_SHIFT                                                   4
+  #define CAU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_E5                                                      (0x1<<6) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define CAU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_E5_SHIFT                                                6
+  #define CAU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB                                                         (0x1<<5) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define CAU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_SHIFT                                                   5
+  #define CAU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_E5                                                      (0x1<<7) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define CAU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_E5_SHIFT                                                7
+  #define CAU_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB                                                         (0x1<<6) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define CAU_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_SHIFT                                                   6
+  #define CAU_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2_E5                                                      (0x1<<8) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define CAU_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2_E5_SHIFT                                                8
+  #define CAU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB                                                         (0x1<<7) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
+  #define CAU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_SHIFT                                                   7
+  #define CAU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2_E5                                                      (0x1<<9) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
+  #define CAU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2_E5_SHIFT                                                9
+  #define CAU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB                                                         (0x1<<8) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
+  #define CAU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_SHIFT                                                   8
+  #define CAU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2_E5                                                      (0x1<<10) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
+  #define CAU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2_E5_SHIFT                                                10
+  #define CAU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_0_BB                                                       (0x1<<10) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY_0 .
+  #define CAU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_0_BB_SHIFT                                                 10
+  #define CAU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_0_K2_E5                                                    (0x1<<11) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY_0 .
+  #define CAU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_0_K2_E5_SHIFT                                              11
+  #define CAU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_1_BB                                                       (0x1<<11) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY_1 .
+  #define CAU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_1_BB_SHIFT                                                 11
+  #define CAU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_1_K2_E5                                                    (0x1<<12) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY_1 .
+  #define CAU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_1_K2_E5_SHIFT                                              12
+  #define CAU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB                                                         (0x1<<9) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define CAU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_SHIFT                                                   9
+  #define CAU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB                                                         (0x1<<12) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define CAU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_SHIFT                                                   12
+#define CAU_REG_MEM_ECC_ENABLE_0                                                                             0x1c0210UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define CAU_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN                                                           (0x1<<0) // Enable ECC for memory ecc instance cau.i_cau_agg_unit_mem.i_ecc in module cau_agg_unit_mem_128data
+  #define CAU_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN_SHIFT                                                     0
+  #define CAU_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_0_EN                                                         (0x1<<1) // Enable ECC for memory ecc instance cau.cau_pi_mem_368sb_IF.i_cau_pi_mem.i_ecc_0 in module cau_pi_mem_368sb
+  #define CAU_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_0_EN_SHIFT                                                   1
+  #define CAU_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_1_EN                                                         (0x1<<2) // Enable ECC for memory ecc instance cau.cau_pi_mem_368sb_IF.i_cau_pi_mem.i_ecc_1 in module cau_pi_mem_368sb
+  #define CAU_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_1_EN_SHIFT                                                   2
+  #define CAU_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN_K2_E5                                                     (0x1<<3) // Enable ECC for memory ecc instance cau.cau_sb_addr_mem_368sb_IF.i_cau_sb_addr_mem.i_ecc in module cau_sb_addr_mem_368sb
+  #define CAU_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN_K2_E5_SHIFT                                               3
+  #define CAU_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_K2_E5                                                     (0x1<<4) // Enable ECC for memory ecc instance cau.cau_sb_var_mem_368sb_IF.i_cau_sb_var_mem.i_ecc in module cau_sb_var_mem_368sb
+  #define CAU_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_K2_E5_SHIFT                                               4
+#define CAU_REG_MEM_ECC_PARITY_ONLY_0                                                                        0x1c0214UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define CAU_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY                                                    (0x1<<0) // Set parity only for memory ecc instance cau.i_cau_agg_unit_mem.i_ecc in module cau_agg_unit_mem_128data
+  #define CAU_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY_SHIFT                                              0
+  #define CAU_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_0_PRTY                                                  (0x1<<1) // Set parity only for memory ecc instance cau.cau_pi_mem_368sb_IF.i_cau_pi_mem.i_ecc_0 in module cau_pi_mem_368sb
+  #define CAU_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_0_PRTY_SHIFT                                            1
+  #define CAU_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_1_PRTY                                                  (0x1<<2) // Set parity only for memory ecc instance cau.cau_pi_mem_368sb_IF.i_cau_pi_mem.i_ecc_1 in module cau_pi_mem_368sb
+  #define CAU_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_1_PRTY_SHIFT                                            2
+  #define CAU_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY_K2_E5                                              (0x1<<3) // Set parity only for memory ecc instance cau.cau_sb_addr_mem_368sb_IF.i_cau_sb_addr_mem.i_ecc in module cau_sb_addr_mem_368sb
+  #define CAU_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY_K2_E5_SHIFT                                        3
+  #define CAU_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_K2_E5                                              (0x1<<4) // Set parity only for memory ecc instance cau.cau_sb_var_mem_368sb_IF.i_cau_sb_var_mem.i_ecc in module cau_sb_var_mem_368sb
+  #define CAU_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_K2_E5_SHIFT                                        4
+#define CAU_REG_MEM_ECC_ERROR_CORRECTED_0                                                                    0x1c0218UL //Access:RC   DataWidth:0x5    // Multi Field Register.
+  #define CAU_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT                                             (0x1<<0) // Record if a correctable error occurred on memory ecc instance cau.i_cau_agg_unit_mem.i_ecc in module cau_agg_unit_mem_128data
+  #define CAU_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT_SHIFT                                       0
+  #define CAU_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_0_CORRECT                                           (0x1<<1) // Record if a correctable error occurred on memory ecc instance cau.cau_pi_mem_368sb_IF.i_cau_pi_mem.i_ecc_0 in module cau_pi_mem_368sb
+  #define CAU_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_0_CORRECT_SHIFT                                     1
+  #define CAU_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_1_CORRECT                                           (0x1<<2) // Record if a correctable error occurred on memory ecc instance cau.cau_pi_mem_368sb_IF.i_cau_pi_mem.i_ecc_1 in module cau_pi_mem_368sb
+  #define CAU_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_1_CORRECT_SHIFT                                     2
+  #define CAU_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT_K2_E5                                       (0x1<<3) // Record if a correctable error occurred on memory ecc instance cau.cau_sb_addr_mem_368sb_IF.i_cau_sb_addr_mem.i_ecc in module cau_sb_addr_mem_368sb
+  #define CAU_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT_K2_E5_SHIFT                                 3
+  #define CAU_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_K2_E5                                       (0x1<<4) // Record if a correctable error occurred on memory ecc instance cau.cau_sb_var_mem_368sb_IF.i_cau_sb_var_mem.i_ecc in module cau_sb_var_mem_368sb
+  #define CAU_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_K2_E5_SHIFT                                 4
+#define CAU_REG_MEM_ECC_EVENTS                                                                               0x1c021cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define CAU_REG_NUM_PI_PER_SB                                                                                0x1c0400UL //Access:RW   DataWidth:0x6    // The number of Protocol Index per Status Block. Value can be even numbers only from 2 to 32. numbers above 12 will reduce the number of SB that are supported (3456/num_pi_per_sb).
+#define CAU_REG_PXP_REQ_MSG_FIELDS                                                                           0x1c0404UL //Access:RW   DataWidth:0x13   // Multi Field Register.
+  #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_SB_TPH_HINT                                                     (0x3<<0) // The value of the TPH Hint field in the PXP request for SB DMA.
+  #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_SB_TPH_HINT_SHIFT                                               0
+  #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_CQE_TPH_HINT                                                    (0x3<<2) // The value of the TPH Hint field in the PXP request for CQE messages.
+  #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_CQE_TPH_HINT_SHIFT                                              2
+  #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_ENDIANITY                                                       (0x3<<4) // The endianity mode in the PXP request.
+  #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_ENDIANITY_SHIFT                                                 4
+  #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_RO                                                              (0x1<<6) // The value of the Relax Ordering field in the PXP request.
+  #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_RO_SHIFT                                                        6
+  #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_NS                                                              (0x1<<7) // The value of the No Snoop field in the PXP request.
+  #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_NS_SHIFT                                                        7
+  #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_VQID                                                            (0x1f<<8) // The value of the VQID field in the PXP request.
+  #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_VQID_SHIFT                                                      8
+  #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_SB_PAD2CACHE                                                    (0x1<<13) // The value of the Pad to Cache Line field in the SB DMA PXP request.
+  #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_SB_PAD2CACHE_SHIFT                                              13
+  #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_CQE_PAD2CACHE                                                   (0x1<<14) // The value of the Pad to Cache Line field in the CQE PXP request.
+  #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_CQE_PAD2CACHE_SHIFT                                             14
+  #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_ATC                                                             (0x7<<15) // The value of the ATC flags  in the PXP request.
+  #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_ATC_SHIFT                                                       15
+  #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_DONE_TYPE                                                       (0x1<<18) // The value of the done type in the PXP request.
+  #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_DONE_TYPE_SHIFT                                                 18
+#define CAU_REG_PI_BYP_GRAY2_EN                                                                              0x1c0408UL //Access:RW   DataWidth:0x1    // Enabling pi value of command N+2/N+1 as part of sb_dma message of command N (Cont00065605 related) When set, bypass can be implemented (i.e. bug not fixed) When reset, bypass cannot be implemented (i.e. bug fixed)
+#define CAU_REG_OUTSTANDING_WRITE                                                                            0x1c040cUL //Access:RW   DataWidth:0x8    // The max number of outstanding write requests without receiving write done. Values 1-128. Zero is not a valid value.
+#define CAU_REG_RESET_MEMORIES                                                                               0x1c0410UL //Access:RW   DataWidth:0x6    // Write one to each bit will reset the whole memory. When the memory reset finished the appropriate bit will be clear. [0] - PI memory; [1] - SB var memory; [2]- SB address memory; [3] -Timers memory; [4] - fsm memory,[5] - aggregation memory.
+#define CAU_REG_CLEANUP_COMMAND                                                                              0x1c0414UL //Access:W    DataWidth:0xd    // Write to this register will perform cleanup on the written SB number. [8:0] - SB absolute index; [9] - Cleanup set/clr (0-clr; 1 - set); [12:10] Cleanup type (0-4).
+#define CAU_REG_CLEANUP_COMMAND_DONE                                                                         0x1c0418UL //Access:R    DataWidth:0x1    // When reading one from this register mean the cleanup was done. Reading it will clear its value.
+#define CAU_REG_IN_ARB_PRIORITY                                                                              0x1c0500UL //Access:RW   DataWidth:0x6    // Input arbiter (sp with anti starvation) priority for the input clients: bits 1:0 PXP input commands. bits 3:2 RBC cleanup. bits 5:4 Timer expiration priority. Priority values are from 0 (highest priority) to 2 (lowest).
+#define CAU_REG_IN_ARB_TIMEOUT                                                                               0x1c0504UL //Access:RW   DataWidth:0x8    // Input arbiter (sp with anti starvation) anti starvation timeout. value of 0 means the arbitration is constant rr.
+#define CAU_REG_CQE_SIZE                                                                                     0x1c0600UL //Access:RW   DataWidth:0x1    // Indicate the size of the CQE. 0 - 32B; 1 - 64B.
+#define CAU_REG_CQE_AGG_UNIT_SIZE                                                                            0x1c0604UL //Access:RW   DataWidth:0x2    // Indicate the size of the AGG unit. 0 - 64B; 1 - 128B; 2 - 256B; 3 - illegal.
+#define CAU_REG_CQE_FLUSH_ALL                                                                                0x1c0608UL //Access:RW   DataWidth:0x1    // Flush all command - will flush all the CQE AGG unit that are in dirty state and free all AGG units.
+#define CAU_REG_CQE_FLUSH_ALL_DONE                                                                           0x1c060cUL //Access:R    DataWidth:0x1    // Read clear register. 1 means the the cqe_flush_all command was finished.
+#define CAU_REG_AGG_RELEASE_TIMER                                                                            0x1c0610UL //Access:RW   DataWidth:0x10   // The value of ReleaseTmr in system clock cycles (25MHz). Each expiration will generate an event that affect the FSM of each AGG unit that is in CLEAN state (will move to TIME WAIT state) and TIME WAIT state (will move to CLEAN). In case this configuration should be changed, the change flow is done in several phases of writes while each write is as close as possible to the required configuration and it should keep one of the bits that are set in the previous write (or in the reset value) as set. Each write should be followed by a read. For example to change the value of (binary) 11001 to (binary) 1100100: write (binary) 1101100, read, write (binary) 1100100.
+#define CAU_REG_TICK_SIZE                                                                                    0x1c0700UL //Access:RW   DataWidth:0x10   // The number of cycles in each tick of the timer. Clock 25 MHz. Value must be bigger than 2. In case this configuration should be changed, the change flow is done in several phases of writes while each write is as close as possible to the required configuration and it should keep one of the bits that are set in the previous write (or in the reset value) as set. Each write should be followed by a read. For example to change the reset value of (binary) 11001 (1usec) to (binary) 1100100 (4usec): write (binary) 1101100, read, write (binary) 1100100.
+#define CAU_REG_SCAN_TICK                                                                                    0x1c0704UL //Access:RW   DataWidth:0xc    // The number of tick that will cause scan. Zero is not a valid number.
+#define CAU_REG_LONG_TIMEOUT_THRESHOLD                                                                       0x1c0708UL //Access:RW   DataWidth:0xa    // Threshold in ticks for indicating far timeout to the MISC block.
+#define CAU_REG_STOP_SCAN                                                                                    0x1c070cUL //Access:RW   DataWidth:0x1    // Setting this bit will disable the timer expiration mechanism. Should be used in close the gate only.
+#define CAU_REG_RX_TIMER_STATUS                                                                              0x1c0780UL //Access:R    DataWidth:0x20   // Rx timers status. 0 - inactive 1 - active.
+#define CAU_REG_RX_TIMER_STATUS_SIZE                                                                         9
+#define CAU_REG_TX_TIMER_STATUS                                                                              0x1c0800UL //Access:R    DataWidth:0x20   // Tx timers status. 0 - inactive 1 - active.
+#define CAU_REG_TX_TIMER_STATUS_SIZE                                                                         9
+#define CAU_REG_WDATA_FIFO_AFULL_THR                                                                         0x1c0880UL //Access:RW   DataWidth:0x6    // almost full threshold for wdata fifo
+#define CAU_REG_CQE_FIFO_AFULL_THR                                                                           0x1c0884UL //Access:RW   DataWidth:0x5    // almost full threshold for cqe fifo (within the input cmd arbiter)
+#define CAU_REG_IGU_REQ_CREDIT_STATUS                                                                        0x1c0980UL //Access:R    DataWidth:0x1    // Debug:  IGU-CAU request interface credit.  In idle should be 1.
+#define CAU_REG_IGU_CMD_CREDIT_STATUS                                                                        0x1c0984UL //Access:R    DataWidth:0x1    // Debug:  IGU-CAU command interface credit.  In idle should be 1.
+#define CAU_REG_STAT_CTRL_SB_SELECT                                                                          0x1c0a80UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define CAU_REG_STAT_CTRL_SB_SELECT_IDX                                                                    (0x1ff<<0) // Statistic: SB index to collect statistics on.
+  #define CAU_REG_STAT_CTRL_SB_SELECT_IDX_SHIFT                                                              0
+  #define CAU_REG_STAT_CTRL_SB_SELECT_EN                                                                     (0x1<<9) // Statistic: enable SB index  statistics.
+  #define CAU_REG_STAT_CTRL_SB_SELECT_EN_SHIFT                                                               9
+#define CAU_REG_STAT_CTRL_PROTOCOL                                                                           0x1c0a84UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define CAU_REG_STAT_CTRL_PROTOCOL_NUM                                                                     (0x1f<<0) // Statistic: protocol number to collect statistics on.
+  #define CAU_REG_STAT_CTRL_PROTOCOL_NUM_SHIFT                                                               0
+  #define CAU_REG_STAT_CTRL_PROTOCOL_EN                                                                      (0x1<<5) // Statistic: enable protocol  statistics.
+  #define CAU_REG_STAT_CTRL_PROTOCOL_EN_SHIFT                                                                5
+#define CAU_REG_STAT_CTRL_CLIENT                                                                             0x1c0a88UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define CAU_REG_STAT_CTRL_CLIENT_IDX                                                                       (0xf<<0) // Statistic: client index to collect statistics on. 0=TSTORM; 1=MSTORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=PSTORM; 6=PCIe; 7=other (PBF/NIG/QM); 8 =  GRC cleanup; 9 = Expiration.
+  #define CAU_REG_STAT_CTRL_CLIENT_IDX_SHIFT                                                                 0
+  #define CAU_REG_STAT_CTRL_CLIENT_EN                                                                        (0x1<<4) // Statistic: enable client  statistics.
+  #define CAU_REG_STAT_CTRL_CLIENT_EN_SHIFT                                                                  4
+#define CAU_REG_STAT_CTRL_FSM0_LINE                                                                          0x1c0a8cUL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define CAU_REG_STAT_CTRL_FSM0_LINE_SELECT                                                                 (0xff<<0) // Statistic: Line number of FSM 0 to collect statistics on.
+  #define CAU_REG_STAT_CTRL_FSM0_LINE_SELECT_SHIFT                                                           0
+  #define CAU_REG_STAT_CTRL_FSM0_LINE_EN                                                                     (0x1<<8) // Statistic: enable FSM 0 line  statistics.
+  #define CAU_REG_STAT_CTRL_FSM0_LINE_EN_SHIFT                                                               8
+#define CAU_REG_STAT_CTRL_FSM1_LINE                                                                          0x1c0a90UL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define CAU_REG_STAT_CTRL_FSM1_LINE_SELECT                                                                 (0xff<<0) // Statistic: Line number of FSM 1 to collect statistics on.
+  #define CAU_REG_STAT_CTRL_FSM1_LINE_SELECT_SHIFT                                                           0
+  #define CAU_REG_STAT_CTRL_FSM1_LINE_EN                                                                     (0x1<<8) // Statistic: enable FSM 1 line  statistics.
+  #define CAU_REG_STAT_CTRL_FSM1_LINE_EN_SHIFT                                                               8
+#define CAU_REG_STAT_CTRL_TIMER_CMD_TYPE                                                                     0x1c0a94UL //Access:RW   DataWidth:0x3    // Statistic: enable timer command type. One bit for each timer command type: [0] - rewind; [1] - clear; [2] - rewind to shorter. When set the counter monitor these commands.
+#define CAU_REG_STAT_COUNTER_SB_GEN                                                                          0x1c0b80UL //Access:RW   DataWidth:0x20   // The number of times that SB was generated (written) for the selected SB (according to stat_ctrl_sb_select_idx).
+#define CAU_REG_STAT_COUNTER_FSM0_TIMER_CMD                                                                  0x1c0b84UL //Access:RW   DataWidth:0x20   // The number of times that the timer was rewind for the selected SB (according to stat_ctrl_sb_select_idx) and timer command (according to stat_ctrl_timer_cmd_type) on FSM0.
+#define CAU_REG_STAT_COUNTER_FSM1_TIMER_CMD                                                                  0x1c0b88UL //Access:RW   DataWidth:0x20   // The number of times that the timer was rewind for the selected SB (according to stat_ctrl_sb_select_idx) and timer command (according to stat_ctrl_timer_cmd_type) on FSM1.
+#define CAU_REG_STAT_COUNTER_FSM0_EXP                                                                        0x1c0b8cUL //Access:RW   DataWidth:0x20   // The number of times that the timer has expired for FSM0 of the selected SB (according to stat_ctrl_sb_select_idx) .
+#define CAU_REG_STAT_COUNTER_FSM1_EXP                                                                        0x1c0b90UL //Access:RW   DataWidth:0x20   // The number of times that the timer has expired for FSM1 of the selected SB (according to stat_ctrl_sb_select_idx) .
+#define CAU_REG_STAT_COUNTER_PROTOCOL_TIMER_CMD                                                              0x1c0b94UL //Access:RW   DataWidth:0x20   // The number of times that the timer was rewind for the selected SB (according to stat_ctrl_sb_select_idx); selected PI (according to stat_ctrl_protocol_num) and timer command (according to stat_ctrl_timer_cmd_type).
+#define CAU_REG_STAT_COUNTER_PI_INCOME_CMD                                                                   0x1c0b98UL //Access:RW   DataWidth:0x20   // The number of incoming producer update commands for the selected PI (according to stat_ctrl_protocol_num) and SB (according to stat_ctrl_sb_idx).
+#define CAU_REG_STAT_COUNTER_CLIENT_INCOME_CMD                                                               0x1c0b9cUL //Access:RW   DataWidth:0x20   // The number of incoming commands from the selected client (according to stat_ctrl_client_idx).
+#define CAU_REG_STAT_COUNTER_FSM0_LINE                                                                       0x1c0ba0UL //Access:RW   DataWidth:0x20   // The number of times the FSM reached a specific line (stat_ctrl_fsm0_line_select) for the selected protocol (stat_ctrl_protocol_idx) within the selected SB (stat_ctrl_sb_select_idx).
+#define CAU_REG_STAT_COUNTER_FSM1_LINE                                                                       0x1c0ba4UL //Access:RW   DataWidth:0x20   // The number of times the FSM reached a specific line (stat_ctrl_fsm1_line_select) for the selected protocol (stat_ctrl_protocol_idx) within the selected SB (stat_ctrl_sb_select_idx).
+#define CAU_REG_STAT_COUNTER_CQE_MSG_SENT                                                                    0x1c0ba8UL //Access:RW   DataWidth:0x20   // The number of CQE messages that where sent to the PXP.
+#define CAU_REG_STAT_COUNTER_CQE_DMA_QWORD                                                                   0x1c0bacUL //Access:RW   DataWidth:0x20   // The amount of CQE data that was sent in QWORD.
+#define CAU_REG_STAT_COUNTER_CQE_CACHE_HIT                                                                   0x1c0bb0UL //Access:RW   DataWidth:0x20   // The number of CQE command that there was a match in the aggregation memory.
+#define CAU_REG_STAT_COUNTER_CQE_CACHE_MISS_NEW_AGG                                                          0x1c0bb4UL //Access:RW   DataWidth:0x20   // The number of CQE command that there was no match in the aggregation memory but there was a free unit found.
+#define CAU_REG_STAT_COUNTER_CQE_CACHE_MISS_NO_FREE                                                          0x1c0bb8UL //Access:RW   DataWidth:0x20   // The number of CQE command that there was no match in the aggregation memory and no free unit was found.
+#define CAU_REG_STAT_COUNTER_CQE_FULL_CACHE                                                                  0x1c0bbcUL //Access:RW   DataWidth:0x20   // The nuber of CQE dmae with full cache (DMA size = cqe_agg_unit_size).
+#define CAU_REG_STAT_COUNTER_CQE_PARTIAL_CACHE                                                               0x1c0bc0UL //Access:RW   DataWidth:0x20   // The nuber of CQE dmae with partial cache (DMA size < cqe_agg_unit_size).
+#define CAU_REG_DEBUG_FIFO_STATUS                                                                            0x1c0c80UL //Access:R    DataWidth:0x6    // Debug: all the FIFO status. 0 - FIFO empty; 1 - FIFO not empty. [0] - PXP command FIFO; [1] - CQE FIFO; [2] - timers expiration FIFO;  [3] - IGU req FIFO; [4] - IGU wdata FIFO; [5] - IGU command FIFO.
+#define CAU_REG_ERROR_PXP_REQ                                                                                0x1c0c84UL //Access:R    DataWidth:0x15   // Debug; debug information if an error command arrived to the CAU from the PXP: [20:18] - error typ (1- read request; 2 - CqeType disabled and length >1 or CQE enable and length not match cqe_siz; 3 - sb_index >= CAU_NUM_SB or SB index >  CAU_NUM_PI/num_pi_per_sb; 4 - pi_relative_number > num_pi_per_sb);  [17:14] - source (0=TSTORM; 1=MSTORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=PSTORM; 6=PCIe; 7=other (PBF/NIG/QM)); [13:5] - SB abs index; [4:0] - pi_relative_number. If error type = 1 ignore bits [13:0].
+#define CAU_REG_ERROR_FSM_LINE                                                                               0x1c0c88UL //Access:R    DataWidth:0x1d   // Debug; debug information if the FSM arived to an invalid line:  [3:0] - source (0=TSTORM; 1=MSTORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=PSTORM; 6=PCIe; 7=other (PBF/NIG/QM); 8=GRC cleanup; 9=timer expiration); [12:4] - SB abs index; [13] -  reserved; [14] otherFSM (if set the commad was due to other FSM); [15] - FSM_sel;  [20:16] - PI relative number; [24:21] - event ID; [28:25] - state;.
+#define CAU_REG_ERROR_FSM_LINE_PRE                                                                           0x1c0c8cUL //Access:R    DataWidth:0xa    // Debug; [9] if set data valid; [8] previous FSM_sel; [7:4] - previous state; [3:0] - previous event ID;.
+#define CAU_REG_PARITY_LATCH_STATUS                                                                          0x1c0c90UL //Access:R    DataWidth:0x1    // Debug: If set a parity occurd and the CAU assert discard flag to the IGU from now on (until hard reset).
+#define CAU_REG_ERROR_CLEANUP_CMD_REG                                                                        0x1c0c94UL //Access:R    DataWidth:0x19   // comment="Debug: [15:0] The PF that caused the error- one bit per PF; [24:16] - SB index.
+#define CAU_REG_AGG_UNITS_STATE_READ_EN                                                                      0x1c0c98UL //Access:W    DataWidth:0x1    // Debug: write only. Writing to this register will copy the aggregation unit status to the agg_unit_state registers.
+#define CAU_REG_AGG_UNITS_0TO15_STATE                                                                        0x1c0c9cUL //Access:R    DataWidth:0x20   // Debug: Each 2 bits reflect the aggregation unit state of unit [i] when there was writing to agg_units_state_read_en register. (i =0-15). 0 - free; 1 - dirty; 2 - clean; 3 - time wait.
+#define CAU_REG_AGG_UNITS_16TO31_STATE                                                                       0x1c0ca0UL //Access:R    DataWidth:0x20   // Debug: Each 2 bits reflect the aggregation unit state of unit [i] when there was writing to agg_units_state_read_en register. (i = 16-31). 0 - free; 1 - dirty; 2 - clean; 3 - time wait.
+#define CAU_REG_AGG_UNITS_32TO47_STATE                                                                       0x1c0ca4UL //Access:R    DataWidth:0x20   // Debug: Each 2 bits reflect the aggregation unit state of unit [i] when there was writing to agg_units_state_read_en register. (i = 32-47). 0 - free; 1 - dirty; 2 - clean; 3 - time wait.
+#define CAU_REG_AGG_UNITS_48TO63_STATE                                                                       0x1c0ca8UL //Access:R    DataWidth:0x20   // Debug: Each 2 bits reflect the aggregation unit state of unit [i] when there was writing to agg_units_state_read_en register. (i = 48-63). 0 - free; 1 - dirty; 2 - clean; 3 - time wait.
+#define CAU_REG_ECO_RESERVED                                                                                 0x1c0cacUL //Access:RW   DataWidth:0x8    // Reserved for ECO if needed.
+#define CAU_REG_DEBUG_RECORD_MASK_MIN_SB                                                                     0x1c0d80UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define CAU_REG_DEBUG_RECORD_MASK_MIN_SB_IDX                                                               (0x1ff<<0) // Debug: minimun SB index for the debug.
+  #define CAU_REG_DEBUG_RECORD_MASK_MIN_SB_IDX_SHIFT                                                         0
+  #define CAU_REG_DEBUG_RECORD_MASK_MIN_SB_EN                                                                (0x1<<9) // Debug: if set the debug information will be collected for SB index equal or above debug_record_mask_min_sb_idx.
+  #define CAU_REG_DEBUG_RECORD_MASK_MIN_SB_EN_SHIFT                                                          9
+#define CAU_REG_DEBUG_RECORD_MASK_MAX_SB                                                                     0x1c0d84UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define CAU_REG_DEBUG_RECORD_MASK_MAX_SB_IDX                                                               (0x1ff<<0) // Debug: maximum SB index for the debug.
+  #define CAU_REG_DEBUG_RECORD_MASK_MAX_SB_IDX_SHIFT                                                         0
+  #define CAU_REG_DEBUG_RECORD_MASK_MAX_SB_EN                                                                (0x1<<9) // Debug: if set the debug information will be collected for SB index equal or below debug_record_mask_min_sb_idx.
+  #define CAU_REG_DEBUG_RECORD_MASK_MAX_SB_EN_SHIFT                                                          9
+#define CAU_REG_DEBUG_RECORD_MASK_FID                                                                        0x1c0d88UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define CAU_REG_DEBUG_RECORD_MASK_FID_NUM                                                                  (0x1ff<<0) // Debug: FID number for debug . if VF - [8] = 1; [7:0] = VF number; if PF - [8] = 0; [7:4] = 0; [3:0] = PF number.
+  #define CAU_REG_DEBUG_RECORD_MASK_FID_NUM_SHIFT                                                            0
+  #define CAU_REG_DEBUG_RECORD_MASK_FID_EN                                                                   (0x1<<9) // Debug: if set the debug information will be collected for FID specified in debug_record_mask_fid_num.
+  #define CAU_REG_DEBUG_RECORD_MASK_FID_EN_SHIFT                                                             9
+  #define CAU_REG_DEBUG_RECORD_MASK_FID_EXCLUDE                                                              (0x1<<10) // Debug: if clear the debug information will be collected for FID equal to debug_record_mask_fid_num. if set he debug information will be collected for FID not equal to debug_record_mask_fid_num.
+  #define CAU_REG_DEBUG_RECORD_MASK_FID_EXCLUDE_SHIFT                                                        10
+#define CAU_REG_DEBUG_RECORD_MASK_SOURCE                                                                     0x1c0d8cUL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define CAU_REG_DEBUG_RECORD_MASK_SOURCE_IDX                                                               (0xf<<0) // Debug: source index for the debug. 0=TSTORM; 1=MSTORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=PSTORM; 6=PCIe; 7=other (PBF/NIG/QM); 8 =  GRC cleanup; 9 = expiration.
+  #define CAU_REG_DEBUG_RECORD_MASK_SOURCE_IDX_SHIFT                                                         0
+  #define CAU_REG_DEBUG_RECORD_MASK_SOURCE_EN                                                                (0x1<<4) // Debug: if set the debug information will be collected for source equal to debug_record_mask_source_idx.
+  #define CAU_REG_DEBUG_RECORD_MASK_SOURCE_EN_SHIFT                                                          4
+#define CAU_REG_DEBUG_RECORD_MASK_CMD_TYPE                                                                   0x1c0d90UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define CAU_REG_DEBUG_RECORD_MASK_CMD_TYPE_IDX                                                             (0x7<<0) // Debug: command type for the debug. [0] - PI producer update; [1] - cleanup; [2] - expiration.
+  #define CAU_REG_DEBUG_RECORD_MASK_CMD_TYPE_IDX_SHIFT                                                       0
+  #define CAU_REG_DEBUG_RECORD_MASK_CMD_TYPE_EN                                                              (0x1<<3) // Debug: if set the debug information will be collected for the marked commands only according to debug_record_mask_cmd_type_idx.
+  #define CAU_REG_DEBUG_RECORD_MASK_CMD_TYPE_EN_SHIFT                                                        3
+#define CAU_REG_REQ_COUNTER                                                                                  0x1c0e00UL //Access:R    DataWidth:0x8    // Debug:  the number of request that were sent to the IGU.
+#define CAU_REG_ACK_COUNTER                                                                                  0x1c0e04UL //Access:R    DataWidth:0x8    // Debug:  the number of ack that were received from the IGU on the recuest interface.
+#define CAU_REG_WDONE_COUNTER                                                                                0x1c0e08UL //Access:R    DataWidth:0x8    // Debug:  the number of write done that were received from the IGU.
+#define CAU_REG_DBG_OUT_DATA                                                                                 0x1c0e80UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define CAU_REG_DBG_OUT_DATA_SIZE                                                                            8
+#define CAU_REG_DBG_OUT_VALID                                                                                0x1c0ea0UL //Access:R    DataWidth:0x4    // Dbgmux output valid
+#define CAU_REG_DBG_OUT_FRAME                                                                                0x1c0ea4UL //Access:R    DataWidth:0x4    // Dbgmux output frame
+#define CAU_REG_DBG_SELECT                                                                                   0x1c0ea8UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define CAU_REG_DBG_DWORD_ENABLE                                                                             0x1c0eacUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define CAU_REG_DBG_SHIFT                                                                                    0x1c0eb0UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define CAU_REG_DBG_FORCE_VALID                                                                              0x1c0eb4UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define CAU_REG_DBG_FORCE_FRAME                                                                              0x1c0eb8UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define CAU_REG_MAIN_FSM_STATUS                                                                              0x1c0f00UL //Access:R    DataWidth:0x4    // Debug:  FSM state for debug.
+#define CAU_REG_VAR_READ_FSM_STATUS                                                                          0x1c0f04UL //Access:R    DataWidth:0x2    // Debug:  FSM state for debug.
+#define CAU_REG_IGU_DMA_FSM_STATUS                                                                           0x1c0f08UL //Access:R    DataWidth:0x3    // Debug:  FSM state for debug.
+#define CAU_REG_IGU_CQE_CMD_FSM_STATUS                                                                       0x1c0f0cUL //Access:R    DataWidth:0x5    // Debug:  FSM state for debug.Idle state value are 0-2
+#define CAU_REG_IGU_CQE_AGG_FSM_STATUS                                                                       0x1c0f10UL //Access:R    DataWidth:0x4    // Debug:  FSM state for debug.
+#define CAU_REG_CQE_FIFO                                                                                     0x1c2000UL //Access:WB_R DataWidth:0x80   // Debug: Provides read-only access of the CQE input command FIFO. Intended for test/debug purposes.
+#define CAU_REG_CQE_FIFO_SIZE                                                                                120
+#define CAU_REG_IGU_CMD_FIFO                                                                                 0x1c2200UL //Access:WB_R DataWidth:0x35   // Debug: Provides read-only access of the IGU command FIFO. Intended for test/debug purposes.
+#define CAU_REG_IGU_CMD_FIFO_SIZE                                                                            16
+#define CAU_REG_PXP_REQ_FIFO                                                                                 0x1c2300UL //Access:WB_R DataWidth:0x62   // Debug: Provides read-only access of the PXP reques FIFO. Intended for test/debug purposes.
+#define CAU_REG_PXP_REQ_FIFO_SIZE                                                                            32
+#define CAU_REG_PXP_WDATA_FIFO                                                                               0x1c2400UL //Access:WB_R DataWidth:0x84   // Debug: Provides read-only access of the PXP write-data FIFO. Intended for test/debug purposes.
+#define CAU_REG_PXP_WDATA_FIFO_SIZE                                                                          256
+#define CAU_REG_AGG_UNIT_CAM                                                                                 0x1c4000UL //Access:R    DataWidth:0xf    // Debug: The SB index and PI relative number of each aggregation unit. [0] - valid; [9:1] - absolute SB index; [14:10] - relative PI number.
+#define CAU_REG_AGG_UNIT_CAM_SIZE                                                                            64
+#define CAU_REG_FSM_TABLE                                                                                    0x1c4400UL //Access:RW   DataWidth:0x10   // The FSM table is a truth table. The inputs to the truth table are the address of the RAM and the outputs is the data in the RAM. The bits [7:4] of the address are the current_state and bits [3:0] are the event_id. The data is :[3:0] - next state; [5:4] - timer cmd (0 - None; 1 - Rewind; 2 - Clear; 3 - Rewind to shorter); [6] - SB producer increment (If set the SB segment index (PROD) is incremented by 1); [7] - SB write cmd (If set the entire SB segment is written over the PXP to host memory); [8] IGU cmd (If set then generate an IGU PROD update command); [12:9] - event ID to other FSM (The event ID value to generate to the other FSM); [14:13] - update timer cmd (0 - NONE; 1 - Set to new; 2 - Set to max (new/old); 3 - Set to min (new/old)); [15] - valid line (If set then this line is a valid line).
+#define CAU_REG_FSM_TABLE_SIZE                                                                               256
+#define CAU_REG_SB_VAR_MEMORY                                                                                0x1c6000UL //Access:WB   DataWidth:0x40   // Status Block variable: [23:0] producer index; [27:24] state0 (RX); [31:28] state1 (TX); [38:32] SbTimeSet0 (Indicates the RX TimeSet that this SB is associated with); [45:39] SbTimeSet1 (Indicates the TX TimeSet that this SB is associated with); [47:46] TimerRes0 (This value will determine the RX FSM timer resolution in ticks. Valid values are 0-2 only); [49:48] TimerRes1 (This value will determine the TX FSM timer resolution in ticks. Valid values are 0-2 only); [62:50] FID ([12:9] - PF number (in case of VF the parent PF); [8] - VF valid (1 - VF; 0 - PF); [7:0] - VF number (if VF valid = 0 -must be zero)); [63] TPH valid (If set then indicates that the TPH STAG is equal to the SB number. Otherwise the STAG will be equal to all ones);  the memory will receive  the following reset values after writing to the appropriate bit in the reset memory register: All fields will be zero; excluding the FID; each PF will receive  17 SB; 0-16 PF0; 17-33 PF1 .. 119-135 PF7. All the SB above 136 reset value is zero therefore thy are allocated to PF 0 also.
+#define CAU_REG_SB_VAR_MEMORY_SIZE_BB                                                                        576
+#define CAU_REG_SB_VAR_MEMORY_SIZE_K2_E5                                                                     736
+#define CAU_REG_SB_ADDR_MEMORY                                                                               0x1c8000UL //Access:WB   DataWidth:0x40   // Address of the Status Block DMA message.
+#define CAU_REG_SB_ADDR_MEMORY_SIZE_BB                                                                       576
+#define CAU_REG_SB_ADDR_MEMORY_SIZE_K2_E5                                                                    736
+#define CAU_REG_PI_MEMORY                                                                                    0x1d0000UL //Access:RW   DataWidth:0x18   // Protocol Index memory.[15:0] - protocol producer; [22:16] - PiTimeSet (This value determines the TimeSet that the PI is associated with); [23] - FsmSel (0-RX; 1 - TX).
+#define CAU_REG_PI_MEMORY_SIZE_BB                                                                            3456
+#define CAU_REG_PI_MEMORY_SIZE_K2_E5                                                                         4416
+#define CAU_REG_AGG_UNIT_DATA_MEMORY                                                                         0x1d8000UL //Access:WB   DataWidth:0x80   // Debug: the CQE aggregated data. Each aggergation unit size occupies N addresses. N: If (cqe_agg_unit_size = 0), then N = 4  addresses If (cqe_agg_unit_size = 1), then N = 8  addresses If (cqe_agg_unit_size = 2), then N = 16 addresses Address calculation: If (AggUnitSizeLog = 2 and CqeSizeLog = 0), then Address = {slot number[2:0], line_couner[0], agg_unit_index[4:0]}; Else If (AggUnitSizeLog = 2 and CqeSizeLog = 1), then  Address = {slot number[1:0], line_couner [1:0], agg_unit_index[4:0]}; Else If (AggUnitSizeLog = 1 and CqeSizeLog = 1), then Address = {slot number[0], line_couner [1:0], agg_unit_index[5:0]}; Else Address = {slot number[1:0], line_couner [0], agg_unit_index[5:0]};                          Note that line_couner is running index in the slot;
+#define CAU_REG_AGG_UNIT_DATA_MEMORY_SIZE_BB                                                                 1792
+#define CAU_REG_AGG_UNIT_DATA_MEMORY_SIZE_K2_E5                                                              3584
+#define CAU_REG_AGG_UNIT_DESCRIPTOR                                                                          0x1dc000UL //Access:WB_R DataWidth:0x56   // Debug: the aggregation data of each unit. [63:0] - address; [71:64] - valid slots; [84:72] - FID ([13:9] - PF number (in case of VF the parent PF); [8] - VF valid (1 - VF; 0 - PF); [7:0] - VF number (if VF valid = 0 -must be zero)). [85] - TPH valid bit.
+#define CAU_REG_AGG_UNIT_DESCRIPTOR_SIZE                                                                     256
+#define CAU_REG_SB_TIMERS_MEMORY                                                                             0x1dd000UL //Access:R    DataWidth:0x18   // The SB timers. For each SB there are two timers: [11:0] - RX timer; [23:12] - TX timer.
+#define CAU_REG_SB_TIMERS_MEMORY_SIZE_BB                                                                     288
+#define CAU_REG_SB_TIMERS_MEMORY_SIZE_K2_E5                                                                  368
+#define PRS_REG_SOFT_RST                                                                                     0x1f0000UL //Access:RW   DataWidth:0x1    // Soft reset - reset all FSM.
+#define PRS_REG_MAC_VLAN_CACHE_INIT                                                                          0x1f0004UL //Access:W    DataWidth:0x1    // Any write to this register triggers MAC-VLAN Cache initialization.
+#define PRS_REG_MAC_VLAN_CACHE_INIT_DONE                                                                     0x1f0008UL //Access:R    DataWidth:0x1    // Set when the cache initialization is complete.
+#define PRS_REG_CAM_SCRUB_HIT_EN                                                                             0x1f000cUL //Access:RW   DataWidth:0x1    // When set to 1 the cam hit parity scrubbing feature is enabled in the MAC/VLAN cache CAM.
+#define PRS_REG_CAM_SCRUB_MISS_EN                                                                            0x1f0010UL //Access:RW   DataWidth:0x1    // When set to 1 the cam miss parity scrubbing feature is enabled in the MAC/VLAN cache CAM.
+#define PRS_REG_INT_STS_0                                                                                    0x1f0040UL //Access:R    DataWidth:0x2    // Multi Field Register.
+  #define PRS_REG_INT_STS_0_ADDRESS_ERROR                                                                    (0x1<<0) // Signals an unknown address to the rf module.
+  #define PRS_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                              0
+  #define PRS_REG_INT_STS_0_LCID_VALIDATION_ERR                                                              (0x1<<1) // Load Request Mini-cache validation error
+  #define PRS_REG_INT_STS_0_LCID_VALIDATION_ERR_SHIFT                                                        1
+#define PRS_REG_INT_MASK_0                                                                                   0x1f0044UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PRS_REG_INT_MASK_0_ADDRESS_ERROR                                                                   (0x1<<0) // This bit masks, when set, the Interrupt bit: PRS_REG_INT_STS_0.ADDRESS_ERROR .
+  #define PRS_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                             0
+  #define PRS_REG_INT_MASK_0_LCID_VALIDATION_ERR                                                             (0x1<<1) // This bit masks, when set, the Interrupt bit: PRS_REG_INT_STS_0.LCID_VALIDATION_ERR .
+  #define PRS_REG_INT_MASK_0_LCID_VALIDATION_ERR_SHIFT                                                       1
+#define PRS_REG_INT_STS_WR_0                                                                                 0x1f0048UL //Access:WR   DataWidth:0x2    // Multi Field Register.
+  #define PRS_REG_INT_STS_WR_0_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define PRS_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                           0
+  #define PRS_REG_INT_STS_WR_0_LCID_VALIDATION_ERR                                                           (0x1<<1) // Load Request Mini-cache validation error
+  #define PRS_REG_INT_STS_WR_0_LCID_VALIDATION_ERR_SHIFT                                                     1
+#define PRS_REG_INT_STS_CLR_0                                                                                0x1f004cUL //Access:RC   DataWidth:0x2    // Multi Field Register.
+  #define PRS_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define PRS_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                          0
+  #define PRS_REG_INT_STS_CLR_0_LCID_VALIDATION_ERR                                                          (0x1<<1) // Load Request Mini-cache validation error
+  #define PRS_REG_INT_STS_CLR_0_LCID_VALIDATION_ERR_SHIFT                                                    1
+#define PRS_REG_PRTY_MASK                                                                                    0x1f0054UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PRS_REG_PRTY_MASK_CAM_PARITY                                                                       (0x1<<0) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS.CAM_PARITY .
+  #define PRS_REG_PRTY_MASK_CAM_PARITY_SHIFT                                                                 0
+  #define PRS_REG_PRTY_MASK_GFT_CAM_PARITY                                                                   (0x1<<1) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS.GFT_CAM_PARITY .
+  #define PRS_REG_PRTY_MASK_GFT_CAM_PARITY_SHIFT                                                             1
+#define PRS_REG_TASK_INC_VALUE                                                                               0x1f0140UL //Access:RW   DataWidth:0x8    // The increment value to send in the TCFC load request message.
+#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE                                                                   0x1f0164UL //Access:RW   DataWidth:0x4    // Search response connection type for an FCoE initiator connection.
+#define PRS_REG_TASK_ID_MAX_INITIATOR_PF                                                                     0x1f0168UL //Access:RW   DataWidth:0x10   // Per-PF: If OX_ID exceeds this value on a PF packet, task-id-not-in-range is set.
+#define PRS_REG_TASK_ID_MAX_INITIATOR_VF                                                                     0x1f016cUL //Access:RW   DataWidth:0x10   // Per-PF: If OX_ID exceeds this value on a VF packet, task-id-not-in-range is set.
+#define PRS_REG_TASK_ID_MAX_TARGET_PF                                                                        0x1f0170UL //Access:RW   DataWidth:0x10   // Per-PF: If RX_ID exceeds this value on a PF packet, task-id-not-in-range is set.
+#define PRS_REG_TASK_ID_MAX_TARGET_VF                                                                        0x1f0174UL //Access:RW   DataWidth:0x10   // Per-PF: If RX_ID exceeds this value on a VF packet, task-id-not-in-range is set.
+#define PRS_REG_TASK_ID_SEGMENT                                                                              0x1f0178UL //Access:RW   DataWidth:0x2    // Part of the task_ID calculation for FCoE.
+#define PRS_REG_TASK_REGIONS_INITIATOR                                                                       0x1f017cUL //Access:RW   DataWidth:0x8    // Context region used in TCFC load requests for initiator mode.
+#define PRS_REG_TASK_REGIONS_TARGET                                                                          0x1f0180UL //Access:RW   DataWidth:0x8    // Context region used in TCFC load requests for target mode.
+#define PRS_REG_TASK_TYPE_INITIATOR                                                                          0x1f0184UL //Access:RW   DataWidth:0x4    // Connection type used in TCFC load requests for initiator mode.
+#define PRS_REG_TASK_TYPE_TARGET                                                                             0x1f0188UL //Access:RW   DataWidth:0x4    // Connection type used in TCFC load requests for target mode.
+#define PRS_REG_ROCE_CON_TYPE                                                                                0x1f018cUL //Access:RW   DataWidth:0x4    // Connection type to be used in RoCE load requests.
+#define PRS_REG_ROCE_SEPARATE_RX_TX_CID_FLG                                                                  0x1f0190UL //Access:RW   DataWidth:0x1    // Per-PF: If set, override of the CID LSb is enabled for RoCE packets.
+#define PRS_REG_ROCE_OPCODE_REQ_RES                                                                          0x1f0194UL //Access:RW   DataWidth:0x20   // Per-opcode requester/responder bit to be used in the CID of RoCE pkts (if enabled in roce_separate_rx_tx_cid_flg).
+#define PRS_REG_LOAD_L2_FILTER                                                                               0x1f0198UL //Access:RW   DataWidth:0x1    // Per-PF: If set, a load request is sent for TCP, UDP, and RoCE packets receiving a search response result code of match L2 filter.
+#define PRS_REG_CFC_LOAD_MINI_CACHE_EN                                                                       0x1f019cUL //Access:RW   DataWidth:0x1    // If set, CFC load mini-cache is enabled.
+#define PRS_REG_TARGET_INITIATOR_SELECT                                                                      0x1f01a0UL //Access:RW   DataWidth:0x1    // 0-search response initiator type,1-Exchange Context
+#define PRS_REG_FCOE_SEARCH_WITH_EXCHANGE_CONTEXT                                                            0x1f01a4UL //Access:RW   DataWidth:0x1    // 0-Exchange Context field in the fcoe search req is zero. 1-Exchange context field in the FCoE search request is taken from the F_CTL field of the FC header.
+#define PRS_REG_ECO_RESERVED                                                                                 0x1f0200UL //Access:RW   DataWidth:0x20   // Debug only: Reserved bits for ECO.
+#define PRS_REG_PRTY_MASK_H_0_BB_K2                                                                          0x1f0208UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define PRS_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT_K2                                                       (0x1<<0) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM011_I_ECC_RF_INT .
+  #define PRS_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT_K2_SHIFT                                                 0
+  #define PRS_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_K2                                                       (0x1<<1) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM012_I_ECC_RF_INT .
+  #define PRS_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_K2_SHIFT                                                 1
+  #define PRS_REG_PRTY_MASK_H_0_MEM016_I_ECC_RF_INT_K2                                                       (0x1<<2) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM016_I_ECC_RF_INT .
+  #define PRS_REG_PRTY_MASK_H_0_MEM016_I_ECC_RF_INT_K2_SHIFT                                                 2
+  #define PRS_REG_PRTY_MASK_H_0_MEM017_I_ECC_RF_INT_K2                                                       (0x1<<3) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM017_I_ECC_RF_INT .
+  #define PRS_REG_PRTY_MASK_H_0_MEM017_I_ECC_RF_INT_K2_SHIFT                                                 3
+  #define PRS_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT_K2                                                       (0x1<<4) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM021_I_ECC_RF_INT .
+  #define PRS_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT_K2_SHIFT                                                 4
+  #define PRS_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT_K2                                                       (0x1<<5) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM022_I_ECC_RF_INT .
+  #define PRS_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT_K2_SHIFT                                                 5
+  #define PRS_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_K2                                                       (0x1<<6) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM026_I_ECC_RF_INT .
+  #define PRS_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_K2_SHIFT                                                 6
+  #define PRS_REG_PRTY_MASK_H_0_MEM027_I_ECC_RF_INT_K2                                                       (0x1<<7) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM027_I_ECC_RF_INT .
+  #define PRS_REG_PRTY_MASK_H_0_MEM027_I_ECC_RF_INT_K2_SHIFT                                                 7
+  #define PRS_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY_K2                                                         (0x1<<8) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM064_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY_K2_SHIFT                                                   8
+  #define PRS_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY_K2                                                         (0x1<<9) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM044_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY_K2_SHIFT                                                   9
+  #define PRS_REG_PRTY_MASK_H_0_MEM043_I_MEM_PRTY_K2                                                         (0x1<<10) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM043_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM043_I_MEM_PRTY_K2_SHIFT                                                   10
+  #define PRS_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_BB                                                         (0x1<<4) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_BB_SHIFT                                                   4
+  #define PRS_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_K2                                                         (0x1<<11) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_K2_SHIFT                                                   11
+  #define PRS_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_BB                                                         (0x1<<25) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_BB_SHIFT                                                   25
+  #define PRS_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_K2                                                         (0x1<<12) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_K2_SHIFT                                                   12
+  #define PRS_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB                                                         (0x1<<16) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_SHIFT                                                   16
+  #define PRS_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_K2                                                         (0x1<<13) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_K2_SHIFT                                                   13
+  #define PRS_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_BB                                                         (0x1<<17) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_BB_SHIFT                                                   17
+  #define PRS_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_K2                                                         (0x1<<14) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_K2_SHIFT                                                   14
+  #define PRS_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_K2                                                         (0x1<<15) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_K2_SHIFT                                                   15
+  #define PRS_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB                                                         (0x1<<29) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_SHIFT                                                   29
+  #define PRS_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2                                                         (0x1<<16) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2_SHIFT                                                   16
+  #define PRS_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB                                                         (0x1<<30) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_SHIFT                                                   30
+  #define PRS_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2                                                         (0x1<<17) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2_SHIFT                                                   17
+  #define PRS_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_K2                                                         (0x1<<18) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_K2_SHIFT                                                   18
+  #define PRS_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB                                                         (0x1<<24) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_SHIFT                                                   24
+  #define PRS_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_K2                                                         (0x1<<19) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_K2_SHIFT                                                   19
+  #define PRS_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB                                                         (0x1<<18) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_SHIFT                                                   18
+  #define PRS_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2                                                         (0x1<<20) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_SHIFT                                                   20
+  #define PRS_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB                                                         (0x1<<28) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_SHIFT                                                   28
+  #define PRS_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2                                                         (0x1<<21) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2_SHIFT                                                   21
+  #define PRS_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_K2                                                         (0x1<<22) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_K2_SHIFT                                                   22
+  #define PRS_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_K2                                                         (0x1<<23) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM040_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_K2_SHIFT                                                   23
+  #define PRS_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY_K2                                                         (0x1<<24) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM058_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY_K2_SHIFT                                                   24
+  #define PRS_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_K2                                                         (0x1<<25) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM059_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_K2_SHIFT                                                   25
+  #define PRS_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY_K2                                                         (0x1<<26) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM041_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY_K2_SHIFT                                                   26
+  #define PRS_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY_K2                                                         (0x1<<27) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM042_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY_K2_SHIFT                                                   27
+  #define PRS_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_K2                                                         (0x1<<28) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM060_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_K2_SHIFT                                                   28
+  #define PRS_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_K2                                                         (0x1<<29) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM061_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_K2_SHIFT                                                   29
+  #define PRS_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2                                                         (0x1<<30) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2_SHIFT                                                   30
+  #define PRS_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_BB                                                       (0x1<<0) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM009_I_ECC_RF_INT .
+  #define PRS_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_BB_SHIFT                                                 0
+  #define PRS_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT_BB                                                       (0x1<<1) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM010_I_ECC_RF_INT .
+  #define PRS_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT_BB_SHIFT                                                 1
+  #define PRS_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_BB                                                       (0x1<<2) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM014_I_ECC_RF_INT .
+  #define PRS_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_BB_SHIFT                                                 2
+  #define PRS_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_BB                                                       (0x1<<3) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM015_I_ECC_RF_INT .
+  #define PRS_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_BB_SHIFT                                                 3
+  #define PRS_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB                                                         (0x1<<5) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_SHIFT                                                   5
+  #define PRS_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB                                                         (0x1<<6) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB_SHIFT                                                   6
+  #define PRS_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB                                                         (0x1<<7) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB_SHIFT                                                   7
+  #define PRS_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB                                                         (0x1<<8) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_SHIFT                                                   8
+  #define PRS_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB                                                         (0x1<<9) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_SHIFT                                                   9
+  #define PRS_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB                                                         (0x1<<10) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_SHIFT                                                   10
+  #define PRS_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB                                                         (0x1<<11) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_SHIFT                                                   11
+  #define PRS_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB                                                         (0x1<<12) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_SHIFT                                                   12
+  #define PRS_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB                                                         (0x1<<13) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_SHIFT                                                   13
+  #define PRS_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB                                                         (0x1<<14) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_SHIFT                                                   14
+  #define PRS_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB                                                         (0x1<<15) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB_SHIFT                                                   15
+  #define PRS_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB                                                         (0x1<<19) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_SHIFT                                                   19
+  #define PRS_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB                                                         (0x1<<20) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_SHIFT                                                   20
+  #define PRS_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB                                                         (0x1<<21) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_SHIFT                                                   21
+  #define PRS_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB                                                         (0x1<<22) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_SHIFT                                                   22
+  #define PRS_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB                                                         (0x1<<23) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_SHIFT                                                   23
+  #define PRS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB                                                         (0x1<<26) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_SHIFT                                                   26
+  #define PRS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB                                                         (0x1<<27) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_SHIFT                                                   27
+#define PRS_REG_PRTY_MASK_H_1_BB_K2                                                                          0x1f0218UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define PRS_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_K2                                                         (0x1<<0) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_K2_SHIFT                                                   0
+  #define PRS_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_K2                                                         (0x1<<1) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_K2_SHIFT                                                   1
+  #define PRS_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_K2                                                         (0x1<<2) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_K2_SHIFT                                                   2
+  #define PRS_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_K2                                                         (0x1<<3) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM019_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_K2_SHIFT                                                   3
+  #define PRS_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_K2                                                         (0x1<<4) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM020_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_K2_SHIFT                                                   4
+  #define PRS_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_K2                                                         (0x1<<5) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM024_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_K2_SHIFT                                                   5
+  #define PRS_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_K2                                                         (0x1<<6) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM025_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_K2_SHIFT                                                   6
+  #define PRS_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_K2                                                         (0x1<<7) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_K2_SHIFT                                                   7
+  #define PRS_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_K2                                                         (0x1<<8) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_K2_SHIFT                                                   8
+  #define PRS_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_K2                                                         (0x1<<9) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM018_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_K2_SHIFT                                                   9
+  #define PRS_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY_K2                                                         (0x1<<10) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM023_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY_K2_SHIFT                                                   10
+  #define PRS_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY_K2                                                         (0x1<<11) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM054_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY_K2_SHIFT                                                   11
+  #define PRS_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_K2                                                         (0x1<<12) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM055_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_K2_SHIFT                                                   12
+  #define PRS_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY_K2                                                         (0x1<<13) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM056_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY_K2_SHIFT                                                   13
+  #define PRS_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_K2                                                         (0x1<<14) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM057_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_K2_SHIFT                                                   14
+  #define PRS_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY_K2                                                         (0x1<<15) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM003_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY_K2_SHIFT                                                   15
+  #define PRS_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_K2                                                         (0x1<<16) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM004_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_K2_SHIFT                                                   16
+  #define PRS_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY_K2                                                         (0x1<<17) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM005_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY_K2_SHIFT                                                   17
+  #define PRS_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_K2                                                         (0x1<<18) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_K2_SHIFT                                                   18
+  #define PRS_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY_K2                                                         (0x1<<19) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM046_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY_K2_SHIFT                                                   19
+  #define PRS_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_K2                                                         (0x1<<20) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM047_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_K2_SHIFT                                                   20
+  #define PRS_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_K2                                                         (0x1<<21) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM048_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_K2_SHIFT                                                   21
+  #define PRS_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_K2                                                         (0x1<<22) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM049_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_K2_SHIFT                                                   22
+  #define PRS_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_K2                                                         (0x1<<23) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_K2_SHIFT                                                   23
+  #define PRS_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_K2                                                         (0x1<<24) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM051_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_K2_SHIFT                                                   24
+  #define PRS_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_K2                                                         (0x1<<25) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_K2_SHIFT                                                   25
+  #define PRS_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_K2                                                         (0x1<<26) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM053_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_K2_SHIFT                                                   26
+  #define PRS_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY_K2                                                         (0x1<<27) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM062_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY_K2_SHIFT                                                   27
+  #define PRS_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY_K2                                                         (0x1<<28) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM045_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY_K2_SHIFT                                                   28
+  #define PRS_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB                                                         (0x1<<3) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_SHIFT                                                   3
+  #define PRS_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2                                                         (0x1<<29) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2_SHIFT                                                   29
+  #define PRS_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB                                                         (0x1<<4) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_SHIFT                                                   4
+  #define PRS_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2                                                         (0x1<<30) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2_SHIFT                                                   30
+  #define PRS_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_BB                                                         (0x1<<0) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM031_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_BB_SHIFT                                                   0
+  #define PRS_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_BB                                                         (0x1<<1) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_BB_SHIFT                                                   1
+  #define PRS_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_BB                                                         (0x1<<2) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM027_I_MEM_PRTY .
+  #define PRS_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_BB_SHIFT                                                   2
+#define PRS_REG_MEM_ECC_ENABLE_0_BB_K2                                                                       0x1f0224UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PRS_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_EN_K2                                                        (0x1<<0) // Enable ECC for memory ecc instance prs.i_msgb_if0_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_EN_K2_SHIFT                                                  0
+  #define PRS_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN_K2                                                        (0x1<<1) // Enable ECC for memory ecc instance prs.i_msgb_if0_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN_K2_SHIFT                                                  1
+  #define PRS_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_EN_K2                                                        (0x1<<2) // Enable ECC for memory ecc instance prs.i_msgb_if1_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_EN_K2_SHIFT                                                  2
+  #define PRS_REG_MEM_ECC_ENABLE_0_MEM017_I_ECC_EN_K2                                                        (0x1<<3) // Enable ECC for memory ecc instance prs.i_msgb_if1_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_ENABLE_0_MEM017_I_ECC_EN_K2_SHIFT                                                  3
+  #define PRS_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_EN_K2                                                        (0x1<<4) // Enable ECC for memory ecc instance prs.i_msgb_if2_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_EN_K2_SHIFT                                                  4
+  #define PRS_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_EN_K2                                                        (0x1<<5) // Enable ECC for memory ecc instance prs.i_msgb_if2_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_EN_K2_SHIFT                                                  5
+  #define PRS_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_EN_K2                                                        (0x1<<6) // Enable ECC for memory ecc instance prs.i_msgb_if3_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_EN_K2_SHIFT                                                  6
+  #define PRS_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_EN_K2                                                        (0x1<<7) // Enable ECC for memory ecc instance prs.i_msgb_if3_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_EN_K2_SHIFT                                                  7
+  #define PRS_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_EN_BB                                                        (0x1<<0) // Enable ECC for memory ecc instance prs.i_msgb_if0_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_EN_BB_SHIFT                                                  0
+  #define PRS_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_EN_BB                                                        (0x1<<1) // Enable ECC for memory ecc instance prs.i_msgb_if0_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_EN_BB_SHIFT                                                  1
+  #define PRS_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN_BB                                                        (0x1<<2) // Enable ECC for memory ecc instance prs.i_msgb_if1_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN_BB_SHIFT                                                  2
+  #define PRS_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN_BB                                                        (0x1<<3) // Enable ECC for memory ecc instance prs.i_msgb_if1_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN_BB_SHIFT                                                  3
+#define PRS_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                  0x1f0228UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_PRTY_K2                                                 (0x1<<0) // Set parity only for memory ecc instance prs.i_msgb_if0_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_PRTY_K2_SHIFT                                           0
+  #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY_K2                                                 (0x1<<1) // Set parity only for memory ecc instance prs.i_msgb_if0_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY_K2_SHIFT                                           1
+  #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_PRTY_K2                                                 (0x1<<2) // Set parity only for memory ecc instance prs.i_msgb_if1_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_PRTY_K2_SHIFT                                           2
+  #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM017_I_ECC_PRTY_K2                                                 (0x1<<3) // Set parity only for memory ecc instance prs.i_msgb_if1_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM017_I_ECC_PRTY_K2_SHIFT                                           3
+  #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_PRTY_K2                                                 (0x1<<4) // Set parity only for memory ecc instance prs.i_msgb_if2_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_PRTY_K2_SHIFT                                           4
+  #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_PRTY_K2                                                 (0x1<<5) // Set parity only for memory ecc instance prs.i_msgb_if2_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_PRTY_K2_SHIFT                                           5
+  #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_PRTY_K2                                                 (0x1<<6) // Set parity only for memory ecc instance prs.i_msgb_if3_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_PRTY_K2_SHIFT                                           6
+  #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_PRTY_K2                                                 (0x1<<7) // Set parity only for memory ecc instance prs.i_msgb_if3_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_PRTY_K2_SHIFT                                           7
+  #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_PRTY_BB                                                 (0x1<<0) // Set parity only for memory ecc instance prs.i_msgb_if0_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_PRTY_BB_SHIFT                                           0
+  #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_PRTY_BB                                                 (0x1<<1) // Set parity only for memory ecc instance prs.i_msgb_if0_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_PRTY_BB_SHIFT                                           1
+  #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY_BB                                                 (0x1<<2) // Set parity only for memory ecc instance prs.i_msgb_if1_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY_BB_SHIFT                                           2
+  #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY_BB                                                 (0x1<<3) // Set parity only for memory ecc instance prs.i_msgb_if1_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY_BB_SHIFT                                           3
+#define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                              0x1f022cUL //Access:RC   DataWidth:0x8    // Multi Field Register.
+  #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_CORRECT_K2                                          (0x1<<0) // Record if a correctable error occurred on memory ecc instance prs.i_msgb_if0_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_CORRECT_K2_SHIFT                                    0
+  #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT_K2                                          (0x1<<1) // Record if a correctable error occurred on memory ecc instance prs.i_msgb_if0_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT_K2_SHIFT                                    1
+  #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_CORRECT_K2                                          (0x1<<2) // Record if a correctable error occurred on memory ecc instance prs.i_msgb_if1_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_CORRECT_K2_SHIFT                                    2
+  #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM017_I_ECC_CORRECT_K2                                          (0x1<<3) // Record if a correctable error occurred on memory ecc instance prs.i_msgb_if1_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM017_I_ECC_CORRECT_K2_SHIFT                                    3
+  #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_CORRECT_K2                                          (0x1<<4) // Record if a correctable error occurred on memory ecc instance prs.i_msgb_if2_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_CORRECT_K2_SHIFT                                    4
+  #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_CORRECT_K2                                          (0x1<<5) // Record if a correctable error occurred on memory ecc instance prs.i_msgb_if2_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_CORRECT_K2_SHIFT                                    5
+  #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM026_I_ECC_CORRECT_K2                                          (0x1<<6) // Record if a correctable error occurred on memory ecc instance prs.i_msgb_if3_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM026_I_ECC_CORRECT_K2_SHIFT                                    6
+  #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_CORRECT_K2                                          (0x1<<7) // Record if a correctable error occurred on memory ecc instance prs.i_msgb_if3_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_CORRECT_K2_SHIFT                                    7
+  #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_CORRECT_BB                                          (0x1<<0) // Record if a correctable error occurred on memory ecc instance prs.i_msgb_if0_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_CORRECT_BB_SHIFT                                    0
+  #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_CORRECT_BB                                          (0x1<<1) // Record if a correctable error occurred on memory ecc instance prs.i_msgb_if0_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_CORRECT_BB_SHIFT                                    1
+  #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT_BB                                          (0x1<<2) // Record if a correctable error occurred on memory ecc instance prs.i_msgb_if1_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT_BB_SHIFT                                    2
+  #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT_BB                                          (0x1<<3) // Record if a correctable error occurred on memory ecc instance prs.i_msgb_if1_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
+  #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT_BB_SHIFT                                    3
+#define PRS_REG_MEM_ECC_EVENTS_BB_K2                                                                         0x1f0230UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define PRS_REG_SEARCH_TCP                                                                                   0x1f0400UL //Access:RW   DataWidth:0x1    // Per-PF: Flag enabling searches for tcp protocol.
+#define PRS_REG_SEARCH_UDP                                                                                   0x1f0404UL //Access:RW   DataWidth:0x1    // Per-PF: Flag enabling searches for udp protocol.
+#define PRS_REG_SEARCH_FCOE                                                                                  0x1f0408UL //Access:RW   DataWidth:0x1    // Per-PF: Flag enabling searches for fcoe protocol.
+#define PRS_REG_SEARCH_ROCE                                                                                  0x1f040cUL //Access:RW   DataWidth:0x1    // Per-PF: Flag enabling searches for roce protocol.
+#define PRS_REG_SEARCH_TCP_FIRST_FRAG                                                                        0x1f0410UL //Access:RW   DataWidth:0x1    // Enables sending messages to CFC on received first TCP fragmented packets.
+#define PRS_REG_TCP_SEARCH_KEY_MASK                                                                          0x1f0414UL //Access:RW   DataWidth:0x7    // Multi Field Register.
+  #define PRS_REG_TCP_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV4                                                   (0x1<<0) // If this bit is 0, the dest_ip_address_ipv4 field will be masked in the TCP search request.
+  #define PRS_REG_TCP_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV4_SHIFT                                             0
+  #define PRS_REG_TCP_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV6                                                   (0x1<<1) // If this bit is 0, the dest_ip_address_ipv6 field will be masked in the TCP search request.
+  #define PRS_REG_TCP_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV6_SHIFT                                             1
+  #define PRS_REG_TCP_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV4                                                 (0x1<<2) // If this bit is 0, the source_ip_address_ipv4 field will be masked in the TCP search request.
+  #define PRS_REG_TCP_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV4_SHIFT                                           2
+  #define PRS_REG_TCP_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV6                                                 (0x1<<3) // If this bit is 0, the source_ip_address_ipv6 field will be masked in the TCP search request.
+  #define PRS_REG_TCP_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV6_SHIFT                                           3
+  #define PRS_REG_TCP_SEARCH_KEY_MASK_TCP_DEST_PORT                                                          (0x1<<4) // If this bit is 0, the tcp_dest_port field will be masked in the TCP search request.
+  #define PRS_REG_TCP_SEARCH_KEY_MASK_TCP_DEST_PORT_SHIFT                                                    4
+  #define PRS_REG_TCP_SEARCH_KEY_MASK_TCP_SOURCE_PORT                                                        (0x1<<5) // If this bit is 0, the tcp_source_port field will be masked in the TCP search request.
+  #define PRS_REG_TCP_SEARCH_KEY_MASK_TCP_SOURCE_PORT_SHIFT                                                  5
+  #define PRS_REG_TCP_SEARCH_KEY_MASK_IP_VERSION                                                             (0x1<<6) // If this bit is 0, the ip_version field will be masked in the TCP search request.
+  #define PRS_REG_TCP_SEARCH_KEY_MASK_IP_VERSION_SHIFT                                                       6
+#define PRS_REG_UDP_SEARCH_KEY_MASK                                                                          0x1f0418UL //Access:RW   DataWidth:0x7    // Multi Field Register.
+  #define PRS_REG_UDP_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV4                                                   (0x1<<0) // If this bit is 0, the dest_ip_address_ipv4 field will be masked in the UDP search request.
+  #define PRS_REG_UDP_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV4_SHIFT                                             0
+  #define PRS_REG_UDP_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV6                                                   (0x1<<1) // If this bit is 0, the dest_ip_address_ipv6 field will be masked in the UDP search request.
+  #define PRS_REG_UDP_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV6_SHIFT                                             1
+  #define PRS_REG_UDP_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV4                                                 (0x1<<2) // If this bit is 0, the source_ip_address_ipv4 field will be masked in the UDP search request.
+  #define PRS_REG_UDP_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV4_SHIFT                                           2
+  #define PRS_REG_UDP_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV6                                                 (0x1<<3) // If this bit is 0, the source_ip_address_ipv6 field will be masked in the UDP search request.
+  #define PRS_REG_UDP_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV6_SHIFT                                           3
+  #define PRS_REG_UDP_SEARCH_KEY_MASK_UDP_DEST_PORT                                                          (0x1<<4) // If this bit is 0, the udp_dest_port field will be masked in the UDP search request.
+  #define PRS_REG_UDP_SEARCH_KEY_MASK_UDP_DEST_PORT_SHIFT                                                    4
+  #define PRS_REG_UDP_SEARCH_KEY_MASK_UDP_SOURCE_PORT                                                        (0x1<<5) // If this bit is 0, the udp_source_port field will be masked in the UDP search request.
+  #define PRS_REG_UDP_SEARCH_KEY_MASK_UDP_SOURCE_PORT_SHIFT                                                  5
+  #define PRS_REG_UDP_SEARCH_KEY_MASK_IP_VERSION                                                             (0x1<<6) // If this bit is 0, the ip_version field will be masked in the UDP search request.
+  #define PRS_REG_UDP_SEARCH_KEY_MASK_IP_VERSION_SHIFT                                                       6
+#define PRS_REG_SEARCH_FCOE_W_SRC_MAC                                                                        0x1f041cUL //Access:RW   DataWidth:0x1    // Per-PF: If set, search requests on FCoE packets are only sent if source MAC address compare matches.
+#define PRS_REG_SEARCH_FCOE_W_VFT                                                                            0x1f0420UL //Access:RW   DataWidth:0x1    // Per-PF: Enables VF_ID (if it exists) to be sent in search requests for FCoE packets.
+#define PRS_REG_ROCE_BUILD_CID_WO_SEARCH                                                                     0x1f0424UL //Access:RW   DataWidth:0x1    // Per-PF: Enables load request for RoCE pkts to be sent even though a search request was not sent
+#define PRS_REG_ROCE_SPCL_QP_VAL                                                                             0x1f0428UL //Access:RW   DataWidth:0x18   // Search is enabled if destination QP equals this value.
+#define PRS_REG_ROCE_DEST_QP_MAX_VF                                                                          0x1f042cUL //Access:RW   DataWidth:0x10   // Per-PF: Max value for temp_qpid used in RoCE CID equation for VF pkts.
+#define PRS_REG_ROCE_DEST_QP_MAX_PF                                                                          0x1f0430UL //Access:RW   DataWidth:0x10   // Per-PF: Max value for temp_qpid used in RoCE CID equation for PF pkts.
+#define PRS_REG_SEARCH_OPENFLOW                                                                              0x1f0434UL //Access:RW   DataWidth:0x1    // Per-PF: Enables openflow search for all packet types.
+#define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW                                                                    0x1f0438UL //Access:RW   DataWidth:0x1    // Per-PF: Enables openflow search for non-IP packets. Only valid if search_openflow is also set.
+#define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP                                                          0x1f043cUL //Access:RW   DataWidth:0x1    // Per-PF: If this field is 1, Over-IPv4-protocol field of Openflow search is only valid for SCTP, TCP, and UDP headers.
+#define PRS_REG_OPENFLOW_SEARCH_KEY_MASK                                                                     0x1f0440UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_TCP_SOURCE_PORT                                                   (0x1<<0) // If this bit is 0, the tcp_source_port field will be masked in the Openflow search request.
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_TCP_SOURCE_PORT_SHIFT                                             0
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_UDP_SOURCE_PORT                                                   (0x1<<1) // If this bit is 0, the udp_source_port field will be masked in the Openflow search request.
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_UDP_SOURCE_PORT_SHIFT                                             1
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SCTP_SOURCE_PORT                                                  (0x1<<2) // If this bit is 0, the sctp_source_port field will be masked in the Openflow search request.
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SCTP_SOURCE_PORT_SHIFT                                            2
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_ICMP_TYPE                                                         (0x1<<3) // If this bit is 0, the icmp_type field will be masked in the Openflow search request.
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_ICMP_TYPE_SHIFT                                                   3
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_TCP_DEST_PORT                                                     (0x1<<4) // If this bit is 0, the tcp_dest_port field will be masked in the Openflow search request.
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_TCP_DEST_PORT_SHIFT                                               4
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_UDP_DEST_PORT                                                     (0x1<<5) // If this bit is 0, the udp_dest_port field will be masked in the Openflow search request.
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_UDP_DEST_PORT_SHIFT                                               5
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SCTP_DEST_PORT                                                    (0x1<<6) // If this bit is 0, the sctp_dest_port field will be masked in the Openflow search request.
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SCTP_DEST_PORT_SHIFT                                              6
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_ICMP_CODE                                                         (0x1<<7) // If this bit is 0, the icmp_code field will be masked in the Openflow search request.
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_ICMP_CODE_SHIFT                                                   7
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_PRIORITY                                                          (0x1<<8) // If this bit is 0, the priority field will be masked in the Openflow search request.
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_PRIORITY_SHIFT                                                    8
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_IPV4_FRAG_TYPE                                                    (0x1<<9) // If this bit is 0, the ipv4_frag_type field will be masked in the Openflow search request.
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_IPV4_FRAG_TYPE_SHIFT                                              9
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_DEST_MAC_ADDRESS                                                  (0x1<<10) // If this bit is 0, the dest_mac_address field will be masked in the Openflow search request.
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_DEST_MAC_ADDRESS_SHIFT                                            10
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_OVER_IPV4_PROTOCOL                                                (0x1<<11) // If this bit is 0, the over_ipv4_protocol field will be masked in the Openflow search request.
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_OVER_IPV4_PROTOCOL_SHIFT                                          11
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_ARP_OPCODE                                                        (0x1<<12) // If this bit is 0, the arp_opcode field will be masked in the Openflow search request.
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_ARP_OPCODE_SHIFT                                                  12
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_IPV4_DSCP                                                         (0x1<<13) // If this bit is 0, the ipv4_dscp field will be masked in the Openflow search request.
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_IPV4_DSCP_SHIFT                                                   13
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SOURCE_MAC_ADDRESS                                                (0x1<<14) // If this bit is 0, the source_mac_address field will be masked in the Openflow search request.
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SOURCE_MAC_ADDRESS_SHIFT                                          14
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV4                                            (0x1<<15) // If this bit is 0, the source_ip_address_ipv4 field will be masked in the Openflow search request.
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV4_SHIFT                                      15
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_ARP                                             (0x1<<16) // If this bit is 0, the source_ip_address_arp field will be masked in the Openflow search request.
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_ARP_SHIFT                                       16
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV4                                              (0x1<<17) // If this bit is 0, the dest_ip_address_ipv4 field will be masked in the Openflow search request.
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV4_SHIFT                                        17
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_DEST_IP_ADDRESS_ARP                                               (0x1<<18) // If this bit is 0, the dest_ip_address_arp field will be masked in the Openflow search request.
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_DEST_IP_ADDRESS_ARP_SHIFT                                         18
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_ETHERTYPE                                                         (0x1<<19) // If this bit is 0, the ethertype field will be masked in the Openflow search request.
+  #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_ETHERTYPE_SHIFT                                                   19
+#define PRS_REG_SEARCH_TAG1                                                                                  0x1f0444UL //Access:RW   DataWidth:0x5    // Per-PF: Indicates whether to include the Inner VLAN in the search for each protocol. 0 - TCP, 1 - UDP, 2 - FCoE, 3 - RoCE, 4 - Openflow- if a bit is set in search_outer_tag it cannot be set here.
+#define PRS_REG_SEARCH_OUTER_TAG                                                                             0x1f0448UL //Access:RW   DataWidth:0x5    // Per-PF: Indicates whether to include the Outer TAG in the search for each protocol. 0 - TCP, 1 - UDP, 2 - FCoE, 3 - RoCE, 4 - Openflow - if a bit is set in search_tag1 it cannot be set here.
+#define PRS_REG_SEARCH_TENANT_ID                                                                             0x1f044cUL //Access:RW   DataWidth:0x6    // Per-PF: Indicates whether to include Tenant ID (if it exists) in the search for each encapsulation type. 0 - L2 GRE, 1 - IP GRE, 2 - VXLAN, 3 - T-Tag, 4 - L2 NGE, 5 - IP NGE
+#define PRS_REG_TENANT_ID_DEFAULT_VAL_ENABLE                                                                 0x1f0450UL //Access:RW   DataWidth:0x6    // Enables Tenant ID Exists bit in the search request to be 0 if the ID matches the default value.  0 - L2 GRE, 1 - IP GRE, 2 - VXLAN, 3 - T-Tag, 4 - L2 NGE, 5 - IP NGE
+#define PRS_REG_TENANT_ID_MASK_ETH_GRE                                                                       0x1f0454UL //Access:RW   DataWidth:0x20   // Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated Ethernet over GRE packet. A zero in this register will mask the corresponding tenant ID bit to 0.
+#define PRS_REG_TENANT_ID_MASK_IP_GRE                                                                        0x1f0458UL //Access:RW   DataWidth:0x20   // Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated IP over GRE packet.. A zero in this register will mask the corresponding tenant ID bit to 0.
+#define PRS_REG_TENANT_ID_MASK_VXLAN                                                                         0x1f045cUL //Access:RW   DataWidth:0x20   // Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated VXLAN packet.. A zero in this register will mask the corresponding tenant ID bit to 0.
+#define PRS_REG_TENANT_ID_MASK_TTAG                                                                          0x1f0460UL //Access:RW   DataWidth:0x20   // Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated T-tag packet.. A zero in this register will mask the corresponding tenant ID bit to 0.
+#define PRS_REG_TENANT_ID_DEFAULT_VAL_ETH_GRE                                                                0x1f0464UL //Access:RW   DataWidth:0x20   // If the Tenant ID exists in the encapsulated Ethernet over GRE packet  and does not match this value the Tenant ID exists bit is set.
+#define PRS_REG_TENANT_ID_DEFAULT_VAL_IP_GRE                                                                 0x1f0468UL //Access:RW   DataWidth:0x20   // If the Tenant ID exists in the encapsulated IP over GRE packet  and does not match this value the Tenant ID exists bit is set.
+#define PRS_REG_TENANT_ID_DEFAULT_VAL_VXLAN                                                                  0x1f046cUL //Access:RW   DataWidth:0x20   // If the Tenant ID exists in the encapsulated VXLAN packet and does not match this value the Tenant ID exists bit is set.
+#define PRS_REG_TENANT_ID_DEFAULT_VAL_TTAG                                                                   0x1f0470UL //Access:RW   DataWidth:0x20   // If the Tenant ID exists in the encapsulated T-Tag packet and does not match this value the Tenant ID exists bit is set.
+#define PRS_REG_T_TAG_TAGNUM                                                                                 0x1f0474UL //Access:RW   DataWidth:0x3    // Per-Port: Specifies the flexible L2 tag to be used for T-tag. The T-tag bit of encapsulation_type_en enables T-tag recognition.
+#define PRS_REG_TENANT_ID_MASK_ETH_NGE                                                                       0x1f0478UL //Access:RW   DataWidth:0x20   // Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated nge packet.. A zero in this register will mask the corresponding tenant ID bit to 0.
+#define PRS_REG_TENANT_ID_MASK_IP_NGE                                                                        0x1f047cUL //Access:RW   DataWidth:0x20   // Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated nge packet.. A zero in this register will mask the corresponding tenant ID bit to 0.
+#define PRS_REG_TENANT_ID_DEFAULT_VAL_ETH_NGE                                                                0x1f0480UL //Access:RW   DataWidth:0x20   // If the Tenant ID exists in the encapsulated ETH NGE packet and does not match this value the Tenant ID exists bit is set.
+#define PRS_REG_TENANT_ID_DEFAULT_VAL_IP_NGE                                                                 0x1f0484UL //Access:RW   DataWidth:0x20   // If the Tenant ID exists in the encapsulated IP NGE packet and does not match this value the Tenant ID exists bit is set.
+#define PRS_REG_PORTS_ARB_SCHEME                                                                             0x1f0500UL //Access:RW   DataWidth:0x1    // MAC port arbitration guarantees fairness at byte-level (0) or packet-level (1).
+#define PRS_REG_MAIN_LB_ARB_SCHEME                                                                           0x1f0504UL //Access:RW   DataWidth:0x1    // Main/LB arbitration guarantees fairness at byte-level (0) or packet-level (1).
+#define PRS_REG_INITIAL_HEADER_SIZE                                                                          0x1f0508UL //Access:RW   DataWidth:0xa    // Initial header size to read from the BRB for received packets.
+#define PRS_REG_MAX_PACKET_SIZE                                                                              0x1f050cUL //Access:RW   DataWidth:0xe    // Maximum packet size used for ETS Arbiter fairness calculation.
+#define PRS_REG_ETS_PACKET_ADDITIONAL_NETWORK_SIZE                                                           0x1f0510UL //Access:RW   DataWidth:0x8    // Size of inter-packet gap and FCS used for ETS Arbiter fairness calculation.
+#define PRS_REG_ETS_ARB_CLIENT_IS_STRICT                                                                     0x1f0514UL //Access:RW   DataWidth:0x9    // Specify whether the client competes directly in the strict priority arbiter.  The bits are mapped according to client ID  (client IDs are defined in *_arb_priority_client): 0-TC0 traffic; 1-TC1 traffic; 2-TC2 traffic; 3-TC3 traffic; 4-TC4 traffic; 5-TC5 traffic; 6-TC6 traffic; 7-TC7 traffic; 8-TC8 traffic.  Default value is set to enable strict priorities for all clients.
+#define PRS_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ                                                                0x1f0518UL //Access:RW   DataWidth:0x9    // Specify whether the client is subject to WFQ credit blocking.  The bits are mapped according to client ID (client IDs are defined in *_arb_priority_client): 0-TC0 traffic; 1-TC1 traffic; 2-TC2 traffic; 3-TC3 traffic; 4-TC4 traffic; 5-TC5 traffic; 6-TC6 traffic; 7-TC7 traffic; 8-TC8 traffic.  Default value is 0 for not using WFQ credit blocking.
+#define PRS_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS                                                                 0x1f051cUL //Access:RW   DataWidth:0xc    // Specify the number of strict priority arbitration slots between two round-robin arbitration slots to avoid starvation.  A value of 0 means no strict priority cycles - the strict priority with anti-starvation arbiter becomes a round-robin arbiter.
+#define PRS_REG_ETS_ARB_PRIORITY_CLIENT_0                                                                    0x1f0520UL //Access:RW   DataWidth:0x20   // Specify the client number to be assigned to each priority of the strict priority arbiter.  Priority 0 is the highest priority.  Bits [3:0] are for priority 0 client; upper bits are for priority 8 client.  The clients are assigned the IDs corresponding to their TC # (0-8)
+#define PRS_REG_ETS_ARB_PRIORITY_CLIENT_1                                                                    0x1f0524UL //Access:RW   DataWidth:0x4    // Specify the client number to be assigned to each priority of the strict priority arbiter.  Priority 0 is the highest priority.  Bits [3:0] are for priority 0 client; upper bits are for priority 8 client.  The clients are assigned the IDs corresponding to their TC # (0-8)
+#define PRS_REG_ETS_ARB_CLIENT_BURSTMODE                                                                     0x1f0528UL //Access:RW   DataWidth:0x2    // Burst mode enables.  Set these bits to have the round-robin arbiter stays on the winning input instead of moving to the next one.  Bit 0 is for the main round-robin arbiter.  Bit 1 is for the round-robin arbiter within the strict priority with anti-starvation feature.
+#define PRS_REG_ETS_ARB_PSEUDO_RR_EN                                                                         0x1f052cUL //Access:RW   DataWidth:0x1    // Enables pseudo-random round robin arbitration.
+#define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_0                                                                 0x1f0530UL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 0 is allowed to reach.
+#define PRS_REG_ETS_ARB_CREDIT_WEIGHT_0                                                                      0x1f0534UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 0 when it is time to increment.
+#define PRS_REG_ETS_ARB_CURRENT_CREDIT_0                                                                     0x1f0538UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register 0.
+#define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_1                                                                 0x1f053cUL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 1 is allowed to reach.
+#define PRS_REG_ETS_ARB_CREDIT_WEIGHT_1                                                                      0x1f0540UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 1 when it is time to increment.
+#define PRS_REG_ETS_ARB_CURRENT_CREDIT_1                                                                     0x1f0544UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register 1.
+#define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_2                                                                 0x1f0548UL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 2 is allowed to reach.
+#define PRS_REG_ETS_ARB_CREDIT_WEIGHT_2                                                                      0x1f054cUL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 2 when it is time to increment.
+#define PRS_REG_ETS_ARB_CURRENT_CREDIT_2                                                                     0x1f0550UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register 2.
+#define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_3                                                                 0x1f0554UL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 3 is allowed to reach.
+#define PRS_REG_ETS_ARB_CREDIT_WEIGHT_3                                                                      0x1f0558UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 3 when it is time to increment.
+#define PRS_REG_ETS_ARB_CURRENT_CREDIT_3                                                                     0x1f055cUL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register 3.
+#define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_4                                                                 0x1f0560UL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 4 is allowed to reach.
+#define PRS_REG_ETS_ARB_CREDIT_WEIGHT_4                                                                      0x1f0564UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 4 when it is time to increment.
+#define PRS_REG_ETS_ARB_CURRENT_CREDIT_4                                                                     0x1f0568UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register 4.
+#define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_5                                                                 0x1f056cUL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 5 is allowed to reach.
+#define PRS_REG_ETS_ARB_CREDIT_WEIGHT_5                                                                      0x1f0570UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 5 when it is time to increment.
+#define PRS_REG_ETS_ARB_CURRENT_CREDIT_5                                                                     0x1f0574UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register 5.
+#define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_6                                                                 0x1f0578UL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 6 is allowed to reach.
+#define PRS_REG_ETS_ARB_CREDIT_WEIGHT_6                                                                      0x1f057cUL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 6 when it is time to increment.
+#define PRS_REG_ETS_ARB_CURRENT_CREDIT_6                                                                     0x1f0580UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register 6.
+#define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_7                                                                 0x1f0584UL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 7 is allowed to reach.
+#define PRS_REG_ETS_ARB_CREDIT_WEIGHT_7                                                                      0x1f0588UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 7 when it is time to increment.
+#define PRS_REG_ETS_ARB_CURRENT_CREDIT_7                                                                     0x1f058cUL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register 7.
+#define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_8                                                                 0x1f0590UL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 8 is allowed to reach.
+#define PRS_REG_ETS_ARB_CREDIT_WEIGHT_8                                                                      0x1f0594UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 8 when it is time to increment.
+#define PRS_REG_ETS_ARB_CURRENT_CREDIT_8                                                                     0x1f0598UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register 8.
+#define PRS_REG_WFQ_MAIN_ARB_CREDIT_UPPER_BOUND_0                                                            0x1f059cUL //Access:RW   DataWidth:0x20   // Specify the upper bound that the credit register is allowed to reach for main traffic on TC 0 during WFQ Main/Loopback arbitration.
+#define PRS_REG_WFQ_MAIN_ARB_CREDIT_WEIGHT_0                                                                 0x1f05a0UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to the credit register for main traffic on TC 0 when it is time to increment during WFQ Main/Loopback arbitration.
+#define PRS_REG_WFQ_MAIN_ARB_CURRENT_CREDIT_0                                                                0x1f05a4UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in the credit register for main traffic on TC 0 during WFQ Main/Loopback arbitration.
+#define PRS_REG_WFQ_LB_ARB_CREDIT_UPPER_BOUND_0                                                              0x1f05a8UL //Access:RW   DataWidth:0x20   // Specify the upper bound that the credit register is allowed to reach for loopback traffic on TC 0 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage
+#define PRS_REG_WFQ_LB_ARB_CREDIT_WEIGHT_0                                                                   0x1f05acUL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to the credit register for loopback traffic on TC 0 when it is time to increment during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage
+#define PRS_REG_WFQ_LB_ARB_CURRENT_CREDIT_0                                                                  0x1f05b0UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register for loopback traffic on TC 0 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage
+#define PRS_REG_WFQ_MAIN_ARB_CREDIT_UPPER_BOUND_1                                                            0x1f05b4UL //Access:RW   DataWidth:0x20   // Specify the upper bound that the credit register is allowed to reach for main traffic on TC 1 during WFQ Main/Loopback arbitration.
+#define PRS_REG_WFQ_MAIN_ARB_CREDIT_WEIGHT_1                                                                 0x1f05b8UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to the credit register for main traffic on TC 1 when it is time to increment during WFQ Main/Loopback arbitration.
+#define PRS_REG_WFQ_MAIN_ARB_CURRENT_CREDIT_1                                                                0x1f05bcUL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in the credit register for main traffic on TC 1 during WFQ Main/Loopback arbitration.
+#define PRS_REG_WFQ_LB_ARB_CREDIT_UPPER_BOUND_1                                                              0x1f05c0UL //Access:RW   DataWidth:0x20   // Specify the upper bound that the credit register is allowed to reach for loopback traffic on TC 1 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage
+#define PRS_REG_WFQ_LB_ARB_CREDIT_WEIGHT_1                                                                   0x1f05c4UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to the credit register for loopback traffic on TC 1 when it is time to increment during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage
+#define PRS_REG_WFQ_LB_ARB_CURRENT_CREDIT_1                                                                  0x1f05c8UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register for loopback traffic on TC 1 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage
+#define PRS_REG_WFQ_MAIN_ARB_CREDIT_UPPER_BOUND_2                                                            0x1f05ccUL //Access:RW   DataWidth:0x20   // Specify the upper bound that the credit register is allowed to reach for main traffic on TC 2 during WFQ Main/Loopback arbitration.
+#define PRS_REG_WFQ_MAIN_ARB_CREDIT_WEIGHT_2                                                                 0x1f05d0UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to the credit register for main traffic on TC 2 when it is time to increment during WFQ Main/Loopback arbitration.
+#define PRS_REG_WFQ_MAIN_ARB_CURRENT_CREDIT_2                                                                0x1f05d4UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in the credit register for main traffic on TC 2 during WFQ Main/Loopback arbitration.
+#define PRS_REG_WFQ_LB_ARB_CREDIT_UPPER_BOUND_2                                                              0x1f05d8UL //Access:RW   DataWidth:0x20   // Specify the upper bound that the credit register is allowed to reach for loopback traffic on TC 2 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage
+#define PRS_REG_WFQ_LB_ARB_CREDIT_WEIGHT_2                                                                   0x1f05dcUL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to the credit register for loopback traffic on TC 2 when it is time to increment during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage
+#define PRS_REG_WFQ_LB_ARB_CURRENT_CREDIT_2                                                                  0x1f05e0UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register for loopback traffic on TC 2 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage
+#define PRS_REG_WFQ_MAIN_ARB_CREDIT_UPPER_BOUND_3                                                            0x1f05e4UL //Access:RW   DataWidth:0x20   // Specify the upper bound that the credit register is allowed to reach for main traffic on TC 3 during WFQ Main/Loopback arbitration.
+#define PRS_REG_WFQ_MAIN_ARB_CREDIT_WEIGHT_3                                                                 0x1f05e8UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to the credit register for main traffic on TC 3 when it is time to increment during WFQ Main/Loopback arbitration.
+#define PRS_REG_WFQ_MAIN_ARB_CURRENT_CREDIT_3                                                                0x1f05ecUL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in the credit register for main traffic on TC 3 during WFQ Main/Loopback arbitration.
+#define PRS_REG_WFQ_LB_ARB_CREDIT_UPPER_BOUND_3                                                              0x1f05f0UL //Access:RW   DataWidth:0x20   // Specify the upper bound that the credit register is allowed to reach for loopback traffic on TC 3 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage
+#define PRS_REG_WFQ_LB_ARB_CREDIT_WEIGHT_3                                                                   0x1f05f4UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to the credit register for loopback traffic on TC 3 when it is time to increment during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage
+#define PRS_REG_WFQ_LB_ARB_CURRENT_CREDIT_3                                                                  0x1f05f8UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register for loopback traffic on TC 3 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage
+#define PRS_REG_WFQ_MAIN_ARB_CREDIT_UPPER_BOUND_4                                                            0x1f05fcUL //Access:RW   DataWidth:0x20   // Specify the upper bound that the credit register is allowed to reach for main traffic on TC 4 during WFQ Main/Loopback arbitration.
+#define PRS_REG_WFQ_MAIN_ARB_CREDIT_WEIGHT_4                                                                 0x1f0600UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to the credit register for main traffic on TC 4 when it is time to increment during WFQ Main/Loopback arbitration.
+#define PRS_REG_WFQ_MAIN_ARB_CURRENT_CREDIT_4                                                                0x1f0604UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in the credit register for main traffic on TC 4 during WFQ Main/Loopback arbitration.
+#define PRS_REG_WFQ_LB_ARB_CREDIT_UPPER_BOUND_4                                                              0x1f0608UL //Access:RW   DataWidth:0x20   // Specify the upper bound that the credit register is allowed to reach for loopback traffic on TC 4 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage
+#define PRS_REG_WFQ_LB_ARB_CREDIT_WEIGHT_4                                                                   0x1f060cUL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to the credit register for loopback traffic on TC 4 when it is time to increment during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage
+#define PRS_REG_WFQ_LB_ARB_CURRENT_CREDIT_4                                                                  0x1f0610UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register for loopback traffic on TC 4 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage
+#define PRS_REG_WFQ_MAIN_ARB_CREDIT_UPPER_BOUND_5                                                            0x1f0614UL //Access:RW   DataWidth:0x20   // Specify the upper bound that the credit register is allowed to reach for main traffic on TC 5 during WFQ Main/Loopback arbitration.
+#define PRS_REG_WFQ_MAIN_ARB_CREDIT_WEIGHT_5                                                                 0x1f0618UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to the credit register for main traffic on TC 5 when it is time to increment during WFQ Main/Loopback arbitration.
+#define PRS_REG_WFQ_MAIN_ARB_CURRENT_CREDIT_5                                                                0x1f061cUL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in the credit register for main traffic on TC 5 during WFQ Main/Loopback arbitration.
+#define PRS_REG_WFQ_LB_ARB_CREDIT_UPPER_BOUND_5                                                              0x1f0620UL //Access:RW   DataWidth:0x20   // Specify the upper bound that the credit register is allowed to reach for loopback traffic on TC 5 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage
+#define PRS_REG_WFQ_LB_ARB_CREDIT_WEIGHT_5                                                                   0x1f0624UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to the credit register for loopback traffic on TC 5 when it is time to increment during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage
+#define PRS_REG_WFQ_LB_ARB_CURRENT_CREDIT_5                                                                  0x1f0628UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register for loopback traffic on TC 5 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage
+#define PRS_REG_WFQ_MAIN_ARB_CREDIT_UPPER_BOUND_6                                                            0x1f062cUL //Access:RW   DataWidth:0x20   // Specify the upper bound that the credit register is allowed to reach for main traffic on TC 6 during WFQ Main/Loopback arbitration.
+#define PRS_REG_WFQ_MAIN_ARB_CREDIT_WEIGHT_6                                                                 0x1f0630UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to the credit register for main traffic on TC 6 when it is time to increment during WFQ Main/Loopback arbitration.
+#define PRS_REG_WFQ_MAIN_ARB_CURRENT_CREDIT_6                                                                0x1f0634UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in the credit register for main traffic on TC 6 during WFQ Main/Loopback arbitration.
+#define PRS_REG_WFQ_LB_ARB_CREDIT_UPPER_BOUND_6                                                              0x1f0638UL //Access:RW   DataWidth:0x20   // Specify the upper bound that the credit register is allowed to reach for loopback traffic on TC 6 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage
+#define PRS_REG_WFQ_LB_ARB_CREDIT_WEIGHT_6                                                                   0x1f063cUL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to the credit register for loopback traffic on TC 6 when it is time to increment during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage
+#define PRS_REG_WFQ_LB_ARB_CURRENT_CREDIT_6                                                                  0x1f0640UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register for loopback traffic on TC 6 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage
+#define PRS_REG_WFQ_MAIN_ARB_CREDIT_UPPER_BOUND_7                                                            0x1f0644UL //Access:RW   DataWidth:0x20   // Specify the upper bound that the credit register is allowed to reach for main traffic on TC 7 during WFQ Main/Loopback arbitration.
+#define PRS_REG_WFQ_MAIN_ARB_CREDIT_WEIGHT_7                                                                 0x1f0648UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to the credit register for main traffic on TC 7 when it is time to increment during WFQ Main/Loopback arbitration.
+#define PRS_REG_WFQ_MAIN_ARB_CURRENT_CREDIT_7                                                                0x1f064cUL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in the credit register for main traffic on TC 7 during WFQ Main/Loopback arbitration.
+#define PRS_REG_WFQ_LB_ARB_CREDIT_UPPER_BOUND_7                                                              0x1f0650UL //Access:RW   DataWidth:0x20   // Specify the upper bound that the credit register is allowed to reach for loopback traffic on TC 7 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage
+#define PRS_REG_WFQ_LB_ARB_CREDIT_WEIGHT_7                                                                   0x1f0654UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to the credit register for loopback traffic on TC 7 when it is time to increment during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage
+#define PRS_REG_WFQ_LB_ARB_CURRENT_CREDIT_7                                                                  0x1f0658UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register for loopback traffic on TC 7 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage
+#define PRS_REG_WFQ_PORT_ARB_CREDIT_UPPER_BOUND                                                              0x1f065cUL //Access:RW   DataWidth:0x20   // Specify the upper bound that the credit register is allowed to reach for each port during WFQ Port Arbitration.
+#define PRS_REG_WFQ_PORT_ARB_CREDIT_WEIGHT                                                                   0x1f0660UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to the credit register for each port when it is time to increment during WFQ Port arbitration.
+#define PRS_REG_WFQ_PORT_ARB_CURRENT_CREDIT                                                                  0x1f0664UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in the credit register for each port during WFQ Port arbitration.
+#define PRS_REG_PROP_HDR_SIZE                                                                                0x1f0700UL //Access:RW   DataWidth:0x4    // Per-port: Size of the proprietary header for this port (in 4B increments). If proprietary header is disabled this value should be 0.  Legal values for this field are from 0 (disabled) to 8 (32B).
+#define PRS_REG_LLC_TYPE_THRESHOLD                                                                           0x1f0704UL //Access:RW   DataWidth:0x10   // Upper value of LLC Ethertype range.
+#define PRS_REG_LLC_JUMBO_TYPE                                                                               0x1f0708UL //Access:RW   DataWidth:0x10   // Jumbo value of LLC Ethertype.
+#define PRS_REG_GRE_ETH_TYPE                                                                                 0x1f070cUL //Access:RW   DataWidth:0x10   // Ethertype for encapsulated ethernet used in GRE header parsing.
+#define PRS_REG_IPV4_TYPE                                                                                    0x1f0710UL //Access:RW   DataWidth:0x10   // IPv4 Ethertype.
+#define PRS_REG_IPV6_TYPE                                                                                    0x1f0714UL //Access:RW   DataWidth:0x10   // IPv6 Ethertype.
+#define PRS_REG_ROCE_TYPE                                                                                    0x1f0718UL //Access:RW   DataWidth:0x10   // RoCE Ethertype.
+#define PRS_REG_ARP_TYPE                                                                                     0x1f071cUL //Access:RW   DataWidth:0x10   // ARP Ethertype.
+#define PRS_REG_TCP_PROTOCOL                                                                                 0x1f0720UL //Access:RW   DataWidth:0x8    // Value used to designate TCP in the IPv4 Protocol and IPv6 Next Header fields.
+#define PRS_REG_UDP_PROTOCOL                                                                                 0x1f0724UL //Access:RW   DataWidth:0x8    // Value used to designate UDP in the IPv4 Protocol and IPv6 Next Header fields.
+#define PRS_REG_SCTP_PROTOCOL                                                                                0x1f0728UL //Access:RW   DataWidth:0x8    // Value used to designate SCTP in the IPv4 Protocol and IPv6 Next Header fields.  Matching can only occur when sctp_enable is set.
+#define PRS_REG_ICMPV4_PROTOCOL                                                                              0x1f072cUL //Access:RW   DataWidth:0x8    // Value used to designate ICMP in the IPv4 Protocol field. Matching can only occur when icmp_enable is set.
+#define PRS_REG_ENCAPSULATION_TYPE_EN                                                                        0x1f0730UL //Access:RW   DataWidth:0x6    // Per-port:  Flag enabling each encapsulation type. 0 - L2 GRE, 1 - IP GRE, 2 - VXLAN, 3 - T-Tag, 4 - L2 NGE, 5 - IP NGE
+#define PRS_REG_GRE_PROTOCOL                                                                                 0x1f0734UL //Access:RW   DataWidth:0x8    // Value used to designate GRE in the IPv4 Protocol and IPv6 Next Header fields.
+#define PRS_REG_VXLAN_PORT                                                                                   0x1f0738UL //Access:RW   DataWidth:0x10   // Dest port value used to designate a VXLAN header following the UDP header.
+#define PRS_REG_ROCE_ICID_BASE_PF                                                                            0x1f073cUL //Access:RW   DataWidth:0x10   // Per-PF: Base value used in the TID calc during RoCE parsing for PF pkts.
+#define PRS_REG_ROCE_ICID_BASE_VF                                                                            0x1f0740UL //Access:RW   DataWidth:0x10   // Per-PF: Base value used in the TID calc during RoCE parsing for VF pkts.
+#define PRS_REG_FCOE_TYPE                                                                                    0x1f0744UL //Access:RW   DataWidth:0x10   // The Ethernet type value for first FCoE type.
+#define PRS_REG_FIP_TYPE                                                                                     0x1f0748UL //Access:RW   DataWidth:0x10   // The Ethernet type value for FIP type.
+#define PRS_REG_TAG_ETHERTYPE_0                                                                              0x1f074cUL //Access:RW   DataWidth:0x10   // The Ethernet type value for L2 tag 0.
+#define PRS_REG_TAG_ETHERTYPE_1                                                                              0x1f0750UL //Access:RW   DataWidth:0x10   // The Ethernet type value for L2 tag 1.
+#define PRS_REG_TAG_ETHERTYPE_2                                                                              0x1f0754UL //Access:RW   DataWidth:0x10   // The Ethernet type value for L2 tag 2.
+#define PRS_REG_TAG_ETHERTYPE_3                                                                              0x1f0758UL //Access:RW   DataWidth:0x10   // The Ethernet type value for L2 tag 3.
+#define PRS_REG_TAG_ETHERTYPE_4                                                                              0x1f075cUL //Access:RW   DataWidth:0x10   // The Ethernet type value for L2 tag 4.
+#define PRS_REG_TAG_ETHERTYPE_5                                                                              0x1f0760UL //Access:RW   DataWidth:0x10   // The Ethernet type value for L2 tag 5.
+#define PRS_REG_TAG_LEN_0                                                                                    0x1f0764UL //Access:RW   DataWidth:0x3    // The length of the info field for L2 tag 0.  The length is between 2B and 14B; in 2B granularity.
+#define PRS_REG_TAG_LEN_1                                                                                    0x1f0768UL //Access:RW   DataWidth:0x3    // The length of the info field for L2 tag 1.  The length is between 2B and 14B; in 2B granularity.
+#define PRS_REG_TAG_LEN_2                                                                                    0x1f076cUL //Access:RW   DataWidth:0x3    // The length of the info field for L2 tag 2.  The length is between 2B and 14B; in 2B granularity.
+#define PRS_REG_TAG_LEN_3                                                                                    0x1f0770UL //Access:RW   DataWidth:0x3    // The length of the info field for L2 tag 3.  The length is between 2B and 14B; in 2B granularity.
+#define PRS_REG_TAG_LEN_4                                                                                    0x1f0774UL //Access:RW   DataWidth:0x3    // The length of the info field for L2 tag 4.  The length is between 2B and 14B; in 2B granularity.
+#define PRS_REG_TAG_LEN_5                                                                                    0x1f0778UL //Access:RW   DataWidth:0x3    // The length of the info field for L2 tag 5.  The length is between 2B and 14B; in 2B granularity.
+#define PRS_REG_FIRST_HDR_HDRS_AFTER_BASIC                                                                   0x1f077cUL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.
+#define PRS_REG_FIRST_HDR_HDRS_AFTER_TAG_0                                                                   0x1f0780UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.
+#define PRS_REG_FIRST_HDR_HDRS_AFTER_TAG_1                                                                   0x1f0784UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.
+#define PRS_REG_FIRST_HDR_HDRS_AFTER_TAG_2                                                                   0x1f0788UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.
+#define PRS_REG_FIRST_HDR_HDRS_AFTER_TAG_3                                                                   0x1f078cUL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.
+#define PRS_REG_FIRST_HDR_HDRS_AFTER_TAG_4                                                                   0x1f0790UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.
+#define PRS_REG_FIRST_HDR_HDRS_AFTER_TAG_5                                                                   0x1f0794UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.
+#define PRS_REG_FIRST_HDR_MUST_HAVE_HDRS                                                                     0x1f0798UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which headers must appear in the packet on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.
+#define PRS_REG_INNER_HDR_HDRS_AFTER_BASIC                                                                   0x1f079cUL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.
+#define PRS_REG_INNER_HDR_HDRS_AFTER_TAG_0                                                                   0x1f07a0UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.
+#define PRS_REG_INNER_HDR_HDRS_AFTER_TAG_1                                                                   0x1f07a4UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.
+#define PRS_REG_INNER_HDR_HDRS_AFTER_TAG_2                                                                   0x1f07a8UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.
+#define PRS_REG_INNER_HDR_HDRS_AFTER_TAG_3                                                                   0x1f07acUL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.
+#define PRS_REG_INNER_HDR_HDRS_AFTER_TAG_4                                                                   0x1f07b0UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.
+#define PRS_REG_INNER_HDR_HDRS_AFTER_TAG_5                                                                   0x1f07b4UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.
+#define PRS_REG_INNER_HDR_MUST_HAVE_HDRS                                                                     0x1f07b8UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which headers must appear in the packet on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.
+#define PRS_REG_DST_MAC_GLOBAL_0                                                                             0x1f07bcUL //Access:RW   DataWidth:0x20   // Global destination address match value.
+#define PRS_REG_DST_MAC_GLOBAL_1                                                                             0x1f07c0UL //Access:RW   DataWidth:0x10   // Global destination address match value.
+#define PRS_REG_DST_MAC_GLOBAL_MASK_0                                                                        0x1f07c4UL //Access:RW   DataWidth:0x20   // Mask for global destination address match value. A zero in this                 register will cause the corresponding bit to not be included in the match.
+#define PRS_REG_DST_MAC_GLOBAL_MASK_1                                                                        0x1f07c8UL //Access:RW   DataWidth:0x10   // Mask for global destination address match value. A zero in this                 register will cause the corresponding bit to not be included in the match.
+#define PRS_REG_FIRST_HDR_DST_MAC_0                                                                          0x1f07ccUL //Access:RW   DataWidth:0x20   // Per-PF/Per-port: Destination address match value.
+#define PRS_REG_FIRST_HDR_DST_MAC_1                                                                          0x1f07d0UL //Access:RW   DataWidth:0x10   // Per-PF/Per-port: Destination address match value.
+#define PRS_REG_FIRST_HDR_DST_IP_0                                                                           0x1f07d4UL //Access:RW   DataWidth:0x20   // Per-PF:  Destination IP address match value - bit 129 indicates validity, bit 128 indicates an IPv6 address.
+#define PRS_REG_FIRST_HDR_DST_IP_1                                                                           0x1f07d8UL //Access:RW   DataWidth:0x20   // Per-PF:  Destination IP address match value - bit 129 indicates validity, bit 128 indicates an IPv6 address.
+#define PRS_REG_FIRST_HDR_DST_IP_2                                                                           0x1f07dcUL //Access:RW   DataWidth:0x20   // Per-PF:  Destination IP address match value - bit 129 indicates validity, bit 128 indicates an IPv6 address.
+#define PRS_REG_FIRST_HDR_DST_IP_3                                                                           0x1f07e0UL //Access:RW   DataWidth:0x20   // Per-PF:  Destination IP address match value - bit 129 indicates validity, bit 128 indicates an IPv6 address.
+#define PRS_REG_FIRST_HDR_DST_IP_4                                                                           0x1f07e4UL //Access:RW   DataWidth:0x2    // Per-PF:  Destination IP address match value - bit 129 indicates validity, bit 128 indicates an IPv6 address.
+#define PRS_REG_SRC_MAC_0_0                                                                                  0x1f07e8UL //Access:RW   DataWidth:0x20   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_0_1                                                                                  0x1f07ecUL //Access:RW   DataWidth:0x10   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_1_0                                                                                  0x1f07f0UL //Access:RW   DataWidth:0x20   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_1_1                                                                                  0x1f07f4UL //Access:RW   DataWidth:0x10   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_2_0                                                                                  0x1f07f8UL //Access:RW   DataWidth:0x20   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_2_1                                                                                  0x1f07fcUL //Access:RW   DataWidth:0x10   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_3_0                                                                                  0x1f0800UL //Access:RW   DataWidth:0x20   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_3_1                                                                                  0x1f0804UL //Access:RW   DataWidth:0x10   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_4_0                                                                                  0x1f0808UL //Access:RW   DataWidth:0x20   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_4_1                                                                                  0x1f080cUL //Access:RW   DataWidth:0x10   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_5_0                                                                                  0x1f0810UL //Access:RW   DataWidth:0x20   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_5_1                                                                                  0x1f0814UL //Access:RW   DataWidth:0x10   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_6_0                                                                                  0x1f0818UL //Access:RW   DataWidth:0x20   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_6_1                                                                                  0x1f081cUL //Access:RW   DataWidth:0x10   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_7_0                                                                                  0x1f0820UL //Access:RW   DataWidth:0x20   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_7_1                                                                                  0x1f0824UL //Access:RW   DataWidth:0x10   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_8_0                                                                                  0x1f0828UL //Access:RW   DataWidth:0x20   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_8_1                                                                                  0x1f082cUL //Access:RW   DataWidth:0x10   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_9_0                                                                                  0x1f0830UL //Access:RW   DataWidth:0x20   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_9_1                                                                                  0x1f0834UL //Access:RW   DataWidth:0x10   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_10_0                                                                                 0x1f0838UL //Access:RW   DataWidth:0x20   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_10_1                                                                                 0x1f083cUL //Access:RW   DataWidth:0x10   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_11_0                                                                                 0x1f0840UL //Access:RW   DataWidth:0x20   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_11_1                                                                                 0x1f0844UL //Access:RW   DataWidth:0x10   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_12_0                                                                                 0x1f0848UL //Access:RW   DataWidth:0x20   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_12_1                                                                                 0x1f084cUL //Access:RW   DataWidth:0x10   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_13_0                                                                                 0x1f0850UL //Access:RW   DataWidth:0x20   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_13_1                                                                                 0x1f0854UL //Access:RW   DataWidth:0x10   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_14_0                                                                                 0x1f0858UL //Access:RW   DataWidth:0x20   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_14_1                                                                                 0x1f085cUL //Access:RW   DataWidth:0x10   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_15_0                                                                                 0x1f0860UL //Access:RW   DataWidth:0x20   // Per-port: Source address match values for this port.
+#define PRS_REG_SRC_MAC_15_1                                                                                 0x1f0864UL //Access:RW   DataWidth:0x10   // Per-port: Source address match values for this port.
+#define PRS_REG_NGE_ETH_TYPE                                                                                 0x1f0868UL //Access:RW   DataWidth:0x10   // Ethertype for encapsulated ethernet used in NGE header parsing.
+#define PRS_REG_NGE_PORT                                                                                     0x1f086cUL //Access:RW   DataWidth:0x10   // Dest port value used to designate a NGE header following the UDP header.
+#define PRS_REG_RROCE_PORT                                                                                   0x1f0870UL //Access:RW   DataWidth:0x10   // Dest port value used to designate a RROCE header following the UDP header.
+#define PRS_REG_RROCE_ENABLE                                                                                 0x1f0874UL //Access:RW   DataWidth:0x1    // Per-port:  Flag enabling RRoCE.
+#define PRS_REG_NGE_COMP_VER                                                                                 0x1f0878UL //Access:RW   DataWidth:0x1    // Per-port:  Flag to compare the value of nge version to 2'b00.
+#define PRS_REG_L2_IRREG_CASES                                                                               0x1f0900UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PRS_REG_L2_IRREG_CASES_EVENT_ID                                                                    (0xff<<0) // Event ID for irregular or errored packets
+  #define PRS_REG_L2_IRREG_CASES_EVENT_ID_SHIFT                                                              0
+  #define PRS_REG_L2_IRREG_CASES_CM_HDR                                                                      (0x3ff<<8) // The CM header for irregular or errored packets. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_L2_IRREG_CASES_CM_HDR_SHIFT                                                                8
+  #define PRS_REG_L2_IRREG_CASES_AFFINITY_TYPE_E5                                                            (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_L2_IRREG_CASES_AFFINITY_TYPE_E5_SHIFT                                                      18
+#define PRS_REG_L2_TUNNELING                                                                                 0x1f0904UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define PRS_REG_L2_TUNNELING_EVENT_ID                                                                      (0xff<<0) // Event ID for tunneled packets with no match in the mac-vlan cache
+  #define PRS_REG_L2_TUNNELING_EVENT_ID_SHIFT                                                                0
+  #define PRS_REG_L2_TUNNELING_CM_HDR                                                                        (0x3ff<<8) // The CM header for tunneled packets with no match in the mac-vlan cache. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_L2_TUNNELING_CM_HDR_SHIFT                                                                  8
+  #define PRS_REG_L2_TUNNELING_AFFINITY_TYPE_E5                                                              (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_L2_TUNNELING_AFFINITY_TYPE_E5_SHIFT                                                        18
+  #define PRS_REG_L2_TUNNELING_EN_L2_MA_E5                                                                   (0x1<<20) // en_l2_ma to be used in storm context update offset field of the cm header.
+  #define PRS_REG_L2_TUNNELING_EN_L2_MA_E5_SHIFT                                                             20
+  #define PRS_REG_L2_TUNNELING_L2_MA_CONFIG_E5                                                               (0x3<<21) // l2_ma_config to be used in storm context update offset field of the cm header.
+  #define PRS_REG_L2_TUNNELING_L2_MA_CONFIG_E5_SHIFT                                                         21
+  #define PRS_REG_L2_TUNNELING_INC_SN_E5                                                                     (0x1<<23) // inc_sn to be used in storm context update offset field of the cm header.
+  #define PRS_REG_L2_TUNNELING_INC_SN_E5_SHIFT                                                               23
+#define PRS_REG_L2_TUNNELING_CACHED_MAC_VLAN                                                                 0x1f0908UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define PRS_REG_L2_TUNNELING_CACHED_MAC_VLAN_EVENT_ID                                                      (0xff<<0) // Event ID for tunneled packets with no match in the mac-vlan cache
+  #define PRS_REG_L2_TUNNELING_CACHED_MAC_VLAN_EVENT_ID_SHIFT                                                0
+  #define PRS_REG_L2_TUNNELING_CACHED_MAC_VLAN_CM_HDR                                                        (0x3ff<<8) // The CM header for tunneled packets with no match in the mac-vlan cache. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_L2_TUNNELING_CACHED_MAC_VLAN_CM_HDR_SHIFT                                                  8
+  #define PRS_REG_L2_TUNNELING_CACHED_MAC_VLAN_AFFINITY_TYPE_E5                                              (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_L2_TUNNELING_CACHED_MAC_VLAN_AFFINITY_TYPE_E5_SHIFT                                        18
+  #define PRS_REG_L2_TUNNELING_CACHED_MAC_VLAN_EN_L2_MA_E5                                                   (0x1<<20) // en_l2_ma to be used in storm context update offset field of the cm header.
+  #define PRS_REG_L2_TUNNELING_CACHED_MAC_VLAN_EN_L2_MA_E5_SHIFT                                             20
+  #define PRS_REG_L2_TUNNELING_CACHED_MAC_VLAN_L2_MA_CONFIG_E5                                               (0x3<<21) // l2_ma_config to be used in storm context update offset field of the cm header.
+  #define PRS_REG_L2_TUNNELING_CACHED_MAC_VLAN_L2_MA_CONFIG_E5_SHIFT                                         21
+  #define PRS_REG_L2_TUNNELING_CACHED_MAC_VLAN_INC_SN_E5                                                     (0x1<<23) // inc_sn to be used in storm context update offset field of the cm header.
+  #define PRS_REG_L2_TUNNELING_CACHED_MAC_VLAN_INC_SN_E5_SHIFT                                               23
+#define PRS_REG_L2_CACHED_MAC_VLAN                                                                           0x1f090cUL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define PRS_REG_L2_CACHED_MAC_VLAN_EVENT_ID                                                                (0xff<<0) // Event ID for packets that hit in the MAC/VLAN cache
+  #define PRS_REG_L2_CACHED_MAC_VLAN_EVENT_ID_SHIFT                                                          0
+  #define PRS_REG_L2_CACHED_MAC_VLAN_CM_HDR                                                                  (0x3ff<<8) // The CM header for packets that hit in the MAC/VLAN cache. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_L2_CACHED_MAC_VLAN_CM_HDR_SHIFT                                                            8
+  #define PRS_REG_L2_CACHED_MAC_VLAN_AFFINITY_TYPE_E5                                                        (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_L2_CACHED_MAC_VLAN_AFFINITY_TYPE_E5_SHIFT                                                  18
+  #define PRS_REG_L2_CACHED_MAC_VLAN_EN_L2_MA_E5                                                             (0x1<<20) // en_l2_ma to be used in storm context update offset field of the cm header.
+  #define PRS_REG_L2_CACHED_MAC_VLAN_EN_L2_MA_E5_SHIFT                                                       20
+  #define PRS_REG_L2_CACHED_MAC_VLAN_L2_MA_CONFIG_E5                                                         (0x3<<21) // l2_ma_config to be used in storm context update offset field of the cm header.
+  #define PRS_REG_L2_CACHED_MAC_VLAN_L2_MA_CONFIG_E5_SHIFT                                                   21
+  #define PRS_REG_L2_CACHED_MAC_VLAN_INC_SN_E5                                                               (0x1<<23) // inc_sn to be used in storm context update offset field of the cm header.
+  #define PRS_REG_L2_CACHED_MAC_VLAN_INC_SN_E5_SHIFT                                                         23
+#define PRS_REG_LIGHT_L2                                                                                     0x1f0910UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PRS_REG_LIGHT_L2_EVENT_ID                                                                          (0xff<<0) // Event ID for light L2
+  #define PRS_REG_LIGHT_L2_EVENT_ID_SHIFT                                                                    0
+  #define PRS_REG_LIGHT_L2_CM_HDR                                                                            (0x3ff<<8) // The CM header for light L2. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_LIGHT_L2_CM_HDR_SHIFT                                                                      8
+  #define PRS_REG_LIGHT_L2_AFFINITY_TYPE_E5                                                                  (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_LIGHT_L2_AFFINITY_TYPE_E5_SHIFT                                                            18
+#define PRS_REG_L2_REGULAR_PKT                                                                               0x1f0934UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define PRS_REG_L2_REGULAR_PKT_EVENT_ID                                                                    (0xff<<0) // Event ID for regular packets
+  #define PRS_REG_L2_REGULAR_PKT_EVENT_ID_SHIFT                                                              0
+  #define PRS_REG_L2_REGULAR_PKT_CM_HDR                                                                      (0x3ff<<8) // The CM header for regular packets. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_L2_REGULAR_PKT_CM_HDR_SHIFT                                                                8
+  #define PRS_REG_L2_REGULAR_PKT_AFFINITY_TYPE_E5                                                            (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_L2_REGULAR_PKT_AFFINITY_TYPE_E5_SHIFT                                                      18
+  #define PRS_REG_L2_REGULAR_PKT_EN_L2_MA_E5                                                                 (0x1<<20) // en_l2_ma to be used in storm context update offset field of the cm header.
+  #define PRS_REG_L2_REGULAR_PKT_EN_L2_MA_E5_SHIFT                                                           20
+  #define PRS_REG_L2_REGULAR_PKT_L2_MA_CONFIG_E5                                                             (0x3<<21) // l2_ma_config to be used in storm context update offset field of the cm header.
+  #define PRS_REG_L2_REGULAR_PKT_L2_MA_CONFIG_E5_SHIFT                                                       21
+  #define PRS_REG_L2_REGULAR_PKT_INC_SN_E5                                                                   (0x1<<23) // inc_sn to be used in storm context update offset field of the cm header.
+  #define PRS_REG_L2_REGULAR_PKT_INC_SN_E5_SHIFT                                                             23
+#define PRS_REG_TASK_CM_HDR                                                                                  0x1f0938UL //Access:RW   DataWidth:0xa    // The CM header for an FCoE packet. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+#define PRS_REG_DEF_L2_CON_TYPE                                                                              0x1f093cUL //Access:RW   DataWidth:0x4    // Connection type for no-match packets.
+#define PRS_REG_NO_MATCH_PFID                                                                                0x1f0940UL //Access:RW   DataWidth:0x4    // Per-port: PFID for no-match packets.
+#define PRS_REG_OVERRIDE_PFID_IF_NO_MATCH                                                                    0x1f0944UL //Access:RW   DataWidth:0x1    // Per-PF: If set, the PFID may be overridden for no-match packets.
+#define PRS_REG_NO_MATCH_CID                                                                                 0x1f0948UL //Access:RW   DataWidth:0x20   // Per-PF: CID for no-match packets.
+#define PRS_REG_NO_MATCH_LCID                                                                                0x1f094cUL //Access:RW   DataWidth:0x9    // Per-PF: LCID for no-match packets.
+#define PRS_REG_LIGHT_L2_ETHERTYPE_0                                                                         0x1f0950UL //Access:RW   DataWidth:0x10   // If one of these Ethertypes matches the last L2 ethertype, light_l2_cm_hdr_event_id can be used for the cm_hdr and eventid values.
+#define PRS_REG_LIGHT_L2_ETHERTYPE_1                                                                         0x1f0954UL //Access:RW   DataWidth:0x10   // If one of these Ethertypes matches the last L2 ethertype, light_l2_cm_hdr_event_id can be used for the cm_hdr and eventid values.
+#define PRS_REG_LIGHT_L2_ETHERTYPE_2                                                                         0x1f0958UL //Access:RW   DataWidth:0x10   // If one of these Ethertypes matches the last L2 ethertype, light_l2_cm_hdr_event_id can be used for the cm_hdr and eventid values.
+#define PRS_REG_LIGHT_L2_ETHERTYPE_3                                                                         0x1f095cUL //Access:RW   DataWidth:0x10   // If one of these Ethertypes matches the last L2 ethertype, light_l2_cm_hdr_event_id can be used for the cm_hdr and eventid values.
+#define PRS_REG_LIGHT_L2_ETHERTYPE_4                                                                         0x1f0960UL //Access:RW   DataWidth:0x10   // If one of these Ethertypes matches the last L2 ethertype, light_l2_cm_hdr_event_id can be used for the cm_hdr and eventid values.
+#define PRS_REG_LIGHT_L2_ETHERTYPE_5                                                                         0x1f0964UL //Access:RW   DataWidth:0x10   // If one of these Ethertypes matches the last L2 ethertype, light_l2_cm_hdr_event_id can be used for the cm_hdr and eventid values.
+#define PRS_REG_LIGHT_L2_ETHERTYPE_EN                                                                        0x1f0968UL //Access:RW   DataWidth:0x6    // Enables for each of the light_l2_ethertypes.
+#define PRS_REG_USE_LIGHT_L2                                                                                 0x1f096cUL //Access:RW   DataWidth:0x1    // Per-PF: If set, and PF classification succeeds, use  light_l2_tbit_eventid
+#define PRS_REG_DST_MAC_SELECT                                                                               0x1f0970UL //Access:RW   DataWidth:0x3    // Selects whether to use the dest MAC address of the first (0) or encapsulated (1) header in the output message for each encapsulation type. 0 - L2 GRE, 1 - VXLAN 2 - NGE
+#define PRS_REG_SRC_MAC_SELECT                                                                               0x1f0974UL //Access:RW   DataWidth:0x3    // Selects whether to use the source MAC address of the first (0) or encapsulated (1) header in the output message for each encapsulation type. 0 - L2 GRE, 1 - VXLAN 2 - NGE
+#define PRS_REG_VLAN_TAG_SELECT                                                                              0x1f0978UL //Access:RW   DataWidth:0x3    // Selects whether to use the 8021q tag of the first (0) or encapsulated (1) header in the output message for each encapsulation type. 0 - L2 GRE, 1 - VXLAN, 2 - NGE
+#define PRS_REG_MAC_VLAN_CACHE_USE_TENANT_ID                                                                 0x1f09bcUL //Access:RW   DataWidth:0x6    // Per-PF: Indicates whether to include Tenant ID (if it exists) in the MAC VLAN Cache entry for each encapsulation type. 0 - L2 GRE, 1 - IP GRE, 2 - VXLAN, 3 - T-Tag, 4 - L2 NGE, 5 - IP NGE
+#define PRS_REG_MAC_VLAN_FLEX_UPPER                                                                          0x1f09c0UL //Access:RW   DataWidth:0xe    // Building block information used to build the MAC-VLAN Cache Flexible Field.  If two blocks are used, this block is used for the upper bytes. 13:11 - number of bytes, 10:8  - Reserved, 7:4   - byte offset, 3:0 - block id.
+#define PRS_REG_MAC_VLAN_FLEX_LOWER                                                                          0x1f09c4UL //Access:RW   DataWidth:0x8    // Building block information used to build the MAC-VLAN Cache Flexible Field.  This block is only used if the number of bytes in mac_vlan_flex_upper is less than 8. 7:4 - byte offset 3:0 - block id.
+#define PRS_REG_MAC_VLAN_FLEX_BITMASK_0                                                                      0x1f09c8UL //Access:RW   DataWidth:0x20   // Used to bitmask the flexible field formed from the building block information in mac_vlan_flex_upper and/or mac_vlan_flex_lower.  A zero in this register will mask the corresponding bit in the flexible field to 0.
+#define PRS_REG_MAC_VLAN_FLEX_BITMASK_1                                                                      0x1f09ccUL //Access:RW   DataWidth:0x20   // Used to bitmask the flexible field formed from the building block information in mac_vlan_flex_upper and/or mac_vlan_flex_lower.  A zero in this register will mask the corresponding bit in the flexible field to 0.
+#define PRS_REG_SORT_SACK                                                                                    0x1f09d0UL //Access:RW   DataWidth:0x1    // Per-PF: If set, the SACK blocks will be sorted and various compares performed.
+#define PRS_REG_SACK_BLK_OVERRIDE                                                                            0x1f09d4UL //Access:RW   DataWidth:0x1    // If set, RoCE building block data is FIFOed on all non-FCoE packets. This allows Over-L2-Raw Part2 to be available on non-RoCE packets. The RoCE specific bits of this block will still show default values on non-RoCE packets.
+#define PRS_REG_RDMA_SYN_MASK                                                                                0x1f09d8UL //Access:RW   DataWidth:0x20   // Per-PF: Mask used in RDMA SYN cookie calculation.
+#define PRS_REG_RDMA_SYN_SEED_0                                                                              0x1f09dcUL //Access:RW   DataWidth:0x20   // Seeds used in RDMA SYN cookie calculation.
+#define PRS_REG_RDMA_SYN_SEED_1                                                                              0x1f09e0UL //Access:RW   DataWidth:0x20   // Seeds used in RDMA SYN cookie calculation.
+#define PRS_REG_RDMA_SYN_SEED_2                                                                              0x1f09e4UL //Access:RW   DataWidth:0x20   // Seeds used in RDMA SYN cookie calculation.
+#define PRS_REG_RDMA_SYN_SEED_3                                                                              0x1f09e8UL //Access:RW   DataWidth:0x20   // Seeds used in RDMA SYN cookie calculation.
+#define PRS_REG_RDMA_SYN_SEED_4                                                                              0x1f09ecUL //Access:RW   DataWidth:0x20   // Seeds used in RDMA SYN cookie calculation.
+#define PRS_REG_RDMA_SYN_SEED_5                                                                              0x1f09f0UL //Access:RW   DataWidth:0x20   // Seeds used in RDMA SYN cookie calculation.
+#define PRS_REG_RDMA_SYN_SEED_6                                                                              0x1f09f4UL //Access:RW   DataWidth:0x20   // Seeds used in RDMA SYN cookie calculation.
+#define PRS_REG_RDMA_SYN_SEED_7                                                                              0x1f09f8UL //Access:RW   DataWidth:0x20   // Seeds used in RDMA SYN cookie calculation.
+#define PRS_REG_RDMA_SYN_COOKIE_EN                                                                           0x1f09fcUL //Access:RW   DataWidth:0x1    // Per-PF: Enables SYN cookie hash function.
+#define PRS_REG_IWARP_EN                                                                                     0x1f0a00UL //Access:RW   DataWidth:0x1    // Per-PF: If set, enables iWarp.
+#define PRS_REG_PKT_LEN_STAT_ADD_CRC                                                                         0x1f0a04UL //Access:RW   DataWidth:0x1    // Per-PF: If set, 4B for Ethernet CRC is included in Packet Length for Statistics field. For pkts where classification failed,  the per-port version of this register is used.
+#define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_INNER                                                          0x1f0a08UL //Access:RW   DataWidth:0x8    // Per-PF: For each bit set, the length of the corresponding tag in the inner header will be subtracted from Packet Length for Statistics Field.  For pkts where classification failed,  the per-port version of this register is used.
+#define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST                                                          0x1f0a0cUL //Access:RW   DataWidth:0x9    // Per-PF: For each bit set, the length of the corresponding tag in the first header will be subtracted from Packet Length for Statistics Field.  The upper bit is for proprietary header. For pkts where classification failed,  the per-port version of this register is used.
+#define PRS_REG_CLASSIFY_FAILED_PKT_LEN_STAT_ADD_CRC                                                         0x1f0a10UL //Access:RW   DataWidth:0x1    // Per-Port: If set and classification failed, 4B for Ethernet CRC is included in Packet Length for Statistics field.
+#define PRS_REG_CLASSIFY_FAILED_PKT_LEN_STAT_TAGS_NOT_COUNTED_INNER                                          0x1f0a14UL //Access:RW   DataWidth:0x8    // Per-Port: If classification failed, for each bit set, the length of the corresponding tag in the inner header will be subtracted from Packet Length for Statistics Field
+#define PRS_REG_CLASSIFY_FAILED_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST                                          0x1f0a18UL //Access:RW   DataWidth:0x9    // Per-Port: If classification failed, for each bit set, the length of the corresponding tag in the first header will be subtracted from Packet Length for Statistics Field.  The upper bit is for proprietary header.
+#define PRS_REG_MSG_INFO                                                                                     0x1f0a1cUL //Access:RW   DataWidth:0x20   // Per-PF: This value is passed to the per-PF configuration field in the output message.
+#define PRS_REG_NIG_CLASSIFY_FAILED                                                                          0x1f0a20UL //Access:RW   DataWidth:0x2    // Per-Port: This value goes in the NIG Classify Failed field of the output message when classification fails.
+#define PRS_REG_MSG_CT_MAIN_0                                                                                0x1f0a24UL //Access:R    DataWidth:0x18   // (per-port) Number of messages sent to TCM on the main port for TC 0. In 4-port mode, only TCs 0-3 are valid.  Counter loops to 0.
+#define PRS_REG_MSG_CT_LB_0                                                                                  0x1f0a28UL //Access:R    DataWidth:0x18   // (per-port) Number of messages sent to TCM on the LB port for TC 0. In 4-port mode, only TCs 0-3 and 8 are valid. Counter loops to 0.
+#define PRS_REG_MSG_CT_MAIN_1                                                                                0x1f0a2cUL //Access:R    DataWidth:0x18   // (per-port) Number of messages sent to TCM on the main port for TC 1. In 4-port mode, only TCs 0-3 are valid.  Counter loops to 0.
+#define PRS_REG_MSG_CT_LB_1                                                                                  0x1f0a30UL //Access:R    DataWidth:0x18   // (per-port) Number of messages sent to TCM on the LB port for TC 1. In 4-port mode, only TCs 0-3 and 8 are valid. Counter loops to 0.
+#define PRS_REG_MSG_CT_MAIN_2                                                                                0x1f0a34UL //Access:R    DataWidth:0x18   // (per-port) Number of messages sent to TCM on the main port for TC 2. In 4-port mode, only TCs 0-3 are valid.  Counter loops to 0.
+#define PRS_REG_MSG_CT_LB_2                                                                                  0x1f0a38UL //Access:R    DataWidth:0x18   // (per-port) Number of messages sent to TCM on the LB port for TC 2. In 4-port mode, only TCs 0-3 and 8 are valid. Counter loops to 0.
+#define PRS_REG_MSG_CT_MAIN_3                                                                                0x1f0a3cUL //Access:R    DataWidth:0x18   // (per-port) Number of messages sent to TCM on the main port for TC 3. In 4-port mode, only TCs 0-3 are valid.  Counter loops to 0.
+#define PRS_REG_MSG_CT_LB_3                                                                                  0x1f0a40UL //Access:R    DataWidth:0x18   // (per-port) Number of messages sent to TCM on the LB port for TC 3. In 4-port mode, only TCs 0-3 and 8 are valid. Counter loops to 0.
+#define PRS_REG_MSG_CT_MAIN_4                                                                                0x1f0a44UL //Access:R    DataWidth:0x18   // (per-port) Number of messages sent to TCM on the main port for TC 4. In 4-port mode, only TCs 0-3 are valid.  Counter loops to 0.
+#define PRS_REG_MSG_CT_LB_4                                                                                  0x1f0a48UL //Access:R    DataWidth:0x18   // (per-port) Number of messages sent to TCM on the LB port for TC 4. In 4-port mode, only TCs 0-3 and 8 are valid. Counter loops to 0.
+#define PRS_REG_MSG_CT_MAIN_5                                                                                0x1f0a4cUL //Access:R    DataWidth:0x18   // (per-port) Number of messages sent to TCM on the main port for TC 5. In 4-port mode, only TCs 0-3 are valid.  Counter loops to 0.
+#define PRS_REG_MSG_CT_LB_5                                                                                  0x1f0a50UL //Access:R    DataWidth:0x18   // (per-port) Number of messages sent to TCM on the LB port for TC 5. In 4-port mode, only TCs 0-3 and 8 are valid. Counter loops to 0.
+#define PRS_REG_MSG_CT_MAIN_6                                                                                0x1f0a54UL //Access:R    DataWidth:0x18   // (per-port) Number of messages sent to TCM on the main port for TC 6. In 4-port mode, only TCs 0-3 are valid.  Counter loops to 0.
+#define PRS_REG_MSG_CT_LB_6                                                                                  0x1f0a58UL //Access:R    DataWidth:0x18   // (per-port) Number of messages sent to TCM on the LB port for TC 6. In 4-port mode, only TCs 0-3 and 8 are valid. Counter loops to 0.
+#define PRS_REG_MSG_CT_MAIN_7                                                                                0x1f0a5cUL //Access:R    DataWidth:0x18   // (per-port) Number of messages sent to TCM on the main port for TC 7. In 4-port mode, only TCs 0-3 are valid.  Counter loops to 0.
+#define PRS_REG_MSG_CT_LB_7                                                                                  0x1f0a60UL //Access:R    DataWidth:0x18   // (per-port) Number of messages sent to TCM on the LB port for TC 7. In 4-port mode, only TCs 0-3 and 8 are valid. Counter loops to 0.
+#define PRS_REG_MSG_CT_LB_8                                                                                  0x1f0a64UL //Access:R    DataWidth:0x18   // (per-port) Number of messages sent to TCM on the LB port for TC 8. In 4-port mode, only TCs 0-3 and 8 are valid. Counter loops to 0.
+#define PRS_REG_IGNORE_UDP_ZERO_CHECKSUM                                                                     0x1f0a68UL //Access:RW   DataWidth:0x3    // bit 0 - ignore for VXLAN, bit 1 - ignore for NGE, bit 2 - ignore for RRoCE
+#define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES                                                                    0x1f0b00UL //Access:RC   DataWidth:0x18   // The number of input CFC flush packets.
+#define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES                                                            0x1f0b04UL //Access:RC   DataWidth:0x18   // The number of input transparent flush packets.
+#define PRS_REG_NUM_OF_PACKETS_0                                                                             0x1f0b08UL //Access:RC   DataWidth:0x18   // The number of processed packets for TC 0.  Counts packets as                             they are chosen for processing.
+#define PRS_REG_NUM_OF_PACKETS_1                                                                             0x1f0b0cUL //Access:RC   DataWidth:0x18   // The number of processed packets for TC 1.  Counts packets as                             they are chosen for processing.
+#define PRS_REG_NUM_OF_PACKETS_2                                                                             0x1f0b10UL //Access:RC   DataWidth:0x18   // The number of processed packets for TC 2.  Counts packets as                             they are chosen for processing.
+#define PRS_REG_NUM_OF_PACKETS_3                                                                             0x1f0b14UL //Access:RC   DataWidth:0x18   // The number of processed packets for TC 3.  Counts packets as                             they are chosen for processing.
+#define PRS_REG_NUM_OF_PACKETS_4                                                                             0x1f0b18UL //Access:RC   DataWidth:0x18   // The number of processed packets for TC 4.  Counts packets as                             they are chosen for processing.
+#define PRS_REG_NUM_OF_PACKETS_5                                                                             0x1f0b1cUL //Access:RC   DataWidth:0x18   // The number of processed packets for TC 5.  Counts packets as                             they are chosen for processing.
+#define PRS_REG_NUM_OF_PACKETS_6                                                                             0x1f0b20UL //Access:RC   DataWidth:0x18   // The number of processed packets for TC 6.  Counts packets as                             they are chosen for processing.
+#define PRS_REG_NUM_OF_PACKETS_7                                                                             0x1f0b24UL //Access:RC   DataWidth:0x18   // The number of processed packets for TC 7.  Counts packets as                             they are chosen for processing.
+#define PRS_REG_NUM_OF_PACKETS_8                                                                             0x1f0b28UL //Access:RC   DataWidth:0x18   // The number of process packets for TC 8.  Counts packets as                             they are chosen for processing.
+#define PRS_REG_FIFO_EMPTY_FLAGS                                                                             0x1f0b30UL //Access:WB_R DataWidth:0x80   // Debug only: Empty_flag for each FIFO.
+#define PRS_REG_FIFO_EMPTY_FLAGS_SIZE                                                                        4
+#define PRS_REG_FIFO_FULL_FLAGS                                                                              0x1f0b40UL //Access:WB_R DataWidth:0x80   // Debug only: Full_flag for each FIFO.
+#define PRS_REG_FIFO_FULL_FLAGS_SIZE                                                                         4
+#define PRS_REG_PRS_PKT_CT_BB_K2                                                                             0x1f0b50UL //Access:R    DataWidth:0x6    // Debug only: Parser pipeline packet count.  This is the value of the counter in the Input Arbiter that keeps track of the number of packets that have been selected to be processed but have not yet resulted in a message to TCM.
+#define PRS_REG_QUEUE_PKT_AVAIL_STATUS                                                                       0x1f0b54UL //Access:R    DataWidth:0x11   // Debug only (per-port): Packet available status of the main and loopback queues of each traffic class, before being back pressured by the STORMs. 16:8 - Loopback, 7:0 - main
+#define PRS_REG_STORM_BKPRS_STATUS                                                                           0x1f0b58UL //Access:R    DataWidth:0x18   // Debug only (per-port): STORM backpressure status (blocked priorities) Each set bit represents a blocked TC (7-0) from MSDM, TSDM, and USDM, respectively.
+#define PRS_REG_STOP_PARSING_STATUS                                                                          0x1f0b5cUL //Access:R    DataWidth:0x1    // Debug only:  BRB has asserted Stop Parsing indication to PRS.
+#define PRS_REG_MINI_CACHE_ENTRY                                                                             0x1f0b60UL //Access:WB_R DataWidth:0x32   // Debug only: In case of LCID validation error, the current value of the single entry in the CID load mini-cache is captured. 49: Valid, 48:40 - LCID, 39:32 - Region, 31:0 - CID
+#define PRS_REG_MINI_CACHE_ENTRY_SIZE                                                                        2
+#define PRS_REG_MINI_CACHE_FAILED_RESPONSE                                                                   0x1f0b68UL //Access:R    DataWidth:0xd    // Debug only:  In the case of a mini-cache LCID validation error, the load response with the mismatched LCID is captured here.
+#define PRS_REG_DBG_SELECT                                                                                   0x1f0b6cUL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PRS_REG_DBG_DWORD_ENABLE                                                                             0x1f0b70UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PRS_REG_DBG_SHIFT                                                                                    0x1f0b74UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PRS_REG_DBG_OUT_DATA                                                                                 0x1f0b80UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PRS_REG_DBG_OUT_DATA_SIZE                                                                            8
+#define PRS_REG_DBG_FORCE_VALID                                                                              0x1f0ba0UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PRS_REG_DBG_FORCE_FRAME                                                                              0x1f0ba4UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PRS_REG_DBG_OUT_VALID                                                                                0x1f0ba8UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define PRS_REG_DBG_OUT_FRAME                                                                                0x1f0bacUL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define PRS_REG_FC_DBG_SELECT_A_E5                                                                           0x1f0bb0UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PRS_REG_FC_DBG_SELECT_BB_K2                                                                          0x1f0bb0UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PRS_REG_FC_DBG_DWORD_ENABLE_A_E5                                                                     0x1f0bb4UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PRS_REG_FC_DBG_DWORD_ENABLE_BB_K2                                                                    0x1f0bb4UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PRS_REG_FC_DBG_SHIFT_A_E5                                                                            0x1f0bb8UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PRS_REG_FC_DBG_SHIFT_BB_K2                                                                           0x1f0bb8UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PRS_REG_FC_DBG_OUT_DATA_A_E5                                                                         0x1f0bc0UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PRS_REG_FC_DBG_OUT_DATA_A_SIZE                                                                       8
+#define PRS_REG_FC_DBG_OUT_DATA_BB_K2                                                                        0x1f0bc0UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PRS_REG_FC_DBG_OUT_DATA_SIZE                                                                         8
+#define PRS_REG_FC_DBG_FORCE_VALID_A_E5                                                                      0x1f0be0UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PRS_REG_FC_DBG_FORCE_VALID_BB_K2                                                                     0x1f0be0UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PRS_REG_FC_DBG_FORCE_FRAME_A_E5                                                                      0x1f0be4UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PRS_REG_FC_DBG_FORCE_FRAME_BB_K2                                                                     0x1f0be4UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PRS_REG_FC_DBG_OUT_VALID_A_E5                                                                        0x1f0be8UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define PRS_REG_FC_DBG_OUT_VALID_BB_K2                                                                       0x1f0be8UL //Access:R    DataWidth:0x4    // Dbgmux output valid
+#define PRS_REG_FC_DBG_OUT_FRAME_A_E5                                                                        0x1f0becUL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define PRS_REG_FC_DBG_OUT_FRAME_BB_K2                                                                       0x1f0becUL //Access:R    DataWidth:0x4    // Dbgmux output frame
+#define PRS_REG_LAST_PKT_LIST_BB_K2                                                                          0x1f0c00UL //Access:R    DataWidth:0x20   // Debug only : Read access to a FIFO containing information from the last 32 pkts sent to TCM: Reserved - 127:66, Parsing and Error flags - 65:50, Start block - 49:37, Priority - 36:34, Port - 33:32, CID - 31:0. To allow this register to be read during traffic, the full entry value is latched when the lowest 4B are read. If the upper bytes of the same entry are read next, the latched value is used.  If another entry is read or the lower 4B are read again, a fresh value is returned from the FIFO. For flush packets, the CID comes from the flush message.
+#define PRS_REG_LAST_PKT_LIST_SIZE                                                                           128
+#define PRS_REG_FC_DBG_SELECT_B_E5                                                                           0x1f0e00UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PRS_REG_FC_DBG_DWORD_ENABLE_B_E5                                                                     0x1f0e04UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PRS_REG_FC_DBG_SHIFT_B_E5                                                                            0x1f0e08UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PRS_REG_FC_DBG_OUT_DATA_B_E5                                                                         0x1f0e20UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PRS_REG_FC_DBG_OUT_DATA_B_SIZE                                                                       8
+#define PRS_REG_FC_DBG_FORCE_VALID_B_E5                                                                      0x1f0e40UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PRS_REG_FC_DBG_FORCE_FRAME_B_E5                                                                      0x1f0e44UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PRS_REG_FC_DBG_OUT_VALID_B_E5                                                                        0x1f0e48UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define PRS_REG_FC_DBG_OUT_FRAME_B_E5                                                                        0x1f0e4cUL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define PRS_REG_PTLD_INITIAL_CREDIT_E5                                                                       0x1f0f00UL //Access:RW   DataWidth:0x8    // The initial credit in the packet start message to the ptld interface. Credit is cycle based.
+#define PRS_REG_TCM_INITIAL_CREDIT_BB_K2                                                                     0x1f0f00UL //Access:RW   DataWidth:0x8    // The initial credit in the packet start message to the TCM interface (message to STORM). Credit is cycle based.
+#define PRS_REG_CCFC_SEARCH_INITIAL_CREDIT                                                                   0x1f0f04UL //Access:RW   DataWidth:0x8    // The initial credit for the search message to the CCFC interface. Credit is transaction based.
+#define PRS_REG_TCFC_SEARCH_INITIAL_CREDIT                                                                   0x1f0f08UL //Access:RW   DataWidth:0x2    // The initial credit for the search message to the TCFC interface. Credit is transaction based.
+#define PRS_REG_PTLD_CURRENT_CREDIT_E5                                                                       0x1f0f0cUL //Access:R    DataWidth:0x8    // Debug only: PTLD current credit. Transaction based. This is a count of the requests                        that have not received an ACK.
+#define PRS_REG_TCM_CURRENT_CREDIT_BB_K2                                                                     0x1f0f0cUL //Access:R    DataWidth:0x8    // Debug only: TCM current credit. Transaction based. This is a count of the requests                        that have not received an ACK.
+#define PRS_REG_CCFC_SEARCH_CURRENT_CREDIT                                                                   0x1f0f10UL //Access:R    DataWidth:0x8    // Debug only: CCFC search request current credit. Transaction based. This is a count of the requests that have not received an ACK.
+#define PRS_REG_TCFC_SEARCH_CURRENT_CREDIT                                                                   0x1f0f14UL //Access:R    DataWidth:0x8    // Debug only: TCFC search request current credit. Transaction based. This is a count of the requests that have not received an ACK.
+#define PRS_REG_CCFC_LOAD_CURRENT_CREDIT                                                                     0x1f0f18UL //Access:R    DataWidth:0x1    // Debug only: CCFC load request current credit. Transaction based. Since the credit limit on this interface is 1, if this bit is high there is a request that has not received an ACK.
+#define PRS_REG_TCFC_LOAD_CURRENT_CREDIT                                                                     0x1f0f1cUL //Access:R    DataWidth:0x1    // Debug only: TCFC load request current credit. Transaction based.  Since the credit limit on this interface is 1, if this bit is high there is a request that has not received an ACK.
+#define PRS_REG_CCFC_SEARCH_REQ_CT                                                                           0x1f0f20UL //Access:R    DataWidth:0x5    // Debug only: The number of outstanding CCFC search requests. This is a count of the requests that have not received a response.
+#define PRS_REG_TCFC_SEARCH_REQ_CT                                                                           0x1f0f24UL //Access:R    DataWidth:0x5    // Debug only: The number of outstanding TCFC search requests This is a count of the requests that have not received a response.
+#define PRS_REG_CCFC_LOAD_REQ_CT                                                                             0x1f0f28UL //Access:R    DataWidth:0x5    // Debug only: The number of outstanding CCFC load requests
+#define PRS_REG_TCFC_LOAD_REQ_CT                                                                             0x1f0f2cUL //Access:R    DataWidth:0x5    // Debug only: The number of outstanding TCFC load requests
+#define PRS_REG_SOP_REQ_CT                                                                                   0x1f0f30UL //Access:R    DataWidth:0x3    // Debug only: Outstanding SOP request count.  The value of the counter in the BRB Interface Unit that keeps track of the number of SOP requests sent to the BRB.
+#define PRS_REG_EOP_REQ_CT                                                                                   0x1f0f34UL //Access:R    DataWidth:0x3    // Debug only (per-port): Outstanding EOP request count.  The value of the counter in the BRB Interface Unit that keeps track of the number of EOP requests sent to the BRB.
+#define PRS_REG_RGFS_INITIAL_CREDIT_E5                                                                       0x1f0f38UL //Access:RW   DataWidth:0x8    // The initial credit in the packet start message to the RGFS interface. Credit is cycle based.
+#define PRS_REG_RGFS_CURRENT_CREDIT_E5                                                                       0x1f0f3cUL //Access:R    DataWidth:0x8    // Debug only: RGFS current credit. Transaction based. This is a count of the requests                        that have not received an ACK.
+#define PRS_REG_FCE_FC_FIFO_INPUT_FIFO_ALMOST_FULL_TH_E5                                                     0x1f0f40UL //Access:RW   DataWidth:0x4    // 
+#define PRS_REG_SOP_DSCR_FIFO_ALMOST_FULL_TH_E5                                                              0x1f0f44UL //Access:RW   DataWidth:0x3    // 
+#define PRS_REG_FCE_MAX_PARKING_LOT_OCCUPANCY_E5                                                             0x1f0f48UL //Access:R    DataWidth:0x4    // 
+#define PRS_REG_FCE_MAX_PARKING_LOT_VALID_ENTRIES_E5                                                         0x1f0f4cUL //Access:R    DataWidth:0x4    // 
+#define PRS_REG_CAM_BIST_EN_BB                                                                               0x1f0f80UL //Access:RW   DataWidth:0x1    // Used to enable/disable BIST mode. When set, BIST testing will be performed and the results will be posted upon completion. When cleared CAM access will be enabled through the CAM BIST mechanism instead.
+#define PRS_REG_CAM_BIST_SKIP_ERROR_CNT_BB                                                                   0x1f0f84UL //Access:RW   DataWidth:0x8    // Provides a threshold for the number of CAM BIST errors that are acceptable before reporting CAM BIST failure status.
+#define PRS_REG_CAM_BIST_STATUS_SEL_BB                                                                       0x1f0f88UL //Access:RW   DataWidth:0x8    // Used to select the BIST status word to read following the completion of a BIST test. Also used to select the data slice when writing data directly to the CAM using the CAM BIST mechanism.
+#define PRS_REG_CAM_BIST_STATUS_BB                                                                           0x1f0f8cUL //Access:R    DataWidth:0x20   // Provides read-only access to the BIST status word selected by cam_bist_status_sel.
+#define PRS_REG_CAM_BIST_DBG_DATA_BB                                                                         0x1f0f90UL //Access:RW   DataWidth:0x20   // For CAM bist usage.
+#define PRS_REG_CAM_BIST_DBG_DATA_VALID_BB                                                                   0x1f0f94UL //Access:RW   DataWidth:0x1    // For CAM bist usage.
+#define PRS_REG_CAM_BIST_DBG_COMPARE_EN_BB                                                                   0x1f0f98UL //Access:RW   DataWidth:0x1    // For CAM bist usage.
+#define PRS_REG_GFT_PROFILE_MASK_RAM                                                                         0x1f1000UL //Access:WB   DataWidth:0x2a   // Used to set the values of the GFT profile mask ram. line #31 must be configured before enabling the GFT since #31 is the default profile. 41.  Tenant ID Inner header(used also for non-encasulated packet): 40.Source MAC 39.Destination MAC 38.VLAN (12b) )  Tag 1 37.Provider VLAN (12b) )  Tag 0 36.Priority taken from CVLAN tag or the SVLAN tag based on GFTInnerVlanSelect global configuration 35.Source IP 34.Destination IP 33.Over IP protocol 32.DSCP (extracted form IP TOS) 31.Source port or ICMP type 30.Destination port or ICMP code 29.TCP flag - NS 28.TCP flag - CWR 27.TCP flag - ECE 26.TCP flag - URG 25.TCP flag - ACK 24.TCP flag - PSH 23.TCP flag - RST 22.TCP flag - SYN 21.TCP flag - FIN 20.reserved 19.Ethertype 18.Ttl 17.TtlEqualOne Tunnel header fields(not used for non-encasulated packet): 16.Source MAC 15.Destination MAC 14.VLAN  Tag 1 13.Provider VLAN  Tag 0 12.Priority taken from CVLAN tag or the SVLAN tag based on GFTTunnelVlanSelect global 11.Source IP 10.Destination IP 9.Over IP protocol 8.DSCP 7.Source port or ICMP type 6.Destination port or ICMP code 5.Ethertype 4.Ttl 3.TtlEqualOne 2.Entrophy : GENEVE, VXLAN  source UDP port number,  NVGRE  FlowID (key 8LBS bits)  1:0 vlan select 0: inner Provider VLAN 1: inner VLAN 2: outer Provider VLAN 3: outer  VLAN
+#define PRS_REG_GFT_PROFILE_MASK_RAM_SIZE                                                                    64
+#define PRS_REG_GFT_CAM                                                                                      0x1f1100UL //Access:RW   DataWidth:0x1d   // Used to set the values of the GFT profile cam: 0 valid, zero at reset 1-14 data 14-11 PF ID (3bit BB 4bit K2) 10-7 Tunnel type (4b) 0000-no tunnel 0001-vxlan 0010-GRE MAC / NVGRE 0011-GRE IP 0100-Genve MAC 0101-Genve IP 1000-1111  reserved   6-3 upper protocol type (4b):  -  by priority 0 is highest  0000  RoCE 0001  RoCE v2 0010  FCoE 0011  ICMP 0100  ARP 0101  User TCP Source Port 1(inner) 0110  User TCP Destination Port 1(inner) 0111  TCP 1000  User UDP Destination Port 1(inner) 1001  User UDP Destination Port 2(outer) 1010  UDP 1011  User IP Protocol 1(inner) 1100  User IP Protocol 2(outer) 1101  User ETH Type 1 (inner) 1110  User ETH Type 2 (outer) 1111  RAW   - by priority  2 Tunnel IP version  0-v4 1-v6 1 IP version  0-v4 1-v6 15-28 mask of bits 1-14 resepectively , 1- compare, 0-dont compare. All the CAM should be initialized in order to prevent false parity error while doing scrubbing. the init value: bits[28-1] - Don't care bit[0](valid) - 1'b0
+#define PRS_REG_GFT_CAM_SIZE                                                                                 31
+#define PRS_REG_GFT_HASH_KEY_0                                                                               0x1f1180UL //Access:RW   DataWidth:0x20   // 
+#define PRS_REG_GFT_HASH_KEY_1                                                                               0x1f1184UL //Access:RW   DataWidth:0x20   // 
+#define PRS_REG_GFT_HASH_KEY_2                                                                               0x1f1188UL //Access:RW   DataWidth:0x20   // 
+#define PRS_REG_GFT_HASH_KEY_3                                                                               0x1f118cUL //Access:RW   DataWidth:0x20   // 
+#define PRS_REG_GFT_HASH_KEY_4                                                                               0x1f1190UL //Access:RW   DataWidth:0x20   // 
+#define PRS_REG_GFT_TCP_SOURCE_PORT_1                                                                        0x1f1194UL //Access:RW   DataWidth:0x10   // tcp source port for the gft profile key upper protocol type
+#define PRS_REG_GFT_TCP_DESTINATION_PORT_1                                                                   0x1f1198UL //Access:RW   DataWidth:0x10   // tcp inner destination port for the gft profile key upper protocol type
+#define PRS_REG_GFT_UDP_DESTINATION_PORT_1                                                                   0x1f119cUL //Access:RW   DataWidth:0x10   // udp inner destination port for the gft profile key upper protocol type
+#define PRS_REG_GFT_UDP_DESTINATION_PORT_2                                                                   0x1f11a0UL //Access:RW   DataWidth:0x10   // udp outer destination port for the gft profile key upper protocol type
+#define PRS_REG_GFT_IP_PROTOCOL_1                                                                            0x1f11a4UL //Access:RW   DataWidth:0x8    // inner ip protocol for the gft profile key upper protocol type
+#define PRS_REG_GFT_IP_PROTOCOL_2                                                                            0x1f11a8UL //Access:RW   DataWidth:0x8    // outer ip protocol for the gft profile key upper protocol type
+#define PRS_REG_GFT_ETH_TYPE_1                                                                               0x1f11acUL //Access:RW   DataWidth:0x10   // inner ethernet type for the gft profile key upper protocol type
+#define PRS_REG_GFT_ETH_TYPE_2                                                                               0x1f11b0UL //Access:RW   DataWidth:0x10   // outer ethernet type for the gft profile key upper protocol type
+#define PRS_REG_GFT_INNER_VLAN_SELECT                                                                        0x1f11b4UL //Access:RW   DataWidth:0x1    // used to build the priority field in the GFT used frame fields inner header 0- use CVLAN priority 1- use SVLAN priority
+#define PRS_REG_GFT_TUNNEL_VLAN_SELECT                                                                       0x1f11b8UL //Access:RW   DataWidth:0x1    // used to build the priority field in the GFT used frame fields tunnel header 0- use CVLAN priority 1- use SVLAN priority
+#define PRS_REG_SEARCH_GFT                                                                                   0x1f11bcUL //Access:RW   DataWidth:0x1    // Per-PF: Enables gft search for all packet types.
+#define PRS_REG_SEARCH_NON_IP_AS_GFT                                                                         0x1f11c0UL //Access:RW   DataWidth:0x1    // Per-PF: Enables gft search for non-IP packets. Only valid if search_gft is also set.
+#define PRS_REG_GFT_CONNECTION_TYPE                                                                          0x1f11c4UL //Access:RW   DataWidth:0x4    // connection type for gft, if the connection type returned in the search response equal to this value, use the CM_HDR_GFT intead of CM_HDR_EVENT_ID_X in the CM header. is also set.
+#define PRS_REG_CM_HDR_GFT                                                                                   0x1f11c8UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PRS_REG_CM_HDR_GFT_EVENT_ID                                                                        (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and gft connection type
+  #define PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT                                                                  0
+  #define PRS_REG_CM_HDR_GFT_CM_HDR                                                                          (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and gft connection type . Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT                                                                    8
+  #define PRS_REG_CM_HDR_GFT_AFFINITY_TYPE_E5                                                                (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_CM_HDR_GFT_AFFINITY_TYPE_E5_SHIFT                                                          18
+#define PRS_REG_GFT_CAM_SCRUB_HIT_EN                                                                         0x1f11ccUL //Access:RW   DataWidth:0x1    // When set to 1 the gft cam hit parity scrubbing feature is enabled.
+#define PRS_REG_GFT_CAM_SCRUB_MISS_EN                                                                        0x1f11d0UL //Access:RW   DataWidth:0x1    // When set to 1 the gft cam miss parity scrubbing feature is enabled.
+#define PRS_REG_COMPARE_GRE_VERSION_E5                                                                       0x1f1400UL //Access:RW   DataWidth:0x1    // compare the GRE version field to the gre_version register.
+#define PRS_REG_GRE_VERSION_E5                                                                               0x1f1404UL //Access:RW   DataWidth:0x3    // compare the GRE version field to gre_version register if compare_gre_version=1.
+#define PRS_REG_MPLS_IPV4_LABEL_E5                                                                           0x1f1408UL //Access:RW   DataWidth:0x14   // mpls_ipv4_label to be compared Vs the label field of the last mpls label if mpls_compare_label is set.
+#define PRS_REG_MPLS_IPV6_LABEL_E5                                                                           0x1f140cUL //Access:RW   DataWidth:0x14   // mpls_ipv6_label to be compared Vs the label field of the last mpls label if mpls_compare_label is set.
+#define PRS_REG_MPLS_COMPARE_LABEL_E5                                                                        0x1f1410UL //Access:RW   DataWidth:0x1    // mpls_ipv6_label/mpls_ipv4_label to be compared Vs the label field of the last mpls label if mpls_compare_label is set.
+#define PRS_REG_MPLS_UNI_TYPE_E5                                                                             0x1f1414UL //Access:RW   DataWidth:0x10   // Ethernet type of MPLS.
+#define PRS_REG_MPLS_MULTI_TYPE_E5                                                                           0x1f1418UL //Access:RW   DataWidth:0x10   // Ethernet type of MPLS.
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_0_E5                                                               0x1f141cUL //Access:RW   DataWidth:0x8    // ipv6 extension uniform header type 0
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_1_E5                                                               0x1f1420UL //Access:RW   DataWidth:0x8    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_2_E5                                                               0x1f1424UL //Access:RW   DataWidth:0x8    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_3_E5                                                               0x1f1428UL //Access:RW   DataWidth:0x8    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_4_E5                                                               0x1f142cUL //Access:RW   DataWidth:0x8    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_5_E5                                                               0x1f1430UL //Access:RW   DataWidth:0x8    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_6_E5                                                               0x1f1434UL //Access:RW   DataWidth:0x8    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_7_E5                                                               0x1f1438UL //Access:RW   DataWidth:0x8    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_8_E5                                                               0x1f143cUL //Access:RW   DataWidth:0x8    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_9_E5                                                               0x1f1440UL //Access:RW   DataWidth:0x8    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_10_E5                                                              0x1f1444UL //Access:RW   DataWidth:0x8    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_11_E5                                                              0x1f1448UL //Access:RW   DataWidth:0x8    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_12_E5                                                              0x1f144cUL //Access:RW   DataWidth:0x8    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_13_E5                                                              0x1f1450UL //Access:RW   DataWidth:0x8    // 
+#define PRS_REG_IPV6_EXT_FRAGMENT_HDR_TYPE_E5                                                                0x1f1454UL //Access:RW   DataWidth:0x8    // 
+#define PRS_REG_IPV6_EXT_AUTHENTICATION_HDR_TYPE_E5                                                          0x1f1458UL //Access:RW   DataWidth:0x8    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_0_VALID_E5                                                         0x1f145cUL //Access:RW   DataWidth:0x1    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_1_VALID_E5                                                         0x1f1460UL //Access:RW   DataWidth:0x1    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_2_VALID_E5                                                         0x1f1464UL //Access:RW   DataWidth:0x1    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_3_VALID_E5                                                         0x1f1468UL //Access:RW   DataWidth:0x1    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_4_VALID_E5                                                         0x1f146cUL //Access:RW   DataWidth:0x1    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_5_VALID_E5                                                         0x1f1470UL //Access:RW   DataWidth:0x1    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_6_VALID_E5                                                         0x1f1474UL //Access:RW   DataWidth:0x1    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_7_VALID_E5                                                         0x1f1478UL //Access:RW   DataWidth:0x1    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_8_VALID_E5                                                         0x1f147cUL //Access:RW   DataWidth:0x1    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_9_VALID_E5                                                         0x1f1480UL //Access:RW   DataWidth:0x1    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_10_VALID_E5                                                        0x1f1484UL //Access:RW   DataWidth:0x1    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_11_VALID_E5                                                        0x1f1488UL //Access:RW   DataWidth:0x1    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_12_VALID_E5                                                        0x1f148cUL //Access:RW   DataWidth:0x1    // 
+#define PRS_REG_IPV6_EXT_UNIFORM_HDR_TYPE_13_VALID_E5                                                        0x1f1490UL //Access:RW   DataWidth:0x1    // 
+#define PRS_REG_IPV6_EXT_FRAGMENT_HDR_TYPE_VALID_E5                                                          0x1f1494UL //Access:RW   DataWidth:0x1    // 
+#define PRS_REG_IPV6_EXT_AUTHENTICATION_HDR_TYPE_VALID_E5                                                    0x1f1498UL //Access:RW   DataWidth:0x1    // 
+#define PRS_REG_PACKET_REGION_0_BB_K2                                                                        0x1f0100UL //Access:RW   DataWidth:0x8    // Context region for received Ethernet packet with a match and packet type 0. Used in CFC load request message.
+#define PRS_REG_PACKET_REGION_0_E5                                                                           0x1f149cUL //Access:RW   DataWidth:0x8    // Context region for received Ethernet packet with a match and packet type 0. Used in CFC load request message.
+#define PRS_REG_PACKET_REGION_1_BB_K2                                                                        0x1f0104UL //Access:RW   DataWidth:0x8    // Context region for received Ethernet packet with a match and packet type 1. Used in CFC load request message.
+#define PRS_REG_PACKET_REGION_1_E5                                                                           0x1f14a0UL //Access:RW   DataWidth:0x8    // Context region for received Ethernet packet with a match and packet type 1. Used in CFC load request message.
+#define PRS_REG_PACKET_REGION_2_BB_K2                                                                        0x1f0108UL //Access:RW   DataWidth:0x8    // Context region for received Ethernet packet with a match and packet type 2. Used in CFC load request message.
+#define PRS_REG_PACKET_REGION_2_E5                                                                           0x1f14a4UL //Access:RW   DataWidth:0x8    // Context region for received Ethernet packet with a match and packet type 2. Used in CFC load request message.
+#define PRS_REG_PACKET_REGION_3_BB_K2                                                                        0x1f010cUL //Access:RW   DataWidth:0x8    // Context region for received Ethernet packet with a match and packet type 3. Used in CFC load request message.
+#define PRS_REG_PACKET_REGION_3_E5                                                                           0x1f14a8UL //Access:RW   DataWidth:0x8    // Context region for received Ethernet packet with a match and packet type 3. Used in CFC load request message.
+#define PRS_REG_PACKET_REGION_4_BB_K2                                                                        0x1f0110UL //Access:RW   DataWidth:0x8    // Context region for received Ethernet packet with a match and packet type 4. Used in CFC load request message.
+#define PRS_REG_PACKET_REGION_4_E5                                                                           0x1f14acUL //Access:RW   DataWidth:0x8    // Context region for received Ethernet packet with a match and packet type 4. Used in CFC load request message.
+#define PRS_REG_PACKET_REGION_5_BB_K2                                                                        0x1f0114UL //Access:RW   DataWidth:0x8    // Context region for received Ethernet packet with a match and packet type 5. Used in CFC load request message.
+#define PRS_REG_PACKET_REGION_5_E5                                                                           0x1f14b0UL //Access:RW   DataWidth:0x8    // Context region for received Ethernet packet with a match and packet type 5. Used in CFC load request message.
+#define PRS_REG_PACKET_REGION_6_BB_K2                                                                        0x1f0118UL //Access:RW   DataWidth:0x8    // Context region for received Ethernet packet with a match and packet type 6. Used in CFC load request message.
+#define PRS_REG_PACKET_REGION_6_E5                                                                           0x1f14b4UL //Access:RW   DataWidth:0x8    // Context region for received Ethernet packet with a match and packet type 6. Used in CFC load request message.
+#define PRS_REG_PACKET_REGION_7_BB_K2                                                                        0x1f011cUL //Access:RW   DataWidth:0x8    // Context region for received Ethernet packet with a match and packet type 7. Used in CFC load request message.
+#define PRS_REG_PACKET_REGION_7_E5                                                                           0x1f14b8UL //Access:RW   DataWidth:0x8    // Context region for received Ethernet packet with a match and packet type 7. Used in CFC load request message.
+#define PRS_REG_PACKET_REGION_8_E5                                                                           0x1f14bcUL //Access:RW   DataWidth:0x8    // Context region for received Ethernet packet with a match and packet type 8. Used in CFC load request message.
+#define PRS_REG_PACKET_REGION_9_E5                                                                           0x1f14c0UL //Access:RW   DataWidth:0x8    // Context region for received Ethernet packet with a match and packet type 9. Used in CFC load request message.
+#define PRS_REG_PACKET_REGION_10_E5                                                                          0x1f14c4UL //Access:RW   DataWidth:0x8    // Context region for received Ethernet packet with a match and packet type 10. Used in CFC load request message.
+#define PRS_REG_PACKET_REGION_11_E5                                                                          0x1f14c8UL //Access:RW   DataWidth:0x8    // Context region for received Ethernet packet with a match and packet type 11. Used in CFC load request message.
+#define PRS_REG_PACKET_REGION_12_E5                                                                          0x1f14ccUL //Access:RW   DataWidth:0x8    // Context region for received Ethernet packet with a match and packet type 12. Used in CFC load request message.
+#define PRS_REG_PACKET_REGION_13_E5                                                                          0x1f14d0UL //Access:RW   DataWidth:0x8    // Context region for received Ethernet packet with a match and packet type 13. Used in CFC load request message.
+#define PRS_REG_PACKET_REGION_14_E5                                                                          0x1f14d4UL //Access:RW   DataWidth:0x8    // Context region for received Ethernet packet with a match and packet type 14. Used in CFC load request message.
+#define PRS_REG_PACKET_REGION_15_E5                                                                          0x1f14d8UL //Access:RW   DataWidth:0x8    // Context region for received Ethernet packet with a match and packet type 15. Used in CFC load request message.
+#define PRS_REG_OUTPUT_FORMAT_IPV6_EXT_PTLD_0_E5                                                             0x1f14dcUL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in PTLD message for ipv6 extension. The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_IPV6_EXT_PTLD_1_E5                                                             0x1f14e0UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in PTLD message for ipv6 extension. The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_AGG_TUNNELING_PTLD_0_E5                                                        0x1f14e4UL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in PTLD message for aggregated tunnel.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_AGG_TUNNELING_PTLD_1_E5                                                        0x1f14e8UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in PTLD message for aggregated tunnel.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_AGG_PTLD_0_E5                                                                  0x1f14ecUL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in PTLD message for aggregated.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_AGG_PTLD_1_E5                                                                  0x1f14f0UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in PTLD message for aggregated.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_TUNNELING_CACHED_MAC_VLAN_PTLD_0_E5                                            0x1f14f4UL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in PTLD message for tunneling cached mac vlan hit.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_TUNNELING_CACHED_MAC_VLAN_PTLD_1_E5                                            0x1f14f8UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in PTLD message for tunneling cached mac vlan hit.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_TUNNELING_PTLD_0_E5                                                            0x1f14fcUL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in PTLD message for tunneling.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_TUNNELING_PTLD_1_E5                                                            0x1f1500UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in PTLD message for tunneling.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_CACHED_MAC_VLAN_PTLD_0_E5                                                      0x1f1504UL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in PTLD message for cache mac vlan hit.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_CACHED_MAC_VLAN_PTLD_1_E5                                                      0x1f1508UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in PTLD message for cache mac vlan hit.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_REGULAR_PTLD_0_E5                                                              0x1f150cUL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in PTLD message for regular packet.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_REGULAR_PTLD_1_E5                                                              0x1f1510UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in PTLD message for regular packet.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_IPV6_EXT_RGFS_0_E5                                                             0x1f1514UL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in RGFS message for ipv6 extension.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_IPV6_EXT_RGFS_1_E5                                                             0x1f1518UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in RGFS message for ipv6 extension.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_AGG_TUNNELING_RGFS_0_E5                                                        0x1f151cUL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in RGFS message for aggregated tunnel.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_AGG_TUNNELING_RGFS_1_E5                                                        0x1f1520UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in RGFS message for aggregated tunnel.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_AGG_RGFS_0_E5                                                                  0x1f1524UL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in RGFS message for aggregated.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_AGG_RGFS_1_E5                                                                  0x1f1528UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in RGFS message for aggregated.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_TUNNELING_CACHED_MAC_VLAN_RGFS_0_E5                                            0x1f152cUL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in RGFS message for tunneling cached mac vlan hit.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_TUNNELING_CACHED_MAC_VLAN_RGFS_1_E5                                            0x1f1530UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in RGFS message for tunneling cached mac vlan hit.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_TUNNELING_RGFS_0_E5                                                            0x1f1534UL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in RGFS message for tunneling.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_TUNNELING_RGFS_1_E5                                                            0x1f1538UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in RGFS message for tunneling.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_CACHED_MAC_VLAN_RGFS_0_E5                                                      0x1f153cUL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in RGFS message for cache mac vlan hit.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_CACHED_MAC_VLAN_RGFS_1_E5                                                      0x1f1540UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in RGFS message for cache mac vlan hit.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_REGULAR_RGFS_0_E5                                                              0x1f1544UL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in RGFS message for regular packet.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_OUTPUT_FORMAT_REGULAR_RGFS_1_E5                                                              0x1f1548UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in RGFS message for regular packet.The same building block shouldn't be used for both RGFS and PTLD.
+#define PRS_REG_PURE_REGION_0_BB_K2                                                                          0x1f0120UL //Access:RW   DataWidth:0x8    // Context region for pure acknowledge packets with connection type 0. Used in CFC load request message.
+#define PRS_REG_PURE_REGION_0_E5                                                                             0x1f154cUL //Access:RW   DataWidth:0x8    // Context region for pure acknowledge packets with connection type 0. Used in CFC load request message.
+#define PRS_REG_PURE_REGION_1_BB_K2                                                                          0x1f0124UL //Access:RW   DataWidth:0x8    // Context region for pure acknowledge packets with connection type 1. Used in CFC load request message.
+#define PRS_REG_PURE_REGION_1_E5                                                                             0x1f1550UL //Access:RW   DataWidth:0x8    // Context region for pure acknowledge packets with connection type 1. Used in CFC load request message.
+#define PRS_REG_PURE_REGION_2_BB_K2                                                                          0x1f0128UL //Access:RW   DataWidth:0x8    // Context region for pure acknowledge packets with connection type 2. Used in CFC load request message.
+#define PRS_REG_PURE_REGION_2_E5                                                                             0x1f1554UL //Access:RW   DataWidth:0x8    // Context region for pure acknowledge packets with connection type 2. Used in CFC load request message.
+#define PRS_REG_PURE_REGION_3_BB_K2                                                                          0x1f012cUL //Access:RW   DataWidth:0x8    // Context region for pure acknowledge packets with connection type 3. Used in CFC load request message.
+#define PRS_REG_PURE_REGION_3_E5                                                                             0x1f1558UL //Access:RW   DataWidth:0x8    // Context region for pure acknowledge packets with connection type 3. Used in CFC load request message.
+#define PRS_REG_PURE_REGION_4_BB_K2                                                                          0x1f0130UL //Access:RW   DataWidth:0x8    // Context region for pure acknowledge packets with connection type 4. Used in CFC load request message.
+#define PRS_REG_PURE_REGION_4_E5                                                                             0x1f155cUL //Access:RW   DataWidth:0x8    // Context region for pure acknowledge packets with connection type 4. Used in CFC load request message.
+#define PRS_REG_PURE_REGION_5_BB_K2                                                                          0x1f0134UL //Access:RW   DataWidth:0x8    // Context region for pure acknowledge packets with connection type 5. Used in CFC load request message.
+#define PRS_REG_PURE_REGION_5_E5                                                                             0x1f1560UL //Access:RW   DataWidth:0x8    // Context region for pure acknowledge packets with connection type 5. Used in CFC load request message.
+#define PRS_REG_PURE_REGION_6_BB_K2                                                                          0x1f0138UL //Access:RW   DataWidth:0x8    // Context region for pure acknowledge packets with connection type 6. Used in CFC load request message.
+#define PRS_REG_PURE_REGION_6_E5                                                                             0x1f1564UL //Access:RW   DataWidth:0x8    // Context region for pure acknowledge packets with connection type 6. Used in CFC load request message.
+#define PRS_REG_PURE_REGION_7_BB_K2                                                                          0x1f013cUL //Access:RW   DataWidth:0x8    // Context region for pure acknowledge packets with connection type 7. Used in CFC load request message.
+#define PRS_REG_PURE_REGION_7_E5                                                                             0x1f1568UL //Access:RW   DataWidth:0x8    // Context region for pure acknowledge packets with connection type 7. Used in CFC load request message.
+#define PRS_REG_PURE_REGION_8_E5                                                                             0x1f156cUL //Access:RW   DataWidth:0x8    // Context region for pure acknowledge packets with connection type 8. Used in CFC load request message.
+#define PRS_REG_PURE_REGION_9_E5                                                                             0x1f1570UL //Access:RW   DataWidth:0x8    // Context region for pure acknowledge packets with connection type 9. Used in CFC load request message.
+#define PRS_REG_PURE_REGION_10_E5                                                                            0x1f1574UL //Access:RW   DataWidth:0x8    // Context region for pure acknowledge packets with connection type 10. Used in CFC load request message.
+#define PRS_REG_PURE_REGION_11_E5                                                                            0x1f1578UL //Access:RW   DataWidth:0x8    // Context region for pure acknowledge packets with connection type 11. Used in CFC load request message.
+#define PRS_REG_PURE_REGION_12_E5                                                                            0x1f157cUL //Access:RW   DataWidth:0x8    // Context region for pure acknowledge packets with connection type 12. Used in CFC load request message.
+#define PRS_REG_PURE_REGION_13_E5                                                                            0x1f1580UL //Access:RW   DataWidth:0x8    // Context region for pure acknowledge packets with connection type 13. Used in CFC load request message.
+#define PRS_REG_PURE_REGION_14_E5                                                                            0x1f1584UL //Access:RW   DataWidth:0x8    // Context region for pure acknowledge packets with connection type 14. Used in CFC load request message.
+#define PRS_REG_PURE_REGION_15_E5                                                                            0x1f1588UL //Access:RW   DataWidth:0x8    // Context region for pure acknowledge packets with connection type 15. Used in CFC load request message.
+#define PRS_REG_CON_INC_VALUE_0_BB_K2                                                                        0x1f0144UL //Access:RW   DataWidth:0x8    // The increment value to send in the CCFC load request message for connection type 0.
+#define PRS_REG_CON_INC_VALUE_0_E5                                                                           0x1f158cUL //Access:RW   DataWidth:0x8    // The increment value to send in the CCFC load request message for connection type 0.
+#define PRS_REG_CON_INC_VALUE_1_BB_K2                                                                        0x1f0148UL //Access:RW   DataWidth:0x8    // The increment value to send in the CCFC load request message for connection type 1.
+#define PRS_REG_CON_INC_VALUE_1_E5                                                                           0x1f1590UL //Access:RW   DataWidth:0x8    // The increment value to send in the CCFC load request message for connection type 1.
+#define PRS_REG_CON_INC_VALUE_2_BB_K2                                                                        0x1f014cUL //Access:RW   DataWidth:0x8    // The increment value to send in the CCFC load request message for connection type 2.
+#define PRS_REG_CON_INC_VALUE_2_E5                                                                           0x1f1594UL //Access:RW   DataWidth:0x8    // The increment value to send in the CCFC load request message for connection type 2.
+#define PRS_REG_CON_INC_VALUE_3_BB_K2                                                                        0x1f0150UL //Access:RW   DataWidth:0x8    // The increment value to send in the CCFC load request message for connection type 3.
+#define PRS_REG_CON_INC_VALUE_3_E5                                                                           0x1f1598UL //Access:RW   DataWidth:0x8    // The increment value to send in the CCFC load request message for connection type 3.
+#define PRS_REG_CON_INC_VALUE_4_BB_K2                                                                        0x1f0154UL //Access:RW   DataWidth:0x8    // The increment value to send in the CCFC load request message for connection type 4.
+#define PRS_REG_CON_INC_VALUE_4_E5                                                                           0x1f159cUL //Access:RW   DataWidth:0x8    // The increment value to send in the CCFC load request message for connection type 4.
+#define PRS_REG_CON_INC_VALUE_5_BB_K2                                                                        0x1f0158UL //Access:RW   DataWidth:0x8    // The increment value to send in the CCFC load request message for connection type 5.
+#define PRS_REG_CON_INC_VALUE_5_E5                                                                           0x1f15a0UL //Access:RW   DataWidth:0x8    // The increment value to send in the CCFC load request message for connection type 5.
+#define PRS_REG_CON_INC_VALUE_6_BB_K2                                                                        0x1f015cUL //Access:RW   DataWidth:0x8    // The increment value to send in the CCFC load request message for connection type 6.
+#define PRS_REG_CON_INC_VALUE_6_E5                                                                           0x1f15a4UL //Access:RW   DataWidth:0x8    // The increment value to send in the CCFC load request message for connection type 6.
+#define PRS_REG_CON_INC_VALUE_7_BB_K2                                                                        0x1f0160UL //Access:RW   DataWidth:0x8    // The increment value to send in the CCFC load request message for connection type 7.
+#define PRS_REG_CON_INC_VALUE_7_E5                                                                           0x1f15a8UL //Access:RW   DataWidth:0x8    // The increment value to send in the CCFC load request message for connection type 7.
+#define PRS_REG_CON_INC_VALUE_8_E5                                                                           0x1f15acUL //Access:RW   DataWidth:0x8    // The increment value to send in the CCFC load request message for connection type 8.
+#define PRS_REG_CON_INC_VALUE_9_E5                                                                           0x1f15b0UL //Access:RW   DataWidth:0x8    // The increment value to send in the CCFC load request message for connection type 9.
+#define PRS_REG_CON_INC_VALUE_10_E5                                                                          0x1f15b4UL //Access:RW   DataWidth:0x8    // The increment value to send in the CCFC load request message for connection type 10.
+#define PRS_REG_CON_INC_VALUE_11_E5                                                                          0x1f15b8UL //Access:RW   DataWidth:0x8    // The increment value to send in the CCFC load request message for connection type 11.
+#define PRS_REG_CON_INC_VALUE_12_E5                                                                          0x1f15bcUL //Access:RW   DataWidth:0x8    // The increment value to send in the CCFC load request message for connection type 12.
+#define PRS_REG_CON_INC_VALUE_13_E5                                                                          0x1f15c0UL //Access:RW   DataWidth:0x8    // The increment value to send in the CCFC load request message for connection type 13.
+#define PRS_REG_CON_INC_VALUE_14_E5                                                                          0x1f15c4UL //Access:RW   DataWidth:0x8    // The increment value to send in the CCFC load request message for connection type 14.
+#define PRS_REG_CON_INC_VALUE_15_E5                                                                          0x1f15c8UL //Access:RW   DataWidth:0x8    // The increment value to send in the CCFC load request message for connection type 15.
+#define PRS_REG_CM_HDR_EVENT_ID_0_BB_K2                                                                      0x1f0914UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+#define PRS_REG_CM_HDR_EVENT_ID_0_E5                                                                         0x1f15ccUL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PRS_REG_CM_HDR_EVENT_ID_0_EVENT_ID                                                                 (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 0
+  #define PRS_REG_CM_HDR_EVENT_ID_0_EVENT_ID_SHIFT                                                           0
+  #define PRS_REG_CM_HDR_EVENT_ID_0_CM_HDR                                                                   (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 0. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_CM_HDR_EVENT_ID_0_CM_HDR_SHIFT                                                             8
+  #define PRS_REG_CM_HDR_EVENT_ID_0_AFFINITY_TYPE_E5                                                         (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_CM_HDR_EVENT_ID_0_AFFINITY_TYPE_E5_SHIFT                                                   18
+#define PRS_REG_CM_HDR_EVENT_ID_1_BB_K2                                                                      0x1f0918UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+#define PRS_REG_CM_HDR_EVENT_ID_1_E5                                                                         0x1f15d0UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PRS_REG_CM_HDR_EVENT_ID_1_EVENT_ID                                                                 (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 1
+  #define PRS_REG_CM_HDR_EVENT_ID_1_EVENT_ID_SHIFT                                                           0
+  #define PRS_REG_CM_HDR_EVENT_ID_1_CM_HDR                                                                   (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 1. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_CM_HDR_EVENT_ID_1_CM_HDR_SHIFT                                                             8
+  #define PRS_REG_CM_HDR_EVENT_ID_1_AFFINITY_TYPE_E5                                                         (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_CM_HDR_EVENT_ID_1_AFFINITY_TYPE_E5_SHIFT                                                   18
+#define PRS_REG_CM_HDR_EVENT_ID_2_BB_K2                                                                      0x1f091cUL //Access:RW   DataWidth:0x12   // Multi Field Register.
+#define PRS_REG_CM_HDR_EVENT_ID_2_E5                                                                         0x1f15d4UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PRS_REG_CM_HDR_EVENT_ID_2_EVENT_ID                                                                 (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 2
+  #define PRS_REG_CM_HDR_EVENT_ID_2_EVENT_ID_SHIFT                                                           0
+  #define PRS_REG_CM_HDR_EVENT_ID_2_CM_HDR                                                                   (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 2. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_CM_HDR_EVENT_ID_2_CM_HDR_SHIFT                                                             8
+  #define PRS_REG_CM_HDR_EVENT_ID_2_AFFINITY_TYPE_E5                                                         (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_CM_HDR_EVENT_ID_2_AFFINITY_TYPE_E5_SHIFT                                                   18
+#define PRS_REG_CM_HDR_EVENT_ID_3_BB_K2                                                                      0x1f0920UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+#define PRS_REG_CM_HDR_EVENT_ID_3_E5                                                                         0x1f15d8UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PRS_REG_CM_HDR_EVENT_ID_3_EVENT_ID                                                                 (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 3
+  #define PRS_REG_CM_HDR_EVENT_ID_3_EVENT_ID_SHIFT                                                           0
+  #define PRS_REG_CM_HDR_EVENT_ID_3_CM_HDR                                                                   (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 3. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_CM_HDR_EVENT_ID_3_CM_HDR_SHIFT                                                             8
+  #define PRS_REG_CM_HDR_EVENT_ID_3_AFFINITY_TYPE_E5                                                         (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_CM_HDR_EVENT_ID_3_AFFINITY_TYPE_E5_SHIFT                                                   18
+#define PRS_REG_CM_HDR_EVENT_ID_4_BB_K2                                                                      0x1f0924UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+#define PRS_REG_CM_HDR_EVENT_ID_4_E5                                                                         0x1f15dcUL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PRS_REG_CM_HDR_EVENT_ID_4_EVENT_ID                                                                 (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 4
+  #define PRS_REG_CM_HDR_EVENT_ID_4_EVENT_ID_SHIFT                                                           0
+  #define PRS_REG_CM_HDR_EVENT_ID_4_CM_HDR                                                                   (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 4. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_CM_HDR_EVENT_ID_4_CM_HDR_SHIFT                                                             8
+  #define PRS_REG_CM_HDR_EVENT_ID_4_AFFINITY_TYPE_E5                                                         (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_CM_HDR_EVENT_ID_4_AFFINITY_TYPE_E5_SHIFT                                                   18
+#define PRS_REG_CM_HDR_EVENT_ID_5_BB_K2                                                                      0x1f0928UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+#define PRS_REG_CM_HDR_EVENT_ID_5_E5                                                                         0x1f15e0UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PRS_REG_CM_HDR_EVENT_ID_5_EVENT_ID                                                                 (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 5
+  #define PRS_REG_CM_HDR_EVENT_ID_5_EVENT_ID_SHIFT                                                           0
+  #define PRS_REG_CM_HDR_EVENT_ID_5_CM_HDR                                                                   (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 5. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_CM_HDR_EVENT_ID_5_CM_HDR_SHIFT                                                             8
+  #define PRS_REG_CM_HDR_EVENT_ID_5_AFFINITY_TYPE_E5                                                         (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_CM_HDR_EVENT_ID_5_AFFINITY_TYPE_E5_SHIFT                                                   18
+#define PRS_REG_CM_HDR_EVENT_ID_6_BB_K2                                                                      0x1f092cUL //Access:RW   DataWidth:0x12   // Multi Field Register.
+#define PRS_REG_CM_HDR_EVENT_ID_6_E5                                                                         0x1f15e4UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PRS_REG_CM_HDR_EVENT_ID_6_EVENT_ID                                                                 (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 6
+  #define PRS_REG_CM_HDR_EVENT_ID_6_EVENT_ID_SHIFT                                                           0
+  #define PRS_REG_CM_HDR_EVENT_ID_6_CM_HDR                                                                   (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 6. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_CM_HDR_EVENT_ID_6_CM_HDR_SHIFT                                                             8
+  #define PRS_REG_CM_HDR_EVENT_ID_6_AFFINITY_TYPE_E5                                                         (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_CM_HDR_EVENT_ID_6_AFFINITY_TYPE_E5_SHIFT                                                   18
+#define PRS_REG_CM_HDR_EVENT_ID_7_BB_K2                                                                      0x1f0930UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+#define PRS_REG_CM_HDR_EVENT_ID_7_E5                                                                         0x1f15e8UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PRS_REG_CM_HDR_EVENT_ID_7_EVENT_ID                                                                 (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 7
+  #define PRS_REG_CM_HDR_EVENT_ID_7_EVENT_ID_SHIFT                                                           0
+  #define PRS_REG_CM_HDR_EVENT_ID_7_CM_HDR                                                                   (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 7. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_CM_HDR_EVENT_ID_7_CM_HDR_SHIFT                                                             8
+  #define PRS_REG_CM_HDR_EVENT_ID_7_AFFINITY_TYPE_E5                                                         (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_CM_HDR_EVENT_ID_7_AFFINITY_TYPE_E5_SHIFT                                                   18
+#define PRS_REG_CM_HDR_EVENT_ID_8_E5                                                                         0x1f15ecUL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PRS_REG_CM_HDR_EVENT_ID_8_EVENT_ID_E5                                                              (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 8
+  #define PRS_REG_CM_HDR_EVENT_ID_8_EVENT_ID_E5_SHIFT                                                        0
+  #define PRS_REG_CM_HDR_EVENT_ID_8_CM_HDR_E5                                                                (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 8. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_CM_HDR_EVENT_ID_8_CM_HDR_E5_SHIFT                                                          8
+  #define PRS_REG_CM_HDR_EVENT_ID_8_AFFINITY_TYPE_E5                                                         (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_CM_HDR_EVENT_ID_8_AFFINITY_TYPE_E5_SHIFT                                                   18
+#define PRS_REG_CM_HDR_EVENT_ID_9_E5                                                                         0x1f15f0UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PRS_REG_CM_HDR_EVENT_ID_9_EVENT_ID_E5                                                              (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 9
+  #define PRS_REG_CM_HDR_EVENT_ID_9_EVENT_ID_E5_SHIFT                                                        0
+  #define PRS_REG_CM_HDR_EVENT_ID_9_CM_HDR_E5                                                                (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 9. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_CM_HDR_EVENT_ID_9_CM_HDR_E5_SHIFT                                                          8
+  #define PRS_REG_CM_HDR_EVENT_ID_9_AFFINITY_TYPE_E5                                                         (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_CM_HDR_EVENT_ID_9_AFFINITY_TYPE_E5_SHIFT                                                   18
+#define PRS_REG_CM_HDR_EVENT_ID_10_E5                                                                        0x1f15f4UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PRS_REG_CM_HDR_EVENT_ID_10_EVENT_ID_E5                                                             (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 10
+  #define PRS_REG_CM_HDR_EVENT_ID_10_EVENT_ID_E5_SHIFT                                                       0
+  #define PRS_REG_CM_HDR_EVENT_ID_10_CM_HDR_E5                                                               (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 10. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_CM_HDR_EVENT_ID_10_CM_HDR_E5_SHIFT                                                         8
+  #define PRS_REG_CM_HDR_EVENT_ID_10_AFFINITY_TYPE_E5                                                        (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_CM_HDR_EVENT_ID_10_AFFINITY_TYPE_E5_SHIFT                                                  18
+#define PRS_REG_CM_HDR_EVENT_ID_11_E5                                                                        0x1f15f8UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PRS_REG_CM_HDR_EVENT_ID_11_EVENT_ID_E5                                                             (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 11
+  #define PRS_REG_CM_HDR_EVENT_ID_11_EVENT_ID_E5_SHIFT                                                       0
+  #define PRS_REG_CM_HDR_EVENT_ID_11_CM_HDR_E5                                                               (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 11. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_CM_HDR_EVENT_ID_11_CM_HDR_E5_SHIFT                                                         8
+  #define PRS_REG_CM_HDR_EVENT_ID_11_AFFINITY_TYPE_E5                                                        (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_CM_HDR_EVENT_ID_11_AFFINITY_TYPE_E5_SHIFT                                                  18
+#define PRS_REG_CM_HDR_EVENT_ID_12_E5                                                                        0x1f15fcUL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PRS_REG_CM_HDR_EVENT_ID_12_EVENT_ID_E5                                                             (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 12
+  #define PRS_REG_CM_HDR_EVENT_ID_12_EVENT_ID_E5_SHIFT                                                       0
+  #define PRS_REG_CM_HDR_EVENT_ID_12_CM_HDR_E5                                                               (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 12. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_CM_HDR_EVENT_ID_12_CM_HDR_E5_SHIFT                                                         8
+  #define PRS_REG_CM_HDR_EVENT_ID_12_AFFINITY_TYPE_E5                                                        (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_CM_HDR_EVENT_ID_12_AFFINITY_TYPE_E5_SHIFT                                                  18
+#define PRS_REG_CM_HDR_EVENT_ID_13_E5                                                                        0x1f1600UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PRS_REG_CM_HDR_EVENT_ID_13_EVENT_ID_E5                                                             (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 13
+  #define PRS_REG_CM_HDR_EVENT_ID_13_EVENT_ID_E5_SHIFT                                                       0
+  #define PRS_REG_CM_HDR_EVENT_ID_13_CM_HDR_E5                                                               (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 13. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_CM_HDR_EVENT_ID_13_CM_HDR_E5_SHIFT                                                         8
+  #define PRS_REG_CM_HDR_EVENT_ID_13_AFFINITY_TYPE_E5                                                        (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_CM_HDR_EVENT_ID_13_AFFINITY_TYPE_E5_SHIFT                                                  18
+#define PRS_REG_CM_HDR_EVENT_ID_14_E5                                                                        0x1f1604UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PRS_REG_CM_HDR_EVENT_ID_14_EVENT_ID_E5                                                             (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 14
+  #define PRS_REG_CM_HDR_EVENT_ID_14_EVENT_ID_E5_SHIFT                                                       0
+  #define PRS_REG_CM_HDR_EVENT_ID_14_CM_HDR_E5                                                               (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 14. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_CM_HDR_EVENT_ID_14_CM_HDR_E5_SHIFT                                                         8
+  #define PRS_REG_CM_HDR_EVENT_ID_14_AFFINITY_TYPE_E5                                                        (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_CM_HDR_EVENT_ID_14_AFFINITY_TYPE_E5_SHIFT                                                  18
+#define PRS_REG_CM_HDR_EVENT_ID_15_E5                                                                        0x1f1608UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PRS_REG_CM_HDR_EVENT_ID_15_EVENT_ID_E5                                                             (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 15
+  #define PRS_REG_CM_HDR_EVENT_ID_15_EVENT_ID_E5_SHIFT                                                       0
+  #define PRS_REG_CM_HDR_EVENT_ID_15_CM_HDR_E5                                                               (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 15. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_CM_HDR_EVENT_ID_15_CM_HDR_E5_SHIFT                                                         8
+  #define PRS_REG_CM_HDR_EVENT_ID_15_AFFINITY_TYPE_E5                                                        (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_CM_HDR_EVENT_ID_15_AFFINITY_TYPE_E5_SHIFT                                                  18
+#define PRS_REG_OUTPUT_FORMAT_0_0_BB_K2                                                                      0x1f097cUL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in TSTORM message for connection type 0. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_0_0_E5                                                                         0x1f160cUL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in PTLD message for connection type 0. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_0_1_BB_K2                                                                      0x1f0980UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in TSTORM message for connection type 0. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_0_1_E5                                                                         0x1f1610UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in PTLD message for connection type 0. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_1_0_BB_K2                                                                      0x1f0984UL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in TSTORM message for connection type 1. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_1_0_E5                                                                         0x1f1614UL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in PTLD message for connection type 1. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_1_1_BB_K2                                                                      0x1f0988UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in TSTORM message for connection type 1. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_1_1_E5                                                                         0x1f1618UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in PTLD message for connection type 1. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_2_0_BB_K2                                                                      0x1f098cUL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in TSTORM message for connection type 2. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_2_0_E5                                                                         0x1f161cUL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in PTLD message for connection type 2. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_2_1_BB_K2                                                                      0x1f0990UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in TSTORM message for connection type 2. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_2_1_E5                                                                         0x1f1620UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in PTLD message for connection type 2. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_3_0_BB_K2                                                                      0x1f0994UL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in TSTORM message for connection type 3. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_3_0_E5                                                                         0x1f1624UL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in PTLD message for connection type 3. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_3_1_BB_K2                                                                      0x1f0998UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in TSTORM message for connection type 3. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_3_1_E5                                                                         0x1f1628UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in PTLD message for connection type 3. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_4_0_BB_K2                                                                      0x1f099cUL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in TSTORM message for connection type 4. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_4_0_E5                                                                         0x1f162cUL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in PTLD message for connection type 4. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_4_1_BB_K2                                                                      0x1f09a0UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in TSTORM message for connection type 4. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_4_1_E5                                                                         0x1f1630UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in PTLD message for connection type 4. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_5_0_BB_K2                                                                      0x1f09a4UL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in TSTORM message for connection type 5. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_5_0_E5                                                                         0x1f1634UL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in PTLD message for connection type 5. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_5_1_BB_K2                                                                      0x1f09a8UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in TSTORM message for connection type 5. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_5_1_E5                                                                         0x1f1638UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in PTLD message for connection type 5. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_6_0_BB_K2                                                                      0x1f09acUL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in TSTORM message for connection type 6. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_6_0_E5                                                                         0x1f163cUL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in PTLD message for connection type 6. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_6_1_BB_K2                                                                      0x1f09b0UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in TSTORM message for connection type 6. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_6_1_E5                                                                         0x1f1640UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in PTLD message for connection type 6. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_7_0_BB_K2                                                                      0x1f09b4UL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in TSTORM message for connection type 7. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_7_0_E5                                                                         0x1f1644UL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in PTLD message for connection type 7. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_7_1_BB_K2                                                                      0x1f09b8UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in TSTORM message for connection type 7. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_7_1_E5                                                                         0x1f1648UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in PTLD message for connection type 7. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_8_0_E5                                                                         0x1f164cUL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in PTLD message for connection type 8. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_8_1_E5                                                                         0x1f1650UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in PTLD message for connection type 8. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_9_0_E5                                                                         0x1f1654UL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in PTLD message for connection type 9. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_9_1_E5                                                                         0x1f1658UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in PTLD message for connection type 9. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_10_0_E5                                                                        0x1f165cUL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in PTLD message for connection type 10. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_10_1_E5                                                                        0x1f1660UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in PTLD message for connection type 10. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_11_0_E5                                                                        0x1f1664UL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in PTLD message for connection type 11. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_11_1_E5                                                                        0x1f1668UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in PTLD message for connection type 11. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_12_0_E5                                                                        0x1f166cUL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in PTLD message for connection type 12. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_12_1_E5                                                                        0x1f1670UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in PTLD message for connection type 12. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_13_0_E5                                                                        0x1f1674UL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in PTLD message for connection type 13. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_13_1_E5                                                                        0x1f1678UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in PTLD message for connection type 13. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_14_0_E5                                                                        0x1f167cUL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in PTLD message for connection type 14. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_14_1_E5                                                                        0x1f1680UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in PTLD message for connection type 14. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_15_0_E5                                                                        0x1f1684UL //Access:RW   DataWidth:0x20   // Ordered list of building blocks in PTLD message for connection type 15. Unused blocks must be set to 0xf.
+#define PRS_REG_OUTPUT_FORMAT_15_1_E5                                                                        0x1f1688UL //Access:RW   DataWidth:0x10   // Ordered list of building blocks in PTLD message for connection type 15. Unused blocks must be set to 0xf.
+#define PRS_REG_IPV6_EXT_E5                                                                                  0x1f168cUL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define PRS_REG_IPV6_EXT_EVENT_ID_E5                                                                       (0xff<<0) // Event ID for ipv6_ext
+  #define PRS_REG_IPV6_EXT_EVENT_ID_E5_SHIFT                                                                 0
+  #define PRS_REG_IPV6_EXT_CM_HDR_E5                                                                         (0x3ff<<8) // The CM header. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_IPV6_EXT_CM_HDR_E5_SHIFT                                                                   8
+  #define PRS_REG_IPV6_EXT_AFFINITY_TYPE_E5                                                                  (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_IPV6_EXT_AFFINITY_TYPE_E5_SHIFT                                                            18
+  #define PRS_REG_IPV6_EXT_EN_L2_MA_E5                                                                       (0x1<<20) // en_l2_ma to be used in storm context update offset field of the cm header.
+  #define PRS_REG_IPV6_EXT_EN_L2_MA_E5_SHIFT                                                                 20
+  #define PRS_REG_IPV6_EXT_L2_MA_CONFIG_E5                                                                   (0x3<<21) // l2_ma_config to be used in storm context update offset field of the cm header.
+  #define PRS_REG_IPV6_EXT_L2_MA_CONFIG_E5_SHIFT                                                             21
+  #define PRS_REG_IPV6_EXT_INC_SN_E5                                                                         (0x1<<23) // inc_sn to be used in storm context update offset field of the cm header.
+  #define PRS_REG_IPV6_EXT_INC_SN_E5_SHIFT                                                                   23
+#define PRS_REG_AGG_TUNNEL_E5                                                                                0x1f1690UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define PRS_REG_AGG_TUNNEL_EVENT_ID_E5                                                                     (0xff<<0) // Event ID for agg_tunnel
+  #define PRS_REG_AGG_TUNNEL_EVENT_ID_E5_SHIFT                                                               0
+  #define PRS_REG_AGG_TUNNEL_CM_HDR_E5                                                                       (0x3ff<<8) // The CM header. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_AGG_TUNNEL_CM_HDR_E5_SHIFT                                                                 8
+  #define PRS_REG_AGG_TUNNEL_AFFINITY_TYPE_E5                                                                (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_AGG_TUNNEL_AFFINITY_TYPE_E5_SHIFT                                                          18
+  #define PRS_REG_AGG_TUNNEL_EN_L2_MA_E5                                                                     (0x1<<20) // en_l2_ma to be used in storm context update offset field of the cm header.
+  #define PRS_REG_AGG_TUNNEL_EN_L2_MA_E5_SHIFT                                                               20
+  #define PRS_REG_AGG_TUNNEL_L2_MA_CONFIG_E5                                                                 (0x3<<21) // l2_ma_config to be used in storm context update offset field of the cm header.
+  #define PRS_REG_AGG_TUNNEL_L2_MA_CONFIG_E5_SHIFT                                                           21
+  #define PRS_REG_AGG_TUNNEL_INC_SN_E5                                                                       (0x1<<23) // inc_sn to be used in storm context update offset field of the cm header.
+  #define PRS_REG_AGG_TUNNEL_INC_SN_E5_SHIFT                                                                 23
+#define PRS_REG_AGG_E5                                                                                       0x1f1694UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define PRS_REG_AGG_EVENT_ID_E5                                                                            (0xff<<0) // Event ID for aggregation
+  #define PRS_REG_AGG_EVENT_ID_E5_SHIFT                                                                      0
+  #define PRS_REG_AGG_CM_HDR_E5                                                                              (0x3ff<<8) // The CM header. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
+  #define PRS_REG_AGG_CM_HDR_E5_SHIFT                                                                        8
+  #define PRS_REG_AGG_AFFINITY_TYPE_E5                                                                       (0x3<<18) // Affinity type to be used in the CM header.
+  #define PRS_REG_AGG_AFFINITY_TYPE_E5_SHIFT                                                                 18
+  #define PRS_REG_AGG_EN_L2_MA_E5                                                                            (0x1<<20) // en_l2_ma to be used in storm context update offset field of the cm header.
+  #define PRS_REG_AGG_EN_L2_MA_E5_SHIFT                                                                      20
+  #define PRS_REG_AGG_L2_MA_CONFIG_E5                                                                        (0x3<<21) // l2_ma_config to be used in storm context update offset field of the cm header.
+  #define PRS_REG_AGG_L2_MA_CONFIG_E5_SHIFT                                                                  21
+  #define PRS_REG_AGG_INC_SN_E5                                                                              (0x1<<23) // inc_sn to be used in storm context update offset field of the cm header.
+  #define PRS_REG_AGG_INC_SN_E5_SHIFT                                                                        23
+#define PRS_REG_L2_HASH_CRC_INIT_VAL_E5                                                                      0x1f1698UL //Access:RW   DataWidth:0x8    // Initial value for L2 CRC hash machine
+#define PRS_REG_TCP_4_TUPLE_SEARCH_E5                                                                        0x1f169cUL //Access:RW   DataWidth:0x1    // 1- perform L2 CRC hash on TCP 4 tuple. 0- perform L2 CRC hash on IP source and dest only.
+#define PRS_REG_UDP_4_TUPLE_SEARCH_E5                                                                        0x1f16a0UL //Access:RW   DataWidth:0x1    // 1- perform L2 CRC hash on UDP 4 tuple. 0- perform L2 CRC hash on IP source and dest only.
+#define PRS_REG_ERROR_FLAGS_MASK_E5                                                                          0x1f16a4UL //Access:RW   DataWidth:0x10   // Used in the aggregatable decision logic
+#define PRS_REG_PARSING_ERROR_FLAGS_MASK_E5                                                                  0x1f16a8UL //Access:RW   DataWidth:0x10   // Used in the aggregatable decision logic
+#define PRS_REG_BASIC_REG_14_MASK_E5                                                                         0x1f16acUL //Access:RW   DataWidth:0x20   // Used in the aggregatable decision logic
+#define PRS_REG_BASIC_REG_5_MASK_E5                                                                          0x1f16b0UL //Access:RW   DataWidth:0x10   // Used in the aggregatable decision logic
+#define PRS_REG_ERROR_FLAGS_VAL_E5                                                                           0x1f16b4UL //Access:RW   DataWidth:0x10   // Used in the aggregatable decision logic
+#define PRS_REG_PARSING_ERROR_FLAGS_VAL_E5                                                                   0x1f16b8UL //Access:RW   DataWidth:0x10   // Used in the aggregatable decision logic
+#define PRS_REG_BASIC_REG_14_VAL_E5                                                                          0x1f16bcUL //Access:RW   DataWidth:0x20   // Used in the aggregatable decision logic
+#define PRS_REG_BASIC_REG_5_VAL_E5                                                                           0x1f16c0UL //Access:RW   DataWidth:0x10   // Used in the aggregatable decision logic
+#define PRS_REG_SAL_VLAN_EN_E5                                                                               0x1f16c4UL //Access:RW   DataWidth:0x1    // Used in the mac vlan cache
+#define PRS_REG_SAL_MAC_EN_E5                                                                                0x1f16c8UL //Access:RW   DataWidth:0x1    // Used in the mac vlan cache
+#define PRS_REG_SAL_TUNNEL_VLAN_EN_E5                                                                        0x1f16ccUL //Access:RW   DataWidth:0x1    // Used in the mac vlan cache
+#define PRS_REG_SAL_TUNNEL_MAC_EN_E5                                                                         0x1f16d0UL //Access:RW   DataWidth:0x1    // Used in the mac vlan cache
+#define PRS_REG_SAL_TUNNEL_TYPE_EN_E5                                                                        0x1f16d4UL //Access:RW   DataWidth:0x1    // Used in the mac vlan cache
+#define PRS_REG_SAL_TENANT_ID_EN_E5                                                                          0x1f16d8UL //Access:RW   DataWidth:0x1    // Used in the mac vlan cache
+#define PRS_REG_XRC_AFFINITY_OFFSET_E5                                                                       0x1f16dcUL //Access:RW   DataWidth:0x8    // Used in the source affinity CM field
+#define PRS_REG_XRC_OPCODES_E5                                                                               0x1f16e0UL //Access:RW   DataWidth:0x20   // Used in the source affinity CM field
+#define PRS_REG_NEW_ENTRY_EXCLUSIVE_E5                                                                       0x1f16e4UL //Access:RW   DataWidth:0x1    // Used in the source affinity CM field
+#define PRS_REG_NEW_ENTRY_EXCLUSIVE_CLASSIFY_FAILED_E5                                                       0x1f16e8UL //Access:RW   DataWidth:0x1    // Used in the source affinity CM field
+#define PRS_REG_MAC_VLAN_HIT_NUM_E5                                                                          0x1f16ecUL //Access:RC   DataWidth:0x18   // The number of mac vlan hits
+#define PRS_REG_ETS_ARB_RR_BURST_MODE_E5                                                                     0x1f16f0UL //Access:RW   DataWidth:0x1    // Burst mode enabled.  Set this bits to have the main round-robin arbiter stays on the winning input instead of moving to the next one.
+#define PRS_REG_EN_IPV6_EXT_EVENT_ID_E5                                                                      0x1f16f4UL //Access:RW   DataWidth:0x1    // enable event_id to be set as ipv6_ext_event_id
+#define XMAC_REG_CTRL_BB                                                                                     0x210000UL //Access:RW   DataWidth:0xe    // Multi Field Register.
+  #define XMAC_REG_CTRL_TX_EN_BB                                                                             (0x1<<0) // Transmit enable.
+  #define XMAC_REG_CTRL_TX_EN_BB_SHIFT                                                                       0
+  #define XMAC_REG_CTRL_RX_EN_BB                                                                             (0x1<<1) // Receive enable.
+  #define XMAC_REG_CTRL_RX_EN_BB_SHIFT                                                                       1
+  #define XMAC_REG_CTRL_LINE_LOCAL_LPBK_BB                                                                   (0x1<<2) // Local loopback from TX to RX. This loopback is on the line side after clock domain crossing - from the last TX pipeline stage to the first RX pipeline stage.
+  #define XMAC_REG_CTRL_LINE_LOCAL_LPBK_BB_SHIFT                                                             2
+  #define XMAC_REG_CTRL_CORE_LOCAL_LPBK_BB                                                                   (0x1<<3) // Local loopback from TX to RX. This loopback is on the core side before clock domain crossing - from the first TX pipeline stage to the last RX pipeline stage.
+  #define XMAC_REG_CTRL_CORE_LOCAL_LPBK_BB_SHIFT                                                             3
+  #define XMAC_REG_CTRL_LINE_REMOTE_LPBK_BB                                                                  (0x1<<4) // Remote loopback from RX to TX. This loopback is on the line side before clock domain crossing - from the first RX pipeline stage to the last TX pipeline stage.
+  #define XMAC_REG_CTRL_LINE_REMOTE_LPBK_BB_SHIFT                                                            4
+  #define XMAC_REG_CTRL_CORE_REMOTE_LPBK_BB                                                                  (0x1<<5) // Remote loopback from RX to TX. This loopback is on the core side after clock domain crossing - from the last RX pipeline stage to the first TX pipeline stage.
+  #define XMAC_REG_CTRL_CORE_REMOTE_LPBK_BB_SHIFT                                                            5
+  #define XMAC_REG_CTRL_SOFT_RESET_BB                                                                        (0x1<<6) // Resets the MAC logic annd status registers only.
+  #define XMAC_REG_CTRL_SOFT_RESET_BB_SHIFT                                                                  6
+  #define XMAC_REG_CTRL_XLGMII_ALIGN_ENB_BB                                                                  (0x1<<7) // Enables SOP; SOM & Sequence alignment to 8 byte boundaries; as defined in 40G mode.
+  #define XMAC_REG_CTRL_XLGMII_ALIGN_ENB_BB_SHIFT                                                            7
+  #define XMAC_REG_CTRL_LOCAL_LPBK_LEAK_ENB_BB                                                               (0x1<<8) // If set; during either of the local loopback modes; the transmit packets are also sent to the TX Warpcore interface; apart from the loopback operation.
+  #define XMAC_REG_CTRL_LOCAL_LPBK_LEAK_ENB_BB_SHIFT                                                         8
+  #define XMAC_REG_CTRL_REMOTE_LPBK_LEAK_ENB_BB                                                              (0x1<<9) // If set; during either of the remote loopback modes; the received packets are also sent to the RX Port interface; apart from the loopback operation.
+  #define XMAC_REG_CTRL_REMOTE_LPBK_LEAK_ENB_BB_SHIFT                                                        9
+  #define XMAC_REG_CTRL_RS_SOFT_RESET_BB                                                                     (0x1<<10) // Resets the RS layer functionality - fault handling.
+  #define XMAC_REG_CTRL_RS_SOFT_RESET_BB_SHIFT                                                               10
+  #define XMAC_REG_CTRL_XGMII_IPG_CHECK_DISABLE_BB                                                           (0x1<<11) // If set; this will override the one column idle/sequence ordered set check before SOP in XGMII mode - effectively supporting 1 byte IPG in XGMII mode.
+  #define XMAC_REG_CTRL_XGMII_IPG_CHECK_DISABLE_BB_SHIFT                                                     11
+  #define XMAC_REG_CTRL_SW_LINK_STATUS_BB                                                                    (0x1<<12) // Link status indication from Software. If set; indicates that link is active. When this transitions from 0 to 1; EEE FSM waits for 1 second before it starts its operation.
+  #define XMAC_REG_CTRL_SW_LINK_STATUS_BB_SHIFT                                                              12
+  #define XMAC_REG_CTRL_LINK_STATUS_SELECT_BB                                                                (0x1<<13) // This is the link status mux select signal to choose between link status indication from software or the link status indication from the strap pin. If reset; it selects the software link status which is also the default value.
+  #define XMAC_REG_CTRL_LINK_STATUS_SELECT_BB_SHIFT                                                          13
+#define XMAC_REG_MODE_BB                                                                                     0x210008UL //Access:RW   DataWidth:0x7    // Multi Field Register.
+  #define XMAC_REG_MODE_HDR_MODE_BB                                                                          (0x7<<0) // Packet Header mode.
+  #define XMAC_REG_MODE_HDR_MODE_BB_SHIFT                                                                    0
+  #define XMAC_REG_MODE_NO_SOP_FOR_CRC_HG_BB                                                                 (0x1<<3) // If set; exclude the SOP byte for CRC calculation in HG modes.
+  #define XMAC_REG_MODE_NO_SOP_FOR_CRC_HG_BB_SHIFT                                                           3
+  #define XMAC_REG_MODE_SPEED_MODE_BB                                                                        (0x7<<4) // Port Speed.
+  #define XMAC_REG_MODE_SPEED_MODE_BB_SHIFT                                                                  4
+#define XMAC_REG_SPARE0_BB                                                                                   0x210010UL //Access:RW   DataWidth:0x20   // SPARE REGISTERS 0.
+#define XMAC_REG_SPARE1_BB                                                                                   0x210018UL //Access:RW   DataWidth:0x2    // SPARE REGISTERS 0.
+#define XMAC_REG_TX_CTRL_LO_BB                                                                               0x210020UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define XMAC_REG_TX_CTRL_LO_CRC_MODE_BB                                                                    (0x3<<0) // CRC mode for Transmit Side.
+  #define XMAC_REG_TX_CTRL_LO_CRC_MODE_BB_SHIFT                                                              0
+  #define XMAC_REG_TX_CTRL_LO_DISCARD_BB                                                                     (0x1<<2) // Accept packets from the host but do not transmit.
+  #define XMAC_REG_TX_CTRL_LO_DISCARD_BB_SHIFT                                                               2
+  #define XMAC_REG_TX_CTRL_LO_TX_ANY_START_BB                                                                (0x1<<3) // Don't force the first byte of a packet to be /Start.
+  #define XMAC_REG_TX_CTRL_LO_TX_ANY_START_BB_SHIFT                                                          3
+  #define XMAC_REG_TX_CTRL_LO_PAD_EN_BB                                                                      (0x1<<4) // Enable XMAC to pad runt packets on the Tx.
+  #define XMAC_REG_TX_CTRL_LO_PAD_EN_BB_SHIFT                                                                4
+  #define XMAC_REG_TX_CTRL_LO_PAD_THRESHOLD_BB                                                               (0x7f<<5) // If padding is enabled; packets less than this size are padded to get to this size.
+  #define XMAC_REG_TX_CTRL_LO_PAD_THRESHOLD_BB_SHIFT                                                         5
+  #define XMAC_REG_TX_CTRL_LO_AVERAGE_IPG_BB                                                                 (0x7f<<12) // Average interpacket gap. Must be >=8.
+  #define XMAC_REG_TX_CTRL_LO_AVERAGE_IPG_BB_SHIFT                                                           12
+  #define XMAC_REG_TX_CTRL_LO_THROT_NUM_BB                                                                   (0x3f<<19) // Number of bytes of extra IPG added whenever txThrotDemon bytes have been transmitted.
+  #define XMAC_REG_TX_CTRL_LO_THROT_NUM_BB_SHIFT                                                             19
+  #define XMAC_REG_TX_CTRL_LO_THROT_DENOM_LO_BB                                                              (0x7f<<25) // Lower 8 bits of throt_denom register. Number of bytes to transmite before adding txThrotNumer bytes to the IPG.
+  #define XMAC_REG_TX_CTRL_LO_THROT_DENOM_LO_BB_SHIFT                                                        25
+#define XMAC_REG_TX_CTRL_HI_BB                                                                               0x210024UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define XMAC_REG_TX_CTRL_HI_THROT_DENOM_HI_BB                                                              (0x1<<0) // Upper 8 bits of throt_denom register. Number of bytes to transmite before adding txThrotNumer bytes to the IPG.
+  #define XMAC_REG_TX_CTRL_HI_THROT_DENOM_HI_BB_SHIFT                                                        0
+  #define XMAC_REG_TX_CTRL_HI_TX_PREAMBLE_LENGTH_BB                                                          (0xf<<1) // Number of preamble bytes for transmit IEEE packets; this value should include the K.SOP & SFD character as well.
+  #define XMAC_REG_TX_CTRL_HI_TX_PREAMBLE_LENGTH_BB_SHIFT                                                    1
+  #define XMAC_REG_TX_CTRL_HI_TX_64BYTE_BUFFER_EN_BB                                                         (0x1<<5) // If enabled; XMAC buffers 64 bytes per packet; before starting transmission of the packet on the line side; helps to prevent underflow issues.
+  #define XMAC_REG_TX_CTRL_HI_TX_64BYTE_BUFFER_EN_BB_SHIFT                                                   5
+#define XMAC_REG_TX_MAC_SA_LO_BB                                                                             0x210028UL //Access:RW   DataWidth:0x20   // Lower 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC packets transmitted by the MAC.
+#define XMAC_REG_TX_MAC_SA_HI_BB                                                                             0x21002cUL //Access:RW   DataWidth:0x10   // Upper 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC packets transmitted by the MAC.
+#define XMAC_REG_RX_CTRL_BB                                                                                  0x210030UL //Access:RW   DataWidth:0xd    // Multi Field Register.
+  #define XMAC_REG_RX_CTRL_RX_PASS_CTRL_BB                                                                   (0x1<<0) // Mac Control packets are passed to the system.
+  #define XMAC_REG_RX_CTRL_RX_PASS_CTRL_BB_SHIFT                                                             0
+  #define XMAC_REG_RX_CTRL_RX_ANY_START_BB                                                                   (0x1<<1) // True to allow any non-Idle character to start a packet.
+  #define XMAC_REG_RX_CTRL_RX_ANY_START_BB_SHIFT                                                             1
+  #define XMAC_REG_RX_CTRL_STRIP_CRC_BB                                                                      (0x1<<2) // CRC is checked; then stripped from the received packet.
+  #define XMAC_REG_RX_CTRL_STRIP_CRC_BB_SHIFT                                                                2
+  #define XMAC_REG_RX_CTRL_STRICT_PREAMBLE_BB                                                                (0x1<<3) // If set; the MAC checks for IEEE Ethernet format premable - K.SOP + 5 '55' premable bytes + 'D5' SFD character - if this sequence is missing it is treated as an errored packet.
+  #define XMAC_REG_RX_CTRL_STRICT_PREAMBLE_BB_SHIFT                                                          3
+  #define XMAC_REG_RX_CTRL_RUNT_THRESHOLD_BB                                                                 (0x7f<<4) // The runt threshold; below which the packets are discarded.
+  #define XMAC_REG_RX_CTRL_RUNT_THRESHOLD_BB_SHIFT                                                           4
+  #define XMAC_REG_RX_CTRL_RECEIVE_18_BYTE_PKTS_BB                                                           (0x1<<11) // If set; the minimum receive packet size is reduced to 18 bytes from the default 33 bytes - Should be used in MACSEC chips with IEEE mode only.
+  #define XMAC_REG_RX_CTRL_RECEIVE_18_BYTE_PKTS_BB_SHIFT                                                     11
+  #define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB                                                      (0x1<<12) // If set; the MAC parses the frame from K.SOP onwards to look for the SFD character and then processes the packet. If disabled; treats the first 8 bytes of packet as preamble.
+  #define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB_SHIFT                                                12
+#define XMAC_REG_RX_MAC_SA_LO_BB                                                                             0x210038UL //Access:RW   DataWidth:0x20   // Lower 48 bits of rx_sa register. SA recognized for MAC control packets in addition to the standard 0x0180C2000001.
+#define XMAC_REG_RX_MAC_SA_HI_BB                                                                             0x21003cUL //Access:RW   DataWidth:0x10   // Upper 48 bits of rx_sa register. SA recognized for MAC control packets in addition to the standard 0x0180C2000001.
+#define XMAC_REG_RX_MAX_SIZE_BB                                                                              0x210040UL //Access:RW   DataWidth:0xe    // Maximum packet size in receive direction; exclusive of preamble & CRC in strip mode.
+#define XMAC_REG_RX_VLAN_TAG_LO_BB                                                                           0x210048UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define XMAC_REG_RX_VLAN_TAG_LO_INNER_VLAN_TAG_BB                                                          (0xffff<<0) // Type field for Inner VLAN tag.
+  #define XMAC_REG_RX_VLAN_TAG_LO_INNER_VLAN_TAG_BB_SHIFT                                                    0
+  #define XMAC_REG_RX_VLAN_TAG_LO_OUTER_VLAN_TAG_BB                                                          (0xffff<<16) // Type field for Outer VLAN tag.
+  #define XMAC_REG_RX_VLAN_TAG_LO_OUTER_VLAN_TAG_BB_SHIFT                                                    16
+#define XMAC_REG_RX_VLAN_TAG_HI_BB                                                                           0x21004cUL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define XMAC_REG_RX_VLAN_TAG_HI_INNER_VLAN_TAG_ENABLE_BB                                                   (0x1<<0) // Enables VLAN tag detection using the INNER_VLAN_TAG.
+  #define XMAC_REG_RX_VLAN_TAG_HI_INNER_VLAN_TAG_ENABLE_BB_SHIFT                                             0
+  #define XMAC_REG_RX_VLAN_TAG_HI_OUTER_VLAN_TAG_ENABLE_BB                                                   (0x1<<1) // Enables VLAN tag detection using the OUTER_VLAN_TAG.
+  #define XMAC_REG_RX_VLAN_TAG_HI_OUTER_VLAN_TAG_ENABLE_BB_SHIFT                                             1
+#define XMAC_REG_RX_LSS_CTRL_BB                                                                              0x210050UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define XMAC_REG_RX_LSS_CTRL_LOCAL_FAULT_DISABLE_BB                                                        (0x1<<0) // True to disable enable processing of LSS message type: Local Fault. When clear and a local fault LSS message is received; a continuous stream of 'Remote Fault' LSS messages will be transmitted to the link partner.
+  #define XMAC_REG_RX_LSS_CTRL_LOCAL_FAULT_DISABLE_BB_SHIFT                                                  0
+  #define XMAC_REG_RX_LSS_CTRL_REMOTE_FAULT_DISABLE_BB                                                       (0x1<<1) // True to disable processing of LSS message type: Remote Fault. When clear and a remote fault LSS message is received; a continuous stream of IDLES will be transmitted to the link partner.
+  #define XMAC_REG_RX_LSS_CTRL_REMOTE_FAULT_DISABLE_BB_SHIFT                                                 1
+  #define XMAC_REG_RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX_BB                                                 (0x1<<2) // If set; the TX faults inputs are used to send out fault sequences - else receive faults are used -- used by MACSEC PHY chips.
+  #define XMAC_REG_RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX_BB_SHIFT                                           2
+  #define XMAC_REG_RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE_BB                                                  (0x1<<3) // True to disable processing of LSS message type: Link Interruption. When clear and a Link Interruption LSS message is received; a continuous stream of IDLES will be transmitted to the link partner.
+  #define XMAC_REG_RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE_BB_SHIFT                                            3
+  #define XMAC_REG_RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT_BB                                                (0x1<<4) // If set; the transmit data is dropped on detection of local fault on the receive side. If reset; transmit data is stalled on detection of local fault.
+  #define XMAC_REG_RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT_BB_SHIFT                                          4
+  #define XMAC_REG_RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT_BB                                               (0x1<<5) // If set; the transmit data is dropped on detection of remote fault on the receive side. If reset; transmit data is stalled on detection of remote fault.
+  #define XMAC_REG_RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT_BB_SHIFT                                         5
+  #define XMAC_REG_RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT_BB                                             (0x1<<6) // If set; the transmit data is dropped on detection of link interruption on the receive side. If reset; transmit data is stalled on detection of link interruption.
+  #define XMAC_REG_RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT_BB_SHIFT                                       6
+  #define XMAC_REG_RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN_BB                                     (0x1<<7) // If set; the Receive LPause; PFC & LLFC timers are reset whenever the link status is down; or we receive local or remote faults.
+  #define XMAC_REG_RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN_BB_SHIFT                               7
+#define XMAC_REG_RX_LSS_STATUS_BB                                                                            0x210058UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define XMAC_REG_RX_LSS_STATUS_LOCAL_FAULT_STATUS_BB                                                       (0x1<<0) // True while 'local fault' LSS messages are being received.
+  #define XMAC_REG_RX_LSS_STATUS_LOCAL_FAULT_STATUS_BB_SHIFT                                                 0
+  #define XMAC_REG_RX_LSS_STATUS_REMOTE_FAULT_STATUS_BB                                                      (0x1<<1) // True while 'remote fault' LSS messages are being received.
+  #define XMAC_REG_RX_LSS_STATUS_REMOTE_FAULT_STATUS_BB_SHIFT                                                1
+  #define XMAC_REG_RX_LSS_STATUS_LINK_INTERRUPTION_STATUS_BB                                                 (0x1<<2) // True while 'Link Interruption' LSS messages are being received.
+  #define XMAC_REG_RX_LSS_STATUS_LINK_INTERRUPTION_STATUS_BB_SHIFT                                           2
+#define XMAC_REG_CLEAR_RX_LSS_STATUS_BB                                                                      0x210060UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define XMAC_REG_CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS_BB                                           (0x1<<0) // A rising edge on this register bit (0->1); clears the sticky LOCAL_FAULT_STATUS bit.
+  #define XMAC_REG_CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS_BB_SHIFT                                     0
+  #define XMAC_REG_CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS_BB                                          (0x1<<1) // A rising edge on this register bit (0->1); clears the sticky REMOTE_FAULT_STATUS bit.
+  #define XMAC_REG_CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS_BB_SHIFT                                    1
+  #define XMAC_REG_CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS_BB                                     (0x1<<2) // A rising edge on this register bit (0->1); clears the sticky LINK_INTERRUPTION_STATUS bit.
+  #define XMAC_REG_CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS_BB_SHIFT                               2
+#define XMAC_REG_PAUSE_CTRL_LO_BB                                                                            0x210068UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define XMAC_REG_PAUSE_CTRL_LO_PAUSE_REFRESH_TIMER_BB                                                      (0xffff<<0) // This field is Threshold for pause timer to cause XOFF to be resent (Unit is 512 bit-times).
+  #define XMAC_REG_PAUSE_CTRL_LO_PAUSE_REFRESH_TIMER_BB_SHIFT                                                0
+  #define XMAC_REG_PAUSE_CTRL_LO_PAUSE_REFRESH_EN_BB                                                         (0x1<<16) // If set; enables the pause regen functionality.
+  #define XMAC_REG_PAUSE_CTRL_LO_PAUSE_REFRESH_EN_BB_SHIFT                                                   16
+  #define XMAC_REG_PAUSE_CTRL_LO_TX_PAUSE_EN_BB                                                              (0x1<<17) // Send PAUSE packets whenever TxPause input is true.
+  #define XMAC_REG_PAUSE_CTRL_LO_TX_PAUSE_EN_BB_SHIFT                                                        17
+  #define XMAC_REG_PAUSE_CTRL_LO_RX_PAUSE_EN_BB                                                              (0x1<<18) // Process PAUSE Frames in the receive direction.
+  #define XMAC_REG_PAUSE_CTRL_LO_RX_PAUSE_EN_BB_SHIFT                                                        18
+  #define XMAC_REG_PAUSE_CTRL_LO_RX_PASS_PAUSE_BB                                                            (0x1<<19) // Send PAUSE frames to the system side.
+  #define XMAC_REG_PAUSE_CTRL_LO_RX_PASS_PAUSE_BB_SHIFT                                                      19
+  #define XMAC_REG_PAUSE_CTRL_LO_PAUSE_GMII_ON_TX_LINE_SIDE_BB                                               (0x1<<20) // If set; the recive pause is used to stop the frame transmission in the GMII convertor block; to reduce the Pause commencement latency.
+  #define XMAC_REG_PAUSE_CTRL_LO_PAUSE_GMII_ON_TX_LINE_SIDE_BB_SHIFT                                         20
+  #define XMAC_REG_PAUSE_CTRL_LO_PAUSE_XOFF_TIMER_LO_BB                                                      (0x7ff<<21) // Lower 16 bits of pause_xoff_timer register. Time value sent in the Timer Field for XOFF state (Unit is 512 bit-times).
+  #define XMAC_REG_PAUSE_CTRL_LO_PAUSE_XOFF_TIMER_LO_BB_SHIFT                                                21
+#define XMAC_REG_PAUSE_CTRL_HI_BB                                                                            0x21006cUL //Access:RW   DataWidth:0x5    // Upper 16 bits of pause_xoff_timer register. Time value sent in the Timer Field for XOFF state (Unit is 512 bit-times).
+#define XMAC_REG_PFC_CTRL_LO_BB                                                                              0x210070UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define XMAC_REG_PFC_CTRL_LO_PFC_REFRESH_TIMER_BB                                                          (0xffff<<0) // Threshold for pause timer to cause XOFF to be resent (Unit is 512 bit-times).
+  #define XMAC_REG_PFC_CTRL_LO_PFC_REFRESH_TIMER_BB_SHIFT                                                    0
+  #define XMAC_REG_PFC_CTRL_LO_PFC_XOFF_TIMER_BB                                                             (0xffff<<16) // Time value sent in the Timer Field for classes in XOFF state (Unit is 512 bit-times).
+  #define XMAC_REG_PFC_CTRL_LO_PFC_XOFF_TIMER_BB_SHIFT                                                       16
+#define XMAC_REG_PFC_CTRL_HI_BB                                                                              0x210074UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define XMAC_REG_PFC_CTRL_HI_PFC_REFRESH_EN_BB                                                             (0x1<<0) // Enable automatic re-send of PFC packet after a period time determined by PFC_REFRESH_TIMER.
+  #define XMAC_REG_PFC_CTRL_HI_PFC_REFRESH_EN_BB_SHIFT                                                       0
+  #define XMAC_REG_PFC_CTRL_HI_FORCE_PFC_XON_BB                                                              (0x1<<1) // Instructs the MAC to send XON for all Classes of Service.
+  #define XMAC_REG_PFC_CTRL_HI_FORCE_PFC_XON_BB_SHIFT                                                        1
+  #define XMAC_REG_PFC_CTRL_HI_RX_PASS_PFC_BB                                                                (0x1<<2) // Set to pass RX PFC frame to core I/F.
+  #define XMAC_REG_PFC_CTRL_HI_RX_PASS_PFC_BB_SHIFT                                                          2
+  #define XMAC_REG_PFC_CTRL_HI_PFC_STATS_EN_BB                                                               (0x1<<3) // Set to enable incrementing IRXPP and ITXPP.
+  #define XMAC_REG_PFC_CTRL_HI_PFC_STATS_EN_BB_SHIFT                                                         3
+  #define XMAC_REG_PFC_CTRL_HI_RX_PFC_EN_BB                                                                  (0x1<<4) // PFC RX enable.
+  #define XMAC_REG_PFC_CTRL_HI_RX_PFC_EN_BB_SHIFT                                                            4
+  #define XMAC_REG_PFC_CTRL_HI_TX_PFC_EN_BB                                                                  (0x1<<5) // PFC TX enable.
+  #define XMAC_REG_PFC_CTRL_HI_TX_PFC_EN_BB_SHIFT                                                            5
+#define XMAC_REG_PFC_TYPE_BB                                                                                 0x210078UL //Access:RW   DataWidth:0x10   // The PFC packet generation and detection uses this Ethertype value.
+#define XMAC_REG_PFC_OPCODE_BB                                                                               0x210080UL //Access:RW   DataWidth:0x10   // The PFC packet generation and detection uses this Ethertype value.
+#define XMAC_REG_PFC_DA_LO_BB                                                                                0x210088UL //Access:RW   DataWidth:0x20   // Lower 48 bits of pfc_macda register. Used as the DA in PFC packets transmitted by the MAC.
+#define XMAC_REG_PFC_DA_HI_BB                                                                                0x21008cUL //Access:RW   DataWidth:0x10   // Upper 48 bits of pfc_macda register. Used as the DA in PFC packets transmitted by the MAC.
+#define XMAC_REG_LLFC_CTRL_BB                                                                                0x210090UL //Access:RW   DataWidth:0xe    // Multi Field Register.
+  #define XMAC_REG_LLFC_CTRL_TX_LLFC_EN_BB                                                                   (0x1<<0) // This bit enables llfc for Tx path in XMAC; works with llfc_en in xport.
+  #define XMAC_REG_LLFC_CTRL_TX_LLFC_EN_BB_SHIFT                                                             0
+  #define XMAC_REG_LLFC_CTRL_RX_LLFC_EN_BB                                                                   (0x1<<1) // This bit enables llfc for Rx path in XMAC; works with llfc_en in xport.
+  #define XMAC_REG_LLFC_CTRL_RX_LLFC_EN_BB_SHIFT                                                             1
+  #define XMAC_REG_LLFC_CTRL_LLFC_IN_IPG_ONLY_BB                                                             (0x1<<2) // When set; LLFC is inserted only during IPG.
+  #define XMAC_REG_LLFC_CTRL_LLFC_IN_IPG_ONLY_BB_SHIFT                                                       2
+  #define XMAC_REG_LLFC_CTRL_LLFC_CUT_THROUGH_MODE_BB                                                        (0x1<<3) // When set and llfc_in_ipg_only =0; GXPORT operates in cut-through mode.
+  #define XMAC_REG_LLFC_CTRL_LLFC_CUT_THROUGH_MODE_BB_SHIFT                                                  3
+  #define XMAC_REG_LLFC_CTRL_LLFC_CRC_IGNORE_BB                                                              (0x1<<4) // This bit if set to 1; disables the crc check for incoming llfc messages.
+  #define XMAC_REG_LLFC_CTRL_LLFC_CRC_IGNORE_BB_SHIFT                                                        4
+  #define XMAC_REG_LLFC_CTRL_NO_SOM_FOR_CRC_LLFC_BB                                                          (0x1<<5) // When set; LLFC crc calculation does not involve SOM.
+  #define XMAC_REG_LLFC_CTRL_NO_SOM_FOR_CRC_LLFC_BB_SHIFT                                                    5
+  #define XMAC_REG_LLFC_CTRL_LLFC_IMG_BB                                                                     (0xff<<6) // The minimum Inter Message gap that must be observed between 2 HG2 Messages.
+  #define XMAC_REG_LLFC_CTRL_LLFC_IMG_BB_SHIFT                                                               6
+#define XMAC_REG_TX_LLFC_MSG_FIELDS_BB                                                                       0x210098UL //Access:RW   DataWidth:0x1c   // Multi Field Register.
+  #define XMAC_REG_TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL_BB                                            (0xff<<0) // Value used for dw0_byte1 of outgoing LLFC message.
+  #define XMAC_REG_TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL_BB_SHIFT                                      0
+  #define XMAC_REG_TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_BB                                              (0xf<<8) // Value used for dw1_byte0 of outgoing LLFC message.
+  #define XMAC_REG_TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_BB_SHIFT                                        8
+  #define XMAC_REG_TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME_BB                                                      (0xffff<<12) // Value used for DW2_byte2 and DW2_byte3 of the outgoing LLFC messages.
+  #define XMAC_REG_TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME_BB_SHIFT                                                12
+#define XMAC_REG_RX_LLFC_MSG_FIELDS_BB                                                                       0x2100a0UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define XMAC_REG_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL_BB                                            (0xff<<0) // Value used to decode dw0_byte1 of incoming LLFC message.
+  #define XMAC_REG_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL_BB_SHIFT                                      0
+  #define XMAC_REG_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_BB                                              (0xf<<8) // Value used to decode dw1_byte0 of incoming LLFC message.
+  #define XMAC_REG_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_BB_SHIFT                                        8
+  #define XMAC_REG_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL_BB                                           (0xff<<12) // Value used to decode dw0_byte1 of incoming PLFC message.
+  #define XMAC_REG_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL_BB_SHIFT                                     12
+  #define XMAC_REG_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL_BB                                             (0xf<<20) // Value used to decode dw1_byte0 of incoming PLFC message.
+  #define XMAC_REG_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL_BB_SHIFT                                       20
+#define XMAC_REG_HCFC_CTRL_BB                                                                                0x2100a8UL //Access:RW   DataWidth:0x15   // Multi Field Register.
+  #define XMAC_REG_HCFC_CTRL_TX_HCFC_EN_BB                                                                   (0x1<<0) // This bit enables HCFC for Tx path in XMAC.
+  #define XMAC_REG_HCFC_CTRL_TX_HCFC_EN_BB_SHIFT                                                             0
+  #define XMAC_REG_HCFC_CTRL_RX_HCFC_EN_BB                                                                   (0x1<<1) // This bit enables HCFC for Rx path in XMAC.
+  #define XMAC_REG_HCFC_CTRL_RX_HCFC_EN_BB_SHIFT                                                             1
+  #define XMAC_REG_HCFC_CTRL_HCFC_CRC_IGNORE_BB                                                              (0x1<<2) // The crc check for HCFC messages is ignored if this bit is set.
+  #define XMAC_REG_HCFC_CTRL_HCFC_CRC_IGNORE_BB_SHIFT                                                        2
+  #define XMAC_REG_HCFC_CTRL_NO_SOM_FOR_CRC_HCFC_BB                                                          (0x1<<3) // When set; HCFC CRC calculation does not involve SOM.
+  #define XMAC_REG_HCFC_CTRL_NO_SOM_FOR_CRC_HCFC_BB_SHIFT                                                    3
+  #define XMAC_REG_HCFC_CTRL_HCFC_IN_IPG_ONLY_BB                                                             (0x1<<4) // If 1; the HCFC packets are sent during IPG; else sent preemptively.
+  #define XMAC_REG_HCFC_CTRL_HCFC_IN_IPG_ONLY_BB_SHIFT                                                       4
+  #define XMAC_REG_HCFC_CTRL_HCFC_SOM_BB                                                                     (0xff<<5) // Sets the new value for the SOM of the HCFC messages.
+  #define XMAC_REG_HCFC_CTRL_HCFC_SOM_BB_SHIFT                                                               5
+  #define XMAC_REG_HCFC_CTRL_HCFC_IMG_BB                                                                     (0xff<<13) // The minimum Inter Message gap between 2 HCFC Messages.
+  #define XMAC_REG_HCFC_CTRL_HCFC_IMG_BB_SHIFT                                                               13
+#define XMAC_REG_FIFO_STATUS_BB                                                                              0x2100c0UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define XMAC_REG_FIFO_STATUS_RX_PKT_OVERFLOW_BB                                                            (0x1<<0) // Indicates rx packet fifo overflow.
+  #define XMAC_REG_FIFO_STATUS_RX_PKT_OVERFLOW_BB_SHIFT                                                      0
+  #define XMAC_REG_FIFO_STATUS_RX_MSG_OVERFLOW_BB                                                            (0x1<<1) // Indicates rx message fifo overflow.
+  #define XMAC_REG_FIFO_STATUS_RX_MSG_OVERFLOW_BB_SHIFT                                                      1
+  #define XMAC_REG_FIFO_STATUS_TX_PKT_UNDERFLOW_BB                                                           (0x1<<2) // Indicates tx packet fifo underflow.
+  #define XMAC_REG_FIFO_STATUS_TX_PKT_UNDERFLOW_BB_SHIFT                                                     2
+  #define XMAC_REG_FIFO_STATUS_TX_PKT_OVERFLOW_BB                                                            (0x1<<3) // Indicates tx packet fifo overflow.
+  #define XMAC_REG_FIFO_STATUS_TX_PKT_OVERFLOW_BB_SHIFT                                                      3
+  #define XMAC_REG_FIFO_STATUS_TX_HCFC_MSG_OVERFLOW_BB                                                       (0x1<<4) // Indicates tx HCFC message fifo overflow.
+  #define XMAC_REG_FIFO_STATUS_TX_HCFC_MSG_OVERFLOW_BB_SHIFT                                                 4
+  #define XMAC_REG_FIFO_STATUS_TX_LLFC_MSG_OVERFLOW_BB                                                       (0x1<<5) // Indicates tx LLFC message fifo overflow.
+  #define XMAC_REG_FIFO_STATUS_TX_LLFC_MSG_OVERFLOW_BB_SHIFT                                                 5
+  #define XMAC_REG_FIFO_STATUS_LINK_STATUS_BB                                                                (0x1<<7) // This bit indicates the link status used by XMAC EEE. This is continuously updated. If set; indicates that link is active.
+  #define XMAC_REG_FIFO_STATUS_LINK_STATUS_BB_SHIFT                                                          7
+#define XMAC_REG_CLEAR_FIFO_STATUS_BB                                                                        0x2100c8UL //Access:RW   DataWidth:0x7    // Multi Field Register.
+  #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW_BB                                                (0x1<<0) // A rising edge on this register bit (0->1); clears the sticky RX_PKT_OVERFLOW status bit.
+  #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW_BB_SHIFT                                          0
+  #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW_BB                                                (0x1<<1) // A rising edge on this register bit (0->1); clears the sticky RX_MSG_OVERFLOW status bit.
+  #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW_BB_SHIFT                                          1
+  #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW_BB                                               (0x1<<2) // A rising edge on this register bit (0->1); clears the sticky TX_PKT_UNDERFLOW status bit.
+  #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW_BB_SHIFT                                         2
+  #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW_BB                                                (0x1<<3) // A rising edge on this register bit (0->1); clears the sticky TX_PKT_OVERFLOW status bit.
+  #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW_BB_SHIFT                                          3
+  #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_HCFC_MSG_OVERFLOW_BB                                           (0x1<<4) // A rising edge on this register bit (0->1); clears the sticky TX_HCFC_MSG_OVERFLOW status bit.
+  #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_HCFC_MSG_OVERFLOW_BB_SHIFT                                     4
+  #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW_BB                                           (0x1<<5) // A rising edge on this register bit (0->1); clears the sticky TX_LLFC_MSG_OVERFLOW status bit.
+  #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW_BB_SHIFT                                     5
+  #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW_BB                                            (0x1<<6) // A rising edge on this register bit (0->1); clears the sticky TX_TS_FIFO_OVERFLOW status bit.
+  #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW_BB_SHIFT                                      6
+#define XMAC_REG_TX_FIFO_CREDITS_BB                                                                          0x2100d0UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define XMAC_REG_TX_FIFO_CREDITS_QUAD_PORT_TX_CREDITS_BB                                                   (0x3f<<0) // Credits for TX FIFO; used by Ports 0/1/2/3 in quad port mode.
+  #define XMAC_REG_TX_FIFO_CREDITS_QUAD_PORT_TX_CREDITS_BB_SHIFT                                             0
+  #define XMAC_REG_TX_FIFO_CREDITS_DUAL_PORT_TX_CREDITS_BB                                                   (0x3f<<6) // Credits for TX FIFO; used by Port 0 & 2 in dual port mode.
+  #define XMAC_REG_TX_FIFO_CREDITS_DUAL_PORT_TX_CREDITS_BB_SHIFT                                             6
+  #define XMAC_REG_TX_FIFO_CREDITS_SINGLE_PORT_TX_CREDITS_BB                                                 (0x3f<<12) // Credits for TX FIFO; used by Port 0 in single port mode.
+  #define XMAC_REG_TX_FIFO_CREDITS_SINGLE_PORT_TX_CREDITS_BB_SHIFT                                           12
+#define XMAC_REG_EEE_CTRL_BB                                                                                 0x2100d8UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define XMAC_REG_EEE_CTRL_EEE_EN_BB                                                                        (0x1<<0) // EEE Enable.
+  #define XMAC_REG_EEE_CTRL_EEE_EN_BB_SHIFT                                                                  0
+  #define XMAC_REG_EEE_CTRL_EEE_DISABLE_TX_PAUSE_XOFF_BB                                                     (0x1<<1) // If set; EEE FSM can go to EMPTY state even when transmit path is in XOFF state and Refresh Pause frame generation is enabled.
+  #define XMAC_REG_EEE_CTRL_EEE_DISABLE_TX_PAUSE_XOFF_BB_SHIFT                                               1
+  #define XMAC_REG_EEE_CTRL_EEE_DISABLE_TX_PFC_XOFF_BB                                                       (0x1<<2) // If set; EEE FSM can go to EMPTY state even when transmit path is in XOFF state per PFC implementation and Refresh PFC frame generation is enabled.
+  #define XMAC_REG_EEE_CTRL_EEE_DISABLE_TX_PFC_XOFF_BB_SHIFT                                                 2
+  #define XMAC_REG_EEE_CTRL_EEE_DISABLE_RX_PAUSE_ACTIVE_BB                                                   (0x1<<3) // If set; EEE FSM can go to EMPTY state even when Receive Pause is active.
+  #define XMAC_REG_EEE_CTRL_EEE_DISABLE_RX_PAUSE_ACTIVE_BB_SHIFT                                             3
+#define XMAC_REG_EEE_TIMERS_LO_BB                                                                            0x2100e0UL //Access:RW   DataWidth:0x20   // This is the duration for which condition to move to LPI state must be satisfied; at the end of which MAC transitions to LPI State. This is in terms of micro seconds.
+#define XMAC_REG_EEE_TIMERS_HI_BB                                                                            0x2100e4UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define XMAC_REG_EEE_TIMERS_HI_EEE_WAKE_TIMER_BB                                                           (0xffff<<0) // This is the duration for which MAC must wait to go back to ACTIVE state from LPI state when it receives packet for transmission. This is in terms of micro seconds.
+  #define XMAC_REG_EEE_TIMERS_HI_EEE_WAKE_TIMER_BB_SHIFT                                                     0
+  #define XMAC_REG_EEE_TIMERS_HI_EEE_REF_COUNT_BB                                                            (0xffff<<16) // This field controls clock divider used to generate ~1us reference pulses used by EEE timers. It specifies integer number of timer clock cycles for 1us using XLGMII txclk.
+  #define XMAC_REG_EEE_TIMERS_HI_EEE_REF_COUNT_BB_SHIFT                                                      16
+#define XMAC_REG_EEE_1_SEC_LINK_STATUS_TIMER_BB                                                              0x2100e8UL //Access:RW   DataWidth:0x18   // This is the duration for which EEE FSM must wait when Link status becomes active before transitioning to ACTIVE state. This is in terms of micro seconds. Default value is set to 1 second.
+#define XMAC_REG_GMII_EEE_CTRL_BB                                                                            0x210118UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define XMAC_REG_GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD_BB                                               (0xffff<<0) // If LPI_Prediction is enabled then this register defines the number of IDLEs to be received by GMII interface before allowing LP_IDLE to be sent to Link Partner.
+  #define XMAC_REG_GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD_BB_SHIFT                                         0
+  #define XMAC_REG_GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN_BB                                                 (0x1<<16) // When set to 1; enables LP_IDLE Prediction. When set to 0; disables LP_IDLE Prediction.
+  #define XMAC_REG_GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN_BB_SHIFT                                           16
+  #define XMAC_REG_GMII_EEE_CTRL_GMII_TXCLK_DIS_BB                                                           (0x1<<17) // When set to 1; GMII interface will shut down TXCLK to PHY; when in LPI state.
+  #define XMAC_REG_GMII_EEE_CTRL_GMII_TXCLK_DIS_BB_SHIFT                                                     17
+#define XMAC_REG_MACSEC_CTRL_LO_BB                                                                           0x210128UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define XMAC_REG_MACSEC_CTRL_LO_MACSEC_TX_LAUNCH_EN_BB                                                     (0x1<<0) // If set; each data frame is transmitted only after the corresponding launch_en signal is asserted.
+  #define XMAC_REG_MACSEC_CTRL_LO_MACSEC_TX_LAUNCH_EN_BB_SHIFT                                               0
+  #define XMAC_REG_MACSEC_CTRL_LO_MACSEC_TX_CRC_CORRUPT_EN_BB                                                (0x1<<1) // Setting this field enables the CRC corruption on the transmitted packets.
+  #define XMAC_REG_MACSEC_CTRL_LO_MACSEC_TX_CRC_CORRUPT_EN_BB_SHIFT                                          1
+  #define XMAC_REG_MACSEC_CTRL_LO_MACSEC_TX_CRC_CORRUPTION_MODE_BB                                           (0x1<<2) // In CRC corruption mode; if this bit is set; replaces computed CRC with XXX; else computed CRC is inverted.
+  #define XMAC_REG_MACSEC_CTRL_LO_MACSEC_TX_CRC_CORRUPTION_MODE_BB_SHIFT                                     2
+  #define XMAC_REG_MACSEC_CTRL_LO_MACSEC_PROG_TX_CRC_LO_BB                                                   (0x1fffffff<<3) // Lower 32 bits of macsec_prog_tx_crc register. Programmable CRC value to corrupt the Tx CRC to be used in MACSEC. The computed CRC is replaced by this programmed CRC value.
+  #define XMAC_REG_MACSEC_CTRL_LO_MACSEC_PROG_TX_CRC_LO_BB_SHIFT                                             3
+#define XMAC_REG_MACSEC_CTRL_HI_BB                                                                           0x21012cUL //Access:RW   DataWidth:0x3    // Upper 32 bits of macsec_prog_tx_crc register. Programmable CRC value to corrupt the Tx CRC to be used in MACSEC. The computed CRC is replaced by this programmed CRC value.
+#define XMAC_REG_VERSION_ID_BB                                                                               0x210130UL //Access:RW   DataWidth:0x10   // XMAC IP Version ID - corresponds to RTL/DV label.
+#define XMAC_REG_WB_TX_CTRL_BB                                                                               0x210420UL //Access:WB   DataWidth:0x26   // This is a WB access for version of the register at XMAC TX_CTRL. The register can be access in either this loation or at XMAC TX_CTRL; but normal WB access methods mus be used at this location. The fields within this WB register are: 1:0=XMAC CRC_MODE; 2:2=XMAC DISCARD; 3:3=XMAC TX_ANY_START; 4:4=XMAC PAD_EN; 11:5=XMAC PAD_THRESHOLD; 18:12=XMAC AVERAGE_IPG; 24:19=XMAC THROT_NUM; 31:25=XMAC THROT_DENOM_LO; 32:32=XMAC THROT_DENOM_HI; 36:33=XMAC TX_PREAMBLE_LENGTH; 37:37=XMAC TX_64BYTE_BUFFER_EN; 63:38=XMAC RESERVED.
+#define XMAC_REG_WB_TX_CTRL_SIZE                                                                             2
+#define XMAC_REG_WB_TX_MAC_SA_BB                                                                             0x210428UL //Access:WB   DataWidth:0x30   // This is a WB access for version of the register at XMAC TX_MAC_SA. The register can be access in either this loation or at XMAC TX_MAC_SA; but normal WB access methods mus be used at this location. The fields within this WB register are: 31:0=XMAC CTRL_SA_LO; 47:32=XMAC CTRL_SA_HI; 63:48=XMAC RESERVED.
+#define XMAC_REG_WB_TX_MAC_SA_SIZE                                                                           2
+#define XMAC_REG_WB_RX_MAC_SA_BB                                                                             0x210438UL //Access:WB   DataWidth:0x30   // This is a WB access for version of the register at XMAC RX_MAC_SA. The register can be access in either this loation or at XMAC RX_MAC_SA; but normal WB access methods mus be used at this location. The fields within this WB register are: 31:0=XMAC RX_SA_LO; 47:32=XMAC RX_SA_HI; 63:48=XMAC RESERVED.
+#define XMAC_REG_WB_RX_MAC_SA_SIZE                                                                           2
+#define XMAC_REG_WB_PAUSE_CTRL_BB                                                                            0x210468UL //Access:WB   DataWidth:0x25   // This is a WB access for version of the register at XMAC PAUSE_CTRL. The register can be access in either this loation or at XMAC PAUSE_CTRL; but normal WB access methods mus be used at this location. The fields within this WB register are: 15:0=XMAC PAUSE_REFRESH_TIMER; 16:16=XMAC PAUSE_REFRESH_EN; 17:17=XMAC TX_PAUSE_EN; 18:18=XMAC RX_PAUSE_EN; 19:19=XMAC RX_PASS_PAUSE; 20:20=XMAC PAUSE_GMII_ON_TX_LINE_SIDE; 31:21=XMAC PAUSE_XOFF_TIMER_LO; 36:32=XMAC PAUSE_XOFF_TIMER_HI; 63:37=XMAC RESERVED.
+#define XMAC_REG_WB_PAUSE_CTRL_SIZE                                                                          2
+#define XMAC_REG_WB_PFC_DA_BB                                                                                0x210488UL //Access:WB   DataWidth:0x30   // This is a WB access for version of the register at XMAC PFC_DA. The register can be access in either this loation or at XMAC PFC_DA; but normal WB access methods mus be used at this location. The fields within this WB register are: 31:0=XMAC PFC_MACDA_LO; 47:32=XMAC PFC_MACDA_HI; 63:48=XMAC RESERVED.
+#define XMAC_REG_WB_PFC_DA_SIZE                                                                              2
+#define XMAC_REG_WB_MACSEC_CTRL_BB                                                                           0x210528UL //Access:WB   DataWidth:0x23   // This is a WB access for version of the register at XMAC MACSEC_CTRL. The register can be access in either this loation or at XMAC MACSEC_CTRL; but normal WB access methods mus be used at this location. The fields within this WB register are: 0:0=XMAC MACSEC_TX_LAUNCH_EN; 1:1=XMAC MACSEC_TX_CRC_CORRUPT_EN; 2:2=XMAC MACSEC_TX_CRC_CORRUPTION_MODE; 31:3=XMAC MACSEC_PROG_TX_CRC_LO; 34:32=XMAC MACSEC_PROG_TX_CRC_HI; 63:35=XMAC RESERVED.
+#define XMAC_REG_WB_MACSEC_CTRL_SIZE                                                                         2
+#define XMAC_REG_XMAC1_BB                                                                                    0x210800UL //Access:RW   DataWidth:0x20   // This is the XMAC for port 1.
+#define XMAC_REG_XMAC1_SIZE                                                                                  512
+#define XMAC_REG_MSTAT0_BB                                                                                   0x211000UL //Access:RW   DataWidth:0x20   // This is the MSTAT block.
+#define XMAC_REG_MSTAT0_SIZE                                                                                 1024
+#define CNIG_REG_NIG_PORT0_CONF_K2_E5                                                                        0x218200UL //Access:RW   DataWidth:0xf    // Multi Field Register.
+  #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5                                                    (0x1<<0) // 0: NIG port inactive 1: NIG prot active
+  #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT                                              0
+  #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5                                              (0x3<<1) // 00: Map to NWM  port 0 01: Map to NWM  port 1 10: Map to NWM  port 2 11: Map to NWM  port 3
+  #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT                                        1
+  #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5                                                      (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
+  #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT                                                3
+  #define CNIG_REG_NIG_PORT0_CONF_CRC_REMOVE_EN_0_K2_E5                                                      (0x1<<6) // This register controls the option for calculating CRC in CNIG RX datapath, remove CRC field from packet and assert Error indication accordingly to CRC correctness.
+  #define CNIG_REG_NIG_PORT0_CONF_CRC_REMOVE_EN_0_K2_E5_SHIFT                                                6
+  #define CNIG_REG_NIG_PORT0_CONF_CRC_APPEND_EN_0_K2_E5                                                      (0x1<<7) // This bit controls the option for calculating CRC in CNIG TX datapath, and append  CRC field at the end of the packet.
+  #define CNIG_REG_NIG_PORT0_CONF_CRC_APPEND_EN_0_K2_E5_SHIFT                                                7
+  #define CNIG_REG_NIG_PORT0_CONF_CRC_APPEND_CORRUPT_EN_0_K2_E5                                              (0x1<<8) // This bit controls the option for corrupting the calculated CRC value in TX path when Parity or error  indication is received from NIG. Note: As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration.
+  #define CNIG_REG_NIG_PORT0_CONF_CRC_APPEND_CORRUPT_EN_0_K2_E5_SHIFT                                        8
+  #define CNIG_REG_NIG_PORT0_CONF_CRC_APPEND_CORRUPT_ON_ERROR_0_K2_E5                                        (0x1<<9) // This bit controls the option for corrupting the calculated CRC value in TX path when error indication is received from NIG. Note: a. As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration.
+  #define CNIG_REG_NIG_PORT0_CONF_CRC_APPEND_CORRUPT_ON_ERROR_0_K2_E5_SHIFT                                  9
+  #define CNIG_REG_NIG_PORT0_CONF_RATE_LIMITER_ENABLE_0_K2_E5                                                (0x1<<10) // This bit controls the option for enabling rate limitation on the CNIG TX data path via controlling the NIGs backpressure mechanism. When this bit is set, the port's TX datapath is limited to 256xactive_cycles/16[bit/cycle]. This mode is intended to be used on loopback mode but can also be active on when loopback mode is disabled.
+  #define CNIG_REG_NIG_PORT0_CONF_RATE_LIMITER_ENABLE_0_K2_E5_SHIFT                                          10
+  #define CNIG_REG_NIG_PORT0_CONF_RATE_LIMITER_ACTIVE_CYCLES_0_K2_E5                                         (0xf<<11) // This 4 bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels, how many cycles backpressure will be deasserted.  Active cycles vlaue = field value + 1.
+  #define CNIG_REG_NIG_PORT0_CONF_RATE_LIMITER_ACTIVE_CYCLES_0_K2_E5_SHIFT                                   11
+#define CNIG_REG_NW_PORT_MODE_BB                                                                             0x218200UL //Access:RW   DataWidth:0x4    // This register sets the Port Mode for the Network interface. 0 : 2x40G (BB), NA (K2) 1 : 2x50G (BB), 2x20G (K2) 2 : 1x100G (BB), 1x40G (K2) 3 : 4x10G_F (BB) (10G with 4x25 SERDES) NA (K2) 4 : 4x10G_E (BB/K2) (10G with 4x10 SERDES) 5 : 4x20G (BB), NA (K2) 6 : 1x40G + 2x10G (BB), NA (K2) 7 : 1x40G + 2x20G (BB), NA (K2) Others: Unused
+#define CNIG_REG_NIG_PORT1_CONF_K2_E5                                                                        0x218204UL //Access:RW   DataWidth:0xf    // Multi Field Register.
+  #define CNIG_REG_NIG_PORT1_CONF_NIG_PORT_ENABLE_1_K2_E5                                                    (0x1<<0) // 0: NIG port inactive 1: NIG prot active
+  #define CNIG_REG_NIG_PORT1_CONF_NIG_PORT_ENABLE_1_K2_E5_SHIFT                                              0
+  #define CNIG_REG_NIG_PORT1_CONF_NIG_PORT_NWM_PORT_MAP_1_K2_E5                                              (0x3<<1) // 00: Map to NWM  port 0 01: Map to NWM  port 1 10: Map to NWM  port 2 11: Map to NWM  port 3
+  #define CNIG_REG_NIG_PORT1_CONF_NIG_PORT_NWM_PORT_MAP_1_K2_E5_SHIFT                                        1
+  #define CNIG_REG_NIG_PORT1_CONF_NIG_PORT_RATE_1_K2_E5                                                      (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
+  #define CNIG_REG_NIG_PORT1_CONF_NIG_PORT_RATE_1_K2_E5_SHIFT                                                3
+  #define CNIG_REG_NIG_PORT1_CONF_CRC_REMOVE_EN_1_K2_E5                                                      (0x1<<6) // This register controls the option for calculating CRC in CNIG RX datapath, remove CRC field from packet and assert Error indication accordingly to CRC correctness.
+  #define CNIG_REG_NIG_PORT1_CONF_CRC_REMOVE_EN_1_K2_E5_SHIFT                                                6
+  #define CNIG_REG_NIG_PORT1_CONF_CRC_APPEND_EN_1_K2_E5                                                      (0x1<<7) // This bit controls the option for calculating CRC in CNIG TX datapath, and append  CRC field at the end of the packet.
+  #define CNIG_REG_NIG_PORT1_CONF_CRC_APPEND_EN_1_K2_E5_SHIFT                                                7
+  #define CNIG_REG_NIG_PORT1_CONF_CRC_APPEND_CORRUPT_EN_1_K2_E5                                              (0x1<<8) // This bit controls the option for corrupting the calculated CRC value in TX path when Parity or error  indication is received from NIG. Note: As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration.
+  #define CNIG_REG_NIG_PORT1_CONF_CRC_APPEND_CORRUPT_EN_1_K2_E5_SHIFT                                        8
+  #define CNIG_REG_NIG_PORT1_CONF_CRC_APPEND_CORRUPT_ON_ERROR_1_K2_E5                                        (0x1<<9) // This bit controls the option for corrupting the calculated CRC value in TX path when error indication is received from NIG. Note: a. As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration.
+  #define CNIG_REG_NIG_PORT1_CONF_CRC_APPEND_CORRUPT_ON_ERROR_1_K2_E5_SHIFT                                  9
+  #define CNIG_REG_NIG_PORT1_CONF_RATE_LIMITER_ENABLE_1_K2_E5                                                (0x1<<10) // This bit controls the option for enabling rate limitation on the CNIG TX data path via controlling the NIGs backpressure mechanism. When this bit is set, the port's TX datapath is limited to 256xactive_cycles/16[bit/cycle]. This mode is intended to be used on loopback mode but can also be active on when loopback mode is disabled.
+  #define CNIG_REG_NIG_PORT1_CONF_RATE_LIMITER_ENABLE_1_K2_E5_SHIFT                                          10
+  #define CNIG_REG_NIG_PORT1_CONF_RATE_LIMITER_ACTIVE_CYCLES_1_K2_E5                                         (0xf<<11) // This 4 bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels, how many cycles backpressure will be deasserted.  Active cycles vlaue = field value + 1.
+  #define CNIG_REG_NIG_PORT1_CONF_RATE_LIMITER_ACTIVE_CYCLES_1_K2_E5_SHIFT                                   11
+#define CNIG_REG_NW_SERDES_SWAP_BB                                                                           0x218204UL //Access:RW   DataWidth:0x1    // This register allows swapping the SERDES instances 0 : 4x25 SERDES connects to Engine 0 and 4x10 SERDES connects to Engine 1 1 : 4x25 SERDES connects to Engine 1 and 4x10 SERDES connects to Engine 0
+#define CNIG_REG_NIG_PORT2_CONF_K2_E5                                                                        0x218208UL //Access:RW   DataWidth:0xf    // Multi Field Register.
+  #define CNIG_REG_NIG_PORT2_CONF_NIG_PORT_ENABLE_2_K2_E5                                                    (0x1<<0) // 0: NIG port inactive 1: NIG prot active
+  #define CNIG_REG_NIG_PORT2_CONF_NIG_PORT_ENABLE_2_K2_E5_SHIFT                                              0
+  #define CNIG_REG_NIG_PORT2_CONF_NIG_PORT_NWM_PORT_MAP_2_K2_E5                                              (0x3<<1) // 00: Map to NWM  port 0 01: Map to NWM  port 1 10: Map to NWM  port 2 11: Map to NWM  port 3
+  #define CNIG_REG_NIG_PORT2_CONF_NIG_PORT_NWM_PORT_MAP_2_K2_E5_SHIFT                                        1
+  #define CNIG_REG_NIG_PORT2_CONF_NIG_PORT_RATE_2_K2_E5                                                      (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
+  #define CNIG_REG_NIG_PORT2_CONF_NIG_PORT_RATE_2_K2_E5_SHIFT                                                3
+  #define CNIG_REG_NIG_PORT2_CONF_CRC_REMOVE_EN_2_K2_E5                                                      (0x1<<6) // This register controls the option for calculating CRC in CNIG RX datapath, remove CRC field from packet and assert Error indication accordingly to CRC correctness.
+  #define CNIG_REG_NIG_PORT2_CONF_CRC_REMOVE_EN_2_K2_E5_SHIFT                                                6
+  #define CNIG_REG_NIG_PORT2_CONF_CRC_APPEND_EN_2_K2_E5                                                      (0x1<<7) // This bit controls the option for calculating CRC in CNIG TX datapath, and append  CRC field at the end of the packet.
+  #define CNIG_REG_NIG_PORT2_CONF_CRC_APPEND_EN_2_K2_E5_SHIFT                                                7
+  #define CNIG_REG_NIG_PORT2_CONF_CRC_APPEND_CORRUPT_EN_2_K2_E5                                              (0x1<<8) // This bit controls the option for corrupting the calculated CRC value in TX path when Parity or error  indication is received from NIG. Note: As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration.
+  #define CNIG_REG_NIG_PORT2_CONF_CRC_APPEND_CORRUPT_EN_2_K2_E5_SHIFT                                        8
+  #define CNIG_REG_NIG_PORT2_CONF_CRC_APPEND_CORRUPT_ON_ERROR_2_K2_E5                                        (0x1<<9) // This bit controls the option for corrupting the calculated CRC value in TX path when error indication is received from NIG. Note: a. As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration.
+  #define CNIG_REG_NIG_PORT2_CONF_CRC_APPEND_CORRUPT_ON_ERROR_2_K2_E5_SHIFT                                  9
+  #define CNIG_REG_NIG_PORT2_CONF_RATE_LIMITER_ENABLE_2_K2_E5                                                (0x1<<10) // This bit controls the option for enabling rate limitation on the CNIG TX data path via controlling the NIGs backpressure mechanism. When this bit is set, the port's TX datapath is limited to 256xactive_cycles/16[bit/cycle]. This mode is intended to be used on loopback mode but can also be active on when loopback mode is disabled.
+  #define CNIG_REG_NIG_PORT2_CONF_RATE_LIMITER_ENABLE_2_K2_E5_SHIFT                                          10
+  #define CNIG_REG_NIG_PORT2_CONF_RATE_LIMITER_ACTIVE_CYCLES_2_K2_E5                                         (0xf<<11) // This 4 bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels, how many cycles backpressure will be deasserted.  Active cycles vlaue = field value + 1.
+  #define CNIG_REG_NIG_PORT2_CONF_RATE_LIMITER_ACTIVE_CYCLES_2_K2_E5_SHIFT                                   11
+#define CNIG_REG_PMFC_IF_CMD_BB                                                                              0x218208UL //Access:RW   DataWidth:0x11   // Multi Field Register.
+  #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_TYPE_BB                                                               (0x1<<0) // 1 : Memory Access 0 : Register Access
+  #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_TYPE_BB_SHIFT                                                         0
+  #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_ADDR_AUTO_INC_BB                                                      (0x1<<1) // Setting this bit to 1 tells the interface logic auto increment the address based on the programmed byte count.
+  #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_ADDR_AUTO_INC_BB_SHIFT                                                1
+  #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_UNUSED_BB                                                             (0x3<<2) // 
+  #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_UNUSED_BB_SHIFT                                                       2
+  #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_ADDR_AUTO_INC_SIZE_BB                                                 (0xf<<4) // In Port Macro the register addresses are index addresses, a 64bit register is considered a single register, the next 64 bit register will be at addr+1. This register allows HW to automatically increment to a programmable index. Normally the value will be just 1.
+  #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_ADDR_AUTO_INC_SIZE_BB_SHIFT                                           4
+  #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_BYTE_COUNT_BB                                                         (0xff<<8) // Byte Count of the transaction. Limit to 32bytes.
+  #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_BYTE_COUNT_BB_SHIFT                                                   8
+  #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_RESET_FSM_BB                                                          (0x1<<16) // Reset the Register interface state machine
+  #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_RESET_FSM_BB_SHIFT                                                    16
+#define CNIG_REG_NIG_PORT3_CONF_K2_E5                                                                        0x21820cUL //Access:RW   DataWidth:0xf    // Multi Field Register.
+  #define CNIG_REG_NIG_PORT3_CONF_NIG_PORT_ENABLE_3_K2_E5                                                    (0x1<<0) // 0: NIG port inactive 1: NIG prot active
+  #define CNIG_REG_NIG_PORT3_CONF_NIG_PORT_ENABLE_3_K2_E5_SHIFT                                              0
+  #define CNIG_REG_NIG_PORT3_CONF_NIG_PORT_NWM_PORT_MAP_3_K2_E5                                              (0x3<<1) // 00: Map to NWM  port 0 01: Map to NWM  port 1 10: Map to NWM  port 2 11: Map to NWM  port 3
+  #define CNIG_REG_NIG_PORT3_CONF_NIG_PORT_NWM_PORT_MAP_3_K2_E5_SHIFT                                        1
+  #define CNIG_REG_NIG_PORT3_CONF_NIG_PORT_RATE_3_K2_E5                                                      (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
+  #define CNIG_REG_NIG_PORT3_CONF_NIG_PORT_RATE_3_K2_E5_SHIFT                                                3
+  #define CNIG_REG_NIG_PORT3_CONF_CRC_REMOVE_EN_3_K2_E5                                                      (0x1<<6) // This register controls the option for calculating CRC in CNIG RX datapath, remove CRC field from packet and assert Error indication accordingly to CRC correctness.
+  #define CNIG_REG_NIG_PORT3_CONF_CRC_REMOVE_EN_3_K2_E5_SHIFT                                                6
+  #define CNIG_REG_NIG_PORT3_CONF_CRC_APPEND_EN_3_K2_E5                                                      (0x1<<7) // This bit controls the option for calculating CRC in CNIG TX datapath, and append  CRC field at the end of the packet.
+  #define CNIG_REG_NIG_PORT3_CONF_CRC_APPEND_EN_3_K2_E5_SHIFT                                                7
+  #define CNIG_REG_NIG_PORT3_CONF_CRC_APPEND_CORRUPT_EN_3_K2_E5                                              (0x1<<8) // This bit controls the option for corrupting the calculated CRC value in TX path when Parity or error  indication is received from NIG. Note: As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration.
+  #define CNIG_REG_NIG_PORT3_CONF_CRC_APPEND_CORRUPT_EN_3_K2_E5_SHIFT                                        8
+  #define CNIG_REG_NIG_PORT3_CONF_CRC_APPEND_CORRUPT_ON_ERROR_3_K2_E5                                        (0x1<<9) // This bit controls the option for corrupting the calculated CRC value in TX path when error indication is received from NIG. Note: a. As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration.
+  #define CNIG_REG_NIG_PORT3_CONF_CRC_APPEND_CORRUPT_ON_ERROR_3_K2_E5_SHIFT                                  9
+  #define CNIG_REG_NIG_PORT3_CONF_RATE_LIMITER_ENABLE_3_K2_E5                                                (0x1<<10) // This bit controls the option for enabling rate limitation on the CNIG TX data path via controlling the NIGs backpressure mechanism. When this bit is set, the port's TX datapath is limited to 256xactive_cycles/16[bit/cycle]. This mode is intended to be used on loopback mode but can also be active on when loopback mode is disabled.
+  #define CNIG_REG_NIG_PORT3_CONF_RATE_LIMITER_ENABLE_3_K2_E5_SHIFT                                          10
+  #define CNIG_REG_NIG_PORT3_CONF_RATE_LIMITER_ACTIVE_CYCLES_3_K2_E5                                         (0xf<<11) // This 4 bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels, how many cycles backpressure will be deasserted.  Active cycles vlaue = field value + 1.
+  #define CNIG_REG_NIG_PORT3_CONF_RATE_LIMITER_ACTIVE_CYCLES_3_K2_E5_SHIFT                                   11
+#define CNIG_REG_PMFC_IF_STATUS_BB                                                                           0x21820cUL //Access:R    DataWidth:0x3    // Multi Field Register.
+  #define CNIG_REG_PMFC_IF_STATUS_PMFC_IF_BUSY_BB                                                            (0x1<<0) // 1 : State Machine is busy
+  #define CNIG_REG_PMFC_IF_STATUS_PMFC_IF_BUSY_BB_SHIFT                                                      0
+  #define CNIG_REG_PMFC_IF_STATUS_PMFC_IF_DONE_BB                                                            (0x1<<1) // 1 : State Machine has completed operation.
+  #define CNIG_REG_PMFC_IF_STATUS_PMFC_IF_DONE_BB_SHIFT                                                      1
+  #define CNIG_REG_PMFC_IF_STATUS_PMFC_IF_ERROR_BB                                                           (0x1<<2) // 1 : Last transaction resulted in an error
+  #define CNIG_REG_PMFC_IF_STATUS_PMFC_IF_ERROR_BB_SHIFT                                                     2
+#define CNIG_REG_LOOPBACK_MODE_K2_E5                                                                         0x218210UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define CNIG_REG_LOOPBACK_MODE_LOOPBACK_ENABLE_K2_E5                                                       (0x1<<0) // This regiseter enables loopback mode (used for debug) 0 - loopback inactive 1 - loopback active
+  #define CNIG_REG_LOOPBACK_MODE_LOOPBACK_ENABLE_K2_E5_SHIFT                                                 0
+  #define CNIG_REG_LOOPBACK_MODE_LOOPBACK_MODE_K2_E5                                                         (0x1<<1) // 0: mode0 is used with the following loopback mapping: NIG TX port 0 => NIG RX port 0 NIG TX port 1 => NIG RX port 1 NIG TX port 2 => NIG RX port 2 NIG TX port 3 => NIG RX port 3 1: mode1 is used with the following loopback mapping: NIG TX port 0 => NIG RX port 1 NIG TX port 1 => NIG RX port 0 NIG TX port 2 => NIG RX port 3 NIG TX port 3 => NIG RX port 2
+  #define CNIG_REG_LOOPBACK_MODE_LOOPBACK_MODE_K2_E5_SHIFT                                                   1
+#define CNIG_REG_PMFC_IF_ADDR_BB                                                                             0x218210UL //Access:RW   DataWidth:0x20   // Address of PM IF transaction. For Register Access 31:26 : Stage ID 25:25 : Register Type 1 = Generic Register, 0 = Per Port 24:08 : Register Offset 07:00 : Port Number For Memory Access 31:26 : Stage ID 25:00 : Memory Index
+#define CNIG_REG_NWM_ERROR_MASK_K2_E5                                                                        0x218214UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define CNIG_REG_NWM_ERROR_MASK_LENGTH_K2_E5                                                               (0x1<<0) // Set to 1 for masking invlaid legth fram error.
+  #define CNIG_REG_NWM_ERROR_MASK_LENGTH_K2_E5_SHIFT                                                         0
+  #define CNIG_REG_NWM_ERROR_MASK_CRC_K2_E5                                                                  (0x1<<1) // Set to 1 for masking crc error.
+  #define CNIG_REG_NWM_ERROR_MASK_CRC_K2_E5_SHIFT                                                            1
+  #define CNIG_REG_NWM_ERROR_MASK_DEC_K2_E5                                                                  (0x1<<2) // Set to 1 for masking decoding error.
+  #define CNIG_REG_NWM_ERROR_MASK_DEC_K2_E5_SHIFT                                                            2
+  #define CNIG_REG_NWM_ERROR_MASK_SHORT_FRAME_K2_E5                                                          (0x1<<3) // Set to 1 for masking fifo overflow error.
+  #define CNIG_REG_NWM_ERROR_MASK_SHORT_FRAME_K2_E5_SHIFT                                                    3
+  #define CNIG_REG_NWM_ERROR_MASK_REMOTE_K2_E5                                                               (0x1<<4) // Set to 1 for masking remote error.
+  #define CNIG_REG_NWM_ERROR_MASK_REMOTE_K2_E5_SHIFT                                                         4
+  #define CNIG_REG_NWM_ERROR_MASK_VLAN_TAG_K2_E5                                                             (0x1<<5) // Set to 1 for masking vlan tag error.
+  #define CNIG_REG_NWM_ERROR_MASK_VLAN_TAG_K2_E5_SHIFT                                                       5
+  #define CNIG_REG_NWM_ERROR_MASK_NWM_ERROR_TRASMIT_K2_E5                                                    (0x1<<6) // Set to 1 for masking vlan transmit error.
+  #define CNIG_REG_NWM_ERROR_MASK_NWM_ERROR_TRASMIT_K2_E5_SHIFT                                              6
+  #define CNIG_REG_NWM_ERROR_MASK_NWM_ERROR_VLAN_K2_E5                                                       (0x1<<7) // Set to 1 for masking vlan error.
+  #define CNIG_REG_NWM_ERROR_MASK_NWM_ERROR_VLAN_K2_E5_SHIFT                                                 7
+#define CNIG_REG_PMFC_IF_WRDATA_BB                                                                           0x218214UL //Access:RW   DataWidth:0x20   // Write Data. This should be the last item written for a transaction. Writing to this register will kick off a transaction
+#define CNIG_REG_INT_STS_BB                                                                                  0x2182e8UL //Access:R    DataWidth:0x6    // Multi Field Register.
+#define CNIG_REG_INT_STS_K2_E5                                                                               0x218218UL //Access:R    DataWidth:0x7    // Multi Field Register.
+  #define CNIG_REG_INT_STS_ADDRESS_ERROR                                                                     (0x1<<0) // Signals an unknown address to the rf module.
+  #define CNIG_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                               0
+  #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT0_BB                                                           (0x1<<4) // This interrupt is asserted when a violation of the ADD CRC PORT  STM occurs. It can result if a packet size is less than 256bit is sent by NIG (which is illegal).
+  #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT0_BB_SHIFT                                                     4
+  #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT0_K2_E5                                                        (0x1<<1) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP +  Byte Valid > 28" without inserting an "empty" transaction in between.
+  #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT0_K2_E5_SHIFT                                                  1
+  #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT1_K2_E5                                                        (0x1<<2) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP +  Byte Valid > 28" without inserting an "empty" transaction in between.
+  #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT1_K2_E5_SHIFT                                                  2
+  #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT2_BB                                                           (0x1<<5) // This interrupt is asserted when a violation of the ADD CRC PORT  STM occurs. It can result if a packet size is less than 256bit is sent by NIG (which is illegal).
+  #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT2_BB_SHIFT                                                     5
+  #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT2_K2_E5                                                        (0x1<<3) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP +  Byte Valid > 28" without inserting an "empty" transaction in between.
+  #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT2_K2_E5_SHIFT                                                  3
+  #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT3_K2_E5                                                        (0x1<<4) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP +  Byte Valid > 28" without inserting an "empty" transaction in between.
+  #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT3_K2_E5_SHIFT                                                  4
+  #define CNIG_REG_INT_STS_TDM_LANE_0_BANDWITH_EXCEED_K2_E5                                                  (0x1<<5) // This interrupt is asserted when a violation of the allocated TDM lane0 bandwith is detected
+  #define CNIG_REG_INT_STS_TDM_LANE_0_BANDWITH_EXCEED_K2_E5_SHIFT                                            5
+  #define CNIG_REG_INT_STS_TDM_LANE_1_BANDWITH_EXCEED_K2_E5                                                  (0x1<<6) // This interrupt is asserted when a violation of the allocated TDM lane1 bandwith is detected
+  #define CNIG_REG_INT_STS_TDM_LANE_1_BANDWITH_EXCEED_K2_E5_SHIFT                                            6
+  #define CNIG_REG_INT_STS_PMEG_INTR_BB                                                                      (0x1<<1) // Interrupt from PMEG.
+  #define CNIG_REG_INT_STS_PMEG_INTR_BB_SHIFT                                                                1
+  #define CNIG_REG_INT_STS_PMFC_INTR_BB                                                                      (0x1<<2) // Interrupt from PMFC.
+  #define CNIG_REG_INT_STS_PMFC_INTR_BB_SHIFT                                                                2
+  #define CNIG_REG_INT_STS_FIFO_ERROR_BB                                                                     (0x1<<3) // Error from an Interface FIFO.
+  #define CNIG_REG_INT_STS_FIFO_ERROR_BB_SHIFT                                                               3
+#define CNIG_REG_PMFC_IF_RDDATA_BB                                                                           0x218218UL //Access:R    DataWidth:0x20   // Read Data
+#define CNIG_REG_INT_MASK_BB                                                                                 0x2182ecUL //Access:RW   DataWidth:0x6    // Multi Field Register.
+#define CNIG_REG_INT_MASK_K2_E5                                                                              0x21821cUL //Access:RW   DataWidth:0x7    // Multi Field Register.
+  #define CNIG_REG_INT_MASK_ADDRESS_ERROR                                                                    (0x1<<0) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.ADDRESS_ERROR .
+  #define CNIG_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                              0
+  #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT0_BB                                                          (0x1<<4) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.TX_ILLEGAL_SOP_PORT0 .
+  #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT0_BB_SHIFT                                                    4
+  #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT0_K2_E5                                                       (0x1<<1) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.TX_ILLEGAL_SOP_PORT0 .
+  #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT0_K2_E5_SHIFT                                                 1
+  #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT1_K2_E5                                                       (0x1<<2) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.TX_ILLEGAL_SOP_PORT1 .
+  #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT1_K2_E5_SHIFT                                                 2
+  #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT2_BB                                                          (0x1<<5) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.TX_ILLEGAL_SOP_PORT2 .
+  #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT2_BB_SHIFT                                                    5
+  #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT2_K2_E5                                                       (0x1<<3) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.TX_ILLEGAL_SOP_PORT2 .
+  #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT2_K2_E5_SHIFT                                                 3
+  #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT3_K2_E5                                                       (0x1<<4) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.TX_ILLEGAL_SOP_PORT3 .
+  #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT3_K2_E5_SHIFT                                                 4
+  #define CNIG_REG_INT_MASK_TDM_LANE_0_BANDWITH_EXCEED_K2_E5                                                 (0x1<<5) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.TDM_LANE_0_BANDWITH_EXCEED .
+  #define CNIG_REG_INT_MASK_TDM_LANE_0_BANDWITH_EXCEED_K2_E5_SHIFT                                           5
+  #define CNIG_REG_INT_MASK_TDM_LANE_1_BANDWITH_EXCEED_K2_E5                                                 (0x1<<6) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.TDM_LANE_1_BANDWITH_EXCEED .
+  #define CNIG_REG_INT_MASK_TDM_LANE_1_BANDWITH_EXCEED_K2_E5_SHIFT                                           6
+  #define CNIG_REG_INT_MASK_PMEG_INTR_BB                                                                     (0x1<<1) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.PMEG_INTR .
+  #define CNIG_REG_INT_MASK_PMEG_INTR_BB_SHIFT                                                               1
+  #define CNIG_REG_INT_MASK_PMFC_INTR_BB                                                                     (0x1<<2) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.PMFC_INTR .
+  #define CNIG_REG_INT_MASK_PMFC_INTR_BB_SHIFT                                                               2
+  #define CNIG_REG_INT_MASK_FIFO_ERROR_BB                                                                    (0x1<<3) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.FIFO_ERROR .
+  #define CNIG_REG_INT_MASK_FIFO_ERROR_BB_SHIFT                                                              3
+#define CNIG_REG_PMEG_IF_CMD_BB                                                                              0x21821cUL //Access:RW   DataWidth:0x11   // Multi Field Register.
+  #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_TYPE_BB                                                               (0x1<<0) // 1 : Memory Access 0 : Register Access
+  #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_TYPE_BB_SHIFT                                                         0
+  #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_ADDR_AUTO_INC_BB                                                      (0x1<<1) // Setting this bit to 1 tells the interface logic auto increment the address based on the programmed byte count.
+  #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_ADDR_AUTO_INC_BB_SHIFT                                                1
+  #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_UNUSED_BB                                                             (0x3<<2) // 
+  #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_UNUSED_BB_SHIFT                                                       2
+  #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_ADDR_AUTO_INC_SIZE_BB                                                 (0xf<<4) // In Port Macro the register addresses are index addresses, a 64bit register is considered a single register, the next 64 bit register will be at addr+1. This register allows HW to automatically increment to a programmable index. Normally the value will be just 1.
+  #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_ADDR_AUTO_INC_SIZE_BB_SHIFT                                           4
+  #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_BYTE_COUNT_BB                                                         (0xff<<8) // Byte Count of the transaction. Limit to 32bytes.
+  #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_BYTE_COUNT_BB_SHIFT                                                   8
+  #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_RESET_FSM_BB                                                          (0x1<<16) // Reset the Register interface state machine
+  #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_RESET_FSM_BB_SHIFT                                                    16
+#define CNIG_REG_INT_STS_WR_BB                                                                               0x2182f0UL //Access:WR   DataWidth:0x6    // Multi Field Register.
+#define CNIG_REG_INT_STS_WR_K2_E5                                                                            0x218220UL //Access:WR   DataWidth:0x7    // Multi Field Register.
+  #define CNIG_REG_INT_STS_WR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define CNIG_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                            0
+  #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT0_BB                                                        (0x1<<4) // This interrupt is asserted when a violation of the ADD CRC PORT  STM occurs. It can result if a packet size is less than 256bit is sent by NIG (which is illegal).
+  #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT0_BB_SHIFT                                                  4
+  #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT0_K2_E5                                                     (0x1<<1) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP +  Byte Valid > 28" without inserting an "empty" transaction in between.
+  #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT0_K2_E5_SHIFT                                               1
+  #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT1_K2_E5                                                     (0x1<<2) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP +  Byte Valid > 28" without inserting an "empty" transaction in between.
+  #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT1_K2_E5_SHIFT                                               2
+  #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT2_BB                                                        (0x1<<5) // This interrupt is asserted when a violation of the ADD CRC PORT  STM occurs. It can result if a packet size is less than 256bit is sent by NIG (which is illegal).
+  #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT2_BB_SHIFT                                                  5
+  #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT2_K2_E5                                                     (0x1<<3) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP +  Byte Valid > 28" without inserting an "empty" transaction in between.
+  #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT2_K2_E5_SHIFT                                               3
+  #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT3_K2_E5                                                     (0x1<<4) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP +  Byte Valid > 28" without inserting an "empty" transaction in between.
+  #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT3_K2_E5_SHIFT                                               4
+  #define CNIG_REG_INT_STS_WR_TDM_LANE_0_BANDWITH_EXCEED_K2_E5                                               (0x1<<5) // This interrupt is asserted when a violation of the allocated TDM lane0 bandwith is detected
+  #define CNIG_REG_INT_STS_WR_TDM_LANE_0_BANDWITH_EXCEED_K2_E5_SHIFT                                         5
+  #define CNIG_REG_INT_STS_WR_TDM_LANE_1_BANDWITH_EXCEED_K2_E5                                               (0x1<<6) // This interrupt is asserted when a violation of the allocated TDM lane1 bandwith is detected
+  #define CNIG_REG_INT_STS_WR_TDM_LANE_1_BANDWITH_EXCEED_K2_E5_SHIFT                                         6
+  #define CNIG_REG_INT_STS_WR_PMEG_INTR_BB                                                                   (0x1<<1) // Interrupt from PMEG.
+  #define CNIG_REG_INT_STS_WR_PMEG_INTR_BB_SHIFT                                                             1
+  #define CNIG_REG_INT_STS_WR_PMFC_INTR_BB                                                                   (0x1<<2) // Interrupt from PMFC.
+  #define CNIG_REG_INT_STS_WR_PMFC_INTR_BB_SHIFT                                                             2
+  #define CNIG_REG_INT_STS_WR_FIFO_ERROR_BB                                                                  (0x1<<3) // Error from an Interface FIFO.
+  #define CNIG_REG_INT_STS_WR_FIFO_ERROR_BB_SHIFT                                                            3
+#define CNIG_REG_PMEG_IF_STATUS_BB                                                                           0x218220UL //Access:R    DataWidth:0x3    // Multi Field Register.
+  #define CNIG_REG_PMEG_IF_STATUS_PMEG_IF_BUSY_BB                                                            (0x1<<0) // 1 : State Machine is busy
+  #define CNIG_REG_PMEG_IF_STATUS_PMEG_IF_BUSY_BB_SHIFT                                                      0
+  #define CNIG_REG_PMEG_IF_STATUS_PMEG_IF_DONE_BB                                                            (0x1<<1) // 1 : State Machine has completed operation.
+  #define CNIG_REG_PMEG_IF_STATUS_PMEG_IF_DONE_BB_SHIFT                                                      1
+  #define CNIG_REG_PMEG_IF_STATUS_PMEG_IF_ERROR_BB                                                           (0x1<<2) // 1 : Last transaction resulted in an error
+  #define CNIG_REG_PMEG_IF_STATUS_PMEG_IF_ERROR_BB_SHIFT                                                     2
+#define CNIG_REG_INT_STS_CLR_BB                                                                              0x2182f4UL //Access:RC   DataWidth:0x6    // Multi Field Register.
+#define CNIG_REG_INT_STS_CLR_K2_E5                                                                           0x218224UL //Access:RC   DataWidth:0x7    // Multi Field Register.
+  #define CNIG_REG_INT_STS_CLR_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define CNIG_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                           0
+  #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT0_BB                                                       (0x1<<4) // This interrupt is asserted when a violation of the ADD CRC PORT  STM occurs. It can result if a packet size is less than 256bit is sent by NIG (which is illegal).
+  #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT0_BB_SHIFT                                                 4
+  #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT0_K2_E5                                                    (0x1<<1) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP +  Byte Valid > 28" without inserting an "empty" transaction in between.
+  #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT0_K2_E5_SHIFT                                              1
+  #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT1_K2_E5                                                    (0x1<<2) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP +  Byte Valid > 28" without inserting an "empty" transaction in between.
+  #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT1_K2_E5_SHIFT                                              2
+  #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT2_BB                                                       (0x1<<5) // This interrupt is asserted when a violation of the ADD CRC PORT  STM occurs. It can result if a packet size is less than 256bit is sent by NIG (which is illegal).
+  #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT2_BB_SHIFT                                                 5
+  #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT2_K2_E5                                                    (0x1<<3) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP +  Byte Valid > 28" without inserting an "empty" transaction in between.
+  #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT2_K2_E5_SHIFT                                              3
+  #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT3_K2_E5                                                    (0x1<<4) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP +  Byte Valid > 28" without inserting an "empty" transaction in between.
+  #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT3_K2_E5_SHIFT                                              4
+  #define CNIG_REG_INT_STS_CLR_TDM_LANE_0_BANDWITH_EXCEED_K2_E5                                              (0x1<<5) // This interrupt is asserted when a violation of the allocated TDM lane0 bandwith is detected
+  #define CNIG_REG_INT_STS_CLR_TDM_LANE_0_BANDWITH_EXCEED_K2_E5_SHIFT                                        5
+  #define CNIG_REG_INT_STS_CLR_TDM_LANE_1_BANDWITH_EXCEED_K2_E5                                              (0x1<<6) // This interrupt is asserted when a violation of the allocated TDM lane1 bandwith is detected
+  #define CNIG_REG_INT_STS_CLR_TDM_LANE_1_BANDWITH_EXCEED_K2_E5_SHIFT                                        6
+  #define CNIG_REG_INT_STS_CLR_PMEG_INTR_BB                                                                  (0x1<<1) // Interrupt from PMEG.
+  #define CNIG_REG_INT_STS_CLR_PMEG_INTR_BB_SHIFT                                                            1
+  #define CNIG_REG_INT_STS_CLR_PMFC_INTR_BB                                                                  (0x1<<2) // Interrupt from PMFC.
+  #define CNIG_REG_INT_STS_CLR_PMFC_INTR_BB_SHIFT                                                            2
+  #define CNIG_REG_INT_STS_CLR_FIFO_ERROR_BB                                                                 (0x1<<3) // Error from an Interface FIFO.
+  #define CNIG_REG_INT_STS_CLR_FIFO_ERROR_BB_SHIFT                                                           3
+#define CNIG_REG_PMEG_IF_ADDR_BB                                                                             0x218224UL //Access:RW   DataWidth:0x20   // Address of PM IF transaction. For Register Access 31:26 : Stage ID 25:25 : Register Type 1 = Generic Register, 0 = Per Port 24:08 : Register Offset 07:00 : Port Number For Memory Access 31:26 : Stage ID 25:00 : Memory Index
+#define CNIG_REG_NWM_LPI_DEFUALT_VALUE_K2_E5                                                                 0x218228UL //Access:RW   DataWidth:0x1    // This register is used to set the value of NWM lpi_indicate default value. The lpi value will be overwriten by cpmu vlaue accordigly to the NWM NIG mapping.
+#define CNIG_REG_PMEG_IF_WRDATA_BB                                                                           0x218228UL //Access:RW   DataWidth:0x20   // Write Data. This should be the last item written for a transaction. Writing to this register will kick off a transaction
+#define CNIG_REG_PMEG_IF_RDDATA_BB                                                                           0x21822cUL //Access:R    DataWidth:0x20   // Read Data
+#define CNIG_REG_PRTY_MASK_BB                                                                                0x21834cUL //Access:RW   DataWidth:0x2    // Multi Field Register.
+#define CNIG_REG_PRTY_MASK_K2_E5                                                                             0x218230UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define CNIG_REG_PRTY_MASK_DATAPATH_TX                                                                     (0x1<<1) // This bit masks, when set, the Parity bit: CNIG_REG_PRTY_STS.DATAPATH_TX .
+  #define CNIG_REG_PRTY_MASK_DATAPATH_TX_SHIFT                                                               1
+  #define CNIG_REG_PRTY_MASK_DATAPATH_RX_BB                                                                  (0x1<<0) // This bit masks, when set, the Parity bit: CNIG_REG_PRTY_STS.DATAPATH_RX .
+  #define CNIG_REG_PRTY_MASK_DATAPATH_RX_BB_SHIFT                                                            0
+#define CNIG_REG_MDIO_SW_ARB_BB                                                                              0x218230UL //Access:RW   DataWidth:0x10   // 
+#define CNIG_REG_MDIO_SW_ARB_SIZE                                                                            2
+#define CNIG_REG_LED_CONTROL_BB                                                                              0x21823cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define CNIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_BB                                                           (0x1<<0) // If set overrides hardware control of the Traffic LED. The Traffic LED will then be controlled via bit LED_CONTROL_TRAFFIC And LED_CONTROL_BLINK_TRAFFIC
+  #define CNIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_BB_SHIFT                                                     0
+  #define CNIG_REG_LED_CONTROL_TRAFFIC_BB                                                                    (0x1<<4) // If set along with the LED_CONTROL_OVERRIDE_TRAFFIC bit turns on the Traffic LED. If the LED_CONTROL_BLINK_TRAFFIC bit bit is also set; the LED will blink with blink rate specified in LED_CONTROL_BLINK_RATE and LED_CONTROL_BLINK_RATE_ENA fields.
+  #define CNIG_REG_LED_CONTROL_TRAFFIC_BB_SHIFT                                                              4
+  #define CNIG_REG_LED_CONTROL_BLINK_TRAFFIC_BB                                                              (0x1<<8) // Port0: If set along with the LED_CONTROL_OVERRIDE_TRAFFIC bit and LED_CONTROL_TRAFFIC LED bit; the Traffic LED will blink with the blink rate specified in LED_CONTROL_BLINK_RATE and LED_CONTROL_BLINK_RATE_ENA fields.
+  #define CNIG_REG_LED_CONTROL_BLINK_TRAFFIC_BB_SHIFT                                                        8
+  #define CNIG_REG_LED_CONTROL_BLINK_RATE_ENA_BB                                                             (0x1<<12) // This bit is set to enable the use of the LED_CONTROL_BLINK_RATE field defined below. If this bit is cleared; then the blink rate will be about 16Hz.
+  #define CNIG_REG_LED_CONTROL_BLINK_RATE_ENA_BB_SHIFT                                                       12
+  #define CNIG_REG_LED_CONTROL_BLINK_RATE_BB                                                                 (0xfff<<20) // Specifies the period of each blink cycle (on + off) for Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field is reset to 0x162; giving a default blink period of approximately 16Hz for the 375Mhz clock (used in 10G/40G modes). For 425Mhz clock (used in 50G/100G modes), the value of 0xb9f should be used for a 16Hz rate.
+  #define CNIG_REG_LED_CONTROL_BLINK_RATE_BB_SHIFT                                                           20
+#define CNIG_REG_COSMAP_TX_SET_K2_E5                                                                         0x218240UL //Access:RW   DataWidth:0x8    // This register enable to read and write the cosmap 8 bit value for each NWM port.
+#define CNIG_REG_COSMAP_TX_SET_SIZE                                                                          4
+#define CNIG_REG_LED_MODE_BB                                                                                 0x218240UL //Access:RW   DataWidth:0x4    // Led mode: 0     -> MAC; 1-3   -> PHY1; 4     -> MAC2; 5-7   -> PHY4; 8     -> MAC3; 9     -> 11PHY7; 12    -> MAC4; 13-15 -> PHY10;
+#define CNIG_REG_LED_PORT_SPD0_EN_BB                                                                         0x218244UL //Access:RW   DataWidth:0x8    // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused A '1' to each bit location will enable the corresponding speed to activate the LED.
+#define CNIG_REG_LED_PORT_SPD1_EN_BB                                                                         0x218248UL //Access:RW   DataWidth:0x8    // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused A '1' to each bit location will enable the corresponding speed to activate the LED.
+#define CNIG_REG_LED_PORT_SPD2_EN_BB                                                                         0x21824cUL //Access:RW   DataWidth:0x8    // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused A '1' to each bit location will enable the corresponding speed to activate the LED.
+#define CNIG_REG_ECO_RESERVED_BB                                                                             0x218238UL //Access:RW   DataWidth:0x8    // Reserved bits for ECO.
+#define CNIG_REG_ECO_RESERVED_K2_E5                                                                          0x218250UL //Access:RW   DataWidth:0x8    // Reserved bits for ECO.
+#define CNIG_REG_MAC_LED_SPEED_BB                                                                            0x218250UL //Access:RW   DataWidth:0x8    // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused This register allows the MAC (Driver/FW) to set the link speed of the particular port. This combined with the mask for each LED will activate the corresponding LED. For ex. if the link speed is 10G, then SW will set bit[1] of this register. If 10G is enabled on LED SPD1, then SPD1 will light up, SPD0 and SPD2 will not.
+#define CNIG_REG_DBG_SELECT_K2_E5                                                                            0x218254UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define CNIG_REG_MAC_LED_SWAP_BB                                                                             0x218254UL //Access:RW   DataWidth:0xe    // Multi Field Register.
+  #define CNIG_REG_MAC_LED_SWAP_P0_BB                                                                        (0x3<<0) // Device Drivers view of a physical port is through the PCIE physical function that was enumerated. In a typical setup, Physical function 0 is connected to Network Port 0, PF1 to NW1 and so on. However, there are cases when the PF and NW conenctions are swapped. This register sets up which PF is connected to which Network Port. For a multiport/multifunction configuration, appropriate settings should be chosen. For ex. in a two port device, only two sets of the the bits below are valid. a Four port device has all four sets of bits valid. These bits makes the connection of Network Port 0 to the corresponding Physical function. 0  -> NW0 connects to PF0 1  -> NW0 connects to PF1 2  -> NW0 connects to PF2 3  -> NW0 connects to PF3
+  #define CNIG_REG_MAC_LED_SWAP_P0_BB_SHIFT                                                                  0
+  #define CNIG_REG_MAC_LED_SWAP_P1_BB                                                                        (0x3<<4) // These bits makes the connection of Network Port 1 to the corresponding Physical function. 0  -> NW1 connects to PF0 1  -> NW1 connects to PF1 2  -> NW1 connects to PF2 3  -> NW1 connects to PF3
+  #define CNIG_REG_MAC_LED_SWAP_P1_BB_SHIFT                                                                  4
+  #define CNIG_REG_MAC_LED_SWAP_P2_BB                                                                        (0x3<<8) // These bits makes the connection of Network Port 2 to the corresponding Physical function. 0  -> NW2 connects to PF0 1  -> NW2 connects to PF1 2  -> NW2 connects to PF2 3  -> NW2 connects to PF3
+  #define CNIG_REG_MAC_LED_SWAP_P2_BB_SHIFT                                                                  8
+  #define CNIG_REG_MAC_LED_SWAP_P3_BB                                                                        (0x3<<12) // These bits makes the connection of Network Port 2 to the corresponding Physical function. 0  -> NW3 connects to PF0 1  -> NW3 connects to PF1 2  -> NW3 connects to PF2 3  -> NW3 connects to PF3
+  #define CNIG_REG_MAC_LED_SWAP_P3_BB_SHIFT                                                                  12
+#define CNIG_REG_DBG_DWORD_ENABLE_K2_E5                                                                      0x218258UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define CNIG_REG_PMFC_RAW_SPEED_LN0_BB                                                                       0x218258UL //Access:R    DataWidth:0x8    // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused RAW version of the LED from the SERDES..
+#define CNIG_REG_DBG_SHIFT_K2_E5                                                                             0x21825cUL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define CNIG_REG_PMFC_RAW_SPEED_LN1_BB                                                                       0x21825cUL //Access:R    DataWidth:0x8    // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused RAW version of the LED from the SERDES..
+#define CNIG_REG_DBG_FORCE_VALID_K2_E5                                                                       0x218260UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define CNIG_REG_PMFC_RAW_SPEED_LN2_BB                                                                       0x218260UL //Access:R    DataWidth:0x8    // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused RAW version of the LED from the SERDES..
+#define CNIG_REG_DBG_FORCE_FRAME_K2_E5                                                                       0x218264UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define CNIG_REG_PMFC_RAW_SPEED_LN3_BB                                                                       0x218264UL //Access:R    DataWidth:0x8    // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused RAW version of the LED from the SERDES..
+#define CNIG_REG_PMEG_RAW_SPEED_LN0_BB                                                                       0x218268UL //Access:R    DataWidth:0x8    // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused RAW version of the LED from the SERDES..
+#define CNIG_REG_PMEG_RAW_SPEED_LN1_BB                                                                       0x21826cUL //Access:R    DataWidth:0x8    // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused RAW version of the LED from the SERDES..
+#define CNIG_REG_PMEG_RAW_SPEED_LN2_BB                                                                       0x218270UL //Access:R    DataWidth:0x8    // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused RAW version of the LED from the SERDES..
+#define CNIG_REG_PMEG_RAW_SPEED_LN3_BB                                                                       0x218274UL //Access:R    DataWidth:0x8    // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused RAW version of the LED from the SERDES..
+#define CNIG_REG_PMIF_OVERRIDE_ENABLE_BB                                                                     0x218278UL //Access:RW   DataWidth:0x1    // When set, PMIF block uses values in following registers to configure NIG - PM interface
+#define CNIG_REG_PMIF_OVERRIDE_PORT_IS_PMEG_BB                                                               0x21827cUL //Access:RW   DataWidth:0x4    // These bits are used to set which NIG Ports are used with the PM4x10. A 1'b0 in these bits indicates that NIG Port is assigned to the PM4x25.
+#define CNIG_REG_DBG_OUT_DATA_K2_E5                                                                          0x218280UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define CNIG_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define CNIG_REG_PMIF_OVERRIDE_PMEG_NIG_PORT_BB                                                              0x218280UL //Access:RW   DataWidth:0x8    // These bits are used to define which NIG port is assigned to each PMEG Port. [1:0] -- PMEG Port 0 [3:2] -- PMEG Port 1 [5:4] -- PMEG Port 2 [7:6] -- PMEG Port 3
+#define CNIG_REG_PMIF_OVERRIDE_PMFC_NIG_PORT_BB                                                              0x218284UL //Access:RW   DataWidth:0x8    // These bits are used to define which NIG port is assigned to each PMFC Port. [1:0] -- PMFC Port 0 [3:2] -- PMFC Port 1 [5:4] -- PMFC Port 2 [7:6] -- PMFC Port 3
+#define CNIG_REG_PMIF_OVERRIDE_PMEG_PORTID_BB                                                                0x218288UL //Access:RW   DataWidth:0x2    // These bits are used to set the number of active ports on PMEG. The value in this register is added to the PMEG Port ID every cycle. Valid values are: 0 -- Only Port 0 is used 1 -- All Ports (0-3) are used 2 -- Only Ports 0 and 2 are used
+#define CNIG_REG_PMIF_OVERRIDE_PMFC_PORTID_BB                                                                0x21828cUL //Access:RW   DataWidth:0x2    // These bits are used to set the number of active ports on PMFC. The value in this register is added to the PMFC Port ID every cycle. Valid values are: 0 -- Only Port 0 is used 1 -- All Ports (0-3) are used 2 -- Only Ports 0 and 2 are used
+#define CNIG_REG_CNIG_DBG_NIGTX_FIFO_AFULL_THRESH_BB                                                         0x218290UL //Access:RW   DataWidth:0x3    // This register sets the Almost Full Threshold for the NIG Tx FIFOs. When this threshold is reached, the backpressure signal will be sent to NIG to stop transmitting data.
+#define CNIG_REG_CNIG_DBG_PMEG_TXFIFO_THRESH_BB                                                              0x218294UL //Access:RW   DataWidth:0x6    // This register sets the Threshold level for Tx Credits from the 4x10 PM. Data will not be sent to the PM unless the current number of credits is greater than the number in this register.  This allows extra levels of registers between the PM and CNIG blocks without overflow.
+#define CNIG_REG_CNIG_DBG_PMFC_TXFIFO_THRESH_BB                                                              0x218298UL //Access:RW   DataWidth:0x6    // This register sets the Threshold level for Tx Credits from the 1x40 PM. Data will not be sent to the PM unless the current number of credits is greater than the number in this register.  This allows extra levels of registers between the PM and CNIG blocks without overflow.
+#define CNIG_REG_CNIG_DBG_FIFO_ERROR_BB                                                                      0x21829cUL //Access:R    DataWidth:0x5    // This register latches the FIFO Error bits from the PMFC Rx FIFO (bit [4]) and the NIG Tx FIFOs (bits [3:0]).  To clear these bits, the NIG block must be reset.
+#define CNIG_REG_DBG_OUT_VALID_K2_E5                                                                         0x2182a0UL //Access:R    DataWidth:0x4    // Dbgmux output valid
+#define CNIG_REG_CNIG_DBG_PMEG_CNIG_PORT_MODE_BB                                                             0x2182a0UL //Access:R    DataWidth:0x3    // 
+#define CNIG_REG_DBG_OUT_FRAME_K2_E5                                                                         0x2182a4UL //Access:R    DataWidth:0x4    // Dbgmux output frame
+#define CNIG_REG_CNIG_DBG_PMFC_CNIG_PORT_MODE_BB                                                             0x2182a4UL //Access:R    DataWidth:0x4    // 
+#define CNIG_REG_CNIG_DBG_PMEG_CNIG_TSFIFO_NOT_EMPTY_BB                                                      0x2182a8UL //Access:R    DataWidth:0x4    // 
+#define CNIG_REG_CNIG_DBG_PMFC_CNIG_TSFIFO_NOT_EMPTY_BB                                                      0x2182acUL //Access:R    DataWidth:0x4    // 
+#define CNIG_REG_CNIG_DBG_PMEG_CNIG_TS_BB                                                                    0x2182b0UL //Access:R    DataWidth:0x20   // 
+#define CNIG_REG_CNIG_DBG_PMFC_CNIG_TS_BB                                                                    0x2182b4UL //Access:R    DataWidth:0x20   // 
+#define CNIG_REG_CNIG_DBG_PMEG_LINK_STATUS_BB                                                                0x2182b8UL //Access:R    DataWidth:0x4    // 
+#define CNIG_REG_CNIG_DBG_PMFC_LINK_STATUS_BB                                                                0x2182bcUL //Access:R    DataWidth:0x4    // 
+#define CNIG_REG_CNIG_DBG_PMEG_STATUS_BB                                                                     0x2182c0UL //Access:R    DataWidth:0xc    // Multi Field Register.
+  #define CNIG_REG_CNIG_DBG_PMEG_STATUS_PMEG_LANE0_STATUS_BB                                                 (0x7<<0) // 
+  #define CNIG_REG_CNIG_DBG_PMEG_STATUS_PMEG_LANE0_STATUS_BB_SHIFT                                           0
+  #define CNIG_REG_CNIG_DBG_PMEG_STATUS_PMEG_LANE1_STATUS_BB                                                 (0x7<<3) // 
+  #define CNIG_REG_CNIG_DBG_PMEG_STATUS_PMEG_LANE1_STATUS_BB_SHIFT                                           3
+  #define CNIG_REG_CNIG_DBG_PMEG_STATUS_PMEG_LANE2_STATUS_BB                                                 (0x7<<6) // 
+  #define CNIG_REG_CNIG_DBG_PMEG_STATUS_PMEG_LANE2_STATUS_BB_SHIFT                                           6
+  #define CNIG_REG_CNIG_DBG_PMEG_STATUS_PMEG_LANE3_STATUS_BB                                                 (0x7<<9) // 
+  #define CNIG_REG_CNIG_DBG_PMEG_STATUS_PMEG_LANE3_STATUS_BB_SHIFT                                           9
+#define CNIG_REG_CNIG_DBG_PMFC_STATUS_BB                                                                     0x2182c4UL //Access:R    DataWidth:0xc    // Multi Field Register.
+  #define CNIG_REG_CNIG_DBG_PMFC_STATUS_PMFC_LANE0_STATUS_BB                                                 (0x7<<0) // 
+  #define CNIG_REG_CNIG_DBG_PMFC_STATUS_PMFC_LANE0_STATUS_BB_SHIFT                                           0
+  #define CNIG_REG_CNIG_DBG_PMFC_STATUS_PMFC_LANE1_STATUS_BB                                                 (0x7<<3) // 
+  #define CNIG_REG_CNIG_DBG_PMFC_STATUS_PMFC_LANE1_STATUS_BB_SHIFT                                           3
+  #define CNIG_REG_CNIG_DBG_PMFC_STATUS_PMFC_LANE2_STATUS_BB                                                 (0x7<<6) // 
+  #define CNIG_REG_CNIG_DBG_PMFC_STATUS_PMFC_LANE2_STATUS_BB_SHIFT                                           6
+  #define CNIG_REG_CNIG_DBG_PMFC_STATUS_PMFC_LANE3_STATUS_BB                                                 (0x7<<9) // 
+  #define CNIG_REG_CNIG_DBG_PMFC_STATUS_PMFC_LANE3_STATUS_BB_SHIFT                                           9
+#define CNIG_REG_CNIG_DBG_PMEG_EXT_LPI_INDICATE_BB                                                           0x2182c8UL //Access:R    DataWidth:0x4    // 
+#define CNIG_REG_CNIG_DBG_PMEG_EXT_LPI_DETECT_BB                                                             0x2182ccUL //Access:R    DataWidth:0x4    // 
+#define CNIG_REG_CNIG_DBG_PMFC_EXT_LPI_INDICATE_BB                                                           0x2182d0UL //Access:R    DataWidth:0x4    // 
+#define CNIG_REG_CNIG_DBG_PMFC_EXT_LPI_DETECT_BB                                                             0x2182d4UL //Access:R    DataWidth:0x4    // 
+#define CNIG_REG_CNIG_DBG_PMEG_RX_FAULT_BB                                                                   0x2182d8UL //Access:R    DataWidth:0xc    // Multi Field Register.
+  #define CNIG_REG_CNIG_DBG_PMEG_RX_FAULT_PMEG_RX_LINK_INTERRUPTION_BB                                       (0xf<<0) // 
+  #define CNIG_REG_CNIG_DBG_PMEG_RX_FAULT_PMEG_RX_LINK_INTERRUPTION_BB_SHIFT                                 0
+  #define CNIG_REG_CNIG_DBG_PMEG_RX_FAULT_PMEG_RX_LOCAL_FAULT_BB                                             (0xf<<4) // 
+  #define CNIG_REG_CNIG_DBG_PMEG_RX_FAULT_PMEG_RX_LOCAL_FAULT_BB_SHIFT                                       4
+  #define CNIG_REG_CNIG_DBG_PMEG_RX_FAULT_PMEG_RX_REMOTE_FAULT_BB                                            (0xf<<8) // 
+  #define CNIG_REG_CNIG_DBG_PMEG_RX_FAULT_PMEG_RX_REMOTE_FAULT_BB_SHIFT                                      8
+#define CNIG_REG_CNIG_DBG_PMFC_RX_FAULT_BB                                                                   0x2182dcUL //Access:R    DataWidth:0xc    // Multi Field Register.
+  #define CNIG_REG_CNIG_DBG_PMFC_RX_FAULT_PMFC_RX_LINK_INTERRUPTION_BB                                       (0xf<<0) // 
+  #define CNIG_REG_CNIG_DBG_PMFC_RX_FAULT_PMFC_RX_LINK_INTERRUPTION_BB_SHIFT                                 0
+  #define CNIG_REG_CNIG_DBG_PMFC_RX_FAULT_PMFC_RX_LOCAL_FAULT_BB                                             (0xf<<4) // 
+  #define CNIG_REG_CNIG_DBG_PMFC_RX_FAULT_PMFC_RX_LOCAL_FAULT_BB_SHIFT                                       4
+  #define CNIG_REG_CNIG_DBG_PMFC_RX_FAULT_PMFC_RX_REMOTE_FAULT_BB                                            (0xf<<8) // 
+  #define CNIG_REG_CNIG_DBG_PMFC_RX_FAULT_PMFC_RX_REMOTE_FAULT_BB_SHIFT                                      8
+#define CNIG_REG_CNIG_DBG_IFMUX_SIGDET_BB                                                                    0x2182e0UL //Access:R    DataWidth:0x4    // 
+#define CNIG_REG_CNIG_DBG_IFMUX_PHY_LASI_B_BB                                                                0x2182e4UL //Access:R    DataWidth:0x4    // 
+#define CNIG_REG_CNIG_DBG_NIGTX_FIFO_AFULL_THRESH_LARGE_BB                                                   0x2182f8UL //Access:RW   DataWidth:0x4    // This register controls the almost full indication of TX FIFO of port 0 and 2. Note: the register value represent the number of FIFO entries before almost full indication is transferred to NIG.
+#define CNIG_REG_PMEG_TX_CREDITS_BB                                                                          0x218300UL //Access:RW   DataWidth:0x6    // Per Eagle port credit RD/WR: Writing to this register will initialize the port's credit with the written value. Reading from this register will return the port's current credit value.
+#define CNIG_REG_PMEG_TX_CREDITS_SIZE                                                                        4
+#define CNIG_REG_PMFC_TX_CREDITS_BB                                                                          0x218310UL //Access:RW   DataWidth:0x6    // Per Falcon port credit RD/WR: Writing to this register will initialize the port's credit with the written value. Reading from this register will return the port's current credit value.
+#define CNIG_REG_PMFC_TX_CREDITS_SIZE                                                                        4
+#define CNIG_REG_PMEG_SIGN_EXT_BB                                                                            0x218320UL //Access:RW   DataWidth:0x1    // This register is used to set the value of cnig_pmeg_sign_ext output signal.
+#define CNIG_REG_PMFC_SIGN_EXT_BB                                                                            0x218324UL //Access:RW   DataWidth:0x1    // This register is used to set the value of cnig_pmfc_sign_ext output signal.
+#define CNIG_REG_PMFC_LPI_DEFUALT_VALUE_BB                                                                   0x218328UL //Access:RW   DataWidth:0x1    // This register is used to set the value of PMFC lpi_indicate default value. The lpi value will be overwriten by cpmu vlaue accordigly to the Port Macro NIG mapping.
+#define CNIG_REG_PMEG_LPI_DEFUALT_VALUE_BB                                                                   0x21832cUL //Access:RW   DataWidth:0x1    // This register is used to set the value of PMEG lpi_indicate default value. The lpi value will be overwriten by cpmu vlaue accordigly to the Port Macro NIG mapping.
+#define CNIG_REG_PMEG_TS_RESET_N_BB                                                                          0x218330UL //Access:RW   DataWidth:0x1    // PMEG timestamp local counter reset. If = 0, the timers is reset. If = 1, the timer is out of reset.
+#define CNIG_REG_PMFC_TS_RESET_N_BB                                                                          0x218334UL //Access:RW   DataWidth:0x1    // PMFC timestamp local counter reset. If = 0, the timers is reset. If = 1, the timer is out of reset.
+#define CNIG_REG_PMFC_CRC_RX_EN_BB                                                                           0x218338UL //Access:RW   DataWidth:0x2    // This register controls the option for calculating CRC in CNIG RX datapath, remove CRC field from packet and assert Error indication accordingly to CRC correctness. Note: this mode can be active only for PMFC ports 0,2 and should be used for 100G or 2x50G NW modes. Bit 0 - port0 CRC enable. Bit 1 - port2 CRC enable.
+#define CNIG_REG_PMFC_CRC_TX_EN_BB                                                                           0x21833cUL //Access:RW   DataWidth:0x2    // This register controls the option for calculating CRC in CNIG TX datapath, and append  CRC field at the end of the packet. Note: this mode can be active only for PMFC ports 0,2 and should be used for 100G or 2x50G NW modes. Bit 0 - port0 CRC enable. Bit 1 - port2 CRC enable.
+#define CNIG_REG_PMFC_CRC_TX_CORRUPT_EN_BB                                                                   0x218340UL //Access:RW   DataWidth:0x2    // This register controls the option for corrupting the calculated CRC value in TX path when Parity or error  indication is received from NIG. Note: a. This mode can be active only for PMFC ports 0,2 and should be used for 100G or 2x50G NW modes. b. As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration. Bit 0 - port0 CRC corrupt enable. Bit 1 - port2 CRC corrupte enable.
+#define CNIG_REG_PMFC_CRC_TX_CORRUPT_ON_ERROR_BB                                                             0x218344UL //Access:RW   DataWidth:0x2    // This register controls the option for corrupting the calculated CRC value in TX path when error indication is received from NIG. Note: a. This mode can be active only for PMFC ports 0,2 and should be used for 100G or 2x50G NW modes. b. As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration. Bit 0 - port0 CRC corrupt enable. Bit 1 - port2 CRC corrupte enable.
+#define PRM_REG_DISABLE_PRM                                                                                  0x230000UL //Access:RW   DataWidth:0x1    // Used to disable the PRM from processing any new commands.
+#define PRM_REG_BRB_DATA_IN_EN                                                                               0x230004UL //Access:RW   DataWidth:0x1    // Enables data to be received on the BRB data interface.
+#define PRM_REG_BRB_FULL_OUT_EN                                                                              0x230008UL //Access:RW   DataWidth:0x1    // Enables the BRB full output to be asserted by the PRM.
+#define PRM_REG_PXP_ACK_IN_EN                                                                                0x23000cUL //Access:RW   DataWidth:0x1    // Enables the PXP request acknowledge to be received by the PRM.
+#define PRM_REG_DISABLE_INPUTS                                                                               0x230010UL //Access:RW   DataWidth:0x1    // Used to disable all PRM block inputs for test purposes.
+#define PRM_REG_DISABLE_OUTPUTS                                                                              0x230014UL //Access:RW   DataWidth:0x1    // Used to disable all PRM block outputs for test purposes.
+#define PRM_REG_INT_STS                                                                                      0x230040UL //Access:R    DataWidth:0xb    // Multi Field Register.
+  #define PRM_REG_INT_STS_ADDRESS_ERROR                                                                      (0x1<<0) // Signals an unknown address to the rf module.
+  #define PRM_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                                0
+  #define PRM_REG_INT_STS_IFIFO_ERROR                                                                        (0x1<<1) // Overrun/underrun error for the BRB input FIFO.
+  #define PRM_REG_INT_STS_IFIFO_ERROR_SHIFT                                                                  1
+  #define PRM_REG_INT_STS_IMMED_FIFO_ERROR                                                                   (0x1<<2) // Overrun/underrun error for the immediate FIFO.
+  #define PRM_REG_INT_STS_IMMED_FIFO_ERROR_SHIFT                                                             2
+  #define PRM_REG_INT_STS_OFST_PEND_ERROR                                                                    (0x1<<3) // Overrun/underrun error for BRB offset pending FIFO.
+  #define PRM_REG_INT_STS_OFST_PEND_ERROR_SHIFT                                                              3
+  #define PRM_REG_INT_STS_PAD_PEND_ERROR                                                                     (0x1<<4) // Overrun/underrun error for pad pending FIFO.
+  #define PRM_REG_INT_STS_PAD_PEND_ERROR_SHIFT                                                               4
+  #define PRM_REG_INT_STS_PBINP_PEND_ERROR                                                                   (0x1<<5) // Overrun/underrun error for PB input pending FIFO.
+  #define PRM_REG_INT_STS_PBINP_PEND_ERROR_SHIFT                                                             5
+  #define PRM_REG_INT_STS_TAG_PEND_ERROR                                                                     (0x1<<6) // Overrun/underrun error for tag pending FIFO.
+  #define PRM_REG_INT_STS_TAG_PEND_ERROR_SHIFT                                                               6
+  #define PRM_REG_INT_STS_MSTORM_EOP_ERR                                                                     (0x1<<7) // End of packet error on M-Storm command interface.
+  #define PRM_REG_INT_STS_MSTORM_EOP_ERR_SHIFT                                                               7
+  #define PRM_REG_INT_STS_USTORM_EOP_ERR                                                                     (0x1<<8) // End of packet error on U-Storm command interface.
+  #define PRM_REG_INT_STS_USTORM_EOP_ERR_SHIFT                                                               8
+  #define PRM_REG_INT_STS_MSTORM_QUE_ERR                                                                     (0x1<<9) // FIFO overflow/underflow error on M-Storm command interface.
+  #define PRM_REG_INT_STS_MSTORM_QUE_ERR_SHIFT                                                               9
+  #define PRM_REG_INT_STS_USTORM_QUE_ERR                                                                     (0x1<<10) // FIFO overflow/underflow error on U-Storm command interface.
+  #define PRM_REG_INT_STS_USTORM_QUE_ERR_SHIFT                                                               10
+#define PRM_REG_INT_MASK                                                                                     0x230044UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define PRM_REG_INT_MASK_ADDRESS_ERROR                                                                     (0x1<<0) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.ADDRESS_ERROR .
+  #define PRM_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                               0
+  #define PRM_REG_INT_MASK_IFIFO_ERROR                                                                       (0x1<<1) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.IFIFO_ERROR .
+  #define PRM_REG_INT_MASK_IFIFO_ERROR_SHIFT                                                                 1
+  #define PRM_REG_INT_MASK_IMMED_FIFO_ERROR                                                                  (0x1<<2) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.IMMED_FIFO_ERROR .
+  #define PRM_REG_INT_MASK_IMMED_FIFO_ERROR_SHIFT                                                            2
+  #define PRM_REG_INT_MASK_OFST_PEND_ERROR                                                                   (0x1<<3) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.OFST_PEND_ERROR .
+  #define PRM_REG_INT_MASK_OFST_PEND_ERROR_SHIFT                                                             3
+  #define PRM_REG_INT_MASK_PAD_PEND_ERROR                                                                    (0x1<<4) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.PAD_PEND_ERROR .
+  #define PRM_REG_INT_MASK_PAD_PEND_ERROR_SHIFT                                                              4
+  #define PRM_REG_INT_MASK_PBINP_PEND_ERROR                                                                  (0x1<<5) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.PBINP_PEND_ERROR .
+  #define PRM_REG_INT_MASK_PBINP_PEND_ERROR_SHIFT                                                            5
+  #define PRM_REG_INT_MASK_TAG_PEND_ERROR                                                                    (0x1<<6) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.TAG_PEND_ERROR .
+  #define PRM_REG_INT_MASK_TAG_PEND_ERROR_SHIFT                                                              6
+  #define PRM_REG_INT_MASK_MSTORM_EOP_ERR                                                                    (0x1<<7) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.MSTORM_EOP_ERR .
+  #define PRM_REG_INT_MASK_MSTORM_EOP_ERR_SHIFT                                                              7
+  #define PRM_REG_INT_MASK_USTORM_EOP_ERR                                                                    (0x1<<8) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.USTORM_EOP_ERR .
+  #define PRM_REG_INT_MASK_USTORM_EOP_ERR_SHIFT                                                              8
+  #define PRM_REG_INT_MASK_MSTORM_QUE_ERR                                                                    (0x1<<9) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.MSTORM_QUE_ERR .
+  #define PRM_REG_INT_MASK_MSTORM_QUE_ERR_SHIFT                                                              9
+  #define PRM_REG_INT_MASK_USTORM_QUE_ERR                                                                    (0x1<<10) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.USTORM_QUE_ERR .
+  #define PRM_REG_INT_MASK_USTORM_QUE_ERR_SHIFT                                                              10
+#define PRM_REG_INT_STS_WR                                                                                   0x230048UL //Access:WR   DataWidth:0xb    // Multi Field Register.
+  #define PRM_REG_INT_STS_WR_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define PRM_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                             0
+  #define PRM_REG_INT_STS_WR_IFIFO_ERROR                                                                     (0x1<<1) // Overrun/underrun error for the BRB input FIFO.
+  #define PRM_REG_INT_STS_WR_IFIFO_ERROR_SHIFT                                                               1
+  #define PRM_REG_INT_STS_WR_IMMED_FIFO_ERROR                                                                (0x1<<2) // Overrun/underrun error for the immediate FIFO.
+  #define PRM_REG_INT_STS_WR_IMMED_FIFO_ERROR_SHIFT                                                          2
+  #define PRM_REG_INT_STS_WR_OFST_PEND_ERROR                                                                 (0x1<<3) // Overrun/underrun error for BRB offset pending FIFO.
+  #define PRM_REG_INT_STS_WR_OFST_PEND_ERROR_SHIFT                                                           3
+  #define PRM_REG_INT_STS_WR_PAD_PEND_ERROR                                                                  (0x1<<4) // Overrun/underrun error for pad pending FIFO.
+  #define PRM_REG_INT_STS_WR_PAD_PEND_ERROR_SHIFT                                                            4
+  #define PRM_REG_INT_STS_WR_PBINP_PEND_ERROR                                                                (0x1<<5) // Overrun/underrun error for PB input pending FIFO.
+  #define PRM_REG_INT_STS_WR_PBINP_PEND_ERROR_SHIFT                                                          5
+  #define PRM_REG_INT_STS_WR_TAG_PEND_ERROR                                                                  (0x1<<6) // Overrun/underrun error for tag pending FIFO.
+  #define PRM_REG_INT_STS_WR_TAG_PEND_ERROR_SHIFT                                                            6
+  #define PRM_REG_INT_STS_WR_MSTORM_EOP_ERR                                                                  (0x1<<7) // End of packet error on M-Storm command interface.
+  #define PRM_REG_INT_STS_WR_MSTORM_EOP_ERR_SHIFT                                                            7
+  #define PRM_REG_INT_STS_WR_USTORM_EOP_ERR                                                                  (0x1<<8) // End of packet error on U-Storm command interface.
+  #define PRM_REG_INT_STS_WR_USTORM_EOP_ERR_SHIFT                                                            8
+  #define PRM_REG_INT_STS_WR_MSTORM_QUE_ERR                                                                  (0x1<<9) // FIFO overflow/underflow error on M-Storm command interface.
+  #define PRM_REG_INT_STS_WR_MSTORM_QUE_ERR_SHIFT                                                            9
+  #define PRM_REG_INT_STS_WR_USTORM_QUE_ERR                                                                  (0x1<<10) // FIFO overflow/underflow error on U-Storm command interface.
+  #define PRM_REG_INT_STS_WR_USTORM_QUE_ERR_SHIFT                                                            10
+#define PRM_REG_INT_STS_CLR                                                                                  0x23004cUL //Access:RC   DataWidth:0xb    // Multi Field Register.
+  #define PRM_REG_INT_STS_CLR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define PRM_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                            0
+  #define PRM_REG_INT_STS_CLR_IFIFO_ERROR                                                                    (0x1<<1) // Overrun/underrun error for the BRB input FIFO.
+  #define PRM_REG_INT_STS_CLR_IFIFO_ERROR_SHIFT                                                              1
+  #define PRM_REG_INT_STS_CLR_IMMED_FIFO_ERROR                                                               (0x1<<2) // Overrun/underrun error for the immediate FIFO.
+  #define PRM_REG_INT_STS_CLR_IMMED_FIFO_ERROR_SHIFT                                                         2
+  #define PRM_REG_INT_STS_CLR_OFST_PEND_ERROR                                                                (0x1<<3) // Overrun/underrun error for BRB offset pending FIFO.
+  #define PRM_REG_INT_STS_CLR_OFST_PEND_ERROR_SHIFT                                                          3
+  #define PRM_REG_INT_STS_CLR_PAD_PEND_ERROR                                                                 (0x1<<4) // Overrun/underrun error for pad pending FIFO.
+  #define PRM_REG_INT_STS_CLR_PAD_PEND_ERROR_SHIFT                                                           4
+  #define PRM_REG_INT_STS_CLR_PBINP_PEND_ERROR                                                               (0x1<<5) // Overrun/underrun error for PB input pending FIFO.
+  #define PRM_REG_INT_STS_CLR_PBINP_PEND_ERROR_SHIFT                                                         5
+  #define PRM_REG_INT_STS_CLR_TAG_PEND_ERROR                                                                 (0x1<<6) // Overrun/underrun error for tag pending FIFO.
+  #define PRM_REG_INT_STS_CLR_TAG_PEND_ERROR_SHIFT                                                           6
+  #define PRM_REG_INT_STS_CLR_MSTORM_EOP_ERR                                                                 (0x1<<7) // End of packet error on M-Storm command interface.
+  #define PRM_REG_INT_STS_CLR_MSTORM_EOP_ERR_SHIFT                                                           7
+  #define PRM_REG_INT_STS_CLR_USTORM_EOP_ERR                                                                 (0x1<<8) // End of packet error on U-Storm command interface.
+  #define PRM_REG_INT_STS_CLR_USTORM_EOP_ERR_SHIFT                                                           8
+  #define PRM_REG_INT_STS_CLR_MSTORM_QUE_ERR                                                                 (0x1<<9) // FIFO overflow/underflow error on M-Storm command interface.
+  #define PRM_REG_INT_STS_CLR_MSTORM_QUE_ERR_SHIFT                                                           9
+  #define PRM_REG_INT_STS_CLR_USTORM_QUE_ERR                                                                 (0x1<<10) // FIFO overflow/underflow error on U-Storm command interface.
+  #define PRM_REG_INT_STS_CLR_USTORM_QUE_ERR_SHIFT                                                           10
+#define PRM_REG_PRTY_MASK                                                                                    0x230054UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define PRM_REG_PRTY_MASK_DATAPATH_REGISTERS                                                               (0x1<<0) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS.DATAPATH_REGISTERS .
+  #define PRM_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                                         0
+#define PRM_REG_PRTY_MASK_H_0_BB_K2                                                                          0x230204UL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define PRM_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_K2                                                       (0x1<<0) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM012_I_ECC_RF_INT .
+  #define PRM_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_K2_SHIFT                                                 0
+  #define PRM_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT_BB                                                       (0x1<<0) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM013_I_ECC_RF_INT .
+  #define PRM_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT_BB_SHIFT                                                 0
+  #define PRM_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT_K2                                                       (0x1<<1) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM013_I_ECC_RF_INT .
+  #define PRM_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT_K2_SHIFT                                                 1
+  #define PRM_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_BB                                                       (0x1<<1) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM014_I_ECC_RF_INT .
+  #define PRM_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_BB_SHIFT                                                 1
+  #define PRM_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_K2                                                       (0x1<<2) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM014_I_ECC_RF_INT .
+  #define PRM_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_K2_SHIFT                                                 2
+  #define PRM_REG_PRTY_MASK_H_0_MEM020_I_ECC_RF_INT_K2                                                       (0x1<<3) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM020_I_ECC_RF_INT .
+  #define PRM_REG_PRTY_MASK_H_0_MEM020_I_ECC_RF_INT_K2_SHIFT                                                 3
+  #define PRM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB                                                         (0x1<<13) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_SHIFT                                                   13
+  #define PRM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2                                                         (0x1<<4) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_SHIFT                                                   4
+  #define PRM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB                                                         (0x1<<16) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB_SHIFT                                                   16
+  #define PRM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2                                                         (0x1<<5) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2_SHIFT                                                   5
+  #define PRM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB                                                         (0x1<<11) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_SHIFT                                                   11
+  #define PRM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2                                                         (0x1<<6) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2_SHIFT                                                   6
+  #define PRM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB                                                         (0x1<<6) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_SHIFT                                                   6
+  #define PRM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2                                                         (0x1<<7) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_SHIFT                                                   7
+  #define PRM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB                                                         (0x1<<18) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_SHIFT                                                   18
+  #define PRM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2                                                         (0x1<<8) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_SHIFT                                                   8
+  #define PRM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB                                                         (0x1<<8) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_SHIFT                                                   8
+  #define PRM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2                                                         (0x1<<9) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2_SHIFT                                                   9
+  #define PRM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB                                                         (0x1<<9) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_SHIFT                                                   9
+  #define PRM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2                                                         (0x1<<10) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2_SHIFT                                                   10
+  #define PRM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2                                                         (0x1<<11) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2_SHIFT                                                   11
+  #define PRM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB                                                         (0x1<<10) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_SHIFT                                                   10
+  #define PRM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2                                                         (0x1<<12) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2_SHIFT                                                   12
+  #define PRM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB                                                         (0x1<<14) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_SHIFT                                                   14
+  #define PRM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2                                                         (0x1<<13) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_SHIFT                                                   13
+  #define PRM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB                                                         (0x1<<20) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_SHIFT                                                   20
+  #define PRM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2                                                         (0x1<<14) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_SHIFT                                                   14
+  #define PRM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB                                                         (0x1<<4) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_SHIFT                                                   4
+  #define PRM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2                                                         (0x1<<15) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2_SHIFT                                                   15
+  #define PRM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB                                                         (0x1<<21) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_SHIFT                                                   21
+  #define PRM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2                                                         (0x1<<16) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2_SHIFT                                                   16
+  #define PRM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB                                                         (0x1<<15) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_SHIFT                                                   15
+  #define PRM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2                                                         (0x1<<17) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_SHIFT                                                   17
+  #define PRM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB                                                         (0x1<<17) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_SHIFT                                                   17
+  #define PRM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2                                                         (0x1<<18) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_SHIFT                                                   18
+  #define PRM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                      (0x1<<19) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                                19
+  #define PRM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB                                                         (0x1<<22) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_SHIFT                                                   22
+  #define PRM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_K2                                                         (0x1<<20) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_K2_SHIFT                                                   20
+  #define PRM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2                                                         (0x1<<21) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2_SHIFT                                                   21
+  #define PRM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2                                                         (0x1<<22) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_SHIFT                                                   22
+  #define PRM_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_BB                                                       (0x1<<2) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM015_I_ECC_RF_INT .
+  #define PRM_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_BB_SHIFT                                                 2
+  #define PRM_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT_BB                                                       (0x1<<3) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM021_I_ECC_RF_INT .
+  #define PRM_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT_BB_SHIFT                                                 3
+  #define PRM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB                                                         (0x1<<5) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB_SHIFT                                                   5
+  #define PRM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB                                                         (0x1<<7) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_SHIFT                                                   7
+  #define PRM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB                                                         (0x1<<12) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_SHIFT                                                   12
+  #define PRM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB                                                         (0x1<<23) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
+  #define PRM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_SHIFT                                                   23
+#define PRM_REG_MEM012_RF_ECC_ERROR_CONNECT_K2                                                               0x230210UL //Access:W    DataWidth:0x10   // Register to generate up to two ECC errors on the next write to memory: prm.i_prm_dp.i_rdif.i_rdif_l1_sector0_mem.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define PRM_REG_MEM013_RF_ECC_ERROR_CONNECT_BB                                                               0x230210UL //Access:W    DataWidth:0x10   // Register to generate up to two ECC errors on the next write to memory: prm.i_prm_dp.i_rdif.i_rdif_l1_sector0_mem.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define PRM_REG_MEM013_RF_ECC_ERROR_CONNECT_K2                                                               0x230214UL //Access:W    DataWidth:0x10   // Register to generate up to two ECC errors on the next write to memory: prm.i_prm_dp.i_rdif.i_rdif_l1_sector1_mem.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define PRM_REG_MEM014_RF_ECC_ERROR_CONNECT_BB                                                               0x230214UL //Access:W    DataWidth:0x10   // Register to generate up to two ECC errors on the next write to memory: prm.i_prm_dp.i_rdif.i_rdif_l1_sector1_mem.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define PRM_REG_MEM014_RF_ECC_ERROR_CONNECT_K2                                                               0x230218UL //Access:W    DataWidth:0x10   // Register to generate up to two ECC errors on the next write to memory: prm.i_prm_dp.i_rdif.i_rdif_l1_sector2_mem.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define PRM_REG_MEM015_RF_ECC_ERROR_CONNECT_BB                                                               0x230218UL //Access:W    DataWidth:0x10   // Register to generate up to two ECC errors on the next write to memory: prm.i_prm_dp.i_rdif.i_rdif_l1_sector2_mem.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define PRM_REG_MEM_ECC_ENABLE_0_BB_K2                                                                       0x23021cUL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define PRM_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN_K2                                                        (0x1<<0) // Enable ECC for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector0_mem.i_ecc in module rdif_l1_sector0_mem
+  #define PRM_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN_K2_SHIFT                                                  0
+  #define PRM_REG_MEM_ECC_ENABLE_0_MEM013_I_ECC_EN_BB                                                        (0x1<<0) // Enable ECC for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector0_mem.i_ecc in module rdif_l1_sector0_mem
+  #define PRM_REG_MEM_ECC_ENABLE_0_MEM013_I_ECC_EN_BB_SHIFT                                                  0
+  #define PRM_REG_MEM_ECC_ENABLE_0_MEM013_I_ECC_EN_K2                                                        (0x1<<1) // Enable ECC for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector1_mem.i_ecc in module rdif_l1_sector1_mem
+  #define PRM_REG_MEM_ECC_ENABLE_0_MEM013_I_ECC_EN_K2_SHIFT                                                  1
+  #define PRM_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN_BB                                                        (0x1<<1) // Enable ECC for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector1_mem.i_ecc in module rdif_l1_sector1_mem
+  #define PRM_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN_BB_SHIFT                                                  1
+  #define PRM_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN_K2                                                        (0x1<<2) // Enable ECC for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector2_mem.i_ecc in module rdif_l1_sector2_mem
+  #define PRM_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN_K2_SHIFT                                                  2
+  #define PRM_REG_MEM_ECC_ENABLE_0_MEM020_I_ECC_EN_K2                                                        (0x1<<3) // Enable ECC for memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram
+  #define PRM_REG_MEM_ECC_ENABLE_0_MEM020_I_ECC_EN_K2_SHIFT                                                  3
+  #define PRM_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN_BB                                                        (0x1<<2) // Enable ECC for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector2_mem.i_ecc in module rdif_l1_sector2_mem
+  #define PRM_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN_BB_SHIFT                                                  2
+  #define PRM_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_EN_BB                                                        (0x1<<3) // Enable ECC for memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram
+  #define PRM_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_EN_BB_SHIFT                                                  3
+#define PRM_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                  0x230220UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY_K2                                                 (0x1<<0) // Set parity only for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector0_mem.i_ecc in module rdif_l1_sector0_mem
+  #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY_K2_SHIFT                                           0
+  #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM013_I_ECC_PRTY_BB                                                 (0x1<<0) // Set parity only for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector0_mem.i_ecc in module rdif_l1_sector0_mem
+  #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM013_I_ECC_PRTY_BB_SHIFT                                           0
+  #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM013_I_ECC_PRTY_K2                                                 (0x1<<1) // Set parity only for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector1_mem.i_ecc in module rdif_l1_sector1_mem
+  #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM013_I_ECC_PRTY_K2_SHIFT                                           1
+  #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY_BB                                                 (0x1<<1) // Set parity only for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector1_mem.i_ecc in module rdif_l1_sector1_mem
+  #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY_BB_SHIFT                                           1
+  #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY_K2                                                 (0x1<<2) // Set parity only for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector2_mem.i_ecc in module rdif_l1_sector2_mem
+  #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY_K2_SHIFT                                           2
+  #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM020_I_ECC_PRTY_K2                                                 (0x1<<3) // Set parity only for memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram
+  #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM020_I_ECC_PRTY_K2_SHIFT                                           3
+  #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY_BB                                                 (0x1<<2) // Set parity only for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector2_mem.i_ecc in module rdif_l1_sector2_mem
+  #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY_BB_SHIFT                                           2
+  #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_PRTY_BB                                                 (0x1<<3) // Set parity only for memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram
+  #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_PRTY_BB_SHIFT                                           3
+#define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                              0x230224UL //Access:RC   DataWidth:0x4    // Multi Field Register.
+  #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT_K2                                          (0x1<<0) // Record if a correctable error occurred on memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector0_mem.i_ecc in module rdif_l1_sector0_mem
+  #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT_K2_SHIFT                                    0
+  #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM013_I_ECC_CORRECT_BB                                          (0x1<<0) // Record if a correctable error occurred on memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector0_mem.i_ecc in module rdif_l1_sector0_mem
+  #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM013_I_ECC_CORRECT_BB_SHIFT                                    0
+  #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM013_I_ECC_CORRECT_K2                                          (0x1<<1) // Record if a correctable error occurred on memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector1_mem.i_ecc in module rdif_l1_sector1_mem
+  #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM013_I_ECC_CORRECT_K2_SHIFT                                    1
+  #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT_BB                                          (0x1<<1) // Record if a correctable error occurred on memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector1_mem.i_ecc in module rdif_l1_sector1_mem
+  #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT_BB_SHIFT                                    1
+  #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT_K2                                          (0x1<<2) // Record if a correctable error occurred on memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector2_mem.i_ecc in module rdif_l1_sector2_mem
+  #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT_K2_SHIFT                                    2
+  #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM020_I_ECC_CORRECT_K2                                          (0x1<<3) // Record if a correctable error occurred on memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram
+  #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM020_I_ECC_CORRECT_K2_SHIFT                                    3
+  #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT_BB                                          (0x1<<2) // Record if a correctable error occurred on memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector2_mem.i_ecc in module rdif_l1_sector2_mem
+  #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT_BB_SHIFT                                    2
+  #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_CORRECT_BB                                          (0x1<<3) // Record if a correctable error occurred on memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram
+  #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_CORRECT_BB_SHIFT                                    3
+#define PRM_REG_MEM_ECC_EVENTS_BB_K2                                                                         0x230228UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define PRM_REG_TAG_SZ                                                                                       0x230400UL //Access:RW   DataWidth:0x4    // Array of registers provides a size (in units of two bytes) for each of the possible seven configurable L2 tags to remove, where the direct register index corresponds with the tag ID. The actual value to remove in bytes will be defined by the following: size (bytes) = (tag_sz+1)*2. Note: there is no tag_sz register for tag ID = 0x7 because this is the LLC/Snap tag ID and is not configurable.
+#define PRM_REG_TAG_SZ_SIZE                                                                                  7
+#define PRM_REG_PAD_DATA                                                                                     0x230420UL //Access:RW   DataWidth:0x10   // Provides the value of the 16-bit pad that will be inserted into the PXP data stream when pad insertion is enabled.
+#define PRM_REG_PAD_FROM_DBG                                                                                 0x230424UL //Access:RW   DataWidth:0x1    // When set, this bit enables the pad insertion logic to use BRB debug field from the PRM command to define the value of the inserted pad; otherwise the pad_data configuration is used.
+#define PRM_REG_INIT_CREDIT_PXP                                                                              0x230428UL //Access:RW   DataWidth:0x3    // Initial credit to be used on the PXP request interface. This value defines the maximum number of outstanding requests allowed.
+#define PRM_REG_INIT_CREDIT_RDIF_CMD                                                                         0x23042cUL //Access:RW   DataWidth:0x4    // Initial credit to be used on the RDIF command interface for regular (non-pass-through) requests. This value defines the maximum number of outstanding regular commands allowed.
+#define PRM_REG_INIT_CREDIT_RDIF_PTH                                                                         0x230430UL //Access:RW   DataWidth:0x6    // Initial credit to be used on the RDIF command interface for pass-through requests. This value defines the maximum number of outstanding pass-through commands allowed.
+#define PRM_REG_RPB_DB_FULL_THR                                                                              0x230500UL //Access:RW   DataWidth:0x6    // Defines the number of occupied entries required in the RPB data buffer before the full signal will be asserted.
+#define PRM_REG_RPB_TQ_FULL_THR                                                                              0x230504UL //Access:RW   DataWidth:0x7    // Defines the number of occupied entries required in the RPB task queue before the full signal will be asserted.
+#define PRM_REG_IFIFO_FULL_THR                                                                               0x230508UL //Access:RW   DataWidth:0x5    // Defines the number of occupied entries required in the BRB input FIFO before the full signal will be asserted.
+#define PRM_REG_ECO_RESERVED                                                                                 0x23050cUL //Access:RW   DataWidth:0x20   // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
+#define PRM_REG_PXP_RESP_FULL_THR                                                                            0x230510UL //Access:RW   DataWidth:0x6    // Defines the number of occupied entries required in the PXP read-response FIFO before the full signal will be asserted.
+#define PRM_REG_NUM_OF_MSTORM_CMD                                                                            0x230600UL //Access:RC   DataWidth:0x18   // Statistics counter provides a count of the number of M-Storm comands that have been received by the PRM.
+#define PRM_REG_NUM_OF_USTORM_CMD                                                                            0x230604UL //Access:RC   DataWidth:0x18   // Statistics counter provides a count of the number of U-Storm comands that have been received by the PRM.
+#define PRM_REG_DBG_OUT_DATA                                                                                 0x230680UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PRM_REG_DBG_OUT_DATA_SIZE                                                                            8
+#define PRM_REG_DBG_OUT_VALID                                                                                0x2306a0UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define PRM_REG_DBG_OUT_FRAME                                                                                0x2306a4UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define PRM_REG_DBG_SELECT                                                                                   0x2306a8UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PRM_REG_DBG_DWORD_ENABLE                                                                             0x2306acUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PRM_REG_DBG_SHIFT                                                                                    0x2306b0UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PRM_REG_DBG_FORCE_VALID                                                                              0x2306b4UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PRM_REG_DBG_FORCE_FRAME                                                                              0x2306b8UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PRM_REG_MSTORM_CMD_QUE_BB_K2                                                                         0x232000UL //Access:WB_R DataWidth:0x80   // Provides read-only access of the M-Storm command queue. Intended for test/debug purposes.
+#define PRM_REG_MSTORM_CMD_QUE_SIZE                                                                          132
+#define PRM_REG_USTORM_CMD_QUE_BB_K2                                                                         0x232400UL //Access:WB_R DataWidth:0x80   // Provides read-only access of the U-Storm command queue. Intended for test/debug purposes.
+#define PRM_REG_USTORM_CMD_QUE_SIZE                                                                          132
+#define PRM_REG_BRB_INP_FIFO_BB_K2                                                                           0x232800UL //Access:WB_R DataWidth:0x108  // Provides read-only access of the BRB input FIFO. Intended for test/debug purposes.
+#define PRM_REG_BRB_INP_FIFO_SIZE                                                                            144
+#define PRM_REG_OFST_PEND_FIFO_BB_K2                                                                         0x232c00UL //Access:R    DataWidth:0x7    // Provides read-only access of the BRB ofset pending request FIFO. Intended for test/debug purposes.
+#define PRM_REG_OFST_PEND_FIFO_SIZE                                                                          49
+#define PRM_REG_TAG_PEND_FIFO_BB_K2                                                                          0x233000UL //Access:WB_R DataWidth:0x2c   // Provides read-only access of the tag removal pending request FIFO. Intended for test/debug purposes.
+#define PRM_REG_TAG_PEND_FIFO_SIZE                                                                           98
+#define PRM_REG_PAD_PEND_FIFO_BB_K2                                                                          0x233400UL //Access:R    DataWidth:0x11   // Provides read-only access of the pad insertion pending request FIFO. Intended for test/debug purposes.
+#define PRM_REG_PAD_PEND_FIFO_SIZE                                                                           49
+#define PRM_REG_PBINP_PEND_FIFO_BB_K2                                                                        0x233600UL //Access:R    DataWidth:0xb    // Provides read-only access of the PB input pending request FIFO. Intended for test/debug purposes.
+#define PRM_REG_PBINP_PEND_FIFO_SIZE                                                                         49
+#define PRM_REG_IMMED_FIFO_BB_K2                                                                             0x233800UL //Access:WB_R DataWidth:0x100  // Provides read-only access of the PRM immediate data FIFO. Intended for test/debug purposes.
+#define PRM_REG_IMMED_FIFO_SIZE                                                                              72
+#define PRM_REG_WDONE_FIFO_BB_K2                                                                             0x233c00UL //Access:R    DataWidth:0x8    // Provides read-only access of the PXP write-done response FIFO. Intended for test/debug purposes.
+#define PRM_REG_WDONE_FIFO_SIZE                                                                              54
+#define PRM_REG_DIR_MSG_BUF_BB_K2                                                                            0x234000UL //Access:WB   DataWidth:0x80   // Provides read/write access to the PRM completion message queue. Intended for test/debug purposes. When the RBC read is done at the same time of a logic read, the logic will get a wrong value which will cause a wrong message to SDM.
+#define PRM_REG_DIR_MSG_BUF_SIZE                                                                             1272
+#define PRM_REG_NOP_WITHOUT_COMPLETION_FIX_DISABLE_K2_E5                                                     0x236000UL //Access:RW   DataWidth:0x1    // Chicken Bit for the NOP without completion fix
+#define SRC_REG_CTRL                                                                                         0x238040UL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define SRC_REG_CTRL_NUM_CONCURRENT_PROCESSES                                                              (0xff<<0) // Number of Concurrent Processes (State Machines); Values can be 1 to 25.
+  #define SRC_REG_CTRL_NUM_CONCURRENT_PROCESSES_SHIFT                                                        0
+  #define SRC_REG_CTRL_MAXNUMHOPS                                                                            (0xff<<8) // The maximum allowed HOP to search.
+  #define SRC_REG_CTRL_MAXNUMHOPS_SHIFT                                                                      8
+  #define SRC_REG_CTRL_VLAN_HASH_ENABLE                                                                      (0x1<<16) // Enable for VLAN in Hash Address. !!! NOTE : vlan_hash_enable == 1 and vlan_match_disable == 1 is illegal !!!
+  #define SRC_REG_CTRL_VLAN_HASH_ENABLE_SHIFT                                                                16
+  #define SRC_REG_CTRL_VLAN_MATCH_DISABLE                                                                    (0x1<<17) // Disable VLAN and VLAN Promiscuous Mode (vpf) matching logic.!!! NOTE : vlan_hash_enable == 1 and vlan_match_disable == 1 is illegal !!!
+  #define SRC_REG_CTRL_VLAN_MATCH_DISABLE_SHIFT                                                              17
+  #define SRC_REG_CTRL_STRING_MATCH_DISABLE                                                                  (0x1<<18) // Disable String Matching Logic.
+  #define SRC_REG_CTRL_STRING_MATCH_DISABLE_SHIFT                                                            18
+  #define SRC_REG_CTRL_ALLOWSHORTCUT                                                                         (0x1<<19) // If set; same search shortcut is allowed.
+  #define SRC_REG_CTRL_ALLOWSHORTCUT_SHIFT                                                                   19
+  #define SRC_REG_CTRL_ALLOWEMPTYSHORTCUT                                                                    (0x1<<20) // If set; search return no match on empty shortcut is allowed.
+  #define SRC_REG_CTRL_ALLOWEMPTYSHORTCUT_SHIFT                                                              20
+  #define SRC_REG_CTRL_TENANT_ID_DISABLE                                                                     (0x1<<21) // Disable Tenant ID Matching Logic.NOTE : tenant_id_in_hash_en == 1 and tenant_id_disable == 1 is illegal !!!
+  #define SRC_REG_CTRL_TENANT_ID_DISABLE_SHIFT                                                               21
+  #define SRC_REG_CTRL_TENANT_ID_IN_HASH_EN                                                                  (0x1<<22) // Enables the use of the tenant_id value in Hash address calculation.!!! NOTE : tenant_id_in_hash_en == 1 and tenant_id_disable == 1 is illegal !!!
+  #define SRC_REG_CTRL_TENANT_ID_IN_HASH_EN_SHIFT                                                            22
+#define SRC_REG_INT_STS                                                                                      0x2381d8UL //Access:R    DataWidth:0x1    // Multi Field Register.
+  #define SRC_REG_INT_STS_ADDRESS_ERROR                                                                      (0x1<<0) // Signals an unknown address to the rf module.
+  #define SRC_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                                0
+#define SRC_REG_INT_STS_CLR                                                                                  0x2381dcUL //Access:RC   DataWidth:0x1    // Multi Field Register.
+  #define SRC_REG_INT_STS_CLR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define SRC_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                            0
+#define SRC_REG_INT_STS_WR                                                                                   0x2381e0UL //Access:WR   DataWidth:0x1    // Multi Field Register.
+  #define SRC_REG_INT_STS_WR_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define SRC_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                             0
+#define SRC_REG_INT_MASK                                                                                     0x2381e4UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define SRC_REG_INT_MASK_ADDRESS_ERROR                                                                     (0x1<<0) // This bit masks, when set, the Interrupt bit: SRC_REG_INT_STS.ADDRESS_ERROR .
+  #define SRC_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                               0
+#define SRC_REG_KEYSEARCH_0                                                                                  0x238400UL //Access:RW   DataWidth:0x20   // Key for searcher hash function.
+#define SRC_REG_KEYSEARCH_1                                                                                  0x238404UL //Access:RW   DataWidth:0x20   // Key for searcher hash function.
+#define SRC_REG_KEYSEARCH_2                                                                                  0x238408UL //Access:RW   DataWidth:0x20   // Key for searcher hash function.
+#define SRC_REG_KEYSEARCH_3                                                                                  0x23840cUL //Access:RW   DataWidth:0x20   // Key for searcher hash function.
+#define SRC_REG_KEYSEARCH_4                                                                                  0x238410UL //Access:RW   DataWidth:0x20   // Key for searcher hash function.
+#define SRC_REG_KEYSEARCH_5                                                                                  0x238414UL //Access:RW   DataWidth:0x20   // Key for searcher hash function.
+#define SRC_REG_KEYSEARCH_6                                                                                  0x238418UL //Access:RW   DataWidth:0x20   // Key for searcher hash function.
+#define SRC_REG_KEYSEARCH_7                                                                                  0x23841cUL //Access:RW   DataWidth:0x20   // Key for searcher hash function.
+#define SRC_REG_KEYSEARCH_8                                                                                  0x238420UL //Access:RW   DataWidth:0x20   // Key for searcher hash function.
+#define SRC_REG_KEYSEARCH_9                                                                                  0x238424UL //Access:RW   DataWidth:0x20   // Key for searcher hash function.
+#define SRC_REG_KEYSEARCH_VLAN                                                                               0x238428UL //Access:RW   DataWidth:0xc    // Key for searcher hash function vlan field. HAS NO EFFECT IN E4 B0!!!
+#define SRC_REG_IF_STAT_PF_CONFIG                                                                            0x238480UL //Access:RW   DataWidth:0x10   // Per-PF Bitmask for inclusion in Ingress Flow Statistics counters.
+#define SRC_REG_IF_STAT_STRTYPE_CONFIG                                                                       0x238484UL //Access:RW   DataWidth:0x8    // Per-StringType Bitmask for inclusion in Ingress Flow Statistics counters.
+#define SRC_REG_IF_STAT_ENABLED                                                                              0x238488UL //Access:RW   DataWidth:0x1    // IF Stats Enable Bit.  IF Stat Counters only count when this bit is set.     This bit is cleared when any IF Stat Counter is read to ensure coherency.     Setting this bit clears all IF Stat Counters.
+#define SRC_REG_IF_STAT_SEARCH_COUNTER                                                                       0x23848cUL //Access:R    DataWidth:0x20   // IF Stat Search Counter.  This register counts all Search Requests received.
+#define SRC_REG_IF_STAT_HIT_COUNTER                                                                          0x238490UL //Access:R    DataWidth:0x20   // IF Stat Hit Counter.  This register counts all Search Hits on both Table 1 and Table 2.
+#define SRC_REG_IF_STAT_T1_HIT_COUNTER                                                                       0x238494UL //Access:R    DataWidth:0x20   // IF Stat T1 Hit Counter.  This register counts all Search Hits on Table 1 only.
+#define SRC_REG_IF_STAT_NO_READ_COUNTER                                                                      0x238498UL //Access:R    DataWidth:0x20   // IF Stat No Read Counter.  This register counts all Search requests which did not generate a Table     Access.  This is caused when there is an outstanding request for the same string.
+#define SRC_REG_NUMIPV4CONN                                                                                  0x23849cUL //Access:R    DataWidth:0x1a   // Number of Ipv4 connections (statistics).
+#define SRC_REG_NUMIPV6CONN                                                                                  0x2384a0UL //Access:R    DataWidth:0x1a   // Number of Ipv6 connections (statistics).
+#define SRC_REG_FIRSTFREE                                                                                    0x238500UL //Access:WB   DataWidth:0x40   // First free element in the free list of T2 entries
+#define SRC_REG_FIRSTFREE_SIZE                                                                               2
+#define SRC_REG_LASTFREE                                                                                     0x238520UL //Access:WB   DataWidth:0x40   // Last free element in the free list of T2 entries
+#define SRC_REG_LASTFREE_SIZE                                                                                2
+#define SRC_REG_COUNTFREE                                                                                    0x238540UL //Access:RW   DataWidth:0x16   // Number of free element in the free list of T2 entries
+#define SRC_REG_PXP_CTRL                                                                                     0x238600UL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define SRC_REG_PXP_CTRL_PXP_ATC_T1                                                                        (0x7<<0) // Controls PXP Request ATC Field for Table1.
+  #define SRC_REG_PXP_CTRL_PXP_ATC_T1_SHIFT                                                                  0
+  #define SRC_REG_PXP_CTRL_PXP_TPHVALID_T1                                                                   (0x1<<3) // Controls PXP Request TPH Valid field for Table1.
+  #define SRC_REG_PXP_CTRL_PXP_TPHVALID_T1_SHIFT                                                             3
+  #define SRC_REG_PXP_CTRL_PXP_ATC_T2                                                                        (0x7<<4) // Controls PXP Request ATC Field for Table2.
+  #define SRC_REG_PXP_CTRL_PXP_ATC_T2_SHIFT                                                                  4
+  #define SRC_REG_PXP_CTRL_PXP_TPHVALID_T2                                                                   (0x1<<7) // Controls PXP Request TPH Valid field for Table2.
+  #define SRC_REG_PXP_CTRL_PXP_TPHVALID_T2_SHIFT                                                             7
+  #define SRC_REG_PXP_CTRL_PXP_DONETYPE                                                                      (0x1<<8) // Controls PXP Request DonType Field.
+  #define SRC_REG_PXP_CTRL_PXP_DONETYPE_SHIFT                                                                8
+#define SRC_REG_NUMBER_HASH_BITS                                                                             0x238604UL //Access:RW   DataWidth:0x5    // The number of hash bits used for the search (h); Values can be 8 to 24.
+#define SRC_REG_EMPTY_PF                                                                                     0x238620UL //Access:RW   DataWidth:0x20   // Empty bit per bin 256 bins per PF.
+#define SRC_REG_EMPTY_PF_SIZE                                                                                8
+#define SRC_REG_DBG_SELECT                                                                                   0x238700UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define SRC_REG_DBG_DWORD_ENABLE                                                                             0x238704UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define SRC_REG_DBG_SHIFT                                                                                    0x238708UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define SRC_REG_DBG_FORCE_VALID                                                                              0x23870cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define SRC_REG_DBG_FORCE_FRAME                                                                              0x238710UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define SRC_REG_DBG_OUT_DATA                                                                                 0x238720UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define SRC_REG_DBG_OUT_DATA_SIZE                                                                            8
+#define SRC_REG_DBG_OUT_VALID                                                                                0x238740UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define SRC_REG_DBG_OUT_FRAME                                                                                0x238744UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define SRC_REG_ECO_RESERVED                                                                                 0x238748UL //Access:RW   DataWidth:0x8    // ECO reserved.
+#define SRC_REG_SOFT_RST                                                                                     0x23874cUL //Access:RW   DataWidth:0x19   // Reset internal state machines.
+#define RSS_REG_RSS_INIT_EN                                                                                  0x238804UL //Access:RW   DataWidth:0x1    // Write to this register will initialize all rows of RSS memory to zeros.It will be be set to 0 when init will be finished.
+#define RSS_REG_RSS_INIT_DONE                                                                                0x238808UL //Access:R    DataWidth:0x1    // This register will be set when init procedure of RSS memory is finished.
+#define RSS_REG_IF_ENABLE                                                                                    0x23880cUL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define RSS_REG_IF_ENABLE_TMLD_INP_EN                                                                      (0x1<<0) // TM loader input interface enable register.
+  #define RSS_REG_IF_ENABLE_TMLD_INP_EN_SHIFT                                                                0
+  #define RSS_REG_IF_ENABLE_RGFS_INP_EN_E5                                                                   (0x1<<1) // RGFS input interface enable register.
+  #define RSS_REG_IF_ENABLE_RGFS_INP_EN_E5_SHIFT                                                             1
+  #define RSS_REG_IF_ENABLE_TMLD_OUT_EN                                                                      (0x1<<2) // TM loader output interface enable register.
+  #define RSS_REG_IF_ENABLE_TMLD_OUT_EN_SHIFT                                                                2
+  #define RSS_REG_IF_ENABLE_RGFS_OUT_EN_E5                                                                   (0x1<<3) // RGFS output interface enable register.
+  #define RSS_REG_IF_ENABLE_RGFS_OUT_EN_E5_SHIFT                                                             3
+  #define RSS_REG_IF_ENABLE_TSEM_INP_EN_BB_K2                                                                (0x1<<1) // TSEM input interface enable register.
+  #define RSS_REG_IF_ENABLE_TSEM_INP_EN_BB_K2_SHIFT                                                          1
+  #define RSS_REG_IF_ENABLE_TSEM_OUT_EN_BB_K2                                                                (0x1<<3) // TSEM output interface enable register.
+  #define RSS_REG_IF_ENABLE_TSEM_OUT_EN_BB_K2_SHIFT                                                          3
+#define RSS_REG_INT_STS                                                                                      0x238980UL //Access:R    DataWidth:0x16   // Multi Field Register.
+  #define RSS_REG_INT_STS_ADDRESS_ERROR                                                                      (0x1<<0) // Signals an unknown address to the rf module.
+  #define RSS_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                                0
+  #define RSS_REG_INT_STS_CMD_FIFO_ERROR                                                                     (0x1<<8) // RSS command FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_CMD_FIFO_ERROR_SHIFT                                                               8
+  #define RSS_REG_INT_STS_RSP_FIFO_ERROR                                                                     (0x1<<10) // Response FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_RSP_FIFO_ERROR_SHIFT                                                               10
+  #define RSS_REG_INT_STS_HDR_FIFO_ERROR                                                                     (0x1<<11) // Header FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_HDR_FIFO_ERROR_SHIFT                                                               11
+  #define RSS_REG_INT_STS_INFO_FIFO_ERROR_E5                                                                 (0x1<<12) // Info FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_INFO_FIFO_ERROR_E5_SHIFT                                                           12
+  #define RSS_REG_INT_STS_KEY_LOW_FIFO_ERROR_E5                                                              (0x1<<13) // Key Low FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_KEY_LOW_FIFO_ERROR_E5_SHIFT                                                        13
+  #define RSS_REG_INT_STS_KEY_MID_FIFO_ERROR_E5                                                              (0x1<<14) // Key Mid FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_KEY_MID_FIFO_ERROR_E5_SHIFT                                                        14
+  #define RSS_REG_INT_STS_KEY_HIGH_FIFO_ERROR_E5                                                             (0x1<<15) // Key High FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_KEY_HIGH_FIFO_ERROR_E5_SHIFT                                                       15
+  #define RSS_REG_INT_STS_TUPLE_FIFO_ERROR_E5                                                                (0x1<<16) // Tuple FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_TUPLE_FIFO_ERROR_E5_SHIFT                                                          16
+  #define RSS_REG_INT_STS_HASH_FIFO_ERROR_E5                                                                 (0x1<<17) // Hash FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_HASH_FIFO_ERROR_E5_SHIFT                                                           17
+  #define RSS_REG_INT_STS_HASH_TUPLE_FIFO_ERROR_E5                                                           (0x1<<18) // Hash Tuple FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_HASH_TUPLE_FIFO_ERROR_E5_SHIFT                                                     18
+  #define RSS_REG_INT_STS_IND_HASH_FIFO_ERROR_E5                                                             (0x1<<19) // Indirect Hash FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_IND_HASH_FIFO_ERROR_E5_SHIFT                                                       19
+  #define RSS_REG_INT_STS_F4TUPLE_OFFSET_ZERO_E5                                                             (0x1<<20) // Received RSS hash command where f4tuple_offset field was 0.
+  #define RSS_REG_INT_STS_F4TUPLE_OFFSET_ZERO_E5_SHIFT                                                       20
+  #define RSS_REG_INT_STS_F4TUPLE_OFFSET_IN_TMLD_E5                                                          (0x1<<21) // Received RSS hash command where f4tuple_offset field puts f4tuple in the tmld header.
+  #define RSS_REG_INT_STS_F4TUPLE_OFFSET_IN_TMLD_E5_SHIFT                                                    21
+  #define RSS_REG_INT_STS_MSG_INP_CNT_ERROR_BB_K2                                                            (0x1<<1) // Number of cycles in CM message from TSEM is 63.
+  #define RSS_REG_INT_STS_MSG_INP_CNT_ERROR_BB_K2_SHIFT                                                      1
+  #define RSS_REG_INT_STS_MSG_OUT_CNT_ERROR_BB_K2                                                            (0x1<<2) // Number of cycles in CM message to TM loader is 63.
+  #define RSS_REG_INT_STS_MSG_OUT_CNT_ERROR_BB_K2_SHIFT                                                      2
+  #define RSS_REG_INT_STS_INP_STATE_ERROR_BB_K2                                                              (0x1<<3) // Input state machine reached error state.
+  #define RSS_REG_INT_STS_INP_STATE_ERROR_BB_K2_SHIFT                                                        3
+  #define RSS_REG_INT_STS_OUT_STATE_ERROR_BB_K2                                                              (0x1<<4) // Output state machine reached error state.
+  #define RSS_REG_INT_STS_OUT_STATE_ERROR_BB_K2_SHIFT                                                        4
+  #define RSS_REG_INT_STS_MAIN_STATE_ERROR_BB_K2                                                             (0x1<<5) // Main state machine in RSS calculation block reached error state.
+  #define RSS_REG_INT_STS_MAIN_STATE_ERROR_BB_K2_SHIFT                                                       5
+  #define RSS_REG_INT_STS_CALC_STATE_ERROR_BB_K2                                                             (0x1<<6) // CALC state machine in RSS calculation block reached error state.
+  #define RSS_REG_INT_STS_CALC_STATE_ERROR_BB_K2_SHIFT                                                       6
+  #define RSS_REG_INT_STS_INP_FIFO_ERROR_BB_K2                                                               (0x1<<7) // Input FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_INP_FIFO_ERROR_BB_K2_SHIFT                                                         7
+  #define RSS_REG_INT_STS_MSG_FIFO_ERROR_BB_K2                                                               (0x1<<9) // Message FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_MSG_FIFO_ERROR_BB_K2_SHIFT                                                         9
+#define RSS_REG_INT_MASK                                                                                     0x238984UL //Access:RW   DataWidth:0x16   // Multi Field Register.
+  #define RSS_REG_INT_MASK_ADDRESS_ERROR                                                                     (0x1<<0) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.ADDRESS_ERROR .
+  #define RSS_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                               0
+  #define RSS_REG_INT_MASK_CMD_FIFO_ERROR                                                                    (0x1<<8) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.CMD_FIFO_ERROR .
+  #define RSS_REG_INT_MASK_CMD_FIFO_ERROR_SHIFT                                                              8
+  #define RSS_REG_INT_MASK_RSP_FIFO_ERROR                                                                    (0x1<<10) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.RSP_FIFO_ERROR .
+  #define RSS_REG_INT_MASK_RSP_FIFO_ERROR_SHIFT                                                              10
+  #define RSS_REG_INT_MASK_HDR_FIFO_ERROR                                                                    (0x1<<11) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.HDR_FIFO_ERROR .
+  #define RSS_REG_INT_MASK_HDR_FIFO_ERROR_SHIFT                                                              11
+  #define RSS_REG_INT_MASK_INFO_FIFO_ERROR_E5                                                                (0x1<<12) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.INFO_FIFO_ERROR .
+  #define RSS_REG_INT_MASK_INFO_FIFO_ERROR_E5_SHIFT                                                          12
+  #define RSS_REG_INT_MASK_KEY_LOW_FIFO_ERROR_E5                                                             (0x1<<13) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.KEY_LOW_FIFO_ERROR .
+  #define RSS_REG_INT_MASK_KEY_LOW_FIFO_ERROR_E5_SHIFT                                                       13
+  #define RSS_REG_INT_MASK_KEY_MID_FIFO_ERROR_E5                                                             (0x1<<14) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.KEY_MID_FIFO_ERROR .
+  #define RSS_REG_INT_MASK_KEY_MID_FIFO_ERROR_E5_SHIFT                                                       14
+  #define RSS_REG_INT_MASK_KEY_HIGH_FIFO_ERROR_E5                                                            (0x1<<15) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.KEY_HIGH_FIFO_ERROR .
+  #define RSS_REG_INT_MASK_KEY_HIGH_FIFO_ERROR_E5_SHIFT                                                      15
+  #define RSS_REG_INT_MASK_TUPLE_FIFO_ERROR_E5                                                               (0x1<<16) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.TUPLE_FIFO_ERROR .
+  #define RSS_REG_INT_MASK_TUPLE_FIFO_ERROR_E5_SHIFT                                                         16
+  #define RSS_REG_INT_MASK_HASH_FIFO_ERROR_E5                                                                (0x1<<17) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.HASH_FIFO_ERROR .
+  #define RSS_REG_INT_MASK_HASH_FIFO_ERROR_E5_SHIFT                                                          17
+  #define RSS_REG_INT_MASK_HASH_TUPLE_FIFO_ERROR_E5                                                          (0x1<<18) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.HASH_TUPLE_FIFO_ERROR .
+  #define RSS_REG_INT_MASK_HASH_TUPLE_FIFO_ERROR_E5_SHIFT                                                    18
+  #define RSS_REG_INT_MASK_IND_HASH_FIFO_ERROR_E5                                                            (0x1<<19) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.IND_HASH_FIFO_ERROR .
+  #define RSS_REG_INT_MASK_IND_HASH_FIFO_ERROR_E5_SHIFT                                                      19
+  #define RSS_REG_INT_MASK_F4TUPLE_OFFSET_ZERO_E5                                                            (0x1<<20) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.F4TUPLE_OFFSET_ZERO .
+  #define RSS_REG_INT_MASK_F4TUPLE_OFFSET_ZERO_E5_SHIFT                                                      20
+  #define RSS_REG_INT_MASK_F4TUPLE_OFFSET_IN_TMLD_E5                                                         (0x1<<21) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.F4TUPLE_OFFSET_IN_TMLD .
+  #define RSS_REG_INT_MASK_F4TUPLE_OFFSET_IN_TMLD_E5_SHIFT                                                   21
+  #define RSS_REG_INT_MASK_MSG_INP_CNT_ERROR_BB_K2                                                           (0x1<<1) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.MSG_INP_CNT_ERROR .
+  #define RSS_REG_INT_MASK_MSG_INP_CNT_ERROR_BB_K2_SHIFT                                                     1
+  #define RSS_REG_INT_MASK_MSG_OUT_CNT_ERROR_BB_K2                                                           (0x1<<2) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.MSG_OUT_CNT_ERROR .
+  #define RSS_REG_INT_MASK_MSG_OUT_CNT_ERROR_BB_K2_SHIFT                                                     2
+  #define RSS_REG_INT_MASK_INP_STATE_ERROR_BB_K2                                                             (0x1<<3) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.INP_STATE_ERROR .
+  #define RSS_REG_INT_MASK_INP_STATE_ERROR_BB_K2_SHIFT                                                       3
+  #define RSS_REG_INT_MASK_OUT_STATE_ERROR_BB_K2                                                             (0x1<<4) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.OUT_STATE_ERROR .
+  #define RSS_REG_INT_MASK_OUT_STATE_ERROR_BB_K2_SHIFT                                                       4
+  #define RSS_REG_INT_MASK_MAIN_STATE_ERROR_BB_K2                                                            (0x1<<5) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.MAIN_STATE_ERROR .
+  #define RSS_REG_INT_MASK_MAIN_STATE_ERROR_BB_K2_SHIFT                                                      5
+  #define RSS_REG_INT_MASK_CALC_STATE_ERROR_BB_K2                                                            (0x1<<6) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.CALC_STATE_ERROR .
+  #define RSS_REG_INT_MASK_CALC_STATE_ERROR_BB_K2_SHIFT                                                      6
+  #define RSS_REG_INT_MASK_INP_FIFO_ERROR_BB_K2                                                              (0x1<<7) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.INP_FIFO_ERROR .
+  #define RSS_REG_INT_MASK_INP_FIFO_ERROR_BB_K2_SHIFT                                                        7
+  #define RSS_REG_INT_MASK_MSG_FIFO_ERROR_BB_K2                                                              (0x1<<9) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.MSG_FIFO_ERROR .
+  #define RSS_REG_INT_MASK_MSG_FIFO_ERROR_BB_K2_SHIFT                                                        9
+#define RSS_REG_INT_STS_WR                                                                                   0x238988UL //Access:WR   DataWidth:0x16   // Multi Field Register.
+  #define RSS_REG_INT_STS_WR_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define RSS_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                             0
+  #define RSS_REG_INT_STS_WR_CMD_FIFO_ERROR                                                                  (0x1<<8) // RSS command FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_WR_CMD_FIFO_ERROR_SHIFT                                                            8
+  #define RSS_REG_INT_STS_WR_RSP_FIFO_ERROR                                                                  (0x1<<10) // Response FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_WR_RSP_FIFO_ERROR_SHIFT                                                            10
+  #define RSS_REG_INT_STS_WR_HDR_FIFO_ERROR                                                                  (0x1<<11) // Header FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_WR_HDR_FIFO_ERROR_SHIFT                                                            11
+  #define RSS_REG_INT_STS_WR_INFO_FIFO_ERROR_E5                                                              (0x1<<12) // Info FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_WR_INFO_FIFO_ERROR_E5_SHIFT                                                        12
+  #define RSS_REG_INT_STS_WR_KEY_LOW_FIFO_ERROR_E5                                                           (0x1<<13) // Key Low FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_WR_KEY_LOW_FIFO_ERROR_E5_SHIFT                                                     13
+  #define RSS_REG_INT_STS_WR_KEY_MID_FIFO_ERROR_E5                                                           (0x1<<14) // Key Mid FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_WR_KEY_MID_FIFO_ERROR_E5_SHIFT                                                     14
+  #define RSS_REG_INT_STS_WR_KEY_HIGH_FIFO_ERROR_E5                                                          (0x1<<15) // Key High FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_WR_KEY_HIGH_FIFO_ERROR_E5_SHIFT                                                    15
+  #define RSS_REG_INT_STS_WR_TUPLE_FIFO_ERROR_E5                                                             (0x1<<16) // Tuple FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_WR_TUPLE_FIFO_ERROR_E5_SHIFT                                                       16
+  #define RSS_REG_INT_STS_WR_HASH_FIFO_ERROR_E5                                                              (0x1<<17) // Hash FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_WR_HASH_FIFO_ERROR_E5_SHIFT                                                        17
+  #define RSS_REG_INT_STS_WR_HASH_TUPLE_FIFO_ERROR_E5                                                        (0x1<<18) // Hash Tuple FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_WR_HASH_TUPLE_FIFO_ERROR_E5_SHIFT                                                  18
+  #define RSS_REG_INT_STS_WR_IND_HASH_FIFO_ERROR_E5                                                          (0x1<<19) // Indirect Hash FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_WR_IND_HASH_FIFO_ERROR_E5_SHIFT                                                    19
+  #define RSS_REG_INT_STS_WR_F4TUPLE_OFFSET_ZERO_E5                                                          (0x1<<20) // Received RSS hash command where f4tuple_offset field was 0.
+  #define RSS_REG_INT_STS_WR_F4TUPLE_OFFSET_ZERO_E5_SHIFT                                                    20
+  #define RSS_REG_INT_STS_WR_F4TUPLE_OFFSET_IN_TMLD_E5                                                       (0x1<<21) // Received RSS hash command where f4tuple_offset field puts f4tuple in the tmld header.
+  #define RSS_REG_INT_STS_WR_F4TUPLE_OFFSET_IN_TMLD_E5_SHIFT                                                 21
+  #define RSS_REG_INT_STS_WR_MSG_INP_CNT_ERROR_BB_K2                                                         (0x1<<1) // Number of cycles in CM message from TSEM is 63.
+  #define RSS_REG_INT_STS_WR_MSG_INP_CNT_ERROR_BB_K2_SHIFT                                                   1
+  #define RSS_REG_INT_STS_WR_MSG_OUT_CNT_ERROR_BB_K2                                                         (0x1<<2) // Number of cycles in CM message to TM loader is 63.
+  #define RSS_REG_INT_STS_WR_MSG_OUT_CNT_ERROR_BB_K2_SHIFT                                                   2
+  #define RSS_REG_INT_STS_WR_INP_STATE_ERROR_BB_K2                                                           (0x1<<3) // Input state machine reached error state.
+  #define RSS_REG_INT_STS_WR_INP_STATE_ERROR_BB_K2_SHIFT                                                     3
+  #define RSS_REG_INT_STS_WR_OUT_STATE_ERROR_BB_K2                                                           (0x1<<4) // Output state machine reached error state.
+  #define RSS_REG_INT_STS_WR_OUT_STATE_ERROR_BB_K2_SHIFT                                                     4
+  #define RSS_REG_INT_STS_WR_MAIN_STATE_ERROR_BB_K2                                                          (0x1<<5) // Main state machine in RSS calculation block reached error state.
+  #define RSS_REG_INT_STS_WR_MAIN_STATE_ERROR_BB_K2_SHIFT                                                    5
+  #define RSS_REG_INT_STS_WR_CALC_STATE_ERROR_BB_K2                                                          (0x1<<6) // CALC state machine in RSS calculation block reached error state.
+  #define RSS_REG_INT_STS_WR_CALC_STATE_ERROR_BB_K2_SHIFT                                                    6
+  #define RSS_REG_INT_STS_WR_INP_FIFO_ERROR_BB_K2                                                            (0x1<<7) // Input FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_WR_INP_FIFO_ERROR_BB_K2_SHIFT                                                      7
+  #define RSS_REG_INT_STS_WR_MSG_FIFO_ERROR_BB_K2                                                            (0x1<<9) // Message FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_WR_MSG_FIFO_ERROR_BB_K2_SHIFT                                                      9
+#define RSS_REG_INT_STS_CLR                                                                                  0x23898cUL //Access:RC   DataWidth:0x16   // Multi Field Register.
+  #define RSS_REG_INT_STS_CLR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define RSS_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                            0
+  #define RSS_REG_INT_STS_CLR_CMD_FIFO_ERROR                                                                 (0x1<<8) // RSS command FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_CLR_CMD_FIFO_ERROR_SHIFT                                                           8
+  #define RSS_REG_INT_STS_CLR_RSP_FIFO_ERROR                                                                 (0x1<<10) // Response FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_CLR_RSP_FIFO_ERROR_SHIFT                                                           10
+  #define RSS_REG_INT_STS_CLR_HDR_FIFO_ERROR                                                                 (0x1<<11) // Header FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_CLR_HDR_FIFO_ERROR_SHIFT                                                           11
+  #define RSS_REG_INT_STS_CLR_INFO_FIFO_ERROR_E5                                                             (0x1<<12) // Info FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_CLR_INFO_FIFO_ERROR_E5_SHIFT                                                       12
+  #define RSS_REG_INT_STS_CLR_KEY_LOW_FIFO_ERROR_E5                                                          (0x1<<13) // Key Low FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_CLR_KEY_LOW_FIFO_ERROR_E5_SHIFT                                                    13
+  #define RSS_REG_INT_STS_CLR_KEY_MID_FIFO_ERROR_E5                                                          (0x1<<14) // Key Mid FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_CLR_KEY_MID_FIFO_ERROR_E5_SHIFT                                                    14
+  #define RSS_REG_INT_STS_CLR_KEY_HIGH_FIFO_ERROR_E5                                                         (0x1<<15) // Key High FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_CLR_KEY_HIGH_FIFO_ERROR_E5_SHIFT                                                   15
+  #define RSS_REG_INT_STS_CLR_TUPLE_FIFO_ERROR_E5                                                            (0x1<<16) // Tuple FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_CLR_TUPLE_FIFO_ERROR_E5_SHIFT                                                      16
+  #define RSS_REG_INT_STS_CLR_HASH_FIFO_ERROR_E5                                                             (0x1<<17) // Hash FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_CLR_HASH_FIFO_ERROR_E5_SHIFT                                                       17
+  #define RSS_REG_INT_STS_CLR_HASH_TUPLE_FIFO_ERROR_E5                                                       (0x1<<18) // Hash Tuple FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_CLR_HASH_TUPLE_FIFO_ERROR_E5_SHIFT                                                 18
+  #define RSS_REG_INT_STS_CLR_IND_HASH_FIFO_ERROR_E5                                                         (0x1<<19) // Indirect Hash FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_CLR_IND_HASH_FIFO_ERROR_E5_SHIFT                                                   19
+  #define RSS_REG_INT_STS_CLR_F4TUPLE_OFFSET_ZERO_E5                                                         (0x1<<20) // Received RSS hash command where f4tuple_offset field was 0.
+  #define RSS_REG_INT_STS_CLR_F4TUPLE_OFFSET_ZERO_E5_SHIFT                                                   20
+  #define RSS_REG_INT_STS_CLR_F4TUPLE_OFFSET_IN_TMLD_E5                                                      (0x1<<21) // Received RSS hash command where f4tuple_offset field puts f4tuple in the tmld header.
+  #define RSS_REG_INT_STS_CLR_F4TUPLE_OFFSET_IN_TMLD_E5_SHIFT                                                21
+  #define RSS_REG_INT_STS_CLR_MSG_INP_CNT_ERROR_BB_K2                                                        (0x1<<1) // Number of cycles in CM message from TSEM is 63.
+  #define RSS_REG_INT_STS_CLR_MSG_INP_CNT_ERROR_BB_K2_SHIFT                                                  1
+  #define RSS_REG_INT_STS_CLR_MSG_OUT_CNT_ERROR_BB_K2                                                        (0x1<<2) // Number of cycles in CM message to TM loader is 63.
+  #define RSS_REG_INT_STS_CLR_MSG_OUT_CNT_ERROR_BB_K2_SHIFT                                                  2
+  #define RSS_REG_INT_STS_CLR_INP_STATE_ERROR_BB_K2                                                          (0x1<<3) // Input state machine reached error state.
+  #define RSS_REG_INT_STS_CLR_INP_STATE_ERROR_BB_K2_SHIFT                                                    3
+  #define RSS_REG_INT_STS_CLR_OUT_STATE_ERROR_BB_K2                                                          (0x1<<4) // Output state machine reached error state.
+  #define RSS_REG_INT_STS_CLR_OUT_STATE_ERROR_BB_K2_SHIFT                                                    4
+  #define RSS_REG_INT_STS_CLR_MAIN_STATE_ERROR_BB_K2                                                         (0x1<<5) // Main state machine in RSS calculation block reached error state.
+  #define RSS_REG_INT_STS_CLR_MAIN_STATE_ERROR_BB_K2_SHIFT                                                   5
+  #define RSS_REG_INT_STS_CLR_CALC_STATE_ERROR_BB_K2                                                         (0x1<<6) // CALC state machine in RSS calculation block reached error state.
+  #define RSS_REG_INT_STS_CLR_CALC_STATE_ERROR_BB_K2_SHIFT                                                   6
+  #define RSS_REG_INT_STS_CLR_INP_FIFO_ERROR_BB_K2                                                           (0x1<<7) // Input FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_CLR_INP_FIFO_ERROR_BB_K2_SHIFT                                                     7
+  #define RSS_REG_INT_STS_CLR_MSG_FIFO_ERROR_BB_K2                                                           (0x1<<9) // Message FIFO overflow or underflow.
+  #define RSS_REG_INT_STS_CLR_MSG_FIFO_ERROR_BB_K2_SHIFT                                                     9
+#define RSS_REG_PRTY_MASK_H_0_BB_K2                                                                          0x238a04UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define RSS_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_BB_K2                                                    (0x1<<0) // This bit masks, when set, the Parity bit: RSS_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT .
+  #define RSS_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_BB_K2_SHIFT                                              0
+  #define RSS_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_K2                                                    (0x1<<1) // This bit masks, when set, the Parity bit: RSS_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
+  #define RSS_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_K2_SHIFT                                              1
+  #define RSS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                      (0x1<<2) // This bit masks, when set, the Parity bit: RSS_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define RSS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                                2
+  #define RSS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                      (0x1<<3) // This bit masks, when set, the Parity bit: RSS_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define RSS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                                3
+#define RSS_REG_MEM_ECC_ENABLE_0_BB_K2                                                                       0x238a10UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define RSS_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN_BB_K2                                                     (0x1<<0) // Enable ECC for memory ecc instance rss.RSS_MEM_K2_GEN_IF.i_rss_mem_ram.i_ecc in module rss_mem_4port_ram
+  #define RSS_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN_BB_K2_SHIFT                                               0
+  #define RSS_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_BB_K2                                                     (0x1<<1) // Enable ECC for memory ecc instance rss.RSS_IND_K2_GEN_IF.i_rss_ind_ram.i_ecc in module rss_ind_4port_ram
+  #define RSS_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_BB_K2_SHIFT                                               1
+#define RSS_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                  0x238a14UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define RSS_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY_BB_K2                                              (0x1<<0) // Set parity only for memory ecc instance rss.RSS_MEM_K2_GEN_IF.i_rss_mem_ram.i_ecc in module rss_mem_4port_ram
+  #define RSS_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY_BB_K2_SHIFT                                        0
+  #define RSS_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_BB_K2                                              (0x1<<1) // Set parity only for memory ecc instance rss.RSS_IND_K2_GEN_IF.i_rss_ind_ram.i_ecc in module rss_ind_4port_ram
+  #define RSS_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_BB_K2_SHIFT                                        1
+#define RSS_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                              0x238a18UL //Access:RC   DataWidth:0x2    // Multi Field Register.
+  #define RSS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT_BB_K2                                       (0x1<<0) // Record if a correctable error occurred on memory ecc instance rss.RSS_MEM_K2_GEN_IF.i_rss_mem_ram.i_ecc in module rss_mem_4port_ram
+  #define RSS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT_BB_K2_SHIFT                                 0
+  #define RSS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_BB_K2                                       (0x1<<1) // Record if a correctable error occurred on memory ecc instance rss.RSS_IND_K2_GEN_IF.i_rss_ind_ram.i_ecc in module rss_ind_4port_ram
+  #define RSS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_BB_K2_SHIFT                                 1
+#define RSS_REG_MEM_ECC_EVENTS_BB_K2                                                                         0x238a1cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define RSS_REG_KEY_RSS_EXT5                                                                                 0x238c00UL //Access:RW   DataWidth:0x8    // Key extension for 5th tuple.
+#define RSS_REG_TMLD_CREDIT                                                                                  0x238c04UL //Access:RW   DataWidth:0x6    // Number of credits on RSS interface to TMLD. Maximal supported value is 32.
+#define RSS_REG_RSS_RAM_MASK                                                                                 0x238c10UL //Access:WB   DataWidth:0x80   // RSS RAM bit enable. It will be used for write operation from RBC. If it equals to 1 then rss_ram_data for appropriate location will be written. Other way data will stay in this place without change.
+#define RSS_REG_RSS_RAM_MASK_SIZE                                                                            4
+#define RSS_REG_RSS_RAM_DATA                                                                                 0x238c20UL //Access:WB   DataWidth:0x80   // RSS RAM data. Read or write to this register will generate read or write transaction to RSS memory. Write data in this register will stay till next read command. After read was done to this register then vaue of this register will be changed to read data from RSS memory.
+#define RSS_REG_RSS_RAM_DATA_SIZE                                                                            4
+#define RSS_REG_RSS_RAM_ADDR                                                                                 0x238c30UL //Access:RW   DataWidth:0xd    // RSS RAM address. If bit 12 is 1 then bits 11:0 is done to RSS indirection memory If bits 12:10 is 0 then bits 6:0 is address to RSS CID table; If bits 12:10 is 1 then bits 9:0 is address to RSS KEY MSB table; If bits 12:10 is 2 then bits 9:0 is address to RSS KEY LSB table; If bits 12:10 is 3 then bits 7:0 is address to RSS INFO table.
+#define RSS_REG_RBC_STATUS                                                                                   0x238c34UL //Access:R    DataWidth:0x2    // B0 is asserted when RSS has a request from RBC that is still not done; B1 is asserted when RSS executed read or write request from RBC and next request still wasn't received.
+#define RSS_REG_EMPTY_STATUS_BB_K2                                                                           0x238c38UL //Access:R    DataWidth:0x5    // Debug register. FIFO empty status: {b0 - MSG FIFO; b1- RSS CMD FIFO; b2- INPUT FIFO; b3 - RSP FIFO; b4- RSS header FIFO}.
+#define RSS_REG_FULL_STATUS_BB_K2                                                                            0x238c3cUL //Access:R    DataWidth:0x5    // Debug register. FIFO empty status: {b0 - MSG FIFO; b1- RSS CMD FIFO; b2- INPUT FIFO; b3 - RSP FIFO; b4- RSS header FIFO}.
+#define RSS_REG_COUNTERS_STATUS_BB_K2                                                                        0x238c40UL //Access:R    DataWidth:0x20   // Debug register. FIFO empty status: {b15:8 - inp_fifo_counter; b7:6- cmd_fifo_couter; b5:0 - msg_fifo_counter}.
+#define RSS_REG_STATE_MACHINES_BB_K2                                                                         0x238c44UL //Access:R    DataWidth:0x10   // Debug register. State of each state machine {b15:12 - calc_cur_state; b11:8 - main_cur_state;b7:4 - msg_cur_state; b3:0 - inp_cur_state}.
+#define RSS_REG_ECO_RESERVED                                                                                 0x238c48UL //Access:RW   DataWidth:0x20   // This is unused register for future ECOs.
+#define RSS_REG_DBG_SELECT                                                                                   0x238c4cUL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define RSS_REG_DBG_DWORD_ENABLE                                                                             0x238c50UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define RSS_REG_DBG_SHIFT                                                                                    0x238c54UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define RSS_REG_DBG_FORCE_VALID                                                                              0x238c58UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define RSS_REG_DBG_FORCE_FRAME                                                                              0x238c5cUL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define RSS_REG_DBG_OUT_DATA                                                                                 0x238c60UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define RSS_REG_DBG_OUT_DATA_SIZE                                                                            8
+#define RSS_REG_DBG_OUT_VALID                                                                                0x238c80UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define RSS_REG_DBG_OUT_FRAME                                                                                0x238c84UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define RSS_REG_MEMCTRL_WR_RD_N_BB                                                                           0x238c88UL //Access:RW   DataWidth:0x1    // wr/rd indication to CPU BIST
+#define RSS_REG_MEMCTRL_CMD_BB                                                                               0x238c8cUL //Access:RW   DataWidth:0x8    // command to CPU BIST
+#define RSS_REG_MEMCTRL_ADDRESS_BB                                                                           0x238c90UL //Access:RW   DataWidth:0x8    // address to CPU BIST
+#define RSS_REG_MEMCTRL_STATUS_BB                                                                            0x238c94UL //Access:R    DataWidth:0x20   // status from CPU BIST
+#define RSS_REG_FIFO_FULL_STATUS1_E5                                                                         0x238c98UL //Access:R    DataWidth:0xd    // Multi Field Register.
+  #define RSS_REG_FIFO_FULL_STATUS1_RSP_FIFO_FULL_E5                                                         (0x1<<0) // The rsp fifio is empty.
+  #define RSS_REG_FIFO_FULL_STATUS1_RSP_FIFO_FULL_E5_SHIFT                                                   0
+  #define RSS_REG_FIFO_FULL_STATUS1_IND_HASH_FIFO_FULL_E5                                                    (0x1<<1) // The ind_hash fifo is full.
+  #define RSS_REG_FIFO_FULL_STATUS1_IND_HASH_FIFO_FULL_E5_SHIFT                                              1
+  #define RSS_REG_FIFO_FULL_STATUS1_HASH_TUPLE_FIFO_FULL_E5                                                  (0x1<<2) // The hash_tuple fifo is full.
+  #define RSS_REG_FIFO_FULL_STATUS1_HASH_TUPLE_FIFO_FULL_E5_SHIFT                                            2
+  #define RSS_REG_FIFO_FULL_STATUS1_HASH_FIFO_FULL_E5                                                        (0x1<<3) // The hash fifo is full.
+  #define RSS_REG_FIFO_FULL_STATUS1_HASH_FIFO_FULL_E5_SHIFT                                                  3
+  #define RSS_REG_FIFO_FULL_STATUS1_TUPLE_FIFO_FULL_E5                                                       (0x1<<4) // The tuple fifo is full.
+  #define RSS_REG_FIFO_FULL_STATUS1_TUPLE_FIFO_FULL_E5_SHIFT                                                 4
+  #define RSS_REG_FIFO_FULL_STATUS1_KEY_HIGH_FIFO_FULL_E5                                                    (0x1<<5) // The key_high fifo is full.
+  #define RSS_REG_FIFO_FULL_STATUS1_KEY_HIGH_FIFO_FULL_E5_SHIFT                                              5
+  #define RSS_REG_FIFO_FULL_STATUS1_KEY_MID_FIFO_FULL_E5                                                     (0x1<<6) // The key_mid fifo is full.
+  #define RSS_REG_FIFO_FULL_STATUS1_KEY_MID_FIFO_FULL_E5_SHIFT                                               6
+  #define RSS_REG_FIFO_FULL_STATUS1_KEY_LOW_FIFO_FULL_E5                                                     (0x1<<7) // The key_low fifo is full.
+  #define RSS_REG_FIFO_FULL_STATUS1_KEY_LOW_FIFO_FULL_E5_SHIFT                                               7
+  #define RSS_REG_FIFO_FULL_STATUS1_INFO_FIFO_FULL_E5                                                        (0x1<<8) // The info fifo is full.
+  #define RSS_REG_FIFO_FULL_STATUS1_INFO_FIFO_FULL_E5_SHIFT                                                  8
+  #define RSS_REG_FIFO_FULL_STATUS1_HEADER_FIFO_FULL_E5                                                      (0x1<<9) // The header fifo is full.
+  #define RSS_REG_FIFO_FULL_STATUS1_HEADER_FIFO_FULL_E5_SHIFT                                                9
+  #define RSS_REG_FIFO_FULL_STATUS1_CMD_FIFO_FULL_E5                                                         (0x1<<10) // The cmd fifo is full.
+  #define RSS_REG_FIFO_FULL_STATUS1_CMD_FIFO_FULL_E5_SHIFT                                                   10
+  #define RSS_REG_FIFO_FULL_STATUS1_MSG_FIFO_FULL_E5                                                         (0x1<<11) // The msg fifo is full.
+  #define RSS_REG_FIFO_FULL_STATUS1_MSG_FIFO_FULL_E5_SHIFT                                                   11
+  #define RSS_REG_FIFO_FULL_STATUS1_INP_FIFO_FULL_E5                                                         (0x1<<12) // The inp fifo is full.
+  #define RSS_REG_FIFO_FULL_STATUS1_INP_FIFO_FULL_E5_SHIFT                                                   12
+#define RSS_REG_FIFO_EMPTY_STATUS1_E5                                                                        0x238c9cUL //Access:R    DataWidth:0xd    // Multi Field Register.
+  #define RSS_REG_FIFO_EMPTY_STATUS1_RSP_FIFO_EMPTY_E5                                                       (0x1<<0) // The rsp fifio is empty.
+  #define RSS_REG_FIFO_EMPTY_STATUS1_RSP_FIFO_EMPTY_E5_SHIFT                                                 0
+  #define RSS_REG_FIFO_EMPTY_STATUS1_IND_HASH_FIFO_EMPTY_E5                                                  (0x1<<1) // The ind_hash fifo is empty.
+  #define RSS_REG_FIFO_EMPTY_STATUS1_IND_HASH_FIFO_EMPTY_E5_SHIFT                                            1
+  #define RSS_REG_FIFO_EMPTY_STATUS1_HASH_TUPLE_FIFO_EMPTY_E5                                                (0x1<<2) // The hash_tuple fifo is empty.
+  #define RSS_REG_FIFO_EMPTY_STATUS1_HASH_TUPLE_FIFO_EMPTY_E5_SHIFT                                          2
+  #define RSS_REG_FIFO_EMPTY_STATUS1_HASH_FIFO_EMPTY_E5                                                      (0x1<<3) // The hash fifo is empty.
+  #define RSS_REG_FIFO_EMPTY_STATUS1_HASH_FIFO_EMPTY_E5_SHIFT                                                3
+  #define RSS_REG_FIFO_EMPTY_STATUS1_TUPLE_FIFO_EMPTY_E5                                                     (0x1<<4) // The tuple fifo is empty.
+  #define RSS_REG_FIFO_EMPTY_STATUS1_TUPLE_FIFO_EMPTY_E5_SHIFT                                               4
+  #define RSS_REG_FIFO_EMPTY_STATUS1_KEY_HIGH_FIFO_EMPTY_E5                                                  (0x1<<5) // The key_high fifo is empty.
+  #define RSS_REG_FIFO_EMPTY_STATUS1_KEY_HIGH_FIFO_EMPTY_E5_SHIFT                                            5
+  #define RSS_REG_FIFO_EMPTY_STATUS1_KEY_MID_FIFO_EMPTY_E5                                                   (0x1<<6) // The key_mid fifo is empty.
+  #define RSS_REG_FIFO_EMPTY_STATUS1_KEY_MID_FIFO_EMPTY_E5_SHIFT                                             6
+  #define RSS_REG_FIFO_EMPTY_STATUS1_KEY_LOW_FIFO_EMPTY_E5                                                   (0x1<<7) // The key_low fifo is empty.
+  #define RSS_REG_FIFO_EMPTY_STATUS1_KEY_LOW_FIFO_EMPTY_E5_SHIFT                                             7
+  #define RSS_REG_FIFO_EMPTY_STATUS1_INFO_FIFO_EMPTY_E5                                                      (0x1<<8) // The info fifo is empty.
+  #define RSS_REG_FIFO_EMPTY_STATUS1_INFO_FIFO_EMPTY_E5_SHIFT                                                8
+  #define RSS_REG_FIFO_EMPTY_STATUS1_HEADER_FIFO_EMPTY_E5                                                    (0x1<<9) // The header fifo is empty.
+  #define RSS_REG_FIFO_EMPTY_STATUS1_HEADER_FIFO_EMPTY_E5_SHIFT                                              9
+  #define RSS_REG_FIFO_EMPTY_STATUS1_CMD_FIFO_EMPTY_E5                                                       (0x1<<10) // The cmd fifo is empty.
+  #define RSS_REG_FIFO_EMPTY_STATUS1_CMD_FIFO_EMPTY_E5_SHIFT                                                 10
+  #define RSS_REG_FIFO_EMPTY_STATUS1_MSG_FIFO_EMPTY_E5                                                       (0x1<<11) // The msg fifo is empty.
+  #define RSS_REG_FIFO_EMPTY_STATUS1_MSG_FIFO_EMPTY_E5_SHIFT                                                 11
+  #define RSS_REG_FIFO_EMPTY_STATUS1_INP_FIFO_EMPTY_E5                                                       (0x1<<12) // The inp fifo is empty.
+  #define RSS_REG_FIFO_EMPTY_STATUS1_INP_FIFO_EMPTY_E5_SHIFT                                                 12
+#define RSS_REG_COUNTER_STATUS1_E5                                                                           0x238ca0UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define RSS_REG_COUNTER_STATUS1_INP_FIFO_COUNTER_E5                                                        (0xf<<0) // number of valid words in the inp fifo.
+  #define RSS_REG_COUNTER_STATUS1_INP_FIFO_COUNTER_E5_SHIFT                                                  0
+  #define RSS_REG_COUNTER_STATUS1_MSG_FIFO_COUNTER_E5                                                        (0x1f<<4) // number of valid words in the msg fifo.
+  #define RSS_REG_COUNTER_STATUS1_MSG_FIFO_COUNTER_E5_SHIFT                                                  4
+  #define RSS_REG_COUNTER_STATUS1_CMD_FIFO_COUNTER_E5                                                        (0x7<<9) // number of valid words in the cmd fifo.
+  #define RSS_REG_COUNTER_STATUS1_CMD_FIFO_COUNTER_E5_SHIFT                                                  9
+  #define RSS_REG_COUNTER_STATUS1_HEADER_FIFO_COUNTER_E5                                                     (0x3<<12) // number of valid words in the header fifo.
+  #define RSS_REG_COUNTER_STATUS1_HEADER_FIFO_COUNTER_E5_SHIFT                                               12
+  #define RSS_REG_COUNTER_STATUS1_INFO_FIFO_COUNTER_E5                                                       (0x3<<14) // number of valid words in the info fifo.
+  #define RSS_REG_COUNTER_STATUS1_INFO_FIFO_COUNTER_E5_SHIFT                                                 14
+  #define RSS_REG_COUNTER_STATUS1_KEY_LOW_FIFO_COUNTER_E5                                                    (0x3<<16) // number of valid words in the key_low fifo.
+  #define RSS_REG_COUNTER_STATUS1_KEY_LOW_FIFO_COUNTER_E5_SHIFT                                              16
+  #define RSS_REG_COUNTER_STATUS1_KEY_MID_FIFO_COUNTER_E5                                                    (0x3<<18) // number of valid words in the key_mid fifo.
+  #define RSS_REG_COUNTER_STATUS1_KEY_MID_FIFO_COUNTER_E5_SHIFT                                              18
+  #define RSS_REG_COUNTER_STATUS1_KEY_HIGH_FIFO_COUNTER_E5                                                   (0x3<<20) // number of valid words in the key_high fifo.
+  #define RSS_REG_COUNTER_STATUS1_KEY_HIGH_FIFO_COUNTER_E5_SHIFT                                             20
+  #define RSS_REG_COUNTER_STATUS1_TUPLE_FIFO_COUNTER_E5                                                      (0x3<<22) // number of valid words in the tuple fifo.
+  #define RSS_REG_COUNTER_STATUS1_TUPLE_FIFO_COUNTER_E5_SHIFT                                                22
+  #define RSS_REG_COUNTER_STATUS1_HASH_FIFO_COUNTER_E5                                                       (0x3<<24) // number of valid words in the hash fifo.
+  #define RSS_REG_COUNTER_STATUS1_HASH_FIFO_COUNTER_E5_SHIFT                                                 24
+  #define RSS_REG_COUNTER_STATUS1_HASH_TUPLE_FIFO_COUNTER_E5                                                 (0x3<<26) // number of valid words in the hash_tuple fifo.
+  #define RSS_REG_COUNTER_STATUS1_HASH_TUPLE_FIFO_COUNTER_E5_SHIFT                                           26
+  #define RSS_REG_COUNTER_STATUS1_IND_HASH_FIFO_COUNTER_E5                                                   (0x3<<28) // number of valid words in the ind_hash fifo.
+  #define RSS_REG_COUNTER_STATUS1_IND_HASH_FIFO_COUNTER_E5_SHIFT                                             28
+  #define RSS_REG_COUNTER_STATUS1_RSP_FIFO_COUNTER_E5                                                        (0x3<<30) // number of valid words in the rsp fifo.
+  #define RSS_REG_COUNTER_STATUS1_RSP_FIFO_COUNTER_E5_SHIFT                                                  30
+#define RSS_REG_STATE_MACHINES1_E5                                                                           0x238ca4UL //Access:R    DataWidth:0x13   // Multi Field Register.
+  #define RSS_REG_STATE_MACHINES1_INP_PARSE_STATE_E5                                                         (0xf<<0) // inp_parse_state delayed 1 clock (rss_inp.v)
+  #define RSS_REG_STATE_MACHINES1_INP_PARSE_STATE_E5_SHIFT                                                   0
+  #define RSS_REG_STATE_MACHINES1_INP_MEM_STATE_E5                                                           (0xf<<4) // inp_mem_state delayed 1 clock (rss_inp.v)
+  #define RSS_REG_STATE_MACHINES1_INP_MEM_STATE_E5_SHIFT                                                     4
+  #define RSS_REG_STATE_MACHINES1_CALC_STATE_E5                                                              (0x3<<8) // calc_state delayed 1 clock (rss_calc.v)
+  #define RSS_REG_STATE_MACHINES1_CALC_STATE_E5_SHIFT                                                        8
+  #define RSS_REG_STATE_MACHINES1_IND_STATE_E5                                                               (0x7<<10) // ind_state delayed 1 clock (rss_ind.v)
+  #define RSS_REG_STATE_MACHINES1_IND_STATE_E5_SHIFT                                                         10
+  #define RSS_REG_STATE_MACHINES1_CID_STATE_E5                                                               (0x7<<13) // ind_state delayed 1 clock (rss_ind.v)
+  #define RSS_REG_STATE_MACHINES1_CID_STATE_E5_SHIFT                                                         13
+  #define RSS_REG_STATE_MACHINES1_OUT_STATE_E5                                                               (0x7<<16) // out_state delayed 1 clock (rss_out.v)
+  #define RSS_REG_STATE_MACHINES1_OUT_STATE_E5_SHIFT                                                         16
+#define RPB_REG_INT_STS                                                                                      0x23c040UL //Access:R    DataWidth:0x9    // Multi Field Register.
+  #define RPB_REG_INT_STS_ADDRESS_ERROR                                                                      (0x1<<0) // Signals an unknown address to the rf module.
+  #define RPB_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                                0
+  #define RPB_REG_INT_STS_EOP_ERROR                                                                          (0x1<<1) // EOP check error.
+  #define RPB_REG_INT_STS_EOP_ERROR_SHIFT                                                                    1
+  #define RPB_REG_INT_STS_IFIFO_ERROR                                                                        (0x1<<2) // Instruction FIFO error.
+  #define RPB_REG_INT_STS_IFIFO_ERROR_SHIFT                                                                  2
+  #define RPB_REG_INT_STS_PFIFO_ERROR                                                                        (0x1<<3) // Parameter FIFO error.
+  #define RPB_REG_INT_STS_PFIFO_ERROR_SHIFT                                                                  3
+  #define RPB_REG_INT_STS_DB_BUF_ERROR                                                                       (0x1<<4) // DB FIFO error.
+  #define RPB_REG_INT_STS_DB_BUF_ERROR_SHIFT                                                                 4
+  #define RPB_REG_INT_STS_TH_EXEC_ERROR                                                                      (0x1<<5) // 
+  #define RPB_REG_INT_STS_TH_EXEC_ERROR_SHIFT                                                                5
+  #define RPB_REG_INT_STS_TQ_ERROR_WR                                                                        (0x1<<6) // TQ write overflow.
+  #define RPB_REG_INT_STS_TQ_ERROR_WR_SHIFT                                                                  6
+  #define RPB_REG_INT_STS_TQ_ERROR_RD_TH                                                                     (0x1<<7) // TQ read underflow by task handler.
+  #define RPB_REG_INT_STS_TQ_ERROR_RD_TH_SHIFT                                                               7
+  #define RPB_REG_INT_STS_TQ_ERROR_RD_IH                                                                     (0x1<<8) // TQ read underflow by instruction handler.
+  #define RPB_REG_INT_STS_TQ_ERROR_RD_IH_SHIFT                                                               8
+#define RPB_REG_INT_MASK                                                                                     0x23c044UL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define RPB_REG_INT_MASK_ADDRESS_ERROR                                                                     (0x1<<0) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.ADDRESS_ERROR .
+  #define RPB_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                               0
+  #define RPB_REG_INT_MASK_EOP_ERROR                                                                         (0x1<<1) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.EOP_ERROR .
+  #define RPB_REG_INT_MASK_EOP_ERROR_SHIFT                                                                   1
+  #define RPB_REG_INT_MASK_IFIFO_ERROR                                                                       (0x1<<2) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.IFIFO_ERROR .
+  #define RPB_REG_INT_MASK_IFIFO_ERROR_SHIFT                                                                 2
+  #define RPB_REG_INT_MASK_PFIFO_ERROR                                                                       (0x1<<3) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.PFIFO_ERROR .
+  #define RPB_REG_INT_MASK_PFIFO_ERROR_SHIFT                                                                 3
+  #define RPB_REG_INT_MASK_DB_BUF_ERROR                                                                      (0x1<<4) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.DB_BUF_ERROR .
+  #define RPB_REG_INT_MASK_DB_BUF_ERROR_SHIFT                                                                4
+  #define RPB_REG_INT_MASK_TH_EXEC_ERROR                                                                     (0x1<<5) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TH_EXEC_ERROR .
+  #define RPB_REG_INT_MASK_TH_EXEC_ERROR_SHIFT                                                               5
+  #define RPB_REG_INT_MASK_TQ_ERROR_WR                                                                       (0x1<<6) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_WR .
+  #define RPB_REG_INT_MASK_TQ_ERROR_WR_SHIFT                                                                 6
+  #define RPB_REG_INT_MASK_TQ_ERROR_RD_TH                                                                    (0x1<<7) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_RD_TH .
+  #define RPB_REG_INT_MASK_TQ_ERROR_RD_TH_SHIFT                                                              7
+  #define RPB_REG_INT_MASK_TQ_ERROR_RD_IH                                                                    (0x1<<8) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_RD_IH .
+  #define RPB_REG_INT_MASK_TQ_ERROR_RD_IH_SHIFT                                                              8
+#define RPB_REG_INT_STS_WR                                                                                   0x23c048UL //Access:WR   DataWidth:0x9    // Multi Field Register.
+  #define RPB_REG_INT_STS_WR_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define RPB_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                             0
+  #define RPB_REG_INT_STS_WR_EOP_ERROR                                                                       (0x1<<1) // EOP check error.
+  #define RPB_REG_INT_STS_WR_EOP_ERROR_SHIFT                                                                 1
+  #define RPB_REG_INT_STS_WR_IFIFO_ERROR                                                                     (0x1<<2) // Instruction FIFO error.
+  #define RPB_REG_INT_STS_WR_IFIFO_ERROR_SHIFT                                                               2
+  #define RPB_REG_INT_STS_WR_PFIFO_ERROR                                                                     (0x1<<3) // Parameter FIFO error.
+  #define RPB_REG_INT_STS_WR_PFIFO_ERROR_SHIFT                                                               3
+  #define RPB_REG_INT_STS_WR_DB_BUF_ERROR                                                                    (0x1<<4) // DB FIFO error.
+  #define RPB_REG_INT_STS_WR_DB_BUF_ERROR_SHIFT                                                              4
+  #define RPB_REG_INT_STS_WR_TH_EXEC_ERROR                                                                   (0x1<<5) // 
+  #define RPB_REG_INT_STS_WR_TH_EXEC_ERROR_SHIFT                                                             5
+  #define RPB_REG_INT_STS_WR_TQ_ERROR_WR                                                                     (0x1<<6) // TQ write overflow.
+  #define RPB_REG_INT_STS_WR_TQ_ERROR_WR_SHIFT                                                               6
+  #define RPB_REG_INT_STS_WR_TQ_ERROR_RD_TH                                                                  (0x1<<7) // TQ read underflow by task handler.
+  #define RPB_REG_INT_STS_WR_TQ_ERROR_RD_TH_SHIFT                                                            7
+  #define RPB_REG_INT_STS_WR_TQ_ERROR_RD_IH                                                                  (0x1<<8) // TQ read underflow by instruction handler.
+  #define RPB_REG_INT_STS_WR_TQ_ERROR_RD_IH_SHIFT                                                            8
+#define RPB_REG_INT_STS_CLR                                                                                  0x23c04cUL //Access:RC   DataWidth:0x9    // Multi Field Register.
+  #define RPB_REG_INT_STS_CLR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define RPB_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                            0
+  #define RPB_REG_INT_STS_CLR_EOP_ERROR                                                                      (0x1<<1) // EOP check error.
+  #define RPB_REG_INT_STS_CLR_EOP_ERROR_SHIFT                                                                1
+  #define RPB_REG_INT_STS_CLR_IFIFO_ERROR                                                                    (0x1<<2) // Instruction FIFO error.
+  #define RPB_REG_INT_STS_CLR_IFIFO_ERROR_SHIFT                                                              2
+  #define RPB_REG_INT_STS_CLR_PFIFO_ERROR                                                                    (0x1<<3) // Parameter FIFO error.
+  #define RPB_REG_INT_STS_CLR_PFIFO_ERROR_SHIFT                                                              3
+  #define RPB_REG_INT_STS_CLR_DB_BUF_ERROR                                                                   (0x1<<4) // DB FIFO error.
+  #define RPB_REG_INT_STS_CLR_DB_BUF_ERROR_SHIFT                                                             4
+  #define RPB_REG_INT_STS_CLR_TH_EXEC_ERROR                                                                  (0x1<<5) // 
+  #define RPB_REG_INT_STS_CLR_TH_EXEC_ERROR_SHIFT                                                            5
+  #define RPB_REG_INT_STS_CLR_TQ_ERROR_WR                                                                    (0x1<<6) // TQ write overflow.
+  #define RPB_REG_INT_STS_CLR_TQ_ERROR_WR_SHIFT                                                              6
+  #define RPB_REG_INT_STS_CLR_TQ_ERROR_RD_TH                                                                 (0x1<<7) // TQ read underflow by task handler.
+  #define RPB_REG_INT_STS_CLR_TQ_ERROR_RD_TH_SHIFT                                                           7
+  #define RPB_REG_INT_STS_CLR_TQ_ERROR_RD_IH                                                                 (0x1<<8) // TQ read underflow by instruction handler.
+  #define RPB_REG_INT_STS_CLR_TQ_ERROR_RD_IH_SHIFT                                                           8
+#define RPB_REG_PRTY_MASK                                                                                    0x23c054UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define RPB_REG_PRTY_MASK_DATAPATH_REGISTERS                                                               (0x1<<0) // This bit masks, when set, the Parity bit: PB_REG_PRTY_STS.DATAPATH_REGISTERS .
+  #define RPB_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                                         0
+#define RPB_REG_CONTROL                                                                                      0x23c400UL //Access:RW   DataWidth:0xd    // Multi Field Register.
+  #define RPB_REG_CONTROL_BYTE_ORDER_SWITCH                                                                  (0x1<<0) // Indicates if to switch the CRC result byte ordering. 0=don't switch;1=switch.
+  #define RPB_REG_CONTROL_BYTE_ORDER_SWITCH_SHIFT                                                            0
+  #define RPB_REG_CONTROL_DB_IGNORE_ERROR                                                                    (0x1<<1) // Indicates if to ignore the input error indication.
+  #define RPB_REG_CONTROL_DB_IGNORE_ERROR_SHIFT                                                              1
+  #define RPB_REG_CONTROL_DONT_PASS_ERROR                                                                    (0x1<<2) // Masks error on output of pb.
+  #define RPB_REG_CONTROL_DONT_PASS_ERROR_SHIFT                                                              2
+  #define RPB_REG_CONTROL_EOP_CHECK_DISABLE                                                                  (0x1<<3) // Disables EOP check (EOP check verifies that the last Task instruction is accessing a line that has EOP on it. this way one could find mismatches between expected length and actual length on some packet.
+  #define RPB_REG_CONTROL_EOP_CHECK_DISABLE_SHIFT                                                            3
+  #define RPB_REG_CONTROL_CRC_COMPARE_DISABLE                                                                (0x1<<4) // Disables CRC2 machine (the machine that is used for comparing actual CRC with a value that is provided to the PB.
+  #define RPB_REG_CONTROL_CRC_COMPARE_DISABLE_SHIFT                                                          4
+  #define RPB_REG_CONTROL_EN_INPUTS                                                                          (0x1<<5) // Enable inputs.
+  #define RPB_REG_CONTROL_EN_INPUTS_SHIFT                                                                    5
+  #define RPB_REG_CONTROL_DISABLE_PB                                                                         (0x1<<6) // Debug only: Disable PB.
+  #define RPB_REG_CONTROL_DISABLE_PB_SHIFT                                                                   6
+  #define RPB_REG_CONTROL_DEBUG_SELECT                                                                       (0xf<<7) // Obsolete.
+  #define RPB_REG_CONTROL_DEBUG_SELECT_SHIFT                                                                 7
+  #define RPB_REG_CONTROL_RELAX_TH                                                                           (0x1<<11) // Dbug only.
+  #define RPB_REG_CONTROL_RELAX_TH_SHIFT                                                                     11
+  #define RPB_REG_CONTROL_DUMMY_ERR_ALLOW                                                                    (0x1<<12) // Dummy ingress error allow.  When cleared, an error received on the ingress interface will be masked for instructions in which the "dummy read" bit is set.
+  #define RPB_REG_CONTROL_DUMMY_ERR_ALLOW_SHIFT                                                              12
+#define RPB_REG_CRC_MASK_1_0                                                                                 0x23c404UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define RPB_REG_CRC_MASK_1_1                                                                                 0x23c408UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define RPB_REG_CRC_MASK_1_2                                                                                 0x23c40cUL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define RPB_REG_CRC_MASK_1_3                                                                                 0x23c410UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define RPB_REG_CRC_MASK_2_0                                                                                 0x23c414UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define RPB_REG_CRC_MASK_2_1                                                                                 0x23c418UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define RPB_REG_CRC_MASK_2_2                                                                                 0x23c41cUL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define RPB_REG_CRC_MASK_2_3                                                                                 0x23c420UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define RPB_REG_CRC_MASK_3_0                                                                                 0x23c424UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define RPB_REG_CRC_MASK_3_1                                                                                 0x23c428UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define RPB_REG_CRC_MASK_3_2                                                                                 0x23c42cUL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define RPB_REG_CRC_MASK_3_3                                                                                 0x23c430UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define RPB_REG_DB_EMPTY                                                                                     0x23c500UL //Access:R    DataWidth:0x1    // Data Buffer empty status.
+#define RPB_REG_DB_FULL                                                                                      0x23c504UL //Access:R    DataWidth:0x1    // Data Buffer full status.
+#define RPB_REG_TQ_EMPTY                                                                                     0x23c508UL //Access:R    DataWidth:0x1    // Task Queue empty status.
+#define RPB_REG_TQ_FULL                                                                                      0x23c50cUL //Access:R    DataWidth:0x1    // Task Queue full status.
+#define RPB_REG_IFIFO_EMPTY                                                                                  0x23c510UL //Access:R    DataWidth:0x1    // Instruction FIFO empty status.
+#define RPB_REG_IFIFO_FULL                                                                                   0x23c514UL //Access:R    DataWidth:0x1    // Instruction FIFO full status.
+#define RPB_REG_PFIFO_EMPTY                                                                                  0x23c518UL //Access:R    DataWidth:0x1    // Parameter FIFO empty status.
+#define RPB_REG_PFIFO_FULL                                                                                   0x23c51cUL //Access:R    DataWidth:0x1    // Parameter FIFO full status.
+#define RPB_REG_TQ_TH_EMPTY                                                                                  0x23c520UL //Access:R    DataWidth:0x1    // Task Queue empty status for task handler.
+#define RPB_REG_ERRORED_CRC                                                                                  0x23c600UL //Access:R    DataWidth:0x20   // CRC mismatch debug register.  This register stores the calculated CRC value that resulted in the most recent CRC error event.
+#define RPB_REG_ERRORED_INSTR                                                                                0x23c604UL //Access:R    DataWidth:0x20   // EOP mismatch debug register.  Use this address to read the instruction being executed at the time EOP error is detected. The instruction is aligned with the least significant bit of this register.  Bits 31:29 provide additional information about the instruction.  Bit 31 indicates whether the instruction is valid.  Bit 30 indicates if the instruction is the first instruction in the task.  Bit 29 indicates whether the instruction is the last instruction in the task.
+#define RPB_REG_ERRORED_HDR_LOW                                                                              0x23c608UL //Access:R    DataWidth:0x20   // EOP mismatch debug register.  Use this address to read the lower 32 bits of the task header being executed at the time EOP error is detected.  The instruction length is not kept and is read as 0.
+#define RPB_REG_ERRORED_HDR_HIGH                                                                             0x23c60cUL //Access:R    DataWidth:0x20   // EOP mismatch debug register.  Use this address to read the upper 32 bits of the task header being executed at the time EOP error is detected.  The task passthrough bit is not kept and is read as 0.
+#define RPB_REG_ERRORED_LENGTH                                                                               0x23c610UL //Access:R    DataWidth:0x10   // EOP mismatch debug register.  This register provides the number of data bytes remaining to be read from DB at the time of EOP error detection.
+#define RPB_REG_ECO_RESERVED                                                                                 0x23c614UL //Access:RW   DataWidth:0x8    // For future eco.
+#define RPB_REG_DBG_OUT_DATA                                                                                 0x23c700UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define RPB_REG_DBG_OUT_DATA_SIZE                                                                            8
+#define RPB_REG_DBG_OUT_VALID                                                                                0x23c720UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define RPB_REG_DBG_OUT_FRAME                                                                                0x23c724UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define RPB_REG_DBG_SELECT                                                                                   0x23c728UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define RPB_REG_DBG_DWORD_ENABLE                                                                             0x23c72cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define RPB_REG_DBG_SHIFT                                                                                    0x23c730UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define RPB_REG_DBG_FORCE_VALID                                                                              0x23c734UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define RPB_REG_DBG_FORCE_FRAME                                                                              0x23c738UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define RPB_REG_DB_FIFO                                                                                      0x23e000UL //Access:WB_R DataWidth:0x108  // Provides read-only access of the data buffer FIFO. Intended for debug purposes.
+#define RPB_REG_DB_FIFO_SIZE                                                                                 512
+#define RPB_REG_L1                                                                                           0x23f000UL //Access:WB   DataWidth:0x40   // L1 CRC memory access.
+#define RPB_REG_L1_SIZE                                                                                      640
+#define PSWRQ2_REG_RBC_DONE                                                                                  0x240000UL //Access:RW   DataWidth:0x1    // Driver should write 1 to this register in order to signal the PSWRQ block to start initializing internal memories.
+#define PSWRQ2_REG_CFG_DONE                                                                                  0x240004UL //Access:R    DataWidth:0x1    // PSWRQ internal memories initialization is done. Driver should check this register is 1 some time after writing 1 to rbc_done register.
+#define PSWRQ2_REG_RESET_STT                                                                                 0x240008UL //Access:RW   DataWidth:0x1    // MCP writes '1' to this bit to indicate PSWRQ to initialize Steering Tag Table with zeros. PSWRQ clears this bit when the initialization is done. MCP can use this register the same as it uses IGU reset_memories register.
+#define PSWRQ2_REG_CDUT_P_SIZE                                                                               0x24000cUL //Access:RW   DataWidth:0x4    // Page size in L2P table for CDU-Task module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M.
+#define PSWRQ2_REG_CDUC_P_SIZE                                                                               0x240010UL //Access:RW   DataWidth:0x4    // Page size in L2P table for CDU module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M.
+#define PSWRQ2_REG_TM_P_SIZE                                                                                 0x240014UL //Access:RW   DataWidth:0x4    // Page size in L2P table for TM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M.
+#define PSWRQ2_REG_QM_P_SIZE                                                                                 0x240018UL //Access:RW   DataWidth:0x4    // Page size in L2P table for QM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M.
+#define PSWRQ2_REG_SRC_P_SIZE                                                                                0x24001cUL //Access:RW   DataWidth:0x4    // Page size in L2P table for SRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M.
+#define PSWRQ2_REG_DBG_P_SIZE                                                                                0x240020UL //Access:RW   DataWidth:0x4    // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M.
+#define PSWRQ2_REG_XSDM_P_SIZE                                                                               0x240024UL //Access:RW   DataWidth:0x4    // Page size in L2P table for SRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M.
+#define PSWRQ2_REG_TSDM_P_SIZE                                                                               0x240028UL //Access:RW   DataWidth:0x4    // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M.
+#define PSWRQ2_REG_USDM_P_SIZE                                                                               0x24002cUL //Access:RW   DataWidth:0x4    // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M.
+#define PSWRQ2_REG_TM_FIRST_ILT                                                                              0x240030UL //Access:RW   DataWidth:0xe    // First memory address base for tm in ILT.
+#define PSWRQ2_REG_TM_LAST_ILT                                                                               0x240034UL //Access:RW   DataWidth:0xe    // Last memory address base for tm in ILT.
+#define PSWRQ2_REG_QM_FIRST_ILT                                                                              0x240038UL //Access:RW   DataWidth:0xe    // First memory address base for qm in ILT.
+#define PSWRQ2_REG_QM_LAST_ILT                                                                               0x24003cUL //Access:RW   DataWidth:0xe    // Last memory address base for qm in ILT.
+#define PSWRQ2_REG_SRC_FIRST_ILT                                                                             0x240040UL //Access:RW   DataWidth:0xe    // First memory address base for src in ILT.
+#define PSWRQ2_REG_SRC_LAST_ILT                                                                              0x240044UL //Access:RW   DataWidth:0xe    // Last memory address base for src in ILT.
+#define PSWRQ2_REG_CDUC_FIRST_ILT                                                                            0x240048UL //Access:RW   DataWidth:0xe    // First memory address base for cdu-connection in ILT.
+#define PSWRQ2_REG_CDUC_LAST_ILT                                                                             0x24004cUL //Access:RW   DataWidth:0xe    // Last memory address base for cdu-connection in ILT.
+#define PSWRQ2_REG_CDUT_FIRST_ILT                                                                            0x240050UL //Access:RW   DataWidth:0xe    // First memory address base for cdu-task in ILT.
+#define PSWRQ2_REG_CDUT_LAST_ILT                                                                             0x240054UL //Access:RW   DataWidth:0xe    // Last memory address base for cdu-task in ILT.
+#define PSWRQ2_REG_XSDM_FIRST_ILT                                                                            0x240058UL //Access:RW   DataWidth:0xe    // First memory address base for xsdm in ILT.
+#define PSWRQ2_REG_XSDM_LAST_ILT                                                                             0x24005cUL //Access:RW   DataWidth:0xe    // Last memory address base for xsdm in ILT.
+#define PSWRQ2_REG_TSDM_FIRST_ILT                                                                            0x240060UL //Access:RW   DataWidth:0xe    // First memory address base for tsdm in ILT.
+#define PSWRQ2_REG_TSDM_LAST_ILT                                                                             0x240064UL //Access:RW   DataWidth:0xe    // Last memory address base for tsdm in ILT.
+#define PSWRQ2_REG_USDM_FIRST_ILT                                                                            0x240068UL //Access:RW   DataWidth:0xe    // First memory address base for usdm in ILT.
+#define PSWRQ2_REG_USDM_LAST_ILT                                                                             0x24006cUL //Access:RW   DataWidth:0xe    // Last memory address base for usdm in ILT.
+#define PSWRQ2_REG_DBG_FIRST_ILT                                                                             0x240070UL //Access:RW   DataWidth:0xe    // First memory address base for dbg in ILT.
+#define PSWRQ2_REG_DBG_LAST_ILT                                                                              0x240074UL //Access:RW   DataWidth:0xe    // Last memory address base for dbg in ILT.
+#define PSWRQ2_REG_ENDIANITY_00                                                                              0x240078UL //Access:RW   DataWidth:0x2    // Requests from all SDM's and DMAE with endian mode 0 will receive the endian mode indicated here.
+#define PSWRQ2_REG_ENDIANITY_01                                                                              0x24007cUL //Access:RW   DataWidth:0x2    // Requests from all SDM's and DMAE with endian mode 1 will receive the endian mode indicated here.
+#define PSWRQ2_REG_ENDIANITY_02                                                                              0x240080UL //Access:RW   DataWidth:0x2    // Requests from all SDM's and DMAE with endian mode 2 will receive the endian mode indicated here.
+#define PSWRQ2_REG_ENDIANITY_03                                                                              0x240084UL //Access:RW   DataWidth:0x2    // Requests from all SDM's and DMAE with endian mode 3 will receive the endian mode indicated here.
+#define PSWRQ2_REG_PTU_ENDIAN_M                                                                              0x240088UL //Access:RW   DataWidth:0x2    // Endian mode for ptu.
+#define PSWRQ2_REG_M2P_ENDIAN_M                                                                              0x24008cUL //Access:RW   DataWidth:0x2    // Endian mode for m2p.
+#define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS                                                                    0x240090UL //Access:RW   DataWidth:0x10   // Number of ILT PF blocks.
+#define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS                                                                  0x240094UL //Access:RW   DataWidth:0x10   // Number of ILT PF blocks.
+#define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS                                                                  0x240098UL //Access:RW   DataWidth:0x10   // Number of ILT PF blocks.
+#define PSWRQ2_REG_TM_VF_BLOCKS                                                                              0x24009cUL //Access:RW   DataWidth:0x8    // Number of ILT VF blocks.
+#define PSWRQ2_REG_CDUT_VF_BLOCKS                                                                            0x2400a0UL //Access:RW   DataWidth:0x8    // Number of ILT VF blocks.
+#define PSWRQ2_REG_CDUC_VF_BLOCKS                                                                            0x2400a4UL //Access:RW   DataWidth:0x8    // Number of ILT VF blocks.
+#define PSWRQ2_REG_TM_BLOCKS_FACTOR                                                                          0x2400a8UL //Access:RW   DataWidth:0x4    // ILT blocks factor.
+#define PSWRQ2_REG_CDUT_BLOCKS_FACTOR                                                                        0x2400acUL //Access:RW   DataWidth:0x4    // ILT blocks factor.
+#define PSWRQ2_REG_CDUC_BLOCKS_FACTOR                                                                        0x2400b0UL //Access:RW   DataWidth:0x4    // ILT blocks factor.
+#define PSWRQ2_REG_VF_BASE                                                                                   0x2400b4UL //Access:RW   DataWidth:0x8    // First VF assigned to this PF. Used for ILT for VFs calculations.
+#define PSWRQ2_REG_VF_LAST_ILT                                                                               0x2400b8UL //Access:RW   DataWidth:0x8    // VF LAST
+#define PSWRQ2_REG_DBG_OUT_DATA                                                                              0x2400e0UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PSWRQ2_REG_DBG_OUT_DATA_SIZE                                                                         8
+#define PSWRQ2_REG_DBG_SELECT                                                                                0x240100UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PSWRQ2_REG_DBG_DWORD_ENABLE                                                                          0x240104UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PSWRQ2_REG_DBG_SHIFT                                                                                 0x240108UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PSWRQ2_REG_DBG_FORCE_VALID                                                                           0x24010cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PSWRQ2_REG_DBG_FORCE_FRAME                                                                           0x240110UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PSWRQ2_REG_DBG_OUT_VALID                                                                             0x240114UL //Access:R    DataWidth:0x4    // Dbgmux output valid
+#define PSWRQ2_REG_DBG_OUT_FRAME                                                                             0x240118UL //Access:R    DataWidth:0x4    // Dbgmux output frame
+#define PSWRQ2_REG_INT_STS                                                                                   0x240180UL //Access:R    DataWidth:0xf    // Multi Field Register.
+  #define PSWRQ2_REG_INT_STS_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSWRQ2_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                             0
+  #define PSWRQ2_REG_INT_STS_L2P_FIFO_OVERFLOW                                                               (0x1<<1) // Overflow in l2p input fifo - hard wired to 0 in E4.
+  #define PSWRQ2_REG_INT_STS_L2P_FIFO_OVERFLOW_SHIFT                                                         1
+  #define PSWRQ2_REG_INT_STS_WDFIFO_OVERFLOW                                                                 (0x1<<2) // Overflow in src write done fifo.
+  #define PSWRQ2_REG_INT_STS_WDFIFO_OVERFLOW_SHIFT                                                           2
+  #define PSWRQ2_REG_INT_STS_PHYADDR_FIFO_OF                                                                 (0x1<<3) // Overflow of phy addr fifo - removed in E4.
+  #define PSWRQ2_REG_INT_STS_PHYADDR_FIFO_OF_SHIFT                                                           3
+  #define PSWRQ2_REG_INT_STS_L2P_VIOLATION_1                                                                 (0x1<<4) // Translation page pointer is bigger than 15 - hard wired to 0 in E4.
+  #define PSWRQ2_REG_INT_STS_L2P_VIOLATION_1_SHIFT                                                           4
+  #define PSWRQ2_REG_INT_STS_L2P_VIOLATION_2                                                                 (0x1<<5) // Vah+elt_first_index is bigger than page size - hard wired to 0 in E4.
+  #define PSWRQ2_REG_INT_STS_L2P_VIOLATION_2_SHIFT                                                           5
+  #define PSWRQ2_REG_INT_STS_FREE_LIST_EMPTY                                                                 (0x1<<6) // If this interrupt occurs then an entry in the cxr_ram was overwritten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset.
+  #define PSWRQ2_REG_INT_STS_FREE_LIST_EMPTY_SHIFT                                                           6
+  #define PSWRQ2_REG_INT_STS_ELT_ADDR                                                                        (0x1<<7) // Indicates that onchip translation did not succeed in ILT mode (in ILT mode all onchip translation MUST succeed).
+  #define PSWRQ2_REG_INT_STS_ELT_ADDR_SHIFT                                                                  7
+  #define PSWRQ2_REG_INT_STS_L2P_VF_ERR                                                                      (0x1<<8) // E4: Indicates a request with: 1. Logical address. 2. Function is a VF. 3. Client is NOT (TM;CDU).
+  #define PSWRQ2_REG_INT_STS_L2P_VF_ERR_SHIFT                                                                8
+  #define PSWRQ2_REG_INT_STS_CORE_WDONE_OVERFLOW                                                             (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue.
+  #define PSWRQ2_REG_INT_STS_CORE_WDONE_OVERFLOW_SHIFT                                                       9
+  #define PSWRQ2_REG_INT_STS_TREQ_FIFO_UNDERFLOW                                                             (0x1<<10) // Underflwoing the treq fifo.
+  #define PSWRQ2_REG_INT_STS_TREQ_FIFO_UNDERFLOW_SHIFT                                                       10
+  #define PSWRQ2_REG_INT_STS_TREQ_FIFO_OVERFLOW                                                              (0x1<<11) // Overflwoing the treq fifo.
+  #define PSWRQ2_REG_INT_STS_TREQ_FIFO_OVERFLOW_SHIFT                                                        11
+  #define PSWRQ2_REG_INT_STS_ICPL_FIFO_UNDERFLOW                                                             (0x1<<12) // Underflwoing the icpl fifo.
+  #define PSWRQ2_REG_INT_STS_ICPL_FIFO_UNDERFLOW_SHIFT                                                       12
+  #define PSWRQ2_REG_INT_STS_ICPL_FIFO_OVERFLOW                                                              (0x1<<13) // Overflwoing the icpl fifo.
+  #define PSWRQ2_REG_INT_STS_ICPL_FIFO_OVERFLOW_SHIFT                                                        13
+  #define PSWRQ2_REG_INT_STS_BACK2BACK_ATC_RESPONSE                                                          (0x1<<14) // 2 consecutive atc responses are not allowed.
+  #define PSWRQ2_REG_INT_STS_BACK2BACK_ATC_RESPONSE_SHIFT                                                    14
+#define PSWRQ2_REG_INT_MASK                                                                                  0x240184UL //Access:RW   DataWidth:0xf    // Multi Field Register.
+  #define PSWRQ2_REG_INT_MASK_ADDRESS_ERROR                                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.ADDRESS_ERROR .
+  #define PSWRQ2_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                            0
+  #define PSWRQ2_REG_INT_MASK_L2P_FIFO_OVERFLOW                                                              (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.L2P_FIFO_OVERFLOW .
+  #define PSWRQ2_REG_INT_MASK_L2P_FIFO_OVERFLOW_SHIFT                                                        1
+  #define PSWRQ2_REG_INT_MASK_WDFIFO_OVERFLOW                                                                (0x1<<2) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.WDFIFO_OVERFLOW .
+  #define PSWRQ2_REG_INT_MASK_WDFIFO_OVERFLOW_SHIFT                                                          2
+  #define PSWRQ2_REG_INT_MASK_PHYADDR_FIFO_OF                                                                (0x1<<3) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.PHYADDR_FIFO_OF .
+  #define PSWRQ2_REG_INT_MASK_PHYADDR_FIFO_OF_SHIFT                                                          3
+  #define PSWRQ2_REG_INT_MASK_L2P_VIOLATION_1                                                                (0x1<<4) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.L2P_VIOLATION_1 .
+  #define PSWRQ2_REG_INT_MASK_L2P_VIOLATION_1_SHIFT                                                          4
+  #define PSWRQ2_REG_INT_MASK_L2P_VIOLATION_2                                                                (0x1<<5) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.L2P_VIOLATION_2 .
+  #define PSWRQ2_REG_INT_MASK_L2P_VIOLATION_2_SHIFT                                                          5
+  #define PSWRQ2_REG_INT_MASK_FREE_LIST_EMPTY                                                                (0x1<<6) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.FREE_LIST_EMPTY .
+  #define PSWRQ2_REG_INT_MASK_FREE_LIST_EMPTY_SHIFT                                                          6
+  #define PSWRQ2_REG_INT_MASK_ELT_ADDR                                                                       (0x1<<7) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.ELT_ADDR .
+  #define PSWRQ2_REG_INT_MASK_ELT_ADDR_SHIFT                                                                 7
+  #define PSWRQ2_REG_INT_MASK_L2P_VF_ERR                                                                     (0x1<<8) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.L2P_VF_ERR .
+  #define PSWRQ2_REG_INT_MASK_L2P_VF_ERR_SHIFT                                                               8
+  #define PSWRQ2_REG_INT_MASK_CORE_WDONE_OVERFLOW                                                            (0x1<<9) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.CORE_WDONE_OVERFLOW .
+  #define PSWRQ2_REG_INT_MASK_CORE_WDONE_OVERFLOW_SHIFT                                                      9
+  #define PSWRQ2_REG_INT_MASK_TREQ_FIFO_UNDERFLOW                                                            (0x1<<10) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.TREQ_FIFO_UNDERFLOW .
+  #define PSWRQ2_REG_INT_MASK_TREQ_FIFO_UNDERFLOW_SHIFT                                                      10
+  #define PSWRQ2_REG_INT_MASK_TREQ_FIFO_OVERFLOW                                                             (0x1<<11) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.TREQ_FIFO_OVERFLOW .
+  #define PSWRQ2_REG_INT_MASK_TREQ_FIFO_OVERFLOW_SHIFT                                                       11
+  #define PSWRQ2_REG_INT_MASK_ICPL_FIFO_UNDERFLOW                                                            (0x1<<12) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.ICPL_FIFO_UNDERFLOW .
+  #define PSWRQ2_REG_INT_MASK_ICPL_FIFO_UNDERFLOW_SHIFT                                                      12
+  #define PSWRQ2_REG_INT_MASK_ICPL_FIFO_OVERFLOW                                                             (0x1<<13) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.ICPL_FIFO_OVERFLOW .
+  #define PSWRQ2_REG_INT_MASK_ICPL_FIFO_OVERFLOW_SHIFT                                                       13
+  #define PSWRQ2_REG_INT_MASK_BACK2BACK_ATC_RESPONSE                                                         (0x1<<14) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.BACK2BACK_ATC_RESPONSE .
+  #define PSWRQ2_REG_INT_MASK_BACK2BACK_ATC_RESPONSE_SHIFT                                                   14
+#define PSWRQ2_REG_INT_STS_WR                                                                                0x240188UL //Access:WR   DataWidth:0xf    // Multi Field Register.
+  #define PSWRQ2_REG_INT_STS_WR_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSWRQ2_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                          0
+  #define PSWRQ2_REG_INT_STS_WR_L2P_FIFO_OVERFLOW                                                            (0x1<<1) // Overflow in l2p input fifo - hard wired to 0 in E4.
+  #define PSWRQ2_REG_INT_STS_WR_L2P_FIFO_OVERFLOW_SHIFT                                                      1
+  #define PSWRQ2_REG_INT_STS_WR_WDFIFO_OVERFLOW                                                              (0x1<<2) // Overflow in src write done fifo.
+  #define PSWRQ2_REG_INT_STS_WR_WDFIFO_OVERFLOW_SHIFT                                                        2
+  #define PSWRQ2_REG_INT_STS_WR_PHYADDR_FIFO_OF                                                              (0x1<<3) // Overflow of phy addr fifo - removed in E4.
+  #define PSWRQ2_REG_INT_STS_WR_PHYADDR_FIFO_OF_SHIFT                                                        3
+  #define PSWRQ2_REG_INT_STS_WR_L2P_VIOLATION_1                                                              (0x1<<4) // Translation page pointer is bigger than 15 - hard wired to 0 in E4.
+  #define PSWRQ2_REG_INT_STS_WR_L2P_VIOLATION_1_SHIFT                                                        4
+  #define PSWRQ2_REG_INT_STS_WR_L2P_VIOLATION_2                                                              (0x1<<5) // Vah+elt_first_index is bigger than page size - hard wired to 0 in E4.
+  #define PSWRQ2_REG_INT_STS_WR_L2P_VIOLATION_2_SHIFT                                                        5
+  #define PSWRQ2_REG_INT_STS_WR_FREE_LIST_EMPTY                                                              (0x1<<6) // If this interrupt occurs then an entry in the cxr_ram was overwritten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset.
+  #define PSWRQ2_REG_INT_STS_WR_FREE_LIST_EMPTY_SHIFT                                                        6
+  #define PSWRQ2_REG_INT_STS_WR_ELT_ADDR                                                                     (0x1<<7) // Indicates that onchip translation did not succeed in ILT mode (in ILT mode all onchip translation MUST succeed).
+  #define PSWRQ2_REG_INT_STS_WR_ELT_ADDR_SHIFT                                                               7
+  #define PSWRQ2_REG_INT_STS_WR_L2P_VF_ERR                                                                   (0x1<<8) // E4: Indicates a request with: 1. Logical address. 2. Function is a VF. 3. Client is NOT (TM;CDU).
+  #define PSWRQ2_REG_INT_STS_WR_L2P_VF_ERR_SHIFT                                                             8
+  #define PSWRQ2_REG_INT_STS_WR_CORE_WDONE_OVERFLOW                                                          (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue.
+  #define PSWRQ2_REG_INT_STS_WR_CORE_WDONE_OVERFLOW_SHIFT                                                    9
+  #define PSWRQ2_REG_INT_STS_WR_TREQ_FIFO_UNDERFLOW                                                          (0x1<<10) // Underflwoing the treq fifo.
+  #define PSWRQ2_REG_INT_STS_WR_TREQ_FIFO_UNDERFLOW_SHIFT                                                    10
+  #define PSWRQ2_REG_INT_STS_WR_TREQ_FIFO_OVERFLOW                                                           (0x1<<11) // Overflwoing the treq fifo.
+  #define PSWRQ2_REG_INT_STS_WR_TREQ_FIFO_OVERFLOW_SHIFT                                                     11
+  #define PSWRQ2_REG_INT_STS_WR_ICPL_FIFO_UNDERFLOW                                                          (0x1<<12) // Underflwoing the icpl fifo.
+  #define PSWRQ2_REG_INT_STS_WR_ICPL_FIFO_UNDERFLOW_SHIFT                                                    12
+  #define PSWRQ2_REG_INT_STS_WR_ICPL_FIFO_OVERFLOW                                                           (0x1<<13) // Overflwoing the icpl fifo.
+  #define PSWRQ2_REG_INT_STS_WR_ICPL_FIFO_OVERFLOW_SHIFT                                                     13
+  #define PSWRQ2_REG_INT_STS_WR_BACK2BACK_ATC_RESPONSE                                                       (0x1<<14) // 2 consecutive atc responses are not allowed.
+  #define PSWRQ2_REG_INT_STS_WR_BACK2BACK_ATC_RESPONSE_SHIFT                                                 14
+#define PSWRQ2_REG_INT_STS_CLR                                                                               0x24018cUL //Access:RC   DataWidth:0xf    // Multi Field Register.
+  #define PSWRQ2_REG_INT_STS_CLR_ADDRESS_ERROR                                                               (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSWRQ2_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                         0
+  #define PSWRQ2_REG_INT_STS_CLR_L2P_FIFO_OVERFLOW                                                           (0x1<<1) // Overflow in l2p input fifo - hard wired to 0 in E4.
+  #define PSWRQ2_REG_INT_STS_CLR_L2P_FIFO_OVERFLOW_SHIFT                                                     1
+  #define PSWRQ2_REG_INT_STS_CLR_WDFIFO_OVERFLOW                                                             (0x1<<2) // Overflow in src write done fifo.
+  #define PSWRQ2_REG_INT_STS_CLR_WDFIFO_OVERFLOW_SHIFT                                                       2
+  #define PSWRQ2_REG_INT_STS_CLR_PHYADDR_FIFO_OF                                                             (0x1<<3) // Overflow of phy addr fifo - removed in E4.
+  #define PSWRQ2_REG_INT_STS_CLR_PHYADDR_FIFO_OF_SHIFT                                                       3
+  #define PSWRQ2_REG_INT_STS_CLR_L2P_VIOLATION_1                                                             (0x1<<4) // Translation page pointer is bigger than 15 - hard wired to 0 in E4.
+  #define PSWRQ2_REG_INT_STS_CLR_L2P_VIOLATION_1_SHIFT                                                       4
+  #define PSWRQ2_REG_INT_STS_CLR_L2P_VIOLATION_2                                                             (0x1<<5) // Vah+elt_first_index is bigger than page size - hard wired to 0 in E4.
+  #define PSWRQ2_REG_INT_STS_CLR_L2P_VIOLATION_2_SHIFT                                                       5
+  #define PSWRQ2_REG_INT_STS_CLR_FREE_LIST_EMPTY                                                             (0x1<<6) // If this interrupt occurs then an entry in the cxr_ram was overwritten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset.
+  #define PSWRQ2_REG_INT_STS_CLR_FREE_LIST_EMPTY_SHIFT                                                       6
+  #define PSWRQ2_REG_INT_STS_CLR_ELT_ADDR                                                                    (0x1<<7) // Indicates that onchip translation did not succeed in ILT mode (in ILT mode all onchip translation MUST succeed).
+  #define PSWRQ2_REG_INT_STS_CLR_ELT_ADDR_SHIFT                                                              7
+  #define PSWRQ2_REG_INT_STS_CLR_L2P_VF_ERR                                                                  (0x1<<8) // E4: Indicates a request with: 1. Logical address. 2. Function is a VF. 3. Client is NOT (TM;CDU).
+  #define PSWRQ2_REG_INT_STS_CLR_L2P_VF_ERR_SHIFT                                                            8
+  #define PSWRQ2_REG_INT_STS_CLR_CORE_WDONE_OVERFLOW                                                         (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue.
+  #define PSWRQ2_REG_INT_STS_CLR_CORE_WDONE_OVERFLOW_SHIFT                                                   9
+  #define PSWRQ2_REG_INT_STS_CLR_TREQ_FIFO_UNDERFLOW                                                         (0x1<<10) // Underflwoing the treq fifo.
+  #define PSWRQ2_REG_INT_STS_CLR_TREQ_FIFO_UNDERFLOW_SHIFT                                                   10
+  #define PSWRQ2_REG_INT_STS_CLR_TREQ_FIFO_OVERFLOW                                                          (0x1<<11) // Overflwoing the treq fifo.
+  #define PSWRQ2_REG_INT_STS_CLR_TREQ_FIFO_OVERFLOW_SHIFT                                                    11
+  #define PSWRQ2_REG_INT_STS_CLR_ICPL_FIFO_UNDERFLOW                                                         (0x1<<12) // Underflwoing the icpl fifo.
+  #define PSWRQ2_REG_INT_STS_CLR_ICPL_FIFO_UNDERFLOW_SHIFT                                                   12
+  #define PSWRQ2_REG_INT_STS_CLR_ICPL_FIFO_OVERFLOW                                                          (0x1<<13) // Overflwoing the icpl fifo.
+  #define PSWRQ2_REG_INT_STS_CLR_ICPL_FIFO_OVERFLOW_SHIFT                                                    13
+  #define PSWRQ2_REG_INT_STS_CLR_BACK2BACK_ATC_RESPONSE                                                      (0x1<<14) // 2 consecutive atc responses are not allowed.
+  #define PSWRQ2_REG_INT_STS_CLR_BACK2BACK_ATC_RESPONSE_SHIFT                                                14
+#define PSWRQ2_REG_PRTY_MASK_H_0                                                                             0x240204UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT                                                       (0x1<<0) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT .
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_SHIFT                                                 0
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_K2_E5                                                 (0x1<<1) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT .
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_K2_E5_SHIFT                                           1
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB                                                    (0x1<<1) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_SHIFT                                              1
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_K2_E5                                                 (0x1<<2) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_K2_E5_SHIFT                                           2
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB                                                      (0x1<<8) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_SHIFT                                                8
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_E5                                                   (0x1<<3) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_E5_SHIFT                                             3
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY                                                         (0x1<<4) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_SHIFT                                                   4
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB                                                      (0x1<<7) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_SHIFT                                                7
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2_E5                                                   (0x1<<5) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2_E5_SHIFT                                             5
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB                                                      (0x1<<5) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_SHIFT                                                5
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_E5                                                   (0x1<<6) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_E5_SHIFT                                             6
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB                                                      (0x1<<6) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_SHIFT                                                6
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_E5                                                   (0x1<<7) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_E5_SHIFT                                             7
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2_E5                                                   (0x1<<8) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2_E5_SHIFT                                             8
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB                                                      (0x1<<3) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_SHIFT                                                3
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_E5                                                   (0x1<<9) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_E5_SHIFT                                             9
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB                                                      (0x1<<2) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define PSWRQ2_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_SHIFT                                                2
+#define PSWRQ2_REG_MEM004_RF_ECC_ERROR_CONNECT                                                               0x240210UL //Access:W    DataWidth:0xe    // Register to generate up to two ECC errors on the next write to memory: pswrq.i_l2p_table.rf_ecc_error_connect Includes 2 words of 7 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 53. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define PSWRQ2_REG_MEM005_RF_ECC_ERROR_CONNECT_K2_E5                                                         0x240214UL //Access:W    DataWidth:0xe    // Register to generate up to two ECC errors on the next write to memory: pswrq.i_l2p_table_high.rf_ecc_error_connect Includes 2 words of 7 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 53. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define PSWRQ2_REG_MEM_ECC_ENABLE_0_BB                                                                       0x240214UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+#define PSWRQ2_REG_MEM_ECC_ENABLE_0_K2_E5                                                                    0x240218UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN                                                        (0x1<<0) // Enable ECC for memory ecc instance pswrq.i_l2p_table.i_ecc in module pswrq_mem_l2p_table
+  #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_SHIFT                                                  0
+  #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_K2_E5                                                  (0x1<<1) // Enable ECC for memory ecc instance pswrq.i_l2p_table_high.i_ecc in module pswrq_mem_l2p_table
+  #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_K2_E5_SHIFT                                            1
+  #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_BB                                                     (0x1<<1) // Enable ECC for memory ecc instance pswrq.i_cxr_ram1.i_ecc in module pswrq_mem_cxr_ram1
+  #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_BB_SHIFT                                               1
+  #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_K2_E5                                                  (0x1<<2) // Enable ECC for memory ecc instance pswrq.i_cxr_ram1.i_ecc in module pswrq_mem_cxr_ram1
+  #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_K2_E5_SHIFT                                            2
+#define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_BB                                                                  0x240218UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+#define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_K2_E5                                                               0x24021cUL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY                                                 (0x1<<0) // Set parity only for memory ecc instance pswrq.i_l2p_table.i_ecc in module pswrq_mem_l2p_table
+  #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_SHIFT                                           0
+  #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_K2_E5                                           (0x1<<1) // Set parity only for memory ecc instance pswrq.i_l2p_table_high.i_ecc in module pswrq_mem_l2p_table
+  #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_K2_E5_SHIFT                                     1
+  #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_BB                                              (0x1<<1) // Set parity only for memory ecc instance pswrq.i_cxr_ram1.i_ecc in module pswrq_mem_cxr_ram1
+  #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_BB_SHIFT                                        1
+  #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_K2_E5                                           (0x1<<2) // Set parity only for memory ecc instance pswrq.i_cxr_ram1.i_ecc in module pswrq_mem_cxr_ram1
+  #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_K2_E5_SHIFT                                     2
+#define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_BB                                                              0x24021cUL //Access:RC   DataWidth:0x2    // Multi Field Register.
+#define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_K2_E5                                                           0x240220UL //Access:RC   DataWidth:0x3    // Multi Field Register.
+  #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT                                          (0x1<<0) // Record if a correctable error occurred on memory ecc instance pswrq.i_l2p_table.i_ecc in module pswrq_mem_l2p_table
+  #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_SHIFT                                    0
+  #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_K2_E5                                    (0x1<<1) // Record if a correctable error occurred on memory ecc instance pswrq.i_l2p_table_high.i_ecc in module pswrq_mem_l2p_table
+  #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_K2_E5_SHIFT                              1
+  #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_BB                                       (0x1<<1) // Record if a correctable error occurred on memory ecc instance pswrq.i_cxr_ram1.i_ecc in module pswrq_mem_cxr_ram1
+  #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_BB_SHIFT                                 1
+  #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_K2_E5                                    (0x1<<2) // Record if a correctable error occurred on memory ecc instance pswrq.i_cxr_ram1.i_ecc in module pswrq_mem_cxr_ram1
+  #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_K2_E5_SHIFT                              2
+#define PSWRQ2_REG_MEM_ECC_EVENTS_BB                                                                         0x240220UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define PSWRQ2_REG_MEM_ECC_EVENTS_K2_E5                                                                      0x240224UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define PSWRQ2_REG_WR_MBS0                                                                                   0x240400UL //Access:RW   DataWidth:0x3    // Max burst size filed for write requests port 0; 000 - 128B; 001:256B; 010: 512B;.
+#define PSWRQ2_REG_RD_MBS0                                                                                   0x240404UL //Access:RW   DataWidth:0x3    // Max burst size filed for read requests port 0; 000 - 128B; 001:256B; 010: 512B;011:1K:100:2K;101:4K.
+#define PSWRQ2_REG_CDU_ENDIAN_M                                                                              0x240408UL //Access:RW   DataWidth:0x2    // Endian mode for cdu.
+#define PSWRQ2_REG_DISABLE_INPUTS                                                                            0x24040cUL //Access:RW   DataWidth:0x1    // When '1'; requests will enter input buffers but wont get out towards the glue.
+#define PSWRQ2_REG_DRAM_ALIGN_WR                                                                             0x240410UL //Access:RW   DataWidth:0x4    // Determines alignment of write SRs when a request is split into several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B aligned. 4 - 512B aligned.
+#define PSWRQ2_REG_DRAM_ALIGN_RD                                                                             0x240414UL //Access:RW   DataWidth:0x4    // Determines alignment of read SRs when a request is split into several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B aligned. 4 - 512B aligned.
+#define PSWRQ2_REG_USDM_ENTRY_TH                                                                             0x240418UL //Access:RW   DataWidth:0x3    // This number indicates how many entries are guaranteed to usdm in the queues.
+#define PSWRQ2_REG_PRM_ENTRY_TH                                                                              0x24041cUL //Access:RW   DataWidth:0x3    // This number indicates how many entries are guaranteed to prm in the queues.
+#define PSWRQ2_REG_TSDM_ENTRY_TH                                                                             0x240420UL //Access:RW   DataWidth:0x3    // This number indicates how many entries are guaranteed to tsdm in the queues.
+#define PSWRQ2_REG_XSDM_ENTRY_TH                                                                             0x240424UL //Access:RW   DataWidth:0x3    // This number indicates how many entries are guaranteed to xsdm in the queues.
+#define PSWRQ2_REG_DMAE_ENTRY_TH                                                                             0x240428UL //Access:RW   DataWidth:0x3    // This number indicates how many entries are guaranteed to rwh in the queues.
+#define PSWRQ2_REG_CDUWR_ENTRY_TH                                                                            0x24042cUL //Access:RW   DataWidth:0x3    // This number indicates how many entries are guaranteed to cduwr in the queues.
+#define PSWRQ2_REG_CDURD_ENTRY_TH                                                                            0x240430UL //Access:RW   DataWidth:0x3    // This number indicates how many entries are guaranteed to cdurd in the queues.
+#define PSWRQ2_REG_PBF_ENTRY_TH                                                                              0x240434UL //Access:RW   DataWidth:0x7    // This number indicates how many entries are guaranteed to pbf in the queues.
+#define PSWRQ2_REG_QM_ENTRY_TH                                                                               0x240438UL //Access:RW   DataWidth:0x3    // This number indicates how many entries are guaranteed to qm in the queues.
+#define PSWRQ2_REG_TM_ENTRY_TH                                                                               0x24043cUL //Access:RW   DataWidth:0x3    // This number indicates how many entries are guaranteed to tm in the queues.
+#define PSWRQ2_REG_SRC_ENTRY_TH                                                                              0x240440UL //Access:RW   DataWidth:0x3    // This number indicates how many entries are guaranteed to src in the queues.
+#define PSWRQ2_REG_DBG_ENTRY_TH                                                                              0x240444UL //Access:RW   DataWidth:0x3    // This number indicates how many entries are guaranteed to debug in the queues.
+#define PSWRQ2_REG_HC_ENTRY_TH                                                                               0x240448UL //Access:RW   DataWidth:0x2    // This number indicates how many entries are guaranteed to hc in the queues.
+#define PSWRQ2_REG_GC_INIT_VAL                                                                               0x24044cUL //Access:RW   DataWidth:0x8    // Initial value of global counter; This value MUST be 256 - sum of all clients thresholds.
+#define PSWRQ2_REG_UFIFO                                                                                     0x240450UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PSWRQ2_REG_UFIFO_UFIFO_LOW_TH                                                                      (0xf<<0) // Low threshold of update fifo; not used.
+  #define PSWRQ2_REG_UFIFO_UFIFO_LOW_TH_SHIFT                                                                0
+  #define PSWRQ2_REG_UFIFO_UFIFO_HIGH_TH                                                                     (0xf<<4) // High threshold of update fifo; not used.
+  #define PSWRQ2_REG_UFIFO_UFIFO_HIGH_TH_SHIFT                                                               4
+#define PSWRQ2_REG_VQ0_ENTRY_CNT                                                                             0x240454UL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 0 in pswrq memory.
+#define PSWRQ2_REG_VQ1_ENTRY_CNT                                                                             0x240458UL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 1 in pswrq memory.
+#define PSWRQ2_REG_VQ2_ENTRY_CNT                                                                             0x24045cUL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 2 in pswrq memory.
+#define PSWRQ2_REG_VQ3_ENTRY_CNT                                                                             0x240460UL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 3 in pswrq memory.
+#define PSWRQ2_REG_VQ4_ENTRY_CNT                                                                             0x240464UL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 4  in pswrq memory.
+#define PSWRQ2_REG_VQ5_ENTRY_CNT                                                                             0x240468UL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 5  in pswrq memory.
+#define PSWRQ2_REG_VQ6_ENTRY_CNT                                                                             0x24046cUL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 6 in pswrq memory.
+#define PSWRQ2_REG_VQ7_ENTRY_CNT                                                                             0x240470UL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 7 in pswrq memory.
+#define PSWRQ2_REG_VQ8_ENTRY_CNT                                                                             0x240474UL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 8  in pswrq memory.
+#define PSWRQ2_REG_VQ9_ENTRY_CNT                                                                             0x240478UL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 9 in pswrq memory.
+#define PSWRQ2_REG_VQ10_ENTRY_CNT                                                                            0x24047cUL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 10 in pswrq memory.
+#define PSWRQ2_REG_VQ11_ENTRY_CNT                                                                            0x240480UL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 11 in pswrq memory.
+#define PSWRQ2_REG_VQ12_ENTRY_CNT                                                                            0x240484UL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 12 in pswrq memory.
+#define PSWRQ2_REG_VQ13_ENTRY_CNT                                                                            0x240488UL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 13 in pswrq memory.
+#define PSWRQ2_REG_VQ14_ENTRY_CNT                                                                            0x24048cUL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 14  in pswrq memory.
+#define PSWRQ2_REG_VQ15_ENTRY_CNT                                                                            0x240490UL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 15  in pswrq memory.
+#define PSWRQ2_REG_VQ16_ENTRY_CNT                                                                            0x240494UL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 16 in pswrq memory.
+#define PSWRQ2_REG_VQ17_ENTRY_CNT                                                                            0x240498UL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 17 in pswrq memory.
+#define PSWRQ2_REG_VQ18_ENTRY_CNT                                                                            0x24049cUL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 18  in pswrq memory.
+#define PSWRQ2_REG_VQ19_ENTRY_CNT                                                                            0x2404a0UL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 19 in pswrq memory.
+#define PSWRQ2_REG_VQ20_ENTRY_CNT                                                                            0x2404a4UL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 20  in pswrq memory.
+#define PSWRQ2_REG_VQ21_ENTRY_CNT                                                                            0x2404a8UL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 21 in pswrq memory.
+#define PSWRQ2_REG_VQ22_ENTRY_CNT                                                                            0x2404acUL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 22 in pswrq memory.
+#define PSWRQ2_REG_VQ23_ENTRY_CNT                                                                            0x2404b0UL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 23 in pswrq memory.
+#define PSWRQ2_REG_VQ24_ENTRY_CNT                                                                            0x2404b4UL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 24  in pswrq memory.
+#define PSWRQ2_REG_VQ25_ENTRY_CNT                                                                            0x2404b8UL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 25  in pswrq memory.
+#define PSWRQ2_REG_VQ26_ENTRY_CNT                                                                            0x2404bcUL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 26 in pswrq memory.
+#define PSWRQ2_REG_VQ27_ENTRY_CNT                                                                            0x2404c0UL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 27 in pswrq memory.
+#define PSWRQ2_REG_VQ28_ENTRY_CNT                                                                            0x2404c4UL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 28  in pswrq memory.
+#define PSWRQ2_REG_VQ29_ENTRY_CNT                                                                            0x2404c8UL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 29 in pswrq memory.
+#define PSWRQ2_REG_VQ30_ENTRY_CNT                                                                            0x2404ccUL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 30  in pswrq memory.
+#define PSWRQ2_REG_VQ31_ENTRY_CNT                                                                            0x2404d0UL //Access:R    DataWidth:0x8    // Number of entries occupied by vq 31 in pswrq memory.
+#define PSWRQ2_REG_VQ0_MAX_ENTRY_CNT                                                                         0x2404d4UL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 0.
+#define PSWRQ2_REG_VQ1_MAX_ENTRY_CNT                                                                         0x2404d8UL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 1.
+#define PSWRQ2_REG_VQ2_MAX_ENTRY_CNT                                                                         0x2404dcUL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 2.
+#define PSWRQ2_REG_VQ3_MAX_ENTRY_CNT                                                                         0x2404e0UL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 3.
+#define PSWRQ2_REG_VQ4_MAX_ENTRY_CNT                                                                         0x2404e4UL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 4.
+#define PSWRQ2_REG_VQ5_MAX_ENTRY_CNT                                                                         0x2404e8UL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 5.
+#define PSWRQ2_REG_VQ6_MAX_ENTRY_CNT                                                                         0x2404ecUL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 6.
+#define PSWRQ2_REG_VQ7_MAX_ENTRY_CNT                                                                         0x2404f0UL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 7.
+#define PSWRQ2_REG_VQ8_MAX_ENTRY_CNT                                                                         0x2404f4UL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 8.
+#define PSWRQ2_REG_VQ9_MAX_ENTRY_CNT                                                                         0x2404f8UL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 9.
+#define PSWRQ2_REG_VQ10_MAX_ENTRY_CNT                                                                        0x2404fcUL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 10.
+#define PSWRQ2_REG_VQ11_MAX_ENTRY_CNT                                                                        0x240500UL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 11.
+#define PSWRQ2_REG_VQ12_MAX_ENTRY_CNT                                                                        0x240504UL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 12.
+#define PSWRQ2_REG_VQ13_MAX_ENTRY_CNT                                                                        0x240508UL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 13.
+#define PSWRQ2_REG_VQ14_MAX_ENTRY_CNT                                                                        0x24050cUL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 14.
+#define PSWRQ2_REG_VQ15_MAX_ENTRY_CNT                                                                        0x240510UL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 15.
+#define PSWRQ2_REG_VQ16_MAX_ENTRY_CNT                                                                        0x240514UL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 16.
+#define PSWRQ2_REG_VQ17_MAX_ENTRY_CNT                                                                        0x240518UL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 17.
+#define PSWRQ2_REG_VQ18_MAX_ENTRY_CNT                                                                        0x24051cUL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 18.
+#define PSWRQ2_REG_VQ19_MAX_ENTRY_CNT                                                                        0x240520UL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 19.
+#define PSWRQ2_REG_VQ20_MAX_ENTRY_CNT                                                                        0x240524UL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 20.
+#define PSWRQ2_REG_VQ21_MAX_ENTRY_CNT                                                                        0x240528UL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 21.
+#define PSWRQ2_REG_VQ22_MAX_ENTRY_CNT                                                                        0x24052cUL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 22.
+#define PSWRQ2_REG_VQ23_MAX_ENTRY_CNT                                                                        0x240530UL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 23.
+#define PSWRQ2_REG_VQ24_MAX_ENTRY_CNT                                                                        0x240534UL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 24.
+#define PSWRQ2_REG_VQ25_MAX_ENTRY_CNT                                                                        0x240538UL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 25.
+#define PSWRQ2_REG_VQ26_MAX_ENTRY_CNT                                                                        0x24053cUL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 26.
+#define PSWRQ2_REG_VQ27_MAX_ENTRY_CNT                                                                        0x240540UL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 27.
+#define PSWRQ2_REG_VQ28_MAX_ENTRY_CNT                                                                        0x240544UL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 28.
+#define PSWRQ2_REG_VQ29_MAX_ENTRY_CNT                                                                        0x240548UL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 29.
+#define PSWRQ2_REG_VQ30_MAX_ENTRY_CNT                                                                        0x24054cUL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 30.
+#define PSWRQ2_REG_VQ31_MAX_ENTRY_CNT                                                                        0x240550UL //Access:R    DataWidth:0x8    // Maximum Number of entries occupied by vq 31.
+#define PSWRQ2_REG_UFIFO_NUM_OF_ENTRY                                                                        0x240554UL //Access:R    DataWidth:0x5    // Number of entries in the ufifo;This fifo has l2p completions.
+#define PSWRQ2_REG_QM_PCI_ATTR                                                                               0x240558UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PSWRQ2_REG_QM_PCI_ATTR_QM_RELAXED                                                                  (0x1<<0) // Relaxed oredering attribute for qm.
+  #define PSWRQ2_REG_QM_PCI_ATTR_QM_RELAXED_SHIFT                                                            0
+  #define PSWRQ2_REG_QM_PCI_ATTR_QM_NOSNOOP                                                                  (0x1<<1) // Nosnoop attribute for qm.
+  #define PSWRQ2_REG_QM_PCI_ATTR_QM_NOSNOOP_SHIFT                                                            1
+#define PSWRQ2_REG_TM_PCI_ATTR                                                                               0x24055cUL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PSWRQ2_REG_TM_PCI_ATTR_TM_RELAXED                                                                  (0x1<<0) // Relaxed oredering attribute for tm.
+  #define PSWRQ2_REG_TM_PCI_ATTR_TM_RELAXED_SHIFT                                                            0
+  #define PSWRQ2_REG_TM_PCI_ATTR_TM_NOSNOOP                                                                  (0x1<<1) // Nosnoop attribute for tm.
+  #define PSWRQ2_REG_TM_PCI_ATTR_TM_NOSNOOP_SHIFT                                                            1
+#define PSWRQ2_REG_SRC_PCI_ATTR                                                                              0x240560UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PSWRQ2_REG_SRC_PCI_ATTR_SRC_RELAXED                                                                (0x1<<0) // Relaxed oredering attribute for src.
+  #define PSWRQ2_REG_SRC_PCI_ATTR_SRC_RELAXED_SHIFT                                                          0
+  #define PSWRQ2_REG_SRC_PCI_ATTR_SRC_NOSNOOP                                                                (0x1<<1) // Nosnoop attribute for src.
+  #define PSWRQ2_REG_SRC_PCI_ATTR_SRC_NOSNOOP_SHIFT                                                          1
+#define PSWRQ2_REG_CDU_PCI_ATTR                                                                              0x240564UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PSWRQ2_REG_CDU_PCI_ATTR_CDU_RELAXED                                                                (0x1<<0) // Relaxed oredering attribute for cdu. Removed in E4B0, PXP request flag is used.
+  #define PSWRQ2_REG_CDU_PCI_ATTR_CDU_RELAXED_SHIFT                                                          0
+  #define PSWRQ2_REG_CDU_PCI_ATTR_CDU_NOSNOOP                                                                (0x1<<1) // Nosnoop attribute for cdu. Removed in E4B0, PXP request flag is used.
+  #define PSWRQ2_REG_CDU_PCI_ATTR_CDU_NOSNOOP_SHIFT                                                          1
+#define PSWRQ2_REG_DBG_PCI_ATTR                                                                              0x240568UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PSWRQ2_REG_DBG_PCI_ATTR_DBG_RELAXED                                                                (0x1<<0) // Relaxed oredering attribute for dbg.
+  #define PSWRQ2_REG_DBG_PCI_ATTR_DBG_RELAXED_SHIFT                                                          0
+  #define PSWRQ2_REG_DBG_PCI_ATTR_DBG_NOSNOOP                                                                (0x1<<1) // Nosnoop attribute for dbg.
+  #define PSWRQ2_REG_DBG_PCI_ATTR_DBG_NOSNOOP_SHIFT                                                          1
+#define PSWRQ2_REG_HC_PCI_ATTR                                                                               0x24056cUL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PSWRQ2_REG_HC_PCI_ATTR_HC_RELAXED                                                                  (0x1<<0) // Relaxed oredering attribute for hc.
+  #define PSWRQ2_REG_HC_PCI_ATTR_HC_RELAXED_SHIFT                                                            0
+  #define PSWRQ2_REG_HC_PCI_ATTR_HC_NOSNOOP                                                                  (0x1<<1) // Nosnoop attribute for hc.
+  #define PSWRQ2_REG_HC_PCI_ATTR_HC_NOSNOOP_SHIFT                                                            1
+#define PSWRQ2_REG_DMAE_PCI_ATTR                                                                             0x240570UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PSWRQ2_REG_DMAE_PCI_ATTR_DMAE_RELAXED                                                              (0x1<<0) // Relaxed oredering attribute for dmae.
+  #define PSWRQ2_REG_DMAE_PCI_ATTR_DMAE_RELAXED_SHIFT                                                        0
+  #define PSWRQ2_REG_DMAE_PCI_ATTR_DMAE_NOSNOOP                                                              (0x1<<1) // Nosnoop attribute for dmae.
+  #define PSWRQ2_REG_DMAE_PCI_ATTR_DMAE_NOSNOOP_SHIFT                                                        1
+#define PSWRQ2_REG_QM_ENDIAN_M                                                                               0x240574UL //Access:RW   DataWidth:0x2    // Endian mode for qm.
+#define PSWRQ2_REG_TM_ENDIAN_M                                                                               0x240578UL //Access:RW   DataWidth:0x2    // Endian mode for tm.
+#define PSWRQ2_REG_SRC_ENDIAN_M                                                                              0x24057cUL //Access:RW   DataWidth:0x2    // Endian mode for src.
+#define PSWRQ2_REG_DBG_ENDIAN_M                                                                              0x240580UL //Access:RW   DataWidth:0x2    // Endian mode for debug.
+#define PSWRQ2_REG_PBF_ENDIAN_M                                                                              0x240584UL //Access:RW   DataWidth:0x2    // Endian mode for pbf.
+#define PSWRQ2_REG_DONE_FIFO_TH                                                                              0x240588UL //Access:RW   DataWidth:0x5    // Write Done fifo threshold; this fifo has write done indications;this threshold would not be reached unless there is a bug.
+#define PSWRQ2_REG_BW_RD_ADD0                                                                                0x24058cUL //Access:RW   DataWidth:0xa    // Bandwidth addition to VQ0 write requests.
+#define PSWRQ2_REG_BW_ADD1                                                                                   0x240590UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PSWRQ2_REG_BW_ADD1_BW_RD_ADD1                                                                      (0x3ff<<0) // Bandwidth addition to VQ1 read requests.
+  #define PSWRQ2_REG_BW_ADD1_BW_RD_ADD1_SHIFT                                                                0
+  #define PSWRQ2_REG_BW_ADD1_BW_WR_ADD1                                                                      (0x3ff<<10) // Bandwidth addition to VQ1 write requests.
+  #define PSWRQ2_REG_BW_ADD1_BW_WR_ADD1_SHIFT                                                                10
+#define PSWRQ2_REG_BW_ADD2                                                                                   0x240594UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PSWRQ2_REG_BW_ADD2_BW_RD_ADD2                                                                      (0x3ff<<0) // Bandwidth addition to VQ2 read requests.
+  #define PSWRQ2_REG_BW_ADD2_BW_RD_ADD2_SHIFT                                                                0
+  #define PSWRQ2_REG_BW_ADD2_BW_WR_ADD2                                                                      (0x3ff<<10) // Bandwidth addition to VQ2 write requests.
+  #define PSWRQ2_REG_BW_ADD2_BW_WR_ADD2_SHIFT                                                                10
+#define PSWRQ2_REG_BW_ADD3                                                                                   0x240598UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PSWRQ2_REG_BW_ADD3_BW_RD_ADD3                                                                      (0x3ff<<0) // Bandwidth addition to VQ3 read requests.
+  #define PSWRQ2_REG_BW_ADD3_BW_RD_ADD3_SHIFT                                                                0
+  #define PSWRQ2_REG_BW_ADD3_BW_WR_ADD3                                                                      (0x3ff<<10) // Bandwidth addition to VQ3 write requests.
+  #define PSWRQ2_REG_BW_ADD3_BW_WR_ADD3_SHIFT                                                                10
+#define PSWRQ2_REG_BW_RD_ADD4                                                                                0x24059cUL //Access:RW   DataWidth:0xa    // Bandwidth addition to VQ4 read requests.
+#define PSWRQ2_REG_BW_RD_ADD5                                                                                0x2405a0UL //Access:RW   DataWidth:0xa    // Bandwidth addition to VQ5 read requests.
+#define PSWRQ2_REG_BW_ADD6                                                                                   0x2405a4UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PSWRQ2_REG_BW_ADD6_BW_RD_ADD6                                                                      (0x3ff<<0) // Bandwidth addition to VQ6 read requests.
+  #define PSWRQ2_REG_BW_ADD6_BW_RD_ADD6_SHIFT                                                                0
+  #define PSWRQ2_REG_BW_ADD6_BW_WR_ADD6                                                                      (0x3ff<<10) // Bandwidth addition to VQ6 write requests.
+  #define PSWRQ2_REG_BW_ADD6_BW_WR_ADD6_SHIFT                                                                10
+#define PSWRQ2_REG_BW_ADD7                                                                                   0x2405a8UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PSWRQ2_REG_BW_ADD7_BW_RD_ADD7                                                                      (0x3ff<<0) // Bandwidth addition to VQ7 read requests.
+  #define PSWRQ2_REG_BW_ADD7_BW_RD_ADD7_SHIFT                                                                0
+  #define PSWRQ2_REG_BW_ADD7_BW_WR_ADD7                                                                      (0x3ff<<10) // Bandwidth addition to VQ7 write requests.
+  #define PSWRQ2_REG_BW_ADD7_BW_WR_ADD7_SHIFT                                                                10
+#define PSWRQ2_REG_BW_ADD8                                                                                   0x2405acUL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PSWRQ2_REG_BW_ADD8_BW_RD_ADD8                                                                      (0x3ff<<0) // Bandwidth addition to VQ8 read requests.
+  #define PSWRQ2_REG_BW_ADD8_BW_RD_ADD8_SHIFT                                                                0
+  #define PSWRQ2_REG_BW_ADD8_BW_WR_ADD8                                                                      (0x3ff<<10) // Bandwidth addition to VQ8 write requests.
+  #define PSWRQ2_REG_BW_ADD8_BW_WR_ADD8_SHIFT                                                                10
+#define PSWRQ2_REG_BW_ADD9                                                                                   0x2405b0UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PSWRQ2_REG_BW_ADD9_BW_RD_ADD9                                                                      (0x3ff<<0) // Bandwidth addition to VQ9 read requests.
+  #define PSWRQ2_REG_BW_ADD9_BW_RD_ADD9_SHIFT                                                                0
+  #define PSWRQ2_REG_BW_ADD9_BW_WR_ADD9                                                                      (0x3ff<<10) // Bandwidth addition to VQ9 write requests.
+  #define PSWRQ2_REG_BW_ADD9_BW_WR_ADD9_SHIFT                                                                10
+#define PSWRQ2_REG_BW_ADD10                                                                                  0x2405b4UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PSWRQ2_REG_BW_ADD10_BW_RD_ADD10                                                                    (0x3ff<<0) // Bandwidth addition to VQ10 read requests.
+  #define PSWRQ2_REG_BW_ADD10_BW_RD_ADD10_SHIFT                                                              0
+  #define PSWRQ2_REG_BW_ADD10_BW_WR_ADD10                                                                    (0x3ff<<10) // Bandwidth addition to VQ10 write requests.
+  #define PSWRQ2_REG_BW_ADD10_BW_WR_ADD10_SHIFT                                                              10
+#define PSWRQ2_REG_BW_ADD11                                                                                  0x2405b8UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PSWRQ2_REG_BW_ADD11_BW_RD_ADD11                                                                    (0x3ff<<0) // Bandwidth addition to VQ11 read requests.
+  #define PSWRQ2_REG_BW_ADD11_BW_RD_ADD11_SHIFT                                                              0
+  #define PSWRQ2_REG_BW_ADD11_BW_WR_ADD11                                                                    (0x3ff<<10) // Bandwidth addition to VQ11 write requests.
+  #define PSWRQ2_REG_BW_ADD11_BW_WR_ADD11_SHIFT                                                              10
+#define PSWRQ2_REG_BW_RD_ADD12                                                                               0x2405bcUL //Access:RW   DataWidth:0xa    // Bandwidth addition to VQ12 read requests.
+#define PSWRQ2_REG_BW_RD_ADD13                                                                               0x2405c0UL //Access:RW   DataWidth:0xa    // Bandwidth addition to VQ13 read requests.
+#define PSWRQ2_REG_BW_ADD14                                                                                  0x2405c4UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PSWRQ2_REG_BW_ADD14_BW_RD_ADD14                                                                    (0x3ff<<0) // Bandwidth addition to VQ14 read requests.
+  #define PSWRQ2_REG_BW_ADD14_BW_RD_ADD14_SHIFT                                                              0
+  #define PSWRQ2_REG_BW_ADD14_BW_WR_ADD14                                                                    (0x3ff<<10) // Bandwidth addition to VQ14 write requests.
+  #define PSWRQ2_REG_BW_ADD14_BW_WR_ADD14_SHIFT                                                              10
+#define PSWRQ2_REG_BW_RD_ADD15                                                                               0x2405c8UL //Access:RW   DataWidth:0xa    // Bandwidth addition to VQ15 read requests.
+#define PSWRQ2_REG_BW_RD_ADD16                                                                               0x2405ccUL //Access:RW   DataWidth:0xa    // Bandwidth addition to VQ16 read requests.
+#define PSWRQ2_REG_BW_RD_ADD17                                                                               0x2405d0UL //Access:RW   DataWidth:0xa    // Bandwidth addition to VQ17 read requests.
+#define PSWRQ2_REG_BW_RD_ADD18                                                                               0x2405d4UL //Access:RW   DataWidth:0xa    // Bandwidth addition to VQ18 read requests.
+#define PSWRQ2_REG_BW_RD_ADD19                                                                               0x2405d8UL //Access:RW   DataWidth:0xa    // Bandwidth addition to VQ19 read requests.
+#define PSWRQ2_REG_BW_RD_ADD20                                                                               0x2405dcUL //Access:RW   DataWidth:0xa    // Bandwidth addition to VQ20 read requests.
+#define PSWRQ2_REG_BW_WR_ADD21                                                                               0x2405e0UL //Access:RW   DataWidth:0xa    // Bandwidth addition to VQ21 write requests.
+#define PSWRQ2_REG_BW_RD_ADD22                                                                               0x2405e4UL //Access:RW   DataWidth:0xa    // Bandwidth addition to VQ22 read requests.
+#define PSWRQ2_REG_BW_RD_ADD23                                                                               0x2405e8UL //Access:RW   DataWidth:0xa    // Bandwidth addition to VQ23 read requests.
+#define PSWRQ2_REG_BW_RD_ADD24                                                                               0x2405ecUL //Access:RW   DataWidth:0xa    // Bandwidth addition to VQ24 read requests.
+#define PSWRQ2_REG_BW_RD_ADD25                                                                               0x2405f0UL //Access:RW   DataWidth:0xa    // Bandwidth addition to VQ25 read requests.
+#define PSWRQ2_REG_BW_RD_ADD26                                                                               0x2405f4UL //Access:RW   DataWidth:0xa    // Bandwidth addition to VQ26 read requests.
+#define PSWRQ2_REG_BW_RD_ADD27                                                                               0x2405f8UL //Access:RW   DataWidth:0xa    // Bandwidth addition to VQ27 read requests.
+#define PSWRQ2_REG_BW_ADD28                                                                                  0x2405fcUL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PSWRQ2_REG_BW_ADD28_BW_RD_ADD28                                                                    (0x3ff<<0) // Bandwidth addition to VQ28 read requests.
+  #define PSWRQ2_REG_BW_ADD28_BW_RD_ADD28_SHIFT                                                              0
+  #define PSWRQ2_REG_BW_ADD28_BW_WR_ADD28                                                                    (0x3ff<<10) // Bandwidth addition to VQ28 write requests.
+  #define PSWRQ2_REG_BW_ADD28_BW_WR_ADD28_SHIFT                                                              10
+#define PSWRQ2_REG_BW_WR_ADD29                                                                               0x240600UL //Access:RW   DataWidth:0xa    // Bandwidth addition to VQ29 write requests.
+#define PSWRQ2_REG_BW_WR_ADD30                                                                               0x240604UL //Access:RW   DataWidth:0xa    // Bandwidth addition to VQ30 write requests.
+#define PSWRQ2_REG_BW_ADD31                                                                                  0x240608UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PSWRQ2_REG_BW_ADD31_BW_RD_ADD31                                                                    (0x3ff<<0) // Bandwidth addition to VQ31 read requests.
+  #define PSWRQ2_REG_BW_ADD31_BW_RD_ADD31_SHIFT                                                              0
+  #define PSWRQ2_REG_BW_ADD31_BW_WR_ADD31                                                                    (0x3ff<<10) // Bandwidth addition to VQ31 write requests.
+  #define PSWRQ2_REG_BW_ADD31_BW_WR_ADD31_SHIFT                                                              10
+#define PSWRQ2_REG_BW_RD_UBOUND0                                                                             0x24060cUL //Access:RW   DataWidth:0x9    // Bandwidth upper bound for VQ0 read requests.
+#define PSWRQ2_REG_BW_UB1                                                                                    0x240610UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRQ2_REG_BW_UB1_BW_RD_UBOUND1                                                                    (0x1ff<<0) // Bandwidth upper bound for VQ1 read requests.
+  #define PSWRQ2_REG_BW_UB1_BW_RD_UBOUND1_SHIFT                                                              0
+  #define PSWRQ2_REG_BW_UB1_BW_WR_UBOUND1                                                                    (0x1ff<<9) // Bandwidth upper bound for VQ1 write requests.
+  #define PSWRQ2_REG_BW_UB1_BW_WR_UBOUND1_SHIFT                                                              9
+#define PSWRQ2_REG_BW_UB2                                                                                    0x240614UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRQ2_REG_BW_UB2_BW_RD_UBOUND2                                                                    (0x1ff<<0) // Bandwidth upper bound for VQ2 read requests.
+  #define PSWRQ2_REG_BW_UB2_BW_RD_UBOUND2_SHIFT                                                              0
+  #define PSWRQ2_REG_BW_UB2_BW_WR_UBOUND2                                                                    (0x1ff<<9) // Bandwidth upper bound for VQ2 read requests.
+  #define PSWRQ2_REG_BW_UB2_BW_WR_UBOUND2_SHIFT                                                              9
+#define PSWRQ2_REG_BW_UB3                                                                                    0x240618UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRQ2_REG_BW_UB3_BW_RD_UBOUND3                                                                    (0x1ff<<0) // Bandwidth upper bound for VQ3 read requests.
+  #define PSWRQ2_REG_BW_UB3_BW_RD_UBOUND3_SHIFT                                                              0
+  #define PSWRQ2_REG_BW_UB3_BW_WR_UBOUND3                                                                    (0x1ff<<9) // Bandwidth upper bound for VQ3 write requests.
+  #define PSWRQ2_REG_BW_UB3_BW_WR_UBOUND3_SHIFT                                                              9
+#define PSWRQ2_REG_BW_RD_UBOUND4                                                                             0x24061cUL //Access:RW   DataWidth:0x9    // Bandwidth upper bound for VQ4 read requests.
+#define PSWRQ2_REG_BW_RD_UBOUND5                                                                             0x240620UL //Access:RW   DataWidth:0x9    // Bandwidth upper bound for VQ5 read requests.
+#define PSWRQ2_REG_BW_UB6                                                                                    0x240624UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRQ2_REG_BW_UB6_BW_RD_UBOUND6                                                                    (0x1ff<<0) // Bandwidth upper bound for VQ6 read requests.
+  #define PSWRQ2_REG_BW_UB6_BW_RD_UBOUND6_SHIFT                                                              0
+  #define PSWRQ2_REG_BW_UB6_BW_WR_UBOUND6                                                                    (0x1ff<<9) // Bandwidth upper bound for VQ6 write requests.
+  #define PSWRQ2_REG_BW_UB6_BW_WR_UBOUND6_SHIFT                                                              9
+#define PSWRQ2_REG_BW_UB7                                                                                    0x240628UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRQ2_REG_BW_UB7_BW_RD_UBOUND7                                                                    (0x1ff<<0) // Bandwidth upper bound for VQ7 read requests.
+  #define PSWRQ2_REG_BW_UB7_BW_RD_UBOUND7_SHIFT                                                              0
+  #define PSWRQ2_REG_BW_UB7_BW_WR_UBOUND7                                                                    (0x1ff<<9) // Bandwidth upper bound for VQ7 write requests.
+  #define PSWRQ2_REG_BW_UB7_BW_WR_UBOUND7_SHIFT                                                              9
+#define PSWRQ2_REG_BW_UB8                                                                                    0x24062cUL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRQ2_REG_BW_UB8_BW_RD_UBOUND8                                                                    (0x1ff<<0) // Bandwidth upper bound for VQ8 read requests.
+  #define PSWRQ2_REG_BW_UB8_BW_RD_UBOUND8_SHIFT                                                              0
+  #define PSWRQ2_REG_BW_UB8_BW_WR_UBOUND8                                                                    (0x1ff<<9) // Bandwidth upper bound for VQ8 write requests.
+  #define PSWRQ2_REG_BW_UB8_BW_WR_UBOUND8_SHIFT                                                              9
+#define PSWRQ2_REG_BW_UB9                                                                                    0x240630UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRQ2_REG_BW_UB9_BW_RD_UBOUND9                                                                    (0x1ff<<0) // Bandwidth upper bound for VQ9 read requests.
+  #define PSWRQ2_REG_BW_UB9_BW_RD_UBOUND9_SHIFT                                                              0
+  #define PSWRQ2_REG_BW_UB9_BW_WR_UBOUND9                                                                    (0x1ff<<9) // Bandwidth upper bound for VQ9 write requests.
+  #define PSWRQ2_REG_BW_UB9_BW_WR_UBOUND9_SHIFT                                                              9
+#define PSWRQ2_REG_BW_UB10                                                                                   0x240634UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRQ2_REG_BW_UB10_BW_RD_UBOUND10                                                                  (0x1ff<<0) // Bandwidth upper bound for VQ10 read requests.
+  #define PSWRQ2_REG_BW_UB10_BW_RD_UBOUND10_SHIFT                                                            0
+  #define PSWRQ2_REG_BW_UB10_BW_WR_UBOUND10                                                                  (0x1ff<<9) // Bandwidth upper bound for VQ10 write requests.
+  #define PSWRQ2_REG_BW_UB10_BW_WR_UBOUND10_SHIFT                                                            9
+#define PSWRQ2_REG_BW_UB11                                                                                   0x240638UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRQ2_REG_BW_UB11_BW_RD_UBOUND11                                                                  (0x1ff<<0) // Bandwidth upper bound for VQ11 read requests.
+  #define PSWRQ2_REG_BW_UB11_BW_RD_UBOUND11_SHIFT                                                            0
+  #define PSWRQ2_REG_BW_UB11_BW_WR_UBOUND11                                                                  (0x1ff<<9) // Bandwidth upper bound for VQ11 write requests.
+  #define PSWRQ2_REG_BW_UB11_BW_WR_UBOUND11_SHIFT                                                            9
+#define PSWRQ2_REG_BW_RD_UBOUND12                                                                            0x24063cUL //Access:RW   DataWidth:0x9    // Bandwidth upper bound for VQ12 read requests.
+#define PSWRQ2_REG_BW_RD_UBOUND13                                                                            0x240640UL //Access:RW   DataWidth:0x9    // Bandwidth upper bound for VQ13 read requests.
+#define PSWRQ2_REG_BW_UB14                                                                                   0x240644UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRQ2_REG_BW_UB14_BW_RD_UBOUND14                                                                  (0x1ff<<0) // Bandwidth upper bound for VQ14 read requests.
+  #define PSWRQ2_REG_BW_UB14_BW_RD_UBOUND14_SHIFT                                                            0
+  #define PSWRQ2_REG_BW_UB14_BW_WR_UBOUND14                                                                  (0x1ff<<9) // Bandwidth upper bound for VQ14 write requests.
+  #define PSWRQ2_REG_BW_UB14_BW_WR_UBOUND14_SHIFT                                                            9
+#define PSWRQ2_REG_BW_RD_UBOUND15                                                                            0x240648UL //Access:RW   DataWidth:0x9    // Bandwidth upper bound for VQ15 read requests.
+#define PSWRQ2_REG_BW_RD_UBOUND16                                                                            0x24064cUL //Access:RW   DataWidth:0x9    // Bandwidth upper bound for VQ16 read requests.
+#define PSWRQ2_REG_BW_RD_UBOUND17                                                                            0x240650UL //Access:RW   DataWidth:0x9    // Bandwidth upper bound for VQ17 read requests.
+#define PSWRQ2_REG_BW_RD_UBOUND18                                                                            0x240654UL //Access:RW   DataWidth:0x9    // Bandwidth upper bound for VQ18 read requests.
+#define PSWRQ2_REG_BW_RD_UBOUND19                                                                            0x240658UL //Access:RW   DataWidth:0x9    // Bandwidth upper bound for VQ19 read requests.
+#define PSWRQ2_REG_BW_RD_UBOUND20                                                                            0x24065cUL //Access:RW   DataWidth:0x9    // Bandwidth upper bound for VQ20 read requests.
+#define PSWRQ2_REG_BW_WR_UBOUND21                                                                            0x240660UL //Access:RW   DataWidth:0x9    // Bandwidth upper bound for VQ21 write requests.
+#define PSWRQ2_REG_BW_RD_UBOUND22                                                                            0x240664UL //Access:RW   DataWidth:0x9    // Bandwidth upper bound for VQ22 read requests.
+#define PSWRQ2_REG_BW_RD_UBOUND23                                                                            0x240668UL //Access:RW   DataWidth:0x9    // Bandwidth upper bound for VQ23 read requests.
+#define PSWRQ2_REG_BW_RD_UBOUND24                                                                            0x24066cUL //Access:RW   DataWidth:0x9    // Bandwidth upper bound for VQ24 read requests.
+#define PSWRQ2_REG_BW_RD_UBOUND25                                                                            0x240670UL //Access:RW   DataWidth:0x9    // Bandwidth upper bound for VQ25 read requests.
+#define PSWRQ2_REG_BW_RD_UBOUND26                                                                            0x240674UL //Access:RW   DataWidth:0x9    // Bandwidth upper bound for VQ26 read requests.
+#define PSWRQ2_REG_BW_RD_UBOUND27                                                                            0x240678UL //Access:RW   DataWidth:0x9    // Bandwidth upper bound for VQ27 read requests.
+#define PSWRQ2_REG_BW_UB28                                                                                   0x24067cUL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRQ2_REG_BW_UB28_BW_RD_UBOUND28                                                                  (0x1ff<<0) // Bandwidth upper bound for VQ28 read requests.
+  #define PSWRQ2_REG_BW_UB28_BW_RD_UBOUND28_SHIFT                                                            0
+  #define PSWRQ2_REG_BW_UB28_BW_WR_UBOUND28                                                                  (0x1ff<<9) // Bandwidth upper bound for VQ28.
+  #define PSWRQ2_REG_BW_UB28_BW_WR_UBOUND28_SHIFT                                                            9
+#define PSWRQ2_REG_BW_WR_UBOUND29                                                                            0x240680UL //Access:RW   DataWidth:0x9    // Bandwidth upper bound for VQ29.
+#define PSWRQ2_REG_BW_WR_UBOUND30                                                                            0x240684UL //Access:RW   DataWidth:0x9    // Bandwidth upper bound for VQ30.
+#define PSWRQ2_REG_BW_UB31                                                                                   0x240688UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRQ2_REG_BW_UB31_BW_RD_UBOUND31                                                                  (0x1ff<<0) // Bandwidth upper bound for VQ31 read requests.
+  #define PSWRQ2_REG_BW_UB31_BW_RD_UBOUND31_SHIFT                                                            0
+  #define PSWRQ2_REG_BW_UB31_BW_WR_UBOUND31                                                                  (0x1ff<<9) // Bandwidth upper bound for VQ31 write requests.
+  #define PSWRQ2_REG_BW_UB31_BW_WR_UBOUND31_SHIFT                                                            9
+#define PSWRQ2_REG_BW_RD_L0                                                                                  0x24068cUL //Access:RW   DataWidth:0x9    // Bandwidth Typical L for VQ0 Read requests.
+#define PSWRQ2_REG_BW_L1                                                                                     0x240690UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRQ2_REG_BW_L1_BW_WR_L1                                                                          (0x1ff<<0) // Bandwidth Typical L for VQ1 Write requests.
+  #define PSWRQ2_REG_BW_L1_BW_WR_L1_SHIFT                                                                    0
+  #define PSWRQ2_REG_BW_L1_BW_RD_L1                                                                          (0x1ff<<9) // Bandwidth Typical L for VQ1 Read requests.
+  #define PSWRQ2_REG_BW_L1_BW_RD_L1_SHIFT                                                                    9
+#define PSWRQ2_REG_BW_L2                                                                                     0x240694UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRQ2_REG_BW_L2_BW_WR_L2                                                                          (0x1ff<<0) // Bandwidth Typical L for VQ2 Write requests.
+  #define PSWRQ2_REG_BW_L2_BW_WR_L2_SHIFT                                                                    0
+  #define PSWRQ2_REG_BW_L2_BW_RD_L2                                                                          (0x1ff<<9) // Bandwidth Typical L for VQ2 Read requests.
+  #define PSWRQ2_REG_BW_L2_BW_RD_L2_SHIFT                                                                    9
+#define PSWRQ2_REG_BW_L3                                                                                     0x240698UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRQ2_REG_BW_L3_BW_WR_L3                                                                          (0x1ff<<0) // Bandwidth Typical L for VQ3 Write requests.
+  #define PSWRQ2_REG_BW_L3_BW_WR_L3_SHIFT                                                                    0
+  #define PSWRQ2_REG_BW_L3_BW_RD_L3                                                                          (0x1ff<<9) // Bandwidth Typical L for VQ3 Read requests.
+  #define PSWRQ2_REG_BW_L3_BW_RD_L3_SHIFT                                                                    9
+#define PSWRQ2_REG_BW_RD_L4                                                                                  0x24069cUL //Access:RW   DataWidth:0x9    // Bandwidth Typical L for VQ4 Read requests.
+#define PSWRQ2_REG_BW_RD_L5                                                                                  0x2406a0UL //Access:RW   DataWidth:0x9    // Bandwidth Typical L for VQ5 Read- currently not used.
+#define PSWRQ2_REG_BW_L6                                                                                     0x2406a4UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRQ2_REG_BW_L6_BW_RD_L6                                                                          (0x1ff<<0) // Bandwidth Typical L for VQ6 Read requests.
+  #define PSWRQ2_REG_BW_L6_BW_RD_L6_SHIFT                                                                    0
+  #define PSWRQ2_REG_BW_L6_BW_WR_L6                                                                          (0x1ff<<9) // Bandwidth Typical L for VQ6 Write requests.
+  #define PSWRQ2_REG_BW_L6_BW_WR_L6_SHIFT                                                                    9
+#define PSWRQ2_REG_BW_L7                                                                                     0x2406a8UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRQ2_REG_BW_L7_BW_RD_L7                                                                          (0x1ff<<0) // Bandwidth Typical L for VQ7 Read requests.
+  #define PSWRQ2_REG_BW_L7_BW_RD_L7_SHIFT                                                                    0
+  #define PSWRQ2_REG_BW_L7_BW_WR_L7                                                                          (0x1ff<<9) // Bandwidth Typical L for VQ7 Write requests.
+  #define PSWRQ2_REG_BW_L7_BW_WR_L7_SHIFT                                                                    9
+#define PSWRQ2_REG_BW_L8                                                                                     0x2406acUL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRQ2_REG_BW_L8_BW_RD_L8                                                                          (0x1ff<<0) // Bandwidth Typical L for VQ8 Read requests.
+  #define PSWRQ2_REG_BW_L8_BW_RD_L8_SHIFT                                                                    0
+  #define PSWRQ2_REG_BW_L8_BW_WR_L8                                                                          (0x1ff<<9) // Bandwidth Typical L for VQ8 Write requests.
+  #define PSWRQ2_REG_BW_L8_BW_WR_L8_SHIFT                                                                    9
+#define PSWRQ2_REG_BW_L9                                                                                     0x2406b0UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRQ2_REG_BW_L9_BW_RD_L9                                                                          (0x1ff<<0) // Bandwidth Typical L for VQ9 Read requests.
+  #define PSWRQ2_REG_BW_L9_BW_RD_L9_SHIFT                                                                    0
+  #define PSWRQ2_REG_BW_L9_BW_WR_L9                                                                          (0x1ff<<9) // Bandwidth Typical L for VQ9 Write requests.
+  #define PSWRQ2_REG_BW_L9_BW_WR_L9_SHIFT                                                                    9
+#define PSWRQ2_REG_BW_L10                                                                                    0x2406b4UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRQ2_REG_BW_L10_BW_RD_L10                                                                        (0x1ff<<0) // Bandwidth Typical L for VQ10 Read requests.
+  #define PSWRQ2_REG_BW_L10_BW_RD_L10_SHIFT                                                                  0
+  #define PSWRQ2_REG_BW_L10_BW_WR_L10                                                                        (0x1ff<<9) // Bandwidth Typical L for VQ10 Write requests.
+  #define PSWRQ2_REG_BW_L10_BW_WR_L10_SHIFT                                                                  9
+#define PSWRQ2_REG_BW_L11                                                                                    0x2406b8UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRQ2_REG_BW_L11_BW_RD_L11                                                                        (0x1ff<<0) // Bandwidth Typical L for VQ11 Read requests.
+  #define PSWRQ2_REG_BW_L11_BW_RD_L11_SHIFT                                                                  0
+  #define PSWRQ2_REG_BW_L11_BW_WR_L11                                                                        (0x1ff<<9) // Bandwidth Typical L for VQ11 Write requests.
+  #define PSWRQ2_REG_BW_L11_BW_WR_L11_SHIFT                                                                  9
+#define PSWRQ2_REG_BW_RD_L12                                                                                 0x2406bcUL //Access:RW   DataWidth:0x9    // Bandwidth Typical L for VQ12 Read requests.
+#define PSWRQ2_REG_BW_RD_L13                                                                                 0x2406c0UL //Access:RW   DataWidth:0x9    // Bandwidth Typical L for VQ13 Read requests.
+#define PSWRQ2_REG_BW_L14                                                                                    0x2406c4UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRQ2_REG_BW_L14_BW_RD_L14                                                                        (0x1ff<<0) // Bandwidth Typical L for VQ14 Read requests.
+  #define PSWRQ2_REG_BW_L14_BW_RD_L14_SHIFT                                                                  0
+  #define PSWRQ2_REG_BW_L14_BW_WR_L14                                                                        (0x1ff<<9) // Bandwidth Typical L for VQ14 Write requests.
+  #define PSWRQ2_REG_BW_L14_BW_WR_L14_SHIFT                                                                  9
+#define PSWRQ2_REG_BW_RD_L15                                                                                 0x2406c8UL //Access:RW   DataWidth:0x9    // Bandwidth Typical L for VQ15 Read requests.
+#define PSWRQ2_REG_BW_RD_L16                                                                                 0x2406ccUL //Access:RW   DataWidth:0x9    // Bandwidth Typical L for VQ16 Read requests.
+#define PSWRQ2_REG_BW_RD_L17                                                                                 0x2406d0UL //Access:RW   DataWidth:0x9    // Bandwidth Typical L for VQ17 Read requests.
+#define PSWRQ2_REG_BW_RD_L18                                                                                 0x2406d4UL //Access:RW   DataWidth:0x9    // Bandwidth Typical L for VQ18 Read requests.
+#define PSWRQ2_REG_BW_RD_L19                                                                                 0x2406d8UL //Access:RW   DataWidth:0x9    // Bandwidth Typical L for VQ19 Read requests.
+#define PSWRQ2_REG_BW_RD_L20                                                                                 0x2406dcUL //Access:RW   DataWidth:0x9    // Bandwidth Typical L for VQ20 Read requests.
+#define PSWRQ2_REG_BW_WR_L21                                                                                 0x2406e0UL //Access:RW   DataWidth:0x9    // Bandwidth Typical L for VQ21 Write requests.
+#define PSWRQ2_REG_BW_RD_L22                                                                                 0x2406e4UL //Access:RW   DataWidth:0x9    // Bandwidth Typical L for VQ22 Read requests.
+#define PSWRQ2_REG_BW_RD_L23                                                                                 0x2406e8UL //Access:RW   DataWidth:0x9    // Bandwidth Typical L for VQ23 Read requests.
+#define PSWRQ2_REG_BW_RD_L24                                                                                 0x2406ecUL //Access:RW   DataWidth:0x9    // Bandwidth Typical L for VQ24 Read requests.
+#define PSWRQ2_REG_BW_RD_L25                                                                                 0x2406f0UL //Access:RW   DataWidth:0x9    // Bandwidth Typical L for VQ25 Read requests.
+#define PSWRQ2_REG_BW_RD_L26                                                                                 0x2406f4UL //Access:RW   DataWidth:0x9    // Bandwidth Typical L for VQ26 Read requests.
+#define PSWRQ2_REG_BW_RD_L27                                                                                 0x2406f8UL //Access:RW   DataWidth:0x9    // Bandwidth Typical L for VQ27 Read requests.
+#define PSWRQ2_REG_BW_L28                                                                                    0x2406fcUL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRQ2_REG_BW_L28_BW_RD_L28                                                                        (0x1ff<<0) // Bandwidth Typical L for VQ28 Read requests.
+  #define PSWRQ2_REG_BW_L28_BW_RD_L28_SHIFT                                                                  0
+  #define PSWRQ2_REG_BW_L28_BW_WR_L28                                                                        (0x1ff<<9) // Bandwidth Typical L for VQ28 Write requests.
+  #define PSWRQ2_REG_BW_L28_BW_WR_L28_SHIFT                                                                  9
+#define PSWRQ2_REG_BW_WR_L29                                                                                 0x240700UL //Access:RW   DataWidth:0x9    // Bandwidth Typical L for VQ29 Write requests.
+#define PSWRQ2_REG_BW_WR_L30                                                                                 0x240704UL //Access:RW   DataWidth:0x9    // Bandwidth Typical L for VQ30 Write requests.
+#define PSWRQ2_REG_BW_L31                                                                                    0x240708UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRQ2_REG_BW_L31_BW_RD_L31                                                                        (0x1ff<<0) // Bandwidth Typical L for VQ31 Read requests.
+  #define PSWRQ2_REG_BW_L31_BW_RD_L31_SHIFT                                                                  0
+  #define PSWRQ2_REG_BW_L31_BW_WR_L31                                                                        (0x1ff<<9) // Bandwidth Typical L for VQ31 Write requests.
+  #define PSWRQ2_REG_BW_L31_BW_WR_L31_SHIFT                                                                  9
+#define PSWRQ2_REG_BW_RD                                                                                     0x24070cUL //Access:RW   DataWidth:0x1c   // Multi Field Register.
+  #define PSWRQ2_REG_BW_RD_RD_BW_ADD                                                                         (0x3ff<<0) // Bandwidth addition for read requests in the read write arbiter.
+  #define PSWRQ2_REG_BW_RD_RD_BW_ADD_SHIFT                                                                   0
+  #define PSWRQ2_REG_BW_RD_RD_BW_UBOUND                                                                      (0x1ff<<10) // Bandwidth upperbound for read requests in the read write arbiter.
+  #define PSWRQ2_REG_BW_RD_RD_BW_UBOUND_SHIFT                                                                10
+  #define PSWRQ2_REG_BW_RD_RD_BW_L                                                                           (0x1ff<<19) // Bandwidth Typical L for read requests in the read write arbiter.
+  #define PSWRQ2_REG_BW_RD_RD_BW_L_SHIFT                                                                     19
+#define PSWRQ2_REG_BW_WR                                                                                     0x240710UL //Access:RW   DataWidth:0x1c   // Multi Field Register.
+  #define PSWRQ2_REG_BW_WR_WR_BW_ADD                                                                         (0x3ff<<0) // Bandwidth addition for write requests in the read write arbiter.
+  #define PSWRQ2_REG_BW_WR_WR_BW_ADD_SHIFT                                                                   0
+  #define PSWRQ2_REG_BW_WR_WR_BW_UBOUND                                                                      (0x1ff<<10) // Bandwidth upperbound for write requests in the read write arbiter.
+  #define PSWRQ2_REG_BW_WR_WR_BW_UBOUND_SHIFT                                                                10
+  #define PSWRQ2_REG_BW_WR_WR_BW_L                                                                           (0x1ff<<19) // Bandwidth Typical L for write requests in the read write arbiter.
+  #define PSWRQ2_REG_BW_WR_WR_BW_L_SHIFT                                                                     19
+#define PSWRQ2_REG_BW_CREDIT                                                                                 0x240714UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PSWRQ2_REG_BW_CREDIT_READ_CREDIT                                                                   (0xf<<0) // Indicates the number of credits for read sub-requests in th requester glue interface.
+  #define PSWRQ2_REG_BW_CREDIT_READ_CREDIT_SHIFT                                                             0
+  #define PSWRQ2_REG_BW_CREDIT_WRITE_CREDIT                                                                  (0xf<<4) // Indicates the number of credits for write sub-requests in th requester glue interface.
+  #define PSWRQ2_REG_BW_CREDIT_WRITE_CREDIT_SHIFT                                                            4
+#define PSWRQ2_REG_L2P_TM                                                                                    0x240718UL //Access:RW   DataWidth:0x5    // Tm input for l2p memory.
+#define PSWRQ2_REG_SLOW_TH                                                                                   0x24071cUL //Access:RW   DataWidth:0x8    // When number of free entries in the context ram will be lower than this;the input clients arbiter will work in a slower pace.
+#define PSWRQ2_REG_PDR_LIMIT                                                                                 0x240720UL //Access:RW   DataWidth:0xe    // Pending read limiter threshold; in Dwords.
+#define PSWRQ2_REG_DBG_HEAD_MUX_SEL                                                                          0x240724UL //Access:RW   DataWidth:0x5    // Sets which vq head pointer to see out of queues 0-31.
+#define PSWRQ2_REG_DBG_TAIL_MUX_SEL                                                                          0x240728UL //Access:RW   DataWidth:0x5    // Sets which vq tail pointer to see out of queues 0-31.
+#define PSWRQ2_REG_L2P_MODE                                                                                  0x24072cUL //Access:RW   DataWidth:0x1    // Will determine how the logical address is calculated; 0: as in E1; 1:with new algorithm.
+#define PSWRQ2_REG_DRAM_ALIGN_SEL                                                                            0x240730UL //Access:RW   DataWidth:0x1    // When set the new alignment method (E2) will be applied; when reset the original alignment method (E1 E1H) will be applied.
+#define PSWRQ2_REG_CXR_RAM0_TM                                                                               0x240734UL //Access:RW   DataWidth:0x8    // TM bits for cxr ram0.
+#define PSWRQ2_REG_CXR_RAM1_TM                                                                               0x240738UL //Access:RW   DataWidth:0x8    // TM bits for cxr ram1.
+#define PSWRQ2_REG_VQ_RD_DISABLE                                                                             0x24073cUL //Access:R    DataWidth:0xc    // Vq read disable as wdone was not received yet for the wr request that was sent {vq1 ; vq2 ; vq3 ; vq6 ; vq7 ; vq8 ; vq9 ; vq10 ; vq11 ; vq14; vq28; vq31}.
+#define PSWRQ2_REG_QC_REG1                                                                                   0x240740UL //Access:R    DataWidth:0x20   // 
+#define PSWRQ2_REG_QC_REG2                                                                                   0x240744UL //Access:R    DataWidth:0x20   // 
+#define PSWRQ2_REG_QC_VIQ_1ENTRY                                                                             0x240748UL //Access:R    DataWidth:0x20   // 
+#define PSWRQ2_REG_QC_HOQ_IS_LOGICAL                                                                         0x24074cUL //Access:R    DataWidth:0x20   // 
+#define PSWRQ2_REG_QC_VIQ_TAIL_V                                                                             0x240750UL //Access:R    DataWidth:0x20   // 
+#define PSWRQ2_REG_QC_VIQ_HEAD_V                                                                             0x240754UL //Access:R    DataWidth:0x20   // 
+#define PSWRQ2_REG_QC_VIQ_31_28_TAIL                                                                         0x240758UL //Access:R    DataWidth:0x20   // 
+#define PSWRQ2_REG_QC_VIQ_27_24_TAIL                                                                         0x24075cUL //Access:R    DataWidth:0x20   // 
+#define PSWRQ2_REG_QC_VIQ_23_20_TAIL                                                                         0x240760UL //Access:R    DataWidth:0x20   // 
+#define PSWRQ2_REG_QC_VIQ_19_16_TAIL                                                                         0x240764UL //Access:R    DataWidth:0x20   // 
+#define PSWRQ2_REG_QC_VIQ_15_12_TAIL                                                                         0x240768UL //Access:R    DataWidth:0x20   // 
+#define PSWRQ2_REG_QC_VIQ_11_8_TAIL                                                                          0x24076cUL //Access:R    DataWidth:0x20   // 
+#define PSWRQ2_REG_QC_VIQ_7_4_TAIL                                                                           0x240770UL //Access:R    DataWidth:0x20   // 
+#define PSWRQ2_REG_QC_VIQ_3_0_TAIL                                                                           0x240774UL //Access:R    DataWidth:0x20   // 
+#define PSWRQ2_REG_QC_VIQ_31_28_HEAD                                                                         0x240778UL //Access:R    DataWidth:0x20   // 
+#define PSWRQ2_REG_QC_VIQ_27_24_HEAD                                                                         0x24077cUL //Access:R    DataWidth:0x20   // 
+#define PSWRQ2_REG_QC_VIQ_23_20_HEAD                                                                         0x240780UL //Access:R    DataWidth:0x20   // 
+#define PSWRQ2_REG_QC_VIQ_19_16_HEAD                                                                         0x240784UL //Access:R    DataWidth:0x20   // 
+#define PSWRQ2_REG_QC_VIQ_15_12_HEAD                                                                         0x240788UL //Access:R    DataWidth:0x20   // 
+#define PSWRQ2_REG_QC_VIQ_11_8_HEAD                                                                          0x24078cUL //Access:R    DataWidth:0x20   // 
+#define PSWRQ2_REG_QC_VIQ_7_4_HEAD                                                                           0x240790UL //Access:R    DataWidth:0x20   // 
+#define PSWRQ2_REG_QC_VIQ_3_0_HEAD                                                                           0x240794UL //Access:R    DataWidth:0x20   // 
+#define PSWRQ2_REG_BW_RD_ADD_TREQ                                                                            0x240798UL //Access:RW   DataWidth:0xa    // Bandwidth addition to VQ TREQ read requests.
+#define PSWRQ2_REG_BW_RD_UBOUND_TREQ                                                                         0x24079cUL //Access:RW   DataWidth:0x9    // Bandwidth upper bound to VQ TREQ read requests.
+#define PSWRQ2_REG_BW_RD_L_TREQ                                                                              0x2407a0UL //Access:RW   DataWidth:0x9    // Bandwidth Typical L to VQ TREQ read requests.
+#define PSWRQ2_REG_BW_WR_ADD_ICPL                                                                            0x2407a4UL //Access:RW   DataWidth:0xa    // Bandwidth addition to VQ ICPL write requests.
+#define PSWRQ2_REG_BW_WR_UBOUND_ICPL                                                                         0x2407a8UL //Access:RW   DataWidth:0x9    // Bandwidth upper bound to VQ ICPL write requests.
+#define PSWRQ2_REG_BW_WR_L_ICPL                                                                              0x2407acUL //Access:RW   DataWidth:0x9    // Bandwidth Typical L to VQ ICPL write requests.
+#define PSWRQ2_REG_ATC_USDM_FLAGS                                                                            0x2407b0UL //Access:RW   DataWidth:0x4    // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
+#define PSWRQ2_REG_ATC_USDMDP_FLAGS                                                                          0x2407b4UL //Access:RW   DataWidth:0x4    // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
+#define PSWRQ2_REG_ATC_TSDM_FLAGS                                                                            0x2407b8UL //Access:RW   DataWidth:0x4    // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
+#define PSWRQ2_REG_ATC_XSDM_FLAGS                                                                            0x2407bcUL //Access:RW   DataWidth:0x4    // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
+#define PSWRQ2_REG_ATC_DMAE_FLAGS                                                                            0x2407c0UL //Access:RW   DataWidth:0x4    // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
+#define PSWRQ2_REG_ATC_CDUWR_FLAGS                                                                           0x2407c4UL //Access:RW   DataWidth:0x4    // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
+#define PSWRQ2_REG_ATC_CDURD_FLAGS                                                                           0x2407c8UL //Access:RW   DataWidth:0x4    // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
+#define PSWRQ2_REG_ATC_PBF_FLAGS                                                                             0x2407ccUL //Access:RW   DataWidth:0x4    // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
+#define PSWRQ2_REG_ATC_QM_FLAGS                                                                              0x2407d0UL //Access:RW   DataWidth:0x4    // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
+#define PSWRQ2_REG_ATC_TM_FLAGS                                                                              0x2407d4UL //Access:RW   DataWidth:0x4    // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
+#define PSWRQ2_REG_ATC_SRC_FLAGS                                                                             0x2407d8UL //Access:RW   DataWidth:0x4    // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
+#define PSWRQ2_REG_ATC_DBG_FLAGS                                                                             0x2407dcUL //Access:RW   DataWidth:0x4    // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
+#define PSWRQ2_REG_ATC_M2P_FLAGS                                                                             0x2407e0UL //Access:RW   DataWidth:0x4    // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
+#define PSWRQ2_REG_ATC_PTU_FLAGS                                                                             0x2407e4UL //Access:RW   DataWidth:0x4    // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
+#define PSWRQ2_REG_ATC_HC_FLAGS                                                                              0x2407e8UL //Access:RW   DataWidth:0x4    // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
+#define PSWRQ2_REG_ATC_VQ_ENABLE                                                                             0x2407ecUL //Access:RW   DataWidth:0x20   // ATC VQ enable bits. When set - SR from the VQ can send ATC lookup request to the ATC (assuming all other conditions are met). When reset - all SR-s from the VQ will NOT go through the ATC. b0 - VQ0; b1 - VQ1; b30 - VQ30; b31 - reserved (should be filled with zeroes).
+#define PSWRQ2_REG_ATC_INTERNAL_ATS_ENABLE                                                                   0x2407f0UL //Access:RW   DataWidth:0x2    // ATC enable values per PF as follows: b0 - PF enable; b1 - VF enable; PF enable bit is relevant when VF_Valid (in the request) bit is 0; VF enable bit is relevant when VF_Valid bit is 1.
+#define PSWRQ2_REG_ATC_INTERNAL_ATS_ENABLE_ALL                                                               0x2407f4UL //Access:R    DataWidth:0x20   // Concatenated values of rq_atc_internal_ats_enable as follows: b0 - PF0; b1 - VF0; b2 - PF1; b3 - VF1; b30 - PF15 ; b31 - VF15;.
+#define PSWRQ2_REG_ATC_VQ_GO_TRANSLATED                                                                      0x2407f8UL //Access:RW   DataWidth:0x20   // DEBUG ONLY. bit per VQ. go translated set means that SR of the matched VQ will be always sent to the GLUE with the at_valid=1 indication (see atc_code in PSWRQ-PGLUE interface for more details). In that case the address will be delivered by the chip (and not by the ATC). This mode will be used mainly for debug and the other configurations must make sure that ATC will never be used for that VQ while the go_translated bit for that VQ is set. when reset means that the at_valid indication will be determined according to the ATC.
+#define PSWRQ2_REG_ATC_GLOBAL_ENABLE                                                                         0x2407fcUL //Access:RW   DataWidth:0x1    // Global ATC enable bit. when reset all ATC logic is disabled within the PSWRQ. The value of this register must be the same as RD_ATC_GLOBAL_ENABLE. This value must be '1' when ATC capability is enabled in PCIe core.
+#define PSWRQ2_REG_CLOSE_GATE_VQ_LSB_EN                                                                      0x240800UL //Access:RW   DataWidth:0x20   // VQ-s that are enabled (i.e. can be chosen by the GARB) in close the gates scenario; VQ32 = TREQ; VQ33 = ICPL; the original E4 plan is to allow IGU TREQ & ICPL requests to be chosen in such scenario.
+#define PSWRQ2_REG_CLOSE_GATE_VQ_MSB_EN                                                                      0x240804UL //Access:RW   DataWidth:0x2    // VQ-s that are enabled (i.e. can be chosen by the GARB) in close the gates scenario; VQ32 = TREQ; VQ33 = ICPL; the original E4 plan is to allow IGU TREQ & ICPL requests to be chosen in such scenario.
+#define PSWRQ2_REG_STALL_MEM_VQ_LSB_EN                                                                       0x240808UL //Access:RW   DataWidth:0x20   // VQ-s that are enabled (i.e. can be chosen by the GARB) in stall mem scenario; VQ32 = TREQ; VQ33 = ICPL; the original E4 plan is to allow IGU requests to be chosen in such scenario.
+#define PSWRQ2_REG_STALL_MEM_VQ_MSB_EN                                                                       0x24080cUL //Access:RW   DataWidth:0x2    // VQ-s that are enabled (i.e. can be chosen by the GARB) in stall mem scenario; VQ32 = TREQ; VQ33 = ICPL; the original E4 plan is to allow IGU requests to be chosen in such scenario.
+#define PSWRQ2_REG_STALL_INT_VQ_LSB_EN                                                                       0x240810UL //Access:RW   DataWidth:0x20   // VQ-s that are enabled (i.e. can be chosen by the GARB) in stall int scenario; VQ32 = TREQ; VQ33 = ICPL; the original E4 plan is to allow non-IGU requests to be chosen in such scenario.
+#define PSWRQ2_REG_STALL_INT_VQ_MSB_EN                                                                       0x240814UL //Access:RW   DataWidth:0x2    // VQ-s that are enabled (i.e. can be chosen by the GARB) in stall int scenario; VQ32 = TREQ; VQ33 = ICPL; the original E4 plan is to allow non-IGU requests to be chosen in such scenario.
+#define PSWRQ2_REG_TREQ_FIFO_FILL_LVL                                                                        0x240818UL //Access:R    DataWidth:0x6    // The fill level of the TREQ fifo.
+#define PSWRQ2_REG_ICPL_FIFO_FILL_LVL                                                                        0x24081cUL //Access:R    DataWidth:0x3    // The fill level of the ICPL fifo.
+#define PSWRQ2_REG_ATC_TREQ_FIFO_TM                                                                          0x240820UL //Access:RW   DataWidth:0x2    // NOT USED.
+#define PSWRQ2_REG_ASSERT_IF_ILT_FAIL                                                                        0x240824UL //Access:RW   DataWidth:0x1    // When set - assert ilt fail interrupt (rq_elt_addr) in case working in ilt mode and onchip translation fail due to overflow on vah_plus_1st signal (Cont00041628). If reset - interrupt will not assert.
+#define PSWRQ2_REG_HOQ_RAM_RD_REQ                                                                            0x240828UL //Access:RW   DataWidth:0x5    // FOR DBG: read request from the hoq ram; the write data represents the address which is the vqid; in order to read from the hoq ram the read enable register should be set as well (rq_hoq_ram_rd_en); upon read completion (rq_hoq_ram_rd_status =1) data_rd_0 data_rd_1 data_rd_2 and data_rd_3 are ready with the valid values.
+#define PSWRQ2_REG_HOQ_RAM_RD_EN                                                                             0x24082cUL //Access:RW   DataWidth:0x1    // FOR DBG: enable reading from the hoq ram; when set hoq rbc read is enabled; when reset hoq rbc read is disabled (i.e. rq_hoq_ram_rd_req will not have any affect).
+#define PSWRQ2_REG_HOQ_RAM_RD_STATUS                                                                         0x240830UL //Access:R    DataWidth:0x1    // FOR DBG: when set - data rd from hoq ram is completed (i.e. data is ready in data_rd_0 data_rd_1 data_rd2 and data_rd_3); when reset - still waiting for hoq ram read request to be completed).
+#define PSWRQ2_REG_HOQ_RAM_DATA_RD_0                                                                         0x240834UL //Access:R    DataWidth:0x20   // FOR DBG: bits 15:0 length; bits 31:16 request id.
+#define PSWRQ2_REG_HOQ_RAM_DATA_RD_1                                                                         0x240838UL //Access:R    DataWidth:0x20   // FOR DBG: address (32 lsb).
+#define PSWRQ2_REG_HOQ_RAM_DATA_RD_2                                                                         0x24083cUL //Access:R    DataWidth:0x20   // FOR DBG: address (32 msb).
+#define PSWRQ2_REG_HOQ_RAM_DATA_RD_3                                                                         0x240840UL //Access:R    DataWidth:0x20   // FOR DBG: bit 0 relaxed ordering; bit 1 no-snoop; bits 5:2 client id; bit 6 done type; bit 7 resevred; bit 10:8 pfid; bit 11 vf_valid; bit 17:12 vfid; bits 20:18 atc flags; bits 31:21 reserved.
+#define PSWRQ2_REG_SR_CNT_WR_CNT                                                                             0x240844UL //Access:R    DataWidth:0x20   // The total number of WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done.
+#define PSWRQ2_REG_SR_CNT_RD_CNT                                                                             0x240848UL //Access:R    DataWidth:0x20   // The total number of RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done.
+#define PSWRQ2_REG_SR_CNT_PBF_CNT                                                                            0x24084cUL //Access:R    DataWidth:0x20   // The number of PBF RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done.
+#define PSWRQ2_REG_SR_CNT_USDMDP_CNT                                                                         0x240850UL //Access:R    DataWidth:0x20   // The number of USDM-DP WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done.
+#define PSWRQ2_REG_SR_CNT_TREQ_CNT                                                                           0x240854UL //Access:R    DataWidth:0x20   // The number of TREQ SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done.
+#define PSWRQ2_REG_SR_CNT_ICPL_CNT                                                                           0x240858UL //Access:R    DataWidth:0x20   // The number of ICPL SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done.
+#define PSWRQ2_REG_SR_CNT_WR_BYTE_LSB                                                                        0x24085cUL //Access:R    DataWidth:0x20   // The total number of bytes for WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - lsb value.
+#define PSWRQ2_REG_SR_CNT_WR_BYTE_MSB                                                                        0x240860UL //Access:R    DataWidth:0x9    // The total number of bytes for WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - msb value.
+#define PSWRQ2_REG_SR_CNT_RD_BYTE_LSB                                                                        0x240864UL //Access:R    DataWidth:0x20   // The total number of bytes for RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - lsb value.
+#define PSWRQ2_REG_SR_CNT_RD_BYTE_MSB                                                                        0x240868UL //Access:R    DataWidth:0xc    // The total number of bytes for RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - msb value.
+#define PSWRQ2_REG_SR_CNT_PBF_BYTE_LSB                                                                       0x24086cUL //Access:R    DataWidth:0x20   // The number of bytes for PBF RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - lsb value.
+#define PSWRQ2_REG_SR_CNT_PBF_BYTE_MSB                                                                       0x240870UL //Access:R    DataWidth:0xc    // The number of bytes for PBF RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - msb value.
+#define PSWRQ2_REG_SR_CNT_USDMDP_BYTE_LSB                                                                    0x240874UL //Access:R    DataWidth:0x20   // The number of bytes for USDM-DP WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - lsb value.
+#define PSWRQ2_REG_SR_CNT_USDMDP_BYTE_MSB                                                                    0x240878UL //Access:R    DataWidth:0x9    // The number of bytes for USDM-DP WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - msb value.
+#define PSWRQ2_REG_SR_CNT_WINDOW_MODE                                                                        0x24087cUL //Access:RW   DataWidth:0x1    // Counting window mode. 0 - manual window: counting is manually being initiated & stopped by the user through GRC. 1 - configured window: counting occurs according to configured window size.
+#define PSWRQ2_REG_SR_CNT_WINDOW_SIZE                                                                        0x240880UL //Access:RW   DataWidth:0x20   // Determines the size of the counting window. Valid when working in predefined window mode (i.e. Sr_cnt_window_mode = 1).  Granularity of sr_cnt_clk_tickxclk_pci cycles.
+#define PSWRQ2_REG_SR_CNT_WINDOW_VALUE                                                                       0x240884UL //Access:R    DataWidth:0x20   // Global window counter for the current value of the recorded window. Represents the number of sr_cnt_clk_tickxclk_pci cycles from the beginning of counting. NOTE: beginning of counting is determined according to Sr_cnt_start_mode.
+#define PSWRQ2_REG_SR_CNT_MANUAL_CMD                                                                         0x240888UL //Access:W    DataWidth:0x1    // Write Only register. The manual window command sent by the user. Valid when working in manual window mode (i.e. Sr_cnt_window_mode = 0). 0 - stop counting. 1 - start counting.
+#define PSWRQ2_REG_SR_CNT_RST                                                                                0x24088cUL //Access:W    DataWidth:0x1    // Write Only register. RBC write command to this reg (any value) will reset the SR counters & the global window counter. In addition it'll move the Sr_cnt_status to idle state.
+#define PSWRQ2_REG_SR_CNT_START_MODE                                                                         0x240890UL //Access:RW   DataWidth:0x1    // Determines the trigger for start counting (for both SR counters & global window counter). 0 - start counting upon any first SR that is sent to the PGLUE. 1 - start counting upon first PBF/USDM-DP SR that is sent to the PGLUE.
+#define PSWRQ2_REG_SR_CNT_ENABLE                                                                             0x240894UL //Access:RW   DataWidth:0x1    // Enables the SR counting mechanism.
+#define PSWRQ2_REG_SR_CNT_CLK_TICK                                                                           0x240898UL //Access:RW   DataWidth:0x3    // The number of clk_pci ticks minus 1 between each increment of the global window counter (i.e. 0 is for 1 clk_pci cycle; 1 is for 2 clk_pci cycles; 7 is for 8 clk_pci cycles).
+#define PSWRQ2_REG_SR_CNT_STATUS                                                                             0x24089cUL //Access:R    DataWidth:0x2    // The status of the SR count mechanism: 0 - idle: ready to start new counting. 1 - ongoing: counting is currently ongoing. 2 - done: counting is completed. SR counters & global window counter are valid.
+#define PSWRQ2_REG_LAST_RD_SR_LOG_0                                                                          0x2408a0UL //Access:R    DataWidth:0x20   // SR address - 32 lsb.
+#define PSWRQ2_REG_LAST_RD_SR_LOG_1                                                                          0x2408a4UL //Access:R    DataWidth:0x20   // SR address - 32 msb.
+#define PSWRQ2_REG_LAST_RD_SR_LOG_2                                                                          0x2408a8UL //Access:R    DataWidth:0x20   // B15-0: reqid; b28-16: SR length; b29 - reserved; b31-30: attributes.
+#define PSWRQ2_REG_LAST_RD_SR_LOG_3                                                                          0x2408acUL //Access:R    DataWidth:0x20   // B3-0: PFID; b4: vf_valid; b12-b5: VFID; b13: first SR; b14: last SR; b19-15: client id; b24-20: vq; b31-25: srid.
+#define PSWRQ2_REG_LAST_RD_SR_LOG_4                                                                          0x2408b0UL //Access:R    DataWidth:0x9    // b1-0: atc code; b3-2: endianity. b8-4: Treq otb entry.
+#define PSWRQ2_REG_LAST_WR_SR_LOG_0                                                                          0x2408b4UL //Access:R    DataWidth:0x20   // SR address - 32 lsb.
+#define PSWRQ2_REG_LAST_WR_SR_LOG_1                                                                          0x2408b8UL //Access:R    DataWidth:0x20   // SR address - 32 msb.
+#define PSWRQ2_REG_LAST_WR_SR_LOG_2                                                                          0x2408bcUL //Access:R    DataWidth:0x20   // B15-0: reqid; b28-16: SR length; b29 - reserved; b31-30: attributes.
+#define PSWRQ2_REG_LAST_WR_SR_LOG_3                                                                          0x2408c0UL //Access:R    DataWidth:0x20   // B3-0: PFID; b4: vf_valid; b12-b5: VFID; b13: first SR; b14: last SR; b19-15: client id; b24-20: vq; b30-25: start offset; b31: usdm err.
+#define PSWRQ2_REG_LAST_WR_SR_LOG_4                                                                          0x2408c4UL //Access:R    DataWidth:0xa    // b1-0: atc code; b2: wdone type; b4-3: endianity; b9-5: Icpl itag index.
+#define PSWRQ2_REG_MSDM_ENTRY_TH                                                                             0x2408c8UL //Access:RW   DataWidth:0x3    // This number indicates how many entries are guaranteed to msdm in the queues.
+#define PSWRQ2_REG_YSDM_ENTRY_TH                                                                             0x2408ccUL //Access:RW   DataWidth:0x3    // This number indicates how many entries are guaranteed to ysdm in the queues.
+#define PSWRQ2_REG_PSDM_ENTRY_TH                                                                             0x2408d0UL //Access:RW   DataWidth:0x3    // This number indicates how many entries are guaranteed to psdm in the queues.
+#define PSWRQ2_REG_MULD_ENTRY_TH                                                                             0x2408d4UL //Access:RW   DataWidth:0x3    // This number indicates how many entries are guaranteed to muld in the queues.
+#define PSWRQ2_REG_PTU_ENTRY_TH                                                                              0x2408d8UL //Access:RW   DataWidth:0x3    // This number indicates how many entries are guaranteed to ptu in the queues.
+#define PSWRQ2_REG_PTU_PCI_ATTR                                                                              0x2408dcUL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PSWRQ2_REG_PTU_PCI_ATTR_PTU_RELAXED                                                                (0x1<<0) // Relaxed oredering attribute for ptu.
+  #define PSWRQ2_REG_PTU_PCI_ATTR_PTU_RELAXED_SHIFT                                                          0
+  #define PSWRQ2_REG_PTU_PCI_ATTR_PTU_NOSNOOP                                                                (0x1<<1) // Nosnoop attribute for ptu.
+  #define PSWRQ2_REG_PTU_PCI_ATTR_PTU_NOSNOOP_SHIFT                                                          1
+#define PSWRQ2_REG_M2P_ENTRY_TH                                                                              0x2408e0UL //Access:RW   DataWidth:0x3    // This number indicates how many entries are guaranteed to m2p in the queues.
+#define PSWRQ2_REG_M2P_PCI_ATTR                                                                              0x2408e4UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PSWRQ2_REG_M2P_PCI_ATTR_M2P_RELAXED                                                                (0x1<<0) // Relaxed oredering attribute for m2p.
+  #define PSWRQ2_REG_M2P_PCI_ATTR_M2P_RELAXED_SHIFT                                                          0
+  #define PSWRQ2_REG_M2P_PCI_ATTR_M2P_NOSNOOP                                                                (0x1<<1) // Nosnoop attribute for m2p.
+  #define PSWRQ2_REG_M2P_PCI_ATTR_M2P_NOSNOOP_SHIFT                                                          1
+#define PSWRQ2_REG_MULD_PCI_ATTR                                                                             0x2408e8UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PSWRQ2_REG_MULD_PCI_ATTR_MULD_RELAXED                                                              (0x1<<0) // Relaxed oredering attribute for muld.
+  #define PSWRQ2_REG_MULD_PCI_ATTR_MULD_RELAXED_SHIFT                                                        0
+  #define PSWRQ2_REG_MULD_PCI_ATTR_MULD_NOSNOOP                                                              (0x1<<1) // Nosnoop attribute for muld.
+  #define PSWRQ2_REG_MULD_PCI_ATTR_MULD_NOSNOOP_SHIFT                                                        1
+#define PSWRQ2_REG_XYLD_ENTRY_TH                                                                             0x2408ecUL //Access:RW   DataWidth:0x3    // This number indicates how many entries are guaranteed to xyld in the queues.
+#define PSWRQ2_REG_XYLD_PCI_ATTR                                                                             0x2408f0UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PSWRQ2_REG_XYLD_PCI_ATTR_XYLD_RELAXED                                                              (0x1<<0) // Relaxed oredering attribute for xyld.
+  #define PSWRQ2_REG_XYLD_PCI_ATTR_XYLD_RELAXED_SHIFT                                                        0
+  #define PSWRQ2_REG_XYLD_PCI_ATTR_XYLD_NOSNOOP                                                              (0x1<<1) // Nosnoop attribute for xyld.
+  #define PSWRQ2_REG_XYLD_PCI_ATTR_XYLD_NOSNOOP_SHIFT                                                        1
+#define PSWRQ2_REG_ATC_MSDM_FLAGS                                                                            0x2408f4UL //Access:RW   DataWidth:0x4    // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
+#define PSWRQ2_REG_ATC_YSDM_FLAGS                                                                            0x2408f8UL //Access:RW   DataWidth:0x4    // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
+#define PSWRQ2_REG_ATC_PSDM_FLAGS                                                                            0x2408fcUL //Access:RW   DataWidth:0x4    // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
+#define PSWRQ2_REG_ATC_MULD_FLAGS                                                                            0x240900UL //Access:RW   DataWidth:0x4    // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
+#define PSWRQ2_REG_ATC_XYLD_FLAGS                                                                            0x240904UL //Access:RW   DataWidth:0x4    // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.
+#define PSWRQ2_REG_RMM_ENABLE                                                                                0x240908UL //Access:RW   DataWidth:0x1    // Debug only. Writing this register from 0 to 1 enables the roundtrip measurement mechanism and resets the registers latest_rtt ,max_hold_rtt, min_hold_rtt, num_of_measurements.
+#define PSWRQ2_REG_LATEST_RTT                                                                                0x24090cUL //Access:R    DataWidth:0x20   // Debug only. Round trip measurement of latest request that was measured. Measured in clk_pci cycles (375 MHz).
+#define PSWRQ2_REG_MAX_HOLD_RTT                                                                              0x240910UL //Access:R    DataWidth:0x20   // Debug only. Maximal round trip measurement value from the time rmm_enable register was written with '1'. Measured in clk_pci cycles (375 MHz).
+#define PSWRQ2_REG_MIN_HOLD_RTT                                                                              0x240914UL //Access:R    DataWidth:0x20   // Debug only. Minimal round trip measurement value from the time rmm_enable register was written with '1'. Measured in clk_pci cycles (375 MHz).
+#define PSWRQ2_REG_NUM_OF_MEASUREMENTS                                                                       0x240918UL //Access:R    DataWidth:0x20   // Debug only. Number of round trip measurements done from the time rmm_enable register was written with '1'. When the register reaches its maximal value of 0xffff_ffff it remains there.
+#define PSWRQ2_REG_CLIENT_RTT                                                                                0x24091cUL //Access:RW   DataWidth:0x5    // Debug only. Indicates the client for which PSWRQ measures roundtrip. 0x1f means 'all clients'. This register should be modified when rmm_enable is 0.
+#define PSWRQ2_REG_VQ_RTT                                                                                    0x240920UL //Access:RW   DataWidth:0x6    // Debug only. Indicates the VQ for which PSWRQ measures roundtrip. 0x3f means 'all clients'. This register should be modified when rmm_enable is 0.
+#define PSWRQ2_REG_L2P_SUPRESS_ERR                                                                           0x240924UL //Access:RW   DataWidth:0x2    // In case this register is set, requests belongs to VFs/PF with logic address, will be silently dropped instead of causing close_the_gate_scenario.
+#define PSWRQ2_REG_L2P_ERR_ADD_31_0                                                                          0x240928UL //Access:R    DataWidth:0x20   // Address [31:0] of first request that triggered rq_l2p_vf_err  or rq_elt_addr interrupt.
+#define PSWRQ2_REG_L2P_ERR_ADD_63_32                                                                         0x24092cUL //Access:R    DataWidth:0x20   // Address [63:32] of first request that triggered rq_l2p_vf_err  or rq_elt_addr interrupt.
+#define PSWRQ2_REG_L2P_ERR_DETAILS                                                                           0x240930UL //Access:R    DataWidth:0x1a   // Details of first request that triggered rq_l2p_vf_err  or rq_elt_addr interrupt.  [12:0] - Length in bytes. [16:13] - PFID. [17] - VF_VALID. [25:18] - VFID.
+#define PSWRQ2_REG_L2P_ERR_DETAILS2                                                                          0x240934UL //Access:R    DataWidth:0x1d   // Details of first request that triggered rq_l2p_vf_err  or rq_elt_addr interrupt. [15:0] Request ID. [20:16] client ID. [21] - Error type - 0 - rq_l2p_vf_err; 1 - rq_elt_addr. [22] - w_nr - 0 - read; 1 - write.[27:23]VQID. [28] valid - indicates if there was a request not submitted due to error since the last time this register was cleared.
+#define PSWRQ2_REG_L2P_ERR_DETAILS_CLR                                                                       0x240938UL //Access:W    DataWidth:0x1    // Writing to this register clears rq_l2p_err registers and enables logging new error details.
+#define PSWRQ2_REG_SR_NUM_CFG                                                                                0x24093cUL //Access:RW   DataWidth:0x7    // Debug only: Total number of available PCI read sub-requests. Must be bigger than 1. Normally should not be changed.
+#define PSWRQ2_REG_BLK_NUM_CFG                                                                               0x240940UL //Access:RW   DataWidth:0x9    // Debug only: Total number of available blocks in Tetris Buffer. Must be bigger than 6. Normally should not be changed.
+#define PSWRQ2_REG_MAX_BLKS_VQ0                                                                              0x240944UL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ1                                                                              0x240948UL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ2                                                                              0x24094cUL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ3                                                                              0x240950UL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ4                                                                              0x240954UL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ5                                                                              0x240958UL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ6                                                                              0x24095cUL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ7                                                                              0x240960UL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ8                                                                              0x240964UL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ9                                                                              0x240968UL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ10                                                                             0x24096cUL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ11                                                                             0x240970UL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ12                                                                             0x240974UL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ13                                                                             0x240978UL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ14                                                                             0x24097cUL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ15                                                                             0x240980UL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ16                                                                             0x240984UL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ17                                                                             0x240988UL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ18                                                                             0x24098cUL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ19                                                                             0x240990UL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ20                                                                             0x240994UL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ21                                                                             0x240998UL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ22                                                                             0x24099cUL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ23                                                                             0x2409a0UL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ24                                                                             0x2409a4UL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ25                                                                             0x2409a8UL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ26                                                                             0x2409acUL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ27                                                                             0x2409b0UL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ28                                                                             0x2409b4UL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_MAX_BLKS_VQ29                                                                             0x2409b8UL //Access:RW   DataWidth:0x9    // Not used. VQ29 is not used for read.
+#define PSWRQ2_REG_MAX_BLKS_VQ30                                                                             0x2409bcUL //Access:RW   DataWidth:0x9    // Not used. VQ30 is not used for read.
+#define PSWRQ2_REG_MAX_BLKS_VQ31                                                                             0x2409c0UL //Access:RW   DataWidth:0x9    // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
+#define PSWRQ2_REG_SR_CNT                                                                                    0x2409c4UL //Access:R    DataWidth:0x7    // Debug only: The SR counter - number of unused sub request ids. Field and register name used to be rd.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_0                                                                           0x2409c8UL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_1                                                                           0x2409ccUL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_2                                                                           0x2409d0UL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_3                                                                           0x2409d4UL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_4                                                                           0x2409d8UL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_5                                                                           0x2409dcUL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_6                                                                           0x2409e0UL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_7                                                                           0x2409e4UL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_8                                                                           0x2409e8UL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_9                                                                           0x2409ecUL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_10                                                                          0x2409f0UL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_11                                                                          0x2409f4UL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_12                                                                          0x2409f8UL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_13                                                                          0x2409fcUL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_14                                                                          0x240a00UL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_15                                                                          0x240a04UL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_16                                                                          0x240a08UL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_17                                                                          0x240a0cUL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_18                                                                          0x240a10UL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_19                                                                          0x240a14UL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_20                                                                          0x240a18UL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_21                                                                          0x240a1cUL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_22                                                                          0x240a20UL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_23                                                                          0x240a24UL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_24                                                                          0x240a28UL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_25                                                                          0x240a2cUL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_26                                                                          0x240a30UL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_27                                                                          0x240a34UL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_28                                                                          0x240a38UL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_29                                                                          0x240a3cUL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_30                                                                          0x240a40UL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_SR_CNT_PER_VQ_31                                                                          0x240a44UL //Access:R    DataWidth:0x7    // Debug only: The SR counter per vq.
+#define PSWRQ2_REG_BLK_CNT                                                                                   0x240a48UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter - number of unused block ids. Field and register name used to be rd.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_0                                                                          0x240a4cUL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_1                                                                          0x240a50UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_2                                                                          0x240a54UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_3                                                                          0x240a58UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_4                                                                          0x240a5cUL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_5                                                                          0x240a60UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_6                                                                          0x240a64UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_7                                                                          0x240a68UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_8                                                                          0x240a6cUL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_9                                                                          0x240a70UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_10                                                                         0x240a74UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_11                                                                         0x240a78UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_12                                                                         0x240a7cUL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_13                                                                         0x240a80UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_14                                                                         0x240a84UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_15                                                                         0x240a88UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_16                                                                         0x240a8cUL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_17                                                                         0x240a90UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_18                                                                         0x240a94UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_19                                                                         0x240a98UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_20                                                                         0x240a9cUL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_21                                                                         0x240aa0UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_22                                                                         0x240aa4UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_23                                                                         0x240aa8UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_24                                                                         0x240aacUL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_25                                                                         0x240ab0UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_26                                                                         0x240ab4UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_27                                                                         0x240ab8UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_28                                                                         0x240abcUL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_29                                                                         0x240ac0UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_30                                                                         0x240ac4UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_BLK_CNT_PER_VQ_31                                                                         0x240ac8UL //Access:R    DataWidth:0x9    // Debug only: The blocks counter per vq.
+#define PSWRQ2_REG_CNT_BYTE_0                                                                                0x240accUL //Access:R    DataWidth:0xe    // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_BYTE_1                                                                                0x240ad0UL //Access:R    DataWidth:0xe    // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_BYTE_2                                                                                0x240ad4UL //Access:R    DataWidth:0xe    // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_BYTE_3                                                                                0x240ad8UL //Access:R    DataWidth:0xe    // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_BYTE_4                                                                                0x240adcUL //Access:R    DataWidth:0xe    // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_BYTE_5                                                                                0x240ae0UL //Access:R    DataWidth:0xe    // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_BYTE_6                                                                                0x240ae4UL //Access:R    DataWidth:0xe    // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_BYTE_7                                                                                0x240ae8UL //Access:R    DataWidth:0xe    // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_BYTE_8                                                                                0x240aecUL //Access:R    DataWidth:0xe    // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_BYTE_9                                                                                0x240af0UL //Access:R    DataWidth:0xe    // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_BYTE_10                                                                               0x240af4UL //Access:R    DataWidth:0xe    // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_BYTE_11                                                                               0x240af8UL //Access:R    DataWidth:0xe    // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_BYTE_12                                                                               0x240afcUL //Access:R    DataWidth:0xe    // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_BYTE_13                                                                               0x240b00UL //Access:R    DataWidth:0xe    // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_BYTE_14                                                                               0x240b04UL //Access:R    DataWidth:0xe    // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_EOP_0                                                                                 0x240b08UL //Access:R    DataWidth:0x8    // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_EOP_1                                                                                 0x240b0cUL //Access:R    DataWidth:0x8    // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_EOP_2                                                                                 0x240b10UL //Access:R    DataWidth:0x8    // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_EOP_3                                                                                 0x240b14UL //Access:R    DataWidth:0x8    // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_EOP_4                                                                                 0x240b18UL //Access:R    DataWidth:0x8    // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_EOP_5                                                                                 0x240b1cUL //Access:R    DataWidth:0x8    // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_EOP_6                                                                                 0x240b20UL //Access:R    DataWidth:0x8    // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_EOP_7                                                                                 0x240b24UL //Access:R    DataWidth:0x8    // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_EOP_8                                                                                 0x240b28UL //Access:R    DataWidth:0x8    // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_EOP_9                                                                                 0x240b2cUL //Access:R    DataWidth:0x8    // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_EOP_10                                                                                0x240b30UL //Access:R    DataWidth:0x8    // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_EOP_11                                                                                0x240b34UL //Access:R    DataWidth:0x8    // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_EOP_12                                                                                0x240b38UL //Access:R    DataWidth:0x8    // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_EOP_13                                                                                0x240b3cUL //Access:R    DataWidth:0x8    // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_CNT_EOP_14                                                                                0x240b40UL //Access:R    DataWidth:0x8    // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.
+#define PSWRQ2_REG_MAX_SRS_VQ0                                                                               0x240b44UL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ1                                                                               0x240b48UL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ2                                                                               0x240b4cUL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ3                                                                               0x240b50UL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ4                                                                               0x240b54UL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ5                                                                               0x240b58UL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ6                                                                               0x240b5cUL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ7                                                                               0x240b60UL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ8                                                                               0x240b64UL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ9                                                                               0x240b68UL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ10                                                                              0x240b6cUL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ11                                                                              0x240b70UL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ12                                                                              0x240b74UL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ13                                                                              0x240b78UL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ14                                                                              0x240b7cUL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ15                                                                              0x240b80UL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ16                                                                              0x240b84UL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ17                                                                              0x240b88UL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ18                                                                              0x240b8cUL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ19                                                                              0x240b90UL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ20                                                                              0x240b94UL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ21                                                                              0x240b98UL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ22                                                                              0x240b9cUL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ23                                                                              0x240ba0UL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ24                                                                              0x240ba4UL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ25                                                                              0x240ba8UL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ26                                                                              0x240bacUL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ27                                                                              0x240bb0UL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ28                                                                              0x240bb4UL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ29                                                                              0x240bb8UL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ30                                                                              0x240bbcUL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_MAX_SRS_VQ31                                                                              0x240bc0UL //Access:RW   DataWidth:0x7    // The maximum number of sub-requests that can be allocated for this vq.
+#define PSWRQ2_REG_REQIF_DEL_DELAY                                                                           0x240bc4UL //Access:RW   DataWidth:0x3    // Number of delay cycles on the reqif del indication.
+#define PSWRQ2_REG_L2P_CLOSE_GATE_STS                                                                        0x240bc8UL //Access:RW   DataWidth:0x1    // L2P error close the gate status register.
+#define PSWRQ2_REG_MISC_CLOSE_GATE_STS                                                                       0x240bccUL //Access:R    DataWidth:0x1    // MISC close the gate status register. 1 indicates the gates are closed.
+#define PSWRQ2_REG_MISC_STALL_MEM_STS                                                                        0x240bd0UL //Access:R    DataWidth:0x1    // MISC stall mem status register. 1 indicates stall mem is active.
+#define PSWRQ2_REG_GARB_STRICT_PRIORITY_FOR_READS                                                            0x240bd4UL //Access:RW   DataWidth:0x1    // GARB config: 1 indicates read SRs have strict priority over write SRs in RW arbiter.
+#define PSWRQ2_REG_GARB_NEGATIVE_BWC_MODE                                                                    0x240bd8UL //Access:RW   DataWidth:0x1    // GARB config: 1 indicates BWCs can become negative. Clients with negative BWCs are not chosen. Default value: 1.
+#define PSWRQ2_REG_GARB_GNT_ABOVE_LIMIT_ONLY_MODE                                                            0x240bdcUL //Access:RW   DataWidth:0x1    // GARB config: 1 indicates that only clients with BWC greater or equal to Li are chosen. 0 indicates that clients with BWC greater or equal to 0 can be chosen if no BWC is greater or equal to Li. Default value: 0. This is a chicken bit in case there are problems/bugs when choosing clients with BWC less than Li.
+#define PSWRQ2_REG_GARB_VQ_2_STRICT_LSB                                                                      0x240be0UL //Access:RW   DataWidth:0x20   // GARB config: mapping of VQ to strict priority: 0 - the VQ is not associated with any strict priority (i.e. the VQ is associated wth the BW counters);  1 - the VQ has strict priority; VQ32 = TREQ; VQ33 = ICPL; NOTE: the VQ-s associated with strict priority slot should match the configuration in garb_strict0_2_vq or garb_strict1_2_vq;.
+#define PSWRQ2_REG_GARB_VQ_2_STRICT_MSB                                                                      0x240be4UL //Access:RW   DataWidth:0x2    // GARB config: mapping of VQ to strict priority: 0 - the VQ is not associated with any strict priority (i.e. the VQ is associated wth the BW counters);  1 - the VQ has strict priority; VQ32 = TREQ; VQ33 = ICPL; NOTE: the VQ-s associated with strict priority slot should match the configuration in garb_strict0_2_vq or garb_strict1_2_vq;.
+#define PSWRQ2_REG_GARB_STRICT0_2_VQ_0                                                                       0x240be8UL //Access:RW   DataWidth:0x7    // GARB config: mapping of strict priority 0 (high priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).
+#define PSWRQ2_REG_GARB_STRICT0_2_VQ_1                                                                       0x240becUL //Access:RW   DataWidth:0x7    // GARB config: mapping of strict priority 0 (high priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).
+#define PSWRQ2_REG_GARB_STRICT0_2_VQ_2                                                                       0x240bf0UL //Access:RW   DataWidth:0x7    // GARB config: mapping of strict priority 0 (high priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).
+#define PSWRQ2_REG_GARB_STRICT0_2_VQ_3                                                                       0x240bf4UL //Access:RW   DataWidth:0x7    // GARB config: mapping of strict priority 0 (high priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).
+#define PSWRQ2_REG_GARB_STRICT0_2_VQ_4                                                                       0x240bf8UL //Access:RW   DataWidth:0x7    // GARB config: mapping of strict priority 0 (high priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).
+#define PSWRQ2_REG_GARB_STRICT0_2_VQ_5                                                                       0x240bfcUL //Access:RW   DataWidth:0x7    // GARB config: mapping of strict priority 0 (high priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).
+#define PSWRQ2_REG_GARB_STRICT0_2_VQ_6                                                                       0x240c00UL //Access:RW   DataWidth:0x7    // GARB config: mapping of strict priority 0 (high priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).
+#define PSWRQ2_REG_GARB_STRICT0_2_VQ_7                                                                       0x240c04UL //Access:RW   DataWidth:0x7    // GARB config: mapping of strict priority 0 (high priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).
+#define PSWRQ2_REG_GARB_STRICT1_2_VQ_0                                                                       0x240c08UL //Access:RW   DataWidth:0x7    // GARB config: mapping of strict priority 1 (low priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).
+#define PSWRQ2_REG_GARB_STRICT1_2_VQ_1                                                                       0x240c0cUL //Access:RW   DataWidth:0x7    // GARB config: mapping of strict priority 1 (low priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).
+#define PSWRQ2_REG_GARB_STRICT1_2_VQ_2                                                                       0x240c10UL //Access:RW   DataWidth:0x7    // GARB config: mapping of strict priority 1 (low priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).
+#define PSWRQ2_REG_GARB_STRICT1_2_VQ_3                                                                       0x240c14UL //Access:RW   DataWidth:0x7    // GARB config: mapping of strict priority 1 (low priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).
+#define PSWRQ2_REG_GARB_STRICT1_2_VQ_4                                                                       0x240c18UL //Access:RW   DataWidth:0x7    // GARB config: mapping of strict priority 1 (low priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).
+#define PSWRQ2_REG_GARB_STRICT1_2_VQ_5                                                                       0x240c1cUL //Access:RW   DataWidth:0x7    // GARB config: mapping of strict priority 1 (low priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).
+#define PSWRQ2_REG_GARB_STRICT1_2_VQ_6                                                                       0x240c20UL //Access:RW   DataWidth:0x7    // GARB config: mapping of strict priority 1 (low priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).
+#define PSWRQ2_REG_GARB_STRICT1_2_VQ_7                                                                       0x240c24UL //Access:RW   DataWidth:0x7    // GARB config: mapping of strict priority 1 (low priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).
+#define PSWRQ2_REG_CREDIT_WR_STS                                                                             0x240c28UL //Access:R    DataWidth:0x1    // The status of the PSWRQ-PGLUE request interface write credit; 0 - no more credit for wr SR-s (i.e. write SR-s cannot be sent to the PGLUE); 1 - credit is greater than 0 for wr SR-s (i.e. more write SR-s can be sent to the PGLUE).
+#define PSWRQ2_REG_CREDIT_RD_STS                                                                             0x240c2cUL //Access:R    DataWidth:0x1    // The status of the PSWRQ-PGLUE request interface read credit; 0 - no more credit for rd SR-s (i.e. read SR-s cannot be sent to the PGLUE); 1 - credit is greater than 0 for rd SR-s (i.e. more read SR-s can be sent to the PGLUE).
+#define PSWRQ2_REG_WAIT_FOR_EOP                                                                              0x240c30UL //Access:RW   DataWidth:0xf    // Per client store_and_forward configuration. When set it will only enable to submit a write request when eop arrived. This can be a workaround for possible bugs in the byte counters. Id-s are based on wr client id-s (taken from pswrq_funcs.v).
+#define PSWRQ2_REG_ADD2Q_2_DELHOQ0_DELAY                                                                     0x240c34UL //Access:RW   DataWidth:0x3    // LSI purpose: the number of [cycles-1] between qc_cmg_add_2_q (indication that new request is written into hoq0) and cmg_qc_del_head (delete request sent by the cmg towards hoq0). This register should be touched unless there is non-expected HW limitation within the QC. value of N means that there are N dead cycles between qc_cmg_add_2_q and cmg_qc_del_head.
+#define PSWRQ2_REG_DELHOQ0_2_DELHOQ0_DELAY_0                                                                 0x240c38UL //Access:RW   DataWidth:0x4    // LSI purpose: the minimum allowed number of [cycles-1] between cmg_qc_del_head (delete request sent by the cmg towards hoq0) and the next cmg_qc_del_head for the same VQ. This register should be touched unless there is non-expected HW limitation within the QC. value of N means that there are N dead cycles between 2 adjacent requests.
+#define PSWRQ2_REG_DELHOQ0_2_DELHOQ0_DELAY_1                                                                 0x240c3cUL //Access:RW   DataWidth:0x4    // LSI purpose: the minimum allowed number of [cycles-1] between cmg_qc_del_head (delete request sent by the cmg towards hoq0) and the next cmg_qc_del_head for different VQ. This register should be touched unless there is non-expected HW limitation within the QC. value of N means that there are N dead cycles between 2 adjacent requests.
+#define PSWRQ2_REG_PDR_CNT                                                                                   0x240c40UL //Access:R    DataWidth:0xe    // For debug and Idle-check use. The value of the PDR counter.
+#define PSWRQ2_REG_CHECK_RESOURCES_FOR_THE_ENTIRE_REQ                                                        0x240c44UL //Access:RW   DataWidth:0x6    // Will be used for OOO clients deadlock prevention. indicating if to submit the first SR of a request only when there are enough SRIDs and blocks for the entire request. bit0: TSDM; bit1: MSDM; bit2: USDM; bit3: XSDM; bit4: YSDM; bit5: PSDM.
+#define PSWRQ2_REG_RW_ORDERING_DISABLE_WR_THR                                                                0x240c48UL //Access:RW   DataWidth:0x6    // LSI purpose: the threshold for the max number of pending wr requests sent to the PGLUE (i.e. sent to the PGLUE and did not receive write done for them from the PGLUE). Upon reaching the threshold no more wr SR-s will be sent by the PSWRQ to the PGLUE until receiving write done for the previous requests.
+#define PSWRQ2_REG_ECO_RESERVED                                                                              0x240c4cUL //Access:RW   DataWidth:0x6    // Debug only: Reserved bits for ECO.
+#define PSWRQ2_REG_L2P_VALIDATE_VFID                                                                         0x240c50UL //Access:RW   DataWidth:0x1    // Enables VFID validate check
+#define PSWRQ2_REG_STEERING_TAG_TABLE                                                                        0x241000UL //Access:RW   DataWidth:0x8    // Steering Tag Table. Used for TPH.
+#define PSWRQ2_REG_STEERING_TAG_TABLE_SIZE_BB                                                                288
+#define PSWRQ2_REG_STEERING_TAG_TABLE_SIZE_K2_E5                                                             368
+#define PSWRQ2_REG_ILT_MEMORY                                                                                0x260000UL //Access:WB   DataWidth:0x35   // Internal lookup table for logical to physical address translation. Re-instantiated in E4 due to size increase.
+#define PSWRQ2_REG_ILT_MEMORY_SIZE_BB                                                                        15200
+#define PSWRQ2_REG_ILT_MEMORY_SIZE_K2_E5                                                                     22000
+#define PSWRQ_REG_DBG_OUT_DATA                                                                               0x280000UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PSWRQ_REG_DBG_OUT_DATA_SIZE                                                                          8
+#define PSWRQ_REG_DBG_SELECT                                                                                 0x280020UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PSWRQ_REG_DBG_DWORD_ENABLE                                                                           0x280024UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PSWRQ_REG_DBG_SHIFT                                                                                  0x280028UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PSWRQ_REG_DBG_FORCE_VALID                                                                            0x28002cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PSWRQ_REG_DBG_FORCE_FRAME                                                                            0x280030UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PSWRQ_REG_DBG_OUT_VALID                                                                              0x280034UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define PSWRQ_REG_DBG_OUT_FRAME                                                                              0x280038UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define PSWRQ_REG_ECO_RESERVED                                                                               0x280060UL //Access:RW   DataWidth:0x6    // Debug only: Reserved bits for ECO.
+#define PSWRQ_REG_INT_STS                                                                                    0x280180UL //Access:R    DataWidth:0x17   // Multi Field Register.
+  #define PSWRQ_REG_INT_STS_ADDRESS_ERROR                                                                    (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSWRQ_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                              0
+  #define PSWRQ_REG_INT_STS_PBF_FIFO_OVERFLOW                                                                (0x1<<1) // Overflow in pbf request input fifo.
+  #define PSWRQ_REG_INT_STS_PBF_FIFO_OVERFLOW_SHIFT                                                          1
+  #define PSWRQ_REG_INT_STS_SRC_FIFO_OVERFLOW                                                                (0x1<<2) // Overflow in src request input fifo.
+  #define PSWRQ_REG_INT_STS_SRC_FIFO_OVERFLOW_SHIFT                                                          2
+  #define PSWRQ_REG_INT_STS_QM_FIFO_OVERFLOW                                                                 (0x1<<3) // Overflow in qm request input fifo.
+  #define PSWRQ_REG_INT_STS_QM_FIFO_OVERFLOW_SHIFT                                                           3
+  #define PSWRQ_REG_INT_STS_TM_FIFO_OVERFLOW                                                                 (0x1<<4) // Overflow in tm request fifo.
+  #define PSWRQ_REG_INT_STS_TM_FIFO_OVERFLOW_SHIFT                                                           4
+  #define PSWRQ_REG_INT_STS_USDM_FIFO_OVERFLOW                                                               (0x1<<5) // Overflow in usdm request input fifo.
+  #define PSWRQ_REG_INT_STS_USDM_FIFO_OVERFLOW_SHIFT                                                         5
+  #define PSWRQ_REG_INT_STS_M2P_FIFO_OVERFLOW                                                                (0x1<<6) // Overflow in m2p request input fifo.
+  #define PSWRQ_REG_INT_STS_M2P_FIFO_OVERFLOW_SHIFT                                                          6
+  #define PSWRQ_REG_INT_STS_XSDM_FIFO_OVERFLOW                                                               (0x1<<7) // Overflow in xsdm request input fifo.
+  #define PSWRQ_REG_INT_STS_XSDM_FIFO_OVERFLOW_SHIFT                                                         7
+  #define PSWRQ_REG_INT_STS_TSDM_FIFO_OVERFLOW                                                               (0x1<<8) // Overflow in tsdm request input fifo.
+  #define PSWRQ_REG_INT_STS_TSDM_FIFO_OVERFLOW_SHIFT                                                         8
+  #define PSWRQ_REG_INT_STS_PTU_FIFO_OVERFLOW                                                                (0x1<<9) // Overflow in ptu request input fifo.
+  #define PSWRQ_REG_INT_STS_PTU_FIFO_OVERFLOW_SHIFT                                                          9
+  #define PSWRQ_REG_INT_STS_CDUWR_FIFO_OVERFLOW                                                              (0x1<<10) // Overflow in cduwr request input fifo.
+  #define PSWRQ_REG_INT_STS_CDUWR_FIFO_OVERFLOW_SHIFT                                                        10
+  #define PSWRQ_REG_INT_STS_CDURD_FIFO_OVERFLOW                                                              (0x1<<11) // Overflow in cdurd request input fifo.
+  #define PSWRQ_REG_INT_STS_CDURD_FIFO_OVERFLOW_SHIFT                                                        11
+  #define PSWRQ_REG_INT_STS_DMAE_FIFO_OVERFLOW                                                               (0x1<<12) // Overflow in dmae request input fifo.
+  #define PSWRQ_REG_INT_STS_DMAE_FIFO_OVERFLOW_SHIFT                                                         12
+  #define PSWRQ_REG_INT_STS_HC_FIFO_OVERFLOW                                                                 (0x1<<13) // Overflow in hc request input fifo.
+  #define PSWRQ_REG_INT_STS_HC_FIFO_OVERFLOW_SHIFT                                                           13
+  #define PSWRQ_REG_INT_STS_DBG_FIFO_OVERFLOW                                                                (0x1<<14) // Overflow in dbg request input fifo.
+  #define PSWRQ_REG_INT_STS_DBG_FIFO_OVERFLOW_SHIFT                                                          14
+  #define PSWRQ_REG_INT_STS_MSDM_FIFO_OVERFLOW                                                               (0x1<<15) // Overflow in msdm request input fifo.
+  #define PSWRQ_REG_INT_STS_MSDM_FIFO_OVERFLOW_SHIFT                                                         15
+  #define PSWRQ_REG_INT_STS_YSDM_FIFO_OVERFLOW                                                               (0x1<<16) // Overflow in ysdm request input fifo.
+  #define PSWRQ_REG_INT_STS_YSDM_FIFO_OVERFLOW_SHIFT                                                         16
+  #define PSWRQ_REG_INT_STS_PSDM_FIFO_OVERFLOW                                                               (0x1<<17) // Overflow in psdm request input fifo.
+  #define PSWRQ_REG_INT_STS_PSDM_FIFO_OVERFLOW_SHIFT                                                         17
+  #define PSWRQ_REG_INT_STS_PRM_FIFO_OVERFLOW                                                                (0x1<<18) // Overflow in prm request input fifo.
+  #define PSWRQ_REG_INT_STS_PRM_FIFO_OVERFLOW_SHIFT                                                          18
+  #define PSWRQ_REG_INT_STS_MULD_FIFO_OVERFLOW                                                               (0x1<<19) // Overflow in muld request input fifo.
+  #define PSWRQ_REG_INT_STS_MULD_FIFO_OVERFLOW_SHIFT                                                         19
+  #define PSWRQ_REG_INT_STS_XYLD_FIFO_OVERFLOW                                                               (0x1<<20) // Overflow in muld request input fifo.
+  #define PSWRQ_REG_INT_STS_XYLD_FIFO_OVERFLOW_SHIFT                                                         20
+  #define PSWRQ_REG_INT_STS_TGFS_FIFO_OVERFLOW_E5                                                            (0x1<<21) // Overflow in tgfs request input fifo.
+  #define PSWRQ_REG_INT_STS_TGFS_FIFO_OVERFLOW_E5_SHIFT                                                      21
+  #define PSWRQ_REG_INT_STS_RGFS_FIFO_OVERFLOW_E5                                                            (0x1<<22) // Overflow in rgfs request input fifo.
+  #define PSWRQ_REG_INT_STS_RGFS_FIFO_OVERFLOW_E5_SHIFT                                                      22
+#define PSWRQ_REG_INT_MASK                                                                                   0x280184UL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define PSWRQ_REG_INT_MASK_ADDRESS_ERROR                                                                   (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.ADDRESS_ERROR .
+  #define PSWRQ_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                             0
+  #define PSWRQ_REG_INT_MASK_PBF_FIFO_OVERFLOW                                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.PBF_FIFO_OVERFLOW .
+  #define PSWRQ_REG_INT_MASK_PBF_FIFO_OVERFLOW_SHIFT                                                         1
+  #define PSWRQ_REG_INT_MASK_SRC_FIFO_OVERFLOW                                                               (0x1<<2) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.SRC_FIFO_OVERFLOW .
+  #define PSWRQ_REG_INT_MASK_SRC_FIFO_OVERFLOW_SHIFT                                                         2
+  #define PSWRQ_REG_INT_MASK_QM_FIFO_OVERFLOW                                                                (0x1<<3) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.QM_FIFO_OVERFLOW .
+  #define PSWRQ_REG_INT_MASK_QM_FIFO_OVERFLOW_SHIFT                                                          3
+  #define PSWRQ_REG_INT_MASK_TM_FIFO_OVERFLOW                                                                (0x1<<4) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.TM_FIFO_OVERFLOW .
+  #define PSWRQ_REG_INT_MASK_TM_FIFO_OVERFLOW_SHIFT                                                          4
+  #define PSWRQ_REG_INT_MASK_USDM_FIFO_OVERFLOW                                                              (0x1<<5) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.USDM_FIFO_OVERFLOW .
+  #define PSWRQ_REG_INT_MASK_USDM_FIFO_OVERFLOW_SHIFT                                                        5
+  #define PSWRQ_REG_INT_MASK_M2P_FIFO_OVERFLOW                                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.M2P_FIFO_OVERFLOW .
+  #define PSWRQ_REG_INT_MASK_M2P_FIFO_OVERFLOW_SHIFT                                                         6
+  #define PSWRQ_REG_INT_MASK_XSDM_FIFO_OVERFLOW                                                              (0x1<<7) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.XSDM_FIFO_OVERFLOW .
+  #define PSWRQ_REG_INT_MASK_XSDM_FIFO_OVERFLOW_SHIFT                                                        7
+  #define PSWRQ_REG_INT_MASK_TSDM_FIFO_OVERFLOW                                                              (0x1<<8) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.TSDM_FIFO_OVERFLOW .
+  #define PSWRQ_REG_INT_MASK_TSDM_FIFO_OVERFLOW_SHIFT                                                        8
+  #define PSWRQ_REG_INT_MASK_PTU_FIFO_OVERFLOW                                                               (0x1<<9) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.PTU_FIFO_OVERFLOW .
+  #define PSWRQ_REG_INT_MASK_PTU_FIFO_OVERFLOW_SHIFT                                                         9
+  #define PSWRQ_REG_INT_MASK_CDUWR_FIFO_OVERFLOW                                                             (0x1<<10) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.CDUWR_FIFO_OVERFLOW .
+  #define PSWRQ_REG_INT_MASK_CDUWR_FIFO_OVERFLOW_SHIFT                                                       10
+  #define PSWRQ_REG_INT_MASK_CDURD_FIFO_OVERFLOW                                                             (0x1<<11) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.CDURD_FIFO_OVERFLOW .
+  #define PSWRQ_REG_INT_MASK_CDURD_FIFO_OVERFLOW_SHIFT                                                       11
+  #define PSWRQ_REG_INT_MASK_DMAE_FIFO_OVERFLOW                                                              (0x1<<12) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.DMAE_FIFO_OVERFLOW .
+  #define PSWRQ_REG_INT_MASK_DMAE_FIFO_OVERFLOW_SHIFT                                                        12
+  #define PSWRQ_REG_INT_MASK_HC_FIFO_OVERFLOW                                                                (0x1<<13) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.HC_FIFO_OVERFLOW .
+  #define PSWRQ_REG_INT_MASK_HC_FIFO_OVERFLOW_SHIFT                                                          13
+  #define PSWRQ_REG_INT_MASK_DBG_FIFO_OVERFLOW                                                               (0x1<<14) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.DBG_FIFO_OVERFLOW .
+  #define PSWRQ_REG_INT_MASK_DBG_FIFO_OVERFLOW_SHIFT                                                         14
+  #define PSWRQ_REG_INT_MASK_MSDM_FIFO_OVERFLOW                                                              (0x1<<15) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.MSDM_FIFO_OVERFLOW .
+  #define PSWRQ_REG_INT_MASK_MSDM_FIFO_OVERFLOW_SHIFT                                                        15
+  #define PSWRQ_REG_INT_MASK_YSDM_FIFO_OVERFLOW                                                              (0x1<<16) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.YSDM_FIFO_OVERFLOW .
+  #define PSWRQ_REG_INT_MASK_YSDM_FIFO_OVERFLOW_SHIFT                                                        16
+  #define PSWRQ_REG_INT_MASK_PSDM_FIFO_OVERFLOW                                                              (0x1<<17) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.PSDM_FIFO_OVERFLOW .
+  #define PSWRQ_REG_INT_MASK_PSDM_FIFO_OVERFLOW_SHIFT                                                        17
+  #define PSWRQ_REG_INT_MASK_PRM_FIFO_OVERFLOW                                                               (0x1<<18) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.PRM_FIFO_OVERFLOW .
+  #define PSWRQ_REG_INT_MASK_PRM_FIFO_OVERFLOW_SHIFT                                                         18
+  #define PSWRQ_REG_INT_MASK_MULD_FIFO_OVERFLOW                                                              (0x1<<19) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.MULD_FIFO_OVERFLOW .
+  #define PSWRQ_REG_INT_MASK_MULD_FIFO_OVERFLOW_SHIFT                                                        19
+  #define PSWRQ_REG_INT_MASK_XYLD_FIFO_OVERFLOW                                                              (0x1<<20) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.XYLD_FIFO_OVERFLOW .
+  #define PSWRQ_REG_INT_MASK_XYLD_FIFO_OVERFLOW_SHIFT                                                        20
+  #define PSWRQ_REG_INT_MASK_TGFS_FIFO_OVERFLOW_E5                                                           (0x1<<21) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.TGFS_FIFO_OVERFLOW .
+  #define PSWRQ_REG_INT_MASK_TGFS_FIFO_OVERFLOW_E5_SHIFT                                                     21
+  #define PSWRQ_REG_INT_MASK_RGFS_FIFO_OVERFLOW_E5                                                           (0x1<<22) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.RGFS_FIFO_OVERFLOW .
+  #define PSWRQ_REG_INT_MASK_RGFS_FIFO_OVERFLOW_E5_SHIFT                                                     22
+#define PSWRQ_REG_INT_STS_WR                                                                                 0x280188UL //Access:WR   DataWidth:0x17   // Multi Field Register.
+  #define PSWRQ_REG_INT_STS_WR_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSWRQ_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                           0
+  #define PSWRQ_REG_INT_STS_WR_PBF_FIFO_OVERFLOW                                                             (0x1<<1) // Overflow in pbf request input fifo.
+  #define PSWRQ_REG_INT_STS_WR_PBF_FIFO_OVERFLOW_SHIFT                                                       1
+  #define PSWRQ_REG_INT_STS_WR_SRC_FIFO_OVERFLOW                                                             (0x1<<2) // Overflow in src request input fifo.
+  #define PSWRQ_REG_INT_STS_WR_SRC_FIFO_OVERFLOW_SHIFT                                                       2
+  #define PSWRQ_REG_INT_STS_WR_QM_FIFO_OVERFLOW                                                              (0x1<<3) // Overflow in qm request input fifo.
+  #define PSWRQ_REG_INT_STS_WR_QM_FIFO_OVERFLOW_SHIFT                                                        3
+  #define PSWRQ_REG_INT_STS_WR_TM_FIFO_OVERFLOW                                                              (0x1<<4) // Overflow in tm request fifo.
+  #define PSWRQ_REG_INT_STS_WR_TM_FIFO_OVERFLOW_SHIFT                                                        4
+  #define PSWRQ_REG_INT_STS_WR_USDM_FIFO_OVERFLOW                                                            (0x1<<5) // Overflow in usdm request input fifo.
+  #define PSWRQ_REG_INT_STS_WR_USDM_FIFO_OVERFLOW_SHIFT                                                      5
+  #define PSWRQ_REG_INT_STS_WR_M2P_FIFO_OVERFLOW                                                             (0x1<<6) // Overflow in m2p request input fifo.
+  #define PSWRQ_REG_INT_STS_WR_M2P_FIFO_OVERFLOW_SHIFT                                                       6
+  #define PSWRQ_REG_INT_STS_WR_XSDM_FIFO_OVERFLOW                                                            (0x1<<7) // Overflow in xsdm request input fifo.
+  #define PSWRQ_REG_INT_STS_WR_XSDM_FIFO_OVERFLOW_SHIFT                                                      7
+  #define PSWRQ_REG_INT_STS_WR_TSDM_FIFO_OVERFLOW                                                            (0x1<<8) // Overflow in tsdm request input fifo.
+  #define PSWRQ_REG_INT_STS_WR_TSDM_FIFO_OVERFLOW_SHIFT                                                      8
+  #define PSWRQ_REG_INT_STS_WR_PTU_FIFO_OVERFLOW                                                             (0x1<<9) // Overflow in ptu request input fifo.
+  #define PSWRQ_REG_INT_STS_WR_PTU_FIFO_OVERFLOW_SHIFT                                                       9
+  #define PSWRQ_REG_INT_STS_WR_CDUWR_FIFO_OVERFLOW                                                           (0x1<<10) // Overflow in cduwr request input fifo.
+  #define PSWRQ_REG_INT_STS_WR_CDUWR_FIFO_OVERFLOW_SHIFT                                                     10
+  #define PSWRQ_REG_INT_STS_WR_CDURD_FIFO_OVERFLOW                                                           (0x1<<11) // Overflow in cdurd request input fifo.
+  #define PSWRQ_REG_INT_STS_WR_CDURD_FIFO_OVERFLOW_SHIFT                                                     11
+  #define PSWRQ_REG_INT_STS_WR_DMAE_FIFO_OVERFLOW                                                            (0x1<<12) // Overflow in dmae request input fifo.
+  #define PSWRQ_REG_INT_STS_WR_DMAE_FIFO_OVERFLOW_SHIFT                                                      12
+  #define PSWRQ_REG_INT_STS_WR_HC_FIFO_OVERFLOW                                                              (0x1<<13) // Overflow in hc request input fifo.
+  #define PSWRQ_REG_INT_STS_WR_HC_FIFO_OVERFLOW_SHIFT                                                        13
+  #define PSWRQ_REG_INT_STS_WR_DBG_FIFO_OVERFLOW                                                             (0x1<<14) // Overflow in dbg request input fifo.
+  #define PSWRQ_REG_INT_STS_WR_DBG_FIFO_OVERFLOW_SHIFT                                                       14
+  #define PSWRQ_REG_INT_STS_WR_MSDM_FIFO_OVERFLOW                                                            (0x1<<15) // Overflow in msdm request input fifo.
+  #define PSWRQ_REG_INT_STS_WR_MSDM_FIFO_OVERFLOW_SHIFT                                                      15
+  #define PSWRQ_REG_INT_STS_WR_YSDM_FIFO_OVERFLOW                                                            (0x1<<16) // Overflow in ysdm request input fifo.
+  #define PSWRQ_REG_INT_STS_WR_YSDM_FIFO_OVERFLOW_SHIFT                                                      16
+  #define PSWRQ_REG_INT_STS_WR_PSDM_FIFO_OVERFLOW                                                            (0x1<<17) // Overflow in psdm request input fifo.
+  #define PSWRQ_REG_INT_STS_WR_PSDM_FIFO_OVERFLOW_SHIFT                                                      17
+  #define PSWRQ_REG_INT_STS_WR_PRM_FIFO_OVERFLOW                                                             (0x1<<18) // Overflow in prm request input fifo.
+  #define PSWRQ_REG_INT_STS_WR_PRM_FIFO_OVERFLOW_SHIFT                                                       18
+  #define PSWRQ_REG_INT_STS_WR_MULD_FIFO_OVERFLOW                                                            (0x1<<19) // Overflow in muld request input fifo.
+  #define PSWRQ_REG_INT_STS_WR_MULD_FIFO_OVERFLOW_SHIFT                                                      19
+  #define PSWRQ_REG_INT_STS_WR_XYLD_FIFO_OVERFLOW                                                            (0x1<<20) // Overflow in muld request input fifo.
+  #define PSWRQ_REG_INT_STS_WR_XYLD_FIFO_OVERFLOW_SHIFT                                                      20
+  #define PSWRQ_REG_INT_STS_WR_TGFS_FIFO_OVERFLOW_E5                                                         (0x1<<21) // Overflow in tgfs request input fifo.
+  #define PSWRQ_REG_INT_STS_WR_TGFS_FIFO_OVERFLOW_E5_SHIFT                                                   21
+  #define PSWRQ_REG_INT_STS_WR_RGFS_FIFO_OVERFLOW_E5                                                         (0x1<<22) // Overflow in rgfs request input fifo.
+  #define PSWRQ_REG_INT_STS_WR_RGFS_FIFO_OVERFLOW_E5_SHIFT                                                   22
+#define PSWRQ_REG_INT_STS_CLR                                                                                0x28018cUL //Access:RC   DataWidth:0x17   // Multi Field Register.
+  #define PSWRQ_REG_INT_STS_CLR_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSWRQ_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                          0
+  #define PSWRQ_REG_INT_STS_CLR_PBF_FIFO_OVERFLOW                                                            (0x1<<1) // Overflow in pbf request input fifo.
+  #define PSWRQ_REG_INT_STS_CLR_PBF_FIFO_OVERFLOW_SHIFT                                                      1
+  #define PSWRQ_REG_INT_STS_CLR_SRC_FIFO_OVERFLOW                                                            (0x1<<2) // Overflow in src request input fifo.
+  #define PSWRQ_REG_INT_STS_CLR_SRC_FIFO_OVERFLOW_SHIFT                                                      2
+  #define PSWRQ_REG_INT_STS_CLR_QM_FIFO_OVERFLOW                                                             (0x1<<3) // Overflow in qm request input fifo.
+  #define PSWRQ_REG_INT_STS_CLR_QM_FIFO_OVERFLOW_SHIFT                                                       3
+  #define PSWRQ_REG_INT_STS_CLR_TM_FIFO_OVERFLOW                                                             (0x1<<4) // Overflow in tm request fifo.
+  #define PSWRQ_REG_INT_STS_CLR_TM_FIFO_OVERFLOW_SHIFT                                                       4
+  #define PSWRQ_REG_INT_STS_CLR_USDM_FIFO_OVERFLOW                                                           (0x1<<5) // Overflow in usdm request input fifo.
+  #define PSWRQ_REG_INT_STS_CLR_USDM_FIFO_OVERFLOW_SHIFT                                                     5
+  #define PSWRQ_REG_INT_STS_CLR_M2P_FIFO_OVERFLOW                                                            (0x1<<6) // Overflow in m2p request input fifo.
+  #define PSWRQ_REG_INT_STS_CLR_M2P_FIFO_OVERFLOW_SHIFT                                                      6
+  #define PSWRQ_REG_INT_STS_CLR_XSDM_FIFO_OVERFLOW                                                           (0x1<<7) // Overflow in xsdm request input fifo.
+  #define PSWRQ_REG_INT_STS_CLR_XSDM_FIFO_OVERFLOW_SHIFT                                                     7
+  #define PSWRQ_REG_INT_STS_CLR_TSDM_FIFO_OVERFLOW                                                           (0x1<<8) // Overflow in tsdm request input fifo.
+  #define PSWRQ_REG_INT_STS_CLR_TSDM_FIFO_OVERFLOW_SHIFT                                                     8
+  #define PSWRQ_REG_INT_STS_CLR_PTU_FIFO_OVERFLOW                                                            (0x1<<9) // Overflow in ptu request input fifo.
+  #define PSWRQ_REG_INT_STS_CLR_PTU_FIFO_OVERFLOW_SHIFT                                                      9
+  #define PSWRQ_REG_INT_STS_CLR_CDUWR_FIFO_OVERFLOW                                                          (0x1<<10) // Overflow in cduwr request input fifo.
+  #define PSWRQ_REG_INT_STS_CLR_CDUWR_FIFO_OVERFLOW_SHIFT                                                    10
+  #define PSWRQ_REG_INT_STS_CLR_CDURD_FIFO_OVERFLOW                                                          (0x1<<11) // Overflow in cdurd request input fifo.
+  #define PSWRQ_REG_INT_STS_CLR_CDURD_FIFO_OVERFLOW_SHIFT                                                    11
+  #define PSWRQ_REG_INT_STS_CLR_DMAE_FIFO_OVERFLOW                                                           (0x1<<12) // Overflow in dmae request input fifo.
+  #define PSWRQ_REG_INT_STS_CLR_DMAE_FIFO_OVERFLOW_SHIFT                                                     12
+  #define PSWRQ_REG_INT_STS_CLR_HC_FIFO_OVERFLOW                                                             (0x1<<13) // Overflow in hc request input fifo.
+  #define PSWRQ_REG_INT_STS_CLR_HC_FIFO_OVERFLOW_SHIFT                                                       13
+  #define PSWRQ_REG_INT_STS_CLR_DBG_FIFO_OVERFLOW                                                            (0x1<<14) // Overflow in dbg request input fifo.
+  #define PSWRQ_REG_INT_STS_CLR_DBG_FIFO_OVERFLOW_SHIFT                                                      14
+  #define PSWRQ_REG_INT_STS_CLR_MSDM_FIFO_OVERFLOW                                                           (0x1<<15) // Overflow in msdm request input fifo.
+  #define PSWRQ_REG_INT_STS_CLR_MSDM_FIFO_OVERFLOW_SHIFT                                                     15
+  #define PSWRQ_REG_INT_STS_CLR_YSDM_FIFO_OVERFLOW                                                           (0x1<<16) // Overflow in ysdm request input fifo.
+  #define PSWRQ_REG_INT_STS_CLR_YSDM_FIFO_OVERFLOW_SHIFT                                                     16
+  #define PSWRQ_REG_INT_STS_CLR_PSDM_FIFO_OVERFLOW                                                           (0x1<<17) // Overflow in psdm request input fifo.
+  #define PSWRQ_REG_INT_STS_CLR_PSDM_FIFO_OVERFLOW_SHIFT                                                     17
+  #define PSWRQ_REG_INT_STS_CLR_PRM_FIFO_OVERFLOW                                                            (0x1<<18) // Overflow in prm request input fifo.
+  #define PSWRQ_REG_INT_STS_CLR_PRM_FIFO_OVERFLOW_SHIFT                                                      18
+  #define PSWRQ_REG_INT_STS_CLR_MULD_FIFO_OVERFLOW                                                           (0x1<<19) // Overflow in muld request input fifo.
+  #define PSWRQ_REG_INT_STS_CLR_MULD_FIFO_OVERFLOW_SHIFT                                                     19
+  #define PSWRQ_REG_INT_STS_CLR_XYLD_FIFO_OVERFLOW                                                           (0x1<<20) // Overflow in muld request input fifo.
+  #define PSWRQ_REG_INT_STS_CLR_XYLD_FIFO_OVERFLOW_SHIFT                                                     20
+  #define PSWRQ_REG_INT_STS_CLR_TGFS_FIFO_OVERFLOW_E5                                                        (0x1<<21) // Overflow in tgfs request input fifo.
+  #define PSWRQ_REG_INT_STS_CLR_TGFS_FIFO_OVERFLOW_E5_SHIFT                                                  21
+  #define PSWRQ_REG_INT_STS_CLR_RGFS_FIFO_OVERFLOW_E5                                                        (0x1<<22) // Overflow in rgfs request input fifo.
+  #define PSWRQ_REG_INT_STS_CLR_RGFS_FIFO_OVERFLOW_E5_SHIFT                                                  22
+#define PSWRQ_REG_PRTY_MASK                                                                                  0x280194UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define PSWRQ_REG_PRTY_MASK_PXP_BUSIP_PARITY                                                               (0x1<<0) // This bit masks, when set, the Parity bit: PSWRQ_REG_PRTY_STS.PXP_BUSIP_PARITY .
+  #define PSWRQ_REG_PRTY_MASK_PXP_BUSIP_PARITY_SHIFT                                                         0
+#define PSWWR_REG_USDM_FULL_TH                                                                               0x29a040UL //Access:RW   DataWidth:0x4    // If number of entries in the usdm fifo is bigger than this number than full will be asserted.
+#define PSWWR_REG_MSDM_FULL_TH                                                                               0x29a044UL //Access:RW   DataWidth:0x4    // If number of entries in the msdm fifo is bigger than this number than full will be asserted.
+#define PSWWR_REG_YSDM_FULL_TH                                                                               0x29a048UL //Access:RW   DataWidth:0x4    // If number of entries in the ysdm fifo is bigger than this number than full will be asserted.
+#define PSWWR_REG_PSDM_FULL_TH                                                                               0x29a04cUL //Access:RW   DataWidth:0x4    // If number of entries in the psdm fifo is bigger than this number than full will be asserted.
+#define PSWWR_REG_XSDM_FULL_TH                                                                               0x29a050UL //Access:RW   DataWidth:0x4    // If number of entries in the xsdm fifo is bigger than this number than full will be asserted.
+#define PSWWR_REG_TSDM_FULL_TH                                                                               0x29a054UL //Access:RW   DataWidth:0x4    // If number of entries in the tsdm fifo is bigger than this number than full will be asserted.
+#define PSWWR_REG_M2P_FULL_TH                                                                                0x29a058UL //Access:RW   DataWidth:0x4    // If number of entries in M2P fifo is bigger than this number than full will be asserted.
+#define PSWWR_REG_QM_FULL_TH                                                                                 0x29a05cUL //Access:RW   DataWidth:0x3    // If number of entries in the qm fifo is bigger than this number than full will be asserted.
+#define PSWWR_REG_TM_FULL_TH                                                                                 0x29a060UL //Access:RW   DataWidth:0x4    // If number of entries in the tm fifo is bigger than this number than full will be asserted.
+#define PSWWR_REG_SRC_FULL_TH                                                                                0x29a064UL //Access:RW   DataWidth:0x4    // If number of entries in the src fifo is bigger than this number than full will be asserted.
+#define PSWWR_REG_DBG_FULL_TH                                                                                0x29a068UL //Access:RW   DataWidth:0x4    // If number of entries in the dbg fifo is bigger than this number than full will be asserted.
+#define PSWWR_REG_HC_FULL_TH                                                                                 0x29a06cUL //Access:RW   DataWidth:0x4    // If number of entries in the hc fifo is bigger than this number than full will be asserted.
+#define PSWWR_REG_DMAE_FULL_TH                                                                               0x29a070UL //Access:RW   DataWidth:0x4    // If number of entries in the dmae input fifo is bigger than this number than full will be asserted.
+#define PSWWR_REG_CDU_FULL_TH                                                                                0x29a074UL //Access:RW   DataWidth:0x4    // If number of entries in the cdu input fifo is bigger than this number than full will be asserted.
+#define PSWWR_REG_USDMDP_FULL_TH                                                                             0x29a078UL //Access:RW   DataWidth:0x4    // If number of entries in the usdmdp input fifo is bigger than this number than full will be asserted.
+#define PSWWR_REG_FIFO_FULL_STATUS                                                                           0x29a07cUL //Access:R    DataWidth:0x12   // Each bit indicates if full is asserted towards the client. The clients order is according to the incrementing client IDs of write clients: 0 - TSDM; 1 - MSDM; 2 - USDM; 3 - XSDM; 4 - YSDM; 5 - PSDM; 6 - QM; 7 - TM; 8 - SRC; 9 - DMAE; 10 - PRM (RDIF); 11 - HC; 12 - CDU; 13 - DBG; 14- M2P; 15 - PRM Secondary; 16 - RGFS; 17 - TGFS;
+#define PSWWR_REG_FIFO_FULL_STICKY                                                                           0x29a080UL //Access:R    DataWidth:0x12   // Each bit indicates if full was asserted since reset towards the client. The clients order is according to the incrementing client IDs of write clients: 0 - TSDM; 1 - MSDM; 2 - USDM; 3 - XSDM; 4 - YSDM; 5 - PSDM; 6 - QM; 7 - TM; 8 - SRC; 9 - DMAE; 10 - PRM (RDIF); 11 - HC; 12 - CDU; 13 - DBG; 14 - M2P; 15- PRM Secondary; 16 - RGFS; 17 - TGFS;
+#define PSWWR_REG_DBG_SELECT                                                                                 0x29a084UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PSWWR_REG_DBG_DWORD_ENABLE                                                                           0x29a088UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PSWWR_REG_DBG_SHIFT                                                                                  0x29a08cUL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PSWWR_REG_DBG_FORCE_VALID                                                                            0x29a090UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PSWWR_REG_DBG_FORCE_FRAME                                                                            0x29a094UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PSWWR_REG_DBG_OUT_DATA                                                                               0x29a0a0UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PSWWR_REG_DBG_OUT_DATA_SIZE                                                                          8
+#define PSWWR_REG_DBG_OUT_VALID                                                                              0x29a0c0UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define PSWWR_REG_DBG_OUT_FRAME                                                                              0x29a0c4UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define PSWWR_REG_ECO_RESERVED                                                                               0x29a0c8UL //Access:RW   DataWidth:0x6    // Debug only: Reserved bits for ECO.
+#define PSWWR_REG_PRM_SEC_FULL_TH_E5                                                                         0x29a0ccUL //Access:RW   DataWidth:0x5    // If number of entries in the PRM Secondary input fifo is bigger than this number than full will be asserted.
+#define PSWWR_REG_RGFS_FULL_TH_E5                                                                            0x29a0d0UL //Access:RW   DataWidth:0x4    // If number of entries in the RGFS input fifo is bigger than this number than full will be asserted.
+#define PSWWR_REG_TGFS_FULL_TH_E5                                                                            0x29a0d4UL //Access:RW   DataWidth:0x4    // If number of entries in the TGFS input fifo is bigger than this number than full will be asserted.
+#define PSWWR_REG_INT_STS                                                                                    0x29a180UL //Access:R    DataWidth:0x13   // Multi Field Register.
+  #define PSWWR_REG_INT_STS_ADDRESS_ERROR                                                                    (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSWWR_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                              0
+  #define PSWWR_REG_INT_STS_SRC_FIFO_OVERFLOW                                                                (0x1<<1) // Overflow in src input fifo.
+  #define PSWWR_REG_INT_STS_SRC_FIFO_OVERFLOW_SHIFT                                                          1
+  #define PSWWR_REG_INT_STS_QM_FIFO_OVERFLOW                                                                 (0x1<<2) // Overflow in qm input fifo.
+  #define PSWWR_REG_INT_STS_QM_FIFO_OVERFLOW_SHIFT                                                           2
+  #define PSWWR_REG_INT_STS_TM_FIFO_OVERFLOW                                                                 (0x1<<3) // Overflow in tm fifo.
+  #define PSWWR_REG_INT_STS_TM_FIFO_OVERFLOW_SHIFT                                                           3
+  #define PSWWR_REG_INT_STS_USDM_FIFO_OVERFLOW                                                               (0x1<<4) // Overflow in usdm input fifo.
+  #define PSWWR_REG_INT_STS_USDM_FIFO_OVERFLOW_SHIFT                                                         4
+  #define PSWWR_REG_INT_STS_USDMDP_FIFO_OVERFLOW                                                             (0x1<<5) // Overflow in usdmdp input fifo.
+  #define PSWWR_REG_INT_STS_USDMDP_FIFO_OVERFLOW_SHIFT                                                       5
+  #define PSWWR_REG_INT_STS_XSDM_FIFO_OVERFLOW                                                               (0x1<<6) // Overflow in xsdm input fifo.
+  #define PSWWR_REG_INT_STS_XSDM_FIFO_OVERFLOW_SHIFT                                                         6
+  #define PSWWR_REG_INT_STS_TSDM_FIFO_OVERFLOW                                                               (0x1<<7) // Overflow in tsdm input fifo.
+  #define PSWWR_REG_INT_STS_TSDM_FIFO_OVERFLOW_SHIFT                                                         7
+  #define PSWWR_REG_INT_STS_CDUWR_FIFO_OVERFLOW                                                              (0x1<<8) // Overflow in cduwr input fifo.
+  #define PSWWR_REG_INT_STS_CDUWR_FIFO_OVERFLOW_SHIFT                                                        8
+  #define PSWWR_REG_INT_STS_DBG_FIFO_OVERFLOW                                                                (0x1<<9) // Overflow in dbg input fifo.
+  #define PSWWR_REG_INT_STS_DBG_FIFO_OVERFLOW_SHIFT                                                          9
+  #define PSWWR_REG_INT_STS_DMAE_FIFO_OVERFLOW                                                               (0x1<<10) // Overflow in dmae input fifo.
+  #define PSWWR_REG_INT_STS_DMAE_FIFO_OVERFLOW_SHIFT                                                         10
+  #define PSWWR_REG_INT_STS_HC_FIFO_OVERFLOW                                                                 (0x1<<11) // Overflow in hc input fifo.
+  #define PSWWR_REG_INT_STS_HC_FIFO_OVERFLOW_SHIFT                                                           11
+  #define PSWWR_REG_INT_STS_MSDM_FIFO_OVERFLOW                                                               (0x1<<12) // Overflow in msdm write input fifo.
+  #define PSWWR_REG_INT_STS_MSDM_FIFO_OVERFLOW_SHIFT                                                         12
+  #define PSWWR_REG_INT_STS_YSDM_FIFO_OVERFLOW                                                               (0x1<<13) // Overflow in ysdm write input fifo.
+  #define PSWWR_REG_INT_STS_YSDM_FIFO_OVERFLOW_SHIFT                                                         13
+  #define PSWWR_REG_INT_STS_PSDM_FIFO_OVERFLOW                                                               (0x1<<14) // Overflow in psdm write input fifo.
+  #define PSWWR_REG_INT_STS_PSDM_FIFO_OVERFLOW_SHIFT                                                         14
+  #define PSWWR_REG_INT_STS_M2P_FIFO_OVERFLOW                                                                (0x1<<15) // Overflow in M2P input fifo.
+  #define PSWWR_REG_INT_STS_M2P_FIFO_OVERFLOW_SHIFT                                                          15
+  #define PSWWR_REG_INT_STS_PRM_SEC_FIFO_OVERFLOW_E5                                                         (0x1<<16) // Overflow in PRM Secondary input fifo.
+  #define PSWWR_REG_INT_STS_PRM_SEC_FIFO_OVERFLOW_E5_SHIFT                                                   16
+  #define PSWWR_REG_INT_STS_RGFS_FIFO_OVERFLOW_E5                                                            (0x1<<17) // Overflow in RGFS input fifo.
+  #define PSWWR_REG_INT_STS_RGFS_FIFO_OVERFLOW_E5_SHIFT                                                      17
+  #define PSWWR_REG_INT_STS_TGFS_FIFO_OVERFLOW_E5                                                            (0x1<<18) // Overflow in TGFS input fifo.
+  #define PSWWR_REG_INT_STS_TGFS_FIFO_OVERFLOW_E5_SHIFT                                                      18
+#define PSWWR_REG_INT_MASK                                                                                   0x29a184UL //Access:RW   DataWidth:0x13   // Multi Field Register.
+  #define PSWWR_REG_INT_MASK_ADDRESS_ERROR                                                                   (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.ADDRESS_ERROR .
+  #define PSWWR_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                             0
+  #define PSWWR_REG_INT_MASK_SRC_FIFO_OVERFLOW                                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.SRC_FIFO_OVERFLOW .
+  #define PSWWR_REG_INT_MASK_SRC_FIFO_OVERFLOW_SHIFT                                                         1
+  #define PSWWR_REG_INT_MASK_QM_FIFO_OVERFLOW                                                                (0x1<<2) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.QM_FIFO_OVERFLOW .
+  #define PSWWR_REG_INT_MASK_QM_FIFO_OVERFLOW_SHIFT                                                          2
+  #define PSWWR_REG_INT_MASK_TM_FIFO_OVERFLOW                                                                (0x1<<3) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.TM_FIFO_OVERFLOW .
+  #define PSWWR_REG_INT_MASK_TM_FIFO_OVERFLOW_SHIFT                                                          3
+  #define PSWWR_REG_INT_MASK_USDM_FIFO_OVERFLOW                                                              (0x1<<4) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.USDM_FIFO_OVERFLOW .
+  #define PSWWR_REG_INT_MASK_USDM_FIFO_OVERFLOW_SHIFT                                                        4
+  #define PSWWR_REG_INT_MASK_USDMDP_FIFO_OVERFLOW                                                            (0x1<<5) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.USDMDP_FIFO_OVERFLOW .
+  #define PSWWR_REG_INT_MASK_USDMDP_FIFO_OVERFLOW_SHIFT                                                      5
+  #define PSWWR_REG_INT_MASK_XSDM_FIFO_OVERFLOW                                                              (0x1<<6) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.XSDM_FIFO_OVERFLOW .
+  #define PSWWR_REG_INT_MASK_XSDM_FIFO_OVERFLOW_SHIFT                                                        6
+  #define PSWWR_REG_INT_MASK_TSDM_FIFO_OVERFLOW                                                              (0x1<<7) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.TSDM_FIFO_OVERFLOW .
+  #define PSWWR_REG_INT_MASK_TSDM_FIFO_OVERFLOW_SHIFT                                                        7
+  #define PSWWR_REG_INT_MASK_CDUWR_FIFO_OVERFLOW                                                             (0x1<<8) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.CDUWR_FIFO_OVERFLOW .
+  #define PSWWR_REG_INT_MASK_CDUWR_FIFO_OVERFLOW_SHIFT                                                       8
+  #define PSWWR_REG_INT_MASK_DBG_FIFO_OVERFLOW                                                               (0x1<<9) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.DBG_FIFO_OVERFLOW .
+  #define PSWWR_REG_INT_MASK_DBG_FIFO_OVERFLOW_SHIFT                                                         9
+  #define PSWWR_REG_INT_MASK_DMAE_FIFO_OVERFLOW                                                              (0x1<<10) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.DMAE_FIFO_OVERFLOW .
+  #define PSWWR_REG_INT_MASK_DMAE_FIFO_OVERFLOW_SHIFT                                                        10
+  #define PSWWR_REG_INT_MASK_HC_FIFO_OVERFLOW                                                                (0x1<<11) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.HC_FIFO_OVERFLOW .
+  #define PSWWR_REG_INT_MASK_HC_FIFO_OVERFLOW_SHIFT                                                          11
+  #define PSWWR_REG_INT_MASK_MSDM_FIFO_OVERFLOW                                                              (0x1<<12) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.MSDM_FIFO_OVERFLOW .
+  #define PSWWR_REG_INT_MASK_MSDM_FIFO_OVERFLOW_SHIFT                                                        12
+  #define PSWWR_REG_INT_MASK_YSDM_FIFO_OVERFLOW                                                              (0x1<<13) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.YSDM_FIFO_OVERFLOW .
+  #define PSWWR_REG_INT_MASK_YSDM_FIFO_OVERFLOW_SHIFT                                                        13
+  #define PSWWR_REG_INT_MASK_PSDM_FIFO_OVERFLOW                                                              (0x1<<14) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.PSDM_FIFO_OVERFLOW .
+  #define PSWWR_REG_INT_MASK_PSDM_FIFO_OVERFLOW_SHIFT                                                        14
+  #define PSWWR_REG_INT_MASK_M2P_FIFO_OVERFLOW                                                               (0x1<<15) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.M2P_FIFO_OVERFLOW .
+  #define PSWWR_REG_INT_MASK_M2P_FIFO_OVERFLOW_SHIFT                                                         15
+  #define PSWWR_REG_INT_MASK_PRM_SEC_FIFO_OVERFLOW_E5                                                        (0x1<<16) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.PRM_SEC_FIFO_OVERFLOW .
+  #define PSWWR_REG_INT_MASK_PRM_SEC_FIFO_OVERFLOW_E5_SHIFT                                                  16
+  #define PSWWR_REG_INT_MASK_RGFS_FIFO_OVERFLOW_E5                                                           (0x1<<17) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.RGFS_FIFO_OVERFLOW .
+  #define PSWWR_REG_INT_MASK_RGFS_FIFO_OVERFLOW_E5_SHIFT                                                     17
+  #define PSWWR_REG_INT_MASK_TGFS_FIFO_OVERFLOW_E5                                                           (0x1<<18) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.TGFS_FIFO_OVERFLOW .
+  #define PSWWR_REG_INT_MASK_TGFS_FIFO_OVERFLOW_E5_SHIFT                                                     18
+#define PSWWR_REG_INT_STS_WR                                                                                 0x29a188UL //Access:WR   DataWidth:0x13   // Multi Field Register.
+  #define PSWWR_REG_INT_STS_WR_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSWWR_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                           0
+  #define PSWWR_REG_INT_STS_WR_SRC_FIFO_OVERFLOW                                                             (0x1<<1) // Overflow in src input fifo.
+  #define PSWWR_REG_INT_STS_WR_SRC_FIFO_OVERFLOW_SHIFT                                                       1
+  #define PSWWR_REG_INT_STS_WR_QM_FIFO_OVERFLOW                                                              (0x1<<2) // Overflow in qm input fifo.
+  #define PSWWR_REG_INT_STS_WR_QM_FIFO_OVERFLOW_SHIFT                                                        2
+  #define PSWWR_REG_INT_STS_WR_TM_FIFO_OVERFLOW                                                              (0x1<<3) // Overflow in tm fifo.
+  #define PSWWR_REG_INT_STS_WR_TM_FIFO_OVERFLOW_SHIFT                                                        3
+  #define PSWWR_REG_INT_STS_WR_USDM_FIFO_OVERFLOW                                                            (0x1<<4) // Overflow in usdm input fifo.
+  #define PSWWR_REG_INT_STS_WR_USDM_FIFO_OVERFLOW_SHIFT                                                      4
+  #define PSWWR_REG_INT_STS_WR_USDMDP_FIFO_OVERFLOW                                                          (0x1<<5) // Overflow in usdmdp input fifo.
+  #define PSWWR_REG_INT_STS_WR_USDMDP_FIFO_OVERFLOW_SHIFT                                                    5
+  #define PSWWR_REG_INT_STS_WR_XSDM_FIFO_OVERFLOW                                                            (0x1<<6) // Overflow in xsdm input fifo.
+  #define PSWWR_REG_INT_STS_WR_XSDM_FIFO_OVERFLOW_SHIFT                                                      6
+  #define PSWWR_REG_INT_STS_WR_TSDM_FIFO_OVERFLOW                                                            (0x1<<7) // Overflow in tsdm input fifo.
+  #define PSWWR_REG_INT_STS_WR_TSDM_FIFO_OVERFLOW_SHIFT                                                      7
+  #define PSWWR_REG_INT_STS_WR_CDUWR_FIFO_OVERFLOW                                                           (0x1<<8) // Overflow in cduwr input fifo.
+  #define PSWWR_REG_INT_STS_WR_CDUWR_FIFO_OVERFLOW_SHIFT                                                     8
+  #define PSWWR_REG_INT_STS_WR_DBG_FIFO_OVERFLOW                                                             (0x1<<9) // Overflow in dbg input fifo.
+  #define PSWWR_REG_INT_STS_WR_DBG_FIFO_OVERFLOW_SHIFT                                                       9
+  #define PSWWR_REG_INT_STS_WR_DMAE_FIFO_OVERFLOW                                                            (0x1<<10) // Overflow in dmae input fifo.
+  #define PSWWR_REG_INT_STS_WR_DMAE_FIFO_OVERFLOW_SHIFT                                                      10
+  #define PSWWR_REG_INT_STS_WR_HC_FIFO_OVERFLOW                                                              (0x1<<11) // Overflow in hc input fifo.
+  #define PSWWR_REG_INT_STS_WR_HC_FIFO_OVERFLOW_SHIFT                                                        11
+  #define PSWWR_REG_INT_STS_WR_MSDM_FIFO_OVERFLOW                                                            (0x1<<12) // Overflow in msdm write input fifo.
+  #define PSWWR_REG_INT_STS_WR_MSDM_FIFO_OVERFLOW_SHIFT                                                      12
+  #define PSWWR_REG_INT_STS_WR_YSDM_FIFO_OVERFLOW                                                            (0x1<<13) // Overflow in ysdm write input fifo.
+  #define PSWWR_REG_INT_STS_WR_YSDM_FIFO_OVERFLOW_SHIFT                                                      13
+  #define PSWWR_REG_INT_STS_WR_PSDM_FIFO_OVERFLOW                                                            (0x1<<14) // Overflow in psdm write input fifo.
+  #define PSWWR_REG_INT_STS_WR_PSDM_FIFO_OVERFLOW_SHIFT                                                      14
+  #define PSWWR_REG_INT_STS_WR_M2P_FIFO_OVERFLOW                                                             (0x1<<15) // Overflow in M2P input fifo.
+  #define PSWWR_REG_INT_STS_WR_M2P_FIFO_OVERFLOW_SHIFT                                                       15
+  #define PSWWR_REG_INT_STS_WR_PRM_SEC_FIFO_OVERFLOW_E5                                                      (0x1<<16) // Overflow in PRM Secondary input fifo.
+  #define PSWWR_REG_INT_STS_WR_PRM_SEC_FIFO_OVERFLOW_E5_SHIFT                                                16
+  #define PSWWR_REG_INT_STS_WR_RGFS_FIFO_OVERFLOW_E5                                                         (0x1<<17) // Overflow in RGFS input fifo.
+  #define PSWWR_REG_INT_STS_WR_RGFS_FIFO_OVERFLOW_E5_SHIFT                                                   17
+  #define PSWWR_REG_INT_STS_WR_TGFS_FIFO_OVERFLOW_E5                                                         (0x1<<18) // Overflow in TGFS input fifo.
+  #define PSWWR_REG_INT_STS_WR_TGFS_FIFO_OVERFLOW_E5_SHIFT                                                   18
+#define PSWWR_REG_INT_STS_CLR                                                                                0x29a18cUL //Access:RC   DataWidth:0x13   // Multi Field Register.
+  #define PSWWR_REG_INT_STS_CLR_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSWWR_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                          0
+  #define PSWWR_REG_INT_STS_CLR_SRC_FIFO_OVERFLOW                                                            (0x1<<1) // Overflow in src input fifo.
+  #define PSWWR_REG_INT_STS_CLR_SRC_FIFO_OVERFLOW_SHIFT                                                      1
+  #define PSWWR_REG_INT_STS_CLR_QM_FIFO_OVERFLOW                                                             (0x1<<2) // Overflow in qm input fifo.
+  #define PSWWR_REG_INT_STS_CLR_QM_FIFO_OVERFLOW_SHIFT                                                       2
+  #define PSWWR_REG_INT_STS_CLR_TM_FIFO_OVERFLOW                                                             (0x1<<3) // Overflow in tm fifo.
+  #define PSWWR_REG_INT_STS_CLR_TM_FIFO_OVERFLOW_SHIFT                                                       3
+  #define PSWWR_REG_INT_STS_CLR_USDM_FIFO_OVERFLOW                                                           (0x1<<4) // Overflow in usdm input fifo.
+  #define PSWWR_REG_INT_STS_CLR_USDM_FIFO_OVERFLOW_SHIFT                                                     4
+  #define PSWWR_REG_INT_STS_CLR_USDMDP_FIFO_OVERFLOW                                                         (0x1<<5) // Overflow in usdmdp input fifo.
+  #define PSWWR_REG_INT_STS_CLR_USDMDP_FIFO_OVERFLOW_SHIFT                                                   5
+  #define PSWWR_REG_INT_STS_CLR_XSDM_FIFO_OVERFLOW                                                           (0x1<<6) // Overflow in xsdm input fifo.
+  #define PSWWR_REG_INT_STS_CLR_XSDM_FIFO_OVERFLOW_SHIFT                                                     6
+  #define PSWWR_REG_INT_STS_CLR_TSDM_FIFO_OVERFLOW                                                           (0x1<<7) // Overflow in tsdm input fifo.
+  #define PSWWR_REG_INT_STS_CLR_TSDM_FIFO_OVERFLOW_SHIFT                                                     7
+  #define PSWWR_REG_INT_STS_CLR_CDUWR_FIFO_OVERFLOW                                                          (0x1<<8) // Overflow in cduwr input fifo.
+  #define PSWWR_REG_INT_STS_CLR_CDUWR_FIFO_OVERFLOW_SHIFT                                                    8
+  #define PSWWR_REG_INT_STS_CLR_DBG_FIFO_OVERFLOW                                                            (0x1<<9) // Overflow in dbg input fifo.
+  #define PSWWR_REG_INT_STS_CLR_DBG_FIFO_OVERFLOW_SHIFT                                                      9
+  #define PSWWR_REG_INT_STS_CLR_DMAE_FIFO_OVERFLOW                                                           (0x1<<10) // Overflow in dmae input fifo.
+  #define PSWWR_REG_INT_STS_CLR_DMAE_FIFO_OVERFLOW_SHIFT                                                     10
+  #define PSWWR_REG_INT_STS_CLR_HC_FIFO_OVERFLOW                                                             (0x1<<11) // Overflow in hc input fifo.
+  #define PSWWR_REG_INT_STS_CLR_HC_FIFO_OVERFLOW_SHIFT                                                       11
+  #define PSWWR_REG_INT_STS_CLR_MSDM_FIFO_OVERFLOW                                                           (0x1<<12) // Overflow in msdm write input fifo.
+  #define PSWWR_REG_INT_STS_CLR_MSDM_FIFO_OVERFLOW_SHIFT                                                     12
+  #define PSWWR_REG_INT_STS_CLR_YSDM_FIFO_OVERFLOW                                                           (0x1<<13) // Overflow in ysdm write input fifo.
+  #define PSWWR_REG_INT_STS_CLR_YSDM_FIFO_OVERFLOW_SHIFT                                                     13
+  #define PSWWR_REG_INT_STS_CLR_PSDM_FIFO_OVERFLOW                                                           (0x1<<14) // Overflow in psdm write input fifo.
+  #define PSWWR_REG_INT_STS_CLR_PSDM_FIFO_OVERFLOW_SHIFT                                                     14
+  #define PSWWR_REG_INT_STS_CLR_M2P_FIFO_OVERFLOW                                                            (0x1<<15) // Overflow in M2P input fifo.
+  #define PSWWR_REG_INT_STS_CLR_M2P_FIFO_OVERFLOW_SHIFT                                                      15
+  #define PSWWR_REG_INT_STS_CLR_PRM_SEC_FIFO_OVERFLOW_E5                                                     (0x1<<16) // Overflow in PRM Secondary input fifo.
+  #define PSWWR_REG_INT_STS_CLR_PRM_SEC_FIFO_OVERFLOW_E5_SHIFT                                               16
+  #define PSWWR_REG_INT_STS_CLR_RGFS_FIFO_OVERFLOW_E5                                                        (0x1<<17) // Overflow in RGFS input fifo.
+  #define PSWWR_REG_INT_STS_CLR_RGFS_FIFO_OVERFLOW_E5_SHIFT                                                  17
+  #define PSWWR_REG_INT_STS_CLR_TGFS_FIFO_OVERFLOW_E5                                                        (0x1<<18) // Overflow in TGFS input fifo.
+  #define PSWWR_REG_INT_STS_CLR_TGFS_FIFO_OVERFLOW_E5_SHIFT                                                  18
+#define PSWWR_REG_PRTY_MASK                                                                                  0x29a194UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define PSWWR_REG_PRTY_MASK_DATAPATH_REGISTERS                                                             (0x1<<0) // This bit masks, when set, the Parity bit: PSWWR_REG_PRTY_STS.DATAPATH_REGISTERS .
+  #define PSWWR_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                                       0
+#define PSWWR2_REG_CDU_FULL_TH2                                                                              0x29b040UL //Access:RW   DataWidth:0x6    // If Number of entries in the cdu internal fifo is bigger than this number than full will be asserted.
+#define PSWWR2_REG_USDMDP_FULL_TH2                                                                           0x29b044UL //Access:RW   DataWidth:0x9    // If Number of entries in the usdmdp internal fifo is bigger than this number than full will be asserted.
+#define PSWWR2_REG_PGLUE_EOP_ERR_DETAILS                                                                     0x29b048UL //Access:R    DataWidth:0xf    // Details of first request that triggered any of the 3 EOP interrupts: [4:0] - client ID. [7:5] - (sum1[5:3] + 1) or (sum1[5:4] + 1) according to the definition in the spec. [10:8] - number_of_valid_64bit_words[2:0] or number_of_valid_128bit_words[1:0] according to the definition in the spec. [13:11] - The type of interrupt the logging corresponds to: [11] - pglue_eop_error; [12] - pglue_lsr_error; [13] - pglue_eop_error_in_line. [14] - valid - indicates if there was a request that triggered EOP interrupt since this register was cleared.
+#define PSWWR2_REG_PGLUE_EOP_ERR_DETAILS_CLR                                                                 0x29b04cUL //Access:W    DataWidth:0x1    // Writing to this register clears pglue_eop_err_details and enables logging new error details.
+#define PSWWR2_REG_PRM_CURR_FILL_LEVEL                                                                       0x29b050UL //Access:R    DataWidth:0x8    // Current internal PRM fill level in 64B lines.
+#define PSWWR2_REG_PRM_MAX_FILL_LEVEL                                                                        0x29b054UL //Access:R    DataWidth:0x8    // Maximum internal PRM fill level since reset in 64B lines.
+#define PSWWR2_REG_CDU_CURR_FILL_LEVEL                                                                       0x29b058UL //Access:R    DataWidth:0x6    // Current internal CDU fill level in 64B lines.
+#define PSWWR2_REG_CDU_MAX_FILL_LEVEL                                                                        0x29b05cUL //Access:R    DataWidth:0x6    // Maximum internal CDU fill level since reset in 64B lines.
+#define PSWWR2_REG_PRM_ERR_FIFO_FULL_TH                                                                      0x29b060UL //Access:RW   DataWidth:0x7    // If Number of entries in the PRM error fifo is bigger than this number than full will be asserted. PRM error FIFO contains 64 entries.
+#define PSWWR2_REG_ECO_RESERVED                                                                              0x29b064UL //Access:RW   DataWidth:0x6    // Debug only: Reserved bits for ECO.
+#define PSWWR2_REG_INT_STS                                                                                   0x29b180UL //Access:R    DataWidth:0x16   // Multi Field Register.
+  #define PSWWR2_REG_INT_STS_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSWWR2_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                             0
+  #define PSWWR2_REG_INT_STS_PGLUE_EOP_ERROR                                                                 (0x1<<1) // Indicates that there was not 'eop' in the last read request from the glue block.
+  #define PSWWR2_REG_INT_STS_PGLUE_EOP_ERROR_SHIFT                                                           1
+  #define PSWWR2_REG_INT_STS_PGLUE_LSR_ERROR                                                                 (0x1<<2) // Indicates that there was 'eop' not in the last read request from the glue block.
+  #define PSWWR2_REG_INT_STS_PGLUE_LSR_ERROR_SHIFT                                                           2
+  #define PSWWR2_REG_INT_STS_TM_UNDERFLOW                                                                    (0x1<<3) // Underflow in the tm fifo.
+  #define PSWWR2_REG_INT_STS_TM_UNDERFLOW_SHIFT                                                              3
+  #define PSWWR2_REG_INT_STS_QM_UNDERFLOW                                                                    (0x1<<4) // Underflow in the qm fifo.
+  #define PSWWR2_REG_INT_STS_QM_UNDERFLOW_SHIFT                                                              4
+  #define PSWWR2_REG_INT_STS_SRC_UNDERFLOW                                                                   (0x1<<5) // Underflow in the src fifo.
+  #define PSWWR2_REG_INT_STS_SRC_UNDERFLOW_SHIFT                                                             5
+  #define PSWWR2_REG_INT_STS_USDM_UNDERFLOW                                                                  (0x1<<6) // Underflow in the usdm fifo.
+  #define PSWWR2_REG_INT_STS_USDM_UNDERFLOW_SHIFT                                                            6
+  #define PSWWR2_REG_INT_STS_TSDM_UNDERFLOW                                                                  (0x1<<7) // Underflow in the tsdm fifo.
+  #define PSWWR2_REG_INT_STS_TSDM_UNDERFLOW_SHIFT                                                            7
+  #define PSWWR2_REG_INT_STS_XSDM_UNDERFLOW                                                                  (0x1<<8) // Underflow in the xsdm fifo.
+  #define PSWWR2_REG_INT_STS_XSDM_UNDERFLOW_SHIFT                                                            8
+  #define PSWWR2_REG_INT_STS_USDMDP_UNDERFLOW                                                                (0x1<<9) // Underflow in the usdmdp fifo.
+  #define PSWWR2_REG_INT_STS_USDMDP_UNDERFLOW_SHIFT                                                          9
+  #define PSWWR2_REG_INT_STS_CDU_UNDERFLOW                                                                   (0x1<<10) // Underflow in the cdu fifo.
+  #define PSWWR2_REG_INT_STS_CDU_UNDERFLOW_SHIFT                                                             10
+  #define PSWWR2_REG_INT_STS_DBG_UNDERFLOW                                                                   (0x1<<11) // Underflow in the dbg fifo.
+  #define PSWWR2_REG_INT_STS_DBG_UNDERFLOW_SHIFT                                                             11
+  #define PSWWR2_REG_INT_STS_DMAE_UNDERFLOW                                                                  (0x1<<12) // Underflow in the dmae fifo.
+  #define PSWWR2_REG_INT_STS_DMAE_UNDERFLOW_SHIFT                                                            12
+  #define PSWWR2_REG_INT_STS_HC_UNDERFLOW                                                                    (0x1<<13) // Underflow in the hc fifo.
+  #define PSWWR2_REG_INT_STS_HC_UNDERFLOW_SHIFT                                                              13
+  #define PSWWR2_REG_INT_STS_MSDM_UNDERFLOW                                                                  (0x1<<14) // Underflow in the msdm fifo.
+  #define PSWWR2_REG_INT_STS_MSDM_UNDERFLOW_SHIFT                                                            14
+  #define PSWWR2_REG_INT_STS_YSDM_UNDERFLOW                                                                  (0x1<<15) // Underflow in the ysdm fifo.
+  #define PSWWR2_REG_INT_STS_YSDM_UNDERFLOW_SHIFT                                                            15
+  #define PSWWR2_REG_INT_STS_PSDM_UNDERFLOW                                                                  (0x1<<16) // Underflow in the psdm fifo.
+  #define PSWWR2_REG_INT_STS_PSDM_UNDERFLOW_SHIFT                                                            16
+  #define PSWWR2_REG_INT_STS_M2P_UNDERFLOW                                                                   (0x1<<17) // Underflow in the M2P fifo.
+  #define PSWWR2_REG_INT_STS_M2P_UNDERFLOW_SHIFT                                                             17
+  #define PSWWR2_REG_INT_STS_PGLUE_EOP_ERROR_IN_LINE                                                         (0x1<<18) // Indicates that there was 'eop' in the last read request from the glue block; but the number of valid 128-bit or 64-bit words in the memory line did not match the PGLUE indication of the request length.
+  #define PSWWR2_REG_INT_STS_PGLUE_EOP_ERROR_IN_LINE_SHIFT                                                   18
+  #define PSWWR2_REG_INT_STS_PRM_SEC_UNDERFLOW_E5                                                            (0x1<<19) // Underflow in the PRM Secondary fifo.
+  #define PSWWR2_REG_INT_STS_PRM_SEC_UNDERFLOW_E5_SHIFT                                                      19
+  #define PSWWR2_REG_INT_STS_RGFS_UNDERFLOW_E5                                                               (0x1<<20) // Underflow in the RGFS fifo.
+  #define PSWWR2_REG_INT_STS_RGFS_UNDERFLOW_E5_SHIFT                                                         20
+  #define PSWWR2_REG_INT_STS_TGFS_UNDERFLOW_E5                                                               (0x1<<21) // Underflow in the TGFS fifo.
+  #define PSWWR2_REG_INT_STS_TGFS_UNDERFLOW_E5_SHIFT                                                         21
+#define PSWWR2_REG_INT_MASK                                                                                  0x29b184UL //Access:RW   DataWidth:0x16   // Multi Field Register.
+  #define PSWWR2_REG_INT_MASK_ADDRESS_ERROR                                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.ADDRESS_ERROR .
+  #define PSWWR2_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                            0
+  #define PSWWR2_REG_INT_MASK_PGLUE_EOP_ERROR                                                                (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.PGLUE_EOP_ERROR .
+  #define PSWWR2_REG_INT_MASK_PGLUE_EOP_ERROR_SHIFT                                                          1
+  #define PSWWR2_REG_INT_MASK_PGLUE_LSR_ERROR                                                                (0x1<<2) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.PGLUE_LSR_ERROR .
+  #define PSWWR2_REG_INT_MASK_PGLUE_LSR_ERROR_SHIFT                                                          2
+  #define PSWWR2_REG_INT_MASK_TM_UNDERFLOW                                                                   (0x1<<3) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.TM_UNDERFLOW .
+  #define PSWWR2_REG_INT_MASK_TM_UNDERFLOW_SHIFT                                                             3
+  #define PSWWR2_REG_INT_MASK_QM_UNDERFLOW                                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.QM_UNDERFLOW .
+  #define PSWWR2_REG_INT_MASK_QM_UNDERFLOW_SHIFT                                                             4
+  #define PSWWR2_REG_INT_MASK_SRC_UNDERFLOW                                                                  (0x1<<5) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.SRC_UNDERFLOW .
+  #define PSWWR2_REG_INT_MASK_SRC_UNDERFLOW_SHIFT                                                            5
+  #define PSWWR2_REG_INT_MASK_USDM_UNDERFLOW                                                                 (0x1<<6) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.USDM_UNDERFLOW .
+  #define PSWWR2_REG_INT_MASK_USDM_UNDERFLOW_SHIFT                                                           6
+  #define PSWWR2_REG_INT_MASK_TSDM_UNDERFLOW                                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.TSDM_UNDERFLOW .
+  #define PSWWR2_REG_INT_MASK_TSDM_UNDERFLOW_SHIFT                                                           7
+  #define PSWWR2_REG_INT_MASK_XSDM_UNDERFLOW                                                                 (0x1<<8) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.XSDM_UNDERFLOW .
+  #define PSWWR2_REG_INT_MASK_XSDM_UNDERFLOW_SHIFT                                                           8
+  #define PSWWR2_REG_INT_MASK_USDMDP_UNDERFLOW                                                               (0x1<<9) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.USDMDP_UNDERFLOW .
+  #define PSWWR2_REG_INT_MASK_USDMDP_UNDERFLOW_SHIFT                                                         9
+  #define PSWWR2_REG_INT_MASK_CDU_UNDERFLOW                                                                  (0x1<<10) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.CDU_UNDERFLOW .
+  #define PSWWR2_REG_INT_MASK_CDU_UNDERFLOW_SHIFT                                                            10
+  #define PSWWR2_REG_INT_MASK_DBG_UNDERFLOW                                                                  (0x1<<11) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.DBG_UNDERFLOW .
+  #define PSWWR2_REG_INT_MASK_DBG_UNDERFLOW_SHIFT                                                            11
+  #define PSWWR2_REG_INT_MASK_DMAE_UNDERFLOW                                                                 (0x1<<12) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.DMAE_UNDERFLOW .
+  #define PSWWR2_REG_INT_MASK_DMAE_UNDERFLOW_SHIFT                                                           12
+  #define PSWWR2_REG_INT_MASK_HC_UNDERFLOW                                                                   (0x1<<13) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.HC_UNDERFLOW .
+  #define PSWWR2_REG_INT_MASK_HC_UNDERFLOW_SHIFT                                                             13
+  #define PSWWR2_REG_INT_MASK_MSDM_UNDERFLOW                                                                 (0x1<<14) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.MSDM_UNDERFLOW .
+  #define PSWWR2_REG_INT_MASK_MSDM_UNDERFLOW_SHIFT                                                           14
+  #define PSWWR2_REG_INT_MASK_YSDM_UNDERFLOW                                                                 (0x1<<15) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.YSDM_UNDERFLOW .
+  #define PSWWR2_REG_INT_MASK_YSDM_UNDERFLOW_SHIFT                                                           15
+  #define PSWWR2_REG_INT_MASK_PSDM_UNDERFLOW                                                                 (0x1<<16) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.PSDM_UNDERFLOW .
+  #define PSWWR2_REG_INT_MASK_PSDM_UNDERFLOW_SHIFT                                                           16
+  #define PSWWR2_REG_INT_MASK_M2P_UNDERFLOW                                                                  (0x1<<17) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.M2P_UNDERFLOW .
+  #define PSWWR2_REG_INT_MASK_M2P_UNDERFLOW_SHIFT                                                            17
+  #define PSWWR2_REG_INT_MASK_PGLUE_EOP_ERROR_IN_LINE                                                        (0x1<<18) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.PGLUE_EOP_ERROR_IN_LINE .
+  #define PSWWR2_REG_INT_MASK_PGLUE_EOP_ERROR_IN_LINE_SHIFT                                                  18
+  #define PSWWR2_REG_INT_MASK_PRM_SEC_UNDERFLOW_E5                                                           (0x1<<19) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.PRM_SEC_UNDERFLOW .
+  #define PSWWR2_REG_INT_MASK_PRM_SEC_UNDERFLOW_E5_SHIFT                                                     19
+  #define PSWWR2_REG_INT_MASK_RGFS_UNDERFLOW_E5                                                              (0x1<<20) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.RGFS_UNDERFLOW .
+  #define PSWWR2_REG_INT_MASK_RGFS_UNDERFLOW_E5_SHIFT                                                        20
+  #define PSWWR2_REG_INT_MASK_TGFS_UNDERFLOW_E5                                                              (0x1<<21) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.TGFS_UNDERFLOW .
+  #define PSWWR2_REG_INT_MASK_TGFS_UNDERFLOW_E5_SHIFT                                                        21
+#define PSWWR2_REG_INT_STS_WR                                                                                0x29b188UL //Access:WR   DataWidth:0x16   // Multi Field Register.
+  #define PSWWR2_REG_INT_STS_WR_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSWWR2_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                          0
+  #define PSWWR2_REG_INT_STS_WR_PGLUE_EOP_ERROR                                                              (0x1<<1) // Indicates that there was not 'eop' in the last read request from the glue block.
+  #define PSWWR2_REG_INT_STS_WR_PGLUE_EOP_ERROR_SHIFT                                                        1
+  #define PSWWR2_REG_INT_STS_WR_PGLUE_LSR_ERROR                                                              (0x1<<2) // Indicates that there was 'eop' not in the last read request from the glue block.
+  #define PSWWR2_REG_INT_STS_WR_PGLUE_LSR_ERROR_SHIFT                                                        2
+  #define PSWWR2_REG_INT_STS_WR_TM_UNDERFLOW                                                                 (0x1<<3) // Underflow in the tm fifo.
+  #define PSWWR2_REG_INT_STS_WR_TM_UNDERFLOW_SHIFT                                                           3
+  #define PSWWR2_REG_INT_STS_WR_QM_UNDERFLOW                                                                 (0x1<<4) // Underflow in the qm fifo.
+  #define PSWWR2_REG_INT_STS_WR_QM_UNDERFLOW_SHIFT                                                           4
+  #define PSWWR2_REG_INT_STS_WR_SRC_UNDERFLOW                                                                (0x1<<5) // Underflow in the src fifo.
+  #define PSWWR2_REG_INT_STS_WR_SRC_UNDERFLOW_SHIFT                                                          5
+  #define PSWWR2_REG_INT_STS_WR_USDM_UNDERFLOW                                                               (0x1<<6) // Underflow in the usdm fifo.
+  #define PSWWR2_REG_INT_STS_WR_USDM_UNDERFLOW_SHIFT                                                         6
+  #define PSWWR2_REG_INT_STS_WR_TSDM_UNDERFLOW                                                               (0x1<<7) // Underflow in the tsdm fifo.
+  #define PSWWR2_REG_INT_STS_WR_TSDM_UNDERFLOW_SHIFT                                                         7
+  #define PSWWR2_REG_INT_STS_WR_XSDM_UNDERFLOW                                                               (0x1<<8) // Underflow in the xsdm fifo.
+  #define PSWWR2_REG_INT_STS_WR_XSDM_UNDERFLOW_SHIFT                                                         8
+  #define PSWWR2_REG_INT_STS_WR_USDMDP_UNDERFLOW                                                             (0x1<<9) // Underflow in the usdmdp fifo.
+  #define PSWWR2_REG_INT_STS_WR_USDMDP_UNDERFLOW_SHIFT                                                       9
+  #define PSWWR2_REG_INT_STS_WR_CDU_UNDERFLOW                                                                (0x1<<10) // Underflow in the cdu fifo.
+  #define PSWWR2_REG_INT_STS_WR_CDU_UNDERFLOW_SHIFT                                                          10
+  #define PSWWR2_REG_INT_STS_WR_DBG_UNDERFLOW                                                                (0x1<<11) // Underflow in the dbg fifo.
+  #define PSWWR2_REG_INT_STS_WR_DBG_UNDERFLOW_SHIFT                                                          11
+  #define PSWWR2_REG_INT_STS_WR_DMAE_UNDERFLOW                                                               (0x1<<12) // Underflow in the dmae fifo.
+  #define PSWWR2_REG_INT_STS_WR_DMAE_UNDERFLOW_SHIFT                                                         12
+  #define PSWWR2_REG_INT_STS_WR_HC_UNDERFLOW                                                                 (0x1<<13) // Underflow in the hc fifo.
+  #define PSWWR2_REG_INT_STS_WR_HC_UNDERFLOW_SHIFT                                                           13
+  #define PSWWR2_REG_INT_STS_WR_MSDM_UNDERFLOW                                                               (0x1<<14) // Underflow in the msdm fifo.
+  #define PSWWR2_REG_INT_STS_WR_MSDM_UNDERFLOW_SHIFT                                                         14
+  #define PSWWR2_REG_INT_STS_WR_YSDM_UNDERFLOW                                                               (0x1<<15) // Underflow in the ysdm fifo.
+  #define PSWWR2_REG_INT_STS_WR_YSDM_UNDERFLOW_SHIFT                                                         15
+  #define PSWWR2_REG_INT_STS_WR_PSDM_UNDERFLOW                                                               (0x1<<16) // Underflow in the psdm fifo.
+  #define PSWWR2_REG_INT_STS_WR_PSDM_UNDERFLOW_SHIFT                                                         16
+  #define PSWWR2_REG_INT_STS_WR_M2P_UNDERFLOW                                                                (0x1<<17) // Underflow in the M2P fifo.
+  #define PSWWR2_REG_INT_STS_WR_M2P_UNDERFLOW_SHIFT                                                          17
+  #define PSWWR2_REG_INT_STS_WR_PGLUE_EOP_ERROR_IN_LINE                                                      (0x1<<18) // Indicates that there was 'eop' in the last read request from the glue block; but the number of valid 128-bit or 64-bit words in the memory line did not match the PGLUE indication of the request length.
+  #define PSWWR2_REG_INT_STS_WR_PGLUE_EOP_ERROR_IN_LINE_SHIFT                                                18
+  #define PSWWR2_REG_INT_STS_WR_PRM_SEC_UNDERFLOW_E5                                                         (0x1<<19) // Underflow in the PRM Secondary fifo.
+  #define PSWWR2_REG_INT_STS_WR_PRM_SEC_UNDERFLOW_E5_SHIFT                                                   19
+  #define PSWWR2_REG_INT_STS_WR_RGFS_UNDERFLOW_E5                                                            (0x1<<20) // Underflow in the RGFS fifo.
+  #define PSWWR2_REG_INT_STS_WR_RGFS_UNDERFLOW_E5_SHIFT                                                      20
+  #define PSWWR2_REG_INT_STS_WR_TGFS_UNDERFLOW_E5                                                            (0x1<<21) // Underflow in the TGFS fifo.
+  #define PSWWR2_REG_INT_STS_WR_TGFS_UNDERFLOW_E5_SHIFT                                                      21
+#define PSWWR2_REG_INT_STS_CLR                                                                               0x29b18cUL //Access:RC   DataWidth:0x16   // Multi Field Register.
+  #define PSWWR2_REG_INT_STS_CLR_ADDRESS_ERROR                                                               (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSWWR2_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                         0
+  #define PSWWR2_REG_INT_STS_CLR_PGLUE_EOP_ERROR                                                             (0x1<<1) // Indicates that there was not 'eop' in the last read request from the glue block.
+  #define PSWWR2_REG_INT_STS_CLR_PGLUE_EOP_ERROR_SHIFT                                                       1
+  #define PSWWR2_REG_INT_STS_CLR_PGLUE_LSR_ERROR                                                             (0x1<<2) // Indicates that there was 'eop' not in the last read request from the glue block.
+  #define PSWWR2_REG_INT_STS_CLR_PGLUE_LSR_ERROR_SHIFT                                                       2
+  #define PSWWR2_REG_INT_STS_CLR_TM_UNDERFLOW                                                                (0x1<<3) // Underflow in the tm fifo.
+  #define PSWWR2_REG_INT_STS_CLR_TM_UNDERFLOW_SHIFT                                                          3
+  #define PSWWR2_REG_INT_STS_CLR_QM_UNDERFLOW                                                                (0x1<<4) // Underflow in the qm fifo.
+  #define PSWWR2_REG_INT_STS_CLR_QM_UNDERFLOW_SHIFT                                                          4
+  #define PSWWR2_REG_INT_STS_CLR_SRC_UNDERFLOW                                                               (0x1<<5) // Underflow in the src fifo.
+  #define PSWWR2_REG_INT_STS_CLR_SRC_UNDERFLOW_SHIFT                                                         5
+  #define PSWWR2_REG_INT_STS_CLR_USDM_UNDERFLOW                                                              (0x1<<6) // Underflow in the usdm fifo.
+  #define PSWWR2_REG_INT_STS_CLR_USDM_UNDERFLOW_SHIFT                                                        6
+  #define PSWWR2_REG_INT_STS_CLR_TSDM_UNDERFLOW                                                              (0x1<<7) // Underflow in the tsdm fifo.
+  #define PSWWR2_REG_INT_STS_CLR_TSDM_UNDERFLOW_SHIFT                                                        7
+  #define PSWWR2_REG_INT_STS_CLR_XSDM_UNDERFLOW                                                              (0x1<<8) // Underflow in the xsdm fifo.
+  #define PSWWR2_REG_INT_STS_CLR_XSDM_UNDERFLOW_SHIFT                                                        8
+  #define PSWWR2_REG_INT_STS_CLR_USDMDP_UNDERFLOW                                                            (0x1<<9) // Underflow in the usdmdp fifo.
+  #define PSWWR2_REG_INT_STS_CLR_USDMDP_UNDERFLOW_SHIFT                                                      9
+  #define PSWWR2_REG_INT_STS_CLR_CDU_UNDERFLOW                                                               (0x1<<10) // Underflow in the cdu fifo.
+  #define PSWWR2_REG_INT_STS_CLR_CDU_UNDERFLOW_SHIFT                                                         10
+  #define PSWWR2_REG_INT_STS_CLR_DBG_UNDERFLOW                                                               (0x1<<11) // Underflow in the dbg fifo.
+  #define PSWWR2_REG_INT_STS_CLR_DBG_UNDERFLOW_SHIFT                                                         11
+  #define PSWWR2_REG_INT_STS_CLR_DMAE_UNDERFLOW                                                              (0x1<<12) // Underflow in the dmae fifo.
+  #define PSWWR2_REG_INT_STS_CLR_DMAE_UNDERFLOW_SHIFT                                                        12
+  #define PSWWR2_REG_INT_STS_CLR_HC_UNDERFLOW                                                                (0x1<<13) // Underflow in the hc fifo.
+  #define PSWWR2_REG_INT_STS_CLR_HC_UNDERFLOW_SHIFT                                                          13
+  #define PSWWR2_REG_INT_STS_CLR_MSDM_UNDERFLOW                                                              (0x1<<14) // Underflow in the msdm fifo.
+  #define PSWWR2_REG_INT_STS_CLR_MSDM_UNDERFLOW_SHIFT                                                        14
+  #define PSWWR2_REG_INT_STS_CLR_YSDM_UNDERFLOW                                                              (0x1<<15) // Underflow in the ysdm fifo.
+  #define PSWWR2_REG_INT_STS_CLR_YSDM_UNDERFLOW_SHIFT                                                        15
+  #define PSWWR2_REG_INT_STS_CLR_PSDM_UNDERFLOW                                                              (0x1<<16) // Underflow in the psdm fifo.
+  #define PSWWR2_REG_INT_STS_CLR_PSDM_UNDERFLOW_SHIFT                                                        16
+  #define PSWWR2_REG_INT_STS_CLR_M2P_UNDERFLOW                                                               (0x1<<17) // Underflow in the M2P fifo.
+  #define PSWWR2_REG_INT_STS_CLR_M2P_UNDERFLOW_SHIFT                                                         17
+  #define PSWWR2_REG_INT_STS_CLR_PGLUE_EOP_ERROR_IN_LINE                                                     (0x1<<18) // Indicates that there was 'eop' in the last read request from the glue block; but the number of valid 128-bit or 64-bit words in the memory line did not match the PGLUE indication of the request length.
+  #define PSWWR2_REG_INT_STS_CLR_PGLUE_EOP_ERROR_IN_LINE_SHIFT                                               18
+  #define PSWWR2_REG_INT_STS_CLR_PRM_SEC_UNDERFLOW_E5                                                        (0x1<<19) // Underflow in the PRM Secondary fifo.
+  #define PSWWR2_REG_INT_STS_CLR_PRM_SEC_UNDERFLOW_E5_SHIFT                                                  19
+  #define PSWWR2_REG_INT_STS_CLR_RGFS_UNDERFLOW_E5                                                           (0x1<<20) // Underflow in the RGFS fifo.
+  #define PSWWR2_REG_INT_STS_CLR_RGFS_UNDERFLOW_E5_SHIFT                                                     20
+  #define PSWWR2_REG_INT_STS_CLR_TGFS_UNDERFLOW_E5                                                           (0x1<<21) // Underflow in the TGFS fifo.
+  #define PSWWR2_REG_INT_STS_CLR_TGFS_UNDERFLOW_E5_SHIFT                                                     21
+#define PSWWR2_REG_PRTY_MASK                                                                                 0x29b194UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define PSWWR2_REG_PRTY_MASK_DATAPATH_REGISTERS                                                            (0x1<<0) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS.DATAPATH_REGISTERS .
+  #define PSWWR2_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                                      0
+#define PSWWR2_REG_PRTY_MASK_H_0_BB_K2                                                                       0x29b204UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT_BB_K2                                                 (0x1<<0) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM008_I_ECC_RF_INT .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT_BB_K2_SHIFT                                           0
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                   (0x1<<1) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                             1
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_0_BB_K2                                                 (0x1<<2) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_0 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_0_BB_K2_SHIFT                                           2
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_1_BB_K2                                                 (0x1<<3) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_1 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_1_BB_K2_SHIFT                                           3
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_2_BB_K2                                                 (0x1<<4) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_2 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_2_BB_K2_SHIFT                                           4
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_3_BB_K2                                                 (0x1<<5) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_3 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_3_BB_K2_SHIFT                                           5
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_4_BB_K2                                                 (0x1<<6) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_4 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_4_BB_K2_SHIFT                                           6
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_5_BB_K2                                                 (0x1<<7) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_5 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_5_BB_K2_SHIFT                                           7
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_6_BB_K2                                                 (0x1<<8) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_6 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_6_BB_K2_SHIFT                                           8
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_7_BB_K2                                                 (0x1<<9) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_7 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_7_BB_K2_SHIFT                                           9
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_8_BB_K2                                                 (0x1<<10) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_8 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_8_BB_K2_SHIFT                                           10
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_0_BB_K2                                                 (0x1<<11) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_0 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_0_BB_K2_SHIFT                                           11
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_1_BB_K2                                                 (0x1<<12) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_1 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_1_BB_K2_SHIFT                                           12
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_2_BB_K2                                                 (0x1<<13) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_2 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_2_BB_K2_SHIFT                                           13
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_3_BB_K2                                                 (0x1<<14) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_3 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_3_BB_K2_SHIFT                                           14
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_4_BB_K2                                                 (0x1<<15) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_4 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_4_BB_K2_SHIFT                                           15
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_5_BB_K2                                                 (0x1<<16) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_5 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_5_BB_K2_SHIFT                                           16
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_6_BB_K2                                                 (0x1<<17) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_6 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_6_BB_K2_SHIFT                                           17
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_7_BB_K2                                                 (0x1<<18) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_7 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_7_BB_K2_SHIFT                                           18
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_8_BB_K2                                                 (0x1<<19) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_8 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_8_BB_K2_SHIFT                                           19
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_BB_K2                                                 (0x1<<20) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_0 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_BB_K2_SHIFT                                           20
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_BB_K2                                                 (0x1<<21) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_1 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_BB_K2_SHIFT                                           21
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_2_BB_K2                                                 (0x1<<22) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_2 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_2_BB_K2_SHIFT                                           22
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_3_BB_K2                                                 (0x1<<23) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_3 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_3_BB_K2_SHIFT                                           23
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_4_BB_K2                                                 (0x1<<24) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_4 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_4_BB_K2_SHIFT                                           24
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_5_BB_K2                                                 (0x1<<25) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_5 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_5_BB_K2_SHIFT                                           25
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_6_BB_K2                                                 (0x1<<26) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_6 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_6_BB_K2_SHIFT                                           26
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_7_BB_K2                                                 (0x1<<27) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_7 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_7_BB_K2_SHIFT                                           27
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_8_BB_K2                                                 (0x1<<28) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_8 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_8_BB_K2_SHIFT                                           28
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_0_BB_K2                                                 (0x1<<29) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY_0 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_0_BB_K2_SHIFT                                           29
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_1_BB_K2                                                 (0x1<<30) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY_1 .
+  #define PSWWR2_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_1_BB_K2_SHIFT                                           30
+#define PSWWR2_REG_PRTY_MASK_H_1_BB_K2                                                                       0x29b214UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_2_BB_K2                                                 (0x1<<0) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY_2 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_2_BB_K2_SHIFT                                           0
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_3_BB_K2                                                 (0x1<<1) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY_3 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_3_BB_K2_SHIFT                                           1
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_4_BB_K2                                                 (0x1<<2) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY_4 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_4_BB_K2_SHIFT                                           2
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_5_BB_K2                                                 (0x1<<3) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY_5 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_5_BB_K2_SHIFT                                           3
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_6_BB_K2                                                 (0x1<<4) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY_6 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_6_BB_K2_SHIFT                                           4
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_7_BB_K2                                                 (0x1<<5) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY_7 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_7_BB_K2_SHIFT                                           5
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_8_BB_K2                                                 (0x1<<6) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY_8 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_8_BB_K2_SHIFT                                           6
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_0_BB_K2                                                 (0x1<<7) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_0 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_0_BB_K2_SHIFT                                           7
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_1_BB_K2                                                 (0x1<<8) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_1 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_1_BB_K2_SHIFT                                           8
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_2_BB_K2                                                 (0x1<<9) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_2 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_2_BB_K2_SHIFT                                           9
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_3_BB_K2                                                 (0x1<<10) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_3 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_3_BB_K2_SHIFT                                           10
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_4_BB_K2                                                 (0x1<<11) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_4 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_4_BB_K2_SHIFT                                           11
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_5_BB_K2                                                 (0x1<<12) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_5 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_5_BB_K2_SHIFT                                           12
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_6_BB_K2                                                 (0x1<<13) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_6 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_6_BB_K2_SHIFT                                           13
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_7_BB_K2                                                 (0x1<<14) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_7 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_7_BB_K2_SHIFT                                           14
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_8_BB_K2                                                 (0x1<<15) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_8 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_8_BB_K2_SHIFT                                           15
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_0_BB_K2                                                 (0x1<<16) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_0 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_0_BB_K2_SHIFT                                           16
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_1_BB_K2                                                 (0x1<<17) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_1 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_1_BB_K2_SHIFT                                           17
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_2_BB_K2                                                 (0x1<<18) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_2 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_2_BB_K2_SHIFT                                           18
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_3_BB_K2                                                 (0x1<<19) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_3 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_3_BB_K2_SHIFT                                           19
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_4_BB_K2                                                 (0x1<<20) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_4 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_4_BB_K2_SHIFT                                           20
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_5_BB_K2                                                 (0x1<<21) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_5 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_5_BB_K2_SHIFT                                           21
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_6_BB_K2                                                 (0x1<<22) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_6 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_6_BB_K2_SHIFT                                           22
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_7_BB_K2                                                 (0x1<<23) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_7 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_7_BB_K2_SHIFT                                           23
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_8_BB_K2                                                 (0x1<<24) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_8 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_8_BB_K2_SHIFT                                           24
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_0_BB_K2                                                 (0x1<<25) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY_0 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_0_BB_K2_SHIFT                                           25
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_1_BB_K2                                                 (0x1<<26) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY_1 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_1_BB_K2_SHIFT                                           26
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_2_BB_K2                                                 (0x1<<27) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY_2 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_2_BB_K2_SHIFT                                           27
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_3_BB_K2                                                 (0x1<<28) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY_3 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_3_BB_K2_SHIFT                                           28
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_4_BB_K2                                                 (0x1<<29) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY_4 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_4_BB_K2_SHIFT                                           29
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_5_BB_K2                                                 (0x1<<30) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY_5 .
+  #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_5_BB_K2_SHIFT                                           30
+#define PSWWR2_REG_PRTY_MASK_H_2_BB_K2                                                                       0x29b224UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM006_I_MEM_PRTY_6_BB_K2                                                 (0x1<<0) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM006_I_MEM_PRTY_6 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM006_I_MEM_PRTY_6_BB_K2_SHIFT                                           0
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM006_I_MEM_PRTY_7_BB_K2                                                 (0x1<<1) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM006_I_MEM_PRTY_7 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM006_I_MEM_PRTY_7_BB_K2_SHIFT                                           1
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM006_I_MEM_PRTY_8_BB_K2                                                 (0x1<<2) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM006_I_MEM_PRTY_8 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM006_I_MEM_PRTY_8_BB_K2_SHIFT                                           2
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_0_BB_K2                                                 (0x1<<3) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_0 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_0_BB_K2_SHIFT                                           3
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_1_BB_K2                                                 (0x1<<4) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_1 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_1_BB_K2_SHIFT                                           4
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_2_BB_K2                                                 (0x1<<5) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_2 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_2_BB_K2_SHIFT                                           5
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_3_BB_K2                                                 (0x1<<6) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_3 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_3_BB_K2_SHIFT                                           6
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_4_BB_K2                                                 (0x1<<7) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_4 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_4_BB_K2_SHIFT                                           7
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_5_BB_K2                                                 (0x1<<8) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_5 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_5_BB_K2_SHIFT                                           8
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_6_BB_K2                                                 (0x1<<9) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_6 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_6_BB_K2_SHIFT                                           9
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_7_BB_K2                                                 (0x1<<10) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_7 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_7_BB_K2_SHIFT                                           10
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_8_BB_K2                                                 (0x1<<11) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_8 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_8_BB_K2_SHIFT                                           11
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM012_I_MEM_PRTY_BB_K2                                                   (0x1<<12) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM012_I_MEM_PRTY .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM012_I_MEM_PRTY_BB_K2_SHIFT                                             12
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_0_BB_K2                                                 (0x1<<13) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_0 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_0_BB_K2_SHIFT                                           13
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_1_BB_K2                                                 (0x1<<14) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_1 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_1_BB_K2_SHIFT                                           14
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_2_BB_K2                                                 (0x1<<15) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_2 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_2_BB_K2_SHIFT                                           15
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_3_BB_K2                                                 (0x1<<16) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_3 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_3_BB_K2_SHIFT                                           16
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_4_BB_K2                                                 (0x1<<17) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_4 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_4_BB_K2_SHIFT                                           17
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_5_BB_K2                                                 (0x1<<18) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_5 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_5_BB_K2_SHIFT                                           18
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_6_BB_K2                                                 (0x1<<19) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_6 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_6_BB_K2_SHIFT                                           19
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_7_BB_K2                                                 (0x1<<20) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_7 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_7_BB_K2_SHIFT                                           20
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_8_BB_K2                                                 (0x1<<21) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_8 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_8_BB_K2_SHIFT                                           21
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_0_BB_K2                                                 (0x1<<22) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_0 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_0_BB_K2_SHIFT                                           22
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_1_BB_K2                                                 (0x1<<23) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_1 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_1_BB_K2_SHIFT                                           23
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_2_BB_K2                                                 (0x1<<24) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_2 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_2_BB_K2_SHIFT                                           24
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_3_BB_K2                                                 (0x1<<25) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_3 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_3_BB_K2_SHIFT                                           25
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_4_BB_K2                                                 (0x1<<26) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_4 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_4_BB_K2_SHIFT                                           26
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_5_BB_K2                                                 (0x1<<27) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_5 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_5_BB_K2_SHIFT                                           27
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_6_BB_K2                                                 (0x1<<28) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_6 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_6_BB_K2_SHIFT                                           28
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_7_BB_K2                                                 (0x1<<29) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_7 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_7_BB_K2_SHIFT                                           29
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_8_BB_K2                                                 (0x1<<30) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_8 .
+  #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_8_BB_K2_SHIFT                                           30
+#define PSWWR2_REG_PRTY_MASK_H_3_BB_K2                                                                       0x29b234UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM015_I_MEM_PRTY_0_BB_K2                                                 (0x1<<0) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM015_I_MEM_PRTY_0 .
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM015_I_MEM_PRTY_0_BB_K2_SHIFT                                           0
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM015_I_MEM_PRTY_1_BB_K2                                                 (0x1<<1) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM015_I_MEM_PRTY_1 .
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM015_I_MEM_PRTY_1_BB_K2_SHIFT                                           1
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM015_I_MEM_PRTY_2_BB_K2                                                 (0x1<<2) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM015_I_MEM_PRTY_2 .
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM015_I_MEM_PRTY_2_BB_K2_SHIFT                                           2
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_0_BB_K2                                                 (0x1<<3) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_0 .
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_0_BB_K2_SHIFT                                           3
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_1_BB_K2                                                 (0x1<<4) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_1 .
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_1_BB_K2_SHIFT                                           4
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_2_BB_K2                                                 (0x1<<5) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_2 .
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_2_BB_K2_SHIFT                                           5
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_3_BB_K2                                                 (0x1<<6) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_3 .
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_3_BB_K2_SHIFT                                           6
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_4_BB_K2                                                 (0x1<<7) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_4 .
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_4_BB_K2_SHIFT                                           7
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_5_BB_K2                                                 (0x1<<8) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_5 .
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_5_BB_K2_SHIFT                                           8
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_6_BB_K2                                                 (0x1<<9) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_6 .
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_6_BB_K2_SHIFT                                           9
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_7_BB_K2                                                 (0x1<<10) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_7 .
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_7_BB_K2_SHIFT                                           10
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_8_BB_K2                                                 (0x1<<11) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_8 .
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_8_BB_K2_SHIFT                                           11
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_0_BB_K2                                                 (0x1<<12) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM002_I_MEM_PRTY_0 .
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_0_BB_K2_SHIFT                                           12
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_1_BB_K2                                                 (0x1<<13) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM002_I_MEM_PRTY_1 .
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_1_BB_K2_SHIFT                                           13
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_2_BB_K2                                                 (0x1<<14) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM002_I_MEM_PRTY_2 .
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_2_BB_K2_SHIFT                                           14
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_3_BB_K2                                                 (0x1<<15) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM002_I_MEM_PRTY_3 .
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_3_BB_K2_SHIFT                                           15
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_4_BB_K2                                                 (0x1<<16) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM002_I_MEM_PRTY_4 .
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_4_BB_K2_SHIFT                                           16
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM003_I_MEM_PRTY_0_BB_K2                                                 (0x1<<17) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM003_I_MEM_PRTY_0 .
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM003_I_MEM_PRTY_0_BB_K2_SHIFT                                           17
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM003_I_MEM_PRTY_1_BB_K2                                                 (0x1<<18) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM003_I_MEM_PRTY_1 .
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM003_I_MEM_PRTY_1_BB_K2_SHIFT                                           18
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM003_I_MEM_PRTY_2_BB_K2                                                 (0x1<<19) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM003_I_MEM_PRTY_2 .
+  #define PSWWR2_REG_PRTY_MASK_H_3_MEM003_I_MEM_PRTY_2_BB_K2_SHIFT                                           19
+#define PSWWR2_REG_MEM008_RF_ECC_ERROR_CONNECT_BB_K2                                                         0x29b240UL //Access:W    DataWidth:0x16   // Register to generate up to two ECC errors on the next write to memory: pswwr.i_prm_fifo.rf_ecc_error_connect Includes 2 words of 11 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 514. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define PSWWR2_REG_MEM_ECC_ENABLE_0_BB_K2                                                                    0x29b244UL //Access:RW   DataWidth:0x1    // Enable ECC for memory ecc instance pswwr.i_prm_fifo.i_ecc in module pswwr_mem_prm_ififo
+#define PSWWR2_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                               0x29b248UL //Access:RW   DataWidth:0x1    // Set parity only for memory ecc instance pswwr.i_prm_fifo.i_ecc in module pswwr_mem_prm_ififo
+#define PSWWR2_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                           0x29b24cUL //Access:RC   DataWidth:0x1    // Record if a correctable error occurred on memory ecc instance pswwr.i_prm_fifo.i_ecc in module pswwr_mem_prm_ififo
+#define PSWWR2_REG_MEM_ECC_EVENTS_BB_K2                                                                      0x29b250UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define PSWRD_REG_DBG_SELECT                                                                                 0x29c040UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PSWRD_REG_DBG_DWORD_ENABLE                                                                           0x29c044UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PSWRD_REG_DBG_SHIFT                                                                                  0x29c048UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PSWRD_REG_DBG_FORCE_VALID                                                                            0x29c04cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PSWRD_REG_DBG_FORCE_FRAME                                                                            0x29c050UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PSWRD_REG_DBG_OUT_DATA                                                                               0x29c060UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PSWRD_REG_DBG_OUT_DATA_SIZE                                                                          8
+#define PSWRD_REG_DBG_OUT_VALID                                                                              0x29c080UL //Access:R    DataWidth:0x4    // Dbgmux output valid
+#define PSWRD_REG_DBG_OUT_FRAME                                                                              0x29c084UL //Access:R    DataWidth:0x4    // Dbgmux output frame
+#define PSWRD_REG_ECO_RESERVED                                                                               0x29c0a0UL //Access:RW   DataWidth:0xa    // Debug only: Reserved bits for ECO.
+#define PSWRD_REG_FIFO_FULL_STATUS                                                                           0x29c0a4UL //Access:R    DataWidth:0x10   // Each bit indicates if full is asserted by the client. The clients order is according to the incrementing client IDs of read clients.
+#define PSWRD_REG_FIFO_FULL_STICKY                                                                           0x29c0a8UL //Access:R    DataWidth:0x10   // Each bit indicates if full was asserted since reset by the client. The clients order is according to the incrementing client IDs of read clients:.
+#define PSWRD_REG_INT_STS                                                                                    0x29c180UL //Access:R    DataWidth:0x3    // Multi Field Register.
+  #define PSWRD_REG_INT_STS_ADDRESS_ERROR                                                                    (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSWRD_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                              0
+  #define PSWRD_REG_INT_STS_POP_ERROR                                                                        (0x1<<1) // An error in one of the clients' (except PBF) FIFOs pop interface.
+  #define PSWRD_REG_INT_STS_POP_ERROR_SHIFT                                                                  1
+  #define PSWRD_REG_INT_STS_POP_PBF_ERROR                                                                    (0x1<<2) // An error in the PBF FIFO pop interface.
+  #define PSWRD_REG_INT_STS_POP_PBF_ERROR_SHIFT                                                              2
+#define PSWRD_REG_INT_MASK                                                                                   0x29c184UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define PSWRD_REG_INT_MASK_ADDRESS_ERROR                                                                   (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWRD_REG_INT_STS.ADDRESS_ERROR .
+  #define PSWRD_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                             0
+  #define PSWRD_REG_INT_MASK_POP_ERROR                                                                       (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWRD_REG_INT_STS.POP_ERROR .
+  #define PSWRD_REG_INT_MASK_POP_ERROR_SHIFT                                                                 1
+  #define PSWRD_REG_INT_MASK_POP_PBF_ERROR                                                                   (0x1<<2) // This bit masks, when set, the Interrupt bit: PSWRD_REG_INT_STS.POP_PBF_ERROR .
+  #define PSWRD_REG_INT_MASK_POP_PBF_ERROR_SHIFT                                                             2
+#define PSWRD_REG_INT_STS_WR                                                                                 0x29c188UL //Access:WR   DataWidth:0x3    // Multi Field Register.
+  #define PSWRD_REG_INT_STS_WR_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSWRD_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                           0
+  #define PSWRD_REG_INT_STS_WR_POP_ERROR                                                                     (0x1<<1) // An error in one of the clients' (except PBF) FIFOs pop interface.
+  #define PSWRD_REG_INT_STS_WR_POP_ERROR_SHIFT                                                               1
+  #define PSWRD_REG_INT_STS_WR_POP_PBF_ERROR                                                                 (0x1<<2) // An error in the PBF FIFO pop interface.
+  #define PSWRD_REG_INT_STS_WR_POP_PBF_ERROR_SHIFT                                                           2
+#define PSWRD_REG_INT_STS_CLR                                                                                0x29c18cUL //Access:RC   DataWidth:0x3    // Multi Field Register.
+  #define PSWRD_REG_INT_STS_CLR_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSWRD_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                          0
+  #define PSWRD_REG_INT_STS_CLR_POP_ERROR                                                                    (0x1<<1) // An error in one of the clients' (except PBF) FIFOs pop interface.
+  #define PSWRD_REG_INT_STS_CLR_POP_ERROR_SHIFT                                                              1
+  #define PSWRD_REG_INT_STS_CLR_POP_PBF_ERROR                                                                (0x1<<2) // An error in the PBF FIFO pop interface.
+  #define PSWRD_REG_INT_STS_CLR_POP_PBF_ERROR_SHIFT                                                          2
+#define PSWRD_REG_PRTY_MASK                                                                                  0x29c194UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define PSWRD_REG_PRTY_MASK_DATAPATH_REGISTERS                                                             (0x1<<0) // This bit masks, when set, the Parity bit: PSWRD_REG_PRTY_STS.DATAPATH_REGISTERS .
+  #define PSWRD_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                                       0
+#define PSWRD2_REG_START_INIT                                                                                0x29d000UL //Access:RW   DataWidth:0x1    // Driver should write 1 to this register in order to signal the PSWRD block to start initializing internal memories.
+#define PSWRD2_REG_INIT_DONE                                                                                 0x29d004UL //Access:R    DataWidth:0x1    // PSWRD internal memories initialization is done. Driver should check this register is 1 some time after writing 1 to start_init register.
+#define PSWRD2_REG_FIRST_SR_NODES                                                                            0x29d040UL //Access:R    DataWidth:0x1c   // Debug only and read only: Each entry provides the first sub request ID in 4 VQs. SR ID of 0x7f is NULL and means there is no sub request in this VQ in PSWRD. The reset value is the one expected in idle check except for the Timers VQ (VQ3).
+#define PSWRD2_REG_FIRST_SR_NODES_SIZE                                                                       8
+#define PSWRD2_REG_MASK_ERROR_TO_CLIENTS                                                                     0x29d060UL //Access:RW   DataWidth:0x10   // Debug only: '1' indicates that error indication is masked towards the corresponding client.
+#define PSWRD2_REG_CONF11                                                                                    0x29d064UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWRD2_REG_CONF11_ERROR_PATTERN                                                                    (0xffff<<0) // Data pattern that should override the data in case of an error. Duplicated 4 times to create 64 bit data. Can be deaddeaddeaddead for example.
+  #define PSWRD2_REG_CONF11_ERROR_PATTERN_SHIFT                                                              0
+  #define PSWRD2_REG_CONF11_OVERRIDE_DATA_WHEN_ERROR                                                         (0x1<<16) // 1 indicates to override the data to the client in case of an error and use the error pattern. 0 indicates not to override the data. Arrowhead: The reset value of 1 should not be changed. It can cause Xs on the outputs - CQ79817.
+  #define PSWRD2_REG_CONF11_OVERRIDE_DATA_WHEN_ERROR_SHIFT                                                   16
+  #define PSWRD2_REG_CONF11_OVERRIDE_LAST_CYCLE_ONLY                                                         (0x1<<17) // Meaningful only when override_data_when_error is 1. 1 indicates to override the data to the client in case of an error only in the last request cycle. 0 indicates to override the data from the time the error indication arrives to delivery sub-block until end of packet. Note that the override may start a few cycles before or after the last data cycle that arrived from PGLUE. Arrowhead: The reset value of 0 should not be changed. It can cause Xs on the outputs - CQ79817.
+  #define PSWRD2_REG_CONF11_OVERRIDE_LAST_CYCLE_ONLY_SHIFT                                                   17
+#define PSWRD2_REG_CPL_ERR_DETAILS                                                                           0x29d068UL //Access:R    DataWidth:0x1f   // Details of first request with error on receive side: [15:0] - Echo ID. [28:16] - sub-request length minus 1. [29] - first SR. [30] - last SR.
+#define PSWRD2_REG_CPL_ERR_DETAILS2                                                                          0x29d06cUL //Access:R    DataWidth:0xb    // Details of first request with error on receive side: [4:0] - VQ ID. [9:5] - client ID. [10] - valid - indicates if there was a completion error since the last time this register was read.
+#define PSWRD2_REG_CPL_ERR_DETAILS_CLR                                                                       0x29d070UL //Access:W    DataWidth:0x1    // Writing to this register clears cpl_err_details and cpl_err_details2 and enables logging new error details.
+#define PSWRD2_REG_ARB_DELAY                                                                                 0x29d074UL //Access:RW   DataWidth:0x4    // Debug only: The arbiter delay. The delivery port waits ARB_DELAY cycles before asserting 'port_is_idle'. This value is based on implementation and should not be changed.
+#define PSWRD2_REG_PBF_IN_SEPARATE_VQ                                                                        0x29d078UL //Access:RW   DataWidth:0x1    // 1' indicates that the PBF has a separate VQ and uses VQ4. '0' indicates it shares VQ9 with SDM clients. This field should be consistent with PBF_REGISTERS_PCI_VOQ_ID.PCI_VOQ_ID .
+#define PSWRD2_REG_PORT_IS_IDLE_0                                                                            0x29d07cUL //Access:R    DataWidth:0x1    // Debug only: Indication if delivery ports are idle.
+#define PSWRD2_REG_PORT_IS_IDLE_1                                                                            0x29d080UL //Access:R    DataWidth:0x1    // Debug only: Indication if delivery ports are idle.
+#define PSWRD2_REG_ECO_RESERVED                                                                              0x29d084UL //Access:RW   DataWidth:0x14   // Debug only: Reserved bits for ECO.
+#define PSWRD2_REG_PBF_SWAP_MODE                                                                             0x29d0c0UL //Access:RW   DataWidth:0x2    // PBF byte swapping mode configuration for master read requests.
+#define PSWRD2_REG_QM_SWAP_MODE                                                                              0x29d0c4UL //Access:RW   DataWidth:0x2    // QM byte swapping mode configuration for master read requests.
+#define PSWRD2_REG_TM_SWAP_MODE                                                                              0x29d0c8UL //Access:RW   DataWidth:0x2    // TM byte swapping mode configuration for master read requests.
+#define PSWRD2_REG_SRC_SWAP_MODE                                                                             0x29d0ccUL //Access:RW   DataWidth:0x2    // SRC byte swapping mode configuration for master read requests.
+#define PSWRD2_REG_CDURD_SWAP_MODE                                                                           0x29d0d0UL //Access:RW   DataWidth:0x2    // CDU byte swapping mode configuration for master read requests.
+#define PSWRD2_REG_PTU_SWAP_MODE                                                                             0x29d0d4UL //Access:RW   DataWidth:0x2    // PTU byte swapping mode configuration for master read requests.
+#define PSWRD2_REG_ALMOST_FULL_0                                                                             0x29d0e0UL //Access:R    DataWidth:0x1    // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
+#define PSWRD2_REG_ALMOST_FULL_1                                                                             0x29d0e4UL //Access:R    DataWidth:0x1    // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
+#define PSWRD2_REG_ALMOST_FULL_2                                                                             0x29d0e8UL //Access:R    DataWidth:0x1    // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
+#define PSWRD2_REG_ALMOST_FULL_3                                                                             0x29d0ecUL //Access:R    DataWidth:0x1    // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
+#define PSWRD2_REG_ALMOST_FULL_4                                                                             0x29d0f0UL //Access:R    DataWidth:0x1    // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
+#define PSWRD2_REG_ALMOST_FULL_5                                                                             0x29d0f4UL //Access:R    DataWidth:0x1    // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
+#define PSWRD2_REG_ALMOST_FULL_6                                                                             0x29d0f8UL //Access:R    DataWidth:0x1    // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
+#define PSWRD2_REG_ALMOST_FULL_7                                                                             0x29d0fcUL //Access:R    DataWidth:0x1    // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
+#define PSWRD2_REG_ALMOST_FULL_8                                                                             0x29d100UL //Access:R    DataWidth:0x1    // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
+#define PSWRD2_REG_ALMOST_FULL_9                                                                             0x29d104UL //Access:R    DataWidth:0x1    // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
+#define PSWRD2_REG_ALMOST_FULL_10                                                                            0x29d108UL //Access:R    DataWidth:0x1    // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
+#define PSWRD2_REG_ALMOST_FULL_11                                                                            0x29d10cUL //Access:R    DataWidth:0x1    // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
+#define PSWRD2_REG_ALMOST_FULL_12                                                                            0x29d110UL //Access:R    DataWidth:0x1    // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
+#define PSWRD2_REG_ALMOST_FULL_13                                                                            0x29d114UL //Access:R    DataWidth:0x1    // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
+#define PSWRD2_REG_ALMOST_FULL_14                                                                            0x29d118UL //Access:R    DataWidth:0x1    // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
+#define PSWRD2_REG_ALMOST_FULL_15                                                                            0x29d11cUL //Access:R    DataWidth:0x1    // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
+#define PSWRD2_REG_ALMOST_FULL_THR_HIGH                                                                      0x29d120UL //Access:RW   DataWidth:0x5    // Debug only: If more than this Number of entries are used in the clock synchronization FIFO; it asserts the 'almost full' bit. This number is common to all clock synchronization FIFOs except PBF, CDU and PRM. This value is based on implementation and should not be changed.
+#define PSWRD2_REG_ALMOST_FULL_THR_LOW                                                                       0x29d124UL //Access:RW   DataWidth:0x5    // Debug only: If less or equal than this Number of entries are used in the clock synchronization FIFO; it de-asserts the 'almost full' bit. This is the almost full low configuration for all clients except PBF, CDU and PRM. It should be equal or smaller to the almost full high consiguration.
+#define PSWRD2_REG_ALMOST_FULL_THR_HIGH_CDU                                                                  0x29d128UL //Access:RW   DataWidth:0x5    // Debug only: If more than this Number of entries are used in the CDU clock synchronization FIFO; it asserts the 'almost full' bit. This is the almost full high configuration for CDU.
+#define PSWRD2_REG_ALMOST_FULL_THR_LOW_CDU                                                                   0x29d12cUL //Access:RW   DataWidth:0x5    // Debug only: If less or equal than this Number of entries are used in the CDU clock synchronization FIFO; it de-asserts the 'almost full' bit. This is the almost full low configuration for CDU. It should be equal or smaller to the almost full high consiguration.
+#define PSWRD2_REG_ALMOST_FULL_THR_HIGH_PBF                                                                  0x29d130UL //Access:RW   DataWidth:0x7    // Debug only: If more than this Number of entries are used in the PBF clock synchronization FIFO; it asserts the 'almost full' bit. This is the almost full high configuration for PBF.
+#define PSWRD2_REG_ALMOST_FULL_THR_LOW_PBF                                                                   0x29d134UL //Access:RW   DataWidth:0x7    // Debug only: If less or equal than this Number of entries are used in the PBF clock synchronization FIFO; it de-asserts the 'almost full' bit. This is the almost full low configuration for PBF It should be equal or smaller to the almost full high consiguration.
+#define PSWRD2_REG_ALMOST_FULL_THR_HIGH_PRM                                                                  0x29d138UL //Access:RW   DataWidth:0x3    // Debug only: If more than this Number of entries are used in the PRM clock synchronization FIFO; it asserts the 'almost full' bit. This is the almost full high configuration for PRM.
+#define PSWRD2_REG_ALMOST_FULL_THR_LOW_PRM                                                                   0x29d13cUL //Access:RW   DataWidth:0x3    // Debug only: If less or equal than this Number of entries are used in the clock synchronization FIFO; it de-asserts the 'almost full' bit. This is the almost full low configuration for PRM. It should be equal or smaller to the almost full high consiguration.
+#define PSWRD2_REG_FIFO_ALMOST_FULL_STICKY                                                                   0x29d140UL //Access:R    DataWidth:0x10   // Each bit indicates if 'almost full' was asserted since reset from the FIFO towards the delivery module. The clients order is according to the incrementing client IDs of read clients: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 PBF (TDIF); 7 QM; 8 TM; 9 SRC; 10 CDURD; 11 DMAE; 12 MULD (Rfetcher); 13 XYLD; 14 PTU; 15 PRM.
+#define PSWRD2_REG_MAX_FILL_LEVEL1                                                                           0x29d144UL //Access:R    DataWidth:0x20   // Per-client maximum sync FIFO fill level since reset in 16B lines. 7:0 TSDM; 15:8 MSDM; 23:16 USDM; 31:24 XSDM.
+#define PSWRD2_REG_MAX_FILL_LEVEL2                                                                           0x29d148UL //Access:R    DataWidth:0x20   // Per-client maximum sync FIFO fill level since reset in 16B lines. 7:0 YSDM; 15:8 PSDM; 23:16 QM; 31:24 TM.
+#define PSWRD2_REG_MAX_FILL_LEVEL3                                                                           0x29d14cUL //Access:R    DataWidth:0x20   // Per-client maximum sync FIFO fill level since reset in 16B lines. 7:0 SRC; 15:8 CDU; 23:16 DMAE; 31:24 MULD.
+#define PSWRD2_REG_MAX_FILL_LEVEL4                                                                           0x29d150UL //Access:R    DataWidth:0x18   // Per-client maximum sync FIFO fill level since reset in 16B lines. 7:0 XYLD. 15:8 PTU. 23:16 PRM.
+#define PSWRD2_REG_MAX_FILL_LEVEL_PBF                                                                        0x29d154UL //Access:R    DataWidth:0x8    // PBF maximum sync FIFO fill level since reset in 16B lines.
+#define PSWRD2_REG_INT_STS                                                                                   0x29d180UL //Access:R    DataWidth:0x5    // Multi Field Register.
+  #define PSWRD2_REG_INT_STS_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSWRD2_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                             0
+  #define PSWRD2_REG_INT_STS_SR_FIFO_ERROR                                                                   (0x1<<1) // An error in the SR free list FIFO.
+  #define PSWRD2_REG_INT_STS_SR_FIFO_ERROR_SHIFT                                                             1
+  #define PSWRD2_REG_INT_STS_BLK_FIFO_ERROR                                                                  (0x1<<2) // An error in the blocks free list FIFO.
+  #define PSWRD2_REG_INT_STS_BLK_FIFO_ERROR_SHIFT                                                            2
+  #define PSWRD2_REG_INT_STS_PUSH_ERROR                                                                      (0x1<<3) // An error in one of the clients' (except PBF) FIFOs push interface.
+  #define PSWRD2_REG_INT_STS_PUSH_ERROR_SHIFT                                                                3
+  #define PSWRD2_REG_INT_STS_PUSH_PBF_ERROR                                                                  (0x1<<4) // An error in the PBF FIFO push interface.
+  #define PSWRD2_REG_INT_STS_PUSH_PBF_ERROR_SHIFT                                                            4
+#define PSWRD2_REG_INT_MASK                                                                                  0x29d184UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define PSWRD2_REG_INT_MASK_ADDRESS_ERROR                                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWRD2_REG_INT_STS.ADDRESS_ERROR .
+  #define PSWRD2_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                            0
+  #define PSWRD2_REG_INT_MASK_SR_FIFO_ERROR                                                                  (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWRD2_REG_INT_STS.SR_FIFO_ERROR .
+  #define PSWRD2_REG_INT_MASK_SR_FIFO_ERROR_SHIFT                                                            1
+  #define PSWRD2_REG_INT_MASK_BLK_FIFO_ERROR                                                                 (0x1<<2) // This bit masks, when set, the Interrupt bit: PSWRD2_REG_INT_STS.BLK_FIFO_ERROR .
+  #define PSWRD2_REG_INT_MASK_BLK_FIFO_ERROR_SHIFT                                                           2
+  #define PSWRD2_REG_INT_MASK_PUSH_ERROR                                                                     (0x1<<3) // This bit masks, when set, the Interrupt bit: PSWRD2_REG_INT_STS.PUSH_ERROR .
+  #define PSWRD2_REG_INT_MASK_PUSH_ERROR_SHIFT                                                               3
+  #define PSWRD2_REG_INT_MASK_PUSH_PBF_ERROR                                                                 (0x1<<4) // This bit masks, when set, the Interrupt bit: PSWRD2_REG_INT_STS.PUSH_PBF_ERROR .
+  #define PSWRD2_REG_INT_MASK_PUSH_PBF_ERROR_SHIFT                                                           4
+#define PSWRD2_REG_INT_STS_WR                                                                                0x29d188UL //Access:WR   DataWidth:0x5    // Multi Field Register.
+  #define PSWRD2_REG_INT_STS_WR_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSWRD2_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                          0
+  #define PSWRD2_REG_INT_STS_WR_SR_FIFO_ERROR                                                                (0x1<<1) // An error in the SR free list FIFO.
+  #define PSWRD2_REG_INT_STS_WR_SR_FIFO_ERROR_SHIFT                                                          1
+  #define PSWRD2_REG_INT_STS_WR_BLK_FIFO_ERROR                                                               (0x1<<2) // An error in the blocks free list FIFO.
+  #define PSWRD2_REG_INT_STS_WR_BLK_FIFO_ERROR_SHIFT                                                         2
+  #define PSWRD2_REG_INT_STS_WR_PUSH_ERROR                                                                   (0x1<<3) // An error in one of the clients' (except PBF) FIFOs push interface.
+  #define PSWRD2_REG_INT_STS_WR_PUSH_ERROR_SHIFT                                                             3
+  #define PSWRD2_REG_INT_STS_WR_PUSH_PBF_ERROR                                                               (0x1<<4) // An error in the PBF FIFO push interface.
+  #define PSWRD2_REG_INT_STS_WR_PUSH_PBF_ERROR_SHIFT                                                         4
+#define PSWRD2_REG_INT_STS_CLR                                                                               0x29d18cUL //Access:RC   DataWidth:0x5    // Multi Field Register.
+  #define PSWRD2_REG_INT_STS_CLR_ADDRESS_ERROR                                                               (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSWRD2_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                         0
+  #define PSWRD2_REG_INT_STS_CLR_SR_FIFO_ERROR                                                               (0x1<<1) // An error in the SR free list FIFO.
+  #define PSWRD2_REG_INT_STS_CLR_SR_FIFO_ERROR_SHIFT                                                         1
+  #define PSWRD2_REG_INT_STS_CLR_BLK_FIFO_ERROR                                                              (0x1<<2) // An error in the blocks free list FIFO.
+  #define PSWRD2_REG_INT_STS_CLR_BLK_FIFO_ERROR_SHIFT                                                        2
+  #define PSWRD2_REG_INT_STS_CLR_PUSH_ERROR                                                                  (0x1<<3) // An error in one of the clients' (except PBF) FIFOs push interface.
+  #define PSWRD2_REG_INT_STS_CLR_PUSH_ERROR_SHIFT                                                            3
+  #define PSWRD2_REG_INT_STS_CLR_PUSH_PBF_ERROR                                                              (0x1<<4) // An error in the PBF FIFO push interface.
+  #define PSWRD2_REG_INT_STS_CLR_PUSH_PBF_ERROR_SHIFT                                                        4
+#define PSWRD2_REG_PRTY_MASK                                                                                 0x29d194UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define PSWRD2_REG_PRTY_MASK_DATAPATH_REGISTERS                                                            (0x1<<0) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS.DATAPATH_REGISTERS .
+  #define PSWRD2_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                                      0
+#define PSWRD2_REG_PRTY_MASK_H_0                                                                             0x29d204UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM017_I_ECC_RF_INT                                                       (0x1<<0) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM017_I_ECC_RF_INT .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM017_I_ECC_RF_INT_SHIFT                                                 0
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM018_I_ECC_RF_INT                                                       (0x1<<1) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM018_I_ECC_RF_INT .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM018_I_ECC_RF_INT_SHIFT                                                 1
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM019_I_ECC_RF_INT                                                       (0x1<<2) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM019_I_ECC_RF_INT .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM019_I_ECC_RF_INT_SHIFT                                                 2
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM020_I_ECC_RF_INT                                                       (0x1<<3) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM020_I_ECC_RF_INT .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM020_I_ECC_RF_INT_SHIFT                                                 3
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT                                                       (0x1<<4) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM021_I_ECC_RF_INT .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT_SHIFT                                                 4
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT                                                       (0x1<<5) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM022_I_ECC_RF_INT .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT_SHIFT                                                 5
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM023_I_ECC_RF_INT                                                       (0x1<<6) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM023_I_ECC_RF_INT .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM023_I_ECC_RF_INT_SHIFT                                                 6
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM024_I_ECC_RF_INT                                                       (0x1<<7) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM024_I_ECC_RF_INT .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM024_I_ECC_RF_INT_SHIFT                                                 7
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM025_I_ECC_RF_INT                                                       (0x1<<8) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM025_I_ECC_RF_INT .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM025_I_ECC_RF_INT_SHIFT                                                 8
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT                                                       (0x1<<9) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM015_I_ECC_RF_INT .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_SHIFT                                                 9
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY                                                         (0x1<<10) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_SHIFT                                                   10
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY                                                         (0x1<<11) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_SHIFT                                                   11
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY                                                         (0x1<<12) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_SHIFT                                                   12
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY                                                         (0x1<<13) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_SHIFT                                                   13
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY                                                         (0x1<<14) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_SHIFT                                                   14
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY                                                         (0x1<<15) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_SHIFT                                                   15
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY                                                         (0x1<<16) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_SHIFT                                                   16
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY                                                         (0x1<<17) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_SHIFT                                                   17
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY                                                         (0x1<<18) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_SHIFT                                                   18
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                         (0x1<<19) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                                   19
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY                                                         (0x1<<20) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_SHIFT                                                   20
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY                                                         (0x1<<21) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_SHIFT                                                   21
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY                                                         (0x1<<22) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT                                                   22
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY                                                         (0x1<<23) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_SHIFT                                                   23
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY                                                         (0x1<<24) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_SHIFT                                                   24
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY                                                         (0x1<<25) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_SHIFT                                                   25
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY                                                         (0x1<<26) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_SHIFT                                                   26
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY                                                         (0x1<<27) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_SHIFT                                                   27
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                         (0x1<<28) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                                   28
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                         (0x1<<29) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                                   29
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                         (0x1<<30) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define PSWRD2_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                                   30
+#define PSWRD2_REG_PRTY_MASK_H_1                                                                             0x29d214UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define PSWRD2_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY                                                         (0x1<<0) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_1.MEM005_I_MEM_PRTY .
+  #define PSWRD2_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY_SHIFT                                                   0
+  #define PSWRD2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY                                                         (0x1<<1) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY .
+  #define PSWRD2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_SHIFT                                                   1
+  #define PSWRD2_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY                                                         (0x1<<2) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY .
+  #define PSWRD2_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_SHIFT                                                   2
+#define PSWRD2_REG_MEM019_RF_ECC_ERROR_CONNECT                                                               0x29d220UL //Access:W    DataWidth:0x10   // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define PSWRD2_REG_MEM020_RF_ECC_ERROR_CONNECT                                                               0x29d224UL //Access:W    DataWidth:0x10   // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define PSWRD2_REG_MEM021_RF_ECC_ERROR_CONNECT                                                               0x29d228UL //Access:W    DataWidth:0x10   // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define PSWRD2_REG_MEM022_RF_ECC_ERROR_CONNECT                                                               0x29d22cUL //Access:W    DataWidth:0x10   // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define PSWRD2_REG_MEM023_RF_ECC_ERROR_CONNECT                                                               0x29d230UL //Access:W    DataWidth:0x10   // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define PSWRD2_REG_MEM024_RF_ECC_ERROR_CONNECT                                                               0x29d234UL //Access:W    DataWidth:0x10   // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define PSWRD2_REG_MEM025_RF_ECC_ERROR_CONNECT                                                               0x29d238UL //Access:W    DataWidth:0x10   // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define PSWRD2_REG_MEM_ECC_ENABLE_0                                                                          0x29d23cUL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM017_I_ECC_EN                                                        (0x1<<0) // Enable ECC for memory ecc instance pswrd.TETRIS_32_GEN_FOR[0].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw
+  #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM017_I_ECC_EN_SHIFT                                                  0
+  #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM018_I_ECC_EN                                                        (0x1<<1) // Enable ECC for memory ecc instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw
+  #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM018_I_ECC_EN_SHIFT                                                  1
+  #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM019_I_ECC_EN                                                        (0x1<<2) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
+  #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM019_I_ECC_EN_SHIFT                                                  2
+  #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM020_I_ECC_EN                                                        (0x1<<3) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
+  #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM020_I_ECC_EN_SHIFT                                                  3
+  #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_EN                                                        (0x1<<4) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
+  #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_EN_SHIFT                                                  4
+  #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_EN                                                        (0x1<<5) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
+  #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_EN_SHIFT                                                  5
+  #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_EN                                                        (0x1<<6) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
+  #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_EN_SHIFT                                                  6
+  #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_EN                                                        (0x1<<7) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
+  #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_EN_SHIFT                                                  7
+  #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_EN                                                        (0x1<<8) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
+  #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_EN_SHIFT                                                  8
+  #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN                                                        (0x1<<9) // Enable ECC for memory ecc instance pswrd.SYNC_FIFO_GEN_PBF_FOR[6].SYNC_FIFO_GEN_PBF_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fifo_pbf_mem_wrap
+  #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN_SHIFT                                                  9
+#define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0                                                                     0x29d240UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM017_I_ECC_PRTY                                                 (0x1<<0) // Set parity only for memory ecc instance pswrd.TETRIS_32_GEN_FOR[0].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw
+  #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM017_I_ECC_PRTY_SHIFT                                           0
+  #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM018_I_ECC_PRTY                                                 (0x1<<1) // Set parity only for memory ecc instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw
+  #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM018_I_ECC_PRTY_SHIFT                                           1
+  #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM019_I_ECC_PRTY                                                 (0x1<<2) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
+  #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM019_I_ECC_PRTY_SHIFT                                           2
+  #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM020_I_ECC_PRTY                                                 (0x1<<3) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
+  #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM020_I_ECC_PRTY_SHIFT                                           3
+  #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_PRTY                                                 (0x1<<4) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
+  #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_PRTY_SHIFT                                           4
+  #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_PRTY                                                 (0x1<<5) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
+  #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_PRTY_SHIFT                                           5
+  #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_PRTY                                                 (0x1<<6) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
+  #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_PRTY_SHIFT                                           6
+  #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_PRTY                                                 (0x1<<7) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
+  #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_PRTY_SHIFT                                           7
+  #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_PRTY                                                 (0x1<<8) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
+  #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_PRTY_SHIFT                                           8
+  #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY                                                 (0x1<<9) // Set parity only for memory ecc instance pswrd.SYNC_FIFO_GEN_PBF_FOR[6].SYNC_FIFO_GEN_PBF_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fifo_pbf_mem_wrap
+  #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY_SHIFT                                           9
+#define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0                                                                 0x29d244UL //Access:RC   DataWidth:0xa    // Multi Field Register.
+  #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM017_I_ECC_CORRECT                                          (0x1<<0) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_32_GEN_FOR[0].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw
+  #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM017_I_ECC_CORRECT_SHIFT                                    0
+  #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM018_I_ECC_CORRECT                                          (0x1<<1) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw
+  #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM018_I_ECC_CORRECT_SHIFT                                    1
+  #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM019_I_ECC_CORRECT                                          (0x1<<2) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
+  #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM019_I_ECC_CORRECT_SHIFT                                    2
+  #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM020_I_ECC_CORRECT                                          (0x1<<3) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
+  #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM020_I_ECC_CORRECT_SHIFT                                    3
+  #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_CORRECT                                          (0x1<<4) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
+  #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_CORRECT_SHIFT                                    4
+  #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_CORRECT                                          (0x1<<5) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
+  #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_CORRECT_SHIFT                                    5
+  #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_CORRECT                                          (0x1<<6) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
+  #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_CORRECT_SHIFT                                    6
+  #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_CORRECT                                          (0x1<<7) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
+  #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_CORRECT_SHIFT                                    7
+  #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_CORRECT                                          (0x1<<8) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
+  #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_CORRECT_SHIFT                                    8
+  #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT                                          (0x1<<9) // Record if a correctable error occurred on memory ecc instance pswrd.SYNC_FIFO_GEN_PBF_FOR[6].SYNC_FIFO_GEN_PBF_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fifo_pbf_mem_wrap
+  #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT_SHIFT                                    9
+#define PSWRD2_REG_MEM_ECC_EVENTS                                                                            0x29d248UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define PSWRD2_REG_DBG_SELECT                                                                                0x29d400UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PSWRD2_REG_DBG_DWORD_ENABLE                                                                          0x29d404UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PSWRD2_REG_DBG_SHIFT                                                                                 0x29d408UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PSWRD2_REG_DBG_FORCE_VALID                                                                           0x29d40cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PSWRD2_REG_DBG_FORCE_FRAME                                                                           0x29d410UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PSWRD2_REG_DBG_OUT_DATA                                                                              0x29d420UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PSWRD2_REG_DBG_OUT_DATA_SIZE                                                                         8
+#define PSWRD2_REG_DBG_OUT_VALID                                                                             0x29d440UL //Access:R    DataWidth:0x4    // Dbgmux output valid
+#define PSWRD2_REG_DBG_OUT_FRAME                                                                             0x29d444UL //Access:R    DataWidth:0x4    // Dbgmux output frame
+#define PSWRD2_REG_DISABLE_INPUTS                                                                            0x29d460UL //Access:RW   DataWidth:0x1    // When '1'; inputs to the PSWRD block are ignored.
+#define PSWRD2_REG_SR_NUM_CFG                                                                                0x29d464UL //Access:RW   DataWidth:0x7    // Debug only: Total number of available PCI read sub-requests. Must be bigger than 1. Normally should not be changed. Should have identical value to rq_sr_num_cfg.
+#define PSWRD2_REG_BLK_NUM_CFG                                                                               0x29d468UL //Access:RW   DataWidth:0x9    // Debug only: Total number of available blocks in Tetris Buffer. Must be bigger than 6. Normally should not be changed. Should have identical value to rq_blk_num_cfg.
+#define PSWRD2_REG_ATC_GLOBAL_ENABLE                                                                         0x29d46cUL //Access:RW   DataWidth:0x1    // Global ATC enable bit. When reset all ATC logic is disabled within the PSWRD. 'ATC entry ID' interface from PSWRQ is ignored and 'ATC RCPL Done' interface to ATC is not generated. The value of this register must be the same as PSWRQ_ATC_GLOBAL_ENABLE. This value must be '1' when ATC capability is enabled in PCIe core.
+#define PSWRD2_REG_CONTINUE_SERVING_PBF                                                                      0x29d470UL //Access:RW   DataWidth:0x1    // This register defines the delivery port behavior when finishing delivering a request to the PBF and the data for the next request is already in the Tetris buffer. 0 - The delivery port continues delivering the next PBF request only if the second delivery port is idle. This is the behavior in E1 E1H and E2. 1 - The delivery port always continues delivering the next PBF request. This is more efficient since about 11 arbitration cycles are not wasted.
+#define PSWRD2_REG_USDM_ADDITIONAL_REQUESTS                                                                  0x29d474UL //Access:RW   DataWidth:0x2    // When finishing delivering a request to this client; this register determines the number of additional requests to deliver to the client without doing arbitration again. This configuration is for all clients except PBF (for PBF the number of additional requests to deliver is unlimited). This feature can save arbitration overhead.
+#define PSWRD2_REG_XSDM_ADDITIONAL_REQUESTS                                                                  0x29d478UL //Access:RW   DataWidth:0x2    // When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.
+#define PSWRD2_REG_MSDM_ADDITIONAL_REQUESTS                                                                  0x29d47cUL //Access:RW   DataWidth:0x2    // When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.
+#define PSWRD2_REG_YSDM_ADDITIONAL_REQUESTS                                                                  0x29d480UL //Access:RW   DataWidth:0x2    // When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.
+#define PSWRD2_REG_PSDM_ADDITIONAL_REQUESTS                                                                  0x29d484UL //Access:RW   DataWidth:0x2    // When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.
+#define PSWRD2_REG_TSDM_ADDITIONAL_REQUESTS                                                                  0x29d488UL //Access:RW   DataWidth:0x2    // When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.
+#define PSWRD2_REG_QM_ADDITIONAL_REQUESTS                                                                    0x29d48cUL //Access:RW   DataWidth:0x2    // When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.
+#define PSWRD2_REG_TM_ADDITIONAL_REQUESTS                                                                    0x29d490UL //Access:RW   DataWidth:0x2    // When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.
+#define PSWRD2_REG_SRC_ADDITIONAL_REQUESTS                                                                   0x29d494UL //Access:RW   DataWidth:0x2    // When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.
+#define PSWRD2_REG_CDU_ADDITIONAL_REQUESTS                                                                   0x29d498UL //Access:RW   DataWidth:0x2    // When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.
+#define PSWRD2_REG_DMAE_ADDITIONAL_REQUESTS                                                                  0x29d49cUL //Access:RW   DataWidth:0x2    // When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.
+#define PSWRD2_REG_MULD_ADDITIONAL_REQUESTS                                                                  0x29d4a0UL //Access:RW   DataWidth:0x2    // When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.
+#define PSWRD2_REG_XYLD_ADDITIONAL_REQUESTS                                                                  0x29d4a4UL //Access:RW   DataWidth:0x2    // When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.
+#define PSWRD2_REG_PTU_ADDITIONAL_REQUESTS                                                                   0x29d4a8UL //Access:RW   DataWidth:0x2    // When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.
+#define PSWRD2_REG_PRM_ADDITIONAL_REQUESTS                                                                   0x29d4acUL //Access:RW   DataWidth:0x2    // When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.
+#define PSWHST2_REG_HEADER_FIFO_STATUS                                                                       0x29e040UL //Access:R    DataWidth:0x7    // Debug only: Number of used entries in the header FIFO.
+#define PSWHST2_REG_DATA_FIFO_STATUS                                                                         0x29e044UL //Access:R    DataWidth:0x7    // Debug only: Number of used entries in the data FIFO.
+#define PSWHST2_REG_HEADER_FIFO_MAX_ENTRIES                                                                  0x29e048UL //Access:R    DataWidth:0x7    // Debug only: Maximum number of entries that were used in the header FIFO.
+#define PSWHST2_REG_DATA_FIFO_MAX_ENTRIES                                                                    0x29e04cUL //Access:R    DataWidth:0x7    // Debug only: Maximum number of entries that were used in the data FIFO.
+#define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR                                                                   0x29e050UL //Access:RW   DataWidth:0x4    // Debug only: If more than this Number of entries are occupied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed. This value is an output from PSWHST to pxp_dbgsyn.
+#define PSWHST2_REG_ECO_RESERVED                                                                             0x29e054UL //Access:RW   DataWidth:0x5    // Debug only: Reserved bits for ECO.
+#define PSWHST2_REG_DBG_SELECT                                                                               0x29e058UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PSWHST2_REG_DBG_DWORD_ENABLE                                                                         0x29e05cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PSWHST2_REG_DBG_SHIFT                                                                                0x29e060UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PSWHST2_REG_DBG_FORCE_VALID                                                                          0x29e064UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PSWHST2_REG_DBG_FORCE_FRAME                                                                          0x29e068UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PSWHST2_REG_DBG_OUT_DATA                                                                             0x29e080UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PSWHST2_REG_DBG_OUT_DATA_SIZE                                                                        8
+#define PSWHST2_REG_DBG_OUT_VALID                                                                            0x29e0a0UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define PSWHST2_REG_DBG_OUT_FRAME                                                                            0x29e0a4UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define PSWHST2_REG_INT_STS                                                                                  0x29e180UL //Access:R    DataWidth:0x5    // Multi Field Register.
+  #define PSWHST2_REG_INT_STS_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSWHST2_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                            0
+  #define PSWHST2_REG_INT_STS_HST_HEADER_FIFO_ERR                                                            (0x1<<1) // An error in the header clock sync  FIFO.
+  #define PSWHST2_REG_INT_STS_HST_HEADER_FIFO_ERR_SHIFT                                                      1
+  #define PSWHST2_REG_INT_STS_HST_DATA_FIFO_ERR                                                              (0x1<<2) // An error in the data clock sync  FIFO.
+  #define PSWHST2_REG_INT_STS_HST_DATA_FIFO_ERR_SHIFT                                                        2
+  #define PSWHST2_REG_INT_STS_HST_CPL_FIFO_ERR                                                               (0x1<<3) // An error in the completion clock sync  FIFO.
+  #define PSWHST2_REG_INT_STS_HST_CPL_FIFO_ERR_SHIFT                                                         3
+  #define PSWHST2_REG_INT_STS_HST_IREQ_FIFO_ERR                                                              (0x1<<4) // An error in the ireq clock sync  FIFO. Removed in E5.
+  #define PSWHST2_REG_INT_STS_HST_IREQ_FIFO_ERR_SHIFT                                                        4
+#define PSWHST2_REG_INT_MASK                                                                                 0x29e184UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define PSWHST2_REG_INT_MASK_ADDRESS_ERROR                                                                 (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWHST2_REG_INT_STS.ADDRESS_ERROR .
+  #define PSWHST2_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                           0
+  #define PSWHST2_REG_INT_MASK_HST_HEADER_FIFO_ERR                                                           (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWHST2_REG_INT_STS.HST_HEADER_FIFO_ERR .
+  #define PSWHST2_REG_INT_MASK_HST_HEADER_FIFO_ERR_SHIFT                                                     1
+  #define PSWHST2_REG_INT_MASK_HST_DATA_FIFO_ERR                                                             (0x1<<2) // This bit masks, when set, the Interrupt bit: PSWHST2_REG_INT_STS.HST_DATA_FIFO_ERR .
+  #define PSWHST2_REG_INT_MASK_HST_DATA_FIFO_ERR_SHIFT                                                       2
+  #define PSWHST2_REG_INT_MASK_HST_CPL_FIFO_ERR                                                              (0x1<<3) // This bit masks, when set, the Interrupt bit: PSWHST2_REG_INT_STS.HST_CPL_FIFO_ERR .
+  #define PSWHST2_REG_INT_MASK_HST_CPL_FIFO_ERR_SHIFT                                                        3
+  #define PSWHST2_REG_INT_MASK_HST_IREQ_FIFO_ERR                                                             (0x1<<4) // This bit masks, when set, the Interrupt bit: PSWHST2_REG_INT_STS.HST_IREQ_FIFO_ERR .
+  #define PSWHST2_REG_INT_MASK_HST_IREQ_FIFO_ERR_SHIFT                                                       4
+#define PSWHST2_REG_INT_STS_WR                                                                               0x29e188UL //Access:WR   DataWidth:0x5    // Multi Field Register.
+  #define PSWHST2_REG_INT_STS_WR_ADDRESS_ERROR                                                               (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSWHST2_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                         0
+  #define PSWHST2_REG_INT_STS_WR_HST_HEADER_FIFO_ERR                                                         (0x1<<1) // An error in the header clock sync  FIFO.
+  #define PSWHST2_REG_INT_STS_WR_HST_HEADER_FIFO_ERR_SHIFT                                                   1
+  #define PSWHST2_REG_INT_STS_WR_HST_DATA_FIFO_ERR                                                           (0x1<<2) // An error in the data clock sync  FIFO.
+  #define PSWHST2_REG_INT_STS_WR_HST_DATA_FIFO_ERR_SHIFT                                                     2
+  #define PSWHST2_REG_INT_STS_WR_HST_CPL_FIFO_ERR                                                            (0x1<<3) // An error in the completion clock sync  FIFO.
+  #define PSWHST2_REG_INT_STS_WR_HST_CPL_FIFO_ERR_SHIFT                                                      3
+  #define PSWHST2_REG_INT_STS_WR_HST_IREQ_FIFO_ERR                                                           (0x1<<4) // An error in the ireq clock sync  FIFO. Removed in E5.
+  #define PSWHST2_REG_INT_STS_WR_HST_IREQ_FIFO_ERR_SHIFT                                                     4
+#define PSWHST2_REG_INT_STS_CLR                                                                              0x29e18cUL //Access:RC   DataWidth:0x5    // Multi Field Register.
+  #define PSWHST2_REG_INT_STS_CLR_ADDRESS_ERROR                                                              (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSWHST2_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                        0
+  #define PSWHST2_REG_INT_STS_CLR_HST_HEADER_FIFO_ERR                                                        (0x1<<1) // An error in the header clock sync  FIFO.
+  #define PSWHST2_REG_INT_STS_CLR_HST_HEADER_FIFO_ERR_SHIFT                                                  1
+  #define PSWHST2_REG_INT_STS_CLR_HST_DATA_FIFO_ERR                                                          (0x1<<2) // An error in the data clock sync  FIFO.
+  #define PSWHST2_REG_INT_STS_CLR_HST_DATA_FIFO_ERR_SHIFT                                                    2
+  #define PSWHST2_REG_INT_STS_CLR_HST_CPL_FIFO_ERR                                                           (0x1<<3) // An error in the completion clock sync  FIFO.
+  #define PSWHST2_REG_INT_STS_CLR_HST_CPL_FIFO_ERR_SHIFT                                                     3
+  #define PSWHST2_REG_INT_STS_CLR_HST_IREQ_FIFO_ERR                                                          (0x1<<4) // An error in the ireq clock sync  FIFO. Removed in E5.
+  #define PSWHST2_REG_INT_STS_CLR_HST_IREQ_FIFO_ERR_SHIFT                                                    4
+#define PSWHST2_REG_PRTY_MASK                                                                                0x29e194UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define PSWHST2_REG_PRTY_MASK_DATAPATH_REGISTERS                                                           (0x1<<0) // This bit masks, when set, the Parity bit: PSWHST2_REG_PRTY_STS.DATAPATH_REGISTERS .
+  #define PSWHST2_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                                     0
+#define PSWHST_REG_ZONE_PERM_TABLE_INIT                                                                      0x2a0000UL //Access:RW   DataWidth:0x1    // Start the Init sequence for the zone permission table.
+#define PSWHST_REG_ZONE_PERM_TABLE_INIT_DONE                                                                 0x2a0004UL //Access:RC   DataWidth:0x1    // Done indication for the permission table's init sequence. Driver should check the value of this register is 1 some time after it wrote 1 to zone_perm_table_init.
+#define PSWHST_REG_DISCARD_INTERNAL_WRITES                                                                   0x2a0040UL //Access:RW   DataWidth:0x1    // When 1; new internal writes arriving to the block are discarded. Should be used for close the gates.
+#define PSWHST_REG_DISCARD_DOORBELLS                                                                         0x2a0044UL //Access:RW   DataWidth:0x1    // When 1; doorbells are discarded and not passed to doorbell queue block. Should be used for close the gates.
+#define PSWHST_REG_DISCARD_P2M                                                                               0x2a0048UL //Access:RW   DataWidth:0x1    // When 1; p2m are discarded and not passed to p2m queue block. Should be used for close the gates.
+#define PSWHST_REG_DISCARD_INTERNAL_WRITES_STATUS                                                            0x2a004cUL //Access:R    DataWidth:0x9    // Debug only: A bit mask for all PSWHST internal write clients. '1' means this PSWHST is discarding inputs from this client. Each bit should update accoring to 'hst_discard_internal_writes' register when the state machine is idle.
+#define PSWHST_REG_DISCARD_DOORBELLS_STATUS                                                                  0x2a0050UL //Access:R    DataWidth:0x1    // Debug only: '1' means this PSWHST is discarding doorbells. This bit should update accoring to 'hst_discard_doorbells' register when the state machine is idle.
+#define PSWHST_REG_DISCARD_P2M_STATUS                                                                        0x2a0054UL //Access:R    DataWidth:0x1    // Debug only: '1' means this PSWHST is discarding p2m. This bit should update accoring to 'hst_discard_p2m' register when the state machine is idle.
+#define PSWHST_REG_ARB_IS_IDLE                                                                               0x2a0058UL //Access:R    DataWidth:0x2    // Debug only: A bit per arbiter-engine indicating if the engine is idle. Idle means the engine is not sending request (and therefore no credits from the target means the arbiter-engine is idle which is different than E3).
+#define PSWHST_REG_VF_DISABLED_ERROR_DATA                                                                    0x2a005cUL //Access:R    DataWidth:0x12   // The FID of the first access to a disabled VF; the format is [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 HC; 7 GRC; 8 DQ; 9 ATC; 10 RESERVED SPACE); [0] - w_nr(0-read req; 1- write req). The data is written only when the valid bit is reset. and it is stays stable until it is reset by the read from interrupt_clr register.
+#define PSWHST_REG_VF_DISABLED_ERROR_VALID                                                                   0x2a0060UL //Access:R    DataWidth:0x1    // 1 - An error request is logged.
+#define PSWHST_REG_VF_DISABLED_ERROR_ADDRESS                                                                 0x2a0064UL //Access:R    DataWidth:0x20   // The address of the first access to a disabled VF.
+#define PSWHST_REG_INCORRECT_ACCESS_DATA                                                                     0x2a0068UL //Access:R    DataWidth:0x20   // The data of the first incorrect access. the format is: [31:26] - RSV [25:18] - byte enable; [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 HC; 7 GRC; 8 DQ; 9 ATC; 10 RESERVED SPACE); [0] - w_nr(0-read req; 1- write req). The data is written only when the valid bit is reset. and it is stays stable until it is reset by the read from interrupt_clr register.
+#define PSWHST_REG_INCORRECT_ACCESS_LENGTH                                                                   0x2a006cUL //Access:R    DataWidth:0x7    // The data of the first incorrect access. the format is: [6:0] - length in DWs. The data is written only when the valid bit is reset. and it is stays stable until it is reset by the read from interrupt_clr register.
+#define PSWHST_REG_INCORRECT_ACCESS_VALID                                                                    0x2a0070UL //Access:R    DataWidth:0x1    // 1 - An incorrect access is logged. The valid bit is reset when the relevant interrupt register is read (PXP_REG_INT_STS_CLR_1).
+#define PSWHST_REG_INCORRECT_ACCESS_ADDRESS                                                                  0x2a0074UL //Access:R    DataWidth:0x20   // The address of the first incorrect access (length and alignement combination).
+#define PSWHST_REG_PER_VIOLATION_VALID                                                                       0x2a0078UL //Access:R    DataWidth:0x1    // 1- permission violation data is logged. The valid bit is reset when the relevant interrupt register is read.
+#define PSWHST_REG_PER_VIOLATION_DATA                                                                        0x2a007cUL //Access:R    DataWidth:0x11   // Log of the permission violation: {QID[8:0];VFID[7:0]}.
+#define PSWHST_REG_SOURCE_SDM_CREDITS                                                                        0x2a0080UL //Access:RW   DataWidth:0x2    // Number of credits for source SDM in internal write interface (common to all SDMs except USDM). PSWHST issues an attention if more credits are consumed.
+#define PSWHST_REG_SOURCE_PBF_CREDITS                                                                        0x2a0084UL //Access:RW   DataWidth:0x2    // Number of credits for source SDM in internal write interface. PSWHST issues an attention if more credits are consumed.
+#define PSWHST_REG_SOURCE_QM_CREDITS                                                                         0x2a0088UL //Access:RW   DataWidth:0x3    // Number of credits for source SDM in internal write interface. PSWHST issues an attention if more credits are consumed.
+#define PSWHST_REG_SOURCE_CREDITS_AVAIL                                                                      0x2a008cUL //Access:R    DataWidth:0x13   // Number of available credits for source in internal write interface: [1:0] usdm; [3:2] xsdm; [5:4] msdm; [7:6] ysdm; [9:8] psdm; [11:10] tsdm; [13:12] pbf; [16:14] qm; [18:17] nig.
+#define PSWHST_REG_SOURCE_CREDIT_VIOL_DATA                                                                   0x2a0090UL //Access:R    DataWidth:0x4    // The data of the first internal write source that consumed more than its allowed credits. the format is: [3:0] - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 PBF; 7 QM; 8 NIG).
+#define PSWHST_REG_SOURCE_CREDIT_VIOL_VALID                                                                  0x2a0094UL //Access:R    DataWidth:0x1    // 1 - A source credit violation is logged. The valid bit is reset when the relevant interrupt register is read (PXP_REG_INT_STS_CLR_1).
+#define PSWHST_REG_DEST_SDM_CREDITS                                                                          0x2a0098UL //Access:RW   DataWidth:0x2    // Number of credits for destination SDM in target write interface (common to all SDMs).
+#define PSWHST_REG_DEST_IGU_CREDITS                                                                          0x2a009cUL //Access:RW   DataWidth:0x2    // Number of credits for destination IGU in target write interface.
+#define PSWHST_REG_DEST_CAU_CREDITS                                                                          0x2a00a0UL //Access:RW   DataWidth:0x2    // Number of credits for destination CAU in target write interface.
+#define PSWHST_REG_DEST_CREDITS_AVAIL                                                                        0x2a00a4UL //Access:R    DataWidth:0x10   // Number of available credits for destination in internal write interface. [1:0] usdm; [3:2] xsdm; [5:4] msdm; [7:6] ysdm; [9:8] psdm; [11:10] tsdm; [13:12] igu; [15:14] cau.
+#define PSWHST_REG_TIMEOUT                                                                                   0x2a00a8UL //Access:RW   DataWidth:0x1e   // Number of cycles to wait before entering drain mode.
+#define PSWHST_REG_IS_IN_DRAIN_MODE                                                                          0x2a00acUL //Access:R    DataWidth:0x1    // 1 - PSWHST is in drain mode.
+#define PSWHST_REG_EXIT_DRAIN_MODE                                                                           0x2a00b0UL //Access:W    DataWidth:0x1    // Writing 1 to this register indicates PSWHST to exit drain mode.
+#define PSWHST_REG_TIMEOUT_DATA                                                                              0x2a00b4UL //Access:R    DataWidth:0x20   // The data of the request that hst_timeout happened while it was processed. the format is (for non P2M): [31:26] - length in DWs; [25:18] - byte enable; [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 HC; 7 GRC; 8 DQ; 9 ATC; 10 RESERVED SPACE); [0] - w_nr(0-read req; 1- write req). for p2m: [24:18] VDM length; [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (P2M); [0] - w_nr(0-read req; 1- write req). The data is written only when the valid bit is reset. and it is stays stable until exiting drain mode.
+#define PSWHST_REG_TIMEOUT_VALID                                                                             0x2a00b8UL //Access:R    DataWidth:0x1    // 1 - An hst timeout data is logged. The valid bit is reset when exiting drain mode (writing to hst_exit_drain_mode).
+#define PSWHST_REG_TIMEOUT_ADDRESS                                                                           0x2a00bcUL //Access:R    DataWidth:0x20   // The address of the first incorrect access (length and alignement combination). not relevant for P2M logging
+#define PSWHST_REG_SOURCE_USDM_CREDITS                                                                       0x2a00c0UL //Access:RW   DataWidth:0x2    // Number of credits for source USDM in internal write interface. PSWHST issues an attention if more credits are consumed. Added in BB-B0 due to pipeline.
+#define PSWHST_REG_DEST_DORQ_CREDITS_E5                                                                      0x2a00c4UL //Access:RW   DataWidth:0x2    // Number of credits for destination DORQ in target write interface.
+#define PSWHST_REG_HOST_STRICT_PRIORITY                                                                      0x2a00c8UL //Access:RW   DataWidth:0x1    // When 1; host requests have strict priority on internal write requests; as in A0. When 0; arbiter alternately chooses host requests and internal write requests.
+#define PSWHST_REG_SDM_MAX_LENGTH                                                                            0x2a00ccUL //Access:RW   DataWidth:0x6    // Maximum write transaction data in DWs that is sent to SDMs and IGU. Write requests with bigger length are discarded in PSWHST.
+#define PSWHST_REG_ECO_RESERVED                                                                              0x2a00d0UL //Access:RW   DataWidth:0xa    // Debug only: Reserved bits for ECO.
+#define PSWHST_REG_USDM_SWAP_MODE                                                                            0x2a00d4UL //Access:RW   DataWidth:0x2    // USDM byte swapping mode configuration for host read and write requests.
+#define PSWHST_REG_XSDM_SWAP_MODE                                                                            0x2a00d8UL //Access:RW   DataWidth:0x2    // XSDM byte swapping mode configuration for host read and write requests.
+#define PSWHST_REG_TSDM_SWAP_MODE                                                                            0x2a00dcUL //Access:RW   DataWidth:0x2    // TSDM byte swapping mode configuration for host read and write requests.
+#define PSWHST_REG_HC_SWAP_MODE                                                                              0x2a00e0UL //Access:RW   DataWidth:0x2    // HC byte swapping mode configuration for host read and write requests.
+#define PSWHST_REG_GRC_SWAP_MODE                                                                             0x2a00e4UL //Access:RW   DataWidth:0x2    // GRC byte swapping mode configuration for host read and write requests.
+#define PSWHST_REG_DQ_SWAP_MODE                                                                              0x2a00e8UL //Access:RW   DataWidth:0x2    // DORQ byte swapping mode configuration for host read and write requests.
+#define PSWHST_REG_P2M_SWAP_MODE                                                                             0x2a00ecUL //Access:RW   DataWidth:0x2    // P2M byte swapping mode configuration for host read and write requests.
+#define PSWHST_REG_MSDM_SWAP_MODE                                                                            0x2a00f0UL //Access:RW   DataWidth:0x2    // MSDM byte swapping mode configuration for host read and write requests.
+#define PSWHST_REG_YSDM_SWAP_MODE                                                                            0x2a00f4UL //Access:RW   DataWidth:0x2    // YSDM byte swapping mode configuration for host read and write requests.
+#define PSWHST_REG_PSDM_SWAP_MODE                                                                            0x2a00f8UL //Access:RW   DataWidth:0x2    // PSDM byte swapping mode configuration for host read and write requests.
+#define PSWHST_REG_DBG_SELECT                                                                                0x2a0100UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PSWHST_REG_DBG_DWORD_ENABLE                                                                          0x2a0104UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PSWHST_REG_DBG_SHIFT                                                                                 0x2a0108UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PSWHST_REG_DBG_FORCE_VALID                                                                           0x2a010cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PSWHST_REG_DBG_FORCE_FRAME                                                                           0x2a0110UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PSWHST_REG_DBG_OUT_DATA                                                                              0x2a0120UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PSWHST_REG_DBG_OUT_DATA_SIZE                                                                         8
+#define PSWHST_REG_DBG_OUT_VALID                                                                             0x2a0140UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define PSWHST_REG_DBG_OUT_FRAME                                                                             0x2a0144UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define PSWHST_REG_CLIENTS_WAITING_TO_SOURCE_ARB                                                             0x2a0160UL //Access:R    DataWidth:0xb    // Debug only: Each entry contains a bit mask for PSWHST source arbiter clients. '1' means this client is waiting for the arbiter. Each entry refers to a different source arbiter. Entry decoding: (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 IGU; 7 CAU). Bit mask decoding: (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 PBF; 7 QM; 8 NIG; 9 HOST WR; 10 HOST RD).
+#define PSWHST_REG_CLIENTS_WAITING_TO_SOURCE_ARB_SIZE                                                        8
+#define PSWHST_REG_INT_STS                                                                                   0x2a0180UL //Access:R    DataWidth:0x12   // Multi Field Register.
+  #define PSWHST_REG_INT_STS_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSWHST_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                             0
+  #define PSWHST_REG_INT_STS_HST_SRC_FIFO1_ERR                                                               (0x1<<1) // An error in write source FIFO 1.
+  #define PSWHST_REG_INT_STS_HST_SRC_FIFO1_ERR_SHIFT                                                         1
+  #define PSWHST_REG_INT_STS_HST_SRC_FIFO2_ERR                                                               (0x1<<2) // An error in write source FIFO 2.
+  #define PSWHST_REG_INT_STS_HST_SRC_FIFO2_ERR_SHIFT                                                         2
+  #define PSWHST_REG_INT_STS_HST_SRC_FIFO3_ERR                                                               (0x1<<3) // An error in write source FIFO 3.
+  #define PSWHST_REG_INT_STS_HST_SRC_FIFO3_ERR_SHIFT                                                         3
+  #define PSWHST_REG_INT_STS_HST_SRC_FIFO4_ERR                                                               (0x1<<4) // An error in write source FIFO 4.
+  #define PSWHST_REG_INT_STS_HST_SRC_FIFO4_ERR_SHIFT                                                         4
+  #define PSWHST_REG_INT_STS_HST_SRC_FIFO5_ERR                                                               (0x1<<5) // An error in write source FIFO 5.
+  #define PSWHST_REG_INT_STS_HST_SRC_FIFO5_ERR_SHIFT                                                         5
+  #define PSWHST_REG_INT_STS_HST_HDR_SYNC_FIFO_ERR                                                           (0x1<<6) // An error in header clock sync FIFO.
+  #define PSWHST_REG_INT_STS_HST_HDR_SYNC_FIFO_ERR_SHIFT                                                     6
+  #define PSWHST_REG_INT_STS_HST_DATA_SYNC_FIFO_ERR                                                          (0x1<<7) // An error in data clock sync FIFO.
+  #define PSWHST_REG_INT_STS_HST_DATA_SYNC_FIFO_ERR_SHIFT                                                    7
+  #define PSWHST_REG_INT_STS_HST_CPL_SYNC_FIFO_ERR                                                           (0x1<<8) // An error in completion clock sync FIFO.
+  #define PSWHST_REG_INT_STS_HST_CPL_SYNC_FIFO_ERR_SHIFT                                                     8
+  #define PSWHST_REG_INT_STS_HST_VF_DISABLED_ACCESS                                                          (0x1<<9) // Indicates there was an access to a disabled VF when client is not IGU or ATC (so access is dropped). The disabled vf registers are valid when it is set and reset when the interrupt clr is read.
+  #define PSWHST_REG_INT_STS_HST_VF_DISABLED_ACCESS_SHIFT                                                    9
+  #define PSWHST_REG_INT_STS_HST_PERMISSION_VIOLATION                                                        (0x1<<10) // Indicates Zone permission violation.  The relevant data is stored in hst_per_violation_data.
+  #define PSWHST_REG_INT_STS_HST_PERMISSION_VIOLATION_SHIFT                                                  10
+  #define PSWHST_REG_INT_STS_HST_INCORRECT_ACCESS                                                            (0x1<<11) // Indicates there was an access to any of the clients  with incorrect length and alignement. Details are logged in incorrect access registers. The incorrect access registers are valid when it is set and reset when the interrupt clr is read.
+  #define PSWHST_REG_INT_STS_HST_INCORRECT_ACCESS_SHIFT                                                      11
+  #define PSWHST_REG_INT_STS_HST_SRC_FIFO6_ERR                                                               (0x1<<12) // An error in write source FIFO 6.
+  #define PSWHST_REG_INT_STS_HST_SRC_FIFO6_ERR_SHIFT                                                         12
+  #define PSWHST_REG_INT_STS_HST_SRC_FIFO7_ERR                                                               (0x1<<13) // An error in write source FIFO 7.
+  #define PSWHST_REG_INT_STS_HST_SRC_FIFO7_ERR_SHIFT                                                         13
+  #define PSWHST_REG_INT_STS_HST_SRC_FIFO8_ERR                                                               (0x1<<14) // An error in write source FIFO 8.
+  #define PSWHST_REG_INT_STS_HST_SRC_FIFO8_ERR_SHIFT                                                         14
+  #define PSWHST_REG_INT_STS_HST_SRC_FIFO9_ERR                                                               (0x1<<15) // An error in write source FIFO 9 (PBF).
+  #define PSWHST_REG_INT_STS_HST_SRC_FIFO9_ERR_SHIFT                                                         15
+  #define PSWHST_REG_INT_STS_HST_SOURCE_CREDIT_VIOLATION                                                     (0x1<<16) // Indicates an internal write source credit violation.  The relevant data is stored in hst_source_credit_viol_data.
+  #define PSWHST_REG_INT_STS_HST_SOURCE_CREDIT_VIOLATION_SHIFT                                               16
+  #define PSWHST_REG_INT_STS_HST_TIMEOUT                                                                     (0x1<<17) // Indicates hst_timeout occurred.
+  #define PSWHST_REG_INT_STS_HST_TIMEOUT_SHIFT                                                               17
+#define PSWHST_REG_INT_MASK                                                                                  0x2a0184UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSWHST_REG_INT_MASK_ADDRESS_ERROR                                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.ADDRESS_ERROR .
+  #define PSWHST_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                            0
+  #define PSWHST_REG_INT_MASK_HST_SRC_FIFO1_ERR                                                              (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO1_ERR .
+  #define PSWHST_REG_INT_MASK_HST_SRC_FIFO1_ERR_SHIFT                                                        1
+  #define PSWHST_REG_INT_MASK_HST_SRC_FIFO2_ERR                                                              (0x1<<2) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO2_ERR .
+  #define PSWHST_REG_INT_MASK_HST_SRC_FIFO2_ERR_SHIFT                                                        2
+  #define PSWHST_REG_INT_MASK_HST_SRC_FIFO3_ERR                                                              (0x1<<3) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO3_ERR .
+  #define PSWHST_REG_INT_MASK_HST_SRC_FIFO3_ERR_SHIFT                                                        3
+  #define PSWHST_REG_INT_MASK_HST_SRC_FIFO4_ERR                                                              (0x1<<4) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO4_ERR .
+  #define PSWHST_REG_INT_MASK_HST_SRC_FIFO4_ERR_SHIFT                                                        4
+  #define PSWHST_REG_INT_MASK_HST_SRC_FIFO5_ERR                                                              (0x1<<5) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO5_ERR .
+  #define PSWHST_REG_INT_MASK_HST_SRC_FIFO5_ERR_SHIFT                                                        5
+  #define PSWHST_REG_INT_MASK_HST_HDR_SYNC_FIFO_ERR                                                          (0x1<<6) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_HDR_SYNC_FIFO_ERR .
+  #define PSWHST_REG_INT_MASK_HST_HDR_SYNC_FIFO_ERR_SHIFT                                                    6
+  #define PSWHST_REG_INT_MASK_HST_DATA_SYNC_FIFO_ERR                                                         (0x1<<7) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_DATA_SYNC_FIFO_ERR .
+  #define PSWHST_REG_INT_MASK_HST_DATA_SYNC_FIFO_ERR_SHIFT                                                   7
+  #define PSWHST_REG_INT_MASK_HST_CPL_SYNC_FIFO_ERR                                                          (0x1<<8) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_CPL_SYNC_FIFO_ERR .
+  #define PSWHST_REG_INT_MASK_HST_CPL_SYNC_FIFO_ERR_SHIFT                                                    8
+  #define PSWHST_REG_INT_MASK_HST_VF_DISABLED_ACCESS                                                         (0x1<<9) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_VF_DISABLED_ACCESS .
+  #define PSWHST_REG_INT_MASK_HST_VF_DISABLED_ACCESS_SHIFT                                                   9
+  #define PSWHST_REG_INT_MASK_HST_PERMISSION_VIOLATION                                                       (0x1<<10) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_PERMISSION_VIOLATION .
+  #define PSWHST_REG_INT_MASK_HST_PERMISSION_VIOLATION_SHIFT                                                 10
+  #define PSWHST_REG_INT_MASK_HST_INCORRECT_ACCESS                                                           (0x1<<11) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_INCORRECT_ACCESS .
+  #define PSWHST_REG_INT_MASK_HST_INCORRECT_ACCESS_SHIFT                                                     11
+  #define PSWHST_REG_INT_MASK_HST_SRC_FIFO6_ERR                                                              (0x1<<12) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO6_ERR .
+  #define PSWHST_REG_INT_MASK_HST_SRC_FIFO6_ERR_SHIFT                                                        12
+  #define PSWHST_REG_INT_MASK_HST_SRC_FIFO7_ERR                                                              (0x1<<13) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO7_ERR .
+  #define PSWHST_REG_INT_MASK_HST_SRC_FIFO7_ERR_SHIFT                                                        13
+  #define PSWHST_REG_INT_MASK_HST_SRC_FIFO8_ERR                                                              (0x1<<14) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO8_ERR .
+  #define PSWHST_REG_INT_MASK_HST_SRC_FIFO8_ERR_SHIFT                                                        14
+  #define PSWHST_REG_INT_MASK_HST_SRC_FIFO9_ERR                                                              (0x1<<15) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO9_ERR .
+  #define PSWHST_REG_INT_MASK_HST_SRC_FIFO9_ERR_SHIFT                                                        15
+  #define PSWHST_REG_INT_MASK_HST_SOURCE_CREDIT_VIOLATION                                                    (0x1<<16) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SOURCE_CREDIT_VIOLATION .
+  #define PSWHST_REG_INT_MASK_HST_SOURCE_CREDIT_VIOLATION_SHIFT                                              16
+  #define PSWHST_REG_INT_MASK_HST_TIMEOUT                                                                    (0x1<<17) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_TIMEOUT .
+  #define PSWHST_REG_INT_MASK_HST_TIMEOUT_SHIFT                                                              17
+#define PSWHST_REG_INT_STS_WR                                                                                0x2a0188UL //Access:WR   DataWidth:0x12   // Multi Field Register.
+  #define PSWHST_REG_INT_STS_WR_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSWHST_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                          0
+  #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO1_ERR                                                            (0x1<<1) // An error in write source FIFO 1.
+  #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO1_ERR_SHIFT                                                      1
+  #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO2_ERR                                                            (0x1<<2) // An error in write source FIFO 2.
+  #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO2_ERR_SHIFT                                                      2
+  #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO3_ERR                                                            (0x1<<3) // An error in write source FIFO 3.
+  #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO3_ERR_SHIFT                                                      3
+  #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO4_ERR                                                            (0x1<<4) // An error in write source FIFO 4.
+  #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO4_ERR_SHIFT                                                      4
+  #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO5_ERR                                                            (0x1<<5) // An error in write source FIFO 5.
+  #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO5_ERR_SHIFT                                                      5
+  #define PSWHST_REG_INT_STS_WR_HST_HDR_SYNC_FIFO_ERR                                                        (0x1<<6) // An error in header clock sync FIFO.
+  #define PSWHST_REG_INT_STS_WR_HST_HDR_SYNC_FIFO_ERR_SHIFT                                                  6
+  #define PSWHST_REG_INT_STS_WR_HST_DATA_SYNC_FIFO_ERR                                                       (0x1<<7) // An error in data clock sync FIFO.
+  #define PSWHST_REG_INT_STS_WR_HST_DATA_SYNC_FIFO_ERR_SHIFT                                                 7
+  #define PSWHST_REG_INT_STS_WR_HST_CPL_SYNC_FIFO_ERR                                                        (0x1<<8) // An error in completion clock sync FIFO.
+  #define PSWHST_REG_INT_STS_WR_HST_CPL_SYNC_FIFO_ERR_SHIFT                                                  8
+  #define PSWHST_REG_INT_STS_WR_HST_VF_DISABLED_ACCESS                                                       (0x1<<9) // Indicates there was an access to a disabled VF when client is not IGU or ATC (so access is dropped). The disabled vf registers are valid when it is set and reset when the interrupt clr is read.
+  #define PSWHST_REG_INT_STS_WR_HST_VF_DISABLED_ACCESS_SHIFT                                                 9
+  #define PSWHST_REG_INT_STS_WR_HST_PERMISSION_VIOLATION                                                     (0x1<<10) // Indicates Zone permission violation.  The relevant data is stored in hst_per_violation_data.
+  #define PSWHST_REG_INT_STS_WR_HST_PERMISSION_VIOLATION_SHIFT                                               10
+  #define PSWHST_REG_INT_STS_WR_HST_INCORRECT_ACCESS                                                         (0x1<<11) // Indicates there was an access to any of the clients  with incorrect length and alignement. Details are logged in incorrect access registers. The incorrect access registers are valid when it is set and reset when the interrupt clr is read.
+  #define PSWHST_REG_INT_STS_WR_HST_INCORRECT_ACCESS_SHIFT                                                   11
+  #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO6_ERR                                                            (0x1<<12) // An error in write source FIFO 6.
+  #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO6_ERR_SHIFT                                                      12
+  #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO7_ERR                                                            (0x1<<13) // An error in write source FIFO 7.
+  #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO7_ERR_SHIFT                                                      13
+  #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO8_ERR                                                            (0x1<<14) // An error in write source FIFO 8.
+  #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO8_ERR_SHIFT                                                      14
+  #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO9_ERR                                                            (0x1<<15) // An error in write source FIFO 9 (PBF).
+  #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO9_ERR_SHIFT                                                      15
+  #define PSWHST_REG_INT_STS_WR_HST_SOURCE_CREDIT_VIOLATION                                                  (0x1<<16) // Indicates an internal write source credit violation.  The relevant data is stored in hst_source_credit_viol_data.
+  #define PSWHST_REG_INT_STS_WR_HST_SOURCE_CREDIT_VIOLATION_SHIFT                                            16
+  #define PSWHST_REG_INT_STS_WR_HST_TIMEOUT                                                                  (0x1<<17) // Indicates hst_timeout occurred.
+  #define PSWHST_REG_INT_STS_WR_HST_TIMEOUT_SHIFT                                                            17
+#define PSWHST_REG_INT_STS_CLR                                                                               0x2a018cUL //Access:RC   DataWidth:0x12   // Multi Field Register.
+  #define PSWHST_REG_INT_STS_CLR_ADDRESS_ERROR                                                               (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSWHST_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                         0
+  #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO1_ERR                                                           (0x1<<1) // An error in write source FIFO 1.
+  #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO1_ERR_SHIFT                                                     1
+  #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO2_ERR                                                           (0x1<<2) // An error in write source FIFO 2.
+  #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO2_ERR_SHIFT                                                     2
+  #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO3_ERR                                                           (0x1<<3) // An error in write source FIFO 3.
+  #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO3_ERR_SHIFT                                                     3
+  #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO4_ERR                                                           (0x1<<4) // An error in write source FIFO 4.
+  #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO4_ERR_SHIFT                                                     4
+  #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO5_ERR                                                           (0x1<<5) // An error in write source FIFO 5.
+  #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO5_ERR_SHIFT                                                     5
+  #define PSWHST_REG_INT_STS_CLR_HST_HDR_SYNC_FIFO_ERR                                                       (0x1<<6) // An error in header clock sync FIFO.
+  #define PSWHST_REG_INT_STS_CLR_HST_HDR_SYNC_FIFO_ERR_SHIFT                                                 6
+  #define PSWHST_REG_INT_STS_CLR_HST_DATA_SYNC_FIFO_ERR                                                      (0x1<<7) // An error in data clock sync FIFO.
+  #define PSWHST_REG_INT_STS_CLR_HST_DATA_SYNC_FIFO_ERR_SHIFT                                                7
+  #define PSWHST_REG_INT_STS_CLR_HST_CPL_SYNC_FIFO_ERR                                                       (0x1<<8) // An error in completion clock sync FIFO.
+  #define PSWHST_REG_INT_STS_CLR_HST_CPL_SYNC_FIFO_ERR_SHIFT                                                 8
+  #define PSWHST_REG_INT_STS_CLR_HST_VF_DISABLED_ACCESS                                                      (0x1<<9) // Indicates there was an access to a disabled VF when client is not IGU or ATC (so access is dropped). The disabled vf registers are valid when it is set and reset when the interrupt clr is read.
+  #define PSWHST_REG_INT_STS_CLR_HST_VF_DISABLED_ACCESS_SHIFT                                                9
+  #define PSWHST_REG_INT_STS_CLR_HST_PERMISSION_VIOLATION                                                    (0x1<<10) // Indicates Zone permission violation.  The relevant data is stored in hst_per_violation_data.
+  #define PSWHST_REG_INT_STS_CLR_HST_PERMISSION_VIOLATION_SHIFT                                              10
+  #define PSWHST_REG_INT_STS_CLR_HST_INCORRECT_ACCESS                                                        (0x1<<11) // Indicates there was an access to any of the clients  with incorrect length and alignement. Details are logged in incorrect access registers. The incorrect access registers are valid when it is set and reset when the interrupt clr is read.
+  #define PSWHST_REG_INT_STS_CLR_HST_INCORRECT_ACCESS_SHIFT                                                  11
+  #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO6_ERR                                                           (0x1<<12) // An error in write source FIFO 6.
+  #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO6_ERR_SHIFT                                                     12
+  #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO7_ERR                                                           (0x1<<13) // An error in write source FIFO 7.
+  #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO7_ERR_SHIFT                                                     13
+  #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO8_ERR                                                           (0x1<<14) // An error in write source FIFO 8.
+  #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO8_ERR_SHIFT                                                     14
+  #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO9_ERR                                                           (0x1<<15) // An error in write source FIFO 9 (PBF).
+  #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO9_ERR_SHIFT                                                     15
+  #define PSWHST_REG_INT_STS_CLR_HST_SOURCE_CREDIT_VIOLATION                                                 (0x1<<16) // Indicates an internal write source credit violation.  The relevant data is stored in hst_source_credit_viol_data.
+  #define PSWHST_REG_INT_STS_CLR_HST_SOURCE_CREDIT_VIOLATION_SHIFT                                           16
+  #define PSWHST_REG_INT_STS_CLR_HST_TIMEOUT                                                                 (0x1<<17) // Indicates hst_timeout occurred.
+  #define PSWHST_REG_INT_STS_CLR_HST_TIMEOUT_SHIFT                                                           17
+#define PSWHST_REG_PRTY_MASK                                                                                 0x2a0194UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define PSWHST_REG_PRTY_MASK_DATAPATH_REGISTERS                                                            (0x1<<0) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS.DATAPATH_REGISTERS .
+  #define PSWHST_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                                      0
+#define PSWHST_REG_PRTY_MASK_H_0_BB_K2                                                                       0x2a0204UL //Access:RW   DataWidth:0x11   // Multi Field Register.
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2                                                   (0x1<<0) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2_SHIFT                                             0
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2                                                   (0x1<<1) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2_SHIFT                                             1
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2                                                   (0x1<<2) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT                                             2
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                   (0x1<<3) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                             3
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                   (0x1<<4) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                             4
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                   (0x1<<5) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                             5
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2                                                   (0x1<<6) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2_SHIFT                                             6
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                   (0x1<<7) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                             7
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2                                                   (0x1<<8) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2_SHIFT                                             8
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2                                                   (0x1<<9) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2_SHIFT                                             9
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_K2                                                   (0x1<<10) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_K2_SHIFT                                             10
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_K2                                                   (0x1<<11) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_K2_SHIFT                                             11
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_K2                                                   (0x1<<12) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_K2_SHIFT                                             12
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_K2                                                   (0x1<<13) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_K2_SHIFT                                             13
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_K2                                                   (0x1<<14) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_K2_SHIFT                                             14
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_K2                                                   (0x1<<15) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_K2_SHIFT                                             15
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_K2                                                   (0x1<<16) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
+  #define PSWHST_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_K2_SHIFT                                             16
+#define PSWHST_REG_MEM_ECC_EVENTS_BB_K2                                                                      0x2a0210UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define PSWHST_REG_INBOUND_INT                                                                               0x2a0400UL //Access:RW   DataWidth:0x20   // Used for initialization of the inbound interrupts memory. E4 entry structure: [15:0] - CompParams. [23:16] - EventID. [24] - T. [28:25] - Trig.
+#define PSWHST_REG_INBOUND_INT_SIZE                                                                          72
+#define PSWHST_REG_ZONE_PERMISSION_TABLE                                                                     0x2a0800UL //Access:RW   DataWidth:0x9    // Indirect access to the permission table. The fields are : {Valid; VFID[7:0]}.
+#define PSWHST_REG_ZONE_PERMISSION_TABLE_SIZE_BB                                                             256
+#define PSWHST_REG_ZONE_PERMISSION_TABLE_SIZE_K2                                                             320
+#define PSWHST_REG_ZONE_PERMISSION_TABLE_SIZE_E5                                                             256
+#define PGLUE_B_REG_START_INIT_INB_INT_MEM                                                                   0x2a8000UL //Access:W    DataWidth:0x1    // Writing 1 to this register signals the PGLUE block to start initializing inbound interrupt memories for PF zone B. Memories are initialized such that all interrupts are disabled: start_address = 1; end_address = 0.
+#define PGLUE_B_REG_INIT_DONE_INB_INT_MEM                                                                    0x2a8004UL //Access:R    DataWidth:0x2    // Initializing inbound interrupt memories for PF zone B is done. Driver should make sure the corresponding bit is 1 some time after writing to start_init_inb_int_mem. Bit 0 is for path 0 and bit 1 is for path 1.
+#define PGLUE_B_REG_START_INIT_PTT_GTT                                                                       0x2a8008UL //Access:W    DataWidth:0x1    // Writing 1 to this register signals the PGLUE block to start initializing PTT and GTT. Offsets should map to reserved space, pretend should map to the same PF. This register should be initialized by MCP.
+#define PGLUE_B_REG_INIT_DONE_PTT_GTT                                                                        0x2a800cUL //Access:R    DataWidth:0x1    // PTT and GTT initialization is done. MCP should make sure this bit is 1 some time after writing to start_init_ptt_gtt.
+#define PGLUE_B_REG_START_INIT_ZONE_A                                                                        0x2a8010UL //Access:W    DataWidth:0x1    // Writing 1 to this register signals the PGLUE block to start calculating the start address of each SDM zone A in VF BAR according to the sdm_queue_zone_size configurations.
+#define PGLUE_B_REG_INIT_DONE_ZONE_A                                                                         0x2a8014UL //Access:R    DataWidth:0x2    // Calculation of SDMs zone A start address in VF BAR  is done. Driver should make sure the corresponding bit is 1 some time after writing to start_init_zone_a. Bit 0 is for path 0 and bit 1 is for path 1.
+#define PGLUE_B_REG_INT_STS                                                                                  0x2a8180UL //Access:R    DataWidth:0x18   // Multi Field Register.
+  #define PGLUE_B_REG_INT_STS_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define PGLUE_B_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                            0
+  #define PGLUE_B_REG_INT_STS_INCORRECT_RCV_BEHAVIOR                                                         (0x1<<1) // Target RW or completion not according to PCIe core spec. See incorrect_rcv_details.
+  #define PGLUE_B_REG_INT_STS_INCORRECT_RCV_BEHAVIOR_SHIFT                                                   1
+  #define PGLUE_B_REG_INT_STS_WAS_ERROR_ATTN                                                                 (0x1<<2) // Indicates a memory read completion was received with an uncorrectable error. Was_error dirty bits provide the function on which the completion was received.
+  #define PGLUE_B_REG_INT_STS_WAS_ERROR_ATTN_SHIFT                                                           2
+  #define PGLUE_B_REG_INT_STS_VF_LENGTH_VIOLATION_ATTN                                                       (0x1<<3) // Indicates a  VF BAR0 length violation: length of more than 2DWs; length of 2DWs and address not QW aligned; window is GRC and length is more than 1 DW. Details are stored in vf_length_violation_details register.
+  #define PGLUE_B_REG_INT_STS_VF_LENGTH_VIOLATION_ATTN_SHIFT                                                 3
+  #define PGLUE_B_REG_INT_STS_VF_GRC_SPACE_VIOLATION_ATTN                                                    (0x1<<4) // Indicates target VF request accessing VF GRC space that failed permission check. Permission checks are: function permission; RW permission; address range permission. Details are stored in vf_grc_space_violation_details register.
+  #define PGLUE_B_REG_INT_STS_VF_GRC_SPACE_VIOLATION_ATTN_SHIFT                                              4
+  #define PGLUE_B_REG_INT_STS_TCPL_ERROR_ATTN                                                                (0x1<<5) // Indicates an ATS translation completion was received with an uncorrectable error.
+  #define PGLUE_B_REG_INT_STS_TCPL_ERROR_ATTN_SHIFT                                                          5
+  #define PGLUE_B_REG_INT_STS_TCPL_IN_TWO_RCBS_ATTN                                                          (0x1<<6) // Indicates ATS Translation Completion received in two rcbs (packets). Details are stored in tcpl_in_two_rcbs_details register.
+  #define PGLUE_B_REG_INT_STS_TCPL_IN_TWO_RCBS_ATTN_SHIFT                                                    6
+  #define PGLUE_B_REG_INT_STS_CSSNOOP_FIFO_OVERFLOW                                                          (0x1<<7) // Indicates an overflow in CSSNOOP sync fifo.
+  #define PGLUE_B_REG_INT_STS_CSSNOOP_FIFO_OVERFLOW_SHIFT                                                    7
+  #define PGLUE_B_REG_INT_STS_TCPL_TRANSLATION_SIZE_DIFFERENT                                                (0x1<<8) // Indicates a function received a Translation Completion with a Translation Size field different than the Function programmed STU value. Note that the disable_tcpl_translation_size_check configuration does not affect this interrupt.
+  #define PGLUE_B_REG_INT_STS_TCPL_TRANSLATION_SIZE_DIFFERENT_SHIFT                                          8
+  #define PGLUE_B_REG_INT_STS_PCIE_RX_L0S_TIMEOUT                                                            (0x1<<9) // A PCIe IP debug signal indicating a failure to exit Rx_L0s correctly.  If this occurs "too frequently", this means that the N_FTS is too low and needs to be adjusted.
+  #define PGLUE_B_REG_INT_STS_PCIE_RX_L0S_TIMEOUT_SHIFT                                                      9
+  #define PGLUE_B_REG_INT_STS_MASTER_ZLR_ATTN                                                                (0x1<<10) // Indicates a zero length read arrived from PSWRQ. Should not normally happen, but might happen with physical device assignement flow.
+  #define PGLUE_B_REG_INT_STS_MASTER_ZLR_ATTN_SHIFT                                                          10
+  #define PGLUE_B_REG_INT_STS_ADMIN_WINDOW_VIOLATION_ATTN                                                    (0x1<<11) // Indicates Read/Write accesses to the admin window that have a length bigger than 1DW or first byte enable != 0xf.
+  #define PGLUE_B_REG_INT_STS_ADMIN_WINDOW_VIOLATION_ATTN_SHIFT                                              11
+  #define PGLUE_B_REG_INT_STS_OUT_OF_RANGE_FUNCTION_IN_PRETEND                                               (0x1<<12) // Indicates Target R/W where pretend register contains an out of range function. Relevant when number of PFs or VFs is not a power of two. In E4, it indicates VFID bigger than 95.
+  #define PGLUE_B_REG_INT_STS_OUT_OF_RANGE_FUNCTION_IN_PRETEND_SHIFT                                         12
+  #define PGLUE_B_REG_INT_STS_ILLEGAL_ADDRESS                                                                (0x1<<13) // Indicates an illegal address event - address smaller than minimal_address_log or bigger than maximal_address_log. Details are stored in illegal_address_add and illegal_address_details registers.
+  #define PGLUE_B_REG_INT_STS_ILLEGAL_ADDRESS_SHIFT                                                          13
+  #define PGLUE_B_REG_INT_STS_PGL_CPL_ERR                                                                    (0x1<<14) // Completion error received from core.
+  #define PGLUE_B_REG_INT_STS_PGL_CPL_ERR_SHIFT                                                              14
+  #define PGLUE_B_REG_INT_STS_PGL_TXW_OF                                                                     (0x1<<15) // Overflow of tx write queue.
+  #define PGLUE_B_REG_INT_STS_PGL_TXW_OF_SHIFT                                                               15
+  #define PGLUE_B_REG_INT_STS_PGL_CPL_AFT                                                                    (0x1<<16) // Overflow of cpl queue.
+  #define PGLUE_B_REG_INT_STS_PGL_CPL_AFT_SHIFT                                                              16
+  #define PGLUE_B_REG_INT_STS_PGL_CPL_OF                                                                     (0x1<<17) // Overflow error on completion or target write.
+  #define PGLUE_B_REG_INT_STS_PGL_CPL_OF_SHIFT                                                               17
+  #define PGLUE_B_REG_INT_STS_PGL_CPL_ECRC                                                                   (0x1<<18) // Ecrc error on completion or target write.
+  #define PGLUE_B_REG_INT_STS_PGL_CPL_ECRC_SHIFT                                                             18
+  #define PGLUE_B_REG_INT_STS_PGL_PCIE_ATTN                                                                  (0x1<<19) // Pcie core raised an attention.
+  #define PGLUE_B_REG_INT_STS_PGL_PCIE_ATTN_SHIFT                                                            19
+  #define PGLUE_B_REG_INT_STS_PGL_READ_BLOCKED                                                               (0x1<<20) // Read was blocked due to master_en.
+  #define PGLUE_B_REG_INT_STS_PGL_READ_BLOCKED_SHIFT                                                         20
+  #define PGLUE_B_REG_INT_STS_PGL_WRITE_BLOCKED                                                              (0x1<<21) // Write was blocked due to master_en.
+  #define PGLUE_B_REG_INT_STS_PGL_WRITE_BLOCKED_SHIFT                                                        21
+  #define PGLUE_B_REG_INT_STS_VF_ILT_ERR                                                                     (0x1<<22) // Indicates a request received with VF ILT error indication from PSWRQ. The request was dropped. Details are stored in vf_ilt_err_add and vf_ilt_err_details registers.
+  #define PGLUE_B_REG_INT_STS_VF_ILT_ERR_SHIFT                                                               22
+  #define PGLUE_B_REG_INT_STS_RXOBFFEXCEPTION_ATTN_K2_E5                                                     (0x1<<23) // Indicate rxobffexception_attn is asseted
+  #define PGLUE_B_REG_INT_STS_RXOBFFEXCEPTION_ATTN_K2_E5_SHIFT                                               23
+#define PGLUE_B_REG_INT_MASK                                                                                 0x2a8184UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define PGLUE_B_REG_INT_MASK_ADDRESS_ERROR                                                                 (0x1<<0) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.ADDRESS_ERROR .
+  #define PGLUE_B_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                           0
+  #define PGLUE_B_REG_INT_MASK_INCORRECT_RCV_BEHAVIOR                                                        (0x1<<1) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.INCORRECT_RCV_BEHAVIOR .
+  #define PGLUE_B_REG_INT_MASK_INCORRECT_RCV_BEHAVIOR_SHIFT                                                  1
+  #define PGLUE_B_REG_INT_MASK_WAS_ERROR_ATTN                                                                (0x1<<2) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.WAS_ERROR_ATTN .
+  #define PGLUE_B_REG_INT_MASK_WAS_ERROR_ATTN_SHIFT                                                          2
+  #define PGLUE_B_REG_INT_MASK_VF_LENGTH_VIOLATION_ATTN                                                      (0x1<<3) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.VF_LENGTH_VIOLATION_ATTN .
+  #define PGLUE_B_REG_INT_MASK_VF_LENGTH_VIOLATION_ATTN_SHIFT                                                3
+  #define PGLUE_B_REG_INT_MASK_VF_GRC_SPACE_VIOLATION_ATTN                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.VF_GRC_SPACE_VIOLATION_ATTN .
+  #define PGLUE_B_REG_INT_MASK_VF_GRC_SPACE_VIOLATION_ATTN_SHIFT                                             4
+  #define PGLUE_B_REG_INT_MASK_TCPL_ERROR_ATTN                                                               (0x1<<5) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.TCPL_ERROR_ATTN .
+  #define PGLUE_B_REG_INT_MASK_TCPL_ERROR_ATTN_SHIFT                                                         5
+  #define PGLUE_B_REG_INT_MASK_TCPL_IN_TWO_RCBS_ATTN                                                         (0x1<<6) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.TCPL_IN_TWO_RCBS_ATTN .
+  #define PGLUE_B_REG_INT_MASK_TCPL_IN_TWO_RCBS_ATTN_SHIFT                                                   6
+  #define PGLUE_B_REG_INT_MASK_CSSNOOP_FIFO_OVERFLOW                                                         (0x1<<7) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.CSSNOOP_FIFO_OVERFLOW .
+  #define PGLUE_B_REG_INT_MASK_CSSNOOP_FIFO_OVERFLOW_SHIFT                                                   7
+  #define PGLUE_B_REG_INT_MASK_TCPL_TRANSLATION_SIZE_DIFFERENT                                               (0x1<<8) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.TCPL_TRANSLATION_SIZE_DIFFERENT .
+  #define PGLUE_B_REG_INT_MASK_TCPL_TRANSLATION_SIZE_DIFFERENT_SHIFT                                         8
+  #define PGLUE_B_REG_INT_MASK_PCIE_RX_L0S_TIMEOUT                                                           (0x1<<9) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PCIE_RX_L0S_TIMEOUT .
+  #define PGLUE_B_REG_INT_MASK_PCIE_RX_L0S_TIMEOUT_SHIFT                                                     9
+  #define PGLUE_B_REG_INT_MASK_MASTER_ZLR_ATTN                                                               (0x1<<10) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.MASTER_ZLR_ATTN .
+  #define PGLUE_B_REG_INT_MASK_MASTER_ZLR_ATTN_SHIFT                                                         10
+  #define PGLUE_B_REG_INT_MASK_ADMIN_WINDOW_VIOLATION_ATTN                                                   (0x1<<11) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.ADMIN_WINDOW_VIOLATION_ATTN .
+  #define PGLUE_B_REG_INT_MASK_ADMIN_WINDOW_VIOLATION_ATTN_SHIFT                                             11
+  #define PGLUE_B_REG_INT_MASK_OUT_OF_RANGE_FUNCTION_IN_PRETEND                                              (0x1<<12) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.OUT_OF_RANGE_FUNCTION_IN_PRETEND .
+  #define PGLUE_B_REG_INT_MASK_OUT_OF_RANGE_FUNCTION_IN_PRETEND_SHIFT                                        12
+  #define PGLUE_B_REG_INT_MASK_ILLEGAL_ADDRESS                                                               (0x1<<13) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.ILLEGAL_ADDRESS .
+  #define PGLUE_B_REG_INT_MASK_ILLEGAL_ADDRESS_SHIFT                                                         13
+  #define PGLUE_B_REG_INT_MASK_PGL_CPL_ERR                                                                   (0x1<<14) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PGL_CPL_ERR .
+  #define PGLUE_B_REG_INT_MASK_PGL_CPL_ERR_SHIFT                                                             14
+  #define PGLUE_B_REG_INT_MASK_PGL_TXW_OF                                                                    (0x1<<15) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PGL_TXW_OF .
+  #define PGLUE_B_REG_INT_MASK_PGL_TXW_OF_SHIFT                                                              15
+  #define PGLUE_B_REG_INT_MASK_PGL_CPL_AFT                                                                   (0x1<<16) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PGL_CPL_AFT .
+  #define PGLUE_B_REG_INT_MASK_PGL_CPL_AFT_SHIFT                                                             16
+  #define PGLUE_B_REG_INT_MASK_PGL_CPL_OF                                                                    (0x1<<17) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PGL_CPL_OF .
+  #define PGLUE_B_REG_INT_MASK_PGL_CPL_OF_SHIFT                                                              17
+  #define PGLUE_B_REG_INT_MASK_PGL_CPL_ECRC                                                                  (0x1<<18) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PGL_CPL_ECRC .
+  #define PGLUE_B_REG_INT_MASK_PGL_CPL_ECRC_SHIFT                                                            18
+  #define PGLUE_B_REG_INT_MASK_PGL_PCIE_ATTN                                                                 (0x1<<19) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PGL_PCIE_ATTN .
+  #define PGLUE_B_REG_INT_MASK_PGL_PCIE_ATTN_SHIFT                                                           19
+  #define PGLUE_B_REG_INT_MASK_PGL_READ_BLOCKED                                                              (0x1<<20) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PGL_READ_BLOCKED .
+  #define PGLUE_B_REG_INT_MASK_PGL_READ_BLOCKED_SHIFT                                                        20
+  #define PGLUE_B_REG_INT_MASK_PGL_WRITE_BLOCKED                                                             (0x1<<21) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PGL_WRITE_BLOCKED .
+  #define PGLUE_B_REG_INT_MASK_PGL_WRITE_BLOCKED_SHIFT                                                       21
+  #define PGLUE_B_REG_INT_MASK_VF_ILT_ERR                                                                    (0x1<<22) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.VF_ILT_ERR .
+  #define PGLUE_B_REG_INT_MASK_VF_ILT_ERR_SHIFT                                                              22
+  #define PGLUE_B_REG_INT_MASK_RXOBFFEXCEPTION_ATTN_K2_E5                                                    (0x1<<23) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.RXOBFFEXCEPTION_ATTN .
+  #define PGLUE_B_REG_INT_MASK_RXOBFFEXCEPTION_ATTN_K2_E5_SHIFT                                              23
+#define PGLUE_B_REG_INT_STS_WR                                                                               0x2a8188UL //Access:WR   DataWidth:0x18   // Multi Field Register.
+  #define PGLUE_B_REG_INT_STS_WR_ADDRESS_ERROR                                                               (0x1<<0) // Signals an unknown address to the rf module.
+  #define PGLUE_B_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                         0
+  #define PGLUE_B_REG_INT_STS_WR_INCORRECT_RCV_BEHAVIOR                                                      (0x1<<1) // Target RW or completion not according to PCIe core spec. See incorrect_rcv_details.
+  #define PGLUE_B_REG_INT_STS_WR_INCORRECT_RCV_BEHAVIOR_SHIFT                                                1
+  #define PGLUE_B_REG_INT_STS_WR_WAS_ERROR_ATTN                                                              (0x1<<2) // Indicates a memory read completion was received with an uncorrectable error. Was_error dirty bits provide the function on which the completion was received.
+  #define PGLUE_B_REG_INT_STS_WR_WAS_ERROR_ATTN_SHIFT                                                        2
+  #define PGLUE_B_REG_INT_STS_WR_VF_LENGTH_VIOLATION_ATTN                                                    (0x1<<3) // Indicates a  VF BAR0 length violation: length of more than 2DWs; length of 2DWs and address not QW aligned; window is GRC and length is more than 1 DW. Details are stored in vf_length_violation_details register.
+  #define PGLUE_B_REG_INT_STS_WR_VF_LENGTH_VIOLATION_ATTN_SHIFT                                              3
+  #define PGLUE_B_REG_INT_STS_WR_VF_GRC_SPACE_VIOLATION_ATTN                                                 (0x1<<4) // Indicates target VF request accessing VF GRC space that failed permission check. Permission checks are: function permission; RW permission; address range permission. Details are stored in vf_grc_space_violation_details register.
+  #define PGLUE_B_REG_INT_STS_WR_VF_GRC_SPACE_VIOLATION_ATTN_SHIFT                                           4
+  #define PGLUE_B_REG_INT_STS_WR_TCPL_ERROR_ATTN                                                             (0x1<<5) // Indicates an ATS translation completion was received with an uncorrectable error.
+  #define PGLUE_B_REG_INT_STS_WR_TCPL_ERROR_ATTN_SHIFT                                                       5
+  #define PGLUE_B_REG_INT_STS_WR_TCPL_IN_TWO_RCBS_ATTN                                                       (0x1<<6) // Indicates ATS Translation Completion received in two rcbs (packets). Details are stored in tcpl_in_two_rcbs_details register.
+  #define PGLUE_B_REG_INT_STS_WR_TCPL_IN_TWO_RCBS_ATTN_SHIFT                                                 6
+  #define PGLUE_B_REG_INT_STS_WR_CSSNOOP_FIFO_OVERFLOW                                                       (0x1<<7) // Indicates an overflow in CSSNOOP sync fifo.
+  #define PGLUE_B_REG_INT_STS_WR_CSSNOOP_FIFO_OVERFLOW_SHIFT                                                 7
+  #define PGLUE_B_REG_INT_STS_WR_TCPL_TRANSLATION_SIZE_DIFFERENT                                             (0x1<<8) // Indicates a function received a Translation Completion with a Translation Size field different than the Function programmed STU value. Note that the disable_tcpl_translation_size_check configuration does not affect this interrupt.
+  #define PGLUE_B_REG_INT_STS_WR_TCPL_TRANSLATION_SIZE_DIFFERENT_SHIFT                                       8
+  #define PGLUE_B_REG_INT_STS_WR_PCIE_RX_L0S_TIMEOUT                                                         (0x1<<9) // A PCIe IP debug signal indicating a failure to exit Rx_L0s correctly.  If this occurs "too frequently", this means that the N_FTS is too low and needs to be adjusted.
+  #define PGLUE_B_REG_INT_STS_WR_PCIE_RX_L0S_TIMEOUT_SHIFT                                                   9
+  #define PGLUE_B_REG_INT_STS_WR_MASTER_ZLR_ATTN                                                             (0x1<<10) // Indicates a zero length read arrived from PSWRQ. Should not normally happen, but might happen with physical device assignement flow.
+  #define PGLUE_B_REG_INT_STS_WR_MASTER_ZLR_ATTN_SHIFT                                                       10
+  #define PGLUE_B_REG_INT_STS_WR_ADMIN_WINDOW_VIOLATION_ATTN                                                 (0x1<<11) // Indicates Read/Write accesses to the admin window that have a length bigger than 1DW or first byte enable != 0xf.
+  #define PGLUE_B_REG_INT_STS_WR_ADMIN_WINDOW_VIOLATION_ATTN_SHIFT                                           11
+  #define PGLUE_B_REG_INT_STS_WR_OUT_OF_RANGE_FUNCTION_IN_PRETEND                                            (0x1<<12) // Indicates Target R/W where pretend register contains an out of range function. Relevant when number of PFs or VFs is not a power of two. In E4, it indicates VFID bigger than 95.
+  #define PGLUE_B_REG_INT_STS_WR_OUT_OF_RANGE_FUNCTION_IN_PRETEND_SHIFT                                      12
+  #define PGLUE_B_REG_INT_STS_WR_ILLEGAL_ADDRESS                                                             (0x1<<13) // Indicates an illegal address event - address smaller than minimal_address_log or bigger than maximal_address_log. Details are stored in illegal_address_add and illegal_address_details registers.
+  #define PGLUE_B_REG_INT_STS_WR_ILLEGAL_ADDRESS_SHIFT                                                       13
+  #define PGLUE_B_REG_INT_STS_WR_PGL_CPL_ERR                                                                 (0x1<<14) // Completion error received from core.
+  #define PGLUE_B_REG_INT_STS_WR_PGL_CPL_ERR_SHIFT                                                           14
+  #define PGLUE_B_REG_INT_STS_WR_PGL_TXW_OF                                                                  (0x1<<15) // Overflow of tx write queue.
+  #define PGLUE_B_REG_INT_STS_WR_PGL_TXW_OF_SHIFT                                                            15
+  #define PGLUE_B_REG_INT_STS_WR_PGL_CPL_AFT                                                                 (0x1<<16) // Overflow of cpl queue.
+  #define PGLUE_B_REG_INT_STS_WR_PGL_CPL_AFT_SHIFT                                                           16
+  #define PGLUE_B_REG_INT_STS_WR_PGL_CPL_OF                                                                  (0x1<<17) // Overflow error on completion or target write.
+  #define PGLUE_B_REG_INT_STS_WR_PGL_CPL_OF_SHIFT                                                            17
+  #define PGLUE_B_REG_INT_STS_WR_PGL_CPL_ECRC                                                                (0x1<<18) // Ecrc error on completion or target write.
+  #define PGLUE_B_REG_INT_STS_WR_PGL_CPL_ECRC_SHIFT                                                          18
+  #define PGLUE_B_REG_INT_STS_WR_PGL_PCIE_ATTN                                                               (0x1<<19) // Pcie core raised an attention.
+  #define PGLUE_B_REG_INT_STS_WR_PGL_PCIE_ATTN_SHIFT                                                         19
+  #define PGLUE_B_REG_INT_STS_WR_PGL_READ_BLOCKED                                                            (0x1<<20) // Read was blocked due to master_en.
+  #define PGLUE_B_REG_INT_STS_WR_PGL_READ_BLOCKED_SHIFT                                                      20
+  #define PGLUE_B_REG_INT_STS_WR_PGL_WRITE_BLOCKED                                                           (0x1<<21) // Write was blocked due to master_en.
+  #define PGLUE_B_REG_INT_STS_WR_PGL_WRITE_BLOCKED_SHIFT                                                     21
+  #define PGLUE_B_REG_INT_STS_WR_VF_ILT_ERR                                                                  (0x1<<22) // Indicates a request received with VF ILT error indication from PSWRQ. The request was dropped. Details are stored in vf_ilt_err_add and vf_ilt_err_details registers.
+  #define PGLUE_B_REG_INT_STS_WR_VF_ILT_ERR_SHIFT                                                            22
+  #define PGLUE_B_REG_INT_STS_WR_RXOBFFEXCEPTION_ATTN_K2_E5                                                  (0x1<<23) // Indicate rxobffexception_attn is asseted
+  #define PGLUE_B_REG_INT_STS_WR_RXOBFFEXCEPTION_ATTN_K2_E5_SHIFT                                            23
+#define PGLUE_B_REG_INT_STS_CLR                                                                              0x2a818cUL //Access:RC   DataWidth:0x18   // Multi Field Register.
+  #define PGLUE_B_REG_INT_STS_CLR_ADDRESS_ERROR                                                              (0x1<<0) // Signals an unknown address to the rf module.
+  #define PGLUE_B_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                        0
+  #define PGLUE_B_REG_INT_STS_CLR_INCORRECT_RCV_BEHAVIOR                                                     (0x1<<1) // Target RW or completion not according to PCIe core spec. See incorrect_rcv_details.
+  #define PGLUE_B_REG_INT_STS_CLR_INCORRECT_RCV_BEHAVIOR_SHIFT                                               1
+  #define PGLUE_B_REG_INT_STS_CLR_WAS_ERROR_ATTN                                                             (0x1<<2) // Indicates a memory read completion was received with an uncorrectable error. Was_error dirty bits provide the function on which the completion was received.
+  #define PGLUE_B_REG_INT_STS_CLR_WAS_ERROR_ATTN_SHIFT                                                       2
+  #define PGLUE_B_REG_INT_STS_CLR_VF_LENGTH_VIOLATION_ATTN                                                   (0x1<<3) // Indicates a  VF BAR0 length violation: length of more than 2DWs; length of 2DWs and address not QW aligned; window is GRC and length is more than 1 DW. Details are stored in vf_length_violation_details register.
+  #define PGLUE_B_REG_INT_STS_CLR_VF_LENGTH_VIOLATION_ATTN_SHIFT                                             3
+  #define PGLUE_B_REG_INT_STS_CLR_VF_GRC_SPACE_VIOLATION_ATTN                                                (0x1<<4) // Indicates target VF request accessing VF GRC space that failed permission check. Permission checks are: function permission; RW permission; address range permission. Details are stored in vf_grc_space_violation_details register.
+  #define PGLUE_B_REG_INT_STS_CLR_VF_GRC_SPACE_VIOLATION_ATTN_SHIFT                                          4
+  #define PGLUE_B_REG_INT_STS_CLR_TCPL_ERROR_ATTN                                                            (0x1<<5) // Indicates an ATS translation completion was received with an uncorrectable error.
+  #define PGLUE_B_REG_INT_STS_CLR_TCPL_ERROR_ATTN_SHIFT                                                      5
+  #define PGLUE_B_REG_INT_STS_CLR_TCPL_IN_TWO_RCBS_ATTN                                                      (0x1<<6) // Indicates ATS Translation Completion received in two rcbs (packets). Details are stored in tcpl_in_two_rcbs_details register.
+  #define PGLUE_B_REG_INT_STS_CLR_TCPL_IN_TWO_RCBS_ATTN_SHIFT                                                6
+  #define PGLUE_B_REG_INT_STS_CLR_CSSNOOP_FIFO_OVERFLOW                                                      (0x1<<7) // Indicates an overflow in CSSNOOP sync fifo.
+  #define PGLUE_B_REG_INT_STS_CLR_CSSNOOP_FIFO_OVERFLOW_SHIFT                                                7
+  #define PGLUE_B_REG_INT_STS_CLR_TCPL_TRANSLATION_SIZE_DIFFERENT                                            (0x1<<8) // Indicates a function received a Translation Completion with a Translation Size field different than the Function programmed STU value. Note that the disable_tcpl_translation_size_check configuration does not affect this interrupt.
+  #define PGLUE_B_REG_INT_STS_CLR_TCPL_TRANSLATION_SIZE_DIFFERENT_SHIFT                                      8
+  #define PGLUE_B_REG_INT_STS_CLR_PCIE_RX_L0S_TIMEOUT                                                        (0x1<<9) // A PCIe IP debug signal indicating a failure to exit Rx_L0s correctly.  If this occurs "too frequently", this means that the N_FTS is too low and needs to be adjusted.
+  #define PGLUE_B_REG_INT_STS_CLR_PCIE_RX_L0S_TIMEOUT_SHIFT                                                  9
+  #define PGLUE_B_REG_INT_STS_CLR_MASTER_ZLR_ATTN                                                            (0x1<<10) // Indicates a zero length read arrived from PSWRQ. Should not normally happen, but might happen with physical device assignement flow.
+  #define PGLUE_B_REG_INT_STS_CLR_MASTER_ZLR_ATTN_SHIFT                                                      10
+  #define PGLUE_B_REG_INT_STS_CLR_ADMIN_WINDOW_VIOLATION_ATTN                                                (0x1<<11) // Indicates Read/Write accesses to the admin window that have a length bigger than 1DW or first byte enable != 0xf.
+  #define PGLUE_B_REG_INT_STS_CLR_ADMIN_WINDOW_VIOLATION_ATTN_SHIFT                                          11
+  #define PGLUE_B_REG_INT_STS_CLR_OUT_OF_RANGE_FUNCTION_IN_PRETEND                                           (0x1<<12) // Indicates Target R/W where pretend register contains an out of range function. Relevant when number of PFs or VFs is not a power of two. In E4, it indicates VFID bigger than 95.
+  #define PGLUE_B_REG_INT_STS_CLR_OUT_OF_RANGE_FUNCTION_IN_PRETEND_SHIFT                                     12
+  #define PGLUE_B_REG_INT_STS_CLR_ILLEGAL_ADDRESS                                                            (0x1<<13) // Indicates an illegal address event - address smaller than minimal_address_log or bigger than maximal_address_log. Details are stored in illegal_address_add and illegal_address_details registers.
+  #define PGLUE_B_REG_INT_STS_CLR_ILLEGAL_ADDRESS_SHIFT                                                      13
+  #define PGLUE_B_REG_INT_STS_CLR_PGL_CPL_ERR                                                                (0x1<<14) // Completion error received from core.
+  #define PGLUE_B_REG_INT_STS_CLR_PGL_CPL_ERR_SHIFT                                                          14
+  #define PGLUE_B_REG_INT_STS_CLR_PGL_TXW_OF                                                                 (0x1<<15) // Overflow of tx write queue.
+  #define PGLUE_B_REG_INT_STS_CLR_PGL_TXW_OF_SHIFT                                                           15
+  #define PGLUE_B_REG_INT_STS_CLR_PGL_CPL_AFT                                                                (0x1<<16) // Overflow of cpl queue.
+  #define PGLUE_B_REG_INT_STS_CLR_PGL_CPL_AFT_SHIFT                                                          16
+  #define PGLUE_B_REG_INT_STS_CLR_PGL_CPL_OF                                                                 (0x1<<17) // Overflow error on completion or target write.
+  #define PGLUE_B_REG_INT_STS_CLR_PGL_CPL_OF_SHIFT                                                           17
+  #define PGLUE_B_REG_INT_STS_CLR_PGL_CPL_ECRC                                                               (0x1<<18) // Ecrc error on completion or target write.
+  #define PGLUE_B_REG_INT_STS_CLR_PGL_CPL_ECRC_SHIFT                                                         18
+  #define PGLUE_B_REG_INT_STS_CLR_PGL_PCIE_ATTN                                                              (0x1<<19) // Pcie core raised an attention.
+  #define PGLUE_B_REG_INT_STS_CLR_PGL_PCIE_ATTN_SHIFT                                                        19
+  #define PGLUE_B_REG_INT_STS_CLR_PGL_READ_BLOCKED                                                           (0x1<<20) // Read was blocked due to master_en.
+  #define PGLUE_B_REG_INT_STS_CLR_PGL_READ_BLOCKED_SHIFT                                                     20
+  #define PGLUE_B_REG_INT_STS_CLR_PGL_WRITE_BLOCKED                                                          (0x1<<21) // Write was blocked due to master_en.
+  #define PGLUE_B_REG_INT_STS_CLR_PGL_WRITE_BLOCKED_SHIFT                                                    21
+  #define PGLUE_B_REG_INT_STS_CLR_VF_ILT_ERR                                                                 (0x1<<22) // Indicates a request received with VF ILT error indication from PSWRQ. The request was dropped. Details are stored in vf_ilt_err_add and vf_ilt_err_details registers.
+  #define PGLUE_B_REG_INT_STS_CLR_VF_ILT_ERR_SHIFT                                                           22
+  #define PGLUE_B_REG_INT_STS_CLR_RXOBFFEXCEPTION_ATTN_K2_E5                                                 (0x1<<23) // Indicate rxobffexception_attn is asseted
+  #define PGLUE_B_REG_INT_STS_CLR_RXOBFFEXCEPTION_ATTN_K2_E5_SHIFT                                           23
+#define PGLUE_B_REG_PRTY_MASK                                                                                0x2a8194UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define PGLUE_B_REG_PRTY_MASK_DATAPATH_REGISTERS                                                           (0x1<<0) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS.DATAPATH_REGISTERS .
+  #define PGLUE_B_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                                     0
+#define PGLUE_B_REG_PRTY_MASK_H_0_BB_K2                                                                      0x2a8204UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2                                                     (0x1<<0) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2_SHIFT                                               0
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB                                                     (0x1<<4) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_SHIFT                                               4
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2                                                     (0x1<<1) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_SHIFT                                               1
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2                                                  (0x1<<2) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2_SHIFT                                            2
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2                                                  (0x1<<3) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2_SHIFT                                            3
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB                                                     (0x1<<5) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_SHIFT                                               5
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2                                                     (0x1<<4) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_SHIFT                                               4
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_K2                                                     (0x1<<5) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_K2_SHIFT                                               5
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2                                                     (0x1<<6) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2_SHIFT                                               6
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2                                                     (0x1<<7) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2_SHIFT                                               7
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_K2                                                     (0x1<<8) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_K2_SHIFT                                               8
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB                                                     (0x1<<10) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_SHIFT                                               10
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2                                                     (0x1<<9) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_SHIFT                                               9
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB                                                     (0x1<<11) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_SHIFT                                               11
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2                                                     (0x1<<10) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2_SHIFT                                               10
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB                                                     (0x1<<6) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_SHIFT                                               6
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2                                                     (0x1<<11) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2_SHIFT                                               11
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2                                                     (0x1<<12) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2_SHIFT                                               12
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2                                                     (0x1<<13) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_SHIFT                                               13
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB                                                     (0x1<<7) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_SHIFT                                               7
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2                                                     (0x1<<14) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2_SHIFT                                               14
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB                                                     (0x1<<8) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_SHIFT                                               8
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2                                                     (0x1<<15) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2_SHIFT                                               15
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB                                                     (0x1<<9) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_SHIFT                                               9
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2                                                     (0x1<<16) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2_SHIFT                                               16
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB                                                     (0x1<<0) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_SHIFT                                               0
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2                                                     (0x1<<17) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2_SHIFT                                               17
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2                                                     (0x1<<18) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2_SHIFT                                               18
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2                                                     (0x1<<19) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2_SHIFT                                               19
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2                                                     (0x1<<20) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2_SHIFT                                               20
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2                                                     (0x1<<21) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_SHIFT                                               21
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_K2                                                     (0x1<<22) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_K2_SHIFT                                               22
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB                                                     (0x1<<1) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_SHIFT                                               1
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2                                                     (0x1<<23) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_SHIFT                                               23
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB                                                     (0x1<<12) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_SHIFT                                               12
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2                                                     (0x1<<24) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_SHIFT                                               24
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_0_BB                                                   (0x1<<13) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_0 .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_0_BB_SHIFT                                             13
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_0_K2                                                   (0x1<<25) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_0 .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_0_K2_SHIFT                                             25
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_1_BB                                                   (0x1<<14) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_1 .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_1_BB_SHIFT                                             14
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_1_K2                                                   (0x1<<26) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_1 .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_1_K2_SHIFT                                             26
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_2_BB                                                   (0x1<<15) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_2 .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_2_BB_SHIFT                                             15
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_2_K2                                                   (0x1<<27) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_2 .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_2_K2_SHIFT                                             27
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_3_BB                                                   (0x1<<16) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_3 .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_3_BB_SHIFT                                             16
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_3_K2                                                   (0x1<<28) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_3 .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_3_K2_SHIFT                                             28
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_4_BB                                                   (0x1<<17) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_4 .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_4_BB_SHIFT                                             17
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_4_K2                                                   (0x1<<29) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_4 .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_4_K2_SHIFT                                             29
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_5_BB                                                   (0x1<<18) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_5 .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_5_BB_SHIFT                                             18
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_5_K2                                                   (0x1<<30) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_5 .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_5_K2_SHIFT                                             30
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_6_BB                                                   (0x1<<19) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_6 .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_6_BB_SHIFT                                             19
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_7_BB                                                   (0x1<<20) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_7 .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_7_BB_SHIFT                                             20
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB                                                     (0x1<<21) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_SHIFT                                               21
+#define PGLUE_B_REG_PRTY_MASK_H_1_K2                                                                         0x2a8214UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define PGLUE_B_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_6_K2                                                   (0x1<<0) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY_6 .
+  #define PGLUE_B_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_6_K2_SHIFT                                             0
+  #define PGLUE_B_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_7_K2                                                   (0x1<<1) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY_7 .
+  #define PGLUE_B_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_7_K2_SHIFT                                             1
+  #define PGLUE_B_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2                                                     (0x1<<2) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
+  #define PGLUE_B_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2_SHIFT                                               2
+#define PGLUE_B_REG_MEM_ECC_EVENTS_BB                                                                        0x2a8210UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define PGLUE_B_REG_MEM_ECC_EVENTS_K2                                                                        0x2a8220UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define PGLUE_B_REG_DBG_SELECT                                                                               0x2a8400UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PGLUE_B_REG_DBG_DWORD_ENABLE                                                                         0x2a8404UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PGLUE_B_REG_DBG_SHIFT                                                                                0x2a8408UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PGLUE_B_REG_DBG_FORCE_VALID                                                                          0x2a840cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PGLUE_B_REG_DBG_FORCE_FRAME                                                                          0x2a8410UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PGLUE_B_REG_DBG_OUT_DATA                                                                             0x2a8420UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PGLUE_B_REG_DBG_OUT_DATA_SIZE                                                                        8
+#define PGLUE_B_REG_DBG_OUT_VALID                                                                            0x2a8440UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define PGLUE_B_REG_DBG_OUT_FRAME                                                                            0x2a8444UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define PGLUE_B_REG_PGL_ECO_RESERVED                                                                         0x2a8460UL //Access:RW   DataWidth:0x20   // Debug only: Reserved bits for ECO. Bit 0 - for Atomic Op / MRD handling of NPH credits. 0 - Can send both if there is one NPH credit and this may cause HOL blocking on user TX interface and theoretically cause deadlock between RC and device. 1 - Each waits for 2 NPH credits to be sent. Bit 1 - For CQ84726 - RW ordering. Should be the same as bit 2 in PGLCS eco_reserved. 0 - Add the fix. 1 - Do not add the fix.
+#define PGLUE_B_REG_PGL_ECO_RESERVED2                                                                        0x2a8464UL //Access:RW   DataWidth:0x20   // Debug only: Reserved bits for ECO.
+#define PGLUE_B_REG_DBGSYN_ALMOST_FULL_THR                                                                   0x2a8468UL //Access:RW   DataWidth:0x4    // Debug only: If more than this Number of entries are occupied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed.
+#define PGLUE_B_REG_DBGBUS_PATH_SELECT                                                                       0x2a846cUL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PGLUE_B_REG_DBGBUS_PATH_SELECT_DBGBUS_PATH_SELECT_E0                                               (0x1<<0) // 0 - Debug bus is not output to RBCN_e0. 1 - Debug bus is output to RBCN_e0.
+  #define PGLUE_B_REG_DBGBUS_PATH_SELECT_DBGBUS_PATH_SELECT_E0_SHIFT                                         0
+  #define PGLUE_B_REG_DBGBUS_PATH_SELECT_DBGBUS_PATH_SELECT_E1                                               (0x1<<1) // 0 - Debug bus is not output to RBCN_e1. 1 - Debug bus is output to RBCN_e1.
+  #define PGLUE_B_REG_DBGBUS_PATH_SELECT_DBGBUS_PATH_SELECT_E1_SHIFT                                         1
+#define PGLUE_B_REG_PGL_DEBUG                                                                                0x2a8470UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define PGLUE_B_REG_PGL_DEBUG_PGL_TXR_RELAX                                                                (0x1<<0) // Debug only.
+  #define PGLUE_B_REG_PGL_DEBUG_PGL_TXR_RELAX_SHIFT                                                          0
+  #define PGLUE_B_REG_PGL_DEBUG_PGL_TXW_RELAX                                                                (0x1<<1) // Debug only.
+  #define PGLUE_B_REG_PGL_DEBUG_PGL_TXW_RELAX_SHIFT                                                          1
+  #define PGLUE_B_REG_PGL_DEBUG_PGL_DISABLE                                                                  (0x1<<2) // Debug only.
+  #define PGLUE_B_REG_PGL_DEBUG_PGL_DISABLE_SHIFT                                                            2
+#define PGLUE_B_REG_PGL_MOT                                                                                  0x2a8474UL //Access:R    DataWidth:0x6    // Debug only.
+#define PGLUE_B_REG_PGL_CORE_DEBUG                                                                           0x2a8478UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define PGLUE_B_REG_PGL_CORE_DEBUG_SEL_1                                                                   (0xf<<0) // Pcie core debug mux select 1. this field controls the output of the debug bus of the pcie_core.
+  #define PGLUE_B_REG_PGL_CORE_DEBUG_SEL_1_SHIFT                                                             0
+  #define PGLUE_B_REG_PGL_CORE_DEBUG_SEL_2                                                                   (0xf<<4) // Pcie core debug mux select 2.
+  #define PGLUE_B_REG_PGL_CORE_DEBUG_SEL_2_SHIFT                                                             4
+  #define PGLUE_B_REG_PGL_CORE_DEBUG_PGL_PARITY_MODE                                                         (0x1<<8) // This bit forces a parity error in the replay buffer.
+  #define PGLUE_B_REG_PGL_CORE_DEBUG_PGL_PARITY_MODE_SHIFT                                                   8
+  #define PGLUE_B_REG_PGL_CORE_DEBUG_PGL_TXARB_SP                                                            (0x1<<9) // This bit give strict priority to read over write on the PGL read-write arbiter.
+  #define PGLUE_B_REG_PGL_CORE_DEBUG_PGL_TXARB_SP_SHIFT                                                      9
+#define PGLUE_B_REG_PGL_PM_STATUS                                                                            0x2a847cUL //Access:R    DataWidth:0x10   // Contains pcie_func_hidden vector.
+#define PGLUE_B_REG_PGL_WRITE_BLOCKED                                                                        0x2a8480UL //Access:R    DataWidth:0x2    // Bit 0: This bit indicates that a write request was blocked because of bus_master_en was deasserted. Bit 1: Added in BigBear-B0. Indicates that currently a write request is blocked due to any of the blocking conditions.
+#define PGLUE_B_REG_PGL_READ_BLOCKED                                                                         0x2a8484UL //Access:R    DataWidth:0x2    // Bit 0: This bit indicates that a read request was blocked because of bus_master_en was deasserted. Bit 1: Added in BigBear-B0. Indicates that currently a read request is blocked due to any of the blocking conditions.
+#define PGLUE_B_REG_READ_FIFO_OCCUPANCY_LEVEL                                                                0x2a8488UL //Access:R    DataWidth:0x4    // Debug only: Occupancy level in PGLUE master read FIFO. This is the driver counter.
+#define PGLUE_B_REG_WRITE_FIFO_MAX_OCCUPANCY_LEVEL                                                           0x2a848cUL //Access:R    DataWidth:0x5    // Debug only: Maximal occupancy level in PGLUE master write FIFO.
+#define PGLUE_B_REG_READ_FIFO_MAX_OCCUPANCY_LEVEL                                                            0x2a8490UL //Access:R    DataWidth:0x4    // Debug only: Maximal occupancy level in PGLUE master read FIFO.
+#define PGLUE_B_REG_WRITE_FIFO_WRITE_PTR                                                                     0x2a8494UL //Access:R    DataWidth:0x5    // Debug only: Write pointer in PGLUE master write FIFO.
+#define PGLUE_B_REG_WRITE_FIFO_DRIVER_READ_PTR                                                               0x2a8498UL //Access:R    DataWidth:0x5    // Debug only: Driver read pointer in PGLUE master write FIFO.
+#define PGLUE_B_REG_WRITE_FIFO_FILLER_READ_PTR                                                               0x2a849cUL //Access:R    DataWidth:0x5    // Debug only: Filler read pointer in PGLUE master write FIFO.
+#define PGLUE_B_REG_READ_FIFO_WRITE_PTR                                                                      0x2a84a0UL //Access:R    DataWidth:0x4    // Debug only: Write pointer in PGLUE master read FIFO.
+#define PGLUE_B_REG_READ_FIFO_DRIVER_READ_PTR                                                                0x2a84a4UL //Access:R    DataWidth:0x4    // Debug only: Driver read pointer in PGLUE master read FIFO.
+#define PGLUE_B_REG_MAX_USED_TAGS                                                                            0x2a84a8UL //Access:R    DataWidth:0x9    // Debug only: Maximal number of used tags at a given time since reset.
+#define PGLUE_B_REG_RX_LEGACY_ERRORS                                                                         0x2a84acUL //Access:R    DataWidth:0x8    // Each bit indicates a type of legacy error that was received in user RX interface since last reset. Note that such errors are legitimate. Bit 0 - Target memory read arrived with a correctable error. Bit 1 - Target memory read arrived with an uncorrectable error. Bit 2 - Configuration RW arrived with a correctable error. Bit 3 - Configuration RW arrived with an uncorrectable error. Bit 4 - Target memory write or MSGD arrived with a correctable error. Bit 5 - Target memory write or MSGD arrived with an uncorrectable error. Bit 6 - Master completion arrived with a correctable error. Bit 7 - Master completion arrived with an uncorrectable error.
+#define PGLUE_B_REG_PCIE_DBGSYN_ALMOST_FULL_THR                                                              0x2a84b0UL //Access:RW   DataWidth:0x4    // Debug only: If more than this Number of entries are occupied in the PCIe dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed.
+#define PGLUE_B_REG_PCIE_DBGSYN_ENABLE                                                                       0x2a84b4UL //Access:RW   DataWidth:0x1    // Debug only: When 1, PCIe dbgsyn clock synchronization FIFO is enabled and frame, valid, data are output from it to the debug block. When 0, PCIe dbgsyn clock synchronization FIFO is disabled and pcie_top_wrapper should output 0 in frame, valid and data outputs.
+#define PGLUE_B_REG_DISABLE_HIGHER_BW                                                                        0x2a84b8UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define PGLUE_B_REG_DISABLE_HIGHER_BW_DISABLE_HIGHER_BW_WAW                                                (0x1<<0) // Debug only. Used to disable an E2 optimization of having less dead cycles between adjacent write request (write after write) from PGLUE to PCIe core. When disable_two_pending_wr_requests is 0; this bit must be 0 as well.
+  #define PGLUE_B_REG_DISABLE_HIGHER_BW_DISABLE_HIGHER_BW_WAW_SHIFT                                          0
+  #define PGLUE_B_REG_DISABLE_HIGHER_BW_DISABLE_TWO_PENDING_REQUESTS                                         (0x1<<1) // Debug only. Used to disable an E2 optimization of sending two pending requests from PGLUE to PCIe core. The two pending requests are of different types (master write; master read; target completion).
+  #define PGLUE_B_REG_DISABLE_HIGHER_BW_DISABLE_TWO_PENDING_REQUESTS_SHIFT                                   1
+  #define PGLUE_B_REG_DISABLE_HIGHER_BW_DISABLE_TWO_PENDING_WR_REQUESTS                                      (0x1<<2) // Debug only. Used to disable an E2 optimization of sending two pending write requests from PGLUE to PCIe core. When this bit is 0; disable_higher_bw_waw must be 0 as well.
+  #define PGLUE_B_REG_DISABLE_HIGHER_BW_DISABLE_TWO_PENDING_WR_REQUESTS_SHIFT                                2
+#define PGLUE_B_REG_MEMCTRL_WR_RD_N_BB                                                                       0x2a84bcUL //Access:RW   DataWidth:0x1    // wr/rd indication to CPU BIST
+#define PGLUE_B_REG_MEMCTRL_CMD_BB                                                                           0x2a84c0UL //Access:RW   DataWidth:0x8    // command to CPU BIST
+#define PGLUE_B_REG_MEMCTRL_ADDRESS_BB                                                                       0x2a84c4UL //Access:RW   DataWidth:0x8    // address to CPU BIST
+#define PGLUE_B_REG_MEMCTRL_STATUS                                                                           0x2a84c8UL //Access:R    DataWidth:0x20   // status from CPU BIST
+#define PGLUE_B_REG_PCIE_CHECKSUM_ERROR                                                                      0x2a84ccUL //Access:R    DataWidth:0x1    // Indicates there was an error in PCIe checksum in data from PCIe core.
+#define PGLUE_B_REG_REMOVE_PCIE_CHECKSUM                                                                     0x2a84d0UL //Access:RW   DataWidth:0x1    // Debug only: 0 - PCIe checksum is generated towards PCIe core. 1 - PCIe checksum is not generated towards PCIe core. This is a chicken bit in case that the extra sample added for checksum calculation needs to be bypassed.
+#define PGLUE_B_REG_TC_PER_VQ                                                                                0x2a84d4UL //Access:RW   DataWidth:0x20   // A bit per VQ that indicates the TC to use.
+#define PGLUE_B_REG_PSEUDO_VF_MASTER_ENABLE                                                                  0x2a84d8UL //Access:RW   DataWidth:0x1    // Enable for pseudo VF master mode.
+#define PGLUE_B_REG_PSEUDO_VF_TARGET_ENABLE                                                                  0x2a84dcUL //Access:RW   DataWidth:0x1    // Enable for pseudo VF target mode.
+#define PGLUE_B_REG_LOG2_F_DB_WND                                                                            0x2a84e0UL //Access:RW   DataWidth:0x5    // Pseudo VF target mode configuration that controls the size of each pseudo-VF in the BAR.
+#define PGLUE_B_REG_VF_BASE                                                                                  0x2a84e4UL //Access:RW   DataWidth:0x5    // Pseudo VF target mode configuration that defines first VF divided by 8 for each PF.
+#define PGLUE_B_REG_DORQ_ACCESS_VIA_BAR0_E5                                                                  0x2a84e8UL //Access:RW   DataWidth:0x3    // Enable PF to accesss DORQ via BAR0: 0-disable access; 1-enable access if BAR0 size is 128K;  2-enable access if BAR0 size is 256K;  4-enable access if BAR0 size is 512K;
+#define PGLUE_B_REG_VSC_EN_E5                                                                                0x2a84ecUL //Access:RW   DataWidth:0x9    // VSC fields: bit 0 - enable VSC; bits 1-8 - VSC reserved bits in VSC header
+#define PGLUE_B_REG_PGL_CONTROL0                                                                             0x2a8520UL //Access:RW   DataWidth:0x13   // Multi Field Register.
+  #define PGLUE_B_REG_PGL_CONTROL0_PGL_CPL_AFT                                                               (0x7f<<0) // Almost full threshold for completion interface (debug purposes).
+  #define PGLUE_B_REG_PGL_CONTROL0_PGL_CPL_AFT_SHIFT                                                         0
+  #define PGLUE_B_REG_PGL_CONTROL0_PGL_DISABLE_INPUTS                                                        (0x1<<7) // Debug only: disable inputs to pgl.
+  #define PGLUE_B_REG_PGL_CONTROL0_PGL_DISABLE_INPUTS_SHIFT                                                  7
+  #define PGLUE_B_REG_PGL_CONTROL0_PGL_TXW_CC_THRESH                                                         (0x1f<<8) // The fullness threshold of the txw data fifo after which transaction may start.
+  #define PGLUE_B_REG_PGL_CONTROL0_PGL_TXW_CC_THRESH_SHIFT                                                   8
+  #define PGLUE_B_REG_PGL_CONTROL0_PGL_TXW_DP_AFT                                                            (0x3f<<13) // The fullnes threshold of the txw data fifo after which the block stops reading from pswwr.
+  #define PGLUE_B_REG_PGL_CONTROL0_PGL_TXW_DP_AFT_SHIFT                                                      13
+#define PGLUE_B_REG_CSSNOOP_ALMOST_FULL_THR                                                                  0x2a8524UL //Access:RW   DataWidth:0x2    // Debug only: If more than this Number of entries are occupied in the cssnoop clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed.
+#define PGLUE_B_REG_TXW_H_SYNCFIFO_ALMOSTFULL_TH_K2_E5                                                       0x2a8528UL //Access:RW   DataWidth:0x5    // Debug only: If more than this Number of entries are occupied in the TXW header clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed. In AH, due to CQ84005, this value must be bigger or equal to txw_d_syncfifo_almostfull_th.
+#define PGLUE_B_REG_TXW_D_SYNCFIFO_ALMOSTFULL_TH_K2_E5                                                       0x2a852cUL //Access:RW   DataWidth:0x5    // Debug only: If more than this Number of entries are occupied in the TXW data clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed.
+#define PGLUE_B_REG_TXR_H_SYNCFIFO_ALMOSTFULL_TH_K2_E5                                                       0x2a8530UL //Access:RW   DataWidth:0x5    // Debug only: If more than this Number of entries are occupied in the TXR header clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed.
+#define PGLUE_B_REG_PGL_TXR_CDTS                                                                             0x2a8560UL //Access:R    DataWidth:0x9    // Debug only.
+#define PGLUE_B_REG_PGL_TXW_CDTS                                                                             0x2a8564UL //Access:R    DataWidth:0x15   // Debug only.
+#define PGLUE_B_REG_ADMIN_PER_PF_REGION                                                                      0x2a9000UL //Access:RW   DataWidth:0x20   // This register maps the Admin per-PF region. Addresses 0x0 - 0x5c: 12 per-PF PF windows. Each PF window contains two 32-bit values. The low address (0, 2, and on) contains the 22-bit offset register. The high address (1, 3 and on) contains the pretend registers. Addresses 0x60-0x1ec: reserved. Address 0x1f0: Global pretend register. Address 0x1f4 - reserved. Address 0x1f8 - ME opaque register. Address 0x1fc - ME concrete register. E4: split16. Note that the reset values of the read only addresses is not X. The reset value of the reserved addresses is 0.
+#define PGLUE_B_REG_ADMIN_PER_PF_REGION_SIZE                                                                 128
+#define PGLUE_B_REG_ADMIN_GLOBAL_REGION                                                                      0x2a9200UL //Access:RW   DataWidth:0x20   // This register maps the Admin global region. 0x0 - 0x3c8 (0x200 - 0x5c8) -  243 global windows. Each entry is the 12-bit window offset. Addresses 0x3cc - 0xe08 (0x5cc - 0xffc) - reserved (reset value 0).
+#define PGLUE_B_REG_ADMIN_GLOBAL_REGION_SIZE                                                                 896
+#define PGLUE_B_REG_CFG_SPACE_A_ADDRESS                                                                      0x2aa000UL //Access:RW   DataWidth:0x6    // Address[12:7] in PCI configuration space of the first register on which config space A attention is generated. Note that this register is in 128-byte units.
+#define PGLUE_B_REG_CFG_SPACE_A_ENABLE                                                                       0x2aa004UL //Access:RW   DataWidth:0x20   // Indicates which of the 32 registers starting in address cfg_space_a_address generates an attention. If bit N is set - a CSSNOOP cycle with address {cfg_space_a_address; 7b0}+4*N will generate a config space A attention.
+#define PGLUE_B_REG_CFG_SPACE_B_ADDRESS                                                                      0x2aa008UL //Access:RW   DataWidth:0x6    // Address[12:7] in PCI configuration space of the first register on which config space B attention is generated. Note that this register is in 128-byte units.
+#define PGLUE_B_REG_CFG_SPACE_B_ENABLE                                                                       0x2aa00cUL //Access:RW   DataWidth:0x20   // Indicates which of the 32 registers starting in address cfg_space_b_address generates an attention. If bit N is set - a CSSNOOP cycle with address {cfg_space_b_address; 7b0}+4*N will generate a config space B attention.
+#define PGLUE_B_REG_CFG_SPACE_A_REQUEST                                                                      0x2aa010UL //Access:R    DataWidth:0x10   // Config space A attention dirty bits. Each bit indicates that the corresponding PF generates config space A attention. Set by PXP. Reset by MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits from both paths.
+#define PGLUE_B_REG_CFG_SPACE_A_REQUEST_CLR                                                                  0x2aa014UL //Access:W    DataWidth:0x10   // Config space A attention dirty bits clear. MCP writes 1 to a bit in this register in order to clear the corresponding bit in cfg_space_a_request register. Note: register contains bits from both paths. Note: Need to re-read the enabled registers after clearing the dirty bit and then check the dirty bit is still clear since they may have been written again during the scan.
+#define PGLUE_B_REG_CFG_SPACE_B_REQUEST                                                                      0x2aa018UL //Access:R    DataWidth:0x10   // Config space B attention dirty bits. Each bit indicates that the corresponding PF generates config space B attention. Set by PXP. Reset by MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits from both paths.
+#define PGLUE_B_REG_CFG_SPACE_B_REQUEST_CLR                                                                  0x2aa01cUL //Access:W    DataWidth:0x10   // Config space B attention dirty bits clear. MCP writes 1 to a bit in this register in order to clear the corresponding bit in cfg_space_b_request register. Note: register contains bits from both paths. Note: Need to re-read the enabled registers after clearing the dirty bit and then check the dirty bit is still clear since they may have been written again during the scan.
+#define PGLUE_B_REG_FLR_REQUEST_VF_31_0                                                                      0x2aa020UL //Access:R    DataWidth:0x20   // FLR request attention dirty bits for VFs 0 to 31. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr.
+#define PGLUE_B_REG_FLR_REQUEST_VF_63_32                                                                     0x2aa024UL //Access:R    DataWidth:0x20   // FLR request attention dirty bits for VFs 32 to 63. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr.
+#define PGLUE_B_REG_FLR_REQUEST_VF_95_64                                                                     0x2aa028UL //Access:R    DataWidth:0x20   // FLR request attention dirty bits for VFs 64 to 95. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr.
+#define PGLUE_B_REG_FLR_REQUEST_VF_127_96                                                                    0x2aa02cUL //Access:R    DataWidth:0x20   // FLR request attention dirty bits for VFs 96 to 127. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr.
+#define PGLUE_B_REG_FLR_REQUEST_VF_159_128                                                                   0x2aa030UL //Access:R    DataWidth:0x20   // FLR request attention dirty bits for VFs 128 to 159. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_159_128_clr.
+#define PGLUE_B_REG_FLR_REQUEST_VF_191_160                                                                   0x2aa034UL //Access:R    DataWidth:0x20   // FLR request attention dirty bits for VFs 160 to 191. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_191_160_clr.
+#define PGLUE_B_REG_FLR_REQUEST_VF_223_192                                                                   0x2aa038UL //Access:R    DataWidth:0x20   // FLR request attention dirty bits for VFs 192 to 223. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_223_192_clr.
+#define PGLUE_B_REG_FLR_REQUEST_VF_255_224                                                                   0x2aa03cUL //Access:R    DataWidth:0x20   // FLR request attention dirty bits for VFs 224 to 255. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_255_224_clr.
+#define PGLUE_B_REG_FLR_REQUEST_PF_31_0                                                                      0x2aa040UL //Access:R    DataWidth:0x10   // FLR request attention dirty bits for all PFs. Each bit indicates that the FLR register of the corresponding PF was set. Set by PXP. Reset by MCP writing 1 to flr_request_pf_31_0_clr. Note: register contains bits from both paths.
+#define PGLUE_B_REG_FLR_REQUEST_VF_31_0_CLR                                                                  0x2aa044UL //Access:W    DataWidth:0x20   // FLR request attention dirty bits clear for VFs 0 to 31. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_vf_31_0 register.
+#define PGLUE_B_REG_FLR_REQUEST_VF_63_32_CLR                                                                 0x2aa048UL //Access:W    DataWidth:0x20   // FLR request attention dirty bits clear for VFs 32 to 63. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_vf_63_32 register.
+#define PGLUE_B_REG_FLR_REQUEST_VF_95_64_CLR                                                                 0x2aa04cUL //Access:W    DataWidth:0x20   // FLR request attention dirty bits clear for VFs 64 to 95. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_vf_95_64 register.
+#define PGLUE_B_REG_FLR_REQUEST_VF_127_96_CLR                                                                0x2aa050UL //Access:W    DataWidth:0x20   // FLR request attention dirty bits clear for VFs 96 to 127. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_vf_127_96 register.
+#define PGLUE_B_REG_FLR_REQUEST_VF_159_128_CLR                                                               0x2aa054UL //Access:W    DataWidth:0x20   // FLR request attention dirty bits clear for VFs 128 to 159. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_vf_159_128 register.
+#define PGLUE_B_REG_FLR_REQUEST_VF_191_160_CLR                                                               0x2aa058UL //Access:W    DataWidth:0x20   // FLR request attention dirty bits clear for VFs 160 to 191. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_vf_191_160 register.
+#define PGLUE_B_REG_FLR_REQUEST_VF_223_192_CLR                                                               0x2aa05cUL //Access:W    DataWidth:0x20   // FLR request attention dirty bits clear for VFs 192 to 223. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_vf_223_192 register.
+#define PGLUE_B_REG_FLR_REQUEST_VF_255_224_CLR                                                               0x2aa060UL //Access:W    DataWidth:0x20   // FLR request attention dirty bits clear for VFs 224 to 255. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_vf_255_224 register.
+#define PGLUE_B_REG_FLR_REQUEST_PF_31_0_CLR                                                                  0x2aa064UL //Access:W    DataWidth:0x10   // FLR request attention dirty bits clear for all PFs.  MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_pf_31_0 register. Note: register contains bits from both paths.
+#define PGLUE_B_REG_DISABLE_FLR_SRIOV_DISABLED                                                               0x2aa068UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PGLUE_B_REG_DISABLE_FLR_SRIOV_DISABLED_DISABLE_FLR_REQUEST                                         (0x1<<0) // Debug only: When 1 flr request is not generated by PGLUE.
+  #define PGLUE_B_REG_DISABLE_FLR_SRIOV_DISABLED_DISABLE_FLR_REQUEST_SHIFT                                   0
+  #define PGLUE_B_REG_DISABLE_FLR_SRIOV_DISABLED_DISABLE_SRIOV_DISABLED_REQUEST                              (0x1<<1) // Debug only: When 1 SR-IOV disbaled request is not generated by PGLUE.
+  #define PGLUE_B_REG_DISABLE_FLR_SRIOV_DISABLED_DISABLE_SRIOV_DISABLED_REQUEST_SHIFT                        1
+#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST                                                                  0x2aa06cUL //Access:R    DataWidth:0x10   // SR IOV disabled attention dirty bits. Each bit indicates that the VF enable register of the corresponding PF is written to 0 and was previously 1. Set by PXP. Reset by MCP writing 1 to sr_iov_disabled_request_clr. Note: register contains bits from both paths.
+#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST_CLR                                                              0x2aa070UL //Access:W    DataWidth:0x10   // SR IOV disabled attention dirty bits clear. MCP writes 1 to a bit in this register in order to clear the corresponding bit in sr_iov_disabled_request register. Note: register contains bits from both paths.
+#define PGLUE_B_REG_SHADOW_BME_VF_31_0                                                                       0x2aa074UL //Access:R    DataWidth:0x20   // Shadow BME register for VFs 0 to 31. Each bit indicates if the corresponding VF is enabled.
+#define PGLUE_B_REG_SHADOW_BME_VF_63_32                                                                      0x2aa078UL //Access:R    DataWidth:0x20   // Shadow BME register for VFs 32 to 63. Each bit indicates if the corresponding VF is enabled.
+#define PGLUE_B_REG_SHADOW_BME_VF_95_64                                                                      0x2aa07cUL //Access:R    DataWidth:0x20   // Shadow BME register for VFs 64 to 95. Each bit indicates if the corresponding VF is enabled.
+#define PGLUE_B_REG_SHADOW_BME_VF_127_96                                                                     0x2aa080UL //Access:R    DataWidth:0x20   // Shadow BME register for VFs 96 to 127. Each bit indicates if the corresponding VF is enabled.
+#define PGLUE_B_REG_SHADOW_BME_VF_159_128                                                                    0x2aa084UL //Access:R    DataWidth:0x20   // Shadow BME register for VFs 128 to 159. Each bit indicates if the corresponding VF is enabled.
+#define PGLUE_B_REG_SHADOW_BME_VF_191_160                                                                    0x2aa088UL //Access:R    DataWidth:0x20   // Shadow BME register for VFs 160 to 191. Each bit indicates if the corresponding VF is enabled.
+#define PGLUE_B_REG_SHADOW_BME_VF_223_192                                                                    0x2aa08cUL //Access:R    DataWidth:0x20   // Shadow BME register for VFs 192 to 223. Each bit indicates if the corresponding VF is enabled.
+#define PGLUE_B_REG_SHADOW_BME_VF_255_224                                                                    0x2aa090UL //Access:R    DataWidth:0x20   // Shadow BME register for VFs 224 to 255. Each bit indicates if the corresponding VF is enabled.
+#define PGLUE_B_REG_SHADOW_BME_PF_31_0                                                                       0x2aa094UL //Access:R    DataWidth:0x10   // Shadow BME register for all PFs. Each bit indicates if the corresponding PF is enabled. Note: register contains bits from both paths.
+#define PGLUE_B_REG_SHADOW_VF_31_0_CLR                                                                       0x2aa098UL //Access:W    DataWidth:0x20   // Shadow bits clear for VFs 0 to 31.  MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled events.
+#define PGLUE_B_REG_SHADOW_VF_63_32_CLR                                                                      0x2aa09cUL //Access:W    DataWidth:0x20   // Shadow bits clear for VFs 32 to 63.  MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled events.
+#define PGLUE_B_REG_SHADOW_VF_95_64_CLR                                                                      0x2aa0a0UL //Access:W    DataWidth:0x20   // Shadow bits clear for VFs 64 to 95.  MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled events.
+#define PGLUE_B_REG_SHADOW_VF_127_96_CLR                                                                     0x2aa0a4UL //Access:W    DataWidth:0x20   // Shadow bits clear for VFs 96 to 127.  MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled events. Note: register contains bits from both paths.
+#define PGLUE_B_REG_SHADOW_VF_159_128_CLR                                                                    0x2aa0a8UL //Access:W    DataWidth:0x20   // Shadow bits clear for VFs 128 to 159.  MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled events.
+#define PGLUE_B_REG_SHADOW_VF_191_160_CLR                                                                    0x2aa0acUL //Access:W    DataWidth:0x20   // Shadow bits clear for VFs 160 to 191.  MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled events.
+#define PGLUE_B_REG_SHADOW_VF_223_192_CLR                                                                    0x2aa0b0UL //Access:W    DataWidth:0x20   // Shadow bits clear for VFs 192 to 223.  MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled events.
+#define PGLUE_B_REG_SHADOW_VF_255_224_CLR                                                                    0x2aa0b4UL //Access:W    DataWidth:0x20   // Shadow bits clear for VFs 224 to 255.  MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled events.
+#define PGLUE_B_REG_SHADOW_PF_31_0_CLR                                                                       0x2aa0b8UL //Access:W    DataWidth:0x10   // Debug only - Shadow bits clear for PFs 0 to 31.  MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select fields. MCP should never use this unless a work-around is needed. Note: register contains bits from both paths.
+#define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_31_0                                                                0x2aa0bcUL //Access:R    DataWidth:0x20   // Shadow ats_enable register for VFs 0 to 31. Each bit indicates if ATS for the corresponding VF is enabled.
+#define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_63_32                                                               0x2aa0c0UL //Access:R    DataWidth:0x20   // Shadow ats_enable register for VFs 32 to 63. Each bit indicates if ATS for the corresponding VF is enabled.
+#define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_95_64                                                               0x2aa0c4UL //Access:R    DataWidth:0x20   // Shadow ats_enable register for VFs 64 to 95. Each bit indicates if ATS for the corresponding VF is enabled.
+#define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_127_96                                                              0x2aa0c8UL //Access:R    DataWidth:0x20   // Shadow ats_enable register for VFs 96 to 127. Each bit indicates if ATS for the corresponding VF is enabled.
+#define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_159_128                                                             0x2aa0ccUL //Access:R    DataWidth:0x20   // Shadow ats_enable register for VFs 128 to 159. Each bit indicates if ATS for the corresponding VF is enabled.
+#define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_191_160                                                             0x2aa0d0UL //Access:R    DataWidth:0x20   // Shadow ats_enable register for VFs 160 to 191. Each bit indicates if ATS for the corresponding VF is enabled.
+#define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_223_192                                                             0x2aa0d4UL //Access:R    DataWidth:0x20   // Shadow ats_enable register for VFs 192 to 223. Each bit indicates if ATS for the corresponding VF is enabled.
+#define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_255_224                                                             0x2aa0d8UL //Access:R    DataWidth:0x20   // Shadow ats_enable register for VFs 224 to 255. Each bit indicates if ATS for the corresponding VF is enabled.
+#define PGLUE_B_REG_SHADOW_ATS_ENABLE_PF_31_0                                                                0x2aa0dcUL //Access:R    DataWidth:0x10   // Shadow ats_enable register for all PFs. Each bit indicates if ATS for the corresponding PF is enabled. Note: register contains bits from both paths.
+#define PGLUE_B_REG_SHADOW_VF_ENABLE_PF_31_0                                                                 0x2aa0e0UL //Access:R    DataWidth:0x10   // Shadow vf_enable register for all PFs. Each bit indicates if SR-IOV for the corresponding PF is enabled. Note: register contains bits from both paths.
+#define PGLUE_B_REG_SHADOW_ATS_STU                                                                           0x2aa0e4UL //Access:R    DataWidth:0x5    // Read only. Shadow ATS_STU register. (2^ATS_STU)*4KB is ATC translation address granularity. E4: split16.
+#define PGLUE_B_REG_SHADOW_IDO_BITS                                                                          0x2aa0e8UL //Access:R    DataWidth:0x20   // Shadow ido bits register for PFs 0 to 15. [15:0] : Each bit indicates if IDO_REQ_ENABLE bit for the corresponding PF is set. [31:16] : Each bit indicates if IDO_CPL_ENABLE bit for the corresponding PF is set. Note: register contains bits from both paths.
+#define PGLUE_B_REG_DISABLE_ATS_EN_CLEARING                                                                  0x2aa0ecUL //Access:RW   DataWidth:0x1    // Debug only: PGLUE automatically clears ATC enable for a function if a TCPL arrived for that function with Unsupported Request error. Setting this register to 1 disables this automatic clearing.
+#define PGLUE_B_REG_INCORRECT_RCV_DETAILS                                                                    0x2aa0f0UL //Access:R    DataWidth:0x8    // Each bit indicates an incorrect behavior in user RX interface. Bit 0 - Reserved. Bit 1 - Reserved. Bit 2 - Reserved. Bit 3 - Reserved. Bit 4 - Completion with Configuration Request Retry Status. Bit 5 - Expansion ROM access received with a write request. Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010; and pcie_rx_last not asserted.
+#define PGLUE_B_REG_WAS_ERROR_VF_31_0                                                                        0x2aa0f4UL //Access:R    DataWidth:0x20   // Was_error indication dirty bits for VFs 0 to 31.  Each bit indicates that there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 to was_error_vf_31_0_clr.
+#define PGLUE_B_REG_WAS_ERROR_VF_63_32                                                                       0x2aa0f8UL //Access:R    DataWidth:0x20   // Was_error indication dirty bits for VFs 32 to 63.  Each bit indicates that there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 to was_error_vf_63_32_clr.
+#define PGLUE_B_REG_WAS_ERROR_VF_95_64                                                                       0x2aa0fcUL //Access:R    DataWidth:0x20   // Was_error indication dirty bits for VFs 64 to 95.  Each bit indicates that there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 to was_error_vf_95_64_clr.
+#define PGLUE_B_REG_WAS_ERROR_VF_127_96                                                                      0x2aa100UL //Access:R    DataWidth:0x20   // Was_error indication dirty bits for VFs 96 to 127.  Each bit indicates that there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 to was_error_vf_127_96_clr.
+#define PGLUE_B_REG_WAS_ERROR_VF_159_128                                                                     0x2aa104UL //Access:R    DataWidth:0x20   // Was_error indication dirty bits for VFs 128 to 159.  Each bit indicates that there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 to was_error_vf_159_128_clr.
+#define PGLUE_B_REG_WAS_ERROR_VF_191_160                                                                     0x2aa108UL //Access:R    DataWidth:0x20   // Was_error indication dirty bits for VFs 160 to 191.  Each bit indicates that there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 to was_error_vf_191_160_clr.
+#define PGLUE_B_REG_WAS_ERROR_VF_223_192                                                                     0x2aa10cUL //Access:R    DataWidth:0x20   // Was_error indication dirty bits for VFs 192 to 223.  Each bit indicates that there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 to was_error_vf_223_192_clr.
+#define PGLUE_B_REG_WAS_ERROR_VF_255_224                                                                     0x2aa110UL //Access:R    DataWidth:0x20   // Was_error indication dirty bits for VFs 224 to 255.  Each bit indicates that there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 to was_error_vf_255_224_clr.
+#define PGLUE_B_REG_WAS_ERROR_PF_31_0                                                                        0x2aa114UL //Access:R    DataWidth:0x10   // Was_error indication dirty bits for PFs 0 to 7.  Each bit indicates that there was a completion with uncorrectable error for the corresponding PF. Set by PXP. Reset by MCP writing 1 to was_error_pf_31_0_clr.
+#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR                                                                    0x2aa118UL //Access:W    DataWidth:0x20   // Was_error indication dirty bits clear for VFs 0 to 31. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_31_0 register. The register is split per path but VFID is global. Each path can reset only the VFs belong to it.
+#define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR                                                                   0x2aa11cUL //Access:W    DataWidth:0x20   // Was_error indication dirty bits clear for VFs 32 to 63. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_63_32 register. The register is split per path but VFID is global. Each path can reset only the VFs belong to it.
+#define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR                                                                   0x2aa120UL //Access:W    DataWidth:0x20   // Was_error indication dirty bits clear for VFs 64 to 95. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_95_64 register. The register is split per path but VFID is global. Each path can reset only the VFs belong to it.
+#define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR                                                                  0x2aa124UL //Access:W    DataWidth:0x20   // Was_error indication dirty bits clear for VFs 96 to 127. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_127_96 register. The register is split per path but VFID is global. Each path can reset only the VFs belong to it.
+#define PGLUE_B_REG_WAS_ERROR_VF_159_128_CLR                                                                 0x2aa128UL //Access:W    DataWidth:0x20   // Was_error indication dirty bits clear for VFs 128 to 159. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_159_128 register. The register is split per path but VFID is global. Each path can reset only the VFs belong to it.
+#define PGLUE_B_REG_WAS_ERROR_VF_191_160_CLR                                                                 0x2aa12cUL //Access:W    DataWidth:0x20   // Was_error indication dirty bits clear for VFs 160 to 191. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_191_160 register. The register is split per path but VFID is global. Each path can reset only the VFs belong to it.
+#define PGLUE_B_REG_WAS_ERROR_VF_223_192_CLR                                                                 0x2aa130UL //Access:W    DataWidth:0x20   // Was_error indication dirty bits clear for VFs 192 to 223. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_223_192 register. The register is split per path but VFID is global. Each path can reset only the VFs belong to it.
+#define PGLUE_B_REG_WAS_ERROR_VF_255_224_CLR                                                                 0x2aa134UL //Access:W    DataWidth:0x20   // Was_error indication dirty bits clear for VFs 224 to 255. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_255_224 register. The register is split per path but VFID is global. Each path can reset only the VFs belong to it.
+#define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR                                                                    0x2aa138UL //Access:W    DataWidth:0x10   // Was_error indication dirty bits clear for PFs 0 to 7.  MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_pf_31_0 register. The register is split per path but PFID is global. Each path can reset only the PFs belong to it.
+#define PGLUE_B_REG_RX_ERR_DETAILS                                                                           0x2aa13cUL //Access:R    DataWidth:0x10   // Details of first request received with error. [3:0] - PFID. [4] - VF_VALID. [12:5] - VFID. [14:13] - Error Code - 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 - unsupported request. 2 - completer abort. 3 - Illegal value for this field. [15] valid - indicates if there was a completion error since the last time this register was cleared.
+#define PGLUE_B_REG_RX_TCPL_ERR_DETAILS                                                                      0x2aa140UL //Access:R    DataWidth:0x15   // Details of first ATS Translation Completion request received with error. [3:0] - PFID. [4] - VF_VALID. [12:5] - VFID. [14:13] - Error Code - 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 - unsupported request. 2 - completer abort. 3 - Illegal value for this field. [19:15] - ATC OTB EntryID. [20] valid - indicates if there was a completion error since the last time this register was cleared.
+#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0                                                                       0x2aa144UL //Access:R    DataWidth:0x20   // Address [31:0] of first write request not submitted due to error.
+#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32                                                                      0x2aa148UL //Access:R    DataWidth:0x20   // Address [63:32] of first write request not submitted due to error.
+#define PGLUE_B_REG_TX_ERR_WR_DETAILS                                                                        0x2aa14cUL //Access:R    DataWidth:0x20   // Details of first write request not submitted due to error. [4:0] VQID. [17:5] - Length in bytes. [19] - VF_VALID. [23:20] - PFID. [31:24] - VFID.
+#define PGLUE_B_REG_TX_ERR_WR_DETAILS2                                                                       0x2aa150UL //Access:R    DataWidth:0x1e   // Details of first write request not submitted due to error. [15:0] Request ID. [20:16] client ID. [24:21] - Error type - [21] - Indicates was_error was set; [22] - Indicates BME was cleared; [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent PF FLR_request or IOV_disable_request dirty bit is set; [25] - Indicates AtomicOp Requester Enable was cleared for Atomic Operation; [26] - last SR. [28:27] - Atomic - 0 - Regular request (not Atomic). 1 - CAS. 2 - FetchAdd. 3 - Swap. [29] - valid - indicates if there was a request not submitted due to error since the last time this register was cleared.
+#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0                                                                       0x2aa154UL //Access:R    DataWidth:0x20   // Address [31:0] of first read request not submitted due to error.
+#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32                                                                      0x2aa158UL //Access:R    DataWidth:0x20   // Address [63:32] of first read request not submitted due to error.
+#define PGLUE_B_REG_TX_ERR_RD_DETAILS                                                                        0x2aa15cUL //Access:R    DataWidth:0x20   // Details of first read request not submitted due to error. [4:0] VQID. [5] TREQ. 1 - Indicates the request is a Translation Request. [18:6] - Length in bytes. [19] - VF_VALID. [23:20] - PFID. [31:24] - VFID.
+#define PGLUE_B_REG_TX_ERR_RD_DETAILS2                                                                       0x2aa160UL //Access:R    DataWidth:0x1c   // Details of first read request not submitted due to error. [15:0] Request ID. [20:16] client ID. [24:21] - Error type - [21] - Indicates was_error was set; [22] - Indicates BME was cleared; [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent PF FLR_request or IOV_disable_request dirty bit is set. [25] - last SR. [26] valid - indicates if there was a request not submitted due to error since the last time this register was cleared. [27] dstate_0 and write discard
+#define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL                                                                   0x2aa164UL //Access:R    DataWidth:0x18   // Details of first Invalidation Completion or MCTP message submitted during a TX error condition. [3:0] - PFID. [11:4] - VFID. [12] - VF_VALID. [17:13] - ITAG Index.  [21:18] - Error type - [18] - Indicates was_error was set; [19] - Indicates BME was cleared; [20] - Indicates FID_enable was cleared; [21] - Indicates VF with parent PF FLR_request or IOV_disable_request dirty bit is set. [22] - 0 indicates ICPL; 1 indicates MCTP. [23] valid - indicates if there was an Invalidation Completion message submitted during a TX error condition since the last time this register was cleared.
+#define PGLUE_B_REG_INTERNAL_VFID_ENABLE                                                                     0x2aa168UL //Access:RW   DataWidth:0x1    // Internal FID_enable configuration per-VF for master and target transactions. E4: split240.
+#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER                                                              0x2aa16cUL //Access:RW   DataWidth:0x1    // Internal FID_enable configuration per-PF for master transactions. E4: split16.
+#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE                                                        0x2aa170UL //Access:RW   DataWidth:0x1    // Internal FID_enable configuration per-PF for target write transactions. E4: split16.
+#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ                                                         0x2aa174UL //Access:RW   DataWidth:0x1    // Internal FID_enable configuration per-PF for target read transactions. E4: split16.
+#define PGLUE_B_REG_INTERNAL_VFID_ENABLE_31_0_VALUE                                                          0x2aa178UL //Access:R    DataWidth:0x20   // A global view of internal_vfid_enable register for VFs 0 to 31.
+#define PGLUE_B_REG_INTERNAL_VFID_ENABLE_63_32_VALUE                                                         0x2aa17cUL //Access:R    DataWidth:0x20   // A global view of internal_vfid_enable register for VFs 32 to 63.
+#define PGLUE_B_REG_INTERNAL_VFID_ENABLE_95_64_VALUE                                                         0x2aa180UL //Access:R    DataWidth:0x20   // A global view of internal_vfid_enable register for VFs 64 to 95.
+#define PGLUE_B_REG_INTERNAL_VFID_ENABLE_127_96_VALUE                                                        0x2aa184UL //Access:R    DataWidth:0x20   // A global view of internal_vfid_enable register for VFs 96 to 127.
+#define PGLUE_B_REG_INTERNAL_VFID_ENABLE_159_128_VALUE                                                       0x2aa188UL //Access:R    DataWidth:0x20   // A global view of internal_vfid_enable register for VFs 128 to 159.
+#define PGLUE_B_REG_INTERNAL_VFID_ENABLE_191_160_VALUE                                                       0x2aa18cUL //Access:R    DataWidth:0x20   // A global view of internal_vfid_enable register for VFs 224 to 191.
+#define PGLUE_B_REG_INTERNAL_VFID_ENABLE_223_192_VALUE                                                       0x2aa190UL //Access:R    DataWidth:0x20   // A global view of internal_vfid_enable register for VFs 192 to 223.
+#define PGLUE_B_REG_INTERNAL_VFID_ENABLE_255_224_VALUE                                                       0x2aa194UL //Access:R    DataWidth:0x20   // A global view of internal_vfid_enable register for VFs 224 to 255.
+#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_VALUE                                                               0x2aa198UL //Access:R    DataWidth:0x20   // A global view of internal_pfid_enable registers for target flow. Bits [15:0] - internal_pfid_enable_target_write; Bits [31:16] - internal_pfid_enable_target_read.
+#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_VALUE_MASTER                                                        0x2aa19cUL //Access:R    DataWidth:0x10   // A global view of internal_pfid_enable registers for master flow. Bits [15:0] - internal_pfid_enable_master.
+#define PGLUE_B_REG_TSDM_START_OFFSET_A                                                                      0x2aa1a0UL //Access:RW   DataWidth:0x13   // Start offset of TSDM zone A (queue zone) in the internal RAM.
+#define PGLUE_B_REG_TSDM_OFFSET_MASK_A                                                                       0x2aa1a4UL //Access:RW   DataWidth:0x5    // Offset mask of TSDM zone A (queue zone) in the internal RAM.
+#define PGLUE_B_REG_TSDM_START_OFFSET_B                                                                      0x2aa1a8UL //Access:RW   DataWidth:0x13   // Start offset of TSDM zone B (legacy zone) in the internal RAM.
+#define PGLUE_B_REG_TSDM_OFFSET_MASK_B                                                                       0x2aa1acUL //Access:RW   DataWidth:0x9    // Offset mask of TSDM zone B (legacy zone) in the internal RAM.
+#define PGLUE_B_REG_TSDM_VF_SHIFT_B                                                                          0x2aa1b0UL //Access:RW   DataWidth:0x5    // VF Shift of TSDM zone B (legacy zone) in the internal RAM.
+#define PGLUE_B_REG_MSDM_START_OFFSET_A                                                                      0x2aa1b4UL //Access:RW   DataWidth:0x13   // Start offset of msdm zone A (queue zone) in the internal RAM.
+#define PGLUE_B_REG_MSDM_OFFSET_MASK_A                                                                       0x2aa1b8UL //Access:RW   DataWidth:0x5    // Offset mask of msdm zone A (queue zone) in the internal RAM.
+#define PGLUE_B_REG_MSDM_START_OFFSET_B                                                                      0x2aa1bcUL //Access:RW   DataWidth:0x13   // Start offset of msdm zone B (legacy zone) in the internal RAM.
+#define PGLUE_B_REG_MSDM_OFFSET_MASK_B                                                                       0x2aa1c0UL //Access:RW   DataWidth:0x9    // Offset mask of msdm zone B (legacy zone) in the internal RAM.
+#define PGLUE_B_REG_MSDM_VF_SHIFT_B                                                                          0x2aa1c4UL //Access:RW   DataWidth:0x5    // VF Shift of msdm zone B (legacy zone) in the internal RAM.
+#define PGLUE_B_REG_USDM_START_OFFSET_A                                                                      0x2aa1c8UL //Access:RW   DataWidth:0x13   // Start offset of USDM zone A (queue zone) in the internal RAM.
+#define PGLUE_B_REG_USDM_OFFSET_MASK_A                                                                       0x2aa1ccUL //Access:RW   DataWidth:0x5    // Offset mask of USDM zone A (queue zone) in the internal RAM.
+#define PGLUE_B_REG_USDM_START_OFFSET_B                                                                      0x2aa1d0UL //Access:RW   DataWidth:0x13   // Start offset of USDM zone B (legacy zone) in the internal RAM.
+#define PGLUE_B_REG_USDM_OFFSET_MASK_B                                                                       0x2aa1d4UL //Access:RW   DataWidth:0x9    // Offset mask of USDM zone B (legacy zone) in the internal RAM.
+#define PGLUE_B_REG_USDM_VF_SHIFT_B                                                                          0x2aa1d8UL //Access:RW   DataWidth:0x5    // VF Shift of USDM zone B (legacy zone) in the internal RAM.
+#define PGLUE_B_REG_XSDM_START_OFFSET_A                                                                      0x2aa1dcUL //Access:RW   DataWidth:0x13   // Start offset of XSDM zone A (queue zone) in the internal RAM.
+#define PGLUE_B_REG_XSDM_OFFSET_MASK_A                                                                       0x2aa1e0UL //Access:RW   DataWidth:0x5    // Offset mask of XSDM zone A (queue zone) in the internal RAM.
+#define PGLUE_B_REG_XSDM_START_OFFSET_B                                                                      0x2aa1e4UL //Access:RW   DataWidth:0x13   // Start offset of XSDM zone B (legacy zone) in the internal RAM.
+#define PGLUE_B_REG_XSDM_OFFSET_MASK_B                                                                       0x2aa1e8UL //Access:RW   DataWidth:0x9    // Offset mask of XSDM zone B (legacy zone) in the internal RAM.
+#define PGLUE_B_REG_XSDM_VF_SHIFT_B                                                                          0x2aa1ecUL //Access:RW   DataWidth:0x5    // VF Shift of XSDM zone B (legacy zone) in the internal RAM.
+#define PGLUE_B_REG_YSDM_START_OFFSET_A                                                                      0x2aa1f0UL //Access:RW   DataWidth:0x13   // Start offset of ysdm zone A (queue zone) in the internal RAM.
+#define PGLUE_B_REG_YSDM_OFFSET_MASK_A                                                                       0x2aa1f4UL //Access:RW   DataWidth:0x5    // Offset mask of ysdm zone A (queue zone) in the internal RAM.
+#define PGLUE_B_REG_YSDM_START_OFFSET_B                                                                      0x2aa1f8UL //Access:RW   DataWidth:0x13   // Start offset of ysdm zone B (legacy zone) in the internal RAM.
+#define PGLUE_B_REG_YSDM_OFFSET_MASK_B                                                                       0x2aa1fcUL //Access:RW   DataWidth:0x9    // Offset mask of ysdm zone B (legacy zone) in the internal RAM.
+#define PGLUE_B_REG_YSDM_VF_SHIFT_B                                                                          0x2aa200UL //Access:RW   DataWidth:0x5    // VF Shift of ysdm zone B (legacy zone) in the internal RAM.
+#define PGLUE_B_REG_PSDM_START_OFFSET_A                                                                      0x2aa204UL //Access:RW   DataWidth:0x13   // Start offset of psdm zone A (queue zone) in the internal RAM.
+#define PGLUE_B_REG_PSDM_OFFSET_MASK_A                                                                       0x2aa208UL //Access:RW   DataWidth:0x5    // Offset mask of psdm zone A (queue zone) in the internal RAM.
+#define PGLUE_B_REG_PSDM_START_OFFSET_B                                                                      0x2aa20cUL //Access:RW   DataWidth:0x13   // Start offset of psdm zone B (legacy zone) in the internal RAM.
+#define PGLUE_B_REG_PSDM_OFFSET_MASK_B                                                                       0x2aa210UL //Access:RW   DataWidth:0x9    // Offset mask of psdm zone B (legacy zone) in the internal RAM.
+#define PGLUE_B_REG_PSDM_VF_SHIFT_B                                                                          0x2aa214UL //Access:RW   DataWidth:0x5    // VF Shift of psdm zone B (legacy zone) in the internal RAM.
+#define PGLUE_B_REG_TSDM_INB_INT_A_0                                                                         0x2aa218UL //Access:RW   DataWidth:0xb    // Type A PF/VF inbound interrupt table for SDM: bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabled for PF and VF. bits[9:5]-end address in byte resolution;bits[4:0]-start address in byte resolution (relative to start_offset_a).
+#define PGLUE_B_REG_TSDM_INB_INT_A_1                                                                         0x2aa21cUL //Access:RW   DataWidth:0xb    // Type A PF/VF inbound interrupt table for SDM: bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabled for PF and VF. bits[9:5]-end address in byte resolution;bits[4:0]-start address in byte resolution (relative to start_offset_a).
+#define PGLUE_B_REG_TSDM_INB_INT_B_VF_0                                                                      0x2aa220UL //Access:RW   DataWidth:0xc    // Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolution (bits 8:3 of the address).
+#define PGLUE_B_REG_TSDM_INB_INT_B_VF_1                                                                      0x2aa224UL //Access:RW   DataWidth:0xc    // Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolution (bits 8:3 of the address).
+#define PGLUE_B_REG_MSDM_INB_INT_A_0                                                                         0x2aa228UL //Access:RW   DataWidth:0xb    // Type A PF/VF inbound interrupt table for SDM: bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabled for PF and VF. bits[9:5]-end address in byte resolution;bits[4:0]-start address in byte resolution (relative to start_offset_a).
+#define PGLUE_B_REG_MSDM_INB_INT_A_1                                                                         0x2aa22cUL //Access:RW   DataWidth:0xb    // Type A PF/VF inbound interrupt table for SDM: bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabled for PF and VF. bits[9:5]-end address in byte resolution;bits[4:0]-start address in byte resolution (relative to start_offset_a).
+#define PGLUE_B_REG_MSDM_INB_INT_B_VF_0                                                                      0x2aa230UL //Access:RW   DataWidth:0xc    // Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolution (bits 8:3 of the address).
+#define PGLUE_B_REG_MSDM_INB_INT_B_VF_1                                                                      0x2aa234UL //Access:RW   DataWidth:0xc    // Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolution (bits 8:3 of the address).
+#define PGLUE_B_REG_USDM_INB_INT_A_0                                                                         0x2aa238UL //Access:RW   DataWidth:0xb    // Type A PF/VF inbound interrupt table for SDM: bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabled for PF and VF. bits[9:5]-end address in byte resolution;bits[4:0]-start address in byte resolution (relative to start_offset_a).
+#define PGLUE_B_REG_USDM_INB_INT_A_1                                                                         0x2aa23cUL //Access:RW   DataWidth:0xb    // Type A PF/VF inbound interrupt table for SDM: bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabled for PF and VF. bits[9:5]-end address in byte resolution;bits[4:0]-start address in byte resolution (relative to start_offset_a).
+#define PGLUE_B_REG_USDM_INB_INT_B_VF_0                                                                      0x2aa240UL //Access:RW   DataWidth:0xc    // Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolution (bits 8:3 of the address).
+#define PGLUE_B_REG_USDM_INB_INT_B_VF_1                                                                      0x2aa244UL //Access:RW   DataWidth:0xc    // Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolution (bits 8:3 of the address).
+#define PGLUE_B_REG_XSDM_INB_INT_A_0                                                                         0x2aa248UL //Access:RW   DataWidth:0xb    // Type A PF/VF inbound interrupt table for SDM: bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabled for PF and VF. bits[9:5]-end address in byte resolution;bits[4:0]-start address in byte resolution (relative to start_offset_a).
+#define PGLUE_B_REG_XSDM_INB_INT_A_1                                                                         0x2aa24cUL //Access:RW   DataWidth:0xb    // Type A PF/VF inbound interrupt table for SDM: bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabled for PF and VF. bits[9:5]-end address in byte resolution;bits[4:0]-start address in byte resolution (relative to start_offset_a).
+#define PGLUE_B_REG_XSDM_INB_INT_B_VF_0                                                                      0x2aa250UL //Access:RW   DataWidth:0xc    // Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolution (bits 8:3 of the address).
+#define PGLUE_B_REG_XSDM_INB_INT_B_VF_1                                                                      0x2aa254UL //Access:RW   DataWidth:0xc    // Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolution (bits 8:3 of the address).
+#define PGLUE_B_REG_YSDM_INB_INT_A_0                                                                         0x2aa258UL //Access:RW   DataWidth:0xb    // Type A PF/VF inbound interrupt table for SDM: bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabled for PF and VF. bits[9:5]-end address in byte resolution;bits[4:0]-start address in byte resolution (relative to start_offset_a).
+#define PGLUE_B_REG_YSDM_INB_INT_A_1                                                                         0x2aa25cUL //Access:RW   DataWidth:0xb    // Type A PF/VF inbound interrupt table for SDM: bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabled for PF and VF. bits[9:5]-end address in byte resolution;bits[4:0]-start address in byte resolution (relative to start_offset_a).
+#define PGLUE_B_REG_YSDM_INB_INT_B_VF_0                                                                      0x2aa260UL //Access:RW   DataWidth:0xc    // Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolution (bits 8:3 of the address).
+#define PGLUE_B_REG_YSDM_INB_INT_B_VF_1                                                                      0x2aa264UL //Access:RW   DataWidth:0xc    // Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolution (bits 8:3 of the address).
+#define PGLUE_B_REG_PSDM_INB_INT_A_0                                                                         0x2aa268UL //Access:RW   DataWidth:0xb    // Type A PF/VF inbound interrupt table for SDM: bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabled for PF and VF. bits[9:5]-end address in byte resolution;bits[4:0]-start address in byte resolution (relative to start_offset_a).
+#define PGLUE_B_REG_PSDM_INB_INT_A_1                                                                         0x2aa26cUL //Access:RW   DataWidth:0xb    // Type A PF/VF inbound interrupt table for SDM: bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabled for PF and VF. bits[9:5]-end address in byte resolution;bits[4:0]-start address in byte resolution (relative to start_offset_a).
+#define PGLUE_B_REG_PSDM_INB_INT_B_VF_0                                                                      0x2aa270UL //Access:RW   DataWidth:0xc    // Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolution (bits 8:3 of the address).
+#define PGLUE_B_REG_PSDM_INB_INT_B_VF_1                                                                      0x2aa274UL //Access:RW   DataWidth:0xc    // Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolution (bits 8:3 of the address).
+#define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF                                                                      0x2aa318UL //Access:RW   DataWidth:0x1    // 0 - Zone A PF has NumQueues queues. 1 - Zone A PF has NumSBs queues. NumQueues is 256 for BB and 320 for K2. NumSBs is 288 for BB and 368 for K2.
+#define PGLUE_B_REG_MSDM_ZONE_A_SIZE_PF                                                                      0x2aa31cUL //Access:RW   DataWidth:0x1    // 0 - Zone A PF has NumQueues queues. 1 - Zone A PF has NumSBs queues. NumQueues is 256 for BB and 320 for K2. NumSBs is 288 for BB and 368 for K2.
+#define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF                                                                      0x2aa320UL //Access:RW   DataWidth:0x1    // 0 - Zone A PF has NumQueues queues. 1 - Zone A PF has NumSBs queues. NumQueues is 256 for BB and 320 for K2. NumSBs is 288 for BB and 368 for K2.
+#define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF                                                                      0x2aa324UL //Access:RW   DataWidth:0x1    // 0 - Zone A PF has NumQueues queues. 1 - Zone A PF has NumSBs queues. NumQueues is 256 for BB and 320 for K2. NumSBs is 288 for BB and 368 for K2.
+#define PGLUE_B_REG_YSDM_ZONE_A_SIZE_PF                                                                      0x2aa328UL //Access:RW   DataWidth:0x1    // 0 - Zone A PF has NumQueues queues. 1 - Zone A PF has NumSBs queues. NumQueues is 256 for BB and 320 for K2. NumSBs is 288 for BB and 368 for K2.
+#define PGLUE_B_REG_PSDM_ZONE_A_SIZE_PF                                                                      0x2aa32cUL //Access:RW   DataWidth:0x1    // 0 - Zone A PF has NumQueues queues. 1 - Zone A PF has NumSBs queues. NumQueues is 256 for BB and 320 for K2. NumSBs is 288 for BB and 368 for K2.
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_0                                                                    0x2aa330UL //Access:RW   DataWidth:0x19   // Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_0                                                                    0x2aa334UL //Access:RW   DataWidth:0x17   // Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_1                                                                    0x2aa338UL //Access:RW   DataWidth:0x19   // Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_1                                                                    0x2aa33cUL //Access:RW   DataWidth:0x17   // Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_2                                                                    0x2aa340UL //Access:RW   DataWidth:0x19   // Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_2                                                                    0x2aa344UL //Access:RW   DataWidth:0x17   // Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_3                                                                    0x2aa348UL //Access:RW   DataWidth:0x19   // Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_3                                                                    0x2aa34cUL //Access:RW   DataWidth:0x17   // Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_4                                                                    0x2aa350UL //Access:RW   DataWidth:0x19   // Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_4                                                                    0x2aa354UL //Access:RW   DataWidth:0x17   // Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_5                                                                    0x2aa358UL //Access:RW   DataWidth:0x19   // Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_5                                                                    0x2aa35cUL //Access:RW   DataWidth:0x17   // Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_6                                                                    0x2aa360UL //Access:RW   DataWidth:0x19   // Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_6                                                                    0x2aa364UL //Access:RW   DataWidth:0x17   // Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_7                                                                    0x2aa368UL //Access:RW   DataWidth:0x19   // Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_7                                                                    0x2aa36cUL //Access:RW   DataWidth:0x17   // Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_8                                                                    0x2aa370UL //Access:RW   DataWidth:0x19   // Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_8                                                                    0x2aa374UL //Access:RW   DataWidth:0x17   // Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_9                                                                    0x2aa378UL //Access:RW   DataWidth:0x19   // Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_9                                                                    0x2aa37cUL //Access:RW   DataWidth:0x17   // Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_10                                                                   0x2aa380UL //Access:RW   DataWidth:0x19   // Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_10                                                                   0x2aa384UL //Access:RW   DataWidth:0x17   // Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_11                                                                   0x2aa388UL //Access:RW   DataWidth:0x19   // Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_11                                                                   0x2aa38cUL //Access:RW   DataWidth:0x17   // Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_12                                                                   0x2aa390UL //Access:RW   DataWidth:0x19   // Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_12                                                                   0x2aa394UL //Access:RW   DataWidth:0x17   // Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_13                                                                   0x2aa398UL //Access:RW   DataWidth:0x19   // Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_13                                                                   0x2aa39cUL //Access:RW   DataWidth:0x17   // Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_14                                                                   0x2aa3a0UL //Access:RW   DataWidth:0x19   // Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_14                                                                   0x2aa3a4UL //Access:RW   DataWidth:0x17   // Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART1_15                                                                   0x2aa3a8UL //Access:RW   DataWidth:0x19   // Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).
+#define PGLUE_B_REG_VF_GRC_ACCESS_PART2_15                                                                   0x2aa3acUL //Access:RW   DataWidth:0x17   // Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.
+#define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS                                                              0x2aa3b0UL //Access:R    DataWidth:0x1b   // Details of first target VF request with length violation (too many DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address). [14:13] BAR. [22:15] VFID. [26:23] - PFID.
+#define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS2                                                             0x2aa3b4UL //Access:R    DataWidth:0x7    // Details of first target VF request with length violation (too many DWs) accessing BAR0. [5:0] - Length in DWs.  [6] valid - indicates if there was a request with length violation since the last time this register was cleared. Length violations: length of more than 2DWs; length of 2DWs and address not QW aligned; window is GRC and length is more than 1 DW.
+#define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS                                                           0x2aa3b8UL //Access:R    DataWidth:0x1d   // Details of first target VF request accessing VF GRC space that failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write. [23:16] VFID. [27:24] - PFID. [28] valid - indicates if there was a request accessing VF GRC space that failed permission check since the last time this register was cleared. Permission checks are: function permission; R/W permission; address range permission.
+#define PGLUE_B_REG_LATCHED_ERRORS_CLR                                                                       0x2aa3bcUL //Access:W    DataWidth:0x11   // Writing 1 to each bit in this register clears a corresponding error details register and enables logging new error details. Bit 0 - clears INCORRECT_RCV_DETAILS; Bit 1 - clears RX_ERR_DETAILS; Bit 2 - clears TX_ERR_WR_ADD_31_0 TX_ERR_WR_ADD_63_32 TX_ERR_WR_DETAILS TX_ERR_WR_DETAILS2 TX_ERR_RD_ADD_31_0 TX_ERR_RD_ADD_63_32 TX_ERR_RD_DETAILS TX_ERR_RD_DETAILS2 TX_ERR_WR_DETAILS_ICPL MASTER_ZLR_ERR_ADD_31_0 MASTER_ZLR_ERR_ADD_63_32 MASTER_ZLR_ERR_DETAILS VF_ILT_ERR_ADD_31_0 VF_ILT_ERR_ADD_63_32 VF_ILT_ERR_DETAILS VF_ILT_ERR_DETAILS2; Bit 3 - clears VF_LENGTH_VIOLATION_DETAILS. Bit 4 - clears VF_GRC_SPACE_VIOLATION_DETAILS. Bit 5 - clears RX_TCPL_ERR_DETAILS. Bit 6 - clears TCPL_IN_TWO_RCBS_DETAILS. Bit 7 - clears ADMIN_WINDOW_VIOLATION_DETAILS. Bit 8 - clears OUT_OF_RANGE_FUNCTION_IN_PRETEND_DETAILS OUT_OF_RANGE_FUNCTION_IN_PRETEND_ADDRESS. Bit 9 - clears ILLEGAL_ADDRESS (DETAILS and ADDRESS registers). Bit 10 - clears TPH (DETAILS and ADDRESS registers) although this logging does not relate to error. Bit 12 - DBI error log clr. Bit 13 - MCT Error log clr Bit 14 - TLP Abort error log clr Bit 15 - ECRC Abort error log clr Bit 16 - Poison error log clr
+#define PGLUE_B_REG_IDO_ENABLE_MASTER_RW                                                                     0x2aa3c0UL //Access:RW   DataWidth:0x20   // Each bit when set indicates that IDO bit towards PGLUE should be set for this VQ.
+#define PGLUE_B_REG_IDO_ENABLE_MASTER_RW2                                                                    0x2aa3c4UL //Access:RW   DataWidth:0x1    // Bit 0 - when set indicates that IDO bit towards PGLUE should be set for Translation Requests.
+#define PGLUE_B_REG_IDO_ENABLE_TARGET_CPL                                                                    0x2aa3c8UL //Access:RW   DataWidth:0x1    // Bit 0 - when set indicates that IDO bit towards PGLUE should be set for Target Completions.
+#define PGLUE_B_REG_IGU_BYPASS_ON_ERR                                                                        0x2aa3ccUL //Access:RW   DataWidth:0x1    // 1 - Do not discard IGU master transactions for PF when the corresponding was_error bit is set.
+#define PGLUE_B_REG_ALLOW_MSIX_ACCESS_IN_BAR0                                                                0x2aa3d0UL //Access:RW   DataWidth:0x1    // 0 - Accesses to the first 8KB of IGU in BAR0 (MSIX table and PBA) are not allowed. When this value is configured; BAR2 size for PFs and VFs should be configured to 8KB to allow ONLY MSIX table and PBA access. 1 - All IGU space in BAR 0 is accessible; including the first 8KB. When this value is configured; BAR2 size for PFs can be configured to 64KB and for VFs to 16KB to allow all IGU space to be accessed in BAR2 as well.
+#define PGLUE_B_REG_TCPL_IN_TWO_RCBS_DETAILS                                                                 0x2aa3d4UL //Access:R    DataWidth:0x13   // Details of first ATS Translation Completion received in two rcbs (packets). Logging is triggered by a Translation Completion with length different than 2 DWs. Such a case is unsupported and the Translation completion is considered erroneous. [3:0] - PFID. [4] - VF_VALID. [12:5] - VFID. [17:13] - OTB EntryID. [18] valid - indicates if there was a Translation Completion received in two rcbs since the last time this register was cleared.
+#define PGLUE_B_REG_PCIE_ERR_STATUS                                                                          0x2aa3d8UL //Access:R    DataWidth:0x4    // Details of PCIe core error status. Valid when pgl_pcie_attn in pxp2 is set. 0 - Unsupported Request or Completer Abort on User RX Interface. 1 - Reception of a poisoned TLP on RX Lanes. 2 - Completion timeout. 3 - Unexpected Completion on RX Lanes. 4 - Detected Unsupported Request on RX Lanes. 5 - ECRC error on RX Lanes. 6 - Reserved. 7 - Reserved. 8 - Illegal operation size on User TX Interface. 9 - Detected Unsupported Request on User TX Interface (Bridge Forwarding Error). 10 - Unsupported header type on User TX Interface. 11 - Reserved. 12 - NP TAG value on User TX Interface already in use. 13 - Completion RTAG value on User TX Interface unexpected. 14 - User TX Interface Overflow Error (Too many req wo/ack). 15 - reserved.
+#define PGLUE_B_REG_CPU_MBIST_MEMCTRL_0_CNTRL_CMD                                                            0x2aa3dcUL //Access:RW   DataWidth:0x5    // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.
+#define PGLUE_B_REG_CPU_MBIST_MEMCTRL_1_CNTRL_CMD                                                            0x2aa3e0UL //Access:RW   DataWidth:0x5    // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.
+#define PGLUE_B_REG_DISABLE_TCPL_TRANSLATION_SIZE_CHECK                                                      0x2aa3ecUL //Access:RW   DataWidth:0x1    // Debug only: 0 - Enable the fix for CQ45220. If a Function receives a Translation Completion with a Translation Size field smaller than the Function programmed STU value; clear the ATS_en shadow bit and send UR to the ATC. 1 - Disable the fix for CQ45220.
+#define PGLUE_B_REG_CPU_MBIST_MEMCTRL_2_CNTRL_CMD                                                            0x2aa3f0UL //Access:RW   DataWidth:0x5    // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.
+#define PGLUE_B_REG_CPU_MBIST_MEMCTRL_3_CNTRL_CMD                                                            0x2aa3f4UL //Access:RW   DataWidth:0x5    // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.
+#define PGLUE_B_REG_PGL_TGTWR_MLENGTH                                                                        0x2aa400UL //Access:RW   DataWidth:0xa    // Maximal length allowed for target writes (dwords). Target writes with bigger length are discarded. Configuration value must be at least 16 DWORDs, so the discarded packetstarget writes have at least two cycles.
+#define PGLUE_B_REG_PGL_ADDR_88_F0_BB                                                                        0x2aa404UL //Access:RW   DataWidth:0x20   // GRC address for configuration access to PCIE config address 0x88. any write to this PCIE address will cause a GRC write access to the address that's in t this register. E4: split16.
+#define PGLUE_B_REG_PGL_ADDR_8C_F0_BB                                                                        0x2aa408UL //Access:RW   DataWidth:0x20   // GRC address for configuration access to PCIE config address 0x8c.  any write to this PCIE address will cause a GRC write access to the address that's in t this register. E4: split16.
+#define PGLUE_B_REG_PGL_ADDR_90_F0_BB                                                                        0x2aa40cUL //Access:RW   DataWidth:0x20   // GRC address for configuration access to PCIE config address 0x90.  any write to this PCIE address will cause a GRC write access to the address that's in t this register. E4: split16.
+#define PGLUE_B_REG_PGL_ADDR_94_F0_BB                                                                        0x2aa410UL //Access:RW   DataWidth:0x20   // GRC address for configuration access to PCIE config address 0x94.  any write to this PCIE address will cause a GRC write access to the address that's in t this register. E4: split16.
+#define PGLUE_B_REG_PGL_EXP_ROM_ADDR                                                                         0x2aa414UL //Access:R    DataWidth:0x19   // The address to be read from expansion rom (address is in bytes according to read packet from host).
+#define PGLUE_B_REG_PGL_EXP_ROM_FUNC                                                                         0x2aa418UL //Access:R    DataWidth:0x4    // The function number of the expansion rom that is being accessed.
+#define PGLUE_B_REG_PGL_EXP_ROM_SIZE                                                                         0x2aa41cUL //Access:R    DataWidth:0x2    // The size in dwords to be read from expansion rom (according to read packet from host).
+#define PGLUE_B_REG_PGL_EXP_ROM0                                                                             0x2aa420UL //Access:RW   DataWidth:0x20   // First dword data of expansion rom request. When this register is written a completion is sent to the pcie core. When the expansion rom request contains more than one dword this register should be written last. Writing to this register when there is not pending expansion rom request should not be done!.
+#define PGLUE_B_REG_PGL_EXP_ROM1                                                                             0x2aa424UL //Access:RW   DataWidth:0x20   // Second dword data of expansion rom request.
+#define PGLUE_B_REG_PGL_EXP_ROM2                                                                             0x2aa428UL //Access:RW   DataWidth:0x20   // Third dword data of expansion rom request.
+#define PGLUE_B_REG_PGL_TAGS_LIMIT                                                                           0x2aa42cUL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define PGLUE_B_REG_PGL_TAGS_LIMIT_PGL_MAX_TAGS                                                            (0xff<<0) // This field sets the maximal number of outstanding tags.
+  #define PGLUE_B_REG_PGL_TAGS_LIMIT_PGL_MAX_TAGS_SHIFT                                                      0
+  #define PGLUE_B_REG_PGL_TAGS_LIMIT_PGL_MAX_TAGS_DISABLE                                                    (0x1<<8) // This field disables the outstadnging tags limit mechanism.
+  #define PGLUE_B_REG_PGL_TAGS_LIMIT_PGL_MAX_TAGS_DISABLE_SHIFT                                              8
+#define PGLUE_B_REG_SDM_INB_INT_B_PF_0                                                                       0x2aa440UL //Access:RW   DataWidth:0x1a   // 8 memories; each corresponds to a different legacy (type B) PF inbound interrupt index. In every memory there are 6 lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-start address in 64B resolution (bits 15:6).
+#define PGLUE_B_REG_SDM_INB_INT_B_PF_0_SIZE                                                                  6
+#define PGLUE_B_REG_SDM_INB_INT_B_PF_1                                                                       0x2aa460UL //Access:RW   DataWidth:0x1a   // 8 memories; each corresponds to a different legacy (type B) PF inbound interrupt index. In every memory there are 6 lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-start address in 64B resolution (bits 15:6).
+#define PGLUE_B_REG_SDM_INB_INT_B_PF_1_SIZE                                                                  6
+#define PGLUE_B_REG_SDM_INB_INT_B_PF_2                                                                       0x2aa480UL //Access:RW   DataWidth:0x1a   // 8 memories; each corresponds to a different legacy (type B) PF inbound interrupt index. In every memory there are 6 lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-start address in 64B resolution (bits 15:6).
+#define PGLUE_B_REG_SDM_INB_INT_B_PF_2_SIZE                                                                  6
+#define PGLUE_B_REG_SDM_INB_INT_B_PF_3                                                                       0x2aa4a0UL //Access:RW   DataWidth:0x1a   // 8 memories; each corresponds to a different legacy (type B) PF inbound interrupt index. In every memory there are 6 lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-start address in 64B resolution (bits 15:6).
+#define PGLUE_B_REG_SDM_INB_INT_B_PF_3_SIZE                                                                  6
+#define PGLUE_B_REG_SDM_INB_INT_B_PF_4                                                                       0x2aa4c0UL //Access:RW   DataWidth:0x1a   // 8 memories; each corresponds to a different legacy (type B) PF inbound interrupt index. In every memory there are 6 lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-start address in 64B resolution (bits 15:6).
+#define PGLUE_B_REG_SDM_INB_INT_B_PF_4_SIZE                                                                  6
+#define PGLUE_B_REG_SDM_INB_INT_B_PF_5                                                                       0x2aa4e0UL //Access:RW   DataWidth:0x1a   // 8 memories; each corresponds to a different legacy (type B) PF inbound interrupt index. In every memory there are 6 lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-start address in 64B resolution (bits 15:6).
+#define PGLUE_B_REG_SDM_INB_INT_B_PF_5_SIZE                                                                  6
+#define PGLUE_B_REG_SDM_INB_INT_B_PF_6                                                                       0x2aa500UL //Access:RW   DataWidth:0x1a   // 8 memories; each corresponds to a different legacy (type B) PF inbound interrupt index. In every memory there are 6 lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-start address in 64B resolution (bits 15:6).
+#define PGLUE_B_REG_SDM_INB_INT_B_PF_6_SIZE                                                                  6
+#define PGLUE_B_REG_SDM_INB_INT_B_PF_7                                                                       0x2aa520UL //Access:RW   DataWidth:0x1a   // 8 memories; each corresponds to a different legacy (type B) PF inbound interrupt index. In every memory there are 6 lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-start address in 64B resolution (bits 15:6).
+#define PGLUE_B_REG_SDM_INB_INT_B_PF_7_SIZE                                                                  6
+#define PGLUE_B_REG_PF_TRUSTED                                                                               0x2aa540UL //Access:RW   DataWidth:0x1    // Each bit in this read-only register reflects the value of the corresponding 'PF trusted' config bit on the external configuration space (on PCI address 0x7C bit0). It is used for physical device assignment flow. 0 - PF is untranted. 1 - PF is trusted.
+#define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0                                                                  0x2aa544UL //Access:R    DataWidth:0x20   // Address [31:0] of first read request with length = 0.
+#define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32                                                                 0x2aa548UL //Access:R    DataWidth:0x20   // Address [63:32] of first read request with length = 0.
+#define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS                                                                   0x2aa54cUL //Access:R    DataWidth:0x1a   // Details of first read request with length = 0. [4:0] VQID. [5] TREQ. 1 - Indicates the request is a Translation Request. [9:6] - PFID. [10] - VF_VALID. [18:11] - VFID. [23:19] client ID. [24] - last SR. [25] valid - indicates if there was a request with length = 0 since the last time this register was cleared. This error should not normally happen, but may happen with physical device assignement flow. The register is cleared with latched_errors_clr bit 2.
+#define PGLUE_B_REG_DISABLE_TPH_NONALIGNED                                                                   0x2aa550UL //Access:RW   DataWidth:0x1    // Relevant for read request with tph_valid = '1' and with either address not DW aligned or length not a multiple of DWs. 0 - PGLUE will submit the request with TPH info. PXP will take care of aligning it correctly when sending the response to the client (already done in E3). 1 - PGLUE should handle the request as it as if it arrived with TPH_Valid = '0'.
+#define PGLUE_B_REG_ADMIN_WINDOW_VIOLATION_DETAILS                                                           0x2aa554UL //Access:R    DataWidth:0x1d   // Details of first target Read/Write access to the admin window that have a length bigger than 1DW or first byte enable != 0xf . [9:0] Address in DWs (bits [11:2] of byte address). [13:10] BE first. [17:14] BE last. [21:18] - PFID. [27:22] - Length in DWs. [28] valid - indicates if there was a request with admin window violation since the last time this register was cleared.
+#define PGLUE_B_REG_OUT_OF_RANGE_FUNCTION_IN_PRETEND_DETAILS                                                 0x2aa558UL //Access:R    DataWidth:0x16   // Details of first target Read/Write access where pretend register contains an out of range function. [3:0] - original PFID. [7:4] Pretend PFID. [15:8] Pretend VFID. [16] Pretend vf_valid. [20:17] Pretend register: 0-11 - One of the PF windows pretend. 12 - global pretend register. [21] valid - indicates there was a GRC access where pretend containe dout of range function since the last time this register was cleared.
+#define PGLUE_B_REG_OUT_OF_RANGE_FUNCTION_IN_PRETEND_ADDRESS                                                 0x2aa55cUL //Access:R    DataWidth:0x19   // Address of first target Read/Write access where pretend register contains an out of range function.
+#define PGLUE_B_REG_DISABLE_EXTERNAL_BAR0                                                                    0x2aa560UL //Access:RW   DataWidth:0x1    // 0 - Work with external BAR0 mechanism as defined in E4 spec. 1 - Disable external BAR0 mechanism. Access will be directly to the internal BAR, except accesses to the Admin Window which will still be executed.
+#define PGLUE_B_REG_TSDM_QUEUE_ZONE_SIZE                                                                     0x2aa564UL //Access:RW   DataWidth:0x6    // Queue size for SDM zone A. Possible values: 0B; 8B; 16B; 32B.
+#define PGLUE_B_REG_MSDM_QUEUE_ZONE_SIZE                                                                     0x2aa568UL //Access:RW   DataWidth:0x6    // Queue size for SDM zone A. Possible values: 0B; 8B; 16B; 32B.
+#define PGLUE_B_REG_USDM_QUEUE_ZONE_SIZE                                                                     0x2aa56cUL //Access:RW   DataWidth:0x6    // Queue size for SDM zone A. Possible values: 0B; 8B; 16B; 32B.
+#define PGLUE_B_REG_XSDM_QUEUE_ZONE_SIZE                                                                     0x2aa570UL //Access:RW   DataWidth:0x6    // Queue size for SDM zone A. Possible values: 0B; 8B; 16B; 32B.
+#define PGLUE_B_REG_YSDM_QUEUE_ZONE_SIZE                                                                     0x2aa574UL //Access:RW   DataWidth:0x6    // Queue size for SDM zone A. Possible values: 0B; 8B; 16B; 32B.
+#define PGLUE_B_REG_PSDM_QUEUE_ZONE_SIZE                                                                     0x2aa578UL //Access:RW   DataWidth:0x6    // Queue size for SDM zone A. Possible values: 0B; 8B; 16B; 32B.
+#define PGLUE_B_REG_FID_CHANNEL_ENABLE                                                                       0x2aa57cUL //Access:RW   DataWidth:0x1    // FID channel enable configuration per-VF.  Controls Target read/write access to specific locations in ZoneB of each SDM window in the VF BAR. E4: split240.
+#define PGLUE_B_REG_SDM_CHANNEL_ENABLE                                                                       0x2aa580UL //Access:RW   DataWidth:0x6    // Defines if the PF to VF channel is enabled for that SDM. One bit per SDM. Bit 0 - TSDM. Bit 1 - MSDM. Bit 2 - USDM. Bit 3 - XSDM. Bit 4 - YSDM. Bit 5 - PSDM.
+#define PGLUE_B_REG_PFVF_WINDOW_SIZE                                                                         0x2aa584UL //Access:RW   DataWidth:0x3    // Window size for VF to PF channel. 0 - NA; 1 - 8B; 2 - 16B; 3 - 32B; 4 - 64B; 5 - 128B; 6 - 256B; 7 - 512B.
+#define PGLUE_B_REG_PFVF_WINDOW_START_OFFSET                                                                 0x2aa588UL //Access:RW   DataWidth:0x6    // Defines the start offset of the VF to PF window within VF ZoneB in 8B granularity.
+#define PGLUE_B_REG_MASTER_DISCARD_NBLOCK                                                                    0x2aa58cUL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_PF_BME                                            (0x1<<0) // Decision bit for PF master requests when BME is cleared: 0 - block; 1 - discard.
+  #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_PF_BME_SHIFT                                      0
+  #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_PF_FID_ENABLE                                     (0x1<<1) // Decision bit for PF master requests when fid_enable is cleared: 0 - block; 1 - discard.
+  #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_PF_FID_ENABLE_SHIFT                               1
+  #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_PF_WAS_ERROR                                      (0x1<<2) // Decision bit for PF master requests when was_error is set: 0 - block; 1 - discard.
+  #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_PF_WAS_ERROR_SHIFT                                2
+  #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_VF_BME                                            (0x1<<3) // Decision bit for VF master requests when BME is cleared: 0 - block; 1 - discard.
+  #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_VF_BME_SHIFT                                      3
+  #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_VF_FID_ENABLE                                     (0x1<<4) // Decision bit for VF master requests when fid_enable is cleared: 0 - block; 1 - discard.
+  #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_VF_FID_ENABLE_SHIFT                               4
+  #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_VF_WAS_ERROR                                      (0x1<<5) // Decision bit for VF master requests when was_error is set: 0 - block; 1 - discard.
+  #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_VF_WAS_ERROR_SHIFT                                5
+#define PGLUE_B_REG_MASTER_ATTENTION_SETTING                                                                 0x2aa590UL //Access:RW   DataWidth:0xc    // Multi Field Register.
+  #define PGLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_PF_BME                                      (0x3<<0) // Attention setting configuration for PF master requests when BME is cleared: 0 - Always set (and log error details); 1 - never set attention; 2 - set attention (and log error details) only if FLR is not in progress and mask_block_discard_attn is cleared.
+  #define PGLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_PF_BME_SHIFT                                0
+  #define PGLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_PF_FID_ENABLE                               (0x3<<2) // Attention setting configuration for PF master requests when fid_enabled is cleared: 0 - Always set (and log error details); 1 - never set attention; 2 - set attention (and log error details) only if FLR is not in progress and mask_block_discard_attn is cleared.
+  #define PGLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_PF_FID_ENABLE_SHIFT                         2
+  #define PGLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_PF_WAS_ERROR                                (0x3<<4) // Attention setting configuration for PF master requests when was_error is set: 0 - Always set (and log error details); 1 - never set attention; 2 - set attention (and log error details) only if FLR is not in progress and mask_block_discard_attn is cleared.
+  #define PGLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_PF_WAS_ERROR_SHIFT                          4
+  #define PGLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_VF_BME                                      (0x3<<6) // Attention setting configuration for VF master requests when BME is cleared: 0 - Always set (and log error details); 1 - never set attention; 2 - set attention (and log error details) only if FLR is not in progress and mask_block_discard_attn is cleared.
+  #define PGLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_VF_BME_SHIFT                                6
+  #define PGLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_VF_FID_ENABLE                               (0x3<<8) // Attention setting configuration for VF master requests when fid_enabled is cleared: 0 - Always set (and log error details); 1 - never set attention; 2 - set attention (and log error details) only if FLR is not in progress and mask_block_discard_attn is cleared.
+  #define PGLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_VF_FID_ENABLE_SHIFT                         8
+  #define PGLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_VF_WAS_ERROR                                (0x3<<10) // Attention setting configuration for VF master requests when was_error is set: 0 - Always set (and log error details); 1 - never set attention; 2 - set attention (and log error details) only if FLR is not in progress and mask_block_discard_attn is cleared.
+  #define PGLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_VF_WAS_ERROR_SHIFT                          10
+#define PGLUE_B_REG_MASK_BLOCK_DISCARD_ATTN_PF                                                               0x2aa594UL //Access:RW   DataWidth:0x1    // When this bit is set and attntion setting configuration is 2 any block or discard event for that function will not generate an attention. This bit will allow SW to extend the period in which attention is masked beyond the FLR_in_progress period. E4: split16.
+#define PGLUE_B_REG_MASK_BLOCK_DISCARD_ATTN_VF                                                               0x2aa598UL //Access:RW   DataWidth:0x1    // When this bit is set and attntion setting configuration is 2 any block or discard event for that function will not generate an attention. This bit will allow SW to extend the period in which attention is masked beyond the FLR_in_progress period. E4: split240.
+#define PGLUE_B_REG_WRITE_FIFO_QUEUE                                                                         0x2aa800UL //Access:WB_R DataWidth:0xfb   // Debug only and read only: Each entry provides the content of the corresponding entry in PGLUE master write FIFO. The structure of every entry appears in TBD.
+#define PGLUE_B_REG_WRITE_FIFO_QUEUE_SIZE                                                                    176
+#define PGLUE_B_REG_READ_FIFO_QUEUE                                                                          0x2aac00UL //Access:WB_R DataWidth:0xae   // Debug only and read only: Each entry provides the content of the corresponding entry in PGLUE master read FIFO. The structure of every entry appears in TBD.
+#define PGLUE_B_REG_READ_FIFO_QUEUE_SIZE                                                                     112
+#define PGLUE_B_REG_WRITE_FIFO_OCCUPANCY_LEVEL                                                               0x2aae00UL //Access:R    DataWidth:0x5    // Debug only: Occupancy level in PGLUE master write FIFO. This is the maximum between driver counter and filler counter.
+#define PGLUE_B_REG_USE_CLIENTID_IN_TAG                                                                      0x2aae04UL //Access:RW   DataWidth:0x1    // A value of '1' instructs PGLUE to use the client ID value in the 'tag' field of non-TPH master write packets. This can be used for debug purposes.
+#define PGLUE_B_REG_DETECT_ILLEGAL_ADDRESS_EN                                                                0x2aae08UL //Access:RW   DataWidth:0x1    // This field is an enable bit for 'detection of out-of-range requests' debug feature. It should be initialized to '0' in systems with IOMMU enabled.
+#define PGLUE_B_REG_DETECT_ILLEGAL_ADDRESS                                                                   0x2aae0cUL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define PGLUE_B_REG_DETECT_ILLEGAL_ADDRESS_MINIMAL_ADDRESS_LOG                                             (0x1f<<0) // This field is (the log of ) the minimal legal address value. It is used in the 'detection of out-of-range requests' debug feature.
+  #define PGLUE_B_REG_DETECT_ILLEGAL_ADDRESS_MINIMAL_ADDRESS_LOG_SHIFT                                       0
+  #define PGLUE_B_REG_DETECT_ILLEGAL_ADDRESS_MAXIMAL_ADDRESS_LOG                                             (0x1f<<5) // This field plus 48 is (the log of ) the maximal legal address value. It is used in the 'detection of out-of-range requests' debug feature.
+  #define PGLUE_B_REG_DETECT_ILLEGAL_ADDRESS_MAXIMAL_ADDRESS_LOG_SHIFT                                       5
+#define PGLUE_B_REG_ILLEGAL_ADDRESS_ADD_31_0                                                                 0x2aae10UL //Access:R    DataWidth:0x20   // Address [31:0] of first request with illegal address.
+#define PGLUE_B_REG_ILLEGAL_ADDRESS_ADD_63_32                                                                0x2aae14UL //Access:R    DataWidth:0x20   // Address [63:32] of first request with illegal address.
+#define PGLUE_B_REG_ILLEGAL_ADDRESS_DETAILS                                                                  0x2aae18UL //Access:R    DataWidth:0x20   // Details of first request with illegal address. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20] - PFID. [31:24] - VFID.
+#define PGLUE_B_REG_ILLEGAL_ADDRESS_DETAILS2                                                                 0x2aae1cUL //Access:R    DataWidth:0x19   // Details of first request with illegal address. [15:0] Request ID. [20:16] client ID. [21] Illegal address cause: 0 - address was smaller than minimal_address_log;  1 - address was bigger than maximal_address_log. [22] - write_n_read: 0 - read; 1 - write. [23] - last SR.  [24] valid - indicates if there was a request submitted with illegal address since the last time this register was cleared.
+#define PGLUE_B_REG_TPH_ADD_31_0                                                                             0x2aae20UL //Access:R    DataWidth:0x20   // Address [31:0] of first request sent with TPH information.
+#define PGLUE_B_REG_TPH_ADD_63_32                                                                            0x2aae24UL //Access:R    DataWidth:0x20   // Address [63:32] of first request sent with TPH information.
+#define PGLUE_B_REG_TPH_DETAILS                                                                              0x2aae28UL //Access:R    DataWidth:0x20   // Details of first request sent with TPH information. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20] - PFID. [31:24] - VFID.
+#define PGLUE_B_REG_TPH_DETAILS2                                                                             0x2aae2cUL //Access:R    DataWidth:0x12   // Details of first request sent with TPH information. [4:0] client ID. [6:5] PH. [14:7] Steering Tag. [15] - write_n_read: 0 - read; 1 - write.  [16] - last SR. [17] valid - indicates if there was a request submitted with TPH informationsince the last time this register was cleared.
+#define PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE                                                                  0x2aae30UL //Access:RW   DataWidth:0x1    // 0 - never pad write sub-requests with zeros. 1 - Pad write sub-requests with zeros and align them to cache line according to the sub-request configuration.
+#define PGLUE_B_REG_CACHE_LINE_SIZE                                                                          0x2aae34UL //Access:RW   DataWidth:0x3    // Cache line size for padding. 0 - 32B. 1 - 64B. 2 - 128B. 3 - 256B.
+#define PGLUE_B_REG_TAGS_31_0                                                                                0x2aae38UL //Access:R    DataWidth:0x20   // Indicates the status of tags. 0 - tags is used - read completion did not return yet. 1 - tag is unused.
+#define PGLUE_B_REG_TAGS_63_32                                                                               0x2aae3cUL //Access:R    DataWidth:0x20   // Indicates the status of tags. 0 - tags is used - read completion did not return yet. 1 - tag is unused.
+#define PGLUE_B_REG_TAGS_95_64                                                                               0x2aae40UL //Access:R    DataWidth:0x20   // Indicates the status of tags. 0 - tags is used - read completion did not return yet. 1 - tag is unused.
+#define PGLUE_B_REG_TAGS_127_96                                                                              0x2aae44UL //Access:R    DataWidth:0x20   // Indicates the status of tags. 0 - tags is used - read completion did not return yet. 1 - tag is unused.
+#define PGLUE_B_REG_TAGS_159_128                                                                             0x2aae48UL //Access:R    DataWidth:0x20   // Indicates the status of tags. 0 - tags is used - read completion did not return yet. 1 - tag is unused.
+#define PGLUE_B_REG_TAGS_191_160                                                                             0x2aae4cUL //Access:R    DataWidth:0x20   // Indicates the status of tags. 0 - tags is used - read completion did not return yet. 1 - tag is unused.
+#define PGLUE_B_REG_TAGS_223_192                                                                             0x2aae50UL //Access:R    DataWidth:0x20   // Indicates the status of tags. 0 - tags is used - read completion did not return yet. 1 - tag is unused.
+#define PGLUE_B_REG_TAGS_255_224                                                                             0x2aae54UL //Access:R    DataWidth:0x20   // Indicates the status of tags. 0 - tags is used - read completion did not return yet. 1 - tag is unused.
+#define PGLUE_B_REG_PCIE_LTR_STATE                                                                           0x2aae58UL //Access:R    DataWidth:0x2    // LTR state indication from PCIe core.
+#define PGLUE_B_REG_CONFIG_REG_78                                                                            0x2aae5cUL //Access:RW   DataWidth:0x20   // This register is used for backdoor rbc access to PCI config space register 0x78. There are certain flows (like FLR) where 0x78 should be written but writing it from config space generates Kernel warning. For these cases only it should be written using this rbc register.
+#define PGLUE_B_REG_PF_BAR0_SIZE                                                                             0x2aae60UL //Access:RW   DataWidth:0x4    // For Coupled Mode Teaming. The driver should read BAR1_SIZE from PCIe IP config space (bits 3:0 in PCIE_REG_PCIER_CONFIG_2) and configure to this register. Decoding: 0 disabled; 1 64K; 2 128K; up to 15 1G.
+#define PGLUE_B_REG_PF_BAR1_SIZE                                                                             0x2aae64UL //Access:RW   DataWidth:0x4    // For Coupled Mode Teaming. The driver should read BAR2_SIZE from PCIe IP config space (bits 3:0 in PCIE_REG_PCIER_REG_BAR2_CONFIG) and configure to this register. Decoding: 0 disabled; 1 64K; 2 128K; up to 15 1G. When using resizable BAR, the driver should read the value from BAR_SIZE (bits 12:8 in PCIE_REG_PCIER_RBAR_CTRL) and adjust the decoding. Adjusting is done by adding 5, since in RBAR 0 represents 1M while in regular decoding 5 represents 1M.
+#define PGLUE_B_REG_VF_BAR1_SIZE                                                                             0x2aae68UL //Access:RW   DataWidth:0x4    // For Coupled Mode Teaming. The driver should read BAR2_SIZE_OF_VF from PCIe IP config space (bits 11:8 in PCIE_REG_PCIER_REG_VF_BAR_REG) and configure to this register. Decoding: 0 disabled; 1 4K; 2 8K; up to 15 64M.
+#define PGLUE_B_REG_MCTP_ATTN_CLR                                                                            0x2aae6cUL //Access:W    DataWidth:0x1    // Indication to clear MCTP attention that was genertaed due to bus number change detected by PCIe IP. MCP writes 1 to this register in order to clear the level attention.
+#define PGLUE_B_REG_MCTP_TC                                                                                  0x2aae70UL //Access:RW   DataWidth:0x3    // MCTP TC field. Normally should not be changed.
+#define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0                                                                      0x2aae74UL //Access:R    DataWidth:0x20   // Address [31:0] of first request with vf ilt error indication.
+#define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32                                                                     0x2aae78UL //Access:R    DataWidth:0x20   // Address [63:32] of first request with vf ilt error indication.
+#define PGLUE_B_REG_VF_ILT_ERR_DETAILS                                                                       0x2aae7cUL //Access:R    DataWidth:0x20   // Details of first request with vf ilt error indication. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20] - PFID. [31:24] - VFID.
+#define PGLUE_B_REG_VF_ILT_ERR_DETAILS2                                                                      0x2aae80UL //Access:R    DataWidth:0x18   // Details of first request with vf ilt error indication. [15:0] Request ID. [20:16] client ID. [21] - write_n_read: 0 - read; 1 - write. [22] - last SR.  [23] valid - indicates if there was a request submitted with illegal address since the last time this register was cleared.
+#define PGLUE_B_REG_ATOMIC_OP_REQUESTER_ENABLE_PF                                                            0x2aae84UL //Access:R    DataWidth:0x10   // Atomic Op requester enable register for all PFs. Each bit indicates if Atomic Operation Requester for the corresponding PF is enabled. Note: register contains bits from both paths.
+#define PGLUE_B_REG_EXPANSION_ROM_ATTN                                                                       0x2aae88UL //Access:R    DataWidth:0x2    // Expansion ROM attention dirty bits. Bit 0 is for engine 0 and bit 1 for engine 1. Set by PXP. Reset by MCP writing 1 to the corresponding bit in expansion_rom_attn_clr.
+#define PGLUE_B_REG_EXPANSION_ROM_ATTN_CLR                                                                   0x2aae8cUL //Access:W    DataWidth:0x2    // Expansion ROM attention dirty bits clear. Bit 0 is for engine 0 and bit 1 for engine 1. MCP writes 1 to a bit in this register in order to clear the corresponding bit in expansion_rom_attn register.
+#define PGLUE_B_REG_MPS_ATTN                                                                                 0x2aae90UL //Access:R    DataWidth:0x10   // MPS attention dirty bit. Set by PXP. Reset by MCP writing 1 to the corresponding bit in mps_attn_clr.
+#define PGLUE_B_REG_MPS_ATTN_CLR                                                                             0x2aae94UL //Access:W    DataWidth:0x10   // MPS attention dirty bit clear. MCP writes 1 to a bit in this register in order to clear the corresponding bit in mps_attn register.
+#define PGLUE_B_REG_VPD_REQUEST_PF_31_0                                                                      0x2aae98UL //Access:R    DataWidth:0x10   // VPD request attention dirty bits for all PFs. Each bit indicates that the VPD register of the corresponding PF was set. Set by PXP. Reset by MCP according to VPD flow (write to 0x2430). Note: register contains bits from both paths.
+#define PGLUE_B_REG_PATH_IN_D3_MASK                                                                          0x2aae9cUL //Access:RW   DataWidth:0x10   // This register controls the path_in_d3 output to CPMU. Each bit corresponds to a PF in the path. A value of 0 indicates the power state of this PF is not taken into account when determining path_in_d3 output.  A value of 1 indicates the power state of this PF is taken into account
+#define PGLUE_B_REG_VF_BAR_PRIVILEGE                                                                         0x2aaea0UL //Access:RW   DataWidth:0x2    // This register determines the GRC privilege level for VF BAR accesses.
+#define PGLUE_B_REG_PF_BAR_PRIVILEGE                                                                         0x2aaea4UL //Access:RW   DataWidth:0x2    // This register determines the GRC privilege level for PF BAR accesses.
+#define PGLUE_B_REG_PCI_CONFIG_PRIVILEGE                                                                     0x2aaea8UL //Access:RW   DataWidth:0x2    // This register determines the GRC privilege level for PCI config space accesses.
+#define PGLUE_B_REG_STICKY_MASTER_ERROR_EN                                                                   0x2aaeacUL //Access:RW   DataWidth:0x1    // Value of 1 indicates that was_error should be set when BME or fid_enabled bits are cleared for master request.
+#define PGLUE_B_REG_CFG_NO_L1_ON_INT_K2_E5                                                                   0x2aaeb0UL //Access:RW   DataWidth:0x1    // Chicken bit to disable app_xfer_pending.
+#define PGLUE_B_REG_VF_BAR0_SIZE_K2_E5                                                                       0x2aaeb4UL //Access:RW   DataWidth:0x4    // For Coupled Mode Teaming. The driver should read BAR2_SIZE_OF_VF from PCIe IP config space (bits 11:8 in PCIE_REG_PCIER_REG_VF_BAR_REG) and configure to this register. Decoding: 0 2K; 1 4K; 2 8K; up to 15 64M
+#define PGLUE_B_REG_PF_ROM_SIZE_K2_E5                                                                        0x2aaeb8UL //Access:RW   DataWidth:0x4    // For Coupled Mode Teaming. The driver should read ROM_SIZE_OF_PF from PCIe IP config space (bits 11:8 in PCIE_REG_PCIER_REG_VF_BAR_REG) and configure to this register. Decoding: 0 2k; 1 4K; 2 8K; up to 15 64M
+#define PGLUE_B_REG_MCTP_MAX_LENGTH_K2_E5                                                                    0x2aaebcUL //Access:RW   DataWidth:0xa    // MCTP MAX lENGTH register If the packet is larger than MAX LENGTH Then the packet will be discard.
+#define PGLUE_B_REG_MCTP_REQID_K2_E5                                                                         0x2aaec0UL //Access:RW   DataWidth:0x10   // Request id register for MCTP
+#define PGLUE_B_REG_CFG_VPD_END_K2_E5                                                                        0x2aaec4UL //Access:W    DataWidth:0x10   // VPD END Register
+#define PGLUE_B_REG_PBUS_NUM_K2_E5                                                                           0x2aaec8UL //Access:R    DataWidth:0x8    // PBUS number
+#define PGLUE_B_REG_PBUS_DEV_NUM_K2_E5                                                                       0x2aaeccUL //Access:R    DataWidth:0x5    // PBUS DEV NUM set for MCTP check
+#define PGLUE_B_REG_POISON_DISCARD_MCMPL_K2_E5                                                               0x2aaed0UL //Access:RW   DataWidth:0x1    // Discard when poisoned for MCTP packet
+#define PGLUE_B_REG_BUS_CHECK_ENABLE_K2_E5                                                                   0x2aaed4UL //Access:RW   DataWidth:0x1    // PBUS bus_check_enable Its for MCTP
+#define PGLUE_B_REG_DEVICE_CHECK_ENABLE_K2_E5                                                                0x2aaed8UL //Access:RW   DataWidth:0x1    // PBUS device check enable Its for MCTP packet
+#define PGLUE_B_REG_MCTP_TD_NOT_DROP_K2_E5                                                                   0x2aaedcUL //Access:RW   DataWidth:0x1    // enable drop packet when TD is 1
+#define PGLUE_B_REG_MCTP_REQID_FLREN_K2_E5                                                                   0x2aaee0UL //Access:RW   DataWidth:0x2    // enable MCTP REQID reuest enable
+#define PGLUE_B_REG_TXR_B2B_DISABLE_K2_E5                                                                    0x2aaee4UL //Access:RW   DataWidth:0x1    // Disable master read back 2 back transition IT's checken bit for perfomance improvement If this register is set then b2b transfer will be disable like BB
+#define PGLUE_B_REG_MRRS_ATTN_K2_E5                                                                          0x2aaee8UL //Access:R    DataWidth:0x10   // mrrs attn register It's the indicator for MRRS attn
+#define PGLUE_B_REG_MRRS_ATTN_CLR_K2_E5                                                                      0x2aaeecUL //Access:W    DataWidth:0x10   // mrrs attn clear set register if these bits set, then we will clear MRRS attn
+#define PGLUE_B_REG_TXW_B2B_DISABLE_K2_E5                                                                    0x2aaef0UL //Access:RW   DataWidth:0x1    // Disable master write back 2 back transition
+#define PGLUE_B_REG_ERROR_REG_K2_E5                                                                          0x2aaef4UL //Access:R    DataWidth:0xc    // Error log for dllp abort bit8 to 11 pfid bit0 to 7  tag
+#define PGLUE_B_REG_FLR_INVALIDATE_DISABLE_K2_E5                                                             0x2aaef8UL //Access:RW   DataWidth:0x1    // Disable FLR Invalidate process
+#define PGLUE_B_REG_INVALIDATE_TAGS_EN_K2_E5                                                                 0x2aaefcUL //Access:RW   DataWidth:0x1    // Enable invalidate tag
+#define PGLUE_B_REG_DBI_ERR_K2_E5                                                                            0x2aaf00UL //Access:R    DataWidth:0x20   // Indicates there was an error in DBI Dbi_error_attn                    Bit0 Dbi_wr                            Bit4 to Bit1 pcie_pgl_dbi_addr                 Bit17 to Bit5 Dbi_func_num                      Bit21 to Bit18 Dbi_vfunc_active                  Bit22 Dbi_vfunc_num                     Bit30 to Bit23
+#define PGLUE_B_REG_DBI_ERR_DATA_K2_E5                                                                       0x2aaf04UL //Access:R    DataWidth:0x20   // DBI Error data information
+#define PGLUE_B_REG_DISABLE_POWER_STATE_CHECK_K2_E5                                                          0x2aaf08UL //Access:RW   DataWidth:0x1    // Power state check disable register If its 0 Then we will do power state check
+#define PGLUE_B_REG_PGL_PM_DSTATE_31_0_K2_E5                                                                 0x2aaf0cUL //Access:R    DataWidth:0x20   // DBI Error data information
+#define PGLUE_B_REG_PGL_PM_DSTATE_47_32_K2_E5                                                                0x2aaf10UL //Access:R    DataWidth:0x10   // pm_dstate 47-032
+#define PGLUE_B_REG_CHECK_TC_ON_ERR_K2_E5                                                                    0x2aaf5cUL //Access:RW   DataWidth:0x1    // check tc on error Its config register if check tc on error = 0 Then we will not check TC If check tc on error =1. we need check if TC = x000
+#define PGLUE_B_REG_FLR_INVALIDATE_IN_PROGRESS_VF_31_0_K2_E5                                                 0x2aaf60UL //Access:R    DataWidth:0x20   // FLR Invalidate in progress vf 31-0
+#define PGLUE_B_REG_FLR_INVALIDATE_IN_PROGRESS_VF_63_32_K2_E5                                                0x2aaf64UL //Access:R    DataWidth:0x20   // FLR Invalidate in progress vf 63 -32
+#define PGLUE_B_REG_FLR_INVALIDATE_IN_PROGRESS_VF_95_64_K2_E5                                                0x2aaf68UL //Access:R    DataWidth:0x20   // FLR Invalidate in progress vf 95 - 64
+#define PGLUE_B_REG_FLR_INVALIDATE_IN_PROGRESS_VF_127_96_K2_E5                                               0x2aaf6cUL //Access:R    DataWidth:0x20   // FLR Invalidate in progress vf 127 - 96
+#define PGLUE_B_REG_FLR_INVALIDATE_IN_PROGRESS_VF_159_128_K2_E5                                              0x2aaf70UL //Access:R    DataWidth:0x20   // FLR Invalidate in progress vf 159-128
+#define PGLUE_B_REG_FLR_INVALIDATE_IN_PROGRESS_VF_191_160_K2_E5                                              0x2aaf74UL //Access:R    DataWidth:0x20   // FLR Invalidate in progress vf 191 to 160
+#define PGLUE_B_REG_FLR_INVALIDATE_IN_PROGRESS_PF_31_0_K2_E5                                                 0x2aaf78UL //Access:R    DataWidth:0x10   // FLR Invalidate in progress pf 31 to 0
+#define PGLUE_B_REG_EXT_TAG_MODE_K2_E5                                                                       0x2aaf7cUL //Access:RW   DataWidth:0x2    // Extand tag mode 00 default mode 01 BB mode 10 Read mode
+#define PGLUE_B_REG_MCTP_ERR1_K2_E5                                                                          0x2aaf80UL //Access:R    DataWidth:0x20   // Indicates there was an error in MCTP BIt 21-30 Message code Bit 7-22  Vender ID Bit 3-6   TAG Bit 0-2   TC
+#define PGLUE_B_REG_MCTP_ERR2_K2_E5                                                                          0x2aaf84UL //Access:R    DataWidth:0x20   // Indicates there was an error in MCTP Bit 21-30 Length Bit 5-20  PCIE REQ ID Bit 0-4   TYPE
+#define PGLUE_B_REG_ERROR_ECRC_REG_K2_E5                                                                     0x2aaf88UL //Access:R    DataWidth:0xc    // Error log for ecrc abort bit8 to 11 pfid bit0 to 7  tag
+#define PGLUE_B_REG_ERROR_TLP_REG_K2_E5                                                                      0x2aaf8cUL //Access:R    DataWidth:0xc    // Error log for tlp abort bit8 to 11 pfid bit0 to 7  tag
+#define PGLUE_B_REG_ERROR_POISON_REG_K2_E5                                                                   0x2aaf90UL //Access:R    DataWidth:0xc    // Error log for poison bit8 to 11 pfid bit0 to 7  tag
+#define PGLUE_B_REG_MCTP_VENDERID_CHK_DISABLE_K2_E5                                                          0x2aaf94UL //Access:RW   DataWidth:0x1    // Disable vendorid check in MCTP
+#define PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5                                                                     0x2aaf98UL //Access:RW   DataWidth:0x20   // GRC address for configuration access to PCIE config address 0xe8. any write to this PCIE address will cause a GRC write access to the address that's in t this register. E4: split16.
+#define PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5                                                                     0x2aaf9cUL //Access:RW   DataWidth:0x20   // GRC address for configuration access to PCIE config address 0xec.  any write to this PCIE address will cause a GRC write access to the address that's in t this register. E4: split16.
+#define PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5                                                                     0x2aafa0UL //Access:RW   DataWidth:0x20   // GRC address for configuration access to PCIE config address 0xf0.  any write to this PCIE address will cause a GRC write access to the address that's in t this register. E4: split16.
+#define PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5                                                                     0x2aafa4UL //Access:RW   DataWidth:0x20   // GRC address for configuration access to PCIE config address 0xf4.  any write to this PCIE address will cause a GRC write access to the address that's in t this register. E4: split16.
+#define PGLUE_B_REG_EXT_TAG_EN_PF_31_0_K2_E5                                                                 0x2aafa8UL //Access:R    DataWidth:0x20   // Extended tag enable per PF
+#define PGLUE_B_REG_NO_SNOOP_EN_PF_31_0_K2_E5                                                                0x2aafacUL //Access:R    DataWidth:0x10   // No snoop enable per PF
+#define PGLUE_B_REG_RELAXED_ORDERING_EN_PF_31_0_K2_E5                                                        0x2aafb0UL //Access:R    DataWidth:0x10   // Relaxed ordering enable per PF
+#define PGLUE_B_REG_DISCARD_HEADER_UNKNOWN_K2_E5                                                             0x2aafb4UL //Access:RW   DataWidth:0x1    // 0 - Don't discard target request with unknown header type 1 - Discard target request with unknown header type
+#define PGLUE_B_REG_COMPARE_CPL_FUNCTION_K2_E5                                                               0x2aafb8UL //Access:RW   DataWidth:0x1    // 0 - Don't compare the function received in the completion to the original MRD function. 1 - Compare the function received in the completion to the original MRD function. Discard the completion if the comparison fails.
+#define PGLUE_B_REG_DISABLE_B2B_K2_E5                                                                        0x2aafbcUL //Access:RW   DataWidth:0x1    // 0 - Enable b2b pop from sync fifos in pgl_pci_core_rx. 1 - Disable b2b pop from sync fifos in pgl_pci_core_rx (chicken bit).
+#define PGLUE_B_REG_DISCARD_MASTER_REQUEST_IN_FLR_K2_E5                                                      0x2aafc0UL //Access:RW   DataWidth:0x1    // 0 - Don't discard master request during FLR 1 - Discard master request during FLR
+#define PGLUE_B_REG_SYNCFIFO_PUSH_OVERFLOW_K2_E5                                                             0x2aafc4UL //Access:R    DataWidth:0x4    // 0 - TXCPL sync fifo push overflow 1 - TXR sync fifo push overflow 2 - TXW header sync fifo push overflow 3 - TXW data sync fifo push overflow
+#define PGLUE_B_REG_SYNCFIFO_POP_UNDERFLOW_K2_E5                                                             0x2aafc8UL //Access:R    DataWidth:0x6    // 0 - RX target read and config sync fifo pop underflow 1 - RX header sync fifo pop underflow 5:2 - RX data sync fifo pop underflow (1 bit per each 128b instance)
+#define PGLUE_B_REG_RXH_SYNCFIFO_POP_STATUS_K2_E5                                                            0x2aafccUL //Access:R    DataWidth:0x12   // 8:0 -  RX target read and config sync fifo pop status 17:9 - RX header sync fifo pop status
+#define PGLUE_B_REG_RXD_SYNCFIFO_POP_STATUS_K2_E5                                                            0x2aafd0UL //Access:R    DataWidth:0x1c   // RX data sync fifo pop status (7 bit per each 128b instance)
+#define TM_REG_MEMORY_SELF_INIT_START                                                                        0x2c0000UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define TM_REG_MEMORY_SELF_INIT_START_CONTEXT_MEM_SELF_INIT_START                                          (0x1<<0) // Reset the context memory. When set, the context memory self init starts.
+  #define TM_REG_MEMORY_SELF_INIT_START_CONTEXT_MEM_SELF_INIT_START_SHIFT                                    0
+  #define TM_REG_MEMORY_SELF_INIT_START_CONFIG_CONN_MEM_SELF_INIT_START                                      (0x1<<1) // Reset the config conn memory. When set, the config conn memory self init starts.
+  #define TM_REG_MEMORY_SELF_INIT_START_CONFIG_CONN_MEM_SELF_INIT_START_SHIFT                                1
+  #define TM_REG_MEMORY_SELF_INIT_START_CONFIG_TASK_MEM_SELF_INIT_START                                      (0x1<<2) // Reset the config task memory. When set, the config task memory self init starts.
+  #define TM_REG_MEMORY_SELF_INIT_START_CONFIG_TASK_MEM_SELF_INIT_START_SHIFT                                2
+  #define TM_REG_MEMORY_SELF_INIT_START_PRE_SCAN_MEM_SELF_INIT_START                                         (0x1<<3) // Reset the pre scan memory. When set, the pre scan memory self init starts.
+  #define TM_REG_MEMORY_SELF_INIT_START_PRE_SCAN_MEM_SELF_INIT_START_SHIFT                                   3
+#define TM_REG_CONTEXT_MEM_SELF_INIT_DONE                                                                    0x2c0004UL //Access:R    DataWidth:0x1    // When set, the self init for the context memory is done. TBD - need to change to read, all the bits.
+#define TM_REG_CONFIG_CONN_MEM_SELF_INIT_DONE                                                                0x2c0008UL //Access:R    DataWidth:0x1    // When set, the self init for the config conn memory is done.
+#define TM_REG_CONFIG_TASK_MEM_SELF_INIT_DONE                                                                0x2c000cUL //Access:R    DataWidth:0x1    // When set, the self init for the config task memory is done.
+#define TM_REG_PRE_SCAN_MEM_SELF_INIT_DONE                                                                   0x2c0010UL //Access:R    DataWidth:0x1    // When set, the self init for the pre scan memory is done.
+#define TM_REG_PXP_READ_DATA_FIFO_INIT                                                                       0x2c0014UL //Access:RW   DataWidth:0x1    // When set init the PXP READ DATA FIFO.
+#define TM_REG_PXP_READ_CTRL_FIFO_INIT                                                                       0x2c0018UL //Access:RW   DataWidth:0x1    // When set init the PXP READ CTRL FIFO.
+#define TM_REG_CFC_LOAD_COMMAND_FIFO_INIT                                                                    0x2c001cUL //Access:RW   DataWidth:0x1    // When set init the CFC LOAD COMMAND FIFO.
+#define TM_REG_CFC_LOAD_ECHO_FIFO_INIT                                                                       0x2c0020UL //Access:RW   DataWidth:0x1    // When set init the CFC LOAD ECHO FIFO.
+#define TM_REG_CLIENT_OUT_FIFO_INIT                                                                          0x2c0024UL //Access:RW   DataWidth:0x1    // When set init the CLIENT OUT FIFO.
+#define TM_REG_CLIENT_IN_PBF_FIFO_INIT                                                                       0x2c0028UL //Access:RW   DataWidth:0x1    // When set init the CLIENT IN PBF FIFO.
+#define TM_REG_CLIENT_IN_XCM_FIFO_INIT                                                                       0x2c002cUL //Access:RW   DataWidth:0x1    // When set init the CLIENT IN XCM FIFO.
+#define TM_REG_CLIENT_IN_TCM_FIFO_INIT                                                                       0x2c0030UL //Access:RW   DataWidth:0x1    // When set init the CLIENT IN TCM FIFO.
+#define TM_REG_CLIENT_IN_UCM_FIFO_INIT                                                                       0x2c0034UL //Access:RW   DataWidth:0x1    // When set init the CLIENT IN UCM FIFO.
+#define TM_REG_EXPIRATION_CMD_FIFO_INIT                                                                      0x2c0038UL //Access:RW   DataWidth:0x1    // When set init the EXPIRATION COMMAND FIFO.
+#define TM_REG_AC_COMMAND_FIFO_INIT                                                                          0x2c003cUL //Access:RW   DataWidth:0x1    // When set init the AC COMMAND FIFO.
+#define TM_REG_PXP_INTERFACE_ENABLE                                                                          0x2c0060UL //Access:RW   DataWidth:0x1    // Enable pxp request, wr and rd interfaces.
+#define TM_REG_CFC_INTERFACE_ENABLE                                                                          0x2c0064UL //Access:RW   DataWidth:0x1    // Enable cfc load request and load response interfaces.
+#define TM_REG_CLIENT_OUT_INTERFACE_ENABLE                                                                   0x2c0068UL //Access:RW   DataWidth:0x1    // Enable client out interfaces (XCM, UCM, TCM).
+#define TM_REG_CLIENT_IN_INTERFACE_ENABLE                                                                    0x2c006cUL //Access:RW   DataWidth:0x1    // Enable client in interfaces (XCM, UCM, TCM, PBF).
+#define TM_REG_PXP_REQUEST_CREDIT                                                                            0x2c0078UL //Access:RW   DataWidth:0x2    // Credit for the PXP request interface.
+#define TM_REG_CLIENT_OUT_XCM_REQ_CREDIT                                                                     0x2c007cUL //Access:RW   DataWidth:0x3    // Credit for the XCM client out request interface.
+#define TM_REG_CLIENT_OUT_TCM_REQ_CREDIT                                                                     0x2c0080UL //Access:RW   DataWidth:0x3    // Credit for the TCM client out request interface.
+#define TM_REG_CLIENT_OUT_UCM_REQ_CREDIT                                                                     0x2c0084UL //Access:RW   DataWidth:0x3    // Credit for the UCM client out request interface.
+#define TM_REG_LOAD_REQUEST_CREDIT                                                                           0x2c0088UL //Access:RW   DataWidth:0x4    // Credit for the CFC load requests. Common for both tasks and connections and equal to the Expiration FIFO row size.                          The number of allowed CFC load requests since they are sent to the CCFC/TCFC till they are read from the Expiration FIFO                           (after CFC load request is received) is less or equal to this credit.                          Value of 0: this credit is disabled.
+#define TM_REG_INT_STS_0                                                                                     0x2c0180UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define TM_REG_INT_STS_0_ADDRESS_ERROR                                                                     (0x1<<0) // Signals an unknown address to the rf module.
+  #define TM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                               0
+  #define TM_REG_INT_STS_0_PXP_READ_DATA_FIFO_OV                                                             (0x1<<1) // PXP READ DATA FIFO Overflow.
+  #define TM_REG_INT_STS_0_PXP_READ_DATA_FIFO_OV_SHIFT                                                       1
+  #define TM_REG_INT_STS_0_PXP_READ_DATA_FIFO_UN                                                             (0x1<<2) // PXP READ DATA FIFO Underrun.
+  #define TM_REG_INT_STS_0_PXP_READ_DATA_FIFO_UN_SHIFT                                                       2
+  #define TM_REG_INT_STS_0_PXP_READ_CTRL_FIFO_OV                                                             (0x1<<3) // PXP READ CTRL FIFO Overflow.
+  #define TM_REG_INT_STS_0_PXP_READ_CTRL_FIFO_OV_SHIFT                                                       3
+  #define TM_REG_INT_STS_0_PXP_READ_CTRL_FIFO_UN                                                             (0x1<<4) // PXP READ CTRL FIFO Underrun.
+  #define TM_REG_INT_STS_0_PXP_READ_CTRL_FIFO_UN_SHIFT                                                       4
+  #define TM_REG_INT_STS_0_CFC_LOAD_COMMAND_FIFO_OV                                                          (0x1<<5) // CFC LOAD COMMAND FIFO Overflow.
+  #define TM_REG_INT_STS_0_CFC_LOAD_COMMAND_FIFO_OV_SHIFT                                                    5
+  #define TM_REG_INT_STS_0_CFC_LOAD_COMMAND_FIFO_UN                                                          (0x1<<6) // CFC LOAD COMMAND FIFO Underrun.
+  #define TM_REG_INT_STS_0_CFC_LOAD_COMMAND_FIFO_UN_SHIFT                                                    6
+  #define TM_REG_INT_STS_0_CFC_LOAD_ECHO_FIFO_OV                                                             (0x1<<7) // CFC LOAD ECHO FIFO Overflow.
+  #define TM_REG_INT_STS_0_CFC_LOAD_ECHO_FIFO_OV_SHIFT                                                       7
+  #define TM_REG_INT_STS_0_CFC_LOAD_ECHO_FIFO_UN                                                             (0x1<<8) // CFC LOAD ECHO FIFO Underrun.
+  #define TM_REG_INT_STS_0_CFC_LOAD_ECHO_FIFO_UN_SHIFT                                                       8
+  #define TM_REG_INT_STS_0_CLIENT_OUT_FIFO_OV                                                                (0x1<<9) // CLIENT OUT FIFO Overflow.
+  #define TM_REG_INT_STS_0_CLIENT_OUT_FIFO_OV_SHIFT                                                          9
+  #define TM_REG_INT_STS_0_CLIENT_OUT_FIFO_UN                                                                (0x1<<10) // CLIENT OUT FIFO Underrun.
+  #define TM_REG_INT_STS_0_CLIENT_OUT_FIFO_UN_SHIFT                                                          10
+  #define TM_REG_INT_STS_0_AC_COMMAND_FIFO_OV                                                                (0x1<<11) // AC COMMAND FIFO Overflow.
+  #define TM_REG_INT_STS_0_AC_COMMAND_FIFO_OV_SHIFT                                                          11
+  #define TM_REG_INT_STS_0_AC_COMMAND_FIFO_UN                                                                (0x1<<12) // AC COMMAND FIFO Underrun.
+  #define TM_REG_INT_STS_0_AC_COMMAND_FIFO_UN_SHIFT                                                          12
+  #define TM_REG_INT_STS_0_CLIENT_IN_PBF_FIFO_OV                                                             (0x1<<13) // CLIENT IN PBF FIFO Overflow.
+  #define TM_REG_INT_STS_0_CLIENT_IN_PBF_FIFO_OV_SHIFT                                                       13
+  #define TM_REG_INT_STS_0_CLIENT_IN_PBF_FIFO_UN                                                             (0x1<<14) // CLIENT IN PBF FIFO Underrun.
+  #define TM_REG_INT_STS_0_CLIENT_IN_PBF_FIFO_UN_SHIFT                                                       14
+  #define TM_REG_INT_STS_0_CLIENT_IN_UCM_FIFO_OV                                                             (0x1<<15) // CLIENT IN UCM FIFO Overflow.
+  #define TM_REG_INT_STS_0_CLIENT_IN_UCM_FIFO_OV_SHIFT                                                       15
+  #define TM_REG_INT_STS_0_CLIENT_IN_UCM_FIFO_UN                                                             (0x1<<16) // CLIENT IN UCM FIFO Underun.
+  #define TM_REG_INT_STS_0_CLIENT_IN_UCM_FIFO_UN_SHIFT                                                       16
+  #define TM_REG_INT_STS_0_CLIENT_IN_TCM_FIFO_OV                                                             (0x1<<17) // CLIENT IN TCM FIFO Overflow.
+  #define TM_REG_INT_STS_0_CLIENT_IN_TCM_FIFO_OV_SHIFT                                                       17
+  #define TM_REG_INT_STS_0_CLIENT_IN_TCM_FIFO_UN                                                             (0x1<<18) // CLIENT IN TCM FIFO Underrun.
+  #define TM_REG_INT_STS_0_CLIENT_IN_TCM_FIFO_UN_SHIFT                                                       18
+  #define TM_REG_INT_STS_0_CLIENT_IN_XCM_FIFO_OV                                                             (0x1<<19) // CLIENT IN XCM FIFO Overflow.
+  #define TM_REG_INT_STS_0_CLIENT_IN_XCM_FIFO_OV_SHIFT                                                       19
+  #define TM_REG_INT_STS_0_CLIENT_IN_XCM_FIFO_UN                                                             (0x1<<20) // CLIENT IN XCM FIFO Underrun.
+  #define TM_REG_INT_STS_0_CLIENT_IN_XCM_FIFO_UN_SHIFT                                                       20
+  #define TM_REG_INT_STS_0_EXPIRATION_CMD_FIFO_OV                                                            (0x1<<21) // EXPIRATION COMMAND FIFO Overflow.
+  #define TM_REG_INT_STS_0_EXPIRATION_CMD_FIFO_OV_SHIFT                                                      21
+  #define TM_REG_INT_STS_0_EXPIRATION_CMD_FIFO_UN                                                            (0x1<<22) // EXPIRATION COMMAND FIFO Underrun.
+  #define TM_REG_INT_STS_0_EXPIRATION_CMD_FIFO_UN_SHIFT                                                      22
+  #define TM_REG_INT_STS_0_STOP_ALL_LC_INVALID                                                               (0x1<<23) // STOP_ALL_TIMERS command and the logical client is invalid.
+  #define TM_REG_INT_STS_0_STOP_ALL_LC_INVALID_SHIFT                                                         23
+  #define TM_REG_INT_STS_0_COMMAND_LC_INVALID_0                                                              (0x1<<24) // SET/CLEAR/FORCE CLEAR command and the logical client invalid and one of the other logical clients is valid.
+  #define TM_REG_INT_STS_0_COMMAND_LC_INVALID_0_SHIFT                                                        24
+  #define TM_REG_INT_STS_0_COMMAND_LC_INVALID_1                                                              (0x1<<25) // SET/CLEAR/FORCE CLEAR command and the logical client is invalid and the other logical clients are also invalid.
+  #define TM_REG_INT_STS_0_COMMAND_LC_INVALID_1_SHIFT                                                        25
+  #define TM_REG_INT_STS_0_INIT_COMMAND_LC_VALID                                                             (0x1<<26) // INIT command and the logical client valid bit is asserted.
+  #define TM_REG_INT_STS_0_INIT_COMMAND_LC_VALID_SHIFT                                                       26
+  #define TM_REG_INT_STS_0_STOP_ALL_EXP_LC_VALID                                                             (0x1<<27) // Stop all expiration and the valid of one of the logical clients is asserted.
+  #define TM_REG_INT_STS_0_STOP_ALL_EXP_LC_VALID_SHIFT                                                       27
+  #define TM_REG_INT_STS_0_COMMAND_CID_INVALID_0                                                             (0x1<<28) // Command with C/TID > 64K or VF TID segment not zero.
+  #define TM_REG_INT_STS_0_COMMAND_CID_INVALID_0_SHIFT                                                       28
+  #define TM_REG_INT_STS_0_RESERVED_COMMAND                                                                  (0x1<<29) // RESERVED command.
+  #define TM_REG_INT_STS_0_RESERVED_COMMAND_SHIFT                                                            29
+  #define TM_REG_INT_STS_0_COMMAND_CID_INVALID_1                                                             (0x1<<30) // Command arrived to the host handler unit with CID/TID > Num_of_timers for that function.
+  #define TM_REG_INT_STS_0_COMMAND_CID_INVALID_1_SHIFT                                                       30
+  #define TM_REG_INT_STS_0_CLOAD_RES_LOADERR_CONN                                                            (0x1<<31) // Connections Load response with Load Error.
+  #define TM_REG_INT_STS_0_CLOAD_RES_LOADERR_CONN_SHIFT                                                      31
+#define TM_REG_INT_MASK_0                                                                                    0x2c0184UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define TM_REG_INT_MASK_0_ADDRESS_ERROR                                                                    (0x1<<0) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.ADDRESS_ERROR .
+  #define TM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                              0
+  #define TM_REG_INT_MASK_0_PXP_READ_DATA_FIFO_OV                                                            (0x1<<1) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.PXP_READ_DATA_FIFO_OV .
+  #define TM_REG_INT_MASK_0_PXP_READ_DATA_FIFO_OV_SHIFT                                                      1
+  #define TM_REG_INT_MASK_0_PXP_READ_DATA_FIFO_UN                                                            (0x1<<2) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.PXP_READ_DATA_FIFO_UN .
+  #define TM_REG_INT_MASK_0_PXP_READ_DATA_FIFO_UN_SHIFT                                                      2
+  #define TM_REG_INT_MASK_0_PXP_READ_CTRL_FIFO_OV                                                            (0x1<<3) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.PXP_READ_CTRL_FIFO_OV .
+  #define TM_REG_INT_MASK_0_PXP_READ_CTRL_FIFO_OV_SHIFT                                                      3
+  #define TM_REG_INT_MASK_0_PXP_READ_CTRL_FIFO_UN                                                            (0x1<<4) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.PXP_READ_CTRL_FIFO_UN .
+  #define TM_REG_INT_MASK_0_PXP_READ_CTRL_FIFO_UN_SHIFT                                                      4
+  #define TM_REG_INT_MASK_0_CFC_LOAD_COMMAND_FIFO_OV                                                         (0x1<<5) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CFC_LOAD_COMMAND_FIFO_OV .
+  #define TM_REG_INT_MASK_0_CFC_LOAD_COMMAND_FIFO_OV_SHIFT                                                   5
+  #define TM_REG_INT_MASK_0_CFC_LOAD_COMMAND_FIFO_UN                                                         (0x1<<6) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CFC_LOAD_COMMAND_FIFO_UN .
+  #define TM_REG_INT_MASK_0_CFC_LOAD_COMMAND_FIFO_UN_SHIFT                                                   6
+  #define TM_REG_INT_MASK_0_CFC_LOAD_ECHO_FIFO_OV                                                            (0x1<<7) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CFC_LOAD_ECHO_FIFO_OV .
+  #define TM_REG_INT_MASK_0_CFC_LOAD_ECHO_FIFO_OV_SHIFT                                                      7
+  #define TM_REG_INT_MASK_0_CFC_LOAD_ECHO_FIFO_UN                                                            (0x1<<8) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CFC_LOAD_ECHO_FIFO_UN .
+  #define TM_REG_INT_MASK_0_CFC_LOAD_ECHO_FIFO_UN_SHIFT                                                      8
+  #define TM_REG_INT_MASK_0_CLIENT_OUT_FIFO_OV                                                               (0x1<<9) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_OUT_FIFO_OV .
+  #define TM_REG_INT_MASK_0_CLIENT_OUT_FIFO_OV_SHIFT                                                         9
+  #define TM_REG_INT_MASK_0_CLIENT_OUT_FIFO_UN                                                               (0x1<<10) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_OUT_FIFO_UN .
+  #define TM_REG_INT_MASK_0_CLIENT_OUT_FIFO_UN_SHIFT                                                         10
+  #define TM_REG_INT_MASK_0_AC_COMMAND_FIFO_OV                                                               (0x1<<11) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.AC_COMMAND_FIFO_OV .
+  #define TM_REG_INT_MASK_0_AC_COMMAND_FIFO_OV_SHIFT                                                         11
+  #define TM_REG_INT_MASK_0_AC_COMMAND_FIFO_UN                                                               (0x1<<12) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.AC_COMMAND_FIFO_UN .
+  #define TM_REG_INT_MASK_0_AC_COMMAND_FIFO_UN_SHIFT                                                         12
+  #define TM_REG_INT_MASK_0_CLIENT_IN_PBF_FIFO_OV                                                            (0x1<<13) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_IN_PBF_FIFO_OV .
+  #define TM_REG_INT_MASK_0_CLIENT_IN_PBF_FIFO_OV_SHIFT                                                      13
+  #define TM_REG_INT_MASK_0_CLIENT_IN_PBF_FIFO_UN                                                            (0x1<<14) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_IN_PBF_FIFO_UN .
+  #define TM_REG_INT_MASK_0_CLIENT_IN_PBF_FIFO_UN_SHIFT                                                      14
+  #define TM_REG_INT_MASK_0_CLIENT_IN_UCM_FIFO_OV                                                            (0x1<<15) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_IN_UCM_FIFO_OV .
+  #define TM_REG_INT_MASK_0_CLIENT_IN_UCM_FIFO_OV_SHIFT                                                      15
+  #define TM_REG_INT_MASK_0_CLIENT_IN_UCM_FIFO_UN                                                            (0x1<<16) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_IN_UCM_FIFO_UN .
+  #define TM_REG_INT_MASK_0_CLIENT_IN_UCM_FIFO_UN_SHIFT                                                      16
+  #define TM_REG_INT_MASK_0_CLIENT_IN_TCM_FIFO_OV                                                            (0x1<<17) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_IN_TCM_FIFO_OV .
+  #define TM_REG_INT_MASK_0_CLIENT_IN_TCM_FIFO_OV_SHIFT                                                      17
+  #define TM_REG_INT_MASK_0_CLIENT_IN_TCM_FIFO_UN                                                            (0x1<<18) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_IN_TCM_FIFO_UN .
+  #define TM_REG_INT_MASK_0_CLIENT_IN_TCM_FIFO_UN_SHIFT                                                      18
+  #define TM_REG_INT_MASK_0_CLIENT_IN_XCM_FIFO_OV                                                            (0x1<<19) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_IN_XCM_FIFO_OV .
+  #define TM_REG_INT_MASK_0_CLIENT_IN_XCM_FIFO_OV_SHIFT                                                      19
+  #define TM_REG_INT_MASK_0_CLIENT_IN_XCM_FIFO_UN                                                            (0x1<<20) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_IN_XCM_FIFO_UN .
+  #define TM_REG_INT_MASK_0_CLIENT_IN_XCM_FIFO_UN_SHIFT                                                      20
+  #define TM_REG_INT_MASK_0_EXPIRATION_CMD_FIFO_OV                                                           (0x1<<21) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.EXPIRATION_CMD_FIFO_OV .
+  #define TM_REG_INT_MASK_0_EXPIRATION_CMD_FIFO_OV_SHIFT                                                     21
+  #define TM_REG_INT_MASK_0_EXPIRATION_CMD_FIFO_UN                                                           (0x1<<22) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.EXPIRATION_CMD_FIFO_UN .
+  #define TM_REG_INT_MASK_0_EXPIRATION_CMD_FIFO_UN_SHIFT                                                     22
+  #define TM_REG_INT_MASK_0_STOP_ALL_LC_INVALID                                                              (0x1<<23) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.STOP_ALL_LC_INVALID .
+  #define TM_REG_INT_MASK_0_STOP_ALL_LC_INVALID_SHIFT                                                        23
+  #define TM_REG_INT_MASK_0_COMMAND_LC_INVALID_0                                                             (0x1<<24) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.COMMAND_LC_INVALID_0 .
+  #define TM_REG_INT_MASK_0_COMMAND_LC_INVALID_0_SHIFT                                                       24
+  #define TM_REG_INT_MASK_0_COMMAND_LC_INVALID_1                                                             (0x1<<25) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.COMMAND_LC_INVALID_1 .
+  #define TM_REG_INT_MASK_0_COMMAND_LC_INVALID_1_SHIFT                                                       25
+  #define TM_REG_INT_MASK_0_INIT_COMMAND_LC_VALID                                                            (0x1<<26) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.INIT_COMMAND_LC_VALID .
+  #define TM_REG_INT_MASK_0_INIT_COMMAND_LC_VALID_SHIFT                                                      26
+  #define TM_REG_INT_MASK_0_STOP_ALL_EXP_LC_VALID                                                            (0x1<<27) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.STOP_ALL_EXP_LC_VALID .
+  #define TM_REG_INT_MASK_0_STOP_ALL_EXP_LC_VALID_SHIFT                                                      27
+  #define TM_REG_INT_MASK_0_COMMAND_CID_INVALID_0                                                            (0x1<<28) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.COMMAND_CID_INVALID_0 .
+  #define TM_REG_INT_MASK_0_COMMAND_CID_INVALID_0_SHIFT                                                      28
+  #define TM_REG_INT_MASK_0_RESERVED_COMMAND                                                                 (0x1<<29) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.RESERVED_COMMAND .
+  #define TM_REG_INT_MASK_0_RESERVED_COMMAND_SHIFT                                                           29
+  #define TM_REG_INT_MASK_0_COMMAND_CID_INVALID_1                                                            (0x1<<30) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.COMMAND_CID_INVALID_1 .
+  #define TM_REG_INT_MASK_0_COMMAND_CID_INVALID_1_SHIFT                                                      30
+  #define TM_REG_INT_MASK_0_CLOAD_RES_LOADERR_CONN                                                           (0x1<<31) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLOAD_RES_LOADERR_CONN .
+  #define TM_REG_INT_MASK_0_CLOAD_RES_LOADERR_CONN_SHIFT                                                     31
+#define TM_REG_INT_STS_WR_0                                                                                  0x2c0188UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define TM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define TM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                            0
+  #define TM_REG_INT_STS_WR_0_PXP_READ_DATA_FIFO_OV                                                          (0x1<<1) // PXP READ DATA FIFO Overflow.
+  #define TM_REG_INT_STS_WR_0_PXP_READ_DATA_FIFO_OV_SHIFT                                                    1
+  #define TM_REG_INT_STS_WR_0_PXP_READ_DATA_FIFO_UN                                                          (0x1<<2) // PXP READ DATA FIFO Underrun.
+  #define TM_REG_INT_STS_WR_0_PXP_READ_DATA_FIFO_UN_SHIFT                                                    2
+  #define TM_REG_INT_STS_WR_0_PXP_READ_CTRL_FIFO_OV                                                          (0x1<<3) // PXP READ CTRL FIFO Overflow.
+  #define TM_REG_INT_STS_WR_0_PXP_READ_CTRL_FIFO_OV_SHIFT                                                    3
+  #define TM_REG_INT_STS_WR_0_PXP_READ_CTRL_FIFO_UN                                                          (0x1<<4) // PXP READ CTRL FIFO Underrun.
+  #define TM_REG_INT_STS_WR_0_PXP_READ_CTRL_FIFO_UN_SHIFT                                                    4
+  #define TM_REG_INT_STS_WR_0_CFC_LOAD_COMMAND_FIFO_OV                                                       (0x1<<5) // CFC LOAD COMMAND FIFO Overflow.
+  #define TM_REG_INT_STS_WR_0_CFC_LOAD_COMMAND_FIFO_OV_SHIFT                                                 5
+  #define TM_REG_INT_STS_WR_0_CFC_LOAD_COMMAND_FIFO_UN                                                       (0x1<<6) // CFC LOAD COMMAND FIFO Underrun.
+  #define TM_REG_INT_STS_WR_0_CFC_LOAD_COMMAND_FIFO_UN_SHIFT                                                 6
+  #define TM_REG_INT_STS_WR_0_CFC_LOAD_ECHO_FIFO_OV                                                          (0x1<<7) // CFC LOAD ECHO FIFO Overflow.
+  #define TM_REG_INT_STS_WR_0_CFC_LOAD_ECHO_FIFO_OV_SHIFT                                                    7
+  #define TM_REG_INT_STS_WR_0_CFC_LOAD_ECHO_FIFO_UN                                                          (0x1<<8) // CFC LOAD ECHO FIFO Underrun.
+  #define TM_REG_INT_STS_WR_0_CFC_LOAD_ECHO_FIFO_UN_SHIFT                                                    8
+  #define TM_REG_INT_STS_WR_0_CLIENT_OUT_FIFO_OV                                                             (0x1<<9) // CLIENT OUT FIFO Overflow.
+  #define TM_REG_INT_STS_WR_0_CLIENT_OUT_FIFO_OV_SHIFT                                                       9
+  #define TM_REG_INT_STS_WR_0_CLIENT_OUT_FIFO_UN                                                             (0x1<<10) // CLIENT OUT FIFO Underrun.
+  #define TM_REG_INT_STS_WR_0_CLIENT_OUT_FIFO_UN_SHIFT                                                       10
+  #define TM_REG_INT_STS_WR_0_AC_COMMAND_FIFO_OV                                                             (0x1<<11) // AC COMMAND FIFO Overflow.
+  #define TM_REG_INT_STS_WR_0_AC_COMMAND_FIFO_OV_SHIFT                                                       11
+  #define TM_REG_INT_STS_WR_0_AC_COMMAND_FIFO_UN                                                             (0x1<<12) // AC COMMAND FIFO Underrun.
+  #define TM_REG_INT_STS_WR_0_AC_COMMAND_FIFO_UN_SHIFT                                                       12
+  #define TM_REG_INT_STS_WR_0_CLIENT_IN_PBF_FIFO_OV                                                          (0x1<<13) // CLIENT IN PBF FIFO Overflow.
+  #define TM_REG_INT_STS_WR_0_CLIENT_IN_PBF_FIFO_OV_SHIFT                                                    13
+  #define TM_REG_INT_STS_WR_0_CLIENT_IN_PBF_FIFO_UN                                                          (0x1<<14) // CLIENT IN PBF FIFO Underrun.
+  #define TM_REG_INT_STS_WR_0_CLIENT_IN_PBF_FIFO_UN_SHIFT                                                    14
+  #define TM_REG_INT_STS_WR_0_CLIENT_IN_UCM_FIFO_OV                                                          (0x1<<15) // CLIENT IN UCM FIFO Overflow.
+  #define TM_REG_INT_STS_WR_0_CLIENT_IN_UCM_FIFO_OV_SHIFT                                                    15
+  #define TM_REG_INT_STS_WR_0_CLIENT_IN_UCM_FIFO_UN                                                          (0x1<<16) // CLIENT IN UCM FIFO Underun.
+  #define TM_REG_INT_STS_WR_0_CLIENT_IN_UCM_FIFO_UN_SHIFT                                                    16
+  #define TM_REG_INT_STS_WR_0_CLIENT_IN_TCM_FIFO_OV                                                          (0x1<<17) // CLIENT IN TCM FIFO Overflow.
+  #define TM_REG_INT_STS_WR_0_CLIENT_IN_TCM_FIFO_OV_SHIFT                                                    17
+  #define TM_REG_INT_STS_WR_0_CLIENT_IN_TCM_FIFO_UN                                                          (0x1<<18) // CLIENT IN TCM FIFO Underrun.
+  #define TM_REG_INT_STS_WR_0_CLIENT_IN_TCM_FIFO_UN_SHIFT                                                    18
+  #define TM_REG_INT_STS_WR_0_CLIENT_IN_XCM_FIFO_OV                                                          (0x1<<19) // CLIENT IN XCM FIFO Overflow.
+  #define TM_REG_INT_STS_WR_0_CLIENT_IN_XCM_FIFO_OV_SHIFT                                                    19
+  #define TM_REG_INT_STS_WR_0_CLIENT_IN_XCM_FIFO_UN                                                          (0x1<<20) // CLIENT IN XCM FIFO Underrun.
+  #define TM_REG_INT_STS_WR_0_CLIENT_IN_XCM_FIFO_UN_SHIFT                                                    20
+  #define TM_REG_INT_STS_WR_0_EXPIRATION_CMD_FIFO_OV                                                         (0x1<<21) // EXPIRATION COMMAND FIFO Overflow.
+  #define TM_REG_INT_STS_WR_0_EXPIRATION_CMD_FIFO_OV_SHIFT                                                   21
+  #define TM_REG_INT_STS_WR_0_EXPIRATION_CMD_FIFO_UN                                                         (0x1<<22) // EXPIRATION COMMAND FIFO Underrun.
+  #define TM_REG_INT_STS_WR_0_EXPIRATION_CMD_FIFO_UN_SHIFT                                                   22
+  #define TM_REG_INT_STS_WR_0_STOP_ALL_LC_INVALID                                                            (0x1<<23) // STOP_ALL_TIMERS command and the logical client is invalid.
+  #define TM_REG_INT_STS_WR_0_STOP_ALL_LC_INVALID_SHIFT                                                      23
+  #define TM_REG_INT_STS_WR_0_COMMAND_LC_INVALID_0                                                           (0x1<<24) // SET/CLEAR/FORCE CLEAR command and the logical client invalid and one of the other logical clients is valid.
+  #define TM_REG_INT_STS_WR_0_COMMAND_LC_INVALID_0_SHIFT                                                     24
+  #define TM_REG_INT_STS_WR_0_COMMAND_LC_INVALID_1                                                           (0x1<<25) // SET/CLEAR/FORCE CLEAR command and the logical client is invalid and the other logical clients are also invalid.
+  #define TM_REG_INT_STS_WR_0_COMMAND_LC_INVALID_1_SHIFT                                                     25
+  #define TM_REG_INT_STS_WR_0_INIT_COMMAND_LC_VALID                                                          (0x1<<26) // INIT command and the logical client valid bit is asserted.
+  #define TM_REG_INT_STS_WR_0_INIT_COMMAND_LC_VALID_SHIFT                                                    26
+  #define TM_REG_INT_STS_WR_0_STOP_ALL_EXP_LC_VALID                                                          (0x1<<27) // Stop all expiration and the valid of one of the logical clients is asserted.
+  #define TM_REG_INT_STS_WR_0_STOP_ALL_EXP_LC_VALID_SHIFT                                                    27
+  #define TM_REG_INT_STS_WR_0_COMMAND_CID_INVALID_0                                                          (0x1<<28) // Command with C/TID > 64K or VF TID segment not zero.
+  #define TM_REG_INT_STS_WR_0_COMMAND_CID_INVALID_0_SHIFT                                                    28
+  #define TM_REG_INT_STS_WR_0_RESERVED_COMMAND                                                               (0x1<<29) // RESERVED command.
+  #define TM_REG_INT_STS_WR_0_RESERVED_COMMAND_SHIFT                                                         29
+  #define TM_REG_INT_STS_WR_0_COMMAND_CID_INVALID_1                                                          (0x1<<30) // Command arrived to the host handler unit with CID/TID > Num_of_timers for that function.
+  #define TM_REG_INT_STS_WR_0_COMMAND_CID_INVALID_1_SHIFT                                                    30
+  #define TM_REG_INT_STS_WR_0_CLOAD_RES_LOADERR_CONN                                                         (0x1<<31) // Connections Load response with Load Error.
+  #define TM_REG_INT_STS_WR_0_CLOAD_RES_LOADERR_CONN_SHIFT                                                   31
+#define TM_REG_INT_STS_CLR_0                                                                                 0x2c018cUL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define TM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define TM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                           0
+  #define TM_REG_INT_STS_CLR_0_PXP_READ_DATA_FIFO_OV                                                         (0x1<<1) // PXP READ DATA FIFO Overflow.
+  #define TM_REG_INT_STS_CLR_0_PXP_READ_DATA_FIFO_OV_SHIFT                                                   1
+  #define TM_REG_INT_STS_CLR_0_PXP_READ_DATA_FIFO_UN                                                         (0x1<<2) // PXP READ DATA FIFO Underrun.
+  #define TM_REG_INT_STS_CLR_0_PXP_READ_DATA_FIFO_UN_SHIFT                                                   2
+  #define TM_REG_INT_STS_CLR_0_PXP_READ_CTRL_FIFO_OV                                                         (0x1<<3) // PXP READ CTRL FIFO Overflow.
+  #define TM_REG_INT_STS_CLR_0_PXP_READ_CTRL_FIFO_OV_SHIFT                                                   3
+  #define TM_REG_INT_STS_CLR_0_PXP_READ_CTRL_FIFO_UN                                                         (0x1<<4) // PXP READ CTRL FIFO Underrun.
+  #define TM_REG_INT_STS_CLR_0_PXP_READ_CTRL_FIFO_UN_SHIFT                                                   4
+  #define TM_REG_INT_STS_CLR_0_CFC_LOAD_COMMAND_FIFO_OV                                                      (0x1<<5) // CFC LOAD COMMAND FIFO Overflow.
+  #define TM_REG_INT_STS_CLR_0_CFC_LOAD_COMMAND_FIFO_OV_SHIFT                                                5
+  #define TM_REG_INT_STS_CLR_0_CFC_LOAD_COMMAND_FIFO_UN                                                      (0x1<<6) // CFC LOAD COMMAND FIFO Underrun.
+  #define TM_REG_INT_STS_CLR_0_CFC_LOAD_COMMAND_FIFO_UN_SHIFT                                                6
+  #define TM_REG_INT_STS_CLR_0_CFC_LOAD_ECHO_FIFO_OV                                                         (0x1<<7) // CFC LOAD ECHO FIFO Overflow.
+  #define TM_REG_INT_STS_CLR_0_CFC_LOAD_ECHO_FIFO_OV_SHIFT                                                   7
+  #define TM_REG_INT_STS_CLR_0_CFC_LOAD_ECHO_FIFO_UN                                                         (0x1<<8) // CFC LOAD ECHO FIFO Underrun.
+  #define TM_REG_INT_STS_CLR_0_CFC_LOAD_ECHO_FIFO_UN_SHIFT                                                   8
+  #define TM_REG_INT_STS_CLR_0_CLIENT_OUT_FIFO_OV                                                            (0x1<<9) // CLIENT OUT FIFO Overflow.
+  #define TM_REG_INT_STS_CLR_0_CLIENT_OUT_FIFO_OV_SHIFT                                                      9
+  #define TM_REG_INT_STS_CLR_0_CLIENT_OUT_FIFO_UN                                                            (0x1<<10) // CLIENT OUT FIFO Underrun.
+  #define TM_REG_INT_STS_CLR_0_CLIENT_OUT_FIFO_UN_SHIFT                                                      10
+  #define TM_REG_INT_STS_CLR_0_AC_COMMAND_FIFO_OV                                                            (0x1<<11) // AC COMMAND FIFO Overflow.
+  #define TM_REG_INT_STS_CLR_0_AC_COMMAND_FIFO_OV_SHIFT                                                      11
+  #define TM_REG_INT_STS_CLR_0_AC_COMMAND_FIFO_UN                                                            (0x1<<12) // AC COMMAND FIFO Underrun.
+  #define TM_REG_INT_STS_CLR_0_AC_COMMAND_FIFO_UN_SHIFT                                                      12
+  #define TM_REG_INT_STS_CLR_0_CLIENT_IN_PBF_FIFO_OV                                                         (0x1<<13) // CLIENT IN PBF FIFO Overflow.
+  #define TM_REG_INT_STS_CLR_0_CLIENT_IN_PBF_FIFO_OV_SHIFT                                                   13
+  #define TM_REG_INT_STS_CLR_0_CLIENT_IN_PBF_FIFO_UN                                                         (0x1<<14) // CLIENT IN PBF FIFO Underrun.
+  #define TM_REG_INT_STS_CLR_0_CLIENT_IN_PBF_FIFO_UN_SHIFT                                                   14
+  #define TM_REG_INT_STS_CLR_0_CLIENT_IN_UCM_FIFO_OV                                                         (0x1<<15) // CLIENT IN UCM FIFO Overflow.
+  #define TM_REG_INT_STS_CLR_0_CLIENT_IN_UCM_FIFO_OV_SHIFT                                                   15
+  #define TM_REG_INT_STS_CLR_0_CLIENT_IN_UCM_FIFO_UN                                                         (0x1<<16) // CLIENT IN UCM FIFO Underun.
+  #define TM_REG_INT_STS_CLR_0_CLIENT_IN_UCM_FIFO_UN_SHIFT                                                   16
+  #define TM_REG_INT_STS_CLR_0_CLIENT_IN_TCM_FIFO_OV                                                         (0x1<<17) // CLIENT IN TCM FIFO Overflow.
+  #define TM_REG_INT_STS_CLR_0_CLIENT_IN_TCM_FIFO_OV_SHIFT                                                   17
+  #define TM_REG_INT_STS_CLR_0_CLIENT_IN_TCM_FIFO_UN                                                         (0x1<<18) // CLIENT IN TCM FIFO Underrun.
+  #define TM_REG_INT_STS_CLR_0_CLIENT_IN_TCM_FIFO_UN_SHIFT                                                   18
+  #define TM_REG_INT_STS_CLR_0_CLIENT_IN_XCM_FIFO_OV                                                         (0x1<<19) // CLIENT IN XCM FIFO Overflow.
+  #define TM_REG_INT_STS_CLR_0_CLIENT_IN_XCM_FIFO_OV_SHIFT                                                   19
+  #define TM_REG_INT_STS_CLR_0_CLIENT_IN_XCM_FIFO_UN                                                         (0x1<<20) // CLIENT IN XCM FIFO Underrun.
+  #define TM_REG_INT_STS_CLR_0_CLIENT_IN_XCM_FIFO_UN_SHIFT                                                   20
+  #define TM_REG_INT_STS_CLR_0_EXPIRATION_CMD_FIFO_OV                                                        (0x1<<21) // EXPIRATION COMMAND FIFO Overflow.
+  #define TM_REG_INT_STS_CLR_0_EXPIRATION_CMD_FIFO_OV_SHIFT                                                  21
+  #define TM_REG_INT_STS_CLR_0_EXPIRATION_CMD_FIFO_UN                                                        (0x1<<22) // EXPIRATION COMMAND FIFO Underrun.
+  #define TM_REG_INT_STS_CLR_0_EXPIRATION_CMD_FIFO_UN_SHIFT                                                  22
+  #define TM_REG_INT_STS_CLR_0_STOP_ALL_LC_INVALID                                                           (0x1<<23) // STOP_ALL_TIMERS command and the logical client is invalid.
+  #define TM_REG_INT_STS_CLR_0_STOP_ALL_LC_INVALID_SHIFT                                                     23
+  #define TM_REG_INT_STS_CLR_0_COMMAND_LC_INVALID_0                                                          (0x1<<24) // SET/CLEAR/FORCE CLEAR command and the logical client invalid and one of the other logical clients is valid.
+  #define TM_REG_INT_STS_CLR_0_COMMAND_LC_INVALID_0_SHIFT                                                    24
+  #define TM_REG_INT_STS_CLR_0_COMMAND_LC_INVALID_1                                                          (0x1<<25) // SET/CLEAR/FORCE CLEAR command and the logical client is invalid and the other logical clients are also invalid.
+  #define TM_REG_INT_STS_CLR_0_COMMAND_LC_INVALID_1_SHIFT                                                    25
+  #define TM_REG_INT_STS_CLR_0_INIT_COMMAND_LC_VALID                                                         (0x1<<26) // INIT command and the logical client valid bit is asserted.
+  #define TM_REG_INT_STS_CLR_0_INIT_COMMAND_LC_VALID_SHIFT                                                   26
+  #define TM_REG_INT_STS_CLR_0_STOP_ALL_EXP_LC_VALID                                                         (0x1<<27) // Stop all expiration and the valid of one of the logical clients is asserted.
+  #define TM_REG_INT_STS_CLR_0_STOP_ALL_EXP_LC_VALID_SHIFT                                                   27
+  #define TM_REG_INT_STS_CLR_0_COMMAND_CID_INVALID_0                                                         (0x1<<28) // Command with C/TID > 64K or VF TID segment not zero.
+  #define TM_REG_INT_STS_CLR_0_COMMAND_CID_INVALID_0_SHIFT                                                   28
+  #define TM_REG_INT_STS_CLR_0_RESERVED_COMMAND                                                              (0x1<<29) // RESERVED command.
+  #define TM_REG_INT_STS_CLR_0_RESERVED_COMMAND_SHIFT                                                        29
+  #define TM_REG_INT_STS_CLR_0_COMMAND_CID_INVALID_1                                                         (0x1<<30) // Command arrived to the host handler unit with CID/TID > Num_of_timers for that function.
+  #define TM_REG_INT_STS_CLR_0_COMMAND_CID_INVALID_1_SHIFT                                                   30
+  #define TM_REG_INT_STS_CLR_0_CLOAD_RES_LOADERR_CONN                                                        (0x1<<31) // Connections Load response with Load Error.
+  #define TM_REG_INT_STS_CLR_0_CLOAD_RES_LOADERR_CONN_SHIFT                                                  31
+#define TM_REG_INT_STS_1                                                                                     0x2c0190UL //Access:R    DataWidth:0xb    // Multi Field Register.
+  #define TM_REG_INT_STS_1_CLOAD_RES_LOADCANCEL_CONN                                                         (0x1<<0) // Connections Load response with Load Cancel Error.
+  #define TM_REG_INT_STS_1_CLOAD_RES_LOADCANCEL_CONN_SHIFT                                                   0
+  #define TM_REG_INT_STS_1_CLOAD_RES_VALIDERR_CONN                                                           (0x1<<1) // Connections Load response with Validation Error.
+  #define TM_REG_INT_STS_1_CLOAD_RES_VALIDERR_CONN_SHIFT                                                     1
+  #define TM_REG_INT_STS_1_CONTEXT_RD_LAST                                                                   (0x1<<2) // Context Read with Last indication de-asserted.
+  #define TM_REG_INT_STS_1_CONTEXT_RD_LAST_SHIFT                                                             2
+  #define TM_REG_INT_STS_1_CONTEXT_WR_LAST                                                                   (0x1<<3) // Context Write with Last indication de-asserted.
+  #define TM_REG_INT_STS_1_CONTEXT_WR_LAST_SHIFT                                                             3
+  #define TM_REG_INT_STS_1_PXP_RD_DATA_EOP_BVALID                                                            (0x1<<4) // PXP Read Data EOP with BVALID != 0.
+  #define TM_REG_INT_STS_1_PXP_RD_DATA_EOP_BVALID_SHIFT                                                      4
+  #define TM_REG_INT_STS_1_PEND_CONN_SCAN                                                                    (0x1<<5) // Pending connection scan (the previous connection scan is still ongoing while there is a new connection scan pulse).
+  #define TM_REG_INT_STS_1_PEND_CONN_SCAN_SHIFT                                                              5
+  #define TM_REG_INT_STS_1_PEND_TASK_SCAN                                                                    (0x1<<6) // Pending task scan (the previous task scan is still ongoing while there is a new task scan pulse).
+  #define TM_REG_INT_STS_1_PEND_TASK_SCAN_SHIFT                                                              6
+  #define TM_REG_INT_STS_1_PXP_RD_DATA_EOP_ERROR                                                             (0x1<<7) // PXP Read Data EOP with ERROR.
+  #define TM_REG_INT_STS_1_PXP_RD_DATA_EOP_ERROR_SHIFT                                                       7
+  #define TM_REG_INT_STS_1_CLOAD_RES_LOADERR_TASK                                                            (0x1<<8) // Tasks Load response with Load Error
+  #define TM_REG_INT_STS_1_CLOAD_RES_LOADERR_TASK_SHIFT                                                      8
+  #define TM_REG_INT_STS_1_CLOAD_RES_LOADCANCEL_TASK                                                         (0x1<<9) // Tasks Load response with Load Cancel Error.
+  #define TM_REG_INT_STS_1_CLOAD_RES_LOADCANCEL_TASK_SHIFT                                                   9
+  #define TM_REG_INT_STS_1_CLOAD_RES_VALIDERR_TASK                                                           (0x1<<10) // Tasks Load response with Validation Error.
+  #define TM_REG_INT_STS_1_CLOAD_RES_VALIDERR_TASK_SHIFT                                                     10
+#define TM_REG_INT_MASK_1                                                                                    0x2c0194UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define TM_REG_INT_MASK_1_CLOAD_RES_LOADCANCEL_CONN                                                        (0x1<<0) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.CLOAD_RES_LOADCANCEL_CONN .
+  #define TM_REG_INT_MASK_1_CLOAD_RES_LOADCANCEL_CONN_SHIFT                                                  0
+  #define TM_REG_INT_MASK_1_CLOAD_RES_VALIDERR_CONN                                                          (0x1<<1) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.CLOAD_RES_VALIDERR_CONN .
+  #define TM_REG_INT_MASK_1_CLOAD_RES_VALIDERR_CONN_SHIFT                                                    1
+  #define TM_REG_INT_MASK_1_CONTEXT_RD_LAST                                                                  (0x1<<2) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.CONTEXT_RD_LAST .
+  #define TM_REG_INT_MASK_1_CONTEXT_RD_LAST_SHIFT                                                            2
+  #define TM_REG_INT_MASK_1_CONTEXT_WR_LAST                                                                  (0x1<<3) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.CONTEXT_WR_LAST .
+  #define TM_REG_INT_MASK_1_CONTEXT_WR_LAST_SHIFT                                                            3
+  #define TM_REG_INT_MASK_1_PXP_RD_DATA_EOP_BVALID                                                           (0x1<<4) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.PXP_RD_DATA_EOP_BVALID .
+  #define TM_REG_INT_MASK_1_PXP_RD_DATA_EOP_BVALID_SHIFT                                                     4
+  #define TM_REG_INT_MASK_1_PEND_CONN_SCAN                                                                   (0x1<<5) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.PEND_CONN_SCAN .
+  #define TM_REG_INT_MASK_1_PEND_CONN_SCAN_SHIFT                                                             5
+  #define TM_REG_INT_MASK_1_PEND_TASK_SCAN                                                                   (0x1<<6) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.PEND_TASK_SCAN .
+  #define TM_REG_INT_MASK_1_PEND_TASK_SCAN_SHIFT                                                             6
+  #define TM_REG_INT_MASK_1_PXP_RD_DATA_EOP_ERROR                                                            (0x1<<7) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.PXP_RD_DATA_EOP_ERROR .
+  #define TM_REG_INT_MASK_1_PXP_RD_DATA_EOP_ERROR_SHIFT                                                      7
+  #define TM_REG_INT_MASK_1_CLOAD_RES_LOADERR_TASK                                                           (0x1<<8) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.CLOAD_RES_LOADERR_TASK .
+  #define TM_REG_INT_MASK_1_CLOAD_RES_LOADERR_TASK_SHIFT                                                     8
+  #define TM_REG_INT_MASK_1_CLOAD_RES_LOADCANCEL_TASK                                                        (0x1<<9) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.CLOAD_RES_LOADCANCEL_TASK .
+  #define TM_REG_INT_MASK_1_CLOAD_RES_LOADCANCEL_TASK_SHIFT                                                  9
+  #define TM_REG_INT_MASK_1_CLOAD_RES_VALIDERR_TASK                                                          (0x1<<10) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.CLOAD_RES_VALIDERR_TASK .
+  #define TM_REG_INT_MASK_1_CLOAD_RES_VALIDERR_TASK_SHIFT                                                    10
+#define TM_REG_INT_STS_WR_1                                                                                  0x2c0198UL //Access:WR   DataWidth:0xb    // Multi Field Register.
+  #define TM_REG_INT_STS_WR_1_CLOAD_RES_LOADCANCEL_CONN                                                      (0x1<<0) // Connections Load response with Load Cancel Error.
+  #define TM_REG_INT_STS_WR_1_CLOAD_RES_LOADCANCEL_CONN_SHIFT                                                0
+  #define TM_REG_INT_STS_WR_1_CLOAD_RES_VALIDERR_CONN                                                        (0x1<<1) // Connections Load response with Validation Error.
+  #define TM_REG_INT_STS_WR_1_CLOAD_RES_VALIDERR_CONN_SHIFT                                                  1
+  #define TM_REG_INT_STS_WR_1_CONTEXT_RD_LAST                                                                (0x1<<2) // Context Read with Last indication de-asserted.
+  #define TM_REG_INT_STS_WR_1_CONTEXT_RD_LAST_SHIFT                                                          2
+  #define TM_REG_INT_STS_WR_1_CONTEXT_WR_LAST                                                                (0x1<<3) // Context Write with Last indication de-asserted.
+  #define TM_REG_INT_STS_WR_1_CONTEXT_WR_LAST_SHIFT                                                          3
+  #define TM_REG_INT_STS_WR_1_PXP_RD_DATA_EOP_BVALID                                                         (0x1<<4) // PXP Read Data EOP with BVALID != 0.
+  #define TM_REG_INT_STS_WR_1_PXP_RD_DATA_EOP_BVALID_SHIFT                                                   4
+  #define TM_REG_INT_STS_WR_1_PEND_CONN_SCAN                                                                 (0x1<<5) // Pending connection scan (the previous connection scan is still ongoing while there is a new connection scan pulse).
+  #define TM_REG_INT_STS_WR_1_PEND_CONN_SCAN_SHIFT                                                           5
+  #define TM_REG_INT_STS_WR_1_PEND_TASK_SCAN                                                                 (0x1<<6) // Pending task scan (the previous task scan is still ongoing while there is a new task scan pulse).
+  #define TM_REG_INT_STS_WR_1_PEND_TASK_SCAN_SHIFT                                                           6
+  #define TM_REG_INT_STS_WR_1_PXP_RD_DATA_EOP_ERROR                                                          (0x1<<7) // PXP Read Data EOP with ERROR.
+  #define TM_REG_INT_STS_WR_1_PXP_RD_DATA_EOP_ERROR_SHIFT                                                    7
+  #define TM_REG_INT_STS_WR_1_CLOAD_RES_LOADERR_TASK                                                         (0x1<<8) // Tasks Load response with Load Error
+  #define TM_REG_INT_STS_WR_1_CLOAD_RES_LOADERR_TASK_SHIFT                                                   8
+  #define TM_REG_INT_STS_WR_1_CLOAD_RES_LOADCANCEL_TASK                                                      (0x1<<9) // Tasks Load response with Load Cancel Error.
+  #define TM_REG_INT_STS_WR_1_CLOAD_RES_LOADCANCEL_TASK_SHIFT                                                9
+  #define TM_REG_INT_STS_WR_1_CLOAD_RES_VALIDERR_TASK                                                        (0x1<<10) // Tasks Load response with Validation Error.
+  #define TM_REG_INT_STS_WR_1_CLOAD_RES_VALIDERR_TASK_SHIFT                                                  10
+#define TM_REG_INT_STS_CLR_1                                                                                 0x2c019cUL //Access:RC   DataWidth:0xb    // Multi Field Register.
+  #define TM_REG_INT_STS_CLR_1_CLOAD_RES_LOADCANCEL_CONN                                                     (0x1<<0) // Connections Load response with Load Cancel Error.
+  #define TM_REG_INT_STS_CLR_1_CLOAD_RES_LOADCANCEL_CONN_SHIFT                                               0
+  #define TM_REG_INT_STS_CLR_1_CLOAD_RES_VALIDERR_CONN                                                       (0x1<<1) // Connections Load response with Validation Error.
+  #define TM_REG_INT_STS_CLR_1_CLOAD_RES_VALIDERR_CONN_SHIFT                                                 1
+  #define TM_REG_INT_STS_CLR_1_CONTEXT_RD_LAST                                                               (0x1<<2) // Context Read with Last indication de-asserted.
+  #define TM_REG_INT_STS_CLR_1_CONTEXT_RD_LAST_SHIFT                                                         2
+  #define TM_REG_INT_STS_CLR_1_CONTEXT_WR_LAST                                                               (0x1<<3) // Context Write with Last indication de-asserted.
+  #define TM_REG_INT_STS_CLR_1_CONTEXT_WR_LAST_SHIFT                                                         3
+  #define TM_REG_INT_STS_CLR_1_PXP_RD_DATA_EOP_BVALID                                                        (0x1<<4) // PXP Read Data EOP with BVALID != 0.
+  #define TM_REG_INT_STS_CLR_1_PXP_RD_DATA_EOP_BVALID_SHIFT                                                  4
+  #define TM_REG_INT_STS_CLR_1_PEND_CONN_SCAN                                                                (0x1<<5) // Pending connection scan (the previous connection scan is still ongoing while there is a new connection scan pulse).
+  #define TM_REG_INT_STS_CLR_1_PEND_CONN_SCAN_SHIFT                                                          5
+  #define TM_REG_INT_STS_CLR_1_PEND_TASK_SCAN                                                                (0x1<<6) // Pending task scan (the previous task scan is still ongoing while there is a new task scan pulse).
+  #define TM_REG_INT_STS_CLR_1_PEND_TASK_SCAN_SHIFT                                                          6
+  #define TM_REG_INT_STS_CLR_1_PXP_RD_DATA_EOP_ERROR                                                         (0x1<<7) // PXP Read Data EOP with ERROR.
+  #define TM_REG_INT_STS_CLR_1_PXP_RD_DATA_EOP_ERROR_SHIFT                                                   7
+  #define TM_REG_INT_STS_CLR_1_CLOAD_RES_LOADERR_TASK                                                        (0x1<<8) // Tasks Load response with Load Error
+  #define TM_REG_INT_STS_CLR_1_CLOAD_RES_LOADERR_TASK_SHIFT                                                  8
+  #define TM_REG_INT_STS_CLR_1_CLOAD_RES_LOADCANCEL_TASK                                                     (0x1<<9) // Tasks Load response with Load Cancel Error.
+  #define TM_REG_INT_STS_CLR_1_CLOAD_RES_LOADCANCEL_TASK_SHIFT                                               9
+  #define TM_REG_INT_STS_CLR_1_CLOAD_RES_VALIDERR_TASK                                                       (0x1<<10) // Tasks Load response with Validation Error.
+  #define TM_REG_INT_STS_CLR_1_CLOAD_RES_VALIDERR_TASK_SHIFT                                                 10
+#define TM_REG_PRTY_MASK_H_0_BB_K2                                                                           0x2c0204UL //Access:RW   DataWidth:0x11   // Multi Field Register.
+  #define TM_REG_PRTY_MASK_H_0_MEM012_I_ECC_0_RF_INT_BB_K2                                                   (0x1<<0) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM012_I_ECC_0_RF_INT .
+  #define TM_REG_PRTY_MASK_H_0_MEM012_I_ECC_0_RF_INT_BB_K2_SHIFT                                             0
+  #define TM_REG_PRTY_MASK_H_0_MEM012_I_ECC_1_RF_INT_BB_K2                                                   (0x1<<1) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM012_I_ECC_1_RF_INT .
+  #define TM_REG_PRTY_MASK_H_0_MEM012_I_ECC_1_RF_INT_BB_K2_SHIFT                                             1
+  #define TM_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_BB_K2                                                     (0x1<<2) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
+  #define TM_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_BB_K2_SHIFT                                               2
+  #define TM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_K2                                                       (0x1<<3) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
+  #define TM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_K2_SHIFT                                                 3
+  #define TM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2                                                       (0x1<<4) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define TM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2_SHIFT                                                 4
+  #define TM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2                                                       (0x1<<5) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
+  #define TM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2_SHIFT                                                 5
+  #define TM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2                                                       (0x1<<6) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define TM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2_SHIFT                                                 6
+  #define TM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2                                                       (0x1<<7) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define TM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2_SHIFT                                                 7
+  #define TM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_K2                                                       (0x1<<8) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
+  #define TM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_K2_SHIFT                                                 8
+  #define TM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_K2                                                       (0x1<<9) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
+  #define TM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_K2_SHIFT                                                 9
+  #define TM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_K2                                                       (0x1<<10) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
+  #define TM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_K2_SHIFT                                                 10
+  #define TM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                       (0x1<<11) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define TM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                                 11
+  #define TM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2                                                       (0x1<<12) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define TM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT                                                 12
+  #define TM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2                                                       (0x1<<13) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define TM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2_SHIFT                                                 13
+  #define TM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_K2                                                       (0x1<<14) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
+  #define TM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_K2_SHIFT                                                 14
+  #define TM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                       (0x1<<15) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define TM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                                 15
+  #define TM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                       (0x1<<16) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define TM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                                 16
+#define TM_REG_MEM_ECC_ENABLE_0_BB_K2                                                                        0x2c0210UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define TM_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_0_EN_BB_K2                                                    (0x1<<0) // Enable ECC for memory ecc instance tm.i_tm_context_mem.i_ecc_0 in module tm_context_mem
+  #define TM_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_0_EN_BB_K2_SHIFT                                              0
+  #define TM_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_1_EN_BB_K2                                                    (0x1<<1) // Enable ECC for memory ecc instance tm.i_tm_context_mem.i_ecc_1 in module tm_context_mem
+  #define TM_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_1_EN_BB_K2_SHIFT                                              1
+  #define TM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_BB_K2                                                      (0x1<<2) // Enable ECC for memory ecc instance tm.TM_PRE_SCAN_2048_ROWS_IF.i_tm_pre_scan_mem.i_ecc in module tm_pre_scan_2048_mem
+  #define TM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_BB_K2_SHIFT                                                2
+#define TM_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                   0x2c0214UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define TM_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_0_PRTY_BB_K2                                             (0x1<<0) // Set parity only for memory ecc instance tm.i_tm_context_mem.i_ecc_0 in module tm_context_mem
+  #define TM_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_0_PRTY_BB_K2_SHIFT                                       0
+  #define TM_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_1_PRTY_BB_K2                                             (0x1<<1) // Set parity only for memory ecc instance tm.i_tm_context_mem.i_ecc_1 in module tm_context_mem
+  #define TM_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_1_PRTY_BB_K2_SHIFT                                       1
+  #define TM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_BB_K2                                               (0x1<<2) // Set parity only for memory ecc instance tm.TM_PRE_SCAN_2048_ROWS_IF.i_tm_pre_scan_mem.i_ecc in module tm_pre_scan_2048_mem
+  #define TM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_BB_K2_SHIFT                                         2
+#define TM_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                               0x2c0218UL //Access:RC   DataWidth:0x3    // Multi Field Register.
+  #define TM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_0_CORRECT_BB_K2                                      (0x1<<0) // Record if a correctable error occurred on memory ecc instance tm.i_tm_context_mem.i_ecc_0 in module tm_context_mem
+  #define TM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_0_CORRECT_BB_K2_SHIFT                                0
+  #define TM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_1_CORRECT_BB_K2                                      (0x1<<1) // Record if a correctable error occurred on memory ecc instance tm.i_tm_context_mem.i_ecc_1 in module tm_context_mem
+  #define TM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_1_CORRECT_BB_K2_SHIFT                                1
+  #define TM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_BB_K2                                        (0x1<<2) // Record if a correctable error occurred on memory ecc instance tm.TM_PRE_SCAN_2048_ROWS_IF.i_tm_pre_scan_mem.i_ecc in module tm_pre_scan_2048_mem
+  #define TM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_BB_K2_SHIFT                                  2
+#define TM_REG_MEM_ECC_EVENTS_BB_K2                                                                          0x2c021cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define TM_REG_PXP_READ_DATA_FIFO_A_F_THR                                                                    0x2c0400UL //Access:RW   DataWidth:0x6    // Almost full threshold for the PXP READ DATA FIFO, which its size is 48 rows.
+#define TM_REG_PXP_READ_CTRL_FIFO_A_F_THR                                                                    0x2c0404UL //Access:RW   DataWidth:0x4    // Almost full threshold for the PXP READ CTRL FIFO, which its size is 8 rows.
+#define TM_REG_CFC_LOAD_COMMAND_FIFO_A_F_THR                                                                 0x2c0408UL //Access:RW   DataWidth:0x5    // Almost full threshold for the CFC LOAD COMMAND FIFO, which its size is 16 rows. For Debug only.
+#define TM_REG_CLIENT_OUT_FIFO_A_F_THR                                                                       0x2c040cUL //Access:RW   DataWidth:0x4    // Almost full threshold for the CLIENT OUT FIFO, which its size is 4 rows. For Debug only.
+#define TM_REG_CLIENT_IN_PBF_FIFO_A_F_THR                                                                    0x2c0410UL //Access:RW   DataWidth:0x3    // Almost full threshold for the CLIENT IN PBF FIFO, which its size is 4 rows. For Debug only.
+#define TM_REG_CLIENT_IN_XCM_FIFO_A_F_THR                                                                    0x2c0414UL //Access:RW   DataWidth:0x3    // Almost full threshold for the CLIENT IN XCM FIFO, which its size is 4 rows. For Debug only.
+#define TM_REG_CLIENT_IN_TCM_FIFO_A_F_THR                                                                    0x2c0418UL //Access:RW   DataWidth:0x3    // Almost full threshold for the CLIENT IN TCM FIFO, which its size is 4 rows. For Debug only.
+#define TM_REG_CLIENT_IN_UCM_FIFO_A_F_THR                                                                    0x2c041cUL //Access:RW   DataWidth:0x3    // Almost full threshold for the CLIENT IN UCM FIFO, which its size is 4 rows. For Debug only.
+#define TM_REG_EXPIRATION_CMD_FIFO_A_F_THR                                                                   0x2c0420UL //Access:RW   DataWidth:0x4    // Almost full threshold for the EXPIRATION COMMAND FIFO, which its size is 8 rows. For Debug only.
+#define TM_REG_CFC_LOAD_ECHO_FIFO_A_F_THR                                                                    0x2c0424UL //Access:RW   DataWidth:0x5    // Almost full threshold for the CFC LOAD ECHO FIFO, which its size is 16 rows. For Debug only.
+#define TM_REG_AC_COMMAND_FIFO_A_F_THR                                                                       0x2c0428UL //Access:RW   DataWidth:0x4    // Almost full threshold for the AC COMMAND FIFO, which its size is 12 rows. For Debug only.
+#define TM_REG_VF_ENABLE_CONN                                                                                0x2c0438UL //Access:RW   DataWidth:0x1    // Enable the VF functions for the connections. This configuration is applicable only to scan operation.  Was: en_linear0_timer.
+#define TM_REG_PF_ENABLE_CONN                                                                                0x2c043cUL //Access:RW   DataWidth:0x1    // Enable the PF functions for the connections. This configuration is applicable only to scan opeartion.
+#define TM_REG_VF_ENABLE_TASK                                                                                0x2c0440UL //Access:RW   DataWidth:0x1    // Enable the VF functions for the tasks. This configuration is applicable only to scan operation.  Was: en_linear1_timer.
+#define TM_REG_PF_ENABLE_TASK                                                                                0x2c0444UL //Access:RW   DataWidth:0x4    // Enable the PF functions for the tasks. This configuration is applicable only to scan opeartion. Bit 0: segment 0, bit 1: segment 1, bit 2: segment 2, bit 3: segment 3. Was: en_linear1_timer.
+#define TM_REG_TICK_TIMER_VAL                                                                                0x2c0448UL //Access:RW   DataWidth:0x12   // The number of clock cycles (25MHz clock) for each timer tick. Previous name: timer_tick_size.
+#define TM_REG_TICK_TIMER_ENABLE                                                                             0x2c044cUL //Access:RW   DataWidth:0x1    // When set, enable the tick_timer.
+#define TM_REG_CONNECTIONS_SCAN_TIMER_VAL                                                                    0x2c0450UL //Access:RW   DataWidth:0x14   // The count value for the connections scan timer, which counts number of ticks (tick_timer) that generate a connection scan pulse, an indication to scan the connections timers. The minimum value is 2.
+#define TM_REG_CONNECTIONS_SCAN_TIMER_ENABLE                                                                 0x2c0454UL //Access:RW   DataWidth:0x1    // When set, enable the connections scan timer.
+#define TM_REG_TASKS_SCAN_TIMER_VAL                                                                          0x2c0458UL //Access:RW   DataWidth:0x14   // The count value for the tasks scan timer, which counts number of ticks (tick_timer) that generate a tasks scan pulse, an indication to scan the tasks timers. The minimum value is 2.
+#define TM_REG_TASKS_SCAN_TIMER_ENABLE                                                                       0x2c045cUL //Access:RW   DataWidth:0x1    // When set, enable the tasks scan timer.
+#define TM_REG_CONTEXT_REGION_CONN                                                                           0x2c0460UL //Access:RW   DataWidth:0x8    // The Context Region for the connections CFC context load command.
+#define TM_REG_CONTEXT_REGION_TASK                                                                           0x2c0464UL //Access:RW   DataWidth:0x8    // The Context Region for the tasks CFC context load command.
+#define TM_REG_PCI_VQ_ID                                                                                     0x2c0468UL //Access:RW   DataWidth:0x5    // Pci VQ ID.
+#define TM_REG_PCI_TPH_VALID                                                                                 0x2c046cUL //Access:RW   DataWidth:0x1    // Pci TPH valid.
+#define TM_REG_PCI_TPH_ST_HINT                                                                               0x2c0470UL //Access:RW   DataWidth:0x2    // Pci TPH ST hint.
+#define TM_REG_PCI_TPH_STT_IDX                                                                               0x2c0474UL //Access:RW   DataWidth:0x9    // Pci TPH STT IDX.
+#define TM_REG_PCI_REQUEST_DONE_TYPE                                                                         0x2c0478UL //Access:RW   DataWidth:0x1    // Pci request done type.
+#define TM_REG_PCI_USE_PARENT_PF                                                                             0x2c047cUL //Access:RW   DataWidth:0x1    // Pci use parent PF.
+#define TM_REG_PCI_NUMBER_READ_REQUESTS                                                                      0x2c0480UL //Access:RW   DataWidth:0x3    // The maximum number for the pci outstanding read requests, generated by the scan engine. The applicable values are 1 to 4.
+#define TM_REG_GROUP_SIZE_RESOLUTION_CONN                                                                    0x2c0484UL //Access:RW   DataWidth:0x2    // Number of timers per connection group: 00 - 128 timers, 01 - 64 timers, 10 - 32 timers, 11 - 16 timers.
+#define TM_REG_GROUP_SIZE_RESOLUTION_TASK                                                                    0x2c0488UL //Access:RW   DataWidth:0x2    // Number of timers per task group: 00 - 128 timers, 01 - 64 timers, 10 - 32 timers, 11 - 16 timers.
+#define TM_REG_PRE_SCAN_RANGE_CONN                                                                           0x2c048cUL //Access:RW   DataWidth:0x2    // Selection when to scan a connection group: 00 - the pre scan feature is disabled, i.e. every scan pulse all the groups are scanned. 01 - each group is selected to be scanned based on its nearest timer, every 1,2,4 scan pulses.  10 - each group is selected to be scanned based on its nearest timer, every 1,4,16 scan pulses.  11 - each group is selected to be scanned based on its nearest timer, every 1,8,64 scan pulses.
+#define TM_REG_PRE_SCAN_RANGE_TASK                                                                           0x2c0490UL //Access:RW   DataWidth:0x2    // Selection when to scan a task group: 00 - the pre scan feature is disabled, i.e. every scan pulse all the groups are scanned. 01 - each group is selected to be scanned based on its nearest timer, every 1,2,4 scan pulses.  10 - each group is selected to be scanned based on its nearest timer, every 1,4,16 scan pulses.  11 - each group is selected to be scanned based on its nearest timer, every 1,8,64 scan pulses.
+#define TM_REG_PRE_SCAN_MEM_BYPASS                                                                           0x2c0494UL //Access:RW   DataWidth:0x1    // When set, the pre scan memory is bypassed. This configuration is applicable only if PreScanRange register is set to 0. TBD = name of the other register.
+#define TM_REG_ECO_RESERVED                                                                                  0x2c0498UL //Access:RW   DataWidth:0x8    // For ECOs.
+#define TM_REG_PCI_ATC_RD_FIRST_BLOCK                                                                        0x2c049cUL //Access:RW   DataWidth:0x3    // ATC flag for reading first block in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search only, 10 - search & cache, 11 - search & release. Was: pci_atc_rd_first_block.
+#define TM_REG_PCI_ATC_RD_LAST_BLOCK                                                                         0x2c04a0UL //Access:RW   DataWidth:0x3    // ATC flag for reading last block in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search only, 10 - search & cache, 11 - search & release. Was: atc_page_las_bnk_rd.
+#define TM_REG_PCI_ATC_RD_MIDDLE_BLOCK                                                                       0x2c04a4UL //Access:RW   DataWidth:0x3    // ATC flag for reading middle blockss in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search only, 10 - search & cache, 11 - search & release. Was atc_page_mid_bnk_rd.
+#define TM_REG_PCI_ATC_WR                                                                                    0x2c04a8UL //Access:RW   DataWidth:0x3    // ATC field for writes; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search only, 10 - search & cache, 11 - search & release.
+#define TM_REG_LOGICAL_0_CLIENT_EXP_CONN                                                                     0x2c04acUL //Access:RW   DataWidth:0x20   // For logical client 0, per each connection type (16 types), configuration of the applicable client out interface that the expiration command is sent to. The client out decoding is : 00 - XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client out for type 1, Bits [5:4] - client out for type 2, Bits [7:6] - client out for type 3, Bits [9:8] - client out for type 4, Bits [11:10] - client out for type 5, Bits [13:12] - client out for type 6, Bits [15:14] - client out for type 7, Bits [17:16] - client out for type 8, Bits [19:18] - client out for type 9, Bits [21:20] - client out for type 10. Bits [23:22] - client out for type 11, Bits [25:24] - client out for type 12, Bits [27:26] - client out for type 13. Bits [29:28] - client out for type 14, Bits [31:30] - client out for type 15.
+#define TM_REG_LOGICAL_1_CLIENT_EXP_CONN                                                                     0x2c04b0UL //Access:RW   DataWidth:0x20   // For logical client 1, per each connection type (16 types), configuration of the applicable client out interface that the expiration command is sent to. The client out decoding is : 00 - XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client out for type 1, Bits [5:4] - client out for type 2, Bits [7:6] - client out for type 3, Bits [9:8] - client out for type 4, Bits [11:10] - client out for type 5, Bits [13:12] - client out for type 6, Bits [15:14] - client out for type 7, Bits [17:16] - client out for type 8, Bits [19:18] - client out for type 9, Bits [21:20] - client out for type 10. Bits [23:22] - client out for type 11, Bits [25:24] - client out for type 12, Bits [27:26] - client out for type 13. Bits [29:28] - client out for type 14, Bits [31:30] - client out for type 15.
+#define TM_REG_LOGICAL_2_CLIENT_EXP_CONN                                                                     0x2c04b4UL //Access:RW   DataWidth:0x20   // For logical client 2, per each connection type (16 types), configuration of the applicable client out interface that the expiration command is sent to. The client out decoding is : 00 - XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client out for type 1, Bits [5:4] - client out for type 2, Bits [7:6] - client out for type 3, Bits [9:8] - client out for type 4, Bits [11:10] - client out for type 5, Bits [13:12] - client out for type 6, Bits [15:14] - client out for type 7, Bits [17:16] - client out for type 8, Bits [19:18] - client out for type 9, Bits [21:20] - client out for type 10. Bits [23:22] - client out for type 11, Bits [25:24] - client out for type 12, Bits [27:26] - client out for type 13. Bits [29:28] - client out for type 14, Bits [31:30] - client out for type 15.
+#define TM_REG_LOGICAL_0_CLIENT_EXP_TASK                                                                     0x2c04b8UL //Access:RW   DataWidth:0x10   // For logical client 0, per each task type (8 types), configuration of the applicable client out interface that the expiration command is sent to. The client out decoding is : 00 - XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client out for type 1, Bits [5:4] - client out for type 2, Bits [7:6] - client out for type 3, Bits [9:8] - client out for type 4, Bits [11:10] - client out for type 5, Bits [13:12] - client out for type 6, Bits [15:14] - client out for type 7.
+#define TM_REG_LOGICAL_1_CLIENT_EXP_TASK                                                                     0x2c04bcUL //Access:RW   DataWidth:0x10   // For logical client 1, per each task type (8 types), configuration of the applicable client out interface that the expiration command is sent to. The client out decoding is : 00 - XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client out for type 1, Bits [5:4] - client out for type 2, Bits [7:6] - client out for type 3, Bits [9:8] - client out for type 4, Bits [11:10] - client out for type 5, Bits [13:12] - client out for type 6, Bits [15:14] - client out for type 7.
+#define TM_REG_LOGICAL_2_CLIENT_EXP_TASK                                                                     0x2c04c0UL //Access:RW   DataWidth:0x10   // For logical client 2, per each task type (8 types), configuration of the applicable client out interface that the expiration command is sent to. The client out decoding is : 00 - XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client out for type 1, Bits [5:4] - client out for type 2, Bits [7:6] - client out for type 3, Bits [9:8] - client out for type 4, Bits [11:10] - client out for type 5, Bits [13:12] - client out for type 6, Bits [15:14] - client out for type 7.
+#define TM_REG_CLIENT_STOP_ALL_EXP_CONN                                                                      0x2c04c4UL //Access:RW   DataWidth:0x20   // For stop all expiration, per each connection type (16 types), configuration of the applicable client out interface that the stop all expiration command is sent to. The client out decoding is : 00 - XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client out for type 1, Bits [5:4] - client out for type 2, Bits [7:6] - client out for type 3, Bits [9:8] - client out for type 4, Bits [11:10] - client out for type 5, Bits [13:12] - client out for type 6, Bits [15:14] - client out for type 7, Bits [17:16] - client out for type 8, Bits [19:18] - client out for type 9, Bits [21:20] - client out for type 10. Bits [23:22] - client out for type 11, Bits [25:24] - client out for type 12, Bits [27:26] - client out for type 13. Bits [29:28] - client out for type 14, Bits [31:30] - client out for type 15.
+#define TM_REG_CLIENT_STOP_ALL_EXP_TASK                                                                      0x2c04c8UL //Access:RW   DataWidth:0x10   // For stop all expiration, per each task type (8 types), configuration of the applicable client out interface that the stop all expiration command is sent to. The client out decoding is : 00 - XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client out for type 1, Bits [5:4] - client out for type 2, Bits [7:6] - client out for type 3, Bits [9:8] - client out for type 4, Bits [11:10] - client out for type 5, Bits [13:12] - client out for type 6, Bits [15:14] - client out for type 7.
+#define TM_REG_LOGICAL_0_CONN_THRESH_SEL                                                                     0x2c04ccUL //Access:RW   DataWidth:0x20   // For logical client 0, per each connection type (8 types), configuration of the threshold on the nearest expiration for sending write command to host. The threshold decoding is : 00 - No threshold; Command to the host is set without checking threshold, 01 - Threshold according to global configuration conn_timer_threshold_0, 10 - Threshold according to global configuration conn_timer_threshold_1, 11 - Threshold according to global configuration conn_timer_threshold_2. Bits [1:0] - threshold selection for type 0, Bits [3:2] - threshold selection for type 1, Bits [5:4] - threshold selection for type 2, Bits [7:6] - threshold selection for type 3, Bits [9:8] - threshold selection for type 4, Bits [11:10] - threshold selection for type 5, Bits [13:12] - threshold selection for type 6, Bits [15:14] - threshold selection for type 7, Bits [17:16] - threshold selection for type 8, Bits [19:18] - threshold selection for type 9, Bits [21:20] - threshold selection for type 10, Bits [23:22] - threshold selection for type 11, Bits [25:24] - threshold selection for type 12, Bits [27:26] - threshold selection for type 13, Bits [29:28] - threshold selection for type 14, Bits [31:30] - threshold selection for type 15.
+#define TM_REG_LOGICAL_1_CONN_THRESH_SEL                                                                     0x2c04d0UL //Access:RW   DataWidth:0x20   // For logical client 1, per each connection type (8 types), configuration of the threshold on the nearest expiration for sending write command to host. The threshold decoding is : 00 - No threshold; Command to the host is set without checking threshold, 01 - Threshold according to global configuration conn_timer_threshold_0, 10 - Threshold according to global configuration conn_timer_threshold_1, 11 - Threshold according to global configuration conn_timer_threshold_2. Bits [1:0] - threshold selection for type 0, Bits [3:2] - threshold selection for type 1, Bits [5:4] - threshold selection for type 2, Bits [7:6] - threshold selection for type 3, Bits [9:8] - threshold selection for type 4, Bits [11:10] - threshold selection for type 5, Bits [13:12] - threshold selection for type 6, Bits [15:14] - threshold selection for type 7, Bits [17:16] - threshold selection for type 8, Bits [19:18] - threshold selection for type 9, Bits [21:20] - threshold selection for type 10, Bits [23:22] - threshold selection for type 11, Bits [25:24] - threshold selection for type 12, Bits [27:26] - threshold selection for type 13, Bits [29:28] - threshold selection for type 14, Bits [31:30] - threshold selection for type 15.
+#define TM_REG_LOGICAL_2_CONN_THRESH_SEL                                                                     0x2c04d4UL //Access:RW   DataWidth:0x20   // For logical client 2, per each connection type (8 types), configuration of the threshold on the nearest expiration for sending write command to host. The threshold decoding is : 00 - No threshold; Command to the host is set without checking threshold, 01 - Threshold according to global configuration conn_timer_threshold_0, 10 - Threshold according to global configuration conn_timer_threshold_1, 11 - Threshold according to global configuration conn_timer_threshold_2. Bits [1:0] - threshold selection for type 0, Bits [3:2] - threshold selection for type 1, Bits [5:4] - threshold selection for type 2, Bits [7:6] - threshold selection for type 3, Bits [9:8] - threshold selection for type 4, Bits [11:10] - threshold selection for type 5, Bits [13:12] - threshold selection for type 6, Bits [15:14] - threshold selection for type 7, Bits [17:16] - threshold selection for type 8, Bits [19:18] - threshold selection for type 9, Bits [21:20] - threshold selection for type 10, Bits [23:22] - threshold selection for type 11, Bits [25:24] - threshold selection for type 12, Bits [27:26] - threshold selection for type 13, Bits [29:28] - threshold selection for type 14, Bits [31:30] - threshold selection for type 15.
+#define TM_REG_LOGICAL_0_TASK_THRESH_SEL                                                                     0x2c04d8UL //Access:RW   DataWidth:0x10   // For logical client 0, per each task type (8 types), configuration of the threshold on the nearest expiration for sending write command to host. The threshold decoding is : 00 - No threshold; Command to the host is set without checking threshold, 01 - Threshold according to global configuration conn_timer_threshold_0, 10 - Threshold according to global configuration conn_timer_threshold_1, 11 - Threshold according to global configuration conn_timer_threshold_2. Bits [1:0] - threshold selection for  type 0, Bits [3:2] - threshold selection for  type 1, Bits [5:4] - threshold selection for  type 2, Bits [7:6] - threshold selection for  type 3, Bits [9:8] - threshold selection for  type 4, Bits [11:10] - threshold selection for  type 5, Bits [13:12] - threshold selection for  type 6, Bits [15:14] - threshold selection for  type 7.
+#define TM_REG_LOGICAL_1_TASK_THRESH_SEL                                                                     0x2c04dcUL //Access:RW   DataWidth:0x10   // For logical client 1, per each task type (8 types), configuration of the threshold on the nearest expiration for sending write command to host. The threshold decoding is : 00 - No threshold; Command to the host is set without checking threshold, 01 - Threshold according to global configuration conn_timer_threshold_0, 10 - Threshold according to global configuration conn_timer_threshold_1, 11 - Threshold according to global configuration conn_timer_threshold_2. Bits [1:0] - threshold selection for  type 0, Bits [3:2] - threshold selection for  type 1, Bits [5:4] - threshold selection for  type 2, Bits [7:6] - threshold selection for  type 3, Bits [9:8] - threshold selection for  type 4, Bits [11:10] - threshold selection for  type 5, Bits [13:12] - threshold selection for  type 6, Bits [15:14] - threshold selection for  type 7.
+#define TM_REG_LOGICAL_2_TASK_THRESH_SEL                                                                     0x2c04e0UL //Access:RW   DataWidth:0x10   // For logical client 2, per each task type (8 types), configuration of the threshold on the nearest expiration for sending write command to host. The threshold decoding is : 00 - No threshold; Command to the host is set without checking threshold, 01 - Threshold according to global configuration conn_timer_threshold_0, 10 - Threshold according to global configuration conn_timer_threshold_1, 11 - Threshold according to global configuration conn_timer_threshold_2. Bits [1:0] - threshold selection for  type 0, Bits [3:2] - threshold selection for  type 1, Bits [5:4] - threshold selection for  type 2, Bits [7:6] - threshold selection for  type 3, Bits [9:8] - threshold selection for  type 4, Bits [11:10] - threshold selection for  type 5, Bits [13:12] - threshold selection for  type 6, Bits [15:14] - threshold selection for  type 7.
+#define TM_REG_CONN_TIMER_THRESHOLD_0                                                                        0x2c04e4UL //Access:RW   DataWidth:0x19   // A threshold value, 0 , for connections, which is used on decision on whether to send a write command to the host or postpone the write command to later stage. This threshold is selected by the logical_0_conn_thresh_sel, logical_1_conn_thresh_sel and logical_1_conn_thresh_sel registers.
+#define TM_REG_CONN_TIMER_THRESHOLD_1                                                                        0x2c04e8UL //Access:RW   DataWidth:0x19   // A threshold value, 1 , for connections, which is used on decision on whether to send a write command to the host or postpone the write command to later stage. This threshold is selected by the logical_0_conn_thresh_sel, logical_1_conn_thresh_sel and logical_1_conn_thresh_sel registers.
+#define TM_REG_CONN_TIMER_THRESHOLD_2                                                                        0x2c04ecUL //Access:RW   DataWidth:0x19   // A threshold value, 2 , for connections, which is used on decision on whether to send a write command to the host or postpone the write command to later stage. This threshold is selected by the logical_0_conn_thresh_sel, logical_1_conn_thresh_sel and logical_1_conn_thresh_sel registers.
+#define TM_REG_TASK_TIMER_THRESHOLD_0                                                                        0x2c04f0UL //Access:RW   DataWidth:0x19   // A threshold value, 0 , for tasks, which is used on decision on whether to send a write command to the host or postpone the write command to later stage. This threshold is selected by the logical_0_task_thresh_sel, logical_1_task_thresh_sel and logical_1_task_thresh_sel registers.
+#define TM_REG_TASK_TIMER_THRESHOLD_1                                                                        0x2c04f4UL //Access:RW   DataWidth:0x19   // A threshold value, 1 , for tasks which is used on decision on whether to send a write command to the host or postpone the write command to later stage. This threshold is selected by the logical_0_task_thresh_sel, logical_1_task_thresh_sel and logical_1_task_thresh_sel registers.
+#define TM_REG_TASK_TIMER_THRESHOLD_2                                                                        0x2c04f8UL //Access:RW   DataWidth:0x19   // A threshold value, 2 , for taskss which is used on decision on whether to send a write command to the host or postpone the write command to later stage. This threshold is selected by the logical_0_task_thresh_sel, logical_1_task_thresh_sel and logical_1_task_thresh_sel registers.
+#define TM_REG_PF_SCAN_ACTIVE_CONN                                                                           0x2c04fcUL //Access:R    DataWidth:0x1    // Indicates if the PF connection is active, ie if it is during the scan process. When =1, the PF connection is active. When =0, the PF connection is not active.
+#define TM_REG_PF_SCAN_ACTIVE_TASK                                                                           0x2c0500UL //Access:R    DataWidth:0x4    // Indicates if the PF task is active, ie if it is during the scan process. Bit 0 is for segment 0, bit 1 is for segment 1, bit 2 is for segment 2 and bit 3 is for segment 3. When =1, the PF task segment is active. When =0, the PF task segment is not active.
+#define TM_REG_VF_SCAN_ACTIVE_CONN                                                                           0x2c0504UL //Access:R    DataWidth:0x1    // Indicates if the VF connection is active, ie if it is during the scan process. When =1, the VF connection is active. When =0, the VF connection is not active.
+#define TM_REG_VF_SCAN_ACTIVE_TASK                                                                           0x2c0508UL //Access:R    DataWidth:0x1    // Indicates if the VF task is active, ie if it is during the scan process. When =1, the VF task is active. When =0, the VF task is not active.
+#define TM_REG_DURING_SCAN_CONN                                                                              0x2c050cUL //Access:R    DataWidth:0x1    // Indicates if the block is during the connections scan process. When =1, the block is during the connections scan process. When =0, the block is not during the connections scan process.
+#define TM_REG_DURING_SCAN_TASK                                                                              0x2c0510UL //Access:R    DataWidth:0x1    // Indicates if the block is during the tasks scan process. When =1, the block is during the tasks scan process. When =0, the block is not during the tasks scan process.
+#define TM_REG_DURING_SCAN                                                                                   0x2c0514UL //Access:R    DataWidth:0x1    // Indicates if the block is during the tasks or connections scan process. When =1, the block is during the tasks or connections scan process. When =0, the block is not during the tasks or connections scan process.
+#define TM_REG_COMPLETED_SCANS                                                                               0x2c0600UL //Access:R    DataWidth:0x20   // Number of completed scans. Incremented if connection scan is completed or if task scan is completed. The counter wraparound, and is not reset when read.
+#define TM_REG_SCAN_PULSE_PRIOR_SCAN_COMPLETED                                                               0x2c0604UL //Access:RC   DataWidth:0x20   // Number of scan pulses that arrived before the compatible scan was completed or even started.                          Incremented if task pulse arrived before the previous task scan was completed or even started or                           if connection pulse arrived before the previous connection scan was completed or even started.
+#define TM_REG_SET_COMMANDS_RCV_ON_PBF                                                                       0x2c0608UL //Access:R    DataWidth:0x20   // Number of SET commands received on the client in PBF interface.
+#define TM_REG_CLEAR_COMMANDS_RCV_ON_PBF                                                                     0x2c060cUL //Access:R    DataWidth:0x20   // Number of CLEAR commands received on the client in PBF interface.
+#define TM_REG_FORCE_CLEAR_COMMANDS_RCV_ON_PBF                                                               0x2c0610UL //Access:R    DataWidth:0x20   // Number of FORCE CLEAR commands received on the client in PBF interface.
+#define TM_REG_INIT_COMMANDS_RCV_ON_PBF                                                                      0x2c0614UL //Access:R    DataWidth:0x20   // Number of INIT commands received on the client in PBF interface.
+#define TM_REG_STOP_ALL_COMMANDS_RCV_ON_PBF                                                                  0x2c0618UL //Access:R    DataWidth:0x20   // Number of STOP ALL commands received on the client in PBF interface.
+#define TM_REG_SET_COMMANDS_RCV_ON_TCM                                                                       0x2c061cUL //Access:R    DataWidth:0x20   // Number of SET commands received on the client in TCM interface.
+#define TM_REG_CLEAR_COMMANDS_RCV_ON_TCM                                                                     0x2c0620UL //Access:R    DataWidth:0x20   // Number of CLEAR commands received on the client in TCM interface.
+#define TM_REG_FORCE_CLEAR_COMMANDS_RCV_ON_TCM                                                               0x2c0624UL //Access:R    DataWidth:0x20   // Number of FORCE CLEAR commands received on the client in TCM interface.
+#define TM_REG_INIT_COMMANDS_RCV_ON_TCM                                                                      0x2c0628UL //Access:R    DataWidth:0x20   // Number of INIT commands received on the client in TCM interface.
+#define TM_REG_STOP_ALL_COMMANDS_RCV_ON_TCM                                                                  0x2c062cUL //Access:R    DataWidth:0x20   // Number of STOP ALL commands received on the client in TCM interface.
+#define TM_REG_SET_COMMANDS_RCV_ON_UCM                                                                       0x2c0630UL //Access:R    DataWidth:0x20   // Number of SET commands received on the client in UCM interface.
+#define TM_REG_CLEAR_COMMANDS_RCV_ON_UCM                                                                     0x2c0634UL //Access:R    DataWidth:0x20   // Number of CLEAR commands received on the client in UCM interface.
+#define TM_REG_FORCE_CLEAR_COMMANDS_RCV_ON_UCM                                                               0x2c0638UL //Access:R    DataWidth:0x20   // Number of FORCE CLEAR commands received on the client in UCM interface.
+#define TM_REG_INIT_COMMANDS_RCV_ON_UCM                                                                      0x2c063cUL //Access:R    DataWidth:0x20   // Number of INIT commands received on the client in UCM interface.
+#define TM_REG_STOP_ALL_COMMANDS_RCV_ON_UCM                                                                  0x2c0640UL //Access:R    DataWidth:0x20   // Number of STOP ALL commands received on the client in UCM interface.
+#define TM_REG_SET_COMMANDS_RCV_ON_XCM                                                                       0x2c0644UL //Access:R    DataWidth:0x20   // Number of SET commands received on the client in XCM interface.
+#define TM_REG_CLEAR_COMMANDS_RCV_ON_XCM                                                                     0x2c0648UL //Access:R    DataWidth:0x20   // Number of CLEAR commands received on the client in XCM interface.
+#define TM_REG_FORCE_CLEAR_COMMANDS_RCV_ON_XCM                                                               0x2c064cUL //Access:R    DataWidth:0x20   // Number of FORCE CLEAR commands received on the client in XCM interface.
+#define TM_REG_INIT_COMMANDS_RCV_ON_XCM                                                                      0x2c0650UL //Access:R    DataWidth:0x20   // Number of INIT commands received on the client in XCM interface.
+#define TM_REG_STOP_ALL_COMMANDS_RCV_ON_XCM                                                                  0x2c0654UL //Access:R    DataWidth:0x20   // Number of STOP ALL commands received on the client in XCM interface.
+#define TM_REG_FALSE_EXPIRATIONS                                                                             0x2c0658UL //Access:RC   DataWidth:0x20   // Number of false expirations.
+#define TM_REG_EXPIRATIONS                                                                                   0x2c065cUL //Access:RC   DataWidth:0x20   // Number of expirations (including stop all expirations).
+#define TM_REG_COMMANDS_SENT_TO_HOST                                                                         0x2c0660UL //Access:RC   DataWidth:0x20   // Number of commands (write requests) sent to host (set, clear, stop all)
+#define TM_REG_LOAD_RESP_LOADERR_CONN                                                                        0x2c0664UL //Access:RC   DataWidth:0x10   // Number of load responses with loaderr asserted on the CCFC interface (connections).
+#define TM_REG_LOAD_RESP_LOADCANCEL_CONN                                                                     0x2c0668UL //Access:RC   DataWidth:0x10   // Number of load responses with loadcancel asserted on the CCFC interface (connections).
+#define TM_REG_LOAD_RESP_LOADERR_TASK                                                                        0x2c066cUL //Access:RC   DataWidth:0x10   // Number of load responses with loaderr asserted on the CCFC interface (tasks).
+#define TM_REG_LOAD_RESP_LOADCANCEL_TASK                                                                     0x2c0670UL //Access:RC   DataWidth:0x10   // Number of load responses with loadcancel asserted on the CCFC interface (tasks).
+#define TM_REG_RD_REQUESTS_SENT_TO_HOST                                                                      0x2c0674UL //Access:RC   DataWidth:0x20   // Number of read requests (scan) sent to host.
+#define TM_REG_PXP_READ_DATA_ERROR                                                                           0x2c0678UL //Access:RC   DataWidth:0x8    // Number of PXP read data packets received with ERROR (on the EOP cycle)
+#define TM_REG_CURRENT_TIME                                                                                  0x2c0700UL //Access:R    DataWidth:0x1b   // The real time clock, incremented every ticks (tick_timer).
+#define TM_REG_CONNECTIONS_SCAN_TIMER                                                                        0x2c0704UL //Access:R    DataWidth:0x14   // Connections scan timer, counts number of ticks (tick_timer) that generates a connection scan pulse, an indication to scan the connections timers.
+#define TM_REG_TASKS_SCAN_TIMER                                                                              0x2c0708UL //Access:R    DataWidth:0x14   // Tasks scan timer, counts number of ticks (tick_timer) that generates a task scan pulse, an indication to scan the tasks timers.
+#define TM_REG_PXP_READ_DATA_FIFO_FULL                                                                       0x2c070cUL //Access:R    DataWidth:0x1    // When set indicates that the PXP READ DATA FIFO is full.
+#define TM_REG_PXP_READ_DATA_FIFO_STATUS                                                                     0x2c0710UL //Access:R    DataWidth:0x6    // Indicates the status of the PXP READ DATA FIFO, number of rows filled with data.
+#define TM_REG_PXP_READ_CTRL_FIFO_FULL                                                                       0x2c0714UL //Access:R    DataWidth:0x1    // When set indicates that the PXP READ CTRL FIFO is full.
+#define TM_REG_PXP_READ_CTRL_FIFO_STATUS                                                                     0x2c0718UL //Access:R    DataWidth:0x4    // Indicates the status of the PXP READ CTRL FIFO, number of rows filled with data.
+#define TM_REG_CFC_LOAD_COMMAND_FIFO_STATUS                                                                  0x2c071cUL //Access:R    DataWidth:0x5    // Indicates the status of the CFC LOAD COMMAND FIFO, number of rows filled with data.
+#define TM_REG_CFC_LOAD_ECHO_FIFO_STATUS                                                                     0x2c0720UL //Access:R    DataWidth:0x5    // Indicates the status of the CFC LOAD ECHO FIFO, number of rows filled with data.
+#define TM_REG_CLIENT_OUT_FIFO_STATUS                                                                        0x2c0724UL //Access:R    DataWidth:0x4    // Indicates the status of the CLIENT IN PBF FIFO, number of rows filled with data.
+#define TM_REG_CLIENT_IN_PBF_FIFO_STATUS                                                                     0x2c0728UL //Access:R    DataWidth:0x3    // Indicates the status of the CLIENT In PBF FIFO, number of rows filled with data.
+#define TM_REG_CLIENT_IN_XCM_FIFO_STATUS                                                                     0x2c072cUL //Access:R    DataWidth:0x3    // Indicates the status of the CLIENT IN XCM FIFO, number of rows filled with data.
+#define TM_REG_CLIENT_IN_TCM_FIFO_STATUS                                                                     0x2c0730UL //Access:R    DataWidth:0x3    // Indicates the status of the CLIENT IN TCM FIFO, number of rows filled with data.
+#define TM_REG_CLIENT_IN_UCM_FIFO_STATUS                                                                     0x2c0734UL //Access:R    DataWidth:0x3    // Indicates the status of the CLIENT IN UCM FIFO, number of rows filled with data.
+#define TM_REG_EXPIRATION_CMD_FIFO_STATUS                                                                    0x2c0738UL //Access:R    DataWidth:0x4    // Indicates the status of the EXPIRATION COMMAND FIFO, number of rows filled with data.
+#define TM_REG_AC_COMMAND_FIFO_STATUS                                                                        0x2c073cUL //Access:R    DataWidth:0x4    // Indicates the status of the AC COMMAND FIFO, number of rows filled with data.
+#define TM_REG_DEBUG_0_ERROR_TYPE_EN                                                                         0x2c0740UL //Access:RW   DataWidth:0x8    // If the error type is enabled, if the error took place, the errored command data is kept in the debug_0 registers: Bit [0]: if = 1,  the following error is enabled: STOP_ALL_TIMERS command and the logical client is invalid, Bit [1]: if = 1,  the following error is enabled: SET/CLEAR/FORCE CLEAR command and the logical client invalid and one of the other logical client is valid, Bit [2]: if = 1,  the following error is enabled: SET/CLEAR/FORCE CLEAR command and the logical client invalid and the other logical client are also invalid, Bit [3]: if = 1,  the following error is enabled: INIT command and the logical client valid bit is asserted, Bit [4]: if = 1,  the following error is enabled: stop all expiration and the valid of one of the logical clients is asserted, Bit [5]: if = 1,  the following error is enabled: command with C/TID > 64K or VF TID segment not zero, Bit [6]: if = 1,  the following error is enabled: RESERVED command, Bit [7]: if = 1,  the following error is enabled: command arrived to the host handler unit with CID/TID > Num_of_timers for that function.
+#define TM_REG_DEBUG_0_FID_EN                                                                                0x2c0744UL //Access:RW   DataWidth:0x1    // If enabled, if the error took place, only a command with error for the fid in the register debug_0_fid_mask is kept in the debug_0 registers.
+#define TM_REG_DEBUG_0_FID_MASK                                                                              0x2c0748UL //Access:RW   DataWidth:0x10   // If debug_0_fid_en is enabled, if the error took place, only a command with error for the fid identical to this regsiter is kept in the debug_0 registers. The fid structure is the opaque fid.
+#define TM_REG_DEBUG_0_SOURCE_EN                                                                             0x2c074cUL //Access:RW   DataWidth:0x1    // If enabled, if the error took place, only a command with error from the source in the register debug_0_source_mask is kept in the debug_0 registers.
+#define TM_REG_DEBUG_0_SOURCE_MASK                                                                           0x2c0750UL //Access:RW   DataWidth:0x3    // If debug_0_source_en is enabled, if the error took place, only a command with error for the source identical to this regsiter is kept in the debug_0 registers. The source: 0 - PBF, 1 -TCM, 2- UCM, 3 - XCM, 4 - expiration, 5 - reserved, 6 - reserved, 7 - reserved.
+#define TM_REG_DEBUG_0_ERROR_VALID                                                                           0x2c0754UL //Access:RW   DataWidth:0x1    // When asserted, = 1, indicates that the debug_0 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
+#define TM_REG_DEBUG_0_CID                                                                                   0x2c0758UL //Access:R    DataWidth:0x20   // The CID for the errored command.
+#define TM_REG_DEBUG_0_LCID                                                                                  0x2c075cUL //Access:R    DataWidth:0x9    // The LCID for the errored command.
+#define TM_REG_DEBUG_0_DONT_DEC_AC                                                                           0x2c0760UL //Access:R    DataWidth:0x1    // The Dont Dec AC field for the errored command.
+#define TM_REG_DEBUG_0_COMMAND                                                                               0x2c0764UL //Access:R    DataWidth:0x3    // The Command field for the errored command: 0 - SET TIMER, 1 - CLEAR TIMER, 2 - STOP ALL TIMERS, 3 - INIT, 4 - FORCE CLEAR TIMER,  5 - reserved, 6 - reservd, 7 -reservd, 1 - EXPIRATION (if SOURCE = EXPIRATION), 2 - STOP ALL EXPIRATION (if SOURCE = EXPIRATION).
+#define TM_REG_DEBUG_0_LOG_CLIENT_NUM                                                                        0x2c0768UL //Access:R    DataWidth:0x2    // The Logical Client for the errored command.
+#define TM_REG_DEBUG_0_TYPE                                                                                  0x2c076cUL //Access:R    DataWidth:0x4    // The TYPE field for the errored command.
+#define TM_REG_DEBUG_0_LEADER_TYPE                                                                           0x2c0770UL //Access:R    DataWidth:0x1    // The Leader Type field for the errored command: 0 - connection, 1 - task.
+#define TM_REG_DEBUG_0_SOURCE                                                                                0x2c0774UL //Access:R    DataWidth:0x3    // The Source for the errored command. The source: 0 - PBF, 1 -TCM, 2- UCM, 3 - XCM, 4 - expiration, 5 - reserved, 6 - reserved, 7 - reserved.
+#define TM_REG_DEBUG_0_CONTEXT_STATUS                                                                        0x2c0778UL //Access:R    DataWidth:0x6    // The Context Status for the errored command: Bit 0: logical client 0 valid bit, Bit 1: logical client 0 active bit, Bit 2: logical client 1 valid bit, Bit 3: logical client 1 active bit, Bit 4: logical client 2 valid bit, Bit 5: logical client 2 active bit. This status information doesnt exist for the error: command arrived to the host handler unit with CID/TID > Num_of_timers for that function.
+#define TM_REG_DEBUG_0_ERROR_TYPE                                                                            0x2c077cUL //Access:R    DataWidth:0x8    // The error type: Bit [0]: if = 1,  the following error happened: STOP_ALL_TIMERS command and the logical client is invalid, Bit [1]: if = 1,  the following error happened: SET/CLEAR/FORCE CLEAR command and the logical client invalid and one of the other logical client is valid, Bit [2]: if = 1,  the following error is happened: SET/CLEAR/FORCE CLEAR command and the logical client invalid and the other logical client are also invalid, Bit [3]: if = 1,  the following error happened: INIT command and the logical client valid bit is asserted, Bit [4]: if = 1,  the following error happened: stop all expiration and the valid of one of the logical clients is asserted, Bit [5]: if = 1,  the following error happened: command with C/TID > 64K or VF TID segment not zero, Bit [6]: if = 1,  the following error happened: RESERVED command, Bit [7]: if = 1,  the following error happened: command arrived to the host handler unit with CID/TID > Num_of_timers for that function.
+#define TM_REG_DEBUG_1_ERROR_VALID                                                                           0x2c0780UL //Access:RW   DataWidth:0x1    // When asserted, = 1, indicates that the debug_1 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
+#define TM_REG_DEBUG_1_CID                                                                                   0x2c0784UL //Access:R    DataWidth:0x20   // The CID for the errored load response.
+#define TM_REG_DEBUG_1                                                                                       0x2c0788UL //Access:R    DataWidth:0x17   // The load response with error fields: Bits 8-0: LCID, Bit 9: scan type (0 - connection, 1 - task), Bits 12-10: type (3 LSbits), Bit 13: Load Error Task, Bit 14: Load Cancel Task, Bit 15: Valid Error Task, Bit 16: Load Error Connection, Bit 17: Load Cancel Connection, Bit 18: Valid Error Connection, Bits 22-19: type (full 4 bits).
+#define TM_REG_DEBUG_2_ERROR_VALID                                                                           0x2c078cUL //Access:RW   DataWidth:0x1    // When asserted, = 1, indicates that the debug_2 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
+#define TM_REG_DEBUG_2                                                                                       0x2c0790UL //Access:R    DataWidth:0xb    // The CDU context read with last indication de-asserted fields: Bits 8-0: LCID, Bit 9: Type (0 - connection, 1 - task), Bit 10: asserted if Last indication is de-asserted.
+#define TM_REG_DEBUG_3_ERROR_VALID                                                                           0x2c0794UL //Access:RW   DataWidth:0x1    // When asserted, = 1, indicates that the debug_3 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
+#define TM_REG_DEBUG_3                                                                                       0x2c0798UL //Access:R    DataWidth:0xd    // The CDU context write with last indication de-asserted fields: Bits 8-0: LCID, Bit 9: Type (0 - connection, 1 - task), Bit 11-10: Qward Valid, Bit 12: asserted if Last indication is de-asserted.
+#define TM_REG_FSMS_STATES                                                                                   0x2c079cUL //Access:R    DataWidth:0x1b   // The current states of the block FSMs:                          Bits 2-0: cmd_handler.                          Bit 3: reserved.                          Bits 7-4: write_timer.                          Bits 9-8: read_fifo.                          Bits 11-10: reserved.                          Bits 14-12: scan.                          Bits 15: reserved.                          Bits 19-16: rd_scan_rate.                          Bits 22-20: expiration.                          Bits 23: reserved.                          Bits 26-24: update_prescan_mem.
+#define TM_REG_DEBUG_4_ERROR_VALID                                                                           0x2c07a0UL //Access:RW   DataWidth:0x1    // When asserted, = 1, indicates that the debug_4 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
+#define TM_REG_DEBUG_4                                                                                       0x2c07a4UL //Access:R    DataWidth:0x17   // The PXP read data is received with an error or with bvalid != 0. The parameters for the errored data:                    Bits 8-0: function # (0-239 VFs, 240 and above PFs / segments) . Bit 9: type (0 - connection, 1 - task). Bits 13-10: group. Bit 22-14: relative row (16 groups in a row).
+#define TM_REG_DBG_SELECT                                                                                    0x2c07a8UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define TM_REG_DBG_DWORD_ENABLE                                                                              0x2c07acUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define TM_REG_DBG_SHIFT                                                                                     0x2c07b0UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define TM_REG_DBG_FORCE_VALID                                                                               0x2c07b4UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define TM_REG_DBG_FORCE_FRAME                                                                               0x2c07b8UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define TM_REG_DBG_OUT_DATA                                                                                  0x2c07c0UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define TM_REG_DBG_OUT_DATA_SIZE                                                                             8
+#define TM_REG_DBG_OUT_VALID                                                                                 0x2c07e0UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define TM_REG_DBG_OUT_FRAME                                                                                 0x2c07e4UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define TM_REG_CONFIG_CONN_MEM                                                                               0x2c1000UL //Access:WB   DataWidth:0x1e   // Configuration memory for the connections. Each row contains the configuration for the compatible function. Rows 0 to 239 are for VFs 0 to 239: row 0 for VF 0, row 1 for VF1, row 2 for VF 2, etc. Rows 240 to 255 are for the PFs: row 240 for PF 0, row 193 for PF 1, row 194 for PF 2, etc. The fields are: bits [15:0] - number of connections, the value should be multiplies of group_size_resolution_conn register (for example, if group_size_resolution_conn = 0, 128 timers, the number of connections can be 128, 256, 384, etc.), bits [25:16] - reserved. bits [29:26] - the parent PF (applicable if VF, NA if PF).
+#define TM_REG_CONFIG_CONN_MEM_SIZE_BB                                                                       256
+#define TM_REG_CONFIG_CONN_MEM_SIZE_K2                                                                       416
+#define TM_REG_CONFIG_CONN_MEM_SIZE_E5                                                                       256
+#define TM_REG_CONFIG_TASK_MEM                                                                               0x2c2000UL //Access:WB   DataWidth:0x31   // Configuration memory for the tasks. Each row contains the configuration for the compatible function. Rows 0 to 239 are for VFs 0 to 239: row 0 for VF 0, row 1 for VF1, row 2 for VF 2, etc. Rows 240 to 303 are for the PFs segments: row 240 for PF 0 segment 0, row 241 for PF 0 segment 1, row 242 for PF 0 segment 2, row 243 for PF 0 segment 3, row 244 for PF1 segment 0, row 245 for PF1 segment 1, etc. The fields are: bits [15:0] - number of tasks, the value should be multiplies of group_size_resolution_task register (for example, if group_size_resolution_task = 0, 128 timers, the number of tasks can be 128, 256, 384, etc.), bits [25:16] - reserved. bits [29:26] - the parent PF (applicable if VF, NA if PF). bits [48:30] - the pci base offset address in 32 bits resolution (all 19 bits are applicable if PF, only the first 17 bits are applicable if VF).
+#define TM_REG_CONFIG_TASK_MEM_SIZE_BB                                                                       304
+#define TM_REG_CONFIG_TASK_MEM_SIZE_K2                                                                       512
+#define TM_REG_CONFIG_TASK_MEM_SIZE_E5                                                                       608
+#define TM_REG_PRE_SCAN_MEM_BB_K2                                                                            0x2c4000UL //Access:RW   DataWidth:0x20   // Pre scan memory which contains the scan rate fields for each group. Each row contains scan rate field (2 bits) per group, for 16 groups. The first 512 rows contain the scan rate fields for connections, the last 512 rows contain the scan rate fields for tasks. TBD - describe the fields.
+#define TM_REG_PRE_SCAN_MEM_SIZE_BB                                                                          1024
+#define TM_REG_PRE_SCAN_MEM_SIZE_K2                                                                          2048
+#define TM_REG_CONTEXT_MEM                                                                                   0x2c8000UL //Access:WB   DataWidth:0x73   // Context memory for connections and tasks. 320 LCIDs for connections and 320 LTIDs for tasks. The addresses are interleaved between connections and tasks. If address [0] = 0, it is LCID (connections), if address [0] = 1, it is LTID (tasks). Previous name: context_ram0.
+#define TM_REG_CONTEXT_MEM_SIZE                                                                              2560
+#define TCFC_REG_INIT_REG                                                                                    0x2d0000UL //Access:RW   DataWidth:0xd    // Multi Field Register.
+  #define TCFC_REG_INIT_REG_AC_INIT                                                                          (0x1<<0) // When set activity counter ram will be initialized to zeros. when this operation is completed CFC_REGISTERS_AC_INITDONE.AC_INIT_DONE will be set.
+  #define TCFC_REG_INIT_REG_AC_INIT_SHIFT                                                                    0
+  #define TCFC_REG_INIT_REG_LL_INIT_LAST_LCID                                                                (0x1ff<<1) // This field is only relevant when setting CFC_REGISTERS_INIT_REG.LL_INIT . indicates the last lcid to be used by the CFC. this field can strict the CFC to work will less than 320 LCIDs.
+  #define TCFC_REG_INIT_REG_LL_INIT_LAST_LCID_SHIFT                                                          1
+  #define TCFC_REG_INIT_REG_LL_INIT                                                                          (0x1<<10) // When set link list ram will be initialized - all LCIDs will be located in the empty link list. when this operation completes CFC_REGISTERS_LL_INITDONE.LL_INIT_DONE will be set.
+  #define TCFC_REG_INIT_REG_LL_INIT_SHIFT                                                                    10
+  #define TCFC_REG_INIT_REG_CAM_INIT                                                                         (0x1<<11) // When set the CFC CAMs will be initialized to zeros. When this operation completes CFC_REGISTERS_CAM_INITDONE.CAM_INIT_DONE will be set.
+  #define TCFC_REG_INIT_REG_CAM_INIT_SHIFT                                                                   11
+  #define TCFC_REG_INIT_REG_TIDRAM_INIT                                                                      (0x1<<12) // Setting this bit causes the TID Lock RAM to be initialized. This cannot be set during normal operation -- the block must be idle or the request will be ignored. When this operation completes CFC_REGISTERS_TIDRAM_INITDONE.TIDRAM_INIT_DONE will be set.
+  #define TCFC_REG_INIT_REG_TIDRAM_INIT_SHIFT                                                                12
+#define TCFC_REG_LL_INIT_DONE                                                                                0x2d0004UL //Access:R    DataWidth:0x1    // Indication the initializing the link list by the hardware was done.
+#define TCFC_REG_AC_INIT_DONE                                                                                0x2d0008UL //Access:R    DataWidth:0x1    // Indication the initializing the activity counter by the hardware was done.
+#define TCFC_REG_CAM_INIT_DONE                                                                               0x2d000cUL //Access:R    DataWidth:0x1    // Indication that initializing the cams by the hardware was done.
+#define TCFC_REG_TIDRAM_INIT_DONE                                                                            0x2d0010UL //Access:R    DataWidth:0x1    // Indication that initializing the TID Lock RAM by the hardware was done.
+#define TCFC_REG_INT_STS_0                                                                                   0x2d0180UL //Access:R    DataWidth:0x2    // Multi Field Register.
+  #define TCFC_REG_INT_STS_0_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define TCFC_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                             0
+  #define TCFC_REG_INT_STS_0_EXE_ERROR                                                                       (0x1<<1) // Interrupt indicating that an execution error has occurred.
+  #define TCFC_REG_INT_STS_0_EXE_ERROR_SHIFT                                                                 1
+#define TCFC_REG_INT_MASK_0                                                                                  0x2d0184UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define TCFC_REG_INT_MASK_0_ADDRESS_ERROR                                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: TCFC_REG_INT_STS_0.ADDRESS_ERROR .
+  #define TCFC_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                            0
+  #define TCFC_REG_INT_MASK_0_EXE_ERROR                                                                      (0x1<<1) // This bit masks, when set, the Interrupt bit: TCFC_REG_INT_STS_0.EXE_ERROR .
+  #define TCFC_REG_INT_MASK_0_EXE_ERROR_SHIFT                                                                1
+#define TCFC_REG_INT_STS_WR_0                                                                                0x2d0188UL //Access:WR   DataWidth:0x2    // Multi Field Register.
+  #define TCFC_REG_INT_STS_WR_0_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define TCFC_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                          0
+  #define TCFC_REG_INT_STS_WR_0_EXE_ERROR                                                                    (0x1<<1) // Interrupt indicating that an execution error has occurred.
+  #define TCFC_REG_INT_STS_WR_0_EXE_ERROR_SHIFT                                                              1
+#define TCFC_REG_INT_STS_CLR_0                                                                               0x2d018cUL //Access:RC   DataWidth:0x2    // Multi Field Register.
+  #define TCFC_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                               (0x1<<0) // Signals an unknown address to the rf module.
+  #define TCFC_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                         0
+  #define TCFC_REG_INT_STS_CLR_0_EXE_ERROR                                                                   (0x1<<1) // Interrupt indicating that an execution error has occurred.
+  #define TCFC_REG_INT_STS_CLR_0_EXE_ERROR_SHIFT                                                             1
+#define TCFC_REG_PRTY_MASK_H_0_BB_K2                                                                         0x2d0204UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define TCFC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                     (0x1<<0) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define TCFC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                               0
+  #define TCFC_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                     (0x1<<1) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define TCFC_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                               1
+#define TCFC_REG_MEM_ECC_EVENTS_BB_K2                                                                        0x2d0210UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define TCFC_REG_LC_BLOCKED                                                                                  0x2d0400UL //Access:RC   DataWidth:0x20   // Statistics register that counts cycles in which load context requests were blocked.
+#define TCFC_REG_TID_LOCK_INC_STAT                                                                           0x2d0404UL //Access:RC   DataWidth:0x20   // This statistic counts the number of cycles in which a Primary Lock condition exists when it was caused by an Increment command on a previously locked LTID. Note that this counts the number of cycles in which this condition exists, not the number of times it occurred.
+#define TCFC_REG_TID_LOCK_LOCK_STAT                                                                          0x2d0408UL //Access:RC   DataWidth:0x20   // This statistic counts the number of cycles in which a Primary Lock condition exists when it was caused by an Lock command on a previously locked LTID. Note that this counts the number of cycles in which this condition exists, not the number of times it occurred.
+#define TCFC_REG_RFE_TASK_COUNTER                                                                            0x2d040cUL //Access:RC   DataWidth:0x20   // Counts number of tasks executed by the RFE controller.
+#define TCFC_REG_LC_STAT_MASK                                                                                0x2d0410UL //Access:RW   DataWidth:0xe    // Used to mask the various load client queues for LC task statistics.
+#define TCFC_REG_LC_TASK_COUNTER                                                                             0x2d0414UL //Access:RC   DataWidth:0x20   // Counts number of tasks executed by the load client controller.
+#define TCFC_REG_MISC_TASK_COUNTER                                                                           0x2d0418UL //Access:RC   DataWidth:0x20   // Counts number of tasks executed by the miscellaneous controller.
+#define TCFC_REG_LOAD_CONTEXT_HITS                                                                           0x2d041cUL //Access:RC   DataWidth:0x20   // Counts the number of load context hits for the load clients selected by lc_stat_mask.
+#define TCFC_REG_LOAD_CONTEXT_MISSES                                                                         0x2d0420UL //Access:RC   DataWidth:0x20   // Counts the number of load context misses for the load clients selected by lc_stat_mask.
+#define TCFC_REG_RFE_SEARCH_HITS                                                                             0x2d0424UL //Access:RC   DataWidth:0x20   // Counts the number of RFE serach hits.
+#define TCFC_REG_RFE_SEARCH_MISSES                                                                           0x2d0428UL //Access:RC   DataWidth:0x20   // Counts the number of RFE serach misses.
+#define TCFC_REG_CDU_WRITE_BACKS                                                                             0x2d042cUL //Access:RC   DataWidth:0x20   // Counts the number of CDU write backs submitted by CFC.
+#define TCFC_REG_DBG_SELECT                                                                                  0x2d0500UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define TCFC_REG_DBG_DWORD_ENABLE                                                                            0x2d0504UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define TCFC_REG_DBG_SHIFT                                                                                   0x2d0508UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define TCFC_REG_DBG_FORCE_VALID                                                                             0x2d050cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define TCFC_REG_DBG_FORCE_FRAME                                                                             0x2d0510UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define TCFC_REG_DBG_OUT_DATA                                                                                0x2d0520UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define TCFC_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define TCFC_REG_DBG_OUT_VALID                                                                               0x2d0540UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define TCFC_REG_DBG_OUT_FRAME                                                                               0x2d0544UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define TCFC_REG_ECO_RESERVED                                                                                0x2d0548UL //Access:RW   DataWidth:0x8    // Eco reserved.  bit0: Chicken bit for CQ73536 fix. When '0' takes into account LCIDs in the pipe. When '1' behaces as A0.
+#define TCFC_REG_ERROR_VECTOR                                                                                0x2d054cUL //Access:R    DataWidth:0x11   // CFC error vector. when the CFC detects an internal error it will set one of these bits. the bit description can be found in CFC specifications.
+#define TCFC_REG_ERROR_MASK                                                                                  0x2d0550UL //Access:RW   DataWidth:0x11   // Masking for error logging. if a bit in this field is set then the corresponding bit in CFC_REGISTERS_CFC_ERROR_VECTOR.ERROR_VECTOR will not be set.
+#define TCFC_REG_DISABLE_ON_ERROR                                                                            0x2d0554UL //Access:RW   DataWidth:0x11   // Indicates per error (in CFC_REGISTERS_CFC_ERROR_VECTOR.CFC_ERROR vector) whether the cfc should be disabled upon it.
+#define TCFC_REG_ERROR_DATA1                                                                                 0x2d0558UL //Access:R    DataWidth:0x20   // When the CFC detects an internal error it updates these fields. [31:28] -- CFC Controller ID [20:16] -- CFC Client ID [15:08] -- Requested Regions [04:00] -- Error ID Note that the Error ID starts counting at 0x1 so that there will always be a bit set in the ID.  This means it is always 1 greater than the bit in the error_vector register which caused the error.  See the CFC EAS document for more details.
+#define TCFC_REG_ERROR_DATA2                                                                                 0x2d055cUL //Access:R    DataWidth:0x20   // When the CFC detects an internal error it updates these fields. [31:00] -- CID
+#define TCFC_REG_ERROR_DATA3                                                                                 0x2d0560UL //Access:R    DataWidth:0x20   // When the CFC detects an internal error it updates these fields. [24:16] -- Request LCID [08:00] -- Active LCID
+#define TCFC_REG_ERROR_DATA4                                                                                 0x2d0564UL //Access:R    DataWidth:0x20   // When the CFC detects an internal error it updates these fields. [23:16] -- Increment Value [15:12] -- Type Field [08:00] -- AC LCID
+#define TCFC_REG_ARBITERS_REG                                                                                0x2d0568UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define TCFC_REG_ARBITERS_REG_SP_LC_DONE_ARB                                                               (0x1<<0) // When set CFC arbiter1 will work in strict priority.
+  #define TCFC_REG_ARBITERS_REG_SP_LC_DONE_ARB_SHIFT                                                         0
+  #define TCFC_REG_ARBITERS_REG_SP_LC_REQ_ARB                                                                (0x1<<1) // When set load context arbiter will work in strict priority.
+  #define TCFC_REG_ARBITERS_REG_SP_LC_REQ_ARB_SHIFT                                                          1
+  #define TCFC_REG_ARBITERS_REG_SP_LC_INP_ARB                                                                (0x1<<2) // When set CFC arbiter2 will work in strict priority.
+  #define TCFC_REG_ARBITERS_REG_SP_LC_INP_ARB_SHIFT                                                          2
+  #define TCFC_REG_ARBITERS_REG_SP_MISC_ARB                                                                  (0x1<<3) // When set CFC arbiter3 will work in strict priority.
+  #define TCFC_REG_ARBITERS_REG_SP_MISC_ARB_SHIFT                                                            3
+  #define TCFC_REG_ARBITERS_REG_SP_AC_DEC                                                                    (0x1<<4) // When set activity counter decrement arbiter will work in strict priority.
+  #define TCFC_REG_ARBITERS_REG_SP_AC_DEC_SHIFT                                                              4
+  #define TCFC_REG_ARBITERS_REG_SP_AC_INC                                                                    (0x1<<5) // When set activity counter increment arbiter will work in strict priority.
+  #define TCFC_REG_ARBITERS_REG_SP_AC_INC_SHIFT                                                              5
+#define TCFC_REG_LCREQ_WEIGHTS                                                                               0x2d0580UL //Access:RW   DataWidth:0x3    // This field allows changing the priorities of the weighted-round-robin arbiter which selects which CFC load client should be served next.
+#define TCFC_REG_LCREQ_WEIGHTS_SIZE                                                                          14
+#define TCFC_REG_DEBUG0                                                                                      0x2d05c0UL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define TCFC_REG_DEBUG0_DISABLE_INPUTS                                                                     (0x1<<0) // This bit disables the inputs on the CFC.
+  #define TCFC_REG_DEBUG0_DISABLE_INPUTS_SHIFT                                                               0
+  #define TCFC_REG_DEBUG0_DISABLE_OUTPUTS                                                                    (0x1<<1) // This bit disables the outputs of the CFC.
+  #define TCFC_REG_DEBUG0_DISABLE_OUTPUTS_SHIFT                                                              1
+  #define TCFC_REG_DEBUG0_AC_COUNTER_ZERO                                                                    (0xff<<2) // Debug only.
+  #define TCFC_REG_DEBUG0_AC_COUNTER_ZERO_SHIFT                                                              2
+  #define TCFC_REG_DEBUG0_AC_GRANT_PERIOD                                                                    (0xf<<10) // This register is not used in BB-B0. Reduced width to 1 bit to keep its address.
+  #define TCFC_REG_DEBUG0_AC_GRANT_PERIOD_SHIFT                                                              10
+  #define TCFC_REG_DEBUG0_E_THRESHOLD                                                                        (0x7<<14) // Debug only.
+  #define TCFC_REG_DEBUG0_E_THRESHOLD_SHIFT                                                                  14
+  #define TCFC_REG_DEBUG0_INA_THRESHOLD                                                                      (0x7<<17) // Debug only.
+  #define TCFC_REG_DEBUG0_INA_THRESHOLD_SHIFT                                                                17
+  #define TCFC_REG_DEBUG0_IO_THRESHOLD                                                                       (0x7<<20) // Debug only.
+  #define TCFC_REG_DEBUG0_IO_THRESHOLD_SHIFT                                                                 20
+#define TCFC_REG_DEBUG1                                                                                      0x2d05c4UL //Access:RW   DataWidth:0xd    // Multi Field Register.
+  #define TCFC_REG_DEBUG1_MARB_THRESHOLD                                                                     (0xf<<0) // Debug only.
+  #define TCFC_REG_DEBUG1_MARB_THRESHOLD_SHIFT                                                               0
+  #define TCFC_REG_DEBUG1_WRITE_AC                                                                           (0x1<<4) // Debug only.
+  #define TCFC_REG_DEBUG1_WRITE_AC_SHIFT                                                                     4
+  #define TCFC_REG_DEBUG1_MY_VAL_AC                                                                          (0x1<<5) // Debug only.
+  #define TCFC_REG_DEBUG1_MY_VAL_AC_SHIFT                                                                    5
+  #define TCFC_REG_DEBUG1_WVAL_AC                                                                            (0x3<<6) // Debug only.
+  #define TCFC_REG_DEBUG1_WVAL_AC_SHIFT                                                                      6
+  #define TCFC_REG_DEBUG1_TYPE_FROM_REQ                                                                      (0x1<<8) // Debug only.
+  #define TCFC_REG_DEBUG1_TYPE_FROM_REQ_SHIFT                                                                8
+  #define TCFC_REG_DEBUG1_CHECK_DEL_STATE                                                                    (0x1<<9) // Debug only.
+  #define TCFC_REG_DEBUG1_CHECK_DEL_STATE_SHIFT                                                              9
+  #define TCFC_REG_DEBUG1_SW_RESET                                                                           (0x1<<10) // Debug only.
+  #define TCFC_REG_DEBUG1_SW_RESET_SHIFT                                                                     10
+  #define TCFC_REG_DEBUG1_EN_ON_INT_CLR                                                                      (0x1<<11) // Debug only.
+  #define TCFC_REG_DEBUG1_EN_ON_INT_CLR_SHIFT                                                                11
+  #define TCFC_REG_DEBUG1_UPD_CANCEL_DIS                                                                     (0x1<<12) // Debug only.
+  #define TCFC_REG_DEBUG1_UPD_CANCEL_DIS_SHIFT                                                               12
+#define TCFC_REG_OPERATION_MASK                                                                              0x2d05c8UL //Access:RW   DataWidth:0x7    // Used to mask all various types of requests.
+#define TCFC_REG_CDU_CV_ERR_MASK                                                                             0x2d05ccUL //Access:RW   DataWidth:0x3    // Error Masking Bits for CDU Context Validation Error. This is independent of the cfc_error_mask register. [2] Mask Error For DORQ Client on Virtual Functions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
+#define TCFC_REG_CDU_AV_ERR_MASK                                                                             0x2d05d0UL //Access:RW   DataWidth:0x3    // Error Masking Bits for CDU Active Validation Error. This is independent of the cfc_error_mask register. [2] Mask Error For DORQ Client on Virtual Functions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
+#define TCFC_REG_CDU_PCIE_ERR_MASK                                                                           0x2d05d4UL //Access:RW   DataWidth:0x3    // Error Masking Bits for CDU PCIE Error. This is independent of the cfc_error_mask register. [2] Mask Error For DORQ Client on Virtual Functions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
+#define TCFC_REG_ROBUSTWB_PF                                                                                 0x2d05d8UL //Access:RW   DataWidth:0x1    // Disable Robust WB change: When an inactivate request is processed do not move the LCID to Inactive state if any of the regions are in error state.
+#define TCFC_REG_SREQ_FULL_STICKY                                                                            0x2d05dcUL //Access:RW   DataWidth:0x1    // The Interface to Searcher Request Queue has reached the maximum value (4).
+#define TCFC_REG_PRSRESP_FULL_STICKY                                                                         0x2d05e0UL //Access:RW   DataWidth:0x1    // The Interface to Parser Response Queue has reached the maximum value (6).
+#define TCFC_REG_PRTY_MASK                                                                                   0x2d05e8UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define TCFC_REG_PRTY_MASK_CCAM_PAR_ERR                                                                    (0x1<<0) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS.CCAM_PAR_ERR .
+  #define TCFC_REG_PRTY_MASK_CCAM_PAR_ERR_SHIFT                                                              0
+  #define TCFC_REG_PRTY_MASK_SCAM_PAR_ERR                                                                    (0x1<<1) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS.SCAM_PAR_ERR .
+  #define TCFC_REG_PRTY_MASK_SCAM_PAR_ERR_SHIFT                                                              1
+  #define TCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTA_LSB_PAR_ERR                                                    (0x1<<2) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS.LC_QUE_RAM_PORTA_LSB_PAR_ERR .
+  #define TCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTA_LSB_PAR_ERR_SHIFT                                              2
+  #define TCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTA_MSB_PAR_ERR                                                    (0x1<<3) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS.LC_QUE_RAM_PORTA_MSB_PAR_ERR .
+  #define TCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTA_MSB_PAR_ERR_SHIFT                                              3
+  #define TCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTB_LSB_PAR_ERR                                                    (0x1<<4) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS.LC_QUE_RAM_PORTB_LSB_PAR_ERR .
+  #define TCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTB_LSB_PAR_ERR_SHIFT                                              4
+  #define TCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTB_MSB_PAR_ERR                                                    (0x1<<5) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS.LC_QUE_RAM_PORTB_MSB_PAR_ERR .
+  #define TCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTB_MSB_PAR_ERR_SHIFT                                              5
+#define TCFC_REG_NUM_LCIDS_EMPTY                                                                             0x2d0600UL //Access:R    DataWidth:0x9    // Number of Empty LCIDs in Link List Block (not allocated).
+#define TCFC_REG_NUM_LCIDS_INA                                                                               0x2d0604UL //Access:R    DataWidth:0x9    // Number of Inside not active LCIDs in Link List Block.
+#define TCFC_REG_NUM_LCIDS_IO                                                                                0x2d0608UL //Access:R    DataWidth:0x9    // Number of inside/outside LCIDs in Link List Block.
+#define TCFC_REG_LSTATE_EMPTY                                                                                0x2d060cUL //Access:R    DataWidth:0x9    // Number of LCIDs in the EMPTY state.
+#define TCFC_REG_LSTATE_ARRIVING                                                                             0x2d0610UL //Access:R    DataWidth:0x9    // Number of LCIDs in the ARRIVING state.
+#define TCFC_REG_LSTATE_INSIDE                                                                               0x2d0614UL //Access:R    DataWidth:0x9    // Number of LCIDs in the INSIDE state.
+#define TCFC_REG_LSTATE_INSIDE_NA                                                                            0x2d0618UL //Access:R    DataWidth:0x9    // Number of LCIDs in the INSIDE_NA state.
+#define TCFC_REG_LSTATE_LEAVING                                                                              0x2d061cUL //Access:R    DataWidth:0x9    // Number of LCIDs in the LEAVING state.
+#define TCFC_REG_LSTATE_I_AND_O                                                                              0x2d0620UL //Access:R    DataWidth:0x9    // Number of LCIDs in the I_AND_O state.
+#define TCFC_REG_LSTATE_BDELETED                                                                             0x2d0624UL //Access:R    DataWidth:0x9    // Number of LCIDs in the BDELETED state.
+#define TCFC_REG_MAX_INSIDE                                                                                  0x2d0628UL //Access:R    DataWidth:0x9    // Reflects the maximum value seen on the lstate_inside counter.
+#define TCFC_REG_WEAK_ENABLE_PF                                                                              0x2d0700UL //Access:RW   DataWidth:0x1    // This bit when clear will cause a load-cancel response to a load request for PF and set an execution error. Set processes load requests normally.
+#define TCFC_REG_WEAK_ENABLE_VF                                                                              0x2d0704UL //Access:RW   DataWidth:0x1    // This bit when clear will cause a load-cancel response to a load request for VF and set an execution error. Set processes load requests normally.
+#define TCFC_REG_STRONG_ENABLE_PF                                                                            0x2d0708UL //Access:RW   DataWidth:0x1    // This bit when clear will cause a CFC execution error (weak_enable will override to force load-cancel) to a search or load request for PF. The PFID that caused the execution error will be stored (exec_error_pf).
+#define TCFC_REG_STRONG_ENABLE_VF                                                                            0x2d070cUL //Access:RW   DataWidth:0x1    // This bit when clear will cause a CFC execution error (weak_enable will override to force load-cancel) to a search or load request for VF. The VFID that caused the execution error will be stored (exec_error_pf).
+#define TCFC_REG_LOADRETRY_TYPES                                                                             0x2d0710UL //Access:RW   DataWidth:0x10   // LoadRetry Enable Vector, Per Type.
+#define TCFC_REG_MINICACHE_CONTROL                                                                           0x2d0714UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define TCFC_REG_MINICACHE_CONTROL_EMPTYTHRESHMINICACHE                                                    (0x3ff<<0) // The Threshold of EmptyLCIDs which must be in the Empty State to enable the MiniCache in the Load Clients.  If there are less Empty LCIDs than this threshold, the Invalidate MiniCache signal will be asserted to the clients.
+  #define TCFC_REG_MINICACHE_CONTROL_EMPTYTHRESHMINICACHE_SHIFT                                              0
+  #define TCFC_REG_MINICACHE_CONTROL_DISABLEATTENTIONMINICACHE                                               (0x1<<10) // This field is not used in BB-B0. When set, this configuration bit will prevent the CFC from setting an Attention or hanging when the AC Counter underflows, as long as the Invalidate Minicache for that LC Client is currently asserted.
+  #define TCFC_REG_MINICACHE_CONTROL_DISABLEATTENTIONMINICACHE_SHIFT                                         10
+#define TCFC_REG_PF_MINICACHE_ENABLE                                                                         0x2d0718UL //Access:RW   DataWidth:0x1    // Enables MiniCache in Load Clients.
+#define TCFC_REG_CONTROL0                                                                                    0x2d071cUL //Access:RW   DataWidth:0x10   // Multi Field Register.
+  #define TCFC_REG_CONTROL0_WB_THRESHOLD                                                                     (0x1ff<<0) // The threshold of number of free entries for WB. If there are less free entries than the threshold a WB will be initiated.
+  #define TCFC_REG_CONTROL0_WB_THRESHOLD_SHIFT                                                               0
+  #define TCFC_REG_CONTROL0_STRING_CAM_DISABLE                                                               (0x1<<9) // When set to 1 the search string caching mechanism is disabled.
+  #define TCFC_REG_CONTROL0_STRING_CAM_DISABLE_SHIFT                                                         9
+  #define TCFC_REG_CONTROL0_CID_CAM_DISABLE                                                                  (0x1<<10) // When set to 1 the cid cam is disabled.
+  #define TCFC_REG_CONTROL0_CID_CAM_DISABLE_SHIFT                                                            10
+  #define TCFC_REG_CONTROL0_NLOE                                                                             (0x1<<11) // New Load On Error. if this bit is set and there is a load request region that is in error state then a new load request for that region will be submitted; otherwise an immediate response will be sent to the client with error.
+  #define TCFC_REG_CONTROL0_NLOE_SHIFT                                                                       11
+  #define TCFC_REG_CONTROL0_SCAM_SCRUB_HIT_EN                                                                (0x1<<12) // When set to 1 the string cam hit parity scrubbing feature is enabled.
+  #define TCFC_REG_CONTROL0_SCAM_SCRUB_HIT_EN_SHIFT                                                          12
+  #define TCFC_REG_CONTROL0_SCAM_SCRUB_MISS_EN                                                               (0x1<<13) // When set to 1 the string cam miss parity scrubbing feature is enabled.
+  #define TCFC_REG_CONTROL0_SCAM_SCRUB_MISS_EN_SHIFT                                                         13
+  #define TCFC_REG_CONTROL0_CCAM_SCRUB_HIT_EN                                                                (0x1<<14) // When set to 1 the cid cam hit parity scrubbing feature is enabled.
+  #define TCFC_REG_CONTROL0_CCAM_SCRUB_HIT_EN_SHIFT                                                          14
+  #define TCFC_REG_CONTROL0_CCAM_SCRUB_MISS_EN                                                               (0x1<<15) // When set to 1 the cid cam miss parity scrubbing feature is enabled.
+  #define TCFC_REG_CONTROL0_CCAM_SCRUB_MISS_EN_SHIFT                                                         15
+#define TCFC_REG_LCREQ_CREDIT                                                                                0x2d0740UL //Access:RW   DataWidth:0x6    // Set the initial credit for each of the load clients if less than the max is desired.
+#define TCFC_REG_LCREQ_CREDIT_SIZE                                                                           14
+#define TCFC_REG_PRSRESP_CREDIT                                                                              0x2d0780UL //Access:RW   DataWidth:0x5    // Set the initial credit for the parser response interface if less than the max is desired.
+#define TCFC_REG_SEARCH_CREDIT                                                                               0x2d0784UL //Access:RW   DataWidth:0x5    // Set the initial credit for the searcher interface if less than the max is desired.
+#define TCFC_REG_CDULD_CREDIT                                                                                0x2d0788UL //Access:RW   DataWidth:0x6    // Set the initial credit for the CDU load interface if less than the max is desired.
+#define TCFC_REG_CDUWB_CREDIT                                                                                0x2d078cUL //Access:RW   DataWidth:0x6    // Set the initial credit for the CDU write-back interface if less than the max is desired.
+#define TCFC_REG_FLOAD_RGN_MSK                                                                               0x2d07a0UL //Access:RW   DataWidth:0x8    // Array of indirect registers defines the forced load regions per type. Applicable only in the TCFC.
+#define TCFC_REG_FLOAD_RGN_MSK_SIZE                                                                          8
+#define TCFC_REG_LL_POLICY_CFG                                                                               0x2d0800UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define TCFC_REG_LL_POLICY_CFG_LL_POLICY_IO                                                                (0x3<<0) // This register is used to set the usage policy for the I/O Link List: 00: Pop LCIDs from the Head of the List (FIFO) 01: Pop LCIDs from the Tail of the List (Stack) 10: Alternate between Head and Tail of the List 11: Reserved
+  #define TCFC_REG_LL_POLICY_CFG_LL_POLICY_IO_SHIFT                                                          0
+  #define TCFC_REG_LL_POLICY_CFG_LL_POLICY_INA                                                               (0x3<<2) // This register is used to set the usage policy for the INA Link List: 00: Pop LCIDs from the Head of the List (FIFO) 01: Pop LCIDs from the Tail of the List (Stack) 10: Alternate between Head and Tail of the List 11: Reserved
+  #define TCFC_REG_LL_POLICY_CFG_LL_POLICY_INA_SHIFT                                                         2
+#define TCFC_REG_EMPTY_HEAD                                                                                  0x2d0804UL //Access:R    DataWidth:0x9    // Reserved:  This register is no longer needed in E4 B0.
+#define TCFC_REG_EMPTY_TAIL                                                                                  0x2d0808UL //Access:R    DataWidth:0x9    // Reserved:  This register is no longer needed in E4 b0.
+#define TCFC_REG_EMPTY_SIZE                                                                                  0x2d080cUL //Access:RW   DataWidth:0x9    // The size of the empty Link List is set accordingly.
+#define TCFC_REG_EIO_THRESHOLD_E5                                                                            0x2d0810UL //Access:RW   DataWidth:0x5    // When the sum of number of elements in empty list and in IO list is bigger than the value of this register, LC controller can start working on a new request. This is used in order to prevent deadlock where LC controller will acquire the (global) CID lock and then wait for an element from one of these lists on cache miss.
+#define TCFC_REG_LC_CLIENT_0_LCID_THRESHOLD                                                                  0x2d0900UL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 0 (YULD). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define TCFC_REG_LC_CLIENT_1_LCID_THRESHOLD                                                                  0x2d0904UL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 1 (XYLD). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define TCFC_REG_LC_CLIENT_2_LCID_THRESHOLD                                                                  0x2d0908UL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 2 (TMLD). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define TCFC_REG_LC_CLIENT_3_LCID_THRESHOLD                                                                  0x2d090cUL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 3 (MULD). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define TCFC_REG_LC_CLIENT_4_LCID_THRESHOLD                                                                  0x2d0910UL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 4 (YSDM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define TCFC_REG_LC_CLIENT_5_LCID_THRESHOLD                                                                  0x2d0914UL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 5 (XSDM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define TCFC_REG_LC_CLIENT_6_LCID_THRESHOLD                                                                  0x2d0918UL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 6 (USDM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define TCFC_REG_LC_CLIENT_7_LCID_THRESHOLD                                                                  0x2d091cUL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 7 (TSDM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define TCFC_REG_LC_CLIENT_8_LCID_THRESHOLD                                                                  0x2d0920UL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 8 (PSDM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define TCFC_REG_LC_CLIENT_9_LCID_THRESHOLD                                                                  0x2d0924UL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 9 (MSDM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define TCFC_REG_LC_CLIENT_10_LCID_THRESHOLD                                                                 0x2d0928UL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 10 (Timers). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define TCFC_REG_LC_CLIENT_11_LCID_THRESHOLD                                                                 0x2d092cUL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 11 (QM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define TCFC_REG_LC_CLIENT_12_LCID_THRESHOLD                                                                 0x2d0930UL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 12 (Parser). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define TCFC_REG_LC_CLIENT_13_LCID_THRESHOLD                                                                 0x2d0934UL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 13 (DORQ). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define TCFC_REG_DORQ_NODIRECT_MSG_THRESH                                                                    0x2d0938UL //Access:RW   DataWidth:0x9    // This is threshold register to disable Direct messages in the DORQ. When the number of Active LCIDs is above this value, CFC will drive a signal to DORQ to prevent it from sending direct messages to XCM.
+#define TCFC_REG_WAVE_SM_RESTART                                                                             0x2d093cUL //Access:RW   DataWidth:0x3    // This is the Restart register for the LCID Limit Waveform Generators. Each bit corresponds to one of the state machines [2:0]. Writing the bits to 1'b1 will restart the Timer in each Generator. At this time, the output of the Generator will be set to the value of the Polarity bit in the corresponding Config register. Reading this register will always return 0.
+#define TCFC_REG_LCID_LIMIT_WAVE_SM_0_CFG                                                                    0x2d0940UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define TCFC_REG_LCID_LIMIT_WAVE_SM_0_CFG_WAVE_SM_0_ENABLED                                                (0x1<<0) // This is the Enable bit for the LCID Limiting Waveform Generator #0.
+  #define TCFC_REG_LCID_LIMIT_WAVE_SM_0_CFG_WAVE_SM_0_ENABLED_SHIFT                                          0
+  #define TCFC_REG_LCID_LIMIT_WAVE_SM_0_CFG_WAVE_SM_0_POLARITY                                               (0x1<<1) // This is the Polarity bit for the LCID Limiting Waveform Generator #0. The Waveform will always output this value when the Restart bit is set.
+  #define TCFC_REG_LCID_LIMIT_WAVE_SM_0_CFG_WAVE_SM_0_POLARITY_SHIFT                                         1
+#define TCFC_REG_WAVE_SM_0_CLIENT_MASK                                                                       0x2d0944UL //Access:RW   DataWidth:0xe    // This is the list of LC Clients that will be affected by Waveform Generator #0.
+#define TCFC_REG_WAVE_SM_0_ACTIVE_THRESH                                                                     0x2d0948UL //Access:RW   DataWidth:0x9    // This is the Threshold value of active LCIDs that triggers masking by Waveform Generator #0.
+#define TCFC_REG_WAVE_SM_0_ZERO_COUNT                                                                        0x2d094cUL //Access:RW   DataWidth:0x10   // This is the count of cycles that Waveform Generator #0 will output a ZERO value.
+#define TCFC_REG_WAVE_SM_0_ONE_COUNT                                                                         0x2d0950UL //Access:RW   DataWidth:0x10   // This is the count of cycles that Waveform Generator #0 will output a ONE value.
+#define TCFC_REG_LCID_LIMIT_WAVE_SM_1_CFG                                                                    0x2d0954UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define TCFC_REG_LCID_LIMIT_WAVE_SM_1_CFG_WAVE_SM_1_ENABLED                                                (0x1<<0) // This is the Enable bit for the LCID Limiting Waveform Generator #1.
+  #define TCFC_REG_LCID_LIMIT_WAVE_SM_1_CFG_WAVE_SM_1_ENABLED_SHIFT                                          0
+  #define TCFC_REG_LCID_LIMIT_WAVE_SM_1_CFG_WAVE_SM_1_POLARITY                                               (0x1<<1) // This is the Polarity bit for the LCID Limiting Waveform Generator #1. The Waveform will always output this value when the Restart bit is set.
+  #define TCFC_REG_LCID_LIMIT_WAVE_SM_1_CFG_WAVE_SM_1_POLARITY_SHIFT                                         1
+#define TCFC_REG_WAVE_SM_1_CLIENT_MASK                                                                       0x2d0958UL //Access:RW   DataWidth:0xe    // This is the list of LC Clients that will be affected by Waveform Generator #1.
+#define TCFC_REG_WAVE_SM_1_ACTIVE_THRESH                                                                     0x2d095cUL //Access:RW   DataWidth:0x9    // This is the Threshold value of active LCIDs that triggers masking by Waveform Generator #1.
+#define TCFC_REG_WAVE_SM_1_ZERO_COUNT                                                                        0x2d0960UL //Access:RW   DataWidth:0x10   // This is the count of cycles that Waveform Generator #1 will output a ZERO value.
+#define TCFC_REG_WAVE_SM_1_ONE_COUNT                                                                         0x2d0964UL //Access:RW   DataWidth:0x10   // This is the count of cycles that Waveform Generator #1 will output a ONE value.
+#define TCFC_REG_LCID_LIMIT_WAVE_SM_2_CFG                                                                    0x2d0968UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define TCFC_REG_LCID_LIMIT_WAVE_SM_2_CFG_WAVE_SM_2_ENABLED                                                (0x1<<0) // This is the Enable bit for the LCID Limiting Waveform Generator #2.
+  #define TCFC_REG_LCID_LIMIT_WAVE_SM_2_CFG_WAVE_SM_2_ENABLED_SHIFT                                          0
+  #define TCFC_REG_LCID_LIMIT_WAVE_SM_2_CFG_WAVE_SM_2_POLARITY                                               (0x1<<1) // This is the Polarity bit for the LCID Limiting Waveform Generator #2. The Waveform will always output this value when the Restart bit is set.
+  #define TCFC_REG_LCID_LIMIT_WAVE_SM_2_CFG_WAVE_SM_2_POLARITY_SHIFT                                         1
+#define TCFC_REG_WAVE_SM_2_CLIENT_MASK                                                                       0x2d096cUL //Access:RW   DataWidth:0xe    // This is the list of LC Clients that will be affected by Waveform Generator #2.
+#define TCFC_REG_WAVE_SM_2_ACTIVE_THRESH                                                                     0x2d0970UL //Access:RW   DataWidth:0x9    // This is the Threshold value of active LCIDs that triggers masking by Waveform Generator #2.
+#define TCFC_REG_WAVE_SM_2_ZERO_COUNT                                                                        0x2d0974UL //Access:RW   DataWidth:0x10   // This is the count of cycles that Waveform Generator #2 will output a ZERO value.
+#define TCFC_REG_WAVE_SM_2_ONE_COUNT                                                                         0x2d0978UL //Access:RW   DataWidth:0x10   // This is the count of cycles that Waveform Generator #2 will output a ONE value.
+#define TCFC_REG_CACHE_STRING_TYPE                                                                           0x2d0a00UL //Access:RW   DataWidth:0x8    // Mask vector for enabling caching on various string types. Each bit in this register matches the corresponding String Type. Bit[0]   = TCP Bit[1]   = UDP Bit[2]   = RoCE Multicast Bit[3]   = RoCE Unicast Bit[4]   = FCoE Bit[5]   = OpenFlow Bit[6]   = GFT Bit[7]   = Reserved
+#define TCFC_REG_SCAM_CACHE_ENABLES                                                                          0x2d0a04UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define TCFC_REG_SCAM_CACHE_ENABLES_ENABLE_NO_MATCH_CACHING                                                (0x1<<0) // When set, the String CAM will be used to cache results from the Searcher that did not match an entry in the external tables.
+  #define TCFC_REG_SCAM_CACHE_ENABLES_ENABLE_NO_MATCH_CACHING_SHIFT                                          0
+  #define TCFC_REG_SCAM_CACHE_ENABLES_ENABLE_L2_CACHING                                                      (0x1<<1) // When set, the String CAM will be used to cache results from the Searcher that Matched on an L2 Filter.
+  #define TCFC_REG_SCAM_CACHE_ENABLES_ENABLE_L2_CACHING_SHIFT                                                1
+#define TCFC_REG_CCAM_MASK_VECTOR                                                                            0x2d0a08UL //Access:RW   DataWidth:0x20   // CID CAM Mask.  This mask is used for Searches and Writes to the CID CAM. Setting a bit to 0 will ignore that bit in a search. Setting a bit to 0 will clear that bit on a write.
+#define TCFC_REG_CCAM_SEARCH                                                                                 0x2d0a0cUL //Access:RW   DataWidth:0x1    // When this bit is set writing to the ccam will cause a search operation on the written item (written using CFC_REGISTERS_LCID_CID_CAM.CID_CAM interface. the write can be to any address).
+#define TCFC_REG_SCAM_HASH_KEY0                                                                              0x2d0a10UL //Access:RW   DataWidth:0x20   // Key for String Cam Hash Algorithm, Bits[31:0].
+#define TCFC_REG_SCAM_HASH_KEY1                                                                              0x2d0a14UL //Access:RW   DataWidth:0x20   // Key for String Cam Hash Algorithm, Bits[63:32].
+#define TCFC_REG_SCAM_HASH_KEY2                                                                              0x2d0a18UL //Access:RW   DataWidth:0x20   // Key for String Cam Hash Algorithm, Bits[95:64].
+#define TCFC_REG_SCAM_HASH_KEY3                                                                              0x2d0a1cUL //Access:RW   DataWidth:0x20   // Key for String Cam Hash Algorithm, Bits[127:96].
+#define TCFC_REG_SCAM_HASH_KEY4                                                                              0x2d0a20UL //Access:RW   DataWidth:0x20   // Key for String Cam Hash Algorithm, Bits[159:128].
+#define TCFC_REG_SCAM_HASH_KEY5                                                                              0x2d0a24UL //Access:RW   DataWidth:0x20   // Key for String Cam Hash Algorithm, Bits[191:160].
+#define TCFC_REG_SCAM_HASH_KEY6                                                                              0x2d0a28UL //Access:RW   DataWidth:0x20   // Key for String Cam Hash Algorithm, Bits[223:192].
+#define TCFC_REG_SCAM_HASH_KEY7                                                                              0x2d0a2cUL //Access:RW   DataWidth:0x20   // Key for String Cam Hash Algorithm, Bits[255:224].
+#define TCFC_REG_SCAM_HASH_KEY8                                                                              0x2d0a30UL //Access:RW   DataWidth:0x20   // Key for String Cam Hash Algorithm, Bits[287:256].
+#define TCFC_REG_SCAM_HASH_KEY9                                                                              0x2d0a34UL //Access:RW   DataWidth:0x18   // Key for String Cam Hash Algorithm, Bits[311:288].
+#define TCFC_REG_SCAM_SEARCH                                                                                 0x2d0a38UL //Access:RW   DataWidth:0x1    // When this bit is set writing to the scam will cause a search operation on the written item (written using CFC_REGISTERS_LCID_STRING_CAM.STRING_CAM interface. the write can be to any address).
+#define TCFC_REG_SEARCH_RESULT                                                                               0x2d0a3cUL //Access:R    DataWidth:0xa    // {HIT;LCID}. HIT - if set then previous CAM seach item (either CCAM or SCAM) was found. LCID contains the result in case CAM search item (either CCAM or SCAM) was found.
+#define TCFC_REG_INCLUDE_TID_IN_HASH                                                                         0x2d0a40UL //Access:RW   DataWidth:0x1    // Added in E4B0. 0 - tid is not included in hash calculation (like in A0). 1 - tid is included in hash calculation by XORing TID[32:16] and TID[15:0] to the hash result. In this case, TID mask bit should be zero.
+#define TCFC_REG_INCLUDE_VLAN_IN_HASH                                                                        0x2d0a44UL //Access:RW   DataWidth:0x1    // Added in E4B0. 0 - vlan is not included in hash calculation (like in A0). 1 - vlan is included in hash calculation by XORing VLAN [11:0] to the hash result. In this case, promiscuous VLAN bit should be zero.
+#define TCFC_REG_CID_CAM_BIST_EN                                                                             0x2d0b00UL //Access:RW   DataWidth:0x1    // Used to enable/disable BIST mode on the CID CAM. When set, BIST testing will be performed and the results will be posted upon completion. When cleared CAM access will be enabled through the CAM BIST mechanism instead.
+#define TCFC_REG_CID_CAM_BIST_SKIP_ERROR_CNT                                                                 0x2d0b04UL //Access:RW   DataWidth:0x8    // Provides a threshold for the number of CID CAM BIST errors that are acceptable before reporting CAM BIST failure status.
+#define TCFC_REG_CID_CAM_BIST_STATUS_SEL                                                                     0x2d0b08UL //Access:RW   DataWidth:0x8    // Used to select the CID CAM BIST status word to read following the completion of a BIST test. Also used to select the data slice when writing data directly to the CAM using the CAM BIST mechanism.
+#define TCFC_REG_CID_CAM_BIST_STATUS                                                                         0x2d0b0cUL //Access:R    DataWidth:0x20   // Provides read-only access to the CID CAM BIST status word selected by cid_cam_bist_status_sel.
+#define TCFC_REG_STRING_CAM_BIST_EN                                                                          0x2d0b10UL //Access:RW   DataWidth:0x1    // Used to enable/disable BIST mode on the STRING CAM. When set, BIST testing will be performed and the results will be posted upon completion. When cleared CAM access will be enabled through the CAM BIST mechanism instead.
+#define TCFC_REG_STRING_CAM_BIST_SKIP_ERROR_CNT                                                              0x2d0b14UL //Access:RW   DataWidth:0x8    // Provides a threshold for the number of STRING CAM BIST errors that are acceptable before reporting CAM BIST failure status.
+#define TCFC_REG_STRING_CAM_BIST_STATUS_SEL                                                                  0x2d0b18UL //Access:RW   DataWidth:0x8    // Used to select the STRING CAM BIST status word to read following the completion of a BIST test. Also used to select the data slice when writing data directly to the CAM using the CAM BIST mechanism.
+#define TCFC_REG_STRING_CAM_BIST_STATUS                                                                      0x2d0b1cUL //Access:R    DataWidth:0x20   // Provides read-only access to the STRING CAM BIST status word selected by string_cam_bist_status_sel.
+#define TCFC_REG_LC_QUE                                                                                      0x2d8000UL //Access:WB   DataWidth:0x36   // Load client queue ram access.
+#define TCFC_REG_LC_QUE_SIZE                                                                                 324
+#define TCFC_REG_ACTIVITY_COUNTER                                                                            0x2d8800UL //Access:RW   DataWidth:0x10   // Activity counter ram access.
+#define TCFC_REG_ACTIVITY_COUNTER_SIZE                                                                       320
+#define TCFC_REG_INFO_STATE                                                                                  0x2d9000UL //Access:R    DataWidth:0x13   // Info store state machines = {lcid_curr_state;region_states}.
+#define TCFC_REG_INFO_STATE_SIZE                                                                             320
+#define TCFC_REG_INFO_REG                                                                                    0x2d9800UL //Access:R    DataWidth:0xe    // Info store register = {fid;type;cvld;ofl}.
+#define TCFC_REG_INFO_REG_SIZE                                                                               320
+#define TCFC_REG_LINK_LIST                                                                                   0x2da000UL //Access:RW   DataWidth:0x12   // Link List ram access; data = {prev_pfid;prev_lcid;next_pfid;next_lcid}.
+#define TCFC_REG_LINK_LIST_SIZE                                                                              320
+#define TCFC_REG_CID_CAM                                                                                     0x2db000UL //Access:WB   DataWidth:0x21   // CID cam  access (Valid - 32;31:0 - Data).
+#define TCFC_REG_CID_CAM_SIZE                                                                                640
+#define TCFC_REG_STRING_CAM                                                                                  0x2dc000UL //Access:WB   DataWidth:0x18   // String CAM Access Register (Hash[23:0])
+#define TCFC_REG_STRING_CAM_SIZE                                                                             8
+#define TCFC_REG_TID_LOCK_RAM                                                                                0x2dc800UL //Access:RW   DataWidth:0xc    // TID Lock RAM Access Register [11]      = Locked [10]      = In Use [09:00]   = Usage Counter Value
+#define TCFC_REG_TID_LOCK_RAM_SIZE                                                                           320
+#define TCFC_REG_VPF1_LSTATE_SEL                                                                             0x2dd000UL //Access:RW   DataWidth:0x7    // State select vector for VF/PF LCID state counter 1 .
+#define TCFC_REG_VPF2_LSTATE_SEL                                                                             0x2dd004UL //Access:RW   DataWidth:0x7    // State select vector for VF/PF LCID state counter 2 .
+#define TCFC_REG_VF_LSTATE_CNT1                                                                              0x2dd008UL //Access:R    DataWidth:0x9    // VF port to VF/PF LCID state counter 1 .
+#define TCFC_REG_PF_LSTATE_CNT1                                                                              0x2dd00cUL //Access:R    DataWidth:0x9    // PF port to VF/PF LCID state counter 1 .
+#define TCFC_REG_VF_LSTATE_CNT2                                                                              0x2dd010UL //Access:R    DataWidth:0x9    // VF port to VF/PF LCID state counter 2 .
+#define TCFC_REG_PF_LSTATE_CNT2                                                                              0x2dd014UL //Access:R    DataWidth:0x9    // PF port to VF/PF LCID state counter 2 .
+#define CCFC_REG_INIT_REG                                                                                    0x2e0000UL //Access:RW   DataWidth:0xd    // Multi Field Register.
+  #define CCFC_REG_INIT_REG_AC_INIT                                                                          (0x1<<0) // When set activity counter ram will be initialized to zeros. when this operation is completed CFC_REGISTERS_AC_INITDONE.AC_INIT_DONE will be set.
+  #define CCFC_REG_INIT_REG_AC_INIT_SHIFT                                                                    0
+  #define CCFC_REG_INIT_REG_LL_INIT_LAST_LCID                                                                (0x1ff<<1) // This field is only relevant when setting CFC_REGISTERS_INIT_REG.LL_INIT . indicates the last lcid to be used by the CFC. this field can strict the CFC to work will less than 320 LCIDs.
+  #define CCFC_REG_INIT_REG_LL_INIT_LAST_LCID_SHIFT                                                          1
+  #define CCFC_REG_INIT_REG_LL_INIT                                                                          (0x1<<10) // When set link list ram will be initialized - all LCIDs will be located in the empty link list. when this operation completes CFC_REGISTERS_LL_INITDONE.LL_INIT_DONE will be set.
+  #define CCFC_REG_INIT_REG_LL_INIT_SHIFT                                                                    10
+  #define CCFC_REG_INIT_REG_CAM_INIT                                                                         (0x1<<11) // When set the CFC CAMs will be initialized to zeros. When this operation completes CFC_REGISTERS_CAM_INITDONE.CAM_INIT_DONE will be set.
+  #define CCFC_REG_INIT_REG_CAM_INIT_SHIFT                                                                   11
+  #define CCFC_REG_INIT_REG_TIDRAM_INIT                                                                      (0x1<<12) // Setting this bit causes the TID Lock RAM to be initialized. This cannot be set during normal operation -- the block must be idle or the request will be ignored. When this operation completes CFC_REGISTERS_TIDRAM_INITDONE.TIDRAM_INIT_DONE will be set.
+  #define CCFC_REG_INIT_REG_TIDRAM_INIT_SHIFT                                                                12
+#define CCFC_REG_LL_INIT_DONE                                                                                0x2e0004UL //Access:R    DataWidth:0x1    // Indication the initializing the link list by the hardware was done.
+#define CCFC_REG_AC_INIT_DONE                                                                                0x2e0008UL //Access:R    DataWidth:0x1    // Indication the initializing the activity counter by the hardware was done.
+#define CCFC_REG_CAM_INIT_DONE                                                                               0x2e000cUL //Access:R    DataWidth:0x1    // Indication that initializing the cams by the hardware was done.
+#define CCFC_REG_TIDRAM_INIT_DONE                                                                            0x2e0010UL //Access:R    DataWidth:0x1    // This bit does not exist for CCFC and will always read '1'.
+#define CCFC_REG_INT_STS_0                                                                                   0x2e0180UL //Access:R    DataWidth:0x2    // Multi Field Register.
+  #define CCFC_REG_INT_STS_0_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define CCFC_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                             0
+  #define CCFC_REG_INT_STS_0_EXE_ERROR                                                                       (0x1<<1) // Interrupt indicating that an execution error has occurred.
+  #define CCFC_REG_INT_STS_0_EXE_ERROR_SHIFT                                                                 1
+#define CCFC_REG_INT_MASK_0                                                                                  0x2e0184UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define CCFC_REG_INT_MASK_0_ADDRESS_ERROR                                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: CCFC_REG_INT_STS_0.ADDRESS_ERROR .
+  #define CCFC_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                            0
+  #define CCFC_REG_INT_MASK_0_EXE_ERROR                                                                      (0x1<<1) // This bit masks, when set, the Interrupt bit: CCFC_REG_INT_STS_0.EXE_ERROR .
+  #define CCFC_REG_INT_MASK_0_EXE_ERROR_SHIFT                                                                1
+#define CCFC_REG_INT_STS_WR_0                                                                                0x2e0188UL //Access:WR   DataWidth:0x2    // Multi Field Register.
+  #define CCFC_REG_INT_STS_WR_0_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define CCFC_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                          0
+  #define CCFC_REG_INT_STS_WR_0_EXE_ERROR                                                                    (0x1<<1) // Interrupt indicating that an execution error has occurred.
+  #define CCFC_REG_INT_STS_WR_0_EXE_ERROR_SHIFT                                                              1
+#define CCFC_REG_INT_STS_CLR_0                                                                               0x2e018cUL //Access:RC   DataWidth:0x2    // Multi Field Register.
+  #define CCFC_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                               (0x1<<0) // Signals an unknown address to the rf module.
+  #define CCFC_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                         0
+  #define CCFC_REG_INT_STS_CLR_0_EXE_ERROR                                                                   (0x1<<1) // Interrupt indicating that an execution error has occurred.
+  #define CCFC_REG_INT_STS_CLR_0_EXE_ERROR_SHIFT                                                             1
+#define CCFC_REG_PRTY_MASK_H_0_BB_K2                                                                         0x2e0204UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define CCFC_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_K2                                                   (0x1<<0) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
+  #define CCFC_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_K2_SHIFT                                             0
+  #define CCFC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                     (0x1<<1) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define CCFC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                               1
+#define CCFC_REG_MEM_ECC_ENABLE_0_BB_K2                                                                      0x2e0210UL //Access:RW   DataWidth:0x1    // Enable ECC for memory ecc instance ccfc.i_cfc_core.CCFC_STR_CAM_GEN_IF.i_cfc_sinfo_ram.i_ecc in module cfc_sinfo_ram
+#define CCFC_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                 0x2e0214UL //Access:RW   DataWidth:0x1    // Set parity only for memory ecc instance ccfc.i_cfc_core.CCFC_STR_CAM_GEN_IF.i_cfc_sinfo_ram.i_ecc in module cfc_sinfo_ram
+#define CCFC_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                             0x2e0218UL //Access:RC   DataWidth:0x1    // Record if a correctable error occurred on memory ecc instance ccfc.i_cfc_core.CCFC_STR_CAM_GEN_IF.i_cfc_sinfo_ram.i_ecc in module cfc_sinfo_ram
+#define CCFC_REG_MEM_ECC_EVENTS_BB_K2                                                                        0x2e021cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define CCFC_REG_LC_BLOCKED                                                                                  0x2e0400UL //Access:RC   DataWidth:0x20   // Statistics register that counts cycles in which load context requests were blocked.
+#define CCFC_REG_TID_LOCK_INC_STAT                                                                           0x2e0404UL //Access:RC   DataWidth:0x20   // This statistic counts the number of cycles in which a Primary Lock condition exists when it was caused by an Increment command on a previously locked LTID. Note that this counts the number of cycles in which this condition exists, not the number of times it occurred.
+#define CCFC_REG_TID_LOCK_LOCK_STAT                                                                          0x2e0408UL //Access:RC   DataWidth:0x20   // This statistic counts the number of cycles in which a Primary Lock condition exists when it was caused by an Lock command on a previously locked LTID. Note that this counts the number of cycles in which this condition exists, not the number of times it occurred.
+#define CCFC_REG_RFE_TASK_COUNTER                                                                            0x2e040cUL //Access:RC   DataWidth:0x20   // Counts number of tasks executed by the RFE controller.
+#define CCFC_REG_LC_STAT_MASK                                                                                0x2e0410UL //Access:RW   DataWidth:0xe    // Used to mask the various load client queues for LC task statistics.
+#define CCFC_REG_LC_TASK_COUNTER                                                                             0x2e0414UL //Access:RC   DataWidth:0x20   // Counts number of tasks executed by the load client controller.
+#define CCFC_REG_MISC_TASK_COUNTER                                                                           0x2e0418UL //Access:RC   DataWidth:0x20   // Counts number of tasks executed by the miscellaneous controller.
+#define CCFC_REG_LOAD_CONTEXT_HITS                                                                           0x2e041cUL //Access:RC   DataWidth:0x20   // Counts the number of load context hits for the load clients selected by lc_stat_mask.
+#define CCFC_REG_LOAD_CONTEXT_MISSES                                                                         0x2e0420UL //Access:RC   DataWidth:0x20   // Counts the number of load context misses for the load clients selected by lc_stat_mask.
+#define CCFC_REG_RFE_SEARCH_HITS                                                                             0x2e0424UL //Access:RC   DataWidth:0x20   // Counts the number of RFE serach hits.
+#define CCFC_REG_RFE_SEARCH_MISSES                                                                           0x2e0428UL //Access:RC   DataWidth:0x20   // Counts the number of RFE serach misses.
+#define CCFC_REG_CDU_WRITE_BACKS                                                                             0x2e042cUL //Access:RC   DataWidth:0x20   // Counts the number of CDU write backs submitted by CFC.
+#define CCFC_REG_DBG_SELECT                                                                                  0x2e0500UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define CCFC_REG_DBG_DWORD_ENABLE                                                                            0x2e0504UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define CCFC_REG_DBG_SHIFT                                                                                   0x2e0508UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define CCFC_REG_DBG_FORCE_VALID                                                                             0x2e050cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define CCFC_REG_DBG_FORCE_FRAME                                                                             0x2e0510UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define CCFC_REG_DBG_OUT_DATA                                                                                0x2e0520UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define CCFC_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define CCFC_REG_DBG_OUT_VALID                                                                               0x2e0540UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define CCFC_REG_DBG_OUT_FRAME                                                                               0x2e0544UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define CCFC_REG_ECO_RESERVED                                                                                0x2e0548UL //Access:RW   DataWidth:0x8    // Eco reserved.  bit0: Chicken bit for CQ73536 fix. When '0' takes into account LCIDs in the pipe. When '1' behaces as A0.
+#define CCFC_REG_ERROR_VECTOR                                                                                0x2e054cUL //Access:R    DataWidth:0x11   // CFC error vector. when the CFC detects an internal error it will set one of these bits. the bit description can be found in CFC specifications.
+#define CCFC_REG_ERROR_MASK                                                                                  0x2e0550UL //Access:RW   DataWidth:0x11   // Masking for error logging. if a bit in this field is set then the corresponding bit in CFC_REGISTERS_CFC_ERROR_VECTOR.ERROR_VECTOR will not be set.
+#define CCFC_REG_DISABLE_ON_ERROR                                                                            0x2e0554UL //Access:RW   DataWidth:0x11   // Indicates per error (in CFC_REGISTERS_CFC_ERROR_VECTOR.CFC_ERROR vector) whether the cfc should be disabled upon it.
+#define CCFC_REG_ERROR_DATA1                                                                                 0x2e0558UL //Access:R    DataWidth:0x20   // When the CFC detects an internal error it updates these fields. [31:28] -- CFC Controller ID [20:16] -- CFC Client ID [15:08] -- Requested Regions [04:00] -- Error ID Note that the Error ID starts counting at 0x1 so that there will always be a bit set in the ID.  This means it is always 1 greater than the bit in the error_vector register which caused the error.  See the CFC EAS document for more details.
+#define CCFC_REG_ERROR_DATA2                                                                                 0x2e055cUL //Access:R    DataWidth:0x20   // When the CFC detects an internal error it updates these fields. [31:00] -- CID
+#define CCFC_REG_ERROR_DATA3                                                                                 0x2e0560UL //Access:R    DataWidth:0x20   // When the CFC detects an internal error it updates these fields. [24:16] -- Request LCID [08:00] -- Active LCID
+#define CCFC_REG_ERROR_DATA4                                                                                 0x2e0564UL //Access:R    DataWidth:0x20   // When the CFC detects an internal error it updates these fields. [23:16] -- Increment Value [15:12] -- Type Field [08:00] -- AC LCID
+#define CCFC_REG_ARBITERS_REG                                                                                0x2e0568UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define CCFC_REG_ARBITERS_REG_SP_LC_DONE_ARB                                                               (0x1<<0) // When set CFC arbiter1 will work in strict priority.
+  #define CCFC_REG_ARBITERS_REG_SP_LC_DONE_ARB_SHIFT                                                         0
+  #define CCFC_REG_ARBITERS_REG_SP_LC_REQ_ARB                                                                (0x1<<1) // When set load context arbiter will work in strict priority.
+  #define CCFC_REG_ARBITERS_REG_SP_LC_REQ_ARB_SHIFT                                                          1
+  #define CCFC_REG_ARBITERS_REG_SP_LC_INP_ARB                                                                (0x1<<2) // When set CFC arbiter2 will work in strict priority.
+  #define CCFC_REG_ARBITERS_REG_SP_LC_INP_ARB_SHIFT                                                          2
+  #define CCFC_REG_ARBITERS_REG_SP_MISC_ARB                                                                  (0x1<<3) // When set CFC arbiter3 will work in strict priority.
+  #define CCFC_REG_ARBITERS_REG_SP_MISC_ARB_SHIFT                                                            3
+  #define CCFC_REG_ARBITERS_REG_SP_AC_DEC                                                                    (0x1<<4) // When set activity counter decrement arbiter will work in strict priority.
+  #define CCFC_REG_ARBITERS_REG_SP_AC_DEC_SHIFT                                                              4
+  #define CCFC_REG_ARBITERS_REG_SP_AC_INC                                                                    (0x1<<5) // When set activity counter increment arbiter will work in strict priority.
+  #define CCFC_REG_ARBITERS_REG_SP_AC_INC_SHIFT                                                              5
+#define CCFC_REG_LCREQ_WEIGHTS                                                                               0x2e0580UL //Access:RW   DataWidth:0x3    // This field allows changing the priorities of the weighted-round-robin arbiter which selects which CFC load client should be served next.
+#define CCFC_REG_LCREQ_WEIGHTS_SIZE                                                                          14
+#define CCFC_REG_DEBUG0                                                                                      0x2e05c0UL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define CCFC_REG_DEBUG0_DISABLE_INPUTS                                                                     (0x1<<0) // This bit disables the inputs on the CFC.
+  #define CCFC_REG_DEBUG0_DISABLE_INPUTS_SHIFT                                                               0
+  #define CCFC_REG_DEBUG0_DISABLE_OUTPUTS                                                                    (0x1<<1) // This bit disables the outputs of the CFC.
+  #define CCFC_REG_DEBUG0_DISABLE_OUTPUTS_SHIFT                                                              1
+  #define CCFC_REG_DEBUG0_AC_COUNTER_ZERO                                                                    (0xff<<2) // Debug only.
+  #define CCFC_REG_DEBUG0_AC_COUNTER_ZERO_SHIFT                                                              2
+  #define CCFC_REG_DEBUG0_AC_GRANT_PERIOD                                                                    (0xf<<10) // This register is not used in BB-B0. Reduced width to 1 bit to keep its address.
+  #define CCFC_REG_DEBUG0_AC_GRANT_PERIOD_SHIFT                                                              10
+  #define CCFC_REG_DEBUG0_E_THRESHOLD                                                                        (0x7<<14) // Debug only.
+  #define CCFC_REG_DEBUG0_E_THRESHOLD_SHIFT                                                                  14
+  #define CCFC_REG_DEBUG0_INA_THRESHOLD                                                                      (0x7<<17) // Debug only.
+  #define CCFC_REG_DEBUG0_INA_THRESHOLD_SHIFT                                                                17
+  #define CCFC_REG_DEBUG0_IO_THRESHOLD                                                                       (0x7<<20) // Debug only.
+  #define CCFC_REG_DEBUG0_IO_THRESHOLD_SHIFT                                                                 20
+#define CCFC_REG_DEBUG1                                                                                      0x2e05c4UL //Access:RW   DataWidth:0xd    // Multi Field Register.
+  #define CCFC_REG_DEBUG1_MARB_THRESHOLD                                                                     (0xf<<0) // Debug only.
+  #define CCFC_REG_DEBUG1_MARB_THRESHOLD_SHIFT                                                               0
+  #define CCFC_REG_DEBUG1_WRITE_AC                                                                           (0x1<<4) // Debug only.
+  #define CCFC_REG_DEBUG1_WRITE_AC_SHIFT                                                                     4
+  #define CCFC_REG_DEBUG1_MY_VAL_AC                                                                          (0x1<<5) // Debug only.
+  #define CCFC_REG_DEBUG1_MY_VAL_AC_SHIFT                                                                    5
+  #define CCFC_REG_DEBUG1_WVAL_AC                                                                            (0x3<<6) // Debug only.
+  #define CCFC_REG_DEBUG1_WVAL_AC_SHIFT                                                                      6
+  #define CCFC_REG_DEBUG1_TYPE_FROM_REQ                                                                      (0x1<<8) // Debug only.
+  #define CCFC_REG_DEBUG1_TYPE_FROM_REQ_SHIFT                                                                8
+  #define CCFC_REG_DEBUG1_CHECK_DEL_STATE                                                                    (0x1<<9) // Debug only.
+  #define CCFC_REG_DEBUG1_CHECK_DEL_STATE_SHIFT                                                              9
+  #define CCFC_REG_DEBUG1_SW_RESET                                                                           (0x1<<10) // Debug only.
+  #define CCFC_REG_DEBUG1_SW_RESET_SHIFT                                                                     10
+  #define CCFC_REG_DEBUG1_EN_ON_INT_CLR                                                                      (0x1<<11) // Debug only.
+  #define CCFC_REG_DEBUG1_EN_ON_INT_CLR_SHIFT                                                                11
+  #define CCFC_REG_DEBUG1_UPD_CANCEL_DIS                                                                     (0x1<<12) // Debug only.
+  #define CCFC_REG_DEBUG1_UPD_CANCEL_DIS_SHIFT                                                               12
+#define CCFC_REG_OPERATION_MASK                                                                              0x2e05c8UL //Access:RW   DataWidth:0x7    // Used to mask all various types of requests.
+#define CCFC_REG_CDU_CV_ERR_MASK                                                                             0x2e05ccUL //Access:RW   DataWidth:0x3    // Error Masking Bits for CDU Context Validation Error. This is independent of the cfc_error_mask register. [2] Mask Error For DORQ Client on Virtual Functions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
+#define CCFC_REG_CDU_AV_ERR_MASK                                                                             0x2e05d0UL //Access:RW   DataWidth:0x3    // Error Masking Bits for CDU Active Validation Error. This is independent of the cfc_error_mask register. [2] Mask Error For DORQ Client on Virtual Functions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
+#define CCFC_REG_CDU_PCIE_ERR_MASK                                                                           0x2e05d4UL //Access:RW   DataWidth:0x3    // Error Masking Bits for CDU PCIE Error. This is independent of the cfc_error_mask register. [2] Mask Error For DORQ Client on Virtual Functions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
+#define CCFC_REG_ROBUSTWB_PF                                                                                 0x2e05d8UL //Access:RW   DataWidth:0x1    // Disable Robust WB change: When an inactivate request is processed do not move the LCID to Inactive state if any of the regions are in error state.
+#define CCFC_REG_SREQ_FULL_STICKY                                                                            0x2e05dcUL //Access:RW   DataWidth:0x1    // The Interface to Searcher Request Queue has reached the maximum value (4).
+#define CCFC_REG_PRSRESP_FULL_STICKY                                                                         0x2e05e0UL //Access:RW   DataWidth:0x1    // The Interface to Parser Response Queue has reached the maximum value (6).
+#define CCFC_REG_PRTY_MASK                                                                                   0x2e05e8UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define CCFC_REG_PRTY_MASK_CCAM_PAR_ERR                                                                    (0x1<<0) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS.CCAM_PAR_ERR .
+  #define CCFC_REG_PRTY_MASK_CCAM_PAR_ERR_SHIFT                                                              0
+  #define CCFC_REG_PRTY_MASK_SCAM_PAR_ERR                                                                    (0x1<<1) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS.SCAM_PAR_ERR .
+  #define CCFC_REG_PRTY_MASK_SCAM_PAR_ERR_SHIFT                                                              1
+  #define CCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTA_LSB_PAR_ERR                                                    (0x1<<2) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS.LC_QUE_RAM_PORTA_LSB_PAR_ERR .
+  #define CCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTA_LSB_PAR_ERR_SHIFT                                              2
+  #define CCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTA_MSB_PAR_ERR                                                    (0x1<<3) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS.LC_QUE_RAM_PORTA_MSB_PAR_ERR .
+  #define CCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTA_MSB_PAR_ERR_SHIFT                                              3
+  #define CCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTB_LSB_PAR_ERR                                                    (0x1<<4) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS.LC_QUE_RAM_PORTB_LSB_PAR_ERR .
+  #define CCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTB_LSB_PAR_ERR_SHIFT                                              4
+  #define CCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTB_MSB_PAR_ERR                                                    (0x1<<5) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS.LC_QUE_RAM_PORTB_MSB_PAR_ERR .
+  #define CCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTB_MSB_PAR_ERR_SHIFT                                              5
+#define CCFC_REG_NUM_LCIDS_EMPTY                                                                             0x2e0600UL //Access:R    DataWidth:0x9    // Number of Empty LCIDs in Link List Block (not allocated).
+#define CCFC_REG_NUM_LCIDS_INA                                                                               0x2e0604UL //Access:R    DataWidth:0x9    // Number of Inside not active LCIDs in Link List Block.
+#define CCFC_REG_NUM_LCIDS_IO                                                                                0x2e0608UL //Access:R    DataWidth:0x9    // Number of inside/outside LCIDs in Link List Block.
+#define CCFC_REG_LSTATE_EMPTY                                                                                0x2e060cUL //Access:R    DataWidth:0x9    // Number of LCIDs in the EMPTY state.
+#define CCFC_REG_LSTATE_ARRIVING                                                                             0x2e0610UL //Access:R    DataWidth:0x9    // Number of LCIDs in the ARRIVING state.
+#define CCFC_REG_LSTATE_INSIDE                                                                               0x2e0614UL //Access:R    DataWidth:0x9    // Number of LCIDs in the INSIDE state.
+#define CCFC_REG_LSTATE_INSIDE_NA                                                                            0x2e0618UL //Access:R    DataWidth:0x9    // Number of LCIDs in the INSIDE_NA state.
+#define CCFC_REG_LSTATE_LEAVING                                                                              0x2e061cUL //Access:R    DataWidth:0x9    // Number of LCIDs in the LEAVING state.
+#define CCFC_REG_LSTATE_I_AND_O                                                                              0x2e0620UL //Access:R    DataWidth:0x9    // Number of LCIDs in the I_AND_O state.
+#define CCFC_REG_LSTATE_BDELETED                                                                             0x2e0624UL //Access:R    DataWidth:0x9    // Number of LCIDs in the BDELETED state.
+#define CCFC_REG_MAX_INSIDE                                                                                  0x2e0628UL //Access:R    DataWidth:0x9    // Reflects the maximum value seen on the lstate_inside counter.
+#define CCFC_REG_WEAK_ENABLE_PF                                                                              0x2e0700UL //Access:RW   DataWidth:0x1    // This bit when clear will cause a load-cancel response to a load request for PF and set an execution error. Set processes load requests normally.
+#define CCFC_REG_WEAK_ENABLE_VF                                                                              0x2e0704UL //Access:RW   DataWidth:0x1    // This bit when clear will cause a load-cancel response to a load request for VF and set an execution error. Set processes load requests normally.
+#define CCFC_REG_STRONG_ENABLE_PF                                                                            0x2e0708UL //Access:RW   DataWidth:0x1    // This bit when clear will cause a CFC execution error (weak_enable will override to force load-cancel) to a search or load request for PF. The PFID that caused the execution error will be stored (exec_error_pf).
+#define CCFC_REG_STRONG_ENABLE_VF                                                                            0x2e070cUL //Access:RW   DataWidth:0x1    // This bit when clear will cause a CFC execution error (weak_enable will override to force load-cancel) to a search or load request for VF. The VFID that caused the execution error will be stored (exec_error_pf).
+#define CCFC_REG_LOADRETRY_TYPES                                                                             0x2e0710UL //Access:RW   DataWidth:0x10   // LoadRetry Enable Vector, Per Type.
+#define CCFC_REG_MINICACHE_CONTROL                                                                           0x2e0714UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define CCFC_REG_MINICACHE_CONTROL_EMPTYTHRESHMINICACHE                                                    (0x3ff<<0) // The Threshold of EmptyLCIDs which must be in the Empty State to enable the MiniCache in the Load Clients.  If there are less Empty LCIDs than this threshold, the Invalidate MiniCache signal will be asserted to the clients.
+  #define CCFC_REG_MINICACHE_CONTROL_EMPTYTHRESHMINICACHE_SHIFT                                              0
+  #define CCFC_REG_MINICACHE_CONTROL_DISABLEATTENTIONMINICACHE                                               (0x1<<10) // This field is not used in BB-B0. When set, this configuration bit will prevent the CFC from setting an Attention or hanging when the AC Counter underflows, as long as the Invalidate Minicache for that LC Client is currently asserted.
+  #define CCFC_REG_MINICACHE_CONTROL_DISABLEATTENTIONMINICACHE_SHIFT                                         10
+#define CCFC_REG_PF_MINICACHE_ENABLE                                                                         0x2e0718UL //Access:RW   DataWidth:0x1    // Enables MiniCache in Load Clients.
+#define CCFC_REG_CONTROL0                                                                                    0x2e071cUL //Access:RW   DataWidth:0x10   // Multi Field Register.
+  #define CCFC_REG_CONTROL0_WB_THRESHOLD                                                                     (0x1ff<<0) // The threshold of number of free entries for WB. If there are less free entries than the threshold a WB will be initiated.
+  #define CCFC_REG_CONTROL0_WB_THRESHOLD_SHIFT                                                               0
+  #define CCFC_REG_CONTROL0_STRING_CAM_DISABLE                                                               (0x1<<9) // When set to 1 the search string caching mechanism is disabled.
+  #define CCFC_REG_CONTROL0_STRING_CAM_DISABLE_SHIFT                                                         9
+  #define CCFC_REG_CONTROL0_CID_CAM_DISABLE                                                                  (0x1<<10) // When set to 1 the cid cam is disabled.
+  #define CCFC_REG_CONTROL0_CID_CAM_DISABLE_SHIFT                                                            10
+  #define CCFC_REG_CONTROL0_NLOE                                                                             (0x1<<11) // New Load On Error. if this bit is set and there is a load request region that is in error state then a new load request for that region will be submitted; otherwise an immediate response will be sent to the client with error.
+  #define CCFC_REG_CONTROL0_NLOE_SHIFT                                                                       11
+  #define CCFC_REG_CONTROL0_SCAM_SCRUB_HIT_EN                                                                (0x1<<12) // When set to 1 the string cam hit parity scrubbing feature is enabled.
+  #define CCFC_REG_CONTROL0_SCAM_SCRUB_HIT_EN_SHIFT                                                          12
+  #define CCFC_REG_CONTROL0_SCAM_SCRUB_MISS_EN                                                               (0x1<<13) // When set to 1 the string cam miss parity scrubbing feature is enabled.
+  #define CCFC_REG_CONTROL0_SCAM_SCRUB_MISS_EN_SHIFT                                                         13
+  #define CCFC_REG_CONTROL0_CCAM_SCRUB_HIT_EN                                                                (0x1<<14) // When set to 1 the cid cam hit parity scrubbing feature is enabled.
+  #define CCFC_REG_CONTROL0_CCAM_SCRUB_HIT_EN_SHIFT                                                          14
+  #define CCFC_REG_CONTROL0_CCAM_SCRUB_MISS_EN                                                               (0x1<<15) // When set to 1 the cid cam miss parity scrubbing feature is enabled.
+  #define CCFC_REG_CONTROL0_CCAM_SCRUB_MISS_EN_SHIFT                                                         15
+#define CCFC_REG_LCREQ_CREDIT                                                                                0x2e0740UL //Access:RW   DataWidth:0x6    // Set the initial credit for each of the load clients if less than the max is desired.
+#define CCFC_REG_LCREQ_CREDIT_SIZE                                                                           14
+#define CCFC_REG_PRSRESP_CREDIT                                                                              0x2e0780UL //Access:RW   DataWidth:0x5    // Set the initial credit for the parser response interface if less than the max is desired.
+#define CCFC_REG_SEARCH_CREDIT                                                                               0x2e0784UL //Access:RW   DataWidth:0x5    // Set the initial credit for the searcher interface if less than the max is desired.
+#define CCFC_REG_CDULD_CREDIT                                                                                0x2e0788UL //Access:RW   DataWidth:0x6    // Set the initial credit for the CDU load interface if less than the max is desired.
+#define CCFC_REG_CDUWB_CREDIT                                                                                0x2e078cUL //Access:RW   DataWidth:0x6    // Set the initial credit for the CDU write-back interface if less than the max is desired.
+#define CCFC_REG_FLOAD_RGN_MSK                                                                               0x2e07a0UL //Access:RW   DataWidth:0x8    // Array of indirect registers defines the forced load regions per type. Applicable only in the TCFC.
+#define CCFC_REG_FLOAD_RGN_MSK_SIZE                                                                          8
+#define CCFC_REG_LL_POLICY_CFG                                                                               0x2e0800UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define CCFC_REG_LL_POLICY_CFG_LL_POLICY_IO                                                                (0x3<<0) // This register is used to set the usage policy for the I/O Link List: 00: Pop LCIDs from the Head of the List (FIFO) 01: Pop LCIDs from the Tail of the List (Stack) 10: Alternate between Head and Tail of the List 11: Reserved
+  #define CCFC_REG_LL_POLICY_CFG_LL_POLICY_IO_SHIFT                                                          0
+  #define CCFC_REG_LL_POLICY_CFG_LL_POLICY_INA                                                               (0x3<<2) // This register is used to set the usage policy for the INA Link List: 00: Pop LCIDs from the Head of the List (FIFO) 01: Pop LCIDs from the Tail of the List (Stack) 10: Alternate between Head and Tail of the List 11: Reserved
+  #define CCFC_REG_LL_POLICY_CFG_LL_POLICY_INA_SHIFT                                                         2
+#define CCFC_REG_EMPTY_HEAD                                                                                  0x2e0804UL //Access:R    DataWidth:0x9    // Reserved:  This register is no longer needed in E4 B0.
+#define CCFC_REG_EMPTY_TAIL                                                                                  0x2e0808UL //Access:R    DataWidth:0x9    // Reserved:  This register is no longer needed in E4 b0.
+#define CCFC_REG_EMPTY_SIZE                                                                                  0x2e080cUL //Access:RW   DataWidth:0x9    // The size of the empty Link List is set accordingly.
+#define CCFC_REG_EIO_THRESHOLD_E5                                                                            0x2e0810UL //Access:RW   DataWidth:0x5    // When the sum of number of elements in empty list and in IO list is bigger than the value of this register, LC controller can start working on a new request. This is used in order to prevent deadlock where LC controller will acquire the (global) CID lock and then wait for an element from one of these lists on cache miss.
+#define CCFC_REG_LC_CLIENT_0_LCID_THRESHOLD                                                                  0x2e0900UL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 0 (YULD). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define CCFC_REG_LC_CLIENT_1_LCID_THRESHOLD                                                                  0x2e0904UL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 1 (XYLD). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define CCFC_REG_LC_CLIENT_2_LCID_THRESHOLD                                                                  0x2e0908UL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 2 (TMLD). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define CCFC_REG_LC_CLIENT_3_LCID_THRESHOLD                                                                  0x2e090cUL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 3 (MULD). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define CCFC_REG_LC_CLIENT_4_LCID_THRESHOLD                                                                  0x2e0910UL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 4 (YSDM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define CCFC_REG_LC_CLIENT_5_LCID_THRESHOLD                                                                  0x2e0914UL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 5 (XSDM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define CCFC_REG_LC_CLIENT_6_LCID_THRESHOLD                                                                  0x2e0918UL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 6 (USDM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define CCFC_REG_LC_CLIENT_7_LCID_THRESHOLD                                                                  0x2e091cUL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 7 (TSDM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define CCFC_REG_LC_CLIENT_8_LCID_THRESHOLD                                                                  0x2e0920UL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 8 (PSDM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define CCFC_REG_LC_CLIENT_9_LCID_THRESHOLD                                                                  0x2e0924UL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 9 (MSDM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define CCFC_REG_LC_CLIENT_10_LCID_THRESHOLD                                                                 0x2e0928UL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 10 (Timers). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define CCFC_REG_LC_CLIENT_11_LCID_THRESHOLD                                                                 0x2e092cUL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 11 (QM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define CCFC_REG_LC_CLIENT_12_LCID_THRESHOLD                                                                 0x2e0930UL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 12 (Parser). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define CCFC_REG_LC_CLIENT_13_LCID_THRESHOLD                                                                 0x2e0934UL //Access:RW   DataWidth:0x9    // This is the LCID Threshold for LC CLient 13 (DORQ). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.
+#define CCFC_REG_DORQ_NODIRECT_MSG_THRESH                                                                    0x2e0938UL //Access:RW   DataWidth:0x9    // This is threshold register to disable Direct messages in the DORQ. When the number of Active LCIDs is above this value, CFC will drive a signal to DORQ to prevent it from sending direct messages to XCM.
+#define CCFC_REG_WAVE_SM_RESTART                                                                             0x2e093cUL //Access:RW   DataWidth:0x3    // This is the Restart register for the LCID Limit Waveform Generators. Each bit corresponds to one of the state machines [2:0]. Writing the bits to 1'b1 will restart the Timer in each Generator. At this time, the output of the Generator will be set to the value of the Polarity bit in the corresponding Config register. Reading this register will always return 0.
+#define CCFC_REG_LCID_LIMIT_WAVE_SM_0_CFG                                                                    0x2e0940UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define CCFC_REG_LCID_LIMIT_WAVE_SM_0_CFG_WAVE_SM_0_ENABLED                                                (0x1<<0) // This is the Enable bit for the LCID Limiting Waveform Generator #0.
+  #define CCFC_REG_LCID_LIMIT_WAVE_SM_0_CFG_WAVE_SM_0_ENABLED_SHIFT                                          0
+  #define CCFC_REG_LCID_LIMIT_WAVE_SM_0_CFG_WAVE_SM_0_POLARITY                                               (0x1<<1) // This is the Polarity bit for the LCID Limiting Waveform Generator #0. The Waveform will always output this value when the Restart bit is set.
+  #define CCFC_REG_LCID_LIMIT_WAVE_SM_0_CFG_WAVE_SM_0_POLARITY_SHIFT                                         1
+#define CCFC_REG_WAVE_SM_0_CLIENT_MASK                                                                       0x2e0944UL //Access:RW   DataWidth:0xe    // This is the list of LC Clients that will be affected by Waveform Generator #0.
+#define CCFC_REG_WAVE_SM_0_ACTIVE_THRESH                                                                     0x2e0948UL //Access:RW   DataWidth:0x9    // This is the Threshold value of active LCIDs that triggers masking by Waveform Generator #0.
+#define CCFC_REG_WAVE_SM_0_ZERO_COUNT                                                                        0x2e094cUL //Access:RW   DataWidth:0x10   // This is the count of cycles that Waveform Generator #0 will output a ZERO value.
+#define CCFC_REG_WAVE_SM_0_ONE_COUNT                                                                         0x2e0950UL //Access:RW   DataWidth:0x10   // This is the count of cycles that Waveform Generator #0 will output a ONE value.
+#define CCFC_REG_LCID_LIMIT_WAVE_SM_1_CFG                                                                    0x2e0954UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define CCFC_REG_LCID_LIMIT_WAVE_SM_1_CFG_WAVE_SM_1_ENABLED                                                (0x1<<0) // This is the Enable bit for the LCID Limiting Waveform Generator #1.
+  #define CCFC_REG_LCID_LIMIT_WAVE_SM_1_CFG_WAVE_SM_1_ENABLED_SHIFT                                          0
+  #define CCFC_REG_LCID_LIMIT_WAVE_SM_1_CFG_WAVE_SM_1_POLARITY                                               (0x1<<1) // This is the Polarity bit for the LCID Limiting Waveform Generator #1. The Waveform will always output this value when the Restart bit is set.
+  #define CCFC_REG_LCID_LIMIT_WAVE_SM_1_CFG_WAVE_SM_1_POLARITY_SHIFT                                         1
+#define CCFC_REG_WAVE_SM_1_CLIENT_MASK                                                                       0x2e0958UL //Access:RW   DataWidth:0xe    // This is the list of LC Clients that will be affected by Waveform Generator #1.
+#define CCFC_REG_WAVE_SM_1_ACTIVE_THRESH                                                                     0x2e095cUL //Access:RW   DataWidth:0x9    // This is the Threshold value of active LCIDs that triggers masking by Waveform Generator #1.
+#define CCFC_REG_WAVE_SM_1_ZERO_COUNT                                                                        0x2e0960UL //Access:RW   DataWidth:0x10   // This is the count of cycles that Waveform Generator #1 will output a ZERO value.
+#define CCFC_REG_WAVE_SM_1_ONE_COUNT                                                                         0x2e0964UL //Access:RW   DataWidth:0x10   // This is the count of cycles that Waveform Generator #1 will output a ONE value.
+#define CCFC_REG_LCID_LIMIT_WAVE_SM_2_CFG                                                                    0x2e0968UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define CCFC_REG_LCID_LIMIT_WAVE_SM_2_CFG_WAVE_SM_2_ENABLED                                                (0x1<<0) // This is the Enable bit for the LCID Limiting Waveform Generator #2.
+  #define CCFC_REG_LCID_LIMIT_WAVE_SM_2_CFG_WAVE_SM_2_ENABLED_SHIFT                                          0
+  #define CCFC_REG_LCID_LIMIT_WAVE_SM_2_CFG_WAVE_SM_2_POLARITY                                               (0x1<<1) // This is the Polarity bit for the LCID Limiting Waveform Generator #2. The Waveform will always output this value when the Restart bit is set.
+  #define CCFC_REG_LCID_LIMIT_WAVE_SM_2_CFG_WAVE_SM_2_POLARITY_SHIFT                                         1
+#define CCFC_REG_WAVE_SM_2_CLIENT_MASK                                                                       0x2e096cUL //Access:RW   DataWidth:0xe    // This is the list of LC Clients that will be affected by Waveform Generator #2.
+#define CCFC_REG_WAVE_SM_2_ACTIVE_THRESH                                                                     0x2e0970UL //Access:RW   DataWidth:0x9    // This is the Threshold value of active LCIDs that triggers masking by Waveform Generator #2.
+#define CCFC_REG_WAVE_SM_2_ZERO_COUNT                                                                        0x2e0974UL //Access:RW   DataWidth:0x10   // This is the count of cycles that Waveform Generator #2 will output a ZERO value.
+#define CCFC_REG_WAVE_SM_2_ONE_COUNT                                                                         0x2e0978UL //Access:RW   DataWidth:0x10   // This is the count of cycles that Waveform Generator #2 will output a ONE value.
+#define CCFC_REG_CACHE_STRING_TYPE                                                                           0x2e0a00UL //Access:RW   DataWidth:0x8    // Mask vector for enabling caching on various string types. Each bit in this register matches the corresponding String Type. Bit[0]   = TCP Bit[1]   = UDP Bit[2]   = RoCE Multicast Bit[3]   = RoCE Unicast Bit[4]   = FCoE Bit[5]   = OpenFlow Bit[6]   = GFT Bit[7]   = Reserved
+#define CCFC_REG_SCAM_CACHE_ENABLES                                                                          0x2e0a04UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define CCFC_REG_SCAM_CACHE_ENABLES_ENABLE_NO_MATCH_CACHING                                                (0x1<<0) // When set, the String CAM will be used to cache results from the Searcher that did not match an entry in the external tables.
+  #define CCFC_REG_SCAM_CACHE_ENABLES_ENABLE_NO_MATCH_CACHING_SHIFT                                          0
+  #define CCFC_REG_SCAM_CACHE_ENABLES_ENABLE_L2_CACHING                                                      (0x1<<1) // When set, the String CAM will be used to cache results from the Searcher that Matched on an L2 Filter.
+  #define CCFC_REG_SCAM_CACHE_ENABLES_ENABLE_L2_CACHING_SHIFT                                                1
+#define CCFC_REG_CCAM_MASK_VECTOR                                                                            0x2e0a08UL //Access:RW   DataWidth:0x20   // CID CAM Mask.  This mask is used for Searches and Writes to the CID CAM. Setting a bit to 0 will ignore that bit in a search. Setting a bit to 0 will clear that bit on a write.
+#define CCFC_REG_CCAM_SEARCH                                                                                 0x2e0a0cUL //Access:RW   DataWidth:0x1    // When this bit is set writing to the ccam will cause a search operation on the written item (written using CFC_REGISTERS_LCID_CID_CAM.CID_CAM interface. the write can be to any address).
+#define CCFC_REG_SCAM_HASH_KEY0                                                                              0x2e0a10UL //Access:RW   DataWidth:0x20   // Key for String Cam Hash Algorithm, Bits[31:0].
+#define CCFC_REG_SCAM_HASH_KEY1                                                                              0x2e0a14UL //Access:RW   DataWidth:0x20   // Key for String Cam Hash Algorithm, Bits[63:32].
+#define CCFC_REG_SCAM_HASH_KEY2                                                                              0x2e0a18UL //Access:RW   DataWidth:0x20   // Key for String Cam Hash Algorithm, Bits[95:64].
+#define CCFC_REG_SCAM_HASH_KEY3                                                                              0x2e0a1cUL //Access:RW   DataWidth:0x20   // Key for String Cam Hash Algorithm, Bits[127:96].
+#define CCFC_REG_SCAM_HASH_KEY4                                                                              0x2e0a20UL //Access:RW   DataWidth:0x20   // Key for String Cam Hash Algorithm, Bits[159:128].
+#define CCFC_REG_SCAM_HASH_KEY5                                                                              0x2e0a24UL //Access:RW   DataWidth:0x20   // Key for String Cam Hash Algorithm, Bits[191:160].
+#define CCFC_REG_SCAM_HASH_KEY6                                                                              0x2e0a28UL //Access:RW   DataWidth:0x20   // Key for String Cam Hash Algorithm, Bits[223:192].
+#define CCFC_REG_SCAM_HASH_KEY7                                                                              0x2e0a2cUL //Access:RW   DataWidth:0x20   // Key for String Cam Hash Algorithm, Bits[255:224].
+#define CCFC_REG_SCAM_HASH_KEY8                                                                              0x2e0a30UL //Access:RW   DataWidth:0x20   // Key for String Cam Hash Algorithm, Bits[287:256].
+#define CCFC_REG_SCAM_HASH_KEY9                                                                              0x2e0a34UL //Access:RW   DataWidth:0x18   // Key for String Cam Hash Algorithm, Bits[311:288].
+#define CCFC_REG_SCAM_SEARCH                                                                                 0x2e0a38UL //Access:RW   DataWidth:0x1    // When this bit is set writing to the scam will cause a search operation on the written item (written using CFC_REGISTERS_LCID_STRING_CAM.STRING_CAM interface. the write can be to any address).
+#define CCFC_REG_SEARCH_RESULT                                                                               0x2e0a3cUL //Access:R    DataWidth:0xa    // {HIT;LCID}. HIT - if set then previous CAM seach item (either CCAM or SCAM) was found. LCID contains the result in case CAM search item (either CCAM or SCAM) was found.
+#define CCFC_REG_INCLUDE_TID_IN_HASH                                                                         0x2e0a40UL //Access:RW   DataWidth:0x1    // Added in E4B0. 0 - tid is not included in hash calculation (like in A0). 1 - tid is included in hash calculation by XORing TID[32:16] and TID[15:0] to the hash result. In this case, TID mask bit should be zero.
+#define CCFC_REG_INCLUDE_VLAN_IN_HASH                                                                        0x2e0a44UL //Access:RW   DataWidth:0x1    // Added in E4B0. 0 - vlan is not included in hash calculation (like in A0). 1 - vlan is included in hash calculation by XORing VLAN [11:0] to the hash result. In this case, promiscuous VLAN bit should be zero.
+#define CCFC_REG_CID_CAM_BIST_EN                                                                             0x2e0b00UL //Access:RW   DataWidth:0x1    // Used to enable/disable BIST mode on the CID CAM. When set, BIST testing will be performed and the results will be posted upon completion. When cleared CAM access will be enabled through the CAM BIST mechanism instead.
+#define CCFC_REG_CID_CAM_BIST_SKIP_ERROR_CNT                                                                 0x2e0b04UL //Access:RW   DataWidth:0x8    // Provides a threshold for the number of CID CAM BIST errors that are acceptable before reporting CAM BIST failure status.
+#define CCFC_REG_CID_CAM_BIST_STATUS_SEL                                                                     0x2e0b08UL //Access:RW   DataWidth:0x8    // Used to select the CID CAM BIST status word to read following the completion of a BIST test. Also used to select the data slice when writing data directly to the CAM using the CAM BIST mechanism.
+#define CCFC_REG_CID_CAM_BIST_STATUS                                                                         0x2e0b0cUL //Access:R    DataWidth:0x20   // Provides read-only access to the CID CAM BIST status word selected by cid_cam_bist_status_sel.
+#define CCFC_REG_STRING_CAM_BIST_EN                                                                          0x2e0b10UL //Access:RW   DataWidth:0x1    // Used to enable/disable BIST mode on the STRING CAM. When set, BIST testing will be performed and the results will be posted upon completion. When cleared CAM access will be enabled through the CAM BIST mechanism instead.
+#define CCFC_REG_STRING_CAM_BIST_SKIP_ERROR_CNT                                                              0x2e0b14UL //Access:RW   DataWidth:0x8    // Provides a threshold for the number of STRING CAM BIST errors that are acceptable before reporting CAM BIST failure status.
+#define CCFC_REG_STRING_CAM_BIST_STATUS_SEL                                                                  0x2e0b18UL //Access:RW   DataWidth:0x8    // Used to select the STRING CAM BIST status word to read following the completion of a BIST test. Also used to select the data slice when writing data directly to the CAM using the CAM BIST mechanism.
+#define CCFC_REG_STRING_CAM_BIST_STATUS                                                                      0x2e0b1cUL //Access:R    DataWidth:0x20   // Provides read-only access to the STRING CAM BIST status word selected by string_cam_bist_status_sel.
+#define CCFC_REG_LC_QUE                                                                                      0x2e8000UL //Access:WB   DataWidth:0x36   // Load client queue ram access.
+#define CCFC_REG_LC_QUE_SIZE                                                                                 430
+#define CCFC_REG_ACTIVITY_COUNTER                                                                            0x2e8800UL //Access:RW   DataWidth:0x10   // Activity counter ram access.
+#define CCFC_REG_ACTIVITY_COUNTER_SIZE                                                                       320
+#define CCFC_REG_INFO_STATE                                                                                  0x2e9000UL //Access:R    DataWidth:0x13   // Info store state machines = {lcid_curr_state;region_states}.
+#define CCFC_REG_INFO_STATE_SIZE                                                                             320
+#define CCFC_REG_INFO_REG                                                                                    0x2e9800UL //Access:R    DataWidth:0xe    // Info store register = {fid;type;cvld;ofl}.
+#define CCFC_REG_INFO_REG_SIZE                                                                               320
+#define CCFC_REG_LINK_LIST                                                                                   0x2ea000UL //Access:RW   DataWidth:0x12   // Link List ram access; data = {prev_pfid;prev_lcid;next_pfid;next_lcid}.
+#define CCFC_REG_LINK_LIST_SIZE                                                                              320
+#define CCFC_REG_CID_CAM                                                                                     0x2eb000UL //Access:WB   DataWidth:0x21   // CID cam  access (Valid - 32;31:0 - Data).
+#define CCFC_REG_CID_CAM_SIZE                                                                                640
+#define CCFC_REG_STRING_CAM                                                                                  0x2ec000UL //Access:WB   DataWidth:0x18   // String CAM Access Register (Hash[23:0])
+#define CCFC_REG_STRING_CAM_SIZE_BB                                                                          320
+#define CCFC_REG_STRING_CAM_SIZE_K2_E5                                                                       512
+#define CCFC_REG_TID_LOCK_RAM                                                                                0x2ec800UL //Access:RW   DataWidth:0xc    // TID Lock RAM Access Register [11]      = Locked [10]      = In Use [09:00]   = Usage Counter Value
+#define CCFC_REG_TID_LOCK_RAM_SIZE                                                                           320
+#define CCFC_REG_VPF1_LSTATE_SEL                                                                             0x2ed000UL //Access:RW   DataWidth:0x7    // State select vector for VF/PF LCID state counter 1 .
+#define CCFC_REG_VPF2_LSTATE_SEL                                                                             0x2ed004UL //Access:RW   DataWidth:0x7    // State select vector for VF/PF LCID state counter 2 .
+#define CCFC_REG_VF_LSTATE_CNT1                                                                              0x2ed008UL //Access:R    DataWidth:0x9    // VF port to VF/PF LCID state counter 1 .
+#define CCFC_REG_PF_LSTATE_CNT1                                                                              0x2ed00cUL //Access:R    DataWidth:0x9    // PF port to VF/PF LCID state counter 1 .
+#define CCFC_REG_VF_LSTATE_CNT2                                                                              0x2ed010UL //Access:R    DataWidth:0x9    // VF port to VF/PF LCID state counter 2 .
+#define CCFC_REG_PF_LSTATE_CNT2                                                                              0x2ed014UL //Access:R    DataWidth:0x9    // PF port to VF/PF LCID state counter 2 .
+#define QM_REG_INT_STS                                                                                       0x2f0180UL //Access:R    DataWidth:0x16   // Multi Field Register.
+  #define QM_REG_INT_STS_ADDRESS_ERROR                                                                       (0x1<<0) // Signals an unknown address to the rf module.
+  #define QM_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                                 0
+  #define QM_REG_INT_STS_OVF_ERR_TX                                                                          (0x1<<1) // Over flow occurs on the TX Queue.
+  #define QM_REG_INT_STS_OVF_ERR_TX_SHIFT                                                                    1
+  #define QM_REG_INT_STS_OVF_ERR_OTHER                                                                       (0x1<<2) // Over flow occurs on the Other Queue.
+  #define QM_REG_INT_STS_OVF_ERR_OTHER_SHIFT                                                                 2
+  #define QM_REG_INT_STS_PF_USG_CNT_ERR                                                                      (0x1<<3) // Overflow of pf usage counter.
+  #define QM_REG_INT_STS_PF_USG_CNT_ERR_SHIFT                                                                3
+  #define QM_REG_INT_STS_VF_USG_CNT_ERR                                                                      (0x1<<4) // Overflow of vf usage counter.
+  #define QM_REG_INT_STS_VF_USG_CNT_ERR_SHIFT                                                                4
+  #define QM_REG_INT_STS_VOQ_CRD_INC_ERR                                                                     (0x1<<5) // Increment overflow on VOQ counter.
+  #define QM_REG_INT_STS_VOQ_CRD_INC_ERR_SHIFT                                                               5
+  #define QM_REG_INT_STS_VOQ_CRD_DEC_ERR                                                                     (0x1<<6) // Decrement underflow on VOQ counter.
+  #define QM_REG_INT_STS_VOQ_CRD_DEC_ERR_SHIFT                                                               6
+  #define QM_REG_INT_STS_BYTE_CRD_INC_ERR                                                                    (0x1<<7) // Increment overflow on byte credit counter.
+  #define QM_REG_INT_STS_BYTE_CRD_INC_ERR_SHIFT                                                              7
+  #define QM_REG_INT_STS_BYTE_CRD_DEC_ERR                                                                    (0x1<<8) // Decrement underflow on byte credit counter.
+  #define QM_REG_INT_STS_BYTE_CRD_DEC_ERR_SHIFT                                                              8
+  #define QM_REG_INT_STS_ERR_INCDEC_RLGLBLCRD                                                                (0x1<<9) // Increment or Decrement error for the RL Global counters.
+  #define QM_REG_INT_STS_ERR_INCDEC_RLGLBLCRD_SHIFT                                                          9
+  #define QM_REG_INT_STS_ERR_INCDEC_RLPFCRD                                                                  (0x1<<10) // Increment or Decrement error for the RL PF counters.
+  #define QM_REG_INT_STS_ERR_INCDEC_RLPFCRD_SHIFT                                                            10
+  #define QM_REG_INT_STS_ERR_INCDEC_WFQPFCRD                                                                 (0x1<<11) // Increment or Decrement error for the WFQ PF counters.
+  #define QM_REG_INT_STS_ERR_INCDEC_WFQPFCRD_SHIFT                                                           11
+  #define QM_REG_INT_STS_ERR_INCDEC_WFQVPCRD                                                                 (0x1<<12) // Increment or Decrement error for the WFQ VP counters.
+  #define QM_REG_INT_STS_ERR_INCDEC_WFQVPCRD_SHIFT                                                           12
+  #define QM_REG_INT_STS_ERR_INCDEC_VOQLINECRD                                                               (0x1<<13) // Increment or Decrement error for the VOQ Line counters.
+  #define QM_REG_INT_STS_ERR_INCDEC_VOQLINECRD_SHIFT                                                         13
+  #define QM_REG_INT_STS_ERR_INCDEC_VOQBYTECRD                                                               (0x1<<14) // Increment or Decrement error for the VOQ Byte counters.
+  #define QM_REG_INT_STS_ERR_INCDEC_VOQBYTECRD_SHIFT                                                         14
+  #define QM_REG_INT_STS_FIFOS_ERROR                                                                         (0x1<<15) // Overflow or underflow error in one of FIFOs.
+  #define QM_REG_INT_STS_FIFOS_ERROR_SHIFT                                                                   15
+  #define QM_REG_INT_STS_QM_RL_DC_EXP_PF_CONTROLER_POP_ERROR                                                 (0x1<<16) // EXP PF controller pop FIFO error.
+  #define QM_REG_INT_STS_QM_RL_DC_EXP_PF_CONTROLER_POP_ERROR_SHIFT                                           16
+  #define QM_REG_INT_STS_QM_RL_DC_EXP_PF_CONTROLER_PUSH_ERROR                                                (0x1<<17) // EXP PF controller push FIFO error.
+  #define QM_REG_INT_STS_QM_RL_DC_EXP_PF_CONTROLER_PUSH_ERROR_SHIFT                                          17
+  #define QM_REG_INT_STS_QM_RL_DC_RF_REQ_CONTROLER_POP_ERROR                                                 (0x1<<18) // REQ controller pop FIFO error.
+  #define QM_REG_INT_STS_QM_RL_DC_RF_REQ_CONTROLER_POP_ERROR_SHIFT                                           18
+  #define QM_REG_INT_STS_QM_RL_DC_RF_REQ_CONTROLER_PUSH_ERROR                                                (0x1<<19) // REQ controller push FIFO error.
+  #define QM_REG_INT_STS_QM_RL_DC_RF_REQ_CONTROLER_PUSH_ERROR_SHIFT                                          19
+  #define QM_REG_INT_STS_QM_RL_DC_RF_RES_CONTROLER_POP_ERROR                                                 (0x1<<20) // RES controller pop FIFO error.
+  #define QM_REG_INT_STS_QM_RL_DC_RF_RES_CONTROLER_POP_ERROR_SHIFT                                           20
+  #define QM_REG_INT_STS_QM_RL_DC_RF_RES_CONTROLER_PUSH_ERROR                                                (0x1<<21) // RES controller push FIFO error.
+  #define QM_REG_INT_STS_QM_RL_DC_RF_RES_CONTROLER_PUSH_ERROR_SHIFT                                          21
+#define QM_REG_INT_MASK                                                                                      0x2f0184UL //Access:RW   DataWidth:0x16   // Multi Field Register.
+  #define QM_REG_INT_MASK_ADDRESS_ERROR                                                                      (0x1<<0) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.ADDRESS_ERROR .
+  #define QM_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                                0
+  #define QM_REG_INT_MASK_OVF_ERR_TX                                                                         (0x1<<1) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.OVF_ERR_TX .
+  #define QM_REG_INT_MASK_OVF_ERR_TX_SHIFT                                                                   1
+  #define QM_REG_INT_MASK_OVF_ERR_OTHER                                                                      (0x1<<2) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.OVF_ERR_OTHER .
+  #define QM_REG_INT_MASK_OVF_ERR_OTHER_SHIFT                                                                2
+  #define QM_REG_INT_MASK_PF_USG_CNT_ERR                                                                     (0x1<<3) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.PF_USG_CNT_ERR .
+  #define QM_REG_INT_MASK_PF_USG_CNT_ERR_SHIFT                                                               3
+  #define QM_REG_INT_MASK_VF_USG_CNT_ERR                                                                     (0x1<<4) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.VF_USG_CNT_ERR .
+  #define QM_REG_INT_MASK_VF_USG_CNT_ERR_SHIFT                                                               4
+  #define QM_REG_INT_MASK_VOQ_CRD_INC_ERR                                                                    (0x1<<5) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.VOQ_CRD_INC_ERR .
+  #define QM_REG_INT_MASK_VOQ_CRD_INC_ERR_SHIFT                                                              5
+  #define QM_REG_INT_MASK_VOQ_CRD_DEC_ERR                                                                    (0x1<<6) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.VOQ_CRD_DEC_ERR .
+  #define QM_REG_INT_MASK_VOQ_CRD_DEC_ERR_SHIFT                                                              6
+  #define QM_REG_INT_MASK_BYTE_CRD_INC_ERR                                                                   (0x1<<7) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.BYTE_CRD_INC_ERR .
+  #define QM_REG_INT_MASK_BYTE_CRD_INC_ERR_SHIFT                                                             7
+  #define QM_REG_INT_MASK_BYTE_CRD_DEC_ERR                                                                   (0x1<<8) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.BYTE_CRD_DEC_ERR .
+  #define QM_REG_INT_MASK_BYTE_CRD_DEC_ERR_SHIFT                                                             8
+  #define QM_REG_INT_MASK_ERR_INCDEC_RLGLBLCRD                                                               (0x1<<9) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.ERR_INCDEC_RLGLBLCRD .
+  #define QM_REG_INT_MASK_ERR_INCDEC_RLGLBLCRD_SHIFT                                                         9
+  #define QM_REG_INT_MASK_ERR_INCDEC_RLPFCRD                                                                 (0x1<<10) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.ERR_INCDEC_RLPFCRD .
+  #define QM_REG_INT_MASK_ERR_INCDEC_RLPFCRD_SHIFT                                                           10
+  #define QM_REG_INT_MASK_ERR_INCDEC_WFQPFCRD                                                                (0x1<<11) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.ERR_INCDEC_WFQPFCRD .
+  #define QM_REG_INT_MASK_ERR_INCDEC_WFQPFCRD_SHIFT                                                          11
+  #define QM_REG_INT_MASK_ERR_INCDEC_WFQVPCRD                                                                (0x1<<12) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.ERR_INCDEC_WFQVPCRD .
+  #define QM_REG_INT_MASK_ERR_INCDEC_WFQVPCRD_SHIFT                                                          12
+  #define QM_REG_INT_MASK_ERR_INCDEC_VOQLINECRD                                                              (0x1<<13) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.ERR_INCDEC_VOQLINECRD .
+  #define QM_REG_INT_MASK_ERR_INCDEC_VOQLINECRD_SHIFT                                                        13
+  #define QM_REG_INT_MASK_ERR_INCDEC_VOQBYTECRD                                                              (0x1<<14) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.ERR_INCDEC_VOQBYTECRD .
+  #define QM_REG_INT_MASK_ERR_INCDEC_VOQBYTECRD_SHIFT                                                        14
+  #define QM_REG_INT_MASK_FIFOS_ERROR                                                                        (0x1<<15) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.FIFOS_ERROR .
+  #define QM_REG_INT_MASK_FIFOS_ERROR_SHIFT                                                                  15
+  #define QM_REG_INT_MASK_QM_RL_DC_EXP_PF_CONTROLER_POP_ERROR                                                (0x1<<16) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.QM_RL_DC_EXP_PF_CONTROLER_POP_ERROR .
+  #define QM_REG_INT_MASK_QM_RL_DC_EXP_PF_CONTROLER_POP_ERROR_SHIFT                                          16
+  #define QM_REG_INT_MASK_QM_RL_DC_EXP_PF_CONTROLER_PUSH_ERROR                                               (0x1<<17) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.QM_RL_DC_EXP_PF_CONTROLER_PUSH_ERROR .
+  #define QM_REG_INT_MASK_QM_RL_DC_EXP_PF_CONTROLER_PUSH_ERROR_SHIFT                                         17
+  #define QM_REG_INT_MASK_QM_RL_DC_RF_REQ_CONTROLER_POP_ERROR                                                (0x1<<18) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.QM_RL_DC_RF_REQ_CONTROLER_POP_ERROR .
+  #define QM_REG_INT_MASK_QM_RL_DC_RF_REQ_CONTROLER_POP_ERROR_SHIFT                                          18
+  #define QM_REG_INT_MASK_QM_RL_DC_RF_REQ_CONTROLER_PUSH_ERROR                                               (0x1<<19) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.QM_RL_DC_RF_REQ_CONTROLER_PUSH_ERROR .
+  #define QM_REG_INT_MASK_QM_RL_DC_RF_REQ_CONTROLER_PUSH_ERROR_SHIFT                                         19
+  #define QM_REG_INT_MASK_QM_RL_DC_RF_RES_CONTROLER_POP_ERROR                                                (0x1<<20) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.QM_RL_DC_RF_RES_CONTROLER_POP_ERROR .
+  #define QM_REG_INT_MASK_QM_RL_DC_RF_RES_CONTROLER_POP_ERROR_SHIFT                                          20
+  #define QM_REG_INT_MASK_QM_RL_DC_RF_RES_CONTROLER_PUSH_ERROR                                               (0x1<<21) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.QM_RL_DC_RF_RES_CONTROLER_PUSH_ERROR .
+  #define QM_REG_INT_MASK_QM_RL_DC_RF_RES_CONTROLER_PUSH_ERROR_SHIFT                                         21
+#define QM_REG_INT_STS_WR                                                                                    0x2f0188UL //Access:WR   DataWidth:0x16   // Multi Field Register.
+  #define QM_REG_INT_STS_WR_ADDRESS_ERROR                                                                    (0x1<<0) // Signals an unknown address to the rf module.
+  #define QM_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                              0
+  #define QM_REG_INT_STS_WR_OVF_ERR_TX                                                                       (0x1<<1) // Over flow occurs on the TX Queue.
+  #define QM_REG_INT_STS_WR_OVF_ERR_TX_SHIFT                                                                 1
+  #define QM_REG_INT_STS_WR_OVF_ERR_OTHER                                                                    (0x1<<2) // Over flow occurs on the Other Queue.
+  #define QM_REG_INT_STS_WR_OVF_ERR_OTHER_SHIFT                                                              2
+  #define QM_REG_INT_STS_WR_PF_USG_CNT_ERR                                                                   (0x1<<3) // Overflow of pf usage counter.
+  #define QM_REG_INT_STS_WR_PF_USG_CNT_ERR_SHIFT                                                             3
+  #define QM_REG_INT_STS_WR_VF_USG_CNT_ERR                                                                   (0x1<<4) // Overflow of vf usage counter.
+  #define QM_REG_INT_STS_WR_VF_USG_CNT_ERR_SHIFT                                                             4
+  #define QM_REG_INT_STS_WR_VOQ_CRD_INC_ERR                                                                  (0x1<<5) // Increment overflow on VOQ counter.
+  #define QM_REG_INT_STS_WR_VOQ_CRD_INC_ERR_SHIFT                                                            5
+  #define QM_REG_INT_STS_WR_VOQ_CRD_DEC_ERR                                                                  (0x1<<6) // Decrement underflow on VOQ counter.
+  #define QM_REG_INT_STS_WR_VOQ_CRD_DEC_ERR_SHIFT                                                            6
+  #define QM_REG_INT_STS_WR_BYTE_CRD_INC_ERR                                                                 (0x1<<7) // Increment overflow on byte credit counter.
+  #define QM_REG_INT_STS_WR_BYTE_CRD_INC_ERR_SHIFT                                                           7
+  #define QM_REG_INT_STS_WR_BYTE_CRD_DEC_ERR                                                                 (0x1<<8) // Decrement underflow on byte credit counter.
+  #define QM_REG_INT_STS_WR_BYTE_CRD_DEC_ERR_SHIFT                                                           8
+  #define QM_REG_INT_STS_WR_ERR_INCDEC_RLGLBLCRD                                                             (0x1<<9) // Increment or Decrement error for the RL Global counters.
+  #define QM_REG_INT_STS_WR_ERR_INCDEC_RLGLBLCRD_SHIFT                                                       9
+  #define QM_REG_INT_STS_WR_ERR_INCDEC_RLPFCRD                                                               (0x1<<10) // Increment or Decrement error for the RL PF counters.
+  #define QM_REG_INT_STS_WR_ERR_INCDEC_RLPFCRD_SHIFT                                                         10
+  #define QM_REG_INT_STS_WR_ERR_INCDEC_WFQPFCRD                                                              (0x1<<11) // Increment or Decrement error for the WFQ PF counters.
+  #define QM_REG_INT_STS_WR_ERR_INCDEC_WFQPFCRD_SHIFT                                                        11
+  #define QM_REG_INT_STS_WR_ERR_INCDEC_WFQVPCRD                                                              (0x1<<12) // Increment or Decrement error for the WFQ VP counters.
+  #define QM_REG_INT_STS_WR_ERR_INCDEC_WFQVPCRD_SHIFT                                                        12
+  #define QM_REG_INT_STS_WR_ERR_INCDEC_VOQLINECRD                                                            (0x1<<13) // Increment or Decrement error for the VOQ Line counters.
+  #define QM_REG_INT_STS_WR_ERR_INCDEC_VOQLINECRD_SHIFT                                                      13
+  #define QM_REG_INT_STS_WR_ERR_INCDEC_VOQBYTECRD                                                            (0x1<<14) // Increment or Decrement error for the VOQ Byte counters.
+  #define QM_REG_INT_STS_WR_ERR_INCDEC_VOQBYTECRD_SHIFT                                                      14
+  #define QM_REG_INT_STS_WR_FIFOS_ERROR                                                                      (0x1<<15) // Overflow or underflow error in one of FIFOs.
+  #define QM_REG_INT_STS_WR_FIFOS_ERROR_SHIFT                                                                15
+  #define QM_REG_INT_STS_WR_QM_RL_DC_EXP_PF_CONTROLER_POP_ERROR                                              (0x1<<16) // EXP PF controller pop FIFO error.
+  #define QM_REG_INT_STS_WR_QM_RL_DC_EXP_PF_CONTROLER_POP_ERROR_SHIFT                                        16
+  #define QM_REG_INT_STS_WR_QM_RL_DC_EXP_PF_CONTROLER_PUSH_ERROR                                             (0x1<<17) // EXP PF controller push FIFO error.
+  #define QM_REG_INT_STS_WR_QM_RL_DC_EXP_PF_CONTROLER_PUSH_ERROR_SHIFT                                       17
+  #define QM_REG_INT_STS_WR_QM_RL_DC_RF_REQ_CONTROLER_POP_ERROR                                              (0x1<<18) // REQ controller pop FIFO error.
+  #define QM_REG_INT_STS_WR_QM_RL_DC_RF_REQ_CONTROLER_POP_ERROR_SHIFT                                        18
+  #define QM_REG_INT_STS_WR_QM_RL_DC_RF_REQ_CONTROLER_PUSH_ERROR                                             (0x1<<19) // REQ controller push FIFO error.
+  #define QM_REG_INT_STS_WR_QM_RL_DC_RF_REQ_CONTROLER_PUSH_ERROR_SHIFT                                       19
+  #define QM_REG_INT_STS_WR_QM_RL_DC_RF_RES_CONTROLER_POP_ERROR                                              (0x1<<20) // RES controller pop FIFO error.
+  #define QM_REG_INT_STS_WR_QM_RL_DC_RF_RES_CONTROLER_POP_ERROR_SHIFT                                        20
+  #define QM_REG_INT_STS_WR_QM_RL_DC_RF_RES_CONTROLER_PUSH_ERROR                                             (0x1<<21) // RES controller push FIFO error.
+  #define QM_REG_INT_STS_WR_QM_RL_DC_RF_RES_CONTROLER_PUSH_ERROR_SHIFT                                       21
+#define QM_REG_INT_STS_CLR                                                                                   0x2f018cUL //Access:RC   DataWidth:0x16   // Multi Field Register.
+  #define QM_REG_INT_STS_CLR_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define QM_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                             0
+  #define QM_REG_INT_STS_CLR_OVF_ERR_TX                                                                      (0x1<<1) // Over flow occurs on the TX Queue.
+  #define QM_REG_INT_STS_CLR_OVF_ERR_TX_SHIFT                                                                1
+  #define QM_REG_INT_STS_CLR_OVF_ERR_OTHER                                                                   (0x1<<2) // Over flow occurs on the Other Queue.
+  #define QM_REG_INT_STS_CLR_OVF_ERR_OTHER_SHIFT                                                             2
+  #define QM_REG_INT_STS_CLR_PF_USG_CNT_ERR                                                                  (0x1<<3) // Overflow of pf usage counter.
+  #define QM_REG_INT_STS_CLR_PF_USG_CNT_ERR_SHIFT                                                            3
+  #define QM_REG_INT_STS_CLR_VF_USG_CNT_ERR                                                                  (0x1<<4) // Overflow of vf usage counter.
+  #define QM_REG_INT_STS_CLR_VF_USG_CNT_ERR_SHIFT                                                            4
+  #define QM_REG_INT_STS_CLR_VOQ_CRD_INC_ERR                                                                 (0x1<<5) // Increment overflow on VOQ counter.
+  #define QM_REG_INT_STS_CLR_VOQ_CRD_INC_ERR_SHIFT                                                           5
+  #define QM_REG_INT_STS_CLR_VOQ_CRD_DEC_ERR                                                                 (0x1<<6) // Decrement underflow on VOQ counter.
+  #define QM_REG_INT_STS_CLR_VOQ_CRD_DEC_ERR_SHIFT                                                           6
+  #define QM_REG_INT_STS_CLR_BYTE_CRD_INC_ERR                                                                (0x1<<7) // Increment overflow on byte credit counter.
+  #define QM_REG_INT_STS_CLR_BYTE_CRD_INC_ERR_SHIFT                                                          7
+  #define QM_REG_INT_STS_CLR_BYTE_CRD_DEC_ERR                                                                (0x1<<8) // Decrement underflow on byte credit counter.
+  #define QM_REG_INT_STS_CLR_BYTE_CRD_DEC_ERR_SHIFT                                                          8
+  #define QM_REG_INT_STS_CLR_ERR_INCDEC_RLGLBLCRD                                                            (0x1<<9) // Increment or Decrement error for the RL Global counters.
+  #define QM_REG_INT_STS_CLR_ERR_INCDEC_RLGLBLCRD_SHIFT                                                      9
+  #define QM_REG_INT_STS_CLR_ERR_INCDEC_RLPFCRD                                                              (0x1<<10) // Increment or Decrement error for the RL PF counters.
+  #define QM_REG_INT_STS_CLR_ERR_INCDEC_RLPFCRD_SHIFT                                                        10
+  #define QM_REG_INT_STS_CLR_ERR_INCDEC_WFQPFCRD                                                             (0x1<<11) // Increment or Decrement error for the WFQ PF counters.
+  #define QM_REG_INT_STS_CLR_ERR_INCDEC_WFQPFCRD_SHIFT                                                       11
+  #define QM_REG_INT_STS_CLR_ERR_INCDEC_WFQVPCRD                                                             (0x1<<12) // Increment or Decrement error for the WFQ VP counters.
+  #define QM_REG_INT_STS_CLR_ERR_INCDEC_WFQVPCRD_SHIFT                                                       12
+  #define QM_REG_INT_STS_CLR_ERR_INCDEC_VOQLINECRD                                                           (0x1<<13) // Increment or Decrement error for the VOQ Line counters.
+  #define QM_REG_INT_STS_CLR_ERR_INCDEC_VOQLINECRD_SHIFT                                                     13
+  #define QM_REG_INT_STS_CLR_ERR_INCDEC_VOQBYTECRD                                                           (0x1<<14) // Increment or Decrement error for the VOQ Byte counters.
+  #define QM_REG_INT_STS_CLR_ERR_INCDEC_VOQBYTECRD_SHIFT                                                     14
+  #define QM_REG_INT_STS_CLR_FIFOS_ERROR                                                                     (0x1<<15) // Overflow or underflow error in one of FIFOs.
+  #define QM_REG_INT_STS_CLR_FIFOS_ERROR_SHIFT                                                               15
+  #define QM_REG_INT_STS_CLR_QM_RL_DC_EXP_PF_CONTROLER_POP_ERROR                                             (0x1<<16) // EXP PF controller pop FIFO error.
+  #define QM_REG_INT_STS_CLR_QM_RL_DC_EXP_PF_CONTROLER_POP_ERROR_SHIFT                                       16
+  #define QM_REG_INT_STS_CLR_QM_RL_DC_EXP_PF_CONTROLER_PUSH_ERROR                                            (0x1<<17) // EXP PF controller push FIFO error.
+  #define QM_REG_INT_STS_CLR_QM_RL_DC_EXP_PF_CONTROLER_PUSH_ERROR_SHIFT                                      17
+  #define QM_REG_INT_STS_CLR_QM_RL_DC_RF_REQ_CONTROLER_POP_ERROR                                             (0x1<<18) // REQ controller pop FIFO error.
+  #define QM_REG_INT_STS_CLR_QM_RL_DC_RF_REQ_CONTROLER_POP_ERROR_SHIFT                                       18
+  #define QM_REG_INT_STS_CLR_QM_RL_DC_RF_REQ_CONTROLER_PUSH_ERROR                                            (0x1<<19) // REQ controller push FIFO error.
+  #define QM_REG_INT_STS_CLR_QM_RL_DC_RF_REQ_CONTROLER_PUSH_ERROR_SHIFT                                      19
+  #define QM_REG_INT_STS_CLR_QM_RL_DC_RF_RES_CONTROLER_POP_ERROR                                             (0x1<<20) // RES controller pop FIFO error.
+  #define QM_REG_INT_STS_CLR_QM_RL_DC_RF_RES_CONTROLER_POP_ERROR_SHIFT                                       20
+  #define QM_REG_INT_STS_CLR_QM_RL_DC_RF_RES_CONTROLER_PUSH_ERROR                                            (0x1<<21) // RES controller push FIFO error.
+  #define QM_REG_INT_STS_CLR_QM_RL_DC_RF_RES_CONTROLER_PUSH_ERROR_SHIFT                                      21
+#define QM_REG_PRTY_MASK                                                                                     0x2f0194UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define QM_REG_PRTY_MASK_XCM_WRC_FIFO                                                                      (0x1<<0) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.XCM_WRC_FIFO .
+  #define QM_REG_PRTY_MASK_XCM_WRC_FIFO_SHIFT                                                                0
+  #define QM_REG_PRTY_MASK_UCM_WRC_FIFO                                                                      (0x1<<1) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.UCM_WRC_FIFO .
+  #define QM_REG_PRTY_MASK_UCM_WRC_FIFO_SHIFT                                                                1
+  #define QM_REG_PRTY_MASK_TCM_WRC_FIFO                                                                      (0x1<<2) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.TCM_WRC_FIFO .
+  #define QM_REG_PRTY_MASK_TCM_WRC_FIFO_SHIFT                                                                2
+  #define QM_REG_PRTY_MASK_CCM_WRC_FIFO                                                                      (0x1<<3) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.CCM_WRC_FIFO .
+  #define QM_REG_PRTY_MASK_CCM_WRC_FIFO_SHIFT                                                                3
+  #define QM_REG_PRTY_MASK_BIGRAMHIGH                                                                        (0x1<<4) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.BIGRAMHIGH .
+  #define QM_REG_PRTY_MASK_BIGRAMHIGH_SHIFT                                                                  4
+  #define QM_REG_PRTY_MASK_BIGRAMLOW                                                                         (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.BIGRAMLOW .
+  #define QM_REG_PRTY_MASK_BIGRAMLOW_SHIFT                                                                   5
+  #define QM_REG_PRTY_MASK_BASE_ADDRESS                                                                      (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.BASE_ADDRESS .
+  #define QM_REG_PRTY_MASK_BASE_ADDRESS_SHIFT                                                                6
+  #define QM_REG_PRTY_MASK_WRBUFF                                                                            (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.WRBUFF .
+  #define QM_REG_PRTY_MASK_WRBUFF_SHIFT                                                                      7
+  #define QM_REG_PRTY_MASK_BIGRAMHIGH_EXT_A                                                                  (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.BIGRAMHIGH_EXT_A .
+  #define QM_REG_PRTY_MASK_BIGRAMHIGH_EXT_A_SHIFT                                                            8
+  #define QM_REG_PRTY_MASK_BIGRAMLOW_EXT_A                                                                   (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.BIGRAMLOW_EXT_A .
+  #define QM_REG_PRTY_MASK_BIGRAMLOW_EXT_A_SHIFT                                                             9
+  #define QM_REG_PRTY_MASK_BASE_ADDRESS_EXT_A                                                                (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.BASE_ADDRESS_EXT_A .
+  #define QM_REG_PRTY_MASK_BASE_ADDRESS_EXT_A_SHIFT                                                          10
+#define QM_REG_PRTY_MASK_H_0_BB_K2                                                                           0x2f0204UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define QM_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT_BB_K2                                                   (0x1<<0) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM006_I_ECC_0_RF_INT .
+  #define QM_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT_BB_K2_SHIFT                                             0
+  #define QM_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT_BB_K2                                                   (0x1<<1) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM006_I_ECC_1_RF_INT .
+  #define QM_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT_BB_K2_SHIFT                                             1
+  #define QM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_BB_K2                                                   (0x1<<2) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
+  #define QM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_BB_K2_SHIFT                                             2
+  #define QM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_K2                                                   (0x1<<3) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
+  #define QM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_K2_SHIFT                                             3
+  #define QM_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_BB_K2                                                     (0x1<<4) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM012_I_ECC_RF_INT .
+  #define QM_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_BB_K2_SHIFT                                               4
+  #define QM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_BB_K2                                                       (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_BB_K2_SHIFT                                                 5
+  #define QM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_BB_K2                                                       (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_BB_K2_SHIFT                                                 6
+  #define QM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_BB_K2                                                       (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_BB_K2_SHIFT                                                 7
+  #define QM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_BB_K2                                                       (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_BB_K2_SHIFT                                                 8
+  #define QM_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_BB_K2                                                       (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM040_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_BB_K2_SHIFT                                                 9
+  #define QM_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY_BB_K2                                                       (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM042_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY_BB_K2_SHIFT                                                 10
+  #define QM_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY_BB_K2                                                       (0x1<<11) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM041_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY_BB_K2_SHIFT                                                 11
+  #define QM_REG_PRTY_MASK_H_0_MEM056_I_MEM_PRTY_BB_K2                                                       (0x1<<12) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM056_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM056_I_MEM_PRTY_BB_K2_SHIFT                                                 12
+  #define QM_REG_PRTY_MASK_H_0_MEM055_I_MEM_PRTY_BB_K2                                                       (0x1<<13) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM055_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM055_I_MEM_PRTY_BB_K2_SHIFT                                                 13
+  #define QM_REG_PRTY_MASK_H_0_MEM053_I_MEM_PRTY_BB_K2                                                       (0x1<<14) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM053_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM053_I_MEM_PRTY_BB_K2_SHIFT                                                 14
+  #define QM_REG_PRTY_MASK_H_0_MEM054_I_MEM_PRTY_BB_K2                                                       (0x1<<15) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM054_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM054_I_MEM_PRTY_BB_K2_SHIFT                                                 15
+  #define QM_REG_PRTY_MASK_H_0_MEM057_I_MEM_PRTY_BB_K2                                                       (0x1<<16) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM057_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM057_I_MEM_PRTY_BB_K2_SHIFT                                                 16
+  #define QM_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY_BB_K2                                                       (0x1<<17) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM058_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY_BB_K2_SHIFT                                                 17
+  #define QM_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY_BB_K2                                                       (0x1<<18) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM062_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY_BB_K2_SHIFT                                                 18
+  #define QM_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_BB_K2                                                       (0x1<<19) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM061_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_BB_K2_SHIFT                                                 19
+  #define QM_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_BB_K2                                                       (0x1<<20) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM059_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_BB_K2_SHIFT                                                 20
+  #define QM_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_BB_K2                                                       (0x1<<21) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM060_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_BB_K2_SHIFT                                                 21
+  #define QM_REG_PRTY_MASK_H_0_MEM063_I_MEM_PRTY_BB_K2                                                       (0x1<<22) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM063_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM063_I_MEM_PRTY_BB_K2_SHIFT                                                 22
+  #define QM_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY_BB_K2                                                       (0x1<<23) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM064_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY_BB_K2_SHIFT                                                 23
+  #define QM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_BB_K2                                                       (0x1<<24) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_BB_K2_SHIFT                                                 24
+  #define QM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_K2                                                       (0x1<<25) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_K2_SHIFT                                                 25
+  #define QM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_K2                                                       (0x1<<26) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_K2_SHIFT                                                 26
+  #define QM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_K2                                                       (0x1<<27) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_K2_SHIFT                                                 27
+  #define QM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_K2                                                       (0x1<<28) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_K2_SHIFT                                                 28
+  #define QM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_BB_K2                                                       (0x1<<29) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_BB_K2_SHIFT                                                 29
+  #define QM_REG_PRTY_MASK_H_0_MEM051_I_MEM_PRTY_BB_K2                                                       (0x1<<30) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM051_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_0_MEM051_I_MEM_PRTY_BB_K2_SHIFT                                                 30
+#define QM_REG_PRTY_MASK_H_1_BB_K2                                                                           0x2f0214UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define QM_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_BB_K2                                                       (0x1<<0) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM047_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_BB_K2_SHIFT                                                 0
+  #define QM_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_BB_K2                                                       (0x1<<1) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM049_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_BB_K2_SHIFT                                                 1
+  #define QM_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_BB_K2                                                       (0x1<<2) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM048_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_BB_K2_SHIFT                                                 2
+  #define QM_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_BB_K2                                                       (0x1<<3) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_BB_K2_SHIFT                                                 3
+  #define QM_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_BB_K2                                                       (0x1<<4) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_BB_K2_SHIFT                                                 4
+  #define QM_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY_BB_K2                                                       (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM045_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY_BB_K2_SHIFT                                                 5
+  #define QM_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY_BB_K2                                                       (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM046_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY_BB_K2_SHIFT                                                 6
+  #define QM_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_BB_K2                                                       (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM043_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_BB_K2_SHIFT                                                 7
+  #define QM_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_BB_K2                                                       (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM044_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_BB_K2_SHIFT                                                 8
+  #define QM_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_BB_K2                                                       (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM029_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_BB_K2_SHIFT                                                 9
+  #define QM_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_BB_K2                                                       (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM004_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                                 10
+  #define QM_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY_BB_K2                                                       (0x1<<11) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM003_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                                 11
+  #define QM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_BB_K2                                                       (0x1<<12) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_BB_K2_SHIFT                                                 12
+  #define QM_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_BB_K2                                                       (0x1<<13) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_BB_K2_SHIFT                                                 13
+  #define QM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_BB_K2                                                       (0x1<<14) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_BB_K2_SHIFT                                                 14
+  #define QM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_BB_K2                                                       (0x1<<15) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_BB_K2_SHIFT                                                 15
+  #define QM_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_BB_K2                                                       (0x1<<16) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM021_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_BB_K2_SHIFT                                                 16
+  #define QM_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_BB_K2                                                       (0x1<<17) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM024_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_BB_K2_SHIFT                                                 17
+  #define QM_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_BB_K2                                                       (0x1<<18) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM019_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_BB_K2_SHIFT                                                 18
+  #define QM_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_BB_K2                                                       (0x1<<19) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM018_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_BB_K2_SHIFT                                                 19
+  #define QM_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_BB_K2                                                       (0x1<<20) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_BB_K2_SHIFT                                                 20
+  #define QM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_BB_K2                                                       (0x1<<21) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_BB_K2_SHIFT                                                 21
+  #define QM_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY_BB_K2                                                       (0x1<<22) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM023_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY_BB_K2_SHIFT                                                 22
+  #define QM_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_BB_K2                                                       (0x1<<23) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM026_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_BB_K2_SHIFT                                                 23
+  #define QM_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_BB_K2                                                       (0x1<<24) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM022_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_BB_K2_SHIFT                                                 24
+  #define QM_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_BB_K2                                                       (0x1<<25) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM025_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_BB_K2_SHIFT                                                 25
+  #define QM_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_BB_K2                                                       (0x1<<26) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM020_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_BB_K2_SHIFT                                                 26
+  #define QM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_BB_K2                                                       (0x1<<27) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_BB_K2_SHIFT                                                 27
+  #define QM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_0_BB_K2                                                     (0x1<<28) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY_0 .
+  #define QM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_0_BB_K2_SHIFT                                               28
+  #define QM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_1_BB_K2                                                     (0x1<<29) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY_1 .
+  #define QM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_1_BB_K2_SHIFT                                               29
+  #define QM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_2_BB_K2                                                     (0x1<<30) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY_2 .
+  #define QM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_2_BB_K2_SHIFT                                               30
+#define QM_REG_PRTY_MASK_H_2_BB_K2                                                                           0x2f0224UL //Access:RW   DataWidth:0x13   // Multi Field Register.
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_3_BB_K2                                                     (0x1<<0) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_3 .
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_3_BB_K2_SHIFT                                               0
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_4_BB_K2                                                     (0x1<<1) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_4 .
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_4_BB_K2_SHIFT                                               1
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_5_BB_K2                                                     (0x1<<2) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_5 .
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_5_BB_K2_SHIFT                                               2
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_6_BB_K2                                                     (0x1<<3) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_6 .
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_6_BB_K2_SHIFT                                               3
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_7_BB_K2                                                     (0x1<<4) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_7 .
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_7_BB_K2_SHIFT                                               4
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_8_K2                                                        (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_8 .
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_8_K2_SHIFT                                                  5
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_9_K2                                                        (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_9 .
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_9_K2_SHIFT                                                  6
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_10_K2                                                       (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_10 .
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_10_K2_SHIFT                                                 7
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_11_K2                                                       (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_11 .
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_11_K2_SHIFT                                                 8
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_12_K2                                                       (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_12 .
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_12_K2_SHIFT                                                 9
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_13_K2                                                       (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_13 .
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_13_K2_SHIFT                                                 10
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_14_K2                                                       (0x1<<11) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_14 .
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_14_K2_SHIFT                                                 11
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_15_K2                                                       (0x1<<12) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_15 .
+  #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_15_K2_SHIFT                                                 12
+  #define QM_REG_PRTY_MASK_H_2_MEM027_I_MEM_PRTY_BB                                                          (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM027_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_2_MEM027_I_MEM_PRTY_BB_SHIFT                                                    5
+  #define QM_REG_PRTY_MASK_H_2_MEM027_I_MEM_PRTY_K2                                                          (0x1<<13) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM027_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_2_MEM027_I_MEM_PRTY_K2_SHIFT                                                    13
+  #define QM_REG_PRTY_MASK_H_2_MEM001_I_MEM_PRTY_BB                                                          (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM001_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_2_MEM001_I_MEM_PRTY_BB_SHIFT                                                    6
+  #define QM_REG_PRTY_MASK_H_2_MEM001_I_MEM_PRTY_K2                                                          (0x1<<14) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM001_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_2_MEM001_I_MEM_PRTY_K2_SHIFT                                                    14
+  #define QM_REG_PRTY_MASK_H_2_MEM028_I_MEM_PRTY_BB                                                          (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM028_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_2_MEM028_I_MEM_PRTY_BB_SHIFT                                                    7
+  #define QM_REG_PRTY_MASK_H_2_MEM028_I_MEM_PRTY_K2                                                          (0x1<<15) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM028_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_2_MEM028_I_MEM_PRTY_K2_SHIFT                                                    15
+  #define QM_REG_PRTY_MASK_H_2_MEM002_I_MEM_PRTY_BB                                                          (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM002_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_2_MEM002_I_MEM_PRTY_BB_SHIFT                                                    8
+  #define QM_REG_PRTY_MASK_H_2_MEM002_I_MEM_PRTY_K2                                                          (0x1<<16) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM002_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_2_MEM002_I_MEM_PRTY_K2_SHIFT                                                    16
+  #define QM_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_BB                                                          (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_BB_SHIFT                                                    9
+  #define QM_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_K2                                                          (0x1<<17) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_K2_SHIFT                                                    17
+  #define QM_REG_PRTY_MASK_H_2_MEM009_I_MEM_PRTY_BB                                                          (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM009_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_2_MEM009_I_MEM_PRTY_BB_SHIFT                                                    10
+  #define QM_REG_PRTY_MASK_H_2_MEM009_I_MEM_PRTY_K2                                                          (0x1<<18) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM009_I_MEM_PRTY .
+  #define QM_REG_PRTY_MASK_H_2_MEM009_I_MEM_PRTY_K2_SHIFT                                                    18
+#define QM_REG_MEM_ECC_ENABLE_0_BB_K2                                                                        0x2f0230UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define QM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_0_EN_BB_K2                                                    (0x1<<0) // Enable ECC for memory ecc instance qm.QM_MEM_BIGRAM_TX_512PQTX_IF.i_qm_mem_bigram_tx.i_ecc_0 in module qm_mem_bigram_tx_512pqtx
+  #define QM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_0_EN_BB_K2_SHIFT                                              0
+  #define QM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_1_EN_BB_K2                                                    (0x1<<1) // Enable ECC for memory ecc instance qm.QM_MEM_BIGRAM_TX_512PQTX_IF.i_qm_mem_bigram_tx.i_ecc_1 in module qm_mem_bigram_tx_512pqtx
+  #define QM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_1_EN_BB_K2_SHIFT                                              1
+  #define QM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN_BB_K2                                                    (0x1<<2) // Enable ECC for memory ecc instance qm.QM_MEM_BIGRAM_OTHER_128PQOTHER_IF.i_qm_mem_bigram_other.i_ecc_0 in module qm_mem_bigram_other_128pqother
+  #define QM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN_BB_K2_SHIFT                                              2
+  #define QM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_BB_K2                                                    (0x1<<3) // Enable ECC for memory ecc instance qm.QM_MEM_BIGRAM_OTHER_128PQOTHER_IF.i_qm_mem_bigram_other.i_ecc_1 in module qm_mem_bigram_other_128pqother
+  #define QM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_BB_K2_SHIFT                                              3
+  #define QM_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN_BB_K2                                                      (0x1<<4) // Enable ECC for memory ecc instance qm.QM_MEM_PTR_TBL_TX_PQ_512PQTX_IF.i_qm_mem_ptr_tbl_tx_pq.i_ecc in module qm_mem_ptr_tbl_tx_pq_512pqtx
+  #define QM_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN_BB_K2_SHIFT                                                4
+#define QM_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                   0x2f0234UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define QM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_0_PRTY_BB_K2                                             (0x1<<0) // Set parity only for memory ecc instance qm.QM_MEM_BIGRAM_TX_512PQTX_IF.i_qm_mem_bigram_tx.i_ecc_0 in module qm_mem_bigram_tx_512pqtx
+  #define QM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_0_PRTY_BB_K2_SHIFT                                       0
+  #define QM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_1_PRTY_BB_K2                                             (0x1<<1) // Set parity only for memory ecc instance qm.QM_MEM_BIGRAM_TX_512PQTX_IF.i_qm_mem_bigram_tx.i_ecc_1 in module qm_mem_bigram_tx_512pqtx
+  #define QM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_1_PRTY_BB_K2_SHIFT                                       1
+  #define QM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY_BB_K2                                             (0x1<<2) // Set parity only for memory ecc instance qm.QM_MEM_BIGRAM_OTHER_128PQOTHER_IF.i_qm_mem_bigram_other.i_ecc_0 in module qm_mem_bigram_other_128pqother
+  #define QM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY_BB_K2_SHIFT                                       2
+  #define QM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_BB_K2                                             (0x1<<3) // Set parity only for memory ecc instance qm.QM_MEM_BIGRAM_OTHER_128PQOTHER_IF.i_qm_mem_bigram_other.i_ecc_1 in module qm_mem_bigram_other_128pqother
+  #define QM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_BB_K2_SHIFT                                       3
+  #define QM_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY_BB_K2                                               (0x1<<4) // Set parity only for memory ecc instance qm.QM_MEM_PTR_TBL_TX_PQ_512PQTX_IF.i_qm_mem_ptr_tbl_tx_pq.i_ecc in module qm_mem_ptr_tbl_tx_pq_512pqtx
+  #define QM_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY_BB_K2_SHIFT                                         4
+#define QM_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                               0x2f0238UL //Access:RC   DataWidth:0x5    // Multi Field Register.
+  #define QM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_0_CORRECT_BB_K2                                      (0x1<<0) // Record if a correctable error occurred on memory ecc instance qm.QM_MEM_BIGRAM_TX_512PQTX_IF.i_qm_mem_bigram_tx.i_ecc_0 in module qm_mem_bigram_tx_512pqtx
+  #define QM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_0_CORRECT_BB_K2_SHIFT                                0
+  #define QM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_1_CORRECT_BB_K2                                      (0x1<<1) // Record if a correctable error occurred on memory ecc instance qm.QM_MEM_BIGRAM_TX_512PQTX_IF.i_qm_mem_bigram_tx.i_ecc_1 in module qm_mem_bigram_tx_512pqtx
+  #define QM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_1_CORRECT_BB_K2_SHIFT                                1
+  #define QM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT_BB_K2                                      (0x1<<2) // Record if a correctable error occurred on memory ecc instance qm.QM_MEM_BIGRAM_OTHER_128PQOTHER_IF.i_qm_mem_bigram_other.i_ecc_0 in module qm_mem_bigram_other_128pqother
+  #define QM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT_BB_K2_SHIFT                                2
+  #define QM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_BB_K2                                      (0x1<<3) // Record if a correctable error occurred on memory ecc instance qm.QM_MEM_BIGRAM_OTHER_128PQOTHER_IF.i_qm_mem_bigram_other.i_ecc_1 in module qm_mem_bigram_other_128pqother
+  #define QM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_BB_K2_SHIFT                                3
+  #define QM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT_BB_K2                                        (0x1<<4) // Record if a correctable error occurred on memory ecc instance qm.QM_MEM_PTR_TBL_TX_PQ_512PQTX_IF.i_qm_mem_ptr_tbl_tx_pq.i_ecc in module qm_mem_ptr_tbl_tx_pq_512pqtx
+  #define QM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT_BB_K2_SHIFT                                  4
+#define QM_REG_MEM_ECC_EVENTS_BB_K2                                                                          0x2f023cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define QM_REG_WRC_DROP_CNT_0                                                                                0x2f0400UL //Access:R    DataWidth:0x8    // drop counter per write client fifo i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).
+#define QM_REG_WRC_DROP_CNT_1                                                                                0x2f0404UL //Access:R    DataWidth:0x8    // drop counter per write client fifo i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).
+#define QM_REG_WRC_DROP_CNT_2                                                                                0x2f0408UL //Access:R    DataWidth:0x8    // drop counter per write client fifo i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).
+#define QM_REG_WRC_DROP_CNT_3                                                                                0x2f040cUL //Access:R    DataWidth:0x8    // drop counter per write client fifo i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).
+#define QM_REG_WRC_DROP_CNT_4                                                                                0x2f0410UL //Access:R    DataWidth:0x8    // drop counter per write client fifo i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).
+#define QM_REG_WRC_DROP_CNT_5                                                                                0x2f0414UL //Access:R    DataWidth:0x8    // drop counter per write client fifo i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).
+#define QM_REG_WRC_FIFOLVL_0                                                                                 0x2f0418UL //Access:R    DataWidth:0x5    // Keep the fill level of the fifo from write client. i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).
+#define QM_REG_WRC_FIFOLVL_1                                                                                 0x2f041cUL //Access:R    DataWidth:0x5    // Keep the fill level of the fifo from write client. i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).
+#define QM_REG_WRC_FIFOLVL_2                                                                                 0x2f0420UL //Access:R    DataWidth:0x5    // Keep the fill level of the fifo from write client. i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).
+#define QM_REG_WRC_FIFOLVL_3                                                                                 0x2f0424UL //Access:R    DataWidth:0x5    // Keep the fill level of the fifo from write client. i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).
+#define QM_REG_WRC_FIFOLVL_4                                                                                 0x2f0428UL //Access:R    DataWidth:0x5    // Keep the fill level of the fifo from write client. i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).
+#define QM_REG_WRC_FIFOLVL_5                                                                                 0x2f042cUL //Access:R    DataWidth:0x5    // Keep the fill level of the fifo from write client. i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).
+#define QM_REG_CM_PUSH_INT_EN                                                                                0x2f0430UL //Access:RW   DataWidth:0x6    // Enable the write client. Bit: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).
+#define QM_REG_MAXPQSIZE_0                                                                                   0x2f0434UL //Access:RW   DataWidth:0x10   // The number of connections divided by 256 minus 1 which dictates the size of the queues which belong to the function for TX queues. There are 2 different values per fucntion and each PQ that belongs to the function can be associated with one of the values. values: 0: 256; 1: 512; ...; N-1: 256xN
+#define QM_REG_MAXPQSIZE_1                                                                                   0x2f0438UL //Access:RW   DataWidth:0x10   // The number of connections divided by 256 minus 1 which dictates the size of the queues which belong to the function for TX queues. There are 2 different values per fucntion and each PQ that belongs to the function can be associated with one of the values. values: 0: 256; 1: 512; ...; N-1: 256xN
+#define QM_REG_MAXPQSIZE_2                                                                                   0x2f043cUL //Access:RW   DataWidth:0x10   // The number of connections divided by 256 minus 1 which dictates the size of the queues which belong to the function for Other queues. There is single values per fucntion and each PQ that belongs to the function can be associated with one of the values. values: 0: 256; 1: 512; ...; N-1: 256xN
+#define QM_REG_MAXPQSIZETXSEL_0                                                                              0x2f0440UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_1                                                                              0x2f0444UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_2                                                                              0x2f0448UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_3                                                                              0x2f044cUL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_4                                                                              0x2f0450UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_5                                                                              0x2f0454UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_6                                                                              0x2f0458UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_7                                                                              0x2f045cUL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_8                                                                              0x2f0460UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_9                                                                              0x2f0464UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_10                                                                             0x2f0468UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_11                                                                             0x2f046cUL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_12                                                                             0x2f0470UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_13                                                                             0x2f0474UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_14                                                                             0x2f0478UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_15                                                                             0x2f047cUL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_16                                                                             0x2f0480UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_17                                                                             0x2f0484UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_18                                                                             0x2f0488UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_19                                                                             0x2f048cUL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_20                                                                             0x2f0490UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_21                                                                             0x2f0494UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_22                                                                             0x2f0498UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_23                                                                             0x2f049cUL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_24                                                                             0x2f04a0UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_25                                                                             0x2f04a4UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_26                                                                             0x2f04a8UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_27                                                                             0x2f04acUL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_28                                                                             0x2f04b0UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_29                                                                             0x2f04b4UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_30                                                                             0x2f04b8UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_31                                                                             0x2f04bcUL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_32                                                                             0x2f04c0UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_33                                                                             0x2f04c4UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_34                                                                             0x2f04c8UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_35                                                                             0x2f04ccUL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_36                                                                             0x2f04d0UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_37                                                                             0x2f04d4UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_38                                                                             0x2f04d8UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_39                                                                             0x2f04dcUL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_40                                                                             0x2f04e0UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_41                                                                             0x2f04e4UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_42                                                                             0x2f04e8UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_43                                                                             0x2f04ecUL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_44                                                                             0x2f04f0UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_45                                                                             0x2f04f4UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_46                                                                             0x2f04f8UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_47                                                                             0x2f04fcUL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_48                                                                             0x2f0500UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_49                                                                             0x2f0504UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_50                                                                             0x2f0508UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_51                                                                             0x2f050cUL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_52                                                                             0x2f0510UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_53                                                                             0x2f0514UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_54                                                                             0x2f0518UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_55                                                                             0x2f051cUL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_56_K2_E5                                                                       0x2f0520UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_57_K2_E5                                                                       0x2f0524UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_58_K2_E5                                                                       0x2f0528UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_59_K2_E5                                                                       0x2f052cUL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_60_K2_E5                                                                       0x2f0530UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_61_K2_E5                                                                       0x2f0534UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_62_K2_E5                                                                       0x2f0538UL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_MAXPQSIZETXSEL_63_K2_E5                                                                       0x2f053cUL //Access:RW   DataWidth:0x8    // Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.
+#define QM_REG_BASEADDROTHERPQ                                                                               0x2f0600UL //Access:RW   DataWidth:0x14   // The base logical address (in 4096 bytes) of each physical queue. The index I represents the physical queue number.
+#define QM_REG_BASEADDROTHERPQ_SIZE_BB                                                                       64
+#define QM_REG_BASEADDROTHERPQ_SIZE_K2_E5                                                                    128
+#define QM_REG_OUTLDREQSIZECONNTX                                                                            0x2f0800UL //Access:RW   DataWidth:0x5    // The max buffer size of the load request buffer within the RC response unit for the TX connection requests (goes to the CCFC). NOTE: The max size should be based on the actual buffer size.
+#define QM_REG_OUTLDREQSIZECONNOTHER                                                                         0x2f0804UL //Access:RW   DataWidth:0x5    // The max buffer size of the load request buffer within the RC response unit for the Other connection requests (goes to the CCFC). NOTE: The max size should be based on the actual buffer size.
+#define QM_REG_OUTLDREQCRDCONNTX                                                                             0x2f0808UL //Access:R    DataWidth:0x5    // The credit of the connection load request TX buffer. Describes the number of outstanding read requests (outstanding means sent by the RC request unit & didn't get CCFC load response yet). Each time the RC request unit sends a TX queue pop request towards the UQE this counter is decremented. Each time the CCFC sends load response this counter is incremented.
+#define QM_REG_OUTLDREQCRDCONNOTHER                                                                          0x2f080cUL //Access:R    DataWidth:0x5    // The credit of the connection load request Other buffer. Describes the number of outstanding read requests (outstanding means sent by the RC request unit & didn't get CCFC load response yet). Each time the RC request unit sends an Other queue pop request towards the UQE this counter is decremented. Each time the CCFC sends load response this counter is incremented.
+#define QM_REG_PTRTBLOTHER                                                                                   0x2f0c00UL //Access:WB   DataWidth:0x36   // Pointer Table Memory for Other queues 63-0; The mapping is as follow: ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank;.
+#define QM_REG_PTRTBLOTHER_SIZE_BB                                                                           128
+#define QM_REG_PTRTBLOTHER_SIZE_K2_E5                                                                        256
+#define QM_REG_BIGRAMTXADDR                                                                                  0x2f1000UL //Access:RW   DataWidth:0xd    // The address of the TX BigRam to access. Accessing the BigRam should be implemented as follows: (a) writing the address BigRamTxAddr; (b) writing the data BigRamTxData (for wr cmd only); (c) writing the cmd type BigRamTxCmd; (d) accessing the rd data BigRamTxData (for rd cmd only).
+#define QM_REG_BIGRAMTXDATA                                                                                  0x2f1008UL //Access:WB   DataWidth:0x3e   // The data of the TX bigRam to access (rd/wr). Accessing the BigRam should be implemented as follows: (a) writing the address BigRamTxAddr; (b) writing the data BigRamTxData (for wr cmd only); (c) writing the cmd type BigRamTxCmd; (d) accessing the rd data BigRamTxData (for rd cmd only).
+#define QM_REG_BIGRAMTXDATA_SIZE                                                                             2
+#define QM_REG_BIGRAMTXCMD                                                                                   0x2f1010UL //Access:W    DataWidth:0x1    // The mem access cmd (0 - rd; 1 - wr) sent towards of the TX bigRam. Accessing the BigRam should be implemented as follows: (a) writing the address BigRamTxAddr; (b) writing the data BigRamTxData (for wr cmd only); (c) writing the cmd type BigRamTxCmd; (d) accessing the rd data BigRamTxData (for rd cmd only).
+#define QM_REG_BIGRAMOTHERADDR                                                                               0x2f1014UL //Access:RW   DataWidth:0xb    // The address of the Other BigRam to access. Accessing the BigRam should be implemented as follows: (a) writing the address BigRamOtherAddr; (b) writing the data BigRamOtherData (for wr cmd only); (c) writing the cmd type BigRamOtherCmd; (d) accessing the rd data BigRamOtherData (for rd cmd only).
+#define QM_REG_BIGRAMOTHERDATA                                                                               0x2f1020UL //Access:WB   DataWidth:0x6e   // The data of the Other bigRam to access (rd/wr). Accessing the BigRam should be implemented as follows: (a) writing the address BigRamOtherAddr; (b) writing the data BigRamOtherData (for wr cmd only); (c) writing the cmd type BigRamOtherCmd; (d) accessing the rd data BigRamOtherData (for rd cmd only).
+#define QM_REG_BIGRAMOTHERDATA_SIZE                                                                          4
+#define QM_REG_BIGRAMOTHERCMD                                                                                0x2f1030UL //Access:W    DataWidth:0x1    // The mem access cmd (0 - rd; 1 - wr) sent towards of the Other bigRam. Accessing the BigRam should be implemented as follows: (a) writing the address BigRamOtherAddr; (b) writing the data BigRamOtherData (for wr cmd only); (c) writing the cmd type BigRamOtherCmd; (d) accessing the rd data BigRamOtherData (for rd cmd only).
+#define QM_REG_QSTATUSTX_0                                                                                   0x2f1040UL //Access:R    DataWidth:0x20   // Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;
+#define QM_REG_QSTATUSTX_1                                                                                   0x2f1044UL //Access:R    DataWidth:0x20   // Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;
+#define QM_REG_QSTATUSTX_2                                                                                   0x2f1048UL //Access:R    DataWidth:0x20   // Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;
+#define QM_REG_QSTATUSTX_3                                                                                   0x2f104cUL //Access:R    DataWidth:0x20   // Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;
+#define QM_REG_QSTATUSTX_4                                                                                   0x2f1050UL //Access:R    DataWidth:0x20   // Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;
+#define QM_REG_QSTATUSTX_5                                                                                   0x2f1054UL //Access:R    DataWidth:0x20   // Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;
+#define QM_REG_QSTATUSTX_6                                                                                   0x2f1058UL //Access:R    DataWidth:0x20   // Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;
+#define QM_REG_QSTATUSTX_7                                                                                   0x2f105cUL //Access:R    DataWidth:0x20   // Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;
+#define QM_REG_QSTATUSTX_8                                                                                   0x2f1060UL //Access:R    DataWidth:0x20   // Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;
+#define QM_REG_QSTATUSTX_9                                                                                   0x2f1064UL //Access:R    DataWidth:0x20   // Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;
+#define QM_REG_QSTATUSTX_10                                                                                  0x2f1068UL //Access:R    DataWidth:0x20   // Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;
+#define QM_REG_QSTATUSTX_11                                                                                  0x2f106cUL //Access:R    DataWidth:0x20   // Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;
+#define QM_REG_QSTATUSTX_12                                                                                  0x2f1070UL //Access:R    DataWidth:0x20   // Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;
+#define QM_REG_QSTATUSTX_13                                                                                  0x2f1074UL //Access:R    DataWidth:0x20   // Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;
+#define QM_REG_QSTATUSTX_14_K2_E5                                                                            0x2f1078UL //Access:R    DataWidth:0x20   // Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;
+#define QM_REG_QSTATUSTX_15_K2_E5                                                                            0x2f107cUL //Access:R    DataWidth:0x20   // Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;
+#define QM_REG_QSTATUSOTHER_0                                                                                0x2f10c0UL //Access:R    DataWidth:0x20   // Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Queues 96-127 in n=3.
+#define QM_REG_QSTATUSOTHER_1                                                                                0x2f10c4UL //Access:R    DataWidth:0x20   // Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Queues 96-127 in n=3.
+#define QM_REG_QSTATUSOTHER_2_K2_E5                                                                          0x2f10c8UL //Access:R    DataWidth:0x20   // Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Queues 96-127 in n=3.
+#define QM_REG_QSTATUSOTHER_3_K2_E5                                                                          0x2f10ccUL //Access:R    DataWidth:0x20   // Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Queues 96-127 in n=3.
+#define QM_REG_CTXREGCCFC_0                                                                                  0x2f1120UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_1                                                                                  0x2f1124UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_2                                                                                  0x2f1128UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_3                                                                                  0x2f112cUL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_4                                                                                  0x2f1130UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_5                                                                                  0x2f1134UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_6                                                                                  0x2f1138UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_7                                                                                  0x2f113cUL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_8                                                                                  0x2f1140UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_9                                                                                  0x2f1144UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_10                                                                                 0x2f1148UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_11                                                                                 0x2f114cUL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_12                                                                                 0x2f1150UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_13                                                                                 0x2f1154UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_14                                                                                 0x2f1158UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_15                                                                                 0x2f115cUL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_16                                                                                 0x2f1160UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_17                                                                                 0x2f1164UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_18                                                                                 0x2f1168UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_19                                                                                 0x2f116cUL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_20                                                                                 0x2f1170UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_21                                                                                 0x2f1174UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_22                                                                                 0x2f1178UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_23                                                                                 0x2f117cUL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_24                                                                                 0x2f1180UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_25                                                                                 0x2f1184UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_26                                                                                 0x2f1188UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_27                                                                                 0x2f118cUL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_28                                                                                 0x2f1190UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_29                                                                                 0x2f1194UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_30                                                                                 0x2f1198UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_31                                                                                 0x2f119cUL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_32                                                                                 0x2f11a0UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_33                                                                                 0x2f11a4UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_34                                                                                 0x2f11a8UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_35                                                                                 0x2f11acUL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_36                                                                                 0x2f11b0UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_37                                                                                 0x2f11b4UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_38                                                                                 0x2f11b8UL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGCCFC_39                                                                                 0x2f11bcUL //Access:RW   DataWidth:0x8    // The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_0                                                                                  0x2f1220UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_1                                                                                  0x2f1224UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_2                                                                                  0x2f1228UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_3                                                                                  0x2f122cUL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_4                                                                                  0x2f1230UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_5                                                                                  0x2f1234UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_6                                                                                  0x2f1238UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_7                                                                                  0x2f123cUL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_8                                                                                  0x2f1240UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_9                                                                                  0x2f1244UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_10                                                                                 0x2f1248UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_11                                                                                 0x2f124cUL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_12                                                                                 0x2f1250UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_13                                                                                 0x2f1254UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_14                                                                                 0x2f1258UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_15                                                                                 0x2f125cUL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_16                                                                                 0x2f1260UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_17                                                                                 0x2f1264UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_18                                                                                 0x2f1268UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_19                                                                                 0x2f126cUL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_20                                                                                 0x2f1270UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_21                                                                                 0x2f1274UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_22                                                                                 0x2f1278UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_23                                                                                 0x2f127cUL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_24                                                                                 0x2f1280UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_25                                                                                 0x2f1284UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_26                                                                                 0x2f1288UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_27                                                                                 0x2f128cUL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_28                                                                                 0x2f1290UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_29                                                                                 0x2f1294UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_30                                                                                 0x2f1298UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_31                                                                                 0x2f129cUL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_32                                                                                 0x2f12a0UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_33                                                                                 0x2f12a4UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_34                                                                                 0x2f12a8UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_35                                                                                 0x2f12acUL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_36                                                                                 0x2f12b0UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_37                                                                                 0x2f12b4UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_38                                                                                 0x2f12b8UL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_CTXREGTCFC_39                                                                                 0x2f12bcUL //Access:RW   DataWidth:0x8    // The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_0                                                                           0x2f1320UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_1                                                                           0x2f1324UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_2                                                                           0x2f1328UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_3                                                                           0x2f132cUL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_4                                                                           0x2f1330UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_5                                                                           0x2f1334UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_6                                                                           0x2f1338UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_7                                                                           0x2f133cUL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_8                                                                           0x2f1340UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_9                                                                           0x2f1344UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_10                                                                          0x2f1348UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_11                                                                          0x2f134cUL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_12                                                                          0x2f1350UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_13                                                                          0x2f1354UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_14                                                                          0x2f1358UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_15                                                                          0x2f135cUL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_16                                                                          0x2f1360UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_17                                                                          0x2f1364UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_18                                                                          0x2f1368UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_19                                                                          0x2f136cUL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_20                                                                          0x2f1370UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_21                                                                          0x2f1374UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_22                                                                          0x2f1378UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_23                                                                          0x2f137cUL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_24                                                                          0x2f1380UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_25                                                                          0x2f1384UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_26                                                                          0x2f1388UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_27                                                                          0x2f138cUL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_28                                                                          0x2f1390UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_29                                                                          0x2f1394UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_30                                                                          0x2f1398UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_31                                                                          0x2f139cUL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_32                                                                          0x2f13a0UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_33                                                                          0x2f13a4UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_34                                                                          0x2f13a8UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_35                                                                          0x2f13acUL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_36                                                                          0x2f13b0UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_37                                                                          0x2f13b4UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_38                                                                          0x2f13b8UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALCCFC_39                                                                          0x2f13bcUL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_0                                                                           0x2f1420UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_1                                                                           0x2f1424UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_2                                                                           0x2f1428UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_3                                                                           0x2f142cUL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_4                                                                           0x2f1430UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_5                                                                           0x2f1434UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_6                                                                           0x2f1438UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_7                                                                           0x2f143cUL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_8                                                                           0x2f1440UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_9                                                                           0x2f1444UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_10                                                                          0x2f1448UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_11                                                                          0x2f144cUL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_12                                                                          0x2f1450UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_13                                                                          0x2f1454UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_14                                                                          0x2f1458UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_15                                                                          0x2f145cUL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_16                                                                          0x2f1460UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_17                                                                          0x2f1464UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_18                                                                          0x2f1468UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_19                                                                          0x2f146cUL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_20                                                                          0x2f1470UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_21                                                                          0x2f1474UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_22                                                                          0x2f1478UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_23                                                                          0x2f147cUL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_24                                                                          0x2f1480UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_25                                                                          0x2f1484UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_26                                                                          0x2f1488UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_27                                                                          0x2f148cUL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_28                                                                          0x2f1490UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_29                                                                          0x2f1494UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_30                                                                          0x2f1498UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_31                                                                          0x2f149cUL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_32                                                                          0x2f14a0UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_33                                                                          0x2f14a4UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_34                                                                          0x2f14a8UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_35                                                                          0x2f14acUL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_36                                                                          0x2f14b0UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_37                                                                          0x2f14b4UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_38                                                                          0x2f14b8UL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_ACTCTRINITVALTCFC_39                                                                          0x2f14bcUL //Access:RW   DataWidth:0x8    // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)
+#define QM_REG_PCIREQQID                                                                                     0x2f1520UL //Access:RW   DataWidth:0x5    // The virtual Queue ID used in the PCI request.
+#define QM_REG_PCIREQAT                                                                                      0x2f1524UL //Access:RW   DataWidth:0x2    // The PCI attributes field used in the PCI request.
+#define QM_REG_PCIREQATC                                                                                     0x2f1528UL //Access:RW   DataWidth:0x18   // The PCI ATC flags used in the PCI request. b2-b0: rd first bank in page; b3: reserved (zero); b6-b4: wr first bank in page; b7: reserved (zero); b10-b8: rd middle bank in page; b11: reserved (zero); b14-b12: wr middle bank in page; b15: reserved (zero); b18-b16: rd last bank in page; b19: reserved (zero); b22-b20: wr last bank in page; b23: reserved (zero);.
+#define QM_REG_QMPAGESIZE                                                                                    0x2f152cUL //Access:RW   DataWidth:0x5    // The STU size; this should be configured according to the minimal STU within the PXP (there is STU per PF). 0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M.
+#define QM_REG_PCIREQTPH                                                                                     0x2f1530UL //Access:RW   DataWidth:0x10   // The PCI TPH field used in the PCI request. Per PF value. bits: 8-0 TPH Steering Tag Index; 12-9 reserved; 14-13 TPH ST hint; 15 TPH Valid.
+#define QM_REG_PCIREQPADTOCACHELINE                                                                          0x2f1534UL //Access:RW   DataWidth:0x1    // pad to cache line field as part of PXP write request
+#define QM_REG_OVFQNUMTX                                                                                     0x2f1538UL //Access:RC   DataWidth:0x9    // The Q were the qverflow occurs.
+#define QM_REG_OVFERRORTX                                                                                    0x2f153cUL //Access:RC   DataWidth:0x1    // A flag to indicate that overflow error occurred in one of the queues.
+#define QM_REG_OVFQNUMOTHER                                                                                  0x2f1540UL //Access:RC   DataWidth:0x6    // The Q were the qverflow occurs.
+#define QM_REG_OVFERROROTHER                                                                                 0x2f1544UL //Access:RC   DataWidth:0x1    // A flag to indicate that overflow error occurred in one of the queues.
+#define QM_REG_VOQCRDLINEFULL                                                                                0x2f1600UL //Access:R    DataWidth:0x20   // VoqCrdLineFull (This one) - VOQs [0..31] VoqCrdLineFull_msb        - VOQs [32..35] Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [8..31] are "not used". port_mode == 1 (2 port device) : VOQs [16..31] are "not used". port_mode == 2 (4 port device) : VOQs [6,7,14,15,22,23,30,31] are "not used" When set, inidicates that the VOQ line credit counter is equal to the VOQ line init value. There is a bit per VOQ.
+#define QM_REG_TASKLINECRDCOST                                                                               0x2f1700UL //Access:RW   DataWidth:0x8    // The lineVOQ credit cost per every task in the QM.  must be smaller or equal to the matched Voq line credit (relevant only for VOQs that are being used - or in other words VOQs that have at least single PQ that is associated with the VOQ). Granularity of 16B.
+#define QM_REG_VOQCRDBYTEFULL                                                                                0x2f1800UL //Access:R    DataWidth:0x20   // VoqCrdByteFull (This one) - VOQs [0..31]. VoqCrdByteFull_msb        - VOQs [32..35]. Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [8..31] are "not used". port_mode == 1 (2 port device) : VOQs [16..31] are "not used". port_mode == 2 (4 port device) : VOQs [6,7,14,15,22,23,30,31] are "not used". When set, inidicates that the VOQ byte credit counter is equal to the VOQ byte init value. There is a bit per VOQ.
+#define QM_REG_TASKBYTECRDCOST_0                                                                             0x2f1900UL //Access:RW   DataWidth:0x10   // The byte credit cost per every task in the QM that will be used for charging the different byte credit resources. i: 0 - VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functional mode all byte credits will have the same value. must be smaller or equal to the matched Voq byte redit (relevant only for VOQs that are being used - or in other words VOQs that have at least single PQ that is associated with the VOQ).
+#define QM_REG_TASKBYTECRDCOST_1                                                                             0x2f1904UL //Access:RW   DataWidth:0x10   // The byte credit cost per every task in the QM that will be used for charging the different byte credit resources. i: 0 - VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functional mode all byte credits will have the same value. must be smaller or equal to the matched Voq byte redit (relevant only for VOQs that are being used - or in other words VOQs that have at least single PQ that is associated with the VOQ).
+#define QM_REG_TASKBYTECRDCOST_2                                                                             0x2f1908UL //Access:RW   DataWidth:0x10   // The byte credit cost per every task in the QM that will be used for charging the different byte credit resources. i: 0 - VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functional mode all byte credits will have the same value. must be smaller or equal to the matched Voq byte redit (relevant only for VOQs that are being used - or in other words VOQs that have at least single PQ that is associated with the VOQ).
+#define QM_REG_TASKBYTECRDCOST_3                                                                             0x2f190cUL //Access:RW   DataWidth:0x10   // The byte credit cost per every task in the QM that will be used for charging the different byte credit resources. i: 0 - VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functional mode all byte credits will have the same value. must be smaller or equal to the matched Voq byte redit (relevant only for VOQs that are being used - or in other words VOQs that have at least single PQ that is associated with the VOQ).
+#define QM_REG_TASKBYTECRDCOST_4                                                                             0x2f1910UL //Access:RW   DataWidth:0x10   // The byte credit cost per every task in the QM that will be used for charging the different byte credit resources. i: 0 - VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functional mode all byte credits will have the same value. must be smaller or equal to the matched Voq byte redit (relevant only for VOQs that are being used - or in other words VOQs that have at least single PQ that is associated with the VOQ).
+#define QM_REG_AFULLQMBYPTHRLINEVOQMASK                                                                      0x2f1914UL //Access:RW   DataWidth:0x20   // VOQ line credit almost full threshold mask for the QM bypass feature (per VOQ id bit). AFullQmBypThrLineVoqMask (This one) - VOQs [0..31]. AFullQmBypThrLineVoqMask_msb        - VOQs [32..35]. Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [8..31] are "not used". port_mode == 1 (2 port device) : VOQs [16..31] are "not used". port_mode == 2 (4 port device) : VOQs [6,7,14,15,22,23,30,31] are "not used" When 1 the VOQ line credit counter should be equal to the VOQ line init value to enable bypass. When 0 - the VOQ line credit counter is don't care, and bypass can be implemented regardless of the VOQ line counter value.
+#define QM_REG_AFULLQMBYPTHRPFWFQ                                                                            0x2f1918UL //Access:RW   DataWidth:0x20   // PF WFQ byte credit almost full threshold for the qm bypass operation.
+#define QM_REG_AFULLQMBYPTHRVPWFQ                                                                            0x2f191cUL //Access:RW   DataWidth:0x20   // VP WFQ byte credit almost full threshold for the qm bypass operation.
+#define QM_REG_AFULLQMBYPTHRPFRL                                                                             0x2f1920UL //Access:RW   DataWidth:0x20   // PF RL byte credit almost full threshold for the qm bypass operation.
+#define QM_REG_AFULLQMBYPTHRGLBLRL                                                                           0x2f1924UL //Access:RW   DataWidth:0x20   // Global VP/QCN RL byte credit almost full threshold for the qm bypass operation.
+#define QM_REG_AFULLQMBYPMASK                                                                                0x2f1928UL //Access:RW   DataWidth:0x7    // Mask bit per credit resource for the qm bypass. 1 - resource is required to be more than the almost full threshold. 0 - resource value is do not care; 0 - line VOQ; 1 - reserved; 2 - PF WFQ; 3 - VP WFQ; 4 - PF RL; 5 - global VP-QCN RL; 6 - FW stop;
+#define QM_REG_AFULLOPRTNSTCTHRLINEVOQ                                                                       0x2f192cUL //Access:RW   DataWidth:0x10   // VOQ line credit almost full threshold for the opportunistic credit flow operation. reset value: +2 x TaskLineCrdCost
+#define QM_REG_AFULLOPRTNSTCTHRBYTEVOQ                                                                       0x2f1930UL //Access:RW   DataWidth:0x18   // VOQ byte credit almost full threshold for the opportunistic credit flow operation. reset value: +2 x TaskByteCrdCost_0
+#define QM_REG_AFULLOPRTNSTCTHRPFWFQ                                                                         0x2f1934UL //Access:RW   DataWidth:0x20   // PF WFQ byte credit almost full threshold for the opportunistic credit flow operation. reset value: -1 x TaskByteCrdCost_3
+#define QM_REG_AFULLOPRTNSTCTHRVPWFQ                                                                         0x2f1938UL //Access:RW   DataWidth:0x20   // VP WFQ byte credit almost full threshold for the opportunistic credit flow operation. reset value: -1 x TaskByteCrdCost_4
+#define QM_REG_AFULLOPRTNSTCTHRPFRL                                                                          0x2f193cUL //Access:RW   DataWidth:0x20   // PF RL byte credit almost full threshold for the opportunistic credit flow operation. reset value: +2 x TaskByteCrdCost_1
+#define QM_REG_AFULLOPRTNSTCTHRGLBLRL                                                                        0x2f1940UL //Access:RW   DataWidth:0x20   // Global VP/QCN RL byte credit almost full threshold for the opportunistic credit flow operation. reset value: +2 x TaskByteCrdCost_2
+#define QM_REG_AFULLOPRTNSTCCRDMASK                                                                          0x2f1944UL //Access:RW   DataWidth:0x9    // Mask bit per credit resource for the opportunistic credit. 1 - resource is required to be more than the almost full threshold. 0 - resource value is do not care; 0 - line VOQ; 1 - byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 - PF RL; 5 - global VP-QCN RL; 6 - FW stop; 7 - reserved; 8 - PQ Empty.
+#define QM_REG_QMBYPENABLE                                                                                   0x2f1948UL //Access:RW   DataWidth:0x1    // Allows the QM to work in qm bypass mode. i.e. sending the bypass indication when conditions are met and open the XCM bypass request interface from the XCM.
+#define QM_REG_OPRTNSTCCRDENABLE                                                                             0x2f194cUL //Access:RW   DataWidth:0x1    // Allows the QM to answer and handle opportunistic bypass requests (i.e. which PQ credit info?) from the Xstorm. otherwise return null on the GPI interface.
+#define QM_REG_QMBYPGLBLCNT_0                                                                                0x2f1950UL //Access:R    DataWidth:0xa    // Global per type counter that counts the number of counters of the same type that are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 - PF R; 5 - Global VP/QCN RL.
+#define QM_REG_QMBYPGLBLCNT_1                                                                                0x2f1954UL //Access:R    DataWidth:0xa    // Global per type counter that counts the number of counters of the same type that are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 - PF R; 5 - Global VP/QCN RL.
+#define QM_REG_QMBYPGLBLCNT_2                                                                                0x2f1958UL //Access:R    DataWidth:0xa    // Global per type counter that counts the number of counters of the same type that are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 - PF R; 5 - Global VP/QCN RL.
+#define QM_REG_QMBYPGLBLCNT_3                                                                                0x2f195cUL //Access:R    DataWidth:0xa    // Global per type counter that counts the number of counters of the same type that are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 - PF R; 5 - Global VP/QCN RL.
+#define QM_REG_QMBYPGLBLCNT_4                                                                                0x2f1960UL //Access:R    DataWidth:0xa    // Global per type counter that counts the number of counters of the same type that are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 - PF R; 5 - Global VP/QCN RL.
+#define QM_REG_QMBYPGLBLCNT_5                                                                                0x2f1964UL //Access:R    DataWidth:0xa    // Global per type counter that counts the number of counters of the same type that are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 - PF R; 5 - Global VP/QCN RL.
+#define QM_REG_WRROTHERPQGRP_0                                                                               0x2f1968UL //Access:RW   DataWidth:0x20   // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
+#define QM_REG_WRROTHERPQGRP_1                                                                               0x2f196cUL //Access:RW   DataWidth:0x20   // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
+#define QM_REG_WRROTHERPQGRP_2                                                                               0x2f1970UL //Access:RW   DataWidth:0x20   // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
+#define QM_REG_WRROTHERPQGRP_3                                                                               0x2f1974UL //Access:RW   DataWidth:0x20   // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
+#define QM_REG_WRROTHERPQGRP_4                                                                               0x2f1978UL //Access:RW   DataWidth:0x20   // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
+#define QM_REG_WRROTHERPQGRP_5                                                                               0x2f197cUL //Access:RW   DataWidth:0x20   // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
+#define QM_REG_WRROTHERPQGRP_6                                                                               0x2f1980UL //Access:RW   DataWidth:0x20   // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
+#define QM_REG_WRROTHERPQGRP_7                                                                               0x2f1984UL //Access:RW   DataWidth:0x20   // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
+#define QM_REG_WRROTHERPQGRP_8_K2_E5                                                                         0x2f1988UL //Access:RW   DataWidth:0x20   // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
+#define QM_REG_WRROTHERPQGRP_9_K2_E5                                                                         0x2f198cUL //Access:RW   DataWidth:0x20   // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
+#define QM_REG_WRROTHERPQGRP_10_K2_E5                                                                        0x2f1990UL //Access:RW   DataWidth:0x20   // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
+#define QM_REG_WRROTHERPQGRP_11_K2_E5                                                                        0x2f1994UL //Access:RW   DataWidth:0x20   // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
+#define QM_REG_WRROTHERPQGRP_12_K2_E5                                                                        0x2f1998UL //Access:RW   DataWidth:0x20   // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
+#define QM_REG_WRROTHERPQGRP_13_K2_E5                                                                        0x2f199cUL //Access:RW   DataWidth:0x20   // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
+#define QM_REG_WRROTHERPQGRP_14_K2_E5                                                                        0x2f19a0UL //Access:RW   DataWidth:0x20   // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
+#define QM_REG_WRROTHERPQGRP_15_K2_E5                                                                        0x2f19a4UL //Access:RW   DataWidth:0x20   // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
+#define QM_REG_WRROTHERGRPWEIGHT_0                                                                           0x2f19e8UL //Access:RW   DataWidth:0x8    // The actual WRR weight that is used by Other PQ-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are either empty or paused. NOTE: (a) if all WrrOtherGrpWeight (3-0) are = 0 --> RR (b) if all WrrOtherGrpWeight (3-0) are > 0 --> WRR in that case the WrrOtherGrpWeight should be ordered. WrrOtherGrpWeight_0 should be configured with the smallest value. WrrOtherGrpWeight_1 should be next (and bigger than WrrOtherGrpWeight_0). WrrOtherGrpWeight_2 should be next (and bigger than WrrOtherGrpWeight_1). WrrOtherGrpWeight_3 should be configured with the max value (bigger than WrrOtherGrpWeight_2). (c) either (a) or (b) are allowed. Weight=0 for some and weight>0 for others is not legal.
+#define QM_REG_WRROTHERGRPWEIGHT_1                                                                           0x2f19ecUL //Access:RW   DataWidth:0x8    // The actual WRR weight that is used by Other PQ-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are either empty or paused. NOTE: (a) if all WrrOtherGrpWeight (3-0) are = 0 --> RR (b) if all WrrOtherGrpWeight (3-0) are > 0 --> WRR in that case the WrrOtherGrpWeight should be ordered. WrrOtherGrpWeight_0 should be configured with the smallest value. WrrOtherGrpWeight_1 should be next (and bigger than WrrOtherGrpWeight_0). WrrOtherGrpWeight_2 should be next (and bigger than WrrOtherGrpWeight_1). WrrOtherGrpWeight_3 should be configured with the max value (bigger than WrrOtherGrpWeight_2). (c) either (a) or (b) are allowed. Weight=0 for some and weight>0 for others is not legal.
+#define QM_REG_WRROTHERGRPWEIGHT_2                                                                           0x2f19f0UL //Access:RW   DataWidth:0x8    // The actual WRR weight that is used by Other PQ-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are either empty or paused. NOTE: (a) if all WrrOtherGrpWeight (3-0) are = 0 --> RR (b) if all WrrOtherGrpWeight (3-0) are > 0 --> WRR in that case the WrrOtherGrpWeight should be ordered. WrrOtherGrpWeight_0 should be configured with the smallest value. WrrOtherGrpWeight_1 should be next (and bigger than WrrOtherGrpWeight_0). WrrOtherGrpWeight_2 should be next (and bigger than WrrOtherGrpWeight_1). WrrOtherGrpWeight_3 should be configured with the max value (bigger than WrrOtherGrpWeight_2). (c) either (a) or (b) are allowed. Weight=0 for some and weight>0 for others is not legal.
+#define QM_REG_WRROTHERGRPWEIGHT_3                                                                           0x2f19f4UL //Access:RW   DataWidth:0x8    // The actual WRR weight that is used by Other PQ-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are either empty or paused. NOTE: (a) if all WrrOtherGrpWeight (3-0) are = 0 --> RR (b) if all WrrOtherGrpWeight (3-0) are > 0 --> WRR in that case the WrrOtherGrpWeight should be ordered. WrrOtherGrpWeight_0 should be configured with the smallest value. WrrOtherGrpWeight_1 should be next (and bigger than WrrOtherGrpWeight_0). WrrOtherGrpWeight_2 should be next (and bigger than WrrOtherGrpWeight_1). WrrOtherGrpWeight_3 should be configured with the max value (bigger than WrrOtherGrpWeight_2). (c) either (a) or (b) are allowed. Weight=0 for some and weight>0 for others is not legal.
+#define QM_REG_WRRTXGRPWEIGHT_0                                                                              0x2f1a08UL //Access:RW   DataWidth:0x8    // The actual WRR weight that is used by TX PQ-s that belong to TxPqMap[WrrWeightGrpRng]==2'b01. NOTE: weight update is allowed only to queues which are either empty or paused. NOTE: (a) if all WrrTxGrpWeight (1-0) are = 0 --> RR (b) if all WrrTxGrpWeight (1-0) are > 0 --> WRR in that case the WrrTxGrpWeight should be ordered. WrrTxGrpWeight_0 should be configured with the smallest value. WrrTxGrpWeight_1 should be configured with the max value (bigger than WrrTxGrpWeight_0). (c) either (a) or (b) are allowed. Weight=0 for some and weight>0 for others is not legal.
+#define QM_REG_WRRTXGRPWEIGHT_1                                                                              0x2f1a0cUL //Access:RW   DataWidth:0x8    // The actual WRR weight that is used by TX PQ-s that belong to TxPqMap[WrrWeightGrpRng]==2'b11. NOTE: weight update is allowed only to queues which are either empty or paused. NOTE: (a) if all WrrTxGrpWeight (1-0) are = 0 --> RR (b) if all WrrTxGrpWeight (1-0) are > 0 --> WRR in that case the WrrTxGrpWeight should be ordered. WrrTxGrpWeight_0 should be configured with the smallest value. WrrTxGrpWeight_1 should be configured with the max value (bigger than WrrTxGrpWeight_0). (c) either (a) or (b) are allowed. Weight=0 for some and weight>0 for others is not legal.
+#define QM_REG_CMINITCRD_0                                                                                   0x2f1a10UL //Access:RW   DataWidth:0x5    // The initial credit for interface; MCM Secondary.
+#define QM_REG_CMINITCRD_1                                                                                   0x2f1a14UL //Access:RW   DataWidth:0x5    // The initial credit for interface; MCM Primary.
+#define QM_REG_CMINITCRD_2                                                                                   0x2f1a18UL //Access:RW   DataWidth:0x5    // The initial credit for interface; UCM Secondary.
+#define QM_REG_CMINITCRD_3                                                                                   0x2f1a1cUL //Access:RW   DataWidth:0x5    // The initial credit for interface; UCM Primary.
+#define QM_REG_CMINITCRD_4                                                                                   0x2f1a20UL //Access:RW   DataWidth:0x5    // The initial credit for interface; TCM Secondary.
+#define QM_REG_CMINITCRD_5                                                                                   0x2f1a24UL //Access:RW   DataWidth:0x5    // The initial credit for interface; TCM Primary.
+#define QM_REG_CMINITCRD_6                                                                                   0x2f1a28UL //Access:RW   DataWidth:0x5    // The initial credit for interface; YCM Secondary.
+#define QM_REG_CMINITCRD_7                                                                                   0x2f1a2cUL //Access:RW   DataWidth:0x5    // The initial credit for interface; YCM Primary.
+#define QM_REG_CMINITCRD_8                                                                                   0x2f1a30UL //Access:RW   DataWidth:0x5    // The initial credit for interface; XCM Secondary.
+#define QM_REG_CMINITCRD_9                                                                                   0x2f1a34UL //Access:RW   DataWidth:0x5    // The initial credit for interface; XCM Primary.
+#define QM_REG_CMCRD_0                                                                                       0x2f1a38UL //Access:R    DataWidth:0x5    // The actual credit for the interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM pri;.
+#define QM_REG_CMCRD_1                                                                                       0x2f1a3cUL //Access:R    DataWidth:0x5    // The actual credit for the interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM pri;.
+#define QM_REG_CMCRD_2                                                                                       0x2f1a40UL //Access:R    DataWidth:0x5    // The actual credit for the interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM pri;.
+#define QM_REG_CMCRD_3                                                                                       0x2f1a44UL //Access:R    DataWidth:0x5    // The actual credit for the interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM pri;.
+#define QM_REG_CMCRD_4                                                                                       0x2f1a48UL //Access:R    DataWidth:0x5    // The actual credit for the interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM pri;.
+#define QM_REG_CMCRD_5                                                                                       0x2f1a4cUL //Access:R    DataWidth:0x5    // The actual credit for the interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM pri;.
+#define QM_REG_CMCRD_6                                                                                       0x2f1a50UL //Access:R    DataWidth:0x5    // The actual credit for the interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM pri;.
+#define QM_REG_CMCRD_7                                                                                       0x2f1a54UL //Access:R    DataWidth:0x5    // The actual credit for the interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM pri;.
+#define QM_REG_CMCRD_8                                                                                       0x2f1a58UL //Access:R    DataWidth:0x5    // The actual credit for the interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM pri;.
+#define QM_REG_CMCRD_9                                                                                       0x2f1a5cUL //Access:R    DataWidth:0x5    // The actual credit for the interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM pri;.
+#define QM_REG_CMINTEN                                                                                       0x2f1a60UL //Access:RW   DataWidth:0xa    // A mask bit per CM interface. If this bit is 0 then this interface is masked.  i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM pri;.
+#define QM_REG_CMINTQMASK                                                                                    0x2f1c00UL //Access:RW   DataWidth:0x8    // A bit vector per CM interface which indicates which one of the Other queues are tied to the matched CM interface. address: 7-0 MCM sec; 15-8 MCM pri; 23-16 UCM sec; 31-24 UCM pri; 39-32 TCM sec; 47-40 TCM pri; 55-48 YCM sec; 63-56 YCM pri; 71-64 XCM sec; for addr[2:0]=0 Other queues 7-0; for addr[2:0]=1 Other queues 15-8; for addr[2:0]=7 Other queues 63-56.
+#define QM_REG_CMINTQMASK_SIZE                                                                               72
+#define QM_REG_VOQBYTECRDENABLE                                                                              0x2f1e00UL //Access:RW   DataWidth:0x1    // Enables the VOQ byte credit logic.
+#define QM_REG_SDMCMDADDR                                                                                    0x2f1e04UL //Access:RW   DataWidth:0x8    // SDM command address. This reg is used for sending SDM command through the RBC. See command description in the QM EAS section SDM memory map. Required flow: (a) Poll on the SdmCmdReady bit (i.e. SdmCmdReady=1). (b) Write SdmCmdAddr, SdmCmdDataLsb and SdmCmdDataMsb (c) Send SdmCmdGo command: (1) wr value=1; and then (2) wr value=0.
+#define QM_REG_SDMCMDDATALSB                                                                                 0x2f1e08UL //Access:RW   DataWidth:0x20   // SDM command data lsb. This reg is used for sending SDM command through the RBC. See command description in the QM EAS section SDM memory map. Required flow: (a) Poll on the SdmCmdReady bit (i.e. SdmCmdReady=1). (b) Write SdmCmdAddr, SdmCmdDataLsb and SdmCmdDataMsb (c) Send SdmCmdGo command: (1) wr value=1; and then (2) wr value=0.
+#define QM_REG_SDMCMDDATAMSB                                                                                 0x2f1e0cUL //Access:RW   DataWidth:0x20   // SDM command data msb. This reg is used for sending SDM command through the RBC. See command description in the QM EAS section SDM memory map. Required flow: (a) Poll on the SdmCmdReady bit (i.e. SdmCmdReady=1). (b) Write SdmCmdAddr, SdmCmdDataLsb and SdmCmdDataMsb (c) Send SdmCmdGo command: (1) wr value=1; and then (2) wr value=0.
+#define QM_REG_SDMCMDREADY                                                                                   0x2f1e10UL //Access:R    DataWidth:0x1    // SDM command Ready. This reg is used for sending SDM command through the RBC. See command description in the QM EAS section SDM memory map. Required flow: (a) Poll on the SdmCmdReady bit (i.e. SdmCmdReady=1). (b) Write SdmCmdAddr, SdmCmdDataLsb and SdmCmdDataMsb (c) Send SdmCmdGo command: (1) wr value=1; and then (2) wr value=0.
+#define QM_REG_SDMCMDGO                                                                                      0x2f1e14UL //Access:RW   DataWidth:0x1    // SDM command Ready. This reg is used for sending SDM command through the RBC. See command description in the QM EAS section SDM memory map. Required flow: (a) Poll on the SdmCmdReady bit (i.e. SdmCmdReady=1). (b) Write SdmCmdAddr, SdmCmdDataLsb and SdmCmdDataMsb (c) Send SdmCmdGo command: wr value=1.
+#define QM_REG_PQFILLLVLOTHER                                                                                0x2f2000UL //Access:RW   DataWidth:0x18   // The number of tasks queued for each Other queue. Should be read only access.
+#define QM_REG_PQFILLLVLOTHER_SIZE_BB                                                                        64
+#define QM_REG_PQFILLLVLOTHER_SIZE_K2_E5                                                                     128
+#define QM_REG_MHQTXNUMSEL                                                                                   0x2f2400UL //Access:RW   DataWidth:0x9    // The physical queue number for the MAX hold TX queue fill level statistics.
+#define QM_REG_QTXLEVELMHVAL                                                                                 0x2f2404UL //Access:RC   DataWidth:0x18   // The MAX hold value of the fill level of the TX physical queue.
+#define QM_REG_MHQOTHERNUMSEL                                                                                0x2f2408UL //Access:RW   DataWidth:0x7    // The physical queue number for the MAX hold Other queue fill level statistics.
+#define QM_REG_QOTHERLEVELMHVAL                                                                              0x2f240cUL //Access:RC   DataWidth:0x18   // The MAX hold value of the fill level of the Other physical queue.
+#define QM_REG_PQSTSOTHER                                                                                    0x2f2800UL //Access:R    DataWidth:0x1    // The status of the Other PQ-s: bit0 - PQ paused. Should be read only access.
+#define QM_REG_PQSTSOTHER_SIZE_BB                                                                            64
+#define QM_REG_PQSTSOTHER_SIZE_K2_E5                                                                         128
+#define QM_REG_SOFT_RESET                                                                                    0x2f2c00UL //Access:RW   DataWidth:0x1    // Initialization bit command.
+#define QM_REG_PQTX2PF_0                                                                                     0x2f2c04UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_1                                                                                     0x2f2c08UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_2                                                                                     0x2f2c0cUL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_3                                                                                     0x2f2c10UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_4                                                                                     0x2f2c14UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_5                                                                                     0x2f2c18UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_6                                                                                     0x2f2c1cUL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_7                                                                                     0x2f2c20UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_8                                                                                     0x2f2c24UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_9                                                                                     0x2f2c28UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_10                                                                                    0x2f2c2cUL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_11                                                                                    0x2f2c30UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_12                                                                                    0x2f2c34UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_13                                                                                    0x2f2c38UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_14                                                                                    0x2f2c3cUL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_15                                                                                    0x2f2c40UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_16                                                                                    0x2f2c44UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_17                                                                                    0x2f2c48UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_18                                                                                    0x2f2c4cUL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_19                                                                                    0x2f2c50UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_20                                                                                    0x2f2c54UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_21                                                                                    0x2f2c58UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_22                                                                                    0x2f2c5cUL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_23                                                                                    0x2f2c60UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_24                                                                                    0x2f2c64UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_25                                                                                    0x2f2c68UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_26                                                                                    0x2f2c6cUL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_27                                                                                    0x2f2c70UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_28                                                                                    0x2f2c74UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_29                                                                                    0x2f2c78UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_30                                                                                    0x2f2c7cUL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_31                                                                                    0x2f2c80UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_32                                                                                    0x2f2c84UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_33                                                                                    0x2f2c88UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_34                                                                                    0x2f2c8cUL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_35                                                                                    0x2f2c90UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_36                                                                                    0x2f2c94UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_37                                                                                    0x2f2c98UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_38                                                                                    0x2f2c9cUL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_39                                                                                    0x2f2ca0UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_40                                                                                    0x2f2ca4UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_41                                                                                    0x2f2ca8UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_42                                                                                    0x2f2cacUL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_43                                                                                    0x2f2cb0UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_44                                                                                    0x2f2cb4UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_45                                                                                    0x2f2cb8UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_46                                                                                    0x2f2cbcUL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_47                                                                                    0x2f2cc0UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_48                                                                                    0x2f2cc4UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_49                                                                                    0x2f2cc8UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_50                                                                                    0x2f2cccUL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_51                                                                                    0x2f2cd0UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_52                                                                                    0x2f2cd4UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_53                                                                                    0x2f2cd8UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_54                                                                                    0x2f2cdcUL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_55                                                                                    0x2f2ce0UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_56_K2_E5                                                                              0x2f2ce4UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_57_K2_E5                                                                              0x2f2ce8UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_58_K2_E5                                                                              0x2f2cecUL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_59_K2_E5                                                                              0x2f2cf0UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_60_K2_E5                                                                              0x2f2cf4UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_61_K2_E5                                                                              0x2f2cf8UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_62_K2_E5                                                                              0x2f2cfcUL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQTX2PF_63_K2_E5                                                                              0x2f2d00UL //Access:RW   DataWidth:0x4    // Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);
+#define QM_REG_PQOTHER2PF_0                                                                                  0x2f2e04UL //Access:RW   DataWidth:0x4    // Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);
+#define QM_REG_PQOTHER2PF_1                                                                                  0x2f2e08UL //Access:RW   DataWidth:0x4    // Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);
+#define QM_REG_PQOTHER2PF_2                                                                                  0x2f2e0cUL //Access:RW   DataWidth:0x4    // Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);
+#define QM_REG_PQOTHER2PF_3                                                                                  0x2f2e10UL //Access:RW   DataWidth:0x4    // Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);
+#define QM_REG_PQOTHER2PF_4                                                                                  0x2f2e14UL //Access:RW   DataWidth:0x4    // Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);
+#define QM_REG_PQOTHER2PF_5                                                                                  0x2f2e18UL //Access:RW   DataWidth:0x4    // Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);
+#define QM_REG_PQOTHER2PF_6                                                                                  0x2f2e1cUL //Access:RW   DataWidth:0x4    // Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);
+#define QM_REG_PQOTHER2PF_7                                                                                  0x2f2e20UL //Access:RW   DataWidth:0x4    // Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);
+#define QM_REG_PQOTHER2PF_8_K2_E5                                                                            0x2f2e24UL //Access:RW   DataWidth:0x4    // Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);
+#define QM_REG_PQOTHER2PF_9_K2_E5                                                                            0x2f2e28UL //Access:RW   DataWidth:0x4    // Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);
+#define QM_REG_PQOTHER2PF_10_K2_E5                                                                           0x2f2e2cUL //Access:RW   DataWidth:0x4    // Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);
+#define QM_REG_PQOTHER2PF_11_K2_E5                                                                           0x2f2e30UL //Access:RW   DataWidth:0x4    // Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);
+#define QM_REG_PQOTHER2PF_12_K2_E5                                                                           0x2f2e34UL //Access:RW   DataWidth:0x4    // Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);
+#define QM_REG_PQOTHER2PF_13_K2_E5                                                                           0x2f2e38UL //Access:RW   DataWidth:0x4    // Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);
+#define QM_REG_PQOTHER2PF_14_K2_E5                                                                           0x2f2e3cUL //Access:RW   DataWidth:0x4    // Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);
+#define QM_REG_PQOTHER2PF_15_K2_E5                                                                           0x2f2e40UL //Access:RW   DataWidth:0x4    // Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);
+#define QM_REG_ARB_TX_EN                                                                                     0x2f2e64UL //Access:RW   DataWidth:0x1    // Enabling the TX PQ arbiter.
+#define QM_REG_ARB_OTHER_EN                                                                                  0x2f2e68UL //Access:RW   DataWidth:0x1    // Enabling the Other PQ arbiter.
+#define QM_REG_PXP_REQ_CRD_INIT                                                                              0x2f2e6cUL //Access:RW   DataWidth:0x2    // Init credit for the pxp request interface.
+#define QM_REG_PXP_REQ_CRD                                                                                   0x2f2e70UL //Access:R    DataWidth:0x2    // Actual credit for the pxp request interface.
+#define QM_REG_DBG_SELECT                                                                                    0x2f2e74UL //Access:RW   DataWidth:0x8    // Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for selecting a line to output to the DBG block.
+#define QM_REG_DBG_DWORD_ENABLE                                                                              0x2f2e78UL //Access:RW   DataWidth:0x4    // Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for enabling dwords in the selected line (after the select before the shift).
+#define QM_REG_DBG_SHIFT                                                                                     0x2f2e7cUL //Access:RW   DataWidth:0x2    // Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for circular right shifting of the selected line (after the enabling).
+#define QM_REG_DBG_FORCE_VALID                                                                               0x2f2e80UL //Access:RW   DataWidth:0x4    // Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - forcing valid.
+#define QM_REG_DBG_FORCE_FRAME                                                                               0x2f2e84UL //Access:RW   DataWidth:0x4    // Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - forcing frame.
+#define QM_REG_DBG_OUT_DATA_LSB                                                                              0x2f2e88UL //Access:R    DataWidth:0x20   // Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 32 lsb data that goes to the DBG block.
+#define QM_REG_DBG_OUT_DATA_MSB                                                                              0x2f2e8cUL //Access:R    DataWidth:0x20   // Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 32 msb data that goes to the DBG block.
+#define QM_REG_DBG_OUT_FRAME                                                                                 0x2f2e90UL //Access:R    DataWidth:0x4    // Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 4 frame bits that goes to the DBG block. Bit0 is the frame of data byte0; Bit1 is the frame of  data byte1; Bit2 is the frame of data byte2; Bit3 is the frame of  data byte4.
+#define QM_REG_DBG_OUT_VALID                                                                                 0x2f2e94UL //Access:R    DataWidth:0x4    // Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 4 valid bits that goes to the DBG block. Bit0 validtes data byte0; Bit1 validates data byte1; Bit2 validates data byte2; Bit3 validates data byte4.
+#define QM_REG_ECO_RESERVED                                                                                  0x2f2e98UL //Access:RW   DataWidth:0x8    // Eco reserved register.
+#define QM_REG_TXPQMAP_MASKACCESS                                                                            0x2f2e9cUL //Access:RW   DataWidth:0x1    // Selects between the Mem Array (0) and the Mask Array (1) when accessing the TxPqMap CAM.
+#define QM_REG_PCI_RD_ERR                                                                                    0x2f2ea0UL //Access:RW   DataWidth:0x1    // PCI rd error indication. The QM sets this reg upon PXP rdata with error. The driver can clear this bit (through RBC) based on the functional flows (e.g. FLR). It is also possible to set this bit by the RBC but this is used for debug.
+#define QM_REG_PF_EN                                                                                         0x2f2ea4UL //Access:RW   DataWidth:0x1    // PF enable vector. Bit per PF. If set the PF is enabled.
+#define QM_REG_VF_EN                                                                                         0x2f2ea8UL //Access:RW   DataWidth:0x1    // VF enable vector. Bit per VF. If set the VF is enabled.
+#define QM_REG_USG_CNT_PF_TX                                                                                 0x2f2eacUL //Access:RW   DataWidth:0x18   // PF Usage counters for TX tasks.
+#define QM_REG_USG_CNT_PF_OTHER                                                                              0x2f2eb0UL //Access:RW   DataWidth:0x18   // PF Usage counters for Other tasks.
+#define QM_REG_USG_CNT_VF_TX                                                                                 0x2f2eb4UL //Access:RW   DataWidth:0x18   // VF Usage counters for TX tasks.
+#define QM_REG_USG_CNT_VF_OTHER                                                                              0x2f2eb8UL //Access:RW   DataWidth:0x18   // VF Usage counters for Other tasks.
+#define QM_REG_XSDM_FIFO_FULL_THR                                                                            0x2f2ebcUL //Access:RW   DataWidth:0x4    // almost full threshold for the xsdm fifo. the value refer fifo size of 8. if the fifo size is different (for different flow control resources) then the rtl should use this value and compensate for the difference.
+#define QM_REG_YSDM_FIFO_FULL_THR                                                                            0x2f2ec0UL //Access:RW   DataWidth:0x4    // almost full threshold for the ysdm fifo. the value refer fifo size of 8. if the fifo size is different (for different flow control resources) then the rtl should use this value and compensate for the difference.
+#define QM_REG_PSDM_FIFO_FULL_THR                                                                            0x2f2ec4UL //Access:RW   DataWidth:0x4    // almost full threshold for the psdm fifo. the value refer fifo size of 8. if the fifo size is different (for different flow control resources) then the rtl should use this value and compensate for the difference.
+#define QM_REG_RLGLBLPERIOD_0                                                                                0x2f2ec8UL //Access:RW   DataWidth:0x20   // The RL timeout period in 25Mhz clock cycles for the global. VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. 1 - Global VP/QCN RL Timeout1. NOTE: ck25 domain. sync should be implemented.
+#define QM_REG_RLGLBLPERIOD_1                                                                                0x2f2eccUL //Access:RW   DataWidth:0x20   // The RL timeout period in 25Mhz clock cycles for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. 1 - Global VP/QCN RL Timeout1. NOTE: ck25 domain. sync should be implemented.
+#define QM_REG_RLGLBLPERIODTIMER_0                                                                           0x2f2ed0UL //Access:RW   DataWidth:0x20   // The RL timeout period counter in 25Mhz clock cycles for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. Upon init should be set with value of RlGlblPeriod_0 by the GRC. 1 - Global VP/QCN RL Timeout1. NOTE: ck25 domain. sync should be implemented.
+#define QM_REG_RLGLBLPERIODTIMER_1                                                                           0x2f2ed4UL //Access:RW   DataWidth:0x20   // The RL timeout period counter in 25Mhz clock cycles for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. 1 - Global VP/QCN RL Timeout1. Upon init should be set with value of RlGlblPeriod_1 by the GRC. NOTE: ck25 domain. sync should be implemented.
+#define QM_REG_RLGLBLPERIODSEL_0                                                                             0x2f2ed8UL //Access:RW   DataWidth:0x20   // The RL timeout period that should be selected for the global VP/QCN RL counter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 - RL-s 63:32; ... 7 - RL-s 255:224
+#define QM_REG_RLGLBLPERIODSEL_1                                                                             0x2f2edcUL //Access:RW   DataWidth:0x20   // The RL timeout period that should be selected for the global VP/QCN RL counter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 - RL-s 63:32; ... 7 - RL-s 255:224
+#define QM_REG_RLGLBLPERIODSEL_2                                                                             0x2f2ee0UL //Access:RW   DataWidth:0x20   // The RL timeout period that should be selected for the global VP/QCN RL counter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 - RL-s 63:32; ... 7 - RL-s 255:224
+#define QM_REG_RLGLBLPERIODSEL_3                                                                             0x2f2ee4UL //Access:RW   DataWidth:0x20   // The RL timeout period that should be selected for the global VP/QCN RL counter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 - RL-s 63:32; ... 7 - RL-s 255:224
+#define QM_REG_RLGLBLPERIODSEL_4                                                                             0x2f2ee8UL //Access:RW   DataWidth:0x20   // The RL timeout period that should be selected for the global VP/QCN RL counter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 - RL-s 63:32; ... 7 - RL-s 255:224
+#define QM_REG_RLGLBLPERIODSEL_5                                                                             0x2f2eecUL //Access:RW   DataWidth:0x20   // The RL timeout period that should be selected for the global VP/QCN RL counter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 - RL-s 63:32; ... 7 - RL-s 255:224
+#define QM_REG_RLGLBLPERIODSEL_6                                                                             0x2f2ef0UL //Access:RW   DataWidth:0x20   // The RL timeout period that should be selected for the global VP/QCN RL counter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 - RL-s 63:32; ... 7 - RL-s 255:224
+#define QM_REG_RLGLBLPERIODSEL_7                                                                             0x2f2ef4UL //Access:RW   DataWidth:0x20   // The RL timeout period that should be selected for the global VP/QCN RL counter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 - RL-s 63:32; ... 7 - RL-s 255:224
+#define QM_REG_RLGLBLINCVAL                                                                                  0x2f3400UL //Access:RW   DataWidth:0x1f   // The RL increment value for the global VP/QCN RL counters.
+#define QM_REG_RLGLBLINCVAL_SIZE                                                                             256
+#define QM_REG_RLGLBLUPPERBOUND                                                                              0x2f3c00UL //Access:RW   DataWidth:0x20   // The RL upper bound for the global VP/QCN RL counters. Sign: the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bits (msb-1) to 0 are in 2s complement representation
+#define QM_REG_RLGLBLUPPERBOUND_SIZE                                                                         256
+#define QM_REG_RLGLBLCRD                                                                                     0x2f4400UL //Access:RW   DataWidth:0x20   // The actual RL credit for the global VP/QCN RL counters. Should be read only access in non-init mode. In init mode should be written with the same value of RlGlblUpperBound. Sign: the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bits (msb-1) to 0 are in 2s complement representation
+#define QM_REG_RLGLBLCRD_SIZE                                                                                256
+#define QM_REG_RLGLBLENABLE                                                                                  0x2f4c00UL //Access:RW   DataWidth:0x1    // Enabling the global VP/QCN RL mechanism.
+#define QM_REG_RLGLBL_CNT_NUM                                                                                0x2f4c04UL //Access:RW   DataWidth:0x9    // number of active RL counters (between 1 to QM_NUM_OF_RL)
+#define QM_REG_RLGLBLCRD_FORCE_STS_UPDATE                                                                    0x2f4c08UL //Access:RW   DataWidth:0x1    // when 1 - force cam search and update sts_rlglbl_pq_blocked vector even when the rlglblcrd did not change from XON->XOFF or XOFF->XON NOTE: this is valid only for rf_qm_ind_rlglblcrd* command (i.e. access the global RL through the RBC)
+#define QM_REG_ERR_INC0_RLGLBLCRD                                                                            0x2f4c0cUL //Access:RC   DataWidth:0x10   // Increment error type0 for the global RL (inc above max allowed value (i.e. overflow the RL credit counter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: client id (b12 - xsdm; b13 - ysdm; b14 - psdm; b15 - periodic timer);
+#define QM_REG_ERR_DEC0_RLGLBLCRD                                                                            0x2f4c10UL //Access:RC   DataWidth:0x10   // Decrement error type0 for the global RL (dec below the most neg value (i.e. underflow the RL credit counter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: client id (b12 - xsdm; b13 - ysdm; b14 - psdm; b15 - tx_arb);
+#define QM_REG_ERR_DEC1_RLGLBLCRD                                                                            0x2f4c14UL //Access:RC   DataWidth:0x10   // Decrement error type1 for the global RL (dec when the credit counter is already below zero). b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: client id (b12 - xsdm; b13 - ysdm; b14 - psdm; b15 - tx_arb);
+#define QM_REG_ERR_MASK_RLGLBLCRD                                                                            0x2f4c18UL //Access:RW   DataWidth:0x4    // per error type bit mask vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_RlGlblCrd; b1 - reserved. b2 - Err_Dec0_RlGlblCrd; b3 - Err_Dec1_RlGlblCrd;
+#define QM_REG_RLPFPERIOD                                                                                    0x2f4c1cUL //Access:RW   DataWidth:0x20   // The RL timeout period in 25Mhz clock cycles for the PF RL-s. NOTE: ck25 domain. sync should be implemented.
+#define QM_REG_RLPFPERIODTIMER                                                                               0x2f4c20UL //Access:RW   DataWidth:0x20   // The RL timeout period counter in 25Mhz clock cycles for the PF RL-s. Upon init should be set with value of RlPfPeriod by the GRC. NOTE: ck25 domain. sync should be implemented.
+#define QM_REG_RLPFINCVAL                                                                                    0x2f4c80UL //Access:RW   DataWidth:0x1f   // The RL increment value for the PF RL counters.
+#define QM_REG_RLPFINCVAL_SIZE_BB                                                                            8
+#define QM_REG_RLPFINCVAL_SIZE_K2_E5                                                                         16
+#define QM_REG_RLPFUPPERBOUND                                                                                0x2f4d00UL //Access:RW   DataWidth:0x20   // The RL upper bound for the PF RL counters. Sign: the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bits (msb-1) to 0 are in 2s complement representation
+#define QM_REG_RLPFUPPERBOUND_SIZE_BB                                                                        8
+#define QM_REG_RLPFUPPERBOUND_SIZE_K2_E5                                                                     16
+#define QM_REG_RLPFCRD                                                                                       0x2f4d80UL //Access:RW   DataWidth:0x20   // The actual RL credit for the PF RL counters. Should be read only access in non-init mode. In init mode should be written with the same value of RlPfUpperBound. Sign: the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bits (msb-1) to 0 are in 2s complement representation
+#define QM_REG_RLPFCRD_SIZE_BB                                                                               8
+#define QM_REG_RLPFCRD_SIZE_K2_E5                                                                            16
+#define QM_REG_RLPFENABLE                                                                                    0x2f4e00UL //Access:RW   DataWidth:0x1    // Enabling the PF RL mechanism.
+#define QM_REG_RLPFVOQENABLE                                                                                 0x2f4e04UL //Access:RW   DataWidth:0x20   // Enabling the PF RL mechanism per VOQ. RlPfVoqEnable (This one) - VOQs [0..31]. RlPfVoqEnable_msb        - VOQs [32..35]. Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [8..31] are "not used". port_mode == 1 (2 port device) : VOQs [16..31] are "not used". port_mode == 2 (4 port device) : VOQs [6,7,14,15,22,23,30,31] are "not used"
+#define QM_REG_ERR_INC0_RLPFCRD                                                                              0x2f4e08UL //Access:RC   DataWidth:0xc    // Increment error type0 for the PF RL (inc above max allowed value (i.e. overflow the RL credit counter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: client id (b8 - xsdm; b9 - ysdm; b10 - psdm; b11 - periodic timer);
+#define QM_REG_ERR_DEC0_RLPFCRD                                                                              0x2f4e0cUL //Access:RC   DataWidth:0xc    // Decrement error type0 for the PF RL (dec below the most neg value (i.e. underflow the RL credit counter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: client id (b8 - xsdm; b9 - ysdm; b10 - psdm; b11 - tx_arb);
+#define QM_REG_ERR_DEC1_RLPFCRD                                                                              0x2f4e10UL //Access:RC   DataWidth:0xc    // Decrement error type1 for the PF RL (dec when the credit counter is already below zero). b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: client id (b8 - xsdm; b9 - ysdm; b10 - psdm; b11 - tx_arb);
+#define QM_REG_ERR_MASK_RLPFCRD                                                                              0x2f4e14UL //Access:RW   DataWidth:0x4    // per error type bit mask vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_RlPfCrd; b1 - reserved. b2 - Err_Dec0_RlPfCrd; b3 - Err_Dec1_RlPfCrd;
+#define QM_REG_WFQPFWEIGHT                                                                                   0x2f4e80UL //Access:RW   DataWidth:0x1f   // The WFQ weight (increment value) for the PF WFQ counters.
+#define QM_REG_WFQPFWEIGHT_SIZE_BB                                                                           8
+#define QM_REG_WFQPFWEIGHT_SIZE_K2_E5                                                                        16
+#define QM_REG_WFQPFUPPERBOUND                                                                               0x2f4f00UL //Access:RW   DataWidth:0x20   // The WFQ upper bound for the PF WFQ counters. Sign: the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bits (msb-1) to 0 are in 2s complement representation
+#define QM_REG_WFQPFUPPERBOUND_SIZE_BB                                                                       8
+#define QM_REG_WFQPFUPPERBOUND_SIZE_K2_E5                                                                    16
+#define QM_REG_WFQPFCRD                                                                                      0x2f5400UL //Access:RW   DataWidth:0x20   // The actual WFQ credit for the PF WFQ counters. WfqPfCrd (This one) - VOQ0..VOQ15. WfqPfCrd_msb - VOQ16..VOQ35. Should be read only access in non-init mode. In init mode should be written with the same value of WfqPfUpperBound. Sign: the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bits (msb-1) to 0 are in 2s complement representation. Mapping: Counters 0-15 are associated with PFs 0..15 of VOQ0. ... Counters 240-255 are associated with PFs 0..15 of VOQ15. Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device ) : VOQs [8..15] are "not used" port_mode == 2 (4 port device ) : VOQs [6,7,14,15] are "not used" NOTE : WR/RD to a "not used" address will not return an ack!!!
+#define QM_REG_WFQPFCRD_SIZE_BB                                                                              144
+#define QM_REG_WFQPFCRD_SIZE_K2                                                                              160
+#define QM_REG_WFQPFCRD_SIZE_E5                                                                              256
+#define QM_REG_WFQPFENABLE                                                                                   0x2f5c00UL //Access:RW   DataWidth:0x1    // Enabling the PF WFQ mechanism.
+#define QM_REG_ERR_INC0_WFQPFCRD                                                                             0x2f5c04UL //Access:RC   DataWidth:0x10   // Increment error type0 for the PF WFQ (inc above max allowed value (i.e. overflow the WFQ credit counter)) b0 - error valid; b1: reserved (should be filled with zeroes); b5-b2: pf id; b11-b6: voq id;  b15-b12: client id (b12 - xsdm; b13 - ysdm; b14 - psdm; b15 - periodic timer);
+#define QM_REG_ERR_DEC0_WFQPFCRD                                                                             0x2f5c08UL //Access:RC   DataWidth:0x10   // Decrement error type0 for the PF WFQ (dec below the most neg value (i.e. underflow the WFQ credit counter)) b0 - error valid; b1: reserved (should be filled with zeroes); b5-b2: pf id; b11-b6: voq id;  b15-b12: client id (b12 - xsdm; b13 - ysdm; b14 - psdm; b15 - tx_arb);
+#define QM_REG_ERR_DEC1_WFQPFCRD                                                                             0x2f5c0cUL //Access:RC   DataWidth:0x11   // Decrement error type1 for the PF WFQ (dec when the credit counter is already below zero). b0 - error valid; b1: reserved (should be filled with zeroes); b5-b2: pf id; b11-b6: voq id;  b15-b12: client id (b12 - xsdm; b13 - ysdm; b14 - psdm; b15 - tx_arb);
+#define QM_REG_ERR_MASK_WFQPFCRD                                                                             0x2f5c10UL //Access:RW   DataWidth:0x4    // per error type bit mask vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_WfqPfCrd; b1 - reserved. b2 - Err_Dec0_WfqPfCrd; b3 - Err_Dec1_WfqPfCrd;
+#define QM_REG_WFQVPENABLE                                                                                   0x2f5c14UL //Access:RW   DataWidth:0x1    // Enabling the VP WFQ mechanism.
+#define QM_REG_WFQVPCRD_FORCE_STS_UPDATE                                                                     0x2f5c18UL //Access:RW   DataWidth:0x1    // when 1 - force cam search and update sts_wfqvp_pq_blocked vector even when the wfqvpcrd did not change from XON->XOFF or XOFF->XON NOTE: this is valid only for rf_qm_ind_wfqvpcrd* command (i.e. access the global RL through the RBC)
+#define QM_REG_ERR_INC0_WFQVPCRD                                                                             0x2f5c1cUL //Access:RC   DataWidth:0x14   // Increment error type0 for the VP WFQ (inc above max allowed value (i.e. overflow the WFQ credit counter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (should be filled with zeroes); b19-b16: client id (b16 - xsdm; b17 - ysdm; b18 - psdm; b19 - periodic timer);
+#define QM_REG_ERR_DEC0_WFQVPCRD                                                                             0x2f5c20UL //Access:RC   DataWidth:0x14   // Decrement error type0 for the VP WFQ (dec below the most neg value (i.e. underflow the WFQ credit counter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (should be filled with zeroes); b19-b16: client id (b16 - xsdm; b17 - ysdm; b18 - psdm; b19 - tx_arb);
+#define QM_REG_ERR_DEC1_WFQVPCRD                                                                             0x2f5c24UL //Access:RC   DataWidth:0x14   // Decrement error type1 for the VP WFQ (dec when the credit counter is already below zero). b0 - error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (should be filled with zeroes); b19-b16: client id (b16 - xsdm; b17 - ysdm; b18 - psdm; b19 - tx_arb);
+#define QM_REG_ERR_MASK_WFQVPCRD                                                                             0x2f5c28UL //Access:RW   DataWidth:0x4    // per error type bit mask vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_WfqVpCrd; b1 - reserved. b2 - Err_Dec0_WfqVpCrd; b3 - Err_Dec1_WfqVpCrd;
+#define QM_REG_VOQ_ARB_GRP0_WEIGHT_0                                                                         0x2f5c2cUL //Access:RW   DataWidth:0x3    // VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; The values are TC numbers (to reflect the priority within a port). The weights are allocated to port according to the port_mode: port_mode == 0 (1 port device) : [grp0_weight_0..grp0_weight_7] are port 0. port_mode == 1 (2 port device) : [grp0_weight_0..grp0_weight_7] are port 0, [grp1_weight_0..grp1_weight_7] are port 1. port_mode == 2 (4 port device) : [grp0_weight_0..grp0_weight_5] are port 0, [grp0_weight_6..grp0_weight_7,grp1_weight_0..grp1_weight_3] are port 1, [grp1_weight_4..grp1_weight_7,grp2_weight_0..grp2_weight_1] are port 2, [grp2_weight_2..grp2_weight_7] are port 3. For port_mode in [0,1] the valid TC numbers are 0..7, for port_mode == 2 the valid TC numbers are 0..5. The values of TC per port should be unique.
+#define QM_REG_VOQ_ARB_GRP0_WEIGHT_1                                                                         0x2f5c30UL //Access:RW   DataWidth:0x3    // VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; The values are TC numbers (to reflect the priority within a port). The weights are allocated to port according to the port_mode: port_mode == 0 (1 port device) : [grp0_weight_0..grp0_weight_7] are port 0. port_mode == 1 (2 port device) : [grp0_weight_0..grp0_weight_7] are port 0, [grp1_weight_0..grp1_weight_7] are port 1. port_mode == 2 (4 port device) : [grp0_weight_0..grp0_weight_5] are port 0, [grp0_weight_6..grp0_weight_7,grp1_weight_0..grp1_weight_3] are port 1, [grp1_weight_4..grp1_weight_7,grp2_weight_0..grp2_weight_1] are port 2, [grp2_weight_2..grp2_weight_7] are port 3. For port_mode in [0,1] the valid TC numbers are 0..7, for port_mode == 2 the valid TC numbers are 0..5. The values of TC per port should be unique.
+#define QM_REG_VOQ_ARB_GRP0_WEIGHT_2                                                                         0x2f5c34UL //Access:RW   DataWidth:0x3    // VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; The values are TC numbers (to reflect the priority within a port). The weights are allocated to port according to the port_mode: port_mode == 0 (1 port device) : [grp0_weight_0..grp0_weight_7] are port 0. port_mode == 1 (2 port device) : [grp0_weight_0..grp0_weight_7] are port 0, [grp1_weight_0..grp1_weight_7] are port 1. port_mode == 2 (4 port device) : [grp0_weight_0..grp0_weight_5] are port 0, [grp0_weight_6..grp0_weight_7,grp1_weight_0..grp1_weight_3] are port 1, [grp1_weight_4..grp1_weight_7,grp2_weight_0..grp2_weight_1] are port 2, [grp2_weight_2..grp2_weight_7] are port 3. For port_mode in [0,1] the valid TC numbers are 0..7, for port_mode == 2 the valid TC numbers are 0..5. The values of TC per port should be unique.
+#define QM_REG_VOQ_ARB_GRP0_WEIGHT_3                                                                         0x2f5c38UL //Access:RW   DataWidth:0x3    // VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; The values are TC numbers (to reflect the priority within a port). The weights are allocated to port according to the port_mode: port_mode == 0 (1 port device) : [grp0_weight_0..grp0_weight_7] are port 0. port_mode == 1 (2 port device) : [grp0_weight_0..grp0_weight_7] are port 0, [grp1_weight_0..grp1_weight_7] are port 1. port_mode == 2 (4 port device) : [grp0_weight_0..grp0_weight_5] are port 0, [grp0_weight_6..grp0_weight_7,grp1_weight_0..grp1_weight_3] are port 1, [grp1_weight_4..grp1_weight_7,grp2_weight_0..grp2_weight_1] are port 2, [grp2_weight_2..grp2_weight_7] are port 3. For port_mode in [0,1] the valid TC numbers are 0..7, for port_mode == 2 the valid TC numbers are 0..5. The values of TC per port should be unique.
+#define QM_REG_VOQ_ARB_GRP0_WEIGHT_4                                                                         0x2f5c3cUL //Access:RW   DataWidth:0x3    // VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; The values are TC numbers (to reflect the priority within a port). The weights are allocated to port according to the port_mode: port_mode == 0 (1 port device) : [grp0_weight_0..grp0_weight_7] are port 0. port_mode == 1 (2 port device) : [grp0_weight_0..grp0_weight_7] are port 0, [grp1_weight_0..grp1_weight_7] are port 1. port_mode == 2 (4 port device) : [grp0_weight_0..grp0_weight_5] are port 0, [grp0_weight_6..grp0_weight_7,grp1_weight_0..grp1_weight_3] are port 1, [grp1_weight_4..grp1_weight_7,grp2_weight_0..grp2_weight_1] are port 2, [grp2_weight_2..grp2_weight_7] are port 3. For port_mode in [0,1] the valid TC numbers are 0..7, for port_mode == 2 the valid TC numbers are 0..5. The values of TC per port should be unique.
+#define QM_REG_VOQ_ARB_GRP0_WEIGHT_5                                                                         0x2f5c40UL //Access:RW   DataWidth:0x3    // VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; The values are TC numbers (to reflect the priority within a port). The weights are allocated to port according to the port_mode: port_mode == 0 (1 port device) : [grp0_weight_0..grp0_weight_7] are port 0. port_mode == 1 (2 port device) : [grp0_weight_0..grp0_weight_7] are port 0, [grp1_weight_0..grp1_weight_7] are port 1. port_mode == 2 (4 port device) : [grp0_weight_0..grp0_weight_5] are port 0, [grp0_weight_6..grp0_weight_7,grp1_weight_0..grp1_weight_3] are port 1, [grp1_weight_4..grp1_weight_7,grp2_weight_0..grp2_weight_1] are port 2, [grp2_weight_2..grp2_weight_7] are port 3. For port_mode in [0,1] the valid TC numbers are 0..7, for port_mode == 2 the valid TC numbers are 0..5. The values of TC per port should be unique.
+#define QM_REG_VOQ_ARB_GRP0_WEIGHT_6                                                                         0x2f5c44UL //Access:RW   DataWidth:0x3    // VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; The values are TC numbers (to reflect the priority within a port). The weights are allocated to port according to the port_mode: port_mode == 0 (1 port device) : [grp0_weight_0..grp0_weight_7] are port 0. port_mode == 1 (2 port device) : [grp0_weight_0..grp0_weight_7] are port 0, [grp1_weight_0..grp1_weight_7] are port 1. port_mode == 2 (4 port device) : [grp0_weight_0..grp0_weight_5] are port 0, [grp0_weight_6..grp0_weight_7,grp1_weight_0..grp1_weight_3] are port 1, [grp1_weight_4..grp1_weight_7,grp2_weight_0..grp2_weight_1] are port 2, [grp2_weight_2..grp2_weight_7] are port 3. For port_mode in [0,1] the valid TC numbers are 0..7, for port_mode == 2 the valid TC numbers are 0..5. The values of TC per port should be unique.
+#define QM_REG_VOQ_ARB_GRP0_WEIGHT_7                                                                         0x2f5c48UL //Access:RW   DataWidth:0x3    // VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; The values are TC numbers (to reflect the priority within a port). The weights are allocated to port according to the port_mode: port_mode == 0 (1 port device) : [grp0_weight_0..grp0_weight_7] are port 0. port_mode == 1 (2 port device) : [grp0_weight_0..grp0_weight_7] are port 0, [grp1_weight_0..grp1_weight_7] are port 1. port_mode == 2 (4 port device) : [grp0_weight_0..grp0_weight_5] are port 0, [grp0_weight_6..grp0_weight_7,grp1_weight_0..grp1_weight_3] are port 1, [grp1_weight_4..grp1_weight_7,grp2_weight_0..grp2_weight_1] are port 2, [grp2_weight_2..grp2_weight_7] are port 3. For port_mode in [0,1] the valid TC numbers are 0..7, for port_mode == 2 the valid TC numbers are 0..5. The values of TC per port should be unique.
+#define QM_REG_VOQ_ARB_GRP1_WEIGHT_0                                                                         0x2f5cacUL //Access:RW   DataWidth:0x3    // VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; The values are TC numbers (to reflect the priority within a port). The weights are allocated to port according to the port_mode: port_mode == 0 (1 port device) : [grp0_weight_0..grp0_weight_7] are port 0. port_mode == 1 (2 port device) : [grp0_weight_0..grp0_weight_7] are port 0, [grp1_weight_0..grp1_weight_7] are port 1. port_mode == 2 (4 port device) : [grp0_weight_0..grp0_weight_5] are port 0, [grp0_weight_6..grp0_weight_7,grp1_weight_0..grp1_weight_3] are port 1, [grp1_weight_4..grp1_weight_7,grp2_weight_0..grp2_weight_1] are port 2, [grp2_weight_2..grp2_weight_7] are port 3. For port_mode in [0,1] the valid TC numbers are 0..7, for port_mode == 2 the valid TC numbers are 0..5. The values of TC per port should be unique.
+#define QM_REG_VOQ_ARB_GRP1_WEIGHT_1                                                                         0x2f5cb0UL //Access:RW   DataWidth:0x3    // VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; The values are TC numbers (to reflect the priority within a port). The weights are allocated to port according to the port_mode: port_mode == 0 (1 port device) : [grp0_weight_0..grp0_weight_7] are port 0. port_mode == 1 (2 port device) : [grp0_weight_0..grp0_weight_7] are port 0, [grp1_weight_0..grp1_weight_7] are port 1. port_mode == 2 (4 port device) : [grp0_weight_0..grp0_weight_5] are port 0, [grp0_weight_6..grp0_weight_7,grp1_weight_0..grp1_weight_3] are port 1, [grp1_weight_4..grp1_weight_7,grp2_weight_0..grp2_weight_1] are port 2, [grp2_weight_2..grp2_weight_7] are port 3. For port_mode in [0,1] the valid TC numbers are 0..7, for port_mode == 2 the valid TC numbers are 0..5. The values of TC per port should be unique.
+#define QM_REG_VOQ_ARB_GRP1_WEIGHT_2                                                                         0x2f5cb4UL //Access:RW   DataWidth:0x3    // VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; The values are TC numbers (to reflect the priority within a port). The weights are allocated to port according to the port_mode: port_mode == 0 (1 port device) : [grp0_weight_0..grp0_weight_7] are port 0. port_mode == 1 (2 port device) : [grp0_weight_0..grp0_weight_7] are port 0, [grp1_weight_0..grp1_weight_7] are port 1. port_mode == 2 (4 port device) : [grp0_weight_0..grp0_weight_5] are port 0, [grp0_weight_6..grp0_weight_7,grp1_weight_0..grp1_weight_3] are port 1, [grp1_weight_4..grp1_weight_7,grp2_weight_0..grp2_weight_1] are port 2, [grp2_weight_2..grp2_weight_7] are port 3. For port_mode in [0,1] the valid TC numbers are 0..7, for port_mode == 2 the valid TC numbers are 0..5. The values of TC per port should be unique.
+#define QM_REG_VOQ_ARB_GRP1_WEIGHT_3                                                                         0x2f5cb8UL //Access:RW   DataWidth:0x3    // VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; The values are TC numbers (to reflect the priority within a port). The weights are allocated to port according to the port_mode: port_mode == 0 (1 port device) : [grp0_weight_0..grp0_weight_7] are port 0. port_mode == 1 (2 port device) : [grp0_weight_0..grp0_weight_7] are port 0, [grp1_weight_0..grp1_weight_7] are port 1. port_mode == 2 (4 port device) : [grp0_weight_0..grp0_weight_5] are port 0, [grp0_weight_6..grp0_weight_7,grp1_weight_0..grp1_weight_3] are port 1, [grp1_weight_4..grp1_weight_7,grp2_weight_0..grp2_weight_1] are port 2, [grp2_weight_2..grp2_weight_7] are port 3. For port_mode in [0,1] the valid TC numbers are 0..7, for port_mode == 2 the valid TC numbers are 0..5. The values of TC per port should be unique.
+#define QM_REG_VOQ_ARB_GRP1_WEIGHT_4                                                                         0x2f5cbcUL //Access:RW   DataWidth:0x3    // VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; The values are TC numbers (to reflect the priority within a port). The weights are allocated to port according to the port_mode: port_mode == 0 (1 port device) : [grp0_weight_0..grp0_weight_7] are port 0. port_mode == 1 (2 port device) : [grp0_weight_0..grp0_weight_7] are port 0, [grp1_weight_0..grp1_weight_7] are port 1. port_mode == 2 (4 port device) : [grp0_weight_0..grp0_weight_5] are port 0, [grp0_weight_6..grp0_weight_7,grp1_weight_0..grp1_weight_3] are port 1, [grp1_weight_4..grp1_weight_7,grp2_weight_0..grp2_weight_1] are port 2, [grp2_weight_2..grp2_weight_7] are port 3. For port_mode in [0,1] the valid TC numbers are 0..7, for port_mode == 2 the valid TC numbers are 0..5. The values of TC per port should be unique.
+#define QM_REG_VOQ_ARB_GRP1_WEIGHT_5                                                                         0x2f5cc0UL //Access:RW   DataWidth:0x3    // VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; The values are TC numbers (to reflect the priority within a port). The weights are allocated to port according to the port_mode: port_mode == 0 (1 port device) : [grp0_weight_0..grp0_weight_7] are port 0. port_mode == 1 (2 port device) : [grp0_weight_0..grp0_weight_7] are port 0, [grp1_weight_0..grp1_weight_7] are port 1. port_mode == 2 (4 port device) : [grp0_weight_0..grp0_weight_5] are port 0, [grp0_weight_6..grp0_weight_7,grp1_weight_0..grp1_weight_3] are port 1, [grp1_weight_4..grp1_weight_7,grp2_weight_0..grp2_weight_1] are port 2, [grp2_weight_2..grp2_weight_7] are port 3. For port_mode in [0,1] the valid TC numbers are 0..7, for port_mode == 2 the valid TC numbers are 0..5. The values of TC per port should be unique.
+#define QM_REG_VOQ_ARB_GRP1_WEIGHT_6                                                                         0x2f5cc4UL //Access:RW   DataWidth:0x3    // VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; The values are TC numbers (to reflect the priority within a port). The weights are allocated to port according to the port_mode: port_mode == 0 (1 port device) : [grp0_weight_0..grp0_weight_7] are port 0. port_mode == 1 (2 port device) : [grp0_weight_0..grp0_weight_7] are port 0, [grp1_weight_0..grp1_weight_7] are port 1. port_mode == 2 (4 port device) : [grp0_weight_0..grp0_weight_5] are port 0, [grp0_weight_6..grp0_weight_7,grp1_weight_0..grp1_weight_3] are port 1, [grp1_weight_4..grp1_weight_7,grp2_weight_0..grp2_weight_1] are port 2, [grp2_weight_2..grp2_weight_7] are port 3. For port_mode in [0,1] the valid TC numbers are 0..7, for port_mode == 2 the valid TC numbers are 0..5. The values of TC per port should be unique.
+#define QM_REG_VOQ_ARB_GRP1_WEIGHT_7                                                                         0x2f5cc8UL //Access:RW   DataWidth:0x3    // VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; The values are TC numbers (to reflect the priority within a port). The weights are allocated to port according to the port_mode: port_mode == 0 (1 port device) : [grp0_weight_0..grp0_weight_7] are port 0. port_mode == 1 (2 port device) : [grp0_weight_0..grp0_weight_7] are port 0, [grp1_weight_0..grp1_weight_7] are port 1. port_mode == 2 (4 port device) : [grp0_weight_0..grp0_weight_5] are port 0, [grp0_weight_6..grp0_weight_7,grp1_weight_0..grp1_weight_3] are port 1, [grp1_weight_4..grp1_weight_7,grp2_weight_0..grp2_weight_1] are port 2, [grp2_weight_2..grp2_weight_7] are port 3. For port_mode in [0,1] the valid TC numbers are 0..7, for port_mode == 2 the valid TC numbers are 0..5. The values of TC per port should be unique.
+#define QM_REG_VOQ_ARB_GRP2_WEIGHT_0_E5                                                                      0x2f5cccUL //Access:RW   DataWidth:0x3    // VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; The values are TC numbers (to reflect the priority within a port). The weights are allocated to port according to the port_mode: port_mode == 0 (1 port device) : [grp0_weight_0..grp0_weight_7] are port 0. port_mode == 1 (2 port device) : [grp0_weight_0..grp0_weight_7] are port 0, [grp1_weight_0..grp1_weight_7] are port 1. port_mode == 2 (4 port device) : [grp0_weight_0..grp0_weight_5] are port 0, [grp0_weight_6..grp0_weight_7,grp1_weight_0..grp1_weight_3] are port 1, [grp1_weight_4..grp1_weight_7,grp2_weight_0..grp2_weight_1] are port 2, [grp2_weight_2..grp2_weight_7] are port 3. For port_mode in [0,1] the valid TC numbers are 0..7, for port_mode == 2 the valid TC numbers are 0..5. The values of TC per port should be unique.
+#define QM_REG_VOQ_ARB_GRP2_WEIGHT_1_E5                                                                      0x2f5cd0UL //Access:RW   DataWidth:0x3    // VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; The values are TC numbers (to reflect the priority within a port). The weights are allocated to port according to the port_mode: port_mode == 0 (1 port device) : [grp0_weight_0..grp0_weight_7] are port 0. port_mode == 1 (2 port device) : [grp0_weight_0..grp0_weight_7] are port 0, [grp1_weight_0..grp1_weight_7] are port 1. port_mode == 2 (4 port device) : [grp0_weight_0..grp0_weight_5] are port 0, [grp0_weight_6..grp0_weight_7,grp1_weight_0..grp1_weight_3] are port 1, [grp1_weight_4..grp1_weight_7,grp2_weight_0..grp2_weight_1] are port 2, [grp2_weight_2..grp2_weight_7] are port 3. For port_mode in [0,1] the valid TC numbers are 0..7, for port_mode == 2 the valid TC numbers are 0..5. The values of TC per port should be unique.
+#define QM_REG_VOQ_ARB_GRP2_WEIGHT_2_E5                                                                      0x2f5cd4UL //Access:RW   DataWidth:0x3    // VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; The values are TC numbers (to reflect the priority within a port). The weights are allocated to port according to the port_mode: port_mode == 0 (1 port device) : [grp0_weight_0..grp0_weight_7] are port 0. port_mode == 1 (2 port device) : [grp0_weight_0..grp0_weight_7] are port 0, [grp1_weight_0..grp1_weight_7] are port 1. port_mode == 2 (4 port device) : [grp0_weight_0..grp0_weight_5] are port 0, [grp0_weight_6..grp0_weight_7,grp1_weight_0..grp1_weight_3] are port 1, [grp1_weight_4..grp1_weight_7,grp2_weight_0..grp2_weight_1] are port 2, [grp2_weight_2..grp2_weight_7] are port 3. For port_mode in [0,1] the valid TC numbers are 0..7, for port_mode == 2 the valid TC numbers are 0..5. The values of TC per port should be unique.
+#define QM_REG_VOQ_ARB_GRP2_WEIGHT_3_E5                                                                      0x2f5cd8UL //Access:RW   DataWidth:0x3    // VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; The values are TC numbers (to reflect the priority within a port). The weights are allocated to port according to the port_mode: port_mode == 0 (1 port device) : [grp0_weight_0..grp0_weight_7] are port 0. port_mode == 1 (2 port device) : [grp0_weight_0..grp0_weight_7] are port 0, [grp1_weight_0..grp1_weight_7] are port 1. port_mode == 2 (4 port device) : [grp0_weight_0..grp0_weight_5] are port 0, [grp0_weight_6..grp0_weight_7,grp1_weight_0..grp1_weight_3] are port 1, [grp1_weight_4..grp1_weight_7,grp2_weight_0..grp2_weight_1] are port 2, [grp2_weight_2..grp2_weight_7] are port 3. For port_mode in [0,1] the valid TC numbers are 0..7, for port_mode == 2 the valid TC numbers are 0..5. The values of TC per port should be unique.
+#define QM_REG_VOQ_ARB_GRP2_WEIGHT_4_E5                                                                      0x2f5cdcUL //Access:RW   DataWidth:0x3    // VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; The values are TC numbers (to reflect the priority within a port). The weights are allocated to port according to the port_mode: port_mode == 0 (1 port device) : [grp0_weight_0..grp0_weight_7] are port 0. port_mode == 1 (2 port device) : [grp0_weight_0..grp0_weight_7] are port 0, [grp1_weight_0..grp1_weight_7] are port 1. port_mode == 2 (4 port device) : [grp0_weight_0..grp0_weight_5] are port 0, [grp0_weight_6..grp0_weight_7,grp1_weight_0..grp1_weight_3] are port 1, [grp1_weight_4..grp1_weight_7,grp2_weight_0..grp2_weight_1] are port 2, [grp2_weight_2..grp2_weight_7] are port 3. For port_mode in [0,1] the valid TC numbers are 0..7, for port_mode == 2 the valid TC numbers are 0..5. The values of TC per port should be unique.
+#define QM_REG_VOQ_ARB_GRP2_WEIGHT_5_E5                                                                      0x2f5ce0UL //Access:RW   DataWidth:0x3    // VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; The values are TC numbers (to reflect the priority within a port). The weights are allocated to port according to the port_mode: port_mode == 0 (1 port device) : [grp0_weight_0..grp0_weight_7] are port 0. port_mode == 1 (2 port device) : [grp0_weight_0..grp0_weight_7] are port 0, [grp1_weight_0..grp1_weight_7] are port 1. port_mode == 2 (4 port device) : [grp0_weight_0..grp0_weight_5] are port 0, [grp0_weight_6..grp0_weight_7,grp1_weight_0..grp1_weight_3] are port 1, [grp1_weight_4..grp1_weight_7,grp2_weight_0..grp2_weight_1] are port 2, [grp2_weight_2..grp2_weight_7] are port 3. For port_mode in [0,1] the valid TC numbers are 0..7, for port_mode == 2 the valid TC numbers are 0..5. The values of TC per port should be unique.
+#define QM_REG_VOQ_ARB_GRP2_WEIGHT_6_E5                                                                      0x2f5ce4UL //Access:RW   DataWidth:0x3    // VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; The values are TC numbers (to reflect the priority within a port). The weights are allocated to port according to the port_mode: port_mode == 0 (1 port device) : [grp0_weight_0..grp0_weight_7] are port 0. port_mode == 1 (2 port device) : [grp0_weight_0..grp0_weight_7] are port 0, [grp1_weight_0..grp1_weight_7] are port 1. port_mode == 2 (4 port device) : [grp0_weight_0..grp0_weight_5] are port 0, [grp0_weight_6..grp0_weight_7,grp1_weight_0..grp1_weight_3] are port 1, [grp1_weight_4..grp1_weight_7,grp2_weight_0..grp2_weight_1] are port 2, [grp2_weight_2..grp2_weight_7] are port 3. For port_mode in [0,1] the valid TC numbers are 0..7, for port_mode == 2 the valid TC numbers are 0..5. The values of TC per port should be unique.
+#define QM_REG_VOQ_ARB_GRP2_WEIGHT_7_E5                                                                      0x2f5ce8UL //Access:RW   DataWidth:0x3    // VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; The values are TC numbers (to reflect the priority within a port). The weights are allocated to port according to the port_mode: port_mode == 0 (1 port device) : [grp0_weight_0..grp0_weight_7] are port 0. port_mode == 1 (2 port device) : [grp0_weight_0..grp0_weight_7] are port 0, [grp1_weight_0..grp1_weight_7] are port 1. port_mode == 2 (4 port device) : [grp0_weight_0..grp0_weight_5] are port 0, [grp0_weight_6..grp0_weight_7,grp1_weight_0..grp1_weight_3] are port 1, [grp1_weight_4..grp1_weight_7,grp2_weight_0..grp2_weight_1] are port 2, [grp2_weight_2..grp2_weight_7] are port 3. For port_mode in [0,1] the valid TC numbers are 0..7, for port_mode == 2 the valid TC numbers are 0..5. The values of TC per port should be unique.
+#define QM_REG_VOQ_ARB_TIMEOUT                                                                               0x2f5d2cUL //Access:RW   DataWidth:0xc    // The number of arbitration cycles between 2 adjacent RR rounds. For anti starvation purpose. Value of 0 will give regular RR arbitration.
+#define QM_REG_TX_ARB_GO_MODE                                                                                0x2f5d30UL //Access:RW   DataWidth:0x1    // Represent the TX arbiter GO working mode. Whenever TX arbitration has completed (i.e. chose the PQ and completed updating all the relevant counters and state bits), new TX arbitration will start. When the new TX arbitration cannot start as no PQ can be chosen, the arbiter enters idle state. Moving to non-idle state, trying to start new TX arbitration depends on the GO mode as follows: 0 - start new TX arbitration whenever one of the state bits (VOQ blocked, PF WFQ blocked, VP WFQ blocked, PF RL blocked, VP/QCN RL blocked, Q active, Q paused) changes its state (either XON or XOFF). 1 - start new TX arbitration whenever Tx_Arb_Go_Cycle_Period of cycles has passed from since the last time TX arbitration has started.
+#define QM_REG_TX_ARB_GO_CYCLE_PERIOD                                                                        0x2f5d34UL //Access:RW   DataWidth:0xa    // The number of cycles between 2 adjacent TX arbitrations. Valid only when Tx_Arb_Go_Mode==1
+#define QM_REG_PQ_ACTIVE_ENABLE                                                                              0x2f5d38UL //Access:RW   DataWidth:0x1    // Enable the active state mechanism logic.
+#define QM_REG_ERR_INC0_VOQLINECRD                                                                           0x2f5d3cUL //Access:RC   DataWidth:0xd    // Increment error type0 for the VOQ Line (inc above max allowed value (i.e. overflow the VOQ Line credit counter)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id;  b12-b9: client id (b9 - xsdm; b10 - ysdm; b11 - psdm; b12 - pbf)
+#define QM_REG_ERR_INC1_VOQLINECRD                                                                           0x2f5d40UL //Access:RC   DataWidth:0xd    // Increment error type1 for the VOQ Line (inc above init value. b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id;  b12-b9: client id (b9 - xsdm; b10 - ysdm; b11 - psdm; b12 - pbf)
+#define QM_REG_ERR_DEC0_VOQLINECRD                                                                           0x2f5d44UL //Access:RC   DataWidth:0xd    // Decrement error type0 for the VOQ Line (dec below the most neg value (i.e. underflow the VOQ Line credit counter)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id;  b12-b9: client id (b9 - xsdm; b10 - ysdm; b11 - psdm; b12 - tx_arb)
+#define QM_REG_ERR_DEC1_VOQLINECRD                                                                           0x2f5d48UL //Access:RC   DataWidth:0xd    // Decrement error type1 for the VOQ Line (dec when the credit counter is below zero). b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id;  b12-b9: client id (b9 - xsdm; b10 - ysdm; b11 - psdm; b12 - tx_arb)
+#define QM_REG_ERR_MASK_VOQLINECRD                                                                           0x2f5d4cUL //Access:RW   DataWidth:0x4    // per error type bit mask vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_VoqLineCrd; b1 - Err_Inc1_VoqLineCrd. b2 - Err_Dec0_VoqLineCrd; b3 - Err_Dec1_VoqLineCrd;
+#define QM_REG_ERR_INC0_VOQBYTECRD                                                                           0x2f5d50UL //Access:RC   DataWidth:0xd    // Increment error type0 for the VOQ Byte (inc above max allowed value (i.e. overflow the VOQ Byte credit counter)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id;  b12-b9: client id (b9 - xsdm; b10 - ysdm; b11 - psdm; b12 - btb)
+#define QM_REG_ERR_INC1_VOQBYTECRD                                                                           0x2f5d54UL //Access:RC   DataWidth:0xd    // Increment error type1 for the VOQ Byte (inc above init value. b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id;  b12-b9: client id (b9 - xsdm; b10 - ysdm; b11 - psdm; b12 - btb)
+#define QM_REG_ERR_DEC0_VOQBYTECRD                                                                           0x2f5d58UL //Access:RC   DataWidth:0xd    // Decrement error type0 for the VOQ Byte (dec below the most neg value (i.e. underflow the VOQ Byte credit counter)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id;  b12-b9: client id (b9 - xsdm; b10 - ysdm; b11 - psdm; b12 - tx_arb)
+#define QM_REG_ERR_DEC1_VOQBYTECRD                                                                           0x2f5d5cUL //Access:RC   DataWidth:0xd    // Decrement error type1 for the VOQ Byte (dec when the credit counter is below zero). b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id;  b12-b9: client id (b9 - xsdm; b10 - ysdm; b11 - psdm; b12 - tx_arb)
+#define QM_REG_ERR_MASK_VOQBYTECRD                                                                           0x2f5d60UL //Access:RW   DataWidth:0x4    // per error type bit mask vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_VoqByteCrd; b1 - Err_Inc1_VoqByteCrd. b2 - Err_Dec0_VoqByteCrd; b3 - Err_Dec1_VoqByteCrd;
+#define QM_REG_FIFO_EMPTY0                                                                                   0x2f5d64UL //Access:R    DataWidth:0x20   // Empty indication for all FIFOs.
+#define QM_REG_FIFO_EMPTY1                                                                                   0x2f5d68UL //Access:R    DataWidth:0x20   // Empty indication for all FIFOs.
+#define QM_REG_FIFO_FULL0                                                                                    0x2f5d6cUL //Access:R    DataWidth:0x20   // Full indication for all FIFOs.
+#define QM_REG_FIFO_FULL1                                                                                    0x2f5d70UL //Access:R    DataWidth:0x20   // Full indication for all FIFOs.
+#define QM_REG_FIFO_ERROR0                                                                                   0x2f5d74UL //Access:R    DataWidth:0x20   // Error indication for all FIFOs.
+#define QM_REG_FIFO_ERROR1                                                                                   0x2f5d78UL //Access:R    DataWidth:0x20   // Error indication for all FIFOs.
+#define QM_REG_MEM_INIT_GO                                                                                   0x2f5d7cUL //Access:RW   DataWidth:0x1    // Init go command. Upon Wr value of 1, the enabled mems (Mem_Init_Mask_0/1) will be initialized with value of Mem_Init_Value_0/1. NOTES: (a) Go command can be sent only when the mem init unit is ready (Mem_Init_Ready=1). the user is responsible to verify that prior to sending go command. (b) Go command can be sent only in init mode (i.e. no functional traffic is allowed). (c) Upon Go command and until the init is done (Mem_Init_Ready), RBC access to the mems that are being initialized (Mem_Init_Mask_0/1) is not allowed.
+#define QM_REG_MEM_INIT_READY                                                                                0x2f5d80UL //Access:R    DataWidth:0x1    // When set indicates that the mem init unit is ready to accept mem init command (Mem_Init_Go)
+#define QM_REG_MEM_INIT_MASK_0                                                                               0x2f5d84UL //Access:RW   DataWidth:0x20   // Indicates which mem to init upon Mem_Init_Go command. When set the mem is initiazlied. when reset the mem in not initiazlied. There is mask bit per mem, the following are mems 31-0: b0: qm_mem_bigram_tx b1: qm_mem_bigram_other b2: qm_mem_pq_fill_lvl_tx b3: qm_mem_pq_fill_lvl_other b4: qm_mem_voq_init_crd_line b5: qm_mem_voq_init_crd_byte b6: qm_mem_voq_crd_line b7: qm_mem_voq_crd_byte b8: qm_mem_rl_glbl_inc_val b9: qm_mem_rl_glbl_ubound b10: qm_mem_rl_glbl_crd b11: qm_mem_rl_pf_inc_val b12: qm_mem_rl_pf_ubound b13: qm_mem_rl_pf_crd b14: qm_mem_wfq_pf_weight b15: qm_mem_wfq_pf_ubound b16: qm_mem_wfq_pf_crd b17: qm_mem_wfq_vp_weight b18: qm_mem_wfq_vp_ubound b19: qm_mem_wfq_vp_crd b20: qm_mem_base_addr_tx b21: qm_mem_base_addr_other b22: qm_mem_ptr_tbl_tx b23: qm_mem_ptr_tbl_other b24: qm_mem_pf_usg_cnt b25: qm_mem_vf_usg_cnt b26: qm_mem_wrc_fifo_xcm_tx b27: qm_mem_wrc_fifo_xcm_other b28: qm_mem_wrc_fifo_ycm_other b29: qm_mem_wrc_fifo_tcm_other b30: qm_mem_wrc_fifo_mcm_other b31: qm_mem_wrc_fifo_ucm_other
+#define QM_REG_MEM_INIT_MASK_1                                                                               0x2f5d88UL //Access:RW   DataWidth:0x20   // Indicates which mem to init upon Mem_Init_Go command. When set the mem is initiazlied. when reset the mem in not initiazlied. There is mask bit per mem, the following are mems 63-32: b32: qm_mem_cfc_ldreq_buffer_ccfc_tx b33: qm_mem_cfc_ldreq_buffer_ccfc_other b34: qm_mem_cfc_ldreq_buffer_tcfc_other b35: qm_mem_pxp_req_fifo_tx b36: qm_mem_pxp_req_fifo_other b37: qm_mem_pxp_wdata_fifo_tx b38: qm_mem_pxp_wdata_fifo_other b39: qm_mem_xsdm_voq_line b40: qm_mem_ysdm_voq_line b41: qm_mem_psdm_voq_line b42: qm_mem_xsdm_voq_byte b43: qm_mem_ysdm_voq_byte b44: qm_mem_psdm_voq_byte b45: qm_mem_xsdm_rl_glbl b46: qm_mem_ysdm_rl_glbl b47: qm_mem_psdm_rl_glbl b48: qm_mem_xsdm_rl_pf b49: qm_mem_ysdm_rl_pf b50: qm_mem_psdm_rl_pf b51: qm_mem_xsdm_wfq_pf b52: qm_mem_ysdm_wfq_pf b53: qm_mem_psdm_wfq_pf b54: qm_mem_xsdm_wfq_vp b55: qm_mem_ysdm_wfq_vp b56: qm_mem_psdm_wfq_vp b57: qm_mem_cm_int_q_mask b58: qm_mem_sync_rl_rf_req b59: qm_mem_sync_rl_rf_res b60: qm_mem_sync_rl_glbl_exp b61: qm_mem_sync_rl_pf_exp b62: qm_mem_vp_arb_last_gnt b63: qm_mem_pq_arb_last_gnt
+#define QM_REG_MEM_INIT_VALUE_0                                                                              0x2f5d8cUL //Access:RW   DataWidth:0x20   // Indicates the init value to write upon Mem_Init_Go command When set the mem is initialized with all ones. when reset the mem in initialized with all zeroes. There is bit per mem, the following are mems 31-0: b0: qm_mem_bigram_tx b1: qm_mem_bigram_other b2: qm_mem_pq_fill_lvl_tx b3: qm_mem_pq_fill_lvl_other b4: qm_mem_voq_init_crd_line b5: qm_mem_voq_init_crd_byte b6: qm_mem_voq_crd_line b7: qm_mem_voq_crd_byte b8: qm_mem_rl_glbl_inc_val b9: qm_mem_rl_glbl_ubound b10: qm_mem_rl_glbl_crd b11: qm_mem_rl_pf_inc_val b12: qm_mem_rl_pf_ubound b13: qm_mem_rl_pf_crd b14: qm_mem_wfq_pf_weight b15: qm_mem_wfq_pf_ubound b16: qm_mem_wfq_pf_crd b17: qm_mem_wfq_vp_weight_ b18: qm_mem_wfq_vp_ubound_ b19: qm_mem_wfq_vp_crd b20: qm_mem_base_addr_tx b21: qm_mem_base_addr_other b22: qm_mem_ptr_tbl_tx b23: qm_mem_ptr_tbl_other b24: qm_mem_pf_usg_cnt b25: qm_mem_vf_usg_cnt b26: qm_mem_wrc_fifo_xcm_tx b27: qm_mem_wrc_fifo_xcm_other b28: qm_mem_wrc_fifo_ycm_other b29: qm_mem_wrc_fifo_tcm_other b30: qm_mem_wrc_fifo_mcm_other b31: qm_mem_wrc_fifo_ucm_other
+#define QM_REG_MEM_INIT_VALUE_1                                                                              0x2f5d90UL //Access:RW   DataWidth:0x20   // Indicates the init value to write upon Mem_Init_Go command When set the mem is initialized with all ones. when reset the mem in initialized with all zeroes. There is bit per mem, the following are mems 63-32: b32: qm_mem_cfc_ldreq_buffer_ccfc_tx b33: qm_mem_cfc_ldreq_buffer_ccfc_other b34: qm_mem_cfc_ldreq_buffer_tcfc_other b35: qm_mem_pxp_req_fifo_tx b36: qm_mem_pxp_req_fifo_other b37: qm_mem_pxp_wdata_fifo_tx b38: qm_mem_pxp_wdata_fifo_other b39: qm_mem_xsdm_voq_line b40: qm_mem_ysdm_voq_line b41: qm_mem_psdm_voq_line b42: qm_mem_xsdm_voq_byte b43: qm_mem_ysdm_voq_byte b44: qm_mem_psdm_voq_byte b45: qm_mem_xsdm_rl_glbl b46: qm_mem_ysdm_rl_glbl b47: qm_mem_psdm_rl_glbl b48: qm_mem_xsdm_rl_pf b49: qm_mem_ysdm_rl_pf b50: qm_mem_psdm_rl_pf b51: qm_mem_xsdm_wfq_pf b52: qm_mem_ysdm_wfq_pf b53: qm_mem_psdm_wfq_pf b54: qm_mem_xsdm_wfq_vp b55: qm_mem_ysdm_wfq_vp b56: qm_mem_psdm_wfq_vp b57: qm_mem_cm_int_q_mask b58: qm_mem_sync_rl_rf_req b59: qm_mem_sync_rl_rf_res b60: qm_mem_sync_rl_glbl_exp b61: qm_mem_sync_rl_pf_exp b62: qm_mem_vp_arb_last_gnt b63: qm_mem_pq_arb_last_gnt
+#define QM_REG_MEM_INIT_STS_0                                                                                0x2f5d94UL //Access:R    DataWidth:0x20   // Describes the status of the mem. When set indicates that the mem is not currently being initialized. When set indicates that the mem is currently being initialized. There is status bit per mem, the following are mems 31-0: b0: qm_mem_bigram_tx b1: qm_mem_bigram_other b2: qm_mem_pq_fill_lvl_tx b3: qm_mem_pq_fill_lvl_other b4: qm_mem_voq_init_crd_line b5: qm_mem_voq_init_crd_byte b6: qm_mem_voq_crd_line b7: qm_mem_voq_crd_byte b8: qm_mem_rl_glbl_inc_val b9: qm_mem_rl_glbl_ubound b10: qm_mem_rl_glbl_crd b11: qm_mem_rl_pf_inc_val b12: qm_mem_rl_pf_ubound b13: qm_mem_rl_pf_crd b14: qm_mem_wfq_pf_weight b15: qm_mem_wfq_pf_ubound b16: qm_mem_wfq_pf_crd b17: qm_mem_wfq_vp_weight_ b18: qm_mem_wfq_vp_ubound_ b19: qm_mem_wfq_vp_crd b20: qm_mem_base_addr_tx b21: qm_mem_base_addr_other b22: qm_mem_ptr_tbl_tx b23: qm_mem_ptr_tbl_other b24: qm_mem_pf_usg_cnt b25: qm_mem_vf_usg_cnt b26: qm_mem_wrc_fifo_xcm_tx b27: qm_mem_wrc_fifo_xcm_other b28: qm_mem_wrc_fifo_ycm_other b29: qm_mem_wrc_fifo_tcm_other b30: qm_mem_wrc_fifo_mcm_other b31: qm_mem_wrc_fifo_ucm_other
+#define QM_REG_MEM_INIT_STS_1                                                                                0x2f5d98UL //Access:R    DataWidth:0x20   // Describes the status of the mem. When set indicates that the mem is not currently being initialized. When set indicates that the mem is currently being initialized. There is status bit per mem, the following are mems 63-32: b32: qm_mem_cfc_ldreq_buffer_ccfc_tx b33: qm_mem_cfc_ldreq_buffer_ccfc_other b34: qm_mem_cfc_ldreq_buffer_tcfc_other b35: qm_mem_pxp_req_fifo_tx b36: qm_mem_pxp_req_fifo_other b37: qm_mem_pxp_wdata_fifo_tx b38: qm_mem_pxp_wdata_fifo_other b39: qm_mem_xsdm_voq_line b40: qm_mem_ysdm_voq_line b41: qm_mem_psdm_voq_line b42: qm_mem_xsdm_voq_byte b43: qm_mem_ysdm_voq_byte b44: qm_mem_psdm_voq_byte b45: qm_mem_xsdm_rl_glbl b46: qm_mem_ysdm_rl_glbl b47: qm_mem_psdm_rl_glbl b48: qm_mem_xsdm_rl_pf b49: qm_mem_ysdm_rl_pf b50: qm_mem_psdm_rl_pf b51: qm_mem_xsdm_wfq_pf b52: qm_mem_ysdm_wfq_pf b53: qm_mem_psdm_wfq_pf b54: qm_mem_xsdm_wfq_vp b55: qm_mem_ysdm_wfq_vp b56: qm_mem_psdm_wfq_vp b57: qm_mem_cm_int_q_mask b58: qm_mem_sync_rl_rf_req b59: qm_mem_sync_rl_rf_res b60: qm_mem_sync_rl_glbl_exp b61: qm_mem_sync_rl_pf_exp b62: qm_mem_vp_arb_last_gnt b63: qm_mem_pq_arb_last_gnt
+#define QM_REG_CAM_BIST_EN                                                                                   0x2f5d9cUL //Access:RW   DataWidth:0x1    // Used to enable/disable BIST mode. When set, BIST testing will be performed and the results will be posted upon completion. When cleared CAM access will be enabled through the CAM BIST mechanism instead.
+#define QM_REG_CAM_BIST_SKIP_ERROR_CNT                                                                       0x2f5da0UL //Access:RW   DataWidth:0x8    // Provides a threshold for the number of CAM BIST errors that are acceptable before reporting CAM BIST failure status.
+#define QM_REG_CAM_BIST_STATUS_SEL                                                                           0x2f5da4UL //Access:RW   DataWidth:0x8    // Used to select the BIST status word to read following the completion of a BIST test. Also used to select the data slice when writing data directly to the CAM using the CAM BIST mechanism.
+#define QM_REG_CAM_BIST_STATUS                                                                               0x2f5da8UL //Access:R    DataWidth:0x16   // Provides read-only access to the BIST status word selected by cam_bist_status_sel.
+#define QM_REG_BASEADDRTXPQ                                                                                  0x2f6000UL //Access:RW   DataWidth:0x14   // The base logical address (in 4096 bytes) of each physical queue. The index I represents the physical queue number.
+#define QM_REG_BASEADDRTXPQ_SIZE_BB                                                                          448
+#define QM_REG_BASEADDRTXPQ_SIZE_K2_E5                                                                       512
+#define QM_REG_PQFILLLVLTX                                                                                   0x2f7000UL //Access:RW   DataWidth:0x18   // The number of tasks queued for each TX queue. Should be read only access.
+#define QM_REG_PQFILLLVLTX_SIZE_BB                                                                           448
+#define QM_REG_PQFILLLVLTX_SIZE_K2_E5                                                                        512
+#define QM_REG_PQSTSTX                                                                                       0x2f8000UL //Access:R    DataWidth:0x4    // The status of the TX PQ-s: bit0 - PQ global VP/QCN RL block; bit1 - PQ active; bit2 - PQ paused; bit3 - PQ VP WFQ blocked. Should be read only access.
+#define QM_REG_PQSTSTX_SIZE_BB                                                                               448
+#define QM_REG_PQSTSTX_SIZE_K2_E5                                                                            512
+#define QM_REG_TXPQMAP                                                                                       0x2f9000UL //Access:RW   DataWidth:0x20   // (1) Mem Array: Maps between TX PQ and its resources as follows: bit  0     - PQ valid; bits 8:1   - RL id; bits 17:9  - VP id (value of all ones is reserved for pure-LB VOQ VP-s. no WFQ is implemented for such VP-s); bits 23:18 - Voq id; bits 25:24 - WRR weight group (allowed values: 2'b00 (associated with weight=0); 2'b01 (associated with weight=WrrTxGrpWeight_0); 2'b11 (associated with weight=WrrTxGrpWeight_1)); bit  26    - RL valid;  NOTE0: the reserved bits must be written with zeroes. NOTE1: Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [8..31,33,34,35] are "not used". port_mode == 1 (2 port device) : VOQs [16..31,34,35] are "not used". port_mode == 2 (4 port device) : VOQs [6,7,14,15,22,23,30,31] are "not used" NOTE : WR with "not used" Voq id value will not return an ack!!! (2) Mask Array: Should be written with the same value as the mem array. (3) NOTES: (a) The Mask array exist as the TxPqMap struct is implemented with. (b) TxPqMap_MaskAccess selects if writing to the mask array (set) or the mem array (reset).
+#define QM_REG_TXPQMAP_SIZE_BB                                                                               448
+#define QM_REG_TXPQMAP_SIZE_K2_E5                                                                            512
+#define QM_REG_WFQVPWEIGHT                                                                                   0x2fa000UL //Access:RW   DataWidth:0x1f   // The WFQ weight (increment value) for the VP WFQ counters.
+#define QM_REG_WFQVPWEIGHT_SIZE_BB                                                                           448
+#define QM_REG_WFQVPWEIGHT_SIZE_K2_E5                                                                        512
+#define QM_REG_WFQVPUPPERBOUND                                                                               0x2fb000UL //Access:RW   DataWidth:0x20   // The WFQ upper bound for the VP WFQ counters. Sign: the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bits (msb-1) to 0 are in 2s complement representation
+#define QM_REG_WFQVPUPPERBOUND_SIZE_BB                                                                       448
+#define QM_REG_WFQVPUPPERBOUND_SIZE_K2_E5                                                                    512
+#define QM_REG_WFQVPCRD                                                                                      0x2fc000UL //Access:RW   DataWidth:0x20   // The actual WFQ credit for the VP WFQ counters. Should be read only access in non-init mode. In init mode should be written with the same value of WfqVpUpperBound. Sign: the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bits (msb-1) to 0 are in 2s complement representation
+#define QM_REG_WFQVPCRD_SIZE_BB                                                                              448
+#define QM_REG_WFQVPCRD_SIZE_K2_E5                                                                           512
+#define QM_REG_WFQVPMAP                                                                                      0x2fd000UL //Access:RW   DataWidth:0xa    // (1) Mem Array: Maps between VP WFQ counter and its resources as follows: bit  5:0   - Voq id; bit  9:6   - Pf id; Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [8..31,33,34,35] are "not used". port_mode == 1 (2 port device) : VOQs [16..31,34,35] are "not used". port_mode == 2 (4 port device) : VOQs [6,7,14,15,22,23,30,31] are "not used" NOTE : WR with "not used" Voq id value will not return an ack!!! (2) NOTE: valud of 0x3ff indicates the Wfq Vp counter is not associated with any Voq and Pf
+#define QM_REG_WFQVPMAP_SIZE_BB                                                                              448
+#define QM_REG_WFQVPMAP_SIZE_K2_E5                                                                           512
+#define QM_REG_PTRTBLTX                                                                                      0x2fe000UL //Access:WB   DataWidth:0x36   // Pointer Table Memory for TX queues 447-0; The mapping is as follow: ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank;.
+#define QM_REG_PTRTBLTX_SIZE_BB                                                                              896
+#define QM_REG_PTRTBLTX_SIZE_K2_E5                                                                           1024
+#define QM_REG_WFQPFCRD_MSB_K2                                                                               0x2ff400UL //Access:RW   DataWidth:0x20   // The actual WFQ credit for the PF WFQ counters. Should be read only access in non-init mode. In init mode should be written with the same value of WfqPfUpperBound. Sign: the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bits (msb-1) to 0 are in 2s complement representation. Mapping: Counters 0-7 are associated with 8 MSB PF of VOQ0 in K2. Counters 8-15 are associated with  8 MSB PF of VOQ1 in K2. ... Counters 136-143 are associated with 8 MSB PF of VOQ17 in K2. Counters 144-151 are associated with 8 MSB PF of VOQ18 in K2. Counters 152-159 are associated with 8 MSB PF of VOQ19 in K2.
+#define QM_REG_WFQPFCRD_MSB_E5                                                                               0x2ff000UL //Access:RW   DataWidth:0x20   // The actual WFQ credit for the PF WFQ counters. Should be read only access in non-init mode. In init mode should be written with the same value of WfqPfUpperBound. Sign: the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bits (msb-1) to 0 are in 2s complement representation. Mapping: Counters 0-15 are associated with PFs 0..15 of VOQ16. ... Counters 314-319 are associated with PFs 0..15 of VOQ35. Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [16..31,33,34,35] are "not used". port_mode == 1 (2 port device) : VOQs [16..31,34,35] are "not used". port_mode == 2 (4 port device) : VOQs [22,23,30,31] are "not used" NOTE : WR/RD to a "not used" address will not return an ack!!! The above is defined in the "TX Resource Mapping" section of the EAS.
+#define QM_REG_WFQPFCRD_MSB_SIZE_K2                                                                          160
+#define QM_REG_WFQPFCRD_MSB_SIZE_E5                                                                          320
+#define QM_REG_CMINTQMASK_MSB_K2                                                                             0x2ff000UL //Access:RW   DataWidth:0x8    // An MSB bit vector per CM interface which indicates which one of the Other queues are tied to the matched CM interface. address: 7-0 MCM sec; 15-8 MCM pri; 23-16 UCM sec; 31-24 UCM pri; 39-32 TCM sec; 47-40 TCM pri; 55-48 YCM sec; 63-56 YCM pri; 71-64 XCM sec; for addr[2:0]=0 Other queues 7-0; for addr[2:0]=1 Other queues 15-8; for addr[2:0]=7 Other queues 63-56.
+#define QM_REG_CMINTQMASK_MSB_E5                                                                             0x2ff800UL //Access:RW   DataWidth:0x8    // An MSB bit vector per CM interface which indicates which one of the Other queues are tied to the matched CM interface. address: 7-0 MCM sec; 15-8 MCM pri; 23-16 UCM sec; 31-24 UCM pri; 39-32 TCM sec; 47-40 TCM pri; 55-48 YCM sec; 63-56 YCM pri; 71-64 XCM sec; for addr[2:0]=0 Other queues 7-0; for addr[2:0]=1 Other queues 15-8; for addr[2:0]=7 Other queues 63-56.
+#define QM_REG_CMINTQMASK_MSB_SIZE                                                                           72
+#define QM_REG_VOQCRDLINE_BB_K2                                                                              0x2f1580UL //Access:RW   DataWidth:0x10   // The actual line credit for each VOQ. Should be read only access in non-init mode. In init mode should be written with the same value of voqinitcrdline. Granularity of 16B.
+#define QM_REG_VOQCRDLINE_E5                                                                                 0x2ffa00UL //Access:RW   DataWidth:0x10   // The actual line credit for each VOQ. Should be read only access in non-init mode. In init mode should be written with the same value of voqinitcrdline. Granularity of 16B.
+#define QM_REG_VOQCRDLINE_SIZE_BB                                                                            18
+#define QM_REG_VOQCRDLINE_SIZE_K2                                                                            20
+#define QM_REG_VOQCRDLINE_SIZE_E5                                                                            36
+#define QM_REG_VOQINITCRDLINE_BB_K2                                                                          0x2f1680UL //Access:RW   DataWidth:0x10   // The init and maximum line credit for each VOQ. The max allowed init value is 2^15-1-2^9. Granularity of 16B.
+#define QM_REG_VOQINITCRDLINE_E5                                                                             0x2ffb00UL //Access:RW   DataWidth:0x10   // The init and maximum line credit for each VOQ. The max allowed init value is 2^15-1-2^9. Granularity of 16B.
+#define QM_REG_VOQINITCRDLINE_SIZE_BB                                                                        18
+#define QM_REG_VOQINITCRDLINE_SIZE_K2                                                                        20
+#define QM_REG_VOQINITCRDLINE_SIZE_E5                                                                        36
+#define QM_REG_VOQCRDBYTE_BB_K2                                                                              0x2f1780UL //Access:RW   DataWidth:0x18   // The actual byte credit for each VOQ. Should be read only access in non-init mode. In init mode should be written with the same value of voqinitcrdbyte.
+#define QM_REG_VOQCRDBYTE_E5                                                                                 0x2ffc00UL //Access:RW   DataWidth:0x18   // The actual byte credit for each VOQ. Should be read only access in non-init mode. In init mode should be written with the same value of voqinitcrdbyte.
+#define QM_REG_VOQCRDBYTE_SIZE_BB                                                                            18
+#define QM_REG_VOQCRDBYTE_SIZE_K2                                                                            20
+#define QM_REG_VOQCRDBYTE_SIZE_E5                                                                            36
+#define QM_REG_VOQINITCRDBYTE_BB_K2                                                                          0x2f1880UL //Access:RW   DataWidth:0x18   // The init and maximum byte credit for each VOQ. The max allowed init value is 2^23-1-2^16.
+#define QM_REG_VOQINITCRDBYTE_E5                                                                             0x2ffd00UL //Access:RW   DataWidth:0x18   // The init and maximum byte credit for each VOQ. The max allowed init value is 2^23-1-2^16.
+#define QM_REG_VOQINITCRDBYTE_SIZE_BB                                                                        18
+#define QM_REG_VOQINITCRDBYTE_SIZE_K2                                                                        20
+#define QM_REG_VOQINITCRDBYTE_SIZE_E5                                                                        36
+#define QM_REG_AFULLQMBYPTHRLINEVOQMASK_MSB_E5                                                               0x2ffe00UL //Access:RW   DataWidth:0x4    // VOQ line credit almost full threshold mask for the QM bypass feature (per VOQ id bit). AFullQmBypThrLineVoqMask                - VOQs [0..31]. AFullQmBypThrLineVoqMask_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [33,34,35] are "not used". port_mode == 1 (2 port device) : VOQs [34,35] are "not used". When 1 the VOQ line credit counter should be equal to the VOQ line init value to enable bypass. When 0 - the VOQ line credit counter is don't care, and bypass can be implemented regardless of the VOQ line counter value.
+#define QM_REG_RLPFVOQENABLE_MSB_E5                                                                          0x2ffe04UL //Access:RW   DataWidth:0x4    // Enabling the PF RL mechanism per VOQ. RlPfVoqEnable                - VOQs [0..31]. RlPfVoqEnable_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [33,34,35] are "not used". port_mode == 1 (2 port device) : VOQs [34,35] are "not used".
+#define QM_REG_VOQCRDLINEFULL_MSB_E5                                                                         0x2ffe08UL //Access:R    DataWidth:0x4    // VoqCrdLineFull                - VOQs [0..31]. VoqCrdLineFull_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [33,34,35] are "not used". port_mode == 1 (2 port device) : VOQs [34,35] are "not used". When set, inidicates that the VOQ line credit counter is equal to the VOQ line init value. There is a bit per VOQ.
+#define QM_REG_VOQCRDBYTEFULL_MSB_E5                                                                         0x2ffe0cUL //Access:R    DataWidth:0x4    // VoqCrdByteFull                - VOQs [0..31]. VoqCrdByteFull_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [33,34,35] are "not used". port_mode == 1 (2 port device) : VOQs [34,35] are "not used". When set, inidicates that the VOQ byte credit counter is equal to the VOQ byte init value. There is a bit per VOQ.
+#define RDIF_REG_RESET_MEMORIES                                                                              0x300000UL //Access:W    DataWidth:0x1    // Write one to this register will write zero to all L1 entries. When the command is complete zero will be indicated in this register.
+#define RDIF_REG_STOP_ON_ERROR                                                                               0x300040UL //Access:RW   DataWidth:0x1    // If set and DIF block found error; the DIF block will be stuck - hard reset is needed.
+#define RDIF_REG_BYPASS_MODE_EN                                                                              0x300044UL //Access:RW   DataWidth:0x1    // If set allow bypass the pipline on pass through commands and in an empty system.
+#define RDIF_REG_ECO_RESERVED                                                                                0x300048UL //Access:RW   DataWidth:0x8    // ECO reserved.
+#define RDIF_REG_MIN_EOB2WF_L1_RD_DEL                                                                        0x30004cUL //Access:RW   DataWidth:0x6    // If the L1 of an LTID is not updated since EOB within the configured number of cycles the dirty_l1 register will be set. Configuring 0 is the same as 1.
+#define RDIF_REG_DIRTY_L1                                                                                    0x300054UL //Access:R    DataWidth:0x1    // Indicates that there is a pending L1 WB. Set only if this is the case for at least min_eob2wf_l1_rd_del cycles.
+#define RDIF_REG_DEBUG_BUFER_0_READ_EN                                                                       0x300058UL //Access:W    DataWidth:0x1    // Writing to this register (any value) will copy the data in buffer 0 to the debug_buffer_0_data_0..8.
+#define RDIF_REG_DEBUG_BUFER_0_READ_EN_SIZE                                                                  2
+#define RDIF_REG_DEBUG_BUFER_1_READ_EN                                                                       0x300068UL //Access:W    DataWidth:0x1    // Writing to this register (any value) will copy the data in buffer 0 to the debug_buffer_1_data_0..8.
+#define RDIF_REG_DEBUG_BUFER_1_READ_EN_SIZE                                                                  2
+#define RDIF_REG_DEBUG_COMMAND_FIFO_EMPTY                                                                    0x300070UL //Access:R    DataWidth:0x1    // Debug: 1 =  fifo is empty.
+#define RDIF_REG_DEBUG_ORDER_FIFO_EMPTY                                                                      0x300074UL //Access:R    DataWidth:0x1    // Debug: 1 =  fifo is empty.
+#define RDIF_REG_DEBUG_RDATA_FIFO_EMPTY                                                                      0x300078UL //Access:R    DataWidth:0x1    // Debug: 1 =  fifo is empty.
+#define RDIF_REG_DEBUG_ERROR_DATA_VALID                                                                      0x30007cUL //Access:RW   DataWidth:0x8    // If bit i is set; the data in the debug_error_info address[5:3] = i is valid. By writing 1 to bit j it will clear the valid bits of bit j.
+#define RDIF_REG_DEBUG_BUFFER_0_DATA_0                                                                       0x300080UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. TID.
+#define RDIF_REG_DEBUG_BUFFER_0_DATA_1                                                                       0x300084UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. Initial referance tag.
+#define RDIF_REG_DEBUG_BUFFER_0_DATA_2                                                                       0x300088UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. [15:0] - application tag; [31:16] - application mask.
+#define RDIF_REG_DEBUG_BUFFER_0_DATA_3                                                                       0x30008cUL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calculated checksum.
+#define RDIF_REG_DEBUG_BUFFER_0_DATA_4                                                                       0x300090UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. Calculated offset in IO.
+#define RDIF_REG_DEBUG_BUFFER_0_DATA_5                                                                       0x300094UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
+#define RDIF_REG_DEBUG_BUFFER_0_DATA_6                                                                       0x300098UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application tag; [31:0] CRC/checksum.
+#define RDIF_REG_DEBUG_BUFFER_0_DATA_7                                                                       0x30009cUL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. [31] partial_chksum_overflow ; [30:27] dif_bytes_tx ; [26:23] dif_bytes_rx ; [22:19] last_dif_size; [18] eob_flag ; [17] data_is_dix ; [16] set_id ; [15:13] protocol_id; [12:9] type;  [8:0] ltid.
+#define RDIF_REG_DEBUG_BUFFER_0_DATA_8                                                                       0x3000a0UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. [20:19]  dix_size; [18] ni ; [17:16] hi ; [15:13] interval_size ; [12] fwrd_ref ; [11] fwrd_app ; [10]  fwrd_guard ; [9] validate_ref ; [8] validate_app ; [7] validate_guard ; [6] crc_seed ; [5:4] protection_type ; [3]  set_err_with_eop ; [2] host_guard_is_crc ; [1]  initial_ref_tag_valid; [0] err_in_io.
+#define RDIF_REG_DEBUG_BUFFER_1_DATA_0                                                                       0x3000a4UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. TID.
+#define RDIF_REG_DEBUG_BUFFER_1_DATA_1                                                                       0x3000a8UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. Initial referance tag.
+#define RDIF_REG_DEBUG_BUFFER_1_DATA_2                                                                       0x3000acUL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. [15:0] - application tag; [31:16] - application mask.
+#define RDIF_REG_DEBUG_BUFFER_1_DATA_3                                                                       0x3000b0UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calculated checksum.
+#define RDIF_REG_DEBUG_BUFFER_1_DATA_4                                                                       0x3000b4UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. Calculated offset in IO.
+#define RDIF_REG_DEBUG_BUFFER_1_DATA_5                                                                       0x3000b8UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
+#define RDIF_REG_DEBUG_BUFFER_1_DATA_6                                                                       0x3000bcUL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application tag; [31:0] CRC/checksum.
+#define RDIF_REG_DEBUG_BUFFER_1_DATA_7                                                                       0x3000c0UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. [31] partial_chksum_overflow ; [30:27] dif_bytes_tx ; [26:23] dif_bytes_rx ; [22:19] last_dif_size; [18] eob_flag ; [17] data_is_dix ; [16] set_id ; [15:13] protocol_id; [12:9] type;  [8:0] ltid.
+#define RDIF_REG_DEBUG_BUFFER_1_DATA_8                                                                       0x3000c4UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. [20:19]  dix_size; [18] ni ; [17:16] hi ; [15:13] interval_size ; [12] fwrd_ref ; [11] fwrd_app ; [10]  fwrd_guard ; [9] validate_ref ; [8] validate_app ; [7] validate_guard ; [6] crc_seed ; [5:4] protection_type ; [3]  set_err_with_eop ; [2] host_guard_is_crc ; [1]  initial_ref_tag_valid; [0] err_in_io.
+#define RDIF_REG_DEBUG_DIX_FIFO_EMPTY                                                                        0x3000c8UL //Access:R    DataWidth:0x1    // Debug: one bit for each protocol ID.  1 =  fifo is empty.
+#define RDIF_REG_DEBUG_UCM_CREDIT                                                                            0x3000ccUL //Access:R    DataWidth:0x1    // DEBUG: 0 - no credit; 1 - there is credit.
+#define RDIF_REG_DEBUG_UCM_MSG_PENDING                                                                       0x3000d0UL //Access:R    DataWidth:0x1    // DEBUG: 0 - no message pending; 1 - message is pending (no credit) or waiting for done.
+#define RDIF_REG_DEBUG_FATAL_CONFIG_ERR_INFO                                                                 0x3000d4UL //Access:R    DataWidth:0x15   // DEBUG: configuration fatal error. [1:0] host interface; [2] network interface; [3] FWRD ref; [4] FWR app; [5] FWRD guard; [6] vlidate ref; [7] validate app; [8] validate guard; [10:9] protocol ID; [19:11] LTID; [20] buffer select.
+#define RDIF_REG_DEBUG_PIPELINE_IDLE                                                                         0x3000d8UL //Access:R    DataWidth:0x1    // DEBUG: if set there is no valid data in the pipeline.
+#define RDIF_REG_STAT_NUM_ERR_INTERVAL_0                                                                     0x3000dcUL //Access:RW   DataWidth:0x20   // Number of interval with error arrived to the DIF for protocol ID 0.
+#define RDIF_REG_INT_STS                                                                                     0x300180UL //Access:R    DataWidth:0x9    // Multi Field Register.
+  #define RDIF_REG_INT_STS_ADDRESS_ERROR                                                                     (0x1<<0) // Signals an unknown address to the rf module.
+  #define RDIF_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                               0
+  #define RDIF_REG_INT_STS_FATAL_DIX_ERR                                                                     (0x1<<1) // DIX data is missing or end of burst assived and not all DIX data was used.
+  #define RDIF_REG_INT_STS_FATAL_DIX_ERR_SHIFT                                                               1
+  #define RDIF_REG_INT_STS_FATAL_CONFIG_ERR                                                                  (0x1<<2) // Fatal configuration error due to illigal comdination of host interface, network interface, validate xxx and forward xxx.
+  #define RDIF_REG_INT_STS_FATAL_CONFIG_ERR_SHIFT                                                            2
+  #define RDIF_REG_INT_STS_CMD_FIFO_ERR                                                                      (0x1<<3) // Write to full FIFO or read from empty FIFO.
+  #define RDIF_REG_INT_STS_CMD_FIFO_ERR_SHIFT                                                                3
+  #define RDIF_REG_INT_STS_ORDER_FIFO_ERR                                                                    (0x1<<4) // Write to full FIFO or read from empty FIFO.
+  #define RDIF_REG_INT_STS_ORDER_FIFO_ERR_SHIFT                                                              4
+  #define RDIF_REG_INT_STS_RDATA_FIFO_ERR                                                                    (0x1<<5) // Write to full FIFO or read from empty FIFO.
+  #define RDIF_REG_INT_STS_RDATA_FIFO_ERR_SHIFT                                                              5
+  #define RDIF_REG_INT_STS_DIF_STOP_ERR                                                                      (0x1<<6) // If stop_on_error is set and the DIF block found error in the DIF/DIX data this interrupt will be asserted. The debug info is in debug_error_info.
+  #define RDIF_REG_INT_STS_DIF_STOP_ERR_SHIFT                                                                6
+  #define RDIF_REG_INT_STS_PARTIAL_DIF_W_EOB                                                                 (0x1<<7) // end of burst arrived with end of interval and only partial DIF data arrived.
+  #define RDIF_REG_INT_STS_PARTIAL_DIF_W_EOB_SHIFT                                                           7
+  #define RDIF_REG_INT_STS_L1_DIRTY_BIT_K2_E5                                                                (0x1<<8) // One of the command buffers has a pending L1 WB for more than MIN_EOB2WF_L1_RD_DEL (register) cycles.
+  #define RDIF_REG_INT_STS_L1_DIRTY_BIT_K2_E5_SHIFT                                                          8
+#define RDIF_REG_INT_MASK                                                                                    0x300184UL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define RDIF_REG_INT_MASK_ADDRESS_ERROR                                                                    (0x1<<0) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.ADDRESS_ERROR .
+  #define RDIF_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                              0
+  #define RDIF_REG_INT_MASK_FATAL_DIX_ERR                                                                    (0x1<<1) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.FATAL_DIX_ERR .
+  #define RDIF_REG_INT_MASK_FATAL_DIX_ERR_SHIFT                                                              1
+  #define RDIF_REG_INT_MASK_FATAL_CONFIG_ERR                                                                 (0x1<<2) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.FATAL_CONFIG_ERR .
+  #define RDIF_REG_INT_MASK_FATAL_CONFIG_ERR_SHIFT                                                           2
+  #define RDIF_REG_INT_MASK_CMD_FIFO_ERR                                                                     (0x1<<3) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.CMD_FIFO_ERR .
+  #define RDIF_REG_INT_MASK_CMD_FIFO_ERR_SHIFT                                                               3
+  #define RDIF_REG_INT_MASK_ORDER_FIFO_ERR                                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.ORDER_FIFO_ERR .
+  #define RDIF_REG_INT_MASK_ORDER_FIFO_ERR_SHIFT                                                             4
+  #define RDIF_REG_INT_MASK_RDATA_FIFO_ERR                                                                   (0x1<<5) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.RDATA_FIFO_ERR .
+  #define RDIF_REG_INT_MASK_RDATA_FIFO_ERR_SHIFT                                                             5
+  #define RDIF_REG_INT_MASK_DIF_STOP_ERR                                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.DIF_STOP_ERR .
+  #define RDIF_REG_INT_MASK_DIF_STOP_ERR_SHIFT                                                               6
+  #define RDIF_REG_INT_MASK_PARTIAL_DIF_W_EOB                                                                (0x1<<7) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.PARTIAL_DIF_W_EOB .
+  #define RDIF_REG_INT_MASK_PARTIAL_DIF_W_EOB_SHIFT                                                          7
+  #define RDIF_REG_INT_MASK_L1_DIRTY_BIT_K2_E5                                                               (0x1<<8) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.L1_DIRTY_BIT .
+  #define RDIF_REG_INT_MASK_L1_DIRTY_BIT_K2_E5_SHIFT                                                         8
+#define RDIF_REG_INT_STS_WR                                                                                  0x300188UL //Access:WR   DataWidth:0x9    // Multi Field Register.
+  #define RDIF_REG_INT_STS_WR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define RDIF_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                            0
+  #define RDIF_REG_INT_STS_WR_FATAL_DIX_ERR                                                                  (0x1<<1) // DIX data is missing or end of burst assived and not all DIX data was used.
+  #define RDIF_REG_INT_STS_WR_FATAL_DIX_ERR_SHIFT                                                            1
+  #define RDIF_REG_INT_STS_WR_FATAL_CONFIG_ERR                                                               (0x1<<2) // Fatal configuration error due to illigal comdination of host interface, network interface, validate xxx and forward xxx.
+  #define RDIF_REG_INT_STS_WR_FATAL_CONFIG_ERR_SHIFT                                                         2
+  #define RDIF_REG_INT_STS_WR_CMD_FIFO_ERR                                                                   (0x1<<3) // Write to full FIFO or read from empty FIFO.
+  #define RDIF_REG_INT_STS_WR_CMD_FIFO_ERR_SHIFT                                                             3
+  #define RDIF_REG_INT_STS_WR_ORDER_FIFO_ERR                                                                 (0x1<<4) // Write to full FIFO or read from empty FIFO.
+  #define RDIF_REG_INT_STS_WR_ORDER_FIFO_ERR_SHIFT                                                           4
+  #define RDIF_REG_INT_STS_WR_RDATA_FIFO_ERR                                                                 (0x1<<5) // Write to full FIFO or read from empty FIFO.
+  #define RDIF_REG_INT_STS_WR_RDATA_FIFO_ERR_SHIFT                                                           5
+  #define RDIF_REG_INT_STS_WR_DIF_STOP_ERR                                                                   (0x1<<6) // If stop_on_error is set and the DIF block found error in the DIF/DIX data this interrupt will be asserted. The debug info is in debug_error_info.
+  #define RDIF_REG_INT_STS_WR_DIF_STOP_ERR_SHIFT                                                             6
+  #define RDIF_REG_INT_STS_WR_PARTIAL_DIF_W_EOB                                                              (0x1<<7) // end of burst arrived with end of interval and only partial DIF data arrived.
+  #define RDIF_REG_INT_STS_WR_PARTIAL_DIF_W_EOB_SHIFT                                                        7
+  #define RDIF_REG_INT_STS_WR_L1_DIRTY_BIT_K2_E5                                                             (0x1<<8) // One of the command buffers has a pending L1 WB for more than MIN_EOB2WF_L1_RD_DEL (register) cycles.
+  #define RDIF_REG_INT_STS_WR_L1_DIRTY_BIT_K2_E5_SHIFT                                                       8
+#define RDIF_REG_INT_STS_CLR                                                                                 0x30018cUL //Access:RC   DataWidth:0x9    // Multi Field Register.
+  #define RDIF_REG_INT_STS_CLR_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define RDIF_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                           0
+  #define RDIF_REG_INT_STS_CLR_FATAL_DIX_ERR                                                                 (0x1<<1) // DIX data is missing or end of burst assived and not all DIX data was used.
+  #define RDIF_REG_INT_STS_CLR_FATAL_DIX_ERR_SHIFT                                                           1
+  #define RDIF_REG_INT_STS_CLR_FATAL_CONFIG_ERR                                                              (0x1<<2) // Fatal configuration error due to illigal comdination of host interface, network interface, validate xxx and forward xxx.
+  #define RDIF_REG_INT_STS_CLR_FATAL_CONFIG_ERR_SHIFT                                                        2
+  #define RDIF_REG_INT_STS_CLR_CMD_FIFO_ERR                                                                  (0x1<<3) // Write to full FIFO or read from empty FIFO.
+  #define RDIF_REG_INT_STS_CLR_CMD_FIFO_ERR_SHIFT                                                            3
+  #define RDIF_REG_INT_STS_CLR_ORDER_FIFO_ERR                                                                (0x1<<4) // Write to full FIFO or read from empty FIFO.
+  #define RDIF_REG_INT_STS_CLR_ORDER_FIFO_ERR_SHIFT                                                          4
+  #define RDIF_REG_INT_STS_CLR_RDATA_FIFO_ERR                                                                (0x1<<5) // Write to full FIFO or read from empty FIFO.
+  #define RDIF_REG_INT_STS_CLR_RDATA_FIFO_ERR_SHIFT                                                          5
+  #define RDIF_REG_INT_STS_CLR_DIF_STOP_ERR                                                                  (0x1<<6) // If stop_on_error is set and the DIF block found error in the DIF/DIX data this interrupt will be asserted. The debug info is in debug_error_info.
+  #define RDIF_REG_INT_STS_CLR_DIF_STOP_ERR_SHIFT                                                            6
+  #define RDIF_REG_INT_STS_CLR_PARTIAL_DIF_W_EOB                                                             (0x1<<7) // end of burst arrived with end of interval and only partial DIF data arrived.
+  #define RDIF_REG_INT_STS_CLR_PARTIAL_DIF_W_EOB_SHIFT                                                       7
+  #define RDIF_REG_INT_STS_CLR_L1_DIRTY_BIT_K2_E5                                                            (0x1<<8) // One of the command buffers has a pending L1 WB for more than MIN_EOB2WF_L1_RD_DEL (register) cycles.
+  #define RDIF_REG_INT_STS_CLR_L1_DIRTY_BIT_K2_E5_SHIFT                                                      8
+#define RDIF_REG_PRTY_MASK                                                                                   0x300194UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define RDIF_REG_PRTY_MASK_DATAPATH_REGISTERS                                                              (0x1<<1) // This bit masks, when set, the Parity bit: RDIF_REG_PRTY_STS.DATAPATH_REGISTERS .
+  #define RDIF_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                                        1
+#define RDIF_REG_DEBUG_ERROR_INFO                                                                            0x300400UL //Access:R    DataWidth:0x20   // Information on the first 8 DIF errors found. In bits [5:3] of the address represent the error number (0-7). Do not read from address[3:5]=i if debug_error_data_valid[i] isn't set. Bits [2:0] in the address will contain the following data: address[2:0] = 0 - [31:0] calculated reference tag; address[2:0] = 1 - [15:0] calculated application tag; [31:0]; calculated CRC/checksum; address[2:0] = 2 - [31:0] expected reference tag; address[2:0] = 3 - [15:0] expected application tag; [31:0] expected CRC/checksum; address[2:0] = 4 - [31:0] the interval number the error occurred; address[2:0] = 5 - [31:0] TID address[2:0] = 6 - [3:0] - type; [12:4] - LTID; [15:13] protocol ID; [16] set ID; [18:17] host interface; [19] network interface; [22:20] error type ([0] - CRC/checksum; [1] application tag; [2] reference tag); [31:23] reserved; address[2:0] = 7 - reserved.
+#define RDIF_REG_DEBUG_ERROR_INFO_SIZE                                                                       64
+#define RDIF_REG_DBG_SELECT                                                                                  0x300500UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define RDIF_REG_DBG_DWORD_ENABLE                                                                            0x300504UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define RDIF_REG_DBG_SHIFT                                                                                   0x300508UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define RDIF_REG_DBG_FORCE_VALID                                                                             0x30050cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define RDIF_REG_DBG_FORCE_FRAME                                                                             0x300510UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define RDIF_REG_DBG_OUT_DATA                                                                                0x300520UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define RDIF_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define RDIF_REG_DBG_OUT_VALID                                                                               0x300540UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define RDIF_REG_DBG_OUT_FRAME                                                                               0x300544UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define RDIF_REG_L1_TASK_CONTEXT                                                                             0x304000UL //Access:WB   DataWidth:0x40   // Task context memory. for TDIF Only 320b are valid. Data order:Field name-Initial reference tag Address offset-0 bits [31:0]; Field name-Application tag value Address offset-0 bits [47:32]; Field name-Application tag mask Address offset-0 bits [63:48]; Field name-Partial CRC value B Address offset-1 bits [15:0]; Field name-Partial checksum value B Address offset-1 bits [31:16]; Field name-Received DIF bytes left B Address offset-1 bits [35:32]; Field name-Transmitted DIF bytes B Address offset-1 bits [39:36]; Field name-Error in IO B Address offset-1 bits [40:40]; Field name-Checksum overflow B Address offset-1 bits [41]; Field name-Reserved Address offset-1  [55:42]; Field name-Ignore application tag for guard  Address offset-1 bits [56]; Field name-Initial reference tag valid  Address offset-1 bits [57]; Field name-Host Guard type Address offset-1 bits [58]; Field name-Set error with EOP Address offset-1 bits [59]; Field name-Protection type Address offset-1 bits [60]; Field name-CRC seed  Address offset-1 bits [62]; Field name-Reserved  Address offset-1 bits [63]; Field name-Validate guard Address offset-2 bits [0]; Field name-Validate application tag Address offset-2 bits [1]; Field name-Validate  reference tag Address offset-2 bits [2]; Field name-Forward guard  Address offset-2 bits [3]; Field name-Forward application tag  Address offset-2 bits [4]; Field name-Forward reference tag  Address offset-2 bits [5]; Field name-Interval size Address offset-2 bits [8:6]; Field name-Host interface Address offset-2 bits [10:9]; Field name-DIX block size Address offset-2 bits [12:11]; Field name-Network Interface  Address offset-2 bits [13]; Field name-Received DIF bytes left A Address offset-2 bits [17:14]; Field name-Transmitted DIF bytes A Address offset-2 bits [21:18]; Field name-Error in IO A Address offset-2 bits [22:22]; Field name-Checksum overflow A Address offset-2 bits [23]; Field name-Reserved Address offset-2 bits [31:24]; Field name-Offset in IO B Address offset-2 bits [63:32]; Field name-Partial CRC value A Address offset-3 bits [15:0]; Field name-Partial checksum value A Address offset-3 bits [31:16]; Field name-Offset in IO A Address offset-3 bits [63:32]; Field name-Partial DIF data A Address offset-4 bits [63:0]; Field name-Partial DIF data B Address offset-5 bits [63:0].  Address offset-6 and 7 - reserved. all reserved fields are un reachable for write and return zero on read. Address offset is in QWORD resolution.
+#define RDIF_REG_L1_TASK_CONTEXT_SIZE                                                                        2560
+#define TDIF_REG_RESET_MEMORIES                                                                              0x310000UL //Access:W    DataWidth:0x1    // Write one to this register will write zero to all L1 entries. When the command is complete zero will be indicated in this register.
+#define TDIF_REG_STOP_ON_ERROR                                                                               0x310040UL //Access:RW   DataWidth:0x1    // If set and DIF block found error; the DIF block will be stuck - hard reset is needed.
+#define TDIF_REG_EOB_AND_PARTIAL_DIF_ERR_MASK                                                                0x310044UL //Access:RW   DataWidth:0x1    // mask bit for the following case: host interface = DIF end of burst arrived with end of interval and only partial DIF data arrived. If clear and this event occuer a fatal error will cause the DIF block to stop.
+#define TDIF_REG_BYPASS_MODE_EN                                                                              0x310048UL //Access:RW   DataWidth:0x1    // If set allow bypass the pipline on pass through commands and in an empty system.
+#define TDIF_REG_ECO_RESERVED                                                                                0x31004cUL //Access:RW   DataWidth:0x8    // ECO reserved.
+#define TDIF_REG_MIN_EOB2WF_L1_RD_DEL                                                                        0x310050UL //Access:RW   DataWidth:0x6    // If the L1 of an LTID is not updated since EOB within the configured number of cycles the dirty_l1 register will be set. Configuring 0 is the same as 1.
+#define TDIF_REG_DIRTY_L1                                                                                    0x310054UL //Access:R    DataWidth:0x1    // Indicates that there is a pending L1 WB. Set only if this is the case for at least min_eob2wf_l1_rd_del cycles.
+#define TDIF_REG_DEBUG_BUFER_0_READ_EN                                                                       0x310058UL //Access:W    DataWidth:0x1    // Writing to this register (any value) will copy the data in buffer 0 to the debug_buffer_0_data_0..8.
+#define TDIF_REG_DEBUG_BUFER_0_READ_EN_SIZE                                                                  2
+#define TDIF_REG_DEBUG_BUFER_1_READ_EN                                                                       0x310068UL //Access:W    DataWidth:0x1    // Writing to this register (any value) will copy the data in buffer 0 to the debug_buffer_1_data_0..8.
+#define TDIF_REG_DEBUG_BUFER_1_READ_EN_SIZE                                                                  2
+#define TDIF_REG_DEBUG_COMMAND_FIFO_EMPTY                                                                    0x310070UL //Access:R    DataWidth:0x1    // Debug: 1 =  fifo is empty.
+#define TDIF_REG_DEBUG_ORDER_FIFO_EMPTY                                                                      0x310074UL //Access:R    DataWidth:0x1    // Debug: 1 =  fifo is empty.
+#define TDIF_REG_DEBUG_RDATA_FIFO_EMPTY                                                                      0x310078UL //Access:R    DataWidth:0x1    // Debug: 1 =  fifo is empty.
+#define TDIF_REG_DEBUG_ERROR_DATA_VALID                                                                      0x31007cUL //Access:RW   DataWidth:0x8    // If bit i is set; the data in the debug_error_info address[5:3] = i is valid. By writing 1 to bit j it will clear the valid bits of bit j.
+#define TDIF_REG_DEBUG_BUFFER_0_DATA_0                                                                       0x310080UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. TID.
+#define TDIF_REG_DEBUG_BUFFER_0_DATA_1                                                                       0x310084UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. Initial referance tag.
+#define TDIF_REG_DEBUG_BUFFER_0_DATA_2                                                                       0x310088UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. [15:0] - application tag; [31:16] - application mask.
+#define TDIF_REG_DEBUG_BUFFER_0_DATA_3                                                                       0x31008cUL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calculated checksum.
+#define TDIF_REG_DEBUG_BUFFER_0_DATA_4                                                                       0x310090UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. Calculated offset in IO.
+#define TDIF_REG_DEBUG_BUFFER_0_DATA_5                                                                       0x310094UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
+#define TDIF_REG_DEBUG_BUFFER_0_DATA_6                                                                       0x310098UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application tag; [31:0] CRC/checksum.
+#define TDIF_REG_DEBUG_BUFFER_0_DATA_7                                                                       0x31009cUL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. [31] partial_chksum_overflow ; [30:27] dif_bytes_tx ; [26:23] dif_bytes_rx ; [22:19] last_dif_size; [18] eob_flag ; [17] data_is_dix ; [16] set_id ; [15:13] protocol_id; [12:9] type;  [8:0] ltid.
+#define TDIF_REG_DEBUG_BUFFER_0_DATA_8                                                                       0x3100a0UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. [20:19]  dix_size; [18] ni ; [17:16] hi ; [15:13] interval_size ; [12] fwrd_ref ; [11] fwrd_app ; [10]  fwrd_guard ; [9] validate_ref ; [8] validate_app ; [7] validate_guard ; [6] crc_seed ; [5:4] protection_type ; [3]  set_err_with_eop ; [2] host_guard_is_crc ; [1]  initial_ref_tag_valid; [0] err_in_io.
+#define TDIF_REG_DEBUG_BUFFER_1_DATA_0                                                                       0x3100a4UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. TID.
+#define TDIF_REG_DEBUG_BUFFER_1_DATA_1                                                                       0x3100a8UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. Initial referance tag.
+#define TDIF_REG_DEBUG_BUFFER_1_DATA_2                                                                       0x3100acUL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. [15:0] - application tag; [31:16] - application mask.
+#define TDIF_REG_DEBUG_BUFFER_1_DATA_3                                                                       0x3100b0UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calculated checksum.
+#define TDIF_REG_DEBUG_BUFFER_1_DATA_4                                                                       0x3100b4UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. Calculated offset in IO.
+#define TDIF_REG_DEBUG_BUFFER_1_DATA_5                                                                       0x3100b8UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
+#define TDIF_REG_DEBUG_BUFFER_1_DATA_6                                                                       0x3100bcUL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application tag; [31:0] CRC/checksum.
+#define TDIF_REG_DEBUG_BUFFER_1_DATA_7                                                                       0x3100c0UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. [31] partial_chksum_overflow ; [30:27] dif_bytes_tx ; [26:23] dif_bytes_rx ; [22:19] last_dif_size; [18] eob_flag ; [17] data_is_dix ; [16] set_id ; [15:13] protocol_id; [12:9] type;  [8:0] ltid.
+#define TDIF_REG_DEBUG_BUFFER_1_DATA_8                                                                       0x3100c4UL //Access:R    DataWidth:0x20   // DEBUG: Buffer information. [20:19]  dix_size; [18] ni ; [17:16] hi ; [15:13] interval_size ; [12] fwrd_ref ; [11] fwrd_app ; [10]  fwrd_guard ; [9] validate_ref ; [8] validate_app ; [7] validate_guard ; [6] crc_seed ; [5:4] protection_type ; [3]  set_err_with_eop ; [2] host_guard_is_crc ; [1]  initial_ref_tag_valid; [0] err_in_io.
+#define TDIF_REG_DEBUG_DIX_FIFO_EMPTY                                                                        0x3100c8UL //Access:R    DataWidth:0x4    // Debug: one bit for each protocol ID.  1 =  fifo is empty.
+#define TDIF_REG_DEBUG_UCM_CREDIT                                                                            0x3100ccUL //Access:R    DataWidth:0x1    // DEBUG: 0 - no credit; 1 - there is credit.
+#define TDIF_REG_DEBUG_UCM_MSG_PENDING                                                                       0x3100d0UL //Access:R    DataWidth:0x1    // DEBUG: 0 - no message pending; 1 - message is pending (no credit) or waiting for done.
+#define TDIF_REG_DEBUG_FATAL_CONFIG_ERR_INFO                                                                 0x3100d4UL //Access:R    DataWidth:0x16   // DEBUG: configuration fatal error. [1:0] host interface; [2] network interface; [3] FWRD ref; [4] FWR app; [5] FWRD guard; [6] vlidate ref; [7] validate app; [8] validate guard; [11:9] protocol ID; [20:12] LTID; [21] buffer select.
+#define TDIF_REG_DEBUG_DIX_FATAL_ERR_INFO                                                                    0x3100d8UL //Access:R    DataWidth:0x1a   // [3:0] - error type ([0] Write overflow. [1] Read overflow. [2] Read from DIX when DIX write pointer =< DIX read pointer. [3] EOB arrived and DIX write pointer != DIX read pointer.); [5:4] protocol ID; [6] reserved;  [7] buffer inuse; [16:8] write pointer; [25:17] read pointer.
+#define TDIF_REG_DEBUG_PIPELINE_IDLE                                                                         0x3100dcUL //Access:R    DataWidth:0x1    // DEBUG: if set there is no valid data in the pipeline.
+#define TDIF_REG_STAT_NUM_ERR_INTERVAL_0                                                                     0x3100e0UL //Access:RW   DataWidth:0x20   // Number of interval with error arrived to the DIF for protocol ID 0.
+#define TDIF_REG_STAT_NUM_ERR_INTERVAL_1                                                                     0x3100e4UL //Access:RW   DataWidth:0x20   // Number of interval with error arrived to the DIF for protocol ID 1.
+#define TDIF_REG_STAT_NUM_ERR_INTERVAL_2                                                                     0x3100e8UL //Access:RW   DataWidth:0x20   // Number of interval with error arrived to the DIF for protocol ID 2.
+#define TDIF_REG_STAT_NUM_ERR_INTERVAL_3                                                                     0x3100ecUL //Access:RW   DataWidth:0x20   // Number of interval with error arrived to the DIF for protocol ID 3.
+#define TDIF_REG_STAT_NUM_ERR_INTERVAL_4_K2_E5                                                               0x3100f0UL //Access:RW   DataWidth:0x20   // Number of interval with error arrived to the DIF for protocol ID 4.
+#define TDIF_REG_STAT_NUM_ERR_INTERVAL_5_K2_E5                                                               0x3100f4UL //Access:RW   DataWidth:0x20   // Number of interval with error arrived to the DIF for protocol ID 5.
+#define TDIF_REG_STAT_NUM_ERR_INTERVAL_6_K2_E5                                                               0x3100f8UL //Access:RW   DataWidth:0x20   // Number of interval with error arrived to the DIF for protocol ID 6.
+#define TDIF_REG_STAT_NUM_ERR_INTERVAL_7_K2_E5                                                               0x3100fcUL //Access:RW   DataWidth:0x20   // Number of interval with error arrived to the DIF for protocol ID 7.
+#define TDIF_REG_INT_STS                                                                                     0x310180UL //Access:R    DataWidth:0x9    // Multi Field Register.
+  #define TDIF_REG_INT_STS_ADDRESS_ERROR                                                                     (0x1<<0) // Signals an unknown address to the rf module.
+  #define TDIF_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                               0
+  #define TDIF_REG_INT_STS_FATAL_DIX_ERR                                                                     (0x1<<1) // DIX data is missing or end of burst assived and not all DIX data was used.
+  #define TDIF_REG_INT_STS_FATAL_DIX_ERR_SHIFT                                                               1
+  #define TDIF_REG_INT_STS_FATAL_CONFIG_ERR                                                                  (0x1<<2) // Fatal configuration error due to illigal comdination of host interface, network interface, validate xxx and forward xxx.
+  #define TDIF_REG_INT_STS_FATAL_CONFIG_ERR_SHIFT                                                            2
+  #define TDIF_REG_INT_STS_CMD_FIFO_ERR                                                                      (0x1<<3) // Write to full FIFO or read from empty FIFO.
+  #define TDIF_REG_INT_STS_CMD_FIFO_ERR_SHIFT                                                                3
+  #define TDIF_REG_INT_STS_ORDER_FIFO_ERR                                                                    (0x1<<4) // Write to full FIFO or read from empty FIFO.
+  #define TDIF_REG_INT_STS_ORDER_FIFO_ERR_SHIFT                                                              4
+  #define TDIF_REG_INT_STS_RDATA_FIFO_ERR                                                                    (0x1<<5) // Write to full FIFO or read from empty FIFO.
+  #define TDIF_REG_INT_STS_RDATA_FIFO_ERR_SHIFT                                                              5
+  #define TDIF_REG_INT_STS_DIF_STOP_ERR                                                                      (0x1<<6) // If stop_on_error is set and the DIF block found error in the DIF/DIX data this interrupt will be asserted. The debug info is in debug_error_info.
+  #define TDIF_REG_INT_STS_DIF_STOP_ERR_SHIFT                                                                6
+  #define TDIF_REG_INT_STS_PARTIAL_DIF_W_EOB                                                                 (0x1<<7) // end of burst arrived with end of interval and only partial DIF data arrived.
+  #define TDIF_REG_INT_STS_PARTIAL_DIF_W_EOB_SHIFT                                                           7
+  #define TDIF_REG_INT_STS_L1_DIRTY_BIT_K2_E5                                                                (0x1<<8) // One of the command buffers has a pending L1 WB for more than MIN_EOB2WF_L1_RD_DEL (register) cycles.
+  #define TDIF_REG_INT_STS_L1_DIRTY_BIT_K2_E5_SHIFT                                                          8
+#define TDIF_REG_INT_MASK                                                                                    0x310184UL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define TDIF_REG_INT_MASK_ADDRESS_ERROR                                                                    (0x1<<0) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.ADDRESS_ERROR .
+  #define TDIF_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                              0
+  #define TDIF_REG_INT_MASK_FATAL_DIX_ERR                                                                    (0x1<<1) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.FATAL_DIX_ERR .
+  #define TDIF_REG_INT_MASK_FATAL_DIX_ERR_SHIFT                                                              1
+  #define TDIF_REG_INT_MASK_FATAL_CONFIG_ERR                                                                 (0x1<<2) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.FATAL_CONFIG_ERR .
+  #define TDIF_REG_INT_MASK_FATAL_CONFIG_ERR_SHIFT                                                           2
+  #define TDIF_REG_INT_MASK_CMD_FIFO_ERR                                                                     (0x1<<3) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.CMD_FIFO_ERR .
+  #define TDIF_REG_INT_MASK_CMD_FIFO_ERR_SHIFT                                                               3
+  #define TDIF_REG_INT_MASK_ORDER_FIFO_ERR                                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.ORDER_FIFO_ERR .
+  #define TDIF_REG_INT_MASK_ORDER_FIFO_ERR_SHIFT                                                             4
+  #define TDIF_REG_INT_MASK_RDATA_FIFO_ERR                                                                   (0x1<<5) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.RDATA_FIFO_ERR .
+  #define TDIF_REG_INT_MASK_RDATA_FIFO_ERR_SHIFT                                                             5
+  #define TDIF_REG_INT_MASK_DIF_STOP_ERR                                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.DIF_STOP_ERR .
+  #define TDIF_REG_INT_MASK_DIF_STOP_ERR_SHIFT                                                               6
+  #define TDIF_REG_INT_MASK_PARTIAL_DIF_W_EOB                                                                (0x1<<7) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.PARTIAL_DIF_W_EOB .
+  #define TDIF_REG_INT_MASK_PARTIAL_DIF_W_EOB_SHIFT                                                          7
+  #define TDIF_REG_INT_MASK_L1_DIRTY_BIT_K2_E5                                                               (0x1<<8) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.L1_DIRTY_BIT .
+  #define TDIF_REG_INT_MASK_L1_DIRTY_BIT_K2_E5_SHIFT                                                         8
+#define TDIF_REG_INT_STS_WR                                                                                  0x310188UL //Access:WR   DataWidth:0x9    // Multi Field Register.
+  #define TDIF_REG_INT_STS_WR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define TDIF_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                            0
+  #define TDIF_REG_INT_STS_WR_FATAL_DIX_ERR                                                                  (0x1<<1) // DIX data is missing or end of burst assived and not all DIX data was used.
+  #define TDIF_REG_INT_STS_WR_FATAL_DIX_ERR_SHIFT                                                            1
+  #define TDIF_REG_INT_STS_WR_FATAL_CONFIG_ERR                                                               (0x1<<2) // Fatal configuration error due to illigal comdination of host interface, network interface, validate xxx and forward xxx.
+  #define TDIF_REG_INT_STS_WR_FATAL_CONFIG_ERR_SHIFT                                                         2
+  #define TDIF_REG_INT_STS_WR_CMD_FIFO_ERR                                                                   (0x1<<3) // Write to full FIFO or read from empty FIFO.
+  #define TDIF_REG_INT_STS_WR_CMD_FIFO_ERR_SHIFT                                                             3
+  #define TDIF_REG_INT_STS_WR_ORDER_FIFO_ERR                                                                 (0x1<<4) // Write to full FIFO or read from empty FIFO.
+  #define TDIF_REG_INT_STS_WR_ORDER_FIFO_ERR_SHIFT                                                           4
+  #define TDIF_REG_INT_STS_WR_RDATA_FIFO_ERR                                                                 (0x1<<5) // Write to full FIFO or read from empty FIFO.
+  #define TDIF_REG_INT_STS_WR_RDATA_FIFO_ERR_SHIFT                                                           5
+  #define TDIF_REG_INT_STS_WR_DIF_STOP_ERR                                                                   (0x1<<6) // If stop_on_error is set and the DIF block found error in the DIF/DIX data this interrupt will be asserted. The debug info is in debug_error_info.
+  #define TDIF_REG_INT_STS_WR_DIF_STOP_ERR_SHIFT                                                             6
+  #define TDIF_REG_INT_STS_WR_PARTIAL_DIF_W_EOB                                                              (0x1<<7) // end of burst arrived with end of interval and only partial DIF data arrived.
+  #define TDIF_REG_INT_STS_WR_PARTIAL_DIF_W_EOB_SHIFT                                                        7
+  #define TDIF_REG_INT_STS_WR_L1_DIRTY_BIT_K2_E5                                                             (0x1<<8) // One of the command buffers has a pending L1 WB for more than MIN_EOB2WF_L1_RD_DEL (register) cycles.
+  #define TDIF_REG_INT_STS_WR_L1_DIRTY_BIT_K2_E5_SHIFT                                                       8
+#define TDIF_REG_INT_STS_CLR                                                                                 0x31018cUL //Access:RC   DataWidth:0x9    // Multi Field Register.
+  #define TDIF_REG_INT_STS_CLR_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define TDIF_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                           0
+  #define TDIF_REG_INT_STS_CLR_FATAL_DIX_ERR                                                                 (0x1<<1) // DIX data is missing or end of burst assived and not all DIX data was used.
+  #define TDIF_REG_INT_STS_CLR_FATAL_DIX_ERR_SHIFT                                                           1
+  #define TDIF_REG_INT_STS_CLR_FATAL_CONFIG_ERR                                                              (0x1<<2) // Fatal configuration error due to illigal comdination of host interface, network interface, validate xxx and forward xxx.
+  #define TDIF_REG_INT_STS_CLR_FATAL_CONFIG_ERR_SHIFT                                                        2
+  #define TDIF_REG_INT_STS_CLR_CMD_FIFO_ERR                                                                  (0x1<<3) // Write to full FIFO or read from empty FIFO.
+  #define TDIF_REG_INT_STS_CLR_CMD_FIFO_ERR_SHIFT                                                            3
+  #define TDIF_REG_INT_STS_CLR_ORDER_FIFO_ERR                                                                (0x1<<4) // Write to full FIFO or read from empty FIFO.
+  #define TDIF_REG_INT_STS_CLR_ORDER_FIFO_ERR_SHIFT                                                          4
+  #define TDIF_REG_INT_STS_CLR_RDATA_FIFO_ERR                                                                (0x1<<5) // Write to full FIFO or read from empty FIFO.
+  #define TDIF_REG_INT_STS_CLR_RDATA_FIFO_ERR_SHIFT                                                          5
+  #define TDIF_REG_INT_STS_CLR_DIF_STOP_ERR                                                                  (0x1<<6) // If stop_on_error is set and the DIF block found error in the DIF/DIX data this interrupt will be asserted. The debug info is in debug_error_info.
+  #define TDIF_REG_INT_STS_CLR_DIF_STOP_ERR_SHIFT                                                            6
+  #define TDIF_REG_INT_STS_CLR_PARTIAL_DIF_W_EOB                                                             (0x1<<7) // end of burst arrived with end of interval and only partial DIF data arrived.
+  #define TDIF_REG_INT_STS_CLR_PARTIAL_DIF_W_EOB_SHIFT                                                       7
+  #define TDIF_REG_INT_STS_CLR_L1_DIRTY_BIT_K2_E5                                                            (0x1<<8) // One of the command buffers has a pending L1 WB for more than MIN_EOB2WF_L1_RD_DEL (register) cycles.
+  #define TDIF_REG_INT_STS_CLR_L1_DIRTY_BIT_K2_E5_SHIFT                                                      8
+#define TDIF_REG_PRTY_MASK                                                                                   0x310194UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define TDIF_REG_PRTY_MASK_DATAPATH_REGISTERS                                                              (0x1<<1) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS.DATAPATH_REGISTERS .
+  #define TDIF_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                                        1
+#define TDIF_REG_PRTY_MASK_H_0_BB_K2                                                                         0x310204UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define TDIF_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_BB_K2                                                   (0x1<<0) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT .
+  #define TDIF_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_BB_K2_SHIFT                                             0
+  #define TDIF_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_BB_K2                                                   (0x1<<1) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM009_I_ECC_RF_INT .
+  #define TDIF_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_BB_K2_SHIFT                                             1
+  #define TDIF_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT_BB_K2                                                   (0x1<<2) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM010_I_ECC_RF_INT .
+  #define TDIF_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT_BB_K2_SHIFT                                             2
+  #define TDIF_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT_BB_K2                                                   (0x1<<3) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM011_I_ECC_RF_INT .
+  #define TDIF_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT_BB_K2_SHIFT                                             3
+  #define TDIF_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                     (0x1<<4) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define TDIF_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                               4
+  #define TDIF_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                     (0x1<<5) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define TDIF_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                               5
+  #define TDIF_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                     (0x1<<6) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define TDIF_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                               6
+  #define TDIF_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2                                                     (0x1<<7) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define TDIF_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2_SHIFT                                               7
+  #define TDIF_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2                                                     (0x1<<8) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define TDIF_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2_SHIFT                                               8
+  #define TDIF_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2                                                     (0x1<<9) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define TDIF_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2_SHIFT                                               9
+  #define TDIF_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                     (0x1<<10) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define TDIF_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                               10
+#define TDIF_REG_MEM_ECC_ENABLE_0_BB_K2                                                                      0x310210UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define TDIF_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_BB_K2                                                    (0x1<<0) // Enable ECC for memory ecc instance tdif.i_tdif_l1_sector0_mem.i_ecc in module tdif_l1_sector0_mem
+  #define TDIF_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_BB_K2_SHIFT                                              0
+  #define TDIF_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_EN_BB_K2                                                    (0x1<<1) // Enable ECC for memory ecc instance tdif.i_tdif_l1_sector4_mem.i_ecc in module tdif_l1_sector4_mem
+  #define TDIF_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_EN_BB_K2_SHIFT                                              1
+  #define TDIF_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_EN_BB_K2                                                    (0x1<<2) // Enable ECC for memory ecc instance tdif.i_tdif_l1_sector5_mem.i_ecc in module tdif_l1_sector5_mem
+  #define TDIF_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_EN_BB_K2_SHIFT                                              2
+  #define TDIF_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_EN_BB_K2                                                    (0x1<<3) // Enable ECC for memory ecc instance tdif.i_tdif_l1_sector6_mem.i_ecc in module tdif_l1_sector6_mem
+  #define TDIF_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_EN_BB_K2_SHIFT                                              3
+#define TDIF_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                 0x310214UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define TDIF_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_BB_K2                                             (0x1<<0) // Set parity only for memory ecc instance tdif.i_tdif_l1_sector0_mem.i_ecc in module tdif_l1_sector0_mem
+  #define TDIF_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_BB_K2_SHIFT                                       0
+  #define TDIF_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_PRTY_BB_K2                                             (0x1<<1) // Set parity only for memory ecc instance tdif.i_tdif_l1_sector4_mem.i_ecc in module tdif_l1_sector4_mem
+  #define TDIF_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_PRTY_BB_K2_SHIFT                                       1
+  #define TDIF_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_PRTY_BB_K2                                             (0x1<<2) // Set parity only for memory ecc instance tdif.i_tdif_l1_sector5_mem.i_ecc in module tdif_l1_sector5_mem
+  #define TDIF_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_PRTY_BB_K2_SHIFT                                       2
+  #define TDIF_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_PRTY_BB_K2                                             (0x1<<3) // Set parity only for memory ecc instance tdif.i_tdif_l1_sector6_mem.i_ecc in module tdif_l1_sector6_mem
+  #define TDIF_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_PRTY_BB_K2_SHIFT                                       3
+#define TDIF_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                             0x310218UL //Access:RC   DataWidth:0x4    // Multi Field Register.
+  #define TDIF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_BB_K2                                      (0x1<<0) // Record if a correctable error occurred on memory ecc instance tdif.i_tdif_l1_sector0_mem.i_ecc in module tdif_l1_sector0_mem
+  #define TDIF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_BB_K2_SHIFT                                0
+  #define TDIF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_CORRECT_BB_K2                                      (0x1<<1) // Record if a correctable error occurred on memory ecc instance tdif.i_tdif_l1_sector4_mem.i_ecc in module tdif_l1_sector4_mem
+  #define TDIF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_CORRECT_BB_K2_SHIFT                                1
+  #define TDIF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_CORRECT_BB_K2                                      (0x1<<2) // Record if a correctable error occurred on memory ecc instance tdif.i_tdif_l1_sector5_mem.i_ecc in module tdif_l1_sector5_mem
+  #define TDIF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_CORRECT_BB_K2_SHIFT                                2
+  #define TDIF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_CORRECT_BB_K2                                      (0x1<<3) // Record if a correctable error occurred on memory ecc instance tdif.i_tdif_l1_sector6_mem.i_ecc in module tdif_l1_sector6_mem
+  #define TDIF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_CORRECT_BB_K2_SHIFT                                3
+#define TDIF_REG_MEM_ECC_EVENTS_BB_K2                                                                        0x31021cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define TDIF_REG_DEBUG_ERROR_INFO                                                                            0x310400UL //Access:R    DataWidth:0x20   // Information on the first 8 DIF errors found. In bits [5:3] of the address represent the error number (0-7). Do not read from address[3:5]=i if debug_error_data_valid[i] isn't set. Bits [2:0] in the address will contain the following data: address[2:0] = 0 - [31:0] calculated reference tag; address[2:0] = 1 - [15:0] calculated application tag; [31:0]; calculated CRC/checksum; address[2:0] = 2 - [31:0] expected reference tag; address[2:0] = 3 - [15:0] expected application tag; [31:0] expected CRC/checksum; address[2:0] = 4 - [31:0] the interval number the error occurred; address[2:0] = 5 - [31:0] TID address[2:0] = 6 - [3:0] - type; [12:4] - LTID; [15:13] protocol ID; [16] set ID; [18:17] host interface; [19] network interface; [22:20] error type ([0] - CRC/checksum; [1] application tag; [2] reference tag); [31:23] reserved; address[2:0] = 7 - reserved.
+#define TDIF_REG_DEBUG_ERROR_INFO_SIZE                                                                       64
+#define TDIF_REG_DBG_SELECT                                                                                  0x310500UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define TDIF_REG_DBG_DWORD_ENABLE                                                                            0x310504UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define TDIF_REG_DBG_SHIFT                                                                                   0x310508UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define TDIF_REG_DBG_FORCE_VALID                                                                             0x31050cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define TDIF_REG_DBG_FORCE_FRAME                                                                             0x310510UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define TDIF_REG_DBG_OUT_DATA                                                                                0x310520UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define TDIF_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define TDIF_REG_DBG_OUT_VALID                                                                               0x310540UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define TDIF_REG_DBG_OUT_FRAME                                                                               0x310544UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define TDIF_REG_L1_TASK_CONTEXT                                                                             0x318000UL //Access:WB   DataWidth:0x40   // Task context memory. for TDIF Only 320b are valid. Data order:Field name-Initial reference tag Address offset-0 bits [31:0]; Field name-Application tag value Address offset-0 bits [47:32]; Field name-Application tag mask Address offset-0 bits [63:48]; Field name-Partial CRC value B Address offset-1 bits [15:0]; Field name-Partial checksum value B Address offset-1 bits [31:16]; Field name-Received DIF bytes left B Address offset-1 bits [35:32]; Field name-Transmitted DIF bytes B Address offset-1 bits [39:36]; Field name-Error in IO B Address offset-1 bits [40:40]; Field name-Checksum overflow B Address offset-1 bits [41]; Field name-Reserved Address offset-1  [55:42]; Field name-Ignore application tag for guard  Address offset-1 bits [56]; Field name-Initial reference tag valid  Address offset-1 bits [57]; Field name-Host Guard type Address offset-1 bits [58]; Field name-Set error with EOP Address offset-1 bits [59]; Field name-Protection type Address offset-1 bits [60]; Field name-CRC seed  Address offset-1 bits [62]; Field name-Reserved  Address offset-1 bits [63]; Field name-Validate guard Address offset-2 bits [0]; Field name-Validate application tag Address offset-2 bits [1]; Field name-Validate  reference tag Address offset-2 bits [2]; Field name-Forward guard  Address offset-2 bits [3]; Field name-Forward application tag  Address offset-2 bits [4]; Field name-Forward reference tag  Address offset-2 bits [5]; Field name-Interval size Address offset-2 bits [8:6]; Field name-Host interface Address offset-2 bits [10:9]; Field name-DIX block size Address offset-2 bits [12:11]; Field name-Network Interface  Address offset-2 bits [13]; Field name-Received DIF bytes left A Address offset-2 bits [17:14]; Field name-Transmitted DIF bytes A Address offset-2 bits [21:18]; Field name-Error in IO A Address offset-2 bits [22:22]; Field name-Checksum overflow A Address offset-2 bits [23]; Field name-Reserved Address offset-2 bits [31:24]; Field name-Offset in IO B Address offset-2 bits [63:32]; Field name-Partial CRC value A Address offset-3 bits [15:0]; Field name-Partial checksum value A Address offset-3 bits [31:16]; Field name-Offset in IO A Address offset-3 bits [63:32]; Field name-Partial DIF data A Address offset-4 bits [63:0]; Field name-Partial DIF data B Address offset-5 bits [63:0].  Address offset-6 and 7 - reserved. all reserved fields are un reachable for write and return zero on read. Address offset is in QWORD resolution.
+#define TDIF_REG_L1_TASK_CONTEXT_SIZE                                                                        5120
+#define RGSRC_REG_DBG_SELECT_E5                                                                              0x320040UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define RGSRC_REG_DBG_DWORD_ENABLE_E5                                                                        0x320044UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define RGSRC_REG_DBG_SHIFT_E5                                                                               0x320048UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define RGSRC_REG_DBG_FORCE_VALID_E5                                                                         0x32004cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define RGSRC_REG_DBG_FORCE_FRAME_E5                                                                         0x320050UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define RGSRC_REG_DBG_OUT_DATA_E5                                                                            0x320060UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define RGSRC_REG_DBG_OUT_DATA_SIZE                                                                          8
+#define RGSRC_REG_DBG_OUT_VALID_E5                                                                           0x320080UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define RGSRC_REG_DBG_OUT_FRAME_E5                                                                           0x320084UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define RGSRC_REG_INT_STS_E5                                                                                 0x320180UL //Access:R    DataWidth:0x1    // Multi Field Register.
+  #define RGSRC_REG_INT_STS_ADDRESS_ERROR_E5                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define RGSRC_REG_INT_STS_ADDRESS_ERROR_E5_SHIFT                                                           0
+#define RGSRC_REG_INT_MASK_E5                                                                                0x320184UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define RGSRC_REG_INT_MASK_ADDRESS_ERROR_E5                                                                (0x1<<0) // This bit masks, when set, the Interrupt bit: RGSRC_REG_INT_STS.ADDRESS_ERROR .
+  #define RGSRC_REG_INT_MASK_ADDRESS_ERROR_E5_SHIFT                                                          0
+#define RGSRC_REG_INT_STS_WR_E5                                                                              0x320188UL //Access:WR   DataWidth:0x1    // Multi Field Register.
+  #define RGSRC_REG_INT_STS_WR_ADDRESS_ERROR_E5                                                              (0x1<<0) // Signals an unknown address to the rf module.
+  #define RGSRC_REG_INT_STS_WR_ADDRESS_ERROR_E5_SHIFT                                                        0
+#define RGSRC_REG_INT_STS_CLR_E5                                                                             0x32018cUL //Access:RC   DataWidth:0x1    // Multi Field Register.
+  #define RGSRC_REG_INT_STS_CLR_ADDRESS_ERROR_E5                                                             (0x1<<0) // Signals an unknown address to the rf module.
+  #define RGSRC_REG_INT_STS_CLR_ADDRESS_ERROR_E5_SHIFT                                                       0
+#define RGSRC_REG_ECO_RESERVED_E5                                                                            0x320200UL //Access:RW   DataWidth:0x8    // Chicken bits.
+#define RGSRC_REG_CACHE_EN_E5                                                                                0x320400UL //Access:RW   DataWidth:0x1    // Enable cache functionality.
+#define RGSRC_REG_WAIT4WDONE_E5                                                                              0x320404UL //Access:RW   DataWidth:0x1    // Wait for write done before sending removing the fencing of a new DEL/ADD/CHG command
+#define RGSRC_REG_MAX_HOPS_EN_E5                                                                             0x320408UL //Access:RW   DataWidth:0x1    // Stop searching when MAX HOPs is reached
+#define RGSRC_REG_MAX_HOPS_E5                                                                                0x32040cUL //Access:RW   DataWidth:0x8    // Number of HOPs, when reached, stop the searching
+#define RGSRC_REG_HASH_BIN_BIT_W_E5                                                                          0x320410UL //Access:RW   DataWidth:0x5    // Number of MSB hash bits to be used for bin
+#define RGSRC_REG_TABLE_T1_ENTRY_SIZE_E5                                                                     0x320418UL //Access:RW   DataWidth:0x20   // Size of T1 table entry in 16-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_qreg_granularity(16 + N*HASH/8 + N*16*RF_GSRC_CTX_SIZE)              if HASH is not aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_qreg_granularity(16 + N*8*round_up(HASH/64));   (N - integer number) (HASH is written in bits)
+#define RGSRC_REG_TABLE_T2_ENTRY_SIZE_E5                                                                     0x32041cUL //Access:RW   DataWidth:0x20   // Size of T2 table entry in 16-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_qreg_granularity(16 + N*HASH/8 + N*16*RF_GSRC_CTX_SIZE)               if HASH is not aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_qreg_granularity(16 + N*8*round_up(HASH/64));                    (N - integer number)              (HASH is written in bits)
+#define RGSRC_REG_PXP_CTRL_E5                                                                                0x320420UL //Access:RW   DataWidth:0x15   // Multi Field Register.
+  #define RGSRC_REG_PXP_CTRL_VQID_E5                                                                         (0x1f<<0) // Controls PXP Request VQID Field
+  #define RGSRC_REG_PXP_CTRL_VQID_E5_SHIFT                                                                   0
+  #define RGSRC_REG_PXP_CTRL_TPH_VALID_E5                                                                    (0x1<<5) // Controls PXP Request TPH valid Field
+  #define RGSRC_REG_PXP_CTRL_TPH_VALID_E5_SHIFT                                                              5
+  #define RGSRC_REG_PXP_CTRL_TPH_HINT_E5                                                                     (0x3<<6) // Controls PXP Request TPH hint Field
+  #define RGSRC_REG_PXP_CTRL_TPH_HINT_E5_SHIFT                                                               6
+  #define RGSRC_REG_PXP_CTRL_TPH_INDEX_E5                                                                    (0x1ff<<8) // Controls PXP Request TPH index Field
+  #define RGSRC_REG_PXP_CTRL_TPH_INDEX_E5_SHIFT                                                              8
+  #define RGSRC_REG_PXP_CTRL_ENDIANITY_E5                                                                    (0x3<<17) // Controls PXP Request endianity Field
+  #define RGSRC_REG_PXP_CTRL_ENDIANITY_E5_SHIFT                                                              17
+  #define RGSRC_REG_PXP_CTRL_WAIT4EOP_E5                                                                     (0x1<<19) // Controls PXP Request wait4eop Field
+  #define RGSRC_REG_PXP_CTRL_WAIT4EOP_E5_SHIFT                                                               19
+  #define RGSRC_REG_PXP_CTRL_DONE_TYPE_E5                                                                    (0x1<<20) // Controls PXP Request done type Field
+  #define RGSRC_REG_PXP_CTRL_DONE_TYPE_E5_SHIFT                                                              20
+#define RGSRC_REG_PXP_REQ_CREDIT_E5                                                                          0x320424UL //Access:RW   DataWidth:0x2    // PXP request intial credits.
+#define RGSRC_REG_CFC_REQ_CREDIT_E5                                                                          0x320428UL //Access:RW   DataWidth:0x4    // CFC request intial credits.
+#define RGSRC_REG_NUM_INHOUSE_CMD_E5                                                                         0x32042cUL //Access:R    DataWidth:0x7    // Number of commands which are currently occupy GSRC FIFO
+#define RGSRC_REG_WAS_ERROR_E5                                                                               0x320430UL //Access:RW   DataWidth:0x8    // Command was found with error. [0] - SRC cmd result in no match; [1] - DEL cmd result in no match; [2] - CHG cmd result in no match; [3] - ADD cmd result in no match; [4] - ADD cmd already exist; [5] - MAX hops reached; [6] - Magic number error; [7] - PCIe error
+#define RGSRC_REG_NUM_SRC_CMD_E5                                                                             0x320434UL //Access:RC   DataWidth:0x20   // Number of src commands which were recieved by GSRC
+#define RGSRC_REG_NUM_NON_SRC_CMD_E5                                                                         0x320438UL //Access:RC   DataWidth:0x20   // Number of ADD/DEL/CHG commands which were recieved by GSRC
+#define RGSRC_REG_NUM_PXP_RD_REQ_E5                                                                          0x32043cUL //Access:RC   DataWidth:0x20   // Number of PXP read requests which were sent
+#define RGSRC_REG_NUM_PXP_RD_DONE_E5                                                                         0x320440UL //Access:RC   DataWidth:0x20   // Number of PXP read done which were recieved
+#define RGSRC_REG_NUM_PXP_WR_REQ_E5                                                                          0x320444UL //Access:RC   DataWidth:0x20   // Number of PXP write requests which were sent
+#define RGSRC_REG_NUM_PXP_WR_DONE_E5                                                                         0x320448UL //Access:RC   DataWidth:0x20   // Number of PXP write done which were recieved
+#define RGSRC_REG_NUM_SRC_CMD_HIT_HOP_1_E5                                                                   0x32044cUL //Access:RC   DataWidth:0x20   // Number of SRC commands which hit with HOP=1
+#define RGSRC_REG_NUM_SRC_CMD_HIT_HOP_2_E5                                                                   0x320450UL //Access:RC   DataWidth:0x20   // Number of SRC commands which hit with HOP=2
+#define RGSRC_REG_NUM_SRC_CMD_HIT_HOP_3_OR_MORE_E5                                                           0x320454UL //Access:RC   DataWidth:0x20   // Number of SRC commands which hit with HOP=3 or more
+#define TGSRC_REG_DBG_SELECT_E5                                                                              0x322040UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define TGSRC_REG_DBG_DWORD_ENABLE_E5                                                                        0x322044UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define TGSRC_REG_DBG_SHIFT_E5                                                                               0x322048UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define TGSRC_REG_DBG_FORCE_VALID_E5                                                                         0x32204cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define TGSRC_REG_DBG_FORCE_FRAME_E5                                                                         0x322050UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define TGSRC_REG_DBG_OUT_DATA_E5                                                                            0x322060UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define TGSRC_REG_DBG_OUT_DATA_SIZE                                                                          8
+#define TGSRC_REG_DBG_OUT_VALID_E5                                                                           0x322080UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define TGSRC_REG_DBG_OUT_FRAME_E5                                                                           0x322084UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define TGSRC_REG_INT_STS_E5                                                                                 0x322180UL //Access:R    DataWidth:0x1    // Multi Field Register.
+  #define TGSRC_REG_INT_STS_ADDRESS_ERROR_E5                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define TGSRC_REG_INT_STS_ADDRESS_ERROR_E5_SHIFT                                                           0
+#define TGSRC_REG_INT_MASK_E5                                                                                0x322184UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define TGSRC_REG_INT_MASK_ADDRESS_ERROR_E5                                                                (0x1<<0) // This bit masks, when set, the Interrupt bit: TGSRC_REG_INT_STS.ADDRESS_ERROR .
+  #define TGSRC_REG_INT_MASK_ADDRESS_ERROR_E5_SHIFT                                                          0
+#define TGSRC_REG_INT_STS_WR_E5                                                                              0x322188UL //Access:WR   DataWidth:0x1    // Multi Field Register.
+  #define TGSRC_REG_INT_STS_WR_ADDRESS_ERROR_E5                                                              (0x1<<0) // Signals an unknown address to the rf module.
+  #define TGSRC_REG_INT_STS_WR_ADDRESS_ERROR_E5_SHIFT                                                        0
+#define TGSRC_REG_INT_STS_CLR_E5                                                                             0x32218cUL //Access:RC   DataWidth:0x1    // Multi Field Register.
+  #define TGSRC_REG_INT_STS_CLR_ADDRESS_ERROR_E5                                                             (0x1<<0) // Signals an unknown address to the rf module.
+  #define TGSRC_REG_INT_STS_CLR_ADDRESS_ERROR_E5_SHIFT                                                       0
+#define TGSRC_REG_ECO_RESERVED_E5                                                                            0x322200UL //Access:RW   DataWidth:0x8    // Chicken bits.
+#define TGSRC_REG_CACHE_EN_E5                                                                                0x322400UL //Access:RW   DataWidth:0x1    // Enable cache functionality.
+#define TGSRC_REG_WAIT4WDONE_E5                                                                              0x322404UL //Access:RW   DataWidth:0x1    // Wait for write done before sending removing the fencing of a new DEL/ADD/CHG command
+#define TGSRC_REG_MAX_HOPS_EN_E5                                                                             0x322408UL //Access:RW   DataWidth:0x1    // Stop searching when MAX HOPs is reached
+#define TGSRC_REG_MAX_HOPS_E5                                                                                0x32240cUL //Access:RW   DataWidth:0x8    // Number of HOPs, when reached, stop the searching
+#define TGSRC_REG_HASH_BIN_BIT_W_E5                                                                          0x322410UL //Access:RW   DataWidth:0x5    // Number of MSB hash bits to be used for bin
+#define TGSRC_REG_TABLE_T1_ENTRY_SIZE_E5                                                                     0x322418UL //Access:RW   DataWidth:0x20   // Size of T1 table entry in 16-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_qreg_granularity(16 + N*HASH/8 + N*16*RF_GSRC_CTX_SIZE)              if HASH is not aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_qreg_granularity(16 + N*8*round_up(HASH/64));   (N - integer number) (HASH is written in bits)
+#define TGSRC_REG_TABLE_T2_ENTRY_SIZE_E5                                                                     0x32241cUL //Access:RW   DataWidth:0x20   // Size of T2 table entry in 16-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_qreg_granularity(16 + N*HASH/8 + N*16*RF_GSRC_CTX_SIZE)               if HASH is not aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_qreg_granularity(16 + N*8*round_up(HASH/64));                    (N - integer number)              (HASH is written in bits)
+#define TGSRC_REG_PXP_CTRL_E5                                                                                0x322420UL //Access:RW   DataWidth:0x15   // Multi Field Register.
+  #define TGSRC_REG_PXP_CTRL_VQID_E5                                                                         (0x1f<<0) // Controls PXP Request VQID Field
+  #define TGSRC_REG_PXP_CTRL_VQID_E5_SHIFT                                                                   0
+  #define TGSRC_REG_PXP_CTRL_TPH_VALID_E5                                                                    (0x1<<5) // Controls PXP Request TPH valid Field
+  #define TGSRC_REG_PXP_CTRL_TPH_VALID_E5_SHIFT                                                              5
+  #define TGSRC_REG_PXP_CTRL_TPH_HINT_E5                                                                     (0x3<<6) // Controls PXP Request TPH hint Field
+  #define TGSRC_REG_PXP_CTRL_TPH_HINT_E5_SHIFT                                                               6
+  #define TGSRC_REG_PXP_CTRL_TPH_INDEX_E5                                                                    (0x1ff<<8) // Controls PXP Request TPH index Field
+  #define TGSRC_REG_PXP_CTRL_TPH_INDEX_E5_SHIFT                                                              8
+  #define TGSRC_REG_PXP_CTRL_ENDIANITY_E5                                                                    (0x3<<17) // Controls PXP Request endianity Field
+  #define TGSRC_REG_PXP_CTRL_ENDIANITY_E5_SHIFT                                                              17
+  #define TGSRC_REG_PXP_CTRL_WAIT4EOP_E5                                                                     (0x1<<19) // Controls PXP Request wait4eop Field
+  #define TGSRC_REG_PXP_CTRL_WAIT4EOP_E5_SHIFT                                                               19
+  #define TGSRC_REG_PXP_CTRL_DONE_TYPE_E5                                                                    (0x1<<20) // Controls PXP Request done type Field
+  #define TGSRC_REG_PXP_CTRL_DONE_TYPE_E5_SHIFT                                                              20
+#define TGSRC_REG_PXP_REQ_CREDIT_E5                                                                          0x322424UL //Access:RW   DataWidth:0x2    // PXP request intial credits.
+#define TGSRC_REG_CFC_REQ_CREDIT_E5                                                                          0x322428UL //Access:RW   DataWidth:0x4    // CFC request intial credits.
+#define TGSRC_REG_NUM_INHOUSE_CMD_E5                                                                         0x32242cUL //Access:R    DataWidth:0x7    // Number of commands which are currently occupy GSRC FIFO
+#define TGSRC_REG_WAS_ERROR_E5                                                                               0x322430UL //Access:RW   DataWidth:0x8    // Command was found with error. [0] - SRC cmd result in no match; [1] - DEL cmd result in no match; [2] - CHG cmd result in no match; [3] - ADD cmd result in no match; [4] - ADD cmd already exist; [5] - MAX hops reached; [6] - Magic number error; [7] - PCIe error
+#define TGSRC_REG_NUM_SRC_CMD_E5                                                                             0x322434UL //Access:RC   DataWidth:0x20   // Number of src commands which were recieved by GSRC
+#define TGSRC_REG_NUM_NON_SRC_CMD_E5                                                                         0x322438UL //Access:RC   DataWidth:0x20   // Number of ADD/DEL/CHG commands which were recieved by GSRC
+#define TGSRC_REG_NUM_PXP_RD_REQ_E5                                                                          0x32243cUL //Access:RC   DataWidth:0x20   // Number of PXP read requests which were sent
+#define TGSRC_REG_NUM_PXP_RD_DONE_E5                                                                         0x322440UL //Access:RC   DataWidth:0x20   // Number of PXP read done which were recieved
+#define TGSRC_REG_NUM_PXP_WR_REQ_E5                                                                          0x322444UL //Access:RC   DataWidth:0x20   // Number of PXP write requests which were sent
+#define TGSRC_REG_NUM_PXP_WR_DONE_E5                                                                         0x322448UL //Access:RC   DataWidth:0x20   // Number of PXP write done which were recieved
+#define TGSRC_REG_NUM_SRC_CMD_HIT_HOP_1_E5                                                                   0x32244cUL //Access:RC   DataWidth:0x20   // Number of SRC commands which hit with HOP=1
+#define TGSRC_REG_NUM_SRC_CMD_HIT_HOP_2_E5                                                                   0x322450UL //Access:RC   DataWidth:0x20   // Number of SRC commands which hit with HOP=2
+#define TGSRC_REG_NUM_SRC_CMD_HIT_HOP_3_OR_MORE_E5                                                           0x322454UL //Access:RC   DataWidth:0x20   // Number of SRC commands which hit with HOP=3 or more
+#define BRB_REG_HW_INIT_EN                                                                                   0x340004UL //Access:RW   DataWidth:0x2    // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en registers will be done by HW.  Bit 1 - if this bit is set then initialization of BIG RAM will be done by HW. Both bits will be reset by HW when initialization is finished.
+#define BRB_REG_INIT_DONE                                                                                    0x340008UL //Access:R    DataWidth:0x2    // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en registers are finished by HW.  Bit 1 - if this bit is set then initialization of BIG RAM is finished by HW.
+#define BRB_REG_START_EN                                                                                     0x34000cUL //Access:RW   DataWidth:0x1    // This bit should be set when initialization of all BRTB registers and memories is finished. BRTB will fill all prefetch FIFO with free pointers. BRTB will not be able to get packets from write clients when this bit is reset. If link list was configured by HW then this bit will be set by HW.
+#define BRB_REG_INT_STS_0                                                                                    0x3400c0UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define BRB_REG_INT_STS_0_ADDRESS_ERROR                                                                    (0x1<<0) // Signals an unknown address to the rf module.
+  #define BRB_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                              0
+  #define BRB_REG_INT_STS_0_RC_PKT0_RLS_ERROR                                                                (0x1<<1) // Read packet client PRM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_0_RC_PKT0_RLS_ERROR_SHIFT                                                          1
+  #define BRB_REG_INT_STS_0_RC_PKT0_1ST_ERROR                                                                (0x1<<2) // Read packet client PRM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR0/PRM/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_0_RC_PKT0_1ST_ERROR_SHIFT                                                          2
+  #define BRB_REG_INT_STS_0_RC_PKT0_LEN_ERROR                                                                (0x1<<3) // Read packet client PRM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_0_RC_PKT0_LEN_ERROR_SHIFT                                                          3
+  #define BRB_REG_INT_STS_0_RC_PKT0_MIDDLE_ERROR                                                             (0x1<<4) // Read packet client PRM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR0/PRM/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_0_RC_PKT0_MIDDLE_ERROR_SHIFT                                                       4
+  #define BRB_REG_INT_STS_0_RC_PKT0_PROTOCOL_ERROR                                                           (0x1<<5) // Read packet client PRM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_0_RC_PKT0_PROTOCOL_ERROR_SHIFT                                                     5
+  #define BRB_REG_INT_STS_0_RC_PKT1_RLS_ERROR                                                                (0x1<<6) // Read packet client MSDM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_0_RC_PKT1_RLS_ERROR_SHIFT                                                          6
+  #define BRB_REG_INT_STS_0_RC_PKT1_1ST_ERROR                                                                (0x1<<7) // Read packet client MSDM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR1/MSDM/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_0_RC_PKT1_1ST_ERROR_SHIFT                                                          7
+  #define BRB_REG_INT_STS_0_RC_PKT1_LEN_ERROR                                                                (0x1<<8) // Read packet client MSDM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_0_RC_PKT1_LEN_ERROR_SHIFT                                                          8
+  #define BRB_REG_INT_STS_0_RC_PKT1_MIDDLE_ERROR                                                             (0x1<<9) // Read packet client MSDM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR1/MSDM/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_0_RC_PKT1_MIDDLE_ERROR_SHIFT                                                       9
+  #define BRB_REG_INT_STS_0_RC_PKT1_PROTOCOL_ERROR                                                           (0x1<<10) // Read packet client MSDM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_0_RC_PKT1_PROTOCOL_ERROR_SHIFT                                                     10
+  #define BRB_REG_INT_STS_0_RC_PKT2_RLS_ERROR                                                                (0x1<<11) // Read packet client TSDM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_0_RC_PKT2_RLS_ERROR_SHIFT                                                          11
+  #define BRB_REG_INT_STS_0_RC_PKT2_1ST_ERROR                                                                (0x1<<12) // Read packet client TSDM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR2/TSDM/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_0_RC_PKT2_1ST_ERROR_SHIFT                                                          12
+  #define BRB_REG_INT_STS_0_RC_PKT2_LEN_ERROR                                                                (0x1<<13) // Read packet client TSDM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_0_RC_PKT2_LEN_ERROR_SHIFT                                                          13
+  #define BRB_REG_INT_STS_0_RC_PKT2_MIDDLE_ERROR                                                             (0x1<<14) // Read packet client TSDM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR2/TSDM/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_0_RC_PKT2_MIDDLE_ERROR_SHIFT                                                       14
+  #define BRB_REG_INT_STS_0_RC_PKT2_PROTOCOL_ERROR                                                           (0x1<<15) // Read packet client TSDM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_0_RC_PKT2_PROTOCOL_ERROR_SHIFT                                                     15
+  #define BRB_REG_INT_STS_0_RC_PKT3_RLS_ERROR                                                                (0x1<<16) // Read packet client parser release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_0_RC_PKT3_RLS_ERROR_SHIFT                                                          16
+  #define BRB_REG_INT_STS_0_RC_PKT3_1ST_ERROR                                                                (0x1<<17) // Read packet client parser first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_0_RC_PKT3_1ST_ERROR_SHIFT                                                          17
+  #define BRB_REG_INT_STS_0_RC_PKT3_LEN_ERROR                                                                (0x1<<18) // Read packet client parser length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_0_RC_PKT3_LEN_ERROR_SHIFT                                                          18
+  #define BRB_REG_INT_STS_0_RC_PKT3_MIDDLE_ERROR                                                             (0x1<<19) // Read packet client parser error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_0_RC_PKT3_MIDDLE_ERROR_SHIFT                                                       19
+  #define BRB_REG_INT_STS_0_RC_PKT3_PROTOCOL_ERROR                                                           (0x1<<20) // Read packet client parser error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_0_RC_PKT3_PROTOCOL_ERROR_SHIFT                                                     20
+  #define BRB_REG_INT_STS_0_RC_SOP_REQ_TC_PORT_ERROR                                                         (0x1<<21) // SOP descriptor request from empty TC or port.
+  #define BRB_REG_INT_STS_0_RC_SOP_REQ_TC_PORT_ERROR_SHIFT                                                   21
+  #define BRB_REG_INT_STS_0_UNCOMPLIENT_LOSSLESS_ERROR                                                       (0x1<<22) // One of uncoplient lossless counters is bigger than threshold PAUSE_EN::/PAUSE_EN/d in Comments.
+  #define BRB_REG_INT_STS_0_UNCOMPLIENT_LOSSLESS_ERROR_SHIFT                                                 22
+  #define BRB_REG_INT_STS_0_WC0_PROTOCOL_ERROR                                                               (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
+  #define BRB_REG_INT_STS_0_WC0_PROTOCOL_ERROR_SHIFT                                                         23
+  #define BRB_REG_INT_STS_0_WC1_PROTOCOL_ERROR                                                               (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 1 RX_INT ::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_0_WC1_PROTOCOL_ERROR_SHIFT                                                         24
+  #define BRB_REG_INT_STS_0_WC2_PROTOCOL_ERROR                                                               (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 2 RX_INT ::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_0_WC2_PROTOCOL_ERROR_SHIFT                                                         25
+  #define BRB_REG_INT_STS_0_WC3_PROTOCOL_ERROR                                                               (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 3 RX_INT ::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_0_WC3_PROTOCOL_ERROR_SHIFT                                                         26
+  #define BRB_REG_INT_STS_0_LL_ARB_PREFETCH_SOP_ERROR                                                        (0x1<<27) // Link list arbiter prefetch SOP error RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_0_LL_ARB_PREFETCH_SOP_ERROR_SHIFT                                                  27
+  #define BRB_REG_INT_STS_0_LL_BLK_ERROR                                                                     (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
+  #define BRB_REG_INT_STS_0_LL_BLK_ERROR_SHIFT                                                               28
+  #define BRB_REG_INT_STS_0_PACKET_COUNTER_ERROR                                                             (0x1<<29) // Packet counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_0_PACKET_COUNTER_ERROR_SHIFT                                                       29
+  #define BRB_REG_INT_STS_0_BYTE_COUNTER_ERROR                                                               (0x1<<30) // Byte counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_0_BYTE_COUNTER_ERROR_SHIFT                                                         30
+  #define BRB_REG_INT_STS_0_MAC0_FC_CNT_ERROR                                                                (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_0_MAC0_FC_CNT_ERROR_SHIFT                                                          31
+#define BRB_REG_INT_MASK_0                                                                                   0x3400c4UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define BRB_REG_INT_MASK_0_ADDRESS_ERROR                                                                   (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.ADDRESS_ERROR .
+  #define BRB_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                             0
+  #define BRB_REG_INT_MASK_0_RC_PKT0_RLS_ERROR                                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT0_RLS_ERROR .
+  #define BRB_REG_INT_MASK_0_RC_PKT0_RLS_ERROR_SHIFT                                                         1
+  #define BRB_REG_INT_MASK_0_RC_PKT0_1ST_ERROR                                                               (0x1<<2) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT0_1ST_ERROR .
+  #define BRB_REG_INT_MASK_0_RC_PKT0_1ST_ERROR_SHIFT                                                         2
+  #define BRB_REG_INT_MASK_0_RC_PKT0_LEN_ERROR                                                               (0x1<<3) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT0_LEN_ERROR .
+  #define BRB_REG_INT_MASK_0_RC_PKT0_LEN_ERROR_SHIFT                                                         3
+  #define BRB_REG_INT_MASK_0_RC_PKT0_MIDDLE_ERROR                                                            (0x1<<4) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT0_MIDDLE_ERROR .
+  #define BRB_REG_INT_MASK_0_RC_PKT0_MIDDLE_ERROR_SHIFT                                                      4
+  #define BRB_REG_INT_MASK_0_RC_PKT0_PROTOCOL_ERROR                                                          (0x1<<5) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT0_PROTOCOL_ERROR .
+  #define BRB_REG_INT_MASK_0_RC_PKT0_PROTOCOL_ERROR_SHIFT                                                    5
+  #define BRB_REG_INT_MASK_0_RC_PKT1_RLS_ERROR                                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT1_RLS_ERROR .
+  #define BRB_REG_INT_MASK_0_RC_PKT1_RLS_ERROR_SHIFT                                                         6
+  #define BRB_REG_INT_MASK_0_RC_PKT1_1ST_ERROR                                                               (0x1<<7) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT1_1ST_ERROR .
+  #define BRB_REG_INT_MASK_0_RC_PKT1_1ST_ERROR_SHIFT                                                         7
+  #define BRB_REG_INT_MASK_0_RC_PKT1_LEN_ERROR                                                               (0x1<<8) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT1_LEN_ERROR .
+  #define BRB_REG_INT_MASK_0_RC_PKT1_LEN_ERROR_SHIFT                                                         8
+  #define BRB_REG_INT_MASK_0_RC_PKT1_MIDDLE_ERROR                                                            (0x1<<9) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT1_MIDDLE_ERROR .
+  #define BRB_REG_INT_MASK_0_RC_PKT1_MIDDLE_ERROR_SHIFT                                                      9
+  #define BRB_REG_INT_MASK_0_RC_PKT1_PROTOCOL_ERROR                                                          (0x1<<10) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT1_PROTOCOL_ERROR .
+  #define BRB_REG_INT_MASK_0_RC_PKT1_PROTOCOL_ERROR_SHIFT                                                    10
+  #define BRB_REG_INT_MASK_0_RC_PKT2_RLS_ERROR                                                               (0x1<<11) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT2_RLS_ERROR .
+  #define BRB_REG_INT_MASK_0_RC_PKT2_RLS_ERROR_SHIFT                                                         11
+  #define BRB_REG_INT_MASK_0_RC_PKT2_1ST_ERROR                                                               (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT2_1ST_ERROR .
+  #define BRB_REG_INT_MASK_0_RC_PKT2_1ST_ERROR_SHIFT                                                         12
+  #define BRB_REG_INT_MASK_0_RC_PKT2_LEN_ERROR                                                               (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT2_LEN_ERROR .
+  #define BRB_REG_INT_MASK_0_RC_PKT2_LEN_ERROR_SHIFT                                                         13
+  #define BRB_REG_INT_MASK_0_RC_PKT2_MIDDLE_ERROR                                                            (0x1<<14) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT2_MIDDLE_ERROR .
+  #define BRB_REG_INT_MASK_0_RC_PKT2_MIDDLE_ERROR_SHIFT                                                      14
+  #define BRB_REG_INT_MASK_0_RC_PKT2_PROTOCOL_ERROR                                                          (0x1<<15) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT2_PROTOCOL_ERROR .
+  #define BRB_REG_INT_MASK_0_RC_PKT2_PROTOCOL_ERROR_SHIFT                                                    15
+  #define BRB_REG_INT_MASK_0_RC_PKT3_RLS_ERROR                                                               (0x1<<16) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT3_RLS_ERROR .
+  #define BRB_REG_INT_MASK_0_RC_PKT3_RLS_ERROR_SHIFT                                                         16
+  #define BRB_REG_INT_MASK_0_RC_PKT3_1ST_ERROR                                                               (0x1<<17) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT3_1ST_ERROR .
+  #define BRB_REG_INT_MASK_0_RC_PKT3_1ST_ERROR_SHIFT                                                         17
+  #define BRB_REG_INT_MASK_0_RC_PKT3_LEN_ERROR                                                               (0x1<<18) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT3_LEN_ERROR .
+  #define BRB_REG_INT_MASK_0_RC_PKT3_LEN_ERROR_SHIFT                                                         18
+  #define BRB_REG_INT_MASK_0_RC_PKT3_MIDDLE_ERROR                                                            (0x1<<19) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT3_MIDDLE_ERROR .
+  #define BRB_REG_INT_MASK_0_RC_PKT3_MIDDLE_ERROR_SHIFT                                                      19
+  #define BRB_REG_INT_MASK_0_RC_PKT3_PROTOCOL_ERROR                                                          (0x1<<20) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT3_PROTOCOL_ERROR .
+  #define BRB_REG_INT_MASK_0_RC_PKT3_PROTOCOL_ERROR_SHIFT                                                    20
+  #define BRB_REG_INT_MASK_0_RC_SOP_REQ_TC_PORT_ERROR                                                        (0x1<<21) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_SOP_REQ_TC_PORT_ERROR .
+  #define BRB_REG_INT_MASK_0_RC_SOP_REQ_TC_PORT_ERROR_SHIFT                                                  21
+  #define BRB_REG_INT_MASK_0_UNCOMPLIENT_LOSSLESS_ERROR                                                      (0x1<<22) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.UNCOMPLIENT_LOSSLESS_ERROR .
+  #define BRB_REG_INT_MASK_0_UNCOMPLIENT_LOSSLESS_ERROR_SHIFT                                                22
+  #define BRB_REG_INT_MASK_0_WC0_PROTOCOL_ERROR                                                              (0x1<<23) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.WC0_PROTOCOL_ERROR .
+  #define BRB_REG_INT_MASK_0_WC0_PROTOCOL_ERROR_SHIFT                                                        23
+  #define BRB_REG_INT_MASK_0_WC1_PROTOCOL_ERROR                                                              (0x1<<24) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.WC1_PROTOCOL_ERROR .
+  #define BRB_REG_INT_MASK_0_WC1_PROTOCOL_ERROR_SHIFT                                                        24
+  #define BRB_REG_INT_MASK_0_WC2_PROTOCOL_ERROR                                                              (0x1<<25) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.WC2_PROTOCOL_ERROR .
+  #define BRB_REG_INT_MASK_0_WC2_PROTOCOL_ERROR_SHIFT                                                        25
+  #define BRB_REG_INT_MASK_0_WC3_PROTOCOL_ERROR                                                              (0x1<<26) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.WC3_PROTOCOL_ERROR .
+  #define BRB_REG_INT_MASK_0_WC3_PROTOCOL_ERROR_SHIFT                                                        26
+  #define BRB_REG_INT_MASK_0_LL_ARB_PREFETCH_SOP_ERROR                                                       (0x1<<27) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.LL_ARB_PREFETCH_SOP_ERROR .
+  #define BRB_REG_INT_MASK_0_LL_ARB_PREFETCH_SOP_ERROR_SHIFT                                                 27
+  #define BRB_REG_INT_MASK_0_LL_BLK_ERROR                                                                    (0x1<<28) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.LL_BLK_ERROR .
+  #define BRB_REG_INT_MASK_0_LL_BLK_ERROR_SHIFT                                                              28
+  #define BRB_REG_INT_MASK_0_PACKET_COUNTER_ERROR                                                            (0x1<<29) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.PACKET_COUNTER_ERROR .
+  #define BRB_REG_INT_MASK_0_PACKET_COUNTER_ERROR_SHIFT                                                      29
+  #define BRB_REG_INT_MASK_0_BYTE_COUNTER_ERROR                                                              (0x1<<30) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.BYTE_COUNTER_ERROR .
+  #define BRB_REG_INT_MASK_0_BYTE_COUNTER_ERROR_SHIFT                                                        30
+  #define BRB_REG_INT_MASK_0_MAC0_FC_CNT_ERROR                                                               (0x1<<31) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.MAC0_FC_CNT_ERROR .
+  #define BRB_REG_INT_MASK_0_MAC0_FC_CNT_ERROR_SHIFT                                                         31
+#define BRB_REG_INT_STS_WR_0                                                                                 0x3400c8UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define BRB_REG_INT_STS_WR_0_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define BRB_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                           0
+  #define BRB_REG_INT_STS_WR_0_RC_PKT0_RLS_ERROR                                                             (0x1<<1) // Read packet client PRM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_WR_0_RC_PKT0_RLS_ERROR_SHIFT                                                       1
+  #define BRB_REG_INT_STS_WR_0_RC_PKT0_1ST_ERROR                                                             (0x1<<2) // Read packet client PRM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR0/PRM/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_0_RC_PKT0_1ST_ERROR_SHIFT                                                       2
+  #define BRB_REG_INT_STS_WR_0_RC_PKT0_LEN_ERROR                                                             (0x1<<3) // Read packet client PRM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_WR_0_RC_PKT0_LEN_ERROR_SHIFT                                                       3
+  #define BRB_REG_INT_STS_WR_0_RC_PKT0_MIDDLE_ERROR                                                          (0x1<<4) // Read packet client PRM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR0/PRM/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_0_RC_PKT0_MIDDLE_ERROR_SHIFT                                                    4
+  #define BRB_REG_INT_STS_WR_0_RC_PKT0_PROTOCOL_ERROR                                                        (0x1<<5) // Read packet client PRM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_WR_0_RC_PKT0_PROTOCOL_ERROR_SHIFT                                                  5
+  #define BRB_REG_INT_STS_WR_0_RC_PKT1_RLS_ERROR                                                             (0x1<<6) // Read packet client MSDM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_WR_0_RC_PKT1_RLS_ERROR_SHIFT                                                       6
+  #define BRB_REG_INT_STS_WR_0_RC_PKT1_1ST_ERROR                                                             (0x1<<7) // Read packet client MSDM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR1/MSDM/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_0_RC_PKT1_1ST_ERROR_SHIFT                                                       7
+  #define BRB_REG_INT_STS_WR_0_RC_PKT1_LEN_ERROR                                                             (0x1<<8) // Read packet client MSDM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_WR_0_RC_PKT1_LEN_ERROR_SHIFT                                                       8
+  #define BRB_REG_INT_STS_WR_0_RC_PKT1_MIDDLE_ERROR                                                          (0x1<<9) // Read packet client MSDM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR1/MSDM/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_0_RC_PKT1_MIDDLE_ERROR_SHIFT                                                    9
+  #define BRB_REG_INT_STS_WR_0_RC_PKT1_PROTOCOL_ERROR                                                        (0x1<<10) // Read packet client MSDM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_WR_0_RC_PKT1_PROTOCOL_ERROR_SHIFT                                                  10
+  #define BRB_REG_INT_STS_WR_0_RC_PKT2_RLS_ERROR                                                             (0x1<<11) // Read packet client TSDM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_WR_0_RC_PKT2_RLS_ERROR_SHIFT                                                       11
+  #define BRB_REG_INT_STS_WR_0_RC_PKT2_1ST_ERROR                                                             (0x1<<12) // Read packet client TSDM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR2/TSDM/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_0_RC_PKT2_1ST_ERROR_SHIFT                                                       12
+  #define BRB_REG_INT_STS_WR_0_RC_PKT2_LEN_ERROR                                                             (0x1<<13) // Read packet client TSDM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_WR_0_RC_PKT2_LEN_ERROR_SHIFT                                                       13
+  #define BRB_REG_INT_STS_WR_0_RC_PKT2_MIDDLE_ERROR                                                          (0x1<<14) // Read packet client TSDM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR2/TSDM/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_0_RC_PKT2_MIDDLE_ERROR_SHIFT                                                    14
+  #define BRB_REG_INT_STS_WR_0_RC_PKT2_PROTOCOL_ERROR                                                        (0x1<<15) // Read packet client TSDM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_WR_0_RC_PKT2_PROTOCOL_ERROR_SHIFT                                                  15
+  #define BRB_REG_INT_STS_WR_0_RC_PKT3_RLS_ERROR                                                             (0x1<<16) // Read packet client parser release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_WR_0_RC_PKT3_RLS_ERROR_SHIFT                                                       16
+  #define BRB_REG_INT_STS_WR_0_RC_PKT3_1ST_ERROR                                                             (0x1<<17) // Read packet client parser first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_0_RC_PKT3_1ST_ERROR_SHIFT                                                       17
+  #define BRB_REG_INT_STS_WR_0_RC_PKT3_LEN_ERROR                                                             (0x1<<18) // Read packet client parser length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_WR_0_RC_PKT3_LEN_ERROR_SHIFT                                                       18
+  #define BRB_REG_INT_STS_WR_0_RC_PKT3_MIDDLE_ERROR                                                          (0x1<<19) // Read packet client parser error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_0_RC_PKT3_MIDDLE_ERROR_SHIFT                                                    19
+  #define BRB_REG_INT_STS_WR_0_RC_PKT3_PROTOCOL_ERROR                                                        (0x1<<20) // Read packet client parser error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_WR_0_RC_PKT3_PROTOCOL_ERROR_SHIFT                                                  20
+  #define BRB_REG_INT_STS_WR_0_RC_SOP_REQ_TC_PORT_ERROR                                                      (0x1<<21) // SOP descriptor request from empty TC or port.
+  #define BRB_REG_INT_STS_WR_0_RC_SOP_REQ_TC_PORT_ERROR_SHIFT                                                21
+  #define BRB_REG_INT_STS_WR_0_UNCOMPLIENT_LOSSLESS_ERROR                                                    (0x1<<22) // One of uncoplient lossless counters is bigger than threshold PAUSE_EN::/PAUSE_EN/d in Comments.
+  #define BRB_REG_INT_STS_WR_0_UNCOMPLIENT_LOSSLESS_ERROR_SHIFT                                              22
+  #define BRB_REG_INT_STS_WR_0_WC0_PROTOCOL_ERROR                                                            (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
+  #define BRB_REG_INT_STS_WR_0_WC0_PROTOCOL_ERROR_SHIFT                                                      23
+  #define BRB_REG_INT_STS_WR_0_WC1_PROTOCOL_ERROR                                                            (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 1 RX_INT ::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_0_WC1_PROTOCOL_ERROR_SHIFT                                                      24
+  #define BRB_REG_INT_STS_WR_0_WC2_PROTOCOL_ERROR                                                            (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 2 RX_INT ::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_0_WC2_PROTOCOL_ERROR_SHIFT                                                      25
+  #define BRB_REG_INT_STS_WR_0_WC3_PROTOCOL_ERROR                                                            (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 3 RX_INT ::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_0_WC3_PROTOCOL_ERROR_SHIFT                                                      26
+  #define BRB_REG_INT_STS_WR_0_LL_ARB_PREFETCH_SOP_ERROR                                                     (0x1<<27) // Link list arbiter prefetch SOP error RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_0_LL_ARB_PREFETCH_SOP_ERROR_SHIFT                                               27
+  #define BRB_REG_INT_STS_WR_0_LL_BLK_ERROR                                                                  (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
+  #define BRB_REG_INT_STS_WR_0_LL_BLK_ERROR_SHIFT                                                            28
+  #define BRB_REG_INT_STS_WR_0_PACKET_COUNTER_ERROR                                                          (0x1<<29) // Packet counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_0_PACKET_COUNTER_ERROR_SHIFT                                                    29
+  #define BRB_REG_INT_STS_WR_0_BYTE_COUNTER_ERROR                                                            (0x1<<30) // Byte counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_0_BYTE_COUNTER_ERROR_SHIFT                                                      30
+  #define BRB_REG_INT_STS_WR_0_MAC0_FC_CNT_ERROR                                                             (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_0_MAC0_FC_CNT_ERROR_SHIFT                                                       31
+#define BRB_REG_INT_STS_CLR_0                                                                                0x3400ccUL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define BRB_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define BRB_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                          0
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT0_RLS_ERROR                                                            (0x1<<1) // Read packet client PRM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT0_RLS_ERROR_SHIFT                                                      1
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT0_1ST_ERROR                                                            (0x1<<2) // Read packet client PRM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR0/PRM/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT0_1ST_ERROR_SHIFT                                                      2
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT0_LEN_ERROR                                                            (0x1<<3) // Read packet client PRM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT0_LEN_ERROR_SHIFT                                                      3
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT0_MIDDLE_ERROR                                                         (0x1<<4) // Read packet client PRM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR0/PRM/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT0_MIDDLE_ERROR_SHIFT                                                   4
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT0_PROTOCOL_ERROR                                                       (0x1<<5) // Read packet client PRM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT0_PROTOCOL_ERROR_SHIFT                                                 5
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT1_RLS_ERROR                                                            (0x1<<6) // Read packet client MSDM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT1_RLS_ERROR_SHIFT                                                      6
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT1_1ST_ERROR                                                            (0x1<<7) // Read packet client MSDM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR1/MSDM/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT1_1ST_ERROR_SHIFT                                                      7
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT1_LEN_ERROR                                                            (0x1<<8) // Read packet client MSDM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT1_LEN_ERROR_SHIFT                                                      8
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT1_MIDDLE_ERROR                                                         (0x1<<9) // Read packet client MSDM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR1/MSDM/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT1_MIDDLE_ERROR_SHIFT                                                   9
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT1_PROTOCOL_ERROR                                                       (0x1<<10) // Read packet client MSDM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT1_PROTOCOL_ERROR_SHIFT                                                 10
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT2_RLS_ERROR                                                            (0x1<<11) // Read packet client TSDM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT2_RLS_ERROR_SHIFT                                                      11
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT2_1ST_ERROR                                                            (0x1<<12) // Read packet client TSDM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR2/TSDM/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT2_1ST_ERROR_SHIFT                                                      12
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT2_LEN_ERROR                                                            (0x1<<13) // Read packet client TSDM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT2_LEN_ERROR_SHIFT                                                      13
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT2_MIDDLE_ERROR                                                         (0x1<<14) // Read packet client TSDM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR2/TSDM/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT2_MIDDLE_ERROR_SHIFT                                                   14
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT2_PROTOCOL_ERROR                                                       (0x1<<15) // Read packet client TSDM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT2_PROTOCOL_ERROR_SHIFT                                                 15
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT3_RLS_ERROR                                                            (0x1<<16) // Read packet client parser release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT3_RLS_ERROR_SHIFT                                                      16
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT3_1ST_ERROR                                                            (0x1<<17) // Read packet client parser first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT3_1ST_ERROR_SHIFT                                                      17
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT3_LEN_ERROR                                                            (0x1<<18) // Read packet client parser length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT3_LEN_ERROR_SHIFT                                                      18
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT3_MIDDLE_ERROR                                                         (0x1<<19) // Read packet client parser error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT3_MIDDLE_ERROR_SHIFT                                                   19
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT3_PROTOCOL_ERROR                                                       (0x1<<20) // Read packet client parser error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_CLR_0_RC_PKT3_PROTOCOL_ERROR_SHIFT                                                 20
+  #define BRB_REG_INT_STS_CLR_0_RC_SOP_REQ_TC_PORT_ERROR                                                     (0x1<<21) // SOP descriptor request from empty TC or port.
+  #define BRB_REG_INT_STS_CLR_0_RC_SOP_REQ_TC_PORT_ERROR_SHIFT                                               21
+  #define BRB_REG_INT_STS_CLR_0_UNCOMPLIENT_LOSSLESS_ERROR                                                   (0x1<<22) // One of uncoplient lossless counters is bigger than threshold PAUSE_EN::/PAUSE_EN/d in Comments.
+  #define BRB_REG_INT_STS_CLR_0_UNCOMPLIENT_LOSSLESS_ERROR_SHIFT                                             22
+  #define BRB_REG_INT_STS_CLR_0_WC0_PROTOCOL_ERROR                                                           (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
+  #define BRB_REG_INT_STS_CLR_0_WC0_PROTOCOL_ERROR_SHIFT                                                     23
+  #define BRB_REG_INT_STS_CLR_0_WC1_PROTOCOL_ERROR                                                           (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 1 RX_INT ::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_0_WC1_PROTOCOL_ERROR_SHIFT                                                     24
+  #define BRB_REG_INT_STS_CLR_0_WC2_PROTOCOL_ERROR                                                           (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 2 RX_INT ::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_0_WC2_PROTOCOL_ERROR_SHIFT                                                     25
+  #define BRB_REG_INT_STS_CLR_0_WC3_PROTOCOL_ERROR                                                           (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 3 RX_INT ::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_0_WC3_PROTOCOL_ERROR_SHIFT                                                     26
+  #define BRB_REG_INT_STS_CLR_0_LL_ARB_PREFETCH_SOP_ERROR                                                    (0x1<<27) // Link list arbiter prefetch SOP error RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_0_LL_ARB_PREFETCH_SOP_ERROR_SHIFT                                              27
+  #define BRB_REG_INT_STS_CLR_0_LL_BLK_ERROR                                                                 (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
+  #define BRB_REG_INT_STS_CLR_0_LL_BLK_ERROR_SHIFT                                                           28
+  #define BRB_REG_INT_STS_CLR_0_PACKET_COUNTER_ERROR                                                         (0x1<<29) // Packet counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_0_PACKET_COUNTER_ERROR_SHIFT                                                   29
+  #define BRB_REG_INT_STS_CLR_0_BYTE_COUNTER_ERROR                                                           (0x1<<30) // Byte counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_0_BYTE_COUNTER_ERROR_SHIFT                                                     30
+  #define BRB_REG_INT_STS_CLR_0_MAC0_FC_CNT_ERROR                                                            (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_0_MAC0_FC_CNT_ERROR_SHIFT                                                      31
+#define BRB_REG_INT_STS_1                                                                                    0x3400d8UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define BRB_REG_INT_STS_1_MAC1_FC_CNT_ERROR                                                                (0x1<<0) // Free shared area calculation error for MAC port 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_1_MAC1_FC_CNT_ERROR_SHIFT                                                          0
+  #define BRB_REG_INT_STS_1_LL_ARB_CALC_ERROR                                                                (0x1<<1) // Calculations error in LL arbiter block.
+  #define BRB_REG_INT_STS_1_LL_ARB_CALC_ERROR_SHIFT                                                          1
+  #define BRB_REG_INT_STS_1_WC0_INP_FIFO_ERROR                                                               (0x1<<3) // Input FIFO error in write client 0.
+  #define BRB_REG_INT_STS_1_WC0_INP_FIFO_ERROR_SHIFT                                                         3
+  #define BRB_REG_INT_STS_1_WC0_SOP_FIFO_ERROR                                                               (0x1<<4) // SOP FIFO error in write client 0.
+  #define BRB_REG_INT_STS_1_WC0_SOP_FIFO_ERROR_SHIFT                                                         4
+  #define BRB_REG_INT_STS_1_WC0_EOP_FIFO_ERROR                                                               (0x1<<6) // EOP FIFO error in write client 0.
+  #define BRB_REG_INT_STS_1_WC0_EOP_FIFO_ERROR_SHIFT                                                         6
+  #define BRB_REG_INT_STS_1_WC0_QUEUE_FIFO_ERROR                                                             (0x1<<7) // Queue FIFO error in write client 0.
+  #define BRB_REG_INT_STS_1_WC0_QUEUE_FIFO_ERROR_SHIFT                                                       7
+  #define BRB_REG_INT_STS_1_WC0_FREE_POINT_FIFO_ERROR                                                        (0x1<<8) // Free ointer FIFO error in write client 0.
+  #define BRB_REG_INT_STS_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT                                                  8
+  #define BRB_REG_INT_STS_1_WC0_NEXT_POINT_FIFO_ERROR                                                        (0x1<<9) // Next pointer FIFO error in write client 0.
+  #define BRB_REG_INT_STS_1_WC0_NEXT_POINT_FIFO_ERROR_SHIFT                                                  9
+  #define BRB_REG_INT_STS_1_WC0_STRT_FIFO_ERROR                                                              (0x1<<10) // Start FIFO error in write client 0.
+  #define BRB_REG_INT_STS_1_WC0_STRT_FIFO_ERROR_SHIFT                                                        10
+  #define BRB_REG_INT_STS_1_WC0_SECOND_DSCR_FIFO_ERROR                                                       (0x1<<11) // Second descriptor FIFO error in write client 0.
+  #define BRB_REG_INT_STS_1_WC0_SECOND_DSCR_FIFO_ERROR_SHIFT                                                 11
+  #define BRB_REG_INT_STS_1_WC0_PKT_AVAIL_FIFO_ERROR                                                         (0x1<<12) // Packet available FIFO error in write client 0.
+  #define BRB_REG_INT_STS_1_WC0_PKT_AVAIL_FIFO_ERROR_SHIFT                                                   12
+  #define BRB_REG_INT_STS_1_WC0_COS_CNT_FIFO_ERROR                                                           (0x1<<13) // COS counter FIFO error in write client 0 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_1_WC0_COS_CNT_FIFO_ERROR_SHIFT                                                     13
+  #define BRB_REG_INT_STS_1_WC0_NOTIFY_FIFO_ERROR                                                            (0x1<<14) // Notify FIFO error in write client 0.
+  #define BRB_REG_INT_STS_1_WC0_NOTIFY_FIFO_ERROR_SHIFT                                                      14
+  #define BRB_REG_INT_STS_1_WC0_LL_REQ_FIFO_ERROR                                                            (0x1<<15) // LL req error in write client 0.
+  #define BRB_REG_INT_STS_1_WC0_LL_REQ_FIFO_ERROR_SHIFT                                                      15
+  #define BRB_REG_INT_STS_1_WC0_LL_PA_CNT_ERROR                                                              (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
+  #define BRB_REG_INT_STS_1_WC0_LL_PA_CNT_ERROR_SHIFT                                                        16
+  #define BRB_REG_INT_STS_1_WC0_BB_PA_CNT_ERROR                                                              (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
+  #define BRB_REG_INT_STS_1_WC0_BB_PA_CNT_ERROR_SHIFT                                                        17
+  #define BRB_REG_INT_STS_1_WC1_INP_FIFO_ERROR                                                               (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_1_WC1_INP_FIFO_ERROR_SHIFT                                                         18
+  #define BRB_REG_INT_STS_1_WC1_SOP_FIFO_ERROR                                                               (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_1_WC1_SOP_FIFO_ERROR_SHIFT                                                         19
+  #define BRB_REG_INT_STS_1_WC1_EOP_FIFO_ERROR                                                               (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_1_WC1_EOP_FIFO_ERROR_SHIFT                                                         20
+  #define BRB_REG_INT_STS_1_WC1_QUEUE_FIFO_ERROR                                                             (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_1_WC1_QUEUE_FIFO_ERROR_SHIFT                                                       21
+  #define BRB_REG_INT_STS_1_WC1_FREE_POINT_FIFO_ERROR                                                        (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_1_WC1_FREE_POINT_FIFO_ERROR_SHIFT                                                  22
+  #define BRB_REG_INT_STS_1_WC1_NEXT_POINT_FIFO_ERROR                                                        (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_1_WC1_NEXT_POINT_FIFO_ERROR_SHIFT                                                  23
+  #define BRB_REG_INT_STS_1_WC1_STRT_FIFO_ERROR                                                              (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_1_WC1_STRT_FIFO_ERROR_SHIFT                                                        24
+  #define BRB_REG_INT_STS_1_WC1_SECOND_DSCR_FIFO_ERROR                                                       (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_1_WC1_SECOND_DSCR_FIFO_ERROR_SHIFT                                                 25
+  #define BRB_REG_INT_STS_1_WC1_PKT_AVAIL_FIFO_ERROR                                                         (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 1 RX_INT ::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_1_WC1_PKT_AVAIL_FIFO_ERROR_SHIFT                                                   26
+  #define BRB_REG_INT_STS_1_WC1_COS_CNT_FIFO_ERROR                                                           (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_1_WC1_COS_CNT_FIFO_ERROR_SHIFT                                                     27
+  #define BRB_REG_INT_STS_1_WC1_NOTIFY_FIFO_ERROR                                                            (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_1_WC1_NOTIFY_FIFO_ERROR_SHIFT                                                      28
+  #define BRB_REG_INT_STS_1_WC1_LL_REQ_FIFO_ERROR                                                            (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_1_WC1_LL_REQ_FIFO_ERROR_SHIFT                                                      29
+  #define BRB_REG_INT_STS_1_WC1_LL_PA_CNT_ERROR                                                              (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_1_WC1_LL_PA_CNT_ERROR_SHIFT                                                        30
+  #define BRB_REG_INT_STS_1_WC1_BB_PA_CNT_ERROR                                                              (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_1_WC1_BB_PA_CNT_ERROR_SHIFT                                                        31
+#define BRB_REG_INT_MASK_1                                                                                   0x3400dcUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define BRB_REG_INT_MASK_1_MAC1_FC_CNT_ERROR                                                               (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.MAC1_FC_CNT_ERROR .
+  #define BRB_REG_INT_MASK_1_MAC1_FC_CNT_ERROR_SHIFT                                                         0
+  #define BRB_REG_INT_MASK_1_LL_ARB_CALC_ERROR                                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.LL_ARB_CALC_ERROR .
+  #define BRB_REG_INT_MASK_1_LL_ARB_CALC_ERROR_SHIFT                                                         1
+  #define BRB_REG_INT_MASK_1_WC0_INP_FIFO_ERROR                                                              (0x1<<3) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_INP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_1_WC0_INP_FIFO_ERROR_SHIFT                                                        3
+  #define BRB_REG_INT_MASK_1_WC0_SOP_FIFO_ERROR                                                              (0x1<<4) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_SOP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_1_WC0_SOP_FIFO_ERROR_SHIFT                                                        4
+  #define BRB_REG_INT_MASK_1_WC0_EOP_FIFO_ERROR                                                              (0x1<<6) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_EOP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_1_WC0_EOP_FIFO_ERROR_SHIFT                                                        6
+  #define BRB_REG_INT_MASK_1_WC0_QUEUE_FIFO_ERROR                                                            (0x1<<7) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_QUEUE_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_1_WC0_QUEUE_FIFO_ERROR_SHIFT                                                      7
+  #define BRB_REG_INT_MASK_1_WC0_FREE_POINT_FIFO_ERROR                                                       (0x1<<8) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_FREE_POINT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT                                                 8
+  #define BRB_REG_INT_MASK_1_WC0_NEXT_POINT_FIFO_ERROR                                                       (0x1<<9) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_NEXT_POINT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_1_WC0_NEXT_POINT_FIFO_ERROR_SHIFT                                                 9
+  #define BRB_REG_INT_MASK_1_WC0_STRT_FIFO_ERROR                                                             (0x1<<10) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_STRT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_1_WC0_STRT_FIFO_ERROR_SHIFT                                                       10
+  #define BRB_REG_INT_MASK_1_WC0_SECOND_DSCR_FIFO_ERROR                                                      (0x1<<11) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_SECOND_DSCR_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_1_WC0_SECOND_DSCR_FIFO_ERROR_SHIFT                                                11
+  #define BRB_REG_INT_MASK_1_WC0_PKT_AVAIL_FIFO_ERROR                                                        (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_PKT_AVAIL_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_1_WC0_PKT_AVAIL_FIFO_ERROR_SHIFT                                                  12
+  #define BRB_REG_INT_MASK_1_WC0_COS_CNT_FIFO_ERROR                                                          (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_COS_CNT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_1_WC0_COS_CNT_FIFO_ERROR_SHIFT                                                    13
+  #define BRB_REG_INT_MASK_1_WC0_NOTIFY_FIFO_ERROR                                                           (0x1<<14) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_NOTIFY_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_1_WC0_NOTIFY_FIFO_ERROR_SHIFT                                                     14
+  #define BRB_REG_INT_MASK_1_WC0_LL_REQ_FIFO_ERROR                                                           (0x1<<15) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_LL_REQ_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_1_WC0_LL_REQ_FIFO_ERROR_SHIFT                                                     15
+  #define BRB_REG_INT_MASK_1_WC0_LL_PA_CNT_ERROR                                                             (0x1<<16) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_LL_PA_CNT_ERROR .
+  #define BRB_REG_INT_MASK_1_WC0_LL_PA_CNT_ERROR_SHIFT                                                       16
+  #define BRB_REG_INT_MASK_1_WC0_BB_PA_CNT_ERROR                                                             (0x1<<17) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_BB_PA_CNT_ERROR .
+  #define BRB_REG_INT_MASK_1_WC0_BB_PA_CNT_ERROR_SHIFT                                                       17
+  #define BRB_REG_INT_MASK_1_WC1_INP_FIFO_ERROR                                                              (0x1<<18) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_INP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_1_WC1_INP_FIFO_ERROR_SHIFT                                                        18
+  #define BRB_REG_INT_MASK_1_WC1_SOP_FIFO_ERROR                                                              (0x1<<19) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_SOP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_1_WC1_SOP_FIFO_ERROR_SHIFT                                                        19
+  #define BRB_REG_INT_MASK_1_WC1_EOP_FIFO_ERROR                                                              (0x1<<20) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_EOP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_1_WC1_EOP_FIFO_ERROR_SHIFT                                                        20
+  #define BRB_REG_INT_MASK_1_WC1_QUEUE_FIFO_ERROR                                                            (0x1<<21) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_QUEUE_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_1_WC1_QUEUE_FIFO_ERROR_SHIFT                                                      21
+  #define BRB_REG_INT_MASK_1_WC1_FREE_POINT_FIFO_ERROR                                                       (0x1<<22) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_FREE_POINT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_1_WC1_FREE_POINT_FIFO_ERROR_SHIFT                                                 22
+  #define BRB_REG_INT_MASK_1_WC1_NEXT_POINT_FIFO_ERROR                                                       (0x1<<23) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_NEXT_POINT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_1_WC1_NEXT_POINT_FIFO_ERROR_SHIFT                                                 23
+  #define BRB_REG_INT_MASK_1_WC1_STRT_FIFO_ERROR                                                             (0x1<<24) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_STRT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_1_WC1_STRT_FIFO_ERROR_SHIFT                                                       24
+  #define BRB_REG_INT_MASK_1_WC1_SECOND_DSCR_FIFO_ERROR                                                      (0x1<<25) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_SECOND_DSCR_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_1_WC1_SECOND_DSCR_FIFO_ERROR_SHIFT                                                25
+  #define BRB_REG_INT_MASK_1_WC1_PKT_AVAIL_FIFO_ERROR                                                        (0x1<<26) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_PKT_AVAIL_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_1_WC1_PKT_AVAIL_FIFO_ERROR_SHIFT                                                  26
+  #define BRB_REG_INT_MASK_1_WC1_COS_CNT_FIFO_ERROR                                                          (0x1<<27) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_COS_CNT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_1_WC1_COS_CNT_FIFO_ERROR_SHIFT                                                    27
+  #define BRB_REG_INT_MASK_1_WC1_NOTIFY_FIFO_ERROR                                                           (0x1<<28) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_NOTIFY_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_1_WC1_NOTIFY_FIFO_ERROR_SHIFT                                                     28
+  #define BRB_REG_INT_MASK_1_WC1_LL_REQ_FIFO_ERROR                                                           (0x1<<29) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_LL_REQ_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_1_WC1_LL_REQ_FIFO_ERROR_SHIFT                                                     29
+  #define BRB_REG_INT_MASK_1_WC1_LL_PA_CNT_ERROR                                                             (0x1<<30) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_LL_PA_CNT_ERROR .
+  #define BRB_REG_INT_MASK_1_WC1_LL_PA_CNT_ERROR_SHIFT                                                       30
+  #define BRB_REG_INT_MASK_1_WC1_BB_PA_CNT_ERROR                                                             (0x1<<31) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_BB_PA_CNT_ERROR .
+  #define BRB_REG_INT_MASK_1_WC1_BB_PA_CNT_ERROR_SHIFT                                                       31
+#define BRB_REG_INT_STS_WR_1                                                                                 0x3400e0UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define BRB_REG_INT_STS_WR_1_MAC1_FC_CNT_ERROR                                                             (0x1<<0) // Free shared area calculation error for MAC port 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_1_MAC1_FC_CNT_ERROR_SHIFT                                                       0
+  #define BRB_REG_INT_STS_WR_1_LL_ARB_CALC_ERROR                                                             (0x1<<1) // Calculations error in LL arbiter block.
+  #define BRB_REG_INT_STS_WR_1_LL_ARB_CALC_ERROR_SHIFT                                                       1
+  #define BRB_REG_INT_STS_WR_1_WC0_INP_FIFO_ERROR                                                            (0x1<<3) // Input FIFO error in write client 0.
+  #define BRB_REG_INT_STS_WR_1_WC0_INP_FIFO_ERROR_SHIFT                                                      3
+  #define BRB_REG_INT_STS_WR_1_WC0_SOP_FIFO_ERROR                                                            (0x1<<4) // SOP FIFO error in write client 0.
+  #define BRB_REG_INT_STS_WR_1_WC0_SOP_FIFO_ERROR_SHIFT                                                      4
+  #define BRB_REG_INT_STS_WR_1_WC0_EOP_FIFO_ERROR                                                            (0x1<<6) // EOP FIFO error in write client 0.
+  #define BRB_REG_INT_STS_WR_1_WC0_EOP_FIFO_ERROR_SHIFT                                                      6
+  #define BRB_REG_INT_STS_WR_1_WC0_QUEUE_FIFO_ERROR                                                          (0x1<<7) // Queue FIFO error in write client 0.
+  #define BRB_REG_INT_STS_WR_1_WC0_QUEUE_FIFO_ERROR_SHIFT                                                    7
+  #define BRB_REG_INT_STS_WR_1_WC0_FREE_POINT_FIFO_ERROR                                                     (0x1<<8) // Free ointer FIFO error in write client 0.
+  #define BRB_REG_INT_STS_WR_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT                                               8
+  #define BRB_REG_INT_STS_WR_1_WC0_NEXT_POINT_FIFO_ERROR                                                     (0x1<<9) // Next pointer FIFO error in write client 0.
+  #define BRB_REG_INT_STS_WR_1_WC0_NEXT_POINT_FIFO_ERROR_SHIFT                                               9
+  #define BRB_REG_INT_STS_WR_1_WC0_STRT_FIFO_ERROR                                                           (0x1<<10) // Start FIFO error in write client 0.
+  #define BRB_REG_INT_STS_WR_1_WC0_STRT_FIFO_ERROR_SHIFT                                                     10
+  #define BRB_REG_INT_STS_WR_1_WC0_SECOND_DSCR_FIFO_ERROR                                                    (0x1<<11) // Second descriptor FIFO error in write client 0.
+  #define BRB_REG_INT_STS_WR_1_WC0_SECOND_DSCR_FIFO_ERROR_SHIFT                                              11
+  #define BRB_REG_INT_STS_WR_1_WC0_PKT_AVAIL_FIFO_ERROR                                                      (0x1<<12) // Packet available FIFO error in write client 0.
+  #define BRB_REG_INT_STS_WR_1_WC0_PKT_AVAIL_FIFO_ERROR_SHIFT                                                12
+  #define BRB_REG_INT_STS_WR_1_WC0_COS_CNT_FIFO_ERROR                                                        (0x1<<13) // COS counter FIFO error in write client 0 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_1_WC0_COS_CNT_FIFO_ERROR_SHIFT                                                  13
+  #define BRB_REG_INT_STS_WR_1_WC0_NOTIFY_FIFO_ERROR                                                         (0x1<<14) // Notify FIFO error in write client 0.
+  #define BRB_REG_INT_STS_WR_1_WC0_NOTIFY_FIFO_ERROR_SHIFT                                                   14
+  #define BRB_REG_INT_STS_WR_1_WC0_LL_REQ_FIFO_ERROR                                                         (0x1<<15) // LL req error in write client 0.
+  #define BRB_REG_INT_STS_WR_1_WC0_LL_REQ_FIFO_ERROR_SHIFT                                                   15
+  #define BRB_REG_INT_STS_WR_1_WC0_LL_PA_CNT_ERROR                                                           (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
+  #define BRB_REG_INT_STS_WR_1_WC0_LL_PA_CNT_ERROR_SHIFT                                                     16
+  #define BRB_REG_INT_STS_WR_1_WC0_BB_PA_CNT_ERROR                                                           (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
+  #define BRB_REG_INT_STS_WR_1_WC0_BB_PA_CNT_ERROR_SHIFT                                                     17
+  #define BRB_REG_INT_STS_WR_1_WC1_INP_FIFO_ERROR                                                            (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_1_WC1_INP_FIFO_ERROR_SHIFT                                                      18
+  #define BRB_REG_INT_STS_WR_1_WC1_SOP_FIFO_ERROR                                                            (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_1_WC1_SOP_FIFO_ERROR_SHIFT                                                      19
+  #define BRB_REG_INT_STS_WR_1_WC1_EOP_FIFO_ERROR                                                            (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_1_WC1_EOP_FIFO_ERROR_SHIFT                                                      20
+  #define BRB_REG_INT_STS_WR_1_WC1_QUEUE_FIFO_ERROR                                                          (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_1_WC1_QUEUE_FIFO_ERROR_SHIFT                                                    21
+  #define BRB_REG_INT_STS_WR_1_WC1_FREE_POINT_FIFO_ERROR                                                     (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_1_WC1_FREE_POINT_FIFO_ERROR_SHIFT                                               22
+  #define BRB_REG_INT_STS_WR_1_WC1_NEXT_POINT_FIFO_ERROR                                                     (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_1_WC1_NEXT_POINT_FIFO_ERROR_SHIFT                                               23
+  #define BRB_REG_INT_STS_WR_1_WC1_STRT_FIFO_ERROR                                                           (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_1_WC1_STRT_FIFO_ERROR_SHIFT                                                     24
+  #define BRB_REG_INT_STS_WR_1_WC1_SECOND_DSCR_FIFO_ERROR                                                    (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_1_WC1_SECOND_DSCR_FIFO_ERROR_SHIFT                                              25
+  #define BRB_REG_INT_STS_WR_1_WC1_PKT_AVAIL_FIFO_ERROR                                                      (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 1 RX_INT ::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_1_WC1_PKT_AVAIL_FIFO_ERROR_SHIFT                                                26
+  #define BRB_REG_INT_STS_WR_1_WC1_COS_CNT_FIFO_ERROR                                                        (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_1_WC1_COS_CNT_FIFO_ERROR_SHIFT                                                  27
+  #define BRB_REG_INT_STS_WR_1_WC1_NOTIFY_FIFO_ERROR                                                         (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_1_WC1_NOTIFY_FIFO_ERROR_SHIFT                                                   28
+  #define BRB_REG_INT_STS_WR_1_WC1_LL_REQ_FIFO_ERROR                                                         (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_1_WC1_LL_REQ_FIFO_ERROR_SHIFT                                                   29
+  #define BRB_REG_INT_STS_WR_1_WC1_LL_PA_CNT_ERROR                                                           (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_1_WC1_LL_PA_CNT_ERROR_SHIFT                                                     30
+  #define BRB_REG_INT_STS_WR_1_WC1_BB_PA_CNT_ERROR                                                           (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_1_WC1_BB_PA_CNT_ERROR_SHIFT                                                     31
+#define BRB_REG_INT_STS_CLR_1                                                                                0x3400e4UL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define BRB_REG_INT_STS_CLR_1_MAC1_FC_CNT_ERROR                                                            (0x1<<0) // Free shared area calculation error for MAC port 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_1_MAC1_FC_CNT_ERROR_SHIFT                                                      0
+  #define BRB_REG_INT_STS_CLR_1_LL_ARB_CALC_ERROR                                                            (0x1<<1) // Calculations error in LL arbiter block.
+  #define BRB_REG_INT_STS_CLR_1_LL_ARB_CALC_ERROR_SHIFT                                                      1
+  #define BRB_REG_INT_STS_CLR_1_WC0_INP_FIFO_ERROR                                                           (0x1<<3) // Input FIFO error in write client 0.
+  #define BRB_REG_INT_STS_CLR_1_WC0_INP_FIFO_ERROR_SHIFT                                                     3
+  #define BRB_REG_INT_STS_CLR_1_WC0_SOP_FIFO_ERROR                                                           (0x1<<4) // SOP FIFO error in write client 0.
+  #define BRB_REG_INT_STS_CLR_1_WC0_SOP_FIFO_ERROR_SHIFT                                                     4
+  #define BRB_REG_INT_STS_CLR_1_WC0_EOP_FIFO_ERROR                                                           (0x1<<6) // EOP FIFO error in write client 0.
+  #define BRB_REG_INT_STS_CLR_1_WC0_EOP_FIFO_ERROR_SHIFT                                                     6
+  #define BRB_REG_INT_STS_CLR_1_WC0_QUEUE_FIFO_ERROR                                                         (0x1<<7) // Queue FIFO error in write client 0.
+  #define BRB_REG_INT_STS_CLR_1_WC0_QUEUE_FIFO_ERROR_SHIFT                                                   7
+  #define BRB_REG_INT_STS_CLR_1_WC0_FREE_POINT_FIFO_ERROR                                                    (0x1<<8) // Free ointer FIFO error in write client 0.
+  #define BRB_REG_INT_STS_CLR_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT                                              8
+  #define BRB_REG_INT_STS_CLR_1_WC0_NEXT_POINT_FIFO_ERROR                                                    (0x1<<9) // Next pointer FIFO error in write client 0.
+  #define BRB_REG_INT_STS_CLR_1_WC0_NEXT_POINT_FIFO_ERROR_SHIFT                                              9
+  #define BRB_REG_INT_STS_CLR_1_WC0_STRT_FIFO_ERROR                                                          (0x1<<10) // Start FIFO error in write client 0.
+  #define BRB_REG_INT_STS_CLR_1_WC0_STRT_FIFO_ERROR_SHIFT                                                    10
+  #define BRB_REG_INT_STS_CLR_1_WC0_SECOND_DSCR_FIFO_ERROR                                                   (0x1<<11) // Second descriptor FIFO error in write client 0.
+  #define BRB_REG_INT_STS_CLR_1_WC0_SECOND_DSCR_FIFO_ERROR_SHIFT                                             11
+  #define BRB_REG_INT_STS_CLR_1_WC0_PKT_AVAIL_FIFO_ERROR                                                     (0x1<<12) // Packet available FIFO error in write client 0.
+  #define BRB_REG_INT_STS_CLR_1_WC0_PKT_AVAIL_FIFO_ERROR_SHIFT                                               12
+  #define BRB_REG_INT_STS_CLR_1_WC0_COS_CNT_FIFO_ERROR                                                       (0x1<<13) // COS counter FIFO error in write client 0 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_1_WC0_COS_CNT_FIFO_ERROR_SHIFT                                                 13
+  #define BRB_REG_INT_STS_CLR_1_WC0_NOTIFY_FIFO_ERROR                                                        (0x1<<14) // Notify FIFO error in write client 0.
+  #define BRB_REG_INT_STS_CLR_1_WC0_NOTIFY_FIFO_ERROR_SHIFT                                                  14
+  #define BRB_REG_INT_STS_CLR_1_WC0_LL_REQ_FIFO_ERROR                                                        (0x1<<15) // LL req error in write client 0.
+  #define BRB_REG_INT_STS_CLR_1_WC0_LL_REQ_FIFO_ERROR_SHIFT                                                  15
+  #define BRB_REG_INT_STS_CLR_1_WC0_LL_PA_CNT_ERROR                                                          (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
+  #define BRB_REG_INT_STS_CLR_1_WC0_LL_PA_CNT_ERROR_SHIFT                                                    16
+  #define BRB_REG_INT_STS_CLR_1_WC0_BB_PA_CNT_ERROR                                                          (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
+  #define BRB_REG_INT_STS_CLR_1_WC0_BB_PA_CNT_ERROR_SHIFT                                                    17
+  #define BRB_REG_INT_STS_CLR_1_WC1_INP_FIFO_ERROR                                                           (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_1_WC1_INP_FIFO_ERROR_SHIFT                                                     18
+  #define BRB_REG_INT_STS_CLR_1_WC1_SOP_FIFO_ERROR                                                           (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_1_WC1_SOP_FIFO_ERROR_SHIFT                                                     19
+  #define BRB_REG_INT_STS_CLR_1_WC1_EOP_FIFO_ERROR                                                           (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_1_WC1_EOP_FIFO_ERROR_SHIFT                                                     20
+  #define BRB_REG_INT_STS_CLR_1_WC1_QUEUE_FIFO_ERROR                                                         (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_1_WC1_QUEUE_FIFO_ERROR_SHIFT                                                   21
+  #define BRB_REG_INT_STS_CLR_1_WC1_FREE_POINT_FIFO_ERROR                                                    (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_1_WC1_FREE_POINT_FIFO_ERROR_SHIFT                                              22
+  #define BRB_REG_INT_STS_CLR_1_WC1_NEXT_POINT_FIFO_ERROR                                                    (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_1_WC1_NEXT_POINT_FIFO_ERROR_SHIFT                                              23
+  #define BRB_REG_INT_STS_CLR_1_WC1_STRT_FIFO_ERROR                                                          (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_1_WC1_STRT_FIFO_ERROR_SHIFT                                                    24
+  #define BRB_REG_INT_STS_CLR_1_WC1_SECOND_DSCR_FIFO_ERROR                                                   (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_1_WC1_SECOND_DSCR_FIFO_ERROR_SHIFT                                             25
+  #define BRB_REG_INT_STS_CLR_1_WC1_PKT_AVAIL_FIFO_ERROR                                                     (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 1 RX_INT ::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_1_WC1_PKT_AVAIL_FIFO_ERROR_SHIFT                                               26
+  #define BRB_REG_INT_STS_CLR_1_WC1_COS_CNT_FIFO_ERROR                                                       (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_1_WC1_COS_CNT_FIFO_ERROR_SHIFT                                                 27
+  #define BRB_REG_INT_STS_CLR_1_WC1_NOTIFY_FIFO_ERROR                                                        (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_1_WC1_NOTIFY_FIFO_ERROR_SHIFT                                                  28
+  #define BRB_REG_INT_STS_CLR_1_WC1_LL_REQ_FIFO_ERROR                                                        (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_1_WC1_LL_REQ_FIFO_ERROR_SHIFT                                                  29
+  #define BRB_REG_INT_STS_CLR_1_WC1_LL_PA_CNT_ERROR                                                          (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_1_WC1_LL_PA_CNT_ERROR_SHIFT                                                    30
+  #define BRB_REG_INT_STS_CLR_1_WC1_BB_PA_CNT_ERROR                                                          (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_1_WC1_BB_PA_CNT_ERROR_SHIFT                                                    31
+#define BRB_REG_INT_STS_2                                                                                    0x3400f0UL //Access:R    DataWidth:0x1c   // Multi Field Register.
+  #define BRB_REG_INT_STS_2_WC2_INP_FIFO_ERROR                                                               (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC2_INP_FIFO_ERROR_SHIFT                                                         0
+  #define BRB_REG_INT_STS_2_WC2_SOP_FIFO_ERROR                                                               (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC2_SOP_FIFO_ERROR_SHIFT                                                         1
+  #define BRB_REG_INT_STS_2_WC2_EOP_FIFO_ERROR                                                               (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC2_EOP_FIFO_ERROR_SHIFT                                                         2
+  #define BRB_REG_INT_STS_2_WC2_QUEUE_FIFO_ERROR                                                             (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC2_QUEUE_FIFO_ERROR_SHIFT                                                       3
+  #define BRB_REG_INT_STS_2_WC2_FREE_POINT_FIFO_ERROR                                                        (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC2_FREE_POINT_FIFO_ERROR_SHIFT                                                  4
+  #define BRB_REG_INT_STS_2_WC2_NEXT_POINT_FIFO_ERROR                                                        (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC2_NEXT_POINT_FIFO_ERROR_SHIFT                                                  5
+  #define BRB_REG_INT_STS_2_WC2_STRT_FIFO_ERROR                                                              (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC2_STRT_FIFO_ERROR_SHIFT                                                        6
+  #define BRB_REG_INT_STS_2_WC2_SECOND_DSCR_FIFO_ERROR                                                       (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC2_SECOND_DSCR_FIFO_ERROR_SHIFT                                                 7
+  #define BRB_REG_INT_STS_2_WC2_PKT_AVAIL_FIFO_ERROR                                                         (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 2 RX_INT ::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC2_PKT_AVAIL_FIFO_ERROR_SHIFT                                                   8
+  #define BRB_REG_INT_STS_2_WC2_COS_CNT_FIFO_ERROR                                                           (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC2_COS_CNT_FIFO_ERROR_SHIFT                                                     9
+  #define BRB_REG_INT_STS_2_WC2_NOTIFY_FIFO_ERROR                                                            (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC2_NOTIFY_FIFO_ERROR_SHIFT                                                      10
+  #define BRB_REG_INT_STS_2_WC2_LL_REQ_FIFO_ERROR                                                            (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC2_LL_REQ_FIFO_ERROR_SHIFT                                                      11
+  #define BRB_REG_INT_STS_2_WC2_LL_PA_CNT_ERROR                                                              (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC2_LL_PA_CNT_ERROR_SHIFT                                                        12
+  #define BRB_REG_INT_STS_2_WC2_BB_PA_CNT_ERROR                                                              (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC2_BB_PA_CNT_ERROR_SHIFT                                                        13
+  #define BRB_REG_INT_STS_2_WC3_INP_FIFO_ERROR                                                               (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC3_INP_FIFO_ERROR_SHIFT                                                         14
+  #define BRB_REG_INT_STS_2_WC3_SOP_FIFO_ERROR                                                               (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC3_SOP_FIFO_ERROR_SHIFT                                                         15
+  #define BRB_REG_INT_STS_2_WC3_EOP_FIFO_ERROR                                                               (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC3_EOP_FIFO_ERROR_SHIFT                                                         16
+  #define BRB_REG_INT_STS_2_WC3_QUEUE_FIFO_ERROR                                                             (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC3_QUEUE_FIFO_ERROR_SHIFT                                                       17
+  #define BRB_REG_INT_STS_2_WC3_FREE_POINT_FIFO_ERROR                                                        (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC3_FREE_POINT_FIFO_ERROR_SHIFT                                                  18
+  #define BRB_REG_INT_STS_2_WC3_NEXT_POINT_FIFO_ERROR                                                        (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC3_NEXT_POINT_FIFO_ERROR_SHIFT                                                  19
+  #define BRB_REG_INT_STS_2_WC3_STRT_FIFO_ERROR                                                              (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC3_STRT_FIFO_ERROR_SHIFT                                                        20
+  #define BRB_REG_INT_STS_2_WC3_SECOND_DSCR_FIFO_ERROR                                                       (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC3_SECOND_DSCR_FIFO_ERROR_SHIFT                                                 21
+  #define BRB_REG_INT_STS_2_WC3_PKT_AVAIL_FIFO_ERROR                                                         (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 3 RX_INT ::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC3_PKT_AVAIL_FIFO_ERROR_SHIFT                                                   22
+  #define BRB_REG_INT_STS_2_WC3_COS_CNT_FIFO_ERROR                                                           (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC3_COS_CNT_FIFO_ERROR_SHIFT                                                     23
+  #define BRB_REG_INT_STS_2_WC3_NOTIFY_FIFO_ERROR                                                            (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC3_NOTIFY_FIFO_ERROR_SHIFT                                                      24
+  #define BRB_REG_INT_STS_2_WC3_LL_REQ_FIFO_ERROR                                                            (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC3_LL_REQ_FIFO_ERROR_SHIFT                                                      25
+  #define BRB_REG_INT_STS_2_WC3_LL_PA_CNT_ERROR                                                              (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC3_LL_PA_CNT_ERROR_SHIFT                                                        26
+  #define BRB_REG_INT_STS_2_WC3_BB_PA_CNT_ERROR                                                              (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_2_WC3_BB_PA_CNT_ERROR_SHIFT                                                        27
+#define BRB_REG_INT_MASK_2                                                                                   0x3400f4UL //Access:RW   DataWidth:0x1c   // Multi Field Register.
+  #define BRB_REG_INT_MASK_2_WC2_INP_FIFO_ERROR                                                              (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_INP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_2_WC2_INP_FIFO_ERROR_SHIFT                                                        0
+  #define BRB_REG_INT_MASK_2_WC2_SOP_FIFO_ERROR                                                              (0x1<<1) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_SOP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_2_WC2_SOP_FIFO_ERROR_SHIFT                                                        1
+  #define BRB_REG_INT_MASK_2_WC2_EOP_FIFO_ERROR                                                              (0x1<<2) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_EOP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_2_WC2_EOP_FIFO_ERROR_SHIFT                                                        2
+  #define BRB_REG_INT_MASK_2_WC2_QUEUE_FIFO_ERROR                                                            (0x1<<3) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_QUEUE_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_2_WC2_QUEUE_FIFO_ERROR_SHIFT                                                      3
+  #define BRB_REG_INT_MASK_2_WC2_FREE_POINT_FIFO_ERROR                                                       (0x1<<4) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_FREE_POINT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_2_WC2_FREE_POINT_FIFO_ERROR_SHIFT                                                 4
+  #define BRB_REG_INT_MASK_2_WC2_NEXT_POINT_FIFO_ERROR                                                       (0x1<<5) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_NEXT_POINT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_2_WC2_NEXT_POINT_FIFO_ERROR_SHIFT                                                 5
+  #define BRB_REG_INT_MASK_2_WC2_STRT_FIFO_ERROR                                                             (0x1<<6) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_STRT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_2_WC2_STRT_FIFO_ERROR_SHIFT                                                       6
+  #define BRB_REG_INT_MASK_2_WC2_SECOND_DSCR_FIFO_ERROR                                                      (0x1<<7) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_SECOND_DSCR_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_2_WC2_SECOND_DSCR_FIFO_ERROR_SHIFT                                                7
+  #define BRB_REG_INT_MASK_2_WC2_PKT_AVAIL_FIFO_ERROR                                                        (0x1<<8) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_PKT_AVAIL_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_2_WC2_PKT_AVAIL_FIFO_ERROR_SHIFT                                                  8
+  #define BRB_REG_INT_MASK_2_WC2_COS_CNT_FIFO_ERROR                                                          (0x1<<9) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_COS_CNT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_2_WC2_COS_CNT_FIFO_ERROR_SHIFT                                                    9
+  #define BRB_REG_INT_MASK_2_WC2_NOTIFY_FIFO_ERROR                                                           (0x1<<10) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_NOTIFY_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_2_WC2_NOTIFY_FIFO_ERROR_SHIFT                                                     10
+  #define BRB_REG_INT_MASK_2_WC2_LL_REQ_FIFO_ERROR                                                           (0x1<<11) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_LL_REQ_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_2_WC2_LL_REQ_FIFO_ERROR_SHIFT                                                     11
+  #define BRB_REG_INT_MASK_2_WC2_LL_PA_CNT_ERROR                                                             (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_LL_PA_CNT_ERROR .
+  #define BRB_REG_INT_MASK_2_WC2_LL_PA_CNT_ERROR_SHIFT                                                       12
+  #define BRB_REG_INT_MASK_2_WC2_BB_PA_CNT_ERROR                                                             (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_BB_PA_CNT_ERROR .
+  #define BRB_REG_INT_MASK_2_WC2_BB_PA_CNT_ERROR_SHIFT                                                       13
+  #define BRB_REG_INT_MASK_2_WC3_INP_FIFO_ERROR                                                              (0x1<<14) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_INP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_2_WC3_INP_FIFO_ERROR_SHIFT                                                        14
+  #define BRB_REG_INT_MASK_2_WC3_SOP_FIFO_ERROR                                                              (0x1<<15) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_SOP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_2_WC3_SOP_FIFO_ERROR_SHIFT                                                        15
+  #define BRB_REG_INT_MASK_2_WC3_EOP_FIFO_ERROR                                                              (0x1<<16) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_EOP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_2_WC3_EOP_FIFO_ERROR_SHIFT                                                        16
+  #define BRB_REG_INT_MASK_2_WC3_QUEUE_FIFO_ERROR                                                            (0x1<<17) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_QUEUE_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_2_WC3_QUEUE_FIFO_ERROR_SHIFT                                                      17
+  #define BRB_REG_INT_MASK_2_WC3_FREE_POINT_FIFO_ERROR                                                       (0x1<<18) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_FREE_POINT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_2_WC3_FREE_POINT_FIFO_ERROR_SHIFT                                                 18
+  #define BRB_REG_INT_MASK_2_WC3_NEXT_POINT_FIFO_ERROR                                                       (0x1<<19) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_NEXT_POINT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_2_WC3_NEXT_POINT_FIFO_ERROR_SHIFT                                                 19
+  #define BRB_REG_INT_MASK_2_WC3_STRT_FIFO_ERROR                                                             (0x1<<20) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_STRT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_2_WC3_STRT_FIFO_ERROR_SHIFT                                                       20
+  #define BRB_REG_INT_MASK_2_WC3_SECOND_DSCR_FIFO_ERROR                                                      (0x1<<21) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_SECOND_DSCR_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_2_WC3_SECOND_DSCR_FIFO_ERROR_SHIFT                                                21
+  #define BRB_REG_INT_MASK_2_WC3_PKT_AVAIL_FIFO_ERROR                                                        (0x1<<22) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_PKT_AVAIL_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_2_WC3_PKT_AVAIL_FIFO_ERROR_SHIFT                                                  22
+  #define BRB_REG_INT_MASK_2_WC3_COS_CNT_FIFO_ERROR                                                          (0x1<<23) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_COS_CNT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_2_WC3_COS_CNT_FIFO_ERROR_SHIFT                                                    23
+  #define BRB_REG_INT_MASK_2_WC3_NOTIFY_FIFO_ERROR                                                           (0x1<<24) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_NOTIFY_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_2_WC3_NOTIFY_FIFO_ERROR_SHIFT                                                     24
+  #define BRB_REG_INT_MASK_2_WC3_LL_REQ_FIFO_ERROR                                                           (0x1<<25) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_LL_REQ_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_2_WC3_LL_REQ_FIFO_ERROR_SHIFT                                                     25
+  #define BRB_REG_INT_MASK_2_WC3_LL_PA_CNT_ERROR                                                             (0x1<<26) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_LL_PA_CNT_ERROR .
+  #define BRB_REG_INT_MASK_2_WC3_LL_PA_CNT_ERROR_SHIFT                                                       26
+  #define BRB_REG_INT_MASK_2_WC3_BB_PA_CNT_ERROR                                                             (0x1<<27) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_BB_PA_CNT_ERROR .
+  #define BRB_REG_INT_MASK_2_WC3_BB_PA_CNT_ERROR_SHIFT                                                       27
+#define BRB_REG_INT_STS_WR_2                                                                                 0x3400f8UL //Access:WR   DataWidth:0x1c   // Multi Field Register.
+  #define BRB_REG_INT_STS_WR_2_WC2_INP_FIFO_ERROR                                                            (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC2_INP_FIFO_ERROR_SHIFT                                                      0
+  #define BRB_REG_INT_STS_WR_2_WC2_SOP_FIFO_ERROR                                                            (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC2_SOP_FIFO_ERROR_SHIFT                                                      1
+  #define BRB_REG_INT_STS_WR_2_WC2_EOP_FIFO_ERROR                                                            (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC2_EOP_FIFO_ERROR_SHIFT                                                      2
+  #define BRB_REG_INT_STS_WR_2_WC2_QUEUE_FIFO_ERROR                                                          (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC2_QUEUE_FIFO_ERROR_SHIFT                                                    3
+  #define BRB_REG_INT_STS_WR_2_WC2_FREE_POINT_FIFO_ERROR                                                     (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC2_FREE_POINT_FIFO_ERROR_SHIFT                                               4
+  #define BRB_REG_INT_STS_WR_2_WC2_NEXT_POINT_FIFO_ERROR                                                     (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC2_NEXT_POINT_FIFO_ERROR_SHIFT                                               5
+  #define BRB_REG_INT_STS_WR_2_WC2_STRT_FIFO_ERROR                                                           (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC2_STRT_FIFO_ERROR_SHIFT                                                     6
+  #define BRB_REG_INT_STS_WR_2_WC2_SECOND_DSCR_FIFO_ERROR                                                    (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC2_SECOND_DSCR_FIFO_ERROR_SHIFT                                              7
+  #define BRB_REG_INT_STS_WR_2_WC2_PKT_AVAIL_FIFO_ERROR                                                      (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 2 RX_INT ::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC2_PKT_AVAIL_FIFO_ERROR_SHIFT                                                8
+  #define BRB_REG_INT_STS_WR_2_WC2_COS_CNT_FIFO_ERROR                                                        (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC2_COS_CNT_FIFO_ERROR_SHIFT                                                  9
+  #define BRB_REG_INT_STS_WR_2_WC2_NOTIFY_FIFO_ERROR                                                         (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC2_NOTIFY_FIFO_ERROR_SHIFT                                                   10
+  #define BRB_REG_INT_STS_WR_2_WC2_LL_REQ_FIFO_ERROR                                                         (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC2_LL_REQ_FIFO_ERROR_SHIFT                                                   11
+  #define BRB_REG_INT_STS_WR_2_WC2_LL_PA_CNT_ERROR                                                           (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC2_LL_PA_CNT_ERROR_SHIFT                                                     12
+  #define BRB_REG_INT_STS_WR_2_WC2_BB_PA_CNT_ERROR                                                           (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC2_BB_PA_CNT_ERROR_SHIFT                                                     13
+  #define BRB_REG_INT_STS_WR_2_WC3_INP_FIFO_ERROR                                                            (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC3_INP_FIFO_ERROR_SHIFT                                                      14
+  #define BRB_REG_INT_STS_WR_2_WC3_SOP_FIFO_ERROR                                                            (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC3_SOP_FIFO_ERROR_SHIFT                                                      15
+  #define BRB_REG_INT_STS_WR_2_WC3_EOP_FIFO_ERROR                                                            (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC3_EOP_FIFO_ERROR_SHIFT                                                      16
+  #define BRB_REG_INT_STS_WR_2_WC3_QUEUE_FIFO_ERROR                                                          (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC3_QUEUE_FIFO_ERROR_SHIFT                                                    17
+  #define BRB_REG_INT_STS_WR_2_WC3_FREE_POINT_FIFO_ERROR                                                     (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC3_FREE_POINT_FIFO_ERROR_SHIFT                                               18
+  #define BRB_REG_INT_STS_WR_2_WC3_NEXT_POINT_FIFO_ERROR                                                     (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC3_NEXT_POINT_FIFO_ERROR_SHIFT                                               19
+  #define BRB_REG_INT_STS_WR_2_WC3_STRT_FIFO_ERROR                                                           (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC3_STRT_FIFO_ERROR_SHIFT                                                     20
+  #define BRB_REG_INT_STS_WR_2_WC3_SECOND_DSCR_FIFO_ERROR                                                    (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC3_SECOND_DSCR_FIFO_ERROR_SHIFT                                              21
+  #define BRB_REG_INT_STS_WR_2_WC3_PKT_AVAIL_FIFO_ERROR                                                      (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 3 RX_INT ::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC3_PKT_AVAIL_FIFO_ERROR_SHIFT                                                22
+  #define BRB_REG_INT_STS_WR_2_WC3_COS_CNT_FIFO_ERROR                                                        (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC3_COS_CNT_FIFO_ERROR_SHIFT                                                  23
+  #define BRB_REG_INT_STS_WR_2_WC3_NOTIFY_FIFO_ERROR                                                         (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC3_NOTIFY_FIFO_ERROR_SHIFT                                                   24
+  #define BRB_REG_INT_STS_WR_2_WC3_LL_REQ_FIFO_ERROR                                                         (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC3_LL_REQ_FIFO_ERROR_SHIFT                                                   25
+  #define BRB_REG_INT_STS_WR_2_WC3_LL_PA_CNT_ERROR                                                           (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC3_LL_PA_CNT_ERROR_SHIFT                                                     26
+  #define BRB_REG_INT_STS_WR_2_WC3_BB_PA_CNT_ERROR                                                           (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_2_WC3_BB_PA_CNT_ERROR_SHIFT                                                     27
+#define BRB_REG_INT_STS_CLR_2                                                                                0x3400fcUL //Access:RC   DataWidth:0x1c   // Multi Field Register.
+  #define BRB_REG_INT_STS_CLR_2_WC2_INP_FIFO_ERROR                                                           (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC2_INP_FIFO_ERROR_SHIFT                                                     0
+  #define BRB_REG_INT_STS_CLR_2_WC2_SOP_FIFO_ERROR                                                           (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC2_SOP_FIFO_ERROR_SHIFT                                                     1
+  #define BRB_REG_INT_STS_CLR_2_WC2_EOP_FIFO_ERROR                                                           (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC2_EOP_FIFO_ERROR_SHIFT                                                     2
+  #define BRB_REG_INT_STS_CLR_2_WC2_QUEUE_FIFO_ERROR                                                         (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC2_QUEUE_FIFO_ERROR_SHIFT                                                   3
+  #define BRB_REG_INT_STS_CLR_2_WC2_FREE_POINT_FIFO_ERROR                                                    (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC2_FREE_POINT_FIFO_ERROR_SHIFT                                              4
+  #define BRB_REG_INT_STS_CLR_2_WC2_NEXT_POINT_FIFO_ERROR                                                    (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC2_NEXT_POINT_FIFO_ERROR_SHIFT                                              5
+  #define BRB_REG_INT_STS_CLR_2_WC2_STRT_FIFO_ERROR                                                          (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC2_STRT_FIFO_ERROR_SHIFT                                                    6
+  #define BRB_REG_INT_STS_CLR_2_WC2_SECOND_DSCR_FIFO_ERROR                                                   (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC2_SECOND_DSCR_FIFO_ERROR_SHIFT                                             7
+  #define BRB_REG_INT_STS_CLR_2_WC2_PKT_AVAIL_FIFO_ERROR                                                     (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 2 RX_INT ::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC2_PKT_AVAIL_FIFO_ERROR_SHIFT                                               8
+  #define BRB_REG_INT_STS_CLR_2_WC2_COS_CNT_FIFO_ERROR                                                       (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC2_COS_CNT_FIFO_ERROR_SHIFT                                                 9
+  #define BRB_REG_INT_STS_CLR_2_WC2_NOTIFY_FIFO_ERROR                                                        (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC2_NOTIFY_FIFO_ERROR_SHIFT                                                  10
+  #define BRB_REG_INT_STS_CLR_2_WC2_LL_REQ_FIFO_ERROR                                                        (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC2_LL_REQ_FIFO_ERROR_SHIFT                                                  11
+  #define BRB_REG_INT_STS_CLR_2_WC2_LL_PA_CNT_ERROR                                                          (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC2_LL_PA_CNT_ERROR_SHIFT                                                    12
+  #define BRB_REG_INT_STS_CLR_2_WC2_BB_PA_CNT_ERROR                                                          (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC2_BB_PA_CNT_ERROR_SHIFT                                                    13
+  #define BRB_REG_INT_STS_CLR_2_WC3_INP_FIFO_ERROR                                                           (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC3_INP_FIFO_ERROR_SHIFT                                                     14
+  #define BRB_REG_INT_STS_CLR_2_WC3_SOP_FIFO_ERROR                                                           (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC3_SOP_FIFO_ERROR_SHIFT                                                     15
+  #define BRB_REG_INT_STS_CLR_2_WC3_EOP_FIFO_ERROR                                                           (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC3_EOP_FIFO_ERROR_SHIFT                                                     16
+  #define BRB_REG_INT_STS_CLR_2_WC3_QUEUE_FIFO_ERROR                                                         (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC3_QUEUE_FIFO_ERROR_SHIFT                                                   17
+  #define BRB_REG_INT_STS_CLR_2_WC3_FREE_POINT_FIFO_ERROR                                                    (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC3_FREE_POINT_FIFO_ERROR_SHIFT                                              18
+  #define BRB_REG_INT_STS_CLR_2_WC3_NEXT_POINT_FIFO_ERROR                                                    (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC3_NEXT_POINT_FIFO_ERROR_SHIFT                                              19
+  #define BRB_REG_INT_STS_CLR_2_WC3_STRT_FIFO_ERROR                                                          (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC3_STRT_FIFO_ERROR_SHIFT                                                    20
+  #define BRB_REG_INT_STS_CLR_2_WC3_SECOND_DSCR_FIFO_ERROR                                                   (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC3_SECOND_DSCR_FIFO_ERROR_SHIFT                                             21
+  #define BRB_REG_INT_STS_CLR_2_WC3_PKT_AVAIL_FIFO_ERROR                                                     (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 3 RX_INT ::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC3_PKT_AVAIL_FIFO_ERROR_SHIFT                                               22
+  #define BRB_REG_INT_STS_CLR_2_WC3_COS_CNT_FIFO_ERROR                                                       (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC3_COS_CNT_FIFO_ERROR_SHIFT                                                 23
+  #define BRB_REG_INT_STS_CLR_2_WC3_NOTIFY_FIFO_ERROR                                                        (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC3_NOTIFY_FIFO_ERROR_SHIFT                                                  24
+  #define BRB_REG_INT_STS_CLR_2_WC3_LL_REQ_FIFO_ERROR                                                        (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC3_LL_REQ_FIFO_ERROR_SHIFT                                                  25
+  #define BRB_REG_INT_STS_CLR_2_WC3_LL_PA_CNT_ERROR                                                          (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC3_LL_PA_CNT_ERROR_SHIFT                                                    26
+  #define BRB_REG_INT_STS_CLR_2_WC3_BB_PA_CNT_ERROR                                                          (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_2_WC3_BB_PA_CNT_ERROR_SHIFT                                                    27
+#define BRB_REG_INT_STS_3                                                                                    0x340108UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define BRB_REG_INT_STS_3_RC_PKT0_SIDE_FIFO_ERROR                                                          (0x1<<1) // Read packet client PRM side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT                                                    1
+  #define BRB_REG_INT_STS_3_RC_PKT0_REQ_FIFO_ERROR                                                           (0x1<<2) // Read packet client PRM request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT0_REQ_FIFO_ERROR_SHIFT                                                     2
+  #define BRB_REG_INT_STS_3_RC_PKT0_BLK_FIFO_ERROR                                                           (0x1<<3) // Read packet client PRM block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT                                                     3
+  #define BRB_REG_INT_STS_3_RC_PKT0_RLS_LEFT_FIFO_ERROR                                                      (0x1<<4) // Read packet client PRM releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT0_RLS_LEFT_FIFO_ERROR_SHIFT                                                4
+  #define BRB_REG_INT_STS_3_RC_PKT0_STRT_PTR_FIFO_ERROR                                                      (0x1<<5) // Read packet client PRM start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT0_STRT_PTR_FIFO_ERROR_SHIFT                                                5
+  #define BRB_REG_INT_STS_3_RC_PKT0_SECOND_PTR_FIFO_ERROR                                                    (0x1<<6) // Read packet client PRM second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT0_SECOND_PTR_FIFO_ERROR_SHIFT                                              6
+  #define BRB_REG_INT_STS_3_RC_PKT0_RSP_FIFO_ERROR                                                           (0x1<<7) // Read packet client PRM response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT                                                     7
+  #define BRB_REG_INT_STS_3_RC_PKT0_DSCR_FIFO_ERROR                                                          (0x1<<8) // Read packet client PRM descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT                                                    8
+  #define BRB_REG_INT_STS_3_RC_PKT1_SIDE_FIFO_ERROR                                                          (0x1<<9) // Read packet client MSDM side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT1_SIDE_FIFO_ERROR_SHIFT                                                    9
+  #define BRB_REG_INT_STS_3_RC_PKT1_REQ_FIFO_ERROR                                                           (0x1<<10) // Read packet client MSDM request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT1_REQ_FIFO_ERROR_SHIFT                                                     10
+  #define BRB_REG_INT_STS_3_RC_PKT1_BLK_FIFO_ERROR                                                           (0x1<<11) // Read packet client MSDM block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT1_BLK_FIFO_ERROR_SHIFT                                                     11
+  #define BRB_REG_INT_STS_3_RC_PKT1_RLS_LEFT_FIFO_ERROR                                                      (0x1<<12) // Read packet client MSDM releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT1_RLS_LEFT_FIFO_ERROR_SHIFT                                                12
+  #define BRB_REG_INT_STS_3_RC_PKT1_STRT_PTR_FIFO_ERROR                                                      (0x1<<13) // Read packet client MSDM start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT1_STRT_PTR_FIFO_ERROR_SHIFT                                                13
+  #define BRB_REG_INT_STS_3_RC_PKT1_SECOND_PTR_FIFO_ERROR                                                    (0x1<<14) // Read packet client MSDM second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT1_SECOND_PTR_FIFO_ERROR_SHIFT                                              14
+  #define BRB_REG_INT_STS_3_RC_PKT1_RSP_FIFO_ERROR                                                           (0x1<<15) // Read packet client MSDM response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT1_RSP_FIFO_ERROR_SHIFT                                                     15
+  #define BRB_REG_INT_STS_3_RC_PKT1_DSCR_FIFO_ERROR                                                          (0x1<<16) // Read packet client MSDM descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT1_DSCR_FIFO_ERROR_SHIFT                                                    16
+  #define BRB_REG_INT_STS_3_RC_PKT2_SIDE_FIFO_ERROR                                                          (0x1<<17) // Read packet client TSDM side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT2_SIDE_FIFO_ERROR_SHIFT                                                    17
+  #define BRB_REG_INT_STS_3_RC_PKT2_REQ_FIFO_ERROR                                                           (0x1<<18) // Read packet client TSDM request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT2_REQ_FIFO_ERROR_SHIFT                                                     18
+  #define BRB_REG_INT_STS_3_RC_PKT2_BLK_FIFO_ERROR                                                           (0x1<<19) // Read packet client TSDM block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT2_BLK_FIFO_ERROR_SHIFT                                                     19
+  #define BRB_REG_INT_STS_3_RC_PKT2_RLS_LEFT_FIFO_ERROR                                                      (0x1<<20) // Read packet client TSDM releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT2_RLS_LEFT_FIFO_ERROR_SHIFT                                                20
+  #define BRB_REG_INT_STS_3_RC_PKT2_STRT_PTR_FIFO_ERROR                                                      (0x1<<21) // Read packet client TSDM start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT2_STRT_PTR_FIFO_ERROR_SHIFT                                                21
+  #define BRB_REG_INT_STS_3_RC_PKT2_SECOND_PTR_FIFO_ERROR                                                    (0x1<<22) // Read packet client TSDM second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT2_SECOND_PTR_FIFO_ERROR_SHIFT                                              22
+  #define BRB_REG_INT_STS_3_RC_PKT2_RSP_FIFO_ERROR                                                           (0x1<<23) // Read packet client TSDM response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT2_RSP_FIFO_ERROR_SHIFT                                                     23
+  #define BRB_REG_INT_STS_3_RC_PKT2_DSCR_FIFO_ERROR                                                          (0x1<<24) // Read packet client TSDM descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT2_DSCR_FIFO_ERROR_SHIFT                                                    24
+  #define BRB_REG_INT_STS_3_RC_PKT3_SIDE_FIFO_ERROR                                                          (0x1<<25) // Read packet client parser side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT3_SIDE_FIFO_ERROR_SHIFT                                                    25
+  #define BRB_REG_INT_STS_3_RC_PKT3_REQ_FIFO_ERROR                                                           (0x1<<26) // Read packet client parser request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT3_REQ_FIFO_ERROR_SHIFT                                                     26
+  #define BRB_REG_INT_STS_3_RC_PKT3_BLK_FIFO_ERROR                                                           (0x1<<27) // Read packet client parser block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT3_BLK_FIFO_ERROR_SHIFT                                                     27
+  #define BRB_REG_INT_STS_3_RC_PKT3_RLS_LEFT_FIFO_ERROR                                                      (0x1<<28) // Read packet client parser releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT3_RLS_LEFT_FIFO_ERROR_SHIFT                                                28
+  #define BRB_REG_INT_STS_3_RC_PKT3_STRT_PTR_FIFO_ERROR                                                      (0x1<<29) // Read packet client parser start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT3_STRT_PTR_FIFO_ERROR_SHIFT                                                29
+  #define BRB_REG_INT_STS_3_RC_PKT3_SECOND_PTR_FIFO_ERROR                                                    (0x1<<30) // Read packet client parser second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT                                              30
+  #define BRB_REG_INT_STS_3_RC_PKT3_RSP_FIFO_ERROR                                                           (0x1<<31) // Read packet client parser response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_3_RC_PKT3_RSP_FIFO_ERROR_SHIFT                                                     31
+#define BRB_REG_INT_MASK_3                                                                                   0x34010cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define BRB_REG_INT_MASK_3_RC_PKT0_SIDE_FIFO_ERROR                                                         (0x1<<1) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT0_SIDE_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT                                                   1
+  #define BRB_REG_INT_MASK_3_RC_PKT0_REQ_FIFO_ERROR                                                          (0x1<<2) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT0_REQ_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT0_REQ_FIFO_ERROR_SHIFT                                                    2
+  #define BRB_REG_INT_MASK_3_RC_PKT0_BLK_FIFO_ERROR                                                          (0x1<<3) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT0_BLK_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT                                                    3
+  #define BRB_REG_INT_MASK_3_RC_PKT0_RLS_LEFT_FIFO_ERROR                                                     (0x1<<4) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT0_RLS_LEFT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT0_RLS_LEFT_FIFO_ERROR_SHIFT                                               4
+  #define BRB_REG_INT_MASK_3_RC_PKT0_STRT_PTR_FIFO_ERROR                                                     (0x1<<5) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT0_STRT_PTR_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT0_STRT_PTR_FIFO_ERROR_SHIFT                                               5
+  #define BRB_REG_INT_MASK_3_RC_PKT0_SECOND_PTR_FIFO_ERROR                                                   (0x1<<6) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT0_SECOND_PTR_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT0_SECOND_PTR_FIFO_ERROR_SHIFT                                             6
+  #define BRB_REG_INT_MASK_3_RC_PKT0_RSP_FIFO_ERROR                                                          (0x1<<7) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT0_RSP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT                                                    7
+  #define BRB_REG_INT_MASK_3_RC_PKT0_DSCR_FIFO_ERROR                                                         (0x1<<8) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT0_DSCR_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT                                                   8
+  #define BRB_REG_INT_MASK_3_RC_PKT1_SIDE_FIFO_ERROR                                                         (0x1<<9) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT1_SIDE_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT1_SIDE_FIFO_ERROR_SHIFT                                                   9
+  #define BRB_REG_INT_MASK_3_RC_PKT1_REQ_FIFO_ERROR                                                          (0x1<<10) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT1_REQ_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT1_REQ_FIFO_ERROR_SHIFT                                                    10
+  #define BRB_REG_INT_MASK_3_RC_PKT1_BLK_FIFO_ERROR                                                          (0x1<<11) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT1_BLK_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT1_BLK_FIFO_ERROR_SHIFT                                                    11
+  #define BRB_REG_INT_MASK_3_RC_PKT1_RLS_LEFT_FIFO_ERROR                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT1_RLS_LEFT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT1_RLS_LEFT_FIFO_ERROR_SHIFT                                               12
+  #define BRB_REG_INT_MASK_3_RC_PKT1_STRT_PTR_FIFO_ERROR                                                     (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT1_STRT_PTR_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT1_STRT_PTR_FIFO_ERROR_SHIFT                                               13
+  #define BRB_REG_INT_MASK_3_RC_PKT1_SECOND_PTR_FIFO_ERROR                                                   (0x1<<14) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT1_SECOND_PTR_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT1_SECOND_PTR_FIFO_ERROR_SHIFT                                             14
+  #define BRB_REG_INT_MASK_3_RC_PKT1_RSP_FIFO_ERROR                                                          (0x1<<15) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT1_RSP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT1_RSP_FIFO_ERROR_SHIFT                                                    15
+  #define BRB_REG_INT_MASK_3_RC_PKT1_DSCR_FIFO_ERROR                                                         (0x1<<16) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT1_DSCR_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT1_DSCR_FIFO_ERROR_SHIFT                                                   16
+  #define BRB_REG_INT_MASK_3_RC_PKT2_SIDE_FIFO_ERROR                                                         (0x1<<17) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT2_SIDE_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT2_SIDE_FIFO_ERROR_SHIFT                                                   17
+  #define BRB_REG_INT_MASK_3_RC_PKT2_REQ_FIFO_ERROR                                                          (0x1<<18) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT2_REQ_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT2_REQ_FIFO_ERROR_SHIFT                                                    18
+  #define BRB_REG_INT_MASK_3_RC_PKT2_BLK_FIFO_ERROR                                                          (0x1<<19) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT2_BLK_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT2_BLK_FIFO_ERROR_SHIFT                                                    19
+  #define BRB_REG_INT_MASK_3_RC_PKT2_RLS_LEFT_FIFO_ERROR                                                     (0x1<<20) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT2_RLS_LEFT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT2_RLS_LEFT_FIFO_ERROR_SHIFT                                               20
+  #define BRB_REG_INT_MASK_3_RC_PKT2_STRT_PTR_FIFO_ERROR                                                     (0x1<<21) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT2_STRT_PTR_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT2_STRT_PTR_FIFO_ERROR_SHIFT                                               21
+  #define BRB_REG_INT_MASK_3_RC_PKT2_SECOND_PTR_FIFO_ERROR                                                   (0x1<<22) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT2_SECOND_PTR_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT2_SECOND_PTR_FIFO_ERROR_SHIFT                                             22
+  #define BRB_REG_INT_MASK_3_RC_PKT2_RSP_FIFO_ERROR                                                          (0x1<<23) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT2_RSP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT2_RSP_FIFO_ERROR_SHIFT                                                    23
+  #define BRB_REG_INT_MASK_3_RC_PKT2_DSCR_FIFO_ERROR                                                         (0x1<<24) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT2_DSCR_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT2_DSCR_FIFO_ERROR_SHIFT                                                   24
+  #define BRB_REG_INT_MASK_3_RC_PKT3_SIDE_FIFO_ERROR                                                         (0x1<<25) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT3_SIDE_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT3_SIDE_FIFO_ERROR_SHIFT                                                   25
+  #define BRB_REG_INT_MASK_3_RC_PKT3_REQ_FIFO_ERROR                                                          (0x1<<26) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT3_REQ_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT3_REQ_FIFO_ERROR_SHIFT                                                    26
+  #define BRB_REG_INT_MASK_3_RC_PKT3_BLK_FIFO_ERROR                                                          (0x1<<27) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT3_BLK_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT3_BLK_FIFO_ERROR_SHIFT                                                    27
+  #define BRB_REG_INT_MASK_3_RC_PKT3_RLS_LEFT_FIFO_ERROR                                                     (0x1<<28) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT3_RLS_LEFT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT3_RLS_LEFT_FIFO_ERROR_SHIFT                                               28
+  #define BRB_REG_INT_MASK_3_RC_PKT3_STRT_PTR_FIFO_ERROR                                                     (0x1<<29) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT3_STRT_PTR_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT3_STRT_PTR_FIFO_ERROR_SHIFT                                               29
+  #define BRB_REG_INT_MASK_3_RC_PKT3_SECOND_PTR_FIFO_ERROR                                                   (0x1<<30) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT3_SECOND_PTR_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT                                             30
+  #define BRB_REG_INT_MASK_3_RC_PKT3_RSP_FIFO_ERROR                                                          (0x1<<31) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT3_RSP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_3_RC_PKT3_RSP_FIFO_ERROR_SHIFT                                                    31
+#define BRB_REG_INT_STS_WR_3                                                                                 0x340110UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT0_SIDE_FIFO_ERROR                                                       (0x1<<1) // Read packet client PRM side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT                                                 1
+  #define BRB_REG_INT_STS_WR_3_RC_PKT0_REQ_FIFO_ERROR                                                        (0x1<<2) // Read packet client PRM request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT0_REQ_FIFO_ERROR_SHIFT                                                  2
+  #define BRB_REG_INT_STS_WR_3_RC_PKT0_BLK_FIFO_ERROR                                                        (0x1<<3) // Read packet client PRM block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT                                                  3
+  #define BRB_REG_INT_STS_WR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR                                                   (0x1<<4) // Read packet client PRM releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR_SHIFT                                             4
+  #define BRB_REG_INT_STS_WR_3_RC_PKT0_STRT_PTR_FIFO_ERROR                                                   (0x1<<5) // Read packet client PRM start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT0_STRT_PTR_FIFO_ERROR_SHIFT                                             5
+  #define BRB_REG_INT_STS_WR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR                                                 (0x1<<6) // Read packet client PRM second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR_SHIFT                                           6
+  #define BRB_REG_INT_STS_WR_3_RC_PKT0_RSP_FIFO_ERROR                                                        (0x1<<7) // Read packet client PRM response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT                                                  7
+  #define BRB_REG_INT_STS_WR_3_RC_PKT0_DSCR_FIFO_ERROR                                                       (0x1<<8) // Read packet client PRM descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT                                                 8
+  #define BRB_REG_INT_STS_WR_3_RC_PKT1_SIDE_FIFO_ERROR                                                       (0x1<<9) // Read packet client MSDM side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT1_SIDE_FIFO_ERROR_SHIFT                                                 9
+  #define BRB_REG_INT_STS_WR_3_RC_PKT1_REQ_FIFO_ERROR                                                        (0x1<<10) // Read packet client MSDM request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT1_REQ_FIFO_ERROR_SHIFT                                                  10
+  #define BRB_REG_INT_STS_WR_3_RC_PKT1_BLK_FIFO_ERROR                                                        (0x1<<11) // Read packet client MSDM block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT1_BLK_FIFO_ERROR_SHIFT                                                  11
+  #define BRB_REG_INT_STS_WR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR                                                   (0x1<<12) // Read packet client MSDM releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR_SHIFT                                             12
+  #define BRB_REG_INT_STS_WR_3_RC_PKT1_STRT_PTR_FIFO_ERROR                                                   (0x1<<13) // Read packet client MSDM start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT1_STRT_PTR_FIFO_ERROR_SHIFT                                             13
+  #define BRB_REG_INT_STS_WR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR                                                 (0x1<<14) // Read packet client MSDM second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR_SHIFT                                           14
+  #define BRB_REG_INT_STS_WR_3_RC_PKT1_RSP_FIFO_ERROR                                                        (0x1<<15) // Read packet client MSDM response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT1_RSP_FIFO_ERROR_SHIFT                                                  15
+  #define BRB_REG_INT_STS_WR_3_RC_PKT1_DSCR_FIFO_ERROR                                                       (0x1<<16) // Read packet client MSDM descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT1_DSCR_FIFO_ERROR_SHIFT                                                 16
+  #define BRB_REG_INT_STS_WR_3_RC_PKT2_SIDE_FIFO_ERROR                                                       (0x1<<17) // Read packet client TSDM side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT2_SIDE_FIFO_ERROR_SHIFT                                                 17
+  #define BRB_REG_INT_STS_WR_3_RC_PKT2_REQ_FIFO_ERROR                                                        (0x1<<18) // Read packet client TSDM request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT2_REQ_FIFO_ERROR_SHIFT                                                  18
+  #define BRB_REG_INT_STS_WR_3_RC_PKT2_BLK_FIFO_ERROR                                                        (0x1<<19) // Read packet client TSDM block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT2_BLK_FIFO_ERROR_SHIFT                                                  19
+  #define BRB_REG_INT_STS_WR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR                                                   (0x1<<20) // Read packet client TSDM releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR_SHIFT                                             20
+  #define BRB_REG_INT_STS_WR_3_RC_PKT2_STRT_PTR_FIFO_ERROR                                                   (0x1<<21) // Read packet client TSDM start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT2_STRT_PTR_FIFO_ERROR_SHIFT                                             21
+  #define BRB_REG_INT_STS_WR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR                                                 (0x1<<22) // Read packet client TSDM second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR_SHIFT                                           22
+  #define BRB_REG_INT_STS_WR_3_RC_PKT2_RSP_FIFO_ERROR                                                        (0x1<<23) // Read packet client TSDM response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT2_RSP_FIFO_ERROR_SHIFT                                                  23
+  #define BRB_REG_INT_STS_WR_3_RC_PKT2_DSCR_FIFO_ERROR                                                       (0x1<<24) // Read packet client TSDM descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT2_DSCR_FIFO_ERROR_SHIFT                                                 24
+  #define BRB_REG_INT_STS_WR_3_RC_PKT3_SIDE_FIFO_ERROR                                                       (0x1<<25) // Read packet client parser side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT3_SIDE_FIFO_ERROR_SHIFT                                                 25
+  #define BRB_REG_INT_STS_WR_3_RC_PKT3_REQ_FIFO_ERROR                                                        (0x1<<26) // Read packet client parser request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT3_REQ_FIFO_ERROR_SHIFT                                                  26
+  #define BRB_REG_INT_STS_WR_3_RC_PKT3_BLK_FIFO_ERROR                                                        (0x1<<27) // Read packet client parser block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT3_BLK_FIFO_ERROR_SHIFT                                                  27
+  #define BRB_REG_INT_STS_WR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR                                                   (0x1<<28) // Read packet client parser releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR_SHIFT                                             28
+  #define BRB_REG_INT_STS_WR_3_RC_PKT3_STRT_PTR_FIFO_ERROR                                                   (0x1<<29) // Read packet client parser start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT3_STRT_PTR_FIFO_ERROR_SHIFT                                             29
+  #define BRB_REG_INT_STS_WR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR                                                 (0x1<<30) // Read packet client parser second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT                                           30
+  #define BRB_REG_INT_STS_WR_3_RC_PKT3_RSP_FIFO_ERROR                                                        (0x1<<31) // Read packet client parser response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_WR_3_RC_PKT3_RSP_FIFO_ERROR_SHIFT                                                  31
+#define BRB_REG_INT_STS_CLR_3                                                                                0x340114UL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT0_SIDE_FIFO_ERROR                                                      (0x1<<1) // Read packet client PRM side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT                                                1
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT0_REQ_FIFO_ERROR                                                       (0x1<<2) // Read packet client PRM request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT0_REQ_FIFO_ERROR_SHIFT                                                 2
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT0_BLK_FIFO_ERROR                                                       (0x1<<3) // Read packet client PRM block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT                                                 3
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR                                                  (0x1<<4) // Read packet client PRM releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR_SHIFT                                            4
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT0_STRT_PTR_FIFO_ERROR                                                  (0x1<<5) // Read packet client PRM start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT0_STRT_PTR_FIFO_ERROR_SHIFT                                            5
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR                                                (0x1<<6) // Read packet client PRM second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR_SHIFT                                          6
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT0_RSP_FIFO_ERROR                                                       (0x1<<7) // Read packet client PRM response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT                                                 7
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT0_DSCR_FIFO_ERROR                                                      (0x1<<8) // Read packet client PRM descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT                                                8
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT1_SIDE_FIFO_ERROR                                                      (0x1<<9) // Read packet client MSDM side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT1_SIDE_FIFO_ERROR_SHIFT                                                9
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT1_REQ_FIFO_ERROR                                                       (0x1<<10) // Read packet client MSDM request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT1_REQ_FIFO_ERROR_SHIFT                                                 10
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT1_BLK_FIFO_ERROR                                                       (0x1<<11) // Read packet client MSDM block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT1_BLK_FIFO_ERROR_SHIFT                                                 11
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR                                                  (0x1<<12) // Read packet client MSDM releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR_SHIFT                                            12
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT1_STRT_PTR_FIFO_ERROR                                                  (0x1<<13) // Read packet client MSDM start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT1_STRT_PTR_FIFO_ERROR_SHIFT                                            13
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR                                                (0x1<<14) // Read packet client MSDM second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR_SHIFT                                          14
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT1_RSP_FIFO_ERROR                                                       (0x1<<15) // Read packet client MSDM response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT1_RSP_FIFO_ERROR_SHIFT                                                 15
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT1_DSCR_FIFO_ERROR                                                      (0x1<<16) // Read packet client MSDM descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT1_DSCR_FIFO_ERROR_SHIFT                                                16
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT2_SIDE_FIFO_ERROR                                                      (0x1<<17) // Read packet client TSDM side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT2_SIDE_FIFO_ERROR_SHIFT                                                17
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT2_REQ_FIFO_ERROR                                                       (0x1<<18) // Read packet client TSDM request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT2_REQ_FIFO_ERROR_SHIFT                                                 18
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT2_BLK_FIFO_ERROR                                                       (0x1<<19) // Read packet client TSDM block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT2_BLK_FIFO_ERROR_SHIFT                                                 19
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR                                                  (0x1<<20) // Read packet client TSDM releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR_SHIFT                                            20
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT2_STRT_PTR_FIFO_ERROR                                                  (0x1<<21) // Read packet client TSDM start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT2_STRT_PTR_FIFO_ERROR_SHIFT                                            21
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR                                                (0x1<<22) // Read packet client TSDM second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR_SHIFT                                          22
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT2_RSP_FIFO_ERROR                                                       (0x1<<23) // Read packet client TSDM response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT2_RSP_FIFO_ERROR_SHIFT                                                 23
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT2_DSCR_FIFO_ERROR                                                      (0x1<<24) // Read packet client TSDM descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT2_DSCR_FIFO_ERROR_SHIFT                                                24
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT3_SIDE_FIFO_ERROR                                                      (0x1<<25) // Read packet client parser side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT3_SIDE_FIFO_ERROR_SHIFT                                                25
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT3_REQ_FIFO_ERROR                                                       (0x1<<26) // Read packet client parser request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT3_REQ_FIFO_ERROR_SHIFT                                                 26
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT3_BLK_FIFO_ERROR                                                       (0x1<<27) // Read packet client parser block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT3_BLK_FIFO_ERROR_SHIFT                                                 27
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR                                                  (0x1<<28) // Read packet client parser releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR_SHIFT                                            28
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT3_STRT_PTR_FIFO_ERROR                                                  (0x1<<29) // Read packet client parser start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT3_STRT_PTR_FIFO_ERROR_SHIFT                                            29
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR                                                (0x1<<30) // Read packet client parser second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT                                          30
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT3_RSP_FIFO_ERROR                                                       (0x1<<31) // Read packet client parser response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_CLR_3_RC_PKT3_RSP_FIFO_ERROR_SHIFT                                                 31
+#define BRB_REG_INT_STS_4                                                                                    0x340120UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define BRB_REG_INT_STS_4_RC_PKT3_DSCR_FIFO_ERROR                                                          (0x1<<0) // Read packet client parser descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_4_RC_PKT3_DSCR_FIFO_ERROR_SHIFT                                                    0
+  #define BRB_REG_INT_STS_4_RC_SOP_STRT_FIFO_ERROR                                                           (0x1<<1) // Read SOP client strt pointer FIFO error RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_4_RC_SOP_STRT_FIFO_ERROR_SHIFT                                                     1
+  #define BRB_REG_INT_STS_4_RC_SOP_REQ_FIFO_ERROR                                                            (0x1<<2) // Read SOP client request FIFO error RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_4_RC_SOP_REQ_FIFO_ERROR_SHIFT                                                      2
+  #define BRB_REG_INT_STS_4_RC_SOP_DSCR_FIFO_ERROR                                                           (0x1<<3) // Read SOP client descriptor FIFO error RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_4_RC_SOP_DSCR_FIFO_ERROR_SHIFT                                                     3
+  #define BRB_REG_INT_STS_4_RC_SOP_QUEUE_FIFO_ERROR                                                          (0x1<<4) // Read SOP client queue FIFO error.
+  #define BRB_REG_INT_STS_4_RC_SOP_QUEUE_FIFO_ERROR_SHIFT                                                    4
+  #define BRB_REG_INT_STS_4_RC0_EOP_ERROR                                                                    (0x1<<5) // Read EOP client 0 request FIFO error RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_4_RC0_EOP_ERROR_SHIFT                                                              5
+  #define BRB_REG_INT_STS_4_RC1_EOP_ERROR                                                                    (0x1<<6) // Read EOP client 1 request FIFO error RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_4_RC1_EOP_ERROR_SHIFT                                                              6
+  #define BRB_REG_INT_STS_4_LL_ARB_RLS_FIFO_ERROR                                                            (0x1<<7) // Link list arbiter release FIFO error.
+  #define BRB_REG_INT_STS_4_LL_ARB_RLS_FIFO_ERROR_SHIFT                                                      7
+  #define BRB_REG_INT_STS_4_LL_ARB_PREFETCH_FIFO_ERROR                                                       (0x1<<8) // Link list arbiter prefetch FIFO error.
+  #define BRB_REG_INT_STS_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT                                                 8
+  #define BRB_REG_INT_STS_4_RC_PKT0_RLS_FIFO_ERROR                                                           (0x1<<9) // Read packet client PRM release fifo error
+  #define BRB_REG_INT_STS_4_RC_PKT0_RLS_FIFO_ERROR_SHIFT                                                     9
+  #define BRB_REG_INT_STS_4_RC_PKT1_RLS_FIFO_ERROR                                                           (0x1<<10) // Read packet client MSDM release fifo error
+  #define BRB_REG_INT_STS_4_RC_PKT1_RLS_FIFO_ERROR_SHIFT                                                     10
+  #define BRB_REG_INT_STS_4_RC_PKT2_RLS_FIFO_ERROR                                                           (0x1<<11) // Read packet client TSDM release fifo error
+  #define BRB_REG_INT_STS_4_RC_PKT2_RLS_FIFO_ERROR_SHIFT                                                     11
+  #define BRB_REG_INT_STS_4_RC_PKT3_RLS_FIFO_ERROR                                                           (0x1<<12) // Read packet client parser release fifo error
+  #define BRB_REG_INT_STS_4_RC_PKT3_RLS_FIFO_ERROR_SHIFT                                                     12
+  #define BRB_REG_INT_STS_4_RC_PKT4_RLS_FIFO_ERROR                                                           (0x1<<13) // Read packet client parser release fifo error
+  #define BRB_REG_INT_STS_4_RC_PKT4_RLS_FIFO_ERROR_SHIFT                                                     13
+  #define BRB_REG_INT_STS_4_RC_PKT4_RLS_ERROR                                                                (0x1<<19) // Read packet client parser release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_4_RC_PKT4_RLS_ERROR_SHIFT                                                          19
+  #define BRB_REG_INT_STS_4_RC_PKT4_1ST_ERROR                                                                (0x1<<20) // Read packet client parser first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_4_RC_PKT4_1ST_ERROR_SHIFT                                                          20
+  #define BRB_REG_INT_STS_4_RC_PKT4_LEN_ERROR                                                                (0x1<<21) // Read packet client parser length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_4_RC_PKT4_LEN_ERROR_SHIFT                                                          21
+  #define BRB_REG_INT_STS_4_RC_PKT4_MIDDLE_ERROR                                                             (0x1<<22) // Read packet client parser error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_4_RC_PKT4_MIDDLE_ERROR_SHIFT                                                       22
+  #define BRB_REG_INT_STS_4_RC_PKT4_PROTOCOL_ERROR                                                           (0x1<<23) // Read packet client parser error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_4_RC_PKT4_PROTOCOL_ERROR_SHIFT                                                     23
+  #define BRB_REG_INT_STS_4_RC_PKT4_SIDE_FIFO_ERROR                                                          (0x1<<24) // Read packet client parser side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_4_RC_PKT4_SIDE_FIFO_ERROR_SHIFT                                                    24
+  #define BRB_REG_INT_STS_4_RC_PKT4_REQ_FIFO_ERROR                                                           (0x1<<25) // Read packet client parser request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_4_RC_PKT4_REQ_FIFO_ERROR_SHIFT                                                     25
+  #define BRB_REG_INT_STS_4_RC_PKT4_BLK_FIFO_ERROR                                                           (0x1<<26) // Read packet client parser block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_4_RC_PKT4_BLK_FIFO_ERROR_SHIFT                                                     26
+  #define BRB_REG_INT_STS_4_RC_PKT4_RLS_LEFT_FIFO_ERROR                                                      (0x1<<27) // Read packet client parser releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_4_RC_PKT4_RLS_LEFT_FIFO_ERROR_SHIFT                                                27
+  #define BRB_REG_INT_STS_4_RC_PKT4_STRT_PTR_FIFO_ERROR                                                      (0x1<<28) // Read packet client parser start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_4_RC_PKT4_STRT_PTR_FIFO_ERROR_SHIFT                                                28
+  #define BRB_REG_INT_STS_4_RC_PKT4_SECOND_PTR_FIFO_ERROR                                                    (0x1<<29) // Read packet client parser second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_4_RC_PKT4_SECOND_PTR_FIFO_ERROR_SHIFT                                              29
+  #define BRB_REG_INT_STS_4_RC_PKT4_RSP_FIFO_ERROR                                                           (0x1<<30) // Read packet client parser response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT                                                     30
+  #define BRB_REG_INT_STS_4_RC_PKT4_DSCR_FIFO_ERROR                                                          (0x1<<31) // Read packet client parser descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_4_RC_PKT4_DSCR_FIFO_ERROR_SHIFT                                                    31
+#define BRB_REG_INT_MASK_4                                                                                   0x340124UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define BRB_REG_INT_MASK_4_RC_PKT3_DSCR_FIFO_ERROR                                                         (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT3_DSCR_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_4_RC_PKT3_DSCR_FIFO_ERROR_SHIFT                                                   0
+  #define BRB_REG_INT_MASK_4_RC_SOP_STRT_FIFO_ERROR                                                          (0x1<<1) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_SOP_STRT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_4_RC_SOP_STRT_FIFO_ERROR_SHIFT                                                    1
+  #define BRB_REG_INT_MASK_4_RC_SOP_REQ_FIFO_ERROR                                                           (0x1<<2) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_SOP_REQ_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_4_RC_SOP_REQ_FIFO_ERROR_SHIFT                                                     2
+  #define BRB_REG_INT_MASK_4_RC_SOP_DSCR_FIFO_ERROR                                                          (0x1<<3) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_SOP_DSCR_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_4_RC_SOP_DSCR_FIFO_ERROR_SHIFT                                                    3
+  #define BRB_REG_INT_MASK_4_RC_SOP_QUEUE_FIFO_ERROR                                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_SOP_QUEUE_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_4_RC_SOP_QUEUE_FIFO_ERROR_SHIFT                                                   4
+  #define BRB_REG_INT_MASK_4_RC0_EOP_ERROR                                                                   (0x1<<5) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC0_EOP_ERROR .
+  #define BRB_REG_INT_MASK_4_RC0_EOP_ERROR_SHIFT                                                             5
+  #define BRB_REG_INT_MASK_4_RC1_EOP_ERROR                                                                   (0x1<<6) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC1_EOP_ERROR .
+  #define BRB_REG_INT_MASK_4_RC1_EOP_ERROR_SHIFT                                                             6
+  #define BRB_REG_INT_MASK_4_LL_ARB_RLS_FIFO_ERROR                                                           (0x1<<7) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.LL_ARB_RLS_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_4_LL_ARB_RLS_FIFO_ERROR_SHIFT                                                     7
+  #define BRB_REG_INT_MASK_4_LL_ARB_PREFETCH_FIFO_ERROR                                                      (0x1<<8) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.LL_ARB_PREFETCH_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT                                                8
+  #define BRB_REG_INT_MASK_4_RC_PKT0_RLS_FIFO_ERROR                                                          (0x1<<9) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT0_RLS_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_4_RC_PKT0_RLS_FIFO_ERROR_SHIFT                                                    9
+  #define BRB_REG_INT_MASK_4_RC_PKT1_RLS_FIFO_ERROR                                                          (0x1<<10) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT1_RLS_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_4_RC_PKT1_RLS_FIFO_ERROR_SHIFT                                                    10
+  #define BRB_REG_INT_MASK_4_RC_PKT2_RLS_FIFO_ERROR                                                          (0x1<<11) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT2_RLS_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_4_RC_PKT2_RLS_FIFO_ERROR_SHIFT                                                    11
+  #define BRB_REG_INT_MASK_4_RC_PKT3_RLS_FIFO_ERROR                                                          (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT3_RLS_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_4_RC_PKT3_RLS_FIFO_ERROR_SHIFT                                                    12
+  #define BRB_REG_INT_MASK_4_RC_PKT4_RLS_FIFO_ERROR                                                          (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_RLS_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_4_RC_PKT4_RLS_FIFO_ERROR_SHIFT                                                    13
+  #define BRB_REG_INT_MASK_4_RC_PKT4_RLS_ERROR                                                               (0x1<<19) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_RLS_ERROR .
+  #define BRB_REG_INT_MASK_4_RC_PKT4_RLS_ERROR_SHIFT                                                         19
+  #define BRB_REG_INT_MASK_4_RC_PKT4_1ST_ERROR                                                               (0x1<<20) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_1ST_ERROR .
+  #define BRB_REG_INT_MASK_4_RC_PKT4_1ST_ERROR_SHIFT                                                         20
+  #define BRB_REG_INT_MASK_4_RC_PKT4_LEN_ERROR                                                               (0x1<<21) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_LEN_ERROR .
+  #define BRB_REG_INT_MASK_4_RC_PKT4_LEN_ERROR_SHIFT                                                         21
+  #define BRB_REG_INT_MASK_4_RC_PKT4_MIDDLE_ERROR                                                            (0x1<<22) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_MIDDLE_ERROR .
+  #define BRB_REG_INT_MASK_4_RC_PKT4_MIDDLE_ERROR_SHIFT                                                      22
+  #define BRB_REG_INT_MASK_4_RC_PKT4_PROTOCOL_ERROR                                                          (0x1<<23) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_PROTOCOL_ERROR .
+  #define BRB_REG_INT_MASK_4_RC_PKT4_PROTOCOL_ERROR_SHIFT                                                    23
+  #define BRB_REG_INT_MASK_4_RC_PKT4_SIDE_FIFO_ERROR                                                         (0x1<<24) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_SIDE_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_4_RC_PKT4_SIDE_FIFO_ERROR_SHIFT                                                   24
+  #define BRB_REG_INT_MASK_4_RC_PKT4_REQ_FIFO_ERROR                                                          (0x1<<25) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_REQ_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_4_RC_PKT4_REQ_FIFO_ERROR_SHIFT                                                    25
+  #define BRB_REG_INT_MASK_4_RC_PKT4_BLK_FIFO_ERROR                                                          (0x1<<26) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_BLK_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_4_RC_PKT4_BLK_FIFO_ERROR_SHIFT                                                    26
+  #define BRB_REG_INT_MASK_4_RC_PKT4_RLS_LEFT_FIFO_ERROR                                                     (0x1<<27) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_RLS_LEFT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_4_RC_PKT4_RLS_LEFT_FIFO_ERROR_SHIFT                                               27
+  #define BRB_REG_INT_MASK_4_RC_PKT4_STRT_PTR_FIFO_ERROR                                                     (0x1<<28) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_STRT_PTR_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_4_RC_PKT4_STRT_PTR_FIFO_ERROR_SHIFT                                               28
+  #define BRB_REG_INT_MASK_4_RC_PKT4_SECOND_PTR_FIFO_ERROR                                                   (0x1<<29) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_SECOND_PTR_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_4_RC_PKT4_SECOND_PTR_FIFO_ERROR_SHIFT                                             29
+  #define BRB_REG_INT_MASK_4_RC_PKT4_RSP_FIFO_ERROR                                                          (0x1<<30) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_RSP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT                                                    30
+  #define BRB_REG_INT_MASK_4_RC_PKT4_DSCR_FIFO_ERROR                                                         (0x1<<31) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_DSCR_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_4_RC_PKT4_DSCR_FIFO_ERROR_SHIFT                                                   31
+#define BRB_REG_INT_STS_WR_4                                                                                 0x340128UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define BRB_REG_INT_STS_WR_4_RC_PKT3_DSCR_FIFO_ERROR                                                       (0x1<<0) // Read packet client parser descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_WR_4_RC_PKT3_DSCR_FIFO_ERROR_SHIFT                                                 0
+  #define BRB_REG_INT_STS_WR_4_RC_SOP_STRT_FIFO_ERROR                                                        (0x1<<1) // Read SOP client strt pointer FIFO error RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_4_RC_SOP_STRT_FIFO_ERROR_SHIFT                                                  1
+  #define BRB_REG_INT_STS_WR_4_RC_SOP_REQ_FIFO_ERROR                                                         (0x1<<2) // Read SOP client request FIFO error RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_4_RC_SOP_REQ_FIFO_ERROR_SHIFT                                                   2
+  #define BRB_REG_INT_STS_WR_4_RC_SOP_DSCR_FIFO_ERROR                                                        (0x1<<3) // Read SOP client descriptor FIFO error RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_4_RC_SOP_DSCR_FIFO_ERROR_SHIFT                                                  3
+  #define BRB_REG_INT_STS_WR_4_RC_SOP_QUEUE_FIFO_ERROR                                                       (0x1<<4) // Read SOP client queue FIFO error.
+  #define BRB_REG_INT_STS_WR_4_RC_SOP_QUEUE_FIFO_ERROR_SHIFT                                                 4
+  #define BRB_REG_INT_STS_WR_4_RC0_EOP_ERROR                                                                 (0x1<<5) // Read EOP client 0 request FIFO error RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_4_RC0_EOP_ERROR_SHIFT                                                           5
+  #define BRB_REG_INT_STS_WR_4_RC1_EOP_ERROR                                                                 (0x1<<6) // Read EOP client 1 request FIFO error RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_4_RC1_EOP_ERROR_SHIFT                                                           6
+  #define BRB_REG_INT_STS_WR_4_LL_ARB_RLS_FIFO_ERROR                                                         (0x1<<7) // Link list arbiter release FIFO error.
+  #define BRB_REG_INT_STS_WR_4_LL_ARB_RLS_FIFO_ERROR_SHIFT                                                   7
+  #define BRB_REG_INT_STS_WR_4_LL_ARB_PREFETCH_FIFO_ERROR                                                    (0x1<<8) // Link list arbiter prefetch FIFO error.
+  #define BRB_REG_INT_STS_WR_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT                                              8
+  #define BRB_REG_INT_STS_WR_4_RC_PKT0_RLS_FIFO_ERROR                                                        (0x1<<9) // Read packet client PRM release fifo error
+  #define BRB_REG_INT_STS_WR_4_RC_PKT0_RLS_FIFO_ERROR_SHIFT                                                  9
+  #define BRB_REG_INT_STS_WR_4_RC_PKT1_RLS_FIFO_ERROR                                                        (0x1<<10) // Read packet client MSDM release fifo error
+  #define BRB_REG_INT_STS_WR_4_RC_PKT1_RLS_FIFO_ERROR_SHIFT                                                  10
+  #define BRB_REG_INT_STS_WR_4_RC_PKT2_RLS_FIFO_ERROR                                                        (0x1<<11) // Read packet client TSDM release fifo error
+  #define BRB_REG_INT_STS_WR_4_RC_PKT2_RLS_FIFO_ERROR_SHIFT                                                  11
+  #define BRB_REG_INT_STS_WR_4_RC_PKT3_RLS_FIFO_ERROR                                                        (0x1<<12) // Read packet client parser release fifo error
+  #define BRB_REG_INT_STS_WR_4_RC_PKT3_RLS_FIFO_ERROR_SHIFT                                                  12
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_RLS_FIFO_ERROR                                                        (0x1<<13) // Read packet client parser release fifo error
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_RLS_FIFO_ERROR_SHIFT                                                  13
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_RLS_ERROR                                                             (0x1<<19) // Read packet client parser release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_RLS_ERROR_SHIFT                                                       19
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_1ST_ERROR                                                             (0x1<<20) // Read packet client parser first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_1ST_ERROR_SHIFT                                                       20
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_LEN_ERROR                                                             (0x1<<21) // Read packet client parser length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_LEN_ERROR_SHIFT                                                       21
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_MIDDLE_ERROR                                                          (0x1<<22) // Read packet client parser error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_MIDDLE_ERROR_SHIFT                                                    22
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_PROTOCOL_ERROR                                                        (0x1<<23) // Read packet client parser error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_PROTOCOL_ERROR_SHIFT                                                  23
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_SIDE_FIFO_ERROR                                                       (0x1<<24) // Read packet client parser side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_SIDE_FIFO_ERROR_SHIFT                                                 24
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_REQ_FIFO_ERROR                                                        (0x1<<25) // Read packet client parser request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_REQ_FIFO_ERROR_SHIFT                                                  25
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_BLK_FIFO_ERROR                                                        (0x1<<26) // Read packet client parser block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_BLK_FIFO_ERROR_SHIFT                                                  26
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR                                                   (0x1<<27) // Read packet client parser releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR_SHIFT                                             27
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_STRT_PTR_FIFO_ERROR                                                   (0x1<<28) // Read packet client parser start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_STRT_PTR_FIFO_ERROR_SHIFT                                             28
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR                                                 (0x1<<29) // Read packet client parser second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR_SHIFT                                           29
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_RSP_FIFO_ERROR                                                        (0x1<<30) // Read packet client parser response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT                                                  30
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_DSCR_FIFO_ERROR                                                       (0x1<<31) // Read packet client parser descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_WR_4_RC_PKT4_DSCR_FIFO_ERROR_SHIFT                                                 31
+#define BRB_REG_INT_STS_CLR_4                                                                                0x34012cUL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT3_DSCR_FIFO_ERROR                                                      (0x1<<0) // Read packet client parser descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT3_DSCR_FIFO_ERROR_SHIFT                                                0
+  #define BRB_REG_INT_STS_CLR_4_RC_SOP_STRT_FIFO_ERROR                                                       (0x1<<1) // Read SOP client strt pointer FIFO error RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_4_RC_SOP_STRT_FIFO_ERROR_SHIFT                                                 1
+  #define BRB_REG_INT_STS_CLR_4_RC_SOP_REQ_FIFO_ERROR                                                        (0x1<<2) // Read SOP client request FIFO error RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_4_RC_SOP_REQ_FIFO_ERROR_SHIFT                                                  2
+  #define BRB_REG_INT_STS_CLR_4_RC_SOP_DSCR_FIFO_ERROR                                                       (0x1<<3) // Read SOP client descriptor FIFO error RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_4_RC_SOP_DSCR_FIFO_ERROR_SHIFT                                                 3
+  #define BRB_REG_INT_STS_CLR_4_RC_SOP_QUEUE_FIFO_ERROR                                                      (0x1<<4) // Read SOP client queue FIFO error.
+  #define BRB_REG_INT_STS_CLR_4_RC_SOP_QUEUE_FIFO_ERROR_SHIFT                                                4
+  #define BRB_REG_INT_STS_CLR_4_RC0_EOP_ERROR                                                                (0x1<<5) // Read EOP client 0 request FIFO error RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_4_RC0_EOP_ERROR_SHIFT                                                          5
+  #define BRB_REG_INT_STS_CLR_4_RC1_EOP_ERROR                                                                (0x1<<6) // Read EOP client 1 request FIFO error RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_4_RC1_EOP_ERROR_SHIFT                                                          6
+  #define BRB_REG_INT_STS_CLR_4_LL_ARB_RLS_FIFO_ERROR                                                        (0x1<<7) // Link list arbiter release FIFO error.
+  #define BRB_REG_INT_STS_CLR_4_LL_ARB_RLS_FIFO_ERROR_SHIFT                                                  7
+  #define BRB_REG_INT_STS_CLR_4_LL_ARB_PREFETCH_FIFO_ERROR                                                   (0x1<<8) // Link list arbiter prefetch FIFO error.
+  #define BRB_REG_INT_STS_CLR_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT                                             8
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT0_RLS_FIFO_ERROR                                                       (0x1<<9) // Read packet client PRM release fifo error
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT0_RLS_FIFO_ERROR_SHIFT                                                 9
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT1_RLS_FIFO_ERROR                                                       (0x1<<10) // Read packet client MSDM release fifo error
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT1_RLS_FIFO_ERROR_SHIFT                                                 10
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT2_RLS_FIFO_ERROR                                                       (0x1<<11) // Read packet client TSDM release fifo error
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT2_RLS_FIFO_ERROR_SHIFT                                                 11
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT3_RLS_FIFO_ERROR                                                       (0x1<<12) // Read packet client parser release fifo error
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT3_RLS_FIFO_ERROR_SHIFT                                                 12
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_RLS_FIFO_ERROR                                                       (0x1<<13) // Read packet client parser release fifo error
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_RLS_FIFO_ERROR_SHIFT                                                 13
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_RLS_ERROR                                                            (0x1<<19) // Read packet client parser release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_RLS_ERROR_SHIFT                                                      19
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_1ST_ERROR                                                            (0x1<<20) // Read packet client parser first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_1ST_ERROR_SHIFT                                                      20
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_LEN_ERROR                                                            (0x1<<21) // Read packet client parser length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_LEN_ERROR_SHIFT                                                      21
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_MIDDLE_ERROR                                                         (0x1<<22) // Read packet client parser error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_MIDDLE_ERROR_SHIFT                                                   22
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_PROTOCOL_ERROR                                                       (0x1<<23) // Read packet client parser error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_PROTOCOL_ERROR_SHIFT                                                 23
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_SIDE_FIFO_ERROR                                                      (0x1<<24) // Read packet client parser side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_SIDE_FIFO_ERROR_SHIFT                                                24
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_REQ_FIFO_ERROR                                                       (0x1<<25) // Read packet client parser request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_REQ_FIFO_ERROR_SHIFT                                                 25
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_BLK_FIFO_ERROR                                                       (0x1<<26) // Read packet client parser block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_BLK_FIFO_ERROR_SHIFT                                                 26
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR                                                  (0x1<<27) // Read packet client parser releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR_SHIFT                                            27
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_STRT_PTR_FIFO_ERROR                                                  (0x1<<28) // Read packet client parser start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_STRT_PTR_FIFO_ERROR_SHIFT                                            28
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR                                                (0x1<<29) // Read packet client parser second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR_SHIFT                                          29
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_RSP_FIFO_ERROR                                                       (0x1<<30) // Read packet client parser response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT                                                 30
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_DSCR_FIFO_ERROR                                                      (0x1<<31) // Read packet client parser descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BRB_REG_INT_STS_CLR_4_RC_PKT4_DSCR_FIFO_ERROR_SHIFT                                                31
+#define BRB_REG_INT_STS_5                                                                                    0x340138UL //Access:R    DataWidth:0x1    // Multi Field Register.
+  #define BRB_REG_INT_STS_5_RC_PKT5_RLS_ERROR                                                                (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
+  #define BRB_REG_INT_STS_5_RC_PKT5_RLS_ERROR_SHIFT                                                          0
+#define BRB_REG_INT_MASK_5                                                                                   0x34013cUL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define BRB_REG_INT_MASK_5_RC_PKT5_RLS_ERROR                                                               (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_5.RC_PKT5_RLS_ERROR .
+  #define BRB_REG_INT_MASK_5_RC_PKT5_RLS_ERROR_SHIFT                                                         0
+#define BRB_REG_INT_STS_WR_5                                                                                 0x340140UL //Access:WR   DataWidth:0x1    // Multi Field Register.
+  #define BRB_REG_INT_STS_WR_5_RC_PKT5_RLS_ERROR                                                             (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
+  #define BRB_REG_INT_STS_WR_5_RC_PKT5_RLS_ERROR_SHIFT                                                       0
+#define BRB_REG_INT_STS_CLR_5                                                                                0x340144UL //Access:RC   DataWidth:0x1    // Multi Field Register.
+  #define BRB_REG_INT_STS_CLR_5_RC_PKT5_RLS_ERROR                                                            (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
+  #define BRB_REG_INT_STS_CLR_5_RC_PKT5_RLS_ERROR_SHIFT                                                      0
+#define BRB_REG_INT_STS_6                                                                                    0x340150UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define BRB_REG_INT_STS_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR                                            (0x1<<0) // Packet available SYNC FIFO error
+  #define BRB_REG_INT_STS_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR_SHIFT                                      0
+  #define BRB_REG_INT_STS_6_WC4_PROTOCOL_ERROR                                                               (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 4.
+  #define BRB_REG_INT_STS_6_WC4_PROTOCOL_ERROR_SHIFT                                                         23
+  #define BRB_REG_INT_STS_6_WC5_PROTOCOL_ERROR                                                               (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 5
+  #define BRB_REG_INT_STS_6_WC5_PROTOCOL_ERROR_SHIFT                                                         24
+  #define BRB_REG_INT_STS_6_WC6_PROTOCOL_ERROR                                                               (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 6
+  #define BRB_REG_INT_STS_6_WC6_PROTOCOL_ERROR_SHIFT                                                         25
+  #define BRB_REG_INT_STS_6_WC7_PROTOCOL_ERROR                                                               (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 7
+  #define BRB_REG_INT_STS_6_WC7_PROTOCOL_ERROR_SHIFT                                                         26
+  #define BRB_REG_INT_STS_6_WC4_INP_FIFO_ERROR                                                               (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 4 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_6_WC4_INP_FIFO_ERROR_SHIFT                                                         29
+  #define BRB_REG_INT_STS_6_WC4_SOP_FIFO_ERROR                                                               (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 4
+  #define BRB_REG_INT_STS_6_WC4_SOP_FIFO_ERROR_SHIFT                                                         30
+  #define BRB_REG_INT_STS_6_WC4_QUEUE_FIFO_ERROR                                                             (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 4
+  #define BRB_REG_INT_STS_6_WC4_QUEUE_FIFO_ERROR_SHIFT                                                       31
+#define BRB_REG_INT_MASK_6                                                                                   0x340154UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define BRB_REG_INT_MASK_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR                                           (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_6.PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR .
+  #define BRB_REG_INT_MASK_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR_SHIFT                                     0
+  #define BRB_REG_INT_MASK_6_WC4_PROTOCOL_ERROR                                                              (0x1<<23) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_6.WC4_PROTOCOL_ERROR .
+  #define BRB_REG_INT_MASK_6_WC4_PROTOCOL_ERROR_SHIFT                                                        23
+  #define BRB_REG_INT_MASK_6_WC5_PROTOCOL_ERROR                                                              (0x1<<24) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_6.WC5_PROTOCOL_ERROR .
+  #define BRB_REG_INT_MASK_6_WC5_PROTOCOL_ERROR_SHIFT                                                        24
+  #define BRB_REG_INT_MASK_6_WC6_PROTOCOL_ERROR                                                              (0x1<<25) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_6.WC6_PROTOCOL_ERROR .
+  #define BRB_REG_INT_MASK_6_WC6_PROTOCOL_ERROR_SHIFT                                                        25
+  #define BRB_REG_INT_MASK_6_WC7_PROTOCOL_ERROR                                                              (0x1<<26) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_6.WC7_PROTOCOL_ERROR .
+  #define BRB_REG_INT_MASK_6_WC7_PROTOCOL_ERROR_SHIFT                                                        26
+  #define BRB_REG_INT_MASK_6_WC4_INP_FIFO_ERROR                                                              (0x1<<29) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_6.WC4_INP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_6_WC4_INP_FIFO_ERROR_SHIFT                                                        29
+  #define BRB_REG_INT_MASK_6_WC4_SOP_FIFO_ERROR                                                              (0x1<<30) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_6.WC4_SOP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_6_WC4_SOP_FIFO_ERROR_SHIFT                                                        30
+  #define BRB_REG_INT_MASK_6_WC4_QUEUE_FIFO_ERROR                                                            (0x1<<31) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_6.WC4_QUEUE_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_6_WC4_QUEUE_FIFO_ERROR_SHIFT                                                      31
+#define BRB_REG_INT_STS_WR_6                                                                                 0x340158UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define BRB_REG_INT_STS_WR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR                                         (0x1<<0) // Packet available SYNC FIFO error
+  #define BRB_REG_INT_STS_WR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR_SHIFT                                   0
+  #define BRB_REG_INT_STS_WR_6_WC4_PROTOCOL_ERROR                                                            (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 4.
+  #define BRB_REG_INT_STS_WR_6_WC4_PROTOCOL_ERROR_SHIFT                                                      23
+  #define BRB_REG_INT_STS_WR_6_WC5_PROTOCOL_ERROR                                                            (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 5
+  #define BRB_REG_INT_STS_WR_6_WC5_PROTOCOL_ERROR_SHIFT                                                      24
+  #define BRB_REG_INT_STS_WR_6_WC6_PROTOCOL_ERROR                                                            (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 6
+  #define BRB_REG_INT_STS_WR_6_WC6_PROTOCOL_ERROR_SHIFT                                                      25
+  #define BRB_REG_INT_STS_WR_6_WC7_PROTOCOL_ERROR                                                            (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 7
+  #define BRB_REG_INT_STS_WR_6_WC7_PROTOCOL_ERROR_SHIFT                                                      26
+  #define BRB_REG_INT_STS_WR_6_WC4_INP_FIFO_ERROR                                                            (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 4 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_WR_6_WC4_INP_FIFO_ERROR_SHIFT                                                      29
+  #define BRB_REG_INT_STS_WR_6_WC4_SOP_FIFO_ERROR                                                            (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 4
+  #define BRB_REG_INT_STS_WR_6_WC4_SOP_FIFO_ERROR_SHIFT                                                      30
+  #define BRB_REG_INT_STS_WR_6_WC4_QUEUE_FIFO_ERROR                                                          (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 4
+  #define BRB_REG_INT_STS_WR_6_WC4_QUEUE_FIFO_ERROR_SHIFT                                                    31
+#define BRB_REG_INT_STS_CLR_6                                                                                0x34015cUL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define BRB_REG_INT_STS_CLR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR                                        (0x1<<0) // Packet available SYNC FIFO error
+  #define BRB_REG_INT_STS_CLR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR_SHIFT                                  0
+  #define BRB_REG_INT_STS_CLR_6_WC4_PROTOCOL_ERROR                                                           (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 4.
+  #define BRB_REG_INT_STS_CLR_6_WC4_PROTOCOL_ERROR_SHIFT                                                     23
+  #define BRB_REG_INT_STS_CLR_6_WC5_PROTOCOL_ERROR                                                           (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 5
+  #define BRB_REG_INT_STS_CLR_6_WC5_PROTOCOL_ERROR_SHIFT                                                     24
+  #define BRB_REG_INT_STS_CLR_6_WC6_PROTOCOL_ERROR                                                           (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 6
+  #define BRB_REG_INT_STS_CLR_6_WC6_PROTOCOL_ERROR_SHIFT                                                     25
+  #define BRB_REG_INT_STS_CLR_6_WC7_PROTOCOL_ERROR                                                           (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 7
+  #define BRB_REG_INT_STS_CLR_6_WC7_PROTOCOL_ERROR_SHIFT                                                     26
+  #define BRB_REG_INT_STS_CLR_6_WC4_INP_FIFO_ERROR                                                           (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 4 RX_INT::/RX_INT/d in Comments.
+  #define BRB_REG_INT_STS_CLR_6_WC4_INP_FIFO_ERROR_SHIFT                                                     29
+  #define BRB_REG_INT_STS_CLR_6_WC4_SOP_FIFO_ERROR                                                           (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 4
+  #define BRB_REG_INT_STS_CLR_6_WC4_SOP_FIFO_ERROR_SHIFT                                                     30
+  #define BRB_REG_INT_STS_CLR_6_WC4_QUEUE_FIFO_ERROR                                                         (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 4
+  #define BRB_REG_INT_STS_CLR_6_WC4_QUEUE_FIFO_ERROR_SHIFT                                                   31
+#define BRB_REG_INT_STS_7                                                                                    0x340168UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define BRB_REG_INT_STS_7_WC4_FREE_POINT_FIFO_ERROR                                                        (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 4
+  #define BRB_REG_INT_STS_7_WC4_FREE_POINT_FIFO_ERROR_SHIFT                                                  0
+  #define BRB_REG_INT_STS_7_WC4_NEXT_POINT_FIFO_ERROR                                                        (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 4
+  #define BRB_REG_INT_STS_7_WC4_NEXT_POINT_FIFO_ERROR_SHIFT                                                  1
+  #define BRB_REG_INT_STS_7_WC4_STRT_FIFO_ERROR                                                              (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 4
+  #define BRB_REG_INT_STS_7_WC4_STRT_FIFO_ERROR_SHIFT                                                        2
+  #define BRB_REG_INT_STS_7_WC4_SECOND_DSCR_FIFO_ERROR                                                       (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 4
+  #define BRB_REG_INT_STS_7_WC4_SECOND_DSCR_FIFO_ERROR_SHIFT                                                 3
+  #define BRB_REG_INT_STS_7_WC4_PKT_AVAIL_FIFO_ERROR                                                         (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 4
+  #define BRB_REG_INT_STS_7_WC4_PKT_AVAIL_FIFO_ERROR_SHIFT                                                   4
+  #define BRB_REG_INT_STS_7_WC4_COS_CNT_FIFO_ERROR                                                           (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 4
+  #define BRB_REG_INT_STS_7_WC4_COS_CNT_FIFO_ERROR_SHIFT                                                     5
+  #define BRB_REG_INT_STS_7_WC4_NOTIFY_FIFO_ERROR                                                            (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 4
+  #define BRB_REG_INT_STS_7_WC4_NOTIFY_FIFO_ERROR_SHIFT                                                      6
+  #define BRB_REG_INT_STS_7_WC4_LL_REQ_FIFO_ERROR                                                            (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 4
+  #define BRB_REG_INT_STS_7_WC4_LL_REQ_FIFO_ERROR_SHIFT                                                      7
+  #define BRB_REG_INT_STS_7_WC4_LL_PA_CNT_ERROR                                                              (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 4
+  #define BRB_REG_INT_STS_7_WC4_LL_PA_CNT_ERROR_SHIFT                                                        8
+  #define BRB_REG_INT_STS_7_WC4_BB_PA_CNT_ERROR                                                              (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 4
+  #define BRB_REG_INT_STS_7_WC4_BB_PA_CNT_ERROR_SHIFT                                                        9
+  #define BRB_REG_INT_STS_7_WC5_INP_FIFO_ERROR                                                               (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 5
+  #define BRB_REG_INT_STS_7_WC5_INP_FIFO_ERROR_SHIFT                                                         10
+  #define BRB_REG_INT_STS_7_WC5_SOP_FIFO_ERROR                                                               (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 5
+  #define BRB_REG_INT_STS_7_WC5_SOP_FIFO_ERROR_SHIFT                                                         11
+  #define BRB_REG_INT_STS_7_WC5_QUEUE_FIFO_ERROR                                                             (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 5
+  #define BRB_REG_INT_STS_7_WC5_QUEUE_FIFO_ERROR_SHIFT                                                       12
+  #define BRB_REG_INT_STS_7_WC5_FREE_POINT_FIFO_ERROR                                                        (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 5
+  #define BRB_REG_INT_STS_7_WC5_FREE_POINT_FIFO_ERROR_SHIFT                                                  13
+  #define BRB_REG_INT_STS_7_WC5_NEXT_POINT_FIFO_ERROR                                                        (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 5
+  #define BRB_REG_INT_STS_7_WC5_NEXT_POINT_FIFO_ERROR_SHIFT                                                  14
+  #define BRB_REG_INT_STS_7_WC5_STRT_FIFO_ERROR                                                              (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 5
+  #define BRB_REG_INT_STS_7_WC5_STRT_FIFO_ERROR_SHIFT                                                        15
+  #define BRB_REG_INT_STS_7_WC5_SECOND_DSCR_FIFO_ERROR                                                       (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 5
+  #define BRB_REG_INT_STS_7_WC5_SECOND_DSCR_FIFO_ERROR_SHIFT                                                 16
+  #define BRB_REG_INT_STS_7_WC5_PKT_AVAIL_FIFO_ERROR                                                         (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 5
+  #define BRB_REG_INT_STS_7_WC5_PKT_AVAIL_FIFO_ERROR_SHIFT                                                   17
+  #define BRB_REG_INT_STS_7_WC5_COS_CNT_FIFO_ERROR                                                           (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 5
+  #define BRB_REG_INT_STS_7_WC5_COS_CNT_FIFO_ERROR_SHIFT                                                     18
+  #define BRB_REG_INT_STS_7_WC5_NOTIFY_FIFO_ERROR                                                            (0x1<<19) // Notify FIFO error in write client 5
+  #define BRB_REG_INT_STS_7_WC5_NOTIFY_FIFO_ERROR_SHIFT                                                      19
+  #define BRB_REG_INT_STS_7_WC5_LL_REQ_FIFO_ERROR                                                            (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 5
+  #define BRB_REG_INT_STS_7_WC5_LL_REQ_FIFO_ERROR_SHIFT                                                      20
+  #define BRB_REG_INT_STS_7_WC5_LL_PA_CNT_ERROR                                                              (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 5
+  #define BRB_REG_INT_STS_7_WC5_LL_PA_CNT_ERROR_SHIFT                                                        21
+  #define BRB_REG_INT_STS_7_WC5_BB_PA_CNT_ERROR                                                              (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 5
+  #define BRB_REG_INT_STS_7_WC5_BB_PA_CNT_ERROR_SHIFT                                                        22
+  #define BRB_REG_INT_STS_7_WC6_INP_FIFO_ERROR                                                               (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 6
+  #define BRB_REG_INT_STS_7_WC6_INP_FIFO_ERROR_SHIFT                                                         23
+  #define BRB_REG_INT_STS_7_WC6_SOP_FIFO_ERROR                                                               (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 6
+  #define BRB_REG_INT_STS_7_WC6_SOP_FIFO_ERROR_SHIFT                                                         24
+  #define BRB_REG_INT_STS_7_WC6_QUEUE_FIFO_ERROR                                                             (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 6
+  #define BRB_REG_INT_STS_7_WC6_QUEUE_FIFO_ERROR_SHIFT                                                       25
+  #define BRB_REG_INT_STS_7_WC6_FREE_POINT_FIFO_ERROR                                                        (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 6
+  #define BRB_REG_INT_STS_7_WC6_FREE_POINT_FIFO_ERROR_SHIFT                                                  26
+  #define BRB_REG_INT_STS_7_WC6_NEXT_POINT_FIFO_ERROR                                                        (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 6
+  #define BRB_REG_INT_STS_7_WC6_NEXT_POINT_FIFO_ERROR_SHIFT                                                  27
+  #define BRB_REG_INT_STS_7_WC6_STRT_FIFO_ERROR                                                              (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 6
+  #define BRB_REG_INT_STS_7_WC6_STRT_FIFO_ERROR_SHIFT                                                        28
+  #define BRB_REG_INT_STS_7_WC6_SECOND_DSCR_FIFO_ERROR                                                       (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 6
+  #define BRB_REG_INT_STS_7_WC6_SECOND_DSCR_FIFO_ERROR_SHIFT                                                 29
+  #define BRB_REG_INT_STS_7_WC6_PKT_AVAIL_FIFO_ERROR                                                         (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 6
+  #define BRB_REG_INT_STS_7_WC6_PKT_AVAIL_FIFO_ERROR_SHIFT                                                   30
+  #define BRB_REG_INT_STS_7_WC6_COS_CNT_FIFO_ERROR                                                           (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 6
+  #define BRB_REG_INT_STS_7_WC6_COS_CNT_FIFO_ERROR_SHIFT                                                     31
+#define BRB_REG_INT_MASK_7                                                                                   0x34016cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define BRB_REG_INT_MASK_7_WC4_FREE_POINT_FIFO_ERROR                                                       (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_FREE_POINT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC4_FREE_POINT_FIFO_ERROR_SHIFT                                                 0
+  #define BRB_REG_INT_MASK_7_WC4_NEXT_POINT_FIFO_ERROR                                                       (0x1<<1) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_NEXT_POINT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC4_NEXT_POINT_FIFO_ERROR_SHIFT                                                 1
+  #define BRB_REG_INT_MASK_7_WC4_STRT_FIFO_ERROR                                                             (0x1<<2) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_STRT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC4_STRT_FIFO_ERROR_SHIFT                                                       2
+  #define BRB_REG_INT_MASK_7_WC4_SECOND_DSCR_FIFO_ERROR                                                      (0x1<<3) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_SECOND_DSCR_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC4_SECOND_DSCR_FIFO_ERROR_SHIFT                                                3
+  #define BRB_REG_INT_MASK_7_WC4_PKT_AVAIL_FIFO_ERROR                                                        (0x1<<4) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_PKT_AVAIL_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC4_PKT_AVAIL_FIFO_ERROR_SHIFT                                                  4
+  #define BRB_REG_INT_MASK_7_WC4_COS_CNT_FIFO_ERROR                                                          (0x1<<5) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_COS_CNT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC4_COS_CNT_FIFO_ERROR_SHIFT                                                    5
+  #define BRB_REG_INT_MASK_7_WC4_NOTIFY_FIFO_ERROR                                                           (0x1<<6) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_NOTIFY_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC4_NOTIFY_FIFO_ERROR_SHIFT                                                     6
+  #define BRB_REG_INT_MASK_7_WC4_LL_REQ_FIFO_ERROR                                                           (0x1<<7) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_LL_REQ_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC4_LL_REQ_FIFO_ERROR_SHIFT                                                     7
+  #define BRB_REG_INT_MASK_7_WC4_LL_PA_CNT_ERROR                                                             (0x1<<8) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_LL_PA_CNT_ERROR .
+  #define BRB_REG_INT_MASK_7_WC4_LL_PA_CNT_ERROR_SHIFT                                                       8
+  #define BRB_REG_INT_MASK_7_WC4_BB_PA_CNT_ERROR                                                             (0x1<<9) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_BB_PA_CNT_ERROR .
+  #define BRB_REG_INT_MASK_7_WC4_BB_PA_CNT_ERROR_SHIFT                                                       9
+  #define BRB_REG_INT_MASK_7_WC5_INP_FIFO_ERROR                                                              (0x1<<10) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_INP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC5_INP_FIFO_ERROR_SHIFT                                                        10
+  #define BRB_REG_INT_MASK_7_WC5_SOP_FIFO_ERROR                                                              (0x1<<11) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_SOP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC5_SOP_FIFO_ERROR_SHIFT                                                        11
+  #define BRB_REG_INT_MASK_7_WC5_QUEUE_FIFO_ERROR                                                            (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_QUEUE_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC5_QUEUE_FIFO_ERROR_SHIFT                                                      12
+  #define BRB_REG_INT_MASK_7_WC5_FREE_POINT_FIFO_ERROR                                                       (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_FREE_POINT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC5_FREE_POINT_FIFO_ERROR_SHIFT                                                 13
+  #define BRB_REG_INT_MASK_7_WC5_NEXT_POINT_FIFO_ERROR                                                       (0x1<<14) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_NEXT_POINT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC5_NEXT_POINT_FIFO_ERROR_SHIFT                                                 14
+  #define BRB_REG_INT_MASK_7_WC5_STRT_FIFO_ERROR                                                             (0x1<<15) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_STRT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC5_STRT_FIFO_ERROR_SHIFT                                                       15
+  #define BRB_REG_INT_MASK_7_WC5_SECOND_DSCR_FIFO_ERROR                                                      (0x1<<16) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_SECOND_DSCR_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC5_SECOND_DSCR_FIFO_ERROR_SHIFT                                                16
+  #define BRB_REG_INT_MASK_7_WC5_PKT_AVAIL_FIFO_ERROR                                                        (0x1<<17) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_PKT_AVAIL_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC5_PKT_AVAIL_FIFO_ERROR_SHIFT                                                  17
+  #define BRB_REG_INT_MASK_7_WC5_COS_CNT_FIFO_ERROR                                                          (0x1<<18) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_COS_CNT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC5_COS_CNT_FIFO_ERROR_SHIFT                                                    18
+  #define BRB_REG_INT_MASK_7_WC5_NOTIFY_FIFO_ERROR                                                           (0x1<<19) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_NOTIFY_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC5_NOTIFY_FIFO_ERROR_SHIFT                                                     19
+  #define BRB_REG_INT_MASK_7_WC5_LL_REQ_FIFO_ERROR                                                           (0x1<<20) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_LL_REQ_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC5_LL_REQ_FIFO_ERROR_SHIFT                                                     20
+  #define BRB_REG_INT_MASK_7_WC5_LL_PA_CNT_ERROR                                                             (0x1<<21) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_LL_PA_CNT_ERROR .
+  #define BRB_REG_INT_MASK_7_WC5_LL_PA_CNT_ERROR_SHIFT                                                       21
+  #define BRB_REG_INT_MASK_7_WC5_BB_PA_CNT_ERROR                                                             (0x1<<22) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_BB_PA_CNT_ERROR .
+  #define BRB_REG_INT_MASK_7_WC5_BB_PA_CNT_ERROR_SHIFT                                                       22
+  #define BRB_REG_INT_MASK_7_WC6_INP_FIFO_ERROR                                                              (0x1<<23) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_INP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC6_INP_FIFO_ERROR_SHIFT                                                        23
+  #define BRB_REG_INT_MASK_7_WC6_SOP_FIFO_ERROR                                                              (0x1<<24) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_SOP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC6_SOP_FIFO_ERROR_SHIFT                                                        24
+  #define BRB_REG_INT_MASK_7_WC6_QUEUE_FIFO_ERROR                                                            (0x1<<25) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_QUEUE_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC6_QUEUE_FIFO_ERROR_SHIFT                                                      25
+  #define BRB_REG_INT_MASK_7_WC6_FREE_POINT_FIFO_ERROR                                                       (0x1<<26) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_FREE_POINT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC6_FREE_POINT_FIFO_ERROR_SHIFT                                                 26
+  #define BRB_REG_INT_MASK_7_WC6_NEXT_POINT_FIFO_ERROR                                                       (0x1<<27) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_NEXT_POINT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC6_NEXT_POINT_FIFO_ERROR_SHIFT                                                 27
+  #define BRB_REG_INT_MASK_7_WC6_STRT_FIFO_ERROR                                                             (0x1<<28) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_STRT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC6_STRT_FIFO_ERROR_SHIFT                                                       28
+  #define BRB_REG_INT_MASK_7_WC6_SECOND_DSCR_FIFO_ERROR                                                      (0x1<<29) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_SECOND_DSCR_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC6_SECOND_DSCR_FIFO_ERROR_SHIFT                                                29
+  #define BRB_REG_INT_MASK_7_WC6_PKT_AVAIL_FIFO_ERROR                                                        (0x1<<30) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_PKT_AVAIL_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC6_PKT_AVAIL_FIFO_ERROR_SHIFT                                                  30
+  #define BRB_REG_INT_MASK_7_WC6_COS_CNT_FIFO_ERROR                                                          (0x1<<31) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_COS_CNT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_7_WC6_COS_CNT_FIFO_ERROR_SHIFT                                                    31
+#define BRB_REG_INT_STS_WR_7                                                                                 0x340170UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define BRB_REG_INT_STS_WR_7_WC4_FREE_POINT_FIFO_ERROR                                                     (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 4
+  #define BRB_REG_INT_STS_WR_7_WC4_FREE_POINT_FIFO_ERROR_SHIFT                                               0
+  #define BRB_REG_INT_STS_WR_7_WC4_NEXT_POINT_FIFO_ERROR                                                     (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 4
+  #define BRB_REG_INT_STS_WR_7_WC4_NEXT_POINT_FIFO_ERROR_SHIFT                                               1
+  #define BRB_REG_INT_STS_WR_7_WC4_STRT_FIFO_ERROR                                                           (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 4
+  #define BRB_REG_INT_STS_WR_7_WC4_STRT_FIFO_ERROR_SHIFT                                                     2
+  #define BRB_REG_INT_STS_WR_7_WC4_SECOND_DSCR_FIFO_ERROR                                                    (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 4
+  #define BRB_REG_INT_STS_WR_7_WC4_SECOND_DSCR_FIFO_ERROR_SHIFT                                              3
+  #define BRB_REG_INT_STS_WR_7_WC4_PKT_AVAIL_FIFO_ERROR                                                      (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 4
+  #define BRB_REG_INT_STS_WR_7_WC4_PKT_AVAIL_FIFO_ERROR_SHIFT                                                4
+  #define BRB_REG_INT_STS_WR_7_WC4_COS_CNT_FIFO_ERROR                                                        (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 4
+  #define BRB_REG_INT_STS_WR_7_WC4_COS_CNT_FIFO_ERROR_SHIFT                                                  5
+  #define BRB_REG_INT_STS_WR_7_WC4_NOTIFY_FIFO_ERROR                                                         (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 4
+  #define BRB_REG_INT_STS_WR_7_WC4_NOTIFY_FIFO_ERROR_SHIFT                                                   6
+  #define BRB_REG_INT_STS_WR_7_WC4_LL_REQ_FIFO_ERROR                                                         (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 4
+  #define BRB_REG_INT_STS_WR_7_WC4_LL_REQ_FIFO_ERROR_SHIFT                                                   7
+  #define BRB_REG_INT_STS_WR_7_WC4_LL_PA_CNT_ERROR                                                           (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 4
+  #define BRB_REG_INT_STS_WR_7_WC4_LL_PA_CNT_ERROR_SHIFT                                                     8
+  #define BRB_REG_INT_STS_WR_7_WC4_BB_PA_CNT_ERROR                                                           (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 4
+  #define BRB_REG_INT_STS_WR_7_WC4_BB_PA_CNT_ERROR_SHIFT                                                     9
+  #define BRB_REG_INT_STS_WR_7_WC5_INP_FIFO_ERROR                                                            (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 5
+  #define BRB_REG_INT_STS_WR_7_WC5_INP_FIFO_ERROR_SHIFT                                                      10
+  #define BRB_REG_INT_STS_WR_7_WC5_SOP_FIFO_ERROR                                                            (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 5
+  #define BRB_REG_INT_STS_WR_7_WC5_SOP_FIFO_ERROR_SHIFT                                                      11
+  #define BRB_REG_INT_STS_WR_7_WC5_QUEUE_FIFO_ERROR                                                          (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 5
+  #define BRB_REG_INT_STS_WR_7_WC5_QUEUE_FIFO_ERROR_SHIFT                                                    12
+  #define BRB_REG_INT_STS_WR_7_WC5_FREE_POINT_FIFO_ERROR                                                     (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 5
+  #define BRB_REG_INT_STS_WR_7_WC5_FREE_POINT_FIFO_ERROR_SHIFT                                               13
+  #define BRB_REG_INT_STS_WR_7_WC5_NEXT_POINT_FIFO_ERROR                                                     (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 5
+  #define BRB_REG_INT_STS_WR_7_WC5_NEXT_POINT_FIFO_ERROR_SHIFT                                               14
+  #define BRB_REG_INT_STS_WR_7_WC5_STRT_FIFO_ERROR                                                           (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 5
+  #define BRB_REG_INT_STS_WR_7_WC5_STRT_FIFO_ERROR_SHIFT                                                     15
+  #define BRB_REG_INT_STS_WR_7_WC5_SECOND_DSCR_FIFO_ERROR                                                    (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 5
+  #define BRB_REG_INT_STS_WR_7_WC5_SECOND_DSCR_FIFO_ERROR_SHIFT                                              16
+  #define BRB_REG_INT_STS_WR_7_WC5_PKT_AVAIL_FIFO_ERROR                                                      (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 5
+  #define BRB_REG_INT_STS_WR_7_WC5_PKT_AVAIL_FIFO_ERROR_SHIFT                                                17
+  #define BRB_REG_INT_STS_WR_7_WC5_COS_CNT_FIFO_ERROR                                                        (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 5
+  #define BRB_REG_INT_STS_WR_7_WC5_COS_CNT_FIFO_ERROR_SHIFT                                                  18
+  #define BRB_REG_INT_STS_WR_7_WC5_NOTIFY_FIFO_ERROR                                                         (0x1<<19) // Notify FIFO error in write client 5
+  #define BRB_REG_INT_STS_WR_7_WC5_NOTIFY_FIFO_ERROR_SHIFT                                                   19
+  #define BRB_REG_INT_STS_WR_7_WC5_LL_REQ_FIFO_ERROR                                                         (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 5
+  #define BRB_REG_INT_STS_WR_7_WC5_LL_REQ_FIFO_ERROR_SHIFT                                                   20
+  #define BRB_REG_INT_STS_WR_7_WC5_LL_PA_CNT_ERROR                                                           (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 5
+  #define BRB_REG_INT_STS_WR_7_WC5_LL_PA_CNT_ERROR_SHIFT                                                     21
+  #define BRB_REG_INT_STS_WR_7_WC5_BB_PA_CNT_ERROR                                                           (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 5
+  #define BRB_REG_INT_STS_WR_7_WC5_BB_PA_CNT_ERROR_SHIFT                                                     22
+  #define BRB_REG_INT_STS_WR_7_WC6_INP_FIFO_ERROR                                                            (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 6
+  #define BRB_REG_INT_STS_WR_7_WC6_INP_FIFO_ERROR_SHIFT                                                      23
+  #define BRB_REG_INT_STS_WR_7_WC6_SOP_FIFO_ERROR                                                            (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 6
+  #define BRB_REG_INT_STS_WR_7_WC6_SOP_FIFO_ERROR_SHIFT                                                      24
+  #define BRB_REG_INT_STS_WR_7_WC6_QUEUE_FIFO_ERROR                                                          (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 6
+  #define BRB_REG_INT_STS_WR_7_WC6_QUEUE_FIFO_ERROR_SHIFT                                                    25
+  #define BRB_REG_INT_STS_WR_7_WC6_FREE_POINT_FIFO_ERROR                                                     (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 6
+  #define BRB_REG_INT_STS_WR_7_WC6_FREE_POINT_FIFO_ERROR_SHIFT                                               26
+  #define BRB_REG_INT_STS_WR_7_WC6_NEXT_POINT_FIFO_ERROR                                                     (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 6
+  #define BRB_REG_INT_STS_WR_7_WC6_NEXT_POINT_FIFO_ERROR_SHIFT                                               27
+  #define BRB_REG_INT_STS_WR_7_WC6_STRT_FIFO_ERROR                                                           (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 6
+  #define BRB_REG_INT_STS_WR_7_WC6_STRT_FIFO_ERROR_SHIFT                                                     28
+  #define BRB_REG_INT_STS_WR_7_WC6_SECOND_DSCR_FIFO_ERROR                                                    (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 6
+  #define BRB_REG_INT_STS_WR_7_WC6_SECOND_DSCR_FIFO_ERROR_SHIFT                                              29
+  #define BRB_REG_INT_STS_WR_7_WC6_PKT_AVAIL_FIFO_ERROR                                                      (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 6
+  #define BRB_REG_INT_STS_WR_7_WC6_PKT_AVAIL_FIFO_ERROR_SHIFT                                                30
+  #define BRB_REG_INT_STS_WR_7_WC6_COS_CNT_FIFO_ERROR                                                        (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 6
+  #define BRB_REG_INT_STS_WR_7_WC6_COS_CNT_FIFO_ERROR_SHIFT                                                  31
+#define BRB_REG_INT_STS_CLR_7                                                                                0x340174UL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define BRB_REG_INT_STS_CLR_7_WC4_FREE_POINT_FIFO_ERROR                                                    (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 4
+  #define BRB_REG_INT_STS_CLR_7_WC4_FREE_POINT_FIFO_ERROR_SHIFT                                              0
+  #define BRB_REG_INT_STS_CLR_7_WC4_NEXT_POINT_FIFO_ERROR                                                    (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 4
+  #define BRB_REG_INT_STS_CLR_7_WC4_NEXT_POINT_FIFO_ERROR_SHIFT                                              1
+  #define BRB_REG_INT_STS_CLR_7_WC4_STRT_FIFO_ERROR                                                          (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 4
+  #define BRB_REG_INT_STS_CLR_7_WC4_STRT_FIFO_ERROR_SHIFT                                                    2
+  #define BRB_REG_INT_STS_CLR_7_WC4_SECOND_DSCR_FIFO_ERROR                                                   (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 4
+  #define BRB_REG_INT_STS_CLR_7_WC4_SECOND_DSCR_FIFO_ERROR_SHIFT                                             3
+  #define BRB_REG_INT_STS_CLR_7_WC4_PKT_AVAIL_FIFO_ERROR                                                     (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 4
+  #define BRB_REG_INT_STS_CLR_7_WC4_PKT_AVAIL_FIFO_ERROR_SHIFT                                               4
+  #define BRB_REG_INT_STS_CLR_7_WC4_COS_CNT_FIFO_ERROR                                                       (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 4
+  #define BRB_REG_INT_STS_CLR_7_WC4_COS_CNT_FIFO_ERROR_SHIFT                                                 5
+  #define BRB_REG_INT_STS_CLR_7_WC4_NOTIFY_FIFO_ERROR                                                        (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 4
+  #define BRB_REG_INT_STS_CLR_7_WC4_NOTIFY_FIFO_ERROR_SHIFT                                                  6
+  #define BRB_REG_INT_STS_CLR_7_WC4_LL_REQ_FIFO_ERROR                                                        (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 4
+  #define BRB_REG_INT_STS_CLR_7_WC4_LL_REQ_FIFO_ERROR_SHIFT                                                  7
+  #define BRB_REG_INT_STS_CLR_7_WC4_LL_PA_CNT_ERROR                                                          (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 4
+  #define BRB_REG_INT_STS_CLR_7_WC4_LL_PA_CNT_ERROR_SHIFT                                                    8
+  #define BRB_REG_INT_STS_CLR_7_WC4_BB_PA_CNT_ERROR                                                          (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 4
+  #define BRB_REG_INT_STS_CLR_7_WC4_BB_PA_CNT_ERROR_SHIFT                                                    9
+  #define BRB_REG_INT_STS_CLR_7_WC5_INP_FIFO_ERROR                                                           (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 5
+  #define BRB_REG_INT_STS_CLR_7_WC5_INP_FIFO_ERROR_SHIFT                                                     10
+  #define BRB_REG_INT_STS_CLR_7_WC5_SOP_FIFO_ERROR                                                           (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 5
+  #define BRB_REG_INT_STS_CLR_7_WC5_SOP_FIFO_ERROR_SHIFT                                                     11
+  #define BRB_REG_INT_STS_CLR_7_WC5_QUEUE_FIFO_ERROR                                                         (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 5
+  #define BRB_REG_INT_STS_CLR_7_WC5_QUEUE_FIFO_ERROR_SHIFT                                                   12
+  #define BRB_REG_INT_STS_CLR_7_WC5_FREE_POINT_FIFO_ERROR                                                    (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 5
+  #define BRB_REG_INT_STS_CLR_7_WC5_FREE_POINT_FIFO_ERROR_SHIFT                                              13
+  #define BRB_REG_INT_STS_CLR_7_WC5_NEXT_POINT_FIFO_ERROR                                                    (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 5
+  #define BRB_REG_INT_STS_CLR_7_WC5_NEXT_POINT_FIFO_ERROR_SHIFT                                              14
+  #define BRB_REG_INT_STS_CLR_7_WC5_STRT_FIFO_ERROR                                                          (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 5
+  #define BRB_REG_INT_STS_CLR_7_WC5_STRT_FIFO_ERROR_SHIFT                                                    15
+  #define BRB_REG_INT_STS_CLR_7_WC5_SECOND_DSCR_FIFO_ERROR                                                   (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 5
+  #define BRB_REG_INT_STS_CLR_7_WC5_SECOND_DSCR_FIFO_ERROR_SHIFT                                             16
+  #define BRB_REG_INT_STS_CLR_7_WC5_PKT_AVAIL_FIFO_ERROR                                                     (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 5
+  #define BRB_REG_INT_STS_CLR_7_WC5_PKT_AVAIL_FIFO_ERROR_SHIFT                                               17
+  #define BRB_REG_INT_STS_CLR_7_WC5_COS_CNT_FIFO_ERROR                                                       (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 5
+  #define BRB_REG_INT_STS_CLR_7_WC5_COS_CNT_FIFO_ERROR_SHIFT                                                 18
+  #define BRB_REG_INT_STS_CLR_7_WC5_NOTIFY_FIFO_ERROR                                                        (0x1<<19) // Notify FIFO error in write client 5
+  #define BRB_REG_INT_STS_CLR_7_WC5_NOTIFY_FIFO_ERROR_SHIFT                                                  19
+  #define BRB_REG_INT_STS_CLR_7_WC5_LL_REQ_FIFO_ERROR                                                        (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 5
+  #define BRB_REG_INT_STS_CLR_7_WC5_LL_REQ_FIFO_ERROR_SHIFT                                                  20
+  #define BRB_REG_INT_STS_CLR_7_WC5_LL_PA_CNT_ERROR                                                          (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 5
+  #define BRB_REG_INT_STS_CLR_7_WC5_LL_PA_CNT_ERROR_SHIFT                                                    21
+  #define BRB_REG_INT_STS_CLR_7_WC5_BB_PA_CNT_ERROR                                                          (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 5
+  #define BRB_REG_INT_STS_CLR_7_WC5_BB_PA_CNT_ERROR_SHIFT                                                    22
+  #define BRB_REG_INT_STS_CLR_7_WC6_INP_FIFO_ERROR                                                           (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 6
+  #define BRB_REG_INT_STS_CLR_7_WC6_INP_FIFO_ERROR_SHIFT                                                     23
+  #define BRB_REG_INT_STS_CLR_7_WC6_SOP_FIFO_ERROR                                                           (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 6
+  #define BRB_REG_INT_STS_CLR_7_WC6_SOP_FIFO_ERROR_SHIFT                                                     24
+  #define BRB_REG_INT_STS_CLR_7_WC6_QUEUE_FIFO_ERROR                                                         (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 6
+  #define BRB_REG_INT_STS_CLR_7_WC6_QUEUE_FIFO_ERROR_SHIFT                                                   25
+  #define BRB_REG_INT_STS_CLR_7_WC6_FREE_POINT_FIFO_ERROR                                                    (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 6
+  #define BRB_REG_INT_STS_CLR_7_WC6_FREE_POINT_FIFO_ERROR_SHIFT                                              26
+  #define BRB_REG_INT_STS_CLR_7_WC6_NEXT_POINT_FIFO_ERROR                                                    (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 6
+  #define BRB_REG_INT_STS_CLR_7_WC6_NEXT_POINT_FIFO_ERROR_SHIFT                                              27
+  #define BRB_REG_INT_STS_CLR_7_WC6_STRT_FIFO_ERROR                                                          (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 6
+  #define BRB_REG_INT_STS_CLR_7_WC6_STRT_FIFO_ERROR_SHIFT                                                    28
+  #define BRB_REG_INT_STS_CLR_7_WC6_SECOND_DSCR_FIFO_ERROR                                                   (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 6
+  #define BRB_REG_INT_STS_CLR_7_WC6_SECOND_DSCR_FIFO_ERROR_SHIFT                                             29
+  #define BRB_REG_INT_STS_CLR_7_WC6_PKT_AVAIL_FIFO_ERROR                                                     (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 6
+  #define BRB_REG_INT_STS_CLR_7_WC6_PKT_AVAIL_FIFO_ERROR_SHIFT                                               30
+  #define BRB_REG_INT_STS_CLR_7_WC6_COS_CNT_FIFO_ERROR                                                       (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 6
+  #define BRB_REG_INT_STS_CLR_7_WC6_COS_CNT_FIFO_ERROR_SHIFT                                                 31
+#define BRB_REG_INT_STS_8                                                                                    0x340184UL //Access:R    DataWidth:0x11   // Multi Field Register.
+  #define BRB_REG_INT_STS_8_WC6_NOTIFY_FIFO_ERROR                                                            (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
+  #define BRB_REG_INT_STS_8_WC6_NOTIFY_FIFO_ERROR_SHIFT                                                      0
+  #define BRB_REG_INT_STS_8_WC6_LL_REQ_FIFO_ERROR                                                            (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 6
+  #define BRB_REG_INT_STS_8_WC6_LL_REQ_FIFO_ERROR_SHIFT                                                      1
+  #define BRB_REG_INT_STS_8_WC6_LL_PA_CNT_ERROR                                                              (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 6
+  #define BRB_REG_INT_STS_8_WC6_LL_PA_CNT_ERROR_SHIFT                                                        2
+  #define BRB_REG_INT_STS_8_WC6_BB_PA_CNT_ERROR                                                              (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 6
+  #define BRB_REG_INT_STS_8_WC6_BB_PA_CNT_ERROR_SHIFT                                                        3
+  #define BRB_REG_INT_STS_8_WC7_INP_FIFO_ERROR                                                               (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 7
+  #define BRB_REG_INT_STS_8_WC7_INP_FIFO_ERROR_SHIFT                                                         4
+  #define BRB_REG_INT_STS_8_WC7_SOP_FIFO_ERROR                                                               (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 7
+  #define BRB_REG_INT_STS_8_WC7_SOP_FIFO_ERROR_SHIFT                                                         5
+  #define BRB_REG_INT_STS_8_WC7_QUEUE_FIFO_ERROR                                                             (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 7
+  #define BRB_REG_INT_STS_8_WC7_QUEUE_FIFO_ERROR_SHIFT                                                       6
+  #define BRB_REG_INT_STS_8_WC7_FREE_POINT_FIFO_ERROR                                                        (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 7
+  #define BRB_REG_INT_STS_8_WC7_FREE_POINT_FIFO_ERROR_SHIFT                                                  7
+  #define BRB_REG_INT_STS_8_WC7_NEXT_POINT_FIFO_ERROR                                                        (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 7
+  #define BRB_REG_INT_STS_8_WC7_NEXT_POINT_FIFO_ERROR_SHIFT                                                  8
+  #define BRB_REG_INT_STS_8_WC7_STRT_FIFO_ERROR                                                              (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 7
+  #define BRB_REG_INT_STS_8_WC7_STRT_FIFO_ERROR_SHIFT                                                        9
+  #define BRB_REG_INT_STS_8_WC7_SECOND_DSCR_FIFO_ERROR                                                       (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 7
+  #define BRB_REG_INT_STS_8_WC7_SECOND_DSCR_FIFO_ERROR_SHIFT                                                 10
+  #define BRB_REG_INT_STS_8_WC7_PKT_AVAIL_FIFO_ERROR                                                         (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 7
+  #define BRB_REG_INT_STS_8_WC7_PKT_AVAIL_FIFO_ERROR_SHIFT                                                   11
+  #define BRB_REG_INT_STS_8_WC7_COS_CNT_FIFO_ERROR                                                           (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 7
+  #define BRB_REG_INT_STS_8_WC7_COS_CNT_FIFO_ERROR_SHIFT                                                     12
+  #define BRB_REG_INT_STS_8_WC7_NOTIFY_FIFO_ERROR                                                            (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 7
+  #define BRB_REG_INT_STS_8_WC7_NOTIFY_FIFO_ERROR_SHIFT                                                      13
+  #define BRB_REG_INT_STS_8_WC7_LL_REQ_FIFO_ERROR                                                            (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 7
+  #define BRB_REG_INT_STS_8_WC7_LL_REQ_FIFO_ERROR_SHIFT                                                      14
+  #define BRB_REG_INT_STS_8_WC7_LL_PA_CNT_ERROR                                                              (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 7
+  #define BRB_REG_INT_STS_8_WC7_LL_PA_CNT_ERROR_SHIFT                                                        15
+  #define BRB_REG_INT_STS_8_WC7_BB_PA_CNT_ERROR                                                              (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 7
+  #define BRB_REG_INT_STS_8_WC7_BB_PA_CNT_ERROR_SHIFT                                                        16
+#define BRB_REG_INT_MASK_8                                                                                   0x340188UL //Access:RW   DataWidth:0x11   // Multi Field Register.
+  #define BRB_REG_INT_MASK_8_WC6_NOTIFY_FIFO_ERROR                                                           (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC6_NOTIFY_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_8_WC6_NOTIFY_FIFO_ERROR_SHIFT                                                     0
+  #define BRB_REG_INT_MASK_8_WC6_LL_REQ_FIFO_ERROR                                                           (0x1<<1) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC6_LL_REQ_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_8_WC6_LL_REQ_FIFO_ERROR_SHIFT                                                     1
+  #define BRB_REG_INT_MASK_8_WC6_LL_PA_CNT_ERROR                                                             (0x1<<2) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC6_LL_PA_CNT_ERROR .
+  #define BRB_REG_INT_MASK_8_WC6_LL_PA_CNT_ERROR_SHIFT                                                       2
+  #define BRB_REG_INT_MASK_8_WC6_BB_PA_CNT_ERROR                                                             (0x1<<3) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC6_BB_PA_CNT_ERROR .
+  #define BRB_REG_INT_MASK_8_WC6_BB_PA_CNT_ERROR_SHIFT                                                       3
+  #define BRB_REG_INT_MASK_8_WC7_INP_FIFO_ERROR                                                              (0x1<<4) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_INP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_8_WC7_INP_FIFO_ERROR_SHIFT                                                        4
+  #define BRB_REG_INT_MASK_8_WC7_SOP_FIFO_ERROR                                                              (0x1<<5) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_SOP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_8_WC7_SOP_FIFO_ERROR_SHIFT                                                        5
+  #define BRB_REG_INT_MASK_8_WC7_QUEUE_FIFO_ERROR                                                            (0x1<<6) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_QUEUE_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_8_WC7_QUEUE_FIFO_ERROR_SHIFT                                                      6
+  #define BRB_REG_INT_MASK_8_WC7_FREE_POINT_FIFO_ERROR                                                       (0x1<<7) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_FREE_POINT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_8_WC7_FREE_POINT_FIFO_ERROR_SHIFT                                                 7
+  #define BRB_REG_INT_MASK_8_WC7_NEXT_POINT_FIFO_ERROR                                                       (0x1<<8) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_NEXT_POINT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_8_WC7_NEXT_POINT_FIFO_ERROR_SHIFT                                                 8
+  #define BRB_REG_INT_MASK_8_WC7_STRT_FIFO_ERROR                                                             (0x1<<9) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_STRT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_8_WC7_STRT_FIFO_ERROR_SHIFT                                                       9
+  #define BRB_REG_INT_MASK_8_WC7_SECOND_DSCR_FIFO_ERROR                                                      (0x1<<10) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_SECOND_DSCR_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_8_WC7_SECOND_DSCR_FIFO_ERROR_SHIFT                                                10
+  #define BRB_REG_INT_MASK_8_WC7_PKT_AVAIL_FIFO_ERROR                                                        (0x1<<11) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_PKT_AVAIL_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_8_WC7_PKT_AVAIL_FIFO_ERROR_SHIFT                                                  11
+  #define BRB_REG_INT_MASK_8_WC7_COS_CNT_FIFO_ERROR                                                          (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_COS_CNT_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_8_WC7_COS_CNT_FIFO_ERROR_SHIFT                                                    12
+  #define BRB_REG_INT_MASK_8_WC7_NOTIFY_FIFO_ERROR                                                           (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_NOTIFY_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_8_WC7_NOTIFY_FIFO_ERROR_SHIFT                                                     13
+  #define BRB_REG_INT_MASK_8_WC7_LL_REQ_FIFO_ERROR                                                           (0x1<<14) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_LL_REQ_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_8_WC7_LL_REQ_FIFO_ERROR_SHIFT                                                     14
+  #define BRB_REG_INT_MASK_8_WC7_LL_PA_CNT_ERROR                                                             (0x1<<15) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_LL_PA_CNT_ERROR .
+  #define BRB_REG_INT_MASK_8_WC7_LL_PA_CNT_ERROR_SHIFT                                                       15
+  #define BRB_REG_INT_MASK_8_WC7_BB_PA_CNT_ERROR                                                             (0x1<<16) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_BB_PA_CNT_ERROR .
+  #define BRB_REG_INT_MASK_8_WC7_BB_PA_CNT_ERROR_SHIFT                                                       16
+#define BRB_REG_INT_STS_WR_8                                                                                 0x34018cUL //Access:WR   DataWidth:0x11   // Multi Field Register.
+  #define BRB_REG_INT_STS_WR_8_WC6_NOTIFY_FIFO_ERROR                                                         (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
+  #define BRB_REG_INT_STS_WR_8_WC6_NOTIFY_FIFO_ERROR_SHIFT                                                   0
+  #define BRB_REG_INT_STS_WR_8_WC6_LL_REQ_FIFO_ERROR                                                         (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 6
+  #define BRB_REG_INT_STS_WR_8_WC6_LL_REQ_FIFO_ERROR_SHIFT                                                   1
+  #define BRB_REG_INT_STS_WR_8_WC6_LL_PA_CNT_ERROR                                                           (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 6
+  #define BRB_REG_INT_STS_WR_8_WC6_LL_PA_CNT_ERROR_SHIFT                                                     2
+  #define BRB_REG_INT_STS_WR_8_WC6_BB_PA_CNT_ERROR                                                           (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 6
+  #define BRB_REG_INT_STS_WR_8_WC6_BB_PA_CNT_ERROR_SHIFT                                                     3
+  #define BRB_REG_INT_STS_WR_8_WC7_INP_FIFO_ERROR                                                            (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 7
+  #define BRB_REG_INT_STS_WR_8_WC7_INP_FIFO_ERROR_SHIFT                                                      4
+  #define BRB_REG_INT_STS_WR_8_WC7_SOP_FIFO_ERROR                                                            (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 7
+  #define BRB_REG_INT_STS_WR_8_WC7_SOP_FIFO_ERROR_SHIFT                                                      5
+  #define BRB_REG_INT_STS_WR_8_WC7_QUEUE_FIFO_ERROR                                                          (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 7
+  #define BRB_REG_INT_STS_WR_8_WC7_QUEUE_FIFO_ERROR_SHIFT                                                    6
+  #define BRB_REG_INT_STS_WR_8_WC7_FREE_POINT_FIFO_ERROR                                                     (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 7
+  #define BRB_REG_INT_STS_WR_8_WC7_FREE_POINT_FIFO_ERROR_SHIFT                                               7
+  #define BRB_REG_INT_STS_WR_8_WC7_NEXT_POINT_FIFO_ERROR                                                     (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 7
+  #define BRB_REG_INT_STS_WR_8_WC7_NEXT_POINT_FIFO_ERROR_SHIFT                                               8
+  #define BRB_REG_INT_STS_WR_8_WC7_STRT_FIFO_ERROR                                                           (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 7
+  #define BRB_REG_INT_STS_WR_8_WC7_STRT_FIFO_ERROR_SHIFT                                                     9
+  #define BRB_REG_INT_STS_WR_8_WC7_SECOND_DSCR_FIFO_ERROR                                                    (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 7
+  #define BRB_REG_INT_STS_WR_8_WC7_SECOND_DSCR_FIFO_ERROR_SHIFT                                              10
+  #define BRB_REG_INT_STS_WR_8_WC7_PKT_AVAIL_FIFO_ERROR                                                      (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 7
+  #define BRB_REG_INT_STS_WR_8_WC7_PKT_AVAIL_FIFO_ERROR_SHIFT                                                11
+  #define BRB_REG_INT_STS_WR_8_WC7_COS_CNT_FIFO_ERROR                                                        (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 7
+  #define BRB_REG_INT_STS_WR_8_WC7_COS_CNT_FIFO_ERROR_SHIFT                                                  12
+  #define BRB_REG_INT_STS_WR_8_WC7_NOTIFY_FIFO_ERROR                                                         (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 7
+  #define BRB_REG_INT_STS_WR_8_WC7_NOTIFY_FIFO_ERROR_SHIFT                                                   13
+  #define BRB_REG_INT_STS_WR_8_WC7_LL_REQ_FIFO_ERROR                                                         (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 7
+  #define BRB_REG_INT_STS_WR_8_WC7_LL_REQ_FIFO_ERROR_SHIFT                                                   14
+  #define BRB_REG_INT_STS_WR_8_WC7_LL_PA_CNT_ERROR                                                           (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 7
+  #define BRB_REG_INT_STS_WR_8_WC7_LL_PA_CNT_ERROR_SHIFT                                                     15
+  #define BRB_REG_INT_STS_WR_8_WC7_BB_PA_CNT_ERROR                                                           (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 7
+  #define BRB_REG_INT_STS_WR_8_WC7_BB_PA_CNT_ERROR_SHIFT                                                     16
+#define BRB_REG_INT_STS_CLR_8                                                                                0x340190UL //Access:RC   DataWidth:0x11   // Multi Field Register.
+  #define BRB_REG_INT_STS_CLR_8_WC6_NOTIFY_FIFO_ERROR                                                        (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
+  #define BRB_REG_INT_STS_CLR_8_WC6_NOTIFY_FIFO_ERROR_SHIFT                                                  0
+  #define BRB_REG_INT_STS_CLR_8_WC6_LL_REQ_FIFO_ERROR                                                        (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 6
+  #define BRB_REG_INT_STS_CLR_8_WC6_LL_REQ_FIFO_ERROR_SHIFT                                                  1
+  #define BRB_REG_INT_STS_CLR_8_WC6_LL_PA_CNT_ERROR                                                          (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 6
+  #define BRB_REG_INT_STS_CLR_8_WC6_LL_PA_CNT_ERROR_SHIFT                                                    2
+  #define BRB_REG_INT_STS_CLR_8_WC6_BB_PA_CNT_ERROR                                                          (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 6
+  #define BRB_REG_INT_STS_CLR_8_WC6_BB_PA_CNT_ERROR_SHIFT                                                    3
+  #define BRB_REG_INT_STS_CLR_8_WC7_INP_FIFO_ERROR                                                           (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 7
+  #define BRB_REG_INT_STS_CLR_8_WC7_INP_FIFO_ERROR_SHIFT                                                     4
+  #define BRB_REG_INT_STS_CLR_8_WC7_SOP_FIFO_ERROR                                                           (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 7
+  #define BRB_REG_INT_STS_CLR_8_WC7_SOP_FIFO_ERROR_SHIFT                                                     5
+  #define BRB_REG_INT_STS_CLR_8_WC7_QUEUE_FIFO_ERROR                                                         (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 7
+  #define BRB_REG_INT_STS_CLR_8_WC7_QUEUE_FIFO_ERROR_SHIFT                                                   6
+  #define BRB_REG_INT_STS_CLR_8_WC7_FREE_POINT_FIFO_ERROR                                                    (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 7
+  #define BRB_REG_INT_STS_CLR_8_WC7_FREE_POINT_FIFO_ERROR_SHIFT                                              7
+  #define BRB_REG_INT_STS_CLR_8_WC7_NEXT_POINT_FIFO_ERROR                                                    (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 7
+  #define BRB_REG_INT_STS_CLR_8_WC7_NEXT_POINT_FIFO_ERROR_SHIFT                                              8
+  #define BRB_REG_INT_STS_CLR_8_WC7_STRT_FIFO_ERROR                                                          (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 7
+  #define BRB_REG_INT_STS_CLR_8_WC7_STRT_FIFO_ERROR_SHIFT                                                    9
+  #define BRB_REG_INT_STS_CLR_8_WC7_SECOND_DSCR_FIFO_ERROR                                                   (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 7
+  #define BRB_REG_INT_STS_CLR_8_WC7_SECOND_DSCR_FIFO_ERROR_SHIFT                                             10
+  #define BRB_REG_INT_STS_CLR_8_WC7_PKT_AVAIL_FIFO_ERROR                                                     (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 7
+  #define BRB_REG_INT_STS_CLR_8_WC7_PKT_AVAIL_FIFO_ERROR_SHIFT                                               11
+  #define BRB_REG_INT_STS_CLR_8_WC7_COS_CNT_FIFO_ERROR                                                       (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 7
+  #define BRB_REG_INT_STS_CLR_8_WC7_COS_CNT_FIFO_ERROR_SHIFT                                                 12
+  #define BRB_REG_INT_STS_CLR_8_WC7_NOTIFY_FIFO_ERROR                                                        (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 7
+  #define BRB_REG_INT_STS_CLR_8_WC7_NOTIFY_FIFO_ERROR_SHIFT                                                  13
+  #define BRB_REG_INT_STS_CLR_8_WC7_LL_REQ_FIFO_ERROR                                                        (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 7
+  #define BRB_REG_INT_STS_CLR_8_WC7_LL_REQ_FIFO_ERROR_SHIFT                                                  14
+  #define BRB_REG_INT_STS_CLR_8_WC7_LL_PA_CNT_ERROR                                                          (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 7
+  #define BRB_REG_INT_STS_CLR_8_WC7_LL_PA_CNT_ERROR_SHIFT                                                    15
+  #define BRB_REG_INT_STS_CLR_8_WC7_BB_PA_CNT_ERROR                                                          (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 7
+  #define BRB_REG_INT_STS_CLR_8_WC7_BB_PA_CNT_ERROR_SHIFT                                                    16
+#define BRB_REG_INT_STS_9                                                                                    0x34019cUL //Access:R    DataWidth:0x1    // Multi Field Register.
+  #define BRB_REG_INT_STS_9_WC9_QUEUE_FIFO_ERROR                                                             (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
+  #define BRB_REG_INT_STS_9_WC9_QUEUE_FIFO_ERROR_SHIFT                                                       0
+#define BRB_REG_INT_MASK_9                                                                                   0x3401a0UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define BRB_REG_INT_MASK_9_WC9_QUEUE_FIFO_ERROR                                                            (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_9.WC9_QUEUE_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_9_WC9_QUEUE_FIFO_ERROR_SHIFT                                                      0
+#define BRB_REG_INT_STS_WR_9                                                                                 0x3401a4UL //Access:WR   DataWidth:0x1    // Multi Field Register.
+  #define BRB_REG_INT_STS_WR_9_WC9_QUEUE_FIFO_ERROR                                                          (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
+  #define BRB_REG_INT_STS_WR_9_WC9_QUEUE_FIFO_ERROR_SHIFT                                                    0
+#define BRB_REG_INT_STS_CLR_9                                                                                0x3401a8UL //Access:RC   DataWidth:0x1    // Multi Field Register.
+  #define BRB_REG_INT_STS_CLR_9_WC9_QUEUE_FIFO_ERROR                                                         (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
+  #define BRB_REG_INT_STS_CLR_9_WC9_QUEUE_FIFO_ERROR_SHIFT                                                   0
+#define BRB_REG_INT_STS_10                                                                                   0x3401b4UL //Access:R    DataWidth:0x1e   // Multi Field Register.
+  #define BRB_REG_INT_STS_10_RC_SOP_INP_SYNC_FIFO_PUSH_ERROR                                                 (0x1<<1) // SOP input SYNC FIFO error (for BRB)
+  #define BRB_REG_INT_STS_10_RC_SOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                           1
+  #define BRB_REG_INT_STS_10_RC0_INP_SYNC_FIFO_PUSH_ERROR                                                    (0x1<<2) // Packet RC input SYNC FIFO error
+  #define BRB_REG_INT_STS_10_RC0_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                              2
+  #define BRB_REG_INT_STS_10_RC1_INP_SYNC_FIFO_PUSH_ERROR                                                    (0x1<<3) // Packet RC input SYNC FIFO error
+  #define BRB_REG_INT_STS_10_RC1_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                              3
+  #define BRB_REG_INT_STS_10_RC2_INP_SYNC_FIFO_PUSH_ERROR                                                    (0x1<<4) // Packet RC input SYNC FIFO error
+  #define BRB_REG_INT_STS_10_RC2_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                              4
+  #define BRB_REG_INT_STS_10_RC3_INP_SYNC_FIFO_PUSH_ERROR                                                    (0x1<<5) // Packet RC input SYNC FIFO error
+  #define BRB_REG_INT_STS_10_RC3_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                              5
+  #define BRB_REG_INT_STS_10_RC0_OUT_SYNC_FIFO_PUSH_ERROR                                                    (0x1<<12) // Packet RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_10_RC0_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                              12
+  #define BRB_REG_INT_STS_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR                                                    (0x1<<13) // Packet RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                              13
+  #define BRB_REG_INT_STS_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR                                                    (0x1<<14) // Packet RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                              14
+  #define BRB_REG_INT_STS_10_RC3_OUT_SYNC_FIFO_PUSH_ERROR                                                    (0x1<<15) // Packet RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_10_RC3_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                              15
+  #define BRB_REG_INT_STS_10_RC4_OUT_SYNC_FIFO_PUSH_ERROR                                                    (0x1<<16) // Packet RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_10_RC4_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                              16
+  #define BRB_REG_INT_STS_10_RC0_EOP_INP_SYNC_FIFO_PUSH_ERROR                                                (0x1<<22) // EOP RC input SYNC FIFO error
+  #define BRB_REG_INT_STS_10_RC0_EOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                          22
+  #define BRB_REG_INT_STS_10_RC1_EOP_INP_SYNC_FIFO_PUSH_ERROR                                                (0x1<<23) // EOP RC input SYNC FIFO error
+  #define BRB_REG_INT_STS_10_RC1_EOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                          23
+  #define BRB_REG_INT_STS_10_RC2_EOP_INP_SYNC_FIFO_PUSH_ERROR_K2_E5                                          (0x1<<24) // EOP RC input SYNC FIFO error
+  #define BRB_REG_INT_STS_10_RC2_EOP_INP_SYNC_FIFO_PUSH_ERROR_K2_E5_SHIFT                                    24
+  #define BRB_REG_INT_STS_10_RC3_EOP_INP_SYNC_FIFO_PUSH_ERROR_K2_E5                                          (0x1<<25) // EOP RC input SYNC FIFO error
+  #define BRB_REG_INT_STS_10_RC3_EOP_INP_SYNC_FIFO_PUSH_ERROR_K2_E5_SHIFT                                    25
+  #define BRB_REG_INT_STS_10_RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR                                                (0x1<<26) // EOP RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_10_RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                          26
+  #define BRB_REG_INT_STS_10_RC1_EOP_OUT_SYNC_FIFO_PUSH_ERROR                                                (0x1<<27) // EOP RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_10_RC1_EOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                          27
+  #define BRB_REG_INT_STS_10_RC2_EOP_OUT_SYNC_FIFO_PUSH_ERROR_K2_E5                                          (0x1<<28) // EOP RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_10_RC2_EOP_OUT_SYNC_FIFO_PUSH_ERROR_K2_E5_SHIFT                                    28
+  #define BRB_REG_INT_STS_10_RC3_EOP_OUT_SYNC_FIFO_PUSH_ERROR_K2_E5                                          (0x1<<29) // EOP RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_10_RC3_EOP_OUT_SYNC_FIFO_PUSH_ERROR_K2_E5_SHIFT                                    29
+#define BRB_REG_INT_MASK_10                                                                                  0x3401b8UL //Access:RW   DataWidth:0x1e   // Multi Field Register.
+  #define BRB_REG_INT_MASK_10_RC_SOP_INP_SYNC_FIFO_PUSH_ERROR                                                (0x1<<1) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC_SOP_INP_SYNC_FIFO_PUSH_ERROR .
+  #define BRB_REG_INT_MASK_10_RC_SOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                          1
+  #define BRB_REG_INT_MASK_10_RC0_INP_SYNC_FIFO_PUSH_ERROR                                                   (0x1<<2) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC0_INP_SYNC_FIFO_PUSH_ERROR .
+  #define BRB_REG_INT_MASK_10_RC0_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                             2
+  #define BRB_REG_INT_MASK_10_RC1_INP_SYNC_FIFO_PUSH_ERROR                                                   (0x1<<3) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC1_INP_SYNC_FIFO_PUSH_ERROR .
+  #define BRB_REG_INT_MASK_10_RC1_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                             3
+  #define BRB_REG_INT_MASK_10_RC2_INP_SYNC_FIFO_PUSH_ERROR                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC2_INP_SYNC_FIFO_PUSH_ERROR .
+  #define BRB_REG_INT_MASK_10_RC2_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                             4
+  #define BRB_REG_INT_MASK_10_RC3_INP_SYNC_FIFO_PUSH_ERROR                                                   (0x1<<5) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC3_INP_SYNC_FIFO_PUSH_ERROR .
+  #define BRB_REG_INT_MASK_10_RC3_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                             5
+  #define BRB_REG_INT_MASK_10_RC0_OUT_SYNC_FIFO_PUSH_ERROR                                                   (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC0_OUT_SYNC_FIFO_PUSH_ERROR .
+  #define BRB_REG_INT_MASK_10_RC0_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                             12
+  #define BRB_REG_INT_MASK_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR                                                   (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC1_OUT_SYNC_FIFO_PUSH_ERROR .
+  #define BRB_REG_INT_MASK_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                             13
+  #define BRB_REG_INT_MASK_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR                                                   (0x1<<14) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC2_OUT_SYNC_FIFO_PUSH_ERROR .
+  #define BRB_REG_INT_MASK_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                             14
+  #define BRB_REG_INT_MASK_10_RC3_OUT_SYNC_FIFO_PUSH_ERROR                                                   (0x1<<15) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC3_OUT_SYNC_FIFO_PUSH_ERROR .
+  #define BRB_REG_INT_MASK_10_RC3_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                             15
+  #define BRB_REG_INT_MASK_10_RC4_OUT_SYNC_FIFO_PUSH_ERROR                                                   (0x1<<16) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC4_OUT_SYNC_FIFO_PUSH_ERROR .
+  #define BRB_REG_INT_MASK_10_RC4_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                             16
+  #define BRB_REG_INT_MASK_10_RC0_EOP_INP_SYNC_FIFO_PUSH_ERROR                                               (0x1<<22) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC0_EOP_INP_SYNC_FIFO_PUSH_ERROR .
+  #define BRB_REG_INT_MASK_10_RC0_EOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                         22
+  #define BRB_REG_INT_MASK_10_RC1_EOP_INP_SYNC_FIFO_PUSH_ERROR                                               (0x1<<23) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC1_EOP_INP_SYNC_FIFO_PUSH_ERROR .
+  #define BRB_REG_INT_MASK_10_RC1_EOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                         23
+  #define BRB_REG_INT_MASK_10_RC2_EOP_INP_SYNC_FIFO_PUSH_ERROR_K2_E5                                         (0x1<<24) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC2_EOP_INP_SYNC_FIFO_PUSH_ERROR .
+  #define BRB_REG_INT_MASK_10_RC2_EOP_INP_SYNC_FIFO_PUSH_ERROR_K2_E5_SHIFT                                   24
+  #define BRB_REG_INT_MASK_10_RC3_EOP_INP_SYNC_FIFO_PUSH_ERROR_K2_E5                                         (0x1<<25) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC3_EOP_INP_SYNC_FIFO_PUSH_ERROR .
+  #define BRB_REG_INT_MASK_10_RC3_EOP_INP_SYNC_FIFO_PUSH_ERROR_K2_E5_SHIFT                                   25
+  #define BRB_REG_INT_MASK_10_RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR                                               (0x1<<26) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR .
+  #define BRB_REG_INT_MASK_10_RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                         26
+  #define BRB_REG_INT_MASK_10_RC1_EOP_OUT_SYNC_FIFO_PUSH_ERROR                                               (0x1<<27) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC1_EOP_OUT_SYNC_FIFO_PUSH_ERROR .
+  #define BRB_REG_INT_MASK_10_RC1_EOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                         27
+  #define BRB_REG_INT_MASK_10_RC2_EOP_OUT_SYNC_FIFO_PUSH_ERROR_K2_E5                                         (0x1<<28) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC2_EOP_OUT_SYNC_FIFO_PUSH_ERROR .
+  #define BRB_REG_INT_MASK_10_RC2_EOP_OUT_SYNC_FIFO_PUSH_ERROR_K2_E5_SHIFT                                   28
+  #define BRB_REG_INT_MASK_10_RC3_EOP_OUT_SYNC_FIFO_PUSH_ERROR_K2_E5                                         (0x1<<29) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC3_EOP_OUT_SYNC_FIFO_PUSH_ERROR .
+  #define BRB_REG_INT_MASK_10_RC3_EOP_OUT_SYNC_FIFO_PUSH_ERROR_K2_E5_SHIFT                                   29
+#define BRB_REG_INT_STS_WR_10                                                                                0x3401bcUL //Access:WR   DataWidth:0x1e   // Multi Field Register.
+  #define BRB_REG_INT_STS_WR_10_RC_SOP_INP_SYNC_FIFO_PUSH_ERROR                                              (0x1<<1) // SOP input SYNC FIFO error (for BRB)
+  #define BRB_REG_INT_STS_WR_10_RC_SOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                        1
+  #define BRB_REG_INT_STS_WR_10_RC0_INP_SYNC_FIFO_PUSH_ERROR                                                 (0x1<<2) // Packet RC input SYNC FIFO error
+  #define BRB_REG_INT_STS_WR_10_RC0_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                           2
+  #define BRB_REG_INT_STS_WR_10_RC1_INP_SYNC_FIFO_PUSH_ERROR                                                 (0x1<<3) // Packet RC input SYNC FIFO error
+  #define BRB_REG_INT_STS_WR_10_RC1_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                           3
+  #define BRB_REG_INT_STS_WR_10_RC2_INP_SYNC_FIFO_PUSH_ERROR                                                 (0x1<<4) // Packet RC input SYNC FIFO error
+  #define BRB_REG_INT_STS_WR_10_RC2_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                           4
+  #define BRB_REG_INT_STS_WR_10_RC3_INP_SYNC_FIFO_PUSH_ERROR                                                 (0x1<<5) // Packet RC input SYNC FIFO error
+  #define BRB_REG_INT_STS_WR_10_RC3_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                           5
+  #define BRB_REG_INT_STS_WR_10_RC0_OUT_SYNC_FIFO_PUSH_ERROR                                                 (0x1<<12) // Packet RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_WR_10_RC0_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                           12
+  #define BRB_REG_INT_STS_WR_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR                                                 (0x1<<13) // Packet RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_WR_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                           13
+  #define BRB_REG_INT_STS_WR_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR                                                 (0x1<<14) // Packet RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_WR_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                           14
+  #define BRB_REG_INT_STS_WR_10_RC3_OUT_SYNC_FIFO_PUSH_ERROR                                                 (0x1<<15) // Packet RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_WR_10_RC3_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                           15
+  #define BRB_REG_INT_STS_WR_10_RC4_OUT_SYNC_FIFO_PUSH_ERROR                                                 (0x1<<16) // Packet RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_WR_10_RC4_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                           16
+  #define BRB_REG_INT_STS_WR_10_RC0_EOP_INP_SYNC_FIFO_PUSH_ERROR                                             (0x1<<22) // EOP RC input SYNC FIFO error
+  #define BRB_REG_INT_STS_WR_10_RC0_EOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                       22
+  #define BRB_REG_INT_STS_WR_10_RC1_EOP_INP_SYNC_FIFO_PUSH_ERROR                                             (0x1<<23) // EOP RC input SYNC FIFO error
+  #define BRB_REG_INT_STS_WR_10_RC1_EOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                       23
+  #define BRB_REG_INT_STS_WR_10_RC2_EOP_INP_SYNC_FIFO_PUSH_ERROR_K2_E5                                       (0x1<<24) // EOP RC input SYNC FIFO error
+  #define BRB_REG_INT_STS_WR_10_RC2_EOP_INP_SYNC_FIFO_PUSH_ERROR_K2_E5_SHIFT                                 24
+  #define BRB_REG_INT_STS_WR_10_RC3_EOP_INP_SYNC_FIFO_PUSH_ERROR_K2_E5                                       (0x1<<25) // EOP RC input SYNC FIFO error
+  #define BRB_REG_INT_STS_WR_10_RC3_EOP_INP_SYNC_FIFO_PUSH_ERROR_K2_E5_SHIFT                                 25
+  #define BRB_REG_INT_STS_WR_10_RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR                                             (0x1<<26) // EOP RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_WR_10_RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                       26
+  #define BRB_REG_INT_STS_WR_10_RC1_EOP_OUT_SYNC_FIFO_PUSH_ERROR                                             (0x1<<27) // EOP RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_WR_10_RC1_EOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                       27
+  #define BRB_REG_INT_STS_WR_10_RC2_EOP_OUT_SYNC_FIFO_PUSH_ERROR_K2_E5                                       (0x1<<28) // EOP RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_WR_10_RC2_EOP_OUT_SYNC_FIFO_PUSH_ERROR_K2_E5_SHIFT                                 28
+  #define BRB_REG_INT_STS_WR_10_RC3_EOP_OUT_SYNC_FIFO_PUSH_ERROR_K2_E5                                       (0x1<<29) // EOP RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_WR_10_RC3_EOP_OUT_SYNC_FIFO_PUSH_ERROR_K2_E5_SHIFT                                 29
+#define BRB_REG_INT_STS_CLR_10                                                                               0x3401c0UL //Access:RC   DataWidth:0x1e   // Multi Field Register.
+  #define BRB_REG_INT_STS_CLR_10_RC_SOP_INP_SYNC_FIFO_PUSH_ERROR                                             (0x1<<1) // SOP input SYNC FIFO error (for BRB)
+  #define BRB_REG_INT_STS_CLR_10_RC_SOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                       1
+  #define BRB_REG_INT_STS_CLR_10_RC0_INP_SYNC_FIFO_PUSH_ERROR                                                (0x1<<2) // Packet RC input SYNC FIFO error
+  #define BRB_REG_INT_STS_CLR_10_RC0_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                          2
+  #define BRB_REG_INT_STS_CLR_10_RC1_INP_SYNC_FIFO_PUSH_ERROR                                                (0x1<<3) // Packet RC input SYNC FIFO error
+  #define BRB_REG_INT_STS_CLR_10_RC1_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                          3
+  #define BRB_REG_INT_STS_CLR_10_RC2_INP_SYNC_FIFO_PUSH_ERROR                                                (0x1<<4) // Packet RC input SYNC FIFO error
+  #define BRB_REG_INT_STS_CLR_10_RC2_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                          4
+  #define BRB_REG_INT_STS_CLR_10_RC3_INP_SYNC_FIFO_PUSH_ERROR                                                (0x1<<5) // Packet RC input SYNC FIFO error
+  #define BRB_REG_INT_STS_CLR_10_RC3_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                          5
+  #define BRB_REG_INT_STS_CLR_10_RC0_OUT_SYNC_FIFO_PUSH_ERROR                                                (0x1<<12) // Packet RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_CLR_10_RC0_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                          12
+  #define BRB_REG_INT_STS_CLR_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR                                                (0x1<<13) // Packet RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_CLR_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                          13
+  #define BRB_REG_INT_STS_CLR_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR                                                (0x1<<14) // Packet RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_CLR_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                          14
+  #define BRB_REG_INT_STS_CLR_10_RC3_OUT_SYNC_FIFO_PUSH_ERROR                                                (0x1<<15) // Packet RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_CLR_10_RC3_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                          15
+  #define BRB_REG_INT_STS_CLR_10_RC4_OUT_SYNC_FIFO_PUSH_ERROR                                                (0x1<<16) // Packet RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_CLR_10_RC4_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                          16
+  #define BRB_REG_INT_STS_CLR_10_RC0_EOP_INP_SYNC_FIFO_PUSH_ERROR                                            (0x1<<22) // EOP RC input SYNC FIFO error
+  #define BRB_REG_INT_STS_CLR_10_RC0_EOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                      22
+  #define BRB_REG_INT_STS_CLR_10_RC1_EOP_INP_SYNC_FIFO_PUSH_ERROR                                            (0x1<<23) // EOP RC input SYNC FIFO error
+  #define BRB_REG_INT_STS_CLR_10_RC1_EOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                      23
+  #define BRB_REG_INT_STS_CLR_10_RC2_EOP_INP_SYNC_FIFO_PUSH_ERROR_K2_E5                                      (0x1<<24) // EOP RC input SYNC FIFO error
+  #define BRB_REG_INT_STS_CLR_10_RC2_EOP_INP_SYNC_FIFO_PUSH_ERROR_K2_E5_SHIFT                                24
+  #define BRB_REG_INT_STS_CLR_10_RC3_EOP_INP_SYNC_FIFO_PUSH_ERROR_K2_E5                                      (0x1<<25) // EOP RC input SYNC FIFO error
+  #define BRB_REG_INT_STS_CLR_10_RC3_EOP_INP_SYNC_FIFO_PUSH_ERROR_K2_E5_SHIFT                                25
+  #define BRB_REG_INT_STS_CLR_10_RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR                                            (0x1<<26) // EOP RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_CLR_10_RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                      26
+  #define BRB_REG_INT_STS_CLR_10_RC1_EOP_OUT_SYNC_FIFO_PUSH_ERROR                                            (0x1<<27) // EOP RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_CLR_10_RC1_EOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                      27
+  #define BRB_REG_INT_STS_CLR_10_RC2_EOP_OUT_SYNC_FIFO_PUSH_ERROR_K2_E5                                      (0x1<<28) // EOP RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_CLR_10_RC2_EOP_OUT_SYNC_FIFO_PUSH_ERROR_K2_E5_SHIFT                                28
+  #define BRB_REG_INT_STS_CLR_10_RC3_EOP_OUT_SYNC_FIFO_PUSH_ERROR_K2_E5                                      (0x1<<29) // EOP RC output SYNC FIFO error
+  #define BRB_REG_INT_STS_CLR_10_RC3_EOP_OUT_SYNC_FIFO_PUSH_ERROR_K2_E5_SHIFT                                29
+#define BRB_REG_INT_STS_11                                                                                   0x3401ccUL //Access:R    DataWidth:0x12   // Multi Field Register.
+  #define BRB_REG_INT_STS_11_RC2_EOP_ERROR                                                                   (0x1<<10) // Read EOP client 2 request FIFO error
+  #define BRB_REG_INT_STS_11_RC2_EOP_ERROR_SHIFT                                                             10
+  #define BRB_REG_INT_STS_11_RC3_EOP_ERROR                                                                   (0x1<<11) // Read EOP client 2 request FIFO error
+  #define BRB_REG_INT_STS_11_RC3_EOP_ERROR_SHIFT                                                             11
+  #define BRB_REG_INT_STS_11_MAC2_FC_CNT_ERROR                                                               (0x1<<12) // Free shared area calculation error for MAC port 2
+  #define BRB_REG_INT_STS_11_MAC2_FC_CNT_ERROR_SHIFT                                                         12
+  #define BRB_REG_INT_STS_11_MAC3_FC_CNT_ERROR                                                               (0x1<<13) // Free shared area calculation error for MAC port 3
+  #define BRB_REG_INT_STS_11_MAC3_FC_CNT_ERROR_SHIFT                                                         13
+  #define BRB_REG_INT_STS_11_WC4_EOP_FIFO_ERROR                                                              (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 4
+  #define BRB_REG_INT_STS_11_WC4_EOP_FIFO_ERROR_SHIFT                                                        14
+  #define BRB_REG_INT_STS_11_WC5_EOP_FIFO_ERROR                                                              (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 5
+  #define BRB_REG_INT_STS_11_WC5_EOP_FIFO_ERROR_SHIFT                                                        15
+  #define BRB_REG_INT_STS_11_WC6_EOP_FIFO_ERROR                                                              (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 6
+  #define BRB_REG_INT_STS_11_WC6_EOP_FIFO_ERROR_SHIFT                                                        16
+  #define BRB_REG_INT_STS_11_WC7_EOP_FIFO_ERROR                                                              (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 7
+  #define BRB_REG_INT_STS_11_WC7_EOP_FIFO_ERROR_SHIFT                                                        17
+#define BRB_REG_INT_MASK_11                                                                                  0x3401d0UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define BRB_REG_INT_MASK_11_RC2_EOP_ERROR                                                                  (0x1<<10) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_11.RC2_EOP_ERROR .
+  #define BRB_REG_INT_MASK_11_RC2_EOP_ERROR_SHIFT                                                            10
+  #define BRB_REG_INT_MASK_11_RC3_EOP_ERROR                                                                  (0x1<<11) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_11.RC3_EOP_ERROR .
+  #define BRB_REG_INT_MASK_11_RC3_EOP_ERROR_SHIFT                                                            11
+  #define BRB_REG_INT_MASK_11_MAC2_FC_CNT_ERROR                                                              (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_11.MAC2_FC_CNT_ERROR .
+  #define BRB_REG_INT_MASK_11_MAC2_FC_CNT_ERROR_SHIFT                                                        12
+  #define BRB_REG_INT_MASK_11_MAC3_FC_CNT_ERROR                                                              (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_11.MAC3_FC_CNT_ERROR .
+  #define BRB_REG_INT_MASK_11_MAC3_FC_CNT_ERROR_SHIFT                                                        13
+  #define BRB_REG_INT_MASK_11_WC4_EOP_FIFO_ERROR                                                             (0x1<<14) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_11.WC4_EOP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_11_WC4_EOP_FIFO_ERROR_SHIFT                                                       14
+  #define BRB_REG_INT_MASK_11_WC5_EOP_FIFO_ERROR                                                             (0x1<<15) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_11.WC5_EOP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_11_WC5_EOP_FIFO_ERROR_SHIFT                                                       15
+  #define BRB_REG_INT_MASK_11_WC6_EOP_FIFO_ERROR                                                             (0x1<<16) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_11.WC6_EOP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_11_WC6_EOP_FIFO_ERROR_SHIFT                                                       16
+  #define BRB_REG_INT_MASK_11_WC7_EOP_FIFO_ERROR                                                             (0x1<<17) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_11.WC7_EOP_FIFO_ERROR .
+  #define BRB_REG_INT_MASK_11_WC7_EOP_FIFO_ERROR_SHIFT                                                       17
+#define BRB_REG_INT_STS_WR_11                                                                                0x3401d4UL //Access:WR   DataWidth:0x12   // Multi Field Register.
+  #define BRB_REG_INT_STS_WR_11_RC2_EOP_ERROR                                                                (0x1<<10) // Read EOP client 2 request FIFO error
+  #define BRB_REG_INT_STS_WR_11_RC2_EOP_ERROR_SHIFT                                                          10
+  #define BRB_REG_INT_STS_WR_11_RC3_EOP_ERROR                                                                (0x1<<11) // Read EOP client 2 request FIFO error
+  #define BRB_REG_INT_STS_WR_11_RC3_EOP_ERROR_SHIFT                                                          11
+  #define BRB_REG_INT_STS_WR_11_MAC2_FC_CNT_ERROR                                                            (0x1<<12) // Free shared area calculation error for MAC port 2
+  #define BRB_REG_INT_STS_WR_11_MAC2_FC_CNT_ERROR_SHIFT                                                      12
+  #define BRB_REG_INT_STS_WR_11_MAC3_FC_CNT_ERROR                                                            (0x1<<13) // Free shared area calculation error for MAC port 3
+  #define BRB_REG_INT_STS_WR_11_MAC3_FC_CNT_ERROR_SHIFT                                                      13
+  #define BRB_REG_INT_STS_WR_11_WC4_EOP_FIFO_ERROR                                                           (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 4
+  #define BRB_REG_INT_STS_WR_11_WC4_EOP_FIFO_ERROR_SHIFT                                                     14
+  #define BRB_REG_INT_STS_WR_11_WC5_EOP_FIFO_ERROR                                                           (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 5
+  #define BRB_REG_INT_STS_WR_11_WC5_EOP_FIFO_ERROR_SHIFT                                                     15
+  #define BRB_REG_INT_STS_WR_11_WC6_EOP_FIFO_ERROR                                                           (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 6
+  #define BRB_REG_INT_STS_WR_11_WC6_EOP_FIFO_ERROR_SHIFT                                                     16
+  #define BRB_REG_INT_STS_WR_11_WC7_EOP_FIFO_ERROR                                                           (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 7
+  #define BRB_REG_INT_STS_WR_11_WC7_EOP_FIFO_ERROR_SHIFT                                                     17
+#define BRB_REG_INT_STS_CLR_11                                                                               0x3401d8UL //Access:RC   DataWidth:0x12   // Multi Field Register.
+  #define BRB_REG_INT_STS_CLR_11_RC2_EOP_ERROR                                                               (0x1<<10) // Read EOP client 2 request FIFO error
+  #define BRB_REG_INT_STS_CLR_11_RC2_EOP_ERROR_SHIFT                                                         10
+  #define BRB_REG_INT_STS_CLR_11_RC3_EOP_ERROR                                                               (0x1<<11) // Read EOP client 2 request FIFO error
+  #define BRB_REG_INT_STS_CLR_11_RC3_EOP_ERROR_SHIFT                                                         11
+  #define BRB_REG_INT_STS_CLR_11_MAC2_FC_CNT_ERROR                                                           (0x1<<12) // Free shared area calculation error for MAC port 2
+  #define BRB_REG_INT_STS_CLR_11_MAC2_FC_CNT_ERROR_SHIFT                                                     12
+  #define BRB_REG_INT_STS_CLR_11_MAC3_FC_CNT_ERROR                                                           (0x1<<13) // Free shared area calculation error for MAC port 3
+  #define BRB_REG_INT_STS_CLR_11_MAC3_FC_CNT_ERROR_SHIFT                                                     13
+  #define BRB_REG_INT_STS_CLR_11_WC4_EOP_FIFO_ERROR                                                          (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 4
+  #define BRB_REG_INT_STS_CLR_11_WC4_EOP_FIFO_ERROR_SHIFT                                                    14
+  #define BRB_REG_INT_STS_CLR_11_WC5_EOP_FIFO_ERROR                                                          (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 5
+  #define BRB_REG_INT_STS_CLR_11_WC5_EOP_FIFO_ERROR_SHIFT                                                    15
+  #define BRB_REG_INT_STS_CLR_11_WC6_EOP_FIFO_ERROR                                                          (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 6
+  #define BRB_REG_INT_STS_CLR_11_WC6_EOP_FIFO_ERROR_SHIFT                                                    16
+  #define BRB_REG_INT_STS_CLR_11_WC7_EOP_FIFO_ERROR                                                          (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 7
+  #define BRB_REG_INT_STS_CLR_11_WC7_EOP_FIFO_ERROR_SHIFT                                                    17
+#define BRB_REG_PRTY_MASK                                                                                    0x3401e0UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define BRB_REG_PRTY_MASK_LL_BANK0_MEM_PRTY                                                                (0x1<<0) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS.LL_BANK0_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_LL_BANK0_MEM_PRTY_SHIFT                                                          0
+  #define BRB_REG_PRTY_MASK_LL_BANK1_MEM_PRTY                                                                (0x1<<1) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS.LL_BANK1_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_LL_BANK1_MEM_PRTY_SHIFT                                                          1
+  #define BRB_REG_PRTY_MASK_LL_BANK2_MEM_PRTY                                                                (0x1<<2) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS.LL_BANK2_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_LL_BANK2_MEM_PRTY_SHIFT                                                          2
+  #define BRB_REG_PRTY_MASK_LL_BANK3_MEM_PRTY                                                                (0x1<<3) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS.LL_BANK3_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_LL_BANK3_MEM_PRTY_SHIFT                                                          3
+  #define BRB_REG_PRTY_MASK_DATAPATH_REGISTERS                                                               (0x1<<4) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS.DATAPATH_REGISTERS .
+  #define BRB_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                                         4
+#define BRB_REG_PRTY_MASK_H_0_BB_K2                                                                          0x340404UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define BRB_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_K2                                                    (0x1<<0) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
+  #define BRB_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_K2_SHIFT                                              0
+  #define BRB_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT_BB_K2                                                    (0x1<<1) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM008_I_ECC_RF_INT .
+  #define BRB_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT_BB_K2_SHIFT                                              1
+  #define BRB_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_BB_K2                                                    (0x1<<2) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM009_I_ECC_RF_INT .
+  #define BRB_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_BB_K2_SHIFT                                              2
+  #define BRB_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT_BB_K2                                                    (0x1<<3) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM010_I_ECC_RF_INT .
+  #define BRB_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT_BB_K2_SHIFT                                              3
+  #define BRB_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT_BB_K2                                                    (0x1<<4) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM011_I_ECC_RF_INT .
+  #define BRB_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT_BB_K2_SHIFT                                              4
+  #define BRB_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_BB_K2                                                    (0x1<<5) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM012_I_ECC_RF_INT .
+  #define BRB_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_BB_K2_SHIFT                                              5
+  #define BRB_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT_BB_K2                                                    (0x1<<6) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM013_I_ECC_RF_INT .
+  #define BRB_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT_BB_K2_SHIFT                                              6
+  #define BRB_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_BB_K2                                                    (0x1<<7) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM014_I_ECC_RF_INT .
+  #define BRB_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_BB_K2_SHIFT                                              7
+  #define BRB_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_BB_K2                                                    (0x1<<8) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM015_I_ECC_RF_INT .
+  #define BRB_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_BB_K2_SHIFT                                              8
+  #define BRB_REG_PRTY_MASK_H_0_MEM016_I_ECC_RF_INT_BB_K2                                                    (0x1<<9) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM016_I_ECC_RF_INT .
+  #define BRB_REG_PRTY_MASK_H_0_MEM016_I_ECC_RF_INT_BB_K2_SHIFT                                              9
+  #define BRB_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_BB_K2                                                    (0x1<<10) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT .
+  #define BRB_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_BB_K2_SHIFT                                              10
+  #define BRB_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_BB_K2                                                    (0x1<<11) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
+  #define BRB_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_BB_K2_SHIFT                                              11
+  #define BRB_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_BB_K2                                                    (0x1<<12) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT .
+  #define BRB_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_BB_K2_SHIFT                                              12
+  #define BRB_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_BB_K2                                                    (0x1<<13) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT .
+  #define BRB_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_BB_K2_SHIFT                                              13
+  #define BRB_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_BB_K2                                                    (0x1<<14) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM006_I_ECC_RF_INT .
+  #define BRB_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_BB_K2_SHIFT                                              14
+  #define BRB_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT_BB_K2                                                    (0x1<<15) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM007_I_ECC_RF_INT .
+  #define BRB_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT_BB_K2_SHIFT                                              15
+  #define BRB_REG_PRTY_MASK_H_0_MEM070_I_MEM_PRTY_K2                                                         (0x1<<16) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM070_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM070_I_MEM_PRTY_K2_SHIFT                                                   16
+  #define BRB_REG_PRTY_MASK_H_0_MEM069_I_MEM_PRTY_K2                                                         (0x1<<17) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM069_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM069_I_MEM_PRTY_K2_SHIFT                                                   17
+  #define BRB_REG_PRTY_MASK_H_0_MEM053_I_MEM_PRTY_BB                                                         (0x1<<17) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM053_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM053_I_MEM_PRTY_BB_SHIFT                                                   17
+  #define BRB_REG_PRTY_MASK_H_0_MEM053_I_MEM_PRTY_K2                                                         (0x1<<18) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM053_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM053_I_MEM_PRTY_K2_SHIFT                                                   18
+  #define BRB_REG_PRTY_MASK_H_0_MEM054_I_MEM_PRTY_BB                                                         (0x1<<16) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM054_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM054_I_MEM_PRTY_BB_SHIFT                                                   16
+  #define BRB_REG_PRTY_MASK_H_0_MEM054_I_MEM_PRTY_K2                                                         (0x1<<19) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM054_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM054_I_MEM_PRTY_K2_SHIFT                                                   19
+  #define BRB_REG_PRTY_MASK_H_0_MEM055_I_MEM_PRTY_K2                                                         (0x1<<20) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM055_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM055_I_MEM_PRTY_K2_SHIFT                                                   20
+  #define BRB_REG_PRTY_MASK_H_0_MEM056_I_MEM_PRTY_K2                                                         (0x1<<21) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM056_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM056_I_MEM_PRTY_K2_SHIFT                                                   21
+  #define BRB_REG_PRTY_MASK_H_0_MEM057_I_MEM_PRTY_K2                                                         (0x1<<22) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM057_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM057_I_MEM_PRTY_K2_SHIFT                                                   22
+  #define BRB_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY_K2                                                         (0x1<<23) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM058_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY_K2_SHIFT                                                   23
+  #define BRB_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_K2                                                         (0x1<<24) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM059_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_K2_SHIFT                                                   24
+  #define BRB_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_K2                                                         (0x1<<25) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM060_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_K2_SHIFT                                                   25
+  #define BRB_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_K2                                                         (0x1<<26) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM061_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_K2_SHIFT                                                   26
+  #define BRB_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY_K2                                                         (0x1<<27) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM062_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY_K2_SHIFT                                                   27
+  #define BRB_REG_PRTY_MASK_H_0_MEM063_I_MEM_PRTY_K2                                                         (0x1<<28) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM063_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM063_I_MEM_PRTY_K2_SHIFT                                                   28
+  #define BRB_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY_K2                                                         (0x1<<29) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM064_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY_K2_SHIFT                                                   29
+  #define BRB_REG_PRTY_MASK_H_0_MEM065_I_MEM_PRTY_K2                                                         (0x1<<30) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM065_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM065_I_MEM_PRTY_K2_SHIFT                                                   30
+  #define BRB_REG_PRTY_MASK_H_0_MEM045_I_MEM_PRTY_BB                                                         (0x1<<18) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM045_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM045_I_MEM_PRTY_BB_SHIFT                                                   18
+  #define BRB_REG_PRTY_MASK_H_0_MEM046_I_MEM_PRTY_BB                                                         (0x1<<19) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM046_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM046_I_MEM_PRTY_BB_SHIFT                                                   19
+  #define BRB_REG_PRTY_MASK_H_0_MEM047_I_MEM_PRTY_BB                                                         (0x1<<20) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM047_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM047_I_MEM_PRTY_BB_SHIFT                                                   20
+  #define BRB_REG_PRTY_MASK_H_0_MEM048_I_MEM_PRTY_BB                                                         (0x1<<21) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM048_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM048_I_MEM_PRTY_BB_SHIFT                                                   21
+  #define BRB_REG_PRTY_MASK_H_0_MEM049_I_MEM_PRTY_BB                                                         (0x1<<22) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM049_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM049_I_MEM_PRTY_BB_SHIFT                                                   22
+  #define BRB_REG_PRTY_MASK_H_0_MEM050_I_MEM_PRTY_BB                                                         (0x1<<23) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM050_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM050_I_MEM_PRTY_BB_SHIFT                                                   23
+  #define BRB_REG_PRTY_MASK_H_0_MEM051_I_MEM_PRTY_BB                                                         (0x1<<24) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM051_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM051_I_MEM_PRTY_BB_SHIFT                                                   24
+  #define BRB_REG_PRTY_MASK_H_0_MEM052_I_MEM_PRTY_BB                                                         (0x1<<25) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM052_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM052_I_MEM_PRTY_BB_SHIFT                                                   25
+  #define BRB_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY_BB                                                         (0x1<<26) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM041_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY_BB_SHIFT                                                   26
+  #define BRB_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY_BB                                                         (0x1<<27) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM042_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY_BB_SHIFT                                                   27
+  #define BRB_REG_PRTY_MASK_H_0_MEM043_I_MEM_PRTY_BB                                                         (0x1<<28) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM043_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM043_I_MEM_PRTY_BB_SHIFT                                                   28
+  #define BRB_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY_BB                                                         (0x1<<29) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM044_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY_BB_SHIFT                                                   29
+  #define BRB_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_BB                                                         (0x1<<30) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM040_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_BB_SHIFT                                                   30
+#define BRB_REG_PRTY_MASK_H_1_BB_K2                                                                          0x340414UL //Access:RW   DataWidth:0x1e   // Multi Field Register.
+  #define BRB_REG_PRTY_MASK_H_1_MEM066_I_MEM_PRTY_K2                                                         (0x1<<0) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM066_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM066_I_MEM_PRTY_K2_SHIFT                                                   0
+  #define BRB_REG_PRTY_MASK_H_1_MEM067_I_MEM_PRTY_K2                                                         (0x1<<1) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM067_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM067_I_MEM_PRTY_K2_SHIFT                                                   1
+  #define BRB_REG_PRTY_MASK_H_1_MEM068_I_MEM_PRTY_K2                                                         (0x1<<2) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM068_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM068_I_MEM_PRTY_K2_SHIFT                                                   2
+  #define BRB_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY_K2                                                         (0x1<<3) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM045_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY_K2_SHIFT                                                   3
+  #define BRB_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY_K2                                                         (0x1<<4) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM046_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY_K2_SHIFT                                                   4
+  #define BRB_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_K2                                                         (0x1<<5) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM047_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_K2_SHIFT                                                   5
+  #define BRB_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_K2                                                         (0x1<<6) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM048_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_K2_SHIFT                                                   6
+  #define BRB_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_K2                                                         (0x1<<7) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM049_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_K2_SHIFT                                                   7
+  #define BRB_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_K2                                                         (0x1<<8) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_K2_SHIFT                                                   8
+  #define BRB_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_K2                                                         (0x1<<9) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM051_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_K2_SHIFT                                                   9
+  #define BRB_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_K2                                                         (0x1<<10) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_K2_SHIFT                                                   10
+  #define BRB_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_K2                                                         (0x1<<11) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM044_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_K2_SHIFT                                                   11
+  #define BRB_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY_BB                                                         (0x1<<6) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM030_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY_BB_SHIFT                                                   6
+  #define BRB_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY_K2                                                         (0x1<<12) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM030_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY_K2_SHIFT                                                   12
+  #define BRB_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_BB                                                         (0x1<<7) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM031_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_BB_SHIFT                                                   7
+  #define BRB_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_K2                                                         (0x1<<13) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM031_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_K2_SHIFT                                                   13
+  #define BRB_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_BB                                                         (0x1<<8) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM032_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_BB_SHIFT                                                   8
+  #define BRB_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_K2                                                         (0x1<<14) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM032_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_K2_SHIFT                                                   14
+  #define BRB_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_BB                                                         (0x1<<4) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM033_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_BB_SHIFT                                                   4
+  #define BRB_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_K2                                                         (0x1<<15) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM033_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_K2_SHIFT                                                   15
+  #define BRB_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_K2                                                         (0x1<<16) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM037_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_K2_SHIFT                                                   16
+  #define BRB_REG_PRTY_MASK_H_1_MEM038_I_MEM_PRTY_K2                                                         (0x1<<17) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM038_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM038_I_MEM_PRTY_K2_SHIFT                                                   17
+  #define BRB_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_BB                                                         (0x1<<5) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM034_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_BB_SHIFT                                                   5
+  #define BRB_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_K2                                                         (0x1<<18) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM034_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_K2_SHIFT                                                   18
+  #define BRB_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_K2                                                         (0x1<<19) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM035_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_K2_SHIFT                                                   19
+  #define BRB_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_K2                                                         (0x1<<20) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_K2_SHIFT                                                   20
+  #define BRB_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_BB                                                         (0x1<<9) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_BB_SHIFT                                                   9
+  #define BRB_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_K2                                                         (0x1<<21) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_K2_SHIFT                                                   21
+  #define BRB_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_BB                                                         (0x1<<10) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM018_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_BB_SHIFT                                                   10
+  #define BRB_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_K2                                                         (0x1<<22) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM018_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_K2_SHIFT                                                   22
+  #define BRB_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_BB                                                         (0x1<<11) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM019_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_BB_SHIFT                                                   11
+  #define BRB_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_K2                                                         (0x1<<23) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM019_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_K2_SHIFT                                                   23
+  #define BRB_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_BB                                                         (0x1<<12) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM020_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_BB_SHIFT                                                   12
+  #define BRB_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_K2                                                         (0x1<<24) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM020_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_K2_SHIFT                                                   24
+  #define BRB_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_K2                                                         (0x1<<25) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM021_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_K2_SHIFT                                                   25
+  #define BRB_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_K2                                                         (0x1<<26) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM022_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_K2_SHIFT                                                   26
+  #define BRB_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY_K2                                                         (0x1<<27) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM023_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY_K2_SHIFT                                                   27
+  #define BRB_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_K2                                                         (0x1<<28) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM024_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_K2_SHIFT                                                   28
+  #define BRB_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_BB                                                         (0x1<<3) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM029_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_BB_SHIFT                                                   3
+  #define BRB_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_K2                                                         (0x1<<29) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM029_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_K2_SHIFT                                                   29
+  #define BRB_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_BB                                                         (0x1<<0) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM026_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_BB_SHIFT                                                   0
+  #define BRB_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_BB                                                         (0x1<<1) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM027_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_BB_SHIFT                                                   1
+  #define BRB_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_BB                                                         (0x1<<2) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM028_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_BB_SHIFT                                                   2
+  #define BRB_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_BB                                                         (0x1<<13) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM025_I_MEM_PRTY .
+  #define BRB_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_BB_SHIFT                                                   13
+#define BRB_REG_MEM_ECC_ENABLE_0_BB                                                                          0x340460UL //Access:RW   DataWidth:0x10   // Multi Field Register.
+#define BRB_REG_MEM_ECC_ENABLE_0_K2                                                                          0x340420UL //Access:RW   DataWidth:0x10   // Multi Field Register.
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_BB_K2                                                     (0x1<<0) // Enable ECC for memory ecc instance brb.BB_BANK_K2_GEN_FOR[0].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_BB_K2_SHIFT                                               0
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_EN_BB_K2                                                     (0x1<<1) // Enable ECC for memory ecc instance brb.BB_BANK_K2_GEN_FOR[1].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_EN_BB_K2_SHIFT                                               1
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_EN_BB_K2                                                     (0x1<<2) // Enable ECC for memory ecc instance brb.BB_BANK_K2_GEN_FOR[2].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_EN_BB_K2_SHIFT                                               2
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_EN_BB_K2                                                     (0x1<<3) // Enable ECC for memory ecc instance brb.BB_BANK_K2_GEN_FOR[3].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_EN_BB_K2_SHIFT                                               3
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_EN_BB_K2                                                     (0x1<<4) // Enable ECC for memory ecc instance brb.BB_BANK_K2_GEN_FOR[4].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_EN_BB_K2_SHIFT                                               4
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN_BB_K2                                                     (0x1<<5) // Enable ECC for memory ecc instance brb.BB_BANK_K2_GEN_FOR[5].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN_BB_K2_SHIFT                                               5
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM013_I_ECC_EN_BB_K2                                                     (0x1<<6) // Enable ECC for memory ecc instance brb.BB_BANK_K2_GEN_FOR[6].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM013_I_ECC_EN_BB_K2_SHIFT                                               6
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN_BB_K2                                                     (0x1<<7) // Enable ECC for memory ecc instance brb.BB_BANK_K2_GEN_FOR[7].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN_BB_K2_SHIFT                                               7
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN_BB_K2                                                     (0x1<<8) // Enable ECC for memory ecc instance brb.BB_BANK_K2_GEN_FOR[8].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN_BB_K2_SHIFT                                               8
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_EN_BB_K2                                                     (0x1<<9) // Enable ECC for memory ecc instance brb.BB_BANK_K2_GEN_FOR[9].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_EN_BB_K2_SHIFT                                               9
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN_BB_K2                                                     (0x1<<10) // Enable ECC for memory ecc instance brb.BB_BANK_K2_GEN_FOR[10].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN_BB_K2_SHIFT                                               10
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_BB_K2                                                     (0x1<<11) // Enable ECC for memory ecc instance brb.BB_BANK_K2_GEN_FOR[11].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_BB_K2_SHIFT                                               11
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_BB_K2                                                     (0x1<<12) // Enable ECC for memory ecc instance brb.BB_BANK_K2_GEN_FOR[12].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_BB_K2_SHIFT                                               12
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_BB_K2                                                     (0x1<<13) // Enable ECC for memory ecc instance brb.BB_BANK_K2_GEN_FOR[13].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_BB_K2_SHIFT                                               13
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN_BB_K2                                                     (0x1<<14) // Enable ECC for memory ecc instance brb.BB_BANK_K2_GEN_FOR[14].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN_BB_K2_SHIFT                                               14
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_EN_BB_K2                                                     (0x1<<15) // Enable ECC for memory ecc instance brb.BB_BANK_K2_GEN_FOR[15].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_EN_BB_K2_SHIFT                                               15
+#define BRB_REG_MEM001_RF_ECC_ERROR_CONNECT_BB                                                               0x340420UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: brb.BB_BANK_BB_GEN_FOR[0].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BRB_REG_MEM_ECC_PARITY_ONLY_0_BB                                                                     0x340464UL //Access:RW   DataWidth:0x10   // Multi Field Register.
+#define BRB_REG_MEM_ECC_PARITY_ONLY_0_K2                                                                     0x340424UL //Access:RW   DataWidth:0x10   // Multi Field Register.
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_BB_K2                                              (0x1<<0) // Set parity only for memory ecc instance brb.BB_BANK_K2_GEN_FOR[0].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_BB_K2_SHIFT                                        0
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_PRTY_BB_K2                                              (0x1<<1) // Set parity only for memory ecc instance brb.BB_BANK_K2_GEN_FOR[1].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_PRTY_BB_K2_SHIFT                                        1
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_PRTY_BB_K2                                              (0x1<<2) // Set parity only for memory ecc instance brb.BB_BANK_K2_GEN_FOR[2].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_PRTY_BB_K2_SHIFT                                        2
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_PRTY_BB_K2                                              (0x1<<3) // Set parity only for memory ecc instance brb.BB_BANK_K2_GEN_FOR[3].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_PRTY_BB_K2_SHIFT                                        3
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_PRTY_BB_K2                                              (0x1<<4) // Set parity only for memory ecc instance brb.BB_BANK_K2_GEN_FOR[4].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_PRTY_BB_K2_SHIFT                                        4
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY_BB_K2                                              (0x1<<5) // Set parity only for memory ecc instance brb.BB_BANK_K2_GEN_FOR[5].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY_BB_K2_SHIFT                                        5
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM013_I_ECC_PRTY_BB_K2                                              (0x1<<6) // Set parity only for memory ecc instance brb.BB_BANK_K2_GEN_FOR[6].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM013_I_ECC_PRTY_BB_K2_SHIFT                                        6
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY_BB_K2                                              (0x1<<7) // Set parity only for memory ecc instance brb.BB_BANK_K2_GEN_FOR[7].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY_BB_K2_SHIFT                                        7
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY_BB_K2                                              (0x1<<8) // Set parity only for memory ecc instance brb.BB_BANK_K2_GEN_FOR[8].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY_BB_K2_SHIFT                                        8
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_PRTY_BB_K2                                              (0x1<<9) // Set parity only for memory ecc instance brb.BB_BANK_K2_GEN_FOR[9].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_PRTY_BB_K2_SHIFT                                        9
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY_BB_K2                                              (0x1<<10) // Set parity only for memory ecc instance brb.BB_BANK_K2_GEN_FOR[10].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY_BB_K2_SHIFT                                        10
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_BB_K2                                              (0x1<<11) // Set parity only for memory ecc instance brb.BB_BANK_K2_GEN_FOR[11].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_BB_K2_SHIFT                                        11
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_BB_K2                                              (0x1<<12) // Set parity only for memory ecc instance brb.BB_BANK_K2_GEN_FOR[12].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_BB_K2_SHIFT                                        12
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_BB_K2                                              (0x1<<13) // Set parity only for memory ecc instance brb.BB_BANK_K2_GEN_FOR[13].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_BB_K2_SHIFT                                        13
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY_BB_K2                                              (0x1<<14) // Set parity only for memory ecc instance brb.BB_BANK_K2_GEN_FOR[14].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY_BB_K2_SHIFT                                        14
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_PRTY_BB_K2                                              (0x1<<15) // Set parity only for memory ecc instance brb.BB_BANK_K2_GEN_FOR[15].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_PRTY_BB_K2_SHIFT                                        15
+#define BRB_REG_MEM008_RF_ECC_ERROR_CONNECT_BB                                                               0x340424UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: brb.BB_BANK_BB_GEN_FOR[1].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_BB                                                                 0x340468UL //Access:RC   DataWidth:0x10   // Multi Field Register.
+#define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_K2                                                                 0x340428UL //Access:RC   DataWidth:0x10   // Multi Field Register.
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_BB_K2                                       (0x1<<0) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_K2_GEN_FOR[0].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_BB_K2_SHIFT                                 0
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_CORRECT_BB_K2                                       (0x1<<1) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_K2_GEN_FOR[1].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_CORRECT_BB_K2_SHIFT                                 1
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_CORRECT_BB_K2                                       (0x1<<2) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_K2_GEN_FOR[2].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_CORRECT_BB_K2_SHIFT                                 2
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_CORRECT_BB_K2                                       (0x1<<3) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_K2_GEN_FOR[3].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_CORRECT_BB_K2_SHIFT                                 3
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_CORRECT_BB_K2                                       (0x1<<4) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_K2_GEN_FOR[4].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_CORRECT_BB_K2_SHIFT                                 4
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT_BB_K2                                       (0x1<<5) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_K2_GEN_FOR[5].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT_BB_K2_SHIFT                                 5
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM013_I_ECC_CORRECT_BB_K2                                       (0x1<<6) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_K2_GEN_FOR[6].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM013_I_ECC_CORRECT_BB_K2_SHIFT                                 6
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT_BB_K2                                       (0x1<<7) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_K2_GEN_FOR[7].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT_BB_K2_SHIFT                                 7
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT_BB_K2                                       (0x1<<8) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_K2_GEN_FOR[8].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT_BB_K2_SHIFT                                 8
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_CORRECT_BB_K2                                       (0x1<<9) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_K2_GEN_FOR[9].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_CORRECT_BB_K2_SHIFT                                 9
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT_BB_K2                                       (0x1<<10) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_K2_GEN_FOR[10].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT_BB_K2_SHIFT                                 10
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_BB_K2                                       (0x1<<11) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_K2_GEN_FOR[11].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_BB_K2_SHIFT                                 11
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_BB_K2                                       (0x1<<12) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_K2_GEN_FOR[12].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_BB_K2_SHIFT                                 12
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_BB_K2                                       (0x1<<13) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_K2_GEN_FOR[13].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_BB_K2_SHIFT                                 13
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT_BB_K2                                       (0x1<<14) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_K2_GEN_FOR[14].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT_BB_K2_SHIFT                                 14
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_CORRECT_BB_K2                                       (0x1<<15) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_K2_GEN_FOR[15].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
+  #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_CORRECT_BB_K2_SHIFT                                 15
+#define BRB_REG_MEM009_RF_ECC_ERROR_CONNECT_BB                                                               0x340428UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: brb.BB_BANK_BB_GEN_FOR[2].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BRB_REG_MEM_ECC_EVENTS_BB                                                                            0x34046cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define BRB_REG_MEM_ECC_EVENTS_K2                                                                            0x34042cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define BRB_REG_MEM010_RF_ECC_ERROR_CONNECT_BB                                                               0x34042cUL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: brb.BB_BANK_BB_GEN_FOR[3].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BRB_REG_MEM011_RF_ECC_ERROR_CONNECT_BB                                                               0x340430UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: brb.BB_BANK_BB_GEN_FOR[4].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BRB_REG_MEM012_RF_ECC_ERROR_CONNECT_BB                                                               0x340434UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: brb.BB_BANK_BB_GEN_FOR[5].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BRB_REG_MEM013_RF_ECC_ERROR_CONNECT_BB                                                               0x340438UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: brb.BB_BANK_BB_GEN_FOR[6].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BRB_REG_MEM014_RF_ECC_ERROR_CONNECT_BB                                                               0x34043cUL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: brb.BB_BANK_BB_GEN_FOR[7].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BRB_REG_MEM015_RF_ECC_ERROR_CONNECT_BB                                                               0x340440UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: brb.BB_BANK_BB_GEN_FOR[8].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BRB_REG_MEM016_RF_ECC_ERROR_CONNECT_BB                                                               0x340444UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: brb.BB_BANK_BB_GEN_FOR[9].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BRB_REG_MEM002_RF_ECC_ERROR_CONNECT_BB                                                               0x340448UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: brb.BB_BANK_BB_GEN_FOR[10].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BRB_REG_MEM003_RF_ECC_ERROR_CONNECT_BB                                                               0x34044cUL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: brb.BB_BANK_BB_GEN_FOR[11].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BRB_REG_MEM004_RF_ECC_ERROR_CONNECT_BB                                                               0x340450UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: brb.BB_BANK_BB_GEN_FOR[12].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BRB_REG_MEM005_RF_ECC_ERROR_CONNECT_BB                                                               0x340454UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: brb.BB_BANK_BB_GEN_FOR[13].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BRB_REG_MEM006_RF_ECC_ERROR_CONNECT_BB                                                               0x340458UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: brb.BB_BANK_BB_GEN_FOR[14].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BRB_REG_MEM007_RF_ECC_ERROR_CONNECT_BB                                                               0x34045cUL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: brb.BB_BANK_BB_GEN_FOR[15].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BRB_REG_BIG_RAM_ADDRESS                                                                              0x340800UL //Access:RW   DataWidth:0xd    // Debug register. It contains address to Big RAM for RBC operations. Value of this register will be incremented by one it was done write access to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_WDTH/13/g in Data Width.
+#define BRB_REG_HEADER_SIZE                                                                                  0x340804UL //Access:RW   DataWidth:0xa    // Number of valid bytes in header in 16-bytes resolution. After this number of bytes will input to BRTB will be sent packet available indication. (reset value of 17 suits to 282 bytes of header)::s/HDR_SIZE_RST/17/g in Reset Value.
+#define BRB_REG_FREE_LIST_HEAD                                                                               0x340810UL //Access:RW   DataWidth:0xe    // Head pointer to each one of 4 free lists::s/BLK_WDTH/13/g in Data Width.
+#define BRB_REG_FREE_LIST_HEAD_SIZE                                                                          4
+#define BRB_REG_FREE_LIST_TAIL                                                                               0x340820UL //Access:RW   DataWidth:0xe    // Tail pointer of each one of 4 free lists::s/BLK_WDTH/13/g in Data Width.
+#define BRB_REG_FREE_LIST_TAIL_SIZE                                                                          4
+#define BRB_REG_FREE_LIST_SIZE                                                                               0x340830UL //Access:RW   DataWidth:0xe    // Number of free blocks in each one of 4 free lists::s/BLK_WDTH/13/g in Data Width.
+#define BRB_REG_FREE_LIST_SIZE_SIZE                                                                          4
+#define BRB_REG_MAX_RELEASES                                                                                 0x340840UL //Access:RW   DataWidth:0xa    // Number of packet copies that should be released before whole packet is released::s/MAX_RLS_WDTH/10/g in Data Width::s/MAX_RLS_RST/512/g in Reset Value::s/MAX_RLS_REQ/required/g in Required::s/MAX_RLS_REQ/required/g in Software init.
+#define BRB_REG_STOP_ON_LEN_ERR                                                                              0x340844UL //Access:RW   DataWidth:0x5    // There is bit for each PACKET read client. When bit is set then read client will not execute more requests till reset in a case of length error other way it will continue to work as usual.::s/STOP_LEN_ERR_RST/7/g in Reset Value::s/PKT_RC_NUM/5/g in Data Width.
+#define BRB_REG_SHARED_HR_AREA                                                                               0x340880UL //Access:RW   DataWidth:0xe    // The total number available blocks for each MAC port that includes shared and headroom areas. This register should be equal to total_mac_size - SUM(tc_guarantied) Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::s/MAX_SHARE_GRP_WDTH/1/g in Address Width::s/SHARED_HR_RST/2112/g in Reset Value::/PAUSE_EN/d in Existance.
+#define BRB_REG_SHARED_HR_AREA_SIZE_BB                                                                       2
+#define BRB_REG_SHARED_HR_AREA_SIZE_K2_E5                                                                    4
+#define BRB_REG_TOTAL_MAC_SIZE                                                                               0x3408c0UL //Access:RW   DataWidth:0xe    // The total number available blocks for each MAC port that includes guaranteed and shared and headroom areas. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::s/MAX_SHARE_GRP_WDTH/1/g in Address Width::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance.
+#define BRB_REG_TOTAL_MAC_SIZE_SIZE_BB                                                                       2
+#define BRB_REG_TOTAL_MAC_SIZE_SIZE_K2_E5                                                                    4
+#define BRB_REG_TC_GUARANTIED_0                                                                              0x340900UL //Access:RW   DataWidth:0xe    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_TC_GUARANTIED_1                                                                              0x340904UL //Access:RW   DataWidth:0xe    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_TC_GUARANTIED_2                                                                              0x340908UL //Access:RW   DataWidth:0xe    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_TC_GUARANTIED_3                                                                              0x34090cUL //Access:RW   DataWidth:0xe    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_TC_GUARANTIED_4                                                                              0x340910UL //Access:RW   DataWidth:0xe    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_TC_GUARANTIED_5                                                                              0x340914UL //Access:RW   DataWidth:0xe    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_TC_GUARANTIED_6                                                                              0x340918UL //Access:RW   DataWidth:0xe    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_TC_GUARANTIED_7                                                                              0x34091cUL //Access:RW   DataWidth:0xe    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_TC_GUARANTIED_8                                                                              0x340920UL //Access:RW   DataWidth:0xe    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_TC_GUARANTIED_9                                                                              0x340924UL //Access:RW   DataWidth:0xe    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_TC_GUARANTIED_10                                                                             0x340928UL //Access:RW   DataWidth:0xe    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_TC_GUARANTIED_11                                                                             0x34092cUL //Access:RW   DataWidth:0xe    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_TC_GUARANTIED_12                                                                             0x340930UL //Access:RW   DataWidth:0xe    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_TC_GUARANTIED_13                                                                             0x340934UL //Access:RW   DataWidth:0xe    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_TC_GUARANTIED_14                                                                             0x340938UL //Access:RW   DataWidth:0xe    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_TC_GUARANTIED_15                                                                             0x34093cUL //Access:RW   DataWidth:0xe    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_TC_GUARANTIED_16                                                                             0x340940UL //Access:RW   DataWidth:0xe    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_TC_GUARANTIED_17                                                                             0x340944UL //Access:RW   DataWidth:0xe    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_TC_GUARANTIED_18_K2_E5                                                                       0x340948UL //Access:RW   DataWidth:0xe    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_TC_GUARANTIED_19_K2_E5                                                                       0x34094cUL //Access:RW   DataWidth:0xe    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_GUARANTIED_HYST_0                                                                    0x340978UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_GUARANTIED_HYST_1                                                                    0x34097cUL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_GUARANTIED_HYST_2                                                                    0x340980UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_GUARANTIED_HYST_3                                                                    0x340984UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_GUARANTIED_HYST_4                                                                    0x340988UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_GUARANTIED_HYST_5                                                                    0x34098cUL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_GUARANTIED_HYST_6                                                                    0x340990UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_GUARANTIED_HYST_7                                                                    0x340994UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_GUARANTIED_HYST_8                                                                    0x340998UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_GUARANTIED_HYST_9                                                                    0x34099cUL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_GUARANTIED_HYST_10                                                                   0x3409a0UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_GUARANTIED_HYST_11                                                                   0x3409a4UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_GUARANTIED_HYST_12                                                                   0x3409a8UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_GUARANTIED_HYST_13                                                                   0x3409acUL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_GUARANTIED_HYST_14                                                                   0x3409b0UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_GUARANTIED_HYST_15                                                                   0x3409b4UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_GUARANTIED_HYST_0                                                                      0x3409d8UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_GUARANTIED_HYST_1                                                                      0x3409dcUL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_GUARANTIED_HYST_2                                                                      0x3409e0UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_GUARANTIED_HYST_3                                                                      0x3409e4UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_GUARANTIED_HYST_4                                                                      0x3409e8UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_GUARANTIED_HYST_5                                                                      0x3409ecUL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_GUARANTIED_HYST_6                                                                      0x3409f0UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_GUARANTIED_HYST_7                                                                      0x3409f4UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_GUARANTIED_HYST_8                                                                      0x3409f8UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_GUARANTIED_HYST_9                                                                      0x3409fcUL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_GUARANTIED_HYST_10                                                                     0x340a00UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_GUARANTIED_HYST_11                                                                     0x340a04UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_GUARANTIED_HYST_12                                                                     0x340a08UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_GUARANTIED_HYST_13                                                                     0x340a0cUL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_GUARANTIED_HYST_14                                                                     0x340a10UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_GUARANTIED_HYST_15                                                                     0x340a14UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_GUARANTIED_HYST_16                                                                     0x340a18UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_GUARANTIED_HYST_17                                                                     0x340a1cUL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_GUARANTIED_HYST_18_K2_E5                                                               0x340a20UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_GUARANTIED_HYST_19_K2_E5                                                               0x340a24UL //Access:RW   DataWidth:0xe    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_0                                                               0x340a50UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_1                                                               0x340a54UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_2                                                               0x340a58UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_3                                                               0x340a5cUL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_4                                                               0x340a60UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_5                                                               0x340a64UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_6                                                               0x340a68UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_7                                                               0x340a6cUL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_8                                                               0x340a70UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_9                                                               0x340a74UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_10                                                              0x340a78UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_11                                                              0x340a7cUL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_12                                                              0x340a80UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_13                                                              0x340a84UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_14                                                              0x340a88UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_15                                                              0x340a8cUL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_0                                                                 0x340ab0UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_1                                                                 0x340ab4UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_2                                                                 0x340ab8UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_3                                                                 0x340abcUL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_4                                                                 0x340ac0UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_5                                                                 0x340ac4UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_6                                                                 0x340ac8UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_7                                                                 0x340accUL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_8                                                                 0x340ad0UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_9                                                                 0x340ad4UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_10                                                                0x340ad8UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_11                                                                0x340adcUL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_12                                                                0x340ae0UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_13                                                                0x340ae4UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_14                                                                0x340ae8UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_15                                                                0x340aecUL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_16                                                                0x340af0UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_17                                                                0x340af4UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_18_K2_E5                                                          0x340af8UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_19_K2_E5                                                          0x340afcUL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_0                                                                0x340b28UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_1                                                                0x340b2cUL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_2                                                                0x340b30UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_3                                                                0x340b34UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_4                                                                0x340b38UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_5                                                                0x340b3cUL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_6                                                                0x340b40UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_7                                                                0x340b44UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_8                                                                0x340b48UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_9                                                                0x340b4cUL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_10                                                               0x340b50UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_11                                                               0x340b54UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_12                                                               0x340b58UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_13                                                               0x340b5cUL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_14                                                               0x340b60UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_15                                                               0x340b64UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_0                                                                  0x340b88UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_1                                                                  0x340b8cUL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_2                                                                  0x340b90UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_3                                                                  0x340b94UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_4                                                                  0x340b98UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_5                                                                  0x340b9cUL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_6                                                                  0x340ba0UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_7                                                                  0x340ba4UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_8                                                                  0x340ba8UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_9                                                                  0x340bacUL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_10                                                                 0x340bb0UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_11                                                                 0x340bb4UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_12                                                                 0x340bb8UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_13                                                                 0x340bbcUL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_14                                                                 0x340bc0UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_15                                                                 0x340bc4UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_16                                                                 0x340bc8UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_17                                                                 0x340bccUL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_18_K2_E5                                                           0x340bd0UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_19_K2_E5                                                           0x340bd4UL //Access:RW   DataWidth:0xe    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_0                                                                0x340c00UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_1                                                                0x340c04UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_2                                                                0x340c08UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_3                                                                0x340c0cUL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_4                                                                0x340c10UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_5                                                                0x340c14UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_6                                                                0x340c18UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_7                                                                0x340c1cUL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_8                                                                0x340c20UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_9                                                                0x340c24UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_10                                                               0x340c28UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_11                                                               0x340c2cUL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_12                                                               0x340c30UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_13                                                               0x340c34UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_14                                                               0x340c38UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_15                                                               0x340c3cUL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_0                                                                  0x340c60UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_1                                                                  0x340c64UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_2                                                                  0x340c68UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_3                                                                  0x340c6cUL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_4                                                                  0x340c70UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_5                                                                  0x340c74UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_6                                                                  0x340c78UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_7                                                                  0x340c7cUL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_8                                                                  0x340c80UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_9                                                                  0x340c84UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_10                                                                 0x340c88UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_11                                                                 0x340c8cUL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_12                                                                 0x340c90UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_13                                                                 0x340c94UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_14                                                                 0x340c98UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_15                                                                 0x340c9cUL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_16                                                                 0x340ca0UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_17                                                                 0x340ca4UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_18_K2_E5                                                           0x340ca8UL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_19_K2_E5                                                           0x340cacUL //Access:RW   DataWidth:0xe    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_0                                                                 0x340cd8UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_1                                                                 0x340cdcUL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_2                                                                 0x340ce0UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_3                                                                 0x340ce4UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_4                                                                 0x340ce8UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_5                                                                 0x340cecUL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_6                                                                 0x340cf0UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_7                                                                 0x340cf4UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_8                                                                 0x340cf8UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_9                                                                 0x340cfcUL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_10                                                                0x340d00UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_11                                                                0x340d04UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_12                                                                0x340d08UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_13                                                                0x340d0cUL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_14                                                                0x340d10UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_15                                                                0x340d14UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_0                                                                   0x340d38UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_1                                                                   0x340d3cUL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_2                                                                   0x340d40UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_3                                                                   0x340d44UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_4                                                                   0x340d48UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_5                                                                   0x340d4cUL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_6                                                                   0x340d50UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_7                                                                   0x340d54UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_8                                                                   0x340d58UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_9                                                                   0x340d5cUL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_10                                                                  0x340d60UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_11                                                                  0x340d64UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_12                                                                  0x340d68UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_13                                                                  0x340d6cUL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_14                                                                  0x340d70UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_15                                                                  0x340d74UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_16                                                                  0x340d78UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_17                                                                  0x340d7cUL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_18_K2_E5                                                            0x340d80UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_19_K2_E5                                                            0x340d84UL //Access:RW   DataWidth:0xe    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LOSSLESS_THRESHOLD                                                                           0x340db0UL //Access:RW   DataWidth:0xe    // The number of allocated blocks in each TC after asserting pause upper whih full to that TC or interrupt will be asserted depending on lossless_int_en::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_LOSSLESS_INT_EN                                                                              0x340db4UL //Access:RW   DataWidth:0x1    // If 1 then interrupt will be asserted when number of allocated blocks in  TC bigger lossless_threshold, if 0 - then full to that TC will be asserted.::/PAUSE_EN/d in Existance.
+#define BRB_REG_BRTB_EMPTY_FOR_DUP                                                                           0x340db8UL //Access:RW   DataWidth:0xe    // The number of blocks used by the MAC port below which EMPTY[0] is asserted for this MAC port::s/BLK_WDTH/13/g in Data Width::/EMPTY_EN/d in Existance.
+#define BRB_REG_BRTB_EMPTY_FOR_RDMA                                                                          0x340dbcUL //Access:RW   DataWidth:0xe    // The number of blocks used by the MAC port below which EMPTY[1] is asserted for this MAC port::s/BLK_WDTH/13/g in Data Width::/EMPTY_EN/d in Existance.
+#define BRB_REG_PKT_CNT_THRESHOLD                                                                            0x340dc0UL //Access:RW   DataWidth:0xe    // The number of packets that were read by EOP read client interface but not released by BRTB above which stop parsing interface is asserted::s/BLK_NUM/4800/g in Reset Value::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_BYTE_CNT_THRESHOLD                                                                           0x340dc4UL //Access:RW   DataWidth:0x15   // The number of bytes that were read by EOP read client interface but not released by BRTB above which stop parsing interface is asserted::s/BLK_WDTH_PLUS_7/20/g in Data Width::s/BYTE_CNT_RST/614400/g in Reset Value::/PAUSE_EN/d in Existance.
+#define BRB_REG_NO_DEAD_CYCLES_EN                                                                            0x340dc8UL //Access:RW   DataWidth:0x5    // There is bit for each PACKET read client. Bit 0 suits to client 0 and so on. If bit is set then packet will be read without dead cycles.B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser ::s/NO_DEAD_CYCLE_RST/1/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser/g in Comments::s/PKT_RC_NUM/5/g in Data Width.
+#define BRB_REG_RC_PKT_PRIORITY                                                                              0x340dccUL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define BRB_REG_RC_PKT_PRIORITY_PRM_RC_PRI                                                                 (0x3<<0) // This is priority for PRM  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
+  #define BRB_REG_RC_PKT_PRIORITY_PRM_RC_PRI_SHIFT                                                           0
+  #define BRB_REG_RC_PKT_PRIORITY_MSDM_RC_PRI                                                                (0x3<<2) // This is priority for MSDM  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
+  #define BRB_REG_RC_PKT_PRIORITY_MSDM_RC_PRI_SHIFT                                                          2
+  #define BRB_REG_RC_PKT_PRIORITY_TSDM_RC_PRI                                                                (0x3<<4) // This is priority for TSDM  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
+  #define BRB_REG_RC_PKT_PRIORITY_TSDM_RC_PRI_SHIFT                                                          4
+  #define BRB_REG_RC_PKT_PRIORITY_PARSER_RC_PRI                                                              (0x3<<6) // This is priority for parser  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
+  #define BRB_REG_RC_PKT_PRIORITY_PARSER_RC_PRI_SHIFT                                                        6
+  #define BRB_REG_RC_PKT_PRIORITY_TMLD_RC_PRI                                                                (0x3<<8) // This is priority for TM loader read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 7 is highest. ::/PAUSE_EN/d in Existance.
+  #define BRB_REG_RC_PKT_PRIORITY_TMLD_RC_PRI_SHIFT                                                          8
+#define BRB_REG_WC_NO_DEAD_CYCLES_EN_K2_E5                                                                   0x340dd0UL //Access:RW   DataWidth:0x8    // There is bit for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then packet will be written without intra packet dead cycles .B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser ::s/NO_DEAD_CYCLE_RST/1/g in Reset
+#define BRB_REG_WC_HIGHEST_PRI_EN_K2_E5                                                                      0x340dd4UL //Access:RW   DataWidth:0x8    // There is bit for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then highest priority mechanism is enabled for the corresponding client. B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser ::s/NO_DEAD_CYCLE_RST/1/g in Reset
+#define BRB_REG_WC_LL_HIGH_PRI_E5                                                                            0x340dd8UL //Access:RW   DataWidth:0x8    // This is a bitmap per WC which is 1 for WC with high priority and 0 o/w.
+#define BRB_REG_BR_FIX_HIGH_PRI_COLLISION_E5                                                                 0x340ddcUL //Access:RW   DataWidth:0x1    // This is a bitmap per WC which is 1 for WC with high priority and 0 o/w.
+#define BRB_REG_RC_SOP_PRIORITY                                                                              0x340e08UL //Access:RW   DataWidth:0x2    // This is priority for SOP read client to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_SOP_PRI_RST/5/g in Reset Value.
+#define BRB_REG_RC_EOP_PRIORITY                                                                              0x340e0cUL //Access:RW   DataWidth:0x2    // This is priority for EOP read client to BIG RAM arbiters. Possible values are 0-7. Priority 7 is highest::s/RC_EOP_PRI_RST/4/g in Reset Value::/EOP_RC_EN/d in Existance.
+#define BRB_REG_WC_PRIORITY                                                                                  0x340e10UL //Access:RW   DataWidth:0x2    // This is priority for packet request of write client group to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_WC_PRI_RST/7/g in Reset Value.
+#define BRB_REG_PRI_OF_MULT_CLIENTS                                                                          0x340e14UL //Access:RW   DataWidth:0x2    // This is priority of multiple clients with identical priority for link list arbiter. Selection from them will be done with round robin. Only one group with multiple clients of identical priority is supported. Possible values are 1-3. Priority 3 is highest::s/RC_MULT_PRI_RST/6/g in Reset Value.
+#define BRB_REG_INP_FIFO_ALM_FULL                                                                            0x340e18UL //Access:RW   DataWidth:0x6    // Number of entries inside input FIFO of each write client upper which full outputs to this write client interface.
+#define BRB_REG_WC_SYNC_FIFO_ALM_FULL                                                                        0x340e1cUL //Access:RW   DataWidth:0x5    // Number of entries inside sync FIFO of each write client.
+#define BRB_REG_PKT_RC_OUT_SYNC_FIFO_ALM_FULL                                                                0x340e20UL //Access:RW   DataWidth:0x5    // Number of entries inside output sync FIFO of each read client.
+#define BRB_REG_PKT_AVAIL_SYNC_FIFO_ALM_FULL                                                                 0x340e24UL //Access:RW   DataWidth:0x4    // Number of entries inside packet available sync FIFO.
+#define BRB_REG_RLS_SYNC_FIFO_ALM_FULL                                                                       0x340e28UL //Access:RW   DataWidth:0x4    // Number of entries inside packet available sync FIFO.
+#define BRB_REG_INP_FIFO_HIGH_THRESHOLD                                                                      0x340e2cUL //Access:RW   DataWidth:0x5    // Number of entries inside input FIFO of each write client upper which all arbiters selects this client with high priority.
+#define BRB_REG_DSCR_FIFO_ALM_FULL                                                                           0x340e30UL //Access:RW   DataWidth:0x5    // Number of entries inside descriptors FIFO of each write client upper which full outputs to this write client interface.::s/DSCR_FIFO_RST/12/g in Reset Value.
+#define BRB_REG_QUEUE_FIFO_ALM_FULL                                                                          0x340e34UL //Access:RW   DataWidth:0x5    // Number of entries inside queue FIFO of each write client upper which full outputs to this write client interface.::s/QUEUE_FIFO_RST/8/g in Reset Value.
+#define BRB_REG_DSCR_FIFO_HIGH_THRESHOLD                                                                     0x340e38UL //Access:RW   DataWidth:0x5    // Number of entries inside descriptors FIFO of each write client upper which all arbiters selects this client with high priority.
+#define BRB_REG_PM_TOTAL_PKT_THRESHOLD                                                                       0x340e3cUL //Access:RW   DataWidth:0xe    // Number of packets above which BRB_above_threshold_mac_n is asserted to power management block::s/BLK_NUM/4800/g in Reset Value::s/BLK_WDTH/13/g in Data Width::/EMPTY_EN/d in Existance.
+#define BRB_REG_PM_FREE_THRESHOLD                                                                            0x340e40UL //Access:RW   DataWidth:0xe    // Number of free blocks below which BRB_above_threshold_mac_n is asserted to power management block::s/BLK_WDTH/13/g in Data Width::/EMPTY_EN/d in Existance.
+#define BRB_REG_PM_TC_LATENCY_SENSITIVE_0                                                                    0x340e44UL //Access:RW   DataWidth:0x9    // Per TC enable for output BRB_above_threshold_mac_n to power management block when number of packets of appropriate TC is bigger than 1::s/COS_NUM/9/g in Data Width::s/LATENCY_RST/511/g in Reset Value::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance.
+#define BRB_REG_PM_TC_LATENCY_SENSITIVE_1                                                                    0x340e48UL //Access:RW   DataWidth:0x9    // Per TC enable for output BRB_above_threshold_mac_n to power management block when number of packets of appropriate TC is bigger than 1::s/COS_NUM/9/g in Data Width::s/LATENCY_RST/511/g in Reset Value::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance.
+#define BRB_REG_PM_TC_LATENCY_SENSITIVE_2_K2_E5                                                              0x340e4cUL //Access:RW   DataWidth:0x9    // Per TC enable for output BRB_above_threshold_mac_n to power management block when number of packets of appropriate TC is bigger than 1::s/COS_NUM/9/g in Data Width::s/LATENCY_RST/511/g in Reset Value::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance.
+#define BRB_REG_PM_TC_LATENCY_SENSITIVE_3_K2_E5                                                              0x340e50UL //Access:RW   DataWidth:0x9    // Per TC enable for output BRB_above_threshold_mac_n to power management block when number of packets of appropriate TC is bigger than 1::s/COS_NUM/9/g in Data Width::s/LATENCY_RST/511/g in Reset Value::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance.
+#define BRB_REG_DBGSYN_ALMOST_FULL_THR                                                                       0x340ec4UL //Access:RW   DataWidth:0x4    // Debug only: If more than this Number of entries are occupied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed.
+#define BRB_REG_DBGSYN_STATUS                                                                                0x340ec8UL //Access:R    DataWidth:0x5    // Fill level of dbgmux fifo.
+#define BRB_REG_ECO_RESERVED                                                                                 0x340eccUL //Access:RW   DataWidth:0x20   // This is unused register for future ECOs.
+#define BRB_REG_DBG_SELECT                                                                                   0x340ed0UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define BRB_REG_DBG_DWORD_ENABLE                                                                             0x340ed4UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define BRB_REG_DBG_SHIFT                                                                                    0x340ed8UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define BRB_REG_DBG_FORCE_VALID                                                                              0x340edcUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define BRB_REG_DBG_FORCE_FRAME                                                                              0x340ee0UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define BRB_REG_DBG_OUT_DATA                                                                                 0x340f00UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define BRB_REG_DBG_OUT_DATA_SIZE                                                                            8
+#define BRB_REG_DBG_OUT_VALID                                                                                0x340f20UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define BRB_REG_DBG_OUT_FRAME                                                                                0x340f24UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define BRB_REG_INP_IF_ENABLE                                                                                0x340f28UL //Access:RW   DataWidth:0x19   // Multi Field Register.
+  #define BRB_REG_INP_IF_ENABLE_RC_PKT_INP_IF_EN                                                             (0x3ff<<0) // There is bit per each read client interface: B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser. When bit is set then appropriate interface is enabled. When bit is reset then request from that interface will not be accepted. All bits of this register should be set after init procedure. ::s/PKT_RC_NUM_MINUS_SOP_EN/4/g in Data Width::s/RC_PKT_INP_IF_RST/15/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser/g in Comments.
+  #define BRB_REG_INP_IF_ENABLE_RC_PKT_INP_IF_EN_SHIFT                                                       0
+  #define BRB_REG_INP_IF_ENABLE_RC_EOP_INP_IF_EN                                                             (0xf<<10) // There is bit per each EOP read client interface: B0 - IF0, B1- IF1. When bit is set then appropriate interface is enabled. When bit is reset then request from that interface will not be accepted.  All bits of this register should be set after init procedure. ::s/SHARE_GRP_CNT/2/g in Data Width::s/SHARE_GRP_INIT/3/g in Reset Value::/EOP_RC_EN/d in Existance.
+  #define BRB_REG_INP_IF_ENABLE_RC_EOP_INP_IF_EN_SHIFT                                                       10
+  #define BRB_REG_INP_IF_ENABLE_RC_SOP_INP_IF_EN                                                             (0x1<<14) // There is bit per SOP read client interface. When bit is set then appropriate interface is enabled. When bit is reset then request from that interface will not be accepted.  All bits of this register should be set after init procedure.
+  #define BRB_REG_INP_IF_ENABLE_RC_SOP_INP_IF_EN_SHIFT                                                       14
+  #define BRB_REG_INP_IF_ENABLE_WC_INP_IF_EN                                                                 (0x3ff<<15) // There is bit per write client interface: B0 - NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1.. When bit is set then appropriate interface is enabled. When bit is reset then request from that interface will not be accepted. All bits of this register should be set after init procedure. ::s/WC_IF_RST/15/g in Reset Value::s/WC_EN/B0 - NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1./g in Comments::s/WC_NUM/4/g in Data Width.
+  #define BRB_REG_INP_IF_ENABLE_WC_INP_IF_EN_SHIFT                                                           15
+#define BRB_REG_OUT_IF_ENABLE                                                                                0x340f2cUL //Access:RW   DataWidth:0x1a   // Multi Field Register.
+  #define BRB_REG_OUT_IF_ENABLE_RC_PKT_OUT_IF_EN                                                             (0x3ff<<0) // There is bit per each read client interface: B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser. When bit is set then appropriate interface is enabled. When bit is reset then valid to that interface will never be asserted. All bits of this register should be set after init procedure. ::s/RC_PKT_OUT_IF_RST/31/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser/g in Comments::s/PKT_RC_NUM/5/g in Data Width.
+  #define BRB_REG_OUT_IF_ENABLE_RC_PKT_OUT_IF_EN_SHIFT                                                       0
+  #define BRB_REG_OUT_IF_ENABLE_RC_EOP_OUT_IF_EN                                                             (0xf<<10) // There is bit per each EOP read client interface: B0 - IF0, B1- IF1. When bit is set then appropriate interface is enabled.When bit is reset then valid to that interface will never be asserted. All bits of this register should be set after init procedure. ::s/SHARE_GRP_CNT/2/g in Data Width::s/SHARE_GRP_INIT/3/g in Reset Value::/EOP_RC_EN/d in Existance.
+  #define BRB_REG_OUT_IF_ENABLE_RC_EOP_OUT_IF_EN_SHIFT                                                       10
+  #define BRB_REG_OUT_IF_ENABLE_RC_SOP_OUT_IF_EN                                                             (0x1<<14) // There is bit per SOP read client interface. When bit is set then appropriate interface is enabled. When bit is reset then valid to that interface will never be asserted.  All bits of this register should be set after init procedure.
+  #define BRB_REG_OUT_IF_ENABLE_RC_SOP_OUT_IF_EN_SHIFT                                                       14
+  #define BRB_REG_OUT_IF_ENABLE_PAUSE_OUT_IF_EN                                                              (0xf<<15) // There is bit for all pause interfaces per each MAC port. When bit is set then pause interface is enabled. When bit is reset then any pause will never be set. This bit should be set after init procedure. ::s/SHARE_GRP_CNT/2/g in Data Width::s/SHARE_GRP_INIT/3/g in Reset Value::/PAUSE_EN/d in Existance.
+  #define BRB_REG_OUT_IF_ENABLE_PAUSE_OUT_IF_EN_SHIFT                                                        15
+  #define BRB_REG_OUT_IF_ENABLE_EMPTY_OUT_IF_EN                                                              (0xf<<19) // There is bit for empty interfaces per each MAC port. When bit is set then empty interface is enabled. When bit is reset then empty interface will never be set. This bit should be set after init procedure. ::s/MAX_SHARE_GRP_CNT/2/g in Data Width::s/MAX_SHARE_GRP_INIT/3/g in Reset Value::/EMPTY_EN/d in Existance.
+  #define BRB_REG_OUT_IF_ENABLE_EMPTY_OUT_IF_EN_SHIFT                                                        19
+  #define BRB_REG_OUT_IF_ENABLE_PKT_AVAILABLE_OUT_IF_EN                                                      (0x1<<23) // There is bit for packet avalable interfaces. When bit is set then packet avalable interface is enabled. When bit is reset then packet avalable interface will never be set.  This bit should be set after init procedure.
+  #define BRB_REG_OUT_IF_ENABLE_PKT_AVAILABLE_OUT_IF_EN_SHIFT                                                23
+  #define BRB_REG_OUT_IF_ENABLE_STOP_PARSING_OUT_IF_EN                                                       (0x1<<24) // There is bit for stop parsing interfaces. When bit is set then stop parsing interface is enabled. When bit is reset then stop parsing interface will never be set.  This bit should be set after init procedure. ::/PAUSE_EN/d in Existance.
+  #define BRB_REG_OUT_IF_ENABLE_STOP_PARSING_OUT_IF_EN_SHIFT                                                 24
+  #define BRB_REG_OUT_IF_ENABLE_PM_OUT_IF_EN                                                                 (0x1<<25) // There is bit for power management interfaces. When bit is set then  power management interface is enabled. When bit is reset then  power management interface will never be set.  This bit should be set after init procedure. ::/EMPTY_EN/d in Existance.
+  #define BRB_REG_OUT_IF_ENABLE_PM_OUT_IF_EN_SHIFT                                                           25
+#define BRB_REG_WC_EMPTY_0                                                                                   0x340f30UL //Access:R    DataWidth:0xd    // Debug register. Empty status of each write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.
+#define BRB_REG_WC_EMPTY_1                                                                                   0x340f34UL //Access:R    DataWidth:0xd    // Debug register. Empty status of each write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.
+#define BRB_REG_WC_EMPTY_2                                                                                   0x340f38UL //Access:R    DataWidth:0xd    // Debug register. Empty status of each write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.
+#define BRB_REG_WC_EMPTY_3                                                                                   0x340f3cUL //Access:R    DataWidth:0xd    // Debug register. Empty status of each write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.
+#define BRB_REG_WC_EMPTY_4_K2_E5                                                                             0x340f40UL //Access:R    DataWidth:0xd    // Debug register. Empty status of each write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.
+#define BRB_REG_WC_EMPTY_5_K2_E5                                                                             0x340f44UL //Access:R    DataWidth:0xd    // Debug register. Empty status of each write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.
+#define BRB_REG_WC_EMPTY_6_K2_E5                                                                             0x340f48UL //Access:R    DataWidth:0xd    // Debug register. Empty status of each write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.
+#define BRB_REG_WC_EMPTY_7_K2_E5                                                                             0x340f4cUL //Access:R    DataWidth:0xd    // Debug register. Empty status of each write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.
+#define BRB_REG_WC_FULL_0                                                                                    0x340f70UL //Access:R    DataWidth:0xd    // Debug register. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}
+#define BRB_REG_WC_FULL_1                                                                                    0x340f74UL //Access:R    DataWidth:0xd    // Debug register. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}
+#define BRB_REG_WC_FULL_2                                                                                    0x340f78UL //Access:R    DataWidth:0xd    // Debug register. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}
+#define BRB_REG_WC_FULL_3                                                                                    0x340f7cUL //Access:R    DataWidth:0xd    // Debug register. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}
+#define BRB_REG_WC_FULL_4_K2_E5                                                                              0x340f80UL //Access:R    DataWidth:0xd    // Debug register. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}
+#define BRB_REG_WC_FULL_5_K2_E5                                                                              0x340f84UL //Access:R    DataWidth:0xd    // Debug register. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}
+#define BRB_REG_WC_FULL_6_K2_E5                                                                              0x340f88UL //Access:R    DataWidth:0xd    // Debug register. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}
+#define BRB_REG_WC_FULL_7_K2_E5                                                                              0x340f8cUL //Access:R    DataWidth:0xd    // Debug register. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}
+#define BRB_REG_WC_BANDWIDTH_IF_FULL                                                                         0x340fb0UL //Access:R    DataWidth:0x8    // Debug register. Full status each write client because of temporal bandwidth problem on interface::s/WC_NUM_MAX/4/g in Data Width.
+#define BRB_REG_RC_PKT_IF_FULL                                                                               0x340fb4UL //Access:R    DataWidth:0x5    // Debug register. Full status of each read packet client interface::s/PKT_RC_NUM/5/g in Data Width.
+#define BRB_REG_RC_PKT_EMPTY_0                                                                               0x340fb8UL //Access:R    DataWidth:0x8    // Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BRB_REG_RC_PKT_EMPTY_1                                                                               0x340fbcUL //Access:R    DataWidth:0x8    // Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BRB_REG_RC_PKT_EMPTY_2                                                                               0x340fc0UL //Access:R    DataWidth:0x8    // Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BRB_REG_RC_PKT_EMPTY_3                                                                               0x340fc4UL //Access:R    DataWidth:0x8    // Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BRB_REG_RC_PKT_EMPTY_4                                                                               0x340fc8UL //Access:R    DataWidth:0x8    // Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BRB_REG_RC_PKT_FULL_0                                                                                0x340ff4UL //Access:R    DataWidth:0x8    // Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BRB_REG_RC_PKT_FULL_1                                                                                0x340ff8UL //Access:R    DataWidth:0x8    // Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BRB_REG_RC_PKT_FULL_2                                                                                0x340ffcUL //Access:R    DataWidth:0x8    // Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BRB_REG_RC_PKT_FULL_3                                                                                0x341000UL //Access:R    DataWidth:0x8    // Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BRB_REG_RC_PKT_FULL_4                                                                                0x341004UL //Access:R    DataWidth:0x8    // Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BRB_REG_RC_PKT_STATUS_0                                                                              0x341030UL //Access:R    DataWidth:0x20   // Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.
+#define BRB_REG_RC_PKT_STATUS_1                                                                              0x341034UL //Access:R    DataWidth:0x20   // Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.
+#define BRB_REG_RC_PKT_STATUS_2                                                                              0x341038UL //Access:R    DataWidth:0x20   // Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.
+#define BRB_REG_RC_PKT_STATUS_3                                                                              0x34103cUL //Access:R    DataWidth:0x20   // Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.
+#define BRB_REG_RC_PKT_STATUS_4                                                                              0x341040UL //Access:R    DataWidth:0x20   // Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.
+#define BRB_REG_RC_SOP_EMPTY                                                                                 0x34106cUL //Access:R    DataWidth:0x4    // Debug register. Empty status of read SOP clients: {B2-req_fifo;  B1-dscr_fifo;  B0-queue_fifo}.
+#define BRB_REG_RC_SOP_FULL                                                                                  0x341070UL //Access:R    DataWidth:0x4    // Debug register. Full status of read SOP clients: {B2-req_fifo;  B1-dscr_fifo;  B0-queue_fifo}.
+#define BRB_REG_RC_SOP_STATUS                                                                                0x341074UL //Access:R    DataWidth:0x10   // Debug register. FIFO counters status of read SOP clients: {B11:8-req_fifo;  B7:4-dscr_fifo;  B3:0-queue_fifo}.
+#define BRB_REG_RC_EOP_EMPTY                                                                                 0x341078UL //Access:R    DataWidth:0x4    // Debug register. Empty status of read EOP  clients: empty status of input FIFO for EOP client 0[0]; empty status of input FIFO for EOP client 1[1]::s/SHARE_GRP_CNT/2/g in Data Width::/EOP_RC_EN/d in Existance.
+#define BRB_REG_RC_EOP_FULL                                                                                  0x34107cUL //Access:R    DataWidth:0x4    // Debug register. Full status of read EOP clients: full status of input FIFO for EOP client 0[0]; full status of input FIFO for EOP client 1[1]::s/SHARE_GRP_CNT/2/g in Data Width::/EOP_RC_EN/d in Existance.
+#define BRB_REG_RC_EOP_STATUS                                                                                0x341080UL //Access:R    DataWidth:0x3    // Debug register.FIFO counters status of read EOP clients: status of input FIFO for EOP client 0[2:0]; status of input FIFO for EOP client 1[6:3]::s/RC_EOP_STAT_WDTH/6/g in Data Width::/EOP_RC_EN/d in Existance.
+#define BRB_REG_LL_ARB_EMPTY                                                                                 0x341084UL //Access:R    DataWidth:0x3    // Debug register. Empty status of link list arbiter: {rls_fifo; prefetch_fifo}.
+#define BRB_REG_LL_ARB_FULL                                                                                  0x341088UL //Access:R    DataWidth:0x3    // Debug register. Full status of link list arbiter: {rls_fifo; prefetch_fifos}.
+#define BRB_REG_LL_ARB_STATUS                                                                                0x34108cUL //Access:R    DataWidth:0xe    // Debug register. FIFO counters status of link list arbiter: {rls_fifo[7:4]; prefetch_fifo_1[4:0], prefetch_fifo_0[4:0]}.
+#define BRB_REG_EMPTY_IF_0                                                                                   0x341090UL //Access:R    DataWidth:0x2    // Debug register. This is empty output IF to SEMI::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance.
+#define BRB_REG_EMPTY_IF_1                                                                                   0x341094UL //Access:R    DataWidth:0x2    // Debug register. This is empty output IF to SEMI::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance.
+#define BRB_REG_EMPTY_IF_2_K2_E5                                                                             0x341098UL //Access:R    DataWidth:0x2    // Debug register. This is empty output IF to SEMI::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance.
+#define BRB_REG_EMPTY_IF_3_K2_E5                                                                             0x34109cUL //Access:R    DataWidth:0x2    // Debug register. This is empty output IF to SEMI::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance.
+#define BRB_REG_RC_SOP_INP_SYNC_FIFO_PUSH_STATUS                                                             0x3410a8UL //Access:R    DataWidth:0x3    // Debug register. This is full status of SOP SYNC FIFO for PRS client
+#define BRB_REG_RC_INP_SYNC_FIFO_PUSH_STATUS_0                                                               0x3410acUL //Access:R    DataWidth:0x5    // Debug register. This is full status of packet RC input SYNC FIFO
+#define BRB_REG_RC_INP_SYNC_FIFO_PUSH_STATUS_1                                                               0x3410b0UL //Access:R    DataWidth:0x5    // Debug register. This is full status of packet RC input SYNC FIFO
+#define BRB_REG_RC_INP_SYNC_FIFO_PUSH_STATUS_2                                                               0x3410b4UL //Access:R    DataWidth:0x5    // Debug register. This is full status of packet RC input SYNC FIFO
+#define BRB_REG_RC_INP_SYNC_FIFO_PUSH_STATUS_3                                                               0x3410b8UL //Access:R    DataWidth:0x5    // Debug register. This is full status of packet RC input SYNC FIFO
+#define BRB_REG_RC_OUT_SYNC_FIFO_PUSH_STATUS_0                                                               0x3410e8UL //Access:R    DataWidth:0x5    // Debug register. This is full status of packet RC output SYNC FIFO
+#define BRB_REG_RC_OUT_SYNC_FIFO_PUSH_STATUS_1                                                               0x3410ecUL //Access:R    DataWidth:0x5    // Debug register. This is full status of packet RC output SYNC FIFO
+#define BRB_REG_RC_OUT_SYNC_FIFO_PUSH_STATUS_2                                                               0x3410f0UL //Access:R    DataWidth:0x5    // Debug register. This is full status of packet RC output SYNC FIFO
+#define BRB_REG_RC_OUT_SYNC_FIFO_PUSH_STATUS_3                                                               0x3410f4UL //Access:R    DataWidth:0x5    // Debug register. This is full status of packet RC output SYNC FIFO
+#define BRB_REG_RC_OUT_SYNC_FIFO_PUSH_STATUS_4                                                               0x3410f8UL //Access:R    DataWidth:0x5    // Debug register. This is full status of packet RC output SYNC FIFO
+#define BRB_REG_RC_EOP_INP_SYNC_FIFO_PUSH_STATUS_0                                                           0x341124UL //Access:R    DataWidth:0x3    // Debug register. This is full status of EOP RC input SYNC FIFO
+#define BRB_REG_RC_EOP_INP_SYNC_FIFO_PUSH_STATUS_1_BB_K2                                                     0x341128UL //Access:R    DataWidth:0x3    // Debug register. This is full status of EOP RC input SYNC FIFO
+#define BRB_REG_RC_EOP_INP_SYNC_FIFO_PUSH_STATUS_2_K2                                                        0x34112cUL //Access:R    DataWidth:0x3    // Debug register. This is full status of EOP RC input SYNC FIFO
+#define BRB_REG_RC_EOP_INP_SYNC_FIFO_PUSH_STATUS_3_K2                                                        0x341130UL //Access:R    DataWidth:0x3    // Debug register. This is full status of EOP RC input SYNC FIFO
+#define BRB_REG_RC_EOP_OUT_SYNC_FIFO_PUSH_STATUS_0                                                           0x341160UL //Access:R    DataWidth:0x3    // Debug register. This is full status of EOP RC output SYNC FIFO
+#define BRB_REG_RC_EOP_OUT_SYNC_FIFO_PUSH_STATUS_1_BB_K2                                                     0x341164UL //Access:R    DataWidth:0x3    // Debug register. This is full status of EOP RC output SYNC FIFO
+#define BRB_REG_RC_EOP_OUT_SYNC_FIFO_PUSH_STATUS_2_K2                                                        0x341168UL //Access:R    DataWidth:0x3    // Debug register. This is full status of EOP RC output SYNC FIFO
+#define BRB_REG_RC_EOP_OUT_SYNC_FIFO_PUSH_STATUS_3_K2                                                        0x34116cUL //Access:R    DataWidth:0x3    // Debug register. This is full status of EOP RC output SYNC FIFO
+#define BRB_REG_PKT_AVAIL_SYNC_FIFO_PUSH_STATUS                                                              0x34119cUL //Access:R    DataWidth:0x4    // Debug register. This is full status of packet available SYNC FIFO
+#define BRB_REG_STOP_PACKET_COUNTER                                                                          0x3411a0UL //Access:R    DataWidth:0xe    // Debug register. This is packet counter that counts number of packets from EOP read request till release. This counter is used for stop parsing interface logic.::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_STOP_BYTE_COUNTER                                                                            0x3411a4UL //Access:R    DataWidth:0x15   // Debug register. This is byte counter that counts number of bytes from EOP read request till release. This counter is used for stop parsing interface logic.::s/BLK_WDTH_PLUS_7/20/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_RC_PKT_STATE                                                                                 0x3411a8UL //Access:R    DataWidth:0x14   // Debug register. This is state machine for each read client. ::s/PKT_RC_NUM_ST/20/g in Data Width.
+#define BRB_REG_MAC_FREE_SHARED_HR_0                                                                         0x3411b8UL //Access:R    DataWidth:0xe    // Debug register. The number of free blocks for each MAC port that includes shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/SHARED_HR_RST/2112/g in Reset Value::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC_FREE_SHARED_HR_1                                                                         0x3411bcUL //Access:R    DataWidth:0xe    // Debug register. The number of free blocks for each MAC port that includes shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/SHARED_HR_RST/2112/g in Reset Value::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC_FREE_SHARED_HR_2_K2_E5                                                                   0x3411c0UL //Access:R    DataWidth:0xe    // Debug register. The number of free blocks for each MAC port that includes shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/SHARED_HR_RST/2112/g in Reset Value::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC_FREE_SHARED_HR_3_K2_E5                                                                   0x3411c4UL //Access:R    DataWidth:0xe    // Debug register. The number of free blocks for each MAC port that includes shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/SHARED_HR_RST/2112/g in Reset Value::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC0_TC_OCCUPANCY_0                                                                          0x3411d0UL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC0_TC_OCCUPANCY_1                                                                          0x3411d4UL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC0_TC_OCCUPANCY_2                                                                          0x3411d8UL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC0_TC_OCCUPANCY_3                                                                          0x3411dcUL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC0_TC_OCCUPANCY_4                                                                          0x3411e0UL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC0_TC_OCCUPANCY_5                                                                          0x3411e4UL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC0_TC_OCCUPANCY_6                                                                          0x3411e8UL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC0_TC_OCCUPANCY_7                                                                          0x3411ecUL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC0_TC_OCCUPANCY_8                                                                          0x3411f0UL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC1_TC_OCCUPANCY_0                                                                          0x341210UL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC1_TC_OCCUPANCY_1                                                                          0x341214UL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC1_TC_OCCUPANCY_2                                                                          0x341218UL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC1_TC_OCCUPANCY_3                                                                          0x34121cUL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC1_TC_OCCUPANCY_4                                                                          0x341220UL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC1_TC_OCCUPANCY_5                                                                          0x341224UL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC1_TC_OCCUPANCY_6                                                                          0x341228UL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC1_TC_OCCUPANCY_7                                                                          0x34122cUL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC1_TC_OCCUPANCY_8                                                                          0x341230UL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC2_TC_OCCUPANCY_0_K2_E5                                                                    0x341250UL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 2::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC2_TC_OCCUPANCY_1_K2_E5                                                                    0x341254UL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 2::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC2_TC_OCCUPANCY_2_K2_E5                                                                    0x341258UL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 2::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC2_TC_OCCUPANCY_3_K2_E5                                                                    0x34125cUL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 2::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC2_TC_OCCUPANCY_4_K2_E5                                                                    0x341260UL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 2::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC3_TC_OCCUPANCY_0_K2_E5                                                                    0x341290UL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 3::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC3_TC_OCCUPANCY_1_K2_E5                                                                    0x341294UL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 3::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC3_TC_OCCUPANCY_2_K2_E5                                                                    0x341298UL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 3::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC3_TC_OCCUPANCY_3_K2_E5                                                                    0x34129cUL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 3::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAC3_TC_OCCUPANCY_4_K2_E5                                                                    0x3412a0UL //Access:R    DataWidth:0xe    // Debug register. The number of block occupied by each TC in each main port 3::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_AVAILABLE_MAC_SIZE_0                                                                         0x3412d0UL //Access:R    DataWidth:0xe    // Debug register. The available number of blocks for each MAC port that includes guaranteed and shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance.
+#define BRB_REG_AVAILABLE_MAC_SIZE_1                                                                         0x3412d4UL //Access:R    DataWidth:0xe    // Debug register. The available number of blocks for each MAC port that includes guaranteed and shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance.
+#define BRB_REG_AVAILABLE_MAC_SIZE_2_K2_E5                                                                   0x3412d8UL //Access:R    DataWidth:0xe    // Debug register. The available number of blocks for each MAC port that includes guaranteed and shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance.
+#define BRB_REG_AVAILABLE_MAC_SIZE_3_K2_E5                                                                   0x3412dcUL //Access:R    DataWidth:0xe    // Debug register. The available number of blocks for each MAC port that includes guaranteed and shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_0                                                                              0x3412e8UL //Access:R    DataWidth:0x8    // Debug register. Output pause signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_1                                                                              0x3412ecUL //Access:R    DataWidth:0x8    // Debug register. Output pause signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_2_K2_E5                                                                        0x3412f0UL //Access:R    DataWidth:0x8    // Debug register. Output pause signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_PAUSE_3_K2_E5                                                                        0x3412f4UL //Access:R    DataWidth:0x8    // Debug register. Output pause signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_0                                                                                0x341300UL //Access:R    DataWidth:0x9    // Debug register. Output pause signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_1                                                                                0x341304UL //Access:R    DataWidth:0x9    // Debug register. Output pause signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_2_K2_E5                                                                          0x341308UL //Access:R    DataWidth:0x9    // Debug register. Output pause signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_PAUSE_3_K2_E5                                                                          0x34130cUL //Access:R    DataWidth:0x9    // Debug register. Output pause signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_0                                                                               0x341318UL //Access:R    DataWidth:0x8    // Debug register. Output full signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_1                                                                               0x34131cUL //Access:R    DataWidth:0x8    // Debug register. Output full signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_2_K2_E5                                                                         0x341320UL //Access:R    DataWidth:0x8    // Debug register. Output full signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_FULL_3_K2_E5                                                                         0x341324UL //Access:R    DataWidth:0x8    // Debug register. Output full signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_0                                                                                 0x341330UL //Access:R    DataWidth:0x9    // Debug register. Output full signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_1                                                                                 0x341334UL //Access:R    DataWidth:0x9    // Debug register. Output full signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_2_K2_E5                                                                           0x341338UL //Access:R    DataWidth:0x9    // Debug register. Output full signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_LB_TC_FULL_3_K2_E5                                                                           0x34133cUL //Access:R    DataWidth:0x9    // Debug register. Output full signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN0_TC_LOSSLESS_CNT_0                                                                      0x341348UL //Access:R    DataWidth:0xe    // Debug register. Uncomplient lossless counter for each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN0_TC_LOSSLESS_CNT_1                                                                      0x34134cUL //Access:R    DataWidth:0xe    // Debug register. Uncomplient lossless counter for each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN0_TC_LOSSLESS_CNT_2                                                                      0x341350UL //Access:R    DataWidth:0xe    // Debug register. Uncomplient lossless counter for each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN0_TC_LOSSLESS_CNT_3                                                                      0x341354UL //Access:R    DataWidth:0xe    // Debug register. Uncomplient lossless counter for each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN0_TC_LOSSLESS_CNT_4                                                                      0x341358UL //Access:R    DataWidth:0xe    // Debug register. Uncomplient lossless counter for each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN0_TC_LOSSLESS_CNT_5                                                                      0x34135cUL //Access:R    DataWidth:0xe    // Debug register. Uncomplient lossless counter for each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN0_TC_LOSSLESS_CNT_6                                                                      0x341360UL //Access:R    DataWidth:0xe    // Debug register. Uncomplient lossless counter for each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN0_TC_LOSSLESS_CNT_7                                                                      0x341364UL //Access:R    DataWidth:0xe    // Debug register. Uncomplient lossless counter for each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN1_TC_LOSSLESS_CNT_0                                                                      0x341388UL //Access:R    DataWidth:0xe    // Debug register. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN1_TC_LOSSLESS_CNT_1                                                                      0x34138cUL //Access:R    DataWidth:0xe    // Debug register. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN1_TC_LOSSLESS_CNT_2                                                                      0x341390UL //Access:R    DataWidth:0xe    // Debug register. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN1_TC_LOSSLESS_CNT_3                                                                      0x341394UL //Access:R    DataWidth:0xe    // Debug register. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN1_TC_LOSSLESS_CNT_4                                                                      0x341398UL //Access:R    DataWidth:0xe    // Debug register. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN1_TC_LOSSLESS_CNT_5                                                                      0x34139cUL //Access:R    DataWidth:0xe    // Debug register. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN1_TC_LOSSLESS_CNT_6                                                                      0x3413a0UL //Access:R    DataWidth:0xe    // Debug register. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN1_TC_LOSSLESS_CNT_7                                                                      0x3413a4UL //Access:R    DataWidth:0xe    // Debug register. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN2_TC_LOSSLESS_CNT_0_K2_E5                                                                0x3413c8UL //Access:R    DataWidth:0xe    // Debug register. Uncomplient lossless counter for each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN2_TC_LOSSLESS_CNT_1_K2_E5                                                                0x3413ccUL //Access:R    DataWidth:0xe    // Debug register. Uncomplient lossless counter for each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN2_TC_LOSSLESS_CNT_2_K2_E5                                                                0x3413d0UL //Access:R    DataWidth:0xe    // Debug register. Uncomplient lossless counter for each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN2_TC_LOSSLESS_CNT_3_K2_E5                                                                0x3413d4UL //Access:R    DataWidth:0xe    // Debug register. Uncomplient lossless counter for each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN3_TC_LOSSLESS_CNT_0_K2_E5                                                                0x341408UL //Access:R    DataWidth:0xe    // Debug register. Uncomplient lossless counter for each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN3_TC_LOSSLESS_CNT_1_K2_E5                                                                0x34140cUL //Access:R    DataWidth:0xe    // Debug register. Uncomplient lossless counter for each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN3_TC_LOSSLESS_CNT_2_K2_E5                                                                0x341410UL //Access:R    DataWidth:0xe    // Debug register. Uncomplient lossless counter for each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN3_TC_LOSSLESS_CNT_3_K2_E5                                                                0x341414UL //Access:R    DataWidth:0xe    // Debug register. Uncomplient lossless counter for each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_LOSSLESS_INT_0                                                                       0x341448UL //Access:R    DataWidth:0x8    // Debug register. Uncomplient lossless counter interrupt for each TC of each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_LOSSLESS_INT_1                                                                       0x34144cUL //Access:R    DataWidth:0x8    // Debug register. Uncomplient lossless counter interrupt for each TC of each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_LOSSLESS_INT_2_K2_E5                                                                 0x341450UL //Access:R    DataWidth:0x8    // Debug register. Uncomplient lossless counter interrupt for each TC of each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_MAIN_TC_LOSSLESS_INT_3_K2_E5                                                                 0x341454UL //Access:R    DataWidth:0x8    // Debug register. Uncomplient lossless counter interrupt for each TC of each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.
+#define BRB_REG_BIG_RAM_DATA                                                                                 0x341500UL //Access:WB   DataWidth:0x80   // Debug register. Data to BIG RAM memory. Write to 32 MSB bits of this register will generate write to BIG RAM according to address that is written in big_ram_address register. Read from 32 LSB bits of this register will generate read from BIG RAM according to address written in big_ram_address register.
+#define BRB_REG_BIG_RAM_DATA_SIZE                                                                            64
+#define BRB_REG_RC_SOP_QUEUE_STATUS                                                                          0x341600UL //Access:R    DataWidth:0x20   // Debug register. There is register for each queue of each write client. It contains: b31 - valid; b30:16 - queue size; b15:0 - queue start pointer::s/SOP_STATUS_RST/536805376/g in Reset Value::s/QUEUE_ARRAY/36/g in memory size::s/SOP_STATUS_WDTH/6/g in Address Width.
+#define BRB_REG_RC_SOP_QUEUE_STATUS_SIZE_BB                                                                  36
+#define BRB_REG_RC_SOP_QUEUE_STATUS_SIZE_K2_E5                                                               120
+#define BRB_REG_STOPPED_RD_REQ                                                                               0x341800UL //Access:WB_R DataWidth:0x45   // If there is length error of first block error then request from read client will be copied to this register for each erad packet client interface: 0-PRM; 1-MSDM ; 2-TSDM; 3-TMLD; 4-PRS. Message spelling (MSB->LSB): rest_size_error[0]; len_error[0]; 1st_error[0]; middle_error[0]; rls_to_do[9:0]; start_block[12:0]; rd_req[0]; rls_req[0]; offset[9:0]; length[13:0]; opaque[15:0]
+#define BRB_REG_STOPPED_RD_REQ_SIZE                                                                          20
+#define BRB_REG_STOPPED_RLS_REQ                                                                              0x341900UL //Access:WB_R DataWidth:0x4c   // If there is release error then request from read client will be copied to this register for each read packet client interface: 0-PRM; 1-MSDM ; 2-TSDM; 3-TMLD; 4-PRS. Message spelling (MSB->LSB): opaque[9:0]; rls_to_do[15:0]; queue_number[3:0]; packet_length[13:0]; rls_left[9:0]; start_block[12:0]
+#define BRB_REG_STOPPED_RLS_REQ_SIZE                                                                         20
+#define BRB_REG_PER_TC_COUNTERS                                                                              0x341a00UL //Access:R    DataWidth:0x18   // Per-port per-TC counters. In BigBear, entries 0-7 are port 0 (main 0) TCs 0-7. Entries 8-16 are port 1 (lb 0) TCs 0-8. Similarly for entries 17-24 for port 2 and 25-33 for port 3. In K2, entries 0-3 are port 0 TCs 0-3. Entries 4-8 are port 1 TCs 0-3, 8. Similarly for the other 6 ports.
+#define BRB_REG_PER_TC_COUNTERS_SIZE                                                                         34
+#define BRB_REG_WC_STATUS_0                                                                                  0x341b00UL //Access:WB_R DataWidth:0x5b   // Debug register. FIFO counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
+#define BRB_REG_WC_STATUS_0_SIZE                                                                             4
+#define BRB_REG_WC_STATUS_1                                                                                  0x341b10UL //Access:WB_R DataWidth:0x5b   // Debug register. FIFO counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
+#define BRB_REG_WC_STATUS_1_SIZE                                                                             4
+#define BRB_REG_WC_STATUS_2                                                                                  0x341b20UL //Access:WB_R DataWidth:0x5b   // Debug register. FIFO counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
+#define BRB_REG_WC_STATUS_2_SIZE                                                                             4
+#define BRB_REG_WC_STATUS_3                                                                                  0x341b30UL //Access:WB_R DataWidth:0x5b   // Debug register. FIFO counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
+#define BRB_REG_WC_STATUS_3_SIZE                                                                             4
+#define BRB_REG_WC_STATUS_4_K2_E5                                                                            0x341b40UL //Access:WB_R DataWidth:0x5b   // Debug register. FIFO counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
+#define BRB_REG_WC_STATUS_4_SIZE                                                                             4
+#define BRB_REG_WC_STATUS_5_K2_E5                                                                            0x341b50UL //Access:WB_R DataWidth:0x5b   // Debug register. FIFO counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
+#define BRB_REG_WC_STATUS_5_SIZE                                                                             4
+#define BRB_REG_WC_STATUS_6_K2_E5                                                                            0x341b60UL //Access:WB_R DataWidth:0x5b   // Debug register. FIFO counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
+#define BRB_REG_WC_STATUS_6_SIZE                                                                             4
+#define BRB_REG_WC_STATUS_7_K2_E5                                                                            0x341b70UL //Access:WB_R DataWidth:0x5b   // Debug register. FIFO counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
+#define BRB_REG_WC_STATUS_7_SIZE                                                                             4
+#define BRB_REG_MEMCTRL_WR_RD_N_BB                                                                           0x341c00UL //Access:RW   DataWidth:0x1    // wr/rd indication to CPU BIST
+#define BRB_REG_MEMCTRL_CMD_BB                                                                               0x341c04UL //Access:RW   DataWidth:0x8    // command to CPU BIST
+#define BRB_REG_MEMCTRL_ADDRESS_BB                                                                           0x341c08UL //Access:RW   DataWidth:0x8    // address to CPU BIST
+#define BRB_REG_MEMCTRL_STATUS_BB                                                                            0x341c0cUL //Access:R    DataWidth:0x20   // status from CPU BIST
+#define BRB_REG_LINK_LIST_BB_K2                                                                              0x348000UL //Access:RW   DataWidth:0xe    // Link list dual port memory that contains per-block descriptor::s/BLK_NUM/4800/g in memory size::s/BLK_WDTH_PLUS_SOP_EN/14/g in Data Width::s/BLK_WDTH/13/g in Address Width.
+#define BRB_REG_LINK_LIST_E5                                                                                 0x350000UL //Access:RW   DataWidth:0xf    // Link list dual port memory that contains per-block descriptor::s/BLK_NUM/4800/g in memory size::s/BLK_WDTH_PLUS_SOP_EN/14/g in Data Width::s/BLK_WDTH/13/g in Address Width.
+#define BRB_REG_LINK_LIST_SIZE_BB                                                                            4800
+#define BRB_REG_LINK_LIST_SIZE_K2                                                                            7680
+#define BRB_REG_LINK_LIST_SIZE_E5                                                                            8832
+#define XYLD_REG_SCBD_STRICT_PRIO                                                                            0x4c0000UL //Access:RW   DataWidth:0x4    // Each bit indicates if the current queue ahs a strict prioirty; 1: The current queue has strict prority; 0: The current queue is part of the WRR scheme.
+#define XYLD_REG_SCBD_WRR_WEIGHT_Q0                                                                          0x4c0004UL //Access:RW   DataWidth:0x2    // The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_strict_prio reg.
+#define XYLD_REG_SCBD_WRR_WEIGHT_Q1                                                                          0x4c0008UL //Access:RW   DataWidth:0x2    // The weight of queue 1 at the WRR arbiteration, in case its bit is reset at scbd_strict_prio reg.
+#define XYLD_REG_FOCI_FOC_CREDITS                                                                            0x4c000cUL //Access:RW   DataWidth:0x6    // Initial credit of the FOC itnerface.
+#define XYLD_REG_PCII_PXP_RD_REQ_CREDITS                                                                     0x4c0010UL //Access:RW   DataWidth:0x2    // Initial credit for the PCI interface::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.
+#define XYLD_REG_PCII_RD_RESP_NUM_SLOTS                                                                      0x4c0014UL //Access:RW   DataWidth:0x3    // Number of slots at the PCI read response buffer: 3=4/8 slots of 512 bytes;4=8/16 slots of 256 bytes;5=16/32 slots of 128 bytes;6=32/64 slots of 64 bytes; 7=64/128 slots of 32 bytes::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.
+#define XYLD_REG_BYPASS_QID                                                                                  0x4c0018UL //Access:RW   DataWidth:0x2    // Selects the queue to which bypass messages will be steered.
+#define XYLD_REG_TCFC_LOAD_MINI_CACHE_EN                                                                     0x4c001cUL //Access:RW   DataWidth:0x1    // Allowes the TID/CID mini cache feature.
+#define XYLD_REG_CCFC_LOAD_MINI_CACHE_EN                                                                     0x4c0020UL //Access:RW   DataWidth:0x1    // Allowes the TID/CID mini cache feature.
+#define XYLD_REG_ECO_RESERVED                                                                                0x4c0024UL //Access:RW   DataWidth:0x8    // Allowes future ECO's
+#define XYLD_REG_LD_VQID                                                                                     0x4c0028UL //Access:RW   DataWidth:0x5    // VQID value for PXP read requests issued from all sources (PCI read BD fetches and SGE fetches).
+#define XYLD_REG_CID_REQ_CREDITS                                                                             0x4c002cUL //Access:RW   DataWidth:0x6    // Max credits value for the load cid request interface.
+#define XYLD_REG_TID_REQ_CREDITS                                                                             0x4c0030UL //Access:RW   DataWidth:0x6    // Max credits value for the load tid request interface.
+#define XYLD_REG_LD_SEG_MSG_Q                                                                                0x4c0034UL //Access:RW   DataWidth:0x2    // The QID to which the segment messages can be mapped::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.
+#define XYLD_REG_TID_REMAIN_CREDITS                                                                          0x4c0038UL //Access:R    DataWidth:0x6    // Remaining credits for the tid interface
+#define XYLD_REG_TID_MSG_STAT                                                                                0x4c003cUL //Access:RC   DataWidth:0x20   // Statistics counter of TID requests
+#define XYLD_REG_CID_REMAIN_CREDITS                                                                          0x4c0040UL //Access:R    DataWidth:0x6    // Remaining credits for the cid interface
+#define XYLD_REG_CID_MSG_STAT                                                                                0x4c0044UL //Access:RC   DataWidth:0x20   // Statistics counter of CID requests
+#define XYLD_REG_EXT_EV_1_STAT                                                                               0x4c0048UL //Access:RC   DataWidth:0x20   // Statistics counter of message pending to external event 1
+#define XYLD_REG_EXT_EV_2_STAT                                                                               0x4c004cUL //Access:RC   DataWidth:0x20   // Statistics counter of message pending to external event 2
+#define XYLD_REG_EXT_EV_3_STAT                                                                               0x4c0050UL //Access:RC   DataWidth:0x20   // Statistics counter of message pending to external event 3
+#define XYLD_REG_EXT_EV_4_STAT                                                                               0x4c0054UL //Access:RC   DataWidth:0x20   // Statistics counter of message pending to external event 0
+#define XYLD_REG_EXT_EV_5_STAT                                                                               0x4c0058UL //Access:RC   DataWidth:0x20   // Statistics counter of message pending to external event 0
+#define XYLD_REG_PENDING_MSG_TO_EXT_EV_1_CTR                                                                 0x4c005cUL //Access:R    DataWidth:0x9    // Counts the number of messages currently pending to external event 1
+#define XYLD_REG_PENDING_MSG_TO_EXT_EV_2_CTR                                                                 0x4c0060UL //Access:R    DataWidth:0x9    // Counts the number of messages currently pending to external event 2
+#define XYLD_REG_PENDING_MSG_TO_EXT_EV_3_CTR                                                                 0x4c0064UL //Access:R    DataWidth:0x9    // Counts the number of messages currently pending to external event 3
+#define XYLD_REG_PENDING_MSG_TO_EXT_EV_4_CTR                                                                 0x4c0068UL //Access:R    DataWidth:0x9    // Counts the number of messages currently pending to external event 4
+#define XYLD_REG_PENDING_MSG_TO_EXT_EV_5_CTR                                                                 0x4c006cUL //Access:R    DataWidth:0x9    // Counts the number of messages currently pending to external event 5
+#define XYLD_REG_FOC_REMAIN_CREDITS                                                                          0x4c0070UL //Access:R    DataWidth:0x6    // Remaining credits on the FOC interface
+#define XYLD_REG_PXP_MSG_STAT                                                                                0x4c0074UL //Access:RC   DataWidth:0x20   // Statistics counter of PXP requests sent
+#define XYLD_REG_PCII_REMAIN_CREDITS                                                                         0x4c0078UL //Access:R    DataWidth:0x2    // Remaining credits on the PCI interface
+#define XYLD_REG_PCI_PENDING_MSG_CTR                                                                         0x4c007cUL //Access:R    DataWidth:0x9    // Number of messages pending to PCI read request
+#define XYLD_REG_LD_CID_MINICACHE_LOG                                                                        0x4c0080UL //Access:R    DataWidth:0x20   // Logging in case of minicache failure.bits 31:0 CID Valid only if bit 13 in ld_cid_minicache_resp_log is set
+#define XYLD_REG_LD_TID_MINICACHE_LOG                                                                        0x4c0084UL //Access:R    DataWidth:0x20   // Logging in case of minicache failure.bits 31:0 TID Valid only if bit 13 in ld_tid_minicache_resp_log is set
+#define XYLD_REG_LD_CID_MINICACHE_RESP_LOG                                                                   0x4c0088UL //Access:R    DataWidth:0xe    // Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_cid_minicache_log register is valid
+#define XYLD_REG_LD_TID_MINICACHE_RESP_LOG                                                                   0x4c008cUL //Access:R    DataWidth:0xe    // Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_tid_minicache_log register is valid
+#define XYLD_REG_LD_HDR_LOG                                                                                  0x4c0090UL //Access:R    DataWidth:0x4    // Logging of the problem which caused the ld_hdr_err interrupt. Bit 0: ilegal flags combination.
+#define XYLD_REG_LD_HDR_1ST_CYC_31_0                                                                         0x4c0094UL //Access:R    DataWidth:0x20   // Logging of the first loader header cycle - for the case ld_hdr_err is raised.
+#define XYLD_REG_LD_HDR_1ST_CYC_63_32                                                                        0x4c0098UL //Access:R    DataWidth:0x20   // Logging of the first loader header cycle - for the case ld_hdr_err is raised.
+#define XYLD_REG_LD_HDR_1ST_CYC_95_64                                                                        0x4c009cUL //Access:R    DataWidth:0x20   // Logging of the first loader header cycle - for the case ld_hdr_err is raised.
+#define XYLD_REG_LD_HDR_1ST_CYC_127_96                                                                       0x4c00a0UL //Access:R    DataWidth:0x20   // Logging of the first loader header cycle - for the case ld_hdr_err is raised.
+#define XYLD_REG_LD_HDR_2ND_CYC_31_0                                                                         0x4c00a4UL //Access:R    DataWidth:0x20   // Logging of the second loader header cycle - for the case ld_hdr_err is raised.
+#define XYLD_REG_LD_HDR_2ND_CYC_63_32                                                                        0x4c00a8UL //Access:R    DataWidth:0x20   // Logging of the second loader header cycle - for the case ld_hdr_err is raised.
+#define XYLD_REG_LD_HDR_2ND_CYC_95_64                                                                        0x4c00acUL //Access:R    DataWidth:0x20   // Logging of the second loader header cycle - for the case ld_hdr_err is raised.
+#define XYLD_REG_LD_HDR_2ND_CYC_127_96                                                                       0x4c00b0UL //Access:R    DataWidth:0x20   // Logging of the second loader header cycle - for the case ld_hdr_err is raised.
+#define XYLD_REG_CM_HDR_31_0                                                                                 0x4c00b4UL //Access:R    DataWidth:0x20   // Logging of the cm header cycle - for the case ld_hdr_err is raised.
+#define XYLD_REG_CM_HDR_63_32                                                                                0x4c00b8UL //Access:R    DataWidth:0x20   // Logging of the cm header cycle - for the case ld_hdr_err is raised.
+#define XYLD_REG_CM_HDR_95_64                                                                                0x4c00bcUL //Access:R    DataWidth:0x20   // Logging of the cm header cycle - for the case ld_hdr_err is raised.
+#define XYLD_REG_CM_HDR_127_96                                                                               0x4c00c0UL //Access:R    DataWidth:0x20   // Logging of the cm header cycle - for the case ld_hdr_err is raised.
+#define XYLD_REG_LD_HDR_CLR                                                                                  0x4c00c4UL //Access:W    DataWidth:0x1    // Writing to this register clears hdr registers and enables logging new error details.
+#define XYLD_REG_SEG_MSG_LOG                                                                                 0x4c00c8UL //Access:R    DataWidth:0x8    // Logging register for segment message error: bits 3:0 - header len; bits 7:4 - number of iteration::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.
+#define XYLD_REG_SEG_MSG_LOG_LEN_ARR_31_0                                                                    0x4c00ccUL //Access:R    DataWidth:0x20   // Logging register for segment message error: bits 31:0 - bits 31:0 of the segment message length array::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.
+#define XYLD_REG_SEG_MSG_LOG_LEN_ARR_63_32                                                                   0x4c00d0UL //Access:R    DataWidth:0x20   // Logging register for segment message error: bits 31:0 - bits 63:32 of the segment message length array::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.
+#define XYLD_REG_SEG_MSG_LOG_LEN_ARR_95_64                                                                   0x4c00d4UL //Access:R    DataWidth:0x20   // Logging register for segment message error: bits 31:0 - bits 95:64 of the segment message length array::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.
+#define XYLD_REG_SEG_MSG_LOG_CLR                                                                             0x4c00d8UL //Access:W    DataWidth:0x1    // Writing to this register clears seg msg logging registers and enables logging new error details::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.
+#define XYLD_REG_SEG_MSG_LOG_V                                                                               0x4c00dcUL //Access:R    DataWidth:0x1    // Indicates that the data at the seg_msg logging registers is valid::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.
+#define XYLD_REG_STAT_FIC_MSG                                                                                0x4c00e0UL //Access:RC   DataWidth:0x20   // Number of FIC messages sent to the loader
+#define XYLD_REG_DBG_PENDING_CCFC_REQ                                                                        0x4c00e4UL //Access:R    DataWidth:0x6    // number of CCFC requests wating for responses
+#define XYLD_REG_DBG_PENDING_TCFC_REQ                                                                        0x4c00e8UL //Access:R    DataWidth:0x6    // number of TCFC requests wating for responses
+#define XYLD_REG_LEN_ERR_LOG_1                                                                               0x4c00ecUL //Access:R    DataWidth:0x10   // Logging register for long message error: bit 0-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SGE fetch; bit 4- Message with BRB fetch; bits 5:6- QID; bits 7-RSV; bits 8-15 message CM length.
+#define XYLD_REG_LEN_ERR_LOG_2                                                                               0x4c00f0UL //Access:R    DataWidth:0x20   // Logging register for long message error: bit 0:3 Segment message header length; 4:7 RSV;8:15 current length out of the segment message length array; 16:23 PCI response len (including BD and SGE fetches); 24:31 BRB
+#define XYLD_REG_LEN_ERR_LOG_CLR                                                                             0x4c00f4UL //Access:W    DataWidth:0x1    // Writing to this register clears len err logging registers and enables logging new error details.
+#define XYLD_REG_LEN_ERR_LOG_V                                                                               0x4c00f8UL //Access:R    DataWidth:0x1    // Indicates that the data at the len_err logging registers is valid.
+#define XYLD_REG_INT_STS                                                                                     0x4c0180UL //Access:R    DataWidth:0x6    // Multi Field Register.
+  #define XYLD_REG_INT_STS_ADDRESS_ERROR                                                                     (0x1<<0) // Signals an unknown address to the rf module.
+  #define XYLD_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                               0
+  #define XYLD_REG_INT_STS_LD_HDR_ERR                                                                        (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
+  #define XYLD_REG_INT_STS_LD_HDR_ERR_SHIFT                                                                  1
+  #define XYLD_REG_INT_STS_LD_SEG_MSG_ERR                                                                    (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
+  #define XYLD_REG_INT_STS_LD_SEG_MSG_ERR_SHIFT                                                              2
+  #define XYLD_REG_INT_STS_LD_TID_MINI_CACHE_ERR                                                             (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
+  #define XYLD_REG_INT_STS_LD_TID_MINI_CACHE_ERR_SHIFT                                                       3
+  #define XYLD_REG_INT_STS_LD_CID_MINI_CACHE_ERR                                                             (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
+  #define XYLD_REG_INT_STS_LD_CID_MINI_CACHE_ERR_SHIFT                                                       4
+  #define XYLD_REG_INT_STS_LD_LONG_MESSAGE                                                                   (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
+  #define XYLD_REG_INT_STS_LD_LONG_MESSAGE_SHIFT                                                             5
+#define XYLD_REG_INT_MASK                                                                                    0x4c0184UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define XYLD_REG_INT_MASK_ADDRESS_ERROR                                                                    (0x1<<0) // This bit masks, when set, the Interrupt bit: XYLD_REG_INT_STS.ADDRESS_ERROR .
+  #define XYLD_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                              0
+  #define XYLD_REG_INT_MASK_LD_HDR_ERR                                                                       (0x1<<1) // This bit masks, when set, the Interrupt bit: XYLD_REG_INT_STS.LD_HDR_ERR .
+  #define XYLD_REG_INT_MASK_LD_HDR_ERR_SHIFT                                                                 1
+  #define XYLD_REG_INT_MASK_LD_SEG_MSG_ERR                                                                   (0x1<<2) // This bit masks, when set, the Interrupt bit: XYLD_REG_INT_STS.LD_SEG_MSG_ERR .
+  #define XYLD_REG_INT_MASK_LD_SEG_MSG_ERR_SHIFT                                                             2
+  #define XYLD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR                                                            (0x1<<3) // This bit masks, when set, the Interrupt bit: XYLD_REG_INT_STS.LD_TID_MINI_CACHE_ERR .
+  #define XYLD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR_SHIFT                                                      3
+  #define XYLD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR                                                            (0x1<<4) // This bit masks, when set, the Interrupt bit: XYLD_REG_INT_STS.LD_CID_MINI_CACHE_ERR .
+  #define XYLD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR_SHIFT                                                      4
+  #define XYLD_REG_INT_MASK_LD_LONG_MESSAGE                                                                  (0x1<<5) // This bit masks, when set, the Interrupt bit: XYLD_REG_INT_STS.LD_LONG_MESSAGE .
+  #define XYLD_REG_INT_MASK_LD_LONG_MESSAGE_SHIFT                                                            5
+#define XYLD_REG_INT_STS_WR                                                                                  0x4c0188UL //Access:WR   DataWidth:0x6    // Multi Field Register.
+  #define XYLD_REG_INT_STS_WR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define XYLD_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                            0
+  #define XYLD_REG_INT_STS_WR_LD_HDR_ERR                                                                     (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
+  #define XYLD_REG_INT_STS_WR_LD_HDR_ERR_SHIFT                                                               1
+  #define XYLD_REG_INT_STS_WR_LD_SEG_MSG_ERR                                                                 (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
+  #define XYLD_REG_INT_STS_WR_LD_SEG_MSG_ERR_SHIFT                                                           2
+  #define XYLD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR                                                          (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
+  #define XYLD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR_SHIFT                                                    3
+  #define XYLD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR                                                          (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
+  #define XYLD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR_SHIFT                                                    4
+  #define XYLD_REG_INT_STS_WR_LD_LONG_MESSAGE                                                                (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
+  #define XYLD_REG_INT_STS_WR_LD_LONG_MESSAGE_SHIFT                                                          5
+#define XYLD_REG_INT_STS_CLR                                                                                 0x4c018cUL //Access:RC   DataWidth:0x6    // Multi Field Register.
+  #define XYLD_REG_INT_STS_CLR_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define XYLD_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                           0
+  #define XYLD_REG_INT_STS_CLR_LD_HDR_ERR                                                                    (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
+  #define XYLD_REG_INT_STS_CLR_LD_HDR_ERR_SHIFT                                                              1
+  #define XYLD_REG_INT_STS_CLR_LD_SEG_MSG_ERR                                                                (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
+  #define XYLD_REG_INT_STS_CLR_LD_SEG_MSG_ERR_SHIFT                                                          2
+  #define XYLD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR                                                         (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
+  #define XYLD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR_SHIFT                                                   3
+  #define XYLD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR                                                         (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
+  #define XYLD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR_SHIFT                                                   4
+  #define XYLD_REG_INT_STS_CLR_LD_LONG_MESSAGE                                                               (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
+  #define XYLD_REG_INT_STS_CLR_LD_LONG_MESSAGE_SHIFT                                                         5
+#define XYLD_REG_PRTY_MASK_H_0_BB_K2                                                                         0x4c0204UL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define XYLD_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_BB_K2                                                   (0x1<<0) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT .
+  #define XYLD_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_BB_K2_SHIFT                                             0
+  #define XYLD_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_BB_K2                                                   (0x1<<1) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM006_I_ECC_RF_INT .
+  #define XYLD_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_BB_K2_SHIFT                                             1
+  #define XYLD_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                     (0x1<<2) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define XYLD_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                               2
+  #define XYLD_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                     (0x1<<3) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define XYLD_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                               3
+  #define XYLD_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2                                                     (0x1<<4) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define XYLD_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2_SHIFT                                               4
+  #define XYLD_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2                                                     (0x1<<5) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define XYLD_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2_SHIFT                                               5
+  #define XYLD_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                     (0x1<<6) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define XYLD_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                               6
+  #define XYLD_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2                                                     (0x1<<7) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define XYLD_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT                                               7
+  #define XYLD_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2                                                     (0x1<<8) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define XYLD_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2_SHIFT                                               8
+#define XYLD_REG_MEM_ECC_ENABLE_0_BB_K2                                                                      0x4c0210UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define XYLD_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_BB_K2                                                    (0x1<<0) // Enable ECC for memory ecc instance xyld.i_msgq_ram.i_ecc in module xyld_i_msgq_ram_1
+  #define XYLD_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_BB_K2_SHIFT                                              0
+  #define XYLD_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN_BB_K2                                                    (0x1<<1) // Enable ECC for memory ecc instance xyld.i_pci_rsep_buf_ram.i_ecc in module xyld_i_pci_rsep_buf_ram
+  #define XYLD_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN_BB_K2_SHIFT                                              1
+#define XYLD_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                 0x4c0214UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define XYLD_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_BB_K2                                             (0x1<<0) // Set parity only for memory ecc instance xyld.i_msgq_ram.i_ecc in module xyld_i_msgq_ram_1
+  #define XYLD_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_BB_K2_SHIFT                                       0
+  #define XYLD_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY_BB_K2                                             (0x1<<1) // Set parity only for memory ecc instance xyld.i_pci_rsep_buf_ram.i_ecc in module xyld_i_pci_rsep_buf_ram
+  #define XYLD_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY_BB_K2_SHIFT                                       1
+#define XYLD_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                             0x4c0218UL //Access:RC   DataWidth:0x2    // Multi Field Register.
+  #define XYLD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_BB_K2                                      (0x1<<0) // Record if a correctable error occurred on memory ecc instance xyld.i_msgq_ram.i_ecc in module xyld_i_msgq_ram_1
+  #define XYLD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_BB_K2_SHIFT                                0
+  #define XYLD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT_BB_K2                                      (0x1<<1) // Record if a correctable error occurred on memory ecc instance xyld.i_pci_rsep_buf_ram.i_ecc in module xyld_i_pci_rsep_buf_ram
+  #define XYLD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT_BB_K2_SHIFT                                1
+#define XYLD_REG_MEM_ECC_EVENTS_BB_K2                                                                        0x4c021cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define XYLD_REG_DESC_QUEUE_Q0                                                                               0x4c0400UL //Access:WB   DataWidth:0x23   // Descriptor FIFO queue0 - Debug access.
+#define XYLD_REG_DESC_QUEUE_Q0_SIZE                                                                          48
+#define XYLD_REG_DESC_QUEUE_Q1                                                                               0x4c0800UL //Access:WB   DataWidth:0x23   // Descriptor FIFO queue1 - Debug access.
+#define XYLD_REG_DESC_QUEUE_Q1_SIZE                                                                          48
+#define XYLD_REG_L2MA_AGGR_CONFIG1_E5                                                                        0x4c0900UL //Access:RW   DataWidth:0x13   // Multi Field Register.
+  #define XYLD_REG_L2MA_AGGR_CONFIG1_L2MA_EN_E5                                                              (0x1<<0) // Enables L2 message aggregation
+  #define XYLD_REG_L2MA_AGGR_CONFIG1_L2MA_EN_E5_SHIFT                                                        0
+  #define XYLD_REG_L2MA_AGGR_CONFIG1_IGNORE_CM_AGG_MSG_E5                                                    (0x1<<1) // indicates not to perform the aggregation logic if there is no L2MA command in the message (there is no L2MA command if DstStormFlg is reset OR ErrFlg is set). If this configuration is reset, messages without L2MA command are treated like messages with L2MA command where EnL2MA flag in the command is reset (i.e. they break existing aggregation).
+  #define XYLD_REG_L2MA_AGGR_CONFIG1_IGNORE_CM_AGG_MSG_E5_SHIFT                                              1
+  #define XYLD_REG_L2MA_AGGR_CONFIG1_BACK_2_BACK_E5                                                          (0x1<<2) // defines that only back-to-back aggregation is allowed
+  #define XYLD_REG_L2MA_AGGR_CONFIG1_BACK_2_BACK_E5_SHIFT                                                    2
+  #define XYLD_REG_L2MA_AGGR_CONFIG1_MIN_QUEUE_OCC_E5                                                        (0xff<<3) // the minimal queue occupancy below which new aggregations are not created
+  #define XYLD_REG_L2MA_AGGR_CONFIG1_MIN_QUEUE_OCC_E5_SHIFT                                                  3
+  #define XYLD_REG_L2MA_AGGR_CONFIG1_MAX_L2MA_DIFF_E5                                                        (0xff<<11) // the maximal difference between the serial number of the parent message and the serial number of its child message
+  #define XYLD_REG_L2MA_AGGR_CONFIG1_MAX_L2MA_DIFF_E5_SHIFT                                                  11
+#define XYLD_REG_L2MA_AGGR_CONFIG2_E5                                                                        0x4c0904UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define XYLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_0_E5                                                     (0x3f<<0) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
+  #define XYLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_0_E5_SHIFT                                               0
+  #define XYLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_1_E5                                                     (0x3f<<6) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
+  #define XYLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_1_E5_SHIFT                                               6
+  #define XYLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_2_E5                                                     (0x3f<<12) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
+  #define XYLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_2_E5_SHIFT                                               12
+  #define XYLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_3_E5                                                     (0x3f<<18) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
+  #define XYLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_3_E5_SHIFT                                               18
+#define XYLD_REG_L2MA_SAME_OFFSET_SET_0_E5                                                                   0x4c0908UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_00_E5                                                       (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_00_E5_SHIFT                                                 0
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_01_E5                                                       (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_01_E5_SHIFT                                                 8
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_02_E5                                                       (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_02_E5_SHIFT                                                 16
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_03_E5                                                       (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_03_E5_SHIFT                                                 24
+#define XYLD_REG_L2MA_SAME_OFFSET_SET_1_E5                                                                   0x4c090cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_10_E5                                                       (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_10_E5_SHIFT                                                 0
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_11_E5                                                       (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_11_E5_SHIFT                                                 8
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_12_E5                                                       (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_12_E5_SHIFT                                                 16
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_13_E5                                                       (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_13_E5_SHIFT                                                 24
+#define XYLD_REG_L2MA_SAME_OFFSET_SET_2_E5                                                                   0x4c0910UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_20_E5                                                       (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_20_E5_SHIFT                                                 0
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_21_E5                                                       (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_21_E5_SHIFT                                                 8
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_22_E5                                                       (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_22_E5_SHIFT                                                 16
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_23_E5                                                       (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_23_E5_SHIFT                                                 24
+#define XYLD_REG_L2MA_SAME_OFFSET_SET_3_E5                                                                   0x4c0914UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_30_E5                                                       (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_30_E5_SHIFT                                                 0
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_31_E5                                                       (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_31_E5_SHIFT                                                 8
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_32_E5                                                       (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_32_E5_SHIFT                                                 16
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_33_E5                                                       (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
+  #define XYLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_33_E5_SHIFT                                                 24
+#define XYLD_REG_L2MA_SAME_LEN_SET_0_1_E5                                                                    0x4c0918UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define XYLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_00_E5                                                           (0xf<<0) // length in 32b units from the same 00 .
+  #define XYLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_00_E5_SHIFT                                                     0
+  #define XYLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_01_E5                                                           (0xf<<4) // length in 32b units from the same 01 .
+  #define XYLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_01_E5_SHIFT                                                     4
+  #define XYLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_02_E5                                                           (0xf<<8) // length in 32b units from the same 02 .
+  #define XYLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_02_E5_SHIFT                                                     8
+  #define XYLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_03_E5                                                           (0xf<<12) // length in 32b units from the same 03 .
+  #define XYLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_03_E5_SHIFT                                                     12
+  #define XYLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_10_E5                                                           (0xf<<16) // length in 32b units from the same 10 .
+  #define XYLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_10_E5_SHIFT                                                     16
+  #define XYLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_11_E5                                                           (0xf<<20) // length in 32b units from the same 11 .
+  #define XYLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_11_E5_SHIFT                                                     20
+  #define XYLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_12_E5                                                           (0xf<<24) // length in 32b units from the same 12 .
+  #define XYLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_12_E5_SHIFT                                                     24
+  #define XYLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_13_E5                                                           (0xf<<28) // length in 32b units from the same 13 .
+  #define XYLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_13_E5_SHIFT                                                     28
+#define XYLD_REG_L2MA_SAME_LEN_SET_2_3_E5                                                                    0x4c091cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define XYLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_20_E5                                                           (0xf<<0) // length in 32b units from the same 20 .
+  #define XYLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_20_E5_SHIFT                                                     0
+  #define XYLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_21_E5                                                           (0xf<<4) // length in 32b units from the same 21 .
+  #define XYLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_21_E5_SHIFT                                                     4
+  #define XYLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_22_E5                                                           (0xf<<8) // length in 32b units from the same 22 .
+  #define XYLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_22_E5_SHIFT                                                     8
+  #define XYLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_23_E5                                                           (0xf<<12) // length in 32b units from the same 23 .
+  #define XYLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_23_E5_SHIFT                                                     12
+  #define XYLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_30_E5                                                           (0xf<<16) // length in 32b units from the same 30 .
+  #define XYLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_30_E5_SHIFT                                                     16
+  #define XYLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_31_E5                                                           (0xf<<20) // length in 32b units from the same 31 .
+  #define XYLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_31_E5_SHIFT                                                     20
+  #define XYLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_32_E5                                                           (0xf<<24) // length in 32b units from the same 32 .
+  #define XYLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_32_E5_SHIFT                                                     24
+  #define XYLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_33_E5                                                           (0xf<<28) // length in 32b units from the same 33 .
+  #define XYLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_33_E5_SHIFT                                                     28
+#define XYLD_REG_L2MA_SAME_MASK_SET_0_E5                                                                     0x4c0920UL //Access:RW   DataWidth:0x20   // bit-mask on the selected 32B same 0 parameters .
+#define XYLD_REG_L2MA_SAME_MASK_SET_1_E5                                                                     0x4c0924UL //Access:RW   DataWidth:0x20   // bit-mask on the selected 32B same 1 parameters .
+#define XYLD_REG_L2MA_SAME_MASK_SET_2_E5                                                                     0x4c0928UL //Access:RW   DataWidth:0x20   // bit-mask on the selected 32B same 2 parameters .
+#define XYLD_REG_L2MA_SAME_MASK_SET_3_E5                                                                     0x4c092cUL //Access:RW   DataWidth:0x20   // bit-mask on the selected 32B same 3 parameters .
+#define XYLD_REG_L2MA_DUP_OFFSET_SET_0_E5                                                                    0x4c0930UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_00_E5                                                    (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_00_E5_SHIFT                                              0
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_01_E5                                                    (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_01_E5_SHIFT                                              8
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_02_E5                                                    (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_02_E5_SHIFT                                              16
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_03_E5                                                    (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_03_E5_SHIFT                                              24
+#define XYLD_REG_L2MA_DUP_OFFSET_SET_1_E5                                                                    0x4c0934UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_10_E5                                                    (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_10_E5_SHIFT                                              0
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_11_E5                                                    (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_11_E5_SHIFT                                              8
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_12_E5                                                    (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_12_E5_SHIFT                                              16
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_13_E5                                                    (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_13_E5_SHIFT                                              24
+#define XYLD_REG_L2MA_DUP_OFFSET_SET_2_E5                                                                    0x4c0938UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_20_E5                                                    (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_20_E5_SHIFT                                              0
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_21_E5                                                    (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_21_E5_SHIFT                                              8
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_22_E5                                                    (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_22_E5_SHIFT                                              16
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_23_E5                                                    (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_23_E5_SHIFT                                              24
+#define XYLD_REG_L2MA_DUP_OFFSET_SET_3_E5                                                                    0x4c093cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_30_E5                                                    (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_30_E5_SHIFT                                              0
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_31_E5                                                    (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_31_E5_SHIFT                                              8
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_32_E5                                                    (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_32_E5_SHIFT                                              16
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_33_E5                                                    (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
+  #define XYLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_33_E5_SHIFT                                              24
+#define XYLD_REG_L2MA_DUP_LEN_SET_0_E5                                                                       0x4c0940UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define XYLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_00_E5                                                          (0x3f<<0) // length in 32b units from the dup 00 .
+  #define XYLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_00_E5_SHIFT                                                    0
+  #define XYLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_01_E5                                                          (0x3f<<6) // length in 32b units from the dup 01 .
+  #define XYLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_01_E5_SHIFT                                                    6
+  #define XYLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_02_E5                                                          (0x3f<<12) // length in 32b units from the dup 02 .
+  #define XYLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_02_E5_SHIFT                                                    12
+  #define XYLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_03_E5                                                          (0x3f<<18) // length in 32b units from the dup 03 .
+  #define XYLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_03_E5_SHIFT                                                    18
+#define XYLD_REG_L2MA_DUP_LEN_SET_1_E5                                                                       0x4c0944UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define XYLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_10_E5                                                          (0x3f<<0) // length in 32b units from the dup 10 .
+  #define XYLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_10_E5_SHIFT                                                    0
+  #define XYLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_11_E5                                                          (0x3f<<6) // length in 32b units from the dup 11 .
+  #define XYLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_11_E5_SHIFT                                                    6
+  #define XYLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_12_E5                                                          (0x3f<<12) // length in 32b units from the dup 12 .
+  #define XYLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_12_E5_SHIFT                                                    12
+  #define XYLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_13_E5                                                          (0x3f<<18) // length in 32b units from the dup 13 .
+  #define XYLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_13_E5_SHIFT                                                    18
+#define XYLD_REG_L2MA_DUP_LEN_SET_2_E5                                                                       0x4c0948UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define XYLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_20_E5                                                          (0x3f<<0) // length in 32b units from the dup 20 .
+  #define XYLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_20_E5_SHIFT                                                    0
+  #define XYLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_21_E5                                                          (0x3f<<6) // length in 32b units from the dup 21 .
+  #define XYLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_21_E5_SHIFT                                                    6
+  #define XYLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_22_E5                                                          (0x3f<<12) // length in 32b units from the dup 22 .
+  #define XYLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_22_E5_SHIFT                                                    12
+  #define XYLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_23_E5                                                          (0x3f<<18) // length in 32b units from the dup 23 .
+  #define XYLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_23_E5_SHIFT                                                    18
+#define XYLD_REG_L2MA_DUP_LEN_SET_3_E5                                                                       0x4c094cUL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define XYLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_30_E5                                                          (0x3f<<0) // length in 32b units from the dup 30 .
+  #define XYLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_30_E5_SHIFT                                                    0
+  #define XYLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_31_E5                                                          (0x3f<<6) // length in 32b units from the dup 31 .
+  #define XYLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_31_E5_SHIFT                                                    6
+  #define XYLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_32_E5                                                          (0x3f<<12) // length in 32b units from the dup 32 .
+  #define XYLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_32_E5_SHIFT                                                    12
+  #define XYLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_33_E5                                                          (0x3f<<18) // length in 32b units from the dup 33 .
+  #define XYLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_33_E5_SHIFT                                                    18
+#define XYLD_REG_L2MA_FLOW_ID_E5                                                                             0x4c0950UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define XYLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_0_E5                                                         (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
+  #define XYLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_0_E5_SHIFT                                                   0
+  #define XYLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_1_E5                                                         (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
+  #define XYLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_1_E5_SHIFT                                                   1
+  #define XYLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_2_E5                                                         (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
+  #define XYLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_2_E5_SHIFT                                                   2
+  #define XYLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_3_E5                                                         (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
+  #define XYLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_3_E5_SHIFT                                                   3
+  #define XYLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_0_E5                                                          (0x1f<<4) // offset of the flow-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of the incoming message (i.e. max value is 23). This parameter is NA if FlowIdInclude is reset. For set 0 .
+  #define XYLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_0_E5_SHIFT                                                    4
+  #define XYLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_1_E5                                                          (0x1f<<9) // offset of the flow-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of the incoming message (i.e. max value is 23). This parameter is NA if FlowIdInclude is reset. For set 1 .
+  #define XYLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_1_E5_SHIFT                                                    9
+  #define XYLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_2_E5                                                          (0x1f<<14) // offset of the flow-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of the incoming message (i.e. max value is 23). This parameter is NA if FlowIdInclude is reset. For set 2 .
+  #define XYLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_2_E5_SHIFT                                                    14
+  #define XYLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_3_E5                                                          (0x1f<<19) // offset of the flow-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of the incoming message (i.e. max value is 23). This parameter is NA if FlowIdInclude is reset. For set 3 .
+  #define XYLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_3_E5_SHIFT                                                    19
+#define XYLD_REG_L2MA_SN_OFFSET_E5                                                                           0x4c0954UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define XYLD_REG_L2MA_SN_OFFSET_SN_OFFSET_0_E5                                                             (0xff<<0) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 0.
+  #define XYLD_REG_L2MA_SN_OFFSET_SN_OFFSET_0_E5_SHIFT                                                       0
+  #define XYLD_REG_L2MA_SN_OFFSET_SN_OFFSET_1_E5                                                             (0xff<<8) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 1.
+  #define XYLD_REG_L2MA_SN_OFFSET_SN_OFFSET_1_E5_SHIFT                                                       8
+  #define XYLD_REG_L2MA_SN_OFFSET_SN_OFFSET_2_E5                                                             (0xff<<16) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 2.
+  #define XYLD_REG_L2MA_SN_OFFSET_SN_OFFSET_2_E5_SHIFT                                                       16
+  #define XYLD_REG_L2MA_SN_OFFSET_SN_OFFSET_3_E5                                                             (0xff<<24) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 3.
+  #define XYLD_REG_L2MA_SN_OFFSET_SN_OFFSET_3_E5_SHIFT                                                       24
+#define XYLD_REG_L2MA_MAX_L2MA_CHILD_E5                                                                      0x4c0958UL //Access:RW   DataWidth:0x10   // Multi Field Register.
+  #define XYLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_0_E5                                                         (0xf<<0) // the maximal number of children in a specific aggregation. for set 0.
+  #define XYLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_0_E5_SHIFT                                                   0
+  #define XYLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_1_E5                                                         (0xf<<4) // the maximal number of children in a specific aggregation. for set 1.
+  #define XYLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_1_E5_SHIFT                                                   4
+  #define XYLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_2_E5                                                         (0xf<<8) // the maximal number of children in a specific aggregation. for set 2.
+  #define XYLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_2_E5_SHIFT                                                   8
+  #define XYLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_3_E5                                                         (0xf<<12) // the maximal number of children in a specific aggregation. for set 3.
+  #define XYLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_3_E5_SHIFT                                                   12
+#define XYLD_REG_L2MA_INC_L2MA_EVENT_ID_E5                                                                   0x4c095cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define XYLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_0_E5                                                  (0xff<<0) // The value by which to increment the event-ID in case of successful aggregation. for set 0.
+  #define XYLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_0_E5_SHIFT                                            0
+  #define XYLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_1_E5                                                  (0xff<<8) // The value by which to increment the event-ID in case of successful aggregation. for set 1.
+  #define XYLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_1_E5_SHIFT                                            8
+  #define XYLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_2_E5                                                  (0xff<<16) // The value by which to increment the event-ID in case of successful aggregation. for set 2.
+  #define XYLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_2_E5_SHIFT                                            16
+  #define XYLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_3_E5                                                  (0xff<<24) // The value by which to increment the event-ID in case of successful aggregation. for set 3.
+  #define XYLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_3_E5_SHIFT                                            24
+#define XYLD_REG_LD_MAX_MSG_SIZE_E5                                                                          0x4c0960UL //Access:RW   DataWidth:0x4    // maximum loader size in 256 bit words
+#define XYLD_REG_DBG_SELECT                                                                                  0x4c1600UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define XYLD_REG_DBG_DWORD_ENABLE                                                                            0x4c1604UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define XYLD_REG_DBG_SHIFT                                                                                   0x4c1608UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define XYLD_REG_DBG_FORCE_VALID                                                                             0x4c160cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define XYLD_REG_DBG_FORCE_FRAME                                                                             0x4c1610UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define XYLD_REG_DBG_OUT_DATA                                                                                0x4c1620UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define XYLD_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define XYLD_REG_DBG_OUT_VALID                                                                               0x4c1640UL //Access:R    DataWidth:0x4    // Dbgmux output valid
+#define XYLD_REG_DBG_OUT_FRAME                                                                               0x4c1644UL //Access:R    DataWidth:0x4    // Dbgmux output frame
+#define XYLD_REG_FIC_INPUT_FIFO                                                                              0x4c2000UL //Access:WB   DataWidth:0x80   // Access to input FIC FIFO
+#define XYLD_REG_FIC_INPUT_FIFO_SIZE                                                                         176
+#define XYLD_REG_QUEUE_MSG_MEM                                                                               0x4c4000UL //Access:WB   DataWidth:0x80   // Debug access to The message queue memory.
+#define XYLD_REG_QUEUE_MSG_MEM_SIZE                                                                          2208
+#define YULD_REG_SCBD_STRICT_PRIO_BB_K2                                                                      0x4c8000UL //Access:RW   DataWidth:0x4    // Each bit indicates if the current queue ahs a strict prioirty; 1: The current queue has strict prority; 0: The current queue is part of the WRR scheme.
+#define YULD_REG_SCBD_WRR_WEIGHT_Q0_BB_K2                                                                    0x4c8004UL //Access:RW   DataWidth:0x2    // The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_strict_prio reg.
+#define YULD_REG_SCBD_WRR_WEIGHT_Q1_BB_K2                                                                    0x4c8008UL //Access:RW   DataWidth:0x2    // The weight of queue 1 at the WRR arbiteration, in case its bit is reset at scbd_strict_prio reg.
+#define YULD_REG_FOCI_FOC_CREDITS_BB_K2                                                                      0x4c800cUL //Access:RW   DataWidth:0x6    // Initial credit of the FOC itnerface.
+#define YULD_REG_BYPASS_QID_BB_K2                                                                            0x4c8010UL //Access:RW   DataWidth:0x2    // Selects the queue to which bypass messages will be steered.
+#define YULD_REG_TCFC_LOAD_MINI_CACHE_EN_BB_K2                                                               0x4c8014UL //Access:RW   DataWidth:0x1    // Allowes the TID/CID mini cache feature.
+#define YULD_REG_CCFC_LOAD_MINI_CACHE_EN_BB_K2                                                               0x4c8018UL //Access:RW   DataWidth:0x1    // Allowes the TID/CID mini cache feature.
+#define YULD_REG_ECO_RESERVED_BB_K2                                                                          0x4c801cUL //Access:RW   DataWidth:0x8    // Allowes future ECO's
+#define YULD_REG_CID_REQ_CREDITS_BB_K2                                                                       0x4c8020UL //Access:RW   DataWidth:0x6    // Max credits value for the load cid request interface.
+#define YULD_REG_TID_REQ_CREDITS_BB_K2                                                                       0x4c8024UL //Access:RW   DataWidth:0x6    // Max credits value for the load tid request interface.
+#define YULD_REG_TID_REMAIN_CREDITS_BB_K2                                                                    0x4c8028UL //Access:R    DataWidth:0x6    // Remaining credits for the tid interface
+#define YULD_REG_TID_MSG_STAT_BB_K2                                                                          0x4c802cUL //Access:RC   DataWidth:0x20   // Statistics counter of TID requests
+#define YULD_REG_CID_REMAIN_CREDITS_BB_K2                                                                    0x4c8030UL //Access:R    DataWidth:0x6    // Remaining credits for the cid interface
+#define YULD_REG_CID_MSG_STAT_BB_K2                                                                          0x4c8034UL //Access:RC   DataWidth:0x20   // Statistics counter of CID requests
+#define YULD_REG_EXT_EV_1_STAT_BB_K2                                                                         0x4c8038UL //Access:RC   DataWidth:0x20   // Statistics counter of message pending to external event 1
+#define YULD_REG_EXT_EV_2_STAT_BB_K2                                                                         0x4c803cUL //Access:RC   DataWidth:0x20   // Statistics counter of message pending to external event 2
+#define YULD_REG_EXT_EV_3_STAT_BB_K2                                                                         0x4c8040UL //Access:RC   DataWidth:0x20   // Statistics counter of message pending to external event 3
+#define YULD_REG_EXT_EV_4_STAT_BB_K2                                                                         0x4c8044UL //Access:RC   DataWidth:0x20   // Statistics counter of message pending to external event 0
+#define YULD_REG_EXT_EV_5_STAT_BB_K2                                                                         0x4c8048UL //Access:RC   DataWidth:0x20   // Statistics counter of message pending to external event 0
+#define YULD_REG_PENDING_MSG_TO_EXT_EV_1_CTR_BB_K2                                                           0x4c804cUL //Access:R    DataWidth:0x9    // Counts the number of messages currently pending to external event 1
+#define YULD_REG_PENDING_MSG_TO_EXT_EV_2_CTR_BB_K2                                                           0x4c8050UL //Access:R    DataWidth:0x9    // Counts the number of messages currently pending to external event 2
+#define YULD_REG_PENDING_MSG_TO_EXT_EV_3_CTR_BB_K2                                                           0x4c8054UL //Access:R    DataWidth:0x9    // Counts the number of messages currently pending to external event 3
+#define YULD_REG_PENDING_MSG_TO_EXT_EV_4_CTR_BB_K2                                                           0x4c8058UL //Access:R    DataWidth:0x9    // Counts the number of messages currently pending to external event 4
+#define YULD_REG_PENDING_MSG_TO_EXT_EV_5_CTR_BB_K2                                                           0x4c805cUL //Access:R    DataWidth:0x9    // Counts the number of messages currently pending to external event 5
+#define YULD_REG_FOC_REMAIN_CREDITS_BB_K2                                                                    0x4c8060UL //Access:R    DataWidth:0x6    // Remaining credits on the FOC interface
+#define YULD_REG_LD_CID_MINICACHE_LOG_BB_K2                                                                  0x4c8064UL //Access:R    DataWidth:0x20   // Logging in case of minicache failure.bits 31:0 CID Valid only if bit 13 in ld_cid_minicache_resp_log is set
+#define YULD_REG_LD_TID_MINICACHE_LOG_BB_K2                                                                  0x4c8068UL //Access:R    DataWidth:0x20   // Logging in case of minicache failure.bits 31:0 TID Valid only if bit 13 in ld_tid_minicache_resp_log is set
+#define YULD_REG_LD_CID_MINICACHE_RESP_LOG_BB_K2                                                             0x4c806cUL //Access:R    DataWidth:0xe    // Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_cid_minicache_log register is valid
+#define YULD_REG_LD_TID_MINICACHE_RESP_LOG_BB_K2                                                             0x4c8070UL //Access:R    DataWidth:0xe    // Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_tid_minicache_log register is valid
+#define YULD_REG_LD_HDR_LOG_BB_K2                                                                            0x4c8074UL //Access:R    DataWidth:0x4    // Logging of the problem which caused the ld_hdr_err interrupt. Bit 0: ilegal flags combination.
+#define YULD_REG_LD_HDR_1ST_CYC_31_0_BB_K2                                                                   0x4c8078UL //Access:R    DataWidth:0x20   // Logging of the first loader header cycle - for the case ld_hdr_err is raised.
+#define YULD_REG_LD_HDR_1ST_CYC_63_32_BB_K2                                                                  0x4c807cUL //Access:R    DataWidth:0x20   // Logging of the first loader header cycle - for the case ld_hdr_err is raised.
+#define YULD_REG_LD_HDR_1ST_CYC_95_64_BB_K2                                                                  0x4c8080UL //Access:R    DataWidth:0x20   // Logging of the first loader header cycle - for the case ld_hdr_err is raised.
+#define YULD_REG_LD_HDR_1ST_CYC_127_96_BB_K2                                                                 0x4c8084UL //Access:R    DataWidth:0x20   // Logging of the first loader header cycle - for the case ld_hdr_err is raised.
+#define YULD_REG_LD_HDR_2ND_CYC_31_0_BB_K2                                                                   0x4c8088UL //Access:R    DataWidth:0x20   // Logging of the second loader header cycle - for the case ld_hdr_err is raised.
+#define YULD_REG_LD_HDR_2ND_CYC_63_32_BB_K2                                                                  0x4c808cUL //Access:R    DataWidth:0x20   // Logging of the second loader header cycle - for the case ld_hdr_err is raised.
+#define YULD_REG_LD_HDR_2ND_CYC_95_64_BB_K2                                                                  0x4c8090UL //Access:R    DataWidth:0x20   // Logging of the second loader header cycle - for the case ld_hdr_err is raised.
+#define YULD_REG_LD_HDR_2ND_CYC_127_96_BB_K2                                                                 0x4c8094UL //Access:R    DataWidth:0x20   // Logging of the second loader header cycle - for the case ld_hdr_err is raised.
+#define YULD_REG_CM_HDR_31_0_BB_K2                                                                           0x4c8098UL //Access:R    DataWidth:0x20   // Logging of the cm header cycle - for the case ld_hdr_err is raised.
+#define YULD_REG_CM_HDR_63_32_BB_K2                                                                          0x4c809cUL //Access:R    DataWidth:0x20   // Logging of the cm header cycle - for the case ld_hdr_err is raised.
+#define YULD_REG_CM_HDR_95_64_BB_K2                                                                          0x4c80a0UL //Access:R    DataWidth:0x20   // Logging of the cm header cycle - for the case ld_hdr_err is raised.
+#define YULD_REG_CM_HDR_127_96_BB_K2                                                                         0x4c80a4UL //Access:R    DataWidth:0x20   // Logging of the cm header cycle - for the case ld_hdr_err is raised.
+#define YULD_REG_LD_HDR_CLR_BB_K2                                                                            0x4c80a8UL //Access:W    DataWidth:0x1    // Writing to this register clears hdr registers and enables logging new error details.
+#define YULD_REG_STAT_FIC_MSG_BB_K2                                                                          0x4c80acUL //Access:RC   DataWidth:0x20   // Number of FIC messages sent to the loader
+#define YULD_REG_DBG_PENDING_CCFC_REQ_BB_K2                                                                  0x4c80b0UL //Access:R    DataWidth:0x5    // number of CCFC requests wating for responses
+#define YULD_REG_DBG_PENDING_TCFC_REQ_BB_K2                                                                  0x4c80b4UL //Access:R    DataWidth:0x5    // number of TCFC requests wating for responses
+#define YULD_REG_LEN_ERR_LOG_1_BB_K2                                                                         0x4c80b8UL //Access:R    DataWidth:0x10   // Logging register for long message error: bit 0-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SGE fetch; bit 4- Message with BRB fetch; bits 5:6- QID; bits 7-RSV; bits 8-15 message CM length.
+#define YULD_REG_LEN_ERR_LOG_2_BB_K2                                                                         0x4c80bcUL //Access:R    DataWidth:0x20   // Logging register for long message error: bit 0:3 Segment message header length; 4:7 RSV;8:15 current length out of the segment message length array; 16:23 PCI response len (including BD and SGE fetches); 24:31 BRB
+#define YULD_REG_LEN_ERR_LOG_CLR_BB_K2                                                                       0x4c80c0UL //Access:W    DataWidth:0x1    // Writing to this register clears len err logging registers and enables logging new error details.
+#define YULD_REG_LEN_ERR_LOG_V_BB_K2                                                                         0x4c80c4UL //Access:R    DataWidth:0x1    // Indicates that the data at the len_err logging registers is valid.
+#define YULD_REG_INT_STS_BB_K2                                                                               0x4c8180UL //Access:R    DataWidth:0x6    // Multi Field Register.
+  #define YULD_REG_INT_STS_ADDRESS_ERROR_BB_K2                                                               (0x1<<0) // Signals an unknown address to the rf module.
+  #define YULD_REG_INT_STS_ADDRESS_ERROR_BB_K2_SHIFT                                                         0
+  #define YULD_REG_INT_STS_LD_HDR_ERR_BB_K2                                                                  (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
+  #define YULD_REG_INT_STS_LD_HDR_ERR_BB_K2_SHIFT                                                            1
+  #define YULD_REG_INT_STS_LD_SEG_MSG_ERR_BB_K2                                                              (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
+  #define YULD_REG_INT_STS_LD_SEG_MSG_ERR_BB_K2_SHIFT                                                        2
+  #define YULD_REG_INT_STS_LD_TID_MINI_CACHE_ERR_BB_K2                                                       (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
+  #define YULD_REG_INT_STS_LD_TID_MINI_CACHE_ERR_BB_K2_SHIFT                                                 3
+  #define YULD_REG_INT_STS_LD_CID_MINI_CACHE_ERR_BB_K2                                                       (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
+  #define YULD_REG_INT_STS_LD_CID_MINI_CACHE_ERR_BB_K2_SHIFT                                                 4
+  #define YULD_REG_INT_STS_LD_LONG_MESSAGE_BB_K2                                                             (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
+  #define YULD_REG_INT_STS_LD_LONG_MESSAGE_BB_K2_SHIFT                                                       5
+#define YULD_REG_INT_MASK_BB_K2                                                                              0x4c8184UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define YULD_REG_INT_MASK_ADDRESS_ERROR_BB_K2                                                              (0x1<<0) // This bit masks, when set, the Interrupt bit: YULD_REG_INT_STS.ADDRESS_ERROR .
+  #define YULD_REG_INT_MASK_ADDRESS_ERROR_BB_K2_SHIFT                                                        0
+  #define YULD_REG_INT_MASK_LD_HDR_ERR_BB_K2                                                                 (0x1<<1) // This bit masks, when set, the Interrupt bit: YULD_REG_INT_STS.LD_HDR_ERR .
+  #define YULD_REG_INT_MASK_LD_HDR_ERR_BB_K2_SHIFT                                                           1
+  #define YULD_REG_INT_MASK_LD_SEG_MSG_ERR_BB_K2                                                             (0x1<<2) // This bit masks, when set, the Interrupt bit: YULD_REG_INT_STS.LD_SEG_MSG_ERR .
+  #define YULD_REG_INT_MASK_LD_SEG_MSG_ERR_BB_K2_SHIFT                                                       2
+  #define YULD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR_BB_K2                                                      (0x1<<3) // This bit masks, when set, the Interrupt bit: YULD_REG_INT_STS.LD_TID_MINI_CACHE_ERR .
+  #define YULD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR_BB_K2_SHIFT                                                3
+  #define YULD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR_BB_K2                                                      (0x1<<4) // This bit masks, when set, the Interrupt bit: YULD_REG_INT_STS.LD_CID_MINI_CACHE_ERR .
+  #define YULD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR_BB_K2_SHIFT                                                4
+  #define YULD_REG_INT_MASK_LD_LONG_MESSAGE_BB_K2                                                            (0x1<<5) // This bit masks, when set, the Interrupt bit: YULD_REG_INT_STS.LD_LONG_MESSAGE .
+  #define YULD_REG_INT_MASK_LD_LONG_MESSAGE_BB_K2_SHIFT                                                      5
+#define YULD_REG_INT_STS_WR_BB_K2                                                                            0x4c8188UL //Access:WR   DataWidth:0x6    // Multi Field Register.
+  #define YULD_REG_INT_STS_WR_ADDRESS_ERROR_BB_K2                                                            (0x1<<0) // Signals an unknown address to the rf module.
+  #define YULD_REG_INT_STS_WR_ADDRESS_ERROR_BB_K2_SHIFT                                                      0
+  #define YULD_REG_INT_STS_WR_LD_HDR_ERR_BB_K2                                                               (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
+  #define YULD_REG_INT_STS_WR_LD_HDR_ERR_BB_K2_SHIFT                                                         1
+  #define YULD_REG_INT_STS_WR_LD_SEG_MSG_ERR_BB_K2                                                           (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
+  #define YULD_REG_INT_STS_WR_LD_SEG_MSG_ERR_BB_K2_SHIFT                                                     2
+  #define YULD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR_BB_K2                                                    (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
+  #define YULD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR_BB_K2_SHIFT                                              3
+  #define YULD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR_BB_K2                                                    (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
+  #define YULD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR_BB_K2_SHIFT                                              4
+  #define YULD_REG_INT_STS_WR_LD_LONG_MESSAGE_BB_K2                                                          (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
+  #define YULD_REG_INT_STS_WR_LD_LONG_MESSAGE_BB_K2_SHIFT                                                    5
+#define YULD_REG_INT_STS_CLR_BB_K2                                                                           0x4c818cUL //Access:RC   DataWidth:0x6    // Multi Field Register.
+  #define YULD_REG_INT_STS_CLR_ADDRESS_ERROR_BB_K2                                                           (0x1<<0) // Signals an unknown address to the rf module.
+  #define YULD_REG_INT_STS_CLR_ADDRESS_ERROR_BB_K2_SHIFT                                                     0
+  #define YULD_REG_INT_STS_CLR_LD_HDR_ERR_BB_K2                                                              (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
+  #define YULD_REG_INT_STS_CLR_LD_HDR_ERR_BB_K2_SHIFT                                                        1
+  #define YULD_REG_INT_STS_CLR_LD_SEG_MSG_ERR_BB_K2                                                          (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
+  #define YULD_REG_INT_STS_CLR_LD_SEG_MSG_ERR_BB_K2_SHIFT                                                    2
+  #define YULD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR_BB_K2                                                   (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
+  #define YULD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR_BB_K2_SHIFT                                             3
+  #define YULD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR_BB_K2                                                   (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
+  #define YULD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR_BB_K2_SHIFT                                             4
+  #define YULD_REG_INT_STS_CLR_LD_LONG_MESSAGE_BB_K2                                                         (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
+  #define YULD_REG_INT_STS_CLR_LD_LONG_MESSAGE_BB_K2_SHIFT                                                   5
+#define YULD_REG_PRTY_MASK_H_0_BB_K2                                                                         0x4c8204UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define YULD_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                     (0x1<<0) // This bit masks, when set, the Parity bit: YULD_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define YULD_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                               0
+  #define YULD_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                     (0x1<<1) // This bit masks, when set, the Parity bit: YULD_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define YULD_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                               1
+  #define YULD_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2                                                     (0x1<<2) // This bit masks, when set, the Parity bit: YULD_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define YULD_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT                                               2
+  #define YULD_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2                                                     (0x1<<3) // This bit masks, when set, the Parity bit: YULD_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define YULD_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2_SHIFT                                               3
+  #define YULD_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                     (0x1<<4) // This bit masks, when set, the Parity bit: YULD_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define YULD_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                               4
+  #define YULD_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                     (0x1<<5) // This bit masks, when set, the Parity bit: YULD_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define YULD_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                               5
+#define YULD_REG_MEM_ECC_EVENTS_BB_K2                                                                        0x4c8210UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define YULD_REG_DESC_QUEUE_Q0_BB_K2                                                                         0x4c8400UL //Access:WB   DataWidth:0x23   // Descriptor FIFO queue0 - Debug access.
+#define YULD_REG_DESC_QUEUE_Q0_SIZE                                                                          32
+#define YULD_REG_DESC_QUEUE_Q1_BB_K2                                                                         0x4c8800UL //Access:WB   DataWidth:0x23   // Descriptor FIFO queue1 - Debug access.
+#define YULD_REG_DESC_QUEUE_Q1_SIZE                                                                          32
+#define YULD_REG_DBG_SELECT_BB_K2                                                                            0x4c9600UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define YULD_REG_DBG_DWORD_ENABLE_BB_K2                                                                      0x4c9604UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define YULD_REG_DBG_SHIFT_BB_K2                                                                             0x4c9608UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define YULD_REG_DBG_FORCE_VALID_BB_K2                                                                       0x4c960cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define YULD_REG_DBG_FORCE_FRAME_BB_K2                                                                       0x4c9610UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define YULD_REG_DBG_OUT_DATA_BB_K2                                                                          0x4c9620UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define YULD_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define YULD_REG_DBG_OUT_VALID_BB_K2                                                                         0x4c9640UL //Access:R    DataWidth:0x4    // Dbgmux output valid
+#define YULD_REG_DBG_OUT_FRAME_BB_K2                                                                         0x4c9644UL //Access:R    DataWidth:0x4    // Dbgmux output frame
+#define YULD_REG_FIC_INPUT_FIFO_BB_K2                                                                        0x4ca000UL //Access:WB   DataWidth:0x80   // Access to input FIC FIFO
+#define YULD_REG_FIC_INPUT_FIFO_SIZE                                                                         176
+#define YULD_REG_QUEUE_MSG_MEM_BB_K2                                                                         0x4cc000UL //Access:WB   DataWidth:0x80   // Debug access to The message queue memory.
+#define YULD_REG_QUEUE_MSG_MEM_SIZE                                                                          256
+#define TMLD_REG_SCBD_STRICT_PRIO                                                                            0x4d0000UL //Access:RW   DataWidth:0x4    // Each bit indicates if the current queue ahs a strict prioirty; 1: The current queue has strict prority; 0: The current queue is part of the WRR scheme.
+#define TMLD_REG_SCBD_WRR_WEIGHT_Q0                                                                          0x4d0004UL //Access:RW   DataWidth:0x2    // The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_strict_prio reg.
+#define TMLD_REG_SCBD_WRR_WEIGHT_Q1                                                                          0x4d0008UL //Access:RW   DataWidth:0x2    // The weight of queue 1 at the WRR arbiteration, in case its bit is reset at scbd_strict_prio reg.
+#define TMLD_REG_FOCI_FOC_CREDITS                                                                            0x4d000cUL //Access:RW   DataWidth:0x6    // Initial credit of the FOC itnerface.
+#define TMLD_REG_BYPASS_QID                                                                                  0x4d0010UL //Access:RW   DataWidth:0x2    // Selects the queue to which bypass messages will be steered.
+#define TMLD_REG_TCFC_LOAD_MINI_CACHE_EN                                                                     0x4d0014UL //Access:RW   DataWidth:0x1    // Allowes the TID/CID mini cache feature.
+#define TMLD_REG_CCFC_LOAD_MINI_CACHE_EN                                                                     0x4d0018UL //Access:RW   DataWidth:0x1    // Allowes the TID/CID mini cache feature.
+#define TMLD_REG_ECO_RESERVED                                                                                0x4d001cUL //Access:RW   DataWidth:0x8    // Allowes future ECO's
+#define TMLD_REG_BRB_RD_RESP_NUM_SLOTS                                                                       0x4d0020UL //Access:RW   DataWidth:0x3    // Log2 of number of slots at the BRB read response buffer. The slot size would be the BRB-response-buffer-size/number-of-slots.::/MULD_DISCARD/d in MULD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD.
+#define TMLD_REG_CID_REQ_CREDITS                                                                             0x4d0024UL //Access:RW   DataWidth:0x6    // Max credits value for the load cid request interface.
+#define TMLD_REG_TID_REQ_CREDITS                                                                             0x4d0028UL //Access:RW   DataWidth:0x6    // Max credits value for the load tid request interface.
+#define TMLD_REG_BRB_SWAP_EN                                                                                 0x4d002cUL //Access:RW   DataWidth:0x1    // When set the data returning from the BRB is swapped.    meaning that bytes 0-3 is swapped with bytes 4-7 in    each 64b boundary
+#define TMLD_REG_BRB_MAX_CREDITS                                                                             0x4d0030UL //Access:RW   DataWidth:0x3    // Max credit number for the BRB request-resonse interface::/MULD_DISCARD/d in MULD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD.
+#define TMLD_REG_TID_REMAIN_CREDITS                                                                          0x4d0034UL //Access:R    DataWidth:0x6    // Remaining credits for the tid interface
+#define TMLD_REG_TID_MSG_STAT                                                                                0x4d0038UL //Access:RC   DataWidth:0x20   // Statistics counter of TID requests
+#define TMLD_REG_CID_REMAIN_CREDITS                                                                          0x4d003cUL //Access:R    DataWidth:0x6    // Remaining credits for the cid interface
+#define TMLD_REG_CID_MSG_STAT                                                                                0x4d0040UL //Access:RC   DataWidth:0x20   // Statistics counter of CID requests
+#define TMLD_REG_EXT_EV_1_STAT                                                                               0x4d0044UL //Access:RC   DataWidth:0x20   // Statistics counter of message pending to external event 1
+#define TMLD_REG_EXT_EV_2_STAT                                                                               0x4d0048UL //Access:RC   DataWidth:0x20   // Statistics counter of message pending to external event 2
+#define TMLD_REG_EXT_EV_3_STAT                                                                               0x4d004cUL //Access:RC   DataWidth:0x20   // Statistics counter of message pending to external event 3
+#define TMLD_REG_EXT_EV_4_STAT                                                                               0x4d0050UL //Access:RC   DataWidth:0x20   // Statistics counter of message pending to external event 0
+#define TMLD_REG_EXT_EV_5_STAT                                                                               0x4d0054UL //Access:RC   DataWidth:0x20   // Statistics counter of message pending to external event 0
+#define TMLD_REG_PENDING_MSG_TO_EXT_EV_1_CTR                                                                 0x4d0058UL //Access:R    DataWidth:0x9    // Counts the number of messages currently pending to external event 1
+#define TMLD_REG_PENDING_MSG_TO_EXT_EV_2_CTR                                                                 0x4d005cUL //Access:R    DataWidth:0x9    // Counts the number of messages currently pending to external event 2
+#define TMLD_REG_PENDING_MSG_TO_EXT_EV_3_CTR                                                                 0x4d0060UL //Access:R    DataWidth:0x9    // Counts the number of messages currently pending to external event 3
+#define TMLD_REG_PENDING_MSG_TO_EXT_EV_4_CTR                                                                 0x4d0064UL //Access:R    DataWidth:0x9    // Counts the number of messages currently pending to external event 4
+#define TMLD_REG_PENDING_MSG_TO_EXT_EV_5_CTR                                                                 0x4d0068UL //Access:R    DataWidth:0x9    // Counts the number of messages currently pending to external event 5
+#define TMLD_REG_FOC_REMAIN_CREDITS                                                                          0x4d006cUL //Access:R    DataWidth:0x6    // Remaining credits on the FOC interface
+#define TMLD_REG_STAT_BRB_REQ                                                                                0x4d0070UL //Access:RC   DataWidth:0x20   // Counts the number of BRB requests sent
+#define TMLD_REG_BRB_REMAINING_CRED                                                                          0x4d0074UL //Access:R    DataWidth:0x3    // Number of remaining credits on the BRB interface
+#define TMLD_REG_LD_CID_MINICACHE_LOG                                                                        0x4d0078UL //Access:R    DataWidth:0x20   // Logging in case of minicache failure.bits 31:0 CID Valid only if bit 13 in ld_cid_minicache_resp_log is set
+#define TMLD_REG_LD_TID_MINICACHE_LOG                                                                        0x4d007cUL //Access:R    DataWidth:0x20   // Logging in case of minicache failure.bits 31:0 TID Valid only if bit 13 in ld_tid_minicache_resp_log is set
+#define TMLD_REG_LD_CID_MINICACHE_RESP_LOG                                                                   0x4d0080UL //Access:R    DataWidth:0xe    // Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_cid_minicache_log register is valid
+#define TMLD_REG_LD_TID_MINICACHE_RESP_LOG                                                                   0x4d0084UL //Access:R    DataWidth:0xe    // Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_tid_minicache_log register is valid
+#define TMLD_REG_LD_HDR_LOG                                                                                  0x4d0088UL //Access:R    DataWidth:0x4    // Logging of the problem which caused the ld_hdr_err interrupt. Bit 0: ilegal flags combination.
+#define TMLD_REG_LD_HDR_1ST_CYC_31_0                                                                         0x4d008cUL //Access:R    DataWidth:0x20   // Logging of the first loader header cycle - for the case ld_hdr_err is raised.
+#define TMLD_REG_LD_HDR_1ST_CYC_63_32                                                                        0x4d0090UL //Access:R    DataWidth:0x20   // Logging of the first loader header cycle - for the case ld_hdr_err is raised.
+#define TMLD_REG_LD_HDR_1ST_CYC_95_64                                                                        0x4d0094UL //Access:R    DataWidth:0x20   // Logging of the first loader header cycle - for the case ld_hdr_err is raised.
+#define TMLD_REG_LD_HDR_1ST_CYC_127_96                                                                       0x4d0098UL //Access:R    DataWidth:0x20   // Logging of the first loader header cycle - for the case ld_hdr_err is raised.
+#define TMLD_REG_LD_HDR_2ND_CYC_31_0                                                                         0x4d009cUL //Access:R    DataWidth:0x20   // Logging of the second loader header cycle - for the case ld_hdr_err is raised.
+#define TMLD_REG_LD_HDR_2ND_CYC_63_32                                                                        0x4d00a0UL //Access:R    DataWidth:0x20   // Logging of the second loader header cycle - for the case ld_hdr_err is raised.
+#define TMLD_REG_LD_HDR_2ND_CYC_95_64                                                                        0x4d00a4UL //Access:R    DataWidth:0x20   // Logging of the second loader header cycle - for the case ld_hdr_err is raised.
+#define TMLD_REG_LD_HDR_2ND_CYC_127_96                                                                       0x4d00a8UL //Access:R    DataWidth:0x20   // Logging of the second loader header cycle - for the case ld_hdr_err is raised.
+#define TMLD_REG_CM_HDR_31_0                                                                                 0x4d00acUL //Access:R    DataWidth:0x20   // Logging of the cm header cycle - for the case ld_hdr_err is raised.
+#define TMLD_REG_CM_HDR_63_32                                                                                0x4d00b0UL //Access:R    DataWidth:0x20   // Logging of the cm header cycle - for the case ld_hdr_err is raised.
+#define TMLD_REG_CM_HDR_95_64                                                                                0x4d00b4UL //Access:R    DataWidth:0x20   // Logging of the cm header cycle - for the case ld_hdr_err is raised.
+#define TMLD_REG_CM_HDR_127_96                                                                               0x4d00b8UL //Access:R    DataWidth:0x20   // Logging of the cm header cycle - for the case ld_hdr_err is raised.
+#define TMLD_REG_LD_HDR_CLR                                                                                  0x4d00bcUL //Access:W    DataWidth:0x1    // Writing to this register clears hdr registers and enables logging new error details.
+#define TMLD_REG_STAT_FIC_MSG                                                                                0x4d00c0UL //Access:RC   DataWidth:0x20   // Number of FIC messages sent to the loader
+#define TMLD_REG_DBG_PENDING_CCFC_REQ                                                                        0x4d00c4UL //Access:R    DataWidth:0x6    // number of CCFC requests wating for responses
+#define TMLD_REG_DBG_PENDING_TCFC_REQ                                                                        0x4d00c8UL //Access:R    DataWidth:0x6    // number of TCFC requests wating for responses
+#define TMLD_REG_LEN_ERR_LOG_1                                                                               0x4d00ccUL //Access:R    DataWidth:0x10   // Logging register for long message error: bit 0-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SGE fetch; bit 4- Message with BRB fetch; bits 5:6- QID; bits 7-RSV; bits 8-15 message CM length.
+#define TMLD_REG_LEN_ERR_LOG_2                                                                               0x4d00d0UL //Access:R    DataWidth:0x20   // Logging register for long message error: bit 0:3 Segment message header length; 4:7 RSV;8:15 current length out of the segment message length array; 16:23 PCI response len (including BD and SGE fetches); 24:31 BRB
+#define TMLD_REG_LEN_ERR_LOG_CLR                                                                             0x4d00d4UL //Access:W    DataWidth:0x1    // Writing to this register clears len err logging registers and enables logging new error details.
+#define TMLD_REG_LEN_ERR_LOG_V                                                                               0x4d00d8UL //Access:R    DataWidth:0x1    // Indicates that the data at the len_err logging registers is valid.
+#define TMLD_REG_INT_STS                                                                                     0x4d0180UL //Access:R    DataWidth:0x6    // Multi Field Register.
+  #define TMLD_REG_INT_STS_ADDRESS_ERROR                                                                     (0x1<<0) // Signals an unknown address to the rf module.
+  #define TMLD_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                               0
+  #define TMLD_REG_INT_STS_LD_HDR_ERR                                                                        (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
+  #define TMLD_REG_INT_STS_LD_HDR_ERR_SHIFT                                                                  1
+  #define TMLD_REG_INT_STS_LD_SEG_MSG_ERR                                                                    (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
+  #define TMLD_REG_INT_STS_LD_SEG_MSG_ERR_SHIFT                                                              2
+  #define TMLD_REG_INT_STS_LD_TID_MINI_CACHE_ERR                                                             (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
+  #define TMLD_REG_INT_STS_LD_TID_MINI_CACHE_ERR_SHIFT                                                       3
+  #define TMLD_REG_INT_STS_LD_CID_MINI_CACHE_ERR                                                             (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
+  #define TMLD_REG_INT_STS_LD_CID_MINI_CACHE_ERR_SHIFT                                                       4
+  #define TMLD_REG_INT_STS_LD_LONG_MESSAGE                                                                   (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
+  #define TMLD_REG_INT_STS_LD_LONG_MESSAGE_SHIFT                                                             5
+#define TMLD_REG_INT_MASK                                                                                    0x4d0184UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define TMLD_REG_INT_MASK_ADDRESS_ERROR                                                                    (0x1<<0) // This bit masks, when set, the Interrupt bit: TMLD_REG_INT_STS.ADDRESS_ERROR .
+  #define TMLD_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                              0
+  #define TMLD_REG_INT_MASK_LD_HDR_ERR                                                                       (0x1<<1) // This bit masks, when set, the Interrupt bit: TMLD_REG_INT_STS.LD_HDR_ERR .
+  #define TMLD_REG_INT_MASK_LD_HDR_ERR_SHIFT                                                                 1
+  #define TMLD_REG_INT_MASK_LD_SEG_MSG_ERR                                                                   (0x1<<2) // This bit masks, when set, the Interrupt bit: TMLD_REG_INT_STS.LD_SEG_MSG_ERR .
+  #define TMLD_REG_INT_MASK_LD_SEG_MSG_ERR_SHIFT                                                             2
+  #define TMLD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR                                                            (0x1<<3) // This bit masks, when set, the Interrupt bit: TMLD_REG_INT_STS.LD_TID_MINI_CACHE_ERR .
+  #define TMLD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR_SHIFT                                                      3
+  #define TMLD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR                                                            (0x1<<4) // This bit masks, when set, the Interrupt bit: TMLD_REG_INT_STS.LD_CID_MINI_CACHE_ERR .
+  #define TMLD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR_SHIFT                                                      4
+  #define TMLD_REG_INT_MASK_LD_LONG_MESSAGE                                                                  (0x1<<5) // This bit masks, when set, the Interrupt bit: TMLD_REG_INT_STS.LD_LONG_MESSAGE .
+  #define TMLD_REG_INT_MASK_LD_LONG_MESSAGE_SHIFT                                                            5
+#define TMLD_REG_INT_STS_WR                                                                                  0x4d0188UL //Access:WR   DataWidth:0x6    // Multi Field Register.
+  #define TMLD_REG_INT_STS_WR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define TMLD_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                            0
+  #define TMLD_REG_INT_STS_WR_LD_HDR_ERR                                                                     (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
+  #define TMLD_REG_INT_STS_WR_LD_HDR_ERR_SHIFT                                                               1
+  #define TMLD_REG_INT_STS_WR_LD_SEG_MSG_ERR                                                                 (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
+  #define TMLD_REG_INT_STS_WR_LD_SEG_MSG_ERR_SHIFT                                                           2
+  #define TMLD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR                                                          (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
+  #define TMLD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR_SHIFT                                                    3
+  #define TMLD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR                                                          (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
+  #define TMLD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR_SHIFT                                                    4
+  #define TMLD_REG_INT_STS_WR_LD_LONG_MESSAGE                                                                (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
+  #define TMLD_REG_INT_STS_WR_LD_LONG_MESSAGE_SHIFT                                                          5
+#define TMLD_REG_INT_STS_CLR                                                                                 0x4d018cUL //Access:RC   DataWidth:0x6    // Multi Field Register.
+  #define TMLD_REG_INT_STS_CLR_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define TMLD_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                           0
+  #define TMLD_REG_INT_STS_CLR_LD_HDR_ERR                                                                    (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
+  #define TMLD_REG_INT_STS_CLR_LD_HDR_ERR_SHIFT                                                              1
+  #define TMLD_REG_INT_STS_CLR_LD_SEG_MSG_ERR                                                                (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
+  #define TMLD_REG_INT_STS_CLR_LD_SEG_MSG_ERR_SHIFT                                                          2
+  #define TMLD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR                                                         (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
+  #define TMLD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR_SHIFT                                                   3
+  #define TMLD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR                                                         (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
+  #define TMLD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR_SHIFT                                                   4
+  #define TMLD_REG_INT_STS_CLR_LD_LONG_MESSAGE                                                               (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
+  #define TMLD_REG_INT_STS_CLR_LD_LONG_MESSAGE_SHIFT                                                         5
+#define TMLD_REG_PRTY_MASK_H_0_BB_K2                                                                         0x4d0204UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define TMLD_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_BB_K2                                                   (0x1<<0) // This bit masks, when set, the Parity bit: TMLD_REG_PRTY_STS_H_0.MEM006_I_ECC_RF_INT .
+  #define TMLD_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_BB_K2_SHIFT                                             0
+  #define TMLD_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_BB_K2                                                   (0x1<<1) // This bit masks, when set, the Parity bit: TMLD_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT .
+  #define TMLD_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_BB_K2_SHIFT                                             1
+  #define TMLD_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                     (0x1<<2) // This bit masks, when set, the Parity bit: TMLD_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define TMLD_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                               2
+  #define TMLD_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                     (0x1<<3) // This bit masks, when set, the Parity bit: TMLD_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define TMLD_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                               3
+  #define TMLD_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2                                                     (0x1<<4) // This bit masks, when set, the Parity bit: TMLD_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define TMLD_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2_SHIFT                                               4
+  #define TMLD_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2                                                     (0x1<<5) // This bit masks, when set, the Parity bit: TMLD_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define TMLD_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2_SHIFT                                               5
+  #define TMLD_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2                                                     (0x1<<6) // This bit masks, when set, the Parity bit: TMLD_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define TMLD_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT                                               6
+  #define TMLD_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                     (0x1<<7) // This bit masks, when set, the Parity bit: TMLD_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define TMLD_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                               7
+#define TMLD_REG_MEM_ECC_ENABLE_0_BB_K2                                                                      0x4d0210UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define TMLD_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN_BB_K2                                                    (0x1<<0) // Enable ECC for memory ecc instance tmld.i_msgq_ram.i_ecc in module tmld_i_msgq_ram_1
+  #define TMLD_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN_BB_K2_SHIFT                                              0
+  #define TMLD_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN_BB_K2                                                    (0x1<<1) // Enable ECC for memory ecc instance tmld.i_brb_resp_buf_ram.i_ecc in module tmld_i_brb_resp_buf_ram
+  #define TMLD_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN_BB_K2_SHIFT                                              1
+#define TMLD_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                 0x4d0214UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define TMLD_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY_BB_K2                                             (0x1<<0) // Set parity only for memory ecc instance tmld.i_msgq_ram.i_ecc in module tmld_i_msgq_ram_1
+  #define TMLD_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY_BB_K2_SHIFT                                       0
+  #define TMLD_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY_BB_K2                                             (0x1<<1) // Set parity only for memory ecc instance tmld.i_brb_resp_buf_ram.i_ecc in module tmld_i_brb_resp_buf_ram
+  #define TMLD_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY_BB_K2_SHIFT                                       1
+#define TMLD_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                             0x4d0218UL //Access:RC   DataWidth:0x2    // Multi Field Register.
+  #define TMLD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT_BB_K2                                      (0x1<<0) // Record if a correctable error occurred on memory ecc instance tmld.i_msgq_ram.i_ecc in module tmld_i_msgq_ram_1
+  #define TMLD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT_BB_K2_SHIFT                                0
+  #define TMLD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT_BB_K2                                      (0x1<<1) // Record if a correctable error occurred on memory ecc instance tmld.i_brb_resp_buf_ram.i_ecc in module tmld_i_brb_resp_buf_ram
+  #define TMLD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT_BB_K2_SHIFT                                1
+#define TMLD_REG_MEM_ECC_EVENTS_BB_K2                                                                        0x4d021cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define TMLD_REG_DESC_QUEUE_Q0                                                                               0x4d0400UL //Access:WB   DataWidth:0x23   // Descriptor FIFO queue0 - Debug access.
+#define TMLD_REG_DESC_QUEUE_Q0_SIZE                                                                          64
+#define TMLD_REG_DESC_QUEUE_Q1                                                                               0x4d0800UL //Access:WB   DataWidth:0x23   // Descriptor FIFO queue1 - Debug access.
+#define TMLD_REG_DESC_QUEUE_Q1_SIZE                                                                          64
+#define TMLD_REG_L2MA_AGGR_CONFIG1_E5                                                                        0x4d0900UL //Access:RW   DataWidth:0x13   // Multi Field Register.
+  #define TMLD_REG_L2MA_AGGR_CONFIG1_L2MA_EN_E5                                                              (0x1<<0) // Enables L2 message aggregation
+  #define TMLD_REG_L2MA_AGGR_CONFIG1_L2MA_EN_E5_SHIFT                                                        0
+  #define TMLD_REG_L2MA_AGGR_CONFIG1_IGNORE_CM_AGG_MSG_E5                                                    (0x1<<1) // indicates not to perform the aggregation logic if there is no L2MA command in the message (there is no L2MA command if DstStormFlg is reset OR ErrFlg is set). If this configuration is reset, messages without L2MA command are treated like messages with L2MA command where EnL2MA flag in the command is reset (i.e. they break existing aggregation).
+  #define TMLD_REG_L2MA_AGGR_CONFIG1_IGNORE_CM_AGG_MSG_E5_SHIFT                                              1
+  #define TMLD_REG_L2MA_AGGR_CONFIG1_BACK_2_BACK_E5                                                          (0x1<<2) // defines that only back-to-back aggregation is allowed
+  #define TMLD_REG_L2MA_AGGR_CONFIG1_BACK_2_BACK_E5_SHIFT                                                    2
+  #define TMLD_REG_L2MA_AGGR_CONFIG1_MIN_QUEUE_OCC_E5                                                        (0xff<<3) // the minimal queue occupancy below which new aggregations are not created
+  #define TMLD_REG_L2MA_AGGR_CONFIG1_MIN_QUEUE_OCC_E5_SHIFT                                                  3
+  #define TMLD_REG_L2MA_AGGR_CONFIG1_MAX_L2MA_DIFF_E5                                                        (0xff<<11) // the maximal difference between the serial number of the parent message and the serial number of its child message
+  #define TMLD_REG_L2MA_AGGR_CONFIG1_MAX_L2MA_DIFF_E5_SHIFT                                                  11
+#define TMLD_REG_L2MA_AGGR_CONFIG2_E5                                                                        0x4d0904UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define TMLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_0_E5                                                     (0x3f<<0) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
+  #define TMLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_0_E5_SHIFT                                               0
+  #define TMLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_1_E5                                                     (0x3f<<6) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
+  #define TMLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_1_E5_SHIFT                                               6
+  #define TMLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_2_E5                                                     (0x3f<<12) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
+  #define TMLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_2_E5_SHIFT                                               12
+  #define TMLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_3_E5                                                     (0x3f<<18) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
+  #define TMLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_3_E5_SHIFT                                               18
+#define TMLD_REG_L2MA_SAME_OFFSET_SET_0_E5                                                                   0x4d0908UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_00_E5                                                       (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_00_E5_SHIFT                                                 0
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_01_E5                                                       (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_01_E5_SHIFT                                                 8
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_02_E5                                                       (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_02_E5_SHIFT                                                 16
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_03_E5                                                       (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_03_E5_SHIFT                                                 24
+#define TMLD_REG_L2MA_SAME_OFFSET_SET_1_E5                                                                   0x4d090cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_10_E5                                                       (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_10_E5_SHIFT                                                 0
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_11_E5                                                       (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_11_E5_SHIFT                                                 8
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_12_E5                                                       (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_12_E5_SHIFT                                                 16
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_13_E5                                                       (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_13_E5_SHIFT                                                 24
+#define TMLD_REG_L2MA_SAME_OFFSET_SET_2_E5                                                                   0x4d0910UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_20_E5                                                       (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_20_E5_SHIFT                                                 0
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_21_E5                                                       (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_21_E5_SHIFT                                                 8
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_22_E5                                                       (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_22_E5_SHIFT                                                 16
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_23_E5                                                       (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_23_E5_SHIFT                                                 24
+#define TMLD_REG_L2MA_SAME_OFFSET_SET_3_E5                                                                   0x4d0914UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_30_E5                                                       (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_30_E5_SHIFT                                                 0
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_31_E5                                                       (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_31_E5_SHIFT                                                 8
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_32_E5                                                       (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_32_E5_SHIFT                                                 16
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_33_E5                                                       (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
+  #define TMLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_33_E5_SHIFT                                                 24
+#define TMLD_REG_L2MA_SAME_LEN_SET_0_1_E5                                                                    0x4d0918UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define TMLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_00_E5                                                           (0xf<<0) // length in 32b units from the same 00 .
+  #define TMLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_00_E5_SHIFT                                                     0
+  #define TMLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_01_E5                                                           (0xf<<4) // length in 32b units from the same 01 .
+  #define TMLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_01_E5_SHIFT                                                     4
+  #define TMLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_02_E5                                                           (0xf<<8) // length in 32b units from the same 02 .
+  #define TMLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_02_E5_SHIFT                                                     8
+  #define TMLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_03_E5                                                           (0xf<<12) // length in 32b units from the same 03 .
+  #define TMLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_03_E5_SHIFT                                                     12
+  #define TMLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_10_E5                                                           (0xf<<16) // length in 32b units from the same 10 .
+  #define TMLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_10_E5_SHIFT                                                     16
+  #define TMLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_11_E5                                                           (0xf<<20) // length in 32b units from the same 11 .
+  #define TMLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_11_E5_SHIFT                                                     20
+  #define TMLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_12_E5                                                           (0xf<<24) // length in 32b units from the same 12 .
+  #define TMLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_12_E5_SHIFT                                                     24
+  #define TMLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_13_E5                                                           (0xf<<28) // length in 32b units from the same 13 .
+  #define TMLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_13_E5_SHIFT                                                     28
+#define TMLD_REG_L2MA_SAME_LEN_SET_2_3_E5                                                                    0x4d091cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define TMLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_20_E5                                                           (0xf<<0) // length in 32b units from the same 20 .
+  #define TMLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_20_E5_SHIFT                                                     0
+  #define TMLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_21_E5                                                           (0xf<<4) // length in 32b units from the same 21 .
+  #define TMLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_21_E5_SHIFT                                                     4
+  #define TMLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_22_E5                                                           (0xf<<8) // length in 32b units from the same 22 .
+  #define TMLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_22_E5_SHIFT                                                     8
+  #define TMLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_23_E5                                                           (0xf<<12) // length in 32b units from the same 23 .
+  #define TMLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_23_E5_SHIFT                                                     12
+  #define TMLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_30_E5                                                           (0xf<<16) // length in 32b units from the same 30 .
+  #define TMLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_30_E5_SHIFT                                                     16
+  #define TMLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_31_E5                                                           (0xf<<20) // length in 32b units from the same 31 .
+  #define TMLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_31_E5_SHIFT                                                     20
+  #define TMLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_32_E5                                                           (0xf<<24) // length in 32b units from the same 32 .
+  #define TMLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_32_E5_SHIFT                                                     24
+  #define TMLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_33_E5                                                           (0xf<<28) // length in 32b units from the same 33 .
+  #define TMLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_33_E5_SHIFT                                                     28
+#define TMLD_REG_L2MA_SAME_MASK_SET_0_E5                                                                     0x4d0920UL //Access:RW   DataWidth:0x20   // bit-mask on the selected 32B same 0 parameters .
+#define TMLD_REG_L2MA_SAME_MASK_SET_1_E5                                                                     0x4d0924UL //Access:RW   DataWidth:0x20   // bit-mask on the selected 32B same 1 parameters .
+#define TMLD_REG_L2MA_SAME_MASK_SET_2_E5                                                                     0x4d0928UL //Access:RW   DataWidth:0x20   // bit-mask on the selected 32B same 2 parameters .
+#define TMLD_REG_L2MA_SAME_MASK_SET_3_E5                                                                     0x4d092cUL //Access:RW   DataWidth:0x20   // bit-mask on the selected 32B same 3 parameters .
+#define TMLD_REG_L2MA_DUP_OFFSET_SET_0_E5                                                                    0x4d0930UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_00_E5                                                    (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_00_E5_SHIFT                                              0
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_01_E5                                                    (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_01_E5_SHIFT                                              8
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_02_E5                                                    (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_02_E5_SHIFT                                              16
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_03_E5                                                    (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_03_E5_SHIFT                                              24
+#define TMLD_REG_L2MA_DUP_OFFSET_SET_1_E5                                                                    0x4d0934UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_10_E5                                                    (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_10_E5_SHIFT                                              0
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_11_E5                                                    (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_11_E5_SHIFT                                              8
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_12_E5                                                    (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_12_E5_SHIFT                                              16
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_13_E5                                                    (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_13_E5_SHIFT                                              24
+#define TMLD_REG_L2MA_DUP_OFFSET_SET_2_E5                                                                    0x4d0938UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_20_E5                                                    (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_20_E5_SHIFT                                              0
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_21_E5                                                    (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_21_E5_SHIFT                                              8
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_22_E5                                                    (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_22_E5_SHIFT                                              16
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_23_E5                                                    (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_23_E5_SHIFT                                              24
+#define TMLD_REG_L2MA_DUP_OFFSET_SET_3_E5                                                                    0x4d093cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_30_E5                                                    (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_30_E5_SHIFT                                              0
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_31_E5                                                    (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_31_E5_SHIFT                                              8
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_32_E5                                                    (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_32_E5_SHIFT                                              16
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_33_E5                                                    (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
+  #define TMLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_33_E5_SHIFT                                              24
+#define TMLD_REG_L2MA_DUP_LEN_SET_0_E5                                                                       0x4d0940UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define TMLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_00_E5                                                          (0x3f<<0) // length in 32b units from the dup 00 .
+  #define TMLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_00_E5_SHIFT                                                    0
+  #define TMLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_01_E5                                                          (0x3f<<6) // length in 32b units from the dup 01 .
+  #define TMLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_01_E5_SHIFT                                                    6
+  #define TMLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_02_E5                                                          (0x3f<<12) // length in 32b units from the dup 02 .
+  #define TMLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_02_E5_SHIFT                                                    12
+  #define TMLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_03_E5                                                          (0x3f<<18) // length in 32b units from the dup 03 .
+  #define TMLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_03_E5_SHIFT                                                    18
+#define TMLD_REG_L2MA_DUP_LEN_SET_1_E5                                                                       0x4d0944UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define TMLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_10_E5                                                          (0x3f<<0) // length in 32b units from the dup 10 .
+  #define TMLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_10_E5_SHIFT                                                    0
+  #define TMLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_11_E5                                                          (0x3f<<6) // length in 32b units from the dup 11 .
+  #define TMLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_11_E5_SHIFT                                                    6
+  #define TMLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_12_E5                                                          (0x3f<<12) // length in 32b units from the dup 12 .
+  #define TMLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_12_E5_SHIFT                                                    12
+  #define TMLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_13_E5                                                          (0x3f<<18) // length in 32b units from the dup 13 .
+  #define TMLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_13_E5_SHIFT                                                    18
+#define TMLD_REG_L2MA_DUP_LEN_SET_2_E5                                                                       0x4d0948UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define TMLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_20_E5                                                          (0x3f<<0) // length in 32b units from the dup 20 .
+  #define TMLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_20_E5_SHIFT                                                    0
+  #define TMLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_21_E5                                                          (0x3f<<6) // length in 32b units from the dup 21 .
+  #define TMLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_21_E5_SHIFT                                                    6
+  #define TMLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_22_E5                                                          (0x3f<<12) // length in 32b units from the dup 22 .
+  #define TMLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_22_E5_SHIFT                                                    12
+  #define TMLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_23_E5                                                          (0x3f<<18) // length in 32b units from the dup 23 .
+  #define TMLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_23_E5_SHIFT                                                    18
+#define TMLD_REG_L2MA_DUP_LEN_SET_3_E5                                                                       0x4d094cUL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define TMLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_30_E5                                                          (0x3f<<0) // length in 32b units from the dup 30 .
+  #define TMLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_30_E5_SHIFT                                                    0
+  #define TMLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_31_E5                                                          (0x3f<<6) // length in 32b units from the dup 31 .
+  #define TMLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_31_E5_SHIFT                                                    6
+  #define TMLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_32_E5                                                          (0x3f<<12) // length in 32b units from the dup 32 .
+  #define TMLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_32_E5_SHIFT                                                    12
+  #define TMLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_33_E5                                                          (0x3f<<18) // length in 32b units from the dup 33 .
+  #define TMLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_33_E5_SHIFT                                                    18
+#define TMLD_REG_L2MA_FLOW_ID_E5                                                                             0x4d0950UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define TMLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_0_E5                                                         (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
+  #define TMLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_0_E5_SHIFT                                                   0
+  #define TMLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_1_E5                                                         (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
+  #define TMLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_1_E5_SHIFT                                                   1
+  #define TMLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_2_E5                                                         (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
+  #define TMLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_2_E5_SHIFT                                                   2
+  #define TMLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_3_E5                                                         (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
+  #define TMLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_3_E5_SHIFT                                                   3
+  #define TMLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_0_E5                                                          (0x1f<<4) // offset of the flow-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of the incoming message (i.e. max value is 23). This parameter is NA if FlowIdInclude is reset. For set 0 .
+  #define TMLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_0_E5_SHIFT                                                    4
+  #define TMLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_1_E5                                                          (0x1f<<9) // offset of the flow-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of the incoming message (i.e. max value is 23). This parameter is NA if FlowIdInclude is reset. For set 1 .
+  #define TMLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_1_E5_SHIFT                                                    9
+  #define TMLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_2_E5                                                          (0x1f<<14) // offset of the flow-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of the incoming message (i.e. max value is 23). This parameter is NA if FlowIdInclude is reset. For set 2 .
+  #define TMLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_2_E5_SHIFT                                                    14
+  #define TMLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_3_E5                                                          (0x1f<<19) // offset of the flow-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of the incoming message (i.e. max value is 23). This parameter is NA if FlowIdInclude is reset. For set 3 .
+  #define TMLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_3_E5_SHIFT                                                    19
+#define TMLD_REG_L2MA_SN_OFFSET_E5                                                                           0x4d0954UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define TMLD_REG_L2MA_SN_OFFSET_SN_OFFSET_0_E5                                                             (0xff<<0) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 0.
+  #define TMLD_REG_L2MA_SN_OFFSET_SN_OFFSET_0_E5_SHIFT                                                       0
+  #define TMLD_REG_L2MA_SN_OFFSET_SN_OFFSET_1_E5                                                             (0xff<<8) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 1.
+  #define TMLD_REG_L2MA_SN_OFFSET_SN_OFFSET_1_E5_SHIFT                                                       8
+  #define TMLD_REG_L2MA_SN_OFFSET_SN_OFFSET_2_E5                                                             (0xff<<16) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 2.
+  #define TMLD_REG_L2MA_SN_OFFSET_SN_OFFSET_2_E5_SHIFT                                                       16
+  #define TMLD_REG_L2MA_SN_OFFSET_SN_OFFSET_3_E5                                                             (0xff<<24) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 3.
+  #define TMLD_REG_L2MA_SN_OFFSET_SN_OFFSET_3_E5_SHIFT                                                       24
+#define TMLD_REG_L2MA_MAX_L2MA_CHILD_E5                                                                      0x4d0958UL //Access:RW   DataWidth:0x10   // Multi Field Register.
+  #define TMLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_0_E5                                                         (0xf<<0) // the maximal number of children in a specific aggregation. for set 0.
+  #define TMLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_0_E5_SHIFT                                                   0
+  #define TMLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_1_E5                                                         (0xf<<4) // the maximal number of children in a specific aggregation. for set 1.
+  #define TMLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_1_E5_SHIFT                                                   4
+  #define TMLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_2_E5                                                         (0xf<<8) // the maximal number of children in a specific aggregation. for set 2.
+  #define TMLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_2_E5_SHIFT                                                   8
+  #define TMLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_3_E5                                                         (0xf<<12) // the maximal number of children in a specific aggregation. for set 3.
+  #define TMLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_3_E5_SHIFT                                                   12
+#define TMLD_REG_L2MA_INC_L2MA_EVENT_ID_E5                                                                   0x4d095cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define TMLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_0_E5                                                  (0xff<<0) // The value by which to increment the event-ID in case of successful aggregation. for set 0.
+  #define TMLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_0_E5_SHIFT                                            0
+  #define TMLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_1_E5                                                  (0xff<<8) // The value by which to increment the event-ID in case of successful aggregation. for set 1.
+  #define TMLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_1_E5_SHIFT                                            8
+  #define TMLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_2_E5                                                  (0xff<<16) // The value by which to increment the event-ID in case of successful aggregation. for set 2.
+  #define TMLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_2_E5_SHIFT                                            16
+  #define TMLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_3_E5                                                  (0xff<<24) // The value by which to increment the event-ID in case of successful aggregation. for set 3.
+  #define TMLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_3_E5_SHIFT                                            24
+#define TMLD_REG_LD_MAX_MSG_SIZE_E5                                                                          0x4d0960UL //Access:RW   DataWidth:0x4    // maximum loader size in 256 bit words
+#define TMLD_REG_DBG_SELECT                                                                                  0x4d1600UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define TMLD_REG_DBG_DWORD_ENABLE                                                                            0x4d1604UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define TMLD_REG_DBG_SHIFT                                                                                   0x4d1608UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define TMLD_REG_DBG_FORCE_VALID                                                                             0x4d160cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define TMLD_REG_DBG_FORCE_FRAME                                                                             0x4d1610UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define TMLD_REG_DBG_OUT_DATA                                                                                0x4d1620UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define TMLD_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define TMLD_REG_DBG_OUT_VALID                                                                               0x4d1640UL //Access:R    DataWidth:0x4    // Dbgmux output valid
+#define TMLD_REG_DBG_OUT_FRAME                                                                               0x4d1644UL //Access:R    DataWidth:0x4    // Dbgmux output frame
+#define TMLD_REG_FIC_INPUT_FIFO                                                                              0x4d2000UL //Access:WB   DataWidth:0x80   // Access to input FIC FIFO
+#define TMLD_REG_FIC_INPUT_FIFO_SIZE                                                                         176
+#define TMLD_REG_QUEUE_MSG_MEM                                                                               0x4d4000UL //Access:WB   DataWidth:0x80   // Debug access to The message queue memory.
+#define TMLD_REG_QUEUE_MSG_MEM_SIZE                                                                          3200
+#define MULD_REG_SCBD_STRICT_PRIO                                                                            0x4e0000UL //Access:RW   DataWidth:0x4    // Each bit indicates if the current queue ahs a strict prioirty; 1: The current queue has strict prority; 0: The current queue is part of the WRR scheme.
+#define MULD_REG_SCBD_WRR_WEIGHT_Q0                                                                          0x4e0004UL //Access:RW   DataWidth:0x2    // The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_strict_prio reg.
+#define MULD_REG_SCBD_WRR_WEIGHT_Q1                                                                          0x4e0008UL //Access:RW   DataWidth:0x2    // The weight of queue 1 at the WRR arbiteration, in case its bit is reset at scbd_strict_prio reg.
+#define MULD_REG_SCBD_WRR_WEIGHT_Q2                                                                          0x4e000cUL //Access:RW   DataWidth:0x2    // The weight of queue 2 at the WRR arbiteration, in case its bit is reset at scbd_strict_prio reg::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD.
+#define MULD_REG_SCBD_WRR_WEIGHT_Q3                                                                          0x4e0010UL //Access:RW   DataWidth:0x2    // The weight of queue 3 at the WRR arbiteration, in case its bit is reset at scbd_strict_prio reg::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD.
+#define MULD_REG_BD_SIZE                                                                                     0x4e0014UL //Access:RW   DataWidth:0x4    // Log 2 of the BD size in bytes - 2:BD size is 4bytes; 3:BD size is 8bytes; 4:BD size is 16bytes etc::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD.
+#define MULD_REG_BD_NEXT_ADDR_OFST                                                                           0x4e0018UL //Access:RW   DataWidth:0x10   // Ofset within a given page of the next page's address (in bytes)::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD.
+#define MULD_REG_SGE_SIZE                                                                                    0x4e001cUL //Access:RW   DataWidth:0x4    // Log 2 of the SGE size in bytes - 2:SGE size is 4bytes; 3:SGE size is 8bytes; 4:SGE size is 16bytes etc::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD.
+#define MULD_REG_SGE_NEXT_ADDR_OFST                                                                          0x4e0020UL //Access:RW   DataWidth:0x10   // Ofset within a given page of the next page's address (in bytes)::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD.
+#define MULD_REG_FOCI_FOC_CREDITS                                                                            0x4e0024UL //Access:RW   DataWidth:0x6    // Initial credit of the FOC itnerface.
+#define MULD_REG_PCII_PXP_RD_REQ_CREDITS                                                                     0x4e0028UL //Access:RW   DataWidth:0x2    // Initial credit for the PCI interface::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.
+#define MULD_REG_PCII_RD_RESP_NUM_SLOTS                                                                      0x4e002cUL //Access:RW   DataWidth:0x3    // Number of slots at the PCI read response buffer: 3=4/8 slots of 512 bytes;4=8/16 slots of 256 bytes;5=16/32 slots of 128 bytes;6=32/64 slots of 64 bytes; 7=64/128 slots of 32 bytes::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.
+#define MULD_REG_BYPASS_QID                                                                                  0x4e0030UL //Access:RW   DataWidth:0x2    // Selects the queue to which bypass messages will be steered.
+#define MULD_REG_TCFC_LOAD_MINI_CACHE_EN                                                                     0x4e0034UL //Access:RW   DataWidth:0x1    // Allowes the TID/CID mini cache feature.
+#define MULD_REG_CCFC_LOAD_MINI_CACHE_EN                                                                     0x4e0038UL //Access:RW   DataWidth:0x1    // Allowes the TID/CID mini cache feature.
+#define MULD_REG_ECO_RESERVED                                                                                0x4e003cUL //Access:RW   DataWidth:0x8    // Allowes future ECO's
+#define MULD_REG_LD_VQID                                                                                     0x4e0040UL //Access:RW   DataWidth:0x5    // VQID value for PXP read requests issued from all sources (PCI read BD fetches and SGE fetches).
+#define MULD_REG_CID_REQ_CREDITS                                                                             0x4e0044UL //Access:RW   DataWidth:0x6    // Max credits value for the load cid request interface.
+#define MULD_REG_TID_REQ_CREDITS                                                                             0x4e0048UL //Access:RW   DataWidth:0x6    // Max credits value for the load tid request interface.
+#define MULD_REG_TID_REMAIN_CREDITS                                                                          0x4e004cUL //Access:R    DataWidth:0x6    // Remaining credits for the tid interface
+#define MULD_REG_TID_MSG_STAT                                                                                0x4e0050UL //Access:RC   DataWidth:0x20   // Statistics counter of TID requests
+#define MULD_REG_CID_REMAIN_CREDITS                                                                          0x4e0054UL //Access:R    DataWidth:0x6    // Remaining credits for the cid interface
+#define MULD_REG_CID_MSG_STAT                                                                                0x4e0058UL //Access:RC   DataWidth:0x20   // Statistics counter of CID requests
+#define MULD_REG_EXT_EV_1_STAT                                                                               0x4e005cUL //Access:RC   DataWidth:0x20   // Statistics counter of message pending to external event 1
+#define MULD_REG_EXT_EV_2_STAT                                                                               0x4e0060UL //Access:RC   DataWidth:0x20   // Statistics counter of message pending to external event 2
+#define MULD_REG_EXT_EV_3_STAT                                                                               0x4e0064UL //Access:RC   DataWidth:0x20   // Statistics counter of message pending to external event 3
+#define MULD_REG_EXT_EV_4_STAT                                                                               0x4e0068UL //Access:RC   DataWidth:0x20   // Statistics counter of message pending to external event 0
+#define MULD_REG_EXT_EV_5_STAT                                                                               0x4e006cUL //Access:RC   DataWidth:0x20   // Statistics counter of message pending to external event 0
+#define MULD_REG_PENDING_MSG_TO_EXT_EV_1_CTR                                                                 0x4e0070UL //Access:R    DataWidth:0x9    // Counts the number of messages currently pending to external event 1
+#define MULD_REG_PENDING_MSG_TO_EXT_EV_2_CTR                                                                 0x4e0074UL //Access:R    DataWidth:0x9    // Counts the number of messages currently pending to external event 2
+#define MULD_REG_PENDING_MSG_TO_EXT_EV_3_CTR                                                                 0x4e0078UL //Access:R    DataWidth:0x9    // Counts the number of messages currently pending to external event 3
+#define MULD_REG_PENDING_MSG_TO_EXT_EV_4_CTR                                                                 0x4e007cUL //Access:R    DataWidth:0x9    // Counts the number of messages currently pending to external event 4
+#define MULD_REG_PENDING_MSG_TO_EXT_EV_5_CTR                                                                 0x4e0080UL //Access:R    DataWidth:0x9    // Counts the number of messages currently pending to external event 5
+#define MULD_REG_FOC_REMAIN_CREDITS                                                                          0x4e0084UL //Access:R    DataWidth:0x6    // Remaining credits on the FOC interface
+#define MULD_REG_BD_PENDING_MSG_CTR                                                                          0x4e0088UL //Access:R    DataWidth:0x9    // Number of messages pending to BD fetch
+#define MULD_REG_SGE_PENDING_MSG_CTR                                                                         0x4e008cUL //Access:R    DataWidth:0x9    // Number of messages pending to SGE fetch
+#define MULD_REG_PXP_MSG_STAT                                                                                0x4e0090UL //Access:RC   DataWidth:0x20   // Statistics counter of PXP requests sent
+#define MULD_REG_PCII_REMAIN_CREDITS                                                                         0x4e0094UL //Access:R    DataWidth:0x2    // Remaining credits on the PCI interface
+#define MULD_REG_PCI_PENDING_MSG_CTR                                                                         0x4e0098UL //Access:R    DataWidth:0x9    // Number of messages pending to PCI read request
+#define MULD_REG_LD_CID_MINICACHE_LOG                                                                        0x4e009cUL //Access:R    DataWidth:0x20   // Logging in case of minicache failure.bits 31:0 CID Valid only if bit 13 in ld_cid_minicache_resp_log is set
+#define MULD_REG_LD_TID_MINICACHE_LOG                                                                        0x4e00a0UL //Access:R    DataWidth:0x20   // Logging in case of minicache failure.bits 31:0 TID Valid only if bit 13 in ld_tid_minicache_resp_log is set
+#define MULD_REG_LD_CID_MINICACHE_RESP_LOG                                                                   0x4e00a4UL //Access:R    DataWidth:0xe    // Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_cid_minicache_log register is valid
+#define MULD_REG_LD_TID_MINICACHE_RESP_LOG                                                                   0x4e00a8UL //Access:R    DataWidth:0xe    // Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_tid_minicache_log register is valid
+#define MULD_REG_LD_HDR_LOG                                                                                  0x4e00acUL //Access:R    DataWidth:0x4    // Logging of the problem which caused the ld_hdr_err interrupt. Bit 0: ilegal flags combination.
+#define MULD_REG_LD_HDR_1ST_CYC_31_0                                                                         0x4e00b0UL //Access:R    DataWidth:0x20   // Logging of the first loader header cycle - for the case ld_hdr_err is raised.
+#define MULD_REG_LD_HDR_1ST_CYC_63_32                                                                        0x4e00b4UL //Access:R    DataWidth:0x20   // Logging of the first loader header cycle - for the case ld_hdr_err is raised.
+#define MULD_REG_LD_HDR_1ST_CYC_95_64                                                                        0x4e00b8UL //Access:R    DataWidth:0x20   // Logging of the first loader header cycle - for the case ld_hdr_err is raised.
+#define MULD_REG_LD_HDR_1ST_CYC_127_96                                                                       0x4e00bcUL //Access:R    DataWidth:0x20   // Logging of the first loader header cycle - for the case ld_hdr_err is raised.
+#define MULD_REG_LD_HDR_2ND_CYC_31_0                                                                         0x4e00c0UL //Access:R    DataWidth:0x20   // Logging of the second loader header cycle - for the case ld_hdr_err is raised.
+#define MULD_REG_LD_HDR_2ND_CYC_63_32                                                                        0x4e00c4UL //Access:R    DataWidth:0x20   // Logging of the second loader header cycle - for the case ld_hdr_err is raised.
+#define MULD_REG_LD_HDR_2ND_CYC_95_64                                                                        0x4e00c8UL //Access:R    DataWidth:0x20   // Logging of the second loader header cycle - for the case ld_hdr_err is raised.
+#define MULD_REG_LD_HDR_2ND_CYC_127_96                                                                       0x4e00ccUL //Access:R    DataWidth:0x20   // Logging of the second loader header cycle - for the case ld_hdr_err is raised.
+#define MULD_REG_CM_HDR_31_0                                                                                 0x4e00d0UL //Access:R    DataWidth:0x20   // Logging of the cm header cycle - for the case ld_hdr_err is raised.
+#define MULD_REG_CM_HDR_63_32                                                                                0x4e00d4UL //Access:R    DataWidth:0x20   // Logging of the cm header cycle - for the case ld_hdr_err is raised.
+#define MULD_REG_CM_HDR_95_64                                                                                0x4e00d8UL //Access:R    DataWidth:0x20   // Logging of the cm header cycle - for the case ld_hdr_err is raised.
+#define MULD_REG_CM_HDR_127_96                                                                               0x4e00dcUL //Access:R    DataWidth:0x20   // Logging of the cm header cycle - for the case ld_hdr_err is raised.
+#define MULD_REG_LD_HDR_CLR                                                                                  0x4e00e0UL //Access:W    DataWidth:0x1    // Writing to this register clears hdr registers and enables logging new error details.
+#define MULD_REG_STAT_FIC_MSG                                                                                0x4e00e4UL //Access:RC   DataWidth:0x20   // Number of FIC messages sent to the loader
+#define MULD_REG_DBG_PENDING_CCFC_REQ                                                                        0x4e00e8UL //Access:R    DataWidth:0x8    // number of CCFC requests wating for responses
+#define MULD_REG_DBG_PENDING_TCFC_REQ                                                                        0x4e00ecUL //Access:R    DataWidth:0x8    // number of TCFC requests wating for responses
+#define MULD_REG_LEN_ERR_LOG_1                                                                               0x4e00f0UL //Access:R    DataWidth:0x10   // Logging register for long message error: bit 0-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SGE fetch; bit 4- Message with BRB fetch; bits 5:6- QID; bits 7-RSV; bits 8-15 message CM length.
+#define MULD_REG_LEN_ERR_LOG_2                                                                               0x4e00f4UL //Access:R    DataWidth:0x20   // Logging register for long message error: bit 0:3 Segment message header length; 4:7 RSV;8:15 current length out of the segment message length array; 16:23 PCI response len (including BD and SGE fetches); 24:31 BRB
+#define MULD_REG_LEN_ERR_LOG_CLR                                                                             0x4e00f8UL //Access:W    DataWidth:0x1    // Writing to this register clears len err logging registers and enables logging new error details.
+#define MULD_REG_LEN_ERR_LOG_V                                                                               0x4e00fcUL //Access:R    DataWidth:0x1    // Indicates that the data at the len_err logging registers is valid.
+#define MULD_REG_INT_STS                                                                                     0x4e0180UL //Access:R    DataWidth:0x6    // Multi Field Register.
+  #define MULD_REG_INT_STS_ADDRESS_ERROR                                                                     (0x1<<0) // Signals an unknown address to the rf module.
+  #define MULD_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                               0
+  #define MULD_REG_INT_STS_LD_HDR_ERR                                                                        (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
+  #define MULD_REG_INT_STS_LD_HDR_ERR_SHIFT                                                                  1
+  #define MULD_REG_INT_STS_LD_SEG_MSG_ERR                                                                    (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
+  #define MULD_REG_INT_STS_LD_SEG_MSG_ERR_SHIFT                                                              2
+  #define MULD_REG_INT_STS_LD_TID_MINI_CACHE_ERR                                                             (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
+  #define MULD_REG_INT_STS_LD_TID_MINI_CACHE_ERR_SHIFT                                                       3
+  #define MULD_REG_INT_STS_LD_CID_MINI_CACHE_ERR                                                             (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
+  #define MULD_REG_INT_STS_LD_CID_MINI_CACHE_ERR_SHIFT                                                       4
+  #define MULD_REG_INT_STS_LD_LONG_MESSAGE                                                                   (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
+  #define MULD_REG_INT_STS_LD_LONG_MESSAGE_SHIFT                                                             5
+#define MULD_REG_INT_MASK                                                                                    0x4e0184UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define MULD_REG_INT_MASK_ADDRESS_ERROR                                                                    (0x1<<0) // This bit masks, when set, the Interrupt bit: MULD_REG_INT_STS.ADDRESS_ERROR .
+  #define MULD_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                              0
+  #define MULD_REG_INT_MASK_LD_HDR_ERR                                                                       (0x1<<1) // This bit masks, when set, the Interrupt bit: MULD_REG_INT_STS.LD_HDR_ERR .
+  #define MULD_REG_INT_MASK_LD_HDR_ERR_SHIFT                                                                 1
+  #define MULD_REG_INT_MASK_LD_SEG_MSG_ERR                                                                   (0x1<<2) // This bit masks, when set, the Interrupt bit: MULD_REG_INT_STS.LD_SEG_MSG_ERR .
+  #define MULD_REG_INT_MASK_LD_SEG_MSG_ERR_SHIFT                                                             2
+  #define MULD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR                                                            (0x1<<3) // This bit masks, when set, the Interrupt bit: MULD_REG_INT_STS.LD_TID_MINI_CACHE_ERR .
+  #define MULD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR_SHIFT                                                      3
+  #define MULD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR                                                            (0x1<<4) // This bit masks, when set, the Interrupt bit: MULD_REG_INT_STS.LD_CID_MINI_CACHE_ERR .
+  #define MULD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR_SHIFT                                                      4
+  #define MULD_REG_INT_MASK_LD_LONG_MESSAGE                                                                  (0x1<<5) // This bit masks, when set, the Interrupt bit: MULD_REG_INT_STS.LD_LONG_MESSAGE .
+  #define MULD_REG_INT_MASK_LD_LONG_MESSAGE_SHIFT                                                            5
+#define MULD_REG_INT_STS_WR                                                                                  0x4e0188UL //Access:WR   DataWidth:0x6    // Multi Field Register.
+  #define MULD_REG_INT_STS_WR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define MULD_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                            0
+  #define MULD_REG_INT_STS_WR_LD_HDR_ERR                                                                     (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
+  #define MULD_REG_INT_STS_WR_LD_HDR_ERR_SHIFT                                                               1
+  #define MULD_REG_INT_STS_WR_LD_SEG_MSG_ERR                                                                 (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
+  #define MULD_REG_INT_STS_WR_LD_SEG_MSG_ERR_SHIFT                                                           2
+  #define MULD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR                                                          (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
+  #define MULD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR_SHIFT                                                    3
+  #define MULD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR                                                          (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
+  #define MULD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR_SHIFT                                                    4
+  #define MULD_REG_INT_STS_WR_LD_LONG_MESSAGE                                                                (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
+  #define MULD_REG_INT_STS_WR_LD_LONG_MESSAGE_SHIFT                                                          5
+#define MULD_REG_INT_STS_CLR                                                                                 0x4e018cUL //Access:RC   DataWidth:0x6    // Multi Field Register.
+  #define MULD_REG_INT_STS_CLR_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define MULD_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                           0
+  #define MULD_REG_INT_STS_CLR_LD_HDR_ERR                                                                    (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
+  #define MULD_REG_INT_STS_CLR_LD_HDR_ERR_SHIFT                                                              1
+  #define MULD_REG_INT_STS_CLR_LD_SEG_MSG_ERR                                                                (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
+  #define MULD_REG_INT_STS_CLR_LD_SEG_MSG_ERR_SHIFT                                                          2
+  #define MULD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR                                                         (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
+  #define MULD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR_SHIFT                                                   3
+  #define MULD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR                                                         (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
+  #define MULD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR_SHIFT                                                   4
+  #define MULD_REG_INT_STS_CLR_LD_LONG_MESSAGE                                                               (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
+  #define MULD_REG_INT_STS_CLR_LD_LONG_MESSAGE_SHIFT                                                         5
+#define MULD_REG_PRTY_MASK_H_0_BB_K2                                                                         0x4e0204UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define MULD_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_BB_K2                                                   (0x1<<0) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT .
+  #define MULD_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_BB_K2_SHIFT                                             0
+  #define MULD_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_K2                                                   (0x1<<1) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
+  #define MULD_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_K2_SHIFT                                             1
+  #define MULD_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT_BB_K2                                                   (0x1<<2) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM008_I_ECC_RF_INT .
+  #define MULD_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT_BB_K2_SHIFT                                             2
+  #define MULD_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT_BB_K2                                                   (0x1<<3) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM007_I_ECC_RF_INT .
+  #define MULD_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT_BB_K2_SHIFT                                             3
+  #define MULD_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                     (0x1<<4) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define MULD_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                               4
+  #define MULD_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                     (0x1<<5) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define MULD_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                               5
+  #define MULD_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2                                                     (0x1<<6) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define MULD_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2_SHIFT                                               6
+  #define MULD_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2                                                     (0x1<<7) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
+  #define MULD_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2_SHIFT                                               7
+  #define MULD_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                     (0x1<<8) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define MULD_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                               8
+  #define MULD_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2                                                     (0x1<<9) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define MULD_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2_SHIFT                                               9
+#define MULD_REG_MEM_ECC_ENABLE_0_BB_K2                                                                      0x4e0210UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define MULD_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_BB_K2                                                    (0x1<<0) // Enable ECC for memory ecc instance muld.i_msgq_ram.i_ecc in module muld_i_msgq_ram_1
+  #define MULD_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_BB_K2_SHIFT                                              0
+  #define MULD_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_BB_K2                                                    (0x1<<1) // Enable ECC for memory ecc instance muld.i_bd_db_ram.i_ecc in module muld_i_bd_db_ram_1_k2
+  #define MULD_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_BB_K2_SHIFT                                              1
+  #define MULD_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_EN_BB_K2                                                    (0x1<<2) // Enable ECC for memory ecc instance muld.i_sge_db_ram.i_ecc in module muld_i_sge_db_ram_1_k2
+  #define MULD_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_EN_BB_K2_SHIFT                                              2
+  #define MULD_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_EN_BB_K2                                                    (0x1<<3) // Enable ECC for memory ecc instance muld.i_pci_rsep_buf_ram.i_ecc in module muld_i_pci_rsep_buf_ram_1
+  #define MULD_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_EN_BB_K2_SHIFT                                              3
+#define MULD_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                 0x4e0214UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define MULD_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_BB_K2                                             (0x1<<0) // Set parity only for memory ecc instance muld.i_msgq_ram.i_ecc in module muld_i_msgq_ram_1
+  #define MULD_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_BB_K2_SHIFT                                       0
+  #define MULD_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_BB_K2                                             (0x1<<1) // Set parity only for memory ecc instance muld.i_bd_db_ram.i_ecc in module muld_i_bd_db_ram_1_k2
+  #define MULD_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_BB_K2_SHIFT                                       1
+  #define MULD_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_PRTY_BB_K2                                             (0x1<<2) // Set parity only for memory ecc instance muld.i_sge_db_ram.i_ecc in module muld_i_sge_db_ram_1_k2
+  #define MULD_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_PRTY_BB_K2_SHIFT                                       2
+  #define MULD_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_PRTY_BB_K2                                             (0x1<<3) // Set parity only for memory ecc instance muld.i_pci_rsep_buf_ram.i_ecc in module muld_i_pci_rsep_buf_ram_1
+  #define MULD_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_PRTY_BB_K2_SHIFT                                       3
+#define MULD_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                             0x4e0218UL //Access:RC   DataWidth:0x4    // Multi Field Register.
+  #define MULD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_BB_K2                                      (0x1<<0) // Record if a correctable error occurred on memory ecc instance muld.i_msgq_ram.i_ecc in module muld_i_msgq_ram_1
+  #define MULD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_BB_K2_SHIFT                                0
+  #define MULD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_BB_K2                                      (0x1<<1) // Record if a correctable error occurred on memory ecc instance muld.i_bd_db_ram.i_ecc in module muld_i_bd_db_ram_1_k2
+  #define MULD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_BB_K2_SHIFT                                1
+  #define MULD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_CORRECT_BB_K2                                      (0x1<<2) // Record if a correctable error occurred on memory ecc instance muld.i_sge_db_ram.i_ecc in module muld_i_sge_db_ram_1_k2
+  #define MULD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_CORRECT_BB_K2_SHIFT                                2
+  #define MULD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_CORRECT_BB_K2                                      (0x1<<3) // Record if a correctable error occurred on memory ecc instance muld.i_pci_rsep_buf_ram.i_ecc in module muld_i_pci_rsep_buf_ram_1
+  #define MULD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_CORRECT_BB_K2_SHIFT                                3
+#define MULD_REG_MEM_ECC_EVENTS_BB_K2                                                                        0x4e021cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define MULD_REG_DESC_QUEUE_Q0                                                                               0x4e0400UL //Access:WB   DataWidth:0x23   // Descriptor FIFO queue0 - Debug access.
+#define MULD_REG_DESC_QUEUE_Q0_SIZE                                                                          150
+#define MULD_REG_DESC_QUEUE_Q1                                                                               0x4e0800UL //Access:WB   DataWidth:0x23   // Descriptor FIFO queue1 - Debug access.
+#define MULD_REG_DESC_QUEUE_Q1_SIZE                                                                          150
+#define MULD_REG_DESC_QUEUE_Q2                                                                               0x4e0c00UL //Access:WB   DataWidth:0x23   // Descriptor FIFO queue2 - Debug access::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD.
+#define MULD_REG_DESC_QUEUE_Q2_SIZE                                                                          150
+#define MULD_REG_DESC_QUEUE_Q3                                                                               0x4e1000UL //Access:WB   DataWidth:0x23   // Descriptor FIFO queue3 - Debug access::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD.
+#define MULD_REG_DESC_QUEUE_Q3_SIZE                                                                          150
+#define MULD_REG_L2MA_AGGR_CONFIG1_E5                                                                        0x4e1400UL //Access:RW   DataWidth:0x13   // Multi Field Register.
+  #define MULD_REG_L2MA_AGGR_CONFIG1_L2MA_EN_E5                                                              (0x1<<0) // Enables L2 message aggregation
+  #define MULD_REG_L2MA_AGGR_CONFIG1_L2MA_EN_E5_SHIFT                                                        0
+  #define MULD_REG_L2MA_AGGR_CONFIG1_IGNORE_CM_AGG_MSG_E5                                                    (0x1<<1) // indicates not to perform the aggregation logic if there is no L2MA command in the message (there is no L2MA command if DstStormFlg is reset OR ErrFlg is set). If this configuration is reset, messages without L2MA command are treated like messages with L2MA command where EnL2MA flag in the command is reset (i.e. they break existing aggregation).
+  #define MULD_REG_L2MA_AGGR_CONFIG1_IGNORE_CM_AGG_MSG_E5_SHIFT                                              1
+  #define MULD_REG_L2MA_AGGR_CONFIG1_BACK_2_BACK_E5                                                          (0x1<<2) // defines that only back-to-back aggregation is allowed
+  #define MULD_REG_L2MA_AGGR_CONFIG1_BACK_2_BACK_E5_SHIFT                                                    2
+  #define MULD_REG_L2MA_AGGR_CONFIG1_MIN_QUEUE_OCC_E5                                                        (0xff<<3) // the minimal queue occupancy below which new aggregations are not created
+  #define MULD_REG_L2MA_AGGR_CONFIG1_MIN_QUEUE_OCC_E5_SHIFT                                                  3
+  #define MULD_REG_L2MA_AGGR_CONFIG1_MAX_L2MA_DIFF_E5                                                        (0xff<<11) // the maximal difference between the serial number of the parent message and the serial number of its child message
+  #define MULD_REG_L2MA_AGGR_CONFIG1_MAX_L2MA_DIFF_E5_SHIFT                                                  11
+#define MULD_REG_L2MA_AGGR_CONFIG2_E5                                                                        0x4e1404UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define MULD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_0_E5                                                     (0x3f<<0) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
+  #define MULD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_0_E5_SHIFT                                               0
+  #define MULD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_1_E5                                                     (0x3f<<6) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
+  #define MULD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_1_E5_SHIFT                                               6
+  #define MULD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_2_E5                                                     (0x3f<<12) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
+  #define MULD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_2_E5_SHIFT                                               12
+  #define MULD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_3_E5                                                     (0x3f<<18) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
+  #define MULD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_3_E5_SHIFT                                               18
+#define MULD_REG_L2MA_SAME_OFFSET_SET_0_E5                                                                   0x4e1408UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_00_E5                                                       (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_00_E5_SHIFT                                                 0
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_01_E5                                                       (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_01_E5_SHIFT                                                 8
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_02_E5                                                       (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_02_E5_SHIFT                                                 16
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_03_E5                                                       (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_03_E5_SHIFT                                                 24
+#define MULD_REG_L2MA_SAME_OFFSET_SET_1_E5                                                                   0x4e140cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_10_E5                                                       (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_10_E5_SHIFT                                                 0
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_11_E5                                                       (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_11_E5_SHIFT                                                 8
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_12_E5                                                       (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_12_E5_SHIFT                                                 16
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_13_E5                                                       (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_13_E5_SHIFT                                                 24
+#define MULD_REG_L2MA_SAME_OFFSET_SET_2_E5                                                                   0x4e1410UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_20_E5                                                       (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_20_E5_SHIFT                                                 0
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_21_E5                                                       (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_21_E5_SHIFT                                                 8
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_22_E5                                                       (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_22_E5_SHIFT                                                 16
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_23_E5                                                       (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_23_E5_SHIFT                                                 24
+#define MULD_REG_L2MA_SAME_OFFSET_SET_3_E5                                                                   0x4e1414UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_30_E5                                                       (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_30_E5_SHIFT                                                 0
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_31_E5                                                       (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_31_E5_SHIFT                                                 8
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_32_E5                                                       (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_32_E5_SHIFT                                                 16
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_33_E5                                                       (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
+  #define MULD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_33_E5_SHIFT                                                 24
+#define MULD_REG_L2MA_SAME_LEN_SET_0_1_E5                                                                    0x4e1418UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MULD_REG_L2MA_SAME_LEN_SET_0_1_LEN_00_E5                                                           (0xf<<0) // length in 32b units from the same 00 .
+  #define MULD_REG_L2MA_SAME_LEN_SET_0_1_LEN_00_E5_SHIFT                                                     0
+  #define MULD_REG_L2MA_SAME_LEN_SET_0_1_LEN_01_E5                                                           (0xf<<4) // length in 32b units from the same 01 .
+  #define MULD_REG_L2MA_SAME_LEN_SET_0_1_LEN_01_E5_SHIFT                                                     4
+  #define MULD_REG_L2MA_SAME_LEN_SET_0_1_LEN_02_E5                                                           (0xf<<8) // length in 32b units from the same 02 .
+  #define MULD_REG_L2MA_SAME_LEN_SET_0_1_LEN_02_E5_SHIFT                                                     8
+  #define MULD_REG_L2MA_SAME_LEN_SET_0_1_LEN_03_E5                                                           (0xf<<12) // length in 32b units from the same 03 .
+  #define MULD_REG_L2MA_SAME_LEN_SET_0_1_LEN_03_E5_SHIFT                                                     12
+  #define MULD_REG_L2MA_SAME_LEN_SET_0_1_LEN_10_E5                                                           (0xf<<16) // length in 32b units from the same 10 .
+  #define MULD_REG_L2MA_SAME_LEN_SET_0_1_LEN_10_E5_SHIFT                                                     16
+  #define MULD_REG_L2MA_SAME_LEN_SET_0_1_LEN_11_E5                                                           (0xf<<20) // length in 32b units from the same 11 .
+  #define MULD_REG_L2MA_SAME_LEN_SET_0_1_LEN_11_E5_SHIFT                                                     20
+  #define MULD_REG_L2MA_SAME_LEN_SET_0_1_LEN_12_E5                                                           (0xf<<24) // length in 32b units from the same 12 .
+  #define MULD_REG_L2MA_SAME_LEN_SET_0_1_LEN_12_E5_SHIFT                                                     24
+  #define MULD_REG_L2MA_SAME_LEN_SET_0_1_LEN_13_E5                                                           (0xf<<28) // length in 32b units from the same 13 .
+  #define MULD_REG_L2MA_SAME_LEN_SET_0_1_LEN_13_E5_SHIFT                                                     28
+#define MULD_REG_L2MA_SAME_LEN_SET_2_3_E5                                                                    0x4e141cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MULD_REG_L2MA_SAME_LEN_SET_2_3_LEN_20_E5                                                           (0xf<<0) // length in 32b units from the same 20 .
+  #define MULD_REG_L2MA_SAME_LEN_SET_2_3_LEN_20_E5_SHIFT                                                     0
+  #define MULD_REG_L2MA_SAME_LEN_SET_2_3_LEN_21_E5                                                           (0xf<<4) // length in 32b units from the same 21 .
+  #define MULD_REG_L2MA_SAME_LEN_SET_2_3_LEN_21_E5_SHIFT                                                     4
+  #define MULD_REG_L2MA_SAME_LEN_SET_2_3_LEN_22_E5                                                           (0xf<<8) // length in 32b units from the same 22 .
+  #define MULD_REG_L2MA_SAME_LEN_SET_2_3_LEN_22_E5_SHIFT                                                     8
+  #define MULD_REG_L2MA_SAME_LEN_SET_2_3_LEN_23_E5                                                           (0xf<<12) // length in 32b units from the same 23 .
+  #define MULD_REG_L2MA_SAME_LEN_SET_2_3_LEN_23_E5_SHIFT                                                     12
+  #define MULD_REG_L2MA_SAME_LEN_SET_2_3_LEN_30_E5                                                           (0xf<<16) // length in 32b units from the same 30 .
+  #define MULD_REG_L2MA_SAME_LEN_SET_2_3_LEN_30_E5_SHIFT                                                     16
+  #define MULD_REG_L2MA_SAME_LEN_SET_2_3_LEN_31_E5                                                           (0xf<<20) // length in 32b units from the same 31 .
+  #define MULD_REG_L2MA_SAME_LEN_SET_2_3_LEN_31_E5_SHIFT                                                     20
+  #define MULD_REG_L2MA_SAME_LEN_SET_2_3_LEN_32_E5                                                           (0xf<<24) // length in 32b units from the same 32 .
+  #define MULD_REG_L2MA_SAME_LEN_SET_2_3_LEN_32_E5_SHIFT                                                     24
+  #define MULD_REG_L2MA_SAME_LEN_SET_2_3_LEN_33_E5                                                           (0xf<<28) // length in 32b units from the same 33 .
+  #define MULD_REG_L2MA_SAME_LEN_SET_2_3_LEN_33_E5_SHIFT                                                     28
+#define MULD_REG_L2MA_SAME_MASK_SET_0_E5                                                                     0x4e1420UL //Access:RW   DataWidth:0x20   // bit-mask on the selected 32B same 0 parameters .
+#define MULD_REG_L2MA_SAME_MASK_SET_1_E5                                                                     0x4e1424UL //Access:RW   DataWidth:0x20   // bit-mask on the selected 32B same 1 parameters .
+#define MULD_REG_L2MA_SAME_MASK_SET_2_E5                                                                     0x4e1428UL //Access:RW   DataWidth:0x20   // bit-mask on the selected 32B same 2 parameters .
+#define MULD_REG_L2MA_SAME_MASK_SET_3_E5                                                                     0x4e142cUL //Access:RW   DataWidth:0x20   // bit-mask on the selected 32B same 3 parameters .
+#define MULD_REG_L2MA_DUP_OFFSET_SET_0_E5                                                                    0x4e1430UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_00_E5                                                    (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_00_E5_SHIFT                                              0
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_01_E5                                                    (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_01_E5_SHIFT                                              8
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_02_E5                                                    (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_02_E5_SHIFT                                              16
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_03_E5                                                    (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_03_E5_SHIFT                                              24
+#define MULD_REG_L2MA_DUP_OFFSET_SET_1_E5                                                                    0x4e1434UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_10_E5                                                    (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_10_E5_SHIFT                                              0
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_11_E5                                                    (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_11_E5_SHIFT                                              8
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_12_E5                                                    (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_12_E5_SHIFT                                              16
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_13_E5                                                    (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_13_E5_SHIFT                                              24
+#define MULD_REG_L2MA_DUP_OFFSET_SET_2_E5                                                                    0x4e1438UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_20_E5                                                    (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_20_E5_SHIFT                                              0
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_21_E5                                                    (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_21_E5_SHIFT                                              8
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_22_E5                                                    (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_22_E5_SHIFT                                              16
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_23_E5                                                    (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_23_E5_SHIFT                                              24
+#define MULD_REG_L2MA_DUP_OFFSET_SET_3_E5                                                                    0x4e143cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_30_E5                                                    (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_30_E5_SHIFT                                              0
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_31_E5                                                    (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_31_E5_SHIFT                                              8
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_32_E5                                                    (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_32_E5_SHIFT                                              16
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_33_E5                                                    (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
+  #define MULD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_33_E5_SHIFT                                              24
+#define MULD_REG_L2MA_DUP_LEN_SET_0_E5                                                                       0x4e1440UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define MULD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_00_E5                                                          (0x3f<<0) // length in 32b units from the dup 00 .
+  #define MULD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_00_E5_SHIFT                                                    0
+  #define MULD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_01_E5                                                          (0x3f<<6) // length in 32b units from the dup 01 .
+  #define MULD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_01_E5_SHIFT                                                    6
+  #define MULD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_02_E5                                                          (0x3f<<12) // length in 32b units from the dup 02 .
+  #define MULD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_02_E5_SHIFT                                                    12
+  #define MULD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_03_E5                                                          (0x3f<<18) // length in 32b units from the dup 03 .
+  #define MULD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_03_E5_SHIFT                                                    18
+#define MULD_REG_L2MA_DUP_LEN_SET_1_E5                                                                       0x4e1444UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define MULD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_10_E5                                                          (0x3f<<0) // length in 32b units from the dup 10 .
+  #define MULD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_10_E5_SHIFT                                                    0
+  #define MULD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_11_E5                                                          (0x3f<<6) // length in 32b units from the dup 11 .
+  #define MULD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_11_E5_SHIFT                                                    6
+  #define MULD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_12_E5                                                          (0x3f<<12) // length in 32b units from the dup 12 .
+  #define MULD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_12_E5_SHIFT                                                    12
+  #define MULD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_13_E5                                                          (0x3f<<18) // length in 32b units from the dup 13 .
+  #define MULD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_13_E5_SHIFT                                                    18
+#define MULD_REG_L2MA_DUP_LEN_SET_2_E5                                                                       0x4e1448UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define MULD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_20_E5                                                          (0x3f<<0) // length in 32b units from the dup 20 .
+  #define MULD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_20_E5_SHIFT                                                    0
+  #define MULD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_21_E5                                                          (0x3f<<6) // length in 32b units from the dup 21 .
+  #define MULD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_21_E5_SHIFT                                                    6
+  #define MULD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_22_E5                                                          (0x3f<<12) // length in 32b units from the dup 22 .
+  #define MULD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_22_E5_SHIFT                                                    12
+  #define MULD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_23_E5                                                          (0x3f<<18) // length in 32b units from the dup 23 .
+  #define MULD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_23_E5_SHIFT                                                    18
+#define MULD_REG_L2MA_DUP_LEN_SET_3_E5                                                                       0x4e144cUL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define MULD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_30_E5                                                          (0x3f<<0) // length in 32b units from the dup 30 .
+  #define MULD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_30_E5_SHIFT                                                    0
+  #define MULD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_31_E5                                                          (0x3f<<6) // length in 32b units from the dup 31 .
+  #define MULD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_31_E5_SHIFT                                                    6
+  #define MULD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_32_E5                                                          (0x3f<<12) // length in 32b units from the dup 32 .
+  #define MULD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_32_E5_SHIFT                                                    12
+  #define MULD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_33_E5                                                          (0x3f<<18) // length in 32b units from the dup 33 .
+  #define MULD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_33_E5_SHIFT                                                    18
+#define MULD_REG_L2MA_FLOW_ID_E5                                                                             0x4e1450UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define MULD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_0_E5                                                         (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
+  #define MULD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_0_E5_SHIFT                                                   0
+  #define MULD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_1_E5                                                         (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
+  #define MULD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_1_E5_SHIFT                                                   1
+  #define MULD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_2_E5                                                         (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
+  #define MULD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_2_E5_SHIFT                                                   2
+  #define MULD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_3_E5                                                         (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
+  #define MULD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_3_E5_SHIFT                                                   3
+  #define MULD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_0_E5                                                          (0x1f<<4) // offset of the flow-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of the incoming message (i.e. max value is 23). This parameter is NA if FlowIdInclude is reset. For set 0 .
+  #define MULD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_0_E5_SHIFT                                                    4
+  #define MULD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_1_E5                                                          (0x1f<<9) // offset of the flow-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of the incoming message (i.e. max value is 23). This parameter is NA if FlowIdInclude is reset. For set 1 .
+  #define MULD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_1_E5_SHIFT                                                    9
+  #define MULD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_2_E5                                                          (0x1f<<14) // offset of the flow-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of the incoming message (i.e. max value is 23). This parameter is NA if FlowIdInclude is reset. For set 2 .
+  #define MULD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_2_E5_SHIFT                                                    14
+  #define MULD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_3_E5                                                          (0x1f<<19) // offset of the flow-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of the incoming message (i.e. max value is 23). This parameter is NA if FlowIdInclude is reset. For set 3 .
+  #define MULD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_3_E5_SHIFT                                                    19
+#define MULD_REG_L2MA_SN_OFFSET_E5                                                                           0x4e1454UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MULD_REG_L2MA_SN_OFFSET_SN_OFFSET_0_E5                                                             (0xff<<0) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 0.
+  #define MULD_REG_L2MA_SN_OFFSET_SN_OFFSET_0_E5_SHIFT                                                       0
+  #define MULD_REG_L2MA_SN_OFFSET_SN_OFFSET_1_E5                                                             (0xff<<8) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 1.
+  #define MULD_REG_L2MA_SN_OFFSET_SN_OFFSET_1_E5_SHIFT                                                       8
+  #define MULD_REG_L2MA_SN_OFFSET_SN_OFFSET_2_E5                                                             (0xff<<16) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 2.
+  #define MULD_REG_L2MA_SN_OFFSET_SN_OFFSET_2_E5_SHIFT                                                       16
+  #define MULD_REG_L2MA_SN_OFFSET_SN_OFFSET_3_E5                                                             (0xff<<24) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 3.
+  #define MULD_REG_L2MA_SN_OFFSET_SN_OFFSET_3_E5_SHIFT                                                       24
+#define MULD_REG_L2MA_MAX_L2MA_CHILD_E5                                                                      0x4e1458UL //Access:RW   DataWidth:0x10   // Multi Field Register.
+  #define MULD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_0_E5                                                         (0xf<<0) // the maximal number of children in a specific aggregation. for set 0.
+  #define MULD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_0_E5_SHIFT                                                   0
+  #define MULD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_1_E5                                                         (0xf<<4) // the maximal number of children in a specific aggregation. for set 1.
+  #define MULD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_1_E5_SHIFT                                                   4
+  #define MULD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_2_E5                                                         (0xf<<8) // the maximal number of children in a specific aggregation. for set 2.
+  #define MULD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_2_E5_SHIFT                                                   8
+  #define MULD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_3_E5                                                         (0xf<<12) // the maximal number of children in a specific aggregation. for set 3.
+  #define MULD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_3_E5_SHIFT                                                   12
+#define MULD_REG_L2MA_INC_L2MA_EVENT_ID_E5                                                                   0x4e145cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MULD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_0_E5                                                  (0xff<<0) // The value by which to increment the event-ID in case of successful aggregation. for set 0.
+  #define MULD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_0_E5_SHIFT                                            0
+  #define MULD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_1_E5                                                  (0xff<<8) // The value by which to increment the event-ID in case of successful aggregation. for set 1.
+  #define MULD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_1_E5_SHIFT                                            8
+  #define MULD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_2_E5                                                  (0xff<<16) // The value by which to increment the event-ID in case of successful aggregation. for set 2.
+  #define MULD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_2_E5_SHIFT                                            16
+  #define MULD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_3_E5                                                  (0xff<<24) // The value by which to increment the event-ID in case of successful aggregation. for set 3.
+  #define MULD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_3_E5_SHIFT                                            24
+#define MULD_REG_LD_MAX_MSG_SIZE_E5                                                                          0x4e1460UL //Access:RW   DataWidth:0x4    // maximum loader size in 256 bit words
+#define MULD_REG_PAGE_SIZE_E5                                                                                0x4e1464UL //Access:RW   DataWidth:0x20   // page size in bytes
+#define MULD_REG_DBG_SELECT                                                                                  0x4e1600UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define MULD_REG_DBG_DWORD_ENABLE                                                                            0x4e1604UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define MULD_REG_DBG_SHIFT                                                                                   0x4e1608UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define MULD_REG_DBG_FORCE_VALID                                                                             0x4e160cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define MULD_REG_DBG_FORCE_FRAME                                                                             0x4e1610UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define MULD_REG_DBG_OUT_DATA                                                                                0x4e1620UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define MULD_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define MULD_REG_DBG_OUT_VALID                                                                               0x4e1640UL //Access:R    DataWidth:0x4    // Dbgmux output valid
+#define MULD_REG_DBG_OUT_FRAME                                                                               0x4e1644UL //Access:R    DataWidth:0x4    // Dbgmux output frame
+#define MULD_REG_FIC_INPUT_FIFO                                                                              0x4e2000UL //Access:WB   DataWidth:0x80   // Access to input FIC FIFO
+#define MULD_REG_FIC_INPUT_FIFO_SIZE                                                                         176
+#define MULD_REG_BD_DB_ARR_DW                                                                                0x4e4000UL //Access:WB   DataWidth:0xb5   // Access the BD DB - Fields order[Link page]: [180] Next address valid; [179:178] Endianity bits; [177] No snoop flag; [176] Releaxed ordering flag;[175:173] ATC flags; [172:161] TPH flags; [160] Ring type; [159:143] Next BD offset; [144:128] FID; [127:64] Next base address; [63:0] Base address::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD. Access the BD DB - Fields order[PBL]: [180] Next address valid; [179:178] Endianity bits; [177] No snoop flag; [176] Releaxed ordering flag;[175:173] ATC flags; [172:161] TPH flags; [160] Ring type; [159:143] Next BD offset; [144:128] FID; [127:64] ;PBL size(in number of entries) [63:0] PBL Base address::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD.
+#define MULD_REG_BD_DB_ARR_DW_SIZE_BB                                                                        2048
+#define MULD_REG_BD_DB_ARR_DW_SIZE_K2                                                                        2560
+#define MULD_REG_BD_DB_ARR_DW_SIZE_E5                                                                        4096
+#define MULD_REG_SGE_DB_ARR_DW                                                                               0x4e8000UL //Access:WB   DataWidth:0xb5   // Access the SGE DB - Fields order[Link page]: [180] Next address valid; [179:178] Endianity bits; [177] No snoop flag; [176] Releaxed ordering flag;[175:173] ATC flags; [172:161] TPH flags; [160] Ring type; [159:143] Next SGE offset; [144:128] FID; [127:64] Next base address; [63:0] Base address::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD. Access the SGE DB - Fields order[PBL]: [180] Next address valid; [179:178] Endianity bits; [177] No snoop flag; [176] Releaxed ordering flag;[175:173] ATC flags; [172:161] TPH flags; [160] Ring type; [159:143] Next SGE offset; [144:128] FID; [127:64] ;PBL size(in number of entries) [63:0] PBL Base address::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD.
+#define MULD_REG_SGE_DB_ARR_DW_SIZE_BB                                                                       2048
+#define MULD_REG_SGE_DB_ARR_DW_SIZE_K2                                                                       2560
+#define MULD_REG_SGE_DB_ARR_DW_SIZE_E5                                                                       4096
+#define MULD_REG_QUEUE_MSG_MEM                                                                               0x4f0000UL //Access:WB   DataWidth:0x80   // Debug access to The message queue memory.
+#define MULD_REG_QUEUE_MSG_MEM_SIZE                                                                          7500
+#define NIG_REG_INT_STS_0                                                                                    0x500040UL //Access:R    DataWidth:0xe    // Multi Field Register.
+  #define NIG_REG_INT_STS_0_ADDRESS_ERROR                                                                    (0x1<<0) // Signals an unknown address to the RF module.
+  #define NIG_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                              0
+  #define NIG_REG_INT_STS_0_DEBUG_FIFO_ERROR                                                                 (0x1<<1) // FIFO error in debug traffic FIFO.
+  #define NIG_REG_INT_STS_0_DEBUG_FIFO_ERROR_SHIFT                                                           1
+  #define NIG_REG_INT_STS_0_DORQ_FIFO_ERROR                                                                  (0x1<<2) // FIFO error in DORQ FIFO.
+  #define NIG_REG_INT_STS_0_DORQ_FIFO_ERROR_SHIFT                                                            2
+  #define NIG_REG_INT_STS_0_DBG_SYNCFIFO_ERROR_WR                                                            (0x1<<3) // FIFO error in debug traffic sync FIFO.
+  #define NIG_REG_INT_STS_0_DBG_SYNCFIFO_ERROR_WR_SHIFT                                                      3
+  #define NIG_REG_INT_STS_0_DORQ_SYNCFIFO_ERROR_WR                                                           (0x1<<4) // FIFO error in DORQ sync FIFO.
+  #define NIG_REG_INT_STS_0_DORQ_SYNCFIFO_ERROR_WR_SHIFT                                                     4
+  #define NIG_REG_INT_STS_0_STORM_SYNCFIFO_ERROR_WR                                                          (0x1<<5) // FIFO error in STORM sync FIFO.
+  #define NIG_REG_INT_STS_0_STORM_SYNCFIFO_ERROR_WR_SHIFT                                                    5
+  #define NIG_REG_INT_STS_0_DBGMUX_SYNCFIFO_ERROR_WR                                                         (0x1<<6) // FIFO error in DBGMUX sync FIFO.
+  #define NIG_REG_INT_STS_0_DBGMUX_SYNCFIFO_ERROR_WR_SHIFT                                                   6
+  #define NIG_REG_INT_STS_0_MSDM_SYNCFIFO_ERROR_WR                                                           (0x1<<7) // FIFO error in MSDM sync FIFO.
+  #define NIG_REG_INT_STS_0_MSDM_SYNCFIFO_ERROR_WR_SHIFT                                                     7
+  #define NIG_REG_INT_STS_0_TSDM_SYNCFIFO_ERROR_WR                                                           (0x1<<8) // FIFO error in TSDM sync FIFO.
+  #define NIG_REG_INT_STS_0_TSDM_SYNCFIFO_ERROR_WR_SHIFT                                                     8
+  #define NIG_REG_INT_STS_0_USDM_SYNCFIFO_ERROR_WR                                                           (0x1<<9) // FIFO error in USDM sync FIFO.
+  #define NIG_REG_INT_STS_0_USDM_SYNCFIFO_ERROR_WR_SHIFT                                                     9
+  #define NIG_REG_INT_STS_0_XSDM_SYNCFIFO_ERROR_WR                                                           (0x1<<10) // FIFO error in XSDM sync FIFO.
+  #define NIG_REG_INT_STS_0_XSDM_SYNCFIFO_ERROR_WR_SHIFT                                                     10
+  #define NIG_REG_INT_STS_0_YSDM_SYNCFIFO_ERROR_WR                                                           (0x1<<11) // FIFO error in YSDM sync FIFO.
+  #define NIG_REG_INT_STS_0_YSDM_SYNCFIFO_ERROR_WR_SHIFT                                                     11
+  #define NIG_REG_INT_STS_0_TX_OOO_RFIFO_ERROR_WR_E5                                                         (0x1<<12) // FIFO error in Out of order RFIFO FIFO.
+  #define NIG_REG_INT_STS_0_TX_OOO_RFIFO_ERROR_WR_E5_SHIFT                                                   12
+  #define NIG_REG_INT_STS_0_LB_OOO_RFIFO_ERROR_WR_E5                                                         (0x1<<13) // FIFO error in Out of order RFIFO FIFO.
+  #define NIG_REG_INT_STS_0_LB_OOO_RFIFO_ERROR_WR_E5_SHIFT                                                   13
+#define NIG_REG_INT_MASK_0                                                                                   0x500044UL //Access:RW   DataWidth:0xe    // Multi Field Register.
+  #define NIG_REG_INT_MASK_0_ADDRESS_ERROR                                                                   (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.ADDRESS_ERROR .
+  #define NIG_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                             0
+  #define NIG_REG_INT_MASK_0_DEBUG_FIFO_ERROR                                                                (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.DEBUG_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_0_DEBUG_FIFO_ERROR_SHIFT                                                          1
+  #define NIG_REG_INT_MASK_0_DORQ_FIFO_ERROR                                                                 (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.DORQ_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_0_DORQ_FIFO_ERROR_SHIFT                                                           2
+  #define NIG_REG_INT_MASK_0_DBG_SYNCFIFO_ERROR_WR                                                           (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.DBG_SYNCFIFO_ERROR_WR .
+  #define NIG_REG_INT_MASK_0_DBG_SYNCFIFO_ERROR_WR_SHIFT                                                     3
+  #define NIG_REG_INT_MASK_0_DORQ_SYNCFIFO_ERROR_WR                                                          (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.DORQ_SYNCFIFO_ERROR_WR .
+  #define NIG_REG_INT_MASK_0_DORQ_SYNCFIFO_ERROR_WR_SHIFT                                                    4
+  #define NIG_REG_INT_MASK_0_STORM_SYNCFIFO_ERROR_WR                                                         (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.STORM_SYNCFIFO_ERROR_WR .
+  #define NIG_REG_INT_MASK_0_STORM_SYNCFIFO_ERROR_WR_SHIFT                                                   5
+  #define NIG_REG_INT_MASK_0_DBGMUX_SYNCFIFO_ERROR_WR                                                        (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.DBGMUX_SYNCFIFO_ERROR_WR .
+  #define NIG_REG_INT_MASK_0_DBGMUX_SYNCFIFO_ERROR_WR_SHIFT                                                  6
+  #define NIG_REG_INT_MASK_0_MSDM_SYNCFIFO_ERROR_WR                                                          (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.MSDM_SYNCFIFO_ERROR_WR .
+  #define NIG_REG_INT_MASK_0_MSDM_SYNCFIFO_ERROR_WR_SHIFT                                                    7
+  #define NIG_REG_INT_MASK_0_TSDM_SYNCFIFO_ERROR_WR                                                          (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.TSDM_SYNCFIFO_ERROR_WR .
+  #define NIG_REG_INT_MASK_0_TSDM_SYNCFIFO_ERROR_WR_SHIFT                                                    8
+  #define NIG_REG_INT_MASK_0_USDM_SYNCFIFO_ERROR_WR                                                          (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.USDM_SYNCFIFO_ERROR_WR .
+  #define NIG_REG_INT_MASK_0_USDM_SYNCFIFO_ERROR_WR_SHIFT                                                    9
+  #define NIG_REG_INT_MASK_0_XSDM_SYNCFIFO_ERROR_WR                                                          (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.XSDM_SYNCFIFO_ERROR_WR .
+  #define NIG_REG_INT_MASK_0_XSDM_SYNCFIFO_ERROR_WR_SHIFT                                                    10
+  #define NIG_REG_INT_MASK_0_YSDM_SYNCFIFO_ERROR_WR                                                          (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.YSDM_SYNCFIFO_ERROR_WR .
+  #define NIG_REG_INT_MASK_0_YSDM_SYNCFIFO_ERROR_WR_SHIFT                                                    11
+  #define NIG_REG_INT_MASK_0_TX_OOO_RFIFO_ERROR_WR_E5                                                        (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.TX_OOO_RFIFO_ERROR_WR .
+  #define NIG_REG_INT_MASK_0_TX_OOO_RFIFO_ERROR_WR_E5_SHIFT                                                  12
+  #define NIG_REG_INT_MASK_0_LB_OOO_RFIFO_ERROR_WR_E5                                                        (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.LB_OOO_RFIFO_ERROR_WR .
+  #define NIG_REG_INT_MASK_0_LB_OOO_RFIFO_ERROR_WR_E5_SHIFT                                                  13
+#define NIG_REG_INT_STS_WR_0                                                                                 0x500048UL //Access:WR   DataWidth:0xe    // Multi Field Register.
+  #define NIG_REG_INT_STS_WR_0_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the RF module.
+  #define NIG_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                           0
+  #define NIG_REG_INT_STS_WR_0_DEBUG_FIFO_ERROR                                                              (0x1<<1) // FIFO error in debug traffic FIFO.
+  #define NIG_REG_INT_STS_WR_0_DEBUG_FIFO_ERROR_SHIFT                                                        1
+  #define NIG_REG_INT_STS_WR_0_DORQ_FIFO_ERROR                                                               (0x1<<2) // FIFO error in DORQ FIFO.
+  #define NIG_REG_INT_STS_WR_0_DORQ_FIFO_ERROR_SHIFT                                                         2
+  #define NIG_REG_INT_STS_WR_0_DBG_SYNCFIFO_ERROR_WR                                                         (0x1<<3) // FIFO error in debug traffic sync FIFO.
+  #define NIG_REG_INT_STS_WR_0_DBG_SYNCFIFO_ERROR_WR_SHIFT                                                   3
+  #define NIG_REG_INT_STS_WR_0_DORQ_SYNCFIFO_ERROR_WR                                                        (0x1<<4) // FIFO error in DORQ sync FIFO.
+  #define NIG_REG_INT_STS_WR_0_DORQ_SYNCFIFO_ERROR_WR_SHIFT                                                  4
+  #define NIG_REG_INT_STS_WR_0_STORM_SYNCFIFO_ERROR_WR                                                       (0x1<<5) // FIFO error in STORM sync FIFO.
+  #define NIG_REG_INT_STS_WR_0_STORM_SYNCFIFO_ERROR_WR_SHIFT                                                 5
+  #define NIG_REG_INT_STS_WR_0_DBGMUX_SYNCFIFO_ERROR_WR                                                      (0x1<<6) // FIFO error in DBGMUX sync FIFO.
+  #define NIG_REG_INT_STS_WR_0_DBGMUX_SYNCFIFO_ERROR_WR_SHIFT                                                6
+  #define NIG_REG_INT_STS_WR_0_MSDM_SYNCFIFO_ERROR_WR                                                        (0x1<<7) // FIFO error in MSDM sync FIFO.
+  #define NIG_REG_INT_STS_WR_0_MSDM_SYNCFIFO_ERROR_WR_SHIFT                                                  7
+  #define NIG_REG_INT_STS_WR_0_TSDM_SYNCFIFO_ERROR_WR                                                        (0x1<<8) // FIFO error in TSDM sync FIFO.
+  #define NIG_REG_INT_STS_WR_0_TSDM_SYNCFIFO_ERROR_WR_SHIFT                                                  8
+  #define NIG_REG_INT_STS_WR_0_USDM_SYNCFIFO_ERROR_WR                                                        (0x1<<9) // FIFO error in USDM sync FIFO.
+  #define NIG_REG_INT_STS_WR_0_USDM_SYNCFIFO_ERROR_WR_SHIFT                                                  9
+  #define NIG_REG_INT_STS_WR_0_XSDM_SYNCFIFO_ERROR_WR                                                        (0x1<<10) // FIFO error in XSDM sync FIFO.
+  #define NIG_REG_INT_STS_WR_0_XSDM_SYNCFIFO_ERROR_WR_SHIFT                                                  10
+  #define NIG_REG_INT_STS_WR_0_YSDM_SYNCFIFO_ERROR_WR                                                        (0x1<<11) // FIFO error in YSDM sync FIFO.
+  #define NIG_REG_INT_STS_WR_0_YSDM_SYNCFIFO_ERROR_WR_SHIFT                                                  11
+  #define NIG_REG_INT_STS_WR_0_TX_OOO_RFIFO_ERROR_WR_E5                                                      (0x1<<12) // FIFO error in Out of order RFIFO FIFO.
+  #define NIG_REG_INT_STS_WR_0_TX_OOO_RFIFO_ERROR_WR_E5_SHIFT                                                12
+  #define NIG_REG_INT_STS_WR_0_LB_OOO_RFIFO_ERROR_WR_E5                                                      (0x1<<13) // FIFO error in Out of order RFIFO FIFO.
+  #define NIG_REG_INT_STS_WR_0_LB_OOO_RFIFO_ERROR_WR_E5_SHIFT                                                13
+#define NIG_REG_INT_STS_CLR_0                                                                                0x50004cUL //Access:RC   DataWidth:0xe    // Multi Field Register.
+  #define NIG_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the RF module.
+  #define NIG_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                          0
+  #define NIG_REG_INT_STS_CLR_0_DEBUG_FIFO_ERROR                                                             (0x1<<1) // FIFO error in debug traffic FIFO.
+  #define NIG_REG_INT_STS_CLR_0_DEBUG_FIFO_ERROR_SHIFT                                                       1
+  #define NIG_REG_INT_STS_CLR_0_DORQ_FIFO_ERROR                                                              (0x1<<2) // FIFO error in DORQ FIFO.
+  #define NIG_REG_INT_STS_CLR_0_DORQ_FIFO_ERROR_SHIFT                                                        2
+  #define NIG_REG_INT_STS_CLR_0_DBG_SYNCFIFO_ERROR_WR                                                        (0x1<<3) // FIFO error in debug traffic sync FIFO.
+  #define NIG_REG_INT_STS_CLR_0_DBG_SYNCFIFO_ERROR_WR_SHIFT                                                  3
+  #define NIG_REG_INT_STS_CLR_0_DORQ_SYNCFIFO_ERROR_WR                                                       (0x1<<4) // FIFO error in DORQ sync FIFO.
+  #define NIG_REG_INT_STS_CLR_0_DORQ_SYNCFIFO_ERROR_WR_SHIFT                                                 4
+  #define NIG_REG_INT_STS_CLR_0_STORM_SYNCFIFO_ERROR_WR                                                      (0x1<<5) // FIFO error in STORM sync FIFO.
+  #define NIG_REG_INT_STS_CLR_0_STORM_SYNCFIFO_ERROR_WR_SHIFT                                                5
+  #define NIG_REG_INT_STS_CLR_0_DBGMUX_SYNCFIFO_ERROR_WR                                                     (0x1<<6) // FIFO error in DBGMUX sync FIFO.
+  #define NIG_REG_INT_STS_CLR_0_DBGMUX_SYNCFIFO_ERROR_WR_SHIFT                                               6
+  #define NIG_REG_INT_STS_CLR_0_MSDM_SYNCFIFO_ERROR_WR                                                       (0x1<<7) // FIFO error in MSDM sync FIFO.
+  #define NIG_REG_INT_STS_CLR_0_MSDM_SYNCFIFO_ERROR_WR_SHIFT                                                 7
+  #define NIG_REG_INT_STS_CLR_0_TSDM_SYNCFIFO_ERROR_WR                                                       (0x1<<8) // FIFO error in TSDM sync FIFO.
+  #define NIG_REG_INT_STS_CLR_0_TSDM_SYNCFIFO_ERROR_WR_SHIFT                                                 8
+  #define NIG_REG_INT_STS_CLR_0_USDM_SYNCFIFO_ERROR_WR                                                       (0x1<<9) // FIFO error in USDM sync FIFO.
+  #define NIG_REG_INT_STS_CLR_0_USDM_SYNCFIFO_ERROR_WR_SHIFT                                                 9
+  #define NIG_REG_INT_STS_CLR_0_XSDM_SYNCFIFO_ERROR_WR                                                       (0x1<<10) // FIFO error in XSDM sync FIFO.
+  #define NIG_REG_INT_STS_CLR_0_XSDM_SYNCFIFO_ERROR_WR_SHIFT                                                 10
+  #define NIG_REG_INT_STS_CLR_0_YSDM_SYNCFIFO_ERROR_WR                                                       (0x1<<11) // FIFO error in YSDM sync FIFO.
+  #define NIG_REG_INT_STS_CLR_0_YSDM_SYNCFIFO_ERROR_WR_SHIFT                                                 11
+  #define NIG_REG_INT_STS_CLR_0_TX_OOO_RFIFO_ERROR_WR_E5                                                     (0x1<<12) // FIFO error in Out of order RFIFO FIFO.
+  #define NIG_REG_INT_STS_CLR_0_TX_OOO_RFIFO_ERROR_WR_E5_SHIFT                                               12
+  #define NIG_REG_INT_STS_CLR_0_LB_OOO_RFIFO_ERROR_WR_E5                                                     (0x1<<13) // FIFO error in Out of order RFIFO FIFO.
+  #define NIG_REG_INT_STS_CLR_0_LB_OOO_RFIFO_ERROR_WR_E5_SHIFT                                               13
+#define NIG_REG_INT_STS_1                                                                                    0x500050UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define NIG_REG_INT_STS_1_TX_SOPQ0_ERROR                                                                   (0x1<<0) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_1_TX_SOPQ0_ERROR_SHIFT                                                             0
+  #define NIG_REG_INT_STS_1_TX_SOPQ1_ERROR                                                                   (0x1<<1) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_1_TX_SOPQ1_ERROR_SHIFT                                                             1
+  #define NIG_REG_INT_STS_1_TX_SOPQ2_ERROR                                                                   (0x1<<2) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_1_TX_SOPQ2_ERROR_SHIFT                                                             2
+  #define NIG_REG_INT_STS_1_TX_SOPQ3_ERROR                                                                   (0x1<<3) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_1_TX_SOPQ3_ERROR_SHIFT                                                             3
+  #define NIG_REG_INT_STS_1_TX_SOPQ4_ERROR                                                                   (0x1<<4) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_1_TX_SOPQ4_ERROR_SHIFT                                                             4
+  #define NIG_REG_INT_STS_1_TX_SOPQ5_ERROR                                                                   (0x1<<5) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_1_TX_SOPQ5_ERROR_SHIFT                                                             5
+  #define NIG_REG_INT_STS_1_TX_SOPQ6_ERROR                                                                   (0x1<<6) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_1_TX_SOPQ6_ERROR_SHIFT                                                             6
+  #define NIG_REG_INT_STS_1_TX_SOPQ7_ERROR                                                                   (0x1<<7) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_1_TX_SOPQ7_ERROR_SHIFT                                                             7
+  #define NIG_REG_INT_STS_1_TX_SOPQ8_ERROR                                                                   (0x1<<8) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_1_TX_SOPQ8_ERROR_SHIFT                                                             8
+  #define NIG_REG_INT_STS_1_TX_SOPQ9_ERROR                                                                   (0x1<<9) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_1_TX_SOPQ9_ERROR_SHIFT                                                             9
+  #define NIG_REG_INT_STS_1_TX_SOPQ10_ERROR                                                                  (0x1<<10) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_1_TX_SOPQ10_ERROR_SHIFT                                                            10
+  #define NIG_REG_INT_STS_1_TX_SOPQ11_ERROR                                                                  (0x1<<11) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_1_TX_SOPQ11_ERROR_SHIFT                                                            11
+  #define NIG_REG_INT_STS_1_TX_SOPQ12_ERROR                                                                  (0x1<<12) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_1_TX_SOPQ12_ERROR_SHIFT                                                            12
+  #define NIG_REG_INT_STS_1_TX_SOPQ13_ERROR                                                                  (0x1<<13) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_1_TX_SOPQ13_ERROR_SHIFT                                                            13
+  #define NIG_REG_INT_STS_1_TX_SOPQ14_ERROR                                                                  (0x1<<14) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_1_TX_SOPQ14_ERROR_SHIFT                                                            14
+  #define NIG_REG_INT_STS_1_TX_SOPQ15_ERROR                                                                  (0x1<<15) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_1_TX_SOPQ15_ERROR_SHIFT                                                            15
+  #define NIG_REG_INT_STS_1_LB_SOPQ0_ERROR                                                                   (0x1<<16) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_1_LB_SOPQ0_ERROR_SHIFT                                                             16
+  #define NIG_REG_INT_STS_1_LB_SOPQ1_ERROR                                                                   (0x1<<17) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_1_LB_SOPQ1_ERROR_SHIFT                                                             17
+  #define NIG_REG_INT_STS_1_LB_SOPQ2_ERROR                                                                   (0x1<<18) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_1_LB_SOPQ2_ERROR_SHIFT                                                             18
+  #define NIG_REG_INT_STS_1_LB_SOPQ3_ERROR                                                                   (0x1<<19) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_1_LB_SOPQ3_ERROR_SHIFT                                                             19
+  #define NIG_REG_INT_STS_1_LB_SOPQ4_ERROR                                                                   (0x1<<20) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_1_LB_SOPQ4_ERROR_SHIFT                                                             20
+  #define NIG_REG_INT_STS_1_LB_SOPQ5_ERROR                                                                   (0x1<<21) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_1_LB_SOPQ5_ERROR_SHIFT                                                             21
+  #define NIG_REG_INT_STS_1_LB_SOPQ6_ERROR                                                                   (0x1<<22) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_1_LB_SOPQ6_ERROR_SHIFT                                                             22
+  #define NIG_REG_INT_STS_1_LB_SOPQ7_ERROR                                                                   (0x1<<23) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_1_LB_SOPQ7_ERROR_SHIFT                                                             23
+  #define NIG_REG_INT_STS_1_LB_SOPQ8_ERROR                                                                   (0x1<<24) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_1_LB_SOPQ8_ERROR_SHIFT                                                             24
+  #define NIG_REG_INT_STS_1_LB_SOPQ9_ERROR                                                                   (0x1<<25) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_1_LB_SOPQ9_ERROR_SHIFT                                                             25
+  #define NIG_REG_INT_STS_1_LB_SOPQ10_ERROR                                                                  (0x1<<26) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_1_LB_SOPQ10_ERROR_SHIFT                                                            26
+  #define NIG_REG_INT_STS_1_LB_SOPQ11_ERROR                                                                  (0x1<<27) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_1_LB_SOPQ11_ERROR_SHIFT                                                            27
+  #define NIG_REG_INT_STS_1_LB_SOPQ12_ERROR                                                                  (0x1<<28) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_1_LB_SOPQ12_ERROR_SHIFT                                                            28
+  #define NIG_REG_INT_STS_1_LB_SOPQ13_ERROR                                                                  (0x1<<29) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_1_LB_SOPQ13_ERROR_SHIFT                                                            29
+  #define NIG_REG_INT_STS_1_LB_SOPQ14_ERROR                                                                  (0x1<<30) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_1_LB_SOPQ14_ERROR_SHIFT                                                            30
+  #define NIG_REG_INT_STS_1_LB_SOPQ15_ERROR                                                                  (0x1<<31) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_1_LB_SOPQ15_ERROR_SHIFT                                                            31
+#define NIG_REG_INT_MASK_1                                                                                   0x500054UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define NIG_REG_INT_MASK_1_TX_SOPQ0_ERROR                                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ0_ERROR .
+  #define NIG_REG_INT_MASK_1_TX_SOPQ0_ERROR_SHIFT                                                            0
+  #define NIG_REG_INT_MASK_1_TX_SOPQ1_ERROR                                                                  (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ1_ERROR .
+  #define NIG_REG_INT_MASK_1_TX_SOPQ1_ERROR_SHIFT                                                            1
+  #define NIG_REG_INT_MASK_1_TX_SOPQ2_ERROR                                                                  (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ2_ERROR .
+  #define NIG_REG_INT_MASK_1_TX_SOPQ2_ERROR_SHIFT                                                            2
+  #define NIG_REG_INT_MASK_1_TX_SOPQ3_ERROR                                                                  (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ3_ERROR .
+  #define NIG_REG_INT_MASK_1_TX_SOPQ3_ERROR_SHIFT                                                            3
+  #define NIG_REG_INT_MASK_1_TX_SOPQ4_ERROR                                                                  (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ4_ERROR .
+  #define NIG_REG_INT_MASK_1_TX_SOPQ4_ERROR_SHIFT                                                            4
+  #define NIG_REG_INT_MASK_1_TX_SOPQ5_ERROR                                                                  (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ5_ERROR .
+  #define NIG_REG_INT_MASK_1_TX_SOPQ5_ERROR_SHIFT                                                            5
+  #define NIG_REG_INT_MASK_1_TX_SOPQ6_ERROR                                                                  (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ6_ERROR .
+  #define NIG_REG_INT_MASK_1_TX_SOPQ6_ERROR_SHIFT                                                            6
+  #define NIG_REG_INT_MASK_1_TX_SOPQ7_ERROR                                                                  (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ7_ERROR .
+  #define NIG_REG_INT_MASK_1_TX_SOPQ7_ERROR_SHIFT                                                            7
+  #define NIG_REG_INT_MASK_1_TX_SOPQ8_ERROR                                                                  (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ8_ERROR .
+  #define NIG_REG_INT_MASK_1_TX_SOPQ8_ERROR_SHIFT                                                            8
+  #define NIG_REG_INT_MASK_1_TX_SOPQ9_ERROR                                                                  (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ9_ERROR .
+  #define NIG_REG_INT_MASK_1_TX_SOPQ9_ERROR_SHIFT                                                            9
+  #define NIG_REG_INT_MASK_1_TX_SOPQ10_ERROR                                                                 (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ10_ERROR .
+  #define NIG_REG_INT_MASK_1_TX_SOPQ10_ERROR_SHIFT                                                           10
+  #define NIG_REG_INT_MASK_1_TX_SOPQ11_ERROR                                                                 (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ11_ERROR .
+  #define NIG_REG_INT_MASK_1_TX_SOPQ11_ERROR_SHIFT                                                           11
+  #define NIG_REG_INT_MASK_1_TX_SOPQ12_ERROR                                                                 (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ12_ERROR .
+  #define NIG_REG_INT_MASK_1_TX_SOPQ12_ERROR_SHIFT                                                           12
+  #define NIG_REG_INT_MASK_1_TX_SOPQ13_ERROR                                                                 (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ13_ERROR .
+  #define NIG_REG_INT_MASK_1_TX_SOPQ13_ERROR_SHIFT                                                           13
+  #define NIG_REG_INT_MASK_1_TX_SOPQ14_ERROR                                                                 (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ14_ERROR .
+  #define NIG_REG_INT_MASK_1_TX_SOPQ14_ERROR_SHIFT                                                           14
+  #define NIG_REG_INT_MASK_1_TX_SOPQ15_ERROR                                                                 (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ15_ERROR .
+  #define NIG_REG_INT_MASK_1_TX_SOPQ15_ERROR_SHIFT                                                           15
+  #define NIG_REG_INT_MASK_1_LB_SOPQ0_ERROR                                                                  (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ0_ERROR .
+  #define NIG_REG_INT_MASK_1_LB_SOPQ0_ERROR_SHIFT                                                            16
+  #define NIG_REG_INT_MASK_1_LB_SOPQ1_ERROR                                                                  (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ1_ERROR .
+  #define NIG_REG_INT_MASK_1_LB_SOPQ1_ERROR_SHIFT                                                            17
+  #define NIG_REG_INT_MASK_1_LB_SOPQ2_ERROR                                                                  (0x1<<18) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ2_ERROR .
+  #define NIG_REG_INT_MASK_1_LB_SOPQ2_ERROR_SHIFT                                                            18
+  #define NIG_REG_INT_MASK_1_LB_SOPQ3_ERROR                                                                  (0x1<<19) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ3_ERROR .
+  #define NIG_REG_INT_MASK_1_LB_SOPQ3_ERROR_SHIFT                                                            19
+  #define NIG_REG_INT_MASK_1_LB_SOPQ4_ERROR                                                                  (0x1<<20) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ4_ERROR .
+  #define NIG_REG_INT_MASK_1_LB_SOPQ4_ERROR_SHIFT                                                            20
+  #define NIG_REG_INT_MASK_1_LB_SOPQ5_ERROR                                                                  (0x1<<21) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ5_ERROR .
+  #define NIG_REG_INT_MASK_1_LB_SOPQ5_ERROR_SHIFT                                                            21
+  #define NIG_REG_INT_MASK_1_LB_SOPQ6_ERROR                                                                  (0x1<<22) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ6_ERROR .
+  #define NIG_REG_INT_MASK_1_LB_SOPQ6_ERROR_SHIFT                                                            22
+  #define NIG_REG_INT_MASK_1_LB_SOPQ7_ERROR                                                                  (0x1<<23) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ7_ERROR .
+  #define NIG_REG_INT_MASK_1_LB_SOPQ7_ERROR_SHIFT                                                            23
+  #define NIG_REG_INT_MASK_1_LB_SOPQ8_ERROR                                                                  (0x1<<24) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ8_ERROR .
+  #define NIG_REG_INT_MASK_1_LB_SOPQ8_ERROR_SHIFT                                                            24
+  #define NIG_REG_INT_MASK_1_LB_SOPQ9_ERROR                                                                  (0x1<<25) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ9_ERROR .
+  #define NIG_REG_INT_MASK_1_LB_SOPQ9_ERROR_SHIFT                                                            25
+  #define NIG_REG_INT_MASK_1_LB_SOPQ10_ERROR                                                                 (0x1<<26) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ10_ERROR .
+  #define NIG_REG_INT_MASK_1_LB_SOPQ10_ERROR_SHIFT                                                           26
+  #define NIG_REG_INT_MASK_1_LB_SOPQ11_ERROR                                                                 (0x1<<27) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ11_ERROR .
+  #define NIG_REG_INT_MASK_1_LB_SOPQ11_ERROR_SHIFT                                                           27
+  #define NIG_REG_INT_MASK_1_LB_SOPQ12_ERROR                                                                 (0x1<<28) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ12_ERROR .
+  #define NIG_REG_INT_MASK_1_LB_SOPQ12_ERROR_SHIFT                                                           28
+  #define NIG_REG_INT_MASK_1_LB_SOPQ13_ERROR                                                                 (0x1<<29) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ13_ERROR .
+  #define NIG_REG_INT_MASK_1_LB_SOPQ13_ERROR_SHIFT                                                           29
+  #define NIG_REG_INT_MASK_1_LB_SOPQ14_ERROR                                                                 (0x1<<30) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ14_ERROR .
+  #define NIG_REG_INT_MASK_1_LB_SOPQ14_ERROR_SHIFT                                                           30
+  #define NIG_REG_INT_MASK_1_LB_SOPQ15_ERROR                                                                 (0x1<<31) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ15_ERROR .
+  #define NIG_REG_INT_MASK_1_LB_SOPQ15_ERROR_SHIFT                                                           31
+#define NIG_REG_INT_STS_WR_1                                                                                 0x500058UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ0_ERROR                                                                (0x1<<0) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ0_ERROR_SHIFT                                                          0
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ1_ERROR                                                                (0x1<<1) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ1_ERROR_SHIFT                                                          1
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ2_ERROR                                                                (0x1<<2) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ2_ERROR_SHIFT                                                          2
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ3_ERROR                                                                (0x1<<3) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ3_ERROR_SHIFT                                                          3
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ4_ERROR                                                                (0x1<<4) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ4_ERROR_SHIFT                                                          4
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ5_ERROR                                                                (0x1<<5) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ5_ERROR_SHIFT                                                          5
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ6_ERROR                                                                (0x1<<6) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ6_ERROR_SHIFT                                                          6
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ7_ERROR                                                                (0x1<<7) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ7_ERROR_SHIFT                                                          7
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ8_ERROR                                                                (0x1<<8) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ8_ERROR_SHIFT                                                          8
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ9_ERROR                                                                (0x1<<9) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ9_ERROR_SHIFT                                                          9
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ10_ERROR                                                               (0x1<<10) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ10_ERROR_SHIFT                                                         10
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ11_ERROR                                                               (0x1<<11) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ11_ERROR_SHIFT                                                         11
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ12_ERROR                                                               (0x1<<12) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ12_ERROR_SHIFT                                                         12
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ13_ERROR                                                               (0x1<<13) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ13_ERROR_SHIFT                                                         13
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ14_ERROR                                                               (0x1<<14) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ14_ERROR_SHIFT                                                         14
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ15_ERROR                                                               (0x1<<15) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_WR_1_TX_SOPQ15_ERROR_SHIFT                                                         15
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ0_ERROR                                                                (0x1<<16) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ0_ERROR_SHIFT                                                          16
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ1_ERROR                                                                (0x1<<17) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ1_ERROR_SHIFT                                                          17
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ2_ERROR                                                                (0x1<<18) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ2_ERROR_SHIFT                                                          18
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ3_ERROR                                                                (0x1<<19) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ3_ERROR_SHIFT                                                          19
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ4_ERROR                                                                (0x1<<20) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ4_ERROR_SHIFT                                                          20
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ5_ERROR                                                                (0x1<<21) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ5_ERROR_SHIFT                                                          21
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ6_ERROR                                                                (0x1<<22) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ6_ERROR_SHIFT                                                          22
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ7_ERROR                                                                (0x1<<23) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ7_ERROR_SHIFT                                                          23
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ8_ERROR                                                                (0x1<<24) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ8_ERROR_SHIFT                                                          24
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ9_ERROR                                                                (0x1<<25) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ9_ERROR_SHIFT                                                          25
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ10_ERROR                                                               (0x1<<26) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ10_ERROR_SHIFT                                                         26
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ11_ERROR                                                               (0x1<<27) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ11_ERROR_SHIFT                                                         27
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ12_ERROR                                                               (0x1<<28) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ12_ERROR_SHIFT                                                         28
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ13_ERROR                                                               (0x1<<29) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ13_ERROR_SHIFT                                                         29
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ14_ERROR                                                               (0x1<<30) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ14_ERROR_SHIFT                                                         30
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ15_ERROR                                                               (0x1<<31) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_WR_1_LB_SOPQ15_ERROR_SHIFT                                                         31
+#define NIG_REG_INT_STS_CLR_1                                                                                0x50005cUL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ0_ERROR                                                               (0x1<<0) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ0_ERROR_SHIFT                                                         0
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ1_ERROR                                                               (0x1<<1) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ1_ERROR_SHIFT                                                         1
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ2_ERROR                                                               (0x1<<2) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ2_ERROR_SHIFT                                                         2
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ3_ERROR                                                               (0x1<<3) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ3_ERROR_SHIFT                                                         3
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ4_ERROR                                                               (0x1<<4) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ4_ERROR_SHIFT                                                         4
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ5_ERROR                                                               (0x1<<5) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ5_ERROR_SHIFT                                                         5
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ6_ERROR                                                               (0x1<<6) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ6_ERROR_SHIFT                                                         6
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ7_ERROR                                                               (0x1<<7) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ7_ERROR_SHIFT                                                         7
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ8_ERROR                                                               (0x1<<8) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ8_ERROR_SHIFT                                                         8
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ9_ERROR                                                               (0x1<<9) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ9_ERROR_SHIFT                                                         9
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ10_ERROR                                                              (0x1<<10) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ10_ERROR_SHIFT                                                        10
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ11_ERROR                                                              (0x1<<11) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ11_ERROR_SHIFT                                                        11
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ12_ERROR                                                              (0x1<<12) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ12_ERROR_SHIFT                                                        12
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ13_ERROR                                                              (0x1<<13) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ13_ERROR_SHIFT                                                        13
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ14_ERROR                                                              (0x1<<14) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ14_ERROR_SHIFT                                                        14
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ15_ERROR                                                              (0x1<<15) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_TX_SOPQ15_ERROR_SHIFT                                                        15
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ0_ERROR                                                               (0x1<<16) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ0_ERROR_SHIFT                                                         16
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ1_ERROR                                                               (0x1<<17) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ1_ERROR_SHIFT                                                         17
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ2_ERROR                                                               (0x1<<18) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ2_ERROR_SHIFT                                                         18
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ3_ERROR                                                               (0x1<<19) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ3_ERROR_SHIFT                                                         19
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ4_ERROR                                                               (0x1<<20) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ4_ERROR_SHIFT                                                         20
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ5_ERROR                                                               (0x1<<21) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ5_ERROR_SHIFT                                                         21
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ6_ERROR                                                               (0x1<<22) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ6_ERROR_SHIFT                                                         22
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ7_ERROR                                                               (0x1<<23) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ7_ERROR_SHIFT                                                         23
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ8_ERROR                                                               (0x1<<24) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ8_ERROR_SHIFT                                                         24
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ9_ERROR                                                               (0x1<<25) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ9_ERROR_SHIFT                                                         25
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ10_ERROR                                                              (0x1<<26) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ10_ERROR_SHIFT                                                        26
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ11_ERROR                                                              (0x1<<27) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ11_ERROR_SHIFT                                                        27
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ12_ERROR                                                              (0x1<<28) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ12_ERROR_SHIFT                                                        28
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ13_ERROR                                                              (0x1<<29) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ13_ERROR_SHIFT                                                        29
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ14_ERROR                                                              (0x1<<30) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ14_ERROR_SHIFT                                                        30
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ15_ERROR                                                              (0x1<<31) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_CLR_1_LB_SOPQ15_ERROR_SHIFT                                                        31
+#define NIG_REG_INT_STS_2                                                                                    0x500060UL //Access:R    DataWidth:0x16   // Multi Field Register.
+  #define NIG_REG_INT_STS_2_P0_PURELB_SOPQ_ERROR                                                             (0x1<<0) // Error in the pure-loopback SOPQ.
+  #define NIG_REG_INT_STS_2_P0_PURELB_SOPQ_ERROR_SHIFT                                                       0
+  #define NIG_REG_INT_STS_2_P0_RX_MACFIFO_ERROR                                                              (0x1<<1) // Error in RX MAC FIFO.
+  #define NIG_REG_INT_STS_2_P0_RX_MACFIFO_ERROR_SHIFT                                                        1
+  #define NIG_REG_INT_STS_2_P0_TX_MACFIFO_ERROR                                                              (0x1<<2) // Error in TX MAC FIFO.
+  #define NIG_REG_INT_STS_2_P0_TX_MACFIFO_ERROR_SHIFT                                                        2
+  #define NIG_REG_INT_STS_2_P0_TX_BMB_FIFO_ERROR                                                             (0x1<<3) // FIFO error in TX BMB FIFO.
+  #define NIG_REG_INT_STS_2_P0_TX_BMB_FIFO_ERROR_SHIFT                                                       3
+  #define NIG_REG_INT_STS_2_P0_LB_BMB_FIFO_ERROR                                                             (0x1<<4) // FIFO error in LB BMB FIFO.
+  #define NIG_REG_INT_STS_2_P0_LB_BMB_FIFO_ERROR_SHIFT                                                       4
+  #define NIG_REG_INT_STS_2_P0_TX_BTB_FIFO_ERROR                                                             (0x1<<5) // Error in BTB FIFO for TX path.
+  #define NIG_REG_INT_STS_2_P0_TX_BTB_FIFO_ERROR_SHIFT                                                       5
+  #define NIG_REG_INT_STS_2_P0_LB_BTB_FIFO_ERROR                                                             (0x1<<6) // Error in BTB FIFO for LB path.
+  #define NIG_REG_INT_STS_2_P0_LB_BTB_FIFO_ERROR_SHIFT                                                       6
+  #define NIG_REG_INT_STS_2_P0_RX_LLH_DFIFO_ERROR                                                            (0x1<<7) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_2_P0_RX_LLH_DFIFO_ERROR_SHIFT                                                      7
+  #define NIG_REG_INT_STS_2_P0_TX_LLH_DFIFO_ERROR                                                            (0x1<<8) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_2_P0_TX_LLH_DFIFO_ERROR_SHIFT                                                      8
+  #define NIG_REG_INT_STS_2_P0_LB_LLH_DFIFO_ERROR                                                            (0x1<<9) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_2_P0_LB_LLH_DFIFO_ERROR_SHIFT                                                      9
+  #define NIG_REG_INT_STS_2_P0_RX_LLH_HFIFO_ERROR                                                            (0x1<<10) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_2_P0_RX_LLH_HFIFO_ERROR_SHIFT                                                      10
+  #define NIG_REG_INT_STS_2_P0_TX_LLH_HFIFO_ERROR                                                            (0x1<<11) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_2_P0_TX_LLH_HFIFO_ERROR_SHIFT                                                      11
+  #define NIG_REG_INT_STS_2_P0_LB_LLH_HFIFO_ERROR                                                            (0x1<<12) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_2_P0_LB_LLH_HFIFO_ERROR_SHIFT                                                      12
+  #define NIG_REG_INT_STS_2_P0_RX_LLH_RFIFO_ERROR                                                            (0x1<<13) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_2_P0_RX_LLH_RFIFO_ERROR_SHIFT                                                      13
+  #define NIG_REG_INT_STS_2_P0_TX_LLH_RFIFO_ERROR                                                            (0x1<<14) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_2_P0_TX_LLH_RFIFO_ERROR_SHIFT                                                      14
+  #define NIG_REG_INT_STS_2_P0_LB_LLH_RFIFO_ERROR                                                            (0x1<<15) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_2_P0_LB_LLH_RFIFO_ERROR_SHIFT                                                      15
+  #define NIG_REG_INT_STS_2_P0_STORM_FIFO_ERROR                                                              (0x1<<16) // FIFO error in STORM message FIFO.
+  #define NIG_REG_INT_STS_2_P0_STORM_FIFO_ERROR_SHIFT                                                        16
+  #define NIG_REG_INT_STS_2_P0_STORM_DSCR_FIFO_ERROR                                                         (0x1<<17) // FIFO error in STORM descriptor FIFO.
+  #define NIG_REG_INT_STS_2_P0_STORM_DSCR_FIFO_ERROR_SHIFT                                                   17
+  #define NIG_REG_INT_STS_2_P0_TX_GNT_FIFO_ERROR                                                             (0x1<<18) // Error in grant FIFO.
+  #define NIG_REG_INT_STS_2_P0_TX_GNT_FIFO_ERROR_SHIFT                                                       18
+  #define NIG_REG_INT_STS_2_P0_LB_GNT_FIFO_ERROR                                                             (0x1<<19) // Error in grant FIFO.
+  #define NIG_REG_INT_STS_2_P0_LB_GNT_FIFO_ERROR_SHIFT                                                       19
+  #define NIG_REG_INT_STS_2_P0_TX_ORDER_FIFO_ERROR_E5                                                        (0x1<<20) // Error in LLH order FIFO.
+  #define NIG_REG_INT_STS_2_P0_TX_ORDER_FIFO_ERROR_E5_SHIFT                                                  20
+  #define NIG_REG_INT_STS_2_P0_LB_ORDER_FIFO_ERROR_E5                                                        (0x1<<21) // Error in LLH order FIFO.
+  #define NIG_REG_INT_STS_2_P0_LB_ORDER_FIFO_ERROR_E5_SHIFT                                                  21
+#define NIG_REG_INT_MASK_2                                                                                   0x500064UL //Access:RW   DataWidth:0x16   // Multi Field Register.
+  #define NIG_REG_INT_MASK_2_P0_PURELB_SOPQ_ERROR                                                            (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_PURELB_SOPQ_ERROR .
+  #define NIG_REG_INT_MASK_2_P0_PURELB_SOPQ_ERROR_SHIFT                                                      0
+  #define NIG_REG_INT_MASK_2_P0_RX_MACFIFO_ERROR                                                             (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_RX_MACFIFO_ERROR .
+  #define NIG_REG_INT_MASK_2_P0_RX_MACFIFO_ERROR_SHIFT                                                       1
+  #define NIG_REG_INT_MASK_2_P0_TX_MACFIFO_ERROR                                                             (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_TX_MACFIFO_ERROR .
+  #define NIG_REG_INT_MASK_2_P0_TX_MACFIFO_ERROR_SHIFT                                                       2
+  #define NIG_REG_INT_MASK_2_P0_TX_BMB_FIFO_ERROR                                                            (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_TX_BMB_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_2_P0_TX_BMB_FIFO_ERROR_SHIFT                                                      3
+  #define NIG_REG_INT_MASK_2_P0_LB_BMB_FIFO_ERROR                                                            (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_LB_BMB_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_2_P0_LB_BMB_FIFO_ERROR_SHIFT                                                      4
+  #define NIG_REG_INT_MASK_2_P0_TX_BTB_FIFO_ERROR                                                            (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_TX_BTB_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_2_P0_TX_BTB_FIFO_ERROR_SHIFT                                                      5
+  #define NIG_REG_INT_MASK_2_P0_LB_BTB_FIFO_ERROR                                                            (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_LB_BTB_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_2_P0_LB_BTB_FIFO_ERROR_SHIFT                                                      6
+  #define NIG_REG_INT_MASK_2_P0_RX_LLH_DFIFO_ERROR                                                           (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_RX_LLH_DFIFO_ERROR .
+  #define NIG_REG_INT_MASK_2_P0_RX_LLH_DFIFO_ERROR_SHIFT                                                     7
+  #define NIG_REG_INT_MASK_2_P0_TX_LLH_DFIFO_ERROR                                                           (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_TX_LLH_DFIFO_ERROR .
+  #define NIG_REG_INT_MASK_2_P0_TX_LLH_DFIFO_ERROR_SHIFT                                                     8
+  #define NIG_REG_INT_MASK_2_P0_LB_LLH_DFIFO_ERROR                                                           (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_LB_LLH_DFIFO_ERROR .
+  #define NIG_REG_INT_MASK_2_P0_LB_LLH_DFIFO_ERROR_SHIFT                                                     9
+  #define NIG_REG_INT_MASK_2_P0_RX_LLH_HFIFO_ERROR                                                           (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_RX_LLH_HFIFO_ERROR .
+  #define NIG_REG_INT_MASK_2_P0_RX_LLH_HFIFO_ERROR_SHIFT                                                     10
+  #define NIG_REG_INT_MASK_2_P0_TX_LLH_HFIFO_ERROR                                                           (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_TX_LLH_HFIFO_ERROR .
+  #define NIG_REG_INT_MASK_2_P0_TX_LLH_HFIFO_ERROR_SHIFT                                                     11
+  #define NIG_REG_INT_MASK_2_P0_LB_LLH_HFIFO_ERROR                                                           (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_LB_LLH_HFIFO_ERROR .
+  #define NIG_REG_INT_MASK_2_P0_LB_LLH_HFIFO_ERROR_SHIFT                                                     12
+  #define NIG_REG_INT_MASK_2_P0_RX_LLH_RFIFO_ERROR                                                           (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_RX_LLH_RFIFO_ERROR .
+  #define NIG_REG_INT_MASK_2_P0_RX_LLH_RFIFO_ERROR_SHIFT                                                     13
+  #define NIG_REG_INT_MASK_2_P0_TX_LLH_RFIFO_ERROR                                                           (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_TX_LLH_RFIFO_ERROR .
+  #define NIG_REG_INT_MASK_2_P0_TX_LLH_RFIFO_ERROR_SHIFT                                                     14
+  #define NIG_REG_INT_MASK_2_P0_LB_LLH_RFIFO_ERROR                                                           (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_LB_LLH_RFIFO_ERROR .
+  #define NIG_REG_INT_MASK_2_P0_LB_LLH_RFIFO_ERROR_SHIFT                                                     15
+  #define NIG_REG_INT_MASK_2_P0_STORM_FIFO_ERROR                                                             (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_STORM_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_2_P0_STORM_FIFO_ERROR_SHIFT                                                       16
+  #define NIG_REG_INT_MASK_2_P0_STORM_DSCR_FIFO_ERROR                                                        (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_STORM_DSCR_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_2_P0_STORM_DSCR_FIFO_ERROR_SHIFT                                                  17
+  #define NIG_REG_INT_MASK_2_P0_TX_GNT_FIFO_ERROR                                                            (0x1<<18) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_TX_GNT_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_2_P0_TX_GNT_FIFO_ERROR_SHIFT                                                      18
+  #define NIG_REG_INT_MASK_2_P0_LB_GNT_FIFO_ERROR                                                            (0x1<<19) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_LB_GNT_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_2_P0_LB_GNT_FIFO_ERROR_SHIFT                                                      19
+  #define NIG_REG_INT_MASK_2_P0_TX_ORDER_FIFO_ERROR_E5                                                       (0x1<<20) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_TX_ORDER_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_2_P0_TX_ORDER_FIFO_ERROR_E5_SHIFT                                                 20
+  #define NIG_REG_INT_MASK_2_P0_LB_ORDER_FIFO_ERROR_E5                                                       (0x1<<21) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_LB_ORDER_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_2_P0_LB_ORDER_FIFO_ERROR_E5_SHIFT                                                 21
+#define NIG_REG_INT_STS_WR_2                                                                                 0x500068UL //Access:WR   DataWidth:0x16   // Multi Field Register.
+  #define NIG_REG_INT_STS_WR_2_P0_PURELB_SOPQ_ERROR                                                          (0x1<<0) // Error in the pure-loopback SOPQ.
+  #define NIG_REG_INT_STS_WR_2_P0_PURELB_SOPQ_ERROR_SHIFT                                                    0
+  #define NIG_REG_INT_STS_WR_2_P0_RX_MACFIFO_ERROR                                                           (0x1<<1) // Error in RX MAC FIFO.
+  #define NIG_REG_INT_STS_WR_2_P0_RX_MACFIFO_ERROR_SHIFT                                                     1
+  #define NIG_REG_INT_STS_WR_2_P0_TX_MACFIFO_ERROR                                                           (0x1<<2) // Error in TX MAC FIFO.
+  #define NIG_REG_INT_STS_WR_2_P0_TX_MACFIFO_ERROR_SHIFT                                                     2
+  #define NIG_REG_INT_STS_WR_2_P0_TX_BMB_FIFO_ERROR                                                          (0x1<<3) // FIFO error in TX BMB FIFO.
+  #define NIG_REG_INT_STS_WR_2_P0_TX_BMB_FIFO_ERROR_SHIFT                                                    3
+  #define NIG_REG_INT_STS_WR_2_P0_LB_BMB_FIFO_ERROR                                                          (0x1<<4) // FIFO error in LB BMB FIFO.
+  #define NIG_REG_INT_STS_WR_2_P0_LB_BMB_FIFO_ERROR_SHIFT                                                    4
+  #define NIG_REG_INT_STS_WR_2_P0_TX_BTB_FIFO_ERROR                                                          (0x1<<5) // Error in BTB FIFO for TX path.
+  #define NIG_REG_INT_STS_WR_2_P0_TX_BTB_FIFO_ERROR_SHIFT                                                    5
+  #define NIG_REG_INT_STS_WR_2_P0_LB_BTB_FIFO_ERROR                                                          (0x1<<6) // Error in BTB FIFO for LB path.
+  #define NIG_REG_INT_STS_WR_2_P0_LB_BTB_FIFO_ERROR_SHIFT                                                    6
+  #define NIG_REG_INT_STS_WR_2_P0_RX_LLH_DFIFO_ERROR                                                         (0x1<<7) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_WR_2_P0_RX_LLH_DFIFO_ERROR_SHIFT                                                   7
+  #define NIG_REG_INT_STS_WR_2_P0_TX_LLH_DFIFO_ERROR                                                         (0x1<<8) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_WR_2_P0_TX_LLH_DFIFO_ERROR_SHIFT                                                   8
+  #define NIG_REG_INT_STS_WR_2_P0_LB_LLH_DFIFO_ERROR                                                         (0x1<<9) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_WR_2_P0_LB_LLH_DFIFO_ERROR_SHIFT                                                   9
+  #define NIG_REG_INT_STS_WR_2_P0_RX_LLH_HFIFO_ERROR                                                         (0x1<<10) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_WR_2_P0_RX_LLH_HFIFO_ERROR_SHIFT                                                   10
+  #define NIG_REG_INT_STS_WR_2_P0_TX_LLH_HFIFO_ERROR                                                         (0x1<<11) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_WR_2_P0_TX_LLH_HFIFO_ERROR_SHIFT                                                   11
+  #define NIG_REG_INT_STS_WR_2_P0_LB_LLH_HFIFO_ERROR                                                         (0x1<<12) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_WR_2_P0_LB_LLH_HFIFO_ERROR_SHIFT                                                   12
+  #define NIG_REG_INT_STS_WR_2_P0_RX_LLH_RFIFO_ERROR                                                         (0x1<<13) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_WR_2_P0_RX_LLH_RFIFO_ERROR_SHIFT                                                   13
+  #define NIG_REG_INT_STS_WR_2_P0_TX_LLH_RFIFO_ERROR                                                         (0x1<<14) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_WR_2_P0_TX_LLH_RFIFO_ERROR_SHIFT                                                   14
+  #define NIG_REG_INT_STS_WR_2_P0_LB_LLH_RFIFO_ERROR                                                         (0x1<<15) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_WR_2_P0_LB_LLH_RFIFO_ERROR_SHIFT                                                   15
+  #define NIG_REG_INT_STS_WR_2_P0_STORM_FIFO_ERROR                                                           (0x1<<16) // FIFO error in STORM message FIFO.
+  #define NIG_REG_INT_STS_WR_2_P0_STORM_FIFO_ERROR_SHIFT                                                     16
+  #define NIG_REG_INT_STS_WR_2_P0_STORM_DSCR_FIFO_ERROR                                                      (0x1<<17) // FIFO error in STORM descriptor FIFO.
+  #define NIG_REG_INT_STS_WR_2_P0_STORM_DSCR_FIFO_ERROR_SHIFT                                                17
+  #define NIG_REG_INT_STS_WR_2_P0_TX_GNT_FIFO_ERROR                                                          (0x1<<18) // Error in grant FIFO.
+  #define NIG_REG_INT_STS_WR_2_P0_TX_GNT_FIFO_ERROR_SHIFT                                                    18
+  #define NIG_REG_INT_STS_WR_2_P0_LB_GNT_FIFO_ERROR                                                          (0x1<<19) // Error in grant FIFO.
+  #define NIG_REG_INT_STS_WR_2_P0_LB_GNT_FIFO_ERROR_SHIFT                                                    19
+  #define NIG_REG_INT_STS_WR_2_P0_TX_ORDER_FIFO_ERROR_E5                                                     (0x1<<20) // Error in LLH order FIFO.
+  #define NIG_REG_INT_STS_WR_2_P0_TX_ORDER_FIFO_ERROR_E5_SHIFT                                               20
+  #define NIG_REG_INT_STS_WR_2_P0_LB_ORDER_FIFO_ERROR_E5                                                     (0x1<<21) // Error in LLH order FIFO.
+  #define NIG_REG_INT_STS_WR_2_P0_LB_ORDER_FIFO_ERROR_E5_SHIFT                                               21
+#define NIG_REG_INT_STS_CLR_2                                                                                0x50006cUL //Access:RC   DataWidth:0x16   // Multi Field Register.
+  #define NIG_REG_INT_STS_CLR_2_P0_PURELB_SOPQ_ERROR                                                         (0x1<<0) // Error in the pure-loopback SOPQ.
+  #define NIG_REG_INT_STS_CLR_2_P0_PURELB_SOPQ_ERROR_SHIFT                                                   0
+  #define NIG_REG_INT_STS_CLR_2_P0_RX_MACFIFO_ERROR                                                          (0x1<<1) // Error in RX MAC FIFO.
+  #define NIG_REG_INT_STS_CLR_2_P0_RX_MACFIFO_ERROR_SHIFT                                                    1
+  #define NIG_REG_INT_STS_CLR_2_P0_TX_MACFIFO_ERROR                                                          (0x1<<2) // Error in TX MAC FIFO.
+  #define NIG_REG_INT_STS_CLR_2_P0_TX_MACFIFO_ERROR_SHIFT                                                    2
+  #define NIG_REG_INT_STS_CLR_2_P0_TX_BMB_FIFO_ERROR                                                         (0x1<<3) // FIFO error in TX BMB FIFO.
+  #define NIG_REG_INT_STS_CLR_2_P0_TX_BMB_FIFO_ERROR_SHIFT                                                   3
+  #define NIG_REG_INT_STS_CLR_2_P0_LB_BMB_FIFO_ERROR                                                         (0x1<<4) // FIFO error in LB BMB FIFO.
+  #define NIG_REG_INT_STS_CLR_2_P0_LB_BMB_FIFO_ERROR_SHIFT                                                   4
+  #define NIG_REG_INT_STS_CLR_2_P0_TX_BTB_FIFO_ERROR                                                         (0x1<<5) // Error in BTB FIFO for TX path.
+  #define NIG_REG_INT_STS_CLR_2_P0_TX_BTB_FIFO_ERROR_SHIFT                                                   5
+  #define NIG_REG_INT_STS_CLR_2_P0_LB_BTB_FIFO_ERROR                                                         (0x1<<6) // Error in BTB FIFO for LB path.
+  #define NIG_REG_INT_STS_CLR_2_P0_LB_BTB_FIFO_ERROR_SHIFT                                                   6
+  #define NIG_REG_INT_STS_CLR_2_P0_RX_LLH_DFIFO_ERROR                                                        (0x1<<7) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_CLR_2_P0_RX_LLH_DFIFO_ERROR_SHIFT                                                  7
+  #define NIG_REG_INT_STS_CLR_2_P0_TX_LLH_DFIFO_ERROR                                                        (0x1<<8) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_CLR_2_P0_TX_LLH_DFIFO_ERROR_SHIFT                                                  8
+  #define NIG_REG_INT_STS_CLR_2_P0_LB_LLH_DFIFO_ERROR                                                        (0x1<<9) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_CLR_2_P0_LB_LLH_DFIFO_ERROR_SHIFT                                                  9
+  #define NIG_REG_INT_STS_CLR_2_P0_RX_LLH_HFIFO_ERROR                                                        (0x1<<10) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_CLR_2_P0_RX_LLH_HFIFO_ERROR_SHIFT                                                  10
+  #define NIG_REG_INT_STS_CLR_2_P0_TX_LLH_HFIFO_ERROR                                                        (0x1<<11) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_CLR_2_P0_TX_LLH_HFIFO_ERROR_SHIFT                                                  11
+  #define NIG_REG_INT_STS_CLR_2_P0_LB_LLH_HFIFO_ERROR                                                        (0x1<<12) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_CLR_2_P0_LB_LLH_HFIFO_ERROR_SHIFT                                                  12
+  #define NIG_REG_INT_STS_CLR_2_P0_RX_LLH_RFIFO_ERROR                                                        (0x1<<13) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_CLR_2_P0_RX_LLH_RFIFO_ERROR_SHIFT                                                  13
+  #define NIG_REG_INT_STS_CLR_2_P0_TX_LLH_RFIFO_ERROR                                                        (0x1<<14) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_CLR_2_P0_TX_LLH_RFIFO_ERROR_SHIFT                                                  14
+  #define NIG_REG_INT_STS_CLR_2_P0_LB_LLH_RFIFO_ERROR                                                        (0x1<<15) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_CLR_2_P0_LB_LLH_RFIFO_ERROR_SHIFT                                                  15
+  #define NIG_REG_INT_STS_CLR_2_P0_STORM_FIFO_ERROR                                                          (0x1<<16) // FIFO error in STORM message FIFO.
+  #define NIG_REG_INT_STS_CLR_2_P0_STORM_FIFO_ERROR_SHIFT                                                    16
+  #define NIG_REG_INT_STS_CLR_2_P0_STORM_DSCR_FIFO_ERROR                                                     (0x1<<17) // FIFO error in STORM descriptor FIFO.
+  #define NIG_REG_INT_STS_CLR_2_P0_STORM_DSCR_FIFO_ERROR_SHIFT                                               17
+  #define NIG_REG_INT_STS_CLR_2_P0_TX_GNT_FIFO_ERROR                                                         (0x1<<18) // Error in grant FIFO.
+  #define NIG_REG_INT_STS_CLR_2_P0_TX_GNT_FIFO_ERROR_SHIFT                                                   18
+  #define NIG_REG_INT_STS_CLR_2_P0_LB_GNT_FIFO_ERROR                                                         (0x1<<19) // Error in grant FIFO.
+  #define NIG_REG_INT_STS_CLR_2_P0_LB_GNT_FIFO_ERROR_SHIFT                                                   19
+  #define NIG_REG_INT_STS_CLR_2_P0_TX_ORDER_FIFO_ERROR_E5                                                    (0x1<<20) // Error in LLH order FIFO.
+  #define NIG_REG_INT_STS_CLR_2_P0_TX_ORDER_FIFO_ERROR_E5_SHIFT                                              20
+  #define NIG_REG_INT_STS_CLR_2_P0_LB_ORDER_FIFO_ERROR_E5                                                    (0x1<<21) // Error in LLH order FIFO.
+  #define NIG_REG_INT_STS_CLR_2_P0_LB_ORDER_FIFO_ERROR_E5_SHIFT                                              21
+#define NIG_REG_INT_STS_3                                                                                    0x500070UL //Access:R    DataWidth:0x12   // Multi Field Register.
+  #define NIG_REG_INT_STS_3_P0_TX_PAUSE_TOO_LONG_INT                                                         (0x1<<0) // Triggered by TX path being paused for the configured period of time.
+  #define NIG_REG_INT_STS_3_P0_TX_PAUSE_TOO_LONG_INT_SHIFT                                                   0
+  #define NIG_REG_INT_STS_3_P0_TC0_PAUSE_TOO_LONG_INT                                                        (0x1<<1) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_3_P0_TC0_PAUSE_TOO_LONG_INT_SHIFT                                                  1
+  #define NIG_REG_INT_STS_3_P0_TC1_PAUSE_TOO_LONG_INT                                                        (0x1<<2) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_3_P0_TC1_PAUSE_TOO_LONG_INT_SHIFT                                                  2
+  #define NIG_REG_INT_STS_3_P0_TC2_PAUSE_TOO_LONG_INT                                                        (0x1<<3) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_3_P0_TC2_PAUSE_TOO_LONG_INT_SHIFT                                                  3
+  #define NIG_REG_INT_STS_3_P0_TC3_PAUSE_TOO_LONG_INT                                                        (0x1<<4) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_3_P0_TC3_PAUSE_TOO_LONG_INT_SHIFT                                                  4
+  #define NIG_REG_INT_STS_3_P0_TC4_PAUSE_TOO_LONG_INT                                                        (0x1<<5) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_3_P0_TC4_PAUSE_TOO_LONG_INT_SHIFT                                                  5
+  #define NIG_REG_INT_STS_3_P0_TC5_PAUSE_TOO_LONG_INT                                                        (0x1<<6) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_3_P0_TC5_PAUSE_TOO_LONG_INT_SHIFT                                                  6
+  #define NIG_REG_INT_STS_3_P0_TC6_PAUSE_TOO_LONG_INT                                                        (0x1<<7) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_3_P0_TC6_PAUSE_TOO_LONG_INT_SHIFT                                                  7
+  #define NIG_REG_INT_STS_3_P0_TC7_PAUSE_TOO_LONG_INT                                                        (0x1<<8) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_3_P0_TC7_PAUSE_TOO_LONG_INT_SHIFT                                                  8
+  #define NIG_REG_INT_STS_3_P0_LB_TC0_PAUSE_TOO_LONG_INT                                                     (0x1<<9) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_3_P0_LB_TC0_PAUSE_TOO_LONG_INT_SHIFT                                               9
+  #define NIG_REG_INT_STS_3_P0_LB_TC1_PAUSE_TOO_LONG_INT                                                     (0x1<<10) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_3_P0_LB_TC1_PAUSE_TOO_LONG_INT_SHIFT                                               10
+  #define NIG_REG_INT_STS_3_P0_LB_TC2_PAUSE_TOO_LONG_INT                                                     (0x1<<11) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_3_P0_LB_TC2_PAUSE_TOO_LONG_INT_SHIFT                                               11
+  #define NIG_REG_INT_STS_3_P0_LB_TC3_PAUSE_TOO_LONG_INT                                                     (0x1<<12) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_3_P0_LB_TC3_PAUSE_TOO_LONG_INT_SHIFT                                               12
+  #define NIG_REG_INT_STS_3_P0_LB_TC4_PAUSE_TOO_LONG_INT                                                     (0x1<<13) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_3_P0_LB_TC4_PAUSE_TOO_LONG_INT_SHIFT                                               13
+  #define NIG_REG_INT_STS_3_P0_LB_TC5_PAUSE_TOO_LONG_INT                                                     (0x1<<14) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_3_P0_LB_TC5_PAUSE_TOO_LONG_INT_SHIFT                                               14
+  #define NIG_REG_INT_STS_3_P0_LB_TC6_PAUSE_TOO_LONG_INT                                                     (0x1<<15) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_3_P0_LB_TC6_PAUSE_TOO_LONG_INT_SHIFT                                               15
+  #define NIG_REG_INT_STS_3_P0_LB_TC7_PAUSE_TOO_LONG_INT                                                     (0x1<<16) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_3_P0_LB_TC7_PAUSE_TOO_LONG_INT_SHIFT                                               16
+  #define NIG_REG_INT_STS_3_P0_LB_TC8_PAUSE_TOO_LONG_INT                                                     (0x1<<17) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_3_P0_LB_TC8_PAUSE_TOO_LONG_INT_SHIFT                                               17
+#define NIG_REG_INT_MASK_3                                                                                   0x500074UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define NIG_REG_INT_MASK_3_P0_TX_PAUSE_TOO_LONG_INT                                                        (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TX_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_3_P0_TX_PAUSE_TOO_LONG_INT_SHIFT                                                  0
+  #define NIG_REG_INT_MASK_3_P0_TC0_PAUSE_TOO_LONG_INT                                                       (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TC0_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_3_P0_TC0_PAUSE_TOO_LONG_INT_SHIFT                                                 1
+  #define NIG_REG_INT_MASK_3_P0_TC1_PAUSE_TOO_LONG_INT                                                       (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TC1_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_3_P0_TC1_PAUSE_TOO_LONG_INT_SHIFT                                                 2
+  #define NIG_REG_INT_MASK_3_P0_TC2_PAUSE_TOO_LONG_INT                                                       (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TC2_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_3_P0_TC2_PAUSE_TOO_LONG_INT_SHIFT                                                 3
+  #define NIG_REG_INT_MASK_3_P0_TC3_PAUSE_TOO_LONG_INT                                                       (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TC3_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_3_P0_TC3_PAUSE_TOO_LONG_INT_SHIFT                                                 4
+  #define NIG_REG_INT_MASK_3_P0_TC4_PAUSE_TOO_LONG_INT                                                       (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TC4_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_3_P0_TC4_PAUSE_TOO_LONG_INT_SHIFT                                                 5
+  #define NIG_REG_INT_MASK_3_P0_TC5_PAUSE_TOO_LONG_INT                                                       (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TC5_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_3_P0_TC5_PAUSE_TOO_LONG_INT_SHIFT                                                 6
+  #define NIG_REG_INT_MASK_3_P0_TC6_PAUSE_TOO_LONG_INT                                                       (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TC6_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_3_P0_TC6_PAUSE_TOO_LONG_INT_SHIFT                                                 7
+  #define NIG_REG_INT_MASK_3_P0_TC7_PAUSE_TOO_LONG_INT                                                       (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TC7_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_3_P0_TC7_PAUSE_TOO_LONG_INT_SHIFT                                                 8
+  #define NIG_REG_INT_MASK_3_P0_LB_TC0_PAUSE_TOO_LONG_INT                                                    (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC0_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_3_P0_LB_TC0_PAUSE_TOO_LONG_INT_SHIFT                                              9
+  #define NIG_REG_INT_MASK_3_P0_LB_TC1_PAUSE_TOO_LONG_INT                                                    (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC1_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_3_P0_LB_TC1_PAUSE_TOO_LONG_INT_SHIFT                                              10
+  #define NIG_REG_INT_MASK_3_P0_LB_TC2_PAUSE_TOO_LONG_INT                                                    (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC2_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_3_P0_LB_TC2_PAUSE_TOO_LONG_INT_SHIFT                                              11
+  #define NIG_REG_INT_MASK_3_P0_LB_TC3_PAUSE_TOO_LONG_INT                                                    (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC3_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_3_P0_LB_TC3_PAUSE_TOO_LONG_INT_SHIFT                                              12
+  #define NIG_REG_INT_MASK_3_P0_LB_TC4_PAUSE_TOO_LONG_INT                                                    (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC4_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_3_P0_LB_TC4_PAUSE_TOO_LONG_INT_SHIFT                                              13
+  #define NIG_REG_INT_MASK_3_P0_LB_TC5_PAUSE_TOO_LONG_INT                                                    (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC5_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_3_P0_LB_TC5_PAUSE_TOO_LONG_INT_SHIFT                                              14
+  #define NIG_REG_INT_MASK_3_P0_LB_TC6_PAUSE_TOO_LONG_INT                                                    (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC6_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_3_P0_LB_TC6_PAUSE_TOO_LONG_INT_SHIFT                                              15
+  #define NIG_REG_INT_MASK_3_P0_LB_TC7_PAUSE_TOO_LONG_INT                                                    (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC7_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_3_P0_LB_TC7_PAUSE_TOO_LONG_INT_SHIFT                                              16
+  #define NIG_REG_INT_MASK_3_P0_LB_TC8_PAUSE_TOO_LONG_INT                                                    (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC8_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_3_P0_LB_TC8_PAUSE_TOO_LONG_INT_SHIFT                                              17
+#define NIG_REG_INT_STS_WR_3                                                                                 0x500078UL //Access:WR   DataWidth:0x12   // Multi Field Register.
+  #define NIG_REG_INT_STS_WR_3_P0_TX_PAUSE_TOO_LONG_INT                                                      (0x1<<0) // Triggered by TX path being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_3_P0_TX_PAUSE_TOO_LONG_INT_SHIFT                                                0
+  #define NIG_REG_INT_STS_WR_3_P0_TC0_PAUSE_TOO_LONG_INT                                                     (0x1<<1) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_3_P0_TC0_PAUSE_TOO_LONG_INT_SHIFT                                               1
+  #define NIG_REG_INT_STS_WR_3_P0_TC1_PAUSE_TOO_LONG_INT                                                     (0x1<<2) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_3_P0_TC1_PAUSE_TOO_LONG_INT_SHIFT                                               2
+  #define NIG_REG_INT_STS_WR_3_P0_TC2_PAUSE_TOO_LONG_INT                                                     (0x1<<3) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_3_P0_TC2_PAUSE_TOO_LONG_INT_SHIFT                                               3
+  #define NIG_REG_INT_STS_WR_3_P0_TC3_PAUSE_TOO_LONG_INT                                                     (0x1<<4) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_3_P0_TC3_PAUSE_TOO_LONG_INT_SHIFT                                               4
+  #define NIG_REG_INT_STS_WR_3_P0_TC4_PAUSE_TOO_LONG_INT                                                     (0x1<<5) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_3_P0_TC4_PAUSE_TOO_LONG_INT_SHIFT                                               5
+  #define NIG_REG_INT_STS_WR_3_P0_TC5_PAUSE_TOO_LONG_INT                                                     (0x1<<6) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_3_P0_TC5_PAUSE_TOO_LONG_INT_SHIFT                                               6
+  #define NIG_REG_INT_STS_WR_3_P0_TC6_PAUSE_TOO_LONG_INT                                                     (0x1<<7) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_3_P0_TC6_PAUSE_TOO_LONG_INT_SHIFT                                               7
+  #define NIG_REG_INT_STS_WR_3_P0_TC7_PAUSE_TOO_LONG_INT                                                     (0x1<<8) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_3_P0_TC7_PAUSE_TOO_LONG_INT_SHIFT                                               8
+  #define NIG_REG_INT_STS_WR_3_P0_LB_TC0_PAUSE_TOO_LONG_INT                                                  (0x1<<9) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_3_P0_LB_TC0_PAUSE_TOO_LONG_INT_SHIFT                                            9
+  #define NIG_REG_INT_STS_WR_3_P0_LB_TC1_PAUSE_TOO_LONG_INT                                                  (0x1<<10) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_3_P0_LB_TC1_PAUSE_TOO_LONG_INT_SHIFT                                            10
+  #define NIG_REG_INT_STS_WR_3_P0_LB_TC2_PAUSE_TOO_LONG_INT                                                  (0x1<<11) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_3_P0_LB_TC2_PAUSE_TOO_LONG_INT_SHIFT                                            11
+  #define NIG_REG_INT_STS_WR_3_P0_LB_TC3_PAUSE_TOO_LONG_INT                                                  (0x1<<12) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_3_P0_LB_TC3_PAUSE_TOO_LONG_INT_SHIFT                                            12
+  #define NIG_REG_INT_STS_WR_3_P0_LB_TC4_PAUSE_TOO_LONG_INT                                                  (0x1<<13) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_3_P0_LB_TC4_PAUSE_TOO_LONG_INT_SHIFT                                            13
+  #define NIG_REG_INT_STS_WR_3_P0_LB_TC5_PAUSE_TOO_LONG_INT                                                  (0x1<<14) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_3_P0_LB_TC5_PAUSE_TOO_LONG_INT_SHIFT                                            14
+  #define NIG_REG_INT_STS_WR_3_P0_LB_TC6_PAUSE_TOO_LONG_INT                                                  (0x1<<15) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_3_P0_LB_TC6_PAUSE_TOO_LONG_INT_SHIFT                                            15
+  #define NIG_REG_INT_STS_WR_3_P0_LB_TC7_PAUSE_TOO_LONG_INT                                                  (0x1<<16) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_3_P0_LB_TC7_PAUSE_TOO_LONG_INT_SHIFT                                            16
+  #define NIG_REG_INT_STS_WR_3_P0_LB_TC8_PAUSE_TOO_LONG_INT                                                  (0x1<<17) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_3_P0_LB_TC8_PAUSE_TOO_LONG_INT_SHIFT                                            17
+#define NIG_REG_INT_STS_CLR_3                                                                                0x50007cUL //Access:RC   DataWidth:0x12   // Multi Field Register.
+  #define NIG_REG_INT_STS_CLR_3_P0_TX_PAUSE_TOO_LONG_INT                                                     (0x1<<0) // Triggered by TX path being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_3_P0_TX_PAUSE_TOO_LONG_INT_SHIFT                                               0
+  #define NIG_REG_INT_STS_CLR_3_P0_TC0_PAUSE_TOO_LONG_INT                                                    (0x1<<1) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_3_P0_TC0_PAUSE_TOO_LONG_INT_SHIFT                                              1
+  #define NIG_REG_INT_STS_CLR_3_P0_TC1_PAUSE_TOO_LONG_INT                                                    (0x1<<2) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_3_P0_TC1_PAUSE_TOO_LONG_INT_SHIFT                                              2
+  #define NIG_REG_INT_STS_CLR_3_P0_TC2_PAUSE_TOO_LONG_INT                                                    (0x1<<3) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_3_P0_TC2_PAUSE_TOO_LONG_INT_SHIFT                                              3
+  #define NIG_REG_INT_STS_CLR_3_P0_TC3_PAUSE_TOO_LONG_INT                                                    (0x1<<4) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_3_P0_TC3_PAUSE_TOO_LONG_INT_SHIFT                                              4
+  #define NIG_REG_INT_STS_CLR_3_P0_TC4_PAUSE_TOO_LONG_INT                                                    (0x1<<5) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_3_P0_TC4_PAUSE_TOO_LONG_INT_SHIFT                                              5
+  #define NIG_REG_INT_STS_CLR_3_P0_TC5_PAUSE_TOO_LONG_INT                                                    (0x1<<6) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_3_P0_TC5_PAUSE_TOO_LONG_INT_SHIFT                                              6
+  #define NIG_REG_INT_STS_CLR_3_P0_TC6_PAUSE_TOO_LONG_INT                                                    (0x1<<7) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_3_P0_TC6_PAUSE_TOO_LONG_INT_SHIFT                                              7
+  #define NIG_REG_INT_STS_CLR_3_P0_TC7_PAUSE_TOO_LONG_INT                                                    (0x1<<8) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_3_P0_TC7_PAUSE_TOO_LONG_INT_SHIFT                                              8
+  #define NIG_REG_INT_STS_CLR_3_P0_LB_TC0_PAUSE_TOO_LONG_INT                                                 (0x1<<9) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_3_P0_LB_TC0_PAUSE_TOO_LONG_INT_SHIFT                                           9
+  #define NIG_REG_INT_STS_CLR_3_P0_LB_TC1_PAUSE_TOO_LONG_INT                                                 (0x1<<10) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_3_P0_LB_TC1_PAUSE_TOO_LONG_INT_SHIFT                                           10
+  #define NIG_REG_INT_STS_CLR_3_P0_LB_TC2_PAUSE_TOO_LONG_INT                                                 (0x1<<11) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_3_P0_LB_TC2_PAUSE_TOO_LONG_INT_SHIFT                                           11
+  #define NIG_REG_INT_STS_CLR_3_P0_LB_TC3_PAUSE_TOO_LONG_INT                                                 (0x1<<12) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_3_P0_LB_TC3_PAUSE_TOO_LONG_INT_SHIFT                                           12
+  #define NIG_REG_INT_STS_CLR_3_P0_LB_TC4_PAUSE_TOO_LONG_INT                                                 (0x1<<13) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_3_P0_LB_TC4_PAUSE_TOO_LONG_INT_SHIFT                                           13
+  #define NIG_REG_INT_STS_CLR_3_P0_LB_TC5_PAUSE_TOO_LONG_INT                                                 (0x1<<14) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_3_P0_LB_TC5_PAUSE_TOO_LONG_INT_SHIFT                                           14
+  #define NIG_REG_INT_STS_CLR_3_P0_LB_TC6_PAUSE_TOO_LONG_INT                                                 (0x1<<15) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_3_P0_LB_TC6_PAUSE_TOO_LONG_INT_SHIFT                                           15
+  #define NIG_REG_INT_STS_CLR_3_P0_LB_TC7_PAUSE_TOO_LONG_INT                                                 (0x1<<16) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_3_P0_LB_TC7_PAUSE_TOO_LONG_INT_SHIFT                                           16
+  #define NIG_REG_INT_STS_CLR_3_P0_LB_TC8_PAUSE_TOO_LONG_INT                                                 (0x1<<17) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_3_P0_LB_TC8_PAUSE_TOO_LONG_INT_SHIFT                                           17
+#define NIG_REG_INT_STS_4                                                                                    0x500080UL //Access:R    DataWidth:0x16   // Multi Field Register.
+  #define NIG_REG_INT_STS_4_P1_PURELB_SOPQ_ERROR                                                             (0x1<<0) // Error in the pure-loopback SOPQ.
+  #define NIG_REG_INT_STS_4_P1_PURELB_SOPQ_ERROR_SHIFT                                                       0
+  #define NIG_REG_INT_STS_4_P1_RX_MACFIFO_ERROR                                                              (0x1<<1) // Error in RX MAC FIFO.
+  #define NIG_REG_INT_STS_4_P1_RX_MACFIFO_ERROR_SHIFT                                                        1
+  #define NIG_REG_INT_STS_4_P1_TX_MACFIFO_ERROR                                                              (0x1<<2) // Error in TX MAC FIFO.
+  #define NIG_REG_INT_STS_4_P1_TX_MACFIFO_ERROR_SHIFT                                                        2
+  #define NIG_REG_INT_STS_4_P1_TX_BMB_FIFO_ERROR                                                             (0x1<<3) // FIFO error in TX BMB FIFO.
+  #define NIG_REG_INT_STS_4_P1_TX_BMB_FIFO_ERROR_SHIFT                                                       3
+  #define NIG_REG_INT_STS_4_P1_LB_BMB_FIFO_ERROR                                                             (0x1<<4) // FIFO error in LB BMB FIFO.
+  #define NIG_REG_INT_STS_4_P1_LB_BMB_FIFO_ERROR_SHIFT                                                       4
+  #define NIG_REG_INT_STS_4_P1_TX_BTB_FIFO_ERROR                                                             (0x1<<5) // Error in BTB FIFO for TX path.
+  #define NIG_REG_INT_STS_4_P1_TX_BTB_FIFO_ERROR_SHIFT                                                       5
+  #define NIG_REG_INT_STS_4_P1_LB_BTB_FIFO_ERROR                                                             (0x1<<6) // Error in BTB FIFO for LB path.
+  #define NIG_REG_INT_STS_4_P1_LB_BTB_FIFO_ERROR_SHIFT                                                       6
+  #define NIG_REG_INT_STS_4_P1_RX_LLH_DFIFO_ERROR                                                            (0x1<<7) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_4_P1_RX_LLH_DFIFO_ERROR_SHIFT                                                      7
+  #define NIG_REG_INT_STS_4_P1_TX_LLH_DFIFO_ERROR                                                            (0x1<<8) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_4_P1_TX_LLH_DFIFO_ERROR_SHIFT                                                      8
+  #define NIG_REG_INT_STS_4_P1_LB_LLH_DFIFO_ERROR                                                            (0x1<<9) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_4_P1_LB_LLH_DFIFO_ERROR_SHIFT                                                      9
+  #define NIG_REG_INT_STS_4_P1_RX_LLH_HFIFO_ERROR                                                            (0x1<<10) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_4_P1_RX_LLH_HFIFO_ERROR_SHIFT                                                      10
+  #define NIG_REG_INT_STS_4_P1_TX_LLH_HFIFO_ERROR                                                            (0x1<<11) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_4_P1_TX_LLH_HFIFO_ERROR_SHIFT                                                      11
+  #define NIG_REG_INT_STS_4_P1_LB_LLH_HFIFO_ERROR                                                            (0x1<<12) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_4_P1_LB_LLH_HFIFO_ERROR_SHIFT                                                      12
+  #define NIG_REG_INT_STS_4_P1_RX_LLH_RFIFO_ERROR                                                            (0x1<<13) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_4_P1_RX_LLH_RFIFO_ERROR_SHIFT                                                      13
+  #define NIG_REG_INT_STS_4_P1_TX_LLH_RFIFO_ERROR                                                            (0x1<<14) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_4_P1_TX_LLH_RFIFO_ERROR_SHIFT                                                      14
+  #define NIG_REG_INT_STS_4_P1_LB_LLH_RFIFO_ERROR                                                            (0x1<<15) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_4_P1_LB_LLH_RFIFO_ERROR_SHIFT                                                      15
+  #define NIG_REG_INT_STS_4_P1_STORM_FIFO_ERROR                                                              (0x1<<16) // FIFO error in STORM message FIFO.
+  #define NIG_REG_INT_STS_4_P1_STORM_FIFO_ERROR_SHIFT                                                        16
+  #define NIG_REG_INT_STS_4_P1_STORM_DSCR_FIFO_ERROR                                                         (0x1<<17) // FIFO error in STORM descriptor FIFO.
+  #define NIG_REG_INT_STS_4_P1_STORM_DSCR_FIFO_ERROR_SHIFT                                                   17
+  #define NIG_REG_INT_STS_4_P1_TX_GNT_FIFO_ERROR                                                             (0x1<<18) // Error in grant FIFO.
+  #define NIG_REG_INT_STS_4_P1_TX_GNT_FIFO_ERROR_SHIFT                                                       18
+  #define NIG_REG_INT_STS_4_P1_LB_GNT_FIFO_ERROR                                                             (0x1<<19) // Error in grant FIFO.
+  #define NIG_REG_INT_STS_4_P1_LB_GNT_FIFO_ERROR_SHIFT                                                       19
+  #define NIG_REG_INT_STS_4_P1_TX_ORDER_FIFO_ERROR_E5                                                        (0x1<<20) // Error in LLH order FIFO.
+  #define NIG_REG_INT_STS_4_P1_TX_ORDER_FIFO_ERROR_E5_SHIFT                                                  20
+  #define NIG_REG_INT_STS_4_P1_LB_ORDER_FIFO_ERROR_E5                                                        (0x1<<21) // Error in LLH order FIFO.
+  #define NIG_REG_INT_STS_4_P1_LB_ORDER_FIFO_ERROR_E5_SHIFT                                                  21
+#define NIG_REG_INT_MASK_4                                                                                   0x500084UL //Access:RW   DataWidth:0x16   // Multi Field Register.
+  #define NIG_REG_INT_MASK_4_P1_PURELB_SOPQ_ERROR                                                            (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_PURELB_SOPQ_ERROR .
+  #define NIG_REG_INT_MASK_4_P1_PURELB_SOPQ_ERROR_SHIFT                                                      0
+  #define NIG_REG_INT_MASK_4_P1_RX_MACFIFO_ERROR                                                             (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_RX_MACFIFO_ERROR .
+  #define NIG_REG_INT_MASK_4_P1_RX_MACFIFO_ERROR_SHIFT                                                       1
+  #define NIG_REG_INT_MASK_4_P1_TX_MACFIFO_ERROR                                                             (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_TX_MACFIFO_ERROR .
+  #define NIG_REG_INT_MASK_4_P1_TX_MACFIFO_ERROR_SHIFT                                                       2
+  #define NIG_REG_INT_MASK_4_P1_TX_BMB_FIFO_ERROR                                                            (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_TX_BMB_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_4_P1_TX_BMB_FIFO_ERROR_SHIFT                                                      3
+  #define NIG_REG_INT_MASK_4_P1_LB_BMB_FIFO_ERROR                                                            (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_LB_BMB_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_4_P1_LB_BMB_FIFO_ERROR_SHIFT                                                      4
+  #define NIG_REG_INT_MASK_4_P1_TX_BTB_FIFO_ERROR                                                            (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_TX_BTB_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_4_P1_TX_BTB_FIFO_ERROR_SHIFT                                                      5
+  #define NIG_REG_INT_MASK_4_P1_LB_BTB_FIFO_ERROR                                                            (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_LB_BTB_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_4_P1_LB_BTB_FIFO_ERROR_SHIFT                                                      6
+  #define NIG_REG_INT_MASK_4_P1_RX_LLH_DFIFO_ERROR                                                           (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_RX_LLH_DFIFO_ERROR .
+  #define NIG_REG_INT_MASK_4_P1_RX_LLH_DFIFO_ERROR_SHIFT                                                     7
+  #define NIG_REG_INT_MASK_4_P1_TX_LLH_DFIFO_ERROR                                                           (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_TX_LLH_DFIFO_ERROR .
+  #define NIG_REG_INT_MASK_4_P1_TX_LLH_DFIFO_ERROR_SHIFT                                                     8
+  #define NIG_REG_INT_MASK_4_P1_LB_LLH_DFIFO_ERROR                                                           (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_LB_LLH_DFIFO_ERROR .
+  #define NIG_REG_INT_MASK_4_P1_LB_LLH_DFIFO_ERROR_SHIFT                                                     9
+  #define NIG_REG_INT_MASK_4_P1_RX_LLH_HFIFO_ERROR                                                           (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_RX_LLH_HFIFO_ERROR .
+  #define NIG_REG_INT_MASK_4_P1_RX_LLH_HFIFO_ERROR_SHIFT                                                     10
+  #define NIG_REG_INT_MASK_4_P1_TX_LLH_HFIFO_ERROR                                                           (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_TX_LLH_HFIFO_ERROR .
+  #define NIG_REG_INT_MASK_4_P1_TX_LLH_HFIFO_ERROR_SHIFT                                                     11
+  #define NIG_REG_INT_MASK_4_P1_LB_LLH_HFIFO_ERROR                                                           (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_LB_LLH_HFIFO_ERROR .
+  #define NIG_REG_INT_MASK_4_P1_LB_LLH_HFIFO_ERROR_SHIFT                                                     12
+  #define NIG_REG_INT_MASK_4_P1_RX_LLH_RFIFO_ERROR                                                           (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_RX_LLH_RFIFO_ERROR .
+  #define NIG_REG_INT_MASK_4_P1_RX_LLH_RFIFO_ERROR_SHIFT                                                     13
+  #define NIG_REG_INT_MASK_4_P1_TX_LLH_RFIFO_ERROR                                                           (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_TX_LLH_RFIFO_ERROR .
+  #define NIG_REG_INT_MASK_4_P1_TX_LLH_RFIFO_ERROR_SHIFT                                                     14
+  #define NIG_REG_INT_MASK_4_P1_LB_LLH_RFIFO_ERROR                                                           (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_LB_LLH_RFIFO_ERROR .
+  #define NIG_REG_INT_MASK_4_P1_LB_LLH_RFIFO_ERROR_SHIFT                                                     15
+  #define NIG_REG_INT_MASK_4_P1_STORM_FIFO_ERROR                                                             (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_STORM_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_4_P1_STORM_FIFO_ERROR_SHIFT                                                       16
+  #define NIG_REG_INT_MASK_4_P1_STORM_DSCR_FIFO_ERROR                                                        (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_STORM_DSCR_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_4_P1_STORM_DSCR_FIFO_ERROR_SHIFT                                                  17
+  #define NIG_REG_INT_MASK_4_P1_TX_GNT_FIFO_ERROR                                                            (0x1<<18) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_TX_GNT_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_4_P1_TX_GNT_FIFO_ERROR_SHIFT                                                      18
+  #define NIG_REG_INT_MASK_4_P1_LB_GNT_FIFO_ERROR                                                            (0x1<<19) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_LB_GNT_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_4_P1_LB_GNT_FIFO_ERROR_SHIFT                                                      19
+  #define NIG_REG_INT_MASK_4_P1_TX_ORDER_FIFO_ERROR_E5                                                       (0x1<<20) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_TX_ORDER_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_4_P1_TX_ORDER_FIFO_ERROR_E5_SHIFT                                                 20
+  #define NIG_REG_INT_MASK_4_P1_LB_ORDER_FIFO_ERROR_E5                                                       (0x1<<21) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_LB_ORDER_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_4_P1_LB_ORDER_FIFO_ERROR_E5_SHIFT                                                 21
+#define NIG_REG_INT_STS_WR_4                                                                                 0x500088UL //Access:WR   DataWidth:0x16   // Multi Field Register.
+  #define NIG_REG_INT_STS_WR_4_P1_PURELB_SOPQ_ERROR                                                          (0x1<<0) // Error in the pure-loopback SOPQ.
+  #define NIG_REG_INT_STS_WR_4_P1_PURELB_SOPQ_ERROR_SHIFT                                                    0
+  #define NIG_REG_INT_STS_WR_4_P1_RX_MACFIFO_ERROR                                                           (0x1<<1) // Error in RX MAC FIFO.
+  #define NIG_REG_INT_STS_WR_4_P1_RX_MACFIFO_ERROR_SHIFT                                                     1
+  #define NIG_REG_INT_STS_WR_4_P1_TX_MACFIFO_ERROR                                                           (0x1<<2) // Error in TX MAC FIFO.
+  #define NIG_REG_INT_STS_WR_4_P1_TX_MACFIFO_ERROR_SHIFT                                                     2
+  #define NIG_REG_INT_STS_WR_4_P1_TX_BMB_FIFO_ERROR                                                          (0x1<<3) // FIFO error in TX BMB FIFO.
+  #define NIG_REG_INT_STS_WR_4_P1_TX_BMB_FIFO_ERROR_SHIFT                                                    3
+  #define NIG_REG_INT_STS_WR_4_P1_LB_BMB_FIFO_ERROR                                                          (0x1<<4) // FIFO error in LB BMB FIFO.
+  #define NIG_REG_INT_STS_WR_4_P1_LB_BMB_FIFO_ERROR_SHIFT                                                    4
+  #define NIG_REG_INT_STS_WR_4_P1_TX_BTB_FIFO_ERROR                                                          (0x1<<5) // Error in BTB FIFO for TX path.
+  #define NIG_REG_INT_STS_WR_4_P1_TX_BTB_FIFO_ERROR_SHIFT                                                    5
+  #define NIG_REG_INT_STS_WR_4_P1_LB_BTB_FIFO_ERROR                                                          (0x1<<6) // Error in BTB FIFO for LB path.
+  #define NIG_REG_INT_STS_WR_4_P1_LB_BTB_FIFO_ERROR_SHIFT                                                    6
+  #define NIG_REG_INT_STS_WR_4_P1_RX_LLH_DFIFO_ERROR                                                         (0x1<<7) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_WR_4_P1_RX_LLH_DFIFO_ERROR_SHIFT                                                   7
+  #define NIG_REG_INT_STS_WR_4_P1_TX_LLH_DFIFO_ERROR                                                         (0x1<<8) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_WR_4_P1_TX_LLH_DFIFO_ERROR_SHIFT                                                   8
+  #define NIG_REG_INT_STS_WR_4_P1_LB_LLH_DFIFO_ERROR                                                         (0x1<<9) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_WR_4_P1_LB_LLH_DFIFO_ERROR_SHIFT                                                   9
+  #define NIG_REG_INT_STS_WR_4_P1_RX_LLH_HFIFO_ERROR                                                         (0x1<<10) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_WR_4_P1_RX_LLH_HFIFO_ERROR_SHIFT                                                   10
+  #define NIG_REG_INT_STS_WR_4_P1_TX_LLH_HFIFO_ERROR                                                         (0x1<<11) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_WR_4_P1_TX_LLH_HFIFO_ERROR_SHIFT                                                   11
+  #define NIG_REG_INT_STS_WR_4_P1_LB_LLH_HFIFO_ERROR                                                         (0x1<<12) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_WR_4_P1_LB_LLH_HFIFO_ERROR_SHIFT                                                   12
+  #define NIG_REG_INT_STS_WR_4_P1_RX_LLH_RFIFO_ERROR                                                         (0x1<<13) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_WR_4_P1_RX_LLH_RFIFO_ERROR_SHIFT                                                   13
+  #define NIG_REG_INT_STS_WR_4_P1_TX_LLH_RFIFO_ERROR                                                         (0x1<<14) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_WR_4_P1_TX_LLH_RFIFO_ERROR_SHIFT                                                   14
+  #define NIG_REG_INT_STS_WR_4_P1_LB_LLH_RFIFO_ERROR                                                         (0x1<<15) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_WR_4_P1_LB_LLH_RFIFO_ERROR_SHIFT                                                   15
+  #define NIG_REG_INT_STS_WR_4_P1_STORM_FIFO_ERROR                                                           (0x1<<16) // FIFO error in STORM message FIFO.
+  #define NIG_REG_INT_STS_WR_4_P1_STORM_FIFO_ERROR_SHIFT                                                     16
+  #define NIG_REG_INT_STS_WR_4_P1_STORM_DSCR_FIFO_ERROR                                                      (0x1<<17) // FIFO error in STORM descriptor FIFO.
+  #define NIG_REG_INT_STS_WR_4_P1_STORM_DSCR_FIFO_ERROR_SHIFT                                                17
+  #define NIG_REG_INT_STS_WR_4_P1_TX_GNT_FIFO_ERROR                                                          (0x1<<18) // Error in grant FIFO.
+  #define NIG_REG_INT_STS_WR_4_P1_TX_GNT_FIFO_ERROR_SHIFT                                                    18
+  #define NIG_REG_INT_STS_WR_4_P1_LB_GNT_FIFO_ERROR                                                          (0x1<<19) // Error in grant FIFO.
+  #define NIG_REG_INT_STS_WR_4_P1_LB_GNT_FIFO_ERROR_SHIFT                                                    19
+  #define NIG_REG_INT_STS_WR_4_P1_TX_ORDER_FIFO_ERROR_E5                                                     (0x1<<20) // Error in LLH order FIFO.
+  #define NIG_REG_INT_STS_WR_4_P1_TX_ORDER_FIFO_ERROR_E5_SHIFT                                               20
+  #define NIG_REG_INT_STS_WR_4_P1_LB_ORDER_FIFO_ERROR_E5                                                     (0x1<<21) // Error in LLH order FIFO.
+  #define NIG_REG_INT_STS_WR_4_P1_LB_ORDER_FIFO_ERROR_E5_SHIFT                                               21
+#define NIG_REG_INT_STS_CLR_4                                                                                0x50008cUL //Access:RC   DataWidth:0x16   // Multi Field Register.
+  #define NIG_REG_INT_STS_CLR_4_P1_PURELB_SOPQ_ERROR                                                         (0x1<<0) // Error in the pure-loopback SOPQ.
+  #define NIG_REG_INT_STS_CLR_4_P1_PURELB_SOPQ_ERROR_SHIFT                                                   0
+  #define NIG_REG_INT_STS_CLR_4_P1_RX_MACFIFO_ERROR                                                          (0x1<<1) // Error in RX MAC FIFO.
+  #define NIG_REG_INT_STS_CLR_4_P1_RX_MACFIFO_ERROR_SHIFT                                                    1
+  #define NIG_REG_INT_STS_CLR_4_P1_TX_MACFIFO_ERROR                                                          (0x1<<2) // Error in TX MAC FIFO.
+  #define NIG_REG_INT_STS_CLR_4_P1_TX_MACFIFO_ERROR_SHIFT                                                    2
+  #define NIG_REG_INT_STS_CLR_4_P1_TX_BMB_FIFO_ERROR                                                         (0x1<<3) // FIFO error in TX BMB FIFO.
+  #define NIG_REG_INT_STS_CLR_4_P1_TX_BMB_FIFO_ERROR_SHIFT                                                   3
+  #define NIG_REG_INT_STS_CLR_4_P1_LB_BMB_FIFO_ERROR                                                         (0x1<<4) // FIFO error in LB BMB FIFO.
+  #define NIG_REG_INT_STS_CLR_4_P1_LB_BMB_FIFO_ERROR_SHIFT                                                   4
+  #define NIG_REG_INT_STS_CLR_4_P1_TX_BTB_FIFO_ERROR                                                         (0x1<<5) // Error in BTB FIFO for TX path.
+  #define NIG_REG_INT_STS_CLR_4_P1_TX_BTB_FIFO_ERROR_SHIFT                                                   5
+  #define NIG_REG_INT_STS_CLR_4_P1_LB_BTB_FIFO_ERROR                                                         (0x1<<6) // Error in BTB FIFO for LB path.
+  #define NIG_REG_INT_STS_CLR_4_P1_LB_BTB_FIFO_ERROR_SHIFT                                                   6
+  #define NIG_REG_INT_STS_CLR_4_P1_RX_LLH_DFIFO_ERROR                                                        (0x1<<7) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_CLR_4_P1_RX_LLH_DFIFO_ERROR_SHIFT                                                  7
+  #define NIG_REG_INT_STS_CLR_4_P1_TX_LLH_DFIFO_ERROR                                                        (0x1<<8) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_CLR_4_P1_TX_LLH_DFIFO_ERROR_SHIFT                                                  8
+  #define NIG_REG_INT_STS_CLR_4_P1_LB_LLH_DFIFO_ERROR                                                        (0x1<<9) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_CLR_4_P1_LB_LLH_DFIFO_ERROR_SHIFT                                                  9
+  #define NIG_REG_INT_STS_CLR_4_P1_RX_LLH_HFIFO_ERROR                                                        (0x1<<10) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_CLR_4_P1_RX_LLH_HFIFO_ERROR_SHIFT                                                  10
+  #define NIG_REG_INT_STS_CLR_4_P1_TX_LLH_HFIFO_ERROR                                                        (0x1<<11) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_CLR_4_P1_TX_LLH_HFIFO_ERROR_SHIFT                                                  11
+  #define NIG_REG_INT_STS_CLR_4_P1_LB_LLH_HFIFO_ERROR                                                        (0x1<<12) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_CLR_4_P1_LB_LLH_HFIFO_ERROR_SHIFT                                                  12
+  #define NIG_REG_INT_STS_CLR_4_P1_RX_LLH_RFIFO_ERROR                                                        (0x1<<13) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_CLR_4_P1_RX_LLH_RFIFO_ERROR_SHIFT                                                  13
+  #define NIG_REG_INT_STS_CLR_4_P1_TX_LLH_RFIFO_ERROR                                                        (0x1<<14) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_CLR_4_P1_TX_LLH_RFIFO_ERROR_SHIFT                                                  14
+  #define NIG_REG_INT_STS_CLR_4_P1_LB_LLH_RFIFO_ERROR                                                        (0x1<<15) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_CLR_4_P1_LB_LLH_RFIFO_ERROR_SHIFT                                                  15
+  #define NIG_REG_INT_STS_CLR_4_P1_STORM_FIFO_ERROR                                                          (0x1<<16) // FIFO error in STORM message FIFO.
+  #define NIG_REG_INT_STS_CLR_4_P1_STORM_FIFO_ERROR_SHIFT                                                    16
+  #define NIG_REG_INT_STS_CLR_4_P1_STORM_DSCR_FIFO_ERROR                                                     (0x1<<17) // FIFO error in STORM descriptor FIFO.
+  #define NIG_REG_INT_STS_CLR_4_P1_STORM_DSCR_FIFO_ERROR_SHIFT                                               17
+  #define NIG_REG_INT_STS_CLR_4_P1_TX_GNT_FIFO_ERROR                                                         (0x1<<18) // Error in grant FIFO.
+  #define NIG_REG_INT_STS_CLR_4_P1_TX_GNT_FIFO_ERROR_SHIFT                                                   18
+  #define NIG_REG_INT_STS_CLR_4_P1_LB_GNT_FIFO_ERROR                                                         (0x1<<19) // Error in grant FIFO.
+  #define NIG_REG_INT_STS_CLR_4_P1_LB_GNT_FIFO_ERROR_SHIFT                                                   19
+  #define NIG_REG_INT_STS_CLR_4_P1_TX_ORDER_FIFO_ERROR_E5                                                    (0x1<<20) // Error in LLH order FIFO.
+  #define NIG_REG_INT_STS_CLR_4_P1_TX_ORDER_FIFO_ERROR_E5_SHIFT                                              20
+  #define NIG_REG_INT_STS_CLR_4_P1_LB_ORDER_FIFO_ERROR_E5                                                    (0x1<<21) // Error in LLH order FIFO.
+  #define NIG_REG_INT_STS_CLR_4_P1_LB_ORDER_FIFO_ERROR_E5_SHIFT                                              21
+#define NIG_REG_INT_STS_5                                                                                    0x500090UL //Access:R    DataWidth:0x12   // Multi Field Register.
+  #define NIG_REG_INT_STS_5_P1_TX_PAUSE_TOO_LONG_INT                                                         (0x1<<0) // Triggered by TX path being paused for the configured period of time.
+  #define NIG_REG_INT_STS_5_P1_TX_PAUSE_TOO_LONG_INT_SHIFT                                                   0
+  #define NIG_REG_INT_STS_5_P1_TC0_PAUSE_TOO_LONG_INT                                                        (0x1<<1) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_5_P1_TC0_PAUSE_TOO_LONG_INT_SHIFT                                                  1
+  #define NIG_REG_INT_STS_5_P1_TC1_PAUSE_TOO_LONG_INT                                                        (0x1<<2) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_5_P1_TC1_PAUSE_TOO_LONG_INT_SHIFT                                                  2
+  #define NIG_REG_INT_STS_5_P1_TC2_PAUSE_TOO_LONG_INT                                                        (0x1<<3) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_5_P1_TC2_PAUSE_TOO_LONG_INT_SHIFT                                                  3
+  #define NIG_REG_INT_STS_5_P1_TC3_PAUSE_TOO_LONG_INT                                                        (0x1<<4) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_5_P1_TC3_PAUSE_TOO_LONG_INT_SHIFT                                                  4
+  #define NIG_REG_INT_STS_5_P1_TC4_PAUSE_TOO_LONG_INT                                                        (0x1<<5) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_5_P1_TC4_PAUSE_TOO_LONG_INT_SHIFT                                                  5
+  #define NIG_REG_INT_STS_5_P1_TC5_PAUSE_TOO_LONG_INT                                                        (0x1<<6) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_5_P1_TC5_PAUSE_TOO_LONG_INT_SHIFT                                                  6
+  #define NIG_REG_INT_STS_5_P1_TC6_PAUSE_TOO_LONG_INT                                                        (0x1<<7) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_5_P1_TC6_PAUSE_TOO_LONG_INT_SHIFT                                                  7
+  #define NIG_REG_INT_STS_5_P1_TC7_PAUSE_TOO_LONG_INT                                                        (0x1<<8) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_5_P1_TC7_PAUSE_TOO_LONG_INT_SHIFT                                                  8
+  #define NIG_REG_INT_STS_5_P1_LB_TC0_PAUSE_TOO_LONG_INT                                                     (0x1<<9) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_5_P1_LB_TC0_PAUSE_TOO_LONG_INT_SHIFT                                               9
+  #define NIG_REG_INT_STS_5_P1_LB_TC1_PAUSE_TOO_LONG_INT                                                     (0x1<<10) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_5_P1_LB_TC1_PAUSE_TOO_LONG_INT_SHIFT                                               10
+  #define NIG_REG_INT_STS_5_P1_LB_TC2_PAUSE_TOO_LONG_INT                                                     (0x1<<11) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_5_P1_LB_TC2_PAUSE_TOO_LONG_INT_SHIFT                                               11
+  #define NIG_REG_INT_STS_5_P1_LB_TC3_PAUSE_TOO_LONG_INT                                                     (0x1<<12) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_5_P1_LB_TC3_PAUSE_TOO_LONG_INT_SHIFT                                               12
+  #define NIG_REG_INT_STS_5_P1_LB_TC4_PAUSE_TOO_LONG_INT                                                     (0x1<<13) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_5_P1_LB_TC4_PAUSE_TOO_LONG_INT_SHIFT                                               13
+  #define NIG_REG_INT_STS_5_P1_LB_TC5_PAUSE_TOO_LONG_INT                                                     (0x1<<14) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_5_P1_LB_TC5_PAUSE_TOO_LONG_INT_SHIFT                                               14
+  #define NIG_REG_INT_STS_5_P1_LB_TC6_PAUSE_TOO_LONG_INT                                                     (0x1<<15) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_5_P1_LB_TC6_PAUSE_TOO_LONG_INT_SHIFT                                               15
+  #define NIG_REG_INT_STS_5_P1_LB_TC7_PAUSE_TOO_LONG_INT                                                     (0x1<<16) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_5_P1_LB_TC7_PAUSE_TOO_LONG_INT_SHIFT                                               16
+  #define NIG_REG_INT_STS_5_P1_LB_TC8_PAUSE_TOO_LONG_INT                                                     (0x1<<17) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_5_P1_LB_TC8_PAUSE_TOO_LONG_INT_SHIFT                                               17
+#define NIG_REG_INT_MASK_5                                                                                   0x500094UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define NIG_REG_INT_MASK_5_P1_TX_PAUSE_TOO_LONG_INT                                                        (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TX_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_5_P1_TX_PAUSE_TOO_LONG_INT_SHIFT                                                  0
+  #define NIG_REG_INT_MASK_5_P1_TC0_PAUSE_TOO_LONG_INT                                                       (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TC0_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_5_P1_TC0_PAUSE_TOO_LONG_INT_SHIFT                                                 1
+  #define NIG_REG_INT_MASK_5_P1_TC1_PAUSE_TOO_LONG_INT                                                       (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TC1_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_5_P1_TC1_PAUSE_TOO_LONG_INT_SHIFT                                                 2
+  #define NIG_REG_INT_MASK_5_P1_TC2_PAUSE_TOO_LONG_INT                                                       (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TC2_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_5_P1_TC2_PAUSE_TOO_LONG_INT_SHIFT                                                 3
+  #define NIG_REG_INT_MASK_5_P1_TC3_PAUSE_TOO_LONG_INT                                                       (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TC3_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_5_P1_TC3_PAUSE_TOO_LONG_INT_SHIFT                                                 4
+  #define NIG_REG_INT_MASK_5_P1_TC4_PAUSE_TOO_LONG_INT                                                       (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TC4_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_5_P1_TC4_PAUSE_TOO_LONG_INT_SHIFT                                                 5
+  #define NIG_REG_INT_MASK_5_P1_TC5_PAUSE_TOO_LONG_INT                                                       (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TC5_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_5_P1_TC5_PAUSE_TOO_LONG_INT_SHIFT                                                 6
+  #define NIG_REG_INT_MASK_5_P1_TC6_PAUSE_TOO_LONG_INT                                                       (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TC6_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_5_P1_TC6_PAUSE_TOO_LONG_INT_SHIFT                                                 7
+  #define NIG_REG_INT_MASK_5_P1_TC7_PAUSE_TOO_LONG_INT                                                       (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TC7_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_5_P1_TC7_PAUSE_TOO_LONG_INT_SHIFT                                                 8
+  #define NIG_REG_INT_MASK_5_P1_LB_TC0_PAUSE_TOO_LONG_INT                                                    (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC0_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_5_P1_LB_TC0_PAUSE_TOO_LONG_INT_SHIFT                                              9
+  #define NIG_REG_INT_MASK_5_P1_LB_TC1_PAUSE_TOO_LONG_INT                                                    (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC1_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_5_P1_LB_TC1_PAUSE_TOO_LONG_INT_SHIFT                                              10
+  #define NIG_REG_INT_MASK_5_P1_LB_TC2_PAUSE_TOO_LONG_INT                                                    (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC2_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_5_P1_LB_TC2_PAUSE_TOO_LONG_INT_SHIFT                                              11
+  #define NIG_REG_INT_MASK_5_P1_LB_TC3_PAUSE_TOO_LONG_INT                                                    (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC3_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_5_P1_LB_TC3_PAUSE_TOO_LONG_INT_SHIFT                                              12
+  #define NIG_REG_INT_MASK_5_P1_LB_TC4_PAUSE_TOO_LONG_INT                                                    (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC4_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_5_P1_LB_TC4_PAUSE_TOO_LONG_INT_SHIFT                                              13
+  #define NIG_REG_INT_MASK_5_P1_LB_TC5_PAUSE_TOO_LONG_INT                                                    (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC5_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_5_P1_LB_TC5_PAUSE_TOO_LONG_INT_SHIFT                                              14
+  #define NIG_REG_INT_MASK_5_P1_LB_TC6_PAUSE_TOO_LONG_INT                                                    (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC6_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_5_P1_LB_TC6_PAUSE_TOO_LONG_INT_SHIFT                                              15
+  #define NIG_REG_INT_MASK_5_P1_LB_TC7_PAUSE_TOO_LONG_INT                                                    (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC7_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_5_P1_LB_TC7_PAUSE_TOO_LONG_INT_SHIFT                                              16
+  #define NIG_REG_INT_MASK_5_P1_LB_TC8_PAUSE_TOO_LONG_INT                                                    (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC8_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_5_P1_LB_TC8_PAUSE_TOO_LONG_INT_SHIFT                                              17
+#define NIG_REG_INT_STS_WR_5                                                                                 0x500098UL //Access:WR   DataWidth:0x12   // Multi Field Register.
+  #define NIG_REG_INT_STS_WR_5_P1_TX_PAUSE_TOO_LONG_INT                                                      (0x1<<0) // Triggered by TX path being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_5_P1_TX_PAUSE_TOO_LONG_INT_SHIFT                                                0
+  #define NIG_REG_INT_STS_WR_5_P1_TC0_PAUSE_TOO_LONG_INT                                                     (0x1<<1) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_5_P1_TC0_PAUSE_TOO_LONG_INT_SHIFT                                               1
+  #define NIG_REG_INT_STS_WR_5_P1_TC1_PAUSE_TOO_LONG_INT                                                     (0x1<<2) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_5_P1_TC1_PAUSE_TOO_LONG_INT_SHIFT                                               2
+  #define NIG_REG_INT_STS_WR_5_P1_TC2_PAUSE_TOO_LONG_INT                                                     (0x1<<3) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_5_P1_TC2_PAUSE_TOO_LONG_INT_SHIFT                                               3
+  #define NIG_REG_INT_STS_WR_5_P1_TC3_PAUSE_TOO_LONG_INT                                                     (0x1<<4) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_5_P1_TC3_PAUSE_TOO_LONG_INT_SHIFT                                               4
+  #define NIG_REG_INT_STS_WR_5_P1_TC4_PAUSE_TOO_LONG_INT                                                     (0x1<<5) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_5_P1_TC4_PAUSE_TOO_LONG_INT_SHIFT                                               5
+  #define NIG_REG_INT_STS_WR_5_P1_TC5_PAUSE_TOO_LONG_INT                                                     (0x1<<6) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_5_P1_TC5_PAUSE_TOO_LONG_INT_SHIFT                                               6
+  #define NIG_REG_INT_STS_WR_5_P1_TC6_PAUSE_TOO_LONG_INT                                                     (0x1<<7) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_5_P1_TC6_PAUSE_TOO_LONG_INT_SHIFT                                               7
+  #define NIG_REG_INT_STS_WR_5_P1_TC7_PAUSE_TOO_LONG_INT                                                     (0x1<<8) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_5_P1_TC7_PAUSE_TOO_LONG_INT_SHIFT                                               8
+  #define NIG_REG_INT_STS_WR_5_P1_LB_TC0_PAUSE_TOO_LONG_INT                                                  (0x1<<9) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_5_P1_LB_TC0_PAUSE_TOO_LONG_INT_SHIFT                                            9
+  #define NIG_REG_INT_STS_WR_5_P1_LB_TC1_PAUSE_TOO_LONG_INT                                                  (0x1<<10) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_5_P1_LB_TC1_PAUSE_TOO_LONG_INT_SHIFT                                            10
+  #define NIG_REG_INT_STS_WR_5_P1_LB_TC2_PAUSE_TOO_LONG_INT                                                  (0x1<<11) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_5_P1_LB_TC2_PAUSE_TOO_LONG_INT_SHIFT                                            11
+  #define NIG_REG_INT_STS_WR_5_P1_LB_TC3_PAUSE_TOO_LONG_INT                                                  (0x1<<12) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_5_P1_LB_TC3_PAUSE_TOO_LONG_INT_SHIFT                                            12
+  #define NIG_REG_INT_STS_WR_5_P1_LB_TC4_PAUSE_TOO_LONG_INT                                                  (0x1<<13) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_5_P1_LB_TC4_PAUSE_TOO_LONG_INT_SHIFT                                            13
+  #define NIG_REG_INT_STS_WR_5_P1_LB_TC5_PAUSE_TOO_LONG_INT                                                  (0x1<<14) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_5_P1_LB_TC5_PAUSE_TOO_LONG_INT_SHIFT                                            14
+  #define NIG_REG_INT_STS_WR_5_P1_LB_TC6_PAUSE_TOO_LONG_INT                                                  (0x1<<15) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_5_P1_LB_TC6_PAUSE_TOO_LONG_INT_SHIFT                                            15
+  #define NIG_REG_INT_STS_WR_5_P1_LB_TC7_PAUSE_TOO_LONG_INT                                                  (0x1<<16) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_5_P1_LB_TC7_PAUSE_TOO_LONG_INT_SHIFT                                            16
+  #define NIG_REG_INT_STS_WR_5_P1_LB_TC8_PAUSE_TOO_LONG_INT                                                  (0x1<<17) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_5_P1_LB_TC8_PAUSE_TOO_LONG_INT_SHIFT                                            17
+#define NIG_REG_INT_STS_CLR_5                                                                                0x50009cUL //Access:RC   DataWidth:0x12   // Multi Field Register.
+  #define NIG_REG_INT_STS_CLR_5_P1_TX_PAUSE_TOO_LONG_INT                                                     (0x1<<0) // Triggered by TX path being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_5_P1_TX_PAUSE_TOO_LONG_INT_SHIFT                                               0
+  #define NIG_REG_INT_STS_CLR_5_P1_TC0_PAUSE_TOO_LONG_INT                                                    (0x1<<1) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_5_P1_TC0_PAUSE_TOO_LONG_INT_SHIFT                                              1
+  #define NIG_REG_INT_STS_CLR_5_P1_TC1_PAUSE_TOO_LONG_INT                                                    (0x1<<2) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_5_P1_TC1_PAUSE_TOO_LONG_INT_SHIFT                                              2
+  #define NIG_REG_INT_STS_CLR_5_P1_TC2_PAUSE_TOO_LONG_INT                                                    (0x1<<3) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_5_P1_TC2_PAUSE_TOO_LONG_INT_SHIFT                                              3
+  #define NIG_REG_INT_STS_CLR_5_P1_TC3_PAUSE_TOO_LONG_INT                                                    (0x1<<4) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_5_P1_TC3_PAUSE_TOO_LONG_INT_SHIFT                                              4
+  #define NIG_REG_INT_STS_CLR_5_P1_TC4_PAUSE_TOO_LONG_INT                                                    (0x1<<5) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_5_P1_TC4_PAUSE_TOO_LONG_INT_SHIFT                                              5
+  #define NIG_REG_INT_STS_CLR_5_P1_TC5_PAUSE_TOO_LONG_INT                                                    (0x1<<6) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_5_P1_TC5_PAUSE_TOO_LONG_INT_SHIFT                                              6
+  #define NIG_REG_INT_STS_CLR_5_P1_TC6_PAUSE_TOO_LONG_INT                                                    (0x1<<7) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_5_P1_TC6_PAUSE_TOO_LONG_INT_SHIFT                                              7
+  #define NIG_REG_INT_STS_CLR_5_P1_TC7_PAUSE_TOO_LONG_INT                                                    (0x1<<8) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_5_P1_TC7_PAUSE_TOO_LONG_INT_SHIFT                                              8
+  #define NIG_REG_INT_STS_CLR_5_P1_LB_TC0_PAUSE_TOO_LONG_INT                                                 (0x1<<9) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_5_P1_LB_TC0_PAUSE_TOO_LONG_INT_SHIFT                                           9
+  #define NIG_REG_INT_STS_CLR_5_P1_LB_TC1_PAUSE_TOO_LONG_INT                                                 (0x1<<10) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_5_P1_LB_TC1_PAUSE_TOO_LONG_INT_SHIFT                                           10
+  #define NIG_REG_INT_STS_CLR_5_P1_LB_TC2_PAUSE_TOO_LONG_INT                                                 (0x1<<11) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_5_P1_LB_TC2_PAUSE_TOO_LONG_INT_SHIFT                                           11
+  #define NIG_REG_INT_STS_CLR_5_P1_LB_TC3_PAUSE_TOO_LONG_INT                                                 (0x1<<12) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_5_P1_LB_TC3_PAUSE_TOO_LONG_INT_SHIFT                                           12
+  #define NIG_REG_INT_STS_CLR_5_P1_LB_TC4_PAUSE_TOO_LONG_INT                                                 (0x1<<13) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_5_P1_LB_TC4_PAUSE_TOO_LONG_INT_SHIFT                                           13
+  #define NIG_REG_INT_STS_CLR_5_P1_LB_TC5_PAUSE_TOO_LONG_INT                                                 (0x1<<14) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_5_P1_LB_TC5_PAUSE_TOO_LONG_INT_SHIFT                                           14
+  #define NIG_REG_INT_STS_CLR_5_P1_LB_TC6_PAUSE_TOO_LONG_INT                                                 (0x1<<15) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_5_P1_LB_TC6_PAUSE_TOO_LONG_INT_SHIFT                                           15
+  #define NIG_REG_INT_STS_CLR_5_P1_LB_TC7_PAUSE_TOO_LONG_INT                                                 (0x1<<16) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_5_P1_LB_TC7_PAUSE_TOO_LONG_INT_SHIFT                                           16
+  #define NIG_REG_INT_STS_CLR_5_P1_LB_TC8_PAUSE_TOO_LONG_INT                                                 (0x1<<17) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_5_P1_LB_TC8_PAUSE_TOO_LONG_INT_SHIFT                                           17
+#define NIG_REG_INT_STS_6_K2_E5                                                                              0x5000a0UL //Access:R    DataWidth:0x16   // Multi Field Register.
+  #define NIG_REG_INT_STS_6_P2_PURELB_SOPQ_ERROR_K2_E5                                                       (0x1<<0) // Error in the pure-loopback SOPQ.
+  #define NIG_REG_INT_STS_6_P2_PURELB_SOPQ_ERROR_K2_E5_SHIFT                                                 0
+  #define NIG_REG_INT_STS_6_P2_RX_MACFIFO_ERROR_K2_E5                                                        (0x1<<1) // Error in RX MAC FIFO.
+  #define NIG_REG_INT_STS_6_P2_RX_MACFIFO_ERROR_K2_E5_SHIFT                                                  1
+  #define NIG_REG_INT_STS_6_P2_TX_MACFIFO_ERROR_K2_E5                                                        (0x1<<2) // Error in TX MAC FIFO.
+  #define NIG_REG_INT_STS_6_P2_TX_MACFIFO_ERROR_K2_E5_SHIFT                                                  2
+  #define NIG_REG_INT_STS_6_P2_TX_BMB_FIFO_ERROR_K2_E5                                                       (0x1<<3) // FIFO error in TX BMB FIFO.
+  #define NIG_REG_INT_STS_6_P2_TX_BMB_FIFO_ERROR_K2_E5_SHIFT                                                 3
+  #define NIG_REG_INT_STS_6_P2_LB_BMB_FIFO_ERROR_K2_E5                                                       (0x1<<4) // FIFO error in LB BMB FIFO.
+  #define NIG_REG_INT_STS_6_P2_LB_BMB_FIFO_ERROR_K2_E5_SHIFT                                                 4
+  #define NIG_REG_INT_STS_6_P2_TX_BTB_FIFO_ERROR_K2_E5                                                       (0x1<<5) // Error in BTB FIFO for TX path.
+  #define NIG_REG_INT_STS_6_P2_TX_BTB_FIFO_ERROR_K2_E5_SHIFT                                                 5
+  #define NIG_REG_INT_STS_6_P2_LB_BTB_FIFO_ERROR_K2_E5                                                       (0x1<<6) // Error in BTB FIFO for LB path.
+  #define NIG_REG_INT_STS_6_P2_LB_BTB_FIFO_ERROR_K2_E5_SHIFT                                                 6
+  #define NIG_REG_INT_STS_6_P2_RX_LLH_DFIFO_ERROR_K2_E5                                                      (0x1<<7) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_6_P2_RX_LLH_DFIFO_ERROR_K2_E5_SHIFT                                                7
+  #define NIG_REG_INT_STS_6_P2_TX_LLH_DFIFO_ERROR_K2_E5                                                      (0x1<<8) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_6_P2_TX_LLH_DFIFO_ERROR_K2_E5_SHIFT                                                8
+  #define NIG_REG_INT_STS_6_P2_LB_LLH_DFIFO_ERROR_K2_E5                                                      (0x1<<9) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_6_P2_LB_LLH_DFIFO_ERROR_K2_E5_SHIFT                                                9
+  #define NIG_REG_INT_STS_6_P2_RX_LLH_HFIFO_ERROR_K2_E5                                                      (0x1<<10) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_6_P2_RX_LLH_HFIFO_ERROR_K2_E5_SHIFT                                                10
+  #define NIG_REG_INT_STS_6_P2_TX_LLH_HFIFO_ERROR_K2_E5                                                      (0x1<<11) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_6_P2_TX_LLH_HFIFO_ERROR_K2_E5_SHIFT                                                11
+  #define NIG_REG_INT_STS_6_P2_LB_LLH_HFIFO_ERROR_K2_E5                                                      (0x1<<12) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_6_P2_LB_LLH_HFIFO_ERROR_K2_E5_SHIFT                                                12
+  #define NIG_REG_INT_STS_6_P2_RX_LLH_RFIFO_ERROR_K2_E5                                                      (0x1<<13) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_6_P2_RX_LLH_RFIFO_ERROR_K2_E5_SHIFT                                                13
+  #define NIG_REG_INT_STS_6_P2_TX_LLH_RFIFO_ERROR_K2_E5                                                      (0x1<<14) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_6_P2_TX_LLH_RFIFO_ERROR_K2_E5_SHIFT                                                14
+  #define NIG_REG_INT_STS_6_P2_LB_LLH_RFIFO_ERROR_K2_E5                                                      (0x1<<15) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_6_P2_LB_LLH_RFIFO_ERROR_K2_E5_SHIFT                                                15
+  #define NIG_REG_INT_STS_6_P2_STORM_FIFO_ERROR_K2_E5                                                        (0x1<<16) // FIFO error in STORM message FIFO.
+  #define NIG_REG_INT_STS_6_P2_STORM_FIFO_ERROR_K2_E5_SHIFT                                                  16
+  #define NIG_REG_INT_STS_6_P2_STORM_DSCR_FIFO_ERROR_K2_E5                                                   (0x1<<17) // FIFO error in STORM descriptor FIFO.
+  #define NIG_REG_INT_STS_6_P2_STORM_DSCR_FIFO_ERROR_K2_E5_SHIFT                                             17
+  #define NIG_REG_INT_STS_6_P2_TX_GNT_FIFO_ERROR_K2_E5                                                       (0x1<<18) // Error in grant FIFO.
+  #define NIG_REG_INT_STS_6_P2_TX_GNT_FIFO_ERROR_K2_E5_SHIFT                                                 18
+  #define NIG_REG_INT_STS_6_P2_LB_GNT_FIFO_ERROR_K2_E5                                                       (0x1<<19) // Error in grant FIFO.
+  #define NIG_REG_INT_STS_6_P2_LB_GNT_FIFO_ERROR_K2_E5_SHIFT                                                 19
+  #define NIG_REG_INT_STS_6_P2_TX_ORDER_FIFO_ERROR_E5                                                        (0x1<<20) // Error in LLH order FIFO.
+  #define NIG_REG_INT_STS_6_P2_TX_ORDER_FIFO_ERROR_E5_SHIFT                                                  20
+  #define NIG_REG_INT_STS_6_P2_LB_ORDER_FIFO_ERROR_E5                                                        (0x1<<21) // Error in LLH order FIFO.
+  #define NIG_REG_INT_STS_6_P2_LB_ORDER_FIFO_ERROR_E5_SHIFT                                                  21
+#define NIG_REG_INT_MASK_6_K2_E5                                                                             0x5000a4UL //Access:RW   DataWidth:0x16   // Multi Field Register.
+  #define NIG_REG_INT_MASK_6_P2_PURELB_SOPQ_ERROR_K2_E5                                                      (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_PURELB_SOPQ_ERROR .
+  #define NIG_REG_INT_MASK_6_P2_PURELB_SOPQ_ERROR_K2_E5_SHIFT                                                0
+  #define NIG_REG_INT_MASK_6_P2_RX_MACFIFO_ERROR_K2_E5                                                       (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_RX_MACFIFO_ERROR .
+  #define NIG_REG_INT_MASK_6_P2_RX_MACFIFO_ERROR_K2_E5_SHIFT                                                 1
+  #define NIG_REG_INT_MASK_6_P2_TX_MACFIFO_ERROR_K2_E5                                                       (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_TX_MACFIFO_ERROR .
+  #define NIG_REG_INT_MASK_6_P2_TX_MACFIFO_ERROR_K2_E5_SHIFT                                                 2
+  #define NIG_REG_INT_MASK_6_P2_TX_BMB_FIFO_ERROR_K2_E5                                                      (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_TX_BMB_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_6_P2_TX_BMB_FIFO_ERROR_K2_E5_SHIFT                                                3
+  #define NIG_REG_INT_MASK_6_P2_LB_BMB_FIFO_ERROR_K2_E5                                                      (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_LB_BMB_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_6_P2_LB_BMB_FIFO_ERROR_K2_E5_SHIFT                                                4
+  #define NIG_REG_INT_MASK_6_P2_TX_BTB_FIFO_ERROR_K2_E5                                                      (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_TX_BTB_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_6_P2_TX_BTB_FIFO_ERROR_K2_E5_SHIFT                                                5
+  #define NIG_REG_INT_MASK_6_P2_LB_BTB_FIFO_ERROR_K2_E5                                                      (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_LB_BTB_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_6_P2_LB_BTB_FIFO_ERROR_K2_E5_SHIFT                                                6
+  #define NIG_REG_INT_MASK_6_P2_RX_LLH_DFIFO_ERROR_K2_E5                                                     (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_RX_LLH_DFIFO_ERROR .
+  #define NIG_REG_INT_MASK_6_P2_RX_LLH_DFIFO_ERROR_K2_E5_SHIFT                                               7
+  #define NIG_REG_INT_MASK_6_P2_TX_LLH_DFIFO_ERROR_K2_E5                                                     (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_TX_LLH_DFIFO_ERROR .
+  #define NIG_REG_INT_MASK_6_P2_TX_LLH_DFIFO_ERROR_K2_E5_SHIFT                                               8
+  #define NIG_REG_INT_MASK_6_P2_LB_LLH_DFIFO_ERROR_K2_E5                                                     (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_LB_LLH_DFIFO_ERROR .
+  #define NIG_REG_INT_MASK_6_P2_LB_LLH_DFIFO_ERROR_K2_E5_SHIFT                                               9
+  #define NIG_REG_INT_MASK_6_P2_RX_LLH_HFIFO_ERROR_K2_E5                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_RX_LLH_HFIFO_ERROR .
+  #define NIG_REG_INT_MASK_6_P2_RX_LLH_HFIFO_ERROR_K2_E5_SHIFT                                               10
+  #define NIG_REG_INT_MASK_6_P2_TX_LLH_HFIFO_ERROR_K2_E5                                                     (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_TX_LLH_HFIFO_ERROR .
+  #define NIG_REG_INT_MASK_6_P2_TX_LLH_HFIFO_ERROR_K2_E5_SHIFT                                               11
+  #define NIG_REG_INT_MASK_6_P2_LB_LLH_HFIFO_ERROR_K2_E5                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_LB_LLH_HFIFO_ERROR .
+  #define NIG_REG_INT_MASK_6_P2_LB_LLH_HFIFO_ERROR_K2_E5_SHIFT                                               12
+  #define NIG_REG_INT_MASK_6_P2_RX_LLH_RFIFO_ERROR_K2_E5                                                     (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_RX_LLH_RFIFO_ERROR .
+  #define NIG_REG_INT_MASK_6_P2_RX_LLH_RFIFO_ERROR_K2_E5_SHIFT                                               13
+  #define NIG_REG_INT_MASK_6_P2_TX_LLH_RFIFO_ERROR_K2_E5                                                     (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_TX_LLH_RFIFO_ERROR .
+  #define NIG_REG_INT_MASK_6_P2_TX_LLH_RFIFO_ERROR_K2_E5_SHIFT                                               14
+  #define NIG_REG_INT_MASK_6_P2_LB_LLH_RFIFO_ERROR_K2_E5                                                     (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_LB_LLH_RFIFO_ERROR .
+  #define NIG_REG_INT_MASK_6_P2_LB_LLH_RFIFO_ERROR_K2_E5_SHIFT                                               15
+  #define NIG_REG_INT_MASK_6_P2_STORM_FIFO_ERROR_K2_E5                                                       (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_STORM_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_6_P2_STORM_FIFO_ERROR_K2_E5_SHIFT                                                 16
+  #define NIG_REG_INT_MASK_6_P2_STORM_DSCR_FIFO_ERROR_K2_E5                                                  (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_STORM_DSCR_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_6_P2_STORM_DSCR_FIFO_ERROR_K2_E5_SHIFT                                            17
+  #define NIG_REG_INT_MASK_6_P2_TX_GNT_FIFO_ERROR_K2_E5                                                      (0x1<<18) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_TX_GNT_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_6_P2_TX_GNT_FIFO_ERROR_K2_E5_SHIFT                                                18
+  #define NIG_REG_INT_MASK_6_P2_LB_GNT_FIFO_ERROR_K2_E5                                                      (0x1<<19) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_LB_GNT_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_6_P2_LB_GNT_FIFO_ERROR_K2_E5_SHIFT                                                19
+  #define NIG_REG_INT_MASK_6_P2_TX_ORDER_FIFO_ERROR_E5                                                       (0x1<<20) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_TX_ORDER_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_6_P2_TX_ORDER_FIFO_ERROR_E5_SHIFT                                                 20
+  #define NIG_REG_INT_MASK_6_P2_LB_ORDER_FIFO_ERROR_E5                                                       (0x1<<21) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_LB_ORDER_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_6_P2_LB_ORDER_FIFO_ERROR_E5_SHIFT                                                 21
+#define NIG_REG_INT_STS_WR_6_K2_E5                                                                           0x5000a8UL //Access:WR   DataWidth:0x16   // Multi Field Register.
+  #define NIG_REG_INT_STS_WR_6_P2_PURELB_SOPQ_ERROR_K2_E5                                                    (0x1<<0) // Error in the pure-loopback SOPQ.
+  #define NIG_REG_INT_STS_WR_6_P2_PURELB_SOPQ_ERROR_K2_E5_SHIFT                                              0
+  #define NIG_REG_INT_STS_WR_6_P2_RX_MACFIFO_ERROR_K2_E5                                                     (0x1<<1) // Error in RX MAC FIFO.
+  #define NIG_REG_INT_STS_WR_6_P2_RX_MACFIFO_ERROR_K2_E5_SHIFT                                               1
+  #define NIG_REG_INT_STS_WR_6_P2_TX_MACFIFO_ERROR_K2_E5                                                     (0x1<<2) // Error in TX MAC FIFO.
+  #define NIG_REG_INT_STS_WR_6_P2_TX_MACFIFO_ERROR_K2_E5_SHIFT                                               2
+  #define NIG_REG_INT_STS_WR_6_P2_TX_BMB_FIFO_ERROR_K2_E5                                                    (0x1<<3) // FIFO error in TX BMB FIFO.
+  #define NIG_REG_INT_STS_WR_6_P2_TX_BMB_FIFO_ERROR_K2_E5_SHIFT                                              3
+  #define NIG_REG_INT_STS_WR_6_P2_LB_BMB_FIFO_ERROR_K2_E5                                                    (0x1<<4) // FIFO error in LB BMB FIFO.
+  #define NIG_REG_INT_STS_WR_6_P2_LB_BMB_FIFO_ERROR_K2_E5_SHIFT                                              4
+  #define NIG_REG_INT_STS_WR_6_P2_TX_BTB_FIFO_ERROR_K2_E5                                                    (0x1<<5) // Error in BTB FIFO for TX path.
+  #define NIG_REG_INT_STS_WR_6_P2_TX_BTB_FIFO_ERROR_K2_E5_SHIFT                                              5
+  #define NIG_REG_INT_STS_WR_6_P2_LB_BTB_FIFO_ERROR_K2_E5                                                    (0x1<<6) // Error in BTB FIFO for LB path.
+  #define NIG_REG_INT_STS_WR_6_P2_LB_BTB_FIFO_ERROR_K2_E5_SHIFT                                              6
+  #define NIG_REG_INT_STS_WR_6_P2_RX_LLH_DFIFO_ERROR_K2_E5                                                   (0x1<<7) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_WR_6_P2_RX_LLH_DFIFO_ERROR_K2_E5_SHIFT                                             7
+  #define NIG_REG_INT_STS_WR_6_P2_TX_LLH_DFIFO_ERROR_K2_E5                                                   (0x1<<8) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_WR_6_P2_TX_LLH_DFIFO_ERROR_K2_E5_SHIFT                                             8
+  #define NIG_REG_INT_STS_WR_6_P2_LB_LLH_DFIFO_ERROR_K2_E5                                                   (0x1<<9) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_WR_6_P2_LB_LLH_DFIFO_ERROR_K2_E5_SHIFT                                             9
+  #define NIG_REG_INT_STS_WR_6_P2_RX_LLH_HFIFO_ERROR_K2_E5                                                   (0x1<<10) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_WR_6_P2_RX_LLH_HFIFO_ERROR_K2_E5_SHIFT                                             10
+  #define NIG_REG_INT_STS_WR_6_P2_TX_LLH_HFIFO_ERROR_K2_E5                                                   (0x1<<11) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_WR_6_P2_TX_LLH_HFIFO_ERROR_K2_E5_SHIFT                                             11
+  #define NIG_REG_INT_STS_WR_6_P2_LB_LLH_HFIFO_ERROR_K2_E5                                                   (0x1<<12) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_WR_6_P2_LB_LLH_HFIFO_ERROR_K2_E5_SHIFT                                             12
+  #define NIG_REG_INT_STS_WR_6_P2_RX_LLH_RFIFO_ERROR_K2_E5                                                   (0x1<<13) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_WR_6_P2_RX_LLH_RFIFO_ERROR_K2_E5_SHIFT                                             13
+  #define NIG_REG_INT_STS_WR_6_P2_TX_LLH_RFIFO_ERROR_K2_E5                                                   (0x1<<14) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_WR_6_P2_TX_LLH_RFIFO_ERROR_K2_E5_SHIFT                                             14
+  #define NIG_REG_INT_STS_WR_6_P2_LB_LLH_RFIFO_ERROR_K2_E5                                                   (0x1<<15) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_WR_6_P2_LB_LLH_RFIFO_ERROR_K2_E5_SHIFT                                             15
+  #define NIG_REG_INT_STS_WR_6_P2_STORM_FIFO_ERROR_K2_E5                                                     (0x1<<16) // FIFO error in STORM message FIFO.
+  #define NIG_REG_INT_STS_WR_6_P2_STORM_FIFO_ERROR_K2_E5_SHIFT                                               16
+  #define NIG_REG_INT_STS_WR_6_P2_STORM_DSCR_FIFO_ERROR_K2_E5                                                (0x1<<17) // FIFO error in STORM descriptor FIFO.
+  #define NIG_REG_INT_STS_WR_6_P2_STORM_DSCR_FIFO_ERROR_K2_E5_SHIFT                                          17
+  #define NIG_REG_INT_STS_WR_6_P2_TX_GNT_FIFO_ERROR_K2_E5                                                    (0x1<<18) // Error in grant FIFO.
+  #define NIG_REG_INT_STS_WR_6_P2_TX_GNT_FIFO_ERROR_K2_E5_SHIFT                                              18
+  #define NIG_REG_INT_STS_WR_6_P2_LB_GNT_FIFO_ERROR_K2_E5                                                    (0x1<<19) // Error in grant FIFO.
+  #define NIG_REG_INT_STS_WR_6_P2_LB_GNT_FIFO_ERROR_K2_E5_SHIFT                                              19
+  #define NIG_REG_INT_STS_WR_6_P2_TX_ORDER_FIFO_ERROR_E5                                                     (0x1<<20) // Error in LLH order FIFO.
+  #define NIG_REG_INT_STS_WR_6_P2_TX_ORDER_FIFO_ERROR_E5_SHIFT                                               20
+  #define NIG_REG_INT_STS_WR_6_P2_LB_ORDER_FIFO_ERROR_E5                                                     (0x1<<21) // Error in LLH order FIFO.
+  #define NIG_REG_INT_STS_WR_6_P2_LB_ORDER_FIFO_ERROR_E5_SHIFT                                               21
+#define NIG_REG_INT_STS_CLR_6_K2_E5                                                                          0x5000acUL //Access:RC   DataWidth:0x16   // Multi Field Register.
+  #define NIG_REG_INT_STS_CLR_6_P2_PURELB_SOPQ_ERROR_K2_E5                                                   (0x1<<0) // Error in the pure-loopback SOPQ.
+  #define NIG_REG_INT_STS_CLR_6_P2_PURELB_SOPQ_ERROR_K2_E5_SHIFT                                             0
+  #define NIG_REG_INT_STS_CLR_6_P2_RX_MACFIFO_ERROR_K2_E5                                                    (0x1<<1) // Error in RX MAC FIFO.
+  #define NIG_REG_INT_STS_CLR_6_P2_RX_MACFIFO_ERROR_K2_E5_SHIFT                                              1
+  #define NIG_REG_INT_STS_CLR_6_P2_TX_MACFIFO_ERROR_K2_E5                                                    (0x1<<2) // Error in TX MAC FIFO.
+  #define NIG_REG_INT_STS_CLR_6_P2_TX_MACFIFO_ERROR_K2_E5_SHIFT                                              2
+  #define NIG_REG_INT_STS_CLR_6_P2_TX_BMB_FIFO_ERROR_K2_E5                                                   (0x1<<3) // FIFO error in TX BMB FIFO.
+  #define NIG_REG_INT_STS_CLR_6_P2_TX_BMB_FIFO_ERROR_K2_E5_SHIFT                                             3
+  #define NIG_REG_INT_STS_CLR_6_P2_LB_BMB_FIFO_ERROR_K2_E5                                                   (0x1<<4) // FIFO error in LB BMB FIFO.
+  #define NIG_REG_INT_STS_CLR_6_P2_LB_BMB_FIFO_ERROR_K2_E5_SHIFT                                             4
+  #define NIG_REG_INT_STS_CLR_6_P2_TX_BTB_FIFO_ERROR_K2_E5                                                   (0x1<<5) // Error in BTB FIFO for TX path.
+  #define NIG_REG_INT_STS_CLR_6_P2_TX_BTB_FIFO_ERROR_K2_E5_SHIFT                                             5
+  #define NIG_REG_INT_STS_CLR_6_P2_LB_BTB_FIFO_ERROR_K2_E5                                                   (0x1<<6) // Error in BTB FIFO for LB path.
+  #define NIG_REG_INT_STS_CLR_6_P2_LB_BTB_FIFO_ERROR_K2_E5_SHIFT                                             6
+  #define NIG_REG_INT_STS_CLR_6_P2_RX_LLH_DFIFO_ERROR_K2_E5                                                  (0x1<<7) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_CLR_6_P2_RX_LLH_DFIFO_ERROR_K2_E5_SHIFT                                            7
+  #define NIG_REG_INT_STS_CLR_6_P2_TX_LLH_DFIFO_ERROR_K2_E5                                                  (0x1<<8) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_CLR_6_P2_TX_LLH_DFIFO_ERROR_K2_E5_SHIFT                                            8
+  #define NIG_REG_INT_STS_CLR_6_P2_LB_LLH_DFIFO_ERROR_K2_E5                                                  (0x1<<9) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_CLR_6_P2_LB_LLH_DFIFO_ERROR_K2_E5_SHIFT                                            9
+  #define NIG_REG_INT_STS_CLR_6_P2_RX_LLH_HFIFO_ERROR_K2_E5                                                  (0x1<<10) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_CLR_6_P2_RX_LLH_HFIFO_ERROR_K2_E5_SHIFT                                            10
+  #define NIG_REG_INT_STS_CLR_6_P2_TX_LLH_HFIFO_ERROR_K2_E5                                                  (0x1<<11) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_CLR_6_P2_TX_LLH_HFIFO_ERROR_K2_E5_SHIFT                                            11
+  #define NIG_REG_INT_STS_CLR_6_P2_LB_LLH_HFIFO_ERROR_K2_E5                                                  (0x1<<12) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_CLR_6_P2_LB_LLH_HFIFO_ERROR_K2_E5_SHIFT                                            12
+  #define NIG_REG_INT_STS_CLR_6_P2_RX_LLH_RFIFO_ERROR_K2_E5                                                  (0x1<<13) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_CLR_6_P2_RX_LLH_RFIFO_ERROR_K2_E5_SHIFT                                            13
+  #define NIG_REG_INT_STS_CLR_6_P2_TX_LLH_RFIFO_ERROR_K2_E5                                                  (0x1<<14) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_CLR_6_P2_TX_LLH_RFIFO_ERROR_K2_E5_SHIFT                                            14
+  #define NIG_REG_INT_STS_CLR_6_P2_LB_LLH_RFIFO_ERROR_K2_E5                                                  (0x1<<15) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_CLR_6_P2_LB_LLH_RFIFO_ERROR_K2_E5_SHIFT                                            15
+  #define NIG_REG_INT_STS_CLR_6_P2_STORM_FIFO_ERROR_K2_E5                                                    (0x1<<16) // FIFO error in STORM message FIFO.
+  #define NIG_REG_INT_STS_CLR_6_P2_STORM_FIFO_ERROR_K2_E5_SHIFT                                              16
+  #define NIG_REG_INT_STS_CLR_6_P2_STORM_DSCR_FIFO_ERROR_K2_E5                                               (0x1<<17) // FIFO error in STORM descriptor FIFO.
+  #define NIG_REG_INT_STS_CLR_6_P2_STORM_DSCR_FIFO_ERROR_K2_E5_SHIFT                                         17
+  #define NIG_REG_INT_STS_CLR_6_P2_TX_GNT_FIFO_ERROR_K2_E5                                                   (0x1<<18) // Error in grant FIFO.
+  #define NIG_REG_INT_STS_CLR_6_P2_TX_GNT_FIFO_ERROR_K2_E5_SHIFT                                             18
+  #define NIG_REG_INT_STS_CLR_6_P2_LB_GNT_FIFO_ERROR_K2_E5                                                   (0x1<<19) // Error in grant FIFO.
+  #define NIG_REG_INT_STS_CLR_6_P2_LB_GNT_FIFO_ERROR_K2_E5_SHIFT                                             19
+  #define NIG_REG_INT_STS_CLR_6_P2_TX_ORDER_FIFO_ERROR_E5                                                    (0x1<<20) // Error in LLH order FIFO.
+  #define NIG_REG_INT_STS_CLR_6_P2_TX_ORDER_FIFO_ERROR_E5_SHIFT                                              20
+  #define NIG_REG_INT_STS_CLR_6_P2_LB_ORDER_FIFO_ERROR_E5                                                    (0x1<<21) // Error in LLH order FIFO.
+  #define NIG_REG_INT_STS_CLR_6_P2_LB_ORDER_FIFO_ERROR_E5_SHIFT                                              21
+#define NIG_REG_INT_STS_7_K2_E5                                                                              0x5000b0UL //Access:R    DataWidth:0x12   // Multi Field Register.
+  #define NIG_REG_INT_STS_7_P2_TX_PAUSE_TOO_LONG_INT_K2_E5                                                   (0x1<<0) // Triggered by TX path being paused for the configured period of time.
+  #define NIG_REG_INT_STS_7_P2_TX_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                             0
+  #define NIG_REG_INT_STS_7_P2_TC0_PAUSE_TOO_LONG_INT_K2_E5                                                  (0x1<<1) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_7_P2_TC0_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                            1
+  #define NIG_REG_INT_STS_7_P2_TC1_PAUSE_TOO_LONG_INT_K2_E5                                                  (0x1<<2) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_7_P2_TC1_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                            2
+  #define NIG_REG_INT_STS_7_P2_TC2_PAUSE_TOO_LONG_INT_K2_E5                                                  (0x1<<3) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_7_P2_TC2_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                            3
+  #define NIG_REG_INT_STS_7_P2_TC3_PAUSE_TOO_LONG_INT_K2_E5                                                  (0x1<<4) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_7_P2_TC3_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                            4
+  #define NIG_REG_INT_STS_7_P2_TC4_PAUSE_TOO_LONG_INT_K2_E5                                                  (0x1<<5) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_7_P2_TC4_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                            5
+  #define NIG_REG_INT_STS_7_P2_TC5_PAUSE_TOO_LONG_INT_K2_E5                                                  (0x1<<6) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_7_P2_TC5_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                            6
+  #define NIG_REG_INT_STS_7_P2_TC6_PAUSE_TOO_LONG_INT_K2_E5                                                  (0x1<<7) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_7_P2_TC6_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                            7
+  #define NIG_REG_INT_STS_7_P2_TC7_PAUSE_TOO_LONG_INT_K2_E5                                                  (0x1<<8) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_7_P2_TC7_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                            8
+  #define NIG_REG_INT_STS_7_P2_LB_TC0_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<9) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_7_P2_LB_TC0_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         9
+  #define NIG_REG_INT_STS_7_P2_LB_TC1_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<10) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_7_P2_LB_TC1_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         10
+  #define NIG_REG_INT_STS_7_P2_LB_TC2_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<11) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_7_P2_LB_TC2_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         11
+  #define NIG_REG_INT_STS_7_P2_LB_TC3_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<12) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_7_P2_LB_TC3_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         12
+  #define NIG_REG_INT_STS_7_P2_LB_TC4_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<13) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_7_P2_LB_TC4_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         13
+  #define NIG_REG_INT_STS_7_P2_LB_TC5_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<14) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_7_P2_LB_TC5_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         14
+  #define NIG_REG_INT_STS_7_P2_LB_TC6_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<15) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_7_P2_LB_TC6_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         15
+  #define NIG_REG_INT_STS_7_P2_LB_TC7_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<16) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_7_P2_LB_TC7_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         16
+  #define NIG_REG_INT_STS_7_P2_LB_TC8_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<17) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_7_P2_LB_TC8_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         17
+#define NIG_REG_INT_MASK_7_K2_E5                                                                             0x5000b4UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define NIG_REG_INT_MASK_7_P2_TX_PAUSE_TOO_LONG_INT_K2_E5                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TX_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_7_P2_TX_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                            0
+  #define NIG_REG_INT_MASK_7_P2_TC0_PAUSE_TOO_LONG_INT_K2_E5                                                 (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TC0_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_7_P2_TC0_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                           1
+  #define NIG_REG_INT_MASK_7_P2_TC1_PAUSE_TOO_LONG_INT_K2_E5                                                 (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TC1_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_7_P2_TC1_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                           2
+  #define NIG_REG_INT_MASK_7_P2_TC2_PAUSE_TOO_LONG_INT_K2_E5                                                 (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TC2_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_7_P2_TC2_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                           3
+  #define NIG_REG_INT_MASK_7_P2_TC3_PAUSE_TOO_LONG_INT_K2_E5                                                 (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TC3_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_7_P2_TC3_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                           4
+  #define NIG_REG_INT_MASK_7_P2_TC4_PAUSE_TOO_LONG_INT_K2_E5                                                 (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TC4_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_7_P2_TC4_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                           5
+  #define NIG_REG_INT_MASK_7_P2_TC5_PAUSE_TOO_LONG_INT_K2_E5                                                 (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TC5_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_7_P2_TC5_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                           6
+  #define NIG_REG_INT_MASK_7_P2_TC6_PAUSE_TOO_LONG_INT_K2_E5                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TC6_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_7_P2_TC6_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                           7
+  #define NIG_REG_INT_MASK_7_P2_TC7_PAUSE_TOO_LONG_INT_K2_E5                                                 (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TC7_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_7_P2_TC7_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                           8
+  #define NIG_REG_INT_MASK_7_P2_LB_TC0_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC0_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_7_P2_LB_TC0_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        9
+  #define NIG_REG_INT_MASK_7_P2_LB_TC1_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC1_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_7_P2_LB_TC1_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        10
+  #define NIG_REG_INT_MASK_7_P2_LB_TC2_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC2_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_7_P2_LB_TC2_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        11
+  #define NIG_REG_INT_MASK_7_P2_LB_TC3_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC3_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_7_P2_LB_TC3_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        12
+  #define NIG_REG_INT_MASK_7_P2_LB_TC4_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC4_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_7_P2_LB_TC4_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        13
+  #define NIG_REG_INT_MASK_7_P2_LB_TC5_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC5_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_7_P2_LB_TC5_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        14
+  #define NIG_REG_INT_MASK_7_P2_LB_TC6_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC6_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_7_P2_LB_TC6_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        15
+  #define NIG_REG_INT_MASK_7_P2_LB_TC7_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC7_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_7_P2_LB_TC7_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        16
+  #define NIG_REG_INT_MASK_7_P2_LB_TC8_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC8_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_7_P2_LB_TC8_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        17
+#define NIG_REG_INT_STS_WR_7_K2_E5                                                                           0x5000b8UL //Access:WR   DataWidth:0x12   // Multi Field Register.
+  #define NIG_REG_INT_STS_WR_7_P2_TX_PAUSE_TOO_LONG_INT_K2_E5                                                (0x1<<0) // Triggered by TX path being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_7_P2_TX_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                          0
+  #define NIG_REG_INT_STS_WR_7_P2_TC0_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<1) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_7_P2_TC0_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         1
+  #define NIG_REG_INT_STS_WR_7_P2_TC1_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<2) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_7_P2_TC1_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         2
+  #define NIG_REG_INT_STS_WR_7_P2_TC2_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<3) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_7_P2_TC2_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         3
+  #define NIG_REG_INT_STS_WR_7_P2_TC3_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<4) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_7_P2_TC3_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         4
+  #define NIG_REG_INT_STS_WR_7_P2_TC4_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<5) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_7_P2_TC4_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         5
+  #define NIG_REG_INT_STS_WR_7_P2_TC5_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<6) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_7_P2_TC5_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         6
+  #define NIG_REG_INT_STS_WR_7_P2_TC6_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<7) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_7_P2_TC6_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         7
+  #define NIG_REG_INT_STS_WR_7_P2_TC7_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<8) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_7_P2_TC7_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         8
+  #define NIG_REG_INT_STS_WR_7_P2_LB_TC0_PAUSE_TOO_LONG_INT_K2_E5                                            (0x1<<9) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_7_P2_LB_TC0_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                      9
+  #define NIG_REG_INT_STS_WR_7_P2_LB_TC1_PAUSE_TOO_LONG_INT_K2_E5                                            (0x1<<10) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_7_P2_LB_TC1_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                      10
+  #define NIG_REG_INT_STS_WR_7_P2_LB_TC2_PAUSE_TOO_LONG_INT_K2_E5                                            (0x1<<11) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_7_P2_LB_TC2_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                      11
+  #define NIG_REG_INT_STS_WR_7_P2_LB_TC3_PAUSE_TOO_LONG_INT_K2_E5                                            (0x1<<12) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_7_P2_LB_TC3_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                      12
+  #define NIG_REG_INT_STS_WR_7_P2_LB_TC4_PAUSE_TOO_LONG_INT_K2_E5                                            (0x1<<13) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_7_P2_LB_TC4_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                      13
+  #define NIG_REG_INT_STS_WR_7_P2_LB_TC5_PAUSE_TOO_LONG_INT_K2_E5                                            (0x1<<14) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_7_P2_LB_TC5_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                      14
+  #define NIG_REG_INT_STS_WR_7_P2_LB_TC6_PAUSE_TOO_LONG_INT_K2_E5                                            (0x1<<15) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_7_P2_LB_TC6_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                      15
+  #define NIG_REG_INT_STS_WR_7_P2_LB_TC7_PAUSE_TOO_LONG_INT_K2_E5                                            (0x1<<16) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_7_P2_LB_TC7_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                      16
+  #define NIG_REG_INT_STS_WR_7_P2_LB_TC8_PAUSE_TOO_LONG_INT_K2_E5                                            (0x1<<17) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_7_P2_LB_TC8_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                      17
+#define NIG_REG_INT_STS_CLR_7_K2_E5                                                                          0x5000bcUL //Access:RC   DataWidth:0x12   // Multi Field Register.
+  #define NIG_REG_INT_STS_CLR_7_P2_TX_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<0) // Triggered by TX path being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_7_P2_TX_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         0
+  #define NIG_REG_INT_STS_CLR_7_P2_TC0_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<1) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_7_P2_TC0_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        1
+  #define NIG_REG_INT_STS_CLR_7_P2_TC1_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<2) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_7_P2_TC1_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        2
+  #define NIG_REG_INT_STS_CLR_7_P2_TC2_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<3) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_7_P2_TC2_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        3
+  #define NIG_REG_INT_STS_CLR_7_P2_TC3_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<4) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_7_P2_TC3_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        4
+  #define NIG_REG_INT_STS_CLR_7_P2_TC4_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<5) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_7_P2_TC4_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        5
+  #define NIG_REG_INT_STS_CLR_7_P2_TC5_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<6) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_7_P2_TC5_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        6
+  #define NIG_REG_INT_STS_CLR_7_P2_TC6_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<7) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_7_P2_TC6_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        7
+  #define NIG_REG_INT_STS_CLR_7_P2_TC7_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<8) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_7_P2_TC7_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        8
+  #define NIG_REG_INT_STS_CLR_7_P2_LB_TC0_PAUSE_TOO_LONG_INT_K2_E5                                           (0x1<<9) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_7_P2_LB_TC0_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                     9
+  #define NIG_REG_INT_STS_CLR_7_P2_LB_TC1_PAUSE_TOO_LONG_INT_K2_E5                                           (0x1<<10) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_7_P2_LB_TC1_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                     10
+  #define NIG_REG_INT_STS_CLR_7_P2_LB_TC2_PAUSE_TOO_LONG_INT_K2_E5                                           (0x1<<11) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_7_P2_LB_TC2_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                     11
+  #define NIG_REG_INT_STS_CLR_7_P2_LB_TC3_PAUSE_TOO_LONG_INT_K2_E5                                           (0x1<<12) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_7_P2_LB_TC3_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                     12
+  #define NIG_REG_INT_STS_CLR_7_P2_LB_TC4_PAUSE_TOO_LONG_INT_K2_E5                                           (0x1<<13) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_7_P2_LB_TC4_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                     13
+  #define NIG_REG_INT_STS_CLR_7_P2_LB_TC5_PAUSE_TOO_LONG_INT_K2_E5                                           (0x1<<14) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_7_P2_LB_TC5_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                     14
+  #define NIG_REG_INT_STS_CLR_7_P2_LB_TC6_PAUSE_TOO_LONG_INT_K2_E5                                           (0x1<<15) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_7_P2_LB_TC6_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                     15
+  #define NIG_REG_INT_STS_CLR_7_P2_LB_TC7_PAUSE_TOO_LONG_INT_K2_E5                                           (0x1<<16) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_7_P2_LB_TC7_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                     16
+  #define NIG_REG_INT_STS_CLR_7_P2_LB_TC8_PAUSE_TOO_LONG_INT_K2_E5                                           (0x1<<17) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_7_P2_LB_TC8_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                     17
+#define NIG_REG_INT_STS_8_K2_E5                                                                              0x5000c0UL //Access:R    DataWidth:0x16   // Multi Field Register.
+  #define NIG_REG_INT_STS_8_P3_PURELB_SOPQ_ERROR_K2_E5                                                       (0x1<<0) // Error in the pure-loopback SOPQ.
+  #define NIG_REG_INT_STS_8_P3_PURELB_SOPQ_ERROR_K2_E5_SHIFT                                                 0
+  #define NIG_REG_INT_STS_8_P3_RX_MACFIFO_ERROR_K2_E5                                                        (0x1<<1) // Error in RX MAC FIFO.
+  #define NIG_REG_INT_STS_8_P3_RX_MACFIFO_ERROR_K2_E5_SHIFT                                                  1
+  #define NIG_REG_INT_STS_8_P3_TX_MACFIFO_ERROR_K2_E5                                                        (0x1<<2) // Error in TX MAC FIFO.
+  #define NIG_REG_INT_STS_8_P3_TX_MACFIFO_ERROR_K2_E5_SHIFT                                                  2
+  #define NIG_REG_INT_STS_8_P3_TX_BMB_FIFO_ERROR_K2_E5                                                       (0x1<<3) // FIFO error in TX BMB FIFO.
+  #define NIG_REG_INT_STS_8_P3_TX_BMB_FIFO_ERROR_K2_E5_SHIFT                                                 3
+  #define NIG_REG_INT_STS_8_P3_LB_BMB_FIFO_ERROR_K2_E5                                                       (0x1<<4) // FIFO error in LB BMB FIFO.
+  #define NIG_REG_INT_STS_8_P3_LB_BMB_FIFO_ERROR_K2_E5_SHIFT                                                 4
+  #define NIG_REG_INT_STS_8_P3_TX_BTB_FIFO_ERROR_K2_E5                                                       (0x1<<5) // Error in BTB FIFO for TX path.
+  #define NIG_REG_INT_STS_8_P3_TX_BTB_FIFO_ERROR_K2_E5_SHIFT                                                 5
+  #define NIG_REG_INT_STS_8_P3_LB_BTB_FIFO_ERROR_K2_E5                                                       (0x1<<6) // Error in BTB FIFO for LB path.
+  #define NIG_REG_INT_STS_8_P3_LB_BTB_FIFO_ERROR_K2_E5_SHIFT                                                 6
+  #define NIG_REG_INT_STS_8_P3_RX_LLH_DFIFO_ERROR_K2_E5                                                      (0x1<<7) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_8_P3_RX_LLH_DFIFO_ERROR_K2_E5_SHIFT                                                7
+  #define NIG_REG_INT_STS_8_P3_TX_LLH_DFIFO_ERROR_K2_E5                                                      (0x1<<8) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_8_P3_TX_LLH_DFIFO_ERROR_K2_E5_SHIFT                                                8
+  #define NIG_REG_INT_STS_8_P3_LB_LLH_DFIFO_ERROR_K2_E5                                                      (0x1<<9) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_8_P3_LB_LLH_DFIFO_ERROR_K2_E5_SHIFT                                                9
+  #define NIG_REG_INT_STS_8_P3_RX_LLH_HFIFO_ERROR_K2_E5                                                      (0x1<<10) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_8_P3_RX_LLH_HFIFO_ERROR_K2_E5_SHIFT                                                10
+  #define NIG_REG_INT_STS_8_P3_TX_LLH_HFIFO_ERROR_K2_E5                                                      (0x1<<11) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_8_P3_TX_LLH_HFIFO_ERROR_K2_E5_SHIFT                                                11
+  #define NIG_REG_INT_STS_8_P3_LB_LLH_HFIFO_ERROR_K2_E5                                                      (0x1<<12) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_8_P3_LB_LLH_HFIFO_ERROR_K2_E5_SHIFT                                                12
+  #define NIG_REG_INT_STS_8_P3_RX_LLH_RFIFO_ERROR_K2_E5                                                      (0x1<<13) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_8_P3_RX_LLH_RFIFO_ERROR_K2_E5_SHIFT                                                13
+  #define NIG_REG_INT_STS_8_P3_TX_LLH_RFIFO_ERROR_K2_E5                                                      (0x1<<14) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_8_P3_TX_LLH_RFIFO_ERROR_K2_E5_SHIFT                                                14
+  #define NIG_REG_INT_STS_8_P3_LB_LLH_RFIFO_ERROR_K2_E5                                                      (0x1<<15) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_8_P3_LB_LLH_RFIFO_ERROR_K2_E5_SHIFT                                                15
+  #define NIG_REG_INT_STS_8_P3_STORM_FIFO_ERROR_K2_E5                                                        (0x1<<16) // FIFO error in STORM message FIFO.
+  #define NIG_REG_INT_STS_8_P3_STORM_FIFO_ERROR_K2_E5_SHIFT                                                  16
+  #define NIG_REG_INT_STS_8_P3_STORM_DSCR_FIFO_ERROR_K2_E5                                                   (0x1<<17) // FIFO error in STORM descriptor FIFO.
+  #define NIG_REG_INT_STS_8_P3_STORM_DSCR_FIFO_ERROR_K2_E5_SHIFT                                             17
+  #define NIG_REG_INT_STS_8_P3_TX_GNT_FIFO_ERROR_K2_E5                                                       (0x1<<18) // Error in grant FIFO.
+  #define NIG_REG_INT_STS_8_P3_TX_GNT_FIFO_ERROR_K2_E5_SHIFT                                                 18
+  #define NIG_REG_INT_STS_8_P3_LB_GNT_FIFO_ERROR_K2_E5                                                       (0x1<<19) // Error in grant FIFO.
+  #define NIG_REG_INT_STS_8_P3_LB_GNT_FIFO_ERROR_K2_E5_SHIFT                                                 19
+  #define NIG_REG_INT_STS_8_P3_TX_ORDER_FIFO_ERROR_E5                                                        (0x1<<20) // Error in LLH order FIFO.
+  #define NIG_REG_INT_STS_8_P3_TX_ORDER_FIFO_ERROR_E5_SHIFT                                                  20
+  #define NIG_REG_INT_STS_8_P3_LB_ORDER_FIFO_ERROR_E5                                                        (0x1<<21) // Error in LLH order FIFO.
+  #define NIG_REG_INT_STS_8_P3_LB_ORDER_FIFO_ERROR_E5_SHIFT                                                  21
+#define NIG_REG_INT_MASK_8_K2_E5                                                                             0x5000c4UL //Access:RW   DataWidth:0x16   // Multi Field Register.
+  #define NIG_REG_INT_MASK_8_P3_PURELB_SOPQ_ERROR_K2_E5                                                      (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_PURELB_SOPQ_ERROR .
+  #define NIG_REG_INT_MASK_8_P3_PURELB_SOPQ_ERROR_K2_E5_SHIFT                                                0
+  #define NIG_REG_INT_MASK_8_P3_RX_MACFIFO_ERROR_K2_E5                                                       (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_RX_MACFIFO_ERROR .
+  #define NIG_REG_INT_MASK_8_P3_RX_MACFIFO_ERROR_K2_E5_SHIFT                                                 1
+  #define NIG_REG_INT_MASK_8_P3_TX_MACFIFO_ERROR_K2_E5                                                       (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_TX_MACFIFO_ERROR .
+  #define NIG_REG_INT_MASK_8_P3_TX_MACFIFO_ERROR_K2_E5_SHIFT                                                 2
+  #define NIG_REG_INT_MASK_8_P3_TX_BMB_FIFO_ERROR_K2_E5                                                      (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_TX_BMB_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_8_P3_TX_BMB_FIFO_ERROR_K2_E5_SHIFT                                                3
+  #define NIG_REG_INT_MASK_8_P3_LB_BMB_FIFO_ERROR_K2_E5                                                      (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_LB_BMB_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_8_P3_LB_BMB_FIFO_ERROR_K2_E5_SHIFT                                                4
+  #define NIG_REG_INT_MASK_8_P3_TX_BTB_FIFO_ERROR_K2_E5                                                      (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_TX_BTB_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_8_P3_TX_BTB_FIFO_ERROR_K2_E5_SHIFT                                                5
+  #define NIG_REG_INT_MASK_8_P3_LB_BTB_FIFO_ERROR_K2_E5                                                      (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_LB_BTB_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_8_P3_LB_BTB_FIFO_ERROR_K2_E5_SHIFT                                                6
+  #define NIG_REG_INT_MASK_8_P3_RX_LLH_DFIFO_ERROR_K2_E5                                                     (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_RX_LLH_DFIFO_ERROR .
+  #define NIG_REG_INT_MASK_8_P3_RX_LLH_DFIFO_ERROR_K2_E5_SHIFT                                               7
+  #define NIG_REG_INT_MASK_8_P3_TX_LLH_DFIFO_ERROR_K2_E5                                                     (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_TX_LLH_DFIFO_ERROR .
+  #define NIG_REG_INT_MASK_8_P3_TX_LLH_DFIFO_ERROR_K2_E5_SHIFT                                               8
+  #define NIG_REG_INT_MASK_8_P3_LB_LLH_DFIFO_ERROR_K2_E5                                                     (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_LB_LLH_DFIFO_ERROR .
+  #define NIG_REG_INT_MASK_8_P3_LB_LLH_DFIFO_ERROR_K2_E5_SHIFT                                               9
+  #define NIG_REG_INT_MASK_8_P3_RX_LLH_HFIFO_ERROR_K2_E5                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_RX_LLH_HFIFO_ERROR .
+  #define NIG_REG_INT_MASK_8_P3_RX_LLH_HFIFO_ERROR_K2_E5_SHIFT                                               10
+  #define NIG_REG_INT_MASK_8_P3_TX_LLH_HFIFO_ERROR_K2_E5                                                     (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_TX_LLH_HFIFO_ERROR .
+  #define NIG_REG_INT_MASK_8_P3_TX_LLH_HFIFO_ERROR_K2_E5_SHIFT                                               11
+  #define NIG_REG_INT_MASK_8_P3_LB_LLH_HFIFO_ERROR_K2_E5                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_LB_LLH_HFIFO_ERROR .
+  #define NIG_REG_INT_MASK_8_P3_LB_LLH_HFIFO_ERROR_K2_E5_SHIFT                                               12
+  #define NIG_REG_INT_MASK_8_P3_RX_LLH_RFIFO_ERROR_K2_E5                                                     (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_RX_LLH_RFIFO_ERROR .
+  #define NIG_REG_INT_MASK_8_P3_RX_LLH_RFIFO_ERROR_K2_E5_SHIFT                                               13
+  #define NIG_REG_INT_MASK_8_P3_TX_LLH_RFIFO_ERROR_K2_E5                                                     (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_TX_LLH_RFIFO_ERROR .
+  #define NIG_REG_INT_MASK_8_P3_TX_LLH_RFIFO_ERROR_K2_E5_SHIFT                                               14
+  #define NIG_REG_INT_MASK_8_P3_LB_LLH_RFIFO_ERROR_K2_E5                                                     (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_LB_LLH_RFIFO_ERROR .
+  #define NIG_REG_INT_MASK_8_P3_LB_LLH_RFIFO_ERROR_K2_E5_SHIFT                                               15
+  #define NIG_REG_INT_MASK_8_P3_STORM_FIFO_ERROR_K2_E5                                                       (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_STORM_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_8_P3_STORM_FIFO_ERROR_K2_E5_SHIFT                                                 16
+  #define NIG_REG_INT_MASK_8_P3_STORM_DSCR_FIFO_ERROR_K2_E5                                                  (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_STORM_DSCR_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_8_P3_STORM_DSCR_FIFO_ERROR_K2_E5_SHIFT                                            17
+  #define NIG_REG_INT_MASK_8_P3_TX_GNT_FIFO_ERROR_K2_E5                                                      (0x1<<18) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_TX_GNT_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_8_P3_TX_GNT_FIFO_ERROR_K2_E5_SHIFT                                                18
+  #define NIG_REG_INT_MASK_8_P3_LB_GNT_FIFO_ERROR_K2_E5                                                      (0x1<<19) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_LB_GNT_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_8_P3_LB_GNT_FIFO_ERROR_K2_E5_SHIFT                                                19
+  #define NIG_REG_INT_MASK_8_P3_TX_ORDER_FIFO_ERROR_E5                                                       (0x1<<20) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_TX_ORDER_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_8_P3_TX_ORDER_FIFO_ERROR_E5_SHIFT                                                 20
+  #define NIG_REG_INT_MASK_8_P3_LB_ORDER_FIFO_ERROR_E5                                                       (0x1<<21) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_LB_ORDER_FIFO_ERROR .
+  #define NIG_REG_INT_MASK_8_P3_LB_ORDER_FIFO_ERROR_E5_SHIFT                                                 21
+#define NIG_REG_INT_STS_WR_8_K2_E5                                                                           0x5000c8UL //Access:WR   DataWidth:0x16   // Multi Field Register.
+  #define NIG_REG_INT_STS_WR_8_P3_PURELB_SOPQ_ERROR_K2_E5                                                    (0x1<<0) // Error in the pure-loopback SOPQ.
+  #define NIG_REG_INT_STS_WR_8_P3_PURELB_SOPQ_ERROR_K2_E5_SHIFT                                              0
+  #define NIG_REG_INT_STS_WR_8_P3_RX_MACFIFO_ERROR_K2_E5                                                     (0x1<<1) // Error in RX MAC FIFO.
+  #define NIG_REG_INT_STS_WR_8_P3_RX_MACFIFO_ERROR_K2_E5_SHIFT                                               1
+  #define NIG_REG_INT_STS_WR_8_P3_TX_MACFIFO_ERROR_K2_E5                                                     (0x1<<2) // Error in TX MAC FIFO.
+  #define NIG_REG_INT_STS_WR_8_P3_TX_MACFIFO_ERROR_K2_E5_SHIFT                                               2
+  #define NIG_REG_INT_STS_WR_8_P3_TX_BMB_FIFO_ERROR_K2_E5                                                    (0x1<<3) // FIFO error in TX BMB FIFO.
+  #define NIG_REG_INT_STS_WR_8_P3_TX_BMB_FIFO_ERROR_K2_E5_SHIFT                                              3
+  #define NIG_REG_INT_STS_WR_8_P3_LB_BMB_FIFO_ERROR_K2_E5                                                    (0x1<<4) // FIFO error in LB BMB FIFO.
+  #define NIG_REG_INT_STS_WR_8_P3_LB_BMB_FIFO_ERROR_K2_E5_SHIFT                                              4
+  #define NIG_REG_INT_STS_WR_8_P3_TX_BTB_FIFO_ERROR_K2_E5                                                    (0x1<<5) // Error in BTB FIFO for TX path.
+  #define NIG_REG_INT_STS_WR_8_P3_TX_BTB_FIFO_ERROR_K2_E5_SHIFT                                              5
+  #define NIG_REG_INT_STS_WR_8_P3_LB_BTB_FIFO_ERROR_K2_E5                                                    (0x1<<6) // Error in BTB FIFO for LB path.
+  #define NIG_REG_INT_STS_WR_8_P3_LB_BTB_FIFO_ERROR_K2_E5_SHIFT                                              6
+  #define NIG_REG_INT_STS_WR_8_P3_RX_LLH_DFIFO_ERROR_K2_E5                                                   (0x1<<7) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_WR_8_P3_RX_LLH_DFIFO_ERROR_K2_E5_SHIFT                                             7
+  #define NIG_REG_INT_STS_WR_8_P3_TX_LLH_DFIFO_ERROR_K2_E5                                                   (0x1<<8) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_WR_8_P3_TX_LLH_DFIFO_ERROR_K2_E5_SHIFT                                             8
+  #define NIG_REG_INT_STS_WR_8_P3_LB_LLH_DFIFO_ERROR_K2_E5                                                   (0x1<<9) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_WR_8_P3_LB_LLH_DFIFO_ERROR_K2_E5_SHIFT                                             9
+  #define NIG_REG_INT_STS_WR_8_P3_RX_LLH_HFIFO_ERROR_K2_E5                                                   (0x1<<10) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_WR_8_P3_RX_LLH_HFIFO_ERROR_K2_E5_SHIFT                                             10
+  #define NIG_REG_INT_STS_WR_8_P3_TX_LLH_HFIFO_ERROR_K2_E5                                                   (0x1<<11) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_WR_8_P3_TX_LLH_HFIFO_ERROR_K2_E5_SHIFT                                             11
+  #define NIG_REG_INT_STS_WR_8_P3_LB_LLH_HFIFO_ERROR_K2_E5                                                   (0x1<<12) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_WR_8_P3_LB_LLH_HFIFO_ERROR_K2_E5_SHIFT                                             12
+  #define NIG_REG_INT_STS_WR_8_P3_RX_LLH_RFIFO_ERROR_K2_E5                                                   (0x1<<13) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_WR_8_P3_RX_LLH_RFIFO_ERROR_K2_E5_SHIFT                                             13
+  #define NIG_REG_INT_STS_WR_8_P3_TX_LLH_RFIFO_ERROR_K2_E5                                                   (0x1<<14) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_WR_8_P3_TX_LLH_RFIFO_ERROR_K2_E5_SHIFT                                             14
+  #define NIG_REG_INT_STS_WR_8_P3_LB_LLH_RFIFO_ERROR_K2_E5                                                   (0x1<<15) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_WR_8_P3_LB_LLH_RFIFO_ERROR_K2_E5_SHIFT                                             15
+  #define NIG_REG_INT_STS_WR_8_P3_STORM_FIFO_ERROR_K2_E5                                                     (0x1<<16) // FIFO error in STORM message FIFO.
+  #define NIG_REG_INT_STS_WR_8_P3_STORM_FIFO_ERROR_K2_E5_SHIFT                                               16
+  #define NIG_REG_INT_STS_WR_8_P3_STORM_DSCR_FIFO_ERROR_K2_E5                                                (0x1<<17) // FIFO error in STORM descriptor FIFO.
+  #define NIG_REG_INT_STS_WR_8_P3_STORM_DSCR_FIFO_ERROR_K2_E5_SHIFT                                          17
+  #define NIG_REG_INT_STS_WR_8_P3_TX_GNT_FIFO_ERROR_K2_E5                                                    (0x1<<18) // Error in grant FIFO.
+  #define NIG_REG_INT_STS_WR_8_P3_TX_GNT_FIFO_ERROR_K2_E5_SHIFT                                              18
+  #define NIG_REG_INT_STS_WR_8_P3_LB_GNT_FIFO_ERROR_K2_E5                                                    (0x1<<19) // Error in grant FIFO.
+  #define NIG_REG_INT_STS_WR_8_P3_LB_GNT_FIFO_ERROR_K2_E5_SHIFT                                              19
+  #define NIG_REG_INT_STS_WR_8_P3_TX_ORDER_FIFO_ERROR_E5                                                     (0x1<<20) // Error in LLH order FIFO.
+  #define NIG_REG_INT_STS_WR_8_P3_TX_ORDER_FIFO_ERROR_E5_SHIFT                                               20
+  #define NIG_REG_INT_STS_WR_8_P3_LB_ORDER_FIFO_ERROR_E5                                                     (0x1<<21) // Error in LLH order FIFO.
+  #define NIG_REG_INT_STS_WR_8_P3_LB_ORDER_FIFO_ERROR_E5_SHIFT                                               21
+#define NIG_REG_INT_STS_CLR_8_K2_E5                                                                          0x5000ccUL //Access:RC   DataWidth:0x16   // Multi Field Register.
+  #define NIG_REG_INT_STS_CLR_8_P3_PURELB_SOPQ_ERROR_K2_E5                                                   (0x1<<0) // Error in the pure-loopback SOPQ.
+  #define NIG_REG_INT_STS_CLR_8_P3_PURELB_SOPQ_ERROR_K2_E5_SHIFT                                             0
+  #define NIG_REG_INT_STS_CLR_8_P3_RX_MACFIFO_ERROR_K2_E5                                                    (0x1<<1) // Error in RX MAC FIFO.
+  #define NIG_REG_INT_STS_CLR_8_P3_RX_MACFIFO_ERROR_K2_E5_SHIFT                                              1
+  #define NIG_REG_INT_STS_CLR_8_P3_TX_MACFIFO_ERROR_K2_E5                                                    (0x1<<2) // Error in TX MAC FIFO.
+  #define NIG_REG_INT_STS_CLR_8_P3_TX_MACFIFO_ERROR_K2_E5_SHIFT                                              2
+  #define NIG_REG_INT_STS_CLR_8_P3_TX_BMB_FIFO_ERROR_K2_E5                                                   (0x1<<3) // FIFO error in TX BMB FIFO.
+  #define NIG_REG_INT_STS_CLR_8_P3_TX_BMB_FIFO_ERROR_K2_E5_SHIFT                                             3
+  #define NIG_REG_INT_STS_CLR_8_P3_LB_BMB_FIFO_ERROR_K2_E5                                                   (0x1<<4) // FIFO error in LB BMB FIFO.
+  #define NIG_REG_INT_STS_CLR_8_P3_LB_BMB_FIFO_ERROR_K2_E5_SHIFT                                             4
+  #define NIG_REG_INT_STS_CLR_8_P3_TX_BTB_FIFO_ERROR_K2_E5                                                   (0x1<<5) // Error in BTB FIFO for TX path.
+  #define NIG_REG_INT_STS_CLR_8_P3_TX_BTB_FIFO_ERROR_K2_E5_SHIFT                                             5
+  #define NIG_REG_INT_STS_CLR_8_P3_LB_BTB_FIFO_ERROR_K2_E5                                                   (0x1<<6) // Error in BTB FIFO for LB path.
+  #define NIG_REG_INT_STS_CLR_8_P3_LB_BTB_FIFO_ERROR_K2_E5_SHIFT                                             6
+  #define NIG_REG_INT_STS_CLR_8_P3_RX_LLH_DFIFO_ERROR_K2_E5                                                  (0x1<<7) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_CLR_8_P3_RX_LLH_DFIFO_ERROR_K2_E5_SHIFT                                            7
+  #define NIG_REG_INT_STS_CLR_8_P3_TX_LLH_DFIFO_ERROR_K2_E5                                                  (0x1<<8) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_CLR_8_P3_TX_LLH_DFIFO_ERROR_K2_E5_SHIFT                                            8
+  #define NIG_REG_INT_STS_CLR_8_P3_LB_LLH_DFIFO_ERROR_K2_E5                                                  (0x1<<9) // Error in LLH Data FIFO.
+  #define NIG_REG_INT_STS_CLR_8_P3_LB_LLH_DFIFO_ERROR_K2_E5_SHIFT                                            9
+  #define NIG_REG_INT_STS_CLR_8_P3_RX_LLH_HFIFO_ERROR_K2_E5                                                  (0x1<<10) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_CLR_8_P3_RX_LLH_HFIFO_ERROR_K2_E5_SHIFT                                            10
+  #define NIG_REG_INT_STS_CLR_8_P3_TX_LLH_HFIFO_ERROR_K2_E5                                                  (0x1<<11) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_CLR_8_P3_TX_LLH_HFIFO_ERROR_K2_E5_SHIFT                                            11
+  #define NIG_REG_INT_STS_CLR_8_P3_LB_LLH_HFIFO_ERROR_K2_E5                                                  (0x1<<12) // Error in LLH Header FIFO.
+  #define NIG_REG_INT_STS_CLR_8_P3_LB_LLH_HFIFO_ERROR_K2_E5_SHIFT                                            12
+  #define NIG_REG_INT_STS_CLR_8_P3_RX_LLH_RFIFO_ERROR_K2_E5                                                  (0x1<<13) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_CLR_8_P3_RX_LLH_RFIFO_ERROR_K2_E5_SHIFT                                            13
+  #define NIG_REG_INT_STS_CLR_8_P3_TX_LLH_RFIFO_ERROR_K2_E5                                                  (0x1<<14) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_CLR_8_P3_TX_LLH_RFIFO_ERROR_K2_E5_SHIFT                                            14
+  #define NIG_REG_INT_STS_CLR_8_P3_LB_LLH_RFIFO_ERROR_K2_E5                                                  (0x1<<15) // Error in LLH Result FIFO.
+  #define NIG_REG_INT_STS_CLR_8_P3_LB_LLH_RFIFO_ERROR_K2_E5_SHIFT                                            15
+  #define NIG_REG_INT_STS_CLR_8_P3_STORM_FIFO_ERROR_K2_E5                                                    (0x1<<16) // FIFO error in STORM message FIFO.
+  #define NIG_REG_INT_STS_CLR_8_P3_STORM_FIFO_ERROR_K2_E5_SHIFT                                              16
+  #define NIG_REG_INT_STS_CLR_8_P3_STORM_DSCR_FIFO_ERROR_K2_E5                                               (0x1<<17) // FIFO error in STORM descriptor FIFO.
+  #define NIG_REG_INT_STS_CLR_8_P3_STORM_DSCR_FIFO_ERROR_K2_E5_SHIFT                                         17
+  #define NIG_REG_INT_STS_CLR_8_P3_TX_GNT_FIFO_ERROR_K2_E5                                                   (0x1<<18) // Error in grant FIFO.
+  #define NIG_REG_INT_STS_CLR_8_P3_TX_GNT_FIFO_ERROR_K2_E5_SHIFT                                             18
+  #define NIG_REG_INT_STS_CLR_8_P3_LB_GNT_FIFO_ERROR_K2_E5                                                   (0x1<<19) // Error in grant FIFO.
+  #define NIG_REG_INT_STS_CLR_8_P3_LB_GNT_FIFO_ERROR_K2_E5_SHIFT                                             19
+  #define NIG_REG_INT_STS_CLR_8_P3_TX_ORDER_FIFO_ERROR_E5                                                    (0x1<<20) // Error in LLH order FIFO.
+  #define NIG_REG_INT_STS_CLR_8_P3_TX_ORDER_FIFO_ERROR_E5_SHIFT                                              20
+  #define NIG_REG_INT_STS_CLR_8_P3_LB_ORDER_FIFO_ERROR_E5                                                    (0x1<<21) // Error in LLH order FIFO.
+  #define NIG_REG_INT_STS_CLR_8_P3_LB_ORDER_FIFO_ERROR_E5_SHIFT                                              21
+#define NIG_REG_INT_STS_9_K2_E5                                                                              0x5000d0UL //Access:R    DataWidth:0x12   // Multi Field Register.
+  #define NIG_REG_INT_STS_9_P3_TX_PAUSE_TOO_LONG_INT_K2_E5                                                   (0x1<<0) // Triggered by TX path being paused for the configured period of time.
+  #define NIG_REG_INT_STS_9_P3_TX_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                             0
+  #define NIG_REG_INT_STS_9_P3_TC0_PAUSE_TOO_LONG_INT_K2_E5                                                  (0x1<<1) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_9_P3_TC0_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                            1
+  #define NIG_REG_INT_STS_9_P3_TC1_PAUSE_TOO_LONG_INT_K2_E5                                                  (0x1<<2) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_9_P3_TC1_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                            2
+  #define NIG_REG_INT_STS_9_P3_TC2_PAUSE_TOO_LONG_INT_K2_E5                                                  (0x1<<3) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_9_P3_TC2_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                            3
+  #define NIG_REG_INT_STS_9_P3_TC3_PAUSE_TOO_LONG_INT_K2_E5                                                  (0x1<<4) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_9_P3_TC3_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                            4
+  #define NIG_REG_INT_STS_9_P3_TC4_PAUSE_TOO_LONG_INT_K2_E5                                                  (0x1<<5) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_9_P3_TC4_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                            5
+  #define NIG_REG_INT_STS_9_P3_TC5_PAUSE_TOO_LONG_INT_K2_E5                                                  (0x1<<6) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_9_P3_TC5_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                            6
+  #define NIG_REG_INT_STS_9_P3_TC6_PAUSE_TOO_LONG_INT_K2_E5                                                  (0x1<<7) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_9_P3_TC6_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                            7
+  #define NIG_REG_INT_STS_9_P3_TC7_PAUSE_TOO_LONG_INT_K2_E5                                                  (0x1<<8) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_9_P3_TC7_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                            8
+  #define NIG_REG_INT_STS_9_P3_LB_TC0_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<9) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_9_P3_LB_TC0_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         9
+  #define NIG_REG_INT_STS_9_P3_LB_TC1_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<10) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_9_P3_LB_TC1_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         10
+  #define NIG_REG_INT_STS_9_P3_LB_TC2_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<11) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_9_P3_LB_TC2_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         11
+  #define NIG_REG_INT_STS_9_P3_LB_TC3_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<12) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_9_P3_LB_TC3_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         12
+  #define NIG_REG_INT_STS_9_P3_LB_TC4_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<13) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_9_P3_LB_TC4_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         13
+  #define NIG_REG_INT_STS_9_P3_LB_TC5_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<14) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_9_P3_LB_TC5_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         14
+  #define NIG_REG_INT_STS_9_P3_LB_TC6_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<15) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_9_P3_LB_TC6_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         15
+  #define NIG_REG_INT_STS_9_P3_LB_TC7_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<16) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_9_P3_LB_TC7_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         16
+  #define NIG_REG_INT_STS_9_P3_LB_TC8_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<17) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_9_P3_LB_TC8_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         17
+#define NIG_REG_INT_MASK_9_K2_E5                                                                             0x5000d4UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define NIG_REG_INT_MASK_9_P3_TX_PAUSE_TOO_LONG_INT_K2_E5                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TX_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_9_P3_TX_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                            0
+  #define NIG_REG_INT_MASK_9_P3_TC0_PAUSE_TOO_LONG_INT_K2_E5                                                 (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TC0_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_9_P3_TC0_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                           1
+  #define NIG_REG_INT_MASK_9_P3_TC1_PAUSE_TOO_LONG_INT_K2_E5                                                 (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TC1_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_9_P3_TC1_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                           2
+  #define NIG_REG_INT_MASK_9_P3_TC2_PAUSE_TOO_LONG_INT_K2_E5                                                 (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TC2_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_9_P3_TC2_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                           3
+  #define NIG_REG_INT_MASK_9_P3_TC3_PAUSE_TOO_LONG_INT_K2_E5                                                 (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TC3_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_9_P3_TC3_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                           4
+  #define NIG_REG_INT_MASK_9_P3_TC4_PAUSE_TOO_LONG_INT_K2_E5                                                 (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TC4_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_9_P3_TC4_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                           5
+  #define NIG_REG_INT_MASK_9_P3_TC5_PAUSE_TOO_LONG_INT_K2_E5                                                 (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TC5_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_9_P3_TC5_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                           6
+  #define NIG_REG_INT_MASK_9_P3_TC6_PAUSE_TOO_LONG_INT_K2_E5                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TC6_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_9_P3_TC6_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                           7
+  #define NIG_REG_INT_MASK_9_P3_TC7_PAUSE_TOO_LONG_INT_K2_E5                                                 (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TC7_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_9_P3_TC7_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                           8
+  #define NIG_REG_INT_MASK_9_P3_LB_TC0_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC0_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_9_P3_LB_TC0_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        9
+  #define NIG_REG_INT_MASK_9_P3_LB_TC1_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC1_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_9_P3_LB_TC1_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        10
+  #define NIG_REG_INT_MASK_9_P3_LB_TC2_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC2_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_9_P3_LB_TC2_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        11
+  #define NIG_REG_INT_MASK_9_P3_LB_TC3_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC3_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_9_P3_LB_TC3_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        12
+  #define NIG_REG_INT_MASK_9_P3_LB_TC4_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC4_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_9_P3_LB_TC4_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        13
+  #define NIG_REG_INT_MASK_9_P3_LB_TC5_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC5_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_9_P3_LB_TC5_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        14
+  #define NIG_REG_INT_MASK_9_P3_LB_TC6_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC6_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_9_P3_LB_TC6_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        15
+  #define NIG_REG_INT_MASK_9_P3_LB_TC7_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC7_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_9_P3_LB_TC7_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        16
+  #define NIG_REG_INT_MASK_9_P3_LB_TC8_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC8_PAUSE_TOO_LONG_INT .
+  #define NIG_REG_INT_MASK_9_P3_LB_TC8_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        17
+#define NIG_REG_INT_STS_WR_9_K2_E5                                                                           0x5000d8UL //Access:WR   DataWidth:0x12   // Multi Field Register.
+  #define NIG_REG_INT_STS_WR_9_P3_TX_PAUSE_TOO_LONG_INT_K2_E5                                                (0x1<<0) // Triggered by TX path being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_9_P3_TX_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                          0
+  #define NIG_REG_INT_STS_WR_9_P3_TC0_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<1) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_9_P3_TC0_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         1
+  #define NIG_REG_INT_STS_WR_9_P3_TC1_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<2) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_9_P3_TC1_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         2
+  #define NIG_REG_INT_STS_WR_9_P3_TC2_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<3) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_9_P3_TC2_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         3
+  #define NIG_REG_INT_STS_WR_9_P3_TC3_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<4) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_9_P3_TC3_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         4
+  #define NIG_REG_INT_STS_WR_9_P3_TC4_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<5) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_9_P3_TC4_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         5
+  #define NIG_REG_INT_STS_WR_9_P3_TC5_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<6) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_9_P3_TC5_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         6
+  #define NIG_REG_INT_STS_WR_9_P3_TC6_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<7) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_9_P3_TC6_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         7
+  #define NIG_REG_INT_STS_WR_9_P3_TC7_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<8) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_9_P3_TC7_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         8
+  #define NIG_REG_INT_STS_WR_9_P3_LB_TC0_PAUSE_TOO_LONG_INT_K2_E5                                            (0x1<<9) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_9_P3_LB_TC0_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                      9
+  #define NIG_REG_INT_STS_WR_9_P3_LB_TC1_PAUSE_TOO_LONG_INT_K2_E5                                            (0x1<<10) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_9_P3_LB_TC1_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                      10
+  #define NIG_REG_INT_STS_WR_9_P3_LB_TC2_PAUSE_TOO_LONG_INT_K2_E5                                            (0x1<<11) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_9_P3_LB_TC2_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                      11
+  #define NIG_REG_INT_STS_WR_9_P3_LB_TC3_PAUSE_TOO_LONG_INT_K2_E5                                            (0x1<<12) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_9_P3_LB_TC3_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                      12
+  #define NIG_REG_INT_STS_WR_9_P3_LB_TC4_PAUSE_TOO_LONG_INT_K2_E5                                            (0x1<<13) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_9_P3_LB_TC4_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                      13
+  #define NIG_REG_INT_STS_WR_9_P3_LB_TC5_PAUSE_TOO_LONG_INT_K2_E5                                            (0x1<<14) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_9_P3_LB_TC5_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                      14
+  #define NIG_REG_INT_STS_WR_9_P3_LB_TC6_PAUSE_TOO_LONG_INT_K2_E5                                            (0x1<<15) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_9_P3_LB_TC6_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                      15
+  #define NIG_REG_INT_STS_WR_9_P3_LB_TC7_PAUSE_TOO_LONG_INT_K2_E5                                            (0x1<<16) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_9_P3_LB_TC7_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                      16
+  #define NIG_REG_INT_STS_WR_9_P3_LB_TC8_PAUSE_TOO_LONG_INT_K2_E5                                            (0x1<<17) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_WR_9_P3_LB_TC8_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                      17
+#define NIG_REG_INT_STS_CLR_9_K2_E5                                                                          0x5000dcUL //Access:RC   DataWidth:0x12   // Multi Field Register.
+  #define NIG_REG_INT_STS_CLR_9_P3_TX_PAUSE_TOO_LONG_INT_K2_E5                                               (0x1<<0) // Triggered by TX path being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_9_P3_TX_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                         0
+  #define NIG_REG_INT_STS_CLR_9_P3_TC0_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<1) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_9_P3_TC0_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        1
+  #define NIG_REG_INT_STS_CLR_9_P3_TC1_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<2) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_9_P3_TC1_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        2
+  #define NIG_REG_INT_STS_CLR_9_P3_TC2_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<3) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_9_P3_TC2_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        3
+  #define NIG_REG_INT_STS_CLR_9_P3_TC3_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<4) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_9_P3_TC3_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        4
+  #define NIG_REG_INT_STS_CLR_9_P3_TC4_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<5) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_9_P3_TC4_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        5
+  #define NIG_REG_INT_STS_CLR_9_P3_TC5_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<6) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_9_P3_TC5_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        6
+  #define NIG_REG_INT_STS_CLR_9_P3_TC6_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<7) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_9_P3_TC6_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        7
+  #define NIG_REG_INT_STS_CLR_9_P3_TC7_PAUSE_TOO_LONG_INT_K2_E5                                              (0x1<<8) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_9_P3_TC7_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                        8
+  #define NIG_REG_INT_STS_CLR_9_P3_LB_TC0_PAUSE_TOO_LONG_INT_K2_E5                                           (0x1<<9) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_9_P3_LB_TC0_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                     9
+  #define NIG_REG_INT_STS_CLR_9_P3_LB_TC1_PAUSE_TOO_LONG_INT_K2_E5                                           (0x1<<10) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_9_P3_LB_TC1_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                     10
+  #define NIG_REG_INT_STS_CLR_9_P3_LB_TC2_PAUSE_TOO_LONG_INT_K2_E5                                           (0x1<<11) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_9_P3_LB_TC2_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                     11
+  #define NIG_REG_INT_STS_CLR_9_P3_LB_TC3_PAUSE_TOO_LONG_INT_K2_E5                                           (0x1<<12) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_9_P3_LB_TC3_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                     12
+  #define NIG_REG_INT_STS_CLR_9_P3_LB_TC4_PAUSE_TOO_LONG_INT_K2_E5                                           (0x1<<13) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_9_P3_LB_TC4_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                     13
+  #define NIG_REG_INT_STS_CLR_9_P3_LB_TC5_PAUSE_TOO_LONG_INT_K2_E5                                           (0x1<<14) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_9_P3_LB_TC5_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                     14
+  #define NIG_REG_INT_STS_CLR_9_P3_LB_TC6_PAUSE_TOO_LONG_INT_K2_E5                                           (0x1<<15) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_9_P3_LB_TC6_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                     15
+  #define NIG_REG_INT_STS_CLR_9_P3_LB_TC7_PAUSE_TOO_LONG_INT_K2_E5                                           (0x1<<16) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_9_P3_LB_TC7_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                     16
+  #define NIG_REG_INT_STS_CLR_9_P3_LB_TC8_PAUSE_TOO_LONG_INT_K2_E5                                           (0x1<<17) // Triggered by TC being paused for the configured period of time.
+  #define NIG_REG_INT_STS_CLR_9_P3_LB_TC8_PAUSE_TOO_LONG_INT_K2_E5_SHIFT                                     17
+#define NIG_REG_PRTY_MASK_BB                                                                                 0x5000a4UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+#define NIG_REG_PRTY_MASK_K2_E5                                                                              0x5000e4UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define NIG_REG_PRTY_MASK_DATAPATH_PARITY_ERROR                                                            (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS.DATAPATH_PARITY_ERROR .
+  #define NIG_REG_PRTY_MASK_DATAPATH_PARITY_ERROR_SHIFT                                                      0
+#define NIG_REG_INT_STS_10_E5                                                                                0x5000f0UL //Access:R    DataWidth:0x10   // Multi Field Register.
+  #define NIG_REG_INT_STS_10_TX_SOPQ16_ERROR_E5                                                              (0x1<<0) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_10_TX_SOPQ16_ERROR_E5_SHIFT                                                        0
+  #define NIG_REG_INT_STS_10_TX_SOPQ17_ERROR_E5                                                              (0x1<<1) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_10_TX_SOPQ17_ERROR_E5_SHIFT                                                        1
+  #define NIG_REG_INT_STS_10_TX_SOPQ18_ERROR_E5                                                              (0x1<<2) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_10_TX_SOPQ18_ERROR_E5_SHIFT                                                        2
+  #define NIG_REG_INT_STS_10_TX_SOPQ19_ERROR_E5                                                              (0x1<<3) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_10_TX_SOPQ19_ERROR_E5_SHIFT                                                        3
+  #define NIG_REG_INT_STS_10_TX_SOPQ20_ERROR_E5                                                              (0x1<<4) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_10_TX_SOPQ20_ERROR_E5_SHIFT                                                        4
+  #define NIG_REG_INT_STS_10_TX_SOPQ21_ERROR_E5                                                              (0x1<<5) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_10_TX_SOPQ21_ERROR_E5_SHIFT                                                        5
+  #define NIG_REG_INT_STS_10_TX_SOPQ22_ERROR_E5                                                              (0x1<<6) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_10_TX_SOPQ22_ERROR_E5_SHIFT                                                        6
+  #define NIG_REG_INT_STS_10_TX_SOPQ23_ERROR_E5                                                              (0x1<<7) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_10_TX_SOPQ23_ERROR_E5_SHIFT                                                        7
+  #define NIG_REG_INT_STS_10_LB_SOPQ16_ERROR_E5                                                              (0x1<<8) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_10_LB_SOPQ16_ERROR_E5_SHIFT                                                        8
+  #define NIG_REG_INT_STS_10_LB_SOPQ17_ERROR_E5                                                              (0x1<<9) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_10_LB_SOPQ17_ERROR_E5_SHIFT                                                        9
+  #define NIG_REG_INT_STS_10_LB_SOPQ18_ERROR_E5                                                              (0x1<<10) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_10_LB_SOPQ18_ERROR_E5_SHIFT                                                        10
+  #define NIG_REG_INT_STS_10_LB_SOPQ19_ERROR_E5                                                              (0x1<<11) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_10_LB_SOPQ19_ERROR_E5_SHIFT                                                        11
+  #define NIG_REG_INT_STS_10_LB_SOPQ20_ERROR_E5                                                              (0x1<<12) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_10_LB_SOPQ20_ERROR_E5_SHIFT                                                        12
+  #define NIG_REG_INT_STS_10_LB_SOPQ21_ERROR_E5                                                              (0x1<<13) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_10_LB_SOPQ21_ERROR_E5_SHIFT                                                        13
+  #define NIG_REG_INT_STS_10_LB_SOPQ22_ERROR_E5                                                              (0x1<<14) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_10_LB_SOPQ22_ERROR_E5_SHIFT                                                        14
+  #define NIG_REG_INT_STS_10_LB_SOPQ23_ERROR_E5                                                              (0x1<<15) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_10_LB_SOPQ23_ERROR_E5_SHIFT                                                        15
+#define NIG_REG_INT_MASK_10_E5                                                                               0x5000f4UL //Access:RW   DataWidth:0x10   // Multi Field Register.
+  #define NIG_REG_INT_MASK_10_TX_SOPQ16_ERROR_E5                                                             (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_10.TX_SOPQ16_ERROR .
+  #define NIG_REG_INT_MASK_10_TX_SOPQ16_ERROR_E5_SHIFT                                                       0
+  #define NIG_REG_INT_MASK_10_TX_SOPQ17_ERROR_E5                                                             (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_10.TX_SOPQ17_ERROR .
+  #define NIG_REG_INT_MASK_10_TX_SOPQ17_ERROR_E5_SHIFT                                                       1
+  #define NIG_REG_INT_MASK_10_TX_SOPQ18_ERROR_E5                                                             (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_10.TX_SOPQ18_ERROR .
+  #define NIG_REG_INT_MASK_10_TX_SOPQ18_ERROR_E5_SHIFT                                                       2
+  #define NIG_REG_INT_MASK_10_TX_SOPQ19_ERROR_E5                                                             (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_10.TX_SOPQ19_ERROR .
+  #define NIG_REG_INT_MASK_10_TX_SOPQ19_ERROR_E5_SHIFT                                                       3
+  #define NIG_REG_INT_MASK_10_TX_SOPQ20_ERROR_E5                                                             (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_10.TX_SOPQ20_ERROR .
+  #define NIG_REG_INT_MASK_10_TX_SOPQ20_ERROR_E5_SHIFT                                                       4
+  #define NIG_REG_INT_MASK_10_TX_SOPQ21_ERROR_E5                                                             (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_10.TX_SOPQ21_ERROR .
+  #define NIG_REG_INT_MASK_10_TX_SOPQ21_ERROR_E5_SHIFT                                                       5
+  #define NIG_REG_INT_MASK_10_TX_SOPQ22_ERROR_E5                                                             (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_10.TX_SOPQ22_ERROR .
+  #define NIG_REG_INT_MASK_10_TX_SOPQ22_ERROR_E5_SHIFT                                                       6
+  #define NIG_REG_INT_MASK_10_TX_SOPQ23_ERROR_E5                                                             (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_10.TX_SOPQ23_ERROR .
+  #define NIG_REG_INT_MASK_10_TX_SOPQ23_ERROR_E5_SHIFT                                                       7
+  #define NIG_REG_INT_MASK_10_LB_SOPQ16_ERROR_E5                                                             (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_10.LB_SOPQ16_ERROR .
+  #define NIG_REG_INT_MASK_10_LB_SOPQ16_ERROR_E5_SHIFT                                                       8
+  #define NIG_REG_INT_MASK_10_LB_SOPQ17_ERROR_E5                                                             (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_10.LB_SOPQ17_ERROR .
+  #define NIG_REG_INT_MASK_10_LB_SOPQ17_ERROR_E5_SHIFT                                                       9
+  #define NIG_REG_INT_MASK_10_LB_SOPQ18_ERROR_E5                                                             (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_10.LB_SOPQ18_ERROR .
+  #define NIG_REG_INT_MASK_10_LB_SOPQ18_ERROR_E5_SHIFT                                                       10
+  #define NIG_REG_INT_MASK_10_LB_SOPQ19_ERROR_E5                                                             (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_10.LB_SOPQ19_ERROR .
+  #define NIG_REG_INT_MASK_10_LB_SOPQ19_ERROR_E5_SHIFT                                                       11
+  #define NIG_REG_INT_MASK_10_LB_SOPQ20_ERROR_E5                                                             (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_10.LB_SOPQ20_ERROR .
+  #define NIG_REG_INT_MASK_10_LB_SOPQ20_ERROR_E5_SHIFT                                                       12
+  #define NIG_REG_INT_MASK_10_LB_SOPQ21_ERROR_E5                                                             (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_10.LB_SOPQ21_ERROR .
+  #define NIG_REG_INT_MASK_10_LB_SOPQ21_ERROR_E5_SHIFT                                                       13
+  #define NIG_REG_INT_MASK_10_LB_SOPQ22_ERROR_E5                                                             (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_10.LB_SOPQ22_ERROR .
+  #define NIG_REG_INT_MASK_10_LB_SOPQ22_ERROR_E5_SHIFT                                                       14
+  #define NIG_REG_INT_MASK_10_LB_SOPQ23_ERROR_E5                                                             (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_10.LB_SOPQ23_ERROR .
+  #define NIG_REG_INT_MASK_10_LB_SOPQ23_ERROR_E5_SHIFT                                                       15
+#define NIG_REG_INT_STS_WR_10_E5                                                                             0x5000f8UL //Access:WR   DataWidth:0x10   // Multi Field Register.
+  #define NIG_REG_INT_STS_WR_10_TX_SOPQ16_ERROR_E5                                                           (0x1<<0) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_WR_10_TX_SOPQ16_ERROR_E5_SHIFT                                                     0
+  #define NIG_REG_INT_STS_WR_10_TX_SOPQ17_ERROR_E5                                                           (0x1<<1) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_WR_10_TX_SOPQ17_ERROR_E5_SHIFT                                                     1
+  #define NIG_REG_INT_STS_WR_10_TX_SOPQ18_ERROR_E5                                                           (0x1<<2) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_WR_10_TX_SOPQ18_ERROR_E5_SHIFT                                                     2
+  #define NIG_REG_INT_STS_WR_10_TX_SOPQ19_ERROR_E5                                                           (0x1<<3) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_WR_10_TX_SOPQ19_ERROR_E5_SHIFT                                                     3
+  #define NIG_REG_INT_STS_WR_10_TX_SOPQ20_ERROR_E5                                                           (0x1<<4) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_WR_10_TX_SOPQ20_ERROR_E5_SHIFT                                                     4
+  #define NIG_REG_INT_STS_WR_10_TX_SOPQ21_ERROR_E5                                                           (0x1<<5) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_WR_10_TX_SOPQ21_ERROR_E5_SHIFT                                                     5
+  #define NIG_REG_INT_STS_WR_10_TX_SOPQ22_ERROR_E5                                                           (0x1<<6) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_WR_10_TX_SOPQ22_ERROR_E5_SHIFT                                                     6
+  #define NIG_REG_INT_STS_WR_10_TX_SOPQ23_ERROR_E5                                                           (0x1<<7) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_WR_10_TX_SOPQ23_ERROR_E5_SHIFT                                                     7
+  #define NIG_REG_INT_STS_WR_10_LB_SOPQ16_ERROR_E5                                                           (0x1<<8) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_WR_10_LB_SOPQ16_ERROR_E5_SHIFT                                                     8
+  #define NIG_REG_INT_STS_WR_10_LB_SOPQ17_ERROR_E5                                                           (0x1<<9) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_WR_10_LB_SOPQ17_ERROR_E5_SHIFT                                                     9
+  #define NIG_REG_INT_STS_WR_10_LB_SOPQ18_ERROR_E5                                                           (0x1<<10) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_WR_10_LB_SOPQ18_ERROR_E5_SHIFT                                                     10
+  #define NIG_REG_INT_STS_WR_10_LB_SOPQ19_ERROR_E5                                                           (0x1<<11) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_WR_10_LB_SOPQ19_ERROR_E5_SHIFT                                                     11
+  #define NIG_REG_INT_STS_WR_10_LB_SOPQ20_ERROR_E5                                                           (0x1<<12) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_WR_10_LB_SOPQ20_ERROR_E5_SHIFT                                                     12
+  #define NIG_REG_INT_STS_WR_10_LB_SOPQ21_ERROR_E5                                                           (0x1<<13) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_WR_10_LB_SOPQ21_ERROR_E5_SHIFT                                                     13
+  #define NIG_REG_INT_STS_WR_10_LB_SOPQ22_ERROR_E5                                                           (0x1<<14) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_WR_10_LB_SOPQ22_ERROR_E5_SHIFT                                                     14
+  #define NIG_REG_INT_STS_WR_10_LB_SOPQ23_ERROR_E5                                                           (0x1<<15) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_WR_10_LB_SOPQ23_ERROR_E5_SHIFT                                                     15
+#define NIG_REG_INT_STS_CLR_10_E5                                                                            0x5000fcUL //Access:RC   DataWidth:0x10   // Multi Field Register.
+  #define NIG_REG_INT_STS_CLR_10_TX_SOPQ16_ERROR_E5                                                          (0x1<<0) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_CLR_10_TX_SOPQ16_ERROR_E5_SHIFT                                                    0
+  #define NIG_REG_INT_STS_CLR_10_TX_SOPQ17_ERROR_E5                                                          (0x1<<1) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_CLR_10_TX_SOPQ17_ERROR_E5_SHIFT                                                    1
+  #define NIG_REG_INT_STS_CLR_10_TX_SOPQ18_ERROR_E5                                                          (0x1<<2) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_CLR_10_TX_SOPQ18_ERROR_E5_SHIFT                                                    2
+  #define NIG_REG_INT_STS_CLR_10_TX_SOPQ19_ERROR_E5                                                          (0x1<<3) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_CLR_10_TX_SOPQ19_ERROR_E5_SHIFT                                                    3
+  #define NIG_REG_INT_STS_CLR_10_TX_SOPQ20_ERROR_E5                                                          (0x1<<4) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_CLR_10_TX_SOPQ20_ERROR_E5_SHIFT                                                    4
+  #define NIG_REG_INT_STS_CLR_10_TX_SOPQ21_ERROR_E5                                                          (0x1<<5) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_CLR_10_TX_SOPQ21_ERROR_E5_SHIFT                                                    5
+  #define NIG_REG_INT_STS_CLR_10_TX_SOPQ22_ERROR_E5                                                          (0x1<<6) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_CLR_10_TX_SOPQ22_ERROR_E5_SHIFT                                                    6
+  #define NIG_REG_INT_STS_CLR_10_TX_SOPQ23_ERROR_E5                                                          (0x1<<7) // Error in the TX SOPQ.
+  #define NIG_REG_INT_STS_CLR_10_TX_SOPQ23_ERROR_E5_SHIFT                                                    7
+  #define NIG_REG_INT_STS_CLR_10_LB_SOPQ16_ERROR_E5                                                          (0x1<<8) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_CLR_10_LB_SOPQ16_ERROR_E5_SHIFT                                                    8
+  #define NIG_REG_INT_STS_CLR_10_LB_SOPQ17_ERROR_E5                                                          (0x1<<9) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_CLR_10_LB_SOPQ17_ERROR_E5_SHIFT                                                    9
+  #define NIG_REG_INT_STS_CLR_10_LB_SOPQ18_ERROR_E5                                                          (0x1<<10) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_CLR_10_LB_SOPQ18_ERROR_E5_SHIFT                                                    10
+  #define NIG_REG_INT_STS_CLR_10_LB_SOPQ19_ERROR_E5                                                          (0x1<<11) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_CLR_10_LB_SOPQ19_ERROR_E5_SHIFT                                                    11
+  #define NIG_REG_INT_STS_CLR_10_LB_SOPQ20_ERROR_E5                                                          (0x1<<12) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_CLR_10_LB_SOPQ20_ERROR_E5_SHIFT                                                    12
+  #define NIG_REG_INT_STS_CLR_10_LB_SOPQ21_ERROR_E5                                                          (0x1<<13) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_CLR_10_LB_SOPQ21_ERROR_E5_SHIFT                                                    13
+  #define NIG_REG_INT_STS_CLR_10_LB_SOPQ22_ERROR_E5                                                          (0x1<<14) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_CLR_10_LB_SOPQ22_ERROR_E5_SHIFT                                                    14
+  #define NIG_REG_INT_STS_CLR_10_LB_SOPQ23_ERROR_E5                                                          (0x1<<15) // Error in the LB SOPQ.
+  #define NIG_REG_INT_STS_CLR_10_LB_SOPQ23_ERROR_E5_SHIFT                                                    15
+#define NIG_REG_PRTY_MASK_H_0_BB_K2                                                                          0x500204UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define NIG_REG_PRTY_MASK_H_0_MEM107_I_MEM_PRTY_K2                                                         (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM107_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM107_I_MEM_PRTY_K2_SHIFT                                                   0
+  #define NIG_REG_PRTY_MASK_H_0_MEM103_I_MEM_PRTY_K2                                                         (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM103_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM103_I_MEM_PRTY_K2_SHIFT                                                   1
+  #define NIG_REG_PRTY_MASK_H_0_MEM104_I_MEM_PRTY_K2                                                         (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM104_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM104_I_MEM_PRTY_K2_SHIFT                                                   2
+  #define NIG_REG_PRTY_MASK_H_0_MEM105_I_MEM_PRTY_BB                                                         (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM105_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM105_I_MEM_PRTY_BB_SHIFT                                                   2
+  #define NIG_REG_PRTY_MASK_H_0_MEM105_I_MEM_PRTY_K2                                                         (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM105_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM105_I_MEM_PRTY_K2_SHIFT                                                   3
+  #define NIG_REG_PRTY_MASK_H_0_MEM106_I_MEM_PRTY_BB                                                         (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM106_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM106_I_MEM_PRTY_BB_SHIFT                                                   3
+  #define NIG_REG_PRTY_MASK_H_0_MEM106_I_MEM_PRTY_K2                                                         (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM106_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM106_I_MEM_PRTY_K2_SHIFT                                                   4
+  #define NIG_REG_PRTY_MASK_H_0_MEM072_I_MEM_PRTY_K2                                                         (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM072_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM072_I_MEM_PRTY_K2_SHIFT                                                   5
+  #define NIG_REG_PRTY_MASK_H_0_MEM071_I_MEM_PRTY_K2                                                         (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM071_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM071_I_MEM_PRTY_K2_SHIFT                                                   6
+  #define NIG_REG_PRTY_MASK_H_0_MEM074_I_MEM_PRTY_K2                                                         (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM074_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM074_I_MEM_PRTY_K2_SHIFT                                                   7
+  #define NIG_REG_PRTY_MASK_H_0_MEM073_I_MEM_PRTY_BB                                                         (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM073_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM073_I_MEM_PRTY_BB_SHIFT                                                   26
+  #define NIG_REG_PRTY_MASK_H_0_MEM073_I_MEM_PRTY_K2                                                         (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM073_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM073_I_MEM_PRTY_K2_SHIFT                                                   8
+  #define NIG_REG_PRTY_MASK_H_0_MEM076_I_MEM_PRTY_K2                                                         (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM076_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM076_I_MEM_PRTY_K2_SHIFT                                                   9
+  #define NIG_REG_PRTY_MASK_H_0_MEM075_I_MEM_PRTY_K2                                                         (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM075_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM075_I_MEM_PRTY_K2_SHIFT                                                   10
+  #define NIG_REG_PRTY_MASK_H_0_MEM078_I_MEM_PRTY_K2                                                         (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM078_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM078_I_MEM_PRTY_K2_SHIFT                                                   11
+  #define NIG_REG_PRTY_MASK_H_0_MEM077_I_MEM_PRTY_K2                                                         (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM077_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM077_I_MEM_PRTY_K2_SHIFT                                                   12
+  #define NIG_REG_PRTY_MASK_H_0_MEM055_I_MEM_PRTY_K2                                                         (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM055_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM055_I_MEM_PRTY_K2_SHIFT                                                   13
+  #define NIG_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY_K2                                                         (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM062_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY_K2_SHIFT                                                   14
+  #define NIG_REG_PRTY_MASK_H_0_MEM063_I_MEM_PRTY_K2                                                         (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM063_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM063_I_MEM_PRTY_K2_SHIFT                                                   15
+  #define NIG_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY_K2                                                         (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM064_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY_K2_SHIFT                                                   16
+  #define NIG_REG_PRTY_MASK_H_0_MEM065_I_MEM_PRTY_K2                                                         (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM065_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM065_I_MEM_PRTY_K2_SHIFT                                                   17
+  #define NIG_REG_PRTY_MASK_H_0_MEM066_I_MEM_PRTY_K2                                                         (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM066_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM066_I_MEM_PRTY_K2_SHIFT                                                   18
+  #define NIG_REG_PRTY_MASK_H_0_MEM067_I_MEM_PRTY_K2                                                         (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM067_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM067_I_MEM_PRTY_K2_SHIFT                                                   19
+  #define NIG_REG_PRTY_MASK_H_0_MEM068_I_MEM_PRTY_K2                                                         (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM068_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM068_I_MEM_PRTY_K2_SHIFT                                                   20
+  #define NIG_REG_PRTY_MASK_H_0_MEM069_I_MEM_PRTY_K2                                                         (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM069_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM069_I_MEM_PRTY_K2_SHIFT                                                   21
+  #define NIG_REG_PRTY_MASK_H_0_MEM070_I_MEM_PRTY_K2                                                         (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM070_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM070_I_MEM_PRTY_K2_SHIFT                                                   22
+  #define NIG_REG_PRTY_MASK_H_0_MEM056_I_MEM_PRTY_K2                                                         (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM056_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM056_I_MEM_PRTY_K2_SHIFT                                                   23
+  #define NIG_REG_PRTY_MASK_H_0_MEM057_I_MEM_PRTY_K2                                                         (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM057_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM057_I_MEM_PRTY_K2_SHIFT                                                   24
+  #define NIG_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY_K2                                                         (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM058_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY_K2_SHIFT                                                   25
+  #define NIG_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_K2                                                         (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM059_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_K2_SHIFT                                                   26
+  #define NIG_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_K2                                                         (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM060_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_K2_SHIFT                                                   27
+  #define NIG_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_K2                                                         (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM061_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_K2_SHIFT                                                   28
+  #define NIG_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_K2                                                         (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_K2_SHIFT                                                   29
+  #define NIG_REG_PRTY_MASK_H_0_MEM046_I_MEM_PRTY_K2                                                         (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM046_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM046_I_MEM_PRTY_K2_SHIFT                                                   30
+  #define NIG_REG_PRTY_MASK_H_0_MEM051_I_MEM_PRTY_BB                                                         (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM051_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM051_I_MEM_PRTY_BB_SHIFT                                                   0
+  #define NIG_REG_PRTY_MASK_H_0_MEM052_I_MEM_PRTY_BB                                                         (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM052_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM052_I_MEM_PRTY_BB_SHIFT                                                   1
+  #define NIG_REG_PRTY_MASK_H_0_MEM090_I_MEM_PRTY_BB                                                         (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM090_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM090_I_MEM_PRTY_BB_SHIFT                                                   4
+  #define NIG_REG_PRTY_MASK_H_0_MEM089_I_MEM_PRTY_BB                                                         (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM089_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM089_I_MEM_PRTY_BB_SHIFT                                                   5
+  #define NIG_REG_PRTY_MASK_H_0_MEM092_I_MEM_PRTY_BB                                                         (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM092_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM092_I_MEM_PRTY_BB_SHIFT                                                   6
+  #define NIG_REG_PRTY_MASK_H_0_MEM091_I_MEM_PRTY_BB                                                         (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM091_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM091_I_MEM_PRTY_BB_SHIFT                                                   7
+  #define NIG_REG_PRTY_MASK_H_0_MEM109_I_MEM_PRTY_BB                                                         (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM109_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM109_I_MEM_PRTY_BB_SHIFT                                                   8
+  #define NIG_REG_PRTY_MASK_H_0_MEM110_I_MEM_PRTY_BB                                                         (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM110_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM110_I_MEM_PRTY_BB_SHIFT                                                   9
+  #define NIG_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB                                                         (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_SHIFT                                                   10
+  #define NIG_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB                                                         (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_SHIFT                                                   11
+  #define NIG_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB                                                         (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_SHIFT                                                   12
+  #define NIG_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB                                                         (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_SHIFT                                                   13
+  #define NIG_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB                                                         (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_SHIFT                                                   14
+  #define NIG_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB                                                         (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_SHIFT                                                   15
+  #define NIG_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB                                                         (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_SHIFT                                                   16
+  #define NIG_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB                                                         (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_SHIFT                                                   17
+  #define NIG_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB                                                         (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_SHIFT                                                   18
+  #define NIG_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB                                                         (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_SHIFT                                                   19
+  #define NIG_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB                                                         (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_SHIFT                                                   20
+  #define NIG_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB                                                         (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_SHIFT                                                   21
+  #define NIG_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB                                                         (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_SHIFT                                                   22
+  #define NIG_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB                                                         (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_SHIFT                                                   23
+  #define NIG_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB                                                         (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_SHIFT                                                   24
+  #define NIG_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB                                                         (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_SHIFT                                                   25
+  #define NIG_REG_PRTY_MASK_H_0_MEM080_I_MEM_PRTY_BB                                                         (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM080_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM080_I_MEM_PRTY_BB_SHIFT                                                   27
+  #define NIG_REG_PRTY_MASK_H_0_MEM081_I_MEM_PRTY_BB                                                         (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM081_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM081_I_MEM_PRTY_BB_SHIFT                                                   28
+  #define NIG_REG_PRTY_MASK_H_0_MEM082_I_MEM_PRTY_BB                                                         (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM082_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM082_I_MEM_PRTY_BB_SHIFT                                                   29
+  #define NIG_REG_PRTY_MASK_H_0_MEM083_I_MEM_PRTY_BB                                                         (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM083_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_0_MEM083_I_MEM_PRTY_BB_SHIFT                                                   30
+#define NIG_REG_PRTY_MASK_H_1_BB_K2                                                                          0x500214UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define NIG_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_K2                                                         (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM047_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_K2_SHIFT                                                   0
+  #define NIG_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_K2                                                         (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM048_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_K2_SHIFT                                                   1
+  #define NIG_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_K2                                                         (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM049_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_K2_SHIFT                                                   2
+  #define NIG_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_K2                                                         (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_K2_SHIFT                                                   3
+  #define NIG_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_K2                                                         (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM051_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_K2_SHIFT                                                   4
+  #define NIG_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_K2                                                         (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_K2_SHIFT                                                   5
+  #define NIG_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_K2                                                         (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM053_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_K2_SHIFT                                                   6
+  #define NIG_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY_K2                                                         (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM054_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY_K2_SHIFT                                                   7
+  #define NIG_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_K2                                                         (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_K2_SHIFT                                                   8
+  #define NIG_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_K2                                                         (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM037_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_K2_SHIFT                                                   9
+  #define NIG_REG_PRTY_MASK_H_1_MEM038_I_MEM_PRTY_K2                                                         (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM038_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM038_I_MEM_PRTY_K2_SHIFT                                                   10
+  #define NIG_REG_PRTY_MASK_H_1_MEM039_I_MEM_PRTY_K2                                                         (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM039_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM039_I_MEM_PRTY_K2_SHIFT                                                   11
+  #define NIG_REG_PRTY_MASK_H_1_MEM040_I_MEM_PRTY_K2                                                         (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM040_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM040_I_MEM_PRTY_K2_SHIFT                                                   12
+  #define NIG_REG_PRTY_MASK_H_1_MEM041_I_MEM_PRTY_K2                                                         (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM041_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM041_I_MEM_PRTY_K2_SHIFT                                                   13
+  #define NIG_REG_PRTY_MASK_H_1_MEM042_I_MEM_PRTY_K2                                                         (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM042_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM042_I_MEM_PRTY_K2_SHIFT                                                   14
+  #define NIG_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_K2                                                         (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM043_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_K2_SHIFT                                                   15
+  #define NIG_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_K2                                                         (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM044_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_K2_SHIFT                                                   16
+  #define NIG_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY_K2                                                         (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM045_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY_K2_SHIFT                                                   17
+  #define NIG_REG_PRTY_MASK_H_1_MEM091_I_MEM_PRTY_K2                                                         (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM091_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM091_I_MEM_PRTY_K2_SHIFT                                                   18
+  #define NIG_REG_PRTY_MASK_H_1_MEM092_I_MEM_PRTY_K2                                                         (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM092_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM092_I_MEM_PRTY_K2_SHIFT                                                   19
+  #define NIG_REG_PRTY_MASK_H_1_MEM093_I_MEM_PRTY_K2                                                         (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM093_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM093_I_MEM_PRTY_K2_SHIFT                                                   20
+  #define NIG_REG_PRTY_MASK_H_1_MEM094_I_MEM_PRTY_K2                                                         (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM094_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM094_I_MEM_PRTY_K2_SHIFT                                                   21
+  #define NIG_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_K2                                                         (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM027_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_K2_SHIFT                                                   22
+  #define NIG_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_K2                                                         (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM028_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_K2_SHIFT                                                   23
+  #define NIG_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_K2                                                         (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM029_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_K2_SHIFT                                                   24
+  #define NIG_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY_K2                                                         (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM030_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY_K2_SHIFT                                                   25
+  #define NIG_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_K2                                                         (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_K2_SHIFT                                                   26
+  #define NIG_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_K2                                                         (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_K2_SHIFT                                                   27
+  #define NIG_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_K2                                                         (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_K2_SHIFT                                                   28
+  #define NIG_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_K2                                                         (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM018_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_K2_SHIFT                                                   29
+  #define NIG_REG_PRTY_MASK_H_1_MEM095_I_MEM_PRTY_K2                                                         (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM095_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM095_I_MEM_PRTY_K2_SHIFT                                                   30
+  #define NIG_REG_PRTY_MASK_H_1_MEM084_I_MEM_PRTY_BB                                                         (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM084_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM084_I_MEM_PRTY_BB_SHIFT                                                   0
+  #define NIG_REG_PRTY_MASK_H_1_MEM085_I_MEM_PRTY_BB                                                         (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM085_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM085_I_MEM_PRTY_BB_SHIFT                                                   1
+  #define NIG_REG_PRTY_MASK_H_1_MEM086_I_MEM_PRTY_BB                                                         (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM086_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM086_I_MEM_PRTY_BB_SHIFT                                                   2
+  #define NIG_REG_PRTY_MASK_H_1_MEM087_I_MEM_PRTY_BB                                                         (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM087_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM087_I_MEM_PRTY_BB_SHIFT                                                   3
+  #define NIG_REG_PRTY_MASK_H_1_MEM088_I_MEM_PRTY_BB                                                         (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM088_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM088_I_MEM_PRTY_BB_SHIFT                                                   4
+  #define NIG_REG_PRTY_MASK_H_1_MEM074_I_MEM_PRTY_BB                                                         (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM074_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM074_I_MEM_PRTY_BB_SHIFT                                                   5
+  #define NIG_REG_PRTY_MASK_H_1_MEM075_I_MEM_PRTY_BB                                                         (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM075_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM075_I_MEM_PRTY_BB_SHIFT                                                   6
+  #define NIG_REG_PRTY_MASK_H_1_MEM076_I_MEM_PRTY_BB                                                         (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM076_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM076_I_MEM_PRTY_BB_SHIFT                                                   7
+  #define NIG_REG_PRTY_MASK_H_1_MEM077_I_MEM_PRTY_BB                                                         (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM077_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM077_I_MEM_PRTY_BB_SHIFT                                                   8
+  #define NIG_REG_PRTY_MASK_H_1_MEM078_I_MEM_PRTY_BB                                                         (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM078_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM078_I_MEM_PRTY_BB_SHIFT                                                   9
+  #define NIG_REG_PRTY_MASK_H_1_MEM079_I_MEM_PRTY_BB                                                         (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM079_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM079_I_MEM_PRTY_BB_SHIFT                                                   10
+  #define NIG_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_BB                                                         (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM055_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_BB_SHIFT                                                   11
+  #define NIG_REG_PRTY_MASK_H_1_MEM064_I_MEM_PRTY_BB                                                         (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM064_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM064_I_MEM_PRTY_BB_SHIFT                                                   12
+  #define NIG_REG_PRTY_MASK_H_1_MEM065_I_MEM_PRTY_BB                                                         (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM065_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM065_I_MEM_PRTY_BB_SHIFT                                                   13
+  #define NIG_REG_PRTY_MASK_H_1_MEM066_I_MEM_PRTY_BB                                                         (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM066_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM066_I_MEM_PRTY_BB_SHIFT                                                   14
+  #define NIG_REG_PRTY_MASK_H_1_MEM067_I_MEM_PRTY_BB                                                         (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM067_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM067_I_MEM_PRTY_BB_SHIFT                                                   15
+  #define NIG_REG_PRTY_MASK_H_1_MEM068_I_MEM_PRTY_BB                                                         (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM068_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM068_I_MEM_PRTY_BB_SHIFT                                                   16
+  #define NIG_REG_PRTY_MASK_H_1_MEM069_I_MEM_PRTY_BB                                                         (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM069_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM069_I_MEM_PRTY_BB_SHIFT                                                   17
+  #define NIG_REG_PRTY_MASK_H_1_MEM070_I_MEM_PRTY_BB                                                         (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM070_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM070_I_MEM_PRTY_BB_SHIFT                                                   18
+  #define NIG_REG_PRTY_MASK_H_1_MEM071_I_MEM_PRTY_BB                                                         (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM071_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM071_I_MEM_PRTY_BB_SHIFT                                                   19
+  #define NIG_REG_PRTY_MASK_H_1_MEM072_I_MEM_PRTY_BB                                                         (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM072_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM072_I_MEM_PRTY_BB_SHIFT                                                   20
+  #define NIG_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY_BB                                                         (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM056_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY_BB_SHIFT                                                   21
+  #define NIG_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_BB                                                         (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM057_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_BB_SHIFT                                                   22
+  #define NIG_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_BB                                                         (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM058_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_BB_SHIFT                                                   23
+  #define NIG_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY_BB                                                         (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM059_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY_BB_SHIFT                                                   24
+  #define NIG_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY_BB                                                         (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM060_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY_BB_SHIFT                                                   25
+  #define NIG_REG_PRTY_MASK_H_1_MEM061_I_MEM_PRTY_BB                                                         (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM061_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM061_I_MEM_PRTY_BB_SHIFT                                                   26
+  #define NIG_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY_BB                                                         (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM062_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY_BB_SHIFT                                                   27
+  #define NIG_REG_PRTY_MASK_H_1_MEM063_I_MEM_PRTY_BB                                                         (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM063_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM063_I_MEM_PRTY_BB_SHIFT                                                   28
+  #define NIG_REG_PRTY_MASK_H_1_MEM099_I_MEM_PRTY_BB                                                         (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM099_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM099_I_MEM_PRTY_BB_SHIFT                                                   29
+  #define NIG_REG_PRTY_MASK_H_1_MEM100_I_MEM_PRTY_BB                                                         (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM100_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_1_MEM100_I_MEM_PRTY_BB_SHIFT                                                   30
+#define NIG_REG_PRTY_MASK_H_2_BB_K2                                                                          0x500224UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define NIG_REG_PRTY_MASK_H_2_MEM096_I_MEM_PRTY_BB                                                         (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM096_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM096_I_MEM_PRTY_BB_SHIFT                                                   26
+  #define NIG_REG_PRTY_MASK_H_2_MEM096_I_MEM_PRTY_K2                                                         (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM096_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM096_I_MEM_PRTY_K2_SHIFT                                                   0
+  #define NIG_REG_PRTY_MASK_H_2_MEM097_I_MEM_PRTY_BB                                                         (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM097_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM097_I_MEM_PRTY_BB_SHIFT                                                   29
+  #define NIG_REG_PRTY_MASK_H_2_MEM097_I_MEM_PRTY_K2                                                         (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM097_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM097_I_MEM_PRTY_K2_SHIFT                                                   1
+  #define NIG_REG_PRTY_MASK_H_2_MEM098_I_MEM_PRTY_BB                                                         (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM098_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM098_I_MEM_PRTY_BB_SHIFT                                                   30
+  #define NIG_REG_PRTY_MASK_H_2_MEM098_I_MEM_PRTY_K2                                                         (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM098_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM098_I_MEM_PRTY_K2_SHIFT                                                   2
+  #define NIG_REG_PRTY_MASK_H_2_MEM031_I_MEM_PRTY_BB                                                         (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM031_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM031_I_MEM_PRTY_BB_SHIFT                                                   21
+  #define NIG_REG_PRTY_MASK_H_2_MEM031_I_MEM_PRTY_K2                                                         (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM031_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM031_I_MEM_PRTY_K2_SHIFT                                                   3
+  #define NIG_REG_PRTY_MASK_H_2_MEM032_I_MEM_PRTY_K2                                                         (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM032_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM032_I_MEM_PRTY_K2_SHIFT                                                   4
+  #define NIG_REG_PRTY_MASK_H_2_MEM033_I_MEM_PRTY_BB                                                         (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM033_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM033_I_MEM_PRTY_BB_SHIFT                                                   12
+  #define NIG_REG_PRTY_MASK_H_2_MEM033_I_MEM_PRTY_K2                                                         (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM033_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM033_I_MEM_PRTY_K2_SHIFT                                                   5
+  #define NIG_REG_PRTY_MASK_H_2_MEM034_I_MEM_PRTY_BB                                                         (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM034_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM034_I_MEM_PRTY_BB_SHIFT                                                   23
+  #define NIG_REG_PRTY_MASK_H_2_MEM034_I_MEM_PRTY_K2                                                         (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM034_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM034_I_MEM_PRTY_K2_SHIFT                                                   6
+  #define NIG_REG_PRTY_MASK_H_2_MEM019_I_MEM_PRTY_K2                                                         (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM019_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM019_I_MEM_PRTY_K2_SHIFT                                                   7
+  #define NIG_REG_PRTY_MASK_H_2_MEM020_I_MEM_PRTY_K2                                                         (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM020_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM020_I_MEM_PRTY_K2_SHIFT                                                   8
+  #define NIG_REG_PRTY_MASK_H_2_MEM021_I_MEM_PRTY_BB                                                         (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM021_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM021_I_MEM_PRTY_BB_SHIFT                                                   27
+  #define NIG_REG_PRTY_MASK_H_2_MEM021_I_MEM_PRTY_K2                                                         (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM021_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM021_I_MEM_PRTY_K2_SHIFT                                                   9
+  #define NIG_REG_PRTY_MASK_H_2_MEM022_I_MEM_PRTY_BB                                                         (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM022_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM022_I_MEM_PRTY_BB_SHIFT                                                   28
+  #define NIG_REG_PRTY_MASK_H_2_MEM022_I_MEM_PRTY_K2                                                         (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM022_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM022_I_MEM_PRTY_K2_SHIFT                                                   10
+  #define NIG_REG_PRTY_MASK_H_2_MEM099_I_MEM_PRTY_K2                                                         (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM099_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM099_I_MEM_PRTY_K2_SHIFT                                                   11
+  #define NIG_REG_PRTY_MASK_H_2_MEM100_I_MEM_PRTY_K2                                                         (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM100_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM100_I_MEM_PRTY_K2_SHIFT                                                   12
+  #define NIG_REG_PRTY_MASK_H_2_MEM101_I_MEM_PRTY_BB                                                         (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM101_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM101_I_MEM_PRTY_BB_SHIFT                                                   4
+  #define NIG_REG_PRTY_MASK_H_2_MEM101_I_MEM_PRTY_K2                                                         (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM101_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM101_I_MEM_PRTY_K2_SHIFT                                                   13
+  #define NIG_REG_PRTY_MASK_H_2_MEM102_I_MEM_PRTY_BB                                                         (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM102_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM102_I_MEM_PRTY_BB_SHIFT                                                   5
+  #define NIG_REG_PRTY_MASK_H_2_MEM102_I_MEM_PRTY_K2                                                         (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM102_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM102_I_MEM_PRTY_K2_SHIFT                                                   14
+  #define NIG_REG_PRTY_MASK_H_2_MEM023_I_MEM_PRTY_K2                                                         (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM023_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM023_I_MEM_PRTY_K2_SHIFT                                                   15
+  #define NIG_REG_PRTY_MASK_H_2_MEM024_I_MEM_PRTY_K2                                                         (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM024_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM024_I_MEM_PRTY_K2_SHIFT                                                   16
+  #define NIG_REG_PRTY_MASK_H_2_MEM025_I_MEM_PRTY_BB                                                         (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM025_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM025_I_MEM_PRTY_BB_SHIFT                                                   2
+  #define NIG_REG_PRTY_MASK_H_2_MEM025_I_MEM_PRTY_K2                                                         (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM025_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM025_I_MEM_PRTY_K2_SHIFT                                                   17
+  #define NIG_REG_PRTY_MASK_H_2_MEM026_I_MEM_PRTY_BB                                                         (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM026_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM026_I_MEM_PRTY_BB_SHIFT                                                   3
+  #define NIG_REG_PRTY_MASK_H_2_MEM026_I_MEM_PRTY_K2                                                         (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM026_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM026_I_MEM_PRTY_K2_SHIFT                                                   18
+  #define NIG_REG_PRTY_MASK_H_2_MEM083_I_MEM_PRTY_K2                                                         (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM083_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM083_I_MEM_PRTY_K2_SHIFT                                                   19
+  #define NIG_REG_PRTY_MASK_H_2_MEM084_I_MEM_PRTY_K2                                                         (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM084_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM084_I_MEM_PRTY_K2_SHIFT                                                   20
+  #define NIG_REG_PRTY_MASK_H_2_MEM085_I_MEM_PRTY_K2                                                         (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM085_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM085_I_MEM_PRTY_K2_SHIFT                                                   21
+  #define NIG_REG_PRTY_MASK_H_2_MEM086_I_MEM_PRTY_K2                                                         (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM086_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM086_I_MEM_PRTY_K2_SHIFT                                                   22
+  #define NIG_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_K2                                                         (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_K2_SHIFT                                                   23
+  #define NIG_REG_PRTY_MASK_H_2_MEM008_I_MEM_PRTY_K2                                                         (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM008_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM008_I_MEM_PRTY_K2_SHIFT                                                   24
+  #define NIG_REG_PRTY_MASK_H_2_MEM009_I_MEM_PRTY_K2                                                         (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM009_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM009_I_MEM_PRTY_K2_SHIFT                                                   25
+  #define NIG_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_K2                                                         (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_K2_SHIFT                                                   26
+  #define NIG_REG_PRTY_MASK_H_2_MEM087_I_MEM_PRTY_K2                                                         (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM087_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM087_I_MEM_PRTY_K2_SHIFT                                                   27
+  #define NIG_REG_PRTY_MASK_H_2_MEM088_I_MEM_PRTY_K2                                                         (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM088_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM088_I_MEM_PRTY_K2_SHIFT                                                   28
+  #define NIG_REG_PRTY_MASK_H_2_MEM089_I_MEM_PRTY_K2                                                         (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM089_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM089_I_MEM_PRTY_K2_SHIFT                                                   29
+  #define NIG_REG_PRTY_MASK_H_2_MEM090_I_MEM_PRTY_K2                                                         (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM090_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM090_I_MEM_PRTY_K2_SHIFT                                                   30
+  #define NIG_REG_PRTY_MASK_H_2_MEM045_I_MEM_PRTY_BB                                                         (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM045_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM045_I_MEM_PRTY_BB_SHIFT                                                   0
+  #define NIG_REG_PRTY_MASK_H_2_MEM046_I_MEM_PRTY_BB                                                         (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM046_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM046_I_MEM_PRTY_BB_SHIFT                                                   1
+  #define NIG_REG_PRTY_MASK_H_2_MEM107_I_MEM_PRTY_BB                                                         (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM107_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM107_I_MEM_PRTY_BB_SHIFT                                                   6
+  #define NIG_REG_PRTY_MASK_H_2_MEM047_I_MEM_PRTY_BB                                                         (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM047_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM047_I_MEM_PRTY_BB_SHIFT                                                   7
+  #define NIG_REG_PRTY_MASK_H_2_MEM048_I_MEM_PRTY_BB                                                         (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM048_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM048_I_MEM_PRTY_BB_SHIFT                                                   8
+  #define NIG_REG_PRTY_MASK_H_2_MEM053_I_MEM_PRTY_BB                                                         (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM053_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM053_I_MEM_PRTY_BB_SHIFT                                                   9
+  #define NIG_REG_PRTY_MASK_H_2_MEM027_I_MEM_PRTY_BB                                                         (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM027_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM027_I_MEM_PRTY_BB_SHIFT                                                   10
+  #define NIG_REG_PRTY_MASK_H_2_MEM028_I_MEM_PRTY_BB                                                         (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM028_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM028_I_MEM_PRTY_BB_SHIFT                                                   11
+  #define NIG_REG_PRTY_MASK_H_2_MEM103_I_MEM_PRTY_BB                                                         (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM103_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM103_I_MEM_PRTY_BB_SHIFT                                                   13
+  #define NIG_REG_PRTY_MASK_H_2_MEM104_I_MEM_PRTY_BB                                                         (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM104_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM104_I_MEM_PRTY_BB_SHIFT                                                   14
+  #define NIG_REG_PRTY_MASK_H_2_MEM108_I_MEM_PRTY_BB                                                         (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM108_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM108_I_MEM_PRTY_BB_SHIFT                                                   15
+  #define NIG_REG_PRTY_MASK_H_2_MEM049_I_MEM_PRTY_BB                                                         (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM049_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM049_I_MEM_PRTY_BB_SHIFT                                                   16
+  #define NIG_REG_PRTY_MASK_H_2_MEM050_I_MEM_PRTY_BB                                                         (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM050_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM050_I_MEM_PRTY_BB_SHIFT                                                   17
+  #define NIG_REG_PRTY_MASK_H_2_MEM054_I_MEM_PRTY_BB                                                         (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM054_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM054_I_MEM_PRTY_BB_SHIFT                                                   18
+  #define NIG_REG_PRTY_MASK_H_2_MEM029_I_MEM_PRTY_BB                                                         (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM029_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM029_I_MEM_PRTY_BB_SHIFT                                                   19
+  #define NIG_REG_PRTY_MASK_H_2_MEM030_I_MEM_PRTY_BB                                                         (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM030_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM030_I_MEM_PRTY_BB_SHIFT                                                   20
+  #define NIG_REG_PRTY_MASK_H_2_MEM031_EXT_I_MEM_PRTY_BB                                                     (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM031_EXT_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM031_EXT_I_MEM_PRTY_BB_SHIFT                                               22
+  #define NIG_REG_PRTY_MASK_H_2_MEM034_EXT_I_MEM_PRTY_BB                                                     (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM034_EXT_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM034_EXT_I_MEM_PRTY_BB_SHIFT                                               24
+  #define NIG_REG_PRTY_MASK_H_2_MEM095_I_MEM_PRTY_BB                                                         (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM095_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_2_MEM095_I_MEM_PRTY_BB_SHIFT                                                   25
+#define NIG_REG_PRTY_MASK_H_3_BB_K2                                                                          0x500234UL //Access:RW   DataWidth:0xe    // Multi Field Register.
+  #define NIG_REG_PRTY_MASK_H_3_MEM011_I_MEM_PRTY_K2                                                         (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM011_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM011_I_MEM_PRTY_K2_SHIFT                                                   0
+  #define NIG_REG_PRTY_MASK_H_3_MEM012_I_MEM_PRTY_K2                                                         (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM012_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM012_I_MEM_PRTY_K2_SHIFT                                                   1
+  #define NIG_REG_PRTY_MASK_H_3_MEM013_I_MEM_PRTY_K2                                                         (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM013_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM013_I_MEM_PRTY_K2_SHIFT                                                   2
+  #define NIG_REG_PRTY_MASK_H_3_MEM014_I_MEM_PRTY_K2                                                         (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM014_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM014_I_MEM_PRTY_K2_SHIFT                                                   3
+  #define NIG_REG_PRTY_MASK_H_3_MEM001_I_MEM_PRTY_K2                                                         (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM001_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM001_I_MEM_PRTY_K2_SHIFT                                                   4
+  #define NIG_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_K2                                                         (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM002_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_K2_SHIFT                                                   5
+  #define NIG_REG_PRTY_MASK_H_3_MEM079_I_MEM_PRTY_K2                                                         (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM079_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM079_I_MEM_PRTY_K2_SHIFT                                                   6
+  #define NIG_REG_PRTY_MASK_H_3_MEM080_I_MEM_PRTY_K2                                                         (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM080_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM080_I_MEM_PRTY_K2_SHIFT                                                   7
+  #define NIG_REG_PRTY_MASK_H_3_MEM081_I_MEM_PRTY_K2                                                         (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM081_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM081_I_MEM_PRTY_K2_SHIFT                                                   8
+  #define NIG_REG_PRTY_MASK_H_3_MEM082_I_MEM_PRTY_K2                                                         (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM082_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM082_I_MEM_PRTY_K2_SHIFT                                                   9
+  #define NIG_REG_PRTY_MASK_H_3_MEM003_I_MEM_PRTY_K2                                                         (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM003_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM003_I_MEM_PRTY_K2_SHIFT                                                   10
+  #define NIG_REG_PRTY_MASK_H_3_MEM004_I_MEM_PRTY_K2                                                         (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM004_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM004_I_MEM_PRTY_K2_SHIFT                                                   11
+  #define NIG_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_K2                                                         (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_K2_SHIFT                                                   12
+  #define NIG_REG_PRTY_MASK_H_3_MEM006_I_MEM_PRTY_K2                                                         (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM006_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM006_I_MEM_PRTY_K2_SHIFT                                                   13
+  #define NIG_REG_PRTY_MASK_H_3_MEM023_I_MEM_PRTY_BB                                                         (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM023_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM023_I_MEM_PRTY_BB_SHIFT                                                   0
+  #define NIG_REG_PRTY_MASK_H_3_MEM024_I_MEM_PRTY_BB                                                         (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM024_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM024_I_MEM_PRTY_BB_SHIFT                                                   1
+  #define NIG_REG_PRTY_MASK_H_3_MEM017_I_MEM_PRTY_BB                                                         (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM017_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM017_I_MEM_PRTY_BB_SHIFT                                                   2
+  #define NIG_REG_PRTY_MASK_H_3_MEM018_I_MEM_PRTY_BB                                                         (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM018_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM018_I_MEM_PRTY_BB_SHIFT                                                   3
+  #define NIG_REG_PRTY_MASK_H_3_MEM093_I_MEM_PRTY_BB                                                         (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM093_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM093_I_MEM_PRTY_BB_SHIFT                                                   4
+  #define NIG_REG_PRTY_MASK_H_3_MEM094_I_MEM_PRTY_BB                                                         (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM094_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM094_I_MEM_PRTY_BB_SHIFT                                                   5
+  #define NIG_REG_PRTY_MASK_H_3_MEM019_I_MEM_PRTY_BB                                                         (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM019_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM019_I_MEM_PRTY_BB_SHIFT                                                   6
+  #define NIG_REG_PRTY_MASK_H_3_MEM020_I_MEM_PRTY_BB                                                         (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM020_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM020_I_MEM_PRTY_BB_SHIFT                                                   7
+  #define NIG_REG_PRTY_MASK_H_3_MEM040_I_MEM_PRTY_BB                                                         (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM040_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM040_I_MEM_PRTY_BB_SHIFT                                                   8
+  #define NIG_REG_PRTY_MASK_H_3_MEM036_I_MEM_PRTY_BB                                                         (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM036_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM036_I_MEM_PRTY_BB_SHIFT                                                   9
+  #define NIG_REG_PRTY_MASK_H_3_MEM039_I_MEM_PRTY_BB                                                         (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM039_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM039_I_MEM_PRTY_BB_SHIFT                                                   10
+  #define NIG_REG_PRTY_MASK_H_3_MEM041_I_MEM_PRTY_BB                                                         (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM041_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM041_I_MEM_PRTY_BB_SHIFT                                                   11
+  #define NIG_REG_PRTY_MASK_H_3_MEM042_I_MEM_PRTY_BB                                                         (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM042_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM042_I_MEM_PRTY_BB_SHIFT                                                   12
+  #define NIG_REG_PRTY_MASK_H_3_MEM043_I_MEM_PRTY_BB                                                         (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM043_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM043_I_MEM_PRTY_BB_SHIFT                                                   13
+  #define NIG_REG_PRTY_MASK_H_3_MEM044_I_MEM_PRTY_BB                                                         (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM044_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM044_I_MEM_PRTY_BB_SHIFT                                                   14
+  #define NIG_REG_PRTY_MASK_H_3_MEM038_I_MEM_PRTY_BB                                                         (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM038_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM038_I_MEM_PRTY_BB_SHIFT                                                   15
+  #define NIG_REG_PRTY_MASK_H_3_MEM037_I_MEM_PRTY_BB                                                         (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM037_I_MEM_PRTY .
+  #define NIG_REG_PRTY_MASK_H_3_MEM037_I_MEM_PRTY_BB_SHIFT                                                   16
+#define NIG_REG_MEM_ECC_EVENTS_BB_K2                                                                         0x500240UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define NIG_REG_CLOSE_GATE_DISABLE                                                                           0x500800UL //Access:RW   DataWidth:0x1    // Close-gate function disable bit:  0 - egress drain mode is enabled when close-gate input from MISC to NIG is active; 1 - close-gate input is ignored.  (The egress drain mode is for dropping all packets in the TX pipe without forwarding the packets to the TX MAC.).
+#define NIG_REG_TAG_ETHERTYPE_0                                                                              0x500804UL //Access:RW   DataWidth:0x10   // The Ethernet type value for L2 tag 0.
+#define NIG_REG_TAG_ETHERTYPE_1                                                                              0x500808UL //Access:RW   DataWidth:0x10   // The Ethernet type value for L2 tag 1.  The reset value is 9x8100 for inner VLAN.
+#define NIG_REG_TAG_ETHERTYPE_2                                                                              0x50080cUL //Access:RW   DataWidth:0x10   // The Ethernet type value for L2 tag 2.
+#define NIG_REG_TAG_ETHERTYPE_3                                                                              0x500810UL //Access:RW   DataWidth:0x10   // The Ethernet type value for L2 tag 3.
+#define NIG_REG_TAG_ETHERTYPE_4                                                                              0x500814UL //Access:RW   DataWidth:0x10   // The Ethernet type value for L2 tag 4.
+#define NIG_REG_TAG_ETHERTYPE_5                                                                              0x500818UL //Access:RW   DataWidth:0x10   // The Ethernet type value for L2 tag 5.
+#define NIG_REG_TAG_LEN_0                                                                                    0x50081cUL //Access:RW   DataWidth:0x3    // The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.
+#define NIG_REG_TAG_LEN_1                                                                                    0x500820UL //Access:RW   DataWidth:0x3    // The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.
+#define NIG_REG_TAG_LEN_2                                                                                    0x500824UL //Access:RW   DataWidth:0x3    // The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.
+#define NIG_REG_TAG_LEN_3                                                                                    0x500828UL //Access:RW   DataWidth:0x3    // The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.
+#define NIG_REG_TAG_LEN_4                                                                                    0x50082cUL //Access:RW   DataWidth:0x3    // The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.
+#define NIG_REG_TAG_LEN_5                                                                                    0x500830UL //Access:RW   DataWidth:0x3    // The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.
+#define NIG_REG_MNG_TO_MCP                                                                                   0x500834UL //Access:RW   DataWidth:0x1    // Direct all management traffic to BMB toward MCP.
+#define NIG_REG_FWD_PKT_TO_STORM                                                                             0x500838UL //Access:RW   DataWidth:0x1    // Select bit for choosing between XSTORM and YSTORM for forwarding RX packets.  0 is for XSTORM; 1 is for YSTORM. This configuration should be static during run-time.
+#define NIG_REG_STORM_CREDIT                                                                                 0x50083cUL //Access:RW   DataWidth:0x5    // Credit for the interface with XSEM and YSEM. Read this register to get the current credit count on the interface. This configuration should be static during run-time.
+#define NIG_REG_CM_HDR                                                                                       0x500840UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define NIG_REG_CM_HDR_EVENT_ID                                                                            (0xff<<0) // Event ID to be used in CM header for packets forwarded to the STORM through the X/YSEM interface.
+  #define NIG_REG_CM_HDR_EVENT_ID_SHIFT                                                                      0
+  #define NIG_REG_CM_HDR_T_BIT                                                                               (0x1<<8) // T-bit to be used in CM header for packets forwarded to the STORM through the X/YSEM interface.
+  #define NIG_REG_CM_HDR_T_BIT_SHIFT                                                                         8
+  #define NIG_REG_CM_HDR_DSTSTORMFLG                                                                         (0x1<<9) // DstStormFlg to be used in CM header for packets forwarded to the STORM through the X/YSEM interface.
+  #define NIG_REG_CM_HDR_DSTSTORMFLG_SHIFT                                                                   9
+  #define NIG_REG_CM_HDR_CONDOMAIN                                                                           (0x1<<10) // ConnectionDomainExist to be used in CM header for packets forwarded to the STORM through the X/YSEM interface.
+  #define NIG_REG_CM_HDR_CONDOMAIN_SHIFT                                                                     10
+#define NIG_REG_TX_LB_DROP_FWDERR                                                                            0x500844UL //Access:RW   DataWidth:0x1    // Global configuration for selecting whether to drop the per-PF drop and per-VPORT drop packets or forward the packet to the destination with the error bit set.  Set this bit to 1 to forward the packet to the destination with error (as if the error indication in the BTB SOP descriptor as set).  This bit affects both the main TX traffic and LB traffic.
+#define NIG_REG_TX_LB_VPORT_DROP_0_BB_K2                                                                     0x500848UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_1_BB_K2                                                                     0x50084cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_2_BB_K2                                                                     0x500850UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_3_BB_K2                                                                     0x500854UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_4_BB_K2                                                                     0x500858UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_5_BB_K2                                                                     0x50085cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_6_BB_K2                                                                     0x500860UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_7_BB_K2                                                                     0x500864UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_8_BB_K2                                                                     0x500868UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_9_BB_K2                                                                     0x50086cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_10_BB_K2                                                                    0x500870UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_11_BB_K2                                                                    0x500874UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_12_BB_K2                                                                    0x500878UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_13_BB_K2                                                                    0x50087cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_14_BB_K2                                                                    0x500880UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_15_BB_K2                                                                    0x500884UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_16_BB_K2                                                                    0x500888UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_17_BB_K2                                                                    0x50088cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_18_BB_K2                                                                    0x500890UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_19_BB_K2                                                                    0x500894UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_20_BB_K2                                                                    0x500898UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_21_BB_K2                                                                    0x50089cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_22_BB_K2                                                                    0x5008a0UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_23_BB_K2                                                                    0x5008a4UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_24_BB_K2                                                                    0x5008a8UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_25_BB_K2                                                                    0x5008acUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_26_BB_K2                                                                    0x5008b0UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_27_BB_K2                                                                    0x5008b4UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_28_BB_K2                                                                    0x5008b8UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_29_BB_K2                                                                    0x5008bcUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_30_BB_K2                                                                    0x5008c0UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_31_BB_K2                                                                    0x5008c4UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_32_BB_K2                                                                    0x5008c8UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_33_BB_K2                                                                    0x5008ccUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_34_BB_K2                                                                    0x5008d0UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_35_BB_K2                                                                    0x5008d4UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_36_BB_K2                                                                    0x5008d8UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_37_BB_K2                                                                    0x5008dcUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_38_BB_K2                                                                    0x5008e0UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_39_BB_K2                                                                    0x5008e4UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_40_BB_K2                                                                    0x5008e8UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_41_BB_K2                                                                    0x5008ecUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_42_BB_K2                                                                    0x5008f0UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_43_BB_K2                                                                    0x5008f4UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_44_BB_K2                                                                    0x5008f8UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_45_BB_K2                                                                    0x5008fcUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_46_BB_K2                                                                    0x500900UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_47_BB_K2                                                                    0x500904UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_48_BB_K2                                                                    0x500908UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_49_BB_K2                                                                    0x50090cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_50_BB_K2                                                                    0x500910UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_51_BB_K2                                                                    0x500914UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_52_BB_K2                                                                    0x500918UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_53_BB_K2                                                                    0x50091cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_54_BB_K2                                                                    0x500920UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_55_BB_K2                                                                    0x500924UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_56_BB_K2                                                                    0x500928UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_57_BB_K2                                                                    0x50092cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_58_BB_K2                                                                    0x500930UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_59_BB_K2                                                                    0x500934UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_60_BB_K2                                                                    0x500938UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_61_BB_K2                                                                    0x50093cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_62_BB_K2                                                                    0x500940UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_63_BB_K2                                                                    0x500944UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_64_BB_K2                                                                    0x500948UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_65_BB_K2                                                                    0x50094cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_66_BB_K2                                                                    0x500950UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_67_BB_K2                                                                    0x500954UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_68_BB_K2                                                                    0x500958UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_69_BB_K2                                                                    0x50095cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_70_BB_K2                                                                    0x500960UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_71_BB_K2                                                                    0x500964UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_72_BB_K2                                                                    0x500968UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_73_BB_K2                                                                    0x50096cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_74_BB_K2                                                                    0x500970UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_75_BB_K2                                                                    0x500974UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_76_BB_K2                                                                    0x500978UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_77_BB_K2                                                                    0x50097cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_78_BB_K2                                                                    0x500980UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_79_BB_K2                                                                    0x500984UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_80_BB_K2                                                                    0x500988UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_81_BB_K2                                                                    0x50098cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_82_BB_K2                                                                    0x500990UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_83_BB_K2                                                                    0x500994UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_84_BB_K2                                                                    0x500998UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_85_BB_K2                                                                    0x50099cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_86_BB_K2                                                                    0x5009a0UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_87_BB_K2                                                                    0x5009a4UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_88_BB_K2                                                                    0x5009a8UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_89_BB_K2                                                                    0x5009acUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_90_BB_K2                                                                    0x5009b0UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_91_BB_K2                                                                    0x5009b4UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_92_BB_K2                                                                    0x5009b8UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_93_BB_K2                                                                    0x5009bcUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_94_BB_K2                                                                    0x5009c0UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_95_BB_K2                                                                    0x5009c4UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_96_BB_K2                                                                    0x5009c8UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_97_BB_K2                                                                    0x5009ccUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_98_BB_K2                                                                    0x5009d0UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_99_BB_K2                                                                    0x5009d4UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_100_BB_K2                                                                   0x5009d8UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_101_BB_K2                                                                   0x5009dcUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_102_BB_K2                                                                   0x5009e0UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_103_BB_K2                                                                   0x5009e4UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_104_BB_K2                                                                   0x5009e8UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_105_BB_K2                                                                   0x5009ecUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_106_BB_K2                                                                   0x5009f0UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_107_BB_K2                                                                   0x5009f4UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_108_BB_K2                                                                   0x5009f8UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_109_BB_K2                                                                   0x5009fcUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_110_BB_K2                                                                   0x500a00UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_111_BB_K2                                                                   0x500a04UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_112_BB_K2                                                                   0x500a08UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_113_BB_K2                                                                   0x500a0cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_114_BB_K2                                                                   0x500a10UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_115_BB_K2                                                                   0x500a14UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_116_BB_K2                                                                   0x500a18UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_117_BB_K2                                                                   0x500a1cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_118_BB_K2                                                                   0x500a20UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_119_BB_K2                                                                   0x500a24UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_120_BB_K2                                                                   0x500a28UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_121_BB_K2                                                                   0x500a2cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_122_BB_K2                                                                   0x500a30UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_123_BB_K2                                                                   0x500a34UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_124_BB_K2                                                                   0x500a38UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_125_BB_K2                                                                   0x500a3cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_126_BB_K2                                                                   0x500a40UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_127_BB_K2                                                                   0x500a44UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_128_BB_K2                                                                   0x500a48UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_129_BB_K2                                                                   0x500a4cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_130_BB_K2                                                                   0x500a50UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_131_BB_K2                                                                   0x500a54UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_132_BB_K2                                                                   0x500a58UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_133_BB_K2                                                                   0x500a5cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_134_BB_K2                                                                   0x500a60UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_135_BB_K2                                                                   0x500a64UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_136_BB_K2                                                                   0x500a68UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_137_BB_K2                                                                   0x500a6cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_138_BB_K2                                                                   0x500a70UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_139_BB_K2                                                                   0x500a74UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_140_BB_K2                                                                   0x500a78UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_141_BB_K2                                                                   0x500a7cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_142_BB_K2                                                                   0x500a80UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_143_BB_K2                                                                   0x500a84UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_144_BB_K2                                                                   0x500a88UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_145_BB_K2                                                                   0x500a8cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_146_BB_K2                                                                   0x500a90UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_147_BB_K2                                                                   0x500a94UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_148_BB_K2                                                                   0x500a98UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_149_BB_K2                                                                   0x500a9cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_150_BB_K2                                                                   0x500aa0UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_151_BB_K2                                                                   0x500aa4UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_152_BB_K2                                                                   0x500aa8UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_153_BB_K2                                                                   0x500aacUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_154_BB_K2                                                                   0x500ab0UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_155_BB_K2                                                                   0x500ab4UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_156_BB_K2                                                                   0x500ab8UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_157_BB_K2                                                                   0x500abcUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_158_BB_K2                                                                   0x500ac0UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_159_BB_K2                                                                   0x500ac4UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_160_K2                                                                      0x500ac8UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_161_K2                                                                      0x500accUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_162_K2                                                                      0x500ad0UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_163_K2                                                                      0x500ad4UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_164_K2                                                                      0x500ad8UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_165_K2                                                                      0x500adcUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_166_K2                                                                      0x500ae0UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_167_K2                                                                      0x500ae4UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_168_K2                                                                      0x500ae8UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_169_K2                                                                      0x500aecUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_170_K2                                                                      0x500af0UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_171_K2                                                                      0x500af4UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_172_K2                                                                      0x500af8UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_173_K2                                                                      0x500afcUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_174_K2                                                                      0x500b00UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_175_K2                                                                      0x500b04UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_176_K2                                                                      0x500b08UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_177_K2                                                                      0x500b0cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_178_K2                                                                      0x500b10UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_179_K2                                                                      0x500b14UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_180_K2                                                                      0x500b18UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_181_K2                                                                      0x500b1cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_182_K2                                                                      0x500b20UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_183_K2                                                                      0x500b24UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_184_K2                                                                      0x500b28UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_185_K2                                                                      0x500b2cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_186_K2                                                                      0x500b30UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_187_K2                                                                      0x500b34UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_188_K2                                                                      0x500b38UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_189_K2                                                                      0x500b3cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_190_K2                                                                      0x500b40UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_191_K2                                                                      0x500b44UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_192_K2                                                                      0x500b48UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_193_K2                                                                      0x500b4cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_194_K2                                                                      0x500b50UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_195_K2                                                                      0x500b54UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_196_K2                                                                      0x500b58UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_197_K2                                                                      0x500b5cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_198_K2                                                                      0x500b60UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_199_K2                                                                      0x500b64UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_200_K2                                                                      0x500b68UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_201_K2                                                                      0x500b6cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_202_K2                                                                      0x500b70UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_203_K2                                                                      0x500b74UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_204_K2                                                                      0x500b78UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_205_K2                                                                      0x500b7cUL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_206_K2                                                                      0x500b80UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_207_K2                                                                      0x500b84UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_PF_DROP_PERPF                                                                          0x500c00UL //Access:RW   DataWidth:0x1    // Per-PF drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_LB_SOPQ_EMPTY                                                                                0x500c04UL //Access:R    DataWidth:0x1c   // LB SOP descriptor queue empty status.  Bits 15:0 are for LB traffic queues.  Bits 19:16 are for the pure LB queues.
+#define NIG_REG_LB_SOPQ_FULL                                                                                 0x500c08UL //Access:R    DataWidth:0x1c   // LB SOP descriptor queue full status.  Bits 15:0 are for LB traffic queues.  Bits 19:16 are for the pure LB queues.
+#define NIG_REG_TX_SOPQ_EMPTY                                                                                0x500c0cUL //Access:R    DataWidth:0x18   // TX SOP descriptor queue empty status - for main traffic queues.
+#define NIG_REG_TX_SOPQ_FULL                                                                                 0x500c10UL //Access:R    DataWidth:0x18   // TX SOP descriptor queue full status - for main traffic queues.
+#define NIG_REG_TIMESYNC_GEN_REG_BB                                                                          0x500d00UL //Access:WB   DataWidth:0x40   // Addresses for TimeSync related registers in the timesync generator sub-module.
+#define NIG_REG_TIMESYNC_GEN_REG_SIZE                                                                        64
+#define NIG_REG_DORQ_IN_EN                                                                                   0x500e00UL //Access:RW   DataWidth:0x1    // Input enable for the DORQ interface.
+#define NIG_REG_DEBUG_IN_EN                                                                                  0x500e04UL //Access:RW   DataWidth:0x1    // Input enable for debug traffic.
+#define NIG_REG_STORM_OUT_EN                                                                                 0x500e08UL //Access:RW   DataWidth:0x1    // Output enable for the STORM interface. This configuration should be static during run-time.
+#define NIG_REG_PPP_OUT_EN                                                                                   0x500e0cUL //Access:RW   DataWidth:0x1    // Output enable of message to PXP IF.
+#define NIG_REG_MAC_IN_EN                                                                                    0x500e10UL //Access:RW   DataWidth:0x1    // Input enable for RX MAC interface.
+#define NIG_REG_MAC_OUT_EN                                                                                   0x500e14UL //Access:RW   DataWidth:0x1    // Output enable for TX MAC interface.
+#define NIG_REG_RX_BRB_OUT_EN                                                                                0x500e18UL //Access:RW   DataWidth:0x1    // Output enble for RX path to BRB.
+#define NIG_REG_LB_BRB_OUT_EN                                                                                0x500e1cUL //Access:RW   DataWidth:0x1    // Output enable for LB path to BRB.
+#define NIG_REG_FLOWCTRL_OUT_EN                                                                              0x500e20UL //Access:RW   DataWidth:0x1    // Output enable for flow control interfaces to the MAC.
+#define NIG_REG_TX_MACFIFO_ALM_FULL_THR_BB_K2                                                                0x500e40UL //Access:RW   DataWidth:0x4    // Almost full threshold for TX MAC FIFO.
+#define NIG_REG_RX_MACFIFO_EMPTY_BB                                                                          0x500e44UL //Access:R    DataWidth:0x1    // RX FIFO for receiving data from MAC is empty.
+#define NIG_REG_RX_MACFIFO_FULL_BB                                                                           0x500e48UL //Access:R    DataWidth:0x1    // RX FIFO for receiving data from MAC is full.
+#define NIG_REG_TX_MACFIFO_ALM_FULL_BB_K2                                                                    0x500e4cUL //Access:R    DataWidth:0x1    // TX FIFO for transmitting data to MAC is almost full.
+#define NIG_REG_TX_MACFIFO_EMPTY_BB_K2                                                                       0x500e50UL //Access:R    DataWidth:0x1    // TX FIFO for transmitting data to MAC is empty.
+#define NIG_REG_TX_MACFIFO_FULL_BB_K2                                                                        0x500f00UL //Access:R    DataWidth:0x1    // TX FIFO for transmitting data to MAC is full.
+#define NIG_REG_HDR_SKIP_SIZE_BB                                                                             0x501000UL //Access:RW   DataWidth:0x4    // Size of the proprietary header, in 32-bit words, that is present at the start of the packet.  This configuration applies to all packets (excluding flush messages) of the same port.  This informatio is used to skip over or remove the proprietary header.  This is also used in tag insertion for management packets.
+#define NIG_REG_INITIAL_HEADER_SIZE                                                                          0x501004UL //Access:RW   DataWidth:0xa    // The number of bytes in the header, counting from the start of the packet, to pass to the frame crackers in LLHs.  The actual size passed to LLH is the entire packet or this value, rounded up to the number of cycles, whichever that is smaller. Values different from the default value are only for debug purposes and may not work.
+#define NIG_REG_RX_PKT_HAS_FCS                                                                               0x501008UL //Access:RW   DataWidth:0x1    // Packet has Ethernet FCS field.  Set this bit to indicate that the packet has the FCS field at the end of the packet.
+#define NIG_REG_LLH_ARP_TYPE                                                                                 0x50100cUL //Access:RW   DataWidth:0x10   // Ethertype for ARP (filtering rules B).  Defaut is 0x0806.
+#define NIG_REG_LLC_JUMBO_TYPE                                                                               0x501010UL //Access:RW   DataWidth:0x10   // Ethertype for jumbo packets.
+#define NIG_REG_LLC_TYPE_THRESHOLD                                                                           0x501014UL //Access:RW   DataWidth:0x10   // Upper value of LLC Ethertype.
+#define NIG_REG_FIRST_HDR_HDRS_AFTER_BASIC                                                                   0x501018UL //Access:RW   DataWidth:0x8    // Bit-map indicating which L2 hdrs may appear after the basic Ethernet header.  Bit 0-tag0 (outer tag); bit 1-tag1 (inner VLAN); bit 2-tag2; bit 3-tag3; bit 4-tag4; bit 5-tag5; bit 6-reserved; bit 7-llc/snap.  Reset defaults to 0x82 to allow LLC and Inner VLAN headers.
+#define NIG_REG_FIRST_HDR_HDRS_AFTER_LLC_BB                                                                  0x50101cUL //Access:RW   DataWidth:0x8    // Bit-map indicating which L2 hdrs may appear after the LLC header.
+#define NIG_REG_FIRST_HDR_HDRS_AFTER_TAG_0                                                                   0x501020UL //Access:RW   DataWidth:0x8    // Bit-map indicating which L2 hdrs may appear after L2 tag 0.
+#define NIG_REG_FIRST_HDR_HDRS_AFTER_TAG_1                                                                   0x501024UL //Access:RW   DataWidth:0x8    // Bit-map indicating which L2 hdrs may appear after L2 tag 1.  Reset defaults to 0x80 to allow LLC header.
+#define NIG_REG_FIRST_HDR_HDRS_AFTER_TAG_2                                                                   0x501028UL //Access:RW   DataWidth:0x8    // Bit-map indicating which L2 hdrs may appear after L2 tag 2.
+#define NIG_REG_FIRST_HDR_HDRS_AFTER_TAG_3                                                                   0x50102cUL //Access:RW   DataWidth:0x8    // Bit-map indicating which L2 hdrs may appear after L2 tag 3.
+#define NIG_REG_FIRST_HDR_HDRS_AFTER_TAG_4                                                                   0x501030UL //Access:RW   DataWidth:0x8    // Bit-map indicating which L2 hdrs may appear after L2 tag 4.
+#define NIG_REG_FIRST_HDR_HDRS_AFTER_TAG_5                                                                   0x501034UL //Access:RW   DataWidth:0x8    // Bit-map indicating which L2 hdrs may appear after L2 tag 5.
+#define NIG_REG_INNER_HDR_HDRS_AFTER_BASIC                                                                   0x501038UL //Access:RW   DataWidth:0x8    // Bit-map indicating which L2 hdrs may appear after the basic Ethernet header.  Bit 0-tag0 (outer tag); bit 1-tag1 (inner VLAN); bit 2-tag2; bit 3-tag3; bit 4-tag4; bit 5-tag5; bit 6-reserved; bit 7-llc/snap.  Reset defaults to 0x82 to allow LLC and Inner VLAN headers.
+#define NIG_REG_INNER_HDR_HDRS_AFTER_LLC_BB                                                                  0x50103cUL //Access:RW   DataWidth:0x8    // Bit-map indicating which L2 hdrs may appear after the LLC header.
+#define NIG_REG_INNER_HDR_HDRS_AFTER_TAG_0                                                                   0x501040UL //Access:RW   DataWidth:0x8    // Bit-map indicating which L2 hdrs may appear after L2 tag 0.
+#define NIG_REG_INNER_HDR_HDRS_AFTER_TAG_1                                                                   0x501044UL //Access:RW   DataWidth:0x8    // Bit-map indicating which L2 hdrs may appear after L2 tag 1.  Reset defaults to 0x80 to allow LLC header.
+#define NIG_REG_INNER_HDR_HDRS_AFTER_TAG_2                                                                   0x501048UL //Access:RW   DataWidth:0x8    // Bit-map indicating which L2 hdrs may appear after L2 tag 2.
+#define NIG_REG_INNER_HDR_HDRS_AFTER_TAG_3                                                                   0x50104cUL //Access:RW   DataWidth:0x8    // Bit-map indicating which L2 hdrs may appear after L2 tag 3.
+#define NIG_REG_INNER_HDR_HDRS_AFTER_TAG_4                                                                   0x501050UL //Access:RW   DataWidth:0x8    // Bit-map indicating which L2 hdrs may appear after L2 tag 4.
+#define NIG_REG_INNER_HDR_HDRS_AFTER_TAG_5                                                                   0x501054UL //Access:RW   DataWidth:0x8    // Bit-map indicating which L2 hdrs may appear after L2 tag 5.
+#define NIG_REG_ENC_TYPE_ENABLE                                                                              0x501058UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE                                                        (0x1<<0) // Enable bit for Ethernet-over-GRE (L2 GRE) encapsulation.  This enables the comparison of the GRE protocol type field to the configured *gre_eth_type.
+  #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT                                                  0
+  #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE                                                         (0x1<<1) // Enable bit for IP-over-GRE (IP GRE) encapsulation.  This enables the comparison of the GRE protocol type field to the configured *ipv4_type and *ipv6_type.
+  #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT                                                   1
+  #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE                                                               (0x1<<2) // Enable bit for VXLAN encapsulation.  This enables the comparison of the UDP destination port number to the configured *vxlan_port.
+  #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT                                                         2
+#define NIG_REG_VXLAN_CTRL                                                                                   0x50105cUL //Access:RW   DataWidth:0x10   // UDP destination port number for VXLAN.
+#define NIG_REG_IPV4_TYPE_BB                                                                                 0x501060UL //Access:RW   DataWidth:0x10   // Ethertype for IPv4 packets.  Defaults to 0x0800.
+#define NIG_REG_IPV6_TYPE_BB                                                                                 0x501064UL //Access:RW   DataWidth:0x10   // Ethertype for IPv6 packets.  Defaults to 0x86DD.
+#define NIG_REG_FCOE_TYPE_BB                                                                                 0x501068UL //Access:RW   DataWidth:0x10   // FCOE Ethertype - default is 0x8906.
+#define NIG_REG_ROCE_TYPE                                                                                    0x50106cUL //Access:RW   DataWidth:0x10   // Ethertype for RoCE packets.  Defaults to 0x8915.
+#define NIG_REG_GRE_ETH_TYPE                                                                                 0x501070UL //Access:RW   DataWidth:0x10   // Ethertype for the encapsulated Ethernet header following the GRE header.
+#define NIG_REG_TCP_PROTOCOL_BB                                                                              0x501074UL //Access:RW   DataWidth:0x8    // Next header value indicating TCP protocol.
+#define NIG_REG_UDP_PROTOCOL_BB                                                                              0x501078UL //Access:RW   DataWidth:0x8    // Next header value indicating UDP protocol.
+#define NIG_REG_ICMPV4_PROTOCOL_BB                                                                           0x50107cUL //Access:RW   DataWidth:0x8    // IPv4 protocol field for ICMPv4 - defaults to 0x01.
+#define NIG_REG_ICMPV6_PROTOCOL_BB                                                                           0x501080UL //Access:RW   DataWidth:0x8    // IPv6 next header field for ICMPv6 - defaults to 0x3A.
+#define NIG_REG_GRE_PROTOCOL                                                                                 0x501084UL //Access:RW   DataWidth:0x8    // Protocol number for GRE header.
+#define NIG_REG_LLH_DEST_MAC_0_0                                                                             0x501088UL //Access:RW   DataWidth:0x20   // Destination MAC address 1; The LLH will look for this address in all incoming packets.
+#define NIG_REG_LLH_DEST_MAC_0_1                                                                             0x50108cUL //Access:RW   DataWidth:0x10   // Destination MAC address 1; The LLH will look for this address in all incoming packets.
+#define NIG_REG_LLH_DEST_MAC_1_0                                                                             0x501090UL //Access:RW   DataWidth:0x20   // Destination MAC address 2;The LLH will look for this address in all incoming packets.
+#define NIG_REG_LLH_DEST_MAC_1_1                                                                             0x501094UL //Access:RW   DataWidth:0x10   // Destination MAC address 2;The LLH will look for this address in all incoming packets.
+#define NIG_REG_LLH_DEST_MAC_2_0                                                                             0x501098UL //Access:RW   DataWidth:0x20   // Destination MAC address 3;The LLH will look for this address in all incoming packets.
+#define NIG_REG_LLH_DEST_MAC_2_1                                                                             0x50109cUL //Access:RW   DataWidth:0x10   // Destination MAC address 3;The LLH will look for this address in all incoming packets.
+#define NIG_REG_LLH_DEST_MAC_3_0                                                                             0x5010a0UL //Access:RW   DataWidth:0x20   // Destination MAC address 3.  LLH will look for this address in all incoming packets.
+#define NIG_REG_LLH_DEST_MAC_3_1                                                                             0x5010a4UL //Access:RW   DataWidth:0x10   // Destination MAC address 3.  LLH will look for this address in all incoming packets.
+#define NIG_REG_LLH_DEST_MAC_4_0                                                                             0x5010a8UL //Access:RW   DataWidth:0x20   // Destination MAC address 4.  LLH will look for this address in all incoming packets.
+#define NIG_REG_LLH_DEST_MAC_4_1                                                                             0x5010acUL //Access:RW   DataWidth:0x10   // Destination MAC address 4.  LLH will look for this address in all incoming packets.
+#define NIG_REG_LLH_DEST_MAC_5_0                                                                             0x5010b0UL //Access:RW   DataWidth:0x20   // Destination MAC address 5.  LLH will look for this address in all incoming packets.
+#define NIG_REG_LLH_DEST_MAC_5_1                                                                             0x5010b4UL //Access:RW   DataWidth:0x10   // Destination MAC address 5.  LLH will look for this address in all incoming packets.
+#define NIG_REG_LLH_ETHERTYPE0                                                                               0x5010b8UL //Access:RW   DataWidth:0x10   // Ethertype for filtering packets.
+#define NIG_REG_LLH_ETHERTYPE1                                                                               0x5010bcUL //Access:RW   DataWidth:0x10   // Ethertype for filtering packets.
+#define NIG_REG_LLH_VLAN_ID_0                                                                                0x5010c0UL //Access:RW   DataWidth:0xc    // Inner VLAN ID  0 used in NCSI filtering.
+#define NIG_REG_LLH_VLAN_ID_1                                                                                0x5010c4UL //Access:RW   DataWidth:0xc    // Inner VLAN ID  1 used in NCSI filtering.
+#define NIG_REG_LLH_VLAN_ID_2                                                                                0x5010c8UL //Access:RW   DataWidth:0xc    // Inner VLAN ID  2 used in NCSI filtering.
+#define NIG_REG_OUTER_TAG_ID0                                                                                0x5010ccUL //Access:RW   DataWidth:0x10   // Outer Tag value to be compared with for NCSI outer tag rules that are enabled by *llh_ncsi_*_mask_otag0 mask bits.  Bits that are not masked out by *outer_tag_value_mask are compared with the value extracted from the packet.  The value from the packet is taken according to the *outer_tag_value_list* configurations, as used for PF classification.
+#define NIG_REG_OUTER_TAG_ID1                                                                                0x5010d0UL //Access:RW   DataWidth:0x10   // Outer Tag value to be compared with for NCSI outer tag rules that are enabled by *llh_ncsi_*_mask_otag1 mask bits.  Bits that are not masked out by *outer_tag_value_mask are compared with the value extracted from the packet.  The value from the packet is taken according to the *outer_tag_value_list* configurations, as used for PF classification.
+#define NIG_REG_LLH_DEST_IP_0_0                                                                              0x5010d4UL //Access:RW   DataWidth:0x20   // Destination IP address 1;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
+#define NIG_REG_LLH_DEST_IP_0_1                                                                              0x5010d8UL //Access:RW   DataWidth:0x20   // Destination IP address 1;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
+#define NIG_REG_LLH_DEST_IP_0_2                                                                              0x5010dcUL //Access:RW   DataWidth:0x20   // Destination IP address 1;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
+#define NIG_REG_LLH_DEST_IP_0_3                                                                              0x5010e0UL //Access:RW   DataWidth:0x20   // Destination IP address 1;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
+#define NIG_REG_LLH_DEST_IP_1_0                                                                              0x5010e4UL //Access:RW   DataWidth:0x20   // Destination IP address 2;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
+#define NIG_REG_LLH_DEST_IP_1_1                                                                              0x5010e8UL //Access:RW   DataWidth:0x20   // Destination IP address 2;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
+#define NIG_REG_LLH_DEST_IP_1_2                                                                              0x5010ecUL //Access:RW   DataWidth:0x20   // Destination IP address 2;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
+#define NIG_REG_LLH_DEST_IP_1_3                                                                              0x5010f0UL //Access:RW   DataWidth:0x20   // Destination IP address 2;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
+#define NIG_REG_LLH_DEST_IP_2_0                                                                              0x5010f4UL //Access:RW   DataWidth:0x20   // Destination IP address 3;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
+#define NIG_REG_LLH_DEST_IP_2_1                                                                              0x5010f8UL //Access:RW   DataWidth:0x20   // Destination IP address 3;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
+#define NIG_REG_LLH_DEST_IP_2_2                                                                              0x5010fcUL //Access:RW   DataWidth:0x20   // Destination IP address 3;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
+#define NIG_REG_LLH_DEST_IP_2_3                                                                              0x501100UL //Access:RW   DataWidth:0x20   // Destination IP address 3;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
+#define NIG_REG_LLH_IPV4_IPV6_0                                                                              0x501104UL //Access:RW   DataWidth:0x1    // Determine the IP version to look for in llh_dest_ip_0: 0 - IPv6; 1-IPv4.
+#define NIG_REG_LLH_IPV4_IPV6_1                                                                              0x501108UL //Access:RW   DataWidth:0x1    // Determine the IP version to look for in llh_dest_ip_1: 0 - IPv6; 1-IPv4.
+#define NIG_REG_LLH_IPV4_IPV6_2                                                                              0x50110cUL //Access:RW   DataWidth:0x1    // Determine the IP version to look for in llh_dest_ip_2: 0 - IPv6; 1-IPv4.
+#define NIG_REG_LLH_DEST_TCP_0                                                                               0x501110UL //Access:RW   DataWidth:0x10   // Destination TCP address  1. The LLH will look for this address in all incoming packets.
+#define NIG_REG_LLH_DEST_TCP_1                                                                               0x501114UL //Access:RW   DataWidth:0x10   // Destination TCP address  2. The LLH will look for this address in all incoming packets.
+#define NIG_REG_LLH_DEST_TCP_2                                                                               0x501118UL //Access:RW   DataWidth:0x10   // Destination TCP address  3. The LLH will look for this address in all incoming packets.
+#define NIG_REG_LLH_DEST_UDP_0                                                                               0x50111cUL //Access:RW   DataWidth:0x10   // Destination UDP address  1 The LLH will look for this address in all incoming packets.
+#define NIG_REG_LLH_DEST_UDP_1                                                                               0x501120UL //Access:RW   DataWidth:0x10   // Destination UDP address  2  The LLH will look for this address in all incoming packets.
+#define NIG_REG_LLH_DEST_UDP_2                                                                               0x501124UL //Access:RW   DataWidth:0x10   // Destination UDP address  3  The LLH will look for this address in all incoming packets.
+#define NIG_REG_RX_LLH_NCSI_MCP_MASK                                                                         0x501128UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_BRCST                                                                 (0x1<<0) // Mask bit for forwarding broadcast (MAC destination address of all 1's) packets to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_BRCST_SHIFT                                                           0
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ALLMLCST                                                              (0x1<<1) // Mask bit for forwarding multicast (MAC destination address[40]==1 and it is not a broadcast packet) packets to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ALLMLCST_SHIFT                                                        1
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IPV4MLCST                                                             (0x1<<2) // Obsolete.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IPV4MLCST_SHIFT                                                       2
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IPV6_MLCST                                                            (0x1<<3) // Mask bit for forwarding IPv6 multicast (MAC destination address [47:32]==0x3333) packets to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IPV6_MLCST_SHIFT                                                      3
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_UNCST                                                                 (0x1<<4) // Mask bit for forwarding unicast (MAC destination address[40]==0) packets to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_UNCST_SHIFT                                                           4
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC0                                                                  (0x1<<5) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_0 to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC0_SHIFT                                                            5
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC1                                                                  (0x1<<6) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_1 to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC1_SHIFT                                                            6
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC2                                                                  (0x1<<7) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_2 to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC2_SHIFT                                                            7
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC3                                                                  (0x1<<8) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_3 to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC3_SHIFT                                                            8
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC4                                                                  (0x1<<9) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_4 to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC4_SHIFT                                                            9
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC5                                                                  (0x1<<10) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_5 to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC5_SHIFT                                                            10
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ETHERTYPE0                                                            (0x1<<11) // Mask bit for forwarding packets with Ethertype matching *llh_ethertype0 to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ETHERTYPE0_SHIFT                                                      11
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ETHERTYPE1                                                            (0x1<<12) // Mask bit for forwarding packets with Ethertype matching *llh_ethertype1 to be forwarded to the host.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ETHERTYPE1_SHIFT                                                      12
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ARP                                                                   (0x1<<13) // Mask bit for forwarding packets with Ethertype of 0x0806 and Bcast address to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ARP_SHIFT                                                             13
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IP0                                                                   (0x1<<14) // Mask bit for forwarding packets with the IP destination address  matching *llh*_dest_ip_0 and the IP version matching *llh*_ipv4_ipv6_0 to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IP0_SHIFT                                                             14
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IP1                                                                   (0x1<<15) // Mask bit for forwarding packets with the IP destination address  matching *llh*_dest_ip_1 and the IP version matching *llh*_ipv4_ipv6_1 to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IP1_SHIFT                                                             15
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IP2                                                                   (0x1<<16) // Mask bit for forwarding packets with the IP destination address  matching *llh*_dest_ip_2 and the IP version matching *llh*_ipv4_ipv6_2 to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IP2_SHIFT                                                             16
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_TCP0                                                                  (0x1<<17) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_0 to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_TCP0_SHIFT                                                            17
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_TCP1                                                                  (0x1<<18) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_1 to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_TCP1_SHIFT                                                            18
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_TCP2                                                                  (0x1<<19) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_2 to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_TCP2_SHIFT                                                            19
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_NTBS_T_DST                                                            (0x1<<20) // Obsolete.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_NTBS_T_DST_SHIFT                                                      20
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_NTBS_T_SRC                                                            (0x1<<21) // Obsolete.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_NTBS_T_SRC_SHIFT                                                      21
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_UDP0                                                                  (0x1<<22) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_0 to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_UDP0_SHIFT                                                            22
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_UDP1                                                                  (0x1<<23) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_1 to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_UDP1_SHIFT                                                            23
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_UDP2                                                                  (0x1<<24) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_2 to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_UDP2_SHIFT                                                            24
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_RMCP                                                                  (0x1<<25) // Mask bit for forwarding packets with RMCP UDP ports (0x26f and 0x298) to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_RMCP_SHIFT                                                            25
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_NTBS_U_DST                                                            (0x1<<26) // Mask bit for forwarding packets with NetBIOS UDP destination port 137/138/139 to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_NTBS_U_DST_SHIFT                                                      26
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_NTBS_U_SRC                                                            (0x1<<27) // Obsolete.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_NTBS_U_SRC_SHIFT                                                      27
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_DHCP                                                                  (0x1<<28) // Obsolete.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_DHCP_SHIFT                                                            28
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ICMPV6_NA                                                             (0x1<<29) // Mask bit for forwarding ICMPv6 Neighbor Advertisement packets (ICMP over IPv6 with ICMP type = 136 and dst_mac = 0x33:33:00:00:00:01) to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ICMPV6_NA_SHIFT                                                       29
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ICMPV6_RA                                                             (0x1<<30) // Mask bit for forwarding ICMPv6 Router Advertisement packets (ICMP over IPv6 with ICMP type= 134 and dst_mac = 0x33:33:00:00:00:01) to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ICMPV6_RA_SHIFT                                                       30
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ICMPV6                                                                (0x1<<31) // Mask bit for forwarding ICMPv6 packets to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ICMPV6_SHIFT                                                          31
+#define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN                                                                   0x50112cUL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_ANY                                                             (0x1<<0) // Mask bit for forwarding packets with inner VLAN present to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_ANY_SHIFT                                                       0
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_NONE                                                            (0x1<<1) // Mask bit for forwarding packets with no inner VLAN to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_NONE_SHIFT                                                      1
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_ID0                                                             (0x1<<2) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_0 to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_ID0_SHIFT                                                       2
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_ID1                                                             (0x1<<3) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_1 to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_ID1_SHIFT                                                       3
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_ID2                                                             (0x1<<4) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_2 to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_ID2_SHIFT                                                       4
+#define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG                                                                    0x501130UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG_ANY                                                              (0x1<<0) // Mask bit for forwarding packets with outer tag present to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG_ANY_SHIFT                                                        0
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG_NONE                                                             (0x1<<1) // Mask bit for forwarding packets with no outer tag to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG_NONE_SHIFT                                                       1
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG0                                                                 (0x1<<2) // Mask bit for forwarding packets with the outer tag matching *outer_tag_id0 to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG0_SHIFT                                                           2
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG1                                                                 (0x1<<3) // Mask bit for forwarding packets with the outer tag matching *outer_tag_id1 to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG1_SHIFT                                                           3
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG_PF                                                               (0x1<<4) // Mask bit for forwarding packets with outer tag matching the outer tag of one of the enabled PFs to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG_PF_SHIFT                                                         4
+#define NIG_REG_RX_LLH_SVOL_MCP_MASK                                                                         0x501134UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ARP                                                                   (0x1<<0) // Mask bit for forwarding packets with Ethertype matching llh_arp_type to MCP.
+  #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ARP_SHIFT                                                             0
+  #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV4                                                                (0x1<<1) // Mask bit for forwarding IPv4 packets with protocol field matching llh_icmpv4_protocol to MCP.
+  #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV4_SHIFT                                                          1
+  #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV6                                                                (0x1<<2) // Mask bit for forwarding IPv6 packets with next header field matching llh_icmpv6_protocol to MCP.
+  #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV6_SHIFT                                                          2
+  #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV4_ER                                                             (0x1<<3) // Mask bit for forwarding ICMPv4 packets with ICMP type 8 to MCP.
+  #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV4_ER_SHIFT                                                       3
+  #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV6_ER                                                             (0x1<<4) // Mask bit for forwarding ICMPv6 packets with ICMP type 128 to MCP.
+  #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV6_ER_SHIFT                                                       4
+  #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV6_NS                                                             (0x1<<5) // Mask bit for forwarding ICMPv6 packets with ICMP type 135 to MCP.
+  #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV6_NS_SHIFT                                                       5
+#define NIG_REG_RX_LLH_SVOL_MCP_FWD_ALLPF                                                                    0x501138UL //Access:RW   DataWidth:0x1    // Enable bit for forwarding packets from all PFs, including packets that failed PF classification, to MCP in multifunction mode.
+#define NIG_REG_RX_LLH_SVOL_MCP_FWD_PERPF                                                                    0x50113cUL //Access:RW   DataWidth:0x1    // Enable bit for forwarding packets for each PF to MCP in multifunction mode.  This is a per-PF split register.
+#define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK                                                                  0x501140UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_BRCST                                                          (0x1<<0) // Mask bit for not forwarding broadcast (MAC destination address of all 1's) packets to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_BRCST_SHIFT                                                    0
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ALLMLCST                                                       (0x1<<1) // Mask bit for not forwarding multicast (MAC destination address[40]==1 and it is not a broadcast packet) packets to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ALLMLCST_SHIFT                                                 1
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IPV4MLCST                                                      (0x1<<2) // Obsolete.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IPV4MLCST_SHIFT                                                2
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IPV6_MLCST                                                     (0x1<<3) // Mask bit for not forwarding IPv6 multicast (MAC destination address [47:32]==0x3333) packets to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IPV6_MLCST_SHIFT                                               3
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_UNCST                                                          (0x1<<4) // Mask bit for not forwarding unicast (MAC destination address[40]==0) packets to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_UNCST_SHIFT                                                    4
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC0                                                           (0x1<<5) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_0 to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC0_SHIFT                                                     5
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC1                                                           (0x1<<6) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_1 to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC1_SHIFT                                                     6
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC2                                                           (0x1<<7) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_2 to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC2_SHIFT                                                     7
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC3                                                           (0x1<<8) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_3 to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC3_SHIFT                                                     8
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC4                                                           (0x1<<9) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_4 to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC4_SHIFT                                                     9
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC5                                                           (0x1<<10) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_5 to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC5_SHIFT                                                     10
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ETHERTYPE0                                                     (0x1<<11) // Mask bit for not forwarding packets with Ethertype matching *llh_ethertype0 to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ETHERTYPE0_SHIFT                                               11
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ETHERTYPE1                                                     (0x1<<12) // Mask bit for not forwarding packets with Ethertype matching *llh_ethertype1 to be forwarded to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ETHERTYPE1_SHIFT                                               12
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ARP                                                            (0x1<<13) // Mask bit for not forwarding packets with Ethertype of 0x0806 and bcast address to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ARP_SHIFT                                                      13
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IP0                                                            (0x1<<14) // Mask bit for not forwarding packets with the IP destination address  matching *llh*_dest_ip_0 and the IP version matching *llh*_ipv4_ipv6_0 to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IP0_SHIFT                                                      14
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IP1                                                            (0x1<<15) // Mask bit for not forwarding packets with the IP destination address  matching *llh*_dest_ip_1 and the IP version matching *llh*_ipv4_ipv6_1 to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IP1_SHIFT                                                      15
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IP2                                                            (0x1<<16) // Mask bit for not forwarding packets with the IP destination address  matching *llh*_dest_ip_2 and the IP version matching *llh*_ipv4_ipv6_2 to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IP2_SHIFT                                                      16
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_TCP0                                                           (0x1<<17) // Mask bit for not forwarding packets with the TCP destination port matching *llh*_dest_tcp_0 to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_TCP0_SHIFT                                                     17
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_TCP1                                                           (0x1<<18) // Mask bit for not forwarding packets with the TCP destination port matching *llh*_dest_tcp_1 to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_TCP1_SHIFT                                                     18
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_TCP2                                                           (0x1<<19) // Mask bit for not forwarding packets with the TCP destination port matching *llh*_dest_tcp_2 to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_TCP2_SHIFT                                                     19
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_NTBS_T_DST                                                     (0x1<<20) // Obsolete.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_NTBS_T_DST_SHIFT                                               20
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_NTBS_T_SRC                                                     (0x1<<21) // Obsolete.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_NTBS_T_SRC_SHIFT                                               21
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_UDP0                                                           (0x1<<22) // Mask bit for not forwarding packets with the UDP destination port matching *llh*_dest_udp_0 to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_UDP0_SHIFT                                                     22
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_UDP1                                                           (0x1<<23) // Mask bit for not forwarding packets with the UDP destination port matching *llh*_dest_udp_1 to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_UDP1_SHIFT                                                     23
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_UDP2                                                           (0x1<<24) // Mask bit for not forwarding packets with the UDP destination port matching *llh*_dest_udp_2 to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_UDP2_SHIFT                                                     24
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_RMCP                                                           (0x1<<25) // Mask bit for not forwarding packets with RMCP UDP ports (0x26f and 0x298) to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_RMCP_SHIFT                                                     25
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_NTBS_U_DST                                                     (0x1<<26) // Mask bit for not forwarding packets with NetBIOS UDP destination port 137/138/139 to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_NTBS_U_DST_SHIFT                                               26
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_NTBS_U_SRC                                                     (0x1<<27) // Obsolete.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_NTBS_U_SRC_SHIFT                                               27
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP                                                           (0x1<<28) // Obsolete.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP_SHIFT                                                     28
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ICMPV6_NA                                                      (0x1<<29) // Mask bit for not forwarding ICMPv6 Neighbor Advertisement packets (ICMP over IPv6 with ICMP type = 136 and dst_mac = 0x33:33:00:00:00:01) to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ICMPV6_NA_SHIFT                                                29
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ICMPV6_RA                                                      (0x1<<30) // Mask bit for not forwarding ICMPv6 Router Advertisement packets (ICMP over IPv6 with ICMP type = 134 and dst_mac = 0x33:33:00:00:00:01) to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ICMPV6_RA_SHIFT                                                30
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ICMPV6                                                         (0x1<<31) // Mask bit for not forwarding ICMPv6 packets to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ICMPV6_SHIFT                                                   31
+#define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN                                                            0x501144UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_ANY                                                      (0x1<<0) // Mask bit for not forwarding packets with inner VLAN present to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_ANY_SHIFT                                                0
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_NONE                                                     (0x1<<1) // Mask bit for not forwarding packets with no inner VLAN to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_NONE_SHIFT                                               1
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_ID0                                                      (0x1<<2) // Mask bit for not forwarding packets with the inner VLAN ID matching *llh*_vlan_id_0 to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_ID0_SHIFT                                                2
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_ID1                                                      (0x1<<3) // Mask bit for not forwarding packets with the inner VLAN ID matching *llh*_vlan_id_1 to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_ID1_SHIFT                                                3
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_ID2                                                      (0x1<<4) // Mask bit for not forwarding packets with the inner VLAN ID matching *llh*_vlan_id_2 to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_ID2_SHIFT                                                4
+#define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG                                                             0x501148UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG_ANY                                                       (0x1<<0) // Mask bit for not forwarding packets with outer tag present to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG_ANY_SHIFT                                                 0
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG_NONE                                                      (0x1<<1) // Mask bit for not forwarding packets with no outer tag to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG_NONE_SHIFT                                                1
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG0                                                          (0x1<<2) // Mask bit for not forwarding packets with the outer tag matching *outer_tag_id0 to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG0_SHIFT                                                    2
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG1                                                          (0x1<<3) // Mask bit for not forwarding packets with the outer tag matching *outer_tag_id1 to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG1_SHIFT                                                    3
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG_PF                                                        (0x1<<4) // Mask bit for not forwarding packets with outer tag matching the outer tag of one of the enabled PFs to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG_PF_SHIFT                                                  4
+#define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK                                                                  0x50114cUL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ARP                                                            (0x1<<0) // Mask bit for not forwarding packets with Ethertype matching llh_arp_type to the host.
+  #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ARP_SHIFT                                                      0
+  #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV4                                                         (0x1<<1) // Mask bit for not forwarding IPv4 packets with protocol field matching llh_icmpv4_protocol to the host.
+  #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV4_SHIFT                                                   1
+  #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV6                                                         (0x1<<2) // Mask bit for not forwarding IPv6 packets with next header field matching llh_icmpv6_protocol to the host.
+  #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV6_SHIFT                                                   2
+  #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV4_ER                                                      (0x1<<3) // Mask bit for not forwarding ICMPv4 packets with ICMP type 8 to the host.
+  #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV4_ER_SHIFT                                                3
+  #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV6_ER                                                      (0x1<<4) // Mask bit for not forwarding ICMPv6 packets with ICMP type 128 to the host.
+  #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV6_ER_SHIFT                                                4
+  #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV6_NS                                                      (0x1<<5) // Mask bit for not forwarding ICMPv6 packets with ICMP type 135 to the host.
+  #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV6_NS_SHIFT                                                5
+#define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_ALLPF                                                                 0x501150UL //Access:RW   DataWidth:0x1    // Enable bit for not forwarding packets from all PFs, including packets that failed PF classification, to the host in multifunction mode.
+#define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_PERPF                                                                 0x501154UL //Access:RW   DataWidth:0x1    // Enable bit for not forwarding packets for the PF to the host in multifunction mode.  This is a per-PF split register.
+#define NIG_REG_L2FILT_ETHERTYPE0                                                                            0x501158UL //Access:RW   DataWidth:0x10   // Ethertype configuration for L2 filter.
+#define NIG_REG_L2FILT_ETHERTYPE1                                                                            0x50115cUL //Access:RW   DataWidth:0x10   // Ethertype configuration for L2 filter.
+#define NIG_REG_L2FILT_ETHERTYPE2                                                                            0x501160UL //Access:RW   DataWidth:0x10   // Ethertype configuration for L2 filter.
+#define NIG_REG_L2FILT_ETHERTYPE3                                                                            0x501164UL //Access:RW   DataWidth:0x10   // Ethertype configuration for L2 filter.
+#define NIG_REG_L2FILT_ETHERTYPE4                                                                            0x501168UL //Access:RW   DataWidth:0x10   // Ethertype configuration for L2 filter.
+#define NIG_REG_L2FILT_ETHERTYPE5                                                                            0x50116cUL //Access:RW   DataWidth:0x10   // Ethertype configuration for L2 filter.
+#define NIG_REG_L2FILT_MAC_DA0_0                                                                             0x501170UL //Access:RW   DataWidth:0x20   // MAC destination address for L2 filter.
+#define NIG_REG_L2FILT_MAC_DA0_1                                                                             0x501174UL //Access:RW   DataWidth:0x10   // MAC destination address for L2 filter.
+#define NIG_REG_L2FILT_MAC_DA1_0                                                                             0x501178UL //Access:RW   DataWidth:0x20   // MAC destination address for L2 filter.
+#define NIG_REG_L2FILT_MAC_DA1_1                                                                             0x50117cUL //Access:RW   DataWidth:0x10   // MAC destination address for L2 filter.
+#define NIG_REG_L2FILT_MAC_DA2_0                                                                             0x501180UL //Access:RW   DataWidth:0x20   // MAC destination address for L2 filter.
+#define NIG_REG_L2FILT_MAC_DA2_1                                                                             0x501184UL //Access:RW   DataWidth:0x10   // MAC destination address for L2 filter.
+#define NIG_REG_L2FILT_MAC_DA3_0                                                                             0x501188UL //Access:RW   DataWidth:0x20   // MAC destination address for L2 filter.
+#define NIG_REG_L2FILT_MAC_DA3_1                                                                             0x50118cUL //Access:RW   DataWidth:0x10   // MAC destination address for L2 filter.
+#define NIG_REG_L2FILT_MAC_DA4_0                                                                             0x501190UL //Access:RW   DataWidth:0x20   // MAC destination address for L2 filter.
+#define NIG_REG_L2FILT_MAC_DA4_1                                                                             0x501194UL //Access:RW   DataWidth:0x10   // MAC destination address for L2 filter.
+#define NIG_REG_L2FILT_MAC_DA5_0                                                                             0x501198UL //Access:RW   DataWidth:0x20   // MAC destination address for L2 filter.
+#define NIG_REG_L2FILT_MAC_DA5_1                                                                             0x50119cUL //Access:RW   DataWidth:0x10   // MAC destination address for L2 filter.
+#define NIG_REG_L2FILT_INNER_VLAN                                                                            0x5011a0UL //Access:RW   DataWidth:0xc    // Inner VLAN ID for L2 filter.
+#define NIG_REG_L2FILT_OUTER_TAG                                                                             0x5011a4UL //Access:RW   DataWidth:0x10   // Outer tag value for L2 filter.
+#define NIG_REG_RX_LLH_L2FILT_MCP_RULE0                                                                      0x5011a8UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_EN                                                                 (0x1<<0) // L2 filter rule enable.  Set this bit to enable this rule.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_EN_SHIFT                                                           0
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_ADDR_EN                                                            (0x1<<1) // L2 filter address matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_ADDR_EN_SHIFT                                                      1
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_ADDR_SEL                                                           (0x7<<2) // L2 filter address select for choosing one of the *llh_l2filt_mac_da* configurations for comparison.  A value of 6 selects the broadcast address of all 1's for comparison.  A value of 7 selects the MAC address range 01-80-C2-00-00-00 to 01-80-C2-00-00-0F.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_ADDR_SEL_SHIFT                                                     2
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_ETHERTYPE_EN                                                       (0x1<<5) // L2 filter Ethertype matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_ETHERTYPE_EN_SHIFT                                                 5
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_ETHERTYPE_SEL                                                      (0x7<<6) // L2 filter Ethertype select for choosing one of the *llh_l2filt_ethertype* configurations for comparison.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_ETHERTYPE_SEL_SHIFT                                                6
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_INNER_VLAN_EN                                                      (0x1<<9) // L2 filter inner VLAN matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_INNER_VLAN_EN_SHIFT                                                9
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_OUTER_TAG_EN                                                       (0x1<<10) // L2 filter outer tag matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_OUTER_TAG_EN_SHIFT                                                 10
+#define NIG_REG_RX_LLH_L2FILT_MCP_RULE1                                                                      0x5011acUL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_EN                                                                 (0x1<<0) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_EN_SHIFT                                                           0
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_ADDR_EN                                                            (0x1<<1) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_ADDR_EN_SHIFT                                                      1
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_ADDR_SEL                                                           (0x7<<2) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_ADDR_SEL_SHIFT                                                     2
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_ETHERTYPE_EN                                                       (0x1<<5) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_ETHERTYPE_EN_SHIFT                                                 5
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_ETHERTYPE_SEL                                                      (0x7<<6) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_ETHERTYPE_SEL_SHIFT                                                6
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_INNER_VLAN_EN                                                      (0x1<<9) // L2 filter inner VLAN matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_INNER_VLAN_EN_SHIFT                                                9
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_OUTER_TAG_EN                                                       (0x1<<10) // L2 filter outer tag matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_OUTER_TAG_EN_SHIFT                                                 10
+#define NIG_REG_RX_LLH_L2FILT_MCP_RULE2                                                                      0x5011b0UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_EN                                                                 (0x1<<0) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_EN_SHIFT                                                           0
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_ADDR_EN                                                            (0x1<<1) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_ADDR_EN_SHIFT                                                      1
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_ADDR_SEL                                                           (0x7<<2) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_ADDR_SEL_SHIFT                                                     2
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_ETHERTYPE_EN                                                       (0x1<<5) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_ETHERTYPE_EN_SHIFT                                                 5
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_ETHERTYPE_SEL                                                      (0x7<<6) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_ETHERTYPE_SEL_SHIFT                                                6
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_INNER_VLAN_EN                                                      (0x1<<9) // L2 filter inner VLAN matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_INNER_VLAN_EN_SHIFT                                                9
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_OUTER_TAG_EN                                                       (0x1<<10) // L2 filter outer tag matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_OUTER_TAG_EN_SHIFT                                                 10
+#define NIG_REG_RX_LLH_L2FILT_MCP_RULE3                                                                      0x5011b4UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_EN                                                                 (0x1<<0) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_EN_SHIFT                                                           0
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_ADDR_EN                                                            (0x1<<1) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_ADDR_EN_SHIFT                                                      1
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_ADDR_SEL                                                           (0x7<<2) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_ADDR_SEL_SHIFT                                                     2
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_ETHERTYPE_EN                                                       (0x1<<5) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_ETHERTYPE_EN_SHIFT                                                 5
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_ETHERTYPE_SEL                                                      (0x7<<6) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_ETHERTYPE_SEL_SHIFT                                                6
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_INNER_VLAN_EN                                                      (0x1<<9) // L2 filter inner VLAN matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_INNER_VLAN_EN_SHIFT                                                9
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_OUTER_TAG_EN                                                       (0x1<<10) // L2 filter outer tag matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_OUTER_TAG_EN_SHIFT                                                 10
+#define NIG_REG_RX_LLH_L2FILT_MCP_RULE4                                                                      0x5011b8UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_EN                                                                 (0x1<<0) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_EN_SHIFT                                                           0
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_ADDR_EN                                                            (0x1<<1) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_ADDR_EN_SHIFT                                                      1
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_ADDR_SEL                                                           (0x7<<2) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_ADDR_SEL_SHIFT                                                     2
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_ETHERTYPE_EN                                                       (0x1<<5) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_ETHERTYPE_EN_SHIFT                                                 5
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_ETHERTYPE_SEL                                                      (0x7<<6) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_ETHERTYPE_SEL_SHIFT                                                6
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_INNER_VLAN_EN                                                      (0x1<<9) // L2 filter inner VLAN matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_INNER_VLAN_EN_SHIFT                                                9
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_OUTER_TAG_EN                                                       (0x1<<10) // L2 filter outer tag matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_OUTER_TAG_EN_SHIFT                                                 10
+#define NIG_REG_RX_LLH_L2FILT_MCP_RULE5                                                                      0x5011bcUL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_EN                                                                 (0x1<<0) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_EN_SHIFT                                                           0
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_ADDR_EN                                                            (0x1<<1) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_ADDR_EN_SHIFT                                                      1
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_ADDR_SEL                                                           (0x7<<2) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_ADDR_SEL_SHIFT                                                     2
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_ETHERTYPE_EN                                                       (0x1<<5) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_ETHERTYPE_EN_SHIFT                                                 5
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_ETHERTYPE_SEL                                                      (0x7<<6) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_ETHERTYPE_SEL_SHIFT                                                6
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_INNER_VLAN_EN                                                      (0x1<<9) // L2 filter inner VLAN matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_INNER_VLAN_EN_SHIFT                                                9
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_OUTER_TAG_EN                                                       (0x1<<10) // L2 filter outer tag matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_OUTER_TAG_EN_SHIFT                                                 10
+#define NIG_REG_RX_LLH_L2FILT_MCP_RULE6                                                                      0x5011c0UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_EN                                                                 (0x1<<0) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_EN_SHIFT                                                           0
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_ADDR_EN                                                            (0x1<<1) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_ADDR_EN_SHIFT                                                      1
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_ADDR_SEL                                                           (0x7<<2) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_ADDR_SEL_SHIFT                                                     2
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_ETHERTYPE_EN                                                       (0x1<<5) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_ETHERTYPE_EN_SHIFT                                                 5
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_ETHERTYPE_SEL                                                      (0x7<<6) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_ETHERTYPE_SEL_SHIFT                                                6
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_INNER_VLAN_EN                                                      (0x1<<9) // L2 filter inner VLAN matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_INNER_VLAN_EN_SHIFT                                                9
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_OUTER_TAG_EN                                                       (0x1<<10) // L2 filter outer tag matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_OUTER_TAG_EN_SHIFT                                                 10
+#define NIG_REG_RX_LLH_L2FILT_MCP_RULE7                                                                      0x5011c4UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_EN                                                                 (0x1<<0) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_EN_SHIFT                                                           0
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_ADDR_EN                                                            (0x1<<1) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_ADDR_EN_SHIFT                                                      1
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_ADDR_SEL                                                           (0x7<<2) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_ADDR_SEL_SHIFT                                                     2
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_ETHERTYPE_EN                                                       (0x1<<5) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_ETHERTYPE_EN_SHIFT                                                 5
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_ETHERTYPE_SEL                                                      (0x7<<6) // See definition for *l2filt_mcp_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_ETHERTYPE_SEL_SHIFT                                                6
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_INNER_VLAN_EN                                                      (0x1<<9) // L2 filter inner VLAN matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_INNER_VLAN_EN_SHIFT                                                9
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_OUTER_TAG_EN                                                       (0x1<<10) // L2 filter outer tag matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_OUTER_TAG_EN_SHIFT                                                 10
+#define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0                                                               0x5011c8UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_EN                                                          (0x1<<0) // L2 filter (for not forwarding to the host) rule enable.  Set this bit to enable this rule.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_EN_SHIFT                                                    0
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_ADDR_EN                                                     (0x1<<1) // L2 filter (for not forwarding to the host) address matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_ADDR_EN_SHIFT                                               1
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_ADDR_SEL                                                    (0x7<<2) // L2 filter (for not forwarding to the host) address select for choosing one of the *llh_l2filt_mac_da* configurations for comparison.  A value of 6 selects the broadcast address of all 1's for comparison. A value of 7 selects the MAC address range 01-80-C2-00-00-00 to 01-80-C2-00-00-0F.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_ADDR_SEL_SHIFT                                              2
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_ETHERTYPE_EN                                                (0x1<<5) // L2 filter (for not forwarding to the host) Ethertype matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_ETHERTYPE_EN_SHIFT                                          5
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_ETHERTYPE_SEL                                               (0x7<<6) // L2 filter (for not forwarding to the host) Ethertype select for choosing one of the *llh_l2filt_ethertype* configurations for comparison.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_ETHERTYPE_SEL_SHIFT                                         6
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_INNER_VLAN_EN                                               (0x1<<9) // L2 filter inner VLAN matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_INNER_VLAN_EN_SHIFT                                         9
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_OUTER_TAG_EN                                                (0x1<<10) // L2 filter outer tag matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_OUTER_TAG_EN_SHIFT                                          10
+#define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1                                                               0x5011ccUL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_EN                                                          (0x1<<0) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_EN_SHIFT                                                    0
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_ADDR_EN                                                     (0x1<<1) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_ADDR_EN_SHIFT                                               1
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_ADDR_SEL                                                    (0x7<<2) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_ADDR_SEL_SHIFT                                              2
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_ETHERTYPE_EN                                                (0x1<<5) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_ETHERTYPE_EN_SHIFT                                          5
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_ETHERTYPE_SEL                                               (0x7<<6) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_ETHERTYPE_SEL_SHIFT                                         6
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_INNER_VLAN_EN                                               (0x1<<9) // L2 filter inner VLAN matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_INNER_VLAN_EN_SHIFT                                         9
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_OUTER_TAG_EN                                                (0x1<<10) // L2 filter outer tag matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_OUTER_TAG_EN_SHIFT                                          10
+#define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2                                                               0x5011d0UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_EN                                                          (0x1<<0) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_EN_SHIFT                                                    0
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_ADDR_EN                                                     (0x1<<1) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_ADDR_EN_SHIFT                                               1
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_ADDR_SEL                                                    (0x7<<2) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_ADDR_SEL_SHIFT                                              2
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_ETHERTYPE_EN                                                (0x1<<5) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_ETHERTYPE_EN_SHIFT                                          5
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_ETHERTYPE_SEL                                               (0x7<<6) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_ETHERTYPE_SEL_SHIFT                                         6
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_INNER_VLAN_EN                                               (0x1<<9) // L2 filter inner VLAN matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_INNER_VLAN_EN_SHIFT                                         9
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_OUTER_TAG_EN                                                (0x1<<10) // L2 filter outer tag matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_OUTER_TAG_EN_SHIFT                                          10
+#define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3                                                               0x5011d4UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_EN                                                          (0x1<<0) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_EN_SHIFT                                                    0
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_ADDR_EN                                                     (0x1<<1) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_ADDR_EN_SHIFT                                               1
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_ADDR_SEL                                                    (0x7<<2) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_ADDR_SEL_SHIFT                                              2
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_ETHERTYPE_EN                                                (0x1<<5) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_ETHERTYPE_EN_SHIFT                                          5
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_ETHERTYPE_SEL                                               (0x7<<6) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_ETHERTYPE_SEL_SHIFT                                         6
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_INNER_VLAN_EN                                               (0x1<<9) // L2 filter inner VLAN matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_INNER_VLAN_EN_SHIFT                                         9
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_OUTER_TAG_EN                                                (0x1<<10) // L2 filter outer tag matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_OUTER_TAG_EN_SHIFT                                          10
+#define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4                                                               0x5011d8UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_EN                                                          (0x1<<0) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_EN_SHIFT                                                    0
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_ADDR_EN                                                     (0x1<<1) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_ADDR_EN_SHIFT                                               1
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_ADDR_SEL                                                    (0x7<<2) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_ADDR_SEL_SHIFT                                              2
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_ETHERTYPE_EN                                                (0x1<<5) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_ETHERTYPE_EN_SHIFT                                          5
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_ETHERTYPE_SEL                                               (0x7<<6) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_ETHERTYPE_SEL_SHIFT                                         6
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_INNER_VLAN_EN                                               (0x1<<9) // L2 filter inner VLAN matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_INNER_VLAN_EN_SHIFT                                         9
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_OUTER_TAG_EN                                                (0x1<<10) // L2 filter outer tag matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_OUTER_TAG_EN_SHIFT                                          10
+#define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5                                                               0x5011dcUL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_EN                                                          (0x1<<0) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_EN_SHIFT                                                    0
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_ADDR_EN                                                     (0x1<<1) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_ADDR_EN_SHIFT                                               1
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_ADDR_SEL                                                    (0x7<<2) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_ADDR_SEL_SHIFT                                              2
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_ETHERTYPE_EN                                                (0x1<<5) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_ETHERTYPE_EN_SHIFT                                          5
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_ETHERTYPE_SEL                                               (0x7<<6) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_ETHERTYPE_SEL_SHIFT                                         6
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_INNER_VLAN_EN                                               (0x1<<9) // L2 filter inner VLAN matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_INNER_VLAN_EN_SHIFT                                         9
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_OUTER_TAG_EN                                                (0x1<<10) // L2 filter outer tag matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_OUTER_TAG_EN_SHIFT                                          10
+#define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6                                                               0x5011e0UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_EN                                                          (0x1<<0) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_EN_SHIFT                                                    0
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_ADDR_EN                                                     (0x1<<1) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_ADDR_EN_SHIFT                                               1
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_ADDR_SEL                                                    (0x7<<2) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_ADDR_SEL_SHIFT                                              2
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_ETHERTYPE_EN                                                (0x1<<5) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_ETHERTYPE_EN_SHIFT                                          5
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_ETHERTYPE_SEL                                               (0x7<<6) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_ETHERTYPE_SEL_SHIFT                                         6
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_INNER_VLAN_EN                                               (0x1<<9) // L2 filter inner VLAN matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_INNER_VLAN_EN_SHIFT                                         9
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_OUTER_TAG_EN                                                (0x1<<10) // L2 filter outer tag matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_OUTER_TAG_EN_SHIFT                                          10
+#define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7                                                               0x5011e4UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_EN                                                          (0x1<<0) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_EN_SHIFT                                                    0
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_ADDR_EN                                                     (0x1<<1) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_ADDR_EN_SHIFT                                               1
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_ADDR_SEL                                                    (0x7<<2) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_ADDR_SEL_SHIFT                                              2
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_ETHERTYPE_EN                                                (0x1<<5) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_ETHERTYPE_EN_SHIFT                                          5
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_ETHERTYPE_SEL                                               (0x7<<6) // See definition for *l2filt_brb_dntfwd_rule0.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_ETHERTYPE_SEL_SHIFT                                         6
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_INNER_VLAN_EN                                               (0x1<<9) // L2 filter inner VLAN matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_INNER_VLAN_EN_SHIFT                                         9
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_OUTER_TAG_EN                                                (0x1<<10) // L2 filter outer tag matching enable.
+  #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_OUTER_TAG_EN_SHIFT                                          10
+#define NIG_REG_BRB_GATE_DNTFWD_PORT                                                                         0x5011e8UL //Access:RW   DataWidth:0x1    // Disable bit for forwarding packets to the host for this port.  No packet is forwarded to BRB when this bit is set.
+#define NIG_REG_RX_LLH_BRB_GATE_DNTFWD                                                                       0x5011ecUL //Access:RW   DataWidth:0x1    // Disable bit for forwarding packets to the host.  No packet is forwarded to BRB when this bit is set.
+#define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_CLSFAILED                                                             0x5011f0UL //Access:RW   DataWidth:0x1    // Disable bit for forwarding packets that failed PF classification to the host.  No packet with classification failed status is forwarded to BRB when this bit is set in multifunction mode.
+#define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF                                                                 0x5011f4UL //Access:RW   DataWidth:0x1    // Per-PF disable bit for forwarding packets to the host. Packets are not forwarded to BRB for PFs that have this bit set in multifunction mode.  This is a per-PF split register.
+#define NIG_REG_STORM_ETHERTYPE0                                                                             0x5011f8UL //Access:RW   DataWidth:0x10   // Ethertype for filtering packets to the STORM(s).
+#define NIG_REG_STORM_ETHERTYPE1                                                                             0x5011fcUL //Access:RW   DataWidth:0x10   // Ethertype for filtering packets to the STORM(s).
+#define NIG_REG_STORM_ETHERTYPE2                                                                             0x501200UL //Access:RW   DataWidth:0x10   // Ethertype for filtering packets to the STORM(s).
+#define NIG_REG_STORM_ETHERTYPE3                                                                             0x501204UL //Access:RW   DataWidth:0x10   // Ethertype for filtering packets to the STORM(s).
+#define NIG_REG_RX_LLH_STORM_MASK                                                                            0x501208UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define NIG_REG_RX_LLH_STORM_MASK_ETHERTYPE0                                                               (0x1<<0) // Mask bit for filtering packets with Ethertype matching *llh_storm_ethertype0 to the STORM(s).
+  #define NIG_REG_RX_LLH_STORM_MASK_ETHERTYPE0_SHIFT                                                         0
+  #define NIG_REG_RX_LLH_STORM_MASK_ETHERTYPE1                                                               (0x1<<1) // Mask bit for filtering packets with Ethertype matching *llh_storm_ethertype1 to the STORM(s).
+  #define NIG_REG_RX_LLH_STORM_MASK_ETHERTYPE1_SHIFT                                                         1
+  #define NIG_REG_RX_LLH_STORM_MASK_ETHERTYPE2                                                               (0x1<<2) // Mask bit for filtering packets with Ethertype matching *llh_storm_ethertype2 to the STORM(s).
+  #define NIG_REG_RX_LLH_STORM_MASK_ETHERTYPE2_SHIFT                                                         2
+  #define NIG_REG_RX_LLH_STORM_MASK_ETHERTYPE3                                                               (0x1<<3) // Mask bit for filtering packets with Ethertype matching *llh_storm_ethertype3 to the STORM(s).
+  #define NIG_REG_RX_LLH_STORM_MASK_ETHERTYPE3_SHIFT                                                         3
+#define NIG_REG_RX_LLH_DFIFO_EMPTY                                                                           0x501308UL //Access:R    DataWidth:0x1    // LLH Data FIFO empty.
+#define NIG_REG_RX_LLH_DFIFO_FULL                                                                            0x50130cUL //Access:R    DataWidth:0x1    // LLH Data FIFO full.
+#define NIG_REG_RX_LLH_HFIFO_EMPTY                                                                           0x501310UL //Access:R    DataWidth:0x1    // LLH header FIFO empty.
+#define NIG_REG_RX_LLH_HFIFO_FULL                                                                            0x501314UL //Access:R    DataWidth:0x1    // LLH header FIFO full.
+#define NIG_REG_RX_LLH_RFIFO_EMPTY                                                                           0x501318UL //Access:R    DataWidth:0x1    // LLH result FIFO empty.
+#define NIG_REG_RX_LLH_RFIFO_FULL                                                                            0x50131cUL //Access:R    DataWidth:0x1    // LLH result FIFO full.
+#define NIG_REG_STORM_STATUS                                                                                 0x501400UL //Access:R    DataWidth:0x6    // Status from the STORM interface logic.  Bit 0 - message FIFO empty. Bit 1 - descriptor FIFO empty. Bit 2 - message FIFO has more than 32 entries of data. Bit 3 - descriptor FIFO has more than 4 entries of data. Bit 4 - message FIFO is full. Bit 5 - descriptor FIFO is full.
+#define NIG_REG_LB_MIN_CYC_THRESHOLD                                                                         0x501500UL //Access:RW   DataWidth:0x6    // Minimum cycle threshold register for specifying the minimum number of cycles of ready-to-send data remaining below which ETS arbiter for the LB path should start selecting the next packet.  This value should cover the BTB access latency and arbitration time to provide back-to-back packets as needed to sustain the data rate, but should be as low as possilbe to minimize delay in responding to a flow control request.
+#define NIG_REG_LB_PKT_HAS_FCS                                                                               0x501504UL //Access:RW   DataWidth:0x1    // Packet has Ethernet FCS field.  Set this bit to indicate that the packet has the FCS field at the end of the packet.
+#define NIG_REG_LB_ZERO_PAD_EN                                                                               0x501508UL //Access:RW   DataWidth:0x1    // Zero-padding enable for LB packets.  Set this bit to enable the padding of short packets to 60B.  When this bit is clear, LB packets with less than 60B are dropped and not forwarded to the BRB.
+#define NIG_REG_LB_BRBRATELIMIT_CTRL                                                                         0x50150cUL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_EN                                                    (0x1<<0) // Enable bit for the BRB interface rate limiter to be used in pacing LB traffic.  Default to enabled rate limiter for 40Gbps.
+  #define NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_EN_SHIFT                                              0
+  #define NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_BASE_TYPE                                             (0x3<<1) // Select between byte, cycle, and packet level of fairness for the BRB interface rate limiter.  0 selects packet level.  1 selects byte level.  2 selects cycle level.  Value configurations should match the type of fairness selected here.
+  #define NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_BASE_TYPE_SHIFT                                       1
+#define NIG_REG_LB_BRBRATELIMIT_INC_PERIOD                                                                   0x501510UL //Access:RW   DataWidth:0x20   // Increment PERIOD for the BRB interface  rate limiter - in term of 25MHz clock cycles.  Note that this register should be programmed only while this rate limiter is disabled.
+#define NIG_REG_LB_BRBRATELIMIT_INC_VALUE                                                                    0x501514UL //Access:RW   DataWidth:0x20   // Increment VALUE for the BRB interface  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration). This is the amount of data allowed in the configured increment period *inc_period to get the desired data rate.
+#define NIG_REG_LB_BRBRATELIMIT_MAX_VALUE                                                                    0x501518UL //Access:RW   DataWidth:0x20   // Upper bound VALUE for the BRB interface  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration).
+#define NIG_REG_LB_BRBRATELIMIT_IFG_SIZE                                                                     0x50151cUL //Access:RW   DataWidth:0x8    // Value to be added to the packet size for the BRB interface rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.
+#define NIG_REG_LB_TCRATELIMIT_CTRL_0                                                                        0x501520UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_EN_0                                                  (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic.  Default to enabled rate limiter for 20Gbps.
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_EN_0_SHIFT                                            0
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_BASE_TYPE_0                                           (0x3<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter.  0 selects packet level.  1 selects byte level.  2 selects cycle level.  Value configurations should match the type of fairness selected here.
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_BASE_TYPE_0_SHIFT                                     1
+#define NIG_REG_LB_TCRATELIMIT_CTRL_1                                                                        0x501524UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_1_LB_TCRATELIMIT_EN_1                                                  (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic.  Default to enabled rate limiter for 20Gbps.
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_1_LB_TCRATELIMIT_EN_1_SHIFT                                            0
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_1_LB_TCRATELIMIT_BASE_TYPE_1                                           (0x3<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter.  0 selects packet level.  1 selects byte level.  2 selects cycle level.  Value configurations should match the type of fairness selected here.
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_1_LB_TCRATELIMIT_BASE_TYPE_1_SHIFT                                     1
+#define NIG_REG_LB_TCRATELIMIT_CTRL_2                                                                        0x501528UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_2_LB_TCRATELIMIT_EN_2                                                  (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic.  Default to enabled rate limiter for 20Gbps.
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_2_LB_TCRATELIMIT_EN_2_SHIFT                                            0
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_2_LB_TCRATELIMIT_BASE_TYPE_2                                           (0x3<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter.  0 selects packet level.  1 selects byte level.  2 selects cycle level.  Value configurations should match the type of fairness selected here.
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_2_LB_TCRATELIMIT_BASE_TYPE_2_SHIFT                                     1
+#define NIG_REG_LB_TCRATELIMIT_CTRL_3                                                                        0x50152cUL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_3_LB_TCRATELIMIT_EN_3                                                  (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic.  Default to enabled rate limiter for 20Gbps.
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_3_LB_TCRATELIMIT_EN_3_SHIFT                                            0
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_3_LB_TCRATELIMIT_BASE_TYPE_3                                           (0x3<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter.  0 selects packet level.  1 selects byte level.  2 selects cycle level.  Value configurations should match the type of fairness selected here.
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_3_LB_TCRATELIMIT_BASE_TYPE_3_SHIFT                                     1
+#define NIG_REG_LB_TCRATELIMIT_CTRL_4                                                                        0x501530UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_4_LB_TCRATELIMIT_EN_4                                                  (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic.  Default to enabled rate limiter for 20Gbps.
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_4_LB_TCRATELIMIT_EN_4_SHIFT                                            0
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_4_LB_TCRATELIMIT_BASE_TYPE_4                                           (0x3<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter.  0 selects packet level.  1 selects byte level.  2 selects cycle level.  Value configurations should match the type of fairness selected here.
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_4_LB_TCRATELIMIT_BASE_TYPE_4_SHIFT                                     1
+#define NIG_REG_LB_TCRATELIMIT_CTRL_5                                                                        0x501534UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_5_LB_TCRATELIMIT_EN_5                                                  (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic.  Default to enabled rate limiter for 20Gbps.
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_5_LB_TCRATELIMIT_EN_5_SHIFT                                            0
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_5_LB_TCRATELIMIT_BASE_TYPE_5                                           (0x3<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter.  0 selects packet level.  1 selects byte level.  2 selects cycle level.  Value configurations should match the type of fairness selected here.
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_5_LB_TCRATELIMIT_BASE_TYPE_5_SHIFT                                     1
+#define NIG_REG_LB_TCRATELIMIT_CTRL_6                                                                        0x501538UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_6_LB_TCRATELIMIT_EN_6                                                  (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic.  Default to enabled rate limiter for 20Gbps.
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_6_LB_TCRATELIMIT_EN_6_SHIFT                                            0
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_6_LB_TCRATELIMIT_BASE_TYPE_6                                           (0x3<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter.  0 selects packet level.  1 selects byte level.  2 selects cycle level.  Value configurations should match the type of fairness selected here.
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_6_LB_TCRATELIMIT_BASE_TYPE_6_SHIFT                                     1
+#define NIG_REG_LB_TCRATELIMIT_CTRL_7                                                                        0x50153cUL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_7_LB_TCRATELIMIT_EN_7                                                  (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic.  Default to enabled rate limiter for 20Gbps.
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_7_LB_TCRATELIMIT_EN_7_SHIFT                                            0
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_7_LB_TCRATELIMIT_BASE_TYPE_7                                           (0x3<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter.  0 selects packet level.  1 selects byte level.  2 selects cycle level.  Value configurations should match the type of fairness selected here.
+  #define NIG_REG_LB_TCRATELIMIT_CTRL_7_LB_TCRATELIMIT_BASE_TYPE_7_SHIFT                                     1
+#define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_0                                                                  0x501540UL //Access:RW   DataWidth:0x20   // Increment PERIOD for the per-TC  rate limiter - in term of 25MHz clock cycles.  Note that this register should be programmed only while this rate limiter is disabled.
+#define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_1                                                                  0x501544UL //Access:RW   DataWidth:0x20   // Increment PERIOD for the per-TC  rate limiter - in term of 25MHz clock cycles.  Note that this register should be programmed only while this rate limiter is disabled.
+#define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_2                                                                  0x501548UL //Access:RW   DataWidth:0x20   // Increment PERIOD for the per-TC  rate limiter - in term of 25MHz clock cycles.  Note that this register should be programmed only while this rate limiter is disabled.
+#define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_3                                                                  0x50154cUL //Access:RW   DataWidth:0x20   // Increment PERIOD for the per-TC  rate limiter - in term of 25MHz clock cycles.  Note that this register should be programmed only while this rate limiter is disabled.
+#define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_4                                                                  0x501550UL //Access:RW   DataWidth:0x20   // Increment PERIOD for the per-TC  rate limiter - in term of 25MHz clock cycles.  Note that this register should be programmed only while this rate limiter is disabled.
+#define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_5                                                                  0x501554UL //Access:RW   DataWidth:0x20   // Increment PERIOD for the per-TC  rate limiter - in term of 25MHz clock cycles.  Note that this register should be programmed only while this rate limiter is disabled.
+#define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_6                                                                  0x501558UL //Access:RW   DataWidth:0x20   // Increment PERIOD for the per-TC  rate limiter - in term of 25MHz clock cycles.  Note that this register should be programmed only while this rate limiter is disabled.
+#define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_7                                                                  0x50155cUL //Access:RW   DataWidth:0x20   // Increment PERIOD for the per-TC  rate limiter - in term of 25MHz clock cycles.  Note that this register should be programmed only while this rate limiter is disabled.
+#define NIG_REG_LB_TCRATELIMIT_INC_VALUE_0                                                                   0x501560UL //Access:RW   DataWidth:0x20   // Increment VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration). This is the amount of data allowed in the configured increment period *inc_period to get the desired data rate.
+#define NIG_REG_LB_TCRATELIMIT_INC_VALUE_1                                                                   0x501564UL //Access:RW   DataWidth:0x20   // Increment VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration). This is the amount of data allowed in the configured increment period *inc_period to get the desired data rate.
+#define NIG_REG_LB_TCRATELIMIT_INC_VALUE_2                                                                   0x501568UL //Access:RW   DataWidth:0x20   // Increment VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration). This is the amount of data allowed in the configured increment period *inc_period to get the desired data rate.
+#define NIG_REG_LB_TCRATELIMIT_INC_VALUE_3                                                                   0x50156cUL //Access:RW   DataWidth:0x20   // Increment VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration). This is the amount of data allowed in the configured increment period *inc_period to get the desired data rate.
+#define NIG_REG_LB_TCRATELIMIT_INC_VALUE_4                                                                   0x501570UL //Access:RW   DataWidth:0x20   // Increment VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration). This is the amount of data allowed in the configured increment period *inc_period to get the desired data rate.
+#define NIG_REG_LB_TCRATELIMIT_INC_VALUE_5                                                                   0x501574UL //Access:RW   DataWidth:0x20   // Increment VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration). This is the amount of data allowed in the configured increment period *inc_period to get the desired data rate.
+#define NIG_REG_LB_TCRATELIMIT_INC_VALUE_6                                                                   0x501578UL //Access:RW   DataWidth:0x20   // Increment VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration). This is the amount of data allowed in the configured increment period *inc_period to get the desired data rate.
+#define NIG_REG_LB_TCRATELIMIT_INC_VALUE_7                                                                   0x50157cUL //Access:RW   DataWidth:0x20   // Increment VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration). This is the amount of data allowed in the configured increment period *inc_period to get the desired data rate.
+#define NIG_REG_LB_TCRATELIMIT_MAX_VALUE_0                                                                   0x501580UL //Access:RW   DataWidth:0x20   // Upper bound VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration).
+#define NIG_REG_LB_TCRATELIMIT_MAX_VALUE_1                                                                   0x501584UL //Access:RW   DataWidth:0x20   // Upper bound VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration).
+#define NIG_REG_LB_TCRATELIMIT_MAX_VALUE_2                                                                   0x501588UL //Access:RW   DataWidth:0x20   // Upper bound VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration).
+#define NIG_REG_LB_TCRATELIMIT_MAX_VALUE_3                                                                   0x50158cUL //Access:RW   DataWidth:0x20   // Upper bound VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration).
+#define NIG_REG_LB_TCRATELIMIT_MAX_VALUE_4                                                                   0x501590UL //Access:RW   DataWidth:0x20   // Upper bound VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration).
+#define NIG_REG_LB_TCRATELIMIT_MAX_VALUE_5                                                                   0x501594UL //Access:RW   DataWidth:0x20   // Upper bound VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration).
+#define NIG_REG_LB_TCRATELIMIT_MAX_VALUE_6                                                                   0x501598UL //Access:RW   DataWidth:0x20   // Upper bound VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration).
+#define NIG_REG_LB_TCRATELIMIT_MAX_VALUE_7                                                                   0x50159cUL //Access:RW   DataWidth:0x20   // Upper bound VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration).
+#define NIG_REG_LB_TCRATELIMIT_IFG_SIZE_0                                                                    0x5015a0UL //Access:RW   DataWidth:0x8    // Value to be added to the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.
+#define NIG_REG_LB_TCRATELIMIT_IFG_SIZE_1                                                                    0x5015a4UL //Access:RW   DataWidth:0x8    // Value to be added to the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.
+#define NIG_REG_LB_TCRATELIMIT_IFG_SIZE_2                                                                    0x5015a8UL //Access:RW   DataWidth:0x8    // Value to be added to the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.
+#define NIG_REG_LB_TCRATELIMIT_IFG_SIZE_3                                                                    0x5015acUL //Access:RW   DataWidth:0x8    // Value to be added to the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.
+#define NIG_REG_LB_TCRATELIMIT_IFG_SIZE_4                                                                    0x5015b0UL //Access:RW   DataWidth:0x8    // Value to be added to the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.
+#define NIG_REG_LB_TCRATELIMIT_IFG_SIZE_5                                                                    0x5015b4UL //Access:RW   DataWidth:0x8    // Value to be added to the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.
+#define NIG_REG_LB_TCRATELIMIT_IFG_SIZE_6                                                                    0x5015b8UL //Access:RW   DataWidth:0x8    // Value to be added to the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.
+#define NIG_REG_LB_TCRATELIMIT_IFG_SIZE_7                                                                    0x5015bcUL //Access:RW   DataWidth:0x8    // Value to be added to the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.
+#define NIG_REG_LB_ARB_CLIENT_IS_STRICT                                                                      0x5015c0UL //Access:RW   DataWidth:0xa    // Specify whether the client competes directly in the strict priority arbiter.  The bits are mapped according to client ID  (client IDs are defined in *_arb_priority_client): 0-management; 1-TC0 traffic; 2-TC1 traffic; 3-TC2 traffic; 4-TC3 traffic; 5-TC4 traffic; 6-TC5 traffic; 7-TC6 traffic; 8-TC7 traffic; 9-TC8 traffic.  Default value is set to enable strict priorities for all clients.
+#define NIG_REG_LB_ARB_CLIENT_IS_SUBJECT2WFQ                                                                 0x5015c4UL //Access:RW   DataWidth:0xa    // Specify whether the client is subject to WFQ credit blocking.  The bits are mapped according to client ID (client IDs are defined in *_arb_priority_client): 0-management; 1-TC0 traffic; 2-TC1 traffic; 3-TC2 traffic; 4-TC3 traffic; 5-TC4 traffic; 6-TC5 traffic; 7-TC6 traffic; 8-TC7 traffic; 9-TC8 traffic.  Default value is 0 for not using WFQ credit blocking.
+#define NIG_REG_LB_ARB_NUM_STRICT_ARB_SLOTS                                                                  0x5015c8UL //Access:RW   DataWidth:0xc    // Specify the number of strict priority arbitration slots between two round-robin arbitration slots to avoid starvation.  A value of 0 means no strict priority cycles - the strict priority with anti-starvation arbiter becomes a round-robin arbiter.
+#define NIG_REG_LB_ARB_PRIORITY_CLIENT                                                                       0x5015d0UL //Access:WB   DataWidth:0x28   // Specify the client number to be assigned to each priority of the strict priority arbiter.  Priority 0 is the highest priority.  Bits [3:0] are for priority 0 client; bits [39:36] are for priority 9 client.  The clients are assigned the following IDs:  0-management; 1-TC0 traffic; 2-TC1 traffic; 3-TC2 traffic; 4-TC3 traffic; 5-TC4 traffic; 6-TC5 traffic; 7-TC6 traffic; 8-TC7 traffic; 9-TC8 traffic.  The reset value is set to 0x1234567890.
+#define NIG_REG_LB_ARB_PRIORITY_CLIENT_SIZE                                                                  2
+#define NIG_REG_LB_ARB_BURST_MODE                                                                            0x5015d8UL //Access:RW   DataWidth:0x2    // Burst mode enables.  Set these bits to have the round-robin arbiter stays on the winning input instead of moving to the next one.  Bit 0 is for the main round-robin arbiter.  Bit 1 is for the round-robin arbiter within the strict priority with anti-starvation feature.
+#define NIG_REG_LB_ARB_IFG_SIZE                                                                              0x5015dcUL //Access:RW   DataWidth:0x8    // Specify the number of bytes to be deducted from the client credit register at the time of grant in additional to the normal packet credit costs.  This may include the IPG and FCS field.
+#define NIG_REG_LB_ARB_PSEUDO_RR_EN                                                                          0x5015e0UL //Access:RW   DataWidth:0x1    // Enable bit for the pseudo-random arbitration mode.
+#define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_0                                                                  0x5015e4UL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 0 is allowed to reach.
+#define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_1                                                                  0x5015e8UL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 1 is allowed to reach.
+#define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_2                                                                  0x5015ecUL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 2 is allowed to reach.
+#define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_3                                                                  0x5015f0UL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 3 is allowed to reach.
+#define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_4                                                                  0x5015f4UL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 4 is allowed to reach.
+#define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_5                                                                  0x5015f8UL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 5 is allowed to reach.
+#define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_6                                                                  0x5015fcUL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 6 is allowed to reach.
+#define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_7                                                                  0x501600UL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 7 is allowed to reach.
+#define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_8                                                                  0x501604UL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 8 is allowed to reach.
+#define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_9                                                                  0x501608UL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 9 is allowed to reach.
+#define NIG_REG_LB_ARB_CREDIT_WEIGHT_0                                                                       0x50160cUL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 0 when it is time to increment.
+#define NIG_REG_LB_ARB_CREDIT_WEIGHT_1                                                                       0x501610UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 1 when it is time to increment.
+#define NIG_REG_LB_ARB_CREDIT_WEIGHT_2                                                                       0x501614UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 2 when it is time to increment.
+#define NIG_REG_LB_ARB_CREDIT_WEIGHT_3                                                                       0x501618UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 3 when it is time to increment.
+#define NIG_REG_LB_ARB_CREDIT_WEIGHT_4                                                                       0x50161cUL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 4 when it is time to increment.
+#define NIG_REG_LB_ARB_CREDIT_WEIGHT_5                                                                       0x501620UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 5 when it is time to increment.
+#define NIG_REG_LB_ARB_CREDIT_WEIGHT_6                                                                       0x501624UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 6 when it is time to increment.
+#define NIG_REG_LB_ARB_CREDIT_WEIGHT_7                                                                       0x501628UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 7 when it is time to increment.
+#define NIG_REG_LB_ARB_CREDIT_WEIGHT_8                                                                       0x50162cUL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 8 when it is time to increment.
+#define NIG_REG_LB_ARB_CREDIT_WEIGHT_9                                                                       0x501630UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 9 when it is time to increment.
+#define NIG_REG_LB_ARB_CURRENT_CREDIT_0                                                                      0x501634UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register 0.
+#define NIG_REG_LB_ARB_CURRENT_CREDIT_1                                                                      0x501638UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register 1.
+#define NIG_REG_LB_ARB_CURRENT_CREDIT_2                                                                      0x50163cUL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register 2.
+#define NIG_REG_LB_ARB_CURRENT_CREDIT_3                                                                      0x501640UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register 3.
+#define NIG_REG_LB_ARB_CURRENT_CREDIT_4                                                                      0x501644UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register 4.
+#define NIG_REG_LB_ARB_CURRENT_CREDIT_5                                                                      0x501648UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register 5.
+#define NIG_REG_LB_ARB_CURRENT_CREDIT_6                                                                      0x50164cUL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register 6.
+#define NIG_REG_LB_ARB_CURRENT_CREDIT_7                                                                      0x501650UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register 7.
+#define NIG_REG_LB_ARB_CURRENT_CREDIT_8                                                                      0x501654UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register 8.
+#define NIG_REG_LB_ARB_CURRENT_CREDIT_9                                                                      0x501658UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in LB arbiter credit register 9.
+#define NIG_REG_LB_LLH_BRB_GATE_DNTFWD                                                                       0x50165cUL //Access:RW   DataWidth:0x1    // Disable bit for forwarding packets to the host.  No packet is forwarded to BRB when this bit is set.
+#define NIG_REG_LB_LLH_BRB_GATE_DNTFWD_CLSFAILED                                                             0x501660UL //Access:RW   DataWidth:0x1    // Disable bit for forwarding packets that failed PF classification to the host.  No packet with classification failed status is forwarded to BRB when this bit is set in multifunction mode.
+#define NIG_REG_LB_LLH_BRB_GATE_DNTFWD_PERPF                                                                 0x501664UL //Access:RW   DataWidth:0x1    // Per-PF disable bit for forwarding packets to the host. Packets are not forwarded to BRB for PFs that have this bit set in multifunction mode.  This is a per-PF split register.
+#define NIG_REG_LB_BTB_FIFO_ALM_FULL_THR                                                                     0x501764UL //Access:RW   DataWidth:0x5    // Almost full threshold for LB BTB FIFO.
+#define NIG_REG_LB_GNT_FIFO_ALM_FULL_THR                                                                     0x501768UL //Access:RW   DataWidth:0x4    // Almost full threshold for LB GNT FIFO.
+#define NIG_REG_LB_BTB_FIFO_EMPTY                                                                            0x50176cUL //Access:R    DataWidth:0x1    // LB BTB FIFO empty status.
+#define NIG_REG_LB_BTB_FIFO_FULL                                                                             0x501770UL //Access:R    DataWidth:0x1    // LB BTB FIFO full status.
+#define NIG_REG_LB_LLH_DFIFO_ALM_FULL_THR                                                                    0x501774UL //Access:RW   DataWidth:0x6    // LLH Data FIFO almost full threshold.
+#define NIG_REG_LB_LLH_HFIFO_ALM_FULL_THR                                                                    0x501778UL //Access:RW   DataWidth:0x5    // LLH header FIFO almost full threshold.
+#define NIG_REG_LB_LLH_RFIFO_ALM_FULL_THR                                                                    0x50177cUL //Access:RW   DataWidth:0x4    // LLH result FIFO almost full threshold.
+#define NIG_REG_LB_LLH_DFIFO_EMPTY                                                                           0x501780UL //Access:R    DataWidth:0x1    // LLH Data FIFO empty.
+#define NIG_REG_LB_LLH_DFIFO_ALM_FULL                                                                        0x501784UL //Access:R    DataWidth:0x1    // LLH Data FIFO almost full.
+#define NIG_REG_LB_LLH_DFIFO_FULL                                                                            0x501788UL //Access:R    DataWidth:0x1    // LLH Data FIFO full.
+#define NIG_REG_LB_LLH_HFIFO_EMPTY                                                                           0x50178cUL //Access:R    DataWidth:0x1    // LLH header FIFO empty.
+#define NIG_REG_LB_LLH_HFIFO_ALM_FULL                                                                        0x501790UL //Access:R    DataWidth:0x1    // LLH header FIFO almost full.
+#define NIG_REG_LB_LLH_HFIFO_FULL                                                                            0x501794UL //Access:R    DataWidth:0x1    // LLH header FIFO full.
+#define NIG_REG_LB_LLH_RFIFO_EMPTY                                                                           0x501798UL //Access:R    DataWidth:0x1    // LLH result FIFO empty.
+#define NIG_REG_LB_LLH_RFIFO_ALM_FULL                                                                        0x50179cUL //Access:R    DataWidth:0x1    // LLH result FIFO almost full.
+#define NIG_REG_LB_LLH_RFIFO_FULL                                                                            0x501800UL //Access:R    DataWidth:0x1    // LLH result FIFO full.
+#define NIG_REG_RX_PTP_EN                                                                                    0x501900UL //Access:RW   DataWidth:0x3    // Enable for TimeSync feature.  Bit 0 enables TimeSync on RX side.  Bit 1 enables V1 frame format in timesync event detection on RX side.  Bit 2 enables V2 frame format in timesync event detection on RX side.  Note that for HW to detect PTP packet and extract data from the packet, at least one of the version bits of that traffic direction has to be enabled.
+#define NIG_REG_TX_PTP_EN                                                                                    0x501904UL //Access:RW   DataWidth:0x3    // Enable for TimeSync feature.  Bit 0 enables TimeSync on TX side.  Bit 1 enables V1 frame format in timesync event detection on TX side.  Bit 2 enables V2 frame format in timesync event detection on TX side.  Note that for HW to detect PTP packet and extract data from the packet, at least one of the version bits of that traffic direction has to be enabled.
+#define NIG_REG_LLH_PTP_TO_HOST                                                                              0x501908UL //Access:RW   DataWidth:0x1    // Set to 1 to enable PTP packets to be forwarded to the host.
+#define NIG_REG_LLH_PTP_TO_MCP                                                                               0x50190cUL //Access:RW   DataWidth:0x1    // Set to 1 to enable PTP packets to be forwarded to MCP.
+#define NIG_REG_PTP_SW_TXTSEN                                                                                0x501910UL //Access:RW   DataWidth:0x1    // Enable for SW-specified packet timestamp mode.  NIG will capture the timestamp value of the packet that SW indicated through PBF interface for host traffic or through the p*_tx_mng_timestamp_pkt bit for TX management packet.  Note that the tx_ptp_en[0] bit has to be set to enable TimeSync on TX side for this mode to work.  NIG will extract and capture the sequence ID if one of the version bits is enabled.
+#define NIG_REG_LLH_PTP_ETHERTYPE_1                                                                          0x501914UL //Access:RW   DataWidth:0x10   // MAC Ethertype 1 for PTP packet detection.  Ethertype 0 is fixed at 0x88F7.  This register defaults to 0x88f7.
+#define NIG_REG_LLH_PTP_MAC_DA_2_LSB                                                                         0x501918UL //Access:RW   DataWidth:0x20   // MAC destination address 2 for PTP packet detection.  This register holds the lower 4 bytes of the address.  MAC destination address 0 is fixed at 0x011B_1900_0000.  MAC destination address 1 is fixed at 0x0180_C200_000E.  This register defaults to 0x011B_1900_0000.
+#define NIG_REG_LLH_PTP_MAC_DA_2_MSB                                                                         0x50191cUL //Access:RW   DataWidth:0x10   // MAC destination address 2 for PTP packet detection.  This register holds the lower 4 bytes of the address.  MAC destination address 0 is fixed at 0x011B_1900_0000.  MAC destination address 1 is fixed at 0x0180_C200_000E.  This register defaults to 0x011B_1900_0000.
+#define NIG_REG_LLH_PTP_PARAM_MASK                                                                           0x501920UL //Access:RW   DataWidth:0xb    // Mask register for the various parameters used in determining PTP packet presence.  Set each bit to 1 to mask out the particular parameter.  0-IPv4 DA 0 of 224.0.1.129.   1-IPv4 DA 1 of 224.0.0.107.   2-IPv6 DA 0 of 0xFF0*:0:0:0:0:0:0:181.   3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B.   4-UDP destination port 0 of 319. 5-UDP destination port 1 of 320.  6-MAC Ethertype 0 of 0x88F7.   7-configurable MAC Ethertype 1.   8-MAC DA 0 of 0x01-1B-19-00-00-00.   9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable MAC DA 2.  The reset default is set to mask out all parameters.
+#define NIG_REG_LLH_PTP_RULE_MASK                                                                            0x501924UL //Access:RW   DataWidth:0xe    // Mask regiser for the rules used in detecting PTP packets. Set each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .   1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} .  3-{IPv4 DA 1; UDP DP 1} . 4-{IPv6 DA 0; UDP DP 0} .  5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; UDP DP 0} .  7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} .  9-{MAC DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} .  11-{MAC DA 1; Ethertype 1} . 12-{MAC DA 2; Ethertype 0} .  13-{MAC DA 2; Ethertype 1} . The reset default is to mask out all of the rules.  Note that rules 0-3 are for IPv4 packets only and require that the packet is IPv4 for the rules to match.  Note that rules 4-7 are for IPv6 packets only and require that the packet is IPv6 for the rules to match.
+#define NIG_REG_TX_LLH_PTP_PARAM_MASK                                                                        0x501928UL //Access:RW   DataWidth:0xb    // Mask register for the various parameters used in determining PTP packet presence.  Set each bit to 1 to mask out the particular parameter.  0-IPv4 DA 0 of 224.0.1.129.   1-IPv4 DA 1 of 224.0.0.107.   2-IPv6 DA 0 of 0xFF0*:0:0:0:0:0:0:181.   3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B.   4-UDP destination port 0 of 319. 5-UDP destination port 1 of 320.  6-MAC Ethertype 0 of 0x88F7.   7-configurable MAC Ethertype 1.   8-MAC DA 0 of 0x01-1B-19-00-00-00.   9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable MAC DA 2.  The reset default is set to mask out all parameters.
+#define NIG_REG_TX_LLH_PTP_RULE_MASK                                                                         0x50192cUL //Access:RW   DataWidth:0xe    // Mask regiser for the rules used in detecting PTP packets. Set each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .   1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} .  3-{IPv4 DA 1; UDP DP 1} . 4-{IPv6 DA 0; UDP DP 0} .  5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; UDP DP 0} .  7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} .  9-{MAC DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} .  11-{MAC DA 1; Ethertype 1} . 12-{MAC DA 2; Ethertype 0} .  13-{MAC DA 2; Ethertype 1} . The reset default is to mask out all of the rules.
+#define NIG_REG_LLH_PTP_HOST_BUF_SEQID                                                                       0x501930UL //Access:RW   DataWidth:0x11   // Packet TimeSync information that is buffered in 1-deep FIFOs for the host.  Bits [15:0] return the sequence ID of the packet.  Bit 16 indicates the validity of the data in the buffer.  Writing a 1 to bit 16 will clear the buffer.
+#define NIG_REG_LLH_PTP_HOST_BUF_TS_LSB                                                                      0x501934UL //Access:R    DataWidth:0x20   // Packet TimeSync information that is buffered in 1-deep FIFOs for the host.  This location returns the lower 32 bits of timestamp value.
+#define NIG_REG_LLH_PTP_HOST_BUF_TS_MSB                                                                      0x501938UL //Access:R    DataWidth:0x20   // Packet TimeSync information that is buffered in 1-deep FIFOs for the host.  This location returns the upper 32 bits of timestamp value.
+#define NIG_REG_LLH_PTP_MCP_BUF_SEQID                                                                        0x50193cUL //Access:RW   DataWidth:0x11   // Packet TimeSync information that is buffered in 1-deep FIFOs for MCP.  Bits [15:0] return the sequence ID of the packet.  Bit 16 indicates the validity of the data in the buffer.  Writing a 1 to bit 16 will clear the buffer.
+#define NIG_REG_LLH_PTP_MCP_BUF_TS_LSB                                                                       0x501940UL //Access:R    DataWidth:0x20   // Packet TimeSync information that is buffered in 1-deep FIFOs for MCP.  This location returns the lower 32 bits of timestamp value.
+#define NIG_REG_LLH_PTP_MCP_BUF_TS_MSB                                                                       0x501944UL //Access:R    DataWidth:0x20   // Packet TimeSync information that is buffered in 1-deep FIFOs for MCP.  This location returns the upper 32 bits of timestamp value.
+#define NIG_REG_TX_LLH_PTP_BUF_SEQID                                                                         0x501948UL //Access:RW   DataWidth:0x13   // Packet TimeSync information that is buffered in 1-deep FIFOs for TX side.  Bits [15:0] reflect the sequence ID of the packet.  Bit 16 indicates the validity of the data in the buffer.  Bit 17 indicates that the sequence ID is valid and it is waiting for the TX timestamp value.  Bit 18 indicates whether the timestamp is from a SW request (value of 1) or HW request (value of 0).  Writing a 1 to bit 16 will clear the buffer.
+#define NIG_REG_TX_LLH_PTP_BUF_TS_LSB                                                                        0x50194cUL //Access:R    DataWidth:0x20   // Packet TimeSync information that is buffered in 1-deep FIFO for the TX path.  This location returns the lower 32 bits of timestamp value.
+#define NIG_REG_TX_LLH_PTP_BUF_TS_MSB                                                                        0x501950UL //Access:R    DataWidth:0x20   // Packet TimeSync information that is buffered in 1-deep FIFO for the TX path.  This location returns the upper 32 bits of timestamp value.
+#define NIG_REG_RX_PTP_TS_MSB_ERR                                                                            0x501954UL //Access:RW   DataWidth:0x6    // Error detected in adjustment of the upper 32-bit time for the 64-bit timestamp value.  Error occurs when bits [31:30] of the MAC timestamp value and the current free-running time are different by 2.  Bits 1:0 reflects MAC timestamp value 31:30.  Bits 3:2 reflects current time value 31:30.  Bit 4 indicates that no adjustment is made to the upper 32-bit time from the current time.  Bit 5 indicates that the upper 32-bit time is the decremented value from the current time.  The error status is latched until cleared by writing a '1' to bit 0.
+#define NIG_REG_TX_PTP_TS_MSB_ERR                                                                            0x501958UL //Access:RW   DataWidth:0x6    // Error detected in adjustment of the upper 32-bit time for the 64-bit timestamp value.  Error occurs when bits [31:30] of the MAC timestamp value and the current free-running time are different by 2.  Bits 1:0 reflects MAC timestamp value 31:30.  Bits 3:2 reflects current time value 31:30.  Bit 4 indicates that no adjustment is made to the upper 32-bit time from the current time.  Bit 5 indicates that the upper 32-bit time is the decremented value from the current time.  The error status is latched until cleared by writing a '1' to bit 0.
+#define NIG_REG_LLH_MULTI_FUNCTION_MODE                                                                      0x50195cUL //Access:RW   DataWidth:0x1    // Multifunction mode enable.  Set this bit to perform PF classification before sending the packet to the BRB and performing WOL detection.  In single function mode, the PFID for port 0 is based on the translation table entry 0 of port 0, the PFID for port 1 is based on the translation table entry 1 of port 1, the PFID for port 2 is based on the translation table entry 2 of port 2, and the PFID for port 3 is based on the translation table entry 3 of port 3. If reset default values are used, then PFID is the same as port ID.
+#define NIG_REG_LLH_CLS_TYPE                                                                                 0x501960UL //Access:RW   DataWidth:0x2    // Select the PF classification mode. 0: no classification.  1: classification based on tag/VLAN/MAC matching.  2: classification based on protocol. 3: dual-stage classification. When no classification is performed in multifunction mode, PPFID defaults to 0 and PFID is set as specified in entry 0 of the translation table.
+#define NIG_REG_LLH_CLS_TYPE_DUALMODE                                                                        0x501964UL //Access:RW   DataWidth:0x2    // Set this register to select the resolution method for combining the results from the two stages in dual-stage classification mode; value of 0: AND the hit vectors; value of 1: OR the hit vectors; value of 2: take the protocol-based hit vector if there is a hit - otherwise take the other vector; value of 3: take the tag/vlan/mac hit vector if there is a hit - take the other hit vector otherwise.  Note that the hit vectors referenced here are the results from each stage, taken after muxing with the default vectors for that case that there is no match found.
+#define NIG_REG_LLH_PROTOCOL_DEF_PF_VECTOR                                                                   0x501968UL //Access:RW   DataWidth:0x8    // Default per-port value to be used when protocol-based classification fails.  This is the per-port per-PF ID (PPFID) value represented in bit-mapped form.  Note that the classification fail flag is set only when the final classification vector is 0 for not having identified a PF.
+#define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR                                                                     0x50196cUL //Access:RW   DataWidth:0x8    // Default per-port value to be used when outer-tag/inner VLAN/MAC  classification fails.  This is the per-port per-PF ID (PPFID) value represented in bit-mapped form. Note that the classification fail flag is set only when the final classification vector is 0 for not having identified a PF.
+#define NIG_REG_LLH_PPFID2PFID_TBL_0                                                                         0x501970UL //Access:RW   DataWidth:0x4    // Table for translating 3-bit PPFID to 4-bit global PFID. Each port supports 8 functions.  These 8 functions are locally referred to as PPF for port PF.  These functions are identified using PPFID.  The PPFID is mapped to the global PFID based on the information in this table before sending out of the NIG block.  Register *_0 holds the PFID value for the local function 0.  Register *_7 holds the PFID value for the local function 7.  In single-function mode, program this register of port 0 to change the PFID for port 0. Valid PFID values for BB are 0-7.  Valid PFID values for K2 are 0-15.
+#define NIG_REG_LLH_PPFID2PFID_TBL_1                                                                         0x501974UL //Access:RW   DataWidth:0x4    // Table for translating 3-bit PPFID to 4-bit global PFID. Each port supports 8 functions.  These 8 functions are locally referred to as PPF for port PF.  These functions are identified using PPFID.  The PPFID is mapped to the global PFID based on the information in this table before sending out of the NIG block.  Register *_0 holds the PFID value for the local function 0.  Register *_7 holds the PFID value for the local function 7.  In single-function mode, program this register of port 1 to change the PFID for port 1. Valid PFID values for BB are 0-7.  Valid PFID values for K2 are 0-15.
+#define NIG_REG_LLH_PPFID2PFID_TBL_2                                                                         0x501978UL //Access:RW   DataWidth:0x4    // Table for translating 3-bit PPFID to 4-bit global PFID. Each port supports 8 functions.  These 8 functions are locally referred to as PPF for port PF.  These functions are identified using PPFID.  The PPFID is mapped to the global PFID based on the information in this table before sending out of the NIG block.  Register *_0 holds the PFID value for the local function 0.  Register *_7 holds the PFID value for the local function 7.  In single-function mode, program this register of port 2 to change the PFID for port 2. Valid PFID values for BB are 0-7.  Valid PFID values for K2 are 0-15.
+#define NIG_REG_LLH_PPFID2PFID_TBL_3                                                                         0x50197cUL //Access:RW   DataWidth:0x4    // Table for translating 3-bit PPFID to 4-bit global PFID. Each port supports 8 functions.  These 8 functions are locally referred to as PPF for port PF.  These functions are identified using PPFID.  The PPFID is mapped to the global PFID based on the information in this table before sending out of the NIG block.  Register *_0 holds the PFID value for the local function 0.  Register *_7 holds the PFID value for the local function 7.  In single-function mode, program this register of port 3 to change the PFID for port 3. Valid PFID values for BB are 0-7.  Valid PFID values for K2 are 0-15.
+#define NIG_REG_LLH_PPFID2PFID_TBL_4                                                                         0x501980UL //Access:RW   DataWidth:0x4    // Table for translating 3-bit PPFID to 4-bit global PFID. Each port supports 8 functions.  These 8 functions are locally referred to as PPF for port PF.  These functions are identified using PPFID.  The PPFID is mapped to the global PFID based on the information in this table before sending out of the NIG block.  Register *_0 holds the PFID value for the local function 0.  Register *_7 holds the PFID value for the local function 7. Valid PFID values for BB are 0-7.  Valid PFID values for K2 are 0-15.
+#define NIG_REG_LLH_PPFID2PFID_TBL_5                                                                         0x501984UL //Access:RW   DataWidth:0x4    // Table for translating 3-bit PPFID to 4-bit global PFID. Each port supports 8 functions.  These 8 functions are locally referred to as PPF for port PF.  These functions are identified using PPFID.  The PPFID is mapped to the global PFID based on the information in this table before sending out of the NIG block.  Register *_0 holds the PFID value for the local function 0.  Register *_7 holds the PFID value for the local function 7. Valid PFID values for BB are 0-7.  Valid PFID values for K2 are 0-15.
+#define NIG_REG_LLH_PPFID2PFID_TBL_6                                                                         0x501988UL //Access:RW   DataWidth:0x4    // Table for translating 3-bit PPFID to 4-bit global PFID. Each port supports 8 functions.  These 8 functions are locally referred to as PPF for port PF.  These functions are identified using PPFID.  The PPFID is mapped to the global PFID based on the information in this table before sending out of the NIG block.  Register *_0 holds the PFID value for the local function 0.  Register *_7 holds the PFID value for the local function 7. Valid PFID values for BB are 0-7.  Valid PFID values for K2 are 0-15.
+#define NIG_REG_LLH_PPFID2PFID_TBL_7                                                                         0x50198cUL //Access:RW   DataWidth:0x4    // Table for translating 3-bit PPFID to 4-bit global PFID. Each port supports 8 functions.  These 8 functions are locally referred to as PPF for port PF.  These functions are identified using PPFID.  The PPFID is mapped to the global PFID based on the information in this table before sending out of the NIG block.  Register *_0 holds the PFID value for the local function 0.  Register *_7 holds the PFID value for the local function 7. Valid PFID values for BB are 0-7.  Valid PFID values for K2 are 0-15.
+#define NIG_REG_OUTER_TAG_VALUE_LIST0                                                                        0x501990UL //Access:RW   DataWidth:0x18   // Outer tag value list.  This register is used to specify the index of the 64-bit field immediately following the Ethertype to be used for each of the outer tag value bit. The first bit following the Ethertype is referred to as bit 63.  The 64th bit following the Ethertype is referred to as bit 0.  The outer tag value is 16-bit wide.  This register specify the indexes for bits 3:0 of the outer tag value[15:0].  Bits [23:18] of this register specify the index for bit 3.  Bits [5:0] of this register specify the index for bit 0.  These registers default to select the 16 bits starting from the 1st bit following the tag Ethertype (bits [63:48] of the 64-bit field).
+#define NIG_REG_OUTER_TAG_VALUE_LIST1                                                                        0x501994UL //Access:RW   DataWidth:0x18   // Outer tag value list.  See the description for *outer_tag_value_list0.  This register specify the indexes for bits 7:4 of the outer tag value[15:0].  Bits [23:18] of this register specify the index for bit 7.  Bits [5:0] of this register specify the index for bit 4.
+#define NIG_REG_OUTER_TAG_VALUE_LIST2                                                                        0x501998UL //Access:RW   DataWidth:0x18   // Outer tag value list.  See the description for *outer_tag_value_list0.  This register specify the indexes for bits 11:8 of the outer tag value[15:0].  Bits [23:18] of this register specify the index for bit 11.  Bits [5:0] of this register specify the index for bit 8.
+#define NIG_REG_OUTER_TAG_VALUE_LIST3                                                                        0x50199cUL //Access:RW   DataWidth:0x18   // Outer tag value list.  See the description for *outer_tag_value_list0.  This register specify the indexes for bits 15:12 of the outer tag value[15:0].  Bits [23:18] of this register specify the index for bit 15.  Bits [5:0] of this register specify the index for bit 12.
+#define NIG_REG_OUTER_TAG_VALUE_MASK                                                                         0x5019a0UL //Access:RW   DataWidth:0x10   // Outer tag value mask.  Set a bit to 0 to mask out the corresponding bit of the outer tag value.  This register defaults to mask out the upper 4 bits of the tag value.
+#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE                                                                     0x5019a4UL //Access:RW   DataWidth:0x3    // This is a per-port per-PF register.  This register selects the classification type for the tag/VLAN/MAC mode.  Bits 1:0 are decoded as follow:  0 - outer-tag/inner VLAN; 1 - MAC address; 2 - both outer-tag/inner VLAN and MAC address; 3 - either outer-tag/inner VLAN or MAC address. Bit 2 specifies whether the classification is based on Inner VLAN (set to 1) or outer-tag (set to 0).
+#define NIG_REG_LLH_FUNC_TAG_EN                                                                              0x5019b0UL //Access:RW   DataWidth:0x1    // This is a per-port per-PF register.  Per-function outer tag/inner VLAN enable for PF classification.  There are 4 of this register per port per function.
+#define NIG_REG_LLH_FUNC_TAG_EN_SIZE                                                                         4
+#define NIG_REG_LLH_FUNC_TAG_HDR_SEL                                                                         0x5019c0UL //Access:RW   DataWidth:0x1    // This is a per-port per-PF register.  Per-function select bit for choosing between the tunnel and encapsulated header from which to take the inner VLAN for comparison with that in llh_func_tag_value for PF classification; 0 selects the outer/tunnel header.  There are 4 of this register per port per function.
+#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_SIZE                                                                    4
+#define NIG_REG_LLH_FUNC_TAG_VALUE                                                                           0x5019d0UL //Access:RW   DataWidth:0x10   // This is a per-port per-PF register.  Per-function outer tag/inner VLAN configuration for PF classification.  These bits specify the value for comparison.  There are 4 of this register per port per function.  Only bits 11:0 are used to specify the inner VLAN ID. Configuration of an inner VLAN ID of 0 also enables a match for the function when there is no inner VLAN.
+#define NIG_REG_LLH_FUNC_TAG_VALUE_SIZE                                                                      4
+#define NIG_REG_LLH_FUNC_NO_TAG                                                                              0x5019e0UL //Access:RW   DataWidth:0x1    // This is a per-port per-PF register.  Per-function no outer tag/inner VLAN configuration for PF classification.  Set this bit to enable a match for the function when there is no outer tag/inner VLAN.
+#define NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2                                                                  0x501a00UL //Access:WB   DataWidth:0x30   // This is a per-port per-PF register.  Per-function MAC addresses to be matched with for MAC-address-based classification.  This register is also used for protocol-based classification; bits [47:32] are for Ethertype; bits [31:16] are for the source port; and bits [15:0] are for the destination port.  There are 16 of this register per port per function.
+#define NIG_REG_LLH_FUNC_FILTER_VALUE_SIZE                                                                   32
+#define NIG_REG_LLH_FUNC_FILTER_EN_BB_K2                                                                     0x501a80UL //Access:RW   DataWidth:0x1    // This is a per-port per-PF register.  Per-function filter enable for PF classification.  There are 16 of this register per port per function.
+#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE                                                                      16
+#define NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2                                                                   0x501ac0UL //Access:RW   DataWidth:0x1    // This is a per-port per-PF register.  Per-function mode select bit to indicate whether the filter is to be used for MAC-addresss based classification or protocol-based classification.  Set this bit to 1 to select protocol-based classification.  There are 16 of this register per port per function.
+#define NIG_REG_LLH_FUNC_FILTER_MODE_SIZE                                                                    16
+#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2                                                          0x501b00UL //Access:RW   DataWidth:0x7    // This is a per-port per-PF register.  Per-function select bits for the different protocol types to be evaluated in protocol-based classification mode: bit 0: compare the Ethertype; bit 1: compare the TCP source port; bit 2: compare the TCP destination port; bit 3: compare the TCP source and destination ports. bit 4: compare the UDP source port; bit 5: compare the UDP destination port; bit 6: compare the UDP source and destination ports. Set the bit to 1 to enable the comparison.  The results are logically OR'ed together, and thus, a match is found when one or more of the enabled types compare successfully. There are 16 of this register per port per function.
+#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_SIZE                                                           16
+#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_BB_K2                                                                0x501b40UL //Access:RW   DataWidth:0x1    // This is a per-port per-PF register.  Per-function select bit for choosing between the tunnel and encapsulated header from which to take the MAC address to be compared with that in llh_func_filter_value for PF classification; 0 selects the outer/tunnel header.  There are 16 of this register per port per function.
+#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_SIZE                                                                 16
+#define NIG_REG_LLH_ENG_CLS_TYPE                                                                             0x501b80UL //Access:RW   DataWidth:0x1    // Engine classification type.  0 selects connection-based classification.  1 selects the PF-based classification. This register is used only in the single-port with dual engine mode.
+#define NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH                                                               0x501b84UL //Access:RW   DataWidth:0x1    // TCP 4-tuple search for TCP packets.  Set this bit to use the TCP 4-tuple (TCP source and destination port numbers and IP source and destination IP addresses) as the hash string. This register is used only in the single-port with dual engine mode.
+#define NIG_REG_LLH_ENG_CLS_UDP_4_TUPLE_SEARCH                                                               0x501b88UL //Access:RW   DataWidth:0x1    // UDP 4-tuple search for UDP packets.  Set this bit to use the UDP 4-tuple (UDP source and destination port numbers and IP source and destination IP addresses) as the hash string.  This register is used only in the single-port with dual engine mode.
+#define NIG_REG_LLH_ENG_CLS_CRC8_INIT_VAL                                                                    0x501b8cUL //Access:RW   DataWidth:0x8    // Initial remainder value for the CRC8 function used to hash the data string in connection-based engine classification.  This register is used only in the single-port with dual engine mode.
+#define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL                                                                       0x501b90UL //Access:WB   DataWidth:0x40   // 64-entry Engine ID lookup table, with 1 bit per entry.  Set the bit to 1 to have packets associated with the index to be routed to engine 1.  Otherwise, the packet is routed to engine 0.  This register is used only in the single-port with dual engine mode.
+#define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL_SIZE                                                                  2
+#define NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL                                                                      0x501b98UL //Access:RW   DataWidth:0x5    // RoCE destination QP bit select.  This configuration selects one of the 24-bit destination QP bits to be used as the engine ID.  Valid values are 0-23.  This register is used only in the single-port with dual engine mode.
+#define NIG_REG_LLH_ENG_CLS_ENG_ID_PERPF                                                                     0x501b9cUL //Access:RW   DataWidth:0x1    // Per-global-PF engine ID to be used in PF-based engine classification.  Set the bit to 1 to have packets associated with the PF to be routed to engine 1.  Otherwise, the packet is routed to engine 0.  This register is used only in the single-port with dual engine mode.
+#define NIG_REG_FLOWCTRL_MODE                                                                                0x501ba0UL //Access:RW   DataWidth:0x3    // Flow control mode.  0 - disable; 1 - PFC; 2 - LLFC; 3 - PPP; 4 - PAUSE; 5-7 are invalid values.
+#define NIG_REG_PKT_PRIORITY_TO_TC                                                                           0x501ba4UL //Access:RW   DataWidth:0x20   // Eight 4-bit configurations for specifying which TC (0-15 for future expansion) each priorty is to be mapped to. Bits 3:0 specify the TC for priority 0.  Bits 31:28 specify the TC for priority 7.
+#define NIG_REG_PKT_PRIORITY_TAG                                                                             0x501ba8UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define NIG_REG_PKT_PRIORITY_TAG_N_SEL                                                                     (0x7<<0) // Select for the L2 tag to be used for extracting the packet priority information.  Valid values are 2-5 for selecting one of the L2 tags 2-5.  This field is evaluated only when the selected tag is the first tag in the packet. Set this field to 0 when not used.
+  #define NIG_REG_PKT_PRIORITY_TAG_N_SEL_SHIFT                                                               0
+  #define NIG_REG_PKT_PRIORITY_TAG_PKT_PRIORITY_OTAG_BITOFFSET                                               (0xf<<3) // Bit offset in the outer tag starting from which to extract the 3-bit packet priority information.  The first bit following the Ethertype field is referenced as bit 15.  Values of 0 and 1 are invalid.
+  #define NIG_REG_PKT_PRIORITY_TAG_PKT_PRIORITY_OTAG_BITOFFSET_SHIFT                                         3
+  #define NIG_REG_PKT_PRIORITY_TAG_N_BITOFFSET                                                               (0xf<<7) // Bit offset in the selected tag starting from which to extract the 3-bit packet priority information.   The first bit following the Ethertype field is referenced as bit 15.  Values of 0 and 1 are invalid.
+  #define NIG_REG_PKT_PRIORITY_TAG_N_BITOFFSET_SHIFT                                                         7
+#define NIG_REG_FORCE_BRB_FULL                                                                               0x501bacUL //Access:RW   DataWidth:0x9    // Force brb_nig_*_tc_full.  There is one bit per TC and the same configuration is applicable to both RX and LB interfaces to the BRB of the same port.  Set a bit to 1 to force 'full' condition.  This is meant to allow BRB configuration change during run time by truncating/discarding all traffic the same way as if BRB asserted the corresponding per-TC full signals.  This register may change during run time.  Packet truncation/discarding affects all packet types, including LB packets with LB-only header and LB packets with no-drop indication.
+#define NIG_REG_FORCE_BRB_PAUSE                                                                              0x501bb0UL //Access:RW   DataWidth:0x9    // Force 'pause' condition for traffic going to BRB.  There is one bit per TC and the same configuration is applicable to both RX and LB interfaces to the BRB of the same port.  Set a bit to 1 to force 'pause' condition.  This is meant to allow BRB configuration change during run time by pausing/dropping all traffic the same way as if BRB asserted the corresponding signals.  This register may change during run time.
+#define NIG_REG_RX_TC_EN                                                                                     0x501bb4UL //Access:RW   DataWidth:0x8    // Per-TC flow control enable for received XOFF requests to pause transmit queues.  Set a bit to 1 to enable the corresponding TC.  A TC is in XON state when not enabled.
+#define NIG_REG_TX_TC_EN                                                                                     0x501bb8UL //Access:RW   DataWidth:0x8    // Per-TC flow control enable for XOFF messages sent to the MAC.  Set a bit to 1 to enable a  TC.  A TC is in XON state when not enabled.
+#define NIG_REG_LB_TC_EN                                                                                     0x501bbcUL //Access:RW   DataWidth:0x9    // Per-TC flow control enable for received XOFF requests to pause LB queues.  Set a bit to 1 to enable a TC.  A TC is in XON state when not enabled.
+#define NIG_REG_LB_NO_DROP_EN                                                                                0x501bc0UL //Access:RW   DataWidth:0x1    // Enable bit for the no-drop-hdr-ind field of the LB-only-header.  When set, the no-drop-hdr-ind bit of the TC has the same effect as the lb_tc_en configuration above.
+#define NIG_REG_LB_NO_DROP_ON_FULL                                                                           0x501bc4UL //Access:RW   DataWidth:0x1    // Enable the no-drop of LB packets with the no-drop-hdr-ind bit set due to per-TC full backpressure from the BRB.  Note that only the first lb_no_drop_hdr_size cycles of the packet are not dropped. If per-TC full condition exists after the lb_no_drop_hdr_size cycles, then a trunctation cycle of EOP+ERR is sent to the BRB.
+#define NIG_REG_LB_NO_DROP_HDR_SIZE                                                                          0x501bc8UL //Access:RW   DataWidth:0x5    // This field specifies the number of 256-bit cycles, starting from the SOP cycle, of the packet not to be dropped due to no_drop_on_full. If per-TC full condition exists after the lb_no_drop_hdr_size cycles, then a trunctation cycle of EOP+ERR is sent to the BRB.
+#define NIG_REG_PRIORITY_FOR_TC_0                                                                            0x501bccUL //Access:RW   DataWidth:0x10   // Flow control priorities used for each TC.  This register is bit-mapped with one bit for each priority.
+#define NIG_REG_PRIORITY_FOR_TC_1                                                                            0x501bd0UL //Access:RW   DataWidth:0x10   // Flow control priorities used for each TC.  This register is bit-mapped with one bit for each priority.
+#define NIG_REG_PRIORITY_FOR_TC_2                                                                            0x501bd4UL //Access:RW   DataWidth:0x10   // Flow control priorities used for each TC.  This register is bit-mapped with one bit for each priority.
+#define NIG_REG_PRIORITY_FOR_TC_3                                                                            0x501bd8UL //Access:RW   DataWidth:0x10   // Flow control priorities used for each TC.  This register is bit-mapped with one bit for each priority.
+#define NIG_REG_PRIORITY_FOR_TC_4                                                                            0x501bdcUL //Access:RW   DataWidth:0x10   // Flow control priorities used for each TC.  This register is bit-mapped with one bit for each priority.
+#define NIG_REG_PRIORITY_FOR_TC_5                                                                            0x501be0UL //Access:RW   DataWidth:0x10   // Flow control priorities used for each TC.  This register is bit-mapped with one bit for each priority.
+#define NIG_REG_PRIORITY_FOR_TC_6                                                                            0x501be4UL //Access:RW   DataWidth:0x10   // Flow control priorities used for each TC.  This register is bit-mapped with one bit for each priority.
+#define NIG_REG_PRIORITY_FOR_TC_7                                                                            0x501be8UL //Access:RW   DataWidth:0x10   // Flow control priorities used for each TC.  This register is bit-mapped with one bit for each priority.
+#define NIG_REG_RX_TC0_PRIORITY_MASK                                                                         0x501becUL //Access:RW   DataWidth:0x10   // Bit-map indicating which received SAFC/PFC priorities to map to the TC.  A priority is mapped to the TC when the corresponding mask bit is 1.  More than one bit may be set, allowing multiple priorities to be mapped to one TC.
+#define NIG_REG_RX_TC1_PRIORITY_MASK                                                                         0x501bf0UL //Access:RW   DataWidth:0x10   // Bit-map indicating which SAFC/PFC priorities to map to the TC.  A priority is mapped to the TC when the corresponding mask bit is 1.  More than one bit may be set; allowing multiple priorities to be mapped to one TC.
+#define NIG_REG_RX_TC2_PRIORITY_MASK                                                                         0x501bf4UL //Access:RW   DataWidth:0x10   // Bit-map indicating which SAFC/PFC priorities to map to the TC.  A priority is mapped to the TC when the corresponding mask bit is 1.  More than one bit may be set; allowing multiple priorities to be mapped to one TC.
+#define NIG_REG_RX_TC3_PRIORITY_MASK                                                                         0x501bf8UL //Access:RW   DataWidth:0x10   // Bit-map indicating which SAFC/PFC priorities to map to the TC.  A priority is mapped to the TC when the corresponding mask bit is 1.  More than one bit may be set; allowing multiple priorities to be mapped to one TC.
+#define NIG_REG_RX_TC4_PRIORITY_MASK                                                                         0x501bfcUL //Access:RW   DataWidth:0x10   // Bit-map indicating which SAFC/PFC priorities to map to the TC.  A priority is mapped to the TC when the corresponding mask bit is 1.  More than one bit may be set; allowing multiple priorities to be mapped to one TC.  Note that in quad-port per engine mode, there are only TC0-3.
+#define NIG_REG_RX_TC5_PRIORITY_MASK                                                                         0x501c00UL //Access:RW   DataWidth:0x10   // Bit-map indicating which SAFC/PFC priorities to map to the TC.  A priority is mapped to the TC when the corresponding mask bit is 1.  More than one bit may be set; allowing multiple priorities to be mapped to one TC.  Note that in quad-port per engine mode, there are only TC0-3.
+#define NIG_REG_RX_TC6_PRIORITY_MASK                                                                         0x501c04UL //Access:RW   DataWidth:0x10   // Bit-map indicating which SAFC/PFC priorities to map to the TC.  A priority is mapped to the TC when the corresponding mask bit is 1.  More than one bit may be set; allowing multiple priorities to be mapped to one TC.  Note that in quad-port per engine mode, there are only TC0-3.
+#define NIG_REG_RX_TC7_PRIORITY_MASK                                                                         0x501c08UL //Access:RW   DataWidth:0x10   // Bit-map indicating which SAFC/PFC priorities to map to the TC.  A priority is mapped to the TC when the corresponding mask bit is 1.  More than one bit may be set; allowing multiple priorities to be mapped to one TC.  Note that in quad-port per engine mode, there are only TC0-3.
+#define NIG_REG_TC_PAUSE_MAX_0                                                                               0x501c0cUL //Access:RW   DataWidth:0x20   // Maximum number of cycles that a TC can be XOFFed/paused before an interrupt is asserted.  This is used for all TCs of the same port.
+#define NIG_REG_TC_PAUSE_MAX_1                                                                               0x501c10UL //Access:RW   DataWidth:0x8    // Maximum number of cycles that a TC can be XOFFed/paused before an interrupt is asserted.  This is used for all TCs of the same port.
+#define NIG_REG_TX_PAUSE_MAX_0                                                                               0x501c14UL //Access:RW   DataWidth:0x20   // Maximum number of cycles that the TX path is PAUSEd before an interrupt is asserted.  This is used for PAUSE only.
+#define NIG_REG_TX_PAUSE_MAX_1                                                                               0x501c18UL //Access:RW   DataWidth:0x8    // Maximum number of cycles that the TX path is PAUSEd before an interrupt is asserted.  This is used for PAUSE only.
+#define NIG_REG_TX_DRAIN_EN                                                                                  0x501c1cUL //Access:RW   DataWidth:0x1    // Drain mode enable.  Set this bit to enable drain mode. Drain mode starts immediately upon assertion and stops at the next packet boundary upon de-assertion.
+#define NIG_REG_TX_MCP_DRAIN_EN                                                                              0x501c20UL //Access:RW   DataWidth:0x1    // Drain mode enable for TX MCP traffic.  Set this bit to enable drain mode.  Drain mode starts immediately upon assertion and stops at the next packet boundary upon de-assertion.  Note that TX MCP traffic may also be drained if it is based on a TC and the corresponding TC is enabled to drain.
+#define NIG_REG_TX_TC_DRAIN_EN                                                                               0x501c24UL //Access:RW   DataWidth:0x8    // Set these bits to enable the drain mode for TC0 and TC7. Bit 0 is for TC0 flow.  Bit 7 is for TC7 flow.  When enabled -- draining of the corrresponding TC  starts immediately - packet data are dropped and not forwarded to the MAC.  When disabled--draining stops at the next packet boundary.
+#define NIG_REG_LB_TC_DRAIN_EN                                                                               0x501c28UL //Access:RW   DataWidth:0x9    // Set these bits to enable the drain mode for TC0 and TC7. Bit 0 is for TC0 flow.  Bit 8 is for TC8 flow.  When enabled -- draining of the corrresponding TC  starts immediately - packet data are dropped and not forwarded to the BRB.  When disabled--draining stops at the next packet boundary.
+#define NIG_REG_LLFC_XOFF_TIMER_MAX                                                                          0x501c2cUL //Access:RW   DataWidth:0x16   // Timeout value for LLFC XOFF timer in the TX direction for sending refresh LLFC messages to the MAC.  The value is in term of the number of core clock cycles.  The timer starts whenever an LLFC request is sent to the MAC with at least one priority in the XOFF state.  An update LLFC request is sent when the timer expires.  This value should be less than (LLFC XOFF TIME x 512) / (data rate in Gbps x core clock period in ns).  The default value is set for XOFF time of 0x8000, data rate of 10Gbps, and core clock of 375MHz, with 64 deducted from the calculated value.
+#define NIG_REG_LLFC_TX_CYCLE_NUM                                                                            0x501c30UL //Access:RW   DataWidth:0xa    // Number of cycles between 2 LLFC request to the MAC; The minimum value of this register must be 16. The value of this register must be bigger then [ LLFC_IMG register x (core frequency / MAC frequency)].
+#define NIG_REG_PAUSE_STATUS_BRB                                                                             0x501c34UL //Access:R    DataWidth:0x8    // TC pause status from BRB input for main RX traffic, per port.
+#define NIG_REG_PAUSE_STATUS_BRB_LB                                                                          0x501c38UL //Access:R    DataWidth:0x9    // TC pause status from BRB input for LB traffic, per port.
+#define NIG_REG_PAUSE_STATUS_MSDM                                                                            0x501c3cUL //Access:R    DataWidth:0x8    // TC pause status from MSDM input, per port.  This affects main and LB traffic going into RX pipe of the chip.
+#define NIG_REG_PAUSE_STATUS_TSDM                                                                            0x501c40UL //Access:R    DataWidth:0x8    // TC pause status from TSDM input, per port.  This affects main and LB traffic going into RX pipe of the chip.
+#define NIG_REG_PAUSE_STATUS_USDM                                                                            0x501c44UL //Access:R    DataWidth:0x8    // TC pause status from USDM input, per port.  This affects main and LB traffic going into RX pipe of the chip.
+#define NIG_REG_PAUSE_PRIORITY_TO_MAC                                                                        0x501c48UL //Access:R    DataWidth:0x10   // Current value of PFC/LLFC priority or PAUSE signal sent to MAC/PXP, depending on the flow control mode.
+#define NIG_REG_RX_FLOWCTRL_STATUS                                                                           0x501c4cUL //Access:R    DataWidth:0x10   // Current latched flow control (PFC/LLFC) priorities received from the MAC, depending on the *flowctrl_mode.
+#define NIG_REG_RX_FLOWCTRL_STATUS_CLEAR                                                                     0x501c50UL //Access:RW   DataWidth:0x1    // Set this bit to clear the current flow control (PFC and LLFC) latched status.
+#define NIG_REG_PPP_ADDRESS                                                                                  0x501c54UL //Access:RW   DataWidth:0x10   // Address to be used in the header of the flow control message sent to PXP internal write interface.  This configuration should be static while flowctrl_mode is set to PPP.
+#define NIG_REG_PPP_STORM_ID                                                                                 0x501c58UL //Access:RW   DataWidth:0x4    // STORM ID to be used for the Destination Client ID field for the header of the flow control message sent to PXP internal write interface.  This configuration should be static while flowctrl_mode is set to PPP.
+#define NIG_REG_PPP_COMPPARAMS                                                                               0x501c5cUL //Access:RW   DataWidth:0x10   // CompParams value for the header of the flow control message sent to PXP internal write interface. This configuration should be static while flowctrl_mode is set to PPP.
+#define NIG_REG_PPP_TRIG                                                                                     0x501c60UL //Access:RW   DataWidth:0x4    // Trigger value to be used in the header of the flow control message sent to PXP internal write interface. This configuration should be static while flowctrl_mode is set to PPP.
+#define NIG_REG_STAT_RX_BRB_PACKET_PRIORITY_0                                                                0x501c64UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_RX_BRB_PACKET_PRIORITY_1                                                                0x501c68UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_RX_BRB_PACKET_PRIORITY_2                                                                0x501c6cUL //Access:RC   DataWidth:0x20   // Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_RX_BRB_PACKET_PRIORITY_3                                                                0x501c70UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_RX_BRB_PACKET_PRIORITY_4                                                                0x501c74UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_RX_BRB_PACKET_PRIORITY_5                                                                0x501c78UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_RX_BRB_PACKET_PRIORITY_6                                                                0x501c7cUL //Access:RC   DataWidth:0x20   // Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_RX_BRB_PACKET_PRIORITY_7                                                                0x501c80UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_0                                                                 0x501ca0UL //Access:ST   DataWidth:0x40   // Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_0_SIZE                                                            2
+#define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_1                                                                 0x501ca8UL //Access:ST   DataWidth:0x40   // Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_1_SIZE                                                            2
+#define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_2                                                                 0x501cb0UL //Access:ST   DataWidth:0x40   // Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_2_SIZE                                                            2
+#define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_3                                                                 0x501cb8UL //Access:ST   DataWidth:0x40   // Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_3_SIZE                                                            2
+#define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_4                                                                 0x501cc0UL //Access:ST   DataWidth:0x40   // Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_4_SIZE                                                            2
+#define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_5                                                                 0x501cc8UL //Access:ST   DataWidth:0x40   // Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_5_SIZE                                                            2
+#define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_6                                                                 0x501cd0UL //Access:ST   DataWidth:0x40   // Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_6_SIZE                                                            2
+#define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_7                                                                 0x501cd8UL //Access:ST   DataWidth:0x40   // Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_7_SIZE                                                            2
+#define NIG_REG_STAT_RX_NO_DEST                                                                              0x501ce0UL //Access:RC   DataWidth:0x20   // Statistics for packets dropped due to minimum size, parsing errors, and filtering. Note that statistics for packets with 32B or less are in stat_*1cyc_pkt_drop.
+#define NIG_REG_STAT_RX_1CYC_PKT_DROP                                                                        0x501ce4UL //Access:RC   DataWidth:0x20   // Statistics for the number of single-cycle packets dropped. This is an RF generated RC statistics register - reading this register clears the value to 0.
+#define NIG_REG_STAT_RX_BRB_TRUNCATE_PRIORITY_0                                                              0x501ce8UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets being truncated due to BRB full.
+#define NIG_REG_STAT_RX_BRB_TRUNCATE_PRIORITY_1                                                              0x501cecUL //Access:RC   DataWidth:0x20   // Statistics for the number of packets being truncated due to BRB full.
+#define NIG_REG_STAT_RX_BRB_TRUNCATE_PRIORITY_2                                                              0x501cf0UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets being truncated due to BRB full.
+#define NIG_REG_STAT_RX_BRB_TRUNCATE_PRIORITY_3                                                              0x501cf4UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets being truncated due to BRB full.
+#define NIG_REG_STAT_RX_BRB_TRUNCATE_PRIORITY_4                                                              0x501cf8UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets being truncated due to BRB full.
+#define NIG_REG_STAT_RX_BRB_TRUNCATE_PRIORITY_5                                                              0x501cfcUL //Access:RC   DataWidth:0x20   // Statistics for the number of packets being truncated due to BRB full.
+#define NIG_REG_STAT_RX_BRB_TRUNCATE_PRIORITY_6                                                              0x501d00UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets being truncated due to BRB full.
+#define NIG_REG_STAT_RX_BRB_TRUNCATE_PRIORITY_7                                                              0x501d04UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets being truncated due to BRB full.
+#define NIG_REG_STAT_RX_BRB_DISCARD_PRIORITY_0                                                               0x501d08UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets discarded due to BRB backpressure.
+#define NIG_REG_STAT_RX_BRB_DISCARD_PRIORITY_1                                                               0x501d0cUL //Access:RC   DataWidth:0x20   // Statistics for the number of packets discarded due to BRB backpressure.
+#define NIG_REG_STAT_RX_BRB_DISCARD_PRIORITY_2                                                               0x501d10UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets discarded due to BRB backpressure.
+#define NIG_REG_STAT_RX_BRB_DISCARD_PRIORITY_3                                                               0x501d14UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets discarded due to BRB backpressure.
+#define NIG_REG_STAT_RX_BRB_DISCARD_PRIORITY_4                                                               0x501d18UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets discarded due to BRB backpressure.
+#define NIG_REG_STAT_RX_BRB_DISCARD_PRIORITY_5                                                               0x501d1cUL //Access:RC   DataWidth:0x20   // Statistics for the number of packets discarded due to BRB backpressure.
+#define NIG_REG_STAT_RX_BRB_DISCARD_PRIORITY_6                                                               0x501d20UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets discarded due to BRB backpressure.
+#define NIG_REG_STAT_RX_BRB_DISCARD_PRIORITY_7                                                               0x501d24UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets discarded due to BRB backpressure.
+#define NIG_REG_STAT_RX_STORM_PACKET_SENT                                                                    0x501d28UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets forwarded to the STORM.
+#define NIG_REG_STAT_RX_STORM_PACKET_DISCARD                                                                 0x501d2cUL //Access:RC   DataWidth:0x20   // Statistics for the number of packets for the STORM that are dropped due to buffer full.  This is an RF generated RC statistics register - reading this register clears the value to 0.
+#define NIG_REG_STAT_RX_STORM_PACKET_TRUNCATE                                                                0x501d30UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets for the STORM that are truncated due to buffer full.  This is an RF generated RC statistics register - reading this register clears the value to 0.
+#define NIG_REG_STAT_LB_BRB_PACKET_PRIORITY_0                                                                0x501d40UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_LB_BRB_PACKET_PRIORITY_1                                                                0x501d44UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_LB_BRB_PACKET_PRIORITY_2                                                                0x501d48UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_LB_BRB_PACKET_PRIORITY_3                                                                0x501d4cUL //Access:RC   DataWidth:0x20   // Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_LB_BRB_PACKET_PRIORITY_4                                                                0x501d50UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_LB_BRB_PACKET_PRIORITY_5                                                                0x501d54UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_LB_BRB_PACKET_PRIORITY_6                                                                0x501d58UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_LB_BRB_PACKET_PRIORITY_7                                                                0x501d5cUL //Access:RC   DataWidth:0x20   // Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_0                                                                 0x501d60UL //Access:ST   DataWidth:0x40   // Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_0_SIZE                                                            2
+#define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_1                                                                 0x501d68UL //Access:ST   DataWidth:0x40   // Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_1_SIZE                                                            2
+#define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_2                                                                 0x501d70UL //Access:ST   DataWidth:0x40   // Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_2_SIZE                                                            2
+#define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_3                                                                 0x501d78UL //Access:ST   DataWidth:0x40   // Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_3_SIZE                                                            2
+#define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_4                                                                 0x501d80UL //Access:ST   DataWidth:0x40   // Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_4_SIZE                                                            2
+#define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_5                                                                 0x501d88UL //Access:ST   DataWidth:0x40   // Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_5_SIZE                                                            2
+#define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_6                                                                 0x501d90UL //Access:ST   DataWidth:0x40   // Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_6_SIZE                                                            2
+#define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_7                                                                 0x501d98UL //Access:ST   DataWidth:0x40   // Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.
+#define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_7_SIZE                                                            2
+#define NIG_REG_STAT_LB_BRB_TRUNCATE_PRIORITY_0                                                              0x501da0UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets being truncated due to BRB full.
+#define NIG_REG_STAT_LB_BRB_TRUNCATE_PRIORITY_1                                                              0x501da4UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets being truncated due to BRB full.
+#define NIG_REG_STAT_LB_BRB_TRUNCATE_PRIORITY_2                                                              0x501da8UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets being truncated due to BRB full.
+#define NIG_REG_STAT_LB_BRB_TRUNCATE_PRIORITY_3                                                              0x501dacUL //Access:RC   DataWidth:0x20   // Statistics for the number of packets being truncated due to BRB full.
+#define NIG_REG_STAT_LB_BRB_TRUNCATE_PRIORITY_4                                                              0x501db0UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets being truncated due to BRB full.
+#define NIG_REG_STAT_LB_BRB_TRUNCATE_PRIORITY_5                                                              0x501db4UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets being truncated due to BRB full.
+#define NIG_REG_STAT_LB_BRB_TRUNCATE_PRIORITY_6                                                              0x501db8UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets being truncated due to BRB full.
+#define NIG_REG_STAT_LB_BRB_TRUNCATE_PRIORITY_7                                                              0x501dbcUL //Access:RC   DataWidth:0x20   // Statistics for the number of packets being truncated due to BRB full.
+#define NIG_REG_STAT_LB_BRB_DISCARD_PRIORITY_0                                                               0x501dc0UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets discarded due to BRB backpressure.
+#define NIG_REG_STAT_LB_BRB_DISCARD_PRIORITY_1                                                               0x501dc4UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets discarded due to BRB backpressure.
+#define NIG_REG_STAT_LB_BRB_DISCARD_PRIORITY_2                                                               0x501dc8UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets discarded due to BRB backpressure.
+#define NIG_REG_STAT_LB_BRB_DISCARD_PRIORITY_3                                                               0x501dccUL //Access:RC   DataWidth:0x20   // Statistics for the number of packets discarded due to BRB backpressure.
+#define NIG_REG_STAT_LB_BRB_DISCARD_PRIORITY_4                                                               0x501dd0UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets discarded due to BRB backpressure.
+#define NIG_REG_STAT_LB_BRB_DISCARD_PRIORITY_5                                                               0x501dd4UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets discarded due to BRB backpressure.
+#define NIG_REG_STAT_LB_BRB_DISCARD_PRIORITY_6                                                               0x501dd8UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets discarded due to BRB backpressure.
+#define NIG_REG_STAT_LB_BRB_DISCARD_PRIORITY_7                                                               0x501ddcUL //Access:RC   DataWidth:0x20   // Statistics for the number of packets discarded due to BRB backpressure.
+#define NIG_REG_STAT_LB_NO_DEST                                                                              0x501de0UL //Access:RC   DataWidth:0x20   // Statistics for packets dropped due to minimum size, parsing errors, and filtering. Note that statistics for packets with 32B or less are in stat_*1cyc_pkt_drop.
+#define NIG_REG_STAT_LB_1CYC_PKT_DROP                                                                        0x501de4UL //Access:RC   DataWidth:0x20   // Statistics for the number of single-cycle packets dropped. This is an RF generated RC statistics register - reading this register clears the value to 0.
+#define NIG_REG_STAT_TX_DROP                                                                                 0x501de8UL //Access:RC   DataWidth:0x20   // Statistic register for all of the TX packets dropped,  due to the drop bit, the per-PF drop, the per-VPORT drop, and the MCP/per-TC drain mode, and are not forwarded to the destination.
+#define NIG_REG_STAT_TX_PF_VPORTDROP                                                                         0x501decUL //Access:RC   DataWidth:0x20   // Statistic register for the number of TX packets that have the per-PF drop or per-VPORT drop configuration set. These packets may be dropped or forwarded to the destination with error, depending on the tx_lb_drop_fwderr. There may be scenarios of changing drop configurations on the fly. In this case it counts dropped SOP messages
+#define NIG_REG_STAT_LB_DROP                                                                                 0x501df0UL //Access:RC   DataWidth:0x20   // Statistic register for all of the LB packets dropped,  due to the drop bit, the per-PF drop, the per-VPORT drop, and the per-TC drain mode, and are not forwarded to the destination.
+#define NIG_REG_STAT_LB_PF_VPORTDROP                                                                         0x501df4UL //Access:RC   DataWidth:0x20   // Statistic register for the number of LB packets that have the per-PF drop or per-VPORT drop configuration set while the no-drop-hdr-ind in the packet is cleared. These packets may be dropped or forwarded to the destination with error, depending on the tx_lb_drop_fwderr.  When the no-drop-hdr-ind bit is set, the packet drop bit and the per-PF/VPORT drop conditions are ignored and not processed; thus, this statistics does not increment in that case.
+#define NIG_REG_STAT_TX_PACKET_TC_0                                                                          0x501df8UL //Access:RC   DataWidth:0x20   // Statistics for the number of user packets transmitted for the TC.
+#define NIG_REG_STAT_TX_PACKET_TC_1                                                                          0x501dfcUL //Access:RC   DataWidth:0x20   // Statistics for the number of user packets transmitted for the TC.
+#define NIG_REG_STAT_TX_PACKET_TC_2                                                                          0x501e00UL //Access:RC   DataWidth:0x20   // Statistics for the number of user packets transmitted for the TC.
+#define NIG_REG_STAT_TX_PACKET_TC_3                                                                          0x501e04UL //Access:RC   DataWidth:0x20   // Statistics for the number of user packets transmitted for the TC.
+#define NIG_REG_STAT_TX_PACKET_TC_4                                                                          0x501e08UL //Access:RC   DataWidth:0x20   // Statistics for the number of user packets transmitted for the TC.
+#define NIG_REG_STAT_TX_PACKET_TC_5                                                                          0x501e0cUL //Access:RC   DataWidth:0x20   // Statistics for the number of user packets transmitted for the TC.
+#define NIG_REG_STAT_TX_PACKET_TC_6                                                                          0x501e10UL //Access:RC   DataWidth:0x20   // Statistics for the number of user packets transmitted for the TC.
+#define NIG_REG_STAT_TX_PACKET_TC_7                                                                          0x501e14UL //Access:RC   DataWidth:0x20   // Statistics for the number of user packets transmitted for the TC.
+#define NIG_REG_STAT_TX_OCTET_TC_0                                                                           0x501e18UL //Access:ST   DataWidth:0x40   // Statistics for the number of user bytes transmitted for the TC.
+#define NIG_REG_STAT_TX_OCTET_TC_0_SIZE                                                                      2
+#define NIG_REG_STAT_TX_OCTET_TC_1                                                                           0x501e20UL //Access:ST   DataWidth:0x40   // Statistics for the number of user bytes transmitted for the TC.
+#define NIG_REG_STAT_TX_OCTET_TC_1_SIZE                                                                      2
+#define NIG_REG_STAT_TX_OCTET_TC_2                                                                           0x501e28UL //Access:ST   DataWidth:0x40   // Statistics for the number of user bytes transmitted for the TC.
+#define NIG_REG_STAT_TX_OCTET_TC_2_SIZE                                                                      2
+#define NIG_REG_STAT_TX_OCTET_TC_3                                                                           0x501e30UL //Access:ST   DataWidth:0x40   // Statistics for the number of user bytes transmitted for the TC.
+#define NIG_REG_STAT_TX_OCTET_TC_3_SIZE                                                                      2
+#define NIG_REG_STAT_TX_OCTET_TC_4                                                                           0x501e38UL //Access:ST   DataWidth:0x40   // Statistics for the number of user bytes transmitted for the TC.
+#define NIG_REG_STAT_TX_OCTET_TC_4_SIZE                                                                      2
+#define NIG_REG_STAT_TX_OCTET_TC_5                                                                           0x501e40UL //Access:ST   DataWidth:0x40   // Statistics for the number of user bytes transmitted for the TC.
+#define NIG_REG_STAT_TX_OCTET_TC_5_SIZE                                                                      2
+#define NIG_REG_STAT_TX_OCTET_TC_6                                                                           0x501e48UL //Access:ST   DataWidth:0x40   // Statistics for the number of user bytes transmitted for the TC.
+#define NIG_REG_STAT_TX_OCTET_TC_6_SIZE                                                                      2
+#define NIG_REG_STAT_TX_OCTET_TC_7                                                                           0x501e50UL //Access:ST   DataWidth:0x40   // Statistics for the number of user bytes transmitted for the TC.
+#define NIG_REG_STAT_TX_OCTET_TC_7_SIZE                                                                      2
+#define NIG_REG_TX_XOFF_CYC_TC_0                                                                             0x501e58UL //Access:WB_R DataWidth:0x28   // Statistics for the number of cycles that the TC is XOFFed.
+#define NIG_REG_TX_XOFF_CYC_TC_0_SIZE                                                                        2
+#define NIG_REG_TX_XOFF_CYC_TC_1                                                                             0x501e60UL //Access:WB_R DataWidth:0x28   // Statistics for the number of cycles that the TC is XOFFed.
+#define NIG_REG_TX_XOFF_CYC_TC_1_SIZE                                                                        2
+#define NIG_REG_TX_XOFF_CYC_TC_2                                                                             0x501e68UL //Access:WB_R DataWidth:0x28   // Statistics for the number of cycles that the TC is XOFFed.
+#define NIG_REG_TX_XOFF_CYC_TC_2_SIZE                                                                        2
+#define NIG_REG_TX_XOFF_CYC_TC_3                                                                             0x501e70UL //Access:WB_R DataWidth:0x28   // Statistics for the number of cycles that the TC is XOFFed.
+#define NIG_REG_TX_XOFF_CYC_TC_3_SIZE                                                                        2
+#define NIG_REG_TX_XOFF_CYC_TC_4                                                                             0x501e78UL //Access:WB_R DataWidth:0x28   // Statistics for the number of cycles that the TC is XOFFed.
+#define NIG_REG_TX_XOFF_CYC_TC_4_SIZE                                                                        2
+#define NIG_REG_TX_XOFF_CYC_TC_5                                                                             0x501e80UL //Access:WB_R DataWidth:0x28   // Statistics for the number of cycles that the TC is XOFFed.
+#define NIG_REG_TX_XOFF_CYC_TC_5_SIZE                                                                        2
+#define NIG_REG_TX_XOFF_CYC_TC_6                                                                             0x501e88UL //Access:WB_R DataWidth:0x28   // Statistics for the number of cycles that the TC is XOFFed.
+#define NIG_REG_TX_XOFF_CYC_TC_6_SIZE                                                                        2
+#define NIG_REG_TX_XOFF_CYC_TC_7                                                                             0x501e90UL //Access:WB_R DataWidth:0x28   // Statistics for the number of cycles that the TC is XOFFed.
+#define NIG_REG_TX_XOFF_CYC_TC_7_SIZE                                                                        2
+#define NIG_REG_LB_XOFF_CYC_TC_0                                                                             0x501e98UL //Access:WB_R DataWidth:0x28   // Statistics for the number of cycles that the TC is XOFFed.
+#define NIG_REG_LB_XOFF_CYC_TC_0_SIZE                                                                        2
+#define NIG_REG_LB_XOFF_CYC_TC_1                                                                             0x501ea0UL //Access:WB_R DataWidth:0x28   // Statistics for the number of cycles that the TC is XOFFed.
+#define NIG_REG_LB_XOFF_CYC_TC_1_SIZE                                                                        2
+#define NIG_REG_LB_XOFF_CYC_TC_2                                                                             0x501ea8UL //Access:WB_R DataWidth:0x28   // Statistics for the number of cycles that the TC is XOFFed.
+#define NIG_REG_LB_XOFF_CYC_TC_2_SIZE                                                                        2
+#define NIG_REG_LB_XOFF_CYC_TC_3                                                                             0x501eb0UL //Access:WB_R DataWidth:0x28   // Statistics for the number of cycles that the TC is XOFFed.
+#define NIG_REG_LB_XOFF_CYC_TC_3_SIZE                                                                        2
+#define NIG_REG_LB_XOFF_CYC_TC_4                                                                             0x501eb8UL //Access:WB_R DataWidth:0x28   // Statistics for the number of cycles that the TC is XOFFed.
+#define NIG_REG_LB_XOFF_CYC_TC_4_SIZE                                                                        2
+#define NIG_REG_LB_XOFF_CYC_TC_5                                                                             0x501ec0UL //Access:WB_R DataWidth:0x28   // Statistics for the number of cycles that the TC is XOFFed.
+#define NIG_REG_LB_XOFF_CYC_TC_5_SIZE                                                                        2
+#define NIG_REG_LB_XOFF_CYC_TC_6                                                                             0x501ec8UL //Access:WB_R DataWidth:0x28   // Statistics for the number of cycles that the TC is XOFFed.
+#define NIG_REG_LB_XOFF_CYC_TC_6_SIZE                                                                        2
+#define NIG_REG_LB_XOFF_CYC_TC_7                                                                             0x501ed0UL //Access:WB_R DataWidth:0x28   // Statistics for the number of cycles that the TC is XOFFed.
+#define NIG_REG_LB_XOFF_CYC_TC_7_SIZE                                                                        2
+#define NIG_REG_STAT_RX_BMB_OCTET                                                                            0x501ed8UL //Access:RC   DataWidth:0x20   // Number of RX octets to be forwarded to BMB.
+#define NIG_REG_STAT_RX_BMB_PACKET                                                                           0x501edcUL //Access:RC   DataWidth:0x20   // Number of RX packets to be forwarded to BMB.
+#define NIG_REG_STAT_RX_BMB_PACKET_TRUNCATE                                                                  0x501ee0UL //Access:RC   DataWidth:0x20   // Number of RX packets to be forwarded to BMB that got truncated due to BMB full backpressure.
+#define NIG_REG_STAT_RX_BMB_PACKET_DISCARD                                                                   0x501ee4UL //Access:RC   DataWidth:0x20   // Number of RX packets to be forwarded to BMB that got discarded due to BMB full backpressure.
+#define NIG_REG_STAT_TX_H2BMB_OCTET                                                                          0x501ee8UL //Access:RC   DataWidth:0x20   // Number of TX octets to be forwarded to BMB.
+#define NIG_REG_STAT_TX_H2BMB_PACKET                                                                         0x501eecUL //Access:RC   DataWidth:0x20   // Number of TX packets to be forwarded to BMB.
+#define NIG_REG_STAT_TX_H2BMB_PACKET_TRUNCATE                                                                0x501ef0UL //Access:RC   DataWidth:0x20   // Number of TX packets to be forwarded to BMB that got truncated due to BMB full backpressure.
+#define NIG_REG_STAT_TX_H2BMB_PACKET_DISCARD                                                                 0x501ef4UL //Access:RC   DataWidth:0x20   // Number of TX packets to be forwarded to BMB that got discarded due to BMB full backpressure.
+#define NIG_REG_STAT_TX_BMB_PACKET                                                                           0x501ef8UL //Access:RC   DataWidth:0x20   // Statistics for the number of packets received from BMB for sending to the network.
+#define NIG_REG_STAT_LB_BMB_PACKET                                                                           0x501efcUL //Access:RC   DataWidth:0x20   // Number of packets received from BMB for forwarding to the host.
+#define NIG_REG_STAT_LB_BMB_PACKET_TRUNCATE                                                                  0x501f00UL //Access:RC   DataWidth:0x20   // Number of packets from BMB to be forwarded to the host that got truncated due to BRB LB per-TC full backpressure.
+#define NIG_REG_STAT_LB_BMB_PACKET_DISCARD                                                                   0x501f04UL //Access:RC   DataWidth:0x20   // Number of packets from BMB to be forwarded to the host that got dropped due to BRB LB per-TC full backpressure.
+#define NIG_REG_TX_ZERO_PAD_EN                                                                               0x501f08UL //Access:RW   DataWidth:0x1    // Zero-padding enable for TX packets.  Set this bit to enable the padding of short packets to 60B.
+#define NIG_REG_TX_EDPM_CTRL                                                                                 0x501f0cUL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN                                                                    (0x1<<0) // Enable EDPM for the port.
+  #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN_SHIFT                                                              0
+  #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN                                                                 (0xff<<1) // TC enable for EDPM.  There is one bit per TC.  This is used in the generation of the EDPM enable output to DORQ.
+  #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN_SHIFT                                                           1
+#define NIG_REG_TX_MIN_CYC_THRESHOLD                                                                         0x501f10UL //Access:RW   DataWidth:0x6    // Minimum cycle threshold register for specifying the minimum number of cycles of ready-to-transmit data remaining  below which ETS arbiter for the transmit path should start selecting the next packet.  This value should cover the BTB access latency and arbitration time to provide back-to-back packets as needed to sustain the data rate, but should be as low as possilbe to minimize delay in responding to a flow control request.
+#define NIG_REG_TX_BTB_FIFO_ALM_FULL_THR                                                                     0x501f14UL //Access:RW   DataWidth:0x5    // Almost full threshold for TX BTB FIFO.
+#define NIG_REG_TX_GNT_FIFO_ALM_FULL_THR                                                                     0x501f18UL //Access:RW   DataWidth:0x4    // Almost full threshold for TX GNT FIFO.
+#define NIG_REG_TX_LB_GLBRATELIMIT_CTRL                                                                      0x501f1cUL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_EN                                              (0x1<<0) // Enable bit for the global rate limiter to be used in pacing TX and LB traffic of the same port.  Defaults to enabled rate limit of 48Gbps.
+  #define NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_EN_SHIFT                                        0
+  #define NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_BASE_TYPE                                       (0x3<<1) // Select between byte, cycle, and packet level of fairness for the global rate limiter.  0 selects packet level.  1 selects byte level.  2 selects cycle level.  Value configurations should match the type of fairness selected here.
+  #define NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_BASE_TYPE_SHIFT                                 1
+#define NIG_REG_TX_LB_GLBRATELIMIT_INC_PERIOD                                                                0x501f20UL //Access:RW   DataWidth:0x20   // Increment PERIOD for the global rate limiter - in term of 25MHz clock cycles.  Note that this register should be programmed only while this rate limiter is disabled.
+#define NIG_REG_TX_LB_GLBRATELIMIT_INC_VALUE                                                                 0x501f24UL //Access:RW   DataWidth:0x20   // Increment VALUE for the global rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration). This is the amount of data allowed in the configured increment period *inc_period to get the desired data rate.
+#define NIG_REG_TX_LB_GLBRATELIMIT_MAX_VALUE                                                                 0x501f28UL //Access:RW   DataWidth:0x20   // Upper bound VALUE for the global rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration).
+#define NIG_REG_TX_LB_GLBRATELIMIT_IFG_SIZE                                                                  0x501f2cUL //Access:RW   DataWidth:0x8    // Value to be added to the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.
+#define NIG_REG_TX_ARB_EN                                                                                    0x501f30UL //Access:RW   DataWidth:0x1    // TX ETS arbitration enable.
+#define NIG_REG_TX_ARB_CLIENT_IS_STRICT                                                                      0x501f34UL //Access:RW   DataWidth:0xc    // Specify whether the client competes directly in the strict priority arbiter.  The bits are mapped according to client ID  (client IDs are defined in *_arb_priority_client): 0-DORQ; 1-management; 2-debug traffic from this port; 3-debug traffic from other port; 4-TC0 traffic; 5-TC1 traffic; 6-TC2 traffic; 7-TC3 traffic; 8-TC4 traffic; 9-TC5 traffic; 10-TC6 traffic; 11-TC7 traffic.  Default value is set to enable strict priorities for all clients.
+#define NIG_REG_TX_ARB_CLIENT_IS_SUBJECT2WFQ                                                                 0x501f38UL //Access:RW   DataWidth:0xc    // Specify whether the client is subject to WFQ credit blocking.  The bits are mapped according to client ID (client IDs are defined in *_arb_priority_client): 0-DORQ; 1-management; 2-debug traffic from this port; 3-debug traffic from other port; 4-TC0 traffic; 5-TC1 traffic; 6-TC2 traffic; 7-TC3 traffic; 8-TC4 traffic; 9-TC5 traffic; 10-TC6 traffic; 11-TC7 traffic.  Default value is 0 for not using WFQ credit blocking.
+#define NIG_REG_TX_ARB_NUM_STRICT_ARB_SLOTS                                                                  0x501f3cUL //Access:RW   DataWidth:0xc    // Specify the number of strict priority arbitration slots between two round-robin arbitration slots to avoid starvation.  A value of 0 means no strict priority cycles - the strict priority with anti-starvation arbiter becomes a round-robin arbiter.
+#define NIG_REG_TX_ARB_PRIORITY_CLIENT                                                                       0x501f40UL //Access:WB   DataWidth:0x30   // Specify the client number to be assigned to each priority of the strict priority arbiter.  Priority 0 is the highest priority.  Bits [3:0] are for priority 0 client; bits [47:44] are for priority 11 client.  The clients are assigned the following IDs:  0-DORQ; 1-management; 2-debug traffic from this port; 3-debug traffic from other port; 4-TC0 traffic; 5-TC1 traffic; 6-TC2 traffic; 7-TC3 traffic; 8-TC4 traffic; 9-TC5 traffic; 10-TC6 traffic; 11-TC7 traffic.  The reset value is set to 0x456789ab_1320.
+#define NIG_REG_TX_ARB_PRIORITY_CLIENT_SIZE                                                                  2
+#define NIG_REG_TX_ARB_BURST_MODE                                                                            0x501f48UL //Access:RW   DataWidth:0x2    // Burst mode enables.  Set these bits to have the round-robin arbiter stays on the winning input instead of moving to the next one.  Bit 0 is for the main round-robin arbiter.  Bit 1 is for the round-robin arbiter within the strict priority with anti-starvation feature.
+#define NIG_REG_TX_ARB_IFG_SIZE                                                                              0x501f4cUL //Access:RW   DataWidth:0x8    // Specify the number of bytes to be deducted from the client credit register at the time of grant in additional to the normal packet credit costs.  This may include the IPG and FCS field.
+#define NIG_REG_TX_ARB_PSEUDO_RR_EN                                                                          0x501f50UL //Access:RW   DataWidth:0x1    // Enable bit for the pseudo-random arbitration mode.
+#define NIG_REG_TX_ARB_DBG_CLIENT_DISABLE                                                                    0x501f54UL //Access:RW   DataWidth:0x1    // Set this bit to disable debug traffic at the inputs to the ETS arbiter.
+#define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_0                                                                  0x501f58UL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 0 is allowed to reach.
+#define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_1                                                                  0x501f5cUL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 1 is allowed to reach.
+#define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_2                                                                  0x501f60UL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 2 is allowed to reach.
+#define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_3                                                                  0x501f64UL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 3 is allowed to reach.
+#define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_4                                                                  0x501f68UL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 4 is allowed to reach.
+#define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_5                                                                  0x501f6cUL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 5 is allowed to reach.
+#define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_6                                                                  0x501f70UL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 6 is allowed to reach.
+#define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_7                                                                  0x501f74UL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 7 is allowed to reach.
+#define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_8                                                                  0x501f78UL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 8 is allowed to reach.
+#define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_9                                                                  0x501f7cUL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 9 is allowed to reach.
+#define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_10                                                                 0x501f80UL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 10 is allowed to reach.
+#define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_11                                                                 0x501f84UL //Access:RW   DataWidth:0x20   // Specify the upper bound that credit register 11 is allowed to reach.
+#define NIG_REG_TX_ARB_CREDIT_WEIGHT_0                                                                       0x501f88UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 0 when it is time to increment.
+#define NIG_REG_TX_ARB_CREDIT_WEIGHT_1                                                                       0x501f8cUL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 1 when it is time to increment.
+#define NIG_REG_TX_ARB_CREDIT_WEIGHT_2                                                                       0x501f90UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 2 when it is time to increment.
+#define NIG_REG_TX_ARB_CREDIT_WEIGHT_3                                                                       0x501f94UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 3 when it is time to increment.
+#define NIG_REG_TX_ARB_CREDIT_WEIGHT_4                                                                       0x501f98UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 4 when it is time to increment.
+#define NIG_REG_TX_ARB_CREDIT_WEIGHT_5                                                                       0x501f9cUL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 5 when it is time to increment.
+#define NIG_REG_TX_ARB_CREDIT_WEIGHT_6                                                                       0x501fa0UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 6 when it is time to increment.
+#define NIG_REG_TX_ARB_CREDIT_WEIGHT_7                                                                       0x501fa4UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 7 when it is time to increment.
+#define NIG_REG_TX_ARB_CREDIT_WEIGHT_8                                                                       0x501fa8UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 8 when it is time to increment.
+#define NIG_REG_TX_ARB_CREDIT_WEIGHT_9                                                                       0x501facUL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 9 when it is time to increment.
+#define NIG_REG_TX_ARB_CREDIT_WEIGHT_10                                                                      0x501fb0UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 10 when it is time to increment.
+#define NIG_REG_TX_ARB_CREDIT_WEIGHT_11                                                                      0x501fb4UL //Access:RW   DataWidth:0x20   // Specify the weight (in bytes) to be added to credit register 11 when it is time to increment.
+#define NIG_REG_TX_ARB_CURRENT_CREDIT_0                                                                      0x501fb8UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in TX arbiter credit register 0.
+#define NIG_REG_TX_ARB_CURRENT_CREDIT_1                                                                      0x501fbcUL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in TX arbiter credit register 1.
+#define NIG_REG_TX_ARB_CURRENT_CREDIT_2                                                                      0x501fc0UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in TX arbiter credit register 2.
+#define NIG_REG_TX_ARB_CURRENT_CREDIT_3                                                                      0x501fc4UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in TX arbiter credit register 3.
+#define NIG_REG_TX_ARB_CURRENT_CREDIT_4                                                                      0x501fc8UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in TX arbiter credit register 4.
+#define NIG_REG_TX_ARB_CURRENT_CREDIT_5                                                                      0x501fccUL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in TX arbiter credit register 5.
+#define NIG_REG_TX_ARB_CURRENT_CREDIT_6                                                                      0x501fd0UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in TX arbiter credit register 6.
+#define NIG_REG_TX_ARB_CURRENT_CREDIT_7                                                                      0x501fd4UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in TX arbiter credit register 7.
+#define NIG_REG_TX_ARB_CURRENT_CREDIT_8                                                                      0x501fd8UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in TX arbiter credit register 8.
+#define NIG_REG_TX_ARB_CURRENT_CREDIT_9                                                                      0x501fdcUL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in TX arbiter credit register 9.
+#define NIG_REG_TX_ARB_CURRENT_CREDIT_10                                                                     0x501fe0UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in TX arbiter credit register 10.
+#define NIG_REG_TX_ARB_CURRENT_CREDIT_11                                                                     0x501fe4UL //Access:R    DataWidth:0x20   // Current upper 32 bits of the 33-bit value in TX arbiter credit register 11.
+#define NIG_REG_TX_LLH_NCSI_MCP_MASK                                                                         0x501fe8UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_BRCST                                                                 (0x1<<0) // Mask bit for forwarding broadcast (MAC destination address of all 1's) packets to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_BRCST_SHIFT                                                           0
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ALLMLCST                                                              (0x1<<1) // Mask bit for forwarding multicast (MAC destination address[40]==1 and it is not a broadcast packet) packets to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ALLMLCST_SHIFT                                                        1
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IPV4MLCST                                                             (0x1<<2) // Obsolete.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IPV4MLCST_SHIFT                                                       2
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IPV6_MLCST                                                            (0x1<<3) // Mask bit for forwarding IPv6 multicast (MAC destination address [47:32]==0x3333) packets to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IPV6_MLCST_SHIFT                                                      3
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_UNCST                                                                 (0x1<<4) // Mask bit for forwarding unicast (MAC destination address[40]==0) packets to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_UNCST_SHIFT                                                           4
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC0                                                                  (0x1<<5) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_0 to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC0_SHIFT                                                            5
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC1                                                                  (0x1<<6) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_1 to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC1_SHIFT                                                            6
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC2                                                                  (0x1<<7) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_2 to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC2_SHIFT                                                            7
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC3                                                                  (0x1<<8) // Mask bit for forwarding packets with the MAC destination address  mtching *llh*_dest_mac_3 to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC3_SHIFT                                                            8
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC4                                                                  (0x1<<9) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_4 to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC4_SHIFT                                                            9
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC5                                                                  (0x1<<10) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_5 to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC5_SHIFT                                                            10
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ETHERTYPE0                                                            (0x1<<11) // Mask bit for forwarding packets with Ethertype matching *llh_ethertype0 to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ETHERTYPE0_SHIFT                                                      11
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ETHERTYPE1                                                            (0x1<<12) // Mask bit for forwarding packets with Ethertype matching *llh_ethertype1 to be forwarded to the host.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ETHERTYPE1_SHIFT                                                      12
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ARP                                                                   (0x1<<13) // Mask bit for forwarding packets with Ethertype of 0x0806 and bcast address to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ARP_SHIFT                                                             13
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IP0                                                                   (0x1<<14) // Mask bit for forwarding packets with the IP destination address  matching *llh*_dest_ip_0 and the IP version matching *llh*_ipv4_ipv6_0 to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IP0_SHIFT                                                             14
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IP1                                                                   (0x1<<15) // Mask bit for forwarding packets with the IP destination address  matching *llh*_dest_ip_1 and the IP version matching *llh*_ipv4_ipv6_1 to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IP1_SHIFT                                                             15
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IP2                                                                   (0x1<<16) // Mask bit for forwarding packets with the IP destination address  matching *llh*_dest_ip_2 and the IP version matching *llh*_ipv4_ipv6_2 to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IP2_SHIFT                                                             16
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_TCP0                                                                  (0x1<<17) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_0 to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_TCP0_SHIFT                                                            17
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_TCP1                                                                  (0x1<<18) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_1 to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_TCP1_SHIFT                                                            18
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_TCP2                                                                  (0x1<<19) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_2 to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_TCP2_SHIFT                                                            19
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_NTBS_T_DST                                                            (0x1<<20) // Obsolete.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_NTBS_T_DST_SHIFT                                                      20
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_NTBS_T_SRC                                                            (0x1<<21) // Obsolete.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_NTBS_T_SRC_SHIFT                                                      21
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_UDP0                                                                  (0x1<<22) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_0 to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_UDP0_SHIFT                                                            22
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_UDP1                                                                  (0x1<<23) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_1 to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_UDP1_SHIFT                                                            23
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_UDP2                                                                  (0x1<<24) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_2 to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_UDP2_SHIFT                                                            24
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_RMCP                                                                  (0x1<<25) // Mask bit for forwarding packets with RMCP UDP ports (0x26f and 0x298) to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_RMCP_SHIFT                                                            25
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_NTBS_U_DST                                                            (0x1<<26) // Mask bit for forwarding packets with NetBIOS UDP destination port 137/138/139 to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_NTBS_U_DST_SHIFT                                                      26
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_NTBS_U_SRC                                                            (0x1<<27) // Obsolete.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_NTBS_U_SRC_SHIFT                                                      27
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_DHCP                                                                  (0x1<<28) // Obsolete.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_DHCP_SHIFT                                                            28
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ICMPV6_NA                                                             (0x1<<29) // Mask bit for forwarding ICMPv6 Neighbor Advertisement packets (ICMP over IPv6 with ICMP type = 136 and dst_mac = 0x33:33:00:00:00:01) to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ICMPV6_NA_SHIFT                                                       29
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ICMPV6_RA                                                             (0x1<<30) // Mask bit for forwarding ICMPv6 Router Advertisement packets (ICMP over IPv6 with ICMP type= 134 and dst_mac = 0x33:33:00:00:00:01) to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ICMPV6_RA_SHIFT                                                       30
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ICMPV6                                                                (0x1<<31) // Mask bit for forwarding ICMPv6 packets to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ICMPV6_SHIFT                                                          31
+#define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN                                                                   0x501fecUL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_ANY                                                             (0x1<<0) // Mask bit for forwarding packets with inner VLAN present to the network.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_ANY_SHIFT                                                       0
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_NONE                                                            (0x1<<1) // Mask bit for forwarding packets with no inner VLAN to the network.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_NONE_SHIFT                                                      1
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_ID0                                                             (0x1<<2) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_0 to the network.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_ID0_SHIFT                                                       2
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_ID1                                                             (0x1<<3) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_1 to the network.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_ID1_SHIFT                                                       3
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_ID2                                                             (0x1<<4) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_2 to the network.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_ID2_SHIFT                                                       4
+#define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK                                                                 0x501ff0UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_BRCST                                                         (0x1<<0) // Mask bit for not forwarding broadcast (MAC destination address of all 1's) packets to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_BRCST_SHIFT                                                   0
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ALLMLCST                                                      (0x1<<1) // Mask bit for not forwarding multicast (MAC destination address[40]==1 and it is not a broadcast packet) packets to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ALLMLCST_SHIFT                                                1
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IPV4MLCST                                                     (0x1<<2) // Obsolete.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IPV4MLCST_SHIFT                                               2
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IPV6_MLCST                                                    (0x1<<3) // Mask bit for not forwarding IPv6 multicast (MAC destination address [47:32]==0x3333) packets to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IPV6_MLCST_SHIFT                                              3
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_UNCST                                                         (0x1<<4) // Mask bit for not forwarding unicast (MAC destination address[40]==0) packets to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_UNCST_SHIFT                                                   4
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC0                                                          (0x1<<5) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_0 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC0_SHIFT                                                    5
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC1                                                          (0x1<<6) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_1 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC1_SHIFT                                                    6
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC2                                                          (0x1<<7) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_2 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC2_SHIFT                                                    7
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC3                                                          (0x1<<8) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_3 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC3_SHIFT                                                    8
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC4                                                          (0x1<<9) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_4 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC4_SHIFT                                                    9
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC5                                                          (0x1<<10) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_5 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC5_SHIFT                                                    10
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ETHERTYPE0                                                    (0x1<<11) // Mask bit for not forwarding packets with Ethertype matching *llh_ethertype0 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ETHERTYPE0_SHIFT                                              11
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ETHERTYPE1                                                    (0x1<<12) // Mask bit for not forwarding packets with Ethertype matching *llh_ethertype1 to be forwarded to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ETHERTYPE1_SHIFT                                              12
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ARP                                                           (0x1<<13) // Mask bit for not forwarding packets with Ethertype of 0x0806 and bcast address to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ARP_SHIFT                                                     13
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IP0                                                           (0x1<<14) // Mask bit for not forwarding packets with the IP destination address  matching *llh*_dest_ip_0 and the IP version matching *llh*_ipv4_ipv6_0 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IP0_SHIFT                                                     14
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IP1                                                           (0x1<<15) // Mask bit for not forwarding packets with the IP destination address  matching *llh*_dest_ip_1 and the IP version matching *llh*_ipv4_ipv6_1 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IP1_SHIFT                                                     15
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IP2                                                           (0x1<<16) // Mask bit for not forwarding packets with the IP destination address  matching *llh*_dest_ip_2 and the IP version matching *llh*_ipv4_ipv6_2 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IP2_SHIFT                                                     16
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_TCP0                                                          (0x1<<17) // Mask bit for not forwarding packets with the TCP destination port matching *llh*_dest_tcp_0 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_TCP0_SHIFT                                                    17
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_TCP1                                                          (0x1<<18) // Mask bit for not forwarding packets with the TCP destination port matching *llh*_dest_tcp_1 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_TCP1_SHIFT                                                    18
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_TCP2                                                          (0x1<<19) // Mask bit for not forwarding packets with the TCP destination port matching *llh*_dest_tcp_2 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_TCP2_SHIFT                                                    19
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_NTBS_T_DST                                                    (0x1<<20) // Obsolete.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_NTBS_T_DST_SHIFT                                              20
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_NTBS_T_SRC                                                    (0x1<<21) // Obsolete.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_NTBS_T_SRC_SHIFT                                              21
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_UDP0                                                          (0x1<<22) // Mask bit for not forwarding packets with the UDP destination port matching *llh*_dest_udp_0 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_UDP0_SHIFT                                                    22
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_UDP1                                                          (0x1<<23) // Mask bit for not forwarding packets with the UDP destination port matching *llh*_dest_udp_1 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_UDP1_SHIFT                                                    23
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_UDP2                                                          (0x1<<24) // Mask bit for not forwarding packets with the UDP destination port matching *llh*_dest_udp_2 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_UDP2_SHIFT                                                    24
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_RMCP                                                          (0x1<<25) // Mask bit for not forwarding packets with RMCP UDP ports (0x26f and 0x298) to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_RMCP_SHIFT                                                    25
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_NTBS_U_DST                                                    (0x1<<26) // Mask bit for not forwarding packets with NetBIOS UDP destination port 137/138/139 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_NTBS_U_DST_SHIFT                                              26
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_NTBS_U_SRC                                                    (0x1<<27) // Obsolete.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_NTBS_U_SRC_SHIFT                                              27
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP                                                          (0x1<<28) // Obsolete.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_SHIFT                                                    28
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ICMPV6_NA                                                     (0x1<<29) // Mask bit for not forwarding ICMPv6 Neighbor Advertisement packets (ICMP over IPv6 with ICMP type = 136 and dst_mac = 0x33:33:00:00:00:01) to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ICMPV6_NA_SHIFT                                               29
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ICMPV6_RA                                                     (0x1<<30) // Mask bit for not forwarding ICMPv6 Router Advertisement packets (ICMP over IPv6 with ICMP type = 134 and dst_mac = 0x33:33:00:00:00:01) to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ICMPV6_RA_SHIFT                                               30
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ICMPV6                                                        (0x1<<31) // Mask bit for not forwarding ICMPv6 packets to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ICMPV6_SHIFT                                                  31
+#define NIG_REG_TX_LLH_NCSI_NTWK_MASK                                                                        0x501ff4UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_BRCST                                                                (0x1<<0) // Mask bit for forwarding broadcast (MAC destination address of all 1's) packets to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_BRCST_SHIFT                                                          0
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ALLMLCST                                                             (0x1<<1) // Mask bit for forwarding multicast (MAC destination address[40]==1 and it is a broadcast packet) packets to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ALLMLCST_SHIFT                                                       1
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IPV4MLCST                                                            (0x1<<2) // Obsolete.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IPV4MLCST_SHIFT                                                      2
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IPV6_MLCST                                                           (0x1<<3) // Mask bit for forwarding IPv6 multicast (MAC destination address [47:32]==0x3333) packets to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IPV6_MLCST_SHIFT                                                     3
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_UNCST                                                                (0x1<<4) // Mask bit for forwarding unicast (MAC destination address[40]==0) packets to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_UNCST_SHIFT                                                          4
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC0                                                                 (0x1<<5) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_0 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC0_SHIFT                                                           5
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC1                                                                 (0x1<<6) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_1 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC1_SHIFT                                                           6
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC2                                                                 (0x1<<7) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_2 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC2_SHIFT                                                           7
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC3                                                                 (0x1<<8) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_3 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC3_SHIFT                                                           8
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC4                                                                 (0x1<<9) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_4 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC4_SHIFT                                                           9
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC5                                                                 (0x1<<10) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_5 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC5_SHIFT                                                           10
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ETHERTYPE0                                                           (0x1<<11) // Mask bit for forwarding packets with Ethertype matching *llh_ethertype0 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ETHERTYPE0_SHIFT                                                     11
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ETHERTYPE1                                                           (0x1<<12) // Mask bit for forwarding packets with Ethertype matching *llh_ethertype1 to be forwarded to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ETHERTYPE1_SHIFT                                                     12
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ARP                                                                  (0x1<<13) // Mask bit for forwarding packets with Ethertype of 0x0806 and bcast address to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ARP_SHIFT                                                            13
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IP0                                                                  (0x1<<14) // Mask bit for forwarding packets with the IP destination address  matching *llh*_dest_ip_0 and the IP version matching *llh*_ipv4_ipv6_0 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IP0_SHIFT                                                            14
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IP1                                                                  (0x1<<15) // Mask bit for forwarding packets with the IP destination address  matching *llh*_dest_ip_1 and the IP version matching *llh*_ipv4_ipv6_1 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IP1_SHIFT                                                            15
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IP2                                                                  (0x1<<16) // Mask bit for forwarding packets with the IP destination address  matching *llh*_dest_ip_2 and the IP version matching *llh*_ipv4_ipv6_2 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IP2_SHIFT                                                            16
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_TCP0                                                                 (0x1<<17) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_0 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_TCP0_SHIFT                                                           17
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_TCP1                                                                 (0x1<<18) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_1 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_TCP1_SHIFT                                                           18
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_TCP2                                                                 (0x1<<19) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_2 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_TCP2_SHIFT                                                           19
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_NTBS_T_DST                                                           (0x1<<20) // Obsolete.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_NTBS_T_DST_SHIFT                                                     20
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_NTBS_T_SRC                                                           (0x1<<21) // Obsolete.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_NTBS_T_SRC_SHIFT                                                     21
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_UDP0                                                                 (0x1<<22) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_0 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_UDP0_SHIFT                                                           22
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_UDP1                                                                 (0x1<<23) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_1 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_UDP1_SHIFT                                                           23
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_UDP2                                                                 (0x1<<24) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_2 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_UDP2_SHIFT                                                           24
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_RMCP                                                                 (0x1<<25) // Mask bit for forwarding packets with RMCP UDP ports (0x26f and 0x298) to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_RMCP_SHIFT                                                           25
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_NTBS_U_DST                                                           (0x1<<26) // Mask bit for forwarding packets with NetBIOS UDP destination port 137/138/139 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_NTBS_U_DST_SHIFT                                                     26
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_NTBS_U_SRC                                                           (0x1<<27) // Obsolete.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_NTBS_U_SRC_SHIFT                                                     27
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_DHCP                                                                 (0x1<<28) // Obsolete.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_DHCP_SHIFT                                                           28
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ICMPV6_NA                                                            (0x1<<29) // Mask bit for forwarding ICMPv6 Neighbor Advertisement packets (ICMP over IPv6 with ICMP type = 136 and dst_mac = 0x33:33:00:00:00:01) to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ICMPV6_NA_SHIFT                                                      29
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ICMPV6_RA                                                            (0x1<<30) // Mask bit for forwarding ICMPv6 Router Advertisement packets (ICMP over IPv6 with ICMP type = 134 and dst_mac = 0x33:33:00:00:00:01) to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ICMPV6_RA_SHIFT                                                      30
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ICMPV6                                                               (0x1<<31) // Mask bit for forwarding ICMPv6 packets to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ICMPV6_SHIFT                                                         31
+#define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN                                                                  0x501ff8UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_ANY                                                            (0x1<<0) // Mask bit for forwarding packets with inner VLAN present to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_ANY_SHIFT                                                      0
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_NONE                                                           (0x1<<1) // Mask bit for forwarding packets with no inner VLAN to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_NONE_SHIFT                                                     1
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_ID0                                                            (0x1<<2) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_0 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_ID0_SHIFT                                                      2
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_ID1                                                            (0x1<<3) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_1 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_ID1_SHIFT                                                      3
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_ID2                                                            (0x1<<4) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_2 to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_ID2_SHIFT                                                      4
+#define NIG_REG_TX_BTB_FIFO_EMPTY                                                                            0x501ffcUL //Access:R    DataWidth:0x1    // TX BTB FIFO empty status.
+#define NIG_REG_TX_BTB_FIFO_FULL                                                                             0x502000UL //Access:R    DataWidth:0x1    // TX BTB FIFO full status.
+#define NIG_REG_TX_LLH_DFIFO_ALM_FULL_THR                                                                    0x502004UL //Access:RW   DataWidth:0x6    // TX LLH Data FIFO almost full threshold.
+#define NIG_REG_TX_LLH_HFIFO_ALM_FULL_THR                                                                    0x502008UL //Access:RW   DataWidth:0x5    // TX LLH header FIFO almost full threshold.
+#define NIG_REG_TX_LLH_RFIFO_ALM_FULL_THR                                                                    0x50200cUL //Access:RW   DataWidth:0x4    // TX LLH result FIFO almost full threshold.
+#define NIG_REG_TX_LLH_DFIFO_EMPTY                                                                           0x502010UL //Access:R    DataWidth:0x1    // TX LLH Data FIFO is empty.
+#define NIG_REG_TX_LLH_DFIFO_ALM_FULL                                                                        0x502014UL //Access:R    DataWidth:0x1    // TX LLH Data FIFO almost full.
+#define NIG_REG_TX_LLH_DFIFO_FULL                                                                            0x502018UL //Access:R    DataWidth:0x1    // TX LLH Data FIFO is full.
+#define NIG_REG_TX_LLH_HFIFO_EMPTY                                                                           0x50201cUL //Access:R    DataWidth:0x1    // TX LLH header FIFO is empty.
+#define NIG_REG_TX_LLH_HFIFO_ALM_FULL                                                                        0x502020UL //Access:R    DataWidth:0x1    // TX LLH header FIFO almost full.
+#define NIG_REG_TX_LLH_HFIFO_FULL                                                                            0x502024UL //Access:R    DataWidth:0x1    // TX LLH header FIFO is full.
+#define NIG_REG_TX_LLH_RFIFO_EMPTY                                                                           0x502028UL //Access:R    DataWidth:0x1    // TX LLH result FIFO is empty.
+#define NIG_REG_TX_LLH_RFIFO_ALM_FULL                                                                        0x50202cUL //Access:R    DataWidth:0x1    // TX LLH result FIFO almost full.
+#define NIG_REG_TX_LLH_RFIFO_FULL                                                                            0x502030UL //Access:R    DataWidth:0x1    // TX LLH result FIFO is full.
+#define NIG_REG_TX_GNT_FIFO_EMPTY                                                                            0x502034UL //Access:R    DataWidth:0x1    // TX GNT FIFO empty status.
+#define NIG_REG_TX_GNT_FIFO_FULL                                                                             0x502038UL //Access:R    DataWidth:0x1    // TX GNT FIFO full status.
+#define NIG_REG_MNG_OUTER_TAG0_0_BB                                                                          0x50203cUL //Access:RW   DataWidth:0x20   // Value of outer tag to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.
+#define NIG_REG_MNG_OUTER_TAG0_1_BB                                                                          0x502040UL //Access:RW   DataWidth:0x20   // Value of outer tag to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.
+#define NIG_REG_MNG_OUTER_TAG1_0_BB                                                                          0x502044UL //Access:RW   DataWidth:0x20   // Value of outer tag to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.
+#define NIG_REG_MNG_OUTER_TAG1_1_BB                                                                          0x502048UL //Access:RW   DataWidth:0x20   // Value of outer tag to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.
+#define NIG_REG_MNG_INNER_VLAN_TAG0_BB                                                                       0x50204cUL //Access:RW   DataWidth:0x10   // Value of inner VLAN tag to be used in tag insertion/override for management packets.  This field consists of {3-bit priority, 1-bit drop eligible, 12-bit VLAN ID}.
+#define NIG_REG_MNG_INNER_VLAN_TAG1_BB                                                                       0x502050UL //Access:RW   DataWidth:0x10   // Value of inner VLAN tag to be used in tag insertion/override for management packets.  This field consists of {3-bit priority, 1-bit drop eligible, 12-bit VLAN ID}.
+#define NIG_REG_MNG_PROP_HDR0_0_BB                                                                           0x502054UL //Access:RW   DataWidth:0x20   // Value of proprietary header to be inserted into the management packets.  The header value should have the MSB aligned with the MSB of this register.
+#define NIG_REG_MNG_PROP_HDR0_1_BB                                                                           0x502058UL //Access:RW   DataWidth:0x20   // Value of proprietary header to be inserted into the management packets.  The header value should have the MSB aligned with the MSB of this register.
+#define NIG_REG_MNG_PROP_HDR0_2_BB                                                                           0x50205cUL //Access:RW   DataWidth:0x20   // Value of proprietary header to be inserted into the management packets.  The header value should have the MSB aligned with the MSB of this register.
+#define NIG_REG_MNG_PROP_HDR0_3_BB                                                                           0x502060UL //Access:RW   DataWidth:0x20   // Value of proprietary header to be inserted into the management packets.  The header value should have the MSB aligned with the MSB of this register.
+#define NIG_REG_MNG_PROP_HDR0_4_BB                                                                           0x502064UL //Access:RW   DataWidth:0x20   // Value of proprietary header to be inserted into the management packets.  The header value should have the MSB aligned with the MSB of this register.
+#define NIG_REG_MNG_PROP_HDR0_5_BB                                                                           0x502068UL //Access:RW   DataWidth:0x20   // Value of proprietary header to be inserted into the management packets.  The header value should have the MSB aligned with the MSB of this register.
+#define NIG_REG_MNG_PROP_HDR0_6_BB                                                                           0x50206cUL //Access:RW   DataWidth:0x20   // Value of proprietary header to be inserted into the management packets.  The header value should have the MSB aligned with the MSB of this register.
+#define NIG_REG_MNG_PROP_HDR0_7_BB                                                                           0x502070UL //Access:RW   DataWidth:0x20   // Value of proprietary header to be inserted into the management packets.  The header value should have the MSB aligned with the MSB of this register.
+#define NIG_REG_MNG_PROP_HDR1_0_BB                                                                           0x502074UL //Access:RW   DataWidth:0x20   // Value of proprietary header to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.
+#define NIG_REG_MNG_PROP_HDR1_1_BB                                                                           0x502078UL //Access:RW   DataWidth:0x20   // Value of proprietary header to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.
+#define NIG_REG_MNG_PROP_HDR1_2_BB                                                                           0x50207cUL //Access:RW   DataWidth:0x20   // Value of proprietary header to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.
+#define NIG_REG_MNG_PROP_HDR1_3_BB                                                                           0x502080UL //Access:RW   DataWidth:0x20   // Value of proprietary header to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.
+#define NIG_REG_MNG_PROP_HDR1_4_BB                                                                           0x502084UL //Access:RW   DataWidth:0x20   // Value of proprietary header to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.
+#define NIG_REG_MNG_PROP_HDR1_5_BB                                                                           0x502088UL //Access:RW   DataWidth:0x20   // Value of proprietary header to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.
+#define NIG_REG_MNG_PROP_HDR1_6_BB                                                                           0x50208cUL //Access:RW   DataWidth:0x20   // Value of proprietary header to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.
+#define NIG_REG_MNG_PROP_HDR1_7_BB                                                                           0x502090UL //Access:RW   DataWidth:0x20   // Value of proprietary header to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.
+#define NIG_REG_MNG_TC                                                                                       0x502094UL //Access:RW   DataWidth:0x3    // TC to be used for management traffic.  This is used in the BMC-to-host path to BRB.  This is also used in the TX management path (when enabled by *tx_mng_tc_en).  Valid values are 0-7, since pure-LB TC cannot be used.
+#define NIG_REG_TX_MNG_TC_EN                                                                                 0x502098UL //Access:RW   DataWidth:0x1    // Enable the use of TC to control the flow of TX management traffic.  Set this bit to 1 to enable the use of *mng_tc configuration to select the TC to use to pause/drain management traffic sent to the network.
+#define NIG_REG_TX_HOST_MNG_ENABLE_BB                                                                        0x50209cUL //Access:RW   DataWidth:0x1    // Host-to-MCP path enable.  Set this bit to enable the routing of management packets from PBF interface toward MCP when the criteria for the MCP filters are met.  All packets from PBF are forwarded to the network when this bit is cleared.
+#define NIG_REG_TX_MNG_TIMESTAMP_PKT                                                                         0x5020a0UL //Access:RW   DataWidth:0x1    // Indicate to timestamp the packet from MCP to network when *_ptp_sw_txtsen is set.
+#define NIG_REG_BMB_PAUSE_NTWK_EN                                                                            0x5020a4UL //Access:RW   DataWidth:0x1    // Enable the usage of BMB WC pause inputs to OR with others for pausing the network peer.
+#define NIG_REG_BMB_PKT_LEN                                                                                  0x5020a8UL //Access:RW   DataWidth:0x9    // Maximum length of management packets, in term of the number of data cycles.
+#define NIG_REG_BMB_FIFO_ALM_FULL_THR                                                                        0x5020acUL //Access:RW   DataWidth:0x6    // Almost-full threshold for BMB FIFO.
+#define NIG_REG_TX_BMB_FIFO_EMPTY                                                                            0x5020b0UL //Access:R    DataWidth:0x1    // TX BMB FIFO empty status.
+#define NIG_REG_TX_BMB_FIFO_FULL                                                                             0x5020b4UL //Access:R    DataWidth:0x1    // TX BMB FIFO full status.
+#define NIG_REG_LB_BMB_FIFO_EMPTY                                                                            0x5020b8UL //Access:R    DataWidth:0x1    // LB BMB FIFO empty status.
+#define NIG_REG_LB_BMB_FIFO_FULL                                                                             0x5020bcUL //Access:R    DataWidth:0x1    // LB BMB FIFO full status.
+#define NIG_REG_DORQ_FIFO_ALM_FULL_THR                                                                       0x5020c0UL //Access:RW   DataWidth:0x7    // Almost-full threshold for DORQ FIFO.
+#define NIG_REG_DORQ_FIFO_EMPTY                                                                              0x5020c4UL //Access:R    DataWidth:0x1    // DORQ FIFO is empty..
+#define NIG_REG_DORQ_FIFO_FULL                                                                               0x5020c8UL //Access:R    DataWidth:0x1    // DORQ FIFO is full.
+#define NIG_REG_DORQ_PKT_WAIT_SIZE                                                                           0x5020ccUL //Access:RW   DataWidth:0x5    // This register specifies the received number of cycles of a DORQ packet, counting from SOP, before enqueuing the packet for transmission.  This is applicalbe to packets longer than this many cycles.  The valid values are 1 to 16.
+#define NIG_REG_DEBUG_PORT                                                                                   0x5020d0UL //Access:RW   DataWidth:0x2    // Port configuration for traffic from the debug interface. 0 - send debug traffic through port 0.  1 - send debug traffic through port 1. 2 - send debug traffic through port 2 (valid  in K2 mode only).  3 - send debug traffic through port 3 (valid  in K2 mode only).
+#define NIG_REG_DEBUG_PKT_LEN                                                                                0x5020d4UL //Access:RW   DataWidth:0x9    // Maximum length of debug packets, in term of the number of data cycles.
+#define NIG_REG_DEBUG_PKT_WAIT_SIZE                                                                          0x5020d8UL //Access:RW   DataWidth:0x8    // This register specifies the received number of cycles of a debug packet, counting from SOP, before enqueuing the packet for transmission.  This is applicalbe to packets longer than this many cycles.  The valid values are 1 to 128.
+#define NIG_REG_DEBUG_FIFO_ALM_FULL_THR                                                                      0x5020dcUL //Access:RW   DataWidth:0x8    // Almost-full threshold for debug traffic FIFO.
+#define NIG_REG_DEBUG_FIFO_EMPTY                                                                             0x5020e0UL //Access:R    DataWidth:0x1    // Debug traffic FIFO is empty..
+#define NIG_REG_DEBUG_FIFO_FULL                                                                              0x5020e4UL //Access:R    DataWidth:0x1    // Debug traffic FIFO is full.
+#define NIG_REG_DEBUG_PACKET                                                                                 0x502100UL //Access:WB_W DataWidth:0x108  // Data register for loading debug packet to RX LLH through RBC.  The bits are mapped as follow: [255:0] data; [260:256]eop_bvalid - the number of valid bytes in the last cycle (0=all bytes are valid); [261]eop - active on the last cycle of the packet; [262]sop - active on the first cycle of the packet; [263]error - indicates error in the packet.  This should be used only when there is no RX traffic from the MAC.
+#define NIG_REG_DEBUG_PACKET_SIZE                                                                            16
+#define NIG_REG_DBG_SELECT                                                                                   0x502140UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define NIG_REG_DBG_DWORD_ENABLE                                                                             0x502144UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define NIG_REG_DBG_SHIFT                                                                                    0x502148UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define NIG_REG_DBG_FORCE_VALID                                                                              0x50214cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define NIG_REG_DBG_FORCE_FRAME                                                                              0x502150UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define NIG_REG_DBG_OUT_DATA                                                                                 0x502160UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define NIG_REG_DBG_OUT_DATA_SIZE                                                                            8
+#define NIG_REG_DBG_OUT_VALID                                                                                0x502180UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define NIG_REG_DBG_OUT_FRAME                                                                                0x502184UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define NIG_REG_RX_FC_DBG_SELECT                                                                             0x502188UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define NIG_REG_RX_FC_DBG_DWORD_ENABLE                                                                       0x50218cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define NIG_REG_RX_FC_DBG_SHIFT                                                                              0x502190UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define NIG_REG_RX_FC_DBG_FORCE_VALID                                                                        0x502194UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define NIG_REG_RX_FC_DBG_FORCE_FRAME                                                                        0x502198UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define NIG_REG_TX_FC_DBG_SELECT                                                                             0x50219cUL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define NIG_REG_TX_FC_DBG_DWORD_ENABLE                                                                       0x5021a0UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define NIG_REG_TX_FC_DBG_SHIFT                                                                              0x5021a4UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define NIG_REG_TX_FC_DBG_FORCE_VALID                                                                        0x5021a8UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define NIG_REG_TX_FC_DBG_FORCE_FRAME                                                                        0x5021acUL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define NIG_REG_LB_FC_DBG_SELECT                                                                             0x5021b0UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define NIG_REG_LB_FC_DBG_DWORD_ENABLE                                                                       0x5021b4UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define NIG_REG_LB_FC_DBG_SHIFT                                                                              0x5021b8UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define NIG_REG_LB_FC_DBG_FORCE_VALID                                                                        0x5021bcUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define NIG_REG_LB_FC_DBG_FORCE_FRAME                                                                        0x5021c0UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define NIG_REG_RX_FC_DBG_SELECT_PLLH                                                                        0x5021c4UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define NIG_REG_RX_FC_DBG_DWORD_ENABLE_PLLH                                                                  0x5021c8UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define NIG_REG_RX_FC_DBG_SHIFT_PLLH                                                                         0x5021ccUL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define NIG_REG_RX_FC_DBG_FORCE_VALID_PLLH                                                                   0x5021d0UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define NIG_REG_RX_FC_DBG_FORCE_FRAME_PLLH                                                                   0x5021d4UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define NIG_REG_TX_FC_DBG_SELECT_PLLH                                                                        0x5021d8UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define NIG_REG_TX_FC_DBG_DWORD_ENABLE_PLLH                                                                  0x5021dcUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define NIG_REG_TX_FC_DBG_SHIFT_PLLH                                                                         0x5021e0UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define NIG_REG_TX_FC_DBG_FORCE_VALID_PLLH                                                                   0x5021e4UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define NIG_REG_TX_FC_DBG_FORCE_FRAME_PLLH                                                                   0x5021e8UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define NIG_REG_LB_FC_DBG_SELECT_PLLH                                                                        0x5021ecUL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define NIG_REG_LB_FC_DBG_DWORD_ENABLE_PLLH                                                                  0x5021f0UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define NIG_REG_LB_FC_DBG_SHIFT_PLLH                                                                         0x5021f4UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define NIG_REG_LB_FC_DBG_FORCE_VALID_PLLH                                                                   0x5021f8UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define NIG_REG_LB_FC_DBG_FORCE_FRAME_PLLH                                                                   0x5021fcUL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define NIG_REG_ECO_RESERVED                                                                                 0x502200UL //Access:RW   DataWidth:0x20   // Reserved bits for ECO.
+#define NIG_REG_ECO_RESERVED_PERPORT                                                                         0x502204UL //Access:RW   DataWidth:0x10   // Reserved bits for ECO.
+#define NIG_REG_ACPI_TAG_RM_BB                                                                               0x508000UL //Access:RW   DataWidth:0x8    // This is a per-port per-PF register.  L2 tag removal configuration for ACPI.  Bit mapped as follow: bit 0: 5 - L2 tags 0 to 5. Bit 6 is reserved and should be set to 0.  Bit 7 is for LLC/SNAP.  Set these bits to 1's to enable the removal of the corresponding tag when it is present in the  packet.  Clear the bit to keep the tag in the  packet.
+#define NIG_REG_ACPI_PROP_HDR_RM_BB                                                                          0x508004UL //Access:RW   DataWidth:0x1    // This is a per-port per-PF register.  Proprietary header removal configuration for ACPI.  Set this bit to 1 to enable the removal of the header.  Clear the bit to keep the header in the  packet.
+#define NIG_REG_MF_GLOBAL_EN_BB                                                                              0x508008UL //Access:RW   DataWidth:0x1    // Set this bit to enable ACPI pattern matching and TCP SYN matching in multi-function mode even when the per-function outer tag matching fails.
+#define NIG_REG_UPON_MGMT_BB                                                                                 0x50800cUL //Access:RW   DataWidth:0x1    // Set this bit to enable ACPI and TCP SYN matching even when the packet is forwarded to MCP.  Clear this bit to disable ACPI and TCP SYN matching when the packet is forwarded to MCP.
+#define NIG_REG_ACPI_BE_MEM_BB                                                                               0x508080UL //Access:WB   DataWidth:0x100  // This is a per-port per-PF register.  Byte enable memory for 8 ACPI patterns.
+#define NIG_REG_ACPI_BE_MEM_SIZE                                                                             32
+#define NIG_REG_ACPI_ENABLE_BB                                                                               0x508100UL //Access:RW   DataWidth:0x1    // This is a per-port per-PF register.  When this bit is set  ACPI packet recognition will be enabled. This bit must not be enabled until after all other ACPI registers were configured.
+#define NIG_REG_ACPI_PAT_0_CRC_BB                                                                            0x508104UL //Access:RW   DataWidth:0x20   // This is a per-port per-PF register.  CRC32C for pattern 0.
+#define NIG_REG_ACPI_PAT_0_LEN_BB                                                                            0x508108UL //Access:RW   DataWidth:0x8    // This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.
+#define NIG_REG_ACPI_PAT_1_CRC_BB                                                                            0x50810cUL //Access:RW   DataWidth:0x20   // This is a per-port per-PF register.  CRC32C for pattern 1.
+#define NIG_REG_ACPI_PAT_1_LEN_BB                                                                            0x508110UL //Access:RW   DataWidth:0x8    // This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.
+#define NIG_REG_ACPI_PAT_2_CRC_BB                                                                            0x508114UL //Access:RW   DataWidth:0x20   // This is a per-port per-PF register.  CRC32C for pattern 2.
+#define NIG_REG_ACPI_PAT_2_LEN_BB                                                                            0x508118UL //Access:RW   DataWidth:0x8    // This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.
+#define NIG_REG_ACPI_PAT_3_CRC_BB                                                                            0x50811cUL //Access:RW   DataWidth:0x20   // This is a per-port per-PF register.  CRC32C for pattern 3.
+#define NIG_REG_ACPI_PAT_3_LEN_BB                                                                            0x508120UL //Access:RW   DataWidth:0x8    // This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.
+#define NIG_REG_ACPI_PAT_4_CRC_BB                                                                            0x508124UL //Access:RW   DataWidth:0x20   // This is a per-port per-PF register.  CRC32C for pattern 4.
+#define NIG_REG_ACPI_PAT_4_LEN_BB                                                                            0x508128UL //Access:RW   DataWidth:0x8    // This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.
+#define NIG_REG_ACPI_PAT_5_CRC_BB                                                                            0x50812cUL //Access:RW   DataWidth:0x20   // This is a per-port per-PF register.  CRC32C for pattern 5.
+#define NIG_REG_ACPI_PAT_5_LEN_BB                                                                            0x508130UL //Access:RW   DataWidth:0x8    // This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.
+#define NIG_REG_ACPI_PAT_6_CRC_BB                                                                            0x508134UL //Access:RW   DataWidth:0x20   // This is a per-port per-PF register.  CRC32C for pattern 6.
+#define NIG_REG_ACPI_PAT_6_LEN_BB                                                                            0x508138UL //Access:RW   DataWidth:0x8    // This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.
+#define NIG_REG_ACPI_PAT_7_CRC_BB                                                                            0x50813cUL //Access:RW   DataWidth:0x20   // This is a per-port per-PF register.  CRC32C for pattern 7.
+#define NIG_REG_ACPI_PAT_7_LEN_BB                                                                            0x508140UL //Access:RW   DataWidth:0x8    // This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.
+#define NIG_REG_TCP_SYN_ENABLE                                                                               0x508144UL //Access:RW   DataWidth:0x2    // This is a per-port per-PF register.  Set bit 0 to enable wake on IPv4 TCP SYN. Set bit 1 to enable wake on IPv6 TCP SYN. These bits must not be set until after after all other registers needed for this feature are configured.
+#define NIG_REG_TCP_SYN_IPV6_MASK                                                                            0x508148UL //Access:RW   DataWidth:0x4    // This is a per-port per-PF register.  Enable bits for fields to be compared if IPv6 is present in the packet.  Bit 0 - TCP destination port; bit 1 - TCP source port; bit 2 - IP destination addresss; bit 3 - IP source address.  Set the bit to 1 to enable comparison.
+#define NIG_REG_TCP_SYN_IPV4_MASK                                                                            0x50814cUL //Access:RW   DataWidth:0x4    // This is a per-port per-PF register.  Enable bits for fields to be compared if IPv4 is present in the packet.  Bit 0 - TCP destination port; bit 1 - TCP source port; bit 2 - IP destination addresss; bit 3 - IP source address.  Set the bit to 1 to enable comparison.
+#define NIG_REG_TCP_SYN_IPV6_SRC_PORT                                                                        0x508150UL //Access:RW   DataWidth:0x10   // This is a per-port per-PF register.  IPv6 TCP source port.
+#define NIG_REG_TCP_SYN_IPV6_DST_PORT                                                                        0x508154UL //Access:RW   DataWidth:0x10   // This is a per-port per-PF register.  TCP IPv6 destination port.
+#define NIG_REG_TCP_SYN_IPV4_SRC_PORT                                                                        0x508158UL //Access:RW   DataWidth:0x10   // This is a per-port per-PF register.  IPv4 TCP source port.
+#define NIG_REG_TCP_SYN_IPV4_DST_PORT                                                                        0x50815cUL //Access:RW   DataWidth:0x10   // This is a per-port per-PF register.  TCP IPv4 destination port.
+#define NIG_REG_TCP_SYN_IPV6_SRC_ADDR                                                                        0x508160UL //Access:WB   DataWidth:0x80   // This is a per-port per-PF register.  IPv6 source address.
+#define NIG_REG_TCP_SYN_IPV6_SRC_ADDR_SIZE                                                                   4
+#define NIG_REG_TCP_SYN_IPV6_DST_ADDR                                                                        0x508170UL //Access:WB   DataWidth:0x80   // This is a per-port per-PF register.  IPv6 destination address.
+#define NIG_REG_TCP_SYN_IPV6_DST_ADDR_SIZE                                                                   4
+#define NIG_REG_TCP_SYN_IPV4_SRC_ADDR                                                                        0x508180UL //Access:RW   DataWidth:0x20   // This is a per-port per-PF register.  IPv4 source address.
+#define NIG_REG_TCP_SYN_IPV4_DST_ADDR                                                                        0x508184UL //Access:RW   DataWidth:0x20   // This is a per-port per-PF register.  IPv4 destination address.
+#define NIG_REG_MPKT_ENABLE_BB                                                                               0x508188UL //Access:RW   DataWidth:0x1    // This is a per-port per-PF register.  When this bit is set  Magic Packet recognition will be enabled. This bit must not be enabled until after after all other Magic Packet registers are configured.
+#define NIG_REG_MPKT_MAC_ADDR_BB                                                                             0x508190UL //Access:WB   DataWidth:0x30   // This is a per-port per-PF register.  MAC address for Magic Packet detection.
+#define NIG_REG_MPKT_MAC_ADDR_SIZE                                                                           2
+#define NIG_REG_FORCE_WOL_BB                                                                                 0x508198UL //Access:RW   DataWidth:0x1    // This is a per-port per-PF register.  A low-to-high transition of this bit forces a wake event.
+#define NIG_REG_WAKE_BUFFER_BB                                                                               0x5081a0UL //Access:WB_R DataWidth:0x100  // Read-only data from the Wake Buffer (organized as a FIFO).
+#define NIG_REG_WAKE_BUFFER_SIZE                                                                             8
+#define NIG_REG_WAKE_BUFFER_CLEAR_BB                                                                         0x5081c0UL //Access:RW   DataWidth:0x1    // Clear the Wake Buffer and Status - a low-to-high transition of this bit clears the wake_info, wake_pkt_len, and wake_details registers and allows the wake buffer to be overwritten, thereby re-enabling pattern detection.
+#define NIG_REG_WAKE_INFO_BB                                                                                 0x5081c4UL //Access:R    DataWidth:0x15   // Wake information register - all fields are sticky.  Bits  15:0 - PF Vector: The bit-mapped vector indicating which of the global PFs detected the wake event.  More than 1 bit may be set. Bit 16 - ACPI RCVD:  This bit is set when an ACPI packet is received. This is an OR of the results from the 8 functions. Bit 17 - MPKT:  This bit is set when a Magic packet is received. This is an OR of the results from the 8 functions. Bit 18 - TCP SYN RCVD:  This bit is set when TCP SYN packet is received. This is an OR of the results from the 8 functions. Bit 19 - FORCE RCVD:  This bit is set when force WOL event is received. This is an OR of the results from the 8 functions. Bit 20 - BUFFER NOT EMPTY:  This bit  is set when the buffer has the 'wake' packet. All fields are cleared by wake_buffer_clear or during a Hard Reset only. Core Reset has no effect on these fields.
+#define NIG_REG_WAKE_PKT_LEN_BB                                                                              0x5081c8UL //Access:R    DataWidth:0xe    // Wake packet length - the actual length of the 'wake' packet, in bytes. This register is sticky and is cleared by wake_buffer_clear or during a Hard Reset only. Core Reset has no effect on this register.
+#define NIG_REG_WAKE_DETAILS_BB                                                                              0x5081ccUL //Access:R    DataWidth:0x20   // Wake detail register - all fields are sticky.  Bits 7:0   - ACPI MATCH:  Per-function bit-mapped result from ACPI pattern match. Bits 15:8  - MPKT MATCH:  Per-function bit-mapped result from Magic packet pattern match. Bits 23:16 - TCP SYN MATCH:  Per-function bit-mapped result from TCP SYN match. Bits 31:24 - FORCE WOL MATCH:  Per-function bit-mapped result from force WOL match. All fields are cleared by wake_buffer_clear or during a Hard Reset only. Core Reset has no effect on these fields.
+#define NIG_REG_LLH_PTP_HOST_BUF_SRC_PORT_IDEN                                                               0x508800UL //Access:WB_R DataWidth:0x50   // Packet TimeSync information that is buffered in 1-deep FIFOs for the host. Source port identify field
+#define NIG_REG_LLH_PTP_HOST_BUF_SRC_PORT_IDEN_SIZE                                                          4
+#define NIG_REG_TX_LLH_PTP_HOST_BUF_SRC_PORT_IDEN                                                            0x508810UL //Access:WB_R DataWidth:0x50   // Packet TimeSync information that is buffered in 1-deep FIFO for the TX path. Source port identify field.
+#define NIG_REG_TX_LLH_PTP_HOST_BUF_SRC_PORT_IDEN_SIZE                                                       4
+#define NIG_REG_TX_UP_TS_EN_BB                                                                               0x508820UL //Access:RW   DataWidth:0x1    // TX User protocol time stamp enable
+#define NIG_REG_RX_UP_TS_EN_BB                                                                               0x508824UL //Access:RW   DataWidth:0x1    // RX User protocol time stamp enable
+#define NIG_REG_TX_PTP_ONE_STP_EN                                                                            0x508828UL //Access:RW   DataWidth:0x1    // Enable TS update for one step packets in the TX path.
+#define NIG_REG_RX_PTP_ONE_STP_EN                                                                            0x50882cUL //Access:RW   DataWidth:0x1    // Enable one step 1588 on RX
+#define NIG_REG_TX_UP_TS_ADDR_0_BB                                                                           0x508830UL //Access:RW   DataWidth:0x20   // TX User protocol address for packet classiification. It serves as source/dset mac address[47:0] or {source/dest UDP port[15:0], source/dest IPV4 address[31:0]} or ethernet type[15:0] or IPV4OptionNumber[7:0]
+#define NIG_REG_TX_UP_TS_ADDR_1_BB                                                                           0x508834UL //Access:RW   DataWidth:0x10   // TX User protocol address for packet classiification. It serves as source/dset mac address[47:0] or {source/dest UDP port[15:0], source/dest IPV4 address[31:0]} or ethernet type[15:0] or IPV4OptionNumber[7:0]
+#define NIG_REG_RX_UP_TS_ADDR_0_BB                                                                           0x508838UL //Access:RW   DataWidth:0x20   // RX User protocol address for packet classiification. It serves as source/dset mac address[47:0] or {source/dest UDP port[15:0], source/dest IPV4 address[31:0]} or ethernet type[15:0] or IPV4OptionNumber[7:0]
+#define NIG_REG_RX_UP_TS_ADDR_1_BB                                                                           0x50883cUL //Access:RW   DataWidth:0x10   // RX User protocol address for packet classiification. It serves as source/dset mac address[47:0] or {source/dest UDP port[15:0], source/dest IPV4 address[31:0]} or ethernet type[15:0] or IPV4OptionNumber[7:0]
+#define NIG_REG_TX_UP_TS_PARAM_MASK_BB                                                                       0x508840UL //Access:RW   DataWidth:0x6    // TX user protocol classification mask bits bit 0: mask_dstMac bit 1: mask_srcMac bit 2: mask_dstIPv4 bit 3: mask_srcIPv4 bit 4: mask_dstUDP bit 5: mask_srcUDP
+#define NIG_REG_RX_UP_TS_PARAM_MASK_BB                                                                       0x508844UL //Access:RW   DataWidth:0x6    // RX user protocol classification mask bits bit 0: mask_dstMac bit 1: mask_srcMac bit 2: mask_dstIPv4 bit 3: mask_srcIPv4 bit 4: mask_dstUDP bit 5: mask_srcUDP
+#define NIG_REG_TX_ENABLE_UP_RULES_BB                                                                        0x508848UL //Access:RW   DataWidth:0x5    // TX enable bits for user protocol classification rules bit 0: MAC address enable bit 1: IPV4 + UDP enable bit 2: Ethernet type enable bit 3: IPV4 option enable bit 4: Record time stamp bit from PBF enable
+#define NIG_REG_RX_ENABLE_UP_RULES_BB                                                                        0x50884cUL //Access:RW   DataWidth:0x5    // RX enable bits for user protocol classification rules bit 0: MAC address enable bit 1: IPV4 + UDP enable bit 2: Ethernet type enable bit 3: IPV4 option enable bit 4: Record time stamp bit from PBF enable
+#define NIG_REG_ADD_FREECNT_OFFSET                                                                           0x508850UL //Access:RW   DataWidth:0x1    // This bit defines whether to add offset and jitter of the timestamp to the returned timestamp from the MAC This bit is shared by TX and RX paths.
+#define NIG_REG_UP_TS_INSERT_EN_BB                                                                           0x508854UL //Access:RW   DataWidth:0x1    // Enable for on wire timestamp insertion for user protocol packets
+#define NIG_REG_PM_TIMER_SELECT                                                                              0x508858UL //Access:RW   DataWidth:0x3    // Selector for the 48 bits timer which is sent to the port macro. 0: free running counter. [1..4]: synchronized counter for port [1..4]
+#define NIG_REG_TS_FOR_SEMI_SELECT                                                                           0x50885cUL //Access:RW   DataWidth:0x3    // Selects which timer will be sent to SEMI/MCP 0: free running counter. [1..4]: synchronized counter for port [1..4]
+#define NIG_REG_USER_ONE_STEP_TYPE_BB                                                                        0x508860UL //Access:RW   DataWidth:0x3    // Define the required operation for user protocol packets: 0: NO_USER_ONE_STEP  no change to outgoing packet 1: ETHERTYPE  insert timestamp if EtherType filter had a hit 2: UDP  insert timestamp to UDP packet and regenerate checksum 3: TRAILER  insert timestamp to packet trailer 4: IPv4_STANDARD  insert timestamp using standard IPv4 Timestamp option. In this mode 32-bit timestamp with set_msb is used
+#define NIG_REG_TXOSTS_SIGNEXT_BB                                                                            0x508864UL //Access:RW   DataWidth:0x1    // sign extension indication for the MAC.
+#define NIG_REG_UP_TS_OFFSET_BB                                                                              0x508868UL //Access:RW   DataWidth:0x8    // Correction field offset for user protocol packets. the offset is relative to the configured value field in user_one_step_type.
+#define NIG_REG_TS_SHIFT_BB                                                                                  0x50886cUL //Access:RW   DataWidth:0x5    // Global timestamp shift for the free running counter. Legal values are 0-16
+#define NIG_REG_TS_OUTPUT_ENABLE_PDA                                                                         0x508870UL //Access:RW   DataWidth:0x1    // Output enable for TS passed to the Port Macro
+#define NIG_REG_TS_OUTPUT_ENABLE_HV                                                                          0x508874UL //Access:RW   DataWidth:0x1    // Output enable for TS passed to the Port Macro
+#define NIG_REG_USER_ONE_STEP_32_BB                                                                          0x508878UL //Access:RW   DataWidth:0x1    // Global parameter which defines that 32 bits timestamp will be inserted to the packet instead of 48 bits
+#define NIG_REG_LLH_UP_BUF_SEQID_BB                                                                          0x50887cUL //Access:RW   DataWidth:0x15   // RX User protocol Packet information that is buffered in 1-deep FIFOs.  Bits [15:0] return the sequence ID of the packet which is set by free running counter for user protocol packets.  Bits [19:16] indicate PF ID Bit 20 indicates the validity of the data in the buffer.  Writing a 1 to bit 16 will clear the buffer.
+#define NIG_REG_LLH_UP_BUF_TIMESTAMP_BB                                                                      0x508880UL //Access:WB_R DataWidth:0x40   // RX user protocol Packet information that is buffered in 1-deep FIFO. Timestamp field
+#define NIG_REG_LLH_UP_BUF_TIMESTAMP_SIZE                                                                    2
+#define NIG_REG_LLH_UP_BUF_SRC_ADDR_BB                                                                       0x508888UL //Access:WB_R DataWidth:0x30   // RX user protocol packet information that is buffered in 1-deep FIFO. Source address field
+#define NIG_REG_LLH_UP_BUF_SRC_ADDR_SIZE                                                                     2
+#define NIG_REG_TX_LLH_UP_BUF_SEQID_BB                                                                       0x508890UL //Access:RW   DataWidth:0x15   // TX User protocol Packet information that is buffered in 1-deep FIFOs.  Bits [15:0] return the sequence ID of the packet which is set by free running counter for user protocol packets.  Bits [19:16] indicate PF ID Bit 20 indicates the validity of the data in the buffer.  Writing a 1 to bit 16 will clear the buffer.
+#define NIG_REG_TX_LLH_UP_BUF_TIMESTAMP_BB                                                                   0x508898UL //Access:WB_R DataWidth:0x40   // TX user protocol Packet information that is buffered in 1-deep FIFO. Timestamp field
+#define NIG_REG_TX_LLH_UP_BUF_TIMESTAMP_SIZE                                                                 2
+#define NIG_REG_LLH_UP_BUF_DST_ADDR_BB                                                                       0x5088a0UL //Access:WB_R DataWidth:0x30   // RX user protocol packet information that is buffered in 1-deep FIFO. Destination address field
+#define NIG_REG_LLH_UP_BUF_DST_ADDR_SIZE                                                                     2
+#define NIG_REG_TSGEN_FREE_CNT_VALUE_LSB                                                                     0x5088a8UL //Access:RW   DataWidth:0x20   // This register contains the 32 bit LSB of the configured free counter. The value is written to the HW when writing to the MSB register
+#define NIG_REG_TSGEN_FREE_CNT_VALUE_MSB                                                                     0x5088acUL //Access:RW   DataWidth:0x20   // This register contains the 32 bit MSB of the configured free counter. Writing to this register also updatea HW value with MSB and LSB registers' value
+#define NIG_REG_TSGEN_OFFSET_VALUE_LSB                                                                       0x5088b0UL //Access:RW   DataWidth:0x20   // This register contains the 32 bit LSB of the offset value. This value is added to the Free Running Counter to create the synchronized time. The value is written to the HW when writing to the MSB register.
+#define NIG_REG_TSGEN_OFFSET_VALUE_MSB                                                                       0x5088b4UL //Access:RW   DataWidth:0x20   // This register contains the 32 bit MSB of the offset value. This value is added to the Free Running Counter to create the synchronized time. Writing to this register also updatea HW value with MSB and LSB registers' value. Read: Since offset width is 64 bits, tsgen_offset_value_lsb should be read first in order to latch the offset's value.
+#define NIG_REG_TSGEN_FREECNT_LSB                                                                            0x5088b8UL //Access:R    DataWidth:0x20   // This register contains the 32 bit LSB of the free running counter
+#define NIG_REG_TSGEN_FREECNT_MSB                                                                            0x5088bcUL //Access:R    DataWidth:0x20   // This register contains the 32 bit MSB of the free running counter. Since free counter width is 64 bits, tsgen_freecnt_lsb should be read first in order to latch the counter's value.
+#define NIG_REG_TSGEN_SYNC_TIME_LSB                                                                          0x5088c0UL //Access:R    DataWidth:0x20   // This register contains the 32 bit LSB of the synchronized time.
+#define NIG_REG_TSGEN_SYNC_TIME_MSB                                                                          0x5088c4UL //Access:R    DataWidth:0x20   // This register contains the 32 bit MSB of the synchronized time. Since synchronized time width is 64 bits, tsgen_sync_time_lsb should be read first in order to latch the counter's value.
+#define NIG_REG_TSGEN_HW_PPS_EN                                                                              0x5088c8UL //Access:RW   DataWidth:0x1    // In this mode,  Start time, high period and low period are all configurable, and when asserting this bit the PPS starts to toggle accoring to HW machine
+#define NIG_REG_TSGEN_SW_PPS_EN                                                                              0x5088ccUL //Access:RW   DataWidth:0x1    // In this mode,  whenever the synchronized time reaches a configurable value, PPS signal is toggled
+#define NIG_REG_TSGEN_PPS_HIGH_TIME                                                                          0x5088d0UL //Access:RW   DataWidth:0x20   // Duration of high PPS period. Valid when tsgen_hw_pps_en is enabled
+#define NIG_REG_TSGEN_PPS_LOW_TIME                                                                           0x5088d4UL //Access:RW   DataWidth:0x20   // Duration of low PPS period. Valid when tsgen_hw_pps_en is enabled
+#define NIG_REG_TSGEN_RST_DRIFT_CNTR                                                                         0x5088d8UL //Access:RW   DataWidth:0x1    // This is a level indication to reset drift counter's value
+#define NIG_REG_TSGEN_DRIFT_CNTR_CONF                                                                        0x5088dcUL //Access:RW   DataWidth:0x20   // This register should be configure only when tsgen_rst_drift_cntr is 1. Bits 27:0 specify how many 16 nsec time quantas to wait before making a Drift adjustment to the TSGEN_OFFSET_T0 register. The drift frequency has a constant added shift of 8 nsec. Bits 30:28 specify how many ns to add or subtract from the TSGEN_OFFSET_T0 register when making a Drift adjustment.  Bit 31 controls whether the Adjustment_Value is added (1'b1) or subtracted (1'b0) from the TSGEN_OFFSET_T0 register when making a Drift adjustment.
+#define NIG_REG_TSGEN_TSIO_OEB                                                                               0x5088e0UL //Access:RW   DataWidth:0x4    // Bits 3:0 are the active-low output enables for the TSIO Output pins 3:0.
+#define NIG_REG_TSGEN_TSIO_OUT_PULSE                                                                         0x5088e4UL //Access:R    DataWidth:0x4    // Bits 3:0 reflect pulse value for the TSIO Output pins 3:0.
+#define NIG_REG_EDPM_FIFO_FULL_THRESH                                                                        0x5088e8UL //Access:RW   DataWidth:0x7    // When EDPM FIFO data bytes occupancy is higher than this threshold nig_dorq_edpm_en is de-asserted. The value is configured in 32 bytes multiples.
+#define NIG_REG_MLD_MSG_TYPE_BB                                                                              0x5088ecUL //Access:RW   DataWidth:0x8    // This field sets message type value in ICMP header to identify MLD packets
+#define NIG_REG_ROCE_DUPLICATE_TO_HOST                                                                       0x5088f0UL //Access:RW   DataWidth:0x3    // This field is relevant to ROCE/RROCE: bit 0 marks that packet should be duplicated to host and Storm when BTH opcode equals bth_hdr_flow_ctrl_opcode_1. bit 1 marks that packet should be duplicated to host and Storm when BTH opcode equals bth_hdr_flow_ctrl_opcode_2. bit 2 marks than packet should be duplicated to host and Storm when (ECN == 2'b11).
+#define NIG_REG_DEFAULT_ENGINE_ID_SEL                                                                        0x5088f4UL //Access:RW   DataWidth:0x2    // This field selects engine ID in case that PF classification fails: 0: Use engine 0. 1: Use engine 1. 2/3: Use connection based classification.
+#define NIG_REG_DSCP_TO_TC_MAP_ENABLE                                                                        0x5088f8UL //Access:RW   DataWidth:0x1    // This field enables the feature that maps DSCP to TC in case that there is no TC in one of the L2 tags
+#define NIG_REG_PPF_TO_ENGINE_SEL                                                                            0x508900UL //Access:RW   DataWidth:0x4    // This field maps Port PF (PPF) to engine selection for ROCE/RROCE packets: Bits [1:0] define decision for ROCE/RROCE packets. Bits [3:2] define decision for other packets 0: use engine 0 1: use engine 1 2/3: use connection based classification
+#define NIG_REG_PPF_TO_ENGINE_SEL_SIZE                                                                       8
+#define NIG_REG_DSCP_TO_TC_MAP                                                                               0x508a00UL //Access:RW   DataWidth:0x6    // This field maps (ipv4_tos >> 2) 6 bits to 6 bits: bits 5:3 - priority bits 2:0 - TC This configuration is used when there is no priority field in one of the L2 headers
+#define NIG_REG_DSCP_TO_TC_MAP_SIZE                                                                          64
+#define NIG_REG_VXLAN_ZERO_UDP_IGNORE                                                                        0x508b00UL //Access:RW   DataWidth:0x1    // This field defines whether to ignore zero UDP value for VXLAN
+#define NIG_REG_NGE_ZERO_UDP_IGNORE                                                                          0x508b04UL //Access:RW   DataWidth:0x1    // This field defines whether to ignore zero UDP value for NGE
+#define NIG_REG_RROCE_ZERO_UDP_IGNORE                                                                        0x508b08UL //Access:RW   DataWidth:0x1    // This field defines whether to ignore zero UDP value for RROCE
+#define NIG_REG_RROCE_PORT                                                                                   0x508b0cUL //Access:RW   DataWidth:0x10   // This field defines UDP destination port number of RROCE
+#define NIG_REG_ACPI_TAG_REMOVE_BB                                                                           0x508b10UL //Access:RW   DataWidth:0x8    // This is a per-port register  L2 tag removal configuration for ACPI.  Bit mapped as follow: bit 0: 5 - L2 tags 0 to 5. Bit 6 is reserved and should be set to 0.  Bit 7 is for LLC/SNAP.  Set these bits to 1's to enable the removal of the corresponding tag when it is present in the  packet.  Clear the bit to keep the tag in the  packet.
+#define NIG_REG_ACPI_PROP_HDR_REMOVE_BB                                                                      0x508b14UL //Access:RW   DataWidth:0x1    // This is a per-port register.  Proprietary header removal configuration for ACPI.  Set this bit to 1 to enable the removal of the header.  Clear the bit to keep the header in the  packet.
+#define NIG_REG_CHECK_ETH_CRC_BB                                                                             0x508b18UL //Access:RW   DataWidth:0x1    // This is a per-port register.  When enabled, NIG will check Ethernet CRC in the packet and update error indication before transferring it to BRB/BMB/Storm
+#define NIG_REG_RM_ETH_CRC_BB                                                                                0x508b1cUL //Access:RW   DataWidth:0x1    // This is a per-port register.  When enabled, NIG will remove Ethernet CRC from the packet before transferring it to BRB/BMB/Storm
+#define NIG_REG_ADD_ETH_CRC                                                                                  0x508b20UL //Access:RW   DataWidth:0x1    // This is a per-port register.  When enabled, it indicates that the CNIG will add ethernet CRC to the packet. In that case, when the last cycle of the packet to the CNIG contains more than 28 valid bytes, a dead cycle will be inserted before the next packet in order to allow the CNIG time to add the CRC.
+#define NIG_REG_CORRUPT_ETH_CRC_BB                                                                           0x508b24UL //Access:RW   DataWidth:0x1    // This is a per-port register.  When enabled, NIG will corrupt ethernet CRC for packets which are received from BTB with error indication or are classified by the NIG as packets which should be transmitted with errors
+#define NIG_REG_NGE_IP_ENABLE                                                                                0x508b28UL //Access:RW   DataWidth:0x1    // This is a per-port register.  Enables NGE port matching during UDP header parsing when the encapsulated header is IP.
+#define NIG_REG_NGE_ETH_ENABLE                                                                               0x508b2cUL //Access:RW   DataWidth:0x1    // This is a per-port register. Enables NGE port matching during UDP header parsing when the encapsulated header is Ethernet.
+#define NIG_REG_NGE_COMP_VER                                                                                 0x508b30UL //Access:RW   DataWidth:0x1    // This is a per-port register.  Perform NGE version match to 2b0
+#define NIG_REG_NGE_ETH_TYPE                                                                                 0x508b34UL //Access:RW   DataWidth:0x10   // This is a per-port register.  Next protocol value to be used for Ethernet in NGE header
+#define NIG_REG_NGE_PORT                                                                                     0x508b38UL //Access:RW   DataWidth:0x10   // This is a per-port register. Destination port value used to designate a NGE header following the UDP header.  Matching can only occur when nge_ip_enable or nge_eth_enable are set.
+#define NIG_REG_LLH_LB_TC_REMAP                                                                              0x508b3cUL //Access:RW   DataWidth:0x18   // This is a per-port register which defines mapping of TC from the received TC to the TC sent to the BRB. bits 2:0: TC 0 bits 5:3: TC 1 ... bits 23:21: TC 7
+#define NIG_REG_BTH_HDR_FLOW_CTRL_OPCODE_1                                                                   0x508b40UL //Access:RW   DataWidth:0x8    // This is the first opcode in the BTH header for flow control packet identification.
+#define NIG_REG_BTH_HDR_FLOW_CTRL_OPCODE_2                                                                   0x508b44UL //Access:RW   DataWidth:0x8    // This is the second opcode in the BTH header for flow control packet identification.
+#define NIG_REG_RX_LLH_NCSI_MCP_MASK_2                                                                       0x508b48UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_IPV6_MLD                                       (0x1<<0) // Mask bit for forwarding IPV6 MLD (configurable MLD MsgType) packets to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_IPV6_MLD_SHIFT                                 0
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_IPV6_NEI_SOLICI                                (0x1<<1) // Mask bit for forwarding IPv6 Neighbor solicitation packets to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_IPV6_NEI_SOLICI_SHIFT                          1
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_DHCP_V6_SERVER                                 (0x1<<2) // Mask bit for forwarding IPv6 DHCP server packets to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_DHCP_V6_SERVER_SHIFT                           2
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_DHCP_V4_CLIENT                                 (0x1<<3) // Mask bit for forwarding DCHPv4 client packets to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_DHCP_V4_CLIENT_SHIFT                           3
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_DHCP_V4_SERVER                                 (0x1<<4) // Mask bit for forwarding DHCP V4 packets to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_DHCP_V4_SERVER_SHIFT                           4
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_MAC6_K2_E5                                     (0x1<<5) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_6 to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_MAC6_K2_E5_SHIFT                               5
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_MAC7_K2_E5                                     (0x1<<6) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_7 to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_MAC7_K2_E5_SHIFT                               6
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_DHCP_V6_CLI_E5                                 (0x1<<7) // Mask bit for forwarding IPv6 DHCP multicast server to client packets to MCP.
+  #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_DHCP_V6_CLI_E5_SHIFT                           7
+#define NIG_REG_TX_LLH_NCSI_MCP_MASK_2                                                                       0x508b4cUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_IPV6_MLD                                       (0x1<<0) // Mask bit for forwarding unicast IPv6 MLD (Configurable MsgType) packets to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_IPV6_MLD_SHIFT                                 0
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_IPV6_NEI_SOLICI                                (0x1<<1) // Mask bit for forwarding IPv6 neighbor solicitation packets to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_IPV6_NEI_SOLICI_SHIFT                          1
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_DHCP_V6_SERVER                                 (0x1<<2) // Mask bit for forwarding DHCP V6 server packets to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_DHCP_V6_SERVER_SHIFT                           2
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_DHCP_V4_CLIENT                                 (0x1<<3) // Mask bit for forwarding DHCP V4 client packets to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_DHCP_V4_CLIENT_SHIFT                           3
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_DHCP_V4_SERVER                                 (0x1<<4) // Mask bit for forwarding DHCP V4 server packets to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_DHCP_V4_SERVER_SHIFT                           4
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_DHCP_V6_CLI_E5                                 (0x1<<7) // Mask bit for forwarding DHCP V6 multicast server to client packets to MCP.
+  #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_DHCP_V6_CLI_E5_SHIFT                           7
+#define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2                                                                0x508b50UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_IPV6_MLD                         (0x1<<0) // Mask bit for not forwarding IPv6 MLD (Configurable MsgType) packets to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_IPV6_MLD_SHIFT                   0
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_IPV6_NEI_SOLICI                  (0x1<<1) // Mask bit for not forwarding IPv6 neighbor solicitation packets to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_IPV6_NEI_SOLICI_SHIFT            1
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V6_SERVER                   (0x1<<2) // Mask bit for not forwarding DHCP V6 server packets to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V6_SERVER_SHIFT             2
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V4_CLIENT                   (0x1<<3) // Mask bit for not forwarding DHCP V4 client packets to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V4_CLIENT_SHIFT             3
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V4_SERVER                   (0x1<<4) // Mask bit for not forwarding DHCP V4 server packets to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V4_SERVER_SHIFT             4
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC6_K2_E5                       (0x1<<5) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_6 to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC6_K2_E5_SHIFT                 5
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC7_K2_E5                       (0x1<<6) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_7 to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC7_K2_E5_SHIFT                 6
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V6_CLI_E5                   (0x1<<7) // Mask bit for not forwarding DHCP V6 multicast server to client packets to the host.
+  #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V6_CLI_E5_SHIFT             7
+#define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2                                                               0x508b54UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IPV6_MLD                       (0x1<<0) // Mask bit for not forwarding IPv6 MLD (Configurable MsgType) packets to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IPV6_MLD_SHIFT                 0
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IPV6_NEI_SOLICI                (0x1<<1) // Mask bit for not forwarding IPv6 neighbor solicitation packets to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IPV6_NEI_SOLICI_SHIFT          1
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V6_SERVER                 (0x1<<2) // Mask bit for not forwarding DHCP V6 server packets to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V6_SERVER_SHIFT           2
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V4_CLIENT                 (0x1<<3) // Mask bit for not forwarding DHCP V4 client packets to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V4_CLIENT_SHIFT           3
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V4_SERVER                 (0x1<<4) // Mask bit for not forwarding DHCP V4 server packets to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V4_SERVER_SHIFT           4
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V6_CLI_E5                 (0x1<<7) // Mask bit for not forwarding DHCP V6 multicast server to client packets to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V6_CLI_E5_SHIFT           7
+#define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2                                                                      0x508b58UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_IPV6_MLD                                     (0x1<<0) // Mask bit for forwarding IPv6 MLD (Configurable MsgType) packets to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_IPV6_MLD_SHIFT                               0
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_IPV6_NEI_SOLICI                              (0x1<<1) // Mask bit for forwarding IPv6 neighbor solicitation packets to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_IPV6_NEI_SOLICI_SHIFT                        1
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_DHCP_V6_SERVER                               (0x1<<2) // Mask bit for forwarding DHCP V6 server packets to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_DHCP_V6_SERVER_SHIFT                         2
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_DHCP_V4_CLIENT                               (0x1<<3) // Mask bit for forwarding DHCP V4 client packets to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_DHCP_V4_CLIENT_SHIFT                         3
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_DHCP_V4_SERVER                               (0x1<<4) // Mask bit for forwarding DHCP V4 server packets to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_DHCP_V4_SERVER_SHIFT                         4
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_DHCP_V6_CLI_E5                               (0x1<<7) // Mask bit for forwarding DHCP V6 multicast server to client packets to the network.
+  #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_DHCP_V6_CLI_E5_SHIFT                         7
+#define NIG_REG_DBGMUX_OVFLW_IND_EN                                                                          0x508b5cUL //Access:RW   DataWidth:0x1    // This is a Global register.  When this bit is enabled, instead of sending frame[0] from dbgmux, NIG will set an indication that some of the entries to the debug mux Were not written as the FIFO was full. This indication will be valid In the next entry which will be written to the FIFO.
+#define NIG_REG_TIMER_COUNTER                                                                                0x508b60UL //Access:R    DataWidth:0x20   // This fields reflects 32 lower bits value of the pause too long timer.
+#define NIG_REG_LB_GNT_FIFO_EMPTY                                                                            0x508b64UL //Access:R    DataWidth:0x1    // LB GNT FIFO empty status.
+#define NIG_REG_LB_GNT_FIFO_FULL                                                                             0x508b68UL //Access:R    DataWidth:0x1    // LB GNT FIFO full status.
+#define NIG_REG_RX_PARITY_ERR                                                                                0x508b6cUL //Access:R    DataWidth:0x3    // parity error status. Indicating the source of the parity error
+#define NIG_REG_TX_PARITY_ERR                                                                                0x508b70UL //Access:R    DataWidth:0x7    // parity error status. Indicating the source of the parity error
+#define NIG_REG_LB_PARITY_ERR                                                                                0x508b74UL //Access:R    DataWidth:0x6    // parity error status. Indicating the source of the parity error
+#define NIG_REG_TX_PARITY_ERROR_CLOSE_EGRESS                                                                 0x508b78UL //Access:RW   DataWidth:0x1    // When this bit is set and there is a parity error on the Tranmit data path, the data to the CNIG will be discarded.
+#define NIG_REG_TX_PARITY_ERROR_TIMER                                                                        0x508b7cUL //Access:RW   DataWidth:0x8    // This field defines the amount of time that the interface to the CNIG will be closed in case a parity error occured in the transmit data path.
+#define NIG_REG_TX_ARB_CLIENT_0_MAP                                                                          0x508b80UL //Access:RW   DataWidth:0x4    // This field defines the mapping of the DORQ request to one of the credit reisters. This enables credit sharing with one of the BTB TCs. 0: DORQ. 1: MNG. 2: Debug. 3: N/A. 4-11: BTB per TC.
+#define NIG_REG_TX_ARB_CLIENT_1_MAP                                                                          0x508b84UL //Access:RW   DataWidth:0x4    // This field defines the mapping of the management request to one of the credit reisters. This enables credit sharing with one of the BTB TCs. 0: DORQ. 1: MNG. 2: Debug. 3: N/A. 4-11: BTB per TC.
+#define NIG_REG_LB_ARB_CLIENT_0_MAP                                                                          0x508b88UL //Access:RW   DataWidth:0x4    // This field defines the mapping of the management request to one of the credit reisters. This enables credit sharing with one of the BTB TCs. 0:   MNG. 1-8: BTB per TC. 9:   BTB pure LB.
+#define NIG_REG_TX_INHIBIT_BMB_ARB_EN                                                                        0x508b8cUL //Access:RW   DataWidth:0x1    // This bit inhibits sending more than one outstanding packet request to the BMB until the last data of the current granted packet is received.
+#define NIG_REG_LB_INHIBIT_BMB_ARB_EN                                                                        0x508b90UL //Access:RW   DataWidth:0x1    // This bit inhibits sending more than one outstanding packet request to the BMB until the last data of the current granted packet is received.
+#define NIG_REG_TX_TDM_0_ENABLE_K2_E5                                                                        0x509000UL //Access:RW   DataWidth:0x1    // When this bit is configured to 1, NIG trasmits ports 0 and 1 data in TDM manner. If 0, then NIG transmits only port 0 data.
+#define NIG_REG_TX_TDM_1_ENABLE_K2_E5                                                                        0x509004UL //Access:RW   DataWidth:0x1    // When this bit is configured to 1, NIG trasmits ports 2 and 2 data in TDM manner. If 0, then NIG transmits only port 2 data.
+#define NIG_REG_TSGEN_FREECNT_UPDATE_K2_E5                                                                   0x509008UL //Access:RW   DataWidth:0x3    // Writing to this register: Bit 0: resets the value of the free running counter. Bit 1: pauses the auto increment of the free running counter. Bit 2: updates the value of the free running counter from tsgen_free_cnt_value_msb and tsgen_free_cnt_value_lsb fields.
+#define NIG_REG_TSGEN_PPS_OUT_SEL_MASK_0_K2_E5                                                               0x50900cUL //Access:RW   DataWidth:0x2    // This register selects which timer will be used as the source to PPS logic of nig_ifmux_tsio_0_out.
+#define NIG_REG_TSGEN_PPS_OUT_SEL_MASK_1_K2_E5                                                               0x509010UL //Access:RW   DataWidth:0x2    // This register selects which timer will be used as the source to PPS logic of nig_ifmux_tsio_1_out.
+#define NIG_REG_TSGEN_PPS_OUT_SEL_MASK_2_K2_E5                                                               0x509014UL //Access:RW   DataWidth:0x2    // This register selects which timer will be used as the source to PPS logic of nig_ifmux_tsio_2_out.
+#define NIG_REG_TSGEN_PPS_OUT_SEL_MASK_3_K2_E5                                                               0x509018UL //Access:RW   DataWidth:0x2    // This register selects which timer will be used as the source to PPS logic of nig_ifmux_tsio_3_out.
+#define NIG_REG_TSGEN_TSIO_IN_SEL_MASK_K2_E5                                                                 0x50901cUL //Access:RW   DataWidth:0x4    // This register selects which TSIO Input signals are used to latch the synchronized time for the per port timer.
+#define NIG_REG_TSGEN_TSIO_IN_SEL_POL_K2_E5                                                                  0x509020UL //Access:RW   DataWidth:0x1    // This register selects the polarity of TSIO signals. 1: active high. 0: active low
+#define NIG_REG_TSGEN_TSIO_IN_VAL_K2_E5                                                                      0x509024UL //Access:R    DataWidth:0x4    // This register reflects the value of the TSIN pins.
+#define NIG_REG_TSGEN_TSIO_IN_LATCHED_VALUE_K2_E5                                                            0x509028UL //Access:WB_R DataWidth:0x40   // This register reflects the value of the Timestamp when the it is latched by input pins.
+#define NIG_REG_TSGEN_TSIO_IN_LATCHED_VALUE_SIZE                                                             2
+#define NIG_REG_TSGEN_TSIO_OUT_NEXT_TOGGLE_TIME_K2_E5                                                        0x509030UL //Access:WB_R DataWidth:0x40   // This register reflects the timestamp of the next PPS toggle.
+#define NIG_REG_TSGEN_TSIO_OUT_NEXT_TOGGLE_TIME_SIZE                                                         2
+#define NIG_REG_TSGEN_PPS_START_TIME_0_K2_E5                                                                 0x509038UL //Access:RW   DataWidth:0x20   // This register reflects the start time of PPS.
+#define NIG_REG_TSGEN_PPS_START_TIME_1_K2_E5                                                                 0x50903cUL //Access:RW   DataWidth:0x20   // This register reflects the start time of PPS.
+#define NIG_REG_PTP_LATCH_OSTS_PKT_TIME_K2_E5                                                                0x509040UL //Access:RW   DataWidth:0x1    // This bit enables time stamp latching for one step PTP packets.
+#define NIG_REG_PTP_LATCH_SW_OSTS_PKT_TIME_K2_E5                                                             0x509044UL //Access:RW   DataWidth:0x1    // This bit enables time stamp latching for one step PTP packets with RECORD_TIME_STAMP bit from BTB/PBF on. This feature is enabled when ptp_sw_txtsen is 1.
+#define NIG_REG_PTP_UPDATE_SW_OSTS_PKT_TIME_K2_E5                                                            0x509048UL //Access:RW   DataWidth:0x1    // This bit enables correction field update for one step PTP packets with RECORD_TIME_STAMP bit from BTB/PBF on. This feature is enabled when ptp_sw_txtsen is 1.
+#define NIG_REG_TS_FOR_PXP_SELECT_K2_E5                                                                      0x50904cUL //Access:RW   DataWidth:0x3    // Selects which timer will be sent to PXP 0: free running counter. [1..4]: synchronized counter for port [1..4]
+#define NIG_REG_PTM_TIME_LATCH_K2_E5                                                                         0x509050UL //Access:WB_R DataWidth:0x40   // When this register is read, it reflects the latched time at that moment.
+#define NIG_REG_PTM_TIME_LATCH_SIZE                                                                          2
+#define NIG_REG_LLH_DEST_MAC_6_0_K2_E5                                                                       0x509058UL //Access:RW   DataWidth:0x20   // Destination MAC address 6.  LLH will look for this address in all incoming packets.
+#define NIG_REG_LLH_DEST_MAC_6_1_K2_E5                                                                       0x50905cUL //Access:RW   DataWidth:0x10   // Destination MAC address 6.  LLH will look for this address in all incoming packets.
+#define NIG_REG_LLH_DEST_MAC_7_0_K2_E5                                                                       0x509060UL //Access:RW   DataWidth:0x20   // Destination MAC address 7.  LLH will look for this address in all incoming packets.
+#define NIG_REG_LLH_DEST_MAC_7_1_K2_E5                                                                       0x509064UL //Access:RW   DataWidth:0x10   // Destination MAC address 7.  LLH will look for this address in all incoming packets.
+#define NIG_REG_MPA_MUL_PDU_CRC_CALC_EN_K2_E5                                                                0x509068UL //Access:RW   DataWidth:0x1    // This bit selects whether to use the MPA CRC calculation on one fully contained PDU (legacy mode - 0) or on multiple PDUs (1).
+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_E5                                                              0x50a000UL //Access:WB   DataWidth:0x30   // This is a global pool of 512 MAC addresses to be matched with for MAC-address-based classification.  This register is also used for protocol-based classification; bits [47:32] are for Ethertype; bits [31:16] are for the source port; and bits [15:0] are for the destination port.
+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_SIZE                                                            1024
+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_E5                                                                 0x50b000UL //Access:RW   DataWidth:0x1    // This is a global pool of 512 filter enables for PF classification.
+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_SIZE                                                               512
+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_E5                                                               0x50b800UL //Access:RW   DataWidth:0x1    // This is a global pool of 512 mode select bits to indicate whether the filter is to be used for MAC-addresss based classification or protocol-based classification.  Set this bit to 1 to select protocol-based classification.
+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_SIZE                                                             512
+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_E5                                                      0x50c000UL //Access:RW   DataWidth:0x7    // This is a global pool of 512 select bits for the different protocol types to be evaluated in protocol-based classification mode: bit 0: compare the Ethertype; bit 1: compare the TCP source port; bit 2: compare the TCP destination port; bit 3: compare the TCP source and destination ports. bit 4: compare the UDP source port; bit 5: compare the UDP destination port; bit 6: compare the UDP source and destination ports. Set the bit to 1 to enable the comparison.  The results are logically OR'ed together, and thus, a match is found when one or more of the enabled types compare successfully.
+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_SIZE                                                    512
+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_E5                                                            0x50c800UL //Access:RW   DataWidth:0x1    // This is a global pool of 512 select bits for choosing between the tunnel and encapsulated header from which to take the MAC address to be compared with that in llh_func_filter_value for PF classification; 0 selects the outer/tunnel header.
+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_SIZE                                                          512
+#define NIG_REG_LLH_PF_CLS_FILTERS_MAP_E5                                                                    0x50d000UL //Access:RW   DataWidth:0x5    // This fields maps between sets of 16 filters to the PPF that uses them There are 32 groups of 16 filters which are used for MAC/protocol based Classification. This filed allows using dynamic number of filters for every PPF. bits [4:3] are the port ID, bits 2:0 are the PPF ID The set of rlevent configurations is: llh_pf_cls_func_filter_value, llh_pf_cls_func_filter_en, llh_pf_cls_func_filter_mode, llh_pf_cls_func_filter_protocol_type and llh_pf_cls_func_filter_hdr_sel. Reset value is the identity mapping.
+#define NIG_REG_LLH_PF_CLS_FILTERS_MAP_SIZE                                                                  32
+#define NIG_REG_MNG_TO_MCP_NCSI_FILTER_0_E5                                                                  0x50d080UL //Access:RW   DataWidth:0x20   // This field is a per NCSI filter rule setting. When configured to 1, it means that the packet will be sent to MCP and not BMC. Bits 31:0 are taken from NCSI table. Bits 33:32 correspond to DA6 and DA7 (rules 9 and 10) Bit  34 corresponds to DHCPv6 client rule (rule 21b).
+#define NIG_REG_MNG_TO_MCP_NCSI_FILTER_1_E5                                                                  0x50d084UL //Access:RW   DataWidth:0x3    // This field is a per NCSI filter rule setting. When configured to 1, it means that the packet will be sent to MCP and not BMC. Bits 31:0 are taken from NCSI table. Bits 33:32 correspond to DA6 and DA7 (rules 9 and 10) Bit  34 corresponds to DHCPv6 client rule (rule 21b).
+#define NIG_REG_TX_LB_VPORT_DROP_E5                                                                          0x50d400UL //Access:RW   DataWidth:0x1    // Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.
+#define NIG_REG_TX_LB_VPORT_DROP_SIZE                                                                        256
+#define NIG_REG_TX_BMB_FIFO_ALM_FULL_THR_E5                                                                  0x50d800UL //Access:RW   DataWidth:0x6    // Almost-full threshold for BMB FIFO.
+#define NIG_REG_TX_ORDER_FIFO_FULL_E5                                                                        0x50d804UL //Access:R    DataWidth:0x1    // This register marks that the order FIFO is full.
+#define NIG_REG_LB_ORDER_FIFO_FULL_E5                                                                        0x50d808UL //Access:R    DataWidth:0x1    // This register marks that the order FIFO is full.
+#define NIG_REG_TX_OOO_RFIFO_FULL_E5                                                                         0x50d80cUL //Access:R    DataWidth:0x1    // This register marks that the out of order FIFO in the LLH is full.
+#define NIG_REG_LB_OOO_RFIFO_FULL_E5                                                                         0x50d810UL //Access:R    DataWidth:0x1    // This register marks that the out of order FIFO in the LLH is full.
+#define NIG_REG_MPLS_IPV4_LABEL_E5                                                                           0x50d814UL //Access:RW   DataWidth:0x14   // mpls_ipv4_label to be compared Vs the label field of the last mpls label if mpls_compare_label is set.
+#define NIG_REG_MPLS_IPV6_LABEL_E5                                                                           0x50d818UL //Access:RW   DataWidth:0x14   // mpls_ipv6_label to be compared Vs the label field of the last mpls label if mpls_compare_label is set.
+#define NIG_REG_MPLS_COMPARE_LABEL_E5                                                                        0x50d81cUL //Access:RW   DataWidth:0x1    // mpls_ipv6_label/mpls_ipv4_label to be compared Vs the label field of the last mpls label if mpls_compare_label is set.
+#define NIG_REG_MPLS_UNI_TYPE_E5                                                                             0x50d820UL //Access:RW   DataWidth:0x10   // Ethernet type of MPLS.
+#define NIG_REG_MPLS_MULTI_TYPE_E5                                                                           0x50d824UL //Access:RW   DataWidth:0x10   // Ethernet type of MPLS.
+#define NIG_REG_COMPARE_GRE_VERSION_E5                                                                       0x50d828UL //Access:RW   DataWidth:0x1    // compare the GRE version field to the gre_version register.
+#define NIG_REG_GRE_VERSION_E5                                                                               0x50d82cUL //Access:RW   DataWidth:0x3    // compare the GRE version field to gre_version register if compare_gre_version=1.
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_0_E5                                                               0x50d830UL //Access:RW   DataWidth:0x8    // ipv6 extension uniform header type 0
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_1_E5                                                               0x50d834UL //Access:RW   DataWidth:0x8    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_2_E5                                                               0x50d838UL //Access:RW   DataWidth:0x8    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_3_E5                                                               0x50d83cUL //Access:RW   DataWidth:0x8    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_4_E5                                                               0x50d840UL //Access:RW   DataWidth:0x8    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_5_E5                                                               0x50d844UL //Access:RW   DataWidth:0x8    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_6_E5                                                               0x50d848UL //Access:RW   DataWidth:0x8    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_7_E5                                                               0x50d84cUL //Access:RW   DataWidth:0x8    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_8_E5                                                               0x50d850UL //Access:RW   DataWidth:0x8    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_9_E5                                                               0x50d854UL //Access:RW   DataWidth:0x8    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_10_E5                                                              0x50d858UL //Access:RW   DataWidth:0x8    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_11_E5                                                              0x50d85cUL //Access:RW   DataWidth:0x8    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_12_E5                                                              0x50d860UL //Access:RW   DataWidth:0x8    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_13_E5                                                              0x50d864UL //Access:RW   DataWidth:0x8    // 
+#define NIG_REG_IPV6_EXT_FRAGMENT_HDR_TYPE_E5                                                                0x50d868UL //Access:RW   DataWidth:0x8    // 
+#define NIG_REG_IPV6_EXT_AUTHENTICATION_HDR_TYPE_E5                                                          0x50d86cUL //Access:RW   DataWidth:0x8    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_0_VALID_E5                                                         0x50d870UL //Access:RW   DataWidth:0x1    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_1_VALID_E5                                                         0x50d874UL //Access:RW   DataWidth:0x1    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_2_VALID_E5                                                         0x50d878UL //Access:RW   DataWidth:0x1    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_3_VALID_E5                                                         0x50d87cUL //Access:RW   DataWidth:0x1    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_4_VALID_E5                                                         0x50d880UL //Access:RW   DataWidth:0x1    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_5_VALID_E5                                                         0x50d884UL //Access:RW   DataWidth:0x1    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_6_VALID_E5                                                         0x50d888UL //Access:RW   DataWidth:0x1    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_7_VALID_E5                                                         0x50d88cUL //Access:RW   DataWidth:0x1    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_8_VALID_E5                                                         0x50d890UL //Access:RW   DataWidth:0x1    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_9_VALID_E5                                                         0x50d894UL //Access:RW   DataWidth:0x1    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_10_VALID_E5                                                        0x50d898UL //Access:RW   DataWidth:0x1    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_11_VALID_E5                                                        0x50d89cUL //Access:RW   DataWidth:0x1    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_12_VALID_E5                                                        0x50d8a0UL //Access:RW   DataWidth:0x1    // 
+#define NIG_REG_IPV6_EXT_UNIFORM_HDR_TYPE_13_VALID_E5                                                        0x50d8a4UL //Access:RW   DataWidth:0x1    // 
+#define NIG_REG_IPV6_EXT_FRAGMENT_HDR_TYPE_VALID_E5                                                          0x50d8a8UL //Access:RW   DataWidth:0x1    // 
+#define NIG_REG_IPV6_EXT_AUTHENTICATION_HDR_TYPE_VALID_E5                                                    0x50d8acUL //Access:RW   DataWidth:0x1    // 
+#define BMB_REG_HW_INIT_EN                                                                                   0x540004UL //Access:RW   DataWidth:0x2    // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en registers will be done by HW.  Bit 1 - if this bit is set then initialization of BIG RAM will be done by HW. Both bits will be reset by HW when initialization is finished.
+#define BMB_REG_INIT_DONE                                                                                    0x540008UL //Access:R    DataWidth:0x2    // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en registers are finished by HW.  Bit 1 - if this bit is set then initialization of BIG RAM is finished by HW.
+#define BMB_REG_START_EN                                                                                     0x54000cUL //Access:RW   DataWidth:0x1    // This bit should be set when initialization of all BRTB registers and memories is finished. BRTB will fill all prefetch FIFO with free pointers. BRTB will not be able to get packets from write clients when this bit is reset. If link list was configured by HW then this bit will be set by HW.
+#define BMB_REG_INT_STS_0                                                                                    0x5400c0UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_0_ADDRESS_ERROR                                                                    (0x1<<0) // Signals an unknown address to the rf module.
+  #define BMB_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                              0
+  #define BMB_REG_INT_STS_0_RC_PKT0_RLS_ERROR                                                                (0x1<<1) // Read packet client rc0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_0_RC_PKT0_RLS_ERROR_SHIFT                                                          1
+  #define BMB_REG_INT_STS_0_RC_PKT0_PROTOCOL_ERROR                                                           (0x1<<5) // Read packet client rc0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_0_RC_PKT0_PROTOCOL_ERROR_SHIFT                                                     5
+  #define BMB_REG_INT_STS_0_RC_PKT1_RLS_ERROR                                                                (0x1<<6) // Read packet client rc1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_0_RC_PKT1_RLS_ERROR_SHIFT                                                          6
+  #define BMB_REG_INT_STS_0_RC_PKT1_PROTOCOL_ERROR                                                           (0x1<<10) // Read packet client rc1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_0_RC_PKT1_PROTOCOL_ERROR_SHIFT                                                     10
+  #define BMB_REG_INT_STS_0_RC_PKT2_RLS_ERROR                                                                (0x1<<11) // Read packet client rc2 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_0_RC_PKT2_RLS_ERROR_SHIFT                                                          11
+  #define BMB_REG_INT_STS_0_RC_PKT2_PROTOCOL_ERROR                                                           (0x1<<15) // Read packet client rc2 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_0_RC_PKT2_PROTOCOL_ERROR_SHIFT                                                     15
+  #define BMB_REG_INT_STS_0_RC_PKT3_RLS_ERROR                                                                (0x1<<16) // Read packet client rc3 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_0_RC_PKT3_RLS_ERROR_SHIFT                                                          16
+  #define BMB_REG_INT_STS_0_RC_PKT3_PROTOCOL_ERROR                                                           (0x1<<20) // Read packet client rc3 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_0_RC_PKT3_PROTOCOL_ERROR_SHIFT                                                     20
+  #define BMB_REG_INT_STS_0_RC_SOP_REQ_TC_PORT_ERROR                                                         (0x1<<21) // SOP descriptor request from empty TC or port.
+  #define BMB_REG_INT_STS_0_RC_SOP_REQ_TC_PORT_ERROR_SHIFT                                                   21
+  #define BMB_REG_INT_STS_0_WC0_PROTOCOL_ERROR                                                               (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
+  #define BMB_REG_INT_STS_0_WC0_PROTOCOL_ERROR_SHIFT                                                         23
+  #define BMB_REG_INT_STS_0_WC1_PROTOCOL_ERROR                                                               (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 1 RX_INT ::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_0_WC1_PROTOCOL_ERROR_SHIFT                                                         24
+  #define BMB_REG_INT_STS_0_WC2_PROTOCOL_ERROR                                                               (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 2 RX_INT ::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_0_WC2_PROTOCOL_ERROR_SHIFT                                                         25
+  #define BMB_REG_INT_STS_0_WC3_PROTOCOL_ERROR                                                               (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 3 RX_INT ::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_0_WC3_PROTOCOL_ERROR_SHIFT                                                         26
+  #define BMB_REG_INT_STS_0_LL_BLK_ERROR                                                                     (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
+  #define BMB_REG_INT_STS_0_LL_BLK_ERROR_SHIFT                                                               28
+  #define BMB_REG_INT_STS_0_MAC0_FC_CNT_ERROR                                                                (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_0_MAC0_FC_CNT_ERROR_SHIFT                                                          31
+#define BMB_REG_INT_MASK_0                                                                                   0x5400c4UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_MASK_0_ADDRESS_ERROR                                                                   (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.ADDRESS_ERROR .
+  #define BMB_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                             0
+  #define BMB_REG_INT_MASK_0_RC_PKT0_RLS_ERROR                                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT0_RLS_ERROR .
+  #define BMB_REG_INT_MASK_0_RC_PKT0_RLS_ERROR_SHIFT                                                         1
+  #define BMB_REG_INT_MASK_0_RC_PKT0_PROTOCOL_ERROR                                                          (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT0_PROTOCOL_ERROR .
+  #define BMB_REG_INT_MASK_0_RC_PKT0_PROTOCOL_ERROR_SHIFT                                                    5
+  #define BMB_REG_INT_MASK_0_RC_PKT1_RLS_ERROR                                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT1_RLS_ERROR .
+  #define BMB_REG_INT_MASK_0_RC_PKT1_RLS_ERROR_SHIFT                                                         6
+  #define BMB_REG_INT_MASK_0_RC_PKT1_PROTOCOL_ERROR                                                          (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT1_PROTOCOL_ERROR .
+  #define BMB_REG_INT_MASK_0_RC_PKT1_PROTOCOL_ERROR_SHIFT                                                    10
+  #define BMB_REG_INT_MASK_0_RC_PKT2_RLS_ERROR                                                               (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT2_RLS_ERROR .
+  #define BMB_REG_INT_MASK_0_RC_PKT2_RLS_ERROR_SHIFT                                                         11
+  #define BMB_REG_INT_MASK_0_RC_PKT2_PROTOCOL_ERROR                                                          (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT2_PROTOCOL_ERROR .
+  #define BMB_REG_INT_MASK_0_RC_PKT2_PROTOCOL_ERROR_SHIFT                                                    15
+  #define BMB_REG_INT_MASK_0_RC_PKT3_RLS_ERROR                                                               (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT3_RLS_ERROR .
+  #define BMB_REG_INT_MASK_0_RC_PKT3_RLS_ERROR_SHIFT                                                         16
+  #define BMB_REG_INT_MASK_0_RC_PKT3_PROTOCOL_ERROR                                                          (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT3_PROTOCOL_ERROR .
+  #define BMB_REG_INT_MASK_0_RC_PKT3_PROTOCOL_ERROR_SHIFT                                                    20
+  #define BMB_REG_INT_MASK_0_RC_SOP_REQ_TC_PORT_ERROR                                                        (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_SOP_REQ_TC_PORT_ERROR .
+  #define BMB_REG_INT_MASK_0_RC_SOP_REQ_TC_PORT_ERROR_SHIFT                                                  21
+  #define BMB_REG_INT_MASK_0_WC0_PROTOCOL_ERROR                                                              (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.WC0_PROTOCOL_ERROR .
+  #define BMB_REG_INT_MASK_0_WC0_PROTOCOL_ERROR_SHIFT                                                        23
+  #define BMB_REG_INT_MASK_0_WC1_PROTOCOL_ERROR                                                              (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.WC1_PROTOCOL_ERROR .
+  #define BMB_REG_INT_MASK_0_WC1_PROTOCOL_ERROR_SHIFT                                                        24
+  #define BMB_REG_INT_MASK_0_WC2_PROTOCOL_ERROR                                                              (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.WC2_PROTOCOL_ERROR .
+  #define BMB_REG_INT_MASK_0_WC2_PROTOCOL_ERROR_SHIFT                                                        25
+  #define BMB_REG_INT_MASK_0_WC3_PROTOCOL_ERROR                                                              (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.WC3_PROTOCOL_ERROR .
+  #define BMB_REG_INT_MASK_0_WC3_PROTOCOL_ERROR_SHIFT                                                        26
+  #define BMB_REG_INT_MASK_0_LL_BLK_ERROR                                                                    (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.LL_BLK_ERROR .
+  #define BMB_REG_INT_MASK_0_LL_BLK_ERROR_SHIFT                                                              28
+  #define BMB_REG_INT_MASK_0_MAC0_FC_CNT_ERROR                                                               (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.MAC0_FC_CNT_ERROR .
+  #define BMB_REG_INT_MASK_0_MAC0_FC_CNT_ERROR_SHIFT                                                         31
+#define BMB_REG_INT_STS_WR_0                                                                                 0x5400c8UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_WR_0_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define BMB_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                           0
+  #define BMB_REG_INT_STS_WR_0_RC_PKT0_RLS_ERROR                                                             (0x1<<1) // Read packet client rc0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_WR_0_RC_PKT0_RLS_ERROR_SHIFT                                                       1
+  #define BMB_REG_INT_STS_WR_0_RC_PKT0_PROTOCOL_ERROR                                                        (0x1<<5) // Read packet client rc0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_WR_0_RC_PKT0_PROTOCOL_ERROR_SHIFT                                                  5
+  #define BMB_REG_INT_STS_WR_0_RC_PKT1_RLS_ERROR                                                             (0x1<<6) // Read packet client rc1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_WR_0_RC_PKT1_RLS_ERROR_SHIFT                                                       6
+  #define BMB_REG_INT_STS_WR_0_RC_PKT1_PROTOCOL_ERROR                                                        (0x1<<10) // Read packet client rc1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_WR_0_RC_PKT1_PROTOCOL_ERROR_SHIFT                                                  10
+  #define BMB_REG_INT_STS_WR_0_RC_PKT2_RLS_ERROR                                                             (0x1<<11) // Read packet client rc2 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_WR_0_RC_PKT2_RLS_ERROR_SHIFT                                                       11
+  #define BMB_REG_INT_STS_WR_0_RC_PKT2_PROTOCOL_ERROR                                                        (0x1<<15) // Read packet client rc2 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_WR_0_RC_PKT2_PROTOCOL_ERROR_SHIFT                                                  15
+  #define BMB_REG_INT_STS_WR_0_RC_PKT3_RLS_ERROR                                                             (0x1<<16) // Read packet client rc3 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_WR_0_RC_PKT3_RLS_ERROR_SHIFT                                                       16
+  #define BMB_REG_INT_STS_WR_0_RC_PKT3_PROTOCOL_ERROR                                                        (0x1<<20) // Read packet client rc3 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_WR_0_RC_PKT3_PROTOCOL_ERROR_SHIFT                                                  20
+  #define BMB_REG_INT_STS_WR_0_RC_SOP_REQ_TC_PORT_ERROR                                                      (0x1<<21) // SOP descriptor request from empty TC or port.
+  #define BMB_REG_INT_STS_WR_0_RC_SOP_REQ_TC_PORT_ERROR_SHIFT                                                21
+  #define BMB_REG_INT_STS_WR_0_WC0_PROTOCOL_ERROR                                                            (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
+  #define BMB_REG_INT_STS_WR_0_WC0_PROTOCOL_ERROR_SHIFT                                                      23
+  #define BMB_REG_INT_STS_WR_0_WC1_PROTOCOL_ERROR                                                            (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 1 RX_INT ::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_0_WC1_PROTOCOL_ERROR_SHIFT                                                      24
+  #define BMB_REG_INT_STS_WR_0_WC2_PROTOCOL_ERROR                                                            (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 2 RX_INT ::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_0_WC2_PROTOCOL_ERROR_SHIFT                                                      25
+  #define BMB_REG_INT_STS_WR_0_WC3_PROTOCOL_ERROR                                                            (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 3 RX_INT ::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_0_WC3_PROTOCOL_ERROR_SHIFT                                                      26
+  #define BMB_REG_INT_STS_WR_0_LL_BLK_ERROR                                                                  (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
+  #define BMB_REG_INT_STS_WR_0_LL_BLK_ERROR_SHIFT                                                            28
+  #define BMB_REG_INT_STS_WR_0_MAC0_FC_CNT_ERROR                                                             (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_0_MAC0_FC_CNT_ERROR_SHIFT                                                       31
+#define BMB_REG_INT_STS_CLR_0                                                                                0x5400ccUL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define BMB_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                          0
+  #define BMB_REG_INT_STS_CLR_0_RC_PKT0_RLS_ERROR                                                            (0x1<<1) // Read packet client rc0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_0_RC_PKT0_RLS_ERROR_SHIFT                                                      1
+  #define BMB_REG_INT_STS_CLR_0_RC_PKT0_PROTOCOL_ERROR                                                       (0x1<<5) // Read packet client rc0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_0_RC_PKT0_PROTOCOL_ERROR_SHIFT                                                 5
+  #define BMB_REG_INT_STS_CLR_0_RC_PKT1_RLS_ERROR                                                            (0x1<<6) // Read packet client rc1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_0_RC_PKT1_RLS_ERROR_SHIFT                                                      6
+  #define BMB_REG_INT_STS_CLR_0_RC_PKT1_PROTOCOL_ERROR                                                       (0x1<<10) // Read packet client rc1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_0_RC_PKT1_PROTOCOL_ERROR_SHIFT                                                 10
+  #define BMB_REG_INT_STS_CLR_0_RC_PKT2_RLS_ERROR                                                            (0x1<<11) // Read packet client rc2 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_0_RC_PKT2_RLS_ERROR_SHIFT                                                      11
+  #define BMB_REG_INT_STS_CLR_0_RC_PKT2_PROTOCOL_ERROR                                                       (0x1<<15) // Read packet client rc2 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_0_RC_PKT2_PROTOCOL_ERROR_SHIFT                                                 15
+  #define BMB_REG_INT_STS_CLR_0_RC_PKT3_RLS_ERROR                                                            (0x1<<16) // Read packet client rc3 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_CLR_0_RC_PKT3_RLS_ERROR_SHIFT                                                      16
+  #define BMB_REG_INT_STS_CLR_0_RC_PKT3_PROTOCOL_ERROR                                                       (0x1<<20) // Read packet client rc3 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_CLR_0_RC_PKT3_PROTOCOL_ERROR_SHIFT                                                 20
+  #define BMB_REG_INT_STS_CLR_0_RC_SOP_REQ_TC_PORT_ERROR                                                     (0x1<<21) // SOP descriptor request from empty TC or port.
+  #define BMB_REG_INT_STS_CLR_0_RC_SOP_REQ_TC_PORT_ERROR_SHIFT                                               21
+  #define BMB_REG_INT_STS_CLR_0_WC0_PROTOCOL_ERROR                                                           (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
+  #define BMB_REG_INT_STS_CLR_0_WC0_PROTOCOL_ERROR_SHIFT                                                     23
+  #define BMB_REG_INT_STS_CLR_0_WC1_PROTOCOL_ERROR                                                           (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 1 RX_INT ::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_0_WC1_PROTOCOL_ERROR_SHIFT                                                     24
+  #define BMB_REG_INT_STS_CLR_0_WC2_PROTOCOL_ERROR                                                           (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 2 RX_INT ::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_0_WC2_PROTOCOL_ERROR_SHIFT                                                     25
+  #define BMB_REG_INT_STS_CLR_0_WC3_PROTOCOL_ERROR                                                           (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 3 RX_INT ::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_0_WC3_PROTOCOL_ERROR_SHIFT                                                     26
+  #define BMB_REG_INT_STS_CLR_0_LL_BLK_ERROR                                                                 (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
+  #define BMB_REG_INT_STS_CLR_0_LL_BLK_ERROR_SHIFT                                                           28
+  #define BMB_REG_INT_STS_CLR_0_MAC0_FC_CNT_ERROR                                                            (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_0_MAC0_FC_CNT_ERROR_SHIFT                                                      31
+#define BMB_REG_INT_STS_1                                                                                    0x5400d8UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_1_LL_ARB_CALC_ERROR                                                                (0x1<<1) // Calculations error in LL arbiter block.
+  #define BMB_REG_INT_STS_1_LL_ARB_CALC_ERROR_SHIFT                                                          1
+  #define BMB_REG_INT_STS_1_WC0_INP_FIFO_ERROR                                                               (0x1<<3) // Input FIFO error in write client 0.
+  #define BMB_REG_INT_STS_1_WC0_INP_FIFO_ERROR_SHIFT                                                         3
+  #define BMB_REG_INT_STS_1_WC0_SOP_FIFO_ERROR                                                               (0x1<<4) // SOP FIFO error in write client 0.
+  #define BMB_REG_INT_STS_1_WC0_SOP_FIFO_ERROR_SHIFT                                                         4
+  #define BMB_REG_INT_STS_1_WC0_LEN_FIFO_ERROR                                                               (0x1<<5) // LEN FIFO error in write client 0.
+  #define BMB_REG_INT_STS_1_WC0_LEN_FIFO_ERROR_SHIFT                                                         5
+  #define BMB_REG_INT_STS_1_WC0_QUEUE_FIFO_ERROR                                                             (0x1<<7) // Queue FIFO error in write client 0.
+  #define BMB_REG_INT_STS_1_WC0_QUEUE_FIFO_ERROR_SHIFT                                                       7
+  #define BMB_REG_INT_STS_1_WC0_FREE_POINT_FIFO_ERROR                                                        (0x1<<8) // Free ointer FIFO error in write client 0.
+  #define BMB_REG_INT_STS_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT                                                  8
+  #define BMB_REG_INT_STS_1_WC0_NEXT_POINT_FIFO_ERROR                                                        (0x1<<9) // Next pointer FIFO error in write client 0.
+  #define BMB_REG_INT_STS_1_WC0_NEXT_POINT_FIFO_ERROR_SHIFT                                                  9
+  #define BMB_REG_INT_STS_1_WC0_STRT_FIFO_ERROR                                                              (0x1<<10) // Start FIFO error in write client 0.
+  #define BMB_REG_INT_STS_1_WC0_STRT_FIFO_ERROR_SHIFT                                                        10
+  #define BMB_REG_INT_STS_1_WC0_SECOND_DSCR_FIFO_ERROR                                                       (0x1<<11) // Second descriptor FIFO error in write client 0.
+  #define BMB_REG_INT_STS_1_WC0_SECOND_DSCR_FIFO_ERROR_SHIFT                                                 11
+  #define BMB_REG_INT_STS_1_WC0_PKT_AVAIL_FIFO_ERROR                                                         (0x1<<12) // Packet available FIFO error in write client 0.
+  #define BMB_REG_INT_STS_1_WC0_PKT_AVAIL_FIFO_ERROR_SHIFT                                                   12
+  #define BMB_REG_INT_STS_1_WC0_COS_CNT_FIFO_ERROR                                                           (0x1<<13) // COS counter FIFO error in write client 0 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_1_WC0_COS_CNT_FIFO_ERROR_SHIFT                                                     13
+  #define BMB_REG_INT_STS_1_WC0_NOTIFY_FIFO_ERROR                                                            (0x1<<14) // Notify FIFO error in write client 0.
+  #define BMB_REG_INT_STS_1_WC0_NOTIFY_FIFO_ERROR_SHIFT                                                      14
+  #define BMB_REG_INT_STS_1_WC0_LL_REQ_FIFO_ERROR                                                            (0x1<<15) // LL req error in write client 0.
+  #define BMB_REG_INT_STS_1_WC0_LL_REQ_FIFO_ERROR_SHIFT                                                      15
+  #define BMB_REG_INT_STS_1_WC0_LL_PA_CNT_ERROR                                                              (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
+  #define BMB_REG_INT_STS_1_WC0_LL_PA_CNT_ERROR_SHIFT                                                        16
+  #define BMB_REG_INT_STS_1_WC0_BB_PA_CNT_ERROR                                                              (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
+  #define BMB_REG_INT_STS_1_WC0_BB_PA_CNT_ERROR_SHIFT                                                        17
+  #define BMB_REG_INT_STS_1_WC1_INP_FIFO_ERROR                                                               (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_1_WC1_INP_FIFO_ERROR_SHIFT                                                         18
+  #define BMB_REG_INT_STS_1_WC1_SOP_FIFO_ERROR                                                               (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_1_WC1_SOP_FIFO_ERROR_SHIFT                                                         19
+  #define BMB_REG_INT_STS_1_WC1_QUEUE_FIFO_ERROR                                                             (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_1_WC1_QUEUE_FIFO_ERROR_SHIFT                                                       21
+  #define BMB_REG_INT_STS_1_WC1_FREE_POINT_FIFO_ERROR                                                        (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_1_WC1_FREE_POINT_FIFO_ERROR_SHIFT                                                  22
+  #define BMB_REG_INT_STS_1_WC1_NEXT_POINT_FIFO_ERROR                                                        (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_1_WC1_NEXT_POINT_FIFO_ERROR_SHIFT                                                  23
+  #define BMB_REG_INT_STS_1_WC1_STRT_FIFO_ERROR                                                              (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_1_WC1_STRT_FIFO_ERROR_SHIFT                                                        24
+  #define BMB_REG_INT_STS_1_WC1_SECOND_DSCR_FIFO_ERROR                                                       (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_1_WC1_SECOND_DSCR_FIFO_ERROR_SHIFT                                                 25
+  #define BMB_REG_INT_STS_1_WC1_PKT_AVAIL_FIFO_ERROR                                                         (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 1 RX_INT ::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_1_WC1_PKT_AVAIL_FIFO_ERROR_SHIFT                                                   26
+  #define BMB_REG_INT_STS_1_WC1_COS_CNT_FIFO_ERROR                                                           (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_1_WC1_COS_CNT_FIFO_ERROR_SHIFT                                                     27
+  #define BMB_REG_INT_STS_1_WC1_NOTIFY_FIFO_ERROR                                                            (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_1_WC1_NOTIFY_FIFO_ERROR_SHIFT                                                      28
+  #define BMB_REG_INT_STS_1_WC1_LL_REQ_FIFO_ERROR                                                            (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_1_WC1_LL_REQ_FIFO_ERROR_SHIFT                                                      29
+  #define BMB_REG_INT_STS_1_WC1_LL_PA_CNT_ERROR                                                              (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_1_WC1_LL_PA_CNT_ERROR_SHIFT                                                        30
+  #define BMB_REG_INT_STS_1_WC1_BB_PA_CNT_ERROR                                                              (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_1_WC1_BB_PA_CNT_ERROR_SHIFT                                                        31
+#define BMB_REG_INT_MASK_1                                                                                   0x5400dcUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_MASK_1_LL_ARB_CALC_ERROR                                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.LL_ARB_CALC_ERROR .
+  #define BMB_REG_INT_MASK_1_LL_ARB_CALC_ERROR_SHIFT                                                         1
+  #define BMB_REG_INT_MASK_1_WC0_INP_FIFO_ERROR                                                              (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_INP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_1_WC0_INP_FIFO_ERROR_SHIFT                                                        3
+  #define BMB_REG_INT_MASK_1_WC0_SOP_FIFO_ERROR                                                              (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_SOP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_1_WC0_SOP_FIFO_ERROR_SHIFT                                                        4
+  #define BMB_REG_INT_MASK_1_WC0_LEN_FIFO_ERROR                                                              (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_LEN_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_1_WC0_LEN_FIFO_ERROR_SHIFT                                                        5
+  #define BMB_REG_INT_MASK_1_WC0_QUEUE_FIFO_ERROR                                                            (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_QUEUE_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_1_WC0_QUEUE_FIFO_ERROR_SHIFT                                                      7
+  #define BMB_REG_INT_MASK_1_WC0_FREE_POINT_FIFO_ERROR                                                       (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_FREE_POINT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT                                                 8
+  #define BMB_REG_INT_MASK_1_WC0_NEXT_POINT_FIFO_ERROR                                                       (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_NEXT_POINT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_1_WC0_NEXT_POINT_FIFO_ERROR_SHIFT                                                 9
+  #define BMB_REG_INT_MASK_1_WC0_STRT_FIFO_ERROR                                                             (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_STRT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_1_WC0_STRT_FIFO_ERROR_SHIFT                                                       10
+  #define BMB_REG_INT_MASK_1_WC0_SECOND_DSCR_FIFO_ERROR                                                      (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_SECOND_DSCR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_1_WC0_SECOND_DSCR_FIFO_ERROR_SHIFT                                                11
+  #define BMB_REG_INT_MASK_1_WC0_PKT_AVAIL_FIFO_ERROR                                                        (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_PKT_AVAIL_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_1_WC0_PKT_AVAIL_FIFO_ERROR_SHIFT                                                  12
+  #define BMB_REG_INT_MASK_1_WC0_COS_CNT_FIFO_ERROR                                                          (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_COS_CNT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_1_WC0_COS_CNT_FIFO_ERROR_SHIFT                                                    13
+  #define BMB_REG_INT_MASK_1_WC0_NOTIFY_FIFO_ERROR                                                           (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_NOTIFY_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_1_WC0_NOTIFY_FIFO_ERROR_SHIFT                                                     14
+  #define BMB_REG_INT_MASK_1_WC0_LL_REQ_FIFO_ERROR                                                           (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_LL_REQ_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_1_WC0_LL_REQ_FIFO_ERROR_SHIFT                                                     15
+  #define BMB_REG_INT_MASK_1_WC0_LL_PA_CNT_ERROR                                                             (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_LL_PA_CNT_ERROR .
+  #define BMB_REG_INT_MASK_1_WC0_LL_PA_CNT_ERROR_SHIFT                                                       16
+  #define BMB_REG_INT_MASK_1_WC0_BB_PA_CNT_ERROR                                                             (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_BB_PA_CNT_ERROR .
+  #define BMB_REG_INT_MASK_1_WC0_BB_PA_CNT_ERROR_SHIFT                                                       17
+  #define BMB_REG_INT_MASK_1_WC1_INP_FIFO_ERROR                                                              (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_INP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_1_WC1_INP_FIFO_ERROR_SHIFT                                                        18
+  #define BMB_REG_INT_MASK_1_WC1_SOP_FIFO_ERROR                                                              (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_SOP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_1_WC1_SOP_FIFO_ERROR_SHIFT                                                        19
+  #define BMB_REG_INT_MASK_1_WC1_QUEUE_FIFO_ERROR                                                            (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_QUEUE_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_1_WC1_QUEUE_FIFO_ERROR_SHIFT                                                      21
+  #define BMB_REG_INT_MASK_1_WC1_FREE_POINT_FIFO_ERROR                                                       (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_FREE_POINT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_1_WC1_FREE_POINT_FIFO_ERROR_SHIFT                                                 22
+  #define BMB_REG_INT_MASK_1_WC1_NEXT_POINT_FIFO_ERROR                                                       (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_NEXT_POINT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_1_WC1_NEXT_POINT_FIFO_ERROR_SHIFT                                                 23
+  #define BMB_REG_INT_MASK_1_WC1_STRT_FIFO_ERROR                                                             (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_STRT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_1_WC1_STRT_FIFO_ERROR_SHIFT                                                       24
+  #define BMB_REG_INT_MASK_1_WC1_SECOND_DSCR_FIFO_ERROR                                                      (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_SECOND_DSCR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_1_WC1_SECOND_DSCR_FIFO_ERROR_SHIFT                                                25
+  #define BMB_REG_INT_MASK_1_WC1_PKT_AVAIL_FIFO_ERROR                                                        (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_PKT_AVAIL_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_1_WC1_PKT_AVAIL_FIFO_ERROR_SHIFT                                                  26
+  #define BMB_REG_INT_MASK_1_WC1_COS_CNT_FIFO_ERROR                                                          (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_COS_CNT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_1_WC1_COS_CNT_FIFO_ERROR_SHIFT                                                    27
+  #define BMB_REG_INT_MASK_1_WC1_NOTIFY_FIFO_ERROR                                                           (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_NOTIFY_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_1_WC1_NOTIFY_FIFO_ERROR_SHIFT                                                     28
+  #define BMB_REG_INT_MASK_1_WC1_LL_REQ_FIFO_ERROR                                                           (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_LL_REQ_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_1_WC1_LL_REQ_FIFO_ERROR_SHIFT                                                     29
+  #define BMB_REG_INT_MASK_1_WC1_LL_PA_CNT_ERROR                                                             (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_LL_PA_CNT_ERROR .
+  #define BMB_REG_INT_MASK_1_WC1_LL_PA_CNT_ERROR_SHIFT                                                       30
+  #define BMB_REG_INT_MASK_1_WC1_BB_PA_CNT_ERROR                                                             (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_BB_PA_CNT_ERROR .
+  #define BMB_REG_INT_MASK_1_WC1_BB_PA_CNT_ERROR_SHIFT                                                       31
+#define BMB_REG_INT_STS_WR_1                                                                                 0x5400e0UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_WR_1_LL_ARB_CALC_ERROR                                                             (0x1<<1) // Calculations error in LL arbiter block.
+  #define BMB_REG_INT_STS_WR_1_LL_ARB_CALC_ERROR_SHIFT                                                       1
+  #define BMB_REG_INT_STS_WR_1_WC0_INP_FIFO_ERROR                                                            (0x1<<3) // Input FIFO error in write client 0.
+  #define BMB_REG_INT_STS_WR_1_WC0_INP_FIFO_ERROR_SHIFT                                                      3
+  #define BMB_REG_INT_STS_WR_1_WC0_SOP_FIFO_ERROR                                                            (0x1<<4) // SOP FIFO error in write client 0.
+  #define BMB_REG_INT_STS_WR_1_WC0_SOP_FIFO_ERROR_SHIFT                                                      4
+  #define BMB_REG_INT_STS_WR_1_WC0_LEN_FIFO_ERROR                                                            (0x1<<5) // LEN FIFO error in write client 0.
+  #define BMB_REG_INT_STS_WR_1_WC0_LEN_FIFO_ERROR_SHIFT                                                      5
+  #define BMB_REG_INT_STS_WR_1_WC0_QUEUE_FIFO_ERROR                                                          (0x1<<7) // Queue FIFO error in write client 0.
+  #define BMB_REG_INT_STS_WR_1_WC0_QUEUE_FIFO_ERROR_SHIFT                                                    7
+  #define BMB_REG_INT_STS_WR_1_WC0_FREE_POINT_FIFO_ERROR                                                     (0x1<<8) // Free ointer FIFO error in write client 0.
+  #define BMB_REG_INT_STS_WR_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT                                               8
+  #define BMB_REG_INT_STS_WR_1_WC0_NEXT_POINT_FIFO_ERROR                                                     (0x1<<9) // Next pointer FIFO error in write client 0.
+  #define BMB_REG_INT_STS_WR_1_WC0_NEXT_POINT_FIFO_ERROR_SHIFT                                               9
+  #define BMB_REG_INT_STS_WR_1_WC0_STRT_FIFO_ERROR                                                           (0x1<<10) // Start FIFO error in write client 0.
+  #define BMB_REG_INT_STS_WR_1_WC0_STRT_FIFO_ERROR_SHIFT                                                     10
+  #define BMB_REG_INT_STS_WR_1_WC0_SECOND_DSCR_FIFO_ERROR                                                    (0x1<<11) // Second descriptor FIFO error in write client 0.
+  #define BMB_REG_INT_STS_WR_1_WC0_SECOND_DSCR_FIFO_ERROR_SHIFT                                              11
+  #define BMB_REG_INT_STS_WR_1_WC0_PKT_AVAIL_FIFO_ERROR                                                      (0x1<<12) // Packet available FIFO error in write client 0.
+  #define BMB_REG_INT_STS_WR_1_WC0_PKT_AVAIL_FIFO_ERROR_SHIFT                                                12
+  #define BMB_REG_INT_STS_WR_1_WC0_COS_CNT_FIFO_ERROR                                                        (0x1<<13) // COS counter FIFO error in write client 0 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_1_WC0_COS_CNT_FIFO_ERROR_SHIFT                                                  13
+  #define BMB_REG_INT_STS_WR_1_WC0_NOTIFY_FIFO_ERROR                                                         (0x1<<14) // Notify FIFO error in write client 0.
+  #define BMB_REG_INT_STS_WR_1_WC0_NOTIFY_FIFO_ERROR_SHIFT                                                   14
+  #define BMB_REG_INT_STS_WR_1_WC0_LL_REQ_FIFO_ERROR                                                         (0x1<<15) // LL req error in write client 0.
+  #define BMB_REG_INT_STS_WR_1_WC0_LL_REQ_FIFO_ERROR_SHIFT                                                   15
+  #define BMB_REG_INT_STS_WR_1_WC0_LL_PA_CNT_ERROR                                                           (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
+  #define BMB_REG_INT_STS_WR_1_WC0_LL_PA_CNT_ERROR_SHIFT                                                     16
+  #define BMB_REG_INT_STS_WR_1_WC0_BB_PA_CNT_ERROR                                                           (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
+  #define BMB_REG_INT_STS_WR_1_WC0_BB_PA_CNT_ERROR_SHIFT                                                     17
+  #define BMB_REG_INT_STS_WR_1_WC1_INP_FIFO_ERROR                                                            (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_1_WC1_INP_FIFO_ERROR_SHIFT                                                      18
+  #define BMB_REG_INT_STS_WR_1_WC1_SOP_FIFO_ERROR                                                            (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_1_WC1_SOP_FIFO_ERROR_SHIFT                                                      19
+  #define BMB_REG_INT_STS_WR_1_WC1_QUEUE_FIFO_ERROR                                                          (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_1_WC1_QUEUE_FIFO_ERROR_SHIFT                                                    21
+  #define BMB_REG_INT_STS_WR_1_WC1_FREE_POINT_FIFO_ERROR                                                     (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_1_WC1_FREE_POINT_FIFO_ERROR_SHIFT                                               22
+  #define BMB_REG_INT_STS_WR_1_WC1_NEXT_POINT_FIFO_ERROR                                                     (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_1_WC1_NEXT_POINT_FIFO_ERROR_SHIFT                                               23
+  #define BMB_REG_INT_STS_WR_1_WC1_STRT_FIFO_ERROR                                                           (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_1_WC1_STRT_FIFO_ERROR_SHIFT                                                     24
+  #define BMB_REG_INT_STS_WR_1_WC1_SECOND_DSCR_FIFO_ERROR                                                    (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_1_WC1_SECOND_DSCR_FIFO_ERROR_SHIFT                                              25
+  #define BMB_REG_INT_STS_WR_1_WC1_PKT_AVAIL_FIFO_ERROR                                                      (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 1 RX_INT ::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_1_WC1_PKT_AVAIL_FIFO_ERROR_SHIFT                                                26
+  #define BMB_REG_INT_STS_WR_1_WC1_COS_CNT_FIFO_ERROR                                                        (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_1_WC1_COS_CNT_FIFO_ERROR_SHIFT                                                  27
+  #define BMB_REG_INT_STS_WR_1_WC1_NOTIFY_FIFO_ERROR                                                         (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_1_WC1_NOTIFY_FIFO_ERROR_SHIFT                                                   28
+  #define BMB_REG_INT_STS_WR_1_WC1_LL_REQ_FIFO_ERROR                                                         (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_1_WC1_LL_REQ_FIFO_ERROR_SHIFT                                                   29
+  #define BMB_REG_INT_STS_WR_1_WC1_LL_PA_CNT_ERROR                                                           (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_1_WC1_LL_PA_CNT_ERROR_SHIFT                                                     30
+  #define BMB_REG_INT_STS_WR_1_WC1_BB_PA_CNT_ERROR                                                           (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_1_WC1_BB_PA_CNT_ERROR_SHIFT                                                     31
+#define BMB_REG_INT_STS_CLR_1                                                                                0x5400e4UL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_CLR_1_LL_ARB_CALC_ERROR                                                            (0x1<<1) // Calculations error in LL arbiter block.
+  #define BMB_REG_INT_STS_CLR_1_LL_ARB_CALC_ERROR_SHIFT                                                      1
+  #define BMB_REG_INT_STS_CLR_1_WC0_INP_FIFO_ERROR                                                           (0x1<<3) // Input FIFO error in write client 0.
+  #define BMB_REG_INT_STS_CLR_1_WC0_INP_FIFO_ERROR_SHIFT                                                     3
+  #define BMB_REG_INT_STS_CLR_1_WC0_SOP_FIFO_ERROR                                                           (0x1<<4) // SOP FIFO error in write client 0.
+  #define BMB_REG_INT_STS_CLR_1_WC0_SOP_FIFO_ERROR_SHIFT                                                     4
+  #define BMB_REG_INT_STS_CLR_1_WC0_LEN_FIFO_ERROR                                                           (0x1<<5) // LEN FIFO error in write client 0.
+  #define BMB_REG_INT_STS_CLR_1_WC0_LEN_FIFO_ERROR_SHIFT                                                     5
+  #define BMB_REG_INT_STS_CLR_1_WC0_QUEUE_FIFO_ERROR                                                         (0x1<<7) // Queue FIFO error in write client 0.
+  #define BMB_REG_INT_STS_CLR_1_WC0_QUEUE_FIFO_ERROR_SHIFT                                                   7
+  #define BMB_REG_INT_STS_CLR_1_WC0_FREE_POINT_FIFO_ERROR                                                    (0x1<<8) // Free ointer FIFO error in write client 0.
+  #define BMB_REG_INT_STS_CLR_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT                                              8
+  #define BMB_REG_INT_STS_CLR_1_WC0_NEXT_POINT_FIFO_ERROR                                                    (0x1<<9) // Next pointer FIFO error in write client 0.
+  #define BMB_REG_INT_STS_CLR_1_WC0_NEXT_POINT_FIFO_ERROR_SHIFT                                              9
+  #define BMB_REG_INT_STS_CLR_1_WC0_STRT_FIFO_ERROR                                                          (0x1<<10) // Start FIFO error in write client 0.
+  #define BMB_REG_INT_STS_CLR_1_WC0_STRT_FIFO_ERROR_SHIFT                                                    10
+  #define BMB_REG_INT_STS_CLR_1_WC0_SECOND_DSCR_FIFO_ERROR                                                   (0x1<<11) // Second descriptor FIFO error in write client 0.
+  #define BMB_REG_INT_STS_CLR_1_WC0_SECOND_DSCR_FIFO_ERROR_SHIFT                                             11
+  #define BMB_REG_INT_STS_CLR_1_WC0_PKT_AVAIL_FIFO_ERROR                                                     (0x1<<12) // Packet available FIFO error in write client 0.
+  #define BMB_REG_INT_STS_CLR_1_WC0_PKT_AVAIL_FIFO_ERROR_SHIFT                                               12
+  #define BMB_REG_INT_STS_CLR_1_WC0_COS_CNT_FIFO_ERROR                                                       (0x1<<13) // COS counter FIFO error in write client 0 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_1_WC0_COS_CNT_FIFO_ERROR_SHIFT                                                 13
+  #define BMB_REG_INT_STS_CLR_1_WC0_NOTIFY_FIFO_ERROR                                                        (0x1<<14) // Notify FIFO error in write client 0.
+  #define BMB_REG_INT_STS_CLR_1_WC0_NOTIFY_FIFO_ERROR_SHIFT                                                  14
+  #define BMB_REG_INT_STS_CLR_1_WC0_LL_REQ_FIFO_ERROR                                                        (0x1<<15) // LL req error in write client 0.
+  #define BMB_REG_INT_STS_CLR_1_WC0_LL_REQ_FIFO_ERROR_SHIFT                                                  15
+  #define BMB_REG_INT_STS_CLR_1_WC0_LL_PA_CNT_ERROR                                                          (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
+  #define BMB_REG_INT_STS_CLR_1_WC0_LL_PA_CNT_ERROR_SHIFT                                                    16
+  #define BMB_REG_INT_STS_CLR_1_WC0_BB_PA_CNT_ERROR                                                          (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
+  #define BMB_REG_INT_STS_CLR_1_WC0_BB_PA_CNT_ERROR_SHIFT                                                    17
+  #define BMB_REG_INT_STS_CLR_1_WC1_INP_FIFO_ERROR                                                           (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_1_WC1_INP_FIFO_ERROR_SHIFT                                                     18
+  #define BMB_REG_INT_STS_CLR_1_WC1_SOP_FIFO_ERROR                                                           (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_1_WC1_SOP_FIFO_ERROR_SHIFT                                                     19
+  #define BMB_REG_INT_STS_CLR_1_WC1_QUEUE_FIFO_ERROR                                                         (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_1_WC1_QUEUE_FIFO_ERROR_SHIFT                                                   21
+  #define BMB_REG_INT_STS_CLR_1_WC1_FREE_POINT_FIFO_ERROR                                                    (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_1_WC1_FREE_POINT_FIFO_ERROR_SHIFT                                              22
+  #define BMB_REG_INT_STS_CLR_1_WC1_NEXT_POINT_FIFO_ERROR                                                    (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_1_WC1_NEXT_POINT_FIFO_ERROR_SHIFT                                              23
+  #define BMB_REG_INT_STS_CLR_1_WC1_STRT_FIFO_ERROR                                                          (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_1_WC1_STRT_FIFO_ERROR_SHIFT                                                    24
+  #define BMB_REG_INT_STS_CLR_1_WC1_SECOND_DSCR_FIFO_ERROR                                                   (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_1_WC1_SECOND_DSCR_FIFO_ERROR_SHIFT                                             25
+  #define BMB_REG_INT_STS_CLR_1_WC1_PKT_AVAIL_FIFO_ERROR                                                     (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 1 RX_INT ::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_1_WC1_PKT_AVAIL_FIFO_ERROR_SHIFT                                               26
+  #define BMB_REG_INT_STS_CLR_1_WC1_COS_CNT_FIFO_ERROR                                                       (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_1_WC1_COS_CNT_FIFO_ERROR_SHIFT                                                 27
+  #define BMB_REG_INT_STS_CLR_1_WC1_NOTIFY_FIFO_ERROR                                                        (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_1_WC1_NOTIFY_FIFO_ERROR_SHIFT                                                  28
+  #define BMB_REG_INT_STS_CLR_1_WC1_LL_REQ_FIFO_ERROR                                                        (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 1 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_1_WC1_LL_REQ_FIFO_ERROR_SHIFT                                                  29
+  #define BMB_REG_INT_STS_CLR_1_WC1_LL_PA_CNT_ERROR                                                          (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_1_WC1_LL_PA_CNT_ERROR_SHIFT                                                    30
+  #define BMB_REG_INT_STS_CLR_1_WC1_BB_PA_CNT_ERROR                                                          (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_1_WC1_BB_PA_CNT_ERROR_SHIFT                                                    31
+#define BMB_REG_INT_STS_2                                                                                    0x5400f0UL //Access:R    DataWidth:0x1c   // Multi Field Register.
+  #define BMB_REG_INT_STS_2_WC2_INP_FIFO_ERROR                                                               (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC2_INP_FIFO_ERROR_SHIFT                                                         0
+  #define BMB_REG_INT_STS_2_WC2_SOP_FIFO_ERROR                                                               (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC2_SOP_FIFO_ERROR_SHIFT                                                         1
+  #define BMB_REG_INT_STS_2_WC2_QUEUE_FIFO_ERROR                                                             (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC2_QUEUE_FIFO_ERROR_SHIFT                                                       3
+  #define BMB_REG_INT_STS_2_WC2_FREE_POINT_FIFO_ERROR                                                        (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC2_FREE_POINT_FIFO_ERROR_SHIFT                                                  4
+  #define BMB_REG_INT_STS_2_WC2_NEXT_POINT_FIFO_ERROR                                                        (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC2_NEXT_POINT_FIFO_ERROR_SHIFT                                                  5
+  #define BMB_REG_INT_STS_2_WC2_STRT_FIFO_ERROR                                                              (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC2_STRT_FIFO_ERROR_SHIFT                                                        6
+  #define BMB_REG_INT_STS_2_WC2_SECOND_DSCR_FIFO_ERROR                                                       (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC2_SECOND_DSCR_FIFO_ERROR_SHIFT                                                 7
+  #define BMB_REG_INT_STS_2_WC2_PKT_AVAIL_FIFO_ERROR                                                         (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 2 RX_INT ::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC2_PKT_AVAIL_FIFO_ERROR_SHIFT                                                   8
+  #define BMB_REG_INT_STS_2_WC2_COS_CNT_FIFO_ERROR                                                           (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC2_COS_CNT_FIFO_ERROR_SHIFT                                                     9
+  #define BMB_REG_INT_STS_2_WC2_NOTIFY_FIFO_ERROR                                                            (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC2_NOTIFY_FIFO_ERROR_SHIFT                                                      10
+  #define BMB_REG_INT_STS_2_WC2_LL_REQ_FIFO_ERROR                                                            (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC2_LL_REQ_FIFO_ERROR_SHIFT                                                      11
+  #define BMB_REG_INT_STS_2_WC2_LL_PA_CNT_ERROR                                                              (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC2_LL_PA_CNT_ERROR_SHIFT                                                        12
+  #define BMB_REG_INT_STS_2_WC2_BB_PA_CNT_ERROR                                                              (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC2_BB_PA_CNT_ERROR_SHIFT                                                        13
+  #define BMB_REG_INT_STS_2_WC3_INP_FIFO_ERROR                                                               (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC3_INP_FIFO_ERROR_SHIFT                                                         14
+  #define BMB_REG_INT_STS_2_WC3_SOP_FIFO_ERROR                                                               (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC3_SOP_FIFO_ERROR_SHIFT                                                         15
+  #define BMB_REG_INT_STS_2_WC3_QUEUE_FIFO_ERROR                                                             (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC3_QUEUE_FIFO_ERROR_SHIFT                                                       17
+  #define BMB_REG_INT_STS_2_WC3_FREE_POINT_FIFO_ERROR                                                        (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC3_FREE_POINT_FIFO_ERROR_SHIFT                                                  18
+  #define BMB_REG_INT_STS_2_WC3_NEXT_POINT_FIFO_ERROR                                                        (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC3_NEXT_POINT_FIFO_ERROR_SHIFT                                                  19
+  #define BMB_REG_INT_STS_2_WC3_STRT_FIFO_ERROR                                                              (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC3_STRT_FIFO_ERROR_SHIFT                                                        20
+  #define BMB_REG_INT_STS_2_WC3_SECOND_DSCR_FIFO_ERROR                                                       (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC3_SECOND_DSCR_FIFO_ERROR_SHIFT                                                 21
+  #define BMB_REG_INT_STS_2_WC3_PKT_AVAIL_FIFO_ERROR                                                         (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 3 RX_INT ::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC3_PKT_AVAIL_FIFO_ERROR_SHIFT                                                   22
+  #define BMB_REG_INT_STS_2_WC3_COS_CNT_FIFO_ERROR                                                           (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC3_COS_CNT_FIFO_ERROR_SHIFT                                                     23
+  #define BMB_REG_INT_STS_2_WC3_NOTIFY_FIFO_ERROR                                                            (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC3_NOTIFY_FIFO_ERROR_SHIFT                                                      24
+  #define BMB_REG_INT_STS_2_WC3_LL_REQ_FIFO_ERROR                                                            (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC3_LL_REQ_FIFO_ERROR_SHIFT                                                      25
+  #define BMB_REG_INT_STS_2_WC3_LL_PA_CNT_ERROR                                                              (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC3_LL_PA_CNT_ERROR_SHIFT                                                        26
+  #define BMB_REG_INT_STS_2_WC3_BB_PA_CNT_ERROR                                                              (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_2_WC3_BB_PA_CNT_ERROR_SHIFT                                                        27
+#define BMB_REG_INT_MASK_2                                                                                   0x5400f4UL //Access:RW   DataWidth:0x1c   // Multi Field Register.
+  #define BMB_REG_INT_MASK_2_WC2_INP_FIFO_ERROR                                                              (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_INP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_2_WC2_INP_FIFO_ERROR_SHIFT                                                        0
+  #define BMB_REG_INT_MASK_2_WC2_SOP_FIFO_ERROR                                                              (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_SOP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_2_WC2_SOP_FIFO_ERROR_SHIFT                                                        1
+  #define BMB_REG_INT_MASK_2_WC2_QUEUE_FIFO_ERROR                                                            (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_QUEUE_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_2_WC2_QUEUE_FIFO_ERROR_SHIFT                                                      3
+  #define BMB_REG_INT_MASK_2_WC2_FREE_POINT_FIFO_ERROR                                                       (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_FREE_POINT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_2_WC2_FREE_POINT_FIFO_ERROR_SHIFT                                                 4
+  #define BMB_REG_INT_MASK_2_WC2_NEXT_POINT_FIFO_ERROR                                                       (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_NEXT_POINT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_2_WC2_NEXT_POINT_FIFO_ERROR_SHIFT                                                 5
+  #define BMB_REG_INT_MASK_2_WC2_STRT_FIFO_ERROR                                                             (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_STRT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_2_WC2_STRT_FIFO_ERROR_SHIFT                                                       6
+  #define BMB_REG_INT_MASK_2_WC2_SECOND_DSCR_FIFO_ERROR                                                      (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_SECOND_DSCR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_2_WC2_SECOND_DSCR_FIFO_ERROR_SHIFT                                                7
+  #define BMB_REG_INT_MASK_2_WC2_PKT_AVAIL_FIFO_ERROR                                                        (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_PKT_AVAIL_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_2_WC2_PKT_AVAIL_FIFO_ERROR_SHIFT                                                  8
+  #define BMB_REG_INT_MASK_2_WC2_COS_CNT_FIFO_ERROR                                                          (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_COS_CNT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_2_WC2_COS_CNT_FIFO_ERROR_SHIFT                                                    9
+  #define BMB_REG_INT_MASK_2_WC2_NOTIFY_FIFO_ERROR                                                           (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_NOTIFY_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_2_WC2_NOTIFY_FIFO_ERROR_SHIFT                                                     10
+  #define BMB_REG_INT_MASK_2_WC2_LL_REQ_FIFO_ERROR                                                           (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_LL_REQ_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_2_WC2_LL_REQ_FIFO_ERROR_SHIFT                                                     11
+  #define BMB_REG_INT_MASK_2_WC2_LL_PA_CNT_ERROR                                                             (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_LL_PA_CNT_ERROR .
+  #define BMB_REG_INT_MASK_2_WC2_LL_PA_CNT_ERROR_SHIFT                                                       12
+  #define BMB_REG_INT_MASK_2_WC2_BB_PA_CNT_ERROR                                                             (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_BB_PA_CNT_ERROR .
+  #define BMB_REG_INT_MASK_2_WC2_BB_PA_CNT_ERROR_SHIFT                                                       13
+  #define BMB_REG_INT_MASK_2_WC3_INP_FIFO_ERROR                                                              (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_INP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_2_WC3_INP_FIFO_ERROR_SHIFT                                                        14
+  #define BMB_REG_INT_MASK_2_WC3_SOP_FIFO_ERROR                                                              (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_SOP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_2_WC3_SOP_FIFO_ERROR_SHIFT                                                        15
+  #define BMB_REG_INT_MASK_2_WC3_QUEUE_FIFO_ERROR                                                            (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_QUEUE_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_2_WC3_QUEUE_FIFO_ERROR_SHIFT                                                      17
+  #define BMB_REG_INT_MASK_2_WC3_FREE_POINT_FIFO_ERROR                                                       (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_FREE_POINT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_2_WC3_FREE_POINT_FIFO_ERROR_SHIFT                                                 18
+  #define BMB_REG_INT_MASK_2_WC3_NEXT_POINT_FIFO_ERROR                                                       (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_NEXT_POINT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_2_WC3_NEXT_POINT_FIFO_ERROR_SHIFT                                                 19
+  #define BMB_REG_INT_MASK_2_WC3_STRT_FIFO_ERROR                                                             (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_STRT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_2_WC3_STRT_FIFO_ERROR_SHIFT                                                       20
+  #define BMB_REG_INT_MASK_2_WC3_SECOND_DSCR_FIFO_ERROR                                                      (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_SECOND_DSCR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_2_WC3_SECOND_DSCR_FIFO_ERROR_SHIFT                                                21
+  #define BMB_REG_INT_MASK_2_WC3_PKT_AVAIL_FIFO_ERROR                                                        (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_PKT_AVAIL_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_2_WC3_PKT_AVAIL_FIFO_ERROR_SHIFT                                                  22
+  #define BMB_REG_INT_MASK_2_WC3_COS_CNT_FIFO_ERROR                                                          (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_COS_CNT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_2_WC3_COS_CNT_FIFO_ERROR_SHIFT                                                    23
+  #define BMB_REG_INT_MASK_2_WC3_NOTIFY_FIFO_ERROR                                                           (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_NOTIFY_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_2_WC3_NOTIFY_FIFO_ERROR_SHIFT                                                     24
+  #define BMB_REG_INT_MASK_2_WC3_LL_REQ_FIFO_ERROR                                                           (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_LL_REQ_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_2_WC3_LL_REQ_FIFO_ERROR_SHIFT                                                     25
+  #define BMB_REG_INT_MASK_2_WC3_LL_PA_CNT_ERROR                                                             (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_LL_PA_CNT_ERROR .
+  #define BMB_REG_INT_MASK_2_WC3_LL_PA_CNT_ERROR_SHIFT                                                       26
+  #define BMB_REG_INT_MASK_2_WC3_BB_PA_CNT_ERROR                                                             (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_BB_PA_CNT_ERROR .
+  #define BMB_REG_INT_MASK_2_WC3_BB_PA_CNT_ERROR_SHIFT                                                       27
+#define BMB_REG_INT_STS_WR_2                                                                                 0x5400f8UL //Access:WR   DataWidth:0x1c   // Multi Field Register.
+  #define BMB_REG_INT_STS_WR_2_WC2_INP_FIFO_ERROR                                                            (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC2_INP_FIFO_ERROR_SHIFT                                                      0
+  #define BMB_REG_INT_STS_WR_2_WC2_SOP_FIFO_ERROR                                                            (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC2_SOP_FIFO_ERROR_SHIFT                                                      1
+  #define BMB_REG_INT_STS_WR_2_WC2_QUEUE_FIFO_ERROR                                                          (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC2_QUEUE_FIFO_ERROR_SHIFT                                                    3
+  #define BMB_REG_INT_STS_WR_2_WC2_FREE_POINT_FIFO_ERROR                                                     (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC2_FREE_POINT_FIFO_ERROR_SHIFT                                               4
+  #define BMB_REG_INT_STS_WR_2_WC2_NEXT_POINT_FIFO_ERROR                                                     (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC2_NEXT_POINT_FIFO_ERROR_SHIFT                                               5
+  #define BMB_REG_INT_STS_WR_2_WC2_STRT_FIFO_ERROR                                                           (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC2_STRT_FIFO_ERROR_SHIFT                                                     6
+  #define BMB_REG_INT_STS_WR_2_WC2_SECOND_DSCR_FIFO_ERROR                                                    (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC2_SECOND_DSCR_FIFO_ERROR_SHIFT                                              7
+  #define BMB_REG_INT_STS_WR_2_WC2_PKT_AVAIL_FIFO_ERROR                                                      (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 2 RX_INT ::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC2_PKT_AVAIL_FIFO_ERROR_SHIFT                                                8
+  #define BMB_REG_INT_STS_WR_2_WC2_COS_CNT_FIFO_ERROR                                                        (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC2_COS_CNT_FIFO_ERROR_SHIFT                                                  9
+  #define BMB_REG_INT_STS_WR_2_WC2_NOTIFY_FIFO_ERROR                                                         (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC2_NOTIFY_FIFO_ERROR_SHIFT                                                   10
+  #define BMB_REG_INT_STS_WR_2_WC2_LL_REQ_FIFO_ERROR                                                         (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC2_LL_REQ_FIFO_ERROR_SHIFT                                                   11
+  #define BMB_REG_INT_STS_WR_2_WC2_LL_PA_CNT_ERROR                                                           (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC2_LL_PA_CNT_ERROR_SHIFT                                                     12
+  #define BMB_REG_INT_STS_WR_2_WC2_BB_PA_CNT_ERROR                                                           (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC2_BB_PA_CNT_ERROR_SHIFT                                                     13
+  #define BMB_REG_INT_STS_WR_2_WC3_INP_FIFO_ERROR                                                            (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC3_INP_FIFO_ERROR_SHIFT                                                      14
+  #define BMB_REG_INT_STS_WR_2_WC3_SOP_FIFO_ERROR                                                            (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC3_SOP_FIFO_ERROR_SHIFT                                                      15
+  #define BMB_REG_INT_STS_WR_2_WC3_QUEUE_FIFO_ERROR                                                          (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC3_QUEUE_FIFO_ERROR_SHIFT                                                    17
+  #define BMB_REG_INT_STS_WR_2_WC3_FREE_POINT_FIFO_ERROR                                                     (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC3_FREE_POINT_FIFO_ERROR_SHIFT                                               18
+  #define BMB_REG_INT_STS_WR_2_WC3_NEXT_POINT_FIFO_ERROR                                                     (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC3_NEXT_POINT_FIFO_ERROR_SHIFT                                               19
+  #define BMB_REG_INT_STS_WR_2_WC3_STRT_FIFO_ERROR                                                           (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC3_STRT_FIFO_ERROR_SHIFT                                                     20
+  #define BMB_REG_INT_STS_WR_2_WC3_SECOND_DSCR_FIFO_ERROR                                                    (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC3_SECOND_DSCR_FIFO_ERROR_SHIFT                                              21
+  #define BMB_REG_INT_STS_WR_2_WC3_PKT_AVAIL_FIFO_ERROR                                                      (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 3 RX_INT ::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC3_PKT_AVAIL_FIFO_ERROR_SHIFT                                                22
+  #define BMB_REG_INT_STS_WR_2_WC3_COS_CNT_FIFO_ERROR                                                        (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC3_COS_CNT_FIFO_ERROR_SHIFT                                                  23
+  #define BMB_REG_INT_STS_WR_2_WC3_NOTIFY_FIFO_ERROR                                                         (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC3_NOTIFY_FIFO_ERROR_SHIFT                                                   24
+  #define BMB_REG_INT_STS_WR_2_WC3_LL_REQ_FIFO_ERROR                                                         (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC3_LL_REQ_FIFO_ERROR_SHIFT                                                   25
+  #define BMB_REG_INT_STS_WR_2_WC3_LL_PA_CNT_ERROR                                                           (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC3_LL_PA_CNT_ERROR_SHIFT                                                     26
+  #define BMB_REG_INT_STS_WR_2_WC3_BB_PA_CNT_ERROR                                                           (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_2_WC3_BB_PA_CNT_ERROR_SHIFT                                                     27
+#define BMB_REG_INT_STS_CLR_2                                                                                0x5400fcUL //Access:RC   DataWidth:0x1c   // Multi Field Register.
+  #define BMB_REG_INT_STS_CLR_2_WC2_INP_FIFO_ERROR                                                           (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC2_INP_FIFO_ERROR_SHIFT                                                     0
+  #define BMB_REG_INT_STS_CLR_2_WC2_SOP_FIFO_ERROR                                                           (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC2_SOP_FIFO_ERROR_SHIFT                                                     1
+  #define BMB_REG_INT_STS_CLR_2_WC2_QUEUE_FIFO_ERROR                                                         (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC2_QUEUE_FIFO_ERROR_SHIFT                                                   3
+  #define BMB_REG_INT_STS_CLR_2_WC2_FREE_POINT_FIFO_ERROR                                                    (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC2_FREE_POINT_FIFO_ERROR_SHIFT                                              4
+  #define BMB_REG_INT_STS_CLR_2_WC2_NEXT_POINT_FIFO_ERROR                                                    (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC2_NEXT_POINT_FIFO_ERROR_SHIFT                                              5
+  #define BMB_REG_INT_STS_CLR_2_WC2_STRT_FIFO_ERROR                                                          (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC2_STRT_FIFO_ERROR_SHIFT                                                    6
+  #define BMB_REG_INT_STS_CLR_2_WC2_SECOND_DSCR_FIFO_ERROR                                                   (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC2_SECOND_DSCR_FIFO_ERROR_SHIFT                                             7
+  #define BMB_REG_INT_STS_CLR_2_WC2_PKT_AVAIL_FIFO_ERROR                                                     (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 2 RX_INT ::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC2_PKT_AVAIL_FIFO_ERROR_SHIFT                                               8
+  #define BMB_REG_INT_STS_CLR_2_WC2_COS_CNT_FIFO_ERROR                                                       (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC2_COS_CNT_FIFO_ERROR_SHIFT                                                 9
+  #define BMB_REG_INT_STS_CLR_2_WC2_NOTIFY_FIFO_ERROR                                                        (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC2_NOTIFY_FIFO_ERROR_SHIFT                                                  10
+  #define BMB_REG_INT_STS_CLR_2_WC2_LL_REQ_FIFO_ERROR                                                        (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC2_LL_REQ_FIFO_ERROR_SHIFT                                                  11
+  #define BMB_REG_INT_STS_CLR_2_WC2_LL_PA_CNT_ERROR                                                          (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC2_LL_PA_CNT_ERROR_SHIFT                                                    12
+  #define BMB_REG_INT_STS_CLR_2_WC2_BB_PA_CNT_ERROR                                                          (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 2 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC2_BB_PA_CNT_ERROR_SHIFT                                                    13
+  #define BMB_REG_INT_STS_CLR_2_WC3_INP_FIFO_ERROR                                                           (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC3_INP_FIFO_ERROR_SHIFT                                                     14
+  #define BMB_REG_INT_STS_CLR_2_WC3_SOP_FIFO_ERROR                                                           (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC3_SOP_FIFO_ERROR_SHIFT                                                     15
+  #define BMB_REG_INT_STS_CLR_2_WC3_QUEUE_FIFO_ERROR                                                         (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC3_QUEUE_FIFO_ERROR_SHIFT                                                   17
+  #define BMB_REG_INT_STS_CLR_2_WC3_FREE_POINT_FIFO_ERROR                                                    (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC3_FREE_POINT_FIFO_ERROR_SHIFT                                              18
+  #define BMB_REG_INT_STS_CLR_2_WC3_NEXT_POINT_FIFO_ERROR                                                    (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC3_NEXT_POINT_FIFO_ERROR_SHIFT                                              19
+  #define BMB_REG_INT_STS_CLR_2_WC3_STRT_FIFO_ERROR                                                          (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC3_STRT_FIFO_ERROR_SHIFT                                                    20
+  #define BMB_REG_INT_STS_CLR_2_WC3_SECOND_DSCR_FIFO_ERROR                                                   (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC3_SECOND_DSCR_FIFO_ERROR_SHIFT                                             21
+  #define BMB_REG_INT_STS_CLR_2_WC3_PKT_AVAIL_FIFO_ERROR                                                     (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 3 RX_INT ::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC3_PKT_AVAIL_FIFO_ERROR_SHIFT                                               22
+  #define BMB_REG_INT_STS_CLR_2_WC3_COS_CNT_FIFO_ERROR                                                       (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC3_COS_CNT_FIFO_ERROR_SHIFT                                                 23
+  #define BMB_REG_INT_STS_CLR_2_WC3_NOTIFY_FIFO_ERROR                                                        (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC3_NOTIFY_FIFO_ERROR_SHIFT                                                  24
+  #define BMB_REG_INT_STS_CLR_2_WC3_LL_REQ_FIFO_ERROR                                                        (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC3_LL_REQ_FIFO_ERROR_SHIFT                                                  25
+  #define BMB_REG_INT_STS_CLR_2_WC3_LL_PA_CNT_ERROR                                                          (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC3_LL_PA_CNT_ERROR_SHIFT                                                    26
+  #define BMB_REG_INT_STS_CLR_2_WC3_BB_PA_CNT_ERROR                                                          (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 3 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_2_WC3_BB_PA_CNT_ERROR_SHIFT                                                    27
+#define BMB_REG_INT_STS_3                                                                                    0x540108UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_3_RC_PKT0_SIDE_FIFO_ERROR                                                          (0x1<<1) // Read packet client rc0 side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT                                                    1
+  #define BMB_REG_INT_STS_3_RC_PKT0_REQ_FIFO_ERROR                                                           (0x1<<2) // Read packet client rc0 request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT0_REQ_FIFO_ERROR_SHIFT                                                     2
+  #define BMB_REG_INT_STS_3_RC_PKT0_BLK_FIFO_ERROR                                                           (0x1<<3) // Read packet client rc0 block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT                                                     3
+  #define BMB_REG_INT_STS_3_RC_PKT0_RLS_LEFT_FIFO_ERROR                                                      (0x1<<4) // Read packet client rc0 releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT0_RLS_LEFT_FIFO_ERROR_SHIFT                                                4
+  #define BMB_REG_INT_STS_3_RC_PKT0_STRT_PTR_FIFO_ERROR                                                      (0x1<<5) // Read packet client rc0 start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT0_STRT_PTR_FIFO_ERROR_SHIFT                                                5
+  #define BMB_REG_INT_STS_3_RC_PKT0_SECOND_PTR_FIFO_ERROR                                                    (0x1<<6) // Read packet client rc0 second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT0_SECOND_PTR_FIFO_ERROR_SHIFT                                              6
+  #define BMB_REG_INT_STS_3_RC_PKT0_RSP_FIFO_ERROR                                                           (0x1<<7) // Read packet client rc0 response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT                                                     7
+  #define BMB_REG_INT_STS_3_RC_PKT0_DSCR_FIFO_ERROR                                                          (0x1<<8) // Read packet client rc0 descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT                                                    8
+  #define BMB_REG_INT_STS_3_RC_PKT1_SIDE_FIFO_ERROR                                                          (0x1<<9) // Read packet client rc1 side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT1_SIDE_FIFO_ERROR_SHIFT                                                    9
+  #define BMB_REG_INT_STS_3_RC_PKT1_REQ_FIFO_ERROR                                                           (0x1<<10) // Read packet client rc1 request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT1_REQ_FIFO_ERROR_SHIFT                                                     10
+  #define BMB_REG_INT_STS_3_RC_PKT1_BLK_FIFO_ERROR                                                           (0x1<<11) // Read packet client rc1 block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT1_BLK_FIFO_ERROR_SHIFT                                                     11
+  #define BMB_REG_INT_STS_3_RC_PKT1_RLS_LEFT_FIFO_ERROR                                                      (0x1<<12) // Read packet client rc1 releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT1_RLS_LEFT_FIFO_ERROR_SHIFT                                                12
+  #define BMB_REG_INT_STS_3_RC_PKT1_STRT_PTR_FIFO_ERROR                                                      (0x1<<13) // Read packet client rc1 start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT1_STRT_PTR_FIFO_ERROR_SHIFT                                                13
+  #define BMB_REG_INT_STS_3_RC_PKT1_SECOND_PTR_FIFO_ERROR                                                    (0x1<<14) // Read packet client rc1 second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT1_SECOND_PTR_FIFO_ERROR_SHIFT                                              14
+  #define BMB_REG_INT_STS_3_RC_PKT1_RSP_FIFO_ERROR                                                           (0x1<<15) // Read packet client rc1 response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT1_RSP_FIFO_ERROR_SHIFT                                                     15
+  #define BMB_REG_INT_STS_3_RC_PKT1_DSCR_FIFO_ERROR                                                          (0x1<<16) // Read packet client rc1 descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT1_DSCR_FIFO_ERROR_SHIFT                                                    16
+  #define BMB_REG_INT_STS_3_RC_PKT2_SIDE_FIFO_ERROR                                                          (0x1<<17) // Read packet client rc2 side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT2_SIDE_FIFO_ERROR_SHIFT                                                    17
+  #define BMB_REG_INT_STS_3_RC_PKT2_REQ_FIFO_ERROR                                                           (0x1<<18) // Read packet client rc2 request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT2_REQ_FIFO_ERROR_SHIFT                                                     18
+  #define BMB_REG_INT_STS_3_RC_PKT2_BLK_FIFO_ERROR                                                           (0x1<<19) // Read packet client rc2 block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT2_BLK_FIFO_ERROR_SHIFT                                                     19
+  #define BMB_REG_INT_STS_3_RC_PKT2_RLS_LEFT_FIFO_ERROR                                                      (0x1<<20) // Read packet client rc2 releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT2_RLS_LEFT_FIFO_ERROR_SHIFT                                                20
+  #define BMB_REG_INT_STS_3_RC_PKT2_STRT_PTR_FIFO_ERROR                                                      (0x1<<21) // Read packet client rc2 start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT2_STRT_PTR_FIFO_ERROR_SHIFT                                                21
+  #define BMB_REG_INT_STS_3_RC_PKT2_SECOND_PTR_FIFO_ERROR                                                    (0x1<<22) // Read packet client rc2 second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT2_SECOND_PTR_FIFO_ERROR_SHIFT                                              22
+  #define BMB_REG_INT_STS_3_RC_PKT2_RSP_FIFO_ERROR                                                           (0x1<<23) // Read packet client rc2 response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT2_RSP_FIFO_ERROR_SHIFT                                                     23
+  #define BMB_REG_INT_STS_3_RC_PKT2_DSCR_FIFO_ERROR                                                          (0x1<<24) // Read packet client rc2 descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT2_DSCR_FIFO_ERROR_SHIFT                                                    24
+  #define BMB_REG_INT_STS_3_RC_PKT3_SIDE_FIFO_ERROR                                                          (0x1<<25) // Read packet client rc3 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT3_SIDE_FIFO_ERROR_SHIFT                                                    25
+  #define BMB_REG_INT_STS_3_RC_PKT3_REQ_FIFO_ERROR                                                           (0x1<<26) // Read packet client rc3 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT3_REQ_FIFO_ERROR_SHIFT                                                     26
+  #define BMB_REG_INT_STS_3_RC_PKT3_BLK_FIFO_ERROR                                                           (0x1<<27) // Read packet client rc3 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT3_BLK_FIFO_ERROR_SHIFT                                                     27
+  #define BMB_REG_INT_STS_3_RC_PKT3_RLS_LEFT_FIFO_ERROR                                                      (0x1<<28) // Read packet client rc3 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT3_RLS_LEFT_FIFO_ERROR_SHIFT                                                28
+  #define BMB_REG_INT_STS_3_RC_PKT3_STRT_PTR_FIFO_ERROR                                                      (0x1<<29) // Read packet client rc3 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT3_STRT_PTR_FIFO_ERROR_SHIFT                                                29
+  #define BMB_REG_INT_STS_3_RC_PKT3_SECOND_PTR_FIFO_ERROR                                                    (0x1<<30) // Read packet client rc3 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT                                              30
+  #define BMB_REG_INT_STS_3_RC_PKT3_RSP_FIFO_ERROR                                                           (0x1<<31) // Read packet client rc3 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_3_RC_PKT3_RSP_FIFO_ERROR_SHIFT                                                     31
+#define BMB_REG_INT_MASK_3                                                                                   0x54010cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_MASK_3_RC_PKT0_SIDE_FIFO_ERROR                                                         (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT0_SIDE_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT                                                   1
+  #define BMB_REG_INT_MASK_3_RC_PKT0_REQ_FIFO_ERROR                                                          (0x1<<2) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT0_REQ_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT0_REQ_FIFO_ERROR_SHIFT                                                    2
+  #define BMB_REG_INT_MASK_3_RC_PKT0_BLK_FIFO_ERROR                                                          (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT0_BLK_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT                                                    3
+  #define BMB_REG_INT_MASK_3_RC_PKT0_RLS_LEFT_FIFO_ERROR                                                     (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT0_RLS_LEFT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT0_RLS_LEFT_FIFO_ERROR_SHIFT                                               4
+  #define BMB_REG_INT_MASK_3_RC_PKT0_STRT_PTR_FIFO_ERROR                                                     (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT0_STRT_PTR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT0_STRT_PTR_FIFO_ERROR_SHIFT                                               5
+  #define BMB_REG_INT_MASK_3_RC_PKT0_SECOND_PTR_FIFO_ERROR                                                   (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT0_SECOND_PTR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT0_SECOND_PTR_FIFO_ERROR_SHIFT                                             6
+  #define BMB_REG_INT_MASK_3_RC_PKT0_RSP_FIFO_ERROR                                                          (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT0_RSP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT                                                    7
+  #define BMB_REG_INT_MASK_3_RC_PKT0_DSCR_FIFO_ERROR                                                         (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT0_DSCR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT                                                   8
+  #define BMB_REG_INT_MASK_3_RC_PKT1_SIDE_FIFO_ERROR                                                         (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT1_SIDE_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT1_SIDE_FIFO_ERROR_SHIFT                                                   9
+  #define BMB_REG_INT_MASK_3_RC_PKT1_REQ_FIFO_ERROR                                                          (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT1_REQ_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT1_REQ_FIFO_ERROR_SHIFT                                                    10
+  #define BMB_REG_INT_MASK_3_RC_PKT1_BLK_FIFO_ERROR                                                          (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT1_BLK_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT1_BLK_FIFO_ERROR_SHIFT                                                    11
+  #define BMB_REG_INT_MASK_3_RC_PKT1_RLS_LEFT_FIFO_ERROR                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT1_RLS_LEFT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT1_RLS_LEFT_FIFO_ERROR_SHIFT                                               12
+  #define BMB_REG_INT_MASK_3_RC_PKT1_STRT_PTR_FIFO_ERROR                                                     (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT1_STRT_PTR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT1_STRT_PTR_FIFO_ERROR_SHIFT                                               13
+  #define BMB_REG_INT_MASK_3_RC_PKT1_SECOND_PTR_FIFO_ERROR                                                   (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT1_SECOND_PTR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT1_SECOND_PTR_FIFO_ERROR_SHIFT                                             14
+  #define BMB_REG_INT_MASK_3_RC_PKT1_RSP_FIFO_ERROR                                                          (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT1_RSP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT1_RSP_FIFO_ERROR_SHIFT                                                    15
+  #define BMB_REG_INT_MASK_3_RC_PKT1_DSCR_FIFO_ERROR                                                         (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT1_DSCR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT1_DSCR_FIFO_ERROR_SHIFT                                                   16
+  #define BMB_REG_INT_MASK_3_RC_PKT2_SIDE_FIFO_ERROR                                                         (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT2_SIDE_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT2_SIDE_FIFO_ERROR_SHIFT                                                   17
+  #define BMB_REG_INT_MASK_3_RC_PKT2_REQ_FIFO_ERROR                                                          (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT2_REQ_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT2_REQ_FIFO_ERROR_SHIFT                                                    18
+  #define BMB_REG_INT_MASK_3_RC_PKT2_BLK_FIFO_ERROR                                                          (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT2_BLK_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT2_BLK_FIFO_ERROR_SHIFT                                                    19
+  #define BMB_REG_INT_MASK_3_RC_PKT2_RLS_LEFT_FIFO_ERROR                                                     (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT2_RLS_LEFT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT2_RLS_LEFT_FIFO_ERROR_SHIFT                                               20
+  #define BMB_REG_INT_MASK_3_RC_PKT2_STRT_PTR_FIFO_ERROR                                                     (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT2_STRT_PTR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT2_STRT_PTR_FIFO_ERROR_SHIFT                                               21
+  #define BMB_REG_INT_MASK_3_RC_PKT2_SECOND_PTR_FIFO_ERROR                                                   (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT2_SECOND_PTR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT2_SECOND_PTR_FIFO_ERROR_SHIFT                                             22
+  #define BMB_REG_INT_MASK_3_RC_PKT2_RSP_FIFO_ERROR                                                          (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT2_RSP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT2_RSP_FIFO_ERROR_SHIFT                                                    23
+  #define BMB_REG_INT_MASK_3_RC_PKT2_DSCR_FIFO_ERROR                                                         (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT2_DSCR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT2_DSCR_FIFO_ERROR_SHIFT                                                   24
+  #define BMB_REG_INT_MASK_3_RC_PKT3_SIDE_FIFO_ERROR                                                         (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT3_SIDE_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT3_SIDE_FIFO_ERROR_SHIFT                                                   25
+  #define BMB_REG_INT_MASK_3_RC_PKT3_REQ_FIFO_ERROR                                                          (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT3_REQ_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT3_REQ_FIFO_ERROR_SHIFT                                                    26
+  #define BMB_REG_INT_MASK_3_RC_PKT3_BLK_FIFO_ERROR                                                          (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT3_BLK_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT3_BLK_FIFO_ERROR_SHIFT                                                    27
+  #define BMB_REG_INT_MASK_3_RC_PKT3_RLS_LEFT_FIFO_ERROR                                                     (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT3_RLS_LEFT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT3_RLS_LEFT_FIFO_ERROR_SHIFT                                               28
+  #define BMB_REG_INT_MASK_3_RC_PKT3_STRT_PTR_FIFO_ERROR                                                     (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT3_STRT_PTR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT3_STRT_PTR_FIFO_ERROR_SHIFT                                               29
+  #define BMB_REG_INT_MASK_3_RC_PKT3_SECOND_PTR_FIFO_ERROR                                                   (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT3_SECOND_PTR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT                                             30
+  #define BMB_REG_INT_MASK_3_RC_PKT3_RSP_FIFO_ERROR                                                          (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT3_RSP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_3_RC_PKT3_RSP_FIFO_ERROR_SHIFT                                                    31
+#define BMB_REG_INT_STS_WR_3                                                                                 0x540110UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT0_SIDE_FIFO_ERROR                                                       (0x1<<1) // Read packet client rc0 side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT                                                 1
+  #define BMB_REG_INT_STS_WR_3_RC_PKT0_REQ_FIFO_ERROR                                                        (0x1<<2) // Read packet client rc0 request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT0_REQ_FIFO_ERROR_SHIFT                                                  2
+  #define BMB_REG_INT_STS_WR_3_RC_PKT0_BLK_FIFO_ERROR                                                        (0x1<<3) // Read packet client rc0 block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT                                                  3
+  #define BMB_REG_INT_STS_WR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR                                                   (0x1<<4) // Read packet client rc0 releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR_SHIFT                                             4
+  #define BMB_REG_INT_STS_WR_3_RC_PKT0_STRT_PTR_FIFO_ERROR                                                   (0x1<<5) // Read packet client rc0 start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT0_STRT_PTR_FIFO_ERROR_SHIFT                                             5
+  #define BMB_REG_INT_STS_WR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR                                                 (0x1<<6) // Read packet client rc0 second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR_SHIFT                                           6
+  #define BMB_REG_INT_STS_WR_3_RC_PKT0_RSP_FIFO_ERROR                                                        (0x1<<7) // Read packet client rc0 response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT                                                  7
+  #define BMB_REG_INT_STS_WR_3_RC_PKT0_DSCR_FIFO_ERROR                                                       (0x1<<8) // Read packet client rc0 descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT                                                 8
+  #define BMB_REG_INT_STS_WR_3_RC_PKT1_SIDE_FIFO_ERROR                                                       (0x1<<9) // Read packet client rc1 side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT1_SIDE_FIFO_ERROR_SHIFT                                                 9
+  #define BMB_REG_INT_STS_WR_3_RC_PKT1_REQ_FIFO_ERROR                                                        (0x1<<10) // Read packet client rc1 request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT1_REQ_FIFO_ERROR_SHIFT                                                  10
+  #define BMB_REG_INT_STS_WR_3_RC_PKT1_BLK_FIFO_ERROR                                                        (0x1<<11) // Read packet client rc1 block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT1_BLK_FIFO_ERROR_SHIFT                                                  11
+  #define BMB_REG_INT_STS_WR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR                                                   (0x1<<12) // Read packet client rc1 releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR_SHIFT                                             12
+  #define BMB_REG_INT_STS_WR_3_RC_PKT1_STRT_PTR_FIFO_ERROR                                                   (0x1<<13) // Read packet client rc1 start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT1_STRT_PTR_FIFO_ERROR_SHIFT                                             13
+  #define BMB_REG_INT_STS_WR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR                                                 (0x1<<14) // Read packet client rc1 second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR_SHIFT                                           14
+  #define BMB_REG_INT_STS_WR_3_RC_PKT1_RSP_FIFO_ERROR                                                        (0x1<<15) // Read packet client rc1 response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT1_RSP_FIFO_ERROR_SHIFT                                                  15
+  #define BMB_REG_INT_STS_WR_3_RC_PKT1_DSCR_FIFO_ERROR                                                       (0x1<<16) // Read packet client rc1 descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT1_DSCR_FIFO_ERROR_SHIFT                                                 16
+  #define BMB_REG_INT_STS_WR_3_RC_PKT2_SIDE_FIFO_ERROR                                                       (0x1<<17) // Read packet client rc2 side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT2_SIDE_FIFO_ERROR_SHIFT                                                 17
+  #define BMB_REG_INT_STS_WR_3_RC_PKT2_REQ_FIFO_ERROR                                                        (0x1<<18) // Read packet client rc2 request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT2_REQ_FIFO_ERROR_SHIFT                                                  18
+  #define BMB_REG_INT_STS_WR_3_RC_PKT2_BLK_FIFO_ERROR                                                        (0x1<<19) // Read packet client rc2 block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT2_BLK_FIFO_ERROR_SHIFT                                                  19
+  #define BMB_REG_INT_STS_WR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR                                                   (0x1<<20) // Read packet client rc2 releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR_SHIFT                                             20
+  #define BMB_REG_INT_STS_WR_3_RC_PKT2_STRT_PTR_FIFO_ERROR                                                   (0x1<<21) // Read packet client rc2 start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT2_STRT_PTR_FIFO_ERROR_SHIFT                                             21
+  #define BMB_REG_INT_STS_WR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR                                                 (0x1<<22) // Read packet client rc2 second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR_SHIFT                                           22
+  #define BMB_REG_INT_STS_WR_3_RC_PKT2_RSP_FIFO_ERROR                                                        (0x1<<23) // Read packet client rc2 response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT2_RSP_FIFO_ERROR_SHIFT                                                  23
+  #define BMB_REG_INT_STS_WR_3_RC_PKT2_DSCR_FIFO_ERROR                                                       (0x1<<24) // Read packet client rc2 descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT2_DSCR_FIFO_ERROR_SHIFT                                                 24
+  #define BMB_REG_INT_STS_WR_3_RC_PKT3_SIDE_FIFO_ERROR                                                       (0x1<<25) // Read packet client rc3 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT3_SIDE_FIFO_ERROR_SHIFT                                                 25
+  #define BMB_REG_INT_STS_WR_3_RC_PKT3_REQ_FIFO_ERROR                                                        (0x1<<26) // Read packet client rc3 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT3_REQ_FIFO_ERROR_SHIFT                                                  26
+  #define BMB_REG_INT_STS_WR_3_RC_PKT3_BLK_FIFO_ERROR                                                        (0x1<<27) // Read packet client rc3 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT3_BLK_FIFO_ERROR_SHIFT                                                  27
+  #define BMB_REG_INT_STS_WR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR                                                   (0x1<<28) // Read packet client rc3 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR_SHIFT                                             28
+  #define BMB_REG_INT_STS_WR_3_RC_PKT3_STRT_PTR_FIFO_ERROR                                                   (0x1<<29) // Read packet client rc3 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT3_STRT_PTR_FIFO_ERROR_SHIFT                                             29
+  #define BMB_REG_INT_STS_WR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR                                                 (0x1<<30) // Read packet client rc3 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT                                           30
+  #define BMB_REG_INT_STS_WR_3_RC_PKT3_RSP_FIFO_ERROR                                                        (0x1<<31) // Read packet client rc3 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_WR_3_RC_PKT3_RSP_FIFO_ERROR_SHIFT                                                  31
+#define BMB_REG_INT_STS_CLR_3                                                                                0x540114UL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT0_SIDE_FIFO_ERROR                                                      (0x1<<1) // Read packet client rc0 side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT                                                1
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT0_REQ_FIFO_ERROR                                                       (0x1<<2) // Read packet client rc0 request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT0_REQ_FIFO_ERROR_SHIFT                                                 2
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT0_BLK_FIFO_ERROR                                                       (0x1<<3) // Read packet client rc0 block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT                                                 3
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR                                                  (0x1<<4) // Read packet client rc0 releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR_SHIFT                                            4
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT0_STRT_PTR_FIFO_ERROR                                                  (0x1<<5) // Read packet client rc0 start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT0_STRT_PTR_FIFO_ERROR_SHIFT                                            5
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR                                                (0x1<<6) // Read packet client rc0 second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR_SHIFT                                          6
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT0_RSP_FIFO_ERROR                                                       (0x1<<7) // Read packet client rc0 response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT                                                 7
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT0_DSCR_FIFO_ERROR                                                      (0x1<<8) // Read packet client rc0 descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT                                                8
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT1_SIDE_FIFO_ERROR                                                      (0x1<<9) // Read packet client rc1 side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT1_SIDE_FIFO_ERROR_SHIFT                                                9
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT1_REQ_FIFO_ERROR                                                       (0x1<<10) // Read packet client rc1 request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT1_REQ_FIFO_ERROR_SHIFT                                                 10
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT1_BLK_FIFO_ERROR                                                       (0x1<<11) // Read packet client rc1 block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT1_BLK_FIFO_ERROR_SHIFT                                                 11
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR                                                  (0x1<<12) // Read packet client rc1 releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR_SHIFT                                            12
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT1_STRT_PTR_FIFO_ERROR                                                  (0x1<<13) // Read packet client rc1 start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT1_STRT_PTR_FIFO_ERROR_SHIFT                                            13
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR                                                (0x1<<14) // Read packet client rc1 second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR_SHIFT                                          14
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT1_RSP_FIFO_ERROR                                                       (0x1<<15) // Read packet client rc1 response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT1_RSP_FIFO_ERROR_SHIFT                                                 15
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT1_DSCR_FIFO_ERROR                                                      (0x1<<16) // Read packet client rc1 descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT1_DSCR_FIFO_ERROR_SHIFT                                                16
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT2_SIDE_FIFO_ERROR                                                      (0x1<<17) // Read packet client rc2 side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT2_SIDE_FIFO_ERROR_SHIFT                                                17
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT2_REQ_FIFO_ERROR                                                       (0x1<<18) // Read packet client rc2 request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT2_REQ_FIFO_ERROR_SHIFT                                                 18
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT2_BLK_FIFO_ERROR                                                       (0x1<<19) // Read packet client rc2 block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT2_BLK_FIFO_ERROR_SHIFT                                                 19
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR                                                  (0x1<<20) // Read packet client rc2 releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR_SHIFT                                            20
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT2_STRT_PTR_FIFO_ERROR                                                  (0x1<<21) // Read packet client rc2 start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT2_STRT_PTR_FIFO_ERROR_SHIFT                                            21
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR                                                (0x1<<22) // Read packet client rc2 second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR_SHIFT                                          22
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT2_RSP_FIFO_ERROR                                                       (0x1<<23) // Read packet client rc2 response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT2_RSP_FIFO_ERROR_SHIFT                                                 23
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT2_DSCR_FIFO_ERROR                                                      (0x1<<24) // Read packet client rc2 descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT2_DSCR_FIFO_ERROR_SHIFT                                                24
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT3_SIDE_FIFO_ERROR                                                      (0x1<<25) // Read packet client rc3 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT3_SIDE_FIFO_ERROR_SHIFT                                                25
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT3_REQ_FIFO_ERROR                                                       (0x1<<26) // Read packet client rc3 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT3_REQ_FIFO_ERROR_SHIFT                                                 26
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT3_BLK_FIFO_ERROR                                                       (0x1<<27) // Read packet client rc3 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT3_BLK_FIFO_ERROR_SHIFT                                                 27
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR                                                  (0x1<<28) // Read packet client rc3 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR_SHIFT                                            28
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT3_STRT_PTR_FIFO_ERROR                                                  (0x1<<29) // Read packet client rc3 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT3_STRT_PTR_FIFO_ERROR_SHIFT                                            29
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR                                                (0x1<<30) // Read packet client rc3 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT                                          30
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT3_RSP_FIFO_ERROR                                                       (0x1<<31) // Read packet client rc3 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_CLR_3_RC_PKT3_RSP_FIFO_ERROR_SHIFT                                                 31
+#define BMB_REG_INT_STS_4                                                                                    0x540120UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_4_RC_PKT3_DSCR_FIFO_ERROR                                                          (0x1<<0) // Read packet client rc3 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_4_RC_PKT3_DSCR_FIFO_ERROR_SHIFT                                                    0
+  #define BMB_REG_INT_STS_4_RC_SOP_STRT_FIFO_ERROR                                                           (0x1<<1) // Read SOP client strt pointer FIFO error RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_4_RC_SOP_STRT_FIFO_ERROR_SHIFT                                                     1
+  #define BMB_REG_INT_STS_4_RC_SOP_REQ_FIFO_ERROR                                                            (0x1<<2) // Read SOP client request FIFO error RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_4_RC_SOP_REQ_FIFO_ERROR_SHIFT                                                      2
+  #define BMB_REG_INT_STS_4_RC_SOP_DSCR_FIFO_ERROR                                                           (0x1<<3) // Read SOP client descriptor FIFO error RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_4_RC_SOP_DSCR_FIFO_ERROR_SHIFT                                                     3
+  #define BMB_REG_INT_STS_4_RC_SOP_QUEUE_FIFO_ERROR                                                          (0x1<<4) // Read SOP client queue FIFO error.
+  #define BMB_REG_INT_STS_4_RC_SOP_QUEUE_FIFO_ERROR_SHIFT                                                    4
+  #define BMB_REG_INT_STS_4_LL_ARB_RLS_FIFO_ERROR                                                            (0x1<<7) // Link list arbiter release FIFO error.
+  #define BMB_REG_INT_STS_4_LL_ARB_RLS_FIFO_ERROR_SHIFT                                                      7
+  #define BMB_REG_INT_STS_4_LL_ARB_PREFETCH_FIFO_ERROR                                                       (0x1<<8) // Link list arbiter prefetch FIFO error.
+  #define BMB_REG_INT_STS_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT                                                 8
+  #define BMB_REG_INT_STS_4_RC_PKT0_RLS_FIFO_ERROR                                                           (0x1<<9) // Read packet client rc0 release fifo error
+  #define BMB_REG_INT_STS_4_RC_PKT0_RLS_FIFO_ERROR_SHIFT                                                     9
+  #define BMB_REG_INT_STS_4_RC_PKT1_RLS_FIFO_ERROR                                                           (0x1<<10) // Read packet client rc1 release fifo error
+  #define BMB_REG_INT_STS_4_RC_PKT1_RLS_FIFO_ERROR_SHIFT                                                     10
+  #define BMB_REG_INT_STS_4_RC_PKT2_RLS_FIFO_ERROR                                                           (0x1<<11) // Read packet client rc2 release fifo error
+  #define BMB_REG_INT_STS_4_RC_PKT2_RLS_FIFO_ERROR_SHIFT                                                     11
+  #define BMB_REG_INT_STS_4_RC_PKT3_RLS_FIFO_ERROR                                                           (0x1<<12) // Read packet client rc3 release fifo error
+  #define BMB_REG_INT_STS_4_RC_PKT3_RLS_FIFO_ERROR_SHIFT                                                     12
+  #define BMB_REG_INT_STS_4_RC_PKT4_RLS_FIFO_ERROR                                                           (0x1<<13) // Read packet client rc4 release fifo error
+  #define BMB_REG_INT_STS_4_RC_PKT4_RLS_FIFO_ERROR_SHIFT                                                     13
+  #define BMB_REG_INT_STS_4_RC_PKT5_RLS_FIFO_ERROR                                                           (0x1<<14) // Read packet client rc4 release fifo error
+  #define BMB_REG_INT_STS_4_RC_PKT5_RLS_FIFO_ERROR_SHIFT                                                     14
+  #define BMB_REG_INT_STS_4_RC_PKT6_RLS_FIFO_ERROR                                                           (0x1<<15) // Read packet client rc4 release fifo error
+  #define BMB_REG_INT_STS_4_RC_PKT6_RLS_FIFO_ERROR_SHIFT                                                     15
+  #define BMB_REG_INT_STS_4_RC_PKT7_RLS_FIFO_ERROR                                                           (0x1<<16) // Read packet client rc4 release fifo error
+  #define BMB_REG_INT_STS_4_RC_PKT7_RLS_FIFO_ERROR_SHIFT                                                     16
+  #define BMB_REG_INT_STS_4_RC_PKT8_RLS_FIFO_ERROR                                                           (0x1<<17) // Read packet client rc4 release fifo error
+  #define BMB_REG_INT_STS_4_RC_PKT8_RLS_FIFO_ERROR_SHIFT                                                     17
+  #define BMB_REG_INT_STS_4_RC_PKT9_RLS_FIFO_ERROR                                                           (0x1<<18) // Read packet client rc4 release fifo error
+  #define BMB_REG_INT_STS_4_RC_PKT9_RLS_FIFO_ERROR_SHIFT                                                     18
+  #define BMB_REG_INT_STS_4_RC_PKT4_RLS_ERROR                                                                (0x1<<19) // Read packet client rc3 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_4_RC_PKT4_RLS_ERROR_SHIFT                                                          19
+  #define BMB_REG_INT_STS_4_RC_PKT4_PROTOCOL_ERROR                                                           (0x1<<23) // Read packet client rc3 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_4_RC_PKT4_PROTOCOL_ERROR_SHIFT                                                     23
+  #define BMB_REG_INT_STS_4_RC_PKT4_SIDE_FIFO_ERROR                                                          (0x1<<24) // Read packet client rc3 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_4_RC_PKT4_SIDE_FIFO_ERROR_SHIFT                                                    24
+  #define BMB_REG_INT_STS_4_RC_PKT4_REQ_FIFO_ERROR                                                           (0x1<<25) // Read packet client rc3 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_4_RC_PKT4_REQ_FIFO_ERROR_SHIFT                                                     25
+  #define BMB_REG_INT_STS_4_RC_PKT4_BLK_FIFO_ERROR                                                           (0x1<<26) // Read packet client rc3 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_4_RC_PKT4_BLK_FIFO_ERROR_SHIFT                                                     26
+  #define BMB_REG_INT_STS_4_RC_PKT4_RLS_LEFT_FIFO_ERROR                                                      (0x1<<27) // Read packet client rc3 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_4_RC_PKT4_RLS_LEFT_FIFO_ERROR_SHIFT                                                27
+  #define BMB_REG_INT_STS_4_RC_PKT4_STRT_PTR_FIFO_ERROR                                                      (0x1<<28) // Read packet client rc3 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_4_RC_PKT4_STRT_PTR_FIFO_ERROR_SHIFT                                                28
+  #define BMB_REG_INT_STS_4_RC_PKT4_SECOND_PTR_FIFO_ERROR                                                    (0x1<<29) // Read packet client rc3 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_4_RC_PKT4_SECOND_PTR_FIFO_ERROR_SHIFT                                              29
+  #define BMB_REG_INT_STS_4_RC_PKT4_RSP_FIFO_ERROR                                                           (0x1<<30) // Read packet client rc3 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT                                                     30
+  #define BMB_REG_INT_STS_4_RC_PKT4_DSCR_FIFO_ERROR                                                          (0x1<<31) // Read packet client rc3 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_4_RC_PKT4_DSCR_FIFO_ERROR_SHIFT                                                    31
+#define BMB_REG_INT_MASK_4                                                                                   0x540124UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_MASK_4_RC_PKT3_DSCR_FIFO_ERROR                                                         (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT3_DSCR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_PKT3_DSCR_FIFO_ERROR_SHIFT                                                   0
+  #define BMB_REG_INT_MASK_4_RC_SOP_STRT_FIFO_ERROR                                                          (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_SOP_STRT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_SOP_STRT_FIFO_ERROR_SHIFT                                                    1
+  #define BMB_REG_INT_MASK_4_RC_SOP_REQ_FIFO_ERROR                                                           (0x1<<2) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_SOP_REQ_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_SOP_REQ_FIFO_ERROR_SHIFT                                                     2
+  #define BMB_REG_INT_MASK_4_RC_SOP_DSCR_FIFO_ERROR                                                          (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_SOP_DSCR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_SOP_DSCR_FIFO_ERROR_SHIFT                                                    3
+  #define BMB_REG_INT_MASK_4_RC_SOP_QUEUE_FIFO_ERROR                                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_SOP_QUEUE_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_SOP_QUEUE_FIFO_ERROR_SHIFT                                                   4
+  #define BMB_REG_INT_MASK_4_LL_ARB_RLS_FIFO_ERROR                                                           (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.LL_ARB_RLS_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_LL_ARB_RLS_FIFO_ERROR_SHIFT                                                     7
+  #define BMB_REG_INT_MASK_4_LL_ARB_PREFETCH_FIFO_ERROR                                                      (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.LL_ARB_PREFETCH_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT                                                8
+  #define BMB_REG_INT_MASK_4_RC_PKT0_RLS_FIFO_ERROR                                                          (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT0_RLS_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_PKT0_RLS_FIFO_ERROR_SHIFT                                                    9
+  #define BMB_REG_INT_MASK_4_RC_PKT1_RLS_FIFO_ERROR                                                          (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT1_RLS_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_PKT1_RLS_FIFO_ERROR_SHIFT                                                    10
+  #define BMB_REG_INT_MASK_4_RC_PKT2_RLS_FIFO_ERROR                                                          (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT2_RLS_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_PKT2_RLS_FIFO_ERROR_SHIFT                                                    11
+  #define BMB_REG_INT_MASK_4_RC_PKT3_RLS_FIFO_ERROR                                                          (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT3_RLS_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_PKT3_RLS_FIFO_ERROR_SHIFT                                                    12
+  #define BMB_REG_INT_MASK_4_RC_PKT4_RLS_FIFO_ERROR                                                          (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_RLS_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_PKT4_RLS_FIFO_ERROR_SHIFT                                                    13
+  #define BMB_REG_INT_MASK_4_RC_PKT5_RLS_FIFO_ERROR                                                          (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT5_RLS_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_PKT5_RLS_FIFO_ERROR_SHIFT                                                    14
+  #define BMB_REG_INT_MASK_4_RC_PKT6_RLS_FIFO_ERROR                                                          (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT6_RLS_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_PKT6_RLS_FIFO_ERROR_SHIFT                                                    15
+  #define BMB_REG_INT_MASK_4_RC_PKT7_RLS_FIFO_ERROR                                                          (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT7_RLS_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_PKT7_RLS_FIFO_ERROR_SHIFT                                                    16
+  #define BMB_REG_INT_MASK_4_RC_PKT8_RLS_FIFO_ERROR                                                          (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT8_RLS_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_PKT8_RLS_FIFO_ERROR_SHIFT                                                    17
+  #define BMB_REG_INT_MASK_4_RC_PKT9_RLS_FIFO_ERROR                                                          (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT9_RLS_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_PKT9_RLS_FIFO_ERROR_SHIFT                                                    18
+  #define BMB_REG_INT_MASK_4_RC_PKT4_RLS_ERROR                                                               (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_RLS_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_PKT4_RLS_ERROR_SHIFT                                                         19
+  #define BMB_REG_INT_MASK_4_RC_PKT4_PROTOCOL_ERROR                                                          (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_PROTOCOL_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_PKT4_PROTOCOL_ERROR_SHIFT                                                    23
+  #define BMB_REG_INT_MASK_4_RC_PKT4_SIDE_FIFO_ERROR                                                         (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_SIDE_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_PKT4_SIDE_FIFO_ERROR_SHIFT                                                   24
+  #define BMB_REG_INT_MASK_4_RC_PKT4_REQ_FIFO_ERROR                                                          (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_REQ_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_PKT4_REQ_FIFO_ERROR_SHIFT                                                    25
+  #define BMB_REG_INT_MASK_4_RC_PKT4_BLK_FIFO_ERROR                                                          (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_BLK_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_PKT4_BLK_FIFO_ERROR_SHIFT                                                    26
+  #define BMB_REG_INT_MASK_4_RC_PKT4_RLS_LEFT_FIFO_ERROR                                                     (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_RLS_LEFT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_PKT4_RLS_LEFT_FIFO_ERROR_SHIFT                                               27
+  #define BMB_REG_INT_MASK_4_RC_PKT4_STRT_PTR_FIFO_ERROR                                                     (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_STRT_PTR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_PKT4_STRT_PTR_FIFO_ERROR_SHIFT                                               28
+  #define BMB_REG_INT_MASK_4_RC_PKT4_SECOND_PTR_FIFO_ERROR                                                   (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_SECOND_PTR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_PKT4_SECOND_PTR_FIFO_ERROR_SHIFT                                             29
+  #define BMB_REG_INT_MASK_4_RC_PKT4_RSP_FIFO_ERROR                                                          (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_RSP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT                                                    30
+  #define BMB_REG_INT_MASK_4_RC_PKT4_DSCR_FIFO_ERROR                                                         (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_DSCR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_4_RC_PKT4_DSCR_FIFO_ERROR_SHIFT                                                   31
+#define BMB_REG_INT_STS_WR_4                                                                                 0x540128UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_WR_4_RC_PKT3_DSCR_FIFO_ERROR                                                       (0x1<<0) // Read packet client rc3 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_WR_4_RC_PKT3_DSCR_FIFO_ERROR_SHIFT                                                 0
+  #define BMB_REG_INT_STS_WR_4_RC_SOP_STRT_FIFO_ERROR                                                        (0x1<<1) // Read SOP client strt pointer FIFO error RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_4_RC_SOP_STRT_FIFO_ERROR_SHIFT                                                  1
+  #define BMB_REG_INT_STS_WR_4_RC_SOP_REQ_FIFO_ERROR                                                         (0x1<<2) // Read SOP client request FIFO error RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_4_RC_SOP_REQ_FIFO_ERROR_SHIFT                                                   2
+  #define BMB_REG_INT_STS_WR_4_RC_SOP_DSCR_FIFO_ERROR                                                        (0x1<<3) // Read SOP client descriptor FIFO error RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_4_RC_SOP_DSCR_FIFO_ERROR_SHIFT                                                  3
+  #define BMB_REG_INT_STS_WR_4_RC_SOP_QUEUE_FIFO_ERROR                                                       (0x1<<4) // Read SOP client queue FIFO error.
+  #define BMB_REG_INT_STS_WR_4_RC_SOP_QUEUE_FIFO_ERROR_SHIFT                                                 4
+  #define BMB_REG_INT_STS_WR_4_LL_ARB_RLS_FIFO_ERROR                                                         (0x1<<7) // Link list arbiter release FIFO error.
+  #define BMB_REG_INT_STS_WR_4_LL_ARB_RLS_FIFO_ERROR_SHIFT                                                   7
+  #define BMB_REG_INT_STS_WR_4_LL_ARB_PREFETCH_FIFO_ERROR                                                    (0x1<<8) // Link list arbiter prefetch FIFO error.
+  #define BMB_REG_INT_STS_WR_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT                                              8
+  #define BMB_REG_INT_STS_WR_4_RC_PKT0_RLS_FIFO_ERROR                                                        (0x1<<9) // Read packet client rc0 release fifo error
+  #define BMB_REG_INT_STS_WR_4_RC_PKT0_RLS_FIFO_ERROR_SHIFT                                                  9
+  #define BMB_REG_INT_STS_WR_4_RC_PKT1_RLS_FIFO_ERROR                                                        (0x1<<10) // Read packet client rc1 release fifo error
+  #define BMB_REG_INT_STS_WR_4_RC_PKT1_RLS_FIFO_ERROR_SHIFT                                                  10
+  #define BMB_REG_INT_STS_WR_4_RC_PKT2_RLS_FIFO_ERROR                                                        (0x1<<11) // Read packet client rc2 release fifo error
+  #define BMB_REG_INT_STS_WR_4_RC_PKT2_RLS_FIFO_ERROR_SHIFT                                                  11
+  #define BMB_REG_INT_STS_WR_4_RC_PKT3_RLS_FIFO_ERROR                                                        (0x1<<12) // Read packet client rc3 release fifo error
+  #define BMB_REG_INT_STS_WR_4_RC_PKT3_RLS_FIFO_ERROR_SHIFT                                                  12
+  #define BMB_REG_INT_STS_WR_4_RC_PKT4_RLS_FIFO_ERROR                                                        (0x1<<13) // Read packet client rc4 release fifo error
+  #define BMB_REG_INT_STS_WR_4_RC_PKT4_RLS_FIFO_ERROR_SHIFT                                                  13
+  #define BMB_REG_INT_STS_WR_4_RC_PKT5_RLS_FIFO_ERROR                                                        (0x1<<14) // Read packet client rc4 release fifo error
+  #define BMB_REG_INT_STS_WR_4_RC_PKT5_RLS_FIFO_ERROR_SHIFT                                                  14
+  #define BMB_REG_INT_STS_WR_4_RC_PKT6_RLS_FIFO_ERROR                                                        (0x1<<15) // Read packet client rc4 release fifo error
+  #define BMB_REG_INT_STS_WR_4_RC_PKT6_RLS_FIFO_ERROR_SHIFT                                                  15
+  #define BMB_REG_INT_STS_WR_4_RC_PKT7_RLS_FIFO_ERROR                                                        (0x1<<16) // Read packet client rc4 release fifo error
+  #define BMB_REG_INT_STS_WR_4_RC_PKT7_RLS_FIFO_ERROR_SHIFT                                                  16
+  #define BMB_REG_INT_STS_WR_4_RC_PKT8_RLS_FIFO_ERROR                                                        (0x1<<17) // Read packet client rc4 release fifo error
+  #define BMB_REG_INT_STS_WR_4_RC_PKT8_RLS_FIFO_ERROR_SHIFT                                                  17
+  #define BMB_REG_INT_STS_WR_4_RC_PKT9_RLS_FIFO_ERROR                                                        (0x1<<18) // Read packet client rc4 release fifo error
+  #define BMB_REG_INT_STS_WR_4_RC_PKT9_RLS_FIFO_ERROR_SHIFT                                                  18
+  #define BMB_REG_INT_STS_WR_4_RC_PKT4_RLS_ERROR                                                             (0x1<<19) // Read packet client rc3 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_WR_4_RC_PKT4_RLS_ERROR_SHIFT                                                       19
+  #define BMB_REG_INT_STS_WR_4_RC_PKT4_PROTOCOL_ERROR                                                        (0x1<<23) // Read packet client rc3 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_WR_4_RC_PKT4_PROTOCOL_ERROR_SHIFT                                                  23
+  #define BMB_REG_INT_STS_WR_4_RC_PKT4_SIDE_FIFO_ERROR                                                       (0x1<<24) // Read packet client rc3 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_WR_4_RC_PKT4_SIDE_FIFO_ERROR_SHIFT                                                 24
+  #define BMB_REG_INT_STS_WR_4_RC_PKT4_REQ_FIFO_ERROR                                                        (0x1<<25) // Read packet client rc3 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_WR_4_RC_PKT4_REQ_FIFO_ERROR_SHIFT                                                  25
+  #define BMB_REG_INT_STS_WR_4_RC_PKT4_BLK_FIFO_ERROR                                                        (0x1<<26) // Read packet client rc3 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_WR_4_RC_PKT4_BLK_FIFO_ERROR_SHIFT                                                  26
+  #define BMB_REG_INT_STS_WR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR                                                   (0x1<<27) // Read packet client rc3 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_WR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR_SHIFT                                             27
+  #define BMB_REG_INT_STS_WR_4_RC_PKT4_STRT_PTR_FIFO_ERROR                                                   (0x1<<28) // Read packet client rc3 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_WR_4_RC_PKT4_STRT_PTR_FIFO_ERROR_SHIFT                                             28
+  #define BMB_REG_INT_STS_WR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR                                                 (0x1<<29) // Read packet client rc3 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_WR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR_SHIFT                                           29
+  #define BMB_REG_INT_STS_WR_4_RC_PKT4_RSP_FIFO_ERROR                                                        (0x1<<30) // Read packet client rc3 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_WR_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT                                                  30
+  #define BMB_REG_INT_STS_WR_4_RC_PKT4_DSCR_FIFO_ERROR                                                       (0x1<<31) // Read packet client rc3 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_WR_4_RC_PKT4_DSCR_FIFO_ERROR_SHIFT                                                 31
+#define BMB_REG_INT_STS_CLR_4                                                                                0x54012cUL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT3_DSCR_FIFO_ERROR                                                      (0x1<<0) // Read packet client rc3 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT3_DSCR_FIFO_ERROR_SHIFT                                                0
+  #define BMB_REG_INT_STS_CLR_4_RC_SOP_STRT_FIFO_ERROR                                                       (0x1<<1) // Read SOP client strt pointer FIFO error RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_4_RC_SOP_STRT_FIFO_ERROR_SHIFT                                                 1
+  #define BMB_REG_INT_STS_CLR_4_RC_SOP_REQ_FIFO_ERROR                                                        (0x1<<2) // Read SOP client request FIFO error RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_4_RC_SOP_REQ_FIFO_ERROR_SHIFT                                                  2
+  #define BMB_REG_INT_STS_CLR_4_RC_SOP_DSCR_FIFO_ERROR                                                       (0x1<<3) // Read SOP client descriptor FIFO error RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_4_RC_SOP_DSCR_FIFO_ERROR_SHIFT                                                 3
+  #define BMB_REG_INT_STS_CLR_4_RC_SOP_QUEUE_FIFO_ERROR                                                      (0x1<<4) // Read SOP client queue FIFO error.
+  #define BMB_REG_INT_STS_CLR_4_RC_SOP_QUEUE_FIFO_ERROR_SHIFT                                                4
+  #define BMB_REG_INT_STS_CLR_4_LL_ARB_RLS_FIFO_ERROR                                                        (0x1<<7) // Link list arbiter release FIFO error.
+  #define BMB_REG_INT_STS_CLR_4_LL_ARB_RLS_FIFO_ERROR_SHIFT                                                  7
+  #define BMB_REG_INT_STS_CLR_4_LL_ARB_PREFETCH_FIFO_ERROR                                                   (0x1<<8) // Link list arbiter prefetch FIFO error.
+  #define BMB_REG_INT_STS_CLR_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT                                             8
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT0_RLS_FIFO_ERROR                                                       (0x1<<9) // Read packet client rc0 release fifo error
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT0_RLS_FIFO_ERROR_SHIFT                                                 9
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT1_RLS_FIFO_ERROR                                                       (0x1<<10) // Read packet client rc1 release fifo error
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT1_RLS_FIFO_ERROR_SHIFT                                                 10
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT2_RLS_FIFO_ERROR                                                       (0x1<<11) // Read packet client rc2 release fifo error
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT2_RLS_FIFO_ERROR_SHIFT                                                 11
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT3_RLS_FIFO_ERROR                                                       (0x1<<12) // Read packet client rc3 release fifo error
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT3_RLS_FIFO_ERROR_SHIFT                                                 12
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT4_RLS_FIFO_ERROR                                                       (0x1<<13) // Read packet client rc4 release fifo error
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT4_RLS_FIFO_ERROR_SHIFT                                                 13
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT5_RLS_FIFO_ERROR                                                       (0x1<<14) // Read packet client rc4 release fifo error
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT5_RLS_FIFO_ERROR_SHIFT                                                 14
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT6_RLS_FIFO_ERROR                                                       (0x1<<15) // Read packet client rc4 release fifo error
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT6_RLS_FIFO_ERROR_SHIFT                                                 15
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT7_RLS_FIFO_ERROR                                                       (0x1<<16) // Read packet client rc4 release fifo error
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT7_RLS_FIFO_ERROR_SHIFT                                                 16
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT8_RLS_FIFO_ERROR                                                       (0x1<<17) // Read packet client rc4 release fifo error
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT8_RLS_FIFO_ERROR_SHIFT                                                 17
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT9_RLS_FIFO_ERROR                                                       (0x1<<18) // Read packet client rc4 release fifo error
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT9_RLS_FIFO_ERROR_SHIFT                                                 18
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT4_RLS_ERROR                                                            (0x1<<19) // Read packet client rc3 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT4_RLS_ERROR_SHIFT                                                      19
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT4_PROTOCOL_ERROR                                                       (0x1<<23) // Read packet client rc3 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT4_PROTOCOL_ERROR_SHIFT                                                 23
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT4_SIDE_FIFO_ERROR                                                      (0x1<<24) // Read packet client rc3 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT4_SIDE_FIFO_ERROR_SHIFT                                                24
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT4_REQ_FIFO_ERROR                                                       (0x1<<25) // Read packet client rc3 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT4_REQ_FIFO_ERROR_SHIFT                                                 25
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT4_BLK_FIFO_ERROR                                                       (0x1<<26) // Read packet client rc3 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT4_BLK_FIFO_ERROR_SHIFT                                                 26
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR                                                  (0x1<<27) // Read packet client rc3 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR_SHIFT                                            27
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT4_STRT_PTR_FIFO_ERROR                                                  (0x1<<28) // Read packet client rc3 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT4_STRT_PTR_FIFO_ERROR_SHIFT                                            28
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR                                                (0x1<<29) // Read packet client rc3 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR_SHIFT                                          29
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT4_RSP_FIFO_ERROR                                                       (0x1<<30) // Read packet client rc3 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT                                                 30
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT4_DSCR_FIFO_ERROR                                                      (0x1<<31) // Read packet client rc3 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BMB_REG_INT_STS_CLR_4_RC_PKT4_DSCR_FIFO_ERROR_SHIFT                                                31
+#define BMB_REG_INT_STS_5                                                                                    0x540138UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_5_RC_PKT5_RLS_ERROR                                                                (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
+  #define BMB_REG_INT_STS_5_RC_PKT5_RLS_ERROR_SHIFT                                                          0
+  #define BMB_REG_INT_STS_5_RC_PKT5_PROTOCOL_ERROR                                                           (0x1<<2) // Read packet client5 error when packet doesn't have SOP or EOP on read response
+  #define BMB_REG_INT_STS_5_RC_PKT5_PROTOCOL_ERROR_SHIFT                                                     2
+  #define BMB_REG_INT_STS_5_RC_PKT5_SIDE_FIFO_ERROR                                                          (0x1<<3) // Read packet client5 side info FIFO error
+  #define BMB_REG_INT_STS_5_RC_PKT5_SIDE_FIFO_ERROR_SHIFT                                                    3
+  #define BMB_REG_INT_STS_5_RC_PKT5_REQ_FIFO_ERROR                                                           (0x1<<4) // Read packet client5 request FIFO error
+  #define BMB_REG_INT_STS_5_RC_PKT5_REQ_FIFO_ERROR_SHIFT                                                     4
+  #define BMB_REG_INT_STS_5_RC_PKT5_BLK_FIFO_ERROR                                                           (0x1<<5) // Read packet client5 block FIFO error
+  #define BMB_REG_INT_STS_5_RC_PKT5_BLK_FIFO_ERROR_SHIFT                                                     5
+  #define BMB_REG_INT_STS_5_RC_PKT5_RLS_LEFT_FIFO_ERROR                                                      (0x1<<6) // Read packet client5 releases left FIFO error
+  #define BMB_REG_INT_STS_5_RC_PKT5_RLS_LEFT_FIFO_ERROR_SHIFT                                                6
+  #define BMB_REG_INT_STS_5_RC_PKT5_STRT_PTR_FIFO_ERROR                                                      (0x1<<7) // Read packet client5 start pointer FIFO error
+  #define BMB_REG_INT_STS_5_RC_PKT5_STRT_PTR_FIFO_ERROR_SHIFT                                                7
+  #define BMB_REG_INT_STS_5_RC_PKT5_SECOND_PTR_FIFO_ERROR                                                    (0x1<<8) // Read packet client5 second pointer FIFO
+  #define BMB_REG_INT_STS_5_RC_PKT5_SECOND_PTR_FIFO_ERROR_SHIFT                                              8
+  #define BMB_REG_INT_STS_5_RC_PKT5_RSP_FIFO_ERROR                                                           (0x1<<9) // Read packet client5 response FIFO error
+  #define BMB_REG_INT_STS_5_RC_PKT5_RSP_FIFO_ERROR_SHIFT                                                     9
+  #define BMB_REG_INT_STS_5_RC_PKT5_DSCR_FIFO_ERROR                                                          (0x1<<10) // Read packet client5 descriptor FIFO error
+  #define BMB_REG_INT_STS_5_RC_PKT5_DSCR_FIFO_ERROR_SHIFT                                                    10
+  #define BMB_REG_INT_STS_5_RC_PKT6_RLS_ERROR                                                                (0x1<<11) // Read packet client6 error when number of requested packet copies is bigger than real number of packet copies
+  #define BMB_REG_INT_STS_5_RC_PKT6_RLS_ERROR_SHIFT                                                          11
+  #define BMB_REG_INT_STS_5_RC_PKT6_PROTOCOL_ERROR                                                           (0x1<<13) // Read packet client6 error when packet doesn't have SOP or EOP on read response
+  #define BMB_REG_INT_STS_5_RC_PKT6_PROTOCOL_ERROR_SHIFT                                                     13
+  #define BMB_REG_INT_STS_5_RC_PKT6_SIDE_FIFO_ERROR                                                          (0x1<<14) // Read packet client6 side info FIFO error
+  #define BMB_REG_INT_STS_5_RC_PKT6_SIDE_FIFO_ERROR_SHIFT                                                    14
+  #define BMB_REG_INT_STS_5_RC_PKT6_REQ_FIFO_ERROR                                                           (0x1<<15) // Read packet client6 request FIFO error
+  #define BMB_REG_INT_STS_5_RC_PKT6_REQ_FIFO_ERROR_SHIFT                                                     15
+  #define BMB_REG_INT_STS_5_RC_PKT6_BLK_FIFO_ERROR                                                           (0x1<<16) // Read packet client6 block FIFO error
+  #define BMB_REG_INT_STS_5_RC_PKT6_BLK_FIFO_ERROR_SHIFT                                                     16
+  #define BMB_REG_INT_STS_5_RC_PKT6_RLS_LEFT_FIFO_ERROR                                                      (0x1<<17) // Read packet client6 releases left FIFO error
+  #define BMB_REG_INT_STS_5_RC_PKT6_RLS_LEFT_FIFO_ERROR_SHIFT                                                17
+  #define BMB_REG_INT_STS_5_RC_PKT6_STRT_PTR_FIFO_ERROR                                                      (0x1<<18) // Read packet client6 start pointer FIFO error
+  #define BMB_REG_INT_STS_5_RC_PKT6_STRT_PTR_FIFO_ERROR_SHIFT                                                18
+  #define BMB_REG_INT_STS_5_RC_PKT6_SECOND_PTR_FIFO_ERROR                                                    (0x1<<19) // Read packet client6 second pointer FIFO
+  #define BMB_REG_INT_STS_5_RC_PKT6_SECOND_PTR_FIFO_ERROR_SHIFT                                              19
+  #define BMB_REG_INT_STS_5_RC_PKT6_RSP_FIFO_ERROR                                                           (0x1<<20) // Read packet client6 response FIFO error
+  #define BMB_REG_INT_STS_5_RC_PKT6_RSP_FIFO_ERROR_SHIFT                                                     20
+  #define BMB_REG_INT_STS_5_RC_PKT6_DSCR_FIFO_ERROR                                                          (0x1<<21) // Read packet client6 descriptor FIFO error
+  #define BMB_REG_INT_STS_5_RC_PKT6_DSCR_FIFO_ERROR_SHIFT                                                    21
+  #define BMB_REG_INT_STS_5_RC_PKT7_RLS_ERROR                                                                (0x1<<22) // Read packet client7 error when number of requested packet copies is bigger than real number of packet copies
+  #define BMB_REG_INT_STS_5_RC_PKT7_RLS_ERROR_SHIFT                                                          22
+  #define BMB_REG_INT_STS_5_RC_PKT7_PROTOCOL_ERROR                                                           (0x1<<24) // Read packet client7 error when packet doesn't have SOP or EOP on read response
+  #define BMB_REG_INT_STS_5_RC_PKT7_PROTOCOL_ERROR_SHIFT                                                     24
+  #define BMB_REG_INT_STS_5_RC_PKT7_SIDE_FIFO_ERROR                                                          (0x1<<25) // Read packet client7 side info FIFO error
+  #define BMB_REG_INT_STS_5_RC_PKT7_SIDE_FIFO_ERROR_SHIFT                                                    25
+  #define BMB_REG_INT_STS_5_RC_PKT7_REQ_FIFO_ERROR                                                           (0x1<<26) // Read packet client7 request FIFO error
+  #define BMB_REG_INT_STS_5_RC_PKT7_REQ_FIFO_ERROR_SHIFT                                                     26
+  #define BMB_REG_INT_STS_5_RC_PKT7_BLK_FIFO_ERROR                                                           (0x1<<27) // Read packet client7 block FIFO error
+  #define BMB_REG_INT_STS_5_RC_PKT7_BLK_FIFO_ERROR_SHIFT                                                     27
+  #define BMB_REG_INT_STS_5_RC_PKT7_RLS_LEFT_FIFO_ERROR                                                      (0x1<<28) // Read packet client7 releases left FIFO error
+  #define BMB_REG_INT_STS_5_RC_PKT7_RLS_LEFT_FIFO_ERROR_SHIFT                                                28
+  #define BMB_REG_INT_STS_5_RC_PKT7_STRT_PTR_FIFO_ERROR                                                      (0x1<<29) // Read packet client7 start pointer FIFO error
+  #define BMB_REG_INT_STS_5_RC_PKT7_STRT_PTR_FIFO_ERROR_SHIFT                                                29
+  #define BMB_REG_INT_STS_5_RC_PKT7_SECOND_PTR_FIFO_ERROR                                                    (0x1<<30) // Read packet client7 second pointer FIFO
+  #define BMB_REG_INT_STS_5_RC_PKT7_SECOND_PTR_FIFO_ERROR_SHIFT                                              30
+  #define BMB_REG_INT_STS_5_RC_PKT7_RSP_FIFO_ERROR                                                           (0x1<<31) // Read packet client7 response FIFO error
+  #define BMB_REG_INT_STS_5_RC_PKT7_RSP_FIFO_ERROR_SHIFT                                                     31
+#define BMB_REG_INT_MASK_5                                                                                   0x54013cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_MASK_5_RC_PKT5_RLS_ERROR                                                               (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_RLS_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT5_RLS_ERROR_SHIFT                                                         0
+  #define BMB_REG_INT_MASK_5_RC_PKT5_PROTOCOL_ERROR                                                          (0x1<<2) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_PROTOCOL_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT5_PROTOCOL_ERROR_SHIFT                                                    2
+  #define BMB_REG_INT_MASK_5_RC_PKT5_SIDE_FIFO_ERROR                                                         (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_SIDE_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT5_SIDE_FIFO_ERROR_SHIFT                                                   3
+  #define BMB_REG_INT_MASK_5_RC_PKT5_REQ_FIFO_ERROR                                                          (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_REQ_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT5_REQ_FIFO_ERROR_SHIFT                                                    4
+  #define BMB_REG_INT_MASK_5_RC_PKT5_BLK_FIFO_ERROR                                                          (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_BLK_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT5_BLK_FIFO_ERROR_SHIFT                                                    5
+  #define BMB_REG_INT_MASK_5_RC_PKT5_RLS_LEFT_FIFO_ERROR                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_RLS_LEFT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT5_RLS_LEFT_FIFO_ERROR_SHIFT                                               6
+  #define BMB_REG_INT_MASK_5_RC_PKT5_STRT_PTR_FIFO_ERROR                                                     (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_STRT_PTR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT5_STRT_PTR_FIFO_ERROR_SHIFT                                               7
+  #define BMB_REG_INT_MASK_5_RC_PKT5_SECOND_PTR_FIFO_ERROR                                                   (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_SECOND_PTR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT5_SECOND_PTR_FIFO_ERROR_SHIFT                                             8
+  #define BMB_REG_INT_MASK_5_RC_PKT5_RSP_FIFO_ERROR                                                          (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_RSP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT5_RSP_FIFO_ERROR_SHIFT                                                    9
+  #define BMB_REG_INT_MASK_5_RC_PKT5_DSCR_FIFO_ERROR                                                         (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_DSCR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT5_DSCR_FIFO_ERROR_SHIFT                                                   10
+  #define BMB_REG_INT_MASK_5_RC_PKT6_RLS_ERROR                                                               (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_RLS_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT6_RLS_ERROR_SHIFT                                                         11
+  #define BMB_REG_INT_MASK_5_RC_PKT6_PROTOCOL_ERROR                                                          (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_PROTOCOL_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT6_PROTOCOL_ERROR_SHIFT                                                    13
+  #define BMB_REG_INT_MASK_5_RC_PKT6_SIDE_FIFO_ERROR                                                         (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_SIDE_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT6_SIDE_FIFO_ERROR_SHIFT                                                   14
+  #define BMB_REG_INT_MASK_5_RC_PKT6_REQ_FIFO_ERROR                                                          (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_REQ_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT6_REQ_FIFO_ERROR_SHIFT                                                    15
+  #define BMB_REG_INT_MASK_5_RC_PKT6_BLK_FIFO_ERROR                                                          (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_BLK_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT6_BLK_FIFO_ERROR_SHIFT                                                    16
+  #define BMB_REG_INT_MASK_5_RC_PKT6_RLS_LEFT_FIFO_ERROR                                                     (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_RLS_LEFT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT6_RLS_LEFT_FIFO_ERROR_SHIFT                                               17
+  #define BMB_REG_INT_MASK_5_RC_PKT6_STRT_PTR_FIFO_ERROR                                                     (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_STRT_PTR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT6_STRT_PTR_FIFO_ERROR_SHIFT                                               18
+  #define BMB_REG_INT_MASK_5_RC_PKT6_SECOND_PTR_FIFO_ERROR                                                   (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_SECOND_PTR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT6_SECOND_PTR_FIFO_ERROR_SHIFT                                             19
+  #define BMB_REG_INT_MASK_5_RC_PKT6_RSP_FIFO_ERROR                                                          (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_RSP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT6_RSP_FIFO_ERROR_SHIFT                                                    20
+  #define BMB_REG_INT_MASK_5_RC_PKT6_DSCR_FIFO_ERROR                                                         (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_DSCR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT6_DSCR_FIFO_ERROR_SHIFT                                                   21
+  #define BMB_REG_INT_MASK_5_RC_PKT7_RLS_ERROR                                                               (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_RLS_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT7_RLS_ERROR_SHIFT                                                         22
+  #define BMB_REG_INT_MASK_5_RC_PKT7_PROTOCOL_ERROR                                                          (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_PROTOCOL_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT7_PROTOCOL_ERROR_SHIFT                                                    24
+  #define BMB_REG_INT_MASK_5_RC_PKT7_SIDE_FIFO_ERROR                                                         (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_SIDE_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT7_SIDE_FIFO_ERROR_SHIFT                                                   25
+  #define BMB_REG_INT_MASK_5_RC_PKT7_REQ_FIFO_ERROR                                                          (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_REQ_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT7_REQ_FIFO_ERROR_SHIFT                                                    26
+  #define BMB_REG_INT_MASK_5_RC_PKT7_BLK_FIFO_ERROR                                                          (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_BLK_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT7_BLK_FIFO_ERROR_SHIFT                                                    27
+  #define BMB_REG_INT_MASK_5_RC_PKT7_RLS_LEFT_FIFO_ERROR                                                     (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_RLS_LEFT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT7_RLS_LEFT_FIFO_ERROR_SHIFT                                               28
+  #define BMB_REG_INT_MASK_5_RC_PKT7_STRT_PTR_FIFO_ERROR                                                     (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_STRT_PTR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT7_STRT_PTR_FIFO_ERROR_SHIFT                                               29
+  #define BMB_REG_INT_MASK_5_RC_PKT7_SECOND_PTR_FIFO_ERROR                                                   (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_SECOND_PTR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT7_SECOND_PTR_FIFO_ERROR_SHIFT                                             30
+  #define BMB_REG_INT_MASK_5_RC_PKT7_RSP_FIFO_ERROR                                                          (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_RSP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_5_RC_PKT7_RSP_FIFO_ERROR_SHIFT                                                    31
+#define BMB_REG_INT_STS_WR_5                                                                                 0x540140UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_WR_5_RC_PKT5_RLS_ERROR                                                             (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
+  #define BMB_REG_INT_STS_WR_5_RC_PKT5_RLS_ERROR_SHIFT                                                       0
+  #define BMB_REG_INT_STS_WR_5_RC_PKT5_PROTOCOL_ERROR                                                        (0x1<<2) // Read packet client5 error when packet doesn't have SOP or EOP on read response
+  #define BMB_REG_INT_STS_WR_5_RC_PKT5_PROTOCOL_ERROR_SHIFT                                                  2
+  #define BMB_REG_INT_STS_WR_5_RC_PKT5_SIDE_FIFO_ERROR                                                       (0x1<<3) // Read packet client5 side info FIFO error
+  #define BMB_REG_INT_STS_WR_5_RC_PKT5_SIDE_FIFO_ERROR_SHIFT                                                 3
+  #define BMB_REG_INT_STS_WR_5_RC_PKT5_REQ_FIFO_ERROR                                                        (0x1<<4) // Read packet client5 request FIFO error
+  #define BMB_REG_INT_STS_WR_5_RC_PKT5_REQ_FIFO_ERROR_SHIFT                                                  4
+  #define BMB_REG_INT_STS_WR_5_RC_PKT5_BLK_FIFO_ERROR                                                        (0x1<<5) // Read packet client5 block FIFO error
+  #define BMB_REG_INT_STS_WR_5_RC_PKT5_BLK_FIFO_ERROR_SHIFT                                                  5
+  #define BMB_REG_INT_STS_WR_5_RC_PKT5_RLS_LEFT_FIFO_ERROR                                                   (0x1<<6) // Read packet client5 releases left FIFO error
+  #define BMB_REG_INT_STS_WR_5_RC_PKT5_RLS_LEFT_FIFO_ERROR_SHIFT                                             6
+  #define BMB_REG_INT_STS_WR_5_RC_PKT5_STRT_PTR_FIFO_ERROR                                                   (0x1<<7) // Read packet client5 start pointer FIFO error
+  #define BMB_REG_INT_STS_WR_5_RC_PKT5_STRT_PTR_FIFO_ERROR_SHIFT                                             7
+  #define BMB_REG_INT_STS_WR_5_RC_PKT5_SECOND_PTR_FIFO_ERROR                                                 (0x1<<8) // Read packet client5 second pointer FIFO
+  #define BMB_REG_INT_STS_WR_5_RC_PKT5_SECOND_PTR_FIFO_ERROR_SHIFT                                           8
+  #define BMB_REG_INT_STS_WR_5_RC_PKT5_RSP_FIFO_ERROR                                                        (0x1<<9) // Read packet client5 response FIFO error
+  #define BMB_REG_INT_STS_WR_5_RC_PKT5_RSP_FIFO_ERROR_SHIFT                                                  9
+  #define BMB_REG_INT_STS_WR_5_RC_PKT5_DSCR_FIFO_ERROR                                                       (0x1<<10) // Read packet client5 descriptor FIFO error
+  #define BMB_REG_INT_STS_WR_5_RC_PKT5_DSCR_FIFO_ERROR_SHIFT                                                 10
+  #define BMB_REG_INT_STS_WR_5_RC_PKT6_RLS_ERROR                                                             (0x1<<11) // Read packet client6 error when number of requested packet copies is bigger than real number of packet copies
+  #define BMB_REG_INT_STS_WR_5_RC_PKT6_RLS_ERROR_SHIFT                                                       11
+  #define BMB_REG_INT_STS_WR_5_RC_PKT6_PROTOCOL_ERROR                                                        (0x1<<13) // Read packet client6 error when packet doesn't have SOP or EOP on read response
+  #define BMB_REG_INT_STS_WR_5_RC_PKT6_PROTOCOL_ERROR_SHIFT                                                  13
+  #define BMB_REG_INT_STS_WR_5_RC_PKT6_SIDE_FIFO_ERROR                                                       (0x1<<14) // Read packet client6 side info FIFO error
+  #define BMB_REG_INT_STS_WR_5_RC_PKT6_SIDE_FIFO_ERROR_SHIFT                                                 14
+  #define BMB_REG_INT_STS_WR_5_RC_PKT6_REQ_FIFO_ERROR                                                        (0x1<<15) // Read packet client6 request FIFO error
+  #define BMB_REG_INT_STS_WR_5_RC_PKT6_REQ_FIFO_ERROR_SHIFT                                                  15
+  #define BMB_REG_INT_STS_WR_5_RC_PKT6_BLK_FIFO_ERROR                                                        (0x1<<16) // Read packet client6 block FIFO error
+  #define BMB_REG_INT_STS_WR_5_RC_PKT6_BLK_FIFO_ERROR_SHIFT                                                  16
+  #define BMB_REG_INT_STS_WR_5_RC_PKT6_RLS_LEFT_FIFO_ERROR                                                   (0x1<<17) // Read packet client6 releases left FIFO error
+  #define BMB_REG_INT_STS_WR_5_RC_PKT6_RLS_LEFT_FIFO_ERROR_SHIFT                                             17
+  #define BMB_REG_INT_STS_WR_5_RC_PKT6_STRT_PTR_FIFO_ERROR                                                   (0x1<<18) // Read packet client6 start pointer FIFO error
+  #define BMB_REG_INT_STS_WR_5_RC_PKT6_STRT_PTR_FIFO_ERROR_SHIFT                                             18
+  #define BMB_REG_INT_STS_WR_5_RC_PKT6_SECOND_PTR_FIFO_ERROR                                                 (0x1<<19) // Read packet client6 second pointer FIFO
+  #define BMB_REG_INT_STS_WR_5_RC_PKT6_SECOND_PTR_FIFO_ERROR_SHIFT                                           19
+  #define BMB_REG_INT_STS_WR_5_RC_PKT6_RSP_FIFO_ERROR                                                        (0x1<<20) // Read packet client6 response FIFO error
+  #define BMB_REG_INT_STS_WR_5_RC_PKT6_RSP_FIFO_ERROR_SHIFT                                                  20
+  #define BMB_REG_INT_STS_WR_5_RC_PKT6_DSCR_FIFO_ERROR                                                       (0x1<<21) // Read packet client6 descriptor FIFO error
+  #define BMB_REG_INT_STS_WR_5_RC_PKT6_DSCR_FIFO_ERROR_SHIFT                                                 21
+  #define BMB_REG_INT_STS_WR_5_RC_PKT7_RLS_ERROR                                                             (0x1<<22) // Read packet client7 error when number of requested packet copies is bigger than real number of packet copies
+  #define BMB_REG_INT_STS_WR_5_RC_PKT7_RLS_ERROR_SHIFT                                                       22
+  #define BMB_REG_INT_STS_WR_5_RC_PKT7_PROTOCOL_ERROR                                                        (0x1<<24) // Read packet client7 error when packet doesn't have SOP or EOP on read response
+  #define BMB_REG_INT_STS_WR_5_RC_PKT7_PROTOCOL_ERROR_SHIFT                                                  24
+  #define BMB_REG_INT_STS_WR_5_RC_PKT7_SIDE_FIFO_ERROR                                                       (0x1<<25) // Read packet client7 side info FIFO error
+  #define BMB_REG_INT_STS_WR_5_RC_PKT7_SIDE_FIFO_ERROR_SHIFT                                                 25
+  #define BMB_REG_INT_STS_WR_5_RC_PKT7_REQ_FIFO_ERROR                                                        (0x1<<26) // Read packet client7 request FIFO error
+  #define BMB_REG_INT_STS_WR_5_RC_PKT7_REQ_FIFO_ERROR_SHIFT                                                  26
+  #define BMB_REG_INT_STS_WR_5_RC_PKT7_BLK_FIFO_ERROR                                                        (0x1<<27) // Read packet client7 block FIFO error
+  #define BMB_REG_INT_STS_WR_5_RC_PKT7_BLK_FIFO_ERROR_SHIFT                                                  27
+  #define BMB_REG_INT_STS_WR_5_RC_PKT7_RLS_LEFT_FIFO_ERROR                                                   (0x1<<28) // Read packet client7 releases left FIFO error
+  #define BMB_REG_INT_STS_WR_5_RC_PKT7_RLS_LEFT_FIFO_ERROR_SHIFT                                             28
+  #define BMB_REG_INT_STS_WR_5_RC_PKT7_STRT_PTR_FIFO_ERROR                                                   (0x1<<29) // Read packet client7 start pointer FIFO error
+  #define BMB_REG_INT_STS_WR_5_RC_PKT7_STRT_PTR_FIFO_ERROR_SHIFT                                             29
+  #define BMB_REG_INT_STS_WR_5_RC_PKT7_SECOND_PTR_FIFO_ERROR                                                 (0x1<<30) // Read packet client7 second pointer FIFO
+  #define BMB_REG_INT_STS_WR_5_RC_PKT7_SECOND_PTR_FIFO_ERROR_SHIFT                                           30
+  #define BMB_REG_INT_STS_WR_5_RC_PKT7_RSP_FIFO_ERROR                                                        (0x1<<31) // Read packet client7 response FIFO error
+  #define BMB_REG_INT_STS_WR_5_RC_PKT7_RSP_FIFO_ERROR_SHIFT                                                  31
+#define BMB_REG_INT_STS_CLR_5                                                                                0x540144UL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT5_RLS_ERROR                                                            (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT5_RLS_ERROR_SHIFT                                                      0
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT5_PROTOCOL_ERROR                                                       (0x1<<2) // Read packet client5 error when packet doesn't have SOP or EOP on read response
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT5_PROTOCOL_ERROR_SHIFT                                                 2
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT5_SIDE_FIFO_ERROR                                                      (0x1<<3) // Read packet client5 side info FIFO error
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT5_SIDE_FIFO_ERROR_SHIFT                                                3
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT5_REQ_FIFO_ERROR                                                       (0x1<<4) // Read packet client5 request FIFO error
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT5_REQ_FIFO_ERROR_SHIFT                                                 4
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT5_BLK_FIFO_ERROR                                                       (0x1<<5) // Read packet client5 block FIFO error
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT5_BLK_FIFO_ERROR_SHIFT                                                 5
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT5_RLS_LEFT_FIFO_ERROR                                                  (0x1<<6) // Read packet client5 releases left FIFO error
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT5_RLS_LEFT_FIFO_ERROR_SHIFT                                            6
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT5_STRT_PTR_FIFO_ERROR                                                  (0x1<<7) // Read packet client5 start pointer FIFO error
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT5_STRT_PTR_FIFO_ERROR_SHIFT                                            7
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT5_SECOND_PTR_FIFO_ERROR                                                (0x1<<8) // Read packet client5 second pointer FIFO
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT5_SECOND_PTR_FIFO_ERROR_SHIFT                                          8
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT5_RSP_FIFO_ERROR                                                       (0x1<<9) // Read packet client5 response FIFO error
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT5_RSP_FIFO_ERROR_SHIFT                                                 9
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT5_DSCR_FIFO_ERROR                                                      (0x1<<10) // Read packet client5 descriptor FIFO error
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT5_DSCR_FIFO_ERROR_SHIFT                                                10
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT6_RLS_ERROR                                                            (0x1<<11) // Read packet client6 error when number of requested packet copies is bigger than real number of packet copies
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT6_RLS_ERROR_SHIFT                                                      11
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT6_PROTOCOL_ERROR                                                       (0x1<<13) // Read packet client6 error when packet doesn't have SOP or EOP on read response
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT6_PROTOCOL_ERROR_SHIFT                                                 13
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT6_SIDE_FIFO_ERROR                                                      (0x1<<14) // Read packet client6 side info FIFO error
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT6_SIDE_FIFO_ERROR_SHIFT                                                14
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT6_REQ_FIFO_ERROR                                                       (0x1<<15) // Read packet client6 request FIFO error
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT6_REQ_FIFO_ERROR_SHIFT                                                 15
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT6_BLK_FIFO_ERROR                                                       (0x1<<16) // Read packet client6 block FIFO error
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT6_BLK_FIFO_ERROR_SHIFT                                                 16
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT6_RLS_LEFT_FIFO_ERROR                                                  (0x1<<17) // Read packet client6 releases left FIFO error
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT6_RLS_LEFT_FIFO_ERROR_SHIFT                                            17
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT6_STRT_PTR_FIFO_ERROR                                                  (0x1<<18) // Read packet client6 start pointer FIFO error
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT6_STRT_PTR_FIFO_ERROR_SHIFT                                            18
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT6_SECOND_PTR_FIFO_ERROR                                                (0x1<<19) // Read packet client6 second pointer FIFO
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT6_SECOND_PTR_FIFO_ERROR_SHIFT                                          19
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT6_RSP_FIFO_ERROR                                                       (0x1<<20) // Read packet client6 response FIFO error
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT6_RSP_FIFO_ERROR_SHIFT                                                 20
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT6_DSCR_FIFO_ERROR                                                      (0x1<<21) // Read packet client6 descriptor FIFO error
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT6_DSCR_FIFO_ERROR_SHIFT                                                21
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT7_RLS_ERROR                                                            (0x1<<22) // Read packet client7 error when number of requested packet copies is bigger than real number of packet copies
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT7_RLS_ERROR_SHIFT                                                      22
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT7_PROTOCOL_ERROR                                                       (0x1<<24) // Read packet client7 error when packet doesn't have SOP or EOP on read response
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT7_PROTOCOL_ERROR_SHIFT                                                 24
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT7_SIDE_FIFO_ERROR                                                      (0x1<<25) // Read packet client7 side info FIFO error
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT7_SIDE_FIFO_ERROR_SHIFT                                                25
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT7_REQ_FIFO_ERROR                                                       (0x1<<26) // Read packet client7 request FIFO error
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT7_REQ_FIFO_ERROR_SHIFT                                                 26
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT7_BLK_FIFO_ERROR                                                       (0x1<<27) // Read packet client7 block FIFO error
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT7_BLK_FIFO_ERROR_SHIFT                                                 27
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT7_RLS_LEFT_FIFO_ERROR                                                  (0x1<<28) // Read packet client7 releases left FIFO error
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT7_RLS_LEFT_FIFO_ERROR_SHIFT                                            28
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT7_STRT_PTR_FIFO_ERROR                                                  (0x1<<29) // Read packet client7 start pointer FIFO error
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT7_STRT_PTR_FIFO_ERROR_SHIFT                                            29
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT7_SECOND_PTR_FIFO_ERROR                                                (0x1<<30) // Read packet client7 second pointer FIFO
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT7_SECOND_PTR_FIFO_ERROR_SHIFT                                          30
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT7_RSP_FIFO_ERROR                                                       (0x1<<31) // Read packet client7 response FIFO error
+  #define BMB_REG_INT_STS_CLR_5_RC_PKT7_RSP_FIFO_ERROR_SHIFT                                                 31
+#define BMB_REG_INT_STS_6                                                                                    0x540150UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR                                            (0x1<<0) // Packet available SYNC FIFO error
+  #define BMB_REG_INT_STS_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR_SHIFT                                      0
+  #define BMB_REG_INT_STS_6_RC_PKT8_RLS_ERROR                                                                (0x1<<1) // Read packet client8 error when number of requested packet copies is bigger than real number of packet copies
+  #define BMB_REG_INT_STS_6_RC_PKT8_RLS_ERROR_SHIFT                                                          1
+  #define BMB_REG_INT_STS_6_RC_PKT8_PROTOCOL_ERROR                                                           (0x1<<3) // Read packet client8 error when packet doesn't have SOP or EOP on read response
+  #define BMB_REG_INT_STS_6_RC_PKT8_PROTOCOL_ERROR_SHIFT                                                     3
+  #define BMB_REG_INT_STS_6_RC_PKT8_SIDE_FIFO_ERROR                                                          (0x1<<4) // Read packet client8 side info FIFO error
+  #define BMB_REG_INT_STS_6_RC_PKT8_SIDE_FIFO_ERROR_SHIFT                                                    4
+  #define BMB_REG_INT_STS_6_RC_PKT8_REQ_FIFO_ERROR                                                           (0x1<<5) // Read packet client8 request FIFO error
+  #define BMB_REG_INT_STS_6_RC_PKT8_REQ_FIFO_ERROR_SHIFT                                                     5
+  #define BMB_REG_INT_STS_6_RC_PKT8_BLK_FIFO_ERROR                                                           (0x1<<6) // Read packet client8 block FIFO error
+  #define BMB_REG_INT_STS_6_RC_PKT8_BLK_FIFO_ERROR_SHIFT                                                     6
+  #define BMB_REG_INT_STS_6_RC_PKT8_RLS_LEFT_FIFO_ERROR                                                      (0x1<<7) // Read packet client8 releases left FIFO error
+  #define BMB_REG_INT_STS_6_RC_PKT8_RLS_LEFT_FIFO_ERROR_SHIFT                                                7
+  #define BMB_REG_INT_STS_6_RC_PKT8_STRT_PTR_FIFO_ERROR                                                      (0x1<<8) // Read packet client8 start pointer FIFO error
+  #define BMB_REG_INT_STS_6_RC_PKT8_STRT_PTR_FIFO_ERROR_SHIFT                                                8
+  #define BMB_REG_INT_STS_6_RC_PKT8_SECOND_PTR_FIFO_ERROR                                                    (0x1<<9) // Read packet client8 second pointer FIFO
+  #define BMB_REG_INT_STS_6_RC_PKT8_SECOND_PTR_FIFO_ERROR_SHIFT                                              9
+  #define BMB_REG_INT_STS_6_RC_PKT8_RSP_FIFO_ERROR                                                           (0x1<<10) // Read packet client8 response FIFO error
+  #define BMB_REG_INT_STS_6_RC_PKT8_RSP_FIFO_ERROR_SHIFT                                                     10
+  #define BMB_REG_INT_STS_6_RC_PKT8_DSCR_FIFO_ERROR                                                          (0x1<<11) // Read packet client8 descriptor FIFO error
+  #define BMB_REG_INT_STS_6_RC_PKT8_DSCR_FIFO_ERROR_SHIFT                                                    11
+  #define BMB_REG_INT_STS_6_RC_PKT9_RLS_ERROR                                                                (0x1<<12) // Read packet client9 error when number of requested packet copies is bigger than real number of packet copies
+  #define BMB_REG_INT_STS_6_RC_PKT9_RLS_ERROR_SHIFT                                                          12
+  #define BMB_REG_INT_STS_6_RC_PKT9_PROTOCOL_ERROR                                                           (0x1<<14) // Read packet client9 error when packet doesn't have SOP or EOP on read response
+  #define BMB_REG_INT_STS_6_RC_PKT9_PROTOCOL_ERROR_SHIFT                                                     14
+  #define BMB_REG_INT_STS_6_RC_PKT9_SIDE_FIFO_ERROR                                                          (0x1<<15) // Read packet client9 side info FIFO error
+  #define BMB_REG_INT_STS_6_RC_PKT9_SIDE_FIFO_ERROR_SHIFT                                                    15
+  #define BMB_REG_INT_STS_6_RC_PKT9_REQ_FIFO_ERROR                                                           (0x1<<16) // Read packet client9 request FIFO error
+  #define BMB_REG_INT_STS_6_RC_PKT9_REQ_FIFO_ERROR_SHIFT                                                     16
+  #define BMB_REG_INT_STS_6_RC_PKT9_BLK_FIFO_ERROR                                                           (0x1<<17) // Read packet client9 block FIFO error
+  #define BMB_REG_INT_STS_6_RC_PKT9_BLK_FIFO_ERROR_SHIFT                                                     17
+  #define BMB_REG_INT_STS_6_RC_PKT9_RLS_LEFT_FIFO_ERROR                                                      (0x1<<18) // Read packet client9 releases left FIFO error
+  #define BMB_REG_INT_STS_6_RC_PKT9_RLS_LEFT_FIFO_ERROR_SHIFT                                                18
+  #define BMB_REG_INT_STS_6_RC_PKT9_STRT_PTR_FIFO_ERROR                                                      (0x1<<19) // Read packet client9 start pointer FIFO error
+  #define BMB_REG_INT_STS_6_RC_PKT9_STRT_PTR_FIFO_ERROR_SHIFT                                                19
+  #define BMB_REG_INT_STS_6_RC_PKT9_SECOND_PTR_FIFO_ERROR                                                    (0x1<<20) // Read packet client9 second pointer FIFO
+  #define BMB_REG_INT_STS_6_RC_PKT9_SECOND_PTR_FIFO_ERROR_SHIFT                                              20
+  #define BMB_REG_INT_STS_6_RC_PKT9_RSP_FIFO_ERROR                                                           (0x1<<21) // Read packet client9 response FIFO error
+  #define BMB_REG_INT_STS_6_RC_PKT9_RSP_FIFO_ERROR_SHIFT                                                     21
+  #define BMB_REG_INT_STS_6_RC_PKT9_DSCR_FIFO_ERROR                                                          (0x1<<22) // Read packet client9 descriptor FIFO error
+  #define BMB_REG_INT_STS_6_RC_PKT9_DSCR_FIFO_ERROR_SHIFT                                                    22
+  #define BMB_REG_INT_STS_6_WC4_PROTOCOL_ERROR                                                               (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 4.
+  #define BMB_REG_INT_STS_6_WC4_PROTOCOL_ERROR_SHIFT                                                         23
+  #define BMB_REG_INT_STS_6_WC5_PROTOCOL_ERROR                                                               (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 5
+  #define BMB_REG_INT_STS_6_WC5_PROTOCOL_ERROR_SHIFT                                                         24
+  #define BMB_REG_INT_STS_6_WC6_PROTOCOL_ERROR                                                               (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 6
+  #define BMB_REG_INT_STS_6_WC6_PROTOCOL_ERROR_SHIFT                                                         25
+  #define BMB_REG_INT_STS_6_WC7_PROTOCOL_ERROR                                                               (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 7
+  #define BMB_REG_INT_STS_6_WC7_PROTOCOL_ERROR_SHIFT                                                         26
+  #define BMB_REG_INT_STS_6_WC8_PROTOCOL_ERROR                                                               (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 8
+  #define BMB_REG_INT_STS_6_WC8_PROTOCOL_ERROR_SHIFT                                                         27
+  #define BMB_REG_INT_STS_6_WC9_PROTOCOL_ERROR                                                               (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 9
+  #define BMB_REG_INT_STS_6_WC9_PROTOCOL_ERROR_SHIFT                                                         28
+  #define BMB_REG_INT_STS_6_WC4_INP_FIFO_ERROR                                                               (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 4 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_6_WC4_INP_FIFO_ERROR_SHIFT                                                         29
+  #define BMB_REG_INT_STS_6_WC4_SOP_FIFO_ERROR                                                               (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 4
+  #define BMB_REG_INT_STS_6_WC4_SOP_FIFO_ERROR_SHIFT                                                         30
+  #define BMB_REG_INT_STS_6_WC4_QUEUE_FIFO_ERROR                                                             (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 4
+  #define BMB_REG_INT_STS_6_WC4_QUEUE_FIFO_ERROR_SHIFT                                                       31
+#define BMB_REG_INT_MASK_6                                                                                   0x540154UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_MASK_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR                                           (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR .
+  #define BMB_REG_INT_MASK_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR_SHIFT                                     0
+  #define BMB_REG_INT_MASK_6_RC_PKT8_RLS_ERROR                                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_RLS_ERROR .
+  #define BMB_REG_INT_MASK_6_RC_PKT8_RLS_ERROR_SHIFT                                                         1
+  #define BMB_REG_INT_MASK_6_RC_PKT8_PROTOCOL_ERROR                                                          (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_PROTOCOL_ERROR .
+  #define BMB_REG_INT_MASK_6_RC_PKT8_PROTOCOL_ERROR_SHIFT                                                    3
+  #define BMB_REG_INT_MASK_6_RC_PKT8_SIDE_FIFO_ERROR                                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_SIDE_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_6_RC_PKT8_SIDE_FIFO_ERROR_SHIFT                                                   4
+  #define BMB_REG_INT_MASK_6_RC_PKT8_REQ_FIFO_ERROR                                                          (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_REQ_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_6_RC_PKT8_REQ_FIFO_ERROR_SHIFT                                                    5
+  #define BMB_REG_INT_MASK_6_RC_PKT8_BLK_FIFO_ERROR                                                          (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_BLK_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_6_RC_PKT8_BLK_FIFO_ERROR_SHIFT                                                    6
+  #define BMB_REG_INT_MASK_6_RC_PKT8_RLS_LEFT_FIFO_ERROR                                                     (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_RLS_LEFT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_6_RC_PKT8_RLS_LEFT_FIFO_ERROR_SHIFT                                               7
+  #define BMB_REG_INT_MASK_6_RC_PKT8_STRT_PTR_FIFO_ERROR                                                     (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_STRT_PTR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_6_RC_PKT8_STRT_PTR_FIFO_ERROR_SHIFT                                               8
+  #define BMB_REG_INT_MASK_6_RC_PKT8_SECOND_PTR_FIFO_ERROR                                                   (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_SECOND_PTR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_6_RC_PKT8_SECOND_PTR_FIFO_ERROR_SHIFT                                             9
+  #define BMB_REG_INT_MASK_6_RC_PKT8_RSP_FIFO_ERROR                                                          (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_RSP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_6_RC_PKT8_RSP_FIFO_ERROR_SHIFT                                                    10
+  #define BMB_REG_INT_MASK_6_RC_PKT8_DSCR_FIFO_ERROR                                                         (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_DSCR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_6_RC_PKT8_DSCR_FIFO_ERROR_SHIFT                                                   11
+  #define BMB_REG_INT_MASK_6_RC_PKT9_RLS_ERROR                                                               (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_RLS_ERROR .
+  #define BMB_REG_INT_MASK_6_RC_PKT9_RLS_ERROR_SHIFT                                                         12
+  #define BMB_REG_INT_MASK_6_RC_PKT9_PROTOCOL_ERROR                                                          (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_PROTOCOL_ERROR .
+  #define BMB_REG_INT_MASK_6_RC_PKT9_PROTOCOL_ERROR_SHIFT                                                    14
+  #define BMB_REG_INT_MASK_6_RC_PKT9_SIDE_FIFO_ERROR                                                         (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_SIDE_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_6_RC_PKT9_SIDE_FIFO_ERROR_SHIFT                                                   15
+  #define BMB_REG_INT_MASK_6_RC_PKT9_REQ_FIFO_ERROR                                                          (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_REQ_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_6_RC_PKT9_REQ_FIFO_ERROR_SHIFT                                                    16
+  #define BMB_REG_INT_MASK_6_RC_PKT9_BLK_FIFO_ERROR                                                          (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_BLK_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_6_RC_PKT9_BLK_FIFO_ERROR_SHIFT                                                    17
+  #define BMB_REG_INT_MASK_6_RC_PKT9_RLS_LEFT_FIFO_ERROR                                                     (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_RLS_LEFT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_6_RC_PKT9_RLS_LEFT_FIFO_ERROR_SHIFT                                               18
+  #define BMB_REG_INT_MASK_6_RC_PKT9_STRT_PTR_FIFO_ERROR                                                     (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_STRT_PTR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_6_RC_PKT9_STRT_PTR_FIFO_ERROR_SHIFT                                               19
+  #define BMB_REG_INT_MASK_6_RC_PKT9_SECOND_PTR_FIFO_ERROR                                                   (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_SECOND_PTR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_6_RC_PKT9_SECOND_PTR_FIFO_ERROR_SHIFT                                             20
+  #define BMB_REG_INT_MASK_6_RC_PKT9_RSP_FIFO_ERROR                                                          (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_RSP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_6_RC_PKT9_RSP_FIFO_ERROR_SHIFT                                                    21
+  #define BMB_REG_INT_MASK_6_RC_PKT9_DSCR_FIFO_ERROR                                                         (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_DSCR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_6_RC_PKT9_DSCR_FIFO_ERROR_SHIFT                                                   22
+  #define BMB_REG_INT_MASK_6_WC4_PROTOCOL_ERROR                                                              (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC4_PROTOCOL_ERROR .
+  #define BMB_REG_INT_MASK_6_WC4_PROTOCOL_ERROR_SHIFT                                                        23
+  #define BMB_REG_INT_MASK_6_WC5_PROTOCOL_ERROR                                                              (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC5_PROTOCOL_ERROR .
+  #define BMB_REG_INT_MASK_6_WC5_PROTOCOL_ERROR_SHIFT                                                        24
+  #define BMB_REG_INT_MASK_6_WC6_PROTOCOL_ERROR                                                              (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC6_PROTOCOL_ERROR .
+  #define BMB_REG_INT_MASK_6_WC6_PROTOCOL_ERROR_SHIFT                                                        25
+  #define BMB_REG_INT_MASK_6_WC7_PROTOCOL_ERROR                                                              (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC7_PROTOCOL_ERROR .
+  #define BMB_REG_INT_MASK_6_WC7_PROTOCOL_ERROR_SHIFT                                                        26
+  #define BMB_REG_INT_MASK_6_WC8_PROTOCOL_ERROR                                                              (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC8_PROTOCOL_ERROR .
+  #define BMB_REG_INT_MASK_6_WC8_PROTOCOL_ERROR_SHIFT                                                        27
+  #define BMB_REG_INT_MASK_6_WC9_PROTOCOL_ERROR                                                              (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC9_PROTOCOL_ERROR .
+  #define BMB_REG_INT_MASK_6_WC9_PROTOCOL_ERROR_SHIFT                                                        28
+  #define BMB_REG_INT_MASK_6_WC4_INP_FIFO_ERROR                                                              (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC4_INP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_6_WC4_INP_FIFO_ERROR_SHIFT                                                        29
+  #define BMB_REG_INT_MASK_6_WC4_SOP_FIFO_ERROR                                                              (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC4_SOP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_6_WC4_SOP_FIFO_ERROR_SHIFT                                                        30
+  #define BMB_REG_INT_MASK_6_WC4_QUEUE_FIFO_ERROR                                                            (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC4_QUEUE_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_6_WC4_QUEUE_FIFO_ERROR_SHIFT                                                      31
+#define BMB_REG_INT_STS_WR_6                                                                                 0x540158UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_WR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR                                         (0x1<<0) // Packet available SYNC FIFO error
+  #define BMB_REG_INT_STS_WR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR_SHIFT                                   0
+  #define BMB_REG_INT_STS_WR_6_RC_PKT8_RLS_ERROR                                                             (0x1<<1) // Read packet client8 error when number of requested packet copies is bigger than real number of packet copies
+  #define BMB_REG_INT_STS_WR_6_RC_PKT8_RLS_ERROR_SHIFT                                                       1
+  #define BMB_REG_INT_STS_WR_6_RC_PKT8_PROTOCOL_ERROR                                                        (0x1<<3) // Read packet client8 error when packet doesn't have SOP or EOP on read response
+  #define BMB_REG_INT_STS_WR_6_RC_PKT8_PROTOCOL_ERROR_SHIFT                                                  3
+  #define BMB_REG_INT_STS_WR_6_RC_PKT8_SIDE_FIFO_ERROR                                                       (0x1<<4) // Read packet client8 side info FIFO error
+  #define BMB_REG_INT_STS_WR_6_RC_PKT8_SIDE_FIFO_ERROR_SHIFT                                                 4
+  #define BMB_REG_INT_STS_WR_6_RC_PKT8_REQ_FIFO_ERROR                                                        (0x1<<5) // Read packet client8 request FIFO error
+  #define BMB_REG_INT_STS_WR_6_RC_PKT8_REQ_FIFO_ERROR_SHIFT                                                  5
+  #define BMB_REG_INT_STS_WR_6_RC_PKT8_BLK_FIFO_ERROR                                                        (0x1<<6) // Read packet client8 block FIFO error
+  #define BMB_REG_INT_STS_WR_6_RC_PKT8_BLK_FIFO_ERROR_SHIFT                                                  6
+  #define BMB_REG_INT_STS_WR_6_RC_PKT8_RLS_LEFT_FIFO_ERROR                                                   (0x1<<7) // Read packet client8 releases left FIFO error
+  #define BMB_REG_INT_STS_WR_6_RC_PKT8_RLS_LEFT_FIFO_ERROR_SHIFT                                             7
+  #define BMB_REG_INT_STS_WR_6_RC_PKT8_STRT_PTR_FIFO_ERROR                                                   (0x1<<8) // Read packet client8 start pointer FIFO error
+  #define BMB_REG_INT_STS_WR_6_RC_PKT8_STRT_PTR_FIFO_ERROR_SHIFT                                             8
+  #define BMB_REG_INT_STS_WR_6_RC_PKT8_SECOND_PTR_FIFO_ERROR                                                 (0x1<<9) // Read packet client8 second pointer FIFO
+  #define BMB_REG_INT_STS_WR_6_RC_PKT8_SECOND_PTR_FIFO_ERROR_SHIFT                                           9
+  #define BMB_REG_INT_STS_WR_6_RC_PKT8_RSP_FIFO_ERROR                                                        (0x1<<10) // Read packet client8 response FIFO error
+  #define BMB_REG_INT_STS_WR_6_RC_PKT8_RSP_FIFO_ERROR_SHIFT                                                  10
+  #define BMB_REG_INT_STS_WR_6_RC_PKT8_DSCR_FIFO_ERROR                                                       (0x1<<11) // Read packet client8 descriptor FIFO error
+  #define BMB_REG_INT_STS_WR_6_RC_PKT8_DSCR_FIFO_ERROR_SHIFT                                                 11
+  #define BMB_REG_INT_STS_WR_6_RC_PKT9_RLS_ERROR                                                             (0x1<<12) // Read packet client9 error when number of requested packet copies is bigger than real number of packet copies
+  #define BMB_REG_INT_STS_WR_6_RC_PKT9_RLS_ERROR_SHIFT                                                       12
+  #define BMB_REG_INT_STS_WR_6_RC_PKT9_PROTOCOL_ERROR                                                        (0x1<<14) // Read packet client9 error when packet doesn't have SOP or EOP on read response
+  #define BMB_REG_INT_STS_WR_6_RC_PKT9_PROTOCOL_ERROR_SHIFT                                                  14
+  #define BMB_REG_INT_STS_WR_6_RC_PKT9_SIDE_FIFO_ERROR                                                       (0x1<<15) // Read packet client9 side info FIFO error
+  #define BMB_REG_INT_STS_WR_6_RC_PKT9_SIDE_FIFO_ERROR_SHIFT                                                 15
+  #define BMB_REG_INT_STS_WR_6_RC_PKT9_REQ_FIFO_ERROR                                                        (0x1<<16) // Read packet client9 request FIFO error
+  #define BMB_REG_INT_STS_WR_6_RC_PKT9_REQ_FIFO_ERROR_SHIFT                                                  16
+  #define BMB_REG_INT_STS_WR_6_RC_PKT9_BLK_FIFO_ERROR                                                        (0x1<<17) // Read packet client9 block FIFO error
+  #define BMB_REG_INT_STS_WR_6_RC_PKT9_BLK_FIFO_ERROR_SHIFT                                                  17
+  #define BMB_REG_INT_STS_WR_6_RC_PKT9_RLS_LEFT_FIFO_ERROR                                                   (0x1<<18) // Read packet client9 releases left FIFO error
+  #define BMB_REG_INT_STS_WR_6_RC_PKT9_RLS_LEFT_FIFO_ERROR_SHIFT                                             18
+  #define BMB_REG_INT_STS_WR_6_RC_PKT9_STRT_PTR_FIFO_ERROR                                                   (0x1<<19) // Read packet client9 start pointer FIFO error
+  #define BMB_REG_INT_STS_WR_6_RC_PKT9_STRT_PTR_FIFO_ERROR_SHIFT                                             19
+  #define BMB_REG_INT_STS_WR_6_RC_PKT9_SECOND_PTR_FIFO_ERROR                                                 (0x1<<20) // Read packet client9 second pointer FIFO
+  #define BMB_REG_INT_STS_WR_6_RC_PKT9_SECOND_PTR_FIFO_ERROR_SHIFT                                           20
+  #define BMB_REG_INT_STS_WR_6_RC_PKT9_RSP_FIFO_ERROR                                                        (0x1<<21) // Read packet client9 response FIFO error
+  #define BMB_REG_INT_STS_WR_6_RC_PKT9_RSP_FIFO_ERROR_SHIFT                                                  21
+  #define BMB_REG_INT_STS_WR_6_RC_PKT9_DSCR_FIFO_ERROR                                                       (0x1<<22) // Read packet client9 descriptor FIFO error
+  #define BMB_REG_INT_STS_WR_6_RC_PKT9_DSCR_FIFO_ERROR_SHIFT                                                 22
+  #define BMB_REG_INT_STS_WR_6_WC4_PROTOCOL_ERROR                                                            (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 4.
+  #define BMB_REG_INT_STS_WR_6_WC4_PROTOCOL_ERROR_SHIFT                                                      23
+  #define BMB_REG_INT_STS_WR_6_WC5_PROTOCOL_ERROR                                                            (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 5
+  #define BMB_REG_INT_STS_WR_6_WC5_PROTOCOL_ERROR_SHIFT                                                      24
+  #define BMB_REG_INT_STS_WR_6_WC6_PROTOCOL_ERROR                                                            (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 6
+  #define BMB_REG_INT_STS_WR_6_WC6_PROTOCOL_ERROR_SHIFT                                                      25
+  #define BMB_REG_INT_STS_WR_6_WC7_PROTOCOL_ERROR                                                            (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 7
+  #define BMB_REG_INT_STS_WR_6_WC7_PROTOCOL_ERROR_SHIFT                                                      26
+  #define BMB_REG_INT_STS_WR_6_WC8_PROTOCOL_ERROR                                                            (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 8
+  #define BMB_REG_INT_STS_WR_6_WC8_PROTOCOL_ERROR_SHIFT                                                      27
+  #define BMB_REG_INT_STS_WR_6_WC9_PROTOCOL_ERROR                                                            (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 9
+  #define BMB_REG_INT_STS_WR_6_WC9_PROTOCOL_ERROR_SHIFT                                                      28
+  #define BMB_REG_INT_STS_WR_6_WC4_INP_FIFO_ERROR                                                            (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 4 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_WR_6_WC4_INP_FIFO_ERROR_SHIFT                                                      29
+  #define BMB_REG_INT_STS_WR_6_WC4_SOP_FIFO_ERROR                                                            (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 4
+  #define BMB_REG_INT_STS_WR_6_WC4_SOP_FIFO_ERROR_SHIFT                                                      30
+  #define BMB_REG_INT_STS_WR_6_WC4_QUEUE_FIFO_ERROR                                                          (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 4
+  #define BMB_REG_INT_STS_WR_6_WC4_QUEUE_FIFO_ERROR_SHIFT                                                    31
+#define BMB_REG_INT_STS_CLR_6                                                                                0x54015cUL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_CLR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR                                        (0x1<<0) // Packet available SYNC FIFO error
+  #define BMB_REG_INT_STS_CLR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR_SHIFT                                  0
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT8_RLS_ERROR                                                            (0x1<<1) // Read packet client8 error when number of requested packet copies is bigger than real number of packet copies
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT8_RLS_ERROR_SHIFT                                                      1
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT8_PROTOCOL_ERROR                                                       (0x1<<3) // Read packet client8 error when packet doesn't have SOP or EOP on read response
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT8_PROTOCOL_ERROR_SHIFT                                                 3
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT8_SIDE_FIFO_ERROR                                                      (0x1<<4) // Read packet client8 side info FIFO error
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT8_SIDE_FIFO_ERROR_SHIFT                                                4
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT8_REQ_FIFO_ERROR                                                       (0x1<<5) // Read packet client8 request FIFO error
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT8_REQ_FIFO_ERROR_SHIFT                                                 5
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT8_BLK_FIFO_ERROR                                                       (0x1<<6) // Read packet client8 block FIFO error
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT8_BLK_FIFO_ERROR_SHIFT                                                 6
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT8_RLS_LEFT_FIFO_ERROR                                                  (0x1<<7) // Read packet client8 releases left FIFO error
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT8_RLS_LEFT_FIFO_ERROR_SHIFT                                            7
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT8_STRT_PTR_FIFO_ERROR                                                  (0x1<<8) // Read packet client8 start pointer FIFO error
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT8_STRT_PTR_FIFO_ERROR_SHIFT                                            8
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT8_SECOND_PTR_FIFO_ERROR                                                (0x1<<9) // Read packet client8 second pointer FIFO
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT8_SECOND_PTR_FIFO_ERROR_SHIFT                                          9
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT8_RSP_FIFO_ERROR                                                       (0x1<<10) // Read packet client8 response FIFO error
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT8_RSP_FIFO_ERROR_SHIFT                                                 10
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT8_DSCR_FIFO_ERROR                                                      (0x1<<11) // Read packet client8 descriptor FIFO error
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT8_DSCR_FIFO_ERROR_SHIFT                                                11
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT9_RLS_ERROR                                                            (0x1<<12) // Read packet client9 error when number of requested packet copies is bigger than real number of packet copies
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT9_RLS_ERROR_SHIFT                                                      12
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT9_PROTOCOL_ERROR                                                       (0x1<<14) // Read packet client9 error when packet doesn't have SOP or EOP on read response
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT9_PROTOCOL_ERROR_SHIFT                                                 14
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT9_SIDE_FIFO_ERROR                                                      (0x1<<15) // Read packet client9 side info FIFO error
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT9_SIDE_FIFO_ERROR_SHIFT                                                15
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT9_REQ_FIFO_ERROR                                                       (0x1<<16) // Read packet client9 request FIFO error
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT9_REQ_FIFO_ERROR_SHIFT                                                 16
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT9_BLK_FIFO_ERROR                                                       (0x1<<17) // Read packet client9 block FIFO error
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT9_BLK_FIFO_ERROR_SHIFT                                                 17
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT9_RLS_LEFT_FIFO_ERROR                                                  (0x1<<18) // Read packet client9 releases left FIFO error
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT9_RLS_LEFT_FIFO_ERROR_SHIFT                                            18
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT9_STRT_PTR_FIFO_ERROR                                                  (0x1<<19) // Read packet client9 start pointer FIFO error
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT9_STRT_PTR_FIFO_ERROR_SHIFT                                            19
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT9_SECOND_PTR_FIFO_ERROR                                                (0x1<<20) // Read packet client9 second pointer FIFO
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT9_SECOND_PTR_FIFO_ERROR_SHIFT                                          20
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT9_RSP_FIFO_ERROR                                                       (0x1<<21) // Read packet client9 response FIFO error
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT9_RSP_FIFO_ERROR_SHIFT                                                 21
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT9_DSCR_FIFO_ERROR                                                      (0x1<<22) // Read packet client9 descriptor FIFO error
+  #define BMB_REG_INT_STS_CLR_6_RC_PKT9_DSCR_FIFO_ERROR_SHIFT                                                22
+  #define BMB_REG_INT_STS_CLR_6_WC4_PROTOCOL_ERROR                                                           (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 4.
+  #define BMB_REG_INT_STS_CLR_6_WC4_PROTOCOL_ERROR_SHIFT                                                     23
+  #define BMB_REG_INT_STS_CLR_6_WC5_PROTOCOL_ERROR                                                           (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 5
+  #define BMB_REG_INT_STS_CLR_6_WC5_PROTOCOL_ERROR_SHIFT                                                     24
+  #define BMB_REG_INT_STS_CLR_6_WC6_PROTOCOL_ERROR                                                           (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 6
+  #define BMB_REG_INT_STS_CLR_6_WC6_PROTOCOL_ERROR_SHIFT                                                     25
+  #define BMB_REG_INT_STS_CLR_6_WC7_PROTOCOL_ERROR                                                           (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 7
+  #define BMB_REG_INT_STS_CLR_6_WC7_PROTOCOL_ERROR_SHIFT                                                     26
+  #define BMB_REG_INT_STS_CLR_6_WC8_PROTOCOL_ERROR                                                           (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 8
+  #define BMB_REG_INT_STS_CLR_6_WC8_PROTOCOL_ERROR_SHIFT                                                     27
+  #define BMB_REG_INT_STS_CLR_6_WC9_PROTOCOL_ERROR                                                           (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 9
+  #define BMB_REG_INT_STS_CLR_6_WC9_PROTOCOL_ERROR_SHIFT                                                     28
+  #define BMB_REG_INT_STS_CLR_6_WC4_INP_FIFO_ERROR                                                           (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 4 RX_INT::/RX_INT/d in Comments.
+  #define BMB_REG_INT_STS_CLR_6_WC4_INP_FIFO_ERROR_SHIFT                                                     29
+  #define BMB_REG_INT_STS_CLR_6_WC4_SOP_FIFO_ERROR                                                           (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 4
+  #define BMB_REG_INT_STS_CLR_6_WC4_SOP_FIFO_ERROR_SHIFT                                                     30
+  #define BMB_REG_INT_STS_CLR_6_WC4_QUEUE_FIFO_ERROR                                                         (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 4
+  #define BMB_REG_INT_STS_CLR_6_WC4_QUEUE_FIFO_ERROR_SHIFT                                                   31
+#define BMB_REG_INT_STS_7                                                                                    0x540168UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_7_WC4_FREE_POINT_FIFO_ERROR                                                        (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 4
+  #define BMB_REG_INT_STS_7_WC4_FREE_POINT_FIFO_ERROR_SHIFT                                                  0
+  #define BMB_REG_INT_STS_7_WC4_NEXT_POINT_FIFO_ERROR                                                        (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 4
+  #define BMB_REG_INT_STS_7_WC4_NEXT_POINT_FIFO_ERROR_SHIFT                                                  1
+  #define BMB_REG_INT_STS_7_WC4_STRT_FIFO_ERROR                                                              (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 4
+  #define BMB_REG_INT_STS_7_WC4_STRT_FIFO_ERROR_SHIFT                                                        2
+  #define BMB_REG_INT_STS_7_WC4_SECOND_DSCR_FIFO_ERROR                                                       (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 4
+  #define BMB_REG_INT_STS_7_WC4_SECOND_DSCR_FIFO_ERROR_SHIFT                                                 3
+  #define BMB_REG_INT_STS_7_WC4_PKT_AVAIL_FIFO_ERROR                                                         (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 4
+  #define BMB_REG_INT_STS_7_WC4_PKT_AVAIL_FIFO_ERROR_SHIFT                                                   4
+  #define BMB_REG_INT_STS_7_WC4_COS_CNT_FIFO_ERROR                                                           (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 4
+  #define BMB_REG_INT_STS_7_WC4_COS_CNT_FIFO_ERROR_SHIFT                                                     5
+  #define BMB_REG_INT_STS_7_WC4_NOTIFY_FIFO_ERROR                                                            (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 4
+  #define BMB_REG_INT_STS_7_WC4_NOTIFY_FIFO_ERROR_SHIFT                                                      6
+  #define BMB_REG_INT_STS_7_WC4_LL_REQ_FIFO_ERROR                                                            (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 4
+  #define BMB_REG_INT_STS_7_WC4_LL_REQ_FIFO_ERROR_SHIFT                                                      7
+  #define BMB_REG_INT_STS_7_WC4_LL_PA_CNT_ERROR                                                              (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 4
+  #define BMB_REG_INT_STS_7_WC4_LL_PA_CNT_ERROR_SHIFT                                                        8
+  #define BMB_REG_INT_STS_7_WC4_BB_PA_CNT_ERROR                                                              (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 4
+  #define BMB_REG_INT_STS_7_WC4_BB_PA_CNT_ERROR_SHIFT                                                        9
+  #define BMB_REG_INT_STS_7_WC5_INP_FIFO_ERROR                                                               (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 5
+  #define BMB_REG_INT_STS_7_WC5_INP_FIFO_ERROR_SHIFT                                                         10
+  #define BMB_REG_INT_STS_7_WC5_SOP_FIFO_ERROR                                                               (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 5
+  #define BMB_REG_INT_STS_7_WC5_SOP_FIFO_ERROR_SHIFT                                                         11
+  #define BMB_REG_INT_STS_7_WC5_QUEUE_FIFO_ERROR                                                             (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 5
+  #define BMB_REG_INT_STS_7_WC5_QUEUE_FIFO_ERROR_SHIFT                                                       12
+  #define BMB_REG_INT_STS_7_WC5_FREE_POINT_FIFO_ERROR                                                        (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 5
+  #define BMB_REG_INT_STS_7_WC5_FREE_POINT_FIFO_ERROR_SHIFT                                                  13
+  #define BMB_REG_INT_STS_7_WC5_NEXT_POINT_FIFO_ERROR                                                        (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 5
+  #define BMB_REG_INT_STS_7_WC5_NEXT_POINT_FIFO_ERROR_SHIFT                                                  14
+  #define BMB_REG_INT_STS_7_WC5_STRT_FIFO_ERROR                                                              (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 5
+  #define BMB_REG_INT_STS_7_WC5_STRT_FIFO_ERROR_SHIFT                                                        15
+  #define BMB_REG_INT_STS_7_WC5_SECOND_DSCR_FIFO_ERROR                                                       (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 5
+  #define BMB_REG_INT_STS_7_WC5_SECOND_DSCR_FIFO_ERROR_SHIFT                                                 16
+  #define BMB_REG_INT_STS_7_WC5_PKT_AVAIL_FIFO_ERROR                                                         (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 5
+  #define BMB_REG_INT_STS_7_WC5_PKT_AVAIL_FIFO_ERROR_SHIFT                                                   17
+  #define BMB_REG_INT_STS_7_WC5_COS_CNT_FIFO_ERROR                                                           (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 5
+  #define BMB_REG_INT_STS_7_WC5_COS_CNT_FIFO_ERROR_SHIFT                                                     18
+  #define BMB_REG_INT_STS_7_WC5_NOTIFY_FIFO_ERROR                                                            (0x1<<19) // Notify FIFO error in write client 5
+  #define BMB_REG_INT_STS_7_WC5_NOTIFY_FIFO_ERROR_SHIFT                                                      19
+  #define BMB_REG_INT_STS_7_WC5_LL_REQ_FIFO_ERROR                                                            (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 5
+  #define BMB_REG_INT_STS_7_WC5_LL_REQ_FIFO_ERROR_SHIFT                                                      20
+  #define BMB_REG_INT_STS_7_WC5_LL_PA_CNT_ERROR                                                              (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 5
+  #define BMB_REG_INT_STS_7_WC5_LL_PA_CNT_ERROR_SHIFT                                                        21
+  #define BMB_REG_INT_STS_7_WC5_BB_PA_CNT_ERROR                                                              (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 5
+  #define BMB_REG_INT_STS_7_WC5_BB_PA_CNT_ERROR_SHIFT                                                        22
+  #define BMB_REG_INT_STS_7_WC6_INP_FIFO_ERROR                                                               (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 6
+  #define BMB_REG_INT_STS_7_WC6_INP_FIFO_ERROR_SHIFT                                                         23
+  #define BMB_REG_INT_STS_7_WC6_SOP_FIFO_ERROR                                                               (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 6
+  #define BMB_REG_INT_STS_7_WC6_SOP_FIFO_ERROR_SHIFT                                                         24
+  #define BMB_REG_INT_STS_7_WC6_QUEUE_FIFO_ERROR                                                             (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 6
+  #define BMB_REG_INT_STS_7_WC6_QUEUE_FIFO_ERROR_SHIFT                                                       25
+  #define BMB_REG_INT_STS_7_WC6_FREE_POINT_FIFO_ERROR                                                        (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 6
+  #define BMB_REG_INT_STS_7_WC6_FREE_POINT_FIFO_ERROR_SHIFT                                                  26
+  #define BMB_REG_INT_STS_7_WC6_NEXT_POINT_FIFO_ERROR                                                        (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 6
+  #define BMB_REG_INT_STS_7_WC6_NEXT_POINT_FIFO_ERROR_SHIFT                                                  27
+  #define BMB_REG_INT_STS_7_WC6_STRT_FIFO_ERROR                                                              (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 6
+  #define BMB_REG_INT_STS_7_WC6_STRT_FIFO_ERROR_SHIFT                                                        28
+  #define BMB_REG_INT_STS_7_WC6_SECOND_DSCR_FIFO_ERROR                                                       (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 6
+  #define BMB_REG_INT_STS_7_WC6_SECOND_DSCR_FIFO_ERROR_SHIFT                                                 29
+  #define BMB_REG_INT_STS_7_WC6_PKT_AVAIL_FIFO_ERROR                                                         (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 6
+  #define BMB_REG_INT_STS_7_WC6_PKT_AVAIL_FIFO_ERROR_SHIFT                                                   30
+  #define BMB_REG_INT_STS_7_WC6_COS_CNT_FIFO_ERROR                                                           (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 6
+  #define BMB_REG_INT_STS_7_WC6_COS_CNT_FIFO_ERROR_SHIFT                                                     31
+#define BMB_REG_INT_MASK_7                                                                                   0x54016cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_MASK_7_WC4_FREE_POINT_FIFO_ERROR                                                       (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_FREE_POINT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC4_FREE_POINT_FIFO_ERROR_SHIFT                                                 0
+  #define BMB_REG_INT_MASK_7_WC4_NEXT_POINT_FIFO_ERROR                                                       (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_NEXT_POINT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC4_NEXT_POINT_FIFO_ERROR_SHIFT                                                 1
+  #define BMB_REG_INT_MASK_7_WC4_STRT_FIFO_ERROR                                                             (0x1<<2) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_STRT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC4_STRT_FIFO_ERROR_SHIFT                                                       2
+  #define BMB_REG_INT_MASK_7_WC4_SECOND_DSCR_FIFO_ERROR                                                      (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_SECOND_DSCR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC4_SECOND_DSCR_FIFO_ERROR_SHIFT                                                3
+  #define BMB_REG_INT_MASK_7_WC4_PKT_AVAIL_FIFO_ERROR                                                        (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_PKT_AVAIL_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC4_PKT_AVAIL_FIFO_ERROR_SHIFT                                                  4
+  #define BMB_REG_INT_MASK_7_WC4_COS_CNT_FIFO_ERROR                                                          (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_COS_CNT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC4_COS_CNT_FIFO_ERROR_SHIFT                                                    5
+  #define BMB_REG_INT_MASK_7_WC4_NOTIFY_FIFO_ERROR                                                           (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_NOTIFY_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC4_NOTIFY_FIFO_ERROR_SHIFT                                                     6
+  #define BMB_REG_INT_MASK_7_WC4_LL_REQ_FIFO_ERROR                                                           (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_LL_REQ_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC4_LL_REQ_FIFO_ERROR_SHIFT                                                     7
+  #define BMB_REG_INT_MASK_7_WC4_LL_PA_CNT_ERROR                                                             (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_LL_PA_CNT_ERROR .
+  #define BMB_REG_INT_MASK_7_WC4_LL_PA_CNT_ERROR_SHIFT                                                       8
+  #define BMB_REG_INT_MASK_7_WC4_BB_PA_CNT_ERROR                                                             (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_BB_PA_CNT_ERROR .
+  #define BMB_REG_INT_MASK_7_WC4_BB_PA_CNT_ERROR_SHIFT                                                       9
+  #define BMB_REG_INT_MASK_7_WC5_INP_FIFO_ERROR                                                              (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_INP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC5_INP_FIFO_ERROR_SHIFT                                                        10
+  #define BMB_REG_INT_MASK_7_WC5_SOP_FIFO_ERROR                                                              (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_SOP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC5_SOP_FIFO_ERROR_SHIFT                                                        11
+  #define BMB_REG_INT_MASK_7_WC5_QUEUE_FIFO_ERROR                                                            (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_QUEUE_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC5_QUEUE_FIFO_ERROR_SHIFT                                                      12
+  #define BMB_REG_INT_MASK_7_WC5_FREE_POINT_FIFO_ERROR                                                       (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_FREE_POINT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC5_FREE_POINT_FIFO_ERROR_SHIFT                                                 13
+  #define BMB_REG_INT_MASK_7_WC5_NEXT_POINT_FIFO_ERROR                                                       (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_NEXT_POINT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC5_NEXT_POINT_FIFO_ERROR_SHIFT                                                 14
+  #define BMB_REG_INT_MASK_7_WC5_STRT_FIFO_ERROR                                                             (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_STRT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC5_STRT_FIFO_ERROR_SHIFT                                                       15
+  #define BMB_REG_INT_MASK_7_WC5_SECOND_DSCR_FIFO_ERROR                                                      (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_SECOND_DSCR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC5_SECOND_DSCR_FIFO_ERROR_SHIFT                                                16
+  #define BMB_REG_INT_MASK_7_WC5_PKT_AVAIL_FIFO_ERROR                                                        (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_PKT_AVAIL_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC5_PKT_AVAIL_FIFO_ERROR_SHIFT                                                  17
+  #define BMB_REG_INT_MASK_7_WC5_COS_CNT_FIFO_ERROR                                                          (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_COS_CNT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC5_COS_CNT_FIFO_ERROR_SHIFT                                                    18
+  #define BMB_REG_INT_MASK_7_WC5_NOTIFY_FIFO_ERROR                                                           (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_NOTIFY_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC5_NOTIFY_FIFO_ERROR_SHIFT                                                     19
+  #define BMB_REG_INT_MASK_7_WC5_LL_REQ_FIFO_ERROR                                                           (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_LL_REQ_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC5_LL_REQ_FIFO_ERROR_SHIFT                                                     20
+  #define BMB_REG_INT_MASK_7_WC5_LL_PA_CNT_ERROR                                                             (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_LL_PA_CNT_ERROR .
+  #define BMB_REG_INT_MASK_7_WC5_LL_PA_CNT_ERROR_SHIFT                                                       21
+  #define BMB_REG_INT_MASK_7_WC5_BB_PA_CNT_ERROR                                                             (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_BB_PA_CNT_ERROR .
+  #define BMB_REG_INT_MASK_7_WC5_BB_PA_CNT_ERROR_SHIFT                                                       22
+  #define BMB_REG_INT_MASK_7_WC6_INP_FIFO_ERROR                                                              (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_INP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC6_INP_FIFO_ERROR_SHIFT                                                        23
+  #define BMB_REG_INT_MASK_7_WC6_SOP_FIFO_ERROR                                                              (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_SOP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC6_SOP_FIFO_ERROR_SHIFT                                                        24
+  #define BMB_REG_INT_MASK_7_WC6_QUEUE_FIFO_ERROR                                                            (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_QUEUE_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC6_QUEUE_FIFO_ERROR_SHIFT                                                      25
+  #define BMB_REG_INT_MASK_7_WC6_FREE_POINT_FIFO_ERROR                                                       (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_FREE_POINT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC6_FREE_POINT_FIFO_ERROR_SHIFT                                                 26
+  #define BMB_REG_INT_MASK_7_WC6_NEXT_POINT_FIFO_ERROR                                                       (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_NEXT_POINT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC6_NEXT_POINT_FIFO_ERROR_SHIFT                                                 27
+  #define BMB_REG_INT_MASK_7_WC6_STRT_FIFO_ERROR                                                             (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_STRT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC6_STRT_FIFO_ERROR_SHIFT                                                       28
+  #define BMB_REG_INT_MASK_7_WC6_SECOND_DSCR_FIFO_ERROR                                                      (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_SECOND_DSCR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC6_SECOND_DSCR_FIFO_ERROR_SHIFT                                                29
+  #define BMB_REG_INT_MASK_7_WC6_PKT_AVAIL_FIFO_ERROR                                                        (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_PKT_AVAIL_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC6_PKT_AVAIL_FIFO_ERROR_SHIFT                                                  30
+  #define BMB_REG_INT_MASK_7_WC6_COS_CNT_FIFO_ERROR                                                          (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_COS_CNT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_7_WC6_COS_CNT_FIFO_ERROR_SHIFT                                                    31
+#define BMB_REG_INT_STS_WR_7                                                                                 0x540170UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_WR_7_WC4_FREE_POINT_FIFO_ERROR                                                     (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 4
+  #define BMB_REG_INT_STS_WR_7_WC4_FREE_POINT_FIFO_ERROR_SHIFT                                               0
+  #define BMB_REG_INT_STS_WR_7_WC4_NEXT_POINT_FIFO_ERROR                                                     (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 4
+  #define BMB_REG_INT_STS_WR_7_WC4_NEXT_POINT_FIFO_ERROR_SHIFT                                               1
+  #define BMB_REG_INT_STS_WR_7_WC4_STRT_FIFO_ERROR                                                           (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 4
+  #define BMB_REG_INT_STS_WR_7_WC4_STRT_FIFO_ERROR_SHIFT                                                     2
+  #define BMB_REG_INT_STS_WR_7_WC4_SECOND_DSCR_FIFO_ERROR                                                    (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 4
+  #define BMB_REG_INT_STS_WR_7_WC4_SECOND_DSCR_FIFO_ERROR_SHIFT                                              3
+  #define BMB_REG_INT_STS_WR_7_WC4_PKT_AVAIL_FIFO_ERROR                                                      (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 4
+  #define BMB_REG_INT_STS_WR_7_WC4_PKT_AVAIL_FIFO_ERROR_SHIFT                                                4
+  #define BMB_REG_INT_STS_WR_7_WC4_COS_CNT_FIFO_ERROR                                                        (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 4
+  #define BMB_REG_INT_STS_WR_7_WC4_COS_CNT_FIFO_ERROR_SHIFT                                                  5
+  #define BMB_REG_INT_STS_WR_7_WC4_NOTIFY_FIFO_ERROR                                                         (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 4
+  #define BMB_REG_INT_STS_WR_7_WC4_NOTIFY_FIFO_ERROR_SHIFT                                                   6
+  #define BMB_REG_INT_STS_WR_7_WC4_LL_REQ_FIFO_ERROR                                                         (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 4
+  #define BMB_REG_INT_STS_WR_7_WC4_LL_REQ_FIFO_ERROR_SHIFT                                                   7
+  #define BMB_REG_INT_STS_WR_7_WC4_LL_PA_CNT_ERROR                                                           (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 4
+  #define BMB_REG_INT_STS_WR_7_WC4_LL_PA_CNT_ERROR_SHIFT                                                     8
+  #define BMB_REG_INT_STS_WR_7_WC4_BB_PA_CNT_ERROR                                                           (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 4
+  #define BMB_REG_INT_STS_WR_7_WC4_BB_PA_CNT_ERROR_SHIFT                                                     9
+  #define BMB_REG_INT_STS_WR_7_WC5_INP_FIFO_ERROR                                                            (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 5
+  #define BMB_REG_INT_STS_WR_7_WC5_INP_FIFO_ERROR_SHIFT                                                      10
+  #define BMB_REG_INT_STS_WR_7_WC5_SOP_FIFO_ERROR                                                            (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 5
+  #define BMB_REG_INT_STS_WR_7_WC5_SOP_FIFO_ERROR_SHIFT                                                      11
+  #define BMB_REG_INT_STS_WR_7_WC5_QUEUE_FIFO_ERROR                                                          (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 5
+  #define BMB_REG_INT_STS_WR_7_WC5_QUEUE_FIFO_ERROR_SHIFT                                                    12
+  #define BMB_REG_INT_STS_WR_7_WC5_FREE_POINT_FIFO_ERROR                                                     (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 5
+  #define BMB_REG_INT_STS_WR_7_WC5_FREE_POINT_FIFO_ERROR_SHIFT                                               13
+  #define BMB_REG_INT_STS_WR_7_WC5_NEXT_POINT_FIFO_ERROR                                                     (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 5
+  #define BMB_REG_INT_STS_WR_7_WC5_NEXT_POINT_FIFO_ERROR_SHIFT                                               14
+  #define BMB_REG_INT_STS_WR_7_WC5_STRT_FIFO_ERROR                                                           (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 5
+  #define BMB_REG_INT_STS_WR_7_WC5_STRT_FIFO_ERROR_SHIFT                                                     15
+  #define BMB_REG_INT_STS_WR_7_WC5_SECOND_DSCR_FIFO_ERROR                                                    (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 5
+  #define BMB_REG_INT_STS_WR_7_WC5_SECOND_DSCR_FIFO_ERROR_SHIFT                                              16
+  #define BMB_REG_INT_STS_WR_7_WC5_PKT_AVAIL_FIFO_ERROR                                                      (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 5
+  #define BMB_REG_INT_STS_WR_7_WC5_PKT_AVAIL_FIFO_ERROR_SHIFT                                                17
+  #define BMB_REG_INT_STS_WR_7_WC5_COS_CNT_FIFO_ERROR                                                        (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 5
+  #define BMB_REG_INT_STS_WR_7_WC5_COS_CNT_FIFO_ERROR_SHIFT                                                  18
+  #define BMB_REG_INT_STS_WR_7_WC5_NOTIFY_FIFO_ERROR                                                         (0x1<<19) // Notify FIFO error in write client 5
+  #define BMB_REG_INT_STS_WR_7_WC5_NOTIFY_FIFO_ERROR_SHIFT                                                   19
+  #define BMB_REG_INT_STS_WR_7_WC5_LL_REQ_FIFO_ERROR                                                         (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 5
+  #define BMB_REG_INT_STS_WR_7_WC5_LL_REQ_FIFO_ERROR_SHIFT                                                   20
+  #define BMB_REG_INT_STS_WR_7_WC5_LL_PA_CNT_ERROR                                                           (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 5
+  #define BMB_REG_INT_STS_WR_7_WC5_LL_PA_CNT_ERROR_SHIFT                                                     21
+  #define BMB_REG_INT_STS_WR_7_WC5_BB_PA_CNT_ERROR                                                           (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 5
+  #define BMB_REG_INT_STS_WR_7_WC5_BB_PA_CNT_ERROR_SHIFT                                                     22
+  #define BMB_REG_INT_STS_WR_7_WC6_INP_FIFO_ERROR                                                            (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 6
+  #define BMB_REG_INT_STS_WR_7_WC6_INP_FIFO_ERROR_SHIFT                                                      23
+  #define BMB_REG_INT_STS_WR_7_WC6_SOP_FIFO_ERROR                                                            (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 6
+  #define BMB_REG_INT_STS_WR_7_WC6_SOP_FIFO_ERROR_SHIFT                                                      24
+  #define BMB_REG_INT_STS_WR_7_WC6_QUEUE_FIFO_ERROR                                                          (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 6
+  #define BMB_REG_INT_STS_WR_7_WC6_QUEUE_FIFO_ERROR_SHIFT                                                    25
+  #define BMB_REG_INT_STS_WR_7_WC6_FREE_POINT_FIFO_ERROR                                                     (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 6
+  #define BMB_REG_INT_STS_WR_7_WC6_FREE_POINT_FIFO_ERROR_SHIFT                                               26
+  #define BMB_REG_INT_STS_WR_7_WC6_NEXT_POINT_FIFO_ERROR                                                     (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 6
+  #define BMB_REG_INT_STS_WR_7_WC6_NEXT_POINT_FIFO_ERROR_SHIFT                                               27
+  #define BMB_REG_INT_STS_WR_7_WC6_STRT_FIFO_ERROR                                                           (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 6
+  #define BMB_REG_INT_STS_WR_7_WC6_STRT_FIFO_ERROR_SHIFT                                                     28
+  #define BMB_REG_INT_STS_WR_7_WC6_SECOND_DSCR_FIFO_ERROR                                                    (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 6
+  #define BMB_REG_INT_STS_WR_7_WC6_SECOND_DSCR_FIFO_ERROR_SHIFT                                              29
+  #define BMB_REG_INT_STS_WR_7_WC6_PKT_AVAIL_FIFO_ERROR                                                      (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 6
+  #define BMB_REG_INT_STS_WR_7_WC6_PKT_AVAIL_FIFO_ERROR_SHIFT                                                30
+  #define BMB_REG_INT_STS_WR_7_WC6_COS_CNT_FIFO_ERROR                                                        (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 6
+  #define BMB_REG_INT_STS_WR_7_WC6_COS_CNT_FIFO_ERROR_SHIFT                                                  31
+#define BMB_REG_INT_STS_CLR_7                                                                                0x540174UL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_CLR_7_WC4_FREE_POINT_FIFO_ERROR                                                    (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 4
+  #define BMB_REG_INT_STS_CLR_7_WC4_FREE_POINT_FIFO_ERROR_SHIFT                                              0
+  #define BMB_REG_INT_STS_CLR_7_WC4_NEXT_POINT_FIFO_ERROR                                                    (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 4
+  #define BMB_REG_INT_STS_CLR_7_WC4_NEXT_POINT_FIFO_ERROR_SHIFT                                              1
+  #define BMB_REG_INT_STS_CLR_7_WC4_STRT_FIFO_ERROR                                                          (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 4
+  #define BMB_REG_INT_STS_CLR_7_WC4_STRT_FIFO_ERROR_SHIFT                                                    2
+  #define BMB_REG_INT_STS_CLR_7_WC4_SECOND_DSCR_FIFO_ERROR                                                   (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 4
+  #define BMB_REG_INT_STS_CLR_7_WC4_SECOND_DSCR_FIFO_ERROR_SHIFT                                             3
+  #define BMB_REG_INT_STS_CLR_7_WC4_PKT_AVAIL_FIFO_ERROR                                                     (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 4
+  #define BMB_REG_INT_STS_CLR_7_WC4_PKT_AVAIL_FIFO_ERROR_SHIFT                                               4
+  #define BMB_REG_INT_STS_CLR_7_WC4_COS_CNT_FIFO_ERROR                                                       (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 4
+  #define BMB_REG_INT_STS_CLR_7_WC4_COS_CNT_FIFO_ERROR_SHIFT                                                 5
+  #define BMB_REG_INT_STS_CLR_7_WC4_NOTIFY_FIFO_ERROR                                                        (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 4
+  #define BMB_REG_INT_STS_CLR_7_WC4_NOTIFY_FIFO_ERROR_SHIFT                                                  6
+  #define BMB_REG_INT_STS_CLR_7_WC4_LL_REQ_FIFO_ERROR                                                        (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 4
+  #define BMB_REG_INT_STS_CLR_7_WC4_LL_REQ_FIFO_ERROR_SHIFT                                                  7
+  #define BMB_REG_INT_STS_CLR_7_WC4_LL_PA_CNT_ERROR                                                          (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 4
+  #define BMB_REG_INT_STS_CLR_7_WC4_LL_PA_CNT_ERROR_SHIFT                                                    8
+  #define BMB_REG_INT_STS_CLR_7_WC4_BB_PA_CNT_ERROR                                                          (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 4
+  #define BMB_REG_INT_STS_CLR_7_WC4_BB_PA_CNT_ERROR_SHIFT                                                    9
+  #define BMB_REG_INT_STS_CLR_7_WC5_INP_FIFO_ERROR                                                           (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 5
+  #define BMB_REG_INT_STS_CLR_7_WC5_INP_FIFO_ERROR_SHIFT                                                     10
+  #define BMB_REG_INT_STS_CLR_7_WC5_SOP_FIFO_ERROR                                                           (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 5
+  #define BMB_REG_INT_STS_CLR_7_WC5_SOP_FIFO_ERROR_SHIFT                                                     11
+  #define BMB_REG_INT_STS_CLR_7_WC5_QUEUE_FIFO_ERROR                                                         (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 5
+  #define BMB_REG_INT_STS_CLR_7_WC5_QUEUE_FIFO_ERROR_SHIFT                                                   12
+  #define BMB_REG_INT_STS_CLR_7_WC5_FREE_POINT_FIFO_ERROR                                                    (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 5
+  #define BMB_REG_INT_STS_CLR_7_WC5_FREE_POINT_FIFO_ERROR_SHIFT                                              13
+  #define BMB_REG_INT_STS_CLR_7_WC5_NEXT_POINT_FIFO_ERROR                                                    (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 5
+  #define BMB_REG_INT_STS_CLR_7_WC5_NEXT_POINT_FIFO_ERROR_SHIFT                                              14
+  #define BMB_REG_INT_STS_CLR_7_WC5_STRT_FIFO_ERROR                                                          (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 5
+  #define BMB_REG_INT_STS_CLR_7_WC5_STRT_FIFO_ERROR_SHIFT                                                    15
+  #define BMB_REG_INT_STS_CLR_7_WC5_SECOND_DSCR_FIFO_ERROR                                                   (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 5
+  #define BMB_REG_INT_STS_CLR_7_WC5_SECOND_DSCR_FIFO_ERROR_SHIFT                                             16
+  #define BMB_REG_INT_STS_CLR_7_WC5_PKT_AVAIL_FIFO_ERROR                                                     (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 5
+  #define BMB_REG_INT_STS_CLR_7_WC5_PKT_AVAIL_FIFO_ERROR_SHIFT                                               17
+  #define BMB_REG_INT_STS_CLR_7_WC5_COS_CNT_FIFO_ERROR                                                       (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 5
+  #define BMB_REG_INT_STS_CLR_7_WC5_COS_CNT_FIFO_ERROR_SHIFT                                                 18
+  #define BMB_REG_INT_STS_CLR_7_WC5_NOTIFY_FIFO_ERROR                                                        (0x1<<19) // Notify FIFO error in write client 5
+  #define BMB_REG_INT_STS_CLR_7_WC5_NOTIFY_FIFO_ERROR_SHIFT                                                  19
+  #define BMB_REG_INT_STS_CLR_7_WC5_LL_REQ_FIFO_ERROR                                                        (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 5
+  #define BMB_REG_INT_STS_CLR_7_WC5_LL_REQ_FIFO_ERROR_SHIFT                                                  20
+  #define BMB_REG_INT_STS_CLR_7_WC5_LL_PA_CNT_ERROR                                                          (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 5
+  #define BMB_REG_INT_STS_CLR_7_WC5_LL_PA_CNT_ERROR_SHIFT                                                    21
+  #define BMB_REG_INT_STS_CLR_7_WC5_BB_PA_CNT_ERROR                                                          (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 5
+  #define BMB_REG_INT_STS_CLR_7_WC5_BB_PA_CNT_ERROR_SHIFT                                                    22
+  #define BMB_REG_INT_STS_CLR_7_WC6_INP_FIFO_ERROR                                                           (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 6
+  #define BMB_REG_INT_STS_CLR_7_WC6_INP_FIFO_ERROR_SHIFT                                                     23
+  #define BMB_REG_INT_STS_CLR_7_WC6_SOP_FIFO_ERROR                                                           (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 6
+  #define BMB_REG_INT_STS_CLR_7_WC6_SOP_FIFO_ERROR_SHIFT                                                     24
+  #define BMB_REG_INT_STS_CLR_7_WC6_QUEUE_FIFO_ERROR                                                         (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 6
+  #define BMB_REG_INT_STS_CLR_7_WC6_QUEUE_FIFO_ERROR_SHIFT                                                   25
+  #define BMB_REG_INT_STS_CLR_7_WC6_FREE_POINT_FIFO_ERROR                                                    (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 6
+  #define BMB_REG_INT_STS_CLR_7_WC6_FREE_POINT_FIFO_ERROR_SHIFT                                              26
+  #define BMB_REG_INT_STS_CLR_7_WC6_NEXT_POINT_FIFO_ERROR                                                    (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 6
+  #define BMB_REG_INT_STS_CLR_7_WC6_NEXT_POINT_FIFO_ERROR_SHIFT                                              27
+  #define BMB_REG_INT_STS_CLR_7_WC6_STRT_FIFO_ERROR                                                          (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 6
+  #define BMB_REG_INT_STS_CLR_7_WC6_STRT_FIFO_ERROR_SHIFT                                                    28
+  #define BMB_REG_INT_STS_CLR_7_WC6_SECOND_DSCR_FIFO_ERROR                                                   (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 6
+  #define BMB_REG_INT_STS_CLR_7_WC6_SECOND_DSCR_FIFO_ERROR_SHIFT                                             29
+  #define BMB_REG_INT_STS_CLR_7_WC6_PKT_AVAIL_FIFO_ERROR                                                     (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 6
+  #define BMB_REG_INT_STS_CLR_7_WC6_PKT_AVAIL_FIFO_ERROR_SHIFT                                               30
+  #define BMB_REG_INT_STS_CLR_7_WC6_COS_CNT_FIFO_ERROR                                                       (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 6
+  #define BMB_REG_INT_STS_CLR_7_WC6_COS_CNT_FIFO_ERROR_SHIFT                                                 31
+#define BMB_REG_INT_STS_8                                                                                    0x540184UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_8_WC6_NOTIFY_FIFO_ERROR                                                            (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
+  #define BMB_REG_INT_STS_8_WC6_NOTIFY_FIFO_ERROR_SHIFT                                                      0
+  #define BMB_REG_INT_STS_8_WC6_LL_REQ_FIFO_ERROR                                                            (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 6
+  #define BMB_REG_INT_STS_8_WC6_LL_REQ_FIFO_ERROR_SHIFT                                                      1
+  #define BMB_REG_INT_STS_8_WC6_LL_PA_CNT_ERROR                                                              (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 6
+  #define BMB_REG_INT_STS_8_WC6_LL_PA_CNT_ERROR_SHIFT                                                        2
+  #define BMB_REG_INT_STS_8_WC6_BB_PA_CNT_ERROR                                                              (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 6
+  #define BMB_REG_INT_STS_8_WC6_BB_PA_CNT_ERROR_SHIFT                                                        3
+  #define BMB_REG_INT_STS_8_WC7_INP_FIFO_ERROR                                                               (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 7
+  #define BMB_REG_INT_STS_8_WC7_INP_FIFO_ERROR_SHIFT                                                         4
+  #define BMB_REG_INT_STS_8_WC7_SOP_FIFO_ERROR                                                               (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 7
+  #define BMB_REG_INT_STS_8_WC7_SOP_FIFO_ERROR_SHIFT                                                         5
+  #define BMB_REG_INT_STS_8_WC7_QUEUE_FIFO_ERROR                                                             (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 7
+  #define BMB_REG_INT_STS_8_WC7_QUEUE_FIFO_ERROR_SHIFT                                                       6
+  #define BMB_REG_INT_STS_8_WC7_FREE_POINT_FIFO_ERROR                                                        (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 7
+  #define BMB_REG_INT_STS_8_WC7_FREE_POINT_FIFO_ERROR_SHIFT                                                  7
+  #define BMB_REG_INT_STS_8_WC7_NEXT_POINT_FIFO_ERROR                                                        (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 7
+  #define BMB_REG_INT_STS_8_WC7_NEXT_POINT_FIFO_ERROR_SHIFT                                                  8
+  #define BMB_REG_INT_STS_8_WC7_STRT_FIFO_ERROR                                                              (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 7
+  #define BMB_REG_INT_STS_8_WC7_STRT_FIFO_ERROR_SHIFT                                                        9
+  #define BMB_REG_INT_STS_8_WC7_SECOND_DSCR_FIFO_ERROR                                                       (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 7
+  #define BMB_REG_INT_STS_8_WC7_SECOND_DSCR_FIFO_ERROR_SHIFT                                                 10
+  #define BMB_REG_INT_STS_8_WC7_PKT_AVAIL_FIFO_ERROR                                                         (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 7
+  #define BMB_REG_INT_STS_8_WC7_PKT_AVAIL_FIFO_ERROR_SHIFT                                                   11
+  #define BMB_REG_INT_STS_8_WC7_COS_CNT_FIFO_ERROR                                                           (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 7
+  #define BMB_REG_INT_STS_8_WC7_COS_CNT_FIFO_ERROR_SHIFT                                                     12
+  #define BMB_REG_INT_STS_8_WC7_NOTIFY_FIFO_ERROR                                                            (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 7
+  #define BMB_REG_INT_STS_8_WC7_NOTIFY_FIFO_ERROR_SHIFT                                                      13
+  #define BMB_REG_INT_STS_8_WC7_LL_REQ_FIFO_ERROR                                                            (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 7
+  #define BMB_REG_INT_STS_8_WC7_LL_REQ_FIFO_ERROR_SHIFT                                                      14
+  #define BMB_REG_INT_STS_8_WC7_LL_PA_CNT_ERROR                                                              (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 7
+  #define BMB_REG_INT_STS_8_WC7_LL_PA_CNT_ERROR_SHIFT                                                        15
+  #define BMB_REG_INT_STS_8_WC7_BB_PA_CNT_ERROR                                                              (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 7
+  #define BMB_REG_INT_STS_8_WC7_BB_PA_CNT_ERROR_SHIFT                                                        16
+  #define BMB_REG_INT_STS_8_WC8_INP_FIFO_ERROR                                                               (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 8
+  #define BMB_REG_INT_STS_8_WC8_INP_FIFO_ERROR_SHIFT                                                         17
+  #define BMB_REG_INT_STS_8_WC8_SOP_FIFO_ERROR                                                               (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 8
+  #define BMB_REG_INT_STS_8_WC8_SOP_FIFO_ERROR_SHIFT                                                         18
+  #define BMB_REG_INT_STS_8_WC8_QUEUE_FIFO_ERROR                                                             (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 8
+  #define BMB_REG_INT_STS_8_WC8_QUEUE_FIFO_ERROR_SHIFT                                                       19
+  #define BMB_REG_INT_STS_8_WC8_FREE_POINT_FIFO_ERROR                                                        (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 8
+  #define BMB_REG_INT_STS_8_WC8_FREE_POINT_FIFO_ERROR_SHIFT                                                  20
+  #define BMB_REG_INT_STS_8_WC8_NEXT_POINT_FIFO_ERROR                                                        (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 8
+  #define BMB_REG_INT_STS_8_WC8_NEXT_POINT_FIFO_ERROR_SHIFT                                                  21
+  #define BMB_REG_INT_STS_8_WC8_STRT_FIFO_ERROR                                                              (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 8
+  #define BMB_REG_INT_STS_8_WC8_STRT_FIFO_ERROR_SHIFT                                                        22
+  #define BMB_REG_INT_STS_8_WC8_SECOND_DSCR_FIFO_ERROR                                                       (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 8
+  #define BMB_REG_INT_STS_8_WC8_SECOND_DSCR_FIFO_ERROR_SHIFT                                                 23
+  #define BMB_REG_INT_STS_8_WC8_PKT_AVAIL_FIFO_ERROR                                                         (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 8
+  #define BMB_REG_INT_STS_8_WC8_PKT_AVAIL_FIFO_ERROR_SHIFT                                                   24
+  #define BMB_REG_INT_STS_8_WC8_COS_CNT_FIFO_ERROR                                                           (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 8
+  #define BMB_REG_INT_STS_8_WC8_COS_CNT_FIFO_ERROR_SHIFT                                                     25
+  #define BMB_REG_INT_STS_8_WC8_NOTIFY_FIFO_ERROR                                                            (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 8
+  #define BMB_REG_INT_STS_8_WC8_NOTIFY_FIFO_ERROR_SHIFT                                                      26
+  #define BMB_REG_INT_STS_8_WC8_LL_REQ_FIFO_ERROR                                                            (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 8
+  #define BMB_REG_INT_STS_8_WC8_LL_REQ_FIFO_ERROR_SHIFT                                                      27
+  #define BMB_REG_INT_STS_8_WC8_LL_PA_CNT_ERROR                                                              (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 8
+  #define BMB_REG_INT_STS_8_WC8_LL_PA_CNT_ERROR_SHIFT                                                        28
+  #define BMB_REG_INT_STS_8_WC8_BB_PA_CNT_ERROR                                                              (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 8
+  #define BMB_REG_INT_STS_8_WC8_BB_PA_CNT_ERROR_SHIFT                                                        29
+  #define BMB_REG_INT_STS_8_WC9_INP_FIFO_ERROR                                                               (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 9
+  #define BMB_REG_INT_STS_8_WC9_INP_FIFO_ERROR_SHIFT                                                         30
+  #define BMB_REG_INT_STS_8_WC9_SOP_FIFO_ERROR                                                               (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 9
+  #define BMB_REG_INT_STS_8_WC9_SOP_FIFO_ERROR_SHIFT                                                         31
+#define BMB_REG_INT_MASK_8                                                                                   0x540188UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_MASK_8_WC6_NOTIFY_FIFO_ERROR                                                           (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC6_NOTIFY_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC6_NOTIFY_FIFO_ERROR_SHIFT                                                     0
+  #define BMB_REG_INT_MASK_8_WC6_LL_REQ_FIFO_ERROR                                                           (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC6_LL_REQ_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC6_LL_REQ_FIFO_ERROR_SHIFT                                                     1
+  #define BMB_REG_INT_MASK_8_WC6_LL_PA_CNT_ERROR                                                             (0x1<<2) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC6_LL_PA_CNT_ERROR .
+  #define BMB_REG_INT_MASK_8_WC6_LL_PA_CNT_ERROR_SHIFT                                                       2
+  #define BMB_REG_INT_MASK_8_WC6_BB_PA_CNT_ERROR                                                             (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC6_BB_PA_CNT_ERROR .
+  #define BMB_REG_INT_MASK_8_WC6_BB_PA_CNT_ERROR_SHIFT                                                       3
+  #define BMB_REG_INT_MASK_8_WC7_INP_FIFO_ERROR                                                              (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_INP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC7_INP_FIFO_ERROR_SHIFT                                                        4
+  #define BMB_REG_INT_MASK_8_WC7_SOP_FIFO_ERROR                                                              (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_SOP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC7_SOP_FIFO_ERROR_SHIFT                                                        5
+  #define BMB_REG_INT_MASK_8_WC7_QUEUE_FIFO_ERROR                                                            (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_QUEUE_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC7_QUEUE_FIFO_ERROR_SHIFT                                                      6
+  #define BMB_REG_INT_MASK_8_WC7_FREE_POINT_FIFO_ERROR                                                       (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_FREE_POINT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC7_FREE_POINT_FIFO_ERROR_SHIFT                                                 7
+  #define BMB_REG_INT_MASK_8_WC7_NEXT_POINT_FIFO_ERROR                                                       (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_NEXT_POINT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC7_NEXT_POINT_FIFO_ERROR_SHIFT                                                 8
+  #define BMB_REG_INT_MASK_8_WC7_STRT_FIFO_ERROR                                                             (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_STRT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC7_STRT_FIFO_ERROR_SHIFT                                                       9
+  #define BMB_REG_INT_MASK_8_WC7_SECOND_DSCR_FIFO_ERROR                                                      (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_SECOND_DSCR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC7_SECOND_DSCR_FIFO_ERROR_SHIFT                                                10
+  #define BMB_REG_INT_MASK_8_WC7_PKT_AVAIL_FIFO_ERROR                                                        (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_PKT_AVAIL_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC7_PKT_AVAIL_FIFO_ERROR_SHIFT                                                  11
+  #define BMB_REG_INT_MASK_8_WC7_COS_CNT_FIFO_ERROR                                                          (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_COS_CNT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC7_COS_CNT_FIFO_ERROR_SHIFT                                                    12
+  #define BMB_REG_INT_MASK_8_WC7_NOTIFY_FIFO_ERROR                                                           (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_NOTIFY_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC7_NOTIFY_FIFO_ERROR_SHIFT                                                     13
+  #define BMB_REG_INT_MASK_8_WC7_LL_REQ_FIFO_ERROR                                                           (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_LL_REQ_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC7_LL_REQ_FIFO_ERROR_SHIFT                                                     14
+  #define BMB_REG_INT_MASK_8_WC7_LL_PA_CNT_ERROR                                                             (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_LL_PA_CNT_ERROR .
+  #define BMB_REG_INT_MASK_8_WC7_LL_PA_CNT_ERROR_SHIFT                                                       15
+  #define BMB_REG_INT_MASK_8_WC7_BB_PA_CNT_ERROR                                                             (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_BB_PA_CNT_ERROR .
+  #define BMB_REG_INT_MASK_8_WC7_BB_PA_CNT_ERROR_SHIFT                                                       16
+  #define BMB_REG_INT_MASK_8_WC8_INP_FIFO_ERROR                                                              (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_INP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC8_INP_FIFO_ERROR_SHIFT                                                        17
+  #define BMB_REG_INT_MASK_8_WC8_SOP_FIFO_ERROR                                                              (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_SOP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC8_SOP_FIFO_ERROR_SHIFT                                                        18
+  #define BMB_REG_INT_MASK_8_WC8_QUEUE_FIFO_ERROR                                                            (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_QUEUE_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC8_QUEUE_FIFO_ERROR_SHIFT                                                      19
+  #define BMB_REG_INT_MASK_8_WC8_FREE_POINT_FIFO_ERROR                                                       (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_FREE_POINT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC8_FREE_POINT_FIFO_ERROR_SHIFT                                                 20
+  #define BMB_REG_INT_MASK_8_WC8_NEXT_POINT_FIFO_ERROR                                                       (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_NEXT_POINT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC8_NEXT_POINT_FIFO_ERROR_SHIFT                                                 21
+  #define BMB_REG_INT_MASK_8_WC8_STRT_FIFO_ERROR                                                             (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_STRT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC8_STRT_FIFO_ERROR_SHIFT                                                       22
+  #define BMB_REG_INT_MASK_8_WC8_SECOND_DSCR_FIFO_ERROR                                                      (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_SECOND_DSCR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC8_SECOND_DSCR_FIFO_ERROR_SHIFT                                                23
+  #define BMB_REG_INT_MASK_8_WC8_PKT_AVAIL_FIFO_ERROR                                                        (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_PKT_AVAIL_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC8_PKT_AVAIL_FIFO_ERROR_SHIFT                                                  24
+  #define BMB_REG_INT_MASK_8_WC8_COS_CNT_FIFO_ERROR                                                          (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_COS_CNT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC8_COS_CNT_FIFO_ERROR_SHIFT                                                    25
+  #define BMB_REG_INT_MASK_8_WC8_NOTIFY_FIFO_ERROR                                                           (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_NOTIFY_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC8_NOTIFY_FIFO_ERROR_SHIFT                                                     26
+  #define BMB_REG_INT_MASK_8_WC8_LL_REQ_FIFO_ERROR                                                           (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_LL_REQ_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC8_LL_REQ_FIFO_ERROR_SHIFT                                                     27
+  #define BMB_REG_INT_MASK_8_WC8_LL_PA_CNT_ERROR                                                             (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_LL_PA_CNT_ERROR .
+  #define BMB_REG_INT_MASK_8_WC8_LL_PA_CNT_ERROR_SHIFT                                                       28
+  #define BMB_REG_INT_MASK_8_WC8_BB_PA_CNT_ERROR                                                             (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_BB_PA_CNT_ERROR .
+  #define BMB_REG_INT_MASK_8_WC8_BB_PA_CNT_ERROR_SHIFT                                                       29
+  #define BMB_REG_INT_MASK_8_WC9_INP_FIFO_ERROR                                                              (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC9_INP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC9_INP_FIFO_ERROR_SHIFT                                                        30
+  #define BMB_REG_INT_MASK_8_WC9_SOP_FIFO_ERROR                                                              (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC9_SOP_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_8_WC9_SOP_FIFO_ERROR_SHIFT                                                        31
+#define BMB_REG_INT_STS_WR_8                                                                                 0x54018cUL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_WR_8_WC6_NOTIFY_FIFO_ERROR                                                         (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
+  #define BMB_REG_INT_STS_WR_8_WC6_NOTIFY_FIFO_ERROR_SHIFT                                                   0
+  #define BMB_REG_INT_STS_WR_8_WC6_LL_REQ_FIFO_ERROR                                                         (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 6
+  #define BMB_REG_INT_STS_WR_8_WC6_LL_REQ_FIFO_ERROR_SHIFT                                                   1
+  #define BMB_REG_INT_STS_WR_8_WC6_LL_PA_CNT_ERROR                                                           (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 6
+  #define BMB_REG_INT_STS_WR_8_WC6_LL_PA_CNT_ERROR_SHIFT                                                     2
+  #define BMB_REG_INT_STS_WR_8_WC6_BB_PA_CNT_ERROR                                                           (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 6
+  #define BMB_REG_INT_STS_WR_8_WC6_BB_PA_CNT_ERROR_SHIFT                                                     3
+  #define BMB_REG_INT_STS_WR_8_WC7_INP_FIFO_ERROR                                                            (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 7
+  #define BMB_REG_INT_STS_WR_8_WC7_INP_FIFO_ERROR_SHIFT                                                      4
+  #define BMB_REG_INT_STS_WR_8_WC7_SOP_FIFO_ERROR                                                            (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 7
+  #define BMB_REG_INT_STS_WR_8_WC7_SOP_FIFO_ERROR_SHIFT                                                      5
+  #define BMB_REG_INT_STS_WR_8_WC7_QUEUE_FIFO_ERROR                                                          (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 7
+  #define BMB_REG_INT_STS_WR_8_WC7_QUEUE_FIFO_ERROR_SHIFT                                                    6
+  #define BMB_REG_INT_STS_WR_8_WC7_FREE_POINT_FIFO_ERROR                                                     (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 7
+  #define BMB_REG_INT_STS_WR_8_WC7_FREE_POINT_FIFO_ERROR_SHIFT                                               7
+  #define BMB_REG_INT_STS_WR_8_WC7_NEXT_POINT_FIFO_ERROR                                                     (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 7
+  #define BMB_REG_INT_STS_WR_8_WC7_NEXT_POINT_FIFO_ERROR_SHIFT                                               8
+  #define BMB_REG_INT_STS_WR_8_WC7_STRT_FIFO_ERROR                                                           (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 7
+  #define BMB_REG_INT_STS_WR_8_WC7_STRT_FIFO_ERROR_SHIFT                                                     9
+  #define BMB_REG_INT_STS_WR_8_WC7_SECOND_DSCR_FIFO_ERROR                                                    (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 7
+  #define BMB_REG_INT_STS_WR_8_WC7_SECOND_DSCR_FIFO_ERROR_SHIFT                                              10
+  #define BMB_REG_INT_STS_WR_8_WC7_PKT_AVAIL_FIFO_ERROR                                                      (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 7
+  #define BMB_REG_INT_STS_WR_8_WC7_PKT_AVAIL_FIFO_ERROR_SHIFT                                                11
+  #define BMB_REG_INT_STS_WR_8_WC7_COS_CNT_FIFO_ERROR                                                        (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 7
+  #define BMB_REG_INT_STS_WR_8_WC7_COS_CNT_FIFO_ERROR_SHIFT                                                  12
+  #define BMB_REG_INT_STS_WR_8_WC7_NOTIFY_FIFO_ERROR                                                         (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 7
+  #define BMB_REG_INT_STS_WR_8_WC7_NOTIFY_FIFO_ERROR_SHIFT                                                   13
+  #define BMB_REG_INT_STS_WR_8_WC7_LL_REQ_FIFO_ERROR                                                         (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 7
+  #define BMB_REG_INT_STS_WR_8_WC7_LL_REQ_FIFO_ERROR_SHIFT                                                   14
+  #define BMB_REG_INT_STS_WR_8_WC7_LL_PA_CNT_ERROR                                                           (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 7
+  #define BMB_REG_INT_STS_WR_8_WC7_LL_PA_CNT_ERROR_SHIFT                                                     15
+  #define BMB_REG_INT_STS_WR_8_WC7_BB_PA_CNT_ERROR                                                           (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 7
+  #define BMB_REG_INT_STS_WR_8_WC7_BB_PA_CNT_ERROR_SHIFT                                                     16
+  #define BMB_REG_INT_STS_WR_8_WC8_INP_FIFO_ERROR                                                            (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 8
+  #define BMB_REG_INT_STS_WR_8_WC8_INP_FIFO_ERROR_SHIFT                                                      17
+  #define BMB_REG_INT_STS_WR_8_WC8_SOP_FIFO_ERROR                                                            (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 8
+  #define BMB_REG_INT_STS_WR_8_WC8_SOP_FIFO_ERROR_SHIFT                                                      18
+  #define BMB_REG_INT_STS_WR_8_WC8_QUEUE_FIFO_ERROR                                                          (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 8
+  #define BMB_REG_INT_STS_WR_8_WC8_QUEUE_FIFO_ERROR_SHIFT                                                    19
+  #define BMB_REG_INT_STS_WR_8_WC8_FREE_POINT_FIFO_ERROR                                                     (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 8
+  #define BMB_REG_INT_STS_WR_8_WC8_FREE_POINT_FIFO_ERROR_SHIFT                                               20
+  #define BMB_REG_INT_STS_WR_8_WC8_NEXT_POINT_FIFO_ERROR                                                     (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 8
+  #define BMB_REG_INT_STS_WR_8_WC8_NEXT_POINT_FIFO_ERROR_SHIFT                                               21
+  #define BMB_REG_INT_STS_WR_8_WC8_STRT_FIFO_ERROR                                                           (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 8
+  #define BMB_REG_INT_STS_WR_8_WC8_STRT_FIFO_ERROR_SHIFT                                                     22
+  #define BMB_REG_INT_STS_WR_8_WC8_SECOND_DSCR_FIFO_ERROR                                                    (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 8
+  #define BMB_REG_INT_STS_WR_8_WC8_SECOND_DSCR_FIFO_ERROR_SHIFT                                              23
+  #define BMB_REG_INT_STS_WR_8_WC8_PKT_AVAIL_FIFO_ERROR                                                      (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 8
+  #define BMB_REG_INT_STS_WR_8_WC8_PKT_AVAIL_FIFO_ERROR_SHIFT                                                24
+  #define BMB_REG_INT_STS_WR_8_WC8_COS_CNT_FIFO_ERROR                                                        (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 8
+  #define BMB_REG_INT_STS_WR_8_WC8_COS_CNT_FIFO_ERROR_SHIFT                                                  25
+  #define BMB_REG_INT_STS_WR_8_WC8_NOTIFY_FIFO_ERROR                                                         (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 8
+  #define BMB_REG_INT_STS_WR_8_WC8_NOTIFY_FIFO_ERROR_SHIFT                                                   26
+  #define BMB_REG_INT_STS_WR_8_WC8_LL_REQ_FIFO_ERROR                                                         (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 8
+  #define BMB_REG_INT_STS_WR_8_WC8_LL_REQ_FIFO_ERROR_SHIFT                                                   27
+  #define BMB_REG_INT_STS_WR_8_WC8_LL_PA_CNT_ERROR                                                           (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 8
+  #define BMB_REG_INT_STS_WR_8_WC8_LL_PA_CNT_ERROR_SHIFT                                                     28
+  #define BMB_REG_INT_STS_WR_8_WC8_BB_PA_CNT_ERROR                                                           (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 8
+  #define BMB_REG_INT_STS_WR_8_WC8_BB_PA_CNT_ERROR_SHIFT                                                     29
+  #define BMB_REG_INT_STS_WR_8_WC9_INP_FIFO_ERROR                                                            (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 9
+  #define BMB_REG_INT_STS_WR_8_WC9_INP_FIFO_ERROR_SHIFT                                                      30
+  #define BMB_REG_INT_STS_WR_8_WC9_SOP_FIFO_ERROR                                                            (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 9
+  #define BMB_REG_INT_STS_WR_8_WC9_SOP_FIFO_ERROR_SHIFT                                                      31
+#define BMB_REG_INT_STS_CLR_8                                                                                0x540190UL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_CLR_8_WC6_NOTIFY_FIFO_ERROR                                                        (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
+  #define BMB_REG_INT_STS_CLR_8_WC6_NOTIFY_FIFO_ERROR_SHIFT                                                  0
+  #define BMB_REG_INT_STS_CLR_8_WC6_LL_REQ_FIFO_ERROR                                                        (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 6
+  #define BMB_REG_INT_STS_CLR_8_WC6_LL_REQ_FIFO_ERROR_SHIFT                                                  1
+  #define BMB_REG_INT_STS_CLR_8_WC6_LL_PA_CNT_ERROR                                                          (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 6
+  #define BMB_REG_INT_STS_CLR_8_WC6_LL_PA_CNT_ERROR_SHIFT                                                    2
+  #define BMB_REG_INT_STS_CLR_8_WC6_BB_PA_CNT_ERROR                                                          (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 6
+  #define BMB_REG_INT_STS_CLR_8_WC6_BB_PA_CNT_ERROR_SHIFT                                                    3
+  #define BMB_REG_INT_STS_CLR_8_WC7_INP_FIFO_ERROR                                                           (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 7
+  #define BMB_REG_INT_STS_CLR_8_WC7_INP_FIFO_ERROR_SHIFT                                                     4
+  #define BMB_REG_INT_STS_CLR_8_WC7_SOP_FIFO_ERROR                                                           (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 7
+  #define BMB_REG_INT_STS_CLR_8_WC7_SOP_FIFO_ERROR_SHIFT                                                     5
+  #define BMB_REG_INT_STS_CLR_8_WC7_QUEUE_FIFO_ERROR                                                         (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 7
+  #define BMB_REG_INT_STS_CLR_8_WC7_QUEUE_FIFO_ERROR_SHIFT                                                   6
+  #define BMB_REG_INT_STS_CLR_8_WC7_FREE_POINT_FIFO_ERROR                                                    (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 7
+  #define BMB_REG_INT_STS_CLR_8_WC7_FREE_POINT_FIFO_ERROR_SHIFT                                              7
+  #define BMB_REG_INT_STS_CLR_8_WC7_NEXT_POINT_FIFO_ERROR                                                    (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 7
+  #define BMB_REG_INT_STS_CLR_8_WC7_NEXT_POINT_FIFO_ERROR_SHIFT                                              8
+  #define BMB_REG_INT_STS_CLR_8_WC7_STRT_FIFO_ERROR                                                          (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 7
+  #define BMB_REG_INT_STS_CLR_8_WC7_STRT_FIFO_ERROR_SHIFT                                                    9
+  #define BMB_REG_INT_STS_CLR_8_WC7_SECOND_DSCR_FIFO_ERROR                                                   (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 7
+  #define BMB_REG_INT_STS_CLR_8_WC7_SECOND_DSCR_FIFO_ERROR_SHIFT                                             10
+  #define BMB_REG_INT_STS_CLR_8_WC7_PKT_AVAIL_FIFO_ERROR                                                     (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 7
+  #define BMB_REG_INT_STS_CLR_8_WC7_PKT_AVAIL_FIFO_ERROR_SHIFT                                               11
+  #define BMB_REG_INT_STS_CLR_8_WC7_COS_CNT_FIFO_ERROR                                                       (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 7
+  #define BMB_REG_INT_STS_CLR_8_WC7_COS_CNT_FIFO_ERROR_SHIFT                                                 12
+  #define BMB_REG_INT_STS_CLR_8_WC7_NOTIFY_FIFO_ERROR                                                        (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 7
+  #define BMB_REG_INT_STS_CLR_8_WC7_NOTIFY_FIFO_ERROR_SHIFT                                                  13
+  #define BMB_REG_INT_STS_CLR_8_WC7_LL_REQ_FIFO_ERROR                                                        (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 7
+  #define BMB_REG_INT_STS_CLR_8_WC7_LL_REQ_FIFO_ERROR_SHIFT                                                  14
+  #define BMB_REG_INT_STS_CLR_8_WC7_LL_PA_CNT_ERROR                                                          (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 7
+  #define BMB_REG_INT_STS_CLR_8_WC7_LL_PA_CNT_ERROR_SHIFT                                                    15
+  #define BMB_REG_INT_STS_CLR_8_WC7_BB_PA_CNT_ERROR                                                          (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 7
+  #define BMB_REG_INT_STS_CLR_8_WC7_BB_PA_CNT_ERROR_SHIFT                                                    16
+  #define BMB_REG_INT_STS_CLR_8_WC8_INP_FIFO_ERROR                                                           (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 8
+  #define BMB_REG_INT_STS_CLR_8_WC8_INP_FIFO_ERROR_SHIFT                                                     17
+  #define BMB_REG_INT_STS_CLR_8_WC8_SOP_FIFO_ERROR                                                           (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 8
+  #define BMB_REG_INT_STS_CLR_8_WC8_SOP_FIFO_ERROR_SHIFT                                                     18
+  #define BMB_REG_INT_STS_CLR_8_WC8_QUEUE_FIFO_ERROR                                                         (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 8
+  #define BMB_REG_INT_STS_CLR_8_WC8_QUEUE_FIFO_ERROR_SHIFT                                                   19
+  #define BMB_REG_INT_STS_CLR_8_WC8_FREE_POINT_FIFO_ERROR                                                    (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 8
+  #define BMB_REG_INT_STS_CLR_8_WC8_FREE_POINT_FIFO_ERROR_SHIFT                                              20
+  #define BMB_REG_INT_STS_CLR_8_WC8_NEXT_POINT_FIFO_ERROR                                                    (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 8
+  #define BMB_REG_INT_STS_CLR_8_WC8_NEXT_POINT_FIFO_ERROR_SHIFT                                              21
+  #define BMB_REG_INT_STS_CLR_8_WC8_STRT_FIFO_ERROR                                                          (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 8
+  #define BMB_REG_INT_STS_CLR_8_WC8_STRT_FIFO_ERROR_SHIFT                                                    22
+  #define BMB_REG_INT_STS_CLR_8_WC8_SECOND_DSCR_FIFO_ERROR                                                   (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 8
+  #define BMB_REG_INT_STS_CLR_8_WC8_SECOND_DSCR_FIFO_ERROR_SHIFT                                             23
+  #define BMB_REG_INT_STS_CLR_8_WC8_PKT_AVAIL_FIFO_ERROR                                                     (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 8
+  #define BMB_REG_INT_STS_CLR_8_WC8_PKT_AVAIL_FIFO_ERROR_SHIFT                                               24
+  #define BMB_REG_INT_STS_CLR_8_WC8_COS_CNT_FIFO_ERROR                                                       (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 8
+  #define BMB_REG_INT_STS_CLR_8_WC8_COS_CNT_FIFO_ERROR_SHIFT                                                 25
+  #define BMB_REG_INT_STS_CLR_8_WC8_NOTIFY_FIFO_ERROR                                                        (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 8
+  #define BMB_REG_INT_STS_CLR_8_WC8_NOTIFY_FIFO_ERROR_SHIFT                                                  26
+  #define BMB_REG_INT_STS_CLR_8_WC8_LL_REQ_FIFO_ERROR                                                        (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 8
+  #define BMB_REG_INT_STS_CLR_8_WC8_LL_REQ_FIFO_ERROR_SHIFT                                                  27
+  #define BMB_REG_INT_STS_CLR_8_WC8_LL_PA_CNT_ERROR                                                          (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 8
+  #define BMB_REG_INT_STS_CLR_8_WC8_LL_PA_CNT_ERROR_SHIFT                                                    28
+  #define BMB_REG_INT_STS_CLR_8_WC8_BB_PA_CNT_ERROR                                                          (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 8
+  #define BMB_REG_INT_STS_CLR_8_WC8_BB_PA_CNT_ERROR_SHIFT                                                    29
+  #define BMB_REG_INT_STS_CLR_8_WC9_INP_FIFO_ERROR                                                           (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 9
+  #define BMB_REG_INT_STS_CLR_8_WC9_INP_FIFO_ERROR_SHIFT                                                     30
+  #define BMB_REG_INT_STS_CLR_8_WC9_SOP_FIFO_ERROR                                                           (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 9
+  #define BMB_REG_INT_STS_CLR_8_WC9_SOP_FIFO_ERROR_SHIFT                                                     31
+#define BMB_REG_INT_STS_9                                                                                    0x54019cUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_9_WC9_QUEUE_FIFO_ERROR                                                             (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
+  #define BMB_REG_INT_STS_9_WC9_QUEUE_FIFO_ERROR_SHIFT                                                       0
+  #define BMB_REG_INT_STS_9_WC9_FREE_POINT_FIFO_ERROR                                                        (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 9
+  #define BMB_REG_INT_STS_9_WC9_FREE_POINT_FIFO_ERROR_SHIFT                                                  1
+  #define BMB_REG_INT_STS_9_WC9_NEXT_POINT_FIFO_ERROR                                                        (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 9
+  #define BMB_REG_INT_STS_9_WC9_NEXT_POINT_FIFO_ERROR_SHIFT                                                  2
+  #define BMB_REG_INT_STS_9_WC9_STRT_FIFO_ERROR                                                              (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 9
+  #define BMB_REG_INT_STS_9_WC9_STRT_FIFO_ERROR_SHIFT                                                        3
+  #define BMB_REG_INT_STS_9_WC9_SECOND_DSCR_FIFO_ERROR                                                       (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 9
+  #define BMB_REG_INT_STS_9_WC9_SECOND_DSCR_FIFO_ERROR_SHIFT                                                 4
+  #define BMB_REG_INT_STS_9_WC9_PKT_AVAIL_FIFO_ERROR                                                         (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 9
+  #define BMB_REG_INT_STS_9_WC9_PKT_AVAIL_FIFO_ERROR_SHIFT                                                   5
+  #define BMB_REG_INT_STS_9_WC9_COS_CNT_FIFO_ERROR                                                           (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 9
+  #define BMB_REG_INT_STS_9_WC9_COS_CNT_FIFO_ERROR_SHIFT                                                     6
+  #define BMB_REG_INT_STS_9_WC9_NOTIFY_FIFO_ERROR                                                            (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 9
+  #define BMB_REG_INT_STS_9_WC9_NOTIFY_FIFO_ERROR_SHIFT                                                      7
+  #define BMB_REG_INT_STS_9_WC9_LL_REQ_FIFO_ERROR                                                            (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 9
+  #define BMB_REG_INT_STS_9_WC9_LL_REQ_FIFO_ERROR_SHIFT                                                      8
+  #define BMB_REG_INT_STS_9_WC9_LL_PA_CNT_ERROR                                                              (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 9
+  #define BMB_REG_INT_STS_9_WC9_LL_PA_CNT_ERROR_SHIFT                                                        9
+  #define BMB_REG_INT_STS_9_WC9_BB_PA_CNT_ERROR                                                              (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 9
+  #define BMB_REG_INT_STS_9_WC9_BB_PA_CNT_ERROR_SHIFT                                                        10
+  #define BMB_REG_INT_STS_9_RC2_SOP_RC_OUT_SYNC_FIFO_ERROR_E5                                                (0x1<<11) // SOP DSCR SYNC FIFO error for RC2
+  #define BMB_REG_INT_STS_9_RC2_SOP_RC_OUT_SYNC_FIFO_ERROR_E5_SHIFT                                          11
+  #define BMB_REG_INT_STS_9_RC2_SOP_OUT_SYNC_FIFO_PUSH_ERROR_E5                                              (0x1<<12) // SOP output SYNC FIFO error for RC2
+  #define BMB_REG_INT_STS_9_RC2_SOP_OUT_SYNC_FIFO_PUSH_ERROR_E5_SHIFT                                        12
+  #define BMB_REG_INT_STS_9_RC0_SOP_PEND_FIFO_ERROR                                                          (0x1<<13) // SOP pending FIFO error for RC0
+  #define BMB_REG_INT_STS_9_RC0_SOP_PEND_FIFO_ERROR_SHIFT                                                    13
+  #define BMB_REG_INT_STS_9_RC1_SOP_PEND_FIFO_ERROR                                                          (0x1<<14) // SOP pending FIFO error for RC01
+  #define BMB_REG_INT_STS_9_RC1_SOP_PEND_FIFO_ERROR_SHIFT                                                    14
+  #define BMB_REG_INT_STS_9_RC2_SOP_PEND_FIFO_ERROR                                                          (0x1<<15) // SOP pending FIFO error for RC2
+  #define BMB_REG_INT_STS_9_RC2_SOP_PEND_FIFO_ERROR_SHIFT                                                    15
+  #define BMB_REG_INT_STS_9_RC3_SOP_PEND_FIFO_ERROR                                                          (0x1<<16) // SOP pending FIFO error for RC3
+  #define BMB_REG_INT_STS_9_RC3_SOP_PEND_FIFO_ERROR_SHIFT                                                    16
+  #define BMB_REG_INT_STS_9_RC4_SOP_PEND_FIFO_ERROR                                                          (0x1<<17) // SOP pending FIFO error for RC4
+  #define BMB_REG_INT_STS_9_RC4_SOP_PEND_FIFO_ERROR_SHIFT                                                    17
+  #define BMB_REG_INT_STS_9_RC5_SOP_PEND_FIFO_ERROR                                                          (0x1<<18) // SOP pending FIFO error for RC05
+  #define BMB_REG_INT_STS_9_RC5_SOP_PEND_FIFO_ERROR_SHIFT                                                    18
+  #define BMB_REG_INT_STS_9_RC6_SOP_PEND_FIFO_ERROR                                                          (0x1<<19) // SOP pending FIFO error for RC6
+  #define BMB_REG_INT_STS_9_RC6_SOP_PEND_FIFO_ERROR_SHIFT                                                    19
+  #define BMB_REG_INT_STS_9_RC7_SOP_PEND_FIFO_ERROR                                                          (0x1<<20) // SOP pending FIFO error for RC7
+  #define BMB_REG_INT_STS_9_RC7_SOP_PEND_FIFO_ERROR_SHIFT                                                    20
+  #define BMB_REG_INT_STS_9_RC0_DSCR_PEND_FIFO_ERROR                                                         (0x1<<21) // SOP descriptor FIFO error for RC0
+  #define BMB_REG_INT_STS_9_RC0_DSCR_PEND_FIFO_ERROR_SHIFT                                                   21
+  #define BMB_REG_INT_STS_9_RC1_DSCR_PEND_FIFO_ERROR                                                         (0x1<<22) // SOP descriptor FIFO error for RC1
+  #define BMB_REG_INT_STS_9_RC1_DSCR_PEND_FIFO_ERROR_SHIFT                                                   22
+  #define BMB_REG_INT_STS_9_RC2_DSCR_PEND_FIFO_ERROR                                                         (0x1<<23) // SOP descriptor FIFO error for RC02
+  #define BMB_REG_INT_STS_9_RC2_DSCR_PEND_FIFO_ERROR_SHIFT                                                   23
+  #define BMB_REG_INT_STS_9_RC3_DSCR_PEND_FIFO_ERROR                                                         (0x1<<24) // SOP descriptor FIFO error for RC3
+  #define BMB_REG_INT_STS_9_RC3_DSCR_PEND_FIFO_ERROR_SHIFT                                                   24
+  #define BMB_REG_INT_STS_9_RC4_DSCR_PEND_FIFO_ERROR                                                         (0x1<<25) // SOP descriptor FIFO error for RC4
+  #define BMB_REG_INT_STS_9_RC4_DSCR_PEND_FIFO_ERROR_SHIFT                                                   25
+  #define BMB_REG_INT_STS_9_RC5_DSCR_PEND_FIFO_ERROR                                                         (0x1<<26) // SOP descriptor FIFO error for RC5
+  #define BMB_REG_INT_STS_9_RC5_DSCR_PEND_FIFO_ERROR_SHIFT                                                   26
+  #define BMB_REG_INT_STS_9_RC6_DSCR_PEND_FIFO_ERROR                                                         (0x1<<27) // SOP descriptor FIFO error for RC6
+  #define BMB_REG_INT_STS_9_RC6_DSCR_PEND_FIFO_ERROR_SHIFT                                                   27
+  #define BMB_REG_INT_STS_9_RC7_DSCR_PEND_FIFO_ERROR                                                         (0x1<<28) // SOP descriptor FIFO error for RC7
+  #define BMB_REG_INT_STS_9_RC7_DSCR_PEND_FIFO_ERROR_SHIFT                                                   28
+  #define BMB_REG_INT_STS_9_RC1_SOP_INP_SYNC_FIFO_PUSH_ERROR_E5                                              (0x1<<29) // SOP input SYNC FIFO error for RC1
+  #define BMB_REG_INT_STS_9_RC1_SOP_INP_SYNC_FIFO_PUSH_ERROR_E5_SHIFT                                        29
+  #define BMB_REG_INT_STS_9_RC2_SOP_INP_SYNC_FIFO_PUSH_ERROR_E5                                              (0x1<<30) // SOP input SYNC FIFO error for RC2
+  #define BMB_REG_INT_STS_9_RC2_SOP_INP_SYNC_FIFO_PUSH_ERROR_E5_SHIFT                                        30
+  #define BMB_REG_INT_STS_9_RC1_SOP_OUT_SYNC_FIFO_PUSH_ERROR_E5                                              (0x1<<31) // SOP output SYNC FIFO error for RC1
+  #define BMB_REG_INT_STS_9_RC1_SOP_OUT_SYNC_FIFO_PUSH_ERROR_E5_SHIFT                                        31
+  #define BMB_REG_INT_STS_9_RC9_SOP_RC_OUT_SYNC_FIFO_ERROR_BB_K2                                             (0x1<<11) // SOP DSCR SYNC FIFO error for RC9
+  #define BMB_REG_INT_STS_9_RC9_SOP_RC_OUT_SYNC_FIFO_ERROR_BB_K2_SHIFT                                       11
+  #define BMB_REG_INT_STS_9_RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2                                           (0x1<<12) // SOP output SYNC FIFO error for RC8
+  #define BMB_REG_INT_STS_9_RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT                                     12
+  #define BMB_REG_INT_STS_9_RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR_BB_K2                                           (0x1<<29) // SOP input SYNC FIFO error for RC8
+  #define BMB_REG_INT_STS_9_RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT                                     29
+  #define BMB_REG_INT_STS_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR_BB_K2                                           (0x1<<30) // SOP input SYNC FIFO error for RC9
+  #define BMB_REG_INT_STS_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT                                     30
+  #define BMB_REG_INT_STS_9_RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2                                           (0x1<<31) // SOP output SYNC FIFO error for RC8
+  #define BMB_REG_INT_STS_9_RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT                                     31
+#define BMB_REG_INT_MASK_9                                                                                   0x5401a0UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_MASK_9_WC9_QUEUE_FIFO_ERROR                                                            (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_QUEUE_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_WC9_QUEUE_FIFO_ERROR_SHIFT                                                      0
+  #define BMB_REG_INT_MASK_9_WC9_FREE_POINT_FIFO_ERROR                                                       (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_FREE_POINT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_WC9_FREE_POINT_FIFO_ERROR_SHIFT                                                 1
+  #define BMB_REG_INT_MASK_9_WC9_NEXT_POINT_FIFO_ERROR                                                       (0x1<<2) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_NEXT_POINT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_WC9_NEXT_POINT_FIFO_ERROR_SHIFT                                                 2
+  #define BMB_REG_INT_MASK_9_WC9_STRT_FIFO_ERROR                                                             (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_STRT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_WC9_STRT_FIFO_ERROR_SHIFT                                                       3
+  #define BMB_REG_INT_MASK_9_WC9_SECOND_DSCR_FIFO_ERROR                                                      (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_SECOND_DSCR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_WC9_SECOND_DSCR_FIFO_ERROR_SHIFT                                                4
+  #define BMB_REG_INT_MASK_9_WC9_PKT_AVAIL_FIFO_ERROR                                                        (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_PKT_AVAIL_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_WC9_PKT_AVAIL_FIFO_ERROR_SHIFT                                                  5
+  #define BMB_REG_INT_MASK_9_WC9_COS_CNT_FIFO_ERROR                                                          (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_COS_CNT_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_WC9_COS_CNT_FIFO_ERROR_SHIFT                                                    6
+  #define BMB_REG_INT_MASK_9_WC9_NOTIFY_FIFO_ERROR                                                           (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_NOTIFY_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_WC9_NOTIFY_FIFO_ERROR_SHIFT                                                     7
+  #define BMB_REG_INT_MASK_9_WC9_LL_REQ_FIFO_ERROR                                                           (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_LL_REQ_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_WC9_LL_REQ_FIFO_ERROR_SHIFT                                                     8
+  #define BMB_REG_INT_MASK_9_WC9_LL_PA_CNT_ERROR                                                             (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_LL_PA_CNT_ERROR .
+  #define BMB_REG_INT_MASK_9_WC9_LL_PA_CNT_ERROR_SHIFT                                                       9
+  #define BMB_REG_INT_MASK_9_WC9_BB_PA_CNT_ERROR                                                             (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_BB_PA_CNT_ERROR .
+  #define BMB_REG_INT_MASK_9_WC9_BB_PA_CNT_ERROR_SHIFT                                                       10
+  #define BMB_REG_INT_MASK_9_RC2_SOP_RC_OUT_SYNC_FIFO_ERROR_E5                                               (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC2_SOP_RC_OUT_SYNC_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_RC2_SOP_RC_OUT_SYNC_FIFO_ERROR_E5_SHIFT                                         11
+  #define BMB_REG_INT_MASK_9_RC2_SOP_OUT_SYNC_FIFO_PUSH_ERROR_E5                                             (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC2_SOP_OUT_SYNC_FIFO_PUSH_ERROR .
+  #define BMB_REG_INT_MASK_9_RC2_SOP_OUT_SYNC_FIFO_PUSH_ERROR_E5_SHIFT                                       12
+  #define BMB_REG_INT_MASK_9_RC0_SOP_PEND_FIFO_ERROR                                                         (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC0_SOP_PEND_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_RC0_SOP_PEND_FIFO_ERROR_SHIFT                                                   13
+  #define BMB_REG_INT_MASK_9_RC1_SOP_PEND_FIFO_ERROR                                                         (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC1_SOP_PEND_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_RC1_SOP_PEND_FIFO_ERROR_SHIFT                                                   14
+  #define BMB_REG_INT_MASK_9_RC2_SOP_PEND_FIFO_ERROR                                                         (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC2_SOP_PEND_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_RC2_SOP_PEND_FIFO_ERROR_SHIFT                                                   15
+  #define BMB_REG_INT_MASK_9_RC3_SOP_PEND_FIFO_ERROR                                                         (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC3_SOP_PEND_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_RC3_SOP_PEND_FIFO_ERROR_SHIFT                                                   16
+  #define BMB_REG_INT_MASK_9_RC4_SOP_PEND_FIFO_ERROR                                                         (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC4_SOP_PEND_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_RC4_SOP_PEND_FIFO_ERROR_SHIFT                                                   17
+  #define BMB_REG_INT_MASK_9_RC5_SOP_PEND_FIFO_ERROR                                                         (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC5_SOP_PEND_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_RC5_SOP_PEND_FIFO_ERROR_SHIFT                                                   18
+  #define BMB_REG_INT_MASK_9_RC6_SOP_PEND_FIFO_ERROR                                                         (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC6_SOP_PEND_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_RC6_SOP_PEND_FIFO_ERROR_SHIFT                                                   19
+  #define BMB_REG_INT_MASK_9_RC7_SOP_PEND_FIFO_ERROR                                                         (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC7_SOP_PEND_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_RC7_SOP_PEND_FIFO_ERROR_SHIFT                                                   20
+  #define BMB_REG_INT_MASK_9_RC0_DSCR_PEND_FIFO_ERROR                                                        (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC0_DSCR_PEND_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_RC0_DSCR_PEND_FIFO_ERROR_SHIFT                                                  21
+  #define BMB_REG_INT_MASK_9_RC1_DSCR_PEND_FIFO_ERROR                                                        (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC1_DSCR_PEND_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_RC1_DSCR_PEND_FIFO_ERROR_SHIFT                                                  22
+  #define BMB_REG_INT_MASK_9_RC2_DSCR_PEND_FIFO_ERROR                                                        (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC2_DSCR_PEND_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_RC2_DSCR_PEND_FIFO_ERROR_SHIFT                                                  23
+  #define BMB_REG_INT_MASK_9_RC3_DSCR_PEND_FIFO_ERROR                                                        (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC3_DSCR_PEND_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_RC3_DSCR_PEND_FIFO_ERROR_SHIFT                                                  24
+  #define BMB_REG_INT_MASK_9_RC4_DSCR_PEND_FIFO_ERROR                                                        (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC4_DSCR_PEND_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_RC4_DSCR_PEND_FIFO_ERROR_SHIFT                                                  25
+  #define BMB_REG_INT_MASK_9_RC5_DSCR_PEND_FIFO_ERROR                                                        (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC5_DSCR_PEND_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_RC5_DSCR_PEND_FIFO_ERROR_SHIFT                                                  26
+  #define BMB_REG_INT_MASK_9_RC6_DSCR_PEND_FIFO_ERROR                                                        (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC6_DSCR_PEND_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_RC6_DSCR_PEND_FIFO_ERROR_SHIFT                                                  27
+  #define BMB_REG_INT_MASK_9_RC7_DSCR_PEND_FIFO_ERROR                                                        (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC7_DSCR_PEND_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_RC7_DSCR_PEND_FIFO_ERROR_SHIFT                                                  28
+  #define BMB_REG_INT_MASK_9_RC1_SOP_INP_SYNC_FIFO_PUSH_ERROR_E5                                             (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC1_SOP_INP_SYNC_FIFO_PUSH_ERROR .
+  #define BMB_REG_INT_MASK_9_RC1_SOP_INP_SYNC_FIFO_PUSH_ERROR_E5_SHIFT                                       29
+  #define BMB_REG_INT_MASK_9_RC2_SOP_INP_SYNC_FIFO_PUSH_ERROR_E5                                             (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC2_SOP_INP_SYNC_FIFO_PUSH_ERROR .
+  #define BMB_REG_INT_MASK_9_RC2_SOP_INP_SYNC_FIFO_PUSH_ERROR_E5_SHIFT                                       30
+  #define BMB_REG_INT_MASK_9_RC1_SOP_OUT_SYNC_FIFO_PUSH_ERROR_E5                                             (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC1_SOP_OUT_SYNC_FIFO_PUSH_ERROR .
+  #define BMB_REG_INT_MASK_9_RC1_SOP_OUT_SYNC_FIFO_PUSH_ERROR_E5_SHIFT                                       31
+  #define BMB_REG_INT_MASK_9_RC9_SOP_RC_OUT_SYNC_FIFO_ERROR_BB_K2                                            (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC9_SOP_RC_OUT_SYNC_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_9_RC9_SOP_RC_OUT_SYNC_FIFO_ERROR_BB_K2_SHIFT                                      11
+  #define BMB_REG_INT_MASK_9_RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2                                          (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR .
+  #define BMB_REG_INT_MASK_9_RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT                                    12
+  #define BMB_REG_INT_MASK_9_RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR_BB_K2                                          (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR .
+  #define BMB_REG_INT_MASK_9_RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT                                    29
+  #define BMB_REG_INT_MASK_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR_BB_K2                                          (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR .
+  #define BMB_REG_INT_MASK_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT                                    30
+  #define BMB_REG_INT_MASK_9_RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2                                          (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR .
+  #define BMB_REG_INT_MASK_9_RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT                                    31
+#define BMB_REG_INT_STS_WR_9                                                                                 0x5401a4UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_WR_9_WC9_QUEUE_FIFO_ERROR                                                          (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
+  #define BMB_REG_INT_STS_WR_9_WC9_QUEUE_FIFO_ERROR_SHIFT                                                    0
+  #define BMB_REG_INT_STS_WR_9_WC9_FREE_POINT_FIFO_ERROR                                                     (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 9
+  #define BMB_REG_INT_STS_WR_9_WC9_FREE_POINT_FIFO_ERROR_SHIFT                                               1
+  #define BMB_REG_INT_STS_WR_9_WC9_NEXT_POINT_FIFO_ERROR                                                     (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 9
+  #define BMB_REG_INT_STS_WR_9_WC9_NEXT_POINT_FIFO_ERROR_SHIFT                                               2
+  #define BMB_REG_INT_STS_WR_9_WC9_STRT_FIFO_ERROR                                                           (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 9
+  #define BMB_REG_INT_STS_WR_9_WC9_STRT_FIFO_ERROR_SHIFT                                                     3
+  #define BMB_REG_INT_STS_WR_9_WC9_SECOND_DSCR_FIFO_ERROR                                                    (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 9
+  #define BMB_REG_INT_STS_WR_9_WC9_SECOND_DSCR_FIFO_ERROR_SHIFT                                              4
+  #define BMB_REG_INT_STS_WR_9_WC9_PKT_AVAIL_FIFO_ERROR                                                      (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 9
+  #define BMB_REG_INT_STS_WR_9_WC9_PKT_AVAIL_FIFO_ERROR_SHIFT                                                5
+  #define BMB_REG_INT_STS_WR_9_WC9_COS_CNT_FIFO_ERROR                                                        (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 9
+  #define BMB_REG_INT_STS_WR_9_WC9_COS_CNT_FIFO_ERROR_SHIFT                                                  6
+  #define BMB_REG_INT_STS_WR_9_WC9_NOTIFY_FIFO_ERROR                                                         (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 9
+  #define BMB_REG_INT_STS_WR_9_WC9_NOTIFY_FIFO_ERROR_SHIFT                                                   7
+  #define BMB_REG_INT_STS_WR_9_WC9_LL_REQ_FIFO_ERROR                                                         (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 9
+  #define BMB_REG_INT_STS_WR_9_WC9_LL_REQ_FIFO_ERROR_SHIFT                                                   8
+  #define BMB_REG_INT_STS_WR_9_WC9_LL_PA_CNT_ERROR                                                           (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 9
+  #define BMB_REG_INT_STS_WR_9_WC9_LL_PA_CNT_ERROR_SHIFT                                                     9
+  #define BMB_REG_INT_STS_WR_9_WC9_BB_PA_CNT_ERROR                                                           (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 9
+  #define BMB_REG_INT_STS_WR_9_WC9_BB_PA_CNT_ERROR_SHIFT                                                     10
+  #define BMB_REG_INT_STS_WR_9_RC2_SOP_RC_OUT_SYNC_FIFO_ERROR_E5                                             (0x1<<11) // SOP DSCR SYNC FIFO error for RC2
+  #define BMB_REG_INT_STS_WR_9_RC2_SOP_RC_OUT_SYNC_FIFO_ERROR_E5_SHIFT                                       11
+  #define BMB_REG_INT_STS_WR_9_RC2_SOP_OUT_SYNC_FIFO_PUSH_ERROR_E5                                           (0x1<<12) // SOP output SYNC FIFO error for RC2
+  #define BMB_REG_INT_STS_WR_9_RC2_SOP_OUT_SYNC_FIFO_PUSH_ERROR_E5_SHIFT                                     12
+  #define BMB_REG_INT_STS_WR_9_RC0_SOP_PEND_FIFO_ERROR                                                       (0x1<<13) // SOP pending FIFO error for RC0
+  #define BMB_REG_INT_STS_WR_9_RC0_SOP_PEND_FIFO_ERROR_SHIFT                                                 13
+  #define BMB_REG_INT_STS_WR_9_RC1_SOP_PEND_FIFO_ERROR                                                       (0x1<<14) // SOP pending FIFO error for RC01
+  #define BMB_REG_INT_STS_WR_9_RC1_SOP_PEND_FIFO_ERROR_SHIFT                                                 14
+  #define BMB_REG_INT_STS_WR_9_RC2_SOP_PEND_FIFO_ERROR                                                       (0x1<<15) // SOP pending FIFO error for RC2
+  #define BMB_REG_INT_STS_WR_9_RC2_SOP_PEND_FIFO_ERROR_SHIFT                                                 15
+  #define BMB_REG_INT_STS_WR_9_RC3_SOP_PEND_FIFO_ERROR                                                       (0x1<<16) // SOP pending FIFO error for RC3
+  #define BMB_REG_INT_STS_WR_9_RC3_SOP_PEND_FIFO_ERROR_SHIFT                                                 16
+  #define BMB_REG_INT_STS_WR_9_RC4_SOP_PEND_FIFO_ERROR                                                       (0x1<<17) // SOP pending FIFO error for RC4
+  #define BMB_REG_INT_STS_WR_9_RC4_SOP_PEND_FIFO_ERROR_SHIFT                                                 17
+  #define BMB_REG_INT_STS_WR_9_RC5_SOP_PEND_FIFO_ERROR                                                       (0x1<<18) // SOP pending FIFO error for RC05
+  #define BMB_REG_INT_STS_WR_9_RC5_SOP_PEND_FIFO_ERROR_SHIFT                                                 18
+  #define BMB_REG_INT_STS_WR_9_RC6_SOP_PEND_FIFO_ERROR                                                       (0x1<<19) // SOP pending FIFO error for RC6
+  #define BMB_REG_INT_STS_WR_9_RC6_SOP_PEND_FIFO_ERROR_SHIFT                                                 19
+  #define BMB_REG_INT_STS_WR_9_RC7_SOP_PEND_FIFO_ERROR                                                       (0x1<<20) // SOP pending FIFO error for RC7
+  #define BMB_REG_INT_STS_WR_9_RC7_SOP_PEND_FIFO_ERROR_SHIFT                                                 20
+  #define BMB_REG_INT_STS_WR_9_RC0_DSCR_PEND_FIFO_ERROR                                                      (0x1<<21) // SOP descriptor FIFO error for RC0
+  #define BMB_REG_INT_STS_WR_9_RC0_DSCR_PEND_FIFO_ERROR_SHIFT                                                21
+  #define BMB_REG_INT_STS_WR_9_RC1_DSCR_PEND_FIFO_ERROR                                                      (0x1<<22) // SOP descriptor FIFO error for RC1
+  #define BMB_REG_INT_STS_WR_9_RC1_DSCR_PEND_FIFO_ERROR_SHIFT                                                22
+  #define BMB_REG_INT_STS_WR_9_RC2_DSCR_PEND_FIFO_ERROR                                                      (0x1<<23) // SOP descriptor FIFO error for RC02
+  #define BMB_REG_INT_STS_WR_9_RC2_DSCR_PEND_FIFO_ERROR_SHIFT                                                23
+  #define BMB_REG_INT_STS_WR_9_RC3_DSCR_PEND_FIFO_ERROR                                                      (0x1<<24) // SOP descriptor FIFO error for RC3
+  #define BMB_REG_INT_STS_WR_9_RC3_DSCR_PEND_FIFO_ERROR_SHIFT                                                24
+  #define BMB_REG_INT_STS_WR_9_RC4_DSCR_PEND_FIFO_ERROR                                                      (0x1<<25) // SOP descriptor FIFO error for RC4
+  #define BMB_REG_INT_STS_WR_9_RC4_DSCR_PEND_FIFO_ERROR_SHIFT                                                25
+  #define BMB_REG_INT_STS_WR_9_RC5_DSCR_PEND_FIFO_ERROR                                                      (0x1<<26) // SOP descriptor FIFO error for RC5
+  #define BMB_REG_INT_STS_WR_9_RC5_DSCR_PEND_FIFO_ERROR_SHIFT                                                26
+  #define BMB_REG_INT_STS_WR_9_RC6_DSCR_PEND_FIFO_ERROR                                                      (0x1<<27) // SOP descriptor FIFO error for RC6
+  #define BMB_REG_INT_STS_WR_9_RC6_DSCR_PEND_FIFO_ERROR_SHIFT                                                27
+  #define BMB_REG_INT_STS_WR_9_RC7_DSCR_PEND_FIFO_ERROR                                                      (0x1<<28) // SOP descriptor FIFO error for RC7
+  #define BMB_REG_INT_STS_WR_9_RC7_DSCR_PEND_FIFO_ERROR_SHIFT                                                28
+  #define BMB_REG_INT_STS_WR_9_RC1_SOP_INP_SYNC_FIFO_PUSH_ERROR_E5                                           (0x1<<29) // SOP input SYNC FIFO error for RC1
+  #define BMB_REG_INT_STS_WR_9_RC1_SOP_INP_SYNC_FIFO_PUSH_ERROR_E5_SHIFT                                     29
+  #define BMB_REG_INT_STS_WR_9_RC2_SOP_INP_SYNC_FIFO_PUSH_ERROR_E5                                           (0x1<<30) // SOP input SYNC FIFO error for RC2
+  #define BMB_REG_INT_STS_WR_9_RC2_SOP_INP_SYNC_FIFO_PUSH_ERROR_E5_SHIFT                                     30
+  #define BMB_REG_INT_STS_WR_9_RC1_SOP_OUT_SYNC_FIFO_PUSH_ERROR_E5                                           (0x1<<31) // SOP output SYNC FIFO error for RC1
+  #define BMB_REG_INT_STS_WR_9_RC1_SOP_OUT_SYNC_FIFO_PUSH_ERROR_E5_SHIFT                                     31
+  #define BMB_REG_INT_STS_WR_9_RC9_SOP_RC_OUT_SYNC_FIFO_ERROR_BB_K2                                          (0x1<<11) // SOP DSCR SYNC FIFO error for RC9
+  #define BMB_REG_INT_STS_WR_9_RC9_SOP_RC_OUT_SYNC_FIFO_ERROR_BB_K2_SHIFT                                    11
+  #define BMB_REG_INT_STS_WR_9_RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2                                        (0x1<<12) // SOP output SYNC FIFO error for RC8
+  #define BMB_REG_INT_STS_WR_9_RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT                                  12
+  #define BMB_REG_INT_STS_WR_9_RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR_BB_K2                                        (0x1<<29) // SOP input SYNC FIFO error for RC8
+  #define BMB_REG_INT_STS_WR_9_RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT                                  29
+  #define BMB_REG_INT_STS_WR_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR_BB_K2                                        (0x1<<30) // SOP input SYNC FIFO error for RC9
+  #define BMB_REG_INT_STS_WR_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT                                  30
+  #define BMB_REG_INT_STS_WR_9_RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2                                        (0x1<<31) // SOP output SYNC FIFO error for RC8
+  #define BMB_REG_INT_STS_WR_9_RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT                                  31
+#define BMB_REG_INT_STS_CLR_9                                                                                0x5401a8UL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define BMB_REG_INT_STS_CLR_9_WC9_QUEUE_FIFO_ERROR                                                         (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
+  #define BMB_REG_INT_STS_CLR_9_WC9_QUEUE_FIFO_ERROR_SHIFT                                                   0
+  #define BMB_REG_INT_STS_CLR_9_WC9_FREE_POINT_FIFO_ERROR                                                    (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 9
+  #define BMB_REG_INT_STS_CLR_9_WC9_FREE_POINT_FIFO_ERROR_SHIFT                                              1
+  #define BMB_REG_INT_STS_CLR_9_WC9_NEXT_POINT_FIFO_ERROR                                                    (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 9
+  #define BMB_REG_INT_STS_CLR_9_WC9_NEXT_POINT_FIFO_ERROR_SHIFT                                              2
+  #define BMB_REG_INT_STS_CLR_9_WC9_STRT_FIFO_ERROR                                                          (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 9
+  #define BMB_REG_INT_STS_CLR_9_WC9_STRT_FIFO_ERROR_SHIFT                                                    3
+  #define BMB_REG_INT_STS_CLR_9_WC9_SECOND_DSCR_FIFO_ERROR                                                   (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 9
+  #define BMB_REG_INT_STS_CLR_9_WC9_SECOND_DSCR_FIFO_ERROR_SHIFT                                             4
+  #define BMB_REG_INT_STS_CLR_9_WC9_PKT_AVAIL_FIFO_ERROR                                                     (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 9
+  #define BMB_REG_INT_STS_CLR_9_WC9_PKT_AVAIL_FIFO_ERROR_SHIFT                                               5
+  #define BMB_REG_INT_STS_CLR_9_WC9_COS_CNT_FIFO_ERROR                                                       (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 9
+  #define BMB_REG_INT_STS_CLR_9_WC9_COS_CNT_FIFO_ERROR_SHIFT                                                 6
+  #define BMB_REG_INT_STS_CLR_9_WC9_NOTIFY_FIFO_ERROR                                                        (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 9
+  #define BMB_REG_INT_STS_CLR_9_WC9_NOTIFY_FIFO_ERROR_SHIFT                                                  7
+  #define BMB_REG_INT_STS_CLR_9_WC9_LL_REQ_FIFO_ERROR                                                        (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 9
+  #define BMB_REG_INT_STS_CLR_9_WC9_LL_REQ_FIFO_ERROR_SHIFT                                                  8
+  #define BMB_REG_INT_STS_CLR_9_WC9_LL_PA_CNT_ERROR                                                          (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 9
+  #define BMB_REG_INT_STS_CLR_9_WC9_LL_PA_CNT_ERROR_SHIFT                                                    9
+  #define BMB_REG_INT_STS_CLR_9_WC9_BB_PA_CNT_ERROR                                                          (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 9
+  #define BMB_REG_INT_STS_CLR_9_WC9_BB_PA_CNT_ERROR_SHIFT                                                    10
+  #define BMB_REG_INT_STS_CLR_9_RC2_SOP_RC_OUT_SYNC_FIFO_ERROR_E5                                            (0x1<<11) // SOP DSCR SYNC FIFO error for RC2
+  #define BMB_REG_INT_STS_CLR_9_RC2_SOP_RC_OUT_SYNC_FIFO_ERROR_E5_SHIFT                                      11
+  #define BMB_REG_INT_STS_CLR_9_RC2_SOP_OUT_SYNC_FIFO_PUSH_ERROR_E5                                          (0x1<<12) // SOP output SYNC FIFO error for RC2
+  #define BMB_REG_INT_STS_CLR_9_RC2_SOP_OUT_SYNC_FIFO_PUSH_ERROR_E5_SHIFT                                    12
+  #define BMB_REG_INT_STS_CLR_9_RC0_SOP_PEND_FIFO_ERROR                                                      (0x1<<13) // SOP pending FIFO error for RC0
+  #define BMB_REG_INT_STS_CLR_9_RC0_SOP_PEND_FIFO_ERROR_SHIFT                                                13
+  #define BMB_REG_INT_STS_CLR_9_RC1_SOP_PEND_FIFO_ERROR                                                      (0x1<<14) // SOP pending FIFO error for RC01
+  #define BMB_REG_INT_STS_CLR_9_RC1_SOP_PEND_FIFO_ERROR_SHIFT                                                14
+  #define BMB_REG_INT_STS_CLR_9_RC2_SOP_PEND_FIFO_ERROR                                                      (0x1<<15) // SOP pending FIFO error for RC2
+  #define BMB_REG_INT_STS_CLR_9_RC2_SOP_PEND_FIFO_ERROR_SHIFT                                                15
+  #define BMB_REG_INT_STS_CLR_9_RC3_SOP_PEND_FIFO_ERROR                                                      (0x1<<16) // SOP pending FIFO error for RC3
+  #define BMB_REG_INT_STS_CLR_9_RC3_SOP_PEND_FIFO_ERROR_SHIFT                                                16
+  #define BMB_REG_INT_STS_CLR_9_RC4_SOP_PEND_FIFO_ERROR                                                      (0x1<<17) // SOP pending FIFO error for RC4
+  #define BMB_REG_INT_STS_CLR_9_RC4_SOP_PEND_FIFO_ERROR_SHIFT                                                17
+  #define BMB_REG_INT_STS_CLR_9_RC5_SOP_PEND_FIFO_ERROR                                                      (0x1<<18) // SOP pending FIFO error for RC05
+  #define BMB_REG_INT_STS_CLR_9_RC5_SOP_PEND_FIFO_ERROR_SHIFT                                                18
+  #define BMB_REG_INT_STS_CLR_9_RC6_SOP_PEND_FIFO_ERROR                                                      (0x1<<19) // SOP pending FIFO error for RC6
+  #define BMB_REG_INT_STS_CLR_9_RC6_SOP_PEND_FIFO_ERROR_SHIFT                                                19
+  #define BMB_REG_INT_STS_CLR_9_RC7_SOP_PEND_FIFO_ERROR                                                      (0x1<<20) // SOP pending FIFO error for RC7
+  #define BMB_REG_INT_STS_CLR_9_RC7_SOP_PEND_FIFO_ERROR_SHIFT                                                20
+  #define BMB_REG_INT_STS_CLR_9_RC0_DSCR_PEND_FIFO_ERROR                                                     (0x1<<21) // SOP descriptor FIFO error for RC0
+  #define BMB_REG_INT_STS_CLR_9_RC0_DSCR_PEND_FIFO_ERROR_SHIFT                                               21
+  #define BMB_REG_INT_STS_CLR_9_RC1_DSCR_PEND_FIFO_ERROR                                                     (0x1<<22) // SOP descriptor FIFO error for RC1
+  #define BMB_REG_INT_STS_CLR_9_RC1_DSCR_PEND_FIFO_ERROR_SHIFT                                               22
+  #define BMB_REG_INT_STS_CLR_9_RC2_DSCR_PEND_FIFO_ERROR                                                     (0x1<<23) // SOP descriptor FIFO error for RC02
+  #define BMB_REG_INT_STS_CLR_9_RC2_DSCR_PEND_FIFO_ERROR_SHIFT                                               23
+  #define BMB_REG_INT_STS_CLR_9_RC3_DSCR_PEND_FIFO_ERROR                                                     (0x1<<24) // SOP descriptor FIFO error for RC3
+  #define BMB_REG_INT_STS_CLR_9_RC3_DSCR_PEND_FIFO_ERROR_SHIFT                                               24
+  #define BMB_REG_INT_STS_CLR_9_RC4_DSCR_PEND_FIFO_ERROR                                                     (0x1<<25) // SOP descriptor FIFO error for RC4
+  #define BMB_REG_INT_STS_CLR_9_RC4_DSCR_PEND_FIFO_ERROR_SHIFT                                               25
+  #define BMB_REG_INT_STS_CLR_9_RC5_DSCR_PEND_FIFO_ERROR                                                     (0x1<<26) // SOP descriptor FIFO error for RC5
+  #define BMB_REG_INT_STS_CLR_9_RC5_DSCR_PEND_FIFO_ERROR_SHIFT                                               26
+  #define BMB_REG_INT_STS_CLR_9_RC6_DSCR_PEND_FIFO_ERROR                                                     (0x1<<27) // SOP descriptor FIFO error for RC6
+  #define BMB_REG_INT_STS_CLR_9_RC6_DSCR_PEND_FIFO_ERROR_SHIFT                                               27
+  #define BMB_REG_INT_STS_CLR_9_RC7_DSCR_PEND_FIFO_ERROR                                                     (0x1<<28) // SOP descriptor FIFO error for RC7
+  #define BMB_REG_INT_STS_CLR_9_RC7_DSCR_PEND_FIFO_ERROR_SHIFT                                               28
+  #define BMB_REG_INT_STS_CLR_9_RC1_SOP_INP_SYNC_FIFO_PUSH_ERROR_E5                                          (0x1<<29) // SOP input SYNC FIFO error for RC1
+  #define BMB_REG_INT_STS_CLR_9_RC1_SOP_INP_SYNC_FIFO_PUSH_ERROR_E5_SHIFT                                    29
+  #define BMB_REG_INT_STS_CLR_9_RC2_SOP_INP_SYNC_FIFO_PUSH_ERROR_E5                                          (0x1<<30) // SOP input SYNC FIFO error for RC2
+  #define BMB_REG_INT_STS_CLR_9_RC2_SOP_INP_SYNC_FIFO_PUSH_ERROR_E5_SHIFT                                    30
+  #define BMB_REG_INT_STS_CLR_9_RC1_SOP_OUT_SYNC_FIFO_PUSH_ERROR_E5                                          (0x1<<31) // SOP output SYNC FIFO error for RC1
+  #define BMB_REG_INT_STS_CLR_9_RC1_SOP_OUT_SYNC_FIFO_PUSH_ERROR_E5_SHIFT                                    31
+  #define BMB_REG_INT_STS_CLR_9_RC9_SOP_RC_OUT_SYNC_FIFO_ERROR_BB_K2                                         (0x1<<11) // SOP DSCR SYNC FIFO error for RC9
+  #define BMB_REG_INT_STS_CLR_9_RC9_SOP_RC_OUT_SYNC_FIFO_ERROR_BB_K2_SHIFT                                   11
+  #define BMB_REG_INT_STS_CLR_9_RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2                                       (0x1<<12) // SOP output SYNC FIFO error for RC8
+  #define BMB_REG_INT_STS_CLR_9_RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT                                 12
+  #define BMB_REG_INT_STS_CLR_9_RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR_BB_K2                                       (0x1<<29) // SOP input SYNC FIFO error for RC8
+  #define BMB_REG_INT_STS_CLR_9_RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT                                 29
+  #define BMB_REG_INT_STS_CLR_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR_BB_K2                                       (0x1<<30) // SOP input SYNC FIFO error for RC9
+  #define BMB_REG_INT_STS_CLR_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT                                 30
+  #define BMB_REG_INT_STS_CLR_9_RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2                                       (0x1<<31) // SOP output SYNC FIFO error for RC8
+  #define BMB_REG_INT_STS_CLR_9_RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT                                 31
+#define BMB_REG_INT_STS_10                                                                                   0x5401b4UL //Access:R    DataWidth:0xf    // Multi Field Register.
+  #define BMB_REG_INT_STS_10_RC_GNT_PEND_FIFO_ERROR                                                          (0x1<<0) // 
+  #define BMB_REG_INT_STS_10_RC_GNT_PEND_FIFO_ERROR_SHIFT                                                    0
+  #define BMB_REG_INT_STS_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR_E5                                                 (0x1<<13) // Packet RC output SYNC FIFO error
+  #define BMB_REG_INT_STS_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR_E5_SHIFT                                           13
+  #define BMB_REG_INT_STS_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR_E5                                                 (0x1<<14) // Packet RC output SYNC FIFO error
+  #define BMB_REG_INT_STS_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR_E5_SHIFT                                           14
+  #define BMB_REG_INT_STS_10_RC8_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2                                              (0x1<<20) // Packet RC output SYNC FIFO error
+  #define BMB_REG_INT_STS_10_RC8_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT                                        20
+  #define BMB_REG_INT_STS_10_RC9_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2                                              (0x1<<21) // Packet RC output SYNC FIFO error
+  #define BMB_REG_INT_STS_10_RC9_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT                                        21
+#define BMB_REG_INT_MASK_10                                                                                  0x5401b8UL //Access:RW   DataWidth:0xf    // Multi Field Register.
+  #define BMB_REG_INT_MASK_10_RC_GNT_PEND_FIFO_ERROR                                                         (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_10.RC_GNT_PEND_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_10_RC_GNT_PEND_FIFO_ERROR_SHIFT                                                   0
+  #define BMB_REG_INT_MASK_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR_E5                                                (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_10.RC1_OUT_SYNC_FIFO_PUSH_ERROR .
+  #define BMB_REG_INT_MASK_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR_E5_SHIFT                                          13
+  #define BMB_REG_INT_MASK_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR_E5                                                (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_10.RC2_OUT_SYNC_FIFO_PUSH_ERROR .
+  #define BMB_REG_INT_MASK_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR_E5_SHIFT                                          14
+  #define BMB_REG_INT_MASK_10_RC8_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2                                             (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_10.RC8_OUT_SYNC_FIFO_PUSH_ERROR .
+  #define BMB_REG_INT_MASK_10_RC8_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT                                       20
+  #define BMB_REG_INT_MASK_10_RC9_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2                                             (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_10.RC9_OUT_SYNC_FIFO_PUSH_ERROR .
+  #define BMB_REG_INT_MASK_10_RC9_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT                                       21
+#define BMB_REG_INT_STS_WR_10                                                                                0x5401bcUL //Access:WR   DataWidth:0xf    // Multi Field Register.
+  #define BMB_REG_INT_STS_WR_10_RC_GNT_PEND_FIFO_ERROR                                                       (0x1<<0) // 
+  #define BMB_REG_INT_STS_WR_10_RC_GNT_PEND_FIFO_ERROR_SHIFT                                                 0
+  #define BMB_REG_INT_STS_WR_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR_E5                                              (0x1<<13) // Packet RC output SYNC FIFO error
+  #define BMB_REG_INT_STS_WR_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR_E5_SHIFT                                        13
+  #define BMB_REG_INT_STS_WR_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR_E5                                              (0x1<<14) // Packet RC output SYNC FIFO error
+  #define BMB_REG_INT_STS_WR_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR_E5_SHIFT                                        14
+  #define BMB_REG_INT_STS_WR_10_RC8_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2                                           (0x1<<20) // Packet RC output SYNC FIFO error
+  #define BMB_REG_INT_STS_WR_10_RC8_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT                                     20
+  #define BMB_REG_INT_STS_WR_10_RC9_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2                                           (0x1<<21) // Packet RC output SYNC FIFO error
+  #define BMB_REG_INT_STS_WR_10_RC9_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT                                     21
+#define BMB_REG_INT_STS_CLR_10                                                                               0x5401c0UL //Access:RC   DataWidth:0xf    // Multi Field Register.
+  #define BMB_REG_INT_STS_CLR_10_RC_GNT_PEND_FIFO_ERROR                                                      (0x1<<0) // 
+  #define BMB_REG_INT_STS_CLR_10_RC_GNT_PEND_FIFO_ERROR_SHIFT                                                0
+  #define BMB_REG_INT_STS_CLR_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR_E5                                             (0x1<<13) // Packet RC output SYNC FIFO error
+  #define BMB_REG_INT_STS_CLR_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR_E5_SHIFT                                       13
+  #define BMB_REG_INT_STS_CLR_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR_E5                                             (0x1<<14) // Packet RC output SYNC FIFO error
+  #define BMB_REG_INT_STS_CLR_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR_E5_SHIFT                                       14
+  #define BMB_REG_INT_STS_CLR_10_RC8_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2                                          (0x1<<20) // Packet RC output SYNC FIFO error
+  #define BMB_REG_INT_STS_CLR_10_RC8_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT                                    20
+  #define BMB_REG_INT_STS_CLR_10_RC9_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2                                          (0x1<<21) // Packet RC output SYNC FIFO error
+  #define BMB_REG_INT_STS_CLR_10_RC9_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT                                    21
+#define BMB_REG_INT_STS_11                                                                                   0x5401ccUL //Access:R    DataWidth:0x13   // Multi Field Register.
+  #define BMB_REG_INT_STS_11_WC8_SYNC_FIFO_PUSH_ERROR                                                        (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. WC input SYNC FIFO error
+  #define BMB_REG_INT_STS_11_WC8_SYNC_FIFO_PUSH_ERROR_SHIFT                                                  6
+  #define BMB_REG_INT_STS_11_WC9_SYNC_FIFO_PUSH_ERROR                                                        (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. WC input SYNC FIFO error
+  #define BMB_REG_INT_STS_11_WC9_SYNC_FIFO_PUSH_ERROR_SHIFT                                                  7
+  #define BMB_REG_INT_STS_11_RC1_SOP_RC_OUT_SYNC_FIFO_ERROR_E5                                               (0x1<<9) // SOP DSCR SYNC FIFO error for RC1
+  #define BMB_REG_INT_STS_11_RC1_SOP_RC_OUT_SYNC_FIFO_ERROR_E5_SHIFT                                         9
+  #define BMB_REG_INT_STS_11_RC_PKT7_DSCR_FIFO_ERROR                                                         (0x1<<18) // Read packet client7 descriptor FIFO error
+  #define BMB_REG_INT_STS_11_RC_PKT7_DSCR_FIFO_ERROR_SHIFT                                                   18
+  #define BMB_REG_INT_STS_11_RC8_SOP_RC_OUT_SYNC_FIFO_ERROR_BB_K2                                            (0x1<<9) // SOP DSCR SYNC FIFO error for RC8
+  #define BMB_REG_INT_STS_11_RC8_SOP_RC_OUT_SYNC_FIFO_ERROR_BB_K2_SHIFT                                      9
+#define BMB_REG_INT_MASK_11                                                                                  0x5401d0UL //Access:RW   DataWidth:0x13   // Multi Field Register.
+  #define BMB_REG_INT_MASK_11_WC8_SYNC_FIFO_PUSH_ERROR                                                       (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_11.WC8_SYNC_FIFO_PUSH_ERROR .
+  #define BMB_REG_INT_MASK_11_WC8_SYNC_FIFO_PUSH_ERROR_SHIFT                                                 6
+  #define BMB_REG_INT_MASK_11_WC9_SYNC_FIFO_PUSH_ERROR                                                       (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_11.WC9_SYNC_FIFO_PUSH_ERROR .
+  #define BMB_REG_INT_MASK_11_WC9_SYNC_FIFO_PUSH_ERROR_SHIFT                                                 7
+  #define BMB_REG_INT_MASK_11_RC1_SOP_RC_OUT_SYNC_FIFO_ERROR_E5                                              (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_11.RC1_SOP_RC_OUT_SYNC_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_11_RC1_SOP_RC_OUT_SYNC_FIFO_ERROR_E5_SHIFT                                        9
+  #define BMB_REG_INT_MASK_11_RC_PKT7_DSCR_FIFO_ERROR                                                        (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_11.RC_PKT7_DSCR_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_11_RC_PKT7_DSCR_FIFO_ERROR_SHIFT                                                  18
+  #define BMB_REG_INT_MASK_11_RC8_SOP_RC_OUT_SYNC_FIFO_ERROR_BB_K2                                           (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_11.RC8_SOP_RC_OUT_SYNC_FIFO_ERROR .
+  #define BMB_REG_INT_MASK_11_RC8_SOP_RC_OUT_SYNC_FIFO_ERROR_BB_K2_SHIFT                                     9
+#define BMB_REG_INT_STS_WR_11                                                                                0x5401d4UL //Access:WR   DataWidth:0x13   // Multi Field Register.
+  #define BMB_REG_INT_STS_WR_11_WC8_SYNC_FIFO_PUSH_ERROR                                                     (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. WC input SYNC FIFO error
+  #define BMB_REG_INT_STS_WR_11_WC8_SYNC_FIFO_PUSH_ERROR_SHIFT                                               6
+  #define BMB_REG_INT_STS_WR_11_WC9_SYNC_FIFO_PUSH_ERROR                                                     (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. WC input SYNC FIFO error
+  #define BMB_REG_INT_STS_WR_11_WC9_SYNC_FIFO_PUSH_ERROR_SHIFT                                               7
+  #define BMB_REG_INT_STS_WR_11_RC1_SOP_RC_OUT_SYNC_FIFO_ERROR_E5                                            (0x1<<9) // SOP DSCR SYNC FIFO error for RC1
+  #define BMB_REG_INT_STS_WR_11_RC1_SOP_RC_OUT_SYNC_FIFO_ERROR_E5_SHIFT                                      9
+  #define BMB_REG_INT_STS_WR_11_RC_PKT7_DSCR_FIFO_ERROR                                                      (0x1<<18) // Read packet client7 descriptor FIFO error
+  #define BMB_REG_INT_STS_WR_11_RC_PKT7_DSCR_FIFO_ERROR_SHIFT                                                18
+  #define BMB_REG_INT_STS_WR_11_RC8_SOP_RC_OUT_SYNC_FIFO_ERROR_BB_K2                                         (0x1<<9) // SOP DSCR SYNC FIFO error for RC8
+  #define BMB_REG_INT_STS_WR_11_RC8_SOP_RC_OUT_SYNC_FIFO_ERROR_BB_K2_SHIFT                                   9
+#define BMB_REG_INT_STS_CLR_11                                                                               0x5401d8UL //Access:RC   DataWidth:0x13   // Multi Field Register.
+  #define BMB_REG_INT_STS_CLR_11_WC8_SYNC_FIFO_PUSH_ERROR                                                    (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. WC input SYNC FIFO error
+  #define BMB_REG_INT_STS_CLR_11_WC8_SYNC_FIFO_PUSH_ERROR_SHIFT                                              6
+  #define BMB_REG_INT_STS_CLR_11_WC9_SYNC_FIFO_PUSH_ERROR                                                    (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. WC input SYNC FIFO error
+  #define BMB_REG_INT_STS_CLR_11_WC9_SYNC_FIFO_PUSH_ERROR_SHIFT                                              7
+  #define BMB_REG_INT_STS_CLR_11_RC1_SOP_RC_OUT_SYNC_FIFO_ERROR_E5                                           (0x1<<9) // SOP DSCR SYNC FIFO error for RC1
+  #define BMB_REG_INT_STS_CLR_11_RC1_SOP_RC_OUT_SYNC_FIFO_ERROR_E5_SHIFT                                     9
+  #define BMB_REG_INT_STS_CLR_11_RC_PKT7_DSCR_FIFO_ERROR                                                     (0x1<<18) // Read packet client7 descriptor FIFO error
+  #define BMB_REG_INT_STS_CLR_11_RC_PKT7_DSCR_FIFO_ERROR_SHIFT                                               18
+  #define BMB_REG_INT_STS_CLR_11_RC8_SOP_RC_OUT_SYNC_FIFO_ERROR_BB_K2                                        (0x1<<9) // SOP DSCR SYNC FIFO error for RC8
+  #define BMB_REG_INT_STS_CLR_11_RC8_SOP_RC_OUT_SYNC_FIFO_ERROR_BB_K2_SHIFT                                  9
+#define BMB_REG_PRTY_MASK                                                                                    0x5401e0UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define BMB_REG_PRTY_MASK_LL_BANK0_MEM_PRTY                                                                (0x1<<0) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS.LL_BANK0_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_LL_BANK0_MEM_PRTY_SHIFT                                                          0
+  #define BMB_REG_PRTY_MASK_LL_BANK1_MEM_PRTY                                                                (0x1<<1) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS.LL_BANK1_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_LL_BANK1_MEM_PRTY_SHIFT                                                          1
+  #define BMB_REG_PRTY_MASK_LL_BANK2_MEM_PRTY                                                                (0x1<<2) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS.LL_BANK2_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_LL_BANK2_MEM_PRTY_SHIFT                                                          2
+  #define BMB_REG_PRTY_MASK_LL_BANK3_MEM_PRTY                                                                (0x1<<3) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS.LL_BANK3_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_LL_BANK3_MEM_PRTY_SHIFT                                                          3
+  #define BMB_REG_PRTY_MASK_DATAPATH_REGISTERS                                                               (0x1<<4) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS.DATAPATH_REGISTERS .
+  #define BMB_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                                         4
+#define BMB_REG_PRTY_MASK_H_0_BB_K2                                                                          0x540404UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define BMB_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_K2                                                    (0x1<<0) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
+  #define BMB_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_K2_SHIFT                                              0
+  #define BMB_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT_BB_K2                                                    (0x1<<1) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM008_I_ECC_RF_INT .
+  #define BMB_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT_BB_K2_SHIFT                                              1
+  #define BMB_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_BB_K2                                                    (0x1<<2) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM009_I_ECC_RF_INT .
+  #define BMB_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_BB_K2_SHIFT                                              2
+  #define BMB_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT_BB_K2                                                    (0x1<<3) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM010_I_ECC_RF_INT .
+  #define BMB_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT_BB_K2_SHIFT                                              3
+  #define BMB_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT_BB_K2                                                    (0x1<<4) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM011_I_ECC_RF_INT .
+  #define BMB_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT_BB_K2_SHIFT                                              4
+  #define BMB_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_BB_K2                                                    (0x1<<5) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM012_I_ECC_RF_INT .
+  #define BMB_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_BB_K2_SHIFT                                              5
+  #define BMB_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT_BB_K2                                                    (0x1<<6) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM013_I_ECC_RF_INT .
+  #define BMB_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT_BB_K2_SHIFT                                              6
+  #define BMB_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_BB_K2                                                    (0x1<<7) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM014_I_ECC_RF_INT .
+  #define BMB_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_BB_K2_SHIFT                                              7
+  #define BMB_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_BB_K2                                                    (0x1<<8) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM015_I_ECC_RF_INT .
+  #define BMB_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_BB_K2_SHIFT                                              8
+  #define BMB_REG_PRTY_MASK_H_0_MEM016_I_ECC_RF_INT_BB_K2                                                    (0x1<<9) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM016_I_ECC_RF_INT .
+  #define BMB_REG_PRTY_MASK_H_0_MEM016_I_ECC_RF_INT_BB_K2_SHIFT                                              9
+  #define BMB_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_BB_K2                                                    (0x1<<10) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT .
+  #define BMB_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_BB_K2_SHIFT                                              10
+  #define BMB_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_BB_K2                                                    (0x1<<11) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
+  #define BMB_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_BB_K2_SHIFT                                              11
+  #define BMB_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_BB_K2                                                    (0x1<<12) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT .
+  #define BMB_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_BB_K2_SHIFT                                              12
+  #define BMB_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_BB_K2                                                    (0x1<<13) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT .
+  #define BMB_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_BB_K2_SHIFT                                              13
+  #define BMB_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_BB_K2                                                    (0x1<<14) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM006_I_ECC_RF_INT .
+  #define BMB_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_BB_K2_SHIFT                                              14
+  #define BMB_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT_BB_K2                                                    (0x1<<15) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM007_I_ECC_RF_INT .
+  #define BMB_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT_BB_K2_SHIFT                                              15
+  #define BMB_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_BB_K2                                                      (0x1<<16) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM059_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_BB_K2_SHIFT                                                16
+  #define BMB_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_BB_K2                                                      (0x1<<17) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM060_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_BB_K2_SHIFT                                                17
+  #define BMB_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_BB_K2                                                      (0x1<<18) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_BB_K2_SHIFT                                                18
+  #define BMB_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_BB_K2                                                      (0x1<<19) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_BB_K2_SHIFT                                                19
+  #define BMB_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_BB_K2                                                      (0x1<<20) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_BB_K2_SHIFT                                                20
+  #define BMB_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_BB_K2                                                      (0x1<<21) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM040_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_BB_K2_SHIFT                                                21
+  #define BMB_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY_BB_K2                                                      (0x1<<22) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM041_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY_BB_K2_SHIFT                                                22
+  #define BMB_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY_BB_K2                                                      (0x1<<23) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM042_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY_BB_K2_SHIFT                                                23
+  #define BMB_REG_PRTY_MASK_H_0_MEM043_I_MEM_PRTY_BB_K2                                                      (0x1<<24) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM043_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_0_MEM043_I_MEM_PRTY_BB_K2_SHIFT                                                24
+  #define BMB_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY_BB_K2                                                      (0x1<<25) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM044_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY_BB_K2_SHIFT                                                25
+  #define BMB_REG_PRTY_MASK_H_0_MEM045_I_MEM_PRTY_BB_K2                                                      (0x1<<26) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM045_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_0_MEM045_I_MEM_PRTY_BB_K2_SHIFT                                                26
+  #define BMB_REG_PRTY_MASK_H_0_MEM046_I_MEM_PRTY_BB_K2                                                      (0x1<<27) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM046_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_0_MEM046_I_MEM_PRTY_BB_K2_SHIFT                                                27
+  #define BMB_REG_PRTY_MASK_H_0_MEM047_I_MEM_PRTY_BB_K2                                                      (0x1<<28) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM047_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_0_MEM047_I_MEM_PRTY_BB_K2_SHIFT                                                28
+  #define BMB_REG_PRTY_MASK_H_0_MEM048_I_MEM_PRTY_BB_K2                                                      (0x1<<29) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM048_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_0_MEM048_I_MEM_PRTY_BB_K2_SHIFT                                                29
+  #define BMB_REG_PRTY_MASK_H_0_MEM049_I_MEM_PRTY_BB_K2                                                      (0x1<<30) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM049_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_0_MEM049_I_MEM_PRTY_BB_K2_SHIFT                                                30
+#define BMB_REG_PRTY_MASK_H_1_BB_K2                                                                          0x540414UL //Access:RW   DataWidth:0xf    // Multi Field Register.
+  #define BMB_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_BB_K2                                                      (0x1<<0) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_BB_K2_SHIFT                                                0
+  #define BMB_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_BB_K2                                                      (0x1<<1) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM051_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_BB_K2_SHIFT                                                1
+  #define BMB_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_BB_K2                                                      (0x1<<2) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_BB_K2_SHIFT                                                2
+  #define BMB_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_BB_K2                                                      (0x1<<3) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM053_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_BB_K2_SHIFT                                                3
+  #define BMB_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY_BB_K2                                                      (0x1<<4) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM054_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY_BB_K2_SHIFT                                                4
+  #define BMB_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_BB_K2                                                      (0x1<<5) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM055_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_BB_K2_SHIFT                                                5
+  #define BMB_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY_BB_K2                                                      (0x1<<6) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM056_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY_BB_K2_SHIFT                                                6
+  #define BMB_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_BB_K2                                                      (0x1<<7) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM057_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_BB_K2_SHIFT                                                7
+  #define BMB_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_BB_K2                                                      (0x1<<8) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM058_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_BB_K2_SHIFT                                                8
+  #define BMB_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_BB_K2                                                      (0x1<<9) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM033_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_BB_K2_SHIFT                                                9
+  #define BMB_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_BB_K2                                                      (0x1<<10) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM034_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_BB_K2_SHIFT                                                10
+  #define BMB_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_BB_K2                                                      (0x1<<11) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM035_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_BB_K2_SHIFT                                                11
+  #define BMB_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_BB_K2                                                      (0x1<<12) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_BB_K2_SHIFT                                                12
+  #define BMB_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_BB_K2                                                      (0x1<<13) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM021_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_BB_K2_SHIFT                                                13
+  #define BMB_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_BB_K2                                                      (0x1<<14) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM022_I_MEM_PRTY .
+  #define BMB_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_BB_K2_SHIFT                                                14
+#define BMB_REG_MEM001_RF_ECC_ERROR_CONNECT_BB_K2                                                            0x540420UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: bmb.BB_BANK_GEN_FOR[0].i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BMB_REG_MEM008_RF_ECC_ERROR_CONNECT_BB_K2                                                            0x540424UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: bmb.BB_BANK_GEN_FOR[1].i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BMB_REG_MEM009_RF_ECC_ERROR_CONNECT_BB_K2                                                            0x540428UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: bmb.BB_BANK_GEN_FOR[2].i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BMB_REG_MEM010_RF_ECC_ERROR_CONNECT_BB_K2                                                            0x54042cUL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: bmb.BB_BANK_GEN_FOR[3].i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BMB_REG_MEM011_RF_ECC_ERROR_CONNECT_BB_K2                                                            0x540430UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: bmb.BB_BANK_GEN_FOR[4].i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BMB_REG_MEM012_RF_ECC_ERROR_CONNECT_BB_K2                                                            0x540434UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: bmb.BB_BANK_GEN_FOR[5].i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BMB_REG_MEM013_RF_ECC_ERROR_CONNECT_BB_K2                                                            0x540438UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: bmb.BB_BANK_GEN_FOR[6].i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BMB_REG_MEM014_RF_ECC_ERROR_CONNECT_BB_K2                                                            0x54043cUL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: bmb.BB_BANK_GEN_FOR[7].i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BMB_REG_MEM015_RF_ECC_ERROR_CONNECT_BB_K2                                                            0x540440UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: bmb.BB_BANK_GEN_FOR[8].i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BMB_REG_MEM016_RF_ECC_ERROR_CONNECT_BB_K2                                                            0x540444UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: bmb.BB_BANK_GEN_FOR[9].i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BMB_REG_MEM002_RF_ECC_ERROR_CONNECT_BB_K2                                                            0x540448UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: bmb.BB_BANK_GEN_FOR[10].i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BMB_REG_MEM003_RF_ECC_ERROR_CONNECT_BB_K2                                                            0x54044cUL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: bmb.BB_BANK_GEN_FOR[11].i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BMB_REG_MEM004_RF_ECC_ERROR_CONNECT_BB_K2                                                            0x540450UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: bmb.BB_BANK_GEN_FOR[12].i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BMB_REG_MEM005_RF_ECC_ERROR_CONNECT_BB_K2                                                            0x540454UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: bmb.BB_BANK_GEN_FOR[13].i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BMB_REG_MEM006_RF_ECC_ERROR_CONNECT_BB_K2                                                            0x540458UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: bmb.BB_BANK_GEN_FOR[14].i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BMB_REG_MEM007_RF_ECC_ERROR_CONNECT_BB_K2                                                            0x54045cUL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: bmb.BB_BANK_GEN_FOR[15].i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BMB_REG_MEM_ECC_ENABLE_0_BB_K2                                                                       0x540460UL //Access:RW   DataWidth:0x10   // Multi Field Register.
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_BB_K2                                                     (0x1<<0) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[0].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_BB_K2_SHIFT                                               0
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_EN_BB_K2                                                     (0x1<<1) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[1].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_EN_BB_K2_SHIFT                                               1
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_EN_BB_K2                                                     (0x1<<2) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[2].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_EN_BB_K2_SHIFT                                               2
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_EN_BB_K2                                                     (0x1<<3) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[3].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_EN_BB_K2_SHIFT                                               3
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_EN_BB_K2                                                     (0x1<<4) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[4].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_EN_BB_K2_SHIFT                                               4
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN_BB_K2                                                     (0x1<<5) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[5].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN_BB_K2_SHIFT                                               5
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM013_I_ECC_EN_BB_K2                                                     (0x1<<6) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[6].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM013_I_ECC_EN_BB_K2_SHIFT                                               6
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN_BB_K2                                                     (0x1<<7) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[7].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN_BB_K2_SHIFT                                               7
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN_BB_K2                                                     (0x1<<8) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[8].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN_BB_K2_SHIFT                                               8
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_EN_BB_K2                                                     (0x1<<9) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[9].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_EN_BB_K2_SHIFT                                               9
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN_BB_K2                                                     (0x1<<10) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[10].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN_BB_K2_SHIFT                                               10
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_BB_K2                                                     (0x1<<11) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[11].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_BB_K2_SHIFT                                               11
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_BB_K2                                                     (0x1<<12) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[12].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_BB_K2_SHIFT                                               12
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_BB_K2                                                     (0x1<<13) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[13].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_BB_K2_SHIFT                                               13
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN_BB_K2                                                     (0x1<<14) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[14].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN_BB_K2_SHIFT                                               14
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_EN_BB_K2                                                     (0x1<<15) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[15].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_EN_BB_K2_SHIFT                                               15
+#define BMB_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                  0x540464UL //Access:RW   DataWidth:0x10   // Multi Field Register.
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_BB_K2                                              (0x1<<0) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[0].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_BB_K2_SHIFT                                        0
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_PRTY_BB_K2                                              (0x1<<1) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[1].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_PRTY_BB_K2_SHIFT                                        1
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_PRTY_BB_K2                                              (0x1<<2) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[2].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_PRTY_BB_K2_SHIFT                                        2
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_PRTY_BB_K2                                              (0x1<<3) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[3].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_PRTY_BB_K2_SHIFT                                        3
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_PRTY_BB_K2                                              (0x1<<4) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[4].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_PRTY_BB_K2_SHIFT                                        4
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY_BB_K2                                              (0x1<<5) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[5].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY_BB_K2_SHIFT                                        5
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM013_I_ECC_PRTY_BB_K2                                              (0x1<<6) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[6].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM013_I_ECC_PRTY_BB_K2_SHIFT                                        6
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY_BB_K2                                              (0x1<<7) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[7].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY_BB_K2_SHIFT                                        7
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY_BB_K2                                              (0x1<<8) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[8].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY_BB_K2_SHIFT                                        8
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_PRTY_BB_K2                                              (0x1<<9) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[9].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_PRTY_BB_K2_SHIFT                                        9
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY_BB_K2                                              (0x1<<10) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[10].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY_BB_K2_SHIFT                                        10
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_BB_K2                                              (0x1<<11) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[11].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_BB_K2_SHIFT                                        11
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_BB_K2                                              (0x1<<12) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[12].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_BB_K2_SHIFT                                        12
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_BB_K2                                              (0x1<<13) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[13].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_BB_K2_SHIFT                                        13
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY_BB_K2                                              (0x1<<14) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[14].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY_BB_K2_SHIFT                                        14
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_PRTY_BB_K2                                              (0x1<<15) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[15].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_PRTY_BB_K2_SHIFT                                        15
+#define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                              0x540468UL //Access:RC   DataWidth:0x10   // Multi Field Register.
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_BB_K2                                       (0x1<<0) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[0].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_BB_K2_SHIFT                                 0
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_CORRECT_BB_K2                                       (0x1<<1) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[1].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_CORRECT_BB_K2_SHIFT                                 1
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_CORRECT_BB_K2                                       (0x1<<2) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[2].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_CORRECT_BB_K2_SHIFT                                 2
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_CORRECT_BB_K2                                       (0x1<<3) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[3].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_CORRECT_BB_K2_SHIFT                                 3
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_CORRECT_BB_K2                                       (0x1<<4) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[4].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_CORRECT_BB_K2_SHIFT                                 4
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT_BB_K2                                       (0x1<<5) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[5].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT_BB_K2_SHIFT                                 5
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM013_I_ECC_CORRECT_BB_K2                                       (0x1<<6) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[6].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM013_I_ECC_CORRECT_BB_K2_SHIFT                                 6
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT_BB_K2                                       (0x1<<7) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[7].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT_BB_K2_SHIFT                                 7
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT_BB_K2                                       (0x1<<8) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[8].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT_BB_K2_SHIFT                                 8
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_CORRECT_BB_K2                                       (0x1<<9) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[9].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_CORRECT_BB_K2_SHIFT                                 9
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT_BB_K2                                       (0x1<<10) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[10].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT_BB_K2_SHIFT                                 10
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_BB_K2                                       (0x1<<11) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[11].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_BB_K2_SHIFT                                 11
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_BB_K2                                       (0x1<<12) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[12].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_BB_K2_SHIFT                                 12
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_BB_K2                                       (0x1<<13) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[13].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_BB_K2_SHIFT                                 13
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT_BB_K2                                       (0x1<<14) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[14].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT_BB_K2_SHIFT                                 14
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_CORRECT_BB_K2                                       (0x1<<15) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[15].i_bb_bank.i_ecc in module bmb_bb_bank
+  #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_CORRECT_BB_K2_SHIFT                                 15
+#define BMB_REG_MEM_ECC_EVENTS_BB_K2                                                                         0x54046cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define BMB_REG_BIG_RAM_ADDRESS                                                                              0x540800UL //Access:RW   DataWidth:0xa    // Debug register. It contains address to Big RAM for RBC operations. Value of this register will be incremented by one it was done write access to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_WDTH/13/g in Data Width.
+#define BMB_REG_HEADER_SIZE                                                                                  0x540804UL //Access:RW   DataWidth:0xa    // Number of valid bytes in header in 16-bytes resolution. After this number of bytes will input to BRTB will be sent packet available indication. (reset value of 17 suits to 282 bytes of header)::s/HDR_SIZE_RST/17/g in Reset Value.
+#define BMB_REG_FREE_LIST_HEAD                                                                               0x540810UL //Access:RW   DataWidth:0xb    // Head pointer to each one of 4 free lists::s/BLK_WDTH/13/g in Data Width.
+#define BMB_REG_FREE_LIST_HEAD_SIZE                                                                          4
+#define BMB_REG_FREE_LIST_TAIL                                                                               0x540820UL //Access:RW   DataWidth:0xb    // Tail pointer of each one of 4 free lists::s/BLK_WDTH/13/g in Data Width.
+#define BMB_REG_FREE_LIST_TAIL_SIZE                                                                          4
+#define BMB_REG_FREE_LIST_SIZE                                                                               0x540830UL //Access:RW   DataWidth:0xb    // Number of free blocks in each one of 4 free lists::s/BLK_WDTH/13/g in Data Width.
+#define BMB_REG_FREE_LIST_SIZE_SIZE                                                                          4
+#define BMB_REG_MAX_RELEASES                                                                                 0x540840UL //Access:RW   DataWidth:0x2    // Number of packet copies that should be released before whole packet is released::s/MAX_RLS_WDTH/10/g in Data Width::s/MAX_RLS_RST/512/g in Reset Value::s/MAX_RLS_REQ/required/g in Required::s/MAX_RLS_REQ/required/g in Software init.
+#define BMB_REG_STOP_ON_LEN_ERR                                                                              0x540844UL //Access:RW   DataWidth:0x3    // There is bit for each PACKET read client. When bit is set then read client will not execute more requests till reset in a case of length error other way it will continue to work as usual.::s/STOP_LEN_ERR_RST/7/g in Reset Value::s/PKT_RC_NUM/5/g in Data Width.
+#define BMB_REG_SHARED_HR_AREA                                                                               0x540848UL //Access:RW   DataWidth:0xb    // The total number available blocks for each MAC port that includes shared and headroom areas. This register should be equal to total_mac_size - SUM(tc_guarantied) Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::s/MAX_SHARE_GRP_WDTH/1/g in Address Width::s/SHARED_HR_RST/2112/g in Reset Value::/PAUSE_EN/d in Existance.
+#define BMB_REG_TOTAL_MAC_SIZE                                                                               0x54084cUL //Access:RW   DataWidth:0xb    // The total number available blocks for each MAC port that includes guaranteed and shared and headroom areas. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::s/MAX_SHARE_GRP_WDTH/1/g in Address Width::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_GUARANTIED_0                                                                              0x540850UL //Access:RW   DataWidth:0xb    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_GUARANTIED_1                                                                              0x540854UL //Access:RW   DataWidth:0xb    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_GUARANTIED_2                                                                              0x540858UL //Access:RW   DataWidth:0xb    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_GUARANTIED_3                                                                              0x54085cUL //Access:RW   DataWidth:0xb    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_GUARANTIED_4                                                                              0x540860UL //Access:RW   DataWidth:0xb    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_GUARANTIED_5                                                                              0x540864UL //Access:RW   DataWidth:0xb    // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_GUARANTIED_HYST_0                                                                         0x540878UL //Access:RW   DataWidth:0xb    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_GUARANTIED_HYST_1                                                                         0x54087cUL //Access:RW   DataWidth:0xb    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_GUARANTIED_HYST_2                                                                         0x540880UL //Access:RW   DataWidth:0xb    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_GUARANTIED_HYST_3                                                                         0x540884UL //Access:RW   DataWidth:0xb    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_GUARANTIED_HYST_4                                                                         0x540888UL //Access:RW   DataWidth:0xb    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_GUARANTIED_HYST_5                                                                         0x54088cUL //Access:RW   DataWidth:0xb    // The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_PAUSE_XOFF_THRESHOLD_0                                                                    0x5408a0UL //Access:RW   DataWidth:0xb    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_PAUSE_XOFF_THRESHOLD_1                                                                    0x5408a4UL //Access:RW   DataWidth:0xb    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_PAUSE_XOFF_THRESHOLD_2                                                                    0x5408a8UL //Access:RW   DataWidth:0xb    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_PAUSE_XOFF_THRESHOLD_3                                                                    0x5408acUL //Access:RW   DataWidth:0xb    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_PAUSE_XOFF_THRESHOLD_4                                                                    0x5408b0UL //Access:RW   DataWidth:0xb    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_PAUSE_XOFF_THRESHOLD_5                                                                    0x5408b4UL //Access:RW   DataWidth:0xb    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_PAUSE_XON_THRESHOLD_0                                                                     0x5408c8UL //Access:RW   DataWidth:0xb    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_PAUSE_XON_THRESHOLD_1                                                                     0x5408ccUL //Access:RW   DataWidth:0xb    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_PAUSE_XON_THRESHOLD_2                                                                     0x5408d0UL //Access:RW   DataWidth:0xb    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_PAUSE_XON_THRESHOLD_3                                                                     0x5408d4UL //Access:RW   DataWidth:0xb    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_PAUSE_XON_THRESHOLD_4                                                                     0x5408d8UL //Access:RW   DataWidth:0xb    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_PAUSE_XON_THRESHOLD_5                                                                     0x5408dcUL //Access:RW   DataWidth:0xb    // If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_FULL_XOFF_THRESHOLD_0                                                                     0x5408f0UL //Access:RW   DataWidth:0xb    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_FULL_XOFF_THRESHOLD_1                                                                     0x5408f4UL //Access:RW   DataWidth:0xb    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_FULL_XOFF_THRESHOLD_2                                                                     0x5408f8UL //Access:RW   DataWidth:0xb    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_FULL_XOFF_THRESHOLD_3                                                                     0x5408fcUL //Access:RW   DataWidth:0xb    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_FULL_XOFF_THRESHOLD_4                                                                     0x540900UL //Access:RW   DataWidth:0xb    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_FULL_XOFF_THRESHOLD_5                                                                     0x540904UL //Access:RW   DataWidth:0xb    // If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_FULL_XON_THRESHOLD_0                                                                      0x540918UL //Access:RW   DataWidth:0xb    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_FULL_XON_THRESHOLD_1                                                                      0x54091cUL //Access:RW   DataWidth:0xb    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_FULL_XON_THRESHOLD_2                                                                      0x540920UL //Access:RW   DataWidth:0xb    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_FULL_XON_THRESHOLD_3                                                                      0x540924UL //Access:RW   DataWidth:0xb    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_FULL_XON_THRESHOLD_4                                                                      0x540928UL //Access:RW   DataWidth:0xb    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_FULL_XON_THRESHOLD_5                                                                      0x54092cUL //Access:RW   DataWidth:0xb    // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_NO_DEAD_CYCLES_EN                                                                            0x540940UL //Access:RW   DataWidth:0x3    // There is bit for each PACKET read client. Bit 0 suits to client 0 and so on. If bit is set then packet will be read without dead cycles.TBD ::s/NO_DEAD_CYCLE_RST/1/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser/g in Comments::s/PKT_RC_NUM/5/g in Data Width.
+#define BMB_REG_RC_PKT_PRIORITY                                                                              0x540944UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define BMB_REG_RC_PKT_PRIORITY_RC0_PRI                                                                    (0x3<<0) // This is priority for rc0  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
+  #define BMB_REG_RC_PKT_PRIORITY_RC0_PRI_SHIFT                                                              0
+  #define BMB_REG_RC_PKT_PRIORITY_RC1_PRI                                                                    (0x3<<2) // This is priority for rc1  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
+  #define BMB_REG_RC_PKT_PRIORITY_RC1_PRI_SHIFT                                                              2
+  #define BMB_REG_RC_PKT_PRIORITY_RC2_PRI                                                                    (0x3<<4) // This is priority for rc2  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
+  #define BMB_REG_RC_PKT_PRIORITY_RC2_PRI_SHIFT                                                              4
+  #define BMB_REG_RC_PKT_PRIORITY_RC3_PRI                                                                    (0x3<<6) // This is priority for rc3  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
+  #define BMB_REG_RC_PKT_PRIORITY_RC3_PRI_SHIFT                                                              6
+  #define BMB_REG_RC_PKT_PRIORITY_RC4_PRI                                                                    (0x3<<8) // This is priority for rc0  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
+  #define BMB_REG_RC_PKT_PRIORITY_RC4_PRI_SHIFT                                                              8
+  #define BMB_REG_RC_PKT_PRIORITY_RC5_PRI                                                                    (0x3<<10) // This is priority for rc5  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
+  #define BMB_REG_RC_PKT_PRIORITY_RC5_PRI_SHIFT                                                              10
+  #define BMB_REG_RC_PKT_PRIORITY_RC6_PRI                                                                    (0x3<<12) // This is priority for parser  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
+  #define BMB_REG_RC_PKT_PRIORITY_RC6_PRI_SHIFT                                                              12
+  #define BMB_REG_RC_PKT_PRIORITY_RC7_PRI                                                                    (0x3<<14) // This is priority for parser  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
+  #define BMB_REG_RC_PKT_PRIORITY_RC7_PRI_SHIFT                                                              14
+  #define BMB_REG_RC_PKT_PRIORITY_RC8_PRI                                                                    (0x3<<16) // This is priority for read client 8 that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest
+  #define BMB_REG_RC_PKT_PRIORITY_RC8_PRI_SHIFT                                                              16
+  #define BMB_REG_RC_PKT_PRIORITY_RC9_PRI                                                                    (0x3<<18) // This is priority for read client 9 that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest
+  #define BMB_REG_RC_PKT_PRIORITY_RC9_PRI_SHIFT                                                              18
+#define BMB_REG_WC_NO_DEAD_CYCLES_EN_K2_E5                                                                   0x540948UL //Access:RW   DataWidth:0xa    // There is bit for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then packet will be written without intra packet dead cycles .TBD ::s/NO_DEAD_CYCLE_RST/1/g in Reset
+#define BMB_REG_WC_HIGHEST_PRI_EN_K2_E5                                                                      0x54094cUL //Access:RW   DataWidth:0xa    // There is bit for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then highest priority mechanism is enabled for the corresponding client. TBD ::s/NO_DEAD_CYCLE_RST/1/g in Reset
+#define BMB_REG_WC_LL_HIGH_PRI_E5                                                                            0x540950UL //Access:RW   DataWidth:0xa    // This is a bitmap per WC which is 1 for WC with high priority and 0 o/w.
+#define BMB_REG_BR_FIX_HIGH_PRI_COLLISION_E5                                                                 0x540954UL //Access:RW   DataWidth:0x1    // This is a bitmap per WC which is 1 for WC with high priority and 0 o/w.
+#define BMB_REG_RC_SOP_PRIORITY                                                                              0x540980UL //Access:RW   DataWidth:0x2    // This is priority for SOP read client to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_SOP_PRI_RST/5/g in Reset Value.
+#define BMB_REG_WC_PRIORITY                                                                                  0x540984UL //Access:RW   DataWidth:0x2    // This is priority for packet request of write client group to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_WC_PRI_RST/7/g in Reset Value.
+#define BMB_REG_PRI_OF_MULT_CLIENTS                                                                          0x540988UL //Access:RW   DataWidth:0x2    // This is priority of multiple clients with identical priority for link list arbiter. Selection from them will be done with round robin. Only one group with multiple clients of identical priority is supported. Possible values are 1-3. Priority 3 is highest::s/RC_MULT_PRI_RST/6/g in Reset Value.
+#define BMB_REG_INP_FIFO_ALM_FULL                                                                            0x54098cUL //Access:RW   DataWidth:0x5    // Number of entries inside input FIFO of each write client upper which full outputs to this write client interface.
+#define BMB_REG_WC_SYNC_FIFO_ALM_FULL                                                                        0x540990UL //Access:RW   DataWidth:0x5    // Number of entries inside sync FIFO of each write client.
+#define BMB_REG_PKT_RC_OUT_SYNC_FIFO_ALM_FULL                                                                0x540994UL //Access:RW   DataWidth:0x5    // Number of entries inside output sync FIFO of each read client.
+#define BMB_REG_PKT_AVAIL_SYNC_FIFO_ALM_FULL                                                                 0x540998UL //Access:RW   DataWidth:0x4    // Number of entries inside packet available sync FIFO.
+#define BMB_REG_RLS_SYNC_FIFO_ALM_FULL                                                                       0x54099cUL //Access:RW   DataWidth:0x4    // Number of entries inside packet available sync FIFO.
+#define BMB_REG_INP_FIFO_HIGH_THRESHOLD                                                                      0x5409a0UL //Access:RW   DataWidth:0x5    // Number of entries inside input FIFO of each write client upper which all arbiters selects this client with high priority.
+#define BMB_REG_DSCR_FIFO_ALM_FULL                                                                           0x5409a4UL //Access:RW   DataWidth:0x5    // Number of entries inside descriptors FIFO of each write client upper which full outputs to this write client interface.::s/DSCR_FIFO_RST/12/g in Reset Value.
+#define BMB_REG_QUEUE_FIFO_ALM_FULL                                                                          0x5409a8UL //Access:RW   DataWidth:0x5    // Number of entries inside queue FIFO of each write client upper which full outputs to this write client interface.::s/QUEUE_FIFO_RST/8/g in Reset Value.
+#define BMB_REG_DSCR_FIFO_HIGH_THRESHOLD                                                                     0x5409acUL //Access:RW   DataWidth:0x5    // Number of entries inside descriptors FIFO of each write client upper which all arbiters selects this client with high priority.
+#define BMB_REG_PM_TC_LATENCY_SENSITIVE_0                                                                    0x5409b0UL //Access:RW   DataWidth:0x6    // Per TC enable for output BRB_above_threshold_mac_n to power management block when number of packets of appropriate TC is bigger than 1::s/COS_NUM/9/g in Data Width::s/LATENCY_RST/511/g in Reset Value::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance.
+#define BMB_REG_PM_COS_THRESHOLD_0                                                                           0x540a30UL //Access:RW   DataWidth:0xb    // Per COS threshold. BRTB indicates full to CPMU if one of the COSes has more blocks than its threshold.
+#define BMB_REG_PM_COS_THRESHOLD_1                                                                           0x540a34UL //Access:RW   DataWidth:0xb    // Per COS threshold. BRTB indicates full to CPMU if one of the COSes has more blocks than its threshold.
+#define BMB_REG_PM_COS_THRESHOLD_2                                                                           0x540a38UL //Access:RW   DataWidth:0xb    // Per COS threshold. BRTB indicates full to CPMU if one of the COSes has more blocks than its threshold.
+#define BMB_REG_PM_COS_THRESHOLD_3                                                                           0x540a3cUL //Access:RW   DataWidth:0xb    // Per COS threshold. BRTB indicates full to CPMU if one of the COSes has more blocks than its threshold.
+#define BMB_REG_PM_COS_THRESHOLD_4                                                                           0x540a40UL //Access:RW   DataWidth:0xb    // Per COS threshold. BRTB indicates full to CPMU if one of the COSes has more blocks than its threshold.
+#define BMB_REG_PM_COS_THRESHOLD_5                                                                           0x540a44UL //Access:RW   DataWidth:0xb    // Per COS threshold. BRTB indicates full to CPMU if one of the COSes has more blocks than its threshold.
+#define BMB_REG_DBGSYN_ALMOST_FULL_THR                                                                       0x540a70UL //Access:RW   DataWidth:0x4    // Debug only: If more than this Number of entries are occupied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed.
+#define BMB_REG_DBGSYN_STATUS                                                                                0x540a74UL //Access:R    DataWidth:0x5    // Fill level of dbgmux fifo.
+#define BMB_REG_ECO_RESERVED                                                                                 0x540a78UL //Access:RW   DataWidth:0x20   // This is unused register for future ECOs.
+#define BMB_REG_DBG_SELECT                                                                                   0x540a7cUL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define BMB_REG_DBG_DWORD_ENABLE                                                                             0x540a80UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define BMB_REG_DBG_SHIFT                                                                                    0x540a84UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define BMB_REG_DBG_FORCE_VALID                                                                              0x540a88UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define BMB_REG_DBG_FORCE_FRAME                                                                              0x540a8cUL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define BMB_REG_DBG_OUT_DATA                                                                                 0x540aa0UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define BMB_REG_DBG_OUT_DATA_SIZE                                                                            8
+#define BMB_REG_DBG_OUT_VALID                                                                                0x540ac0UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define BMB_REG_DBG_OUT_FRAME                                                                                0x540ac4UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define BMB_REG_INP_IF_ENABLE                                                                                0x540ac8UL //Access:RW   DataWidth:0x15   // Multi Field Register.
+  #define BMB_REG_INP_IF_ENABLE_RC_PKT_INP_IF_EN                                                             (0x3ff<<0) // There is bit per each read client interface: TBD. When bit is set then appropriate interface is enabled. When bit is reset then request from that interface will not be accepted. All bits of this register should be set after init procedure. ::s/PKT_RC_NUM_MINUS_SOP_EN/4/g in Data Width::s/RC_PKT_INP_IF_RST/15/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser/g in Comments.
+  #define BMB_REG_INP_IF_ENABLE_RC_PKT_INP_IF_EN_SHIFT                                                       0
+  #define BMB_REG_INP_IF_ENABLE_RC_SOP_INP_IF_EN                                                             (0x1<<10) // There is bit per SOP read client interface. When bit is set then appropriate interface is enabled. When bit is reset then request from that interface will not be accepted.  All bits of this register should be set after init procedure.
+  #define BMB_REG_INP_IF_ENABLE_RC_SOP_INP_IF_EN_SHIFT                                                       10
+  #define BMB_REG_INP_IF_ENABLE_WC_INP_IF_EN                                                                 (0x3ff<<11) // There is bit per write client interface: B0 - NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1.. When bit is set then appropriate interface is enabled. When bit is reset then request from that interface will not be accepted. All bits of this register should be set after init procedure. ::s/WC_IF_RST/15/g in Reset Value::s/WC_EN/B0 - NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1./g in Comments::s/WC_NUM/4/g in Data Width.
+  #define BMB_REG_INP_IF_ENABLE_WC_INP_IF_EN_SHIFT                                                           11
+#define BMB_REG_OUT_IF_ENABLE                                                                                0x540accUL //Access:RW   DataWidth:0x11   // Multi Field Register.
+  #define BMB_REG_OUT_IF_ENABLE_RC_PKT_OUT_IF_EN                                                             (0x3ff<<0) // There is bit per each read client interface: TBD. When bit is set then appropriate interface is enabled. When bit is reset then valid to that interface will never be asserted. All bits of this register should be set after init procedure. ::s/RC_PKT_OUT_IF_RST/31/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser/g in Comments::s/PKT_RC_NUM/5/g in Data Width.
+  #define BMB_REG_OUT_IF_ENABLE_RC_PKT_OUT_IF_EN_SHIFT                                                       0
+  #define BMB_REG_OUT_IF_ENABLE_RC_SOP_OUT_IF_EN                                                             (0x1<<10) // There is bit per SOP read client interface. When bit is set then appropriate interface is enabled. When bit is reset then valid to that interface will never be asserted.  All bits of this register should be set after init procedure.
+  #define BMB_REG_OUT_IF_ENABLE_RC_SOP_OUT_IF_EN_SHIFT                                                       10
+  #define BMB_REG_OUT_IF_ENABLE_PAUSE_OUT_IF_EN                                                              (0xf<<11) // There is bit for all pause interfaces per each MAC port. When bit is set then pause interface is enabled. When bit is reset then any pause will never be set. This bit should be set after init procedure. ::s/SHARE_GRP_CNT/2/g in Data Width::s/SHARE_GRP_INIT/3/g in Reset Value::/PAUSE_EN/d in Existance.
+  #define BMB_REG_OUT_IF_ENABLE_PAUSE_OUT_IF_EN_SHIFT                                                        11
+  #define BMB_REG_OUT_IF_ENABLE_PKT_AVAILABLE_OUT_IF_EN                                                      (0x1<<15) // There is bit for packet avalable interfaces. When bit is set then packet avalable interface is enabled. When bit is reset then packet avalable interface will never be set.  This bit should be set after init procedure.
+  #define BMB_REG_OUT_IF_ENABLE_PKT_AVAILABLE_OUT_IF_EN_SHIFT                                                15
+  #define BMB_REG_OUT_IF_ENABLE_PM_OUT_IF_EN                                                                 (0x1<<16) // There is bit for power management interfaces. When bit is set then  power management interface is enabled. When bit is reset then  power management interface will never be set.  This bit should be set after init procedure. ::/EMPTY_EN/d in Existance.
+  #define BMB_REG_OUT_IF_ENABLE_PM_OUT_IF_EN_SHIFT                                                           16
+#define BMB_REG_WC_EMPTY_0                                                                                   0x540ad0UL //Access:R    DataWidth:0xd    // Debug register. Empty status of each write clients. TBD: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.
+#define BMB_REG_WC_EMPTY_1                                                                                   0x540ad4UL //Access:R    DataWidth:0xd    // Debug register. Empty status of each write clients. TBD: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.
+#define BMB_REG_WC_EMPTY_2                                                                                   0x540ad8UL //Access:R    DataWidth:0xd    // Debug register. Empty status of each write clients. TBD: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.
+#define BMB_REG_WC_EMPTY_3                                                                                   0x540adcUL //Access:R    DataWidth:0xd    // Debug register. Empty status of each write clients. TBD: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.
+#define BMB_REG_WC_EMPTY_4                                                                                   0x540ae0UL //Access:R    DataWidth:0xd    // Debug register. Empty status of each write clients. TBD: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.
+#define BMB_REG_WC_EMPTY_5                                                                                   0x540ae4UL //Access:R    DataWidth:0xd    // Debug register. Empty status of each write clients. TBD: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.
+#define BMB_REG_WC_EMPTY_6                                                                                   0x540ae8UL //Access:R    DataWidth:0xd    // Debug register. Empty status of each write clients. TBD: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.
+#define BMB_REG_WC_EMPTY_7                                                                                   0x540aecUL //Access:R    DataWidth:0xd    // Debug register. Empty status of each write clients. TBD: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.
+#define BMB_REG_WC_EMPTY_8                                                                                   0x540af0UL //Access:R    DataWidth:0xd    // Debug register. Empty status of each write clients. TBD: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.
+#define BMB_REG_WC_EMPTY_9                                                                                   0x540af4UL //Access:R    DataWidth:0xd    // Debug register. Empty status of each write clients. TBD: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.
+#define BMB_REG_WC_FULL_0                                                                                    0x540b10UL //Access:R    DataWidth:0xd    // Debug register. Full status of write clients. TBD: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}
+#define BMB_REG_WC_FULL_1                                                                                    0x540b14UL //Access:R    DataWidth:0xd    // Debug register. Full status of write clients. TBD: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}
+#define BMB_REG_WC_FULL_2                                                                                    0x540b18UL //Access:R    DataWidth:0xd    // Debug register. Full status of write clients. TBD: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}
+#define BMB_REG_WC_FULL_3                                                                                    0x540b1cUL //Access:R    DataWidth:0xd    // Debug register. Full status of write clients. TBD: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}
+#define BMB_REG_WC_FULL_4                                                                                    0x540b20UL //Access:R    DataWidth:0xd    // Debug register. Full status of write clients. TBD: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}
+#define BMB_REG_WC_FULL_5                                                                                    0x540b24UL //Access:R    DataWidth:0xd    // Debug register. Full status of write clients. TBD: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}
+#define BMB_REG_WC_FULL_6                                                                                    0x540b28UL //Access:R    DataWidth:0xd    // Debug register. Full status of write clients. TBD: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}
+#define BMB_REG_WC_FULL_7                                                                                    0x540b2cUL //Access:R    DataWidth:0xd    // Debug register. Full status of write clients. TBD: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}
+#define BMB_REG_WC_FULL_8                                                                                    0x540b30UL //Access:R    DataWidth:0xd    // Debug register. Full status of write clients. TBD: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}
+#define BMB_REG_WC_FULL_9                                                                                    0x540b34UL //Access:R    DataWidth:0xd    // Debug register. Full status of write clients. TBD: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}
+#define BMB_REG_WC_BANDWIDTH_IF_FULL                                                                         0x540b50UL //Access:R    DataWidth:0xa    // Debug register. Full status each write client because of temporal bandwidth problem on interface::s/WC_NUM_MAX/4/g in Data Width.
+#define BMB_REG_RC_PKT_IF_FULL                                                                               0x540b54UL //Access:R    DataWidth:0x3    // Debug register. Full status of each read packet client interface::s/PKT_RC_NUM/5/g in Data Width.
+#define BMB_REG_RC_PKT_EMPTY_0                                                                               0x540b58UL //Access:R    DataWidth:0x8    // Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_EMPTY_1                                                                               0x540b5cUL //Access:R    DataWidth:0x8    // Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_EMPTY_2                                                                               0x540b60UL //Access:R    DataWidth:0x8    // Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_EMPTY_3_BB_K2                                                                         0x540b64UL //Access:R    DataWidth:0x8    // Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_EMPTY_4_BB_K2                                                                         0x540b68UL //Access:R    DataWidth:0x8    // Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_EMPTY_5_BB_K2                                                                         0x540b6cUL //Access:R    DataWidth:0x8    // Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_EMPTY_6_BB_K2                                                                         0x540b70UL //Access:R    DataWidth:0x8    // Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_EMPTY_7_BB_K2                                                                         0x540b74UL //Access:R    DataWidth:0x8    // Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_EMPTY_8_BB_K2                                                                         0x540b78UL //Access:R    DataWidth:0x8    // Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_EMPTY_9_BB_K2                                                                         0x540b7cUL //Access:R    DataWidth:0x8    // Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_FULL_0                                                                                0x540b94UL //Access:R    DataWidth:0x8    // Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_FULL_1                                                                                0x540b98UL //Access:R    DataWidth:0x8    // Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_FULL_2                                                                                0x540b9cUL //Access:R    DataWidth:0x8    // Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_FULL_3_BB_K2                                                                          0x540ba0UL //Access:R    DataWidth:0x8    // Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_FULL_4_BB_K2                                                                          0x540ba4UL //Access:R    DataWidth:0x8    // Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_FULL_5_BB_K2                                                                          0x540ba8UL //Access:R    DataWidth:0x8    // Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_FULL_6_BB_K2                                                                          0x540bacUL //Access:R    DataWidth:0x8    // Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_FULL_7_BB_K2                                                                          0x540bb0UL //Access:R    DataWidth:0x8    // Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_FULL_8_BB_K2                                                                          0x540bb4UL //Access:R    DataWidth:0x8    // Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_FULL_9_BB_K2                                                                          0x540bb8UL //Access:R    DataWidth:0x8    // Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_STATUS_0                                                                              0x540bd0UL //Access:R    DataWidth:0x20   // Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_STATUS_1                                                                              0x540bd4UL //Access:R    DataWidth:0x20   // Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_STATUS_2                                                                              0x540bd8UL //Access:R    DataWidth:0x20   // Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_STATUS_3_BB_K2                                                                        0x540bdcUL //Access:R    DataWidth:0x20   // Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_STATUS_4_BB_K2                                                                        0x540be0UL //Access:R    DataWidth:0x20   // Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_STATUS_5_BB_K2                                                                        0x540be4UL //Access:R    DataWidth:0x20   // Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_STATUS_6_BB_K2                                                                        0x540be8UL //Access:R    DataWidth:0x20   // Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_STATUS_7_BB_K2                                                                        0x540becUL //Access:R    DataWidth:0x20   // Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_STATUS_8_BB_K2                                                                        0x540bf0UL //Access:R    DataWidth:0x20   // Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_PKT_STATUS_9_BB_K2                                                                        0x540bf4UL //Access:R    DataWidth:0x20   // Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.
+#define BMB_REG_RC_SOP_EMPTY                                                                                 0x540c0cUL //Access:R    DataWidth:0x4    // Debug register. Empty status of read SOP clients: {B2-req_fifo;  B1-dscr_fifo;  B0-queue_fifo}.
+#define BMB_REG_RC_SOP_FULL                                                                                  0x540c10UL //Access:R    DataWidth:0x4    // Debug register. Full status of read SOP clients: {B2-req_fifo;  B1-dscr_fifo;  B0-queue_fifo}.
+#define BMB_REG_RC_SOP_STATUS                                                                                0x540c14UL //Access:R    DataWidth:0x10   // Debug register. FIFO counters status of read SOP clients: {B11:8-req_fifo;  B7:4-dscr_fifo;  B3:0-queue_fifo}.
+#define BMB_REG_LL_ARB_EMPTY                                                                                 0x540c18UL //Access:R    DataWidth:0x3    // Debug register. Empty status of link list arbiter: {rls_fifo; prefetch_fifo}.
+#define BMB_REG_LL_ARB_FULL                                                                                  0x540c1cUL //Access:R    DataWidth:0x3    // Debug register. Full status of link list arbiter: {rls_fifo; prefetch_fifos}.
+#define BMB_REG_LL_ARB_STATUS                                                                                0x540c20UL //Access:R    DataWidth:0xe    // Debug register. FIFO counters status of link list arbiter: {rls_fifo[7:4]; prefetch_fifo_1[4:0], prefetch_fifo_0[4:0]}.
+#define BMB_REG_RC_SOP_PEND_FIFO_EMPTY_0                                                                     0x540c24UL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP pending FIFO for each client
+#define BMB_REG_RC_SOP_PEND_FIFO_EMPTY_1                                                                     0x540c28UL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP pending FIFO for each client
+#define BMB_REG_RC_SOP_PEND_FIFO_EMPTY_2                                                                     0x540c2cUL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP pending FIFO for each client
+#define BMB_REG_RC_SOP_PEND_FIFO_EMPTY_3                                                                     0x540c30UL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP pending FIFO for each client
+#define BMB_REG_RC_SOP_PEND_FIFO_EMPTY_4                                                                     0x540c34UL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP pending FIFO for each client
+#define BMB_REG_RC_SOP_PEND_FIFO_EMPTY_5                                                                     0x540c38UL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP pending FIFO for each client
+#define BMB_REG_RC_SOP_PEND_FIFO_EMPTY_6                                                                     0x540c3cUL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP pending FIFO for each client
+#define BMB_REG_RC_SOP_PEND_FIFO_EMPTY_7                                                                     0x540c40UL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP pending FIFO for each client
+#define BMB_REG_RC_SOP_PEND_FIFO_FULL_0                                                                      0x540c44UL //Access:R    DataWidth:0x1    // Debug register. This is full status of SOP pending FIFO for each client
+#define BMB_REG_RC_SOP_PEND_FIFO_FULL_1                                                                      0x540c48UL //Access:R    DataWidth:0x1    // Debug register. This is full status of SOP pending FIFO for each client
+#define BMB_REG_RC_SOP_PEND_FIFO_FULL_2                                                                      0x540c4cUL //Access:R    DataWidth:0x1    // Debug register. This is full status of SOP pending FIFO for each client
+#define BMB_REG_RC_SOP_PEND_FIFO_FULL_3                                                                      0x540c50UL //Access:R    DataWidth:0x1    // Debug register. This is full status of SOP pending FIFO for each client
+#define BMB_REG_RC_SOP_PEND_FIFO_FULL_4                                                                      0x540c54UL //Access:R    DataWidth:0x1    // Debug register. This is full status of SOP pending FIFO for each client
+#define BMB_REG_RC_SOP_PEND_FIFO_FULL_5                                                                      0x540c58UL //Access:R    DataWidth:0x1    // Debug register. This is full status of SOP pending FIFO for each client
+#define BMB_REG_RC_SOP_PEND_FIFO_FULL_6                                                                      0x540c5cUL //Access:R    DataWidth:0x1    // Debug register. This is full status of SOP pending FIFO for each client
+#define BMB_REG_RC_SOP_PEND_FIFO_FULL_7                                                                      0x540c60UL //Access:R    DataWidth:0x1    // Debug register. This is full status of SOP pending FIFO for each client
+#define BMB_REG_RC_SOP_PEND_FIFO_CNT_0                                                                       0x540c64UL //Access:R    DataWidth:0x2    // Debug register. This is status of SOP pending FIFO for each client
+#define BMB_REG_RC_SOP_PEND_FIFO_CNT_1                                                                       0x540c68UL //Access:R    DataWidth:0x2    // Debug register. This is status of SOP pending FIFO for each client
+#define BMB_REG_RC_SOP_PEND_FIFO_CNT_2                                                                       0x540c6cUL //Access:R    DataWidth:0x2    // Debug register. This is status of SOP pending FIFO for each client
+#define BMB_REG_RC_SOP_PEND_FIFO_CNT_3                                                                       0x540c70UL //Access:R    DataWidth:0x2    // Debug register. This is status of SOP pending FIFO for each client
+#define BMB_REG_RC_SOP_PEND_FIFO_CNT_4                                                                       0x540c74UL //Access:R    DataWidth:0x2    // Debug register. This is status of SOP pending FIFO for each client
+#define BMB_REG_RC_SOP_PEND_FIFO_CNT_5                                                                       0x540c78UL //Access:R    DataWidth:0x2    // Debug register. This is status of SOP pending FIFO for each client
+#define BMB_REG_RC_SOP_PEND_FIFO_CNT_6                                                                       0x540c7cUL //Access:R    DataWidth:0x2    // Debug register. This is status of SOP pending FIFO for each client
+#define BMB_REG_RC_SOP_PEND_FIFO_CNT_7                                                                       0x540c80UL //Access:R    DataWidth:0x2    // Debug register. This is status of SOP pending FIFO for each client
+#define BMB_REG_RC_DSCR_PEND_FIFO_EMPTY_0                                                                    0x540c84UL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP DSCR pending FIFO for each client
+#define BMB_REG_RC_DSCR_PEND_FIFO_EMPTY_1                                                                    0x540c88UL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP DSCR pending FIFO for each client
+#define BMB_REG_RC_DSCR_PEND_FIFO_EMPTY_2                                                                    0x540c8cUL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP DSCR pending FIFO for each client
+#define BMB_REG_RC_DSCR_PEND_FIFO_EMPTY_3                                                                    0x540c90UL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP DSCR pending FIFO for each client
+#define BMB_REG_RC_DSCR_PEND_FIFO_EMPTY_4                                                                    0x540c94UL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP DSCR pending FIFO for each client
+#define BMB_REG_RC_DSCR_PEND_FIFO_EMPTY_5                                                                    0x540c98UL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP DSCR pending FIFO for each client
+#define BMB_REG_RC_DSCR_PEND_FIFO_EMPTY_6                                                                    0x540c9cUL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP DSCR pending FIFO for each client
+#define BMB_REG_RC_DSCR_PEND_FIFO_EMPTY_7                                                                    0x540ca0UL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP DSCR pending FIFO for each client
+#define BMB_REG_RC_DSCR_PEND_FIFO_FULL_0                                                                     0x540ca4UL //Access:R    DataWidth:0x1    // Debug register. This is full status of SOP DSCR pending FIFO for each client
+#define BMB_REG_RC_DSCR_PEND_FIFO_FULL_1                                                                     0x540ca8UL //Access:R    DataWidth:0x1    // Debug register. This is full status of SOP DSCR pending FIFO for each client
+#define BMB_REG_RC_DSCR_PEND_FIFO_FULL_2                                                                     0x540cacUL //Access:R    DataWidth:0x1    // Debug register. This is full status of SOP DSCR pending FIFO for each client
+#define BMB_REG_RC_DSCR_PEND_FIFO_FULL_3                                                                     0x540cb0UL //Access:R    DataWidth:0x1    // Debug register. This is full status of SOP DSCR pending FIFO for each client
+#define BMB_REG_RC_DSCR_PEND_FIFO_FULL_4                                                                     0x540cb4UL //Access:R    DataWidth:0x1    // Debug register. This is full status of SOP DSCR pending FIFO for each client
+#define BMB_REG_RC_DSCR_PEND_FIFO_FULL_5                                                                     0x540cb8UL //Access:R    DataWidth:0x1    // Debug register. This is full status of SOP DSCR pending FIFO for each client
+#define BMB_REG_RC_DSCR_PEND_FIFO_FULL_6                                                                     0x540cbcUL //Access:R    DataWidth:0x1    // Debug register. This is full status of SOP DSCR pending FIFO for each client
+#define BMB_REG_RC_DSCR_PEND_FIFO_FULL_7                                                                     0x540cc0UL //Access:R    DataWidth:0x1    // Debug register. This is full status of SOP DSCR pending FIFO for each client
+#define BMB_REG_RC_DSCR_PEND_FIFO_CNT_0                                                                      0x540cc4UL //Access:R    DataWidth:0x2    // Debug register. This is status of SOP DSCR pending FIFO for each client
+#define BMB_REG_RC_DSCR_PEND_FIFO_CNT_1                                                                      0x540cc8UL //Access:R    DataWidth:0x2    // Debug register. This is status of SOP DSCR pending FIFO for each client
+#define BMB_REG_RC_DSCR_PEND_FIFO_CNT_2                                                                      0x540cccUL //Access:R    DataWidth:0x2    // Debug register. This is status of SOP DSCR pending FIFO for each client
+#define BMB_REG_RC_DSCR_PEND_FIFO_CNT_3                                                                      0x540cd0UL //Access:R    DataWidth:0x2    // Debug register. This is status of SOP DSCR pending FIFO for each client
+#define BMB_REG_RC_DSCR_PEND_FIFO_CNT_4                                                                      0x540cd4UL //Access:R    DataWidth:0x2    // Debug register. This is status of SOP DSCR pending FIFO for each client
+#define BMB_REG_RC_DSCR_PEND_FIFO_CNT_5                                                                      0x540cd8UL //Access:R    DataWidth:0x2    // Debug register. This is status of SOP DSCR pending FIFO for each client
+#define BMB_REG_RC_DSCR_PEND_FIFO_CNT_6                                                                      0x540cdcUL //Access:R    DataWidth:0x2    // Debug register. This is status of SOP DSCR pending FIFO for each client
+#define BMB_REG_RC_DSCR_PEND_FIFO_CNT_7                                                                      0x540ce0UL //Access:R    DataWidth:0x2    // Debug register. This is status of SOP DSCR pending FIFO for each client
+#define BMB_REG_RC_SOP_INP_SYNC_FIFO_POP_EMPTY_1_E5                                                          0x540ce4UL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP SYNC INP FIFO for client 1
+#define BMB_REG_RC_SOP_INP_SYNC_FIFO_POP_EMPTY_8_BB_K2                                                       0x540ce4UL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP SYNC INP FIFO for client 8
+#define BMB_REG_RC_SOP_INP_SYNC_FIFO_POP_EMPTY_2_E5                                                          0x540ce8UL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP SYNC INP FIFO for client 2
+#define BMB_REG_RC_SOP_INP_SYNC_FIFO_POP_EMPTY_9_BB_K2                                                       0x540ce8UL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP SYNC INP FIFO for client 9
+#define BMB_REG_RC_SOP_INP_SYNC_FIFO_PUSH_STATUS_1_E5                                                        0x540cecUL //Access:R    DataWidth:0x2    // Debug register. This is status of SOP SYNC INP FIFO for each client
+#define BMB_REG_RC_SOP_INP_SYNC_FIFO_PUSH_STATUS_8_BB_K2                                                     0x540cecUL //Access:R    DataWidth:0x2    // Debug register. This is status of SOP SYNC INP FIFO for each client
+#define BMB_REG_RC_SOP_INP_SYNC_FIFO_PUSH_STATUS_2_E5                                                        0x540cf0UL //Access:R    DataWidth:0x2    // Debug register. This is status of SOP SYNC INP FIFO for each client
+#define BMB_REG_RC_SOP_INP_SYNC_FIFO_PUSH_STATUS_9_BB_K2                                                     0x540cf0UL //Access:R    DataWidth:0x2    // Debug register. This is status of SOP SYNC INP FIFO for each client
+#define BMB_REG_RC_SOP_OUT_SYNC_FIFO_POP_EMPTY_1_E5                                                          0x540cf4UL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP SYNC out FIFO for client 1
+#define BMB_REG_RC_SOP_OUT_SYNC_FIFO_POP_EMPTY_8_BB_K2                                                       0x540cf4UL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP SYNC out FIFO for client 8
+#define BMB_REG_RC_SOP_OUT_SYNC_FIFO_POP_EMPTY_2_E5                                                          0x540cf8UL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP SYNC out FIFO for client 2
+#define BMB_REG_RC_SOP_OUT_SYNC_FIFO_POP_EMPTY_9_BB_K2                                                       0x540cf8UL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP SYNC out FIFO for client 9
+#define BMB_REG_RC_SOP_OUT_SYNC_FIFO_PUSH_STATUS_1_E5                                                        0x540cfcUL //Access:R    DataWidth:0x2    // Debug register. This is full status of SOP SYNC OUT FIFO for each client
+#define BMB_REG_RC_SOP_OUT_SYNC_FIFO_PUSH_STATUS_8_BB_K2                                                     0x540cfcUL //Access:R    DataWidth:0x2    // Debug register. This is full status of SOP SYNC OUT FIFO for each client
+#define BMB_REG_RC_SOP_OUT_SYNC_FIFO_PUSH_STATUS_2_E5                                                        0x540d00UL //Access:R    DataWidth:0x2    // Debug register. This is full status of SOP SYNC OUT FIFO for each client
+#define BMB_REG_RC_SOP_OUT_SYNC_FIFO_PUSH_STATUS_9_BB_K2                                                     0x540d00UL //Access:R    DataWidth:0x2    // Debug register. This is full status of SOP SYNC OUT FIFO for each client
+#define BMB_REG_RC_GNT_PEND_FIFO_EMPTY                                                                       0x540d04UL //Access:R    DataWidth:0x1    // Debug register. This is empty status of SOP grant FIFO
+#define BMB_REG_RC_GNT_PEND_FIFO_FULL                                                                        0x540d08UL //Access:R    DataWidth:0x1    // Debug register. This is full status of SOP grant FIFO
+#define BMB_REG_RC_GNT_PEND_FIFO_CNT                                                                         0x540d0cUL //Access:R    DataWidth:0x5    // Debug register. This is full status of SOP grant FIFO
+#define BMB_REG_RC_OUT_SYNC_FIFO_PUSH_STATUS_1_E5                                                            0x540d10UL //Access:R    DataWidth:0x5    // Debug register. This is full status of packet RC output SYNC FIFO
+#define BMB_REG_RC_OUT_SYNC_FIFO_PUSH_STATUS_8_BB_K2                                                         0x540d10UL //Access:R    DataWidth:0x5    // Debug register. This is full status of packet RC output SYNC FIFO
+#define BMB_REG_RC_OUT_SYNC_FIFO_PUSH_STATUS_2_E5                                                            0x540d14UL //Access:R    DataWidth:0x5    // Debug register. This is full status of packet RC output SYNC FIFO
+#define BMB_REG_RC_OUT_SYNC_FIFO_PUSH_STATUS_9_BB_K2                                                         0x540d14UL //Access:R    DataWidth:0x5    // Debug register. This is full status of packet RC output SYNC FIFO
+#define BMB_REG_WC_SYNC_FIFO_PUSH_STATUS_8                                                                   0x540d4cUL //Access:R    DataWidth:0x6    // Debug register. This is full status of WC SYNC FIFO
+#define BMB_REG_WC_SYNC_FIFO_PUSH_STATUS_9                                                                   0x540d50UL //Access:R    DataWidth:0x6    // Debug register. This is full status of WC SYNC FIFO
+#define BMB_REG_PKT_AVAIL_SYNC_FIFO_PUSH_STATUS                                                              0x540d88UL //Access:R    DataWidth:0x4    // Debug register. This is full status of packet available SYNC FIFO
+#define BMB_REG_RC_PKT_STATE                                                                                 0x540d8cUL //Access:R    DataWidth:0xc    // Debug register. This is state machine for each read client. ::s/PKT_RC_NUM_ST/20/g in Data Width.
+#define BMB_REG_RC_PKT_STATE_1_BB_K2                                                                         0x540d90UL //Access:R    DataWidth:0x8    // Debug register. This is state machine for each read client 8 and 9.
+#define BMB_REG_MAC_FREE_SHARED_HR_0                                                                         0x540d9cUL //Access:R    DataWidth:0xb    // Debug register. The number of free blocks for each MAC port that includes shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/SHARED_HR_RST/2112/g in Reset Value::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_OCCUPANCY_0                                                                               0x540db4UL //Access:R    DataWidth:0xb    // Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_OCCUPANCY_1                                                                               0x540db8UL //Access:R    DataWidth:0xb    // Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_OCCUPANCY_2                                                                               0x540dbcUL //Access:R    DataWidth:0xb    // Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_OCCUPANCY_3                                                                               0x540dc0UL //Access:R    DataWidth:0xb    // Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_OCCUPANCY_4                                                                               0x540dc4UL //Access:R    DataWidth:0xb    // Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_OCCUPANCY_5                                                                               0x540dc8UL //Access:R    DataWidth:0xb    // Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.
+#define BMB_REG_AVAILABLE_MAC_SIZE_0                                                                         0x540df4UL //Access:R    DataWidth:0xb    // Debug register. The available number of blocks for each MAC port that includes guaranteed and shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_PAUSE_0                                                                                   0x540e0cUL //Access:R    DataWidth:0x6    // Debug register. Output pause signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_TC_FULL_0                                                                                    0x540e24UL //Access:R    DataWidth:0x6    // Debug register. Output full signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.
+#define BMB_REG_BIG_RAM_DATA                                                                                 0x540f00UL //Access:WB   DataWidth:0x80   // Debug register. Data to BIG RAM memory. Write to 32 MSB bits of this register will generate write to BIG RAM according to address that is written in big_ram_address register. Read from 32 LSB bits of this register will generate read from BIG RAM according to address written in big_ram_address register.
+#define BMB_REG_BIG_RAM_DATA_SIZE                                                                            64
+#define BMB_REG_RC_SOP_QUEUE_STATUS                                                                          0x541000UL //Access:R    DataWidth:0x20   // Debug register. There is register for each queue of each write client. It contains: b31 - valid; b30:16 - queue size; b15:0 - queue start pointer::s/SOP_STATUS_RST/536805376/g in Reset Value::s/QUEUE_ARRAY/36/g in memory size::s/SOP_STATUS_WDTH/6/g in Address Width.
+#define BMB_REG_RC_SOP_QUEUE_STATUS_SIZE                                                                     90
+#define BMB_REG_STOPPED_RD_REQ                                                                               0x541200UL //Access:WB_R DataWidth:0x3f   // If there is length error of first block error then request from read client will be copied to this register for each erad packet client interface: TBD. Message spelling (MSB->LSB): rest_size_error[0]; len_error[0]; 1st_error[0]; middle_error[0]; rls_to_do[1:0]; start_block[12:0]; rd_req[0]; rls_req[0]; offset[9:0]; length[13:0]; opaque[15:0]
+#define BMB_REG_STOPPED_RD_REQ_SIZE_BB_K2                                                                    20
+#define BMB_REG_STOPPED_RD_REQ_SIZE_E5                                                                       6
+#define BMB_REG_STOPPED_RLS_REQ                                                                              0x541300UL //Access:WB_R DataWidth:0x4c   // If there is release error then request from read client will be copied to this register for each read packet client interface: TBD. Message spelling (MSB->LSB): opaque[1:0]; rls_to_do[15:0]; queue_number[3:0]; packet_length[13:0]; rls_left[1:0]; start_block[12:0]
+#define BMB_REG_STOPPED_RLS_REQ_SIZE_BB_K2                                                                   40
+#define BMB_REG_STOPPED_RLS_REQ_SIZE_E5                                                                      12
+#define BMB_REG_WC_STATUS_0                                                                                  0x541400UL //Access:WB_R DataWidth:0x5b   // Debug register. FIFO counters status of write clients. TBD: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
+#define BMB_REG_WC_STATUS_0_SIZE                                                                             4
+#define BMB_REG_WC_STATUS_1                                                                                  0x541410UL //Access:WB_R DataWidth:0x5b   // Debug register. FIFO counters status of write clients. TBD: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
+#define BMB_REG_WC_STATUS_1_SIZE                                                                             4
+#define BMB_REG_WC_STATUS_2                                                                                  0x541420UL //Access:WB_R DataWidth:0x5b   // Debug register. FIFO counters status of write clients. TBD: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
+#define BMB_REG_WC_STATUS_2_SIZE                                                                             4
+#define BMB_REG_WC_STATUS_3                                                                                  0x541430UL //Access:WB_R DataWidth:0x5b   // Debug register. FIFO counters status of write clients. TBD: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
+#define BMB_REG_WC_STATUS_3_SIZE                                                                             4
+#define BMB_REG_WC_STATUS_4                                                                                  0x541440UL //Access:WB_R DataWidth:0x5b   // Debug register. FIFO counters status of write clients. TBD: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
+#define BMB_REG_WC_STATUS_4_SIZE                                                                             4
+#define BMB_REG_WC_STATUS_5                                                                                  0x541450UL //Access:WB_R DataWidth:0x5b   // Debug register. FIFO counters status of write clients. TBD: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
+#define BMB_REG_WC_STATUS_5_SIZE                                                                             4
+#define BMB_REG_WC_STATUS_6                                                                                  0x541460UL //Access:WB_R DataWidth:0x5b   // Debug register. FIFO counters status of write clients. TBD: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
+#define BMB_REG_WC_STATUS_6_SIZE                                                                             4
+#define BMB_REG_WC_STATUS_7                                                                                  0x541470UL //Access:WB_R DataWidth:0x5b   // Debug register. FIFO counters status of write clients. TBD: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
+#define BMB_REG_WC_STATUS_7_SIZE                                                                             4
+#define BMB_REG_WC_STATUS_8                                                                                  0x541480UL //Access:WB_R DataWidth:0x5b   // Debug register. FIFO counters status of write clients. TBD: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
+#define BMB_REG_WC_STATUS_8_SIZE                                                                             4
+#define BMB_REG_WC_STATUS_9                                                                                  0x541490UL //Access:WB_R DataWidth:0x5b   // Debug register. FIFO counters status of write clients. TBD: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
+#define BMB_REG_WC_STATUS_9_SIZE                                                                             4
+#define BMB_REG_LINK_LIST                                                                                    0x542000UL //Access:RW   DataWidth:0xc    // Link list dual port memory that contains per-block descriptor::s/BLK_NUM/4800/g in memory size::s/BLK_WDTH_PLUS_SOP_EN/14/g in Data Width::s/BLK_WDTH/13/g in Address Width.
+#define BMB_REG_LINK_LIST_SIZE                                                                               1152
+#define PTU_REG_ATC_INIT_ARRAY                                                                               0x560000UL //Access:RW   DataWidth:0x1    // Initiate the ATC array - reset all the valid bits.
+#define PTU_REG_ATC_INIT_DONE                                                                                0x560004UL //Access:R    DataWidth:0x1    // ATC initalization done.
+#define PTU_REG_LOG_TRANSPEND_REUSE_MISS_TID                                                                 0x560040UL //Access:RC   DataWidth:0x20   // Logging register for reuse miss on transpend entry [31:0] - TID of the problematic request
+#define PTU_REG_LOG_TRANSPEND_REUSE_MISS_PAGE_INDEX                                                          0x560044UL //Access:RC   DataWidth:0x1c   // Logging register for reuse miss on transpend entry [27:0] - ATC page index of the problematic request
+#define PTU_REG_LOG_TRANSPEND_REUSE_MISS_REUSE_CNT                                                           0x560048UL //Access:RC   DataWidth:0x18   // Logging register for reuse miss on transpend entry [11:0] - Reuse count of the problematic lookuprequest [23:12] - Reuse count stored in the matched entry
+#define PTU_REG_LOG_INV_HALT_TID                                                                             0x56004cUL //Access:RC   DataWidth:0x20   // Logging register for the case of invalidation halt (lkpres of invalidated range) [31:0] - TID of the problematic request
+#define PTU_REG_LOG_INV_HALT_PAGE_INDEX                                                                      0x560050UL //Access:RC   DataWidth:0x1c   // Logging register for the case of invalidation halt (lkpres of invalidated range) [27:0] - ATC page index of the problematic request
+#define PTU_REG_LOG_INV_HALT_REUSE_CNT                                                                       0x560054UL //Access:RC   DataWidth:0xc    // Logging register for the case of invalidation halt (lkpres of invalidated range) [11:0] - Reuse count of the problematic lookuprequest
+#define PTU_REG_VQID_CFG                                                                                     0x560058UL //Access:RW   DataWidth:0x5    // VQID of the PXP read requests issued by the PTU logic.
+#define PTU_REG_TPH_CFG                                                                                      0x56005cUL //Access:RW   DataWidth:0xc    // TPH fileds of the PXP read requests issued by the PTU logic. [0:8] - ST index; [10:9] - ST hint; [11] - ST valid.
+#define PTU_REG_RO_CFG                                                                                       0x560060UL //Access:RW   DataWidth:0x1    // Releaxed Ordering flag of the PXP read requests issued by the PTU.
+#define PTU_REG_NS_CFG                                                                                       0x560064UL //Access:RW   DataWidth:0x1    // No Snoop flag of the PXP read requests issued by the PTU.
+#define PTU_REG_ATC_FLG_CFG                                                                                  0x560068UL //Access:RW   DataWidth:0x3    // ATC flags of the PXP read requests issued by the PTU logic.
+#define PTU_REG_PBL_PAGE_SIZE                                                                                0x56006cUL //Access:RW   DataWidth:0x5    // Page size in the PBL table, needed for calculating the address of the translation read request.
+#define PTU_REG_PXP_ERR_CTR                                                                                  0x560070UL //Access:RC   DataWidth:0x10   // Counter for the number of PTU read responses retunring with error flag set.
+#define PTU_REG_INV_ERR_CTR                                                                                  0x560074UL //Access:R    DataWidth:0x10   // Counter for the number of PTU requests to addresses belongs to ongoing invalidations.
+#define PTU_REG_INV_TID                                                                                      0x560078UL //Access:RW   DataWidth:0x20   // TID of the invalidated range - register per PF.
+#define PTU_REG_INV_TID_MASK                                                                                 0x56007cUL //Access:RW   DataWidth:0x20   // Bit mask for the invalidated TID. Shows which of the TID bits should be compared in the invalidation flow.
+#define PTU_REG_INV_TID_V                                                                                    0x560080UL //Access:RW   DataWidth:0x1    // Bit per PF.Indicates that the data in inv_tid and inv_tid_mask is valid and invalidation should take place. When invalidation operation is done, the corresponding bit in inv_tid_done is set
+#define PTU_REG_INV_TID_DONE                                                                                 0x560084UL //Access:RW   DataWidth:0x1    // Bit per PF. Indicates that the marked invalidation is done - when read it is also being reset.
+#define PTU_REG_INV_HALT_ON_ERR                                                                              0x560088UL //Access:RW   DataWidth:0x1    // Bit per PF. If set, the block halts in case it gets PTU requests to an address belongs to a range which is currently invalidated; if reset such requests will be sent towards the PXP with the PBLBase and discard flag (in case of PRM).
+#define PTU_REG_INV_HALT_ON_REUSE_CNT_ERR                                                                    0x56008cUL //Access:RW   DataWidth:0x1    // When set - the block will halt in case reuse cnt error is found, other wise the erronous request will be sent on with error indication
+#define PTU_REG_PBF_PXP_CREDITS                                                                              0x560090UL //Access:RW   DataWidth:0x3    // Max credits of the PBF->PXP interface.
+#define PTU_REG_PRM_PXP_CREDITS                                                                              0x560094UL //Access:RW   DataWidth:0x3    // Max credits of the PRM->PXP interface.
+#define PTU_REG_PTU_PXP_CREDITS                                                                              0x560098UL //Access:RW   DataWidth:0x3    // Max credits of the PTU->PXP interface.
+#define PTU_REG_PXP_1ST_REQ_ATC_CFG                                                                          0x56009cUL //Access:RW   DataWidth:0x3    // Max credits of the PTU->PXP interface.
+#define PTU_REG_PXP_2ND_REQ_ATC_CFG                                                                          0x5600a0UL //Access:RW   DataWidth:0x3    // Max credits of the PTU->PXP interface.
+#define PTU_REG_USE_CRC_INDEX1                                                                               0x5600a4UL //Access:RW   DataWidth:0x1    // CRC Index1 enable
+#define PTU_REG_USE_CRC_INDEX2                                                                               0x5600a8UL //Access:RW   DataWidth:0x1    // CRC Index2 enable
+#define PTU_REG_INDEX1_SHIFT                                                                                 0x5600acUL //Access:RW   DataWidth:0x5    // CRC Index1 shift right value
+#define PTU_REG_INDEX2_SHIFT                                                                                 0x5600b0UL //Access:RW   DataWidth:0x6    // CRC Index2 shift right value
+#define PTU_REG_INDEX3_SHIFT                                                                                 0x5600b4UL //Access:RW   DataWidth:0x5    // CRC Index3 shift right value
+#define PTU_REG_INDEX1_MASK                                                                                  0x5600b8UL //Access:RW   DataWidth:0x20   // CRC Index1 mask
+#define PTU_REG_INDEX2_MASK                                                                                  0x5600bcUL //Access:RW   DataWidth:0x20   // CRC Index2 mask
+#define PTU_REG_INDEX3_MASK                                                                                  0x5600c0UL //Access:RW   DataWidth:0x20   // CRC Index3 mask
+#define PTU_REG_ATC_REP_MODE                                                                                 0x5600c4UL //Access:RW   DataWidth:0x1    // Replacement mode for the ATC. If de-asserted then low priority request will replace a high priority entry only if there are no low priority entries at all. If set then a high priority with PLRU=0 will be replaced in higher priority than low priority entries with PLRU=1.
+#define PTU_REG_PBF_FILL_LEVEL                                                                               0x5600c8UL //Access:R    DataWidth:0x8    // Current number of pending pbf messages
+#define PTU_REG_PRM_FILL_LEVEL                                                                               0x5600ccUL //Access:R    DataWidth:0x8    // Current number of pending prm messages
+#define PTU_REG_PBF_FILL_LEVEL_MH                                                                            0x5600d0UL //Access:RC   DataWidth:0x8    // Maximal number of pending pbf messages
+#define PTU_REG_PRM_FILL_LEVEL_MH                                                                            0x5600d4UL //Access:RC   DataWidth:0x8    // Maximal number of pending prm messages
+#define PTU_REG_PTU_B0_DISABLE                                                                               0x5600d8UL //Access:RW   DataWidth:0x1    // Disable B0 feature
+#define PTU_REG_ATC_OTB_OVERRUN_FIX_CHICKEN_BIT_K2_E5                                                        0x5600dcUL //Access:RW   DataWidth:0x1    // Chicken bit for the atc otb overrun fix.
+#define PTU_REG_DBG_SELECT                                                                                   0x560100UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PTU_REG_DBG_DWORD_ENABLE                                                                             0x560104UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PTU_REG_DBG_SHIFT                                                                                    0x560108UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PTU_REG_DBG_FORCE_VALID                                                                              0x56010cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PTU_REG_DBG_FORCE_FRAME                                                                              0x560110UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PTU_REG_DBG_OUT_DATA                                                                                 0x560120UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PTU_REG_DBG_OUT_DATA_SIZE                                                                            8
+#define PTU_REG_DBG_OUT_VALID                                                                                0x560140UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define PTU_REG_DBG_OUT_FRAME                                                                                0x560144UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define PTU_REG_INT_STS                                                                                      0x560180UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define PTU_REG_INT_STS_ADDRESS_ERROR                                                                      (0x1<<0) // Signals an unknown address to the rf module.
+  #define PTU_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                                0
+  #define PTU_REG_INT_STS_ATC_TCPL_TO_NOT_PEND                                                               (0x1<<1) // TCPL arrives to an entry not in Trans-Pend state.
+  #define PTU_REG_INT_STS_ATC_TCPL_TO_NOT_PEND_SHIFT                                                         1
+  #define PTU_REG_INT_STS_ATC_GPA_MULTIPLE_HITS                                                              (0x1<<2) // Several hits in the GPA for the same lookup.
+  #define PTU_REG_INT_STS_ATC_GPA_MULTIPLE_HITS_SHIFT                                                        2
+  #define PTU_REG_INT_STS_ATC_RCPL_TO_EMPTY_CNT                                                              (0x1<<3) // RCPL arrives to an entry with empty R_Cnt.
+  #define PTU_REG_INT_STS_ATC_RCPL_TO_EMPTY_CNT_SHIFT                                                        3
+  #define PTU_REG_INT_STS_ATC_TCPL_ERROR                                                                     (0x1<<4) // Indicates TCPL response with error code set.
+  #define PTU_REG_INT_STS_ATC_TCPL_ERROR_SHIFT                                                               4
+  #define PTU_REG_INT_STS_ATC_INV_HALT                                                                       (0x1<<5) // Indicates Lookup to invalidated range with inv_halt_on_err set
+  #define PTU_REG_INT_STS_ATC_INV_HALT_SHIFT                                                                 5
+  #define PTU_REG_INT_STS_ATC_REUSE_TRANSPEND                                                                (0x1<<6) // Indicates Lookup to entry markes as transpend with reuse counter mismatch
+  #define PTU_REG_INT_STS_ATC_REUSE_TRANSPEND_SHIFT                                                          6
+  #define PTU_REG_INT_STS_ATC_IREQ_LESS_THAN_STU                                                             (0x1<<7) // Indicates Ireq with invalidation range shorter than STU of the relevant func.
+  #define PTU_REG_INT_STS_ATC_IREQ_LESS_THAN_STU_SHIFT                                                       7
+#define PTU_REG_INT_MASK                                                                                     0x560184UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PTU_REG_INT_MASK_ADDRESS_ERROR                                                                     (0x1<<0) // This bit masks, when set, the Interrupt bit: PTU_REG_INT_STS.ADDRESS_ERROR .
+  #define PTU_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                               0
+  #define PTU_REG_INT_MASK_ATC_TCPL_TO_NOT_PEND                                                              (0x1<<1) // This bit masks, when set, the Interrupt bit: PTU_REG_INT_STS.ATC_TCPL_TO_NOT_PEND .
+  #define PTU_REG_INT_MASK_ATC_TCPL_TO_NOT_PEND_SHIFT                                                        1
+  #define PTU_REG_INT_MASK_ATC_GPA_MULTIPLE_HITS                                                             (0x1<<2) // This bit masks, when set, the Interrupt bit: PTU_REG_INT_STS.ATC_GPA_MULTIPLE_HITS .
+  #define PTU_REG_INT_MASK_ATC_GPA_MULTIPLE_HITS_SHIFT                                                       2
+  #define PTU_REG_INT_MASK_ATC_RCPL_TO_EMPTY_CNT                                                             (0x1<<3) // This bit masks, when set, the Interrupt bit: PTU_REG_INT_STS.ATC_RCPL_TO_EMPTY_CNT .
+  #define PTU_REG_INT_MASK_ATC_RCPL_TO_EMPTY_CNT_SHIFT                                                       3
+  #define PTU_REG_INT_MASK_ATC_TCPL_ERROR                                                                    (0x1<<4) // This bit masks, when set, the Interrupt bit: PTU_REG_INT_STS.ATC_TCPL_ERROR .
+  #define PTU_REG_INT_MASK_ATC_TCPL_ERROR_SHIFT                                                              4
+  #define PTU_REG_INT_MASK_ATC_INV_HALT                                                                      (0x1<<5) // This bit masks, when set, the Interrupt bit: PTU_REG_INT_STS.ATC_INV_HALT .
+  #define PTU_REG_INT_MASK_ATC_INV_HALT_SHIFT                                                                5
+  #define PTU_REG_INT_MASK_ATC_REUSE_TRANSPEND                                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: PTU_REG_INT_STS.ATC_REUSE_TRANSPEND .
+  #define PTU_REG_INT_MASK_ATC_REUSE_TRANSPEND_SHIFT                                                         6
+  #define PTU_REG_INT_MASK_ATC_IREQ_LESS_THAN_STU                                                            (0x1<<7) // This bit masks, when set, the Interrupt bit: PTU_REG_INT_STS.ATC_IREQ_LESS_THAN_STU .
+  #define PTU_REG_INT_MASK_ATC_IREQ_LESS_THAN_STU_SHIFT                                                      7
+#define PTU_REG_INT_STS_WR                                                                                   0x560188UL //Access:WR   DataWidth:0x8    // Multi Field Register.
+  #define PTU_REG_INT_STS_WR_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define PTU_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                             0
+  #define PTU_REG_INT_STS_WR_ATC_TCPL_TO_NOT_PEND                                                            (0x1<<1) // TCPL arrives to an entry not in Trans-Pend state.
+  #define PTU_REG_INT_STS_WR_ATC_TCPL_TO_NOT_PEND_SHIFT                                                      1
+  #define PTU_REG_INT_STS_WR_ATC_GPA_MULTIPLE_HITS                                                           (0x1<<2) // Several hits in the GPA for the same lookup.
+  #define PTU_REG_INT_STS_WR_ATC_GPA_MULTIPLE_HITS_SHIFT                                                     2
+  #define PTU_REG_INT_STS_WR_ATC_RCPL_TO_EMPTY_CNT                                                           (0x1<<3) // RCPL arrives to an entry with empty R_Cnt.
+  #define PTU_REG_INT_STS_WR_ATC_RCPL_TO_EMPTY_CNT_SHIFT                                                     3
+  #define PTU_REG_INT_STS_WR_ATC_TCPL_ERROR                                                                  (0x1<<4) // Indicates TCPL response with error code set.
+  #define PTU_REG_INT_STS_WR_ATC_TCPL_ERROR_SHIFT                                                            4
+  #define PTU_REG_INT_STS_WR_ATC_INV_HALT                                                                    (0x1<<5) // Indicates Lookup to invalidated range with inv_halt_on_err set
+  #define PTU_REG_INT_STS_WR_ATC_INV_HALT_SHIFT                                                              5
+  #define PTU_REG_INT_STS_WR_ATC_REUSE_TRANSPEND                                                             (0x1<<6) // Indicates Lookup to entry markes as transpend with reuse counter mismatch
+  #define PTU_REG_INT_STS_WR_ATC_REUSE_TRANSPEND_SHIFT                                                       6
+  #define PTU_REG_INT_STS_WR_ATC_IREQ_LESS_THAN_STU                                                          (0x1<<7) // Indicates Ireq with invalidation range shorter than STU of the relevant func.
+  #define PTU_REG_INT_STS_WR_ATC_IREQ_LESS_THAN_STU_SHIFT                                                    7
+#define PTU_REG_INT_STS_CLR                                                                                  0x56018cUL //Access:RC   DataWidth:0x8    // Multi Field Register.
+  #define PTU_REG_INT_STS_CLR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define PTU_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                            0
+  #define PTU_REG_INT_STS_CLR_ATC_TCPL_TO_NOT_PEND                                                           (0x1<<1) // TCPL arrives to an entry not in Trans-Pend state.
+  #define PTU_REG_INT_STS_CLR_ATC_TCPL_TO_NOT_PEND_SHIFT                                                     1
+  #define PTU_REG_INT_STS_CLR_ATC_GPA_MULTIPLE_HITS                                                          (0x1<<2) // Several hits in the GPA for the same lookup.
+  #define PTU_REG_INT_STS_CLR_ATC_GPA_MULTIPLE_HITS_SHIFT                                                    2
+  #define PTU_REG_INT_STS_CLR_ATC_RCPL_TO_EMPTY_CNT                                                          (0x1<<3) // RCPL arrives to an entry with empty R_Cnt.
+  #define PTU_REG_INT_STS_CLR_ATC_RCPL_TO_EMPTY_CNT_SHIFT                                                    3
+  #define PTU_REG_INT_STS_CLR_ATC_TCPL_ERROR                                                                 (0x1<<4) // Indicates TCPL response with error code set.
+  #define PTU_REG_INT_STS_CLR_ATC_TCPL_ERROR_SHIFT                                                           4
+  #define PTU_REG_INT_STS_CLR_ATC_INV_HALT                                                                   (0x1<<5) // Indicates Lookup to invalidated range with inv_halt_on_err set
+  #define PTU_REG_INT_STS_CLR_ATC_INV_HALT_SHIFT                                                             5
+  #define PTU_REG_INT_STS_CLR_ATC_REUSE_TRANSPEND                                                            (0x1<<6) // Indicates Lookup to entry markes as transpend with reuse counter mismatch
+  #define PTU_REG_INT_STS_CLR_ATC_REUSE_TRANSPEND_SHIFT                                                      6
+  #define PTU_REG_INT_STS_CLR_ATC_IREQ_LESS_THAN_STU                                                         (0x1<<7) // Indicates Ireq with invalidation range shorter than STU of the relevant func.
+  #define PTU_REG_INT_STS_CLR_ATC_IREQ_LESS_THAN_STU_SHIFT                                                   7
+#define PTU_REG_PRTY_MASK_H_0_BB_K2                                                                          0x560204UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PTU_REG_PRTY_MASK_H_0_MEM017_I_ECC_RF_INT_BB_K2                                                    (0x1<<0) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM017_I_ECC_RF_INT .
+  #define PTU_REG_PRTY_MASK_H_0_MEM017_I_ECC_RF_INT_BB_K2_SHIFT                                              0
+  #define PTU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_K2                                                      (0x1<<1) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
+  #define PTU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_K2_SHIFT                                                1
+  #define PTU_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2                                                      (0x1<<2) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define PTU_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2_SHIFT                                                2
+  #define PTU_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                      (0x1<<3) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define PTU_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                                3
+  #define PTU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                      (0x1<<4) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define PTU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                                4
+  #define PTU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                      (0x1<<5) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define PTU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                                5
+  #define PTU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                      (0x1<<6) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define PTU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                                6
+  #define PTU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2                                                      (0x1<<7) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define PTU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT                                                7
+  #define PTU_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2                                                      (0x1<<8) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define PTU_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2_SHIFT                                                8
+  #define PTU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2                                                      (0x1<<9) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
+  #define PTU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2_SHIFT                                                9
+  #define PTU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_K2                                                      (0x1<<10) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
+  #define PTU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_K2_SHIFT                                                10
+  #define PTU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2                                                      (0x1<<11) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define PTU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2_SHIFT                                                11
+  #define PTU_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_K2                                                      (0x1<<12) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
+  #define PTU_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_K2_SHIFT                                                12
+  #define PTU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_K2                                                      (0x1<<13) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
+  #define PTU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_K2_SHIFT                                                13
+  #define PTU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_K2                                                      (0x1<<14) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
+  #define PTU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_K2_SHIFT                                                14
+  #define PTU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_K2                                                      (0x1<<15) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
+  #define PTU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_K2_SHIFT                                                15
+  #define PTU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_K2                                                      (0x1<<16) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
+  #define PTU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_K2_SHIFT                                                16
+  #define PTU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2                                                      (0x1<<17) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define PTU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2_SHIFT                                                17
+#define PTU_REG_MEM_ECC_ENABLE_0_BB_K2                                                                       0x560210UL //Access:RW   DataWidth:0x1    // Enable ECC for memory ecc instance ptu.i_ram_spa.i_ecc in module ptu_spa_ram
+#define PTU_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                  0x560214UL //Access:RW   DataWidth:0x1    // Set parity only for memory ecc instance ptu.i_ram_spa.i_ecc in module ptu_spa_ram
+#define PTU_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                              0x560218UL //Access:RC   DataWidth:0x1    // Record if a correctable error occurred on memory ecc instance ptu.i_ram_spa.i_ecc in module ptu_spa_ram
+#define PTU_REG_MEM_ECC_EVENTS_BB_K2                                                                         0x56021cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define PTU_REG_ATC_NUM_SETS                                                                                 0x560400UL //Access:RW   DataWidth:0x2    // Defines the number of sets - 3 - 512 ;2- 256; 1- 128; 0- 64.
+#define PTU_REG_ATC_1_WAY                                                                                    0x560404UL //Access:RW   DataWidth:0x1    // If set the ATC will use only one way per set.
+#define PTU_REG_ATC_FULL_REG                                                                                 0x560408UL //Access:R    DataWidth:0x8    // SPA Done FIFO full bit; RCPL FIFO full bit; TCPL FIFO full bit; IREQ full bit; PLKP FIFO full bit; MLKP FIFO full bit; OTB full bit; OIB full bit.
+#define PTU_REG_ATC_EMPTY_REG                                                                                0x56040cUL //Access:R    DataWidth:0x8    // SPA Done FIFO empty bit; RCPL FIFO empty bit; TCPL FIFO empty bit; IREQ empty bit; PLKP FIFO empty bit; MLKP FIFO empty bit; OTB empty bit; OIB empty bit.
+#define PTU_REG_ATC_WAIT_IF_MISS                                                                             0x560410UL //Access:RW   DataWidth:0x1    // WaitIfMiss configuration bit.
+#define PTU_REG_ATC_WAIT_IF_PENDING                                                                          0x560414UL //Access:RW   DataWidth:0x1    // WaitTransPending cofiguration bit.
+#define PTU_REG_ATC_STALL_SEQ_0                                                                              0x560418UL //Access:RW   DataWidth:0x6    // Indicates the B2B event sequnece which will cause stall (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction.
+#define PTU_REG_ATC_STALL_SEQ_1                                                                              0x56041cUL //Access:RW   DataWidth:0x6    // Indicates the B2B event sequnece which will cause stall (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction.
+#define PTU_REG_ATC_STALL_SEQ_2                                                                              0x560420UL //Access:RW   DataWidth:0x6    // Indicates the B2B event sequnece which will cause stall (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction.
+#define PTU_REG_ATC_STALL_SEQ_3                                                                              0x560424UL //Access:RW   DataWidth:0x6    // Indicates the B2B event sequnece which will cause stall (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction.
+#define PTU_REG_ATC_STALL_SEQ_4                                                                              0x560428UL //Access:RW   DataWidth:0x6    // Indicates the B2B event sequnece which will cause stall (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction.
+#define PTU_REG_ATC_STALL_SEQ_5                                                                              0x56042cUL //Access:RW   DataWidth:0x6    // Indicates the B2B event sequnece which will cause stall (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction.
+#define PTU_REG_ATC_SET_STALL_SEQ_0                                                                          0x560430UL //Access:RW   DataWidth:0x6    // Indicates the B2B event sequnece which will cause stall in case of 2 consecutive accesses to the same set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y to the same set; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction.
+#define PTU_REG_ATC_SET_STALL_SEQ_1                                                                          0x560434UL //Access:RW   DataWidth:0x6    // Indicates the B2B event sequnece which will cause stall in case of 2 consecutive accesses to the same set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y to the same set; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction.
+#define PTU_REG_ATC_SET_STALL_SEQ_2                                                                          0x560438UL //Access:RW   DataWidth:0x6    // Indicates the B2B event sequnece which will cause stall in case of 2 consecutive accesses to the same set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y to the same set; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction.
+#define PTU_REG_ATC_SET_STALL_SEQ_3                                                                          0x56043cUL //Access:RW   DataWidth:0x6    // Indicates the B2B event sequnece which will cause stall in case of 2 consecutive accesses to the same set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y to the same set; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction.
+#define PTU_REG_ATC_SET_STALL_SEQ_4                                                                          0x560440UL //Access:RW   DataWidth:0x6    // Indicates the B2B event sequnece which will cause stall in case of 2 consecutive accesses to the same set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y to the same set; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction.
+#define PTU_REG_ATC_SET_STALL_SEQ_5                                                                          0x560444UL //Access:RW   DataWidth:0x6    // Indicates the B2B event sequnece which will cause stall in case of 2 consecutive accesses to the same set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y to the same set; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction.
+#define PTU_REG_ATC_DISABLE_BYPASS                                                                           0x560448UL //Access:RW   DataWidth:0x1    // Disables the bypass on the GPA table.
+#define PTU_REG_ATC_ISSUE_4_CYCLES                                                                           0x56044cUL //Access:RW   DataWidth:0x1    // Issue event once in four cycles (instead of 2).
+#define PTU_REG_ATC_IREQ_FIFO_SIZE                                                                           0x560450UL //Access:RW   DataWidth:0x8    // Defines the size of the IREQ fifo.
+#define PTU_REG_ATC_IREQ_ALMOST_FULL_THR                                                                     0x560454UL //Access:RW   DataWidth:0x8    // Debug only: defines the IFIFO almost full threshold. Its size can't be bigger than the Ireq FIFO size. The full resp delay of the interface is 4. There is a problem with the implementation and the real value the FIFO can absorbe is 1 below the configured value, but 4 request still can be received when the register configured to 6
+#define PTU_REG_ATC_PIGGYBACKED_TREQ_EN                                                                      0x560458UL //Access:RW   DataWidth:0x1    // Piggybacked treq issue enabled.
+#define PTU_REG_ATC_WAIT_RESP                                                                                0x56045cUL //Access:RW   DataWidth:0x1    // Allows the ATC to return Wait response.
+#define PTU_REG_ATC_TREQ_CREDITS                                                                             0x560460UL //Access:RW   DataWidth:0x7    // Number of credits for the treq interface.
+#define PTU_REG_ATC_ARBITER_PRIO_MLKP                                                                        0x560464UL //Access:RW   DataWidth:0x2    // MLKP prio.
+#define PTU_REG_ATC_ARBITER_PRIO_PLKP                                                                        0x560468UL //Access:RW   DataWidth:0x2    // PLKP prio.
+#define PTU_REG_ATC_ARBITER_PRIO_IREQ                                                                        0x56046cUL //Access:RW   DataWidth:0x2    // IREQ prio.
+#define PTU_REG_ATC_ARBITER_PRIO_TCPL                                                                        0x560470UL //Access:RW   DataWidth:0x2    // TCPL prio.
+#define PTU_REG_ATC_ARBITER_PRIO_SPAD                                                                        0x560474UL //Access:RW   DataWidth:0x2    // SPAD prio.
+#define PTU_REG_ATC_ARBITER_PRIO_RCPL                                                                        0x560478UL //Access:RW   DataWidth:0x2    // RCPL prio.
+#define PTU_REG_ATC_OTB_MAX_ENTRY                                                                            0x56047cUL //Access:RW   DataWidth:0x7    // Defines the number of entries in the OTB when 31 indicates 32 entries (entries count begins in 0).
+#define PTU_REG_ATC_CHECK_TAGS                                                                               0x560480UL //Access:RW   DataWidth:0x1    // CheckTags configuration bit - when set the available NPH credits is checked before issuing TREQ.
+#define PTU_REG_ATC_TAG_THR                                                                                  0x560484UL //Access:RW   DataWidth:0x8    // TAG threshold - for the checkTags feature.
+#define PTU_REG_ATC_ICPL_CREDIT                                                                              0x560488UL //Access:RW   DataWidth:0x3    // Credit value for the ICPL interface.
+#define PTU_REG_ATC_DIS_MLKP                                                                                 0x56048cUL //Access:RW   DataWidth:0x1    // Disables the main lookup interface.
+#define PTU_REG_ATC_DIS_PLKP                                                                                 0x560490UL //Access:RW   DataWidth:0x1    // Disables the pre lookup interface.
+#define PTU_REG_ATC_DIS_IREQ                                                                                 0x560494UL //Access:RW   DataWidth:0x1    // Disables the invalidation request interface.
+#define PTU_REG_ATC_DIS_TCPL                                                                                 0x560498UL //Access:RW   DataWidth:0x1    // Disables the translation completion interface.
+#define PTU_REG_ATC_DIS_SPAD                                                                                 0x56049cUL //Access:RW   DataWidth:0x1    // Disables the spa done interface.
+#define PTU_REG_ATC_DIS_RCPL                                                                                 0x5604a0UL //Access:RW   DataWidth:0x1    // Disables the Read Completion interface.
+#define PTU_REG_ATC_DIS_LKPRES                                                                               0x5604a4UL //Access:RW   DataWidth:0x1    // Disables the lookup response interface.
+#define PTU_REG_ATC_DIS_TREQ                                                                                 0x5604a8UL //Access:RW   DataWidth:0x1    // Disables the translation request interface.
+#define PTU_REG_ATC_DIS_ICPL                                                                                 0x5604acUL //Access:RW   DataWidth:0x1    // Disables the invalidation completion interface.
+#define PTU_REG_ATC_SCRUB_CYC                                                                                0x5604b0UL //Access:RW   DataWidth:0x8    // Number of cycles between one scrub event to another.
+#define PTU_REG_ATC_SCRUB_DIS                                                                                0x5604b4UL //Access:RW   DataWidth:0x1    // Disable bit for the scrubbing event of the GPA table.
+#define PTU_REG_ATC_STAT_MLKP_HITS                                                                           0x5604b8UL //Access:RC   DataWidth:0x20   // Number of hits for Main-lookups in the ATC.
+#define PTU_REG_ATC_STAT_MLKP_NUM                                                                            0x5604bcUL //Access:RC   DataWidth:0x20   // Number of Main lookups in the ATC.
+#define PTU_REG_ATC_STAT_PLKP_TREQ                                                                           0x5604c0UL //Access:RC   DataWidth:0x20   // Number of treqs issued due to pre-lookup.
+#define PTU_REG_ATC_STAT_PLKP_NUM                                                                            0x5604c4UL //Access:RC   DataWidth:0x20   // Number of Pre Lookps in the ATC.
+#define PTU_REG_ATC_STAT_EVICT_NUM                                                                           0x5604c8UL //Access:RC   DataWidth:0x20   // Number of evictions out of the ATC.
+#define PTU_REG_ATC_STAT_INV_NUM                                                                             0x5604ccUL //Access:RC   DataWidth:0x20   // Number of invalidations handled by the ATC.
+#define PTU_REG_ATC_STAT_TREQ_NUM                                                                            0x5604d0UL //Access:RC   DataWidth:0x20   // Number of translation requests issued by the ATC.
+#define PTU_REG_ATC_STAT_ACTIVE                                                                              0x5604d4UL //Access:RW   DataWidth:0x1    // When this signal is set the statistics count is on.
+#define PTU_REG_ATC_STAT_USDM_LKP_NUM                                                                        0x5604d8UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_USDM_HIT_NUM                                                                        0x5604dcUL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_XSDM_LKP_NUM                                                                        0x5604e0UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_XSDM_HIT_NUM                                                                        0x5604e4UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_TSDM_LKP_NUM                                                                        0x5604e8UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_TSDM_HIT_NUM                                                                        0x5604ecUL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_PBF_LKP_NUM                                                                         0x5604f0UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_PBF_HIT_NUM                                                                         0x5604f4UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_QM_LKP_NUM                                                                          0x5604f8UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_QM_HIT_NUM                                                                          0x5604fcUL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_TM_LKP_NUM                                                                          0x560500UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_TM_HIT_NUM                                                                          0x560504UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_SRC_LKP_NUM                                                                         0x560508UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_SRC_HIT_NUM                                                                         0x56050cUL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_CDURD_LKP_NUM                                                                       0x560510UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_CDURD_HIT_NUM                                                                       0x560514UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_DMAE_LKP_NUM                                                                        0x560518UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_DMAE_HIT_NUM                                                                        0x56051cUL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_HC_LKP_NUM                                                                          0x560520UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_HC_HIT_NUM                                                                          0x560524UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_CDUWR_LKP_NUM                                                                       0x560528UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_CDUWR_HIT_NUM                                                                       0x56052cUL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_DBG_LKP_NUM                                                                         0x560530UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_DBG_HIT_NUM                                                                         0x560534UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_MSDM_LKP_NUM                                                                        0x560538UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_MSDM_HIT_NUM                                                                        0x56053cUL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_YSDM_LKP_NUM                                                                        0x560540UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_YSDM_HIT_NUM                                                                        0x560544UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_PSDM_LKP_NUM                                                                        0x560548UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_PSDM_HIT_NUM                                                                        0x56054cUL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_MULD_LKP_NUM                                                                        0x560550UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_MULD_HIT_NUM                                                                        0x560554UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_XYLD_LKP_NUM                                                                        0x560558UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_XYLD_HIT_NUM                                                                        0x56055cUL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_PRM_LKP_NUM                                                                         0x560560UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_STAT_PRM_HIT_NUM                                                                         0x560564UL //Access:RC   DataWidth:0x20   // Count lookups and hit for the different clients.
+#define PTU_REG_ATC_GPA_HASH_EN                                                                              0x560568UL //Access:RW   DataWidth:0x1    // Enable the use of a hash function for the GPA table; instead of the lsb bits of the address.
+#define PTU_REG_ATC_GPA_HASH_CRC                                                                             0x56056cUL //Access:RW   DataWidth:0x1    // Relevant only if hash_en is set. selects the CRC as hash function for the GPA table; If reset use xor of the FID LS bits with the relevant bits out of the GPA as hash function.
+#define PTU_REG_ATC_TCPL_LOG_ON_ERROR                                                                        0x560570UL //Access:RW   DataWidth:0x5    // In case of TCPL with error log the relevant data. The seperation for the different errors is: BME clear [0]; Unsupported request [1]; Completer abort/completion timeout [2]; Both R & W bits are reset [3]; Other [4].
+#define PTU_REG_ATC_TCPL_DIS_ON_ERROR                                                                        0x560574UL //Access:RW   DataWidth:0x5    // In case of TCPL with error disable the ATC.  The seperation for the different errors is: BME clear [0]; Unsupported request [1]; Completer abort/completion timeout [2]; Both R & W bits are reset [3]; Other [4].
+#define PTU_REG_ATC_TCPL_ERR_LOG                                                                             0x560578UL //Access:R    DataWidth:0x19   // Data belongs to an erroneous TCPL: [12:0] Func (VF_Valid;VFID;PFID);[13] U bit; [14] W bit; [15] R bit; [16] NS bit; [21:17] OTBEntryID;[24:22] Error code.
+#define PTU_REG_ATC_TCPL_ERR_ADDR_LSB                                                                        0x56057cUL //Access:R    DataWidth:0x20   // Data belongs to an erroneous TCPL: [31:0]-bits [31:0] of the address.
+#define PTU_REG_ATC_TCPL_ERR_ADDR_MSB                                                                        0x560580UL //Access:R    DataWidth:0x14   // Data belongs to an erroneous TCPL: [19:0]-bits [51:32] of the address.
+#define PTU_REG_ATC_TCPL_ERR_LOG_VALID                                                                       0x560584UL //Access:R    DataWidth:0x1    // Indicates valid data at the tcpl error log registers.
+#define PTU_REG_ATC_ARRAY_ACCESS_ENABLE                                                                      0x560588UL //Access:RW   DataWidth:0x1    // Allows GRC access to the GPA and SPA table.
+#define PTU_REG_ATC_DURING_FLI                                                                               0x56058cUL //Access:R    DataWidth:0x1    // Indication that the ATC currently handles FLI.
+#define PTU_REG_ATC_DURING_INV                                                                               0x560590UL //Access:R    DataWidth:0x1    // Indication that the ATC currently handles Any type of invalidation.
+#define PTU_REG_ATC_FLI_DONE_VF_31_0_BB_K2                                                                   0x560594UL //Access:R    DataWidth:0x20   // Indicates the end of FLI flow for VF 31-0.
+#define PTU_REG_ATC_FLI_DONE_VF_63_32_BB_K2                                                                  0x560598UL //Access:R    DataWidth:0x20   // Indicates the end of FLI flow for VF 63-32.
+#define PTU_REG_ATC_FLI_DONE_VF_95_64_BB_K2                                                                  0x56059cUL //Access:R    DataWidth:0x20   // Indicates the end of FLI flow for VF 95-64.
+#define PTU_REG_ATC_FLI_DONE_VF_127_96_BB_K2                                                                 0x5605a0UL //Access:R    DataWidth:0x20   // Indicates the end of FLI flow for VF 127-96.
+#define PTU_REG_ATC_FLI_DONE_VF_159_128_BB_K2                                                                0x5605a4UL //Access:R    DataWidth:0x20   // Indicates the end of FLI flow for VF 159-128.
+#define PTU_REG_ATC_FLI_DONE_VF_191_160_BB_K2                                                                0x5605a8UL //Access:R    DataWidth:0x20   // Indicates the end of FLI flow for VF 191-160.
+#define PTU_REG_ATC_FLI_DONE_PF_15_0_BB_K2                                                                   0x5605acUL //Access:R    DataWidth:0x10   // Indicates the end of FLI flow for PF 15-0.
+#define PTU_REG_ATC_FLI_DONE_CLR_VF_31_0_BB_K2                                                               0x5605b0UL //Access:RW   DataWidth:0x20   // Clears the FLI done indication for VF bits 31-0 accordingly.
+#define PTU_REG_ATC_FLI_DONE_CLR_VF_63_32_BB_K2                                                              0x5605b4UL //Access:RW   DataWidth:0x20   // Clears the FLI done indication for VFbits 63-32 accordingly.
+#define PTU_REG_ATC_FLI_DONE_CLR_VF_95_64_BB_K2                                                              0x5605b8UL //Access:RW   DataWidth:0x20   // Clears the FLI done indication for VF bits 95-64 accordingly.
+#define PTU_REG_ATC_FLI_DONE_CLR_VF_127_96_BB_K2                                                             0x5605bcUL //Access:RW   DataWidth:0x20   // Clears the FLI done indication for VFbits 127-96 accordingly.
+#define PTU_REG_ATC_FLI_DONE_CLR_VF_159_128_BB_K2                                                            0x5605c0UL //Access:RW   DataWidth:0x20   // Clears the FLI done indication for VF bits 159-128 accordingly.
+#define PTU_REG_ATC_FLI_DONE_CLR_VF_191_160_BB_K2                                                            0x5605c4UL //Access:RW   DataWidth:0x20   // Clears the FLI done indication for VFbits 191-160 accordingly.
+#define PTU_REG_ATC_FLI_DONE_CLR_PF_15_0_BB_K2                                                               0x5605c8UL //Access:RW   DataWidth:0x10   // Clears the FLI done indication for PF bits 15-0 accordingly.
+#define PTU_REG_DBGSYN_ALMOST_FULL_THR                                                                       0x5605ccUL //Access:RW   DataWidth:0x4    // Debug only: If more than this Number of entries are occupied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed. Its value can't be bigger than the set dbg FIFO size.
+#define PTU_REG_ATC_ALLOW_LOW_REP_HIGH                                                                       0x5605d0UL //Access:RW   DataWidth:0x1    // When set low priority lookup can replace high priority entry; iff the set is full with high prio entries.
+#define PTU_REG_ATC_DIS_IREQ_EVENT                                                                           0x5605d4UL //Access:RW   DataWidth:0x1    // When set Ireq event won't be selected by the ATC arbiter.
+#define PTU_REG_ATC_ECO_RESERVED                                                                             0x5605d8UL //Access:RW   DataWidth:0x1    // For future ECOs implementation.
+#define PTU_REG_ATC_TM                                                                                       0x5605dcUL //Access:RW   DataWidth:0x1e   // Multi Field Register.
+  #define PTU_REG_ATC_TM_ATC_SPA_TABLE_TM                                                                    (0x1f<<0) // TM bits of SPA table.
+  #define PTU_REG_ATC_TM_ATC_SPA_TABLE_TM_SHIFT                                                              0
+  #define PTU_REG_ATC_TM_ATC_GPA_DATA_W0_TM                                                                  (0x1f<<5) // TM bits of GPA data Way0.
+  #define PTU_REG_ATC_TM_ATC_GPA_DATA_W0_TM_SHIFT                                                            5
+  #define PTU_REG_ATC_TM_ATC_GPA_DATA_W1_TM                                                                  (0x1f<<10) // TM bits of GPA data Way1.
+  #define PTU_REG_ATC_TM_ATC_GPA_DATA_W1_TM_SHIFT                                                            10
+  #define PTU_REG_ATC_TM_ATC_GPA_DATA_W2_TM                                                                  (0x1f<<15) // TM bits of GPA data Way2.
+  #define PTU_REG_ATC_TM_ATC_GPA_DATA_W2_TM_SHIFT                                                            15
+  #define PTU_REG_ATC_TM_ATC_GPA_DATA_W3_TM                                                                  (0x1f<<20) // TM bits of GPA data Way3.
+  #define PTU_REG_ATC_TM_ATC_GPA_DATA_W3_TM_SHIFT                                                            20
+  #define PTU_REG_ATC_TM_ATC_GPA_STATE_TM                                                                    (0x1f<<25) // TM bits of GPA state array.
+  #define PTU_REG_ATC_TM_ATC_GPA_STATE_TM_SHIFT                                                              25
+#define PTU_REG_ATC_IREQ_FIFO_TM                                                                             0x5605e0UL //Access:RW   DataWidth:0x8    // TM bits of GPA state array.
+#define PTU_REG_INV_RSC_TYPE_E5                                                                              0x5605e4UL //Access:RW   DataWidth:0x8    // Resource Type of the invalidated range - register per PF.
+#define PTU_REG_INV_RSC_TYPE_MASK_E5                                                                         0x5605e8UL //Access:RW   DataWidth:0x8    // Bit mask for the invalidated RSC Type. Shows which of the RSC Type bits should be compared in the invalidation flow.
+#define PTU_REG_LOG_INV_HALT_RSC_TYPE_E5                                                                     0x5605ecUL //Access:R    DataWidth:0x8    // Logging register for the case of invalidation halt (lkpres of invalidated range)    [7:0] - Resource type of the problematic request
+#define PTU_REG_LOG_INV_HALT_PAGE_INDEX_MSB_E5                                                               0x5605f0UL //Access:R    DataWidth:0x8    // Logging register for the case of invalidation halt (lkpres of invalidated range)    bits [35:28] of the problematic request page index
+#define PTU_REG_LOG_TRANSPEND_REUSE_MISS_RSC_TYPE_E5                                                         0x5605f4UL //Access:R    DataWidth:0x8    // Logging register for reuse miss on transpend entry    bits [35:28] - of the problematic request page index
+#define PTU_REG_LOG_TRANSPEND_REUSE_MISS_PAGE_INDEX_MSB_E5                                                   0x5605f8UL //Access:R    DataWidth:0x8    // Logging register for reuse miss on transpend entry    [7:0] - Resource type of the problematic request
+#define PTU_REG_INDEX2_RSC_TYPE_MASK_E5                                                                      0x5605fcUL //Access:RW   DataWidth:0x8    // CRC Index2 resource type mask
+#define PTU_REG_GP_INV_TID_E5                                                                                0x560600UL //Access:RW   DataWidth:0x20   // TID of the invalidated range - register per Strom.
+#define PTU_REG_GP_INV_TID_SIZE                                                                              6
+#define PTU_REG_GP_INV_TID_MASK_E5                                                                           0x560620UL //Access:RW   DataWidth:0x20   // Bit mask for the invalidated TID. Shows which of the TID bits should be compared in the invalidation flow.
+#define PTU_REG_GP_INV_TID_MASK_SIZE                                                                         6
+#define PTU_REG_GP_INV_RSC_TYPE_E5                                                                           0x560640UL //Access:RW   DataWidth:0x8    // TID of the invalidated range - register per Storm.
+#define PTU_REG_GP_INV_RSC_TYPE_SIZE                                                                         6
+#define PTU_REG_GP_INV_RSC_TYPE_MASK_E5                                                                      0x560660UL //Access:RW   DataWidth:0x8    // Bit mask for the invalidated TID. Shows which of the TID bits should be compared in the invalidation flow.
+#define PTU_REG_GP_INV_RSC_TYPE_MASK_SIZE                                                                    6
+#define PTU_REG_GP_INV_TID_V_E5                                                                              0x560680UL //Access:RW   DataWidth:0x1    // Bit per Storm. Indicates that the data in inv_tid and inv_tid_mask is valid and invalidation should take place. When invalidation operation is done, the corresponding bit in inv_tid_done is set
+#define PTU_REG_GP_INV_TID_V_SIZE                                                                            6
+#define PTU_REG_GP_INV_TID_DONE_E5                                                                           0x5606a0UL //Access:RW   DataWidth:0x1    // Bit per Storm. Indicates that the marked invalidation is done - when read it is also being reset.
+#define PTU_REG_GP_INV_TID_DONE_SIZE                                                                         6
+#define PTU_REG_GP_INV_HALT_ON_ERR_E5                                                                        0x5606c0UL //Access:RW   DataWidth:0x1    // Bit per PF. If set, the block halts in case it gets PTU requests to an address belongs to a range which is currently invalidated; if reset such requests will be sent towards the PXP with the PBLBase and discard flag (in case of PRM).
+#define PTU_REG_GP_INV_HALT_ON_ERR_SIZE                                                                      6
+#define PTU_REG_ATC_GPA_ARRAY_ACCESS_W0_BB_K2                                                                0x560800UL //Access:WB   DataWidth:0x40   // Access the GPA table way 0; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:0]-[63:61].
+#define PTU_REG_ATC_GPA_ARRAY_ACCESS_W0_SIZE                                                                 512
+#define PTU_REG_ATC_GPA_ARRAY_ACCESS_W1_BB_K2                                                                0x561000UL //Access:WB   DataWidth:0x40   // Access the GPA table way 1; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:0]-[63:60].
+#define PTU_REG_ATC_GPA_ARRAY_ACCESS_W1_SIZE                                                                 512
+#define PTU_REG_ATC_GPA_ARRAY_ACCESS_W2_BB_K2                                                                0x561800UL //Access:WB   DataWidth:0x40   // Access the GPA table way 2; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:0]-[63:61].
+#define PTU_REG_ATC_GPA_ARRAY_ACCESS_W2_SIZE                                                                 512
+#define PTU_REG_ATC_SPA_ARRAY_ACCESS_BB_K2                                                                   0x562000UL //Access:WB   DataWidth:0x34   // Debug access to the SPA array.
+#define PTU_REG_ATC_SPA_ARRAY_ACCESS_SIZE                                                                    2048
+#define PTU_REG_ATC_GPA_ARRAY_ACCESS_W3_BB_K2                                                                0x564000UL //Access:WB   DataWidth:0x40   // Access the GPA table way3; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID-[63:61].
+#define PTU_REG_ATC_GPA_ARRAY_ACCESS_W3_SIZE                                                                 512
+#define PTU_REG_ATC_GPA_ARRAY_ACCESS_STATE_BB_K2                                                             0x564800UL //Access:WB   DataWidth:0x14   // Access the state fields of the GPA table; format is: W3 - {par - [51]; NS bit - [50]; W bit - [49]; R bit - [48]; U bit - [47]; Priority bit - [46]; PLRU - [45];  R-counter - [44:42]; transpend bit - [41]; invpend bit [40]; valid bit[39]}; W2 - {par - [38]; NS bit - [37]; W bit - [36]; R bit - [35]; U bit - [34]; Priority bit - [33]; PLRU - [32];  R-counter - [31:29]; transpend bit - [28]; invpend bit [27]; valid bit[26]}; W1 -  {par - [25]; NS bit - [24]; W bit - [23]; R bit - [22]; U bit - [21]; Priority bit - [20]; PLRU - [19];  R-counter - [18:16]; transpend bit - [15]; invpend bit [14]; valid bit[13]}; W0 -  {par - [12]; NS bit - [11]; W bit - [10]; R bit - [9]; U bit - [8]; Priority bit - [7]; PLRU - [6];  R-counter - [5:3]; transpend bit - [2]; invpend bit [1]; valid bit[0]}.
+#define PTU_REG_ATC_GPA_ARRAY_ACCESS_STATE_SIZE                                                              256
+#define PTU_REG_ATC_GPA_MEM_ACCESS_W0_E5                                                                     0x566000UL //Access:WB   DataWidth:0x58   // Access the GPA table way 0; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 88:52 - page index
+#define PTU_REG_ATC_GPA_MEM_ACCESS_W0_SIZE                                                                   2048
+#define PTU_REG_ATC_GPA_MEM_ACCESS_W1_E5                                                                     0x568000UL //Access:WB   DataWidth:0x58   // Access the GPA table way 1; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 88:52 - page index
+#define PTU_REG_ATC_GPA_MEM_ACCESS_W1_SIZE                                                                   2048
+#define PTU_REG_ATC_GPA_MEM_ACCESS_W2_E5                                                                     0x56a000UL //Access:WB   DataWidth:0x58   // Access the GPA table way 2; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 88:52 - page index
+#define PTU_REG_ATC_GPA_MEM_ACCESS_W2_SIZE                                                                   2048
+#define PTU_REG_ATC_GPA_MEM_ACCESS_W3_E5                                                                     0x56c000UL //Access:WB   DataWidth:0x58   // Access the GPA table way3; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 88:52 - page index
+#define PTU_REG_ATC_GPA_MEM_ACCESS_W3_SIZE                                                                   2048
+#define PTU_REG_ATC_GPA_MEM_ACCESS_STATE_E5                                                                  0x56e000UL //Access:WB   DataWidth:0x18   // Access the state fields of the GPA table; format is: W3 - { Priority bit - [23]; PLRU - [22]; Err bit - [21]; invpend bit [20]; transpend bit - [19]; valid bit[18]}; W2 - { Priority bit - [17]; PLRU - [16]; Err bit - [15]; invpend bit [14]; transpend bit - [13]; valid bit[12]}; W1 - { Priority bit - [11]; PLRU - [10]; Err bit - [9]; invpend bit [8]; transpend bit - [7]; valid bit[6]}; W0 - { Priority bit - [5]; PLRU - [4]; Err bit - [3]; invpend bit [2]; transpend bit - [1]; valid bit[0]}
+#define PTU_REG_ATC_GPA_MEM_ACCESS_STATE_SIZE                                                                512
+#define PTU_REG_ATC_SPA_MEM_ACCESS_E5                                                                        0x570000UL //Access:WB   DataWidth:0x34   // Debug access to the SPA array.
+#define PTU_REG_ATC_SPA_MEM_ACCESS_SIZE                                                                      4096
+#define CDU_REG_CONTROL0                                                                                     0x580040UL //Access:RW   DataWidth:0x7    // Multi Field Register.
+  #define CDU_REG_CONTROL0_ENABLE_PXP                                                                        (0x1<<0) // Enables PXP Accesses.
+  #define CDU_REG_CONTROL0_ENABLE_PXP_SHIFT                                                                  0
+  #define CDU_REG_CONTROL0_ENABLE_INPUTS                                                                     (0x1<<1) // Enables CDU Inputs -- Must be set for normal operation.
+  #define CDU_REG_CONTROL0_ENABLE_INPUTS_SHIFT                                                               1
+  #define CDU_REG_CONTROL0_ENABLE_OUTPUTS                                                                    (0x1<<2) // Enables CDU Outputs --  Must be set for normal operation.
+  #define CDU_REG_CONTROL0_ENABLE_OUTPUTS_SHIFT                                                              2
+  #define CDU_REG_CONTROL0_L1TT_SP                                                                           (0x1<<3) // Sets the L1TT Arbiter to Strict Priority;  This causes the WB Controller to always have priority over the LD Controller.
+  #define CDU_REG_CONTROL0_L1TT_SP_SHIFT                                                                     3
+  #define CDU_REG_CONTROL0_MATT_SP                                                                           (0x1<<4) // Sets the MATT Arbiter to Strict Priority;  This causes the WB Controller to always have priority over the LD Controller.
+  #define CDU_REG_CONTROL0_MATT_SP_SHIFT                                                                     4
+  #define CDU_REG_CONTROL0_PXP_SP                                                                            (0x1<<5) // Sets the PXP Arbiter to Strict Priority;  This causes the WB Controller to always have priority over the LD Controller.
+  #define CDU_REG_CONTROL0_PXP_SP_SHIFT                                                                      5
+  #define CDU_REG_CONTROL0_MASK_PCIE_ERR                                                                     (0x1<<6) // Masks all PCIE Errors for Load transactions.         NOTE -- This is not connected in E4 A0.
+  #define CDU_REG_CONTROL0_MASK_PCIE_ERR_SHIFT                                                               6
+#define CDU_REG_INT_STS                                                                                      0x5801c0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define CDU_REG_INT_STS_ADDRESS_ERROR                                                                      (0x1<<0) // Signals an unknown address to the rf module.
+  #define CDU_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                                0
+  #define CDU_REG_INT_STS_CCFC_LD_L1_NUM_ERROR                                                               (0x1<<1) // Number of L1s within a CCFC Load Request exceeds total number of L1s allowed. Error data is logged in the ccfc_ld_l1_num_error_data register.
+  #define CDU_REG_INT_STS_CCFC_LD_L1_NUM_ERROR_SHIFT                                                         1
+  #define CDU_REG_INT_STS_TCFC_LD_L1_NUM_ERROR                                                               (0x1<<2) // Number of L1s within a TCFC Load Request exceeds total number of L1s allowed. Error data is logged in the tcfc_ld_l1_num_error_data register.
+  #define CDU_REG_INT_STS_TCFC_LD_L1_NUM_ERROR_SHIFT                                                         2
+  #define CDU_REG_INT_STS_CCFC_WB_L1_NUM_ERROR                                                               (0x1<<3) // Number of L1s within a CCFC WriteBack Request exceeds total number of L1s allowed. Error data is logged in the ccfc_wb_l1_num_error_data register.
+  #define CDU_REG_INT_STS_CCFC_WB_L1_NUM_ERROR_SHIFT                                                         3
+  #define CDU_REG_INT_STS_TCFC_WB_L1_NUM_ERROR                                                               (0x1<<4) // Number of L1s within a TCFC WriteBack Request exceeds total number of L1s allowed. Error data is logged in the tcfc_wb_l1_num_error_data register.
+  #define CDU_REG_INT_STS_TCFC_WB_L1_NUM_ERROR_SHIFT                                                         4
+  #define CDU_REG_INT_STS_CCFC_CVLD_ERROR                                                                    (0x1<<5) // Context or Active Validation error in CCFC Load Datapath. Error data is logged in the ccfc_cvld_error_data register.
+  #define CDU_REG_INT_STS_CCFC_CVLD_ERROR_SHIFT                                                              5
+  #define CDU_REG_INT_STS_TCFC_CVLD_ERROR                                                                    (0x1<<6) // Context or Active Validation error in CCFC Load Datapath. Error data is logged in the ccfc_cvld_error_data register.
+  #define CDU_REG_INT_STS_TCFC_CVLD_ERROR_SHIFT                                                              6
+  #define CDU_REG_INT_STS_BVALID_ERROR                                                                       (0x1<<7) // Byte valid Error on PXP Interface.  All transactions should be either 8 or 16 bytes, so pxp_bvalid[2:0] should always be 3'b000.
+  #define CDU_REG_INT_STS_BVALID_ERROR_SHIFT                                                                 7
+#define CDU_REG_INT_STS_CLR                                                                                  0x5801c4UL //Access:RC   DataWidth:0x8    // Multi Field Register.
+  #define CDU_REG_INT_STS_CLR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define CDU_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                            0
+  #define CDU_REG_INT_STS_CLR_CCFC_LD_L1_NUM_ERROR                                                           (0x1<<1) // Number of L1s within a CCFC Load Request exceeds total number of L1s allowed. Error data is logged in the ccfc_ld_l1_num_error_data register.
+  #define CDU_REG_INT_STS_CLR_CCFC_LD_L1_NUM_ERROR_SHIFT                                                     1
+  #define CDU_REG_INT_STS_CLR_TCFC_LD_L1_NUM_ERROR                                                           (0x1<<2) // Number of L1s within a TCFC Load Request exceeds total number of L1s allowed. Error data is logged in the tcfc_ld_l1_num_error_data register.
+  #define CDU_REG_INT_STS_CLR_TCFC_LD_L1_NUM_ERROR_SHIFT                                                     2
+  #define CDU_REG_INT_STS_CLR_CCFC_WB_L1_NUM_ERROR                                                           (0x1<<3) // Number of L1s within a CCFC WriteBack Request exceeds total number of L1s allowed. Error data is logged in the ccfc_wb_l1_num_error_data register.
+  #define CDU_REG_INT_STS_CLR_CCFC_WB_L1_NUM_ERROR_SHIFT                                                     3
+  #define CDU_REG_INT_STS_CLR_TCFC_WB_L1_NUM_ERROR                                                           (0x1<<4) // Number of L1s within a TCFC WriteBack Request exceeds total number of L1s allowed. Error data is logged in the tcfc_wb_l1_num_error_data register.
+  #define CDU_REG_INT_STS_CLR_TCFC_WB_L1_NUM_ERROR_SHIFT                                                     4
+  #define CDU_REG_INT_STS_CLR_CCFC_CVLD_ERROR                                                                (0x1<<5) // Context or Active Validation error in CCFC Load Datapath. Error data is logged in the ccfc_cvld_error_data register.
+  #define CDU_REG_INT_STS_CLR_CCFC_CVLD_ERROR_SHIFT                                                          5
+  #define CDU_REG_INT_STS_CLR_TCFC_CVLD_ERROR                                                                (0x1<<6) // Context or Active Validation error in CCFC Load Datapath. Error data is logged in the ccfc_cvld_error_data register.
+  #define CDU_REG_INT_STS_CLR_TCFC_CVLD_ERROR_SHIFT                                                          6
+  #define CDU_REG_INT_STS_CLR_BVALID_ERROR                                                                   (0x1<<7) // Byte valid Error on PXP Interface.  All transactions should be either 8 or 16 bytes, so pxp_bvalid[2:0] should always be 3'b000.
+  #define CDU_REG_INT_STS_CLR_BVALID_ERROR_SHIFT                                                             7
+#define CDU_REG_INT_STS_WR                                                                                   0x5801c8UL //Access:WR   DataWidth:0x8    // Multi Field Register.
+  #define CDU_REG_INT_STS_WR_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define CDU_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                             0
+  #define CDU_REG_INT_STS_WR_CCFC_LD_L1_NUM_ERROR                                                            (0x1<<1) // Number of L1s within a CCFC Load Request exceeds total number of L1s allowed. Error data is logged in the ccfc_ld_l1_num_error_data register.
+  #define CDU_REG_INT_STS_WR_CCFC_LD_L1_NUM_ERROR_SHIFT                                                      1
+  #define CDU_REG_INT_STS_WR_TCFC_LD_L1_NUM_ERROR                                                            (0x1<<2) // Number of L1s within a TCFC Load Request exceeds total number of L1s allowed. Error data is logged in the tcfc_ld_l1_num_error_data register.
+  #define CDU_REG_INT_STS_WR_TCFC_LD_L1_NUM_ERROR_SHIFT                                                      2
+  #define CDU_REG_INT_STS_WR_CCFC_WB_L1_NUM_ERROR                                                            (0x1<<3) // Number of L1s within a CCFC WriteBack Request exceeds total number of L1s allowed. Error data is logged in the ccfc_wb_l1_num_error_data register.
+  #define CDU_REG_INT_STS_WR_CCFC_WB_L1_NUM_ERROR_SHIFT                                                      3
+  #define CDU_REG_INT_STS_WR_TCFC_WB_L1_NUM_ERROR                                                            (0x1<<4) // Number of L1s within a TCFC WriteBack Request exceeds total number of L1s allowed. Error data is logged in the tcfc_wb_l1_num_error_data register.
+  #define CDU_REG_INT_STS_WR_TCFC_WB_L1_NUM_ERROR_SHIFT                                                      4
+  #define CDU_REG_INT_STS_WR_CCFC_CVLD_ERROR                                                                 (0x1<<5) // Context or Active Validation error in CCFC Load Datapath. Error data is logged in the ccfc_cvld_error_data register.
+  #define CDU_REG_INT_STS_WR_CCFC_CVLD_ERROR_SHIFT                                                           5
+  #define CDU_REG_INT_STS_WR_TCFC_CVLD_ERROR                                                                 (0x1<<6) // Context or Active Validation error in CCFC Load Datapath. Error data is logged in the ccfc_cvld_error_data register.
+  #define CDU_REG_INT_STS_WR_TCFC_CVLD_ERROR_SHIFT                                                           6
+  #define CDU_REG_INT_STS_WR_BVALID_ERROR                                                                    (0x1<<7) // Byte valid Error on PXP Interface.  All transactions should be either 8 or 16 bytes, so pxp_bvalid[2:0] should always be 3'b000.
+  #define CDU_REG_INT_STS_WR_BVALID_ERROR_SHIFT                                                              7
+#define CDU_REG_INT_MASK                                                                                     0x5801ccUL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define CDU_REG_INT_MASK_ADDRESS_ERROR                                                                     (0x1<<0) // This bit masks, when set, the Interrupt bit: CDU_REG_INT_STS.ADDRESS_ERROR .
+  #define CDU_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                               0
+  #define CDU_REG_INT_MASK_CCFC_LD_L1_NUM_ERROR                                                              (0x1<<1) // This bit masks, when set, the Interrupt bit: CDU_REG_INT_STS.CCFC_LD_L1_NUM_ERROR .
+  #define CDU_REG_INT_MASK_CCFC_LD_L1_NUM_ERROR_SHIFT                                                        1
+  #define CDU_REG_INT_MASK_TCFC_LD_L1_NUM_ERROR                                                              (0x1<<2) // This bit masks, when set, the Interrupt bit: CDU_REG_INT_STS.TCFC_LD_L1_NUM_ERROR .
+  #define CDU_REG_INT_MASK_TCFC_LD_L1_NUM_ERROR_SHIFT                                                        2
+  #define CDU_REG_INT_MASK_CCFC_WB_L1_NUM_ERROR                                                              (0x1<<3) // This bit masks, when set, the Interrupt bit: CDU_REG_INT_STS.CCFC_WB_L1_NUM_ERROR .
+  #define CDU_REG_INT_MASK_CCFC_WB_L1_NUM_ERROR_SHIFT                                                        3
+  #define CDU_REG_INT_MASK_TCFC_WB_L1_NUM_ERROR                                                              (0x1<<4) // This bit masks, when set, the Interrupt bit: CDU_REG_INT_STS.TCFC_WB_L1_NUM_ERROR .
+  #define CDU_REG_INT_MASK_TCFC_WB_L1_NUM_ERROR_SHIFT                                                        4
+  #define CDU_REG_INT_MASK_CCFC_CVLD_ERROR                                                                   (0x1<<5) // This bit masks, when set, the Interrupt bit: CDU_REG_INT_STS.CCFC_CVLD_ERROR .
+  #define CDU_REG_INT_MASK_CCFC_CVLD_ERROR_SHIFT                                                             5
+  #define CDU_REG_INT_MASK_TCFC_CVLD_ERROR                                                                   (0x1<<6) // This bit masks, when set, the Interrupt bit: CDU_REG_INT_STS.TCFC_CVLD_ERROR .
+  #define CDU_REG_INT_MASK_TCFC_CVLD_ERROR_SHIFT                                                             6
+  #define CDU_REG_INT_MASK_BVALID_ERROR                                                                      (0x1<<7) // This bit masks, when set, the Interrupt bit: CDU_REG_INT_STS.BVALID_ERROR .
+  #define CDU_REG_INT_MASK_BVALID_ERROR_SHIFT                                                                7
+#define CDU_REG_PRTY_MASK_H_0_BB_K2                                                                          0x580204UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define CDU_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                      (0x1<<0) // This bit masks, when set, the Parity bit: CDU_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define CDU_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                                0
+  #define CDU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                      (0x1<<1) // This bit masks, when set, the Parity bit: CDU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define CDU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                                1
+  #define CDU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                      (0x1<<2) // This bit masks, when set, the Parity bit: CDU_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define CDU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                                2
+  #define CDU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2                                                      (0x1<<3) // This bit masks, when set, the Parity bit: CDU_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define CDU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT                                                3
+  #define CDU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                      (0x1<<4) // This bit masks, when set, the Parity bit: CDU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define CDU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                                4
+#define CDU_REG_MEM_ECC_EVENTS_BB_K2                                                                         0x580210UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define CDU_REG_CCFC_CTX_VALID0                                                                              0x580400UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define CDU_REG_CCFC_CTX_VALID0_CHECK_EN0_CCFC                                                             (0xff<<0) // CCFC Conxtext Validation for Region0 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
+  #define CDU_REG_CCFC_CTX_VALID0_CHECK_EN0_CCFC_SHIFT                                                       0
+  #define CDU_REG_CCFC_CTX_VALID0_CHECK_EN1_CCFC                                                             (0xff<<8) // CCFC Conxtext Validation for Region1 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
+  #define CDU_REG_CCFC_CTX_VALID0_CHECK_EN1_CCFC_SHIFT                                                       8
+  #define CDU_REG_CCFC_CTX_VALID0_CHECK_EN2_CCFC                                                             (0xff<<16) // CCFC Conxtext Validation for Region2 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
+  #define CDU_REG_CCFC_CTX_VALID0_CHECK_EN2_CCFC_SHIFT                                                       16
+  #define CDU_REG_CCFC_CTX_VALID0_CHECK_EN3_CCFC                                                             (0xff<<24) // CCFC Conxtext Validation for Region3 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
+  #define CDU_REG_CCFC_CTX_VALID0_CHECK_EN3_CCFC_SHIFT                                                       24
+#define CDU_REG_CCFC_CTX_VALID1                                                                              0x580404UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define CDU_REG_CCFC_CTX_VALID1_CHECK_EN4_CCFC                                                             (0xff<<0) // CCFC Conxtext Validation for Region4 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
+  #define CDU_REG_CCFC_CTX_VALID1_CHECK_EN4_CCFC_SHIFT                                                       0
+  #define CDU_REG_CCFC_CTX_VALID1_CHECK_EN5_CCFC                                                             (0xff<<8) // CCFC Conxtext Validation for Region5 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
+  #define CDU_REG_CCFC_CTX_VALID1_CHECK_EN5_CCFC_SHIFT                                                       8
+  #define CDU_REG_CCFC_CTX_VALID1_CHECK_EN6_CCFC                                                             (0xff<<16) // CCFC Conxtext Validation for Region6 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
+  #define CDU_REG_CCFC_CTX_VALID1_CHECK_EN6_CCFC_SHIFT                                                       16
+  #define CDU_REG_CCFC_CTX_VALID1_CHECK_EN7_CCFC                                                             (0xff<<24) // CCFC Conxtext Validation for Region7 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
+  #define CDU_REG_CCFC_CTX_VALID1_CHECK_EN7_CCFC_SHIFT                                                       24
+#define CDU_REG_TCFC_CTX_VALID0                                                                              0x580408UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define CDU_REG_TCFC_CTX_VALID0_CHECK_EN0_TCFC                                                             (0xff<<0) // TCFC Conxtext Validation for Region0 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
+  #define CDU_REG_TCFC_CTX_VALID0_CHECK_EN0_TCFC_SHIFT                                                       0
+  #define CDU_REG_TCFC_CTX_VALID0_CHECK_EN1_TCFC                                                             (0xff<<8) // TCFC Conxtext Validation for Region1 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
+  #define CDU_REG_TCFC_CTX_VALID0_CHECK_EN1_TCFC_SHIFT                                                       8
+  #define CDU_REG_TCFC_CTX_VALID0_CHECK_EN2_TCFC                                                             (0xff<<16) // TCFC Conxtext Validation for Region2 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
+  #define CDU_REG_TCFC_CTX_VALID0_CHECK_EN2_TCFC_SHIFT                                                       16
+  #define CDU_REG_TCFC_CTX_VALID0_CHECK_EN3_TCFC                                                             (0xff<<24) // TCFC Conxtext Validation for Region3 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
+  #define CDU_REG_TCFC_CTX_VALID0_CHECK_EN3_TCFC_SHIFT                                                       24
+#define CDU_REG_TCFC_CTX_VALID1                                                                              0x58040cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define CDU_REG_TCFC_CTX_VALID1_CHECK_EN4_TCFC                                                             (0xff<<0) // TCFC Conxtext Validation for Region4 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
+  #define CDU_REG_TCFC_CTX_VALID1_CHECK_EN4_TCFC_SHIFT                                                       0
+  #define CDU_REG_TCFC_CTX_VALID1_CHECK_EN5_TCFC                                                             (0xff<<8) // TCFC Conxtext Validation for Region5 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
+  #define CDU_REG_TCFC_CTX_VALID1_CHECK_EN5_TCFC_SHIFT                                                       8
+  #define CDU_REG_TCFC_CTX_VALID1_CHECK_EN6_TCFC                                                             (0xff<<16) // TCFC Conxtext Validation for Region6 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
+  #define CDU_REG_TCFC_CTX_VALID1_CHECK_EN6_TCFC_SHIFT                                                       16
+  #define CDU_REG_TCFC_CTX_VALID1_CHECK_EN7_TCFC                                                             (0xff<<24) // TCFC Conxtext Validation for Region7 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
+  #define CDU_REG_TCFC_CTX_VALID1_CHECK_EN7_TCFC_SHIFT                                                       24
+#define CDU_REG_LDBUF_AF_THRESH                                                                              0x580500UL //Access:RW   DataWidth:0x4    // Almost Full Threshold on Load Datapath;  Controls the Full signal to PXP. This register must never be set higher than 8 -- doing so will result in FIFO overflows due to the Reponse time from the PXP lock.
+#define CDU_REG_WBBUF_AF_THRESH                                                                              0x580504UL //Access:RW   DataWidth:0x4    // Almost Full Threshold on Writeback Datapath;  Stops Reading L1 Memories when past this limit. This register must never be set higher than 13 -- doing so will result in data corruption to the PXP due to FIFO overflow.
+#define CDU_REG_CCFC_PXP                                                                                     0x580600UL //Access:RW   DataWidth:0x15   // Multi Field Register.
+  #define CDU_REG_CCFC_PXP_CCFC_ATC_FLAGS_WB                                                                 (0x7<<0) // ATC Flags Field for CCFC PXP Writes.
+  #define CDU_REG_CCFC_PXP_CCFC_ATC_FLAGS_WB_SHIFT                                                           0
+  #define CDU_REG_CCFC_PXP_CCFC_ATC_FLAGS_LD                                                                 (0x7<<3) // ATC Flags Field for CCFC PXP Reads.
+  #define CDU_REG_CCFC_PXP_CCFC_ATC_FLAGS_LD_SHIFT                                                           3
+  #define CDU_REG_CCFC_PXP_RESERVED_4                                                                        (0x3ff<<6) // Reserved Bits.
+  #define CDU_REG_CCFC_PXP_RESERVED_4_SHIFT                                                                  6
+  #define CDU_REG_CCFC_PXP_CCFC_TPH_VALID                                                                    (0x1<<16) // TPH Valid bit for CCFC PXP Requests.
+  #define CDU_REG_CCFC_PXP_CCFC_TPH_VALID_SHIFT                                                              16
+  #define CDU_REG_CCFC_PXP_CCFC_RO_LD                                                                        (0x1<<17) // Relaxed ordering bit for CCFC PXP rd_req.
+  #define CDU_REG_CCFC_PXP_CCFC_RO_LD_SHIFT                                                                  17
+  #define CDU_REG_CCFC_PXP_CCFC_RO_WB                                                                        (0x1<<18) // Relaxed ordering bit for CCFC PXP wr_req.
+  #define CDU_REG_CCFC_PXP_CCFC_RO_WB_SHIFT                                                                  18
+  #define CDU_REG_CCFC_PXP_CCFC_NS_LD                                                                        (0x1<<19) // No snoop bit for CCFC PXP rd_req.
+  #define CDU_REG_CCFC_PXP_CCFC_NS_LD_SHIFT                                                                  19
+  #define CDU_REG_CCFC_PXP_CCFC_NS_WB                                                                        (0x1<<20) // No snoop bit for CCFC PXP wr_req.
+  #define CDU_REG_CCFC_PXP_CCFC_NS_WB_SHIFT                                                                  20
+#define CDU_REG_TCFC_PXP                                                                                     0x580604UL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define CDU_REG_TCFC_PXP_TCFC_ATC_FLAGS_WB                                                                 (0x7<<0) // ATC Flags Field for TCFC PXP Writes.
+  #define CDU_REG_TCFC_PXP_TCFC_ATC_FLAGS_WB_SHIFT                                                           0
+  #define CDU_REG_TCFC_PXP_TCFC_ATC_FLAGS_LD                                                                 (0x7<<3) // ATC Flags Field for TCFC PXP Reads.
+  #define CDU_REG_TCFC_PXP_TCFC_ATC_FLAGS_LD_SHIFT                                                           3
+  #define CDU_REG_TCFC_PXP_RESERVED_5                                                                        (0x3ff<<6) // Reserved Bits.
+  #define CDU_REG_TCFC_PXP_RESERVED_5_SHIFT                                                                  6
+  #define CDU_REG_TCFC_PXP_TCFC_TPH_VALID                                                                    (0x1<<16) // TPH Valid bit for TCFC PXP Requests.
+  #define CDU_REG_TCFC_PXP_TCFC_TPH_VALID_SHIFT                                                              16
+  #define CDU_REG_TCFC_PXP_TCFC_RO_LD                                                                        (0x1<<17) // Relaxed ordering bit for TCFC working memory PXP rd_req.
+  #define CDU_REG_TCFC_PXP_TCFC_RO_LD_SHIFT                                                                  17
+  #define CDU_REG_TCFC_PXP_TCFC_FL_RO_LD                                                                     (0x1<<18) // Relaxed ordering bit for TCFC init memory PXP rd_req.
+  #define CDU_REG_TCFC_PXP_TCFC_FL_RO_LD_SHIFT                                                               18
+  #define CDU_REG_TCFC_PXP_TCFC_RO_WB                                                                        (0x1<<19) // Relaxed ordering bit for TCFC working memory PXP wr_req.
+  #define CDU_REG_TCFC_PXP_TCFC_RO_WB_SHIFT                                                                  19
+  #define CDU_REG_TCFC_PXP_TCFC_NS_LD                                                                        (0x1<<20) // No snoop bit for TCFC working memory PXP rd_req.
+  #define CDU_REG_TCFC_PXP_TCFC_NS_LD_SHIFT                                                                  20
+  #define CDU_REG_TCFC_PXP_TCFC_FL_NS_LD                                                                     (0x1<<21) // No snoop bit for TCFC init memory PXP rd_req.
+  #define CDU_REG_TCFC_PXP_TCFC_FL_NS_LD_SHIFT                                                               21
+  #define CDU_REG_TCFC_PXP_TCFC_NS_WB                                                                        (0x1<<22) // No snoop bit for TCFC working memory PXP wr_req.
+  #define CDU_REG_TCFC_PXP_TCFC_NS_WB_SHIFT                                                                  22
+#define CDU_REG_LD_VQID                                                                                      0x580608UL //Access:RW   DataWidth:0x5    // VQID used for PXP Read (Load) transactions.
+#define CDU_REG_WB_VQID                                                                                      0x58060cUL //Access:RW   DataWidth:0x5    // VQID used for PXP Write (WriteBack) transactions.
+#define CDU_REG_DEBUG                                                                                        0x580700UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define CDU_REG_DEBUG_DISABLE_MERGE                                                                        (0x1<<0) // Disables Merge Functionality.
+  #define CDU_REG_DEBUG_DISABLE_MERGE_SHIFT                                                                  0
+  #define CDU_REG_DEBUG_RESERVED_1                                                                           (0x7fff<<1) // Reserved Bits.
+  #define CDU_REG_DEBUG_RESERVED_1_SHIFT                                                                     1
+  #define CDU_REG_DEBUG_PXP_INIT_LDCREDIT                                                                    (0x3<<16) // PXP Read Request Credits.
+  #define CDU_REG_DEBUG_PXP_INIT_LDCREDIT_SHIFT                                                              16
+  #define CDU_REG_DEBUG_RESERVED_2                                                                           (0x1f<<18) // Reserved Bits.
+  #define CDU_REG_DEBUG_RESERVED_2_SHIFT                                                                     18
+  #define CDU_REG_DEBUG_PXP_INIT_LDCREDIT_SET                                                                (0x1<<23) // Uses pxp_init_ldcredit to update PXP Read Credits.
+  #define CDU_REG_DEBUG_PXP_INIT_LDCREDIT_SET_SHIFT                                                          23
+  #define CDU_REG_DEBUG_PXP_INIT_WBCREDIT                                                                    (0x3<<24) // PXP Write Request Credits.
+  #define CDU_REG_DEBUG_PXP_INIT_WBCREDIT_SHIFT                                                              24
+  #define CDU_REG_DEBUG_RESERVED_3                                                                           (0x1f<<26) // Reserved Bits.
+  #define CDU_REG_DEBUG_RESERVED_3_SHIFT                                                                     26
+  #define CDU_REG_DEBUG_PXP_INIT_WBCREDIT_SET                                                                (0x1<<31) // Uses pxp_init_wbcredit to update PXP Write Credits.
+  #define CDU_REG_DEBUG_PXP_INIT_WBCREDIT_SET_SHIFT                                                          31
+#define CDU_REG_DBG_SELECT                                                                                   0x580704UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define CDU_REG_DBG_DWORD_ENABLE                                                                             0x580708UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define CDU_REG_DBG_SHIFT                                                                                    0x58070cUL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define CDU_REG_DBG_FORCE_VALID                                                                              0x580710UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define CDU_REG_DBG_FORCE_FRAME                                                                              0x580714UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define CDU_REG_DBG_OUT_DATA                                                                                 0x580720UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define CDU_REG_DBG_OUT_DATA_SIZE                                                                            8
+#define CDU_REG_DBG_OUT_VALID                                                                                0x580740UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define CDU_REG_DBG_OUT_FRAME                                                                                0x580744UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define CDU_REG_ECO_RESERVED                                                                                 0x580748UL //Access:RW   DataWidth:0x8    // Eco reserved register.
+#define CDU_REG_MEMCTRL_WR_RD_N_BB                                                                           0x58074cUL //Access:RW   DataWidth:0x1    // wr/rd indication to CPU BIST
+#define CDU_REG_MEMCTRL_CMD_BB                                                                               0x580750UL //Access:RW   DataWidth:0x8    // command to CPU BIST
+#define CDU_REG_MEMCTRL_ADDRESS_BB                                                                           0x580754UL //Access:RW   DataWidth:0x8    // address to CPU BIST
+#define CDU_REG_MEMCTRL_STATUS_BB                                                                            0x580758UL //Access:R    DataWidth:0x20   // status from CPU BIST
+#define CDU_REG_CCFC_CVLD_ERROR_DATA                                                                         0x580800UL //Access:R    DataWidth:0x19   // CCFC Context Validation Error Data. [24:16] LCID of Error Transaction [14:8]  Expected Compressed Context [6:0]   Received Compressed Context
+#define CDU_REG_TCFC_CVLD_ERROR_DATA                                                                         0x580804UL //Access:R    DataWidth:0x19   // TCFC Context Validation Error Data. [24:16] LCID of Error Transaction [14:8]  Expected Compressed Context [6:0]   Received Compressed Context
+#define CDU_REG_CCFC_LD_L1_NUM_ERROR_DATA                                                                    0x580808UL //Access:R    DataWidth:0x19   // Logging of error data in case of a CCFC Load error. [24:16]  LCID [11:8]   Type [7:0]    Regions
+#define CDU_REG_TCFC_LD_L1_NUM_ERROR_DATA                                                                    0x58080cUL //Access:R    DataWidth:0x19   // Logging of error data in case of a TCFC Load error. [24:16]  LCID [11:8]   Type [7:0]    Regions
+#define CDU_REG_CCFC_WB_L1_NUM_ERROR_DATA                                                                    0x580810UL //Access:R    DataWidth:0x19   // Logging of error data in case of a CCFC Writeback Error. [24:16]  LCID [11:8]   Type [7:0]    Regions
+#define CDU_REG_TCFC_WB_L1_NUM_ERROR_DATA                                                                    0x580814UL //Access:R    DataWidth:0x19   // Logging of error data in case of a TCFC Writeback Error. [24:16]  LCID [11:8]   Type [7:0]    Regions
+#define CDU_REG_CID_ADDR_PARAMS                                                                              0x580900UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE                                                               (0xfff<<0) // Global context size of a CID.
+  #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT                                                         0
+  #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE                                                                (0xfff<<12) // Block waste within a page. this number equals to PageSize-NCIB*ContextSize.
+  #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT                                                          12
+  #define CDU_REG_CID_ADDR_PARAMS_NCIB                                                                       (0xff<<24) // Number of CIDs in Block.
+  #define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT                                                                 24
+#define CDU_REG_SEGMENT0_PARAMS                                                                              0x580904UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK                                                       (0xfff<<0) // Number of TIDs per Block for this Segment (Type0).
+  #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT                                                 0
+  #define CDU_REG_SEGMENT0_PARAMS_RESERVED_6                                                                 (0xf<<12) // Reserved Bits.
+  #define CDU_REG_SEGMENT0_PARAMS_RESERVED_6_SHIFT                                                           12
+  #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE                                                         (0xff<<16) // Number of Waste locations per TID Block (in Qwords) (Type0).
+  #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT                                                   16
+  #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE                                                                (0xff<<24) // Size of TID (in Qwords) (Type0).
+  #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT                                                          24
+#define CDU_REG_SEGMENT1_PARAMS                                                                              0x580908UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK                                                       (0xfff<<0) // Number of TIDs per Block for this Segment (Type1).
+  #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT                                                 0
+  #define CDU_REG_SEGMENT1_PARAMS_RESERVED_7                                                                 (0xf<<12) // Reserved Bits.
+  #define CDU_REG_SEGMENT1_PARAMS_RESERVED_7_SHIFT                                                           12
+  #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE                                                         (0xff<<16) // Number of Waste locations per TID Block (in Qwords) (Type1).
+  #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT                                                   16
+  #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE                                                                (0xff<<24) // Size of TID (in Qwords) (Type1).
+  #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT                                                          24
+#define CDU_REG_PF_SEG0_TYPE_OFFSET                                                                          0x58090cUL //Access:RW   DataWidth:0x12   // Start Offset for this Segment (in 32KB pages).
+#define CDU_REG_PF_SEG1_TYPE_OFFSET                                                                          0x580910UL //Access:RW   DataWidth:0x12   // Start Offset for this Segment (in 32KB pages).
+#define CDU_REG_PF_SEG2_TYPE_OFFSET                                                                          0x580914UL //Access:RW   DataWidth:0x12   // Start Offset for this Segment (in 32KB pages).
+#define CDU_REG_PF_SEG3_TYPE_OFFSET                                                                          0x580918UL //Access:RW   DataWidth:0x12   // Start Offset for this Segment (in 32KB pages).
+#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET                                                                       0x58091cUL //Access:RW   DataWidth:0x12   // Force Load Start Offset for this Segment (in 32KB pages).
+#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET                                                                       0x580920UL //Access:RW   DataWidth:0x12   // Force Load Start Offset for this Segment (in 32KB pages).
+#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET                                                                       0x580924UL //Access:RW   DataWidth:0x12   // Force Load Start Offset for this Segment (in 32KB pages).
+#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET                                                                       0x580928UL //Access:RW   DataWidth:0x12   // Force Load Start Offset for this Segment (in 32KB pages).
+#define CDU_REG_VF_SEG_TYPE_OFFSET                                                                           0x58092cUL //Access:RW   DataWidth:0x12   // VF Start Offset for this Segment (in 32KB pages).
+#define CDU_REG_VF_FL_SEG_TYPE_OFFSET                                                                        0x580930UL //Access:RW   DataWidth:0xd    // VF Force Load Start Offset for this Segment (in 32KB pages).
+#define CDU_REG_TCFC_L1TT                                                                                    0x582000UL //Access:WB   DataWidth:0x110  // L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*[4:0]}.
+#define CDU_REG_TCFC_L1TT_SIZE                                                                               1024
+#define CDU_REG_TCFC_MATT                                                                                    0x583100UL //Access:WB   DataWidth:0x18   // MATT Access; Each entry has the following format: {RegionLength[11:0]; RegionOffset[11:0]}.
+#define CDU_REG_TCFC_MATT_SIZE                                                                               64
+#define CDU_REG_TCFC_FL_MATT_BB_K2                                                                           0x583200UL //Access:WB   DataWidth:0x18   // MATT Access; Each entry has the following format: {RegionLength[11:0]; RegionOffset[11:0]}.
+#define CDU_REG_TCFC_FL_MATT_SIZE                                                                            64
+#define CDU_REG_CCFC_L1TT_BB_K2                                                                              0x581000UL //Access:WB   DataWidth:0x110  // L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*[4:0]}.
+#define CDU_REG_CCFC_L1TT_E5                                                                                 0x584000UL //Access:WB   DataWidth:0x110  // L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*[4:0]}.
+#define CDU_REG_CCFC_L1TT_SIZE_BB_K2                                                                         1024
+#define CDU_REG_CCFC_L1TT_SIZE_E5                                                                            2048
+#define CDU_REG_CCFC_MATT_BB_K2                                                                              0x583000UL //Access:WB   DataWidth:0x18   // MATT Access; Each entry has the following format: {RegionLength[11:0]; RegionOffset[11:0]}.
+#define CDU_REG_CCFC_MATT_E5                                                                                 0x586000UL //Access:WB   DataWidth:0x18   // MATT Access; Each entry has the following format: {RegionLength[11:0]; RegionOffset[11:0]}.
+#define CDU_REG_CCFC_MATT_SIZE_BB_K2                                                                         64
+#define CDU_REG_CCFC_MATT_SIZE_E5                                                                            128
+#define PTLD_REG_FOCI_FOC_CREDITS_E5                                                                         0x590000UL //Access:RW   DataWidth:0x6    // Initial credit of the FOC itnerface.
+#define PTLD_REG_ECO_RESERVED_E5                                                                             0x590004UL //Access:RW   DataWidth:0x8    // Allowes future ECO's
+#define PTLD_REG_FOC_REMAIN_CREDITS_E5                                                                       0x590008UL //Access:R    DataWidth:0x6    // Remaining credits on the FOC interface
+#define PTLD_REG_LD_HDR_LOG_E5                                                                               0x59000cUL //Access:R    DataWidth:0x4    // Logging of the problem which caused the ld_hdr_err interrupt. Bit 0: ilegal flags combination.
+#define PTLD_REG_LD_HDR_1ST_CYC_31_0_E5                                                                      0x590010UL //Access:R    DataWidth:0x20   // Logging of the first loader header cycle - for the case ld_hdr_err is raised.
+#define PTLD_REG_LD_HDR_1ST_CYC_63_32_E5                                                                     0x590014UL //Access:R    DataWidth:0x20   // Logging of the first loader header cycle - for the case ld_hdr_err is raised.
+#define PTLD_REG_LD_HDR_1ST_CYC_95_64_E5                                                                     0x590018UL //Access:R    DataWidth:0x20   // Logging of the first loader header cycle - for the case ld_hdr_err is raised.
+#define PTLD_REG_LD_HDR_1ST_CYC_127_96_E5                                                                    0x59001cUL //Access:R    DataWidth:0x20   // Logging of the first loader header cycle - for the case ld_hdr_err is raised.
+#define PTLD_REG_LD_HDR_2ND_CYC_31_0_E5                                                                      0x590020UL //Access:R    DataWidth:0x20   // Logging of the second loader header cycle - for the case ld_hdr_err is raised.
+#define PTLD_REG_LD_HDR_2ND_CYC_63_32_E5                                                                     0x590024UL //Access:R    DataWidth:0x20   // Logging of the second loader header cycle - for the case ld_hdr_err is raised.
+#define PTLD_REG_LD_HDR_2ND_CYC_95_64_E5                                                                     0x590028UL //Access:R    DataWidth:0x20   // Logging of the second loader header cycle - for the case ld_hdr_err is raised.
+#define PTLD_REG_LD_HDR_2ND_CYC_127_96_E5                                                                    0x59002cUL //Access:R    DataWidth:0x20   // Logging of the second loader header cycle - for the case ld_hdr_err is raised.
+#define PTLD_REG_CM_HDR_31_0_E5                                                                              0x590030UL //Access:R    DataWidth:0x20   // Logging of the cm header cycle - for the case ld_hdr_err is raised.
+#define PTLD_REG_CM_HDR_63_32_E5                                                                             0x590034UL //Access:R    DataWidth:0x20   // Logging of the cm header cycle - for the case ld_hdr_err is raised.
+#define PTLD_REG_CM_HDR_95_64_E5                                                                             0x590038UL //Access:R    DataWidth:0x20   // Logging of the cm header cycle - for the case ld_hdr_err is raised.
+#define PTLD_REG_CM_HDR_127_96_E5                                                                            0x59003cUL //Access:R    DataWidth:0x20   // Logging of the cm header cycle - for the case ld_hdr_err is raised.
+#define PTLD_REG_LD_HDR_CLR_E5                                                                               0x590040UL //Access:W    DataWidth:0x1    // Writing to this register clears hdr registers and enables logging new error details.
+#define PTLD_REG_STAT_FIC_MSG_E5                                                                             0x590044UL //Access:RC   DataWidth:0x20   // Number of FIC messages sent to the loader
+#define PTLD_REG_LEN_ERR_LOG_1_E5                                                                            0x590048UL //Access:R    DataWidth:0x10   // Logging register for long message error: bit 0-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SGE fetch; bit 4- Message with BRB fetch; bits 5:6- QID; bits 7-RSV; bits 8-15 message CM length.
+#define PTLD_REG_LEN_ERR_LOG_2_E5                                                                            0x59004cUL //Access:R    DataWidth:0x20   // Logging register for long message error: bit 0:3 Segment message header length; 4:7 RSV;8:15 current length out of the segment message length array; 16:23 PCI response len (including BD and SGE fetches); 24:31 BRB
+#define PTLD_REG_LEN_ERR_LOG_CLR_E5                                                                          0x590050UL //Access:W    DataWidth:0x1    // Writing to this register clears len err logging registers and enables logging new error details.
+#define PTLD_REG_LEN_ERR_LOG_V_E5                                                                            0x590054UL //Access:R    DataWidth:0x1    // Indicates that the data at the len_err logging registers is valid.
+#define PTLD_REG_INT_STS_E5                                                                                  0x590180UL //Access:R    DataWidth:0x6    // Multi Field Register.
+  #define PTLD_REG_INT_STS_ADDRESS_ERROR_E5                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define PTLD_REG_INT_STS_ADDRESS_ERROR_E5_SHIFT                                                            0
+  #define PTLD_REG_INT_STS_LD_HDR_ERR_E5                                                                     (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
+  #define PTLD_REG_INT_STS_LD_HDR_ERR_E5_SHIFT                                                               1
+  #define PTLD_REG_INT_STS_LD_SEG_MSG_ERR_E5                                                                 (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
+  #define PTLD_REG_INT_STS_LD_SEG_MSG_ERR_E5_SHIFT                                                           2
+  #define PTLD_REG_INT_STS_LD_TID_MINI_CACHE_ERR_E5                                                          (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
+  #define PTLD_REG_INT_STS_LD_TID_MINI_CACHE_ERR_E5_SHIFT                                                    3
+  #define PTLD_REG_INT_STS_LD_CID_MINI_CACHE_ERR_E5                                                          (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
+  #define PTLD_REG_INT_STS_LD_CID_MINI_CACHE_ERR_E5_SHIFT                                                    4
+  #define PTLD_REG_INT_STS_LD_LONG_MESSAGE_E5                                                                (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
+  #define PTLD_REG_INT_STS_LD_LONG_MESSAGE_E5_SHIFT                                                          5
+#define PTLD_REG_INT_MASK_E5                                                                                 0x590184UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define PTLD_REG_INT_MASK_ADDRESS_ERROR_E5                                                                 (0x1<<0) // This bit masks, when set, the Interrupt bit: PTLD_REG_INT_STS.ADDRESS_ERROR .
+  #define PTLD_REG_INT_MASK_ADDRESS_ERROR_E5_SHIFT                                                           0
+  #define PTLD_REG_INT_MASK_LD_HDR_ERR_E5                                                                    (0x1<<1) // This bit masks, when set, the Interrupt bit: PTLD_REG_INT_STS.LD_HDR_ERR .
+  #define PTLD_REG_INT_MASK_LD_HDR_ERR_E5_SHIFT                                                              1
+  #define PTLD_REG_INT_MASK_LD_SEG_MSG_ERR_E5                                                                (0x1<<2) // This bit masks, when set, the Interrupt bit: PTLD_REG_INT_STS.LD_SEG_MSG_ERR .
+  #define PTLD_REG_INT_MASK_LD_SEG_MSG_ERR_E5_SHIFT                                                          2
+  #define PTLD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR_E5                                                         (0x1<<3) // This bit masks, when set, the Interrupt bit: PTLD_REG_INT_STS.LD_TID_MINI_CACHE_ERR .
+  #define PTLD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR_E5_SHIFT                                                   3
+  #define PTLD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR_E5                                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: PTLD_REG_INT_STS.LD_CID_MINI_CACHE_ERR .
+  #define PTLD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR_E5_SHIFT                                                   4
+  #define PTLD_REG_INT_MASK_LD_LONG_MESSAGE_E5                                                               (0x1<<5) // This bit masks, when set, the Interrupt bit: PTLD_REG_INT_STS.LD_LONG_MESSAGE .
+  #define PTLD_REG_INT_MASK_LD_LONG_MESSAGE_E5_SHIFT                                                         5
+#define PTLD_REG_INT_STS_WR_E5                                                                               0x590188UL //Access:WR   DataWidth:0x6    // Multi Field Register.
+  #define PTLD_REG_INT_STS_WR_ADDRESS_ERROR_E5                                                               (0x1<<0) // Signals an unknown address to the rf module.
+  #define PTLD_REG_INT_STS_WR_ADDRESS_ERROR_E5_SHIFT                                                         0
+  #define PTLD_REG_INT_STS_WR_LD_HDR_ERR_E5                                                                  (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
+  #define PTLD_REG_INT_STS_WR_LD_HDR_ERR_E5_SHIFT                                                            1
+  #define PTLD_REG_INT_STS_WR_LD_SEG_MSG_ERR_E5                                                              (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
+  #define PTLD_REG_INT_STS_WR_LD_SEG_MSG_ERR_E5_SHIFT                                                        2
+  #define PTLD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR_E5                                                       (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
+  #define PTLD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR_E5_SHIFT                                                 3
+  #define PTLD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR_E5                                                       (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
+  #define PTLD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR_E5_SHIFT                                                 4
+  #define PTLD_REG_INT_STS_WR_LD_LONG_MESSAGE_E5                                                             (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
+  #define PTLD_REG_INT_STS_WR_LD_LONG_MESSAGE_E5_SHIFT                                                       5
+#define PTLD_REG_INT_STS_CLR_E5                                                                              0x59018cUL //Access:RC   DataWidth:0x6    // Multi Field Register.
+  #define PTLD_REG_INT_STS_CLR_ADDRESS_ERROR_E5                                                              (0x1<<0) // Signals an unknown address to the rf module.
+  #define PTLD_REG_INT_STS_CLR_ADDRESS_ERROR_E5_SHIFT                                                        0
+  #define PTLD_REG_INT_STS_CLR_LD_HDR_ERR_E5                                                                 (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
+  #define PTLD_REG_INT_STS_CLR_LD_HDR_ERR_E5_SHIFT                                                           1
+  #define PTLD_REG_INT_STS_CLR_LD_SEG_MSG_ERR_E5                                                             (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
+  #define PTLD_REG_INT_STS_CLR_LD_SEG_MSG_ERR_E5_SHIFT                                                       2
+  #define PTLD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR_E5                                                      (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
+  #define PTLD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR_E5_SHIFT                                                3
+  #define PTLD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR_E5                                                      (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
+  #define PTLD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR_E5_SHIFT                                                4
+  #define PTLD_REG_INT_STS_CLR_LD_LONG_MESSAGE_E5                                                            (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
+  #define PTLD_REG_INT_STS_CLR_LD_LONG_MESSAGE_E5_SHIFT                                                      5
+#define PTLD_REG_DESC_QUEUE_Q0_E5                                                                            0x590400UL //Access:WB   DataWidth:0x23   // Descriptor FIFO queue0 - Debug access.
+#define PTLD_REG_DESC_QUEUE_Q0_SIZE                                                                          150
+#define PTLD_REG_DESC_QUEUE_Q1_E5                                                                            0x590800UL //Access:WB   DataWidth:0x23   // Descriptor FIFO queue1 - Debug access.
+#define PTLD_REG_DESC_QUEUE_Q1_SIZE                                                                          150
+#define PTLD_REG_L2MA_AGGR_CONFIG1_E5                                                                        0x590c00UL //Access:RW   DataWidth:0x13   // Multi Field Register.
+  #define PTLD_REG_L2MA_AGGR_CONFIG1_L2MA_EN_E5                                                              (0x1<<0) // Enables L2 message aggregation
+  #define PTLD_REG_L2MA_AGGR_CONFIG1_L2MA_EN_E5_SHIFT                                                        0
+  #define PTLD_REG_L2MA_AGGR_CONFIG1_IGNORE_CM_AGG_MSG_E5                                                    (0x1<<1) // indicates not to perform the aggregation logic if there is no L2MA command in the message (there is no L2MA command if DstStormFlg is reset OR ErrFlg is set). If this configuration is reset, messages without L2MA command are treated like messages with L2MA command where EnL2MA flag in the command is reset (i.e. they break existing aggregation).
+  #define PTLD_REG_L2MA_AGGR_CONFIG1_IGNORE_CM_AGG_MSG_E5_SHIFT                                              1
+  #define PTLD_REG_L2MA_AGGR_CONFIG1_BACK_2_BACK_E5                                                          (0x1<<2) // defines that only back-to-back aggregation is allowed
+  #define PTLD_REG_L2MA_AGGR_CONFIG1_BACK_2_BACK_E5_SHIFT                                                    2
+  #define PTLD_REG_L2MA_AGGR_CONFIG1_MIN_QUEUE_OCC_E5                                                        (0xff<<3) // the minimal queue occupancy below which new aggregations are not created
+  #define PTLD_REG_L2MA_AGGR_CONFIG1_MIN_QUEUE_OCC_E5_SHIFT                                                  3
+  #define PTLD_REG_L2MA_AGGR_CONFIG1_MAX_L2MA_DIFF_E5                                                        (0xff<<11) // the maximal difference between the serial number of the parent message and the serial number of its child message
+  #define PTLD_REG_L2MA_AGGR_CONFIG1_MAX_L2MA_DIFF_E5_SHIFT                                                  11
+#define PTLD_REG_L2MA_AGGR_CONFIG2_E5                                                                        0x590c04UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define PTLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_0_E5                                                     (0x3f<<0) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
+  #define PTLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_0_E5_SHIFT                                               0
+  #define PTLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_1_E5                                                     (0x3f<<6) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
+  #define PTLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_1_E5_SHIFT                                               6
+  #define PTLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_2_E5                                                     (0x3f<<12) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
+  #define PTLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_2_E5_SHIFT                                               12
+  #define PTLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_3_E5                                                     (0x3f<<18) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
+  #define PTLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_3_E5_SHIFT                                               18
+#define PTLD_REG_L2MA_SAME_OFFSET_SET_0_E5                                                                   0x590c08UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_00_E5                                                       (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_00_E5_SHIFT                                                 0
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_01_E5                                                       (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_01_E5_SHIFT                                                 8
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_02_E5                                                       (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_02_E5_SHIFT                                                 16
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_03_E5                                                       (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_03_E5_SHIFT                                                 24
+#define PTLD_REG_L2MA_SAME_OFFSET_SET_1_E5                                                                   0x590c0cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_10_E5                                                       (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_10_E5_SHIFT                                                 0
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_11_E5                                                       (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_11_E5_SHIFT                                                 8
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_12_E5                                                       (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_12_E5_SHIFT                                                 16
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_13_E5                                                       (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_13_E5_SHIFT                                                 24
+#define PTLD_REG_L2MA_SAME_OFFSET_SET_2_E5                                                                   0x590c10UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_20_E5                                                       (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_20_E5_SHIFT                                                 0
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_21_E5                                                       (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_21_E5_SHIFT                                                 8
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_22_E5                                                       (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_22_E5_SHIFT                                                 16
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_23_E5                                                       (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_23_E5_SHIFT                                                 24
+#define PTLD_REG_L2MA_SAME_OFFSET_SET_3_E5                                                                   0x590c14UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_30_E5                                                       (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_30_E5_SHIFT                                                 0
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_31_E5                                                       (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_31_E5_SHIFT                                                 8
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_32_E5                                                       (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_32_E5_SHIFT                                                 16
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_33_E5                                                       (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
+  #define PTLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_33_E5_SHIFT                                                 24
+#define PTLD_REG_L2MA_SAME_LEN_SET_0_1_E5                                                                    0x590c18UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PTLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_00_E5                                                           (0xf<<0) // length in 32b units from the same 00 .
+  #define PTLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_00_E5_SHIFT                                                     0
+  #define PTLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_01_E5                                                           (0xf<<4) // length in 32b units from the same 01 .
+  #define PTLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_01_E5_SHIFT                                                     4
+  #define PTLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_02_E5                                                           (0xf<<8) // length in 32b units from the same 02 .
+  #define PTLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_02_E5_SHIFT                                                     8
+  #define PTLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_03_E5                                                           (0xf<<12) // length in 32b units from the same 03 .
+  #define PTLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_03_E5_SHIFT                                                     12
+  #define PTLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_10_E5                                                           (0xf<<16) // length in 32b units from the same 10 .
+  #define PTLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_10_E5_SHIFT                                                     16
+  #define PTLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_11_E5                                                           (0xf<<20) // length in 32b units from the same 11 .
+  #define PTLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_11_E5_SHIFT                                                     20
+  #define PTLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_12_E5                                                           (0xf<<24) // length in 32b units from the same 12 .
+  #define PTLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_12_E5_SHIFT                                                     24
+  #define PTLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_13_E5                                                           (0xf<<28) // length in 32b units from the same 13 .
+  #define PTLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_13_E5_SHIFT                                                     28
+#define PTLD_REG_L2MA_SAME_LEN_SET_2_3_E5                                                                    0x590c1cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PTLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_20_E5                                                           (0xf<<0) // length in 32b units from the same 20 .
+  #define PTLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_20_E5_SHIFT                                                     0
+  #define PTLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_21_E5                                                           (0xf<<4) // length in 32b units from the same 21 .
+  #define PTLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_21_E5_SHIFT                                                     4
+  #define PTLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_22_E5                                                           (0xf<<8) // length in 32b units from the same 22 .
+  #define PTLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_22_E5_SHIFT                                                     8
+  #define PTLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_23_E5                                                           (0xf<<12) // length in 32b units from the same 23 .
+  #define PTLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_23_E5_SHIFT                                                     12
+  #define PTLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_30_E5                                                           (0xf<<16) // length in 32b units from the same 30 .
+  #define PTLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_30_E5_SHIFT                                                     16
+  #define PTLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_31_E5                                                           (0xf<<20) // length in 32b units from the same 31 .
+  #define PTLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_31_E5_SHIFT                                                     20
+  #define PTLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_32_E5                                                           (0xf<<24) // length in 32b units from the same 32 .
+  #define PTLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_32_E5_SHIFT                                                     24
+  #define PTLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_33_E5                                                           (0xf<<28) // length in 32b units from the same 33 .
+  #define PTLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_33_E5_SHIFT                                                     28
+#define PTLD_REG_L2MA_SAME_MASK_SET_0_E5                                                                     0x590c20UL //Access:RW   DataWidth:0x20   // bit-mask on the selected 32B same 0 parameters .
+#define PTLD_REG_L2MA_SAME_MASK_SET_1_E5                                                                     0x590c24UL //Access:RW   DataWidth:0x20   // bit-mask on the selected 32B same 1 parameters .
+#define PTLD_REG_L2MA_SAME_MASK_SET_2_E5                                                                     0x590c28UL //Access:RW   DataWidth:0x20   // bit-mask on the selected 32B same 2 parameters .
+#define PTLD_REG_L2MA_SAME_MASK_SET_3_E5                                                                     0x590c2cUL //Access:RW   DataWidth:0x20   // bit-mask on the selected 32B same 3 parameters .
+#define PTLD_REG_L2MA_DUP_OFFSET_SET_0_E5                                                                    0x590c30UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_00_E5                                                    (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_00_E5_SHIFT                                              0
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_01_E5                                                    (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_01_E5_SHIFT                                              8
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_02_E5                                                    (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_02_E5_SHIFT                                              16
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_03_E5                                                    (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_03_E5_SHIFT                                              24
+#define PTLD_REG_L2MA_DUP_OFFSET_SET_1_E5                                                                    0x590c34UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_10_E5                                                    (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_10_E5_SHIFT                                              0
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_11_E5                                                    (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_11_E5_SHIFT                                              8
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_12_E5                                                    (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_12_E5_SHIFT                                              16
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_13_E5                                                    (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_13_E5_SHIFT                                              24
+#define PTLD_REG_L2MA_DUP_OFFSET_SET_2_E5                                                                    0x590c38UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_20_E5                                                    (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_20_E5_SHIFT                                              0
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_21_E5                                                    (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_21_E5_SHIFT                                              8
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_22_E5                                                    (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_22_E5_SHIFT                                              16
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_23_E5                                                    (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_23_E5_SHIFT                                              24
+#define PTLD_REG_L2MA_DUP_OFFSET_SET_3_E5                                                                    0x590c3cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_30_E5                                                    (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_30_E5_SHIFT                                              0
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_31_E5                                                    (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_31_E5_SHIFT                                              8
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_32_E5                                                    (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_32_E5_SHIFT                                              16
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_33_E5                                                    (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
+  #define PTLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_33_E5_SHIFT                                              24
+#define PTLD_REG_L2MA_DUP_LEN_SET_0_E5                                                                       0x590c40UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define PTLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_00_E5                                                          (0x3f<<0) // length in 32b units from the dup 00 .
+  #define PTLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_00_E5_SHIFT                                                    0
+  #define PTLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_01_E5                                                          (0x3f<<6) // length in 32b units from the dup 01 .
+  #define PTLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_01_E5_SHIFT                                                    6
+  #define PTLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_02_E5                                                          (0x3f<<12) // length in 32b units from the dup 02 .
+  #define PTLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_02_E5_SHIFT                                                    12
+  #define PTLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_03_E5                                                          (0x3f<<18) // length in 32b units from the dup 03 .
+  #define PTLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_03_E5_SHIFT                                                    18
+#define PTLD_REG_L2MA_DUP_LEN_SET_1_E5                                                                       0x590c44UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define PTLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_10_E5                                                          (0x3f<<0) // length in 32b units from the dup 10 .
+  #define PTLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_10_E5_SHIFT                                                    0
+  #define PTLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_11_E5                                                          (0x3f<<6) // length in 32b units from the dup 11 .
+  #define PTLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_11_E5_SHIFT                                                    6
+  #define PTLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_12_E5                                                          (0x3f<<12) // length in 32b units from the dup 12 .
+  #define PTLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_12_E5_SHIFT                                                    12
+  #define PTLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_13_E5                                                          (0x3f<<18) // length in 32b units from the dup 13 .
+  #define PTLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_13_E5_SHIFT                                                    18
+#define PTLD_REG_L2MA_DUP_LEN_SET_2_E5                                                                       0x590c48UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define PTLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_20_E5                                                          (0x3f<<0) // length in 32b units from the dup 20 .
+  #define PTLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_20_E5_SHIFT                                                    0
+  #define PTLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_21_E5                                                          (0x3f<<6) // length in 32b units from the dup 21 .
+  #define PTLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_21_E5_SHIFT                                                    6
+  #define PTLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_22_E5                                                          (0x3f<<12) // length in 32b units from the dup 22 .
+  #define PTLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_22_E5_SHIFT                                                    12
+  #define PTLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_23_E5                                                          (0x3f<<18) // length in 32b units from the dup 23 .
+  #define PTLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_23_E5_SHIFT                                                    18
+#define PTLD_REG_L2MA_DUP_LEN_SET_3_E5                                                                       0x590c4cUL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define PTLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_30_E5                                                          (0x3f<<0) // length in 32b units from the dup 30 .
+  #define PTLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_30_E5_SHIFT                                                    0
+  #define PTLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_31_E5                                                          (0x3f<<6) // length in 32b units from the dup 31 .
+  #define PTLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_31_E5_SHIFT                                                    6
+  #define PTLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_32_E5                                                          (0x3f<<12) // length in 32b units from the dup 32 .
+  #define PTLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_32_E5_SHIFT                                                    12
+  #define PTLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_33_E5                                                          (0x3f<<18) // length in 32b units from the dup 33 .
+  #define PTLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_33_E5_SHIFT                                                    18
+#define PTLD_REG_L2MA_FLOW_ID_E5                                                                             0x590c50UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_0_E5                                                         (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
+  #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_0_E5_SHIFT                                                   0
+  #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_1_E5                                                         (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
+  #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_1_E5_SHIFT                                                   1
+  #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_2_E5                                                         (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
+  #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_2_E5_SHIFT                                                   2
+  #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_3_E5                                                         (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
+  #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_3_E5_SHIFT                                                   3
+  #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_0_E5                                                          (0x1f<<4) // offset of the flow-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of the incoming message (i.e. max value is 23). This parameter is NA if FlowIdInclude is reset. For set 0 .
+  #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_0_E5_SHIFT                                                    4
+  #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_1_E5                                                          (0x1f<<9) // offset of the flow-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of the incoming message (i.e. max value is 23). This parameter is NA if FlowIdInclude is reset. For set 1 .
+  #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_1_E5_SHIFT                                                    9
+  #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_2_E5                                                          (0x1f<<14) // offset of the flow-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of the incoming message (i.e. max value is 23). This parameter is NA if FlowIdInclude is reset. For set 2 .
+  #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_2_E5_SHIFT                                                    14
+  #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_3_E5                                                          (0x1f<<19) // offset of the flow-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of the incoming message (i.e. max value is 23). This parameter is NA if FlowIdInclude is reset. For set 3 .
+  #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_3_E5_SHIFT                                                    19
+#define PTLD_REG_L2MA_SN_OFFSET_E5                                                                           0x590c54UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PTLD_REG_L2MA_SN_OFFSET_SN_OFFSET_0_E5                                                             (0xff<<0) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 0.
+  #define PTLD_REG_L2MA_SN_OFFSET_SN_OFFSET_0_E5_SHIFT                                                       0
+  #define PTLD_REG_L2MA_SN_OFFSET_SN_OFFSET_1_E5                                                             (0xff<<8) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 1.
+  #define PTLD_REG_L2MA_SN_OFFSET_SN_OFFSET_1_E5_SHIFT                                                       8
+  #define PTLD_REG_L2MA_SN_OFFSET_SN_OFFSET_2_E5                                                             (0xff<<16) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 2.
+  #define PTLD_REG_L2MA_SN_OFFSET_SN_OFFSET_2_E5_SHIFT                                                       16
+  #define PTLD_REG_L2MA_SN_OFFSET_SN_OFFSET_3_E5                                                             (0xff<<24) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 3.
+  #define PTLD_REG_L2MA_SN_OFFSET_SN_OFFSET_3_E5_SHIFT                                                       24
+#define PTLD_REG_L2MA_MAX_L2MA_CHILD_E5                                                                      0x590c58UL //Access:RW   DataWidth:0x10   // Multi Field Register.
+  #define PTLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_0_E5                                                         (0xf<<0) // the maximal number of children in a specific aggregation. for set 0.
+  #define PTLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_0_E5_SHIFT                                                   0
+  #define PTLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_1_E5                                                         (0xf<<4) // the maximal number of children in a specific aggregation. for set 1.
+  #define PTLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_1_E5_SHIFT                                                   4
+  #define PTLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_2_E5                                                         (0xf<<8) // the maximal number of children in a specific aggregation. for set 2.
+  #define PTLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_2_E5_SHIFT                                                   8
+  #define PTLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_3_E5                                                         (0xf<<12) // the maximal number of children in a specific aggregation. for set 3.
+  #define PTLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_3_E5_SHIFT                                                   12
+#define PTLD_REG_L2MA_INC_L2MA_EVENT_ID_E5                                                                   0x590c5cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PTLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_0_E5                                                  (0xff<<0) // The value by which to increment the event-ID in case of successful aggregation. for set 0.
+  #define PTLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_0_E5_SHIFT                                            0
+  #define PTLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_1_E5                                                  (0xff<<8) // The value by which to increment the event-ID in case of successful aggregation. for set 1.
+  #define PTLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_1_E5_SHIFT                                            8
+  #define PTLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_2_E5                                                  (0xff<<16) // The value by which to increment the event-ID in case of successful aggregation. for set 2.
+  #define PTLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_2_E5_SHIFT                                            16
+  #define PTLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_3_E5                                                  (0xff<<24) // The value by which to increment the event-ID in case of successful aggregation. for set 3.
+  #define PTLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_3_E5_SHIFT                                            24
+#define PTLD_REG_LD_MAX_MSG_SIZE_E5                                                                          0x590c60UL //Access:RW   DataWidth:0x4    // maximum loader size in 256 bit words
+#define PTLD_REG_DBG_SELECT_E5                                                                               0x591600UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PTLD_REG_DBG_DWORD_ENABLE_E5                                                                         0x591604UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PTLD_REG_DBG_SHIFT_E5                                                                                0x591608UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PTLD_REG_DBG_FORCE_VALID_E5                                                                          0x59160cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PTLD_REG_DBG_FORCE_FRAME_E5                                                                          0x591610UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PTLD_REG_DBG_OUT_DATA_E5                                                                             0x591620UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PTLD_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define PTLD_REG_DBG_OUT_VALID_E5                                                                            0x591640UL //Access:R    DataWidth:0x4    // Dbgmux output valid
+#define PTLD_REG_DBG_OUT_FRAME_E5                                                                            0x591644UL //Access:R    DataWidth:0x4    // Dbgmux output frame
+#define PTLD_REG_FIC_INPUT_FIFO_E5                                                                           0x592000UL //Access:WB   DataWidth:0x80   // Access to input FIC FIFO
+#define PTLD_REG_FIC_INPUT_FIFO_SIZE                                                                         176
+#define PTLD_REG_QUEUE_MSG_MEM_E5                                                                            0x5a0000UL //Access:WB   DataWidth:0x80   // Debug access to The message queue memory.
+#define PTLD_REG_QUEUE_MSG_MEM_SIZE                                                                          7500
+#define YPLD_REG_FOCI_FOC_CREDITS_E5                                                                         0x5b0000UL //Access:RW   DataWidth:0x6    // Initial credit of the FOC itnerface.
+#define YPLD_REG_ECO_RESERVED_E5                                                                             0x5b0004UL //Access:RW   DataWidth:0x8    // Allowes future ECO's
+#define YPLD_REG_FOC_REMAIN_CREDITS_E5                                                                       0x5b0008UL //Access:R    DataWidth:0x6    // Remaining credits on the FOC interface
+#define YPLD_REG_LD_HDR_LOG_E5                                                                               0x5b000cUL //Access:R    DataWidth:0x4    // Logging of the problem which caused the ld_hdr_err interrupt. Bit 0: ilegal flags combination.
+#define YPLD_REG_LD_HDR_1ST_CYC_31_0_E5                                                                      0x5b0010UL //Access:R    DataWidth:0x20   // Logging of the first loader header cycle - for the case ld_hdr_err is raised.
+#define YPLD_REG_LD_HDR_1ST_CYC_63_32_E5                                                                     0x5b0014UL //Access:R    DataWidth:0x20   // Logging of the first loader header cycle - for the case ld_hdr_err is raised.
+#define YPLD_REG_LD_HDR_1ST_CYC_95_64_E5                                                                     0x5b0018UL //Access:R    DataWidth:0x20   // Logging of the first loader header cycle - for the case ld_hdr_err is raised.
+#define YPLD_REG_LD_HDR_1ST_CYC_127_96_E5                                                                    0x5b001cUL //Access:R    DataWidth:0x20   // Logging of the first loader header cycle - for the case ld_hdr_err is raised.
+#define YPLD_REG_LD_HDR_2ND_CYC_31_0_E5                                                                      0x5b0020UL //Access:R    DataWidth:0x20   // Logging of the second loader header cycle - for the case ld_hdr_err is raised.
+#define YPLD_REG_LD_HDR_2ND_CYC_63_32_E5                                                                     0x5b0024UL //Access:R    DataWidth:0x20   // Logging of the second loader header cycle - for the case ld_hdr_err is raised.
+#define YPLD_REG_LD_HDR_2ND_CYC_95_64_E5                                                                     0x5b0028UL //Access:R    DataWidth:0x20   // Logging of the second loader header cycle - for the case ld_hdr_err is raised.
+#define YPLD_REG_LD_HDR_2ND_CYC_127_96_E5                                                                    0x5b002cUL //Access:R    DataWidth:0x20   // Logging of the second loader header cycle - for the case ld_hdr_err is raised.
+#define YPLD_REG_CM_HDR_31_0_E5                                                                              0x5b0030UL //Access:R    DataWidth:0x20   // Logging of the cm header cycle - for the case ld_hdr_err is raised.
+#define YPLD_REG_CM_HDR_63_32_E5                                                                             0x5b0034UL //Access:R    DataWidth:0x20   // Logging of the cm header cycle - for the case ld_hdr_err is raised.
+#define YPLD_REG_CM_HDR_95_64_E5                                                                             0x5b0038UL //Access:R    DataWidth:0x20   // Logging of the cm header cycle - for the case ld_hdr_err is raised.
+#define YPLD_REG_CM_HDR_127_96_E5                                                                            0x5b003cUL //Access:R    DataWidth:0x20   // Logging of the cm header cycle - for the case ld_hdr_err is raised.
+#define YPLD_REG_LD_HDR_CLR_E5                                                                               0x5b0040UL //Access:W    DataWidth:0x1    // Writing to this register clears hdr registers and enables logging new error details.
+#define YPLD_REG_STAT_FIC_MSG_E5                                                                             0x5b0044UL //Access:RC   DataWidth:0x20   // Number of FIC messages sent to the loader
+#define YPLD_REG_LEN_ERR_LOG_1_E5                                                                            0x5b0048UL //Access:R    DataWidth:0x10   // Logging register for long message error: bit 0-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SGE fetch; bit 4- Message with BRB fetch; bits 5:6- QID; bits 7-RSV; bits 8-15 message CM length.
+#define YPLD_REG_LEN_ERR_LOG_2_E5                                                                            0x5b004cUL //Access:R    DataWidth:0x20   // Logging register for long message error: bit 0:3 Segment message header length; 4:7 RSV;8:15 current length out of the segment message length array; 16:23 PCI response len (including BD and SGE fetches); 24:31 BRB
+#define YPLD_REG_LEN_ERR_LOG_CLR_E5                                                                          0x5b0050UL //Access:W    DataWidth:0x1    // Writing to this register clears len err logging registers and enables logging new error details.
+#define YPLD_REG_LEN_ERR_LOG_V_E5                                                                            0x5b0054UL //Access:R    DataWidth:0x1    // Indicates that the data at the len_err logging registers is valid.
+#define YPLD_REG_INT_STS_E5                                                                                  0x5b0180UL //Access:R    DataWidth:0x6    // Multi Field Register.
+  #define YPLD_REG_INT_STS_ADDRESS_ERROR_E5                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define YPLD_REG_INT_STS_ADDRESS_ERROR_E5_SHIFT                                                            0
+  #define YPLD_REG_INT_STS_LD_HDR_ERR_E5                                                                     (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
+  #define YPLD_REG_INT_STS_LD_HDR_ERR_E5_SHIFT                                                               1
+  #define YPLD_REG_INT_STS_LD_SEG_MSG_ERR_E5                                                                 (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
+  #define YPLD_REG_INT_STS_LD_SEG_MSG_ERR_E5_SHIFT                                                           2
+  #define YPLD_REG_INT_STS_LD_TID_MINI_CACHE_ERR_E5                                                          (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
+  #define YPLD_REG_INT_STS_LD_TID_MINI_CACHE_ERR_E5_SHIFT                                                    3
+  #define YPLD_REG_INT_STS_LD_CID_MINI_CACHE_ERR_E5                                                          (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
+  #define YPLD_REG_INT_STS_LD_CID_MINI_CACHE_ERR_E5_SHIFT                                                    4
+  #define YPLD_REG_INT_STS_LD_LONG_MESSAGE_E5                                                                (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
+  #define YPLD_REG_INT_STS_LD_LONG_MESSAGE_E5_SHIFT                                                          5
+#define YPLD_REG_INT_MASK_E5                                                                                 0x5b0184UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define YPLD_REG_INT_MASK_ADDRESS_ERROR_E5                                                                 (0x1<<0) // This bit masks, when set, the Interrupt bit: YPLD_REG_INT_STS.ADDRESS_ERROR .
+  #define YPLD_REG_INT_MASK_ADDRESS_ERROR_E5_SHIFT                                                           0
+  #define YPLD_REG_INT_MASK_LD_HDR_ERR_E5                                                                    (0x1<<1) // This bit masks, when set, the Interrupt bit: YPLD_REG_INT_STS.LD_HDR_ERR .
+  #define YPLD_REG_INT_MASK_LD_HDR_ERR_E5_SHIFT                                                              1
+  #define YPLD_REG_INT_MASK_LD_SEG_MSG_ERR_E5                                                                (0x1<<2) // This bit masks, when set, the Interrupt bit: YPLD_REG_INT_STS.LD_SEG_MSG_ERR .
+  #define YPLD_REG_INT_MASK_LD_SEG_MSG_ERR_E5_SHIFT                                                          2
+  #define YPLD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR_E5                                                         (0x1<<3) // This bit masks, when set, the Interrupt bit: YPLD_REG_INT_STS.LD_TID_MINI_CACHE_ERR .
+  #define YPLD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR_E5_SHIFT                                                   3
+  #define YPLD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR_E5                                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: YPLD_REG_INT_STS.LD_CID_MINI_CACHE_ERR .
+  #define YPLD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR_E5_SHIFT                                                   4
+  #define YPLD_REG_INT_MASK_LD_LONG_MESSAGE_E5                                                               (0x1<<5) // This bit masks, when set, the Interrupt bit: YPLD_REG_INT_STS.LD_LONG_MESSAGE .
+  #define YPLD_REG_INT_MASK_LD_LONG_MESSAGE_E5_SHIFT                                                         5
+#define YPLD_REG_INT_STS_WR_E5                                                                               0x5b0188UL //Access:WR   DataWidth:0x6    // Multi Field Register.
+  #define YPLD_REG_INT_STS_WR_ADDRESS_ERROR_E5                                                               (0x1<<0) // Signals an unknown address to the rf module.
+  #define YPLD_REG_INT_STS_WR_ADDRESS_ERROR_E5_SHIFT                                                         0
+  #define YPLD_REG_INT_STS_WR_LD_HDR_ERR_E5                                                                  (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
+  #define YPLD_REG_INT_STS_WR_LD_HDR_ERR_E5_SHIFT                                                            1
+  #define YPLD_REG_INT_STS_WR_LD_SEG_MSG_ERR_E5                                                              (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
+  #define YPLD_REG_INT_STS_WR_LD_SEG_MSG_ERR_E5_SHIFT                                                        2
+  #define YPLD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR_E5                                                       (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
+  #define YPLD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR_E5_SHIFT                                                 3
+  #define YPLD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR_E5                                                       (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
+  #define YPLD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR_E5_SHIFT                                                 4
+  #define YPLD_REG_INT_STS_WR_LD_LONG_MESSAGE_E5                                                             (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
+  #define YPLD_REG_INT_STS_WR_LD_LONG_MESSAGE_E5_SHIFT                                                       5
+#define YPLD_REG_INT_STS_CLR_E5                                                                              0x5b018cUL //Access:RC   DataWidth:0x6    // Multi Field Register.
+  #define YPLD_REG_INT_STS_CLR_ADDRESS_ERROR_E5                                                              (0x1<<0) // Signals an unknown address to the rf module.
+  #define YPLD_REG_INT_STS_CLR_ADDRESS_ERROR_E5_SHIFT                                                        0
+  #define YPLD_REG_INT_STS_CLR_LD_HDR_ERR_E5                                                                 (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
+  #define YPLD_REG_INT_STS_CLR_LD_HDR_ERR_E5_SHIFT                                                           1
+  #define YPLD_REG_INT_STS_CLR_LD_SEG_MSG_ERR_E5                                                             (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
+  #define YPLD_REG_INT_STS_CLR_LD_SEG_MSG_ERR_E5_SHIFT                                                       2
+  #define YPLD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR_E5                                                      (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
+  #define YPLD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR_E5_SHIFT                                                3
+  #define YPLD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR_E5                                                      (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
+  #define YPLD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR_E5_SHIFT                                                4
+  #define YPLD_REG_INT_STS_CLR_LD_LONG_MESSAGE_E5                                                            (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
+  #define YPLD_REG_INT_STS_CLR_LD_LONG_MESSAGE_E5_SHIFT                                                      5
+#define YPLD_REG_DESC_QUEUE_Q0_E5                                                                            0x5b0400UL //Access:WB   DataWidth:0x23   // Descriptor FIFO queue0 - Debug access.
+#define YPLD_REG_DESC_QUEUE_Q0_SIZE                                                                          150
+#define YPLD_REG_DESC_QUEUE_Q1_E5                                                                            0x5b0800UL //Access:WB   DataWidth:0x23   // Descriptor FIFO queue1 - Debug access.
+#define YPLD_REG_DESC_QUEUE_Q1_SIZE                                                                          150
+#define YPLD_REG_L2MA_AGGR_CONFIG1_E5                                                                        0x5b0c00UL //Access:RW   DataWidth:0x13   // Multi Field Register.
+  #define YPLD_REG_L2MA_AGGR_CONFIG1_L2MA_EN_E5                                                              (0x1<<0) // Enables L2 message aggregation
+  #define YPLD_REG_L2MA_AGGR_CONFIG1_L2MA_EN_E5_SHIFT                                                        0
+  #define YPLD_REG_L2MA_AGGR_CONFIG1_IGNORE_CM_AGG_MSG_E5                                                    (0x1<<1) // indicates not to perform the aggregation logic if there is no L2MA command in the message (there is no L2MA command if DstStormFlg is reset OR ErrFlg is set). If this configuration is reset, messages without L2MA command are treated like messages with L2MA command where EnL2MA flag in the command is reset (i.e. they break existing aggregation).
+  #define YPLD_REG_L2MA_AGGR_CONFIG1_IGNORE_CM_AGG_MSG_E5_SHIFT                                              1
+  #define YPLD_REG_L2MA_AGGR_CONFIG1_BACK_2_BACK_E5                                                          (0x1<<2) // defines that only back-to-back aggregation is allowed
+  #define YPLD_REG_L2MA_AGGR_CONFIG1_BACK_2_BACK_E5_SHIFT                                                    2
+  #define YPLD_REG_L2MA_AGGR_CONFIG1_MIN_QUEUE_OCC_E5                                                        (0xff<<3) // the minimal queue occupancy below which new aggregations are not created
+  #define YPLD_REG_L2MA_AGGR_CONFIG1_MIN_QUEUE_OCC_E5_SHIFT                                                  3
+  #define YPLD_REG_L2MA_AGGR_CONFIG1_MAX_L2MA_DIFF_E5                                                        (0xff<<11) // the maximal difference between the serial number of the parent message and the serial number of its child message
+  #define YPLD_REG_L2MA_AGGR_CONFIG1_MAX_L2MA_DIFF_E5_SHIFT                                                  11
+#define YPLD_REG_L2MA_AGGR_CONFIG2_E5                                                                        0x5b0c04UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define YPLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_0_E5                                                     (0x3f<<0) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
+  #define YPLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_0_E5_SHIFT                                               0
+  #define YPLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_1_E5                                                     (0x3f<<6) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
+  #define YPLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_1_E5_SHIFT                                               6
+  #define YPLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_2_E5                                                     (0x3f<<12) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
+  #define YPLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_2_E5_SHIFT                                               12
+  #define YPLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_3_E5                                                     (0x3f<<18) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
+  #define YPLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_3_E5_SHIFT                                               18
+#define YPLD_REG_L2MA_SAME_OFFSET_SET_0_E5                                                                   0x5b0c08UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_00_E5                                                       (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_00_E5_SHIFT                                                 0
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_01_E5                                                       (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_01_E5_SHIFT                                                 8
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_02_E5                                                       (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_02_E5_SHIFT                                                 16
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_03_E5                                                       (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_03_E5_SHIFT                                                 24
+#define YPLD_REG_L2MA_SAME_OFFSET_SET_1_E5                                                                   0x5b0c0cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_10_E5                                                       (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_10_E5_SHIFT                                                 0
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_11_E5                                                       (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_11_E5_SHIFT                                                 8
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_12_E5                                                       (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_12_E5_SHIFT                                                 16
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_13_E5                                                       (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_13_E5_SHIFT                                                 24
+#define YPLD_REG_L2MA_SAME_OFFSET_SET_2_E5                                                                   0x5b0c10UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_20_E5                                                       (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_20_E5_SHIFT                                                 0
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_21_E5                                                       (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_21_E5_SHIFT                                                 8
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_22_E5                                                       (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_22_E5_SHIFT                                                 16
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_23_E5                                                       (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_23_E5_SHIFT                                                 24
+#define YPLD_REG_L2MA_SAME_OFFSET_SET_3_E5                                                                   0x5b0c14UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_30_E5                                                       (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_30_E5_SHIFT                                                 0
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_31_E5                                                       (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_31_E5_SHIFT                                                 8
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_32_E5                                                       (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_32_E5_SHIFT                                                 16
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_33_E5                                                       (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
+  #define YPLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_33_E5_SHIFT                                                 24
+#define YPLD_REG_L2MA_SAME_LEN_SET_0_1_E5                                                                    0x5b0c18UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define YPLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_00_E5                                                           (0xf<<0) // length in 32b units from the same 00 .
+  #define YPLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_00_E5_SHIFT                                                     0
+  #define YPLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_01_E5                                                           (0xf<<4) // length in 32b units from the same 01 .
+  #define YPLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_01_E5_SHIFT                                                     4
+  #define YPLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_02_E5                                                           (0xf<<8) // length in 32b units from the same 02 .
+  #define YPLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_02_E5_SHIFT                                                     8
+  #define YPLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_03_E5                                                           (0xf<<12) // length in 32b units from the same 03 .
+  #define YPLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_03_E5_SHIFT                                                     12
+  #define YPLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_10_E5                                                           (0xf<<16) // length in 32b units from the same 10 .
+  #define YPLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_10_E5_SHIFT                                                     16
+  #define YPLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_11_E5                                                           (0xf<<20) // length in 32b units from the same 11 .
+  #define YPLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_11_E5_SHIFT                                                     20
+  #define YPLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_12_E5                                                           (0xf<<24) // length in 32b units from the same 12 .
+  #define YPLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_12_E5_SHIFT                                                     24
+  #define YPLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_13_E5                                                           (0xf<<28) // length in 32b units from the same 13 .
+  #define YPLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_13_E5_SHIFT                                                     28
+#define YPLD_REG_L2MA_SAME_LEN_SET_2_3_E5                                                                    0x5b0c1cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define YPLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_20_E5                                                           (0xf<<0) // length in 32b units from the same 20 .
+  #define YPLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_20_E5_SHIFT                                                     0
+  #define YPLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_21_E5                                                           (0xf<<4) // length in 32b units from the same 21 .
+  #define YPLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_21_E5_SHIFT                                                     4
+  #define YPLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_22_E5                                                           (0xf<<8) // length in 32b units from the same 22 .
+  #define YPLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_22_E5_SHIFT                                                     8
+  #define YPLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_23_E5                                                           (0xf<<12) // length in 32b units from the same 23 .
+  #define YPLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_23_E5_SHIFT                                                     12
+  #define YPLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_30_E5                                                           (0xf<<16) // length in 32b units from the same 30 .
+  #define YPLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_30_E5_SHIFT                                                     16
+  #define YPLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_31_E5                                                           (0xf<<20) // length in 32b units from the same 31 .
+  #define YPLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_31_E5_SHIFT                                                     20
+  #define YPLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_32_E5                                                           (0xf<<24) // length in 32b units from the same 32 .
+  #define YPLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_32_E5_SHIFT                                                     24
+  #define YPLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_33_E5                                                           (0xf<<28) // length in 32b units from the same 33 .
+  #define YPLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_33_E5_SHIFT                                                     28
+#define YPLD_REG_L2MA_SAME_MASK_SET_0_E5                                                                     0x5b0c20UL //Access:RW   DataWidth:0x20   // bit-mask on the selected 32B same 0 parameters .
+#define YPLD_REG_L2MA_SAME_MASK_SET_1_E5                                                                     0x5b0c24UL //Access:RW   DataWidth:0x20   // bit-mask on the selected 32B same 1 parameters .
+#define YPLD_REG_L2MA_SAME_MASK_SET_2_E5                                                                     0x5b0c28UL //Access:RW   DataWidth:0x20   // bit-mask on the selected 32B same 2 parameters .
+#define YPLD_REG_L2MA_SAME_MASK_SET_3_E5                                                                     0x5b0c2cUL //Access:RW   DataWidth:0x20   // bit-mask on the selected 32B same 3 parameters .
+#define YPLD_REG_L2MA_DUP_OFFSET_SET_0_E5                                                                    0x5b0c30UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_00_E5                                                    (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_00_E5_SHIFT                                              0
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_01_E5                                                    (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_01_E5_SHIFT                                              8
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_02_E5                                                    (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_02_E5_SHIFT                                              16
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_03_E5                                                    (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_03_E5_SHIFT                                              24
+#define YPLD_REG_L2MA_DUP_OFFSET_SET_1_E5                                                                    0x5b0c34UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_10_E5                                                    (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_10_E5_SHIFT                                              0
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_11_E5                                                    (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_11_E5_SHIFT                                              8
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_12_E5                                                    (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_12_E5_SHIFT                                              16
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_13_E5                                                    (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_13_E5_SHIFT                                              24
+#define YPLD_REG_L2MA_DUP_OFFSET_SET_2_E5                                                                    0x5b0c38UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_20_E5                                                    (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_20_E5_SHIFT                                              0
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_21_E5                                                    (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_21_E5_SHIFT                                              8
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_22_E5                                                    (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_22_E5_SHIFT                                              16
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_23_E5                                                    (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_23_E5_SHIFT                                              24
+#define YPLD_REG_L2MA_DUP_OFFSET_SET_3_E5                                                                    0x5b0c3cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_30_E5                                                    (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_30_E5_SHIFT                                              0
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_31_E5                                                    (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_31_E5_SHIFT                                              8
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_32_E5                                                    (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_32_E5_SHIFT                                              16
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_33_E5                                                    (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
+  #define YPLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_33_E5_SHIFT                                              24
+#define YPLD_REG_L2MA_DUP_LEN_SET_0_E5                                                                       0x5b0c40UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define YPLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_00_E5                                                          (0x3f<<0) // length in 32b units from the dup 00 .
+  #define YPLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_00_E5_SHIFT                                                    0
+  #define YPLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_01_E5                                                          (0x3f<<6) // length in 32b units from the dup 01 .
+  #define YPLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_01_E5_SHIFT                                                    6
+  #define YPLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_02_E5                                                          (0x3f<<12) // length in 32b units from the dup 02 .
+  #define YPLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_02_E5_SHIFT                                                    12
+  #define YPLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_03_E5                                                          (0x3f<<18) // length in 32b units from the dup 03 .
+  #define YPLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_03_E5_SHIFT                                                    18
+#define YPLD_REG_L2MA_DUP_LEN_SET_1_E5                                                                       0x5b0c44UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define YPLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_10_E5                                                          (0x3f<<0) // length in 32b units from the dup 10 .
+  #define YPLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_10_E5_SHIFT                                                    0
+  #define YPLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_11_E5                                                          (0x3f<<6) // length in 32b units from the dup 11 .
+  #define YPLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_11_E5_SHIFT                                                    6
+  #define YPLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_12_E5                                                          (0x3f<<12) // length in 32b units from the dup 12 .
+  #define YPLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_12_E5_SHIFT                                                    12
+  #define YPLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_13_E5                                                          (0x3f<<18) // length in 32b units from the dup 13 .
+  #define YPLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_13_E5_SHIFT                                                    18
+#define YPLD_REG_L2MA_DUP_LEN_SET_2_E5                                                                       0x5b0c48UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define YPLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_20_E5                                                          (0x3f<<0) // length in 32b units from the dup 20 .
+  #define YPLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_20_E5_SHIFT                                                    0
+  #define YPLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_21_E5                                                          (0x3f<<6) // length in 32b units from the dup 21 .
+  #define YPLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_21_E5_SHIFT                                                    6
+  #define YPLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_22_E5                                                          (0x3f<<12) // length in 32b units from the dup 22 .
+  #define YPLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_22_E5_SHIFT                                                    12
+  #define YPLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_23_E5                                                          (0x3f<<18) // length in 32b units from the dup 23 .
+  #define YPLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_23_E5_SHIFT                                                    18
+#define YPLD_REG_L2MA_DUP_LEN_SET_3_E5                                                                       0x5b0c4cUL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define YPLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_30_E5                                                          (0x3f<<0) // length in 32b units from the dup 30 .
+  #define YPLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_30_E5_SHIFT                                                    0
+  #define YPLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_31_E5                                                          (0x3f<<6) // length in 32b units from the dup 31 .
+  #define YPLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_31_E5_SHIFT                                                    6
+  #define YPLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_32_E5                                                          (0x3f<<12) // length in 32b units from the dup 32 .
+  #define YPLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_32_E5_SHIFT                                                    12
+  #define YPLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_33_E5                                                          (0x3f<<18) // length in 32b units from the dup 33 .
+  #define YPLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_33_E5_SHIFT                                                    18
+#define YPLD_REG_L2MA_FLOW_ID_E5                                                                             0x5b0c50UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_0_E5                                                         (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
+  #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_0_E5_SHIFT                                                   0
+  #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_1_E5                                                         (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
+  #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_1_E5_SHIFT                                                   1
+  #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_2_E5                                                         (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
+  #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_2_E5_SHIFT                                                   2
+  #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_3_E5                                                         (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
+  #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_3_E5_SHIFT                                                   3
+  #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_0_E5                                                          (0x1f<<4) // offset of the flow-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of the incoming message (i.e. max value is 23). This parameter is NA if FlowIdInclude is reset. For set 0 .
+  #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_0_E5_SHIFT                                                    4
+  #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_1_E5                                                          (0x1f<<9) // offset of the flow-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of the incoming message (i.e. max value is 23). This parameter is NA if FlowIdInclude is reset. For set 1 .
+  #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_1_E5_SHIFT                                                    9
+  #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_2_E5                                                          (0x1f<<14) // offset of the flow-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of the incoming message (i.e. max value is 23). This parameter is NA if FlowIdInclude is reset. For set 2 .
+  #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_2_E5_SHIFT                                                    14
+  #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_3_E5                                                          (0x1f<<19) // offset of the flow-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of the incoming message (i.e. max value is 23). This parameter is NA if FlowIdInclude is reset. For set 3 .
+  #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_3_E5_SHIFT                                                    19
+#define YPLD_REG_L2MA_SN_OFFSET_E5                                                                           0x5b0c54UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define YPLD_REG_L2MA_SN_OFFSET_SN_OFFSET_0_E5                                                             (0xff<<0) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 0.
+  #define YPLD_REG_L2MA_SN_OFFSET_SN_OFFSET_0_E5_SHIFT                                                       0
+  #define YPLD_REG_L2MA_SN_OFFSET_SN_OFFSET_1_E5                                                             (0xff<<8) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 1.
+  #define YPLD_REG_L2MA_SN_OFFSET_SN_OFFSET_1_E5_SHIFT                                                       8
+  #define YPLD_REG_L2MA_SN_OFFSET_SN_OFFSET_2_E5                                                             (0xff<<16) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 2.
+  #define YPLD_REG_L2MA_SN_OFFSET_SN_OFFSET_2_E5_SHIFT                                                       16
+  #define YPLD_REG_L2MA_SN_OFFSET_SN_OFFSET_3_E5                                                             (0xff<<24) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 3.
+  #define YPLD_REG_L2MA_SN_OFFSET_SN_OFFSET_3_E5_SHIFT                                                       24
+#define YPLD_REG_L2MA_MAX_L2MA_CHILD_E5                                                                      0x5b0c58UL //Access:RW   DataWidth:0x10   // Multi Field Register.
+  #define YPLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_0_E5                                                         (0xf<<0) // the maximal number of children in a specific aggregation. for set 0.
+  #define YPLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_0_E5_SHIFT                                                   0
+  #define YPLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_1_E5                                                         (0xf<<4) // the maximal number of children in a specific aggregation. for set 1.
+  #define YPLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_1_E5_SHIFT                                                   4
+  #define YPLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_2_E5                                                         (0xf<<8) // the maximal number of children in a specific aggregation. for set 2.
+  #define YPLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_2_E5_SHIFT                                                   8
+  #define YPLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_3_E5                                                         (0xf<<12) // the maximal number of children in a specific aggregation. for set 3.
+  #define YPLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_3_E5_SHIFT                                                   12
+#define YPLD_REG_L2MA_INC_L2MA_EVENT_ID_E5                                                                   0x5b0c5cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define YPLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_0_E5                                                  (0xff<<0) // The value by which to increment the event-ID in case of successful aggregation. for set 0.
+  #define YPLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_0_E5_SHIFT                                            0
+  #define YPLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_1_E5                                                  (0xff<<8) // The value by which to increment the event-ID in case of successful aggregation. for set 1.
+  #define YPLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_1_E5_SHIFT                                            8
+  #define YPLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_2_E5                                                  (0xff<<16) // The value by which to increment the event-ID in case of successful aggregation. for set 2.
+  #define YPLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_2_E5_SHIFT                                            16
+  #define YPLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_3_E5                                                  (0xff<<24) // The value by which to increment the event-ID in case of successful aggregation. for set 3.
+  #define YPLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_3_E5_SHIFT                                            24
+#define YPLD_REG_LD_MAX_MSG_SIZE_E5                                                                          0x5b0c60UL //Access:RW   DataWidth:0x4    // maximum loader size in 256 bit words
+#define YPLD_REG_DBG_SELECT_E5                                                                               0x5b1600UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define YPLD_REG_DBG_DWORD_ENABLE_E5                                                                         0x5b1604UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define YPLD_REG_DBG_SHIFT_E5                                                                                0x5b1608UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define YPLD_REG_DBG_FORCE_VALID_E5                                                                          0x5b160cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define YPLD_REG_DBG_FORCE_FRAME_E5                                                                          0x5b1610UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define YPLD_REG_DBG_OUT_DATA_E5                                                                             0x5b1620UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define YPLD_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define YPLD_REG_DBG_OUT_VALID_E5                                                                            0x5b1640UL //Access:R    DataWidth:0x4    // Dbgmux output valid
+#define YPLD_REG_DBG_OUT_FRAME_E5                                                                            0x5b1644UL //Access:R    DataWidth:0x4    // Dbgmux output frame
+#define YPLD_REG_FIC_INPUT_FIFO_E5                                                                           0x5b2000UL //Access:WB   DataWidth:0x80   // Access to input FIC FIFO
+#define YPLD_REG_FIC_INPUT_FIFO_SIZE                                                                         176
+#define YPLD_REG_QUEUE_MSG_MEM_E5                                                                            0x5c0000UL //Access:WB   DataWidth:0x80   // Debug access to The message queue memory.
+#define YPLD_REG_QUEUE_MSG_MEM_SIZE                                                                          7500
+#define WOL_REG_INT_STS_0_K2_E5                                                                              0x600040UL //Access:R    DataWidth:0x1    // Multi Field Register.
+  #define WOL_REG_INT_STS_0_ADDRESS_ERROR_K2_E5                                                              (0x1<<0) // Signals an unknown address to the RF module.
+  #define WOL_REG_INT_STS_0_ADDRESS_ERROR_K2_E5_SHIFT                                                        0
+#define WOL_REG_INT_MASK_0_K2_E5                                                                             0x600044UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define WOL_REG_INT_MASK_0_ADDRESS_ERROR_K2_E5                                                             (0x1<<0) // This bit masks, when set, the Interrupt bit: WOL_REG_INT_STS_0.ADDRESS_ERROR .
+  #define WOL_REG_INT_MASK_0_ADDRESS_ERROR_K2_E5_SHIFT                                                       0
+#define WOL_REG_INT_STS_WR_0_K2_E5                                                                           0x600048UL //Access:WR   DataWidth:0x1    // Multi Field Register.
+  #define WOL_REG_INT_STS_WR_0_ADDRESS_ERROR_K2_E5                                                           (0x1<<0) // Signals an unknown address to the RF module.
+  #define WOL_REG_INT_STS_WR_0_ADDRESS_ERROR_K2_E5_SHIFT                                                     0
+#define WOL_REG_INT_STS_CLR_0_K2_E5                                                                          0x60004cUL //Access:RC   DataWidth:0x1    // Multi Field Register.
+  #define WOL_REG_INT_STS_CLR_0_ADDRESS_ERROR_K2_E5                                                          (0x1<<0) // Signals an unknown address to the RF module.
+  #define WOL_REG_INT_STS_CLR_0_ADDRESS_ERROR_K2_E5_SHIFT                                                    0
+#define WOL_REG_DBG_SELECT_K2_E5                                                                             0x600140UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define WOL_REG_DBG_DWORD_ENABLE_K2_E5                                                                       0x600144UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define WOL_REG_DBG_SHIFT_K2_E5                                                                              0x600148UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define WOL_REG_DBG_FORCE_VALID_K2_E5                                                                        0x60014cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define WOL_REG_DBG_FORCE_FRAME_K2_E5                                                                        0x600150UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define WOL_REG_DBG_OUT_DATA_K2_E5                                                                           0x600160UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define WOL_REG_DBG_OUT_DATA_SIZE                                                                            8
+#define WOL_REG_DBG_OUT_VALID_K2_E5                                                                          0x600180UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define WOL_REG_DBG_OUT_FRAME_K2_E5                                                                          0x600184UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define WOL_REG_PRTY_MASK_H_0_K2                                                                             0x600204UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define WOL_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2                                                         (0x1<<0) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
+  #define WOL_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_SHIFT                                                   0
+  #define WOL_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2                                                         (0x1<<1) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
+  #define WOL_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2_SHIFT                                                   1
+  #define WOL_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2                                                         (0x1<<2) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
+  #define WOL_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_SHIFT                                                   2
+  #define WOL_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2                                                         (0x1<<3) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
+  #define WOL_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2_SHIFT                                                   3
+  #define WOL_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2                                                         (0x1<<4) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
+  #define WOL_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2_SHIFT                                                   4
+  #define WOL_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_K2                                                         (0x1<<5) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
+  #define WOL_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_K2_SHIFT                                                   5
+  #define WOL_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2                                                         (0x1<<6) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
+  #define WOL_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2_SHIFT                                                   6
+  #define WOL_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2                                                         (0x1<<7) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
+  #define WOL_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2_SHIFT                                                   7
+  #define WOL_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_K2                                                         (0x1<<8) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define WOL_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_K2_SHIFT                                                   8
+  #define WOL_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2                                                         (0x1<<9) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define WOL_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_SHIFT                                                   9
+  #define WOL_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2                                                         (0x1<<10) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define WOL_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2_SHIFT                                                   10
+  #define WOL_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2                                                         (0x1<<11) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
+  #define WOL_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2_SHIFT                                                   11
+  #define WOL_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2                                                         (0x1<<12) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
+  #define WOL_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2_SHIFT                                                   12
+  #define WOL_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2                                                         (0x1<<13) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
+  #define WOL_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2_SHIFT                                                   13
+  #define WOL_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2                                                         (0x1<<14) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
+  #define WOL_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2_SHIFT                                                   14
+  #define WOL_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2                                                         (0x1<<15) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
+  #define WOL_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2_SHIFT                                                   15
+  #define WOL_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2                                                         (0x1<<16) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
+  #define WOL_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2_SHIFT                                                   16
+  #define WOL_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2                                                         (0x1<<17) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
+  #define WOL_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2_SHIFT                                                   17
+  #define WOL_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2                                                         (0x1<<18) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define WOL_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_SHIFT                                                   18
+  #define WOL_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2                                                         (0x1<<19) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define WOL_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_SHIFT                                                   19
+  #define WOL_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2                                                         (0x1<<20) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define WOL_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_SHIFT                                                   20
+  #define WOL_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2                                                         (0x1<<21) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define WOL_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2_SHIFT                                                   21
+  #define WOL_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2                                                         (0x1<<22) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define WOL_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_SHIFT                                                   22
+  #define WOL_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2                                                         (0x1<<23) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define WOL_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_SHIFT                                                   23
+#define WOL_REG_MEM_ECC_EVENTS_K2                                                                            0x600210UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define WOL_REG_ACPI_TAG_RM_K2_E5                                                                            0x608000UL //Access:RW   DataWidth:0x8    // This is a per-port per-PF register.  L2 tag removal configuration for ACPI.  Bit mapped as follow: bit 0: 5 - L2 tags 0 to 5. Bit 6 is reserved and should be set to 0.  Bit 7 is for LLC/SNAP.  Set these bits to 1's to enable the removal of the corresponding tag when it is present in the  packet.  Clear the bit to keep the tag in the  packet.
+#define WOL_REG_UPON_MGMT_K2_E5                                                                              0x608004UL //Access:RW   DataWidth:0x1    // Set this bit to enable ACPI and TCP SYN matching even when the packet is forwarded to MCP.  Clear this bit to disable ACPI and TCP SYN matching when the packet is forwarded to MCP.
+#define WOL_REG_ACPI_BE_MEM_K2_E5                                                                            0x608080UL //Access:WB   DataWidth:0x100  // This is a per-port per-PF register.  Byte enable memory for 8 ACPI patterns.
+#define WOL_REG_ACPI_BE_MEM_SIZE                                                                             32
+#define WOL_REG_ACPI_ENABLE_K2_E5                                                                            0x608100UL //Access:RW   DataWidth:0x1    // This is a per-port register.  When this bit is set  ACPI packet recognition will be enabled. This bit must not be enabled until after all other ACPI registers were configured.
+#define WOL_REG_ACPI_PAT_0_CRC_K2_E5                                                                         0x608104UL //Access:RW   DataWidth:0x20   // This is a per-port per-PF register.  CRC32C for pattern 0.
+#define WOL_REG_ACPI_PAT_0_LEN_K2_E5                                                                         0x608108UL //Access:RW   DataWidth:0x8    // This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.
+#define WOL_REG_ACPI_PAT_1_CRC_K2_E5                                                                         0x60810cUL //Access:RW   DataWidth:0x20   // This is a per-port per-PF register.  CRC32C for pattern 1.
+#define WOL_REG_ACPI_PAT_1_LEN_K2_E5                                                                         0x608110UL //Access:RW   DataWidth:0x8    // This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.
+#define WOL_REG_ACPI_PAT_2_CRC_K2_E5                                                                         0x608114UL //Access:RW   DataWidth:0x20   // This is a per-port per-PF register.  CRC32C for pattern 2.
+#define WOL_REG_ACPI_PAT_2_LEN_K2_E5                                                                         0x608118UL //Access:RW   DataWidth:0x8    // This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.
+#define WOL_REG_ACPI_PAT_3_CRC_K2_E5                                                                         0x60811cUL //Access:RW   DataWidth:0x20   // This is a per-port per-PF register.  CRC32C for pattern 3.
+#define WOL_REG_ACPI_PAT_3_LEN_K2_E5                                                                         0x608120UL //Access:RW   DataWidth:0x8    // This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.
+#define WOL_REG_ACPI_PAT_4_CRC_K2_E5                                                                         0x608124UL //Access:RW   DataWidth:0x20   // This is a per-port per-PF register.  CRC32C for pattern 4.
+#define WOL_REG_ACPI_PAT_4_LEN_K2_E5                                                                         0x608128UL //Access:RW   DataWidth:0x8    // This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.
+#define WOL_REG_ACPI_PAT_5_CRC_K2_E5                                                                         0x60812cUL //Access:RW   DataWidth:0x20   // This is a per-port per-PF register.  CRC32C for pattern 5.
+#define WOL_REG_ACPI_PAT_5_LEN_K2_E5                                                                         0x608130UL //Access:RW   DataWidth:0x8    // This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.
+#define WOL_REG_ACPI_PAT_6_CRC_K2_E5                                                                         0x608134UL //Access:RW   DataWidth:0x20   // This is a per-port per-PF register.  CRC32C for pattern 6.
+#define WOL_REG_ACPI_PAT_6_LEN_K2_E5                                                                         0x608138UL //Access:RW   DataWidth:0x8    // This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.
+#define WOL_REG_ACPI_PAT_7_CRC_K2_E5                                                                         0x60813cUL //Access:RW   DataWidth:0x20   // This is a per-port per-PF register.  CRC32C for pattern 7.
+#define WOL_REG_ACPI_PAT_7_LEN_K2_E5                                                                         0x608140UL //Access:RW   DataWidth:0x8    // This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.
+#define WOL_REG_MPKT_ENABLE_K2_E5                                                                            0x608144UL //Access:RW   DataWidth:0x1    // This is a per-port per-PF register.  When this bit is set  Magic Packet recognition will be enabled. This bit must not be enabled until after after all other Magic Packet registers are configured.
+#define WOL_REG_MPKT_MAC_ADDR_K2_E5                                                                          0x608148UL //Access:WB   DataWidth:0x30   // This is a per-port per-PF register.  MAC address for Magic Packet detection.
+#define WOL_REG_MPKT_MAC_ADDR_SIZE                                                                           2
+#define WOL_REG_FORCE_WOL_K2_E5                                                                              0x608150UL //Access:RW   DataWidth:0x1    // This is a per-port per-PF register.  A low-to-high transition of this bit forces a wake event.
+#define WOL_REG_WAKE_BUFFER_K2_E5                                                                            0x608160UL //Access:WB_R DataWidth:0x100  // Read-only data from the Wake Buffer (organized as a FIFO).
+#define WOL_REG_WAKE_BUFFER_SIZE                                                                             8
+#define WOL_REG_WAKE_BUFFER_CLEAR_K2_E5                                                                      0x608180UL //Access:RW   DataWidth:0x1    // Clear the Wake Buffer and Status - a low-to-high transition of this bit clears the wake_info, wake_pkt_len, and wake_details registers and allows the wake buffer to be overwritten, thereby re-enabling pattern detection.
+#define WOL_REG_WAKE_INFO_K2_E5                                                                              0x608184UL //Access:R    DataWidth:0x15   // Wake information register - all fields are sticky.  Bits  15:0 - PF Vector: The bit-mapped vector indicating which of the global PFs detected the wake event.  More than 1 bit may be set. Bit 16 - ACPI RCVD:  This bit is set when an ACPI packet is received. This is an OR of the results from the 8 functions. Bit 17 - MPKT:  This bit is set when a Magic packet is received. This is an OR of the results from the 8 functions. Bit 18 - TCP SYN RCVD:  This bit is set when TCP SYN packet is received. This is an OR of the results from the 8 functions. Bit 19 - FORCE RCVD:  This bit is set when force WOL event is received. This is an OR of the results from the 8 functions. Bit 20 - BUFFER NOT EMPTY:  This bit  is set when the buffer has the 'wake' packet. All fields are cleared by wake_buffer_clear or during a Hard Reset only. Core Reset has no effect on these fields.
+#define WOL_REG_WAKE_PKT_LEN_K2_E5                                                                           0x608188UL //Access:R    DataWidth:0xe    // Wake packet length - the actual length of the 'wake' packet, in bytes. This register is sticky and is cleared by wake_buffer_clear or during a Hard Reset only. Core Reset has no effect on this register.
+#define WOL_REG_WAKE_DETAILS_K2_E5                                                                           0x60818cUL //Access:R    DataWidth:0x20   // Wake detail register - all fields are sticky.  Bits 7:0   - ACPI MATCH:  Per-function bit-mapped result from ACPI pattern match. Bits 15:8  - MPKT MATCH:  Per-function bit-mapped result from Magic packet pattern match. Bits 23:16 - TCP SYN MATCH:  Per-function bit-mapped result from TCP SYN match. Bits 31:24 - FORCE WOL MATCH:  Per-function bit-mapped result from force WOL match. All fields are cleared by wake_buffer_clear or during a Hard Reset only. Core Reset has no effect on these fields.
+#define WOL_REG_ACPI_DEFAULT_PF_SEL_K2_E5                                                                    0x608190UL //Access:RW   DataWidth:0x3    // This bit selects the default PF for selecting the ACPI patterns.
+#define WOL_REG_ACPI_PAT_SEL_K2_E5                                                                           0x608194UL //Access:RW   DataWidth:0x2    // These two bits select which pattern will be chosen for the ACPI CRC matching: 0: Select patterns based on LLH PF classification. 1: Select patterns based on static PF selection - acpi_default_pf_sel. 2: Select the first of each: 2 ports (quad_port_mode is 0) - use one of each PF. 4 ports (quad_port_mode is 1) - use two of each PF. 3: reserved.
+#define WOL_REG_TCP_SYN_ENABLE_K2_E5                                                                         0x608198UL //Access:RW   DataWidth:0x2    // This is a per-PF register.  Set bit 0 to enable wake on IPv4 TCP SYN. Set bit 1 to enable wake on IPv6 TCP SYN. These bits must not be set until after after all other registers needed for this feature are configured.
+#define WOL_REG_TAG_LEN_0_K2_E5                                                                              0x60819cUL //Access:RW   DataWidth:0x3    // The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.
+#define WOL_REG_TAG_LEN_1_K2_E5                                                                              0x6081a0UL //Access:RW   DataWidth:0x3    // The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.
+#define WOL_REG_TAG_LEN_2_K2_E5                                                                              0x6081a4UL //Access:RW   DataWidth:0x3    // The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.
+#define WOL_REG_TAG_LEN_3_K2_E5                                                                              0x6081a8UL //Access:RW   DataWidth:0x3    // The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.
+#define WOL_REG_TAG_LEN_4_K2_E5                                                                              0x6081acUL //Access:RW   DataWidth:0x3    // The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.
+#define WOL_REG_TAG_LEN_5_K2_E5                                                                              0x6081b0UL //Access:RW   DataWidth:0x3    // The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.
+#define WOL_REG_WAKE_MEM_RD_OFFSET_K2_E5                                                                     0x6081b4UL //Access:R    DataWidth:0x3    // This is the current offset of the read pointer in the wake buffer.
+#define WOL_REG_ECO_RESERVED_K2_E5                                                                           0x6081b8UL //Access:RW   DataWidth:0x8    // Reserved bits for ECO.
+#define WOL_REG_ECO_RESERVED_PERPORT_K2_E5                                                                   0x6081bcUL //Access:RW   DataWidth:0x8    // Reserved bits for ECO.
+#define WOL_REG_HDR_FIFO_EMPTY_K2_E5                                                                         0x6081c0UL //Access:R    DataWidth:0x1    // WOL header FIFO empty status.
+#define WOL_REG_HDR_FIFO_FULL_K2_E5                                                                          0x6081c4UL //Access:R    DataWidth:0x1    // WOL header FIFO full status.
+#define WOL_REG_HDR_FIFO_ERROR_K2_E5                                                                         0x6081c8UL //Access:R    DataWidth:0x1    // WOL header FIFO error status.
+#define BMBN_REG_INT_STS_0_K2_E5                                                                             0x610040UL //Access:R    DataWidth:0x1    // Multi Field Register.
+  #define BMBN_REG_INT_STS_0_ADDRESS_ERROR_K2_E5                                                             (0x1<<0) // Signals an unknown address to the RF module.
+  #define BMBN_REG_INT_STS_0_ADDRESS_ERROR_K2_E5_SHIFT                                                       0
+#define BMBN_REG_INT_MASK_0_K2_E5                                                                            0x610044UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define BMBN_REG_INT_MASK_0_ADDRESS_ERROR_K2_E5                                                            (0x1<<0) // This bit masks, when set, the Interrupt bit: BMBN_REG_INT_STS_0.ADDRESS_ERROR .
+  #define BMBN_REG_INT_MASK_0_ADDRESS_ERROR_K2_E5_SHIFT                                                      0
+#define BMBN_REG_INT_STS_WR_0_K2_E5                                                                          0x610048UL //Access:WR   DataWidth:0x1    // Multi Field Register.
+  #define BMBN_REG_INT_STS_WR_0_ADDRESS_ERROR_K2_E5                                                          (0x1<<0) // Signals an unknown address to the RF module.
+  #define BMBN_REG_INT_STS_WR_0_ADDRESS_ERROR_K2_E5_SHIFT                                                    0
+#define BMBN_REG_INT_STS_CLR_0_K2_E5                                                                         0x61004cUL //Access:RC   DataWidth:0x1    // Multi Field Register.
+  #define BMBN_REG_INT_STS_CLR_0_ADDRESS_ERROR_K2_E5                                                         (0x1<<0) // Signals an unknown address to the RF module.
+  #define BMBN_REG_INT_STS_CLR_0_ADDRESS_ERROR_K2_E5_SHIFT                                                   0
+#define BMBN_REG_DBG_SELECT_K2_E5                                                                            0x610140UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define BMBN_REG_DBG_DWORD_ENABLE_K2_E5                                                                      0x610144UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define BMBN_REG_DBG_SHIFT_K2_E5                                                                             0x610148UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define BMBN_REG_DBG_FORCE_VALID_K2_E5                                                                       0x61014cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define BMBN_REG_DBG_FORCE_FRAME_K2_E5                                                                       0x610150UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define BMBN_REG_DBG_OUT_DATA_K2_E5                                                                          0x610160UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define BMBN_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define BMBN_REG_DBG_OUT_VALID_K2_E5                                                                         0x610180UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define BMBN_REG_DBG_OUT_FRAME_K2_E5                                                                         0x610184UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define BMBN_REG_MNG_OUTER_TAG0_0_K2_E5                                                                      0x6101e0UL //Access:RW   DataWidth:0x20   // Value of outer tag to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.
+#define BMBN_REG_MNG_OUTER_TAG0_1_K2_E5                                                                      0x6101e4UL //Access:RW   DataWidth:0x20   // Value of outer tag to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.
+#define BMBN_REG_MNG_OUTER_TAG1_0_K2_E5                                                                      0x6101e8UL //Access:RW   DataWidth:0x20   // Value of outer tag to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.
+#define BMBN_REG_MNG_OUTER_TAG1_1_K2_E5                                                                      0x6101ecUL //Access:RW   DataWidth:0x20   // Value of outer tag to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.
+#define BMBN_REG_MNG_INNER_VLAN_TAG0_K2_E5                                                                   0x6101f0UL //Access:RW   DataWidth:0x10   // Value of inner VLAN tag to be used in tag insertion/override for management packets.  This field consists of {3-bit priority, 1-bit drop eligible, 12-bit VLAN ID}.
+#define BMBN_REG_MNG_INNER_VLAN_TAG1_K2_E5                                                                   0x6101f4UL //Access:RW   DataWidth:0x10   // Value of inner VLAN tag to be used in tag insertion/override for management packets.  This field consists of {3-bit priority, 1-bit drop eligible, 12-bit VLAN ID}.
+#define BMBN_REG_TAG_LEN_0_K2_E5                                                                             0x6101f8UL //Access:RW   DataWidth:0x3    // The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.
+#define BMBN_REG_TAG_ETHERTYPE_1_K2_E5                                                                       0x6101fcUL //Access:RW   DataWidth:0x10   // The Ethernet type value for L2 tag 1.  The reset value is 9x8100 for inner VLAN.
+#define BMBN_REG_ECO_RESERVED_K2_E5                                                                          0x610200UL //Access:RW   DataWidth:0x8    // Reserved bits for ECO.
+#define BMBN_REG_ECO_RESERVED_PERPORT_K2_E5                                                                  0x610204UL //Access:RW   DataWidth:0x8    // Reserved bits for ECO.
+#define PHY_PCIE_REG_PHY0_K2_E5                                                                              0x620000UL //Access:RW   DataWidth:0x10   // AHB bus for pcie_phy 0.
+#define PHY_PCIE_REG_PHY0_SIZE                                                                               4096
+#define PHY_PCIE_REG_PHY1_K2_E5                                                                              0x624000UL //Access:RW   DataWidth:0x10   // AHB bus for pcie_phy 1.
+#define PHY_PCIE_REG_PHY1_SIZE                                                                               4096
+#define PHY_PCIE_REG_ECO_RESERVED_K2_E5                                                                      0x628000UL //Access:RW   DataWidth:0x20   // 
+#define PHY_PCIE_REG_PHY_REFCLK_SELECT_K2_E5                                                                 0x628004UL //Access:RW   DataWidth:0xe    // Multi Field Register.
+  #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_INPUT_SEL_I_K2_E5                                   (0x3<<0) // 
+  #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_INPUT_SEL_I_K2_E5_SHIFT                             0
+  #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_OE_L_I_K2_E5                                        (0x1<<2) // 
+  #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_OE_L_I_K2_E5_SHIFT                                  2
+  #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_QFWD_L_I_K2_E5                                      (0x1<<3) // 
+  #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_QFWD_L_I_K2_E5_SHIFT                                3
+  #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_OE_R_I_K2_E5                                        (0x1<<4) // 
+  #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_OE_R_I_K2_E5_SHIFT                                  4
+  #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_QFWD_R_I_K2_E5                                      (0x1<<5) // 
+  #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_QFWD_R_I_K2_E5_SHIFT                                5
+  #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_SEL_I_K2_E5                                         (0x1<<6) // 
+  #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_SEL_I_K2_E5_SHIFT                                   6
+  #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_INPUT_SEL_I_K2_E5                                   (0x3<<7) // 
+  #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_INPUT_SEL_I_K2_E5_SHIFT                             7
+  #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_OE_L_I_K2_E5                                        (0x1<<9) // 
+  #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_OE_L_I_K2_E5_SHIFT                                  9
+  #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_QFWD_L_I_K2_E5                                      (0x1<<10) // 
+  #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_QFWD_L_I_K2_E5_SHIFT                                10
+  #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_OE_R_I_K2_E5                                        (0x1<<11) // 
+  #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_OE_R_I_K2_E5_SHIFT                                  11
+  #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_QFWD_R_I_K2_E5                                      (0x1<<12) // 
+  #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_QFWD_R_I_K2_E5_SHIFT                                12
+  #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_SEL_I_K2_E5                                         (0x1<<13) // 
+  #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_SEL_I_K2_E5_SHIFT                                   13
+#define PHY_PCIE_REG_PHY_REFCLK_CONTROL_K2_E5                                                                0x628008UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_CMU_CK_SOC_DIV_I_K2_E5                                             (0x3<<0) // 
+  #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_CMU_CK_SOC_DIV_I_K2_E5_SHIFT                                       0
+  #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY0_CMU_PD_I_K2_E5                                                (0x1<<2) // 
+  #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY0_CMU_PD_I_K2_E5_SHIFT                                          2
+  #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY1_CMU_PD_I_K2_E5                                                (0x1<<3) // 
+  #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY1_CMU_PD_I_K2_E5_SHIFT                                          3
+  #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY0_CMU_IDDQ_I_K2_E5                                              (0x1<<4) // 
+  #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY0_CMU_IDDQ_I_K2_E5_SHIFT                                        4
+  #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY1_CMU_IDDQ_I_K2_E5                                              (0x1<<5) // 
+  #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY1_CMU_IDDQ_I_K2_E5_SHIFT                                        5
+  #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY0_REFCLK_GATE_I_K2_E5                                           (0x1<<6) // 
+  #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY0_REFCLK_GATE_I_K2_E5_SHIFT                                     6
+  #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY1_REFCLK_GATE_I_K2_E5                                           (0x1<<7) // 
+  #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY1_REFCLK_GATE_I_K2_E5_SHIFT                                     7
+#define PHY_PCIE_REG_SOFT_RESET_CONTROL_K2_E5                                                                0x62800cUL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PHY_PCIE_REG_SOFT_RESET_CONTROL_SOFT_PWR_RST_N_K2_E5                                               (0x1<<0) // 
+  #define PHY_PCIE_REG_SOFT_RESET_CONTROL_SOFT_PWR_RST_N_K2_E5_SHIFT                                         0
+  #define PHY_PCIE_REG_SOFT_RESET_CONTROL_SOFT_PHY_RST_N_K2_E5                                               (0x1<<1) // 
+  #define PHY_PCIE_REG_SOFT_RESET_CONTROL_SOFT_PHY_RST_N_K2_E5_SHIFT                                         1
+#define PHY_PCIE_REG_PHY_RESET_CONTROL_K2_E5                                                                 0x628010UL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define PHY_PCIE_REG_PHY_RESET_CONTROL_LNX_RSTN_I_K2_E5                                                    (0xff<<0) // Firmware must set this bit to 1 after finished configuring PCIe Serdes AHB registers to bring Serdes channel out of reset
+  #define PHY_PCIE_REG_PHY_RESET_CONTROL_LNX_RSTN_I_K2_E5_SHIFT                                              0
+  #define PHY_PCIE_REG_PHY_RESET_CONTROL_CMU_RESETN_I_K2_E5                                                  (0x1<<8) // Firmware must set this bit to 1 after finished configuring PCIe Serdes AHB registers to bring Serdes CMU out of reset
+  #define PHY_PCIE_REG_PHY_RESET_CONTROL_CMU_RESETN_I_K2_E5_SHIFT                                            8
+#define PHY_PCIE_REG_PHY_STATUS_K2_E5                                                                        0x628014UL //Access:R    DataWidth:0xc    // Multi Field Register.
+  #define PHY_PCIE_REG_PHY_STATUS_PHY0_CMU_OK_O_K2_E5                                                        (0x1<<0) // 
+  #define PHY_PCIE_REG_PHY_STATUS_PHY0_CMU_OK_O_K2_E5_SHIFT                                                  0
+  #define PHY_PCIE_REG_PHY_STATUS_PHY1_CMU_OK_O_K2_E5                                                        (0x1<<1) // 
+  #define PHY_PCIE_REG_PHY_STATUS_PHY1_CMU_OK_O_K2_E5_SHIFT                                                  1
+  #define PHY_PCIE_REG_PHY_STATUS_PHY0_REFCLK_GATE_ACK_O_K2_E5                                               (0x1<<2) // 
+  #define PHY_PCIE_REG_PHY_STATUS_PHY0_REFCLK_GATE_ACK_O_K2_E5_SHIFT                                         2
+  #define PHY_PCIE_REG_PHY_STATUS_PHY1_REFCLK_GATE_ACK_O_K2_E5                                               (0x1<<3) // 
+  #define PHY_PCIE_REG_PHY_STATUS_PHY1_REFCLK_GATE_ACK_O_K2_E5_SHIFT                                         3
+  #define PHY_PCIE_REG_PHY_STATUS_PHY_MAC_PHYSTATUS_K2_E5                                                    (0xff<<4) // 
+  #define PHY_PCIE_REG_PHY_STATUS_PHY_MAC_PHYSTATUS_K2_E5_SHIFT                                              4
+#define PHY_PCIE_REG_PCS_CONTROL_1_K2_E5                                                                     0x628018UL //Access:RW   DataWidth:0x10   // Bit masks to be ANDed with cxpl_debug_info_ei[15:0] to control glue_mac_init_info_i[15:0] of PCIe PHY
+#define PHY_PCIE_REG_PCS_CONTROL_2_K2_E5                                                                     0x62801cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PHY_PCIE_REG_PCS_CONTROL_2_LNX_RXSIG_DET_MASK_I_K2_E5                                              (0xff<<0) // 
+  #define PHY_PCIE_REG_PCS_CONTROL_2_LNX_RXSIG_DET_MASK_I_K2_E5_SHIFT                                        0
+  #define PHY_PCIE_REG_PCS_CONTROL_2_LNX_RXEII_EXIT_TYPE_I_K2_E5                                             (0xff<<8) // 
+  #define PHY_PCIE_REG_PCS_CONTROL_2_LNX_RXEII_EXIT_TYPE_I_K2_E5_SHIFT                                       8
+  #define PHY_PCIE_REG_PCS_CONTROL_2_LNX_RXEI_INFER_I_K2_E5                                                  (0xff<<16) // 
+  #define PHY_PCIE_REG_PCS_CONTROL_2_LNX_RXEI_INFER_I_K2_E5_SHIFT                                            16
+  #define PHY_PCIE_REG_PCS_CONTROL_2_LNX_IDDQ_I_K2_E5                                                        (0xff<<24) // 
+  #define PHY_PCIE_REG_PCS_CONTROL_2_LNX_IDDQ_I_K2_E5_SHIFT                                                  24
+#define PHY_PCIE_REG_PCIE_PHY0_ASTAT_K2_E5                                                                   0x628020UL //Access:R    DataWidth:0x18   // Multi Field Register.
+  #define PHY_PCIE_REG_PCIE_PHY0_ASTAT_LN0_ASTAT_O_K2_E5                                                     (0x3f<<0) // 
+  #define PHY_PCIE_REG_PCIE_PHY0_ASTAT_LN0_ASTAT_O_K2_E5_SHIFT                                               0
+  #define PHY_PCIE_REG_PCIE_PHY0_ASTAT_LN1_ASTAT_O_K2_E5                                                     (0x3f<<6) // 
+  #define PHY_PCIE_REG_PCIE_PHY0_ASTAT_LN1_ASTAT_O_K2_E5_SHIFT                                               6
+  #define PHY_PCIE_REG_PCIE_PHY0_ASTAT_LN2_ASTAT_O_K2_E5                                                     (0x3f<<12) // 
+  #define PHY_PCIE_REG_PCIE_PHY0_ASTAT_LN2_ASTAT_O_K2_E5_SHIFT                                               12
+  #define PHY_PCIE_REG_PCIE_PHY0_ASTAT_LN3_ASTAT_O_K2_E5                                                     (0x3f<<18) // 
+  #define PHY_PCIE_REG_PCIE_PHY0_ASTAT_LN3_ASTAT_O_K2_E5_SHIFT                                               18
+#define PHY_PCIE_REG_PCIE_PHY1_ASTAT_K2_E5                                                                   0x628024UL //Access:R    DataWidth:0x18   // Multi Field Register.
+  #define PHY_PCIE_REG_PCIE_PHY1_ASTAT_LN4_ASTAT_O_K2_E5                                                     (0x3f<<0) // 
+  #define PHY_PCIE_REG_PCIE_PHY1_ASTAT_LN4_ASTAT_O_K2_E5_SHIFT                                               0
+  #define PHY_PCIE_REG_PCIE_PHY1_ASTAT_LN5_ASTAT_O_K2_E5                                                     (0x3f<<6) // 
+  #define PHY_PCIE_REG_PCIE_PHY1_ASTAT_LN5_ASTAT_O_K2_E5_SHIFT                                               6
+  #define PHY_PCIE_REG_PCIE_PHY1_ASTAT_LN6_ASTAT_O_K2_E5                                                     (0x3f<<12) // 
+  #define PHY_PCIE_REG_PCIE_PHY1_ASTAT_LN6_ASTAT_O_K2_E5_SHIFT                                               12
+  #define PHY_PCIE_REG_PCIE_PHY1_ASTAT_LN7_ASTAT_O_K2_E5                                                     (0x3f<<18) // 
+  #define PHY_PCIE_REG_PCIE_PHY1_ASTAT_LN7_ASTAT_O_K2_E5_SHIFT                                               18
+#define PHY_PCIE_REG_HW_INIT_CONFIG_K2_E5                                                                    0x628028UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define PHY_PCIE_REG_HW_INIT_CONFIG_FIRMWARE_EXIST_K2_E5                                                   (0x1<<0) // When set to 1, represents FW exists
+  #define PHY_PCIE_REG_HW_INIT_CONFIG_FIRMWARE_EXIST_K2_E5_SHIFT                                             0
+  #define PHY_PCIE_REG_HW_INIT_CONFIG_CMU_RESET_OVR_K2_E5                                                    (0x1<<1) // When set to 0, HWInit controls cmu_reset
+  #define PHY_PCIE_REG_HW_INIT_CONFIG_CMU_RESET_OVR_K2_E5_SHIFT                                              1
+  #define PHY_PCIE_REG_HW_INIT_CONFIG_LN_RESET_OVR_K2_E5                                                     (0x1<<2) // When set to 0, HWInit controls ln_reset
+  #define PHY_PCIE_REG_HW_INIT_CONFIG_LN_RESET_OVR_K2_E5_SHIFT                                               2
+#define PHY_PCIE_REG_DBG_STATUS_K2_E5                                                                        0x62802cUL //Access:R    DataWidth:0x5    // 
+#define PHY_PCIE_REG_DBG_OUT_DATA_K2_E5                                                                      0x629fc0UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PHY_PCIE_REG_DBG_OUT_DATA_SIZE                                                                       8
+#define PHY_PCIE_REG_DBG_OUT_VALID_K2_E5                                                                     0x629fe0UL //Access:R    DataWidth:0x4    // Dbgmux output valid
+#define PHY_PCIE_REG_DBG_OUT_FRAME_K2_E5                                                                     0x629fe4UL //Access:R    DataWidth:0x4    // Dbgmux output frame
+#define PHY_PCIE_REG_DBG_SELECT_K2_E5                                                                        0x629fe8UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PHY_PCIE_REG_DBG_DWORD_ENABLE_K2_E5                                                                  0x629fecUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PHY_PCIE_REG_DBG_SHIFT_K2_E5                                                                         0x629ff0UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PHY_PCIE_REG_DBG_FORCE_VALID_K2_E5                                                                   0x629ff4UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PHY_PCIE_REG_DBG_FORCE_FRAME_K2_E5                                                                   0x629ff8UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define MS_REG_COMMON_CONTROL_K2_E5                                                                          0x6a0000UL //Access:RW   DataWidth:0xd    // Multi Field Register.
+  #define MS_REG_COMMON_CONTROL_POR_N_I_K2_E5                                                                (0x1<<0) // Controls por_n_i reset signal into the SerDes. This should be 0 (Reset value) write 1 to this bit to allow the SerDes to begin normal Operation.
+  #define MS_REG_COMMON_CONTROL_POR_N_I_K2_E5_SHIFT                                                          0
+  #define MS_REG_COMMON_CONTROL_CMU_RESETN_I_K2_E5                                                           (0x1<<1) // Active low. Can be asserted on CMU0 in multiple CMU PHYs to save power if TX clock is being supplied by CMU1 and there are active lanes.
+  #define MS_REG_COMMON_CONTROL_CMU_RESETN_I_K2_E5_SHIFT                                                     1
+  #define MS_REG_COMMON_CONTROL_CMU_PD_I_K2_E5                                                               (0x1<<2) // Powerdown control for CMU. Can be asserted when CMU is in reset mode for increased power savings. Cannot be asserted on CMU0 in multiple CMU PHYs if there are any active lanes. Signal is over-riden by por_n_i so has no affect in power on reset state.
+  #define MS_REG_COMMON_CONTROL_CMU_PD_I_K2_E5_SHIFT                                                         2
+  #define MS_REG_COMMON_CONTROL_CMU_IDDQ_I_K2_E5                                                             (0x1<<3) // Turn off CMU master bias only. Cannot be asserted if there are any active lanes.
+  #define MS_REG_COMMON_CONTROL_CMU_IDDQ_I_K2_E5_SHIFT                                                       3
+  #define MS_REG_COMMON_CONTROL_CMU_CK_SOC_DIV_I_K2_E5                                                       (0x3<<4) // Divider control for SOC 1 clock for both CMUs. 00 = Divide by 1 01,10 = Divide by 2 11 = Divide by 4
+  #define MS_REG_COMMON_CONTROL_CMU_CK_SOC_DIV_I_K2_E5_SHIFT                                                 4
+  #define MS_REG_COMMON_CONTROL_CMU1_RESETN_I_K2_E5                                                          (0x1<<6) // Active low.
+  #define MS_REG_COMMON_CONTROL_CMU1_RESETN_I_K2_E5_SHIFT                                                    6
+  #define MS_REG_COMMON_CONTROL_CMU1_PD_I_K2_E5                                                              (0x1<<7) // Powerdown control for CMU1.
+  #define MS_REG_COMMON_CONTROL_CMU1_PD_I_K2_E5_SHIFT                                                        7
+  #define MS_REG_COMMON_CONTROL_CMU1_IDDQ_I_K2_E5                                                            (0x1<<8) // Turn off CMU master bias only. Cannot be asserted if there are any active lanes.
+  #define MS_REG_COMMON_CONTROL_CMU1_IDDQ_I_K2_E5_SHIFT                                                      8
+  #define MS_REG_COMMON_CONTROL_CMU1_CK_SOC_DIV_I_K2_E5                                                      (0x3<<9) // Divider control for SOC 1 clock for both CMUs. 00 = Divide by 1 01,10 = Divide by 2 11 = Divide by 4
+  #define MS_REG_COMMON_CONTROL_CMU1_CK_SOC_DIV_I_K2_E5_SHIFT                                                9
+  #define MS_REG_COMMON_CONTROL_CMU1_REFCLK_QFWD_L_I_K2_E5                                                   (0x1<<11) // Forward reference clock control from refclk_l_o.
+  #define MS_REG_COMMON_CONTROL_CMU1_REFCLK_QFWD_L_I_K2_E5_SHIFT                                             11
+  #define MS_REG_COMMON_CONTROL_CMU1_REFCLK_QFWD_R_I_K2_E5                                                   (0x1<<12) // Forward reference clock control from refclk_r_o.
+  #define MS_REG_COMMON_CONTROL_CMU1_REFCLK_QFWD_R_I_K2_E5_SHIFT                                             12
+#define MS_REG_LN1_CNTL_K2_E5                                                                                0x6a0004UL //Access:RW   DataWidth:0x15   // Multi Field Register.
+  #define MS_REG_LN1_CNTL_LN1_PD_K2_E5                                                                       (0x7<<0) // Lane Partial powerdown mode enable signal. ln1_pd[0] = Lane partial power down enable. ln1_pd[1] = Lane Slumber power down enable. ln1_pd[2] = Reserved.
+  #define MS_REG_LN1_CNTL_LN1_PD_K2_E5_SHIFT                                                                 0
+  #define MS_REG_LN1_CNTL_LN1_IDDQ_K2_E5                                                                     (0x1<<3) // Lane IDDQ mode enable.  Powers down entire PMA lane when asserted.
+  #define MS_REG_LN1_CNTL_LN1_IDDQ_K2_E5_SHIFT                                                               3
+  #define MS_REG_LN1_CNTL_LN1_RATE_K2_E5                                                                     (0x1f<<4) // Data rate control. See 4.2.4 changing data rates section of User Guide.
+  #define MS_REG_LN1_CNTL_LN1_RATE_K2_E5_SHIFT                                                               4
+  #define MS_REG_LN1_CNTL_LN1_CTRL_K2_E5                                                                     (0x1ff<<9) // Lane control 17 - rxsig_det_mask_i 16 - rxeii_exit_type_i 15 - rxei_infer_i 14 - bslip_req_i 13 - data_width_i - 0 = 10bit internal main data path, 1 = 20bit internal main data path. 12 - rxpolarity_i 11 - txcompliance_i 10 - txenable_i[1] send ln1_txdata_i[19:10] 9  - txenable_i[0] send ln1_txdata_i[9:0]
+  #define MS_REG_LN1_CNTL_LN1_CTRL_K2_E5_SHIFT                                                               9
+  #define MS_REG_LN1_CNTL_LN1_RSTN_I_K2_E5                                                                   (0x1<<18) // Active low. lane reset signal.
+  #define MS_REG_LN1_CNTL_LN1_RSTN_I_K2_E5_SHIFT                                                             18
+  #define MS_REG_LN1_CNTL_MS_OPCS_SDET_SELECT_K2_E5                                                          (0x3<<19) // Selects which signal is used to drive ms_opcs_sdet 0 - ln1_stat_o[2]  (RX Locked indicator) 1 - ln1_astat_o[5] (Raw signal detext indicator) 2 - ln1_stat_o[12] (lane OK indicator) 3 - Reserved
+  #define MS_REG_LN1_CNTL_MS_OPCS_SDET_SELECT_K2_E5_SHIFT                                                    19
+#define MS_REG_CMU_STATUS_K2_E5                                                                              0x6a0008UL //Access:R    DataWidth:0x2    // Multi Field Register.
+  #define MS_REG_CMU_STATUS_CMU_OK_O_K2_E5                                                                   (0x1<<0) // Indicates CMU PLL has locked to the reference clock and all output clocks are at the correct frequency.
+  #define MS_REG_CMU_STATUS_CMU_OK_O_K2_E5_SHIFT                                                             0
+  #define MS_REG_CMU_STATUS_CMU1_OK_O_K2_E5                                                                  (0x1<<1) // Indicates CMU1 PLL has locked to the reference clock and all output clocks are at the correct frequency.
+  #define MS_REG_CMU_STATUS_CMU1_OK_O_K2_E5_SHIFT                                                            1
+#define MS_REG_LN1_STATUS_K2_E5                                                                              0x6a000cUL //Access:R    DataWidth:0x14   // Multi Field Register.
+  #define MS_REG_LN1_STATUS_LN1_STAT_O_K2_E5                                                                 (0x3fff<<0) // 13 - not used 12 - ln1_ok_o 11 - ln1_runlen_err_o 10:4 - not used 3:2 - ln1_rx_locked_o - bit 3 =rxdata[19:10] locked, bit 2 = rxdata[9:0] locked. 1:0 - ln1_k28p5_det_o - bit 1 = k28.5 detected on [19:10], bit 0 = k28.5 detected on [9:0]
+  #define MS_REG_LN1_STATUS_LN1_STAT_O_K2_E5_SHIFT                                                           0
+  #define MS_REG_LN1_STATUS_LN1_ASTAT_O_K2_E5                                                                (0x3f<<14) // 19 - Raw signal detect - Bit Slip Ack 18 - ln1_bitslip_ack_o - Bit Slip Ack 17 - not used 16 - not used 15 - not used 14 - ln1_sig_level_valid_o
+  #define MS_REG_LN1_STATUS_LN1_ASTAT_O_K2_E5_SHIFT                                                          14
+#define MS_REG_CLOCK_SELECT_K2_E5                                                                            0x6a0010UL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define MS_REG_CLOCK_SELECT_CMU_REFCLK_INPUT_SEL_I_K2_E5                                                   (0x7<<0) // Reference clock input select
+  #define MS_REG_CLOCK_SELECT_CMU_REFCLK_INPUT_SEL_I_K2_E5_SHIFT                                             0
+  #define MS_REG_CLOCK_SELECT_CMU_REFCLK_SEL_I_K2_E5                                                         (0x1<<3) // Assert to provide CMU0 with the reference clock selected by CMU1.
+  #define MS_REG_CLOCK_SELECT_CMU_REFCLK_SEL_I_K2_E5_SHIFT                                                   3
+  #define MS_REG_CLOCK_SELECT_CMU1_REFCLK_INPUT_SEL_I_K2_E5                                                  (0x3<<4) // Reference clock input select
+  #define MS_REG_CLOCK_SELECT_CMU1_REFCLK_INPUT_SEL_I_K2_E5_SHIFT                                            4
+  #define MS_REG_CLOCK_SELECT_CMU1_REFCLK_SEL_I_K2_E5                                                        (0x1<<6) // Assert to provide CMU1 with the reference clock selected by CMU0.
+  #define MS_REG_CLOCK_SELECT_CMU1_REFCLK_SEL_I_K2_E5_SHIFT                                                  6
+  #define MS_REG_CLOCK_SELECT_CMU1_REFCLK_OE_L_I_K2_E5                                                       (0x1<<7) // Output enables for bidirectional CML refclk buffers.
+  #define MS_REG_CLOCK_SELECT_CMU1_REFCLK_OE_L_I_K2_E5_SHIFT                                                 7
+  #define MS_REG_CLOCK_SELECT_CMU1_REFCLK_OE_R_I_K2_E5                                                       (0x1<<8) // Output enables for bidirectional CML refclk buffers.
+  #define MS_REG_CLOCK_SELECT_CMU1_REFCLK_OE_R_I_K2_E5_SHIFT                                                 8
+#define MS_REG_ECO_RESERVED_K2_E5                                                                            0x6a0014UL //Access:RW   DataWidth:0x20   // This is unused register for future ECOs.
+#define MS_REG_INT_STS_K2_E5                                                                                 0x6a0180UL //Access:R    DataWidth:0x1    // Multi Field Register.
+  #define MS_REG_INT_STS_ADDRESS_ERROR_K2_E5                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define MS_REG_INT_STS_ADDRESS_ERROR_K2_E5_SHIFT                                                           0
+#define MS_REG_INT_MASK_K2_E5                                                                                0x6a0184UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define MS_REG_INT_MASK_ADDRESS_ERROR_K2_E5                                                                (0x1<<0) // This bit masks, when set, the Interrupt bit: MS_REG_INT_STS.ADDRESS_ERROR .
+  #define MS_REG_INT_MASK_ADDRESS_ERROR_K2_E5_SHIFT                                                          0
+#define MS_REG_INT_STS_WR_K2_E5                                                                              0x6a0188UL //Access:WR   DataWidth:0x1    // Multi Field Register.
+  #define MS_REG_INT_STS_WR_ADDRESS_ERROR_K2_E5                                                              (0x1<<0) // Signals an unknown address to the rf module.
+  #define MS_REG_INT_STS_WR_ADDRESS_ERROR_K2_E5_SHIFT                                                        0
+#define MS_REG_INT_STS_CLR_K2_E5                                                                             0x6a018cUL //Access:RC   DataWidth:0x1    // Multi Field Register.
+  #define MS_REG_INT_STS_CLR_ADDRESS_ERROR_K2_E5                                                             (0x1<<0) // Signals an unknown address to the rf module.
+  #define MS_REG_INT_STS_CLR_ADDRESS_ERROR_K2_E5_SHIFT                                                       0
+#define MS_REG_DBG_OUT_DATA_K2_E5                                                                            0x6a0200UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define MS_REG_DBG_OUT_DATA_SIZE                                                                             8
+#define MS_REG_DBG_OUT_VALID_K2_E5                                                                           0x6a0220UL //Access:R    DataWidth:0x4    // Dbgmux output valid
+#define MS_REG_DBG_OUT_FRAME_K2_E5                                                                           0x6a0224UL //Access:R    DataWidth:0x4    // Dbgmux output frame
+#define MS_REG_DBG_SELECT_K2_E5                                                                              0x6a0228UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define MS_REG_DBG_DWORD_ENABLE_K2_E5                                                                        0x6a022cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define MS_REG_DBG_SHIFT_K2_E5                                                                               0x6a0230UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define MS_REG_DBG_FORCE_VALID_K2_E5                                                                         0x6a0234UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define MS_REG_DBG_FORCE_FRAME_K2_E5                                                                         0x6a0238UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define MS_REG_DBGSYN_ALMOST_FULL_THR_K2_E5                                                                  0x6a023cUL //Access:RW   DataWidth:0x4    // Debug only: If more than this Number of entries are occupied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed.
+#define MS_REG_DBGSYN_STATUS_K2_E5                                                                           0x6a0240UL //Access:R    DataWidth:0x5    // Debug only: Fill level of dbgmux fifo.
+#define MS_REG_DBG_SAMPLING_INTERVAL_K2_E5                                                                   0x6a0244UL //Access:RW   DataWidth:0x14   // Debug only: Sampling interval * pclk, 2ns to 2ms.
+#define MS_REG_DBG_REPEAT_THRESHOLD_COUNT_K2_E5                                                              0x6a0248UL //Access:RW   DataWidth:0x4    // Debug only: If 0 or 1, trigger on first occurrence. If greater than 1, wait until counter value match to trigger.
+#define MS_REG_DBG_POST_TRIGGER_LATENCY_COUNT_K2_E5                                                          0x6a024cUL //Access:RW   DataWidth:0x18   // Debug only: If greater than 0, delay trigger count value * pclk, 0 to 32ms
+#define MS_REG_DBG_FW_TRIGGER_ENABLE_K2_E5                                                                   0x6a0250UL //Access:RW   DataWidth:0x1    // Debug only: FW trigger is set.
+#define MS_REG_MS_CMU_K2_E5                                                                                  0x6a4000UL //Access:RW   DataWidth:0x8    // CMU registers   = 0-0x1ff. Reserved        = 0x200-0x3ff. LANE1 registers = 0x400-0x5ff. Reserved        = 0x600-0x7ff. Reserved        = 0x800-0x9ff. Common Lane block registers = 0xa00-0xbff. CMU1 registers  = 0xc00-0xdff.
+#define MS_REG_MS_CMU_SIZE                                                                                   4096
+#define AVS_WRAP_REG_AVS_IND_K2                                                                              0x6b2000UL //Access:RW   DataWidth:0x20   // This indirect register is used to access the AVS blocks. For more detailes see eSilicon_AVS_RefManual.pdf specification.
+#define AVS_WRAP_REG_AVS_IND_SIZE                                                                            2048
+#define AVS_WRAP_REG_AVS_CONTROL_K2                                                                          0x6b4000UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define AVS_WRAP_REG_AVS_CONTROL_HRESET_K2                                                                 (0x1<<0) // Asynchronous reset, active high When asserted, it resets all the controller logic, except configuration register. It is internally synchronized with cmn_refclk.
+  #define AVS_WRAP_REG_AVS_CONTROL_HRESET_K2_SHIFT                                                           0
+  #define AVS_WRAP_REG_AVS_CONTROL_MODESEL_K2                                                                (0x3<<1) // Mode selection driven by core signals. This bus, when HW control gate is enabled, directly control the configuration registers that are connected to regulators 00: Using constants 01: Using flow1 10: Using flow2 11: reserved There is one port per AVS controller
+  #define AVS_WRAP_REG_AVS_CONTROL_MODESEL_K2_SHIFT                                                          1
+  #define AVS_WRAP_REG_AVS_CONTROL_SETSEL_K2                                                                 (0x7<<3) // Register subst selection driven by core signals. This bus, when HW control gate is enabled, directly controls the configuration registers that are connected to regulators 0: Using registers belonging to set0 1: Using registers belonging to set1 SETS_W-1: Using set of registers belonging to set SETS_W-1
+  #define AVS_WRAP_REG_AVS_CONTROL_SETSEL_K2_SHIFT                                                           3
+  #define AVS_WRAP_REG_AVS_CONTROL_CORE_CMD_K2                                                               (0x3<<6) // This signal has sense when HW control gate is enabled or its corresponding bit in the AVSC_FLOW_CTRL is enabled. Bit [0] : corresponds to FLOW 1 Bit [1] : corresponds to FLOW 2 Any toggle from zero-to-one will generate an internal pulse which, if not masked, may start the corresponding flow. There is one port per AVS controller
+  #define AVS_WRAP_REG_AVS_CONTROL_CORE_CMD_K2_SHIFT                                                         6
+#define AVS_WRAP_REG_AVS_INDICATION_K2                                                                       0x6b4004UL //Access:R    DataWidth:0xa    // Multi Field Register.
+  #define AVS_WRAP_REG_AVS_INDICATION_CORE_PWROK_K2                                                          (0x1<<0) // This signal is set when the voltage is stable at its target value, typically after a change of selection (either mode or set) When either modesel and setsel changes, the output goes down. Once power reaches the target voltage, it is asserted.
+  #define AVS_WRAP_REG_AVS_INDICATION_CORE_PWROK_K2_SHIFT                                                    0
+  #define AVS_WRAP_REG_AVS_INDICATION_CORE_MODEACK_K2                                                        (0x3<<1) // It replicates the mode-sel value when voltage is stable.
+  #define AVS_WRAP_REG_AVS_INDICATION_CORE_MODEACK_K2_SHIFT                                                  1
+  #define AVS_WRAP_REG_AVS_INDICATION_CORE_SETACK_K2                                                         (0x7<<3) // It replicates the set-sel value when voltage is stable.
+  #define AVS_WRAP_REG_AVS_INDICATION_CORE_SETACK_K2_SHIFT                                                   3
+  #define AVS_WRAP_REG_AVS_INDICATION_BIN_SEL_K2                                                             (0xf<<6) // Out put bin indication from AVS IP.
+  #define AVS_WRAP_REG_AVS_INDICATION_BIN_SEL_K2_SHIFT                                                       6
+#define AVS_WRAP_REG_INT_STS_K2                                                                              0x6b4008UL //Access:R    DataWidth:0x3    // Multi Field Register.
+  #define AVS_WRAP_REG_INT_STS_ADDRESS_ERROR_K2                                                              (0x1<<0) // Signals an unknown address to the rf module.
+  #define AVS_WRAP_REG_INT_STS_ADDRESS_ERROR_K2_SHIFT                                                        0
+  #define AVS_WRAP_REG_INT_STS_AVS_IRQ_K2                                                                    (0x1<<2) // This interrupt is asserted following the assertion of the AVS block interrupt
+  #define AVS_WRAP_REG_INT_STS_AVS_IRQ_K2_SHIFT                                                              2
+#define AVS_WRAP_REG_INT_MASK_K2                                                                             0x6b400cUL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define AVS_WRAP_REG_INT_MASK_ADDRESS_ERROR_K2                                                             (0x1<<0) // This bit masks, when set, the Interrupt bit: AVS_WRAP_REG_INT_STS.ADDRESS_ERROR .
+  #define AVS_WRAP_REG_INT_MASK_ADDRESS_ERROR_K2_SHIFT                                                       0
+  #define AVS_WRAP_REG_INT_MASK_AVS_IRQ_K2                                                                   (0x1<<2) // This bit masks, when set, the Interrupt bit: AVS_WRAP_REG_INT_STS.AVS_IRQ .
+  #define AVS_WRAP_REG_INT_MASK_AVS_IRQ_K2_SHIFT                                                             2
+#define AVS_WRAP_REG_INT_STS_WR_K2                                                                           0x6b4010UL //Access:WR   DataWidth:0x3    // Multi Field Register.
+  #define AVS_WRAP_REG_INT_STS_WR_ADDRESS_ERROR_K2                                                           (0x1<<0) // Signals an unknown address to the rf module.
+  #define AVS_WRAP_REG_INT_STS_WR_ADDRESS_ERROR_K2_SHIFT                                                     0
+  #define AVS_WRAP_REG_INT_STS_WR_AVS_IRQ_K2                                                                 (0x1<<2) // This interrupt is asserted following the assertion of the AVS block interrupt
+  #define AVS_WRAP_REG_INT_STS_WR_AVS_IRQ_K2_SHIFT                                                           2
+#define AVS_WRAP_REG_INT_STS_CLR_K2                                                                          0x6b4014UL //Access:RC   DataWidth:0x3    // Multi Field Register.
+  #define AVS_WRAP_REG_INT_STS_CLR_ADDRESS_ERROR_K2                                                          (0x1<<0) // Signals an unknown address to the rf module.
+  #define AVS_WRAP_REG_INT_STS_CLR_ADDRESS_ERROR_K2_SHIFT                                                    0
+  #define AVS_WRAP_REG_INT_STS_CLR_AVS_IRQ_K2                                                                (0x1<<2) // This interrupt is asserted following the assertion of the AVS block interrupt
+  #define AVS_WRAP_REG_INT_STS_CLR_AVS_IRQ_K2_SHIFT                                                          2
+#define AVS_WRAP_REG_PRTY_MASK_K2                                                                            0x6b401cUL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define AVS_WRAP_REG_PRTY_MASK_FUSE_STAT_CORRUPTED_K2                                                      (0x1<<0) // This bit masks, when set, the Parity bit: AVS_WRAP_REG_PRTY_STS.FUSE_STAT_CORRUPTED .
+  #define AVS_WRAP_REG_PRTY_MASK_FUSE_STAT_CORRUPTED_K2_SHIFT                                                0
+  #define AVS_WRAP_REG_PRTY_MASK_MEANSMEM_PERR_K2                                                            (0x1<<1) // This bit masks, when set, the Parity bit: AVS_WRAP_REG_PRTY_STS.MEANSMEM_PERR .
+  #define AVS_WRAP_REG_PRTY_MASK_MEANSMEM_PERR_K2_SHIFT                                                      1
+  #define AVS_WRAP_REG_PRTY_MASK_BINMEM_PERR_K2                                                              (0x1<<2) // This bit masks, when set, the Parity bit: AVS_WRAP_REG_PRTY_STS.BINMEM_PERR .
+  #define AVS_WRAP_REG_PRTY_MASK_BINMEM_PERR_K2_SHIFT                                                        2
+#define AVS_WRAP_REG_ECO_RESERVED_K2                                                                         0x6b4028UL //Access:RW   DataWidth:0x20   // Reserved bits for ECO.
+#define AVS_WRAP_REG_EFUSE_DATA_WORD_16_K2                                                                   0x6b402cUL //Access:R    DataWidth:0x20   // Read only line 16 of eFuse data.
+#define AVS_WRAP_REG_EFUSE_DATA_WORD_17_K2                                                                   0x6b4030UL //Access:R    DataWidth:0x20   // Read only line 17 of eFuse data.
+#define AVS_WRAP_REG_EFUSE_DATA_WORD_18_K2                                                                   0x6b4034UL //Access:R    DataWidth:0x20   // Read only line 18 of eFuse data.
+#define AVS_WRAP_REG_EFUSE_DATA_WORD_19_K2                                                                   0x6b4038UL //Access:R    DataWidth:0x20   // Read only line 19 of eFuse data.
+#define AVS_WRAP_REG_EFUSE_DATA_WORD_20_K2                                                                   0x6b403cUL //Access:R    DataWidth:0x20   // Read only line 20 of eFuse data.
+#define AVS_WRAP_REG_EFUSE_DATA_WORD_21_K2                                                                   0x6b4040UL //Access:R    DataWidth:0x20   // Read only line 21 of eFuse data.
+#define AVS_WRAP_REG_EFUSE_DATA_WORD_22_K2                                                                   0x6b4044UL //Access:R    DataWidth:0x20   // Read only line 22 of eFuse data.
+#define AVS_WRAP_REG_EFUSE_DATA_WORD_23_K2                                                                   0x6b4048UL //Access:R    DataWidth:0x20   // Read only line 23 of eFuse data.
+#define LED_REG_CONTROL_K2_E5                                                                                0x6b8000UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define LED_REG_CONTROL_OVERRIDE_TRAFFIC_K2_E5                                                             (0x1<<0) // If set overrides hardware control of the Traffic LED. The Traffic LED will then be controlled via bit LED_CONTROL_TRAFFIC And LED_CONTROL_BLINK_TRAFFIC
+  #define LED_REG_CONTROL_OVERRIDE_TRAFFIC_K2_E5_SHIFT                                                       0
+  #define LED_REG_CONTROL_TRAFFIC_K2_E5                                                                      (0x1<<4) // If set along with the LED_CONTROL_OVERRIDE_TRAFFIC bit turns on the Traffic LED. If the LED_CONTROL_BLINK_TRAFFIC bit bit is also set; the LED will blink with blink rate specified in LED_CONTROL_BLINK_RATE and LED_CONTROL_BLINK_RATE_ENA fields.
+  #define LED_REG_CONTROL_TRAFFIC_K2_E5_SHIFT                                                                4
+  #define LED_REG_CONTROL_BLINK_TRAFFIC_K2_E5                                                                (0x1<<8) // If set along with the LED_CONTROL_OVERRIDE_TRAFFIC bit and LED_CONTROL_TRAFFIC LED bit; the Traffic LED will blink with the blink rate specified in LED_CONTROL_BLINK_RATE and LED_CONTROL_BLINK_RATE_ENA fields.
+  #define LED_REG_CONTROL_BLINK_TRAFFIC_K2_E5_SHIFT                                                          8
+  #define LED_REG_CONTROL_BLINK_RATE_ENA_K2_E5                                                               (0x1<<12) // This bit is set to enable the use of the LED_CONTROL_BLINK_RATE field defined below. If this bit is cleared: Number of main clock cycles the led is ON will be 2^32. Number of main clock cycles the led is ON will be 2^32.
+  #define LED_REG_CONTROL_BLINK_RATE_ENA_K2_E5_SHIFT                                                         12
+  #define LED_REG_CONTROL_ALTERNATING_K2_E5                                                                  (0x1<<13) // This bit is set to enable the alternating between activity and speed LEDs of the same port The alternating feature is used only with MAC1 and MAC2 modes.
+  #define LED_REG_CONTROL_ALTERNATING_K2_E5_SHIFT                                                            13
+  #define LED_REG_CONTROL_BLINK_RATE_K2_E5                                                                   (0x1ffff<<15) // Specifies the period of each blink cycle (on + off) for Traffic LED. number of main clock cycles the led is ON  = (contorl_blink_rate*2^15) number of main clock cycles the led is OFF = (contorl_blink_rate*2^15)
+  #define LED_REG_CONTROL_BLINK_RATE_K2_E5_SHIFT                                                             15
+#define LED_REG_MODE_K2_E5                                                                                   0x6b8004UL //Access:RW   DataWidth:0x4    // Led mode: 0     -> MAC; 1-2   -> PHY1; 3     -> PHY3; 4     -> MAC2; 5-6   -> PHY4; 7     -> PHY6; 8     -> MAC3; 9     -> PHY7; 10    -> PHY8; 11    -> PHY9; 12    -> MAC4; 13    -> PHY10; 14    -> PHY11; 15    -> PHY1;
+#define LED_REG_PORT_SPD0_EN_K2_E5                                                                           0x6b8008UL //Access:RW   DataWidth:0x5    // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G A '1' to each bit location will enable the corresponding speed to activate the LED.
+#define LED_REG_PORT_SPD1_EN_K2_E5                                                                           0x6b800cUL //Access:RW   DataWidth:0x5    // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G A '1' to each bit location will enable the corresponding speed to activate the LED.
+#define LED_REG_PORT_SPD2_EN_K2_E5                                                                           0x6b8010UL //Access:RW   DataWidth:0x5    // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G A '1' to each bit location will enable the corresponding speed to activate the LED.
+#define LED_REG_MAC_LED_SPEED_K2_E5                                                                          0x6b8014UL //Access:RW   DataWidth:0x5    // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G This register allows the MAC (Driver/FW) to set the link speed of the particular port. This combined with the mask for each LED will activate the corresponding LED. For ex. if the link speed is 10G, then SW will set bit[1] of this register. If 10G is enabled on LED SPD1, then SPD1 will light up, SPD0 and SPD2 will not.
+#define LED_REG_MAC_LED_SWAP_K2_E5                                                                           0x6b8018UL //Access:RW   DataWidth:0xe    // Multi Field Register.
+  #define LED_REG_MAC_LED_SWAP_P0_K2_E5                                                                      (0x3<<0) // Device Drivers view of a physical port is through the PCIE physical function that was enumerated. In a typical setup, Physical function 0 is connected to Network Port 0, PF1 to NW1 and so on. However, there are cases when the PF and NW conenctions are swapped. This register sets up which PF is connected to which Network Port. For a multiport/multifunction configuration, appropriate settings should be chosen. For ex. in a two port device, only two sets of the the bits below are valid. a Four port device has all four sets of bits valid. These bits makes the connection of Network Port 0 to the corresponding Physical function. 0  -> NW0 connects to PF0 1  -> NW0 connects to PF1 2  -> NW0 connects to PF2 3  -> NW0 connects to PF3
+  #define LED_REG_MAC_LED_SWAP_P0_K2_E5_SHIFT                                                                0
+  #define LED_REG_MAC_LED_SWAP_P1_K2_E5                                                                      (0x3<<4) // These bits makes the connection of Network Port 1 to the corresponding Physical function. 0  -> NW1 connects to PF0 1  -> NW1 connects to PF1 2  -> NW1 connects to PF2 3  -> NW1 connects to PF3
+  #define LED_REG_MAC_LED_SWAP_P1_K2_E5_SHIFT                                                                4
+  #define LED_REG_MAC_LED_SWAP_P2_K2_E5                                                                      (0x3<<8) // These bits makes the connection of Network Port 2 to the corresponding Physical function. 0  -> NW2 connects to PF0 1  -> NW2 connects to PF1 2  -> NW2 connects to PF2 3  -> NW2 connects to PF3
+  #define LED_REG_MAC_LED_SWAP_P2_K2_E5_SHIFT                                                                8
+  #define LED_REG_MAC_LED_SWAP_P3_K2_E5                                                                      (0x3<<12) // These bits makes the connection of Network Port 2 to the corresponding Physical function. 0  -> NW3 connects to PF0 1  -> NW3 connects to PF1 2  -> NW3 connects to PF2 3  -> NW3 connects to PF3
+  #define LED_REG_MAC_LED_SWAP_P3_K2_E5_SHIFT                                                                12
+#define LED_REG_RAW_SPEED_LN0_K2_E5                                                                          0x6b801cUL //Access:R    DataWidth:0x5    // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G RAW version of the LED from the SERDES..
+#define LED_REG_RAW_SPEED_LN1_K2_E5                                                                          0x6b8020UL //Access:R    DataWidth:0x5    // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G RAW version of the LED from the SERDES..
+#define LED_REG_RAW_SPEED_LN2_K2_E5                                                                          0x6b8024UL //Access:R    DataWidth:0x5    // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G RAW version of the LED from the SERDES..
+#define LED_REG_RAW_SPEED_LN3_K2_E5                                                                          0x6b8028UL //Access:R    DataWidth:0x5    // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G RAW version of the LED from the SERDES..
+#define LED_REG_ECO_RESERVED_K2_E5                                                                           0x6b802cUL //Access:RW   DataWidth:0x20   // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
+#define LED_REG_INT_STS_0_K2_E5                                                                              0x6b8180UL //Access:R    DataWidth:0x1    // Multi Field Register.
+  #define LED_REG_INT_STS_0_ADDRESS_ERROR_K2_E5                                                              (0x1<<0) // Signals an unknown address to the rf module.
+  #define LED_REG_INT_STS_0_ADDRESS_ERROR_K2_E5_SHIFT                                                        0
+#define LED_REG_INT_MASK_0_K2_E5                                                                             0x6b8184UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define LED_REG_INT_MASK_0_ADDRESS_ERROR_K2_E5                                                             (0x1<<0) // This bit masks, when set, the Interrupt bit: LED_REG_INT_STS_0.ADDRESS_ERROR .
+  #define LED_REG_INT_MASK_0_ADDRESS_ERROR_K2_E5_SHIFT                                                       0
+#define LED_REG_INT_STS_WR_0_K2_E5                                                                           0x6b8188UL //Access:WR   DataWidth:0x1    // Multi Field Register.
+  #define LED_REG_INT_STS_WR_0_ADDRESS_ERROR_K2_E5                                                           (0x1<<0) // Signals an unknown address to the rf module.
+  #define LED_REG_INT_STS_WR_0_ADDRESS_ERROR_K2_E5_SHIFT                                                     0
+#define LED_REG_INT_STS_CLR_0_K2_E5                                                                          0x6b818cUL //Access:RC   DataWidth:0x1    // Multi Field Register.
+  #define LED_REG_INT_STS_CLR_0_ADDRESS_ERROR_K2_E5                                                          (0x1<<0) // Signals an unknown address to the rf module.
+  #define LED_REG_INT_STS_CLR_0_ADDRESS_ERROR_K2_E5_SHIFT                                                    0
+#define NWS_REG_COMMON_CONTROL_K2_E5                                                                         0x700000UL //Access:RW   DataWidth:0x1e   // Multi Field Register.
+  #define NWS_REG_COMMON_CONTROL_REFCLK_INPUT_SEL_I_K2_E5                                                    (0x3<<0) // 0x0 - Select reference clock from Bump 0x1 - Select inter-macro refrence clock from the left side 0x2 - Same as 0x0 0x3 - Select inter-macro refrence clock from the right side
+  #define NWS_REG_COMMON_CONTROL_REFCLK_INPUT_SEL_I_K2_E5_SHIFT                                              0
+  #define NWS_REG_COMMON_CONTROL_REFCLK_LEFT_SEL_I_K2_E5                                                     (0x3<<2) // 0x0 - Saves Power 0x1 - Select reference clock from Bump 0x2 - Select inter-macro refrence clock from the right side 0x3 - Same as 0x2
+  #define NWS_REG_COMMON_CONTROL_REFCLK_LEFT_SEL_I_K2_E5_SHIFT                                               2
+  #define NWS_REG_COMMON_CONTROL_REFCLK_RIGHT_SEL_I_K2_E5                                                    (0x3<<4) // 0x0 - Saves Power 0x1 - Select reference clock from Bump 0x2 - Select inter-macro refrence clock from the left side 0x3 - Same as 0x2
+  #define NWS_REG_COMMON_CONTROL_REFCLK_RIGHT_SEL_I_K2_E5_SHIFT                                              4
+  #define NWS_REG_COMMON_CONTROL_STAT_LOS_SELECT_K2_E5                                                       (0x3<<6) // Selects which stat_los signal is used for nws_nwm_sd_energy_detect. 0 - use ~lnX_stat_los_o 1 - use ~lnX_stat_los_deglitch_o (Default) 2 - use lnX_stat_rxvalid_o
+  #define NWS_REG_COMMON_CONTROL_STAT_LOS_SELECT_K2_E5_SHIFT                                                 6
+  #define NWS_REG_COMMON_CONTROL_CPU_RESET_K2_E5                                                             (0x1<<10) // Controls cpu_reset_i reset signal into the SerDes.
+  #define NWS_REG_COMMON_CONTROL_CPU_RESET_K2_E5_SHIFT                                                       10
+  #define NWS_REG_COMMON_CONTROL_POR_N_K2_E5                                                                 (0x1<<11) // Controls por_n_i reset signal into the SerDes. This should be 0 (Reset value) while the SerDes program and data rams are being written, and the serdes is being configured.  This holds the SerDes in Reset. Once the memory is configured, write 1 to this bit to allow the SerDes to begin normal Operation.
+  #define NWS_REG_COMMON_CONTROL_POR_N_K2_E5_SHIFT                                                           11
+  #define NWS_REG_COMMON_CONTROL_CM0_RST_N_K2_E5                                                             (0x1<<12) // Controls cm0_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the cmu0 in Reset. write 1 to this bit to allow the SerDes to begin normal Operation.
+  #define NWS_REG_COMMON_CONTROL_CM0_RST_N_K2_E5_SHIFT                                                       12
+  #define NWS_REG_COMMON_CONTROL_CM1_RST_N_K2_E5                                                             (0x1<<13) // Controls cm1_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the cmu0 in Reset. write 1 to this bit to allow the SerDes to begin normal Operation.
+  #define NWS_REG_COMMON_CONTROL_CM1_RST_N_K2_E5_SHIFT                                                       13
+  #define NWS_REG_COMMON_CONTROL_LN0_RST_N_K2_E5                                                             (0x1<<14) // Controls ln0_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the ln0 in Reset. write 1 to begin normal Operation on ln0.
+  #define NWS_REG_COMMON_CONTROL_LN0_RST_N_K2_E5_SHIFT                                                       14
+  #define NWS_REG_COMMON_CONTROL_LN1_RST_N_K2_E5                                                             (0x1<<15) // Controls ln1_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the ln1 in Reset. write 1 to begin normal Operation on ln1.
+  #define NWS_REG_COMMON_CONTROL_LN1_RST_N_K2_E5_SHIFT                                                       15
+  #define NWS_REG_COMMON_CONTROL_LN2_RST_N_K2_E5                                                             (0x1<<16) // Controls ln0_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the ln2 in Reset. write 1 to begin normal Operation on ln2.
+  #define NWS_REG_COMMON_CONTROL_LN2_RST_N_K2_E5_SHIFT                                                       16
+  #define NWS_REG_COMMON_CONTROL_LN3_RST_N_K2_E5                                                             (0x1<<17) // Controls ln3_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the ln3 in Reset. write 1 to begin normal Operation on ln3.
+  #define NWS_REG_COMMON_CONTROL_LN3_RST_N_K2_E5_SHIFT                                                       17
+  #define NWS_REG_COMMON_CONTROL_CM0_PD_K2_E5                                                                (0x3<<18) // CMU Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode)
+  #define NWS_REG_COMMON_CONTROL_CM0_PD_K2_E5_SHIFT                                                          18
+  #define NWS_REG_COMMON_CONTROL_CM1_PD_K2_E5                                                                (0x3<<20) // CMU Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode)
+  #define NWS_REG_COMMON_CONTROL_CM1_PD_K2_E5_SHIFT                                                          20
+  #define NWS_REG_COMMON_CONTROL_LN0_PD_K2_E5                                                                (0x3<<22) // Lane Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode)
+  #define NWS_REG_COMMON_CONTROL_LN0_PD_K2_E5_SHIFT                                                          22
+  #define NWS_REG_COMMON_CONTROL_LN1_PD_K2_E5                                                                (0x3<<24) // Lane Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode)
+  #define NWS_REG_COMMON_CONTROL_LN1_PD_K2_E5_SHIFT                                                          24
+  #define NWS_REG_COMMON_CONTROL_LN2_PD_K2_E5                                                                (0x3<<26) // Lane Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode)
+  #define NWS_REG_COMMON_CONTROL_LN2_PD_K2_E5_SHIFT                                                          26
+  #define NWS_REG_COMMON_CONTROL_LN3_PD_K2_E5                                                                (0x3<<28) // Lane Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode)
+  #define NWS_REG_COMMON_CONTROL_LN3_PD_K2_E5_SHIFT                                                          28
+#define NWS_REG_PHY_CTRL_K2_E5                                                                               0x700004UL //Access:RW   DataWidth:0x11   // Multi Field Register.
+  #define NWS_REG_PHY_CTRL_REFCLK_K2_E5                                                                      (0x1f<<0) // Sets phy_ctrl_refclk_i used for CMU0 0x09 - refclk is 257.8125Mhz
+  #define NWS_REG_PHY_CTRL_REFCLK_K2_E5_SHIFT                                                                0
+  #define NWS_REG_PHY_CTRL_RATE1_K2_E5                                                                       (0x3f<<5) // Sets phy_ctrl_rate1_i used for CMU0 0x03 - Data rate is 25.78125 Gbps 0x23 - Data rate is 10.3125 Gbps 0x2F - Data rate is 1.25 Gbps
+  #define NWS_REG_PHY_CTRL_RATE1_K2_E5_SHIFT                                                                 5
+  #define NWS_REG_PHY_CTRL_RATE2_K2_E5                                                                       (0x3f<<11) // Sets phy_ctrl_rate1_i used for CMU1 0x03 - Data rate is 25.78125 Gbps 0x23 - Data rate is 10.3125 Gbps 0x2F - Data rate is 1.25 Gbps
+  #define NWS_REG_PHY_CTRL_RATE2_K2_E5_SHIFT                                                                 11
+#define NWS_REG_ANEG_CFG_K2_E5                                                                               0x700008UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define NWS_REG_ANEG_CFG_LN0_ANEG_CFG_I_K2_E5                                                              (0x3<<0) // 0x0 - Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x1 - auto-negotiation controlled, but auto-negotiation is not run on the lane (call it an AN-slave lane) 0x2 - auto-negotiation controlled, and auto-negotiation is run on the lane (call it an AN-master lane) 0x3 - reserved
+  #define NWS_REG_ANEG_CFG_LN0_ANEG_CFG_I_K2_E5_SHIFT                                                        0
+  #define NWS_REG_ANEG_CFG_LN1_ANEG_CFG_I_K2_E5                                                              (0x3<<2) // 0x0 - Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x1 - auto-negotiation controlled, but auto-negotiation is not run on the lane (call it an AN-slave lane) 0x2 - auto-negotiation controlled, and auto-negotiation is run on the lane (call it an AN-master lane) 0x3 - reserved
+  #define NWS_REG_ANEG_CFG_LN1_ANEG_CFG_I_K2_E5_SHIFT                                                        2
+  #define NWS_REG_ANEG_CFG_LN2_ANEG_CFG_I_K2_E5                                                              (0x3<<4) // 0x0 - Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x1 - auto-negotiation controlled, but auto-negotiation is not run on the lane (call it an AN-slave lane) 0x2 - auto-negotiation controlled, and auto-negotiation is run on the lane (call it an AN-master lane) 0x3 - reserved
+  #define NWS_REG_ANEG_CFG_LN2_ANEG_CFG_I_K2_E5_SHIFT                                                        4
+  #define NWS_REG_ANEG_CFG_LN3_ANEG_CFG_I_K2_E5                                                              (0x3<<6) // 0x0 - Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x1 - auto-negotiation controlled, but auto-negotiation is not run on the lane (call it an AN-slave lane) 0x2 - auto-negotiation controlled, and auto-negotiation is run on the lane (call it an AN-master lane) 0x3 - reserved
+  #define NWS_REG_ANEG_CFG_LN3_ANEG_CFG_I_K2_E5_SHIFT                                                        6
+#define NWS_REG_COMMON_STATUS_K2_E5                                                                          0x70000cUL //Access:R    DataWidth:0x9    // Multi Field Register.
+  #define NWS_REG_COMMON_STATUS_ERR_O_K2_E5                                                                  (0x1<<0) // 0x0 - No error 0x1 - Phy has internal error
+  #define NWS_REG_COMMON_STATUS_ERR_O_K2_E5_SHIFT                                                            0
+  #define NWS_REG_COMMON_STATUS_CM0_OK_O_K2_E5                                                               (0x1<<1) // 0x1 - Indicates CMU0 PLL has locked to the reference clock and all output clocks are at the correct frequency
+  #define NWS_REG_COMMON_STATUS_CM0_OK_O_K2_E5_SHIFT                                                         1
+  #define NWS_REG_COMMON_STATUS_CM1_OK_O_K2_E5                                                               (0x1<<2) // 0x1 - Indicates CMU1 PLL has locked to the reference clock and all output clocks are at the correct frequency
+  #define NWS_REG_COMMON_STATUS_CM1_OK_O_K2_E5_SHIFT                                                         2
+  #define NWS_REG_COMMON_STATUS_CM0_RST_PD_READY_O_K2_E5                                                     (0x1<<3) // 0x0 - PHY is not ready to respond to cm0_rst_n_i and cm0_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to cm0_rst_n_i and cm0_pd_i[1:0].
+  #define NWS_REG_COMMON_STATUS_CM0_RST_PD_READY_O_K2_E5_SHIFT                                               3
+  #define NWS_REG_COMMON_STATUS_CM1_RST_PD_READY_O_K2_E5                                                     (0x1<<4) // 0x0 - PHY is not ready to respond to cm1_rst_n_i and cm1_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to cm1_rst_n_i and cm1_pd_i[1:0].
+  #define NWS_REG_COMMON_STATUS_CM1_RST_PD_READY_O_K2_E5_SHIFT                                               4
+  #define NWS_REG_COMMON_STATUS_LN0_RST_PD_READY_O_K2_E5                                                     (0x1<<5) // 0x0 - PHY is not ready to respond to ln0_rst_n_i and ln0_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to ln0_rst_n_i and ln0_pd_i[1:0].
+  #define NWS_REG_COMMON_STATUS_LN0_RST_PD_READY_O_K2_E5_SHIFT                                               5
+  #define NWS_REG_COMMON_STATUS_LN1_RST_PD_READY_O_K2_E5                                                     (0x1<<6) // 0x0 - PHY is not ready to respond to ln1_rst_n_i and ln1_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to ln1_rst_n_i and ln1_pd_i[1:0].
+  #define NWS_REG_COMMON_STATUS_LN1_RST_PD_READY_O_K2_E5_SHIFT                                               6
+  #define NWS_REG_COMMON_STATUS_LN2_RST_PD_READY_O_K2_E5                                                     (0x1<<7) // 0x0 - PHY is not ready to respond to ln2_rst_n_i and ln2_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to ln2_rst_n_i and ln2_pd_i[1:0].
+  #define NWS_REG_COMMON_STATUS_LN2_RST_PD_READY_O_K2_E5_SHIFT                                               7
+  #define NWS_REG_COMMON_STATUS_LN3_RST_PD_READY_O_K2_E5                                                     (0x1<<8) // 0x0 - PHY is not ready to respond to ln3_rst_n_i and ln3_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to ln3_rst_n_i and ln3_pd_i[1:0].
+  #define NWS_REG_COMMON_STATUS_LN3_RST_PD_READY_O_K2_E5_SHIFT                                               8
+#define NWS_REG_LN0_CNTL_K2_E5                                                                               0x700010UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define NWS_REG_LN0_CNTL_LN0_CTRL_DATA_WIDTH_K2_E5                                                         (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 - 40bit (25G/50G) Others - Reserved
+  #define NWS_REG_LN0_CNTL_LN0_CTRL_DATA_WIDTH_K2_E5_SHIFT                                                   0
+  #define NWS_REG_LN0_CNTL_LN0_CTRL_RXPOLARITY_K2_E5                                                         (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Phy does polarity inversion.
+  #define NWS_REG_LN0_CNTL_LN0_CTRL_RXPOLARITY_K2_E5_SHIFT                                                   3
+  #define NWS_REG_LN0_CNTL_LN0_CTRL_LOS_EII_EN_K2_E5                                                         (0x1<<4) // Informs the PHY to bypass the output of the analog LOS detector and instead rely upon a protocal LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS detection via input lnX_ctrl_los_eli_value (net bit in this register).
+  #define NWS_REG_LN0_CNTL_LN0_CTRL_LOS_EII_EN_K2_E5_SHIFT                                                   4
+  #define NWS_REG_LN0_CNTL_LN0_CTRL_LOS_EII_VALUE_K2_E5                                                      (0x1<<5) // Informs the PHY that the received signal was lost.
+  #define NWS_REG_LN0_CNTL_LN0_CTRL_LOS_EII_VALUE_K2_E5_SHIFT                                                5
+  #define NWS_REG_LN0_CNTL_LN0_CTRL_DATA_RATE_I_K2_E5                                                        (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2/4.125 (1G) Others - Reserved
+  #define NWS_REG_LN0_CNTL_LN0_CTRL_DATA_RATE_I_K2_E5_SHIFT                                                  8
+#define NWS_REG_LN0_STATUS_K2_E5                                                                             0x700014UL //Access:R    DataWidth:0x5    // Multi Field Register.
+  #define NWS_REG_LN0_STATUS_LN0_STAT_OK_K2_E5                                                               (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0x1 - Lane is ready to send and receive data.
+  #define NWS_REG_LN0_STATUS_LN0_STAT_OK_K2_E5_SHIFT                                                         0
+  #define NWS_REG_LN0_STATUS_LN0_STAT_RXVALID_K2_E5                                                          (0x1<<1) // 0x0 - data on ln0_rxdata_o is invalid. 0x1 - data on the active bits of ln0_rxdata_o is valid.
+  #define NWS_REG_LN0_STATUS_LN0_STAT_RXVALID_K2_E5_SHIFT                                                    1
+  #define NWS_REG_LN0_STATUS_LN0_STAT_RUNLEN_ERR_K2_E5                                                       (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run length detector threshold. 0x1 - received data run length has exceeded the programmable run length detector threshold.
+  #define NWS_REG_LN0_STATUS_LN0_STAT_RUNLEN_ERR_K2_E5_SHIFT                                                 2
+  #define NWS_REG_LN0_STATUS_LN0_STAT_LOS_K2_E5                                                              (0x1<<3) // Loss of Signal (LOS) indicator that includes the combined functions of the digitally assisted analog LOS, digital LOS, and protocol LOS override features. 0x0 - Signal detected on ln0_rxp_i / ln0_rxm_i pins. 0x1 - No Signal detected on ln0_rxp_i / ln0_rxm_i pins.
+  #define NWS_REG_LN0_STATUS_LN0_STAT_LOS_K2_E5_SHIFT                                                        3
+  #define NWS_REG_LN0_STATUS_LN0_STAT_LOS_DEGLITCH_K2_E5                                                     (0x1<<4) // This is another LOS status indicator that is the direct output of the digitally filtered analog LOS and does not include the digital LOS and protocol LOS bypass features. This signal can be used as a wakeup signal in the case that the digital or protocol LOS features are enabled. 0x0 - Signal detected on ln0_rxp_i / ln0_rxm_i pins. 0x1 - No Signal detected on ln0_rxp_i / ln0_rxm_i pins.
+  #define NWS_REG_LN0_STATUS_LN0_STAT_LOS_DEGLITCH_K2_E5_SHIFT                                               4
+#define NWS_REG_LN0_AN_LINK_INPUTS_K2_E5                                                                     0x700018UL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_50G_CR2_I_K2_E5                                         (0x1<<0) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_50G_CR2_I_K2_E5_SHIFT                                   0
+  #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_50G_KR2_I_K2_E5                                         (0x1<<1) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_50G_KR2_I_K2_E5_SHIFT                                   1
+  #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_40G_CR4_I_K2_E5                                         (0x1<<2) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_40G_CR4_I_K2_E5_SHIFT                                   2
+  #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_40G_KR4_I_K2_E5                                         (0x1<<3) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_40G_KR4_I_K2_E5_SHIFT                                   3
+  #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_CR_I_K2_E5                                          (0x1<<4) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_CR_I_K2_E5_SHIFT                                    4
+  #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_GR_I_K2_E5                                          (0x1<<5) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_GR_I_K2_E5_SHIFT                                    5
+  #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_KR_I_K2_E5                                          (0x1<<6) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_KR_I_K2_E5_SHIFT                                    6
+  #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_10G_KR_I_K2_E5                                          (0x1<<7) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_10G_KR_I_K2_E5_SHIFT                                    7
+  #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_1G_KX_I_K2_E5                                           (0x1<<8) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_1G_KX_I_K2_E5_SHIFT                                     8
+#define NWS_REG_LN0_AN_LINK_OUTPUTS_K2_E5                                                                    0x70001cUL //Access:R    DataWidth:0x19   // Multi Field Register.
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_50G_CR2_O_K2_E5                                          (0x3<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_50G_CR2_O_K2_E5_SHIFT                                    0
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_50G_KR2_O_K2_E5                                          (0x3<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_50G_KR2_O_K2_E5_SHIFT                                    2
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_40G_CR4_O_K2_E5                                          (0x3<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_40G_CR4_O_K2_E5_SHIFT                                    4
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_40G_KR4_O_K2_E5                                          (0x3<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_40G_KR4_O_K2_E5_SHIFT                                    6
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_CR_O_K2_E5                                           (0x3<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_CR_O_K2_E5_SHIFT                                     8
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_GR_O_K2_E5                                           (0x3<<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_GR_O_K2_E5_SHIFT                                     10
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_KR_O_K2_E5                                           (0x3<<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_KR_O_K2_E5_SHIFT                                     12
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_10G_KR_O_K2_E5                                           (0x3<<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_10G_KR_O_K2_E5_SHIFT                                     14
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_1G_KX_O_K2_E5                                            (0x3<<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_1G_KX_O_K2_E5_SHIFT                                      16
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_STAT_LT_SIGDET_O_K2_E5                                             (0x1<<18) // This signal detect output corresponds to the sigdet variable described in the Ethernet LT specification.
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_STAT_LT_SIGDET_O_K2_E5_SHIFT                                       18
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_DME_OP_O_K2_E5                                                  (0x1<<19) // This is an active high signal that indicates when the auto negotiation circuit is transmitting valid DME pages. It is intended to be used in instances where the PMD output is optically or magnetically coupled, and a changing signal is always required. In those instances, this output signal may be used to turn off driver circuits during auto-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high, the auto-negotiation circuit is transmitting valid DME pages. When this signal is low, the auto-negotiation circuit is transmitting a steady idle or mark signal.
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_DME_OP_O_K2_E5_SHIFT                                            19
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_TX_PAUSE_EN_O_K2_E5                                             (0x1<<20) // This is the negotiated enable signal to allow pause control packets to be generated in the MAC and transmitted from the output of the transmitter. When this signal is a 1, it allows the transmitter to generate pause control packets according to any predetermined algorithm. When this signal is a 0, it prevents the transmitter generating pause control packets.
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_TX_PAUSE_EN_O_K2_E5_SHIFT                                       20
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_RX_PAUSE_EN_O_K2_E5                                             (0x1<<21) // This is the negotiated enable signal to allow pause control packets that have arrived at the receiver to be detected in the MAC and subsequently used to suspend the transmitter. If this bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are subsequently used to suspend the transmitter. If this bit is a 0, pause control packets that arrive at the receiver have no effect on the behavior of the transmitter.
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_RX_PAUSE_EN_O_K2_E5_SHIFT                                       21
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_FC_FEC_EN_O_K2_E5                                               (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error correction. If this output is a 1, the Clause 74 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 74 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively.
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_FC_FEC_EN_O_K2_E5_SHIFT                                         22
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_RS_FEC_EN_O_K2_E5                                               (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error correction. If this output is a 1, the Clause 91 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 91 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively.
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_RS_FEC_EN_O_K2_E5_SHIFT                                         23
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_EEE_EN_O_K2_E5                                                  (0x1<<24) // This is an active high signal that indicates the resolved EEE capability. If the output is 1, both the local device and the link partner advertise the EEE capability for the resolved PHY type. It is 0 otherewise. Note that it indicates deep sleep capability. Note the EEE capability can also be resolved by logis outside of the PHY. Therefore, the PHY does not implement any logic based on the state of this output.
+  #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_EEE_EN_O_K2_E5_SHIFT                                            24
+#define NWS_REG_LN1_CNTL_K2_E5                                                                               0x700020UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define NWS_REG_LN1_CNTL_LN1_CTRL_DATA_WIDTH_K2_E5                                                         (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 - 40bit (25G/50G) Others - Reserved
+  #define NWS_REG_LN1_CNTL_LN1_CTRL_DATA_WIDTH_K2_E5_SHIFT                                                   0
+  #define NWS_REG_LN1_CNTL_LN1_CTRL_RXPOLARITY_K2_E5                                                         (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Phy does polarity inversion.
+  #define NWS_REG_LN1_CNTL_LN1_CTRL_RXPOLARITY_K2_E5_SHIFT                                                   3
+  #define NWS_REG_LN1_CNTL_LN1_CTRL_LOS_EII_EN_K2_E5                                                         (0x1<<4) // Informs the PHY to bypass the output of the analog LOS detector and instead rely upon a protocal LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS detection via input lnX_ctrl_los_eli_value (net bit in this register).
+  #define NWS_REG_LN1_CNTL_LN1_CTRL_LOS_EII_EN_K2_E5_SHIFT                                                   4
+  #define NWS_REG_LN1_CNTL_LN1_CTRL_LOS_EII_VALUE_K2_E5                                                      (0x1<<5) // Informs the PHY that the received signal was lost.
+  #define NWS_REG_LN1_CNTL_LN1_CTRL_LOS_EII_VALUE_K2_E5_SHIFT                                                5
+  #define NWS_REG_LN1_CNTL_LN1_CTRL_DATA_RATE_I_K2_E5                                                        (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2/4.125 (1G) Others - Reserved
+  #define NWS_REG_LN1_CNTL_LN1_CTRL_DATA_RATE_I_K2_E5_SHIFT                                                  8
+#define NWS_REG_LN1_STATUS_K2_E5                                                                             0x700024UL //Access:R    DataWidth:0x5    // Multi Field Register.
+  #define NWS_REG_LN1_STATUS_LN1_STAT_OK_K2_E5                                                               (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0x1 - Lane is ready to send and receive data.
+  #define NWS_REG_LN1_STATUS_LN1_STAT_OK_K2_E5_SHIFT                                                         0
+  #define NWS_REG_LN1_STATUS_LN1_STAT_RXVALID_K2_E5                                                          (0x1<<1) // 0x0 - data on ln1_rxdata_o is invalid. 0x1 - data on the active bits of ln1_rxdata_o is valid.
+  #define NWS_REG_LN1_STATUS_LN1_STAT_RXVALID_K2_E5_SHIFT                                                    1
+  #define NWS_REG_LN1_STATUS_LN1_STAT_RUNLEN_ERR_K2_E5                                                       (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run length detector threshold. 0x1 - received data run length has exceeded the programmable run length detector threshold.
+  #define NWS_REG_LN1_STATUS_LN1_STAT_RUNLEN_ERR_K2_E5_SHIFT                                                 2
+  #define NWS_REG_LN1_STATUS_LN1_STAT_LOS_K2_E5                                                              (0x1<<3) // Loss of Signal (LOS) indicator that includes the combined functions of the digitally assisted analog LOS, digital LOS, and protocol LOS override features. 0x0 - Signal detected on ln1_rxp_i / ln1_rxm_i pins. 0x1 - No Signal detected on ln1_rxp_i / ln1_rxm_i pins.
+  #define NWS_REG_LN1_STATUS_LN1_STAT_LOS_K2_E5_SHIFT                                                        3
+  #define NWS_REG_LN1_STATUS_LN1_STAT_LOS_DEGLITCH_K2_E5                                                     (0x1<<4) // This is another LOS status indicator that is the direct output of the digitally filtered analog LOS and does not include the digital LOS and protocol LOS bypass features. This signal can be used as a wakeup signal in the case that the digital or protocol LOS features are enabled. 0x0 - Signal detected on ln1_rxp_i / ln1_rxm_i pins. 0x1 - No Signal detected on ln1_rxp_i / ln1_rxm_i pins.
+  #define NWS_REG_LN1_STATUS_LN1_STAT_LOS_DEGLITCH_K2_E5_SHIFT                                               4
+#define NWS_REG_LN1_AN_LINK_INPUTS_K2_E5                                                                     0x700028UL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_50G_CR2_I_K2_E5                                         (0x1<<0) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_50G_CR2_I_K2_E5_SHIFT                                   0
+  #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_50G_KR2_I_K2_E5                                         (0x1<<1) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_50G_KR2_I_K2_E5_SHIFT                                   1
+  #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_40G_CR4_I_K2_E5                                         (0x1<<2) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_40G_CR4_I_K2_E5_SHIFT                                   2
+  #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_40G_KR4_I_K2_E5                                         (0x1<<3) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_40G_KR4_I_K2_E5_SHIFT                                   3
+  #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_CR_I_K2_E5                                          (0x1<<4) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_CR_I_K2_E5_SHIFT                                    4
+  #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_GR_I_K2_E5                                          (0x1<<5) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_GR_I_K2_E5_SHIFT                                    5
+  #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_KR_I_K2_E5                                          (0x1<<6) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_KR_I_K2_E5_SHIFT                                    6
+  #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_10G_KR_I_K2_E5                                          (0x1<<7) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_10G_KR_I_K2_E5_SHIFT                                    7
+  #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_1G_KX_I_K2_E5                                           (0x1<<8) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_1G_KX_I_K2_E5_SHIFT                                     8
+#define NWS_REG_LN1_AN_LINK_OUTPUTS_K2_E5                                                                    0x70002cUL //Access:R    DataWidth:0x19   // Multi Field Register.
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_50G_CR2_O_K2_E5                                          (0x3<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_50G_CR2_O_K2_E5_SHIFT                                    0
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_50G_KR2_O_K2_E5                                          (0x3<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_50G_KR2_O_K2_E5_SHIFT                                    2
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_40G_CR4_O_K2_E5                                          (0x3<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_40G_CR4_O_K2_E5_SHIFT                                    4
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_40G_KR4_O_K2_E5                                          (0x3<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_40G_KR4_O_K2_E5_SHIFT                                    6
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_CR_O_K2_E5                                           (0x3<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_CR_O_K2_E5_SHIFT                                     8
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_GR_O_K2_E5                                           (0x3<<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_GR_O_K2_E5_SHIFT                                     10
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_KR_O_K2_E5                                           (0x3<<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_KR_O_K2_E5_SHIFT                                     12
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_10G_KR_O_K2_E5                                           (0x3<<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_10G_KR_O_K2_E5_SHIFT                                     14
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_1G_KX_O_K2_E5                                            (0x3<<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_1G_KX_O_K2_E5_SHIFT                                      16
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_STAT_LT_SIGDET_O_K2_E5                                             (0x1<<18) // This signal detect output corresponds to the sigdet variable described in the Ethernet LT specification.
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_STAT_LT_SIGDET_O_K2_E5_SHIFT                                       18
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_DME_OP_O_K2_E5                                                  (0x1<<19) // This is an active high signal that indicates when the auto negotiation circuit is transmitting valid DME pages. It is intended to be used in instances where the PMD output is optically or magnetically coupled, and a changing signal is always required. In those instances, this output signal may be used to turn off driver circuits during auto-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high, the auto-negotiation circuit is transmitting valid DME pages. When this signal is low, the auto-negotiation circuit is transmitting a steady idle or mark signal.
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_DME_OP_O_K2_E5_SHIFT                                            19
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_TX_PAUSE_EN_O_K2_E5                                             (0x1<<20) // This is the negotiated enable signal to allow pause control packets to be generated in the MAC and transmitted from the output of the transmitter. When this signal is a 1, it allows the transmitter to generate pause control packets according to any predetermined algorithm. When this signal is a 0, it prevents the transmitter generating pause control packets.
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_TX_PAUSE_EN_O_K2_E5_SHIFT                                       20
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_RX_PAUSE_EN_O_K2_E5                                             (0x1<<21) // This is the negotiated enable signal to allow pause control packets that have arrived at the receiver to be detected in the MAC and subsequently used to suspend the transmitter. If this bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are subsequently used to suspend the transmitter. If this bit is a 0, pause control packets that arrive at the receiver have no effect on the behavior of the transmitter.
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_RX_PAUSE_EN_O_K2_E5_SHIFT                                       21
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_FC_FEC_EN_O_K2_E5                                               (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error correction. If this output is a 1, the Clause 74 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 74 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively.
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_FC_FEC_EN_O_K2_E5_SHIFT                                         22
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_RS_FEC_EN_O_K2_E5                                               (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error correction. If this output is a 1, the Clause 91 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 91 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively.
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_RS_FEC_EN_O_K2_E5_SHIFT                                         23
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_EEE_EN_O_K2_E5                                                  (0x1<<24) // This is an active high signal that indicates the resolved EEE capability. If the output is 1, both the local device and the link partner advertise the EEE capability for the resolved PHY type. It is 0 otherewise. Note that it indicates deep sleep capability. Note the EEE capability can also be resolved by logis outside of the PHY. Therefore, the PHY does not implement any logic based on the state of this output.
+  #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_EEE_EN_O_K2_E5_SHIFT                                            24
+#define NWS_REG_LN2_CNTL_K2_E5                                                                               0x700030UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define NWS_REG_LN2_CNTL_LN2_CTRL_DATA_WIDTH_K2_E5                                                         (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 - 40bit (25G/50G) Others - Reserved
+  #define NWS_REG_LN2_CNTL_LN2_CTRL_DATA_WIDTH_K2_E5_SHIFT                                                   0
+  #define NWS_REG_LN2_CNTL_LN2_CTRL_RXPOLARITY_K2_E5                                                         (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Phy does polarity inversion.
+  #define NWS_REG_LN2_CNTL_LN2_CTRL_RXPOLARITY_K2_E5_SHIFT                                                   3
+  #define NWS_REG_LN2_CNTL_LN2_CTRL_LOS_EII_EN_K2_E5                                                         (0x1<<4) // Informs the PHY to bypass the output of the analog LOS detector and instead rely upon a protocal LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS detection via input lnX_ctrl_los_eli_value (net bit in this register).
+  #define NWS_REG_LN2_CNTL_LN2_CTRL_LOS_EII_EN_K2_E5_SHIFT                                                   4
+  #define NWS_REG_LN2_CNTL_LN2_CTRL_LOS_EII_VALUE_K2_E5                                                      (0x1<<5) // Informs the PHY that the received signal was lost.
+  #define NWS_REG_LN2_CNTL_LN2_CTRL_LOS_EII_VALUE_K2_E5_SHIFT                                                5
+  #define NWS_REG_LN2_CNTL_LN2_CTRL_DATA_RATE_I_K2_E5                                                        (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2/4.125 (1G) Others - Reserved
+  #define NWS_REG_LN2_CNTL_LN2_CTRL_DATA_RATE_I_K2_E5_SHIFT                                                  8
+#define NWS_REG_LN2_STATUS_K2_E5                                                                             0x700034UL //Access:R    DataWidth:0x5    // Multi Field Register.
+  #define NWS_REG_LN2_STATUS_LN2_STAT_OK_K2_E5                                                               (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0x1 - Lane is ready to send and receive data.
+  #define NWS_REG_LN2_STATUS_LN2_STAT_OK_K2_E5_SHIFT                                                         0
+  #define NWS_REG_LN2_STATUS_LN2_STAT_RXVALID_K2_E5                                                          (0x1<<1) // 0x0 - data on ln2_rxdata_o is invalid. 0x1 - data on the active bits of ln2_rxdata_o is valid.
+  #define NWS_REG_LN2_STATUS_LN2_STAT_RXVALID_K2_E5_SHIFT                                                    1
+  #define NWS_REG_LN2_STATUS_LN2_STAT_RUNLEN_ERR_K2_E5                                                       (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run length detector threshold. 0x1 - received data run length has exceeded the programmable run length detector threshold.
+  #define NWS_REG_LN2_STATUS_LN2_STAT_RUNLEN_ERR_K2_E5_SHIFT                                                 2
+  #define NWS_REG_LN2_STATUS_LN2_STAT_LOS_K2_E5                                                              (0x1<<3) // Loss of Signal (LOS) indicator that includes the combined functions of the digitally assisted analog LOS, digital LOS, and protocol LOS override features. 0x0 - Signal detected on ln2_rxp_i / ln2_rxm_i pins. 0x1 - No Signal detected on ln2_rxp_i / ln2_rxm_i pins.
+  #define NWS_REG_LN2_STATUS_LN2_STAT_LOS_K2_E5_SHIFT                                                        3
+  #define NWS_REG_LN2_STATUS_LN2_STAT_LOS_DEGLITCH_K2_E5                                                     (0x1<<4) // This is another LOS status indicator that is the direct output of the digitally filtered analog LOS and does not include the digital LOS and protocol LOS bypass features. This signal can be used as a wakeup signal in the case that the digital or protocol LOS features are enabled. 0x0 - Signal detected on ln2_rxp_i / ln2_rxm_i pins. 0x1 - No Signal detected on ln2_rxp_i / ln2_rxm_i pins.
+  #define NWS_REG_LN2_STATUS_LN2_STAT_LOS_DEGLITCH_K2_E5_SHIFT                                               4
+#define NWS_REG_LN2_AN_LINK_INPUTS_K2_E5                                                                     0x700038UL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_50G_CR2_I_K2_E5                                         (0x1<<0) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_50G_CR2_I_K2_E5_SHIFT                                   0
+  #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_50G_KR2_I_K2_E5                                         (0x1<<1) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_50G_KR2_I_K2_E5_SHIFT                                   1
+  #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_40G_CR4_I_K2_E5                                         (0x1<<2) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_40G_CR4_I_K2_E5_SHIFT                                   2
+  #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_40G_KR4_I_K2_E5                                         (0x1<<3) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_40G_KR4_I_K2_E5_SHIFT                                   3
+  #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_CR_I_K2_E5                                          (0x1<<4) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_CR_I_K2_E5_SHIFT                                    4
+  #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_GR_I_K2_E5                                          (0x1<<5) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_GR_I_K2_E5_SHIFT                                    5
+  #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_KR_I_K2_E5                                          (0x1<<6) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_KR_I_K2_E5_SHIFT                                    6
+  #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_10G_KR_I_K2_E5                                          (0x1<<7) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_10G_KR_I_K2_E5_SHIFT                                    7
+  #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_1G_KX_I_K2_E5                                           (0x1<<8) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_1G_KX_I_K2_E5_SHIFT                                     8
+#define NWS_REG_LN2_AN_LINK_OUTPUTS_K2_E5                                                                    0x70003cUL //Access:R    DataWidth:0x19   // Multi Field Register.
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_50G_CR2_O_K2_E5                                          (0x3<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_50G_CR2_O_K2_E5_SHIFT                                    0
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_50G_KR2_O_K2_E5                                          (0x3<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_50G_KR2_O_K2_E5_SHIFT                                    2
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_40G_CR4_O_K2_E5                                          (0x3<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_40G_CR4_O_K2_E5_SHIFT                                    4
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_40G_KR4_O_K2_E5                                          (0x3<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_40G_KR4_O_K2_E5_SHIFT                                    6
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_CR_O_K2_E5                                           (0x3<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_CR_O_K2_E5_SHIFT                                     8
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_GR_O_K2_E5                                           (0x3<<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_GR_O_K2_E5_SHIFT                                     10
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_KR_O_K2_E5                                           (0x3<<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_KR_O_K2_E5_SHIFT                                     12
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_10G_KR_O_K2_E5                                           (0x3<<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_10G_KR_O_K2_E5_SHIFT                                     14
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_1G_KX_O_K2_E5                                            (0x3<<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_1G_KX_O_K2_E5_SHIFT                                      16
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_STAT_LT_SIGDET_O_K2_E5                                             (0x1<<18) // This signal detect output corresponds to the sigdet variable described in the Ethernet LT specification.
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_STAT_LT_SIGDET_O_K2_E5_SHIFT                                       18
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_DME_OP_O_K2_E5                                                  (0x1<<19) // This is an active high signal that indicates when the auto negotiation circuit is transmitting valid DME pages. It is intended to be used in instances where the PMD output is optically or magnetically coupled, and a changing signal is always required. In those instances, this output signal may be used to turn off driver circuits during auto-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high, the auto-negotiation circuit is transmitting valid DME pages. When this signal is low, the auto-negotiation circuit is transmitting a steady idle or mark signal.
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_DME_OP_O_K2_E5_SHIFT                                            19
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_TX_PAUSE_EN_O_K2_E5                                             (0x1<<20) // This is the negotiated enable signal to allow pause control packets to be generated in the MAC and transmitted from the output of the transmitter. When this signal is a 1, it allows the transmitter to generate pause control packets according to any predetermined algorithm. When this signal is a 0, it prevents the transmitter generating pause control packets.
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_TX_PAUSE_EN_O_K2_E5_SHIFT                                       20
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_RX_PAUSE_EN_O_K2_E5                                             (0x1<<21) // This is the negotiated enable signal to allow pause control packets that have arrived at the receiver to be detected in the MAC and subsequently used to suspend the transmitter. If this bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are subsequently used to suspend the transmitter. If this bit is a 0, pause control packets that arrive at the receiver have no effect on the behavior of the transmitter.
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_RX_PAUSE_EN_O_K2_E5_SHIFT                                       21
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_FC_FEC_EN_O_K2_E5                                               (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error correction. If this output is a 1, the Clause 74 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 74 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively.
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_FC_FEC_EN_O_K2_E5_SHIFT                                         22
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_RS_FEC_EN_O_K2_E5                                               (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error correction. If this output is a 1, the Clause 91 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 91 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively.
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_RS_FEC_EN_O_K2_E5_SHIFT                                         23
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_EEE_EN_O_K2_E5                                                  (0x1<<24) // This is an active high signal that indicates the resolved EEE capability. If the output is 1, both the local device and the link partner advertise the EEE capability for the resolved PHY type. It is 0 otherewise. Note that it indicates deep sleep capability. Note the EEE capability can also be resolved by logis outside of the PHY. Therefore, the PHY does not implement any logic based on the state of this output.
+  #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_EEE_EN_O_K2_E5_SHIFT                                            24
+#define NWS_REG_LN3_CNTL_K2_E5                                                                               0x700040UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define NWS_REG_LN3_CNTL_LN3_CTRL_DATA_WIDTH_K2_E5                                                         (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 - 40bit (25G/50G) Others - Reserved
+  #define NWS_REG_LN3_CNTL_LN3_CTRL_DATA_WIDTH_K2_E5_SHIFT                                                   0
+  #define NWS_REG_LN3_CNTL_LN3_CTRL_RXPOLARITY_K2_E5                                                         (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Phy does polarity inversion.
+  #define NWS_REG_LN3_CNTL_LN3_CTRL_RXPOLARITY_K2_E5_SHIFT                                                   3
+  #define NWS_REG_LN3_CNTL_LN3_CTRL_LOS_EII_EN_K2_E5                                                         (0x1<<4) // Informs the PHY to bypass the output of the analog LOS detector and instead rely upon a protocal LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS detection via input lnX_ctrl_los_eli_value (net bit in this register).
+  #define NWS_REG_LN3_CNTL_LN3_CTRL_LOS_EII_EN_K2_E5_SHIFT                                                   4
+  #define NWS_REG_LN3_CNTL_LN3_CTRL_LOS_EII_VALUE_K2_E5                                                      (0x1<<5) // Informs the PHY that the received signal was lost.
+  #define NWS_REG_LN3_CNTL_LN3_CTRL_LOS_EII_VALUE_K2_E5_SHIFT                                                5
+  #define NWS_REG_LN3_CNTL_LN3_CTRL_DATA_RATE_I_K2_E5                                                        (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2/4.125 (1G) Others - Reserved
+  #define NWS_REG_LN3_CNTL_LN3_CTRL_DATA_RATE_I_K2_E5_SHIFT                                                  8
+#define NWS_REG_LN3_STATUS_K2_E5                                                                             0x700044UL //Access:R    DataWidth:0x5    // Multi Field Register.
+  #define NWS_REG_LN3_STATUS_LN3_STAT_OK_K2_E5                                                               (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0x1 - Lane is ready to send and receive data.
+  #define NWS_REG_LN3_STATUS_LN3_STAT_OK_K2_E5_SHIFT                                                         0
+  #define NWS_REG_LN3_STATUS_LN3_STAT_RXVALID_K2_E5                                                          (0x1<<1) // 0x0 - data on ln3_rxdata_o is invalid. 0x1 - data on the active bits of ln3_rxdata_o is valid.
+  #define NWS_REG_LN3_STATUS_LN3_STAT_RXVALID_K2_E5_SHIFT                                                    1
+  #define NWS_REG_LN3_STATUS_LN3_STAT_RUNLEN_ERR_K2_E5                                                       (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run length detector threshold. 0x1 - received data run length has exceeded the programmable run length detector threshold.
+  #define NWS_REG_LN3_STATUS_LN3_STAT_RUNLEN_ERR_K2_E5_SHIFT                                                 2
+  #define NWS_REG_LN3_STATUS_LN3_STAT_LOS_K2_E5                                                              (0x1<<3) // Loss of Signal (LOS) indicator that includes the combined functions of the digitally assisted analog LOS, digital LOS, and protocol LOS override features. 0x0 - Signal detected on ln3_rxp_i / ln3_rxm_i pins. 0x1 - No Signal detected on ln3_rxp_i / ln3_rxm_i pins.
+  #define NWS_REG_LN3_STATUS_LN3_STAT_LOS_K2_E5_SHIFT                                                        3
+  #define NWS_REG_LN3_STATUS_LN3_STAT_LOS_DEGLITCH_K2_E5                                                     (0x1<<4) // This is another LOS status indicator that is the direct output of the digitally filtered analog LOS and does not include the digital LOS and protocol LOS bypass features. This signal can be used as a wakeup signal in the case that the digital or protocol LOS features are enabled. 0x0 - Signal detected on ln3_rxp_i / ln3_rxm_i pins. 0x1 - No Signal detected on ln3_rxp_i / ln3_rxm_i pins.
+  #define NWS_REG_LN3_STATUS_LN3_STAT_LOS_DEGLITCH_K2_E5_SHIFT                                               4
+#define NWS_REG_LN3_AN_LINK_INPUTS_K2_E5                                                                     0x700048UL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_50G_CR2_I_K2_E5                                         (0x1<<0) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_50G_CR2_I_K2_E5_SHIFT                                   0
+  #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_50G_KR2_I_K2_E5                                         (0x1<<1) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_50G_KR2_I_K2_E5_SHIFT                                   1
+  #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_40G_CR4_I_K2_E5                                         (0x1<<2) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_40G_CR4_I_K2_E5_SHIFT                                   2
+  #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_40G_KR4_I_K2_E5                                         (0x1<<3) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_40G_KR4_I_K2_E5_SHIFT                                   3
+  #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_CR_I_K2_E5                                          (0x1<<4) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_CR_I_K2_E5_SHIFT                                    4
+  #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_GR_I_K2_E5                                          (0x1<<5) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_GR_I_K2_E5_SHIFT                                    5
+  #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_KR_I_K2_E5                                          (0x1<<6) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_KR_I_K2_E5_SHIFT                                    6
+  #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_10G_KR_I_K2_E5                                          (0x1<<7) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_10G_KR_I_K2_E5_SHIFT                                    7
+  #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_1G_KX_I_K2_E5                                           (0x1<<8) // Set to 1 if the respective link is receiving a valid signal from the link partner
+  #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_1G_KX_I_K2_E5_SHIFT                                     8
+#define NWS_REG_LN3_AN_LINK_OUTPUTS_K2_E5                                                                    0x70004cUL //Access:R    DataWidth:0x19   // Multi Field Register.
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_50G_CR2_O_K2_E5                                          (0x3<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_50G_CR2_O_K2_E5_SHIFT                                    0
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_50G_KR2_O_K2_E5                                          (0x3<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_50G_KR2_O_K2_E5_SHIFT                                    2
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_40G_CR4_O_K2_E5                                          (0x3<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_40G_CR4_O_K2_E5_SHIFT                                    4
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_40G_KR4_O_K2_E5                                          (0x3<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_40G_KR4_O_K2_E5_SHIFT                                    6
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_CR_O_K2_E5                                           (0x3<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_CR_O_K2_E5_SHIFT                                     8
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_GR_O_K2_E5                                           (0x3<<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_GR_O_K2_E5_SHIFT                                     10
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_KR_O_K2_E5                                           (0x3<<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_KR_O_K2_E5_SHIFT                                     12
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_10G_KR_O_K2_E5                                           (0x3<<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_10G_KR_O_K2_E5_SHIFT                                     14
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_1G_KX_O_K2_E5                                            (0x3<<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_1G_KX_O_K2_E5_SHIFT                                      16
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_STAT_LT_SIGDET_O_K2_E5                                             (0x1<<18) // This signal detect output corresponds to the sigdet variable described in the Ethernet LT specification.
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_STAT_LT_SIGDET_O_K2_E5_SHIFT                                       18
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_DME_OP_O_K2_E5                                                  (0x1<<19) // This is an active high signal that indicates when the auto negotiation circuit is transmitting valid DME pages. It is intended to be used in instances where the PMD output is optically or magnetically coupled, and a changing signal is always required. In those instances, this output signal may be used to turn off driver circuits during auto-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high, the auto-negotiation circuit is transmitting valid DME pages. When this signal is low, the auto-negotiation circuit is transmitting a steady idle or mark signal.
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_DME_OP_O_K2_E5_SHIFT                                            19
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_TX_PAUSE_EN_O_K2_E5                                             (0x1<<20) // This is the negotiated enable signal to allow pause control packets to be generated in the MAC and transmitted from the output of the transmitter. When this signal is a 1, it allows the transmitter to generate pause control packets according to any predetermined algorithm. When this signal is a 0, it prevents the transmitter generating pause control packets.
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_TX_PAUSE_EN_O_K2_E5_SHIFT                                       20
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_RX_PAUSE_EN_O_K2_E5                                             (0x1<<21) // This is the negotiated enable signal to allow pause control packets that have arrived at the receiver to be detected in the MAC and subsequently used to suspend the transmitter. If this bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are subsequently used to suspend the transmitter. If this bit is a 0, pause control packets that arrive at the receiver have no effect on the behavior of the transmitter.
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_RX_PAUSE_EN_O_K2_E5_SHIFT                                       21
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_FC_FEC_EN_O_K2_E5                                               (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error correction. If this output is a 1, the Clause 74 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 74 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively.
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_FC_FEC_EN_O_K2_E5_SHIFT                                         22
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_RS_FEC_EN_O_K2_E5                                               (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error correction. If this output is a 1, the Clause 91 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 91 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively.
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_RS_FEC_EN_O_K2_E5_SHIFT                                         23
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_EEE_EN_O_K2_E5                                                  (0x1<<24) // This is an active high signal that indicates the resolved EEE capability. If the output is 1, both the local device and the link partner advertise the EEE capability for the resolved PHY type. It is 0 otherewise. Note that it indicates deep sleep capability. Note the EEE capability can also be resolved by logis outside of the PHY. Therefore, the PHY does not implement any logic based on the state of this output.
+  #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_EEE_EN_O_K2_E5_SHIFT                                            24
+#define NWS_REG_EXTERNAL_SIGNAL_DETECT_K2_E5                                                                 0x700050UL //Access:R    DataWidth:0x4    // Multi Field Register.
+  #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P0_K2_E5                                            (0x1<<0) // Used to detect the presence of energy on SerDes receive channels or to detect the receiver loss condition(RX_LOS) from an external optical module Connects directly to pin P0_SIGDET
+  #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P0_K2_E5_SHIFT                                      0
+  #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P1_K2_E5                                            (0x1<<1) // Used to detect the presence of energy on SerDes receive channels or to detect the receiver loss condition(RX_LOS) from an external optical module Connects directly to pin P1_SIGDET
+  #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P1_K2_E5_SHIFT                                      1
+  #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P2_K2_E5                                            (0x1<<2) // Used to detect the presence of energy on SerDes receive channels or to detect the receiver loss condition(RX_LOS) from an external optical module Connects directly to pin P2_SIGDET
+  #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P2_K2_E5_SHIFT                                      2
+  #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P3_K2_E5                                            (0x1<<3) // Used to detect the presence of energy on SerDes receive channels or to detect the receiver loss condition(RX_LOS) from an external optical module Connects directly to pin P3_SIGDET
+  #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P3_K2_E5_SHIFT                                      3
+#define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_K2_E5                                                             0x700054UL //Access:R    DataWidth:0x4    // Multi Field Register.
+  #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P0_K2_E5                                    (0x1<<0) // Link Alarm Status Indication An asserted low input from the optical module or external PHY. When asserted, this signal indicates that a fault condition has been detected or cleared. Refer to the XENPAK MSA Release v3.0 for more details. This signal is an output from an external PHY that can drive LASI to the Controller to indicate a link status change or other events outlined in the XENPAK MSA standard. Connects directly to pin P0_PHY_LASI_B
+  #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P0_K2_E5_SHIFT                              0
+  #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P1_K2_E5                                    (0x1<<1) // Link Alarm Status Indication An asserted low input from the optical module or external PHY. When asserted, this signal indicates that a fault condition has been detected or cleared. Refer to the XENPAK MSA Release v3.0 for more details. This signal is an output from an external PHY that can drive LASI to the Controller to indicate a link status change or other events outlined in the XENPAK MSA standard. Connects directly to pin P1_PHY_LASI_B
+  #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P1_K2_E5_SHIFT                              1
+  #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P2_K2_E5                                    (0x1<<2) // Link Alarm Status Indication An asserted low input from the optical module or external PHY. When asserted, this signal indicates that a fault condition has been detected or cleared. Refer to the XENPAK MSA Release v3.0 for more details. This signal is an output from an external PHY that can drive LASI to the Controller to indicate a link status change or other events outlined in the XENPAK MSA standard. Connects directly to pin P2_PHY_LASI_B
+  #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P2_K2_E5_SHIFT                              2
+  #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P3_K2_E5                                    (0x1<<3) // Link Alarm Status Indication An asserted low input from the optical module or external PHY. When asserted, this signal indicates that a fault condition has been detected or cleared. Refer to the XENPAK MSA Release v3.0 for more details. This signal is an output from an external PHY that can drive LASI to the Controller to indicate a link status change or other events outlined in the XENPAK MSA standard. Connects directly to pin P3_PHY_LASI_B
+  #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P3_K2_E5_SHIFT                              3
+#define NWS_REG_ECO_RESERVED_K2_E5                                                                           0x700058UL //Access:RW   DataWidth:0x20   // This is unused register for future ECOs.
+#define NWS_REG_DBG_OUT_DATA_K2_E5                                                                           0x700100UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define NWS_REG_DBG_OUT_DATA_SIZE                                                                            8
+#define NWS_REG_DBG_OUT_VALID_K2_E5                                                                          0x700120UL //Access:R    DataWidth:0x4    // Dbgmux output valid
+#define NWS_REG_DBG_OUT_FRAME_K2_E5                                                                          0x700124UL //Access:R    DataWidth:0x4    // Dbgmux output frame
+#define NWS_REG_DBG_SELECT_K2_E5                                                                             0x700128UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define NWS_REG_DBG_DWORD_ENABLE_K2_E5                                                                       0x70012cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define NWS_REG_DBG_SHIFT_K2_E5                                                                              0x700130UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define NWS_REG_DBG_FORCE_VALID_K2_E5                                                                        0x700134UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define NWS_REG_DBG_FORCE_FRAME_K2_E5                                                                        0x700138UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define NWS_REG_DBGSYN_ALMOST_FULL_THR_K2_E5                                                                 0x70013cUL //Access:RW   DataWidth:0x4    // Debug only: If more than this Number of entries are occupied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed.
+#define NWS_REG_DBGSYN_STATUS_K2_E5                                                                          0x700140UL //Access:R    DataWidth:0x5    // Debug only: Fill level of dbgmux fifo.
+#define NWS_REG_DBG_SAMPLING_INTERVAL_K2_E5                                                                  0x700144UL //Access:RW   DataWidth:0x14   // Debug only: Sampling interval * pclk, 2ns to 2ms.
+#define NWS_REG_DBG_REPEAT_THRESHOLD_COUNT_K2_E5                                                             0x700148UL //Access:RW   DataWidth:0x4    // Debug only: If 0 or 1, trigger on first occurrence. If greater than 1, wait until counter value match to trigger.
+#define NWS_REG_DBG_POST_TRIGGER_LATENCY_COUNT_K2_E5                                                         0x70014cUL //Access:RW   DataWidth:0x18   // Debug only: If greater than 0, delay trigger count value * pclk, 0 to 32ms
+#define NWS_REG_DBG_FW_TRIGGER_ENABLE_K2_E5                                                                  0x700150UL //Access:RW   DataWidth:0x1    // Debug only: FW trigger is set.
+#define NWS_REG_INT_STS_0_K2_E5                                                                              0x700180UL //Access:R    DataWidth:0xa    // Multi Field Register.
+  #define NWS_REG_INT_STS_0_ADDRESS_ERROR_K2_E5                                                              (0x1<<0) // Signals an unknown address to the rf module.
+  #define NWS_REG_INT_STS_0_ADDRESS_ERROR_K2_E5_SHIFT                                                        0
+  #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_50G_CR2_K2_E5                                                     (0x1<<1) // Autonegotiation resolved to 50g_cr2
+  #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_50G_CR2_K2_E5_SHIFT                                               1
+  #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_50G_KR2_K2_E5                                                     (0x1<<2) // Autonegotiation resolved to 50g_kr2
+  #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_50G_KR2_K2_E5_SHIFT                                               2
+  #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_40G_CR4_K2_E5                                                     (0x1<<3) // Autonegotiation resolved to 40g_cr4
+  #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_40G_CR4_K2_E5_SHIFT                                               3
+  #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_40G_KR4_K2_E5                                                     (0x1<<4) // Autonegotiation resolved to 40g_kr4
+  #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_40G_KR4_K2_E5_SHIFT                                               4
+  #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_GR_K2_E5                                                      (0x1<<5) // Autonegotiation resolved to 25g_gr
+  #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_GR_K2_E5_SHIFT                                                5
+  #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_CR_K2_E5                                                      (0x1<<6) // Autonegotiation resolved to 25g_cr
+  #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_CR_K2_E5_SHIFT                                                6
+  #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_KR_K2_E5                                                      (0x1<<7) // Autonegotiation resolved to 25g_kr
+  #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_KR_K2_E5_SHIFT                                                7
+  #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_10G_KR_K2_E5                                                      (0x1<<8) // Autonegotiation resolved to 10g_kr
+  #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_10G_KR_K2_E5_SHIFT                                                8
+  #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_1G_KX_K2_E5                                                       (0x1<<9) // Autonegotiation resolved to 1g_kx
+  #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_1G_KX_K2_E5_SHIFT                                                 9
+#define NWS_REG_INT_MASK_0_K2_E5                                                                             0x700184UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define NWS_REG_INT_MASK_0_ADDRESS_ERROR_K2_E5                                                             (0x1<<0) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.ADDRESS_ERROR .
+  #define NWS_REG_INT_MASK_0_ADDRESS_ERROR_K2_E5_SHIFT                                                       0
+  #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_50G_CR2_K2_E5                                                    (0x1<<1) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_50G_CR2 .
+  #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_50G_CR2_K2_E5_SHIFT                                              1
+  #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_50G_KR2_K2_E5                                                    (0x1<<2) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_50G_KR2 .
+  #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_50G_KR2_K2_E5_SHIFT                                              2
+  #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_40G_CR4_K2_E5                                                    (0x1<<3) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_40G_CR4 .
+  #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_40G_CR4_K2_E5_SHIFT                                              3
+  #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_40G_KR4_K2_E5                                                    (0x1<<4) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_40G_KR4 .
+  #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_40G_KR4_K2_E5_SHIFT                                              4
+  #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_GR_K2_E5                                                     (0x1<<5) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_25G_GR .
+  #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_GR_K2_E5_SHIFT                                               5
+  #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_CR_K2_E5                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_25G_CR .
+  #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_CR_K2_E5_SHIFT                                               6
+  #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_KR_K2_E5                                                     (0x1<<7) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_25G_KR .
+  #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_KR_K2_E5_SHIFT                                               7
+  #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_10G_KR_K2_E5                                                     (0x1<<8) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_10G_KR .
+  #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_10G_KR_K2_E5_SHIFT                                               8
+  #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_1G_KX_K2_E5                                                      (0x1<<9) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_1G_KX .
+  #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_1G_KX_K2_E5_SHIFT                                                9
+#define NWS_REG_INT_STS_WR_0_K2_E5                                                                           0x700188UL //Access:WR   DataWidth:0xa    // Multi Field Register.
+  #define NWS_REG_INT_STS_WR_0_ADDRESS_ERROR_K2_E5                                                           (0x1<<0) // Signals an unknown address to the rf module.
+  #define NWS_REG_INT_STS_WR_0_ADDRESS_ERROR_K2_E5_SHIFT                                                     0
+  #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_50G_CR2_K2_E5                                                  (0x1<<1) // Autonegotiation resolved to 50g_cr2
+  #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_50G_CR2_K2_E5_SHIFT                                            1
+  #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_50G_KR2_K2_E5                                                  (0x1<<2) // Autonegotiation resolved to 50g_kr2
+  #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_50G_KR2_K2_E5_SHIFT                                            2
+  #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_40G_CR4_K2_E5                                                  (0x1<<3) // Autonegotiation resolved to 40g_cr4
+  #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_40G_CR4_K2_E5_SHIFT                                            3
+  #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_40G_KR4_K2_E5                                                  (0x1<<4) // Autonegotiation resolved to 40g_kr4
+  #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_40G_KR4_K2_E5_SHIFT                                            4
+  #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_GR_K2_E5                                                   (0x1<<5) // Autonegotiation resolved to 25g_gr
+  #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_GR_K2_E5_SHIFT                                             5
+  #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_CR_K2_E5                                                   (0x1<<6) // Autonegotiation resolved to 25g_cr
+  #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_CR_K2_E5_SHIFT                                             6
+  #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_KR_K2_E5                                                   (0x1<<7) // Autonegotiation resolved to 25g_kr
+  #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_KR_K2_E5_SHIFT                                             7
+  #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_10G_KR_K2_E5                                                   (0x1<<8) // Autonegotiation resolved to 10g_kr
+  #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_10G_KR_K2_E5_SHIFT                                             8
+  #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_1G_KX_K2_E5                                                    (0x1<<9) // Autonegotiation resolved to 1g_kx
+  #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_1G_KX_K2_E5_SHIFT                                              9
+#define NWS_REG_INT_STS_CLR_0_K2_E5                                                                          0x70018cUL //Access:RC   DataWidth:0xa    // Multi Field Register.
+  #define NWS_REG_INT_STS_CLR_0_ADDRESS_ERROR_K2_E5                                                          (0x1<<0) // Signals an unknown address to the rf module.
+  #define NWS_REG_INT_STS_CLR_0_ADDRESS_ERROR_K2_E5_SHIFT                                                    0
+  #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_50G_CR2_K2_E5                                                 (0x1<<1) // Autonegotiation resolved to 50g_cr2
+  #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_50G_CR2_K2_E5_SHIFT                                           1
+  #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_50G_KR2_K2_E5                                                 (0x1<<2) // Autonegotiation resolved to 50g_kr2
+  #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_50G_KR2_K2_E5_SHIFT                                           2
+  #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_40G_CR4_K2_E5                                                 (0x1<<3) // Autonegotiation resolved to 40g_cr4
+  #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_40G_CR4_K2_E5_SHIFT                                           3
+  #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_40G_KR4_K2_E5                                                 (0x1<<4) // Autonegotiation resolved to 40g_kr4
+  #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_40G_KR4_K2_E5_SHIFT                                           4
+  #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_GR_K2_E5                                                  (0x1<<5) // Autonegotiation resolved to 25g_gr
+  #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_GR_K2_E5_SHIFT                                            5
+  #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_CR_K2_E5                                                  (0x1<<6) // Autonegotiation resolved to 25g_cr
+  #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_CR_K2_E5_SHIFT                                            6
+  #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_KR_K2_E5                                                  (0x1<<7) // Autonegotiation resolved to 25g_kr
+  #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_KR_K2_E5_SHIFT                                            7
+  #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_10G_KR_K2_E5                                                  (0x1<<8) // Autonegotiation resolved to 10g_kr
+  #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_10G_KR_K2_E5_SHIFT                                            8
+  #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_1G_KX_K2_E5                                                   (0x1<<9) // Autonegotiation resolved to 1g_kx
+  #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_1G_KX_K2_E5_SHIFT                                             9
+#define NWS_REG_INT_STS_1_K2_E5                                                                              0x700190UL //Access:R    DataWidth:0xa    // Multi Field Register.
+  #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_50G_CR2_K2_E5                                                     (0x1<<1) // Autonegotiation resolved to 50g_cr2
+  #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_50G_CR2_K2_E5_SHIFT                                               1
+  #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_50G_KR2_K2_E5                                                     (0x1<<2) // Autonegotiation resolved to 50g_kr2
+  #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_50G_KR2_K2_E5_SHIFT                                               2
+  #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_40G_CR4_K2_E5                                                     (0x1<<3) // Autonegotiation resolved to 40g_cr4
+  #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_40G_CR4_K2_E5_SHIFT                                               3
+  #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_40G_KR4_K2_E5                                                     (0x1<<4) // Autonegotiation resolved to 40g_kr4
+  #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_40G_KR4_K2_E5_SHIFT                                               4
+  #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_GR_K2_E5                                                      (0x1<<5) // Autonegotiation resolved to 25g_gr
+  #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_GR_K2_E5_SHIFT                                                5
+  #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_CR_K2_E5                                                      (0x1<<6) // Autonegotiation resolved to 25g_cr
+  #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_CR_K2_E5_SHIFT                                                6
+  #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_KR_K2_E5                                                      (0x1<<7) // Autonegotiation resolved to 25g_kr
+  #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_KR_K2_E5_SHIFT                                                7
+  #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_10G_KR_K2_E5                                                      (0x1<<8) // Autonegotiation resolved to 10g_kr
+  #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_10G_KR_K2_E5_SHIFT                                                8
+  #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_1G_KX_K2_E5                                                       (0x1<<9) // Autonegotiation resolved to 1g_kx
+  #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_1G_KX_K2_E5_SHIFT                                                 9
+#define NWS_REG_INT_MASK_1_K2_E5                                                                             0x700194UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_50G_CR2_K2_E5                                                    (0x1<<1) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_50G_CR2 .
+  #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_50G_CR2_K2_E5_SHIFT                                              1
+  #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_50G_KR2_K2_E5                                                    (0x1<<2) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_50G_KR2 .
+  #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_50G_KR2_K2_E5_SHIFT                                              2
+  #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_40G_CR4_K2_E5                                                    (0x1<<3) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_40G_CR4 .
+  #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_40G_CR4_K2_E5_SHIFT                                              3
+  #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_40G_KR4_K2_E5                                                    (0x1<<4) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_40G_KR4 .
+  #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_40G_KR4_K2_E5_SHIFT                                              4
+  #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_GR_K2_E5                                                     (0x1<<5) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_25G_GR .
+  #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_GR_K2_E5_SHIFT                                               5
+  #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_CR_K2_E5                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_25G_CR .
+  #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_CR_K2_E5_SHIFT                                               6
+  #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_KR_K2_E5                                                     (0x1<<7) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_25G_KR .
+  #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_KR_K2_E5_SHIFT                                               7
+  #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_10G_KR_K2_E5                                                     (0x1<<8) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_10G_KR .
+  #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_10G_KR_K2_E5_SHIFT                                               8
+  #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_1G_KX_K2_E5                                                      (0x1<<9) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_1G_KX .
+  #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_1G_KX_K2_E5_SHIFT                                                9
+#define NWS_REG_INT_STS_WR_1_K2_E5                                                                           0x700198UL //Access:WR   DataWidth:0xa    // Multi Field Register.
+  #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_50G_CR2_K2_E5                                                  (0x1<<1) // Autonegotiation resolved to 50g_cr2
+  #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_50G_CR2_K2_E5_SHIFT                                            1
+  #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_50G_KR2_K2_E5                                                  (0x1<<2) // Autonegotiation resolved to 50g_kr2
+  #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_50G_KR2_K2_E5_SHIFT                                            2
+  #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_40G_CR4_K2_E5                                                  (0x1<<3) // Autonegotiation resolved to 40g_cr4
+  #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_40G_CR4_K2_E5_SHIFT                                            3
+  #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_40G_KR4_K2_E5                                                  (0x1<<4) // Autonegotiation resolved to 40g_kr4
+  #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_40G_KR4_K2_E5_SHIFT                                            4
+  #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_GR_K2_E5                                                   (0x1<<5) // Autonegotiation resolved to 25g_gr
+  #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_GR_K2_E5_SHIFT                                             5
+  #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_CR_K2_E5                                                   (0x1<<6) // Autonegotiation resolved to 25g_cr
+  #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_CR_K2_E5_SHIFT                                             6
+  #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_KR_K2_E5                                                   (0x1<<7) // Autonegotiation resolved to 25g_kr
+  #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_KR_K2_E5_SHIFT                                             7
+  #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_10G_KR_K2_E5                                                   (0x1<<8) // Autonegotiation resolved to 10g_kr
+  #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_10G_KR_K2_E5_SHIFT                                             8
+  #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_1G_KX_K2_E5                                                    (0x1<<9) // Autonegotiation resolved to 1g_kx
+  #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_1G_KX_K2_E5_SHIFT                                              9
+#define NWS_REG_INT_STS_CLR_1_K2_E5                                                                          0x70019cUL //Access:RC   DataWidth:0xa    // Multi Field Register.
+  #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_50G_CR2_K2_E5                                                 (0x1<<1) // Autonegotiation resolved to 50g_cr2
+  #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_50G_CR2_K2_E5_SHIFT                                           1
+  #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_50G_KR2_K2_E5                                                 (0x1<<2) // Autonegotiation resolved to 50g_kr2
+  #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_50G_KR2_K2_E5_SHIFT                                           2
+  #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_40G_CR4_K2_E5                                                 (0x1<<3) // Autonegotiation resolved to 40g_cr4
+  #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_40G_CR4_K2_E5_SHIFT                                           3
+  #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_40G_KR4_K2_E5                                                 (0x1<<4) // Autonegotiation resolved to 40g_kr4
+  #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_40G_KR4_K2_E5_SHIFT                                           4
+  #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_GR_K2_E5                                                  (0x1<<5) // Autonegotiation resolved to 25g_gr
+  #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_GR_K2_E5_SHIFT                                            5
+  #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_CR_K2_E5                                                  (0x1<<6) // Autonegotiation resolved to 25g_cr
+  #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_CR_K2_E5_SHIFT                                            6
+  #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_KR_K2_E5                                                  (0x1<<7) // Autonegotiation resolved to 25g_kr
+  #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_KR_K2_E5_SHIFT                                            7
+  #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_10G_KR_K2_E5                                                  (0x1<<8) // Autonegotiation resolved to 10g_kr
+  #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_10G_KR_K2_E5_SHIFT                                            8
+  #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_1G_KX_K2_E5                                                   (0x1<<9) // Autonegotiation resolved to 1g_kx
+  #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_1G_KX_K2_E5_SHIFT                                             9
+#define NWS_REG_INT_STS_2_K2_E5                                                                              0x7001a0UL //Access:R    DataWidth:0xa    // Multi Field Register.
+  #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_50G_CR2_K2_E5                                                     (0x1<<1) // Autonegotiation resolved to 50g_cr2
+  #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_50G_CR2_K2_E5_SHIFT                                               1
+  #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_50G_KR2_K2_E5                                                     (0x1<<2) // Autonegotiation resolved to 50g_kr2
+  #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_50G_KR2_K2_E5_SHIFT                                               2
+  #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_40G_CR4_K2_E5                                                     (0x1<<3) // Autonegotiation resolved to 40g_cr4
+  #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_40G_CR4_K2_E5_SHIFT                                               3
+  #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_40G_KR4_K2_E5                                                     (0x1<<4) // Autonegotiation resolved to 40g_kr4
+  #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_40G_KR4_K2_E5_SHIFT                                               4
+  #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_GR_K2_E5                                                      (0x1<<5) // Autonegotiation resolved to 25g_gr
+  #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_GR_K2_E5_SHIFT                                                5
+  #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_CR_K2_E5                                                      (0x1<<6) // Autonegotiation resolved to 25g_cr
+  #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_CR_K2_E5_SHIFT                                                6
+  #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_KR_K2_E5                                                      (0x1<<7) // Autonegotiation resolved to 25g_kr
+  #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_KR_K2_E5_SHIFT                                                7
+  #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_10G_KR_K2_E5                                                      (0x1<<8) // Autonegotiation resolved to 10g_kr
+  #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_10G_KR_K2_E5_SHIFT                                                8
+  #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_1G_KX_K2_E5                                                       (0x1<<9) // Autonegotiation resolved to 1g_kx
+  #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_1G_KX_K2_E5_SHIFT                                                 9
+#define NWS_REG_INT_MASK_2_K2_E5                                                                             0x7001a4UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_50G_CR2_K2_E5                                                    (0x1<<1) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_50G_CR2 .
+  #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_50G_CR2_K2_E5_SHIFT                                              1
+  #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_50G_KR2_K2_E5                                                    (0x1<<2) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_50G_KR2 .
+  #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_50G_KR2_K2_E5_SHIFT                                              2
+  #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_40G_CR4_K2_E5                                                    (0x1<<3) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_40G_CR4 .
+  #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_40G_CR4_K2_E5_SHIFT                                              3
+  #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_40G_KR4_K2_E5                                                    (0x1<<4) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_40G_KR4 .
+  #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_40G_KR4_K2_E5_SHIFT                                              4
+  #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_GR_K2_E5                                                     (0x1<<5) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_25G_GR .
+  #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_GR_K2_E5_SHIFT                                               5
+  #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_CR_K2_E5                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_25G_CR .
+  #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_CR_K2_E5_SHIFT                                               6
+  #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_KR_K2_E5                                                     (0x1<<7) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_25G_KR .
+  #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_KR_K2_E5_SHIFT                                               7
+  #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_10G_KR_K2_E5                                                     (0x1<<8) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_10G_KR .
+  #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_10G_KR_K2_E5_SHIFT                                               8
+  #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_1G_KX_K2_E5                                                      (0x1<<9) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_1G_KX .
+  #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_1G_KX_K2_E5_SHIFT                                                9
+#define NWS_REG_INT_STS_WR_2_K2_E5                                                                           0x7001a8UL //Access:WR   DataWidth:0xa    // Multi Field Register.
+  #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_50G_CR2_K2_E5                                                  (0x1<<1) // Autonegotiation resolved to 50g_cr2
+  #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_50G_CR2_K2_E5_SHIFT                                            1
+  #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_50G_KR2_K2_E5                                                  (0x1<<2) // Autonegotiation resolved to 50g_kr2
+  #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_50G_KR2_K2_E5_SHIFT                                            2
+  #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_40G_CR4_K2_E5                                                  (0x1<<3) // Autonegotiation resolved to 40g_cr4
+  #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_40G_CR4_K2_E5_SHIFT                                            3
+  #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_40G_KR4_K2_E5                                                  (0x1<<4) // Autonegotiation resolved to 40g_kr4
+  #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_40G_KR4_K2_E5_SHIFT                                            4
+  #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_GR_K2_E5                                                   (0x1<<5) // Autonegotiation resolved to 25g_gr
+  #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_GR_K2_E5_SHIFT                                             5
+  #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_CR_K2_E5                                                   (0x1<<6) // Autonegotiation resolved to 25g_cr
+  #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_CR_K2_E5_SHIFT                                             6
+  #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_KR_K2_E5                                                   (0x1<<7) // Autonegotiation resolved to 25g_kr
+  #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_KR_K2_E5_SHIFT                                             7
+  #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_10G_KR_K2_E5                                                   (0x1<<8) // Autonegotiation resolved to 10g_kr
+  #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_10G_KR_K2_E5_SHIFT                                             8
+  #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_1G_KX_K2_E5                                                    (0x1<<9) // Autonegotiation resolved to 1g_kx
+  #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_1G_KX_K2_E5_SHIFT                                              9
+#define NWS_REG_INT_STS_CLR_2_K2_E5                                                                          0x7001acUL //Access:RC   DataWidth:0xa    // Multi Field Register.
+  #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_50G_CR2_K2_E5                                                 (0x1<<1) // Autonegotiation resolved to 50g_cr2
+  #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_50G_CR2_K2_E5_SHIFT                                           1
+  #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_50G_KR2_K2_E5                                                 (0x1<<2) // Autonegotiation resolved to 50g_kr2
+  #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_50G_KR2_K2_E5_SHIFT                                           2
+  #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_40G_CR4_K2_E5                                                 (0x1<<3) // Autonegotiation resolved to 40g_cr4
+  #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_40G_CR4_K2_E5_SHIFT                                           3
+  #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_40G_KR4_K2_E5                                                 (0x1<<4) // Autonegotiation resolved to 40g_kr4
+  #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_40G_KR4_K2_E5_SHIFT                                           4
+  #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_GR_K2_E5                                                  (0x1<<5) // Autonegotiation resolved to 25g_gr
+  #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_GR_K2_E5_SHIFT                                            5
+  #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_CR_K2_E5                                                  (0x1<<6) // Autonegotiation resolved to 25g_cr
+  #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_CR_K2_E5_SHIFT                                            6
+  #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_KR_K2_E5                                                  (0x1<<7) // Autonegotiation resolved to 25g_kr
+  #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_KR_K2_E5_SHIFT                                            7
+  #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_10G_KR_K2_E5                                                  (0x1<<8) // Autonegotiation resolved to 10g_kr
+  #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_10G_KR_K2_E5_SHIFT                                            8
+  #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_1G_KX_K2_E5                                                   (0x1<<9) // Autonegotiation resolved to 1g_kx
+  #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_1G_KX_K2_E5_SHIFT                                             9
+#define NWS_REG_INT_STS_3_K2_E5                                                                              0x7001b0UL //Access:R    DataWidth:0xa    // Multi Field Register.
+  #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_50G_CR2_K2_E5                                                     (0x1<<1) // Autonegotiation resolved to 50g_cr2
+  #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_50G_CR2_K2_E5_SHIFT                                               1
+  #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_50G_KR2_K2_E5                                                     (0x1<<2) // Autonegotiation resolved to 50g_kr2
+  #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_50G_KR2_K2_E5_SHIFT                                               2
+  #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_40G_CR4_K2_E5                                                     (0x1<<3) // Autonegotiation resolved to 40g_cr4
+  #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_40G_CR4_K2_E5_SHIFT                                               3
+  #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_40G_KR4_K2_E5                                                     (0x1<<4) // Autonegotiation resolved to 40g_kr4
+  #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_40G_KR4_K2_E5_SHIFT                                               4
+  #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_GR_K2_E5                                                      (0x1<<5) // Autonegotiation resolved to 25g_gr
+  #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_GR_K2_E5_SHIFT                                                5
+  #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_CR_K2_E5                                                      (0x1<<6) // Autonegotiation resolved to 25g_cr
+  #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_CR_K2_E5_SHIFT                                                6
+  #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_KR_K2_E5                                                      (0x1<<7) // Autonegotiation resolved to 25g_kr
+  #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_KR_K2_E5_SHIFT                                                7
+  #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_10G_KR_K2_E5                                                      (0x1<<8) // Autonegotiation resolved to 10g_kr
+  #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_10G_KR_K2_E5_SHIFT                                                8
+  #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_1G_KX_K2_E5                                                       (0x1<<9) // Autonegotiation resolved to 1g_kx
+  #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_1G_KX_K2_E5_SHIFT                                                 9
+#define NWS_REG_INT_MASK_3_K2_E5                                                                             0x7001b4UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_50G_CR2_K2_E5                                                    (0x1<<1) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_50G_CR2 .
+  #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_50G_CR2_K2_E5_SHIFT                                              1
+  #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_50G_KR2_K2_E5                                                    (0x1<<2) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_50G_KR2 .
+  #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_50G_KR2_K2_E5_SHIFT                                              2
+  #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_40G_CR4_K2_E5                                                    (0x1<<3) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_40G_CR4 .
+  #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_40G_CR4_K2_E5_SHIFT                                              3
+  #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_40G_KR4_K2_E5                                                    (0x1<<4) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_40G_KR4 .
+  #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_40G_KR4_K2_E5_SHIFT                                              4
+  #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_GR_K2_E5                                                     (0x1<<5) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_25G_GR .
+  #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_GR_K2_E5_SHIFT                                               5
+  #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_CR_K2_E5                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_25G_CR .
+  #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_CR_K2_E5_SHIFT                                               6
+  #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_KR_K2_E5                                                     (0x1<<7) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_25G_KR .
+  #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_KR_K2_E5_SHIFT                                               7
+  #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_10G_KR_K2_E5                                                     (0x1<<8) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_10G_KR .
+  #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_10G_KR_K2_E5_SHIFT                                               8
+  #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_1G_KX_K2_E5                                                      (0x1<<9) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_1G_KX .
+  #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_1G_KX_K2_E5_SHIFT                                                9
+#define NWS_REG_INT_STS_WR_3_K2_E5                                                                           0x7001b8UL //Access:WR   DataWidth:0xa    // Multi Field Register.
+  #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_50G_CR2_K2_E5                                                  (0x1<<1) // Autonegotiation resolved to 50g_cr2
+  #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_50G_CR2_K2_E5_SHIFT                                            1
+  #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_50G_KR2_K2_E5                                                  (0x1<<2) // Autonegotiation resolved to 50g_kr2
+  #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_50G_KR2_K2_E5_SHIFT                                            2
+  #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_40G_CR4_K2_E5                                                  (0x1<<3) // Autonegotiation resolved to 40g_cr4
+  #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_40G_CR4_K2_E5_SHIFT                                            3
+  #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_40G_KR4_K2_E5                                                  (0x1<<4) // Autonegotiation resolved to 40g_kr4
+  #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_40G_KR4_K2_E5_SHIFT                                            4
+  #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_GR_K2_E5                                                   (0x1<<5) // Autonegotiation resolved to 25g_gr
+  #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_GR_K2_E5_SHIFT                                             5
+  #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_CR_K2_E5                                                   (0x1<<6) // Autonegotiation resolved to 25g_cr
+  #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_CR_K2_E5_SHIFT                                             6
+  #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_KR_K2_E5                                                   (0x1<<7) // Autonegotiation resolved to 25g_kr
+  #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_KR_K2_E5_SHIFT                                             7
+  #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_10G_KR_K2_E5                                                   (0x1<<8) // Autonegotiation resolved to 10g_kr
+  #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_10G_KR_K2_E5_SHIFT                                             8
+  #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_1G_KX_K2_E5                                                    (0x1<<9) // Autonegotiation resolved to 1g_kx
+  #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_1G_KX_K2_E5_SHIFT                                              9
+#define NWS_REG_INT_STS_CLR_3_K2_E5                                                                          0x7001bcUL //Access:RC   DataWidth:0xa    // Multi Field Register.
+  #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_50G_CR2_K2_E5                                                 (0x1<<1) // Autonegotiation resolved to 50g_cr2
+  #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_50G_CR2_K2_E5_SHIFT                                           1
+  #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_50G_KR2_K2_E5                                                 (0x1<<2) // Autonegotiation resolved to 50g_kr2
+  #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_50G_KR2_K2_E5_SHIFT                                           2
+  #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_40G_CR4_K2_E5                                                 (0x1<<3) // Autonegotiation resolved to 40g_cr4
+  #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_40G_CR4_K2_E5_SHIFT                                           3
+  #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_40G_KR4_K2_E5                                                 (0x1<<4) // Autonegotiation resolved to 40g_kr4
+  #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_40G_KR4_K2_E5_SHIFT                                           4
+  #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_GR_K2_E5                                                  (0x1<<5) // Autonegotiation resolved to 25g_gr
+  #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_GR_K2_E5_SHIFT                                            5
+  #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_CR_K2_E5                                                  (0x1<<6) // Autonegotiation resolved to 25g_cr
+  #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_CR_K2_E5_SHIFT                                            6
+  #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_KR_K2_E5                                                  (0x1<<7) // Autonegotiation resolved to 25g_kr
+  #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_KR_K2_E5_SHIFT                                            7
+  #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_10G_KR_K2_E5                                                  (0x1<<8) // Autonegotiation resolved to 10g_kr
+  #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_10G_KR_K2_E5_SHIFT                                            8
+  #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_1G_KX_K2_E5                                                   (0x1<<9) // Autonegotiation resolved to 1g_kx
+  #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_1G_KX_K2_E5_SHIFT                                             9
+#define NWS_REG_PRTY_MASK_H_0_K2_E5                                                                          0x700204UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define NWS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_E5                                                      (0x1<<0) // This bit masks, when set, the Parity bit: NWS_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define NWS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_E5_SHIFT                                                0
+  #define NWS_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_K2_E5                                                      (0x1<<1) // This bit masks, when set, the Parity bit: NWS_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define NWS_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_K2_E5_SHIFT                                                1
+  #define NWS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_E5                                                      (0x1<<2) // This bit masks, when set, the Parity bit: NWS_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define NWS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_E5_SHIFT                                                2
+  #define NWS_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_E5                                                      (0x1<<3) // This bit masks, when set, the Parity bit: NWS_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define NWS_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_E5_SHIFT                                                3
+#define NWS_REG_MEM_ECC_EVENTS_K2_E5                                                                         0x700210UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define NWS_REG_NWS_CMU_K2_E5                                                                                0x720000UL //Access:RW   DataWidth:0x8    // PHY Top registers = 0-0x7ff. CMU0 registers    = 0x0800-0x0bff. CMU1 registers    = 0x0c00-0x0fff. Reserved          = 0x1000-0x17ff. LANE0 registers   = 0x1800-0x1fff. LANE1 registers   = 0x2000-0x27ff. LANE2 registers   = 0x2800-0x2fff. LANE3 registers   = 0x3000-0x37ff. Please see IPXACT_Capri_4l2c.xml for details.
+#define NWS_REG_NWS_CMU_SIZE                                                                                 20479
+#define NWS_REG_NWS_DATA_RAM_ACCESS_K2_E5                                                                    0x740000UL //Access:RW   DataWidth:0x20   // Used to load operating tables into data ram. Each register location is 4 bytes in ram. bits[31:24] = ram address [0] bits[23:16] = ram address [1] bits[15:8]  = ram address [2] bits[7:0]   = ram address [3] register 0 = ram location [3:0] register 1 = ram location [7:4] register 2 = ram location [11:8]
+#define NWS_REG_NWS_DATA_RAM_ACCESS_SIZE                                                                     2048
+#define NWS_REG_NWS_PROGRAM_RAM_ACCESS_K2_E5                                                                 0x760000UL //Access:RW   DataWidth:0x20   // Used to load operating firmware into program ram. Each register location is 4 bytes in ram. bits[31:24] = ram address [0] bits[23:16] = ram address [1] bits[15:8]  = ram address [2] bits[7:0]   = ram address [3] register 0 = ram location [3:0] register 1 = ram location [7:4] register 2 = ram location [11:8]
+#define NWS_REG_NWS_PROGRAM_RAM_ACCESS_SIZE                                                                  32768
+#define NWM_REG_INT_STS_K2_E5                                                                                0x800004UL //Access:R    DataWidth:0x18   // Multi Field Register.
+  #define NWM_REG_INT_STS_ADDRESS_ERROR_K2_E5                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define NWM_REG_INT_STS_ADDRESS_ERROR_K2_E5_SHIFT                                                          0
+  #define NWM_REG_INT_STS_TX_OVERFLOW_0_K2_E5                                                                (0x1<<1) // TX fifo overflow
+  #define NWM_REG_INT_STS_TX_OVERFLOW_0_K2_E5_SHIFT                                                          1
+  #define NWM_REG_INT_STS_TX_UNDERFLOW_0_K2_E5                                                               (0x1<<2) // TX fifo underflow
+  #define NWM_REG_INT_STS_TX_UNDERFLOW_0_K2_E5_SHIFT                                                         2
+  #define NWM_REG_INT_STS_TX_OVERFLOW_1_K2_E5                                                                (0x1<<3) // TX fifo overflow
+  #define NWM_REG_INT_STS_TX_OVERFLOW_1_K2_E5_SHIFT                                                          3
+  #define NWM_REG_INT_STS_TX_UNDERFLOW_1_K2_E5                                                               (0x1<<4) // TX fifo underflow
+  #define NWM_REG_INT_STS_TX_UNDERFLOW_1_K2_E5_SHIFT                                                         4
+  #define NWM_REG_INT_STS_TX_OVERFLOW_2_K2_E5                                                                (0x1<<5) // TX fifo overflow
+  #define NWM_REG_INT_STS_TX_OVERFLOW_2_K2_E5_SHIFT                                                          5
+  #define NWM_REG_INT_STS_TX_UNDERFLOW_2_K2_E5                                                               (0x1<<6) // TX fifo underflow
+  #define NWM_REG_INT_STS_TX_UNDERFLOW_2_K2_E5_SHIFT                                                         6
+  #define NWM_REG_INT_STS_TX_OVERFLOW_3_K2_E5                                                                (0x1<<7) // TX fifo overflow
+  #define NWM_REG_INT_STS_TX_OVERFLOW_3_K2_E5_SHIFT                                                          7
+  #define NWM_REG_INT_STS_TX_UNDERFLOW_3_K2_E5                                                               (0x1<<8) // TX fifo underflow
+  #define NWM_REG_INT_STS_TX_UNDERFLOW_3_K2_E5_SHIFT                                                         8
+  #define NWM_REG_INT_STS_LN0_AT_10M_K2_E5                                                                   (0x1<<16) // Lane 0 Resolved to 10Mb rate
+  #define NWM_REG_INT_STS_LN0_AT_10M_K2_E5_SHIFT                                                             16
+  #define NWM_REG_INT_STS_LN0_AT_100M_K2_E5                                                                  (0x1<<17) // Lane 0 Resolved to 100Mb rate
+  #define NWM_REG_INT_STS_LN0_AT_100M_K2_E5_SHIFT                                                            17
+  #define NWM_REG_INT_STS_LN1_AT_10M_K2_E5                                                                   (0x1<<18) // Lane 1 Resolved to 10Mb rate
+  #define NWM_REG_INT_STS_LN1_AT_10M_K2_E5_SHIFT                                                             18
+  #define NWM_REG_INT_STS_LN1_AT_100M_K2_E5                                                                  (0x1<<19) // Lane 1 Resolved to 100Mb rate
+  #define NWM_REG_INT_STS_LN1_AT_100M_K2_E5_SHIFT                                                            19
+  #define NWM_REG_INT_STS_LN2_AT_10M_K2_E5                                                                   (0x1<<20) // Lane 2 Resolved to 10Mb rate
+  #define NWM_REG_INT_STS_LN2_AT_10M_K2_E5_SHIFT                                                             20
+  #define NWM_REG_INT_STS_LN2_AT_100M_K2_E5                                                                  (0x1<<21) // Lane 2 Resolved to 100Mb rate
+  #define NWM_REG_INT_STS_LN2_AT_100M_K2_E5_SHIFT                                                            21
+  #define NWM_REG_INT_STS_LN3_AT_10M_K2_E5                                                                   (0x1<<22) // Lane 3 Resolved to 10Mb rate
+  #define NWM_REG_INT_STS_LN3_AT_10M_K2_E5_SHIFT                                                             22
+  #define NWM_REG_INT_STS_LN3_AT_100M_K2_E5                                                                  (0x1<<23) // Lane 3 Resolved to 100Mb rate
+  #define NWM_REG_INT_STS_LN3_AT_100M_K2_E5_SHIFT                                                            23
+#define NWM_REG_INT_MASK_K2_E5                                                                               0x800008UL //Access:RW   DataWidth:0x18   // Multi Field Register.
+  #define NWM_REG_INT_MASK_ADDRESS_ERROR_K2_E5                                                               (0x1<<0) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.ADDRESS_ERROR .
+  #define NWM_REG_INT_MASK_ADDRESS_ERROR_K2_E5_SHIFT                                                         0
+  #define NWM_REG_INT_MASK_TX_OVERFLOW_0_K2_E5                                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.TX_OVERFLOW_0 .
+  #define NWM_REG_INT_MASK_TX_OVERFLOW_0_K2_E5_SHIFT                                                         1
+  #define NWM_REG_INT_MASK_TX_UNDERFLOW_0_K2_E5                                                              (0x1<<2) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.TX_UNDERFLOW_0 .
+  #define NWM_REG_INT_MASK_TX_UNDERFLOW_0_K2_E5_SHIFT                                                        2
+  #define NWM_REG_INT_MASK_TX_OVERFLOW_1_K2_E5                                                               (0x1<<3) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.TX_OVERFLOW_1 .
+  #define NWM_REG_INT_MASK_TX_OVERFLOW_1_K2_E5_SHIFT                                                         3
+  #define NWM_REG_INT_MASK_TX_UNDERFLOW_1_K2_E5                                                              (0x1<<4) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.TX_UNDERFLOW_1 .
+  #define NWM_REG_INT_MASK_TX_UNDERFLOW_1_K2_E5_SHIFT                                                        4
+  #define NWM_REG_INT_MASK_TX_OVERFLOW_2_K2_E5                                                               (0x1<<5) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.TX_OVERFLOW_2 .
+  #define NWM_REG_INT_MASK_TX_OVERFLOW_2_K2_E5_SHIFT                                                         5
+  #define NWM_REG_INT_MASK_TX_UNDERFLOW_2_K2_E5                                                              (0x1<<6) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.TX_UNDERFLOW_2 .
+  #define NWM_REG_INT_MASK_TX_UNDERFLOW_2_K2_E5_SHIFT                                                        6
+  #define NWM_REG_INT_MASK_TX_OVERFLOW_3_K2_E5                                                               (0x1<<7) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.TX_OVERFLOW_3 .
+  #define NWM_REG_INT_MASK_TX_OVERFLOW_3_K2_E5_SHIFT                                                         7
+  #define NWM_REG_INT_MASK_TX_UNDERFLOW_3_K2_E5                                                              (0x1<<8) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.TX_UNDERFLOW_3 .
+  #define NWM_REG_INT_MASK_TX_UNDERFLOW_3_K2_E5_SHIFT                                                        8
+  #define NWM_REG_INT_MASK_LN0_AT_10M_K2_E5                                                                  (0x1<<16) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.LN0_AT_10M .
+  #define NWM_REG_INT_MASK_LN0_AT_10M_K2_E5_SHIFT                                                            16
+  #define NWM_REG_INT_MASK_LN0_AT_100M_K2_E5                                                                 (0x1<<17) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.LN0_AT_100M .
+  #define NWM_REG_INT_MASK_LN0_AT_100M_K2_E5_SHIFT                                                           17
+  #define NWM_REG_INT_MASK_LN1_AT_10M_K2_E5                                                                  (0x1<<18) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.LN1_AT_10M .
+  #define NWM_REG_INT_MASK_LN1_AT_10M_K2_E5_SHIFT                                                            18
+  #define NWM_REG_INT_MASK_LN1_AT_100M_K2_E5                                                                 (0x1<<19) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.LN1_AT_100M .
+  #define NWM_REG_INT_MASK_LN1_AT_100M_K2_E5_SHIFT                                                           19
+  #define NWM_REG_INT_MASK_LN2_AT_10M_K2_E5                                                                  (0x1<<20) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.LN2_AT_10M .
+  #define NWM_REG_INT_MASK_LN2_AT_10M_K2_E5_SHIFT                                                            20
+  #define NWM_REG_INT_MASK_LN2_AT_100M_K2_E5                                                                 (0x1<<21) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.LN2_AT_100M .
+  #define NWM_REG_INT_MASK_LN2_AT_100M_K2_E5_SHIFT                                                           21
+  #define NWM_REG_INT_MASK_LN3_AT_10M_K2_E5                                                                  (0x1<<22) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.LN3_AT_10M .
+  #define NWM_REG_INT_MASK_LN3_AT_10M_K2_E5_SHIFT                                                            22
+  #define NWM_REG_INT_MASK_LN3_AT_100M_K2_E5                                                                 (0x1<<23) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.LN3_AT_100M .
+  #define NWM_REG_INT_MASK_LN3_AT_100M_K2_E5_SHIFT                                                           23
+#define NWM_REG_INT_STS_WR_K2_E5                                                                             0x80000cUL //Access:WR   DataWidth:0x18   // Multi Field Register.
+  #define NWM_REG_INT_STS_WR_ADDRESS_ERROR_K2_E5                                                             (0x1<<0) // Signals an unknown address to the rf module.
+  #define NWM_REG_INT_STS_WR_ADDRESS_ERROR_K2_E5_SHIFT                                                       0
+  #define NWM_REG_INT_STS_WR_TX_OVERFLOW_0_K2_E5                                                             (0x1<<1) // TX fifo overflow
+  #define NWM_REG_INT_STS_WR_TX_OVERFLOW_0_K2_E5_SHIFT                                                       1
+  #define NWM_REG_INT_STS_WR_TX_UNDERFLOW_0_K2_E5                                                            (0x1<<2) // TX fifo underflow
+  #define NWM_REG_INT_STS_WR_TX_UNDERFLOW_0_K2_E5_SHIFT                                                      2
+  #define NWM_REG_INT_STS_WR_TX_OVERFLOW_1_K2_E5                                                             (0x1<<3) // TX fifo overflow
+  #define NWM_REG_INT_STS_WR_TX_OVERFLOW_1_K2_E5_SHIFT                                                       3
+  #define NWM_REG_INT_STS_WR_TX_UNDERFLOW_1_K2_E5                                                            (0x1<<4) // TX fifo underflow
+  #define NWM_REG_INT_STS_WR_TX_UNDERFLOW_1_K2_E5_SHIFT                                                      4
+  #define NWM_REG_INT_STS_WR_TX_OVERFLOW_2_K2_E5                                                             (0x1<<5) // TX fifo overflow
+  #define NWM_REG_INT_STS_WR_TX_OVERFLOW_2_K2_E5_SHIFT                                                       5
+  #define NWM_REG_INT_STS_WR_TX_UNDERFLOW_2_K2_E5                                                            (0x1<<6) // TX fifo underflow
+  #define NWM_REG_INT_STS_WR_TX_UNDERFLOW_2_K2_E5_SHIFT                                                      6
+  #define NWM_REG_INT_STS_WR_TX_OVERFLOW_3_K2_E5                                                             (0x1<<7) // TX fifo overflow
+  #define NWM_REG_INT_STS_WR_TX_OVERFLOW_3_K2_E5_SHIFT                                                       7
+  #define NWM_REG_INT_STS_WR_TX_UNDERFLOW_3_K2_E5                                                            (0x1<<8) // TX fifo underflow
+  #define NWM_REG_INT_STS_WR_TX_UNDERFLOW_3_K2_E5_SHIFT                                                      8
+  #define NWM_REG_INT_STS_WR_LN0_AT_10M_K2_E5                                                                (0x1<<16) // Lane 0 Resolved to 10Mb rate
+  #define NWM_REG_INT_STS_WR_LN0_AT_10M_K2_E5_SHIFT                                                          16
+  #define NWM_REG_INT_STS_WR_LN0_AT_100M_K2_E5                                                               (0x1<<17) // Lane 0 Resolved to 100Mb rate
+  #define NWM_REG_INT_STS_WR_LN0_AT_100M_K2_E5_SHIFT                                                         17
+  #define NWM_REG_INT_STS_WR_LN1_AT_10M_K2_E5                                                                (0x1<<18) // Lane 1 Resolved to 10Mb rate
+  #define NWM_REG_INT_STS_WR_LN1_AT_10M_K2_E5_SHIFT                                                          18
+  #define NWM_REG_INT_STS_WR_LN1_AT_100M_K2_E5                                                               (0x1<<19) // Lane 1 Resolved to 100Mb rate
+  #define NWM_REG_INT_STS_WR_LN1_AT_100M_K2_E5_SHIFT                                                         19
+  #define NWM_REG_INT_STS_WR_LN2_AT_10M_K2_E5                                                                (0x1<<20) // Lane 2 Resolved to 10Mb rate
+  #define NWM_REG_INT_STS_WR_LN2_AT_10M_K2_E5_SHIFT                                                          20
+  #define NWM_REG_INT_STS_WR_LN2_AT_100M_K2_E5                                                               (0x1<<21) // Lane 2 Resolved to 100Mb rate
+  #define NWM_REG_INT_STS_WR_LN2_AT_100M_K2_E5_SHIFT                                                         21
+  #define NWM_REG_INT_STS_WR_LN3_AT_10M_K2_E5                                                                (0x1<<22) // Lane 3 Resolved to 10Mb rate
+  #define NWM_REG_INT_STS_WR_LN3_AT_10M_K2_E5_SHIFT                                                          22
+  #define NWM_REG_INT_STS_WR_LN3_AT_100M_K2_E5                                                               (0x1<<23) // Lane 3 Resolved to 100Mb rate
+  #define NWM_REG_INT_STS_WR_LN3_AT_100M_K2_E5_SHIFT                                                         23
+#define NWM_REG_INT_STS_CLR_K2_E5                                                                            0x800010UL //Access:RC   DataWidth:0x18   // Multi Field Register.
+  #define NWM_REG_INT_STS_CLR_ADDRESS_ERROR_K2_E5                                                            (0x1<<0) // Signals an unknown address to the rf module.
+  #define NWM_REG_INT_STS_CLR_ADDRESS_ERROR_K2_E5_SHIFT                                                      0
+  #define NWM_REG_INT_STS_CLR_TX_OVERFLOW_0_K2_E5                                                            (0x1<<1) // TX fifo overflow
+  #define NWM_REG_INT_STS_CLR_TX_OVERFLOW_0_K2_E5_SHIFT                                                      1
+  #define NWM_REG_INT_STS_CLR_TX_UNDERFLOW_0_K2_E5                                                           (0x1<<2) // TX fifo underflow
+  #define NWM_REG_INT_STS_CLR_TX_UNDERFLOW_0_K2_E5_SHIFT                                                     2
+  #define NWM_REG_INT_STS_CLR_TX_OVERFLOW_1_K2_E5                                                            (0x1<<3) // TX fifo overflow
+  #define NWM_REG_INT_STS_CLR_TX_OVERFLOW_1_K2_E5_SHIFT                                                      3
+  #define NWM_REG_INT_STS_CLR_TX_UNDERFLOW_1_K2_E5                                                           (0x1<<4) // TX fifo underflow
+  #define NWM_REG_INT_STS_CLR_TX_UNDERFLOW_1_K2_E5_SHIFT                                                     4
+  #define NWM_REG_INT_STS_CLR_TX_OVERFLOW_2_K2_E5                                                            (0x1<<5) // TX fifo overflow
+  #define NWM_REG_INT_STS_CLR_TX_OVERFLOW_2_K2_E5_SHIFT                                                      5
+  #define NWM_REG_INT_STS_CLR_TX_UNDERFLOW_2_K2_E5                                                           (0x1<<6) // TX fifo underflow
+  #define NWM_REG_INT_STS_CLR_TX_UNDERFLOW_2_K2_E5_SHIFT                                                     6
+  #define NWM_REG_INT_STS_CLR_TX_OVERFLOW_3_K2_E5                                                            (0x1<<7) // TX fifo overflow
+  #define NWM_REG_INT_STS_CLR_TX_OVERFLOW_3_K2_E5_SHIFT                                                      7
+  #define NWM_REG_INT_STS_CLR_TX_UNDERFLOW_3_K2_E5                                                           (0x1<<8) // TX fifo underflow
+  #define NWM_REG_INT_STS_CLR_TX_UNDERFLOW_3_K2_E5_SHIFT                                                     8
+  #define NWM_REG_INT_STS_CLR_LN0_AT_10M_K2_E5                                                               (0x1<<16) // Lane 0 Resolved to 10Mb rate
+  #define NWM_REG_INT_STS_CLR_LN0_AT_10M_K2_E5_SHIFT                                                         16
+  #define NWM_REG_INT_STS_CLR_LN0_AT_100M_K2_E5                                                              (0x1<<17) // Lane 0 Resolved to 100Mb rate
+  #define NWM_REG_INT_STS_CLR_LN0_AT_100M_K2_E5_SHIFT                                                        17
+  #define NWM_REG_INT_STS_CLR_LN1_AT_10M_K2_E5                                                               (0x1<<18) // Lane 1 Resolved to 10Mb rate
+  #define NWM_REG_INT_STS_CLR_LN1_AT_10M_K2_E5_SHIFT                                                         18
+  #define NWM_REG_INT_STS_CLR_LN1_AT_100M_K2_E5                                                              (0x1<<19) // Lane 1 Resolved to 100Mb rate
+  #define NWM_REG_INT_STS_CLR_LN1_AT_100M_K2_E5_SHIFT                                                        19
+  #define NWM_REG_INT_STS_CLR_LN2_AT_10M_K2_E5                                                               (0x1<<20) // Lane 2 Resolved to 10Mb rate
+  #define NWM_REG_INT_STS_CLR_LN2_AT_10M_K2_E5_SHIFT                                                         20
+  #define NWM_REG_INT_STS_CLR_LN2_AT_100M_K2_E5                                                              (0x1<<21) // Lane 2 Resolved to 100Mb rate
+  #define NWM_REG_INT_STS_CLR_LN2_AT_100M_K2_E5_SHIFT                                                        21
+  #define NWM_REG_INT_STS_CLR_LN3_AT_10M_K2_E5                                                               (0x1<<22) // Lane 3 Resolved to 10Mb rate
+  #define NWM_REG_INT_STS_CLR_LN3_AT_10M_K2_E5_SHIFT                                                         22
+  #define NWM_REG_INT_STS_CLR_LN3_AT_100M_K2_E5                                                              (0x1<<23) // Lane 3 Resolved to 100Mb rate
+  #define NWM_REG_INT_STS_CLR_LN3_AT_100M_K2_E5_SHIFT                                                        23
+#define NWM_REG_MAC0_PEER_DELAY_K2_E5                                                                        0x800014UL //Access:RW   DataWidth:0x1e   // A so-called Peer Delay value that can be added to the correction field for all 1-step updates Refer to the MAC reference guide 1-step description on usage. Reset = 0
+#define NWM_REG_MAC1_PEER_DELAY_K2_E5                                                                        0x800018UL //Access:RW   DataWidth:0x1e   // A so-called Peer Delay value that can be added to the correction field for all 1-step updates Refer to the MAC reference guide 1-step description on usage. Reset = 0
+#define NWM_REG_MAC2_PEER_DELAY_K2_E5                                                                        0x80001cUL //Access:RW   DataWidth:0x1e   // A so-called Peer Delay value that can be added to the correction field for all 1-step updates Refer to the MAC reference guide 1-step description on usage. Reset = 0
+#define NWM_REG_MAC3_PEER_DELAY_K2_E5                                                                        0x800020UL //Access:RW   DataWidth:0x1e   // A so-called Peer Delay value that can be added to the correction field for all 1-step updates Refer to the MAC reference guide 1-step description on usage. Reset = 0
+#define NWM_REG_FEC_74_LOCKED_STATUS_K2_E5                                                                   0x800024UL //Access:R    DataWidth:0x8    // Per virtual lane indication that FEC has acheived lock on the FEC boundaries and valid data is being decoded.
+#define NWM_REG_LN0_LATCHED_STATUS_K2_E5                                                                     0x800028UL //Access:RC   DataWidth:0xa    // The following bits a latched high.  All bits are cleared when the register is read. bit 9 - LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - REMOTE_FAULT_LH Remote_fault indicator has transitioned from Low to High since last read. bit 7 - LINK_INTERRUPT_LH Link Interrupt Received indicator has transitioned from Low to High since last read. bit 6 - LPI_RECEIVED_LH LPI Received indicator has transitioned from Low to High since last read. bit 5 - HI_BER_LH HI BER indicator has transitioned from Low to High since last read. bit 4 - HI_BER_LL HI BER indicator has transitioned from High to Low since last read.(Note supported,always reads 0 CQ85103) bit 3 - LINK_STATUS_LH Link Status indicator has transitioned from Low to High since last read. bit 2 - LINK_STATUS_LL Link Status indicator has transitioned from High to Low since last read. bit 1 - BLOCK_LOCK_LH Link Status indicator has transitioned from Low to High since last read. bit 0 - BLOCK_LOCK_LL Link Status indicator has transitioned from High to Low since last read.
+#define NWM_REG_LN0_LIVE_STS_K2_E5                                                                           0x80002cUL //Access:R    DataWidth:0x7    // Multi Field Register.
+  #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_LOCAL_FAULT_K2_E5                                                    (0x1<<6) // Live Local Fault Indicator
+  #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_LOCAL_FAULT_K2_E5_SHIFT                                              6
+  #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_REMOTE_FAULT_K2_E5                                                   (0x1<<7) // Live Remote Fault Indicator
+  #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_REMOTE_FAULT_K2_E5_SHIFT                                             7
+  #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_LINK_INTERRUPT_K2_E5                                                 (0x1<<8) // Live Link Interrupt Indicator
+  #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_LINK_INTERRUPT_K2_E5_SHIFT                                           8
+  #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_LPI_RECEIVED_K2_E5                                                   (0x1<<9) // Live LPI Received Indicator
+  #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_LPI_RECEIVED_K2_E5_SHIFT                                             9
+  #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_HI_BER_K2_E5                                                         (0x1<<10) // Live Hi BER Indicator
+  #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_HI_BER_K2_E5_SHIFT                                                   10
+  #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_LINK_STATUS_K2_E5                                                    (0x1<<11) // Live Link Status Indicator
+  #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_LINK_STATUS_K2_E5_SHIFT                                              11
+  #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_BLOCK_LOCK_K2_E5                                                     (0x1<<12) // Live block lock Indicator
+  #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_BLOCK_LOCK_K2_E5_SHIFT                                               12
+#define NWM_REG_LN1_LATCHED_STATUS_K2_E5                                                                     0x800030UL //Access:RC   DataWidth:0xa    // The following bits a latched high.  All bits are cleared when the register is read. bit 9 - LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - REMOTE_FAULT_LH Remote_fault indicator has transitioned from Low to High since last read. bit 7 - LINK_INTERRUPT_LH Link Interrupt Received indicator has transitioned from Low to High since last read. bit 6 - LPI_RECEIVED_LH LPI Received indicator has transitioned from Low to High since last read. bit 5 - HI_BER_LH HI BER indicator has transitioned from Low to High since last read. bit 4 - HI_BER_LL HI BER indicator has transitioned from High to Low since last read.(Note supported,always reads 0 CQ85103) bit 3 - LINK_STATUS_LH Link Status indicator has transitioned from Low to High since last read. bit 2 - LINK_STATUS_LL Link Status indicator has transitioned from High to Low since last read. bit 1 - BLOCK_LOCK_LH Link Status indicator has transitioned from Low to High since last read. bit 0 - BLOCK_LOCK_LL Link Status indicator has transitioned from High to Low since last read.
+#define NWM_REG_LN1_LIVE_STS_K2_E5                                                                           0x800034UL //Access:R    DataWidth:0x7    // Multi Field Register.
+  #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_LOCAL_FAULT_K2_E5                                                    (0x1<<6) // Live Local Fault Indicator
+  #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_LOCAL_FAULT_K2_E5_SHIFT                                              6
+  #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_REMOTE_FAULT_K2_E5                                                   (0x1<<7) // Live Remote Fault Indicator
+  #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_REMOTE_FAULT_K2_E5_SHIFT                                             7
+  #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_LINK_INTERRUPT_K2_E5                                                 (0x1<<8) // Live Link Interrupt Indicator
+  #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_LINK_INTERRUPT_K2_E5_SHIFT                                           8
+  #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_LPI_RECEIVED_K2_E5                                                   (0x1<<9) // Live LPI Received Indicator
+  #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_LPI_RECEIVED_K2_E5_SHIFT                                             9
+  #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_HI_BER_K2_E5                                                         (0x1<<10) // Live Hi BER Indicator
+  #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_HI_BER_K2_E5_SHIFT                                                   10
+  #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_LINK_STATUS_K2_E5                                                    (0x1<<11) // Live Link Status Indicator
+  #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_LINK_STATUS_K2_E5_SHIFT                                              11
+  #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_BLOCK_LOCK_K2_E5                                                     (0x1<<12) // Live block lock Indicator
+  #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_BLOCK_LOCK_K2_E5_SHIFT                                               12
+#define NWM_REG_LN2_LATCHED_STATUS_K2_E5                                                                     0x800038UL //Access:RC   DataWidth:0xa    // The following bits a latched high.  All bits are cleared when the register is read. bit 9 - LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - REMOTE_FAULT_LH Remote_fault indicator has transitioned from Low to High since last read. bit 7 - LINK_INTERRUPT_LH Link Interrupt Received indicator has transitioned from Low to High since last read. bit 6 - LPI_RECEIVED_LH LPI Received indicator has transitioned from Low to High since last read. bit 5 - HI_BER_LH HI BER indicator has transitioned from Low to High since last read. bit 4 - HI_BER_LL HI BER indicator has transitioned from High to Low since last read.(Note supported,always reads 0 CQ85103) bit 3 - LINK_STATUS_LH Link Status indicator has transitioned from Low to High since last read. bit 2 - LINK_STATUS_LL Link Status indicator has transitioned from High to Low since last read. bit 1 - BLOCK_LOCK_LH Link Status indicator has transitioned from Low to High since last read. bit 0 - BLOCK_LOCK_LL Link Status indicator has transitioned from High to Low since last read.
+#define NWM_REG_LN2_LIVE_STS_K2_E5                                                                           0x80003cUL //Access:R    DataWidth:0x7    // Multi Field Register.
+  #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_LOCAL_FAULT_K2_E5                                                    (0x1<<6) // Live Local Fault Indicator
+  #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_LOCAL_FAULT_K2_E5_SHIFT                                              6
+  #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_REMOTE_FAULT_K2_E5                                                   (0x1<<7) // Live Remote Fault Indicator
+  #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_REMOTE_FAULT_K2_E5_SHIFT                                             7
+  #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_LINK_INTERRUPT_K2_E5                                                 (0x1<<8) // Live Link Interrupt Indicator
+  #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_LINK_INTERRUPT_K2_E5_SHIFT                                           8
+  #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_LPI_RECEIVED_K2_E5                                                   (0x1<<9) // Live LPI Received Indicator
+  #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_LPI_RECEIVED_K2_E5_SHIFT                                             9
+  #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_HI_BER_K2_E5                                                         (0x1<<10) // Live Hi BER Indicator
+  #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_HI_BER_K2_E5_SHIFT                                                   10
+  #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_LINK_STATUS_K2_E5                                                    (0x1<<11) // Live Link Status Indicator
+  #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_LINK_STATUS_K2_E5_SHIFT                                              11
+  #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_BLOCK_LOCK_K2_E5                                                     (0x1<<12) // Live block lock Indicator
+  #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_BLOCK_LOCK_K2_E5_SHIFT                                               12
+#define NWM_REG_LN3_LATCHED_STATUS_K2_E5                                                                     0x800040UL //Access:RC   DataWidth:0xa    // The following bits a latched high.  All bits are cleared when the register is read. bit 9 - LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - REMOTE_FAULT_LH Remote_fault indicator has transitioned from Low to High since last read. bit 7 - LINK_INTERRUPT_LH Link Interrupt Received indicator has transitioned from Low to High since last read. bit 6 - LPI_RECEIVED_LH LPI Received indicator has transitioned from Low to High since last read. bit 5 - HI_BER_LH HI BER indicator has transitioned from Low to High since last read. bit 4 - HI_BER_LL HI BER indicator has transitioned from High to Low since last read.(Note supported,always reads 0 CQ85103) bit 3 - LINK_STATUS_LH Link Status indicator has transitioned from Low to High since last read. bit 2 - LINK_STATUS_LL Link Status indicator has transitioned from High to Low since last read. bit 1 - BLOCK_LOCK_LH Link Status indicator has transitioned from Low to High since last read. bit 0 - BLOCK_LOCK_LL Link Status indicator has transitioned from High to Low since last read.
+#define NWM_REG_LN3_LIVE_STS_K2_E5                                                                           0x800044UL //Access:R    DataWidth:0x7    // Multi Field Register.
+  #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_LOCAL_FAULT_K2_E5                                                    (0x1<<6) // Live Local Fault Indicator
+  #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_LOCAL_FAULT_K2_E5_SHIFT                                              6
+  #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_REMOTE_FAULT_K2_E5                                                   (0x1<<7) // Live Remote Fault Indicator
+  #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_REMOTE_FAULT_K2_E5_SHIFT                                             7
+  #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_LINK_INTERRUPT_K2_E5                                                 (0x1<<8) // Live Link Interrupt Indicator
+  #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_LINK_INTERRUPT_K2_E5_SHIFT                                           8
+  #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_LPI_RECEIVED_K2_E5                                                   (0x1<<9) // Live LPI Received Indicator
+  #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_LPI_RECEIVED_K2_E5_SHIFT                                             9
+  #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_HI_BER_K2_E5                                                         (0x1<<10) // Live Hi BER Indicator
+  #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_HI_BER_K2_E5_SHIFT                                                   10
+  #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_LINK_STATUS_K2_E5                                                    (0x1<<11) // Live Link Status Indicator
+  #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_LINK_STATUS_K2_E5_SHIFT                                              11
+  #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_BLOCK_LOCK_K2_E5                                                     (0x1<<12) // Live block lock Indicator
+  #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_BLOCK_LOCK_K2_E5_SHIFT                                               12
+#define NWM_REG_PCS_SELECT_K2_E5                                                                             0x800048UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define NWM_REG_PCS_SELECT_SG0_ENA_K2_E5                                                                   (0x1<<0) // SGMII PCS Enable.  When set to 1, the SGMII PCS is enabled.  When set to 0, the 10/25/40/50Geth PCS is enabled.
+  #define NWM_REG_PCS_SELECT_SG0_ENA_K2_E5_SHIFT                                                             0
+  #define NWM_REG_PCS_SELECT_SG1_ENA_K2_E5                                                                   (0x1<<1) // SGMII PCS Enable.  When set to 1, the SGMII PCS is enabled.  When set to 0, the 10/25/50Geth PCS is enabled.
+  #define NWM_REG_PCS_SELECT_SG1_ENA_K2_E5_SHIFT                                                             1
+  #define NWM_REG_PCS_SELECT_SG2_ENA_K2_E5                                                                   (0x1<<2) // SGMII PCS Enable.  When set to 1, the SGMII PCS is enabled.  When set to 0, the 10/25Geth PCS is enabled.
+  #define NWM_REG_PCS_SELECT_SG2_ENA_K2_E5_SHIFT                                                             2
+  #define NWM_REG_PCS_SELECT_SG3_ENA_K2_E5                                                                   (0x1<<3) // SGMII PCS Enable.  When set to 1, the SGMII PCS is enabled.  When set to 0, the 10/25Geth PCS is enabled.
+  #define NWM_REG_PCS_SELECT_SG3_ENA_K2_E5_SHIFT                                                             3
+#define NWM_REG_SGMII_PCS_STATUS_K2_E5                                                                       0x80004cUL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define NWM_REG_SGMII_PCS_STATUS_SG0_RX_SYNC_K2_E5                                                         (0x1<<0) // Set to '1' to indicate successul link synchronization.
+  #define NWM_REG_SGMII_PCS_STATUS_SG0_RX_SYNC_K2_E5_SHIFT                                                   0
+  #define NWM_REG_SGMII_PCS_STATUS_SG0_AN_DONE_K2_E5                                                         (0x1<<1) // Auto-Negotiation status. Set to '1' when the Auto-Negotiation is complete.
+  #define NWM_REG_SGMII_PCS_STATUS_SG0_AN_DONE_K2_E5_SHIFT                                                   1
+  #define NWM_REG_SGMII_PCS_STATUS_SG1_RX_SYNC_K2_E5                                                         (0x1<<2) // Set to '1' to indicate successul link synchronization.
+  #define NWM_REG_SGMII_PCS_STATUS_SG1_RX_SYNC_K2_E5_SHIFT                                                   2
+  #define NWM_REG_SGMII_PCS_STATUS_SG1_AN_DONE_K2_E5                                                         (0x1<<3) // Auto-Negotiation status. Set to '1' when the Auto-Negotiation is complete.
+  #define NWM_REG_SGMII_PCS_STATUS_SG1_AN_DONE_K2_E5_SHIFT                                                   3
+  #define NWM_REG_SGMII_PCS_STATUS_SG2_RX_SYNC_K2_E5                                                         (0x1<<4) // Set to '1' to indicate successul link synchronization.
+  #define NWM_REG_SGMII_PCS_STATUS_SG2_RX_SYNC_K2_E5_SHIFT                                                   4
+  #define NWM_REG_SGMII_PCS_STATUS_SG2_AN_DONE_K2_E5                                                         (0x1<<5) // Auto-Negotiation status. Set to '1' when the Auto-Negotiation is complete.
+  #define NWM_REG_SGMII_PCS_STATUS_SG2_AN_DONE_K2_E5_SHIFT                                                   5
+  #define NWM_REG_SGMII_PCS_STATUS_SG3_RX_SYNC_K2_E5                                                         (0x1<<6) // Set to '1' to indicate successul link synchronization.
+  #define NWM_REG_SGMII_PCS_STATUS_SG3_RX_SYNC_K2_E5_SHIFT                                                   6
+  #define NWM_REG_SGMII_PCS_STATUS_SG3_AN_DONE_K2_E5                                                         (0x1<<7) // Auto-Negotiation status. Set to '1' when the Auto-Negotiation is complete.
+  #define NWM_REG_SGMII_PCS_STATUS_SG3_AN_DONE_K2_E5_SHIFT                                                   7
+#define NWM_REG_FC_FEC_CONTROL_SIGNALS_K2_E5                                                                 0x800050UL //Access:RW   DataWidth:0xc    // Multi Field Register.
+  #define NWM_REG_FC_FEC_CONTROL_SIGNALS_FEC_ENA_TX_K2_E5                                                    (0xf<<0) // Set to '1' for a given lane to enable FEC74.
+  #define NWM_REG_FC_FEC_CONTROL_SIGNALS_FEC_ENA_TX_K2_E5_SHIFT                                              0
+  #define NWM_REG_FC_FEC_CONTROL_SIGNALS_FEC_ENA_RX_K2_E5                                                    (0xf<<4) // Set to '1' for a given lane to enable FEC74.
+  #define NWM_REG_FC_FEC_CONTROL_SIGNALS_FEC_ENA_RX_K2_E5_SHIFT                                              4
+  #define NWM_REG_FC_FEC_CONTROL_SIGNALS_FEC_ERR_ENA_K2_E5                                                   (0xf<<8) // Set to '1' for a given lane to enable FEC74 forward indication of uncorrectable errors to the PCS layer by corrupting sync headers. Per lane.
+  #define NWM_REG_FC_FEC_CONTROL_SIGNALS_FEC_ERR_ENA_K2_E5_SHIFT                                             8
+#define NWM_REG_SERDES_CROSSBAR_CONTROLS_K2_E5                                                               0x800054UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define NWM_REG_SERDES_CROSSBAR_CONTROLS_SD0_SEL_K2_E5                                                     (0x3<<0) // Defines for each physical serdes lane separately, to which PCS lane it should connect
+  #define NWM_REG_SERDES_CROSSBAR_CONTROLS_SD0_SEL_K2_E5_SHIFT                                               0
+  #define NWM_REG_SERDES_CROSSBAR_CONTROLS_SD1_SEL_K2_E5                                                     (0x3<<2) // Defines for each physical serdes lane separately, to which PCS lane it should connect
+  #define NWM_REG_SERDES_CROSSBAR_CONTROLS_SD1_SEL_K2_E5_SHIFT                                               2
+  #define NWM_REG_SERDES_CROSSBAR_CONTROLS_SD2_SEL_K2_E5                                                     (0x3<<4) // Defines for each physical serdes lane separately, to which PCS lane it should connect
+  #define NWM_REG_SERDES_CROSSBAR_CONTROLS_SD2_SEL_K2_E5_SHIFT                                               4
+  #define NWM_REG_SERDES_CROSSBAR_CONTROLS_SD3_SEL_K2_E5                                                     (0x3<<6) // Defines for each physical serdes lane separately, to which PCS lane it should connect
+  #define NWM_REG_SERDES_CROSSBAR_CONTROLS_SD3_SEL_K2_E5_SHIFT                                               6
+#define NWM_REG_XPCS_LPI_FAST_WAKE_CONTROL_K2_E5                                                             0x800058UL //Access:RW   DataWidth:0x1    // Controls the fast-wake mode for the LPI transmit and receive functions. When set to 1, the link is to use fast wake mechanisim. When set to 0, the link is to use the optional deep sleep mechanism for each direction. Should default to 1 and may only be cleared if the optional deep sleep mode is supported.
+#define NWM_REG_PORT0_XPCS_EEE_STATUS_K2_E5                                                                  0x80005cUL //Access:R    DataWidth:0xa    // Multi Field Register.
+  #define NWM_REG_PORT0_XPCS_EEE_STATUS_XPCS0_TX_LPI_MODE_K2_E5                                              (0x3<<0) // A variable reflecting the state of the LPI transmit function.
+  #define NWM_REG_PORT0_XPCS_EEE_STATUS_XPCS0_TX_LPI_MODE_K2_E5_SHIFT                                        0
+  #define NWM_REG_PORT0_XPCS_EEE_STATUS_XPCS0_TX_LPI_STATE_K2_E5                                             (0x7<<2) // A variable reflecting the state of the LPI Transmit State Machine.
+  #define NWM_REG_PORT0_XPCS_EEE_STATUS_XPCS0_TX_LPI_STATE_K2_E5_SHIFT                                       2
+  #define NWM_REG_PORT0_XPCS_EEE_STATUS_XPCS0_RX_LPI_MODE_K2_E5                                              (0x1<<5) // A variable reflecting the state of the LPI receive function.
+  #define NWM_REG_PORT0_XPCS_EEE_STATUS_XPCS0_RX_LPI_MODE_K2_E5_SHIFT                                        5
+  #define NWM_REG_PORT0_XPCS_EEE_STATUS_XPCS0_RX_LPI_STATE_K2_E5                                             (0x7<<6) // A variable reflecting the state of the LPI Receive State Machine.
+  #define NWM_REG_PORT0_XPCS_EEE_STATUS_XPCS0_RX_LPI_STATE_K2_E5_SHIFT                                       6
+  #define NWM_REG_PORT0_XPCS_EEE_STATUS_XPCS0_RX_LPI_ACTIVE_K2_E5                                            (0x1<<9) // A boolean value that is set true (1) when the receive is in a low power state and set to false (0) when it is in an active state and capable of receiving data.
+  #define NWM_REG_PORT0_XPCS_EEE_STATUS_XPCS0_RX_LPI_ACTIVE_K2_E5_SHIFT                                      9
+#define NWM_REG_PORT1_XPCS_EEE_STATUS_K2_E5                                                                  0x800060UL //Access:R    DataWidth:0xa    // Multi Field Register.
+  #define NWM_REG_PORT1_XPCS_EEE_STATUS_XPCS1_TX_LPI_MODE_K2_E5                                              (0x3<<0) // A variable reflecting the state of the LPI transmit function.
+  #define NWM_REG_PORT1_XPCS_EEE_STATUS_XPCS1_TX_LPI_MODE_K2_E5_SHIFT                                        0
+  #define NWM_REG_PORT1_XPCS_EEE_STATUS_XPCS1_TX_LPI_STATE_K2_E5                                             (0x7<<2) // A variable reflecting the state of the LPI Transmit State Machine.
+  #define NWM_REG_PORT1_XPCS_EEE_STATUS_XPCS1_TX_LPI_STATE_K2_E5_SHIFT                                       2
+  #define NWM_REG_PORT1_XPCS_EEE_STATUS_XPCS1_RX_LPI_MODE_K2_E5                                              (0x1<<5) // A variable reflecting the state of the LPI receive function.
+  #define NWM_REG_PORT1_XPCS_EEE_STATUS_XPCS1_RX_LPI_MODE_K2_E5_SHIFT                                        5
+  #define NWM_REG_PORT1_XPCS_EEE_STATUS_XPCS1_RX_LPI_STATE_K2_E5                                             (0x7<<6) // A variable reflecting the state of the LPI Receive State Machine.
+  #define NWM_REG_PORT1_XPCS_EEE_STATUS_XPCS1_RX_LPI_STATE_K2_E5_SHIFT                                       6
+  #define NWM_REG_PORT1_XPCS_EEE_STATUS_XPCS1_RX_LPI_ACTIVE_K2_E5                                            (0x1<<9) // A boolean value that is set true (1) when the receive is in a low power state and set to false (0) when it is in an active state and capable of receiving data.
+  #define NWM_REG_PORT1_XPCS_EEE_STATUS_XPCS1_RX_LPI_ACTIVE_K2_E5_SHIFT                                      9
+#define NWM_REG_PORT2_XPCS_EEE_STATUS_K2_E5                                                                  0x800064UL //Access:R    DataWidth:0xa    // Multi Field Register.
+  #define NWM_REG_PORT2_XPCS_EEE_STATUS_XPCS2_TX_LPI_MODE_K2_E5                                              (0x3<<0) // A variable reflecting the state of the LPI transmit function.
+  #define NWM_REG_PORT2_XPCS_EEE_STATUS_XPCS2_TX_LPI_MODE_K2_E5_SHIFT                                        0
+  #define NWM_REG_PORT2_XPCS_EEE_STATUS_XPCS2_TX_LPI_STATE_K2_E5                                             (0x7<<2) // A variable reflecting the state of the LPI Transmit State Machine.
+  #define NWM_REG_PORT2_XPCS_EEE_STATUS_XPCS2_TX_LPI_STATE_K2_E5_SHIFT                                       2
+  #define NWM_REG_PORT2_XPCS_EEE_STATUS_XPCS2_RX_LPI_MODE_K2_E5                                              (0x1<<5) // A variable reflecting the state of the LPI receive function.
+  #define NWM_REG_PORT2_XPCS_EEE_STATUS_XPCS2_RX_LPI_MODE_K2_E5_SHIFT                                        5
+  #define NWM_REG_PORT2_XPCS_EEE_STATUS_XPCS2_RX_LPI_STATE_K2_E5                                             (0x7<<6) // A variable reflecting the state of the LPI Receive State Machine.
+  #define NWM_REG_PORT2_XPCS_EEE_STATUS_XPCS2_RX_LPI_STATE_K2_E5_SHIFT                                       6
+  #define NWM_REG_PORT2_XPCS_EEE_STATUS_XPCS2_RX_LPI_ACTIVE_K2_E5                                            (0x1<<9) // A boolean value that is set true (1) when the receive is in a low power state and set to false (0) when it is in an active state and capable of receiving data.
+  #define NWM_REG_PORT2_XPCS_EEE_STATUS_XPCS2_RX_LPI_ACTIVE_K2_E5_SHIFT                                      9
+#define NWM_REG_PORT3_XPCS_EEE_STATUS_K2_E5                                                                  0x800068UL //Access:R    DataWidth:0xa    // Multi Field Register.
+  #define NWM_REG_PORT3_XPCS_EEE_STATUS_XPCS3_TX_LPI_MODE_K2_E5                                              (0x3<<0) // A variable reflecting the state of the LPI transmit function.
+  #define NWM_REG_PORT3_XPCS_EEE_STATUS_XPCS3_TX_LPI_MODE_K2_E5_SHIFT                                        0
+  #define NWM_REG_PORT3_XPCS_EEE_STATUS_XPCS3_TX_LPI_STATE_K2_E5                                             (0x7<<2) // A variable reflecting the state of the LPI Transmit State Machine.
+  #define NWM_REG_PORT3_XPCS_EEE_STATUS_XPCS3_TX_LPI_STATE_K2_E5_SHIFT                                       2
+  #define NWM_REG_PORT3_XPCS_EEE_STATUS_XPCS3_RX_LPI_MODE_K2_E5                                              (0x1<<5) // A variable reflecting the state of the LPI receive function.
+  #define NWM_REG_PORT3_XPCS_EEE_STATUS_XPCS3_RX_LPI_MODE_K2_E5_SHIFT                                        5
+  #define NWM_REG_PORT3_XPCS_EEE_STATUS_XPCS3_RX_LPI_STATE_K2_E5                                             (0x7<<6) // A variable reflecting the state of the LPI Receive State Machine.
+  #define NWM_REG_PORT3_XPCS_EEE_STATUS_XPCS3_RX_LPI_STATE_K2_E5_SHIFT                                       6
+  #define NWM_REG_PORT3_XPCS_EEE_STATUS_XPCS3_RX_LPI_ACTIVE_K2_E5                                            (0x1<<9) // A boolean value that is set true (1) when the receive is in a low power state and set to false (0) when it is in an active state and capable of receiving data.
+  #define NWM_REG_PORT3_XPCS_EEE_STATUS_XPCS3_RX_LPI_ACTIVE_K2_E5_SHIFT                                      9
+#define NWM_REG_PORT0_SG_EEE_STATUS_K2_E5                                                                    0x80006cUL //Access:R    DataWidth:0x4    // Multi Field Register.
+  #define NWM_REG_PORT0_SG_EEE_STATUS_SG0_TX_LPI_ACTIVE_K2_E5                                                (0x1<<0) // PCS Indication to the application that the transmitter is performing a low power cycle.
+  #define NWM_REG_PORT0_SG_EEE_STATUS_SG0_TX_LPI_ACTIVE_K2_E5_SHIFT                                          0
+  #define NWM_REG_PORT0_SG_EEE_STATUS_SG0_PMA_TXMODE_QUIET_K2_E5                                             (0x1<<1) // Indicates (when 1) that the transmitter has reached the quiet state.
+  #define NWM_REG_PORT0_SG_EEE_STATUS_SG0_PMA_TXMODE_QUIET_K2_E5_SHIFT                                       1
+  #define NWM_REG_PORT0_SG_EEE_STATUS_SG0_RX_LPI_ACTIVE_K2_E5                                                (0x1<<2) // Indicates (when 1) that the PCS receiver is performing a low power cycle.
+  #define NWM_REG_PORT0_SG_EEE_STATUS_SG0_RX_LPI_ACTIVE_K2_E5_SHIFT                                          2
+  #define NWM_REG_PORT0_SG_EEE_STATUS_SG0_PMA_RXMODE_QUIET_K2_E5                                             (0x1<<3) // Indication that the remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
+  #define NWM_REG_PORT0_SG_EEE_STATUS_SG0_PMA_RXMODE_QUIET_K2_E5_SHIFT                                       3
+#define NWM_REG_PORT1_SG_EEE_STATUS_K2_E5                                                                    0x800070UL //Access:R    DataWidth:0x4    // Multi Field Register.
+  #define NWM_REG_PORT1_SG_EEE_STATUS_SG1_TX_LPI_ACTIVE_K2_E5                                                (0x1<<0) // PCS Indication to the application that the transmitter is performing a low power cycle.
+  #define NWM_REG_PORT1_SG_EEE_STATUS_SG1_TX_LPI_ACTIVE_K2_E5_SHIFT                                          0
+  #define NWM_REG_PORT1_SG_EEE_STATUS_SG1_PMA_TXMODE_QUIET_K2_E5                                             (0x1<<1) // Indicates (when 1) that the transmitter has reached the quiet state.
+  #define NWM_REG_PORT1_SG_EEE_STATUS_SG1_PMA_TXMODE_QUIET_K2_E5_SHIFT                                       1
+  #define NWM_REG_PORT1_SG_EEE_STATUS_SG1_RX_LPI_ACTIVE_K2_E5                                                (0x1<<2) // Indicates (when 1) that the PCS receiver is performing a low power cycle.
+  #define NWM_REG_PORT1_SG_EEE_STATUS_SG1_RX_LPI_ACTIVE_K2_E5_SHIFT                                          2
+  #define NWM_REG_PORT1_SG_EEE_STATUS_SG1_PMA_RXMODE_QUIET_K2_E5                                             (0x1<<3) // Indication that the remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
+  #define NWM_REG_PORT1_SG_EEE_STATUS_SG1_PMA_RXMODE_QUIET_K2_E5_SHIFT                                       3
+#define NWM_REG_PORT2_SG_EEE_STATUS_K2_E5                                                                    0x800074UL //Access:R    DataWidth:0x4    // Multi Field Register.
+  #define NWM_REG_PORT2_SG_EEE_STATUS_SG2_TX_LPI_ACTIVE_K2_E5                                                (0x1<<0) // PCS Indication to the application that the transmitter is performing a low power cycle.
+  #define NWM_REG_PORT2_SG_EEE_STATUS_SG2_TX_LPI_ACTIVE_K2_E5_SHIFT                                          0
+  #define NWM_REG_PORT2_SG_EEE_STATUS_SG2_PMA_TXMODE_QUIET_K2_E5                                             (0x1<<1) // Indicates (when 1) that the transmitter has reached the quiet state.
+  #define NWM_REG_PORT2_SG_EEE_STATUS_SG2_PMA_TXMODE_QUIET_K2_E5_SHIFT                                       1
+  #define NWM_REG_PORT2_SG_EEE_STATUS_SG2_RX_LPI_ACTIVE_K2_E5                                                (0x1<<2) // Indicates (when 1) that the PCS receiver is performing a low power cycle.
+  #define NWM_REG_PORT2_SG_EEE_STATUS_SG2_RX_LPI_ACTIVE_K2_E5_SHIFT                                          2
+  #define NWM_REG_PORT2_SG_EEE_STATUS_SG2_PMA_RXMODE_QUIET_K2_E5                                             (0x1<<3) // Indication that the remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
+  #define NWM_REG_PORT2_SG_EEE_STATUS_SG2_PMA_RXMODE_QUIET_K2_E5_SHIFT                                       3
+#define NWM_REG_PORT3_SG_EEE_STATUS_K2_E5                                                                    0x800078UL //Access:R    DataWidth:0x4    // Multi Field Register.
+  #define NWM_REG_PORT3_SG_EEE_STATUS_SG3_TX_LPI_ACTIVE_K2_E5                                                (0x1<<0) // PCS Indication to the application that the transmitter is performing a low power cycle.
+  #define NWM_REG_PORT3_SG_EEE_STATUS_SG3_TX_LPI_ACTIVE_K2_E5_SHIFT                                          0
+  #define NWM_REG_PORT3_SG_EEE_STATUS_SG3_PMA_TXMODE_QUIET_K2_E5                                             (0x1<<1) // Indicates (when 1) that the transmitter has reached the quiet state.
+  #define NWM_REG_PORT3_SG_EEE_STATUS_SG3_PMA_TXMODE_QUIET_K2_E5_SHIFT                                       1
+  #define NWM_REG_PORT3_SG_EEE_STATUS_SG3_RX_LPI_ACTIVE_K2_E5                                                (0x1<<2) // Indicates (when 1) that the PCS receiver is performing a low power cycle.
+  #define NWM_REG_PORT3_SG_EEE_STATUS_SG3_RX_LPI_ACTIVE_K2_E5_SHIFT                                          2
+  #define NWM_REG_PORT3_SG_EEE_STATUS_SG3_PMA_RXMODE_QUIET_K2_E5                                             (0x1<<3) // Indication that the remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
+  #define NWM_REG_PORT3_SG_EEE_STATUS_SG3_PMA_RXMODE_QUIET_K2_E5_SHIFT                                       3
+#define NWM_REG_PCS_STATUS_K2_E5                                                                             0x80007cUL //Access:R    DataWidth:0x10   // Multi Field Register.
+  #define NWM_REG_PCS_STATUS_ALIGN_DONE_K2_E5                                                                (0xf<<0) // Alignment Marker Lock indication, per PCS. When asserted (1) the alignment marker lock state machines could successfully lock onto detection of alignment markers on all virtual lanes. The signal stays asserted as long as alignment marker lock is maintained.
+  #define NWM_REG_PCS_STATUS_ALIGN_DONE_K2_E5_SHIFT                                                          0
+  #define NWM_REG_PCS_STATUS_BLOCK_LOCK_K2_E5                                                                (0xf<<4) // Combined Block synchronization indication for each PCS (not lane). When asserted (1) the block synchronization state machines could successfully lock onto 66-bit block boundaries on all virtual lanes relevant to the PCS. The signals stay asserted as long as block lock is maintained.
+  #define NWM_REG_PCS_STATUS_BLOCK_LOCK_K2_E5_SHIFT                                                          4
+  #define NWM_REG_PCS_STATUS_HI_BER_K2_E5                                                                    (0xf<<8) // High Bit Error Rate indication for all lanes. Depending on mode, when asserted, at least 97 invalid synchronization headers have been found in a 1.25ms measurement period (40G) or 16 invalid headers within 125ìs (10G), indicating a high bit error rate on the Serdes side. As long as hi_ber stays asserted, local fault is signaled on XLGMII. hi_ber deasserts again, only if less than the acceptable invalid synchronization headers have been detected within the same measurement period. Note: If the short marker distance is configured (See Register VL_INTVL) the measurement period shrinks to 12.5ìs, independent of the mode. Note: the mentioned values are correct only for standard modes, which is 10G and 40G. The measurement window shrinks accordingly when operating in 25G or 50G modes.
+  #define NWM_REG_PCS_STATUS_HI_BER_K2_E5_SHIFT                                                              8
+  #define NWM_REG_PCS_STATUS_LINK_STATUS_K2_E5                                                               (0xf<<12) // Indicates operational status of the link, per PCS. When 1 indicates the link is in its normal operational state. It is the result of an asserted block-lock or align-done status, depending on current mode, and a cleared hi-ber status. The signal stays asserted during EEE quiet states. The signal represents the link status (802.3 variable PCS_Status) usable by Clause 73 backplane auto-negotiation according to 802.3 Clauses 49.2.16 and 82.6. Note: When a channel has its SGMII PCS enabled this link status has no meaning and instead the SGMII PCS' status (sg_rx_sync) is then relevant.
+  #define NWM_REG_PCS_STATUS_LINK_STATUS_K2_E5_SHIFT                                                         12
+#define NWM_REG_RX_FAULT_K2_E5                                                                               0x800080UL //Access:R    DataWidth:0xc    // Multi Field Register.
+  #define NWM_REG_RX_FAULT_RX_LINK_INTERRUPTION_K2_E5                                                        (0xf<<0) // Asserted when the  XLGMII reconciliation layer detects the remote sequences received on the link. One bit per port.
+  #define NWM_REG_RX_FAULT_RX_LINK_INTERRUPTION_K2_E5_SHIFT                                                  0
+  #define NWM_REG_RX_FAULT_RX_LOCAL_FAULT_K2_E5                                                              (0xf<<4) // Asserted when the  XLGMII/XGMII reconciliation layer detects the local fault sequences received on the link. One bit per port.
+  #define NWM_REG_RX_FAULT_RX_LOCAL_FAULT_K2_E5_SHIFT                                                        4
+  #define NWM_REG_RX_FAULT_RX_REMOTE_FAULT_K2_E5                                                             (0xf<<8) // Asserted when the  XLGMII reconciliation layer detects the Link Interruption (fault) sequences received on the link. One bit per port.
+  #define NWM_REG_RX_FAULT_RX_REMOTE_FAULT_K2_E5_SHIFT                                                       8
+#define NWM_REG_TX_FAULT_K2_E5                                                                               0x800084UL //Access:RW   DataWidth:0xc    // Multi Field Register.
+  #define NWM_REG_TX_FAULT_MAC0_TX_LOC_FAULT_K2_E5                                                           (0x1<<0) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Note: Only one of macN_tx_xxx_fault can be asserted at any time. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send loc fault
+  #define NWM_REG_TX_FAULT_MAC0_TX_LOC_FAULT_K2_E5_SHIFT                                                     0
+  #define NWM_REG_TX_FAULT_MAC0_TX_REM_FAULT_K2_E5                                                           (0x1<<1) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send loc rem
+  #define NWM_REG_TX_FAULT_MAC0_TX_REM_FAULT_K2_E5_SHIFT                                                     1
+  #define NWM_REG_TX_FAULT_MAC0_TX_LI_FAULT_K2_E5                                                            (0x1<<2) // Instructs the XLGMII/XGMII reconciliation layer to transmit Link Interruption Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send li rem
+  #define NWM_REG_TX_FAULT_MAC0_TX_LI_FAULT_K2_E5_SHIFT                                                      2
+  #define NWM_REG_TX_FAULT_MAC1_TX_LOC_FAULT_K2_E5                                                           (0x1<<3) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Note: Only one of macN_tx_xxx_fault can be asserted at any time. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send loc fault
+  #define NWM_REG_TX_FAULT_MAC1_TX_LOC_FAULT_K2_E5_SHIFT                                                     3
+  #define NWM_REG_TX_FAULT_MAC1_TX_REM_FAULT_K2_E5                                                           (0x1<<4) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send loc rem
+  #define NWM_REG_TX_FAULT_MAC1_TX_REM_FAULT_K2_E5_SHIFT                                                     4
+  #define NWM_REG_TX_FAULT_MAC1_TX_LI_FAULT_K2_E5                                                            (0x1<<5) // Instructs the XLGMII/XGMII reconciliation layer to transmit Link Interruption Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send li rem
+  #define NWM_REG_TX_FAULT_MAC1_TX_LI_FAULT_K2_E5_SHIFT                                                      5
+  #define NWM_REG_TX_FAULT_MAC2_TX_LOC_FAULT_K2_E5                                                           (0x1<<6) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Note: Only one of macN_tx_xxx_fault can be asserted at any time. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send loc fault
+  #define NWM_REG_TX_FAULT_MAC2_TX_LOC_FAULT_K2_E5_SHIFT                                                     6
+  #define NWM_REG_TX_FAULT_MAC2_TX_REM_FAULT_K2_E5                                                           (0x1<<7) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send loc rem
+  #define NWM_REG_TX_FAULT_MAC2_TX_REM_FAULT_K2_E5_SHIFT                                                     7
+  #define NWM_REG_TX_FAULT_MAC2_TX_LI_FAULT_K2_E5                                                            (0x1<<8) // Instructs the XLGMII/XGMII reconciliation layer to transmit Link Interruption Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send li rem
+  #define NWM_REG_TX_FAULT_MAC2_TX_LI_FAULT_K2_E5_SHIFT                                                      8
+  #define NWM_REG_TX_FAULT_MAC3_TX_LOC_FAULT_K2_E5                                                           (0x1<<9) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Note: Only one of macN_tx_xxx_fault can be asserted at any time. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send loc fault
+  #define NWM_REG_TX_FAULT_MAC3_TX_LOC_FAULT_K2_E5_SHIFT                                                     9
+  #define NWM_REG_TX_FAULT_MAC3_TX_REM_FAULT_K2_E5                                                           (0x1<<10) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send loc rem
+  #define NWM_REG_TX_FAULT_MAC3_TX_REM_FAULT_K2_E5_SHIFT                                                     10
+  #define NWM_REG_TX_FAULT_MAC3_TX_LI_FAULT_K2_E5                                                            (0x1<<11) // Instructs the XLGMII/XGMII reconciliation layer to transmit Link Interruption Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send li rem
+  #define NWM_REG_TX_FAULT_MAC3_TX_LI_FAULT_K2_E5_SHIFT                                                      11
+#define NWM_REG_LPI_IEEE_IDLE_CNT_VAL_0_K2_E5                                                                0x800088UL //Access:RW   DataWidth:0x9    // This field controls the minimum amount of time in which idle character will be transferred on TX line after going off LPI mode (and before transferring packets). The time for idle counter is defined as "REGISTER VAL"x100nsec. The reset value for this counter is 70 which represent 7usec.
+#define NWM_REG_LPI_IEEE_IDLE_CNT_VAL_1_K2_E5                                                                0x80008cUL //Access:RW   DataWidth:0x9    // This field controls the minimum amount of time in which idle character will be transferred on TX line after going off LPI mode (and before transferring packets). The time for idle counter is defined as "REGISTER VAL"x100nsec. The reset value for this counter is 70 which represent 7usec.
+#define NWM_REG_LPI_IEEE_IDLE_CNT_VAL_2_K2_E5                                                                0x800090UL //Access:RW   DataWidth:0x9    // This field controls the minimum amount of time in which idle character will be transferred on TX line after going off LPI mode (and before transferring packets). The time for idle counter is defined as "REGISTER VAL"x100nsec. The reset value for this counter is 70 which represent 7usec.
+#define NWM_REG_LPI_IEEE_IDLE_CNT_VAL_3_K2_E5                                                                0x800094UL //Access:RW   DataWidth:0x9    // This field controls the minimum amount of time in which idle character will be transferred on TX line after going off LPI mode (and before transferring packets). The time for idle counter is defined as "REGISTER VAL"x100nsec. The reset value for this counter is 70 which represent 7usec.
+#define NWM_REG_BER_TIMER_DONE_COUNT_0_K2_E5                                                                 0x800098UL //Access:RC   DataWidth:0x20   // count of the number of times ber_timer_done asserted. Clear on Read.
+#define NWM_REG_BER_TIMER_DONE_COUNT_1_K2_E5                                                                 0x80009cUL //Access:RC   DataWidth:0x20   // count of the number of times ber_timer_done asserted. Clear on Read.
+#define NWM_REG_BER_TIMER_DONE_COUNT_2_K2_E5                                                                 0x8000a0UL //Access:RC   DataWidth:0x20   // count of the number of times ber_timer_done asserted. Clear on Read.
+#define NWM_REG_BER_TIMER_DONE_COUNT_3_K2_E5                                                                 0x8000a4UL //Access:RC   DataWidth:0x20   // count of the number of times ber_timer_done asserted. Clear on Read.
+#define NWM_REG_FC_FEC_CERR_COUNT_0_K2_E5                                                                    0x8000a8UL //Access:RC   DataWidth:0x20   // FEC corrected error indication. The FEC could detect and correct receive errors in a block. count of the number of times fec_cerr asserted for virtual lane 0. Clear on Read.
+#define NWM_REG_FC_FEC_CERR_COUNT_1_K2_E5                                                                    0x8000acUL //Access:RC   DataWidth:0x20   // FEC corrected error indication. The FEC could detect and correct receive errors in a block. count of the number of times fec_cerr asserted for virtual lane 1. Clear on Read.
+#define NWM_REG_FC_FEC_CERR_COUNT_2_K2_E5                                                                    0x8000b0UL //Access:RC   DataWidth:0x20   // FEC corrected error indication. The FEC could detect and correct receive errors in a block. count of the number of times fec_cerr asserted for virtual lane 2. Clear on Read.
+#define NWM_REG_FC_FEC_CERR_COUNT_3_K2_E5                                                                    0x8000b4UL //Access:RC   DataWidth:0x20   // FEC corrected error indication. The FEC could detect and correct receive errors in a block. count of the number of times fec_cerr asserted for virtual lane 3. Clear on Read.
+#define NWM_REG_FC_FEC_CERR_COUNT_4_K2_E5                                                                    0x8000b8UL //Access:RC   DataWidth:0x20   // FEC corrected error indication. The FEC could detect and correct receive errors in a block. count of the number of times fec_cerr asserted for virtual lane 4. Clear on Read.
+#define NWM_REG_FC_FEC_CERR_COUNT_5_K2_E5                                                                    0x8000bcUL //Access:RC   DataWidth:0x20   // FEC corrected error indication. The FEC could detect and correct receive errors in a block. count of the number of times fec_cerr asserted for virtual lane 5. Clear on Read.
+#define NWM_REG_FC_FEC_CERR_COUNT_6_K2_E5                                                                    0x8000c0UL //Access:RC   DataWidth:0x20   // FEC corrected error indication. The FEC could detect and correct receive errors in a block. count of the number of times fec_cerr asserted for virtual lane 6. Clear on Read.
+#define NWM_REG_FC_FEC_CERR_COUNT_7_K2_E5                                                                    0x8000c4UL //Access:RC   DataWidth:0x20   // FEC corrected error indication. The FEC could detect and correct receive errors in a block. count of the number of times fec_cerr asserted for virtual lane 7. Clear on Read.
+#define NWM_REG_FC_FEC_NCERR_COUNT_0_K2_E5                                                                   0x8000c8UL //Access:RC   DataWidth:0x20   // count of the number of times fec_ncerr asserted for virtual lane 0. Clear on Read.
+#define NWM_REG_FC_FEC_NCERR_COUNT_1_K2_E5                                                                   0x8000ccUL //Access:RC   DataWidth:0x20   // FEC uncorrectable error indication. The FEC could detect but not correct receive errors in a block. count of the number of times fec_ncerr asserted for virtual lane 1. Clear on Read.
+#define NWM_REG_FC_FEC_NCERR_COUNT_2_K2_E5                                                                   0x8000d0UL //Access:RC   DataWidth:0x20   // FEC uncorrectable error indication. The FEC could detect but not correct receive errors in a block. count of the number of times fec_ncerr asserted for virtual lane 2. Clear on Read.
+#define NWM_REG_FC_FEC_NCERR_COUNT_3_K2_E5                                                                   0x8000d4UL //Access:RC   DataWidth:0x20   // FEC uncorrectable error indication. The FEC could detect but not correct receive errors in a block. count of the number of times fec_ncerr asserted for virtual lane 3. Clear on Read.
+#define NWM_REG_FC_FEC_NCERR_COUNT_4_K2_E5                                                                   0x8000d8UL //Access:RC   DataWidth:0x20   // FEC uncorrectable error indication. The FEC could detect but not correct receive errors in a block. count of the number of times fec_ncerr asserted for virtual lane 4. Clear on Read.
+#define NWM_REG_FC_FEC_NCERR_COUNT_5_K2_E5                                                                   0x8000dcUL //Access:RC   DataWidth:0x20   // FEC uncorrectable error indication. The FEC could detect but not correct receive errors in a block. count of the number of times fec_ncerr asserted for virtual lane 5. Clear on Read.
+#define NWM_REG_FC_FEC_NCERR_COUNT_6_K2_E5                                                                   0x8000e0UL //Access:RC   DataWidth:0x20   // FEC uncorrectable error indication. The FEC could detect but not correct receive errors in a block. count of the number of times fec_ncerr asserted for virtual lane 6. Clear on Read.
+#define NWM_REG_FC_FEC_NCERR_COUNT_7_K2_E5                                                                   0x8000e4UL //Access:RC   DataWidth:0x20   // FEC uncorrectable error indication. The FEC could detect but not correct receive errors in a block. count of the number of times fec_ncerr asserted for virtual lane 7. Clear on Read.
+#define NWM_REG_ECO_RESERVED_K2_E5                                                                           0x8000e8UL //Access:RW   DataWidth:0x20   // This is unused register for future ECOs.
+#define NWM_REG_DBG_SELECT_K2_E5                                                                             0x8000ecUL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define NWM_REG_DBG_DWORD_ENABLE_K2_E5                                                                       0x8000f0UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define NWM_REG_DBG_SHIFT_K2_E5                                                                              0x8000f4UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define NWM_REG_DBG_FORCE_VALID_K2_E5                                                                        0x8000f8UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define NWM_REG_DBG_FORCE_FRAME_K2_E5                                                                        0x8000fcUL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define NWM_REG_DBG_OUT_DATA_K2_E5                                                                           0x800100UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define NWM_REG_DBG_OUT_DATA_SIZE                                                                            8
+#define NWM_REG_DBG_OUT_VALID_K2_E5                                                                          0x800120UL //Access:R    DataWidth:0x4    // Dbgmux output valid
+#define NWM_REG_DBG_OUT_FRAME_K2_E5                                                                          0x800124UL //Access:R    DataWidth:0x4    // Dbgmux output frame
+#define NWM_REG_PRTY_MASK_H_0_K2_E5                                                                          0x800204UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define NWM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2_E5                                                      (0x1<<0) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2_E5_SHIFT                                                0
+  #define NWM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2_E5                                                      (0x1<<1) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2_E5_SHIFT                                                1
+  #define NWM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_K2_E5                                                      (0x1<<2) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_K2_E5_SHIFT                                                2
+  #define NWM_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY_K2_E5                                                      (0x1<<3) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM044_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY_K2_E5_SHIFT                                                3
+  #define NWM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2_E5                                                      (0x1<<4) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2_E5_SHIFT                                                4
+  #define NWM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_K2_E5                                                      (0x1<<5) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_K2_E5_SHIFT                                                5
+  #define NWM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_K2_E5                                                      (0x1<<6) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_K2_E5_SHIFT                                                6
+  #define NWM_REG_PRTY_MASK_H_0_MEM047_I_MEM_PRTY_K2_E5                                                      (0x1<<7) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM047_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM047_I_MEM_PRTY_K2_E5_SHIFT                                                7
+  #define NWM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2_E5                                                      (0x1<<8) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2_E5_SHIFT                                                8
+  #define NWM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_K2_E5                                                      (0x1<<9) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_K2_E5_SHIFT                                                9
+  #define NWM_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_K2_E5                                                      (0x1<<10) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM040_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_K2_E5_SHIFT                                                10
+  #define NWM_REG_PRTY_MASK_H_0_MEM048_I_MEM_PRTY_K2_E5                                                      (0x1<<11) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM048_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM048_I_MEM_PRTY_K2_E5_SHIFT                                                11
+  #define NWM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2_E5                                                      (0x1<<12) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2_E5_SHIFT                                                12
+  #define NWM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_K2_E5                                                      (0x1<<13) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_K2_E5_SHIFT                                                13
+  #define NWM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_K2_E5                                                      (0x1<<14) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_K2_E5_SHIFT                                                14
+  #define NWM_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY_K2_E5                                                      (0x1<<15) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM042_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY_K2_E5_SHIFT                                                15
+  #define NWM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_E5                                                      (0x1<<16) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_E5_SHIFT                                                16
+  #define NWM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_K2_E5                                                      (0x1<<17) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_K2_E5_SHIFT                                                17
+  #define NWM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_K2_E5                                                      (0x1<<18) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_K2_E5_SHIFT                                                18
+  #define NWM_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY_K2_E5                                                      (0x1<<19) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM041_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY_K2_E5_SHIFT                                                19
+  #define NWM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2_E5                                                      (0x1<<20) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2_E5_SHIFT                                                20
+  #define NWM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2_E5                                                      (0x1<<21) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2_E5_SHIFT                                                21
+  #define NWM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_K2_E5                                                      (0x1<<22) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_K2_E5_SHIFT                                                22
+  #define NWM_REG_PRTY_MASK_H_0_MEM045_I_MEM_PRTY_K2_E5                                                      (0x1<<23) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM045_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM045_I_MEM_PRTY_K2_E5_SHIFT                                                23
+  #define NWM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_E5                                                      (0x1<<24) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_E5_SHIFT                                                24
+  #define NWM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2_E5                                                      (0x1<<25) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2_E5_SHIFT                                                25
+  #define NWM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_K2_E5                                                      (0x1<<26) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_K2_E5_SHIFT                                                26
+  #define NWM_REG_PRTY_MASK_H_0_MEM043_I_MEM_PRTY_K2_E5                                                      (0x1<<27) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM043_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM043_I_MEM_PRTY_K2_E5_SHIFT                                                27
+  #define NWM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_K2_E5                                                      (0x1<<28) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_K2_E5_SHIFT                                                28
+  #define NWM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2_E5                                                      (0x1<<29) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2_E5_SHIFT                                                29
+  #define NWM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_K2_E5                                                      (0x1<<30) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_K2_E5_SHIFT                                                30
+#define NWM_REG_PRTY_MASK_H_1_K2_E5                                                                          0x800214UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define NWM_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY_K2_E5                                                      (0x1<<0) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM046_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY_K2_E5_SHIFT                                                0
+  #define NWM_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_K2_E5                                                      (0x1<<1) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM057_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_K2_E5_SHIFT                                                1
+  #define NWM_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY_K2_E5                                                      (0x1<<2) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM059_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY_K2_E5_SHIFT                                                2
+  #define NWM_REG_PRTY_MASK_H_1_MEM061_I_MEM_PRTY_K2_E5                                                      (0x1<<3) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM061_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM061_I_MEM_PRTY_K2_E5_SHIFT                                                3
+  #define NWM_REG_PRTY_MASK_H_1_MEM063_I_MEM_PRTY_K2_E5                                                      (0x1<<4) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM063_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM063_I_MEM_PRTY_K2_E5_SHIFT                                                4
+  #define NWM_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_K2_E5                                                      (0x1<<5) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM058_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_K2_E5_SHIFT                                                5
+  #define NWM_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY_K2_E5                                                      (0x1<<6) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM060_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY_K2_E5_SHIFT                                                6
+  #define NWM_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY_K2_E5                                                      (0x1<<7) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM062_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY_K2_E5_SHIFT                                                7
+  #define NWM_REG_PRTY_MASK_H_1_MEM064_I_MEM_PRTY_K2_E5                                                      (0x1<<8) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM064_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM064_I_MEM_PRTY_K2_E5_SHIFT                                                8
+  #define NWM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_K2_E5                                                      (0x1<<9) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_K2_E5_SHIFT                                                9
+  #define NWM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_K2_E5                                                      (0x1<<10) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_K2_E5_SHIFT                                                10
+  #define NWM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_K2_E5                                                      (0x1<<11) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_K2_E5_SHIFT                                                11
+  #define NWM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_K2_E5                                                      (0x1<<12) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM012_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_K2_E5_SHIFT                                                12
+  #define NWM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_K2_E5                                                      (0x1<<13) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_K2_E5_SHIFT                                                13
+  #define NWM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_K2_E5                                                      (0x1<<14) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_K2_E5_SHIFT                                                14
+  #define NWM_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_K2_E5                                                      (0x1<<15) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_K2_E5_SHIFT                                                15
+  #define NWM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_K2_E5                                                      (0x1<<16) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_K2_E5_SHIFT                                                16
+  #define NWM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2_E5                                                      (0x1<<17) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2_E5_SHIFT                                                17
+  #define NWM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2_E5                                                      (0x1<<18) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2_E5_SHIFT                                                18
+  #define NWM_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY_K2_E5                                                      (0x1<<19) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM003_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY_K2_E5_SHIFT                                                19
+  #define NWM_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_K2_E5                                                      (0x1<<20) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM004_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_K2_E5_SHIFT                                                20
+  #define NWM_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY_K2_E5                                                      (0x1<<21) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM005_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY_K2_E5_SHIFT                                                21
+  #define NWM_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_K2_E5                                                      (0x1<<22) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_K2_E5_SHIFT                                                22
+  #define NWM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_K2_E5                                                      (0x1<<23) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_K2_E5_SHIFT                                                23
+  #define NWM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_K2_E5                                                      (0x1<<24) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_K2_E5_SHIFT                                                24
+  #define NWM_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_K2_E5                                                      (0x1<<25) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM049_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_K2_E5_SHIFT                                                25
+  #define NWM_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_K2_E5                                                      (0x1<<26) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM053_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_K2_E5_SHIFT                                                26
+  #define NWM_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_K2_E5                                                      (0x1<<27) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_K2_E5_SHIFT                                                27
+  #define NWM_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY_K2_E5                                                      (0x1<<28) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM054_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY_K2_E5_SHIFT                                                28
+  #define NWM_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_K2_E5                                                      (0x1<<29) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM051_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_K2_E5_SHIFT                                                29
+  #define NWM_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_K2_E5                                                      (0x1<<30) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM055_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_K2_E5_SHIFT                                                30
+#define NWM_REG_PRTY_MASK_H_2_K2_E5                                                                          0x800224UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define NWM_REG_PRTY_MASK_H_2_MEM052_I_MEM_PRTY_K2_E5                                                      (0x1<<0) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM052_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_2_MEM052_I_MEM_PRTY_K2_E5_SHIFT                                                0
+  #define NWM_REG_PRTY_MASK_H_2_MEM056_I_MEM_PRTY_K2_E5                                                      (0x1<<1) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM056_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_2_MEM056_I_MEM_PRTY_K2_E5_SHIFT                                                1
+  #define NWM_REG_PRTY_MASK_H_2_MEM066_I_MEM_PRTY_K2_E5                                                      (0x1<<2) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM066_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_2_MEM066_I_MEM_PRTY_K2_E5_SHIFT                                                2
+  #define NWM_REG_PRTY_MASK_H_2_MEM068_I_MEM_PRTY_K2_E5                                                      (0x1<<3) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM068_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_2_MEM068_I_MEM_PRTY_K2_E5_SHIFT                                                3
+  #define NWM_REG_PRTY_MASK_H_2_MEM070_I_MEM_PRTY_K2_E5                                                      (0x1<<4) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM070_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_2_MEM070_I_MEM_PRTY_K2_E5_SHIFT                                                4
+  #define NWM_REG_PRTY_MASK_H_2_MEM072_I_MEM_PRTY_K2_E5                                                      (0x1<<5) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM072_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_2_MEM072_I_MEM_PRTY_K2_E5_SHIFT                                                5
+  #define NWM_REG_PRTY_MASK_H_2_MEM065_I_MEM_PRTY_K2_E5                                                      (0x1<<6) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM065_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_2_MEM065_I_MEM_PRTY_K2_E5_SHIFT                                                6
+  #define NWM_REG_PRTY_MASK_H_2_MEM067_I_MEM_PRTY_K2_E5                                                      (0x1<<7) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM067_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_2_MEM067_I_MEM_PRTY_K2_E5_SHIFT                                                7
+  #define NWM_REG_PRTY_MASK_H_2_MEM069_I_MEM_PRTY_K2_E5                                                      (0x1<<8) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM069_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_2_MEM069_I_MEM_PRTY_K2_E5_SHIFT                                                8
+  #define NWM_REG_PRTY_MASK_H_2_MEM071_I_MEM_PRTY_K2_E5                                                      (0x1<<9) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM071_I_MEM_PRTY .
+  #define NWM_REG_PRTY_MASK_H_2_MEM071_I_MEM_PRTY_K2_E5_SHIFT                                                9
+#define NWM_REG_MEM_ECC_EVENTS_K2_E5                                                                         0x800230UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define NWM_REG_MAC0_K2_E5                                                                                   0x800400UL //Access:RW   DataWidth:0x20   // Register space for MAC port 0. Registers defined in MAC64.1.0.xml
+#define NWM_REG_MAC0_SIZE                                                                                    256
+#define NWM_REG_MAC1_K2_E5                                                                                   0x800800UL //Access:RW   DataWidth:0x20   // Register space for MAC port 1. Registers defined in MAC64.1.0.xml
+#define NWM_REG_MAC1_SIZE                                                                                    256
+#define NWM_REG_MAC2_K2_E5                                                                                   0x800c00UL //Access:RW   DataWidth:0x20   // Register space for MAC port 2. Registers defined in MAC64.1.0.xml
+#define NWM_REG_MAC2_SIZE                                                                                    256
+#define NWM_REG_MAC3_K2_E5                                                                                   0x801000UL //Access:RW   DataWidth:0x20   // Register space for MAC port 3. Registers defined in MAC64.1.0.xml
+#define NWM_REG_MAC3_SIZE                                                                                    256
+#define NWM_REG_PCS_REG91_0_K2_E5                                                                            0x801400UL //Access:RW   DataWidth:0x10   // Register space for 10/25/40/50G PCS RS FEC port 0. Registers defined in rsfec91.1.0.xml
+#define NWM_REG_PCS_REG91_0_SIZE                                                                             256
+#define NWM_REG_PCS_REG91_1_K2_E5                                                                            0x801800UL //Access:RW   DataWidth:0x10   // Register space for 10/25/40/50G PCS RS FEC port 1. Registers defined in rsfec91.1.0.xml
+#define NWM_REG_PCS_REG91_1_SIZE                                                                             256
+#define NWM_REG_PCS_REG91_2_K2_E5                                                                            0x801c00UL //Access:RW   DataWidth:0x10   // Register space for 10/25G PCS RS FEC port 2. Registers defined in rsfec91.1.0.xml
+#define NWM_REG_PCS_REG91_2_SIZE                                                                             256
+#define NWM_REG_PCS_REG91_3_K2_E5                                                                            0x802000UL //Access:RW   DataWidth:0x10   // Register space for 10/25G PCS RS FEC port 3. Registers defined in rsfec91.1.0.xml
+#define NWM_REG_PCS_REG91_3_SIZE                                                                             256
+#define NWM_REG_PCS_LS0_K2_E5                                                                                0x802400UL //Access:RW   DataWidth:0x10   // Register space for 1G PCS port 0. Registers defined in PCS_1000basex_sgmii.1.0.xml
+#define NWM_REG_PCS_LS0_SIZE                                                                                 32
+#define NWM_REG_PCS_LS1_K2_E5                                                                                0x802480UL //Access:RW   DataWidth:0x10   // Register space for 1G PCS port 1. Registers defined in PCS_1000basex_sgmii.1.0.xml
+#define NWM_REG_PCS_LS1_SIZE                                                                                 32
+#define NWM_REG_PCS_LS2_K2_E5                                                                                0x802500UL //Access:RW   DataWidth:0x10   // Register space for 1G PCS port 2. Registers defined in PCS_1000basex_sgmii.1.0.xml
+#define NWM_REG_PCS_LS2_SIZE                                                                                 32
+#define NWM_REG_PCS_LS3_K2_E5                                                                                0x802580UL //Access:RW   DataWidth:0x10   // Register space for 1G PCS port 3. Registers defined in PCS_1000basex_sgmii.1.0.xml
+#define NWM_REG_PCS_LS3_SIZE                                                                                 32
+#define NWM_REG_PCS_HS0_K2_E5                                                                                0x840000UL //Access:RW   DataWidth:0x10   // Register space for 10/25/40/50G PCS port 0. Registers defined in pcs10254050.1.0.xml
+#define NWM_REG_PCS_HS0_SIZE                                                                                 65536
+#define NWM_REG_PCS_HS1_K2_E5                                                                                0x880000UL //Access:RW   DataWidth:0x10   // Register space for 10/25/40/50G PCS port 1. Registers defined in pcs10254050.1.0.xml
+#define NWM_REG_PCS_HS1_SIZE                                                                                 65536
+#define NWM_REG_PCS_HS2_K2_E5                                                                                0x8c0000UL //Access:RW   DataWidth:0x10   // Register space for 10/25G PCS port 2. Registers defined in pcs1025.1.0.xml
+#define NWM_REG_PCS_HS2_SIZE                                                                                 65536
+#define NWM_REG_PCS_HS3_K2_E5                                                                                0x900000UL //Access:RW   DataWidth:0x10   // Register space for 10/25G PCS port 3. Registers defined in pcs1025.1.0.xml
+#define NWM_REG_PCS_HS3_SIZE                                                                                 65536
+#define PBF_REG_INIT                                                                                         0xd80000UL //Access:RW   DataWidth:0x1    // Init bit. When set the initial credits are copied to the credit registers (except the port credits). Should be set and then reset after the configuration of the block has ended.
+#define PBF_REG_IF_ENABLE_REG                                                                                0xd80040UL //Access:RW   DataWidth:0x16   // Multi Field Register.
+  #define PBF_REG_IF_ENABLE_REG_DORQ_IF_ENABLE                                                               (0x1<<0) // Enables the dorq interface.
+  #define PBF_REG_IF_ENABLE_REG_DORQ_IF_ENABLE_SHIFT                                                         0
+  #define PBF_REG_IF_ENABLE_REG_YSEM_IF_ENABLE                                                               (0x1<<1) // Enables the ysem interface.
+  #define PBF_REG_IF_ENABLE_REG_YSEM_IF_ENABLE_SHIFT                                                         1
+  #define PBF_REG_IF_ENABLE_REG_PTU_REQ_IF_ENABLE                                                            (0x1<<2) // Enables the ptu_req interface.
+  #define PBF_REG_IF_ENABLE_REG_PTU_REQ_IF_ENABLE_SHIFT                                                      2
+  #define PBF_REG_IF_ENABLE_REG_TDIF_CMD_IF_ENABLE                                                           (0x1<<4) // Enables the tdif_cmd interface.
+  #define PBF_REG_IF_ENABLE_REG_TDIF_CMD_IF_ENABLE_SHIFT                                                     4
+  #define PBF_REG_IF_ENABLE_REG_TDIF_RDATA_IF_ENABLE                                                         (0x1<<5) // Enables the tdif_rdata interface.
+  #define PBF_REG_IF_ENABLE_REG_TDIF_RDATA_IF_ENABLE_SHIFT                                                   5
+  #define PBF_REG_IF_ENABLE_REG_PSEM_IF_ENABLE                                                               (0x1<<6) // Enables the psem interface.
+  #define PBF_REG_IF_ENABLE_REG_PSEM_IF_ENABLE_SHIFT                                                         6
+  #define PBF_REG_IF_ENABLE_REG_QM_LINE_CREDIT_IF_ENABLE                                                     (0x1<<7) // Enables the qm_line_credit interface.
+  #define PBF_REG_IF_ENABLE_REG_QM_LINE_CREDIT_IF_ENABLE_SHIFT                                               7
+  #define PBF_REG_IF_ENABLE_REG_TM_REQ_IF_ENABLE                                                             (0x1<<8) // Enables the tm_req interface.
+  #define PBF_REG_IF_ENABLE_REG_TM_REQ_IF_ENABLE_SHIFT                                                       8
+  #define PBF_REG_IF_ENABLE_REG_PXP_INT_WRREQ_IF_ENABLE                                                      (0x1<<9) // Enables the pxp_int_wrreq interface.
+  #define PBF_REG_IF_ENABLE_REG_PXP_INT_WRREQ_IF_ENABLE_SHIFT                                                9
+  #define PBF_REG_IF_ENABLE_REG_BTB_DATA_IF_ENABLE                                                           (0x1<<10) // Enables the btb_data interface.
+  #define PBF_REG_IF_ENABLE_REG_BTB_DATA_IF_ENABLE_SHIFT                                                     10
+  #define PBF_REG_IF_ENABLE_REG_BTB_RLS_IF_ENABLE                                                            (0x1<<11) // Enables the btb_rls interface.
+  #define PBF_REG_IF_ENABLE_REG_BTB_RLS_IF_ENABLE_SHIFT                                                      11
+  #define PBF_REG_IF_ENABLE_REG_TCM_IF_ENABLE                                                                (0x1<<12) // Enables the tcm interface.
+  #define PBF_REG_IF_ENABLE_REG_TCM_IF_ENABLE_SHIFT                                                          12
+  #define PBF_REG_IF_ENABLE_REG_MCM_IF_ENABLE                                                                (0x1<<13) // Enables the mcm interface.
+  #define PBF_REG_IF_ENABLE_REG_MCM_IF_ENABLE_SHIFT                                                          13
+  #define PBF_REG_IF_ENABLE_REG_UCM_IF_ENABLE                                                                (0x1<<14) // Enables the ucm interface.
+  #define PBF_REG_IF_ENABLE_REG_UCM_IF_ENABLE_SHIFT                                                          14
+  #define PBF_REG_IF_ENABLE_REG_XCM_IF_ENABLE                                                                (0x1<<15) // Enables the xcm interface.
+  #define PBF_REG_IF_ENABLE_REG_XCM_IF_ENABLE_SHIFT                                                          15
+  #define PBF_REG_IF_ENABLE_REG_YCM_IF_ENABLE                                                                (0x1<<16) // Enables the ycm interface.
+  #define PBF_REG_IF_ENABLE_REG_YCM_IF_ENABLE_SHIFT                                                          16
+  #define PBF_REG_IF_ENABLE_REG_TCM_DONE_IF_ENABLE                                                           (0x1<<17) // Enables the tcm_done interface.
+  #define PBF_REG_IF_ENABLE_REG_TCM_DONE_IF_ENABLE_SHIFT                                                     17
+  #define PBF_REG_IF_ENABLE_REG_MCM_DONE_IF_ENABLE                                                           (0x1<<18) // Enables the mcm_done interface.
+  #define PBF_REG_IF_ENABLE_REG_MCM_DONE_IF_ENABLE_SHIFT                                                     18
+  #define PBF_REG_IF_ENABLE_REG_UCM_DONE_IF_ENABLE                                                           (0x1<<19) // Enables the ucm_done interface.
+  #define PBF_REG_IF_ENABLE_REG_UCM_DONE_IF_ENABLE_SHIFT                                                     19
+  #define PBF_REG_IF_ENABLE_REG_YCM_DONE_IF_ENABLE                                                           (0x1<<20) // Enables the ycm_done interface.
+  #define PBF_REG_IF_ENABLE_REG_YCM_DONE_IF_ENABLE_SHIFT                                                     20
+  #define PBF_REG_IF_ENABLE_REG_TGFS_IF_ENABLE_E5                                                            (0x1<<21) // Enables the tgfs interface.
+  #define PBF_REG_IF_ENABLE_REG_TGFS_IF_ENABLE_E5_SHIFT                                                      21
+  #define PBF_REG_IF_ENABLE_REG_PCM_IF_ENABLE_BB_K2                                                          (0x1<<3) // Enables the pcm interface.
+  #define PBF_REG_IF_ENABLE_REG_PCM_IF_ENABLE_BB_K2_SHIFT                                                    3
+#define PBF_REG_DBG_SELECT                                                                                   0xd80060UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PBF_REG_DBG_DWORD_ENABLE                                                                             0xd80064UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PBF_REG_DBG_SHIFT                                                                                    0xd80068UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PBF_REG_DBG_FORCE_VALID                                                                              0xd8006cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PBF_REG_DBG_FORCE_FRAME                                                                              0xd80070UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PBF_REG_DBG_OUT_DATA                                                                                 0xd80080UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PBF_REG_DBG_OUT_DATA_SIZE                                                                            8
+#define PBF_REG_DBG_OUT_VALID                                                                                0xd800a0UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define PBF_REG_DBG_OUT_FRAME                                                                                0xd800a4UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define PBF_REG_FC_DBG_SELECT                                                                                0xd800a8UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PBF_REG_FC_DBG_DWORD_ENABLE                                                                          0xd800acUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PBF_REG_FC_DBG_SHIFT                                                                                 0xd800b0UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PBF_REG_FC_DBG_OUT_DATA                                                                              0xd800c0UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PBF_REG_FC_DBG_OUT_DATA_SIZE                                                                         8
+#define PBF_REG_FC_DBG_FORCE_VALID                                                                           0xd800e0UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PBF_REG_FC_DBG_FORCE_FRAME                                                                           0xd800e4UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PBF_REG_FC_DBG_OUT_VALID                                                                             0xd800e8UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define PBF_REG_FC_DBG_OUT_FRAME                                                                             0xd800ecUL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define PBF_REG_MEMCTRL_WR_RD_N_BB                                                                           0xd80100UL //Access:RW   DataWidth:0x1    // wr/rd indication to CPU BIST
+#define PBF_REG_MEMCTRL_CMD_BB                                                                               0xd80104UL //Access:RW   DataWidth:0x8    // command to CPU BIST
+#define PBF_REG_MEMCTRL_ADDRESS_BB                                                                           0xd80108UL //Access:RW   DataWidth:0x8    // address to CPU BIST
+#define PBF_REG_MEMCTRL_STATUS                                                                               0xd8010cUL //Access:R    DataWidth:0x20   // obsolete
+#define PBF_REG_INT_STS                                                                                      0xd80180UL //Access:R    DataWidth:0x1    // Multi Field Register.
+  #define PBF_REG_INT_STS_ADDRESS_ERROR                                                                      (0x1<<0) // Signals an unknown address to the rf module.
+  #define PBF_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                                0
+#define PBF_REG_INT_MASK                                                                                     0xd80184UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define PBF_REG_INT_MASK_ADDRESS_ERROR                                                                     (0x1<<0) // This bit masks, when set, the Interrupt bit: PBF_REG_INT_STS.ADDRESS_ERROR .
+  #define PBF_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                               0
+#define PBF_REG_INT_STS_WR                                                                                   0xd80188UL //Access:WR   DataWidth:0x1    // Multi Field Register.
+  #define PBF_REG_INT_STS_WR_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define PBF_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                             0
+#define PBF_REG_INT_STS_CLR                                                                                  0xd8018cUL //Access:RC   DataWidth:0x1    // Multi Field Register.
+  #define PBF_REG_INT_STS_CLR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define PBF_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                            0
+#define PBF_REG_PRTY_MASK                                                                                    0xd80194UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define PBF_REG_PRTY_MASK_DATAPATH_REGISTERS                                                               (0x1<<0) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS.DATAPATH_REGISTERS .
+  #define PBF_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                                         0
+#define PBF_REG_PRTY_MASK_H_0_BB_K2                                                                          0xd80204UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define PBF_REG_PRTY_MASK_H_0_MEM041_I_ECC_RF_INT_BB_K2                                                    (0x1<<0) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM041_I_ECC_RF_INT .
+  #define PBF_REG_PRTY_MASK_H_0_MEM041_I_ECC_RF_INT_BB_K2_SHIFT                                              0
+  #define PBF_REG_PRTY_MASK_H_0_MEM042_I_ECC_RF_INT_BB_K2                                                    (0x1<<1) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM042_I_ECC_RF_INT .
+  #define PBF_REG_PRTY_MASK_H_0_MEM042_I_ECC_RF_INT_BB_K2_SHIFT                                              1
+  #define PBF_REG_PRTY_MASK_H_0_MEM033_I_ECC_RF_INT_BB_K2                                                    (0x1<<2) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM033_I_ECC_RF_INT .
+  #define PBF_REG_PRTY_MASK_H_0_MEM033_I_ECC_RF_INT_BB_K2_SHIFT                                              2
+  #define PBF_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_BB_K2                                                    (0x1<<3) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
+  #define PBF_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_BB_K2_SHIFT                                              3
+  #define PBF_REG_PRTY_MASK_H_0_MEM018_I_ECC_RF_INT_BB_K2                                                    (0x1<<4) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM018_I_ECC_RF_INT .
+  #define PBF_REG_PRTY_MASK_H_0_MEM018_I_ECC_RF_INT_BB_K2_SHIFT                                              4
+  #define PBF_REG_PRTY_MASK_H_0_MEM009_I_ECC_0_RF_INT_BB_K2                                                  (0x1<<5) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM009_I_ECC_0_RF_INT .
+  #define PBF_REG_PRTY_MASK_H_0_MEM009_I_ECC_0_RF_INT_BB_K2_SHIFT                                            5
+  #define PBF_REG_PRTY_MASK_H_0_MEM009_I_ECC_1_RF_INT_BB_K2                                                  (0x1<<6) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM009_I_ECC_1_RF_INT .
+  #define PBF_REG_PRTY_MASK_H_0_MEM009_I_ECC_1_RF_INT_BB_K2_SHIFT                                            6
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_0_RF_INT_BB_K2                                                  (0x1<<7) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_0_RF_INT .
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_0_RF_INT_BB_K2_SHIFT                                            7
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_1_RF_INT_BB_K2                                                  (0x1<<8) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_1_RF_INT .
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_1_RF_INT_BB_K2_SHIFT                                            8
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_2_RF_INT_BB_K2                                                  (0x1<<9) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_2_RF_INT .
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_2_RF_INT_BB_K2_SHIFT                                            9
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_3_RF_INT_BB_K2                                                  (0x1<<10) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_3_RF_INT .
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_3_RF_INT_BB_K2_SHIFT                                            10
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_4_RF_INT_BB_K2                                                  (0x1<<11) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_4_RF_INT .
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_4_RF_INT_BB_K2_SHIFT                                            11
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_5_RF_INT_BB_K2                                                  (0x1<<12) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_5_RF_INT .
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_5_RF_INT_BB_K2_SHIFT                                            12
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_6_RF_INT_BB_K2                                                  (0x1<<13) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_6_RF_INT .
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_6_RF_INT_BB_K2_SHIFT                                            13
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_7_RF_INT_BB_K2                                                  (0x1<<14) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_7_RF_INT .
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_7_RF_INT_BB_K2_SHIFT                                            14
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_8_RF_INT_BB_K2                                                  (0x1<<15) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_8_RF_INT .
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_8_RF_INT_BB_K2_SHIFT                                            15
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_9_RF_INT_BB_K2                                                  (0x1<<16) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_9_RF_INT .
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_9_RF_INT_BB_K2_SHIFT                                            16
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_10_RF_INT_BB_K2                                                 (0x1<<17) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_10_RF_INT .
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_10_RF_INT_BB_K2_SHIFT                                           17
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_11_RF_INT_BB_K2                                                 (0x1<<18) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_11_RF_INT .
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_11_RF_INT_BB_K2_SHIFT                                           18
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_12_RF_INT_BB_K2                                                 (0x1<<19) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_12_RF_INT .
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_12_RF_INT_BB_K2_SHIFT                                           19
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_13_RF_INT_BB_K2                                                 (0x1<<20) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_13_RF_INT .
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_13_RF_INT_BB_K2_SHIFT                                           20
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_14_RF_INT_BB_K2                                                 (0x1<<21) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_14_RF_INT .
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_14_RF_INT_BB_K2_SHIFT                                           21
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_15_RF_INT_BB_K2                                                 (0x1<<22) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_15_RF_INT .
+  #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_15_RF_INT_BB_K2_SHIFT                                           22
+  #define PBF_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_BB_K2                                                      (0x1<<23) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM040_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_BB_K2_SHIFT                                                23
+  #define PBF_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_BB_K2                                                      (0x1<<24) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_BB_K2_SHIFT                                                24
+  #define PBF_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_BB_K2                                                      (0x1<<25) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_BB_K2_SHIFT                                                25
+  #define PBF_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_K2                                                      (0x1<<26) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_K2_SHIFT                                                26
+  #define PBF_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_K2                                                      (0x1<<27) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_K2_SHIFT                                                27
+  #define PBF_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_K2                                                      (0x1<<28) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_K2_SHIFT                                                28
+  #define PBF_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_K2                                                      (0x1<<29) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_K2_SHIFT                                                29
+  #define PBF_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_K2                                                      (0x1<<30) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_K2_SHIFT                                                30
+#define PBF_REG_PRTY_MASK_H_1_BB_K2                                                                          0xd80214UL //Access:RW   DataWidth:0x1b   // Multi Field Register.
+  #define PBF_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_BB_K2                                                      (0x1<<0) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM022_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_BB_K2_SHIFT                                                0
+  #define PBF_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY_BB_K2                                                      (0x1<<1) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM023_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY_BB_K2_SHIFT                                                1
+  #define PBF_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_BB_K2                                                      (0x1<<2) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM021_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_BB_K2_SHIFT                                                2
+  #define PBF_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_BB_K2                                                      (0x1<<3) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM020_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_BB_K2_SHIFT                                                3
+  #define PBF_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_K2                                                      (0x1<<4) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                                4
+  #define PBF_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_K2                                                      (0x1<<5) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                                5
+  #define PBF_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_BB_K2                                                      (0x1<<6) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_BB_K2_SHIFT                                                6
+  #define PBF_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_BB_K2                                                      (0x1<<7) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_BB_K2_SHIFT                                                7
+  #define PBF_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY_BB_K2                                                      (0x1<<8) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM005_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY_BB_K2_SHIFT                                                8
+  #define PBF_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_BB_K2                                                      (0x1<<9) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM004_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                                9
+  #define PBF_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_BB_K2                                                      (0x1<<10) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM028_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_BB_K2_SHIFT                                                10
+  #define PBF_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_BB_K2                                                      (0x1<<11) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM026_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_BB_K2_SHIFT                                                11
+  #define PBF_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_BB_K2                                                      (0x1<<12) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM027_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_BB_K2_SHIFT                                                12
+  #define PBF_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_BB_K2                                                      (0x1<<13) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM019_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_BB_K2_SHIFT                                                13
+  #define PBF_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_BB_K2                                                      (0x1<<14) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_BB_K2_SHIFT                                                14
+  #define PBF_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_BB_K2                                                      (0x1<<15) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_BB_K2_SHIFT                                                15
+  #define PBF_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_BB_K2                                                      (0x1<<16) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_BB_K2_SHIFT                                                16
+  #define PBF_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_BB_K2                                                      (0x1<<17) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_BB_K2_SHIFT                                                17
+  #define PBF_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB_K2                                                      (0x1<<18) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB_K2_SHIFT                                                18
+  #define PBF_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_BB_K2                                                      (0x1<<19) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM024_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_BB_K2_SHIFT                                                19
+  #define PBF_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_BB_K2                                                      (0x1<<20) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM025_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_BB_K2_SHIFT                                                20
+  #define PBF_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_BB_K2                                                      (0x1<<21) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM037_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_BB_K2_SHIFT                                                21
+  #define PBF_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_BB_K2                                                      (0x1<<22) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_BB_K2_SHIFT                                                22
+  #define PBF_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_BB_K2                                                      (0x1<<23) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM035_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_BB_K2_SHIFT                                                23
+  #define PBF_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_BB_K2                                                      (0x1<<24) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_BB_K2_SHIFT                                                24
+  #define PBF_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_BB_K2                                                      (0x1<<25) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_BB_K2_SHIFT                                                25
+  #define PBF_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_BB_K2                                                      (0x1<<26) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY .
+  #define PBF_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_BB_K2_SHIFT                                                26
+#define PBF_REG_MEM041_RF_ECC_ERROR_CONNECT_BB_K2                                                            0xd80220UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_even.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define PBF_REG_MEM042_RF_ECC_ERROR_CONNECT_BB_K2                                                            0xd80224UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_odd.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define PBF_REG_MEM_ECC_ENABLE_0_BB_K2                                                                       0xd80228UL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM041_I_ECC_EN_BB_K2                                                     (0x1<<0) // Enable ECC for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_even.i_ecc in module pbf_mem_ycmd_qs_mem_even
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM041_I_ECC_EN_BB_K2_SHIFT                                               0
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM042_I_ECC_EN_BB_K2                                                     (0x1<<1) // Enable ECC for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_odd.i_ecc in module pbf_mem_ycmd_qs_mem_odd
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM042_I_ECC_EN_BB_K2_SHIFT                                               1
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_EN_BB_K2                                                     (0x1<<2) // Enable ECC for memory ecc instance pbf.i_pbf_pmsgb.i_pbf_mem_parsing_info_database.i_ecc in module pbf_mem_parsing_info_database
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_EN_BB_K2_SHIFT                                               2
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_BB_K2                                                     (0x1<<3) // Enable ECC for memory ecc instance pbf.i_pb1_db.i_ecc in module pbf_mem_pb1_data_buffer
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_BB_K2_SHIFT                                               3
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM018_I_ECC_EN_BB_K2                                                     (0x1<<4) // Enable ECC for memory ecc instance pbf.i_pbf_hahd.i_pbf_mem_header_database.i_ecc in module pbf_mem_header_database
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM018_I_ECC_EN_BB_K2_SHIFT                                               4
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_0_EN_BB_K2                                                   (0x1<<5) // Enable ECC for memory ecc instance pbf.i_pb2_l1.i_ecc_0 in module pbf_mem_pb2_l1
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_0_EN_BB_K2_SHIFT                                             5
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_1_EN_BB_K2                                                   (0x1<<6) // Enable ECC for memory ecc instance pbf.i_pb2_l1.i_ecc_1 in module pbf_mem_pb2_l1
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_1_EN_BB_K2_SHIFT                                             6
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_0_EN_BB_K2                                                   (0x1<<7) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_0 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_0_EN_BB_K2_SHIFT                                             7
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_1_EN_BB_K2                                                   (0x1<<8) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_1 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_1_EN_BB_K2_SHIFT                                             8
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_2_EN_BB_K2                                                   (0x1<<9) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_2 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_2_EN_BB_K2_SHIFT                                             9
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_3_EN_BB_K2                                                   (0x1<<10) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_3 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_3_EN_BB_K2_SHIFT                                             10
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_4_EN_BB_K2                                                   (0x1<<11) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_4 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_4_EN_BB_K2_SHIFT                                             11
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_5_EN_BB_K2                                                   (0x1<<12) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_5 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_5_EN_BB_K2_SHIFT                                             12
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_6_EN_BB_K2                                                   (0x1<<13) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_6 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_6_EN_BB_K2_SHIFT                                             13
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_7_EN_BB_K2                                                   (0x1<<14) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_7 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_7_EN_BB_K2_SHIFT                                             14
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_8_EN_BB_K2                                                   (0x1<<15) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_8 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_8_EN_BB_K2_SHIFT                                             15
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_9_EN_BB_K2                                                   (0x1<<16) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_9 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_9_EN_BB_K2_SHIFT                                             16
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_10_EN_BB_K2                                                  (0x1<<17) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_10 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_10_EN_BB_K2_SHIFT                                            17
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_11_EN_BB_K2                                                  (0x1<<18) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_11 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_11_EN_BB_K2_SHIFT                                            18
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_12_EN_BB_K2                                                  (0x1<<19) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_12 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_12_EN_BB_K2_SHIFT                                            19
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_13_EN_BB_K2                                                  (0x1<<20) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_13 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_13_EN_BB_K2_SHIFT                                            20
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_14_EN_BB_K2                                                  (0x1<<21) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_14 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_14_EN_BB_K2_SHIFT                                            21
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_15_EN_BB_K2                                                  (0x1<<22) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_15 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_15_EN_BB_K2_SHIFT                                            22
+#define PBF_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                  0xd8022cUL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM041_I_ECC_PRTY_BB_K2                                              (0x1<<0) // Set parity only for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_even.i_ecc in module pbf_mem_ycmd_qs_mem_even
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM041_I_ECC_PRTY_BB_K2_SHIFT                                        0
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM042_I_ECC_PRTY_BB_K2                                              (0x1<<1) // Set parity only for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_odd.i_ecc in module pbf_mem_ycmd_qs_mem_odd
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM042_I_ECC_PRTY_BB_K2_SHIFT                                        1
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_PRTY_BB_K2                                              (0x1<<2) // Set parity only for memory ecc instance pbf.i_pbf_pmsgb.i_pbf_mem_parsing_info_database.i_ecc in module pbf_mem_parsing_info_database
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_PRTY_BB_K2_SHIFT                                        2
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_BB_K2                                              (0x1<<3) // Set parity only for memory ecc instance pbf.i_pb1_db.i_ecc in module pbf_mem_pb1_data_buffer
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_BB_K2_SHIFT                                        3
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM018_I_ECC_PRTY_BB_K2                                              (0x1<<4) // Set parity only for memory ecc instance pbf.i_pbf_hahd.i_pbf_mem_header_database.i_ecc in module pbf_mem_header_database
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM018_I_ECC_PRTY_BB_K2_SHIFT                                        4
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_0_PRTY_BB_K2                                            (0x1<<5) // Set parity only for memory ecc instance pbf.i_pb2_l1.i_ecc_0 in module pbf_mem_pb2_l1
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_0_PRTY_BB_K2_SHIFT                                      5
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_1_PRTY_BB_K2                                            (0x1<<6) // Set parity only for memory ecc instance pbf.i_pb2_l1.i_ecc_1 in module pbf_mem_pb2_l1
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_1_PRTY_BB_K2_SHIFT                                      6
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_0_PRTY_BB_K2                                            (0x1<<7) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_0 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_0_PRTY_BB_K2_SHIFT                                      7
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_1_PRTY_BB_K2                                            (0x1<<8) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_1 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_1_PRTY_BB_K2_SHIFT                                      8
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_2_PRTY_BB_K2                                            (0x1<<9) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_2 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_2_PRTY_BB_K2_SHIFT                                      9
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_3_PRTY_BB_K2                                            (0x1<<10) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_3 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_3_PRTY_BB_K2_SHIFT                                      10
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_4_PRTY_BB_K2                                            (0x1<<11) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_4 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_4_PRTY_BB_K2_SHIFT                                      11
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_5_PRTY_BB_K2                                            (0x1<<12) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_5 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_5_PRTY_BB_K2_SHIFT                                      12
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_6_PRTY_BB_K2                                            (0x1<<13) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_6 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_6_PRTY_BB_K2_SHIFT                                      13
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_7_PRTY_BB_K2                                            (0x1<<14) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_7 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_7_PRTY_BB_K2_SHIFT                                      14
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_8_PRTY_BB_K2                                            (0x1<<15) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_8 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_8_PRTY_BB_K2_SHIFT                                      15
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_9_PRTY_BB_K2                                            (0x1<<16) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_9 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_9_PRTY_BB_K2_SHIFT                                      16
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_10_PRTY_BB_K2                                           (0x1<<17) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_10 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_10_PRTY_BB_K2_SHIFT                                     17
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_11_PRTY_BB_K2                                           (0x1<<18) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_11 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_11_PRTY_BB_K2_SHIFT                                     18
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_12_PRTY_BB_K2                                           (0x1<<19) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_12 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_12_PRTY_BB_K2_SHIFT                                     19
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_13_PRTY_BB_K2                                           (0x1<<20) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_13 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_13_PRTY_BB_K2_SHIFT                                     20
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_14_PRTY_BB_K2                                           (0x1<<21) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_14 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_14_PRTY_BB_K2_SHIFT                                     21
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_15_PRTY_BB_K2                                           (0x1<<22) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_15 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_15_PRTY_BB_K2_SHIFT                                     22
+#define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                              0xd80230UL //Access:RC   DataWidth:0x17   // Multi Field Register.
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM041_I_ECC_CORRECT_BB_K2                                       (0x1<<0) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_even.i_ecc in module pbf_mem_ycmd_qs_mem_even
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM041_I_ECC_CORRECT_BB_K2_SHIFT                                 0
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM042_I_ECC_CORRECT_BB_K2                                       (0x1<<1) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_odd.i_ecc in module pbf_mem_ycmd_qs_mem_odd
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM042_I_ECC_CORRECT_BB_K2_SHIFT                                 1
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_CORRECT_BB_K2                                       (0x1<<2) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_pmsgb.i_pbf_mem_parsing_info_database.i_ecc in module pbf_mem_parsing_info_database
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_CORRECT_BB_K2_SHIFT                                 2
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_BB_K2                                       (0x1<<3) // Record if a correctable error occurred on memory ecc instance pbf.i_pb1_db.i_ecc in module pbf_mem_pb1_data_buffer
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_BB_K2_SHIFT                                 3
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM018_I_ECC_CORRECT_BB_K2                                       (0x1<<4) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_hahd.i_pbf_mem_header_database.i_ecc in module pbf_mem_header_database
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM018_I_ECC_CORRECT_BB_K2_SHIFT                                 4
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_0_CORRECT_BB_K2                                     (0x1<<5) // Record if a correctable error occurred on memory ecc instance pbf.i_pb2_l1.i_ecc_0 in module pbf_mem_pb2_l1
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_0_CORRECT_BB_K2_SHIFT                               5
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_1_CORRECT_BB_K2                                     (0x1<<6) // Record if a correctable error occurred on memory ecc instance pbf.i_pb2_l1.i_ecc_1 in module pbf_mem_pb2_l1
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_1_CORRECT_BB_K2_SHIFT                               6
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_0_CORRECT_BB_K2                                     (0x1<<7) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_0 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_0_CORRECT_BB_K2_SHIFT                               7
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_1_CORRECT_BB_K2                                     (0x1<<8) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_1 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_1_CORRECT_BB_K2_SHIFT                               8
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_2_CORRECT_BB_K2                                     (0x1<<9) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_2 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_2_CORRECT_BB_K2_SHIFT                               9
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_3_CORRECT_BB_K2                                     (0x1<<10) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_3 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_3_CORRECT_BB_K2_SHIFT                               10
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_4_CORRECT_BB_K2                                     (0x1<<11) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_4 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_4_CORRECT_BB_K2_SHIFT                               11
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_5_CORRECT_BB_K2                                     (0x1<<12) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_5 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_5_CORRECT_BB_K2_SHIFT                               12
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_6_CORRECT_BB_K2                                     (0x1<<13) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_6 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_6_CORRECT_BB_K2_SHIFT                               13
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_7_CORRECT_BB_K2                                     (0x1<<14) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_7 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_7_CORRECT_BB_K2_SHIFT                               14
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_8_CORRECT_BB_K2                                     (0x1<<15) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_8 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_8_CORRECT_BB_K2_SHIFT                               15
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_9_CORRECT_BB_K2                                     (0x1<<16) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_9 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_9_CORRECT_BB_K2_SHIFT                               16
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_10_CORRECT_BB_K2                                    (0x1<<17) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_10 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_10_CORRECT_BB_K2_SHIFT                              17
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_11_CORRECT_BB_K2                                    (0x1<<18) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_11 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_11_CORRECT_BB_K2_SHIFT                              18
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_12_CORRECT_BB_K2                                    (0x1<<19) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_12 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_12_CORRECT_BB_K2_SHIFT                              19
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_13_CORRECT_BB_K2                                    (0x1<<20) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_13 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_13_CORRECT_BB_K2_SHIFT                              20
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_14_CORRECT_BB_K2                                    (0x1<<21) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_14 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_14_CORRECT_BB_K2_SHIFT                              21
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_15_CORRECT_BB_K2                                    (0x1<<22) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_15 in module pbf_mem_btbif_buffer
+  #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_15_CORRECT_BB_K2_SHIFT                              22
+#define PBF_REG_MEM_ECC_EVENTS_BB_K2                                                                         0xd80234UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define PBF_REG_PXP_REQ_IF_INIT_CRD                                                                          0xd80400UL //Access:RW   DataWidth:0x3    // PXP read request interface initial credit - transoriented.
+#define PBF_REG_TDIF_PASS_THROUGH_INIT_CRD                                                                   0xd80404UL //Access:RW   DataWidth:0x6    // TDIF pass-through command interface initial credit.
+#define PBF_REG_TDIF_NON_PASS_THROUGH_INIT_CRD                                                               0xd80408UL //Access:RW   DataWidth:0x6    // TDIF non_pass-through command interface initial credit.
+#define PBF_REG_QM_LINE_CREDIT_IF_INIT_CRD                                                                   0xd8040cUL //Access:RW   DataWidth:0x2    // QM line credit interface initial credit.
+#define PBF_REG_PXP_INT_WRREQ_IF_INIT_CRD                                                                    0xd80410UL //Access:RW   DataWidth:0x2    // PXP internal write interface initial credit - transoriented.
+#define PBF_REG_TM_IF_INIT_CRD                                                                               0xd80414UL //Access:RW   DataWidth:0x3    // TM interface initial credit - transoriented.
+#define PBF_REG_PCM_IF_INIT_CRD_BB_K2                                                                        0xd80418UL //Access:RW   DataWidth:0x6    // PCM interface initial credit.
+#define PBF_REG_TCM_IF_INIT_CRD                                                                              0xd8041cUL //Access:RW   DataWidth:0x4    // TCM interface initial credit.
+#define PBF_REG_MCM_IF_INIT_CRD                                                                              0xd80420UL //Access:RW   DataWidth:0x4    // MCM interface initial credit.
+#define PBF_REG_UCM_IF_INIT_CRD                                                                              0xd80424UL //Access:RW   DataWidth:0x4    // UCM interface initial credit.
+#define PBF_REG_XCM_IF_INIT_CRD                                                                              0xd80428UL //Access:RW   DataWidth:0x4    // XCM interface initial credit.
+#define PBF_REG_YCM_IF_INIT_CRD                                                                              0xd8042cUL //Access:RW   DataWidth:0x4    // YCM interface initial credit.
+#define PBF_REG_TGFS_MAIN_IF_INIT_CRD_E5                                                                     0xd80430UL //Access:RW   DataWidth:0x6    // TGFS Main interface initial credit.
+#define PBF_REG_TGFS_SIDE_IF_INIT_CRD_E5                                                                     0xd80434UL //Access:RW   DataWidth:0x6    // TGFS Side interface initial credit.
+#define PBF_REG_PB1_DB_ALMOST_FULL_THRSH                                                                     0xd80440UL //Access:RW   DataWidth:0x7    // Almost full threhsold for PB1 that indicates the occupancy before full will be raised.
+#define PBF_REG_PB2_DB_ALMOST_FULL_THRSH                                                                     0xd80444UL //Access:RW   DataWidth:0x5    // Almost full threhsold for PB2 that indicates the occupancy before full will be raised.
+#define PBF_REG_PB1_TQ_ALMOST_FULL_THRSH                                                                     0xd80448UL //Access:RW   DataWidth:0x7    // Almost full threhsold for PB1 that indicates the occupancy before full will be raised.
+#define PBF_REG_PB2_TQ_ALMOST_FULL_THRSH                                                                     0xd8044cUL //Access:RW   DataWidth:0x7    // Almost full threhsold for PB2 that indicates the occupancy before full will be raised.
+#define PBF_REG_HPRS_DIN_BUFF_ALMOST_FULL_THRSH                                                              0xd80450UL //Access:RW   DataWidth:0x6    // Almost full threhsold for header parser data input buffer that indicates the occupancy before full will be raised.
+#define PBF_REG_HPRS_EXT_HDR_BUFF_ALMOST_FULL_THRSH                                                          0xd80454UL //Access:RW   DataWidth:0x5    // Almost full threhsold for header parser extracted header buffer that indicates the occupancy before full will be raised.
+#define PBF_REG_HB_MEM_ALMOST_FULL_THRSH                                                                     0xd80458UL //Access:RW   DataWidth:0x5    // Almost full threhsold for the memory that holds the header builder header, that indicates the occupancy before full will be raised.
+#define PBF_REG_MRKU_ALMOST_FULL_THRSH                                                                       0xd8045cUL //Access:RW   DataWidth:0x4    // Almost full threhsold for the FIFO at the output of PB1, that indicates the occupancy before full will be raised.
+#define PBF_REG_TAG_ETHERTYPE_0                                                                              0xd80480UL //Access:RW   DataWidth:0x10   // The Ethernet type value for L2 tag 0.
+#define PBF_REG_TAG_ETHERTYPE_1                                                                              0xd80484UL //Access:RW   DataWidth:0x10   // The Ethernet type value for L2 tag 1.
+#define PBF_REG_TAG_ETHERTYPE_2                                                                              0xd80488UL //Access:RW   DataWidth:0x10   // The Ethernet type value for L2 tag 2.
+#define PBF_REG_TAG_ETHERTYPE_3                                                                              0xd8048cUL //Access:RW   DataWidth:0x10   // The Ethernet type value for L2 tag 3.
+#define PBF_REG_TAG_ETHERTYPE_4                                                                              0xd80490UL //Access:RW   DataWidth:0x10   // The Ethernet type value for L2 tag 4.
+#define PBF_REG_TAG_ETHERTYPE_5                                                                              0xd80494UL //Access:RW   DataWidth:0x10   // The Ethernet type value for L2 tag 5.
+#define PBF_REG_TAG_LEN_0                                                                                    0xd80498UL //Access:RW   DataWidth:0x3    // The length of the info field for L2 tag 0.  The length is between 2B and 14B; in 2B granularity.
+#define PBF_REG_TAG_LEN_1                                                                                    0xd8049cUL //Access:RW   DataWidth:0x3    // The length of the info field for L2 tag 1.  The length is between 2B and 14B; in 2B granularity.
+#define PBF_REG_TAG_LEN_2                                                                                    0xd804a0UL //Access:RW   DataWidth:0x3    // The length of the info field for L2 tag 2.  The length is between 2B and 14B; in 2B granularity.
+#define PBF_REG_TAG_LEN_3                                                                                    0xd804a4UL //Access:RW   DataWidth:0x3    // The length of the info field for L2 tag 3.  The length is between 2B and 14B; in 2B granularity.
+#define PBF_REG_TAG_LEN_4                                                                                    0xd804a8UL //Access:RW   DataWidth:0x3    // The length of the info field for L2 tag 4.  The length is between 2B and 14B; in 2B granularity.
+#define PBF_REG_TAG_LEN_5                                                                                    0xd804acUL //Access:RW   DataWidth:0x3    // The length of the info field for L2 tag 5.  The length is between 2B and 14B; in 2B granularity.
+#define PBF_REG_FIRST_HDR_HDRS_AFTER_BASIC                                                                   0xd804b0UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.
+#define PBF_REG_FIRST_HDR_HDRS_AFTER_LLC                                                                     0xd804b4UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after the LLC header on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.
+#define PBF_REG_FIRST_HDR_HDRS_AFTER_TAG_0                                                                   0xd804b8UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.
+#define PBF_REG_FIRST_HDR_HDRS_AFTER_TAG_1                                                                   0xd804bcUL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.
+#define PBF_REG_FIRST_HDR_HDRS_AFTER_TAG_2                                                                   0xd804c0UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.
+#define PBF_REG_FIRST_HDR_HDRS_AFTER_TAG_3                                                                   0xd804c4UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.
+#define PBF_REG_FIRST_HDR_HDRS_AFTER_TAG_4                                                                   0xd804c8UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.
+#define PBF_REG_FIRST_HDR_HDRS_AFTER_TAG_5                                                                   0xd804ccUL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.
+#define PBF_REG_FIRST_HDR_MUST_HAVE_HDRS                                                                     0xd804d0UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which headers must appear in the packet on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.
+#define PBF_REG_INNER_HDR_HDRS_AFTER_BASIC                                                                   0xd804d4UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.
+#define PBF_REG_INNER_HDR_HDRS_AFTER_LLC                                                                     0xd804d8UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after the LLC header on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.
+#define PBF_REG_INNER_HDR_HDRS_AFTER_TAG_0                                                                   0xd804dcUL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.
+#define PBF_REG_INNER_HDR_HDRS_AFTER_TAG_1                                                                   0xd804e0UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.
+#define PBF_REG_INNER_HDR_HDRS_AFTER_TAG_2                                                                   0xd804e4UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.
+#define PBF_REG_INNER_HDR_HDRS_AFTER_TAG_3                                                                   0xd804e8UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.
+#define PBF_REG_INNER_HDR_HDRS_AFTER_TAG_4                                                                   0xd804ecUL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.
+#define PBF_REG_INNER_HDR_HDRS_AFTER_TAG_5                                                                   0xd804f0UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.
+#define PBF_REG_INNER_HDR_MUST_HAVE_HDRS                                                                     0xd804f4UL //Access:RW   DataWidth:0x8    // Per-port: Bit-map indicating which headers must appear in the packet on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.
+#define PBF_REG_LLC_TYPE_THRESHOLD                                                                           0xd804f8UL //Access:RW   DataWidth:0x10   // Upper value of LLC Ethertype range.
+#define PBF_REG_LLC_JUMBO_TYPE                                                                               0xd804fcUL //Access:RW   DataWidth:0x10   // Jumbo value of LLC Ethertype.
+#define PBF_REG_GRE_ETH_TYPE                                                                                 0xd80500UL //Access:RW   DataWidth:0x10   // Ethertype for encapsulated ethernet used in GRE header parsing.
+#define PBF_REG_IPV4_TYPE                                                                                    0xd80504UL //Access:RW   DataWidth:0x10   // IPv4 Ethertype.
+#define PBF_REG_IPV6_TYPE                                                                                    0xd80508UL //Access:RW   DataWidth:0x10   // IPv6 Ethertype.
+#define PBF_REG_TCP_PROTOCOL                                                                                 0xd8050cUL //Access:RW   DataWidth:0x8    // Value used to designate TCP in the IPv4 Protocol and IPv6 Next Header fields.
+#define PBF_REG_UDP_PROTOCOL                                                                                 0xd80510UL //Access:RW   DataWidth:0x8    // Value used to designate UDP in the IPv4 Protocol and IPv6 Next Header fields.
+#define PBF_REG_GRE_PROTOCOL                                                                                 0xd80514UL //Access:RW   DataWidth:0x8    // Value used to designate GRE in the IPv4 Protocol and IPv6 Next Header fields.
+#define PBF_REG_VXLAN_PORT                                                                                   0xd80518UL //Access:RW   DataWidth:0x10   // Dest port value used to designate a VXLAN header following the UDP header.
+#define PBF_REG_NGE_PORT                                                                                     0xd8051cUL //Access:RW   DataWidth:0x10   // Dest port value used to designate a NGE header following the UDP header.
+#define PBF_REG_NGE_ETH_TYPE                                                                                 0xd80520UL //Access:RW   DataWidth:0x10   // Ethertype for encapsulated ethernet used in NGE header parsing.
+#define PBF_REG_NGE_COMP_VER                                                                                 0xd80524UL //Access:RW   DataWidth:0x1    // Per-port:  Flag to compare the value of nge version to 2'b00.
+#define PBF_REG_SAME_AS_LAST_CONFIG_E5                                                                       0xd80528UL //Access:RW   DataWidth:0x13   // Multi Field Register.
+  #define PBF_REG_SAME_AS_LAST_CONFIG_SAL_VPORT_EN_E5                                                        (0x1<<0) // When High, it enables the Same as Last operation.
+  #define PBF_REG_SAME_AS_LAST_CONFIG_SAL_VPORT_EN_E5_SHIFT                                                  0
+  #define PBF_REG_SAME_AS_LAST_CONFIG_SAL_RESET_TCAM_ENTRIES_E5                                              (0x1<<1) // When high, it resets all tcam entries to invalid state
+  #define PBF_REG_SAME_AS_LAST_CONFIG_SAL_RESET_TCAM_ENTRIES_E5_SHIFT                                        1
+  #define PBF_REG_SAME_AS_LAST_CONFIG_SAL_RESET_PLRU_E5                                                      (0x1<<2) // When high, it resets the PLRU bits
+  #define PBF_REG_SAME_AS_LAST_CONFIG_SAL_RESET_PLRU_E5_SHIFT                                                2
+  #define PBF_REG_SAME_AS_LAST_CONFIG_SAL_FIRSTVLAN_EN_E5                                                    (0x1<<3) // Enables inclusion of the First VLAN ID in lookup tuple. If disabled, zero assigned to this VLAN ID field
+  #define PBF_REG_SAME_AS_LAST_CONFIG_SAL_FIRSTVLAN_EN_E5_SHIFT                                              3
+  #define PBF_REG_SAME_AS_LAST_CONFIG_SAL_FIRSTMAC_EN_E5                                                     (0x1<<4) // Enables inclusion of the First Destination MAC in lookup tuple. If disabled, zero assigned to this MAC field
+  #define PBF_REG_SAME_AS_LAST_CONFIG_SAL_FIRSTMAC_EN_E5_SHIFT                                               4
+  #define PBF_REG_SAME_AS_LAST_CONFIG_SAL_INNER_VLAN_EN_E5                                                   (0x1<<5) // Enables inclusion of the inner VLAN ID in lookup tuple. If disabled, zero assigned to this VLAN ID field
+  #define PBF_REG_SAME_AS_LAST_CONFIG_SAL_INNER_VLAN_EN_E5_SHIFT                                             5
+  #define PBF_REG_SAME_AS_LAST_CONFIG_SAL_INNER_SRCMAC_EN_E5                                                 (0x3<<6) // Enables inclusion of the Inner  Mac in lookup tuple, and has following options: 0: None, the corresponding field in tuple is 0 1: Source MAC address, the corresponding field in the tuple will include the source MAC address of the first MAC header in the packet 2: Inner destination MAC address. The corresponding field in the tuple will include the inner MAC header destination MAC address
+  #define PBF_REG_SAME_AS_LAST_CONFIG_SAL_INNER_SRCMAC_EN_E5_SHIFT                                           6
+  #define PBF_REG_SAME_AS_LAST_CONFIG_SAL_TUNNEL_TYPE_EN_E5                                                  (0x1<<8) // Enables inclusion of Tunnel Type in lookup tuple. If disabled, zero assigned for this field
+  #define PBF_REG_SAME_AS_LAST_CONFIG_SAL_TUNNEL_TYPE_EN_E5_SHIFT                                            8
+  #define PBF_REG_SAME_AS_LAST_CONFIG_SAL_TUNNEL_ID_EN_E5                                                    (0x1<<9) // Enables inclusion of Tunnel ID in lookup tuple. If disabled, zero assigned for this field
+  #define PBF_REG_SAME_AS_LAST_CONFIG_SAL_TUNNEL_ID_EN_E5_SHIFT                                              9
+  #define PBF_REG_SAME_AS_LAST_CONFIG_SAL_TUNNEL_ID_EXIST_EN_E5                                              (0x1<<10) // Enables inclusion of Tunnel ID Exist bit in lookup tuple. If disabled, zero assigned for this field
+  #define PBF_REG_SAME_AS_LAST_CONFIG_SAL_TUNNEL_ID_EXIST_EN_E5_SHIFT                                        10
+  #define PBF_REG_SAME_AS_LAST_CONFIG_SAL_VPORT_ID_BYTE_OFFSET_E5                                            (0x1f<<11) // Byte offset for vport id to be obtained from Y2P message
+  #define PBF_REG_SAME_AS_LAST_CONFIG_SAL_VPORT_ID_BYTE_OFFSET_E5_SHIFT                                      11
+  #define PBF_REG_SAME_AS_LAST_CONFIG_SAL_VPORT_ID_CYCLE_OFFSET_E5                                           (0x7<<16) // Cycle offset for vport id to be obtained from Y2P message
+  #define PBF_REG_SAME_AS_LAST_CONFIG_SAL_VPORT_ID_CYCLE_OFFSET_E5_SHIFT                                     16
+#define PBF_REG_SAME_AS_LAST_FLEX_FIELD_CONFIG_E5                                                            0xd8052cUL //Access:RW   DataWidth:0x1a   // Multi Field Register.
+  #define PBF_REG_SAME_AS_LAST_FLEX_FIELD_CONFIG_FLEX_FIELD_1_LENGTH_E5                                      (0x7<<0) // Length in bytes to be extracted from PBF2TGFS message for Flexible Field 1 in the tuple
+  #define PBF_REG_SAME_AS_LAST_FLEX_FIELD_CONFIG_FLEX_FIELD_1_LENGTH_E5_SHIFT                                0
+  #define PBF_REG_SAME_AS_LAST_FLEX_FIELD_CONFIG_FLEX_FIELD_1_CYCLE_OFFSET_E5                                (0x1f<<3) // Cycle offset for the field extracted from PBF2TGFS message for Flexible Field 1 in the tuple
+  #define PBF_REG_SAME_AS_LAST_FLEX_FIELD_CONFIG_FLEX_FIELD_1_CYCLE_OFFSET_E5_SHIFT                          3
+  #define PBF_REG_SAME_AS_LAST_FLEX_FIELD_CONFIG_FLEX_FIELD_1_BYTE_OFFSET_E5                                 (0x1f<<8) // Byte offset for the field extracted from PBF2TGFS message for Flexible Field 1 in the tuple
+  #define PBF_REG_SAME_AS_LAST_FLEX_FIELD_CONFIG_FLEX_FIELD_1_BYTE_OFFSET_E5_SHIFT                           8
+  #define PBF_REG_SAME_AS_LAST_FLEX_FIELD_CONFIG_FLEX_FIELD_2_LENGTH_E5                                      (0x7<<13) // Length in bytes to be extracted from PBF2TGFS message for Flexible Field 2 in the tuple
+  #define PBF_REG_SAME_AS_LAST_FLEX_FIELD_CONFIG_FLEX_FIELD_2_LENGTH_E5_SHIFT                                13
+  #define PBF_REG_SAME_AS_LAST_FLEX_FIELD_CONFIG_FLEX_FIELD_2_CYCLE_OFFSET_E5                                (0x1f<<16) // Cycle offset for the field extracted from PBF2TGFS message for Flexible Field 2 in the tuple
+  #define PBF_REG_SAME_AS_LAST_FLEX_FIELD_CONFIG_FLEX_FIELD_2_CYCLE_OFFSET_E5_SHIFT                          16
+  #define PBF_REG_SAME_AS_LAST_FLEX_FIELD_CONFIG_FLEX_FIELD_2_BYTE_OFFSET_E5                                 (0x1f<<21) // Byte offset for the field extracted from PBF2TGFS message for Flexible Field 2 in the tuple
+  #define PBF_REG_SAME_AS_LAST_FLEX_FIELD_CONFIG_FLEX_FIELD_2_BYTE_OFFSET_E5_SHIFT                           21
+#define PBF_REG_SAL_FLEX_MASK_0_E5                                                                           0xd80530UL //Access:RW   DataWidth:0x20   // Masks 64 bit Flexible field used for Same-as-last lookup. A 0 in each bit masks the corresponding key bit to 0
+#define PBF_REG_SAL_FLEX_MASK_1_E5                                                                           0xd80534UL //Access:RW   DataWidth:0x20   // Masks 64 bit Flexible field used for Same-as-last lookup. A 0 in each bit masks the corresponding key bit to 0
+#define PBF_REG_NUM_HITS_IN_SAL_E5                                                                           0xd80538UL //Access:ST   DataWidth:0x38   // Number of hits in Same as Last Lookup
+#define PBF_REG_NUM_HITS_IN_SAL_SIZE                                                                         2
+#define PBF_REG_NUM_LOOKUPS_IN_SAL_E5                                                                        0xd80540UL //Access:ST   DataWidth:0x38   // Number of lookup requests for Same as Last Lookup
+#define PBF_REG_NUM_LOOKUPS_IN_SAL_SIZE                                                                      2
+#define PBF_REG_PROP_HDR_SIZE                                                                                0xd80580UL //Access:RW   DataWidth:0x3    // PORT SPLIT. Size of the Propriatery/HiGig header. (in 4B increments). If HiGig is disabled this value should be 0.
+#define PBF_REG_REGULAR_INBAND_TAG_ORDER                                                                     0xd80584UL //Access:RW   DataWidth:0x1c   // The regular inband TAG order. Reset value is in the order from left to right: tag0; tag1; tag2; tag3; tag4; tag5; llc-snap.
+#define PBF_REG_T_TAG_TAGNUM                                                                                 0xd80588UL //Access:RW   DataWidth:0x4    // Per-Port: Specifies the flexible L2 tag to be used for T-tag.  The MSB enables T-tag recognition.
+#define PBF_REG_DST_MAC_GLOBAL_0                                                                             0xd8058cUL //Access:RW   DataWidth:0x20   // Global destination address match value.
+#define PBF_REG_DST_MAC_GLOBAL_1                                                                             0xd80590UL //Access:RW   DataWidth:0x10   // Global destination address match value.
+#define PBF_REG_DST_MAC_GLOBAL_MASK_0                                                                        0xd80594UL //Access:RW   DataWidth:0x20   // Mask for global destination address match value. A zero in this                 register will cause the corresponding bit to not be included in the match.
+#define PBF_REG_DST_MAC_GLOBAL_MASK_1                                                                        0xd80598UL //Access:RW   DataWidth:0x10   // Mask for global destination address match value. A zero in this                 register will cause the corresponding bit to not be included in the match.
+#define PBF_REG_UDP_DST_PORT_CFG_0                                                                           0xd8059cUL //Access:RW   DataWidth:0x10   // UDP destination port configuration 0 for match check.
+#define PBF_REG_UDP_DST_PORT_CFG_1                                                                           0xd805a0UL //Access:RW   DataWidth:0x10   // UDP destination port configuration 1 for match check.
+#define PBF_REG_UDP_DST_PORT_CFG_2                                                                           0xd805a4UL //Access:RW   DataWidth:0x10   // UDP destination port configuration 2 for match check.
+#define PBF_REG_BTB_SHARED_AREA_SIZE                                                                         0xd805c0UL //Access:RW   DataWidth:0xb    // Number of shared BTB 256 byte blocks which can be used by all TC-s in the port.
+#define PBF_REG_BTB_ALLOCATED_BLOCKS_SHARED                                                                  0xd805c4UL //Access:R    DataWidth:0xc    // Number of blocks that are currently allocated in the shared area of the port.
+#define PBF_REG_JUMBO_PKT_THRSH                                                                              0xd805c8UL //Access:RW   DataWidth:0x6    // Jumbo packet threshold in 256 byte blocks to determine if a TC can use the BTB shared area.
+#define PBF_REG_PRIORITY_CLIENT                                                                              0xd805ccUL //Access:RW   DataWidth:0x20   // Each nibble in the register from LS nibble to MS nibble holds the TC number of the corresponding priority. bits 3:0 hold the TC number from 0 to 7 of the highest priority TC. bits 31:28 hold the TC number from 0 to 7 of the lowest priority TC.
+#define PBF_REG_NUM_STRICT_PRIORITY_SLOTS                                                                    0xd805d0UL //Access:RW   DataWidth:0xa    // The number of strict priority arbitration slots between 2 RR arbitration slots in the ycommand arbiter. A value of 0 means no strict priority cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR arbiter. A value of all ones means no RR slots; i.e. the strict-priority w/ anti-starvation arbiter is a strict-priority arbiter.
+#define PBF_REG_L2_EDPM_THRSH                                                                                0xd805d4UL //Access:RW   DataWidth:0x8    // L2 EDPM threshold in 256 byte blocks. Only if all TC-s have allocated blocks below this threshold, L2 EDPM will be enabled.
+#define PBF_REG_CPMU_THRSH                                                                                   0xd805d8UL //Access:RW   DataWidth:0xb    // CPMU threshold in 256 byte blocks. Only if all TC-s in port N have allocated blocks above this threshold, the corresponding bit for that port will be set towards CPMU.
+#define PBF_REG_IP_ID_MASK_0                                                                                 0xd80600UL //Access:RW   DataWidth:0x10   // 1st bit mask used to control the rollover when increasing the IP ID field in the packet. Selected per command.
+#define PBF_REG_IP_ID_MASK_1                                                                                 0xd80604UL //Access:RW   DataWidth:0x10   // 2nd bit mask used to control the rollover when increasing the IP ID field in the packet. Selected per command.
+#define PBF_REG_IP_ID_MASK_2                                                                                 0xd80608UL //Access:RW   DataWidth:0x10   // 3rd bit mask used to control the rollover when increasing the IP ID field in the packet. Selected per command.
+#define PBF_REG_IP_ID_MASK_3                                                                                 0xd8060cUL //Access:RW   DataWidth:0x10   // 4th bit mask used to control the rollover when increasing the IP ID field in the packet. Selected per command.
+#define PBF_REG_ACK_FLG_MODE                                                                                 0xd80610UL //Access:RW   DataWidth:0x2    // Update mode for the ACK flag
+#define PBF_REG_CWR_FLG_MODE                                                                                 0xd80614UL //Access:RW   DataWidth:0x2    // Update mode for the CWR flag
+#define PBF_REG_ECE_FLG_MODE                                                                                 0xd80618UL //Access:RW   DataWidth:0x2    // Update mode for the ECE flag
+#define PBF_REG_FIN_FLG_MODE                                                                                 0xd8061cUL //Access:RW   DataWidth:0x2    // Update mode for the FIN flag
+#define PBF_REG_NS_FLG_MODE                                                                                  0xd80620UL //Access:RW   DataWidth:0x2    // Update mode for the NS flag
+#define PBF_REG_PUSH_FLG_MODE                                                                                0xd80624UL //Access:RW   DataWidth:0x2    // Update mode for the PUSH flag
+#define PBF_REG_RST_FLG_MODE                                                                                 0xd80628UL //Access:RW   DataWidth:0x2    // Update mode for the RESET flag
+#define PBF_REG_SYN_FLG_MODE                                                                                 0xd8062cUL //Access:RW   DataWidth:0x2    // Update mode for the SYN flag
+#define PBF_REG_URG_FLG_MODE                                                                                 0xd80630UL //Access:RW   DataWidth:0x2    // Update mode for the URG flag
+#define PBF_REG_TCM_SND_NXT_REG_OFFSET                                                                       0xd80634UL //Access:RW   DataWidth:0x4    // Update mode for the URG flag
+#define PBF_REG_PCI_VQ_ID                                                                                    0xd80640UL //Access:RW   DataWidth:0x5    // PCI VOQ ID used in read request to PCI.
+#define PBF_REG_DROP_PKT_UPON_ERR                                                                            0xd80644UL //Access:RW   DataWidth:0x1    // if set, packets with a PCIE/DIF error will be sent to BTB with a drop indication, otherwise will be sent with an error indication.
+#define PBF_REG_PER_VOQ_STAT_MASK                                                                            0xd80658UL //Access:RW   DataWidth:0x14   // per VOQ indication if it should be accounted for in bytes/packet statistics
+#define PBF_REG_NUM_PKTS_SENT_TO_BTB                                                                         0xd8065cUL //Access:RC   DataWidth:0x20   // Number of packets sent to BTB
+#define PBF_REG_NUM_BYTES_SENT_TO_BTB                                                                        0xd80660UL //Access:ST   DataWidth:0x30   // Number of bytes sent to BTB
+#define PBF_REG_NUM_BYTES_SENT_TO_BTB_SIZE                                                                   2
+#define PBF_REG_NUM_PKTS_RECEIVED_WITH_ERROR                                                                 0xd80668UL //Access:RC   DataWidth:0x8    // Number of packets received with error indication from PXP/TDIF
+#define PBF_REG_NUM_PKTS_SENT_WITH_ERROR_TO_BTB                                                              0xd8066cUL //Access:RC   DataWidth:0x8    // Number of packets sent to BTB with error indication
+#define PBF_REG_NUM_PKTS_SENT_WITH_DROP_TO_BTB                                                               0xd80670UL //Access:RC   DataWidth:0x8    // Number of packets sent to BTB with drop indication
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0                                                                       0xd806a0UL //Access:RW   DataWidth:0xc    // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 0.
+#define PBF_REG_YCMD_QS_THRSH_VOQ0                                                                           0xd806a4UL //Access:RW   DataWidth:0x5    // Almost full threshold for VOQ 0 in the YSTORM command Q in 32 byte lines.
+#define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ0                                                            0xd806a8UL //Access:RW   DataWidth:0x1    // Disable processing further Y commands from VOQ 0  (after ending the current command in process).
+#define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ0                                                                    0xd806acUL //Access:RC   DataWidth:0x20   // Number of commands received on VOQ 0 from YSTORM.
+#define PBF_REG_YCMD_QS_CMD_CNT_VOQ0                                                                         0xd806b0UL //Access:R    DataWidth:0xa    // Number of commands in the Y command queue of VOQ 0.
+#define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ0                                                                 0xd806b4UL //Access:R    DataWidth:0x20   // Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 0. Reset upon init.
+#define PBF_REG_YCMD_QS_OCCUPANCY_VOQ0                                                                       0xd806b8UL //Access:R    DataWidth:0xd    // Number of 16 bytes lines occupied in the Y command queue of VOQ 0.
+#define PBF_REG_BTB_GUARANTEED_VOQ0                                                                          0xd806bcUL //Access:RW   DataWidth:0xb    // The number of BTB 256 byte blocks guaranteed for VOQ 0
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0                                                                   0xd806c0UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_BTB_MAX_SHARED_ALLOC_VOQ0                                       (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 0
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_BTB_MAX_SHARED_ALLOC_VOQ0_SHIFT                                 0
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_BTB_CAN_USE_SHARED_VOQ0                                         (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_BTB_CAN_USE_SHARED_VOQ0_SHIFT                                   16
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ0                               (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ0_SHIFT                         17
+#define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ0                                                                    0xd806c4UL //Access:R    DataWidth:0xc    // Number of blocks allocated in the BTB for VOQ 0 in both guaranteed and shared areas.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0                                                               0xd806c8UL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks allocated (producer) for VOQ 0. Reset upon init.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0                                                               0xd806ccUL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks released (consumer) for VOQ 0. Reset upon init.
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1                                                                       0xd806e0UL //Access:RW   DataWidth:0xc    // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 1.
+#define PBF_REG_YCMD_QS_THRSH_VOQ1                                                                           0xd806e4UL //Access:RW   DataWidth:0x5    // Almost full threshold for VOQ 1 in the YSTORM command Q in 32 byte lines.
+#define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ1                                                            0xd806e8UL //Access:RW   DataWidth:0x1    // Disable processing further Y commands from VOQ 1  (after ending the current command in process).
+#define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ1                                                                    0xd806ecUL //Access:RC   DataWidth:0x20   // Number of commands received on VOQ 1 from YSTORM.
+#define PBF_REG_YCMD_QS_CMD_CNT_VOQ1                                                                         0xd806f0UL //Access:R    DataWidth:0xa    // Number of commands in the Y command queue of VOQ 1.
+#define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ1                                                                 0xd806f4UL //Access:R    DataWidth:0x20   // Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 1. Reset upon init.
+#define PBF_REG_YCMD_QS_OCCUPANCY_VOQ1                                                                       0xd806f8UL //Access:R    DataWidth:0xd    // Number of 16 bytes lines occupied in the Y command queue of VOQ 1.
+#define PBF_REG_BTB_GUARANTEED_VOQ1                                                                          0xd806fcUL //Access:RW   DataWidth:0xb    // The number of BTB 256 byte blocks guaranteed for VOQ 1
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1                                                                   0xd80700UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_BTB_MAX_SHARED_ALLOC_VOQ1                                       (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 1
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_BTB_MAX_SHARED_ALLOC_VOQ1_SHIFT                                 0
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_BTB_CAN_USE_SHARED_VOQ1                                         (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_BTB_CAN_USE_SHARED_VOQ1_SHIFT                                   16
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ1                               (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ1_SHIFT                         17
+#define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ1                                                                    0xd80704UL //Access:R    DataWidth:0xc    // Number of blocks allocated in the BTB for VOQ 1 in both guaranteed and shared areas.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ1                                                               0xd80708UL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks allocated (producer) for VOQ 1. Reset upon init.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ1                                                               0xd8070cUL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks released (consumer) for VOQ 1. Reset upon init.
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2                                                                       0xd80720UL //Access:RW   DataWidth:0xc    // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 2.
+#define PBF_REG_YCMD_QS_THRSH_VOQ2                                                                           0xd80724UL //Access:RW   DataWidth:0x5    // Almost full threshold for VOQ 2 in the YSTORM command Q in 32 byte lines.
+#define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ2                                                            0xd80728UL //Access:RW   DataWidth:0x1    // Disable processing further Y commands from VOQ 2  (after ending the current command in process).
+#define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ2                                                                    0xd8072cUL //Access:RC   DataWidth:0x20   // Number of commands received on VOQ 2 from YSTORM.
+#define PBF_REG_YCMD_QS_CMD_CNT_VOQ2                                                                         0xd80730UL //Access:R    DataWidth:0xa    // Number of commands in the Y command queue of VOQ 2.
+#define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ2                                                                 0xd80734UL //Access:R    DataWidth:0x20   // Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 2. Reset upon init.
+#define PBF_REG_YCMD_QS_OCCUPANCY_VOQ2                                                                       0xd80738UL //Access:R    DataWidth:0xd    // Number of 16 bytes lines occupied in the Y command queue of VOQ 2.
+#define PBF_REG_BTB_GUARANTEED_VOQ2                                                                          0xd8073cUL //Access:RW   DataWidth:0xb    // The number of BTB 256 byte blocks guaranteed for VOQ 2
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2                                                                   0xd80740UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_BTB_MAX_SHARED_ALLOC_VOQ2                                       (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 2
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_BTB_MAX_SHARED_ALLOC_VOQ2_SHIFT                                 0
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_BTB_CAN_USE_SHARED_VOQ2                                         (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_BTB_CAN_USE_SHARED_VOQ2_SHIFT                                   16
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ2                               (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ2_SHIFT                         17
+#define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ2                                                                    0xd80744UL //Access:R    DataWidth:0xc    // Number of blocks allocated in the BTB for VOQ 2 in both guaranteed and shared areas.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ2                                                               0xd80748UL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks allocated (producer) for VOQ 2. Reset upon init.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ2                                                               0xd8074cUL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks released (consumer) for VOQ 2. Reset upon init.
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3                                                                       0xd80760UL //Access:RW   DataWidth:0xc    // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 3.
+#define PBF_REG_YCMD_QS_THRSH_VOQ3                                                                           0xd80764UL //Access:RW   DataWidth:0x5    // Almost full threshold for VOQ 3 in the YSTORM command Q in 32 byte lines.
+#define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ3                                                            0xd80768UL //Access:RW   DataWidth:0x1    // Disable processing further Y commands from VOQ 3  (after ending the current command in process).
+#define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ3                                                                    0xd8076cUL //Access:RC   DataWidth:0x20   // Number of commands received on VOQ 3 from YSTORM.
+#define PBF_REG_YCMD_QS_CMD_CNT_VOQ3                                                                         0xd80770UL //Access:R    DataWidth:0xa    // Number of commands in the Y command queue of VOQ 3.
+#define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ3                                                                 0xd80774UL //Access:R    DataWidth:0x20   // Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 3. Reset upon init.
+#define PBF_REG_YCMD_QS_OCCUPANCY_VOQ3                                                                       0xd80778UL //Access:R    DataWidth:0xd    // Number of 16 bytes lines occupied in the Y command queue of VOQ 3.
+#define PBF_REG_BTB_GUARANTEED_VOQ3                                                                          0xd8077cUL //Access:RW   DataWidth:0xb    // The number of BTB 256 byte blocks guaranteed for VOQ 3
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3                                                                   0xd80780UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_BTB_MAX_SHARED_ALLOC_VOQ3                                       (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 3
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_BTB_MAX_SHARED_ALLOC_VOQ3_SHIFT                                 0
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_BTB_CAN_USE_SHARED_VOQ3                                         (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_BTB_CAN_USE_SHARED_VOQ3_SHIFT                                   16
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ3                               (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ3_SHIFT                         17
+#define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ3                                                                    0xd80784UL //Access:R    DataWidth:0xc    // Number of blocks allocated in the BTB for VOQ 3 in both guaranteed and shared areas.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ3                                                               0xd80788UL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks allocated (producer) for VOQ 3. Reset upon init.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ3                                                               0xd8078cUL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks released (consumer) for VOQ 3. Reset upon init.
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4                                                                       0xd807a0UL //Access:RW   DataWidth:0xc    // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 4.
+#define PBF_REG_YCMD_QS_THRSH_VOQ4                                                                           0xd807a4UL //Access:RW   DataWidth:0x5    // Almost full threshold for VOQ 4 in the YSTORM command Q in 32 byte lines.
+#define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ4                                                            0xd807a8UL //Access:RW   DataWidth:0x1    // Disable processing further Y commands from VOQ 4  (after ending the current command in process).
+#define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ4                                                                    0xd807acUL //Access:RC   DataWidth:0x20   // Number of commands received on VOQ 4 from YSTORM.
+#define PBF_REG_YCMD_QS_CMD_CNT_VOQ4                                                                         0xd807b0UL //Access:R    DataWidth:0xa    // Number of commands in the Y command queue of VOQ 4.
+#define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ4                                                                 0xd807b4UL //Access:R    DataWidth:0x20   // Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 4. Reset upon init.
+#define PBF_REG_YCMD_QS_OCCUPANCY_VOQ4                                                                       0xd807b8UL //Access:R    DataWidth:0xd    // Number of 16 bytes lines occupied in the Y command queue of VOQ 4.
+#define PBF_REG_BTB_GUARANTEED_VOQ4                                                                          0xd807bcUL //Access:RW   DataWidth:0xb    // The number of BTB 256 byte blocks guaranteed for VOQ 4
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4                                                                   0xd807c0UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_BTB_MAX_SHARED_ALLOC_VOQ4                                       (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 4
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_BTB_MAX_SHARED_ALLOC_VOQ4_SHIFT                                 0
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_BTB_CAN_USE_SHARED_VOQ4                                         (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_BTB_CAN_USE_SHARED_VOQ4_SHIFT                                   16
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ4                               (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ4_SHIFT                         17
+#define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ4                                                                    0xd807c4UL //Access:R    DataWidth:0xc    // Number of blocks allocated in the BTB for VOQ 4 in both guaranteed and shared areas.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ4                                                               0xd807c8UL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks allocated (producer) for VOQ 4. Reset upon init.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ4                                                               0xd807ccUL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks released (consumer) for VOQ 4. Reset upon init.
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5                                                                       0xd807e0UL //Access:RW   DataWidth:0xc    // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 5.
+#define PBF_REG_YCMD_QS_THRSH_VOQ5                                                                           0xd807e4UL //Access:RW   DataWidth:0x5    // Almost full threshold for VOQ 5 in the YSTORM command Q in 32 byte lines.
+#define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ5                                                            0xd807e8UL //Access:RW   DataWidth:0x1    // Disable processing further Y commands from VOQ 5  (after ending the current command in process).
+#define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ5                                                                    0xd807ecUL //Access:RC   DataWidth:0x20   // Number of commands received on VOQ 5 from YSTORM.
+#define PBF_REG_YCMD_QS_CMD_CNT_VOQ5                                                                         0xd807f0UL //Access:R    DataWidth:0xa    // Number of commands in the Y command queue of VOQ 5.
+#define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ5                                                                 0xd807f4UL //Access:R    DataWidth:0x20   // Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 5. Reset upon init.
+#define PBF_REG_YCMD_QS_OCCUPANCY_VOQ5                                                                       0xd807f8UL //Access:R    DataWidth:0xd    // Number of 16 bytes lines occupied in the Y command queue of VOQ 5.
+#define PBF_REG_BTB_GUARANTEED_VOQ5                                                                          0xd807fcUL //Access:RW   DataWidth:0xb    // The number of BTB 256 byte blocks guaranteed for VOQ 5
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5                                                                   0xd80800UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_BTB_MAX_SHARED_ALLOC_VOQ5                                       (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 5
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_BTB_MAX_SHARED_ALLOC_VOQ5_SHIFT                                 0
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_BTB_CAN_USE_SHARED_VOQ5                                         (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_BTB_CAN_USE_SHARED_VOQ5_SHIFT                                   16
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ5                               (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ5_SHIFT                         17
+#define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ5                                                                    0xd80804UL //Access:R    DataWidth:0xc    // Number of blocks allocated in the BTB for VOQ 5 in both guaranteed and shared areas.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ5                                                               0xd80808UL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks allocated (producer) for VOQ 5. Reset upon init.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ5                                                               0xd8080cUL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks released (consumer) for VOQ 5. Reset upon init.
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6                                                                       0xd80820UL //Access:RW   DataWidth:0xc    // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 6.
+#define PBF_REG_YCMD_QS_THRSH_VOQ6                                                                           0xd80824UL //Access:RW   DataWidth:0x5    // Almost full threshold for VOQ 6 in the YSTORM command Q in 32 byte lines.
+#define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ6                                                            0xd80828UL //Access:RW   DataWidth:0x1    // Disable processing further Y commands from VOQ 6  (after ending the current command in process).
+#define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ6                                                                    0xd8082cUL //Access:RC   DataWidth:0x20   // Number of commands received on VOQ 6 from YSTORM.
+#define PBF_REG_YCMD_QS_CMD_CNT_VOQ6                                                                         0xd80830UL //Access:R    DataWidth:0xa    // Number of commands in the Y command queue of VOQ 6.
+#define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ6                                                                 0xd80834UL //Access:R    DataWidth:0x20   // Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 6. Reset upon init.
+#define PBF_REG_YCMD_QS_OCCUPANCY_VOQ6                                                                       0xd80838UL //Access:R    DataWidth:0xd    // Number of 16 bytes lines occupied in the Y command queue of VOQ 6.
+#define PBF_REG_BTB_GUARANTEED_VOQ6                                                                          0xd8083cUL //Access:RW   DataWidth:0xb    // The number of BTB 256 byte blocks guaranteed for VOQ 6
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6                                                                   0xd80840UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_BTB_MAX_SHARED_ALLOC_VOQ6                                       (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 6
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_BTB_MAX_SHARED_ALLOC_VOQ6_SHIFT                                 0
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_BTB_CAN_USE_SHARED_VOQ6                                         (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_BTB_CAN_USE_SHARED_VOQ6_SHIFT                                   16
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ6                               (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ6_SHIFT                         17
+#define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ6                                                                    0xd80844UL //Access:R    DataWidth:0xc    // Number of blocks allocated in the BTB for VOQ 6 in both guaranteed and shared areas.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ6                                                               0xd80848UL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks allocated (producer) for VOQ 6. Reset upon init.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ6                                                               0xd8084cUL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks released (consumer) for VOQ 6. Reset upon init.
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7                                                                       0xd80860UL //Access:RW   DataWidth:0xc    // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 7.
+#define PBF_REG_YCMD_QS_THRSH_VOQ7                                                                           0xd80864UL //Access:RW   DataWidth:0x5    // Almost full threshold for VOQ 7 in the YSTORM command Q in 32 byte lines.
+#define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ7                                                            0xd80868UL //Access:RW   DataWidth:0x1    // Disable processing further Y commands from VOQ 7  (after ending the current command in process).
+#define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ7                                                                    0xd8086cUL //Access:RC   DataWidth:0x20   // Number of commands received on VOQ 7 from YSTORM.
+#define PBF_REG_YCMD_QS_CMD_CNT_VOQ7                                                                         0xd80870UL //Access:R    DataWidth:0xa    // Number of commands in the Y command queue of VOQ 7.
+#define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ7                                                                 0xd80874UL //Access:R    DataWidth:0x20   // Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 7. Reset upon init.
+#define PBF_REG_YCMD_QS_OCCUPANCY_VOQ7                                                                       0xd80878UL //Access:R    DataWidth:0xd    // Number of 16 bytes lines occupied in the Y command queue of VOQ 7.
+#define PBF_REG_BTB_GUARANTEED_VOQ7                                                                          0xd8087cUL //Access:RW   DataWidth:0xb    // The number of BTB 256 byte blocks guaranteed for VOQ 7
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7                                                                   0xd80880UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_BTB_MAX_SHARED_ALLOC_VOQ7                                       (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 7
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_BTB_MAX_SHARED_ALLOC_VOQ7_SHIFT                                 0
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_BTB_CAN_USE_SHARED_VOQ7                                         (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_BTB_CAN_USE_SHARED_VOQ7_SHIFT                                   16
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ7                               (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ7_SHIFT                         17
+#define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ7                                                                    0xd80884UL //Access:R    DataWidth:0xc    // Number of blocks allocated in the BTB for VOQ 7 in both guaranteed and shared areas.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ7                                                               0xd80888UL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks allocated (producer) for VOQ 7. Reset upon init.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ7                                                               0xd8088cUL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks released (consumer) for VOQ 7. Reset upon init.
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8                                                                       0xd808a0UL //Access:RW   DataWidth:0xc    // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 8.
+#define PBF_REG_YCMD_QS_THRSH_VOQ8                                                                           0xd808a4UL //Access:RW   DataWidth:0x5    // Almost full threshold for VOQ 8 in the YSTORM command Q in 32 byte lines.
+#define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ8                                                            0xd808a8UL //Access:RW   DataWidth:0x1    // Disable processing further Y commands from VOQ 8  (after ending the current command in process).
+#define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ8                                                                    0xd808acUL //Access:RC   DataWidth:0x20   // Number of commands received on VOQ 8 from YSTORM.
+#define PBF_REG_YCMD_QS_CMD_CNT_VOQ8                                                                         0xd808b0UL //Access:R    DataWidth:0xa    // Number of commands in the Y command queue of VOQ 8.
+#define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ8                                                                 0xd808b4UL //Access:R    DataWidth:0x20   // Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 8. Reset upon init.
+#define PBF_REG_YCMD_QS_OCCUPANCY_VOQ8                                                                       0xd808b8UL //Access:R    DataWidth:0xd    // Number of 16 bytes lines occupied in the Y command queue of VOQ 8.
+#define PBF_REG_BTB_GUARANTEED_VOQ8                                                                          0xd808bcUL //Access:RW   DataWidth:0xb    // The number of BTB 256 byte blocks guaranteed for VOQ 8
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8                                                                   0xd808c0UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_BTB_MAX_SHARED_ALLOC_VOQ8                                       (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 8
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_BTB_MAX_SHARED_ALLOC_VOQ8_SHIFT                                 0
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_BTB_CAN_USE_SHARED_VOQ8                                         (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_BTB_CAN_USE_SHARED_VOQ8_SHIFT                                   16
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ8                               (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ8_SHIFT                         17
+#define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ8                                                                    0xd808c4UL //Access:R    DataWidth:0xc    // Number of blocks allocated in the BTB for VOQ 8 in both guaranteed and shared areas.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ8                                                               0xd808c8UL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks allocated (producer) for VOQ 8. Reset upon init.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ8                                                               0xd808ccUL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks released (consumer) for VOQ 8. Reset upon init.
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9                                                                       0xd808e0UL //Access:RW   DataWidth:0xc    // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 9.
+#define PBF_REG_YCMD_QS_THRSH_VOQ9                                                                           0xd808e4UL //Access:RW   DataWidth:0x5    // Almost full threshold for VOQ 9 in the YSTORM command Q in 32 byte lines.
+#define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ9                                                            0xd808e8UL //Access:RW   DataWidth:0x1    // Disable processing further Y commands from VOQ 9  (after ending the current command in process).
+#define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ9                                                                    0xd808ecUL //Access:RC   DataWidth:0x20   // Number of commands received on VOQ 9 from YSTORM.
+#define PBF_REG_YCMD_QS_CMD_CNT_VOQ9                                                                         0xd808f0UL //Access:R    DataWidth:0xa    // Number of commands in the Y command queue of VOQ 9.
+#define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ9                                                                 0xd808f4UL //Access:R    DataWidth:0x20   // Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 9. Reset upon init.
+#define PBF_REG_YCMD_QS_OCCUPANCY_VOQ9                                                                       0xd808f8UL //Access:R    DataWidth:0xd    // Number of 16 bytes lines occupied in the Y command queue of VOQ 9.
+#define PBF_REG_BTB_GUARANTEED_VOQ9                                                                          0xd808fcUL //Access:RW   DataWidth:0xb    // The number of BTB 256 byte blocks guaranteed for VOQ 9
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9                                                                   0xd80900UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_BTB_MAX_SHARED_ALLOC_VOQ9                                       (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 9
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_BTB_MAX_SHARED_ALLOC_VOQ9_SHIFT                                 0
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_BTB_CAN_USE_SHARED_VOQ9                                         (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_BTB_CAN_USE_SHARED_VOQ9_SHIFT                                   16
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ9                               (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ9_SHIFT                         17
+#define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ9                                                                    0xd80904UL //Access:R    DataWidth:0xc    // Number of blocks allocated in the BTB for VOQ 9 in both guaranteed and shared areas.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ9                                                               0xd80908UL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks allocated (producer) for VOQ 9. Reset upon init.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ9                                                               0xd8090cUL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks released (consumer) for VOQ 9. Reset upon init.
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10                                                                      0xd80920UL //Access:RW   DataWidth:0xc    // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 10.
+#define PBF_REG_YCMD_QS_THRSH_VOQ10                                                                          0xd80924UL //Access:RW   DataWidth:0x5    // Almost full threshold for VOQ 10 in the YSTORM command Q in 32 byte lines.
+#define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ10                                                           0xd80928UL //Access:RW   DataWidth:0x1    // Disable processing further Y commands from VOQ 10  (after ending the current command in process).
+#define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ10                                                                   0xd8092cUL //Access:RC   DataWidth:0x20   // Number of commands received on VOQ 10 from YSTORM.
+#define PBF_REG_YCMD_QS_CMD_CNT_VOQ10                                                                        0xd80930UL //Access:R    DataWidth:0xa    // Number of commands in the Y command queue of VOQ 10.
+#define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ10                                                                0xd80934UL //Access:R    DataWidth:0x20   // Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 10. Reset upon init.
+#define PBF_REG_YCMD_QS_OCCUPANCY_VOQ10                                                                      0xd80938UL //Access:R    DataWidth:0xd    // Number of 16 bytes lines occupied in the Y command queue of VOQ 10.
+#define PBF_REG_BTB_GUARANTEED_VOQ10                                                                         0xd8093cUL //Access:RW   DataWidth:0xb    // The number of BTB 256 byte blocks guaranteed for VOQ 10
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10                                                                  0xd80940UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_BTB_MAX_SHARED_ALLOC_VOQ10                                     (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 10
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_BTB_MAX_SHARED_ALLOC_VOQ10_SHIFT                               0
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_BTB_CAN_USE_SHARED_VOQ10                                       (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_BTB_CAN_USE_SHARED_VOQ10_SHIFT                                 16
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ10                             (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ10_SHIFT                       17
+#define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ10                                                                   0xd80944UL //Access:R    DataWidth:0xc    // Number of blocks allocated in the BTB for VOQ 10 in both guaranteed and shared areas.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ10                                                              0xd80948UL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks allocated (producer) for VOQ 10. Reset upon init.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ10                                                              0xd8094cUL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks released (consumer) for VOQ 10. Reset upon init.
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11                                                                      0xd80960UL //Access:RW   DataWidth:0xc    // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 11.
+#define PBF_REG_YCMD_QS_THRSH_VOQ11                                                                          0xd80964UL //Access:RW   DataWidth:0x5    // Almost full threshold for VOQ 11 in the YSTORM command Q in 32 byte lines.
+#define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ11                                                           0xd80968UL //Access:RW   DataWidth:0x1    // Disable processing further Y commands from VOQ 11  (after ending the current command in process).
+#define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ11                                                                   0xd8096cUL //Access:RC   DataWidth:0x20   // Number of commands received on VOQ 11 from YSTORM.
+#define PBF_REG_YCMD_QS_CMD_CNT_VOQ11                                                                        0xd80970UL //Access:R    DataWidth:0xa    // Number of commands in the Y command queue of VOQ 11.
+#define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ11                                                                0xd80974UL //Access:R    DataWidth:0x20   // Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 11. Reset upon init.
+#define PBF_REG_YCMD_QS_OCCUPANCY_VOQ11                                                                      0xd80978UL //Access:R    DataWidth:0xd    // Number of 16 bytes lines occupied in the Y command queue of VOQ 11.
+#define PBF_REG_BTB_GUARANTEED_VOQ11                                                                         0xd8097cUL //Access:RW   DataWidth:0xb    // The number of BTB 256 byte blocks guaranteed for VOQ 11
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11                                                                  0xd80980UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_BTB_MAX_SHARED_ALLOC_VOQ11                                     (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 11
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_BTB_MAX_SHARED_ALLOC_VOQ11_SHIFT                               0
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_BTB_CAN_USE_SHARED_VOQ11                                       (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_BTB_CAN_USE_SHARED_VOQ11_SHIFT                                 16
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ11                             (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ11_SHIFT                       17
+#define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ11                                                                   0xd80984UL //Access:R    DataWidth:0xc    // Number of blocks allocated in the BTB for VOQ 11 in both guaranteed and shared areas.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ11                                                              0xd80988UL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks allocated (producer) for VOQ 11. Reset upon init.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ11                                                              0xd8098cUL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks released (consumer) for VOQ 11. Reset upon init.
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12                                                                      0xd809a0UL //Access:RW   DataWidth:0xc    // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 12.
+#define PBF_REG_YCMD_QS_THRSH_VOQ12                                                                          0xd809a4UL //Access:RW   DataWidth:0x5    // Almost full threshold for VOQ 12 in the YSTORM command Q in 32 byte lines.
+#define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ12                                                           0xd809a8UL //Access:RW   DataWidth:0x1    // Disable processing further Y commands from VOQ 12  (after ending the current command in process).
+#define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ12                                                                   0xd809acUL //Access:RC   DataWidth:0x20   // Number of commands received on VOQ 12 from YSTORM.
+#define PBF_REG_YCMD_QS_CMD_CNT_VOQ12                                                                        0xd809b0UL //Access:R    DataWidth:0xa    // Number of commands in the Y command queue of VOQ 12.
+#define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ12                                                                0xd809b4UL //Access:R    DataWidth:0x20   // Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 12. Reset upon init.
+#define PBF_REG_YCMD_QS_OCCUPANCY_VOQ12                                                                      0xd809b8UL //Access:R    DataWidth:0xd    // Number of 16 bytes lines occupied in the Y command queue of VOQ 12.
+#define PBF_REG_BTB_GUARANTEED_VOQ12                                                                         0xd809bcUL //Access:RW   DataWidth:0xb    // The number of BTB 256 byte blocks guaranteed for VOQ 12
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12                                                                  0xd809c0UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_BTB_MAX_SHARED_ALLOC_VOQ12                                     (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 12
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_BTB_MAX_SHARED_ALLOC_VOQ12_SHIFT                               0
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_BTB_CAN_USE_SHARED_VOQ12                                       (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_BTB_CAN_USE_SHARED_VOQ12_SHIFT                                 16
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ12                             (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ12_SHIFT                       17
+#define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ12                                                                   0xd809c4UL //Access:R    DataWidth:0xc    // Number of blocks allocated in the BTB for VOQ 12 in both guaranteed and shared areas.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ12                                                              0xd809c8UL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks allocated (producer) for VOQ 12. Reset upon init.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ12                                                              0xd809ccUL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks released (consumer) for VOQ 12. Reset upon init.
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13                                                                      0xd809e0UL //Access:RW   DataWidth:0xc    // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 13.
+#define PBF_REG_YCMD_QS_THRSH_VOQ13                                                                          0xd809e4UL //Access:RW   DataWidth:0x5    // Almost full threshold for VOQ 13 in the YSTORM command Q in 32 byte lines.
+#define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ13                                                           0xd809e8UL //Access:RW   DataWidth:0x1    // Disable processing further Y commands from VOQ 13  (after ending the current command in process).
+#define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ13                                                                   0xd809ecUL //Access:RC   DataWidth:0x20   // Number of commands received on VOQ 13 from YSTORM.
+#define PBF_REG_YCMD_QS_CMD_CNT_VOQ13                                                                        0xd809f0UL //Access:R    DataWidth:0xa    // Number of commands in the Y command queue of VOQ 13.
+#define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ13                                                                0xd809f4UL //Access:R    DataWidth:0x20   // Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 13. Reset upon init.
+#define PBF_REG_YCMD_QS_OCCUPANCY_VOQ13                                                                      0xd809f8UL //Access:R    DataWidth:0xd    // Number of 16 bytes lines occupied in the Y command queue of VOQ 13.
+#define PBF_REG_BTB_GUARANTEED_VOQ13                                                                         0xd809fcUL //Access:RW   DataWidth:0xb    // The number of BTB 256 byte blocks guaranteed for VOQ 13
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13                                                                  0xd80a00UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_BTB_MAX_SHARED_ALLOC_VOQ13                                     (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 13
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_BTB_MAX_SHARED_ALLOC_VOQ13_SHIFT                               0
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_BTB_CAN_USE_SHARED_VOQ13                                       (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_BTB_CAN_USE_SHARED_VOQ13_SHIFT                                 16
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ13                             (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ13_SHIFT                       17
+#define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ13                                                                   0xd80a04UL //Access:R    DataWidth:0xc    // Number of blocks allocated in the BTB for VOQ 13 in both guaranteed and shared areas.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ13                                                              0xd80a08UL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks allocated (producer) for VOQ 13. Reset upon init.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ13                                                              0xd80a0cUL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks released (consumer) for VOQ 13. Reset upon init.
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14                                                                      0xd80a20UL //Access:RW   DataWidth:0xc    // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 14.
+#define PBF_REG_YCMD_QS_THRSH_VOQ14                                                                          0xd80a24UL //Access:RW   DataWidth:0x5    // Almost full threshold for VOQ 14 in the YSTORM command Q in 32 byte lines.
+#define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ14                                                           0xd80a28UL //Access:RW   DataWidth:0x1    // Disable processing further Y commands from VOQ 14  (after ending the current command in process).
+#define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ14                                                                   0xd80a2cUL //Access:RC   DataWidth:0x20   // Number of commands received on VOQ 14 from YSTORM.
+#define PBF_REG_YCMD_QS_CMD_CNT_VOQ14                                                                        0xd80a30UL //Access:R    DataWidth:0xa    // Number of commands in the Y command queue of VOQ 14.
+#define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ14                                                                0xd80a34UL //Access:R    DataWidth:0x20   // Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 14. Reset upon init.
+#define PBF_REG_YCMD_QS_OCCUPANCY_VOQ14                                                                      0xd80a38UL //Access:R    DataWidth:0xd    // Number of 16 bytes lines occupied in the Y command queue of VOQ 14.
+#define PBF_REG_BTB_GUARANTEED_VOQ14                                                                         0xd80a3cUL //Access:RW   DataWidth:0xb    // The number of BTB 256 byte blocks guaranteed for VOQ 14
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14                                                                  0xd80a40UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_BTB_MAX_SHARED_ALLOC_VOQ14                                     (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 14
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_BTB_MAX_SHARED_ALLOC_VOQ14_SHIFT                               0
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_BTB_CAN_USE_SHARED_VOQ14                                       (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_BTB_CAN_USE_SHARED_VOQ14_SHIFT                                 16
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ14                             (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ14_SHIFT                       17
+#define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ14                                                                   0xd80a44UL //Access:R    DataWidth:0xc    // Number of blocks allocated in the BTB for VOQ 14 in both guaranteed and shared areas.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ14                                                              0xd80a48UL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks allocated (producer) for VOQ 14. Reset upon init.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ14                                                              0xd80a4cUL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks released (consumer) for VOQ 14. Reset upon init.
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15                                                                      0xd80a60UL //Access:RW   DataWidth:0xc    // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 15.
+#define PBF_REG_YCMD_QS_THRSH_VOQ15                                                                          0xd80a64UL //Access:RW   DataWidth:0x5    // Almost full threshold for VOQ 15 in the YSTORM command Q in 32 byte lines.
+#define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ15                                                           0xd80a68UL //Access:RW   DataWidth:0x1    // Disable processing further Y commands from VOQ 15  (after ending the current command in process).
+#define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ15                                                                   0xd80a6cUL //Access:RC   DataWidth:0x20   // Number of commands received on VOQ 15 from YSTORM.
+#define PBF_REG_YCMD_QS_CMD_CNT_VOQ15                                                                        0xd80a70UL //Access:R    DataWidth:0xa    // Number of commands in the Y command queue of VOQ 15.
+#define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ15                                                                0xd80a74UL //Access:R    DataWidth:0x20   // Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 15. Reset upon init.
+#define PBF_REG_YCMD_QS_OCCUPANCY_VOQ15                                                                      0xd80a78UL //Access:R    DataWidth:0xd    // Number of 16 bytes lines occupied in the Y command queue of VOQ 15.
+#define PBF_REG_BTB_GUARANTEED_VOQ15                                                                         0xd80a7cUL //Access:RW   DataWidth:0xb    // The number of BTB 256 byte blocks guaranteed for VOQ 15
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15                                                                  0xd80a80UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_BTB_MAX_SHARED_ALLOC_VOQ15                                     (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 15
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_BTB_MAX_SHARED_ALLOC_VOQ15_SHIFT                               0
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_BTB_CAN_USE_SHARED_VOQ15                                       (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_BTB_CAN_USE_SHARED_VOQ15_SHIFT                                 16
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ15                             (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ15_SHIFT                       17
+#define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ15                                                                   0xd80a84UL //Access:R    DataWidth:0xc    // Number of blocks allocated in the BTB for VOQ 15 in both guaranteed and shared areas.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ15                                                              0xd80a88UL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks allocated (producer) for VOQ 15. Reset upon init.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ15                                                              0xd80a8cUL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks released (consumer) for VOQ 15. Reset upon init.
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16                                                                      0xd80aa0UL //Access:RW   DataWidth:0xc    // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 16.
+#define PBF_REG_YCMD_QS_THRSH_VOQ16                                                                          0xd80aa4UL //Access:RW   DataWidth:0x5    // Almost full threshold for VOQ 16 in the YSTORM command Q in 32 byte lines.
+#define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ16                                                           0xd80aa8UL //Access:RW   DataWidth:0x1    // Disable processing further Y commands from VOQ 16  (after ending the current command in process).
+#define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ16                                                                   0xd80aacUL //Access:RC   DataWidth:0x20   // Number of commands received on VOQ 16 from YSTORM.
+#define PBF_REG_YCMD_QS_CMD_CNT_VOQ16                                                                        0xd80ab0UL //Access:R    DataWidth:0xa    // Number of commands in the Y command queue of VOQ 16.
+#define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ16                                                                0xd80ab4UL //Access:R    DataWidth:0x20   // Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 16. Reset upon init.
+#define PBF_REG_YCMD_QS_OCCUPANCY_VOQ16                                                                      0xd80ab8UL //Access:R    DataWidth:0xd    // Number of 16 bytes lines occupied in the Y command queue of VOQ 16.
+#define PBF_REG_BTB_GUARANTEED_VOQ16                                                                         0xd80abcUL //Access:RW   DataWidth:0xb    // The number of BTB 256 byte blocks guaranteed for VOQ 16
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16                                                                  0xd80ac0UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_BTB_MAX_SHARED_ALLOC_VOQ16                                     (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 16
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_BTB_MAX_SHARED_ALLOC_VOQ16_SHIFT                               0
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_BTB_CAN_USE_SHARED_VOQ16                                       (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_BTB_CAN_USE_SHARED_VOQ16_SHIFT                                 16
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ16                             (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ16_SHIFT                       17
+#define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ16                                                                   0xd80ac4UL //Access:R    DataWidth:0xc    // Number of blocks allocated in the BTB for VOQ 16 in both guaranteed and shared areas.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ16                                                              0xd80ac8UL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks allocated (producer) for VOQ 16. Reset upon init.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ16                                                              0xd80accUL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks released (consumer) for VOQ 16. Reset upon init.
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17                                                                      0xd80ae0UL //Access:RW   DataWidth:0xc    // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 17.
+#define PBF_REG_YCMD_QS_THRSH_VOQ17                                                                          0xd80ae4UL //Access:RW   DataWidth:0x5    // Almost full threshold for VOQ 17 in the YSTORM command Q in 32 byte lines.
+#define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ17                                                           0xd80ae8UL //Access:RW   DataWidth:0x1    // Disable processing further Y commands from VOQ 17  (after ending the current command in process).
+#define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ17                                                                   0xd80aecUL //Access:RC   DataWidth:0x20   // Number of commands received on VOQ 17 from YSTORM.
+#define PBF_REG_YCMD_QS_CMD_CNT_VOQ17                                                                        0xd80af0UL //Access:R    DataWidth:0xa    // Number of commands in the Y command queue of VOQ 17.
+#define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ17                                                                0xd80af4UL //Access:R    DataWidth:0x20   // Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 17. Reset upon init.
+#define PBF_REG_YCMD_QS_OCCUPANCY_VOQ17                                                                      0xd80af8UL //Access:R    DataWidth:0xd    // Number of 16 bytes lines occupied in the Y command queue of VOQ 17.
+#define PBF_REG_BTB_GUARANTEED_VOQ17                                                                         0xd80afcUL //Access:RW   DataWidth:0xb    // The number of BTB 256 byte blocks guaranteed for VOQ 17
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17                                                                  0xd80b00UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_BTB_MAX_SHARED_ALLOC_VOQ17                                     (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 17
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_BTB_MAX_SHARED_ALLOC_VOQ17_SHIFT                               0
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_BTB_CAN_USE_SHARED_VOQ17                                       (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_BTB_CAN_USE_SHARED_VOQ17_SHIFT                                 16
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ17                             (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ17_SHIFT                       17
+#define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ17                                                                   0xd80b04UL //Access:R    DataWidth:0xc    // Number of blocks allocated in the BTB for VOQ 17 in both guaranteed and shared areas.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ17                                                              0xd80b08UL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks allocated (producer) for VOQ 17. Reset upon init.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ17                                                              0xd80b0cUL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks released (consumer) for VOQ 17. Reset upon init.
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18                                                                      0xd80b20UL //Access:RW   DataWidth:0xc    // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 18.
+#define PBF_REG_YCMD_QS_THRSH_VOQ18                                                                          0xd80b24UL //Access:RW   DataWidth:0x5    // Almost full threshold for VOQ 18 in the YSTORM command Q in 32 byte lines.
+#define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ18                                                           0xd80b28UL //Access:RW   DataWidth:0x1    // Disable processing further Y commands from VOQ 18  (after ending the current command in process).
+#define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ18                                                                   0xd80b2cUL //Access:RC   DataWidth:0x20   // Number of commands received on VOQ 18 from YSTORM.
+#define PBF_REG_YCMD_QS_CMD_CNT_VOQ18                                                                        0xd80b30UL //Access:R    DataWidth:0xa    // Number of commands in the Y command queue of VOQ 18.
+#define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ18                                                                0xd80b34UL //Access:R    DataWidth:0x20   // Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 18. Reset upon init.
+#define PBF_REG_YCMD_QS_OCCUPANCY_VOQ18                                                                      0xd80b38UL //Access:R    DataWidth:0xd    // Number of 16 bytes lines occupied in the Y command queue of VOQ 18.
+#define PBF_REG_BTB_GUARANTEED_VOQ18                                                                         0xd80b3cUL //Access:RW   DataWidth:0xb    // The number of BTB 256 byte blocks guaranteed for VOQ 18
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18                                                                  0xd80b40UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_BTB_MAX_SHARED_ALLOC_VOQ18                                     (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 18
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_BTB_MAX_SHARED_ALLOC_VOQ18_SHIFT                               0
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_BTB_CAN_USE_SHARED_VOQ18                                       (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_BTB_CAN_USE_SHARED_VOQ18_SHIFT                                 16
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ18                             (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ18_SHIFT                       17
+#define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ18                                                                   0xd80b44UL //Access:R    DataWidth:0xc    // Number of blocks allocated in the BTB for VOQ 18 in both guaranteed and shared areas.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ18                                                              0xd80b48UL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks allocated (producer) for VOQ 18. Reset upon init.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ18                                                              0xd80b4cUL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks released (consumer) for VOQ 18. Reset upon init.
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19                                                                      0xd80b60UL //Access:RW   DataWidth:0xc    // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 19.
+#define PBF_REG_YCMD_QS_THRSH_VOQ19                                                                          0xd80b64UL //Access:RW   DataWidth:0x5    // Almost full threshold for VOQ 19 in the YSTORM command Q in 32 byte lines.
+#define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ19                                                           0xd80b68UL //Access:RW   DataWidth:0x1    // Disable processing further Y commands from VOQ 19  (after ending the current command in process).
+#define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ19                                                                   0xd80b6cUL //Access:RC   DataWidth:0x20   // Number of commands received on VOQ 19 from YSTORM.
+#define PBF_REG_YCMD_QS_CMD_CNT_VOQ19                                                                        0xd80b70UL //Access:R    DataWidth:0xa    // Number of commands in the Y command queue of VOQ 19.
+#define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ19                                                                0xd80b74UL //Access:R    DataWidth:0x20   // Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 19. Reset upon init.
+#define PBF_REG_YCMD_QS_OCCUPANCY_VOQ19                                                                      0xd80b78UL //Access:R    DataWidth:0xd    // Number of 16 bytes lines occupied in the Y command queue of VOQ 19.
+#define PBF_REG_BTB_GUARANTEED_VOQ19                                                                         0xd80b7cUL //Access:RW   DataWidth:0xb    // The number of BTB 256 byte blocks guaranteed for VOQ 19
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19                                                                  0xd80b80UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_BTB_MAX_SHARED_ALLOC_VOQ19                                     (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 19
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_BTB_MAX_SHARED_ALLOC_VOQ19_SHIFT                               0
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_BTB_CAN_USE_SHARED_VOQ19                                       (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_BTB_CAN_USE_SHARED_VOQ19_SHIFT                                 16
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ19                             (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
+  #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ19_SHIFT                       17
+#define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ19                                                                   0xd80b84UL //Access:R    DataWidth:0xc    // Number of blocks allocated in the BTB for VOQ 19 in both guaranteed and shared areas.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ19                                                              0xd80b88UL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks allocated (producer) for VOQ 19. Reset upon init.
+#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ19                                                              0xd80b8cUL //Access:R    DataWidth:0x20   // Cyclic counter for number of blocks released (consumer) for VOQ 19. Reset upon init.
+#define PBF_REG_ECO_RESERVED                                                                                 0xd80ea0UL //Access:RW   DataWidth:0x20   // reserved for ECOs
+#define PBF_PB1_REG_INT_STS                                                                                  0xda0040UL //Access:R    DataWidth:0x9    // Multi Field Register.
+  #define PBF_PB1_REG_INT_STS_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define PBF_PB1_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                            0
+  #define PBF_PB1_REG_INT_STS_EOP_ERROR                                                                      (0x1<<1) // EOP check error.
+  #define PBF_PB1_REG_INT_STS_EOP_ERROR_SHIFT                                                                1
+  #define PBF_PB1_REG_INT_STS_IFIFO_ERROR                                                                    (0x1<<2) // Instruction FIFO error.
+  #define PBF_PB1_REG_INT_STS_IFIFO_ERROR_SHIFT                                                              2
+  #define PBF_PB1_REG_INT_STS_PFIFO_ERROR                                                                    (0x1<<3) // Parameter FIFO error.
+  #define PBF_PB1_REG_INT_STS_PFIFO_ERROR_SHIFT                                                              3
+  #define PBF_PB1_REG_INT_STS_DB_BUF_ERROR                                                                   (0x1<<4) // DB FIFO error.
+  #define PBF_PB1_REG_INT_STS_DB_BUF_ERROR_SHIFT                                                             4
+  #define PBF_PB1_REG_INT_STS_TH_EXEC_ERROR                                                                  (0x1<<5) // 
+  #define PBF_PB1_REG_INT_STS_TH_EXEC_ERROR_SHIFT                                                            5
+  #define PBF_PB1_REG_INT_STS_TQ_ERROR_WR                                                                    (0x1<<6) // TQ write overflow.
+  #define PBF_PB1_REG_INT_STS_TQ_ERROR_WR_SHIFT                                                              6
+  #define PBF_PB1_REG_INT_STS_TQ_ERROR_RD_TH                                                                 (0x1<<7) // TQ read underflow by task handler.
+  #define PBF_PB1_REG_INT_STS_TQ_ERROR_RD_TH_SHIFT                                                           7
+  #define PBF_PB1_REG_INT_STS_TQ_ERROR_RD_IH                                                                 (0x1<<8) // TQ read underflow by instruction handler.
+  #define PBF_PB1_REG_INT_STS_TQ_ERROR_RD_IH_SHIFT                                                           8
+#define PBF_PB1_REG_INT_MASK                                                                                 0xda0044UL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define PBF_PB1_REG_INT_MASK_ADDRESS_ERROR                                                                 (0x1<<0) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.ADDRESS_ERROR .
+  #define PBF_PB1_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                           0
+  #define PBF_PB1_REG_INT_MASK_EOP_ERROR                                                                     (0x1<<1) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.EOP_ERROR .
+  #define PBF_PB1_REG_INT_MASK_EOP_ERROR_SHIFT                                                               1
+  #define PBF_PB1_REG_INT_MASK_IFIFO_ERROR                                                                   (0x1<<2) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.IFIFO_ERROR .
+  #define PBF_PB1_REG_INT_MASK_IFIFO_ERROR_SHIFT                                                             2
+  #define PBF_PB1_REG_INT_MASK_PFIFO_ERROR                                                                   (0x1<<3) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.PFIFO_ERROR .
+  #define PBF_PB1_REG_INT_MASK_PFIFO_ERROR_SHIFT                                                             3
+  #define PBF_PB1_REG_INT_MASK_DB_BUF_ERROR                                                                  (0x1<<4) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.DB_BUF_ERROR .
+  #define PBF_PB1_REG_INT_MASK_DB_BUF_ERROR_SHIFT                                                            4
+  #define PBF_PB1_REG_INT_MASK_TH_EXEC_ERROR                                                                 (0x1<<5) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TH_EXEC_ERROR .
+  #define PBF_PB1_REG_INT_MASK_TH_EXEC_ERROR_SHIFT                                                           5
+  #define PBF_PB1_REG_INT_MASK_TQ_ERROR_WR                                                                   (0x1<<6) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_WR .
+  #define PBF_PB1_REG_INT_MASK_TQ_ERROR_WR_SHIFT                                                             6
+  #define PBF_PB1_REG_INT_MASK_TQ_ERROR_RD_TH                                                                (0x1<<7) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_RD_TH .
+  #define PBF_PB1_REG_INT_MASK_TQ_ERROR_RD_TH_SHIFT                                                          7
+  #define PBF_PB1_REG_INT_MASK_TQ_ERROR_RD_IH                                                                (0x1<<8) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_RD_IH .
+  #define PBF_PB1_REG_INT_MASK_TQ_ERROR_RD_IH_SHIFT                                                          8
+#define PBF_PB1_REG_INT_STS_WR                                                                               0xda0048UL //Access:WR   DataWidth:0x9    // Multi Field Register.
+  #define PBF_PB1_REG_INT_STS_WR_ADDRESS_ERROR                                                               (0x1<<0) // Signals an unknown address to the rf module.
+  #define PBF_PB1_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                         0
+  #define PBF_PB1_REG_INT_STS_WR_EOP_ERROR                                                                   (0x1<<1) // EOP check error.
+  #define PBF_PB1_REG_INT_STS_WR_EOP_ERROR_SHIFT                                                             1
+  #define PBF_PB1_REG_INT_STS_WR_IFIFO_ERROR                                                                 (0x1<<2) // Instruction FIFO error.
+  #define PBF_PB1_REG_INT_STS_WR_IFIFO_ERROR_SHIFT                                                           2
+  #define PBF_PB1_REG_INT_STS_WR_PFIFO_ERROR                                                                 (0x1<<3) // Parameter FIFO error.
+  #define PBF_PB1_REG_INT_STS_WR_PFIFO_ERROR_SHIFT                                                           3
+  #define PBF_PB1_REG_INT_STS_WR_DB_BUF_ERROR                                                                (0x1<<4) // DB FIFO error.
+  #define PBF_PB1_REG_INT_STS_WR_DB_BUF_ERROR_SHIFT                                                          4
+  #define PBF_PB1_REG_INT_STS_WR_TH_EXEC_ERROR                                                               (0x1<<5) // 
+  #define PBF_PB1_REG_INT_STS_WR_TH_EXEC_ERROR_SHIFT                                                         5
+  #define PBF_PB1_REG_INT_STS_WR_TQ_ERROR_WR                                                                 (0x1<<6) // TQ write overflow.
+  #define PBF_PB1_REG_INT_STS_WR_TQ_ERROR_WR_SHIFT                                                           6
+  #define PBF_PB1_REG_INT_STS_WR_TQ_ERROR_RD_TH                                                              (0x1<<7) // TQ read underflow by task handler.
+  #define PBF_PB1_REG_INT_STS_WR_TQ_ERROR_RD_TH_SHIFT                                                        7
+  #define PBF_PB1_REG_INT_STS_WR_TQ_ERROR_RD_IH                                                              (0x1<<8) // TQ read underflow by instruction handler.
+  #define PBF_PB1_REG_INT_STS_WR_TQ_ERROR_RD_IH_SHIFT                                                        8
+#define PBF_PB1_REG_INT_STS_CLR                                                                              0xda004cUL //Access:RC   DataWidth:0x9    // Multi Field Register.
+  #define PBF_PB1_REG_INT_STS_CLR_ADDRESS_ERROR                                                              (0x1<<0) // Signals an unknown address to the rf module.
+  #define PBF_PB1_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                        0
+  #define PBF_PB1_REG_INT_STS_CLR_EOP_ERROR                                                                  (0x1<<1) // EOP check error.
+  #define PBF_PB1_REG_INT_STS_CLR_EOP_ERROR_SHIFT                                                            1
+  #define PBF_PB1_REG_INT_STS_CLR_IFIFO_ERROR                                                                (0x1<<2) // Instruction FIFO error.
+  #define PBF_PB1_REG_INT_STS_CLR_IFIFO_ERROR_SHIFT                                                          2
+  #define PBF_PB1_REG_INT_STS_CLR_PFIFO_ERROR                                                                (0x1<<3) // Parameter FIFO error.
+  #define PBF_PB1_REG_INT_STS_CLR_PFIFO_ERROR_SHIFT                                                          3
+  #define PBF_PB1_REG_INT_STS_CLR_DB_BUF_ERROR                                                               (0x1<<4) // DB FIFO error.
+  #define PBF_PB1_REG_INT_STS_CLR_DB_BUF_ERROR_SHIFT                                                         4
+  #define PBF_PB1_REG_INT_STS_CLR_TH_EXEC_ERROR                                                              (0x1<<5) // 
+  #define PBF_PB1_REG_INT_STS_CLR_TH_EXEC_ERROR_SHIFT                                                        5
+  #define PBF_PB1_REG_INT_STS_CLR_TQ_ERROR_WR                                                                (0x1<<6) // TQ write overflow.
+  #define PBF_PB1_REG_INT_STS_CLR_TQ_ERROR_WR_SHIFT                                                          6
+  #define PBF_PB1_REG_INT_STS_CLR_TQ_ERROR_RD_TH                                                             (0x1<<7) // TQ read underflow by task handler.
+  #define PBF_PB1_REG_INT_STS_CLR_TQ_ERROR_RD_TH_SHIFT                                                       7
+  #define PBF_PB1_REG_INT_STS_CLR_TQ_ERROR_RD_IH                                                             (0x1<<8) // TQ read underflow by instruction handler.
+  #define PBF_PB1_REG_INT_STS_CLR_TQ_ERROR_RD_IH_SHIFT                                                       8
+#define PBF_PB1_REG_PRTY_MASK                                                                                0xda0054UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define PBF_PB1_REG_PRTY_MASK_DATAPATH_REGISTERS                                                           (0x1<<0) // This bit masks, when set, the Parity bit: PB_REG_PRTY_STS.DATAPATH_REGISTERS .
+  #define PBF_PB1_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                                     0
+#define PBF_PB1_REG_CONTROL                                                                                  0xda0400UL //Access:RW   DataWidth:0xd    // Multi Field Register.
+  #define PBF_PB1_REG_CONTROL_BYTE_ORDER_SWITCH                                                              (0x1<<0) // Indicates if to switch the CRC result byte ordering. 0=don't switch;1=switch.
+  #define PBF_PB1_REG_CONTROL_BYTE_ORDER_SWITCH_SHIFT                                                        0
+  #define PBF_PB1_REG_CONTROL_DB_IGNORE_ERROR                                                                (0x1<<1) // Indicates if to ignore the input error indication.
+  #define PBF_PB1_REG_CONTROL_DB_IGNORE_ERROR_SHIFT                                                          1
+  #define PBF_PB1_REG_CONTROL_DONT_PASS_ERROR                                                                (0x1<<2) // Masks error on output of pb.
+  #define PBF_PB1_REG_CONTROL_DONT_PASS_ERROR_SHIFT                                                          2
+  #define PBF_PB1_REG_CONTROL_EOP_CHECK_DISABLE                                                              (0x1<<3) // Disables EOP check (EOP check verifies that the last Task instruction is accessing a line that has EOP on it. this way one could find mismatches between expected length and actual length on some packet.
+  #define PBF_PB1_REG_CONTROL_EOP_CHECK_DISABLE_SHIFT                                                        3
+  #define PBF_PB1_REG_CONTROL_CRC_COMPARE_DISABLE                                                            (0x1<<4) // Disables CRC2 machine (the machine that is used for comparing actual CRC with a value that is provided to the PB.
+  #define PBF_PB1_REG_CONTROL_CRC_COMPARE_DISABLE_SHIFT                                                      4
+  #define PBF_PB1_REG_CONTROL_EN_INPUTS                                                                      (0x1<<5) // Enable inputs.
+  #define PBF_PB1_REG_CONTROL_EN_INPUTS_SHIFT                                                                5
+  #define PBF_PB1_REG_CONTROL_DISABLE_PB                                                                     (0x1<<6) // Debug only: Disable PB.
+  #define PBF_PB1_REG_CONTROL_DISABLE_PB_SHIFT                                                               6
+  #define PBF_PB1_REG_CONTROL_DEBUG_SELECT                                                                   (0xf<<7) // Obsolete.
+  #define PBF_PB1_REG_CONTROL_DEBUG_SELECT_SHIFT                                                             7
+  #define PBF_PB1_REG_CONTROL_RELAX_TH                                                                       (0x1<<11) // Dbug only.
+  #define PBF_PB1_REG_CONTROL_RELAX_TH_SHIFT                                                                 11
+  #define PBF_PB1_REG_CONTROL_DUMMY_ERR_ALLOW                                                                (0x1<<12) // Dummy ingress error allow.  When cleared, an error received on the ingress interface will be masked for instructions in which the "dummy read" bit is set.
+  #define PBF_PB1_REG_CONTROL_DUMMY_ERR_ALLOW_SHIFT                                                          12
+#define PBF_PB1_REG_CRC_MASK_1_0                                                                             0xda0404UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PBF_PB1_REG_CRC_MASK_1_1                                                                             0xda0408UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PBF_PB1_REG_CRC_MASK_1_2                                                                             0xda040cUL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PBF_PB1_REG_CRC_MASK_1_3                                                                             0xda0410UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PBF_PB1_REG_CRC_MASK_2_0                                                                             0xda0414UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PBF_PB1_REG_CRC_MASK_2_1                                                                             0xda0418UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PBF_PB1_REG_CRC_MASK_2_2                                                                             0xda041cUL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PBF_PB1_REG_CRC_MASK_2_3                                                                             0xda0420UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PBF_PB1_REG_CRC_MASK_3_0                                                                             0xda0424UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PBF_PB1_REG_CRC_MASK_3_1                                                                             0xda0428UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PBF_PB1_REG_CRC_MASK_3_2                                                                             0xda042cUL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PBF_PB1_REG_CRC_MASK_3_3                                                                             0xda0430UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PBF_PB1_REG_DB_EMPTY                                                                                 0xda0500UL //Access:R    DataWidth:0x1    // Data Buffer empty status.
+#define PBF_PB1_REG_DB_FULL                                                                                  0xda0504UL //Access:R    DataWidth:0x1    // Data Buffer full status.
+#define PBF_PB1_REG_TQ_EMPTY                                                                                 0xda0508UL //Access:R    DataWidth:0x1    // Task Queue empty status.
+#define PBF_PB1_REG_TQ_FULL                                                                                  0xda050cUL //Access:R    DataWidth:0x1    // Task Queue full status.
+#define PBF_PB1_REG_IFIFO_EMPTY                                                                              0xda0510UL //Access:R    DataWidth:0x1    // Instruction FIFO empty status.
+#define PBF_PB1_REG_IFIFO_FULL                                                                               0xda0514UL //Access:R    DataWidth:0x1    // Instruction FIFO full status.
+#define PBF_PB1_REG_PFIFO_EMPTY                                                                              0xda0518UL //Access:R    DataWidth:0x1    // Parameter FIFO empty status.
+#define PBF_PB1_REG_PFIFO_FULL                                                                               0xda051cUL //Access:R    DataWidth:0x1    // Parameter FIFO full status.
+#define PBF_PB1_REG_TQ_TH_EMPTY                                                                              0xda0520UL //Access:R    DataWidth:0x1    // Task Queue empty status for task handler.
+#define PBF_PB1_REG_ERRORED_CRC                                                                              0xda0600UL //Access:R    DataWidth:0x20   // CRC mismatch debug register.  This register stores the calculated CRC value that resulted in the most recent CRC error event.
+#define PBF_PB1_REG_ERRORED_INSTR                                                                            0xda0604UL //Access:R    DataWidth:0x20   // EOP mismatch debug register.  Use this address to read the instruction being executed at the time EOP error is detected. The instruction is aligned with the least significant bit of this register.  Bits 31:29 provide additional information about the instruction.  Bit 31 indicates whether the instruction is valid.  Bit 30 indicates if the instruction is the first instruction in the task.  Bit 29 indicates whether the instruction is the last instruction in the task.
+#define PBF_PB1_REG_ERRORED_HDR_LOW                                                                          0xda0608UL //Access:R    DataWidth:0x20   // EOP mismatch debug register.  Use this address to read the lower 32 bits of the task header being executed at the time EOP error is detected.  The instruction length is not kept and is read as 0.
+#define PBF_PB1_REG_ERRORED_HDR_HIGH                                                                         0xda060cUL //Access:R    DataWidth:0x20   // EOP mismatch debug register.  Use this address to read the upper 32 bits of the task header being executed at the time EOP error is detected.  The task passthrough bit is not kept and is read as 0.
+#define PBF_PB1_REG_ERRORED_LENGTH                                                                           0xda0610UL //Access:R    DataWidth:0x10   // EOP mismatch debug register.  This register provides the number of data bytes remaining to be read from DB at the time of EOP error detection.
+#define PBF_PB1_REG_ECO_RESERVED                                                                             0xda0614UL //Access:RW   DataWidth:0x8    // For future eco.
+#define PBF_PB1_REG_DBG_OUT_DATA                                                                             0xda0700UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PBF_PB1_REG_DBG_OUT_DATA_SIZE                                                                        8
+#define PBF_PB1_REG_DBG_OUT_VALID                                                                            0xda0720UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define PBF_PB1_REG_DBG_OUT_FRAME                                                                            0xda0724UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define PBF_PB1_REG_DBG_SELECT                                                                               0xda0728UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PBF_PB1_REG_DBG_DWORD_ENABLE                                                                         0xda072cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PBF_PB1_REG_DBG_SHIFT                                                                                0xda0730UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PBF_PB1_REG_DBG_FORCE_VALID                                                                          0xda0734UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PBF_PB1_REG_DBG_FORCE_FRAME                                                                          0xda0738UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PBF_PB1_REG_DB_FIFO                                                                                  0xda2000UL //Access:WB_R DataWidth:0x108  // Provides read-only access of the data buffer FIFO. Intended for debug purposes.
+#define PBF_PB1_REG_DB_FIFO_SIZE                                                                             512
+#define PBF_PB1_REG_L1                                                                                       0xda3000UL //Access:WB   DataWidth:0x40   // L1 CRC memory access.
+#define PBF_PB1_REG_L1_SIZE                                                                                  640
+#define PBF_PB2_REG_INT_STS                                                                                  0xda4040UL //Access:R    DataWidth:0x9    // Multi Field Register.
+  #define PBF_PB2_REG_INT_STS_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define PBF_PB2_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                            0
+  #define PBF_PB2_REG_INT_STS_EOP_ERROR                                                                      (0x1<<1) // EOP check error.
+  #define PBF_PB2_REG_INT_STS_EOP_ERROR_SHIFT                                                                1
+  #define PBF_PB2_REG_INT_STS_IFIFO_ERROR                                                                    (0x1<<2) // Instruction FIFO error.
+  #define PBF_PB2_REG_INT_STS_IFIFO_ERROR_SHIFT                                                              2
+  #define PBF_PB2_REG_INT_STS_PFIFO_ERROR                                                                    (0x1<<3) // Parameter FIFO error.
+  #define PBF_PB2_REG_INT_STS_PFIFO_ERROR_SHIFT                                                              3
+  #define PBF_PB2_REG_INT_STS_DB_BUF_ERROR                                                                   (0x1<<4) // DB FIFO error.
+  #define PBF_PB2_REG_INT_STS_DB_BUF_ERROR_SHIFT                                                             4
+  #define PBF_PB2_REG_INT_STS_TH_EXEC_ERROR                                                                  (0x1<<5) // 
+  #define PBF_PB2_REG_INT_STS_TH_EXEC_ERROR_SHIFT                                                            5
+  #define PBF_PB2_REG_INT_STS_TQ_ERROR_WR                                                                    (0x1<<6) // TQ write overflow.
+  #define PBF_PB2_REG_INT_STS_TQ_ERROR_WR_SHIFT                                                              6
+  #define PBF_PB2_REG_INT_STS_TQ_ERROR_RD_TH                                                                 (0x1<<7) // TQ read underflow by task handler.
+  #define PBF_PB2_REG_INT_STS_TQ_ERROR_RD_TH_SHIFT                                                           7
+  #define PBF_PB2_REG_INT_STS_TQ_ERROR_RD_IH                                                                 (0x1<<8) // TQ read underflow by instruction handler.
+  #define PBF_PB2_REG_INT_STS_TQ_ERROR_RD_IH_SHIFT                                                           8
+#define PBF_PB2_REG_INT_MASK                                                                                 0xda4044UL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define PBF_PB2_REG_INT_MASK_ADDRESS_ERROR                                                                 (0x1<<0) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.ADDRESS_ERROR .
+  #define PBF_PB2_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                           0
+  #define PBF_PB2_REG_INT_MASK_EOP_ERROR                                                                     (0x1<<1) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.EOP_ERROR .
+  #define PBF_PB2_REG_INT_MASK_EOP_ERROR_SHIFT                                                               1
+  #define PBF_PB2_REG_INT_MASK_IFIFO_ERROR                                                                   (0x1<<2) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.IFIFO_ERROR .
+  #define PBF_PB2_REG_INT_MASK_IFIFO_ERROR_SHIFT                                                             2
+  #define PBF_PB2_REG_INT_MASK_PFIFO_ERROR                                                                   (0x1<<3) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.PFIFO_ERROR .
+  #define PBF_PB2_REG_INT_MASK_PFIFO_ERROR_SHIFT                                                             3
+  #define PBF_PB2_REG_INT_MASK_DB_BUF_ERROR                                                                  (0x1<<4) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.DB_BUF_ERROR .
+  #define PBF_PB2_REG_INT_MASK_DB_BUF_ERROR_SHIFT                                                            4
+  #define PBF_PB2_REG_INT_MASK_TH_EXEC_ERROR                                                                 (0x1<<5) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TH_EXEC_ERROR .
+  #define PBF_PB2_REG_INT_MASK_TH_EXEC_ERROR_SHIFT                                                           5
+  #define PBF_PB2_REG_INT_MASK_TQ_ERROR_WR                                                                   (0x1<<6) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_WR .
+  #define PBF_PB2_REG_INT_MASK_TQ_ERROR_WR_SHIFT                                                             6
+  #define PBF_PB2_REG_INT_MASK_TQ_ERROR_RD_TH                                                                (0x1<<7) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_RD_TH .
+  #define PBF_PB2_REG_INT_MASK_TQ_ERROR_RD_TH_SHIFT                                                          7
+  #define PBF_PB2_REG_INT_MASK_TQ_ERROR_RD_IH                                                                (0x1<<8) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_RD_IH .
+  #define PBF_PB2_REG_INT_MASK_TQ_ERROR_RD_IH_SHIFT                                                          8
+#define PBF_PB2_REG_INT_STS_WR                                                                               0xda4048UL //Access:WR   DataWidth:0x9    // Multi Field Register.
+  #define PBF_PB2_REG_INT_STS_WR_ADDRESS_ERROR                                                               (0x1<<0) // Signals an unknown address to the rf module.
+  #define PBF_PB2_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                         0
+  #define PBF_PB2_REG_INT_STS_WR_EOP_ERROR                                                                   (0x1<<1) // EOP check error.
+  #define PBF_PB2_REG_INT_STS_WR_EOP_ERROR_SHIFT                                                             1
+  #define PBF_PB2_REG_INT_STS_WR_IFIFO_ERROR                                                                 (0x1<<2) // Instruction FIFO error.
+  #define PBF_PB2_REG_INT_STS_WR_IFIFO_ERROR_SHIFT                                                           2
+  #define PBF_PB2_REG_INT_STS_WR_PFIFO_ERROR                                                                 (0x1<<3) // Parameter FIFO error.
+  #define PBF_PB2_REG_INT_STS_WR_PFIFO_ERROR_SHIFT                                                           3
+  #define PBF_PB2_REG_INT_STS_WR_DB_BUF_ERROR                                                                (0x1<<4) // DB FIFO error.
+  #define PBF_PB2_REG_INT_STS_WR_DB_BUF_ERROR_SHIFT                                                          4
+  #define PBF_PB2_REG_INT_STS_WR_TH_EXEC_ERROR                                                               (0x1<<5) // 
+  #define PBF_PB2_REG_INT_STS_WR_TH_EXEC_ERROR_SHIFT                                                         5
+  #define PBF_PB2_REG_INT_STS_WR_TQ_ERROR_WR                                                                 (0x1<<6) // TQ write overflow.
+  #define PBF_PB2_REG_INT_STS_WR_TQ_ERROR_WR_SHIFT                                                           6
+  #define PBF_PB2_REG_INT_STS_WR_TQ_ERROR_RD_TH                                                              (0x1<<7) // TQ read underflow by task handler.
+  #define PBF_PB2_REG_INT_STS_WR_TQ_ERROR_RD_TH_SHIFT                                                        7
+  #define PBF_PB2_REG_INT_STS_WR_TQ_ERROR_RD_IH                                                              (0x1<<8) // TQ read underflow by instruction handler.
+  #define PBF_PB2_REG_INT_STS_WR_TQ_ERROR_RD_IH_SHIFT                                                        8
+#define PBF_PB2_REG_INT_STS_CLR                                                                              0xda404cUL //Access:RC   DataWidth:0x9    // Multi Field Register.
+  #define PBF_PB2_REG_INT_STS_CLR_ADDRESS_ERROR                                                              (0x1<<0) // Signals an unknown address to the rf module.
+  #define PBF_PB2_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                        0
+  #define PBF_PB2_REG_INT_STS_CLR_EOP_ERROR                                                                  (0x1<<1) // EOP check error.
+  #define PBF_PB2_REG_INT_STS_CLR_EOP_ERROR_SHIFT                                                            1
+  #define PBF_PB2_REG_INT_STS_CLR_IFIFO_ERROR                                                                (0x1<<2) // Instruction FIFO error.
+  #define PBF_PB2_REG_INT_STS_CLR_IFIFO_ERROR_SHIFT                                                          2
+  #define PBF_PB2_REG_INT_STS_CLR_PFIFO_ERROR                                                                (0x1<<3) // Parameter FIFO error.
+  #define PBF_PB2_REG_INT_STS_CLR_PFIFO_ERROR_SHIFT                                                          3
+  #define PBF_PB2_REG_INT_STS_CLR_DB_BUF_ERROR                                                               (0x1<<4) // DB FIFO error.
+  #define PBF_PB2_REG_INT_STS_CLR_DB_BUF_ERROR_SHIFT                                                         4
+  #define PBF_PB2_REG_INT_STS_CLR_TH_EXEC_ERROR                                                              (0x1<<5) // 
+  #define PBF_PB2_REG_INT_STS_CLR_TH_EXEC_ERROR_SHIFT                                                        5
+  #define PBF_PB2_REG_INT_STS_CLR_TQ_ERROR_WR                                                                (0x1<<6) // TQ write overflow.
+  #define PBF_PB2_REG_INT_STS_CLR_TQ_ERROR_WR_SHIFT                                                          6
+  #define PBF_PB2_REG_INT_STS_CLR_TQ_ERROR_RD_TH                                                             (0x1<<7) // TQ read underflow by task handler.
+  #define PBF_PB2_REG_INT_STS_CLR_TQ_ERROR_RD_TH_SHIFT                                                       7
+  #define PBF_PB2_REG_INT_STS_CLR_TQ_ERROR_RD_IH                                                             (0x1<<8) // TQ read underflow by instruction handler.
+  #define PBF_PB2_REG_INT_STS_CLR_TQ_ERROR_RD_IH_SHIFT                                                       8
+#define PBF_PB2_REG_PRTY_MASK                                                                                0xda4054UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define PBF_PB2_REG_PRTY_MASK_DATAPATH_REGISTERS                                                           (0x1<<0) // This bit masks, when set, the Parity bit: PB_REG_PRTY_STS.DATAPATH_REGISTERS .
+  #define PBF_PB2_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                                     0
+#define PBF_PB2_REG_CONTROL                                                                                  0xda4400UL //Access:RW   DataWidth:0xd    // Multi Field Register.
+  #define PBF_PB2_REG_CONTROL_BYTE_ORDER_SWITCH                                                              (0x1<<0) // Indicates if to switch the CRC result byte ordering. 0=don't switch;1=switch.
+  #define PBF_PB2_REG_CONTROL_BYTE_ORDER_SWITCH_SHIFT                                                        0
+  #define PBF_PB2_REG_CONTROL_DB_IGNORE_ERROR                                                                (0x1<<1) // Indicates if to ignore the input error indication.
+  #define PBF_PB2_REG_CONTROL_DB_IGNORE_ERROR_SHIFT                                                          1
+  #define PBF_PB2_REG_CONTROL_DONT_PASS_ERROR                                                                (0x1<<2) // Masks error on output of pb.
+  #define PBF_PB2_REG_CONTROL_DONT_PASS_ERROR_SHIFT                                                          2
+  #define PBF_PB2_REG_CONTROL_EOP_CHECK_DISABLE                                                              (0x1<<3) // Disables EOP check (EOP check verifies that the last Task instruction is accessing a line that has EOP on it. this way one could find mismatches between expected length and actual length on some packet.
+  #define PBF_PB2_REG_CONTROL_EOP_CHECK_DISABLE_SHIFT                                                        3
+  #define PBF_PB2_REG_CONTROL_CRC_COMPARE_DISABLE                                                            (0x1<<4) // Disables CRC2 machine (the machine that is used for comparing actual CRC with a value that is provided to the PB.
+  #define PBF_PB2_REG_CONTROL_CRC_COMPARE_DISABLE_SHIFT                                                      4
+  #define PBF_PB2_REG_CONTROL_EN_INPUTS                                                                      (0x1<<5) // Enable inputs.
+  #define PBF_PB2_REG_CONTROL_EN_INPUTS_SHIFT                                                                5
+  #define PBF_PB2_REG_CONTROL_DISABLE_PB                                                                     (0x1<<6) // Debug only: Disable PB.
+  #define PBF_PB2_REG_CONTROL_DISABLE_PB_SHIFT                                                               6
+  #define PBF_PB2_REG_CONTROL_DEBUG_SELECT                                                                   (0xf<<7) // Obsolete.
+  #define PBF_PB2_REG_CONTROL_DEBUG_SELECT_SHIFT                                                             7
+  #define PBF_PB2_REG_CONTROL_RELAX_TH                                                                       (0x1<<11) // Dbug only.
+  #define PBF_PB2_REG_CONTROL_RELAX_TH_SHIFT                                                                 11
+  #define PBF_PB2_REG_CONTROL_DUMMY_ERR_ALLOW                                                                (0x1<<12) // Dummy ingress error allow.  When cleared, an error received on the ingress interface will be masked for instructions in which the "dummy read" bit is set.
+  #define PBF_PB2_REG_CONTROL_DUMMY_ERR_ALLOW_SHIFT                                                          12
+#define PBF_PB2_REG_CRC_MASK_1_0                                                                             0xda4404UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PBF_PB2_REG_CRC_MASK_1_1                                                                             0xda4408UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PBF_PB2_REG_CRC_MASK_1_2                                                                             0xda440cUL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PBF_PB2_REG_CRC_MASK_1_3                                                                             0xda4410UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PBF_PB2_REG_CRC_MASK_2_0                                                                             0xda4414UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PBF_PB2_REG_CRC_MASK_2_1                                                                             0xda4418UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PBF_PB2_REG_CRC_MASK_2_2                                                                             0xda441cUL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PBF_PB2_REG_CRC_MASK_2_3                                                                             0xda4420UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PBF_PB2_REG_CRC_MASK_3_0                                                                             0xda4424UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PBF_PB2_REG_CRC_MASK_3_1                                                                             0xda4428UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PBF_PB2_REG_CRC_MASK_3_2                                                                             0xda442cUL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PBF_PB2_REG_CRC_MASK_3_3                                                                             0xda4430UL //Access:RW   DataWidth:0x20   // defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])
+#define PBF_PB2_REG_DB_EMPTY                                                                                 0xda4500UL //Access:R    DataWidth:0x1    // Data Buffer empty status.
+#define PBF_PB2_REG_DB_FULL                                                                                  0xda4504UL //Access:R    DataWidth:0x1    // Data Buffer full status.
+#define PBF_PB2_REG_TQ_EMPTY                                                                                 0xda4508UL //Access:R    DataWidth:0x1    // Task Queue empty status.
+#define PBF_PB2_REG_TQ_FULL                                                                                  0xda450cUL //Access:R    DataWidth:0x1    // Task Queue full status.
+#define PBF_PB2_REG_IFIFO_EMPTY                                                                              0xda4510UL //Access:R    DataWidth:0x1    // Instruction FIFO empty status.
+#define PBF_PB2_REG_IFIFO_FULL                                                                               0xda4514UL //Access:R    DataWidth:0x1    // Instruction FIFO full status.
+#define PBF_PB2_REG_PFIFO_EMPTY                                                                              0xda4518UL //Access:R    DataWidth:0x1    // Parameter FIFO empty status.
+#define PBF_PB2_REG_PFIFO_FULL                                                                               0xda451cUL //Access:R    DataWidth:0x1    // Parameter FIFO full status.
+#define PBF_PB2_REG_TQ_TH_EMPTY                                                                              0xda4520UL //Access:R    DataWidth:0x1    // Task Queue empty status for task handler.
+#define PBF_PB2_REG_ERRORED_CRC                                                                              0xda4600UL //Access:R    DataWidth:0x20   // CRC mismatch debug register.  This register stores the calculated CRC value that resulted in the most recent CRC error event.
+#define PBF_PB2_REG_ERRORED_INSTR                                                                            0xda4604UL //Access:R    DataWidth:0x20   // EOP mismatch debug register.  Use this address to read the instruction being executed at the time EOP error is detected. The instruction is aligned with the least significant bit of this register.  Bits 31:29 provide additional information about the instruction.  Bit 31 indicates whether the instruction is valid.  Bit 30 indicates if the instruction is the first instruction in the task.  Bit 29 indicates whether the instruction is the last instruction in the task.
+#define PBF_PB2_REG_ERRORED_HDR_LOW                                                                          0xda4608UL //Access:R    DataWidth:0x20   // EOP mismatch debug register.  Use this address to read the lower 32 bits of the task header being executed at the time EOP error is detected.  The instruction length is not kept and is read as 0.
+#define PBF_PB2_REG_ERRORED_HDR_HIGH                                                                         0xda460cUL //Access:R    DataWidth:0x20   // EOP mismatch debug register.  Use this address to read the upper 32 bits of the task header being executed at the time EOP error is detected.  The task passthrough bit is not kept and is read as 0.
+#define PBF_PB2_REG_ERRORED_LENGTH                                                                           0xda4610UL //Access:R    DataWidth:0x10   // EOP mismatch debug register.  This register provides the number of data bytes remaining to be read from DB at the time of EOP error detection.
+#define PBF_PB2_REG_ECO_RESERVED                                                                             0xda4614UL //Access:RW   DataWidth:0x8    // For future eco.
+#define PBF_PB2_REG_DBG_OUT_DATA                                                                             0xda4700UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PBF_PB2_REG_DBG_OUT_DATA_SIZE                                                                        8
+#define PBF_PB2_REG_DBG_OUT_VALID                                                                            0xda4720UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define PBF_PB2_REG_DBG_OUT_FRAME                                                                            0xda4724UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define PBF_PB2_REG_DBG_SELECT                                                                               0xda4728UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PBF_PB2_REG_DBG_DWORD_ENABLE                                                                         0xda472cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PBF_PB2_REG_DBG_SHIFT                                                                                0xda4730UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PBF_PB2_REG_DBG_FORCE_VALID                                                                          0xda4734UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PBF_PB2_REG_DBG_FORCE_FRAME                                                                          0xda4738UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PBF_PB2_REG_DB_FIFO                                                                                  0xda6000UL //Access:WB_R DataWidth:0x108  // Provides read-only access of the data buffer FIFO. Intended for debug purposes.
+#define PBF_PB2_REG_DB_FIFO_SIZE                                                                             512
+#define PBF_PB2_REG_L1                                                                                       0xda7000UL //Access:WB   DataWidth:0x40   // L1 CRC memory access.
+#define PBF_PB2_REG_L1_SIZE                                                                                  640
+#define BTB_REG_HW_INIT_EN                                                                                   0xdb0004UL //Access:RW   DataWidth:0x2    // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en registers will be done by HW.  Bit 1 - if this bit is set then initialization of BIG RAM will be done by HW. Both bits will be reset by HW when initialization is finished.
+#define BTB_REG_INIT_DONE                                                                                    0xdb0008UL //Access:R    DataWidth:0x2    // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en registers are finished by HW.  Bit 1 - if this bit is set then initialization of BIG RAM is finished by HW.
+#define BTB_REG_START_EN                                                                                     0xdb000cUL //Access:RW   DataWidth:0x1    // This bit should be set when initialization of all BRTB registers and memories is finished. BRTB will fill all prefetch FIFO with free pointers. BRTB will not be able to get packets from write clients when this bit is reset. If link list was configured by HW then this bit will be set by HW.
+#define BTB_REG_INT_STS_0                                                                                    0xdb00c0UL //Access:R    DataWidth:0x1d   // Multi Field Register.
+  #define BTB_REG_INT_STS_0_ADDRESS_ERROR                                                                    (0x1<<0) // Signals an unknown address to the rf module.
+  #define BTB_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                              0
+  #define BTB_REG_INT_STS_0_RC_PKT0_RLS_ERROR                                                                (0x1<<1) // Read packet client NIG main port 0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_0_RC_PKT0_RLS_ERROR_SHIFT                                                          1
+  #define BTB_REG_INT_STS_0_RC_PKT0_LEN_ERROR                                                                (0x1<<3) // Read packet client NIG main port 0 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_0_RC_PKT0_LEN_ERROR_SHIFT                                                          3
+  #define BTB_REG_INT_STS_0_RC_PKT0_PROTOCOL_ERROR                                                           (0x1<<5) // Read packet client NIG main port 0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_0_RC_PKT0_PROTOCOL_ERROR_SHIFT                                                     5
+  #define BTB_REG_INT_STS_0_RC_PKT1_RLS_ERROR                                                                (0x1<<6) // Read packet client NIG LB port 0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_0_RC_PKT1_RLS_ERROR_SHIFT                                                          6
+  #define BTB_REG_INT_STS_0_RC_PKT1_LEN_ERROR                                                                (0x1<<8) // Read packet client NIG LB port 0 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_0_RC_PKT1_LEN_ERROR_SHIFT                                                          8
+  #define BTB_REG_INT_STS_0_RC_PKT1_PROTOCOL_ERROR                                                           (0x1<<10) // Read packet client NIG LB port 0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_0_RC_PKT1_PROTOCOL_ERROR_SHIFT                                                     10
+  #define BTB_REG_INT_STS_0_RC_PKT2_RLS_ERROR                                                                (0x1<<11) // Read packet client NIG main port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_0_RC_PKT2_RLS_ERROR_SHIFT                                                          11
+  #define BTB_REG_INT_STS_0_RC_PKT2_LEN_ERROR                                                                (0x1<<13) // Read packet client NIG main port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_0_RC_PKT2_LEN_ERROR_SHIFT                                                          13
+  #define BTB_REG_INT_STS_0_RC_PKT2_PROTOCOL_ERROR                                                           (0x1<<15) // Read packet client NIG main port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_0_RC_PKT2_PROTOCOL_ERROR_SHIFT                                                     15
+  #define BTB_REG_INT_STS_0_RC_PKT3_RLS_ERROR                                                                (0x1<<16) // Read packet client NIG LB port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_0_RC_PKT3_RLS_ERROR_SHIFT                                                          16
+  #define BTB_REG_INT_STS_0_RC_PKT3_LEN_ERROR                                                                (0x1<<18) // Read packet client NIG LB port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_0_RC_PKT3_LEN_ERROR_SHIFT                                                          18
+  #define BTB_REG_INT_STS_0_RC_PKT3_PROTOCOL_ERROR                                                           (0x1<<20) // Read packet client NIG LB port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_0_RC_PKT3_PROTOCOL_ERROR_SHIFT                                                     20
+  #define BTB_REG_INT_STS_0_RC_SOP_REQ_TC_PORT_ERROR                                                         (0x1<<21) // SOP descriptor request from empty TC or port.
+  #define BTB_REG_INT_STS_0_RC_SOP_REQ_TC_PORT_ERROR_SHIFT                                                   21
+  #define BTB_REG_INT_STS_0_WC0_PROTOCOL_ERROR                                                               (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
+  #define BTB_REG_INT_STS_0_WC0_PROTOCOL_ERROR_SHIFT                                                         23
+  #define BTB_REG_INT_STS_0_LL_BLK_ERROR                                                                     (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
+  #define BTB_REG_INT_STS_0_LL_BLK_ERROR_SHIFT                                                               28
+#define BTB_REG_INT_MASK_0                                                                                   0xdb00c4UL //Access:RW   DataWidth:0x1d   // Multi Field Register.
+  #define BTB_REG_INT_MASK_0_ADDRESS_ERROR                                                                   (0x1<<0) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.ADDRESS_ERROR .
+  #define BTB_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                             0
+  #define BTB_REG_INT_MASK_0_RC_PKT0_RLS_ERROR                                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT0_RLS_ERROR .
+  #define BTB_REG_INT_MASK_0_RC_PKT0_RLS_ERROR_SHIFT                                                         1
+  #define BTB_REG_INT_MASK_0_RC_PKT0_LEN_ERROR                                                               (0x1<<3) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT0_LEN_ERROR .
+  #define BTB_REG_INT_MASK_0_RC_PKT0_LEN_ERROR_SHIFT                                                         3
+  #define BTB_REG_INT_MASK_0_RC_PKT0_PROTOCOL_ERROR                                                          (0x1<<5) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT0_PROTOCOL_ERROR .
+  #define BTB_REG_INT_MASK_0_RC_PKT0_PROTOCOL_ERROR_SHIFT                                                    5
+  #define BTB_REG_INT_MASK_0_RC_PKT1_RLS_ERROR                                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT1_RLS_ERROR .
+  #define BTB_REG_INT_MASK_0_RC_PKT1_RLS_ERROR_SHIFT                                                         6
+  #define BTB_REG_INT_MASK_0_RC_PKT1_LEN_ERROR                                                               (0x1<<8) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT1_LEN_ERROR .
+  #define BTB_REG_INT_MASK_0_RC_PKT1_LEN_ERROR_SHIFT                                                         8
+  #define BTB_REG_INT_MASK_0_RC_PKT1_PROTOCOL_ERROR                                                          (0x1<<10) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT1_PROTOCOL_ERROR .
+  #define BTB_REG_INT_MASK_0_RC_PKT1_PROTOCOL_ERROR_SHIFT                                                    10
+  #define BTB_REG_INT_MASK_0_RC_PKT2_RLS_ERROR                                                               (0x1<<11) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT2_RLS_ERROR .
+  #define BTB_REG_INT_MASK_0_RC_PKT2_RLS_ERROR_SHIFT                                                         11
+  #define BTB_REG_INT_MASK_0_RC_PKT2_LEN_ERROR                                                               (0x1<<13) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT2_LEN_ERROR .
+  #define BTB_REG_INT_MASK_0_RC_PKT2_LEN_ERROR_SHIFT                                                         13
+  #define BTB_REG_INT_MASK_0_RC_PKT2_PROTOCOL_ERROR                                                          (0x1<<15) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT2_PROTOCOL_ERROR .
+  #define BTB_REG_INT_MASK_0_RC_PKT2_PROTOCOL_ERROR_SHIFT                                                    15
+  #define BTB_REG_INT_MASK_0_RC_PKT3_RLS_ERROR                                                               (0x1<<16) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT3_RLS_ERROR .
+  #define BTB_REG_INT_MASK_0_RC_PKT3_RLS_ERROR_SHIFT                                                         16
+  #define BTB_REG_INT_MASK_0_RC_PKT3_LEN_ERROR                                                               (0x1<<18) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT3_LEN_ERROR .
+  #define BTB_REG_INT_MASK_0_RC_PKT3_LEN_ERROR_SHIFT                                                         18
+  #define BTB_REG_INT_MASK_0_RC_PKT3_PROTOCOL_ERROR                                                          (0x1<<20) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT3_PROTOCOL_ERROR .
+  #define BTB_REG_INT_MASK_0_RC_PKT3_PROTOCOL_ERROR_SHIFT                                                    20
+  #define BTB_REG_INT_MASK_0_RC_SOP_REQ_TC_PORT_ERROR                                                        (0x1<<21) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_SOP_REQ_TC_PORT_ERROR .
+  #define BTB_REG_INT_MASK_0_RC_SOP_REQ_TC_PORT_ERROR_SHIFT                                                  21
+  #define BTB_REG_INT_MASK_0_WC0_PROTOCOL_ERROR                                                              (0x1<<23) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.WC0_PROTOCOL_ERROR .
+  #define BTB_REG_INT_MASK_0_WC0_PROTOCOL_ERROR_SHIFT                                                        23
+  #define BTB_REG_INT_MASK_0_LL_BLK_ERROR                                                                    (0x1<<28) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.LL_BLK_ERROR .
+  #define BTB_REG_INT_MASK_0_LL_BLK_ERROR_SHIFT                                                              28
+#define BTB_REG_INT_STS_WR_0                                                                                 0xdb00c8UL //Access:WR   DataWidth:0x1d   // Multi Field Register.
+  #define BTB_REG_INT_STS_WR_0_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define BTB_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                           0
+  #define BTB_REG_INT_STS_WR_0_RC_PKT0_RLS_ERROR                                                             (0x1<<1) // Read packet client NIG main port 0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_WR_0_RC_PKT0_RLS_ERROR_SHIFT                                                       1
+  #define BTB_REG_INT_STS_WR_0_RC_PKT0_LEN_ERROR                                                             (0x1<<3) // Read packet client NIG main port 0 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_WR_0_RC_PKT0_LEN_ERROR_SHIFT                                                       3
+  #define BTB_REG_INT_STS_WR_0_RC_PKT0_PROTOCOL_ERROR                                                        (0x1<<5) // Read packet client NIG main port 0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_WR_0_RC_PKT0_PROTOCOL_ERROR_SHIFT                                                  5
+  #define BTB_REG_INT_STS_WR_0_RC_PKT1_RLS_ERROR                                                             (0x1<<6) // Read packet client NIG LB port 0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_WR_0_RC_PKT1_RLS_ERROR_SHIFT                                                       6
+  #define BTB_REG_INT_STS_WR_0_RC_PKT1_LEN_ERROR                                                             (0x1<<8) // Read packet client NIG LB port 0 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_WR_0_RC_PKT1_LEN_ERROR_SHIFT                                                       8
+  #define BTB_REG_INT_STS_WR_0_RC_PKT1_PROTOCOL_ERROR                                                        (0x1<<10) // Read packet client NIG LB port 0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_WR_0_RC_PKT1_PROTOCOL_ERROR_SHIFT                                                  10
+  #define BTB_REG_INT_STS_WR_0_RC_PKT2_RLS_ERROR                                                             (0x1<<11) // Read packet client NIG main port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_WR_0_RC_PKT2_RLS_ERROR_SHIFT                                                       11
+  #define BTB_REG_INT_STS_WR_0_RC_PKT2_LEN_ERROR                                                             (0x1<<13) // Read packet client NIG main port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_WR_0_RC_PKT2_LEN_ERROR_SHIFT                                                       13
+  #define BTB_REG_INT_STS_WR_0_RC_PKT2_PROTOCOL_ERROR                                                        (0x1<<15) // Read packet client NIG main port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_WR_0_RC_PKT2_PROTOCOL_ERROR_SHIFT                                                  15
+  #define BTB_REG_INT_STS_WR_0_RC_PKT3_RLS_ERROR                                                             (0x1<<16) // Read packet client NIG LB port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_WR_0_RC_PKT3_RLS_ERROR_SHIFT                                                       16
+  #define BTB_REG_INT_STS_WR_0_RC_PKT3_LEN_ERROR                                                             (0x1<<18) // Read packet client NIG LB port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_WR_0_RC_PKT3_LEN_ERROR_SHIFT                                                       18
+  #define BTB_REG_INT_STS_WR_0_RC_PKT3_PROTOCOL_ERROR                                                        (0x1<<20) // Read packet client NIG LB port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_WR_0_RC_PKT3_PROTOCOL_ERROR_SHIFT                                                  20
+  #define BTB_REG_INT_STS_WR_0_RC_SOP_REQ_TC_PORT_ERROR                                                      (0x1<<21) // SOP descriptor request from empty TC or port.
+  #define BTB_REG_INT_STS_WR_0_RC_SOP_REQ_TC_PORT_ERROR_SHIFT                                                21
+  #define BTB_REG_INT_STS_WR_0_WC0_PROTOCOL_ERROR                                                            (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
+  #define BTB_REG_INT_STS_WR_0_WC0_PROTOCOL_ERROR_SHIFT                                                      23
+  #define BTB_REG_INT_STS_WR_0_LL_BLK_ERROR                                                                  (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
+  #define BTB_REG_INT_STS_WR_0_LL_BLK_ERROR_SHIFT                                                            28
+#define BTB_REG_INT_STS_CLR_0                                                                                0xdb00ccUL //Access:RC   DataWidth:0x1d   // Multi Field Register.
+  #define BTB_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define BTB_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                          0
+  #define BTB_REG_INT_STS_CLR_0_RC_PKT0_RLS_ERROR                                                            (0x1<<1) // Read packet client NIG main port 0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_0_RC_PKT0_RLS_ERROR_SHIFT                                                      1
+  #define BTB_REG_INT_STS_CLR_0_RC_PKT0_LEN_ERROR                                                            (0x1<<3) // Read packet client NIG main port 0 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_0_RC_PKT0_LEN_ERROR_SHIFT                                                      3
+  #define BTB_REG_INT_STS_CLR_0_RC_PKT0_PROTOCOL_ERROR                                                       (0x1<<5) // Read packet client NIG main port 0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_0_RC_PKT0_PROTOCOL_ERROR_SHIFT                                                 5
+  #define BTB_REG_INT_STS_CLR_0_RC_PKT1_RLS_ERROR                                                            (0x1<<6) // Read packet client NIG LB port 0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_0_RC_PKT1_RLS_ERROR_SHIFT                                                      6
+  #define BTB_REG_INT_STS_CLR_0_RC_PKT1_LEN_ERROR                                                            (0x1<<8) // Read packet client NIG LB port 0 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_0_RC_PKT1_LEN_ERROR_SHIFT                                                      8
+  #define BTB_REG_INT_STS_CLR_0_RC_PKT1_PROTOCOL_ERROR                                                       (0x1<<10) // Read packet client NIG LB port 0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_0_RC_PKT1_PROTOCOL_ERROR_SHIFT                                                 10
+  #define BTB_REG_INT_STS_CLR_0_RC_PKT2_RLS_ERROR                                                            (0x1<<11) // Read packet client NIG main port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_0_RC_PKT2_RLS_ERROR_SHIFT                                                      11
+  #define BTB_REG_INT_STS_CLR_0_RC_PKT2_LEN_ERROR                                                            (0x1<<13) // Read packet client NIG main port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_0_RC_PKT2_LEN_ERROR_SHIFT                                                      13
+  #define BTB_REG_INT_STS_CLR_0_RC_PKT2_PROTOCOL_ERROR                                                       (0x1<<15) // Read packet client NIG main port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_0_RC_PKT2_PROTOCOL_ERROR_SHIFT                                                 15
+  #define BTB_REG_INT_STS_CLR_0_RC_PKT3_RLS_ERROR                                                            (0x1<<16) // Read packet client NIG LB port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_CLR_0_RC_PKT3_RLS_ERROR_SHIFT                                                      16
+  #define BTB_REG_INT_STS_CLR_0_RC_PKT3_LEN_ERROR                                                            (0x1<<18) // Read packet client NIG LB port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_CLR_0_RC_PKT3_LEN_ERROR_SHIFT                                                      18
+  #define BTB_REG_INT_STS_CLR_0_RC_PKT3_PROTOCOL_ERROR                                                       (0x1<<20) // Read packet client NIG LB port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_CLR_0_RC_PKT3_PROTOCOL_ERROR_SHIFT                                                 20
+  #define BTB_REG_INT_STS_CLR_0_RC_SOP_REQ_TC_PORT_ERROR                                                     (0x1<<21) // SOP descriptor request from empty TC or port.
+  #define BTB_REG_INT_STS_CLR_0_RC_SOP_REQ_TC_PORT_ERROR_SHIFT                                               21
+  #define BTB_REG_INT_STS_CLR_0_WC0_PROTOCOL_ERROR                                                           (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
+  #define BTB_REG_INT_STS_CLR_0_WC0_PROTOCOL_ERROR_SHIFT                                                     23
+  #define BTB_REG_INT_STS_CLR_0_LL_BLK_ERROR                                                                 (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
+  #define BTB_REG_INT_STS_CLR_0_LL_BLK_ERROR_SHIFT                                                           28
+#define BTB_REG_INT_STS_1                                                                                    0xdb00d8UL //Access:R    DataWidth:0x12   // Multi Field Register.
+  #define BTB_REG_INT_STS_1_LL_ARB_CALC_ERROR                                                                (0x1<<1) // Calculations error in LL arbiter block.
+  #define BTB_REG_INT_STS_1_LL_ARB_CALC_ERROR_SHIFT                                                          1
+  #define BTB_REG_INT_STS_1_FC_ALM_CALC_ERROR                                                                (0x1<<2) // Calculations error in almost full counter block ALM_FULL_EN::/ALM_FULL_EN/d in Comments.
+  #define BTB_REG_INT_STS_1_FC_ALM_CALC_ERROR_SHIFT                                                          2
+  #define BTB_REG_INT_STS_1_WC0_INP_FIFO_ERROR                                                               (0x1<<3) // Input FIFO error in write client 0.
+  #define BTB_REG_INT_STS_1_WC0_INP_FIFO_ERROR_SHIFT                                                         3
+  #define BTB_REG_INT_STS_1_WC0_SOP_FIFO_ERROR                                                               (0x1<<4) // SOP FIFO error in write client 0.
+  #define BTB_REG_INT_STS_1_WC0_SOP_FIFO_ERROR_SHIFT                                                         4
+  #define BTB_REG_INT_STS_1_WC0_LEN_FIFO_ERROR                                                               (0x1<<5) // LEN FIFO error in write client 0.
+  #define BTB_REG_INT_STS_1_WC0_LEN_FIFO_ERROR_SHIFT                                                         5
+  #define BTB_REG_INT_STS_1_WC0_EOP_FIFO_ERROR                                                               (0x1<<6) // EOP FIFO error in write client 0.
+  #define BTB_REG_INT_STS_1_WC0_EOP_FIFO_ERROR_SHIFT                                                         6
+  #define BTB_REG_INT_STS_1_WC0_QUEUE_FIFO_ERROR                                                             (0x1<<7) // Queue FIFO error in write client 0.
+  #define BTB_REG_INT_STS_1_WC0_QUEUE_FIFO_ERROR_SHIFT                                                       7
+  #define BTB_REG_INT_STS_1_WC0_FREE_POINT_FIFO_ERROR                                                        (0x1<<8) // Free ointer FIFO error in write client 0.
+  #define BTB_REG_INT_STS_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT                                                  8
+  #define BTB_REG_INT_STS_1_WC0_NEXT_POINT_FIFO_ERROR                                                        (0x1<<9) // Next pointer FIFO error in write client 0.
+  #define BTB_REG_INT_STS_1_WC0_NEXT_POINT_FIFO_ERROR_SHIFT                                                  9
+  #define BTB_REG_INT_STS_1_WC0_STRT_FIFO_ERROR                                                              (0x1<<10) // Start FIFO error in write client 0.
+  #define BTB_REG_INT_STS_1_WC0_STRT_FIFO_ERROR_SHIFT                                                        10
+  #define BTB_REG_INT_STS_1_WC0_SECOND_DSCR_FIFO_ERROR                                                       (0x1<<11) // Second descriptor FIFO error in write client 0.
+  #define BTB_REG_INT_STS_1_WC0_SECOND_DSCR_FIFO_ERROR_SHIFT                                                 11
+  #define BTB_REG_INT_STS_1_WC0_PKT_AVAIL_FIFO_ERROR                                                         (0x1<<12) // Packet available FIFO error in write client 0.
+  #define BTB_REG_INT_STS_1_WC0_PKT_AVAIL_FIFO_ERROR_SHIFT                                                   12
+  #define BTB_REG_INT_STS_1_WC0_NOTIFY_FIFO_ERROR                                                            (0x1<<14) // Notify FIFO error in write client 0.
+  #define BTB_REG_INT_STS_1_WC0_NOTIFY_FIFO_ERROR_SHIFT                                                      14
+  #define BTB_REG_INT_STS_1_WC0_LL_REQ_FIFO_ERROR                                                            (0x1<<15) // LL req error in write client 0.
+  #define BTB_REG_INT_STS_1_WC0_LL_REQ_FIFO_ERROR_SHIFT                                                      15
+  #define BTB_REG_INT_STS_1_WC0_LL_PA_CNT_ERROR                                                              (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
+  #define BTB_REG_INT_STS_1_WC0_LL_PA_CNT_ERROR_SHIFT                                                        16
+  #define BTB_REG_INT_STS_1_WC0_BB_PA_CNT_ERROR                                                              (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
+  #define BTB_REG_INT_STS_1_WC0_BB_PA_CNT_ERROR_SHIFT                                                        17
+#define BTB_REG_INT_MASK_1                                                                                   0xdb00dcUL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define BTB_REG_INT_MASK_1_LL_ARB_CALC_ERROR                                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.LL_ARB_CALC_ERROR .
+  #define BTB_REG_INT_MASK_1_LL_ARB_CALC_ERROR_SHIFT                                                         1
+  #define BTB_REG_INT_MASK_1_FC_ALM_CALC_ERROR                                                               (0x1<<2) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.FC_ALM_CALC_ERROR .
+  #define BTB_REG_INT_MASK_1_FC_ALM_CALC_ERROR_SHIFT                                                         2
+  #define BTB_REG_INT_MASK_1_WC0_INP_FIFO_ERROR                                                              (0x1<<3) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_INP_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_1_WC0_INP_FIFO_ERROR_SHIFT                                                        3
+  #define BTB_REG_INT_MASK_1_WC0_SOP_FIFO_ERROR                                                              (0x1<<4) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_SOP_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_1_WC0_SOP_FIFO_ERROR_SHIFT                                                        4
+  #define BTB_REG_INT_MASK_1_WC0_LEN_FIFO_ERROR                                                              (0x1<<5) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_LEN_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_1_WC0_LEN_FIFO_ERROR_SHIFT                                                        5
+  #define BTB_REG_INT_MASK_1_WC0_EOP_FIFO_ERROR                                                              (0x1<<6) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_EOP_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_1_WC0_EOP_FIFO_ERROR_SHIFT                                                        6
+  #define BTB_REG_INT_MASK_1_WC0_QUEUE_FIFO_ERROR                                                            (0x1<<7) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_QUEUE_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_1_WC0_QUEUE_FIFO_ERROR_SHIFT                                                      7
+  #define BTB_REG_INT_MASK_1_WC0_FREE_POINT_FIFO_ERROR                                                       (0x1<<8) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_FREE_POINT_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT                                                 8
+  #define BTB_REG_INT_MASK_1_WC0_NEXT_POINT_FIFO_ERROR                                                       (0x1<<9) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_NEXT_POINT_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_1_WC0_NEXT_POINT_FIFO_ERROR_SHIFT                                                 9
+  #define BTB_REG_INT_MASK_1_WC0_STRT_FIFO_ERROR                                                             (0x1<<10) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_STRT_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_1_WC0_STRT_FIFO_ERROR_SHIFT                                                       10
+  #define BTB_REG_INT_MASK_1_WC0_SECOND_DSCR_FIFO_ERROR                                                      (0x1<<11) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_SECOND_DSCR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_1_WC0_SECOND_DSCR_FIFO_ERROR_SHIFT                                                11
+  #define BTB_REG_INT_MASK_1_WC0_PKT_AVAIL_FIFO_ERROR                                                        (0x1<<12) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_PKT_AVAIL_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_1_WC0_PKT_AVAIL_FIFO_ERROR_SHIFT                                                  12
+  #define BTB_REG_INT_MASK_1_WC0_NOTIFY_FIFO_ERROR                                                           (0x1<<14) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_NOTIFY_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_1_WC0_NOTIFY_FIFO_ERROR_SHIFT                                                     14
+  #define BTB_REG_INT_MASK_1_WC0_LL_REQ_FIFO_ERROR                                                           (0x1<<15) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_LL_REQ_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_1_WC0_LL_REQ_FIFO_ERROR_SHIFT                                                     15
+  #define BTB_REG_INT_MASK_1_WC0_LL_PA_CNT_ERROR                                                             (0x1<<16) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_LL_PA_CNT_ERROR .
+  #define BTB_REG_INT_MASK_1_WC0_LL_PA_CNT_ERROR_SHIFT                                                       16
+  #define BTB_REG_INT_MASK_1_WC0_BB_PA_CNT_ERROR                                                             (0x1<<17) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_BB_PA_CNT_ERROR .
+  #define BTB_REG_INT_MASK_1_WC0_BB_PA_CNT_ERROR_SHIFT                                                       17
+#define BTB_REG_INT_STS_WR_1                                                                                 0xdb00e0UL //Access:WR   DataWidth:0x12   // Multi Field Register.
+  #define BTB_REG_INT_STS_WR_1_LL_ARB_CALC_ERROR                                                             (0x1<<1) // Calculations error in LL arbiter block.
+  #define BTB_REG_INT_STS_WR_1_LL_ARB_CALC_ERROR_SHIFT                                                       1
+  #define BTB_REG_INT_STS_WR_1_FC_ALM_CALC_ERROR                                                             (0x1<<2) // Calculations error in almost full counter block ALM_FULL_EN::/ALM_FULL_EN/d in Comments.
+  #define BTB_REG_INT_STS_WR_1_FC_ALM_CALC_ERROR_SHIFT                                                       2
+  #define BTB_REG_INT_STS_WR_1_WC0_INP_FIFO_ERROR                                                            (0x1<<3) // Input FIFO error in write client 0.
+  #define BTB_REG_INT_STS_WR_1_WC0_INP_FIFO_ERROR_SHIFT                                                      3
+  #define BTB_REG_INT_STS_WR_1_WC0_SOP_FIFO_ERROR                                                            (0x1<<4) // SOP FIFO error in write client 0.
+  #define BTB_REG_INT_STS_WR_1_WC0_SOP_FIFO_ERROR_SHIFT                                                      4
+  #define BTB_REG_INT_STS_WR_1_WC0_LEN_FIFO_ERROR                                                            (0x1<<5) // LEN FIFO error in write client 0.
+  #define BTB_REG_INT_STS_WR_1_WC0_LEN_FIFO_ERROR_SHIFT                                                      5
+  #define BTB_REG_INT_STS_WR_1_WC0_EOP_FIFO_ERROR                                                            (0x1<<6) // EOP FIFO error in write client 0.
+  #define BTB_REG_INT_STS_WR_1_WC0_EOP_FIFO_ERROR_SHIFT                                                      6
+  #define BTB_REG_INT_STS_WR_1_WC0_QUEUE_FIFO_ERROR                                                          (0x1<<7) // Queue FIFO error in write client 0.
+  #define BTB_REG_INT_STS_WR_1_WC0_QUEUE_FIFO_ERROR_SHIFT                                                    7
+  #define BTB_REG_INT_STS_WR_1_WC0_FREE_POINT_FIFO_ERROR                                                     (0x1<<8) // Free ointer FIFO error in write client 0.
+  #define BTB_REG_INT_STS_WR_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT                                               8
+  #define BTB_REG_INT_STS_WR_1_WC0_NEXT_POINT_FIFO_ERROR                                                     (0x1<<9) // Next pointer FIFO error in write client 0.
+  #define BTB_REG_INT_STS_WR_1_WC0_NEXT_POINT_FIFO_ERROR_SHIFT                                               9
+  #define BTB_REG_INT_STS_WR_1_WC0_STRT_FIFO_ERROR                                                           (0x1<<10) // Start FIFO error in write client 0.
+  #define BTB_REG_INT_STS_WR_1_WC0_STRT_FIFO_ERROR_SHIFT                                                     10
+  #define BTB_REG_INT_STS_WR_1_WC0_SECOND_DSCR_FIFO_ERROR                                                    (0x1<<11) // Second descriptor FIFO error in write client 0.
+  #define BTB_REG_INT_STS_WR_1_WC0_SECOND_DSCR_FIFO_ERROR_SHIFT                                              11
+  #define BTB_REG_INT_STS_WR_1_WC0_PKT_AVAIL_FIFO_ERROR                                                      (0x1<<12) // Packet available FIFO error in write client 0.
+  #define BTB_REG_INT_STS_WR_1_WC0_PKT_AVAIL_FIFO_ERROR_SHIFT                                                12
+  #define BTB_REG_INT_STS_WR_1_WC0_NOTIFY_FIFO_ERROR                                                         (0x1<<14) // Notify FIFO error in write client 0.
+  #define BTB_REG_INT_STS_WR_1_WC0_NOTIFY_FIFO_ERROR_SHIFT                                                   14
+  #define BTB_REG_INT_STS_WR_1_WC0_LL_REQ_FIFO_ERROR                                                         (0x1<<15) // LL req error in write client 0.
+  #define BTB_REG_INT_STS_WR_1_WC0_LL_REQ_FIFO_ERROR_SHIFT                                                   15
+  #define BTB_REG_INT_STS_WR_1_WC0_LL_PA_CNT_ERROR                                                           (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
+  #define BTB_REG_INT_STS_WR_1_WC0_LL_PA_CNT_ERROR_SHIFT                                                     16
+  #define BTB_REG_INT_STS_WR_1_WC0_BB_PA_CNT_ERROR                                                           (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
+  #define BTB_REG_INT_STS_WR_1_WC0_BB_PA_CNT_ERROR_SHIFT                                                     17
+#define BTB_REG_INT_STS_CLR_1                                                                                0xdb00e4UL //Access:RC   DataWidth:0x12   // Multi Field Register.
+  #define BTB_REG_INT_STS_CLR_1_LL_ARB_CALC_ERROR                                                            (0x1<<1) // Calculations error in LL arbiter block.
+  #define BTB_REG_INT_STS_CLR_1_LL_ARB_CALC_ERROR_SHIFT                                                      1
+  #define BTB_REG_INT_STS_CLR_1_FC_ALM_CALC_ERROR                                                            (0x1<<2) // Calculations error in almost full counter block ALM_FULL_EN::/ALM_FULL_EN/d in Comments.
+  #define BTB_REG_INT_STS_CLR_1_FC_ALM_CALC_ERROR_SHIFT                                                      2
+  #define BTB_REG_INT_STS_CLR_1_WC0_INP_FIFO_ERROR                                                           (0x1<<3) // Input FIFO error in write client 0.
+  #define BTB_REG_INT_STS_CLR_1_WC0_INP_FIFO_ERROR_SHIFT                                                     3
+  #define BTB_REG_INT_STS_CLR_1_WC0_SOP_FIFO_ERROR                                                           (0x1<<4) // SOP FIFO error in write client 0.
+  #define BTB_REG_INT_STS_CLR_1_WC0_SOP_FIFO_ERROR_SHIFT                                                     4
+  #define BTB_REG_INT_STS_CLR_1_WC0_LEN_FIFO_ERROR                                                           (0x1<<5) // LEN FIFO error in write client 0.
+  #define BTB_REG_INT_STS_CLR_1_WC0_LEN_FIFO_ERROR_SHIFT                                                     5
+  #define BTB_REG_INT_STS_CLR_1_WC0_EOP_FIFO_ERROR                                                           (0x1<<6) // EOP FIFO error in write client 0.
+  #define BTB_REG_INT_STS_CLR_1_WC0_EOP_FIFO_ERROR_SHIFT                                                     6
+  #define BTB_REG_INT_STS_CLR_1_WC0_QUEUE_FIFO_ERROR                                                         (0x1<<7) // Queue FIFO error in write client 0.
+  #define BTB_REG_INT_STS_CLR_1_WC0_QUEUE_FIFO_ERROR_SHIFT                                                   7
+  #define BTB_REG_INT_STS_CLR_1_WC0_FREE_POINT_FIFO_ERROR                                                    (0x1<<8) // Free ointer FIFO error in write client 0.
+  #define BTB_REG_INT_STS_CLR_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT                                              8
+  #define BTB_REG_INT_STS_CLR_1_WC0_NEXT_POINT_FIFO_ERROR                                                    (0x1<<9) // Next pointer FIFO error in write client 0.
+  #define BTB_REG_INT_STS_CLR_1_WC0_NEXT_POINT_FIFO_ERROR_SHIFT                                              9
+  #define BTB_REG_INT_STS_CLR_1_WC0_STRT_FIFO_ERROR                                                          (0x1<<10) // Start FIFO error in write client 0.
+  #define BTB_REG_INT_STS_CLR_1_WC0_STRT_FIFO_ERROR_SHIFT                                                    10
+  #define BTB_REG_INT_STS_CLR_1_WC0_SECOND_DSCR_FIFO_ERROR                                                   (0x1<<11) // Second descriptor FIFO error in write client 0.
+  #define BTB_REG_INT_STS_CLR_1_WC0_SECOND_DSCR_FIFO_ERROR_SHIFT                                             11
+  #define BTB_REG_INT_STS_CLR_1_WC0_PKT_AVAIL_FIFO_ERROR                                                     (0x1<<12) // Packet available FIFO error in write client 0.
+  #define BTB_REG_INT_STS_CLR_1_WC0_PKT_AVAIL_FIFO_ERROR_SHIFT                                               12
+  #define BTB_REG_INT_STS_CLR_1_WC0_NOTIFY_FIFO_ERROR                                                        (0x1<<14) // Notify FIFO error in write client 0.
+  #define BTB_REG_INT_STS_CLR_1_WC0_NOTIFY_FIFO_ERROR_SHIFT                                                  14
+  #define BTB_REG_INT_STS_CLR_1_WC0_LL_REQ_FIFO_ERROR                                                        (0x1<<15) // LL req error in write client 0.
+  #define BTB_REG_INT_STS_CLR_1_WC0_LL_REQ_FIFO_ERROR_SHIFT                                                  15
+  #define BTB_REG_INT_STS_CLR_1_WC0_LL_PA_CNT_ERROR                                                          (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
+  #define BTB_REG_INT_STS_CLR_1_WC0_LL_PA_CNT_ERROR_SHIFT                                                    16
+  #define BTB_REG_INT_STS_CLR_1_WC0_BB_PA_CNT_ERROR                                                          (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
+  #define BTB_REG_INT_STS_CLR_1_WC0_BB_PA_CNT_ERROR_SHIFT                                                    17
+#define BTB_REG_INT_STS_2                                                                                    0xdb00f0UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define BTB_REG_INT_STS_2_WC_DUP_UPD_DATA_FIFO_ERROR                                                       (0x1<<28) // Updated data FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
+  #define BTB_REG_INT_STS_2_WC_DUP_UPD_DATA_FIFO_ERROR_SHIFT                                                 28
+  #define BTB_REG_INT_STS_2_WC_DUP_RSP_DSCR_FIFO_ERROR                                                       (0x1<<29) // Response descriptor FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
+  #define BTB_REG_INT_STS_2_WC_DUP_RSP_DSCR_FIFO_ERROR_SHIFT                                                 29
+  #define BTB_REG_INT_STS_2_WC_DUP_UPD_POINT_FIFO_ERROR                                                      (0x1<<30) // Updated pointer FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
+  #define BTB_REG_INT_STS_2_WC_DUP_UPD_POINT_FIFO_ERROR_SHIFT                                                30
+  #define BTB_REG_INT_STS_2_WC_DUP_PKT_AVAIL_FIFO_ERROR                                                      (0x1<<31) // Packet available FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
+  #define BTB_REG_INT_STS_2_WC_DUP_PKT_AVAIL_FIFO_ERROR_SHIFT                                                31
+#define BTB_REG_INT_MASK_2                                                                                   0xdb00f4UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define BTB_REG_INT_MASK_2_WC_DUP_UPD_DATA_FIFO_ERROR                                                      (0x1<<28) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_2.WC_DUP_UPD_DATA_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_2_WC_DUP_UPD_DATA_FIFO_ERROR_SHIFT                                                28
+  #define BTB_REG_INT_MASK_2_WC_DUP_RSP_DSCR_FIFO_ERROR                                                      (0x1<<29) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_2.WC_DUP_RSP_DSCR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_2_WC_DUP_RSP_DSCR_FIFO_ERROR_SHIFT                                                29
+  #define BTB_REG_INT_MASK_2_WC_DUP_UPD_POINT_FIFO_ERROR                                                     (0x1<<30) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_2.WC_DUP_UPD_POINT_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_2_WC_DUP_UPD_POINT_FIFO_ERROR_SHIFT                                               30
+  #define BTB_REG_INT_MASK_2_WC_DUP_PKT_AVAIL_FIFO_ERROR                                                     (0x1<<31) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_2.WC_DUP_PKT_AVAIL_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_2_WC_DUP_PKT_AVAIL_FIFO_ERROR_SHIFT                                               31
+#define BTB_REG_INT_STS_WR_2                                                                                 0xdb00f8UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define BTB_REG_INT_STS_WR_2_WC_DUP_UPD_DATA_FIFO_ERROR                                                    (0x1<<28) // Updated data FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
+  #define BTB_REG_INT_STS_WR_2_WC_DUP_UPD_DATA_FIFO_ERROR_SHIFT                                              28
+  #define BTB_REG_INT_STS_WR_2_WC_DUP_RSP_DSCR_FIFO_ERROR                                                    (0x1<<29) // Response descriptor FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
+  #define BTB_REG_INT_STS_WR_2_WC_DUP_RSP_DSCR_FIFO_ERROR_SHIFT                                              29
+  #define BTB_REG_INT_STS_WR_2_WC_DUP_UPD_POINT_FIFO_ERROR                                                   (0x1<<30) // Updated pointer FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
+  #define BTB_REG_INT_STS_WR_2_WC_DUP_UPD_POINT_FIFO_ERROR_SHIFT                                             30
+  #define BTB_REG_INT_STS_WR_2_WC_DUP_PKT_AVAIL_FIFO_ERROR                                                   (0x1<<31) // Packet available FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
+  #define BTB_REG_INT_STS_WR_2_WC_DUP_PKT_AVAIL_FIFO_ERROR_SHIFT                                             31
+#define BTB_REG_INT_STS_CLR_2                                                                                0xdb00fcUL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define BTB_REG_INT_STS_CLR_2_WC_DUP_UPD_DATA_FIFO_ERROR                                                   (0x1<<28) // Updated data FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
+  #define BTB_REG_INT_STS_CLR_2_WC_DUP_UPD_DATA_FIFO_ERROR_SHIFT                                             28
+  #define BTB_REG_INT_STS_CLR_2_WC_DUP_RSP_DSCR_FIFO_ERROR                                                   (0x1<<29) // Response descriptor FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
+  #define BTB_REG_INT_STS_CLR_2_WC_DUP_RSP_DSCR_FIFO_ERROR_SHIFT                                             29
+  #define BTB_REG_INT_STS_CLR_2_WC_DUP_UPD_POINT_FIFO_ERROR                                                  (0x1<<30) // Updated pointer FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
+  #define BTB_REG_INT_STS_CLR_2_WC_DUP_UPD_POINT_FIFO_ERROR_SHIFT                                            30
+  #define BTB_REG_INT_STS_CLR_2_WC_DUP_PKT_AVAIL_FIFO_ERROR                                                  (0x1<<31) // Packet available FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
+  #define BTB_REG_INT_STS_CLR_2_WC_DUP_PKT_AVAIL_FIFO_ERROR_SHIFT                                            31
+#define BTB_REG_INT_STS_3                                                                                    0xdb0108UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define BTB_REG_INT_STS_3_WC_DUP_PKT_AVAIL_CNT_ERROR                                                       (0x1<<0) // Packet available counter overflow or underflow in duplicated write client DUP_EN::/DUP_EN/d in Comments.
+  #define BTB_REG_INT_STS_3_WC_DUP_PKT_AVAIL_CNT_ERROR_SHIFT                                                 0
+  #define BTB_REG_INT_STS_3_RC_PKT0_SIDE_FIFO_ERROR                                                          (0x1<<1) // Read packet client NIG main port 0 side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT                                                    1
+  #define BTB_REG_INT_STS_3_RC_PKT0_REQ_FIFO_ERROR                                                           (0x1<<2) // Read packet client NIG main port 0 request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT0_REQ_FIFO_ERROR_SHIFT                                                     2
+  #define BTB_REG_INT_STS_3_RC_PKT0_BLK_FIFO_ERROR                                                           (0x1<<3) // Read packet client NIG main port 0 block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT                                                     3
+  #define BTB_REG_INT_STS_3_RC_PKT0_RLS_LEFT_FIFO_ERROR                                                      (0x1<<4) // Read packet client NIG main port 0 releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT0_RLS_LEFT_FIFO_ERROR_SHIFT                                                4
+  #define BTB_REG_INT_STS_3_RC_PKT0_STRT_PTR_FIFO_ERROR                                                      (0x1<<5) // Read packet client NIG main port 0 start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT0_STRT_PTR_FIFO_ERROR_SHIFT                                                5
+  #define BTB_REG_INT_STS_3_RC_PKT0_SECOND_PTR_FIFO_ERROR                                                    (0x1<<6) // Read packet client NIG main port 0 second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT0_SECOND_PTR_FIFO_ERROR_SHIFT                                              6
+  #define BTB_REG_INT_STS_3_RC_PKT0_RSP_FIFO_ERROR                                                           (0x1<<7) // Read packet client NIG main port 0 response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT                                                     7
+  #define BTB_REG_INT_STS_3_RC_PKT0_DSCR_FIFO_ERROR                                                          (0x1<<8) // Read packet client NIG main port 0 descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT                                                    8
+  #define BTB_REG_INT_STS_3_RC_PKT1_SIDE_FIFO_ERROR                                                          (0x1<<9) // Read packet client NIG LB port 0 side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT1_SIDE_FIFO_ERROR_SHIFT                                                    9
+  #define BTB_REG_INT_STS_3_RC_PKT1_REQ_FIFO_ERROR                                                           (0x1<<10) // Read packet client NIG LB port 0 request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT1_REQ_FIFO_ERROR_SHIFT                                                     10
+  #define BTB_REG_INT_STS_3_RC_PKT1_BLK_FIFO_ERROR                                                           (0x1<<11) // Read packet client NIG LB port 0 block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT1_BLK_FIFO_ERROR_SHIFT                                                     11
+  #define BTB_REG_INT_STS_3_RC_PKT1_RLS_LEFT_FIFO_ERROR                                                      (0x1<<12) // Read packet client NIG LB port 0 releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT1_RLS_LEFT_FIFO_ERROR_SHIFT                                                12
+  #define BTB_REG_INT_STS_3_RC_PKT1_STRT_PTR_FIFO_ERROR                                                      (0x1<<13) // Read packet client NIG LB port 0 start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT1_STRT_PTR_FIFO_ERROR_SHIFT                                                13
+  #define BTB_REG_INT_STS_3_RC_PKT1_SECOND_PTR_FIFO_ERROR                                                    (0x1<<14) // Read packet client NIG LB port 0 second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT1_SECOND_PTR_FIFO_ERROR_SHIFT                                              14
+  #define BTB_REG_INT_STS_3_RC_PKT1_RSP_FIFO_ERROR                                                           (0x1<<15) // Read packet client NIG LB port 0 response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT1_RSP_FIFO_ERROR_SHIFT                                                     15
+  #define BTB_REG_INT_STS_3_RC_PKT1_DSCR_FIFO_ERROR                                                          (0x1<<16) // Read packet client NIG LB port 0 descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT1_DSCR_FIFO_ERROR_SHIFT                                                    16
+  #define BTB_REG_INT_STS_3_RC_PKT2_SIDE_FIFO_ERROR                                                          (0x1<<17) // Read packet client NIG main port 1 side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT2_SIDE_FIFO_ERROR_SHIFT                                                    17
+  #define BTB_REG_INT_STS_3_RC_PKT2_REQ_FIFO_ERROR                                                           (0x1<<18) // Read packet client NIG main port 1 request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT2_REQ_FIFO_ERROR_SHIFT                                                     18
+  #define BTB_REG_INT_STS_3_RC_PKT2_BLK_FIFO_ERROR                                                           (0x1<<19) // Read packet client NIG main port 1 block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT2_BLK_FIFO_ERROR_SHIFT                                                     19
+  #define BTB_REG_INT_STS_3_RC_PKT2_RLS_LEFT_FIFO_ERROR                                                      (0x1<<20) // Read packet client NIG main port 1 releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT2_RLS_LEFT_FIFO_ERROR_SHIFT                                                20
+  #define BTB_REG_INT_STS_3_RC_PKT2_STRT_PTR_FIFO_ERROR                                                      (0x1<<21) // Read packet client NIG main port 1 start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT2_STRT_PTR_FIFO_ERROR_SHIFT                                                21
+  #define BTB_REG_INT_STS_3_RC_PKT2_SECOND_PTR_FIFO_ERROR                                                    (0x1<<22) // Read packet client NIG main port 1 second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT2_SECOND_PTR_FIFO_ERROR_SHIFT                                              22
+  #define BTB_REG_INT_STS_3_RC_PKT2_RSP_FIFO_ERROR                                                           (0x1<<23) // Read packet client NIG main port 1 response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT2_RSP_FIFO_ERROR_SHIFT                                                     23
+  #define BTB_REG_INT_STS_3_RC_PKT2_DSCR_FIFO_ERROR                                                          (0x1<<24) // Read packet client NIG main port 1 descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT2_DSCR_FIFO_ERROR_SHIFT                                                    24
+  #define BTB_REG_INT_STS_3_RC_PKT3_SIDE_FIFO_ERROR                                                          (0x1<<25) // Read packet client NIG LB port 1 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT3_SIDE_FIFO_ERROR_SHIFT                                                    25
+  #define BTB_REG_INT_STS_3_RC_PKT3_REQ_FIFO_ERROR                                                           (0x1<<26) // Read packet client NIG LB port 1 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT3_REQ_FIFO_ERROR_SHIFT                                                     26
+  #define BTB_REG_INT_STS_3_RC_PKT3_BLK_FIFO_ERROR                                                           (0x1<<27) // Read packet client NIG LB port 1 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT3_BLK_FIFO_ERROR_SHIFT                                                     27
+  #define BTB_REG_INT_STS_3_RC_PKT3_RLS_LEFT_FIFO_ERROR                                                      (0x1<<28) // Read packet client NIG LB port 1 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT3_RLS_LEFT_FIFO_ERROR_SHIFT                                                28
+  #define BTB_REG_INT_STS_3_RC_PKT3_STRT_PTR_FIFO_ERROR                                                      (0x1<<29) // Read packet client NIG LB port 1 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT3_STRT_PTR_FIFO_ERROR_SHIFT                                                29
+  #define BTB_REG_INT_STS_3_RC_PKT3_SECOND_PTR_FIFO_ERROR                                                    (0x1<<30) // Read packet client NIG LB port 1 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT                                              30
+  #define BTB_REG_INT_STS_3_RC_PKT3_RSP_FIFO_ERROR                                                           (0x1<<31) // Read packet client NIG LB port 1 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_3_RC_PKT3_RSP_FIFO_ERROR_SHIFT                                                     31
+#define BTB_REG_INT_MASK_3                                                                                   0xdb010cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define BTB_REG_INT_MASK_3_WC_DUP_PKT_AVAIL_CNT_ERROR                                                      (0x1<<0) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.WC_DUP_PKT_AVAIL_CNT_ERROR .
+  #define BTB_REG_INT_MASK_3_WC_DUP_PKT_AVAIL_CNT_ERROR_SHIFT                                                0
+  #define BTB_REG_INT_MASK_3_RC_PKT0_SIDE_FIFO_ERROR                                                         (0x1<<1) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT0_SIDE_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT                                                   1
+  #define BTB_REG_INT_MASK_3_RC_PKT0_REQ_FIFO_ERROR                                                          (0x1<<2) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT0_REQ_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT0_REQ_FIFO_ERROR_SHIFT                                                    2
+  #define BTB_REG_INT_MASK_3_RC_PKT0_BLK_FIFO_ERROR                                                          (0x1<<3) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT0_BLK_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT                                                    3
+  #define BTB_REG_INT_MASK_3_RC_PKT0_RLS_LEFT_FIFO_ERROR                                                     (0x1<<4) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT0_RLS_LEFT_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT0_RLS_LEFT_FIFO_ERROR_SHIFT                                               4
+  #define BTB_REG_INT_MASK_3_RC_PKT0_STRT_PTR_FIFO_ERROR                                                     (0x1<<5) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT0_STRT_PTR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT0_STRT_PTR_FIFO_ERROR_SHIFT                                               5
+  #define BTB_REG_INT_MASK_3_RC_PKT0_SECOND_PTR_FIFO_ERROR                                                   (0x1<<6) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT0_SECOND_PTR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT0_SECOND_PTR_FIFO_ERROR_SHIFT                                             6
+  #define BTB_REG_INT_MASK_3_RC_PKT0_RSP_FIFO_ERROR                                                          (0x1<<7) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT0_RSP_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT                                                    7
+  #define BTB_REG_INT_MASK_3_RC_PKT0_DSCR_FIFO_ERROR                                                         (0x1<<8) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT0_DSCR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT                                                   8
+  #define BTB_REG_INT_MASK_3_RC_PKT1_SIDE_FIFO_ERROR                                                         (0x1<<9) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT1_SIDE_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT1_SIDE_FIFO_ERROR_SHIFT                                                   9
+  #define BTB_REG_INT_MASK_3_RC_PKT1_REQ_FIFO_ERROR                                                          (0x1<<10) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT1_REQ_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT1_REQ_FIFO_ERROR_SHIFT                                                    10
+  #define BTB_REG_INT_MASK_3_RC_PKT1_BLK_FIFO_ERROR                                                          (0x1<<11) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT1_BLK_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT1_BLK_FIFO_ERROR_SHIFT                                                    11
+  #define BTB_REG_INT_MASK_3_RC_PKT1_RLS_LEFT_FIFO_ERROR                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT1_RLS_LEFT_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT1_RLS_LEFT_FIFO_ERROR_SHIFT                                               12
+  #define BTB_REG_INT_MASK_3_RC_PKT1_STRT_PTR_FIFO_ERROR                                                     (0x1<<13) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT1_STRT_PTR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT1_STRT_PTR_FIFO_ERROR_SHIFT                                               13
+  #define BTB_REG_INT_MASK_3_RC_PKT1_SECOND_PTR_FIFO_ERROR                                                   (0x1<<14) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT1_SECOND_PTR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT1_SECOND_PTR_FIFO_ERROR_SHIFT                                             14
+  #define BTB_REG_INT_MASK_3_RC_PKT1_RSP_FIFO_ERROR                                                          (0x1<<15) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT1_RSP_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT1_RSP_FIFO_ERROR_SHIFT                                                    15
+  #define BTB_REG_INT_MASK_3_RC_PKT1_DSCR_FIFO_ERROR                                                         (0x1<<16) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT1_DSCR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT1_DSCR_FIFO_ERROR_SHIFT                                                   16
+  #define BTB_REG_INT_MASK_3_RC_PKT2_SIDE_FIFO_ERROR                                                         (0x1<<17) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT2_SIDE_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT2_SIDE_FIFO_ERROR_SHIFT                                                   17
+  #define BTB_REG_INT_MASK_3_RC_PKT2_REQ_FIFO_ERROR                                                          (0x1<<18) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT2_REQ_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT2_REQ_FIFO_ERROR_SHIFT                                                    18
+  #define BTB_REG_INT_MASK_3_RC_PKT2_BLK_FIFO_ERROR                                                          (0x1<<19) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT2_BLK_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT2_BLK_FIFO_ERROR_SHIFT                                                    19
+  #define BTB_REG_INT_MASK_3_RC_PKT2_RLS_LEFT_FIFO_ERROR                                                     (0x1<<20) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT2_RLS_LEFT_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT2_RLS_LEFT_FIFO_ERROR_SHIFT                                               20
+  #define BTB_REG_INT_MASK_3_RC_PKT2_STRT_PTR_FIFO_ERROR                                                     (0x1<<21) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT2_STRT_PTR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT2_STRT_PTR_FIFO_ERROR_SHIFT                                               21
+  #define BTB_REG_INT_MASK_3_RC_PKT2_SECOND_PTR_FIFO_ERROR                                                   (0x1<<22) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT2_SECOND_PTR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT2_SECOND_PTR_FIFO_ERROR_SHIFT                                             22
+  #define BTB_REG_INT_MASK_3_RC_PKT2_RSP_FIFO_ERROR                                                          (0x1<<23) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT2_RSP_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT2_RSP_FIFO_ERROR_SHIFT                                                    23
+  #define BTB_REG_INT_MASK_3_RC_PKT2_DSCR_FIFO_ERROR                                                         (0x1<<24) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT2_DSCR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT2_DSCR_FIFO_ERROR_SHIFT                                                   24
+  #define BTB_REG_INT_MASK_3_RC_PKT3_SIDE_FIFO_ERROR                                                         (0x1<<25) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT3_SIDE_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT3_SIDE_FIFO_ERROR_SHIFT                                                   25
+  #define BTB_REG_INT_MASK_3_RC_PKT3_REQ_FIFO_ERROR                                                          (0x1<<26) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT3_REQ_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT3_REQ_FIFO_ERROR_SHIFT                                                    26
+  #define BTB_REG_INT_MASK_3_RC_PKT3_BLK_FIFO_ERROR                                                          (0x1<<27) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT3_BLK_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT3_BLK_FIFO_ERROR_SHIFT                                                    27
+  #define BTB_REG_INT_MASK_3_RC_PKT3_RLS_LEFT_FIFO_ERROR                                                     (0x1<<28) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT3_RLS_LEFT_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT3_RLS_LEFT_FIFO_ERROR_SHIFT                                               28
+  #define BTB_REG_INT_MASK_3_RC_PKT3_STRT_PTR_FIFO_ERROR                                                     (0x1<<29) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT3_STRT_PTR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT3_STRT_PTR_FIFO_ERROR_SHIFT                                               29
+  #define BTB_REG_INT_MASK_3_RC_PKT3_SECOND_PTR_FIFO_ERROR                                                   (0x1<<30) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT3_SECOND_PTR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT                                             30
+  #define BTB_REG_INT_MASK_3_RC_PKT3_RSP_FIFO_ERROR                                                          (0x1<<31) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT3_RSP_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_3_RC_PKT3_RSP_FIFO_ERROR_SHIFT                                                    31
+#define BTB_REG_INT_STS_WR_3                                                                                 0xdb0110UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define BTB_REG_INT_STS_WR_3_WC_DUP_PKT_AVAIL_CNT_ERROR                                                    (0x1<<0) // Packet available counter overflow or underflow in duplicated write client DUP_EN::/DUP_EN/d in Comments.
+  #define BTB_REG_INT_STS_WR_3_WC_DUP_PKT_AVAIL_CNT_ERROR_SHIFT                                              0
+  #define BTB_REG_INT_STS_WR_3_RC_PKT0_SIDE_FIFO_ERROR                                                       (0x1<<1) // Read packet client NIG main port 0 side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT                                                 1
+  #define BTB_REG_INT_STS_WR_3_RC_PKT0_REQ_FIFO_ERROR                                                        (0x1<<2) // Read packet client NIG main port 0 request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT0_REQ_FIFO_ERROR_SHIFT                                                  2
+  #define BTB_REG_INT_STS_WR_3_RC_PKT0_BLK_FIFO_ERROR                                                        (0x1<<3) // Read packet client NIG main port 0 block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT                                                  3
+  #define BTB_REG_INT_STS_WR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR                                                   (0x1<<4) // Read packet client NIG main port 0 releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR_SHIFT                                             4
+  #define BTB_REG_INT_STS_WR_3_RC_PKT0_STRT_PTR_FIFO_ERROR                                                   (0x1<<5) // Read packet client NIG main port 0 start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT0_STRT_PTR_FIFO_ERROR_SHIFT                                             5
+  #define BTB_REG_INT_STS_WR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR                                                 (0x1<<6) // Read packet client NIG main port 0 second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR_SHIFT                                           6
+  #define BTB_REG_INT_STS_WR_3_RC_PKT0_RSP_FIFO_ERROR                                                        (0x1<<7) // Read packet client NIG main port 0 response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT                                                  7
+  #define BTB_REG_INT_STS_WR_3_RC_PKT0_DSCR_FIFO_ERROR                                                       (0x1<<8) // Read packet client NIG main port 0 descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT                                                 8
+  #define BTB_REG_INT_STS_WR_3_RC_PKT1_SIDE_FIFO_ERROR                                                       (0x1<<9) // Read packet client NIG LB port 0 side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT1_SIDE_FIFO_ERROR_SHIFT                                                 9
+  #define BTB_REG_INT_STS_WR_3_RC_PKT1_REQ_FIFO_ERROR                                                        (0x1<<10) // Read packet client NIG LB port 0 request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT1_REQ_FIFO_ERROR_SHIFT                                                  10
+  #define BTB_REG_INT_STS_WR_3_RC_PKT1_BLK_FIFO_ERROR                                                        (0x1<<11) // Read packet client NIG LB port 0 block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT1_BLK_FIFO_ERROR_SHIFT                                                  11
+  #define BTB_REG_INT_STS_WR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR                                                   (0x1<<12) // Read packet client NIG LB port 0 releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR_SHIFT                                             12
+  #define BTB_REG_INT_STS_WR_3_RC_PKT1_STRT_PTR_FIFO_ERROR                                                   (0x1<<13) // Read packet client NIG LB port 0 start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT1_STRT_PTR_FIFO_ERROR_SHIFT                                             13
+  #define BTB_REG_INT_STS_WR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR                                                 (0x1<<14) // Read packet client NIG LB port 0 second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR_SHIFT                                           14
+  #define BTB_REG_INT_STS_WR_3_RC_PKT1_RSP_FIFO_ERROR                                                        (0x1<<15) // Read packet client NIG LB port 0 response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT1_RSP_FIFO_ERROR_SHIFT                                                  15
+  #define BTB_REG_INT_STS_WR_3_RC_PKT1_DSCR_FIFO_ERROR                                                       (0x1<<16) // Read packet client NIG LB port 0 descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT1_DSCR_FIFO_ERROR_SHIFT                                                 16
+  #define BTB_REG_INT_STS_WR_3_RC_PKT2_SIDE_FIFO_ERROR                                                       (0x1<<17) // Read packet client NIG main port 1 side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT2_SIDE_FIFO_ERROR_SHIFT                                                 17
+  #define BTB_REG_INT_STS_WR_3_RC_PKT2_REQ_FIFO_ERROR                                                        (0x1<<18) // Read packet client NIG main port 1 request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT2_REQ_FIFO_ERROR_SHIFT                                                  18
+  #define BTB_REG_INT_STS_WR_3_RC_PKT2_BLK_FIFO_ERROR                                                        (0x1<<19) // Read packet client NIG main port 1 block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT2_BLK_FIFO_ERROR_SHIFT                                                  19
+  #define BTB_REG_INT_STS_WR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR                                                   (0x1<<20) // Read packet client NIG main port 1 releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR_SHIFT                                             20
+  #define BTB_REG_INT_STS_WR_3_RC_PKT2_STRT_PTR_FIFO_ERROR                                                   (0x1<<21) // Read packet client NIG main port 1 start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT2_STRT_PTR_FIFO_ERROR_SHIFT                                             21
+  #define BTB_REG_INT_STS_WR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR                                                 (0x1<<22) // Read packet client NIG main port 1 second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR_SHIFT                                           22
+  #define BTB_REG_INT_STS_WR_3_RC_PKT2_RSP_FIFO_ERROR                                                        (0x1<<23) // Read packet client NIG main port 1 response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT2_RSP_FIFO_ERROR_SHIFT                                                  23
+  #define BTB_REG_INT_STS_WR_3_RC_PKT2_DSCR_FIFO_ERROR                                                       (0x1<<24) // Read packet client NIG main port 1 descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT2_DSCR_FIFO_ERROR_SHIFT                                                 24
+  #define BTB_REG_INT_STS_WR_3_RC_PKT3_SIDE_FIFO_ERROR                                                       (0x1<<25) // Read packet client NIG LB port 1 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT3_SIDE_FIFO_ERROR_SHIFT                                                 25
+  #define BTB_REG_INT_STS_WR_3_RC_PKT3_REQ_FIFO_ERROR                                                        (0x1<<26) // Read packet client NIG LB port 1 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT3_REQ_FIFO_ERROR_SHIFT                                                  26
+  #define BTB_REG_INT_STS_WR_3_RC_PKT3_BLK_FIFO_ERROR                                                        (0x1<<27) // Read packet client NIG LB port 1 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT3_BLK_FIFO_ERROR_SHIFT                                                  27
+  #define BTB_REG_INT_STS_WR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR                                                   (0x1<<28) // Read packet client NIG LB port 1 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR_SHIFT                                             28
+  #define BTB_REG_INT_STS_WR_3_RC_PKT3_STRT_PTR_FIFO_ERROR                                                   (0x1<<29) // Read packet client NIG LB port 1 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT3_STRT_PTR_FIFO_ERROR_SHIFT                                             29
+  #define BTB_REG_INT_STS_WR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR                                                 (0x1<<30) // Read packet client NIG LB port 1 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT                                           30
+  #define BTB_REG_INT_STS_WR_3_RC_PKT3_RSP_FIFO_ERROR                                                        (0x1<<31) // Read packet client NIG LB port 1 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_WR_3_RC_PKT3_RSP_FIFO_ERROR_SHIFT                                                  31
+#define BTB_REG_INT_STS_CLR_3                                                                                0xdb0114UL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define BTB_REG_INT_STS_CLR_3_WC_DUP_PKT_AVAIL_CNT_ERROR                                                   (0x1<<0) // Packet available counter overflow or underflow in duplicated write client DUP_EN::/DUP_EN/d in Comments.
+  #define BTB_REG_INT_STS_CLR_3_WC_DUP_PKT_AVAIL_CNT_ERROR_SHIFT                                             0
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT0_SIDE_FIFO_ERROR                                                      (0x1<<1) // Read packet client NIG main port 0 side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT                                                1
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT0_REQ_FIFO_ERROR                                                       (0x1<<2) // Read packet client NIG main port 0 request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT0_REQ_FIFO_ERROR_SHIFT                                                 2
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT0_BLK_FIFO_ERROR                                                       (0x1<<3) // Read packet client NIG main port 0 block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT                                                 3
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR                                                  (0x1<<4) // Read packet client NIG main port 0 releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR_SHIFT                                            4
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT0_STRT_PTR_FIFO_ERROR                                                  (0x1<<5) // Read packet client NIG main port 0 start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT0_STRT_PTR_FIFO_ERROR_SHIFT                                            5
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR                                                (0x1<<6) // Read packet client NIG main port 0 second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR_SHIFT                                          6
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT0_RSP_FIFO_ERROR                                                       (0x1<<7) // Read packet client NIG main port 0 response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT                                                 7
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT0_DSCR_FIFO_ERROR                                                      (0x1<<8) // Read packet client NIG main port 0 descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT                                                8
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT1_SIDE_FIFO_ERROR                                                      (0x1<<9) // Read packet client NIG LB port 0 side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT1_SIDE_FIFO_ERROR_SHIFT                                                9
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT1_REQ_FIFO_ERROR                                                       (0x1<<10) // Read packet client NIG LB port 0 request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT1_REQ_FIFO_ERROR_SHIFT                                                 10
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT1_BLK_FIFO_ERROR                                                       (0x1<<11) // Read packet client NIG LB port 0 block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT1_BLK_FIFO_ERROR_SHIFT                                                 11
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR                                                  (0x1<<12) // Read packet client NIG LB port 0 releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR_SHIFT                                            12
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT1_STRT_PTR_FIFO_ERROR                                                  (0x1<<13) // Read packet client NIG LB port 0 start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT1_STRT_PTR_FIFO_ERROR_SHIFT                                            13
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR                                                (0x1<<14) // Read packet client NIG LB port 0 second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR_SHIFT                                          14
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT1_RSP_FIFO_ERROR                                                       (0x1<<15) // Read packet client NIG LB port 0 response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT1_RSP_FIFO_ERROR_SHIFT                                                 15
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT1_DSCR_FIFO_ERROR                                                      (0x1<<16) // Read packet client NIG LB port 0 descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT1_DSCR_FIFO_ERROR_SHIFT                                                16
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT2_SIDE_FIFO_ERROR                                                      (0x1<<17) // Read packet client NIG main port 1 side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT2_SIDE_FIFO_ERROR_SHIFT                                                17
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT2_REQ_FIFO_ERROR                                                       (0x1<<18) // Read packet client NIG main port 1 request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT2_REQ_FIFO_ERROR_SHIFT                                                 18
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT2_BLK_FIFO_ERROR                                                       (0x1<<19) // Read packet client NIG main port 1 block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT2_BLK_FIFO_ERROR_SHIFT                                                 19
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR                                                  (0x1<<20) // Read packet client NIG main port 1 releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR_SHIFT                                            20
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT2_STRT_PTR_FIFO_ERROR                                                  (0x1<<21) // Read packet client NIG main port 1 start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT2_STRT_PTR_FIFO_ERROR_SHIFT                                            21
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR                                                (0x1<<22) // Read packet client NIG main port 1 second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR_SHIFT                                          22
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT2_RSP_FIFO_ERROR                                                       (0x1<<23) // Read packet client NIG main port 1 response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT2_RSP_FIFO_ERROR_SHIFT                                                 23
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT2_DSCR_FIFO_ERROR                                                      (0x1<<24) // Read packet client NIG main port 1 descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT2_DSCR_FIFO_ERROR_SHIFT                                                24
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT3_SIDE_FIFO_ERROR                                                      (0x1<<25) // Read packet client NIG LB port 1 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT3_SIDE_FIFO_ERROR_SHIFT                                                25
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT3_REQ_FIFO_ERROR                                                       (0x1<<26) // Read packet client NIG LB port 1 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT3_REQ_FIFO_ERROR_SHIFT                                                 26
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT3_BLK_FIFO_ERROR                                                       (0x1<<27) // Read packet client NIG LB port 1 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT3_BLK_FIFO_ERROR_SHIFT                                                 27
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR                                                  (0x1<<28) // Read packet client NIG LB port 1 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR_SHIFT                                            28
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT3_STRT_PTR_FIFO_ERROR                                                  (0x1<<29) // Read packet client NIG LB port 1 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT3_STRT_PTR_FIFO_ERROR_SHIFT                                            29
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR                                                (0x1<<30) // Read packet client NIG LB port 1 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT                                          30
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT3_RSP_FIFO_ERROR                                                       (0x1<<31) // Read packet client NIG LB port 1 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_CLR_3_RC_PKT3_RSP_FIFO_ERROR_SHIFT                                                 31
+#define BTB_REG_INT_STS_4                                                                                    0xdb0120UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define BTB_REG_INT_STS_4_RC_PKT3_DSCR_FIFO_ERROR                                                          (0x1<<0) // Read packet client NIG LB port 1 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_4_RC_PKT3_DSCR_FIFO_ERROR_SHIFT                                                    0
+  #define BTB_REG_INT_STS_4_RC_SOP_QUEUE_FIFO_ERROR                                                          (0x1<<4) // Read SOP client queue FIFO error.
+  #define BTB_REG_INT_STS_4_RC_SOP_QUEUE_FIFO_ERROR_SHIFT                                                    4
+  #define BTB_REG_INT_STS_4_LL_ARB_RLS_FIFO_ERROR                                                            (0x1<<7) // Link list arbiter release FIFO error.
+  #define BTB_REG_INT_STS_4_LL_ARB_RLS_FIFO_ERROR_SHIFT                                                      7
+  #define BTB_REG_INT_STS_4_LL_ARB_PREFETCH_FIFO_ERROR                                                       (0x1<<8) // Link list arbiter prefetch FIFO error.
+  #define BTB_REG_INT_STS_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT                                                 8
+  #define BTB_REG_INT_STS_4_RC_PKT0_RLS_FIFO_ERROR                                                           (0x1<<9) // Read packet client NIG main port 0 release fifo error
+  #define BTB_REG_INT_STS_4_RC_PKT0_RLS_FIFO_ERROR_SHIFT                                                     9
+  #define BTB_REG_INT_STS_4_RC_PKT1_RLS_FIFO_ERROR                                                           (0x1<<10) // Read packet client NIG LB port 0 release fifo error
+  #define BTB_REG_INT_STS_4_RC_PKT1_RLS_FIFO_ERROR_SHIFT                                                     10
+  #define BTB_REG_INT_STS_4_RC_PKT2_RLS_FIFO_ERROR                                                           (0x1<<11) // Read packet client NIG main port 1 release fifo error
+  #define BTB_REG_INT_STS_4_RC_PKT2_RLS_FIFO_ERROR_SHIFT                                                     11
+  #define BTB_REG_INT_STS_4_RC_PKT3_RLS_FIFO_ERROR                                                           (0x1<<12) // Read packet client NIG LB port 1 release fifo error
+  #define BTB_REG_INT_STS_4_RC_PKT3_RLS_FIFO_ERROR_SHIFT                                                     12
+  #define BTB_REG_INT_STS_4_RC_PKT4_RLS_FIFO_ERROR                                                           (0x1<<13) // Read packet client NIG main port 2 release fifo error
+  #define BTB_REG_INT_STS_4_RC_PKT4_RLS_FIFO_ERROR_SHIFT                                                     13
+  #define BTB_REG_INT_STS_4_RC_PKT5_RLS_FIFO_ERROR                                                           (0x1<<14) // Read packet client NIG main port 2 release fifo error
+  #define BTB_REG_INT_STS_4_RC_PKT5_RLS_FIFO_ERROR_SHIFT                                                     14
+  #define BTB_REG_INT_STS_4_RC_PKT6_RLS_FIFO_ERROR                                                           (0x1<<15) // Read packet client NIG main port 2 release fifo error
+  #define BTB_REG_INT_STS_4_RC_PKT6_RLS_FIFO_ERROR_SHIFT                                                     15
+  #define BTB_REG_INT_STS_4_RC_PKT7_RLS_FIFO_ERROR                                                           (0x1<<16) // Read packet client NIG main port 2 release fifo error
+  #define BTB_REG_INT_STS_4_RC_PKT7_RLS_FIFO_ERROR_SHIFT                                                     16
+  #define BTB_REG_INT_STS_4_RC_PKT4_RLS_ERROR                                                                (0x1<<19) // Read packet client NIG LB port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_4_RC_PKT4_RLS_ERROR_SHIFT                                                          19
+  #define BTB_REG_INT_STS_4_RC_PKT4_LEN_ERROR                                                                (0x1<<21) // Read packet client NIG LB port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_4_RC_PKT4_LEN_ERROR_SHIFT                                                          21
+  #define BTB_REG_INT_STS_4_RC_PKT4_PROTOCOL_ERROR                                                           (0x1<<23) // Read packet client NIG LB port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_4_RC_PKT4_PROTOCOL_ERROR_SHIFT                                                     23
+  #define BTB_REG_INT_STS_4_RC_PKT4_SIDE_FIFO_ERROR                                                          (0x1<<24) // Read packet client NIG LB port 1 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_4_RC_PKT4_SIDE_FIFO_ERROR_SHIFT                                                    24
+  #define BTB_REG_INT_STS_4_RC_PKT4_REQ_FIFO_ERROR                                                           (0x1<<25) // Read packet client NIG LB port 1 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_4_RC_PKT4_REQ_FIFO_ERROR_SHIFT                                                     25
+  #define BTB_REG_INT_STS_4_RC_PKT4_BLK_FIFO_ERROR                                                           (0x1<<26) // Read packet client NIG LB port 1 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_4_RC_PKT4_BLK_FIFO_ERROR_SHIFT                                                     26
+  #define BTB_REG_INT_STS_4_RC_PKT4_RLS_LEFT_FIFO_ERROR                                                      (0x1<<27) // Read packet client NIG LB port 1 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_4_RC_PKT4_RLS_LEFT_FIFO_ERROR_SHIFT                                                27
+  #define BTB_REG_INT_STS_4_RC_PKT4_STRT_PTR_FIFO_ERROR                                                      (0x1<<28) // Read packet client NIG LB port 1 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_4_RC_PKT4_STRT_PTR_FIFO_ERROR_SHIFT                                                28
+  #define BTB_REG_INT_STS_4_RC_PKT4_SECOND_PTR_FIFO_ERROR                                                    (0x1<<29) // Read packet client NIG LB port 1 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_4_RC_PKT4_SECOND_PTR_FIFO_ERROR_SHIFT                                              29
+  #define BTB_REG_INT_STS_4_RC_PKT4_RSP_FIFO_ERROR                                                           (0x1<<30) // Read packet client NIG LB port 1 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT                                                     30
+  #define BTB_REG_INT_STS_4_RC_PKT4_DSCR_FIFO_ERROR                                                          (0x1<<31) // Read packet client NIG LB port 1 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_4_RC_PKT4_DSCR_FIFO_ERROR_SHIFT                                                    31
+#define BTB_REG_INT_MASK_4                                                                                   0xdb0124UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define BTB_REG_INT_MASK_4_RC_PKT3_DSCR_FIFO_ERROR                                                         (0x1<<0) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT3_DSCR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_4_RC_PKT3_DSCR_FIFO_ERROR_SHIFT                                                   0
+  #define BTB_REG_INT_MASK_4_RC_SOP_QUEUE_FIFO_ERROR                                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_SOP_QUEUE_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_4_RC_SOP_QUEUE_FIFO_ERROR_SHIFT                                                   4
+  #define BTB_REG_INT_MASK_4_LL_ARB_RLS_FIFO_ERROR                                                           (0x1<<7) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.LL_ARB_RLS_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_4_LL_ARB_RLS_FIFO_ERROR_SHIFT                                                     7
+  #define BTB_REG_INT_MASK_4_LL_ARB_PREFETCH_FIFO_ERROR                                                      (0x1<<8) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.LL_ARB_PREFETCH_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT                                                8
+  #define BTB_REG_INT_MASK_4_RC_PKT0_RLS_FIFO_ERROR                                                          (0x1<<9) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT0_RLS_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_4_RC_PKT0_RLS_FIFO_ERROR_SHIFT                                                    9
+  #define BTB_REG_INT_MASK_4_RC_PKT1_RLS_FIFO_ERROR                                                          (0x1<<10) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT1_RLS_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_4_RC_PKT1_RLS_FIFO_ERROR_SHIFT                                                    10
+  #define BTB_REG_INT_MASK_4_RC_PKT2_RLS_FIFO_ERROR                                                          (0x1<<11) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT2_RLS_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_4_RC_PKT2_RLS_FIFO_ERROR_SHIFT                                                    11
+  #define BTB_REG_INT_MASK_4_RC_PKT3_RLS_FIFO_ERROR                                                          (0x1<<12) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT3_RLS_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_4_RC_PKT3_RLS_FIFO_ERROR_SHIFT                                                    12
+  #define BTB_REG_INT_MASK_4_RC_PKT4_RLS_FIFO_ERROR                                                          (0x1<<13) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_RLS_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_4_RC_PKT4_RLS_FIFO_ERROR_SHIFT                                                    13
+  #define BTB_REG_INT_MASK_4_RC_PKT5_RLS_FIFO_ERROR                                                          (0x1<<14) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT5_RLS_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_4_RC_PKT5_RLS_FIFO_ERROR_SHIFT                                                    14
+  #define BTB_REG_INT_MASK_4_RC_PKT6_RLS_FIFO_ERROR                                                          (0x1<<15) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT6_RLS_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_4_RC_PKT6_RLS_FIFO_ERROR_SHIFT                                                    15
+  #define BTB_REG_INT_MASK_4_RC_PKT7_RLS_FIFO_ERROR                                                          (0x1<<16) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT7_RLS_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_4_RC_PKT7_RLS_FIFO_ERROR_SHIFT                                                    16
+  #define BTB_REG_INT_MASK_4_RC_PKT4_RLS_ERROR                                                               (0x1<<19) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_RLS_ERROR .
+  #define BTB_REG_INT_MASK_4_RC_PKT4_RLS_ERROR_SHIFT                                                         19
+  #define BTB_REG_INT_MASK_4_RC_PKT4_LEN_ERROR                                                               (0x1<<21) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_LEN_ERROR .
+  #define BTB_REG_INT_MASK_4_RC_PKT4_LEN_ERROR_SHIFT                                                         21
+  #define BTB_REG_INT_MASK_4_RC_PKT4_PROTOCOL_ERROR                                                          (0x1<<23) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_PROTOCOL_ERROR .
+  #define BTB_REG_INT_MASK_4_RC_PKT4_PROTOCOL_ERROR_SHIFT                                                    23
+  #define BTB_REG_INT_MASK_4_RC_PKT4_SIDE_FIFO_ERROR                                                         (0x1<<24) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_SIDE_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_4_RC_PKT4_SIDE_FIFO_ERROR_SHIFT                                                   24
+  #define BTB_REG_INT_MASK_4_RC_PKT4_REQ_FIFO_ERROR                                                          (0x1<<25) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_REQ_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_4_RC_PKT4_REQ_FIFO_ERROR_SHIFT                                                    25
+  #define BTB_REG_INT_MASK_4_RC_PKT4_BLK_FIFO_ERROR                                                          (0x1<<26) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_BLK_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_4_RC_PKT4_BLK_FIFO_ERROR_SHIFT                                                    26
+  #define BTB_REG_INT_MASK_4_RC_PKT4_RLS_LEFT_FIFO_ERROR                                                     (0x1<<27) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_RLS_LEFT_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_4_RC_PKT4_RLS_LEFT_FIFO_ERROR_SHIFT                                               27
+  #define BTB_REG_INT_MASK_4_RC_PKT4_STRT_PTR_FIFO_ERROR                                                     (0x1<<28) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_STRT_PTR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_4_RC_PKT4_STRT_PTR_FIFO_ERROR_SHIFT                                               28
+  #define BTB_REG_INT_MASK_4_RC_PKT4_SECOND_PTR_FIFO_ERROR                                                   (0x1<<29) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_SECOND_PTR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_4_RC_PKT4_SECOND_PTR_FIFO_ERROR_SHIFT                                             29
+  #define BTB_REG_INT_MASK_4_RC_PKT4_RSP_FIFO_ERROR                                                          (0x1<<30) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_RSP_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT                                                    30
+  #define BTB_REG_INT_MASK_4_RC_PKT4_DSCR_FIFO_ERROR                                                         (0x1<<31) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_DSCR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_4_RC_PKT4_DSCR_FIFO_ERROR_SHIFT                                                   31
+#define BTB_REG_INT_STS_WR_4                                                                                 0xdb0128UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define BTB_REG_INT_STS_WR_4_RC_PKT3_DSCR_FIFO_ERROR                                                       (0x1<<0) // Read packet client NIG LB port 1 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_WR_4_RC_PKT3_DSCR_FIFO_ERROR_SHIFT                                                 0
+  #define BTB_REG_INT_STS_WR_4_RC_SOP_QUEUE_FIFO_ERROR                                                       (0x1<<4) // Read SOP client queue FIFO error.
+  #define BTB_REG_INT_STS_WR_4_RC_SOP_QUEUE_FIFO_ERROR_SHIFT                                                 4
+  #define BTB_REG_INT_STS_WR_4_LL_ARB_RLS_FIFO_ERROR                                                         (0x1<<7) // Link list arbiter release FIFO error.
+  #define BTB_REG_INT_STS_WR_4_LL_ARB_RLS_FIFO_ERROR_SHIFT                                                   7
+  #define BTB_REG_INT_STS_WR_4_LL_ARB_PREFETCH_FIFO_ERROR                                                    (0x1<<8) // Link list arbiter prefetch FIFO error.
+  #define BTB_REG_INT_STS_WR_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT                                              8
+  #define BTB_REG_INT_STS_WR_4_RC_PKT0_RLS_FIFO_ERROR                                                        (0x1<<9) // Read packet client NIG main port 0 release fifo error
+  #define BTB_REG_INT_STS_WR_4_RC_PKT0_RLS_FIFO_ERROR_SHIFT                                                  9
+  #define BTB_REG_INT_STS_WR_4_RC_PKT1_RLS_FIFO_ERROR                                                        (0x1<<10) // Read packet client NIG LB port 0 release fifo error
+  #define BTB_REG_INT_STS_WR_4_RC_PKT1_RLS_FIFO_ERROR_SHIFT                                                  10
+  #define BTB_REG_INT_STS_WR_4_RC_PKT2_RLS_FIFO_ERROR                                                        (0x1<<11) // Read packet client NIG main port 1 release fifo error
+  #define BTB_REG_INT_STS_WR_4_RC_PKT2_RLS_FIFO_ERROR_SHIFT                                                  11
+  #define BTB_REG_INT_STS_WR_4_RC_PKT3_RLS_FIFO_ERROR                                                        (0x1<<12) // Read packet client NIG LB port 1 release fifo error
+  #define BTB_REG_INT_STS_WR_4_RC_PKT3_RLS_FIFO_ERROR_SHIFT                                                  12
+  #define BTB_REG_INT_STS_WR_4_RC_PKT4_RLS_FIFO_ERROR                                                        (0x1<<13) // Read packet client NIG main port 2 release fifo error
+  #define BTB_REG_INT_STS_WR_4_RC_PKT4_RLS_FIFO_ERROR_SHIFT                                                  13
+  #define BTB_REG_INT_STS_WR_4_RC_PKT5_RLS_FIFO_ERROR                                                        (0x1<<14) // Read packet client NIG main port 2 release fifo error
+  #define BTB_REG_INT_STS_WR_4_RC_PKT5_RLS_FIFO_ERROR_SHIFT                                                  14
+  #define BTB_REG_INT_STS_WR_4_RC_PKT6_RLS_FIFO_ERROR                                                        (0x1<<15) // Read packet client NIG main port 2 release fifo error
+  #define BTB_REG_INT_STS_WR_4_RC_PKT6_RLS_FIFO_ERROR_SHIFT                                                  15
+  #define BTB_REG_INT_STS_WR_4_RC_PKT7_RLS_FIFO_ERROR                                                        (0x1<<16) // Read packet client NIG main port 2 release fifo error
+  #define BTB_REG_INT_STS_WR_4_RC_PKT7_RLS_FIFO_ERROR_SHIFT                                                  16
+  #define BTB_REG_INT_STS_WR_4_RC_PKT4_RLS_ERROR                                                             (0x1<<19) // Read packet client NIG LB port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_WR_4_RC_PKT4_RLS_ERROR_SHIFT                                                       19
+  #define BTB_REG_INT_STS_WR_4_RC_PKT4_LEN_ERROR                                                             (0x1<<21) // Read packet client NIG LB port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_WR_4_RC_PKT4_LEN_ERROR_SHIFT                                                       21
+  #define BTB_REG_INT_STS_WR_4_RC_PKT4_PROTOCOL_ERROR                                                        (0x1<<23) // Read packet client NIG LB port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_WR_4_RC_PKT4_PROTOCOL_ERROR_SHIFT                                                  23
+  #define BTB_REG_INT_STS_WR_4_RC_PKT4_SIDE_FIFO_ERROR                                                       (0x1<<24) // Read packet client NIG LB port 1 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_WR_4_RC_PKT4_SIDE_FIFO_ERROR_SHIFT                                                 24
+  #define BTB_REG_INT_STS_WR_4_RC_PKT4_REQ_FIFO_ERROR                                                        (0x1<<25) // Read packet client NIG LB port 1 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_WR_4_RC_PKT4_REQ_FIFO_ERROR_SHIFT                                                  25
+  #define BTB_REG_INT_STS_WR_4_RC_PKT4_BLK_FIFO_ERROR                                                        (0x1<<26) // Read packet client NIG LB port 1 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_WR_4_RC_PKT4_BLK_FIFO_ERROR_SHIFT                                                  26
+  #define BTB_REG_INT_STS_WR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR                                                   (0x1<<27) // Read packet client NIG LB port 1 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_WR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR_SHIFT                                             27
+  #define BTB_REG_INT_STS_WR_4_RC_PKT4_STRT_PTR_FIFO_ERROR                                                   (0x1<<28) // Read packet client NIG LB port 1 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_WR_4_RC_PKT4_STRT_PTR_FIFO_ERROR_SHIFT                                             28
+  #define BTB_REG_INT_STS_WR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR                                                 (0x1<<29) // Read packet client NIG LB port 1 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_WR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR_SHIFT                                           29
+  #define BTB_REG_INT_STS_WR_4_RC_PKT4_RSP_FIFO_ERROR                                                        (0x1<<30) // Read packet client NIG LB port 1 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_WR_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT                                                  30
+  #define BTB_REG_INT_STS_WR_4_RC_PKT4_DSCR_FIFO_ERROR                                                       (0x1<<31) // Read packet client NIG LB port 1 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_WR_4_RC_PKT4_DSCR_FIFO_ERROR_SHIFT                                                 31
+#define BTB_REG_INT_STS_CLR_4                                                                                0xdb012cUL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT3_DSCR_FIFO_ERROR                                                      (0x1<<0) // Read packet client NIG LB port 1 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT3_DSCR_FIFO_ERROR_SHIFT                                                0
+  #define BTB_REG_INT_STS_CLR_4_RC_SOP_QUEUE_FIFO_ERROR                                                      (0x1<<4) // Read SOP client queue FIFO error.
+  #define BTB_REG_INT_STS_CLR_4_RC_SOP_QUEUE_FIFO_ERROR_SHIFT                                                4
+  #define BTB_REG_INT_STS_CLR_4_LL_ARB_RLS_FIFO_ERROR                                                        (0x1<<7) // Link list arbiter release FIFO error.
+  #define BTB_REG_INT_STS_CLR_4_LL_ARB_RLS_FIFO_ERROR_SHIFT                                                  7
+  #define BTB_REG_INT_STS_CLR_4_LL_ARB_PREFETCH_FIFO_ERROR                                                   (0x1<<8) // Link list arbiter prefetch FIFO error.
+  #define BTB_REG_INT_STS_CLR_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT                                             8
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT0_RLS_FIFO_ERROR                                                       (0x1<<9) // Read packet client NIG main port 0 release fifo error
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT0_RLS_FIFO_ERROR_SHIFT                                                 9
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT1_RLS_FIFO_ERROR                                                       (0x1<<10) // Read packet client NIG LB port 0 release fifo error
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT1_RLS_FIFO_ERROR_SHIFT                                                 10
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT2_RLS_FIFO_ERROR                                                       (0x1<<11) // Read packet client NIG main port 1 release fifo error
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT2_RLS_FIFO_ERROR_SHIFT                                                 11
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT3_RLS_FIFO_ERROR                                                       (0x1<<12) // Read packet client NIG LB port 1 release fifo error
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT3_RLS_FIFO_ERROR_SHIFT                                                 12
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT4_RLS_FIFO_ERROR                                                       (0x1<<13) // Read packet client NIG main port 2 release fifo error
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT4_RLS_FIFO_ERROR_SHIFT                                                 13
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT5_RLS_FIFO_ERROR                                                       (0x1<<14) // Read packet client NIG main port 2 release fifo error
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT5_RLS_FIFO_ERROR_SHIFT                                                 14
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT6_RLS_FIFO_ERROR                                                       (0x1<<15) // Read packet client NIG main port 2 release fifo error
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT6_RLS_FIFO_ERROR_SHIFT                                                 15
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT7_RLS_FIFO_ERROR                                                       (0x1<<16) // Read packet client NIG main port 2 release fifo error
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT7_RLS_FIFO_ERROR_SHIFT                                                 16
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT4_RLS_ERROR                                                            (0x1<<19) // Read packet client NIG LB port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT4_RLS_ERROR_SHIFT                                                      19
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT4_LEN_ERROR                                                            (0x1<<21) // Read packet client NIG LB port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT4_LEN_ERROR_SHIFT                                                      21
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT4_PROTOCOL_ERROR                                                       (0x1<<23) // Read packet client NIG LB port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT4_PROTOCOL_ERROR_SHIFT                                                 23
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT4_SIDE_FIFO_ERROR                                                      (0x1<<24) // Read packet client NIG LB port 1 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT4_SIDE_FIFO_ERROR_SHIFT                                                24
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT4_REQ_FIFO_ERROR                                                       (0x1<<25) // Read packet client NIG LB port 1 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT4_REQ_FIFO_ERROR_SHIFT                                                 25
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT4_BLK_FIFO_ERROR                                                       (0x1<<26) // Read packet client NIG LB port 1 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT4_BLK_FIFO_ERROR_SHIFT                                                 26
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR                                                  (0x1<<27) // Read packet client NIG LB port 1 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR_SHIFT                                            27
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT4_STRT_PTR_FIFO_ERROR                                                  (0x1<<28) // Read packet client NIG LB port 1 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT4_STRT_PTR_FIFO_ERROR_SHIFT                                            28
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR                                                (0x1<<29) // Read packet client NIG LB port 1 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR_SHIFT                                          29
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT4_RSP_FIFO_ERROR                                                       (0x1<<30) // Read packet client NIG LB port 1 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT                                                 30
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT4_DSCR_FIFO_ERROR                                                      (0x1<<31) // Read packet client NIG LB port 1 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
+  #define BTB_REG_INT_STS_CLR_4_RC_PKT4_DSCR_FIFO_ERROR_SHIFT                                                31
+#define BTB_REG_INT_STS_5                                                                                    0xdb0138UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define BTB_REG_INT_STS_5_RC_PKT5_RLS_ERROR                                                                (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
+  #define BTB_REG_INT_STS_5_RC_PKT5_RLS_ERROR_SHIFT                                                          0
+  #define BTB_REG_INT_STS_5_RC_PKT5_LEN_ERROR                                                                (0x1<<1) // Read packet client5 length error when requested packet length is bigger than real packet length
+  #define BTB_REG_INT_STS_5_RC_PKT5_LEN_ERROR_SHIFT                                                          1
+  #define BTB_REG_INT_STS_5_RC_PKT5_PROTOCOL_ERROR                                                           (0x1<<2) // Read packet client5 error when packet doesn't have SOP or EOP on read response
+  #define BTB_REG_INT_STS_5_RC_PKT5_PROTOCOL_ERROR_SHIFT                                                     2
+  #define BTB_REG_INT_STS_5_RC_PKT5_SIDE_FIFO_ERROR                                                          (0x1<<3) // Read packet client5 side info FIFO error
+  #define BTB_REG_INT_STS_5_RC_PKT5_SIDE_FIFO_ERROR_SHIFT                                                    3
+  #define BTB_REG_INT_STS_5_RC_PKT5_REQ_FIFO_ERROR                                                           (0x1<<4) // Read packet client5 request FIFO error
+  #define BTB_REG_INT_STS_5_RC_PKT5_REQ_FIFO_ERROR_SHIFT                                                     4
+  #define BTB_REG_INT_STS_5_RC_PKT5_BLK_FIFO_ERROR                                                           (0x1<<5) // Read packet client5 block FIFO error
+  #define BTB_REG_INT_STS_5_RC_PKT5_BLK_FIFO_ERROR_SHIFT                                                     5
+  #define BTB_REG_INT_STS_5_RC_PKT5_RLS_LEFT_FIFO_ERROR                                                      (0x1<<6) // Read packet client5 releases left FIFO error
+  #define BTB_REG_INT_STS_5_RC_PKT5_RLS_LEFT_FIFO_ERROR_SHIFT                                                6
+  #define BTB_REG_INT_STS_5_RC_PKT5_STRT_PTR_FIFO_ERROR                                                      (0x1<<7) // Read packet client5 start pointer FIFO error
+  #define BTB_REG_INT_STS_5_RC_PKT5_STRT_PTR_FIFO_ERROR_SHIFT                                                7
+  #define BTB_REG_INT_STS_5_RC_PKT5_SECOND_PTR_FIFO_ERROR                                                    (0x1<<8) // Read packet client5 second pointer FIFO
+  #define BTB_REG_INT_STS_5_RC_PKT5_SECOND_PTR_FIFO_ERROR_SHIFT                                              8
+  #define BTB_REG_INT_STS_5_RC_PKT5_RSP_FIFO_ERROR                                                           (0x1<<9) // Read packet client5 response FIFO error
+  #define BTB_REG_INT_STS_5_RC_PKT5_RSP_FIFO_ERROR_SHIFT                                                     9
+  #define BTB_REG_INT_STS_5_RC_PKT5_DSCR_FIFO_ERROR                                                          (0x1<<10) // Read packet client5 descriptor FIFO error
+  #define BTB_REG_INT_STS_5_RC_PKT5_DSCR_FIFO_ERROR_SHIFT                                                    10
+  #define BTB_REG_INT_STS_5_RC_PKT6_RLS_ERROR                                                                (0x1<<11) // Read packet client6 error when number of requested packet copies is bigger than real number of packet copies
+  #define BTB_REG_INT_STS_5_RC_PKT6_RLS_ERROR_SHIFT                                                          11
+  #define BTB_REG_INT_STS_5_RC_PKT6_LEN_ERROR                                                                (0x1<<12) // Read packet client6 length error when requested packet length is bigger than real packet length
+  #define BTB_REG_INT_STS_5_RC_PKT6_LEN_ERROR_SHIFT                                                          12
+  #define BTB_REG_INT_STS_5_RC_PKT6_PROTOCOL_ERROR                                                           (0x1<<13) // Read packet client6 error when packet doesn't have SOP or EOP on read response
+  #define BTB_REG_INT_STS_5_RC_PKT6_PROTOCOL_ERROR_SHIFT                                                     13
+  #define BTB_REG_INT_STS_5_RC_PKT6_SIDE_FIFO_ERROR                                                          (0x1<<14) // Read packet client6 side info FIFO error
+  #define BTB_REG_INT_STS_5_RC_PKT6_SIDE_FIFO_ERROR_SHIFT                                                    14
+  #define BTB_REG_INT_STS_5_RC_PKT6_REQ_FIFO_ERROR                                                           (0x1<<15) // Read packet client6 request FIFO error
+  #define BTB_REG_INT_STS_5_RC_PKT6_REQ_FIFO_ERROR_SHIFT                                                     15
+  #define BTB_REG_INT_STS_5_RC_PKT6_BLK_FIFO_ERROR                                                           (0x1<<16) // Read packet client6 block FIFO error
+  #define BTB_REG_INT_STS_5_RC_PKT6_BLK_FIFO_ERROR_SHIFT                                                     16
+  #define BTB_REG_INT_STS_5_RC_PKT6_RLS_LEFT_FIFO_ERROR                                                      (0x1<<17) // Read packet client6 releases left FIFO error
+  #define BTB_REG_INT_STS_5_RC_PKT6_RLS_LEFT_FIFO_ERROR_SHIFT                                                17
+  #define BTB_REG_INT_STS_5_RC_PKT6_STRT_PTR_FIFO_ERROR                                                      (0x1<<18) // Read packet client6 start pointer FIFO error
+  #define BTB_REG_INT_STS_5_RC_PKT6_STRT_PTR_FIFO_ERROR_SHIFT                                                18
+  #define BTB_REG_INT_STS_5_RC_PKT6_SECOND_PTR_FIFO_ERROR                                                    (0x1<<19) // Read packet client6 second pointer FIFO
+  #define BTB_REG_INT_STS_5_RC_PKT6_SECOND_PTR_FIFO_ERROR_SHIFT                                              19
+  #define BTB_REG_INT_STS_5_RC_PKT6_RSP_FIFO_ERROR                                                           (0x1<<20) // Read packet client6 response FIFO error
+  #define BTB_REG_INT_STS_5_RC_PKT6_RSP_FIFO_ERROR_SHIFT                                                     20
+  #define BTB_REG_INT_STS_5_RC_PKT6_DSCR_FIFO_ERROR                                                          (0x1<<21) // Read packet client6 descriptor FIFO error
+  #define BTB_REG_INT_STS_5_RC_PKT6_DSCR_FIFO_ERROR_SHIFT                                                    21
+  #define BTB_REG_INT_STS_5_RC_PKT7_RLS_ERROR                                                                (0x1<<22) // Read packet client7 error when number of requested packet copies is bigger than real number of packet copies
+  #define BTB_REG_INT_STS_5_RC_PKT7_RLS_ERROR_SHIFT                                                          22
+  #define BTB_REG_INT_STS_5_RC_PKT7_LEN_ERROR                                                                (0x1<<23) // Read packet client7 length error when requested packet length is bigger than real packet length
+  #define BTB_REG_INT_STS_5_RC_PKT7_LEN_ERROR_SHIFT                                                          23
+  #define BTB_REG_INT_STS_5_RC_PKT7_PROTOCOL_ERROR                                                           (0x1<<24) // Read packet client7 error when packet doesn't have SOP or EOP on read response
+  #define BTB_REG_INT_STS_5_RC_PKT7_PROTOCOL_ERROR_SHIFT                                                     24
+  #define BTB_REG_INT_STS_5_RC_PKT7_SIDE_FIFO_ERROR                                                          (0x1<<25) // Read packet client7 side info FIFO error
+  #define BTB_REG_INT_STS_5_RC_PKT7_SIDE_FIFO_ERROR_SHIFT                                                    25
+  #define BTB_REG_INT_STS_5_RC_PKT7_REQ_FIFO_ERROR                                                           (0x1<<26) // Read packet client7 request FIFO error
+  #define BTB_REG_INT_STS_5_RC_PKT7_REQ_FIFO_ERROR_SHIFT                                                     26
+  #define BTB_REG_INT_STS_5_RC_PKT7_BLK_FIFO_ERROR                                                           (0x1<<27) // Read packet client7 block FIFO error
+  #define BTB_REG_INT_STS_5_RC_PKT7_BLK_FIFO_ERROR_SHIFT                                                     27
+  #define BTB_REG_INT_STS_5_RC_PKT7_RLS_LEFT_FIFO_ERROR                                                      (0x1<<28) // Read packet client7 releases left FIFO error
+  #define BTB_REG_INT_STS_5_RC_PKT7_RLS_LEFT_FIFO_ERROR_SHIFT                                                28
+  #define BTB_REG_INT_STS_5_RC_PKT7_STRT_PTR_FIFO_ERROR                                                      (0x1<<29) // Read packet client7 start pointer FIFO error
+  #define BTB_REG_INT_STS_5_RC_PKT7_STRT_PTR_FIFO_ERROR_SHIFT                                                29
+  #define BTB_REG_INT_STS_5_RC_PKT7_SECOND_PTR_FIFO_ERROR                                                    (0x1<<30) // Read packet client7 second pointer FIFO
+  #define BTB_REG_INT_STS_5_RC_PKT7_SECOND_PTR_FIFO_ERROR_SHIFT                                              30
+  #define BTB_REG_INT_STS_5_RC_PKT7_RSP_FIFO_ERROR                                                           (0x1<<31) // Read packet client7 response FIFO error
+  #define BTB_REG_INT_STS_5_RC_PKT7_RSP_FIFO_ERROR_SHIFT                                                     31
+#define BTB_REG_INT_MASK_5                                                                                   0xdb013cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define BTB_REG_INT_MASK_5_RC_PKT5_RLS_ERROR                                                               (0x1<<0) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_RLS_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT5_RLS_ERROR_SHIFT                                                         0
+  #define BTB_REG_INT_MASK_5_RC_PKT5_LEN_ERROR                                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_LEN_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT5_LEN_ERROR_SHIFT                                                         1
+  #define BTB_REG_INT_MASK_5_RC_PKT5_PROTOCOL_ERROR                                                          (0x1<<2) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_PROTOCOL_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT5_PROTOCOL_ERROR_SHIFT                                                    2
+  #define BTB_REG_INT_MASK_5_RC_PKT5_SIDE_FIFO_ERROR                                                         (0x1<<3) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_SIDE_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT5_SIDE_FIFO_ERROR_SHIFT                                                   3
+  #define BTB_REG_INT_MASK_5_RC_PKT5_REQ_FIFO_ERROR                                                          (0x1<<4) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_REQ_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT5_REQ_FIFO_ERROR_SHIFT                                                    4
+  #define BTB_REG_INT_MASK_5_RC_PKT5_BLK_FIFO_ERROR                                                          (0x1<<5) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_BLK_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT5_BLK_FIFO_ERROR_SHIFT                                                    5
+  #define BTB_REG_INT_MASK_5_RC_PKT5_RLS_LEFT_FIFO_ERROR                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_RLS_LEFT_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT5_RLS_LEFT_FIFO_ERROR_SHIFT                                               6
+  #define BTB_REG_INT_MASK_5_RC_PKT5_STRT_PTR_FIFO_ERROR                                                     (0x1<<7) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_STRT_PTR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT5_STRT_PTR_FIFO_ERROR_SHIFT                                               7
+  #define BTB_REG_INT_MASK_5_RC_PKT5_SECOND_PTR_FIFO_ERROR                                                   (0x1<<8) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_SECOND_PTR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT5_SECOND_PTR_FIFO_ERROR_SHIFT                                             8
+  #define BTB_REG_INT_MASK_5_RC_PKT5_RSP_FIFO_ERROR                                                          (0x1<<9) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_RSP_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT5_RSP_FIFO_ERROR_SHIFT                                                    9
+  #define BTB_REG_INT_MASK_5_RC_PKT5_DSCR_FIFO_ERROR                                                         (0x1<<10) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_DSCR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT5_DSCR_FIFO_ERROR_SHIFT                                                   10
+  #define BTB_REG_INT_MASK_5_RC_PKT6_RLS_ERROR                                                               (0x1<<11) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_RLS_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT6_RLS_ERROR_SHIFT                                                         11
+  #define BTB_REG_INT_MASK_5_RC_PKT6_LEN_ERROR                                                               (0x1<<12) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_LEN_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT6_LEN_ERROR_SHIFT                                                         12
+  #define BTB_REG_INT_MASK_5_RC_PKT6_PROTOCOL_ERROR                                                          (0x1<<13) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_PROTOCOL_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT6_PROTOCOL_ERROR_SHIFT                                                    13
+  #define BTB_REG_INT_MASK_5_RC_PKT6_SIDE_FIFO_ERROR                                                         (0x1<<14) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_SIDE_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT6_SIDE_FIFO_ERROR_SHIFT                                                   14
+  #define BTB_REG_INT_MASK_5_RC_PKT6_REQ_FIFO_ERROR                                                          (0x1<<15) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_REQ_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT6_REQ_FIFO_ERROR_SHIFT                                                    15
+  #define BTB_REG_INT_MASK_5_RC_PKT6_BLK_FIFO_ERROR                                                          (0x1<<16) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_BLK_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT6_BLK_FIFO_ERROR_SHIFT                                                    16
+  #define BTB_REG_INT_MASK_5_RC_PKT6_RLS_LEFT_FIFO_ERROR                                                     (0x1<<17) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_RLS_LEFT_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT6_RLS_LEFT_FIFO_ERROR_SHIFT                                               17
+  #define BTB_REG_INT_MASK_5_RC_PKT6_STRT_PTR_FIFO_ERROR                                                     (0x1<<18) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_STRT_PTR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT6_STRT_PTR_FIFO_ERROR_SHIFT                                               18
+  #define BTB_REG_INT_MASK_5_RC_PKT6_SECOND_PTR_FIFO_ERROR                                                   (0x1<<19) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_SECOND_PTR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT6_SECOND_PTR_FIFO_ERROR_SHIFT                                             19
+  #define BTB_REG_INT_MASK_5_RC_PKT6_RSP_FIFO_ERROR                                                          (0x1<<20) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_RSP_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT6_RSP_FIFO_ERROR_SHIFT                                                    20
+  #define BTB_REG_INT_MASK_5_RC_PKT6_DSCR_FIFO_ERROR                                                         (0x1<<21) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_DSCR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT6_DSCR_FIFO_ERROR_SHIFT                                                   21
+  #define BTB_REG_INT_MASK_5_RC_PKT7_RLS_ERROR                                                               (0x1<<22) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_RLS_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT7_RLS_ERROR_SHIFT                                                         22
+  #define BTB_REG_INT_MASK_5_RC_PKT7_LEN_ERROR                                                               (0x1<<23) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_LEN_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT7_LEN_ERROR_SHIFT                                                         23
+  #define BTB_REG_INT_MASK_5_RC_PKT7_PROTOCOL_ERROR                                                          (0x1<<24) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_PROTOCOL_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT7_PROTOCOL_ERROR_SHIFT                                                    24
+  #define BTB_REG_INT_MASK_5_RC_PKT7_SIDE_FIFO_ERROR                                                         (0x1<<25) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_SIDE_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT7_SIDE_FIFO_ERROR_SHIFT                                                   25
+  #define BTB_REG_INT_MASK_5_RC_PKT7_REQ_FIFO_ERROR                                                          (0x1<<26) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_REQ_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT7_REQ_FIFO_ERROR_SHIFT                                                    26
+  #define BTB_REG_INT_MASK_5_RC_PKT7_BLK_FIFO_ERROR                                                          (0x1<<27) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_BLK_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT7_BLK_FIFO_ERROR_SHIFT                                                    27
+  #define BTB_REG_INT_MASK_5_RC_PKT7_RLS_LEFT_FIFO_ERROR                                                     (0x1<<28) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_RLS_LEFT_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT7_RLS_LEFT_FIFO_ERROR_SHIFT                                               28
+  #define BTB_REG_INT_MASK_5_RC_PKT7_STRT_PTR_FIFO_ERROR                                                     (0x1<<29) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_STRT_PTR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT7_STRT_PTR_FIFO_ERROR_SHIFT                                               29
+  #define BTB_REG_INT_MASK_5_RC_PKT7_SECOND_PTR_FIFO_ERROR                                                   (0x1<<30) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_SECOND_PTR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT7_SECOND_PTR_FIFO_ERROR_SHIFT                                             30
+  #define BTB_REG_INT_MASK_5_RC_PKT7_RSP_FIFO_ERROR                                                          (0x1<<31) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_RSP_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_5_RC_PKT7_RSP_FIFO_ERROR_SHIFT                                                    31
+#define BTB_REG_INT_STS_WR_5                                                                                 0xdb0140UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define BTB_REG_INT_STS_WR_5_RC_PKT5_RLS_ERROR                                                             (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
+  #define BTB_REG_INT_STS_WR_5_RC_PKT5_RLS_ERROR_SHIFT                                                       0
+  #define BTB_REG_INT_STS_WR_5_RC_PKT5_LEN_ERROR                                                             (0x1<<1) // Read packet client5 length error when requested packet length is bigger than real packet length
+  #define BTB_REG_INT_STS_WR_5_RC_PKT5_LEN_ERROR_SHIFT                                                       1
+  #define BTB_REG_INT_STS_WR_5_RC_PKT5_PROTOCOL_ERROR                                                        (0x1<<2) // Read packet client5 error when packet doesn't have SOP or EOP on read response
+  #define BTB_REG_INT_STS_WR_5_RC_PKT5_PROTOCOL_ERROR_SHIFT                                                  2
+  #define BTB_REG_INT_STS_WR_5_RC_PKT5_SIDE_FIFO_ERROR                                                       (0x1<<3) // Read packet client5 side info FIFO error
+  #define BTB_REG_INT_STS_WR_5_RC_PKT5_SIDE_FIFO_ERROR_SHIFT                                                 3
+  #define BTB_REG_INT_STS_WR_5_RC_PKT5_REQ_FIFO_ERROR                                                        (0x1<<4) // Read packet client5 request FIFO error
+  #define BTB_REG_INT_STS_WR_5_RC_PKT5_REQ_FIFO_ERROR_SHIFT                                                  4
+  #define BTB_REG_INT_STS_WR_5_RC_PKT5_BLK_FIFO_ERROR                                                        (0x1<<5) // Read packet client5 block FIFO error
+  #define BTB_REG_INT_STS_WR_5_RC_PKT5_BLK_FIFO_ERROR_SHIFT                                                  5
+  #define BTB_REG_INT_STS_WR_5_RC_PKT5_RLS_LEFT_FIFO_ERROR                                                   (0x1<<6) // Read packet client5 releases left FIFO error
+  #define BTB_REG_INT_STS_WR_5_RC_PKT5_RLS_LEFT_FIFO_ERROR_SHIFT                                             6
+  #define BTB_REG_INT_STS_WR_5_RC_PKT5_STRT_PTR_FIFO_ERROR                                                   (0x1<<7) // Read packet client5 start pointer FIFO error
+  #define BTB_REG_INT_STS_WR_5_RC_PKT5_STRT_PTR_FIFO_ERROR_SHIFT                                             7
+  #define BTB_REG_INT_STS_WR_5_RC_PKT5_SECOND_PTR_FIFO_ERROR                                                 (0x1<<8) // Read packet client5 second pointer FIFO
+  #define BTB_REG_INT_STS_WR_5_RC_PKT5_SECOND_PTR_FIFO_ERROR_SHIFT                                           8
+  #define BTB_REG_INT_STS_WR_5_RC_PKT5_RSP_FIFO_ERROR                                                        (0x1<<9) // Read packet client5 response FIFO error
+  #define BTB_REG_INT_STS_WR_5_RC_PKT5_RSP_FIFO_ERROR_SHIFT                                                  9
+  #define BTB_REG_INT_STS_WR_5_RC_PKT5_DSCR_FIFO_ERROR                                                       (0x1<<10) // Read packet client5 descriptor FIFO error
+  #define BTB_REG_INT_STS_WR_5_RC_PKT5_DSCR_FIFO_ERROR_SHIFT                                                 10
+  #define BTB_REG_INT_STS_WR_5_RC_PKT6_RLS_ERROR                                                             (0x1<<11) // Read packet client6 error when number of requested packet copies is bigger than real number of packet copies
+  #define BTB_REG_INT_STS_WR_5_RC_PKT6_RLS_ERROR_SHIFT                                                       11
+  #define BTB_REG_INT_STS_WR_5_RC_PKT6_LEN_ERROR                                                             (0x1<<12) // Read packet client6 length error when requested packet length is bigger than real packet length
+  #define BTB_REG_INT_STS_WR_5_RC_PKT6_LEN_ERROR_SHIFT                                                       12
+  #define BTB_REG_INT_STS_WR_5_RC_PKT6_PROTOCOL_ERROR                                                        (0x1<<13) // Read packet client6 error when packet doesn't have SOP or EOP on read response
+  #define BTB_REG_INT_STS_WR_5_RC_PKT6_PROTOCOL_ERROR_SHIFT                                                  13
+  #define BTB_REG_INT_STS_WR_5_RC_PKT6_SIDE_FIFO_ERROR                                                       (0x1<<14) // Read packet client6 side info FIFO error
+  #define BTB_REG_INT_STS_WR_5_RC_PKT6_SIDE_FIFO_ERROR_SHIFT                                                 14
+  #define BTB_REG_INT_STS_WR_5_RC_PKT6_REQ_FIFO_ERROR                                                        (0x1<<15) // Read packet client6 request FIFO error
+  #define BTB_REG_INT_STS_WR_5_RC_PKT6_REQ_FIFO_ERROR_SHIFT                                                  15
+  #define BTB_REG_INT_STS_WR_5_RC_PKT6_BLK_FIFO_ERROR                                                        (0x1<<16) // Read packet client6 block FIFO error
+  #define BTB_REG_INT_STS_WR_5_RC_PKT6_BLK_FIFO_ERROR_SHIFT                                                  16
+  #define BTB_REG_INT_STS_WR_5_RC_PKT6_RLS_LEFT_FIFO_ERROR                                                   (0x1<<17) // Read packet client6 releases left FIFO error
+  #define BTB_REG_INT_STS_WR_5_RC_PKT6_RLS_LEFT_FIFO_ERROR_SHIFT                                             17
+  #define BTB_REG_INT_STS_WR_5_RC_PKT6_STRT_PTR_FIFO_ERROR                                                   (0x1<<18) // Read packet client6 start pointer FIFO error
+  #define BTB_REG_INT_STS_WR_5_RC_PKT6_STRT_PTR_FIFO_ERROR_SHIFT                                             18
+  #define BTB_REG_INT_STS_WR_5_RC_PKT6_SECOND_PTR_FIFO_ERROR                                                 (0x1<<19) // Read packet client6 second pointer FIFO
+  #define BTB_REG_INT_STS_WR_5_RC_PKT6_SECOND_PTR_FIFO_ERROR_SHIFT                                           19
+  #define BTB_REG_INT_STS_WR_5_RC_PKT6_RSP_FIFO_ERROR                                                        (0x1<<20) // Read packet client6 response FIFO error
+  #define BTB_REG_INT_STS_WR_5_RC_PKT6_RSP_FIFO_ERROR_SHIFT                                                  20
+  #define BTB_REG_INT_STS_WR_5_RC_PKT6_DSCR_FIFO_ERROR                                                       (0x1<<21) // Read packet client6 descriptor FIFO error
+  #define BTB_REG_INT_STS_WR_5_RC_PKT6_DSCR_FIFO_ERROR_SHIFT                                                 21
+  #define BTB_REG_INT_STS_WR_5_RC_PKT7_RLS_ERROR                                                             (0x1<<22) // Read packet client7 error when number of requested packet copies is bigger than real number of packet copies
+  #define BTB_REG_INT_STS_WR_5_RC_PKT7_RLS_ERROR_SHIFT                                                       22
+  #define BTB_REG_INT_STS_WR_5_RC_PKT7_LEN_ERROR                                                             (0x1<<23) // Read packet client7 length error when requested packet length is bigger than real packet length
+  #define BTB_REG_INT_STS_WR_5_RC_PKT7_LEN_ERROR_SHIFT                                                       23
+  #define BTB_REG_INT_STS_WR_5_RC_PKT7_PROTOCOL_ERROR                                                        (0x1<<24) // Read packet client7 error when packet doesn't have SOP or EOP on read response
+  #define BTB_REG_INT_STS_WR_5_RC_PKT7_PROTOCOL_ERROR_SHIFT                                                  24
+  #define BTB_REG_INT_STS_WR_5_RC_PKT7_SIDE_FIFO_ERROR                                                       (0x1<<25) // Read packet client7 side info FIFO error
+  #define BTB_REG_INT_STS_WR_5_RC_PKT7_SIDE_FIFO_ERROR_SHIFT                                                 25
+  #define BTB_REG_INT_STS_WR_5_RC_PKT7_REQ_FIFO_ERROR                                                        (0x1<<26) // Read packet client7 request FIFO error
+  #define BTB_REG_INT_STS_WR_5_RC_PKT7_REQ_FIFO_ERROR_SHIFT                                                  26
+  #define BTB_REG_INT_STS_WR_5_RC_PKT7_BLK_FIFO_ERROR                                                        (0x1<<27) // Read packet client7 block FIFO error
+  #define BTB_REG_INT_STS_WR_5_RC_PKT7_BLK_FIFO_ERROR_SHIFT                                                  27
+  #define BTB_REG_INT_STS_WR_5_RC_PKT7_RLS_LEFT_FIFO_ERROR                                                   (0x1<<28) // Read packet client7 releases left FIFO error
+  #define BTB_REG_INT_STS_WR_5_RC_PKT7_RLS_LEFT_FIFO_ERROR_SHIFT                                             28
+  #define BTB_REG_INT_STS_WR_5_RC_PKT7_STRT_PTR_FIFO_ERROR                                                   (0x1<<29) // Read packet client7 start pointer FIFO error
+  #define BTB_REG_INT_STS_WR_5_RC_PKT7_STRT_PTR_FIFO_ERROR_SHIFT                                             29
+  #define BTB_REG_INT_STS_WR_5_RC_PKT7_SECOND_PTR_FIFO_ERROR                                                 (0x1<<30) // Read packet client7 second pointer FIFO
+  #define BTB_REG_INT_STS_WR_5_RC_PKT7_SECOND_PTR_FIFO_ERROR_SHIFT                                           30
+  #define BTB_REG_INT_STS_WR_5_RC_PKT7_RSP_FIFO_ERROR                                                        (0x1<<31) // Read packet client7 response FIFO error
+  #define BTB_REG_INT_STS_WR_5_RC_PKT7_RSP_FIFO_ERROR_SHIFT                                                  31
+#define BTB_REG_INT_STS_CLR_5                                                                                0xdb0144UL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT5_RLS_ERROR                                                            (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT5_RLS_ERROR_SHIFT                                                      0
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT5_LEN_ERROR                                                            (0x1<<1) // Read packet client5 length error when requested packet length is bigger than real packet length
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT5_LEN_ERROR_SHIFT                                                      1
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT5_PROTOCOL_ERROR                                                       (0x1<<2) // Read packet client5 error when packet doesn't have SOP or EOP on read response
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT5_PROTOCOL_ERROR_SHIFT                                                 2
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT5_SIDE_FIFO_ERROR                                                      (0x1<<3) // Read packet client5 side info FIFO error
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT5_SIDE_FIFO_ERROR_SHIFT                                                3
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT5_REQ_FIFO_ERROR                                                       (0x1<<4) // Read packet client5 request FIFO error
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT5_REQ_FIFO_ERROR_SHIFT                                                 4
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT5_BLK_FIFO_ERROR                                                       (0x1<<5) // Read packet client5 block FIFO error
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT5_BLK_FIFO_ERROR_SHIFT                                                 5
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT5_RLS_LEFT_FIFO_ERROR                                                  (0x1<<6) // Read packet client5 releases left FIFO error
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT5_RLS_LEFT_FIFO_ERROR_SHIFT                                            6
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT5_STRT_PTR_FIFO_ERROR                                                  (0x1<<7) // Read packet client5 start pointer FIFO error
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT5_STRT_PTR_FIFO_ERROR_SHIFT                                            7
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT5_SECOND_PTR_FIFO_ERROR                                                (0x1<<8) // Read packet client5 second pointer FIFO
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT5_SECOND_PTR_FIFO_ERROR_SHIFT                                          8
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT5_RSP_FIFO_ERROR                                                       (0x1<<9) // Read packet client5 response FIFO error
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT5_RSP_FIFO_ERROR_SHIFT                                                 9
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT5_DSCR_FIFO_ERROR                                                      (0x1<<10) // Read packet client5 descriptor FIFO error
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT5_DSCR_FIFO_ERROR_SHIFT                                                10
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT6_RLS_ERROR                                                            (0x1<<11) // Read packet client6 error when number of requested packet copies is bigger than real number of packet copies
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT6_RLS_ERROR_SHIFT                                                      11
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT6_LEN_ERROR                                                            (0x1<<12) // Read packet client6 length error when requested packet length is bigger than real packet length
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT6_LEN_ERROR_SHIFT                                                      12
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT6_PROTOCOL_ERROR                                                       (0x1<<13) // Read packet client6 error when packet doesn't have SOP or EOP on read response
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT6_PROTOCOL_ERROR_SHIFT                                                 13
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT6_SIDE_FIFO_ERROR                                                      (0x1<<14) // Read packet client6 side info FIFO error
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT6_SIDE_FIFO_ERROR_SHIFT                                                14
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT6_REQ_FIFO_ERROR                                                       (0x1<<15) // Read packet client6 request FIFO error
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT6_REQ_FIFO_ERROR_SHIFT                                                 15
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT6_BLK_FIFO_ERROR                                                       (0x1<<16) // Read packet client6 block FIFO error
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT6_BLK_FIFO_ERROR_SHIFT                                                 16
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT6_RLS_LEFT_FIFO_ERROR                                                  (0x1<<17) // Read packet client6 releases left FIFO error
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT6_RLS_LEFT_FIFO_ERROR_SHIFT                                            17
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT6_STRT_PTR_FIFO_ERROR                                                  (0x1<<18) // Read packet client6 start pointer FIFO error
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT6_STRT_PTR_FIFO_ERROR_SHIFT                                            18
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT6_SECOND_PTR_FIFO_ERROR                                                (0x1<<19) // Read packet client6 second pointer FIFO
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT6_SECOND_PTR_FIFO_ERROR_SHIFT                                          19
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT6_RSP_FIFO_ERROR                                                       (0x1<<20) // Read packet client6 response FIFO error
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT6_RSP_FIFO_ERROR_SHIFT                                                 20
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT6_DSCR_FIFO_ERROR                                                      (0x1<<21) // Read packet client6 descriptor FIFO error
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT6_DSCR_FIFO_ERROR_SHIFT                                                21
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT7_RLS_ERROR                                                            (0x1<<22) // Read packet client7 error when number of requested packet copies is bigger than real number of packet copies
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT7_RLS_ERROR_SHIFT                                                      22
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT7_LEN_ERROR                                                            (0x1<<23) // Read packet client7 length error when requested packet length is bigger than real packet length
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT7_LEN_ERROR_SHIFT                                                      23
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT7_PROTOCOL_ERROR                                                       (0x1<<24) // Read packet client7 error when packet doesn't have SOP or EOP on read response
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT7_PROTOCOL_ERROR_SHIFT                                                 24
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT7_SIDE_FIFO_ERROR                                                      (0x1<<25) // Read packet client7 side info FIFO error
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT7_SIDE_FIFO_ERROR_SHIFT                                                25
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT7_REQ_FIFO_ERROR                                                       (0x1<<26) // Read packet client7 request FIFO error
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT7_REQ_FIFO_ERROR_SHIFT                                                 26
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT7_BLK_FIFO_ERROR                                                       (0x1<<27) // Read packet client7 block FIFO error
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT7_BLK_FIFO_ERROR_SHIFT                                                 27
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT7_RLS_LEFT_FIFO_ERROR                                                  (0x1<<28) // Read packet client7 releases left FIFO error
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT7_RLS_LEFT_FIFO_ERROR_SHIFT                                            28
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT7_STRT_PTR_FIFO_ERROR                                                  (0x1<<29) // Read packet client7 start pointer FIFO error
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT7_STRT_PTR_FIFO_ERROR_SHIFT                                            29
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT7_SECOND_PTR_FIFO_ERROR                                                (0x1<<30) // Read packet client7 second pointer FIFO
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT7_SECOND_PTR_FIFO_ERROR_SHIFT                                          30
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT7_RSP_FIFO_ERROR                                                       (0x1<<31) // Read packet client7 response FIFO error
+  #define BTB_REG_INT_STS_CLR_5_RC_PKT7_RSP_FIFO_ERROR_SHIFT                                                 31
+#define BTB_REG_INT_STS_6                                                                                    0xdb0150UL //Access:R    DataWidth:0x1    // Multi Field Register.
+  #define BTB_REG_INT_STS_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR                                            (0x1<<0) // Packet available SYNC FIFO error
+  #define BTB_REG_INT_STS_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR_SHIFT                                      0
+#define BTB_REG_INT_MASK_6                                                                                   0xdb0154UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define BTB_REG_INT_MASK_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR                                           (0x1<<0) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_6.PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR .
+  #define BTB_REG_INT_MASK_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR_SHIFT                                     0
+#define BTB_REG_INT_STS_WR_6                                                                                 0xdb0158UL //Access:WR   DataWidth:0x1    // Multi Field Register.
+  #define BTB_REG_INT_STS_WR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR                                         (0x1<<0) // Packet available SYNC FIFO error
+  #define BTB_REG_INT_STS_WR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR_SHIFT                                   0
+#define BTB_REG_INT_STS_CLR_6                                                                                0xdb015cUL //Access:RC   DataWidth:0x1    // Multi Field Register.
+  #define BTB_REG_INT_STS_CLR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR                                        (0x1<<0) // Packet available SYNC FIFO error
+  #define BTB_REG_INT_STS_CLR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR_SHIFT                                  0
+#define BTB_REG_INT_STS_8                                                                                    0xdb0184UL //Access:R    DataWidth:0x1    // Multi Field Register.
+  #define BTB_REG_INT_STS_8_WC6_NOTIFY_FIFO_ERROR                                                            (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
+  #define BTB_REG_INT_STS_8_WC6_NOTIFY_FIFO_ERROR_SHIFT                                                      0
+#define BTB_REG_INT_MASK_8                                                                                   0xdb0188UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define BTB_REG_INT_MASK_8_WC6_NOTIFY_FIFO_ERROR                                                           (0x1<<0) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_8.WC6_NOTIFY_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_8_WC6_NOTIFY_FIFO_ERROR_SHIFT                                                     0
+#define BTB_REG_INT_STS_WR_8                                                                                 0xdb018cUL //Access:WR   DataWidth:0x1    // Multi Field Register.
+  #define BTB_REG_INT_STS_WR_8_WC6_NOTIFY_FIFO_ERROR                                                         (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
+  #define BTB_REG_INT_STS_WR_8_WC6_NOTIFY_FIFO_ERROR_SHIFT                                                   0
+#define BTB_REG_INT_STS_CLR_8                                                                                0xdb0190UL //Access:RC   DataWidth:0x1    // Multi Field Register.
+  #define BTB_REG_INT_STS_CLR_8_WC6_NOTIFY_FIFO_ERROR                                                        (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
+  #define BTB_REG_INT_STS_CLR_8_WC6_NOTIFY_FIFO_ERROR_SHIFT                                                  0
+#define BTB_REG_INT_STS_9                                                                                    0xdb019cUL //Access:R    DataWidth:0x1    // Multi Field Register.
+  #define BTB_REG_INT_STS_9_WC9_QUEUE_FIFO_ERROR                                                             (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
+  #define BTB_REG_INT_STS_9_WC9_QUEUE_FIFO_ERROR_SHIFT                                                       0
+#define BTB_REG_INT_MASK_9                                                                                   0xdb01a0UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define BTB_REG_INT_MASK_9_WC9_QUEUE_FIFO_ERROR                                                            (0x1<<0) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_9.WC9_QUEUE_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_9_WC9_QUEUE_FIFO_ERROR_SHIFT                                                      0
+#define BTB_REG_INT_STS_WR_9                                                                                 0xdb01a4UL //Access:WR   DataWidth:0x1    // Multi Field Register.
+  #define BTB_REG_INT_STS_WR_9_WC9_QUEUE_FIFO_ERROR                                                          (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
+  #define BTB_REG_INT_STS_WR_9_WC9_QUEUE_FIFO_ERROR_SHIFT                                                    0
+#define BTB_REG_INT_STS_CLR_9                                                                                0xdb01a8UL //Access:RC   DataWidth:0x1    // Multi Field Register.
+  #define BTB_REG_INT_STS_CLR_9_WC9_QUEUE_FIFO_ERROR                                                         (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
+  #define BTB_REG_INT_STS_CLR_9_WC9_QUEUE_FIFO_ERROR_SHIFT                                                   0
+#define BTB_REG_INT_STS_10                                                                                   0xdb01b4UL //Access:R    DataWidth:0x1f   // Multi Field Register.
+  #define BTB_REG_INT_STS_10_WC0_SYNC_FIFO_PUSH_ERROR                                                        (0x1<<30) // WC input SYNC FIFO error
+  #define BTB_REG_INT_STS_10_WC0_SYNC_FIFO_PUSH_ERROR_SHIFT                                                  30
+#define BTB_REG_INT_MASK_10                                                                                  0xdb01b8UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define BTB_REG_INT_MASK_10_WC0_SYNC_FIFO_PUSH_ERROR                                                       (0x1<<30) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_10.WC0_SYNC_FIFO_PUSH_ERROR .
+  #define BTB_REG_INT_MASK_10_WC0_SYNC_FIFO_PUSH_ERROR_SHIFT                                                 30
+#define BTB_REG_INT_STS_WR_10                                                                                0xdb01bcUL //Access:WR   DataWidth:0x1f   // Multi Field Register.
+  #define BTB_REG_INT_STS_WR_10_WC0_SYNC_FIFO_PUSH_ERROR                                                     (0x1<<30) // WC input SYNC FIFO error
+  #define BTB_REG_INT_STS_WR_10_WC0_SYNC_FIFO_PUSH_ERROR_SHIFT                                               30
+#define BTB_REG_INT_STS_CLR_10                                                                               0xdb01c0UL //Access:RC   DataWidth:0x1f   // Multi Field Register.
+  #define BTB_REG_INT_STS_CLR_10_WC0_SYNC_FIFO_PUSH_ERROR                                                    (0x1<<30) // WC input SYNC FIFO error
+  #define BTB_REG_INT_STS_CLR_10_WC0_SYNC_FIFO_PUSH_ERROR_SHIFT                                              30
+#define BTB_REG_INT_STS_11                                                                                   0xdb01ccUL //Access:R    DataWidth:0x13   // Multi Field Register.
+  #define BTB_REG_INT_STS_11_RLS_SYNC_FIFO_PUSH_ERROR                                                        (0x1<<8) // Release SYNC FIFO error
+  #define BTB_REG_INT_STS_11_RLS_SYNC_FIFO_PUSH_ERROR_SHIFT                                                  8
+  #define BTB_REG_INT_STS_11_RC_PKT7_DSCR_FIFO_ERROR                                                         (0x1<<18) // Read packet client7 descriptor FIFO error
+  #define BTB_REG_INT_STS_11_RC_PKT7_DSCR_FIFO_ERROR_SHIFT                                                   18
+#define BTB_REG_INT_MASK_11                                                                                  0xdb01d0UL //Access:RW   DataWidth:0x13   // Multi Field Register.
+  #define BTB_REG_INT_MASK_11_RLS_SYNC_FIFO_PUSH_ERROR                                                       (0x1<<8) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_11.RLS_SYNC_FIFO_PUSH_ERROR .
+  #define BTB_REG_INT_MASK_11_RLS_SYNC_FIFO_PUSH_ERROR_SHIFT                                                 8
+  #define BTB_REG_INT_MASK_11_RC_PKT7_DSCR_FIFO_ERROR                                                        (0x1<<18) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_11.RC_PKT7_DSCR_FIFO_ERROR .
+  #define BTB_REG_INT_MASK_11_RC_PKT7_DSCR_FIFO_ERROR_SHIFT                                                  18
+#define BTB_REG_INT_STS_WR_11                                                                                0xdb01d4UL //Access:WR   DataWidth:0x13   // Multi Field Register.
+  #define BTB_REG_INT_STS_WR_11_RLS_SYNC_FIFO_PUSH_ERROR                                                     (0x1<<8) // Release SYNC FIFO error
+  #define BTB_REG_INT_STS_WR_11_RLS_SYNC_FIFO_PUSH_ERROR_SHIFT                                               8
+  #define BTB_REG_INT_STS_WR_11_RC_PKT7_DSCR_FIFO_ERROR                                                      (0x1<<18) // Read packet client7 descriptor FIFO error
+  #define BTB_REG_INT_STS_WR_11_RC_PKT7_DSCR_FIFO_ERROR_SHIFT                                                18
+#define BTB_REG_INT_STS_CLR_11                                                                               0xdb01d8UL //Access:RC   DataWidth:0x13   // Multi Field Register.
+  #define BTB_REG_INT_STS_CLR_11_RLS_SYNC_FIFO_PUSH_ERROR                                                    (0x1<<8) // Release SYNC FIFO error
+  #define BTB_REG_INT_STS_CLR_11_RLS_SYNC_FIFO_PUSH_ERROR_SHIFT                                              8
+  #define BTB_REG_INT_STS_CLR_11_RC_PKT7_DSCR_FIFO_ERROR                                                     (0x1<<18) // Read packet client7 descriptor FIFO error
+  #define BTB_REG_INT_STS_CLR_11_RC_PKT7_DSCR_FIFO_ERROR_SHIFT                                               18
+#define BTB_REG_PRTY_MASK                                                                                    0xdb01e0UL //Access:RW   DataWidth:0x5    // Multi Field Register.
+  #define BTB_REG_PRTY_MASK_LL_BANK0_MEM_PRTY                                                                (0x1<<0) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS.LL_BANK0_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_LL_BANK0_MEM_PRTY_SHIFT                                                          0
+  #define BTB_REG_PRTY_MASK_LL_BANK1_MEM_PRTY                                                                (0x1<<1) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS.LL_BANK1_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_LL_BANK1_MEM_PRTY_SHIFT                                                          1
+  #define BTB_REG_PRTY_MASK_LL_BANK2_MEM_PRTY                                                                (0x1<<2) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS.LL_BANK2_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_LL_BANK2_MEM_PRTY_SHIFT                                                          2
+  #define BTB_REG_PRTY_MASK_LL_BANK3_MEM_PRTY                                                                (0x1<<3) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS.LL_BANK3_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_LL_BANK3_MEM_PRTY_SHIFT                                                          3
+  #define BTB_REG_PRTY_MASK_DATAPATH_REGISTERS                                                               (0x1<<4) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS.DATAPATH_REGISTERS .
+  #define BTB_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                                         4
+#define BTB_REG_PRTY_MASK_H_0_BB_K2                                                                          0xdb0404UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define BTB_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_K2                                                    (0x1<<0) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
+  #define BTB_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_K2_SHIFT                                              0
+  #define BTB_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT_BB_K2                                                    (0x1<<1) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM008_I_ECC_RF_INT .
+  #define BTB_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT_BB_K2_SHIFT                                              1
+  #define BTB_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_BB_K2                                                    (0x1<<2) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM009_I_ECC_RF_INT .
+  #define BTB_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_BB_K2_SHIFT                                              2
+  #define BTB_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT_BB_K2                                                    (0x1<<3) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM010_I_ECC_RF_INT .
+  #define BTB_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT_BB_K2_SHIFT                                              3
+  #define BTB_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT_BB_K2                                                    (0x1<<4) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM011_I_ECC_RF_INT .
+  #define BTB_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT_BB_K2_SHIFT                                              4
+  #define BTB_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_BB_K2                                                    (0x1<<5) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM012_I_ECC_RF_INT .
+  #define BTB_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_BB_K2_SHIFT                                              5
+  #define BTB_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT_BB_K2                                                    (0x1<<6) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM013_I_ECC_RF_INT .
+  #define BTB_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT_BB_K2_SHIFT                                              6
+  #define BTB_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_BB_K2                                                    (0x1<<7) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM014_I_ECC_RF_INT .
+  #define BTB_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_BB_K2_SHIFT                                              7
+  #define BTB_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_BB_K2                                                    (0x1<<8) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM015_I_ECC_RF_INT .
+  #define BTB_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_BB_K2_SHIFT                                              8
+  #define BTB_REG_PRTY_MASK_H_0_MEM016_I_ECC_RF_INT_BB_K2                                                    (0x1<<9) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM016_I_ECC_RF_INT .
+  #define BTB_REG_PRTY_MASK_H_0_MEM016_I_ECC_RF_INT_BB_K2_SHIFT                                              9
+  #define BTB_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_BB_K2                                                    (0x1<<10) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT .
+  #define BTB_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_BB_K2_SHIFT                                              10
+  #define BTB_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_BB_K2                                                    (0x1<<11) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
+  #define BTB_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_BB_K2_SHIFT                                              11
+  #define BTB_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_BB_K2                                                    (0x1<<12) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT .
+  #define BTB_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_BB_K2_SHIFT                                              12
+  #define BTB_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_BB_K2                                                    (0x1<<13) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT .
+  #define BTB_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_BB_K2_SHIFT                                              13
+  #define BTB_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_BB_K2                                                    (0x1<<14) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM006_I_ECC_RF_INT .
+  #define BTB_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_BB_K2_SHIFT                                              14
+  #define BTB_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT_BB_K2                                                    (0x1<<15) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM007_I_ECC_RF_INT .
+  #define BTB_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT_BB_K2_SHIFT                                              15
+  #define BTB_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_K2                                                         (0x1<<16) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_K2_SHIFT                                                   16
+  #define BTB_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_K2                                                         (0x1<<17) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_K2_SHIFT                                                   17
+  #define BTB_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_K2                                                         (0x1<<18) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_K2_SHIFT                                                   18
+  #define BTB_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_K2                                                         (0x1<<19) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_K2_SHIFT                                                   19
+  #define BTB_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB                                                         (0x1<<17) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_SHIFT                                                   17
+  #define BTB_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_K2                                                         (0x1<<20) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_K2_SHIFT                                                   20
+  #define BTB_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2                                                         (0x1<<21) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2_SHIFT                                                   21
+  #define BTB_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_K2                                                         (0x1<<22) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_K2_SHIFT                                                   22
+  #define BTB_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2                                                         (0x1<<23) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2_SHIFT                                                   23
+  #define BTB_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2                                                         (0x1<<24) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2_SHIFT                                                   24
+  #define BTB_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB                                                         (0x1<<22) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB_SHIFT                                                   22
+  #define BTB_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_K2                                                         (0x1<<25) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_K2_SHIFT                                                   25
+  #define BTB_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB                                                         (0x1<<21) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_SHIFT                                                   21
+  #define BTB_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_K2                                                         (0x1<<26) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_K2_SHIFT                                                   26
+  #define BTB_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB                                                         (0x1<<20) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_SHIFT                                                   20
+  #define BTB_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2                                                         (0x1<<27) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2_SHIFT                                                   27
+  #define BTB_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB                                                         (0x1<<19) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_SHIFT                                                   19
+  #define BTB_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2                                                         (0x1<<28) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2_SHIFT                                                   28
+  #define BTB_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB                                                         (0x1<<18) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_SHIFT                                                   18
+  #define BTB_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2                                                         (0x1<<29) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2_SHIFT                                                   29
+  #define BTB_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB                                                         (0x1<<16) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_SHIFT                                                   16
+  #define BTB_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2                                                         (0x1<<30) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
+  #define BTB_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2_SHIFT                                                   30
+#define BTB_REG_MEM_ECC_ENABLE_0_BB                                                                          0xdb0450UL //Access:RW   DataWidth:0x10   // Multi Field Register.
+#define BTB_REG_MEM_ECC_ENABLE_0_K2                                                                          0xdb0410UL //Access:RW   DataWidth:0x10   // Multi Field Register.
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_BB_K2                                                     (0x1<<0) // Enable ECC for memory ecc instance btb.BB_BANK_K2_GEN_FOR[0].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_BB_K2_SHIFT                                               0
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_EN_BB_K2                                                     (0x1<<1) // Enable ECC for memory ecc instance btb.BB_BANK_K2_GEN_FOR[1].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_EN_BB_K2_SHIFT                                               1
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_EN_BB_K2                                                     (0x1<<2) // Enable ECC for memory ecc instance btb.BB_BANK_K2_GEN_FOR[2].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_EN_BB_K2_SHIFT                                               2
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_EN_BB_K2                                                     (0x1<<3) // Enable ECC for memory ecc instance btb.BB_BANK_K2_GEN_FOR[3].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_EN_BB_K2_SHIFT                                               3
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_EN_BB_K2                                                     (0x1<<4) // Enable ECC for memory ecc instance btb.BB_BANK_K2_GEN_FOR[4].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_EN_BB_K2_SHIFT                                               4
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN_BB_K2                                                     (0x1<<5) // Enable ECC for memory ecc instance btb.BB_BANK_K2_GEN_FOR[5].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN_BB_K2_SHIFT                                               5
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM013_I_ECC_EN_BB_K2                                                     (0x1<<6) // Enable ECC for memory ecc instance btb.BB_BANK_K2_GEN_FOR[6].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM013_I_ECC_EN_BB_K2_SHIFT                                               6
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN_BB_K2                                                     (0x1<<7) // Enable ECC for memory ecc instance btb.BB_BANK_K2_GEN_FOR[7].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN_BB_K2_SHIFT                                               7
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN_BB_K2                                                     (0x1<<8) // Enable ECC for memory ecc instance btb.BB_BANK_K2_GEN_FOR[8].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN_BB_K2_SHIFT                                               8
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_EN_BB_K2                                                     (0x1<<9) // Enable ECC for memory ecc instance btb.BB_BANK_K2_GEN_FOR[9].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_EN_BB_K2_SHIFT                                               9
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN_BB_K2                                                     (0x1<<10) // Enable ECC for memory ecc instance btb.BB_BANK_K2_GEN_FOR[10].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN_BB_K2_SHIFT                                               10
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_BB_K2                                                     (0x1<<11) // Enable ECC for memory ecc instance btb.BB_BANK_K2_GEN_FOR[11].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_BB_K2_SHIFT                                               11
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_BB_K2                                                     (0x1<<12) // Enable ECC for memory ecc instance btb.BB_BANK_K2_GEN_FOR[12].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_BB_K2_SHIFT                                               12
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_BB_K2                                                     (0x1<<13) // Enable ECC for memory ecc instance btb.BB_BANK_K2_GEN_FOR[13].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_BB_K2_SHIFT                                               13
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN_BB_K2                                                     (0x1<<14) // Enable ECC for memory ecc instance btb.BB_BANK_K2_GEN_FOR[14].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN_BB_K2_SHIFT                                               14
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_EN_BB_K2                                                     (0x1<<15) // Enable ECC for memory ecc instance btb.BB_BANK_K2_GEN_FOR[15].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_EN_BB_K2_SHIFT                                               15
+#define BTB_REG_MEM001_RF_ECC_ERROR_CONNECT_BB                                                               0xdb0410UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: btb.BB_BANK_BB_GEN_FOR[0].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BTB_REG_MEM_ECC_PARITY_ONLY_0_BB                                                                     0xdb0454UL //Access:RW   DataWidth:0x10   // Multi Field Register.
+#define BTB_REG_MEM_ECC_PARITY_ONLY_0_K2                                                                     0xdb0414UL //Access:RW   DataWidth:0x10   // Multi Field Register.
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_BB_K2                                              (0x1<<0) // Set parity only for memory ecc instance btb.BB_BANK_K2_GEN_FOR[0].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_BB_K2_SHIFT                                        0
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_PRTY_BB_K2                                              (0x1<<1) // Set parity only for memory ecc instance btb.BB_BANK_K2_GEN_FOR[1].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_PRTY_BB_K2_SHIFT                                        1
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_PRTY_BB_K2                                              (0x1<<2) // Set parity only for memory ecc instance btb.BB_BANK_K2_GEN_FOR[2].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_PRTY_BB_K2_SHIFT                                        2
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_PRTY_BB_K2                                              (0x1<<3) // Set parity only for memory ecc instance btb.BB_BANK_K2_GEN_FOR[3].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_PRTY_BB_K2_SHIFT                                        3
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_PRTY_BB_K2                                              (0x1<<4) // Set parity only for memory ecc instance btb.BB_BANK_K2_GEN_FOR[4].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_PRTY_BB_K2_SHIFT                                        4
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY_BB_K2                                              (0x1<<5) // Set parity only for memory ecc instance btb.BB_BANK_K2_GEN_FOR[5].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY_BB_K2_SHIFT                                        5
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM013_I_ECC_PRTY_BB_K2                                              (0x1<<6) // Set parity only for memory ecc instance btb.BB_BANK_K2_GEN_FOR[6].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM013_I_ECC_PRTY_BB_K2_SHIFT                                        6
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY_BB_K2                                              (0x1<<7) // Set parity only for memory ecc instance btb.BB_BANK_K2_GEN_FOR[7].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY_BB_K2_SHIFT                                        7
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY_BB_K2                                              (0x1<<8) // Set parity only for memory ecc instance btb.BB_BANK_K2_GEN_FOR[8].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY_BB_K2_SHIFT                                        8
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_PRTY_BB_K2                                              (0x1<<9) // Set parity only for memory ecc instance btb.BB_BANK_K2_GEN_FOR[9].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_PRTY_BB_K2_SHIFT                                        9
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY_BB_K2                                              (0x1<<10) // Set parity only for memory ecc instance btb.BB_BANK_K2_GEN_FOR[10].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY_BB_K2_SHIFT                                        10
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_BB_K2                                              (0x1<<11) // Set parity only for memory ecc instance btb.BB_BANK_K2_GEN_FOR[11].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_BB_K2_SHIFT                                        11
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_BB_K2                                              (0x1<<12) // Set parity only for memory ecc instance btb.BB_BANK_K2_GEN_FOR[12].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_BB_K2_SHIFT                                        12
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_BB_K2                                              (0x1<<13) // Set parity only for memory ecc instance btb.BB_BANK_K2_GEN_FOR[13].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_BB_K2_SHIFT                                        13
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY_BB_K2                                              (0x1<<14) // Set parity only for memory ecc instance btb.BB_BANK_K2_GEN_FOR[14].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY_BB_K2_SHIFT                                        14
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_PRTY_BB_K2                                              (0x1<<15) // Set parity only for memory ecc instance btb.BB_BANK_K2_GEN_FOR[15].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_PRTY_BB_K2_SHIFT                                        15
+#define BTB_REG_MEM008_RF_ECC_ERROR_CONNECT_BB                                                               0xdb0414UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: btb.BB_BANK_BB_GEN_FOR[1].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_BB                                                                 0xdb0458UL //Access:RC   DataWidth:0x10   // Multi Field Register.
+#define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_K2                                                                 0xdb0418UL //Access:RC   DataWidth:0x10   // Multi Field Register.
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_BB_K2                                       (0x1<<0) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_K2_GEN_FOR[0].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_BB_K2_SHIFT                                 0
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_CORRECT_BB_K2                                       (0x1<<1) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_K2_GEN_FOR[1].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_CORRECT_BB_K2_SHIFT                                 1
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_CORRECT_BB_K2                                       (0x1<<2) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_K2_GEN_FOR[2].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_CORRECT_BB_K2_SHIFT                                 2
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_CORRECT_BB_K2                                       (0x1<<3) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_K2_GEN_FOR[3].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_CORRECT_BB_K2_SHIFT                                 3
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_CORRECT_BB_K2                                       (0x1<<4) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_K2_GEN_FOR[4].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_CORRECT_BB_K2_SHIFT                                 4
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT_BB_K2                                       (0x1<<5) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_K2_GEN_FOR[5].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT_BB_K2_SHIFT                                 5
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM013_I_ECC_CORRECT_BB_K2                                       (0x1<<6) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_K2_GEN_FOR[6].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM013_I_ECC_CORRECT_BB_K2_SHIFT                                 6
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT_BB_K2                                       (0x1<<7) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_K2_GEN_FOR[7].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT_BB_K2_SHIFT                                 7
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT_BB_K2                                       (0x1<<8) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_K2_GEN_FOR[8].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT_BB_K2_SHIFT                                 8
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_CORRECT_BB_K2                                       (0x1<<9) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_K2_GEN_FOR[9].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_CORRECT_BB_K2_SHIFT                                 9
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT_BB_K2                                       (0x1<<10) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_K2_GEN_FOR[10].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT_BB_K2_SHIFT                                 10
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_BB_K2                                       (0x1<<11) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_K2_GEN_FOR[11].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_BB_K2_SHIFT                                 11
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_BB_K2                                       (0x1<<12) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_K2_GEN_FOR[12].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_BB_K2_SHIFT                                 12
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_BB_K2                                       (0x1<<13) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_K2_GEN_FOR[13].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_BB_K2_SHIFT                                 13
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT_BB_K2                                       (0x1<<14) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_K2_GEN_FOR[14].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT_BB_K2_SHIFT                                 14
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_CORRECT_BB_K2                                       (0x1<<15) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_K2_GEN_FOR[15].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
+  #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_CORRECT_BB_K2_SHIFT                                 15
+#define BTB_REG_MEM009_RF_ECC_ERROR_CONNECT_BB                                                               0xdb0418UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: btb.BB_BANK_BB_GEN_FOR[2].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BTB_REG_MEM_ECC_EVENTS_BB                                                                            0xdb045cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define BTB_REG_MEM_ECC_EVENTS_K2                                                                            0xdb041cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define BTB_REG_MEM010_RF_ECC_ERROR_CONNECT_BB                                                               0xdb041cUL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: btb.BB_BANK_BB_GEN_FOR[3].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BTB_REG_MEM011_RF_ECC_ERROR_CONNECT_BB                                                               0xdb0420UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: btb.BB_BANK_BB_GEN_FOR[4].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BTB_REG_MEM012_RF_ECC_ERROR_CONNECT_BB                                                               0xdb0424UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: btb.BB_BANK_BB_GEN_FOR[5].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BTB_REG_MEM013_RF_ECC_ERROR_CONNECT_BB                                                               0xdb0428UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: btb.BB_BANK_BB_GEN_FOR[6].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BTB_REG_MEM014_RF_ECC_ERROR_CONNECT_BB                                                               0xdb042cUL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: btb.BB_BANK_BB_GEN_FOR[7].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BTB_REG_MEM015_RF_ECC_ERROR_CONNECT_BB                                                               0xdb0430UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: btb.BB_BANK_BB_GEN_FOR[8].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BTB_REG_MEM016_RF_ECC_ERROR_CONNECT_BB                                                               0xdb0434UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: btb.BB_BANK_BB_GEN_FOR[9].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BTB_REG_MEM002_RF_ECC_ERROR_CONNECT_BB                                                               0xdb0438UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: btb.BB_BANK_BB_GEN_FOR[10].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BTB_REG_MEM003_RF_ECC_ERROR_CONNECT_BB                                                               0xdb043cUL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: btb.BB_BANK_BB_GEN_FOR[11].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BTB_REG_MEM004_RF_ECC_ERROR_CONNECT_BB                                                               0xdb0440UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: btb.BB_BANK_BB_GEN_FOR[12].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BTB_REG_MEM005_RF_ECC_ERROR_CONNECT_BB                                                               0xdb0444UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: btb.BB_BANK_BB_GEN_FOR[13].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BTB_REG_MEM006_RF_ECC_ERROR_CONNECT_BB                                                               0xdb0448UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: btb.BB_BANK_BB_GEN_FOR[14].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BTB_REG_MEM007_RF_ECC_ERROR_CONNECT_BB                                                               0xdb044cUL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: btb.BB_BANK_BB_GEN_FOR[15].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 129. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define BTB_REG_BIG_RAM_ADDRESS                                                                              0xdb0800UL //Access:RW   DataWidth:0xc    // Debug register. It contains address to Big RAM for RBC operations. Value of this register will be incremented by one it was done write access to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_WDTH/13/g in Data Width.
+#define BTB_REG_HEADER_SIZE                                                                                  0xdb0804UL //Access:RW   DataWidth:0xa    // Number of valid bytes in header in 16-bytes resolution. After this number of bytes will input to BRTB will be sent packet available indication. (reset value of 17 suits to 282 bytes of header)::s/HDR_SIZE_RST/17/g in Reset Value.
+#define BTB_REG_FREE_LIST_HEAD                                                                               0xdb0810UL //Access:RW   DataWidth:0xd    // Head pointer to each one of 4 free lists::s/BLK_WDTH/13/g in Data Width.
+#define BTB_REG_FREE_LIST_HEAD_SIZE                                                                          4
+#define BTB_REG_FREE_LIST_TAIL                                                                               0xdb0820UL //Access:RW   DataWidth:0xd    // Tail pointer of each one of 4 free lists::s/BLK_WDTH/13/g in Data Width.
+#define BTB_REG_FREE_LIST_TAIL_SIZE                                                                          4
+#define BTB_REG_FREE_LIST_SIZE                                                                               0xdb0830UL //Access:RW   DataWidth:0xd    // Number of free blocks in each one of 4 free lists::s/BLK_WDTH/13/g in Data Width.
+#define BTB_REG_FREE_LIST_SIZE_SIZE                                                                          4
+#define BTB_REG_MAX_RELEASES                                                                                 0xdb0840UL //Access:RW   DataWidth:0x2    // Number of packet copies that should be released before whole packet is released::s/MAX_RLS_WDTH/10/g in Data Width::s/MAX_RLS_RST/512/g in Reset Value::s/MAX_RLS_REQ/required/g in Required::s/MAX_RLS_REQ/required/g in Software init.
+#define BTB_REG_STOP_ON_LEN_ERR                                                                              0xdb0844UL //Access:RW   DataWidth:0x8    // There is bit for each PACKET read client. When bit is set then read client will not execute more requests till reset in a case of length error other way it will continue to work as usual.::s/STOP_LEN_ERR_RST/7/g in Reset Value::s/PKT_RC_NUM/5/g in Data Width.
+#define BTB_REG_ALM_FULL_THRESHOLD                                                                           0xdb0848UL //Access:RW   DataWidth:0xd    // The number of blocks occupied in BTB upper which ALMOST FULL is asserted and BTB stops writing new packets to BIG RAM from its input FIFO. Miniml value is total number of TCs for all ports + 2 + number of blocks in maximal packet size::s/BLK_WDTH/13/g in Data Width::/ALM_FULL_EN/d in Existance. Value for 40G mode (reset value, both BB and K2): 2880 - (34 + 2 + (9600+32)/128) = 2768 = 0xAD0 Value for 100G mode (BB only): 2880/2  (34/2 + 2 + (9600+64)/256) = 1383 = 0x567
+#define BTB_REG_NO_DEAD_CYCLES_EN                                                                            0xdb084cUL //Access:RW   DataWidth:0x8    // There is bit for each PACKET read client. Bit 0 suits to client 0 and so on. If bit is set then packet will be read without dead cycles.B0-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1 ::s/NO_DEAD_CYCLE_RST/1/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser/g in Comments::s/PKT_RC_NUM/5/g in Data Width.
+#define BTB_REG_RC_PKT_PRIORITY                                                                              0xdb0850UL //Access:RW   DataWidth:0x10   // Multi Field Register.
+  #define BTB_REG_RC_PKT_PRIORITY_NIG_MAIN0_RC_PRI                                                           (0x3<<0) // This is priority for NIG main port 0  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
+  #define BTB_REG_RC_PKT_PRIORITY_NIG_MAIN0_RC_PRI_SHIFT                                                     0
+  #define BTB_REG_RC_PKT_PRIORITY_NIG_LB0_RC_PRI                                                             (0x3<<2) // This is priority for NIG LB port 0  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
+  #define BTB_REG_RC_PKT_PRIORITY_NIG_LB0_RC_PRI_SHIFT                                                       2
+  #define BTB_REG_RC_PKT_PRIORITY_NIG_MAIN1_RC_PRI                                                           (0x3<<4) // This is priority for NIG main port 1  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
+  #define BTB_REG_RC_PKT_PRIORITY_NIG_MAIN1_RC_PRI_SHIFT                                                     4
+  #define BTB_REG_RC_PKT_PRIORITY_NIG_LB1_RC_PRI                                                             (0x3<<6) // This is priority for NIG LB port 1  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
+  #define BTB_REG_RC_PKT_PRIORITY_NIG_LB1_RC_PRI_SHIFT                                                       6
+  #define BTB_REG_RC_PKT_PRIORITY_NIG_MAIN2_RC_PRI                                                           (0x3<<8) // This is priority for NIG main port 0  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
+  #define BTB_REG_RC_PKT_PRIORITY_NIG_MAIN2_RC_PRI_SHIFT                                                     8
+  #define BTB_REG_RC_PKT_PRIORITY_NIG_LB2_RC_PRI                                                             (0x3<<10) // This is priority for NIG LB port 2  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
+  #define BTB_REG_RC_PKT_PRIORITY_NIG_LB2_RC_PRI_SHIFT                                                       10
+  #define BTB_REG_RC_PKT_PRIORITY_NIG_MAIN3_RC_PRI                                                           (0x3<<12) // This is priority for NIG main port 3  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
+  #define BTB_REG_RC_PKT_PRIORITY_NIG_MAIN3_RC_PRI_SHIFT                                                     12
+  #define BTB_REG_RC_PKT_PRIORITY_NIG_LB3_RC_PRI                                                             (0x3<<14) // This is priority for NIG LB port 3  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
+  #define BTB_REG_RC_PKT_PRIORITY_NIG_LB3_RC_PRI_SHIFT                                                       14
+#define BTB_REG_WC_NO_DEAD_CYCLES_EN_K2_E5                                                                   0xdb0854UL //Access:RW   DataWidth:0x1    // There is bit for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then packet will be written without intra packet dead cycles .B0-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1 ::s/NO_DEAD_CYCLE_RST/1/g in Reset
+#define BTB_REG_WC_HIGHEST_PRI_EN_K2_E5                                                                      0xdb0858UL //Access:RW   DataWidth:0x1    // There is bit for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then highest priority mechanism is enabled for the corresponding client. B0-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1 ::s/NO_DEAD_CYCLE_RST/1/g in Reset
+#define BTB_REG_WC_LL_HIGH_PRI_E5                                                                            0xdb085cUL //Access:RW   DataWidth:0x1    // This is a bitmap per WC which is 1 for WC with high priority and 0 o/w.
+#define BTB_REG_BR_FIX_HIGH_PRI_COLLISION_E5                                                                 0xdb0860UL //Access:RW   DataWidth:0x1    // This is a bitmap per WC which is 1 for WC with high priority and 0 o/w.
+#define BTB_REG_RC_SOP_PRIORITY                                                                              0xdb088cUL //Access:RW   DataWidth:0x2    // This is priority for SOP read client to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_SOP_PRI_RST/5/g in Reset Value.
+#define BTB_REG_WC_PRIORITY                                                                                  0xdb0890UL //Access:RW   DataWidth:0x2    // This is priority for packet request of write client group to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_WC_PRI_RST/7/g in Reset Value.
+#define BTB_REG_PRI_OF_MULT_CLIENTS                                                                          0xdb0894UL //Access:RW   DataWidth:0x2    // This is priority of multiple clients with identical priority for link list arbiter. Selection from them will be done with round robin. Only one group with multiple clients of identical priority is supported. Possible values are 1-3. Priority 3 is highest::s/RC_MULT_PRI_RST/6/g in Reset Value.
+#define BTB_REG_INP_FIFO_ALM_FULL                                                                            0xdb0898UL //Access:RW   DataWidth:0x6    // Number of entries inside input FIFO of each write client upper which full outputs to this write client interface.
+#define BTB_REG_WC_SYNC_FIFO_ALM_FULL                                                                        0xdb089cUL //Access:RW   DataWidth:0x6    // Number of entries inside sync FIFO of each write client.
+#define BTB_REG_PKT_RC_OUT_SYNC_FIFO_ALM_FULL                                                                0xdb08a0UL //Access:RW   DataWidth:0x5    // Number of entries inside output sync FIFO of each read client.
+#define BTB_REG_PKT_AVAIL_SYNC_FIFO_ALM_FULL                                                                 0xdb08a4UL //Access:RW   DataWidth:0x4    // Number of entries inside packet available sync FIFO.
+#define BTB_REG_RLS_SYNC_FIFO_ALM_FULL                                                                       0xdb08a8UL //Access:RW   DataWidth:0x4    // Number of entries inside packet available sync FIFO.
+#define BTB_REG_INP_FIFO_HIGH_THRESHOLD                                                                      0xdb08acUL //Access:RW   DataWidth:0x5    // Number of entries inside input FIFO of each write client upper which all arbiters selects this client with high priority.
+#define BTB_REG_DSCR_FIFO_ALM_FULL                                                                           0xdb08b0UL //Access:RW   DataWidth:0x5    // Number of entries inside descriptors FIFO of each write client upper which full outputs to this write client interface.::s/DSCR_FIFO_RST/12/g in Reset Value.
+#define BTB_REG_QUEUE_FIFO_ALM_FULL                                                                          0xdb08b4UL //Access:RW   DataWidth:0x5    // Number of entries inside queue FIFO of each write client upper which full outputs to this write client interface.::s/QUEUE_FIFO_RST/8/g in Reset Value.
+#define BTB_REG_DSCR_FIFO_HIGH_THRESHOLD                                                                     0xdb08b8UL //Access:RW   DataWidth:0x5    // Number of entries inside descriptors FIFO of each write client upper which all arbiters selects this client with high priority.
+#define BTB_REG_DBGSYN_ALMOST_FULL_THR                                                                       0xdb08bcUL //Access:RW   DataWidth:0x4    // Debug only: If more than this Number of entries are occupied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed.
+#define BTB_REG_DBGSYN_STATUS                                                                                0xdb08c0UL //Access:R    DataWidth:0x5    // Fill level of dbgmux fifo.
+#define BTB_REG_ECO_RESERVED                                                                                 0xdb08c4UL //Access:RW   DataWidth:0x20   // This is unused register for future ECOs.
+#define BTB_REG_DBG_SELECT                                                                                   0xdb08c8UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define BTB_REG_DBG_DWORD_ENABLE                                                                             0xdb08ccUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define BTB_REG_DBG_SHIFT                                                                                    0xdb08d0UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define BTB_REG_DBG_FORCE_VALID                                                                              0xdb08d4UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define BTB_REG_DBG_FORCE_FRAME                                                                              0xdb08d8UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define BTB_REG_DBG_OUT_DATA                                                                                 0xdb08e0UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define BTB_REG_DBG_OUT_DATA_SIZE                                                                            8
+#define BTB_REG_DBG_OUT_VALID                                                                                0xdb0900UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define BTB_REG_DBG_OUT_FRAME                                                                                0xdb0904UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define BTB_REG_INP_IF_ENABLE                                                                                0xdb0908UL //Access:RW   DataWidth:0x15   // Multi Field Register.
+  #define BTB_REG_INP_IF_ENABLE_RC_PKT_INP_IF_EN                                                             (0x3ff<<0) // There is bit per each read client interface: B0-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1. When bit is set then appropriate interface is enabled. When bit is reset then request from that interface will not be accepted. All bits of this register should be set after init procedure. ::s/PKT_RC_NUM_MINUS_SOP_EN/4/g in Data Width::s/RC_PKT_INP_IF_RST/15/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser/g in Comments.
+  #define BTB_REG_INP_IF_ENABLE_RC_PKT_INP_IF_EN_SHIFT                                                       0
+  #define BTB_REG_INP_IF_ENABLE_RC_SOP_INP_IF_EN                                                             (0x1<<10) // There is bit per SOP read client interface. When bit is set then appropriate interface is enabled. When bit is reset then request from that interface will not be accepted.  All bits of this register should be set after init procedure.
+  #define BTB_REG_INP_IF_ENABLE_RC_SOP_INP_IF_EN_SHIFT                                                       10
+  #define BTB_REG_INP_IF_ENABLE_WC_INP_IF_EN                                                                 (0x3ff<<11) // There is bit per write client interface: B0 - NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1.. When bit is set then appropriate interface is enabled. When bit is reset then request from that interface will not be accepted. All bits of this register should be set after init procedure. ::s/WC_IF_RST/15/g in Reset Value::s/WC_EN/B0 - NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1./g in Comments::s/WC_NUM/4/g in Data Width.
+  #define BTB_REG_INP_IF_ENABLE_WC_INP_IF_EN_SHIFT                                                           11
+#define BTB_REG_OUT_IF_ENABLE                                                                                0xdb090cUL //Access:RW   DataWidth:0xe    // Multi Field Register.
+  #define BTB_REG_OUT_IF_ENABLE_RC_PKT_OUT_IF_EN                                                             (0x3ff<<0) // There is bit per each read client interface: B0-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1. When bit is set then appropriate interface is enabled. When bit is reset then valid to that interface will never be asserted. All bits of this register should be set after init procedure. ::s/RC_PKT_OUT_IF_RST/31/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser/g in Comments::s/PKT_RC_NUM/5/g in Data Width.
+  #define BTB_REG_OUT_IF_ENABLE_RC_PKT_OUT_IF_EN_SHIFT                                                       0
+  #define BTB_REG_OUT_IF_ENABLE_RC_SOP_OUT_IF_EN                                                             (0x1<<10) // There is bit per SOP read client interface. When bit is set then appropriate interface is enabled. When bit is reset then valid to that interface will never be asserted.  All bits of this register should be set after init procedure.
+  #define BTB_REG_OUT_IF_ENABLE_RC_SOP_OUT_IF_EN_SHIFT                                                       10
+  #define BTB_REG_OUT_IF_ENABLE_ALM_FULL_OUT_IF_EN                                                           (0x1<<11) // There is bit for almost full interfaces. When bit is set then almost full interface is enabled. When bit is reset then almost full will never be set.  All bits of this register should be set after init procedure. ::/ALM_FULL_EN/d in Existance.
+  #define BTB_REG_OUT_IF_ENABLE_ALM_FULL_OUT_IF_EN_SHIFT                                                     11
+  #define BTB_REG_OUT_IF_ENABLE_PKT_AVAILABLE_OUT_IF_EN                                                      (0x1<<12) // There is bit for packet avalable interfaces. When bit is set then packet avalable interface is enabled. When bit is reset then packet avalable interface will never be set.  This bit should be set after init procedure.
+  #define BTB_REG_OUT_IF_ENABLE_PKT_AVAILABLE_OUT_IF_EN_SHIFT                                                12
+  #define BTB_REG_OUT_IF_ENABLE_RELEASE_OUT_IF_EN                                                            (0x1<<13) // There is bit for release interfaces. When bit is set then release interface is enabled. When bit is reset then release interface will never be set.  This bit should be set after init procedure. ::/RLS_EN/d in Existance.
+  #define BTB_REG_OUT_IF_ENABLE_RELEASE_OUT_IF_EN_SHIFT                                                      13
+#define BTB_REG_WC_DUP_EMPTY                                                                                 0xdb0910UL //Access:R    DataWidth:0x4    // Debug register. Empty status of write clients: {pkt_avail_fifo ;upd_point_fifo ; rsp_dscr_fifo; upd_data_fifo}::/DUP_EN/d in Existance.
+#define BTB_REG_WC_DUP_FULL                                                                                  0xdb0914UL //Access:R    DataWidth:0x4    // Debug register. Full status of write clients: {pkt_avail_fifo ;upd_point_fifo ; rsp_dscr_fifo; upd_data_fifo}::/DUP_EN/d in Existance.
+#define BTB_REG_WC_DUP_STATUS                                                                                0xdb0918UL //Access:R    DataWidth:0x10   // Debug register. FIFO counters status of write clients: {delayed_fifo ;upd_point_fifo ; rsp_dscr_fifo; upd_data_fifo}::/DUP_EN/d in Existance.
+#define BTB_REG_WC_EMPTY_0                                                                                   0xdb091cUL //Access:R    DataWidth:0xd    // Debug register. Empty status of each write clients. 8 bits spelling of write client status: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.
+#define BTB_REG_WC_FULL_0                                                                                    0xdb095cUL //Access:R    DataWidth:0xd    // Debug register. Full status of write clients. 8 bits spelling of write client status: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}
+#define BTB_REG_WC_BANDWIDTH_IF_FULL                                                                         0xdb099cUL //Access:R    DataWidth:0x1    // Debug register. Full status each write client because of temporal bandwidth problem on interface::s/WC_NUM_MAX/4/g in Data Width.
+#define BTB_REG_RC_PKT_IF_FULL                                                                               0xdb09a0UL //Access:R    DataWidth:0x8    // Debug register. Full status of each read packet client interface::s/PKT_RC_NUM/5/g in Data Width.
+#define BTB_REG_RC_PKT_EMPTY_0                                                                               0xdb09a4UL //Access:R    DataWidth:0x8    // Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BTB_REG_RC_PKT_EMPTY_1                                                                               0xdb09a8UL //Access:R    DataWidth:0x8    // Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BTB_REG_RC_PKT_EMPTY_2                                                                               0xdb09acUL //Access:R    DataWidth:0x8    // Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BTB_REG_RC_PKT_EMPTY_3                                                                               0xdb09b0UL //Access:R    DataWidth:0x8    // Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BTB_REG_RC_PKT_EMPTY_4_K2_E5                                                                         0xdb09b4UL //Access:R    DataWidth:0x8    // Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BTB_REG_RC_PKT_EMPTY_5_K2_E5                                                                         0xdb09b8UL //Access:R    DataWidth:0x8    // Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BTB_REG_RC_PKT_EMPTY_6_K2_E5                                                                         0xdb09bcUL //Access:R    DataWidth:0x8    // Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BTB_REG_RC_PKT_EMPTY_7_K2_E5                                                                         0xdb09c0UL //Access:R    DataWidth:0x8    // Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BTB_REG_RC_PKT_FULL_0                                                                                0xdb09e0UL //Access:R    DataWidth:0x8    // Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BTB_REG_RC_PKT_FULL_1                                                                                0xdb09e4UL //Access:R    DataWidth:0x8    // Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BTB_REG_RC_PKT_FULL_2                                                                                0xdb09e8UL //Access:R    DataWidth:0x8    // Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BTB_REG_RC_PKT_FULL_3                                                                                0xdb09ecUL //Access:R    DataWidth:0x8    // Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BTB_REG_RC_PKT_FULL_4_K2_E5                                                                          0xdb09f0UL //Access:R    DataWidth:0x8    // Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BTB_REG_RC_PKT_FULL_5_K2_E5                                                                          0xdb09f4UL //Access:R    DataWidth:0x8    // Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BTB_REG_RC_PKT_FULL_6_K2_E5                                                                          0xdb09f8UL //Access:R    DataWidth:0x8    // Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BTB_REG_RC_PKT_FULL_7_K2_E5                                                                          0xdb09fcUL //Access:R    DataWidth:0x8    // Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.
+#define BTB_REG_RC_PKT_STATUS_0                                                                              0xdb0a1cUL //Access:R    DataWidth:0x20   // Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.
+#define BTB_REG_RC_PKT_STATUS_1                                                                              0xdb0a20UL //Access:R    DataWidth:0x20   // Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.
+#define BTB_REG_RC_PKT_STATUS_2                                                                              0xdb0a24UL //Access:R    DataWidth:0x20   // Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.
+#define BTB_REG_RC_PKT_STATUS_3                                                                              0xdb0a28UL //Access:R    DataWidth:0x20   // Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.
+#define BTB_REG_RC_PKT_STATUS_4_K2_E5                                                                        0xdb0a2cUL //Access:R    DataWidth:0x20   // Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.
+#define BTB_REG_RC_PKT_STATUS_5_K2_E5                                                                        0xdb0a30UL //Access:R    DataWidth:0x20   // Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.
+#define BTB_REG_RC_PKT_STATUS_6_K2_E5                                                                        0xdb0a34UL //Access:R    DataWidth:0x20   // Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.
+#define BTB_REG_RC_PKT_STATUS_7_K2_E5                                                                        0xdb0a38UL //Access:R    DataWidth:0x20   // Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.
+#define BTB_REG_RC_SOP_EMPTY                                                                                 0xdb0a58UL //Access:R    DataWidth:0x4    // Debug register. Empty status of read SOP clients: {B2-req_fifo;  B1-dscr_fifo;  B0-queue_fifo}.
+#define BTB_REG_RC_SOP_FULL                                                                                  0xdb0a5cUL //Access:R    DataWidth:0x4    // Debug register. Full status of read SOP clients: {B2-req_fifo;  B1-dscr_fifo;  B0-queue_fifo}.
+#define BTB_REG_RC_SOP_STATUS                                                                                0xdb0a60UL //Access:R    DataWidth:0x10   // Debug register. FIFO counters status of read SOP clients: {B11:8-req_fifo;  B7:4-dscr_fifo;  B3:0-queue_fifo}.
+#define BTB_REG_LL_ARB_EMPTY                                                                                 0xdb0a64UL //Access:R    DataWidth:0x3    // Debug register. Empty status of link list arbiter: {rls_fifo; prefetch_fifo}.
+#define BTB_REG_LL_ARB_FULL                                                                                  0xdb0a68UL //Access:R    DataWidth:0x3    // Debug register. Full status of link list arbiter: {rls_fifo; prefetch_fifos}.
+#define BTB_REG_LL_ARB_STATUS                                                                                0xdb0a6cUL //Access:R    DataWidth:0xe    // Debug register. FIFO counters status of link list arbiter: {rls_fifo[7:4]; prefetch_fifo_1[4:0], prefetch_fifo_0[4:0]}.
+#define BTB_REG_BLOCK_OCCUPANCY                                                                              0xdb0a70UL //Access:R    DataWidth:0xd    // Debug register. This is number of allocated blocks ::s/BLK_WDTH/13/g in Data Width::/ALM_FULL_EN/d in Existance.
+#define BTB_REG_ALM_FULL                                                                                     0xdb0a74UL //Access:R    DataWidth:0x1    // Debug register. This is  almost full output IF to PBF::/ALM_FULL_EN/d in Existance.
+#define BTB_REG_WC_SYNC_FIFO_PUSH_STATUS_0                                                                   0xdb0a78UL //Access:R    DataWidth:0x7    // Debug register. This is full status of WC SYNC FIFO
+#define BTB_REG_RLS_SYNC_FIFO_PUSH_STATUS                                                                    0xdb0ab4UL //Access:R    DataWidth:0x4    // Debug register. This is full status of release SYNC FIFO
+#define BTB_REG_RC_PKT_STATE                                                                                 0xdb0ab8UL //Access:R    DataWidth:0x20   // Debug register. This is state machine for each read client. ::s/PKT_RC_NUM_ST/20/g in Data Width.
+#define BTB_REG_CLOCKS_RATIO                                                                                 0xdb0ac8UL //Access:RW   DataWidth:0x4    // Indicates the ratio of bytes arrived we need to wait for, in power of 2, before sending new packet indication to read client. This should ensure no underflow when read client reads the packet in higher frequency than write client writes it. In E4 the configuration value will be 3, meaning after 1/(2power3) of the packet arrived it can be sent to the read client. This is because (375-425)/425 is less then 1/(2power3).
+#define BTB_REG_LAST_BLK_POOL                                                                                0xdb0b00UL //Access:R    DataWidth:0x10   // Debug register. There is requister for each queue of duplicated client that contains pointer to first block of last packet from that queue in bits 11:0; b12: update enable status; b13: duplicated queue update enable; b14: man queue update status.::/DUP_EN/d in Existance.
+#define BTB_REG_LAST_BLK_POOL_SIZE                                                                           34
+#define BTB_REG_BIG_RAM_DATA                                                                                 0xdb0c00UL //Access:WB   DataWidth:0x80   // Debug register. Data to BIG RAM memory. Write to 32 MSB bits of this register will generate write to BIG RAM according to address that is written in big_ram_address register. Read from 32 LSB bits of this register will generate read from BIG RAM according to address written in big_ram_address register.
+#define BTB_REG_BIG_RAM_DATA_SIZE                                                                            64
+#define BTB_REG_RC_SOP_QUEUE_STATUS                                                                          0xdb0e00UL //Access:R    DataWidth:0x20   // Debug register. There is register for each queue of each write client. It contains: b31 - valid; b30:16 - queue size; b15:0 - queue start pointer::s/SOP_STATUS_RST/536805376/g in Reset Value::s/QUEUE_ARRAY/36/g in memory size::s/SOP_STATUS_WDTH/6/g in Address Width.
+#define BTB_REG_RC_SOP_QUEUE_STATUS_SIZE_BB                                                                  34
+#define BTB_REG_RC_SOP_QUEUE_STATUS_SIZE_K2_E5                                                               36
+#define BTB_REG_STOPPED_RD_REQ                                                                               0xdb1000UL //Access:WB_R DataWidth:0x41   // If there is length error of first block error then request from read client will be copied to this register for each erad packet client interface: 0-NIG main port0; 1-NIG LB port0; 2-NIG main port1; 2-NIG LB port1. Message spelling (MSB->LSB): rest_size_error[0]; len_error[0]; 1st_error[0]; middle_error[0]; rls_to_do[1:0]; start_block[12:0]; rd_req[0]; rls_req[0]; offset[9:0]; length[13:0]; opaque[15:0]
+#define BTB_REG_STOPPED_RD_REQ_SIZE_BB                                                                       8
+#define BTB_REG_STOPPED_RD_REQ_SIZE_K2                                                                       16
+#define BTB_REG_STOPPED_RD_REQ_SIZE_E5                                                                       32
+#define BTB_REG_STOPPED_RLS_REQ                                                                              0xdb1100UL //Access:WB_R DataWidth:0x3c   // If there is release error then request from read client will be copied to this register for each read packet client interface: 0-NIG main port0; 1-NIG LB port0; 2-NIG main port1; 2-NIG LB port1. Message spelling (MSB->LSB): opaque[1:0]; rls_to_do[15:0]; queue_number[5:0]; packet_length[13:0]; rls_left[1:0]; start_block[12:0]
+#define BTB_REG_STOPPED_RLS_REQ_SIZE_BB                                                                      8
+#define BTB_REG_STOPPED_RLS_REQ_SIZE_K2_E5                                                                   16
+#define BTB_REG_WC_STATUS_0                                                                                  0xdb1200UL //Access:WB_R DataWidth:0x5b   // Debug register. FIFO counters status of write clients. 8 bits spelling of write client status: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
+#define BTB_REG_WC_STATUS_0_SIZE                                                                             4
+#define BTB_REG_LINK_LIST_BB_K2                                                                              0xdb4000UL //Access:RW   DataWidth:0xc    // Link list dual port memory that contains per-block descriptor::s/BLK_NUM/4800/g in memory size::s/BLK_WDTH_PLUS_SOP_EN/14/g in Data Width::s/BLK_WDTH/13/g in Address Width.
+#define BTB_REG_LINK_LIST_E5                                                                                 0xdb8000UL //Access:RW   DataWidth:0xd    // Link list dual port memory that contains per-block descriptor::s/BLK_NUM/4800/g in memory size::s/BLK_WDTH_PLUS_SOP_EN/14/g in Data Width::s/BLK_WDTH/13/g in Address Width.
+#define BTB_REG_LINK_LIST_SIZE_BB                                                                            2880
+#define BTB_REG_LINK_LIST_SIZE_K2                                                                            3680
+#define BTB_REG_LINK_LIST_SIZE_E5                                                                            6400
+#define MCP_REG_MCP_CONTROL                                                                                  0xe00080UL //Access:RW   DataWidth:0x20   // These are basic configurations for the MCP block.
+  #define MCP_REG_MCP_CONTROL_UNUSED0                                                                        (0x7fffffff<<0) // 
+  #define MCP_REG_MCP_CONTROL_UNUSED0_SHIFT                                                                  0
+  #define MCP_REG_MCP_CONTROL_MCP_ISOLATE                                                                    (0x1<<31) // This bit is set by the driver before it sets the MCP_RESET bit. When set this bit disables MCP's GRC Master interface. This bit should cleared by the driver when the MCP reset completes.
+  #define MCP_REG_MCP_CONTROL_MCP_ISOLATE_SHIFT                                                              31
+#define MCP_REG_MCP_ATTENTION_STATUS                                                                         0xe00084UL //Access:RW   DataWidth:0x20   // SHARE : This register shows the status of the bits that generate attention from the MCP.
+  #define MCP_REG_MCP_ATTENTION_STATUS_UNUSED0                                                               (0x3ffffff<<0) // 
+  #define MCP_REG_MCP_ATTENTION_STATUS_UNUSED0_SHIFT                                                         0
+  #define MCP_REG_MCP_ATTENTION_STATUS_M2P_ATTN                                                              (0x1<<26) // Attention from the M2P Block.
+  #define MCP_REG_MCP_ATTENTION_STATUS_M2P_ATTN_SHIFT                                                        26
+  #define MCP_REG_MCP_ATTENTION_STATUS_SPAD_CACHE_ATTN                                                       (0x1<<27) // Illegal transaction occurred in the MCP cache block.
+  #define MCP_REG_MCP_ATTENTION_STATUS_SPAD_CACHE_ATTN_SHIFT                                                 27
+  #define MCP_REG_MCP_ATTENTION_STATUS_SMB_EVENT                                                             (0x1<<28) // Event from the SMBUS Block.
+  #define MCP_REG_MCP_ATTENTION_STATUS_SMB_EVENT_SHIFT                                                       28
+  #define MCP_REG_MCP_ATTENTION_STATUS_FLSH_EVENT                                                            (0x1<<29) // Event from the Flash Block.
+  #define MCP_REG_MCP_ATTENTION_STATUS_FLSH_EVENT_SHIFT                                                      29
+  #define MCP_REG_MCP_ATTENTION_STATUS_WATCHDOG_TIMEOUT                                                      (0x1<<30) // This bit is set when the watchdog timer expires. This bit reflects state of the WATCHDOG_ATTN bit. When this bit is written as '1', the value will return to '0'. !!! Writing '1' has effect only after watchdog_reset register had been written !!!
+  #define MCP_REG_MCP_ATTENTION_STATUS_WATCHDOG_TIMEOUT_SHIFT                                                30
+  #define MCP_REG_MCP_ATTENTION_STATUS_CPU_EVENT                                                             (0x1<<31) // This bit is set any time an internal CPU event that requires the driver's attention happens.
+  #define MCP_REG_MCP_ATTENTION_STATUS_CPU_EVENT_SHIFT                                                       31
+#define MCP_REG_MCP_HEARTBEAT_CONTROL                                                                        0xe00088UL //Access:RW   DataWidth:0x20   // Control for MCP heartbeat feature.
+  #define MCP_REG_MCP_HEARTBEAT_CONTROL_UNUSED0                                                              (0x7fffffff<<0) // 
+  #define MCP_REG_MCP_HEARTBEAT_CONTROL_UNUSED0_SHIFT                                                        0
+  #define MCP_REG_MCP_HEARTBEAT_CONTROL_MCP_HEARTBEAT_ENABLE                                                 (0x1<<31) // When this bit is set by the driver it indicates to MCP that it should start incrementing the MCP_HEARTBEAT register. The MCP reports the increment period to the driver using MCP_HEARTBEAT_STATUS register.
+  #define MCP_REG_MCP_HEARTBEAT_CONTROL_MCP_HEARTBEAT_ENABLE_SHIFT                                           31
+#define MCP_REG_MCP_HEARTBEAT_STATUS                                                                         0xe0008cUL //Access:RW   DataWidth:0x20   // Status of MCP heartbeat feature.
+  #define MCP_REG_MCP_HEARTBEAT_STATUS_MCP_HEARTBEAT_PERIOD                                                  (0x7ff<<0) // This value is written by the MCP and indicates (in ms) to the driver MCP_HEARTBEAT increment period. This is just rough increment period as estimated by the firmware and not the exact increment period.
+  #define MCP_REG_MCP_HEARTBEAT_STATUS_MCP_HEARTBEAT_PERIOD_SHIFT                                            0
+  #define MCP_REG_MCP_HEARTBEAT_STATUS_UNUSED0                                                               (0xfffff<<11) // 
+  #define MCP_REG_MCP_HEARTBEAT_STATUS_UNUSED0_SHIFT                                                         11
+  #define MCP_REG_MCP_HEARTBEAT_STATUS_VALID                                                                 (0x1<<31) // When set this bit validates bits 10-0 of this register.
+  #define MCP_REG_MCP_HEARTBEAT_STATUS_VALID_SHIFT                                                           31
+#define MCP_REG_MCP_HEARTBEAT                                                                                0xe00090UL //Access:RW   DataWidth:0x20   // Doorbell registoer for MCP heartbeat feature.
+  #define MCP_REG_MCP_HEARTBEAT_MCP_HEARTBEAT_COUNT                                                          (0x3fffffff<<0) // This is free running counter incremented roughly with the period that is specified in MCP_HEARTBEAT_STATUS register.
+  #define MCP_REG_MCP_HEARTBEAT_MCP_HEARTBEAT_COUNT_SHIFT                                                    0
+  #define MCP_REG_MCP_HEARTBEAT_MCP_HEARTBEAT_INC                                                            (0x1<<30) // When set this bit causes MCP heartbeat counter to increment. Typically used by the MCP.
+  #define MCP_REG_MCP_HEARTBEAT_MCP_HEARTBEAT_INC_SHIFT                                                      30
+  #define MCP_REG_MCP_HEARTBEAT_MCP_HEARTBEAT_RESET                                                          (0x1<<31) // When set this bit resets the heartbeat counter. Typically used by the MCP or the driver.
+  #define MCP_REG_MCP_HEARTBEAT_MCP_HEARTBEAT_RESET_SHIFT                                                    31
+#define MCP_REG_WATCHDOG_RESET                                                                               0xe00094UL //Access:RW   DataWidth:0x20   // Doorbell to reset the watchog timer.
+  #define MCP_REG_WATCHDOG_RESET_UNUSED0                                                                     (0x3fffffff<<0) // 
+  #define MCP_REG_WATCHDOG_RESET_UNUSED0_SHIFT                                                               0
+  #define MCP_REG_WATCHDOG_RESET_WATCHDOG_2_RESET                                                            (0x1<<30) // When set this bit resets the watchdog timer #2. Typically used by the MCP or the driver.
+  #define MCP_REG_WATCHDOG_RESET_WATCHDOG_2_RESET_SHIFT                                                      30
+  #define MCP_REG_WATCHDOG_RESET_WATCHDOG_RESET                                                              (0x1<<31) // When set this bit resets the watchdog timer #1. Typically used by the MCP or the driver.
+  #define MCP_REG_WATCHDOG_RESET_WATCHDOG_RESET_SHIFT                                                        31
+#define MCP_REG_WATCHDOG_CONTROL                                                                             0xe00098UL //Access:RW   DataWidth:0x20   // Control for the watchog timer.
+  #define MCP_REG_WATCHDOG_CONTROL_UNUSED0                                                                   (0x7ffffff<<0) // 
+  #define MCP_REG_WATCHDOG_CONTROL_UNUSED0_SHIFT                                                             0
+  #define MCP_REG_WATCHDOG_CONTROL_WATCHDOG_2_ENABLE                                                         (0x1<<27) // When set this bit enables watchdog timer #2. Typically used by the driver
+  #define MCP_REG_WATCHDOG_CONTROL_WATCHDOG_2_ENABLE_SHIFT                                                   27
+  #define MCP_REG_WATCHDOG_CONTROL_WATCHDOG_MASTER_WRITE_STALL_ENABLE                                        (0x1<<28) // When this bit is set, expiration of watchdog timer will result in MCP losing ability to perform GRC master write operations. Default is for MCP to have GRC write capability even through a watchdog timer expiration.
+  #define MCP_REG_WATCHDOG_CONTROL_WATCHDOG_MASTER_WRITE_STALL_ENABLE_SHIFT                                  28
+  #define MCP_REG_WATCHDOG_CONTROL_WATCHDOG_ATTN                                                             (0x1<<29) // When set indicates that watchdog timer has reached 0 and that it requires driver's attention. Low to high transition on this bit should generate MCP attention toward the HC which will send it back to the driver using driver status block. Cleared when the watchdog timer is reset.
+  #define MCP_REG_WATCHDOG_CONTROL_WATCHDOG_ATTN_SHIFT                                                       29
+  #define MCP_REG_WATCHDOG_CONTROL_MCP_RST_ENABLE                                                            (0x1<<30) // When set this bit enables the watchdog timer to reset the MCP instead of halting it. The watchdog hardware must set MCP_ISOLATE bit before it resets the MCP.
+  #define MCP_REG_WATCHDOG_CONTROL_MCP_RST_ENABLE_SHIFT                                                      30
+  #define MCP_REG_WATCHDOG_CONTROL_WATCHDOG_ENABLE                                                           (0x1<<31) // When set this bit enables watchdog timer #1. Typically used by the driver.
+  #define MCP_REG_WATCHDOG_CONTROL_WATCHDOG_ENABLE_SHIFT                                                     31
+#define MCP_REG_WATCHDOG_1_TIMEOUT                                                                           0xe0009cUL //Access:RW   DataWidth:0x20   // Timeout value for watchog timer #1. These bits specify the watchdog timeout period with respect to the MCP (1/2 speed) core_clk. Using core clock should provide timeout period scaling in case where core/cpu clocks are slowed down. Reset value is 500ms.
+#define MCP_REG_WATCHDOG_2_TIMEOUT                                                                           0xe000a0UL //Access:RW   DataWidth:0x20   // Timeout value for watchog timer #2. These bits specify the watchdog timeout period with respect to the MCP (1/2 speed) core_clk. Using core clock should provide timeout period scaling in case where core/cpu clocks are slowed down. Reset value is 2 seconds.
+#define MCP_REG_ACCESS_LOCK                                                                                  0xe000a4UL //Access:RW   DataWidth:0x20   // SPLIT16: Access Lock Register.
+  #define MCP_REG_ACCESS_LOCK_UNUSED0                                                                        (0x7fffffff<<0) // 
+  #define MCP_REG_ACCESS_LOCK_UNUSED0_SHIFT                                                                  0
+  #define MCP_REG_ACCESS_LOCK_LOCK                                                                           (0x1<<31) // Driver writes '1' to this bit in order to obtain the lock over the shared resources within the chip. The actual "lock" is implemented in hardware using the state machine that keeps track of who is the owner of the lock. Only the owner of the lock can release the lock. When read by the driver as '1' (after it was written with '1' it tells the driver that it obtained the lock. If read as '0' it means that the other driver holds the lock. Driver writes '0' to this bit to release the lock in case that it owns the lock.
+  #define MCP_REG_ACCESS_LOCK_LOCK_SHIFT                                                                     31
+#define MCP_REG_TOE_ID                                                                                       0xe000a8UL //Access:R    DataWidth:0x20   // SPLIT2: Function ID register
+  #define MCP_REG_TOE_ID_UNUSED0                                                                             (0x7fffffff<<0) // 
+  #define MCP_REG_TOE_ID_UNUSED0_SHIFT                                                                       0
+  #define MCP_REG_TOE_ID_FUNCTION_ID                                                                         (0x1<<31) // This bit tells driver the PCIE function that is associated with. '0' corresponds to even PCIE functions '1' to odd PCIE functions. Since the value is different for both functions, the reset value is shown as unknown.
+  #define MCP_REG_TOE_ID_FUNCTION_ID_SHIFT                                                                   31
+#define MCP_REG_MAILBOX_CFG                                                                                  0xe000acUL //Access:RW   DataWidth:0x20   // SPLIT2: Configuration for mailbox trigger.
+  #define MCP_REG_MAILBOX_CFG_MAILBOX_OFFSET                                                                 (0x3fff<<0) // Offset (in 32-bit words) of the mailbox within the MCP scratchpad. There are two reset values. Register that corresponds to even functions should have reset value of 0x3EC0 and register that corresponds to odd functions should have reset value of 0x3F00
+  #define MCP_REG_MAILBOX_CFG_MAILBOX_OFFSET_SHIFT                                                           0
+  #define MCP_REG_MAILBOX_CFG_UNUSED0                                                                        (0x3f<<14) // 
+  #define MCP_REG_MAILBOX_CFG_UNUSED0_SHIFT                                                                  14
+  #define MCP_REG_MAILBOX_CFG_MAILBOX_SIZE                                                                   (0xfff<<20) // Mailbox size in 32-bit words. Default mailbox size is 1KB.
+  #define MCP_REG_MAILBOX_CFG_MAILBOX_SIZE_SHIFT                                                             20
+#define MCP_REG_MAILBOX_CFG_OTHER_FUNC                                                                       0xe000b0UL //Access:RW   DataWidth:0x20   // SPLIT2: Configuration for mailbox trigger.
+  #define MCP_REG_MAILBOX_CFG_OTHER_FUNC_MAILBOX_OFFSET                                                      (0x3fff<<0) // Offset (in 32-bit words) of the mailbox within the MCP scratchpad. There are two reset values. Register that corresponds to even functions should have reset value of 0x3EC0 and register that corresponds to odd functions should have reset value of 0x3F00
+  #define MCP_REG_MAILBOX_CFG_OTHER_FUNC_MAILBOX_OFFSET_SHIFT                                                0
+  #define MCP_REG_MAILBOX_CFG_OTHER_FUNC_UNUSED0                                                             (0x3f<<14) // 
+  #define MCP_REG_MAILBOX_CFG_OTHER_FUNC_UNUSED0_SHIFT                                                       14
+  #define MCP_REG_MAILBOX_CFG_OTHER_FUNC_MAILBOX_SIZE                                                        (0xfff<<20) // Mailbox size in 32-bit words. Default mailbox size is 1KB.
+  #define MCP_REG_MAILBOX_CFG_OTHER_FUNC_MAILBOX_SIZE_SHIFT                                                  20
+#define MCP_REG_MCP_DOORBELL                                                                                 0xe000b4UL //Access:RW   DataWidth:0x20   // SPLIT16: Doorbell that is written by firmware.
+  #define MCP_REG_MCP_DOORBELL_UNUSED0                                                                       (0x7fffffff<<0) // 
+  #define MCP_REG_MCP_DOORBELL_UNUSED0_SHIFT                                                                 0
+  #define MCP_REG_MCP_DOORBELL_MCP_DOORBELL                                                                  (0x1<<31) // Set by the driver to alert the MCP. Changing this register updates the corresponding per-PF bit in the MCP Doorbell Status register. Cleared by the MCP when it services the message.
+  #define MCP_REG_MCP_DOORBELL_MCP_DOORBELL_SHIFT                                                            31
+#define MCP_REG_MCP_VFID                                                                                     0xe000c4UL //Access:RW   DataWidth:0x20   // VFID settings.
+  #define MCP_REG_MCP_VFID_VFID                                                                              (0xff<<0) // Register supports up to an 8 bit VFID. For smaller VFIDs, the extra bits wil be ignored.
+  #define MCP_REG_MCP_VFID_VFID_SHIFT                                                                        0
+  #define MCP_REG_MCP_VFID_UNUSED0                                                                           (0xff<<8) // 
+  #define MCP_REG_MCP_VFID_UNUSED0_SHIFT                                                                     8
+  #define MCP_REG_MCP_VFID_VFID_VALID                                                                        (0x1<<16) // 
+  #define MCP_REG_MCP_VFID_VFID_VALID_SHIFT                                                                  16
+  #define MCP_REG_MCP_VFID_UNUSED1                                                                           (0x7<<17) // 
+  #define MCP_REG_MCP_VFID_UNUSED1_SHIFT                                                                     17
+  #define MCP_REG_MCP_VFID_PATHID                                                                            (0x1<<20) // 
+  #define MCP_REG_MCP_VFID_PATHID_SHIFT                                                                      20
+  #define MCP_REG_MCP_VFID_UNUSED2                                                                           (0x3ff<<21) // 
+  #define MCP_REG_MCP_VFID_UNUSED2_SHIFT                                                                     21
+  #define MCP_REG_MCP_VFID_PATH_FORCE                                                                        (0x1<<31) // 
+  #define MCP_REG_MCP_VFID_PATH_FORCE_SHIFT                                                                  31
+#define MCP_REG_GP_INPUTS                                                                                    0xe000c8UL //Access:R    DataWidth:0x20   // Extended General Purpose Inputs
+#define MCP_REG_PORT_MODE                                                                                    0xe000ccUL //Access:RW   DataWidth:0x20   // Port mode for GRC Master transactions 0: 1-port mode, 1: 2-port mode, 2: 4-port mode All bits are RW, but only the 2 lsb are relevant
+#define MCP_REG_GP_OENABLE                                                                                   0xe000d0UL //Access:RW   DataWidth:0x20   // Extended General Purpose Output Enable
+#define MCP_REG_GP_MASK_HI_TO_LO                                                                             0xe000d4UL //Access:RW   DataWidth:0x20   // EPIO mask for signal transitioning from high to low. 1 -&gt; MASK the event
+#define MCP_REG_GP_MASK_LO_TO_HI                                                                             0xe000d8UL //Access:RW   DataWidth:0x20   // EPIO mask for signal transitioning from low to high. 1 -&gt; MASK the event
+#define MCP_REG_GP_HI_TO_LO                                                                                  0xe000dcUL //Access:RW   DataWidth:0x20   // EPIO event status for high to low transition prior to mask
+#define MCP_REG_GP_LO_TO_HI                                                                                  0xe000e0UL //Access:RW   DataWidth:0x20   // EPIO event status for low to high transition prior to mask
+#define MCP_REG_GP_EVENT_VEC                                                                                 0xe000e4UL //Access:RW   DataWidth:0x20   // EPIO event status for either transitions with the mask applied.
+#define MCP_REG_CPU_MODE                                                                                     0xe05000UL //Access:RW   DataWidth:0x20   // CPU Internal registers.
+  #define MCP_REG_CPU_MODE_LOCAL_RST                                                                         (0x1<<0) // When this bit is written to a 1, the processor will reset as if from power-up state. All "Reset" value of registers will be assigned.
+  #define MCP_REG_CPU_MODE_LOCAL_RST_SHIFT                                                                   0
+  #define MCP_REG_CPU_MODE_STEP_ENA                                                                          (0x1<<1) // When this bit is set, the processor is allowed to execute one cycle regardless of any halt conditions. If the halting condition still exists, the CPU will halt again after the one cycle, otherwise, it will resume normal operation.
+  #define MCP_REG_CPU_MODE_STEP_ENA_SHIFT                                                                    1
+  #define MCP_REG_CPU_MODE_PAGE_0_DATA_ENA                                                                   (0x1<<2) // This bit enables the processor to halt and to latch the value of bit 3 of the state register when data references the first 256 bytes of memory space (page 0). This bit is cleared by an interrupt or reset.
+  #define MCP_REG_CPU_MODE_PAGE_0_DATA_ENA_SHIFT                                                             2
+  #define MCP_REG_CPU_MODE_PAGE_0_INST_ENA                                                                   (0x1<<3) // This bit enables the processor to halt and to latch the value of bit 4 of the state register when an instruction references the first 256 bytes of memory space (page 0). This bit is cleared by an interrupt or reset.
+  #define MCP_REG_CPU_MODE_PAGE_0_INST_ENA_SHIFT                                                             3
+  #define MCP_REG_CPU_MODE_UNUSED0                                                                           (0x3<<4) // 
+  #define MCP_REG_CPU_MODE_UNUSED0_SHIFT                                                                     4
+  #define MCP_REG_CPU_MODE_MSG_BIT1                                                                          (0x1<<6) // This is a simple RW bit.
+  #define MCP_REG_CPU_MODE_MSG_BIT1_SHIFT                                                                    6
+  #define MCP_REG_CPU_MODE_INTERRUPT_ENA                                                                     (0x1<<7) // When this bit is set to 1, the interrupt is enabled. When this bit is zero, any interrupt will be ignored. This bit can also be set by writing the interrupt_enable register
+  #define MCP_REG_CPU_MODE_INTERRUPT_ENA_SHIFT                                                               7
+  #define MCP_REG_CPU_MODE_UNUSED1                                                                           (0x3<<8) // 
+  #define MCP_REG_CPU_MODE_UNUSED1_SHIFT                                                                     8
+  #define MCP_REG_CPU_MODE_SOFT_HALT                                                                         (0x1<<10) // When this bit is set, the CPU will halt. This bit is cleared by an exception or reset. If the processor does not have a ROM, then this bit will reset to set so that no code is executed from the scratchpad. If the processor does have a ROM, this bit resets a cleared so that the processor executes from ROM after reset.
+  #define MCP_REG_CPU_MODE_SOFT_HALT_SHIFT                                                                   10
+  #define MCP_REG_CPU_MODE_BAD_DATA_HALT_ENA                                                                 (0x1<<11) // When this bit is set, the CPU will halt when any condition that causes bit 5 in the CPU state register to be set occurs. This bit is cleared by an interrupt.
+  #define MCP_REG_CPU_MODE_BAD_DATA_HALT_ENA_SHIFT                                                           11
+  #define MCP_REG_CPU_MODE_BAD_INST_HALT_ENA                                                                 (0x1<<12) // When this bit is set, the CPU will halt when any condition that causes bit 6 in the CPU state register to be set occurs. This bit is cleared by an interrupt.
+  #define MCP_REG_CPU_MODE_BAD_INST_HALT_ENA_SHIFT                                                           12
+  #define MCP_REG_CPU_MODE_FIO_ABORT_HALT_ENA                                                                (0x1<<13) // When this bit is set, the CPU will halt when a abort is indicated from any "Fast IO" space peripheral.
+  #define MCP_REG_CPU_MODE_FIO_ABORT_HALT_ENA_SHIFT                                                          13
+  #define MCP_REG_CPU_MODE_UNUSED2                                                                           (0x1<<14) // 
+  #define MCP_REG_CPU_MODE_UNUSED2_SHIFT                                                                     14
+  #define MCP_REG_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA                                                           (0x1<<15) // When this bit is set, the CPU will halt when state bit 11 is set.
+  #define MCP_REG_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA_SHIFT                                                     15
+#define MCP_REG_CPU_STATE                                                                                    0xe05004UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_CPU_STATE_BREAKPOINT                                                                       (0x1<<0) // This bit is set while the processor is halted due reaching a hardware breakpoint as enabled in the mode register. This bit is cleared by writing a 1 to this bit position.
+  #define MCP_REG_CPU_STATE_BREAKPOINT_SHIFT                                                                 0
+  #define MCP_REG_CPU_STATE_UNUSED0                                                                          (0x1<<1) // 
+  #define MCP_REG_CPU_STATE_UNUSED0_SHIFT                                                                    1
+  #define MCP_REG_CPU_STATE_BAD_INST_HALTED                                                                  (0x1<<2) // This bit is set while the processor is halted due fetching an invalid instruction. This bit is cleared by writing a 1 to this bit position.
+  #define MCP_REG_CPU_STATE_BAD_INST_HALTED_SHIFT                                                            2
+  #define MCP_REG_CPU_STATE_PAGE_0_DATA_HALTED                                                               (0x1<<3) // This bit is set while the processor is halted due to accessing data within page 0 (the first 256 bytes) of memory. This bit is cleared by writing a 1 to this bit position.
+  #define MCP_REG_CPU_STATE_PAGE_0_DATA_HALTED_SHIFT                                                         3
+  #define MCP_REG_CPU_STATE_PAGE_0_INST_HALTED                                                               (0x1<<4) // This bit is set while the processor is halted due to executing an instruction within page 0 (the first 256 bytes) of memory. This bit is cleared by writing a 1 to this bit position.
+  #define MCP_REG_CPU_STATE_PAGE_0_INST_HALTED_SHIFT                                                         4
+  #define MCP_REG_CPU_STATE_BAD_DATA_ADDR_HALTED                                                             (0x1<<5) // This bit is set while the processor is halted due to bad data reference address. This bit is cleared by writing a 1 to this bit position.
+  #define MCP_REG_CPU_STATE_BAD_DATA_ADDR_HALTED_SHIFT                                                       5
+  #define MCP_REG_CPU_STATE_BAD_PC_HALTED                                                                    (0x1<<6) // This bit is set while the processor is halted due to bad value in the Program Counter (PC). This bit is cleared by writing a 1 to this bit position.
+  #define MCP_REG_CPU_STATE_BAD_PC_HALTED_SHIFT                                                              6
+  #define MCP_REG_CPU_STATE_ALIGN_HALTED                                                                     (0x1<<7) // This bit is set while the processor is halted due to bad memory alignment problem on a load or store instruction. This bit is cleared by writing a 1 to this bit position.
+  #define MCP_REG_CPU_STATE_ALIGN_HALTED_SHIFT                                                               7
+  #define MCP_REG_CPU_STATE_FIO_ABORT_HALTED                                                                 (0x1<<8) // This bit is set while the processor is halted due to the generation of a abort condition by one, or more, "Fast IO" devices within the CPU block. This will only happen if halt is enabled by bit 13 in the mode register.
+  #define MCP_REG_CPU_STATE_FIO_ABORT_HALTED_SHIFT                                                           8
+  #define MCP_REG_CPU_STATE_UNUSED1                                                                          (0x1<<9) // 
+  #define MCP_REG_CPU_STATE_UNUSED1_SHIFT                                                                    9
+  #define MCP_REG_CPU_STATE_SOFT_HALTED                                                                      (0x1<<10) // This bit is set while the processor is halted due to the setting of bit 10 in the mode register.
+  #define MCP_REG_CPU_STATE_SOFT_HALTED_SHIFT                                                                10
+  #define MCP_REG_CPU_STATE_SPAD_UNDERFLOW                                                                   (0x1<<11) // This bit is each time an attempt is made to access the underflow area of the Scratchpad.
+  #define MCP_REG_CPU_STATE_SPAD_UNDERFLOW_SHIFT                                                             11
+  #define MCP_REG_CPU_STATE_INTERRRUPT                                                                       (0x1<<12) // This bit is each time an interrupt input is asserted, regardless of the interrupt enable bit (bit 7, mode).
+  #define MCP_REG_CPU_STATE_INTERRRUPT_SHIFT                                                                 12
+  #define MCP_REG_CPU_STATE_UNUSED2                                                                          (0x1<<13) // 
+  #define MCP_REG_CPU_STATE_UNUSED2_SHIFT                                                                    13
+  #define MCP_REG_CPU_STATE_DATA_ACCESS_STALL                                                                (0x1<<14) // This bit is set while the processor is stalled due to data access.
+  #define MCP_REG_CPU_STATE_DATA_ACCESS_STALL_SHIFT                                                          14
+  #define MCP_REG_CPU_STATE_INST_FETCH_STALL                                                                 (0x1<<15) // This bit is set while the processor is stalled due to instruction fetch.
+  #define MCP_REG_CPU_STATE_INST_FETCH_STALL_SHIFT                                                           15
+  #define MCP_REG_CPU_STATE_UNUSED3                                                                          (0x7fff<<16) // 
+  #define MCP_REG_CPU_STATE_UNUSED3_SHIFT                                                                    16
+  #define MCP_REG_CPU_STATE_BLOCKED_READ                                                                     (0x1<<31) // This bit indicates that a blocking data cache miss occurred, causing the CPU to stall while data is fetched from memory. This is intended as a debugging tool. No state is saved other than the fact that the miss occurred. This bit is cleared by writing a 1 to this bit position.
+  #define MCP_REG_CPU_STATE_BLOCKED_READ_SHIFT                                                               31
+#define MCP_REG_CPU_EVENT_MASK                                                                               0xe05008UL //Access:RW   DataWidth:0x20   // This register provides one bit for each state register bit to enable it into the equation for generation the TX Processor Attention output. The reset value of 1 masks all halt conditions from generating an attention.
+  #define MCP_REG_CPU_EVENT_MASK_BREAKPOINT_MASK                                                             (0x1<<0) // This bit enables breakpoints to generate Attention output.
+  #define MCP_REG_CPU_EVENT_MASK_BREAKPOINT_MASK_SHIFT                                                       0
+  #define MCP_REG_CPU_EVENT_MASK_UNUSED0                                                                     (0x1<<1) // 
+  #define MCP_REG_CPU_EVENT_MASK_UNUSED0_SHIFT                                                               1
+  #define MCP_REG_CPU_EVENT_MASK_BAD_INST_HALTED_MASK                                                        (0x1<<2) // This bit enables invalid instruction decodes to generate Attention output.
+  #define MCP_REG_CPU_EVENT_MASK_BAD_INST_HALTED_MASK_SHIFT                                                  2
+  #define MCP_REG_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK                                                     (0x1<<3) // This bit enables page 0 data access to generate Attention output.
+  #define MCP_REG_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK_SHIFT                                               3
+  #define MCP_REG_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK                                                     (0x1<<4) // This bit enables page 0 instructions to generate Attention output.
+  #define MCP_REG_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK_SHIFT                                               4
+  #define MCP_REG_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK                                                   (0x1<<5) // This bit enables invalid data addresses to generate Attention output.
+  #define MCP_REG_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK_SHIFT                                             5
+  #define MCP_REG_CPU_EVENT_MASK_BAD_PC_HALTED_MASK                                                          (0x1<<6) // This bit enables invalid PC values to generate Attention output.
+  #define MCP_REG_CPU_EVENT_MASK_BAD_PC_HALTED_MASK_SHIFT                                                    6
+  #define MCP_REG_CPU_EVENT_MASK_ALIGN_HALTED_MASK                                                           (0x1<<7) // This bit enables alignment errors to generate Attention output.
+  #define MCP_REG_CPU_EVENT_MASK_ALIGN_HALTED_MASK_SHIFT                                                     7
+  #define MCP_REG_CPU_EVENT_MASK_FIO_ABORT_MASK                                                              (0x1<<8) // This bit enables the attention output when bit 8 of the state register is set.
+  #define MCP_REG_CPU_EVENT_MASK_FIO_ABORT_MASK_SHIFT                                                        8
+  #define MCP_REG_CPU_EVENT_MASK_UNUSED1                                                                     (0x1<<9) // 
+  #define MCP_REG_CPU_EVENT_MASK_UNUSED1_SHIFT                                                               9
+  #define MCP_REG_CPU_EVENT_MASK_SOFT_HALTED_MASK                                                            (0x1<<10) // This bit enables soft halts to generate Attention output.
+  #define MCP_REG_CPU_EVENT_MASK_SOFT_HALTED_MASK_SHIFT                                                      10
+  #define MCP_REG_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK                                                         (0x1<<11) // This bit attention when bit 11 of the state register is set.
+  #define MCP_REG_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK_SHIFT                                                   11
+  #define MCP_REG_CPU_EVENT_MASK_INTERRUPT_MASK                                                              (0x1<<12) // This bit attention when bit 12 of the state register is set.
+  #define MCP_REG_CPU_EVENT_MASK_INTERRUPT_MASK_SHIFT                                                        12
+#define MCP_REG_CPU_PROGRAM_COUNTER                                                                          0xe0501cUL //Access:RW   DataWidth:0x20   // This register allows the program counter to read at any time. The value can be modified when the processor is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. '1's written to bits 1-0 are ignored. If the processor has a ROM, then the reset value of this register points to the internal ROM. If the processor does not have a ROM, then this reset value points to the scratchpad area.
+#define MCP_REG_CPU_INSTRUCTION                                                                              0xe05020UL //Access:RW   DataWidth:0x20   // This register allows access instruction in the decode sate of the pipeline while the processor is halted. This register is only intended for debugging use. This register may be used to replace a halt instruction with some other instruction after the halt has been executed.
+#define MCP_REG_CPU_DATA_ACCESS                                                                              0xe05024UL //Access:R    DataWidth:0x20   // This register allows access to the address of the current data access of the processor. It is only valid when the processor is doing a load or a store. Normally this will be used for debug of stalls caused by firmware accesses to invalid memory areas.
+#define MCP_REG_CPU_INTERRUPT_ENABLE                                                                         0xe05028UL //Access:W    DataWidth:0x20   // Any write to this register will enable CPU Interrupts (set bit 7 in mode register). This register is intended to allow a way to return from an interrupt service routine (ISR) using only 2 general purpose registers. MIPS conventions reserve registers 26 and 27 (k0 and k1) for use by an interrupt handler. At the end of an ISR, k0 should be loaded with the return address from the CPU Interrupt Saved PC register. Then k1 should be loaded with the address of the CPU Interrupt Enable register. The last 2 instructions in the ISR should be a jump register (jr) to k0 followed immediately by a store word (sw) to k1. This ensures that we can't respond to another interrupt until we are safely out of the ISR. Interrupts can also be enabled through the CPU Mode Register. They can be disabled only through the CPU Mode Register. Each time this register is written, bit 7 of the mode register is set. The data value of the write is not used. The read value of this register is always zero.
+#define MCP_REG_CPU_INTERRUPT_VECTOR                                                                         0xe0502cUL //Access:RW   DataWidth:0x20   // This register sets the program counter value that will be loaded when an interrupt is performed due to the interrupt input.
+#define MCP_REG_CPU_INTERRUPT_SAVED_PC                                                                       0xe05030UL //Access:R    DataWidth:0x20   // This register reports the PC that was saved during the execution of an interrupt.
+#define MCP_REG_CPU_HW_BREAKPOINT                                                                            0xe05034UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_CPU_HW_BREAKPOINT_DISABLE                                                                  (0x1<<0) // Reset: 1 When this bit is set, the hardware breakpoint feature is disabled.
+  #define MCP_REG_CPU_HW_BREAKPOINT_DISABLE_SHIFT                                                            0
+  #define MCP_REG_CPU_HW_BREAKPOINT_UNUSED0                                                                  (0x1<<1) // 
+  #define MCP_REG_CPU_HW_BREAKPOINT_UNUSED0_SHIFT                                                            1
+  #define MCP_REG_CPU_HW_BREAKPOINT_ADDRESS                                                                  (0x3fffffff<<2) // This field sets the 32-bit word on which the * hardware breakpoint will execute.
+  #define MCP_REG_CPU_HW_BREAKPOINT_ADDRESS_SHIFT                                                            2
+#define MCP_REG_CPU_DEBUG_VECT_PEEK                                                                          0xe05038UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_CPU_DEBUG_VECT_PEEK__1_VALUE                                                               (0x7ff<<0) // 11 bit set-1 debug visibility vector value. This value is selected by the 1_SEL value and enabled by 1_PEEK_EN. This value is undefined if 1_PEEK_EN is '0'.
+  #define MCP_REG_CPU_DEBUG_VECT_PEEK__1_VALUE_SHIFT                                                         0
+  #define MCP_REG_CPU_DEBUG_VECT_PEEK__1_PEEK_EN                                                             (0x1<<11) // When this bit is '0', then the debug visiblity mux is controlled by the setting in the misc. block and is available on the visibility output pins. When this bit is '1', then the mux is controlled by 1_SEL.
+  #define MCP_REG_CPU_DEBUG_VECT_PEEK__1_PEEK_EN_SHIFT                                                       11
+  #define MCP_REG_CPU_DEBUG_VECT_PEEK__1_SEL                                                                 (0xf<<12) // 4 bit select for the peek value of the set-1 debug visibility vector.
+  #define MCP_REG_CPU_DEBUG_VECT_PEEK__1_SEL_SHIFT                                                           12
+  #define MCP_REG_CPU_DEBUG_VECT_PEEK__2_VALUE                                                               (0x7ff<<16) // 11 bit set-2 debug visibility vector value. This value is selected by the 2_SEL value and enabled by 2_PEEK_EN. This value is undefined if 2_PEEK_EN is '0'.
+  #define MCP_REG_CPU_DEBUG_VECT_PEEK__2_VALUE_SHIFT                                                         16
+  #define MCP_REG_CPU_DEBUG_VECT_PEEK__2_PEEK_EN                                                             (0x1<<27) // When this bit is '0', then the debug visiblity mux is controlled by the setting in the misc. block and is available on the visibility output pins. When this bit is '1', then the mux is controlled by 1_SEL.
+  #define MCP_REG_CPU_DEBUG_VECT_PEEK__2_PEEK_EN_SHIFT                                                       27
+  #define MCP_REG_CPU_DEBUG_VECT_PEEK__2_SEL                                                                 (0xf<<28) // 4 bit select for the peek value of the set-2 debug visibility vector.
+  #define MCP_REG_CPU_DEBUG_VECT_PEEK__2_SEL_SHIFT                                                           28
+#define MCP_REG_CPU_LAST_BRANCH_ADDR                                                                         0xe05048UL //Access:R    DataWidth:0x20   // This register indicates that address and branch type of the last branch that was taken. This register is for debug use only.
+  #define MCP_REG_CPU_LAST_BRANCH_ADDR_UNUSED0                                                               (0x1<<0) // 
+  #define MCP_REG_CPU_LAST_BRANCH_ADDR_UNUSED0_SHIFT                                                         0
+  #define MCP_REG_CPU_LAST_BRANCH_ADDR_TYPE                                                                  (0x1<<1) // This bit indicates the type of branch that * was last taken.
+  #define MCP_REG_CPU_LAST_BRANCH_ADDR_TYPE_SHIFT                                                            1
+  #define MCP_REG_CPU_LAST_BRANCH_ADDR_LBA                                                                   (0x3fffffff<<2) // This value indicates the address of the last branch that was taken. An offset as indicated by the type field must be subtracted from this value.
+  #define MCP_REG_CPU_LAST_BRANCH_ADDR_LBA_SHIFT                                                             2
+#define MCP_REG_CPU_REG_FILE                                                                                 0xe05200UL //Access:RW   DataWidth:0x20   // While the processor is halted, the general purpose processor registers (r0-r31) can be read and written through these register locations.
+#define MCP_REG_CPU_REG_FILE_SIZE                                                                            32
+#define MCP_REG_MDIO_AUTO_POLL                                                                               0xe054a8UL //Access:RW   DataWidth:0x20   // This register is mirrored from EMAC. Hardware uses EMAC defines, so this register must match EMAC register.
+  #define MCP_REG_MDIO_AUTO_POLL_DATA_MASK                                                                   (0xffff<<0) // This value is used to specify the bit at the auto-polled address that indicates "link up". The bit which corresponds to "link up" should be set in this data mask field.
+  #define MCP_REG_MDIO_AUTO_POLL_DATA_MASK_SHIFT                                                             0
+  #define MCP_REG_MDIO_AUTO_POLL_REG_ADDR                                                                    (0xffff<<16) // This value is used to define the register address in MDIO auto-poll transactions. For Clause 22, only the bottom 5 bits are utilized. For Clause 45, all 16 bits are utilized.
+  #define MCP_REG_MDIO_AUTO_POLL_REG_ADDR_SHIFT                                                              16
+#define MCP_REG_MDIO_COMM                                                                                    0xe054acUL //Access:RW   DataWidth:0x20   // This register is mirrored from EMAC. Hardware uses EMAC defines, so this register must match EMAC register.
+  #define MCP_REG_MDIO_COMM_DATA                                                                             (0xffff<<0) // When this register is read, it returns the results of the last MDIO transaction that was performed. When this register value is written, it updates the value that will be used on the next MDIO write transaction that will be performed. In case of Clause 45, when the address transaction is executed, this value specifies the register address. On chip versions before TetonII-B0, on the first read of this register when the START_BUSY bit returns to '0', this value, in the same read, is invalid. A 2nd read must be executed to get the correct value. This problem is fixed in TetonII-B0 and later.
+  #define MCP_REG_MDIO_COMM_DATA_SHIFT                                                                       0
+  #define MCP_REG_MDIO_COMM_REG_ADDR                                                                         (0x1f<<16) // This value is used to define the register address portion of the MDIO transaction for Clause 22. This selects what register within a PHY device is being accessed. In case of Clause 45 this value specifies the device address.
+  #define MCP_REG_MDIO_COMM_REG_ADDR_SHIFT                                                                   16
+  #define MCP_REG_MDIO_COMM_PHY_ADDR                                                                         (0x1f<<21) // This value is used to define the PHY address portion of the MDIO transaction for Clause 22 and the port address for Clause 45.
+  #define MCP_REG_MDIO_COMM_PHY_ADDR_SHIFT                                                                   21
+  #define MCP_REG_MDIO_COMM_COMMAND                                                                          (0x3<<26) // This field controls the type of MDIO transaction that will be performed when the START_BUSY bit is set.
+  #define MCP_REG_MDIO_COMM_COMMAND_SHIFT                                                                    26
+  #define MCP_REG_MDIO_COMM_FAIL                                                                             (0x1<<28) // This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction.
+  #define MCP_REG_MDIO_COMM_FAIL_SHIFT                                                                       28
+  #define MCP_REG_MDIO_COMM_START_BUSY                                                                       (0x1<<29) // This bit is self clearing. When written to a '1', the currently programmed MDIO transaction will activate. When the operation is complete, this bit will clear and the MI_COMPLETE bit will be set in the emac_status register. Writing this bit as a '0' has no effect. This bit must be read as a '0' before setting to prevent un-predictable results. On chip versions before TetonII-B0, on the first read of this register when this bit returns to '0', the DATA value in the same read is invalid. A 2nd read must be executed to get the correct DATA value. This problem is fixed in TetonII, B0 and later.
+  #define MCP_REG_MDIO_COMM_START_BUSY_SHIFT                                                                 29
+#define MCP_REG_MDIO_STATUS                                                                                  0xe054b0UL //Access:RW   DataWidth:0x20   // This register is mirrored from EMAC. Hardware uses EMAC defines, so this register must match EMAC register.
+  #define MCP_REG_MDIO_STATUS_LINK                                                                           (0x1<<0) // This bit is updated by the MDIO interface if auto-polling is enabled. The value of this bit is reflected by in the main link status bit if auto-polling of the MDIO is enabled.
+  #define MCP_REG_MDIO_STATUS_LINK_SHIFT                                                                     0
+  #define MCP_REG_MDIO_STATUS__10MB                                                                          (0x1<<1) // This bit is manually controlled only. It is not effect at all by the MDIO interface. The value of this setting is not used for TetonII. The mode is completly determined from the mode register settings.
+  #define MCP_REG_MDIO_STATUS__10MB_SHIFT                                                                    1
+#define MCP_REG_MDIO_MODE                                                                                    0xe054b4UL //Access:RW   DataWidth:0x20   // This register is mirrored from EMAC. Hardware uses EMAC defines, so this register must match EMAC register.
+  #define MCP_REG_MDIO_MODE_UNUSED0                                                                          (0x1<<0) // 
+  #define MCP_REG_MDIO_MODE_UNUSED0_SHIFT                                                                    0
+  #define MCP_REG_MDIO_MODE_SHORT_PREAMBLE                                                                   (0x1<<1) // If this bit is set, the 32-bit pre-amble will not be generated during auto-polling.
+  #define MCP_REG_MDIO_MODE_SHORT_PREAMBLE_SHIFT                                                             1
+  #define MCP_REG_MDIO_MODE_UNUSED1                                                                          (0x3<<2) // 
+  #define MCP_REG_MDIO_MODE_UNUSED1_SHIFT                                                                    2
+  #define MCP_REG_MDIO_MODE_AUTO_POLL                                                                        (0x1<<4) // This bit enables auto-polling. When auto-polling is on, the START_BUSY bit in the mdio_comm register must not be set. The interface will automatically poll the PHY device and set the LINK bit in the mdio_status register according to bit 2 of the PHY register 1. The PHY address used is that programmed into the PHY_ADDR field of the mdio_comm register.
+  #define MCP_REG_MDIO_MODE_AUTO_POLL_SHIFT                                                                  4
+  #define MCP_REG_MDIO_MODE_UNUSED2                                                                          (0x7<<5) // 
+  #define MCP_REG_MDIO_MODE_UNUSED2_SHIFT                                                                    5
+  #define MCP_REG_MDIO_MODE_BIT_BANG                                                                         (0x1<<8) // If this bit is '1', the MDIO interface is controlled by the MDIO, MDIO_OE, and MDC bits in this register. When this bit is '0', the commands in the mdio_cmd register will be executed.
+  #define MCP_REG_MDIO_MODE_BIT_BANG_SHIFT                                                                   8
+  #define MCP_REG_MDIO_MODE_MDIO                                                                             (0x1<<9) // The write value of this bit controls the drive state of the MDIO pin if the BIT_BANG bit is set. The read value of this bit always reflects the state of the MDIO pin.
+  #define MCP_REG_MDIO_MODE_MDIO_SHIFT                                                                       9
+  #define MCP_REG_MDIO_MODE_MDIO_OE                                                                          (0x1<<10) // Setting this bit to '1' will cause the MDIO pin to drive the value written to the MDIO bit if the BIT_BANG bit is set. Setting this bit to zero will make the MDIO pin an input.
+  #define MCP_REG_MDIO_MODE_MDIO_OE_SHIFT                                                                    10
+  #define MCP_REG_MDIO_MODE_MDC                                                                              (0x1<<11) // Setting this bit to '1' will cause the MDC pin to high if the BIT_BANG bit is set. . Setting this pin low will cause the MDC pin to drive low if the BIT_BANG bit is set.
+  #define MCP_REG_MDIO_MODE_MDC_SHIFT                                                                        11
+  #define MCP_REG_MDIO_MODE_MDINT                                                                            (0x1<<12) // The read value of this bit reflects the current state of the MDINT input pin from the Copper PHY. If the interrupt is asserted, this bit will be '0', otherwise, this bit will be '1'.
+  #define MCP_REG_MDIO_MODE_MDINT_SHIFT                                                                      12
+  #define MCP_REG_MDIO_MODE_EXT_MDINT                                                                        (0x1<<13) // The read value of this bit reflects the current state of the External MDINT input pin. If the interrupt is asserted, this bit will be '0', otherwise, this bit will be '1'.
+  #define MCP_REG_MDIO_MODE_EXT_MDINT_SHIFT                                                                  13
+  #define MCP_REG_MDIO_MODE_UNUSED3                                                                          (0x3<<14) // 
+  #define MCP_REG_MDIO_MODE_UNUSED3_SHIFT                                                                    14
+  #define MCP_REG_MDIO_MODE_CLOCK_CNT                                                                        (0x3f<<16) // This field controls the MDIO clock speed. The output MDIO clock runs at a frequency equal to CORE_CLK/(2*(CLOCK_CNT+1)). A value of 0 is invalid for this register.
+  #define MCP_REG_MDIO_MODE_CLOCK_CNT_SHIFT                                                                  16
+  #define MCP_REG_MDIO_MODE_UNUSED4                                                                          (0x1ff<<22) // 
+  #define MCP_REG_MDIO_MODE_UNUSED4_SHIFT                                                                    22
+  #define MCP_REG_MDIO_MODE_CLAUSE_45                                                                        (0x1<<31) // When set to 1 this bit indicates that the current MDIO transaction will be executed as a Clause 45 transaction. When 0 the transaction is executed as a Clause 22 transaction. Value of this bit also determines the meaning of bits specified in bits [27:0] of the MDIO COMMAND register. This bit must be set to proper value before the link auto-polling function is enabled.
+  #define MCP_REG_MDIO_MODE_CLAUSE_45_SHIFT                                                                  31
+#define MCP_REG_MDIO_AUTO_STATUS                                                                             0xe054b8UL //Access:RW   DataWidth:0x20   // This register is mirrored from EMAC. Hardware uses EMAC defines, so this register must match EMAC register.
+  #define MCP_REG_MDIO_AUTO_STATUS_AUTO_ERR                                                                  (0x1<<0) // This bit is set each time an error is detected during a auto poll sequence. The bit is cleared by writing a '1' to this bit position.
+  #define MCP_REG_MDIO_AUTO_STATUS_AUTO_ERR_SHIFT                                                            0
+#define MCP_REG_UCINT_WARP_MODE                                                                              0xe05900UL //Access:RW   DataWidth:0x20   // This register controls accesses to 3 WarpCore SERDES microcontroller program memory interfaces.
+  #define MCP_REG_UCINT_WARP_MODE_ACCESS_MODE                                                                (0x3<<0) // Enumeration:
+  #define MCP_REG_UCINT_WARP_MODE_ACCESS_MODE_SHIFT                                                          0
+  #define MCP_REG_UCINT_WARP_MODE_UNUSED0                                                                    (0x3<<2) // 
+  #define MCP_REG_UCINT_WARP_MODE_UNUSED0_SHIFT                                                              2
+  #define MCP_REG_UCINT_WARP_MODE_TARGET                                                                     (0x3<<4) // This field controls which of the uC interfaces will be accessed when the access_mode field is set to specific_read or specific_write.
+  #define MCP_REG_UCINT_WARP_MODE_TARGET_SHIFT                                                               4
+  #define MCP_REG_UCINT_WARP_MODE_UNUSED1                                                                    (0x3<<6) // 
+  #define MCP_REG_UCINT_WARP_MODE_UNUSED1_SHIFT                                                              6
+  #define MCP_REG_UCINT_WARP_MODE_BYTE_SWAP                                                                  (0x1<<8) // This field controls the swapping of the data register bytes when accessing the uC interface.
+  #define MCP_REG_UCINT_WARP_MODE_BYTE_SWAP_SHIFT                                                            8
+  #define MCP_REG_UCINT_WARP_MODE_UNUSED2                                                                    (0x7f<<9) // 
+  #define MCP_REG_UCINT_WARP_MODE_UNUSED2_SHIFT                                                              9
+  #define MCP_REG_UCINT_WARP_MODE_DUMMY_CYCLES                                                               (0xff<<16) // This field controls how many dummy ext_mem_clk cycles will be driven when a new target is enabled based on a change in the access_mode field.
+  #define MCP_REG_UCINT_WARP_MODE_DUMMY_CYCLES_SHIFT                                                         16
+#define MCP_REG_UCINT_WARP_CLK_DIV                                                                           0xe05904UL //Access:RW   DataWidth:0x20   // This register controls the clock speed for the 3 WarpCore SERDES microcontroller program memory interfaces. All clocks are divided from the MCP (1/2 speed) core_clk.
+  #define MCP_REG_UCINT_WARP_CLK_DIV_CLOCK_RATE                                                              (0x3<<0) // Enumeration:
+  #define MCP_REG_UCINT_WARP_CLK_DIV_CLOCK_RATE_SHIFT                                                        0
+#define MCP_REG_UCINT_WARP_ADDRESS                                                                           0xe05908UL //Access:RW   DataWidth:0x20   // This register controls the address offset for the 3 WarpCore SERDES microcontroller program memory interfaces. This register auto-increments after each transaction.
+  #define MCP_REG_UCINT_WARP_ADDRESS_ADDRESS                                                                 (0xffff<<0) // 
+  #define MCP_REG_UCINT_WARP_ADDRESS_ADDRESS_SHIFT                                                           0
+#define MCP_REG_UCINT_WARP_DATA                                                                              0xe0590cUL //Access:RW   DataWidth:0x20   // Read/write data register for the 3 WarpCore SERDES microcontroller program memory interfaces. Accessing this register will start the transaction specified in the mode register.
+#define MCP_REG_UCINT_WARP_TARGET_ENABLE                                                                     0xe05910UL //Access:RW   DataWidth:0x20   // This register controls the level of the uC_enable signal for the 3 WarpCore SERDES microcontroller program memory interfaces.
+  #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_SET0                                                           (0x1<<0) // Write this bit as a '1' to set ext_uc_enable for target 0.
+  #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_SET0_SHIFT                                                     0
+  #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_SET1                                                           (0x1<<1) // Write this bit as a '1' to set ext_uc_enable for target 1.
+  #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_SET1_SHIFT                                                     1
+  #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_SET2                                                           (0x1<<2) // Write this bit as a '1' to set ext_uc_enable for target 2.
+  #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_SET2_SHIFT                                                     2
+  #define MCP_REG_UCINT_WARP_TARGET_ENABLE_UNUSED0                                                           (0x1f<<3) // 
+  #define MCP_REG_UCINT_WARP_TARGET_ENABLE_UNUSED0_SHIFT                                                     3
+  #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_CLR0                                                           (0x1<<8) // Write this bit as a '1' to clear ext_uc_enable for target 0.
+  #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_CLR0_SHIFT                                                     8
+  #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_CLR1                                                           (0x1<<9) // Write this bit as a '1' to clear ext_uc_enable for target 1.
+  #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_CLR1_SHIFT                                                     9
+  #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_CLR2                                                           (0x1<<10) // Write this bit as a '1' to clear ext_uc_enable for target 2.
+  #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_CLR2_SHIFT                                                     10
+  #define MCP_REG_UCINT_WARP_TARGET_ENABLE_UNUSED1                                                           (0x1f<<11) // 
+  #define MCP_REG_UCINT_WARP_TARGET_ENABLE_UNUSED1_SHIFT                                                     11
+  #define MCP_REG_UCINT_WARP_TARGET_ENABLE_UC_ENABLE0                                                        (0x1<<16) // Current status of ext_uc_enable for target 0.
+  #define MCP_REG_UCINT_WARP_TARGET_ENABLE_UC_ENABLE0_SHIFT                                                  16
+  #define MCP_REG_UCINT_WARP_TARGET_ENABLE_UC_ENABLE1                                                        (0x1<<17) // Current status of ext_uc_enable for target 1.
+  #define MCP_REG_UCINT_WARP_TARGET_ENABLE_UC_ENABLE1_SHIFT                                                  17
+  #define MCP_REG_UCINT_WARP_TARGET_ENABLE_UC_ENABLE2                                                        (0x1<<18) // Current status of ext_uc_enable for target 2.
+  #define MCP_REG_UCINT_WARP_TARGET_ENABLE_UC_ENABLE2_SHIFT                                                  18
+#define MCP_REG_UCINT_PCIE_MODE                                                                              0xe05914UL //Access:RW   DataWidth:0x20   // This register controls accesses to 2 PCIE SERDES microcontroller program memory interfaces.
+  #define MCP_REG_UCINT_PCIE_MODE_ACCESS_MODE                                                                (0x3<<0) // Enumeration:
+  #define MCP_REG_UCINT_PCIE_MODE_ACCESS_MODE_SHIFT                                                          0
+  #define MCP_REG_UCINT_PCIE_MODE_UNUSED0                                                                    (0x3<<2) // 
+  #define MCP_REG_UCINT_PCIE_MODE_UNUSED0_SHIFT                                                              2
+  #define MCP_REG_UCINT_PCIE_MODE_TARGET                                                                     (0x3<<4) // This field controls which of the uC interfaces will be accessed when the access_mode field is set to specific_read or specific_write.
+  #define MCP_REG_UCINT_PCIE_MODE_TARGET_SHIFT                                                               4
+  #define MCP_REG_UCINT_PCIE_MODE_UNUSED1                                                                    (0x3<<6) // 
+  #define MCP_REG_UCINT_PCIE_MODE_UNUSED1_SHIFT                                                              6
+  #define MCP_REG_UCINT_PCIE_MODE_BYTE_SWAP                                                                  (0x1<<8) // This field controls the swapping of the data register bytes when accessing the uC interface.
+  #define MCP_REG_UCINT_PCIE_MODE_BYTE_SWAP_SHIFT                                                            8
+  #define MCP_REG_UCINT_PCIE_MODE_UNUSED2                                                                    (0x7f<<9) // 
+  #define MCP_REG_UCINT_PCIE_MODE_UNUSED2_SHIFT                                                              9
+  #define MCP_REG_UCINT_PCIE_MODE_DUMMY_CYCLES                                                               (0xff<<16) // This field controls how many dummy ext_mem_clk cycles will be driven when a new target is enabled based on a change in the access_mode field.
+  #define MCP_REG_UCINT_PCIE_MODE_DUMMY_CYCLES_SHIFT                                                         16
+#define MCP_REG_UCINT_PCIE_CLK_DIV                                                                           0xe05918UL //Access:RW   DataWidth:0x20   // This register controls the clock speed for the 2 PCIE SERDES microcontroller program memory interfaces. All clocks are divided from the MCP (1/2 speed) core_clk.
+  #define MCP_REG_UCINT_PCIE_CLK_DIV_CLOCK_RATE                                                              (0x3<<0) // Enumeration:
+  #define MCP_REG_UCINT_PCIE_CLK_DIV_CLOCK_RATE_SHIFT                                                        0
+#define MCP_REG_UCINT_PCIE_ADDRESS                                                                           0xe0591cUL //Access:RW   DataWidth:0x20   // This register controls the address offset for the 2 PCIE SERDES microcontroller program memory interfaces. This register auto-increments after each transaction.
+  #define MCP_REG_UCINT_PCIE_ADDRESS_ADDRESS                                                                 (0xffff<<0) // 
+  #define MCP_REG_UCINT_PCIE_ADDRESS_ADDRESS_SHIFT                                                           0
+#define MCP_REG_UCINT_PCIE_DATA                                                                              0xe05920UL //Access:RW   DataWidth:0x20   // Read/write data register for the 2 PCIE SERDES microcontroller program memory interfaces. Accessing this register will start the transaction specified in the mode register.
+#define MCP_REG_UCINT_PCIE_TARGET_ENABLE                                                                     0xe05924UL //Access:RW   DataWidth:0x20   // This register controls the level of the uC_enable signal for the 2 PCIE SERDES microcontroller program memory interfaces.
+  #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_EN_SET0                                                           (0x1<<0) // Write this bit as a '1' to set ext_uc_enable for target 0.
+  #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_EN_SET0_SHIFT                                                     0
+  #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_EN_SET1                                                           (0x1<<1) // Write this bit as a '1' to set ext_uc_enable for target 1.
+  #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_EN_SET1_SHIFT                                                     1
+  #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_UNUSED0                                                           (0x3f<<2) // 
+  #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_UNUSED0_SHIFT                                                     2
+  #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_EN_CLR0                                                           (0x1<<8) // Write this bit as a '1' to clear ext_uc_enable for target 0.
+  #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_EN_CLR0_SHIFT                                                     8
+  #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_EN_CLR1                                                           (0x1<<9) // Write this bit as a '1' to clear ext_uc_enable for target 1.
+  #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_EN_CLR1_SHIFT                                                     9
+  #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_UNUSED1                                                           (0x3f<<10) // 
+  #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_UNUSED1_SHIFT                                                     10
+  #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_UC_ENABLE0                                                        (0x1<<16) // Current status of ext_uc_enable for target 0.
+  #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_UC_ENABLE0_SHIFT                                                  16
+  #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_UC_ENABLE1                                                        (0x1<<17) // Current status of ext_uc_enable for target 1.
+  #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_UC_ENABLE1_SHIFT                                                  17
+#define MCP_REG_UCINT_AVS_ADDRESS                                                                            0xe05928UL //Access:RW   DataWidth:0x20   // This register controls the address offset for the AVS RBUS program memory interface. This register auto-increments after each transaction.
+  #define MCP_REG_UCINT_AVS_ADDRESS_ADDRESS                                                                  (0x1ffff<<0) // 
+  #define MCP_REG_UCINT_AVS_ADDRESS_ADDRESS_SHIFT                                                            0
+#define MCP_REG_UCINT_AVS_DATA                                                                               0xe0592cUL //Access:RW   DataWidth:0x20   // Read/write data register for the AVS microcontroller program memory interfaces. Accessing this register will start the transaction specified in the mode register.
+#define MCP_REG_IMC_COMMAND                                                                                  0xe05a00UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_IMC_COMMAND_TRANSFER_COUNT                                                                 (0x1f<<0) // Number of bytes to be transfered in Read or Write operation. Valid lengths are 0-16.
+  #define MCP_REG_IMC_COMMAND_TRANSFER_COUNT_SHIFT                                                           0
+  #define MCP_REG_IMC_COMMAND_UNUSED0                                                                        (0x7<<5) // 
+  #define MCP_REG_IMC_COMMAND_UNUSED0_SHIFT                                                                  5
+  #define MCP_REG_IMC_COMMAND_TRANSFER_ADDRESS                                                               (0xf<<8) // Address of initial Data Register for Read or Write operation. If the transfer_count&gt;1, additional bytes will be accessed. Address 0 is DataReg0[7:0], Address 7 is DataReg3[31:24].
+  #define MCP_REG_IMC_COMMAND_TRANSFER_ADDRESS_SHIFT                                                         8
+  #define MCP_REG_IMC_COMMAND_UNUSED1                                                                        (0xf<<12) // 
+  #define MCP_REG_IMC_COMMAND_UNUSED1_SHIFT                                                                  12
+  #define MCP_REG_IMC_COMMAND_IMC_STATUS                                                                     (0x3<<16) // Status of current IMC Transaction. 00: No_Op 01: Successful Completion 10: Transaction Pending 10: Error
+  #define MCP_REG_IMC_COMMAND_IMC_STATUS_SHIFT                                                               16
+  #define MCP_REG_IMC_COMMAND_UNUSED2                                                                        (0x3ff<<18) // 
+  #define MCP_REG_IMC_COMMAND_UNUSED2_SHIFT                                                                  18
+  #define MCP_REG_IMC_COMMAND_OPERATION                                                                      (0x3<<28) // Setting these bits starts a I2C Operation 00: No_Op 01: Read 10: Write 11: Flush
+  #define MCP_REG_IMC_COMMAND_OPERATION_SHIFT                                                                28
+  #define MCP_REG_IMC_COMMAND_SOFT_RESET                                                                     (0x1<<30) // Setting this bit will synchronously reset the entire IMC Block.
+  #define MCP_REG_IMC_COMMAND_SOFT_RESET_SHIFT                                                               30
+  #define MCP_REG_IMC_COMMAND_ENABLE                                                                         (0x1<<31) // Setting this bit enables the IMC Block
+  #define MCP_REG_IMC_COMMAND_ENABLE_SHIFT                                                                   31
+#define MCP_REG_IMC_SLAVE_CONTROL                                                                            0xe05a04UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_IMC_SLAVE_CONTROL_SLAVE_ADDRESS                                                            (0xff<<0) // This field sets the address which is sent to the Slave Device as the source/destination for the Read or Write transfer. This is not used during FLUSH operations.
+  #define MCP_REG_IMC_SLAVE_CONTROL_SLAVE_ADDRESS_SHIFT                                                      0
+  #define MCP_REG_IMC_SLAVE_CONTROL_UNUSED0                                                                  (0x1ff<<8) // 
+  #define MCP_REG_IMC_SLAVE_CONTROL_UNUSED0_SHIFT                                                            8
+  #define MCP_REG_IMC_SLAVE_CONTROL_SLAVE_DEVICE_ID                                                          (0x7f<<17) // This field sets the Device ID of the Slave Device. This is a 7-bit field as defined by the I2C spec, but can be written here as 8-bits -- the LSB is ignored.
+  #define MCP_REG_IMC_SLAVE_CONTROL_SLAVE_DEVICE_ID_SHIFT                                                    17
+#define MCP_REG_IMC_TIMING0                                                                                  0xe05a14UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_IMC_TIMING0_SCL_LOW_PERIOD                                                                 (0x7ff<<0) // This timing value sets the number of core_clk cycles while SCL is low.
+  #define MCP_REG_IMC_TIMING0_SCL_LOW_PERIOD_SHIFT                                                           0
+  #define MCP_REG_IMC_TIMING0_UNUSED0                                                                        (0x1f<<11) // 
+  #define MCP_REG_IMC_TIMING0_UNUSED0_SHIFT                                                                  11
+  #define MCP_REG_IMC_TIMING0_SCL_HIGH_PERIOD                                                                (0x7ff<<16) // This timing value sets the number of core_clk cycles while SCL is high.
+  #define MCP_REG_IMC_TIMING0_SCL_HIGH_PERIOD_SHIFT                                                          16
+#define MCP_REG_IMC_TIMING1                                                                                  0xe05a18UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_IMC_TIMING1_START_TO_SCL_LOW                                                               (0x7ff<<0) // This timing value sets the number of core_clk cycles between a START and SCL going low.
+  #define MCP_REG_IMC_TIMING1_START_TO_SCL_LOW_SHIFT                                                         0
+  #define MCP_REG_IMC_TIMING1_UNUSED0                                                                        (0x1f<<11) // 
+  #define MCP_REG_IMC_TIMING1_UNUSED0_SHIFT                                                                  11
+  #define MCP_REG_IMC_TIMING1_DATA_HOLD_TIME                                                                 (0x7ff<<16) // This timing value sets the number of core_clk cycles of hold time on SDA after SCL goes low.
+  #define MCP_REG_IMC_TIMING1_DATA_HOLD_TIME_SHIFT                                                           16
+#define MCP_REG_IMC_TIMING2                                                                                  0xe05a1cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_IMC_TIMING2_STOP_TO_SDA_HIGH                                                               (0x7ff<<0) // This timing value sets the number of core_clk cycles between a STOP and SDA going high.
+  #define MCP_REG_IMC_TIMING2_STOP_TO_SDA_HIGH_SHIFT                                                         0
+  #define MCP_REG_IMC_TIMING2_UNUSED0                                                                        (0x1f<<11) // 
+  #define MCP_REG_IMC_TIMING2_UNUSED0_SHIFT                                                                  11
+  #define MCP_REG_IMC_TIMING2_STOP_TO_START                                                                  (0x7ff<<16) // This timing value sets the number of core_clk cycles between a STOP and a START.
+  #define MCP_REG_IMC_TIMING2_STOP_TO_START_SHIFT                                                            16
+#define MCP_REG_IMC_DATAREG0                                                                                 0xe05a20UL //Access:RW   DataWidth:0x20   // This register is used to store bytes for Read or Write I2C Transactions.
+#define MCP_REG_IMC_DATAREG1                                                                                 0xe05a24UL //Access:RW   DataWidth:0x20   // This register is used to store bytes for Read or Write I2C Transactions.
+#define MCP_REG_IMC_DATAREG2                                                                                 0xe05a28UL //Access:RW   DataWidth:0x20   // This register is used to store bytes for Read or Write I2C Transactions.
+#define MCP_REG_IMC_DATAREG3                                                                                 0xe05a2cUL //Access:RW   DataWidth:0x20   // This register is used to store bytes for Read or Write I2C Transactions.
+#define MCP_REG_M2P_M2P_STATUS                                                                               0xe06100UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_M2P_M2P_STATUS_M2P_BUSY                                                                    (0x1<<0) // This bit indicates that M2P is currently sending a packet. If this bit is set, no new data should be written to the FIFO memory or to the Header registers. This should be polled until it is clear once a VDM transfer is started before another can begin.
+  #define MCP_REG_M2P_M2P_STATUS_M2P_BUSY_SHIFT                                                              0
+  #define MCP_REG_M2P_M2P_STATUS_M2P_PKT_INUSE_ERROR                                                         (0x1<<1) // This bit indicates that in In-Use Error has occured. This is generated if a new VDM transfer is started when the m2p_busy bit was already set.
+  #define MCP_REG_M2P_M2P_STATUS_M2P_PKT_INUSE_ERROR_SHIFT                                                   1
+  #define MCP_REG_M2P_M2P_STATUS_M2P_PKT_OVERFLOW_ERROR                                                      (0x1<<2) // This bit indicates that the packet FIFO was overwritten with too much data. The FIFO is designed to hold a max sized packet of 256 bytes.
+  #define MCP_REG_M2P_M2P_STATUS_M2P_PKT_OVERFLOW_ERROR_SHIFT                                                2
+  #define MCP_REG_M2P_M2P_STATUS_M2P_PKT_UNDERFLOW_ERROR                                                     (0x1<<3) // This bit is set when the Length specified in the VDM header exceeded the amount of data in the Packet FIFO.
+  #define MCP_REG_M2P_M2P_STATUS_M2P_PKT_UNDERFLOW_ERROR_SHIFT                                               3
+  #define MCP_REG_M2P_M2P_STATUS_M2P_ZERO_LENGTH_ERROR                                                       (0x1<<4) // This bit is set when a packet is transmitted while the VDM Length is set to 0x0.
+  #define MCP_REG_M2P_M2P_STATUS_M2P_ZERO_LENGTH_ERROR_SHIFT                                                 4
+  #define MCP_REG_M2P_M2P_STATUS_UNUSED0                                                                     (0x7<<5) // 
+  #define MCP_REG_M2P_M2P_STATUS_UNUSED0_SHIFT                                                               5
+  #define MCP_REG_M2P_M2P_STATUS_M2P_DATA_SM                                                                 (0x3<<8) // This is the internal State Machine, for debugging purposes only.
+  #define MCP_REG_M2P_M2P_STATUS_M2P_DATA_SM_SHIFT                                                           8
+  #define MCP_REG_M2P_M2P_STATUS_UNUSED1                                                                     (0x3f<<10) // 
+  #define MCP_REG_M2P_M2P_STATUS_UNUSED1_SHIFT                                                               10
+  #define MCP_REG_M2P_M2P_STATUS_M2P_PKT_FIFO_STATUS                                                         (0x3f<<16) // This is the current count of locations used in the packet FIFO, for debugging.
+  #define MCP_REG_M2P_M2P_STATUS_M2P_PKT_FIFO_STATUS_SHIFT                                                   16
+#define MCP_REG_M2P_M2P_COMMAND                                                                              0xe06104UL //Access:W    DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_M2P_M2P_COMMAND_SEND_PKT_TO_PXP                                                            (0x1<<0) // Setting this bit will transmit the VDM that was already loaded in the packet FIFO.
+  #define MCP_REG_M2P_M2P_COMMAND_SEND_PKT_TO_PXP_SHIFT                                                      0
+#define MCP_REG_M2P_M2P_VDM_LENGTH                                                                           0xe06108UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_M2P_M2P_VDM_LENGTH_VDM_LENGTH                                                              (0x7f<<0) // This is the length of the VDM packet, in 32-bit DWords. 0x0 is an illegal value. Max sized packet is 256 bytes (0x100).
+  #define MCP_REG_M2P_M2P_VDM_LENGTH_VDM_LENGTH_SHIFT                                                        0
+#define MCP_REG_M2P_M2P_PCI_ID                                                                               0xe0610cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_M2P_M2P_PCI_ID_PCI_ID                                                                      (0xffff<<0) // This is the PCI Target ID field for the VDM Header.
+  #define MCP_REG_M2P_M2P_PCI_ID_PCI_ID_SHIFT                                                                0
+#define MCP_REG_M2P_M2P_VENDOR_ID                                                                            0xe06110UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_M2P_M2P_VENDOR_ID_VENDOR_ID                                                                (0xffff<<0) // This is the Vendor ID field for the VDM Header.
+  #define MCP_REG_M2P_M2P_VENDOR_ID_VENDOR_ID_SHIFT                                                          0
+#define MCP_REG_M2P_M2P_VQ_ID                                                                                0xe06114UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_M2P_M2P_VQ_ID_VQR_ID                                                                       (0x1f<<0) // This is the VQ_ID field for the VDM Header.
+  #define MCP_REG_M2P_M2P_VQ_ID_VQR_ID_SHIFT                                                                 0
+#define MCP_REG_M2P_M2P_SRC_FID                                                                              0xe06118UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_M2P_M2P_SRC_FID_SRC_FID                                                                    (0xffff<<0) // This is the SRC_FID field for the VDM Header.
+  #define MCP_REG_M2P_M2P_SRC_FID_SRC_FID_SHIFT                                                              0
+#define MCP_REG_M2P_M2P_ROUTE_TYPE                                                                           0xe0611cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_M2P_M2P_ROUTE_TYPE_ROUTE_TYPE                                                              (0x7<<0) // This is the Route/Type field for the VDM Header.
+  #define MCP_REG_M2P_M2P_ROUTE_TYPE_ROUTE_TYPE_SHIFT                                                        0
+#define MCP_REG_M2P_M2P_TAG                                                                                  0xe06120UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_M2P_M2P_TAG_TAG                                                                            (0xff<<0) // This is the Tag field for the VDM Header.
+  #define MCP_REG_M2P_M2P_TAG_TAG_SHIFT                                                                      0
+#define MCP_REG_M2P_M2P_VENDOR_DWORD                                                                         0xe06124UL //Access:RW   DataWidth:0x20   // This is the Vendor DWord field for the VDM Header.
+#define MCP_REG_M2P_M2P_PATH_ID                                                                              0xe06128UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_M2P_M2P_PATH_ID_PATH_ID                                                                    (0x1<<0) // This bit selects whether the VDM will be sent to Engine 0 or Engine 1.
+  #define MCP_REG_M2P_M2P_PATH_ID_PATH_ID_SHIFT                                                              0
+#define MCP_REG_M2P_M2P_TX_DATA_FIFO                                                                         0xe0612cUL //Access:W    DataWidth:0x20   // Writing to this register will store the data in the Tx FIFO to be sent in the VDM.
+#define MCP_REG_P2M_P2M_STATUS                                                                               0xe06200UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_P2M_P2M_STATUS_PKT_HDR_CNT                                                                 (0x7f<<0) // This field is a count of the number of Packet Headers currently stored in the P2M FIFO.
+  #define MCP_REG_P2M_P2M_STATUS_PKT_HDR_CNT_SHIFT                                                           0
+  #define MCP_REG_P2M_P2M_STATUS_RESERVED1                                                                   (0x1ff<<7) // Reserved for future use.
+  #define MCP_REG_P2M_P2M_STATUS_RESERVED1_SHIFT                                                             7
+  #define MCP_REG_P2M_P2M_STATUS_PKT_DATA_CNT                                                                (0x1ff<<16) // This field is a count of the number of Packet Data Words currently stored in the P2M FIFO.
+  #define MCP_REG_P2M_P2M_STATUS_PKT_DATA_CNT_SHIFT                                                          16
+  #define MCP_REG_P2M_P2M_STATUS_RESERVED2                                                                   (0x3f<<25) // Reserved for future use.
+  #define MCP_REG_P2M_P2M_STATUS_RESERVED2_SHIFT                                                             25
+  #define MCP_REG_P2M_P2M_STATUS_P2M_ATTN_BIT                                                                (0x1<<31) // This bit shows the current status of the P2M Attention signal.
+  #define MCP_REG_P2M_P2M_STATUS_P2M_ATTN_BIT_SHIFT                                                          31
+#define MCP_REG_P2M_P2M_CONFIG                                                                               0xe06204UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_P2M_P2M_CONFIG_BACKPRESSURE_MODE                                                           (0x1<<0) // Setting this bit will cause the P2M block to assert backpressure to the PXP when the packet FIFO is full. If this bit is cleared, packets arriving when the FIFO is full are discarded.
+  #define MCP_REG_P2M_P2M_CONFIG_BACKPRESSURE_MODE_SHIFT                                                     0
+  #define MCP_REG_P2M_P2M_CONFIG_DRAIN_MODE                                                                  (0x1<<1) // When set, this bit forces P2M to constantly drain the packet FIFO and discard all received packets.
+  #define MCP_REG_P2M_P2M_CONFIG_DRAIN_MODE_SHIFT                                                            1
+  #define MCP_REG_P2M_P2M_CONFIG_VID_FILTER_DISCARD                                                          (0x1<<2) // When set, this bit will cause any packet that doesn't match one of the two Vendor ID Filters to be discarded. If this bit isn't set, all packets that don't match will be accepted.
+  #define MCP_REG_P2M_P2M_CONFIG_VID_FILTER_DISCARD_SHIFT                                                    2
+  #define MCP_REG_P2M_P2M_CONFIG_RESERVED                                                                    (0x1fffffff<<3) // Reserved for future use.
+  #define MCP_REG_P2M_P2M_CONFIG_RESERVED_SHIFT                                                              3
+#define MCP_REG_P2M_P2M_VID_FILT_CONFIG_0                                                                    0xe06208UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_0_VID_FILT_VENDORID                                                (0xffff<<0) // This is the Vendor ID to use for this VID Filter.
+  #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_0_VID_FILT_VENDORID_SHIFT                                          0
+  #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_0_VID_FILT_DISCARD                                                 (0x1<<16) // When set, this bit causes packets which match this VID Filter to be discarded.
+  #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_0_VID_FILT_DISCARD_SHIFT                                           16
+  #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_0_VID_FILT_ENABLE                                                  (0x1<<17) // When set, this VID Filter is enabled.
+  #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_0_VID_FILT_ENABLE_SHIFT                                            17
+#define MCP_REG_P2M_P2M_VID_FILT_CONFIG_1                                                                    0xe0620cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_1_VID_FILT_VENDORID                                                (0xffff<<0) // This is the Vendor ID to use for this VID Filter.
+  #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_1_VID_FILT_VENDORID_SHIFT                                          0
+  #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_1_VID_FILT_DISCARD                                                 (0x1<<16) // When set, this bit causes packets which match this VID Filter to be discarded.
+  #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_1_VID_FILT_DISCARD_SHIFT                                           16
+  #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_1_VID_FILT_ENABLE                                                  (0x1<<17) // When set, this VID Filter is enabled.
+  #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_1_VID_FILT_ENABLE_SHIFT                                            17
+#define MCP_REG_P2M_P2M_TAG_FILT_CONFIG                                                                      0xe06210UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_P2M_P2M_TAG_FILT_CONFIG_TAG_FILT_VALUE                                                     (0xff<<0) // This is the Tag Value to use in the Filter.
+  #define MCP_REG_P2M_P2M_TAG_FILT_CONFIG_TAG_FILT_VALUE_SHIFT                                               0
+  #define MCP_REG_P2M_P2M_TAG_FILT_CONFIG_TAG_FILT_MASK                                                      (0xff<<8) // This is the mask value to apply to the Tag for Filtering.
+  #define MCP_REG_P2M_P2M_TAG_FILT_CONFIG_TAG_FILT_MASK_SHIFT                                                8
+  #define MCP_REG_P2M_P2M_TAG_FILT_CONFIG_TAG_FILT_DISCARD                                                   (0x1<<16) // When set, packets matching the Tag Filter will be discarded.
+  #define MCP_REG_P2M_P2M_TAG_FILT_CONFIG_TAG_FILT_DISCARD_SHIFT                                             16
+#define MCP_REG_P2M_P2M_LENGTH_FILT_CONFIG                                                                   0xe06214UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_P2M_P2M_LENGTH_FILT_CONFIG_LENGTH_MIN_VALUE                                                (0x7f<<0) // This is the Minimum VDM Length Value that will be accepted. Packets smaller than this will be discarded. This length is in DWords, as in the VDM Header.
+  #define MCP_REG_P2M_P2M_LENGTH_FILT_CONFIG_LENGTH_MIN_VALUE_SHIFT                                          0
+  #define MCP_REG_P2M_P2M_LENGTH_FILT_CONFIG_UNUSED0                                                         (0x1<<7) // 
+  #define MCP_REG_P2M_P2M_LENGTH_FILT_CONFIG_UNUSED0_SHIFT                                                   7
+  #define MCP_REG_P2M_P2M_LENGTH_FILT_CONFIG_TAG_FILT_MASK                                                   (0x7f<<8) // This is the Maximum VDM Length Value that will be accepted. Packets larger than this will be discarded. This length is in DWords, as in the VDM Header.
+  #define MCP_REG_P2M_P2M_LENGTH_FILT_CONFIG_TAG_FILT_MASK_SHIFT                                             8
+#define MCP_REG_P2M_P2M_DISCARD_STAT_VENDORID                                                                0xe06218UL //Access:R    DataWidth:0x20   // This statistic counts the number of VDM packets discarded due to VendorID Filtering. Reading this register will clear the statistic.
+#define MCP_REG_P2M_P2M_DISCARD_STAT_TAG                                                                     0xe0621cUL //Access:R    DataWidth:0x20   // This statistic counts the number of VDM packets discarded due to Tag Filtering. Reading this register will clear the statistic.
+#define MCP_REG_P2M_P2M_DISCARD_STAT_LENGTH                                                                  0xe06220UL //Access:R    DataWidth:0x20   // This statistic counts the number of VDM packets discarded due to Length Filtering. Reading this register will clear the statistic.
+#define MCP_REG_P2M_P2M_DROP_STAT                                                                            0xe06224UL //Access:R    DataWidth:0x20   // This statistic counts the number of VDM packets dropped due to the FIFO being full. This also counts packets being dropped while in Drain mode. Reading this register will clear the statistic.
+#define MCP_REG_P2M_P2M_RCVD_STAT                                                                            0xe06228UL //Access:R    DataWidth:0x20   // This statistic counts the number of VDM packets received and passed to the MCP. This does not count packets which were dropped or discarded. Reading this register will clear the statistic.
+#define MCP_REG_P2M_P2M_HDR_SINGLE_REG                                                                       0xe0622cUL //Access:R    DataWidth:0x20   // Reading this register will give the next 32-bits of the current Header. The first access will give bits [31:0], then [63:32], then [95:64]. The fourth access will give bits [98:96] and will automatically pop the FIFO so that the next access will give data for the next Header in the FIFO. Be sure to always access this register four times to ensure correct behavior.
+#define MCP_REG_P2M_P2M_HDR_FIFO_0                                                                           0xe06230UL //Access:R    DataWidth:0x20   // Bits [31:0] of the Header Data.
+#define MCP_REG_P2M_P2M_HDR_FIFO_1                                                                           0xe06234UL //Access:R    DataWidth:0x20   // Bits [63:32] of the Header Data.
+#define MCP_REG_P2M_P2M_HDR_FIFO_2                                                                           0xe06238UL //Access:R    DataWidth:0x20   // Bits [95:64] of the Header Data.
+#define MCP_REG_P2M_P2M_HDR_FIFO_3                                                                           0xe0623cUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_P2M_P2M_HDR_FIFO_3_HEADER_3                                                                (0x7<<0) // Bits [98:96] of the Header Data.
+  #define MCP_REG_P2M_P2M_HDR_FIFO_3_HEADER_3_SHIFT                                                          0
+  #define MCP_REG_P2M_P2M_HDR_FIFO_3_RESERVED                                                                (0x1fffffff<<3) // Reserved for future use.
+  #define MCP_REG_P2M_P2M_HDR_FIFO_3_RESERVED_SHIFT                                                          3
+#define MCP_REG_P2M_P2M_DATA_FIFO                                                                            0xe06240UL //Access:R    DataWidth:0x20   // 32-bit Packet Data.
+#define MCP_REG_P2M_P2M_VDM_LENGTH                                                                           0xe06244UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_P2M_P2M_VDM_LENGTH_VDM_LENGTH                                                              (0x7f<<0) // 7-bit Length from VDM Header, in DWords.
+  #define MCP_REG_P2M_P2M_VDM_LENGTH_VDM_LENGTH_SHIFT                                                        0
+#define MCP_REG_P2M_P2M_PCI_REQ_ID                                                                           0xe06248UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_P2M_P2M_PCI_REQ_ID_PCI_REQ_ID                                                              (0xffff<<0) // 16-bit PCI Requester ID from VDM Header.
+  #define MCP_REG_P2M_P2M_PCI_REQ_ID_PCI_REQ_ID_SHIFT                                                        0
+#define MCP_REG_P2M_P2M_VENDOR_ID                                                                            0xe0624cUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_P2M_P2M_VENDOR_ID_VENDOR_ID                                                                (0xffff<<0) // 16-bit Vendor ID from VDM Header.
+  #define MCP_REG_P2M_P2M_VENDOR_ID_VENDOR_ID_SHIFT                                                          0
+#define MCP_REG_P2M_P2M_FID                                                                                  0xe06250UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_P2M_P2M_FID_FID                                                                            (0xffff<<0) // 16-bit FID from VDM Header.
+  #define MCP_REG_P2M_P2M_FID_FID_SHIFT                                                                      0
+#define MCP_REG_P2M_P2M_VENDOR_DWORD                                                                         0xe06254UL //Access:R    DataWidth:0x20   // 32-bit Vendor Defined DWord from VDM Header. For MCTP, this is the MCTP Transport Header.
+#define MCP_REG_P2M_P2M_OTHER_HDR_FIELDS                                                                     0xe06258UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_P2M_P2M_OTHER_HDR_FIELDS_PATH_ID                                                           (0x1<<0) // This is the Path ID of the PCI Function on which the message arrived.
+  #define MCP_REG_P2M_P2M_OTHER_HDR_FIELDS_PATH_ID_SHIFT                                                     0
+  #define MCP_REG_P2M_P2M_OTHER_HDR_FIELDS_UNUSED0                                                           (0x7<<1) // 
+  #define MCP_REG_P2M_P2M_OTHER_HDR_FIELDS_UNUSED0_SHIFT                                                     1
+  #define MCP_REG_P2M_P2M_OTHER_HDR_FIELDS_ROUTING_FIELD                                                     (0x7<<4) // This field is the 3 LSB's of the TLP Type.
+  #define MCP_REG_P2M_P2M_OTHER_HDR_FIELDS_ROUTING_FIELD_SHIFT                                               4
+  #define MCP_REG_P2M_P2M_OTHER_HDR_FIELDS_UNUSED1                                                           (0x1ff<<7) // 
+  #define MCP_REG_P2M_P2M_OTHER_HDR_FIELDS_UNUSED1_SHIFT                                                     7
+  #define MCP_REG_P2M_P2M_OTHER_HDR_FIELDS_TAG                                                               (0xff<<16) // This is the 8-bit Tag from VDM Header.
+  #define MCP_REG_P2M_P2M_OTHER_HDR_FIELDS_TAG_SHIFT                                                         16
+#define MCP_REG_CACHE_PIM_NVRAM_BASE                                                                         0xe06300UL //Access:RW   DataWidth:0x20   // The start address of the PIM in the NVRAM.
+#define MCP_REG_CACHE_PAGING_ENABLE                                                                          0xe06304UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_CACHE_PAGING_ENABLE_ENABLE                                                                 (0x1<<0) // If this bit is cleared then the look-up is bypassed and the scratchpad is always accessed with the address that was provided by the MCP. When this bit is changed from 1 to 0, all appropriate status and valid bits are cleared.
+  #define MCP_REG_CACHE_PAGING_ENABLE_ENABLE_SHIFT                                                           0
+#define MCP_REG_CACHE_FETCH_COMPLETION                                                                       0xe06308UL //Access:W    DataWidth:0x20   // Any write to this register will signal completion of the page fetch by the expansion ROM engine.
+#define MCP_REG_CACHE_CACHE_CTRL_STATUS_0                                                                    0xe0630cUL //Access:RW   DataWidth:0x20   // Reflects the status of page 0.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_0_LOCK                                                             (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_0_LOCK_SHIFT                                                       0
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_0_ACTIVE                                                           (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_0_ACTIVE_SHIFT                                                     1
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_0_VALID                                                            (0x1<<2) // The data in this page is valid.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_0_VALID_SHIFT                                                      2
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_0_NVRAM_PAGE_OFFSET                                                (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_0_NVRAM_PAGE_OFFSET_SHIFT                                          3
+#define MCP_REG_CACHE_CACHE_CTRL_STATUS_1                                                                    0xe06310UL //Access:RW   DataWidth:0x20   // Reflects the status of page 1.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_1_LOCK                                                             (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_1_LOCK_SHIFT                                                       0
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_1_ACTIVE                                                           (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_1_ACTIVE_SHIFT                                                     1
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_1_VALID                                                            (0x1<<2) // The data in this page is valid.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_1_VALID_SHIFT                                                      2
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_1_NVRAM_PAGE_OFFSET                                                (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_1_NVRAM_PAGE_OFFSET_SHIFT                                          3
+#define MCP_REG_CACHE_CACHE_CTRL_STATUS_2                                                                    0xe06314UL //Access:RW   DataWidth:0x20   // Reflects the status of page 2.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_2_LOCK                                                             (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_2_LOCK_SHIFT                                                       0
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_2_ACTIVE                                                           (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_2_ACTIVE_SHIFT                                                     1
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_2_VALID                                                            (0x1<<2) // The data in this page is valid.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_2_VALID_SHIFT                                                      2
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_2_NVRAM_PAGE_OFFSET                                                (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_2_NVRAM_PAGE_OFFSET_SHIFT                                          3
+#define MCP_REG_CACHE_CACHE_CTRL_STATUS_3                                                                    0xe06318UL //Access:RW   DataWidth:0x20   // Reflects the status of page 3.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_3_LOCK                                                             (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_3_LOCK_SHIFT                                                       0
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_3_ACTIVE                                                           (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_3_ACTIVE_SHIFT                                                     1
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_3_VALID                                                            (0x1<<2) // The data in this page is valid.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_3_VALID_SHIFT                                                      2
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_3_NVRAM_PAGE_OFFSET                                                (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_3_NVRAM_PAGE_OFFSET_SHIFT                                          3
+#define MCP_REG_CACHE_CACHE_CTRL_STATUS_4                                                                    0xe0631cUL //Access:RW   DataWidth:0x20   // Reflects the status of page 4.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_4_LOCK                                                             (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_4_LOCK_SHIFT                                                       0
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_4_ACTIVE                                                           (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_4_ACTIVE_SHIFT                                                     1
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_4_VALID                                                            (0x1<<2) // The data in this page is valid.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_4_VALID_SHIFT                                                      2
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_4_NVRAM_PAGE_OFFSET                                                (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_4_NVRAM_PAGE_OFFSET_SHIFT                                          3
+#define MCP_REG_CACHE_CACHE_CTRL_STATUS_5                                                                    0xe06320UL //Access:RW   DataWidth:0x20   // Reflects the status of page 5.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_5_LOCK                                                             (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_5_LOCK_SHIFT                                                       0
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_5_ACTIVE                                                           (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_5_ACTIVE_SHIFT                                                     1
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_5_VALID                                                            (0x1<<2) // The data in this page is valid.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_5_VALID_SHIFT                                                      2
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_5_NVRAM_PAGE_OFFSET                                                (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_5_NVRAM_PAGE_OFFSET_SHIFT                                          3
+#define MCP_REG_CACHE_CACHE_CTRL_STATUS_6                                                                    0xe06324UL //Access:RW   DataWidth:0x20   // Reflects the status of page 6.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_6_LOCK                                                             (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_6_LOCK_SHIFT                                                       0
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_6_ACTIVE                                                           (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_6_ACTIVE_SHIFT                                                     1
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_6_VALID                                                            (0x1<<2) // The data in this page is valid.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_6_VALID_SHIFT                                                      2
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_6_NVRAM_PAGE_OFFSET                                                (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_6_NVRAM_PAGE_OFFSET_SHIFT                                          3
+#define MCP_REG_CACHE_CACHE_CTRL_STATUS_7                                                                    0xe06328UL //Access:RW   DataWidth:0x20   // Reflects the status of page 7.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_7_LOCK                                                             (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_7_LOCK_SHIFT                                                       0
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_7_ACTIVE                                                           (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_7_ACTIVE_SHIFT                                                     1
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_7_VALID                                                            (0x1<<2) // The data in this page is valid.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_7_VALID_SHIFT                                                      2
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_7_NVRAM_PAGE_OFFSET                                                (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_7_NVRAM_PAGE_OFFSET_SHIFT                                          3
+#define MCP_REG_CACHE_CACHE_CTRL_STATUS_8                                                                    0xe0632cUL //Access:RW   DataWidth:0x20   // Reflects the status of page 8.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_8_LOCK                                                             (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_8_LOCK_SHIFT                                                       0
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_8_ACTIVE                                                           (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_8_ACTIVE_SHIFT                                                     1
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_8_VALID                                                            (0x1<<2) // The data in this page is valid.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_8_VALID_SHIFT                                                      2
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_8_NVRAM_PAGE_OFFSET                                                (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_8_NVRAM_PAGE_OFFSET_SHIFT                                          3
+#define MCP_REG_CACHE_CACHE_CTRL_STATUS_9                                                                    0xe06330UL //Access:RW   DataWidth:0x20   // Reflects the status of page 9.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_9_LOCK                                                             (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_9_LOCK_SHIFT                                                       0
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_9_ACTIVE                                                           (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_9_ACTIVE_SHIFT                                                     1
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_9_VALID                                                            (0x1<<2) // The data in this page is valid.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_9_VALID_SHIFT                                                      2
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_9_NVRAM_PAGE_OFFSET                                                (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_9_NVRAM_PAGE_OFFSET_SHIFT                                          3
+#define MCP_REG_CACHE_CACHE_CTRL_STATUS_10                                                                   0xe06334UL //Access:RW   DataWidth:0x20   // Reflects the status of page 10.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_10_LOCK                                                            (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_10_LOCK_SHIFT                                                      0
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_10_ACTIVE                                                          (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_10_ACTIVE_SHIFT                                                    1
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_10_VALID                                                           (0x1<<2) // The data in this page is valid.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_10_VALID_SHIFT                                                     2
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_10_NVRAM_PAGE_OFFSET                                               (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_10_NVRAM_PAGE_OFFSET_SHIFT                                         3
+#define MCP_REG_CACHE_CACHE_CTRL_STATUS_11                                                                   0xe06338UL //Access:RW   DataWidth:0x20   // Reflects the status of page 11.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_11_LOCK                                                            (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_11_LOCK_SHIFT                                                      0
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_11_ACTIVE                                                          (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_11_ACTIVE_SHIFT                                                    1
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_11_VALID                                                           (0x1<<2) // The data in this page is valid.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_11_VALID_SHIFT                                                     2
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_11_NVRAM_PAGE_OFFSET                                               (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_11_NVRAM_PAGE_OFFSET_SHIFT                                         3
+#define MCP_REG_CACHE_CACHE_CTRL_STATUS_12                                                                   0xe0633cUL //Access:RW   DataWidth:0x20   // Reflects the status of page 12.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_12_LOCK                                                            (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_12_LOCK_SHIFT                                                      0
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_12_ACTIVE                                                          (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_12_ACTIVE_SHIFT                                                    1
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_12_VALID                                                           (0x1<<2) // The data in this page is valid.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_12_VALID_SHIFT                                                     2
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_12_NVRAM_PAGE_OFFSET                                               (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_12_NVRAM_PAGE_OFFSET_SHIFT                                         3
+#define MCP_REG_CACHE_CACHE_CTRL_STATUS_13                                                                   0xe06340UL //Access:RW   DataWidth:0x20   // Reflects the status of page 13.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_13_LOCK                                                            (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_13_LOCK_SHIFT                                                      0
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_13_ACTIVE                                                          (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_13_ACTIVE_SHIFT                                                    1
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_13_VALID                                                           (0x1<<2) // The data in this page is valid.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_13_VALID_SHIFT                                                     2
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_13_NVRAM_PAGE_OFFSET                                               (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_13_NVRAM_PAGE_OFFSET_SHIFT                                         3
+#define MCP_REG_CACHE_CACHE_CTRL_STATUS_14                                                                   0xe06344UL //Access:RW   DataWidth:0x20   // Reflects the status of page 14.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_14_LOCK                                                            (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_14_LOCK_SHIFT                                                      0
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_14_ACTIVE                                                          (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_14_ACTIVE_SHIFT                                                    1
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_14_VALID                                                           (0x1<<2) // The data in this page is valid.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_14_VALID_SHIFT                                                     2
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_14_NVRAM_PAGE_OFFSET                                               (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_14_NVRAM_PAGE_OFFSET_SHIFT                                         3
+#define MCP_REG_CACHE_CACHE_CTRL_STATUS_15                                                                   0xe06348UL //Access:RW   DataWidth:0x20   // Reflects the status of page 15.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_15_LOCK                                                            (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_15_LOCK_SHIFT                                                      0
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_15_ACTIVE                                                          (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_15_ACTIVE_SHIFT                                                    1
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_15_VALID                                                           (0x1<<2) // The data in this page is valid.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_15_VALID_SHIFT                                                     2
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_15_NVRAM_PAGE_OFFSET                                               (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
+  #define MCP_REG_CACHE_CACHE_CTRL_STATUS_15_NVRAM_PAGE_OFFSET_SHIFT                                         3
+#define MCP_REG_CACHE_IMG_LOADER_BADDR                                                                       0xe0634cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_CACHE_IMG_LOADER_BADDR_UNUSED0                                                             (0x3<<0) // 
+  #define MCP_REG_CACHE_IMG_LOADER_BADDR_UNUSED0_SHIFT                                                       0
+  #define MCP_REG_CACHE_IMG_LOADER_BADDR_VALUE                                                               (0x7fffff<<2) // This register provides the GRC address of the Expansion ROM Engine Baddr register used in the cache fetch logic. Reset value points to Engine 0.
+  #define MCP_REG_CACHE_IMG_LOADER_BADDR_VALUE_SHIFT                                                         2
+#define MCP_REG_CACHE_IMG_LOADER_GADDR                                                                       0xe06350UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_CACHE_IMG_LOADER_GADDR_UNUSED0                                                             (0x3<<0) // 
+  #define MCP_REG_CACHE_IMG_LOADER_GADDR_UNUSED0_SHIFT                                                       0
+  #define MCP_REG_CACHE_IMG_LOADER_GADDR_VALUE                                                               (0x7fffff<<2) // This register provides the GRC address of the Expansion ROM Engine Gaddr register used in the cache fetch logic. Reset value points to Engine 0.
+  #define MCP_REG_CACHE_IMG_LOADER_GADDR_VALUE_SHIFT                                                         2
+#define MCP_REG_CACHE_IMG_LOADER_CADDR                                                                       0xe06354UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_CACHE_IMG_LOADER_CADDR_UNUSED0                                                             (0x3<<0) // 
+  #define MCP_REG_CACHE_IMG_LOADER_CADDR_UNUSED0_SHIFT                                                       0
+  #define MCP_REG_CACHE_IMG_LOADER_CADDR_VALUE                                                               (0x7fffff<<2) // This register provides the GRC address of the Expansion ROM Engine Caddr register used in the cache fetch logic. Reset value points to Engine 0.
+  #define MCP_REG_CACHE_IMG_LOADER_CADDR_VALUE_SHIFT                                                         2
+#define MCP_REG_CACHE_IMG_LOADER_CDATA                                                                       0xe06358UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_CACHE_IMG_LOADER_CDATA_UNUSED0                                                             (0x3<<0) // 
+  #define MCP_REG_CACHE_IMG_LOADER_CDATA_UNUSED0_SHIFT                                                       0
+  #define MCP_REG_CACHE_IMG_LOADER_CDATA_VALUE                                                               (0x7fffff<<2) // This register provides the GRC address of the Expansion ROM Engine Cdata register used in the cache fetch logic. Reset value points to Engine 0.
+  #define MCP_REG_CACHE_IMG_LOADER_CDATA_VALUE_SHIFT                                                         2
+#define MCP_REG_CACHE_IMG_LOADER_CFG                                                                         0xe0635cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_CACHE_IMG_LOADER_CFG_UNUSED0                                                               (0x3<<0) // 
+  #define MCP_REG_CACHE_IMG_LOADER_CFG_UNUSED0_SHIFT                                                         0
+  #define MCP_REG_CACHE_IMG_LOADER_CFG_VALUE                                                                 (0x7fffff<<2) // This register provides the GRC address of the Expansion ROM Engine Cfg register used in the cache fetch logic. Reset value points to Engine 0.
+  #define MCP_REG_CACHE_IMG_LOADER_CFG_VALUE_SHIFT                                                           2
+#define MCP_REG_CACHE_STAT_HIT_COUNTER                                                                       0xe06360UL //Access:RW   DataWidth:0x20   // Statistic: Incremented whenever a Pageable-memory instruction hits in the page cache. Will be stuck on all ones.
+#define MCP_REG_CACHE_STAT_MISS_COUNTER                                                                      0xe06364UL //Access:RW   DataWidth:0x20   // Statistic: Incremented whenever a Pageable-memory instruction misses in the page cache. Will be stuck on all ones.
+#define MCP_REG_CACHE_LAST_PAGE_0                                                                            0xe06368UL //Access:RW   DataWidth:0x20   // Stores the values from one of the last 2 pages used.
+  #define MCP_REG_CACHE_LAST_PAGE_0_VALID                                                                    (0x1<<0) // The data in this register is valid.
+  #define MCP_REG_CACHE_LAST_PAGE_0_VALID_SHIFT                                                              0
+  #define MCP_REG_CACHE_LAST_PAGE_0_IS_LAST                                                                  (0x1<<1) // If set, this page is the most recently accessed.
+  #define MCP_REG_CACHE_LAST_PAGE_0_IS_LAST_SHIFT                                                            1
+  #define MCP_REG_CACHE_LAST_PAGE_0_PAGE_INDEX                                                               (0xf<<2) // Index in the page table associated with this page.
+  #define MCP_REG_CACHE_LAST_PAGE_0_PAGE_INDEX_SHIFT                                                         2
+  #define MCP_REG_CACHE_LAST_PAGE_0_PAGE_OFFSET                                                              (0x1ff<<6) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
+  #define MCP_REG_CACHE_LAST_PAGE_0_PAGE_OFFSET_SHIFT                                                        6
+#define MCP_REG_CACHE_LAST_PAGE_1                                                                            0xe0636cUL //Access:RW   DataWidth:0x20   // Stores the values from one of the last 2 pages used.
+  #define MCP_REG_CACHE_LAST_PAGE_1_VALID                                                                    (0x1<<0) // The data in this register is valid.
+  #define MCP_REG_CACHE_LAST_PAGE_1_VALID_SHIFT                                                              0
+  #define MCP_REG_CACHE_LAST_PAGE_1_IS_LAST                                                                  (0x1<<1) // If set, this page is the most recently accessed.
+  #define MCP_REG_CACHE_LAST_PAGE_1_IS_LAST_SHIFT                                                            1
+  #define MCP_REG_CACHE_LAST_PAGE_1_PAGE_INDEX                                                               (0xf<<2) // Index in the page table associated with this page.
+  #define MCP_REG_CACHE_LAST_PAGE_1_PAGE_INDEX_SHIFT                                                         2
+  #define MCP_REG_CACHE_LAST_PAGE_1_PAGE_OFFSET                                                              (0x1ff<<6) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
+  #define MCP_REG_CACHE_LAST_PAGE_1_PAGE_OFFSET_SHIFT                                                        6
+#define MCP_REG_CACHE_PAGE_FETCH_STATE                                                                       0xe06370UL //Access:R    DataWidth:0x20   // For debug: the cache status
+#define MCP_REG_CACHE_CACHE_ERROR_STATUS                                                                     0xe06374UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_CACHE_CACHE_ERROR_STATUS_OUT_OF_BOUNDS_READ                                                (0x1<<0) // If set, Paging_enable is clear and read from address &gt; StaticMemorySize + PageableMemorySize
+  #define MCP_REG_CACHE_CACHE_ERROR_STATUS_OUT_OF_BOUNDS_READ_SHIFT                                          0
+  #define MCP_REG_CACHE_CACHE_ERROR_STATUS_ILLEGAL_FETCH                                                     (0x1<<1) // If set, a read attempt to a second page was detected while a page fetch was already in progress.
+  #define MCP_REG_CACHE_CACHE_ERROR_STATUS_ILLEGAL_FETCH_SHIFT                                               1
+#define MCP_REG_NVM_COMMAND                                                                                  0xe06400UL //Access:RW   DataWidth:0x20   // NVM Command register.
+  #define MCP_REG_NVM_COMMAND_RST                                                                            (0x1<<0) // When set, the entire NVM state machine is reset. This bit is self clearing.
+  #define MCP_REG_NVM_COMMAND_RST_SHIFT                                                                      0
+  #define MCP_REG_NVM_COMMAND_UNUSED0                                                                        (0x3<<1) // 
+  #define MCP_REG_NVM_COMMAND_UNUSED0_SHIFT                                                                  1
+  #define MCP_REG_NVM_COMMAND_DONE                                                                           (0x1<<3) // Sequence completion bit that is asserted when the command requested by assertion of the doit bit has completed. done Will be cleared while the command is in progress. done Will stay asserted until doit is reasserted or the done bit is cleared by writing a 1 to the done bit. The done bit is the FLSH_ATTN signal.
+  #define MCP_REG_NVM_COMMAND_DONE_SHIFT                                                                     3
+  #define MCP_REG_NVM_COMMAND_DOIT                                                                           (0x1<<4) // Command from software to start the defined command. The done bit must be clear before setting this bit. This bit is self clearing and will remain set while the command is active.
+  #define MCP_REG_NVM_COMMAND_DOIT_SHIFT                                                                     4
+  #define MCP_REG_NVM_COMMAND_WR                                                                             (0x1<<5) // The Write/Not_Read command bit. Set high to execute write or erase.
+  #define MCP_REG_NVM_COMMAND_WR_SHIFT                                                                       5
+  #define MCP_REG_NVM_COMMAND_ERASE                                                                          (0x1<<6) // The erase page/sector command bit. Set high to execute a page/sector erase_cmd. This bit is ignored if the WR bit is clear.
+  #define MCP_REG_NVM_COMMAND_ERASE_SHIFT                                                                    6
+  #define MCP_REG_NVM_COMMAND_FIRST                                                                          (0x1<<7) // This bit is passed to the SEE_FSM or SPI_FSM if the pass_mode bit is set.
+  #define MCP_REG_NVM_COMMAND_FIRST_SHIFT                                                                    7
+  #define MCP_REG_NVM_COMMAND_LAST                                                                           (0x1<<8) // When this bit is set, the next command sequence will be interpreted as the last one of a burst and any cleanup work will be done. This means that the buffer will be written to flash memory if needed on a write.
+  #define MCP_REG_NVM_COMMAND_LAST_SHIFT                                                                     8
+  #define MCP_REG_NVM_COMMAND_ADDR_INCR                                                                      (0x1<<9) // When this bit is set, the address in the address register will be incremented by 4 (1 word) after the command sequence has finished. Intended to be used for consecutive read or write access eliminating the need to update the address register on each access.
+  #define MCP_REG_NVM_COMMAND_ADDR_INCR_SHIFT                                                                9
+  #define MCP_REG_NVM_COMMAND_UNUSED1                                                                        (0x3f<<10) // 
+  #define MCP_REG_NVM_COMMAND_UNUSED1_SHIFT                                                                  10
+  #define MCP_REG_NVM_COMMAND_WREN                                                                           (0x1<<16) // The write enable command bit. Set '1' will make flash interface state machine Generate wren_cmd to flash device through SPI interface to set Flash device to be write-enabled. Used for the device with protection function
+  #define MCP_REG_NVM_COMMAND_WREN_SHIFT                                                                     16
+  #define MCP_REG_NVM_COMMAND_WRDI                                                                           (0x1<<17) // The write disable command bit. Set '1' will make flash interface state machine Generate wrdi_cmd to flash device through SPI interface to set Flash device to be write-disabled. Used for the device with protection function.
+  #define MCP_REG_NVM_COMMAND_WRDI_SHIFT                                                                     17
+  #define MCP_REG_NVM_COMMAND_ERASE_ALL                                                                      (0x1<<18) // The erase all/chip command bit. Set high to execute an all/chip erase_all_cmd. This bit is ignored if the WR bit is clear.
+  #define MCP_REG_NVM_COMMAND_ERASE_ALL_SHIFT                                                                18
+  #define MCP_REG_NVM_COMMAND_UNUSED2                                                                        (0x1<<19) // 
+  #define MCP_REG_NVM_COMMAND_UNUSED2_SHIFT                                                                  19
+  #define MCP_REG_NVM_COMMAND_RD_ID                                                                          (0x1<<20) // The read ID command bit. When set, the flash controller will read the ID register from the external flash device. This is specifically for ST devices. Setting this bit for Atmel devices will give the same results as RD_STATUS.
+  #define MCP_REG_NVM_COMMAND_RD_ID_SHIFT                                                                    20
+  #define MCP_REG_NVM_COMMAND_RD_STATUS                                                                      (0x1<<21) // The read status command bit. When set, the flash controller will read the status register from the external flash device
+  #define MCP_REG_NVM_COMMAND_RD_STATUS_SHIFT                                                                21
+  #define MCP_REG_NVM_COMMAND_MODE_256                                                                       (0x1<<22) // The 256B page size mode disable bit. A 256 byte page mode has been added to the block. This mode is normally on. The mode helps convert a 264B page Atmel part to act more like a 256B page part. For reads, the controller transparently closes the page after byte location 0xFF and opens the next page. For writes, it is the FW or SW responsiblity to close the page at 0xFF and start a new operation on the next page. When this bit is written as '1' when the FIRST bit is set, the 256B page mode is disabled for the next operation. It is self-clearing when both the LAST bit is set and the DONE bit is asserted. Effects Atmel only. No effect with ST devices.
+  #define MCP_REG_NVM_COMMAND_MODE_256_SHIFT                                                                 22
+#define MCP_REG_NVM_STATUS                                                                                   0xe06404UL //Access:R    DataWidth:0x20   // NVM Status register.
+  #define MCP_REG_NVM_STATUS_SPI_FSM_STATE                                                                   (0x3f<<0) // Enumeration:
+  #define MCP_REG_NVM_STATUS_SPI_FSM_STATE_SHIFT                                                             0
+#define MCP_REG_NVM_WRITE                                                                                    0xe06408UL //Access:RW   DataWidth:0x20   // NVM data write register.
+#define MCP_REG_NVM_ADDR                                                                                     0xe0640cUL //Access:RW   DataWidth:0x20   // NVM address register.
+  #define MCP_REG_NVM_ADDR_NVM_ADDR_VALUE                                                                    (0xffffff<<0) // 24 bit address value used in read, write and erase operations. When in bit-bang mode, the bottom 6 bits control the output enable for each pin.
+  #define MCP_REG_NVM_ADDR_NVM_ADDR_VALUE_SHIFT                                                              0
+#define MCP_REG_NVM_READ                                                                                     0xe06410UL //Access:R    DataWidth:0x20   // NVM data read register.
+#define MCP_REG_NVM_CFG1                                                                                     0xe06414UL //Access:RW   DataWidth:0x20   // NVM configuration one register.
+  #define MCP_REG_NVM_CFG1_FLASH_MODE                                                                        (0x1<<0) // Legacy strap_value[1]. Read only. Set based on new strap values to indicate either Atmel o
+  #define MCP_REG_NVM_CFG1_FLASH_MODE_SHIFT                                                                  0
+  #define MCP_REG_NVM_CFG1_BUFFER_MODE                                                                       (0x1<<1) // Legacy strap_value[0]. Read only. Set based on new strap values to indicate either Atmel or ST.
+  #define MCP_REG_NVM_CFG1_BUFFER_MODE_SHIFT                                                                 1
+  #define MCP_REG_NVM_CFG1_PASS_MODE                                                                         (0x1<<2) // Enable pass-thru mode to the byte level SPI state machine. When this mode is enabled, the controller can send/recieve single bytes at the SPI level. All upper level functions of the controller state machine are disabled.
+  #define MCP_REG_NVM_CFG1_PASS_MODE_SHIFT                                                                   2
+  #define MCP_REG_NVM_CFG1_BITBANG_MODE                                                                      (0x1<<3) // Enable bit-bang mode to control pins.
+  #define MCP_REG_NVM_CFG1_BITBANG_MODE_SHIFT                                                                3
+  #define MCP_REG_NVM_CFG1_STATUS_BIT                                                                        (0x7<<4) // Bit offset in status command response to interpret as the "ready" flag. For Atmel, this defaults to 3'h7. For ST, this defaults to 3'h0. NOTE: For ST, the status value of 1'b0 means "ready". For Atmel, the status value of 1 means "ready". This is automatically interpreted by hardware. This value is self-configured on reset based on the strap values. It can be overriden.
+  #define MCP_REG_NVM_CFG1_STATUS_BIT_SHIFT                                                                  4
+  #define MCP_REG_NVM_CFG1_SPI_CLK_DIV                                                                       (0xf<<7) // Divisor used to create all "1x" time for all Flash Interface I/O pin timing definition A value of 0 means that SCLK will be 1/2 of core_clk [f(SCLK) = f(CLK)/2]. The equation to calculate the Flash clock frequency for SCLK is: f(SCLK) = f(CLK)/((spi_clk_div + 1) * 2).
+  #define MCP_REG_NVM_CFG1_SPI_CLK_DIV_SHIFT                                                                 7
+  #define MCP_REG_NVM_CFG1_SEE_CLK_DIV                                                                       (0x7ff<<11) // Legacy value. Read only.
+  #define MCP_REG_NVM_CFG1_SEE_CLK_DIV_SHIFT                                                                 11
+  #define MCP_REG_NVM_CFG1_UNUSED0                                                                           (0x1<<22) // 
+  #define MCP_REG_NVM_CFG1_UNUSED0_SHIFT                                                                     22
+  #define MCP_REG_NVM_CFG1_STRAP_CONTROL_0                                                                   (0x1<<23) // Legacy strap_control[1] bit. Read only set to 1, indicating FLASH has already been configured.
+  #define MCP_REG_NVM_CFG1_STRAP_CONTROL_0_SHIFT                                                             23
+  #define MCP_REG_NVM_CFG1_PROTECT_MODE                                                                      (0x1<<24) // Legacy strap_value[2]. Read only. Set based on new strap values to indicate either Atmel or ST.
+  #define MCP_REG_NVM_CFG1_PROTECT_MODE_SHIFT                                                                24
+  #define MCP_REG_NVM_CFG1_FLASH_SIZE                                                                        (0x1<<25) // Legacy strap_value[3]. Read only. Set based on new strap values to indicate either Atmel or ST.
+  #define MCP_REG_NVM_CFG1_FLASH_SIZE_SHIFT                                                                  25
+  #define MCP_REG_NVM_CFG1_FW_USTRAP_1                                                                       (0x1<<26) // Legacy strap_value[1]. Read only. Set based on new strap values to indicate either Atmel or ST.
+  #define MCP_REG_NVM_CFG1_FW_USTRAP_1_SHIFT                                                                 26
+  #define MCP_REG_NVM_CFG1_FW_USTRAP_0                                                                       (0x1<<27) // Legacy strap_value[0]. Read only. Set based on new strap values to indicate either Atmel or ST.
+  #define MCP_REG_NVM_CFG1_FW_USTRAP_0_SHIFT                                                                 27
+  #define MCP_REG_NVM_CFG1_FW_USTRAP_2                                                                       (0x1<<28) // Legacy strap_value[2]. Read only. Set based on new strap values to indicate either Atmel or ST.
+  #define MCP_REG_NVM_CFG1_FW_USTRAP_2_SHIFT                                                                 28
+  #define MCP_REG_NVM_CFG1_FW_USTRAP_3                                                                       (0x1<<29) // Legacy strap_value[3]. Read only. Set based on new strap values to indicate either Atmel or ST.
+  #define MCP_REG_NVM_CFG1_FW_USTRAP_3_SHIFT                                                                 29
+  #define MCP_REG_NVM_CFG1_FW_FLASH_TYPE_EN                                                                  (0x1<<30) // Legacy strap_control[1] bit. Read only set to 1, indicating FLASH has already been configured.This register has no hardware function, but can be modified by firmware.
+  #define MCP_REG_NVM_CFG1_FW_FLASH_TYPE_EN_SHIFT                                                            30
+  #define MCP_REG_NVM_CFG1_COMPAT_BYPASSS                                                                    (0x1<<31) // Legacy bit. Acts as dummy R/W bit.
+  #define MCP_REG_NVM_CFG1_COMPAT_BYPASSS_SHIFT                                                              31
+#define MCP_REG_NVM_CFG2                                                                                     0xe06418UL //Access:RW   DataWidth:0x20   // NVM configuration two register.
+  #define MCP_REG_NVM_CFG2_ERASE_CMD                                                                         (0xff<<0) // Flash block erase command. "ready" status will be polled for after this command. Reset value is 0x20h if flash_mode=1, 0x81h if buffer_mode=1, and 0xd8h if protect_mode=1.
+  #define MCP_REG_NVM_CFG2_ERASE_CMD_SHIFT                                                                   0
+  #define MCP_REG_NVM_CFG2_CSB_W                                                                             (0xff<<8) // Controls the delay from the CSB assertion to the first clock and from the last clock to the CSB deassertion. commands. Reset value is 0x1e in Legacy ST mode, 0x58 in Legacy Atmel mode, and 0x8 in Auto mode.
+  #define MCP_REG_NVM_CFG2_CSB_W_SHIFT                                                                       8
+  #define MCP_REG_NVM_CFG2_STATUS_CMD                                                                        (0xff<<16) // Flash status command. This command is used to poll the "ready" status of the flash part after many of the commands. Reset value is 0x9Fh if flash_mode=1, 0x57h if buffer_mode=1, and 0x5h if protect_mode =1.
+  #define MCP_REG_NVM_CFG2_STATUS_CMD_SHIFT                                                                  16
+  #define MCP_REG_NVM_CFG2_READ_ID_CMD                                                                       (0xff<<24) // Flash Read ID register command. This command is used to read the ID register from ST devices. Reset value depends on strap values. (0x57 for Atmel; 0x9f for ST/Numonyx/Macronix/Winbond)
+  #define MCP_REG_NVM_CFG2_READ_ID_CMD_SHIFT                                                                 24
+#define MCP_REG_NVM_CFG3                                                                                     0xe0641cUL //Access:RW   DataWidth:0x20   // NVM configuration three register.
+  #define MCP_REG_NVM_CFG3_BUFFER_RD_CMD                                                                     (0xff<<0) // Transfer flash device page to its internal buffer command. For Atmel devices, this command is issued automatically upon the "FIRST" write. It is not issued for ST devices since they automatically do this operation internally. (0x53 for Atmel; 0x53 for ST)
+  #define MCP_REG_NVM_CFG3_BUFFER_RD_CMD_SHIFT                                                               0
+  #define MCP_REG_NVM_CFG3_WRITE_CMD                                                                         (0xff<<8) // Command to write one byte to the flash array or SSRAM buffer, depending on the value of buffer_mode. If BUFFER_MODE is not active, then this command will poll for "ready" status when complete. For SEEPROM (flash_mode=0), this is SEEPROM write command. Bit[10:9] is address bit A1 and A0 of SEEPROM. User should modify those two bits base on the value of A1 and A0 assigned to this SEEPROM device. Reset value is 0x10 if flash_mode=1, 0x83 if buffer_mode=1, and 0x2 if protect_mode=1, 0xA0 otherwise.
+  #define MCP_REG_NVM_CFG3_WRITE_CMD_SHIFT                                                                   8
+  #define MCP_REG_NVM_CFG3_FAST_READ_CMD                                                                     (0xff<<16) // This is the fast read command. This command is used in Fast ST Mode. Following this command, any number of bytes may be read up to the end of the flash memory. This command is similar to the read command, but with an additional 8b of dummy read between the command/address and the first data read response.
+  #define MCP_REG_NVM_CFG3_FAST_READ_CMD_SHIFT                                                               16
+  #define MCP_REG_NVM_CFG3_READ_CMD                                                                          (0xff<<24) // This is the flash/seeprom read command. Following this command, any number of bytes may be read up to the end of the flash memory. For SEEPROM (flash_mode=0), this is SEEPROM read command. Bit[26:25] is address bit A1 and A0 of SEEPROM. User should modify those two bits base on the value of A1 and A0 assigned to this SEEPROM device. Reset value is 0xFF if flash_mode=1, 0x68 if buffer_mode=1, 0x3 if protect_mode=1, and 0xA1 otherwise.
+  #define MCP_REG_NVM_CFG3_READ_CMD_SHIFT                                                                    24
+#define MCP_REG_NVM_SW_ARB                                                                                   0xe06420UL //Access:RW   DataWidth:0x20   // SPLIT: NVM arbitration register. This register provides aribtration resoures for both functions. The register is split, so arbitration depends on what function you are accessing as.
+  #define MCP_REG_NVM_SW_ARB_ARB_REQ_SET0                                                                    (0x1<<0) // Set Software Arbitration request Bit 0. This bit is set by writing a '1' to this bit position.
+  #define MCP_REG_NVM_SW_ARB_ARB_REQ_SET0_SHIFT                                                              0
+  #define MCP_REG_NVM_SW_ARB_ARB_REQ_SET1                                                                    (0x1<<1) // Set Software Arbitration request Bit 1. This bit is set by writing a '1' to this bit position.
+  #define MCP_REG_NVM_SW_ARB_ARB_REQ_SET1_SHIFT                                                              1
+  #define MCP_REG_NVM_SW_ARB_ARB_REQ_SET2                                                                    (0x1<<2) // Set Software Arbitration request Bit 2. This bit is set by writing a '1' to this bit position.
+  #define MCP_REG_NVM_SW_ARB_ARB_REQ_SET2_SHIFT                                                              2
+  #define MCP_REG_NVM_SW_ARB_ARB_REQ_SET3                                                                    (0x1<<3) // Set Software Arbitration request Bit 3. This bit is set by writing a '1' to this bit position.
+  #define MCP_REG_NVM_SW_ARB_ARB_REQ_SET3_SHIFT                                                              3
+  #define MCP_REG_NVM_SW_ARB_ARB_REQ_CLR0                                                                    (0x1<<4) // Write this bit as a '1' to clear req0 bit.
+  #define MCP_REG_NVM_SW_ARB_ARB_REQ_CLR0_SHIFT                                                              4
+  #define MCP_REG_NVM_SW_ARB_ARB_REQ_CLR1                                                                    (0x1<<5) // Write this bit as a '1' to clear req1 bit.
+  #define MCP_REG_NVM_SW_ARB_ARB_REQ_CLR1_SHIFT                                                              5
+  #define MCP_REG_NVM_SW_ARB_ARB_REQ_CLR2                                                                    (0x1<<6) // Write this bit as a '1' to clear req2 bit.
+  #define MCP_REG_NVM_SW_ARB_ARB_REQ_CLR2_SHIFT                                                              6
+  #define MCP_REG_NVM_SW_ARB_ARB_REQ_CLR3                                                                    (0x1<<7) // Write this bit as a '1' to clear req3 bit.
+  #define MCP_REG_NVM_SW_ARB_ARB_REQ_CLR3_SHIFT                                                              7
+  #define MCP_REG_NVM_SW_ARB_ARB_ARB0                                                                        (0x1<<8) // when REQ0 arbitration is won, this bit will be read as 1, when an operation is complete, then the CLR_ARB0 must be written to clear this bit. At that point, the next Arb bit will read as 1. At any time, only one of the ARB[7:0] bits will be read as a 1. Arb0 has highest priority, and Arb7 has lowest priority.
+  #define MCP_REG_NVM_SW_ARB_ARB_ARB0_SHIFT                                                                  8
+  #define MCP_REG_NVM_SW_ARB_ARB_ARB1                                                                        (0x1<<9) // when REQ1 arbitration is won, this bit will be read as 1, when an operation is complete, then the CLR_ARB1 must be written to clear this bit.
+  #define MCP_REG_NVM_SW_ARB_ARB_ARB1_SHIFT                                                                  9
+  #define MCP_REG_NVM_SW_ARB_ARB_ARB2                                                                        (0x1<<10) // when REQ2 arbitration is won, this bit will be read as 1, when an operation is complete, then the CLR_ARB2 must be written to clear this bit.
+  #define MCP_REG_NVM_SW_ARB_ARB_ARB2_SHIFT                                                                  10
+  #define MCP_REG_NVM_SW_ARB_ARB_ARB3                                                                        (0x1<<11) // when REQ3 arbitration is won, this bit will be read as 1, when an operation is complete, then the CLR_ARB3 must be written to clear this bit.
+  #define MCP_REG_NVM_SW_ARB_ARB_ARB3_SHIFT                                                                  11
+  #define MCP_REG_NVM_SW_ARB_REQ0                                                                            (0x1<<12) // This is the current status of requester 0. When this bit is one, it means that REQ_SET0 has been set since REQ_CLR0.
+  #define MCP_REG_NVM_SW_ARB_REQ0_SHIFT                                                                      12
+  #define MCP_REG_NVM_SW_ARB_REQ1                                                                            (0x1<<13) // This is the current status of requester 1. When this bit is one, it means that REQ_SET1 has been set since REQ_CLR1.
+  #define MCP_REG_NVM_SW_ARB_REQ1_SHIFT                                                                      13
+  #define MCP_REG_NVM_SW_ARB_REQ2                                                                            (0x1<<14) // This is the current status of requester 2. When this bit is one, it means that REQ_SET2 has been set since REQ_CLR2.
+  #define MCP_REG_NVM_SW_ARB_REQ2_SHIFT                                                                      14
+  #define MCP_REG_NVM_SW_ARB_REQ3                                                                            (0x1<<15) // This is the current status of requester 3. When this bit is one, it means that REQ_SET3 has been set since REQ_CLR3.
+  #define MCP_REG_NVM_SW_ARB_REQ3_SHIFT                                                                      15
+#define MCP_REG_NVM_JEDEC_ID                                                                                 0xe06424UL //Access:R    DataWidth:0x20   // NVM configuration three register.
+  #define MCP_REG_NVM_JEDEC_ID_EXTENDED_DEVICE_INFO_LENGTH                                                   (0xff<<0) // Length of extended device info to follow.
+  #define MCP_REG_NVM_JEDEC_ID_EXTENDED_DEVICE_INFO_LENGTH_SHIFT                                             0
+  #define MCP_REG_NVM_JEDEC_ID_DEVICE_ID                                                                     (0xffff<<8) // Device ID: Memory type = device_id[15:8] Size = device_id[7:0]
+  #define MCP_REG_NVM_JEDEC_ID_DEVICE_ID_SHIFT                                                               8
+  #define MCP_REG_NVM_JEDEC_ID_MANUFACTURE_ID                                                                (0xff<<24) // JEDEC manufacturer ID. Adesto/Atmel: 0x1F Macronix: 0xC2 Micron/Numonyx/St: 0x20 Winbond: 0xEF
+  #define MCP_REG_NVM_JEDEC_ID_MANUFACTURE_ID_SHIFT                                                          24
+#define MCP_REG_NVM_CFG5                                                                                     0xe06428UL //Access:RW   DataWidth:0x20   // NVM write1 configuration register.
+  #define MCP_REG_NVM_CFG5_WREN_CMD                                                                          (0xff<<0) // Flash write enable command when device with protection function is used. This command will be issued by the flash interface state machine through SPI interface To flash device, and make the flash device write-enabled.
+  #define MCP_REG_NVM_CFG5_WREN_CMD_SHIFT                                                                    0
+  #define MCP_REG_NVM_CFG5_WRDI_CMD                                                                          (0xff<<8) // Flash write disable command when device with protection function is used. This command will be issued by the flash interface state machine through SPI interface To flash device, and make the flash device write-disabled.
+  #define MCP_REG_NVM_CFG5_WRDI_CMD_SHIFT                                                                    8
+  #define MCP_REG_NVM_CFG5_ERASE_ALL_CMD                                                                     (0xff<<16) // Flash block erase all command. "ready" status will be polled for after this command. nvm_command.DONE will be asserted when chip erase has completed.
+  #define MCP_REG_NVM_CFG5_ERASE_ALL_CMD_SHIFT                                                               16
+  #define MCP_REG_NVM_CFG5_UNUSED0                                                                           (0x3f<<24) // 
+  #define MCP_REG_NVM_CFG5_UNUSED0_SHIFT                                                                     24
+  #define MCP_REG_NVM_CFG5_USE_BUFFER                                                                        (0x1<<30) // When set to 1, write operations to Flash will use an internal 4KB sector buffer. Some Flash (Macronix, Winbond) only support PageProgram, which requires the Flash to be erased prior to programming. To make write operations identical across Flash devices, a buffer was added to store the sector data prior to an internally generated erase and then all data is written back to Flash including the write modifications. When cleared to 0, the buffer is unused.
+  #define MCP_REG_NVM_CFG5_USE_BUFFER_SHIFT                                                                  30
+  #define MCP_REG_NVM_CFG5_USE_LEGACY_SPI_FSM                                                                (0x1<<31) // Set to 1 to use legacy/previous flsh_spi_fsm. Clear to 0 to use latest flsh_spi_fsm.
+  #define MCP_REG_NVM_CFG5_USE_LEGACY_SPI_FSM_SHIFT                                                          31
+#define MCP_REG_NVM_CFG4                                                                                     0xe0642cUL //Access:RW   DataWidth:0x20   // NVM configuration four register.
+  #define MCP_REG_NVM_CFG4_FLASH_SIZE                                                                        (0x7<<0) // Size of the external flash device. This information is not used by FLSH hardware. It is only used by software. This value is self-configured on reset based on the external device.
+  #define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT                                                                  0
+  #define MCP_REG_NVM_CFG4_FLASH_VENDOR                                                                      (0x1<<3) // This bit is self-configured on reset based on the strap values. It can be overriden.
+  #define MCP_REG_NVM_CFG4_FLASH_VENDOR_SHIFT                                                                3
+  #define MCP_REG_NVM_CFG4_MODE_256_EMPTY_BIT_LOC                                                            (0x3<<4) // Bit location for hardware to insert an empty address bit when MODE_256 is not set with Atmel devices. This value is self-configured on reset based on the external device. NOTE: Max Atmel device size is 64 Mbit due to different bus protocols.
+  #define MCP_REG_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_SHIFT                                                      4
+  #define MCP_REG_NVM_CFG4_STATUS_BIT_POLARITY                                                               (0x1<<6) // This bit determines how the status bit of the device status register is interpreted by hardware. If 0, then 0 means "ready". If 1, then 1 means "ready". For Atmel, this defaults to 1. For ST, this defaults to 0. This value is self-configured on reset based on the strap values. It can be overriden.
+  #define MCP_REG_NVM_CFG4_STATUS_BIT_POLARITY_SHIFT                                                         6
+  #define MCP_REG_NVM_CFG4_FAST                                                                              (0x1<<7) // Fast Mode. When this bit is set in ST mode, fast read command is used. In Atmel mode, this bit should be set when using the 0xE8 read command. It should be cleared when using the 0x68 read command. This value is self-configured on reset based on the external device.
+  #define MCP_REG_NVM_CFG4_FAST_SHIFT                                                                        7
+  #define MCP_REG_NVM_CFG4_SI_INPUT_RELAXED_TIMING                                                           (0x1<<8) // When this bit is set, the SI input from the external flash device is latched one cycle later than normal. This bit defaults to 0.
+  #define MCP_REG_NVM_CFG4_SI_INPUT_RELAXED_TIMING_SHIFT                                                     8
+  #define MCP_REG_NVM_CFG4_PASS_MODE_RELAXED_TIMING                                                          (0x1<<9) // When this bit is set, the pass mode data is captured one cycle later than normal. If using pass mode, this bit should be set whenever the si_input_relaxed_timing bit is set. This bit defaults to 0.
+  #define MCP_REG_NVM_CFG4_PASS_MODE_RELAXED_TIMING_SHIFT                                                    9
+  #define MCP_REG_NVM_CFG4_SR_TURNAROUND                                                                     (0x1<<10) // When this bit is set, a turnaround cycle is inserted in between the address and data phases of a status read for Atmel devices. This bit should only be set when the legacy status read command (0x57) is used. This bit defaults to 0.
+  #define MCP_REG_NVM_CFG4_SR_TURNAROUND_SHIFT                                                               10
+  #define MCP_REG_NVM_CFG4_READ_DUMMY_CYCLES                                                                 (0xf<<11) // This is the number of dummy cycles needed after the address phase before the read data is available for opcode: READ, READ_ID.
+  #define MCP_REG_NVM_CFG4_READ_DUMMY_CYCLES_SHIFT                                                           11
+  #define MCP_REG_NVM_CFG4_FAST_READ_DUMMY_CYCLES                                                            (0xf<<15) // This is the number of dummy cycles needed after the address phase before the read data is available for opcode: FAST_READ.
+  #define MCP_REG_NVM_CFG4_FAST_READ_DUMMY_CYCLES_SHIFT                                                      15
+  #define MCP_REG_NVM_CFG4_SPI_SLOW_CLK_DIV                                                                  (0xf<<19) // Slow SCLK used for OPCODEs that cannot be executed using SPI_CLK_DIV. It is also used during startup when no info about Flash device is known. Calculate SCLK frequency using f(SCLK) = f(core_clk)/(2*(SPI_SLOW_CLK_DIV +1)). [Ex: SPI_SLOW_CLK_DIV=0 -&gt; f(SCLK) = f(core_clk)/2]
+  #define MCP_REG_NVM_CFG4_SPI_SLOW_CLK_DIV_SHIFT                                                            19
+  #define MCP_REG_NVM_CFG4_SLOW_CLK_4_BUFFER_RD                                                              (0x1<<23) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
+  #define MCP_REG_NVM_CFG4_SLOW_CLK_4_BUFFER_RD_SHIFT                                                        23
+  #define MCP_REG_NVM_CFG4_SLOW_CLK_4_ERASE                                                                  (0x1<<24) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
+  #define MCP_REG_NVM_CFG4_SLOW_CLK_4_ERASE_SHIFT                                                            24
+  #define MCP_REG_NVM_CFG4_SLOW_CLK_4_FAST_READ                                                              (0x1<<25) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
+  #define MCP_REG_NVM_CFG4_SLOW_CLK_4_FAST_READ_SHIFT                                                        25
+  #define MCP_REG_NVM_CFG4_SLOW_CLK_4_READ                                                                   (0x1<<26) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
+  #define MCP_REG_NVM_CFG4_SLOW_CLK_4_READ_SHIFT                                                             26
+  #define MCP_REG_NVM_CFG4_SLOW_CLK_4_READ_ID                                                                (0x1<<27) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
+  #define MCP_REG_NVM_CFG4_SLOW_CLK_4_READ_ID_SHIFT                                                          27
+  #define MCP_REG_NVM_CFG4_SLOW_CLK_4_STATUS                                                                 (0x1<<28) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
+  #define MCP_REG_NVM_CFG4_SLOW_CLK_4_STATUS_SHIFT                                                           28
+  #define MCP_REG_NVM_CFG4_SLOW_CLK_4_WRDI                                                                   (0x1<<29) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
+  #define MCP_REG_NVM_CFG4_SLOW_CLK_4_WRDI_SHIFT                                                             29
+  #define MCP_REG_NVM_CFG4_SLOW_CLK_4_WREN                                                                   (0x1<<30) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
+  #define MCP_REG_NVM_CFG4_SLOW_CLK_4_WREN_SHIFT                                                             30
+  #define MCP_REG_NVM_CFG4_SLOW_CLK_4_WRITE                                                                  (0x1<<31) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
+  #define MCP_REG_NVM_CFG4_SLOW_CLK_4_WRITE_SHIFT                                                            31
+#define MCP_REG_NVM_RECONFIG                                                                                 0xe06430UL //Access:RW   DataWidth:0x20   // NVM re-configuration register.
+  #define MCP_REG_NVM_RECONFIG_ORIG_STRAP_VALUE                                                              (0xf<<0) // Strap value from iologic pins. Only bit[0] is used. Bits[3:1] are for future support.
+  #define MCP_REG_NVM_RECONFIG_ORIG_STRAP_VALUE_SHIFT                                                        0
+  #define MCP_REG_NVM_RECONFIG_RECONFIG_STRAP_VALUE                                                          (0xf<<4) // Used by software to numerically encode how the FLSH has been reconfigured. On reset, this register is set to the same value as ORIG_STRAP_VALUE. These bits have no hardware functionality.
+  #define MCP_REG_NVM_RECONFIG_RECONFIG_STRAP_VALUE_SHIFT                                                    4
+  #define MCP_REG_NVM_RECONFIG_RESERVED                                                                      (0x7fffff<<8) // Reserved for future use
+  #define MCP_REG_NVM_RECONFIG_RESERVED_SHIFT                                                                8
+  #define MCP_REG_NVM_RECONFIG_RECONFIG_DONE                                                                 (0x1<<31) // This bit is 0 on reset. After software finishes reconfiguring FLSH, they will set this bit to 1 to indicate that FLSH has been reconfigured. This bit has no hardware functionality.
+  #define MCP_REG_NVM_RECONFIG_RECONFIG_DONE_SHIFT                                                           31
+#define MCP_REG_ERNGN_EXP_ROM_CTRL                                                                           0xe06800UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_ERNGN_EXP_ROM_CTRL_ENA                                                                     (0x1<<0) // Enable bit for the expansion ROM engine. When '1', the expansion ROM engine will automatically service expansion ROM requests. When this bit is cleared, the engine will not service a new request and the on chip cpu will have to take over the chores.
+  #define MCP_REG_ERNGN_EXP_ROM_CTRL_ENA_SHIFT                                                               0
+  #define MCP_REG_ERNGN_EXP_ROM_CTRL_BFRD                                                                    (0x1<<1) // When this bit is set to '1', the expansion ROM engine will utilize the buffered mode address translation mode in the flash controller to adjust the address for flash devices with 264 byte blocks, spaced every 512 bytes.
+  #define MCP_REG_ERNGN_EXP_ROM_CTRL_BFRD_SHIFT                                                              1
+  #define MCP_REG_ERNGN_EXP_ROM_CTRL_UNUSED0                                                                 (0x3<<2) // 
+  #define MCP_REG_ERNGN_EXP_ROM_CTRL_UNUSED0_SHIFT                                                           2
+  #define MCP_REG_ERNGN_EXP_ROM_CTRL_ARB_NUM                                                                 (0x3<<4) // Request number to use to arbitrate for expansion ROM access to the flash controller
+  #define MCP_REG_ERNGN_EXP_ROM_CTRL_ARB_NUM_SHIFT                                                           4
+  #define MCP_REG_ERNGN_EXP_ROM_CTRL_UNUSED1                                                                 (0x3ff<<6) // 
+  #define MCP_REG_ERNGN_EXP_ROM_CTRL_UNUSED1_SHIFT                                                           6
+  #define MCP_REG_ERNGN_EXP_ROM_CTRL_STATE                                                                   (0x3f<<16) // The current state of expansion ROM engine, for debugging purposes.
+  #define MCP_REG_ERNGN_EXP_ROM_CTRL_STATE_SHIFT                                                             16
+  #define MCP_REG_ERNGN_EXP_ROM_CTRL_UNUSED2                                                                 (0x3f<<22) // 
+  #define MCP_REG_ERNGN_EXP_ROM_CTRL_UNUSED2_SHIFT                                                           22
+  #define MCP_REG_ERNGN_EXP_ROM_CTRL_CACHE_VALID                                                             (0x1<<28) // This bit is set to '1' when the cache is valid.
+  #define MCP_REG_ERNGN_EXP_ROM_CTRL_CACHE_VALID_SHIFT                                                       28
+  #define MCP_REG_ERNGN_EXP_ROM_CTRL_ARB_TIMEOUT                                                             (0x1<<29) // This bit is set to '1' when an arbitration timeout happens.
+  #define MCP_REG_ERNGN_EXP_ROM_CTRL_ARB_TIMEOUT_SHIFT                                                       29
+  #define MCP_REG_ERNGN_EXP_ROM_CTRL_READ_TIMEOUT                                                            (0x1<<30) // This bit is set to '1' when a read timeout happens.
+  #define MCP_REG_ERNGN_EXP_ROM_CTRL_READ_TIMEOUT_SHIFT                                                      30
+  #define MCP_REG_ERNGN_EXP_ROM_CTRL_ACTIVE                                                                  (0x1<<31) // This bit is set to '1' when the expansion ROM engine is actively operating on a expansion ROM request.
+  #define MCP_REG_ERNGN_EXP_ROM_CTRL_ACTIVE_SHIFT                                                            31
+#define MCP_REG_ERNGN_EXP_ROM_BADDR                                                                          0xe06804UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_ERNGN_EXP_ROM_BADDR_UNUSED0                                                                (0x3<<0) // 
+  #define MCP_REG_ERNGN_EXP_ROM_BADDR_UNUSED0_SHIFT                                                          0
+  #define MCP_REG_ERNGN_EXP_ROM_BADDR_VALUE                                                                  (0x3fffff<<2) // Image base address. The expansion ROM engine fetches the values for the expansion ROM interface starting at this base address.
+  #define MCP_REG_ERNGN_EXP_ROM_BADDR_VALUE_SHIFT                                                            2
+#define MCP_REG_ERNGN_EXP_ROM_CFG                                                                            0xe06808UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_ERNGN_EXP_ROM_CFG_ARB_TIMEOUT_SHFT                                                         (0xf<<0) // Arbitration timeout value. The value of 0x20 is shifted left number of bits determined by this value to determine the number of times the nvm_sw_arb register inside the expansion ROM interface will be polled before giving up on arbitration.
+  #define MCP_REG_ERNGN_EXP_ROM_CFG_ARB_TIMEOUT_SHFT_SHIFT                                                   0
+  #define MCP_REG_ERNGN_EXP_ROM_CFG_READ_TIMEOUT_SHFT                                                        (0xf<<4) // Read timeout value. The value of 0x20 is shifted left number of bits determined by this value to determine the number of core clocks to wait for the expansion ROM interface to complete a single word read before giving up.
+  #define MCP_REG_ERNGN_EXP_ROM_CFG_READ_TIMEOUT_SHFT_SHIFT                                                  4
+#define MCP_REG_ERNGN_EXP_ROM_ADR                                                                            0xe0680cUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_ERNGN_EXP_ROM_ADR_UNUSED0                                                                  (0x3<<0) // 
+  #define MCP_REG_ERNGN_EXP_ROM_ADR_UNUSED0_SHIFT                                                            0
+  #define MCP_REG_ERNGN_EXP_ROM_ADR_ADDRESS                                                                  (0x3fffff<<2) // This value is the address requested by the current (or last) PCI ROM Expansion cycle request. When the PCI block detect a decode of the ROM BAR area, it will place the offset from the BAR value in this register and re-try the PCI bus to make the requester wait.
+  #define MCP_REG_ERNGN_EXP_ROM_ADR_ADDRESS_SHIFT                                                            2
+  #define MCP_REG_ERNGN_EXP_ROM_ADR_ADDR_SIZE                                                                (0x3<<24) // The size of the PCI BAR rom read request. This value ranges from 1 to 3 dwords
+  #define MCP_REG_ERNGN_EXP_ROM_ADR_ADDR_SIZE_SHIFT                                                          24
+  #define MCP_REG_ERNGN_EXP_ROM_ADR_ACT_FUNC                                                                 (0x1f<<26) // These bits indicate which function is currently accessing the expansion rom.
+  #define MCP_REG_ERNGN_EXP_ROM_ADR_ACT_FUNC_SHIFT                                                           26
+  #define MCP_REG_ERNGN_EXP_ROM_ADR_REQ                                                                      (0x1<<31) // This bit will be set if there is a pending request for action. This bit is equivalent to the EXP_ROM_ATTN attention word bit.
+  #define MCP_REG_ERNGN_EXP_ROM_ADR_REQ_SHIFT                                                                31
+#define MCP_REG_ERNGN_EXP_ROM_DATA0                                                                          0xe06810UL //Access:R    DataWidth:0x20   // This register shows the first dword for the expansion ROM access. This is for debug purposes only.
+#define MCP_REG_ERNGN_EXP_ROM_DATA1                                                                          0xe06814UL //Access:R    DataWidth:0x20   // This register shows the second dword for the expansion ROM access. This is for debug purposes only.
+#define MCP_REG_ERNGN_EXP_ROM_DATA2                                                                          0xe06818UL //Access:R    DataWidth:0x20   // This register shows the third dword for the expansion ROM access. This is for debug purposes only.
+#define MCP_REG_ERNGN_IMG_LOADER0_BADDR                                                                      0xe0681cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_ERNGN_IMG_LOADER0_BADDR_UNUSED0                                                            (0x3<<0) // 
+  #define MCP_REG_ERNGN_IMG_LOADER0_BADDR_UNUSED0_SHIFT                                                      0
+  #define MCP_REG_ERNGN_IMG_LOADER0_BADDR_VALUE                                                              (0x3fffff<<2) // Image base address. This register provides the base address of the image in the NVRAM that the Image Loader Engine 0 will use.
+  #define MCP_REG_ERNGN_IMG_LOADER0_BADDR_VALUE_SHIFT                                                        2
+#define MCP_REG_ERNGN_IMG_LOADER0_GADDR                                                                      0xe06820UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_ERNGN_IMG_LOADER0_GADDR_UNUSED0                                                            (0x3<<0) // 
+  #define MCP_REG_ERNGN_IMG_LOADER0_GADDR_UNUSED0_SHIFT                                                      0
+  #define MCP_REG_ERNGN_IMG_LOADER0_GADDR_VALUE                                                              (0xfffffff<<2) // This register provides the GRC address of the internal register where the data from NVRAM will be written. 24:2 will be the GRC address 29:26 will be the GRC function
+  #define MCP_REG_ERNGN_IMG_LOADER0_GADDR_VALUE_SHIFT                                                        2
+#define MCP_REG_ERNGN_IMG_LOADER0_CADDR                                                                      0xe06824UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_ERNGN_IMG_LOADER0_CADDR_UNUSED0                                                            (0x3<<0) // 
+  #define MCP_REG_ERNGN_IMG_LOADER0_CADDR_UNUSED0_SHIFT                                                      0
+  #define MCP_REG_ERNGN_IMG_LOADER0_CADDR_VALUE                                                              (0x7fffff<<2) // This register provides the GRC address of the internal register where the completion data will be written.
+  #define MCP_REG_ERNGN_IMG_LOADER0_CADDR_VALUE_SHIFT                                                        2
+#define MCP_REG_ERNGN_IMG_LOADER0_CDATA                                                                      0xe06828UL //Access:RW   DataWidth:0x20   // This register provides the value of the completion data that will be written to the completion address.
+#define MCP_REG_ERNGN_IMG_LOADER0_CFG                                                                        0xe0682cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_ERNGN_IMG_LOADER0_CFG_UNUSED0                                                              (0x3<<0) // 
+  #define MCP_REG_ERNGN_IMG_LOADER0_CFG_UNUSED0_SHIFT                                                        0
+  #define MCP_REG_ERNGN_IMG_LOADER0_CFG_XFER_SIZE                                                            (0x3fff<<2) // These bits indicate the transfer size in 4bytes (word) granularity. A maximum of 64KB can be transfered with one command. A read to this register will indicate the current status of the command.
+  #define MCP_REG_ERNGN_IMG_LOADER0_CFG_XFER_SIZE_SHIFT                                                      2
+  #define MCP_REG_ERNGN_IMG_LOADER0_CFG_UNUSED1                                                              (0xf<<16) // 
+  #define MCP_REG_ERNGN_IMG_LOADER0_CFG_UNUSED1_SHIFT                                                        16
+  #define MCP_REG_ERNGN_IMG_LOADER0_CFG_BURST_SIZE                                                           (0xf<<20) // These bits are used for setting up the burst size of a single NVRAM arbitration cycle. NVRAM is a shared resource and every master needs to arbitrate for access to the NVRAM. Once a master wins arbitration, it can keep the NVRAM till the access is relinquished. Using these bits, SW/FW can limit how many words get transferred in a single arbitration cycle. For ex. if xfer_size = 4KB and burst_size = 32 words, then the image loader engine will arbitrate to win the access of NVRAM 32 times.
+  #define MCP_REG_ERNGN_IMG_LOADER0_CFG_BURST_SIZE_SHIFT                                                     20
+  #define MCP_REG_ERNGN_IMG_LOADER0_CFG_AUTO_INC                                                             (0x1<<24) // Setting this bit will cause the GRC address to be incremented by 4bytes for every transfer on the GRC interface for the command.
+  #define MCP_REG_ERNGN_IMG_LOADER0_CFG_AUTO_INC_SHIFT                                                       24
+  #define MCP_REG_ERNGN_IMG_LOADER0_CFG_UNUSED2                                                              (0x7<<25) // 
+  #define MCP_REG_ERNGN_IMG_LOADER0_CFG_UNUSED2_SHIFT                                                        25
+  #define MCP_REG_ERNGN_IMG_LOADER0_CFG_ARB_TO                                                               (0x1<<28) // This bit indicates that there was a Arbitration timeout on this image loader and all the transfers are invalid
+  #define MCP_REG_ERNGN_IMG_LOADER0_CFG_ARB_TO_SHIFT                                                         28
+  #define MCP_REG_ERNGN_IMG_LOADER0_CFG_READ_TO                                                              (0x1<<29) // This bit indicates that there was a NVRAM Read timeout on this image loader and all the transfers are invalid
+  #define MCP_REG_ERNGN_IMG_LOADER0_CFG_READ_TO_SHIFT                                                        29
+  #define MCP_REG_ERNGN_IMG_LOADER0_CFG_BUSY                                                                 (0x1<<30) // This bit indicates that this image loader engine is busy. When this bit is set, the baddr/gaddr/cfg registers should not be written to.
+  #define MCP_REG_ERNGN_IMG_LOADER0_CFG_BUSY_SHIFT                                                           30
+  #define MCP_REG_ERNGN_IMG_LOADER0_CFG_ACTIVE                                                               (0x1<<31) // This bit indicates that this image loader engine is currently the active master.
+  #define MCP_REG_ERNGN_IMG_LOADER0_CFG_ACTIVE_SHIFT                                                         31
+#define MCP_REG_ERNGN_IMG_LOADER1_BADDR                                                                      0xe06830UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_ERNGN_IMG_LOADER1_BADDR_UNUSED0                                                            (0x3<<0) // 
+  #define MCP_REG_ERNGN_IMG_LOADER1_BADDR_UNUSED0_SHIFT                                                      0
+  #define MCP_REG_ERNGN_IMG_LOADER1_BADDR_VALUE                                                              (0x3fffff<<2) // Image base address. This register provides the base address of the image in the NVRAM that the Image Loader Engine 1 will use.
+  #define MCP_REG_ERNGN_IMG_LOADER1_BADDR_VALUE_SHIFT                                                        2
+#define MCP_REG_ERNGN_IMG_LOADER1_GADDR                                                                      0xe06834UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_ERNGN_IMG_LOADER1_GADDR_UNUSED0                                                            (0x3<<0) // 
+  #define MCP_REG_ERNGN_IMG_LOADER1_GADDR_UNUSED0_SHIFT                                                      0
+  #define MCP_REG_ERNGN_IMG_LOADER1_GADDR_VALUE                                                              (0xfffffff<<2) // This register provides the GRC address of the internal register where the data from NVRAM will be written. 24:2 will be the GRC address 29:26 will be the GRC function
+  #define MCP_REG_ERNGN_IMG_LOADER1_GADDR_VALUE_SHIFT                                                        2
+#define MCP_REG_ERNGN_IMG_LOADER1_CADDR                                                                      0xe06838UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_ERNGN_IMG_LOADER1_CADDR_UNUSED0                                                            (0x3<<0) // 
+  #define MCP_REG_ERNGN_IMG_LOADER1_CADDR_UNUSED0_SHIFT                                                      0
+  #define MCP_REG_ERNGN_IMG_LOADER1_CADDR_VALUE                                                              (0x7fffff<<2) // This register provides the GRC address of the internal register where the completion data will be written.
+  #define MCP_REG_ERNGN_IMG_LOADER1_CADDR_VALUE_SHIFT                                                        2
+#define MCP_REG_ERNGN_IMG_LOADER1_CDATA                                                                      0xe0683cUL //Access:RW   DataWidth:0x20   // This register provides the value of the completion data that will be written to the completion address.
+#define MCP_REG_ERNGN_IMG_LOADER1_CFG                                                                        0xe06840UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_ERNGN_IMG_LOADER1_CFG_UNUSED0                                                              (0x3<<0) // 
+  #define MCP_REG_ERNGN_IMG_LOADER1_CFG_UNUSED0_SHIFT                                                        0
+  #define MCP_REG_ERNGN_IMG_LOADER1_CFG_XFER_SIZE                                                            (0x3fff<<2) // These bits indicate the transfer size in 4bytes (word) granularity. A maximum of 64KB can be transfered with one command. A read to this register will indicate the current status of the command.
+  #define MCP_REG_ERNGN_IMG_LOADER1_CFG_XFER_SIZE_SHIFT                                                      2
+  #define MCP_REG_ERNGN_IMG_LOADER1_CFG_UNUSED1                                                              (0xf<<16) // 
+  #define MCP_REG_ERNGN_IMG_LOADER1_CFG_UNUSED1_SHIFT                                                        16
+  #define MCP_REG_ERNGN_IMG_LOADER1_CFG_BURST_SIZE                                                           (0xf<<20) // These bits are used for setting up the burst size of a single NVRAM arbitration cycle. NVRAM is a shared resource and every master needs to arbitrate for access to the NVRAM. Once a master wins arbitration, it can keep the NVRAM till the access is relinquished. Using these bits, SW/FW can limit how many words get transferred in a single arbitration cycle. For ex. if xfer_size = 4KB and burst_size = 32 words, then the image loader engine will arbitrate to win the access of NVRAM 32 times.
+  #define MCP_REG_ERNGN_IMG_LOADER1_CFG_BURST_SIZE_SHIFT                                                     20
+  #define MCP_REG_ERNGN_IMG_LOADER1_CFG_AUTO_INC                                                             (0x1<<24) // Setting this bit will cause the GRC address to be incremented by 4bytes for every transfer on the GRC interface for the command.
+  #define MCP_REG_ERNGN_IMG_LOADER1_CFG_AUTO_INC_SHIFT                                                       24
+  #define MCP_REG_ERNGN_IMG_LOADER1_CFG_UNUSED2                                                              (0x7<<25) // 
+  #define MCP_REG_ERNGN_IMG_LOADER1_CFG_UNUSED2_SHIFT                                                        25
+  #define MCP_REG_ERNGN_IMG_LOADER1_CFG_ARB_TO                                                               (0x1<<28) // This bit indicates that there was a Arbitration timeout on this image loader and all the transfers are invalid
+  #define MCP_REG_ERNGN_IMG_LOADER1_CFG_ARB_TO_SHIFT                                                         28
+  #define MCP_REG_ERNGN_IMG_LOADER1_CFG_READ_TO                                                              (0x1<<29) // This bit indicates that there was a NVRAM Read timeout on this image loader and all the transfers are invalid
+  #define MCP_REG_ERNGN_IMG_LOADER1_CFG_READ_TO_SHIFT                                                        29
+  #define MCP_REG_ERNGN_IMG_LOADER1_CFG_BUSY                                                                 (0x1<<30) // This bit indicates that this image loader engine is busy. When this bit is set, the baddr/gaddr/cfg registers should not be written to.
+  #define MCP_REG_ERNGN_IMG_LOADER1_CFG_BUSY_SHIFT                                                           30
+  #define MCP_REG_ERNGN_IMG_LOADER1_CFG_ACTIVE                                                               (0x1<<31) // This bit indicates that this image loader engine is currently the active master.
+  #define MCP_REG_ERNGN_IMG_LOADER1_CFG_ACTIVE_SHIFT                                                         31
+#define MCP_REG_ERNGN_IMG_LOADER2_BADDR                                                                      0xe06844UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_ERNGN_IMG_LOADER2_BADDR_UNUSED0                                                            (0x3<<0) // 
+  #define MCP_REG_ERNGN_IMG_LOADER2_BADDR_UNUSED0_SHIFT                                                      0
+  #define MCP_REG_ERNGN_IMG_LOADER2_BADDR_VALUE                                                              (0x3fffff<<2) // Image base address. This register provides the base address of the image in the NVRAM that the Image Loader Engine 2 will use.
+  #define MCP_REG_ERNGN_IMG_LOADER2_BADDR_VALUE_SHIFT                                                        2
+#define MCP_REG_ERNGN_IMG_LOADER2_GADDR                                                                      0xe06848UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_ERNGN_IMG_LOADER2_GADDR_UNUSED0                                                            (0x3<<0) // 
+  #define MCP_REG_ERNGN_IMG_LOADER2_GADDR_UNUSED0_SHIFT                                                      0
+  #define MCP_REG_ERNGN_IMG_LOADER2_GADDR_VALUE                                                              (0xfffffff<<2) // This register provides the GRC address of the internal register where the data from NVRAM will be written. 24:2 will be the GRC address 29:26 will be the GRC function
+  #define MCP_REG_ERNGN_IMG_LOADER2_GADDR_VALUE_SHIFT                                                        2
+#define MCP_REG_ERNGN_IMG_LOADER2_CADDR                                                                      0xe0684cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_ERNGN_IMG_LOADER2_CADDR_UNUSED0                                                            (0x3<<0) // 
+  #define MCP_REG_ERNGN_IMG_LOADER2_CADDR_UNUSED0_SHIFT                                                      0
+  #define MCP_REG_ERNGN_IMG_LOADER2_CADDR_VALUE                                                              (0x7fffff<<2) // This register provides the GRC address of the internal register where the completion data will be written.
+  #define MCP_REG_ERNGN_IMG_LOADER2_CADDR_VALUE_SHIFT                                                        2
+#define MCP_REG_ERNGN_IMG_LOADER2_CDATA                                                                      0xe06850UL //Access:RW   DataWidth:0x20   // This register provides the value of the completion data that will be written to the completion address.
+#define MCP_REG_ERNGN_IMG_LOADER2_CFG                                                                        0xe06854UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_ERNGN_IMG_LOADER2_CFG_UNUSED0                                                              (0x3<<0) // 
+  #define MCP_REG_ERNGN_IMG_LOADER2_CFG_UNUSED0_SHIFT                                                        0
+  #define MCP_REG_ERNGN_IMG_LOADER2_CFG_XFER_SIZE                                                            (0x3fff<<2) // These bits indicate the transfer size in 4bytes (word) granularity. A maximum of 64KB can be transfered with one command. A read to this register will indicate the current status of the command.
+  #define MCP_REG_ERNGN_IMG_LOADER2_CFG_XFER_SIZE_SHIFT                                                      2
+  #define MCP_REG_ERNGN_IMG_LOADER2_CFG_UNUSED1                                                              (0xf<<16) // 
+  #define MCP_REG_ERNGN_IMG_LOADER2_CFG_UNUSED1_SHIFT                                                        16
+  #define MCP_REG_ERNGN_IMG_LOADER2_CFG_BURST_SIZE                                                           (0xf<<20) // These bits are used for setting up the burst size of a single NVRAM arbitration cycle. NVRAM is a shared resource and every master needs to arbitrate for access to the NVRAM. Once a master wins arbitration, it can keep the NVRAM till the access is relinquished. Using these bits, SW/FW can limit how many words get transferred in a single arbitration cycle. For ex. if xfer_size = 4KB and burst_size = 32 words, then the image loader engine will arbitrate to win the access of NVRAM 32 times.
+  #define MCP_REG_ERNGN_IMG_LOADER2_CFG_BURST_SIZE_SHIFT                                                     20
+  #define MCP_REG_ERNGN_IMG_LOADER2_CFG_AUTO_INC                                                             (0x1<<24) // Setting this bit will cause the GRC address to be incremented by 4bytes for every transfer on the GRC interface for the command.
+  #define MCP_REG_ERNGN_IMG_LOADER2_CFG_AUTO_INC_SHIFT                                                       24
+  #define MCP_REG_ERNGN_IMG_LOADER2_CFG_UNUSED2                                                              (0x7<<25) // 
+  #define MCP_REG_ERNGN_IMG_LOADER2_CFG_UNUSED2_SHIFT                                                        25
+  #define MCP_REG_ERNGN_IMG_LOADER2_CFG_ARB_TO                                                               (0x1<<28) // This bit indicates that there was a Arbitration timeout on this image loader and all the transfers are invalid
+  #define MCP_REG_ERNGN_IMG_LOADER2_CFG_ARB_TO_SHIFT                                                         28
+  #define MCP_REG_ERNGN_IMG_LOADER2_CFG_READ_TO                                                              (0x1<<29) // This bit indicates that there was a NVRAM Read timeout on this image loader and all the transfers are invalid
+  #define MCP_REG_ERNGN_IMG_LOADER2_CFG_READ_TO_SHIFT                                                        29
+  #define MCP_REG_ERNGN_IMG_LOADER2_CFG_BUSY                                                                 (0x1<<30) // This bit indicates that this image loader engine is busy. When this bit is set, the baddr/gaddr/cfg registers should not be written to.
+  #define MCP_REG_ERNGN_IMG_LOADER2_CFG_BUSY_SHIFT                                                           30
+  #define MCP_REG_ERNGN_IMG_LOADER2_CFG_ACTIVE                                                               (0x1<<31) // This bit indicates that this image loader engine is currently the active master.
+  #define MCP_REG_ERNGN_IMG_LOADER2_CFG_ACTIVE_SHIFT                                                         31
+#define MCP_REG_SMBUS_CONFIG                                                                                 0xe08000UL //Access:RW   DataWidth:0x20   // All registers in the SMB block are shared.
+  #define MCP_REG_SMBUS_CONFIG_UNUSED0                                                                       (0x7f<<0) // 
+  #define MCP_REG_SMBUS_CONFIG_UNUSED0_SHIFT                                                                 0
+  #define MCP_REG_SMBUS_CONFIG_HW_ARP_ASSIGN_ADDR                                                            (0x1<<7) // When this bit is set HW will service the ARP Assign Address command, set the AR_FLAG[1:0] and AV_FLAG[1:0] flags, and program the NIC_SMB_ADDR[1:0] values.
+  #define MCP_REG_SMBUS_CONFIG_HW_ARP_ASSIGN_ADDR_SHIFT                                                      7
+  #define MCP_REG_SMBUS_CONFIG_ARP_EN0                                                                       (0x1<<8) // When this bit is set the SMBUS block will respond to ARP that is it to SMBUS Device Default Address (7'b1100001) and reslove NIC_SMB_ADDR0 using ARP.
+  #define MCP_REG_SMBUS_CONFIG_ARP_EN0_SHIFT                                                                 8
+  #define MCP_REG_SMBUS_CONFIG_ARP_EN1                                                                       (0x1<<9) // When this bit is set the SMBUS block will respond to ARP that is it to SMBUS Device Default Address (7'b1100001) and reslove NIC_SMB_ADDR1 using ARP.
+  #define MCP_REG_SMBUS_CONFIG_ARP_EN1_SHIFT                                                                 9
+  #define MCP_REG_SMBUS_CONFIG_UNUSED1                                                                       (0x3f<<10) // 
+  #define MCP_REG_SMBUS_CONFIG_UNUSED1_SHIFT                                                                 10
+  #define MCP_REG_SMBUS_CONFIG_MASTER_RTRY_CNT                                                               (0xf<<16) // This bit indicates a number of retries in case where SMBUS block acted as a master and lost SMBUS arbitration. HW will retry transaction as many times as specified in this register before it reports lost of arbitration status to the firmware. When this field is 0 firmware will not do any retries but it will report loss of arbitration on the initial attempt.
+  #define MCP_REG_SMBUS_CONFIG_MASTER_RTRY_CNT_SHIFT                                                         16
+  #define MCP_REG_SMBUS_CONFIG_UNUSED2                                                                       (0x3f<<20) // 
+  #define MCP_REG_SMBUS_CONFIG_UNUSED2_SHIFT                                                                 20
+  #define MCP_REG_SMBUS_CONFIG_TIMESTAMP_CNT_EN                                                              (0x1<<26) // When this bit is '1' the TIMESTAMP counter is enabled. When '0' the counter holds its value.
+  #define MCP_REG_SMBUS_CONFIG_TIMESTAMP_CNT_EN_SHIFT                                                        26
+  #define MCP_REG_SMBUS_CONFIG_PROMISCOUS_MODE                                                               (0x1<<27) // When this bit is '1' the SMBUS block responds to all SMBUS transactions regardless of the slave address.
+  #define MCP_REG_SMBUS_CONFIG_PROMISCOUS_MODE_SHIFT                                                         27
+  #define MCP_REG_SMBUS_CONFIG_EN_NIC_SMB_ADDR_0                                                             (0x1<<28) // When this bit is '1' the SMBUS block responds to slave address 7'b0000000.
+  #define MCP_REG_SMBUS_CONFIG_EN_NIC_SMB_ADDR_0_SHIFT                                                       28
+  #define MCP_REG_SMBUS_CONFIG_BIT_BANG_EN                                                                   (0x1<<29) // When this bit is '1', the SMBUS block is placed into bit-bang mode. SMBUS interface pins are controlled using Bit-Bang Control Register.
+  #define MCP_REG_SMBUS_CONFIG_BIT_BANG_EN_SHIFT                                                             29
+  #define MCP_REG_SMBUS_CONFIG_SMB_EN                                                                        (0x1<<30) // When this bit is '1', the SMBUS block is enabled for operation. When set the SMBUS block will abort current transaction in compliance with the SMBUS master and slave behavior at the end of the current transaction and stop responding to the SMBUS master/slave transactions.
+  #define MCP_REG_SMBUS_CONFIG_SMB_EN_SHIFT                                                                  30
+  #define MCP_REG_SMBUS_CONFIG_RESET                                                                         (0x1<<31) // When this bit is set it will reset SMBUS block to its default state.
+  #define MCP_REG_SMBUS_CONFIG_RESET_SHIFT                                                                   31
+#define MCP_REG_SMBUS_TIMING_CONFIG                                                                          0xe08004UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_SMBUS_TIMING_CONFIG_UNUSED0                                                                (0xff<<0) // 
+  #define MCP_REG_SMBUS_TIMING_CONFIG_UNUSED0_SHIFT                                                          0
+  #define MCP_REG_SMBUS_TIMING_CONFIG_SMBUS_IDLE_TIME                                                        (0xff<<8) // These bits specify the time for which both SMBCLK and SMBDAT must be high before a master can assume that bus is free. Register has 1us resolution. Default is 50us.
+  #define MCP_REG_SMBUS_TIMING_CONFIG_SMBUS_IDLE_TIME_SHIFT                                                  8
+  #define MCP_REG_SMBUS_TIMING_CONFIG_PERIODIC_SLAVE_STRETCH                                                 (0xff<<16) // These bits specify time for which each clock period low time will be stretched when the SMBUS block acts as a slave. Note that a cumulative clock low extend time (TLOW:SEXT) for which slave device is allowed to stretch the clock from the beginning to end of the message (that is from START to STOP) is 25ms. For example, if the message is Block Write transaction 36B long allowed periodic stretch would be 25ms/(9*36) ~= 77us. This is assuming that random slave stretching is not used. Register has 1us resolution.
+  #define MCP_REG_SMBUS_TIMING_CONFIG_PERIODIC_SLAVE_STRETCH_SHIFT                                           16
+  #define MCP_REG_SMBUS_TIMING_CONFIG_RANDOM_SLAVE_STRETCH                                                   (0x7f<<24) // These bits specify time for which clock low time will be stretched after each byte (that is ACK bit) when the SMBUS block acts as a slave. This is useful in "legacy mode" to allow firmware time to handle the data. Note that this time contributes to the slave TLOW:SEXT time, that is combined random and periodic slave stretch should not exceed 25ms. Register has 1ms resolution. Default is 25ms.
+  #define MCP_REG_SMBUS_TIMING_CONFIG_RANDOM_SLAVE_STRETCH_SHIFT                                             24
+  #define MCP_REG_SMBUS_TIMING_CONFIG_MODE_400                                                               (0x1<<31) // When this bit is set the SMBUS block operates in 400KHz mode. When cleared SMBUS operates in 100KHz mode.
+  #define MCP_REG_SMBUS_TIMING_CONFIG_MODE_400_SHIFT                                                         31
+#define MCP_REG_SMBUS_ADDRESS                                                                                0xe08008UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_SMBUS_ADDRESS_NIC_SMB_ADDR0                                                                (0x7f<<0) // This is the first SM Bus addresses which will be used to match for incoming messages. This address is also used for ARP that is this is the address that will be resolved using ARP when the ARP function is enabled. When the PROMISCOUS_MODE bit is '1', this value is ignored.
+  #define MCP_REG_SMBUS_ADDRESS_NIC_SMB_ADDR0_SHIFT                                                          0
+  #define MCP_REG_SMBUS_ADDRESS_EN_NIC_SMB_ADDR0                                                             (0x1<<7) // When this bit is '1' NIC_SMB_ADDR0 will be used as a slave address to match for incoming messages.
+  #define MCP_REG_SMBUS_ADDRESS_EN_NIC_SMB_ADDR0_SHIFT                                                       7
+  #define MCP_REG_SMBUS_ADDRESS_NIC_SMB_ADDR1                                                                (0x7f<<8) // This is the second SM Bus addresses which will be used to match for incoming messages. When the PROMISCOUS_MODE bit is '1', this value is ignored.
+  #define MCP_REG_SMBUS_ADDRESS_NIC_SMB_ADDR1_SHIFT                                                          8
+  #define MCP_REG_SMBUS_ADDRESS_EN_NIC_SMB_ADDR1                                                             (0x1<<15) // When this bit is '1' NIC_SMB_ADDR1 will be used as a slave address to match for incoming messages.
+  #define MCP_REG_SMBUS_ADDRESS_EN_NIC_SMB_ADDR1_SHIFT                                                       15
+  #define MCP_REG_SMBUS_ADDRESS_NIC_SMB_ADDR2                                                                (0x7f<<16) // This is the third SM Bus addresses which will be used to match for incoming messages. When the PROMISCOUS_MODE bit is '1', this value is ignored. 0x0 This address is also used for ARP. The address will be resolved using ARP when the ARP_EN1 bit is set.
+  #define MCP_REG_SMBUS_ADDRESS_NIC_SMB_ADDR2_SHIFT                                                          16
+  #define MCP_REG_SMBUS_ADDRESS_EN_NIC_SMB_ADDR2                                                             (0x1<<23) // When this bit is '1' NIC_SMB_ADDR2 will be used as a slave address to match for incoming messages.
+  #define MCP_REG_SMBUS_ADDRESS_EN_NIC_SMB_ADDR2_SHIFT                                                       23
+  #define MCP_REG_SMBUS_ADDRESS_NIC_SMB_ADDR3                                                                (0x7f<<24) // This is the fourth SM Bus addresses which will be used to match for incoming messages. When the PROMISCOUS_MODE bit is '1', this value is ignored.
+  #define MCP_REG_SMBUS_ADDRESS_NIC_SMB_ADDR3_SHIFT                                                          24
+  #define MCP_REG_SMBUS_ADDRESS_EN_NIC_SMB_ADDR3                                                             (0x1<<31) // When this bit is '1' NIC_SMB_ADDR3 will be used as a slave address to match for incoming messages.
+  #define MCP_REG_SMBUS_ADDRESS_EN_NIC_SMB_ADDR3_SHIFT                                                       31
+#define MCP_REG_SMBUS_MASTER_FIFO_CONTROL                                                                    0xe0800cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_UNUSED0                                                          (0xff<<0) // 
+  #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_UNUSED0_SHIFT                                                    0
+  #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_FIFO_THRESHOLD                                         (0x7f<<8) // When the Master Receive FIFO hits this threshold the SMBUS block will generate an event for the control processor. When set to 0x0 event generation is disabled. Threshold is specified with the byte resolution.
+  #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_FIFO_THRESHOLD_SHIFT                                   8
+  #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_UNUSED1                                                          (0x1<<15) // 
+  #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_UNUSED1_SHIFT                                                    15
+  #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_PKT_COUNT                                              (0x7f<<16) // Number of packets in the Master RX FIFO.
+  #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_PKT_COUNT_SHIFT                                        16
+  #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_UNUSED2                                                          (0x7f<<23) // 
+  #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_UNUSED2_SHIFT                                                    23
+  #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_MASTER_TX_FIFO_FLUSH                                             (0x1<<30) // When this bit is set HW will flush Master TX FIFO when current TX transaction completes.
+  #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_MASTER_TX_FIFO_FLUSH_SHIFT                                       30
+  #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_FIFO_FLUSH                                             (0x1<<31) // When this bit is set HW will flush Master RX FIFO when the current RX transaction completes.
+  #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_FIFO_FLUSH_SHIFT                                       31
+#define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL                                                                     0xe08010UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_UNUSED0                                                           (0xff<<0) // 
+  #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_UNUSED0_SHIFT                                                     0
+  #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_FIFO_THRESHOLD                                           (0x7f<<8) // When the Slave Receive FIFO hits this threshold the SMBUS block will generate an event for the control processor. When set to 0x0 event generation is disabled. Threshold is specified with the byte resolution.
+  #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_FIFO_THRESHOLD_SHIFT                                     8
+  #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_UNUSED1                                                           (0x1<<15) // 
+  #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_UNUSED1_SHIFT                                                     15
+  #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_PKT_COUNT                                                (0x7f<<16) // Number of packets in the Slave RX FIFO.
+  #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_PKT_COUNT_SHIFT                                          16
+  #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_UNUSED2                                                           (0x7f<<23) // 
+  #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_UNUSED2_SHIFT                                                     23
+  #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_TX_FIFO_FLUSH                                               (0x1<<30) // When this bit is set HW will flush Slave TX FIFO when current TX transaction completes.
+  #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_TX_FIFO_FLUSH_SHIFT                                         30
+  #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_FIFO_FLUSH                                               (0x1<<31) // When this bit is set HW will flush Slave RX FIFO when the current RX transaction completes.
+  #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_FIFO_FLUSH_SHIFT                                         31
+#define MCP_REG_SMBUS_BIT_BANG_CONTROL                                                                       0xe08014UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_SMBUS_BIT_BANG_CONTROL_UNUSED0                                                             (0xfffffff<<0) // 
+  #define MCP_REG_SMBUS_BIT_BANG_CONTROL_UNUSED0_SHIFT                                                       0
+  #define MCP_REG_SMBUS_BIT_BANG_CONTROL_SMBDAT_OUT_EN                                                       (0x1<<28) // When the SMBUS interface is configured for bit-bang mode, this bit controlls the output enable for the SMBDAT pin. When this bit is '0', the SMBDAT pin will drive low. When this bit is '1', the SMBDAT pin will float.
+  #define MCP_REG_SMBUS_BIT_BANG_CONTROL_SMBDAT_OUT_EN_SHIFT                                                 28
+  #define MCP_REG_SMBUS_BIT_BANG_CONTROL_SMBDAT_IN                                                           (0x1<<29) // This bit reflects the current input value of the SMBDAT pin. When the SMBDAT pin is high, this bit will read as '1'. When the SMBDAT pin is low, this pin will read as '0'.
+  #define MCP_REG_SMBUS_BIT_BANG_CONTROL_SMBDAT_IN_SHIFT                                                     29
+  #define MCP_REG_SMBUS_BIT_BANG_CONTROL_SMBCLK_OUT_EN                                                       (0x1<<30) // When the SM Bus interface is configured for bit-bang mode, this bit controlls the output enable for the CLK pin. When this bit is '0', the CLK pin will drive low. When this bit is '1', the CLK pin will float.
+  #define MCP_REG_SMBUS_BIT_BANG_CONTROL_SMBCLK_OUT_EN_SHIFT                                                 30
+  #define MCP_REG_SMBUS_BIT_BANG_CONTROL_SMBCLK_IN                                                           (0x1<<31) // This bit reflects the current input value of the SMBCLK pin. When the SMBCLK pin is high, this bit will read as '1'. When the SMBCLK pin is low, this pin will read as '0'.
+  #define MCP_REG_SMBUS_BIT_BANG_CONTROL_SMBCLK_IN_SHIFT                                                     31
+#define MCP_REG_SMBUS_WATCHDOG                                                                               0xe08018UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_SMBUS_WATCHDOG_WATCHDOG                                                                    (0xffff<<0) // This value counts down to zero once each second and sets the WG_TO bit when it reaches zero. The counter stops when it reaches zero.
+  #define MCP_REG_SMBUS_WATCHDOG_WATCHDOG_SHIFT                                                              0
+#define MCP_REG_SMBUS_HEARTBEAT                                                                              0xe0801cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_SMBUS_HEARTBEAT_HEARTBEAT                                                                  (0xffff<<0) // This value counts down to zero once each second and sets the HB_TO bit when it reaches zero. The counter stops when it reaches zero.
+  #define MCP_REG_SMBUS_HEARTBEAT_HEARTBEAT_SHIFT                                                            0
+#define MCP_REG_SMBUS_POLL_ASF                                                                               0xe08020UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_SMBUS_POLL_ASF_POLL_ASF                                                                    (0xffff<<0) // This value counts down to zero once each 5 msec. and sets the PA_TO bit when it reaches zero. The counter stops when it reaches zero.
+  #define MCP_REG_SMBUS_POLL_ASF_POLL_ASF_SHIFT                                                              0
+#define MCP_REG_SMBUS_POLL_LEGACY                                                                            0xe08024UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_SMBUS_POLL_LEGACY_POLL_LEGACY                                                              (0xffff<<0) // This value counts down to zero once each 250 msec. and sets the PL_TO bit when it reaches zero. The counter stops when it reaches zero.
+  #define MCP_REG_SMBUS_POLL_LEGACY_POLL_LEGACY_SHIFT                                                        0
+#define MCP_REG_SMBUS_RETRAN                                                                                 0xe08028UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_SMBUS_RETRAN_RETRAN                                                                        (0xff<<0) // This value counts down to zero once each second and sets the RT_TO bit when it reaches zero. The counter stops when it reaches zero.
+  #define MCP_REG_SMBUS_RETRAN_RETRAN_SHIFT                                                                  0
+#define MCP_REG_SMBUS_TIMESTAMP                                                                              0xe0802cUL //Access:RW   DataWidth:0x20   // This value counts up once each second and rolls to zero each time it passes 0xffffffff. This counter only counts when the TIMESTAMP_CNT_EN bit is '1'.
+#define MCP_REG_SMBUS_MASTER_COMMAND                                                                         0xe08030UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_SMBUS_MASTER_COMMAND_RD_BYTE_COUNT                                                         (0xff<<0) // This is number of bytes that SMBUS block should read from the slave in Block Write - Block Read Process Call or Block Read. If this field is 0 the SMBUS block will assume that first byte received from the slave is a Byte Count. If different than 0 HW will use this value as an indication as where to insert NACK and STOP that is end the transaction.
+  #define MCP_REG_SMBUS_MASTER_COMMAND_RD_BYTE_COUNT_SHIFT                                                   0
+  #define MCP_REG_SMBUS_MASTER_COMMAND_PEC                                                                   (0x1<<8) // PEC should be checked or calculated for this transaction.
+  #define MCP_REG_SMBUS_MASTER_COMMAND_PEC_SHIFT                                                             8
+  #define MCP_REG_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL                                                        (0xf<<9) // SMBUS Protocol encoded as
+  #define MCP_REG_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_SHIFT                                                  9
+  #define MCP_REG_SMBUS_MASTER_COMMAND_UNUSED0                                                               (0xfff<<13) // 
+  #define MCP_REG_SMBUS_MASTER_COMMAND_UNUSED0_SHIFT                                                         13
+  #define MCP_REG_SMBUS_MASTER_COMMAND_STATUS                                                                (0x7<<25) // These bits encode status of the last master transaction. Valid when START_BUSY is cleared after it was set
+  #define MCP_REG_SMBUS_MASTER_COMMAND_STATUS_SHIFT                                                          25
+  #define MCP_REG_SMBUS_MASTER_COMMAND_UNUSED1                                                               (0x3<<28) // 
+  #define MCP_REG_SMBUS_MASTER_COMMAND_UNUSED1_SHIFT                                                         28
+  #define MCP_REG_SMBUS_MASTER_COMMAND_ABORT                                                                 (0x1<<30) // Transaction Abort. This bit can be set at any time by the firmware or the driver in order to abort the transaction. The HW will abort transaction in compliance with the SMBUS rules and clear the bit when done.
+  #define MCP_REG_SMBUS_MASTER_COMMAND_ABORT_SHIFT                                                           30
+  #define MCP_REG_SMBUS_MASTER_COMMAND_START_BUSY                                                            (0x1<<31) // This bit is self clearing. When written to a '1', the currently programmed SMBUS transaction will activate. Writing this bit as a '0' has no effect. This bit must be read as a '0' before setting it to prevent un-predictable results.
+  #define MCP_REG_SMBUS_MASTER_COMMAND_START_BUSY_SHIFT                                                      31
+#define MCP_REG_SMBUS_SLAVE_COMMAND                                                                          0xe08034UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_SMBUS_SLAVE_COMMAND_UNUSED0                                                                (0xff<<0) // 
+  #define MCP_REG_SMBUS_SLAVE_COMMAND_UNUSED0_SHIFT                                                          0
+  #define MCP_REG_SMBUS_SLAVE_COMMAND_PEC                                                                    (0x1<<8) // PEC should be calculated for this transaction.
+  #define MCP_REG_SMBUS_SLAVE_COMMAND_PEC_SHIFT                                                              8
+  #define MCP_REG_SMBUS_SLAVE_COMMAND_UNUSED1                                                                (0x3fff<<9) // 
+  #define MCP_REG_SMBUS_SLAVE_COMMAND_UNUSED1_SHIFT                                                          9
+  #define MCP_REG_SMBUS_SLAVE_COMMAND_STATUS                                                                 (0x7<<23) // These bits encode status of the last slave transaction. Valid when START_BUSY is cleared after it was set
+  #define MCP_REG_SMBUS_SLAVE_COMMAND_STATUS_SHIFT                                                           23
+  #define MCP_REG_SMBUS_SLAVE_COMMAND_UNUSED2                                                                (0xf<<26) // 
+  #define MCP_REG_SMBUS_SLAVE_COMMAND_UNUSED2_SHIFT                                                          26
+  #define MCP_REG_SMBUS_SLAVE_COMMAND_ABORT                                                                  (0x1<<30) // Transaction Abort. This bit can be set at any time by the firmware or the driver in order to abort the transaction. The HW will abort transaction in compliance with the SMBUS rules and clear the bit when done. When set and the slave transaction is received the HW will ACK the address and float the bus thereafter.
+  #define MCP_REG_SMBUS_SLAVE_COMMAND_ABORT_SHIFT                                                            30
+  #define MCP_REG_SMBUS_SLAVE_COMMAND_START                                                                  (0x1<<31) // _BUSY This bit is self clearing. When written to a '1', the currently programmed SMBUS transaction will activate. Writing this bit as a '0' has no effect. This bit must be read as a '0' before setting it to prevent un-predictable results. Used only for read response.
+  #define MCP_REG_SMBUS_SLAVE_COMMAND_START_SHIFT                                                            31
+#define MCP_REG_SMBUS_EVENT_ENABLE                                                                           0xe08038UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_SMBUS_EVENT_ENABLE_WATCHDOG_TO_EN                                                          (0x1<<0) // When set enables Watchdog Timer to generate smbus event.
+  #define MCP_REG_SMBUS_EVENT_ENABLE_WATCHDOG_TO_EN_SHIFT                                                    0
+  #define MCP_REG_SMBUS_EVENT_ENABLE_HEARTBEAT_TO_EN                                                         (0x1<<1) // When set enables Heartbeat Timer to generate smbus event.
+  #define MCP_REG_SMBUS_EVENT_ENABLE_HEARTBEAT_TO_EN_SHIFT                                                   1
+  #define MCP_REG_SMBUS_EVENT_ENABLE_POLL_ASF_TO_EN                                                          (0x1<<2) // When set enables ASF Sensor Poll Timer to generate smbus event.
+  #define MCP_REG_SMBUS_EVENT_ENABLE_POLL_ASF_TO_EN_SHIFT                                                    2
+  #define MCP_REG_SMBUS_EVENT_ENABLE_POLL_LEGACY_TO_EN                                                       (0x1<<3) // When set enables Legacy Sensor Poll Timer to generate smbus event.
+  #define MCP_REG_SMBUS_EVENT_ENABLE_POLL_LEGACY_TO_EN_SHIFT                                                 3
+  #define MCP_REG_SMBUS_EVENT_ENABLE_RETRANSMIT_TO_EN                                                        (0x1<<4) // When set enables Retransmit Timer to generate smbus event.
+  #define MCP_REG_SMBUS_EVENT_ENABLE_RETRANSMIT_TO_EN_SHIFT                                                  4
+  #define MCP_REG_SMBUS_EVENT_ENABLE_UNUSED0                                                                 (0x7fff<<5) // 
+  #define MCP_REG_SMBUS_EVENT_ENABLE_UNUSED0_SHIFT                                                           5
+  #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_ARP_EVENT_EN                                                      (0x1<<20) // When set enables hardware to generate smbus event any time and ARP command is received and ARP_EN0 or ARP_EN1 bit is set.
+  #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_ARP_EVENT_EN_SHIFT                                                20
+  #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_RD_EVENT_EN                                                       (0x1<<21) // Enables SLAVE_RD_EVENT to generate smbus event.
+  #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_RD_EVENT_EN_SHIFT                                                 21
+  #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_TX_UNDERRUN_EN                                                    (0x1<<22) // When set enables generation of a smbus event when Slave Tx FIFO becomes empty and less then PKT_LENGTH bytes were output on the SMBUS.
+  #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_TX_UNDERRUN_EN_SHIFT                                              22
+  #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_START_BUSY_EN                                                     (0x1<<23) // When set enables generation of a smbus event on slave START_BUSY 1 to 0 transition.
+  #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_START_BUSY_EN_SHIFT                                               23
+  #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_RX_EVENT_EN                                                       (0x1<<24) // Enables SLAVE_RX_EVENT to generate smbus event.
+  #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_RX_EVENT_EN_SHIFT                                                 24
+  #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_RX_THRESHOLD_HIT_EN                                               (0x1<<25) // When set enables SLAVE_RX_THRESHOLD_HIT to generate smbus event.
+  #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_RX_THRESHOLD_HIT_EN_SHIFT                                         25
+  #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_RX_FIFO_FULL_EN                                                   (0x1<<26) // When set enables SLAVE_RX_FIFO_FULL to generate smbus event.
+  #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_RX_FIFO_FULL_EN_SHIFT                                             26
+  #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_TX_UNDERRUN_EN                                                   (0x1<<27) // When set enables generation of a smbus event when Master Tx FIFO becomes empty and less then PKT_LENGTH bytes were output on the SMBUS.
+  #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_TX_UNDERRUN_EN_SHIFT                                             27
+  #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_START_BUSY_EN                                                    (0x1<<28) // When set enables generation of a smbus event on master START_BUSY 1 to 0 transition.
+  #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_START_BUSY_EN_SHIFT                                              28
+  #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_RX_EVENT_EN                                                      (0x1<<29) // When set enables MASTER_RX_EVENT to generate smbus event.
+  #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_RX_EVENT_EN_SHIFT                                                29
+  #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_RX_THRESHOLD_HIT_EN                                              (0x1<<30) // When set enables MASTER_RX_THRESHOLD_HIT to generate smbus event.
+  #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_RX_THRESHOLD_HIT_EN_SHIFT                                        30
+  #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_RX_FIFO_FULL_EN                                                  (0x1<<31) // When set enables MASTER_RX_FIFO_FULL to generate smbus event.
+  #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_RX_FIFO_FULL_EN_SHIFT                                            31
+#define MCP_REG_SMBUS_EVENT_STATUS                                                                           0xe0803cUL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_SMBUS_EVENT_STATUS_WATCHDOG_TO                                                             (0x1<<0) // This bit changes to '1' each time the WATCHDOG timer reaches zero. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
+  #define MCP_REG_SMBUS_EVENT_STATUS_WATCHDOG_TO_SHIFT                                                       0
+  #define MCP_REG_SMBUS_EVENT_STATUS_HEARTBEAT_TO                                                            (0x1<<1) // This bit changes to '1' each time the HEARTBEAT timer reaches zero. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
+  #define MCP_REG_SMBUS_EVENT_STATUS_HEARTBEAT_TO_SHIFT                                                      1
+  #define MCP_REG_SMBUS_EVENT_STATUS_POLL_ASF_TO                                                             (0x1<<2) // This bit changes to '1' each time the POLL_ASF timer reaches zero. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
+  #define MCP_REG_SMBUS_EVENT_STATUS_POLL_ASF_TO_SHIFT                                                       2
+  #define MCP_REG_SMBUS_EVENT_STATUS_POLL_LEGACY_TO                                                          (0x1<<3) // This bit changes to '1' each time the POLL_LEGACY timer reaches zero. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
+  #define MCP_REG_SMBUS_EVENT_STATUS_POLL_LEGACY_TO_SHIFT                                                    3
+  #define MCP_REG_SMBUS_EVENT_STATUS_RETRANSMIT_TO                                                           (0x1<<4) // This bit changes to '1' each time the RETRANSMIT timer reaches zero. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
+  #define MCP_REG_SMBUS_EVENT_STATUS_RETRANSMIT_TO_SHIFT                                                     4
+  #define MCP_REG_SMBUS_EVENT_STATUS_UNUSED0                                                                 (0x7fff<<5) // 
+  #define MCP_REG_SMBUS_EVENT_STATUS_UNUSED0_SHIFT                                                           5
+  #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_ARP_EVENT                                                         (0x1<<20) // This bit set when slave hardware received an ARP command and ARP_EN0 or ARP_EN1 bit is set.
+  #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_ARP_EVENT_SHIFT                                                   20
+  #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_RD_EVENT                                                          (0x1<<21) // This bit is set when slave hardware detected read transaction directed toward the SMBUS block. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
+  #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_RD_EVENT_SHIFT                                                    21
+  #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_TX_UNDERRUN                                                       (0x1<<22) // This bit is set when Slave Tx FIFO becomes empty and less then PKT_LENGTH bytes were output on the SMBUS.
+  #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_TX_UNDERRUN_SHIFT                                                 22
+  #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_START_BUSY                                                        (0x1<<23) // This bit is set when slave START_BUSY transitions from 1 to 0. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor. 0x
+  #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_START_BUSY_SHIFT                                                  23
+  #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_RX_EVENT                                                          (0x1<<24) // This bit is set when the slave receive FIFO holds at least one valid transaction. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
+  #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_RX_EVENT_SHIFT                                                    24
+  #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_RX_THRESHOLD_HIT                                                  (0x1<<25) // This bit is set when the slave receive FIFO is equal to or larger than the Slave RX_FIFO_THRESHOLD. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
+  #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_RX_THRESHOLD_HIT_SHIFT                                            25
+  #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_RX_FIFO_FULL                                                      (0x1<<26) // This bit is set when the slave receive FIFO become full. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
+  #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_RX_FIFO_FULL_SHIFT                                                26
+  #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_TX_UNDERRUN                                                      (0x1<<27) // This bit is set when Master Tx FIFO becomes empty and less then PKT_LENGTH bytes were output on the SMBUS.
+  #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_TX_UNDERRUN_SHIFT                                                27
+  #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_START_BUSY                                                       (0x1<<28) // This bit is set when master START_BUSY transitions from 1 to 0. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor. 0x
+  #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_START_BUSY_SHIFT                                                 28
+  #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_RX_EVENT                                                         (0x1<<29) // This bit is set when the master receive FIFO holds at least one valid transaction. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
+  #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_RX_EVENT_SHIFT                                                   29
+  #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_RX_THRESHOLD_HIT                                                 (0x1<<30) // This bit is set when the master receive FIFO is equal to or larger than the Master RX_FIFO_THRESHOLD. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
+  #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_RX_THRESHOLD_HIT_SHIFT                                           30
+  #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_RX_FIFO_FULL                                                     (0x1<<31) // This bit is set when the master receive FIFO become full. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
+  #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_RX_FIFO_FULL_SHIFT                                               31
+#define MCP_REG_SMBUS_MASTER_DATA_WRITE                                                                      0xe08040UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_SMBUS_MASTER_DATA_WRITE_MASTER_SMBUS_WR_DATA                                               (0xff<<0) // This is a software interface to the SMBUS Master Transmit FIFO. Software should use this register to provide data for an SMBUS write transaction. Data should be written before the SMBUS Command is programmed.
+  #define MCP_REG_SMBUS_MASTER_DATA_WRITE_MASTER_SMBUS_WR_DATA_SHIFT                                         0
+  #define MCP_REG_SMBUS_MASTER_DATA_WRITE_UNUSED0                                                            (0x7fffff<<8) // 
+  #define MCP_REG_SMBUS_MASTER_DATA_WRITE_UNUSED0_SHIFT                                                      8
+  #define MCP_REG_SMBUS_MASTER_DATA_WRITE_WR_STATUS                                                          (0x1<<31) // 0 - Byte other then last in an WMBUS transaction 1 - End of SMBUS transaction
+  #define MCP_REG_SMBUS_MASTER_DATA_WRITE_WR_STATUS_SHIFT                                                    31
+#define MCP_REG_SMBUS_MASTER_DATA_READ                                                                       0xe08044UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_SMBUS_MASTER_DATA_READ_MASTER_SMBUS_RD_DATA                                                (0xff<<0) // SMBUS Read Data in Network Byte Order (MSB first). This is a software interface to the SMBUS Master Receive FIFO. Software should use this register to read data received from the SMBUS.
+  #define MCP_REG_SMBUS_MASTER_DATA_READ_MASTER_SMBUS_RD_DATA_SHIFT                                          0
+  #define MCP_REG_SMBUS_MASTER_DATA_READ_UNUSED0                                                             (0x1fffff<<8) // 
+  #define MCP_REG_SMBUS_MASTER_DATA_READ_UNUSED0_SHIFT                                                       8
+  #define MCP_REG_SMBUS_MASTER_DATA_READ_PEC_ERR                                                             (0x1<<29) // PEC error. This bit indicates status of the PEC checking. HW will check the PEC only in case where PEC bit in SMBUS Master Command Register was set for rhe transaction This field is valid only when RD_STATUS = 2'b11.
+  #define MCP_REG_SMBUS_MASTER_DATA_READ_PEC_ERR_SHIFT                                                       29
+  #define MCP_REG_SMBUS_MASTER_DATA_READ_RD_STATUS                                                           (0x3<<30) // Enumeration:
+  #define MCP_REG_SMBUS_MASTER_DATA_READ_RD_STATUS_SHIFT                                                     30
+#define MCP_REG_SMBUS_SLAVE_DATA_WRITE                                                                       0xe08048UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_SMBUS_SLAVE_DATA_WRITE_SLAVE_SMBUS_WR_DATA                                                 (0xff<<0) // This is a software interface to the SMBUS Slave Transmit FIFO. Software should use this register to provide data for an SMBUS read transaction.
+  #define MCP_REG_SMBUS_SLAVE_DATA_WRITE_SLAVE_SMBUS_WR_DATA_SHIFT                                           0
+  #define MCP_REG_SMBUS_SLAVE_DATA_WRITE_UNUSED0                                                             (0x7fffff<<8) // 
+  #define MCP_REG_SMBUS_SLAVE_DATA_WRITE_UNUSED0_SHIFT                                                       8
+  #define MCP_REG_SMBUS_SLAVE_DATA_WRITE_WR_STATUS                                                           (0x1<<31) // Enumeration:
+  #define MCP_REG_SMBUS_SLAVE_DATA_WRITE_WR_STATUS_SHIFT                                                     31
+#define MCP_REG_SMBUS_SLAVE_DATA_READ                                                                        0xe0804cUL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_SMBUS_SLAVE_DATA_READ_SLAVE_SMBUS_RD_DATA                                                  (0xff<<0) // This is a software interface to the SMBUS Slave Receive FIFO. Software should use this register to read data received from the SMBUS.
+  #define MCP_REG_SMBUS_SLAVE_DATA_READ_SLAVE_SMBUS_RD_DATA_SHIFT                                            0
+  #define MCP_REG_SMBUS_SLAVE_DATA_READ_UNUSED0                                                              (0xfffff<<8) // 
+  #define MCP_REG_SMBUS_SLAVE_DATA_READ_UNUSED0_SHIFT                                                        8
+  #define MCP_REG_SMBUS_SLAVE_DATA_READ_ERR_STATUS                                                           (0x3<<28) // This field is valid only when RD_STATUS = 2'b11.
+  #define MCP_REG_SMBUS_SLAVE_DATA_READ_ERR_STATUS_SHIFT                                                     28
+  #define MCP_REG_SMBUS_SLAVE_DATA_READ_RD_STATUS                                                            (0x3<<30) // Enumeration:
+  #define MCP_REG_SMBUS_SLAVE_DATA_READ_RD_STATUS_SHIFT                                                      30
+#define MCP_REG_SMBUS_ARP_STATE                                                                              0xe08080UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_SMBUS_ARP_STATE_AV_FLAG0                                                                   (0x1<<0) // This bit should be set by firmware before ARP_EN0 bit is set. This bit is typically set to '1' based on the NVRAM content that is if device supports Persistent Slave Address and cleared otherwise.
+  #define MCP_REG_SMBUS_ARP_STATE_AV_FLAG0_SHIFT                                                             0
+  #define MCP_REG_SMBUS_ARP_STATE_AR_FLAG0                                                                   (0x1<<1) // This bit should be set by firmware before ARP_EN0 bit is set. This bit is typically initialized to '0'.
+  #define MCP_REG_SMBUS_ARP_STATE_AR_FLAG0_SHIFT                                                             1
+  #define MCP_REG_SMBUS_ARP_STATE_UNUSED0                                                                    (0x3<<2) // 
+  #define MCP_REG_SMBUS_ARP_STATE_UNUSED0_SHIFT                                                              2
+  #define MCP_REG_SMBUS_ARP_STATE_AV_FLAG1                                                                   (0x1<<4) // This bit should be set by firmware before ARP_EN1 bit is set. This bit is typically set to '1' based on the NVRAM content that is if device supports Persistent Slave Address and cleared otherwise.
+  #define MCP_REG_SMBUS_ARP_STATE_AV_FLAG1_SHIFT                                                             4
+  #define MCP_REG_SMBUS_ARP_STATE_AR_FLAG1                                                                   (0x1<<5) // This bit should be set by firmware before ARP_EN1 bit is set. This bit is typically initialized to '0'.
+  #define MCP_REG_SMBUS_ARP_STATE_AR_FLAG1_SHIFT                                                             5
+#define MCP_REG_SMBUS_UDID0_3                                                                                0xe08090UL //Access:RW   DataWidth:0x20   // This register should be set by firmware before ARP_EN0 bit is set.
+  #define MCP_REG_SMBUS_UDID0_3_BYTE_12                                                                      (0xff<<0) // UDID_0 byte 12.
+  #define MCP_REG_SMBUS_UDID0_3_BYTE_12_SHIFT                                                                0
+  #define MCP_REG_SMBUS_UDID0_3_BYTE_13                                                                      (0xff<<8) // UDID_0 byte 13.
+  #define MCP_REG_SMBUS_UDID0_3_BYTE_13_SHIFT                                                                8
+  #define MCP_REG_SMBUS_UDID0_3_BYTE_14                                                                      (0xff<<16) // UDID_0 byte 14.
+  #define MCP_REG_SMBUS_UDID0_3_BYTE_14_SHIFT                                                                16
+  #define MCP_REG_SMBUS_UDID0_3_BYTE_15                                                                      (0xff<<24) // UDID_0 byte 15.
+  #define MCP_REG_SMBUS_UDID0_3_BYTE_15_SHIFT                                                                24
+#define MCP_REG_SMBUS_UDID0_2                                                                                0xe08094UL //Access:RW   DataWidth:0x20   // This register should be set by firmware before ARP_EN0 bit is set.
+  #define MCP_REG_SMBUS_UDID0_2_BYTE_8                                                                       (0xff<<0) // UDID_0 byte 8.
+  #define MCP_REG_SMBUS_UDID0_2_BYTE_8_SHIFT                                                                 0
+  #define MCP_REG_SMBUS_UDID0_2_BYTE_9                                                                       (0xff<<8) // UDID_0 byte 9.
+  #define MCP_REG_SMBUS_UDID0_2_BYTE_9_SHIFT                                                                 8
+  #define MCP_REG_SMBUS_UDID0_2_BYTE_10                                                                      (0xff<<16) // UDID_0 byte 10.
+  #define MCP_REG_SMBUS_UDID0_2_BYTE_10_SHIFT                                                                16
+  #define MCP_REG_SMBUS_UDID0_2_BYTE_11                                                                      (0xff<<24) // UDID_0 byte 11.
+  #define MCP_REG_SMBUS_UDID0_2_BYTE_11_SHIFT                                                                24
+#define MCP_REG_SMBUS_UDID0_1                                                                                0xe08098UL //Access:RW   DataWidth:0x20   // This register should be set by firmware before ARP_EN0 bit is set.
+  #define MCP_REG_SMBUS_UDID0_1_BYTE_4                                                                       (0xff<<0) // UDID_0 byte 4.
+  #define MCP_REG_SMBUS_UDID0_1_BYTE_4_SHIFT                                                                 0
+  #define MCP_REG_SMBUS_UDID0_1_BYTE_5                                                                       (0xff<<8) // UDID_0 byte 5.
+  #define MCP_REG_SMBUS_UDID0_1_BYTE_5_SHIFT                                                                 8
+  #define MCP_REG_SMBUS_UDID0_1_BYTE_6                                                                       (0xff<<16) // UDID_0 byte 6.
+  #define MCP_REG_SMBUS_UDID0_1_BYTE_6_SHIFT                                                                 16
+  #define MCP_REG_SMBUS_UDID0_1_BYTE_7                                                                       (0xff<<24) // UDID_0 byte 7.
+  #define MCP_REG_SMBUS_UDID0_1_BYTE_7_SHIFT                                                                 24
+#define MCP_REG_SMBUS_UDID0_0                                                                                0xe0809cUL //Access:RW   DataWidth:0x20   // This register should be set by firmware before ARP_EN0 bit is set.
+  #define MCP_REG_SMBUS_UDID0_0_BYTE_0                                                                       (0xff<<0) // UDID_0 byte 0.
+  #define MCP_REG_SMBUS_UDID0_0_BYTE_0_SHIFT                                                                 0
+  #define MCP_REG_SMBUS_UDID0_0_BYTE_1                                                                       (0xff<<8) // UDID_0 byte 1.
+  #define MCP_REG_SMBUS_UDID0_0_BYTE_1_SHIFT                                                                 8
+  #define MCP_REG_SMBUS_UDID0_0_BYTE_2                                                                       (0xff<<16) // UDID_0 byte 2.
+  #define MCP_REG_SMBUS_UDID0_0_BYTE_2_SHIFT                                                                 16
+  #define MCP_REG_SMBUS_UDID0_0_BYTE_3                                                                       (0xff<<24) // UDID_0 byte 3.
+  #define MCP_REG_SMBUS_UDID0_0_BYTE_3_SHIFT                                                                 24
+#define MCP_REG_SMBUS_UDID1_3                                                                                0xe080a0UL //Access:RW   DataWidth:0x20   // This register should be set by firmware before ARP_EN1 bit is set.
+  #define MCP_REG_SMBUS_UDID1_3_BYTE_12                                                                      (0xff<<0) // UDID_1 byte 12.
+  #define MCP_REG_SMBUS_UDID1_3_BYTE_12_SHIFT                                                                0
+  #define MCP_REG_SMBUS_UDID1_3_BYTE_13                                                                      (0xff<<8) // UDID_1 byte 13.
+  #define MCP_REG_SMBUS_UDID1_3_BYTE_13_SHIFT                                                                8
+  #define MCP_REG_SMBUS_UDID1_3_BYTE_14                                                                      (0xff<<16) // UDID_1 byte 14.
+  #define MCP_REG_SMBUS_UDID1_3_BYTE_14_SHIFT                                                                16
+  #define MCP_REG_SMBUS_UDID1_3_BYTE_15                                                                      (0xff<<24) // UDID_1 byte 15.
+  #define MCP_REG_SMBUS_UDID1_3_BYTE_15_SHIFT                                                                24
+#define MCP_REG_SMBUS_UDID1_2                                                                                0xe080a4UL //Access:RW   DataWidth:0x20   // This register should be set by firmware before ARP_EN1 bit is set.
+  #define MCP_REG_SMBUS_UDID1_2_BYTE_8                                                                       (0xff<<0) // UDID_1 byte 8.
+  #define MCP_REG_SMBUS_UDID1_2_BYTE_8_SHIFT                                                                 0
+  #define MCP_REG_SMBUS_UDID1_2_BYTE_9                                                                       (0xff<<8) // UDID_1 byte 9.
+  #define MCP_REG_SMBUS_UDID1_2_BYTE_9_SHIFT                                                                 8
+  #define MCP_REG_SMBUS_UDID1_2_BYTE_10                                                                      (0xff<<16) // UDID_1 byte 10.
+  #define MCP_REG_SMBUS_UDID1_2_BYTE_10_SHIFT                                                                16
+  #define MCP_REG_SMBUS_UDID1_2_BYTE_11                                                                      (0xff<<24) // UDID_1 byte 11.
+  #define MCP_REG_SMBUS_UDID1_2_BYTE_11_SHIFT                                                                24
+#define MCP_REG_SMBUS_UDID1_1                                                                                0xe080a8UL //Access:RW   DataWidth:0x20   // This register should be set by firmware before ARP_EN1 bit is set.
+  #define MCP_REG_SMBUS_UDID1_1_BYTE_4                                                                       (0xff<<0) // UDID_1 byte 4.
+  #define MCP_REG_SMBUS_UDID1_1_BYTE_4_SHIFT                                                                 0
+  #define MCP_REG_SMBUS_UDID1_1_BYTE_5                                                                       (0xff<<8) // UDID_1 byte 5.
+  #define MCP_REG_SMBUS_UDID1_1_BYTE_5_SHIFT                                                                 8
+  #define MCP_REG_SMBUS_UDID1_1_BYTE_6                                                                       (0xff<<16) // UDID_1 byte 6.
+  #define MCP_REG_SMBUS_UDID1_1_BYTE_6_SHIFT                                                                 16
+  #define MCP_REG_SMBUS_UDID1_1_BYTE_7                                                                       (0xff<<24) // UDID_1 byte 7.
+  #define MCP_REG_SMBUS_UDID1_1_BYTE_7_SHIFT                                                                 24
+#define MCP_REG_SMBUS_UDID1_0                                                                                0xe080acUL //Access:RW   DataWidth:0x20   // This register should be set by firmware before ARP_EN1 bit is set.
+  #define MCP_REG_SMBUS_UDID1_0_BYTE_0                                                                       (0xff<<0) // UDID_1 byte 0.
+  #define MCP_REG_SMBUS_UDID1_0_BYTE_0_SHIFT                                                                 0
+  #define MCP_REG_SMBUS_UDID1_0_BYTE_1                                                                       (0xff<<8) // UDID_1 byte 1.
+  #define MCP_REG_SMBUS_UDID1_0_BYTE_1_SHIFT                                                                 8
+  #define MCP_REG_SMBUS_UDID1_0_BYTE_2                                                                       (0xff<<16) // UDID_1 byte 2.
+  #define MCP_REG_SMBUS_UDID1_0_BYTE_2_SHIFT                                                                 16
+  #define MCP_REG_SMBUS_UDID1_0_BYTE_3                                                                       (0xff<<24) // UDID_1 byte 3.
+  #define MCP_REG_SMBUS_UDID1_0_BYTE_3_SHIFT                                                                 24
+#define MCP_REG_SMBUS_SMB_REG_END                                                                            0xe083fcUL //Access:R    DataWidth:0x20   // 
+#define MCP_REG_TO_BMB_FIFO_COMMAND                                                                          0xe08400UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_TO_BMB_FIFO_COMMAND_FLUSH                                                                  (0x1<<0) // Setting this bit to '1' will flush the packet in the FIFO.
+  #define MCP_REG_TO_BMB_FIFO_COMMAND_FLUSH_SHIFT                                                            0
+  #define MCP_REG_TO_BMB_FIFO_COMMAND__ERROR                                                                 (0x1<<1) // Setting this bit to '1' will set the error bit for the packet.
+  #define MCP_REG_TO_BMB_FIFO_COMMAND__ERROR_SHIFT                                                           1
+  #define MCP_REG_TO_BMB_FIFO_COMMAND_UNUSED0                                                                (0x3<<2) // 
+  #define MCP_REG_TO_BMB_FIFO_COMMAND_UNUSED0_SHIFT                                                          2
+  #define MCP_REG_TO_BMB_FIFO_COMMAND_PKT_TC                                                                 (0xf<<4) // These bits indicate the read client of the packet
+  #define MCP_REG_TO_BMB_FIFO_COMMAND_PKT_TC_SHIFT                                                           4
+  #define MCP_REG_TO_BMB_FIFO_COMMAND_UNUSED1                                                                (0xff<<8) // 
+  #define MCP_REG_TO_BMB_FIFO_COMMAND_UNUSED1_SHIFT                                                          8
+  #define MCP_REG_TO_BMB_FIFO_COMMAND_PKT_LEN                                                                (0xffff<<16) // These bits indicate the length of the packet.
+  #define MCP_REG_TO_BMB_FIFO_COMMAND_PKT_LEN_SHIFT                                                          16
+#define MCP_REG_TO_BMB_FIFO_STATUS                                                                           0xe08404UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_TO_BMB_FIFO_STATUS_WRITE_DONE                                                              (0x1<<0) // This bit indicates that the write to BMB has been completed.
+  #define MCP_REG_TO_BMB_FIFO_STATUS_WRITE_DONE_SHIFT                                                        0
+#define MCP_REG_TO_BMB_FIFO_WR_DATA                                                                          0xe08408UL //Access:RW   DataWidth:0x20   // Write data
+#define MCP_REG_TO_BMB_FIFO_SOP_DSCR0                                                                        0xe08410UL //Access:RW   DataWidth:0x20   // 
+#define MCP_REG_TO_BMB_FIFO_SOP_DSCR1                                                                        0xe08414UL //Access:RW   DataWidth:0x20   // 
+#define MCP_REG_TO_BMB_FIFO_SOP_DSCR2                                                                        0xe08418UL //Access:RW   DataWidth:0x20   // 
+#define MCP_REG_TO_BMB_FIFO_SOP_DSCR3                                                                        0xe0841cUL //Access:RW   DataWidth:0x20   // 
+#define MCP_REG_FRM_BMB_FIFO_COMMAND                                                                         0xe08420UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_FRM_BMB_FIFO_COMMAND_READ_DONE                                                             (0x1<<0) // Setting this bit to '1' will indicate that FW has completed read of the packet.
+  #define MCP_REG_FRM_BMB_FIFO_COMMAND_READ_DONE_SHIFT                                                       0
+  #define MCP_REG_FRM_BMB_FIFO_COMMAND_UNUSED0                                                               (0x7<<1) // 
+  #define MCP_REG_FRM_BMB_FIFO_COMMAND_UNUSED0_SHIFT                                                         1
+  #define MCP_REG_FRM_BMB_FIFO_COMMAND_FLUSH                                                                 (0x1<<4) // Setting this bit to '1' will flush the current packet in the FIFO
+  #define MCP_REG_FRM_BMB_FIFO_COMMAND_FLUSH_SHIFT                                                           4
+  #define MCP_REG_FRM_BMB_FIFO_COMMAND_CLR_PKT_COUNTERS                                                      (0x1<<5) // Setting this bit to '1' will clear all packet available counters in the BMB read client interface
+  #define MCP_REG_FRM_BMB_FIFO_COMMAND_CLR_PKT_COUNTERS_SHIFT                                                5
+#define MCP_REG_FRM_BMB_FIFO_STATUS                                                                          0xe08424UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define MCP_REG_FRM_BMB_FIFO_STATUS_BUSY                                                                   (0x1<<0) // This bit indicates that the FIFO is busy
+  #define MCP_REG_FRM_BMB_FIFO_STATUS_BUSY_SHIFT                                                             0
+  #define MCP_REG_FRM_BMB_FIFO_STATUS_UNUSED0                                                                (0x1<<1) // 
+  #define MCP_REG_FRM_BMB_FIFO_STATUS_UNUSED0_SHIFT                                                          1
+  #define MCP_REG_FRM_BMB_FIFO_STATUS_PKT_TC0                                                                (0x3<<2) // These bits indicate the incoming traffic class of the packet. These are bits [1:0] of the PKT_TC from BMB.
+  #define MCP_REG_FRM_BMB_FIFO_STATUS_PKT_TC0_SHIFT                                                          2
+  #define MCP_REG_FRM_BMB_FIFO_STATUS_DATA_VALID                                                             (0x1<<4) // This bit indicates that the data is valid.
+  #define MCP_REG_FRM_BMB_FIFO_STATUS_DATA_VALID_SHIFT                                                       4
+  #define MCP_REG_FRM_BMB_FIFO_STATUS_SOP                                                                    (0x1<<5) // This bit indicates that the next data is the SOP of the packet.
+  #define MCP_REG_FRM_BMB_FIFO_STATUS_SOP_SHIFT                                                              5
+  #define MCP_REG_FRM_BMB_FIFO_STATUS_EOP                                                                    (0x1<<6) // This bit indicates that the next data is the EOP of the packet.
+  #define MCP_REG_FRM_BMB_FIFO_STATUS_EOP_SHIFT                                                              6
+  #define MCP_REG_FRM_BMB_FIFO_STATUS_ERR                                                                    (0x1<<7) // This bit indicates that the packet was received with an error.
+  #define MCP_REG_FRM_BMB_FIFO_STATUS_ERR_SHIFT                                                              7
+  #define MCP_REG_FRM_BMB_FIFO_STATUS_BYTE_VALID                                                             (0x3<<8) // These bits indicate the bytes that are valid in the 4byte data.
+  #define MCP_REG_FRM_BMB_FIFO_STATUS_BYTE_VALID_SHIFT                                                       8
+  #define MCP_REG_FRM_BMB_FIFO_STATUS_PKT_TC1                                                                (0x3<<10) // These bits indicate the incoming traffic class of the packet. These are bits [3:2] of the PKT_TC from BMB
+  #define MCP_REG_FRM_BMB_FIFO_STATUS_PKT_TC1_SHIFT                                                          10
+  #define MCP_REG_FRM_BMB_FIFO_STATUS_PKT_PORT                                                               (0xf<<12) // These bits indicate the write client of the packet. These are bits[3:0] of PKT_PORT from BMB
+  #define MCP_REG_FRM_BMB_FIFO_STATUS_PKT_PORT_SHIFT                                                         12
+  #define MCP_REG_FRM_BMB_FIFO_STATUS_PKT_LEN                                                                (0xffff<<16) // These bits indicate the length of the packet
+  #define MCP_REG_FRM_BMB_FIFO_STATUS_PKT_LEN_SHIFT                                                          16
+#define MCP_REG_FRM_BMB_FIFO_RD_DATA                                                                         0xe0842cUL //Access:RW   DataWidth:0x20   // 
+#define MCP_REG_FRM_BMB_FIFO_SOP_DSCR0                                                                       0xe08430UL //Access:RW   DataWidth:0x20   // 
+#define MCP_REG_FRM_BMB_FIFO_SOP_DSCR1                                                                       0xe08434UL //Access:RW   DataWidth:0x20   // 
+#define MCP_REG_FRM_BMB_FIFO_SOP_DSCR2                                                                       0xe08438UL //Access:RW   DataWidth:0x20   // 
+#define MCP_REG_FRM_BMB_FIFO_SOP_DSCR3                                                                       0xe0843cUL //Access:RW   DataWidth:0x20   // 
+#define MCP_REG_BMB_REG_END                                                                                  0xe087fcUL //Access:R    DataWidth:0x20   // 
+#define MCP_REG_ROM                                                                                          0xe10000UL //Access:R    DataWidth:0x20   // This location provides a location for the ROM contents to be read for debug pourposes.
+#define MCP_REG_ROM_SIZE                                                                                     320
+#define MCP_REG_SCRATCH                                                                                      0xe20000UL //Access:RW   DataWidth:0x20   // This is the supported processor scratch pad space that is visible at 0x0 by the processor. This can be modified at any time and may be used for processor-to-processor communication.
+#define MCP_REG_SCRATCH_SIZE                                                                                 57344
+#define XSDM_REG_ENABLE_IN1                                                                                  0xf80004UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define XSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN                                                                (0x1<<0) // Enable for input command from STORM.
+  #define XSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN_SHIFT                                                          0
+  #define XSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN                                                             (0x1<<1) // Enable for input data from internal ram interface in DMA_RSP block.
+  #define XSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN_SHIFT                                                       1
+  #define XSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN                                                             (0x1<<2) // Enable for input done from internal ram interface in DMA_RSP block.
+  #define XSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN_SHIFT                                                       2
+  #define XSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN                                                             (0x1<<3) // Enable for input full from internal ram interface in DMA_RSP block.
+  #define XSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN_SHIFT                                                       3
+  #define XSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN                                                             (0x1<<4) // Enable for input done from passive buffer interface in DMA_RSP block.
+  #define XSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN_SHIFT                                                       4
+  #define XSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN                                                             (0x1<<5) // Enable for input full from passive buffer interface in DMA_RSP block.
+  #define XSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN_SHIFT                                                       5
+  #define XSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN                                                                 (0x1<<6) // Enable for input done from pxp-HW interface in DMA_DST block.
+  #define XSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN_SHIFT                                                           6
+  #define XSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN                                                                 (0x1<<7) // Enable for input full from pxp-HW interface in DMA_DST block.
+  #define XSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN_SHIFT                                                           7
+  #define XSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN                                                                 (0x1<<8) // Enable for input data from pxp-HW interface in DMA_RSP block.
+  #define XSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN_SHIFT                                                           8
+  #define XSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN                                                              (0x1<<9) // Enable for input ack from pxp-internal write for SDM_INT block.
+  #define XSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN_SHIFT                                                        9
+  #define XSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN                                                                  (0x1<<10) // Enable for input acknowledge to credit counter from pxp_HW interface.
+  #define XSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN_SHIFT                                                            10
+  #define XSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN                                                                 (0x1<<11) // Enable for input data from BRB interface in DMA_RSP block.
+  #define XSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN_SHIFT                                                           11
+  #define XSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN                                                                  (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
+  #define XSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN_SHIFT                                                            12
+  #define XSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN                                                                  (0x1<<13) // Enable for input completion message from PRM in prm_if block.
+  #define XSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN_SHIFT                                                            13
+  #define XSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN                                                            (0x1<<14) // Enable for input ack to CCFC load credit counter.
+  #define XSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN_SHIFT                                                      14
+  #define XSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN                                                            (0x1<<15) // Enable for input ack to TCFC load credit counter.
+  #define XSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN_SHIFT                                                      15
+  #define XSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN                                                            (0x1<<16) // Enable for input response from CCFC in CCFC block.
+  #define XSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN_SHIFT                                                      16
+  #define XSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN                                                              (0x1<<17) // Enable for input ack to CCFC credit counter on the A/C interface.
+  #define XSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN_SHIFT                                                        17
+  #define XSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN                                                              (0x1<<18) // Enable for input ack to TCFC credit counter on the A/C interface.
+  #define XSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN_SHIFT                                                        18
+  #define XSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN                                                           (0x1<<19) // Enable for input full from qm in SDM_INP block.
+  #define XSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN_SHIFT                                                     19
+#define XSDM_REG_ENABLE_IN2                                                                                  0xf80008UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define XSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN                                                            (0x1<<0) // Enable for input response from TCFC in TCFC block.
+  #define XSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN_SHIFT                                                      0
+  #define XSDM_REG_ENABLE_IN2_CM_ACK_IN_EN                                                                   (0x1<<1) // Enable for input acknowledge from Cm  in SDM_CM block.
+  #define XSDM_REG_ENABLE_IN2_CM_ACK_IN_EN_SHIFT                                                             1
+  #define XSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN                                                                 (0x1<<2) // Enable for input DPM requests in SDM_DORQ block.
+  #define XSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN_SHIFT                                                           2
+#define XSDM_REG_ENABLE_OUT1                                                                                 0xf8000cUL //Access:RW   DataWidth:0x15   // Multi Field Register.
+  #define XSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN                                                                (0x1<<0) // Enable for output request to pxp internal write for SDM_INT block.
+  #define XSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN_SHIFT                                                          0
+  #define XSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN                                                             (0x1<<1) // Enable for output thread ready to the SEMI.
+  #define XSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN_SHIFT                                                       1
+  #define XSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN                                                             (0x1<<2) // Enable the output thread release to the SEMI.
+  #define XSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN_SHIFT                                                       2
+  #define XSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN                                                              (0x1<<3) // Enable for output load request to CCFC.
+  #define XSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN_SHIFT                                                        3
+  #define XSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN                                                              (0x1<<4) // Enable for output load request to TCFC.
+  #define XSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN_SHIFT                                                        4
+  #define XSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN                                                                (0x1<<5) // Enable for output increment to CCFC activity counter.
+  #define XSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN_SHIFT                                                          5
+  #define XSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN                                                                (0x1<<6) // Enable for output decrement to TCFC activity counter.
+  #define XSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN_SHIFT                                                          6
+  #define XSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN                                                                (0x1<<7) // Enable for output data to pxp-HW interface in DMA_REQ block.
+  #define XSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN_SHIFT                                                          7
+  #define XSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN                                                                (0x1<<8) // Enable for output request to BRB interface in DMA_REQ block.
+  #define XSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN_SHIFT                                                          8
+  #define XSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN                                                                (0x1<<9) // Enable for output write to int_ram in DMA_DST block.
+  #define XSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN_SHIFT                                                          9
+  #define XSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN                                                                (0x1<<10) // Enable for output write topassive buffer in DMA_DST block.
+  #define XSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN_SHIFT                                                          10
+  #define XSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN                                                              (0x1<<11) // Enable for output write to pxp async in DMA_DST block.
+  #define XSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN_SHIFT                                                        11
+  #define XSDM_REG_ENABLE_OUT1_PXP_OUT_EN                                                                    (0x1<<12) // Enable for output write to pxp  in DMA_DST block.
+  #define XSDM_REG_ENABLE_OUT1_PXP_OUT_EN_SHIFT                                                              12
+  #define XSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN                                                               (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
+  #define XSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN_SHIFT                                                         13
+  #define XSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN                                                               (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
+  #define XSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN_SHIFT                                                         14
+  #define XSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN                                                               (0x1<<15) // Enable for output external full to SEMI block.
+  #define XSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN_SHIFT                                                         15
+  #define XSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN                                                           (0x1<<16) // Enable for output done to async PXP host IF.
+  #define XSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN_SHIFT                                                     16
+  #define XSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN                                                           (0x1<<17) // Enable the output done (ack) to PRM.
+  #define XSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN_SHIFT                                                     17
+  #define XSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN                                                                 (0x1<<18) // Enable for output message to CM in SDM_CM block.
+  #define XSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN_SHIFT                                                           18
+  #define XSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN                                                           (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
+  #define XSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN_SHIFT                                                     19
+  #define XSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN                                                           (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
+  #define XSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN_SHIFT                                                     20
+#define XSDM_REG_ENABLE_OUT2                                                                                 0xf80010UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define XSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN                                                              (0x1<<0) // Enable for output command to qm in SDM_INP block.
+  #define XSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN_SHIFT                                                        0
+  #define XSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN                                                               (0x1<<1) // Enable for VF/PF error valid in DMA_DST block.
+  #define XSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN_SHIFT                                                         1
+  #define XSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN                                                          (0x1<<2) // Enable for DPM request done output in SDM_DORQ block.
+  #define XSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN_SHIFT                                                    2
+#define XSDM_REG_DISABLE_ENGINE                                                                              0xf80014UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define XSDM_REG_DISABLE_ENGINE_DISABLE_DMA                                                                (0x1<<0) // This bit should be set to disable the DMA exectuion engine from processing DMA commands.
+  #define XSDM_REG_DISABLE_ENGINE_DISABLE_DMA_SHIFT                                                          0
+  #define XSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS                                                             (0x1<<1) // This bit should be set to disable the timers' exectuion engine from processing timers' commands.
+  #define XSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS_SHIFT                                                       1
+  #define XSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD                                                          (0x1<<2) // This bit should be set to disable the CCFC exectuion engine from processing CCFC load commands.
+  #define XSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD_SHIFT                                                    2
+  #define XSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD                                                          (0x1<<3) // This bit should be set to disable the TCFC exectuion engine from processing TCFC load commands.
+  #define XSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD_SHIFT                                                    3
+  #define XSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR                                                             (0x1<<4) // This bit should be set to disable the internal write exectuion engine from processing Internal write commands.
+  #define XSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR_SHIFT                                                       4
+  #define XSDM_REG_DISABLE_ENGINE_DISABLE_NOP                                                                (0x1<<5) // This bit should be set to disable the SDM NOP exectuion engine from processing NOP commands.
+  #define XSDM_REG_DISABLE_ENGINE_DISABLE_NOP_SHIFT                                                          5
+  #define XSDM_REG_DISABLE_ENGINE_DISABLE_GRC                                                                (0x1<<6) // This bit should be set to disable the GRC master exectuion engine from processing GRC master commands.
+  #define XSDM_REG_DISABLE_ENGINE_DISABLE_GRC_SHIFT                                                          6
+  #define XSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC                                                              (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Async requests.
+  #define XSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC_SHIFT                                                        7
+  #define XSDM_REG_DISABLE_ENGINE_DISABLE_PRM                                                                (0x1<<8) // This bit should be set to disable the PRM interface from processing PRM completion commands.
+  #define XSDM_REG_DISABLE_ENGINE_DISABLE_PRM_SHIFT                                                          8
+  #define XSDM_REG_DISABLE_ENGINE_DISABLE_DORQ                                                               (0x1<<9) // This bit should be set to disable the DORQ DPM interface from processing DPM commands.
+  #define XSDM_REG_DISABLE_ENGINE_DISABLE_DORQ_SHIFT                                                         9
+#define XSDM_REG_INT_STS                                                                                     0xf80040UL //Access:R    DataWidth:0x1c   // Multi Field Register.
+  #define XSDM_REG_INT_STS_ADDRESS_ERROR                                                                     (0x1<<0) // Signals an unknown address to the rf module.
+  #define XSDM_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                               0
+  #define XSDM_REG_INT_STS_INP_QUEUE_ERROR                                                                   (0x1<<1) // Indicates that one of the input queues had a FIFO error.
+  #define XSDM_REG_INT_STS_INP_QUEUE_ERROR_SHIFT                                                             1
+  #define XSDM_REG_INT_STS_DELAY_FIFO_ERROR                                                                  (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
+  #define XSDM_REG_INT_STS_DELAY_FIFO_ERROR_SHIFT                                                            2
+  #define XSDM_REG_INT_STS_ASYNC_HOST_ERROR                                                                  (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
+  #define XSDM_REG_INT_STS_ASYNC_HOST_ERROR_SHIFT                                                            3
+  #define XSDM_REG_INT_STS_PRM_FIFO_ERROR                                                                    (0x1<<4) // FIFO in PRM interface sub-module reported an error.
+  #define XSDM_REG_INT_STS_PRM_FIFO_ERROR_SHIFT                                                              4
+  #define XSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR                                                              (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
+  #define XSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR_SHIFT                                                        5
+  #define XSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR                                                              (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
+  #define XSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR_SHIFT                                                        6
+  #define XSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR                                                            (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
+  #define XSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR_SHIFT                                                      7
+  #define XSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR                                                            (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
+  #define XSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR_SHIFT                                                      8
+  #define XSDM_REG_INT_STS_DST_PXP_IMMED_ERROR                                                               (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
+  #define XSDM_REG_INT_STS_DST_PXP_IMMED_ERROR_SHIFT                                                         9
+  #define XSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR                                                            (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
+  #define XSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR_SHIFT                                                      10
+  #define XSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR                                                            (0x1<<11) // BRB src pend fifo error in DMA_DST block.
+  #define XSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR_SHIFT                                                      11
+  #define XSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR                                                            (0x1<<12) // BRB src addr fifo error in DMA_DST block.
+  #define XSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR_SHIFT                                                      12
+  #define XSDM_REG_INT_STS_RSP_BRB_PEND_ERROR                                                                (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
+  #define XSDM_REG_INT_STS_RSP_BRB_PEND_ERROR_SHIFT                                                          13
+  #define XSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR                                                            (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
+  #define XSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR_SHIFT                                                      14
+  #define XSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR                                                             (0x1<<15) // Read data firo in DMA_RSP block for BRB.
+  #define XSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR_SHIFT                                                       15
+  #define XSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR                                                         (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
+  #define XSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                                   16
+  #define XSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR                                                             (0x1<<17) // PXP read data fifo error in DMA_RSP block.
+  #define XSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR_SHIFT                                                       17
+  #define XSDM_REG_INT_STS_CM_DELAY_ERROR                                                                    (0x1<<18) // Delay CM fifo error in CM block.
+  #define XSDM_REG_INT_STS_CM_DELAY_ERROR_SHIFT                                                              18
+  #define XSDM_REG_INT_STS_SH_DELAY_ERROR                                                                    (0x1<<19) // Delay shared fifo error in CM block.
+  #define XSDM_REG_INT_STS_SH_DELAY_ERROR_SHIFT                                                              19
+  #define XSDM_REG_INT_STS_CMPL_PEND_ERROR                                                                   (0x1<<20) // Error in completion pending FIFO in internal write block.
+  #define XSDM_REG_INT_STS_CMPL_PEND_ERROR_SHIFT                                                             20
+  #define XSDM_REG_INT_STS_CPRM_PEND_ERROR                                                                   (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
+  #define XSDM_REG_INT_STS_CPRM_PEND_ERROR_SHIFT                                                             21
+  #define XSDM_REG_INT_STS_TIMER_ADDR_ERROR                                                                  (0x1<<22) // Address fifo error in timer block.
+  #define XSDM_REG_INT_STS_TIMER_ADDR_ERROR_SHIFT                                                            22
+  #define XSDM_REG_INT_STS_TIMER_PEND_ERROR                                                                  (0x1<<23) // Pending fifo error in timer block.
+  #define XSDM_REG_INT_STS_TIMER_PEND_ERROR_SHIFT                                                            23
+  #define XSDM_REG_INT_STS_DORQ_DPM_ERROR                                                                    (0x1<<24) // Dpm fifo error in dorq I/F block.
+  #define XSDM_REG_INT_STS_DORQ_DPM_ERROR_SHIFT                                                              24
+  #define XSDM_REG_INT_STS_DST_PXP_DONE_ERROR                                                                (0x1<<25) // PXP done fifo error in DMA_dst block.
+  #define XSDM_REG_INT_STS_DST_PXP_DONE_ERROR_SHIFT                                                          25
+  #define XSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR_K2_E5                                                        (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define XSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                                  26
+  #define XSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_K2_E5                                                        (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define XSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                                  27
+#define XSDM_REG_INT_MASK                                                                                    0xf80044UL //Access:RW   DataWidth:0x1c   // Multi Field Register.
+  #define XSDM_REG_INT_MASK_ADDRESS_ERROR                                                                    (0x1<<0) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.ADDRESS_ERROR .
+  #define XSDM_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                              0
+  #define XSDM_REG_INT_MASK_INP_QUEUE_ERROR                                                                  (0x1<<1) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.INP_QUEUE_ERROR .
+  #define XSDM_REG_INT_MASK_INP_QUEUE_ERROR_SHIFT                                                            1
+  #define XSDM_REG_INT_MASK_DELAY_FIFO_ERROR                                                                 (0x1<<2) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DELAY_FIFO_ERROR .
+  #define XSDM_REG_INT_MASK_DELAY_FIFO_ERROR_SHIFT                                                           2
+  #define XSDM_REG_INT_MASK_ASYNC_HOST_ERROR                                                                 (0x1<<3) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.ASYNC_HOST_ERROR .
+  #define XSDM_REG_INT_MASK_ASYNC_HOST_ERROR_SHIFT                                                           3
+  #define XSDM_REG_INT_MASK_PRM_FIFO_ERROR                                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.PRM_FIFO_ERROR .
+  #define XSDM_REG_INT_MASK_PRM_FIFO_ERROR_SHIFT                                                             4
+  #define XSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR                                                             (0x1<<5) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.CCFC_LOAD_PEND_ERROR .
+  #define XSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR_SHIFT                                                       5
+  #define XSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR                                                             (0x1<<6) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.TCFC_LOAD_PEND_ERROR .
+  #define XSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR_SHIFT                                                       6
+  #define XSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR                                                           (0x1<<7) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DST_INT_RAM_WAIT_ERROR .
+  #define XSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR_SHIFT                                                     7
+  #define XSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR                                                           (0x1<<8) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DST_PAS_BUF_WAIT_ERROR .
+  #define XSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR_SHIFT                                                     8
+  #define XSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR                                                              (0x1<<9) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DST_PXP_IMMED_ERROR .
+  #define XSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR_SHIFT                                                        9
+  #define XSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR                                                           (0x1<<10) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DST_PXP_DST_PEND_ERROR .
+  #define XSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR_SHIFT                                                     10
+  #define XSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR                                                           (0x1<<11) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DST_BRB_SRC_PEND_ERROR .
+  #define XSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR_SHIFT                                                     11
+  #define XSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR                                                           (0x1<<12) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DST_BRB_SRC_ADDR_ERROR .
+  #define XSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR_SHIFT                                                     12
+  #define XSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR                                                               (0x1<<13) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.RSP_BRB_PEND_ERROR .
+  #define XSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR_SHIFT                                                         13
+  #define XSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR                                                           (0x1<<14) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.RSP_INT_RAM_PEND_ERROR .
+  #define XSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR_SHIFT                                                     14
+  #define XSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR                                                            (0x1<<15) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.RSP_BRB_RD_DATA_ERROR .
+  #define XSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR_SHIFT                                                      15
+  #define XSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR                                                        (0x1<<16) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.RSP_INT_RAM_RD_DATA_ERROR .
+  #define XSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                                  16
+  #define XSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR                                                            (0x1<<17) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.RSP_PXP_RD_DATA_ERROR .
+  #define XSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR_SHIFT                                                      17
+  #define XSDM_REG_INT_MASK_CM_DELAY_ERROR                                                                   (0x1<<18) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.CM_DELAY_ERROR .
+  #define XSDM_REG_INT_MASK_CM_DELAY_ERROR_SHIFT                                                             18
+  #define XSDM_REG_INT_MASK_SH_DELAY_ERROR                                                                   (0x1<<19) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.SH_DELAY_ERROR .
+  #define XSDM_REG_INT_MASK_SH_DELAY_ERROR_SHIFT                                                             19
+  #define XSDM_REG_INT_MASK_CMPL_PEND_ERROR                                                                  (0x1<<20) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.CMPL_PEND_ERROR .
+  #define XSDM_REG_INT_MASK_CMPL_PEND_ERROR_SHIFT                                                            20
+  #define XSDM_REG_INT_MASK_CPRM_PEND_ERROR                                                                  (0x1<<21) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.CPRM_PEND_ERROR .
+  #define XSDM_REG_INT_MASK_CPRM_PEND_ERROR_SHIFT                                                            21
+  #define XSDM_REG_INT_MASK_TIMER_ADDR_ERROR                                                                 (0x1<<22) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.TIMER_ADDR_ERROR .
+  #define XSDM_REG_INT_MASK_TIMER_ADDR_ERROR_SHIFT                                                           22
+  #define XSDM_REG_INT_MASK_TIMER_PEND_ERROR                                                                 (0x1<<23) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.TIMER_PEND_ERROR .
+  #define XSDM_REG_INT_MASK_TIMER_PEND_ERROR_SHIFT                                                           23
+  #define XSDM_REG_INT_MASK_DORQ_DPM_ERROR                                                                   (0x1<<24) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DORQ_DPM_ERROR .
+  #define XSDM_REG_INT_MASK_DORQ_DPM_ERROR_SHIFT                                                             24
+  #define XSDM_REG_INT_MASK_DST_PXP_DONE_ERROR                                                               (0x1<<25) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DST_PXP_DONE_ERROR .
+  #define XSDM_REG_INT_MASK_DST_PXP_DONE_ERROR_SHIFT                                                         25
+  #define XSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR_K2_E5                                                       (0x1<<26) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.XCM_RMT_BUFFER_ERROR .
+  #define XSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                                 26
+  #define XSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_K2_E5                                                       (0x1<<27) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.YCM_RMT_BUFFER_ERROR .
+  #define XSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                                 27
+#define XSDM_REG_INT_STS_WR                                                                                  0xf80048UL //Access:WR   DataWidth:0x1c   // Multi Field Register.
+  #define XSDM_REG_INT_STS_WR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define XSDM_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                            0
+  #define XSDM_REG_INT_STS_WR_INP_QUEUE_ERROR                                                                (0x1<<1) // Indicates that one of the input queues had a FIFO error.
+  #define XSDM_REG_INT_STS_WR_INP_QUEUE_ERROR_SHIFT                                                          1
+  #define XSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR                                                               (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
+  #define XSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR_SHIFT                                                         2
+  #define XSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR                                                               (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
+  #define XSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR_SHIFT                                                         3
+  #define XSDM_REG_INT_STS_WR_PRM_FIFO_ERROR                                                                 (0x1<<4) // FIFO in PRM interface sub-module reported an error.
+  #define XSDM_REG_INT_STS_WR_PRM_FIFO_ERROR_SHIFT                                                           4
+  #define XSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR                                                           (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
+  #define XSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR_SHIFT                                                     5
+  #define XSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR                                                           (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
+  #define XSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR_SHIFT                                                     6
+  #define XSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR                                                         (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
+  #define XSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR_SHIFT                                                   7
+  #define XSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR                                                         (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
+  #define XSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR_SHIFT                                                   8
+  #define XSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR                                                            (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
+  #define XSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR_SHIFT                                                      9
+  #define XSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR                                                         (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
+  #define XSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR_SHIFT                                                   10
+  #define XSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR                                                         (0x1<<11) // BRB src pend fifo error in DMA_DST block.
+  #define XSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR_SHIFT                                                   11
+  #define XSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR                                                         (0x1<<12) // BRB src addr fifo error in DMA_DST block.
+  #define XSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR_SHIFT                                                   12
+  #define XSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR                                                             (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
+  #define XSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR_SHIFT                                                       13
+  #define XSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR                                                         (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
+  #define XSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR_SHIFT                                                   14
+  #define XSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR                                                          (0x1<<15) // Read data firo in DMA_RSP block for BRB.
+  #define XSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR_SHIFT                                                    15
+  #define XSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR                                                      (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
+  #define XSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                                16
+  #define XSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR                                                          (0x1<<17) // PXP read data fifo error in DMA_RSP block.
+  #define XSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR_SHIFT                                                    17
+  #define XSDM_REG_INT_STS_WR_CM_DELAY_ERROR                                                                 (0x1<<18) // Delay CM fifo error in CM block.
+  #define XSDM_REG_INT_STS_WR_CM_DELAY_ERROR_SHIFT                                                           18
+  #define XSDM_REG_INT_STS_WR_SH_DELAY_ERROR                                                                 (0x1<<19) // Delay shared fifo error in CM block.
+  #define XSDM_REG_INT_STS_WR_SH_DELAY_ERROR_SHIFT                                                           19
+  #define XSDM_REG_INT_STS_WR_CMPL_PEND_ERROR                                                                (0x1<<20) // Error in completion pending FIFO in internal write block.
+  #define XSDM_REG_INT_STS_WR_CMPL_PEND_ERROR_SHIFT                                                          20
+  #define XSDM_REG_INT_STS_WR_CPRM_PEND_ERROR                                                                (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
+  #define XSDM_REG_INT_STS_WR_CPRM_PEND_ERROR_SHIFT                                                          21
+  #define XSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR                                                               (0x1<<22) // Address fifo error in timer block.
+  #define XSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR_SHIFT                                                         22
+  #define XSDM_REG_INT_STS_WR_TIMER_PEND_ERROR                                                               (0x1<<23) // Pending fifo error in timer block.
+  #define XSDM_REG_INT_STS_WR_TIMER_PEND_ERROR_SHIFT                                                         23
+  #define XSDM_REG_INT_STS_WR_DORQ_DPM_ERROR                                                                 (0x1<<24) // Dpm fifo error in dorq I/F block.
+  #define XSDM_REG_INT_STS_WR_DORQ_DPM_ERROR_SHIFT                                                           24
+  #define XSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR                                                             (0x1<<25) // PXP done fifo error in DMA_dst block.
+  #define XSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR_SHIFT                                                       25
+  #define XSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR_K2_E5                                                     (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define XSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                               26
+  #define XSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_K2_E5                                                     (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define XSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                               27
+#define XSDM_REG_INT_STS_CLR                                                                                 0xf8004cUL //Access:RC   DataWidth:0x1c   // Multi Field Register.
+  #define XSDM_REG_INT_STS_CLR_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define XSDM_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                           0
+  #define XSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR                                                               (0x1<<1) // Indicates that one of the input queues had a FIFO error.
+  #define XSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR_SHIFT                                                         1
+  #define XSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR                                                              (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
+  #define XSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR_SHIFT                                                        2
+  #define XSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR                                                              (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
+  #define XSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR_SHIFT                                                        3
+  #define XSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR                                                                (0x1<<4) // FIFO in PRM interface sub-module reported an error.
+  #define XSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR_SHIFT                                                          4
+  #define XSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR                                                          (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
+  #define XSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR_SHIFT                                                    5
+  #define XSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR                                                          (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
+  #define XSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR_SHIFT                                                    6
+  #define XSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR                                                        (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
+  #define XSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR_SHIFT                                                  7
+  #define XSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR                                                        (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
+  #define XSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR_SHIFT                                                  8
+  #define XSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR                                                           (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
+  #define XSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR_SHIFT                                                     9
+  #define XSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR                                                        (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
+  #define XSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR_SHIFT                                                  10
+  #define XSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR                                                        (0x1<<11) // BRB src pend fifo error in DMA_DST block.
+  #define XSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR_SHIFT                                                  11
+  #define XSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR                                                        (0x1<<12) // BRB src addr fifo error in DMA_DST block.
+  #define XSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR_SHIFT                                                  12
+  #define XSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR                                                            (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
+  #define XSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR_SHIFT                                                      13
+  #define XSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR                                                        (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
+  #define XSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR_SHIFT                                                  14
+  #define XSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR                                                         (0x1<<15) // Read data firo in DMA_RSP block for BRB.
+  #define XSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR_SHIFT                                                   15
+  #define XSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR                                                     (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
+  #define XSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                               16
+  #define XSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR                                                         (0x1<<17) // PXP read data fifo error in DMA_RSP block.
+  #define XSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR_SHIFT                                                   17
+  #define XSDM_REG_INT_STS_CLR_CM_DELAY_ERROR                                                                (0x1<<18) // Delay CM fifo error in CM block.
+  #define XSDM_REG_INT_STS_CLR_CM_DELAY_ERROR_SHIFT                                                          18
+  #define XSDM_REG_INT_STS_CLR_SH_DELAY_ERROR                                                                (0x1<<19) // Delay shared fifo error in CM block.
+  #define XSDM_REG_INT_STS_CLR_SH_DELAY_ERROR_SHIFT                                                          19
+  #define XSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR                                                               (0x1<<20) // Error in completion pending FIFO in internal write block.
+  #define XSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR_SHIFT                                                         20
+  #define XSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR                                                               (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
+  #define XSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR_SHIFT                                                         21
+  #define XSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR                                                              (0x1<<22) // Address fifo error in timer block.
+  #define XSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR_SHIFT                                                        22
+  #define XSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR                                                              (0x1<<23) // Pending fifo error in timer block.
+  #define XSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR_SHIFT                                                        23
+  #define XSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR                                                                (0x1<<24) // Dpm fifo error in dorq I/F block.
+  #define XSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR_SHIFT                                                          24
+  #define XSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR                                                            (0x1<<25) // PXP done fifo error in DMA_dst block.
+  #define XSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR_SHIFT                                                      25
+  #define XSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR_K2_E5                                                    (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define XSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                              26
+  #define XSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_K2_E5                                                    (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define XSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                              27
+#define XSDM_REG_PRTY_MASK_H_0_BB_K2                                                                         0xf80204UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define XSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2                                                     (0x1<<0) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define XSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2_SHIFT                                               0
+  #define XSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2                                                     (0x1<<1) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define XSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2_SHIFT                                               1
+  #define XSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2                                                     (0x1<<2) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define XSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2_SHIFT                                               2
+  #define XSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2                                                     (0x1<<3) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define XSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2_SHIFT                                               3
+  #define XSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                     (0x1<<4) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define XSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                               4
+  #define XSDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2                                                     (0x1<<5) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
+  #define XSDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2_SHIFT                                               5
+  #define XSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                     (0x1<<6) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define XSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                               6
+  #define XSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                     (0x1<<7) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define XSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                               7
+  #define XSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2                                                     (0x1<<8) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define XSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT                                               8
+  #define XSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                     (0x1<<9) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define XSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                               9
+#define XSDM_REG_MEM_ECC_EVENTS_BB_K2                                                                        0xf80210UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define XSDM_REG_TIMER_TICK                                                                                  0xf80400UL //Access:RW   DataWidth:0x20   // Defines the number of system clock cycles that are used to define a timers clock tick cycle. Note: The minimal legal value for this register is 25, lower values can cause timers functionality issues.
+#define XSDM_REG_TIMERS_TICK_ENABLE                                                                          0xf80404UL //Access:RW   DataWidth:0x1    // Enable for tick counter.
+#define XSDM_REG_OPERATION_GEN                                                                               0xf80408UL //Access:W    DataWidth:0x14   // This register is used to assert a completion operation of choice; It includes the following completion fields: bits 19:16 are Trig; bits 15:0 are CompParams. Note that trigger types 3,5 or 8 are not supported by this interface as they require a completion message. If there is an attempt to assert an OperationGen with Trig = 3,5 or 8, the operation will be voided.
+#define XSDM_REG_GRC_PRIVILEGE_LEVEL                                                                         0xf8040cUL //Access:RW   DataWidth:0x2    // This register defines the PRV (privilege level) field within the FID structure of the SDM GRC master request.
+#define XSDM_REG_CM_MSG_CNT_ADDRESS                                                                          0xf80410UL //Access:RW   DataWidth:0xf    // The internal RAM address for storing the shadow of the CM completion message counter.
+#define XSDM_REG_DORQ_DPM_START_ADDR                                                                         0xf80414UL //Access:RW   DataWidth:0xf    // The start address in the internal RAM for DORQ DPM messages.
+#define XSDM_REG_RR_COMPLETE_REQ                                                                             0xf80418UL //Access:R    DataWidth:0xa    // Provides read access to the round robin arbiter used for all completion write requests  in the completion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b7-PRM interface; b8-CCFC load; b9-TCFC load.
+#define XSDM_REG_RR_PTR_REQ                                                                                  0xf8041cUL //Access:R    DataWidth:0x9    // Provides read access to the round robin arbiter for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-int_wr; b7-prm; b8-grc_master.
+#define XSDM_REG_INT_RAM_RR_REQ                                                                              0xf80420UL //Access:R    DataWidth:0x4    // Provides read access to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination;b2-PXP source/destination;b3-BRB source.
+#define XSDM_REG_INP_QUEUE_ERR_VECT                                                                          0xf80424UL //Access:R    DataWidth:0x9    // This register is intended to be read in the event of an inp_queue_error interrupt.  It contains a vector with a bit per input queue. Clearing the interrupt causes this vector to be cleared. Errors on multiple FIFOs will be aggregated between interrupt clear requests.
+#define XSDM_REG_ASYNC_CMSG_ALLOC_LIMIT                                                                      0xf80428UL //Access:RW   DataWidth:0x5    // This register defines the maximum number of completion messages that can be allocated to PXP-Async transactions at any given time. If the PXP-Async interface attempts to reserve beyond this limit, it will be held off until the situation is resolved.
+#define XSDM_REG_ECO_RESERVED                                                                                0xf8042cUL //Access:RW   DataWidth:0x8    // Reserved bits for ECO.
+#define XSDM_REG_INIT_CREDIT_PXP                                                                             0xf80500UL //Access:RW   DataWidth:0x3    // The initial number of messages that can be sent to the pxp interface without receiving any ACK.
+#define XSDM_REG_INIT_CREDIT_PCI                                                                             0xf80504UL //Access:RW   DataWidth:0x2    // The initial number of messages that can be sent to the PCI-Switch on the internal write interface without receiving any ACK.
+#define XSDM_REG_INIT_CREDIT_TCFC_AC                                                                         0xf80508UL //Access:RW   DataWidth:0x4    // The initial number of messages that can be sent to the TCFC activity counters interface without receiving any ACK.
+#define XSDM_REG_INIT_CREDIT_CCFC_AC                                                                         0xf8050cUL //Access:RW   DataWidth:0x4    // The initial number of messages that can be sent to the CCFC activity counters interface without receiving any ACK.
+#define XSDM_REG_INIT_CREDIT_CM                                                                              0xf80510UL //Access:RW   DataWidth:0x4    // The initial number of cycles that can be sent to the CM interface without receiving any ACK in CM block.
+#define XSDM_REG_INIT_CREDIT_CM_RMT                                                                          0xf80520UL //Access:RW   DataWidth:0x4    // The initial number of cycles that can be sent to a remote CM interface without receiving any ACK in CM block.
+#define XSDM_REG_NUM_OF_DMA_CMD                                                                              0xf80600UL //Access:RC   DataWidth:0x20   // The number of SDM DMA commands executed.
+#define XSDM_REG_NUM_OF_TIMERS_CMD                                                                           0xf80604UL //Access:RC   DataWidth:0x20   // The number of SDM timers commands executed.
+#define XSDM_REG_NUM_OF_CCFC_LD_CMD                                                                          0xf80608UL //Access:RC   DataWidth:0x20   // The number of SDM CCFC load commands executed.
+#define XSDM_REG_NUM_OF_CCFC_AC_CMD                                                                          0xf8060cUL //Access:RC   DataWidth:0x20   // The number of SDM CCFC activity counter commands executed.
+#define XSDM_REG_NUM_OF_TCFC_LD_CMD                                                                          0xf80610UL //Access:RC   DataWidth:0x20   // The number of SDM TCFC load commands executed.
+#define XSDM_REG_NUM_OF_TCFC_AC_CMD                                                                          0xf80614UL //Access:RC   DataWidth:0x20   // The number of SDM TCFC activity counter commands executed.
+#define XSDM_REG_NUM_OF_INT_CMD                                                                              0xf80618UL //Access:RC   DataWidth:0x20   // The number of SDM internal write commands executed.
+#define XSDM_REG_NUM_OF_NOP_CMD                                                                              0xf8061cUL //Access:RC   DataWidth:0x20   // The number of SDM NOP commands executed.
+#define XSDM_REG_NUM_OF_GRC_CMD                                                                              0xf80620UL //Access:RC   DataWidth:0x20   // The number of GRC master commands executed.
+#define XSDM_REG_NUM_OF_PRM_REQ                                                                              0xf80624UL //Access:RC   DataWidth:0x20   // The number of packet end messages received on the PRM completion interface.
+#define XSDM_REG_NUM_OF_PXP_ASYNC_REQ                                                                        0xf80628UL //Access:RC   DataWidth:0x20   // The number of requests received from the pxp async if.
+#define XSDM_REG_NUM_OF_DPM_REQ                                                                              0xf8062cUL //Access:RC   DataWidth:0x20   // The number of DORQ DPM messages received.
+#define XSDM_REG_BRB_ALMOST_FULL                                                                             0xf80700UL //Access:RW   DataWidth:0x5    // Almost full signal for read data from BRB in DMA_RSP block.
+#define XSDM_REG_PXP_ALMOST_FULL                                                                             0xf80704UL //Access:RW   DataWidth:0x4    // Almost full signal for read data from pxp in DMA_RSP block.
+#define XSDM_REG_DORQ_ALMOST_FULL                                                                            0xf80708UL //Access:RW   DataWidth:0x6    // Almost full signal for read data from DORQ in SDM_DORQ block.
+#define XSDM_REG_AGG_INT_CTRL                                                                                0xf80800UL //Access:RW   DataWidth:0xa    // This array of registers provides controls for each of the aggregated interrupts; The fields are defined as follows: [20:16] Affinity [15:12] NumL2m. [11]    Exclusive. [10]    Core-selection where 0=Core_A and 1=Core_B. [9]     Mode bit where 0=normal and 1=auto-mask-mode. [8]     T-flag which determines if a thread is allocated for this handler in the Storm. [7:0]   EventID which selects the event ID of the associated handler.
+#define XSDM_REG_AGG_INT_CTRL_SIZE                                                                           32
+#define XSDM_REG_AGG_INT_STATE                                                                               0xf80a00UL //Access:R    DataWidth:0x2    // This array of registers provides access to each of the 32 aggregated interrupt request state machines; The values read from this register mean the following; 00 = IDLE; 01 = PEND; 10 = MASK; 11 = PANDM.
+#define XSDM_REG_AGG_INT_STATE_SIZE                                                                          32
+#define XSDM_REG_QUEUE_FULL                                                                                  0xf80c00UL //Access:R    DataWidth:0x9    // Input queue fifo full in sdm_inp block.
+#define XSDM_REG_INT_CMPL_PEND_FULL                                                                          0xf80c04UL //Access:R    DataWidth:0x1    // Internal write completion pending full in internal write block.
+#define XSDM_REG_INT_CPRM_PEND_FULL                                                                          0xf80c08UL //Access:R    DataWidth:0x1    // Internal write completion parameter pending full in internal write block.
+#define XSDM_REG_QM_FULL                                                                                     0xf80c0cUL //Access:R    DataWidth:0x1    // QM IF  full in sdm_inp block.
+#define XSDM_REG_DELAY_FIFO_FULL                                                                             0xf80c10UL //Access:R    DataWidth:0x1    // Delay FIFO  full in sdm_inp block.
+#define XSDM_REG_TIMERS_PEND_FULL                                                                            0xf80c14UL //Access:R    DataWidth:0x1    // Pending FIFO  full in sdm_timers block.
+#define XSDM_REG_TIMERS_ADDR_FULL                                                                            0xf80c18UL //Access:R    DataWidth:0x1    // Address FIFO  full in sdm_timers block.
+#define XSDM_REG_RSP_PXP_RDATA_FULL                                                                          0xf80c1cUL //Access:R    DataWidth:0x1    // PXP rd_data fifo  full in sdm_dma_rsp block.
+#define XSDM_REG_RSP_BRB_RDATA_FULL                                                                          0xf80c20UL //Access:R    DataWidth:0x1    // BRB read data fifo  full in sdm_dma_rsp block.
+#define XSDM_REG_RSP_INT_RAM_RDATA_FULL                                                                      0xf80c24UL //Access:R    DataWidth:0x1    // Int_ram rd_data fifo  full in sdm_dma_rsp block.
+#define XSDM_REG_RSP_BRB_PEND_FULL                                                                           0xf80c28UL //Access:R    DataWidth:0x1    // BRB pending fifo  full in sdm_dma_rsp block.
+#define XSDM_REG_RSP_INT_RAM_PEND_FULL                                                                       0xf80c2cUL //Access:R    DataWidth:0x1    // Int_ram pending fifo  full in sdm_dma_rsp block.
+#define XSDM_REG_RSP_BRB_IF_FULL                                                                             0xf80c30UL //Access:R    DataWidth:0x1    // BRB interface is  full in sdm_dma_rsp block.
+#define XSDM_REG_RSP_PXP_IF_FULL                                                                             0xf80c34UL //Access:R    DataWidth:0x1    // PXP interface is  full in sdm_dma_rsp block.
+#define XSDM_REG_DST_PXP_IMMED_FULL                                                                          0xf80c38UL //Access:R    DataWidth:0x1    // PXP immediate fifo full in sdm_dma_dst block.
+#define XSDM_REG_DST_PXP_DST_PEND_FULL                                                                       0xf80c3cUL //Access:R    DataWidth:0x1    // PXP destination pending fifo full in sdm_dma_dst block.
+#define XSDM_REG_DST_PXP_SRC_PEND_FULL                                                                       0xf80c40UL //Access:R    DataWidth:0x1    // PXP source pending fifo full in sdm_dma_dst block.
+#define XSDM_REG_DST_BRB_SRC_PEND_FULL                                                                       0xf80c44UL //Access:R    DataWidth:0x1    // BRB source pending fifo full in sdm_dma_dst block.
+#define XSDM_REG_DST_BRB_SRC_ADDR_FULL                                                                       0xf80c48UL //Access:R    DataWidth:0x1    // BRB source address fifo full in sdm_dma_dst block.
+#define XSDM_REG_DST_PXP_LINK_FULL                                                                           0xf80c4cUL //Access:R    DataWidth:0x1    // PXP link list full in sdm_dma_dst block.
+#define XSDM_REG_DST_INT_RAM_WAIT_FULL                                                                       0xf80c50UL //Access:R    DataWidth:0x1    // Int_ram_wait fifo full in sdm_dma_dst block.
+#define XSDM_REG_DST_PAS_BUF_WAIT_FULL                                                                       0xf80c54UL //Access:R    DataWidth:0x1    // Pas_buf_wait fifo full in sdm_dma_dst block.
+#define XSDM_REG_DST_PXP_IF_FULL                                                                             0xf80c58UL //Access:R    DataWidth:0x1    // PXP if full in sdm_dma_dst block.
+#define XSDM_REG_DST_INT_RAM_IF_FULL                                                                         0xf80c5cUL //Access:R    DataWidth:0x1    // Int_ram if full in sdm_dma_dst block.
+#define XSDM_REG_DST_PAS_BUF_IF_FULL                                                                         0xf80c60UL //Access:R    DataWidth:0x1    // Pas_buf if full in sdm_dma_dst block.
+#define XSDM_REG_SH_DELAY_FULL                                                                               0xf80c64UL //Access:R    DataWidth:0x1    // Shared delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.
+#define XSDM_REG_CM_DELAY_FULL                                                                               0xf80c68UL //Access:R    DataWidth:0x1    // CM delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.
+#define XSDM_REG_CMSG_QUE_FULL                                                                               0xf80c6cUL //Access:R    DataWidth:0x1    // Completion message queue fifo full in sdm_cm block.
+#define XSDM_REG_CCFC_LOAD_PEND_FULL                                                                         0xf80c70UL //Access:R    DataWidth:0x1    // CCFC load pending fifo full in the CCFC interface  block.
+#define XSDM_REG_TCFC_LOAD_PEND_FULL                                                                         0xf80c74UL //Access:R    DataWidth:0x1    // TCFC load pending fifo full in the TCFC interface block.
+#define XSDM_REG_ASYNC_HOST_FULL                                                                             0xf80c78UL //Access:R    DataWidth:0x1    // Async fifo full in sdm_async block.
+#define XSDM_REG_PRM_FIFO_FULL                                                                               0xf80c7cUL //Access:R    DataWidth:0x1    // PRM FIFO full in PRM interface block.
+#define XSDM_REG_RMT_XCM_FIFO_FULL_K2_E5                                                                     0xf80c80UL //Access:R    DataWidth:0x1    // Remote XCM FIFO full (exist only in MSDM => XCM interface).
+#define XSDM_REG_RMT_YCM_FIFO_FULL_K2_E5                                                                     0xf80c84UL //Access:R    DataWidth:0x1    // Remote YCM FIFO full (exist only in MSDM => YCM interface).
+#define XSDM_REG_INT_CMPL_PEND_EMPTY                                                                         0xf80d00UL //Access:R    DataWidth:0x1    // Internal write completion pending empty in internal write block.
+#define XSDM_REG_INT_CPRM_PEND_EMPTY                                                                         0xf80d04UL //Access:R    DataWidth:0x1    // Internal write completion parameter pending empty in internal write block.
+#define XSDM_REG_QUEUE_EMPTY                                                                                 0xf80d08UL //Access:R    DataWidth:0x9    // Input queue fifo empty in sdm_inp block.
+#define XSDM_REG_DELAY_FIFO_EMPTY                                                                            0xf80d0cUL //Access:R    DataWidth:0x1    // Delay FIFO  empty in sdm_inp block.
+#define XSDM_REG_TIMERS_PEND_EMPTY                                                                           0xf80d10UL //Access:R    DataWidth:0x1    // Pending FIFO  empty in sdm_timers block.
+#define XSDM_REG_TIMERS_ADDR_EMPTY                                                                           0xf80d14UL //Access:R    DataWidth:0x1    // Address FIFO  empty in sdm_timers block.
+#define XSDM_REG_RSP_PXP_RDATA_EMPTY                                                                         0xf80d18UL //Access:R    DataWidth:0x1    // PXP rd_data fifo  empty in sdm_dma_rsp block.
+#define XSDM_REG_RSP_BRB_RDATA_EMPTY                                                                         0xf80d1cUL //Access:R    DataWidth:0x1    // BRB read data fifo  empty in sdm_dma_rsp block.
+#define XSDM_REG_RSP_INT_RAM_RDATA_EMPTY                                                                     0xf80d20UL //Access:R    DataWidth:0x1    // Int_ram rd_data fifo  empty in sdm_dma_rsp block.
+#define XSDM_REG_RSP_BRB_PEND_EMPTY                                                                          0xf80d24UL //Access:R    DataWidth:0x1    // BRB pending fifo  empty in sdm_dma_rsp block.
+#define XSDM_REG_RSP_INT_RAM_PEND_EMPTY                                                                      0xf80d28UL //Access:R    DataWidth:0x1    // Int_ram pending fifo  empty in sdm_dma_rsp block.
+#define XSDM_REG_DST_PXP_IMMED_EMPTY                                                                         0xf80d2cUL //Access:R    DataWidth:0x1    // PXP immediate fifo empty in sdm_dma_dst block.
+#define XSDM_REG_DST_PXP_DST_PEND_EMPTY                                                                      0xf80d30UL //Access:R    DataWidth:0x1    // PXP destination pending fifo empty in sdm_dma_dst block.
+#define XSDM_REG_DST_PXP_SRC_PEND_EMPTY                                                                      0xf80d34UL //Access:R    DataWidth:0x1    // PXP source pending fifo empty in sdm_dma_dst block.
+#define XSDM_REG_DST_BRB_SRC_PEND_EMPTY                                                                      0xf80d38UL //Access:R    DataWidth:0x1    // BRB source pending fifo empty in sdm_dma_dst block.
+#define XSDM_REG_DST_BRB_SRC_ADDR_EMPTY                                                                      0xf80d3cUL //Access:R    DataWidth:0x1    // BRB source address fifo empty in sdm_dma_dst block.
+#define XSDM_REG_DST_PXP_LINK_EMPTY                                                                          0xf80d40UL //Access:R    DataWidth:0x1    // PXP link list empty in sdm_dma_dst block.
+#define XSDM_REG_DST_INT_RAM_WAIT_EMPTY                                                                      0xf80d44UL //Access:R    DataWidth:0x1    // Int_ram_wait fifo empty in sdm_dma_dst block.
+#define XSDM_REG_DST_PAS_BUF_WAIT_EMPTY                                                                      0xf80d48UL //Access:R    DataWidth:0x1    // Pas_buf_wait fifo empty in sdm_dma_dst block.
+#define XSDM_REG_SH_DELAY_EMPTY                                                                              0xf80d4cUL //Access:R    DataWidth:0x1    // Shared delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.
+#define XSDM_REG_CM_DELAY_EMPTY                                                                              0xf80d50UL //Access:R    DataWidth:0x1    // CM delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.
+#define XSDM_REG_CMSG_QUE_EMPTY                                                                              0xf80d54UL //Access:R    DataWidth:0x1    // Completion message queue fifo empty in sdm_dma_dst block.
+#define XSDM_REG_CCFC_LOAD_PEND_EMPTY                                                                        0xf80d58UL //Access:R    DataWidth:0x1    // CCFC load pending fifo empty in sdm_ccfc block.
+#define XSDM_REG_TCFC_LOAD_PEND_EMPTY                                                                        0xf80d5cUL //Access:R    DataWidth:0x1    // TCFC load pending fifo empty in sdm_tcfc block.
+#define XSDM_REG_ASYNC_HOST_EMPTY                                                                            0xf80d60UL //Access:R    DataWidth:0x1    // Async fifo empty in sdm_async block.
+#define XSDM_REG_PRM_FIFO_EMPTY                                                                              0xf80d64UL //Access:R    DataWidth:0x1    // PRM FIFO empty in sdm_prm_if block.
+#define XSDM_REG_RMT_XCM_FIFO_EMPTY_K2_E5                                                                    0xf80d68UL //Access:R    DataWidth:0x1    // Remote XCM FIFO empty (exist only within MSDM => XCM path).
+#define XSDM_REG_RMT_YCM_FIFO_EMPTY_K2_E5                                                                    0xf80d6cUL //Access:R    DataWidth:0x1    // Remote YCM FIFO empty (exist only within MSDM => YCM path).
+#define XSDM_REG_DBG_OUT_DATA                                                                                0xf80e00UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define XSDM_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define XSDM_REG_DBG_OUT_VALID                                                                               0xf80e20UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define XSDM_REG_DBG_OUT_FRAME                                                                               0xf80e24UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define XSDM_REG_DBG_SELECT                                                                                  0xf80e28UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define XSDM_REG_DBG_DWORD_ENABLE                                                                            0xf80e2cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define XSDM_REG_DBG_SHIFT                                                                                   0xf80e30UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define XSDM_REG_DBG_FORCE_VALID                                                                             0xf80e34UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define XSDM_REG_DBG_FORCE_FRAME                                                                             0xf80e38UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define XSDM_REG_ASYNC_FIFO                                                                                  0xf82000UL //Access:WB_R DataWidth:0x49   // Provides read-only access of the PXP-Async input FIFO. Intended for debug purposes.
+#define XSDM_REG_ASYNC_FIFO_SIZE                                                                             116
+#define XSDM_REG_IMMED_FIFO                                                                                  0xf82400UL //Access:WB_R DataWidth:0x40   // Provides read-only access of the immediate data FIFO. Intended for debug purposes.
+#define XSDM_REG_IMMED_FIFO_SIZE                                                                             38
+#define XSDM_REG_BRB_FIFO                                                                                    0xf82800UL //Access:WB_R DataWidth:0x86   // Provides read-only access of the BRB response FIFO. Intended for debug purposes.
+#define XSDM_REG_BRB_FIFO_SIZE                                                                               152
+#define XSDM_REG_PXP_FIFO                                                                                    0xf82c00UL //Access:WB_R DataWidth:0x4a   // Provides read-only access of the PXP response FIFO. Intended for debug purposes.
+#define XSDM_REG_PXP_FIFO_SIZE                                                                               76
+#define XSDM_REG_INT_RAM_FIFO                                                                                0xf83000UL //Access:WB_R DataWidth:0x41   // Provides read-only access of the internal RAM response FIFO. Intended for debug purposes.
+#define XSDM_REG_INT_RAM_FIFO_SIZE                                                                           76
+#define XSDM_REG_DPM_FIFO                                                                                    0xf83400UL //Access:WB_R DataWidth:0x51   // Provides read-only access of the DORQ DPM input FIFO. Intended for debug purposes.
+#define XSDM_REG_DPM_FIFO_SIZE                                                                               172
+#define XSDM_REG_EXT_OVERFLOW                                                                                0xf83800UL //Access:WB_R DataWidth:0x4b   // Provides read-only access of the external store overflow FIFO. Intended for debug purposes.
+#define XSDM_REG_EXT_OVERFLOW_SIZE                                                                           36
+#define XSDM_REG_PRM_FIFO                                                                                    0xf83c00UL //Access:WB_R DataWidth:0x41   // Provides read-only access of the PRM completion input FIFO. Intended for debug purposes.
+#define XSDM_REG_PRM_FIFO_SIZE                                                                               84
+#define XSDM_REG_TIMERS                                                                                      0xf84000UL //Access:WB   DataWidth:0x39   // Provides memory-mapped read/write access to the timers' memory. Intended for debug purposes.
+#define XSDM_REG_TIMERS_SIZE                                                                                 48
+#define XSDM_REG_INP_QUEUE                                                                                   0xf85000UL //Access:WB   DataWidth:0x40   // Input queue memory. Access only for debugging.
+#define XSDM_REG_INP_QUEUE_SIZE                                                                              416
+#define XSDM_REG_CMSG_QUE                                                                                    0xf88000UL //Access:WB   DataWidth:0x40   // CM queue memory. Access only for debugging.
+#define XSDM_REG_CMSG_QUE_SIZE                                                                               128
+#define YSDM_REG_ENABLE_IN1                                                                                  0xf90004UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define YSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN                                                                (0x1<<0) // Enable for input command from STORM.
+  #define YSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN_SHIFT                                                          0
+  #define YSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN                                                             (0x1<<1) // Enable for input data from internal ram interface in DMA_RSP block.
+  #define YSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN_SHIFT                                                       1
+  #define YSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN                                                             (0x1<<2) // Enable for input done from internal ram interface in DMA_RSP block.
+  #define YSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN_SHIFT                                                       2
+  #define YSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN                                                             (0x1<<3) // Enable for input full from internal ram interface in DMA_RSP block.
+  #define YSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN_SHIFT                                                       3
+  #define YSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN                                                             (0x1<<4) // Enable for input done from passive buffer interface in DMA_RSP block.
+  #define YSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN_SHIFT                                                       4
+  #define YSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN                                                             (0x1<<5) // Enable for input full from passive buffer interface in DMA_RSP block.
+  #define YSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN_SHIFT                                                       5
+  #define YSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN                                                                 (0x1<<6) // Enable for input done from pxp-HW interface in DMA_DST block.
+  #define YSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN_SHIFT                                                           6
+  #define YSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN                                                                 (0x1<<7) // Enable for input full from pxp-HW interface in DMA_DST block.
+  #define YSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN_SHIFT                                                           7
+  #define YSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN                                                                 (0x1<<8) // Enable for input data from pxp-HW interface in DMA_RSP block.
+  #define YSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN_SHIFT                                                           8
+  #define YSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN                                                              (0x1<<9) // Enable for input ack from pxp-internal write for SDM_INT block.
+  #define YSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN_SHIFT                                                        9
+  #define YSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN                                                                  (0x1<<10) // Enable for input acknowledge to credit counter from pxp_HW interface.
+  #define YSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN_SHIFT                                                            10
+  #define YSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN                                                                 (0x1<<11) // Enable for input data from BRB interface in DMA_RSP block.
+  #define YSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN_SHIFT                                                           11
+  #define YSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN                                                                  (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
+  #define YSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN_SHIFT                                                            12
+  #define YSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN                                                                  (0x1<<13) // Enable for input completion message from PRM in prm_if block.
+  #define YSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN_SHIFT                                                            13
+  #define YSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN                                                            (0x1<<14) // Enable for input ack to CCFC load credit counter.
+  #define YSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN_SHIFT                                                      14
+  #define YSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN                                                            (0x1<<15) // Enable for input ack to TCFC load credit counter.
+  #define YSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN_SHIFT                                                      15
+  #define YSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN                                                            (0x1<<16) // Enable for input response from CCFC in CCFC block.
+  #define YSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN_SHIFT                                                      16
+  #define YSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN                                                              (0x1<<17) // Enable for input ack to CCFC credit counter on the A/C interface.
+  #define YSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN_SHIFT                                                        17
+  #define YSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN                                                              (0x1<<18) // Enable for input ack to TCFC credit counter on the A/C interface.
+  #define YSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN_SHIFT                                                        18
+  #define YSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN                                                           (0x1<<19) // Enable for input full from qm in SDM_INP block.
+  #define YSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN_SHIFT                                                     19
+#define YSDM_REG_ENABLE_IN2                                                                                  0xf90008UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define YSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN                                                            (0x1<<0) // Enable for input response from TCFC in TCFC block.
+  #define YSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN_SHIFT                                                      0
+  #define YSDM_REG_ENABLE_IN2_CM_ACK_IN_EN                                                                   (0x1<<1) // Enable for input acknowledge from Cm  in SDM_CM block.
+  #define YSDM_REG_ENABLE_IN2_CM_ACK_IN_EN_SHIFT                                                             1
+  #define YSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN                                                                 (0x1<<2) // Enable for input DPM requests in SDM_DORQ block.
+  #define YSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN_SHIFT                                                           2
+#define YSDM_REG_ENABLE_OUT1                                                                                 0xf9000cUL //Access:RW   DataWidth:0x15   // Multi Field Register.
+  #define YSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN                                                                (0x1<<0) // Enable for output request to pxp internal write for SDM_INT block.
+  #define YSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN_SHIFT                                                          0
+  #define YSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN                                                             (0x1<<1) // Enable for output thread ready to the SEMI.
+  #define YSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN_SHIFT                                                       1
+  #define YSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN                                                             (0x1<<2) // Enable the output thread release to the SEMI.
+  #define YSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN_SHIFT                                                       2
+  #define YSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN                                                              (0x1<<3) // Enable for output load request to CCFC.
+  #define YSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN_SHIFT                                                        3
+  #define YSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN                                                              (0x1<<4) // Enable for output load request to TCFC.
+  #define YSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN_SHIFT                                                        4
+  #define YSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN                                                                (0x1<<5) // Enable for output increment to CCFC activity counter.
+  #define YSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN_SHIFT                                                          5
+  #define YSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN                                                                (0x1<<6) // Enable for output decrement to TCFC activity counter.
+  #define YSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN_SHIFT                                                          6
+  #define YSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN                                                                (0x1<<7) // Enable for output data to pxp-HW interface in DMA_REQ block.
+  #define YSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN_SHIFT                                                          7
+  #define YSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN                                                                (0x1<<8) // Enable for output request to BRB interface in DMA_REQ block.
+  #define YSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN_SHIFT                                                          8
+  #define YSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN                                                                (0x1<<9) // Enable for output write to int_ram in DMA_DST block.
+  #define YSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN_SHIFT                                                          9
+  #define YSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN                                                                (0x1<<10) // Enable for output write topassive buffer in DMA_DST block.
+  #define YSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN_SHIFT                                                          10
+  #define YSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN                                                              (0x1<<11) // Enable for output write to pxp async in DMA_DST block.
+  #define YSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN_SHIFT                                                        11
+  #define YSDM_REG_ENABLE_OUT1_PXP_OUT_EN                                                                    (0x1<<12) // Enable for output write to pxp  in DMA_DST block.
+  #define YSDM_REG_ENABLE_OUT1_PXP_OUT_EN_SHIFT                                                              12
+  #define YSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN                                                               (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
+  #define YSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN_SHIFT                                                         13
+  #define YSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN                                                               (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
+  #define YSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN_SHIFT                                                         14
+  #define YSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN                                                               (0x1<<15) // Enable for output external full to SEMI block.
+  #define YSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN_SHIFT                                                         15
+  #define YSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN                                                           (0x1<<16) // Enable for output done to async PXP host IF.
+  #define YSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN_SHIFT                                                     16
+  #define YSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN                                                           (0x1<<17) // Enable the output done (ack) to PRM.
+  #define YSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN_SHIFT                                                     17
+  #define YSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN                                                                 (0x1<<18) // Enable for output message to CM in SDM_CM block.
+  #define YSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN_SHIFT                                                           18
+  #define YSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN                                                           (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
+  #define YSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN_SHIFT                                                     19
+  #define YSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN                                                           (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
+  #define YSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN_SHIFT                                                     20
+#define YSDM_REG_ENABLE_OUT2                                                                                 0xf90010UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define YSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN                                                              (0x1<<0) // Enable for output command to qm in SDM_INP block.
+  #define YSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN_SHIFT                                                        0
+  #define YSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN                                                               (0x1<<1) // Enable for VF/PF error valid in DMA_DST block.
+  #define YSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN_SHIFT                                                         1
+  #define YSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN                                                          (0x1<<2) // Enable for DPM request done output in SDM_DORQ block.
+  #define YSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN_SHIFT                                                    2
+#define YSDM_REG_DISABLE_ENGINE                                                                              0xf90014UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define YSDM_REG_DISABLE_ENGINE_DISABLE_DMA                                                                (0x1<<0) // This bit should be set to disable the DMA exectuion engine from processing DMA commands.
+  #define YSDM_REG_DISABLE_ENGINE_DISABLE_DMA_SHIFT                                                          0
+  #define YSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS                                                             (0x1<<1) // This bit should be set to disable the timers' exectuion engine from processing timers' commands.
+  #define YSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS_SHIFT                                                       1
+  #define YSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD                                                          (0x1<<2) // This bit should be set to disable the CCFC exectuion engine from processing CCFC load commands.
+  #define YSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD_SHIFT                                                    2
+  #define YSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD                                                          (0x1<<3) // This bit should be set to disable the TCFC exectuion engine from processing TCFC load commands.
+  #define YSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD_SHIFT                                                    3
+  #define YSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR                                                             (0x1<<4) // This bit should be set to disable the internal write exectuion engine from processing Internal write commands.
+  #define YSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR_SHIFT                                                       4
+  #define YSDM_REG_DISABLE_ENGINE_DISABLE_NOP                                                                (0x1<<5) // This bit should be set to disable the SDM NOP exectuion engine from processing NOP commands.
+  #define YSDM_REG_DISABLE_ENGINE_DISABLE_NOP_SHIFT                                                          5
+  #define YSDM_REG_DISABLE_ENGINE_DISABLE_GRC                                                                (0x1<<6) // This bit should be set to disable the GRC master exectuion engine from processing GRC master commands.
+  #define YSDM_REG_DISABLE_ENGINE_DISABLE_GRC_SHIFT                                                          6
+  #define YSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC                                                              (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Async requests.
+  #define YSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC_SHIFT                                                        7
+  #define YSDM_REG_DISABLE_ENGINE_DISABLE_PRM                                                                (0x1<<8) // This bit should be set to disable the PRM interface from processing PRM completion commands.
+  #define YSDM_REG_DISABLE_ENGINE_DISABLE_PRM_SHIFT                                                          8
+  #define YSDM_REG_DISABLE_ENGINE_DISABLE_DORQ                                                               (0x1<<9) // This bit should be set to disable the DORQ DPM interface from processing DPM commands.
+  #define YSDM_REG_DISABLE_ENGINE_DISABLE_DORQ_SHIFT                                                         9
+#define YSDM_REG_INT_STS                                                                                     0xf90040UL //Access:R    DataWidth:0x1c   // Multi Field Register.
+  #define YSDM_REG_INT_STS_ADDRESS_ERROR                                                                     (0x1<<0) // Signals an unknown address to the rf module.
+  #define YSDM_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                               0
+  #define YSDM_REG_INT_STS_INP_QUEUE_ERROR                                                                   (0x1<<1) // Indicates that one of the input queues had a FIFO error.
+  #define YSDM_REG_INT_STS_INP_QUEUE_ERROR_SHIFT                                                             1
+  #define YSDM_REG_INT_STS_DELAY_FIFO_ERROR                                                                  (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
+  #define YSDM_REG_INT_STS_DELAY_FIFO_ERROR_SHIFT                                                            2
+  #define YSDM_REG_INT_STS_ASYNC_HOST_ERROR                                                                  (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
+  #define YSDM_REG_INT_STS_ASYNC_HOST_ERROR_SHIFT                                                            3
+  #define YSDM_REG_INT_STS_PRM_FIFO_ERROR                                                                    (0x1<<4) // FIFO in PRM interface sub-module reported an error.
+  #define YSDM_REG_INT_STS_PRM_FIFO_ERROR_SHIFT                                                              4
+  #define YSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR                                                              (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
+  #define YSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR_SHIFT                                                        5
+  #define YSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR                                                              (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
+  #define YSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR_SHIFT                                                        6
+  #define YSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR                                                            (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
+  #define YSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR_SHIFT                                                      7
+  #define YSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR                                                            (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
+  #define YSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR_SHIFT                                                      8
+  #define YSDM_REG_INT_STS_DST_PXP_IMMED_ERROR                                                               (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
+  #define YSDM_REG_INT_STS_DST_PXP_IMMED_ERROR_SHIFT                                                         9
+  #define YSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR                                                            (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
+  #define YSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR_SHIFT                                                      10
+  #define YSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR                                                            (0x1<<11) // BRB src pend fifo error in DMA_DST block.
+  #define YSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR_SHIFT                                                      11
+  #define YSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR                                                            (0x1<<12) // BRB src addr fifo error in DMA_DST block.
+  #define YSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR_SHIFT                                                      12
+  #define YSDM_REG_INT_STS_RSP_BRB_PEND_ERROR                                                                (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
+  #define YSDM_REG_INT_STS_RSP_BRB_PEND_ERROR_SHIFT                                                          13
+  #define YSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR                                                            (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
+  #define YSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR_SHIFT                                                      14
+  #define YSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR                                                             (0x1<<15) // Read data firo in DMA_RSP block for BRB.
+  #define YSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR_SHIFT                                                       15
+  #define YSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR                                                         (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
+  #define YSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                                   16
+  #define YSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR                                                             (0x1<<17) // PXP read data fifo error in DMA_RSP block.
+  #define YSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR_SHIFT                                                       17
+  #define YSDM_REG_INT_STS_CM_DELAY_ERROR                                                                    (0x1<<18) // Delay CM fifo error in CM block.
+  #define YSDM_REG_INT_STS_CM_DELAY_ERROR_SHIFT                                                              18
+  #define YSDM_REG_INT_STS_SH_DELAY_ERROR                                                                    (0x1<<19) // Delay shared fifo error in CM block.
+  #define YSDM_REG_INT_STS_SH_DELAY_ERROR_SHIFT                                                              19
+  #define YSDM_REG_INT_STS_CMPL_PEND_ERROR                                                                   (0x1<<20) // Error in completion pending FIFO in internal write block.
+  #define YSDM_REG_INT_STS_CMPL_PEND_ERROR_SHIFT                                                             20
+  #define YSDM_REG_INT_STS_CPRM_PEND_ERROR                                                                   (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
+  #define YSDM_REG_INT_STS_CPRM_PEND_ERROR_SHIFT                                                             21
+  #define YSDM_REG_INT_STS_TIMER_ADDR_ERROR                                                                  (0x1<<22) // Address fifo error in timer block.
+  #define YSDM_REG_INT_STS_TIMER_ADDR_ERROR_SHIFT                                                            22
+  #define YSDM_REG_INT_STS_TIMER_PEND_ERROR                                                                  (0x1<<23) // Pending fifo error in timer block.
+  #define YSDM_REG_INT_STS_TIMER_PEND_ERROR_SHIFT                                                            23
+  #define YSDM_REG_INT_STS_DORQ_DPM_ERROR                                                                    (0x1<<24) // Dpm fifo error in dorq I/F block.
+  #define YSDM_REG_INT_STS_DORQ_DPM_ERROR_SHIFT                                                              24
+  #define YSDM_REG_INT_STS_DST_PXP_DONE_ERROR                                                                (0x1<<25) // PXP done fifo error in DMA_dst block.
+  #define YSDM_REG_INT_STS_DST_PXP_DONE_ERROR_SHIFT                                                          25
+  #define YSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR_K2_E5                                                        (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define YSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                                  26
+  #define YSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_K2_E5                                                        (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define YSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                                  27
+#define YSDM_REG_INT_MASK                                                                                    0xf90044UL //Access:RW   DataWidth:0x1c   // Multi Field Register.
+  #define YSDM_REG_INT_MASK_ADDRESS_ERROR                                                                    (0x1<<0) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.ADDRESS_ERROR .
+  #define YSDM_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                              0
+  #define YSDM_REG_INT_MASK_INP_QUEUE_ERROR                                                                  (0x1<<1) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.INP_QUEUE_ERROR .
+  #define YSDM_REG_INT_MASK_INP_QUEUE_ERROR_SHIFT                                                            1
+  #define YSDM_REG_INT_MASK_DELAY_FIFO_ERROR                                                                 (0x1<<2) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DELAY_FIFO_ERROR .
+  #define YSDM_REG_INT_MASK_DELAY_FIFO_ERROR_SHIFT                                                           2
+  #define YSDM_REG_INT_MASK_ASYNC_HOST_ERROR                                                                 (0x1<<3) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.ASYNC_HOST_ERROR .
+  #define YSDM_REG_INT_MASK_ASYNC_HOST_ERROR_SHIFT                                                           3
+  #define YSDM_REG_INT_MASK_PRM_FIFO_ERROR                                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.PRM_FIFO_ERROR .
+  #define YSDM_REG_INT_MASK_PRM_FIFO_ERROR_SHIFT                                                             4
+  #define YSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR                                                             (0x1<<5) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.CCFC_LOAD_PEND_ERROR .
+  #define YSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR_SHIFT                                                       5
+  #define YSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR                                                             (0x1<<6) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.TCFC_LOAD_PEND_ERROR .
+  #define YSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR_SHIFT                                                       6
+  #define YSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR                                                           (0x1<<7) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DST_INT_RAM_WAIT_ERROR .
+  #define YSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR_SHIFT                                                     7
+  #define YSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR                                                           (0x1<<8) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DST_PAS_BUF_WAIT_ERROR .
+  #define YSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR_SHIFT                                                     8
+  #define YSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR                                                              (0x1<<9) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DST_PXP_IMMED_ERROR .
+  #define YSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR_SHIFT                                                        9
+  #define YSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR                                                           (0x1<<10) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DST_PXP_DST_PEND_ERROR .
+  #define YSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR_SHIFT                                                     10
+  #define YSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR                                                           (0x1<<11) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DST_BRB_SRC_PEND_ERROR .
+  #define YSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR_SHIFT                                                     11
+  #define YSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR                                                           (0x1<<12) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DST_BRB_SRC_ADDR_ERROR .
+  #define YSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR_SHIFT                                                     12
+  #define YSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR                                                               (0x1<<13) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.RSP_BRB_PEND_ERROR .
+  #define YSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR_SHIFT                                                         13
+  #define YSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR                                                           (0x1<<14) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.RSP_INT_RAM_PEND_ERROR .
+  #define YSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR_SHIFT                                                     14
+  #define YSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR                                                            (0x1<<15) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.RSP_BRB_RD_DATA_ERROR .
+  #define YSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR_SHIFT                                                      15
+  #define YSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR                                                        (0x1<<16) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.RSP_INT_RAM_RD_DATA_ERROR .
+  #define YSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                                  16
+  #define YSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR                                                            (0x1<<17) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.RSP_PXP_RD_DATA_ERROR .
+  #define YSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR_SHIFT                                                      17
+  #define YSDM_REG_INT_MASK_CM_DELAY_ERROR                                                                   (0x1<<18) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.CM_DELAY_ERROR .
+  #define YSDM_REG_INT_MASK_CM_DELAY_ERROR_SHIFT                                                             18
+  #define YSDM_REG_INT_MASK_SH_DELAY_ERROR                                                                   (0x1<<19) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.SH_DELAY_ERROR .
+  #define YSDM_REG_INT_MASK_SH_DELAY_ERROR_SHIFT                                                             19
+  #define YSDM_REG_INT_MASK_CMPL_PEND_ERROR                                                                  (0x1<<20) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.CMPL_PEND_ERROR .
+  #define YSDM_REG_INT_MASK_CMPL_PEND_ERROR_SHIFT                                                            20
+  #define YSDM_REG_INT_MASK_CPRM_PEND_ERROR                                                                  (0x1<<21) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.CPRM_PEND_ERROR .
+  #define YSDM_REG_INT_MASK_CPRM_PEND_ERROR_SHIFT                                                            21
+  #define YSDM_REG_INT_MASK_TIMER_ADDR_ERROR                                                                 (0x1<<22) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.TIMER_ADDR_ERROR .
+  #define YSDM_REG_INT_MASK_TIMER_ADDR_ERROR_SHIFT                                                           22
+  #define YSDM_REG_INT_MASK_TIMER_PEND_ERROR                                                                 (0x1<<23) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.TIMER_PEND_ERROR .
+  #define YSDM_REG_INT_MASK_TIMER_PEND_ERROR_SHIFT                                                           23
+  #define YSDM_REG_INT_MASK_DORQ_DPM_ERROR                                                                   (0x1<<24) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DORQ_DPM_ERROR .
+  #define YSDM_REG_INT_MASK_DORQ_DPM_ERROR_SHIFT                                                             24
+  #define YSDM_REG_INT_MASK_DST_PXP_DONE_ERROR                                                               (0x1<<25) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DST_PXP_DONE_ERROR .
+  #define YSDM_REG_INT_MASK_DST_PXP_DONE_ERROR_SHIFT                                                         25
+  #define YSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR_K2_E5                                                       (0x1<<26) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.XCM_RMT_BUFFER_ERROR .
+  #define YSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                                 26
+  #define YSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_K2_E5                                                       (0x1<<27) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.YCM_RMT_BUFFER_ERROR .
+  #define YSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                                 27
+#define YSDM_REG_INT_STS_WR                                                                                  0xf90048UL //Access:WR   DataWidth:0x1c   // Multi Field Register.
+  #define YSDM_REG_INT_STS_WR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define YSDM_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                            0
+  #define YSDM_REG_INT_STS_WR_INP_QUEUE_ERROR                                                                (0x1<<1) // Indicates that one of the input queues had a FIFO error.
+  #define YSDM_REG_INT_STS_WR_INP_QUEUE_ERROR_SHIFT                                                          1
+  #define YSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR                                                               (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
+  #define YSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR_SHIFT                                                         2
+  #define YSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR                                                               (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
+  #define YSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR_SHIFT                                                         3
+  #define YSDM_REG_INT_STS_WR_PRM_FIFO_ERROR                                                                 (0x1<<4) // FIFO in PRM interface sub-module reported an error.
+  #define YSDM_REG_INT_STS_WR_PRM_FIFO_ERROR_SHIFT                                                           4
+  #define YSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR                                                           (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
+  #define YSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR_SHIFT                                                     5
+  #define YSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR                                                           (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
+  #define YSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR_SHIFT                                                     6
+  #define YSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR                                                         (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
+  #define YSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR_SHIFT                                                   7
+  #define YSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR                                                         (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
+  #define YSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR_SHIFT                                                   8
+  #define YSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR                                                            (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
+  #define YSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR_SHIFT                                                      9
+  #define YSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR                                                         (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
+  #define YSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR_SHIFT                                                   10
+  #define YSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR                                                         (0x1<<11) // BRB src pend fifo error in DMA_DST block.
+  #define YSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR_SHIFT                                                   11
+  #define YSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR                                                         (0x1<<12) // BRB src addr fifo error in DMA_DST block.
+  #define YSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR_SHIFT                                                   12
+  #define YSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR                                                             (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
+  #define YSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR_SHIFT                                                       13
+  #define YSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR                                                         (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
+  #define YSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR_SHIFT                                                   14
+  #define YSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR                                                          (0x1<<15) // Read data firo in DMA_RSP block for BRB.
+  #define YSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR_SHIFT                                                    15
+  #define YSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR                                                      (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
+  #define YSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                                16
+  #define YSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR                                                          (0x1<<17) // PXP read data fifo error in DMA_RSP block.
+  #define YSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR_SHIFT                                                    17
+  #define YSDM_REG_INT_STS_WR_CM_DELAY_ERROR                                                                 (0x1<<18) // Delay CM fifo error in CM block.
+  #define YSDM_REG_INT_STS_WR_CM_DELAY_ERROR_SHIFT                                                           18
+  #define YSDM_REG_INT_STS_WR_SH_DELAY_ERROR                                                                 (0x1<<19) // Delay shared fifo error in CM block.
+  #define YSDM_REG_INT_STS_WR_SH_DELAY_ERROR_SHIFT                                                           19
+  #define YSDM_REG_INT_STS_WR_CMPL_PEND_ERROR                                                                (0x1<<20) // Error in completion pending FIFO in internal write block.
+  #define YSDM_REG_INT_STS_WR_CMPL_PEND_ERROR_SHIFT                                                          20
+  #define YSDM_REG_INT_STS_WR_CPRM_PEND_ERROR                                                                (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
+  #define YSDM_REG_INT_STS_WR_CPRM_PEND_ERROR_SHIFT                                                          21
+  #define YSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR                                                               (0x1<<22) // Address fifo error in timer block.
+  #define YSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR_SHIFT                                                         22
+  #define YSDM_REG_INT_STS_WR_TIMER_PEND_ERROR                                                               (0x1<<23) // Pending fifo error in timer block.
+  #define YSDM_REG_INT_STS_WR_TIMER_PEND_ERROR_SHIFT                                                         23
+  #define YSDM_REG_INT_STS_WR_DORQ_DPM_ERROR                                                                 (0x1<<24) // Dpm fifo error in dorq I/F block.
+  #define YSDM_REG_INT_STS_WR_DORQ_DPM_ERROR_SHIFT                                                           24
+  #define YSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR                                                             (0x1<<25) // PXP done fifo error in DMA_dst block.
+  #define YSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR_SHIFT                                                       25
+  #define YSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR_K2_E5                                                     (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define YSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                               26
+  #define YSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_K2_E5                                                     (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define YSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                               27
+#define YSDM_REG_INT_STS_CLR                                                                                 0xf9004cUL //Access:RC   DataWidth:0x1c   // Multi Field Register.
+  #define YSDM_REG_INT_STS_CLR_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define YSDM_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                           0
+  #define YSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR                                                               (0x1<<1) // Indicates that one of the input queues had a FIFO error.
+  #define YSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR_SHIFT                                                         1
+  #define YSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR                                                              (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
+  #define YSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR_SHIFT                                                        2
+  #define YSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR                                                              (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
+  #define YSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR_SHIFT                                                        3
+  #define YSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR                                                                (0x1<<4) // FIFO in PRM interface sub-module reported an error.
+  #define YSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR_SHIFT                                                          4
+  #define YSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR                                                          (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
+  #define YSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR_SHIFT                                                    5
+  #define YSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR                                                          (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
+  #define YSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR_SHIFT                                                    6
+  #define YSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR                                                        (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
+  #define YSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR_SHIFT                                                  7
+  #define YSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR                                                        (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
+  #define YSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR_SHIFT                                                  8
+  #define YSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR                                                           (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
+  #define YSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR_SHIFT                                                     9
+  #define YSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR                                                        (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
+  #define YSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR_SHIFT                                                  10
+  #define YSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR                                                        (0x1<<11) // BRB src pend fifo error in DMA_DST block.
+  #define YSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR_SHIFT                                                  11
+  #define YSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR                                                        (0x1<<12) // BRB src addr fifo error in DMA_DST block.
+  #define YSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR_SHIFT                                                  12
+  #define YSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR                                                            (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
+  #define YSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR_SHIFT                                                      13
+  #define YSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR                                                        (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
+  #define YSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR_SHIFT                                                  14
+  #define YSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR                                                         (0x1<<15) // Read data firo in DMA_RSP block for BRB.
+  #define YSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR_SHIFT                                                   15
+  #define YSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR                                                     (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
+  #define YSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                               16
+  #define YSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR                                                         (0x1<<17) // PXP read data fifo error in DMA_RSP block.
+  #define YSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR_SHIFT                                                   17
+  #define YSDM_REG_INT_STS_CLR_CM_DELAY_ERROR                                                                (0x1<<18) // Delay CM fifo error in CM block.
+  #define YSDM_REG_INT_STS_CLR_CM_DELAY_ERROR_SHIFT                                                          18
+  #define YSDM_REG_INT_STS_CLR_SH_DELAY_ERROR                                                                (0x1<<19) // Delay shared fifo error in CM block.
+  #define YSDM_REG_INT_STS_CLR_SH_DELAY_ERROR_SHIFT                                                          19
+  #define YSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR                                                               (0x1<<20) // Error in completion pending FIFO in internal write block.
+  #define YSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR_SHIFT                                                         20
+  #define YSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR                                                               (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
+  #define YSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR_SHIFT                                                         21
+  #define YSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR                                                              (0x1<<22) // Address fifo error in timer block.
+  #define YSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR_SHIFT                                                        22
+  #define YSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR                                                              (0x1<<23) // Pending fifo error in timer block.
+  #define YSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR_SHIFT                                                        23
+  #define YSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR                                                                (0x1<<24) // Dpm fifo error in dorq I/F block.
+  #define YSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR_SHIFT                                                          24
+  #define YSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR                                                            (0x1<<25) // PXP done fifo error in DMA_dst block.
+  #define YSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR_SHIFT                                                      25
+  #define YSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR_K2_E5                                                    (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define YSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                              26
+  #define YSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_K2_E5                                                    (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define YSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                              27
+#define YSDM_REG_PRTY_MASK_H_0_BB_K2                                                                         0xf90204UL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define YSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2                                                     (0x1<<0) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define YSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2_SHIFT                                               0
+  #define YSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2                                                     (0x1<<1) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define YSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2_SHIFT                                               1
+  #define YSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2                                                     (0x1<<2) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define YSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2_SHIFT                                               2
+  #define YSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2                                                     (0x1<<3) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define YSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT                                               3
+  #define YSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                     (0x1<<4) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define YSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                               4
+  #define YSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2                                                     (0x1<<5) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define YSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2_SHIFT                                               5
+  #define YSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                     (0x1<<6) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define YSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                               6
+  #define YSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                     (0x1<<7) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define YSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                               7
+  #define YSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                     (0x1<<8) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define YSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                               8
+#define YSDM_REG_MEM_ECC_EVENTS_BB_K2                                                                        0xf90210UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define YSDM_REG_TIMER_TICK                                                                                  0xf90400UL //Access:RW   DataWidth:0x20   // Defines the number of system clock cycles that are used to define a timers clock tick cycle. Note: The minimal legal value for this register is 25, lower values can cause timers functionality issues.
+#define YSDM_REG_TIMERS_TICK_ENABLE                                                                          0xf90404UL //Access:RW   DataWidth:0x1    // Enable for tick counter.
+#define YSDM_REG_OPERATION_GEN                                                                               0xf90408UL //Access:W    DataWidth:0x14   // This register is used to assert a completion operation of choice; It includes the following completion fields: bits 19:16 are Trig; bits 15:0 are CompParams. Note that trigger types 3,5 or 8 are not supported by this interface as they require a completion message. If there is an attempt to assert an OperationGen with Trig = 3,5 or 8, the operation will be voided.
+#define YSDM_REG_GRC_PRIVILEGE_LEVEL                                                                         0xf9040cUL //Access:RW   DataWidth:0x2    // This register defines the PRV (privilege level) field within the FID structure of the SDM GRC master request.
+#define YSDM_REG_CM_MSG_CNT_ADDRESS                                                                          0xf90410UL //Access:RW   DataWidth:0xf    // The internal RAM address for storing the shadow of the CM completion message counter.
+#define YSDM_REG_DORQ_DPM_START_ADDR                                                                         0xf90414UL //Access:RW   DataWidth:0xf    // The start address in the internal RAM for DORQ DPM messages.
+#define YSDM_REG_RR_COMPLETE_REQ                                                                             0xf90418UL //Access:R    DataWidth:0xa    // Provides read access to the round robin arbiter used for all completion write requests  in the completion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b7-PRM interface; b8-CCFC load; b9-TCFC load.
+#define YSDM_REG_RR_PTR_REQ                                                                                  0xf9041cUL //Access:R    DataWidth:0x9    // Provides read access to the round robin arbiter for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-int_wr; b7-prm; b8-grc_master.
+#define YSDM_REG_INT_RAM_RR_REQ                                                                              0xf90420UL //Access:R    DataWidth:0x4    // Provides read access to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination;b2-PXP source/destination;b3-BRB source.
+#define YSDM_REG_INP_QUEUE_ERR_VECT                                                                          0xf90424UL //Access:R    DataWidth:0x9    // This register is intended to be read in the event of an inp_queue_error interrupt.  It contains a vector with a bit per input queue. Clearing the interrupt causes this vector to be cleared. Errors on multiple FIFOs will be aggregated between interrupt clear requests.
+#define YSDM_REG_ASYNC_CMSG_ALLOC_LIMIT                                                                      0xf90428UL //Access:RW   DataWidth:0x5    // This register defines the maximum number of completion messages that can be allocated to PXP-Async transactions at any given time. If the PXP-Async interface attempts to reserve beyond this limit, it will be held off until the situation is resolved.
+#define YSDM_REG_ECO_RESERVED                                                                                0xf9042cUL //Access:RW   DataWidth:0x8    // Reserved bits for ECO.
+#define YSDM_REG_INIT_CREDIT_PXP                                                                             0xf90500UL //Access:RW   DataWidth:0x3    // The initial number of messages that can be sent to the pxp interface without receiving any ACK.
+#define YSDM_REG_INIT_CREDIT_PCI                                                                             0xf90504UL //Access:RW   DataWidth:0x2    // The initial number of messages that can be sent to the PCI-Switch on the internal write interface without receiving any ACK.
+#define YSDM_REG_INIT_CREDIT_TCFC_AC                                                                         0xf90508UL //Access:RW   DataWidth:0x4    // The initial number of messages that can be sent to the TCFC activity counters interface without receiving any ACK.
+#define YSDM_REG_INIT_CREDIT_CCFC_AC                                                                         0xf9050cUL //Access:RW   DataWidth:0x4    // The initial number of messages that can be sent to the CCFC activity counters interface without receiving any ACK.
+#define YSDM_REG_INIT_CREDIT_CM                                                                              0xf90510UL //Access:RW   DataWidth:0x4    // The initial number of cycles that can be sent to the CM interface without receiving any ACK in CM block.
+#define YSDM_REG_INIT_CREDIT_CM_RMT                                                                          0xf90520UL //Access:RW   DataWidth:0x4    // The initial number of cycles that can be sent to a remote CM interface without receiving any ACK in CM block.
+#define YSDM_REG_INIT_CREDIT_CM_RMT_SIZE                                                                     3
+#define YSDM_REG_NUM_OF_DMA_CMD                                                                              0xf90600UL //Access:RC   DataWidth:0x20   // The number of SDM DMA commands executed.
+#define YSDM_REG_NUM_OF_TIMERS_CMD                                                                           0xf90604UL //Access:RC   DataWidth:0x20   // The number of SDM timers commands executed.
+#define YSDM_REG_NUM_OF_CCFC_LD_CMD                                                                          0xf90608UL //Access:RC   DataWidth:0x20   // The number of SDM CCFC load commands executed.
+#define YSDM_REG_NUM_OF_CCFC_AC_CMD                                                                          0xf9060cUL //Access:RC   DataWidth:0x20   // The number of SDM CCFC activity counter commands executed.
+#define YSDM_REG_NUM_OF_TCFC_LD_CMD                                                                          0xf90610UL //Access:RC   DataWidth:0x20   // The number of SDM TCFC load commands executed.
+#define YSDM_REG_NUM_OF_TCFC_AC_CMD                                                                          0xf90614UL //Access:RC   DataWidth:0x20   // The number of SDM TCFC activity counter commands executed.
+#define YSDM_REG_NUM_OF_INT_CMD                                                                              0xf90618UL //Access:RC   DataWidth:0x20   // The number of SDM internal write commands executed.
+#define YSDM_REG_NUM_OF_NOP_CMD                                                                              0xf9061cUL //Access:RC   DataWidth:0x20   // The number of SDM NOP commands executed.
+#define YSDM_REG_NUM_OF_GRC_CMD                                                                              0xf90620UL //Access:RC   DataWidth:0x20   // The number of GRC master commands executed.
+#define YSDM_REG_NUM_OF_PRM_REQ                                                                              0xf90624UL //Access:RC   DataWidth:0x20   // The number of packet end messages received on the PRM completion interface.
+#define YSDM_REG_NUM_OF_PXP_ASYNC_REQ                                                                        0xf90628UL //Access:RC   DataWidth:0x20   // The number of requests received from the pxp async if.
+#define YSDM_REG_NUM_OF_DPM_REQ                                                                              0xf9062cUL //Access:RC   DataWidth:0x20   // The number of DORQ DPM messages received.
+#define YSDM_REG_BRB_ALMOST_FULL                                                                             0xf90700UL //Access:RW   DataWidth:0x5    // Almost full signal for read data from BRB in DMA_RSP block.
+#define YSDM_REG_PXP_ALMOST_FULL                                                                             0xf90704UL //Access:RW   DataWidth:0x4    // Almost full signal for read data from pxp in DMA_RSP block.
+#define YSDM_REG_DORQ_ALMOST_FULL                                                                            0xf90708UL //Access:RW   DataWidth:0x6    // Almost full signal for read data from DORQ in SDM_DORQ block.
+#define YSDM_REG_AGG_INT_CTRL                                                                                0xf90800UL //Access:RW   DataWidth:0xa    // This array of registers provides controls for each of the aggregated interrupts; The fields are defined as follows: [20:16] Affinity [15:12] NumL2m. [11]    Exclusive. [10]    Core-selection where 0=Core_A and 1=Core_B. [9]     Mode bit where 0=normal and 1=auto-mask-mode. [8]     T-flag which determines if a thread is allocated for this handler in the Storm. [7:0]   EventID which selects the event ID of the associated handler.
+#define YSDM_REG_AGG_INT_CTRL_SIZE                                                                           32
+#define YSDM_REG_AGG_INT_STATE                                                                               0xf90a00UL //Access:R    DataWidth:0x2    // This array of registers provides access to each of the 32 aggregated interrupt request state machines; The values read from this register mean the following; 00 = IDLE; 01 = PEND; 10 = MASK; 11 = PANDM.
+#define YSDM_REG_AGG_INT_STATE_SIZE                                                                          32
+#define YSDM_REG_QUEUE_FULL                                                                                  0xf90c00UL //Access:R    DataWidth:0x9    // Input queue fifo full in sdm_inp block.
+#define YSDM_REG_INT_CMPL_PEND_FULL                                                                          0xf90c04UL //Access:R    DataWidth:0x1    // Internal write completion pending full in internal write block.
+#define YSDM_REG_INT_CPRM_PEND_FULL                                                                          0xf90c08UL //Access:R    DataWidth:0x1    // Internal write completion parameter pending full in internal write block.
+#define YSDM_REG_QM_FULL                                                                                     0xf90c0cUL //Access:R    DataWidth:0x1    // QM IF  full in sdm_inp block.
+#define YSDM_REG_DELAY_FIFO_FULL                                                                             0xf90c10UL //Access:R    DataWidth:0x1    // Delay FIFO  full in sdm_inp block.
+#define YSDM_REG_TIMERS_PEND_FULL                                                                            0xf90c14UL //Access:R    DataWidth:0x1    // Pending FIFO  full in sdm_timers block.
+#define YSDM_REG_TIMERS_ADDR_FULL                                                                            0xf90c18UL //Access:R    DataWidth:0x1    // Address FIFO  full in sdm_timers block.
+#define YSDM_REG_RSP_PXP_RDATA_FULL                                                                          0xf90c1cUL //Access:R    DataWidth:0x1    // PXP rd_data fifo  full in sdm_dma_rsp block.
+#define YSDM_REG_RSP_BRB_RDATA_FULL                                                                          0xf90c20UL //Access:R    DataWidth:0x1    // BRB read data fifo  full in sdm_dma_rsp block.
+#define YSDM_REG_RSP_INT_RAM_RDATA_FULL                                                                      0xf90c24UL //Access:R    DataWidth:0x1    // Int_ram rd_data fifo  full in sdm_dma_rsp block.
+#define YSDM_REG_RSP_BRB_PEND_FULL                                                                           0xf90c28UL //Access:R    DataWidth:0x1    // BRB pending fifo  full in sdm_dma_rsp block.
+#define YSDM_REG_RSP_INT_RAM_PEND_FULL                                                                       0xf90c2cUL //Access:R    DataWidth:0x1    // Int_ram pending fifo  full in sdm_dma_rsp block.
+#define YSDM_REG_RSP_BRB_IF_FULL                                                                             0xf90c30UL //Access:R    DataWidth:0x1    // BRB interface is  full in sdm_dma_rsp block.
+#define YSDM_REG_RSP_PXP_IF_FULL                                                                             0xf90c34UL //Access:R    DataWidth:0x1    // PXP interface is  full in sdm_dma_rsp block.
+#define YSDM_REG_DST_PXP_IMMED_FULL                                                                          0xf90c38UL //Access:R    DataWidth:0x1    // PXP immediate fifo full in sdm_dma_dst block.
+#define YSDM_REG_DST_PXP_DST_PEND_FULL                                                                       0xf90c3cUL //Access:R    DataWidth:0x1    // PXP destination pending fifo full in sdm_dma_dst block.
+#define YSDM_REG_DST_PXP_SRC_PEND_FULL                                                                       0xf90c40UL //Access:R    DataWidth:0x1    // PXP source pending fifo full in sdm_dma_dst block.
+#define YSDM_REG_DST_BRB_SRC_PEND_FULL                                                                       0xf90c44UL //Access:R    DataWidth:0x1    // BRB source pending fifo full in sdm_dma_dst block.
+#define YSDM_REG_DST_BRB_SRC_ADDR_FULL                                                                       0xf90c48UL //Access:R    DataWidth:0x1    // BRB source address fifo full in sdm_dma_dst block.
+#define YSDM_REG_DST_PXP_LINK_FULL                                                                           0xf90c4cUL //Access:R    DataWidth:0x1    // PXP link list full in sdm_dma_dst block.
+#define YSDM_REG_DST_INT_RAM_WAIT_FULL                                                                       0xf90c50UL //Access:R    DataWidth:0x1    // Int_ram_wait fifo full in sdm_dma_dst block.
+#define YSDM_REG_DST_PAS_BUF_WAIT_FULL                                                                       0xf90c54UL //Access:R    DataWidth:0x1    // Pas_buf_wait fifo full in sdm_dma_dst block.
+#define YSDM_REG_DST_PXP_IF_FULL                                                                             0xf90c58UL //Access:R    DataWidth:0x1    // PXP if full in sdm_dma_dst block.
+#define YSDM_REG_DST_INT_RAM_IF_FULL                                                                         0xf90c5cUL //Access:R    DataWidth:0x1    // Int_ram if full in sdm_dma_dst block.
+#define YSDM_REG_DST_PAS_BUF_IF_FULL                                                                         0xf90c60UL //Access:R    DataWidth:0x1    // Pas_buf if full in sdm_dma_dst block.
+#define YSDM_REG_SH_DELAY_FULL                                                                               0xf90c64UL //Access:R    DataWidth:0x1    // Shared delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.
+#define YSDM_REG_CM_DELAY_FULL                                                                               0xf90c68UL //Access:R    DataWidth:0x1    // CM delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.
+#define YSDM_REG_CMSG_QUE_FULL                                                                               0xf90c6cUL //Access:R    DataWidth:0x1    // Completion message queue fifo full in sdm_cm block.
+#define YSDM_REG_CCFC_LOAD_PEND_FULL                                                                         0xf90c70UL //Access:R    DataWidth:0x1    // CCFC load pending fifo full in the CCFC interface  block.
+#define YSDM_REG_TCFC_LOAD_PEND_FULL                                                                         0xf90c74UL //Access:R    DataWidth:0x1    // TCFC load pending fifo full in the TCFC interface block.
+#define YSDM_REG_ASYNC_HOST_FULL                                                                             0xf90c78UL //Access:R    DataWidth:0x1    // Async fifo full in sdm_async block.
+#define YSDM_REG_PRM_FIFO_FULL                                                                               0xf90c7cUL //Access:R    DataWidth:0x1    // PRM FIFO full in PRM interface block.
+#define YSDM_REG_RMT_XCM_FIFO_FULL_K2_E5                                                                     0xf90c80UL //Access:R    DataWidth:0x1    // Remote XCM FIFO full (exist only in MSDM => XCM interface).
+#define YSDM_REG_RMT_YCM_FIFO_FULL_K2_E5                                                                     0xf90c84UL //Access:R    DataWidth:0x1    // Remote YCM FIFO full (exist only in MSDM => YCM interface).
+#define YSDM_REG_INT_CMPL_PEND_EMPTY                                                                         0xf90d00UL //Access:R    DataWidth:0x1    // Internal write completion pending empty in internal write block.
+#define YSDM_REG_INT_CPRM_PEND_EMPTY                                                                         0xf90d04UL //Access:R    DataWidth:0x1    // Internal write completion parameter pending empty in internal write block.
+#define YSDM_REG_QUEUE_EMPTY                                                                                 0xf90d08UL //Access:R    DataWidth:0x9    // Input queue fifo empty in sdm_inp block.
+#define YSDM_REG_DELAY_FIFO_EMPTY                                                                            0xf90d0cUL //Access:R    DataWidth:0x1    // Delay FIFO  empty in sdm_inp block.
+#define YSDM_REG_TIMERS_PEND_EMPTY                                                                           0xf90d10UL //Access:R    DataWidth:0x1    // Pending FIFO  empty in sdm_timers block.
+#define YSDM_REG_TIMERS_ADDR_EMPTY                                                                           0xf90d14UL //Access:R    DataWidth:0x1    // Address FIFO  empty in sdm_timers block.
+#define YSDM_REG_RSP_PXP_RDATA_EMPTY                                                                         0xf90d18UL //Access:R    DataWidth:0x1    // PXP rd_data fifo  empty in sdm_dma_rsp block.
+#define YSDM_REG_RSP_BRB_RDATA_EMPTY                                                                         0xf90d1cUL //Access:R    DataWidth:0x1    // BRB read data fifo  empty in sdm_dma_rsp block.
+#define YSDM_REG_RSP_INT_RAM_RDATA_EMPTY                                                                     0xf90d20UL //Access:R    DataWidth:0x1    // Int_ram rd_data fifo  empty in sdm_dma_rsp block.
+#define YSDM_REG_RSP_BRB_PEND_EMPTY                                                                          0xf90d24UL //Access:R    DataWidth:0x1    // BRB pending fifo  empty in sdm_dma_rsp block.
+#define YSDM_REG_RSP_INT_RAM_PEND_EMPTY                                                                      0xf90d28UL //Access:R    DataWidth:0x1    // Int_ram pending fifo  empty in sdm_dma_rsp block.
+#define YSDM_REG_DST_PXP_IMMED_EMPTY                                                                         0xf90d2cUL //Access:R    DataWidth:0x1    // PXP immediate fifo empty in sdm_dma_dst block.
+#define YSDM_REG_DST_PXP_DST_PEND_EMPTY                                                                      0xf90d30UL //Access:R    DataWidth:0x1    // PXP destination pending fifo empty in sdm_dma_dst block.
+#define YSDM_REG_DST_PXP_SRC_PEND_EMPTY                                                                      0xf90d34UL //Access:R    DataWidth:0x1    // PXP source pending fifo empty in sdm_dma_dst block.
+#define YSDM_REG_DST_BRB_SRC_PEND_EMPTY                                                                      0xf90d38UL //Access:R    DataWidth:0x1    // BRB source pending fifo empty in sdm_dma_dst block.
+#define YSDM_REG_DST_BRB_SRC_ADDR_EMPTY                                                                      0xf90d3cUL //Access:R    DataWidth:0x1    // BRB source address fifo empty in sdm_dma_dst block.
+#define YSDM_REG_DST_PXP_LINK_EMPTY                                                                          0xf90d40UL //Access:R    DataWidth:0x1    // PXP link list empty in sdm_dma_dst block.
+#define YSDM_REG_DST_INT_RAM_WAIT_EMPTY                                                                      0xf90d44UL //Access:R    DataWidth:0x1    // Int_ram_wait fifo empty in sdm_dma_dst block.
+#define YSDM_REG_DST_PAS_BUF_WAIT_EMPTY                                                                      0xf90d48UL //Access:R    DataWidth:0x1    // Pas_buf_wait fifo empty in sdm_dma_dst block.
+#define YSDM_REG_SH_DELAY_EMPTY                                                                              0xf90d4cUL //Access:R    DataWidth:0x1    // Shared delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.
+#define YSDM_REG_CM_DELAY_EMPTY                                                                              0xf90d50UL //Access:R    DataWidth:0x1    // CM delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.
+#define YSDM_REG_CMSG_QUE_EMPTY                                                                              0xf90d54UL //Access:R    DataWidth:0x1    // Completion message queue fifo empty in sdm_dma_dst block.
+#define YSDM_REG_CCFC_LOAD_PEND_EMPTY                                                                        0xf90d58UL //Access:R    DataWidth:0x1    // CCFC load pending fifo empty in sdm_ccfc block.
+#define YSDM_REG_TCFC_LOAD_PEND_EMPTY                                                                        0xf90d5cUL //Access:R    DataWidth:0x1    // TCFC load pending fifo empty in sdm_tcfc block.
+#define YSDM_REG_ASYNC_HOST_EMPTY                                                                            0xf90d60UL //Access:R    DataWidth:0x1    // Async fifo empty in sdm_async block.
+#define YSDM_REG_PRM_FIFO_EMPTY                                                                              0xf90d64UL //Access:R    DataWidth:0x1    // PRM FIFO empty in sdm_prm_if block.
+#define YSDM_REG_RMT_XCM_FIFO_EMPTY_K2_E5                                                                    0xf90d68UL //Access:R    DataWidth:0x1    // Remote XCM FIFO empty (exist only within MSDM => XCM path).
+#define YSDM_REG_RMT_YCM_FIFO_EMPTY_K2_E5                                                                    0xf90d6cUL //Access:R    DataWidth:0x1    // Remote YCM FIFO empty (exist only within MSDM => YCM path).
+#define YSDM_REG_DBG_OUT_DATA                                                                                0xf90e00UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define YSDM_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define YSDM_REG_DBG_OUT_VALID                                                                               0xf90e20UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define YSDM_REG_DBG_OUT_FRAME                                                                               0xf90e24UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define YSDM_REG_DBG_SELECT                                                                                  0xf90e28UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define YSDM_REG_DBG_DWORD_ENABLE                                                                            0xf90e2cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define YSDM_REG_DBG_SHIFT                                                                                   0xf90e30UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define YSDM_REG_DBG_FORCE_VALID                                                                             0xf90e34UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define YSDM_REG_DBG_FORCE_FRAME                                                                             0xf90e38UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define YSDM_REG_ASYNC_FIFO                                                                                  0xf92000UL //Access:WB_R DataWidth:0x49   // Provides read-only access of the PXP-Async input FIFO. Intended for debug purposes.
+#define YSDM_REG_ASYNC_FIFO_SIZE                                                                             116
+#define YSDM_REG_IMMED_FIFO                                                                                  0xf92400UL //Access:WB_R DataWidth:0x40   // Provides read-only access of the immediate data FIFO. Intended for debug purposes.
+#define YSDM_REG_IMMED_FIFO_SIZE                                                                             38
+#define YSDM_REG_BRB_FIFO                                                                                    0xf92800UL //Access:WB_R DataWidth:0x86   // Provides read-only access of the BRB response FIFO. Intended for debug purposes.
+#define YSDM_REG_BRB_FIFO_SIZE                                                                               152
+#define YSDM_REG_PXP_FIFO                                                                                    0xf92c00UL //Access:WB_R DataWidth:0x4a   // Provides read-only access of the PXP response FIFO. Intended for debug purposes.
+#define YSDM_REG_PXP_FIFO_SIZE                                                                               76
+#define YSDM_REG_INT_RAM_FIFO                                                                                0xf93000UL //Access:WB_R DataWidth:0x41   // Provides read-only access of the internal RAM response FIFO. Intended for debug purposes.
+#define YSDM_REG_INT_RAM_FIFO_SIZE                                                                           76
+#define YSDM_REG_DPM_FIFO                                                                                    0xf93400UL //Access:WB_R DataWidth:0x51   // Provides read-only access of the DORQ DPM input FIFO. Intended for debug purposes.
+#define YSDM_REG_DPM_FIFO_SIZE                                                                               172
+#define YSDM_REG_EXT_OVERFLOW                                                                                0xf93800UL //Access:WB_R DataWidth:0x4b   // Provides read-only access of the external store overflow FIFO. Intended for debug purposes.
+#define YSDM_REG_EXT_OVERFLOW_SIZE                                                                           36
+#define YSDM_REG_PRM_FIFO                                                                                    0xf93c00UL //Access:WB_R DataWidth:0x41   // Provides read-only access of the PRM completion input FIFO. Intended for debug purposes.
+#define YSDM_REG_PRM_FIFO_SIZE                                                                               84
+#define YSDM_REG_TIMERS                                                                                      0xf94000UL //Access:WB   DataWidth:0x3a   // Provides memory-mapped read/write access to the timers' memory. Intended for debug purposes.
+#define YSDM_REG_TIMERS_SIZE                                                                                 28
+#define YSDM_REG_INP_QUEUE                                                                                   0xf95000UL //Access:WB   DataWidth:0x40   // Input queue memory. Access only for debugging.
+#define YSDM_REG_INP_QUEUE_SIZE                                                                              344
+#define YSDM_REG_CMSG_QUE                                                                                    0xf98000UL //Access:WB   DataWidth:0x40   // CM queue memory. Access only for debugging.
+#define YSDM_REG_CMSG_QUE_SIZE                                                                               192
+#define PSDM_REG_ENABLE_IN1                                                                                  0xfa0004UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define PSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN                                                                (0x1<<0) // Enable for input command from STORM.
+  #define PSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN_SHIFT                                                          0
+  #define PSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN                                                             (0x1<<1) // Enable for input data from internal ram interface in DMA_RSP block.
+  #define PSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN_SHIFT                                                       1
+  #define PSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN                                                             (0x1<<2) // Enable for input done from internal ram interface in DMA_RSP block.
+  #define PSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN_SHIFT                                                       2
+  #define PSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN                                                             (0x1<<3) // Enable for input full from internal ram interface in DMA_RSP block.
+  #define PSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN_SHIFT                                                       3
+  #define PSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN                                                             (0x1<<4) // Enable for input done from passive buffer interface in DMA_RSP block.
+  #define PSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN_SHIFT                                                       4
+  #define PSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN                                                             (0x1<<5) // Enable for input full from passive buffer interface in DMA_RSP block.
+  #define PSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN_SHIFT                                                       5
+  #define PSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN                                                                 (0x1<<6) // Enable for input done from pxp-HW interface in DMA_DST block.
+  #define PSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN_SHIFT                                                           6
+  #define PSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN                                                                 (0x1<<7) // Enable for input full from pxp-HW interface in DMA_DST block.
+  #define PSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN_SHIFT                                                           7
+  #define PSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN                                                                 (0x1<<8) // Enable for input data from pxp-HW interface in DMA_RSP block.
+  #define PSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN_SHIFT                                                           8
+  #define PSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN                                                              (0x1<<9) // Enable for input ack from pxp-internal write for SDM_INT block.
+  #define PSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN_SHIFT                                                        9
+  #define PSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN                                                                  (0x1<<10) // Enable for input acknowledge to credit counter from pxp_HW interface.
+  #define PSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN_SHIFT                                                            10
+  #define PSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN                                                                 (0x1<<11) // Enable for input data from BRB interface in DMA_RSP block.
+  #define PSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN_SHIFT                                                           11
+  #define PSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN                                                                  (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
+  #define PSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN_SHIFT                                                            12
+  #define PSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN                                                                  (0x1<<13) // Enable for input completion message from PRM in prm_if block.
+  #define PSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN_SHIFT                                                            13
+  #define PSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN                                                            (0x1<<14) // Enable for input ack to CCFC load credit counter.
+  #define PSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN_SHIFT                                                      14
+  #define PSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN                                                            (0x1<<15) // Enable for input ack to TCFC load credit counter.
+  #define PSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN_SHIFT                                                      15
+  #define PSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN                                                            (0x1<<16) // Enable for input response from CCFC in CCFC block.
+  #define PSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN_SHIFT                                                      16
+  #define PSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN                                                              (0x1<<17) // Enable for input ack to CCFC credit counter on the A/C interface.
+  #define PSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN_SHIFT                                                        17
+  #define PSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN                                                              (0x1<<18) // Enable for input ack to TCFC credit counter on the A/C interface.
+  #define PSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN_SHIFT                                                        18
+  #define PSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN                                                           (0x1<<19) // Enable for input full from qm in SDM_INP block.
+  #define PSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN_SHIFT                                                     19
+#define PSDM_REG_ENABLE_IN2                                                                                  0xfa0008UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define PSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN                                                            (0x1<<0) // Enable for input response from TCFC in TCFC block.
+  #define PSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN_SHIFT                                                      0
+  #define PSDM_REG_ENABLE_IN2_CM_ACK_IN_EN                                                                   (0x1<<1) // Enable for input acknowledge from Cm  in SDM_CM block.
+  #define PSDM_REG_ENABLE_IN2_CM_ACK_IN_EN_SHIFT                                                             1
+  #define PSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN                                                                 (0x1<<2) // Enable for input DPM requests in SDM_DORQ block.
+  #define PSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN_SHIFT                                                           2
+#define PSDM_REG_ENABLE_OUT1                                                                                 0xfa000cUL //Access:RW   DataWidth:0x15   // Multi Field Register.
+  #define PSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN                                                                (0x1<<0) // Enable for output request to pxp internal write for SDM_INT block.
+  #define PSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN_SHIFT                                                          0
+  #define PSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN                                                             (0x1<<1) // Enable for output thread ready to the SEMI.
+  #define PSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN_SHIFT                                                       1
+  #define PSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN                                                             (0x1<<2) // Enable the output thread release to the SEMI.
+  #define PSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN_SHIFT                                                       2
+  #define PSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN                                                              (0x1<<3) // Enable for output load request to CCFC.
+  #define PSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN_SHIFT                                                        3
+  #define PSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN                                                              (0x1<<4) // Enable for output load request to TCFC.
+  #define PSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN_SHIFT                                                        4
+  #define PSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN                                                                (0x1<<5) // Enable for output increment to CCFC activity counter.
+  #define PSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN_SHIFT                                                          5
+  #define PSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN                                                                (0x1<<6) // Enable for output decrement to TCFC activity counter.
+  #define PSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN_SHIFT                                                          6
+  #define PSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN                                                                (0x1<<7) // Enable for output data to pxp-HW interface in DMA_REQ block.
+  #define PSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN_SHIFT                                                          7
+  #define PSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN                                                                (0x1<<8) // Enable for output request to BRB interface in DMA_REQ block.
+  #define PSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN_SHIFT                                                          8
+  #define PSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN                                                                (0x1<<9) // Enable for output write to int_ram in DMA_DST block.
+  #define PSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN_SHIFT                                                          9
+  #define PSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN                                                                (0x1<<10) // Enable for output write topassive buffer in DMA_DST block.
+  #define PSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN_SHIFT                                                          10
+  #define PSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN                                                              (0x1<<11) // Enable for output write to pxp async in DMA_DST block.
+  #define PSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN_SHIFT                                                        11
+  #define PSDM_REG_ENABLE_OUT1_PXP_OUT_EN                                                                    (0x1<<12) // Enable for output write to pxp  in DMA_DST block.
+  #define PSDM_REG_ENABLE_OUT1_PXP_OUT_EN_SHIFT                                                              12
+  #define PSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN                                                               (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
+  #define PSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN_SHIFT                                                         13
+  #define PSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN                                                               (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
+  #define PSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN_SHIFT                                                         14
+  #define PSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN                                                               (0x1<<15) // Enable for output external full to SEMI block.
+  #define PSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN_SHIFT                                                         15
+  #define PSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN                                                           (0x1<<16) // Enable for output done to async PXP host IF.
+  #define PSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN_SHIFT                                                     16
+  #define PSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN                                                           (0x1<<17) // Enable the output done (ack) to PRM.
+  #define PSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN_SHIFT                                                     17
+  #define PSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN                                                                 (0x1<<18) // Enable for output message to CM in SDM_CM block.
+  #define PSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN_SHIFT                                                           18
+  #define PSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN                                                           (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
+  #define PSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN_SHIFT                                                     19
+  #define PSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN                                                           (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
+  #define PSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN_SHIFT                                                     20
+#define PSDM_REG_ENABLE_OUT2                                                                                 0xfa0010UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define PSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN                                                              (0x1<<0) // Enable for output command to qm in SDM_INP block.
+  #define PSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN_SHIFT                                                        0
+  #define PSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN                                                               (0x1<<1) // Enable for VF/PF error valid in DMA_DST block.
+  #define PSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN_SHIFT                                                         1
+  #define PSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN                                                          (0x1<<2) // Enable for DPM request done output in SDM_DORQ block.
+  #define PSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN_SHIFT                                                    2
+#define PSDM_REG_DISABLE_ENGINE                                                                              0xfa0014UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define PSDM_REG_DISABLE_ENGINE_DISABLE_DMA                                                                (0x1<<0) // This bit should be set to disable the DMA exectuion engine from processing DMA commands.
+  #define PSDM_REG_DISABLE_ENGINE_DISABLE_DMA_SHIFT                                                          0
+  #define PSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS                                                             (0x1<<1) // This bit should be set to disable the timers' exectuion engine from processing timers' commands.
+  #define PSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS_SHIFT                                                       1
+  #define PSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD                                                          (0x1<<2) // This bit should be set to disable the CCFC exectuion engine from processing CCFC load commands.
+  #define PSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD_SHIFT                                                    2
+  #define PSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD                                                          (0x1<<3) // This bit should be set to disable the TCFC exectuion engine from processing TCFC load commands.
+  #define PSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD_SHIFT                                                    3
+  #define PSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR                                                             (0x1<<4) // This bit should be set to disable the internal write exectuion engine from processing Internal write commands.
+  #define PSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR_SHIFT                                                       4
+  #define PSDM_REG_DISABLE_ENGINE_DISABLE_NOP                                                                (0x1<<5) // This bit should be set to disable the SDM NOP exectuion engine from processing NOP commands.
+  #define PSDM_REG_DISABLE_ENGINE_DISABLE_NOP_SHIFT                                                          5
+  #define PSDM_REG_DISABLE_ENGINE_DISABLE_GRC                                                                (0x1<<6) // This bit should be set to disable the GRC master exectuion engine from processing GRC master commands.
+  #define PSDM_REG_DISABLE_ENGINE_DISABLE_GRC_SHIFT                                                          6
+  #define PSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC                                                              (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Async requests.
+  #define PSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC_SHIFT                                                        7
+  #define PSDM_REG_DISABLE_ENGINE_DISABLE_PRM                                                                (0x1<<8) // This bit should be set to disable the PRM interface from processing PRM completion commands.
+  #define PSDM_REG_DISABLE_ENGINE_DISABLE_PRM_SHIFT                                                          8
+  #define PSDM_REG_DISABLE_ENGINE_DISABLE_DORQ                                                               (0x1<<9) // This bit should be set to disable the DORQ DPM interface from processing DPM commands.
+  #define PSDM_REG_DISABLE_ENGINE_DISABLE_DORQ_SHIFT                                                         9
+#define PSDM_REG_INT_STS                                                                                     0xfa0040UL //Access:R    DataWidth:0x1c   // Multi Field Register.
+  #define PSDM_REG_INT_STS_ADDRESS_ERROR                                                                     (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSDM_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                               0
+  #define PSDM_REG_INT_STS_INP_QUEUE_ERROR                                                                   (0x1<<1) // Indicates that one of the input queues had a FIFO error.
+  #define PSDM_REG_INT_STS_INP_QUEUE_ERROR_SHIFT                                                             1
+  #define PSDM_REG_INT_STS_DELAY_FIFO_ERROR                                                                  (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
+  #define PSDM_REG_INT_STS_DELAY_FIFO_ERROR_SHIFT                                                            2
+  #define PSDM_REG_INT_STS_ASYNC_HOST_ERROR                                                                  (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
+  #define PSDM_REG_INT_STS_ASYNC_HOST_ERROR_SHIFT                                                            3
+  #define PSDM_REG_INT_STS_PRM_FIFO_ERROR                                                                    (0x1<<4) // FIFO in PRM interface sub-module reported an error.
+  #define PSDM_REG_INT_STS_PRM_FIFO_ERROR_SHIFT                                                              4
+  #define PSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR                                                              (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
+  #define PSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR_SHIFT                                                        5
+  #define PSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR                                                              (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
+  #define PSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR_SHIFT                                                        6
+  #define PSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR                                                            (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
+  #define PSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR_SHIFT                                                      7
+  #define PSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR                                                            (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
+  #define PSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR_SHIFT                                                      8
+  #define PSDM_REG_INT_STS_DST_PXP_IMMED_ERROR                                                               (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
+  #define PSDM_REG_INT_STS_DST_PXP_IMMED_ERROR_SHIFT                                                         9
+  #define PSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR                                                            (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
+  #define PSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR_SHIFT                                                      10
+  #define PSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR                                                            (0x1<<11) // BRB src pend fifo error in DMA_DST block.
+  #define PSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR_SHIFT                                                      11
+  #define PSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR                                                            (0x1<<12) // BRB src addr fifo error in DMA_DST block.
+  #define PSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR_SHIFT                                                      12
+  #define PSDM_REG_INT_STS_RSP_BRB_PEND_ERROR                                                                (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
+  #define PSDM_REG_INT_STS_RSP_BRB_PEND_ERROR_SHIFT                                                          13
+  #define PSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR                                                            (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
+  #define PSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR_SHIFT                                                      14
+  #define PSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR                                                             (0x1<<15) // Read data firo in DMA_RSP block for BRB.
+  #define PSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR_SHIFT                                                       15
+  #define PSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR                                                         (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
+  #define PSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                                   16
+  #define PSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR                                                             (0x1<<17) // PXP read data fifo error in DMA_RSP block.
+  #define PSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR_SHIFT                                                       17
+  #define PSDM_REG_INT_STS_CM_DELAY_ERROR                                                                    (0x1<<18) // Delay CM fifo error in CM block.
+  #define PSDM_REG_INT_STS_CM_DELAY_ERROR_SHIFT                                                              18
+  #define PSDM_REG_INT_STS_SH_DELAY_ERROR                                                                    (0x1<<19) // Delay shared fifo error in CM block.
+  #define PSDM_REG_INT_STS_SH_DELAY_ERROR_SHIFT                                                              19
+  #define PSDM_REG_INT_STS_CMPL_PEND_ERROR                                                                   (0x1<<20) // Error in completion pending FIFO in internal write block.
+  #define PSDM_REG_INT_STS_CMPL_PEND_ERROR_SHIFT                                                             20
+  #define PSDM_REG_INT_STS_CPRM_PEND_ERROR                                                                   (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
+  #define PSDM_REG_INT_STS_CPRM_PEND_ERROR_SHIFT                                                             21
+  #define PSDM_REG_INT_STS_TIMER_ADDR_ERROR                                                                  (0x1<<22) // Address fifo error in timer block.
+  #define PSDM_REG_INT_STS_TIMER_ADDR_ERROR_SHIFT                                                            22
+  #define PSDM_REG_INT_STS_TIMER_PEND_ERROR                                                                  (0x1<<23) // Pending fifo error in timer block.
+  #define PSDM_REG_INT_STS_TIMER_PEND_ERROR_SHIFT                                                            23
+  #define PSDM_REG_INT_STS_DORQ_DPM_ERROR                                                                    (0x1<<24) // Dpm fifo error in dorq I/F block.
+  #define PSDM_REG_INT_STS_DORQ_DPM_ERROR_SHIFT                                                              24
+  #define PSDM_REG_INT_STS_DST_PXP_DONE_ERROR                                                                (0x1<<25) // PXP done fifo error in DMA_dst block.
+  #define PSDM_REG_INT_STS_DST_PXP_DONE_ERROR_SHIFT                                                          25
+  #define PSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR_K2_E5                                                        (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define PSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                                  26
+  #define PSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_K2_E5                                                        (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define PSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                                  27
+#define PSDM_REG_INT_MASK                                                                                    0xfa0044UL //Access:RW   DataWidth:0x1c   // Multi Field Register.
+  #define PSDM_REG_INT_MASK_ADDRESS_ERROR                                                                    (0x1<<0) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.ADDRESS_ERROR .
+  #define PSDM_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                              0
+  #define PSDM_REG_INT_MASK_INP_QUEUE_ERROR                                                                  (0x1<<1) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.INP_QUEUE_ERROR .
+  #define PSDM_REG_INT_MASK_INP_QUEUE_ERROR_SHIFT                                                            1
+  #define PSDM_REG_INT_MASK_DELAY_FIFO_ERROR                                                                 (0x1<<2) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DELAY_FIFO_ERROR .
+  #define PSDM_REG_INT_MASK_DELAY_FIFO_ERROR_SHIFT                                                           2
+  #define PSDM_REG_INT_MASK_ASYNC_HOST_ERROR                                                                 (0x1<<3) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.ASYNC_HOST_ERROR .
+  #define PSDM_REG_INT_MASK_ASYNC_HOST_ERROR_SHIFT                                                           3
+  #define PSDM_REG_INT_MASK_PRM_FIFO_ERROR                                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.PRM_FIFO_ERROR .
+  #define PSDM_REG_INT_MASK_PRM_FIFO_ERROR_SHIFT                                                             4
+  #define PSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR                                                             (0x1<<5) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.CCFC_LOAD_PEND_ERROR .
+  #define PSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR_SHIFT                                                       5
+  #define PSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR                                                             (0x1<<6) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.TCFC_LOAD_PEND_ERROR .
+  #define PSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR_SHIFT                                                       6
+  #define PSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR                                                           (0x1<<7) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DST_INT_RAM_WAIT_ERROR .
+  #define PSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR_SHIFT                                                     7
+  #define PSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR                                                           (0x1<<8) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DST_PAS_BUF_WAIT_ERROR .
+  #define PSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR_SHIFT                                                     8
+  #define PSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR                                                              (0x1<<9) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DST_PXP_IMMED_ERROR .
+  #define PSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR_SHIFT                                                        9
+  #define PSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR                                                           (0x1<<10) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DST_PXP_DST_PEND_ERROR .
+  #define PSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR_SHIFT                                                     10
+  #define PSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR                                                           (0x1<<11) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DST_BRB_SRC_PEND_ERROR .
+  #define PSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR_SHIFT                                                     11
+  #define PSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR                                                           (0x1<<12) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DST_BRB_SRC_ADDR_ERROR .
+  #define PSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR_SHIFT                                                     12
+  #define PSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR                                                               (0x1<<13) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.RSP_BRB_PEND_ERROR .
+  #define PSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR_SHIFT                                                         13
+  #define PSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR                                                           (0x1<<14) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.RSP_INT_RAM_PEND_ERROR .
+  #define PSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR_SHIFT                                                     14
+  #define PSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR                                                            (0x1<<15) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.RSP_BRB_RD_DATA_ERROR .
+  #define PSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR_SHIFT                                                      15
+  #define PSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR                                                        (0x1<<16) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.RSP_INT_RAM_RD_DATA_ERROR .
+  #define PSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                                  16
+  #define PSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR                                                            (0x1<<17) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.RSP_PXP_RD_DATA_ERROR .
+  #define PSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR_SHIFT                                                      17
+  #define PSDM_REG_INT_MASK_CM_DELAY_ERROR                                                                   (0x1<<18) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.CM_DELAY_ERROR .
+  #define PSDM_REG_INT_MASK_CM_DELAY_ERROR_SHIFT                                                             18
+  #define PSDM_REG_INT_MASK_SH_DELAY_ERROR                                                                   (0x1<<19) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.SH_DELAY_ERROR .
+  #define PSDM_REG_INT_MASK_SH_DELAY_ERROR_SHIFT                                                             19
+  #define PSDM_REG_INT_MASK_CMPL_PEND_ERROR                                                                  (0x1<<20) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.CMPL_PEND_ERROR .
+  #define PSDM_REG_INT_MASK_CMPL_PEND_ERROR_SHIFT                                                            20
+  #define PSDM_REG_INT_MASK_CPRM_PEND_ERROR                                                                  (0x1<<21) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.CPRM_PEND_ERROR .
+  #define PSDM_REG_INT_MASK_CPRM_PEND_ERROR_SHIFT                                                            21
+  #define PSDM_REG_INT_MASK_TIMER_ADDR_ERROR                                                                 (0x1<<22) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.TIMER_ADDR_ERROR .
+  #define PSDM_REG_INT_MASK_TIMER_ADDR_ERROR_SHIFT                                                           22
+  #define PSDM_REG_INT_MASK_TIMER_PEND_ERROR                                                                 (0x1<<23) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.TIMER_PEND_ERROR .
+  #define PSDM_REG_INT_MASK_TIMER_PEND_ERROR_SHIFT                                                           23
+  #define PSDM_REG_INT_MASK_DORQ_DPM_ERROR                                                                   (0x1<<24) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DORQ_DPM_ERROR .
+  #define PSDM_REG_INT_MASK_DORQ_DPM_ERROR_SHIFT                                                             24
+  #define PSDM_REG_INT_MASK_DST_PXP_DONE_ERROR                                                               (0x1<<25) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DST_PXP_DONE_ERROR .
+  #define PSDM_REG_INT_MASK_DST_PXP_DONE_ERROR_SHIFT                                                         25
+  #define PSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR_K2_E5                                                       (0x1<<26) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.XCM_RMT_BUFFER_ERROR .
+  #define PSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                                 26
+  #define PSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_K2_E5                                                       (0x1<<27) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.YCM_RMT_BUFFER_ERROR .
+  #define PSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                                 27
+#define PSDM_REG_INT_STS_WR                                                                                  0xfa0048UL //Access:WR   DataWidth:0x1c   // Multi Field Register.
+  #define PSDM_REG_INT_STS_WR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSDM_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                            0
+  #define PSDM_REG_INT_STS_WR_INP_QUEUE_ERROR                                                                (0x1<<1) // Indicates that one of the input queues had a FIFO error.
+  #define PSDM_REG_INT_STS_WR_INP_QUEUE_ERROR_SHIFT                                                          1
+  #define PSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR                                                               (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
+  #define PSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR_SHIFT                                                         2
+  #define PSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR                                                               (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
+  #define PSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR_SHIFT                                                         3
+  #define PSDM_REG_INT_STS_WR_PRM_FIFO_ERROR                                                                 (0x1<<4) // FIFO in PRM interface sub-module reported an error.
+  #define PSDM_REG_INT_STS_WR_PRM_FIFO_ERROR_SHIFT                                                           4
+  #define PSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR                                                           (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
+  #define PSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR_SHIFT                                                     5
+  #define PSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR                                                           (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
+  #define PSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR_SHIFT                                                     6
+  #define PSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR                                                         (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
+  #define PSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR_SHIFT                                                   7
+  #define PSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR                                                         (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
+  #define PSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR_SHIFT                                                   8
+  #define PSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR                                                            (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
+  #define PSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR_SHIFT                                                      9
+  #define PSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR                                                         (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
+  #define PSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR_SHIFT                                                   10
+  #define PSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR                                                         (0x1<<11) // BRB src pend fifo error in DMA_DST block.
+  #define PSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR_SHIFT                                                   11
+  #define PSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR                                                         (0x1<<12) // BRB src addr fifo error in DMA_DST block.
+  #define PSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR_SHIFT                                                   12
+  #define PSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR                                                             (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
+  #define PSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR_SHIFT                                                       13
+  #define PSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR                                                         (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
+  #define PSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR_SHIFT                                                   14
+  #define PSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR                                                          (0x1<<15) // Read data firo in DMA_RSP block for BRB.
+  #define PSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR_SHIFT                                                    15
+  #define PSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR                                                      (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
+  #define PSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                                16
+  #define PSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR                                                          (0x1<<17) // PXP read data fifo error in DMA_RSP block.
+  #define PSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR_SHIFT                                                    17
+  #define PSDM_REG_INT_STS_WR_CM_DELAY_ERROR                                                                 (0x1<<18) // Delay CM fifo error in CM block.
+  #define PSDM_REG_INT_STS_WR_CM_DELAY_ERROR_SHIFT                                                           18
+  #define PSDM_REG_INT_STS_WR_SH_DELAY_ERROR                                                                 (0x1<<19) // Delay shared fifo error in CM block.
+  #define PSDM_REG_INT_STS_WR_SH_DELAY_ERROR_SHIFT                                                           19
+  #define PSDM_REG_INT_STS_WR_CMPL_PEND_ERROR                                                                (0x1<<20) // Error in completion pending FIFO in internal write block.
+  #define PSDM_REG_INT_STS_WR_CMPL_PEND_ERROR_SHIFT                                                          20
+  #define PSDM_REG_INT_STS_WR_CPRM_PEND_ERROR                                                                (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
+  #define PSDM_REG_INT_STS_WR_CPRM_PEND_ERROR_SHIFT                                                          21
+  #define PSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR                                                               (0x1<<22) // Address fifo error in timer block.
+  #define PSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR_SHIFT                                                         22
+  #define PSDM_REG_INT_STS_WR_TIMER_PEND_ERROR                                                               (0x1<<23) // Pending fifo error in timer block.
+  #define PSDM_REG_INT_STS_WR_TIMER_PEND_ERROR_SHIFT                                                         23
+  #define PSDM_REG_INT_STS_WR_DORQ_DPM_ERROR                                                                 (0x1<<24) // Dpm fifo error in dorq I/F block.
+  #define PSDM_REG_INT_STS_WR_DORQ_DPM_ERROR_SHIFT                                                           24
+  #define PSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR                                                             (0x1<<25) // PXP done fifo error in DMA_dst block.
+  #define PSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR_SHIFT                                                       25
+  #define PSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR_K2_E5                                                     (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define PSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                               26
+  #define PSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_K2_E5                                                     (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define PSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                               27
+#define PSDM_REG_INT_STS_CLR                                                                                 0xfa004cUL //Access:RC   DataWidth:0x1c   // Multi Field Register.
+  #define PSDM_REG_INT_STS_CLR_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSDM_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                           0
+  #define PSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR                                                               (0x1<<1) // Indicates that one of the input queues had a FIFO error.
+  #define PSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR_SHIFT                                                         1
+  #define PSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR                                                              (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
+  #define PSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR_SHIFT                                                        2
+  #define PSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR                                                              (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
+  #define PSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR_SHIFT                                                        3
+  #define PSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR                                                                (0x1<<4) // FIFO in PRM interface sub-module reported an error.
+  #define PSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR_SHIFT                                                          4
+  #define PSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR                                                          (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
+  #define PSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR_SHIFT                                                    5
+  #define PSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR                                                          (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
+  #define PSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR_SHIFT                                                    6
+  #define PSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR                                                        (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
+  #define PSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR_SHIFT                                                  7
+  #define PSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR                                                        (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
+  #define PSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR_SHIFT                                                  8
+  #define PSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR                                                           (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
+  #define PSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR_SHIFT                                                     9
+  #define PSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR                                                        (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
+  #define PSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR_SHIFT                                                  10
+  #define PSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR                                                        (0x1<<11) // BRB src pend fifo error in DMA_DST block.
+  #define PSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR_SHIFT                                                  11
+  #define PSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR                                                        (0x1<<12) // BRB src addr fifo error in DMA_DST block.
+  #define PSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR_SHIFT                                                  12
+  #define PSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR                                                            (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
+  #define PSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR_SHIFT                                                      13
+  #define PSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR                                                        (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
+  #define PSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR_SHIFT                                                  14
+  #define PSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR                                                         (0x1<<15) // Read data firo in DMA_RSP block for BRB.
+  #define PSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR_SHIFT                                                   15
+  #define PSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR                                                     (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
+  #define PSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                               16
+  #define PSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR                                                         (0x1<<17) // PXP read data fifo error in DMA_RSP block.
+  #define PSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR_SHIFT                                                   17
+  #define PSDM_REG_INT_STS_CLR_CM_DELAY_ERROR                                                                (0x1<<18) // Delay CM fifo error in CM block.
+  #define PSDM_REG_INT_STS_CLR_CM_DELAY_ERROR_SHIFT                                                          18
+  #define PSDM_REG_INT_STS_CLR_SH_DELAY_ERROR                                                                (0x1<<19) // Delay shared fifo error in CM block.
+  #define PSDM_REG_INT_STS_CLR_SH_DELAY_ERROR_SHIFT                                                          19
+  #define PSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR                                                               (0x1<<20) // Error in completion pending FIFO in internal write block.
+  #define PSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR_SHIFT                                                         20
+  #define PSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR                                                               (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
+  #define PSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR_SHIFT                                                         21
+  #define PSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR                                                              (0x1<<22) // Address fifo error in timer block.
+  #define PSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR_SHIFT                                                        22
+  #define PSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR                                                              (0x1<<23) // Pending fifo error in timer block.
+  #define PSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR_SHIFT                                                        23
+  #define PSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR                                                                (0x1<<24) // Dpm fifo error in dorq I/F block.
+  #define PSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR_SHIFT                                                          24
+  #define PSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR                                                            (0x1<<25) // PXP done fifo error in DMA_dst block.
+  #define PSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR_SHIFT                                                      25
+  #define PSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR_K2_E5                                                    (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define PSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                              26
+  #define PSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_K2_E5                                                    (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define PSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                              27
+#define PSDM_REG_PRTY_MASK_H_0_BB_K2                                                                         0xfa0204UL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define PSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2                                                     (0x1<<0) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define PSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2_SHIFT                                               0
+  #define PSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2                                                     (0x1<<1) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define PSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2_SHIFT                                               1
+  #define PSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2                                                     (0x1<<2) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define PSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2_SHIFT                                               2
+  #define PSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2                                                     (0x1<<3) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define PSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT                                               3
+  #define PSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                     (0x1<<4) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define PSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                               4
+  #define PSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2                                                     (0x1<<5) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define PSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2_SHIFT                                               5
+  #define PSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                     (0x1<<6) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define PSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                               6
+  #define PSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                     (0x1<<7) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define PSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                               7
+  #define PSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                     (0x1<<8) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define PSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                               8
+#define PSDM_REG_MEM_ECC_EVENTS_BB_K2                                                                        0xfa0210UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define PSDM_REG_TIMER_TICK                                                                                  0xfa0400UL //Access:RW   DataWidth:0x20   // Defines the number of system clock cycles that are used to define a timers clock tick cycle. Note: The minimal legal value for this register is 25, lower values can cause timers functionality issues.
+#define PSDM_REG_TIMERS_TICK_ENABLE                                                                          0xfa0404UL //Access:RW   DataWidth:0x1    // Enable for tick counter.
+#define PSDM_REG_OPERATION_GEN                                                                               0xfa0408UL //Access:W    DataWidth:0x14   // This register is used to assert a completion operation of choice; It includes the following completion fields: bits 19:16 are Trig; bits 15:0 are CompParams. Note that trigger types 3,5 or 8 are not supported by this interface as they require a completion message. If there is an attempt to assert an OperationGen with Trig = 3,5 or 8, the operation will be voided.
+#define PSDM_REG_GRC_PRIVILEGE_LEVEL                                                                         0xfa040cUL //Access:RW   DataWidth:0x2    // This register defines the PRV (privilege level) field within the FID structure of the SDM GRC master request.
+#define PSDM_REG_CM_MSG_CNT_ADDRESS                                                                          0xfa0410UL //Access:RW   DataWidth:0xf    // The internal RAM address for storing the shadow of the CM completion message counter.
+#define PSDM_REG_DORQ_DPM_START_ADDR                                                                         0xfa0414UL //Access:RW   DataWidth:0xf    // The start address in the internal RAM for DORQ DPM messages.
+#define PSDM_REG_RR_COMPLETE_REQ                                                                             0xfa0418UL //Access:R    DataWidth:0xa    // Provides read access to the round robin arbiter used for all completion write requests  in the completion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b7-PRM interface; b8-CCFC load; b9-TCFC load.
+#define PSDM_REG_RR_PTR_REQ                                                                                  0xfa041cUL //Access:R    DataWidth:0x9    // Provides read access to the round robin arbiter for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-int_wr; b7-prm; b8-grc_master.
+#define PSDM_REG_INT_RAM_RR_REQ                                                                              0xfa0420UL //Access:R    DataWidth:0x4    // Provides read access to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination;b2-PXP source/destination;b3-BRB source.
+#define PSDM_REG_INP_QUEUE_ERR_VECT                                                                          0xfa0424UL //Access:R    DataWidth:0x9    // This register is intended to be read in the event of an inp_queue_error interrupt.  It contains a vector with a bit per input queue. Clearing the interrupt causes this vector to be cleared. Errors on multiple FIFOs will be aggregated between interrupt clear requests.
+#define PSDM_REG_ASYNC_CMSG_ALLOC_LIMIT                                                                      0xfa0428UL //Access:RW   DataWidth:0x5    // This register defines the maximum number of completion messages that can be allocated to PXP-Async transactions at any given time. If the PXP-Async interface attempts to reserve beyond this limit, it will be held off until the situation is resolved.
+#define PSDM_REG_ECO_RESERVED                                                                                0xfa042cUL //Access:RW   DataWidth:0x8    // Reserved bits for ECO.
+#define PSDM_REG_INIT_CREDIT_PXP                                                                             0xfa0500UL //Access:RW   DataWidth:0x3    // The initial number of messages that can be sent to the pxp interface without receiving any ACK.
+#define PSDM_REG_INIT_CREDIT_PCI                                                                             0xfa0504UL //Access:RW   DataWidth:0x2    // The initial number of messages that can be sent to the PCI-Switch on the internal write interface without receiving any ACK.
+#define PSDM_REG_INIT_CREDIT_TCFC_AC                                                                         0xfa0508UL //Access:RW   DataWidth:0x4    // The initial number of messages that can be sent to the TCFC activity counters interface without receiving any ACK.
+#define PSDM_REG_INIT_CREDIT_CCFC_AC                                                                         0xfa050cUL //Access:RW   DataWidth:0x4    // The initial number of messages that can be sent to the CCFC activity counters interface without receiving any ACK.
+#define PSDM_REG_INIT_CREDIT_CM                                                                              0xfa0510UL //Access:RW   DataWidth:0x4    // The initial number of cycles that can be sent to the CM interface without receiving any ACK in CM block.
+#define PSDM_REG_INIT_CREDIT_CM_RMT_E5                                                                       0xfa0520UL //Access:RW   DataWidth:0x4    // The initial number of cycles that can be sent to a remote CM interface without receiving any ACK in CM block.
+#define PSDM_REG_INIT_CREDIT_CM_RMT_SIZE                                                                     2
+#define PSDM_REG_NUM_OF_DMA_CMD                                                                              0xfa0600UL //Access:RC   DataWidth:0x20   // The number of SDM DMA commands executed.
+#define PSDM_REG_NUM_OF_TIMERS_CMD                                                                           0xfa0604UL //Access:RC   DataWidth:0x20   // The number of SDM timers commands executed.
+#define PSDM_REG_NUM_OF_CCFC_LD_CMD                                                                          0xfa0608UL //Access:RC   DataWidth:0x20   // The number of SDM CCFC load commands executed.
+#define PSDM_REG_NUM_OF_CCFC_AC_CMD                                                                          0xfa060cUL //Access:RC   DataWidth:0x20   // The number of SDM CCFC activity counter commands executed.
+#define PSDM_REG_NUM_OF_TCFC_LD_CMD                                                                          0xfa0610UL //Access:RC   DataWidth:0x20   // The number of SDM TCFC load commands executed.
+#define PSDM_REG_NUM_OF_TCFC_AC_CMD                                                                          0xfa0614UL //Access:RC   DataWidth:0x20   // The number of SDM TCFC activity counter commands executed.
+#define PSDM_REG_NUM_OF_INT_CMD                                                                              0xfa0618UL //Access:RC   DataWidth:0x20   // The number of SDM internal write commands executed.
+#define PSDM_REG_NUM_OF_NOP_CMD                                                                              0xfa061cUL //Access:RC   DataWidth:0x20   // The number of SDM NOP commands executed.
+#define PSDM_REG_NUM_OF_GRC_CMD                                                                              0xfa0620UL //Access:RC   DataWidth:0x20   // The number of GRC master commands executed.
+#define PSDM_REG_NUM_OF_PRM_REQ                                                                              0xfa0624UL //Access:RC   DataWidth:0x20   // The number of packet end messages received on the PRM completion interface.
+#define PSDM_REG_NUM_OF_PXP_ASYNC_REQ                                                                        0xfa0628UL //Access:RC   DataWidth:0x20   // The number of requests received from the pxp async if.
+#define PSDM_REG_NUM_OF_DPM_REQ                                                                              0xfa062cUL //Access:RC   DataWidth:0x20   // The number of DORQ DPM messages received.
+#define PSDM_REG_BRB_ALMOST_FULL                                                                             0xfa0700UL //Access:RW   DataWidth:0x5    // Almost full signal for read data from BRB in DMA_RSP block.
+#define PSDM_REG_PXP_ALMOST_FULL                                                                             0xfa0704UL //Access:RW   DataWidth:0x4    // Almost full signal for read data from pxp in DMA_RSP block.
+#define PSDM_REG_DORQ_ALMOST_FULL                                                                            0xfa0708UL //Access:RW   DataWidth:0x6    // Almost full signal for read data from DORQ in SDM_DORQ block.
+#define PSDM_REG_AGG_INT_CTRL                                                                                0xfa0800UL //Access:RW   DataWidth:0xa    // This array of registers provides controls for each of the aggregated interrupts; The fields are defined as follows: [20:16] Affinity [15:12] NumL2m. [11]    Exclusive. [10]    Core-selection where 0=Core_A and 1=Core_B. [9]     Mode bit where 0=normal and 1=auto-mask-mode. [8]     T-flag which determines if a thread is allocated for this handler in the Storm. [7:0]   EventID which selects the event ID of the associated handler.
+#define PSDM_REG_AGG_INT_CTRL_SIZE                                                                           32
+#define PSDM_REG_AGG_INT_STATE                                                                               0xfa0a00UL //Access:R    DataWidth:0x2    // This array of registers provides access to each of the 32 aggregated interrupt request state machines; The values read from this register mean the following; 00 = IDLE; 01 = PEND; 10 = MASK; 11 = PANDM.
+#define PSDM_REG_AGG_INT_STATE_SIZE                                                                          32
+#define PSDM_REG_QUEUE_FULL                                                                                  0xfa0c00UL //Access:R    DataWidth:0x9    // Input queue fifo full in sdm_inp block.
+#define PSDM_REG_INT_CMPL_PEND_FULL                                                                          0xfa0c04UL //Access:R    DataWidth:0x1    // Internal write completion pending full in internal write block.
+#define PSDM_REG_INT_CPRM_PEND_FULL                                                                          0xfa0c08UL //Access:R    DataWidth:0x1    // Internal write completion parameter pending full in internal write block.
+#define PSDM_REG_QM_FULL                                                                                     0xfa0c0cUL //Access:R    DataWidth:0x1    // QM IF  full in sdm_inp block.
+#define PSDM_REG_DELAY_FIFO_FULL                                                                             0xfa0c10UL //Access:R    DataWidth:0x1    // Delay FIFO  full in sdm_inp block.
+#define PSDM_REG_TIMERS_PEND_FULL                                                                            0xfa0c14UL //Access:R    DataWidth:0x1    // Pending FIFO  full in sdm_timers block.
+#define PSDM_REG_TIMERS_ADDR_FULL                                                                            0xfa0c18UL //Access:R    DataWidth:0x1    // Address FIFO  full in sdm_timers block.
+#define PSDM_REG_RSP_PXP_RDATA_FULL                                                                          0xfa0c1cUL //Access:R    DataWidth:0x1    // PXP rd_data fifo  full in sdm_dma_rsp block.
+#define PSDM_REG_RSP_BRB_RDATA_FULL                                                                          0xfa0c20UL //Access:R    DataWidth:0x1    // BRB read data fifo  full in sdm_dma_rsp block.
+#define PSDM_REG_RSP_INT_RAM_RDATA_FULL                                                                      0xfa0c24UL //Access:R    DataWidth:0x1    // Int_ram rd_data fifo  full in sdm_dma_rsp block.
+#define PSDM_REG_RSP_BRB_PEND_FULL                                                                           0xfa0c28UL //Access:R    DataWidth:0x1    // BRB pending fifo  full in sdm_dma_rsp block.
+#define PSDM_REG_RSP_INT_RAM_PEND_FULL                                                                       0xfa0c2cUL //Access:R    DataWidth:0x1    // Int_ram pending fifo  full in sdm_dma_rsp block.
+#define PSDM_REG_RSP_BRB_IF_FULL                                                                             0xfa0c30UL //Access:R    DataWidth:0x1    // BRB interface is  full in sdm_dma_rsp block.
+#define PSDM_REG_RSP_PXP_IF_FULL                                                                             0xfa0c34UL //Access:R    DataWidth:0x1    // PXP interface is  full in sdm_dma_rsp block.
+#define PSDM_REG_DST_PXP_IMMED_FULL                                                                          0xfa0c38UL //Access:R    DataWidth:0x1    // PXP immediate fifo full in sdm_dma_dst block.
+#define PSDM_REG_DST_PXP_DST_PEND_FULL                                                                       0xfa0c3cUL //Access:R    DataWidth:0x1    // PXP destination pending fifo full in sdm_dma_dst block.
+#define PSDM_REG_DST_PXP_SRC_PEND_FULL                                                                       0xfa0c40UL //Access:R    DataWidth:0x1    // PXP source pending fifo full in sdm_dma_dst block.
+#define PSDM_REG_DST_BRB_SRC_PEND_FULL                                                                       0xfa0c44UL //Access:R    DataWidth:0x1    // BRB source pending fifo full in sdm_dma_dst block.
+#define PSDM_REG_DST_BRB_SRC_ADDR_FULL                                                                       0xfa0c48UL //Access:R    DataWidth:0x1    // BRB source address fifo full in sdm_dma_dst block.
+#define PSDM_REG_DST_PXP_LINK_FULL                                                                           0xfa0c4cUL //Access:R    DataWidth:0x1    // PXP link list full in sdm_dma_dst block.
+#define PSDM_REG_DST_INT_RAM_WAIT_FULL                                                                       0xfa0c50UL //Access:R    DataWidth:0x1    // Int_ram_wait fifo full in sdm_dma_dst block.
+#define PSDM_REG_DST_PAS_BUF_WAIT_FULL                                                                       0xfa0c54UL //Access:R    DataWidth:0x1    // Pas_buf_wait fifo full in sdm_dma_dst block.
+#define PSDM_REG_DST_PXP_IF_FULL                                                                             0xfa0c58UL //Access:R    DataWidth:0x1    // PXP if full in sdm_dma_dst block.
+#define PSDM_REG_DST_INT_RAM_IF_FULL                                                                         0xfa0c5cUL //Access:R    DataWidth:0x1    // Int_ram if full in sdm_dma_dst block.
+#define PSDM_REG_DST_PAS_BUF_IF_FULL                                                                         0xfa0c60UL //Access:R    DataWidth:0x1    // Pas_buf if full in sdm_dma_dst block.
+#define PSDM_REG_SH_DELAY_FULL                                                                               0xfa0c64UL //Access:R    DataWidth:0x1    // Shared delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.
+#define PSDM_REG_CM_DELAY_FULL                                                                               0xfa0c68UL //Access:R    DataWidth:0x1    // CM delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.
+#define PSDM_REG_CMSG_QUE_FULL                                                                               0xfa0c6cUL //Access:R    DataWidth:0x1    // Completion message queue fifo full in sdm_cm block.
+#define PSDM_REG_CCFC_LOAD_PEND_FULL                                                                         0xfa0c70UL //Access:R    DataWidth:0x1    // CCFC load pending fifo full in the CCFC interface  block.
+#define PSDM_REG_TCFC_LOAD_PEND_FULL                                                                         0xfa0c74UL //Access:R    DataWidth:0x1    // TCFC load pending fifo full in the TCFC interface block.
+#define PSDM_REG_ASYNC_HOST_FULL                                                                             0xfa0c78UL //Access:R    DataWidth:0x1    // Async fifo full in sdm_async block.
+#define PSDM_REG_PRM_FIFO_FULL                                                                               0xfa0c7cUL //Access:R    DataWidth:0x1    // PRM FIFO full in PRM interface block.
+#define PSDM_REG_RMT_XCM_FIFO_FULL_K2_E5                                                                     0xfa0c80UL //Access:R    DataWidth:0x1    // Remote XCM FIFO full (exist only in MSDM => XCM interface).
+#define PSDM_REG_RMT_YCM_FIFO_FULL_K2_E5                                                                     0xfa0c84UL //Access:R    DataWidth:0x1    // Remote YCM FIFO full (exist only in MSDM => YCM interface).
+#define PSDM_REG_INT_CMPL_PEND_EMPTY                                                                         0xfa0d00UL //Access:R    DataWidth:0x1    // Internal write completion pending empty in internal write block.
+#define PSDM_REG_INT_CPRM_PEND_EMPTY                                                                         0xfa0d04UL //Access:R    DataWidth:0x1    // Internal write completion parameter pending empty in internal write block.
+#define PSDM_REG_QUEUE_EMPTY                                                                                 0xfa0d08UL //Access:R    DataWidth:0x9    // Input queue fifo empty in sdm_inp block.
+#define PSDM_REG_DELAY_FIFO_EMPTY                                                                            0xfa0d0cUL //Access:R    DataWidth:0x1    // Delay FIFO  empty in sdm_inp block.
+#define PSDM_REG_TIMERS_PEND_EMPTY                                                                           0xfa0d10UL //Access:R    DataWidth:0x1    // Pending FIFO  empty in sdm_timers block.
+#define PSDM_REG_TIMERS_ADDR_EMPTY                                                                           0xfa0d14UL //Access:R    DataWidth:0x1    // Address FIFO  empty in sdm_timers block.
+#define PSDM_REG_RSP_PXP_RDATA_EMPTY                                                                         0xfa0d18UL //Access:R    DataWidth:0x1    // PXP rd_data fifo  empty in sdm_dma_rsp block.
+#define PSDM_REG_RSP_BRB_RDATA_EMPTY                                                                         0xfa0d1cUL //Access:R    DataWidth:0x1    // BRB read data fifo  empty in sdm_dma_rsp block.
+#define PSDM_REG_RSP_INT_RAM_RDATA_EMPTY                                                                     0xfa0d20UL //Access:R    DataWidth:0x1    // Int_ram rd_data fifo  empty in sdm_dma_rsp block.
+#define PSDM_REG_RSP_BRB_PEND_EMPTY                                                                          0xfa0d24UL //Access:R    DataWidth:0x1    // BRB pending fifo  empty in sdm_dma_rsp block.
+#define PSDM_REG_RSP_INT_RAM_PEND_EMPTY                                                                      0xfa0d28UL //Access:R    DataWidth:0x1    // Int_ram pending fifo  empty in sdm_dma_rsp block.
+#define PSDM_REG_DST_PXP_IMMED_EMPTY                                                                         0xfa0d2cUL //Access:R    DataWidth:0x1    // PXP immediate fifo empty in sdm_dma_dst block.
+#define PSDM_REG_DST_PXP_DST_PEND_EMPTY                                                                      0xfa0d30UL //Access:R    DataWidth:0x1    // PXP destination pending fifo empty in sdm_dma_dst block.
+#define PSDM_REG_DST_PXP_SRC_PEND_EMPTY                                                                      0xfa0d34UL //Access:R    DataWidth:0x1    // PXP source pending fifo empty in sdm_dma_dst block.
+#define PSDM_REG_DST_BRB_SRC_PEND_EMPTY                                                                      0xfa0d38UL //Access:R    DataWidth:0x1    // BRB source pending fifo empty in sdm_dma_dst block.
+#define PSDM_REG_DST_BRB_SRC_ADDR_EMPTY                                                                      0xfa0d3cUL //Access:R    DataWidth:0x1    // BRB source address fifo empty in sdm_dma_dst block.
+#define PSDM_REG_DST_PXP_LINK_EMPTY                                                                          0xfa0d40UL //Access:R    DataWidth:0x1    // PXP link list empty in sdm_dma_dst block.
+#define PSDM_REG_DST_INT_RAM_WAIT_EMPTY                                                                      0xfa0d44UL //Access:R    DataWidth:0x1    // Int_ram_wait fifo empty in sdm_dma_dst block.
+#define PSDM_REG_DST_PAS_BUF_WAIT_EMPTY                                                                      0xfa0d48UL //Access:R    DataWidth:0x1    // Pas_buf_wait fifo empty in sdm_dma_dst block.
+#define PSDM_REG_SH_DELAY_EMPTY                                                                              0xfa0d4cUL //Access:R    DataWidth:0x1    // Shared delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.
+#define PSDM_REG_CM_DELAY_EMPTY                                                                              0xfa0d50UL //Access:R    DataWidth:0x1    // CM delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.
+#define PSDM_REG_CMSG_QUE_EMPTY                                                                              0xfa0d54UL //Access:R    DataWidth:0x1    // Completion message queue fifo empty in sdm_dma_dst block.
+#define PSDM_REG_CCFC_LOAD_PEND_EMPTY                                                                        0xfa0d58UL //Access:R    DataWidth:0x1    // CCFC load pending fifo empty in sdm_ccfc block.
+#define PSDM_REG_TCFC_LOAD_PEND_EMPTY                                                                        0xfa0d5cUL //Access:R    DataWidth:0x1    // TCFC load pending fifo empty in sdm_tcfc block.
+#define PSDM_REG_ASYNC_HOST_EMPTY                                                                            0xfa0d60UL //Access:R    DataWidth:0x1    // Async fifo empty in sdm_async block.
+#define PSDM_REG_PRM_FIFO_EMPTY                                                                              0xfa0d64UL //Access:R    DataWidth:0x1    // PRM FIFO empty in sdm_prm_if block.
+#define PSDM_REG_RMT_XCM_FIFO_EMPTY_K2_E5                                                                    0xfa0d68UL //Access:R    DataWidth:0x1    // Remote XCM FIFO empty (exist only within MSDM => XCM path).
+#define PSDM_REG_RMT_YCM_FIFO_EMPTY_K2_E5                                                                    0xfa0d6cUL //Access:R    DataWidth:0x1    // Remote YCM FIFO empty (exist only within MSDM => YCM path).
+#define PSDM_REG_DBG_OUT_DATA                                                                                0xfa0e00UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PSDM_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define PSDM_REG_DBG_OUT_VALID                                                                               0xfa0e20UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define PSDM_REG_DBG_OUT_FRAME                                                                               0xfa0e24UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define PSDM_REG_DBG_SELECT                                                                                  0xfa0e28UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PSDM_REG_DBG_DWORD_ENABLE                                                                            0xfa0e2cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PSDM_REG_DBG_SHIFT                                                                                   0xfa0e30UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PSDM_REG_DBG_FORCE_VALID                                                                             0xfa0e34UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PSDM_REG_DBG_FORCE_FRAME                                                                             0xfa0e38UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PSDM_REG_ASYNC_FIFO                                                                                  0xfa2000UL //Access:WB_R DataWidth:0x49   // Provides read-only access of the PXP-Async input FIFO. Intended for debug purposes.
+#define PSDM_REG_ASYNC_FIFO_SIZE                                                                             116
+#define PSDM_REG_IMMED_FIFO                                                                                  0xfa2400UL //Access:WB_R DataWidth:0x40   // Provides read-only access of the immediate data FIFO. Intended for debug purposes.
+#define PSDM_REG_IMMED_FIFO_SIZE                                                                             38
+#define PSDM_REG_BRB_FIFO                                                                                    0xfa2800UL //Access:WB_R DataWidth:0x86   // Provides read-only access of the BRB response FIFO. Intended for debug purposes.
+#define PSDM_REG_BRB_FIFO_SIZE                                                                               152
+#define PSDM_REG_PXP_FIFO                                                                                    0xfa2c00UL //Access:WB_R DataWidth:0x4a   // Provides read-only access of the PXP response FIFO. Intended for debug purposes.
+#define PSDM_REG_PXP_FIFO_SIZE                                                                               76
+#define PSDM_REG_INT_RAM_FIFO                                                                                0xfa3000UL //Access:WB_R DataWidth:0x41   // Provides read-only access of the internal RAM response FIFO. Intended for debug purposes.
+#define PSDM_REG_INT_RAM_FIFO_SIZE                                                                           76
+#define PSDM_REG_DPM_FIFO                                                                                    0xfa3400UL //Access:WB_R DataWidth:0x51   // Provides read-only access of the DORQ DPM input FIFO. Intended for debug purposes.
+#define PSDM_REG_DPM_FIFO_SIZE                                                                               172
+#define PSDM_REG_EXT_OVERFLOW                                                                                0xfa3800UL //Access:WB_R DataWidth:0x4b   // Provides read-only access of the external store overflow FIFO. Intended for debug purposes.
+#define PSDM_REG_EXT_OVERFLOW_SIZE                                                                           36
+#define PSDM_REG_PRM_FIFO                                                                                    0xfa3c00UL //Access:WB_R DataWidth:0x41   // Provides read-only access of the PRM completion input FIFO. Intended for debug purposes.
+#define PSDM_REG_PRM_FIFO_SIZE                                                                               84
+#define PSDM_REG_TIMERS                                                                                      0xfa4000UL //Access:WB   DataWidth:0x39   // Provides memory-mapped read/write access to the timers' memory. Intended for debug purposes.
+#define PSDM_REG_TIMERS_SIZE                                                                                 8
+#define PSDM_REG_INP_QUEUE                                                                                   0xfa5000UL //Access:WB   DataWidth:0x40   // Input queue memory. Access only for debugging.
+#define PSDM_REG_INP_QUEUE_SIZE                                                                              272
+#define PSDM_REG_CMSG_QUE                                                                                    0xfa8000UL //Access:WB   DataWidth:0x40   // CM queue memory. Access only for debugging.
+#define PSDM_REG_CMSG_QUE_SIZE                                                                               128
+#define TSDM_REG_ENABLE_IN1                                                                                  0xfb0004UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define TSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN                                                                (0x1<<0) // Enable for input command from STORM.
+  #define TSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN_SHIFT                                                          0
+  #define TSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN                                                             (0x1<<1) // Enable for input data from internal ram interface in DMA_RSP block.
+  #define TSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN_SHIFT                                                       1
+  #define TSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN                                                             (0x1<<2) // Enable for input done from internal ram interface in DMA_RSP block.
+  #define TSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN_SHIFT                                                       2
+  #define TSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN                                                             (0x1<<3) // Enable for input full from internal ram interface in DMA_RSP block.
+  #define TSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN_SHIFT                                                       3
+  #define TSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN                                                             (0x1<<4) // Enable for input done from passive buffer interface in DMA_RSP block.
+  #define TSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN_SHIFT                                                       4
+  #define TSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN                                                             (0x1<<5) // Enable for input full from passive buffer interface in DMA_RSP block.
+  #define TSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN_SHIFT                                                       5
+  #define TSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN                                                                 (0x1<<6) // Enable for input done from pxp-HW interface in DMA_DST block.
+  #define TSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN_SHIFT                                                           6
+  #define TSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN                                                                 (0x1<<7) // Enable for input full from pxp-HW interface in DMA_DST block.
+  #define TSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN_SHIFT                                                           7
+  #define TSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN                                                                 (0x1<<8) // Enable for input data from pxp-HW interface in DMA_RSP block.
+  #define TSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN_SHIFT                                                           8
+  #define TSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN                                                              (0x1<<9) // Enable for input ack from pxp-internal write for SDM_INT block.
+  #define TSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN_SHIFT                                                        9
+  #define TSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN                                                                  (0x1<<10) // Enable for input acknowledge to credit counter from pxp_HW interface.
+  #define TSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN_SHIFT                                                            10
+  #define TSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN                                                                 (0x1<<11) // Enable for input data from BRB interface in DMA_RSP block.
+  #define TSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN_SHIFT                                                           11
+  #define TSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN                                                                  (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
+  #define TSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN_SHIFT                                                            12
+  #define TSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN                                                                  (0x1<<13) // Enable for input completion message from PRM in prm_if block.
+  #define TSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN_SHIFT                                                            13
+  #define TSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN                                                            (0x1<<14) // Enable for input ack to CCFC load credit counter.
+  #define TSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN_SHIFT                                                      14
+  #define TSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN                                                            (0x1<<15) // Enable for input ack to TCFC load credit counter.
+  #define TSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN_SHIFT                                                      15
+  #define TSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN                                                            (0x1<<16) // Enable for input response from CCFC in CCFC block.
+  #define TSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN_SHIFT                                                      16
+  #define TSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN                                                              (0x1<<17) // Enable for input ack to CCFC credit counter on the A/C interface.
+  #define TSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN_SHIFT                                                        17
+  #define TSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN                                                              (0x1<<18) // Enable for input ack to TCFC credit counter on the A/C interface.
+  #define TSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN_SHIFT                                                        18
+  #define TSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN                                                           (0x1<<19) // Enable for input full from qm in SDM_INP block.
+  #define TSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN_SHIFT                                                     19
+#define TSDM_REG_ENABLE_IN2                                                                                  0xfb0008UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define TSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN                                                            (0x1<<0) // Enable for input response from TCFC in TCFC block.
+  #define TSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN_SHIFT                                                      0
+  #define TSDM_REG_ENABLE_IN2_CM_ACK_IN_EN                                                                   (0x1<<1) // Enable for input acknowledge from Cm  in SDM_CM block.
+  #define TSDM_REG_ENABLE_IN2_CM_ACK_IN_EN_SHIFT                                                             1
+  #define TSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN                                                                 (0x1<<2) // Enable for input DPM requests in SDM_DORQ block.
+  #define TSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN_SHIFT                                                           2
+#define TSDM_REG_ENABLE_OUT1                                                                                 0xfb000cUL //Access:RW   DataWidth:0x15   // Multi Field Register.
+  #define TSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN                                                                (0x1<<0) // Enable for output request to pxp internal write for SDM_INT block.
+  #define TSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN_SHIFT                                                          0
+  #define TSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN                                                             (0x1<<1) // Enable for output thread ready to the SEMI.
+  #define TSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN_SHIFT                                                       1
+  #define TSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN                                                             (0x1<<2) // Enable the output thread release to the SEMI.
+  #define TSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN_SHIFT                                                       2
+  #define TSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN                                                              (0x1<<3) // Enable for output load request to CCFC.
+  #define TSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN_SHIFT                                                        3
+  #define TSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN                                                              (0x1<<4) // Enable for output load request to TCFC.
+  #define TSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN_SHIFT                                                        4
+  #define TSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN                                                                (0x1<<5) // Enable for output increment to CCFC activity counter.
+  #define TSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN_SHIFT                                                          5
+  #define TSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN                                                                (0x1<<6) // Enable for output decrement to TCFC activity counter.
+  #define TSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN_SHIFT                                                          6
+  #define TSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN                                                                (0x1<<7) // Enable for output data to pxp-HW interface in DMA_REQ block.
+  #define TSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN_SHIFT                                                          7
+  #define TSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN                                                                (0x1<<8) // Enable for output request to BRB interface in DMA_REQ block.
+  #define TSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN_SHIFT                                                          8
+  #define TSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN                                                                (0x1<<9) // Enable for output write to int_ram in DMA_DST block.
+  #define TSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN_SHIFT                                                          9
+  #define TSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN                                                                (0x1<<10) // Enable for output write topassive buffer in DMA_DST block.
+  #define TSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN_SHIFT                                                          10
+  #define TSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN                                                              (0x1<<11) // Enable for output write to pxp async in DMA_DST block.
+  #define TSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN_SHIFT                                                        11
+  #define TSDM_REG_ENABLE_OUT1_PXP_OUT_EN                                                                    (0x1<<12) // Enable for output write to pxp  in DMA_DST block.
+  #define TSDM_REG_ENABLE_OUT1_PXP_OUT_EN_SHIFT                                                              12
+  #define TSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN                                                               (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
+  #define TSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN_SHIFT                                                         13
+  #define TSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN                                                               (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
+  #define TSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN_SHIFT                                                         14
+  #define TSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN                                                               (0x1<<15) // Enable for output external full to SEMI block.
+  #define TSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN_SHIFT                                                         15
+  #define TSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN                                                           (0x1<<16) // Enable for output done to async PXP host IF.
+  #define TSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN_SHIFT                                                     16
+  #define TSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN                                                           (0x1<<17) // Enable the output done (ack) to PRM.
+  #define TSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN_SHIFT                                                     17
+  #define TSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN                                                                 (0x1<<18) // Enable for output message to CM in SDM_CM block.
+  #define TSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN_SHIFT                                                           18
+  #define TSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN                                                           (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
+  #define TSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN_SHIFT                                                     19
+  #define TSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN                                                           (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
+  #define TSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN_SHIFT                                                     20
+#define TSDM_REG_ENABLE_OUT2                                                                                 0xfb0010UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define TSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN                                                              (0x1<<0) // Enable for output command to qm in SDM_INP block.
+  #define TSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN_SHIFT                                                        0
+  #define TSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN                                                               (0x1<<1) // Enable for VF/PF error valid in DMA_DST block.
+  #define TSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN_SHIFT                                                         1
+  #define TSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN                                                          (0x1<<2) // Enable for DPM request done output in SDM_DORQ block.
+  #define TSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN_SHIFT                                                    2
+#define TSDM_REG_DISABLE_ENGINE                                                                              0xfb0014UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define TSDM_REG_DISABLE_ENGINE_DISABLE_DMA                                                                (0x1<<0) // This bit should be set to disable the DMA exectuion engine from processing DMA commands.
+  #define TSDM_REG_DISABLE_ENGINE_DISABLE_DMA_SHIFT                                                          0
+  #define TSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS                                                             (0x1<<1) // This bit should be set to disable the timers' exectuion engine from processing timers' commands.
+  #define TSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS_SHIFT                                                       1
+  #define TSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD                                                          (0x1<<2) // This bit should be set to disable the CCFC exectuion engine from processing CCFC load commands.
+  #define TSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD_SHIFT                                                    2
+  #define TSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD                                                          (0x1<<3) // This bit should be set to disable the TCFC exectuion engine from processing TCFC load commands.
+  #define TSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD_SHIFT                                                    3
+  #define TSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR                                                             (0x1<<4) // This bit should be set to disable the internal write exectuion engine from processing Internal write commands.
+  #define TSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR_SHIFT                                                       4
+  #define TSDM_REG_DISABLE_ENGINE_DISABLE_NOP                                                                (0x1<<5) // This bit should be set to disable the SDM NOP exectuion engine from processing NOP commands.
+  #define TSDM_REG_DISABLE_ENGINE_DISABLE_NOP_SHIFT                                                          5
+  #define TSDM_REG_DISABLE_ENGINE_DISABLE_GRC                                                                (0x1<<6) // This bit should be set to disable the GRC master exectuion engine from processing GRC master commands.
+  #define TSDM_REG_DISABLE_ENGINE_DISABLE_GRC_SHIFT                                                          6
+  #define TSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC                                                              (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Async requests.
+  #define TSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC_SHIFT                                                        7
+  #define TSDM_REG_DISABLE_ENGINE_DISABLE_PRM                                                                (0x1<<8) // This bit should be set to disable the PRM interface from processing PRM completion commands.
+  #define TSDM_REG_DISABLE_ENGINE_DISABLE_PRM_SHIFT                                                          8
+  #define TSDM_REG_DISABLE_ENGINE_DISABLE_DORQ                                                               (0x1<<9) // This bit should be set to disable the DORQ DPM interface from processing DPM commands.
+  #define TSDM_REG_DISABLE_ENGINE_DISABLE_DORQ_SHIFT                                                         9
+#define TSDM_REG_INT_STS                                                                                     0xfb0040UL //Access:R    DataWidth:0x1c   // Multi Field Register.
+  #define TSDM_REG_INT_STS_ADDRESS_ERROR                                                                     (0x1<<0) // Signals an unknown address to the rf module.
+  #define TSDM_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                               0
+  #define TSDM_REG_INT_STS_INP_QUEUE_ERROR                                                                   (0x1<<1) // Indicates that one of the input queues had a FIFO error.
+  #define TSDM_REG_INT_STS_INP_QUEUE_ERROR_SHIFT                                                             1
+  #define TSDM_REG_INT_STS_DELAY_FIFO_ERROR                                                                  (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
+  #define TSDM_REG_INT_STS_DELAY_FIFO_ERROR_SHIFT                                                            2
+  #define TSDM_REG_INT_STS_ASYNC_HOST_ERROR                                                                  (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
+  #define TSDM_REG_INT_STS_ASYNC_HOST_ERROR_SHIFT                                                            3
+  #define TSDM_REG_INT_STS_PRM_FIFO_ERROR                                                                    (0x1<<4) // FIFO in PRM interface sub-module reported an error.
+  #define TSDM_REG_INT_STS_PRM_FIFO_ERROR_SHIFT                                                              4
+  #define TSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR                                                              (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
+  #define TSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR_SHIFT                                                        5
+  #define TSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR                                                              (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
+  #define TSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR_SHIFT                                                        6
+  #define TSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR                                                            (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
+  #define TSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR_SHIFT                                                      7
+  #define TSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR                                                            (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
+  #define TSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR_SHIFT                                                      8
+  #define TSDM_REG_INT_STS_DST_PXP_IMMED_ERROR                                                               (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
+  #define TSDM_REG_INT_STS_DST_PXP_IMMED_ERROR_SHIFT                                                         9
+  #define TSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR                                                            (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
+  #define TSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR_SHIFT                                                      10
+  #define TSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR                                                            (0x1<<11) // BRB src pend fifo error in DMA_DST block.
+  #define TSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR_SHIFT                                                      11
+  #define TSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR                                                            (0x1<<12) // BRB src addr fifo error in DMA_DST block.
+  #define TSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR_SHIFT                                                      12
+  #define TSDM_REG_INT_STS_RSP_BRB_PEND_ERROR                                                                (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
+  #define TSDM_REG_INT_STS_RSP_BRB_PEND_ERROR_SHIFT                                                          13
+  #define TSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR                                                            (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
+  #define TSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR_SHIFT                                                      14
+  #define TSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR                                                             (0x1<<15) // Read data firo in DMA_RSP block for BRB.
+  #define TSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR_SHIFT                                                       15
+  #define TSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR                                                         (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
+  #define TSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                                   16
+  #define TSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR                                                             (0x1<<17) // PXP read data fifo error in DMA_RSP block.
+  #define TSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR_SHIFT                                                       17
+  #define TSDM_REG_INT_STS_CM_DELAY_ERROR                                                                    (0x1<<18) // Delay CM fifo error in CM block.
+  #define TSDM_REG_INT_STS_CM_DELAY_ERROR_SHIFT                                                              18
+  #define TSDM_REG_INT_STS_SH_DELAY_ERROR                                                                    (0x1<<19) // Delay shared fifo error in CM block.
+  #define TSDM_REG_INT_STS_SH_DELAY_ERROR_SHIFT                                                              19
+  #define TSDM_REG_INT_STS_CMPL_PEND_ERROR                                                                   (0x1<<20) // Error in completion pending FIFO in internal write block.
+  #define TSDM_REG_INT_STS_CMPL_PEND_ERROR_SHIFT                                                             20
+  #define TSDM_REG_INT_STS_CPRM_PEND_ERROR                                                                   (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
+  #define TSDM_REG_INT_STS_CPRM_PEND_ERROR_SHIFT                                                             21
+  #define TSDM_REG_INT_STS_TIMER_ADDR_ERROR                                                                  (0x1<<22) // Address fifo error in timer block.
+  #define TSDM_REG_INT_STS_TIMER_ADDR_ERROR_SHIFT                                                            22
+  #define TSDM_REG_INT_STS_TIMER_PEND_ERROR                                                                  (0x1<<23) // Pending fifo error in timer block.
+  #define TSDM_REG_INT_STS_TIMER_PEND_ERROR_SHIFT                                                            23
+  #define TSDM_REG_INT_STS_DORQ_DPM_ERROR                                                                    (0x1<<24) // Dpm fifo error in dorq I/F block.
+  #define TSDM_REG_INT_STS_DORQ_DPM_ERROR_SHIFT                                                              24
+  #define TSDM_REG_INT_STS_DST_PXP_DONE_ERROR                                                                (0x1<<25) // PXP done fifo error in DMA_dst block.
+  #define TSDM_REG_INT_STS_DST_PXP_DONE_ERROR_SHIFT                                                          25
+  #define TSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR_K2_E5                                                        (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define TSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                                  26
+  #define TSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_K2_E5                                                        (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define TSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                                  27
+#define TSDM_REG_INT_MASK                                                                                    0xfb0044UL //Access:RW   DataWidth:0x1c   // Multi Field Register.
+  #define TSDM_REG_INT_MASK_ADDRESS_ERROR                                                                    (0x1<<0) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.ADDRESS_ERROR .
+  #define TSDM_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                              0
+  #define TSDM_REG_INT_MASK_INP_QUEUE_ERROR                                                                  (0x1<<1) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.INP_QUEUE_ERROR .
+  #define TSDM_REG_INT_MASK_INP_QUEUE_ERROR_SHIFT                                                            1
+  #define TSDM_REG_INT_MASK_DELAY_FIFO_ERROR                                                                 (0x1<<2) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DELAY_FIFO_ERROR .
+  #define TSDM_REG_INT_MASK_DELAY_FIFO_ERROR_SHIFT                                                           2
+  #define TSDM_REG_INT_MASK_ASYNC_HOST_ERROR                                                                 (0x1<<3) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.ASYNC_HOST_ERROR .
+  #define TSDM_REG_INT_MASK_ASYNC_HOST_ERROR_SHIFT                                                           3
+  #define TSDM_REG_INT_MASK_PRM_FIFO_ERROR                                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.PRM_FIFO_ERROR .
+  #define TSDM_REG_INT_MASK_PRM_FIFO_ERROR_SHIFT                                                             4
+  #define TSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR                                                             (0x1<<5) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.CCFC_LOAD_PEND_ERROR .
+  #define TSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR_SHIFT                                                       5
+  #define TSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR                                                             (0x1<<6) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.TCFC_LOAD_PEND_ERROR .
+  #define TSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR_SHIFT                                                       6
+  #define TSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR                                                           (0x1<<7) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DST_INT_RAM_WAIT_ERROR .
+  #define TSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR_SHIFT                                                     7
+  #define TSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR                                                           (0x1<<8) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DST_PAS_BUF_WAIT_ERROR .
+  #define TSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR_SHIFT                                                     8
+  #define TSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR                                                              (0x1<<9) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DST_PXP_IMMED_ERROR .
+  #define TSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR_SHIFT                                                        9
+  #define TSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR                                                           (0x1<<10) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DST_PXP_DST_PEND_ERROR .
+  #define TSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR_SHIFT                                                     10
+  #define TSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR                                                           (0x1<<11) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DST_BRB_SRC_PEND_ERROR .
+  #define TSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR_SHIFT                                                     11
+  #define TSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR                                                           (0x1<<12) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DST_BRB_SRC_ADDR_ERROR .
+  #define TSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR_SHIFT                                                     12
+  #define TSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR                                                               (0x1<<13) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.RSP_BRB_PEND_ERROR .
+  #define TSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR_SHIFT                                                         13
+  #define TSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR                                                           (0x1<<14) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.RSP_INT_RAM_PEND_ERROR .
+  #define TSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR_SHIFT                                                     14
+  #define TSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR                                                            (0x1<<15) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.RSP_BRB_RD_DATA_ERROR .
+  #define TSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR_SHIFT                                                      15
+  #define TSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR                                                        (0x1<<16) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.RSP_INT_RAM_RD_DATA_ERROR .
+  #define TSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                                  16
+  #define TSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR                                                            (0x1<<17) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.RSP_PXP_RD_DATA_ERROR .
+  #define TSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR_SHIFT                                                      17
+  #define TSDM_REG_INT_MASK_CM_DELAY_ERROR                                                                   (0x1<<18) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.CM_DELAY_ERROR .
+  #define TSDM_REG_INT_MASK_CM_DELAY_ERROR_SHIFT                                                             18
+  #define TSDM_REG_INT_MASK_SH_DELAY_ERROR                                                                   (0x1<<19) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.SH_DELAY_ERROR .
+  #define TSDM_REG_INT_MASK_SH_DELAY_ERROR_SHIFT                                                             19
+  #define TSDM_REG_INT_MASK_CMPL_PEND_ERROR                                                                  (0x1<<20) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.CMPL_PEND_ERROR .
+  #define TSDM_REG_INT_MASK_CMPL_PEND_ERROR_SHIFT                                                            20
+  #define TSDM_REG_INT_MASK_CPRM_PEND_ERROR                                                                  (0x1<<21) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.CPRM_PEND_ERROR .
+  #define TSDM_REG_INT_MASK_CPRM_PEND_ERROR_SHIFT                                                            21
+  #define TSDM_REG_INT_MASK_TIMER_ADDR_ERROR                                                                 (0x1<<22) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.TIMER_ADDR_ERROR .
+  #define TSDM_REG_INT_MASK_TIMER_ADDR_ERROR_SHIFT                                                           22
+  #define TSDM_REG_INT_MASK_TIMER_PEND_ERROR                                                                 (0x1<<23) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.TIMER_PEND_ERROR .
+  #define TSDM_REG_INT_MASK_TIMER_PEND_ERROR_SHIFT                                                           23
+  #define TSDM_REG_INT_MASK_DORQ_DPM_ERROR                                                                   (0x1<<24) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DORQ_DPM_ERROR .
+  #define TSDM_REG_INT_MASK_DORQ_DPM_ERROR_SHIFT                                                             24
+  #define TSDM_REG_INT_MASK_DST_PXP_DONE_ERROR                                                               (0x1<<25) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DST_PXP_DONE_ERROR .
+  #define TSDM_REG_INT_MASK_DST_PXP_DONE_ERROR_SHIFT                                                         25
+  #define TSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR_K2_E5                                                       (0x1<<26) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.XCM_RMT_BUFFER_ERROR .
+  #define TSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                                 26
+  #define TSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_K2_E5                                                       (0x1<<27) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.YCM_RMT_BUFFER_ERROR .
+  #define TSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                                 27
+#define TSDM_REG_INT_STS_WR                                                                                  0xfb0048UL //Access:WR   DataWidth:0x1c   // Multi Field Register.
+  #define TSDM_REG_INT_STS_WR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define TSDM_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                            0
+  #define TSDM_REG_INT_STS_WR_INP_QUEUE_ERROR                                                                (0x1<<1) // Indicates that one of the input queues had a FIFO error.
+  #define TSDM_REG_INT_STS_WR_INP_QUEUE_ERROR_SHIFT                                                          1
+  #define TSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR                                                               (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
+  #define TSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR_SHIFT                                                         2
+  #define TSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR                                                               (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
+  #define TSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR_SHIFT                                                         3
+  #define TSDM_REG_INT_STS_WR_PRM_FIFO_ERROR                                                                 (0x1<<4) // FIFO in PRM interface sub-module reported an error.
+  #define TSDM_REG_INT_STS_WR_PRM_FIFO_ERROR_SHIFT                                                           4
+  #define TSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR                                                           (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
+  #define TSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR_SHIFT                                                     5
+  #define TSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR                                                           (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
+  #define TSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR_SHIFT                                                     6
+  #define TSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR                                                         (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
+  #define TSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR_SHIFT                                                   7
+  #define TSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR                                                         (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
+  #define TSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR_SHIFT                                                   8
+  #define TSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR                                                            (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
+  #define TSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR_SHIFT                                                      9
+  #define TSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR                                                         (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
+  #define TSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR_SHIFT                                                   10
+  #define TSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR                                                         (0x1<<11) // BRB src pend fifo error in DMA_DST block.
+  #define TSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR_SHIFT                                                   11
+  #define TSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR                                                         (0x1<<12) // BRB src addr fifo error in DMA_DST block.
+  #define TSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR_SHIFT                                                   12
+  #define TSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR                                                             (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
+  #define TSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR_SHIFT                                                       13
+  #define TSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR                                                         (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
+  #define TSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR_SHIFT                                                   14
+  #define TSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR                                                          (0x1<<15) // Read data firo in DMA_RSP block for BRB.
+  #define TSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR_SHIFT                                                    15
+  #define TSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR                                                      (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
+  #define TSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                                16
+  #define TSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR                                                          (0x1<<17) // PXP read data fifo error in DMA_RSP block.
+  #define TSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR_SHIFT                                                    17
+  #define TSDM_REG_INT_STS_WR_CM_DELAY_ERROR                                                                 (0x1<<18) // Delay CM fifo error in CM block.
+  #define TSDM_REG_INT_STS_WR_CM_DELAY_ERROR_SHIFT                                                           18
+  #define TSDM_REG_INT_STS_WR_SH_DELAY_ERROR                                                                 (0x1<<19) // Delay shared fifo error in CM block.
+  #define TSDM_REG_INT_STS_WR_SH_DELAY_ERROR_SHIFT                                                           19
+  #define TSDM_REG_INT_STS_WR_CMPL_PEND_ERROR                                                                (0x1<<20) // Error in completion pending FIFO in internal write block.
+  #define TSDM_REG_INT_STS_WR_CMPL_PEND_ERROR_SHIFT                                                          20
+  #define TSDM_REG_INT_STS_WR_CPRM_PEND_ERROR                                                                (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
+  #define TSDM_REG_INT_STS_WR_CPRM_PEND_ERROR_SHIFT                                                          21
+  #define TSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR                                                               (0x1<<22) // Address fifo error in timer block.
+  #define TSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR_SHIFT                                                         22
+  #define TSDM_REG_INT_STS_WR_TIMER_PEND_ERROR                                                               (0x1<<23) // Pending fifo error in timer block.
+  #define TSDM_REG_INT_STS_WR_TIMER_PEND_ERROR_SHIFT                                                         23
+  #define TSDM_REG_INT_STS_WR_DORQ_DPM_ERROR                                                                 (0x1<<24) // Dpm fifo error in dorq I/F block.
+  #define TSDM_REG_INT_STS_WR_DORQ_DPM_ERROR_SHIFT                                                           24
+  #define TSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR                                                             (0x1<<25) // PXP done fifo error in DMA_dst block.
+  #define TSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR_SHIFT                                                       25
+  #define TSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR_K2_E5                                                     (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define TSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                               26
+  #define TSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_K2_E5                                                     (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define TSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                               27
+#define TSDM_REG_INT_STS_CLR                                                                                 0xfb004cUL //Access:RC   DataWidth:0x1c   // Multi Field Register.
+  #define TSDM_REG_INT_STS_CLR_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define TSDM_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                           0
+  #define TSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR                                                               (0x1<<1) // Indicates that one of the input queues had a FIFO error.
+  #define TSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR_SHIFT                                                         1
+  #define TSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR                                                              (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
+  #define TSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR_SHIFT                                                        2
+  #define TSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR                                                              (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
+  #define TSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR_SHIFT                                                        3
+  #define TSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR                                                                (0x1<<4) // FIFO in PRM interface sub-module reported an error.
+  #define TSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR_SHIFT                                                          4
+  #define TSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR                                                          (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
+  #define TSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR_SHIFT                                                    5
+  #define TSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR                                                          (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
+  #define TSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR_SHIFT                                                    6
+  #define TSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR                                                        (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
+  #define TSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR_SHIFT                                                  7
+  #define TSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR                                                        (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
+  #define TSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR_SHIFT                                                  8
+  #define TSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR                                                           (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
+  #define TSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR_SHIFT                                                     9
+  #define TSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR                                                        (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
+  #define TSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR_SHIFT                                                  10
+  #define TSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR                                                        (0x1<<11) // BRB src pend fifo error in DMA_DST block.
+  #define TSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR_SHIFT                                                  11
+  #define TSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR                                                        (0x1<<12) // BRB src addr fifo error in DMA_DST block.
+  #define TSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR_SHIFT                                                  12
+  #define TSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR                                                            (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
+  #define TSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR_SHIFT                                                      13
+  #define TSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR                                                        (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
+  #define TSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR_SHIFT                                                  14
+  #define TSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR                                                         (0x1<<15) // Read data firo in DMA_RSP block for BRB.
+  #define TSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR_SHIFT                                                   15
+  #define TSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR                                                     (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
+  #define TSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                               16
+  #define TSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR                                                         (0x1<<17) // PXP read data fifo error in DMA_RSP block.
+  #define TSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR_SHIFT                                                   17
+  #define TSDM_REG_INT_STS_CLR_CM_DELAY_ERROR                                                                (0x1<<18) // Delay CM fifo error in CM block.
+  #define TSDM_REG_INT_STS_CLR_CM_DELAY_ERROR_SHIFT                                                          18
+  #define TSDM_REG_INT_STS_CLR_SH_DELAY_ERROR                                                                (0x1<<19) // Delay shared fifo error in CM block.
+  #define TSDM_REG_INT_STS_CLR_SH_DELAY_ERROR_SHIFT                                                          19
+  #define TSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR                                                               (0x1<<20) // Error in completion pending FIFO in internal write block.
+  #define TSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR_SHIFT                                                         20
+  #define TSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR                                                               (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
+  #define TSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR_SHIFT                                                         21
+  #define TSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR                                                              (0x1<<22) // Address fifo error in timer block.
+  #define TSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR_SHIFT                                                        22
+  #define TSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR                                                              (0x1<<23) // Pending fifo error in timer block.
+  #define TSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR_SHIFT                                                        23
+  #define TSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR                                                                (0x1<<24) // Dpm fifo error in dorq I/F block.
+  #define TSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR_SHIFT                                                          24
+  #define TSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR                                                            (0x1<<25) // PXP done fifo error in DMA_dst block.
+  #define TSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR_SHIFT                                                      25
+  #define TSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR_K2_E5                                                    (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define TSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                              26
+  #define TSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_K2_E5                                                    (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define TSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                              27
+#define TSDM_REG_PRTY_MASK_H_0_BB_K2                                                                         0xfb0204UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define TSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2                                                     (0x1<<0) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define TSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2_SHIFT                                               0
+  #define TSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2                                                     (0x1<<1) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define TSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2_SHIFT                                               1
+  #define TSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2                                                     (0x1<<2) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define TSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2_SHIFT                                               2
+  #define TSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2                                                     (0x1<<3) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define TSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2_SHIFT                                               3
+  #define TSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2                                                     (0x1<<4) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define TSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT                                               4
+  #define TSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                     (0x1<<5) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define TSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                               5
+  #define TSDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2                                                     (0x1<<6) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
+  #define TSDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2_SHIFT                                               6
+  #define TSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                     (0x1<<7) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define TSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                               7
+  #define TSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                     (0x1<<8) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define TSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                               8
+  #define TSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                     (0x1<<9) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define TSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                               9
+#define TSDM_REG_MEM_ECC_EVENTS_BB_K2                                                                        0xfb0210UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define TSDM_REG_TIMER_TICK                                                                                  0xfb0400UL //Access:RW   DataWidth:0x20   // Defines the number of system clock cycles that are used to define a timers clock tick cycle. Note: The minimal legal value for this register is 25, lower values can cause timers functionality issues.
+#define TSDM_REG_TIMERS_TICK_ENABLE                                                                          0xfb0404UL //Access:RW   DataWidth:0x1    // Enable for tick counter.
+#define TSDM_REG_OPERATION_GEN                                                                               0xfb0408UL //Access:W    DataWidth:0x14   // This register is used to assert a completion operation of choice; It includes the following completion fields: bits 19:16 are Trig; bits 15:0 are CompParams. Note that trigger types 3,5 or 8 are not supported by this interface as they require a completion message. If there is an attempt to assert an OperationGen with Trig = 3,5 or 8, the operation will be voided.
+#define TSDM_REG_GRC_PRIVILEGE_LEVEL                                                                         0xfb040cUL //Access:RW   DataWidth:0x2    // This register defines the PRV (privilege level) field within the FID structure of the SDM GRC master request.
+#define TSDM_REG_CM_MSG_CNT_ADDRESS                                                                          0xfb0410UL //Access:RW   DataWidth:0xf    // The internal RAM address for storing the shadow of the CM completion message counter.
+#define TSDM_REG_DORQ_DPM_START_ADDR                                                                         0xfb0414UL //Access:RW   DataWidth:0xf    // The start address in the internal RAM for DORQ DPM messages.
+#define TSDM_REG_RR_COMPLETE_REQ                                                                             0xfb0418UL //Access:R    DataWidth:0xa    // Provides read access to the round robin arbiter used for all completion write requests  in the completion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b7-PRM interface; b8-CCFC load; b9-TCFC load.
+#define TSDM_REG_RR_PTR_REQ                                                                                  0xfb041cUL //Access:R    DataWidth:0x9    // Provides read access to the round robin arbiter for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-int_wr; b7-prm; b8-grc_master.
+#define TSDM_REG_INT_RAM_RR_REQ                                                                              0xfb0420UL //Access:R    DataWidth:0x4    // Provides read access to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination;b2-PXP source/destination;b3-BRB source.
+#define TSDM_REG_INP_QUEUE_ERR_VECT                                                                          0xfb0424UL //Access:R    DataWidth:0x9    // This register is intended to be read in the event of an inp_queue_error interrupt.  It contains a vector with a bit per input queue. Clearing the interrupt causes this vector to be cleared. Errors on multiple FIFOs will be aggregated between interrupt clear requests.
+#define TSDM_REG_ASYNC_CMSG_ALLOC_LIMIT                                                                      0xfb0428UL //Access:RW   DataWidth:0x5    // This register defines the maximum number of completion messages that can be allocated to PXP-Async transactions at any given time. If the PXP-Async interface attempts to reserve beyond this limit, it will be held off until the situation is resolved.
+#define TSDM_REG_ECO_RESERVED                                                                                0xfb042cUL //Access:RW   DataWidth:0x8    // Reserved bits for ECO.
+#define TSDM_REG_INIT_CREDIT_PXP                                                                             0xfb0500UL //Access:RW   DataWidth:0x3    // The initial number of messages that can be sent to the pxp interface without receiving any ACK.
+#define TSDM_REG_INIT_CREDIT_PCI                                                                             0xfb0504UL //Access:RW   DataWidth:0x2    // The initial number of messages that can be sent to the PCI-Switch on the internal write interface without receiving any ACK.
+#define TSDM_REG_INIT_CREDIT_TCFC_AC                                                                         0xfb0508UL //Access:RW   DataWidth:0x4    // The initial number of messages that can be sent to the TCFC activity counters interface without receiving any ACK.
+#define TSDM_REG_INIT_CREDIT_CCFC_AC                                                                         0xfb050cUL //Access:RW   DataWidth:0x4    // The initial number of messages that can be sent to the CCFC activity counters interface without receiving any ACK.
+#define TSDM_REG_INIT_CREDIT_CM                                                                              0xfb0510UL //Access:RW   DataWidth:0x4    // The initial number of cycles that can be sent to the CM interface without receiving any ACK in CM block.
+#define TSDM_REG_INIT_CREDIT_CM_RMT_E5                                                                       0xfb0520UL //Access:RW   DataWidth:0x4    // The initial number of cycles that can be sent to a remote CM interface without receiving any ACK in CM block.
+#define TSDM_REG_NUM_OF_DMA_CMD                                                                              0xfb0600UL //Access:RC   DataWidth:0x20   // The number of SDM DMA commands executed.
+#define TSDM_REG_NUM_OF_TIMERS_CMD                                                                           0xfb0604UL //Access:RC   DataWidth:0x20   // The number of SDM timers commands executed.
+#define TSDM_REG_NUM_OF_CCFC_LD_CMD                                                                          0xfb0608UL //Access:RC   DataWidth:0x20   // The number of SDM CCFC load commands executed.
+#define TSDM_REG_NUM_OF_CCFC_AC_CMD                                                                          0xfb060cUL //Access:RC   DataWidth:0x20   // The number of SDM CCFC activity counter commands executed.
+#define TSDM_REG_NUM_OF_TCFC_LD_CMD                                                                          0xfb0610UL //Access:RC   DataWidth:0x20   // The number of SDM TCFC load commands executed.
+#define TSDM_REG_NUM_OF_TCFC_AC_CMD                                                                          0xfb0614UL //Access:RC   DataWidth:0x20   // The number of SDM TCFC activity counter commands executed.
+#define TSDM_REG_NUM_OF_INT_CMD                                                                              0xfb0618UL //Access:RC   DataWidth:0x20   // The number of SDM internal write commands executed.
+#define TSDM_REG_NUM_OF_NOP_CMD                                                                              0xfb061cUL //Access:RC   DataWidth:0x20   // The number of SDM NOP commands executed.
+#define TSDM_REG_NUM_OF_GRC_CMD                                                                              0xfb0620UL //Access:RC   DataWidth:0x20   // The number of GRC master commands executed.
+#define TSDM_REG_NUM_OF_PRM_REQ                                                                              0xfb0624UL //Access:RC   DataWidth:0x20   // The number of packet end messages received on the PRM completion interface.
+#define TSDM_REG_NUM_OF_PXP_ASYNC_REQ                                                                        0xfb0628UL //Access:RC   DataWidth:0x20   // The number of requests received from the pxp async if.
+#define TSDM_REG_NUM_OF_DPM_REQ                                                                              0xfb062cUL //Access:RC   DataWidth:0x20   // The number of DORQ DPM messages received.
+#define TSDM_REG_BRB_ALMOST_FULL                                                                             0xfb0700UL //Access:RW   DataWidth:0x5    // Almost full signal for read data from BRB in DMA_RSP block.
+#define TSDM_REG_PXP_ALMOST_FULL                                                                             0xfb0704UL //Access:RW   DataWidth:0x4    // Almost full signal for read data from pxp in DMA_RSP block.
+#define TSDM_REG_DORQ_ALMOST_FULL                                                                            0xfb0708UL //Access:RW   DataWidth:0x6    // Almost full signal for read data from DORQ in SDM_DORQ block.
+#define TSDM_REG_AGG_INT_CTRL                                                                                0xfb0800UL //Access:RW   DataWidth:0xa    // This array of registers provides controls for each of the aggregated interrupts; The fields are defined as follows: [20:16] Affinity [15:12] NumL2m. [11]    Exclusive. [10]    Core-selection where 0=Core_A and 1=Core_B. [9]     Mode bit where 0=normal and 1=auto-mask-mode. [8]     T-flag which determines if a thread is allocated for this handler in the Storm. [7:0]   EventID which selects the event ID of the associated handler.
+#define TSDM_REG_AGG_INT_CTRL_SIZE                                                                           32
+#define TSDM_REG_AGG_INT_STATE                                                                               0xfb0a00UL //Access:R    DataWidth:0x2    // This array of registers provides access to each of the 32 aggregated interrupt request state machines; The values read from this register mean the following; 00 = IDLE; 01 = PEND; 10 = MASK; 11 = PANDM.
+#define TSDM_REG_AGG_INT_STATE_SIZE                                                                          32
+#define TSDM_REG_QUEUE_FULL                                                                                  0xfb0c00UL //Access:R    DataWidth:0x9    // Input queue fifo full in sdm_inp block.
+#define TSDM_REG_INT_CMPL_PEND_FULL                                                                          0xfb0c04UL //Access:R    DataWidth:0x1    // Internal write completion pending full in internal write block.
+#define TSDM_REG_INT_CPRM_PEND_FULL                                                                          0xfb0c08UL //Access:R    DataWidth:0x1    // Internal write completion parameter pending full in internal write block.
+#define TSDM_REG_QM_FULL                                                                                     0xfb0c0cUL //Access:R    DataWidth:0x1    // QM IF  full in sdm_inp block.
+#define TSDM_REG_DELAY_FIFO_FULL                                                                             0xfb0c10UL //Access:R    DataWidth:0x1    // Delay FIFO  full in sdm_inp block.
+#define TSDM_REG_TIMERS_PEND_FULL                                                                            0xfb0c14UL //Access:R    DataWidth:0x1    // Pending FIFO  full in sdm_timers block.
+#define TSDM_REG_TIMERS_ADDR_FULL                                                                            0xfb0c18UL //Access:R    DataWidth:0x1    // Address FIFO  full in sdm_timers block.
+#define TSDM_REG_RSP_PXP_RDATA_FULL                                                                          0xfb0c1cUL //Access:R    DataWidth:0x1    // PXP rd_data fifo  full in sdm_dma_rsp block.
+#define TSDM_REG_RSP_BRB_RDATA_FULL                                                                          0xfb0c20UL //Access:R    DataWidth:0x1    // BRB read data fifo  full in sdm_dma_rsp block.
+#define TSDM_REG_RSP_INT_RAM_RDATA_FULL                                                                      0xfb0c24UL //Access:R    DataWidth:0x1    // Int_ram rd_data fifo  full in sdm_dma_rsp block.
+#define TSDM_REG_RSP_BRB_PEND_FULL                                                                           0xfb0c28UL //Access:R    DataWidth:0x1    // BRB pending fifo  full in sdm_dma_rsp block.
+#define TSDM_REG_RSP_INT_RAM_PEND_FULL                                                                       0xfb0c2cUL //Access:R    DataWidth:0x1    // Int_ram pending fifo  full in sdm_dma_rsp block.
+#define TSDM_REG_RSP_BRB_IF_FULL                                                                             0xfb0c30UL //Access:R    DataWidth:0x1    // BRB interface is  full in sdm_dma_rsp block.
+#define TSDM_REG_RSP_PXP_IF_FULL                                                                             0xfb0c34UL //Access:R    DataWidth:0x1    // PXP interface is  full in sdm_dma_rsp block.
+#define TSDM_REG_DST_PXP_IMMED_FULL                                                                          0xfb0c38UL //Access:R    DataWidth:0x1    // PXP immediate fifo full in sdm_dma_dst block.
+#define TSDM_REG_DST_PXP_DST_PEND_FULL                                                                       0xfb0c3cUL //Access:R    DataWidth:0x1    // PXP destination pending fifo full in sdm_dma_dst block.
+#define TSDM_REG_DST_PXP_SRC_PEND_FULL                                                                       0xfb0c40UL //Access:R    DataWidth:0x1    // PXP source pending fifo full in sdm_dma_dst block.
+#define TSDM_REG_DST_BRB_SRC_PEND_FULL                                                                       0xfb0c44UL //Access:R    DataWidth:0x1    // BRB source pending fifo full in sdm_dma_dst block.
+#define TSDM_REG_DST_BRB_SRC_ADDR_FULL                                                                       0xfb0c48UL //Access:R    DataWidth:0x1    // BRB source address fifo full in sdm_dma_dst block.
+#define TSDM_REG_DST_PXP_LINK_FULL                                                                           0xfb0c4cUL //Access:R    DataWidth:0x1    // PXP link list full in sdm_dma_dst block.
+#define TSDM_REG_DST_INT_RAM_WAIT_FULL                                                                       0xfb0c50UL //Access:R    DataWidth:0x1    // Int_ram_wait fifo full in sdm_dma_dst block.
+#define TSDM_REG_DST_PAS_BUF_WAIT_FULL                                                                       0xfb0c54UL //Access:R    DataWidth:0x1    // Pas_buf_wait fifo full in sdm_dma_dst block.
+#define TSDM_REG_DST_PXP_IF_FULL                                                                             0xfb0c58UL //Access:R    DataWidth:0x1    // PXP if full in sdm_dma_dst block.
+#define TSDM_REG_DST_INT_RAM_IF_FULL                                                                         0xfb0c5cUL //Access:R    DataWidth:0x1    // Int_ram if full in sdm_dma_dst block.
+#define TSDM_REG_DST_PAS_BUF_IF_FULL                                                                         0xfb0c60UL //Access:R    DataWidth:0x1    // Pas_buf if full in sdm_dma_dst block.
+#define TSDM_REG_SH_DELAY_FULL                                                                               0xfb0c64UL //Access:R    DataWidth:0x1    // Shared delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.
+#define TSDM_REG_CM_DELAY_FULL                                                                               0xfb0c68UL //Access:R    DataWidth:0x1    // CM delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.
+#define TSDM_REG_CMSG_QUE_FULL                                                                               0xfb0c6cUL //Access:R    DataWidth:0x1    // Completion message queue fifo full in sdm_cm block.
+#define TSDM_REG_CCFC_LOAD_PEND_FULL                                                                         0xfb0c70UL //Access:R    DataWidth:0x1    // CCFC load pending fifo full in the CCFC interface  block.
+#define TSDM_REG_TCFC_LOAD_PEND_FULL                                                                         0xfb0c74UL //Access:R    DataWidth:0x1    // TCFC load pending fifo full in the TCFC interface block.
+#define TSDM_REG_ASYNC_HOST_FULL                                                                             0xfb0c78UL //Access:R    DataWidth:0x1    // Async fifo full in sdm_async block.
+#define TSDM_REG_PRM_FIFO_FULL                                                                               0xfb0c7cUL //Access:R    DataWidth:0x1    // PRM FIFO full in PRM interface block.
+#define TSDM_REG_RMT_XCM_FIFO_FULL_K2_E5                                                                     0xfb0c80UL //Access:R    DataWidth:0x1    // Remote XCM FIFO full (exist only in MSDM => XCM interface).
+#define TSDM_REG_RMT_YCM_FIFO_FULL_K2_E5                                                                     0xfb0c84UL //Access:R    DataWidth:0x1    // Remote YCM FIFO full (exist only in MSDM => YCM interface).
+#define TSDM_REG_INT_CMPL_PEND_EMPTY                                                                         0xfb0d00UL //Access:R    DataWidth:0x1    // Internal write completion pending empty in internal write block.
+#define TSDM_REG_INT_CPRM_PEND_EMPTY                                                                         0xfb0d04UL //Access:R    DataWidth:0x1    // Internal write completion parameter pending empty in internal write block.
+#define TSDM_REG_QUEUE_EMPTY                                                                                 0xfb0d08UL //Access:R    DataWidth:0x9    // Input queue fifo empty in sdm_inp block.
+#define TSDM_REG_DELAY_FIFO_EMPTY                                                                            0xfb0d0cUL //Access:R    DataWidth:0x1    // Delay FIFO  empty in sdm_inp block.
+#define TSDM_REG_TIMERS_PEND_EMPTY                                                                           0xfb0d10UL //Access:R    DataWidth:0x1    // Pending FIFO  empty in sdm_timers block.
+#define TSDM_REG_TIMERS_ADDR_EMPTY                                                                           0xfb0d14UL //Access:R    DataWidth:0x1    // Address FIFO  empty in sdm_timers block.
+#define TSDM_REG_RSP_PXP_RDATA_EMPTY                                                                         0xfb0d18UL //Access:R    DataWidth:0x1    // PXP rd_data fifo  empty in sdm_dma_rsp block.
+#define TSDM_REG_RSP_BRB_RDATA_EMPTY                                                                         0xfb0d1cUL //Access:R    DataWidth:0x1    // BRB read data fifo  empty in sdm_dma_rsp block.
+#define TSDM_REG_RSP_INT_RAM_RDATA_EMPTY                                                                     0xfb0d20UL //Access:R    DataWidth:0x1    // Int_ram rd_data fifo  empty in sdm_dma_rsp block.
+#define TSDM_REG_RSP_BRB_PEND_EMPTY                                                                          0xfb0d24UL //Access:R    DataWidth:0x1    // BRB pending fifo  empty in sdm_dma_rsp block.
+#define TSDM_REG_RSP_INT_RAM_PEND_EMPTY                                                                      0xfb0d28UL //Access:R    DataWidth:0x1    // Int_ram pending fifo  empty in sdm_dma_rsp block.
+#define TSDM_REG_DST_PXP_IMMED_EMPTY                                                                         0xfb0d2cUL //Access:R    DataWidth:0x1    // PXP immediate fifo empty in sdm_dma_dst block.
+#define TSDM_REG_DST_PXP_DST_PEND_EMPTY                                                                      0xfb0d30UL //Access:R    DataWidth:0x1    // PXP destination pending fifo empty in sdm_dma_dst block.
+#define TSDM_REG_DST_PXP_SRC_PEND_EMPTY                                                                      0xfb0d34UL //Access:R    DataWidth:0x1    // PXP source pending fifo empty in sdm_dma_dst block.
+#define TSDM_REG_DST_BRB_SRC_PEND_EMPTY                                                                      0xfb0d38UL //Access:R    DataWidth:0x1    // BRB source pending fifo empty in sdm_dma_dst block.
+#define TSDM_REG_DST_BRB_SRC_ADDR_EMPTY                                                                      0xfb0d3cUL //Access:R    DataWidth:0x1    // BRB source address fifo empty in sdm_dma_dst block.
+#define TSDM_REG_DST_PXP_LINK_EMPTY                                                                          0xfb0d40UL //Access:R    DataWidth:0x1    // PXP link list empty in sdm_dma_dst block.
+#define TSDM_REG_DST_INT_RAM_WAIT_EMPTY                                                                      0xfb0d44UL //Access:R    DataWidth:0x1    // Int_ram_wait fifo empty in sdm_dma_dst block.
+#define TSDM_REG_DST_PAS_BUF_WAIT_EMPTY                                                                      0xfb0d48UL //Access:R    DataWidth:0x1    // Pas_buf_wait fifo empty in sdm_dma_dst block.
+#define TSDM_REG_SH_DELAY_EMPTY                                                                              0xfb0d4cUL //Access:R    DataWidth:0x1    // Shared delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.
+#define TSDM_REG_CM_DELAY_EMPTY                                                                              0xfb0d50UL //Access:R    DataWidth:0x1    // CM delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.
+#define TSDM_REG_CMSG_QUE_EMPTY                                                                              0xfb0d54UL //Access:R    DataWidth:0x1    // Completion message queue fifo empty in sdm_dma_dst block.
+#define TSDM_REG_CCFC_LOAD_PEND_EMPTY                                                                        0xfb0d58UL //Access:R    DataWidth:0x1    // CCFC load pending fifo empty in sdm_ccfc block.
+#define TSDM_REG_TCFC_LOAD_PEND_EMPTY                                                                        0xfb0d5cUL //Access:R    DataWidth:0x1    // TCFC load pending fifo empty in sdm_tcfc block.
+#define TSDM_REG_ASYNC_HOST_EMPTY                                                                            0xfb0d60UL //Access:R    DataWidth:0x1    // Async fifo empty in sdm_async block.
+#define TSDM_REG_PRM_FIFO_EMPTY                                                                              0xfb0d64UL //Access:R    DataWidth:0x1    // PRM FIFO empty in sdm_prm_if block.
+#define TSDM_REG_RMT_XCM_FIFO_EMPTY_K2_E5                                                                    0xfb0d68UL //Access:R    DataWidth:0x1    // Remote XCM FIFO empty (exist only within MSDM => XCM path).
+#define TSDM_REG_RMT_YCM_FIFO_EMPTY_K2_E5                                                                    0xfb0d6cUL //Access:R    DataWidth:0x1    // Remote YCM FIFO empty (exist only within MSDM => YCM path).
+#define TSDM_REG_DBG_OUT_DATA                                                                                0xfb0e00UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define TSDM_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define TSDM_REG_DBG_OUT_VALID                                                                               0xfb0e20UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define TSDM_REG_DBG_OUT_FRAME                                                                               0xfb0e24UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define TSDM_REG_DBG_SELECT                                                                                  0xfb0e28UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define TSDM_REG_DBG_DWORD_ENABLE                                                                            0xfb0e2cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define TSDM_REG_DBG_SHIFT                                                                                   0xfb0e30UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define TSDM_REG_DBG_FORCE_VALID                                                                             0xfb0e34UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define TSDM_REG_DBG_FORCE_FRAME                                                                             0xfb0e38UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define TSDM_REG_ASYNC_FIFO                                                                                  0xfb2000UL //Access:WB_R DataWidth:0x49   // Provides read-only access of the PXP-Async input FIFO. Intended for debug purposes.
+#define TSDM_REG_ASYNC_FIFO_SIZE                                                                             116
+#define TSDM_REG_IMMED_FIFO                                                                                  0xfb2400UL //Access:WB_R DataWidth:0x40   // Provides read-only access of the immediate data FIFO. Intended for debug purposes.
+#define TSDM_REG_IMMED_FIFO_SIZE                                                                             38
+#define TSDM_REG_BRB_FIFO                                                                                    0xfb2800UL //Access:WB_R DataWidth:0x86   // Provides read-only access of the BRB response FIFO. Intended for debug purposes.
+#define TSDM_REG_BRB_FIFO_SIZE                                                                               152
+#define TSDM_REG_PXP_FIFO                                                                                    0xfb2c00UL //Access:WB_R DataWidth:0x4a   // Provides read-only access of the PXP response FIFO. Intended for debug purposes.
+#define TSDM_REG_PXP_FIFO_SIZE                                                                               76
+#define TSDM_REG_INT_RAM_FIFO                                                                                0xfb3000UL //Access:WB_R DataWidth:0x41   // Provides read-only access of the internal RAM response FIFO. Intended for debug purposes.
+#define TSDM_REG_INT_RAM_FIFO_SIZE                                                                           76
+#define TSDM_REG_DPM_FIFO                                                                                    0xfb3400UL //Access:WB_R DataWidth:0x51   // Provides read-only access of the DORQ DPM input FIFO. Intended for debug purposes.
+#define TSDM_REG_DPM_FIFO_SIZE                                                                               172
+#define TSDM_REG_EXT_OVERFLOW                                                                                0xfb3800UL //Access:WB_R DataWidth:0x4b   // Provides read-only access of the external store overflow FIFO. Intended for debug purposes.
+#define TSDM_REG_EXT_OVERFLOW_SIZE                                                                           36
+#define TSDM_REG_PRM_FIFO                                                                                    0xfb3c00UL //Access:WB_R DataWidth:0x41   // Provides read-only access of the PRM completion input FIFO. Intended for debug purposes.
+#define TSDM_REG_PRM_FIFO_SIZE                                                                               84
+#define TSDM_REG_TIMERS                                                                                      0xfb4000UL //Access:WB   DataWidth:0x3a   // Provides memory-mapped read/write access to the timers' memory. Intended for debug purposes.
+#define TSDM_REG_TIMERS_SIZE                                                                                 48
+#define TSDM_REG_INP_QUEUE                                                                                   0xfb5000UL //Access:WB   DataWidth:0x40   // Input queue memory. Access only for debugging.
+#define TSDM_REG_INP_QUEUE_SIZE                                                                              416
+#define TSDM_REG_CMSG_QUE                                                                                    0xfb8000UL //Access:WB   DataWidth:0x40   // CM queue memory. Access only for debugging.
+#define TSDM_REG_CMSG_QUE_SIZE                                                                               192
+#define MSDM_REG_ENABLE_IN1                                                                                  0xfc0004UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define MSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN                                                                (0x1<<0) // Enable for input command from STORM.
+  #define MSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN_SHIFT                                                          0
+  #define MSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN                                                             (0x1<<1) // Enable for input data from internal ram interface in DMA_RSP block.
+  #define MSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN_SHIFT                                                       1
+  #define MSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN                                                             (0x1<<2) // Enable for input done from internal ram interface in DMA_RSP block.
+  #define MSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN_SHIFT                                                       2
+  #define MSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN                                                             (0x1<<3) // Enable for input full from internal ram interface in DMA_RSP block.
+  #define MSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN_SHIFT                                                       3
+  #define MSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN                                                             (0x1<<4) // Enable for input done from passive buffer interface in DMA_RSP block.
+  #define MSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN_SHIFT                                                       4
+  #define MSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN                                                             (0x1<<5) // Enable for input full from passive buffer interface in DMA_RSP block.
+  #define MSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN_SHIFT                                                       5
+  #define MSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN                                                                 (0x1<<6) // Enable for input done from pxp-HW interface in DMA_DST block.
+  #define MSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN_SHIFT                                                           6
+  #define MSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN                                                                 (0x1<<7) // Enable for input full from pxp-HW interface in DMA_DST block.
+  #define MSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN_SHIFT                                                           7
+  #define MSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN                                                                 (0x1<<8) // Enable for input data from pxp-HW interface in DMA_RSP block.
+  #define MSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN_SHIFT                                                           8
+  #define MSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN                                                              (0x1<<9) // Enable for input ack from pxp-internal write for SDM_INT block.
+  #define MSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN_SHIFT                                                        9
+  #define MSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN                                                                  (0x1<<10) // Enable for input acknowledge to credit counter from pxp_HW interface.
+  #define MSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN_SHIFT                                                            10
+  #define MSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN                                                                 (0x1<<11) // Enable for input data from BRB interface in DMA_RSP block.
+  #define MSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN_SHIFT                                                           11
+  #define MSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN                                                                  (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
+  #define MSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN_SHIFT                                                            12
+  #define MSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN                                                                  (0x1<<13) // Enable for input completion message from PRM in prm_if block.
+  #define MSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN_SHIFT                                                            13
+  #define MSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN                                                            (0x1<<14) // Enable for input ack to CCFC load credit counter.
+  #define MSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN_SHIFT                                                      14
+  #define MSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN                                                            (0x1<<15) // Enable for input ack to TCFC load credit counter.
+  #define MSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN_SHIFT                                                      15
+  #define MSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN                                                            (0x1<<16) // Enable for input response from CCFC in CCFC block.
+  #define MSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN_SHIFT                                                      16
+  #define MSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN                                                              (0x1<<17) // Enable for input ack to CCFC credit counter on the A/C interface.
+  #define MSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN_SHIFT                                                        17
+  #define MSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN                                                              (0x1<<18) // Enable for input ack to TCFC credit counter on the A/C interface.
+  #define MSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN_SHIFT                                                        18
+  #define MSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN                                                           (0x1<<19) // Enable for input full from qm in SDM_INP block.
+  #define MSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN_SHIFT                                                     19
+#define MSDM_REG_ENABLE_IN2                                                                                  0xfc0008UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define MSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN                                                            (0x1<<0) // Enable for input response from TCFC in TCFC block.
+  #define MSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN_SHIFT                                                      0
+  #define MSDM_REG_ENABLE_IN2_CM_ACK_IN_EN                                                                   (0x1<<1) // Enable for input acknowledge from Cm  in SDM_CM block.
+  #define MSDM_REG_ENABLE_IN2_CM_ACK_IN_EN_SHIFT                                                             1
+  #define MSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN                                                                 (0x1<<2) // Enable for input DPM requests in SDM_DORQ block.
+  #define MSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN_SHIFT                                                           2
+#define MSDM_REG_ENABLE_OUT1                                                                                 0xfc000cUL //Access:RW   DataWidth:0x15   // Multi Field Register.
+  #define MSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN                                                                (0x1<<0) // Enable for output request to pxp internal write for SDM_INT block.
+  #define MSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN_SHIFT                                                          0
+  #define MSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN                                                             (0x1<<1) // Enable for output thread ready to the SEMI.
+  #define MSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN_SHIFT                                                       1
+  #define MSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN                                                             (0x1<<2) // Enable the output thread release to the SEMI.
+  #define MSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN_SHIFT                                                       2
+  #define MSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN                                                              (0x1<<3) // Enable for output load request to CCFC.
+  #define MSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN_SHIFT                                                        3
+  #define MSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN                                                              (0x1<<4) // Enable for output load request to TCFC.
+  #define MSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN_SHIFT                                                        4
+  #define MSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN                                                                (0x1<<5) // Enable for output increment to CCFC activity counter.
+  #define MSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN_SHIFT                                                          5
+  #define MSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN                                                                (0x1<<6) // Enable for output decrement to TCFC activity counter.
+  #define MSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN_SHIFT                                                          6
+  #define MSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN                                                                (0x1<<7) // Enable for output data to pxp-HW interface in DMA_REQ block.
+  #define MSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN_SHIFT                                                          7
+  #define MSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN                                                                (0x1<<8) // Enable for output request to BRB interface in DMA_REQ block.
+  #define MSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN_SHIFT                                                          8
+  #define MSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN                                                                (0x1<<9) // Enable for output write to int_ram in DMA_DST block.
+  #define MSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN_SHIFT                                                          9
+  #define MSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN                                                                (0x1<<10) // Enable for output write topassive buffer in DMA_DST block.
+  #define MSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN_SHIFT                                                          10
+  #define MSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN                                                              (0x1<<11) // Enable for output write to pxp async in DMA_DST block.
+  #define MSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN_SHIFT                                                        11
+  #define MSDM_REG_ENABLE_OUT1_PXP_OUT_EN                                                                    (0x1<<12) // Enable for output write to pxp  in DMA_DST block.
+  #define MSDM_REG_ENABLE_OUT1_PXP_OUT_EN_SHIFT                                                              12
+  #define MSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN                                                               (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
+  #define MSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN_SHIFT                                                         13
+  #define MSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN                                                               (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
+  #define MSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN_SHIFT                                                         14
+  #define MSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN                                                               (0x1<<15) // Enable for output external full to SEMI block.
+  #define MSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN_SHIFT                                                         15
+  #define MSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN                                                           (0x1<<16) // Enable for output done to async PXP host IF.
+  #define MSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN_SHIFT                                                     16
+  #define MSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN                                                           (0x1<<17) // Enable the output done (ack) to PRM.
+  #define MSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN_SHIFT                                                     17
+  #define MSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN                                                                 (0x1<<18) // Enable for output message to CM in SDM_CM block.
+  #define MSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN_SHIFT                                                           18
+  #define MSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN                                                           (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
+  #define MSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN_SHIFT                                                     19
+  #define MSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN                                                           (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
+  #define MSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN_SHIFT                                                     20
+#define MSDM_REG_ENABLE_OUT2                                                                                 0xfc0010UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define MSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN                                                              (0x1<<0) // Enable for output command to qm in SDM_INP block.
+  #define MSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN_SHIFT                                                        0
+  #define MSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN                                                               (0x1<<1) // Enable for VF/PF error valid in DMA_DST block.
+  #define MSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN_SHIFT                                                         1
+  #define MSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN                                                          (0x1<<2) // Enable for DPM request done output in SDM_DORQ block.
+  #define MSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN_SHIFT                                                    2
+#define MSDM_REG_DISABLE_ENGINE                                                                              0xfc0014UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define MSDM_REG_DISABLE_ENGINE_DISABLE_DMA                                                                (0x1<<0) // This bit should be set to disable the DMA exectuion engine from processing DMA commands.
+  #define MSDM_REG_DISABLE_ENGINE_DISABLE_DMA_SHIFT                                                          0
+  #define MSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS                                                             (0x1<<1) // This bit should be set to disable the timers' exectuion engine from processing timers' commands.
+  #define MSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS_SHIFT                                                       1
+  #define MSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD                                                          (0x1<<2) // This bit should be set to disable the CCFC exectuion engine from processing CCFC load commands.
+  #define MSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD_SHIFT                                                    2
+  #define MSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD                                                          (0x1<<3) // This bit should be set to disable the TCFC exectuion engine from processing TCFC load commands.
+  #define MSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD_SHIFT                                                    3
+  #define MSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR                                                             (0x1<<4) // This bit should be set to disable the internal write exectuion engine from processing Internal write commands.
+  #define MSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR_SHIFT                                                       4
+  #define MSDM_REG_DISABLE_ENGINE_DISABLE_NOP                                                                (0x1<<5) // This bit should be set to disable the SDM NOP exectuion engine from processing NOP commands.
+  #define MSDM_REG_DISABLE_ENGINE_DISABLE_NOP_SHIFT                                                          5
+  #define MSDM_REG_DISABLE_ENGINE_DISABLE_GRC                                                                (0x1<<6) // This bit should be set to disable the GRC master exectuion engine from processing GRC master commands.
+  #define MSDM_REG_DISABLE_ENGINE_DISABLE_GRC_SHIFT                                                          6
+  #define MSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC                                                              (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Async requests.
+  #define MSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC_SHIFT                                                        7
+  #define MSDM_REG_DISABLE_ENGINE_DISABLE_PRM                                                                (0x1<<8) // This bit should be set to disable the PRM interface from processing PRM completion commands.
+  #define MSDM_REG_DISABLE_ENGINE_DISABLE_PRM_SHIFT                                                          8
+  #define MSDM_REG_DISABLE_ENGINE_DISABLE_DORQ                                                               (0x1<<9) // This bit should be set to disable the DORQ DPM interface from processing DPM commands.
+  #define MSDM_REG_DISABLE_ENGINE_DISABLE_DORQ_SHIFT                                                         9
+#define MSDM_REG_INT_STS                                                                                     0xfc0040UL //Access:R    DataWidth:0x1c   // Multi Field Register.
+  #define MSDM_REG_INT_STS_ADDRESS_ERROR                                                                     (0x1<<0) // Signals an unknown address to the rf module.
+  #define MSDM_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                               0
+  #define MSDM_REG_INT_STS_INP_QUEUE_ERROR                                                                   (0x1<<1) // Indicates that one of the input queues had a FIFO error.
+  #define MSDM_REG_INT_STS_INP_QUEUE_ERROR_SHIFT                                                             1
+  #define MSDM_REG_INT_STS_DELAY_FIFO_ERROR                                                                  (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
+  #define MSDM_REG_INT_STS_DELAY_FIFO_ERROR_SHIFT                                                            2
+  #define MSDM_REG_INT_STS_ASYNC_HOST_ERROR                                                                  (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
+  #define MSDM_REG_INT_STS_ASYNC_HOST_ERROR_SHIFT                                                            3
+  #define MSDM_REG_INT_STS_PRM_FIFO_ERROR                                                                    (0x1<<4) // FIFO in PRM interface sub-module reported an error.
+  #define MSDM_REG_INT_STS_PRM_FIFO_ERROR_SHIFT                                                              4
+  #define MSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR                                                              (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
+  #define MSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR_SHIFT                                                        5
+  #define MSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR                                                              (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
+  #define MSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR_SHIFT                                                        6
+  #define MSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR                                                            (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
+  #define MSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR_SHIFT                                                      7
+  #define MSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR                                                            (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
+  #define MSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR_SHIFT                                                      8
+  #define MSDM_REG_INT_STS_DST_PXP_IMMED_ERROR                                                               (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
+  #define MSDM_REG_INT_STS_DST_PXP_IMMED_ERROR_SHIFT                                                         9
+  #define MSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR                                                            (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
+  #define MSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR_SHIFT                                                      10
+  #define MSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR                                                            (0x1<<11) // BRB src pend fifo error in DMA_DST block.
+  #define MSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR_SHIFT                                                      11
+  #define MSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR                                                            (0x1<<12) // BRB src addr fifo error in DMA_DST block.
+  #define MSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR_SHIFT                                                      12
+  #define MSDM_REG_INT_STS_RSP_BRB_PEND_ERROR                                                                (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
+  #define MSDM_REG_INT_STS_RSP_BRB_PEND_ERROR_SHIFT                                                          13
+  #define MSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR                                                            (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
+  #define MSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR_SHIFT                                                      14
+  #define MSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR                                                             (0x1<<15) // Read data firo in DMA_RSP block for BRB.
+  #define MSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR_SHIFT                                                       15
+  #define MSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR                                                         (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
+  #define MSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                                   16
+  #define MSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR                                                             (0x1<<17) // PXP read data fifo error in DMA_RSP block.
+  #define MSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR_SHIFT                                                       17
+  #define MSDM_REG_INT_STS_CM_DELAY_ERROR                                                                    (0x1<<18) // Delay CM fifo error in CM block.
+  #define MSDM_REG_INT_STS_CM_DELAY_ERROR_SHIFT                                                              18
+  #define MSDM_REG_INT_STS_SH_DELAY_ERROR                                                                    (0x1<<19) // Delay shared fifo error in CM block.
+  #define MSDM_REG_INT_STS_SH_DELAY_ERROR_SHIFT                                                              19
+  #define MSDM_REG_INT_STS_CMPL_PEND_ERROR                                                                   (0x1<<20) // Error in completion pending FIFO in internal write block.
+  #define MSDM_REG_INT_STS_CMPL_PEND_ERROR_SHIFT                                                             20
+  #define MSDM_REG_INT_STS_CPRM_PEND_ERROR                                                                   (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
+  #define MSDM_REG_INT_STS_CPRM_PEND_ERROR_SHIFT                                                             21
+  #define MSDM_REG_INT_STS_TIMER_ADDR_ERROR                                                                  (0x1<<22) // Address fifo error in timer block.
+  #define MSDM_REG_INT_STS_TIMER_ADDR_ERROR_SHIFT                                                            22
+  #define MSDM_REG_INT_STS_TIMER_PEND_ERROR                                                                  (0x1<<23) // Pending fifo error in timer block.
+  #define MSDM_REG_INT_STS_TIMER_PEND_ERROR_SHIFT                                                            23
+  #define MSDM_REG_INT_STS_DORQ_DPM_ERROR                                                                    (0x1<<24) // Dpm fifo error in dorq I/F block.
+  #define MSDM_REG_INT_STS_DORQ_DPM_ERROR_SHIFT                                                              24
+  #define MSDM_REG_INT_STS_DST_PXP_DONE_ERROR                                                                (0x1<<25) // PXP done fifo error in DMA_dst block.
+  #define MSDM_REG_INT_STS_DST_PXP_DONE_ERROR_SHIFT                                                          25
+  #define MSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR_K2_E5                                                        (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define MSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                                  26
+  #define MSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_K2_E5                                                        (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define MSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                                  27
+#define MSDM_REG_INT_MASK                                                                                    0xfc0044UL //Access:RW   DataWidth:0x1c   // Multi Field Register.
+  #define MSDM_REG_INT_MASK_ADDRESS_ERROR                                                                    (0x1<<0) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.ADDRESS_ERROR .
+  #define MSDM_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                              0
+  #define MSDM_REG_INT_MASK_INP_QUEUE_ERROR                                                                  (0x1<<1) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.INP_QUEUE_ERROR .
+  #define MSDM_REG_INT_MASK_INP_QUEUE_ERROR_SHIFT                                                            1
+  #define MSDM_REG_INT_MASK_DELAY_FIFO_ERROR                                                                 (0x1<<2) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DELAY_FIFO_ERROR .
+  #define MSDM_REG_INT_MASK_DELAY_FIFO_ERROR_SHIFT                                                           2
+  #define MSDM_REG_INT_MASK_ASYNC_HOST_ERROR                                                                 (0x1<<3) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.ASYNC_HOST_ERROR .
+  #define MSDM_REG_INT_MASK_ASYNC_HOST_ERROR_SHIFT                                                           3
+  #define MSDM_REG_INT_MASK_PRM_FIFO_ERROR                                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.PRM_FIFO_ERROR .
+  #define MSDM_REG_INT_MASK_PRM_FIFO_ERROR_SHIFT                                                             4
+  #define MSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR                                                             (0x1<<5) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.CCFC_LOAD_PEND_ERROR .
+  #define MSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR_SHIFT                                                       5
+  #define MSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR                                                             (0x1<<6) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.TCFC_LOAD_PEND_ERROR .
+  #define MSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR_SHIFT                                                       6
+  #define MSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR                                                           (0x1<<7) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DST_INT_RAM_WAIT_ERROR .
+  #define MSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR_SHIFT                                                     7
+  #define MSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR                                                           (0x1<<8) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DST_PAS_BUF_WAIT_ERROR .
+  #define MSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR_SHIFT                                                     8
+  #define MSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR                                                              (0x1<<9) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DST_PXP_IMMED_ERROR .
+  #define MSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR_SHIFT                                                        9
+  #define MSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR                                                           (0x1<<10) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DST_PXP_DST_PEND_ERROR .
+  #define MSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR_SHIFT                                                     10
+  #define MSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR                                                           (0x1<<11) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DST_BRB_SRC_PEND_ERROR .
+  #define MSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR_SHIFT                                                     11
+  #define MSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR                                                           (0x1<<12) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DST_BRB_SRC_ADDR_ERROR .
+  #define MSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR_SHIFT                                                     12
+  #define MSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR                                                               (0x1<<13) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.RSP_BRB_PEND_ERROR .
+  #define MSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR_SHIFT                                                         13
+  #define MSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR                                                           (0x1<<14) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.RSP_INT_RAM_PEND_ERROR .
+  #define MSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR_SHIFT                                                     14
+  #define MSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR                                                            (0x1<<15) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.RSP_BRB_RD_DATA_ERROR .
+  #define MSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR_SHIFT                                                      15
+  #define MSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR                                                        (0x1<<16) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.RSP_INT_RAM_RD_DATA_ERROR .
+  #define MSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                                  16
+  #define MSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR                                                            (0x1<<17) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.RSP_PXP_RD_DATA_ERROR .
+  #define MSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR_SHIFT                                                      17
+  #define MSDM_REG_INT_MASK_CM_DELAY_ERROR                                                                   (0x1<<18) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.CM_DELAY_ERROR .
+  #define MSDM_REG_INT_MASK_CM_DELAY_ERROR_SHIFT                                                             18
+  #define MSDM_REG_INT_MASK_SH_DELAY_ERROR                                                                   (0x1<<19) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.SH_DELAY_ERROR .
+  #define MSDM_REG_INT_MASK_SH_DELAY_ERROR_SHIFT                                                             19
+  #define MSDM_REG_INT_MASK_CMPL_PEND_ERROR                                                                  (0x1<<20) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.CMPL_PEND_ERROR .
+  #define MSDM_REG_INT_MASK_CMPL_PEND_ERROR_SHIFT                                                            20
+  #define MSDM_REG_INT_MASK_CPRM_PEND_ERROR                                                                  (0x1<<21) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.CPRM_PEND_ERROR .
+  #define MSDM_REG_INT_MASK_CPRM_PEND_ERROR_SHIFT                                                            21
+  #define MSDM_REG_INT_MASK_TIMER_ADDR_ERROR                                                                 (0x1<<22) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.TIMER_ADDR_ERROR .
+  #define MSDM_REG_INT_MASK_TIMER_ADDR_ERROR_SHIFT                                                           22
+  #define MSDM_REG_INT_MASK_TIMER_PEND_ERROR                                                                 (0x1<<23) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.TIMER_PEND_ERROR .
+  #define MSDM_REG_INT_MASK_TIMER_PEND_ERROR_SHIFT                                                           23
+  #define MSDM_REG_INT_MASK_DORQ_DPM_ERROR                                                                   (0x1<<24) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DORQ_DPM_ERROR .
+  #define MSDM_REG_INT_MASK_DORQ_DPM_ERROR_SHIFT                                                             24
+  #define MSDM_REG_INT_MASK_DST_PXP_DONE_ERROR                                                               (0x1<<25) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DST_PXP_DONE_ERROR .
+  #define MSDM_REG_INT_MASK_DST_PXP_DONE_ERROR_SHIFT                                                         25
+  #define MSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR_K2_E5                                                       (0x1<<26) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.XCM_RMT_BUFFER_ERROR .
+  #define MSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                                 26
+  #define MSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_K2_E5                                                       (0x1<<27) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.YCM_RMT_BUFFER_ERROR .
+  #define MSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                                 27
+#define MSDM_REG_INT_STS_WR                                                                                  0xfc0048UL //Access:WR   DataWidth:0x1c   // Multi Field Register.
+  #define MSDM_REG_INT_STS_WR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define MSDM_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                            0
+  #define MSDM_REG_INT_STS_WR_INP_QUEUE_ERROR                                                                (0x1<<1) // Indicates that one of the input queues had a FIFO error.
+  #define MSDM_REG_INT_STS_WR_INP_QUEUE_ERROR_SHIFT                                                          1
+  #define MSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR                                                               (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
+  #define MSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR_SHIFT                                                         2
+  #define MSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR                                                               (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
+  #define MSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR_SHIFT                                                         3
+  #define MSDM_REG_INT_STS_WR_PRM_FIFO_ERROR                                                                 (0x1<<4) // FIFO in PRM interface sub-module reported an error.
+  #define MSDM_REG_INT_STS_WR_PRM_FIFO_ERROR_SHIFT                                                           4
+  #define MSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR                                                           (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
+  #define MSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR_SHIFT                                                     5
+  #define MSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR                                                           (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
+  #define MSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR_SHIFT                                                     6
+  #define MSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR                                                         (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
+  #define MSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR_SHIFT                                                   7
+  #define MSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR                                                         (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
+  #define MSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR_SHIFT                                                   8
+  #define MSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR                                                            (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
+  #define MSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR_SHIFT                                                      9
+  #define MSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR                                                         (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
+  #define MSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR_SHIFT                                                   10
+  #define MSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR                                                         (0x1<<11) // BRB src pend fifo error in DMA_DST block.
+  #define MSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR_SHIFT                                                   11
+  #define MSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR                                                         (0x1<<12) // BRB src addr fifo error in DMA_DST block.
+  #define MSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR_SHIFT                                                   12
+  #define MSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR                                                             (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
+  #define MSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR_SHIFT                                                       13
+  #define MSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR                                                         (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
+  #define MSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR_SHIFT                                                   14
+  #define MSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR                                                          (0x1<<15) // Read data firo in DMA_RSP block for BRB.
+  #define MSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR_SHIFT                                                    15
+  #define MSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR                                                      (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
+  #define MSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                                16
+  #define MSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR                                                          (0x1<<17) // PXP read data fifo error in DMA_RSP block.
+  #define MSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR_SHIFT                                                    17
+  #define MSDM_REG_INT_STS_WR_CM_DELAY_ERROR                                                                 (0x1<<18) // Delay CM fifo error in CM block.
+  #define MSDM_REG_INT_STS_WR_CM_DELAY_ERROR_SHIFT                                                           18
+  #define MSDM_REG_INT_STS_WR_SH_DELAY_ERROR                                                                 (0x1<<19) // Delay shared fifo error in CM block.
+  #define MSDM_REG_INT_STS_WR_SH_DELAY_ERROR_SHIFT                                                           19
+  #define MSDM_REG_INT_STS_WR_CMPL_PEND_ERROR                                                                (0x1<<20) // Error in completion pending FIFO in internal write block.
+  #define MSDM_REG_INT_STS_WR_CMPL_PEND_ERROR_SHIFT                                                          20
+  #define MSDM_REG_INT_STS_WR_CPRM_PEND_ERROR                                                                (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
+  #define MSDM_REG_INT_STS_WR_CPRM_PEND_ERROR_SHIFT                                                          21
+  #define MSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR                                                               (0x1<<22) // Address fifo error in timer block.
+  #define MSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR_SHIFT                                                         22
+  #define MSDM_REG_INT_STS_WR_TIMER_PEND_ERROR                                                               (0x1<<23) // Pending fifo error in timer block.
+  #define MSDM_REG_INT_STS_WR_TIMER_PEND_ERROR_SHIFT                                                         23
+  #define MSDM_REG_INT_STS_WR_DORQ_DPM_ERROR                                                                 (0x1<<24) // Dpm fifo error in dorq I/F block.
+  #define MSDM_REG_INT_STS_WR_DORQ_DPM_ERROR_SHIFT                                                           24
+  #define MSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR                                                             (0x1<<25) // PXP done fifo error in DMA_dst block.
+  #define MSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR_SHIFT                                                       25
+  #define MSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR_K2_E5                                                     (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define MSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                               26
+  #define MSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_K2_E5                                                     (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define MSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                               27
+#define MSDM_REG_INT_STS_CLR                                                                                 0xfc004cUL //Access:RC   DataWidth:0x1c   // Multi Field Register.
+  #define MSDM_REG_INT_STS_CLR_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define MSDM_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                           0
+  #define MSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR                                                               (0x1<<1) // Indicates that one of the input queues had a FIFO error.
+  #define MSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR_SHIFT                                                         1
+  #define MSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR                                                              (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
+  #define MSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR_SHIFT                                                        2
+  #define MSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR                                                              (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
+  #define MSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR_SHIFT                                                        3
+  #define MSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR                                                                (0x1<<4) // FIFO in PRM interface sub-module reported an error.
+  #define MSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR_SHIFT                                                          4
+  #define MSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR                                                          (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
+  #define MSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR_SHIFT                                                    5
+  #define MSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR                                                          (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
+  #define MSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR_SHIFT                                                    6
+  #define MSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR                                                        (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
+  #define MSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR_SHIFT                                                  7
+  #define MSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR                                                        (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
+  #define MSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR_SHIFT                                                  8
+  #define MSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR                                                           (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
+  #define MSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR_SHIFT                                                     9
+  #define MSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR                                                        (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
+  #define MSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR_SHIFT                                                  10
+  #define MSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR                                                        (0x1<<11) // BRB src pend fifo error in DMA_DST block.
+  #define MSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR_SHIFT                                                  11
+  #define MSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR                                                        (0x1<<12) // BRB src addr fifo error in DMA_DST block.
+  #define MSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR_SHIFT                                                  12
+  #define MSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR                                                            (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
+  #define MSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR_SHIFT                                                      13
+  #define MSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR                                                        (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
+  #define MSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR_SHIFT                                                  14
+  #define MSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR                                                         (0x1<<15) // Read data firo in DMA_RSP block for BRB.
+  #define MSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR_SHIFT                                                   15
+  #define MSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR                                                     (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
+  #define MSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                               16
+  #define MSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR                                                         (0x1<<17) // PXP read data fifo error in DMA_RSP block.
+  #define MSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR_SHIFT                                                   17
+  #define MSDM_REG_INT_STS_CLR_CM_DELAY_ERROR                                                                (0x1<<18) // Delay CM fifo error in CM block.
+  #define MSDM_REG_INT_STS_CLR_CM_DELAY_ERROR_SHIFT                                                          18
+  #define MSDM_REG_INT_STS_CLR_SH_DELAY_ERROR                                                                (0x1<<19) // Delay shared fifo error in CM block.
+  #define MSDM_REG_INT_STS_CLR_SH_DELAY_ERROR_SHIFT                                                          19
+  #define MSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR                                                               (0x1<<20) // Error in completion pending FIFO in internal write block.
+  #define MSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR_SHIFT                                                         20
+  #define MSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR                                                               (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
+  #define MSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR_SHIFT                                                         21
+  #define MSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR                                                              (0x1<<22) // Address fifo error in timer block.
+  #define MSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR_SHIFT                                                        22
+  #define MSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR                                                              (0x1<<23) // Pending fifo error in timer block.
+  #define MSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR_SHIFT                                                        23
+  #define MSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR                                                                (0x1<<24) // Dpm fifo error in dorq I/F block.
+  #define MSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR_SHIFT                                                          24
+  #define MSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR                                                            (0x1<<25) // PXP done fifo error in DMA_dst block.
+  #define MSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR_SHIFT                                                      25
+  #define MSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR_K2_E5                                                    (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define MSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                              26
+  #define MSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_K2_E5                                                    (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define MSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                              27
+#define MSDM_REG_PRTY_MASK_H_0_BB_K2                                                                         0xfc0204UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define MSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2                                                     (0x1<<0) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define MSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2_SHIFT                                               0
+  #define MSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2                                                     (0x1<<1) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define MSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2_SHIFT                                               1
+  #define MSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2                                                     (0x1<<2) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define MSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2_SHIFT                                               2
+  #define MSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2                                                     (0x1<<3) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define MSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2_SHIFT                                               3
+  #define MSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2                                                     (0x1<<4) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define MSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT                                               4
+  #define MSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                     (0x1<<5) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define MSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                               5
+  #define MSDM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_K2                                                     (0x1<<6) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
+  #define MSDM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_K2_SHIFT                                               6
+  #define MSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                     (0x1<<7) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define MSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                               7
+  #define MSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                     (0x1<<8) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define MSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                               8
+  #define MSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                     (0x1<<9) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define MSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                               9
+  #define MSDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2                                                     (0x1<<10) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
+  #define MSDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2_SHIFT                                               10
+#define MSDM_REG_MEM_ECC_EVENTS_BB_K2                                                                        0xfc0210UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define MSDM_REG_TIMER_TICK                                                                                  0xfc0400UL //Access:RW   DataWidth:0x20   // Defines the number of system clock cycles that are used to define a timers clock tick cycle. Note: The minimal legal value for this register is 25, lower values can cause timers functionality issues.
+#define MSDM_REG_TIMERS_TICK_ENABLE                                                                          0xfc0404UL //Access:RW   DataWidth:0x1    // Enable for tick counter.
+#define MSDM_REG_OPERATION_GEN                                                                               0xfc0408UL //Access:W    DataWidth:0x14   // This register is used to assert a completion operation of choice; It includes the following completion fields: bits 19:16 are Trig; bits 15:0 are CompParams. Note that trigger types 3,5 or 8 are not supported by this interface as they require a completion message. If there is an attempt to assert an OperationGen with Trig = 3,5 or 8, the operation will be voided.
+#define MSDM_REG_GRC_PRIVILEGE_LEVEL                                                                         0xfc040cUL //Access:RW   DataWidth:0x2    // This register defines the PRV (privilege level) field within the FID structure of the SDM GRC master request.
+#define MSDM_REG_CM_MSG_CNT_ADDRESS                                                                          0xfc0410UL //Access:RW   DataWidth:0xf    // The internal RAM address for storing the shadow of the CM completion message counter.
+#define MSDM_REG_DORQ_DPM_START_ADDR                                                                         0xfc0414UL //Access:RW   DataWidth:0xf    // The start address in the internal RAM for DORQ DPM messages.
+#define MSDM_REG_RR_COMPLETE_REQ                                                                             0xfc0418UL //Access:R    DataWidth:0xa    // Provides read access to the round robin arbiter used for all completion write requests  in the completion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b7-PRM interface; b8-CCFC load; b9-TCFC load.
+#define MSDM_REG_RR_PTR_REQ                                                                                  0xfc041cUL //Access:R    DataWidth:0x9    // Provides read access to the round robin arbiter for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-int_wr; b7-prm; b8-grc_master.
+#define MSDM_REG_INT_RAM_RR_REQ                                                                              0xfc0420UL //Access:R    DataWidth:0x4    // Provides read access to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination;b2-PXP source/destination;b3-BRB source.
+#define MSDM_REG_INP_QUEUE_ERR_VECT                                                                          0xfc0424UL //Access:R    DataWidth:0x9    // This register is intended to be read in the event of an inp_queue_error interrupt.  It contains a vector with a bit per input queue. Clearing the interrupt causes this vector to be cleared. Errors on multiple FIFOs will be aggregated between interrupt clear requests.
+#define MSDM_REG_ASYNC_CMSG_ALLOC_LIMIT                                                                      0xfc0428UL //Access:RW   DataWidth:0x5    // This register defines the maximum number of completion messages that can be allocated to PXP-Async transactions at any given time. If the PXP-Async interface attempts to reserve beyond this limit, it will be held off until the situation is resolved.
+#define MSDM_REG_ECO_RESERVED                                                                                0xfc042cUL //Access:RW   DataWidth:0x8    // Reserved bits for ECO.
+#define MSDM_REG_INIT_CREDIT_PXP                                                                             0xfc0500UL //Access:RW   DataWidth:0x3    // The initial number of messages that can be sent to the pxp interface without receiving any ACK.
+#define MSDM_REG_INIT_CREDIT_PCI                                                                             0xfc0504UL //Access:RW   DataWidth:0x2    // The initial number of messages that can be sent to the PCI-Switch on the internal write interface without receiving any ACK.
+#define MSDM_REG_INIT_CREDIT_TCFC_AC                                                                         0xfc0508UL //Access:RW   DataWidth:0x4    // The initial number of messages that can be sent to the TCFC activity counters interface without receiving any ACK.
+#define MSDM_REG_INIT_CREDIT_CCFC_AC                                                                         0xfc050cUL //Access:RW   DataWidth:0x4    // The initial number of messages that can be sent to the CCFC activity counters interface without receiving any ACK.
+#define MSDM_REG_INIT_CREDIT_CM                                                                              0xfc0510UL //Access:RW   DataWidth:0x4    // The initial number of cycles that can be sent to the CM interface without receiving any ACK in CM block.
+#define MSDM_REG_INIT_CREDIT_CM_RMT                                                                          0xfc0520UL //Access:RW   DataWidth:0x4    // The initial number of cycles that can be sent to a remote CM interface without receiving any ACK in CM block.
+#define MSDM_REG_INIT_CREDIT_CM_RMT_SIZE_BB_K2                                                               2
+#define MSDM_REG_INIT_CREDIT_CM_RMT_SIZE_E5                                                                  3
+#define MSDM_REG_NUM_OF_DMA_CMD                                                                              0xfc0600UL //Access:RC   DataWidth:0x20   // The number of SDM DMA commands executed.
+#define MSDM_REG_NUM_OF_TIMERS_CMD                                                                           0xfc0604UL //Access:RC   DataWidth:0x20   // The number of SDM timers commands executed.
+#define MSDM_REG_NUM_OF_CCFC_LD_CMD                                                                          0xfc0608UL //Access:RC   DataWidth:0x20   // The number of SDM CCFC load commands executed.
+#define MSDM_REG_NUM_OF_CCFC_AC_CMD                                                                          0xfc060cUL //Access:RC   DataWidth:0x20   // The number of SDM CCFC activity counter commands executed.
+#define MSDM_REG_NUM_OF_TCFC_LD_CMD                                                                          0xfc0610UL //Access:RC   DataWidth:0x20   // The number of SDM TCFC load commands executed.
+#define MSDM_REG_NUM_OF_TCFC_AC_CMD                                                                          0xfc0614UL //Access:RC   DataWidth:0x20   // The number of SDM TCFC activity counter commands executed.
+#define MSDM_REG_NUM_OF_INT_CMD                                                                              0xfc0618UL //Access:RC   DataWidth:0x20   // The number of SDM internal write commands executed.
+#define MSDM_REG_NUM_OF_NOP_CMD                                                                              0xfc061cUL //Access:RC   DataWidth:0x20   // The number of SDM NOP commands executed.
+#define MSDM_REG_NUM_OF_GRC_CMD                                                                              0xfc0620UL //Access:RC   DataWidth:0x20   // The number of GRC master commands executed.
+#define MSDM_REG_NUM_OF_PRM_REQ                                                                              0xfc0624UL //Access:RC   DataWidth:0x20   // The number of packet end messages received on the PRM completion interface.
+#define MSDM_REG_NUM_OF_PXP_ASYNC_REQ                                                                        0xfc0628UL //Access:RC   DataWidth:0x20   // The number of requests received from the pxp async if.
+#define MSDM_REG_NUM_OF_DPM_REQ                                                                              0xfc062cUL //Access:RC   DataWidth:0x20   // The number of DORQ DPM messages received.
+#define MSDM_REG_BRB_ALMOST_FULL                                                                             0xfc0700UL //Access:RW   DataWidth:0x5    // Almost full signal for read data from BRB in DMA_RSP block.
+#define MSDM_REG_PXP_ALMOST_FULL                                                                             0xfc0704UL //Access:RW   DataWidth:0x4    // Almost full signal for read data from pxp in DMA_RSP block.
+#define MSDM_REG_DORQ_ALMOST_FULL                                                                            0xfc0708UL //Access:RW   DataWidth:0x6    // Almost full signal for read data from DORQ in SDM_DORQ block.
+#define MSDM_REG_AGG_INT_CTRL                                                                                0xfc0800UL //Access:RW   DataWidth:0xa    // This array of registers provides controls for each of the aggregated interrupts; The fields are defined as follows: [20:16] Affinity [15:12] NumL2m. [11]    Exclusive. [10]    Core-selection where 0=Core_A and 1=Core_B. [9]     Mode bit where 0=normal and 1=auto-mask-mode. [8]     T-flag which determines if a thread is allocated for this handler in the Storm. [7:0]   EventID which selects the event ID of the associated handler.
+#define MSDM_REG_AGG_INT_CTRL_SIZE                                                                           32
+#define MSDM_REG_AGG_INT_STATE                                                                               0xfc0a00UL //Access:R    DataWidth:0x2    // This array of registers provides access to each of the 32 aggregated interrupt request state machines; The values read from this register mean the following; 00 = IDLE; 01 = PEND; 10 = MASK; 11 = PANDM.
+#define MSDM_REG_AGG_INT_STATE_SIZE                                                                          32
+#define MSDM_REG_QUEUE_FULL                                                                                  0xfc0c00UL //Access:R    DataWidth:0x9    // Input queue fifo full in sdm_inp block.
+#define MSDM_REG_INT_CMPL_PEND_FULL                                                                          0xfc0c04UL //Access:R    DataWidth:0x1    // Internal write completion pending full in internal write block.
+#define MSDM_REG_INT_CPRM_PEND_FULL                                                                          0xfc0c08UL //Access:R    DataWidth:0x1    // Internal write completion parameter pending full in internal write block.
+#define MSDM_REG_QM_FULL                                                                                     0xfc0c0cUL //Access:R    DataWidth:0x1    // QM IF  full in sdm_inp block.
+#define MSDM_REG_DELAY_FIFO_FULL                                                                             0xfc0c10UL //Access:R    DataWidth:0x1    // Delay FIFO  full in sdm_inp block.
+#define MSDM_REG_TIMERS_PEND_FULL                                                                            0xfc0c14UL //Access:R    DataWidth:0x1    // Pending FIFO  full in sdm_timers block.
+#define MSDM_REG_TIMERS_ADDR_FULL                                                                            0xfc0c18UL //Access:R    DataWidth:0x1    // Address FIFO  full in sdm_timers block.
+#define MSDM_REG_RSP_PXP_RDATA_FULL                                                                          0xfc0c1cUL //Access:R    DataWidth:0x1    // PXP rd_data fifo  full in sdm_dma_rsp block.
+#define MSDM_REG_RSP_BRB_RDATA_FULL                                                                          0xfc0c20UL //Access:R    DataWidth:0x1    // BRB read data fifo  full in sdm_dma_rsp block.
+#define MSDM_REG_RSP_INT_RAM_RDATA_FULL                                                                      0xfc0c24UL //Access:R    DataWidth:0x1    // Int_ram rd_data fifo  full in sdm_dma_rsp block.
+#define MSDM_REG_RSP_BRB_PEND_FULL                                                                           0xfc0c28UL //Access:R    DataWidth:0x1    // BRB pending fifo  full in sdm_dma_rsp block.
+#define MSDM_REG_RSP_INT_RAM_PEND_FULL                                                                       0xfc0c2cUL //Access:R    DataWidth:0x1    // Int_ram pending fifo  full in sdm_dma_rsp block.
+#define MSDM_REG_RSP_BRB_IF_FULL                                                                             0xfc0c30UL //Access:R    DataWidth:0x1    // BRB interface is  full in sdm_dma_rsp block.
+#define MSDM_REG_RSP_PXP_IF_FULL                                                                             0xfc0c34UL //Access:R    DataWidth:0x1    // PXP interface is  full in sdm_dma_rsp block.
+#define MSDM_REG_DST_PXP_IMMED_FULL                                                                          0xfc0c38UL //Access:R    DataWidth:0x1    // PXP immediate fifo full in sdm_dma_dst block.
+#define MSDM_REG_DST_PXP_DST_PEND_FULL                                                                       0xfc0c3cUL //Access:R    DataWidth:0x1    // PXP destination pending fifo full in sdm_dma_dst block.
+#define MSDM_REG_DST_PXP_SRC_PEND_FULL                                                                       0xfc0c40UL //Access:R    DataWidth:0x1    // PXP source pending fifo full in sdm_dma_dst block.
+#define MSDM_REG_DST_BRB_SRC_PEND_FULL                                                                       0xfc0c44UL //Access:R    DataWidth:0x1    // BRB source pending fifo full in sdm_dma_dst block.
+#define MSDM_REG_DST_BRB_SRC_ADDR_FULL                                                                       0xfc0c48UL //Access:R    DataWidth:0x1    // BRB source address fifo full in sdm_dma_dst block.
+#define MSDM_REG_DST_PXP_LINK_FULL                                                                           0xfc0c4cUL //Access:R    DataWidth:0x1    // PXP link list full in sdm_dma_dst block.
+#define MSDM_REG_DST_INT_RAM_WAIT_FULL                                                                       0xfc0c50UL //Access:R    DataWidth:0x1    // Int_ram_wait fifo full in sdm_dma_dst block.
+#define MSDM_REG_DST_PAS_BUF_WAIT_FULL                                                                       0xfc0c54UL //Access:R    DataWidth:0x1    // Pas_buf_wait fifo full in sdm_dma_dst block.
+#define MSDM_REG_DST_PXP_IF_FULL                                                                             0xfc0c58UL //Access:R    DataWidth:0x1    // PXP if full in sdm_dma_dst block.
+#define MSDM_REG_DST_INT_RAM_IF_FULL                                                                         0xfc0c5cUL //Access:R    DataWidth:0x1    // Int_ram if full in sdm_dma_dst block.
+#define MSDM_REG_DST_PAS_BUF_IF_FULL                                                                         0xfc0c60UL //Access:R    DataWidth:0x1    // Pas_buf if full in sdm_dma_dst block.
+#define MSDM_REG_SH_DELAY_FULL                                                                               0xfc0c64UL //Access:R    DataWidth:0x1    // Shared delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.
+#define MSDM_REG_CM_DELAY_FULL                                                                               0xfc0c68UL //Access:R    DataWidth:0x1    // CM delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.
+#define MSDM_REG_CMSG_QUE_FULL                                                                               0xfc0c6cUL //Access:R    DataWidth:0x1    // Completion message queue fifo full in sdm_cm block.
+#define MSDM_REG_CCFC_LOAD_PEND_FULL                                                                         0xfc0c70UL //Access:R    DataWidth:0x1    // CCFC load pending fifo full in the CCFC interface  block.
+#define MSDM_REG_TCFC_LOAD_PEND_FULL                                                                         0xfc0c74UL //Access:R    DataWidth:0x1    // TCFC load pending fifo full in the TCFC interface block.
+#define MSDM_REG_ASYNC_HOST_FULL                                                                             0xfc0c78UL //Access:R    DataWidth:0x1    // Async fifo full in sdm_async block.
+#define MSDM_REG_PRM_FIFO_FULL                                                                               0xfc0c7cUL //Access:R    DataWidth:0x1    // PRM FIFO full in PRM interface block.
+#define MSDM_REG_RMT_XCM_FIFO_FULL_K2_E5                                                                     0xfc0c80UL //Access:R    DataWidth:0x1    // Remote XCM FIFO full (exist only in MSDM => XCM interface).
+#define MSDM_REG_RMT_YCM_FIFO_FULL_K2_E5                                                                     0xfc0c84UL //Access:R    DataWidth:0x1    // Remote YCM FIFO full (exist only in MSDM => YCM interface).
+#define MSDM_REG_INT_CMPL_PEND_EMPTY                                                                         0xfc0d00UL //Access:R    DataWidth:0x1    // Internal write completion pending empty in internal write block.
+#define MSDM_REG_INT_CPRM_PEND_EMPTY                                                                         0xfc0d04UL //Access:R    DataWidth:0x1    // Internal write completion parameter pending empty in internal write block.
+#define MSDM_REG_QUEUE_EMPTY                                                                                 0xfc0d08UL //Access:R    DataWidth:0x9    // Input queue fifo empty in sdm_inp block.
+#define MSDM_REG_DELAY_FIFO_EMPTY                                                                            0xfc0d0cUL //Access:R    DataWidth:0x1    // Delay FIFO  empty in sdm_inp block.
+#define MSDM_REG_TIMERS_PEND_EMPTY                                                                           0xfc0d10UL //Access:R    DataWidth:0x1    // Pending FIFO  empty in sdm_timers block.
+#define MSDM_REG_TIMERS_ADDR_EMPTY                                                                           0xfc0d14UL //Access:R    DataWidth:0x1    // Address FIFO  empty in sdm_timers block.
+#define MSDM_REG_RSP_PXP_RDATA_EMPTY                                                                         0xfc0d18UL //Access:R    DataWidth:0x1    // PXP rd_data fifo  empty in sdm_dma_rsp block.
+#define MSDM_REG_RSP_BRB_RDATA_EMPTY                                                                         0xfc0d1cUL //Access:R    DataWidth:0x1    // BRB read data fifo  empty in sdm_dma_rsp block.
+#define MSDM_REG_RSP_INT_RAM_RDATA_EMPTY                                                                     0xfc0d20UL //Access:R    DataWidth:0x1    // Int_ram rd_data fifo  empty in sdm_dma_rsp block.
+#define MSDM_REG_RSP_BRB_PEND_EMPTY                                                                          0xfc0d24UL //Access:R    DataWidth:0x1    // BRB pending fifo  empty in sdm_dma_rsp block.
+#define MSDM_REG_RSP_INT_RAM_PEND_EMPTY                                                                      0xfc0d28UL //Access:R    DataWidth:0x1    // Int_ram pending fifo  empty in sdm_dma_rsp block.
+#define MSDM_REG_DST_PXP_IMMED_EMPTY                                                                         0xfc0d2cUL //Access:R    DataWidth:0x1    // PXP immediate fifo empty in sdm_dma_dst block.
+#define MSDM_REG_DST_PXP_DST_PEND_EMPTY                                                                      0xfc0d30UL //Access:R    DataWidth:0x1    // PXP destination pending fifo empty in sdm_dma_dst block.
+#define MSDM_REG_DST_PXP_SRC_PEND_EMPTY                                                                      0xfc0d34UL //Access:R    DataWidth:0x1    // PXP source pending fifo empty in sdm_dma_dst block.
+#define MSDM_REG_DST_BRB_SRC_PEND_EMPTY                                                                      0xfc0d38UL //Access:R    DataWidth:0x1    // BRB source pending fifo empty in sdm_dma_dst block.
+#define MSDM_REG_DST_BRB_SRC_ADDR_EMPTY                                                                      0xfc0d3cUL //Access:R    DataWidth:0x1    // BRB source address fifo empty in sdm_dma_dst block.
+#define MSDM_REG_DST_PXP_LINK_EMPTY                                                                          0xfc0d40UL //Access:R    DataWidth:0x1    // PXP link list empty in sdm_dma_dst block.
+#define MSDM_REG_DST_INT_RAM_WAIT_EMPTY                                                                      0xfc0d44UL //Access:R    DataWidth:0x1    // Int_ram_wait fifo empty in sdm_dma_dst block.
+#define MSDM_REG_DST_PAS_BUF_WAIT_EMPTY                                                                      0xfc0d48UL //Access:R    DataWidth:0x1    // Pas_buf_wait fifo empty in sdm_dma_dst block.
+#define MSDM_REG_SH_DELAY_EMPTY                                                                              0xfc0d4cUL //Access:R    DataWidth:0x1    // Shared delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.
+#define MSDM_REG_CM_DELAY_EMPTY                                                                              0xfc0d50UL //Access:R    DataWidth:0x1    // CM delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.
+#define MSDM_REG_CMSG_QUE_EMPTY                                                                              0xfc0d54UL //Access:R    DataWidth:0x1    // Completion message queue fifo empty in sdm_dma_dst block.
+#define MSDM_REG_CCFC_LOAD_PEND_EMPTY                                                                        0xfc0d58UL //Access:R    DataWidth:0x1    // CCFC load pending fifo empty in sdm_ccfc block.
+#define MSDM_REG_TCFC_LOAD_PEND_EMPTY                                                                        0xfc0d5cUL //Access:R    DataWidth:0x1    // TCFC load pending fifo empty in sdm_tcfc block.
+#define MSDM_REG_ASYNC_HOST_EMPTY                                                                            0xfc0d60UL //Access:R    DataWidth:0x1    // Async fifo empty in sdm_async block.
+#define MSDM_REG_PRM_FIFO_EMPTY                                                                              0xfc0d64UL //Access:R    DataWidth:0x1    // PRM FIFO empty in sdm_prm_if block.
+#define MSDM_REG_RMT_XCM_FIFO_EMPTY_K2_E5                                                                    0xfc0d68UL //Access:R    DataWidth:0x1    // Remote XCM FIFO empty (exist only within MSDM => XCM path).
+#define MSDM_REG_RMT_YCM_FIFO_EMPTY_K2_E5                                                                    0xfc0d6cUL //Access:R    DataWidth:0x1    // Remote YCM FIFO empty (exist only within MSDM => YCM path).
+#define MSDM_REG_DBG_OUT_DATA                                                                                0xfc0e00UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define MSDM_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define MSDM_REG_DBG_OUT_VALID                                                                               0xfc0e20UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define MSDM_REG_DBG_OUT_FRAME                                                                               0xfc0e24UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define MSDM_REG_DBG_SELECT                                                                                  0xfc0e28UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define MSDM_REG_DBG_DWORD_ENABLE                                                                            0xfc0e2cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define MSDM_REG_DBG_SHIFT                                                                                   0xfc0e30UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define MSDM_REG_DBG_FORCE_VALID                                                                             0xfc0e34UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define MSDM_REG_DBG_FORCE_FRAME                                                                             0xfc0e38UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define MSDM_REG_ASYNC_FIFO                                                                                  0xfc2000UL //Access:WB_R DataWidth:0x49   // Provides read-only access of the PXP-Async input FIFO. Intended for debug purposes.
+#define MSDM_REG_ASYNC_FIFO_SIZE                                                                             116
+#define MSDM_REG_IMMED_FIFO                                                                                  0xfc2400UL //Access:WB_R DataWidth:0x40   // Provides read-only access of the immediate data FIFO. Intended for debug purposes.
+#define MSDM_REG_IMMED_FIFO_SIZE                                                                             38
+#define MSDM_REG_BRB_FIFO                                                                                    0xfc2800UL //Access:WB_R DataWidth:0x86   // Provides read-only access of the BRB response FIFO. Intended for debug purposes.
+#define MSDM_REG_BRB_FIFO_SIZE                                                                               152
+#define MSDM_REG_PXP_FIFO                                                                                    0xfc2c00UL //Access:WB_R DataWidth:0x4a   // Provides read-only access of the PXP response FIFO. Intended for debug purposes.
+#define MSDM_REG_PXP_FIFO_SIZE                                                                               76
+#define MSDM_REG_INT_RAM_FIFO                                                                                0xfc3000UL //Access:WB_R DataWidth:0x41   // Provides read-only access of the internal RAM response FIFO. Intended for debug purposes.
+#define MSDM_REG_INT_RAM_FIFO_SIZE                                                                           76
+#define MSDM_REG_DPM_FIFO                                                                                    0xfc3400UL //Access:WB_R DataWidth:0x51   // Provides read-only access of the DORQ DPM input FIFO. Intended for debug purposes.
+#define MSDM_REG_DPM_FIFO_SIZE                                                                               172
+#define MSDM_REG_EXT_OVERFLOW                                                                                0xfc3800UL //Access:WB_R DataWidth:0x4b   // Provides read-only access of the external store overflow FIFO. Intended for debug purposes.
+#define MSDM_REG_EXT_OVERFLOW_SIZE                                                                           36
+#define MSDM_REG_PRM_FIFO                                                                                    0xfc3c00UL //Access:WB_R DataWidth:0x41   // Provides read-only access of the PRM completion input FIFO. Intended for debug purposes.
+#define MSDM_REG_PRM_FIFO_SIZE                                                                               84
+#define MSDM_REG_TIMERS                                                                                      0xfc4000UL //Access:WB   DataWidth:0x3a   // Provides memory-mapped read/write access to the timers' memory. Intended for debug purposes.
+#define MSDM_REG_TIMERS_SIZE                                                                                 48
+#define MSDM_REG_INP_QUEUE                                                                                   0xfc5000UL //Access:WB   DataWidth:0x40   // Input queue memory. Access only for debugging.
+#define MSDM_REG_INP_QUEUE_SIZE                                                                              416
+#define MSDM_REG_CMSG_QUE                                                                                    0xfc8000UL //Access:WB   DataWidth:0x40   // CM queue memory. Access only for debugging.
+#define MSDM_REG_CMSG_QUE_SIZE                                                                               576
+#define USDM_REG_ENABLE_IN1                                                                                  0xfd0004UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define USDM_REG_ENABLE_IN1_EXT_STORE_IN_EN                                                                (0x1<<0) // Enable for input command from STORM.
+  #define USDM_REG_ENABLE_IN1_EXT_STORE_IN_EN_SHIFT                                                          0
+  #define USDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN                                                             (0x1<<1) // Enable for input data from internal ram interface in DMA_RSP block.
+  #define USDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN_SHIFT                                                       1
+  #define USDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN                                                             (0x1<<2) // Enable for input done from internal ram interface in DMA_RSP block.
+  #define USDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN_SHIFT                                                       2
+  #define USDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN                                                             (0x1<<3) // Enable for input full from internal ram interface in DMA_RSP block.
+  #define USDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN_SHIFT                                                       3
+  #define USDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN                                                             (0x1<<4) // Enable for input done from passive buffer interface in DMA_RSP block.
+  #define USDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN_SHIFT                                                       4
+  #define USDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN                                                             (0x1<<5) // Enable for input full from passive buffer interface in DMA_RSP block.
+  #define USDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN_SHIFT                                                       5
+  #define USDM_REG_ENABLE_IN1_PXP_DONE_IN_EN                                                                 (0x1<<6) // Enable for input done from pxp-HW interface in DMA_DST block.
+  #define USDM_REG_ENABLE_IN1_PXP_DONE_IN_EN_SHIFT                                                           6
+  #define USDM_REG_ENABLE_IN1_PXP_FULL_IN_EN                                                                 (0x1<<7) // Enable for input full from pxp-HW interface in DMA_DST block.
+  #define USDM_REG_ENABLE_IN1_PXP_FULL_IN_EN_SHIFT                                                           7
+  #define USDM_REG_ENABLE_IN1_PXP_DATA_IN_EN                                                                 (0x1<<8) // Enable for input data from pxp-HW interface in DMA_RSP block.
+  #define USDM_REG_ENABLE_IN1_PXP_DATA_IN_EN_SHIFT                                                           8
+  #define USDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN                                                              (0x1<<9) // Enable for input ack from pxp-internal write for SDM_INT block.
+  #define USDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN_SHIFT                                                        9
+  #define USDM_REG_ENABLE_IN1_PXP_ACK_IN_EN                                                                  (0x1<<10) // Enable for input acknowledge to credit counter from pxp_HW interface.
+  #define USDM_REG_ENABLE_IN1_PXP_ACK_IN_EN_SHIFT                                                            10
+  #define USDM_REG_ENABLE_IN1_BRB_DATA_IN_EN                                                                 (0x1<<11) // Enable for input data from BRB interface in DMA_RSP block.
+  #define USDM_REG_ENABLE_IN1_BRB_DATA_IN_EN_SHIFT                                                           11
+  #define USDM_REG_ENABLE_IN1_PXP_REQ_IN_EN                                                                  (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
+  #define USDM_REG_ENABLE_IN1_PXP_REQ_IN_EN_SHIFT                                                            12
+  #define USDM_REG_ENABLE_IN1_PRM_REQ_IN_EN                                                                  (0x1<<13) // Enable for input completion message from PRM in prm_if block.
+  #define USDM_REG_ENABLE_IN1_PRM_REQ_IN_EN_SHIFT                                                            13
+  #define USDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN                                                            (0x1<<14) // Enable for input ack to CCFC load credit counter.
+  #define USDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN_SHIFT                                                      14
+  #define USDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN                                                            (0x1<<15) // Enable for input ack to TCFC load credit counter.
+  #define USDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN_SHIFT                                                      15
+  #define USDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN                                                            (0x1<<16) // Enable for input response from CCFC in CCFC block.
+  #define USDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN_SHIFT                                                      16
+  #define USDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN                                                              (0x1<<17) // Enable for input ack to CCFC credit counter on the A/C interface.
+  #define USDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN_SHIFT                                                        17
+  #define USDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN                                                              (0x1<<18) // Enable for input ack to TCFC credit counter on the A/C interface.
+  #define USDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN_SHIFT                                                        18
+  #define USDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN                                                           (0x1<<19) // Enable for input full from qm in SDM_INP block.
+  #define USDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN_SHIFT                                                     19
+#define USDM_REG_ENABLE_IN2                                                                                  0xfd0008UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define USDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN                                                            (0x1<<0) // Enable for input response from TCFC in TCFC block.
+  #define USDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN_SHIFT                                                      0
+  #define USDM_REG_ENABLE_IN2_CM_ACK_IN_EN                                                                   (0x1<<1) // Enable for input acknowledge from Cm  in SDM_CM block.
+  #define USDM_REG_ENABLE_IN2_CM_ACK_IN_EN_SHIFT                                                             1
+  #define USDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN                                                                 (0x1<<2) // Enable for input DPM requests in SDM_DORQ block.
+  #define USDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN_SHIFT                                                           2
+#define USDM_REG_ENABLE_OUT1                                                                                 0xfd000cUL //Access:RW   DataWidth:0x15   // Multi Field Register.
+  #define USDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN                                                                (0x1<<0) // Enable for output request to pxp internal write for SDM_INT block.
+  #define USDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN_SHIFT                                                          0
+  #define USDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN                                                             (0x1<<1) // Enable for output thread ready to the SEMI.
+  #define USDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN_SHIFT                                                       1
+  #define USDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN                                                             (0x1<<2) // Enable the output thread release to the SEMI.
+  #define USDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN_SHIFT                                                       2
+  #define USDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN                                                              (0x1<<3) // Enable for output load request to CCFC.
+  #define USDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN_SHIFT                                                        3
+  #define USDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN                                                              (0x1<<4) // Enable for output load request to TCFC.
+  #define USDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN_SHIFT                                                        4
+  #define USDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN                                                                (0x1<<5) // Enable for output increment to CCFC activity counter.
+  #define USDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN_SHIFT                                                          5
+  #define USDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN                                                                (0x1<<6) // Enable for output decrement to TCFC activity counter.
+  #define USDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN_SHIFT                                                          6
+  #define USDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN                                                                (0x1<<7) // Enable for output data to pxp-HW interface in DMA_REQ block.
+  #define USDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN_SHIFT                                                          7
+  #define USDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN                                                                (0x1<<8) // Enable for output request to BRB interface in DMA_REQ block.
+  #define USDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN_SHIFT                                                          8
+  #define USDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN                                                                (0x1<<9) // Enable for output write to int_ram in DMA_DST block.
+  #define USDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN_SHIFT                                                          9
+  #define USDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN                                                                (0x1<<10) // Enable for output write topassive buffer in DMA_DST block.
+  #define USDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN_SHIFT                                                          10
+  #define USDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN                                                              (0x1<<11) // Enable for output write to pxp async in DMA_DST block.
+  #define USDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN_SHIFT                                                        11
+  #define USDM_REG_ENABLE_OUT1_PXP_OUT_EN                                                                    (0x1<<12) // Enable for output write to pxp  in DMA_DST block.
+  #define USDM_REG_ENABLE_OUT1_PXP_OUT_EN_SHIFT                                                              12
+  #define USDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN                                                               (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
+  #define USDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN_SHIFT                                                         13
+  #define USDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN                                                               (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
+  #define USDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN_SHIFT                                                         14
+  #define USDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN                                                               (0x1<<15) // Enable for output external full to SEMI block.
+  #define USDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN_SHIFT                                                         15
+  #define USDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN                                                           (0x1<<16) // Enable for output done to async PXP host IF.
+  #define USDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN_SHIFT                                                     16
+  #define USDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN                                                           (0x1<<17) // Enable the output done (ack) to PRM.
+  #define USDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN_SHIFT                                                     17
+  #define USDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN                                                                 (0x1<<18) // Enable for output message to CM in SDM_CM block.
+  #define USDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN_SHIFT                                                           18
+  #define USDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN                                                           (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
+  #define USDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN_SHIFT                                                     19
+  #define USDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN                                                           (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
+  #define USDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN_SHIFT                                                     20
+#define USDM_REG_ENABLE_OUT2                                                                                 0xfd0010UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define USDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN                                                              (0x1<<0) // Enable for output command to qm in SDM_INP block.
+  #define USDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN_SHIFT                                                        0
+  #define USDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN                                                               (0x1<<1) // Enable for VF/PF error valid in DMA_DST block.
+  #define USDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN_SHIFT                                                         1
+  #define USDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN                                                          (0x1<<2) // Enable for DPM request done output in SDM_DORQ block.
+  #define USDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN_SHIFT                                                    2
+#define USDM_REG_DISABLE_ENGINE                                                                              0xfd0014UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define USDM_REG_DISABLE_ENGINE_DISABLE_DMA                                                                (0x1<<0) // This bit should be set to disable the DMA exectuion engine from processing DMA commands.
+  #define USDM_REG_DISABLE_ENGINE_DISABLE_DMA_SHIFT                                                          0
+  #define USDM_REG_DISABLE_ENGINE_DISABLE_TIMERS                                                             (0x1<<1) // This bit should be set to disable the timers' exectuion engine from processing timers' commands.
+  #define USDM_REG_DISABLE_ENGINE_DISABLE_TIMERS_SHIFT                                                       1
+  #define USDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD                                                          (0x1<<2) // This bit should be set to disable the CCFC exectuion engine from processing CCFC load commands.
+  #define USDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD_SHIFT                                                    2
+  #define USDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD                                                          (0x1<<3) // This bit should be set to disable the TCFC exectuion engine from processing TCFC load commands.
+  #define USDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD_SHIFT                                                    3
+  #define USDM_REG_DISABLE_ENGINE_DISABLE_INT_WR                                                             (0x1<<4) // This bit should be set to disable the internal write exectuion engine from processing Internal write commands.
+  #define USDM_REG_DISABLE_ENGINE_DISABLE_INT_WR_SHIFT                                                       4
+  #define USDM_REG_DISABLE_ENGINE_DISABLE_NOP                                                                (0x1<<5) // This bit should be set to disable the SDM NOP exectuion engine from processing NOP commands.
+  #define USDM_REG_DISABLE_ENGINE_DISABLE_NOP_SHIFT                                                          5
+  #define USDM_REG_DISABLE_ENGINE_DISABLE_GRC                                                                (0x1<<6) // This bit should be set to disable the GRC master exectuion engine from processing GRC master commands.
+  #define USDM_REG_DISABLE_ENGINE_DISABLE_GRC_SHIFT                                                          6
+  #define USDM_REG_DISABLE_ENGINE_DISABLE_ASYNC                                                              (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Async requests.
+  #define USDM_REG_DISABLE_ENGINE_DISABLE_ASYNC_SHIFT                                                        7
+  #define USDM_REG_DISABLE_ENGINE_DISABLE_PRM                                                                (0x1<<8) // This bit should be set to disable the PRM interface from processing PRM completion commands.
+  #define USDM_REG_DISABLE_ENGINE_DISABLE_PRM_SHIFT                                                          8
+  #define USDM_REG_DISABLE_ENGINE_DISABLE_DORQ                                                               (0x1<<9) // This bit should be set to disable the DORQ DPM interface from processing DPM commands.
+  #define USDM_REG_DISABLE_ENGINE_DISABLE_DORQ_SHIFT                                                         9
+#define USDM_REG_INT_STS                                                                                     0xfd0040UL //Access:R    DataWidth:0x1c   // Multi Field Register.
+  #define USDM_REG_INT_STS_ADDRESS_ERROR                                                                     (0x1<<0) // Signals an unknown address to the rf module.
+  #define USDM_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                               0
+  #define USDM_REG_INT_STS_INP_QUEUE_ERROR                                                                   (0x1<<1) // Indicates that one of the input queues had a FIFO error.
+  #define USDM_REG_INT_STS_INP_QUEUE_ERROR_SHIFT                                                             1
+  #define USDM_REG_INT_STS_DELAY_FIFO_ERROR                                                                  (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
+  #define USDM_REG_INT_STS_DELAY_FIFO_ERROR_SHIFT                                                            2
+  #define USDM_REG_INT_STS_ASYNC_HOST_ERROR                                                                  (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
+  #define USDM_REG_INT_STS_ASYNC_HOST_ERROR_SHIFT                                                            3
+  #define USDM_REG_INT_STS_PRM_FIFO_ERROR                                                                    (0x1<<4) // FIFO in PRM interface sub-module reported an error.
+  #define USDM_REG_INT_STS_PRM_FIFO_ERROR_SHIFT                                                              4
+  #define USDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR                                                              (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
+  #define USDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR_SHIFT                                                        5
+  #define USDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR                                                              (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
+  #define USDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR_SHIFT                                                        6
+  #define USDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR                                                            (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
+  #define USDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR_SHIFT                                                      7
+  #define USDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR                                                            (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
+  #define USDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR_SHIFT                                                      8
+  #define USDM_REG_INT_STS_DST_PXP_IMMED_ERROR                                                               (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
+  #define USDM_REG_INT_STS_DST_PXP_IMMED_ERROR_SHIFT                                                         9
+  #define USDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR                                                            (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
+  #define USDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR_SHIFT                                                      10
+  #define USDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR                                                            (0x1<<11) // BRB src pend fifo error in DMA_DST block.
+  #define USDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR_SHIFT                                                      11
+  #define USDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR                                                            (0x1<<12) // BRB src addr fifo error in DMA_DST block.
+  #define USDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR_SHIFT                                                      12
+  #define USDM_REG_INT_STS_RSP_BRB_PEND_ERROR                                                                (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
+  #define USDM_REG_INT_STS_RSP_BRB_PEND_ERROR_SHIFT                                                          13
+  #define USDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR                                                            (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
+  #define USDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR_SHIFT                                                      14
+  #define USDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR                                                             (0x1<<15) // Read data firo in DMA_RSP block for BRB.
+  #define USDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR_SHIFT                                                       15
+  #define USDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR                                                         (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
+  #define USDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                                   16
+  #define USDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR                                                             (0x1<<17) // PXP read data fifo error in DMA_RSP block.
+  #define USDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR_SHIFT                                                       17
+  #define USDM_REG_INT_STS_CM_DELAY_ERROR                                                                    (0x1<<18) // Delay CM fifo error in CM block.
+  #define USDM_REG_INT_STS_CM_DELAY_ERROR_SHIFT                                                              18
+  #define USDM_REG_INT_STS_SH_DELAY_ERROR                                                                    (0x1<<19) // Delay shared fifo error in CM block.
+  #define USDM_REG_INT_STS_SH_DELAY_ERROR_SHIFT                                                              19
+  #define USDM_REG_INT_STS_CMPL_PEND_ERROR                                                                   (0x1<<20) // Error in completion pending FIFO in internal write block.
+  #define USDM_REG_INT_STS_CMPL_PEND_ERROR_SHIFT                                                             20
+  #define USDM_REG_INT_STS_CPRM_PEND_ERROR                                                                   (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
+  #define USDM_REG_INT_STS_CPRM_PEND_ERROR_SHIFT                                                             21
+  #define USDM_REG_INT_STS_TIMER_ADDR_ERROR                                                                  (0x1<<22) // Address fifo error in timer block.
+  #define USDM_REG_INT_STS_TIMER_ADDR_ERROR_SHIFT                                                            22
+  #define USDM_REG_INT_STS_TIMER_PEND_ERROR                                                                  (0x1<<23) // Pending fifo error in timer block.
+  #define USDM_REG_INT_STS_TIMER_PEND_ERROR_SHIFT                                                            23
+  #define USDM_REG_INT_STS_DORQ_DPM_ERROR                                                                    (0x1<<24) // Dpm fifo error in dorq I/F block.
+  #define USDM_REG_INT_STS_DORQ_DPM_ERROR_SHIFT                                                              24
+  #define USDM_REG_INT_STS_DST_PXP_DONE_ERROR                                                                (0x1<<25) // PXP done fifo error in DMA_dst block.
+  #define USDM_REG_INT_STS_DST_PXP_DONE_ERROR_SHIFT                                                          25
+  #define USDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR_K2_E5                                                        (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define USDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                                  26
+  #define USDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_K2_E5                                                        (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define USDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                                  27
+#define USDM_REG_INT_MASK                                                                                    0xfd0044UL //Access:RW   DataWidth:0x1c   // Multi Field Register.
+  #define USDM_REG_INT_MASK_ADDRESS_ERROR                                                                    (0x1<<0) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.ADDRESS_ERROR .
+  #define USDM_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                              0
+  #define USDM_REG_INT_MASK_INP_QUEUE_ERROR                                                                  (0x1<<1) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.INP_QUEUE_ERROR .
+  #define USDM_REG_INT_MASK_INP_QUEUE_ERROR_SHIFT                                                            1
+  #define USDM_REG_INT_MASK_DELAY_FIFO_ERROR                                                                 (0x1<<2) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DELAY_FIFO_ERROR .
+  #define USDM_REG_INT_MASK_DELAY_FIFO_ERROR_SHIFT                                                           2
+  #define USDM_REG_INT_MASK_ASYNC_HOST_ERROR                                                                 (0x1<<3) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.ASYNC_HOST_ERROR .
+  #define USDM_REG_INT_MASK_ASYNC_HOST_ERROR_SHIFT                                                           3
+  #define USDM_REG_INT_MASK_PRM_FIFO_ERROR                                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.PRM_FIFO_ERROR .
+  #define USDM_REG_INT_MASK_PRM_FIFO_ERROR_SHIFT                                                             4
+  #define USDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR                                                             (0x1<<5) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.CCFC_LOAD_PEND_ERROR .
+  #define USDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR_SHIFT                                                       5
+  #define USDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR                                                             (0x1<<6) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.TCFC_LOAD_PEND_ERROR .
+  #define USDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR_SHIFT                                                       6
+  #define USDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR                                                           (0x1<<7) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DST_INT_RAM_WAIT_ERROR .
+  #define USDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR_SHIFT                                                     7
+  #define USDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR                                                           (0x1<<8) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DST_PAS_BUF_WAIT_ERROR .
+  #define USDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR_SHIFT                                                     8
+  #define USDM_REG_INT_MASK_DST_PXP_IMMED_ERROR                                                              (0x1<<9) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DST_PXP_IMMED_ERROR .
+  #define USDM_REG_INT_MASK_DST_PXP_IMMED_ERROR_SHIFT                                                        9
+  #define USDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR                                                           (0x1<<10) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DST_PXP_DST_PEND_ERROR .
+  #define USDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR_SHIFT                                                     10
+  #define USDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR                                                           (0x1<<11) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DST_BRB_SRC_PEND_ERROR .
+  #define USDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR_SHIFT                                                     11
+  #define USDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR                                                           (0x1<<12) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DST_BRB_SRC_ADDR_ERROR .
+  #define USDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR_SHIFT                                                     12
+  #define USDM_REG_INT_MASK_RSP_BRB_PEND_ERROR                                                               (0x1<<13) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.RSP_BRB_PEND_ERROR .
+  #define USDM_REG_INT_MASK_RSP_BRB_PEND_ERROR_SHIFT                                                         13
+  #define USDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR                                                           (0x1<<14) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.RSP_INT_RAM_PEND_ERROR .
+  #define USDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR_SHIFT                                                     14
+  #define USDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR                                                            (0x1<<15) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.RSP_BRB_RD_DATA_ERROR .
+  #define USDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR_SHIFT                                                      15
+  #define USDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR                                                        (0x1<<16) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.RSP_INT_RAM_RD_DATA_ERROR .
+  #define USDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                                  16
+  #define USDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR                                                            (0x1<<17) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.RSP_PXP_RD_DATA_ERROR .
+  #define USDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR_SHIFT                                                      17
+  #define USDM_REG_INT_MASK_CM_DELAY_ERROR                                                                   (0x1<<18) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.CM_DELAY_ERROR .
+  #define USDM_REG_INT_MASK_CM_DELAY_ERROR_SHIFT                                                             18
+  #define USDM_REG_INT_MASK_SH_DELAY_ERROR                                                                   (0x1<<19) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.SH_DELAY_ERROR .
+  #define USDM_REG_INT_MASK_SH_DELAY_ERROR_SHIFT                                                             19
+  #define USDM_REG_INT_MASK_CMPL_PEND_ERROR                                                                  (0x1<<20) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.CMPL_PEND_ERROR .
+  #define USDM_REG_INT_MASK_CMPL_PEND_ERROR_SHIFT                                                            20
+  #define USDM_REG_INT_MASK_CPRM_PEND_ERROR                                                                  (0x1<<21) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.CPRM_PEND_ERROR .
+  #define USDM_REG_INT_MASK_CPRM_PEND_ERROR_SHIFT                                                            21
+  #define USDM_REG_INT_MASK_TIMER_ADDR_ERROR                                                                 (0x1<<22) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.TIMER_ADDR_ERROR .
+  #define USDM_REG_INT_MASK_TIMER_ADDR_ERROR_SHIFT                                                           22
+  #define USDM_REG_INT_MASK_TIMER_PEND_ERROR                                                                 (0x1<<23) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.TIMER_PEND_ERROR .
+  #define USDM_REG_INT_MASK_TIMER_PEND_ERROR_SHIFT                                                           23
+  #define USDM_REG_INT_MASK_DORQ_DPM_ERROR                                                                   (0x1<<24) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DORQ_DPM_ERROR .
+  #define USDM_REG_INT_MASK_DORQ_DPM_ERROR_SHIFT                                                             24
+  #define USDM_REG_INT_MASK_DST_PXP_DONE_ERROR                                                               (0x1<<25) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DST_PXP_DONE_ERROR .
+  #define USDM_REG_INT_MASK_DST_PXP_DONE_ERROR_SHIFT                                                         25
+  #define USDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR_K2_E5                                                       (0x1<<26) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.XCM_RMT_BUFFER_ERROR .
+  #define USDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                                 26
+  #define USDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_K2_E5                                                       (0x1<<27) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.YCM_RMT_BUFFER_ERROR .
+  #define USDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                                 27
+#define USDM_REG_INT_STS_WR                                                                                  0xfd0048UL //Access:WR   DataWidth:0x1c   // Multi Field Register.
+  #define USDM_REG_INT_STS_WR_ADDRESS_ERROR                                                                  (0x1<<0) // Signals an unknown address to the rf module.
+  #define USDM_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                            0
+  #define USDM_REG_INT_STS_WR_INP_QUEUE_ERROR                                                                (0x1<<1) // Indicates that one of the input queues had a FIFO error.
+  #define USDM_REG_INT_STS_WR_INP_QUEUE_ERROR_SHIFT                                                          1
+  #define USDM_REG_INT_STS_WR_DELAY_FIFO_ERROR                                                               (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
+  #define USDM_REG_INT_STS_WR_DELAY_FIFO_ERROR_SHIFT                                                         2
+  #define USDM_REG_INT_STS_WR_ASYNC_HOST_ERROR                                                               (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
+  #define USDM_REG_INT_STS_WR_ASYNC_HOST_ERROR_SHIFT                                                         3
+  #define USDM_REG_INT_STS_WR_PRM_FIFO_ERROR                                                                 (0x1<<4) // FIFO in PRM interface sub-module reported an error.
+  #define USDM_REG_INT_STS_WR_PRM_FIFO_ERROR_SHIFT                                                           4
+  #define USDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR                                                           (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
+  #define USDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR_SHIFT                                                     5
+  #define USDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR                                                           (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
+  #define USDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR_SHIFT                                                     6
+  #define USDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR                                                         (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
+  #define USDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR_SHIFT                                                   7
+  #define USDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR                                                         (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
+  #define USDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR_SHIFT                                                   8
+  #define USDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR                                                            (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
+  #define USDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR_SHIFT                                                      9
+  #define USDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR                                                         (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
+  #define USDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR_SHIFT                                                   10
+  #define USDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR                                                         (0x1<<11) // BRB src pend fifo error in DMA_DST block.
+  #define USDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR_SHIFT                                                   11
+  #define USDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR                                                         (0x1<<12) // BRB src addr fifo error in DMA_DST block.
+  #define USDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR_SHIFT                                                   12
+  #define USDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR                                                             (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
+  #define USDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR_SHIFT                                                       13
+  #define USDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR                                                         (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
+  #define USDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR_SHIFT                                                   14
+  #define USDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR                                                          (0x1<<15) // Read data firo in DMA_RSP block for BRB.
+  #define USDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR_SHIFT                                                    15
+  #define USDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR                                                      (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
+  #define USDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                                16
+  #define USDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR                                                          (0x1<<17) // PXP read data fifo error in DMA_RSP block.
+  #define USDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR_SHIFT                                                    17
+  #define USDM_REG_INT_STS_WR_CM_DELAY_ERROR                                                                 (0x1<<18) // Delay CM fifo error in CM block.
+  #define USDM_REG_INT_STS_WR_CM_DELAY_ERROR_SHIFT                                                           18
+  #define USDM_REG_INT_STS_WR_SH_DELAY_ERROR                                                                 (0x1<<19) // Delay shared fifo error in CM block.
+  #define USDM_REG_INT_STS_WR_SH_DELAY_ERROR_SHIFT                                                           19
+  #define USDM_REG_INT_STS_WR_CMPL_PEND_ERROR                                                                (0x1<<20) // Error in completion pending FIFO in internal write block.
+  #define USDM_REG_INT_STS_WR_CMPL_PEND_ERROR_SHIFT                                                          20
+  #define USDM_REG_INT_STS_WR_CPRM_PEND_ERROR                                                                (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
+  #define USDM_REG_INT_STS_WR_CPRM_PEND_ERROR_SHIFT                                                          21
+  #define USDM_REG_INT_STS_WR_TIMER_ADDR_ERROR                                                               (0x1<<22) // Address fifo error in timer block.
+  #define USDM_REG_INT_STS_WR_TIMER_ADDR_ERROR_SHIFT                                                         22
+  #define USDM_REG_INT_STS_WR_TIMER_PEND_ERROR                                                               (0x1<<23) // Pending fifo error in timer block.
+  #define USDM_REG_INT_STS_WR_TIMER_PEND_ERROR_SHIFT                                                         23
+  #define USDM_REG_INT_STS_WR_DORQ_DPM_ERROR                                                                 (0x1<<24) // Dpm fifo error in dorq I/F block.
+  #define USDM_REG_INT_STS_WR_DORQ_DPM_ERROR_SHIFT                                                           24
+  #define USDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR                                                             (0x1<<25) // PXP done fifo error in DMA_dst block.
+  #define USDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR_SHIFT                                                       25
+  #define USDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR_K2_E5                                                     (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define USDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                               26
+  #define USDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_K2_E5                                                     (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define USDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                               27
+#define USDM_REG_INT_STS_CLR                                                                                 0xfd004cUL //Access:RC   DataWidth:0x1c   // Multi Field Register.
+  #define USDM_REG_INT_STS_CLR_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define USDM_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                           0
+  #define USDM_REG_INT_STS_CLR_INP_QUEUE_ERROR                                                               (0x1<<1) // Indicates that one of the input queues had a FIFO error.
+  #define USDM_REG_INT_STS_CLR_INP_QUEUE_ERROR_SHIFT                                                         1
+  #define USDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR                                                              (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
+  #define USDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR_SHIFT                                                        2
+  #define USDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR                                                              (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
+  #define USDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR_SHIFT                                                        3
+  #define USDM_REG_INT_STS_CLR_PRM_FIFO_ERROR                                                                (0x1<<4) // FIFO in PRM interface sub-module reported an error.
+  #define USDM_REG_INT_STS_CLR_PRM_FIFO_ERROR_SHIFT                                                          4
+  #define USDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR                                                          (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
+  #define USDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR_SHIFT                                                    5
+  #define USDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR                                                          (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
+  #define USDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR_SHIFT                                                    6
+  #define USDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR                                                        (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
+  #define USDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR_SHIFT                                                  7
+  #define USDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR                                                        (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
+  #define USDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR_SHIFT                                                  8
+  #define USDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR                                                           (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
+  #define USDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR_SHIFT                                                     9
+  #define USDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR                                                        (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
+  #define USDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR_SHIFT                                                  10
+  #define USDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR                                                        (0x1<<11) // BRB src pend fifo error in DMA_DST block.
+  #define USDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR_SHIFT                                                  11
+  #define USDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR                                                        (0x1<<12) // BRB src addr fifo error in DMA_DST block.
+  #define USDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR_SHIFT                                                  12
+  #define USDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR                                                            (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
+  #define USDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR_SHIFT                                                      13
+  #define USDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR                                                        (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
+  #define USDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR_SHIFT                                                  14
+  #define USDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR                                                         (0x1<<15) // Read data firo in DMA_RSP block for BRB.
+  #define USDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR_SHIFT                                                   15
+  #define USDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR                                                     (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
+  #define USDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                               16
+  #define USDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR                                                         (0x1<<17) // PXP read data fifo error in DMA_RSP block.
+  #define USDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR_SHIFT                                                   17
+  #define USDM_REG_INT_STS_CLR_CM_DELAY_ERROR                                                                (0x1<<18) // Delay CM fifo error in CM block.
+  #define USDM_REG_INT_STS_CLR_CM_DELAY_ERROR_SHIFT                                                          18
+  #define USDM_REG_INT_STS_CLR_SH_DELAY_ERROR                                                                (0x1<<19) // Delay shared fifo error in CM block.
+  #define USDM_REG_INT_STS_CLR_SH_DELAY_ERROR_SHIFT                                                          19
+  #define USDM_REG_INT_STS_CLR_CMPL_PEND_ERROR                                                               (0x1<<20) // Error in completion pending FIFO in internal write block.
+  #define USDM_REG_INT_STS_CLR_CMPL_PEND_ERROR_SHIFT                                                         20
+  #define USDM_REG_INT_STS_CLR_CPRM_PEND_ERROR                                                               (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
+  #define USDM_REG_INT_STS_CLR_CPRM_PEND_ERROR_SHIFT                                                         21
+  #define USDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR                                                              (0x1<<22) // Address fifo error in timer block.
+  #define USDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR_SHIFT                                                        22
+  #define USDM_REG_INT_STS_CLR_TIMER_PEND_ERROR                                                              (0x1<<23) // Pending fifo error in timer block.
+  #define USDM_REG_INT_STS_CLR_TIMER_PEND_ERROR_SHIFT                                                        23
+  #define USDM_REG_INT_STS_CLR_DORQ_DPM_ERROR                                                                (0x1<<24) // Dpm fifo error in dorq I/F block.
+  #define USDM_REG_INT_STS_CLR_DORQ_DPM_ERROR_SHIFT                                                          24
+  #define USDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR                                                            (0x1<<25) // PXP done fifo error in DMA_dst block.
+  #define USDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR_SHIFT                                                      25
+  #define USDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR_K2_E5                                                    (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define USDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                              26
+  #define USDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_K2_E5                                                    (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
+  #define USDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT                                              27
+#define USDM_REG_PRTY_MASK_H_0_BB_K2                                                                         0xfd0204UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define USDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2                                                     (0x1<<0) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define USDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2_SHIFT                                               0
+  #define USDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2                                                     (0x1<<1) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define USDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2_SHIFT                                               1
+  #define USDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2                                                     (0x1<<2) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define USDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2_SHIFT                                               2
+  #define USDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2                                                     (0x1<<3) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define USDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT                                               3
+  #define USDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                     (0x1<<4) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define USDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                               4
+  #define USDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2                                                     (0x1<<5) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
+  #define USDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2_SHIFT                                               5
+  #define USDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                     (0x1<<6) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define USDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                               6
+  #define USDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                     (0x1<<7) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define USDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                               7
+  #define USDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                     (0x1<<8) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define USDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                               8
+  #define USDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2                                                     (0x1<<9) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define USDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2_SHIFT                                               9
+#define USDM_REG_MEM_ECC_EVENTS_BB_K2                                                                        0xfd0210UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define USDM_REG_TIMER_TICK                                                                                  0xfd0400UL //Access:RW   DataWidth:0x20   // Defines the number of system clock cycles that are used to define a timers clock tick cycle. Note: The minimal legal value for this register is 25, lower values can cause timers functionality issues.
+#define USDM_REG_TIMERS_TICK_ENABLE                                                                          0xfd0404UL //Access:RW   DataWidth:0x1    // Enable for tick counter.
+#define USDM_REG_OPERATION_GEN                                                                               0xfd0408UL //Access:W    DataWidth:0x14   // This register is used to assert a completion operation of choice; It includes the following completion fields: bits 19:16 are Trig; bits 15:0 are CompParams. Note that trigger types 3,5 or 8 are not supported by this interface as they require a completion message. If there is an attempt to assert an OperationGen with Trig = 3,5 or 8, the operation will be voided.
+#define USDM_REG_GRC_PRIVILEGE_LEVEL                                                                         0xfd040cUL //Access:RW   DataWidth:0x2    // This register defines the PRV (privilege level) field within the FID structure of the SDM GRC master request.
+#define USDM_REG_CM_MSG_CNT_ADDRESS                                                                          0xfd0410UL //Access:RW   DataWidth:0xf    // The internal RAM address for storing the shadow of the CM completion message counter.
+#define USDM_REG_DORQ_DPM_START_ADDR                                                                         0xfd0414UL //Access:RW   DataWidth:0xf    // The start address in the internal RAM for DORQ DPM messages.
+#define USDM_REG_RR_COMPLETE_REQ                                                                             0xfd0418UL //Access:R    DataWidth:0xa    // Provides read access to the round robin arbiter used for all completion write requests  in the completion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b7-PRM interface; b8-CCFC load; b9-TCFC load.
+#define USDM_REG_RR_PTR_REQ                                                                                  0xfd041cUL //Access:R    DataWidth:0x9    // Provides read access to the round robin arbiter for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-int_wr; b7-prm; b8-grc_master.
+#define USDM_REG_INT_RAM_RR_REQ                                                                              0xfd0420UL //Access:R    DataWidth:0x4    // Provides read access to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination;b2-PXP source/destination;b3-BRB source.
+#define USDM_REG_INP_QUEUE_ERR_VECT                                                                          0xfd0424UL //Access:R    DataWidth:0x9    // This register is intended to be read in the event of an inp_queue_error interrupt.  It contains a vector with a bit per input queue. Clearing the interrupt causes this vector to be cleared. Errors on multiple FIFOs will be aggregated between interrupt clear requests.
+#define USDM_REG_ASYNC_CMSG_ALLOC_LIMIT                                                                      0xfd0428UL //Access:RW   DataWidth:0x5    // This register defines the maximum number of completion messages that can be allocated to PXP-Async transactions at any given time. If the PXP-Async interface attempts to reserve beyond this limit, it will be held off until the situation is resolved.
+#define USDM_REG_ECO_RESERVED                                                                                0xfd042cUL //Access:RW   DataWidth:0x8    // Reserved bits for ECO.
+#define USDM_REG_INIT_CREDIT_PXP                                                                             0xfd0500UL //Access:RW   DataWidth:0x3    // The initial number of messages that can be sent to the pxp interface without receiving any ACK.
+#define USDM_REG_INIT_CREDIT_PCI                                                                             0xfd0504UL //Access:RW   DataWidth:0x2    // The initial number of messages that can be sent to the PCI-Switch on the internal write interface without receiving any ACK.
+#define USDM_REG_INIT_CREDIT_TCFC_AC                                                                         0xfd0508UL //Access:RW   DataWidth:0x4    // The initial number of messages that can be sent to the TCFC activity counters interface without receiving any ACK.
+#define USDM_REG_INIT_CREDIT_CCFC_AC                                                                         0xfd050cUL //Access:RW   DataWidth:0x4    // The initial number of messages that can be sent to the CCFC activity counters interface without receiving any ACK.
+#define USDM_REG_INIT_CREDIT_CM                                                                              0xfd0510UL //Access:RW   DataWidth:0x4    // The initial number of cycles that can be sent to the CM interface without receiving any ACK in CM block.
+#define USDM_REG_INIT_CREDIT_CM_RMT                                                                          0xfd0520UL //Access:RW   DataWidth:0x4    // The initial number of cycles that can be sent to a remote CM interface without receiving any ACK in CM block.
+#define USDM_REG_INIT_CREDIT_CM_RMT_SIZE                                                                     2
+#define USDM_REG_NUM_OF_DMA_CMD                                                                              0xfd0600UL //Access:RC   DataWidth:0x20   // The number of SDM DMA commands executed.
+#define USDM_REG_NUM_OF_TIMERS_CMD                                                                           0xfd0604UL //Access:RC   DataWidth:0x20   // The number of SDM timers commands executed.
+#define USDM_REG_NUM_OF_CCFC_LD_CMD                                                                          0xfd0608UL //Access:RC   DataWidth:0x20   // The number of SDM CCFC load commands executed.
+#define USDM_REG_NUM_OF_CCFC_AC_CMD                                                                          0xfd060cUL //Access:RC   DataWidth:0x20   // The number of SDM CCFC activity counter commands executed.
+#define USDM_REG_NUM_OF_TCFC_LD_CMD                                                                          0xfd0610UL //Access:RC   DataWidth:0x20   // The number of SDM TCFC load commands executed.
+#define USDM_REG_NUM_OF_TCFC_AC_CMD                                                                          0xfd0614UL //Access:RC   DataWidth:0x20   // The number of SDM TCFC activity counter commands executed.
+#define USDM_REG_NUM_OF_INT_CMD                                                                              0xfd0618UL //Access:RC   DataWidth:0x20   // The number of SDM internal write commands executed.
+#define USDM_REG_NUM_OF_NOP_CMD                                                                              0xfd061cUL //Access:RC   DataWidth:0x20   // The number of SDM NOP commands executed.
+#define USDM_REG_NUM_OF_GRC_CMD                                                                              0xfd0620UL //Access:RC   DataWidth:0x20   // The number of GRC master commands executed.
+#define USDM_REG_NUM_OF_PRM_REQ                                                                              0xfd0624UL //Access:RC   DataWidth:0x20   // The number of packet end messages received on the PRM completion interface.
+#define USDM_REG_NUM_OF_PXP_ASYNC_REQ                                                                        0xfd0628UL //Access:RC   DataWidth:0x20   // The number of requests received from the pxp async if.
+#define USDM_REG_NUM_OF_DPM_REQ                                                                              0xfd062cUL //Access:RC   DataWidth:0x20   // The number of DORQ DPM messages received.
+#define USDM_REG_BRB_ALMOST_FULL                                                                             0xfd0700UL //Access:RW   DataWidth:0x5    // Almost full signal for read data from BRB in DMA_RSP block.
+#define USDM_REG_PXP_ALMOST_FULL                                                                             0xfd0704UL //Access:RW   DataWidth:0x4    // Almost full signal for read data from pxp in DMA_RSP block.
+#define USDM_REG_DORQ_ALMOST_FULL                                                                            0xfd0708UL //Access:RW   DataWidth:0x6    // Almost full signal for read data from DORQ in SDM_DORQ block.
+#define USDM_REG_AGG_INT_CTRL                                                                                0xfd0800UL //Access:RW   DataWidth:0xa    // This array of registers provides controls for each of the aggregated interrupts; The fields are defined as follows: [20:16] Affinity [15:12] NumL2m. [11]    Exclusive. [10]    Core-selection where 0=Core_A and 1=Core_B. [9]     Mode bit where 0=normal and 1=auto-mask-mode. [8]     T-flag which determines if a thread is allocated for this handler in the Storm. [7:0]   EventID which selects the event ID of the associated handler.
+#define USDM_REG_AGG_INT_CTRL_SIZE                                                                           32
+#define USDM_REG_AGG_INT_STATE                                                                               0xfd0a00UL //Access:R    DataWidth:0x2    // This array of registers provides access to each of the 32 aggregated interrupt request state machines; The values read from this register mean the following; 00 = IDLE; 01 = PEND; 10 = MASK; 11 = PANDM.
+#define USDM_REG_AGG_INT_STATE_SIZE                                                                          32
+#define USDM_REG_QUEUE_FULL                                                                                  0xfd0c00UL //Access:R    DataWidth:0x9    // Input queue fifo full in sdm_inp block.
+#define USDM_REG_INT_CMPL_PEND_FULL                                                                          0xfd0c04UL //Access:R    DataWidth:0x1    // Internal write completion pending full in internal write block.
+#define USDM_REG_INT_CPRM_PEND_FULL                                                                          0xfd0c08UL //Access:R    DataWidth:0x1    // Internal write completion parameter pending full in internal write block.
+#define USDM_REG_QM_FULL                                                                                     0xfd0c0cUL //Access:R    DataWidth:0x1    // QM IF  full in sdm_inp block.
+#define USDM_REG_DELAY_FIFO_FULL                                                                             0xfd0c10UL //Access:R    DataWidth:0x1    // Delay FIFO  full in sdm_inp block.
+#define USDM_REG_TIMERS_PEND_FULL                                                                            0xfd0c14UL //Access:R    DataWidth:0x1    // Pending FIFO  full in sdm_timers block.
+#define USDM_REG_TIMERS_ADDR_FULL                                                                            0xfd0c18UL //Access:R    DataWidth:0x1    // Address FIFO  full in sdm_timers block.
+#define USDM_REG_RSP_PXP_RDATA_FULL                                                                          0xfd0c1cUL //Access:R    DataWidth:0x1    // PXP rd_data fifo  full in sdm_dma_rsp block.
+#define USDM_REG_RSP_BRB_RDATA_FULL                                                                          0xfd0c20UL //Access:R    DataWidth:0x1    // BRB read data fifo  full in sdm_dma_rsp block.
+#define USDM_REG_RSP_INT_RAM_RDATA_FULL                                                                      0xfd0c24UL //Access:R    DataWidth:0x1    // Int_ram rd_data fifo  full in sdm_dma_rsp block.
+#define USDM_REG_RSP_BRB_PEND_FULL                                                                           0xfd0c28UL //Access:R    DataWidth:0x1    // BRB pending fifo  full in sdm_dma_rsp block.
+#define USDM_REG_RSP_INT_RAM_PEND_FULL                                                                       0xfd0c2cUL //Access:R    DataWidth:0x1    // Int_ram pending fifo  full in sdm_dma_rsp block.
+#define USDM_REG_RSP_BRB_IF_FULL                                                                             0xfd0c30UL //Access:R    DataWidth:0x1    // BRB interface is  full in sdm_dma_rsp block.
+#define USDM_REG_RSP_PXP_IF_FULL                                                                             0xfd0c34UL //Access:R    DataWidth:0x1    // PXP interface is  full in sdm_dma_rsp block.
+#define USDM_REG_DST_PXP_IMMED_FULL                                                                          0xfd0c38UL //Access:R    DataWidth:0x1    // PXP immediate fifo full in sdm_dma_dst block.
+#define USDM_REG_DST_PXP_DST_PEND_FULL                                                                       0xfd0c3cUL //Access:R    DataWidth:0x1    // PXP destination pending fifo full in sdm_dma_dst block.
+#define USDM_REG_DST_PXP_SRC_PEND_FULL                                                                       0xfd0c40UL //Access:R    DataWidth:0x1    // PXP source pending fifo full in sdm_dma_dst block.
+#define USDM_REG_DST_BRB_SRC_PEND_FULL                                                                       0xfd0c44UL //Access:R    DataWidth:0x1    // BRB source pending fifo full in sdm_dma_dst block.
+#define USDM_REG_DST_BRB_SRC_ADDR_FULL                                                                       0xfd0c48UL //Access:R    DataWidth:0x1    // BRB source address fifo full in sdm_dma_dst block.
+#define USDM_REG_DST_PXP_LINK_FULL                                                                           0xfd0c4cUL //Access:R    DataWidth:0x1    // PXP link list full in sdm_dma_dst block.
+#define USDM_REG_DST_INT_RAM_WAIT_FULL                                                                       0xfd0c50UL //Access:R    DataWidth:0x1    // Int_ram_wait fifo full in sdm_dma_dst block.
+#define USDM_REG_DST_PAS_BUF_WAIT_FULL                                                                       0xfd0c54UL //Access:R    DataWidth:0x1    // Pas_buf_wait fifo full in sdm_dma_dst block.
+#define USDM_REG_DST_PXP_IF_FULL                                                                             0xfd0c58UL //Access:R    DataWidth:0x1    // PXP if full in sdm_dma_dst block.
+#define USDM_REG_DST_INT_RAM_IF_FULL                                                                         0xfd0c5cUL //Access:R    DataWidth:0x1    // Int_ram if full in sdm_dma_dst block.
+#define USDM_REG_DST_PAS_BUF_IF_FULL                                                                         0xfd0c60UL //Access:R    DataWidth:0x1    // Pas_buf if full in sdm_dma_dst block.
+#define USDM_REG_SH_DELAY_FULL                                                                               0xfd0c64UL //Access:R    DataWidth:0x1    // Shared delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.
+#define USDM_REG_CM_DELAY_FULL                                                                               0xfd0c68UL //Access:R    DataWidth:0x1    // CM delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.
+#define USDM_REG_CMSG_QUE_FULL                                                                               0xfd0c6cUL //Access:R    DataWidth:0x1    // Completion message queue fifo full in sdm_cm block.
+#define USDM_REG_CCFC_LOAD_PEND_FULL                                                                         0xfd0c70UL //Access:R    DataWidth:0x1    // CCFC load pending fifo full in the CCFC interface  block.
+#define USDM_REG_TCFC_LOAD_PEND_FULL                                                                         0xfd0c74UL //Access:R    DataWidth:0x1    // TCFC load pending fifo full in the TCFC interface block.
+#define USDM_REG_ASYNC_HOST_FULL                                                                             0xfd0c78UL //Access:R    DataWidth:0x1    // Async fifo full in sdm_async block.
+#define USDM_REG_PRM_FIFO_FULL                                                                               0xfd0c7cUL //Access:R    DataWidth:0x1    // PRM FIFO full in PRM interface block.
+#define USDM_REG_RMT_XCM_FIFO_FULL_K2_E5                                                                     0xfd0c80UL //Access:R    DataWidth:0x1    // Remote XCM FIFO full (exist only in MSDM => XCM interface).
+#define USDM_REG_RMT_YCM_FIFO_FULL_K2_E5                                                                     0xfd0c84UL //Access:R    DataWidth:0x1    // Remote YCM FIFO full (exist only in MSDM => YCM interface).
+#define USDM_REG_INT_CMPL_PEND_EMPTY                                                                         0xfd0d00UL //Access:R    DataWidth:0x1    // Internal write completion pending empty in internal write block.
+#define USDM_REG_INT_CPRM_PEND_EMPTY                                                                         0xfd0d04UL //Access:R    DataWidth:0x1    // Internal write completion parameter pending empty in internal write block.
+#define USDM_REG_QUEUE_EMPTY                                                                                 0xfd0d08UL //Access:R    DataWidth:0x9    // Input queue fifo empty in sdm_inp block.
+#define USDM_REG_DELAY_FIFO_EMPTY                                                                            0xfd0d0cUL //Access:R    DataWidth:0x1    // Delay FIFO  empty in sdm_inp block.
+#define USDM_REG_TIMERS_PEND_EMPTY                                                                           0xfd0d10UL //Access:R    DataWidth:0x1    // Pending FIFO  empty in sdm_timers block.
+#define USDM_REG_TIMERS_ADDR_EMPTY                                                                           0xfd0d14UL //Access:R    DataWidth:0x1    // Address FIFO  empty in sdm_timers block.
+#define USDM_REG_RSP_PXP_RDATA_EMPTY                                                                         0xfd0d18UL //Access:R    DataWidth:0x1    // PXP rd_data fifo  empty in sdm_dma_rsp block.
+#define USDM_REG_RSP_BRB_RDATA_EMPTY                                                                         0xfd0d1cUL //Access:R    DataWidth:0x1    // BRB read data fifo  empty in sdm_dma_rsp block.
+#define USDM_REG_RSP_INT_RAM_RDATA_EMPTY                                                                     0xfd0d20UL //Access:R    DataWidth:0x1    // Int_ram rd_data fifo  empty in sdm_dma_rsp block.
+#define USDM_REG_RSP_BRB_PEND_EMPTY                                                                          0xfd0d24UL //Access:R    DataWidth:0x1    // BRB pending fifo  empty in sdm_dma_rsp block.
+#define USDM_REG_RSP_INT_RAM_PEND_EMPTY                                                                      0xfd0d28UL //Access:R    DataWidth:0x1    // Int_ram pending fifo  empty in sdm_dma_rsp block.
+#define USDM_REG_DST_PXP_IMMED_EMPTY                                                                         0xfd0d2cUL //Access:R    DataWidth:0x1    // PXP immediate fifo empty in sdm_dma_dst block.
+#define USDM_REG_DST_PXP_DST_PEND_EMPTY                                                                      0xfd0d30UL //Access:R    DataWidth:0x1    // PXP destination pending fifo empty in sdm_dma_dst block.
+#define USDM_REG_DST_PXP_SRC_PEND_EMPTY                                                                      0xfd0d34UL //Access:R    DataWidth:0x1    // PXP source pending fifo empty in sdm_dma_dst block.
+#define USDM_REG_DST_BRB_SRC_PEND_EMPTY                                                                      0xfd0d38UL //Access:R    DataWidth:0x1    // BRB source pending fifo empty in sdm_dma_dst block.
+#define USDM_REG_DST_BRB_SRC_ADDR_EMPTY                                                                      0xfd0d3cUL //Access:R    DataWidth:0x1    // BRB source address fifo empty in sdm_dma_dst block.
+#define USDM_REG_DST_PXP_LINK_EMPTY                                                                          0xfd0d40UL //Access:R    DataWidth:0x1    // PXP link list empty in sdm_dma_dst block.
+#define USDM_REG_DST_INT_RAM_WAIT_EMPTY                                                                      0xfd0d44UL //Access:R    DataWidth:0x1    // Int_ram_wait fifo empty in sdm_dma_dst block.
+#define USDM_REG_DST_PAS_BUF_WAIT_EMPTY                                                                      0xfd0d48UL //Access:R    DataWidth:0x1    // Pas_buf_wait fifo empty in sdm_dma_dst block.
+#define USDM_REG_SH_DELAY_EMPTY                                                                              0xfd0d4cUL //Access:R    DataWidth:0x1    // Shared delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.
+#define USDM_REG_CM_DELAY_EMPTY                                                                              0xfd0d50UL //Access:R    DataWidth:0x1    // CM delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.
+#define USDM_REG_CMSG_QUE_EMPTY                                                                              0xfd0d54UL //Access:R    DataWidth:0x1    // Completion message queue fifo empty in sdm_dma_dst block.
+#define USDM_REG_CCFC_LOAD_PEND_EMPTY                                                                        0xfd0d58UL //Access:R    DataWidth:0x1    // CCFC load pending fifo empty in sdm_ccfc block.
+#define USDM_REG_TCFC_LOAD_PEND_EMPTY                                                                        0xfd0d5cUL //Access:R    DataWidth:0x1    // TCFC load pending fifo empty in sdm_tcfc block.
+#define USDM_REG_ASYNC_HOST_EMPTY                                                                            0xfd0d60UL //Access:R    DataWidth:0x1    // Async fifo empty in sdm_async block.
+#define USDM_REG_PRM_FIFO_EMPTY                                                                              0xfd0d64UL //Access:R    DataWidth:0x1    // PRM FIFO empty in sdm_prm_if block.
+#define USDM_REG_RMT_XCM_FIFO_EMPTY_K2_E5                                                                    0xfd0d68UL //Access:R    DataWidth:0x1    // Remote XCM FIFO empty (exist only within MSDM => XCM path).
+#define USDM_REG_RMT_YCM_FIFO_EMPTY_K2_E5                                                                    0xfd0d6cUL //Access:R    DataWidth:0x1    // Remote YCM FIFO empty (exist only within MSDM => YCM path).
+#define USDM_REG_DBG_OUT_DATA                                                                                0xfd0e00UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define USDM_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define USDM_REG_DBG_OUT_VALID                                                                               0xfd0e20UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define USDM_REG_DBG_OUT_FRAME                                                                               0xfd0e24UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define USDM_REG_DBG_SELECT                                                                                  0xfd0e28UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define USDM_REG_DBG_DWORD_ENABLE                                                                            0xfd0e2cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define USDM_REG_DBG_SHIFT                                                                                   0xfd0e30UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define USDM_REG_DBG_FORCE_VALID                                                                             0xfd0e34UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define USDM_REG_DBG_FORCE_FRAME                                                                             0xfd0e38UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define USDM_REG_ASYNC_FIFO                                                                                  0xfd2000UL //Access:WB_R DataWidth:0x49   // Provides read-only access of the PXP-Async input FIFO. Intended for debug purposes.
+#define USDM_REG_ASYNC_FIFO_SIZE                                                                             116
+#define USDM_REG_IMMED_FIFO                                                                                  0xfd2400UL //Access:WB_R DataWidth:0x40   // Provides read-only access of the immediate data FIFO. Intended for debug purposes.
+#define USDM_REG_IMMED_FIFO_SIZE                                                                             38
+#define USDM_REG_BRB_FIFO                                                                                    0xfd2800UL //Access:WB_R DataWidth:0x86   // Provides read-only access of the BRB response FIFO. Intended for debug purposes.
+#define USDM_REG_BRB_FIFO_SIZE                                                                               152
+#define USDM_REG_PXP_FIFO                                                                                    0xfd2c00UL //Access:WB_R DataWidth:0x4a   // Provides read-only access of the PXP response FIFO. Intended for debug purposes.
+#define USDM_REG_PXP_FIFO_SIZE                                                                               76
+#define USDM_REG_INT_RAM_FIFO                                                                                0xfd3000UL //Access:WB_R DataWidth:0x41   // Provides read-only access of the internal RAM response FIFO. Intended for debug purposes.
+#define USDM_REG_INT_RAM_FIFO_SIZE                                                                           76
+#define USDM_REG_DPM_FIFO                                                                                    0xfd3400UL //Access:WB_R DataWidth:0x51   // Provides read-only access of the DORQ DPM input FIFO. Intended for debug purposes.
+#define USDM_REG_DPM_FIFO_SIZE                                                                               172
+#define USDM_REG_EXT_OVERFLOW                                                                                0xfd3800UL //Access:WB_R DataWidth:0x4b   // Provides read-only access of the external store overflow FIFO. Intended for debug purposes.
+#define USDM_REG_EXT_OVERFLOW_SIZE                                                                           36
+#define USDM_REG_PRM_FIFO                                                                                    0xfd3c00UL //Access:WB_R DataWidth:0x41   // Provides read-only access of the PRM completion input FIFO. Intended for debug purposes.
+#define USDM_REG_PRM_FIFO_SIZE                                                                               116
+#define USDM_REG_TIMERS                                                                                      0xfd4000UL //Access:WB   DataWidth:0x39   // Provides memory-mapped read/write access to the timers' memory. Intended for debug purposes.
+#define USDM_REG_TIMERS_SIZE                                                                                 32
+#define USDM_REG_INP_QUEUE                                                                                   0xfd5000UL //Access:WB   DataWidth:0x40   // Input queue memory. Access only for debugging.
+#define USDM_REG_INP_QUEUE_SIZE                                                                              376
+#define USDM_REG_CMSG_QUE                                                                                    0xfd8000UL //Access:WB   DataWidth:0x40   // CM queue memory. Access only for debugging.
+#define USDM_REG_CMSG_QUE_SIZE                                                                               384
+#define XCM_REG_INIT                                                                                         0x1000000UL //Access:RW   DataWidth:0x1    // Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
+#define XCM_REG_QM_ACT_ST_CNT_INIT                                                                           0x1000004UL //Access:W    DataWidth:0x1    // QM Active State counter initialization trigger.
+#define XCM_REG_QM_ACT_ST_CNT_INIT_DONE                                                                      0x1000008UL //Access:RC   DataWidth:0x1    // QM Active State counter initialization done.
+#define XCM_REG_DBG_SELECT                                                                                   0x1000040UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define XCM_REG_DBG_DWORD_ENABLE                                                                             0x1000044UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define XCM_REG_DBG_SHIFT                                                                                    0x1000048UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define XCM_REG_DBG_FORCE_VALID                                                                              0x100004cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define XCM_REG_DBG_FORCE_FRAME                                                                              0x1000050UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define XCM_REG_DBG_OUT_DATA                                                                                 0x1000060UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define XCM_REG_DBG_OUT_DATA_SIZE                                                                            8
+#define XCM_REG_DBG_OUT_VALID                                                                                0x1000080UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define XCM_REG_DBG_OUT_FRAME                                                                                0x1000084UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define XCM_REG_AFFINITY_TYPE_0_E5                                                                           0x1000088UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define XCM_REG_AFFINITY_TYPE_1_E5                                                                           0x100008cUL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define XCM_REG_AFFINITY_TYPE_2_E5                                                                           0x1000090UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define XCM_REG_AFFINITY_TYPE_3_E5                                                                           0x1000094UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define XCM_REG_AFFINITY_TYPE_4_E5                                                                           0x1000098UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define XCM_REG_AFFINITY_TYPE_5_E5                                                                           0x100009cUL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define XCM_REG_AFFINITY_TYPE_6_E5                                                                           0x10000a0UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define XCM_REG_AFFINITY_TYPE_7_E5                                                                           0x10000a4UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define XCM_REG_AFFINITY_TYPE_8_E5                                                                           0x10000a8UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define XCM_REG_AFFINITY_TYPE_9_E5                                                                           0x10000acUL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define XCM_REG_AFFINITY_TYPE_10_E5                                                                          0x10000b0UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define XCM_REG_AFFINITY_TYPE_11_E5                                                                          0x10000b4UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define XCM_REG_AFFINITY_TYPE_12_E5                                                                          0x10000b8UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define XCM_REG_AFFINITY_TYPE_13_E5                                                                          0x10000bcUL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define XCM_REG_AFFINITY_TYPE_14_E5                                                                          0x10000c0UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define XCM_REG_AFFINITY_TYPE_15_E5                                                                          0x10000c4UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define XCM_REG_EXCLUSIVE_FLG_0_E5                                                                           0x10000c8UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define XCM_REG_EXCLUSIVE_FLG_1_E5                                                                           0x10000ccUL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define XCM_REG_EXCLUSIVE_FLG_2_E5                                                                           0x10000d0UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define XCM_REG_EXCLUSIVE_FLG_3_E5                                                                           0x10000d4UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define XCM_REG_EXCLUSIVE_FLG_4_E5                                                                           0x10000d8UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define XCM_REG_EXCLUSIVE_FLG_5_E5                                                                           0x10000dcUL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define XCM_REG_EXCLUSIVE_FLG_6_E5                                                                           0x10000e0UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define XCM_REG_EXCLUSIVE_FLG_7_E5                                                                           0x10000e4UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define XCM_REG_EXCLUSIVE_FLG_8_E5                                                                           0x10000e8UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define XCM_REG_EXCLUSIVE_FLG_9_E5                                                                           0x10000ecUL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define XCM_REG_EXCLUSIVE_FLG_10_E5                                                                          0x10000f0UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define XCM_REG_EXCLUSIVE_FLG_11_E5                                                                          0x10000f4UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define XCM_REG_EXCLUSIVE_FLG_12_E5                                                                          0x10000f8UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define XCM_REG_EXCLUSIVE_FLG_13_E5                                                                          0x10000fcUL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define XCM_REG_EXCLUSIVE_FLG_14_E5                                                                          0x1000100UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define XCM_REG_EXCLUSIVE_FLG_15_E5                                                                          0x1000104UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define XCM_REG_AGG_CON_CF0_Q_BB_K2                                                                          0x1000908UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_CF0_Q_E5                                                                             0x1000108UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_CF1_Q_BB_K2                                                                          0x100090cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_CF1_Q_E5                                                                             0x100010cUL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_CF2_Q_BB_K2                                                                          0x1000910UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_CF2_Q_E5                                                                             0x1000110UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_CF3_Q_BB_K2                                                                          0x1000914UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_CF3_Q_E5                                                                             0x1000114UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_CF4_Q_BB_K2                                                                          0x1000918UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_CF4_Q_E5                                                                             0x1000118UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_CF5_Q_BB_K2                                                                          0x100091cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_CF5_Q_E5                                                                             0x100011cUL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_CF6_Q_BB_K2                                                                          0x1000920UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_CF6_Q_E5                                                                             0x1000120UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_CF7_Q_BB_K2                                                                          0x1000924UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_CF7_Q_E5                                                                             0x1000124UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_CF8_Q_BB_K2                                                                          0x1000928UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_CF8_Q_E5                                                                             0x1000128UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_CF9_Q_BB_K2                                                                          0x100092cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_CF9_Q_E5                                                                             0x100012cUL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_CF10_Q_BB_K2                                                                         0x1000930UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_CF10_Q_E5                                                                            0x1000130UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_CF11_Q_BB_K2                                                                         0x1000934UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_CF11_Q_E5                                                                            0x1000134UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_CF12_Q_BB_K2                                                                         0x1000938UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_CF12_Q_E5                                                                            0x1000138UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_CF13_Q_BB_K2                                                                         0x100093cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_CF13_Q_E5                                                                            0x100013cUL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_CF14_Q_BB_K2                                                                         0x1000940UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_CF14_Q_E5                                                                            0x1000140UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_CF15_Q_BB_K2                                                                         0x1000944UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_CF15_Q_E5                                                                            0x1000144UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_CF16_Q_BB_K2                                                                         0x1000948UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_CF16_Q_E5                                                                            0x1000148UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_CF17_Q_BB_K2                                                                         0x100094cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_CF17_Q_E5                                                                            0x100014cUL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_CF18_Q_BB_K2                                                                         0x1000950UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).:
+#define XCM_REG_AGG_CON_CF18_Q_E5                                                                            0x1000150UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_CF19_Q_BB_K2                                                                         0x1000954UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_CF19_Q_E5                                                                            0x1000154UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_CF20_Q_BB_K2                                                                         0x1000958UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_CF20_Q_E5                                                                            0x1000158UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_CF21_Q_BB_K2                                                                         0x100095cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_CF21_Q_E5                                                                            0x100015cUL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_CF22_Q_BB_K2                                                                         0x1000960UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_CF22_Q_E5                                                                            0x1000160UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_CF23_Q_BB_K2                                                                         0x1000964UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_CF23_Q_E5                                                                            0x1000164UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_CF24_Q_E5                                                                            0x1000168UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_INT_STS_0                                                                                    0x1000180UL //Access:R    DataWidth:0x14   // Multi Field Register.
+  #define XCM_REG_INT_STS_0_ADDRESS_ERROR                                                                    (0x1<<0) // Signals an unknown address to the rf module.
+  #define XCM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                              0
+  #define XCM_REG_INT_STS_0_IS_STORM_OVFL_ERR                                                                (0x1<<1) // Write to full STORM input buffer.
+  #define XCM_REG_INT_STS_0_IS_STORM_OVFL_ERR_SHIFT                                                          1
+  #define XCM_REG_INT_STS_0_IS_STORM_UNDER_ERR                                                               (0x1<<2) // Read from empty  STORM input buffer.
+  #define XCM_REG_INT_STS_0_IS_STORM_UNDER_ERR_SHIFT                                                         2
+  #define XCM_REG_INT_STS_0_IS_MSDM_OVFL_ERR                                                                 (0x1<<3) // Write to full MSDM input buffer.
+  #define XCM_REG_INT_STS_0_IS_MSDM_OVFL_ERR_SHIFT                                                           3
+  #define XCM_REG_INT_STS_0_IS_MSDM_UNDER_ERR                                                                (0x1<<4) // Read from empty MSDM input buffer.
+  #define XCM_REG_INT_STS_0_IS_MSDM_UNDER_ERR_SHIFT                                                          4
+  #define XCM_REG_INT_STS_0_IS_XSDM_OVFL_ERR                                                                 (0x1<<5) // Write to full XSDM input buffer.
+  #define XCM_REG_INT_STS_0_IS_XSDM_OVFL_ERR_SHIFT                                                           5
+  #define XCM_REG_INT_STS_0_IS_XSDM_UNDER_ERR                                                                (0x1<<6) // Read from empty XSDM input buffer.
+  #define XCM_REG_INT_STS_0_IS_XSDM_UNDER_ERR_SHIFT                                                          6
+  #define XCM_REG_INT_STS_0_IS_YSDM_OVFL_ERR                                                                 (0x1<<7) // Write to full YSDM input buffer.
+  #define XCM_REG_INT_STS_0_IS_YSDM_OVFL_ERR_SHIFT                                                           7
+  #define XCM_REG_INT_STS_0_IS_YSDM_UNDER_ERR                                                                (0x1<<8) // Read from empty  YSDM input buffer.
+  #define XCM_REG_INT_STS_0_IS_YSDM_UNDER_ERR_SHIFT                                                          8
+  #define XCM_REG_INT_STS_0_IS_USDM_OVFL_ERR                                                                 (0x1<<9) // Write to full USDM input buffer.
+  #define XCM_REG_INT_STS_0_IS_USDM_OVFL_ERR_SHIFT                                                           9
+  #define XCM_REG_INT_STS_0_IS_USDM_UNDER_ERR                                                                (0x1<<10) // Read from empty USDM input buffer.
+  #define XCM_REG_INT_STS_0_IS_USDM_UNDER_ERR_SHIFT                                                          10
+  #define XCM_REG_INT_STS_0_IS_MSEM_OVFL_ERR                                                                 (0x1<<11) // Write to full Msem input buffer.
+  #define XCM_REG_INT_STS_0_IS_MSEM_OVFL_ERR_SHIFT                                                           11
+  #define XCM_REG_INT_STS_0_IS_MSEM_UNDER_ERR                                                                (0x1<<12) // Read from empty  Msem input buffer.
+  #define XCM_REG_INT_STS_0_IS_MSEM_UNDER_ERR_SHIFT                                                          12
+  #define XCM_REG_INT_STS_0_IS_USEM_OVFL_ERR                                                                 (0x1<<13) // Write to full Usem input buffer.
+  #define XCM_REG_INT_STS_0_IS_USEM_OVFL_ERR_SHIFT                                                           13
+  #define XCM_REG_INT_STS_0_IS_USEM_UNDER_ERR                                                                (0x1<<14) // Read from empty Usem input buffer.
+  #define XCM_REG_INT_STS_0_IS_USEM_UNDER_ERR_SHIFT                                                          14
+  #define XCM_REG_INT_STS_0_IS_YSEM_OVFL_ERR                                                                 (0x1<<15) // Write to full Ysem input buffer.
+  #define XCM_REG_INT_STS_0_IS_YSEM_OVFL_ERR_SHIFT                                                           15
+  #define XCM_REG_INT_STS_0_EXT_LD_UNDER_ERR_E5                                                              (0x1<<16) // Read from empty External read buffer.
+  #define XCM_REG_INT_STS_0_EXT_LD_UNDER_ERR_E5_SHIFT                                                        16
+  #define XCM_REG_INT_STS_0_EXT_LD_OVFL_ERR_E5                                                               (0x1<<17) // Write to fully External read buffer.
+  #define XCM_REG_INT_STS_0_EXT_LD_OVFL_ERR_E5_SHIFT                                                         17
+  #define XCM_REG_INT_STS_0_AFFINITY_TYPE_NO_CON_E5                                                          (0x1<<18) // Affinity type = 2 (connection based) but connection doesn't exist.
+  #define XCM_REG_INT_STS_0_AFFINITY_TYPE_NO_CON_E5_SHIFT                                                    18
+  #define XCM_REG_INT_STS_0_AFFINITY_TYPE_NO_TASK_E5                                                         (0x1<<19) // Affinity type = 3 (task based) but task doesn't exist.
+  #define XCM_REG_INT_STS_0_AFFINITY_TYPE_NO_TASK_E5_SHIFT                                                   19
+#define XCM_REG_INT_MASK_0                                                                                   0x1000184UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define XCM_REG_INT_MASK_0_ADDRESS_ERROR                                                                   (0x1<<0) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.ADDRESS_ERROR .
+  #define XCM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                             0
+  #define XCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR                                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_STORM_OVFL_ERR .
+  #define XCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR_SHIFT                                                         1
+  #define XCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR                                                              (0x1<<2) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_STORM_UNDER_ERR .
+  #define XCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR_SHIFT                                                        2
+  #define XCM_REG_INT_MASK_0_IS_MSDM_OVFL_ERR                                                                (0x1<<3) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_MSDM_OVFL_ERR .
+  #define XCM_REG_INT_MASK_0_IS_MSDM_OVFL_ERR_SHIFT                                                          3
+  #define XCM_REG_INT_MASK_0_IS_MSDM_UNDER_ERR                                                               (0x1<<4) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_MSDM_UNDER_ERR .
+  #define XCM_REG_INT_MASK_0_IS_MSDM_UNDER_ERR_SHIFT                                                         4
+  #define XCM_REG_INT_MASK_0_IS_XSDM_OVFL_ERR                                                                (0x1<<5) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_XSDM_OVFL_ERR .
+  #define XCM_REG_INT_MASK_0_IS_XSDM_OVFL_ERR_SHIFT                                                          5
+  #define XCM_REG_INT_MASK_0_IS_XSDM_UNDER_ERR                                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_XSDM_UNDER_ERR .
+  #define XCM_REG_INT_MASK_0_IS_XSDM_UNDER_ERR_SHIFT                                                         6
+  #define XCM_REG_INT_MASK_0_IS_YSDM_OVFL_ERR                                                                (0x1<<7) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_YSDM_OVFL_ERR .
+  #define XCM_REG_INT_MASK_0_IS_YSDM_OVFL_ERR_SHIFT                                                          7
+  #define XCM_REG_INT_MASK_0_IS_YSDM_UNDER_ERR                                                               (0x1<<8) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_YSDM_UNDER_ERR .
+  #define XCM_REG_INT_MASK_0_IS_YSDM_UNDER_ERR_SHIFT                                                         8
+  #define XCM_REG_INT_MASK_0_IS_USDM_OVFL_ERR                                                                (0x1<<9) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_USDM_OVFL_ERR .
+  #define XCM_REG_INT_MASK_0_IS_USDM_OVFL_ERR_SHIFT                                                          9
+  #define XCM_REG_INT_MASK_0_IS_USDM_UNDER_ERR                                                               (0x1<<10) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_USDM_UNDER_ERR .
+  #define XCM_REG_INT_MASK_0_IS_USDM_UNDER_ERR_SHIFT                                                         10
+  #define XCM_REG_INT_MASK_0_IS_MSEM_OVFL_ERR                                                                (0x1<<11) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_MSEM_OVFL_ERR .
+  #define XCM_REG_INT_MASK_0_IS_MSEM_OVFL_ERR_SHIFT                                                          11
+  #define XCM_REG_INT_MASK_0_IS_MSEM_UNDER_ERR                                                               (0x1<<12) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_MSEM_UNDER_ERR .
+  #define XCM_REG_INT_MASK_0_IS_MSEM_UNDER_ERR_SHIFT                                                         12
+  #define XCM_REG_INT_MASK_0_IS_USEM_OVFL_ERR                                                                (0x1<<13) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_USEM_OVFL_ERR .
+  #define XCM_REG_INT_MASK_0_IS_USEM_OVFL_ERR_SHIFT                                                          13
+  #define XCM_REG_INT_MASK_0_IS_USEM_UNDER_ERR                                                               (0x1<<14) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_USEM_UNDER_ERR .
+  #define XCM_REG_INT_MASK_0_IS_USEM_UNDER_ERR_SHIFT                                                         14
+  #define XCM_REG_INT_MASK_0_IS_YSEM_OVFL_ERR                                                                (0x1<<15) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_YSEM_OVFL_ERR .
+  #define XCM_REG_INT_MASK_0_IS_YSEM_OVFL_ERR_SHIFT                                                          15
+  #define XCM_REG_INT_MASK_0_EXT_LD_UNDER_ERR_E5                                                             (0x1<<16) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.EXT_LD_UNDER_ERR .
+  #define XCM_REG_INT_MASK_0_EXT_LD_UNDER_ERR_E5_SHIFT                                                       16
+  #define XCM_REG_INT_MASK_0_EXT_LD_OVFL_ERR_E5                                                              (0x1<<17) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.EXT_LD_OVFL_ERR .
+  #define XCM_REG_INT_MASK_0_EXT_LD_OVFL_ERR_E5_SHIFT                                                        17
+  #define XCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_CON_E5                                                         (0x1<<18) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.AFFINITY_TYPE_NO_CON .
+  #define XCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_CON_E5_SHIFT                                                   18
+  #define XCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_TASK_E5                                                        (0x1<<19) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.AFFINITY_TYPE_NO_TASK .
+  #define XCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_TASK_E5_SHIFT                                                  19
+#define XCM_REG_INT_STS_WR_0                                                                                 0x1000188UL //Access:WR   DataWidth:0x14   // Multi Field Register.
+  #define XCM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define XCM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                           0
+  #define XCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR                                                             (0x1<<1) // Write to full STORM input buffer.
+  #define XCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR_SHIFT                                                       1
+  #define XCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR                                                            (0x1<<2) // Read from empty  STORM input buffer.
+  #define XCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR_SHIFT                                                      2
+  #define XCM_REG_INT_STS_WR_0_IS_MSDM_OVFL_ERR                                                              (0x1<<3) // Write to full MSDM input buffer.
+  #define XCM_REG_INT_STS_WR_0_IS_MSDM_OVFL_ERR_SHIFT                                                        3
+  #define XCM_REG_INT_STS_WR_0_IS_MSDM_UNDER_ERR                                                             (0x1<<4) // Read from empty MSDM input buffer.
+  #define XCM_REG_INT_STS_WR_0_IS_MSDM_UNDER_ERR_SHIFT                                                       4
+  #define XCM_REG_INT_STS_WR_0_IS_XSDM_OVFL_ERR                                                              (0x1<<5) // Write to full XSDM input buffer.
+  #define XCM_REG_INT_STS_WR_0_IS_XSDM_OVFL_ERR_SHIFT                                                        5
+  #define XCM_REG_INT_STS_WR_0_IS_XSDM_UNDER_ERR                                                             (0x1<<6) // Read from empty XSDM input buffer.
+  #define XCM_REG_INT_STS_WR_0_IS_XSDM_UNDER_ERR_SHIFT                                                       6
+  #define XCM_REG_INT_STS_WR_0_IS_YSDM_OVFL_ERR                                                              (0x1<<7) // Write to full YSDM input buffer.
+  #define XCM_REG_INT_STS_WR_0_IS_YSDM_OVFL_ERR_SHIFT                                                        7
+  #define XCM_REG_INT_STS_WR_0_IS_YSDM_UNDER_ERR                                                             (0x1<<8) // Read from empty  YSDM input buffer.
+  #define XCM_REG_INT_STS_WR_0_IS_YSDM_UNDER_ERR_SHIFT                                                       8
+  #define XCM_REG_INT_STS_WR_0_IS_USDM_OVFL_ERR                                                              (0x1<<9) // Write to full USDM input buffer.
+  #define XCM_REG_INT_STS_WR_0_IS_USDM_OVFL_ERR_SHIFT                                                        9
+  #define XCM_REG_INT_STS_WR_0_IS_USDM_UNDER_ERR                                                             (0x1<<10) // Read from empty USDM input buffer.
+  #define XCM_REG_INT_STS_WR_0_IS_USDM_UNDER_ERR_SHIFT                                                       10
+  #define XCM_REG_INT_STS_WR_0_IS_MSEM_OVFL_ERR                                                              (0x1<<11) // Write to full Msem input buffer.
+  #define XCM_REG_INT_STS_WR_0_IS_MSEM_OVFL_ERR_SHIFT                                                        11
+  #define XCM_REG_INT_STS_WR_0_IS_MSEM_UNDER_ERR                                                             (0x1<<12) // Read from empty  Msem input buffer.
+  #define XCM_REG_INT_STS_WR_0_IS_MSEM_UNDER_ERR_SHIFT                                                       12
+  #define XCM_REG_INT_STS_WR_0_IS_USEM_OVFL_ERR                                                              (0x1<<13) // Write to full Usem input buffer.
+  #define XCM_REG_INT_STS_WR_0_IS_USEM_OVFL_ERR_SHIFT                                                        13
+  #define XCM_REG_INT_STS_WR_0_IS_USEM_UNDER_ERR                                                             (0x1<<14) // Read from empty Usem input buffer.
+  #define XCM_REG_INT_STS_WR_0_IS_USEM_UNDER_ERR_SHIFT                                                       14
+  #define XCM_REG_INT_STS_WR_0_IS_YSEM_OVFL_ERR                                                              (0x1<<15) // Write to full Ysem input buffer.
+  #define XCM_REG_INT_STS_WR_0_IS_YSEM_OVFL_ERR_SHIFT                                                        15
+  #define XCM_REG_INT_STS_WR_0_EXT_LD_UNDER_ERR_E5                                                           (0x1<<16) // Read from empty External read buffer.
+  #define XCM_REG_INT_STS_WR_0_EXT_LD_UNDER_ERR_E5_SHIFT                                                     16
+  #define XCM_REG_INT_STS_WR_0_EXT_LD_OVFL_ERR_E5                                                            (0x1<<17) // Write to fully External read buffer.
+  #define XCM_REG_INT_STS_WR_0_EXT_LD_OVFL_ERR_E5_SHIFT                                                      17
+  #define XCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_CON_E5                                                       (0x1<<18) // Affinity type = 2 (connection based) but connection doesn't exist.
+  #define XCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_CON_E5_SHIFT                                                 18
+  #define XCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_TASK_E5                                                      (0x1<<19) // Affinity type = 3 (task based) but task doesn't exist.
+  #define XCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_TASK_E5_SHIFT                                                19
+#define XCM_REG_INT_STS_CLR_0                                                                                0x100018cUL //Access:RC   DataWidth:0x14   // Multi Field Register.
+  #define XCM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define XCM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                          0
+  #define XCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR                                                            (0x1<<1) // Write to full STORM input buffer.
+  #define XCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR_SHIFT                                                      1
+  #define XCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR                                                           (0x1<<2) // Read from empty  STORM input buffer.
+  #define XCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR_SHIFT                                                     2
+  #define XCM_REG_INT_STS_CLR_0_IS_MSDM_OVFL_ERR                                                             (0x1<<3) // Write to full MSDM input buffer.
+  #define XCM_REG_INT_STS_CLR_0_IS_MSDM_OVFL_ERR_SHIFT                                                       3
+  #define XCM_REG_INT_STS_CLR_0_IS_MSDM_UNDER_ERR                                                            (0x1<<4) // Read from empty MSDM input buffer.
+  #define XCM_REG_INT_STS_CLR_0_IS_MSDM_UNDER_ERR_SHIFT                                                      4
+  #define XCM_REG_INT_STS_CLR_0_IS_XSDM_OVFL_ERR                                                             (0x1<<5) // Write to full XSDM input buffer.
+  #define XCM_REG_INT_STS_CLR_0_IS_XSDM_OVFL_ERR_SHIFT                                                       5
+  #define XCM_REG_INT_STS_CLR_0_IS_XSDM_UNDER_ERR                                                            (0x1<<6) // Read from empty XSDM input buffer.
+  #define XCM_REG_INT_STS_CLR_0_IS_XSDM_UNDER_ERR_SHIFT                                                      6
+  #define XCM_REG_INT_STS_CLR_0_IS_YSDM_OVFL_ERR                                                             (0x1<<7) // Write to full YSDM input buffer.
+  #define XCM_REG_INT_STS_CLR_0_IS_YSDM_OVFL_ERR_SHIFT                                                       7
+  #define XCM_REG_INT_STS_CLR_0_IS_YSDM_UNDER_ERR                                                            (0x1<<8) // Read from empty  YSDM input buffer.
+  #define XCM_REG_INT_STS_CLR_0_IS_YSDM_UNDER_ERR_SHIFT                                                      8
+  #define XCM_REG_INT_STS_CLR_0_IS_USDM_OVFL_ERR                                                             (0x1<<9) // Write to full USDM input buffer.
+  #define XCM_REG_INT_STS_CLR_0_IS_USDM_OVFL_ERR_SHIFT                                                       9
+  #define XCM_REG_INT_STS_CLR_0_IS_USDM_UNDER_ERR                                                            (0x1<<10) // Read from empty USDM input buffer.
+  #define XCM_REG_INT_STS_CLR_0_IS_USDM_UNDER_ERR_SHIFT                                                      10
+  #define XCM_REG_INT_STS_CLR_0_IS_MSEM_OVFL_ERR                                                             (0x1<<11) // Write to full Msem input buffer.
+  #define XCM_REG_INT_STS_CLR_0_IS_MSEM_OVFL_ERR_SHIFT                                                       11
+  #define XCM_REG_INT_STS_CLR_0_IS_MSEM_UNDER_ERR                                                            (0x1<<12) // Read from empty  Msem input buffer.
+  #define XCM_REG_INT_STS_CLR_0_IS_MSEM_UNDER_ERR_SHIFT                                                      12
+  #define XCM_REG_INT_STS_CLR_0_IS_USEM_OVFL_ERR                                                             (0x1<<13) // Write to full Usem input buffer.
+  #define XCM_REG_INT_STS_CLR_0_IS_USEM_OVFL_ERR_SHIFT                                                       13
+  #define XCM_REG_INT_STS_CLR_0_IS_USEM_UNDER_ERR                                                            (0x1<<14) // Read from empty Usem input buffer.
+  #define XCM_REG_INT_STS_CLR_0_IS_USEM_UNDER_ERR_SHIFT                                                      14
+  #define XCM_REG_INT_STS_CLR_0_IS_YSEM_OVFL_ERR                                                             (0x1<<15) // Write to full Ysem input buffer.
+  #define XCM_REG_INT_STS_CLR_0_IS_YSEM_OVFL_ERR_SHIFT                                                       15
+  #define XCM_REG_INT_STS_CLR_0_EXT_LD_UNDER_ERR_E5                                                          (0x1<<16) // Read from empty External read buffer.
+  #define XCM_REG_INT_STS_CLR_0_EXT_LD_UNDER_ERR_E5_SHIFT                                                    16
+  #define XCM_REG_INT_STS_CLR_0_EXT_LD_OVFL_ERR_E5                                                           (0x1<<17) // Write to fully External read buffer.
+  #define XCM_REG_INT_STS_CLR_0_EXT_LD_OVFL_ERR_E5_SHIFT                                                     17
+  #define XCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_CON_E5                                                      (0x1<<18) // Affinity type = 2 (connection based) but connection doesn't exist.
+  #define XCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_CON_E5_SHIFT                                                18
+  #define XCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_TASK_E5                                                     (0x1<<19) // Affinity type = 3 (task based) but task doesn't exist.
+  #define XCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_TASK_E5_SHIFT                                               19
+#define XCM_REG_INT_STS_1                                                                                    0x1000190UL //Access:R    DataWidth:0x19   // Multi Field Register.
+  #define XCM_REG_INT_STS_1_IS_YSEM_UNDER_ERR                                                                (0x1<<0) // Read from empty  Ysem input buffer.
+  #define XCM_REG_INT_STS_1_IS_YSEM_UNDER_ERR_SHIFT                                                          0
+  #define XCM_REG_INT_STS_1_IS_DORQ_OVFL_ERR                                                                 (0x1<<1) // Write to full Dorq input buffer.
+  #define XCM_REG_INT_STS_1_IS_DORQ_OVFL_ERR_SHIFT                                                           1
+  #define XCM_REG_INT_STS_1_IS_DORQ_UNDER_ERR                                                                (0x1<<2) // Read from empty  Dorq input buffer.
+  #define XCM_REG_INT_STS_1_IS_DORQ_UNDER_ERR_SHIFT                                                          2
+  #define XCM_REG_INT_STS_1_IS_PBF_OVFL_ERR                                                                  (0x1<<3) // Write to full Pbf input buffer.
+  #define XCM_REG_INT_STS_1_IS_PBF_OVFL_ERR_SHIFT                                                            3
+  #define XCM_REG_INT_STS_1_IS_PBF_UNDER_ERR                                                                 (0x1<<4) // Read from empty Pbf input buffer.
+  #define XCM_REG_INT_STS_1_IS_PBF_UNDER_ERR_SHIFT                                                           4
+  #define XCM_REG_INT_STS_1_IS_TM_OVFL_ERR                                                                   (0x1<<5) // Write to full TM input buffer.
+  #define XCM_REG_INT_STS_1_IS_TM_OVFL_ERR_SHIFT                                                             5
+  #define XCM_REG_INT_STS_1_IS_TM_UNDER_ERR                                                                  (0x1<<6) // Read from empty TM input buffer.
+  #define XCM_REG_INT_STS_1_IS_TM_UNDER_ERR_SHIFT                                                            6
+  #define XCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR                                                                 (0x1<<7) // Write to full QM input buffer.
+  #define XCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR_SHIFT                                                           7
+  #define XCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR                                                                (0x1<<8) // Read from empty QM input buffer.
+  #define XCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR_SHIFT                                                          8
+  #define XCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR                                                                 (0x1<<9) // Write to full QM input buffer.
+  #define XCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR_SHIFT                                                           9
+  #define XCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR                                                                (0x1<<10) // Read from empty QM input buffer.
+  #define XCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR_SHIFT                                                          10
+  #define XCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0                                                                 (0x1<<11) // Write to full GRC input buffer bits [31:0].
+  #define XCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0_SHIFT                                                           11
+  #define XCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0                                                                (0x1<<12) // Read from empty  GRC input buffer bits [31:0].
+  #define XCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0_SHIFT                                                          12
+  #define XCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1                                                                 (0x1<<13) // Write to full GRC input buffer bits [63:32].
+  #define XCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1_SHIFT                                                           13
+  #define XCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1                                                                (0x1<<14) // Read from empty  GRC input buffer bits [63:32].
+  #define XCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1_SHIFT                                                          14
+  #define XCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2                                                                 (0x1<<15) // Write to full GRC input buffer bits [95:64].
+  #define XCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2_SHIFT                                                           15
+  #define XCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2                                                                (0x1<<16) // Read from empty  GRC input buffer bits [95:64].
+  #define XCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2_SHIFT                                                          16
+  #define XCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3                                                                 (0x1<<17) // Write to full GRC input buffer bits [127:96].
+  #define XCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3_SHIFT                                                           17
+  #define XCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3                                                                (0x1<<18) // Read from empty  GRC input buffer bits [127:96].
+  #define XCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3_SHIFT                                                          18
+  #define XCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL                                                                 (0x1<<19) // In-process Table overflow.
+  #define XCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL_SHIFT                                                           19
+  #define XCM_REG_INT_STS_1_AGG_CON_DATA_BUF_OVFL                                                            (0x1<<20) // Message Processor Aggregation Connection Data buffer overflow.
+  #define XCM_REG_INT_STS_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                                      20
+  #define XCM_REG_INT_STS_1_AGG_CON_CMD_BUF_OVFL                                                             (0x1<<21) // Message Processor Aggregation Connection Command buffer overflow.
+  #define XCM_REG_INT_STS_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                                       21
+  #define XCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL                                                             (0x1<<22) // Message Processor Storm Connection Data buffer overflow.
+  #define XCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL_SHIFT                                                       22
+  #define XCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL                                                              (0x1<<23) // Message Processor Storm Connection Command buffer overflow.
+  #define XCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL_SHIFT                                                        23
+  #define XCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE                                                            (0x1<<24) // Input message first descriptor fields violation.
+  #define XCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE_SHIFT                                                      24
+#define XCM_REG_INT_MASK_1                                                                                   0x1000194UL //Access:RW   DataWidth:0x19   // Multi Field Register.
+  #define XCM_REG_INT_MASK_1_IS_YSEM_UNDER_ERR                                                               (0x1<<0) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_YSEM_UNDER_ERR .
+  #define XCM_REG_INT_MASK_1_IS_YSEM_UNDER_ERR_SHIFT                                                         0
+  #define XCM_REG_INT_MASK_1_IS_DORQ_OVFL_ERR                                                                (0x1<<1) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_DORQ_OVFL_ERR .
+  #define XCM_REG_INT_MASK_1_IS_DORQ_OVFL_ERR_SHIFT                                                          1
+  #define XCM_REG_INT_MASK_1_IS_DORQ_UNDER_ERR                                                               (0x1<<2) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_DORQ_UNDER_ERR .
+  #define XCM_REG_INT_MASK_1_IS_DORQ_UNDER_ERR_SHIFT                                                         2
+  #define XCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR                                                                 (0x1<<3) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_PBF_OVFL_ERR .
+  #define XCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR_SHIFT                                                           3
+  #define XCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR                                                                (0x1<<4) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_PBF_UNDER_ERR .
+  #define XCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR_SHIFT                                                          4
+  #define XCM_REG_INT_MASK_1_IS_TM_OVFL_ERR                                                                  (0x1<<5) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_TM_OVFL_ERR .
+  #define XCM_REG_INT_MASK_1_IS_TM_OVFL_ERR_SHIFT                                                            5
+  #define XCM_REG_INT_MASK_1_IS_TM_UNDER_ERR                                                                 (0x1<<6) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_TM_UNDER_ERR .
+  #define XCM_REG_INT_MASK_1_IS_TM_UNDER_ERR_SHIFT                                                           6
+  #define XCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR                                                                (0x1<<7) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_QM_P_OVFL_ERR .
+  #define XCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR_SHIFT                                                          7
+  #define XCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR                                                               (0x1<<8) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_QM_P_UNDER_ERR .
+  #define XCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR_SHIFT                                                         8
+  #define XCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR                                                                (0x1<<9) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_QM_S_OVFL_ERR .
+  #define XCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR_SHIFT                                                          9
+  #define XCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR                                                               (0x1<<10) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_QM_S_UNDER_ERR .
+  #define XCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR_SHIFT                                                         10
+  #define XCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0                                                                (0x1<<11) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_GRC_OVFL_ERR0 .
+  #define XCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0_SHIFT                                                          11
+  #define XCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0                                                               (0x1<<12) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_GRC_UNDER_ERR0 .
+  #define XCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0_SHIFT                                                         12
+  #define XCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1                                                                (0x1<<13) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_GRC_OVFL_ERR1 .
+  #define XCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1_SHIFT                                                          13
+  #define XCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1                                                               (0x1<<14) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_GRC_UNDER_ERR1 .
+  #define XCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1_SHIFT                                                         14
+  #define XCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2                                                                (0x1<<15) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_GRC_OVFL_ERR2 .
+  #define XCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2_SHIFT                                                          15
+  #define XCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2                                                               (0x1<<16) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_GRC_UNDER_ERR2 .
+  #define XCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2_SHIFT                                                         16
+  #define XCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3                                                                (0x1<<17) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_GRC_OVFL_ERR3 .
+  #define XCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3_SHIFT                                                          17
+  #define XCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3                                                               (0x1<<18) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_GRC_UNDER_ERR3 .
+  #define XCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3_SHIFT                                                         18
+  #define XCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL                                                                (0x1<<19) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IN_PRCS_TBL_OVFL .
+  #define XCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL_SHIFT                                                          19
+  #define XCM_REG_INT_MASK_1_AGG_CON_DATA_BUF_OVFL                                                           (0x1<<20) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.AGG_CON_DATA_BUF_OVFL .
+  #define XCM_REG_INT_MASK_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                                     20
+  #define XCM_REG_INT_MASK_1_AGG_CON_CMD_BUF_OVFL                                                            (0x1<<21) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.AGG_CON_CMD_BUF_OVFL .
+  #define XCM_REG_INT_MASK_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                                      21
+  #define XCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL                                                            (0x1<<22) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.SM_CON_DATA_BUF_OVFL .
+  #define XCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL_SHIFT                                                      22
+  #define XCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL                                                             (0x1<<23) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.SM_CON_CMD_BUF_OVFL .
+  #define XCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL_SHIFT                                                       23
+  #define XCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE                                                           (0x1<<24) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.FI_DESC_INPUT_VIOLATE .
+  #define XCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE_SHIFT                                                     24
+#define XCM_REG_INT_STS_WR_1                                                                                 0x1000198UL //Access:WR   DataWidth:0x19   // Multi Field Register.
+  #define XCM_REG_INT_STS_WR_1_IS_YSEM_UNDER_ERR                                                             (0x1<<0) // Read from empty  Ysem input buffer.
+  #define XCM_REG_INT_STS_WR_1_IS_YSEM_UNDER_ERR_SHIFT                                                       0
+  #define XCM_REG_INT_STS_WR_1_IS_DORQ_OVFL_ERR                                                              (0x1<<1) // Write to full Dorq input buffer.
+  #define XCM_REG_INT_STS_WR_1_IS_DORQ_OVFL_ERR_SHIFT                                                        1
+  #define XCM_REG_INT_STS_WR_1_IS_DORQ_UNDER_ERR                                                             (0x1<<2) // Read from empty  Dorq input buffer.
+  #define XCM_REG_INT_STS_WR_1_IS_DORQ_UNDER_ERR_SHIFT                                                       2
+  #define XCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR                                                               (0x1<<3) // Write to full Pbf input buffer.
+  #define XCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR_SHIFT                                                         3
+  #define XCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR                                                              (0x1<<4) // Read from empty Pbf input buffer.
+  #define XCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR_SHIFT                                                        4
+  #define XCM_REG_INT_STS_WR_1_IS_TM_OVFL_ERR                                                                (0x1<<5) // Write to full TM input buffer.
+  #define XCM_REG_INT_STS_WR_1_IS_TM_OVFL_ERR_SHIFT                                                          5
+  #define XCM_REG_INT_STS_WR_1_IS_TM_UNDER_ERR                                                               (0x1<<6) // Read from empty TM input buffer.
+  #define XCM_REG_INT_STS_WR_1_IS_TM_UNDER_ERR_SHIFT                                                         6
+  #define XCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR                                                              (0x1<<7) // Write to full QM input buffer.
+  #define XCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR_SHIFT                                                        7
+  #define XCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR                                                             (0x1<<8) // Read from empty QM input buffer.
+  #define XCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR_SHIFT                                                       8
+  #define XCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR                                                              (0x1<<9) // Write to full QM input buffer.
+  #define XCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR_SHIFT                                                        9
+  #define XCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR                                                             (0x1<<10) // Read from empty QM input buffer.
+  #define XCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR_SHIFT                                                       10
+  #define XCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0                                                              (0x1<<11) // Write to full GRC input buffer bits [31:0].
+  #define XCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0_SHIFT                                                        11
+  #define XCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0                                                             (0x1<<12) // Read from empty  GRC input buffer bits [31:0].
+  #define XCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0_SHIFT                                                       12
+  #define XCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1                                                              (0x1<<13) // Write to full GRC input buffer bits [63:32].
+  #define XCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1_SHIFT                                                        13
+  #define XCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1                                                             (0x1<<14) // Read from empty  GRC input buffer bits [63:32].
+  #define XCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1_SHIFT                                                       14
+  #define XCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2                                                              (0x1<<15) // Write to full GRC input buffer bits [95:64].
+  #define XCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2_SHIFT                                                        15
+  #define XCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2                                                             (0x1<<16) // Read from empty  GRC input buffer bits [95:64].
+  #define XCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2_SHIFT                                                       16
+  #define XCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3                                                              (0x1<<17) // Write to full GRC input buffer bits [127:96].
+  #define XCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3_SHIFT                                                        17
+  #define XCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3                                                             (0x1<<18) // Read from empty  GRC input buffer bits [127:96].
+  #define XCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3_SHIFT                                                       18
+  #define XCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL                                                              (0x1<<19) // In-process Table overflow.
+  #define XCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL_SHIFT                                                        19
+  #define XCM_REG_INT_STS_WR_1_AGG_CON_DATA_BUF_OVFL                                                         (0x1<<20) // Message Processor Aggregation Connection Data buffer overflow.
+  #define XCM_REG_INT_STS_WR_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                                   20
+  #define XCM_REG_INT_STS_WR_1_AGG_CON_CMD_BUF_OVFL                                                          (0x1<<21) // Message Processor Aggregation Connection Command buffer overflow.
+  #define XCM_REG_INT_STS_WR_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                                    21
+  #define XCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL                                                          (0x1<<22) // Message Processor Storm Connection Data buffer overflow.
+  #define XCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL_SHIFT                                                    22
+  #define XCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL                                                           (0x1<<23) // Message Processor Storm Connection Command buffer overflow.
+  #define XCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL_SHIFT                                                     23
+  #define XCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE                                                         (0x1<<24) // Input message first descriptor fields violation.
+  #define XCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE_SHIFT                                                   24
+#define XCM_REG_INT_STS_CLR_1                                                                                0x100019cUL //Access:RC   DataWidth:0x19   // Multi Field Register.
+  #define XCM_REG_INT_STS_CLR_1_IS_YSEM_UNDER_ERR                                                            (0x1<<0) // Read from empty  Ysem input buffer.
+  #define XCM_REG_INT_STS_CLR_1_IS_YSEM_UNDER_ERR_SHIFT                                                      0
+  #define XCM_REG_INT_STS_CLR_1_IS_DORQ_OVFL_ERR                                                             (0x1<<1) // Write to full Dorq input buffer.
+  #define XCM_REG_INT_STS_CLR_1_IS_DORQ_OVFL_ERR_SHIFT                                                       1
+  #define XCM_REG_INT_STS_CLR_1_IS_DORQ_UNDER_ERR                                                            (0x1<<2) // Read from empty  Dorq input buffer.
+  #define XCM_REG_INT_STS_CLR_1_IS_DORQ_UNDER_ERR_SHIFT                                                      2
+  #define XCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR                                                              (0x1<<3) // Write to full Pbf input buffer.
+  #define XCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR_SHIFT                                                        3
+  #define XCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR                                                             (0x1<<4) // Read from empty Pbf input buffer.
+  #define XCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR_SHIFT                                                       4
+  #define XCM_REG_INT_STS_CLR_1_IS_TM_OVFL_ERR                                                               (0x1<<5) // Write to full TM input buffer.
+  #define XCM_REG_INT_STS_CLR_1_IS_TM_OVFL_ERR_SHIFT                                                         5
+  #define XCM_REG_INT_STS_CLR_1_IS_TM_UNDER_ERR                                                              (0x1<<6) // Read from empty TM input buffer.
+  #define XCM_REG_INT_STS_CLR_1_IS_TM_UNDER_ERR_SHIFT                                                        6
+  #define XCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR                                                             (0x1<<7) // Write to full QM input buffer.
+  #define XCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR_SHIFT                                                       7
+  #define XCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR                                                            (0x1<<8) // Read from empty QM input buffer.
+  #define XCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR_SHIFT                                                      8
+  #define XCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR                                                             (0x1<<9) // Write to full QM input buffer.
+  #define XCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR_SHIFT                                                       9
+  #define XCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR                                                            (0x1<<10) // Read from empty QM input buffer.
+  #define XCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR_SHIFT                                                      10
+  #define XCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0                                                             (0x1<<11) // Write to full GRC input buffer bits [31:0].
+  #define XCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0_SHIFT                                                       11
+  #define XCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0                                                            (0x1<<12) // Read from empty  GRC input buffer bits [31:0].
+  #define XCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0_SHIFT                                                      12
+  #define XCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1                                                             (0x1<<13) // Write to full GRC input buffer bits [63:32].
+  #define XCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1_SHIFT                                                       13
+  #define XCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1                                                            (0x1<<14) // Read from empty  GRC input buffer bits [63:32].
+  #define XCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1_SHIFT                                                      14
+  #define XCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2                                                             (0x1<<15) // Write to full GRC input buffer bits [95:64].
+  #define XCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2_SHIFT                                                       15
+  #define XCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2                                                            (0x1<<16) // Read from empty  GRC input buffer bits [95:64].
+  #define XCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2_SHIFT                                                      16
+  #define XCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3                                                             (0x1<<17) // Write to full GRC input buffer bits [127:96].
+  #define XCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3_SHIFT                                                       17
+  #define XCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3                                                            (0x1<<18) // Read from empty  GRC input buffer bits [127:96].
+  #define XCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3_SHIFT                                                      18
+  #define XCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL                                                             (0x1<<19) // In-process Table overflow.
+  #define XCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL_SHIFT                                                       19
+  #define XCM_REG_INT_STS_CLR_1_AGG_CON_DATA_BUF_OVFL                                                        (0x1<<20) // Message Processor Aggregation Connection Data buffer overflow.
+  #define XCM_REG_INT_STS_CLR_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                                  20
+  #define XCM_REG_INT_STS_CLR_1_AGG_CON_CMD_BUF_OVFL                                                         (0x1<<21) // Message Processor Aggregation Connection Command buffer overflow.
+  #define XCM_REG_INT_STS_CLR_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                                   21
+  #define XCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL                                                         (0x1<<22) // Message Processor Storm Connection Data buffer overflow.
+  #define XCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL_SHIFT                                                   22
+  #define XCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL                                                          (0x1<<23) // Message Processor Storm Connection Command buffer overflow.
+  #define XCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL_SHIFT                                                    23
+  #define XCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE                                                        (0x1<<24) // Input message first descriptor fields violation.
+  #define XCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE_SHIFT                                                  24
+#define XCM_REG_INT_STS_2                                                                                    0x10001a0UL //Access:R    DataWidth:0x8    // Multi Field Register.
+  #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_MSG_PRCS_UNDER                                                     (0x1<<0) // QM Active State Counter underrun interrupt in case of message processing. Can happen in case of erroneous ExistInQm clears or QM drops.
+  #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_MSG_PRCS_UNDER_SHIFT                                               0
+  #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_MSG_PRCS_OVFL                                                      (0x1<<1) // QM Active State Counter overflow interrupt in case of message processing. Can happen in case of erroneous QM registrations.
+  #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_MSG_PRCS_OVFL_SHIFT                                                1
+  #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_EXT_LD_UNDER                                                       (0x1<<2) // QM Active State Counter underrun interrupt in case of External load. Can happen in case of erroneous decrement or erroneous ExistInQm clears or QM drops.
+  #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_EXT_LD_UNDER_SHIFT                                                 2
+  #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_EXT_LD_OVFL                                                        (0x1<<3) // QM Active State Counter overflow interrupt in case of External load. Can happen in case of erroneous increment.
+  #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_EXT_LD_OVFL_SHIFT                                                  3
+  #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_RBC_UNDER                                                          (0x1<<4) // QM Active State Counter underrun interrupt in case of RBC access. Can happen in case of erroneous decrement or erroneous ExistInQm clears or QM drops.
+  #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_RBC_UNDER_SHIFT                                                    4
+  #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_RBC_OVFL                                                           (0x1<<5) // QM Active State Counter overflow interrupt in case of RBC access. Can happen in case of erroneous increment.
+  #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_RBC_OVFL_SHIFT                                                     5
+  #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_DROP_UNDER                                                         (0x1<<6) // QM Active State Counter underrun interrupt in case of drop. Can happen in case of erroneous decrement.
+  #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_DROP_UNDER_SHIFT                                                   6
+  #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_ILLEG_PQNUM                                                        (0x1<<7) // Access to illegal PQ number in QM Active State Counter (more than 447).
+  #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_ILLEG_PQNUM_SHIFT                                                  7
+#define XCM_REG_INT_MASK_2                                                                                   0x10001a4UL //Access:RW   DataWidth:0x8    // Multi Field Register.
+  #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_MSG_PRCS_UNDER                                                    (0x1<<0) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_2.QM_ACT_ST_CNT_MSG_PRCS_UNDER .
+  #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_MSG_PRCS_UNDER_SHIFT                                              0
+  #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_MSG_PRCS_OVFL                                                     (0x1<<1) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_2.QM_ACT_ST_CNT_MSG_PRCS_OVFL .
+  #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_MSG_PRCS_OVFL_SHIFT                                               1
+  #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_EXT_LD_UNDER                                                      (0x1<<2) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_2.QM_ACT_ST_CNT_EXT_LD_UNDER .
+  #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_EXT_LD_UNDER_SHIFT                                                2
+  #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_EXT_LD_OVFL                                                       (0x1<<3) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_2.QM_ACT_ST_CNT_EXT_LD_OVFL .
+  #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_EXT_LD_OVFL_SHIFT                                                 3
+  #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_RBC_UNDER                                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_2.QM_ACT_ST_CNT_RBC_UNDER .
+  #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_RBC_UNDER_SHIFT                                                   4
+  #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_RBC_OVFL                                                          (0x1<<5) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_2.QM_ACT_ST_CNT_RBC_OVFL .
+  #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_RBC_OVFL_SHIFT                                                    5
+  #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_DROP_UNDER                                                        (0x1<<6) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_2.QM_ACT_ST_CNT_DROP_UNDER .
+  #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_DROP_UNDER_SHIFT                                                  6
+  #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_ILLEG_PQNUM                                                       (0x1<<7) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_2.QM_ACT_ST_CNT_ILLEG_PQNUM .
+  #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_ILLEG_PQNUM_SHIFT                                                 7
+#define XCM_REG_INT_STS_WR_2                                                                                 0x10001a8UL //Access:WR   DataWidth:0x8    // Multi Field Register.
+  #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_MSG_PRCS_UNDER                                                  (0x1<<0) // QM Active State Counter underrun interrupt in case of message processing. Can happen in case of erroneous ExistInQm clears or QM drops.
+  #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_MSG_PRCS_UNDER_SHIFT                                            0
+  #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_MSG_PRCS_OVFL                                                   (0x1<<1) // QM Active State Counter overflow interrupt in case of message processing. Can happen in case of erroneous QM registrations.
+  #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_MSG_PRCS_OVFL_SHIFT                                             1
+  #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_EXT_LD_UNDER                                                    (0x1<<2) // QM Active State Counter underrun interrupt in case of External load. Can happen in case of erroneous decrement or erroneous ExistInQm clears or QM drops.
+  #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_EXT_LD_UNDER_SHIFT                                              2
+  #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_EXT_LD_OVFL                                                     (0x1<<3) // QM Active State Counter overflow interrupt in case of External load. Can happen in case of erroneous increment.
+  #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_EXT_LD_OVFL_SHIFT                                               3
+  #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_RBC_UNDER                                                       (0x1<<4) // QM Active State Counter underrun interrupt in case of RBC access. Can happen in case of erroneous decrement or erroneous ExistInQm clears or QM drops.
+  #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_RBC_UNDER_SHIFT                                                 4
+  #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_RBC_OVFL                                                        (0x1<<5) // QM Active State Counter overflow interrupt in case of RBC access. Can happen in case of erroneous increment.
+  #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_RBC_OVFL_SHIFT                                                  5
+  #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_DROP_UNDER                                                      (0x1<<6) // QM Active State Counter underrun interrupt in case of drop. Can happen in case of erroneous decrement.
+  #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_DROP_UNDER_SHIFT                                                6
+  #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_ILLEG_PQNUM                                                     (0x1<<7) // Access to illegal PQ number in QM Active State Counter (more than 447).
+  #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_ILLEG_PQNUM_SHIFT                                               7
+#define XCM_REG_INT_STS_CLR_2                                                                                0x10001acUL //Access:RC   DataWidth:0x8    // Multi Field Register.
+  #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_MSG_PRCS_UNDER                                                 (0x1<<0) // QM Active State Counter underrun interrupt in case of message processing. Can happen in case of erroneous ExistInQm clears or QM drops.
+  #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_MSG_PRCS_UNDER_SHIFT                                           0
+  #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_MSG_PRCS_OVFL                                                  (0x1<<1) // QM Active State Counter overflow interrupt in case of message processing. Can happen in case of erroneous QM registrations.
+  #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_MSG_PRCS_OVFL_SHIFT                                            1
+  #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_EXT_LD_UNDER                                                   (0x1<<2) // QM Active State Counter underrun interrupt in case of External load. Can happen in case of erroneous decrement or erroneous ExistInQm clears or QM drops.
+  #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_EXT_LD_UNDER_SHIFT                                             2
+  #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_EXT_LD_OVFL                                                    (0x1<<3) // QM Active State Counter overflow interrupt in case of External load. Can happen in case of erroneous increment.
+  #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_EXT_LD_OVFL_SHIFT                                              3
+  #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_RBC_UNDER                                                      (0x1<<4) // QM Active State Counter underrun interrupt in case of RBC access. Can happen in case of erroneous decrement or erroneous ExistInQm clears or QM drops.
+  #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_RBC_UNDER_SHIFT                                                4
+  #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_RBC_OVFL                                                       (0x1<<5) // QM Active State Counter overflow interrupt in case of RBC access. Can happen in case of erroneous increment.
+  #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_RBC_OVFL_SHIFT                                                 5
+  #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_DROP_UNDER                                                     (0x1<<6) // QM Active State Counter underrun interrupt in case of drop. Can happen in case of erroneous decrement.
+  #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_DROP_UNDER_SHIFT                                               6
+  #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_ILLEG_PQNUM                                                    (0x1<<7) // Access to illegal PQ number in QM Active State Counter (more than 447).
+  #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_ILLEG_PQNUM_SHIFT                                              7
+#define XCM_REG_PRTY_MASK_H_0_BB_K2                                                                          0x1000204UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define XCM_REG_PRTY_MASK_H_0_MEM036_I_ECC_RF_INT_K2                                                       (0x1<<0) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM036_I_ECC_RF_INT .
+  #define XCM_REG_PRTY_MASK_H_0_MEM036_I_ECC_RF_INT_K2_SHIFT                                                 0
+  #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT_BB_K2                                                  (0x1<<1) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM003_I_ECC_0_RF_INT .
+  #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT_BB_K2_SHIFT                                            1
+  #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT_BB_K2                                                  (0x1<<2) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM003_I_ECC_1_RF_INT .
+  #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT_BB_K2_SHIFT                                            2
+  #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_2_RF_INT_BB_K2                                                  (0x1<<3) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM003_I_ECC_2_RF_INT .
+  #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_2_RF_INT_BB_K2_SHIFT                                            3
+  #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_3_RF_INT_BB_K2                                                  (0x1<<4) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM003_I_ECC_3_RF_INT .
+  #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_3_RF_INT_BB_K2_SHIFT                                            4
+  #define XCM_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_BB_K2                                                    (0x1<<5) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT .
+  #define XCM_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_BB_K2_SHIFT                                              5
+  #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_0_RF_INT_K2                                                     (0x1<<6) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM033_I_ECC_0_RF_INT .
+  #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_0_RF_INT_K2_SHIFT                                               6
+  #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_1_RF_INT_K2                                                     (0x1<<7) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM033_I_ECC_1_RF_INT .
+  #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_1_RF_INT_K2_SHIFT                                               7
+  #define XCM_REG_PRTY_MASK_H_0_MEM034_I_ECC_RF_INT_K2                                                       (0x1<<8) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM034_I_ECC_RF_INT .
+  #define XCM_REG_PRTY_MASK_H_0_MEM034_I_ECC_RF_INT_K2_SHIFT                                                 8
+  #define XCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_K2                                                      (0x1<<9) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_K2_SHIFT                                                9
+  #define XCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB_K2                                                      (0x1<<10) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB_K2_SHIFT                                                10
+  #define XCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_K2                                                      (0x1<<11) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_K2_SHIFT                                                11
+  #define XCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB                                                         (0x1<<14) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_SHIFT                                                   14
+  #define XCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2                                                         (0x1<<12) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2_SHIFT                                                   12
+  #define XCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB                                                         (0x1<<12) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_SHIFT                                                   12
+  #define XCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2                                                         (0x1<<13) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2_SHIFT                                                   13
+  #define XCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB                                                         (0x1<<13) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_SHIFT                                                   13
+  #define XCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2                                                         (0x1<<14) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2_SHIFT                                                   14
+  #define XCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB                                                         (0x1<<27) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_SHIFT                                                   27
+  #define XCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2                                                         (0x1<<15) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2_SHIFT                                                   15
+  #define XCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB                                                         (0x1<<15) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_SHIFT                                                   15
+  #define XCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2                                                         (0x1<<16) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_SHIFT                                                   16
+  #define XCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB                                                         (0x1<<16) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB_SHIFT                                                   16
+  #define XCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2                                                         (0x1<<17) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2_SHIFT                                                   17
+  #define XCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB                                                         (0x1<<17) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_SHIFT                                                   17
+  #define XCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2                                                         (0x1<<18) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2_SHIFT                                                   18
+  #define XCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB                                                         (0x1<<18) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_SHIFT                                                   18
+  #define XCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2                                                         (0x1<<19) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2_SHIFT                                                   19
+  #define XCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB                                                         (0x1<<19) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_SHIFT                                                   19
+  #define XCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2                                                         (0x1<<20) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_SHIFT                                                   20
+  #define XCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB                                                         (0x1<<20) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_SHIFT                                                   20
+  #define XCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2                                                         (0x1<<21) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2_SHIFT                                                   21
+  #define XCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB                                                         (0x1<<21) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB_SHIFT                                                   21
+  #define XCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2                                                         (0x1<<22) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2_SHIFT                                                   22
+  #define XCM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_K2                                                         (0x1<<23) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_K2_SHIFT                                                   23
+  #define XCM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_BB                                                         (0x1<<22) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_BB_SHIFT                                                   22
+  #define XCM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_K2                                                         (0x1<<24) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_K2_SHIFT                                                   24
+  #define XCM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_BB                                                         (0x1<<23) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_BB_SHIFT                                                   23
+  #define XCM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_K2                                                         (0x1<<25) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_K2_SHIFT                                                   25
+  #define XCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB                                                         (0x1<<25) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_SHIFT                                                   25
+  #define XCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2                                                         (0x1<<26) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2_SHIFT                                                   26
+  #define XCM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_K2                                                         (0x1<<27) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_K2_SHIFT                                                   27
+  #define XCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_K2                                                         (0x1<<28) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_K2_SHIFT                                                   28
+  #define XCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB                                                         (0x1<<28) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_SHIFT                                                   28
+  #define XCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2                                                         (0x1<<29) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_SHIFT                                                   29
+  #define XCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB                                                         (0x1<<29) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_SHIFT                                                   29
+  #define XCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2                                                         (0x1<<30) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2_SHIFT                                                   30
+  #define XCM_REG_PRTY_MASK_H_0_MEM035_I_ECC_RF_INT_BB                                                       (0x1<<0) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM035_I_ECC_RF_INT .
+  #define XCM_REG_PRTY_MASK_H_0_MEM035_I_ECC_RF_INT_BB_SHIFT                                                 0
+  #define XCM_REG_PRTY_MASK_H_0_MEM032_I_ECC_0_RF_INT_BB                                                     (0x1<<6) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM032_I_ECC_0_RF_INT .
+  #define XCM_REG_PRTY_MASK_H_0_MEM032_I_ECC_0_RF_INT_BB_SHIFT                                               6
+  #define XCM_REG_PRTY_MASK_H_0_MEM032_I_ECC_1_RF_INT_BB                                                     (0x1<<7) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM032_I_ECC_1_RF_INT .
+  #define XCM_REG_PRTY_MASK_H_0_MEM032_I_ECC_1_RF_INT_BB_SHIFT                                               7
+  #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_RF_INT_BB                                                       (0x1<<8) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM033_I_ECC_RF_INT .
+  #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_RF_INT_BB_SHIFT                                                 8
+  #define XCM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_BB                                                         (0x1<<24) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_BB_SHIFT                                                   24
+  #define XCM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB                                                         (0x1<<26) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_SHIFT                                                   26
+  #define XCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB                                                         (0x1<<30) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_SHIFT                                                   30
+#define XCM_REG_PRTY_MASK_H_1_BB_K2                                                                          0x1000214UL //Access:RW   DataWidth:0xc    // Multi Field Register.
+  #define XCM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_K2                                                         (0x1<<0) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_K2_SHIFT                                                   0
+  #define XCM_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_K2                                                         (0x1<<1) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM032_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_K2_SHIFT                                                   1
+  #define XCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_BB                                                         (0x1<<1) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_BB_SHIFT                                                   1
+  #define XCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_K2                                                         (0x1<<2) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_K2_SHIFT                                                   2
+  #define XCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_BB                                                         (0x1<<2) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_BB_SHIFT                                                   2
+  #define XCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_K2                                                         (0x1<<3) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_K2_SHIFT                                                   3
+  #define XCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_BB                                                         (0x1<<3) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_BB_SHIFT                                                   3
+  #define XCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_K2                                                         (0x1<<4) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_K2_SHIFT                                                   4
+  #define XCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB                                                         (0x1<<4) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB_SHIFT                                                   4
+  #define XCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_K2                                                         (0x1<<5) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_K2_SHIFT                                                   5
+  #define XCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_BB                                                         (0x1<<5) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_BB_SHIFT                                                   5
+  #define XCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_K2                                                         (0x1<<6) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_K2_SHIFT                                                   6
+  #define XCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_BB                                                         (0x1<<6) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM012_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_BB_SHIFT                                                   6
+  #define XCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_K2                                                         (0x1<<7) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM012_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_K2_SHIFT                                                   7
+  #define XCM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_BB                                                         (0x1<<7) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_BB_SHIFT                                                   7
+  #define XCM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_K2                                                         (0x1<<8) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_K2_SHIFT                                                   8
+  #define XCM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_BB                                                         (0x1<<8) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_BB_SHIFT                                                   8
+  #define XCM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_K2                                                         (0x1<<9) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_K2_SHIFT                                                   9
+  #define XCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB                                                         (0x1<<9) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_SHIFT                                                   9
+  #define XCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2                                                         (0x1<<10) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2_SHIFT                                                   10
+  #define XCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB                                                         (0x1<<10) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_SHIFT                                                   10
+  #define XCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2                                                         (0x1<<11) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2_SHIFT                                                   11
+  #define XCM_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_BB                                                         (0x1<<0) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM031_I_MEM_PRTY .
+  #define XCM_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_BB_SHIFT                                                   0
+#define XCM_REG_MEM_ECC_ENABLE_0_BB_K2                                                                       0x1000220UL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM036_I_ECC_EN_K2                                                        (0x1<<0) // Enable ECC for memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM036_I_ECC_EN_K2_SHIFT                                                  0
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_0_EN_BB_K2                                                   (0x1<<1) // Enable ECC for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_0 in module xcm_mem_agg_con_ctx_0_7
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_0_EN_BB_K2_SHIFT                                             1
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_1_EN_BB_K2                                                   (0x1<<2) // Enable ECC for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_1 in module xcm_mem_agg_con_ctx_0_7
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_1_EN_BB_K2_SHIFT                                             2
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_2_EN_BB_K2                                                   (0x1<<3) // Enable ECC for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_2 in module xcm_mem_agg_con_ctx_0_7
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_2_EN_BB_K2_SHIFT                                             3
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_3_EN_BB_K2                                                   (0x1<<4) // Enable ECC for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_3 in module xcm_mem_agg_con_ctx_0_7
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_3_EN_BB_K2_SHIFT                                             4
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_BB_K2                                                     (0x1<<5) // Enable ECC for memory ecc instance xcm.i_agg_con_ctx_8.i_ecc in module xcm_mem_agg_con_ctx_8
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_BB_K2_SHIFT                                               5
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_0_EN_K2                                                      (0x1<<6) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_0 in module xcm_mem_sm_con_ctx_0_13
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_0_EN_K2_SHIFT                                                6
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_1_EN_K2                                                      (0x1<<7) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_1 in module xcm_mem_sm_con_ctx_0_13
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_1_EN_K2_SHIFT                                                7
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM034_I_ECC_EN_K2                                                        (0x1<<8) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx_14.i_ecc in module xcm_mem_sm_con_ctx_14
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM034_I_ECC_EN_K2_SHIFT                                                  8
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM035_I_ECC_EN_BB                                                        (0x1<<0) // Enable ECC for memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM035_I_ECC_EN_BB_SHIFT                                                  0
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM032_I_ECC_0_EN_BB                                                      (0x1<<6) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_0 in module xcm_mem_sm_con_ctx_0_13
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM032_I_ECC_0_EN_BB_SHIFT                                                6
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM032_I_ECC_1_EN_BB                                                      (0x1<<7) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_1 in module xcm_mem_sm_con_ctx_0_13
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM032_I_ECC_1_EN_BB_SHIFT                                                7
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_EN_BB                                                        (0x1<<8) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx_14.i_ecc in module xcm_mem_sm_con_ctx_14
+  #define XCM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_EN_BB_SHIFT                                                  8
+#define XCM_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                  0x1000224UL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM036_I_ECC_PRTY_K2                                                 (0x1<<0) // Set parity only for memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM036_I_ECC_PRTY_K2_SHIFT                                           0
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_0_PRTY_BB_K2                                            (0x1<<1) // Set parity only for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_0 in module xcm_mem_agg_con_ctx_0_7
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_0_PRTY_BB_K2_SHIFT                                      1
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_1_PRTY_BB_K2                                            (0x1<<2) // Set parity only for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_1 in module xcm_mem_agg_con_ctx_0_7
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_1_PRTY_BB_K2_SHIFT                                      2
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_2_PRTY_BB_K2                                            (0x1<<3) // Set parity only for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_2 in module xcm_mem_agg_con_ctx_0_7
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_2_PRTY_BB_K2_SHIFT                                      3
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_3_PRTY_BB_K2                                            (0x1<<4) // Set parity only for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_3 in module xcm_mem_agg_con_ctx_0_7
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_3_PRTY_BB_K2_SHIFT                                      4
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_BB_K2                                              (0x1<<5) // Set parity only for memory ecc instance xcm.i_agg_con_ctx_8.i_ecc in module xcm_mem_agg_con_ctx_8
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_BB_K2_SHIFT                                        5
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_0_PRTY_K2                                               (0x1<<6) // Set parity only for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_0 in module xcm_mem_sm_con_ctx_0_13
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_0_PRTY_K2_SHIFT                                         6
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_1_PRTY_K2                                               (0x1<<7) // Set parity only for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_1 in module xcm_mem_sm_con_ctx_0_13
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_1_PRTY_K2_SHIFT                                         7
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM034_I_ECC_PRTY_K2                                                 (0x1<<8) // Set parity only for memory ecc instance xcm.i_sm_con_ctx_14.i_ecc in module xcm_mem_sm_con_ctx_14
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM034_I_ECC_PRTY_K2_SHIFT                                           8
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM035_I_ECC_PRTY_BB                                                 (0x1<<0) // Set parity only for memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM035_I_ECC_PRTY_BB_SHIFT                                           0
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM032_I_ECC_0_PRTY_BB                                               (0x1<<6) // Set parity only for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_0 in module xcm_mem_sm_con_ctx_0_13
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM032_I_ECC_0_PRTY_BB_SHIFT                                         6
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM032_I_ECC_1_PRTY_BB                                               (0x1<<7) // Set parity only for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_1 in module xcm_mem_sm_con_ctx_0_13
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM032_I_ECC_1_PRTY_BB_SHIFT                                         7
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_PRTY_BB                                                 (0x1<<8) // Set parity only for memory ecc instance xcm.i_sm_con_ctx_14.i_ecc in module xcm_mem_sm_con_ctx_14
+  #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_PRTY_BB_SHIFT                                           8
+#define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                              0x1000228UL //Access:RC   DataWidth:0x9    // Multi Field Register.
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM036_I_ECC_CORRECT_K2                                          (0x1<<0) // Record if a correctable error occurred on memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM036_I_ECC_CORRECT_K2_SHIFT                                    0
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_0_CORRECT_BB_K2                                     (0x1<<1) // Record if a correctable error occurred on memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_0 in module xcm_mem_agg_con_ctx_0_7
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_0_CORRECT_BB_K2_SHIFT                               1
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_1_CORRECT_BB_K2                                     (0x1<<2) // Record if a correctable error occurred on memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_1 in module xcm_mem_agg_con_ctx_0_7
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_1_CORRECT_BB_K2_SHIFT                               2
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_2_CORRECT_BB_K2                                     (0x1<<3) // Record if a correctable error occurred on memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_2 in module xcm_mem_agg_con_ctx_0_7
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_2_CORRECT_BB_K2_SHIFT                               3
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_3_CORRECT_BB_K2                                     (0x1<<4) // Record if a correctable error occurred on memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_3 in module xcm_mem_agg_con_ctx_0_7
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_3_CORRECT_BB_K2_SHIFT                               4
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_BB_K2                                       (0x1<<5) // Record if a correctable error occurred on memory ecc instance xcm.i_agg_con_ctx_8.i_ecc in module xcm_mem_agg_con_ctx_8
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_BB_K2_SHIFT                                 5
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_0_CORRECT_K2                                        (0x1<<6) // Record if a correctable error occurred on memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_0 in module xcm_mem_sm_con_ctx_0_13
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_0_CORRECT_K2_SHIFT                                  6
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_1_CORRECT_K2                                        (0x1<<7) // Record if a correctable error occurred on memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_1 in module xcm_mem_sm_con_ctx_0_13
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_1_CORRECT_K2_SHIFT                                  7
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM034_I_ECC_CORRECT_K2                                          (0x1<<8) // Record if a correctable error occurred on memory ecc instance xcm.i_sm_con_ctx_14.i_ecc in module xcm_mem_sm_con_ctx_14
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM034_I_ECC_CORRECT_K2_SHIFT                                    8
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM035_I_ECC_CORRECT_BB                                          (0x1<<0) // Record if a correctable error occurred on memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM035_I_ECC_CORRECT_BB_SHIFT                                    0
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM032_I_ECC_0_CORRECT_BB                                        (0x1<<6) // Record if a correctable error occurred on memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_0 in module xcm_mem_sm_con_ctx_0_13
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM032_I_ECC_0_CORRECT_BB_SHIFT                                  6
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM032_I_ECC_1_CORRECT_BB                                        (0x1<<7) // Record if a correctable error occurred on memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_1 in module xcm_mem_sm_con_ctx_0_13
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM032_I_ECC_1_CORRECT_BB_SHIFT                                  7
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_CORRECT_BB                                          (0x1<<8) // Record if a correctable error occurred on memory ecc instance xcm.i_sm_con_ctx_14.i_ecc in module xcm_mem_sm_con_ctx_14
+  #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_CORRECT_BB_SHIFT                                    8
+#define XCM_REG_MEM_ECC_EVENTS_BB_K2                                                                         0x100022cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define XCM_REG_IFEN                                                                                         0x1000400UL //Access:RW   DataWidth:0x1    // Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
+#define XCM_REG_ERR_EVNT_ID                                                                                  0x10004c4UL //Access:RW   DataWidth:0x8    // The Event ID in case one of errors is set in QM input message.
+#define XCM_REG_AGG_CON_RULE0_Q_BB_K2                                                                        0x1000968UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE0_Q_E5                                                                           0x10004c8UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE1_Q_BB_K2                                                                        0x100096cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE1_Q_E5                                                                           0x10004ccUL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE2_Q_BB_K2                                                                        0x1000970UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE2_Q_E5                                                                           0x10004d0UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE3_Q_BB_K2                                                                        0x1000974UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE3_Q_E5                                                                           0x10004d4UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE4_Q_BB_K2                                                                        0x1000978UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE4_Q_E5                                                                           0x10004d8UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE5_Q_BB_K2                                                                        0x100097cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).:
+#define XCM_REG_AGG_CON_RULE5_Q_E5                                                                           0x10004dcUL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE6_Q_BB_K2                                                                        0x1000980UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE6_Q_E5                                                                           0x10004e0UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE7_Q_BB_K2                                                                        0x1000984UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE7_Q_E5                                                                           0x10004e4UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE8_Q_BB_K2                                                                        0x1000988UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE8_Q_E5                                                                           0x10004e8UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE9_Q_BB_K2                                                                        0x100098cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE9_Q_E5                                                                           0x10004ecUL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE10_Q_BB_K2                                                                       0x1000990UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE10_Q_E5                                                                          0x10004f0UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE11_Q_BB_K2                                                                       0x1000994UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE11_Q_E5                                                                          0x10004f4UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE12_Q_BB_K2                                                                       0x1000998UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE12_Q_E5                                                                          0x10004f8UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE13_Q_BB_K2                                                                       0x100099cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE13_Q_E5                                                                          0x10004fcUL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE14_Q_BB_K2                                                                       0x10009a0UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE14_Q_E5                                                                          0x1000500UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE15_Q_BB_K2                                                                       0x10009a4UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE15_Q_E5                                                                          0x1000504UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE16_Q_BB_K2                                                                       0x10009a8UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE16_Q_E5                                                                          0x1000508UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE17_Q_BB_K2                                                                       0x10009acUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE17_Q_E5                                                                          0x100050cUL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE18_Q_BB_K2                                                                       0x10009b0UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE18_Q_E5                                                                          0x1000510UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE19_Q_BB_K2                                                                       0x10009b4UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE19_Q_E5                                                                          0x1000514UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE20_Q_BB_K2                                                                       0x10009b8UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE20_Q_E5                                                                          0x1000518UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE21_Q_BB_K2                                                                       0x10009bcUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE21_Q_E5                                                                          0x100051cUL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE22_Q_BB_K2                                                                       0x10009c0UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE22_Q_E5                                                                          0x1000520UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE23_Q_BB_K2                                                                       0x10009c4UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE23_Q_E5                                                                          0x1000524UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE24_Q_BB_K2                                                                       0x10009c8UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE24_Q_E5                                                                          0x1000528UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE25_Q_BB_K2                                                                       0x10009ccUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define XCM_REG_AGG_CON_RULE25_Q_E5                                                                          0x100052cUL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE26_Q_E5                                                                          0x1000530UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_AGG_CON_RULE27_Q_E5                                                                          0x1000534UL //Access:RW   DataWidth:0x3    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define XCM_REG_STORM_WEIGHT                                                                                 0x1000604UL //Access:RW   DataWidth:0x3    // The weight of the local Storm input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define XCM_REG_MSEM_WEIGHT                                                                                  0x1000608UL //Access:RW   DataWidth:0x3    // The weight of the input Msem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define XCM_REG_USEM_WEIGHT                                                                                  0x100060cUL //Access:RW   DataWidth:0x3    // The weight of the input Usem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define XCM_REG_DORQ_WEIGHT                                                                                  0x1000614UL //Access:RW   DataWidth:0x3    // The weight of the input Dorq in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define XCM_REG_PBF_WEIGHT                                                                                   0x1000618UL //Access:RW   DataWidth:0x3    // The weight of the input Pbf in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define XCM_REG_GRC_WEIGHT                                                                                   0x100061cUL //Access:RW   DataWidth:0x3    // The weight of the GRC input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define XCM_REG_XSDM_WEIGHT                                                                                  0x1000624UL //Access:RW   DataWidth:0x3    // The weight of the XSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define XCM_REG_YSDM_WEIGHT                                                                                  0x1000628UL //Access:RW   DataWidth:0x3    // The weight of the YSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define XCM_REG_USDM_WEIGHT                                                                                  0x100062cUL //Access:RW   DataWidth:0x3    // The weight of the input USDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define XCM_REG_QM_P_WEIGHT                                                                                  0x1000630UL //Access:RW   DataWidth:0x3    // The weight of the QM (primary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define XCM_REG_QM_S_WEIGHT                                                                                  0x1000634UL //Access:RW   DataWidth:0x3    // The weight of the QM (secondary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define XCM_REG_TM_WEIGHT                                                                                    0x1000638UL //Access:RW   DataWidth:0x3    // The weight of the Timers input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define XCM_REG_IA_GROUP_PR0                                                                                 0x100063cUL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: ia_group_pr0 is the highest priority; ia_group_pr5 is the lowest priority.
+#define XCM_REG_IA_GROUP_PR1                                                                                 0x1000640UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define XCM_REG_IA_GROUP_PR2                                                                                 0x1000644UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define XCM_REG_IA_GROUP_PR3                                                                                 0x1000648UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define XCM_REG_IA_GROUP_PR4                                                                                 0x100064cUL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define XCM_REG_IA_GROUP_PR5                                                                                 0x1000650UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define XCM_REG_IA_ARB_SP_TIMEOUT                                                                            0x1000654UL //Access:RW   DataWidth:0x8    // Input Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8'h0 - constant RR; 8'h80 - constant strict priority. In all other cases the following is true: Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance.
+#define XCM_REG_STORM_FRWRD_MODE                                                                             0x1000658UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define XCM_REG_XSDM_FRWRD_MODE                                                                              0x1000660UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define XCM_REG_YSDM_FRWRD_MODE                                                                              0x1000664UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define XCM_REG_USDM_FRWRD_MODE                                                                              0x1000668UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define XCM_REG_MSEM_FRWRD_MODE                                                                              0x100066cUL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define XCM_REG_USEM_FRWRD_MODE                                                                              0x1000670UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define XCM_REG_DORQ_FRWRD_MODE                                                                              0x1000678UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define XCM_REG_PBF_FRWRD_MODE                                                                               0x100067cUL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define XCM_REG_SDM_ERR_HANDLE_EN                                                                            0x1000680UL //Access:RW   DataWidth:0x1    // 0 - disable error handling in SDM message; 1 - enable error handling in SDM message.
+#define XCM_REG_DIR_BYP_EN                                                                                   0x1000684UL //Access:RW   DataWidth:0x1    // Direct bypass enable.
+#define XCM_REG_FI_DESC_INPUT_VIOLATE                                                                        0x1000688UL //Access:R    DataWidth:0xf    // Input message first descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0  then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL  then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation:  Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation:  TaskExist==0 -> XxLockCmd != XX_UNLOCK_CID_TID and XxLockCmd != XX_LOCK_CID_TID_BYPASS;  [12] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0;[13] - Violation: Agg message: Loader done with error then SmCtxLdStFlg==0; [14] - Violation: XxBypass message in PCM block;
+#define XCM_REG_IA_AGG_CON_PART_FILL_LVL                                                                     0x100068cUL //Access:R    DataWidth:0x3    // Input Arbiter Aggregation Connection part FIFO fill level (in messages).
+#define XCM_REG_IA_SM_CON_PART_FILL_LVL                                                                      0x1000690UL //Access:R    DataWidth:0x3    // Input Arbiter Storm Connection part FIFO fill level (in messages).
+#define XCM_REG_IA_TRANS_PART_FILL_LVL                                                                       0x1000694UL //Access:R    DataWidth:0x3    // Input Arbiter Transparent part FIFO fill level (in messages).
+#define XCM_REG_EXT_RD_FILL_LVL_E5                                                                           0x1000698UL //Access:R    DataWidth:0x2    // External read buffer FIFO fill level (in FIFO entries).
+#define XCM_REG_XX_MSG_UP_BND                                                                                0x1000704UL //Access:RW   DataWidth:0x7    // The maximum number of Xx RAM messages; which may be stored in XX protection. Is restricted by Xx Messages RAM size and the size of Xx protected message CM_REGISTERS_XX_MSG_SIZE.XX_MSG_SIZE
+#define XCM_REG_XX_MSG_SIZE                                                                                  0x1000708UL //Access:RW   DataWidth:0x2    // The size of Xx protected message in Xx Messages RAM in QREGs. Upper rounded to 4 and multiplied by CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND should not exceed XxMessagesRam size which is: MCM: 0d1792 PCM: 0d176 TCM: 0d1536 UCM: 0d1792 XCM: 0d256 YCM: 0d1536
+#define XCM_REG_XX_LCID_CAM_UP_BND                                                                           0x100070cUL //Access:RW   DataWidth:0x7    // The maximum number of connections in the XX protection LCID CAM.
+#define XCM_REG_XX_FREE_CNT                                                                                  0x1000710UL //Access:R    DataWidth:0x7    // Used to read the XX protection Free counter. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND
+#define XCM_REG_XX_LCID_CAM_FILL_LVL                                                                         0x1000714UL //Access:R    DataWidth:0x7    // Used to read XX protection LCID CAM fill level. Fill level is calculated as the number of locked LCIDs, i.e. LCIDs that have at least one Xx locked message or LCIDs that have no Xx locked messages but haven't been unlocked yet from LCID CAM. Simple saying it calculates for number of valid entries in LCID CAM.
+#define XCM_REG_XX_LCID_CAM_ST_STAT                                                                          0x1000718UL //Access:RC   DataWidth:0x7    // CAM occupancy sticky status. The write to the register is performed by the XX internal circuitry.
+#define XCM_REG_XX_IA_GROUP_PR0                                                                              0x100071cUL //Access:RW   DataWidth:0x1    // Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
+#define XCM_REG_XX_IA_GROUP_PR1                                                                              0x1000720UL //Access:RW   DataWidth:0x1    // Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
+#define XCM_REG_XX_NON_LOCK_LCID_THR                                                                         0x1000724UL //Access:RW   DataWidth:0x7    // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decision of Xx Input Arbiter non-locked group.
+#define XCM_REG_XX_LOCK_LCID_THR                                                                             0x1000728UL //Access:RW   DataWidth:0x7    // Xx locked LCIDs threshold (maximum value). Participates in Xx Bypass global enable decision.
+#define XCM_REG_XX_IA_ARB_SP_TIMEOUT                                                                         0x100072cUL //Access:RW   DataWidth:0x8    // Xx Input Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. E.g. bits[6:0]=0; bit[7]=0 - always strict priority; bits[6:0]=1; bit[7]=0 - strict priority; then RR; bits[6:0]=3; bit[7]=0 - 3 times strict priority; then RR.
+#define XCM_REG_XX_FREE_HEAD_PTR                                                                             0x1000730UL //Access:R    DataWidth:0x6    // Xx Free Head Pointer.
+#define XCM_REG_XX_FREE_TAIL_PTR                                                                             0x1000734UL //Access:R    DataWidth:0x6    // Xx Free Tail Pointer. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND
+#define XCM_REG_XX_NON_LOCK_CNT                                                                              0x1000738UL //Access:R    DataWidth:0x7    // Xx NonLock Counter.
+#define XCM_REG_XX_LOCK_CNT                                                                                  0x100073cUL //Access:R    DataWidth:0x7    // Xx Lock Counter.
+#define XCM_REG_XX_LCID_ARB_GROUP_PR0                                                                        0x1000740UL //Access:RW   DataWidth:0x2    // Xx LCID Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.
+#define XCM_REG_XX_LCID_ARB_GROUP_PR1                                                                        0x1000744UL //Access:RW   DataWidth:0x2    // Xx LCID Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.
+#define XCM_REG_XX_LCID_ARB_GROUP_PR2                                                                        0x1000748UL //Access:RW   DataWidth:0x2    // Xx LCID Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.
+#define XCM_REG_XX_LCID_ARB_SP_TIMEOUT                                                                       0x100074cUL //Access:RW   DataWidth:0x8    // Xx LCID Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. E.g. bits[6:0]=0; bit[7]=0 - always strict priority; bits[6:0]=1; bit[7]=0 - strict priority; then RR; bits[6:0]=3; bit[7]=0 - 3 times strict priority; then RR.
+#define XCM_REG_XX_FREE_THR_HIGH                                                                             0x1000750UL //Access:RW   DataWidth:0x7    // Xx free messages threshold high. Used in Xx Bypass global enable condition.
+#define XCM_REG_XX_FREE_THR_LOW                                                                              0x1000754UL //Access:RW   DataWidth:0x7    // Xx free messages threshold low Used in Xx Bypass global enable condition.
+#define XCM_REG_XX_CBYP_TBL_FILL_LVL                                                                         0x1000758UL //Access:R    DataWidth:0x4    // Xx Connection Bypass Table fill level (in connections).
+#define XCM_REG_XX_CBYP_TBL_ST_STAT                                                                          0x100075cUL //Access:RC   DataWidth:0x4    // Xx Connection Bypass Table sticky status. Reset on read.
+#define XCM_REG_XX_CBYP_TBL_UP_BND                                                                           0x1000760UL //Access:RW   DataWidth:0x4    // Xx Bypass Table (Connection) maximum fill level.
+#define XCM_REG_XX_BYP_LOCK_MSG_THR                                                                          0x1000784UL //Access:RW   DataWidth:0x6    // Xx Bypass messages lock threshold. The number of locked messages per LCID is above this threshold is one of conditions to start XxBypass for this LCID.
+#define XCM_REG_XX_PREF_DIR_FILL_LVL                                                                         0x1000788UL //Access:R    DataWidth:0x3    // Xx LCID Arbiter direct prefetch FIFO fill level (in entries).
+#define XCM_REG_XX_PREF_AGGST_FILL_LVL                                                                       0x100078cUL //Access:R    DataWidth:0x3    // Xx LCID Arbiter aggregation store prefetch FIFO fill level (in entries).
+#define XCM_REG_XX_PREF_BYP_FILL_LVL                                                                         0x1000790UL //Access:R    DataWidth:0x3    // Xx LCID Arbiter bypass prefetch FIFO fill level (in entries).
+#define XCM_REG_UNLOCK_MISS                                                                                  0x1000794UL //Access:RC   DataWidth:0x1    // Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM.
+#define XCM_REG_ERR_AFFINITY_TYPE_E5                                                                         0x1000798UL //Access:RW   DataWidth:0x2    // Affinity type in case of input message error.
+#define XCM_REG_ERR_EXCLUSIVE_FLG_E5                                                                         0x100079cUL //Access:RW   DataWidth:0x1    // Exclusive type in case of input message error.
+#define XCM_REG_ERR_SRC_AFFINITY_E5                                                                          0x10007a0UL //Access:RW   DataWidth:0x3    // Source affinity in case of input message error.
+#define XCM_REG_XX_BYP_MSG_UP_BND_0_BB_K2                                                                    0x1000764UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define XCM_REG_XX_BYP_MSG_UP_BND_0_E5                                                                       0x10007a4UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define XCM_REG_XX_BYP_MSG_UP_BND_1_BB_K2                                                                    0x1000768UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define XCM_REG_XX_BYP_MSG_UP_BND_1_E5                                                                       0x10007a8UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define XCM_REG_XX_BYP_MSG_UP_BND_2_BB_K2                                                                    0x100076cUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define XCM_REG_XX_BYP_MSG_UP_BND_2_E5                                                                       0x10007acUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define XCM_REG_XX_BYP_MSG_UP_BND_3_BB_K2                                                                    0x1000770UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define XCM_REG_XX_BYP_MSG_UP_BND_3_E5                                                                       0x10007b0UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define XCM_REG_XX_BYP_MSG_UP_BND_4_BB_K2                                                                    0x1000774UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define XCM_REG_XX_BYP_MSG_UP_BND_4_E5                                                                       0x10007b4UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define XCM_REG_XX_BYP_MSG_UP_BND_5_BB_K2                                                                    0x1000778UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define XCM_REG_XX_BYP_MSG_UP_BND_5_E5                                                                       0x10007b8UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define XCM_REG_XX_BYP_MSG_UP_BND_6_BB_K2                                                                    0x100077cUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define XCM_REG_XX_BYP_MSG_UP_BND_6_E5                                                                       0x10007bcUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define XCM_REG_XX_BYP_MSG_UP_BND_7_BB_K2                                                                    0x1000780UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define XCM_REG_XX_BYP_MSG_UP_BND_7_E5                                                                       0x10007c0UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define XCM_REG_XX_BYP_MSG_UP_BND_8_E5                                                                       0x10007c4UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define XCM_REG_XX_BYP_MSG_UP_BND_9_E5                                                                       0x10007c8UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define XCM_REG_XX_BYP_MSG_UP_BND_10_E5                                                                      0x10007ccUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define XCM_REG_XX_BYP_MSG_UP_BND_11_E5                                                                      0x10007d0UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define XCM_REG_XX_BYP_MSG_UP_BND_12_E5                                                                      0x10007d4UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define XCM_REG_XX_BYP_MSG_UP_BND_13_E5                                                                      0x10007d8UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define XCM_REG_XX_BYP_MSG_UP_BND_14_E5                                                                      0x10007dcUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define XCM_REG_XX_BYP_MSG_UP_BND_15_E5                                                                      0x10007e0UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define XCM_REG_PRCS_AGG_CON_CURR_ST                                                                         0x1000804UL //Access:R    DataWidth:0x4    // Aggregation Connection Processor FSM.
+#define XCM_REG_PRCS_SM_CON_CURR_ST                                                                          0x1000808UL //Access:R    DataWidth:0x2    // STORM Connection Processor FSM.
+#define XCM_REG_AGG_CON_FIC_BUF_FILL_LVL                                                                     0x100082cUL //Access:R    DataWidth:0x4    // Aggregation Connection FIC buffer fill level (in messages).
+#define XCM_REG_SM_CON_FIC_BUF_FILL_LVL                                                                      0x1000830UL //Access:R    DataWidth:0x5    // Storm Connection FIC buffer fill level (in messages).
+#define XCM_REG_AGG_CON_FIC_BUF_CRD                                                                          0x1000834UL //Access:RW   DataWidth:0x2    // Aggregation Connection FIC buffer credit (in full message out parts).
+#define XCM_REG_SM_CON_FIC_BUF_CRD                                                                           0x1000838UL //Access:RW   DataWidth:0x2    // Storm Connection FIC buffer credit (in full message out parts).
+#define XCM_REG_AGG_CON_BUF_CRD_AGG                                                                          0x100083cUL //Access:RW   DataWidth:0x3    // Aggregation Connection buffer (data or command) credit (Aggregation group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than Agregation Connection data buffer size=4. In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST and CM_REGISTERS_AGG_CON_CMD_BUF_CRD_DIR.AGG_CON_CMD_BUF_CRD_DIR need be no more than Agregation Connection command buffer size=6.
+#define XCM_REG_AGG_CON_BUF_CRD_AGGST                                                                        0x1000840UL //Access:RW   DataWidth:0x3    // Aggregation Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG need be no more than Agregation Connection data buffer size=4. In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG and CM_REGISTERS_AGG_CON_CMD_BUF_CRD_DIR.AGG_CON_CMD_BUF_CRD_DIR need be no more than Agregation Connection command buffer size=6.
+#define XCM_REG_SM_CON_BUF_CRD_AGGST                                                                         0x1000844UL //Access:RW   DataWidth:0x1    // Storm Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_CON_CMD_BUF_CRD_DIR.SM_CON_CMD_BUF_CRD_DIR need be no more than Storm Connection command buffer size=3.
+#define XCM_REG_AGG_CON_CMD_BUF_CRD_DIR                                                                      0x1000848UL //Access:RW   DataWidth:0x2    // Aggregation Connection command buffer credit (Direct group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG and XCM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than Agregation Connection command buffer size=6.
+#define XCM_REG_SM_CON_CMD_BUF_CRD_DIR                                                                       0x100084cUL //Access:RW   DataWidth:0x2    // Storm Connection command buffer credit (Direct group). In sum with CM_REGISTERS_SM_CON_BUF_CRD_AGGST.SM_CON_BUF_CRD_AGGST need be no more than Storm Connection command buffer size=3.
+#define XCM_REG_TRANS_DATA_BUF_CRD_DIR                                                                       0x1000850UL //Access:RW   DataWidth:0x2    // Transparent data buffer credit (Direct group).
+#define XCM_REG_CM_CON_REG0_SZ                                                                               0x1000874UL //Access:RW   DataWidth:0x3    // The size of AGG Connection context region 0 in REGQ. Is used to determine the number of the AG context REGQ written back; when the Reg1WbFlg isn't set.
+#define XCM_REG_SM_CON_CTX_SIZE                                                                              0x1000878UL //Access:RW   DataWidth:0x5    // STORM Connnection context per LCID size (REGQ). Default context size of 15 (REGQ) complies to 320 LCIDs. Maximum context size per LCID is 24. Maximum number of LCIDs allowed at maximum context size per LCID is 200. If not at default value need to be 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER((320*INTEGER(15/2))/(24/2)).
+#define XCM_REG_CON_PHY_Q3                                                                                   0x1000904UL //Access:RW   DataWidth:0xa    // [9]: PQ Type (0-Other PQ; 1-TX PQ); if bit[9]=0; then [8:6] reserved; [5:0] Physical queue connection number (queue number 3); if bit[9]=1; then [8:0] Physical queue connection number (queue number 3).
+#define XCM_REG_IN_PRCS_TBL_CRD_AGG                                                                          0x1000a04UL //Access:RW   DataWidth:0x4    // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.IN_PRCS_TBL_CRD_AGGST need be no more than In-process table size=12.
+#define XCM_REG_IN_PRCS_TBL_CRD_AGGST                                                                        0x1000a08UL //Access:RW   DataWidth:0x4    // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGG.IN_PRCS_TBL_CRD_AGG need be no more than In-process table size=12.
+#define XCM_REG_IN_PRCS_TBL_FILL_LVL                                                                         0x1000a0cUL //Access:R    DataWidth:0x4    // In-process Table fill level  (in messages).
+#define XCM_REG_IN_PRCS_TBL_ALMOST_FULL                                                                      0x1000a10UL //Access:R    DataWidth:0x1    // In-process Table almost full.
+#define XCM_REG_QMCON_CURR_ST                                                                                0x1000a14UL //Access:R    DataWidth:0x3    // QM connection registration FSM current state.
+#define XCM_REG_TMCON_CURR_ST                                                                                0x1000a18UL //Access:R    DataWidth:0x1    // TM connection output FSM current state.
+#define XCM_REG_CCFC_CURR_ST                                                                                 0x1000a1cUL //Access:R    DataWidth:0x1    // CFC connection output FSM current state.
+#define XCM_REG_CMPL_DIR_CURR_ST                                                                             0x1000a20UL //Access:R    DataWidth:0x4    // Direct Completer FSM current state.
+#define XCM_REG_XX_BYP_CON_STATE_EVNT_ID_FLG                                                                 0x1000a24UL //Access:RW   DataWidth:0x1    // If set, Xx connection bypass state will be added in calculation of CM output Event ID.
+#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_0_E5                                                                  0x1000a28UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_1_E5                                                                  0x1000a2cUL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_2_E5                                                                  0x1000a30UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_3_E5                                                                  0x1000a34UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_4_E5                                                                  0x1000a38UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_5_E5                                                                  0x1000a3cUL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_6_E5                                                                  0x1000a40UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_7_E5                                                                  0x1000a44UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_8_E5                                                                  0x1000a48UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_9_E5                                                                  0x1000a4cUL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_10_E5                                                                 0x1000a50UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_11_E5                                                                 0x1000a54UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_12_E5                                                                 0x1000a58UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_13_E5                                                                 0x1000a5cUL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_14_E5                                                                 0x1000a60UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_15_E5                                                                 0x1000a64UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define XCM_REG_CCFC_INIT_CRD                                                                                0x1000a84UL //Access:RW   DataWidth:0x4    // CCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.
+#define XCM_REG_QM_INIT_CRD0                                                                                 0x1000a88UL //Access:RW   DataWidth:0x5    // QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 16.Write writes the initial credit value; read returns the current value of the credit counter.
+#define XCM_REG_QM_INIT_CRD1                                                                                 0x1000a8cUL //Access:RW   DataWidth:0x5    // QM output initial credit (XCM TX queues). Max credit available - 16.Write writes the initial credit value; read returns the current value of the credit counter.
+#define XCM_REG_TM_INIT_CRD                                                                                  0x1000a90UL //Access:RW   DataWidth:0x4    // Timers output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.
+#define XCM_REG_FIC_INIT_CRD                                                                                 0x1000a94UL //Access:RW   DataWidth:0x6    // FIC output initial credit. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 44 at start-up.
+#define XCM_REG_DIR_BYP_MSG_CNT                                                                              0x1000aa4UL //Access:RC   DataWidth:0x20   // Counter of direct bypassed messages.
+#define XCM_REG_XSDM_LENGTH_MIS                                                                              0x1000aacUL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at XSDM interface.
+#define XCM_REG_YSDM_LENGTH_MIS                                                                              0x1000ab0UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at YSDM interface.
+#define XCM_REG_USDM_LENGTH_MIS                                                                              0x1000ab4UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at USDM interface.
+#define XCM_REG_DORQ_LENGTH_MIS                                                                              0x1000ab8UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at the dorq interface.
+#define XCM_REG_PBF_LENGTH_MIS                                                                               0x1000abcUL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at PBF interface.
+#define XCM_REG_GRC_BUF_EMPTY                                                                                0x1000ac0UL //Access:R    DataWidth:0x1    // Input Stage GRC buffer is empty.
+#define XCM_REG_GRC_BUF_STATUS                                                                               0x1000ac4UL //Access:R    DataWidth:0x6    // Input Stage GRC buffer status.
+#define XCM_REG_STORM_MSG_CNTR                                                                               0x1000ac8UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the STORM input.
+#define XCM_REG_XSDM_MSG_CNTR                                                                                0x1000ad0UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input XSDM.
+#define XCM_REG_YSDM_MSG_CNTR                                                                                0x1000ad4UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input YSDM.
+#define XCM_REG_USDM_MSG_CNTR                                                                                0x1000ad8UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input USDM.
+#define XCM_REG_MSEM_MSG_CNTR                                                                                0x1000adcUL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input MSEM.
+#define XCM_REG_USEM_MSG_CNTR                                                                                0x1000ae0UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at input USEM.
+#define XCM_REG_DORQ_MSG_CNTR                                                                                0x1000ae8UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at  input DORQ.
+#define XCM_REG_PBF_MSG_CNTR                                                                                 0x1000aecUL //Access:RC   DataWidth:0x1c   // Counter of the input messages at input PBF.
+#define XCM_REG_QM_P_MSG_CNTR                                                                                0x1000af0UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the QM input (primary).
+#define XCM_REG_QM_S_MSG_CNTR                                                                                0x1000af4UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the QM input (secondary).
+#define XCM_REG_TM_MSG_CNTR                                                                                  0x1000af8UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the Timers input.
+#define XCM_REG_IS_GRC                                                                                       0x1000afcUL //Access:W    DataWidth:0x20   // Used to write the GRC message. Write only. To distinguish if the register can be accessed to write GRC message                           polling of CM_REGISTERS.GRC_BUF_EMPTY need to be done
+#define XCM_REG_IS_QM_P_FILL_LVL                                                                             0x1000b00UL //Access:R    DataWidth:0x4    // Number of QREGs (128b) of data in QM Primary Input Stage (except of bypass).
+#define XCM_REG_IS_QM_S_FILL_LVL                                                                             0x1000b04UL //Access:R    DataWidth:0x4    // Number of QREGs (128b) of data in QM Secondary Input Stage (except of bypass).
+#define XCM_REG_IS_TM_FILL_LVL                                                                               0x1000b08UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in TM Input Stage.
+#define XCM_REG_IS_STORM_FILL_LVL                                                                            0x1000b0cUL //Access:R    DataWidth:0x6    // Number of entries (2 QREGs each) of data in STORM Input Stage.
+#define XCM_REG_IS_XSDM_FILL_LVL                                                                             0x1000b14UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in XSDM Input Stage.
+#define XCM_REG_IS_YSDM_FILL_LVL                                                                             0x1000b18UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in YSDM Input Stage.
+#define XCM_REG_IS_USDM_FILL_LVL                                                                             0x1000b1cUL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in USDM Input Stage.
+#define XCM_REG_IS_MSEM_FILL_LVL                                                                             0x1000b20UL //Access:R    DataWidth:0x4    // Number of QREGs (128b) in TCM, YCM or 2 QREGs (256b) in XCM of data in MSEM Input Stage.
+#define XCM_REG_IS_USEM_FILL_LVL                                                                             0x1000b24UL //Access:R    DataWidth:0x4    // Number of QREGs (128b) of data in USEM Input Stage.
+#define XCM_REG_IS_DORQ_FILL_LVL                                                                             0x1000b2cUL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in DORQ Input Stage.
+#define XCM_REG_IS_PBF_FILL_LVL                                                                              0x1000b30UL //Access:R    DataWidth:0x4    // Number of QREGs (128b) of data in PBF Input Stage.
+#define XCM_REG_QM_ACT_ST_FIFO_FILL_LVL                                                                      0x1000b44UL //Access:R    DataWidth:0x4    // QM Active State Counter FIFO fill level (entries).
+#define XCM_REG_QM_ACT_CNT_RD_CURR_ST                                                                        0x1000b48UL //Access:R    DataWidth:0x3    // QM Active State Counter read FSM.
+#define XCM_REG_QM_ACT_ST_CURR_ST                                                                            0x1000b4cUL //Access:R    DataWidth:0x1    // QM Active State output FSM.
+#define XCM_REG_QM_ACT_ST_CNT_ERR_DETAILS                                                                    0x1000b50UL //Access:RW   DataWidth:0xb    // Tracks error details of the transaction, which caused QM Active counter overflow/uder-run. Is reset on read. [0] - If set, there was under-run; [1] - If set, there was overflow; [10:2] - PQ number;
+#define XCM_REG_FIC_MSG_CNTR                                                                                 0x1000b54UL //Access:RC   DataWidth:0x1c   // Counter of the output messages at FIC interfaces.
+#define XCM_REG_QM_OUT_CNTR                                                                                  0x1000b58UL //Access:RC   DataWidth:0x1c   // Counter of the output QM commands.
+#define XCM_REG_TM_OUT_CNTR                                                                                  0x1000b5cUL //Access:RC   DataWidth:0x1c   // Counter of the output Timers commands.
+#define XCM_REG_DONE0_CNTR                                                                                   0x1000b60UL //Access:RC   DataWidth:0x1c   // Counter of the output Done0.
+#define XCM_REG_DONE1_CNTR                                                                                   0x1000b64UL //Access:RC   DataWidth:0x1c   // Counter of the output Done1.
+#define XCM_REG_DONE2_CNTR                                                                                   0x1000b68UL //Access:RC   DataWidth:0x1c   // Counter of the output Done2.
+#define XCM_REG_CCFC_CNTR                                                                                    0x1000b6cUL //Access:RC   DataWidth:0x1c   // Counter of the output CCFC.
+#define XCM_REG_ECO_RESERVED                                                                                 0x1000b84UL //Access:RW   DataWidth:0x8    // Chicken bits.
+#define XCM_REG_IS_FOC_MSEM_NXT_INF_UNIT                                                                     0x1000b88UL //Access:R    DataWidth:0x5    // Debug read from MSEM Input stage buffer: number of reads to next information unit.
+#define XCM_REG_IS_FOC_USEM_NXT_INF_UNIT                                                                     0x1000b8cUL //Access:R    DataWidth:0x6    // Debug read from USEM Input stage buffer: number of reads to next information unit.
+#define XCM_REG_IS_FOC_XSEM_NXT_INF_UNIT                                                                     0x1000b90UL //Access:R    DataWidth:0x5    // Debug read from XSEM Input stage buffer: number of reads to next information unit.
+#define XCM_REG_IS_FOC_PBF_NXT_INF_UNIT                                                                      0x1000b98UL //Access:R    DataWidth:0x6    // Debug read from PBF Input stage buffer: number of reads to next information unit.
+#define XCM_REG_IS_FOC_DORQ_NXT_INF_UNIT                                                                     0x1000b9cUL //Access:R    DataWidth:0x6    // Debug read from DORQ Input stage buffer: number of reads to next information unit.
+#define XCM_REG_IS_FOC_USDM_NXT_INF_UNIT                                                                     0x1000ba4UL //Access:R    DataWidth:0x6    // Debug read from USDM Input stage buffer: number of reads to next information unit.
+#define XCM_REG_IS_FOC_XSDM_NXT_INF_UNIT                                                                     0x1000ba8UL //Access:R    DataWidth:0x6    // Debug read from XSDM Input stage buffer: number of reads to next information unit.
+#define XCM_REG_IS_FOC_YSDM_NXT_INF_UNIT                                                                     0x1000bacUL //Access:R    DataWidth:0x6    // Debug read from YSDM Input stage buffer: number of reads to next information unit.
+#define XCM_REG_IS_FOC_MSEM                                                                                  0x1000c00UL //Access:R    DataWidth:0x20   // Debug read from MSEM Input stage buffer with 32-bits granularity. Read only.
+#define XCM_REG_IS_FOC_MSEM_SIZE_BB_K2                                                                       72
+#define XCM_REG_IS_FOC_MSEM_SIZE_E5                                                                          80
+#define XCM_REG_IS_FOC_USEM                                                                                  0x1000e00UL //Access:R    DataWidth:0x20   // Debug read from USEM Input stage buffer with 32-bits granularity. Read only.
+#define XCM_REG_IS_FOC_USEM_SIZE                                                                             44
+#define XCM_REG_IS_FOC_XSEM                                                                                  0x1001000UL //Access:R    DataWidth:0x20   // Debug read from XSEM Input stage buffer with 32-bits granularity. Read only.
+#define XCM_REG_IS_FOC_XSEM_SIZE                                                                             256
+#define XCM_REG_IS_FOC_PBF                                                                                   0x1001500UL //Access:R    DataWidth:0x20   // Debug read from PBF Input stage buffer with 32-bits granularity. Read only.
+#define XCM_REG_IS_FOC_PBF_SIZE                                                                              36
+#define XCM_REG_IS_FOC_DORQ                                                                                  0x1001600UL //Access:R    DataWidth:0x20   // Debug read from DORQ Input stage buffer with 32-bits granularity. Read only.
+#define XCM_REG_IS_FOC_DORQ_SIZE                                                                             24
+#define XCM_REG_IS_FOC_USDM                                                                                  0x1001700UL //Access:R    DataWidth:0x20   // Debug read from USDM Input stage buffer with 32-bits granularity. Read only.
+#define XCM_REG_IS_FOC_USDM_SIZE                                                                             28
+#define XCM_REG_IS_FOC_XSDM                                                                                  0x1001780UL //Access:R    DataWidth:0x20   // Debug read from XSDM Input stage buffer with 32-bits granularity. Read only.
+#define XCM_REG_IS_FOC_XSDM_SIZE                                                                             16
+#define XCM_REG_IS_FOC_YSDM                                                                                  0x10017c0UL //Access:R    DataWidth:0x20   // Debug read from YSDM Input stage buffer with 32-bits granularity. Read only.
+#define XCM_REG_IS_FOC_YSDM_SIZE                                                                             12
+#define XCM_REG_CTX_RBC_ACCS                                                                                 0x1001800UL //Access:RW   DataWidth:0x10   // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - offset (in REGs (32b)) within LCID/LTID. The procedure to read context is: first define base address and offset; then read context with one of the following registers: CM_REGISTERS_AGG_CON_CTX.AGG_CON_CTX CM_REGISTERS_SM_CON_CTX.SM_CON_CTX CM_REGISTERS_AGG_TASK_CTX.AGG_TASK_CTX CM_REGISTERS_SM_TASK_CTX.SM_TASK_CTX
+#define XCM_REG_AGG_CON_CTX                                                                                  0x1001804UL //Access:RW   DataWidth:0x20   // Access is allowed only on idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The address base (LCID) and offset within LCID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to Aggregation Connection context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.
+#define XCM_REG_SM_CON_CTX                                                                                   0x1001808UL //Access:RW   DataWidth:0x20   // Access is allowed only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The address base (LCID) and offset within LCID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to STORM Connection context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.
+#define XCM_REG_XX_CBYP_TBL                                                                                  0x1001820UL //Access:R    DataWidth:0xf    // Xx Connection Bypass Table.
+#define XCM_REG_XX_CBYP_TBL_SIZE                                                                             8
+#define XCM_REG_XX_LCID_CAM                                                                                  0x1001900UL //Access:R    DataWidth:0xa    // Debug only. Read only access to LCID CAM in XX protection mechanism.
+#define XCM_REG_XX_LCID_CAM_SIZE_BB_K2                                                                       30
+#define XCM_REG_XX_LCID_CAM_SIZE_E5                                                                          64
+#define XCM_REG_XX_TBL                                                                                       0x1001a00UL //Access:R    DataWidth:0x18   // Indirect access to the XX table of the XX protection mechanism. The fields are: [0] - Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: PCM - [9:8]; M/T/U/X/YCM - [17:12]; Next pointer: PCM - [11:10]; M/T/U/X/YCM - [23:18];
+#define XCM_REG_XX_TBL_SIZE_BB_K2                                                                            30
+#define XCM_REG_XX_TBL_SIZE_E5                                                                               64
+#define XCM_REG_XX_DSCR_TBL                                                                                  0x1001b00UL //Access:RW   DataWidth:0x11   // Indirect access to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [13:9];PCM [14:9]; TCM [13:9]; UCM [13:9];XCM [10:9];YCM[13:9]); Next pointer (MCM [19:14]; PCM [16:15]; TCM[19:14]; UCM [19:14]; XCM [16:11]; YCM [19:14]); LTID (MCM [28:20]; PCM [25:17] - reserved; TCM[28:20]; UCM [28:20]; XCM [25:17] - reserved; YCM [28:20]). Task Domain Exist (MCM [29]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - reserved; YCM [29]). A free link list in the XX descriptor table should be build. This is done by writing the following values to all effective entries in the table:xx_descr_table[i].next_pointer = i+1 (i=0 - (xx_msg_up_bnd-2)); xx_descr_table[i].next_pointer= 0 (i=xx_msg_up_bnd-1). The value of i is between 0 to the configured (not default) value of (xx_msg_up_bnd-1). The not effective entries (those which succeed the last effective entry with index (xx_msg_up_bnd-1)) can be initialized to any value for initialization procedure simplicity seek.
+#define XCM_REG_XX_DSCR_TBL_SIZE                                                                             64
+#define XCM_REG_TM_CON_EVNT_ID_0_BB_K2                                                                       0x10004a4UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define XCM_REG_TM_CON_EVNT_ID_0_E5                                                                          0x1001c00UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define XCM_REG_TM_CON_EVNT_ID_1_BB_K2                                                                       0x10004a8UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define XCM_REG_TM_CON_EVNT_ID_1_E5                                                                          0x1001c04UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define XCM_REG_TM_CON_EVNT_ID_2_BB_K2                                                                       0x10004acUL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define XCM_REG_TM_CON_EVNT_ID_2_E5                                                                          0x1001c08UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define XCM_REG_TM_CON_EVNT_ID_3_BB_K2                                                                       0x10004b0UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define XCM_REG_TM_CON_EVNT_ID_3_E5                                                                          0x1001c0cUL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define XCM_REG_TM_CON_EVNT_ID_4_BB_K2                                                                       0x10004b4UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define XCM_REG_TM_CON_EVNT_ID_4_E5                                                                          0x1001c10UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define XCM_REG_TM_CON_EVNT_ID_5_BB_K2                                                                       0x10004b8UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define XCM_REG_TM_CON_EVNT_ID_5_E5                                                                          0x1001c14UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define XCM_REG_TM_CON_EVNT_ID_6_BB_K2                                                                       0x10004bcUL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define XCM_REG_TM_CON_EVNT_ID_6_E5                                                                          0x1001c18UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define XCM_REG_TM_CON_EVNT_ID_7_BB_K2                                                                       0x10004c0UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.:
+#define XCM_REG_TM_CON_EVNT_ID_7_E5                                                                          0x1001c1cUL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.:
+#define XCM_REG_TM_CON_EVNT_ID_8_E5                                                                          0x1001c20UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define XCM_REG_TM_CON_EVNT_ID_9_E5                                                                          0x1001c24UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define XCM_REG_TM_CON_EVNT_ID_10_E5                                                                         0x1001c28UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define XCM_REG_TM_CON_EVNT_ID_11_E5                                                                         0x1001c2cUL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define XCM_REG_TM_CON_EVNT_ID_12_E5                                                                         0x1001c30UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define XCM_REG_TM_CON_EVNT_ID_13_E5                                                                         0x1001c34UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define XCM_REG_TM_CON_EVNT_ID_14_E5                                                                         0x1001c38UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define XCM_REG_TM_CON_EVNT_ID_15_E5                                                                         0x1001c3cUL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.:
+#define XCM_REG_N_SM_CON_CTX_LD_0_BB_K2                                                                      0x100080cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define XCM_REG_N_SM_CON_CTX_LD_0_E5                                                                         0x1001c40UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define XCM_REG_N_SM_CON_CTX_LD_1_BB_K2                                                                      0x1000810UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define XCM_REG_N_SM_CON_CTX_LD_1_E5                                                                         0x1001c44UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define XCM_REG_N_SM_CON_CTX_LD_2_BB_K2                                                                      0x1000814UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define XCM_REG_N_SM_CON_CTX_LD_2_E5                                                                         0x1001c48UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define XCM_REG_N_SM_CON_CTX_LD_3_BB_K2                                                                      0x1000818UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define XCM_REG_N_SM_CON_CTX_LD_3_E5                                                                         0x1001c4cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define XCM_REG_N_SM_CON_CTX_LD_4_BB_K2                                                                      0x100081cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define XCM_REG_N_SM_CON_CTX_LD_4_E5                                                                         0x1001c50UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define XCM_REG_N_SM_CON_CTX_LD_5_BB_K2                                                                      0x1000820UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define XCM_REG_N_SM_CON_CTX_LD_5_E5                                                                         0x1001c54UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define XCM_REG_N_SM_CON_CTX_LD_6_BB_K2                                                                      0x1000824UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define XCM_REG_N_SM_CON_CTX_LD_6_E5                                                                         0x1001c58UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define XCM_REG_N_SM_CON_CTX_LD_7_BB_K2                                                                      0x1000828UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define XCM_REG_N_SM_CON_CTX_LD_7_E5                                                                         0x1001c5cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define XCM_REG_N_SM_CON_CTX_LD_8_E5                                                                         0x1001c60UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define XCM_REG_N_SM_CON_CTX_LD_9_E5                                                                         0x1001c64UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define XCM_REG_N_SM_CON_CTX_LD_10_E5                                                                        0x1001c68UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 10).
+#define XCM_REG_N_SM_CON_CTX_LD_11_E5                                                                        0x1001c6cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define XCM_REG_N_SM_CON_CTX_LD_12_E5                                                                        0x1001c70UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define XCM_REG_N_SM_CON_CTX_LD_13_E5                                                                        0x1001c74UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define XCM_REG_N_SM_CON_CTX_LD_14_E5                                                                        0x1001c78UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define XCM_REG_N_SM_CON_CTX_LD_15_E5                                                                        0x1001c7cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define XCM_REG_AGG_CON_CTX_SIZE_0_BB_K2                                                                     0x1000854UL //Access:RW   DataWidth:0x4    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less or 9.
+#define XCM_REG_AGG_CON_CTX_SIZE_0_E5                                                                        0x1001c80UL //Access:RW   DataWidth:0x4    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.
+#define XCM_REG_AGG_CON_CTX_SIZE_1_BB_K2                                                                     0x1000858UL //Access:RW   DataWidth:0x4    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.
+#define XCM_REG_AGG_CON_CTX_SIZE_1_E5                                                                        0x1001c84UL //Access:RW   DataWidth:0x4    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.
+#define XCM_REG_AGG_CON_CTX_SIZE_2_BB_K2                                                                     0x100085cUL //Access:RW   DataWidth:0x4    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.
+#define XCM_REG_AGG_CON_CTX_SIZE_2_E5                                                                        0x1001c88UL //Access:RW   DataWidth:0x4    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.
+#define XCM_REG_AGG_CON_CTX_SIZE_3_BB_K2                                                                     0x1000860UL //Access:RW   DataWidth:0x4    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.
+#define XCM_REG_AGG_CON_CTX_SIZE_3_E5                                                                        0x1001c8cUL //Access:RW   DataWidth:0x4    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.
+#define XCM_REG_AGG_CON_CTX_SIZE_4_BB_K2                                                                     0x1000864UL //Access:RW   DataWidth:0x4    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.
+#define XCM_REG_AGG_CON_CTX_SIZE_4_E5                                                                        0x1001c90UL //Access:RW   DataWidth:0x4    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.
+#define XCM_REG_AGG_CON_CTX_SIZE_5_BB_K2                                                                     0x1000868UL //Access:RW   DataWidth:0x4    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.
+#define XCM_REG_AGG_CON_CTX_SIZE_5_E5                                                                        0x1001c94UL //Access:RW   DataWidth:0x4    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.
+#define XCM_REG_AGG_CON_CTX_SIZE_6_BB_K2                                                                     0x100086cUL //Access:RW   DataWidth:0x4    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.
+#define XCM_REG_AGG_CON_CTX_SIZE_6_E5                                                                        0x1001c98UL //Access:RW   DataWidth:0x4    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.
+#define XCM_REG_AGG_CON_CTX_SIZE_7_BB_K2                                                                     0x1000870UL //Access:RW   DataWidth:0x4    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.
+#define XCM_REG_AGG_CON_CTX_SIZE_7_E5                                                                        0x1001c9cUL //Access:RW   DataWidth:0x4    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.
+#define XCM_REG_AGG_CON_CTX_SIZE_8_E5                                                                        0x1001ca0UL //Access:RW   DataWidth:0x4    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less or 9.
+#define XCM_REG_AGG_CON_CTX_SIZE_9_E5                                                                        0x1001ca4UL //Access:RW   DataWidth:0x4    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.
+#define XCM_REG_AGG_CON_CTX_SIZE_10_E5                                                                       0x1001ca8UL //Access:RW   DataWidth:0x4    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.
+#define XCM_REG_AGG_CON_CTX_SIZE_11_E5                                                                       0x1001cacUL //Access:RW   DataWidth:0x4    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.
+#define XCM_REG_AGG_CON_CTX_SIZE_12_E5                                                                       0x1001cb0UL //Access:RW   DataWidth:0x4    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.
+#define XCM_REG_AGG_CON_CTX_SIZE_13_E5                                                                       0x1001cb4UL //Access:RW   DataWidth:0x4    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.
+#define XCM_REG_AGG_CON_CTX_SIZE_14_E5                                                                       0x1001cb8UL //Access:RW   DataWidth:0x4    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.
+#define XCM_REG_AGG_CON_CTX_SIZE_15_E5                                                                       0x1001cbcUL //Access:RW   DataWidth:0x4    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.
+#define XCM_REG_QM_CON_BASE_EVNT_ID_0_BB_K2                                                                  0x1000404UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define XCM_REG_QM_CON_BASE_EVNT_ID_0_E5                                                                     0x1001cc0UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define XCM_REG_QM_CON_BASE_EVNT_ID_1_BB_K2                                                                  0x1000408UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define XCM_REG_QM_CON_BASE_EVNT_ID_1_E5                                                                     0x1001cc4UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define XCM_REG_QM_CON_BASE_EVNT_ID_2_BB_K2                                                                  0x100040cUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define XCM_REG_QM_CON_BASE_EVNT_ID_2_E5                                                                     0x1001cc8UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define XCM_REG_QM_CON_BASE_EVNT_ID_3_BB_K2                                                                  0x1000410UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define XCM_REG_QM_CON_BASE_EVNT_ID_3_E5                                                                     0x1001cccUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define XCM_REG_QM_CON_BASE_EVNT_ID_4_BB_K2                                                                  0x1000414UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define XCM_REG_QM_CON_BASE_EVNT_ID_4_E5                                                                     0x1001cd0UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define XCM_REG_QM_CON_BASE_EVNT_ID_5_BB_K2                                                                  0x1000418UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define XCM_REG_QM_CON_BASE_EVNT_ID_5_E5                                                                     0x1001cd4UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define XCM_REG_QM_CON_BASE_EVNT_ID_6_BB_K2                                                                  0x100041cUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define XCM_REG_QM_CON_BASE_EVNT_ID_6_E5                                                                     0x1001cd8UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define XCM_REG_QM_CON_BASE_EVNT_ID_7_BB_K2                                                                  0x1000420UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define XCM_REG_QM_CON_BASE_EVNT_ID_7_E5                                                                     0x1001cdcUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define XCM_REG_QM_CON_BASE_EVNT_ID_8_E5                                                                     0x1001ce0UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define XCM_REG_QM_CON_BASE_EVNT_ID_9_E5                                                                     0x1001ce4UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define XCM_REG_QM_CON_BASE_EVNT_ID_10_E5                                                                    0x1001ce8UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define XCM_REG_QM_CON_BASE_EVNT_ID_11_E5                                                                    0x1001cecUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define XCM_REG_QM_CON_BASE_EVNT_ID_12_E5                                                                    0x1001cf0UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define XCM_REG_QM_CON_BASE_EVNT_ID_13_E5                                                                    0x1001cf4UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define XCM_REG_QM_CON_BASE_EVNT_ID_14_E5                                                                    0x1001cf8UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define XCM_REG_QM_CON_BASE_EVNT_ID_15_E5                                                                    0x1001cfcUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_0_BB_K2                                                             0x1000424UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_0_E5                                                                0x1001d00UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_1_BB_K2                                                             0x1000428UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_1_E5                                                                0x1001d04UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_2_BB_K2                                                             0x100042cUL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_2_E5                                                                0x1001d08UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_3_BB_K2                                                             0x1000430UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_3_E5                                                                0x1001d0cUL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_4_BB_K2                                                             0x1000434UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_4_E5                                                                0x1001d10UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_5_BB_K2                                                             0x1000438UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_5_E5                                                                0x1001d14UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_6_BB_K2                                                             0x100043cUL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_6_E5                                                                0x1001d18UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_7_BB_K2                                                             0x1000440UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_7_E5                                                                0x1001d1cUL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_8_E5                                                                0x1001d20UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_9_E5                                                                0x1001d24UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_10_E5                                                               0x1001d28UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_11_E5                                                               0x1001d2cUL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_12_E5                                                               0x1001d30UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_13_E5                                                               0x1001d34UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_14_E5                                                               0x1001d38UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_15_E5                                                               0x1001d3cUL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define XCM_REG_QM_XXLOCK_CMD_0_BB_K2                                                                        0x1000464UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define XCM_REG_QM_XXLOCK_CMD_0_E5                                                                           0x1001d40UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define XCM_REG_QM_XXLOCK_CMD_1_BB_K2                                                                        0x1000468UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define XCM_REG_QM_XXLOCK_CMD_1_E5                                                                           0x1001d44UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define XCM_REG_QM_XXLOCK_CMD_2_BB_K2                                                                        0x100046cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define XCM_REG_QM_XXLOCK_CMD_2_E5                                                                           0x1001d48UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define XCM_REG_QM_XXLOCK_CMD_3_BB_K2                                                                        0x1000470UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define XCM_REG_QM_XXLOCK_CMD_3_E5                                                                           0x1001d4cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define XCM_REG_QM_XXLOCK_CMD_4_BB_K2                                                                        0x1000474UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define XCM_REG_QM_XXLOCK_CMD_4_E5                                                                           0x1001d50UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define XCM_REG_QM_XXLOCK_CMD_5_BB_K2                                                                        0x1000478UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define XCM_REG_QM_XXLOCK_CMD_5_E5                                                                           0x1001d54UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define XCM_REG_QM_XXLOCK_CMD_6_BB_K2                                                                        0x100047cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define XCM_REG_QM_XXLOCK_CMD_6_E5                                                                           0x1001d58UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define XCM_REG_QM_XXLOCK_CMD_7_BB_K2                                                                        0x1000480UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define XCM_REG_QM_XXLOCK_CMD_7_E5                                                                           0x1001d5cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define XCM_REG_QM_XXLOCK_CMD_8_E5                                                                           0x1001d60UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define XCM_REG_QM_XXLOCK_CMD_9_E5                                                                           0x1001d64UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define XCM_REG_QM_XXLOCK_CMD_10_E5                                                                          0x1001d68UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define XCM_REG_QM_XXLOCK_CMD_11_E5                                                                          0x1001d6cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define XCM_REG_QM_XXLOCK_CMD_12_E5                                                                          0x1001d70UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define XCM_REG_QM_XXLOCK_CMD_13_E5                                                                          0x1001d74UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define XCM_REG_QM_XXLOCK_CMD_14_E5                                                                          0x1001d78UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define XCM_REG_QM_XXLOCK_CMD_15_E5                                                                          0x1001d7cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define XCM_REG_QM_CON_USE_ST_FLG_0_BB_K2                                                                    0x1000484UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define XCM_REG_QM_CON_USE_ST_FLG_0_E5                                                                       0x1001d80UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define XCM_REG_QM_CON_USE_ST_FLG_1_BB_K2                                                                    0x1000488UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define XCM_REG_QM_CON_USE_ST_FLG_1_E5                                                                       0x1001d84UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define XCM_REG_QM_CON_USE_ST_FLG_2_BB_K2                                                                    0x100048cUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define XCM_REG_QM_CON_USE_ST_FLG_2_E5                                                                       0x1001d88UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define XCM_REG_QM_CON_USE_ST_FLG_3_BB_K2                                                                    0x1000490UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define XCM_REG_QM_CON_USE_ST_FLG_3_E5                                                                       0x1001d8cUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define XCM_REG_QM_CON_USE_ST_FLG_4_BB_K2                                                                    0x1000494UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define XCM_REG_QM_CON_USE_ST_FLG_4_E5                                                                       0x1001d90UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define XCM_REG_QM_CON_USE_ST_FLG_5_BB_K2                                                                    0x1000498UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define XCM_REG_QM_CON_USE_ST_FLG_5_E5                                                                       0x1001d94UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define XCM_REG_QM_CON_USE_ST_FLG_6_BB_K2                                                                    0x100049cUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define XCM_REG_QM_CON_USE_ST_FLG_6_E5                                                                       0x1001d98UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define XCM_REG_QM_CON_USE_ST_FLG_7_BB_K2                                                                    0x10004a0UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define XCM_REG_QM_CON_USE_ST_FLG_7_E5                                                                       0x1001d9cUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define XCM_REG_QM_CON_USE_ST_FLG_8_E5                                                                       0x1001da0UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define XCM_REG_QM_CON_USE_ST_FLG_9_E5                                                                       0x1001da4UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define XCM_REG_QM_CON_USE_ST_FLG_10_E5                                                                      0x1001da8UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define XCM_REG_QM_CON_USE_ST_FLG_11_E5                                                                      0x1001dacUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define XCM_REG_QM_CON_USE_ST_FLG_12_E5                                                                      0x1001db0UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define XCM_REG_QM_CON_USE_ST_FLG_13_E5                                                                      0x1001db4UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define XCM_REG_QM_CON_USE_ST_FLG_14_E5                                                                      0x1001db8UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define XCM_REG_QM_CON_USE_ST_FLG_15_E5                                                                      0x1001dbcUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define XCM_REG_QM_SM_CON_CTX_LDST_FLG_0_BB_K2                                                               0x1000444UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define XCM_REG_QM_SM_CON_CTX_LDST_FLG_0_E5                                                                  0x1001dc0UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define XCM_REG_QM_SM_CON_CTX_LDST_FLG_1_BB_K2                                                               0x1000448UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define XCM_REG_QM_SM_CON_CTX_LDST_FLG_1_E5                                                                  0x1001dc4UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define XCM_REG_QM_SM_CON_CTX_LDST_FLG_2_BB_K2                                                               0x100044cUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define XCM_REG_QM_SM_CON_CTX_LDST_FLG_2_E5                                                                  0x1001dc8UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define XCM_REG_QM_SM_CON_CTX_LDST_FLG_3_BB_K2                                                               0x1000450UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define XCM_REG_QM_SM_CON_CTX_LDST_FLG_3_E5                                                                  0x1001dccUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define XCM_REG_QM_SM_CON_CTX_LDST_FLG_4_BB_K2                                                               0x1000454UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define XCM_REG_QM_SM_CON_CTX_LDST_FLG_4_E5                                                                  0x1001dd0UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define XCM_REG_QM_SM_CON_CTX_LDST_FLG_5_BB_K2                                                               0x1000458UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define XCM_REG_QM_SM_CON_CTX_LDST_FLG_5_E5                                                                  0x1001dd4UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define XCM_REG_QM_SM_CON_CTX_LDST_FLG_6_BB_K2                                                               0x100045cUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define XCM_REG_QM_SM_CON_CTX_LDST_FLG_6_E5                                                                  0x1001dd8UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define XCM_REG_QM_SM_CON_CTX_LDST_FLG_7_BB_K2                                                               0x1000460UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define XCM_REG_QM_SM_CON_CTX_LDST_FLG_7_E5                                                                  0x1001ddcUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define XCM_REG_QM_SM_CON_CTX_LDST_FLG_8_E5                                                                  0x1001de0UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define XCM_REG_QM_SM_CON_CTX_LDST_FLG_9_E5                                                                  0x1001de4UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define XCM_REG_QM_SM_CON_CTX_LDST_FLG_10_E5                                                                 0x1001de8UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define XCM_REG_QM_SM_CON_CTX_LDST_FLG_11_E5                                                                 0x1001decUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define XCM_REG_QM_SM_CON_CTX_LDST_FLG_12_E5                                                                 0x1001df0UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define XCM_REG_QM_SM_CON_CTX_LDST_FLG_13_E5                                                                 0x1001df4UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define XCM_REG_QM_SM_CON_CTX_LDST_FLG_14_E5                                                                 0x1001df8UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define XCM_REG_QM_SM_CON_CTX_LDST_FLG_15_E5                                                                 0x1001dfcUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define XCM_REG_EN_QINDEX_20_MERGE_0_E5                                                                      0x1001e00UL //Access:RW   DataWidth:0x1    // Enables QIndex 2 and 0 merge in XCM per connection type.
+#define XCM_REG_EN_QINDEX_20_MERGE_1_E5                                                                      0x1001e04UL //Access:RW   DataWidth:0x1    // Enables QIndex 2 and 0 merge in XCM per connection type.
+#define XCM_REG_EN_QINDEX_20_MERGE_2_E5                                                                      0x1001e08UL //Access:RW   DataWidth:0x1    // Enables QIndex 2 and 0 merge in XCM per connection type.
+#define XCM_REG_EN_QINDEX_20_MERGE_3_E5                                                                      0x1001e0cUL //Access:RW   DataWidth:0x1    // Enables QIndex 2 and 0 merge in XCM per connection type.
+#define XCM_REG_EN_QINDEX_20_MERGE_4_E5                                                                      0x1001e10UL //Access:RW   DataWidth:0x1    // Enables QIndex 2 and 0 merge in XCM per connection type.
+#define XCM_REG_EN_QINDEX_20_MERGE_5_E5                                                                      0x1001e14UL //Access:RW   DataWidth:0x1    // Enables QIndex 2 and 0 merge in XCM per connection type.
+#define XCM_REG_EN_QINDEX_20_MERGE_6_E5                                                                      0x1001e18UL //Access:RW   DataWidth:0x1    // Enables QIndex 2 and 0 merge in XCM per connection type.
+#define XCM_REG_EN_QINDEX_20_MERGE_7_E5                                                                      0x1001e1cUL //Access:RW   DataWidth:0x1    // Enables QIndex 2 and 0 merge in XCM per connection type.
+#define XCM_REG_EN_QINDEX_20_MERGE_8_E5                                                                      0x1001e20UL //Access:RW   DataWidth:0x1    // Enables QIndex 2 and 0 merge in XCM per connection type.
+#define XCM_REG_EN_QINDEX_20_MERGE_9_E5                                                                      0x1001e24UL //Access:RW   DataWidth:0x1    // Enables QIndex 2 and 0 merge in XCM per connection type.
+#define XCM_REG_EN_QINDEX_20_MERGE_10_E5                                                                     0x1001e28UL //Access:RW   DataWidth:0x1    // Enables QIndex 2 and 0 merge in XCM per connection type.
+#define XCM_REG_EN_QINDEX_20_MERGE_11_E5                                                                     0x1001e2cUL //Access:RW   DataWidth:0x1    // Enables QIndex 2 and 0 merge in XCM per connection type.
+#define XCM_REG_EN_QINDEX_20_MERGE_12_E5                                                                     0x1001e30UL //Access:RW   DataWidth:0x1    // Enables QIndex 2 and 0 merge in XCM per connection type.
+#define XCM_REG_EN_QINDEX_20_MERGE_13_E5                                                                     0x1001e34UL //Access:RW   DataWidth:0x1    // Enables QIndex 2 and 0 merge in XCM per connection type.
+#define XCM_REG_EN_QINDEX_20_MERGE_14_E5                                                                     0x1001e38UL //Access:RW   DataWidth:0x1    // Enables QIndex 2 and 0 merge in XCM per connection type.
+#define XCM_REG_EN_QINDEX_20_MERGE_15_E5                                                                     0x1001e3cUL //Access:RW   DataWidth:0x1    // Enables QIndex 2 and 0 merge in XCM per connection type.
+#define XCM_REG_MSDM_WEIGHT_BB_K2                                                                            0x1000620UL //Access:RW   DataWidth:0x3    // The weight of the MSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define XCM_REG_MSDM_WEIGHT_E5                                                                               0x1001e40UL //Access:RW   DataWidth:0x3    // The weight of the input MSDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define XCM_REG_MSDM_FRWRD_MODE_BB_K2                                                                        0x100065cUL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define XCM_REG_MSDM_FRWRD_MODE_E5                                                                           0x1001e44UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define XCM_REG_MSDM_LENGTH_MIS_BB_K2                                                                        0x1000aa8UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at MSDM interface.
+#define XCM_REG_MSDM_LENGTH_MIS_E5                                                                           0x1001e48UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at MSDM interface.
+#define XCM_REG_MSDM_MSG_CNTR_BB_K2                                                                          0x1000accUL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input MSDM.
+#define XCM_REG_MSDM_MSG_CNTR_E5                                                                             0x1001e4cUL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input MSDM.
+#define XCM_REG_IS_MSDM_FILL_LVL_BB_K2                                                                       0x1000b10UL //Access:R    DataWidth:0x4    // Number of QREGs (128b) of data in MSDM Input Stage.
+#define XCM_REG_IS_MSDM_FILL_LVL_E5                                                                          0x1001e50UL //Access:R    DataWidth:0x4    // Number of QREGs (128b) of data in MSDM Input Stage.
+#define XCM_REG_IS_FOC_MSDM_NXT_INF_UNIT_BB_K2                                                               0x1000ba0UL //Access:R    DataWidth:0x6    // Debug read from MSDM Input stage buffer: number of reads to next information unit.
+#define XCM_REG_IS_FOC_MSDM_NXT_INF_UNIT_E5                                                                  0x1001e54UL //Access:R    DataWidth:0x6    // Debug read from MSDM Input stage buffer: number of reads to next information unit.
+#define XCM_REG_IS_FOC_MSDM_E5                                                                               0x1001e80UL //Access:R    DataWidth:0x20   // Debug read from MSDM Input stage buffer with 32-bits granularity. Read only.
+#define XCM_REG_IS_FOC_MSDM_SIZE                                                                             32
+#define XCM_REG_YSEM_WEIGHT_BB_K2                                                                            0x1000610UL //Access:RW   DataWidth:0x3    // The weight of the input Ysem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define XCM_REG_YSEM_WEIGHT_E5                                                                               0x1001f00UL //Access:RW   DataWidth:0x3    // The weight of the input Ysem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define XCM_REG_YSEM_FRWRD_MODE_BB_K2                                                                        0x1000674UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define XCM_REG_YSEM_FRWRD_MODE_E5                                                                           0x1001f04UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define XCM_REG_YSEM_MSG_CNTR_BB_K2                                                                          0x1000ae4UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at input Ysem.
+#define XCM_REG_YSEM_MSG_CNTR_E5                                                                             0x1001f08UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at input Ysem.
+#define XCM_REG_IS_YSEM_FILL_LVL_BB_K2                                                                       0x1000b28UL //Access:R    DataWidth:0x4    // Number of QREGs (128b) of data in YSEM Input Stage.
+#define XCM_REG_IS_YSEM_FILL_LVL_E5                                                                          0x1001f0cUL //Access:R    DataWidth:0x4    // Number of QREGs (128b) for TCM, XCM or 2 QREGs (256b) for MCM of data in YSEM Input Stage.
+#define XCM_REG_IS_FOC_YSEM_NXT_INF_UNIT_BB_K2                                                               0x1000b94UL //Access:R    DataWidth:0x6    // Debug read from YSEM Input stage buffer: number of reads to next information unit.
+#define XCM_REG_IS_FOC_YSEM_NXT_INF_UNIT_E5                                                                  0x1001f10UL //Access:R    DataWidth:0x6    // Debug read from YSEM Input stage buffer: number of reads to next information unit.
+#define XCM_REG_IS_FOC_YSEM_BB_K2                                                                            0x1001400UL //Access:R    DataWidth:0x20   // Debug read from YSEM Input stage buffer with 32-bits granularity. Read only.
+#define XCM_REG_IS_FOC_YSEM_E5                                                                               0x1001f80UL //Access:R    DataWidth:0x20   // Debug read from YSEM Input stage buffer with 32-bits granularity. Read only.
+#define XCM_REG_IS_FOC_YSEM_SIZE                                                                             32
+#define XCM_REG_XX_MSG_RAM                                                                                   0x1002000UL //Access:R    DataWidth:0x20   // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
+#define XCM_REG_XX_MSG_RAM_SIZE                                                                              1024
+#define XCM_REG_QM_ACT_ST_CNT                                                                                0x1004000UL //Access:RW   DataWidth:0x20   // At write the following fields are used to implement a QM active state counter update: [19:0]: PQ counter update value. [28:20] PQ number. [29:29] Reserved. [31:30] Command type: 0 - SET; 1 - DEC; 2 - INC; The address provided is don't care. At read the address provided defines the PQ number to be accessed for read.
+#define XCM_REG_QM_ACT_ST_CNT_SIZE_BB                                                                        448
+#define XCM_REG_QM_ACT_ST_CNT_SIZE_K2_E5                                                                     512
+#define YCM_REG_INIT                                                                                         0x1080000UL //Access:RW   DataWidth:0x1    // Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
+#define YCM_REG_DBG_SELECT                                                                                   0x1080040UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define YCM_REG_DBG_DWORD_ENABLE                                                                             0x1080044UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define YCM_REG_DBG_SHIFT                                                                                    0x1080048UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define YCM_REG_DBG_FORCE_VALID                                                                              0x108004cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define YCM_REG_DBG_FORCE_FRAME                                                                              0x1080050UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define YCM_REG_DBG_OUT_DATA                                                                                 0x1080060UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define YCM_REG_DBG_OUT_DATA_SIZE                                                                            8
+#define YCM_REG_DBG_OUT_VALID                                                                                0x1080080UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define YCM_REG_DBG_OUT_FRAME                                                                                0x1080084UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define YCM_REG_AFFINITY_TYPE_0_E5                                                                           0x1080088UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define YCM_REG_AFFINITY_TYPE_1_E5                                                                           0x108008cUL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define YCM_REG_AFFINITY_TYPE_2_E5                                                                           0x1080090UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define YCM_REG_AFFINITY_TYPE_3_E5                                                                           0x1080094UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define YCM_REG_AFFINITY_TYPE_4_E5                                                                           0x1080098UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define YCM_REG_AFFINITY_TYPE_5_E5                                                                           0x108009cUL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define YCM_REG_AFFINITY_TYPE_6_E5                                                                           0x10800a0UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define YCM_REG_AFFINITY_TYPE_7_E5                                                                           0x10800a4UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define YCM_REG_AFFINITY_TYPE_8_E5                                                                           0x10800a8UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define YCM_REG_AFFINITY_TYPE_9_E5                                                                           0x10800acUL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define YCM_REG_AFFINITY_TYPE_10_E5                                                                          0x10800b0UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define YCM_REG_AFFINITY_TYPE_11_E5                                                                          0x10800b4UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define YCM_REG_AFFINITY_TYPE_12_E5                                                                          0x10800b8UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define YCM_REG_AFFINITY_TYPE_13_E5                                                                          0x10800bcUL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define YCM_REG_AFFINITY_TYPE_14_E5                                                                          0x10800c0UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define YCM_REG_AFFINITY_TYPE_15_E5                                                                          0x10800c4UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define YCM_REG_EXCLUSIVE_FLG_0_E5                                                                           0x10800c8UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define YCM_REG_EXCLUSIVE_FLG_1_E5                                                                           0x10800ccUL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define YCM_REG_EXCLUSIVE_FLG_2_E5                                                                           0x10800d0UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define YCM_REG_EXCLUSIVE_FLG_3_E5                                                                           0x10800d4UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define YCM_REG_EXCLUSIVE_FLG_4_E5                                                                           0x10800d8UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define YCM_REG_EXCLUSIVE_FLG_5_E5                                                                           0x10800dcUL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define YCM_REG_EXCLUSIVE_FLG_6_E5                                                                           0x10800e0UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define YCM_REG_EXCLUSIVE_FLG_7_E5                                                                           0x10800e4UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define YCM_REG_EXCLUSIVE_FLG_8_E5                                                                           0x10800e8UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define YCM_REG_EXCLUSIVE_FLG_9_E5                                                                           0x10800ecUL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define YCM_REG_EXCLUSIVE_FLG_10_E5                                                                          0x10800f0UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define YCM_REG_EXCLUSIVE_FLG_11_E5                                                                          0x10800f4UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define YCM_REG_EXCLUSIVE_FLG_12_E5                                                                          0x10800f8UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define YCM_REG_EXCLUSIVE_FLG_13_E5                                                                          0x10800fcUL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define YCM_REG_EXCLUSIVE_FLG_14_E5                                                                          0x1080100UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define YCM_REG_EXCLUSIVE_FLG_15_E5                                                                          0x1080104UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define YCM_REG_AGG_CON_CF0_Q_BB_K2                                                                          0x1080914UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define YCM_REG_AGG_CON_CF0_Q_E5                                                                             0x1080108UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define YCM_REG_AGG_CON_CF1_Q_BB_K2                                                                          0x1080918UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define YCM_REG_AGG_CON_CF1_Q_E5                                                                             0x108010cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define YCM_REG_AGG_CON_CF2_Q_BB_K2                                                                          0x108091cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define YCM_REG_AGG_CON_CF2_Q_E5                                                                             0x1080110UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define YCM_REG_INT_STS_0                                                                                    0x1080180UL //Access:R    DataWidth:0x11   // Multi Field Register.
+  #define YCM_REG_INT_STS_0_ADDRESS_ERROR                                                                    (0x1<<0) // Signals an unknown address to the rf module.
+  #define YCM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                              0
+  #define YCM_REG_INT_STS_0_IS_STORM_OVFL_ERR                                                                (0x1<<1) // Write to full STORM input buffer.
+  #define YCM_REG_INT_STS_0_IS_STORM_OVFL_ERR_SHIFT                                                          1
+  #define YCM_REG_INT_STS_0_IS_STORM_UNDER_ERR                                                               (0x1<<2) // Read from empty  STORM input buffer.
+  #define YCM_REG_INT_STS_0_IS_STORM_UNDER_ERR_SHIFT                                                         2
+  #define YCM_REG_INT_STS_0_IS_MSDM_OVFL_ERR                                                                 (0x1<<3) // Write to full MSDM input buffer.
+  #define YCM_REG_INT_STS_0_IS_MSDM_OVFL_ERR_SHIFT                                                           3
+  #define YCM_REG_INT_STS_0_IS_MSDM_UNDER_ERR                                                                (0x1<<4) // Read from empty MSDM input buffer.
+  #define YCM_REG_INT_STS_0_IS_MSDM_UNDER_ERR_SHIFT                                                          4
+  #define YCM_REG_INT_STS_0_IS_YSDM_OVFL_ERR                                                                 (0x1<<5) // Write to full YSDM input buffer.
+  #define YCM_REG_INT_STS_0_IS_YSDM_OVFL_ERR_SHIFT                                                           5
+  #define YCM_REG_INT_STS_0_IS_YSDM_UNDER_ERR                                                                (0x1<<6) // Read from empty  YSDM input buffer.
+  #define YCM_REG_INT_STS_0_IS_YSDM_UNDER_ERR_SHIFT                                                          6
+  #define YCM_REG_INT_STS_0_IS_XYLD_OVFL_ERR                                                                 (0x1<<7) // Write to full XYLD input buffer.
+  #define YCM_REG_INT_STS_0_IS_XYLD_OVFL_ERR_SHIFT                                                           7
+  #define YCM_REG_INT_STS_0_IS_XYLD_UNDER_ERR                                                                (0x1<<8) // Read from empty XYLD input buffer.
+  #define YCM_REG_INT_STS_0_IS_XYLD_UNDER_ERR_SHIFT                                                          8
+  #define YCM_REG_INT_STS_0_IS_MSEM_OVFL_ERR                                                                 (0x1<<9) // Write to full Msem input buffer.
+  #define YCM_REG_INT_STS_0_IS_MSEM_OVFL_ERR_SHIFT                                                           9
+  #define YCM_REG_INT_STS_0_IS_MSEM_UNDER_ERR                                                                (0x1<<10) // Read from empty  Msem input buffer.
+  #define YCM_REG_INT_STS_0_IS_MSEM_UNDER_ERR_SHIFT                                                          10
+  #define YCM_REG_INT_STS_0_IS_USEM_OVFL_ERR                                                                 (0x1<<11) // Write to full Usem input buffer.
+  #define YCM_REG_INT_STS_0_IS_USEM_OVFL_ERR_SHIFT                                                           11
+  #define YCM_REG_INT_STS_0_IS_USEM_UNDER_ERR                                                                (0x1<<12) // Read from empty Usem input buffer.
+  #define YCM_REG_INT_STS_0_IS_USEM_UNDER_ERR_SHIFT                                                          12
+  #define YCM_REG_INT_STS_0_EXT_LD_UNDER_ERR_E5                                                              (0x1<<13) // Read from empty External read buffer.
+  #define YCM_REG_INT_STS_0_EXT_LD_UNDER_ERR_E5_SHIFT                                                        13
+  #define YCM_REG_INT_STS_0_EXT_LD_OVFL_ERR_E5                                                               (0x1<<14) // Write to fully External read buffer.
+  #define YCM_REG_INT_STS_0_EXT_LD_OVFL_ERR_E5_SHIFT                                                         14
+  #define YCM_REG_INT_STS_0_AFFINITY_TYPE_NO_CON_E5                                                          (0x1<<15) // Affinity type = 2 (connection based) but connection doesn't exist.
+  #define YCM_REG_INT_STS_0_AFFINITY_TYPE_NO_CON_E5_SHIFT                                                    15
+  #define YCM_REG_INT_STS_0_AFFINITY_TYPE_NO_TASK_E5                                                         (0x1<<16) // Affinity type = 3 (task based) but task doesn't exist.
+  #define YCM_REG_INT_STS_0_AFFINITY_TYPE_NO_TASK_E5_SHIFT                                                   16
+#define YCM_REG_INT_MASK_0                                                                                   0x1080184UL //Access:RW   DataWidth:0x11   // Multi Field Register.
+  #define YCM_REG_INT_MASK_0_ADDRESS_ERROR                                                                   (0x1<<0) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.ADDRESS_ERROR .
+  #define YCM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                             0
+  #define YCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR                                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_STORM_OVFL_ERR .
+  #define YCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR_SHIFT                                                         1
+  #define YCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR                                                              (0x1<<2) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_STORM_UNDER_ERR .
+  #define YCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR_SHIFT                                                        2
+  #define YCM_REG_INT_MASK_0_IS_MSDM_OVFL_ERR                                                                (0x1<<3) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_MSDM_OVFL_ERR .
+  #define YCM_REG_INT_MASK_0_IS_MSDM_OVFL_ERR_SHIFT                                                          3
+  #define YCM_REG_INT_MASK_0_IS_MSDM_UNDER_ERR                                                               (0x1<<4) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_MSDM_UNDER_ERR .
+  #define YCM_REG_INT_MASK_0_IS_MSDM_UNDER_ERR_SHIFT                                                         4
+  #define YCM_REG_INT_MASK_0_IS_YSDM_OVFL_ERR                                                                (0x1<<5) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_YSDM_OVFL_ERR .
+  #define YCM_REG_INT_MASK_0_IS_YSDM_OVFL_ERR_SHIFT                                                          5
+  #define YCM_REG_INT_MASK_0_IS_YSDM_UNDER_ERR                                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_YSDM_UNDER_ERR .
+  #define YCM_REG_INT_MASK_0_IS_YSDM_UNDER_ERR_SHIFT                                                         6
+  #define YCM_REG_INT_MASK_0_IS_XYLD_OVFL_ERR                                                                (0x1<<7) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_XYLD_OVFL_ERR .
+  #define YCM_REG_INT_MASK_0_IS_XYLD_OVFL_ERR_SHIFT                                                          7
+  #define YCM_REG_INT_MASK_0_IS_XYLD_UNDER_ERR                                                               (0x1<<8) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_XYLD_UNDER_ERR .
+  #define YCM_REG_INT_MASK_0_IS_XYLD_UNDER_ERR_SHIFT                                                         8
+  #define YCM_REG_INT_MASK_0_IS_MSEM_OVFL_ERR                                                                (0x1<<9) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_MSEM_OVFL_ERR .
+  #define YCM_REG_INT_MASK_0_IS_MSEM_OVFL_ERR_SHIFT                                                          9
+  #define YCM_REG_INT_MASK_0_IS_MSEM_UNDER_ERR                                                               (0x1<<10) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_MSEM_UNDER_ERR .
+  #define YCM_REG_INT_MASK_0_IS_MSEM_UNDER_ERR_SHIFT                                                         10
+  #define YCM_REG_INT_MASK_0_IS_USEM_OVFL_ERR                                                                (0x1<<11) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_USEM_OVFL_ERR .
+  #define YCM_REG_INT_MASK_0_IS_USEM_OVFL_ERR_SHIFT                                                          11
+  #define YCM_REG_INT_MASK_0_IS_USEM_UNDER_ERR                                                               (0x1<<12) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_USEM_UNDER_ERR .
+  #define YCM_REG_INT_MASK_0_IS_USEM_UNDER_ERR_SHIFT                                                         12
+  #define YCM_REG_INT_MASK_0_EXT_LD_UNDER_ERR_E5                                                             (0x1<<13) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.EXT_LD_UNDER_ERR .
+  #define YCM_REG_INT_MASK_0_EXT_LD_UNDER_ERR_E5_SHIFT                                                       13
+  #define YCM_REG_INT_MASK_0_EXT_LD_OVFL_ERR_E5                                                              (0x1<<14) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.EXT_LD_OVFL_ERR .
+  #define YCM_REG_INT_MASK_0_EXT_LD_OVFL_ERR_E5_SHIFT                                                        14
+  #define YCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_CON_E5                                                         (0x1<<15) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.AFFINITY_TYPE_NO_CON .
+  #define YCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_CON_E5_SHIFT                                                   15
+  #define YCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_TASK_E5                                                        (0x1<<16) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.AFFINITY_TYPE_NO_TASK .
+  #define YCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_TASK_E5_SHIFT                                                  16
+#define YCM_REG_INT_STS_WR_0                                                                                 0x1080188UL //Access:WR   DataWidth:0x11   // Multi Field Register.
+  #define YCM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define YCM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                           0
+  #define YCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR                                                             (0x1<<1) // Write to full STORM input buffer.
+  #define YCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR_SHIFT                                                       1
+  #define YCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR                                                            (0x1<<2) // Read from empty  STORM input buffer.
+  #define YCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR_SHIFT                                                      2
+  #define YCM_REG_INT_STS_WR_0_IS_MSDM_OVFL_ERR                                                              (0x1<<3) // Write to full MSDM input buffer.
+  #define YCM_REG_INT_STS_WR_0_IS_MSDM_OVFL_ERR_SHIFT                                                        3
+  #define YCM_REG_INT_STS_WR_0_IS_MSDM_UNDER_ERR                                                             (0x1<<4) // Read from empty MSDM input buffer.
+  #define YCM_REG_INT_STS_WR_0_IS_MSDM_UNDER_ERR_SHIFT                                                       4
+  #define YCM_REG_INT_STS_WR_0_IS_YSDM_OVFL_ERR                                                              (0x1<<5) // Write to full YSDM input buffer.
+  #define YCM_REG_INT_STS_WR_0_IS_YSDM_OVFL_ERR_SHIFT                                                        5
+  #define YCM_REG_INT_STS_WR_0_IS_YSDM_UNDER_ERR                                                             (0x1<<6) // Read from empty  YSDM input buffer.
+  #define YCM_REG_INT_STS_WR_0_IS_YSDM_UNDER_ERR_SHIFT                                                       6
+  #define YCM_REG_INT_STS_WR_0_IS_XYLD_OVFL_ERR                                                              (0x1<<7) // Write to full XYLD input buffer.
+  #define YCM_REG_INT_STS_WR_0_IS_XYLD_OVFL_ERR_SHIFT                                                        7
+  #define YCM_REG_INT_STS_WR_0_IS_XYLD_UNDER_ERR                                                             (0x1<<8) // Read from empty XYLD input buffer.
+  #define YCM_REG_INT_STS_WR_0_IS_XYLD_UNDER_ERR_SHIFT                                                       8
+  #define YCM_REG_INT_STS_WR_0_IS_MSEM_OVFL_ERR                                                              (0x1<<9) // Write to full Msem input buffer.
+  #define YCM_REG_INT_STS_WR_0_IS_MSEM_OVFL_ERR_SHIFT                                                        9
+  #define YCM_REG_INT_STS_WR_0_IS_MSEM_UNDER_ERR                                                             (0x1<<10) // Read from empty  Msem input buffer.
+  #define YCM_REG_INT_STS_WR_0_IS_MSEM_UNDER_ERR_SHIFT                                                       10
+  #define YCM_REG_INT_STS_WR_0_IS_USEM_OVFL_ERR                                                              (0x1<<11) // Write to full Usem input buffer.
+  #define YCM_REG_INT_STS_WR_0_IS_USEM_OVFL_ERR_SHIFT                                                        11
+  #define YCM_REG_INT_STS_WR_0_IS_USEM_UNDER_ERR                                                             (0x1<<12) // Read from empty Usem input buffer.
+  #define YCM_REG_INT_STS_WR_0_IS_USEM_UNDER_ERR_SHIFT                                                       12
+  #define YCM_REG_INT_STS_WR_0_EXT_LD_UNDER_ERR_E5                                                           (0x1<<13) // Read from empty External read buffer.
+  #define YCM_REG_INT_STS_WR_0_EXT_LD_UNDER_ERR_E5_SHIFT                                                     13
+  #define YCM_REG_INT_STS_WR_0_EXT_LD_OVFL_ERR_E5                                                            (0x1<<14) // Write to fully External read buffer.
+  #define YCM_REG_INT_STS_WR_0_EXT_LD_OVFL_ERR_E5_SHIFT                                                      14
+  #define YCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_CON_E5                                                       (0x1<<15) // Affinity type = 2 (connection based) but connection doesn't exist.
+  #define YCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_CON_E5_SHIFT                                                 15
+  #define YCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_TASK_E5                                                      (0x1<<16) // Affinity type = 3 (task based) but task doesn't exist.
+  #define YCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_TASK_E5_SHIFT                                                16
+#define YCM_REG_INT_STS_CLR_0                                                                                0x108018cUL //Access:RC   DataWidth:0x11   // Multi Field Register.
+  #define YCM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define YCM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                          0
+  #define YCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR                                                            (0x1<<1) // Write to full STORM input buffer.
+  #define YCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR_SHIFT                                                      1
+  #define YCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR                                                           (0x1<<2) // Read from empty  STORM input buffer.
+  #define YCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR_SHIFT                                                     2
+  #define YCM_REG_INT_STS_CLR_0_IS_MSDM_OVFL_ERR                                                             (0x1<<3) // Write to full MSDM input buffer.
+  #define YCM_REG_INT_STS_CLR_0_IS_MSDM_OVFL_ERR_SHIFT                                                       3
+  #define YCM_REG_INT_STS_CLR_0_IS_MSDM_UNDER_ERR                                                            (0x1<<4) // Read from empty MSDM input buffer.
+  #define YCM_REG_INT_STS_CLR_0_IS_MSDM_UNDER_ERR_SHIFT                                                      4
+  #define YCM_REG_INT_STS_CLR_0_IS_YSDM_OVFL_ERR                                                             (0x1<<5) // Write to full YSDM input buffer.
+  #define YCM_REG_INT_STS_CLR_0_IS_YSDM_OVFL_ERR_SHIFT                                                       5
+  #define YCM_REG_INT_STS_CLR_0_IS_YSDM_UNDER_ERR                                                            (0x1<<6) // Read from empty  YSDM input buffer.
+  #define YCM_REG_INT_STS_CLR_0_IS_YSDM_UNDER_ERR_SHIFT                                                      6
+  #define YCM_REG_INT_STS_CLR_0_IS_XYLD_OVFL_ERR                                                             (0x1<<7) // Write to full XYLD input buffer.
+  #define YCM_REG_INT_STS_CLR_0_IS_XYLD_OVFL_ERR_SHIFT                                                       7
+  #define YCM_REG_INT_STS_CLR_0_IS_XYLD_UNDER_ERR                                                            (0x1<<8) // Read from empty XYLD input buffer.
+  #define YCM_REG_INT_STS_CLR_0_IS_XYLD_UNDER_ERR_SHIFT                                                      8
+  #define YCM_REG_INT_STS_CLR_0_IS_MSEM_OVFL_ERR                                                             (0x1<<9) // Write to full Msem input buffer.
+  #define YCM_REG_INT_STS_CLR_0_IS_MSEM_OVFL_ERR_SHIFT                                                       9
+  #define YCM_REG_INT_STS_CLR_0_IS_MSEM_UNDER_ERR                                                            (0x1<<10) // Read from empty  Msem input buffer.
+  #define YCM_REG_INT_STS_CLR_0_IS_MSEM_UNDER_ERR_SHIFT                                                      10
+  #define YCM_REG_INT_STS_CLR_0_IS_USEM_OVFL_ERR                                                             (0x1<<11) // Write to full Usem input buffer.
+  #define YCM_REG_INT_STS_CLR_0_IS_USEM_OVFL_ERR_SHIFT                                                       11
+  #define YCM_REG_INT_STS_CLR_0_IS_USEM_UNDER_ERR                                                            (0x1<<12) // Read from empty Usem input buffer.
+  #define YCM_REG_INT_STS_CLR_0_IS_USEM_UNDER_ERR_SHIFT                                                      12
+  #define YCM_REG_INT_STS_CLR_0_EXT_LD_UNDER_ERR_E5                                                          (0x1<<13) // Read from empty External read buffer.
+  #define YCM_REG_INT_STS_CLR_0_EXT_LD_UNDER_ERR_E5_SHIFT                                                    13
+  #define YCM_REG_INT_STS_CLR_0_EXT_LD_OVFL_ERR_E5                                                           (0x1<<14) // Write to fully External read buffer.
+  #define YCM_REG_INT_STS_CLR_0_EXT_LD_OVFL_ERR_E5_SHIFT                                                     14
+  #define YCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_CON_E5                                                      (0x1<<15) // Affinity type = 2 (connection based) but connection doesn't exist.
+  #define YCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_CON_E5_SHIFT                                                15
+  #define YCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_TASK_E5                                                     (0x1<<16) // Affinity type = 3 (task based) but task doesn't exist.
+  #define YCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_TASK_E5_SHIFT                                               16
+#define YCM_REG_INT_STS_1                                                                                    0x1080190UL //Access:R    DataWidth:0x17   // Multi Field Register.
+  #define YCM_REG_INT_STS_1_IS_PBF_OVFL_ERR                                                                  (0x1<<0) // Write to full Pbf input buffer.
+  #define YCM_REG_INT_STS_1_IS_PBF_OVFL_ERR_SHIFT                                                            0
+  #define YCM_REG_INT_STS_1_IS_PBF_UNDER_ERR                                                                 (0x1<<1) // Read from empty Pbf input buffer.
+  #define YCM_REG_INT_STS_1_IS_PBF_UNDER_ERR_SHIFT                                                           1
+  #define YCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR                                                                 (0x1<<2) // Write to full QM input buffer.
+  #define YCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR_SHIFT                                                           2
+  #define YCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR                                                                (0x1<<3) // Read from empty QM input buffer.
+  #define YCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR_SHIFT                                                          3
+  #define YCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR                                                                 (0x1<<4) // Write to full QM input buffer.
+  #define YCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR_SHIFT                                                           4
+  #define YCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR                                                                (0x1<<5) // Read from empty QM input buffer.
+  #define YCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR_SHIFT                                                          5
+  #define YCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0                                                                 (0x1<<6) // Write to full GRC input buffer bits [31:0].
+  #define YCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0_SHIFT                                                           6
+  #define YCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0                                                                (0x1<<7) // Read from empty  GRC input buffer bits [31:0].
+  #define YCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0_SHIFT                                                          7
+  #define YCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1                                                                 (0x1<<8) // Write to full GRC input buffer bits [63:32].
+  #define YCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1_SHIFT                                                           8
+  #define YCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1                                                                (0x1<<9) // Read from empty  GRC input buffer bits [63:32].
+  #define YCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1_SHIFT                                                          9
+  #define YCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2                                                                 (0x1<<10) // Write to full GRC input buffer bits [95:64].
+  #define YCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2_SHIFT                                                           10
+  #define YCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2                                                                (0x1<<11) // Read from empty  GRC input buffer bits [95:64].
+  #define YCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2_SHIFT                                                          11
+  #define YCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3                                                                 (0x1<<12) // Write to full GRC input buffer bits [127:96].
+  #define YCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3_SHIFT                                                           12
+  #define YCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3                                                                (0x1<<13) // Read from empty  GRC input buffer bits [127:96].
+  #define YCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3_SHIFT                                                          13
+  #define YCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL                                                                 (0x1<<14) // In-process Table overflow.
+  #define YCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL_SHIFT                                                           14
+  #define YCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL                                                             (0x1<<15) // Message Processor Storm Connection Data buffer overflow.
+  #define YCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL_SHIFT                                                       15
+  #define YCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL                                                              (0x1<<16) // Message Processor Storm Connection Command buffer overflow.
+  #define YCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL_SHIFT                                                        16
+  #define YCM_REG_INT_STS_1_AGG_TASK_DATA_BUF_OVFL                                                           (0x1<<17) // Message Processor Aggregation Task Data buffer overflow.
+  #define YCM_REG_INT_STS_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                                     17
+  #define YCM_REG_INT_STS_1_AGG_TASK_CMD_BUF_OVFL                                                            (0x1<<18) // Message Processor Aggregation Task Command buffer overflow.
+  #define YCM_REG_INT_STS_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                                      18
+  #define YCM_REG_INT_STS_1_SM_TASK_DATA_BUF_OVFL                                                            (0x1<<19) // Message Processor Storm Task Data buffer overflow.
+  #define YCM_REG_INT_STS_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                                      19
+  #define YCM_REG_INT_STS_1_SM_TASK_CMD_BUF_OVFL                                                             (0x1<<20) // Message Processor Storm Task Command buffer overflow.
+  #define YCM_REG_INT_STS_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                                       20
+  #define YCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE                                                            (0x1<<21) // Input message first descriptor fields violation.
+  #define YCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE_SHIFT                                                      21
+  #define YCM_REG_INT_STS_1_SE_DESC_INPUT_VIOLATE                                                            (0x1<<22) // Input message second descriptor fields violation.
+  #define YCM_REG_INT_STS_1_SE_DESC_INPUT_VIOLATE_SHIFT                                                      22
+#define YCM_REG_INT_MASK_1                                                                                   0x1080194UL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define YCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR                                                                 (0x1<<0) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_PBF_OVFL_ERR .
+  #define YCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR_SHIFT                                                           0
+  #define YCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR                                                                (0x1<<1) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_PBF_UNDER_ERR .
+  #define YCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR_SHIFT                                                          1
+  #define YCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR                                                                (0x1<<2) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_QM_P_OVFL_ERR .
+  #define YCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR_SHIFT                                                          2
+  #define YCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR                                                               (0x1<<3) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_QM_P_UNDER_ERR .
+  #define YCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR_SHIFT                                                         3
+  #define YCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR                                                                (0x1<<4) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_QM_S_OVFL_ERR .
+  #define YCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR_SHIFT                                                          4
+  #define YCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR                                                               (0x1<<5) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_QM_S_UNDER_ERR .
+  #define YCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR_SHIFT                                                         5
+  #define YCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0                                                                (0x1<<6) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_GRC_OVFL_ERR0 .
+  #define YCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0_SHIFT                                                          6
+  #define YCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0                                                               (0x1<<7) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_GRC_UNDER_ERR0 .
+  #define YCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0_SHIFT                                                         7
+  #define YCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1                                                                (0x1<<8) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_GRC_OVFL_ERR1 .
+  #define YCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1_SHIFT                                                          8
+  #define YCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1                                                               (0x1<<9) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_GRC_UNDER_ERR1 .
+  #define YCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1_SHIFT                                                         9
+  #define YCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2                                                                (0x1<<10) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_GRC_OVFL_ERR2 .
+  #define YCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2_SHIFT                                                          10
+  #define YCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2                                                               (0x1<<11) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_GRC_UNDER_ERR2 .
+  #define YCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2_SHIFT                                                         11
+  #define YCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3                                                                (0x1<<12) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_GRC_OVFL_ERR3 .
+  #define YCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3_SHIFT                                                          12
+  #define YCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3                                                               (0x1<<13) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_GRC_UNDER_ERR3 .
+  #define YCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3_SHIFT                                                         13
+  #define YCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL                                                                (0x1<<14) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IN_PRCS_TBL_OVFL .
+  #define YCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL_SHIFT                                                          14
+  #define YCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL                                                            (0x1<<15) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.SM_CON_DATA_BUF_OVFL .
+  #define YCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL_SHIFT                                                      15
+  #define YCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL                                                             (0x1<<16) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.SM_CON_CMD_BUF_OVFL .
+  #define YCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL_SHIFT                                                       16
+  #define YCM_REG_INT_MASK_1_AGG_TASK_DATA_BUF_OVFL                                                          (0x1<<17) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.AGG_TASK_DATA_BUF_OVFL .
+  #define YCM_REG_INT_MASK_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                                    17
+  #define YCM_REG_INT_MASK_1_AGG_TASK_CMD_BUF_OVFL                                                           (0x1<<18) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.AGG_TASK_CMD_BUF_OVFL .
+  #define YCM_REG_INT_MASK_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                                     18
+  #define YCM_REG_INT_MASK_1_SM_TASK_DATA_BUF_OVFL                                                           (0x1<<19) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.SM_TASK_DATA_BUF_OVFL .
+  #define YCM_REG_INT_MASK_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                                     19
+  #define YCM_REG_INT_MASK_1_SM_TASK_CMD_BUF_OVFL                                                            (0x1<<20) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.SM_TASK_CMD_BUF_OVFL .
+  #define YCM_REG_INT_MASK_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                                      20
+  #define YCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE                                                           (0x1<<21) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.FI_DESC_INPUT_VIOLATE .
+  #define YCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE_SHIFT                                                     21
+  #define YCM_REG_INT_MASK_1_SE_DESC_INPUT_VIOLATE                                                           (0x1<<22) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.SE_DESC_INPUT_VIOLATE .
+  #define YCM_REG_INT_MASK_1_SE_DESC_INPUT_VIOLATE_SHIFT                                                     22
+#define YCM_REG_INT_STS_WR_1                                                                                 0x1080198UL //Access:WR   DataWidth:0x17   // Multi Field Register.
+  #define YCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR                                                               (0x1<<0) // Write to full Pbf input buffer.
+  #define YCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR_SHIFT                                                         0
+  #define YCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR                                                              (0x1<<1) // Read from empty Pbf input buffer.
+  #define YCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR_SHIFT                                                        1
+  #define YCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR                                                              (0x1<<2) // Write to full QM input buffer.
+  #define YCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR_SHIFT                                                        2
+  #define YCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR                                                             (0x1<<3) // Read from empty QM input buffer.
+  #define YCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR_SHIFT                                                       3
+  #define YCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR                                                              (0x1<<4) // Write to full QM input buffer.
+  #define YCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR_SHIFT                                                        4
+  #define YCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR                                                             (0x1<<5) // Read from empty QM input buffer.
+  #define YCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR_SHIFT                                                       5
+  #define YCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0                                                              (0x1<<6) // Write to full GRC input buffer bits [31:0].
+  #define YCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0_SHIFT                                                        6
+  #define YCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0                                                             (0x1<<7) // Read from empty  GRC input buffer bits [31:0].
+  #define YCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0_SHIFT                                                       7
+  #define YCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1                                                              (0x1<<8) // Write to full GRC input buffer bits [63:32].
+  #define YCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1_SHIFT                                                        8
+  #define YCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1                                                             (0x1<<9) // Read from empty  GRC input buffer bits [63:32].
+  #define YCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1_SHIFT                                                       9
+  #define YCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2                                                              (0x1<<10) // Write to full GRC input buffer bits [95:64].
+  #define YCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2_SHIFT                                                        10
+  #define YCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2                                                             (0x1<<11) // Read from empty  GRC input buffer bits [95:64].
+  #define YCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2_SHIFT                                                       11
+  #define YCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3                                                              (0x1<<12) // Write to full GRC input buffer bits [127:96].
+  #define YCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3_SHIFT                                                        12
+  #define YCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3                                                             (0x1<<13) // Read from empty  GRC input buffer bits [127:96].
+  #define YCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3_SHIFT                                                       13
+  #define YCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL                                                              (0x1<<14) // In-process Table overflow.
+  #define YCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL_SHIFT                                                        14
+  #define YCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL                                                          (0x1<<15) // Message Processor Storm Connection Data buffer overflow.
+  #define YCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL_SHIFT                                                    15
+  #define YCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL                                                           (0x1<<16) // Message Processor Storm Connection Command buffer overflow.
+  #define YCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL_SHIFT                                                     16
+  #define YCM_REG_INT_STS_WR_1_AGG_TASK_DATA_BUF_OVFL                                                        (0x1<<17) // Message Processor Aggregation Task Data buffer overflow.
+  #define YCM_REG_INT_STS_WR_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                                  17
+  #define YCM_REG_INT_STS_WR_1_AGG_TASK_CMD_BUF_OVFL                                                         (0x1<<18) // Message Processor Aggregation Task Command buffer overflow.
+  #define YCM_REG_INT_STS_WR_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                                   18
+  #define YCM_REG_INT_STS_WR_1_SM_TASK_DATA_BUF_OVFL                                                         (0x1<<19) // Message Processor Storm Task Data buffer overflow.
+  #define YCM_REG_INT_STS_WR_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                                   19
+  #define YCM_REG_INT_STS_WR_1_SM_TASK_CMD_BUF_OVFL                                                          (0x1<<20) // Message Processor Storm Task Command buffer overflow.
+  #define YCM_REG_INT_STS_WR_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                                    20
+  #define YCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE                                                         (0x1<<21) // Input message first descriptor fields violation.
+  #define YCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE_SHIFT                                                   21
+  #define YCM_REG_INT_STS_WR_1_SE_DESC_INPUT_VIOLATE                                                         (0x1<<22) // Input message second descriptor fields violation.
+  #define YCM_REG_INT_STS_WR_1_SE_DESC_INPUT_VIOLATE_SHIFT                                                   22
+#define YCM_REG_INT_STS_CLR_1                                                                                0x108019cUL //Access:RC   DataWidth:0x17   // Multi Field Register.
+  #define YCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR                                                              (0x1<<0) // Write to full Pbf input buffer.
+  #define YCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR_SHIFT                                                        0
+  #define YCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR                                                             (0x1<<1) // Read from empty Pbf input buffer.
+  #define YCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR_SHIFT                                                       1
+  #define YCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR                                                             (0x1<<2) // Write to full QM input buffer.
+  #define YCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR_SHIFT                                                       2
+  #define YCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR                                                            (0x1<<3) // Read from empty QM input buffer.
+  #define YCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR_SHIFT                                                      3
+  #define YCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR                                                             (0x1<<4) // Write to full QM input buffer.
+  #define YCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR_SHIFT                                                       4
+  #define YCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR                                                            (0x1<<5) // Read from empty QM input buffer.
+  #define YCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR_SHIFT                                                      5
+  #define YCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0                                                             (0x1<<6) // Write to full GRC input buffer bits [31:0].
+  #define YCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0_SHIFT                                                       6
+  #define YCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0                                                            (0x1<<7) // Read from empty  GRC input buffer bits [31:0].
+  #define YCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0_SHIFT                                                      7
+  #define YCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1                                                             (0x1<<8) // Write to full GRC input buffer bits [63:32].
+  #define YCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1_SHIFT                                                       8
+  #define YCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1                                                            (0x1<<9) // Read from empty  GRC input buffer bits [63:32].
+  #define YCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1_SHIFT                                                      9
+  #define YCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2                                                             (0x1<<10) // Write to full GRC input buffer bits [95:64].
+  #define YCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2_SHIFT                                                       10
+  #define YCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2                                                            (0x1<<11) // Read from empty  GRC input buffer bits [95:64].
+  #define YCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2_SHIFT                                                      11
+  #define YCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3                                                             (0x1<<12) // Write to full GRC input buffer bits [127:96].
+  #define YCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3_SHIFT                                                       12
+  #define YCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3                                                            (0x1<<13) // Read from empty  GRC input buffer bits [127:96].
+  #define YCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3_SHIFT                                                      13
+  #define YCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL                                                             (0x1<<14) // In-process Table overflow.
+  #define YCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL_SHIFT                                                       14
+  #define YCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL                                                         (0x1<<15) // Message Processor Storm Connection Data buffer overflow.
+  #define YCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL_SHIFT                                                   15
+  #define YCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL                                                          (0x1<<16) // Message Processor Storm Connection Command buffer overflow.
+  #define YCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL_SHIFT                                                    16
+  #define YCM_REG_INT_STS_CLR_1_AGG_TASK_DATA_BUF_OVFL                                                       (0x1<<17) // Message Processor Aggregation Task Data buffer overflow.
+  #define YCM_REG_INT_STS_CLR_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                                 17
+  #define YCM_REG_INT_STS_CLR_1_AGG_TASK_CMD_BUF_OVFL                                                        (0x1<<18) // Message Processor Aggregation Task Command buffer overflow.
+  #define YCM_REG_INT_STS_CLR_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                                  18
+  #define YCM_REG_INT_STS_CLR_1_SM_TASK_DATA_BUF_OVFL                                                        (0x1<<19) // Message Processor Storm Task Data buffer overflow.
+  #define YCM_REG_INT_STS_CLR_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                                  19
+  #define YCM_REG_INT_STS_CLR_1_SM_TASK_CMD_BUF_OVFL                                                         (0x1<<20) // Message Processor Storm Task Command buffer overflow.
+  #define YCM_REG_INT_STS_CLR_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                                   20
+  #define YCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE                                                        (0x1<<21) // Input message first descriptor fields violation.
+  #define YCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE_SHIFT                                                  21
+  #define YCM_REG_INT_STS_CLR_1_SE_DESC_INPUT_VIOLATE                                                        (0x1<<22) // Input message second descriptor fields violation.
+  #define YCM_REG_INT_STS_CLR_1_SE_DESC_INPUT_VIOLATE_SHIFT                                                  22
+#define YCM_REG_INT_STS_2                                                                                    0x10801a0UL //Access:R    DataWidth:0x1    // Multi Field Register.
+  #define YCM_REG_INT_STS_2_QMREG_MORE4                                                                      (0x1<<0) // More than 4 QM registrations.
+  #define YCM_REG_INT_STS_2_QMREG_MORE4_SHIFT                                                                0
+#define YCM_REG_INT_MASK_2                                                                                   0x10801a4UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define YCM_REG_INT_MASK_2_QMREG_MORE4                                                                     (0x1<<0) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_2.QMREG_MORE4 .
+  #define YCM_REG_INT_MASK_2_QMREG_MORE4_SHIFT                                                               0
+#define YCM_REG_INT_STS_WR_2                                                                                 0x10801a8UL //Access:WR   DataWidth:0x1    // Multi Field Register.
+  #define YCM_REG_INT_STS_WR_2_QMREG_MORE4                                                                   (0x1<<0) // More than 4 QM registrations.
+  #define YCM_REG_INT_STS_WR_2_QMREG_MORE4_SHIFT                                                             0
+#define YCM_REG_INT_STS_CLR_2                                                                                0x10801acUL //Access:RC   DataWidth:0x1    // Multi Field Register.
+  #define YCM_REG_INT_STS_CLR_2_QMREG_MORE4                                                                  (0x1<<0) // More than 4 QM registrations.
+  #define YCM_REG_INT_STS_CLR_2_QMREG_MORE4_SHIFT                                                            0
+#define YCM_REG_PRTY_MASK_H_0_BB_K2                                                                          0x1080204UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define YCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_RF_INT_K2                                                       (0x1<<0) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM027_I_ECC_RF_INT .
+  #define YCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_RF_INT_K2_SHIFT                                                 0
+  #define YCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT_BB_K2                                                  (0x1<<1) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM003_I_ECC_0_RF_INT .
+  #define YCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT_BB_K2_SHIFT                                            1
+  #define YCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT_BB_K2                                                  (0x1<<2) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM003_I_ECC_1_RF_INT .
+  #define YCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT_BB_K2_SHIFT                                            2
+  #define YCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_0_RF_INT_K2                                                     (0x1<<3) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM022_I_ECC_0_RF_INT .
+  #define YCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_0_RF_INT_K2_SHIFT                                               3
+  #define YCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_1_RF_INT_K2                                                     (0x1<<4) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM022_I_ECC_1_RF_INT .
+  #define YCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_1_RF_INT_K2_SHIFT                                               4
+  #define YCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_RF_INT_K2                                                       (0x1<<5) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM023_I_ECC_RF_INT .
+  #define YCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_RF_INT_K2_SHIFT                                                 5
+  #define YCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_BB_K2                                                  (0x1<<6) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
+  #define YCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_BB_K2_SHIFT                                            6
+  #define YCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_K2                                                  (0x1<<7) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
+  #define YCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_K2_SHIFT                                            7
+  #define YCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_0_RF_INT_K2                                                     (0x1<<8) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM025_I_ECC_0_RF_INT .
+  #define YCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_0_RF_INT_K2_SHIFT                                               8
+  #define YCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_1_RF_INT_K2                                                     (0x1<<9) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM025_I_ECC_1_RF_INT .
+  #define YCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_1_RF_INT_K2_SHIFT                                               9
+  #define YCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_K2                                                      (0x1<<10) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_K2_SHIFT                                                10
+  #define YCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB                                                         (0x1<<26) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_SHIFT                                                   26
+  #define YCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2                                                         (0x1<<11) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2_SHIFT                                                   11
+  #define YCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB                                                         (0x1<<11) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_SHIFT                                                   11
+  #define YCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2                                                         (0x1<<12) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_SHIFT                                                   12
+  #define YCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB                                                         (0x1<<12) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_SHIFT                                                   12
+  #define YCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2                                                         (0x1<<13) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2_SHIFT                                                   13
+  #define YCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB                                                         (0x1<<13) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_SHIFT                                                   13
+  #define YCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2                                                         (0x1<<14) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_SHIFT                                                   14
+  #define YCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB                                                         (0x1<<14) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_SHIFT                                                   14
+  #define YCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2                                                         (0x1<<15) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2_SHIFT                                                   15
+  #define YCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB                                                         (0x1<<15) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_SHIFT                                                   15
+  #define YCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2                                                         (0x1<<16) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2_SHIFT                                                   16
+  #define YCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB                                                         (0x1<<16) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_SHIFT                                                   16
+  #define YCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2                                                         (0x1<<17) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2_SHIFT                                                   17
+  #define YCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB                                                         (0x1<<17) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_SHIFT                                                   17
+  #define YCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2                                                         (0x1<<18) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2_SHIFT                                                   18
+  #define YCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB                                                         (0x1<<18) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_SHIFT                                                   18
+  #define YCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2                                                         (0x1<<19) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2_SHIFT                                                   19
+  #define YCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2                                                         (0x1<<20) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2_SHIFT                                                   20
+  #define YCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB                                                         (0x1<<19) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_SHIFT                                                   19
+  #define YCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2                                                         (0x1<<21) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2_SHIFT                                                   21
+  #define YCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB                                                         (0x1<<20) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_SHIFT                                                   20
+  #define YCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2                                                         (0x1<<22) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2_SHIFT                                                   22
+  #define YCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB                                                         (0x1<<22) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_SHIFT                                                   22
+  #define YCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2                                                         (0x1<<23) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_SHIFT                                                   23
+  #define YCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2                                                         (0x1<<24) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2_SHIFT                                                   24
+  #define YCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB                                                         (0x1<<24) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_SHIFT                                                   24
+  #define YCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2                                                         (0x1<<25) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_SHIFT                                                   25
+  #define YCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_K2                                                         (0x1<<26) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_K2_SHIFT                                                   26
+  #define YCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2                                                         (0x1<<27) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2_SHIFT                                                   27
+  #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_BB                                                       (0x1<<27) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_0 .
+  #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_BB_SHIFT                                                 27
+  #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_K2                                                       (0x1<<28) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_0 .
+  #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_K2_SHIFT                                                 28
+  #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_BB                                                       (0x1<<28) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_1 .
+  #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_BB_SHIFT                                                 28
+  #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_K2                                                       (0x1<<29) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_1 .
+  #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_K2_SHIFT                                                 29
+  #define YCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB                                                         (0x1<<29) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_SHIFT                                                   29
+  #define YCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2                                                         (0x1<<30) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_SHIFT                                                   30
+  #define YCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_BB                                                       (0x1<<0) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM026_I_ECC_RF_INT .
+  #define YCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_BB_SHIFT                                                 0
+  #define YCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_0_RF_INT_BB                                                     (0x1<<3) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM021_I_ECC_0_RF_INT .
+  #define YCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_0_RF_INT_BB_SHIFT                                               3
+  #define YCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_1_RF_INT_BB                                                     (0x1<<4) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM021_I_ECC_1_RF_INT .
+  #define YCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_1_RF_INT_BB_SHIFT                                               4
+  #define YCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT_BB                                                       (0x1<<5) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM022_I_ECC_RF_INT .
+  #define YCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT_BB_SHIFT                                                 5
+  #define YCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_0_RF_INT_BB                                                     (0x1<<8) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM024_I_ECC_0_RF_INT .
+  #define YCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_0_RF_INT_BB_SHIFT                                               8
+  #define YCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_1_RF_INT_BB                                                     (0x1<<9) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM024_I_ECC_1_RF_INT .
+  #define YCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_1_RF_INT_BB_SHIFT                                               9
+  #define YCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB                                                         (0x1<<21) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_SHIFT                                                   21
+  #define YCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB                                                         (0x1<<23) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_SHIFT                                                   23
+  #define YCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB                                                         (0x1<<25) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB_SHIFT                                                   25
+  #define YCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB                                                         (0x1<<30) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_SHIFT                                                   30
+#define YCM_REG_PRTY_MASK_H_1_BB_K2                                                                          0x1080214UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define YCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_K2                                                         (0x1<<0) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_K2_SHIFT                                                   0
+  #define YCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB                                                         (0x1<<0) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB_SHIFT                                                   0
+  #define YCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_K2                                                         (0x1<<1) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_K2_SHIFT                                                   1
+  #define YCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB                                                         (0x1<<1) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_SHIFT                                                   1
+  #define YCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2                                                         (0x1<<2) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2_SHIFT                                                   2
+  #define YCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB                                                         (0x1<<2) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_SHIFT                                                   2
+  #define YCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2                                                         (0x1<<3) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
+  #define YCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2_SHIFT                                                   3
+#define YCM_REG_MEM005_RF_ECC_ERROR_CONNECT_0_BB_K2                                                          0x1080220UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: ycm.i_agg_task_ctx.rf_ecc_error_connect_0 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define YCM_REG_MEM005_RF_ECC_ERROR_CONNECT_1_BB_K2                                                          0x1080224UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: ycm.i_agg_task_ctx.rf_ecc_error_connect_1 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define YCM_REG_MEM_ECC_ENABLE_0_BB_K2                                                                       0x1080228UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_EN_K2                                                        (0x1<<0) // Enable ECC for memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_msg_ram
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_EN_K2_SHIFT                                                  0
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_0_EN_BB_K2                                                   (0x1<<1) // Enable ECC for memory ecc instance ycm.i_agg_con_ctx.i_ecc_0 in module ycm_mem_agg_con_ctx
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_0_EN_BB_K2_SHIFT                                             1
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_1_EN_BB_K2                                                   (0x1<<2) // Enable ECC for memory ecc instance ycm.i_agg_con_ctx.i_ecc_1 in module ycm_mem_agg_con_ctx
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_1_EN_BB_K2_SHIFT                                             2
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_0_EN_K2                                                      (0x1<<3) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_0 in module ycm_mem_sm_con_ctx_0_1
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_0_EN_K2_SHIFT                                                3
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_1_EN_K2                                                      (0x1<<4) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_1 in module ycm_mem_sm_con_ctx_0_1
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_1_EN_K2_SHIFT                                                4
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_EN_K2                                                        (0x1<<5) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx_2.i_ecc in module ycm_mem_sm_con_ctx_2
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_EN_K2_SHIFT                                                  5
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN_BB_K2                                                   (0x1<<6) // Enable ECC for memory ecc instance ycm.i_agg_task_ctx.i_ecc_0 in module ycm_mem_agg_task_ctx
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN_BB_K2_SHIFT                                             6
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_BB_K2                                                   (0x1<<7) // Enable ECC for memory ecc instance ycm.i_agg_task_ctx.i_ecc_1 in module ycm_mem_agg_task_ctx
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_BB_K2_SHIFT                                             7
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_0_EN_K2                                                      (0x1<<8) // Enable ECC for memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_task_ctx
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_0_EN_K2_SHIFT                                                8
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_1_EN_K2                                                      (0x1<<9) // Enable ECC for memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_task_ctx
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_1_EN_K2_SHIFT                                                9
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_EN_BB                                                        (0x1<<0) // Enable ECC for memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_msg_ram
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_EN_BB_SHIFT                                                  0
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_0_EN_BB                                                      (0x1<<3) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_0 in module ycm_mem_sm_con_ctx_0_1
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_0_EN_BB_SHIFT                                                3
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_1_EN_BB                                                      (0x1<<4) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_1 in module ycm_mem_sm_con_ctx_0_1
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_1_EN_BB_SHIFT                                                4
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_EN_BB                                                        (0x1<<5) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx_2.i_ecc in module ycm_mem_sm_con_ctx_2
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_EN_BB_SHIFT                                                  5
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_0_EN_BB                                                      (0x1<<8) // Enable ECC for memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_task_ctx
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_0_EN_BB_SHIFT                                                8
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_1_EN_BB                                                      (0x1<<9) // Enable ECC for memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_task_ctx
+  #define YCM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_1_EN_BB_SHIFT                                                9
+#define YCM_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                  0x108022cUL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_PRTY_K2                                                 (0x1<<0) // Set parity only for memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_msg_ram
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_PRTY_K2_SHIFT                                           0
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_0_PRTY_BB_K2                                            (0x1<<1) // Set parity only for memory ecc instance ycm.i_agg_con_ctx.i_ecc_0 in module ycm_mem_agg_con_ctx
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_0_PRTY_BB_K2_SHIFT                                      1
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_1_PRTY_BB_K2                                            (0x1<<2) // Set parity only for memory ecc instance ycm.i_agg_con_ctx.i_ecc_1 in module ycm_mem_agg_con_ctx
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_1_PRTY_BB_K2_SHIFT                                      2
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_0_PRTY_K2                                               (0x1<<3) // Set parity only for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_0 in module ycm_mem_sm_con_ctx_0_1
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_0_PRTY_K2_SHIFT                                         3
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_1_PRTY_K2                                               (0x1<<4) // Set parity only for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_1 in module ycm_mem_sm_con_ctx_0_1
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_1_PRTY_K2_SHIFT                                         4
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_PRTY_K2                                                 (0x1<<5) // Set parity only for memory ecc instance ycm.i_sm_con_ctx_2.i_ecc in module ycm_mem_sm_con_ctx_2
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_PRTY_K2_SHIFT                                           5
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY_BB_K2                                            (0x1<<6) // Set parity only for memory ecc instance ycm.i_agg_task_ctx.i_ecc_0 in module ycm_mem_agg_task_ctx
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY_BB_K2_SHIFT                                      6
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_BB_K2                                            (0x1<<7) // Set parity only for memory ecc instance ycm.i_agg_task_ctx.i_ecc_1 in module ycm_mem_agg_task_ctx
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_BB_K2_SHIFT                                      7
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_0_PRTY_K2                                               (0x1<<8) // Set parity only for memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_task_ctx
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_0_PRTY_K2_SHIFT                                         8
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_1_PRTY_K2                                               (0x1<<9) // Set parity only for memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_task_ctx
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_1_PRTY_K2_SHIFT                                         9
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_PRTY_BB                                                 (0x1<<0) // Set parity only for memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_msg_ram
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_PRTY_BB_SHIFT                                           0
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_0_PRTY_BB                                               (0x1<<3) // Set parity only for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_0 in module ycm_mem_sm_con_ctx_0_1
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_0_PRTY_BB_SHIFT                                         3
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_1_PRTY_BB                                               (0x1<<4) // Set parity only for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_1 in module ycm_mem_sm_con_ctx_0_1
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_1_PRTY_BB_SHIFT                                         4
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_PRTY_BB                                                 (0x1<<5) // Set parity only for memory ecc instance ycm.i_sm_con_ctx_2.i_ecc in module ycm_mem_sm_con_ctx_2
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_PRTY_BB_SHIFT                                           5
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_0_PRTY_BB                                               (0x1<<8) // Set parity only for memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_task_ctx
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_0_PRTY_BB_SHIFT                                         8
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_1_PRTY_BB                                               (0x1<<9) // Set parity only for memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_task_ctx
+  #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_1_PRTY_BB_SHIFT                                         9
+#define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                              0x1080230UL //Access:RC   DataWidth:0xa    // Multi Field Register.
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_CORRECT_K2                                          (0x1<<0) // Record if a correctable error occurred on memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_msg_ram
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_CORRECT_K2_SHIFT                                    0
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_0_CORRECT_BB_K2                                     (0x1<<1) // Record if a correctable error occurred on memory ecc instance ycm.i_agg_con_ctx.i_ecc_0 in module ycm_mem_agg_con_ctx
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_0_CORRECT_BB_K2_SHIFT                               1
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_1_CORRECT_BB_K2                                     (0x1<<2) // Record if a correctable error occurred on memory ecc instance ycm.i_agg_con_ctx.i_ecc_1 in module ycm_mem_agg_con_ctx
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_1_CORRECT_BB_K2_SHIFT                               2
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_0_CORRECT_K2                                        (0x1<<3) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_0 in module ycm_mem_sm_con_ctx_0_1
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_0_CORRECT_K2_SHIFT                                  3
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_1_CORRECT_K2                                        (0x1<<4) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_1 in module ycm_mem_sm_con_ctx_0_1
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_1_CORRECT_K2_SHIFT                                  4
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_CORRECT_K2                                          (0x1<<5) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_con_ctx_2.i_ecc in module ycm_mem_sm_con_ctx_2
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_CORRECT_K2_SHIFT                                    5
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT_BB_K2                                     (0x1<<6) // Record if a correctable error occurred on memory ecc instance ycm.i_agg_task_ctx.i_ecc_0 in module ycm_mem_agg_task_ctx
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT_BB_K2_SHIFT                               6
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_BB_K2                                     (0x1<<7) // Record if a correctable error occurred on memory ecc instance ycm.i_agg_task_ctx.i_ecc_1 in module ycm_mem_agg_task_ctx
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_BB_K2_SHIFT                               7
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_0_CORRECT_K2                                        (0x1<<8) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_task_ctx
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_0_CORRECT_K2_SHIFT                                  8
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_1_CORRECT_K2                                        (0x1<<9) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_task_ctx
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_1_CORRECT_K2_SHIFT                                  9
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM026_I_ECC_CORRECT_BB                                          (0x1<<0) // Record if a correctable error occurred on memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_msg_ram
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM026_I_ECC_CORRECT_BB_SHIFT                                    0
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_0_CORRECT_BB                                        (0x1<<3) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_0 in module ycm_mem_sm_con_ctx_0_1
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_0_CORRECT_BB_SHIFT                                  3
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_1_CORRECT_BB                                        (0x1<<4) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_1 in module ycm_mem_sm_con_ctx_0_1
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_1_CORRECT_BB_SHIFT                                  4
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_CORRECT_BB                                          (0x1<<5) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_con_ctx_2.i_ecc in module ycm_mem_sm_con_ctx_2
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_CORRECT_BB_SHIFT                                    5
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_0_CORRECT_BB                                        (0x1<<8) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_task_ctx
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_0_CORRECT_BB_SHIFT                                  8
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_1_CORRECT_BB                                        (0x1<<9) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_task_ctx
+  #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_1_CORRECT_BB_SHIFT                                  9
+#define YCM_REG_MEM_ECC_EVENTS_BB_K2                                                                         0x1080234UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define YCM_REG_IFEN                                                                                         0x1080400UL //Access:RW   DataWidth:0x1    // Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
+#define YCM_REG_QM_TASK_BASE_EVNT_ID_0                                                                       0x1080424UL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define YCM_REG_QM_TASK_BASE_EVNT_ID_1                                                                       0x1080428UL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define YCM_REG_QM_TASK_BASE_EVNT_ID_2                                                                       0x108042cUL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define YCM_REG_QM_TASK_BASE_EVNT_ID_3                                                                       0x1080430UL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define YCM_REG_QM_TASK_BASE_EVNT_ID_4                                                                       0x1080434UL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define YCM_REG_QM_TASK_BASE_EVNT_ID_5                                                                       0x1080438UL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define YCM_REG_QM_TASK_BASE_EVNT_ID_6                                                                       0x108043cUL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define YCM_REG_QM_TASK_BASE_EVNT_ID_7                                                                       0x1080440UL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define YCM_REG_QM_AGG_TASK_CTX_PART_SIZE_0                                                                  0x1080484UL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define YCM_REG_QM_AGG_TASK_CTX_PART_SIZE_1                                                                  0x1080488UL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define YCM_REG_QM_AGG_TASK_CTX_PART_SIZE_2                                                                  0x108048cUL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define YCM_REG_QM_AGG_TASK_CTX_PART_SIZE_3                                                                  0x1080490UL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define YCM_REG_QM_AGG_TASK_CTX_PART_SIZE_4                                                                  0x1080494UL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define YCM_REG_QM_AGG_TASK_CTX_PART_SIZE_5                                                                  0x1080498UL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define YCM_REG_QM_AGG_TASK_CTX_PART_SIZE_6                                                                  0x108049cUL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define YCM_REG_QM_AGG_TASK_CTX_PART_SIZE_7                                                                  0x10804a0UL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define YCM_REG_QM_SM_TASK_CTX_LDST_FLG_0                                                                    0x10804a4UL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define YCM_REG_QM_SM_TASK_CTX_LDST_FLG_1                                                                    0x10804a8UL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define YCM_REG_QM_SM_TASK_CTX_LDST_FLG_2                                                                    0x10804acUL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define YCM_REG_QM_SM_TASK_CTX_LDST_FLG_3                                                                    0x10804b0UL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define YCM_REG_QM_SM_TASK_CTX_LDST_FLG_4                                                                    0x10804b4UL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define YCM_REG_QM_SM_TASK_CTX_LDST_FLG_5                                                                    0x10804b8UL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define YCM_REG_QM_SM_TASK_CTX_LDST_FLG_6                                                                    0x10804bcUL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define YCM_REG_QM_SM_TASK_CTX_LDST_FLG_7                                                                    0x10804c0UL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define YCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_0                                                                    0x10804c4UL //Access:RW   DataWidth:0x4    // TCFC Lock UC Update value per task type.
+#define YCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_1                                                                    0x10804c8UL //Access:RW   DataWidth:0x4    // TCFC Lock UC Update value per task type.
+#define YCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_2                                                                    0x10804ccUL //Access:RW   DataWidth:0x4    // TCFC Lock UC Update value per task type.
+#define YCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_3                                                                    0x10804d0UL //Access:RW   DataWidth:0x4    // TCFC Lock UC Update value per task type.
+#define YCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_4                                                                    0x10804d4UL //Access:RW   DataWidth:0x4    // TCFC Lock UC Update value per task type.
+#define YCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_5                                                                    0x10804d8UL //Access:RW   DataWidth:0x4    // TCFC Lock UC Update value per task type.
+#define YCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_6                                                                    0x10804dcUL //Access:RW   DataWidth:0x4    // TCFC Lock UC Update value per task type.
+#define YCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_7                                                                    0x10804e0UL //Access:RW   DataWidth:0x4    // TCFC Lock UC Update value per task type.
+#define YCM_REG_QM_TCFC_XXLOCK_CMD_0                                                                         0x10804e4UL //Access:RW   DataWidth:0x3    // TCFC Lock UC xxLock command per task type.
+#define YCM_REG_QM_TCFC_XXLOCK_CMD_1                                                                         0x10804e8UL //Access:RW   DataWidth:0x3    // TCFC Lock UC xxLock command per task type.
+#define YCM_REG_QM_TCFC_XXLOCK_CMD_2                                                                         0x10804ecUL //Access:RW   DataWidth:0x3    // TCFC Lock UC xxLock command per task type.
+#define YCM_REG_QM_TCFC_XXLOCK_CMD_3                                                                         0x10804f0UL //Access:RW   DataWidth:0x3    // TCFC Lock UC xxLock command per task type.
+#define YCM_REG_QM_TCFC_XXLOCK_CMD_4                                                                         0x10804f4UL //Access:RW   DataWidth:0x3    // TCFC Lock UC xxLock command per task type.
+#define YCM_REG_QM_TCFC_XXLOCK_CMD_5                                                                         0x10804f8UL //Access:RW   DataWidth:0x3    // TCFC Lock UC xxLock command per task type.
+#define YCM_REG_QM_TCFC_XXLOCK_CMD_6                                                                         0x10804fcUL //Access:RW   DataWidth:0x3    // TCFC Lock UC xxLock command per task type.
+#define YCM_REG_QM_TCFC_XXLOCK_CMD_7                                                                         0x1080500UL //Access:RW   DataWidth:0x3    // TCFC Lock UC xxLock command per task type.
+#define YCM_REG_QM_TASK_USE_ST_FLG_0                                                                         0x1080544UL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define YCM_REG_QM_TASK_USE_ST_FLG_1                                                                         0x1080548UL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define YCM_REG_QM_TASK_USE_ST_FLG_2                                                                         0x108054cUL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define YCM_REG_QM_TASK_USE_ST_FLG_3                                                                         0x1080550UL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define YCM_REG_QM_TASK_USE_ST_FLG_4                                                                         0x1080554UL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define YCM_REG_QM_TASK_USE_ST_FLG_5                                                                         0x1080558UL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define YCM_REG_QM_TASK_USE_ST_FLG_6                                                                         0x108055cUL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define YCM_REG_QM_TASK_USE_ST_FLG_7                                                                         0x1080560UL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM.
+#define YCM_REG_ERR_EVNT_ID                                                                                  0x1080564UL //Access:RW   DataWidth:0x8    // The Event ID in case one of errors is set in QM input message.
+#define YCM_REG_STORM_WEIGHT                                                                                 0x1080604UL //Access:RW   DataWidth:0x3    // The weight of the local Storm input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define YCM_REG_MSEM_WEIGHT                                                                                  0x1080608UL //Access:RW   DataWidth:0x3    // The weight of the input Msem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define YCM_REG_USEM_WEIGHT                                                                                  0x108060cUL //Access:RW   DataWidth:0x3    // The weight of the input Usem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define YCM_REG_PBF_WEIGHT                                                                                   0x1080610UL //Access:RW   DataWidth:0x3    // The weight of the input Pbf in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define YCM_REG_GRC_WEIGHT                                                                                   0x1080614UL //Access:RW   DataWidth:0x3    // The weight of the GRC input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define YCM_REG_YSDM_WEIGHT                                                                                  0x108061cUL //Access:RW   DataWidth:0x3    // The weight of the YSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define YCM_REG_XYLD_WEIGHT                                                                                  0x1080620UL //Access:RW   DataWidth:0x3    // The weight of the input XYLD in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define YCM_REG_QM_P_WEIGHT                                                                                  0x1080624UL //Access:RW   DataWidth:0x3    // The weight of the QM (primary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define YCM_REG_QM_S_WEIGHT                                                                                  0x1080628UL //Access:RW   DataWidth:0x3    // The weight of the QM (secondary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define YCM_REG_IA_GROUP_PR0                                                                                 0x108062cUL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: ia_group_pr0 is the highest priority; ia_group_pr5 is the lowest priority.
+#define YCM_REG_IA_GROUP_PR1                                                                                 0x1080630UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define YCM_REG_IA_GROUP_PR2                                                                                 0x1080634UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define YCM_REG_IA_GROUP_PR3                                                                                 0x1080638UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define YCM_REG_IA_GROUP_PR4                                                                                 0x108063cUL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define YCM_REG_IA_GROUP_PR5                                                                                 0x1080640UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define YCM_REG_IA_ARB_SP_TIMEOUT                                                                            0x1080644UL //Access:RW   DataWidth:0x8    // Input Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8'h0 - constant RR; 8'h80 - constant strict priority. In all other cases the following is true: Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance.
+#define YCM_REG_STORM_FRWRD_MODE                                                                             0x1080648UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define YCM_REG_YSDM_FRWRD_MODE                                                                              0x1080650UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define YCM_REG_XYLD_FRWRD_MODE                                                                              0x1080654UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define YCM_REG_MSEM_FRWRD_MODE                                                                              0x1080658UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define YCM_REG_USEM_FRWRD_MODE                                                                              0x108065cUL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define YCM_REG_PBF_FRWRD_MODE                                                                               0x1080660UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define YCM_REG_SDM_ERR_HANDLE_EN                                                                            0x1080664UL //Access:RW   DataWidth:0x1    // 0 - disable error handling in SDM message; 1 - enable error handling in SDM message.
+#define YCM_REG_DIR_BYP_EN                                                                                   0x1080668UL //Access:RW   DataWidth:0x1    // Direct bypass enable.
+#define YCM_REG_FI_DESC_INPUT_VIOLATE                                                                        0x108066cUL //Access:R    DataWidth:0xf    // Input message first descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0  then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL  then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation:  Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation:  TaskExist==0 -> XxLockCmd != XX_UNLOCK_CID_TID and XxLockCmd != XX_LOCK_CID_TID_BYPASS;  [12] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0;[13] - Violation: Agg message: Loader done with error then SmCtxLdStFlg==0; [14] - Violation: XxBypass message in PCM block;
+#define YCM_REG_SE_DESC_INPUT_VIOLATE                                                                        0x1080670UL //Access:R    DataWidth:0xc    // Input message second descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0  then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL  then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation:  Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0; Read only register.
+#define YCM_REG_IA_AGG_CON_PART_FILL_LVL                                                                     0x1080674UL //Access:R    DataWidth:0x3    // Input Arbiter Aggregation Connection part FIFO fill level (in messages).
+#define YCM_REG_IA_SM_CON_PART_FILL_LVL                                                                      0x1080678UL //Access:R    DataWidth:0x3    // Input Arbiter Storm Connection part FIFO fill level (in messages).
+#define YCM_REG_IA_AGG_TASK_PART_FILL_LVL                                                                    0x108067cUL //Access:R    DataWidth:0x3    // Input Arbiter Aggregation Task part FIFO fill level (in messages).
+#define YCM_REG_IA_SM_TASK_PART_FILL_LVL                                                                     0x1080680UL //Access:R    DataWidth:0x3    // Input Arbiter Storm Task part FIFO fill level (in messages).
+#define YCM_REG_IA_TRANS_PART_FILL_LVL                                                                       0x1080684UL //Access:R    DataWidth:0x3    // Input Arbiter Transparent part FIFO fill level (in messages).
+#define YCM_REG_EXT_RD_FILL_LVL_E5                                                                           0x1080688UL //Access:R    DataWidth:0x2    // External read buffer FIFO fill level (in FIFO entries).
+#define YCM_REG_XX_MSG_UP_BND                                                                                0x1080704UL //Access:RW   DataWidth:0x7    // The maximum number of Xx RAM messages; which may be stored in XX protection. Is restricted by Xx Messages RAM size and the size of Xx protected message CM_REGISTERS_XX_MSG_SIZE.XX_MSG_SIZE
+#define YCM_REG_XX_MSG_SIZE                                                                                  0x1080708UL //Access:RW   DataWidth:0x5    // The size of Xx protected message in Xx Messages RAM in QREGs. Upper rounded to 4 and multiplied by CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND should not exceed XxMessagesRam size which is: MCM: 0d1792 PCM: 0d176 TCM: 0d1536 UCM: 0d1792 XCM: 0d256 YCM: 0d1536
+#define YCM_REG_XX_LCID_CAM_UP_BND                                                                           0x108070cUL //Access:RW   DataWidth:0x7    // The maximum number of connections in the XX protection LCID CAM.
+#define YCM_REG_XX_FREE_CNT                                                                                  0x1080710UL //Access:R    DataWidth:0x7    // Used to read the XX protection Free counter. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND
+#define YCM_REG_XX_LCID_CAM_FILL_LVL                                                                         0x1080714UL //Access:R    DataWidth:0x7    // Used to read XX protection LCID CAM fill level. Fill level is calculated as the number of locked LCIDs, i.e. LCIDs that have at least one Xx locked message or LCIDs that have no Xx locked messages but haven't been unlocked yet from LCID CAM. Simple saying it calculates for number of valid entries in LCID CAM.
+#define YCM_REG_XX_LCID_CAM_ST_STAT                                                                          0x1080718UL //Access:RC   DataWidth:0x7    // CAM occupancy sticky status. The write to the register is performed by the XX internal circuitry.
+#define YCM_REG_XX_IA_GROUP_PR0                                                                              0x108071cUL //Access:RW   DataWidth:0x1    // Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
+#define YCM_REG_XX_IA_GROUP_PR1                                                                              0x1080720UL //Access:RW   DataWidth:0x1    // Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
+#define YCM_REG_XX_NON_LOCK_LCID_THR                                                                         0x1080724UL //Access:RW   DataWidth:0x7    // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decision of Xx Input Arbiter non-locked group.
+#define YCM_REG_XX_LOCK_LCID_THR                                                                             0x1080728UL //Access:RW   DataWidth:0x7    // Xx locked LCIDs threshold (maximum value). Participates in Xx Bypass global enable decision.
+#define YCM_REG_XX_IA_ARB_SP_TIMEOUT                                                                         0x108072cUL //Access:RW   DataWidth:0x8    // Xx Input Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. E.g. bits[6:0]=0; bit[7]=0 - always strict priority; bits[6:0]=1; bit[7]=0 - strict priority; then RR; bits[6:0]=3; bit[7]=0 - 3 times strict priority; then RR.
+#define YCM_REG_XX_FREE_HEAD_PTR                                                                             0x1080730UL //Access:R    DataWidth:0x6    // Xx Free Head Pointer.
+#define YCM_REG_XX_FREE_TAIL_PTR                                                                             0x1080734UL //Access:R    DataWidth:0x6    // Xx Free Tail Pointer. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND
+#define YCM_REG_XX_NON_LOCK_CNT                                                                              0x1080738UL //Access:R    DataWidth:0x7    // Xx NonLock Counter.
+#define YCM_REG_XX_LOCK_CNT                                                                                  0x108073cUL //Access:R    DataWidth:0x7    // Xx Lock Counter.
+#define YCM_REG_XX_LCID_ARB_GROUP_PR0                                                                        0x1080740UL //Access:RW   DataWidth:0x2    // Xx LCID Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.
+#define YCM_REG_XX_LCID_ARB_GROUP_PR1                                                                        0x1080744UL //Access:RW   DataWidth:0x2    // Xx LCID Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.
+#define YCM_REG_XX_LCID_ARB_GROUP_PR2                                                                        0x1080748UL //Access:RW   DataWidth:0x2    // Xx LCID Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.
+#define YCM_REG_XX_LCID_ARB_SP_TIMEOUT                                                                       0x108074cUL //Access:RW   DataWidth:0x8    // Xx LCID Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. E.g. bits[6:0]=0; bit[7]=0 - always strict priority; bits[6:0]=1; bit[7]=0 - strict priority; then RR; bits[6:0]=3; bit[7]=0 - 3 times strict priority; then RR.
+#define YCM_REG_XX_FREE_THR_HIGH                                                                             0x1080750UL //Access:RW   DataWidth:0x7    // Xx free messages threshold high. Used in Xx Bypass global enable condition.
+#define YCM_REG_XX_FREE_THR_LOW                                                                              0x1080754UL //Access:RW   DataWidth:0x7    // Xx free messages threshold low Used in Xx Bypass global enable condition.
+#define YCM_REG_XX_CBYP_TBL_FILL_LVL                                                                         0x1080758UL //Access:R    DataWidth:0x4    // Xx Connection Bypass Table fill level (in connections).
+#define YCM_REG_XX_CBYP_TBL_ST_STAT                                                                          0x108075cUL //Access:RC   DataWidth:0x4    // Xx Connection Bypass Table sticky status. Reset on read.
+#define YCM_REG_XX_CBYP_TBL_UP_BND                                                                           0x1080760UL //Access:RW   DataWidth:0x4    // Xx Bypass Table (Connection) maximum fill level.
+#define YCM_REG_XX_TBYP_TBL_FILL_LVL                                                                         0x1080764UL //Access:R    DataWidth:0x7    // Xx Task Bypass Table fill level (in tasks).
+#define YCM_REG_XX_TBYP_TBL_ST_STAT                                                                          0x1080768UL //Access:RC   DataWidth:0x7    // Xx Task Bypass Table sticky status. Reset on read.
+#define YCM_REG_XX_TBYP_TBL_UP_BND                                                                           0x108076cUL //Access:RW   DataWidth:0x7    // Xx Bypass Table (Task) maximum fill level.
+#define YCM_REG_XX_BYP_LOCK_MSG_THR                                                                          0x1080790UL //Access:RW   DataWidth:0x6    // Xx Bypass messages lock threshold. The number of locked messages per LCID is above this threshold is one of conditions to start XxBypass for this LCID.
+#define YCM_REG_XX_PREF_DIR_FILL_LVL                                                                         0x1080794UL //Access:R    DataWidth:0x5    // Xx LCID Arbiter direct prefetch FIFO fill level (in entries).
+#define YCM_REG_XX_PREF_AGGST_FILL_LVL                                                                       0x1080798UL //Access:R    DataWidth:0x5    // Xx LCID Arbiter aggregation store prefetch FIFO fill level (in entries).
+#define YCM_REG_XX_PREF_BYP_FILL_LVL                                                                         0x108079cUL //Access:R    DataWidth:0x5    // Xx LCID Arbiter bypass prefetch FIFO fill level (in entries).
+#define YCM_REG_UNLOCK_MISS                                                                                  0x10807a0UL //Access:RC   DataWidth:0x1    // Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM.
+#define YCM_REG_ERR_AFFINITY_TYPE_E5                                                                         0x10807a4UL //Access:RW   DataWidth:0x2    // Affinity type in case of input message error.
+#define YCM_REG_ERR_EXCLUSIVE_FLG_E5                                                                         0x10807a8UL //Access:RW   DataWidth:0x1    // Exclusive type in case of input message error.
+#define YCM_REG_ERR_SRC_AFFINITY_E5                                                                          0x10807acUL //Access:RW   DataWidth:0x3    // Source affinity in case of input message error.
+#define YCM_REG_XX_BYP_MSG_UP_BND_0_BB_K2                                                                    0x1080770UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define YCM_REG_XX_BYP_MSG_UP_BND_0_E5                                                                       0x10807b0UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define YCM_REG_XX_BYP_MSG_UP_BND_1_BB_K2                                                                    0x1080774UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define YCM_REG_XX_BYP_MSG_UP_BND_1_E5                                                                       0x10807b4UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define YCM_REG_XX_BYP_MSG_UP_BND_2_BB_K2                                                                    0x1080778UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define YCM_REG_XX_BYP_MSG_UP_BND_2_E5                                                                       0x10807b8UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define YCM_REG_XX_BYP_MSG_UP_BND_3_BB_K2                                                                    0x108077cUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define YCM_REG_XX_BYP_MSG_UP_BND_3_E5                                                                       0x10807bcUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define YCM_REG_XX_BYP_MSG_UP_BND_4_BB_K2                                                                    0x1080780UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define YCM_REG_XX_BYP_MSG_UP_BND_4_E5                                                                       0x10807c0UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define YCM_REG_XX_BYP_MSG_UP_BND_5_BB_K2                                                                    0x1080784UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define YCM_REG_XX_BYP_MSG_UP_BND_5_E5                                                                       0x10807c4UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define YCM_REG_XX_BYP_MSG_UP_BND_6_BB_K2                                                                    0x1080788UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define YCM_REG_XX_BYP_MSG_UP_BND_6_E5                                                                       0x10807c8UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define YCM_REG_XX_BYP_MSG_UP_BND_7_BB_K2                                                                    0x108078cUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define YCM_REG_XX_BYP_MSG_UP_BND_7_E5                                                                       0x10807ccUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define YCM_REG_XX_BYP_MSG_UP_BND_8_E5                                                                       0x10807d0UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define YCM_REG_XX_BYP_MSG_UP_BND_9_E5                                                                       0x10807d4UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define YCM_REG_XX_BYP_MSG_UP_BND_10_E5                                                                      0x10807d8UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define YCM_REG_XX_BYP_MSG_UP_BND_11_E5                                                                      0x10807dcUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define YCM_REG_XX_BYP_MSG_UP_BND_12_E5                                                                      0x10807e0UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define YCM_REG_XX_BYP_MSG_UP_BND_13_E5                                                                      0x10807e4UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define YCM_REG_XX_BYP_MSG_UP_BND_14_E5                                                                      0x10807e8UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define YCM_REG_XX_BYP_MSG_UP_BND_15_E5                                                                      0x10807ecUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define YCM_REG_PRCS_AGG_CON_CURR_ST                                                                         0x1080804UL //Access:R    DataWidth:0x4    // Aggregation Connection Processor FSM.
+#define YCM_REG_PRCS_SM_CON_CURR_ST                                                                          0x1080808UL //Access:R    DataWidth:0x2    // STORM Connection Processor FSM.
+#define YCM_REG_PRCS_AGG_TASK_CURR_ST                                                                        0x108080cUL //Access:R    DataWidth:0x4    // Aggregation Task Processor FSM.
+#define YCM_REG_PRCS_SM_TASK_CURR_ST                                                                         0x1080810UL //Access:R    DataWidth:0x2    // STORM Task Processor FSM.
+#define YCM_REG_N_SM_TASK_CTX_LD_0                                                                           0x1080834UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define YCM_REG_N_SM_TASK_CTX_LD_1                                                                           0x1080838UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define YCM_REG_N_SM_TASK_CTX_LD_2                                                                           0x108083cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define YCM_REG_N_SM_TASK_CTX_LD_3                                                                           0x1080840UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define YCM_REG_N_SM_TASK_CTX_LD_4                                                                           0x1080844UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define YCM_REG_N_SM_TASK_CTX_LD_5                                                                           0x1080848UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define YCM_REG_N_SM_TASK_CTX_LD_6                                                                           0x108084cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define YCM_REG_N_SM_TASK_CTX_LD_7                                                                           0x1080850UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define YCM_REG_AGG_CON_FIC_BUF_FILL_LVL                                                                     0x1080854UL //Access:R    DataWidth:0x2    // Aggregation Connection FIC buffer fill level (in messages).
+#define YCM_REG_SM_CON_FIC_BUF_FILL_LVL                                                                      0x1080858UL //Access:R    DataWidth:0x4    // Storm Connection FIC buffer fill level (in messages).
+#define YCM_REG_AGG_CON_FIC_BUF_CRD                                                                          0x108085cUL //Access:RW   DataWidth:0x2    // Aggregation Connection FIC buffer credit (in full message out parts).
+#define YCM_REG_SM_CON_FIC_BUF_CRD                                                                           0x1080860UL //Access:RW   DataWidth:0x2    // Storm Connection FIC buffer credit (in full message out parts).
+#define YCM_REG_AGG_CON_BUF_CRD_AGG                                                                          0x1080864UL //Access:RW   DataWidth:0x3    // Aggregation Connection buffer (data or command) credit (Aggregation group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than Agregation Connection data buffer size=4. In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST and CM_REGISTERS_AGG_CON_CMD_BUF_CRD_DIR.AGG_CON_CMD_BUF_CRD_DIR need be no more than Agregation Connection command buffer size=6.
+#define YCM_REG_AGG_CON_BUF_CRD_AGGST                                                                        0x1080868UL //Access:RW   DataWidth:0x3    // Aggregation Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG need be no more than Agregation Connection data buffer size=4. In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG and CM_REGISTERS_AGG_CON_CMD_BUF_CRD_DIR.AGG_CON_CMD_BUF_CRD_DIR need be no more than Agregation Connection command buffer size=6.
+#define YCM_REG_SM_CON_BUF_CRD_AGGST                                                                         0x108086cUL //Access:RW   DataWidth:0x1    // Storm Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_CON_CMD_BUF_CRD_DIR.SM_CON_CMD_BUF_CRD_DIR need be no more than Storm Connection command buffer size=3.
+#define YCM_REG_AGG_CON_CMD_BUF_CRD_DIR                                                                      0x1080870UL //Access:RW   DataWidth:0x2    // Aggregation Connection command buffer credit (Direct group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG and XCM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than Agregation Connection command buffer size=6.
+#define YCM_REG_SM_CON_CMD_BUF_CRD_DIR                                                                       0x1080874UL //Access:RW   DataWidth:0x2    // Storm Connection command buffer credit (Direct group). In sum with CM_REGISTERS_SM_CON_BUF_CRD_AGGST.SM_CON_BUF_CRD_AGGST need be no more than Storm Connection command buffer size=3.
+#define YCM_REG_AGG_TASK_FIC_BUF_FILL_LVL                                                                    0x1080878UL //Access:R    DataWidth:0x2    // Aggregation Task FIC buffer fill level (in messages).
+#define YCM_REG_SM_TASK_FIC_BUF_FILL_LVL                                                                     0x108087cUL //Access:R    DataWidth:0x5    // Storm Task FIC buffer fill level (in messages).
+#define YCM_REG_AGG_TASK_FIC_BUF_CRD                                                                         0x1080880UL //Access:RW   DataWidth:0x2    // Aggregation Task FIC buffer credit (in full message out parts).
+#define YCM_REG_SM_TASK_FIC_BUF_CRD                                                                          0x1080884UL //Access:RW   DataWidth:0x2    // Storm Task FIC buffer credit (in full message out parts).
+#define YCM_REG_AGG_TASK_BUF_CRD_AGG                                                                         0x1080888UL //Access:RW   DataWidth:0x3    // Aggregation Task buffer (data or command) credit (Aggregation group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST need be no more than Agregation Task data buffer size=4. In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST and CM_REGISTERS_AGG_TASK_CMD_BUF_CRD_DIR.AGG_TASK_CMD_BUF_CRD_DIR need be no more than Agregation Task command buffer size=6.
+#define YCM_REG_AGG_TASK_BUF_CRD_AGGST                                                                       0x108088cUL //Access:RW   DataWidth:0x3    // Aggregation Task buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG need be no more than Agregation Task data buffer size=4. In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG and CM_REGISTERS_AGG_TASK_CMD_BUF_CRD_DIR.AGG_TASK_CMD_BUF_CRD_DIR need be no more than Agregation Task command buffer size=6.
+#define YCM_REG_SM_TASK_BUF_CRD_AGGST                                                                        0x1080890UL //Access:RW   DataWidth:0x1    // Storm Task buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_TASK_CMD_BUF_CRD_DIR.SM_TASK_CMD_BUF_CRD_DIR need be no more than Storm Task command buffer size=3.
+#define YCM_REG_AGG_TASK_CMD_BUF_CRD_DIR                                                                     0x1080894UL //Access:RW   DataWidth:0x2    // Aggregation Task command buffer credit (Direct group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG and CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST need be no more than Agregation Task command buffer size=6.
+#define YCM_REG_SM_TASK_CMD_BUF_CRD_DIR                                                                      0x1080898UL //Access:RW   DataWidth:0x2    // Storm Task command buffer credit (Direct group). In sum with CM_REGISTERS_SM_TASK_BUF_CRD_AGGST.SM_TASK_BUF_CRD_AGGST need be no more than Storm Task command buffer size=3.
+#define YCM_REG_TRANS_DATA_BUF_CRD_DIR                                                                       0x108089cUL //Access:RW   DataWidth:0x2    // Transparent data buffer credit (Direct group).
+#define YCM_REG_AGG_TASK_CTX_SIZE_0                                                                          0x10808c0UL //Access:RW   DataWidth:0x2    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define YCM_REG_AGG_TASK_CTX_SIZE_1                                                                          0x10808c4UL //Access:RW   DataWidth:0x2    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define YCM_REG_AGG_TASK_CTX_SIZE_2                                                                          0x10808c8UL //Access:RW   DataWidth:0x2    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define YCM_REG_AGG_TASK_CTX_SIZE_3                                                                          0x10808ccUL //Access:RW   DataWidth:0x2    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define YCM_REG_AGG_TASK_CTX_SIZE_4                                                                          0x10808d0UL //Access:RW   DataWidth:0x2    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define YCM_REG_AGG_TASK_CTX_SIZE_5                                                                          0x10808d4UL //Access:RW   DataWidth:0x2    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define YCM_REG_AGG_TASK_CTX_SIZE_6                                                                          0x10808d8UL //Access:RW   DataWidth:0x2    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define YCM_REG_AGG_TASK_CTX_SIZE_7                                                                          0x10808dcUL //Access:RW   DataWidth:0x2    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define YCM_REG_SM_CON_CTX_SIZE                                                                              0x10808e0UL //Access:RW   DataWidth:0x4    // STORM Connnection context per LCID size (REGQ). Default context size of 3 (REGQ) complies to 320 LCIDs. Maximum context size per LCID is 12. Maximum number of LCIDs allowed at maximum context size per LCID is 52. If not at default value need to be 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER((320*INTEGER(3/2))/(12/2)).
+#define YCM_REG_SM_TASK_CTX_SIZE                                                                             0x10808e4UL //Access:RW   DataWidth:0x5    // STORM Task context per LTID size (REGQ). Default context size of 12 (REGQ) complies to 320 LTIDs. Maximum context size per LTID is 20. Maximum number of LTIDs allowed at maximum context size per LTID is 128. If not at default value need to be 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER((320*INTEGER(12/2))/(20/2)).
+#define YCM_REG_CON_PHY_Q0                                                                                   0x1080904UL //Access:RW   DataWidth:0x9    // Physical queue connection number (queue number 0).
+#define YCM_REG_CON_PHY_Q1                                                                                   0x1080908UL //Access:RW   DataWidth:0x9    // Physical queue connection number (queue number 1).
+#define YCM_REG_TASK_PHY_Q0                                                                                  0x108090cUL //Access:RW   DataWidth:0x7    // Physical queue task number (queue number 0).
+#define YCM_REG_TASK_PHY_Q1                                                                                  0x1080910UL //Access:RW   DataWidth:0x7    // Physical queue task number (queue number 1).
+#define YCM_REG_AGG_CON_RULE0_Q                                                                              0x1080920UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define YCM_REG_AGG_CON_RULE1_Q                                                                              0x1080924UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define YCM_REG_AGG_CON_RULE2_Q                                                                              0x1080928UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define YCM_REG_AGG_CON_RULE3_Q                                                                              0x108092cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define YCM_REG_AGG_CON_RULE4_Q                                                                              0x1080930UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define YCM_REG_AGG_TASK_RULE0_Q_BB_K2                                                                       0x108093cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define YCM_REG_AGG_TASK_RULE0_Q_E5                                                                          0x1080944UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define YCM_REG_AGG_TASK_RULE1_Q_BB_K2                                                                       0x1080940UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define YCM_REG_AGG_TASK_RULE1_Q_E5                                                                          0x1080948UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define YCM_REG_AGG_TASK_RULE2_Q_BB_K2                                                                       0x1080944UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define YCM_REG_AGG_TASK_RULE2_Q_E5                                                                          0x108094cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define YCM_REG_AGG_TASK_RULE3_Q_BB_K2                                                                       0x1080948UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define YCM_REG_AGG_TASK_RULE3_Q_E5                                                                          0x1080950UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define YCM_REG_AGG_TASK_RULE4_Q_BB_K2                                                                       0x108094cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define YCM_REG_AGG_TASK_RULE4_Q_E5                                                                          0x1080954UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define YCM_REG_AGG_TASK_RULE5_Q_BB_K2                                                                       0x1080950UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define YCM_REG_AGG_TASK_RULE5_Q_E5                                                                          0x1080958UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define YCM_REG_AGG_TASK_RULE6_Q_BB_K2                                                                       0x1080954UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define YCM_REG_AGG_TASK_RULE6_Q_E5                                                                          0x108095cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define YCM_REG_AGG_TASK_RULE7_Q_E5                                                                          0x1080960UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define YCM_REG_CM_TASK_EVENT_ID_BWIDTH_0_E5                                                                 0x1080964UL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define YCM_REG_CM_TASK_EVENT_ID_BWIDTH_1_E5                                                                 0x1080968UL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define YCM_REG_CM_TASK_EVENT_ID_BWIDTH_2_E5                                                                 0x108096cUL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define YCM_REG_CM_TASK_EVENT_ID_BWIDTH_3_E5                                                                 0x1080970UL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define YCM_REG_CM_TASK_EVENT_ID_BWIDTH_4_E5                                                                 0x1080974UL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define YCM_REG_CM_TASK_EVENT_ID_BWIDTH_5_E5                                                                 0x1080978UL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define YCM_REG_CM_TASK_EVENT_ID_BWIDTH_6_E5                                                                 0x108097cUL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define YCM_REG_CM_TASK_EVENT_ID_BWIDTH_7_E5                                                                 0x1080980UL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define YCM_REG_IN_PRCS_TBL_CRD_AGG                                                                          0x1080a04UL //Access:RW   DataWidth:0x4    // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.IN_PRCS_TBL_CRD_AGGST need be no more than In-process table size=12.
+#define YCM_REG_IN_PRCS_TBL_CRD_AGGST                                                                        0x1080a08UL //Access:RW   DataWidth:0x4    // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGG.IN_PRCS_TBL_CRD_AGG need be no more than In-process table size=12.
+#define YCM_REG_IN_PRCS_TBL_FILL_LVL                                                                         0x1080a0cUL //Access:R    DataWidth:0x4    // In-process Table fill level  (in messages).
+#define YCM_REG_IN_PRCS_TBL_ALMOST_FULL                                                                      0x1080a10UL //Access:R    DataWidth:0x1    // In-process Table almost full.
+#define YCM_REG_QMCON_CURR_ST                                                                                0x1080a14UL //Access:R    DataWidth:0x3    // QM connection registration FSM current state.
+#define YCM_REG_QMTASK_CURR_ST                                                                               0x1080a18UL //Access:R    DataWidth:0x3    // QM task registration FSM current state.
+#define YCM_REG_CCFC_CURR_ST                                                                                 0x1080a1cUL //Access:R    DataWidth:0x1    // CFC connection output FSM current state.
+#define YCM_REG_TCFC_CURR_ST                                                                                 0x1080a20UL //Access:R    DataWidth:0x1    // CFC task output FSM current state.
+#define YCM_REG_CMPL_DIR_CURR_ST                                                                             0x1080a24UL //Access:R    DataWidth:0x4    // Direct Completer FSM current state.
+#define YCM_REG_XX_BYP_CON_STATE_EVNT_ID_FLG                                                                 0x1080a28UL //Access:RW   DataWidth:0x1    // If set, Xx connection bypass state will be added in calculation of CM output Event ID.
+#define YCM_REG_XX_BYP_TASK_STATE_EVNT_ID_FLG                                                                0x1080a2cUL //Access:RW   DataWidth:0x1    // If set, Xx task bypass state will be added in calculation of CM output Event ID.
+#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_0_E5                                                                  0x1080a30UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_1_E5                                                                  0x1080a34UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_2_E5                                                                  0x1080a38UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_3_E5                                                                  0x1080a3cUL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_4_E5                                                                  0x1080a40UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_5_E5                                                                  0x1080a44UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_6_E5                                                                  0x1080a48UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_7_E5                                                                  0x1080a4cUL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_8_E5                                                                  0x1080a50UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_9_E5                                                                  0x1080a54UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_10_E5                                                                 0x1080a58UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_11_E5                                                                 0x1080a5cUL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_12_E5                                                                 0x1080a60UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_13_E5                                                                 0x1080a64UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_14_E5                                                                 0x1080a68UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_15_E5                                                                 0x1080a6cUL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define YCM_REG_CCFC_INIT_CRD                                                                                0x1080a84UL //Access:RW   DataWidth:0x4    // CCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.
+#define YCM_REG_TCFC_INIT_CRD                                                                                0x1080a88UL //Access:RW   DataWidth:0x4    // TCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.
+#define YCM_REG_QM_INIT_CRD0                                                                                 0x1080a8cUL //Access:RW   DataWidth:0x5    // QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 16.Write writes the initial credit value; read returns the current value of the credit counter.
+#define YCM_REG_TCFC_INCLOCK_INIT_CRD                                                                        0x1080a90UL //Access:RW   DataWidth:0x1    // TCFC UC Inc/Lock Update output initial credit. Max credit available - 1.Write writes the initial credit value; read returns the current value of the credit counter.
+#define YCM_REG_TCFC_DEC_INIT_CRD                                                                            0x1080a94UL //Access:RW   DataWidth:0x3    // TCFC UC Dec Update output initial credit. Max credit available - 7.Write writes the initial credit value; read returns the current value of the credit counter.
+#define YCM_REG_FIC_INIT_CRD                                                                                 0x1080a98UL //Access:RW   DataWidth:0x6    // FIC output initial credit. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 44 at start-up.
+#define YCM_REG_DIR_BYP_MSG_CNT                                                                              0x1080aa4UL //Access:RC   DataWidth:0x20   // Counter of direct bypassed messages.
+#define YCM_REG_YSDM_LENGTH_MIS                                                                              0x1080aacUL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at YSDM interface.
+#define YCM_REG_PBF_LENGTH_MIS                                                                               0x1080ab0UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at PBF interface.
+#define YCM_REG_XYLD_LENGTH_MIS                                                                              0x1080ab4UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at XYLD interface.
+#define YCM_REG_GRC_BUF_EMPTY                                                                                0x1080ab8UL //Access:R    DataWidth:0x1    // Input Stage GRC buffer is empty.
+#define YCM_REG_GRC_BUF_STATUS                                                                               0x1080abcUL //Access:R    DataWidth:0x6    // Input Stage GRC buffer status.
+#define YCM_REG_STORM_MSG_CNTR                                                                               0x1080ac0UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the STORM input.
+#define YCM_REG_YSDM_MSG_CNTR                                                                                0x1080ac8UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input YSDM.
+#define YCM_REG_XYLD_MSG_CNTR                                                                                0x1080accUL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input XYLD.
+#define YCM_REG_MSEM_MSG_CNTR                                                                                0x1080ad0UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input MSEM.
+#define YCM_REG_USEM_MSG_CNTR                                                                                0x1080ad4UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at input USEM.
+#define YCM_REG_PBF_MSG_CNTR                                                                                 0x1080ad8UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at input PBF.
+#define YCM_REG_QM_P_MSG_CNTR                                                                                0x1080adcUL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the QM input (primary).
+#define YCM_REG_QM_S_MSG_CNTR                                                                                0x1080ae0UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the QM input (secondary).
+#define YCM_REG_IS_GRC                                                                                       0x1080ae4UL //Access:W    DataWidth:0x20   // Used to write the GRC message. Write only. To distinguish if the register can be accessed to write GRC message                           polling of CM_REGISTERS.GRC_BUF_EMPTY need to be done
+#define YCM_REG_IS_QM_P_FILL_LVL                                                                             0x1080ae8UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in QM Primary Input Stage (except of bypass).
+#define YCM_REG_IS_QM_S_FILL_LVL                                                                             0x1080aecUL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in QM Secondary Input Stage (except of bypass).
+#define YCM_REG_IS_STORM_FILL_LVL                                                                            0x1080af0UL //Access:R    DataWidth:0x5    // Number of entries (2 QREGs each) of data in STORM Input Stage.
+#define YCM_REG_IS_YSDM_FILL_LVL                                                                             0x1080af8UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in YSDM Input Stage.
+#define YCM_REG_IS_XYLD_FILL_LVL                                                                             0x1080afcUL //Access:R    DataWidth:0x5    // Number of QREGs (128b) of data in XYLD Input Stage.
+#define YCM_REG_IS_MSEM_FILL_LVL                                                                             0x1080b00UL //Access:R    DataWidth:0x4    // Number of QREGs (128b) in TCM, YCM or 2 QREGs (256b) in XCM of data in MSEM Input Stage.
+#define YCM_REG_IS_USEM_FILL_LVL                                                                             0x1080b04UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in USEM Input Stage.
+#define YCM_REG_IS_PBF_FILL_LVL                                                                              0x1080b08UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in PBF Input Stage.
+#define YCM_REG_FIC_MSG_CNTR                                                                                 0x1080b44UL //Access:RC   DataWidth:0x1c   // Counter of the output messages at FIC interfaces.
+#define YCM_REG_QM_OUT_CNTR                                                                                  0x1080b48UL //Access:RC   DataWidth:0x1c   // Counter of the output QM commands.
+#define YCM_REG_DONE0_CNTR                                                                                   0x1080b4cUL //Access:RC   DataWidth:0x1c   // Counter of the output Done0.
+#define YCM_REG_DONE1_CNTR                                                                                   0x1080b50UL //Access:RC   DataWidth:0x1c   // Counter of the output Done1.
+#define YCM_REG_DONE2_CNTR                                                                                   0x1080b54UL //Access:RC   DataWidth:0x1c   // Counter of the output Done2.
+#define YCM_REG_DONE3_CNTR                                                                                   0x1080b58UL //Access:RC   DataWidth:0x1c   // Counter of the output Done3.
+#define YCM_REG_CCFC_CNTR                                                                                    0x1080b5cUL //Access:RC   DataWidth:0x1c   // Counter of the output CCFC.
+#define YCM_REG_TCFC_CNTR                                                                                    0x1080b60UL //Access:RC   DataWidth:0x1c   // Counter of the output TCFC.
+#define YCM_REG_ECO_RESERVED                                                                                 0x1080b84UL //Access:RW   DataWidth:0x8    // Chicken bits.
+#define YCM_REG_IS_FOC_MSEM_NXT_INF_UNIT                                                                     0x1080b88UL //Access:R    DataWidth:0x6    // Debug read from MSEM Input stage buffer: number of reads to next information unit.
+#define YCM_REG_IS_FOC_USEM_NXT_INF_UNIT                                                                     0x1080b8cUL //Access:R    DataWidth:0x6    // Debug read from USEM Input stage buffer: number of reads to next information unit.
+#define YCM_REG_IS_FOC_PBF_NXT_INF_UNIT                                                                      0x1080b94UL //Access:R    DataWidth:0x6    // Debug read from PBF Input stage buffer: number of reads to next information unit.
+#define YCM_REG_IS_FOC_YSDM_NXT_INF_UNIT                                                                     0x1080b9cUL //Access:R    DataWidth:0x6    // Debug read from YSDM Input stage buffer: number of reads to next information unit.
+#define YCM_REG_IS_FOC_XYLD_NXT_INF_UNIT                                                                     0x1080ba0UL //Access:R    DataWidth:0x5    // Debug read from XYLD Input stage buffer: number of reads to next information unit.
+#define YCM_REG_IS_FOC_MSEM                                                                                  0x1080c00UL //Access:R    DataWidth:0x20   // Debug read from MSEM Input stage buffer with 32-bits granularity. Read only.
+#define YCM_REG_IS_FOC_MSEM_SIZE                                                                             32
+#define YCM_REG_IS_FOC_USEM                                                                                  0x1080c80UL //Access:R    DataWidth:0x20   // Debug read from USEM Input stage buffer with 32-bits granularity. Read only.
+#define YCM_REG_IS_FOC_USEM_SIZE                                                                             12
+#define YCM_REG_IS_FOC_PBF                                                                                   0x1081400UL //Access:R    DataWidth:0x20   // Debug read from PBF Input stage buffer with 32-bits granularity. Read only.
+#define YCM_REG_IS_FOC_PBF_SIZE                                                                              24
+#define YCM_REG_IS_FOC_YSDM                                                                                  0x1081500UL //Access:R    DataWidth:0x20   // Debug read from YSDM Input stage buffer with 32-bits granularity. Read only.
+#define YCM_REG_IS_FOC_YSDM_SIZE                                                                             16
+#define YCM_REG_CTX_RBC_ACCS                                                                                 0x1081800UL //Access:RW   DataWidth:0x10   // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - offset (in REGs (32b)) within LCID/LTID. The procedure to read context is: first define base address and offset; then read context with one of the following registers: CM_REGISTERS_AGG_CON_CTX.AGG_CON_CTX CM_REGISTERS_SM_CON_CTX.SM_CON_CTX CM_REGISTERS_AGG_TASK_CTX.AGG_TASK_CTX CM_REGISTERS_SM_TASK_CTX.SM_TASK_CTX
+#define YCM_REG_AGG_CON_CTX                                                                                  0x1081804UL //Access:RW   DataWidth:0x20   // Access is allowed only on idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The address base (LCID) and offset within LCID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to Aggregation Connection context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.
+#define YCM_REG_AGG_TASK_CTX                                                                                 0x1081808UL //Access:RW   DataWidth:0x20   // Access is allowed only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The address base (LTID) and offset within LTID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to Aggregation Task context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.
+#define YCM_REG_SM_CON_CTX                                                                                   0x108180cUL //Access:RW   DataWidth:0x20   // Access is allowed only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The address base (LCID) and offset within LCID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to STORM Connection context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.
+#define YCM_REG_SM_TASK_CTX                                                                                  0x1081810UL //Access:RW   DataWidth:0x20   // Access is allowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The address base (LTID) and offset within LTID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to STORM Task context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.
+#define YCM_REG_XX_CBYP_TBL                                                                                  0x1081820UL //Access:R    DataWidth:0xf    // Xx Connection Bypass Table.
+#define YCM_REG_XX_CBYP_TBL_SIZE                                                                             8
+#define YCM_REG_XX_TBYP_TBL                                                                                  0x1081900UL //Access:R    DataWidth:0xf    // Xx Task Bypass Table.
+#define YCM_REG_XX_TBYP_TBL_SIZE_BB_K2                                                                       22
+#define YCM_REG_XX_TBYP_TBL_SIZE_E5                                                                          64
+#define YCM_REG_XX_LCID_CAM                                                                                  0x1081a00UL //Access:R    DataWidth:0xa    // Debug only. Read only access to LCID CAM in XX protection mechanism.
+#define YCM_REG_XX_LCID_CAM_SIZE_BB_K2                                                                       22
+#define YCM_REG_XX_LCID_CAM_SIZE_E5                                                                          64
+#define YCM_REG_XX_TBL                                                                                       0x1081b00UL //Access:R    DataWidth:0x18   // Indirect access to the XX table of the XX protection mechanism. The fields are: [0] - Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: PCM - [9:8]; M/T/U/X/YCM - [17:12]; Next pointer: PCM - [11:10]; M/T/U/X/YCM - [23:18];
+#define YCM_REG_XX_TBL_SIZE_BB_K2                                                                            22
+#define YCM_REG_XX_TBL_SIZE_E5                                                                               64
+#define YCM_REG_XX_DSCR_TBL                                                                                  0x1081c00UL //Access:RW   DataWidth:0x1e   // Indirect access to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [13:9];PCM [14:9]; TCM [13:9]; UCM [13:9];XCM [10:9];YCM[13:9]); Next pointer (MCM [19:14]; PCM [16:15]; TCM[19:14]; UCM [19:14]; XCM [16:11]; YCM [19:14]); LTID (MCM [28:20]; PCM [25:17] - reserved; TCM[28:20]; UCM [28:20]; XCM [25:17] - reserved; YCM [28:20]). Task Domain Exist (MCM [29]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - reserved; YCM [29]). A free link list in the XX descriptor table should be build. This is done by writing the following values to all effective entries in the table:xx_descr_table[i].next_pointer = i+1 (i=0 - (xx_msg_up_bnd-2)); xx_descr_table[i].next_pointer= 0 (i=xx_msg_up_bnd-1). The value of i is between 0 to the configured (not default) value of (xx_msg_up_bnd-1). The not effective entries (those which succeed the last effective entry with index (xx_msg_up_bnd-1)) can be initialized to any value for initialization procedure simplicity seek.
+#define YCM_REG_XX_DSCR_TBL_SIZE                                                                             64
+#define YCM_REG_N_SM_CON_CTX_LD_0_BB_K2                                                                      0x1080814UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define YCM_REG_N_SM_CON_CTX_LD_0_E5                                                                         0x1081d00UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define YCM_REG_N_SM_CON_CTX_LD_1_BB_K2                                                                      0x1080818UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define YCM_REG_N_SM_CON_CTX_LD_1_E5                                                                         0x1081d04UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define YCM_REG_N_SM_CON_CTX_LD_2_BB_K2                                                                      0x108081cUL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define YCM_REG_N_SM_CON_CTX_LD_2_E5                                                                         0x1081d08UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define YCM_REG_N_SM_CON_CTX_LD_3_BB_K2                                                                      0x1080820UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define YCM_REG_N_SM_CON_CTX_LD_3_E5                                                                         0x1081d0cUL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define YCM_REG_N_SM_CON_CTX_LD_4_BB_K2                                                                      0x1080824UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define YCM_REG_N_SM_CON_CTX_LD_4_E5                                                                         0x1081d10UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define YCM_REG_N_SM_CON_CTX_LD_5_BB_K2                                                                      0x1080828UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define YCM_REG_N_SM_CON_CTX_LD_5_E5                                                                         0x1081d14UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define YCM_REG_N_SM_CON_CTX_LD_6_BB_K2                                                                      0x108082cUL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define YCM_REG_N_SM_CON_CTX_LD_6_E5                                                                         0x1081d18UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define YCM_REG_N_SM_CON_CTX_LD_7_BB_K2                                                                      0x1080830UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define YCM_REG_N_SM_CON_CTX_LD_7_E5                                                                         0x1081d1cUL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define YCM_REG_N_SM_CON_CTX_LD_8_E5                                                                         0x1081d20UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define YCM_REG_N_SM_CON_CTX_LD_9_E5                                                                         0x1081d24UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define YCM_REG_N_SM_CON_CTX_LD_10_E5                                                                        0x1081d28UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 10).
+#define YCM_REG_N_SM_CON_CTX_LD_11_E5                                                                        0x1081d2cUL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define YCM_REG_N_SM_CON_CTX_LD_12_E5                                                                        0x1081d30UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define YCM_REG_N_SM_CON_CTX_LD_13_E5                                                                        0x1081d34UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define YCM_REG_N_SM_CON_CTX_LD_14_E5                                                                        0x1081d38UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define YCM_REG_N_SM_CON_CTX_LD_15_E5                                                                        0x1081d3cUL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define YCM_REG_AGG_CON_CTX_SIZE_0_BB_K2                                                                     0x10808a0UL //Access:RW   DataWidth:0x2    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less or 0.
+#define YCM_REG_AGG_CON_CTX_SIZE_0_E5                                                                        0x1081d40UL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.
+#define YCM_REG_AGG_CON_CTX_SIZE_1_BB_K2                                                                     0x10808a4UL //Access:RW   DataWidth:0x2    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.
+#define YCM_REG_AGG_CON_CTX_SIZE_1_E5                                                                        0x1081d44UL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.
+#define YCM_REG_AGG_CON_CTX_SIZE_2_BB_K2                                                                     0x10808a8UL //Access:RW   DataWidth:0x2    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.
+#define YCM_REG_AGG_CON_CTX_SIZE_2_E5                                                                        0x1081d48UL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.
+#define YCM_REG_AGG_CON_CTX_SIZE_3_BB_K2                                                                     0x10808acUL //Access:RW   DataWidth:0x2    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.
+#define YCM_REG_AGG_CON_CTX_SIZE_3_E5                                                                        0x1081d4cUL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.
+#define YCM_REG_AGG_CON_CTX_SIZE_4_BB_K2                                                                     0x10808b0UL //Access:RW   DataWidth:0x2    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.
+#define YCM_REG_AGG_CON_CTX_SIZE_4_E5                                                                        0x1081d50UL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.
+#define YCM_REG_AGG_CON_CTX_SIZE_5_BB_K2                                                                     0x10808b4UL //Access:RW   DataWidth:0x2    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.
+#define YCM_REG_AGG_CON_CTX_SIZE_5_E5                                                                        0x1081d54UL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.
+#define YCM_REG_AGG_CON_CTX_SIZE_6_BB_K2                                                                     0x10808b8UL //Access:RW   DataWidth:0x2    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.
+#define YCM_REG_AGG_CON_CTX_SIZE_6_E5                                                                        0x1081d58UL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.
+#define YCM_REG_AGG_CON_CTX_SIZE_7_BB_K2                                                                     0x10808bcUL //Access:RW   DataWidth:0x2    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.
+#define YCM_REG_AGG_CON_CTX_SIZE_7_E5                                                                        0x1081d5cUL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.
+#define YCM_REG_AGG_CON_CTX_SIZE_8_E5                                                                        0x1081d60UL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less or 0.
+#define YCM_REG_AGG_CON_CTX_SIZE_9_E5                                                                        0x1081d64UL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.
+#define YCM_REG_AGG_CON_CTX_SIZE_10_E5                                                                       0x1081d68UL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.
+#define YCM_REG_AGG_CON_CTX_SIZE_11_E5                                                                       0x1081d6cUL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.
+#define YCM_REG_AGG_CON_CTX_SIZE_12_E5                                                                       0x1081d70UL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.
+#define YCM_REG_AGG_CON_CTX_SIZE_13_E5                                                                       0x1081d74UL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.
+#define YCM_REG_AGG_CON_CTX_SIZE_14_E5                                                                       0x1081d78UL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.
+#define YCM_REG_AGG_CON_CTX_SIZE_15_E5                                                                       0x1081d7cUL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.
+#define YCM_REG_QM_CON_BASE_EVNT_ID_0_BB_K2                                                                  0x1080404UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define YCM_REG_QM_CON_BASE_EVNT_ID_0_E5                                                                     0x1081d80UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define YCM_REG_QM_CON_BASE_EVNT_ID_1_BB_K2                                                                  0x1080408UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define YCM_REG_QM_CON_BASE_EVNT_ID_1_E5                                                                     0x1081d84UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define YCM_REG_QM_CON_BASE_EVNT_ID_2_BB_K2                                                                  0x108040cUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define YCM_REG_QM_CON_BASE_EVNT_ID_2_E5                                                                     0x1081d88UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define YCM_REG_QM_CON_BASE_EVNT_ID_3_BB_K2                                                                  0x1080410UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define YCM_REG_QM_CON_BASE_EVNT_ID_3_E5                                                                     0x1081d8cUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define YCM_REG_QM_CON_BASE_EVNT_ID_4_BB_K2                                                                  0x1080414UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define YCM_REG_QM_CON_BASE_EVNT_ID_4_E5                                                                     0x1081d90UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define YCM_REG_QM_CON_BASE_EVNT_ID_5_BB_K2                                                                  0x1080418UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define YCM_REG_QM_CON_BASE_EVNT_ID_5_E5                                                                     0x1081d94UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define YCM_REG_QM_CON_BASE_EVNT_ID_6_BB_K2                                                                  0x108041cUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define YCM_REG_QM_CON_BASE_EVNT_ID_6_E5                                                                     0x1081d98UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define YCM_REG_QM_CON_BASE_EVNT_ID_7_BB_K2                                                                  0x1080420UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define YCM_REG_QM_CON_BASE_EVNT_ID_7_E5                                                                     0x1081d9cUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define YCM_REG_QM_CON_BASE_EVNT_ID_8_E5                                                                     0x1081da0UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define YCM_REG_QM_CON_BASE_EVNT_ID_9_E5                                                                     0x1081da4UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define YCM_REG_QM_CON_BASE_EVNT_ID_10_E5                                                                    0x1081da8UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define YCM_REG_QM_CON_BASE_EVNT_ID_11_E5                                                                    0x1081dacUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define YCM_REG_QM_CON_BASE_EVNT_ID_12_E5                                                                    0x1081db0UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define YCM_REG_QM_CON_BASE_EVNT_ID_13_E5                                                                    0x1081db4UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define YCM_REG_QM_CON_BASE_EVNT_ID_14_E5                                                                    0x1081db8UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define YCM_REG_QM_CON_BASE_EVNT_ID_15_E5                                                                    0x1081dbcUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_0_BB_K2                                                             0x1080444UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_0_E5                                                                0x1081dc0UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_1_BB_K2                                                             0x1080448UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_1_E5                                                                0x1081dc4UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_2_BB_K2                                                             0x108044cUL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_2_E5                                                                0x1081dc8UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_3_BB_K2                                                             0x1080450UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_3_E5                                                                0x1081dccUL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_4_BB_K2                                                             0x1080454UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_4_E5                                                                0x1081dd0UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_5_BB_K2                                                             0x1080458UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_5_E5                                                                0x1081dd4UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_6_BB_K2                                                             0x108045cUL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_6_E5                                                                0x1081dd8UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_7_BB_K2                                                             0x1080460UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_7_E5                                                                0x1081ddcUL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_8_E5                                                                0x1081de0UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_9_E5                                                                0x1081de4UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_10_E5                                                               0x1081de8UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_11_E5                                                               0x1081decUL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_12_E5                                                               0x1081df0UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_13_E5                                                               0x1081df4UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_14_E5                                                               0x1081df8UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_15_E5                                                               0x1081dfcUL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define YCM_REG_QM_XXLOCK_CMD_0_BB_K2                                                                        0x1080504UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define YCM_REG_QM_XXLOCK_CMD_0_E5                                                                           0x1081e00UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define YCM_REG_QM_XXLOCK_CMD_1_BB_K2                                                                        0x1080508UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define YCM_REG_QM_XXLOCK_CMD_1_E5                                                                           0x1081e04UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define YCM_REG_QM_XXLOCK_CMD_2_BB_K2                                                                        0x108050cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define YCM_REG_QM_XXLOCK_CMD_2_E5                                                                           0x1081e08UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define YCM_REG_QM_XXLOCK_CMD_3_BB_K2                                                                        0x1080510UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define YCM_REG_QM_XXLOCK_CMD_3_E5                                                                           0x1081e0cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define YCM_REG_QM_XXLOCK_CMD_4_BB_K2                                                                        0x1080514UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define YCM_REG_QM_XXLOCK_CMD_4_E5                                                                           0x1081e10UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define YCM_REG_QM_XXLOCK_CMD_5_BB_K2                                                                        0x1080518UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define YCM_REG_QM_XXLOCK_CMD_5_E5                                                                           0x1081e14UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define YCM_REG_QM_XXLOCK_CMD_6_BB_K2                                                                        0x108051cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define YCM_REG_QM_XXLOCK_CMD_6_E5                                                                           0x1081e18UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define YCM_REG_QM_XXLOCK_CMD_7_BB_K2                                                                        0x1080520UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define YCM_REG_QM_XXLOCK_CMD_7_E5                                                                           0x1081e1cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define YCM_REG_QM_XXLOCK_CMD_8_E5                                                                           0x1081e20UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define YCM_REG_QM_XXLOCK_CMD_9_E5                                                                           0x1081e24UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define YCM_REG_QM_XXLOCK_CMD_10_E5                                                                          0x1081e28UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define YCM_REG_QM_XXLOCK_CMD_11_E5                                                                          0x1081e2cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define YCM_REG_QM_XXLOCK_CMD_12_E5                                                                          0x1081e30UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define YCM_REG_QM_XXLOCK_CMD_13_E5                                                                          0x1081e34UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define YCM_REG_QM_XXLOCK_CMD_14_E5                                                                          0x1081e38UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define YCM_REG_QM_XXLOCK_CMD_15_E5                                                                          0x1081e3cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define YCM_REG_QM_CON_USE_ST_FLG_0_BB_K2                                                                    0x1080524UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define YCM_REG_QM_CON_USE_ST_FLG_0_E5                                                                       0x1081e40UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define YCM_REG_QM_CON_USE_ST_FLG_1_BB_K2                                                                    0x1080528UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define YCM_REG_QM_CON_USE_ST_FLG_1_E5                                                                       0x1081e44UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define YCM_REG_QM_CON_USE_ST_FLG_2_BB_K2                                                                    0x108052cUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define YCM_REG_QM_CON_USE_ST_FLG_2_E5                                                                       0x1081e48UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define YCM_REG_QM_CON_USE_ST_FLG_3_BB_K2                                                                    0x1080530UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define YCM_REG_QM_CON_USE_ST_FLG_3_E5                                                                       0x1081e4cUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define YCM_REG_QM_CON_USE_ST_FLG_4_BB_K2                                                                    0x1080534UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define YCM_REG_QM_CON_USE_ST_FLG_4_E5                                                                       0x1081e50UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define YCM_REG_QM_CON_USE_ST_FLG_5_BB_K2                                                                    0x1080538UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define YCM_REG_QM_CON_USE_ST_FLG_5_E5                                                                       0x1081e54UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define YCM_REG_QM_CON_USE_ST_FLG_6_BB_K2                                                                    0x108053cUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define YCM_REG_QM_CON_USE_ST_FLG_6_E5                                                                       0x1081e58UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define YCM_REG_QM_CON_USE_ST_FLG_7_BB_K2                                                                    0x1080540UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define YCM_REG_QM_CON_USE_ST_FLG_7_E5                                                                       0x1081e5cUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define YCM_REG_QM_CON_USE_ST_FLG_8_E5                                                                       0x1081e60UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define YCM_REG_QM_CON_USE_ST_FLG_9_E5                                                                       0x1081e64UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define YCM_REG_QM_CON_USE_ST_FLG_10_E5                                                                      0x1081e68UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define YCM_REG_QM_CON_USE_ST_FLG_11_E5                                                                      0x1081e6cUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define YCM_REG_QM_CON_USE_ST_FLG_12_E5                                                                      0x1081e70UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define YCM_REG_QM_CON_USE_ST_FLG_13_E5                                                                      0x1081e74UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define YCM_REG_QM_CON_USE_ST_FLG_14_E5                                                                      0x1081e78UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define YCM_REG_QM_CON_USE_ST_FLG_15_E5                                                                      0x1081e7cUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define YCM_REG_QM_SM_CON_CTX_LDST_FLG_0_BB_K2                                                               0x1080464UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define YCM_REG_QM_SM_CON_CTX_LDST_FLG_0_E5                                                                  0x1081e80UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define YCM_REG_QM_SM_CON_CTX_LDST_FLG_1_BB_K2                                                               0x1080468UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define YCM_REG_QM_SM_CON_CTX_LDST_FLG_1_E5                                                                  0x1081e84UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define YCM_REG_QM_SM_CON_CTX_LDST_FLG_2_BB_K2                                                               0x108046cUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define YCM_REG_QM_SM_CON_CTX_LDST_FLG_2_E5                                                                  0x1081e88UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define YCM_REG_QM_SM_CON_CTX_LDST_FLG_3_BB_K2                                                               0x1080470UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define YCM_REG_QM_SM_CON_CTX_LDST_FLG_3_E5                                                                  0x1081e8cUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define YCM_REG_QM_SM_CON_CTX_LDST_FLG_4_BB_K2                                                               0x1080474UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define YCM_REG_QM_SM_CON_CTX_LDST_FLG_4_E5                                                                  0x1081e90UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define YCM_REG_QM_SM_CON_CTX_LDST_FLG_5_BB_K2                                                               0x1080478UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define YCM_REG_QM_SM_CON_CTX_LDST_FLG_5_E5                                                                  0x1081e94UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define YCM_REG_QM_SM_CON_CTX_LDST_FLG_6_BB_K2                                                               0x108047cUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define YCM_REG_QM_SM_CON_CTX_LDST_FLG_6_E5                                                                  0x1081e98UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define YCM_REG_QM_SM_CON_CTX_LDST_FLG_7_BB_K2                                                               0x1080480UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define YCM_REG_QM_SM_CON_CTX_LDST_FLG_7_E5                                                                  0x1081e9cUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define YCM_REG_QM_SM_CON_CTX_LDST_FLG_8_E5                                                                  0x1081ea0UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define YCM_REG_QM_SM_CON_CTX_LDST_FLG_9_E5                                                                  0x1081ea4UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define YCM_REG_QM_SM_CON_CTX_LDST_FLG_10_E5                                                                 0x1081ea8UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define YCM_REG_QM_SM_CON_CTX_LDST_FLG_11_E5                                                                 0x1081eacUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define YCM_REG_QM_SM_CON_CTX_LDST_FLG_12_E5                                                                 0x1081eb0UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define YCM_REG_QM_SM_CON_CTX_LDST_FLG_13_E5                                                                 0x1081eb4UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define YCM_REG_QM_SM_CON_CTX_LDST_FLG_14_E5                                                                 0x1081eb8UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define YCM_REG_QM_SM_CON_CTX_LDST_FLG_15_E5                                                                 0x1081ebcUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define YCM_REG_MSDM_WEIGHT_BB_K2                                                                            0x1080618UL //Access:RW   DataWidth:0x3    // The weight of the MSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define YCM_REG_MSDM_WEIGHT_E5                                                                               0x1081ec0UL //Access:RW   DataWidth:0x3    // The weight of the input MSDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define YCM_REG_MSDM_FRWRD_MODE_BB_K2                                                                        0x108064cUL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define YCM_REG_MSDM_FRWRD_MODE_E5                                                                           0x1081ec4UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define YCM_REG_MSDM_LENGTH_MIS_BB_K2                                                                        0x1080aa8UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at MSDM interface.
+#define YCM_REG_MSDM_LENGTH_MIS_E5                                                                           0x1081ec8UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at MSDM interface.
+#define YCM_REG_MSDM_MSG_CNTR_BB_K2                                                                          0x1080ac4UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input MSDM.
+#define YCM_REG_MSDM_MSG_CNTR_E5                                                                             0x1081eccUL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input MSDM.
+#define YCM_REG_IS_MSDM_FILL_LVL_BB_K2                                                                       0x1080af4UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in MSDM Input Stage.
+#define YCM_REG_IS_MSDM_FILL_LVL_E5                                                                          0x1081ed0UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in MSDM Input Stage.
+#define YCM_REG_IS_FOC_MSDM_NXT_INF_UNIT_BB_K2                                                               0x1080b98UL //Access:R    DataWidth:0x6    // Debug read from MSDM Input stage buffer: number of reads to next information unit.
+#define YCM_REG_IS_FOC_MSDM_NXT_INF_UNIT_E5                                                                  0x1081ed4UL //Access:R    DataWidth:0x6    // Debug read from MSDM Input stage buffer: number of reads to next information unit.
+#define YCM_REG_IS_FOC_MSDM_BB_K2                                                                            0x1081480UL //Access:R    DataWidth:0x20   // Debug read from MSDM Input stage buffer with 32-bits granularity. Read only.
+#define YCM_REG_IS_FOC_MSDM_E5                                                                               0x1081f00UL //Access:R    DataWidth:0x20   // Debug read from MSDM Input stage buffer with 32-bits granularity. Read only.
+#define YCM_REG_IS_FOC_MSDM_SIZE                                                                             20
+#define YCM_REG_IS_FOC_XYLD_BB_K2                                                                            0x1081600UL //Access:R    DataWidth:0x20   // Debug read from XYLD Input stage buffer with 32-bits granularity. Read only.
+#define YCM_REG_IS_FOC_XYLD_E5                                                                               0x1082000UL //Access:R    DataWidth:0x20   // Debug read from XYLD Input stage buffer with 32-bits granularity. Read only.
+#define YCM_REG_IS_FOC_XYLD_SIZE_BB_K2                                                                       116
+#define YCM_REG_IS_FOC_XYLD_SIZE_E5                                                                          176
+#define YCM_REG_IS_FOC_YSEM_NXT_INF_UNIT_BB_K2                                                               0x1080b90UL //Access:R    DataWidth:0x6    // Debug read from YSEM Input stage buffer: number of reads to next information unit.
+#define YCM_REG_IS_FOC_YSEM_NXT_INF_UNIT_E5                                                                  0x1082400UL //Access:R    DataWidth:0x5    // Debug read from YSEM Input stage buffer: number of reads to next information unit.
+#define YCM_REG_IS_FOC_YSEM_BB_K2                                                                            0x1081000UL //Access:R    DataWidth:0x20   // Debug read from YSEM Input stage buffer with 32-bits granularity. Read only.
+#define YCM_REG_IS_FOC_YSEM_E5                                                                               0x1082800UL //Access:R    DataWidth:0x20   // Debug read from YSEM Input stage buffer with 32-bits granularity. Read only.
+#define YCM_REG_IS_FOC_YSEM_SIZE_BB_K2                                                                       156
+#define YCM_REG_IS_FOC_YSEM_SIZE_E5                                                                          168
+#define YCM_REG_AGG_TASK_CF0_Q_BB_K2                                                                         0x1080934UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define YCM_REG_AGG_TASK_CF0_Q_E5                                                                            0x1082c00UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define YCM_REG_AGG_TASK_CF1_Q_BB_K2                                                                         0x1080938UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define YCM_REG_AGG_TASK_CF1_Q_E5                                                                            0x1082c04UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define YCM_REG_AGG_TASK_CF3_Q_E5                                                                            0x1082c08UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define YCM_REG_AGG_TASK_CF4_Q_E5                                                                            0x1082c0cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define YCM_REG_XX_MSG_RAM                                                                                   0x1088000UL //Access:R    DataWidth:0x20   // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
+#define YCM_REG_XX_MSG_RAM_SIZE                                                                              6240
+#define PCM_REG_INIT                                                                                         0x1100000UL //Access:RW   DataWidth:0x1    // Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
+#define PCM_REG_DBG_SELECT                                                                                   0x1100040UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PCM_REG_DBG_DWORD_ENABLE                                                                             0x1100044UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PCM_REG_DBG_SHIFT                                                                                    0x1100048UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PCM_REG_DBG_FORCE_VALID                                                                              0x110004cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PCM_REG_DBG_FORCE_FRAME                                                                              0x1100050UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PCM_REG_DBG_OUT_DATA                                                                                 0x1100060UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PCM_REG_DBG_OUT_DATA_SIZE                                                                            8
+#define PCM_REG_DBG_OUT_VALID                                                                                0x1100080UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define PCM_REG_DBG_OUT_FRAME                                                                                0x1100084UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define PCM_REG_INT_STS_0                                                                                    0x1100180UL //Access:R    DataWidth:0xb    // Multi Field Register.
+  #define PCM_REG_INT_STS_0_ADDRESS_ERROR                                                                    (0x1<<0) // Signals an unknown address to the rf module.
+  #define PCM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                              0
+  #define PCM_REG_INT_STS_0_IS_STORM_OVFL_ERR                                                                (0x1<<1) // Write to full STORM input buffer.
+  #define PCM_REG_INT_STS_0_IS_STORM_OVFL_ERR_SHIFT                                                          1
+  #define PCM_REG_INT_STS_0_IS_STORM_UNDER_ERR                                                               (0x1<<2) // Read from empty  STORM input buffer.
+  #define PCM_REG_INT_STS_0_IS_STORM_UNDER_ERR_SHIFT                                                         2
+  #define PCM_REG_INT_STS_0_IS_PSDM_OVFL_ERR                                                                 (0x1<<3) // Write to full PSDM input buffer.
+  #define PCM_REG_INT_STS_0_IS_PSDM_OVFL_ERR_SHIFT                                                           3
+  #define PCM_REG_INT_STS_0_IS_PSDM_UNDER_ERR                                                                (0x1<<4) // Read from empty PSDM input buffer.
+  #define PCM_REG_INT_STS_0_IS_PSDM_UNDER_ERR_SHIFT                                                          4
+  #define PCM_REG_INT_STS_0_EXT_LD_UNDER_ERR_E5                                                              (0x1<<5) // Read from empty External read buffer.
+  #define PCM_REG_INT_STS_0_EXT_LD_UNDER_ERR_E5_SHIFT                                                        5
+  #define PCM_REG_INT_STS_0_EXT_LD_OVFL_ERR_E5                                                               (0x1<<6) // Write to fully External read buffer.
+  #define PCM_REG_INT_STS_0_EXT_LD_OVFL_ERR_E5_SHIFT                                                         6
+  #define PCM_REG_INT_STS_0_IS_YPLD_OVFL_ERR_E5                                                              (0x1<<7) // Write to full YPLD input buffer.
+  #define PCM_REG_INT_STS_0_IS_YPLD_OVFL_ERR_E5_SHIFT                                                        7
+  #define PCM_REG_INT_STS_0_IS_YPLD_UNDER_ERR_E5                                                             (0x1<<8) // Read from empty YPLD input buffer.
+  #define PCM_REG_INT_STS_0_IS_YPLD_UNDER_ERR_E5_SHIFT                                                       8
+  #define PCM_REG_INT_STS_0_AFFINITY_TYPE_NO_CON_E5                                                          (0x1<<9) // Affinity type = 2 (connection based) but connection doesn't exist.
+  #define PCM_REG_INT_STS_0_AFFINITY_TYPE_NO_CON_E5_SHIFT                                                    9
+  #define PCM_REG_INT_STS_0_AFFINITY_TYPE_NO_TASK_E5                                                         (0x1<<10) // Affinity type = 3 (task based) but task doesn't exist.
+  #define PCM_REG_INT_STS_0_AFFINITY_TYPE_NO_TASK_E5_SHIFT                                                   10
+#define PCM_REG_INT_MASK_0                                                                                   0x1100184UL //Access:RW   DataWidth:0xb    // Multi Field Register.
+  #define PCM_REG_INT_MASK_0_ADDRESS_ERROR                                                                   (0x1<<0) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.ADDRESS_ERROR .
+  #define PCM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                             0
+  #define PCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR                                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.IS_STORM_OVFL_ERR .
+  #define PCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR_SHIFT                                                         1
+  #define PCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR                                                              (0x1<<2) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.IS_STORM_UNDER_ERR .
+  #define PCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR_SHIFT                                                        2
+  #define PCM_REG_INT_MASK_0_IS_PSDM_OVFL_ERR                                                                (0x1<<3) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.IS_PSDM_OVFL_ERR .
+  #define PCM_REG_INT_MASK_0_IS_PSDM_OVFL_ERR_SHIFT                                                          3
+  #define PCM_REG_INT_MASK_0_IS_PSDM_UNDER_ERR                                                               (0x1<<4) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.IS_PSDM_UNDER_ERR .
+  #define PCM_REG_INT_MASK_0_IS_PSDM_UNDER_ERR_SHIFT                                                         4
+  #define PCM_REG_INT_MASK_0_EXT_LD_UNDER_ERR_E5                                                             (0x1<<5) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.EXT_LD_UNDER_ERR .
+  #define PCM_REG_INT_MASK_0_EXT_LD_UNDER_ERR_E5_SHIFT                                                       5
+  #define PCM_REG_INT_MASK_0_EXT_LD_OVFL_ERR_E5                                                              (0x1<<6) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.EXT_LD_OVFL_ERR .
+  #define PCM_REG_INT_MASK_0_EXT_LD_OVFL_ERR_E5_SHIFT                                                        6
+  #define PCM_REG_INT_MASK_0_IS_YPLD_OVFL_ERR_E5                                                             (0x1<<7) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.IS_YPLD_OVFL_ERR .
+  #define PCM_REG_INT_MASK_0_IS_YPLD_OVFL_ERR_E5_SHIFT                                                       7
+  #define PCM_REG_INT_MASK_0_IS_YPLD_UNDER_ERR_E5                                                            (0x1<<8) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.IS_YPLD_UNDER_ERR .
+  #define PCM_REG_INT_MASK_0_IS_YPLD_UNDER_ERR_E5_SHIFT                                                      8
+  #define PCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_CON_E5                                                         (0x1<<9) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.AFFINITY_TYPE_NO_CON .
+  #define PCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_CON_E5_SHIFT                                                   9
+  #define PCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_TASK_E5                                                        (0x1<<10) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.AFFINITY_TYPE_NO_TASK .
+  #define PCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_TASK_E5_SHIFT                                                  10
+#define PCM_REG_INT_STS_WR_0                                                                                 0x1100188UL //Access:WR   DataWidth:0xb    // Multi Field Register.
+  #define PCM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define PCM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                           0
+  #define PCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR                                                             (0x1<<1) // Write to full STORM input buffer.
+  #define PCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR_SHIFT                                                       1
+  #define PCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR                                                            (0x1<<2) // Read from empty  STORM input buffer.
+  #define PCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR_SHIFT                                                      2
+  #define PCM_REG_INT_STS_WR_0_IS_PSDM_OVFL_ERR                                                              (0x1<<3) // Write to full PSDM input buffer.
+  #define PCM_REG_INT_STS_WR_0_IS_PSDM_OVFL_ERR_SHIFT                                                        3
+  #define PCM_REG_INT_STS_WR_0_IS_PSDM_UNDER_ERR                                                             (0x1<<4) // Read from empty PSDM input buffer.
+  #define PCM_REG_INT_STS_WR_0_IS_PSDM_UNDER_ERR_SHIFT                                                       4
+  #define PCM_REG_INT_STS_WR_0_EXT_LD_UNDER_ERR_E5                                                           (0x1<<5) // Read from empty External read buffer.
+  #define PCM_REG_INT_STS_WR_0_EXT_LD_UNDER_ERR_E5_SHIFT                                                     5
+  #define PCM_REG_INT_STS_WR_0_EXT_LD_OVFL_ERR_E5                                                            (0x1<<6) // Write to fully External read buffer.
+  #define PCM_REG_INT_STS_WR_0_EXT_LD_OVFL_ERR_E5_SHIFT                                                      6
+  #define PCM_REG_INT_STS_WR_0_IS_YPLD_OVFL_ERR_E5                                                           (0x1<<7) // Write to full YPLD input buffer.
+  #define PCM_REG_INT_STS_WR_0_IS_YPLD_OVFL_ERR_E5_SHIFT                                                     7
+  #define PCM_REG_INT_STS_WR_0_IS_YPLD_UNDER_ERR_E5                                                          (0x1<<8) // Read from empty YPLD input buffer.
+  #define PCM_REG_INT_STS_WR_0_IS_YPLD_UNDER_ERR_E5_SHIFT                                                    8
+  #define PCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_CON_E5                                                       (0x1<<9) // Affinity type = 2 (connection based) but connection doesn't exist.
+  #define PCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_CON_E5_SHIFT                                                 9
+  #define PCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_TASK_E5                                                      (0x1<<10) // Affinity type = 3 (task based) but task doesn't exist.
+  #define PCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_TASK_E5_SHIFT                                                10
+#define PCM_REG_INT_STS_CLR_0                                                                                0x110018cUL //Access:RC   DataWidth:0xb    // Multi Field Register.
+  #define PCM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define PCM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                          0
+  #define PCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR                                                            (0x1<<1) // Write to full STORM input buffer.
+  #define PCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR_SHIFT                                                      1
+  #define PCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR                                                           (0x1<<2) // Read from empty  STORM input buffer.
+  #define PCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR_SHIFT                                                     2
+  #define PCM_REG_INT_STS_CLR_0_IS_PSDM_OVFL_ERR                                                             (0x1<<3) // Write to full PSDM input buffer.
+  #define PCM_REG_INT_STS_CLR_0_IS_PSDM_OVFL_ERR_SHIFT                                                       3
+  #define PCM_REG_INT_STS_CLR_0_IS_PSDM_UNDER_ERR                                                            (0x1<<4) // Read from empty PSDM input buffer.
+  #define PCM_REG_INT_STS_CLR_0_IS_PSDM_UNDER_ERR_SHIFT                                                      4
+  #define PCM_REG_INT_STS_CLR_0_EXT_LD_UNDER_ERR_E5                                                          (0x1<<5) // Read from empty External read buffer.
+  #define PCM_REG_INT_STS_CLR_0_EXT_LD_UNDER_ERR_E5_SHIFT                                                    5
+  #define PCM_REG_INT_STS_CLR_0_EXT_LD_OVFL_ERR_E5                                                           (0x1<<6) // Write to fully External read buffer.
+  #define PCM_REG_INT_STS_CLR_0_EXT_LD_OVFL_ERR_E5_SHIFT                                                     6
+  #define PCM_REG_INT_STS_CLR_0_IS_YPLD_OVFL_ERR_E5                                                          (0x1<<7) // Write to full YPLD input buffer.
+  #define PCM_REG_INT_STS_CLR_0_IS_YPLD_OVFL_ERR_E5_SHIFT                                                    7
+  #define PCM_REG_INT_STS_CLR_0_IS_YPLD_UNDER_ERR_E5                                                         (0x1<<8) // Read from empty YPLD input buffer.
+  #define PCM_REG_INT_STS_CLR_0_IS_YPLD_UNDER_ERR_E5_SHIFT                                                   8
+  #define PCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_CON_E5                                                      (0x1<<9) // Affinity type = 2 (connection based) but connection doesn't exist.
+  #define PCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_CON_E5_SHIFT                                                9
+  #define PCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_TASK_E5                                                     (0x1<<10) // Affinity type = 3 (task based) but task doesn't exist.
+  #define PCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_TASK_E5_SHIFT                                               10
+#define PCM_REG_INT_STS_1                                                                                    0x1100190UL //Access:R    DataWidth:0xc    // Multi Field Register.
+  #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0_BB_K2                                                           (0x1<<2) // Write to full GRC input buffer bits [31:0].
+  #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0_BB_K2_SHIFT                                                     2
+  #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0_E5                                                              (0x1<<0) // Write to full GRC input buffer bits [31:0].
+  #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0_E5_SHIFT                                                        0
+  #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0_BB_K2                                                          (0x1<<3) // Read from empty  GRC input buffer bits [31:0].
+  #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0_BB_K2_SHIFT                                                    3
+  #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0_E5                                                             (0x1<<1) // Read from empty  GRC input buffer bits [31:0].
+  #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0_E5_SHIFT                                                       1
+  #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1_BB_K2                                                           (0x1<<4) // Write to full GRC input buffer bits [63:32].
+  #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1_BB_K2_SHIFT                                                     4
+  #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1_E5                                                              (0x1<<2) // Write to full GRC input buffer bits [63:32].
+  #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1_E5_SHIFT                                                        2
+  #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1_BB_K2                                                          (0x1<<5) // Read from empty  GRC input buffer bits [63:32].
+  #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1_BB_K2_SHIFT                                                    5
+  #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1_E5                                                             (0x1<<3) // Read from empty  GRC input buffer bits [63:32].
+  #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1_E5_SHIFT                                                       3
+  #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2_BB_K2                                                           (0x1<<6) // Write to full GRC input buffer bits [95:64].
+  #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2_BB_K2_SHIFT                                                     6
+  #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2_E5                                                              (0x1<<4) // Write to full GRC input buffer bits [95:64].
+  #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2_E5_SHIFT                                                        4
+  #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2_BB_K2                                                          (0x1<<7) // Read from empty  GRC input buffer bits [95:64].
+  #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2_BB_K2_SHIFT                                                    7
+  #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2_E5                                                             (0x1<<5) // Read from empty  GRC input buffer bits [95:64].
+  #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2_E5_SHIFT                                                       5
+  #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3_BB_K2                                                           (0x1<<8) // Write to full GRC input buffer bits [127:96].
+  #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3_BB_K2_SHIFT                                                     8
+  #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3_E5                                                              (0x1<<6) // Write to full GRC input buffer bits [127:96].
+  #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3_E5_SHIFT                                                        6
+  #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3_BB_K2                                                          (0x1<<9) // Read from empty  GRC input buffer bits [127:96].
+  #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3_BB_K2_SHIFT                                                    9
+  #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3_E5                                                             (0x1<<7) // Read from empty  GRC input buffer bits [127:96].
+  #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3_E5_SHIFT                                                       7
+  #define PCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL_BB_K2                                                           (0x1<<10) // In-process Table overflow.
+  #define PCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL_BB_K2_SHIFT                                                     10
+  #define PCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL_E5                                                              (0x1<<8) // In-process Table overflow.
+  #define PCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL_E5_SHIFT                                                        8
+  #define PCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL_BB_K2                                                       (0x1<<11) // Message Processor Storm Connection Data buffer overflow.
+  #define PCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL_BB_K2_SHIFT                                                 11
+  #define PCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL_E5                                                          (0x1<<9) // Message Processor Storm Connection Data buffer overflow.
+  #define PCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL_E5_SHIFT                                                    9
+  #define PCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL_BB_K2                                                        (0x1<<12) // Message Processor Storm Connection Command buffer overflow.
+  #define PCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL_BB_K2_SHIFT                                                  12
+  #define PCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL_E5                                                           (0x1<<10) // Message Processor Storm Connection Command buffer overflow.
+  #define PCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL_E5_SHIFT                                                     10
+  #define PCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE_BB_K2                                                      (0x1<<13) // Input message first descriptor fields violation.
+  #define PCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE_BB_K2_SHIFT                                                13
+  #define PCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE_E5                                                         (0x1<<11) // Input message first descriptor fields violation.
+  #define PCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE_E5_SHIFT                                                   11
+  #define PCM_REG_INT_STS_1_IS_PBF_OVFL_ERR_BB_K2                                                            (0x1<<0) // Write to full Pbf input buffer.
+  #define PCM_REG_INT_STS_1_IS_PBF_OVFL_ERR_BB_K2_SHIFT                                                      0
+  #define PCM_REG_INT_STS_1_IS_PBF_UNDER_ERR_BB_K2                                                           (0x1<<1) // Read from empty Pbf input buffer.
+  #define PCM_REG_INT_STS_1_IS_PBF_UNDER_ERR_BB_K2_SHIFT                                                     1
+#define PCM_REG_INT_MASK_1                                                                                   0x1100194UL //Access:RW   DataWidth:0xc    // Multi Field Register.
+  #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0_BB_K2                                                          (0x1<<2) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_OVFL_ERR0 .
+  #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0_BB_K2_SHIFT                                                    2
+  #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0_E5                                                             (0x1<<0) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_OVFL_ERR0 .
+  #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0_E5_SHIFT                                                       0
+  #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0_BB_K2                                                         (0x1<<3) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_UNDER_ERR0 .
+  #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0_BB_K2_SHIFT                                                   3
+  #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0_E5                                                            (0x1<<1) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_UNDER_ERR0 .
+  #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0_E5_SHIFT                                                      1
+  #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1_BB_K2                                                          (0x1<<4) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_OVFL_ERR1 .
+  #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1_BB_K2_SHIFT                                                    4
+  #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1_E5                                                             (0x1<<2) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_OVFL_ERR1 .
+  #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1_E5_SHIFT                                                       2
+  #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1_BB_K2                                                         (0x1<<5) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_UNDER_ERR1 .
+  #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1_BB_K2_SHIFT                                                   5
+  #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1_E5                                                            (0x1<<3) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_UNDER_ERR1 .
+  #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1_E5_SHIFT                                                      3
+  #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2_BB_K2                                                          (0x1<<6) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_OVFL_ERR2 .
+  #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2_BB_K2_SHIFT                                                    6
+  #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2_E5                                                             (0x1<<4) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_OVFL_ERR2 .
+  #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2_E5_SHIFT                                                       4
+  #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2_BB_K2                                                         (0x1<<7) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_UNDER_ERR2 .
+  #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2_BB_K2_SHIFT                                                   7
+  #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2_E5                                                            (0x1<<5) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_UNDER_ERR2 .
+  #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2_E5_SHIFT                                                      5
+  #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3_BB_K2                                                          (0x1<<8) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_OVFL_ERR3 .
+  #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3_BB_K2_SHIFT                                                    8
+  #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3_E5                                                             (0x1<<6) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_OVFL_ERR3 .
+  #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3_E5_SHIFT                                                       6
+  #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3_BB_K2                                                         (0x1<<9) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_UNDER_ERR3 .
+  #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3_BB_K2_SHIFT                                                   9
+  #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3_E5                                                            (0x1<<7) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_UNDER_ERR3 .
+  #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3_E5_SHIFT                                                      7
+  #define PCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL_BB_K2                                                          (0x1<<10) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IN_PRCS_TBL_OVFL .
+  #define PCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL_BB_K2_SHIFT                                                    10
+  #define PCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL_E5                                                             (0x1<<8) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IN_PRCS_TBL_OVFL .
+  #define PCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL_E5_SHIFT                                                       8
+  #define PCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL_BB_K2                                                      (0x1<<11) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.SM_CON_DATA_BUF_OVFL .
+  #define PCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL_BB_K2_SHIFT                                                11
+  #define PCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL_E5                                                         (0x1<<9) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.SM_CON_DATA_BUF_OVFL .
+  #define PCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL_E5_SHIFT                                                   9
+  #define PCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL_BB_K2                                                       (0x1<<12) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.SM_CON_CMD_BUF_OVFL .
+  #define PCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL_BB_K2_SHIFT                                                 12
+  #define PCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL_E5                                                          (0x1<<10) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.SM_CON_CMD_BUF_OVFL .
+  #define PCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL_E5_SHIFT                                                    10
+  #define PCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE_BB_K2                                                     (0x1<<13) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.FI_DESC_INPUT_VIOLATE .
+  #define PCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE_BB_K2_SHIFT                                               13
+  #define PCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE_E5                                                        (0x1<<11) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.FI_DESC_INPUT_VIOLATE .
+  #define PCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE_E5_SHIFT                                                  11
+  #define PCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR_BB_K2                                                           (0x1<<0) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_PBF_OVFL_ERR .
+  #define PCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR_BB_K2_SHIFT                                                     0
+  #define PCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR_BB_K2                                                          (0x1<<1) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_PBF_UNDER_ERR .
+  #define PCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR_BB_K2_SHIFT                                                    1
+#define PCM_REG_INT_STS_WR_1                                                                                 0x1100198UL //Access:WR   DataWidth:0xc    // Multi Field Register.
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0_BB_K2                                                        (0x1<<2) // Write to full GRC input buffer bits [31:0].
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0_BB_K2_SHIFT                                                  2
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0_E5                                                           (0x1<<0) // Write to full GRC input buffer bits [31:0].
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0_E5_SHIFT                                                     0
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0_BB_K2                                                       (0x1<<3) // Read from empty  GRC input buffer bits [31:0].
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0_BB_K2_SHIFT                                                 3
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0_E5                                                          (0x1<<1) // Read from empty  GRC input buffer bits [31:0].
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0_E5_SHIFT                                                    1
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1_BB_K2                                                        (0x1<<4) // Write to full GRC input buffer bits [63:32].
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1_BB_K2_SHIFT                                                  4
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1_E5                                                           (0x1<<2) // Write to full GRC input buffer bits [63:32].
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1_E5_SHIFT                                                     2
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1_BB_K2                                                       (0x1<<5) // Read from empty  GRC input buffer bits [63:32].
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1_BB_K2_SHIFT                                                 5
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1_E5                                                          (0x1<<3) // Read from empty  GRC input buffer bits [63:32].
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1_E5_SHIFT                                                    3
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2_BB_K2                                                        (0x1<<6) // Write to full GRC input buffer bits [95:64].
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2_BB_K2_SHIFT                                                  6
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2_E5                                                           (0x1<<4) // Write to full GRC input buffer bits [95:64].
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2_E5_SHIFT                                                     4
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2_BB_K2                                                       (0x1<<7) // Read from empty  GRC input buffer bits [95:64].
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2_BB_K2_SHIFT                                                 7
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2_E5                                                          (0x1<<5) // Read from empty  GRC input buffer bits [95:64].
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2_E5_SHIFT                                                    5
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3_BB_K2                                                        (0x1<<8) // Write to full GRC input buffer bits [127:96].
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3_BB_K2_SHIFT                                                  8
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3_E5                                                           (0x1<<6) // Write to full GRC input buffer bits [127:96].
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3_E5_SHIFT                                                     6
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3_BB_K2                                                       (0x1<<9) // Read from empty  GRC input buffer bits [127:96].
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3_BB_K2_SHIFT                                                 9
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3_E5                                                          (0x1<<7) // Read from empty  GRC input buffer bits [127:96].
+  #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3_E5_SHIFT                                                    7
+  #define PCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL_BB_K2                                                        (0x1<<10) // In-process Table overflow.
+  #define PCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL_BB_K2_SHIFT                                                  10
+  #define PCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL_E5                                                           (0x1<<8) // In-process Table overflow.
+  #define PCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL_E5_SHIFT                                                     8
+  #define PCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL_BB_K2                                                    (0x1<<11) // Message Processor Storm Connection Data buffer overflow.
+  #define PCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL_BB_K2_SHIFT                                              11
+  #define PCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL_E5                                                       (0x1<<9) // Message Processor Storm Connection Data buffer overflow.
+  #define PCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL_E5_SHIFT                                                 9
+  #define PCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL_BB_K2                                                     (0x1<<12) // Message Processor Storm Connection Command buffer overflow.
+  #define PCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL_BB_K2_SHIFT                                               12
+  #define PCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL_E5                                                        (0x1<<10) // Message Processor Storm Connection Command buffer overflow.
+  #define PCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL_E5_SHIFT                                                  10
+  #define PCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE_BB_K2                                                   (0x1<<13) // Input message first descriptor fields violation.
+  #define PCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE_BB_K2_SHIFT                                             13
+  #define PCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE_E5                                                      (0x1<<11) // Input message first descriptor fields violation.
+  #define PCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE_E5_SHIFT                                                11
+  #define PCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR_BB_K2                                                         (0x1<<0) // Write to full Pbf input buffer.
+  #define PCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR_BB_K2_SHIFT                                                   0
+  #define PCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR_BB_K2                                                        (0x1<<1) // Read from empty Pbf input buffer.
+  #define PCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR_BB_K2_SHIFT                                                  1
+#define PCM_REG_INT_STS_CLR_1                                                                                0x110019cUL //Access:RC   DataWidth:0xc    // Multi Field Register.
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0_BB_K2                                                       (0x1<<2) // Write to full GRC input buffer bits [31:0].
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0_BB_K2_SHIFT                                                 2
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0_E5                                                          (0x1<<0) // Write to full GRC input buffer bits [31:0].
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0_E5_SHIFT                                                    0
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0_BB_K2                                                      (0x1<<3) // Read from empty  GRC input buffer bits [31:0].
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0_BB_K2_SHIFT                                                3
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0_E5                                                         (0x1<<1) // Read from empty  GRC input buffer bits [31:0].
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0_E5_SHIFT                                                   1
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1_BB_K2                                                       (0x1<<4) // Write to full GRC input buffer bits [63:32].
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1_BB_K2_SHIFT                                                 4
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1_E5                                                          (0x1<<2) // Write to full GRC input buffer bits [63:32].
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1_E5_SHIFT                                                    2
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1_BB_K2                                                      (0x1<<5) // Read from empty  GRC input buffer bits [63:32].
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1_BB_K2_SHIFT                                                5
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1_E5                                                         (0x1<<3) // Read from empty  GRC input buffer bits [63:32].
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1_E5_SHIFT                                                   3
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2_BB_K2                                                       (0x1<<6) // Write to full GRC input buffer bits [95:64].
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2_BB_K2_SHIFT                                                 6
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2_E5                                                          (0x1<<4) // Write to full GRC input buffer bits [95:64].
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2_E5_SHIFT                                                    4
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2_BB_K2                                                      (0x1<<7) // Read from empty  GRC input buffer bits [95:64].
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2_BB_K2_SHIFT                                                7
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2_E5                                                         (0x1<<5) // Read from empty  GRC input buffer bits [95:64].
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2_E5_SHIFT                                                   5
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3_BB_K2                                                       (0x1<<8) // Write to full GRC input buffer bits [127:96].
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3_BB_K2_SHIFT                                                 8
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3_E5                                                          (0x1<<6) // Write to full GRC input buffer bits [127:96].
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3_E5_SHIFT                                                    6
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3_BB_K2                                                      (0x1<<9) // Read from empty  GRC input buffer bits [127:96].
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3_BB_K2_SHIFT                                                9
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3_E5                                                         (0x1<<7) // Read from empty  GRC input buffer bits [127:96].
+  #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3_E5_SHIFT                                                   7
+  #define PCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL_BB_K2                                                       (0x1<<10) // In-process Table overflow.
+  #define PCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL_BB_K2_SHIFT                                                 10
+  #define PCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL_E5                                                          (0x1<<8) // In-process Table overflow.
+  #define PCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL_E5_SHIFT                                                    8
+  #define PCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL_BB_K2                                                   (0x1<<11) // Message Processor Storm Connection Data buffer overflow.
+  #define PCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL_BB_K2_SHIFT                                             11
+  #define PCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL_E5                                                      (0x1<<9) // Message Processor Storm Connection Data buffer overflow.
+  #define PCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL_E5_SHIFT                                                9
+  #define PCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL_BB_K2                                                    (0x1<<12) // Message Processor Storm Connection Command buffer overflow.
+  #define PCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL_BB_K2_SHIFT                                              12
+  #define PCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL_E5                                                       (0x1<<10) // Message Processor Storm Connection Command buffer overflow.
+  #define PCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL_E5_SHIFT                                                 10
+  #define PCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE_BB_K2                                                  (0x1<<13) // Input message first descriptor fields violation.
+  #define PCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE_BB_K2_SHIFT                                            13
+  #define PCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE_E5                                                     (0x1<<11) // Input message first descriptor fields violation.
+  #define PCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE_E5_SHIFT                                               11
+  #define PCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR_BB_K2                                                        (0x1<<0) // Write to full Pbf input buffer.
+  #define PCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR_BB_K2_SHIFT                                                  0
+  #define PCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR_BB_K2                                                       (0x1<<1) // Read from empty Pbf input buffer.
+  #define PCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR_BB_K2_SHIFT                                                 1
+#define PCM_REG_INT_STS_2                                                                                    0x11001a0UL //Access:R    DataWidth:0x1    // Multi Field Register.
+  #define PCM_REG_INT_STS_2_QMREG_MORE4                                                                      (0x1<<0) // More than 4 QM registrations.
+  #define PCM_REG_INT_STS_2_QMREG_MORE4_SHIFT                                                                0
+#define PCM_REG_INT_MASK_2                                                                                   0x11001a4UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define PCM_REG_INT_MASK_2_QMREG_MORE4                                                                     (0x1<<0) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_2.QMREG_MORE4 .
+  #define PCM_REG_INT_MASK_2_QMREG_MORE4_SHIFT                                                               0
+#define PCM_REG_INT_STS_WR_2                                                                                 0x11001a8UL //Access:WR   DataWidth:0x1    // Multi Field Register.
+  #define PCM_REG_INT_STS_WR_2_QMREG_MORE4                                                                   (0x1<<0) // More than 4 QM registrations.
+  #define PCM_REG_INT_STS_WR_2_QMREG_MORE4_SHIFT                                                             0
+#define PCM_REG_INT_STS_CLR_2                                                                                0x11001acUL //Access:RC   DataWidth:0x1    // Multi Field Register.
+  #define PCM_REG_INT_STS_CLR_2_QMREG_MORE4                                                                  (0x1<<0) // More than 4 QM registrations.
+  #define PCM_REG_INT_STS_CLR_2_QMREG_MORE4_SHIFT                                                            0
+#define PCM_REG_PRTY_MASK_H_0_BB_K2                                                                          0x1100204UL //Access:RW   DataWidth:0xf    // Multi Field Register.
+  #define PCM_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_K2                                                       (0x1<<0) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM012_I_ECC_RF_INT .
+  #define PCM_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_K2_SHIFT                                                 0
+  #define PCM_REG_PRTY_MASK_H_0_MEM010_I_ECC_0_RF_INT_K2                                                     (0x1<<1) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM010_I_ECC_0_RF_INT .
+  #define PCM_REG_PRTY_MASK_H_0_MEM010_I_ECC_0_RF_INT_K2_SHIFT                                               1
+  #define PCM_REG_PRTY_MASK_H_0_MEM010_I_ECC_1_RF_INT_K2                                                     (0x1<<2) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM010_I_ECC_1_RF_INT .
+  #define PCM_REG_PRTY_MASK_H_0_MEM010_I_ECC_1_RF_INT_K2_SHIFT                                               2
+  #define PCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2                                                         (0x1<<3) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define PCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_SHIFT                                                   3
+  #define PCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB                                                         (0x1<<3) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define PCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_SHIFT                                                   3
+  #define PCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2                                                         (0x1<<4) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
+  #define PCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_SHIFT                                                   4
+  #define PCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB                                                         (0x1<<4) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define PCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_SHIFT                                                   4
+  #define PCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2                                                         (0x1<<5) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define PCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_SHIFT                                                   5
+  #define PCM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB                                                         (0x1<<5) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define PCM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_SHIFT                                                   5
+  #define PCM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2                                                         (0x1<<6) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define PCM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_SHIFT                                                   6
+  #define PCM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB                                                         (0x1<<6) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define PCM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_SHIFT                                                   6
+  #define PCM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2                                                         (0x1<<7) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define PCM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_SHIFT                                                   7
+  #define PCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB                                                         (0x1<<7) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define PCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_SHIFT                                                   7
+  #define PCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2                                                         (0x1<<8) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define PCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_SHIFT                                                   8
+  #define PCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB                                                         (0x1<<8) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define PCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_SHIFT                                                   8
+  #define PCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2                                                         (0x1<<9) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define PCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2_SHIFT                                                   9
+  #define PCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2                                                         (0x1<<10) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
+  #define PCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2_SHIFT                                                   10
+  #define PCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2                                                         (0x1<<11) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
+  #define PCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2_SHIFT                                                   11
+  #define PCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2                                                         (0x1<<12) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
+  #define PCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2_SHIFT                                                   12
+  #define PCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2                                                         (0x1<<13) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define PCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2_SHIFT                                                   13
+  #define PCM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB                                                         (0x1<<10) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define PCM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_SHIFT                                                   10
+  #define PCM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_K2                                                         (0x1<<14) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define PCM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_K2_SHIFT                                                   14
+  #define PCM_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT_BB                                                       (0x1<<0) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM011_I_ECC_RF_INT .
+  #define PCM_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT_BB_SHIFT                                                 0
+  #define PCM_REG_PRTY_MASK_H_0_MEM009_I_ECC_0_RF_INT_BB                                                     (0x1<<1) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM009_I_ECC_0_RF_INT .
+  #define PCM_REG_PRTY_MASK_H_0_MEM009_I_ECC_0_RF_INT_BB_SHIFT                                               1
+  #define PCM_REG_PRTY_MASK_H_0_MEM009_I_ECC_1_RF_INT_BB                                                     (0x1<<2) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM009_I_ECC_1_RF_INT .
+  #define PCM_REG_PRTY_MASK_H_0_MEM009_I_ECC_1_RF_INT_BB_SHIFT                                               2
+  #define PCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB                                                         (0x1<<9) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
+  #define PCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_SHIFT                                                   9
+#define PCM_REG_MEM010_RF_ECC_ERROR_CONNECT_0_K2                                                             0x1100210UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: pcm.i_sm_con_ctx.rf_ecc_error_connect_0 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define PCM_REG_MEM009_RF_ECC_ERROR_CONNECT_0_BB                                                             0x1100210UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: pcm.i_sm_con_ctx.rf_ecc_error_connect_0 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define PCM_REG_MEM010_RF_ECC_ERROR_CONNECT_1_K2                                                             0x1100214UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: pcm.i_sm_con_ctx.rf_ecc_error_connect_1 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define PCM_REG_MEM009_RF_ECC_ERROR_CONNECT_1_BB                                                             0x1100214UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: pcm.i_sm_con_ctx.rf_ecc_error_connect_1 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define PCM_REG_MEM_ECC_ENABLE_0_BB_K2                                                                       0x1100218UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define PCM_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN_K2                                                        (0x1<<0) // Enable ECC for memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_msg_ram
+  #define PCM_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN_K2_SHIFT                                                  0
+  #define PCM_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_0_EN_K2                                                      (0x1<<1) // Enable ECC for memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_con_ctx
+  #define PCM_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_0_EN_K2_SHIFT                                                1
+  #define PCM_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_1_EN_K2                                                      (0x1<<2) // Enable ECC for memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_con_ctx
+  #define PCM_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_1_EN_K2_SHIFT                                                2
+  #define PCM_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_EN_BB                                                        (0x1<<0) // Enable ECC for memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_msg_ram
+  #define PCM_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_EN_BB_SHIFT                                                  0
+  #define PCM_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_0_EN_BB                                                      (0x1<<1) // Enable ECC for memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_con_ctx
+  #define PCM_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_0_EN_BB_SHIFT                                                1
+  #define PCM_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_1_EN_BB                                                      (0x1<<2) // Enable ECC for memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_con_ctx
+  #define PCM_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_1_EN_BB_SHIFT                                                2
+#define PCM_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                  0x110021cUL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY_K2                                                 (0x1<<0) // Set parity only for memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_msg_ram
+  #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY_K2_SHIFT                                           0
+  #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_0_PRTY_K2                                               (0x1<<1) // Set parity only for memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_con_ctx
+  #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_0_PRTY_K2_SHIFT                                         1
+  #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_1_PRTY_K2                                               (0x1<<2) // Set parity only for memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_con_ctx
+  #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_1_PRTY_K2_SHIFT                                         2
+  #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_PRTY_BB                                                 (0x1<<0) // Set parity only for memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_msg_ram
+  #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_PRTY_BB_SHIFT                                           0
+  #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_0_PRTY_BB                                               (0x1<<1) // Set parity only for memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_con_ctx
+  #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_0_PRTY_BB_SHIFT                                         1
+  #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_1_PRTY_BB                                               (0x1<<2) // Set parity only for memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_con_ctx
+  #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_1_PRTY_BB_SHIFT                                         2
+#define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                              0x1100220UL //Access:RC   DataWidth:0x3    // Multi Field Register.
+  #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT_K2                                          (0x1<<0) // Record if a correctable error occurred on memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_msg_ram
+  #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT_K2_SHIFT                                    0
+  #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_0_CORRECT_K2                                        (0x1<<1) // Record if a correctable error occurred on memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_con_ctx
+  #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_0_CORRECT_K2_SHIFT                                  1
+  #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_1_CORRECT_K2                                        (0x1<<2) // Record if a correctable error occurred on memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_con_ctx
+  #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_1_CORRECT_K2_SHIFT                                  2
+  #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_CORRECT_BB                                          (0x1<<0) // Record if a correctable error occurred on memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_msg_ram
+  #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_CORRECT_BB_SHIFT                                    0
+  #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_0_CORRECT_BB                                        (0x1<<1) // Record if a correctable error occurred on memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_con_ctx
+  #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_0_CORRECT_BB_SHIFT                                  1
+  #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_1_CORRECT_BB                                        (0x1<<2) // Record if a correctable error occurred on memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_con_ctx
+  #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_1_CORRECT_BB_SHIFT                                  2
+#define PCM_REG_MEM_ECC_EVENTS_BB_K2                                                                         0x1100224UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define PCM_REG_IFEN                                                                                         0x1100400UL //Access:RW   DataWidth:0x1    // Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
+#define PCM_REG_ERR_EVNT_ID                                                                                  0x1100404UL //Access:RW   DataWidth:0x8    // The Event ID in case one of errors is set in QM input message.
+#define PCM_REG_STORM_WEIGHT                                                                                 0x1100604UL //Access:RW   DataWidth:0x3    // The weight of the local Storm input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define PCM_REG_PBF_WEIGHT_BB_K2                                                                             0x1100608UL //Access:RW   DataWidth:0x3    // The weight of the input Pbf in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define PCM_REG_GRC_WEIGHT                                                                                   0x110060cUL //Access:RW   DataWidth:0x3    // The weight of the GRC input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define PCM_REG_IA_GROUP_PR0                                                                                 0x1100614UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: ia_group_pr0 is the highest priority; ia_group_pr5 is the lowest priority.
+#define PCM_REG_IA_GROUP_PR1                                                                                 0x1100618UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define PCM_REG_IA_GROUP_PR2                                                                                 0x110061cUL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define PCM_REG_IA_GROUP_PR3                                                                                 0x1100620UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define PCM_REG_IA_GROUP_PR4                                                                                 0x1100624UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define PCM_REG_IA_GROUP_PR5                                                                                 0x1100628UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define PCM_REG_IA_ARB_SP_TIMEOUT                                                                            0x110062cUL //Access:RW   DataWidth:0x8    // Input Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8'h0 - constant RR; 8'h80 - constant strict priority. In all other cases the following is true: Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance.
+#define PCM_REG_STORM_FRWRD_MODE                                                                             0x1100630UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define PCM_REG_PBF_FRWRD_MODE_BB_K2                                                                         0x1100638UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define PCM_REG_SDM_ERR_HANDLE_EN                                                                            0x110063cUL //Access:RW   DataWidth:0x1    // 0 - disable error handling in SDM message; 1 - enable error handling in SDM message.
+#define PCM_REG_DIR_BYP_EN                                                                                   0x1100640UL //Access:RW   DataWidth:0x1    // Direct bypass enable.
+#define PCM_REG_FI_DESC_INPUT_VIOLATE                                                                        0x1100644UL //Access:R    DataWidth:0xf    // Input message first descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0  then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL  then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation:  Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation:  TaskExist==0 -> XxLockCmd != XX_UNLOCK_CID_TID and XxLockCmd != XX_LOCK_CID_TID_BYPASS;  [12] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0;[13] - Violation: Agg message: Loader done with error then SmCtxLdStFlg==0; [14] - Violation: XxBypass message in PCM block;
+#define PCM_REG_IA_SM_CON_PART_FILL_LVL                                                                      0x1100648UL //Access:R    DataWidth:0x3    // Input Arbiter Storm Connection part FIFO fill level (in messages).
+#define PCM_REG_IA_TRANS_PART_FILL_LVL                                                                       0x110064cUL //Access:R    DataWidth:0x3    // Input Arbiter Transparent part FIFO fill level (in messages).
+#define PCM_REG_EXT_RD_FILL_LVL_E5                                                                           0x1100650UL //Access:R    DataWidth:0x2    // External read buffer FIFO fill level (in FIFO entries).
+#define PCM_REG_XX_MSG_UP_BND                                                                                0x1100704UL //Access:RW   DataWidth:0x3    // The maximum number of Xx RAM messages; which may be stored in XX protection. Is restricted by Xx Messages RAM size and the size of Xx protected message CM_REGISTERS_XX_MSG_SIZE.XX_MSG_SIZE
+#define PCM_REG_XX_MSG_SIZE                                                                                  0x1100708UL //Access:RW   DataWidth:0x6    // The size of Xx protected message in Xx Messages RAM in QREGs. Upper rounded to 4 and multiplied by CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND should not exceed XxMessagesRam size which is: MCM: 0d1792 PCM: 0d176 TCM: 0d1536 UCM: 0d1792 XCM: 0d256 YCM: 0d1536
+#define PCM_REG_XX_LCID_CAM_UP_BND                                                                           0x110070cUL //Access:RW   DataWidth:0x2    // The maximum number of connections in the XX protection LCID CAM.
+#define PCM_REG_XX_FREE_CNT                                                                                  0x1100710UL //Access:R    DataWidth:0x3    // Used to read the XX protection Free counter. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND
+#define PCM_REG_XX_LCID_CAM_FILL_LVL                                                                         0x1100714UL //Access:R    DataWidth:0x2    // Used to read XX protection LCID CAM fill level. Fill level is calculated as the number of locked LCIDs, i.e. LCIDs that have at least one Xx locked message or LCIDs that have no Xx locked messages but haven't been unlocked yet from LCID CAM. Simple saying it calculates for number of valid entries in LCID CAM.
+#define PCM_REG_XX_LCID_CAM_ST_STAT                                                                          0x1100718UL //Access:RC   DataWidth:0x2    // CAM occupancy sticky status. The write to the register is performed by the XX internal circuitry.
+#define PCM_REG_XX_IA_GROUP_PR0                                                                              0x110071cUL //Access:RW   DataWidth:0x1    // Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
+#define PCM_REG_XX_IA_GROUP_PR1                                                                              0x1100720UL //Access:RW   DataWidth:0x1    // Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
+#define PCM_REG_XX_NON_LOCK_LCID_THR                                                                         0x1100724UL //Access:RW   DataWidth:0x2    // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decision of Xx Input Arbiter non-locked group.
+#define PCM_REG_XX_LOCK_LCID_THR                                                                             0x1100728UL //Access:RW   DataWidth:0x2    // Xx locked LCIDs threshold (maximum value). Participates in Xx Bypass global enable decision.
+#define PCM_REG_XX_IA_ARB_SP_TIMEOUT                                                                         0x110072cUL //Access:RW   DataWidth:0x8    // Xx Input Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. E.g. bits[6:0]=0; bit[7]=0 - always strict priority; bits[6:0]=1; bit[7]=0 - strict priority; then RR; bits[6:0]=3; bit[7]=0 - 3 times strict priority; then RR.
+#define PCM_REG_XX_FREE_HEAD_PTR                                                                             0x1100730UL //Access:R    DataWidth:0x2    // Xx Free Head Pointer.
+#define PCM_REG_XX_FREE_TAIL_PTR                                                                             0x1100734UL //Access:R    DataWidth:0x2    // Xx Free Tail Pointer. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND
+#define PCM_REG_XX_NON_LOCK_CNT                                                                              0x1100738UL //Access:R    DataWidth:0x2    // Xx NonLock Counter.
+#define PCM_REG_XX_LOCK_CNT                                                                                  0x110073cUL //Access:R    DataWidth:0x2    // Xx Lock Counter.
+#define PCM_REG_XX_LCID_ARB_GROUP_PR0                                                                        0x1100740UL //Access:RW   DataWidth:0x2    // Xx LCID Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.
+#define PCM_REG_XX_LCID_ARB_GROUP_PR1                                                                        0x1100744UL //Access:RW   DataWidth:0x2    // Xx LCID Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.
+#define PCM_REG_XX_LCID_ARB_GROUP_PR2                                                                        0x1100748UL //Access:RW   DataWidth:0x2    // Xx LCID Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.
+#define PCM_REG_XX_LCID_ARB_SP_TIMEOUT                                                                       0x110074cUL //Access:RW   DataWidth:0x8    // Xx LCID Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. E.g. bits[6:0]=0; bit[7]=0 - always strict priority; bits[6:0]=1; bit[7]=0 - strict priority; then RR; bits[6:0]=3; bit[7]=0 - 3 times strict priority; then RR.
+#define PCM_REG_XX_FREE_THR_HIGH                                                                             0x1100750UL //Access:RW   DataWidth:0x3    // Xx free messages threshold high. Used in Xx Bypass global enable condition.
+#define PCM_REG_XX_FREE_THR_LOW                                                                              0x1100754UL //Access:RW   DataWidth:0x3    // Xx free messages threshold low Used in Xx Bypass global enable condition.
+#define PCM_REG_XX_PREF_DIR_FILL_LVL                                                                         0x1100758UL //Access:R    DataWidth:0x6    // Xx LCID Arbiter direct prefetch FIFO fill level (in entries).
+#define PCM_REG_XX_PREF_AGGST_FILL_LVL                                                                       0x110075cUL //Access:R    DataWidth:0x6    // Xx LCID Arbiter aggregation store prefetch FIFO fill level (in entries).
+#define PCM_REG_UNLOCK_MISS                                                                                  0x1100760UL //Access:RC   DataWidth:0x1    // Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM.
+#define PCM_REG_ERR_AFFINITY_TYPE_E5                                                                         0x1100764UL //Access:RW   DataWidth:0x2    // Affinity type in case of input message error.
+#define PCM_REG_ERR_EXCLUSIVE_FLG_E5                                                                         0x1100768UL //Access:RW   DataWidth:0x1    // Exclusive type in case of input message error.
+#define PCM_REG_ERR_SRC_AFFINITY_E5                                                                          0x110076cUL //Access:RW   DataWidth:0x3    // Source affinity in case of input message error.
+#define PCM_REG_PRCS_SM_CON_CURR_ST                                                                          0x1100804UL //Access:R    DataWidth:0x2    // STORM Connection Processor FSM.
+#define PCM_REG_SM_CON_FIC_BUF_FILL_LVL                                                                      0x1100828UL //Access:R    DataWidth:0x5    // Storm Connection FIC buffer fill level (in messages).
+#define PCM_REG_SM_CON_FIC_BUF_CRD                                                                           0x110082cUL //Access:RW   DataWidth:0x2    // Storm Connection FIC buffer credit (in full message out parts).
+#define PCM_REG_SM_CON_BUF_CRD_AGGST                                                                         0x1100830UL //Access:RW   DataWidth:0x1    // Storm Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_CON_CMD_BUF_CRD_DIR.SM_CON_CMD_BUF_CRD_DIR need be no more than Storm Connection command buffer size=3.
+#define PCM_REG_SM_CON_CMD_BUF_CRD_DIR                                                                       0x1100834UL //Access:RW   DataWidth:0x2    // Storm Connection command buffer credit (Direct group). In sum with CM_REGISTERS_SM_CON_BUF_CRD_AGGST.SM_CON_BUF_CRD_AGGST need be no more than Storm Connection command buffer size=3.
+#define PCM_REG_TRANS_DATA_BUF_CRD_DIR                                                                       0x1100838UL //Access:RW   DataWidth:0x2    // Transparent data buffer credit (Direct group).
+#define PCM_REG_SM_CON_CTX_SIZE                                                                              0x110083cUL //Access:RW   DataWidth:0x5    // STORM Connnection context per LCID size (REGQ). Default context size of 10 (REGQ) complies to 320 LCIDs. Maximum context size per LCID is 20. Maximum number of LCIDs allowed at maximum context size per LCID is 160. If not at default value need to be 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER((320*INTEGER(10/2))/(20/2)).
+#define PCM_REG_IN_PRCS_TBL_CRD_AGG                                                                          0x1100a04UL //Access:RW   DataWidth:0x4    // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.IN_PRCS_TBL_CRD_AGGST need be no more than In-process table size=12.
+#define PCM_REG_IN_PRCS_TBL_CRD_AGGST                                                                        0x1100a08UL //Access:RW   DataWidth:0x4    // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGG.IN_PRCS_TBL_CRD_AGG need be no more than In-process table size=12.
+#define PCM_REG_IN_PRCS_TBL_FILL_LVL                                                                         0x1100a0cUL //Access:R    DataWidth:0x4    // In-process Table fill level  (in messages).
+#define PCM_REG_IN_PRCS_TBL_ALMOST_FULL                                                                      0x1100a10UL //Access:R    DataWidth:0x1    // In-process Table almost full.
+#define PCM_REG_CCFC_CURR_ST                                                                                 0x1100a14UL //Access:R    DataWidth:0x1    // CFC connection output FSM current state.
+#define PCM_REG_CMPL_DIR_CURR_ST                                                                             0x1100a18UL //Access:R    DataWidth:0x4    // Direct Completer FSM current state.
+#define PCM_REG_XX_BYP_CON_STATE_EVNT_ID_FLG                                                                 0x1100a1cUL //Access:RW   DataWidth:0x1    // If set, Xx connection bypass state will be added in calculation of CM output Event ID.
+#define PCM_REG_CCFC_INIT_CRD                                                                                0x1100a84UL //Access:RW   DataWidth:0x4    // CCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.
+#define PCM_REG_FIC_INIT_CRD                                                                                 0x1100a88UL //Access:RW   DataWidth:0x6    // FIC output initial credit. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 44 at start-up.
+#define PCM_REG_DIR_BYP_MSG_CNT                                                                              0x1100aa4UL //Access:RC   DataWidth:0x20   // Counter of direct bypassed messages.
+#define PCM_REG_PBF_LENGTH_MIS_BB_K2                                                                         0x1100aacUL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at PBF interface.
+#define PCM_REG_GRC_BUF_EMPTY                                                                                0x1100ab0UL //Access:R    DataWidth:0x1    // Input Stage GRC buffer is empty.
+#define PCM_REG_GRC_BUF_STATUS                                                                               0x1100ab4UL //Access:R    DataWidth:0x6    // Input Stage GRC buffer status.
+#define PCM_REG_STORM_MSG_CNTR                                                                               0x1100ab8UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the STORM input.
+#define PCM_REG_PBF_MSG_CNTR_BB_K2                                                                           0x1100ac0UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at input PBF.
+#define PCM_REG_IS_GRC                                                                                       0x1100ac4UL //Access:W    DataWidth:0x20   // Used to write the GRC message. Write only. To distinguish if the register can be accessed to write GRC message                           polling of CM_REGISTERS.GRC_BUF_EMPTY need to be done
+#define PCM_REG_IS_STORM_FILL_LVL                                                                            0x1100ac8UL //Access:R    DataWidth:0x4    // Number of entries (2 QREGs each) of data in STORM Input Stage.
+#define PCM_REG_IS_PBF_FILL_LVL_BB_K2                                                                        0x1100ad0UL //Access:R    DataWidth:0x6    // Number of QREGs (128b) of data in PBF Input Stage.
+#define PCM_REG_FIC_MSG_CNTR                                                                                 0x1100b44UL //Access:RC   DataWidth:0x1c   // Counter of the output messages at FIC interfaces.
+#define PCM_REG_CCFC_CNTR                                                                                    0x1100b48UL //Access:RC   DataWidth:0x1c   // Counter of the output CCFC.
+#define PCM_REG_ECO_RESERVED                                                                                 0x1100b84UL //Access:RW   DataWidth:0x8    // Chicken bits.
+#define PCM_REG_IS_FOC_PSEM_NXT_INF_UNIT                                                                     0x1100b88UL //Access:R    DataWidth:0x5    // Debug read from PSEM Input stage buffer: number of reads to next information unit.
+#define PCM_REG_IS_FOC_PBF_NXT_INF_UNIT_BB_K2                                                                0x1100b8cUL //Access:R    DataWidth:0x6    // Debug read from PBF Input stage buffer: number of reads to next information unit.
+#define PCM_REG_IS_FOC_PSEM                                                                                  0x1100c00UL //Access:R    DataWidth:0x20   // Debug read from PSEM Input stage buffer with 32-bits granularity. Read only.
+#define PCM_REG_IS_FOC_PSEM_SIZE_BB_K2                                                                       96
+#define PCM_REG_IS_FOC_PSEM_SIZE_E5                                                                          104
+#define PCM_REG_IS_FOC_PBF_BB_K2                                                                             0x1101000UL //Access:R    DataWidth:0x20   // Debug read from PBF Input stage buffer with 32-bits granularity. Read only.
+#define PCM_REG_IS_FOC_PBF_SIZE                                                                              180
+#define PCM_REG_CTX_RBC_ACCS                                                                                 0x1101440UL //Access:RW   DataWidth:0x10   // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - offset (in REGs (32b)) within LCID/LTID. The procedure to read context is: first define base address and offset; then read context with one of the following registers: CM_REGISTERS_AGG_CON_CTX.AGG_CON_CTX CM_REGISTERS_SM_CON_CTX.SM_CON_CTX CM_REGISTERS_AGG_TASK_CTX.AGG_TASK_CTX CM_REGISTERS_SM_TASK_CTX.SM_TASK_CTX
+#define PCM_REG_SM_CON_CTX                                                                                   0x1101444UL //Access:RW   DataWidth:0x20   // Access is allowed only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The address base (LCID) and offset within LCID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to STORM Connection context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.
+#define PCM_REG_XX_LCID_CAM                                                                                  0x1101500UL //Access:R    DataWidth:0xa    // Debug only. Read only access to LCID CAM in XX protection mechanism.
+#define PCM_REG_XX_LCID_CAM_SIZE                                                                             2
+#define PCM_REG_XX_TBL                                                                                       0x1101600UL //Access:R    DataWidth:0xc    // Indirect access to the XX table of the XX protection mechanism. The fields are: [0] - Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: PCM - [9:8]; M/T/U/X/YCM - [17:12]; Next pointer: PCM - [11:10]; M/T/U/X/YCM - [23:18];
+#define PCM_REG_XX_TBL_SIZE                                                                                  2
+#define PCM_REG_XX_DSCR_TBL                                                                                  0x1101700UL //Access:RW   DataWidth:0x11   // Indirect access to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [13:9];PCM [14:9]; TCM [13:9]; UCM [13:9];XCM [10:9];YCM[13:9]); Next pointer (MCM [19:14]; PCM [16:15]; TCM[19:14]; UCM [19:14]; XCM [16:11]; YCM [19:14]); LTID (MCM [28:20]; PCM [25:17] - reserved; TCM[28:20]; UCM [28:20]; XCM [25:17] - reserved; YCM [28:20]). Task Domain Exist (MCM [29]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - reserved; YCM [29]). A free link list in the XX descriptor table should be build. This is done by writing the following values to all effective entries in the table:xx_descr_table[i].next_pointer = i+1 (i=0 - (xx_msg_up_bnd-2)); xx_descr_table[i].next_pointer= 0 (i=xx_msg_up_bnd-1). The value of i is between 0 to the configured (not default) value of (xx_msg_up_bnd-1). The not effective entries (those which succeed the last effective entry with index (xx_msg_up_bnd-1)) can be initialized to any value for initialization procedure simplicity seek.
+#define PCM_REG_XX_DSCR_TBL_SIZE                                                                             4
+#define PCM_REG_N_SM_CON_CTX_LD_0_BB_K2                                                                      0x1100808UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define PCM_REG_N_SM_CON_CTX_LD_0_E5                                                                         0x1101710UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define PCM_REG_N_SM_CON_CTX_LD_1_BB_K2                                                                      0x110080cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define PCM_REG_N_SM_CON_CTX_LD_1_E5                                                                         0x1101714UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define PCM_REG_N_SM_CON_CTX_LD_2_BB_K2                                                                      0x1100810UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define PCM_REG_N_SM_CON_CTX_LD_2_E5                                                                         0x1101718UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define PCM_REG_N_SM_CON_CTX_LD_3_BB_K2                                                                      0x1100814UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define PCM_REG_N_SM_CON_CTX_LD_3_E5                                                                         0x110171cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define PCM_REG_N_SM_CON_CTX_LD_4_BB_K2                                                                      0x1100818UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define PCM_REG_N_SM_CON_CTX_LD_4_E5                                                                         0x1101720UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define PCM_REG_N_SM_CON_CTX_LD_5_BB_K2                                                                      0x110081cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define PCM_REG_N_SM_CON_CTX_LD_5_E5                                                                         0x1101724UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define PCM_REG_N_SM_CON_CTX_LD_6_BB_K2                                                                      0x1100820UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define PCM_REG_N_SM_CON_CTX_LD_6_E5                                                                         0x1101728UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define PCM_REG_N_SM_CON_CTX_LD_7_BB_K2                                                                      0x1100824UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define PCM_REG_N_SM_CON_CTX_LD_7_E5                                                                         0x110172cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define PCM_REG_N_SM_CON_CTX_LD_8_E5                                                                         0x1101730UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define PCM_REG_N_SM_CON_CTX_LD_9_E5                                                                         0x1101734UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define PCM_REG_N_SM_CON_CTX_LD_10_E5                                                                        0x1101738UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 10).
+#define PCM_REG_N_SM_CON_CTX_LD_11_E5                                                                        0x110173cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define PCM_REG_N_SM_CON_CTX_LD_12_E5                                                                        0x1101740UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define PCM_REG_N_SM_CON_CTX_LD_13_E5                                                                        0x1101744UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define PCM_REG_N_SM_CON_CTX_LD_14_E5                                                                        0x1101748UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define PCM_REG_N_SM_CON_CTX_LD_15_E5                                                                        0x110174cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define PCM_REG_PSDM_WEIGHT_BB_K2                                                                            0x1100610UL //Access:RW   DataWidth:0x3    // The weight of the input PSDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define PCM_REG_PSDM_WEIGHT_E5                                                                               0x1101750UL //Access:RW   DataWidth:0x3    // The weight of the input PSDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define PCM_REG_PSDM_FRWRD_MODE_BB_K2                                                                        0x1100634UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define PCM_REG_PSDM_FRWRD_MODE_E5                                                                           0x1101754UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define PCM_REG_PSDM_LENGTH_MIS_BB_K2                                                                        0x1100aa8UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at PSDM interface.
+#define PCM_REG_PSDM_LENGTH_MIS_E5                                                                           0x1101758UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at PSDM interface.
+#define PCM_REG_PSDM_MSG_CNTR_BB_K2                                                                          0x1100abcUL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input PSDM.
+#define PCM_REG_PSDM_MSG_CNTR_E5                                                                             0x110175cUL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input PSDM.
+#define PCM_REG_IS_PSDM_FILL_LVL_BB_K2                                                                       0x1100accUL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in PSDM Input Stage.
+#define PCM_REG_IS_PSDM_FILL_LVL_E5                                                                          0x1101760UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in PSDM Input Stage.
+#define PCM_REG_IS_FOC_PSDM_NXT_INF_UNIT_BB_K2                                                               0x1100b90UL //Access:R    DataWidth:0x6    // Debug read from PSDM Input stage buffer: number of reads to next information unit.
+#define PCM_REG_IS_FOC_PSDM_NXT_INF_UNIT_E5                                                                  0x1101764UL //Access:R    DataWidth:0x6    // Debug read from PSDM Input stage buffer: number of reads to next information unit.
+#define PCM_REG_IS_FOC_PSDM_BB_K2                                                                            0x1101400UL //Access:R    DataWidth:0x20   // Debug read from PSDM Input stage buffer with 32-bits granularity. Read only.
+#define PCM_REG_IS_FOC_PSDM_E5                                                                               0x1101780UL //Access:R    DataWidth:0x20   // Debug read from PSDM Input stage buffer with 32-bits granularity. Read only.
+#define PCM_REG_IS_FOC_PSDM_SIZE                                                                             16
+#define PCM_REG_YPLD_WEIGHT_E5                                                                               0x11017c0UL //Access:RW   DataWidth:0x3    // The weight of the input YPLD in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define PCM_REG_YPLD_LENGTH_MIS_E5                                                                           0x11017c4UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at YPLD interface.
+#define PCM_REG_YPLD_MSG_CNTR_E5                                                                             0x11017c8UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at input YPLD.
+#define PCM_REG_IS_YPLD_FILL_LVL_E5                                                                          0x11017ccUL //Access:R    DataWidth:0x5    // Number of QREGs (128b) of data in YPLD Input Stage.
+#define PCM_REG_IS_FOC_YPLD_NXT_INF_UNIT_E5                                                                  0x11017d0UL //Access:R    DataWidth:0x5    // Debug read from YPLD Input stage buffer: number of reads to next information unit.
+#define PCM_REG_IS_FOC_YPLD_E5                                                                               0x1101800UL //Access:R    DataWidth:0x20   // Debug read from YPLD Input stage buffer with 32-bits granularity. Read only.
+#define PCM_REG_IS_FOC_YPLD_SIZE                                                                             44
+#define PCM_REG_XX_MSG_RAM                                                                                   0x1102000UL //Access:R    DataWidth:0x20   // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
+#define PCM_REG_XX_MSG_RAM_SIZE                                                                              704
+#define TCM_REG_INIT                                                                                         0x1180000UL //Access:RW   DataWidth:0x1    // Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
+#define TCM_REG_DBG_SELECT                                                                                   0x1180040UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define TCM_REG_DBG_DWORD_ENABLE                                                                             0x1180044UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define TCM_REG_DBG_SHIFT                                                                                    0x1180048UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define TCM_REG_DBG_FORCE_VALID                                                                              0x118004cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define TCM_REG_DBG_FORCE_FRAME                                                                              0x1180050UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define TCM_REG_DBG_OUT_DATA                                                                                 0x1180060UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define TCM_REG_DBG_OUT_DATA_SIZE                                                                            8
+#define TCM_REG_DBG_OUT_VALID                                                                                0x1180080UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define TCM_REG_DBG_OUT_FRAME                                                                                0x1180084UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define TCM_REG_AFFINITY_TYPE_0_E5                                                                           0x1180088UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define TCM_REG_AFFINITY_TYPE_1_E5                                                                           0x118008cUL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define TCM_REG_AFFINITY_TYPE_2_E5                                                                           0x1180090UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define TCM_REG_AFFINITY_TYPE_3_E5                                                                           0x1180094UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define TCM_REG_AFFINITY_TYPE_4_E5                                                                           0x1180098UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define TCM_REG_AFFINITY_TYPE_5_E5                                                                           0x118009cUL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define TCM_REG_AFFINITY_TYPE_6_E5                                                                           0x11800a0UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define TCM_REG_AFFINITY_TYPE_7_E5                                                                           0x11800a4UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define TCM_REG_AFFINITY_TYPE_8_E5                                                                           0x11800a8UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define TCM_REG_AFFINITY_TYPE_9_E5                                                                           0x11800acUL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define TCM_REG_AFFINITY_TYPE_10_E5                                                                          0x11800b0UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define TCM_REG_AFFINITY_TYPE_11_E5                                                                          0x11800b4UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define TCM_REG_AFFINITY_TYPE_12_E5                                                                          0x11800b8UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define TCM_REG_AFFINITY_TYPE_13_E5                                                                          0x11800bcUL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define TCM_REG_AFFINITY_TYPE_14_E5                                                                          0x11800c0UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define TCM_REG_AFFINITY_TYPE_15_E5                                                                          0x11800c4UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define TCM_REG_EXCLUSIVE_FLG_0_E5                                                                           0x11800c8UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define TCM_REG_EXCLUSIVE_FLG_1_E5                                                                           0x11800ccUL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define TCM_REG_EXCLUSIVE_FLG_2_E5                                                                           0x11800d0UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define TCM_REG_EXCLUSIVE_FLG_3_E5                                                                           0x11800d4UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define TCM_REG_EXCLUSIVE_FLG_4_E5                                                                           0x11800d8UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define TCM_REG_EXCLUSIVE_FLG_5_E5                                                                           0x11800dcUL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define TCM_REG_EXCLUSIVE_FLG_6_E5                                                                           0x11800e0UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define TCM_REG_EXCLUSIVE_FLG_7_E5                                                                           0x11800e4UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define TCM_REG_EXCLUSIVE_FLG_8_E5                                                                           0x11800e8UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define TCM_REG_EXCLUSIVE_FLG_9_E5                                                                           0x11800ecUL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define TCM_REG_EXCLUSIVE_FLG_10_E5                                                                          0x11800f0UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define TCM_REG_EXCLUSIVE_FLG_11_E5                                                                          0x11800f4UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define TCM_REG_EXCLUSIVE_FLG_12_E5                                                                          0x11800f8UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define TCM_REG_EXCLUSIVE_FLG_13_E5                                                                          0x11800fcUL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define TCM_REG_EXCLUSIVE_FLG_14_E5                                                                          0x1180100UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define TCM_REG_EXCLUSIVE_FLG_15_E5                                                                          0x1180104UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define TCM_REG_AGG_CON_CF0_Q_BB_K2                                                                          0x1180914UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_CON_CF0_Q_E5                                                                             0x1180108UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define TCM_REG_AGG_CON_CF1_Q_BB_K2                                                                          0x1180918UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_CON_CF1_Q_E5                                                                             0x118010cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define TCM_REG_AGG_CON_CF2_Q_BB_K2                                                                          0x118091cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_CON_CF2_Q_E5                                                                             0x1180110UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define TCM_REG_AGG_CON_CF3_Q_BB_K2                                                                          0x1180920UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_CON_CF3_Q_E5                                                                             0x1180114UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define TCM_REG_AGG_CON_CF4_Q_BB_K2                                                                          0x1180924UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_CON_CF4_Q_E5                                                                             0x1180118UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define TCM_REG_AGG_CON_CF5_Q_BB_K2                                                                          0x1180928UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_CON_CF5_Q_E5                                                                             0x118011cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define TCM_REG_AGG_CON_CF6_Q_BB_K2                                                                          0x118092cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_CON_CF6_Q_E5                                                                             0x1180120UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define TCM_REG_AGG_CON_CF7_Q_BB_K2                                                                          0x1180930UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_CON_CF7_Q_E5                                                                             0x1180124UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define TCM_REG_AGG_CON_CF8_Q_BB_K2                                                                          0x1180934UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_CON_CF8_Q_E5                                                                             0x1180128UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define TCM_REG_AGG_CON_CF9_Q_BB_K2                                                                          0x1180938UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_CON_CF9_Q_E5                                                                             0x118012cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define TCM_REG_AGG_CON_CF10_Q_BB_K2                                                                         0x118093cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_CON_CF10_Q_E5                                                                            0x1180130UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define TCM_REG_AGG_CON_CF11_Q_E5                                                                            0x1180134UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define TCM_REG_INT_STS_0                                                                                    0x1180180UL //Access:R    DataWidth:0x10   // Multi Field Register.
+  #define TCM_REG_INT_STS_0_ADDRESS_ERROR                                                                    (0x1<<0) // Signals an unknown address to the rf module.
+  #define TCM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                              0
+  #define TCM_REG_INT_STS_0_IS_STORM_OVFL_ERR                                                                (0x1<<1) // Write to full STORM input buffer.
+  #define TCM_REG_INT_STS_0_IS_STORM_OVFL_ERR_SHIFT                                                          1
+  #define TCM_REG_INT_STS_0_IS_STORM_UNDER_ERR                                                               (0x1<<2) // Read from empty  STORM input buffer.
+  #define TCM_REG_INT_STS_0_IS_STORM_UNDER_ERR_SHIFT                                                         2
+  #define TCM_REG_INT_STS_0_IS_MSDM_OVFL_ERR_E5                                                              (0x1<<3) // Write to full MSDM input buffer.
+  #define TCM_REG_INT_STS_0_IS_MSDM_OVFL_ERR_E5_SHIFT                                                        3
+  #define TCM_REG_INT_STS_0_IS_MSDM_UNDER_ERR_E5                                                             (0x1<<4) // Read from empty MSDM input buffer.
+  #define TCM_REG_INT_STS_0_IS_MSDM_UNDER_ERR_E5_SHIFT                                                       4
+  #define TCM_REG_INT_STS_0_IS_TSDM_OVFL_ERR_BB_K2                                                           (0x1<<3) // Write to full TSDM input buffer.
+  #define TCM_REG_INT_STS_0_IS_TSDM_OVFL_ERR_BB_K2_SHIFT                                                     3
+  #define TCM_REG_INT_STS_0_IS_TSDM_OVFL_ERR_E5                                                              (0x1<<5) // Write to full TSDM input buffer.
+  #define TCM_REG_INT_STS_0_IS_TSDM_OVFL_ERR_E5_SHIFT                                                        5
+  #define TCM_REG_INT_STS_0_IS_TSDM_UNDER_ERR_BB_K2                                                          (0x1<<4) // Read from empty TSDM input buffer.
+  #define TCM_REG_INT_STS_0_IS_TSDM_UNDER_ERR_BB_K2_SHIFT                                                    4
+  #define TCM_REG_INT_STS_0_IS_TSDM_UNDER_ERR_E5                                                             (0x1<<6) // Read from empty TSDM input buffer.
+  #define TCM_REG_INT_STS_0_IS_TSDM_UNDER_ERR_E5_SHIFT                                                       6
+  #define TCM_REG_INT_STS_0_IS_PSDM_OVFL_ERR_E5                                                              (0x1<<7) // Write to full PSDM input buffer.
+  #define TCM_REG_INT_STS_0_IS_PSDM_OVFL_ERR_E5_SHIFT                                                        7
+  #define TCM_REG_INT_STS_0_IS_PSDM_UNDER_ERR_E5                                                             (0x1<<8) // Read from empty PSDM input buffer.
+  #define TCM_REG_INT_STS_0_IS_PSDM_UNDER_ERR_E5_SHIFT                                                       8
+  #define TCM_REG_INT_STS_0_IS_MSEM_OVFL_ERR_BB_K2                                                           (0x1<<5) // Write to full Msem input buffer.
+  #define TCM_REG_INT_STS_0_IS_MSEM_OVFL_ERR_BB_K2_SHIFT                                                     5
+  #define TCM_REG_INT_STS_0_IS_MSEM_OVFL_ERR_E5                                                              (0x1<<9) // Write to full Msem input buffer.
+  #define TCM_REG_INT_STS_0_IS_MSEM_OVFL_ERR_E5_SHIFT                                                        9
+  #define TCM_REG_INT_STS_0_IS_MSEM_UNDER_ERR_BB_K2                                                          (0x1<<6) // Read from empty  Msem input buffer.
+  #define TCM_REG_INT_STS_0_IS_MSEM_UNDER_ERR_BB_K2_SHIFT                                                    6
+  #define TCM_REG_INT_STS_0_IS_MSEM_UNDER_ERR_E5                                                             (0x1<<10) // Read from empty  Msem input buffer.
+  #define TCM_REG_INT_STS_0_IS_MSEM_UNDER_ERR_E5_SHIFT                                                       10
+  #define TCM_REG_INT_STS_0_IS_YSEM_OVFL_ERR_BB_K2                                                           (0x1<<7) // Write to full Ysem input buffer.
+  #define TCM_REG_INT_STS_0_IS_YSEM_OVFL_ERR_BB_K2_SHIFT                                                     7
+  #define TCM_REG_INT_STS_0_IS_YSEM_OVFL_ERR_E5                                                              (0x1<<11) // Write to full Ysem input buffer.
+  #define TCM_REG_INT_STS_0_IS_YSEM_OVFL_ERR_E5_SHIFT                                                        11
+  #define TCM_REG_INT_STS_0_EXT_LD_UNDER_ERR_E5                                                              (0x1<<12) // Read from empty External read buffer.
+  #define TCM_REG_INT_STS_0_EXT_LD_UNDER_ERR_E5_SHIFT                                                        12
+  #define TCM_REG_INT_STS_0_EXT_LD_OVFL_ERR_E5                                                               (0x1<<13) // Write to fully External read buffer.
+  #define TCM_REG_INT_STS_0_EXT_LD_OVFL_ERR_E5_SHIFT                                                         13
+  #define TCM_REG_INT_STS_0_AFFINITY_TYPE_NO_CON_E5                                                          (0x1<<14) // Affinity type = 2 (connection based) but connection doesn't exist.
+  #define TCM_REG_INT_STS_0_AFFINITY_TYPE_NO_CON_E5_SHIFT                                                    14
+  #define TCM_REG_INT_STS_0_AFFINITY_TYPE_NO_TASK_E5                                                         (0x1<<15) // Affinity type = 3 (task based) but task doesn't exist.
+  #define TCM_REG_INT_STS_0_AFFINITY_TYPE_NO_TASK_E5_SHIFT                                                   15
+#define TCM_REG_INT_MASK_0                                                                                   0x1180184UL //Access:RW   DataWidth:0x10   // Multi Field Register.
+  #define TCM_REG_INT_MASK_0_ADDRESS_ERROR                                                                   (0x1<<0) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.ADDRESS_ERROR .
+  #define TCM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                             0
+  #define TCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR                                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_STORM_OVFL_ERR .
+  #define TCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR_SHIFT                                                         1
+  #define TCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR                                                              (0x1<<2) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_STORM_UNDER_ERR .
+  #define TCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR_SHIFT                                                        2
+  #define TCM_REG_INT_MASK_0_IS_MSDM_OVFL_ERR_E5                                                             (0x1<<3) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_MSDM_OVFL_ERR .
+  #define TCM_REG_INT_MASK_0_IS_MSDM_OVFL_ERR_E5_SHIFT                                                       3
+  #define TCM_REG_INT_MASK_0_IS_MSDM_UNDER_ERR_E5                                                            (0x1<<4) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_MSDM_UNDER_ERR .
+  #define TCM_REG_INT_MASK_0_IS_MSDM_UNDER_ERR_E5_SHIFT                                                      4
+  #define TCM_REG_INT_MASK_0_IS_TSDM_OVFL_ERR_BB_K2                                                          (0x1<<3) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_TSDM_OVFL_ERR .
+  #define TCM_REG_INT_MASK_0_IS_TSDM_OVFL_ERR_BB_K2_SHIFT                                                    3
+  #define TCM_REG_INT_MASK_0_IS_TSDM_OVFL_ERR_E5                                                             (0x1<<5) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_TSDM_OVFL_ERR .
+  #define TCM_REG_INT_MASK_0_IS_TSDM_OVFL_ERR_E5_SHIFT                                                       5
+  #define TCM_REG_INT_MASK_0_IS_TSDM_UNDER_ERR_BB_K2                                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_TSDM_UNDER_ERR .
+  #define TCM_REG_INT_MASK_0_IS_TSDM_UNDER_ERR_BB_K2_SHIFT                                                   4
+  #define TCM_REG_INT_MASK_0_IS_TSDM_UNDER_ERR_E5                                                            (0x1<<6) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_TSDM_UNDER_ERR .
+  #define TCM_REG_INT_MASK_0_IS_TSDM_UNDER_ERR_E5_SHIFT                                                      6
+  #define TCM_REG_INT_MASK_0_IS_PSDM_OVFL_ERR_E5                                                             (0x1<<7) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_PSDM_OVFL_ERR .
+  #define TCM_REG_INT_MASK_0_IS_PSDM_OVFL_ERR_E5_SHIFT                                                       7
+  #define TCM_REG_INT_MASK_0_IS_PSDM_UNDER_ERR_E5                                                            (0x1<<8) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_PSDM_UNDER_ERR .
+  #define TCM_REG_INT_MASK_0_IS_PSDM_UNDER_ERR_E5_SHIFT                                                      8
+  #define TCM_REG_INT_MASK_0_IS_MSEM_OVFL_ERR_BB_K2                                                          (0x1<<5) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_MSEM_OVFL_ERR .
+  #define TCM_REG_INT_MASK_0_IS_MSEM_OVFL_ERR_BB_K2_SHIFT                                                    5
+  #define TCM_REG_INT_MASK_0_IS_MSEM_OVFL_ERR_E5                                                             (0x1<<9) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_MSEM_OVFL_ERR .
+  #define TCM_REG_INT_MASK_0_IS_MSEM_OVFL_ERR_E5_SHIFT                                                       9
+  #define TCM_REG_INT_MASK_0_IS_MSEM_UNDER_ERR_BB_K2                                                         (0x1<<6) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_MSEM_UNDER_ERR .
+  #define TCM_REG_INT_MASK_0_IS_MSEM_UNDER_ERR_BB_K2_SHIFT                                                   6
+  #define TCM_REG_INT_MASK_0_IS_MSEM_UNDER_ERR_E5                                                            (0x1<<10) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_MSEM_UNDER_ERR .
+  #define TCM_REG_INT_MASK_0_IS_MSEM_UNDER_ERR_E5_SHIFT                                                      10
+  #define TCM_REG_INT_MASK_0_IS_YSEM_OVFL_ERR_BB_K2                                                          (0x1<<7) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_YSEM_OVFL_ERR .
+  #define TCM_REG_INT_MASK_0_IS_YSEM_OVFL_ERR_BB_K2_SHIFT                                                    7
+  #define TCM_REG_INT_MASK_0_IS_YSEM_OVFL_ERR_E5                                                             (0x1<<11) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_YSEM_OVFL_ERR .
+  #define TCM_REG_INT_MASK_0_IS_YSEM_OVFL_ERR_E5_SHIFT                                                       11
+  #define TCM_REG_INT_MASK_0_EXT_LD_UNDER_ERR_E5                                                             (0x1<<12) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.EXT_LD_UNDER_ERR .
+  #define TCM_REG_INT_MASK_0_EXT_LD_UNDER_ERR_E5_SHIFT                                                       12
+  #define TCM_REG_INT_MASK_0_EXT_LD_OVFL_ERR_E5                                                              (0x1<<13) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.EXT_LD_OVFL_ERR .
+  #define TCM_REG_INT_MASK_0_EXT_LD_OVFL_ERR_E5_SHIFT                                                        13
+  #define TCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_CON_E5                                                         (0x1<<14) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.AFFINITY_TYPE_NO_CON .
+  #define TCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_CON_E5_SHIFT                                                   14
+  #define TCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_TASK_E5                                                        (0x1<<15) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.AFFINITY_TYPE_NO_TASK .
+  #define TCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_TASK_E5_SHIFT                                                  15
+#define TCM_REG_INT_STS_WR_0                                                                                 0x1180188UL //Access:WR   DataWidth:0x10   // Multi Field Register.
+  #define TCM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define TCM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                           0
+  #define TCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR                                                             (0x1<<1) // Write to full STORM input buffer.
+  #define TCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR_SHIFT                                                       1
+  #define TCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR                                                            (0x1<<2) // Read from empty  STORM input buffer.
+  #define TCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR_SHIFT                                                      2
+  #define TCM_REG_INT_STS_WR_0_IS_MSDM_OVFL_ERR_E5                                                           (0x1<<3) // Write to full MSDM input buffer.
+  #define TCM_REG_INT_STS_WR_0_IS_MSDM_OVFL_ERR_E5_SHIFT                                                     3
+  #define TCM_REG_INT_STS_WR_0_IS_MSDM_UNDER_ERR_E5                                                          (0x1<<4) // Read from empty MSDM input buffer.
+  #define TCM_REG_INT_STS_WR_0_IS_MSDM_UNDER_ERR_E5_SHIFT                                                    4
+  #define TCM_REG_INT_STS_WR_0_IS_TSDM_OVFL_ERR_BB_K2                                                        (0x1<<3) // Write to full TSDM input buffer.
+  #define TCM_REG_INT_STS_WR_0_IS_TSDM_OVFL_ERR_BB_K2_SHIFT                                                  3
+  #define TCM_REG_INT_STS_WR_0_IS_TSDM_OVFL_ERR_E5                                                           (0x1<<5) // Write to full TSDM input buffer.
+  #define TCM_REG_INT_STS_WR_0_IS_TSDM_OVFL_ERR_E5_SHIFT                                                     5
+  #define TCM_REG_INT_STS_WR_0_IS_TSDM_UNDER_ERR_BB_K2                                                       (0x1<<4) // Read from empty TSDM input buffer.
+  #define TCM_REG_INT_STS_WR_0_IS_TSDM_UNDER_ERR_BB_K2_SHIFT                                                 4
+  #define TCM_REG_INT_STS_WR_0_IS_TSDM_UNDER_ERR_E5                                                          (0x1<<6) // Read from empty TSDM input buffer.
+  #define TCM_REG_INT_STS_WR_0_IS_TSDM_UNDER_ERR_E5_SHIFT                                                    6
+  #define TCM_REG_INT_STS_WR_0_IS_PSDM_OVFL_ERR_E5                                                           (0x1<<7) // Write to full PSDM input buffer.
+  #define TCM_REG_INT_STS_WR_0_IS_PSDM_OVFL_ERR_E5_SHIFT                                                     7
+  #define TCM_REG_INT_STS_WR_0_IS_PSDM_UNDER_ERR_E5                                                          (0x1<<8) // Read from empty PSDM input buffer.
+  #define TCM_REG_INT_STS_WR_0_IS_PSDM_UNDER_ERR_E5_SHIFT                                                    8
+  #define TCM_REG_INT_STS_WR_0_IS_MSEM_OVFL_ERR_BB_K2                                                        (0x1<<5) // Write to full Msem input buffer.
+  #define TCM_REG_INT_STS_WR_0_IS_MSEM_OVFL_ERR_BB_K2_SHIFT                                                  5
+  #define TCM_REG_INT_STS_WR_0_IS_MSEM_OVFL_ERR_E5                                                           (0x1<<9) // Write to full Msem input buffer.
+  #define TCM_REG_INT_STS_WR_0_IS_MSEM_OVFL_ERR_E5_SHIFT                                                     9
+  #define TCM_REG_INT_STS_WR_0_IS_MSEM_UNDER_ERR_BB_K2                                                       (0x1<<6) // Read from empty  Msem input buffer.
+  #define TCM_REG_INT_STS_WR_0_IS_MSEM_UNDER_ERR_BB_K2_SHIFT                                                 6
+  #define TCM_REG_INT_STS_WR_0_IS_MSEM_UNDER_ERR_E5                                                          (0x1<<10) // Read from empty  Msem input buffer.
+  #define TCM_REG_INT_STS_WR_0_IS_MSEM_UNDER_ERR_E5_SHIFT                                                    10
+  #define TCM_REG_INT_STS_WR_0_IS_YSEM_OVFL_ERR_BB_K2                                                        (0x1<<7) // Write to full Ysem input buffer.
+  #define TCM_REG_INT_STS_WR_0_IS_YSEM_OVFL_ERR_BB_K2_SHIFT                                                  7
+  #define TCM_REG_INT_STS_WR_0_IS_YSEM_OVFL_ERR_E5                                                           (0x1<<11) // Write to full Ysem input buffer.
+  #define TCM_REG_INT_STS_WR_0_IS_YSEM_OVFL_ERR_E5_SHIFT                                                     11
+  #define TCM_REG_INT_STS_WR_0_EXT_LD_UNDER_ERR_E5                                                           (0x1<<12) // Read from empty External read buffer.
+  #define TCM_REG_INT_STS_WR_0_EXT_LD_UNDER_ERR_E5_SHIFT                                                     12
+  #define TCM_REG_INT_STS_WR_0_EXT_LD_OVFL_ERR_E5                                                            (0x1<<13) // Write to fully External read buffer.
+  #define TCM_REG_INT_STS_WR_0_EXT_LD_OVFL_ERR_E5_SHIFT                                                      13
+  #define TCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_CON_E5                                                       (0x1<<14) // Affinity type = 2 (connection based) but connection doesn't exist.
+  #define TCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_CON_E5_SHIFT                                                 14
+  #define TCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_TASK_E5                                                      (0x1<<15) // Affinity type = 3 (task based) but task doesn't exist.
+  #define TCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_TASK_E5_SHIFT                                                15
+#define TCM_REG_INT_STS_CLR_0                                                                                0x118018cUL //Access:RC   DataWidth:0x10   // Multi Field Register.
+  #define TCM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define TCM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                          0
+  #define TCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR                                                            (0x1<<1) // Write to full STORM input buffer.
+  #define TCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR_SHIFT                                                      1
+  #define TCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR                                                           (0x1<<2) // Read from empty  STORM input buffer.
+  #define TCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR_SHIFT                                                     2
+  #define TCM_REG_INT_STS_CLR_0_IS_MSDM_OVFL_ERR_E5                                                          (0x1<<3) // Write to full MSDM input buffer.
+  #define TCM_REG_INT_STS_CLR_0_IS_MSDM_OVFL_ERR_E5_SHIFT                                                    3
+  #define TCM_REG_INT_STS_CLR_0_IS_MSDM_UNDER_ERR_E5                                                         (0x1<<4) // Read from empty MSDM input buffer.
+  #define TCM_REG_INT_STS_CLR_0_IS_MSDM_UNDER_ERR_E5_SHIFT                                                   4
+  #define TCM_REG_INT_STS_CLR_0_IS_TSDM_OVFL_ERR_BB_K2                                                       (0x1<<3) // Write to full TSDM input buffer.
+  #define TCM_REG_INT_STS_CLR_0_IS_TSDM_OVFL_ERR_BB_K2_SHIFT                                                 3
+  #define TCM_REG_INT_STS_CLR_0_IS_TSDM_OVFL_ERR_E5                                                          (0x1<<5) // Write to full TSDM input buffer.
+  #define TCM_REG_INT_STS_CLR_0_IS_TSDM_OVFL_ERR_E5_SHIFT                                                    5
+  #define TCM_REG_INT_STS_CLR_0_IS_TSDM_UNDER_ERR_BB_K2                                                      (0x1<<4) // Read from empty TSDM input buffer.
+  #define TCM_REG_INT_STS_CLR_0_IS_TSDM_UNDER_ERR_BB_K2_SHIFT                                                4
+  #define TCM_REG_INT_STS_CLR_0_IS_TSDM_UNDER_ERR_E5                                                         (0x1<<6) // Read from empty TSDM input buffer.
+  #define TCM_REG_INT_STS_CLR_0_IS_TSDM_UNDER_ERR_E5_SHIFT                                                   6
+  #define TCM_REG_INT_STS_CLR_0_IS_PSDM_OVFL_ERR_E5                                                          (0x1<<7) // Write to full PSDM input buffer.
+  #define TCM_REG_INT_STS_CLR_0_IS_PSDM_OVFL_ERR_E5_SHIFT                                                    7
+  #define TCM_REG_INT_STS_CLR_0_IS_PSDM_UNDER_ERR_E5                                                         (0x1<<8) // Read from empty PSDM input buffer.
+  #define TCM_REG_INT_STS_CLR_0_IS_PSDM_UNDER_ERR_E5_SHIFT                                                   8
+  #define TCM_REG_INT_STS_CLR_0_IS_MSEM_OVFL_ERR_BB_K2                                                       (0x1<<5) // Write to full Msem input buffer.
+  #define TCM_REG_INT_STS_CLR_0_IS_MSEM_OVFL_ERR_BB_K2_SHIFT                                                 5
+  #define TCM_REG_INT_STS_CLR_0_IS_MSEM_OVFL_ERR_E5                                                          (0x1<<9) // Write to full Msem input buffer.
+  #define TCM_REG_INT_STS_CLR_0_IS_MSEM_OVFL_ERR_E5_SHIFT                                                    9
+  #define TCM_REG_INT_STS_CLR_0_IS_MSEM_UNDER_ERR_BB_K2                                                      (0x1<<6) // Read from empty  Msem input buffer.
+  #define TCM_REG_INT_STS_CLR_0_IS_MSEM_UNDER_ERR_BB_K2_SHIFT                                                6
+  #define TCM_REG_INT_STS_CLR_0_IS_MSEM_UNDER_ERR_E5                                                         (0x1<<10) // Read from empty  Msem input buffer.
+  #define TCM_REG_INT_STS_CLR_0_IS_MSEM_UNDER_ERR_E5_SHIFT                                                   10
+  #define TCM_REG_INT_STS_CLR_0_IS_YSEM_OVFL_ERR_BB_K2                                                       (0x1<<7) // Write to full Ysem input buffer.
+  #define TCM_REG_INT_STS_CLR_0_IS_YSEM_OVFL_ERR_BB_K2_SHIFT                                                 7
+  #define TCM_REG_INT_STS_CLR_0_IS_YSEM_OVFL_ERR_E5                                                          (0x1<<11) // Write to full Ysem input buffer.
+  #define TCM_REG_INT_STS_CLR_0_IS_YSEM_OVFL_ERR_E5_SHIFT                                                    11
+  #define TCM_REG_INT_STS_CLR_0_EXT_LD_UNDER_ERR_E5                                                          (0x1<<12) // Read from empty External read buffer.
+  #define TCM_REG_INT_STS_CLR_0_EXT_LD_UNDER_ERR_E5_SHIFT                                                    12
+  #define TCM_REG_INT_STS_CLR_0_EXT_LD_OVFL_ERR_E5                                                           (0x1<<13) // Write to fully External read buffer.
+  #define TCM_REG_INT_STS_CLR_0_EXT_LD_OVFL_ERR_E5_SHIFT                                                     13
+  #define TCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_CON_E5                                                      (0x1<<14) // Affinity type = 2 (connection based) but connection doesn't exist.
+  #define TCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_CON_E5_SHIFT                                                14
+  #define TCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_TASK_E5                                                     (0x1<<15) // Affinity type = 3 (task based) but task doesn't exist.
+  #define TCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_TASK_E5_SHIFT                                               15
+#define TCM_REG_INT_STS_1                                                                                    0x1180190UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define TCM_REG_INT_STS_1_IS_YSEM_UNDER_ERR                                                                (0x1<<0) // Read from empty  Ysem input buffer.
+  #define TCM_REG_INT_STS_1_IS_YSEM_UNDER_ERR_SHIFT                                                          0
+  #define TCM_REG_INT_STS_1_IS_DORQ_OVFL_ERR                                                                 (0x1<<1) // Write to full Dorq input buffer.
+  #define TCM_REG_INT_STS_1_IS_DORQ_OVFL_ERR_SHIFT                                                           1
+  #define TCM_REG_INT_STS_1_IS_DORQ_UNDER_ERR                                                                (0x1<<2) // Read from empty  Dorq input buffer.
+  #define TCM_REG_INT_STS_1_IS_DORQ_UNDER_ERR_SHIFT                                                          2
+  #define TCM_REG_INT_STS_1_IS_PBF_OVFL_ERR                                                                  (0x1<<3) // Write to full Pbf input buffer.
+  #define TCM_REG_INT_STS_1_IS_PBF_OVFL_ERR_SHIFT                                                            3
+  #define TCM_REG_INT_STS_1_IS_PBF_UNDER_ERR                                                                 (0x1<<4) // Read from empty Pbf input buffer.
+  #define TCM_REG_INT_STS_1_IS_PBF_UNDER_ERR_SHIFT                                                           4
+  #define TCM_REG_INT_STS_1_IS_PTLD_OVFL_ERR_E5                                                              (0x1<<5) // Write to full PTLD input buffer.
+  #define TCM_REG_INT_STS_1_IS_PTLD_OVFL_ERR_E5_SHIFT                                                        5
+  #define TCM_REG_INT_STS_1_IS_PTLD_UNDER_ERR_E5                                                             (0x1<<6) // Read from empty PTLD input buffer.
+  #define TCM_REG_INT_STS_1_IS_PTLD_UNDER_ERR_E5_SHIFT                                                       6
+  #define TCM_REG_INT_STS_1_IS_TM_OVFL_ERR                                                                   (0x1<<7) // Write to full TM input buffer.
+  #define TCM_REG_INT_STS_1_IS_TM_OVFL_ERR_SHIFT                                                             7
+  #define TCM_REG_INT_STS_1_IS_TM_UNDER_ERR                                                                  (0x1<<8) // Read from empty TM input buffer.
+  #define TCM_REG_INT_STS_1_IS_TM_UNDER_ERR_SHIFT                                                            8
+  #define TCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR                                                                 (0x1<<9) // Write to full QM input buffer.
+  #define TCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR_SHIFT                                                           9
+  #define TCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR                                                                (0x1<<10) // Read from empty QM input buffer.
+  #define TCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR_SHIFT                                                          10
+  #define TCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR                                                                 (0x1<<11) // Write to full QM input buffer.
+  #define TCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR_SHIFT                                                           11
+  #define TCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR                                                                (0x1<<12) // Read from empty QM input buffer.
+  #define TCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR_SHIFT                                                          12
+  #define TCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0                                                                 (0x1<<13) // Write to full GRC input buffer bits [31:0].
+  #define TCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0_SHIFT                                                           13
+  #define TCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0                                                                (0x1<<14) // Read from empty  GRC input buffer bits [31:0].
+  #define TCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0_SHIFT                                                          14
+  #define TCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1                                                                 (0x1<<15) // Write to full GRC input buffer bits [63:32].
+  #define TCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1_SHIFT                                                           15
+  #define TCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1                                                                (0x1<<16) // Read from empty  GRC input buffer bits [63:32].
+  #define TCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1_SHIFT                                                          16
+  #define TCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2                                                                 (0x1<<17) // Write to full GRC input buffer bits [95:64].
+  #define TCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2_SHIFT                                                           17
+  #define TCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2                                                                (0x1<<18) // Read from empty  GRC input buffer bits [95:64].
+  #define TCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2_SHIFT                                                          18
+  #define TCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3                                                                 (0x1<<19) // Write to full GRC input buffer bits [127:96].
+  #define TCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3_SHIFT                                                           19
+  #define TCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3                                                                (0x1<<20) // Read from empty  GRC input buffer bits [127:96].
+  #define TCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3_SHIFT                                                          20
+  #define TCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL                                                                 (0x1<<21) // In-process Table overflow.
+  #define TCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL_SHIFT                                                           21
+  #define TCM_REG_INT_STS_1_AGG_CON_DATA_BUF_OVFL                                                            (0x1<<22) // Message Processor Aggregation Connection Data buffer overflow.
+  #define TCM_REG_INT_STS_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                                      22
+  #define TCM_REG_INT_STS_1_AGG_CON_CMD_BUF_OVFL                                                             (0x1<<23) // Message Processor Aggregation Connection Command buffer overflow.
+  #define TCM_REG_INT_STS_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                                       23
+  #define TCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL                                                             (0x1<<24) // Message Processor Storm Connection Data buffer overflow.
+  #define TCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL_SHIFT                                                       24
+  #define TCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL                                                              (0x1<<25) // Message Processor Storm Connection Command buffer overflow.
+  #define TCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL_SHIFT                                                        25
+  #define TCM_REG_INT_STS_1_AGG_TASK_DATA_BUF_OVFL                                                           (0x1<<26) // Message Processor Aggregation Task Data buffer overflow.
+  #define TCM_REG_INT_STS_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                                     26
+  #define TCM_REG_INT_STS_1_AGG_TASK_CMD_BUF_OVFL                                                            (0x1<<27) // Message Processor Aggregation Task Command buffer overflow.
+  #define TCM_REG_INT_STS_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                                      27
+  #define TCM_REG_INT_STS_1_SM_TASK_DATA_BUF_OVFL                                                            (0x1<<28) // Message Processor Storm Task Data buffer overflow.
+  #define TCM_REG_INT_STS_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                                      28
+  #define TCM_REG_INT_STS_1_SM_TASK_CMD_BUF_OVFL                                                             (0x1<<29) // Message Processor Storm Task Command buffer overflow.
+  #define TCM_REG_INT_STS_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                                       29
+  #define TCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE                                                            (0x1<<30) // Input message first descriptor fields violation.
+  #define TCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE_SHIFT                                                      30
+  #define TCM_REG_INT_STS_1_SE_DESC_INPUT_VIOLATE                                                            (0x1<<31) // Input message second descriptor fields violation.
+  #define TCM_REG_INT_STS_1_SE_DESC_INPUT_VIOLATE_SHIFT                                                      31
+  #define TCM_REG_INT_STS_1_IS_PRS_OVFL_ERR_BB_K2                                                            (0x1<<5) // Write to full Pbf input buffer.
+  #define TCM_REG_INT_STS_1_IS_PRS_OVFL_ERR_BB_K2_SHIFT                                                      5
+  #define TCM_REG_INT_STS_1_IS_PRS_UNDER_ERR_BB_K2                                                           (0x1<<6) // Read from empty Pbf input buffer.
+  #define TCM_REG_INT_STS_1_IS_PRS_UNDER_ERR_BB_K2_SHIFT                                                     6
+#define TCM_REG_INT_MASK_1                                                                                   0x1180194UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define TCM_REG_INT_MASK_1_IS_YSEM_UNDER_ERR                                                               (0x1<<0) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_YSEM_UNDER_ERR .
+  #define TCM_REG_INT_MASK_1_IS_YSEM_UNDER_ERR_SHIFT                                                         0
+  #define TCM_REG_INT_MASK_1_IS_DORQ_OVFL_ERR                                                                (0x1<<1) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_DORQ_OVFL_ERR .
+  #define TCM_REG_INT_MASK_1_IS_DORQ_OVFL_ERR_SHIFT                                                          1
+  #define TCM_REG_INT_MASK_1_IS_DORQ_UNDER_ERR                                                               (0x1<<2) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_DORQ_UNDER_ERR .
+  #define TCM_REG_INT_MASK_1_IS_DORQ_UNDER_ERR_SHIFT                                                         2
+  #define TCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR                                                                 (0x1<<3) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_PBF_OVFL_ERR .
+  #define TCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR_SHIFT                                                           3
+  #define TCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR                                                                (0x1<<4) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_PBF_UNDER_ERR .
+  #define TCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR_SHIFT                                                          4
+  #define TCM_REG_INT_MASK_1_IS_PTLD_OVFL_ERR_E5                                                             (0x1<<5) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_PTLD_OVFL_ERR .
+  #define TCM_REG_INT_MASK_1_IS_PTLD_OVFL_ERR_E5_SHIFT                                                       5
+  #define TCM_REG_INT_MASK_1_IS_PTLD_UNDER_ERR_E5                                                            (0x1<<6) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_PTLD_UNDER_ERR .
+  #define TCM_REG_INT_MASK_1_IS_PTLD_UNDER_ERR_E5_SHIFT                                                      6
+  #define TCM_REG_INT_MASK_1_IS_TM_OVFL_ERR                                                                  (0x1<<7) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_TM_OVFL_ERR .
+  #define TCM_REG_INT_MASK_1_IS_TM_OVFL_ERR_SHIFT                                                            7
+  #define TCM_REG_INT_MASK_1_IS_TM_UNDER_ERR                                                                 (0x1<<8) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_TM_UNDER_ERR .
+  #define TCM_REG_INT_MASK_1_IS_TM_UNDER_ERR_SHIFT                                                           8
+  #define TCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR                                                                (0x1<<9) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_QM_P_OVFL_ERR .
+  #define TCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR_SHIFT                                                          9
+  #define TCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR                                                               (0x1<<10) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_QM_P_UNDER_ERR .
+  #define TCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR_SHIFT                                                         10
+  #define TCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR                                                                (0x1<<11) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_QM_S_OVFL_ERR .
+  #define TCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR_SHIFT                                                          11
+  #define TCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR                                                               (0x1<<12) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_QM_S_UNDER_ERR .
+  #define TCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR_SHIFT                                                         12
+  #define TCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0                                                                (0x1<<13) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_GRC_OVFL_ERR0 .
+  #define TCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0_SHIFT                                                          13
+  #define TCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0                                                               (0x1<<14) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_GRC_UNDER_ERR0 .
+  #define TCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0_SHIFT                                                         14
+  #define TCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1                                                                (0x1<<15) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_GRC_OVFL_ERR1 .
+  #define TCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1_SHIFT                                                          15
+  #define TCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1                                                               (0x1<<16) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_GRC_UNDER_ERR1 .
+  #define TCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1_SHIFT                                                         16
+  #define TCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2                                                                (0x1<<17) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_GRC_OVFL_ERR2 .
+  #define TCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2_SHIFT                                                          17
+  #define TCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2                                                               (0x1<<18) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_GRC_UNDER_ERR2 .
+  #define TCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2_SHIFT                                                         18
+  #define TCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3                                                                (0x1<<19) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_GRC_OVFL_ERR3 .
+  #define TCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3_SHIFT                                                          19
+  #define TCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3                                                               (0x1<<20) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_GRC_UNDER_ERR3 .
+  #define TCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3_SHIFT                                                         20
+  #define TCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL                                                                (0x1<<21) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IN_PRCS_TBL_OVFL .
+  #define TCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL_SHIFT                                                          21
+  #define TCM_REG_INT_MASK_1_AGG_CON_DATA_BUF_OVFL                                                           (0x1<<22) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.AGG_CON_DATA_BUF_OVFL .
+  #define TCM_REG_INT_MASK_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                                     22
+  #define TCM_REG_INT_MASK_1_AGG_CON_CMD_BUF_OVFL                                                            (0x1<<23) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.AGG_CON_CMD_BUF_OVFL .
+  #define TCM_REG_INT_MASK_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                                      23
+  #define TCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL                                                            (0x1<<24) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.SM_CON_DATA_BUF_OVFL .
+  #define TCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL_SHIFT                                                      24
+  #define TCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL                                                             (0x1<<25) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.SM_CON_CMD_BUF_OVFL .
+  #define TCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL_SHIFT                                                       25
+  #define TCM_REG_INT_MASK_1_AGG_TASK_DATA_BUF_OVFL                                                          (0x1<<26) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.AGG_TASK_DATA_BUF_OVFL .
+  #define TCM_REG_INT_MASK_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                                    26
+  #define TCM_REG_INT_MASK_1_AGG_TASK_CMD_BUF_OVFL                                                           (0x1<<27) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.AGG_TASK_CMD_BUF_OVFL .
+  #define TCM_REG_INT_MASK_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                                     27
+  #define TCM_REG_INT_MASK_1_SM_TASK_DATA_BUF_OVFL                                                           (0x1<<28) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.SM_TASK_DATA_BUF_OVFL .
+  #define TCM_REG_INT_MASK_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                                     28
+  #define TCM_REG_INT_MASK_1_SM_TASK_CMD_BUF_OVFL                                                            (0x1<<29) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.SM_TASK_CMD_BUF_OVFL .
+  #define TCM_REG_INT_MASK_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                                      29
+  #define TCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE                                                           (0x1<<30) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.FI_DESC_INPUT_VIOLATE .
+  #define TCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE_SHIFT                                                     30
+  #define TCM_REG_INT_MASK_1_SE_DESC_INPUT_VIOLATE                                                           (0x1<<31) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.SE_DESC_INPUT_VIOLATE .
+  #define TCM_REG_INT_MASK_1_SE_DESC_INPUT_VIOLATE_SHIFT                                                     31
+  #define TCM_REG_INT_MASK_1_IS_PRS_OVFL_ERR_BB_K2                                                           (0x1<<5) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_PRS_OVFL_ERR .
+  #define TCM_REG_INT_MASK_1_IS_PRS_OVFL_ERR_BB_K2_SHIFT                                                     5
+  #define TCM_REG_INT_MASK_1_IS_PRS_UNDER_ERR_BB_K2                                                          (0x1<<6) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_PRS_UNDER_ERR .
+  #define TCM_REG_INT_MASK_1_IS_PRS_UNDER_ERR_BB_K2_SHIFT                                                    6
+#define TCM_REG_INT_STS_WR_1                                                                                 0x1180198UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define TCM_REG_INT_STS_WR_1_IS_YSEM_UNDER_ERR                                                             (0x1<<0) // Read from empty  Ysem input buffer.
+  #define TCM_REG_INT_STS_WR_1_IS_YSEM_UNDER_ERR_SHIFT                                                       0
+  #define TCM_REG_INT_STS_WR_1_IS_DORQ_OVFL_ERR                                                              (0x1<<1) // Write to full Dorq input buffer.
+  #define TCM_REG_INT_STS_WR_1_IS_DORQ_OVFL_ERR_SHIFT                                                        1
+  #define TCM_REG_INT_STS_WR_1_IS_DORQ_UNDER_ERR                                                             (0x1<<2) // Read from empty  Dorq input buffer.
+  #define TCM_REG_INT_STS_WR_1_IS_DORQ_UNDER_ERR_SHIFT                                                       2
+  #define TCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR                                                               (0x1<<3) // Write to full Pbf input buffer.
+  #define TCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR_SHIFT                                                         3
+  #define TCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR                                                              (0x1<<4) // Read from empty Pbf input buffer.
+  #define TCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR_SHIFT                                                        4
+  #define TCM_REG_INT_STS_WR_1_IS_PTLD_OVFL_ERR_E5                                                           (0x1<<5) // Write to full PTLD input buffer.
+  #define TCM_REG_INT_STS_WR_1_IS_PTLD_OVFL_ERR_E5_SHIFT                                                     5
+  #define TCM_REG_INT_STS_WR_1_IS_PTLD_UNDER_ERR_E5                                                          (0x1<<6) // Read from empty PTLD input buffer.
+  #define TCM_REG_INT_STS_WR_1_IS_PTLD_UNDER_ERR_E5_SHIFT                                                    6
+  #define TCM_REG_INT_STS_WR_1_IS_TM_OVFL_ERR                                                                (0x1<<7) // Write to full TM input buffer.
+  #define TCM_REG_INT_STS_WR_1_IS_TM_OVFL_ERR_SHIFT                                                          7
+  #define TCM_REG_INT_STS_WR_1_IS_TM_UNDER_ERR                                                               (0x1<<8) // Read from empty TM input buffer.
+  #define TCM_REG_INT_STS_WR_1_IS_TM_UNDER_ERR_SHIFT                                                         8
+  #define TCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR                                                              (0x1<<9) // Write to full QM input buffer.
+  #define TCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR_SHIFT                                                        9
+  #define TCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR                                                             (0x1<<10) // Read from empty QM input buffer.
+  #define TCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR_SHIFT                                                       10
+  #define TCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR                                                              (0x1<<11) // Write to full QM input buffer.
+  #define TCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR_SHIFT                                                        11
+  #define TCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR                                                             (0x1<<12) // Read from empty QM input buffer.
+  #define TCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR_SHIFT                                                       12
+  #define TCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0                                                              (0x1<<13) // Write to full GRC input buffer bits [31:0].
+  #define TCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0_SHIFT                                                        13
+  #define TCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0                                                             (0x1<<14) // Read from empty  GRC input buffer bits [31:0].
+  #define TCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0_SHIFT                                                       14
+  #define TCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1                                                              (0x1<<15) // Write to full GRC input buffer bits [63:32].
+  #define TCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1_SHIFT                                                        15
+  #define TCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1                                                             (0x1<<16) // Read from empty  GRC input buffer bits [63:32].
+  #define TCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1_SHIFT                                                       16
+  #define TCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2                                                              (0x1<<17) // Write to full GRC input buffer bits [95:64].
+  #define TCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2_SHIFT                                                        17
+  #define TCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2                                                             (0x1<<18) // Read from empty  GRC input buffer bits [95:64].
+  #define TCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2_SHIFT                                                       18
+  #define TCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3                                                              (0x1<<19) // Write to full GRC input buffer bits [127:96].
+  #define TCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3_SHIFT                                                        19
+  #define TCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3                                                             (0x1<<20) // Read from empty  GRC input buffer bits [127:96].
+  #define TCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3_SHIFT                                                       20
+  #define TCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL                                                              (0x1<<21) // In-process Table overflow.
+  #define TCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL_SHIFT                                                        21
+  #define TCM_REG_INT_STS_WR_1_AGG_CON_DATA_BUF_OVFL                                                         (0x1<<22) // Message Processor Aggregation Connection Data buffer overflow.
+  #define TCM_REG_INT_STS_WR_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                                   22
+  #define TCM_REG_INT_STS_WR_1_AGG_CON_CMD_BUF_OVFL                                                          (0x1<<23) // Message Processor Aggregation Connection Command buffer overflow.
+  #define TCM_REG_INT_STS_WR_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                                    23
+  #define TCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL                                                          (0x1<<24) // Message Processor Storm Connection Data buffer overflow.
+  #define TCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL_SHIFT                                                    24
+  #define TCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL                                                           (0x1<<25) // Message Processor Storm Connection Command buffer overflow.
+  #define TCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL_SHIFT                                                     25
+  #define TCM_REG_INT_STS_WR_1_AGG_TASK_DATA_BUF_OVFL                                                        (0x1<<26) // Message Processor Aggregation Task Data buffer overflow.
+  #define TCM_REG_INT_STS_WR_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                                  26
+  #define TCM_REG_INT_STS_WR_1_AGG_TASK_CMD_BUF_OVFL                                                         (0x1<<27) // Message Processor Aggregation Task Command buffer overflow.
+  #define TCM_REG_INT_STS_WR_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                                   27
+  #define TCM_REG_INT_STS_WR_1_SM_TASK_DATA_BUF_OVFL                                                         (0x1<<28) // Message Processor Storm Task Data buffer overflow.
+  #define TCM_REG_INT_STS_WR_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                                   28
+  #define TCM_REG_INT_STS_WR_1_SM_TASK_CMD_BUF_OVFL                                                          (0x1<<29) // Message Processor Storm Task Command buffer overflow.
+  #define TCM_REG_INT_STS_WR_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                                    29
+  #define TCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE                                                         (0x1<<30) // Input message first descriptor fields violation.
+  #define TCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE_SHIFT                                                   30
+  #define TCM_REG_INT_STS_WR_1_SE_DESC_INPUT_VIOLATE                                                         (0x1<<31) // Input message second descriptor fields violation.
+  #define TCM_REG_INT_STS_WR_1_SE_DESC_INPUT_VIOLATE_SHIFT                                                   31
+  #define TCM_REG_INT_STS_WR_1_IS_PRS_OVFL_ERR_BB_K2                                                         (0x1<<5) // Write to full Pbf input buffer.
+  #define TCM_REG_INT_STS_WR_1_IS_PRS_OVFL_ERR_BB_K2_SHIFT                                                   5
+  #define TCM_REG_INT_STS_WR_1_IS_PRS_UNDER_ERR_BB_K2                                                        (0x1<<6) // Read from empty Pbf input buffer.
+  #define TCM_REG_INT_STS_WR_1_IS_PRS_UNDER_ERR_BB_K2_SHIFT                                                  6
+#define TCM_REG_INT_STS_CLR_1                                                                                0x118019cUL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define TCM_REG_INT_STS_CLR_1_IS_YSEM_UNDER_ERR                                                            (0x1<<0) // Read from empty  Ysem input buffer.
+  #define TCM_REG_INT_STS_CLR_1_IS_YSEM_UNDER_ERR_SHIFT                                                      0
+  #define TCM_REG_INT_STS_CLR_1_IS_DORQ_OVFL_ERR                                                             (0x1<<1) // Write to full Dorq input buffer.
+  #define TCM_REG_INT_STS_CLR_1_IS_DORQ_OVFL_ERR_SHIFT                                                       1
+  #define TCM_REG_INT_STS_CLR_1_IS_DORQ_UNDER_ERR                                                            (0x1<<2) // Read from empty  Dorq input buffer.
+  #define TCM_REG_INT_STS_CLR_1_IS_DORQ_UNDER_ERR_SHIFT                                                      2
+  #define TCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR                                                              (0x1<<3) // Write to full Pbf input buffer.
+  #define TCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR_SHIFT                                                        3
+  #define TCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR                                                             (0x1<<4) // Read from empty Pbf input buffer.
+  #define TCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR_SHIFT                                                       4
+  #define TCM_REG_INT_STS_CLR_1_IS_PTLD_OVFL_ERR_E5                                                          (0x1<<5) // Write to full PTLD input buffer.
+  #define TCM_REG_INT_STS_CLR_1_IS_PTLD_OVFL_ERR_E5_SHIFT                                                    5
+  #define TCM_REG_INT_STS_CLR_1_IS_PTLD_UNDER_ERR_E5                                                         (0x1<<6) // Read from empty PTLD input buffer.
+  #define TCM_REG_INT_STS_CLR_1_IS_PTLD_UNDER_ERR_E5_SHIFT                                                   6
+  #define TCM_REG_INT_STS_CLR_1_IS_TM_OVFL_ERR                                                               (0x1<<7) // Write to full TM input buffer.
+  #define TCM_REG_INT_STS_CLR_1_IS_TM_OVFL_ERR_SHIFT                                                         7
+  #define TCM_REG_INT_STS_CLR_1_IS_TM_UNDER_ERR                                                              (0x1<<8) // Read from empty TM input buffer.
+  #define TCM_REG_INT_STS_CLR_1_IS_TM_UNDER_ERR_SHIFT                                                        8
+  #define TCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR                                                             (0x1<<9) // Write to full QM input buffer.
+  #define TCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR_SHIFT                                                       9
+  #define TCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR                                                            (0x1<<10) // Read from empty QM input buffer.
+  #define TCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR_SHIFT                                                      10
+  #define TCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR                                                             (0x1<<11) // Write to full QM input buffer.
+  #define TCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR_SHIFT                                                       11
+  #define TCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR                                                            (0x1<<12) // Read from empty QM input buffer.
+  #define TCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR_SHIFT                                                      12
+  #define TCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0                                                             (0x1<<13) // Write to full GRC input buffer bits [31:0].
+  #define TCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0_SHIFT                                                       13
+  #define TCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0                                                            (0x1<<14) // Read from empty  GRC input buffer bits [31:0].
+  #define TCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0_SHIFT                                                      14
+  #define TCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1                                                             (0x1<<15) // Write to full GRC input buffer bits [63:32].
+  #define TCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1_SHIFT                                                       15
+  #define TCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1                                                            (0x1<<16) // Read from empty  GRC input buffer bits [63:32].
+  #define TCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1_SHIFT                                                      16
+  #define TCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2                                                             (0x1<<17) // Write to full GRC input buffer bits [95:64].
+  #define TCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2_SHIFT                                                       17
+  #define TCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2                                                            (0x1<<18) // Read from empty  GRC input buffer bits [95:64].
+  #define TCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2_SHIFT                                                      18
+  #define TCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3                                                             (0x1<<19) // Write to full GRC input buffer bits [127:96].
+  #define TCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3_SHIFT                                                       19
+  #define TCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3                                                            (0x1<<20) // Read from empty  GRC input buffer bits [127:96].
+  #define TCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3_SHIFT                                                      20
+  #define TCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL                                                             (0x1<<21) // In-process Table overflow.
+  #define TCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL_SHIFT                                                       21
+  #define TCM_REG_INT_STS_CLR_1_AGG_CON_DATA_BUF_OVFL                                                        (0x1<<22) // Message Processor Aggregation Connection Data buffer overflow.
+  #define TCM_REG_INT_STS_CLR_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                                  22
+  #define TCM_REG_INT_STS_CLR_1_AGG_CON_CMD_BUF_OVFL                                                         (0x1<<23) // Message Processor Aggregation Connection Command buffer overflow.
+  #define TCM_REG_INT_STS_CLR_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                                   23
+  #define TCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL                                                         (0x1<<24) // Message Processor Storm Connection Data buffer overflow.
+  #define TCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL_SHIFT                                                   24
+  #define TCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL                                                          (0x1<<25) // Message Processor Storm Connection Command buffer overflow.
+  #define TCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL_SHIFT                                                    25
+  #define TCM_REG_INT_STS_CLR_1_AGG_TASK_DATA_BUF_OVFL                                                       (0x1<<26) // Message Processor Aggregation Task Data buffer overflow.
+  #define TCM_REG_INT_STS_CLR_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                                 26
+  #define TCM_REG_INT_STS_CLR_1_AGG_TASK_CMD_BUF_OVFL                                                        (0x1<<27) // Message Processor Aggregation Task Command buffer overflow.
+  #define TCM_REG_INT_STS_CLR_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                                  27
+  #define TCM_REG_INT_STS_CLR_1_SM_TASK_DATA_BUF_OVFL                                                        (0x1<<28) // Message Processor Storm Task Data buffer overflow.
+  #define TCM_REG_INT_STS_CLR_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                                  28
+  #define TCM_REG_INT_STS_CLR_1_SM_TASK_CMD_BUF_OVFL                                                         (0x1<<29) // Message Processor Storm Task Command buffer overflow.
+  #define TCM_REG_INT_STS_CLR_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                                   29
+  #define TCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE                                                        (0x1<<30) // Input message first descriptor fields violation.
+  #define TCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE_SHIFT                                                  30
+  #define TCM_REG_INT_STS_CLR_1_SE_DESC_INPUT_VIOLATE                                                        (0x1<<31) // Input message second descriptor fields violation.
+  #define TCM_REG_INT_STS_CLR_1_SE_DESC_INPUT_VIOLATE_SHIFT                                                  31
+  #define TCM_REG_INT_STS_CLR_1_IS_PRS_OVFL_ERR_BB_K2                                                        (0x1<<5) // Write to full Pbf input buffer.
+  #define TCM_REG_INT_STS_CLR_1_IS_PRS_OVFL_ERR_BB_K2_SHIFT                                                  5
+  #define TCM_REG_INT_STS_CLR_1_IS_PRS_UNDER_ERR_BB_K2                                                       (0x1<<6) // Read from empty Pbf input buffer.
+  #define TCM_REG_INT_STS_CLR_1_IS_PRS_UNDER_ERR_BB_K2_SHIFT                                                 6
+#define TCM_REG_INT_STS_2                                                                                    0x11801a0UL //Access:R    DataWidth:0x1    // Multi Field Register.
+  #define TCM_REG_INT_STS_2_QMREG_MORE4                                                                      (0x1<<0) // More than 4 QM registrations.
+  #define TCM_REG_INT_STS_2_QMREG_MORE4_SHIFT                                                                0
+#define TCM_REG_INT_MASK_2                                                                                   0x11801a4UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define TCM_REG_INT_MASK_2_QMREG_MORE4                                                                     (0x1<<0) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_2.QMREG_MORE4 .
+  #define TCM_REG_INT_MASK_2_QMREG_MORE4_SHIFT                                                               0
+#define TCM_REG_INT_STS_WR_2                                                                                 0x11801a8UL //Access:WR   DataWidth:0x1    // Multi Field Register.
+  #define TCM_REG_INT_STS_WR_2_QMREG_MORE4                                                                   (0x1<<0) // More than 4 QM registrations.
+  #define TCM_REG_INT_STS_WR_2_QMREG_MORE4_SHIFT                                                             0
+#define TCM_REG_INT_STS_CLR_2                                                                                0x11801acUL //Access:RC   DataWidth:0x1    // Multi Field Register.
+  #define TCM_REG_INT_STS_CLR_2_QMREG_MORE4                                                                  (0x1<<0) // More than 4 QM registrations.
+  #define TCM_REG_INT_STS_CLR_2_QMREG_MORE4_SHIFT                                                            0
+#define TCM_REG_PRTY_MASK_H_0_BB_K2                                                                          0x1180204UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define TCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_K2                                                       (0x1<<0) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM026_I_ECC_RF_INT .
+  #define TCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_K2_SHIFT                                                 0
+  #define TCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT_BB_K2                                                  (0x1<<1) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM003_I_ECC_0_RF_INT .
+  #define TCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT_BB_K2_SHIFT                                            1
+  #define TCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT_BB_K2                                                  (0x1<<2) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM003_I_ECC_1_RF_INT .
+  #define TCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT_BB_K2_SHIFT                                            2
+  #define TCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_0_RF_INT_K2                                                     (0x1<<3) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM022_I_ECC_0_RF_INT .
+  #define TCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_0_RF_INT_K2_SHIFT                                               3
+  #define TCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_1_RF_INT_K2                                                     (0x1<<4) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM022_I_ECC_1_RF_INT .
+  #define TCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_1_RF_INT_K2_SHIFT                                               4
+  #define TCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_BB_K2                                                  (0x1<<5) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
+  #define TCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_BB_K2_SHIFT                                            5
+  #define TCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_K2                                                  (0x1<<6) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
+  #define TCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_K2_SHIFT                                            6
+  #define TCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_0_RF_INT_K2                                                     (0x1<<7) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM024_I_ECC_0_RF_INT .
+  #define TCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_0_RF_INT_K2_SHIFT                                               7
+  #define TCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_1_RF_INT_K2                                                     (0x1<<8) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM024_I_ECC_1_RF_INT .
+  #define TCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_1_RF_INT_K2_SHIFT                                               8
+  #define TCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_K2                                                      (0x1<<9) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_K2_SHIFT                                                9
+  #define TCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB                                                         (0x1<<14) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_SHIFT                                                   14
+  #define TCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2                                                         (0x1<<10) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_SHIFT                                                   10
+  #define TCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB                                                         (0x1<<10) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_SHIFT                                                   10
+  #define TCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2                                                         (0x1<<11) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2_SHIFT                                                   11
+  #define TCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB                                                         (0x1<<11) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_SHIFT                                                   11
+  #define TCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2                                                         (0x1<<12) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2_SHIFT                                                   12
+  #define TCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB                                                         (0x1<<12) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_SHIFT                                                   12
+  #define TCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2                                                         (0x1<<13) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_SHIFT                                                   13
+  #define TCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB                                                         (0x1<<13) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_SHIFT                                                   13
+  #define TCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2                                                         (0x1<<14) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2_SHIFT                                                   14
+  #define TCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB                                                         (0x1<<26) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_SHIFT                                                   26
+  #define TCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2                                                         (0x1<<15) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2_SHIFT                                                   15
+  #define TCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB                                                         (0x1<<15) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_SHIFT                                                   15
+  #define TCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2                                                         (0x1<<16) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2_SHIFT                                                   16
+  #define TCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB                                                         (0x1<<16) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_SHIFT                                                   16
+  #define TCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2                                                         (0x1<<17) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2_SHIFT                                                   17
+  #define TCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB                                                         (0x1<<17) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_SHIFT                                                   17
+  #define TCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2                                                         (0x1<<18) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2_SHIFT                                                   18
+  #define TCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB                                                         (0x1<<18) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_SHIFT                                                   18
+  #define TCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2                                                         (0x1<<19) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2_SHIFT                                                   19
+  #define TCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2                                                         (0x1<<20) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2_SHIFT                                                   20
+  #define TCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB                                                         (0x1<<19) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_SHIFT                                                   19
+  #define TCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2                                                         (0x1<<21) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2_SHIFT                                                   21
+  #define TCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB                                                         (0x1<<20) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_SHIFT                                                   20
+  #define TCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2                                                         (0x1<<22) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2_SHIFT                                                   22
+  #define TCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB                                                         (0x1<<22) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_SHIFT                                                   22
+  #define TCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2                                                         (0x1<<23) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_SHIFT                                                   23
+  #define TCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2                                                         (0x1<<24) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2_SHIFT                                                   24
+  #define TCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB                                                         (0x1<<24) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_SHIFT                                                   24
+  #define TCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2                                                         (0x1<<25) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_SHIFT                                                   25
+  #define TCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_K2                                                         (0x1<<26) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_K2_SHIFT                                                   26
+  #define TCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2                                                         (0x1<<27) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2_SHIFT                                                   27
+  #define TCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_BB                                                       (0x1<<27) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_0 .
+  #define TCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_BB_SHIFT                                                 27
+  #define TCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_K2                                                       (0x1<<28) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_0 .
+  #define TCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_K2_SHIFT                                                 28
+  #define TCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_BB                                                       (0x1<<28) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_1 .
+  #define TCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_BB_SHIFT                                                 28
+  #define TCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_K2                                                       (0x1<<29) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_1 .
+  #define TCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_K2_SHIFT                                                 29
+  #define TCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB                                                         (0x1<<29) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_SHIFT                                                   29
+  #define TCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2                                                         (0x1<<30) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_SHIFT                                                   30
+  #define TCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_RF_INT_BB                                                       (0x1<<0) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM025_I_ECC_RF_INT .
+  #define TCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_RF_INT_BB_SHIFT                                                 0
+  #define TCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_0_RF_INT_BB                                                     (0x1<<3) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM021_I_ECC_0_RF_INT .
+  #define TCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_0_RF_INT_BB_SHIFT                                               3
+  #define TCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_1_RF_INT_BB                                                     (0x1<<4) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM021_I_ECC_1_RF_INT .
+  #define TCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_1_RF_INT_BB_SHIFT                                               4
+  #define TCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_0_RF_INT_BB                                                     (0x1<<7) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM023_I_ECC_0_RF_INT .
+  #define TCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_0_RF_INT_BB_SHIFT                                               7
+  #define TCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_1_RF_INT_BB                                                     (0x1<<8) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM023_I_ECC_1_RF_INT .
+  #define TCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_1_RF_INT_BB_SHIFT                                               8
+  #define TCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB                                                         (0x1<<21) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_SHIFT                                                   21
+  #define TCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB                                                         (0x1<<23) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_SHIFT                                                   23
+  #define TCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB                                                         (0x1<<25) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB_SHIFT                                                   25
+  #define TCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB                                                         (0x1<<30) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_SHIFT                                                   30
+#define TCM_REG_PRTY_MASK_H_1_BB_K2                                                                          0x1180214UL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define TCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_K2                                                         (0x1<<0) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_K2_SHIFT                                                   0
+  #define TCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB                                                         (0x1<<0) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_SHIFT                                                   0
+  #define TCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2                                                         (0x1<<1) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2_SHIFT                                                   1
+  #define TCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB                                                         (0x1<<1) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_SHIFT                                                   1
+  #define TCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2                                                         (0x1<<2) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
+  #define TCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2_SHIFT                                                   2
+#define TCM_REG_MEM_ECC_ENABLE_0_BB_K2                                                                       0x1180220UL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_EN_K2                                                        (0x1<<0) // Enable ECC for memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_msg_ram
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_EN_K2_SHIFT                                                  0
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_0_EN_BB_K2                                                   (0x1<<1) // Enable ECC for memory ecc instance tcm.i_agg_con_ctx.i_ecc_0 in module tcm_mem_agg_con_ctx
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_0_EN_BB_K2_SHIFT                                             1
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_1_EN_BB_K2                                                   (0x1<<2) // Enable ECC for memory ecc instance tcm.i_agg_con_ctx.i_ecc_1 in module tcm_mem_agg_con_ctx
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_1_EN_BB_K2_SHIFT                                             2
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_0_EN_K2                                                      (0x1<<3) // Enable ECC for memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_con_ctx
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_0_EN_K2_SHIFT                                                3
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_1_EN_K2                                                      (0x1<<4) // Enable ECC for memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_con_ctx
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_1_EN_K2_SHIFT                                                4
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN_BB_K2                                                   (0x1<<5) // Enable ECC for memory ecc instance tcm.i_agg_task_ctx.i_ecc_0 in module tcm_mem_agg_task_ctx
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN_BB_K2_SHIFT                                             5
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_BB_K2                                                   (0x1<<6) // Enable ECC for memory ecc instance tcm.i_agg_task_ctx.i_ecc_1 in module tcm_mem_agg_task_ctx
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_BB_K2_SHIFT                                             6
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_0_EN_K2                                                      (0x1<<7) // Enable ECC for memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_task_ctx
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_0_EN_K2_SHIFT                                                7
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_1_EN_K2                                                      (0x1<<8) // Enable ECC for memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_task_ctx
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_1_EN_K2_SHIFT                                                8
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_EN_BB                                                        (0x1<<0) // Enable ECC for memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_msg_ram
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_EN_BB_SHIFT                                                  0
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_0_EN_BB                                                      (0x1<<3) // Enable ECC for memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_con_ctx
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_0_EN_BB_SHIFT                                                3
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_1_EN_BB                                                      (0x1<<4) // Enable ECC for memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_con_ctx
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_1_EN_BB_SHIFT                                                4
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_0_EN_BB                                                      (0x1<<7) // Enable ECC for memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_task_ctx
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_0_EN_BB_SHIFT                                                7
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_1_EN_BB                                                      (0x1<<8) // Enable ECC for memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_task_ctx
+  #define TCM_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_1_EN_BB_SHIFT                                                8
+#define TCM_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                  0x1180224UL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_PRTY_K2                                                 (0x1<<0) // Set parity only for memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_msg_ram
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_PRTY_K2_SHIFT                                           0
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_0_PRTY_BB_K2                                            (0x1<<1) // Set parity only for memory ecc instance tcm.i_agg_con_ctx.i_ecc_0 in module tcm_mem_agg_con_ctx
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_0_PRTY_BB_K2_SHIFT                                      1
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_1_PRTY_BB_K2                                            (0x1<<2) // Set parity only for memory ecc instance tcm.i_agg_con_ctx.i_ecc_1 in module tcm_mem_agg_con_ctx
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_1_PRTY_BB_K2_SHIFT                                      2
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_0_PRTY_K2                                               (0x1<<3) // Set parity only for memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_con_ctx
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_0_PRTY_K2_SHIFT                                         3
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_1_PRTY_K2                                               (0x1<<4) // Set parity only for memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_con_ctx
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_1_PRTY_K2_SHIFT                                         4
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY_BB_K2                                            (0x1<<5) // Set parity only for memory ecc instance tcm.i_agg_task_ctx.i_ecc_0 in module tcm_mem_agg_task_ctx
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY_BB_K2_SHIFT                                      5
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_BB_K2                                            (0x1<<6) // Set parity only for memory ecc instance tcm.i_agg_task_ctx.i_ecc_1 in module tcm_mem_agg_task_ctx
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_BB_K2_SHIFT                                      6
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_0_PRTY_K2                                               (0x1<<7) // Set parity only for memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_task_ctx
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_0_PRTY_K2_SHIFT                                         7
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_1_PRTY_K2                                               (0x1<<8) // Set parity only for memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_task_ctx
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_1_PRTY_K2_SHIFT                                         8
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_PRTY_BB                                                 (0x1<<0) // Set parity only for memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_msg_ram
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_PRTY_BB_SHIFT                                           0
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_0_PRTY_BB                                               (0x1<<3) // Set parity only for memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_con_ctx
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_0_PRTY_BB_SHIFT                                         3
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_1_PRTY_BB                                               (0x1<<4) // Set parity only for memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_con_ctx
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_1_PRTY_BB_SHIFT                                         4
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_0_PRTY_BB                                               (0x1<<7) // Set parity only for memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_task_ctx
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_0_PRTY_BB_SHIFT                                         7
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_1_PRTY_BB                                               (0x1<<8) // Set parity only for memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_task_ctx
+  #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_1_PRTY_BB_SHIFT                                         8
+#define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                              0x1180228UL //Access:RC   DataWidth:0x9    // Multi Field Register.
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM026_I_ECC_CORRECT_K2                                          (0x1<<0) // Record if a correctable error occurred on memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_msg_ram
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM026_I_ECC_CORRECT_K2_SHIFT                                    0
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_0_CORRECT_BB_K2                                     (0x1<<1) // Record if a correctable error occurred on memory ecc instance tcm.i_agg_con_ctx.i_ecc_0 in module tcm_mem_agg_con_ctx
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_0_CORRECT_BB_K2_SHIFT                               1
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_1_CORRECT_BB_K2                                     (0x1<<2) // Record if a correctable error occurred on memory ecc instance tcm.i_agg_con_ctx.i_ecc_1 in module tcm_mem_agg_con_ctx
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_1_CORRECT_BB_K2_SHIFT                               2
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_0_CORRECT_K2                                        (0x1<<3) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_con_ctx
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_0_CORRECT_K2_SHIFT                                  3
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_1_CORRECT_K2                                        (0x1<<4) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_con_ctx
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_1_CORRECT_K2_SHIFT                                  4
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT_BB_K2                                     (0x1<<5) // Record if a correctable error occurred on memory ecc instance tcm.i_agg_task_ctx.i_ecc_0 in module tcm_mem_agg_task_ctx
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT_BB_K2_SHIFT                               5
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_BB_K2                                     (0x1<<6) // Record if a correctable error occurred on memory ecc instance tcm.i_agg_task_ctx.i_ecc_1 in module tcm_mem_agg_task_ctx
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_BB_K2_SHIFT                               6
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_0_CORRECT_K2                                        (0x1<<7) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_task_ctx
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_0_CORRECT_K2_SHIFT                                  7
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_1_CORRECT_K2                                        (0x1<<8) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_task_ctx
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_1_CORRECT_K2_SHIFT                                  8
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_CORRECT_BB                                          (0x1<<0) // Record if a correctable error occurred on memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_msg_ram
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_CORRECT_BB_SHIFT                                    0
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_0_CORRECT_BB                                        (0x1<<3) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_con_ctx
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_0_CORRECT_BB_SHIFT                                  3
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_1_CORRECT_BB                                        (0x1<<4) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_con_ctx
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_1_CORRECT_BB_SHIFT                                  4
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_0_CORRECT_BB                                        (0x1<<7) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_task_ctx
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_0_CORRECT_BB_SHIFT                                  7
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_1_CORRECT_BB                                        (0x1<<8) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_task_ctx
+  #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_1_CORRECT_BB_SHIFT                                  8
+#define TCM_REG_MEM_ECC_EVENTS_BB_K2                                                                         0x118022cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define TCM_REG_IFEN                                                                                         0x1180400UL //Access:RW   DataWidth:0x1    // Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
+#define TCM_REG_QM_TASK_BASE_EVNT_ID_0                                                                       0x1180424UL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define TCM_REG_QM_TASK_BASE_EVNT_ID_1                                                                       0x1180428UL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define TCM_REG_QM_TASK_BASE_EVNT_ID_2                                                                       0x118042cUL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define TCM_REG_QM_TASK_BASE_EVNT_ID_3                                                                       0x1180430UL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define TCM_REG_QM_TASK_BASE_EVNT_ID_4                                                                       0x1180434UL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define TCM_REG_QM_TASK_BASE_EVNT_ID_5                                                                       0x1180438UL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define TCM_REG_QM_TASK_BASE_EVNT_ID_6                                                                       0x118043cUL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define TCM_REG_QM_TASK_BASE_EVNT_ID_7                                                                       0x1180440UL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define TCM_REG_QM_AGG_TASK_CTX_PART_SIZE_0                                                                  0x1180484UL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define TCM_REG_QM_AGG_TASK_CTX_PART_SIZE_1                                                                  0x1180488UL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define TCM_REG_QM_AGG_TASK_CTX_PART_SIZE_2                                                                  0x118048cUL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define TCM_REG_QM_AGG_TASK_CTX_PART_SIZE_3                                                                  0x1180490UL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define TCM_REG_QM_AGG_TASK_CTX_PART_SIZE_4                                                                  0x1180494UL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define TCM_REG_QM_AGG_TASK_CTX_PART_SIZE_5                                                                  0x1180498UL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define TCM_REG_QM_AGG_TASK_CTX_PART_SIZE_6                                                                  0x118049cUL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define TCM_REG_QM_AGG_TASK_CTX_PART_SIZE_7                                                                  0x11804a0UL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define TCM_REG_QM_SM_TASK_CTX_LDST_FLG_0                                                                    0x11804a4UL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define TCM_REG_QM_SM_TASK_CTX_LDST_FLG_1                                                                    0x11804a8UL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define TCM_REG_QM_SM_TASK_CTX_LDST_FLG_2                                                                    0x11804acUL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define TCM_REG_QM_SM_TASK_CTX_LDST_FLG_3                                                                    0x11804b0UL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define TCM_REG_QM_SM_TASK_CTX_LDST_FLG_4                                                                    0x11804b4UL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define TCM_REG_QM_SM_TASK_CTX_LDST_FLG_5                                                                    0x11804b8UL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define TCM_REG_QM_SM_TASK_CTX_LDST_FLG_6                                                                    0x11804bcUL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define TCM_REG_QM_SM_TASK_CTX_LDST_FLG_7                                                                    0x11804c0UL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define TCM_REG_QM_TASK_USE_ST_FLG_0                                                                         0x1180504UL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define TCM_REG_QM_TASK_USE_ST_FLG_1                                                                         0x1180508UL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define TCM_REG_QM_TASK_USE_ST_FLG_2                                                                         0x118050cUL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define TCM_REG_QM_TASK_USE_ST_FLG_3                                                                         0x1180510UL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define TCM_REG_QM_TASK_USE_ST_FLG_4                                                                         0x1180514UL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define TCM_REG_QM_TASK_USE_ST_FLG_5                                                                         0x1180518UL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define TCM_REG_QM_TASK_USE_ST_FLG_6                                                                         0x118051cUL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define TCM_REG_QM_TASK_USE_ST_FLG_7                                                                         0x1180520UL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM.
+#define TCM_REG_TM_TASK_EVNT_ID_0                                                                            0x1180544UL //Access:RW   DataWidth:0x8    // TM task Event ID per connection type.
+#define TCM_REG_TM_TASK_EVNT_ID_1                                                                            0x1180548UL //Access:RW   DataWidth:0x8    // TM task Event ID per connection type.
+#define TCM_REG_TM_TASK_EVNT_ID_2                                                                            0x118054cUL //Access:RW   DataWidth:0x8    // TM task Event ID per connection type.
+#define TCM_REG_TM_TASK_EVNT_ID_3                                                                            0x1180550UL //Access:RW   DataWidth:0x8    // TM task Event ID per connection type.
+#define TCM_REG_TM_TASK_EVNT_ID_4                                                                            0x1180554UL //Access:RW   DataWidth:0x8    // TM task Event ID per connection type.
+#define TCM_REG_TM_TASK_EVNT_ID_5                                                                            0x1180558UL //Access:RW   DataWidth:0x8    // TM task Event ID per connection type.
+#define TCM_REG_TM_TASK_EVNT_ID_6                                                                            0x118055cUL //Access:RW   DataWidth:0x8    // TM task Event ID per connection type.
+#define TCM_REG_TM_TASK_EVNT_ID_7                                                                            0x1180560UL //Access:RW   DataWidth:0x8    // TM task Event ID per connection type.
+#define TCM_REG_ERR_EVNT_ID                                                                                  0x1180564UL //Access:RW   DataWidth:0x8    // The Event ID in case one of errors is set in QM input message.
+#define TCM_REG_AGG_CON_RULE0_Q_BB_K2                                                                        0x1180940UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_CON_RULE0_Q_E5                                                                           0x1180568UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define TCM_REG_AGG_CON_RULE1_Q_BB_K2                                                                        0x1180944UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_CON_RULE1_Q_E5                                                                           0x118056cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define TCM_REG_AGG_CON_RULE2_Q_BB_K2                                                                        0x1180948UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_CON_RULE2_Q_E5                                                                           0x1180570UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define TCM_REG_AGG_CON_RULE3_Q_BB_K2                                                                        0x118094cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_CON_RULE3_Q_E5                                                                           0x1180574UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define TCM_REG_AGG_CON_RULE4_Q_BB_K2                                                                        0x1180950UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_CON_RULE4_Q_E5                                                                           0x1180578UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define TCM_REG_AGG_CON_RULE5_Q_BB_K2                                                                        0x1180954UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).:
+#define TCM_REG_AGG_CON_RULE5_Q_E5                                                                           0x118057cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define TCM_REG_AGG_CON_RULE6_Q_BB_K2                                                                        0x1180958UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_CON_RULE6_Q_E5                                                                           0x1180580UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define TCM_REG_AGG_CON_RULE7_Q_BB_K2                                                                        0x118095cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_CON_RULE7_Q_E5                                                                           0x1180584UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define TCM_REG_AGG_CON_RULE8_Q_BB_K2                                                                        0x1180960UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_CON_RULE8_Q_E5                                                                           0x1180588UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define TCM_REG_AGG_CON_RULE9_Q_E5                                                                           0x118058cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define TCM_REG_AGG_CON_RULE10_Q_E5                                                                          0x1180590UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define TCM_REG_STORM_WEIGHT                                                                                 0x1180604UL //Access:RW   DataWidth:0x3    // The weight of the local Storm input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define TCM_REG_MSEM_WEIGHT                                                                                  0x1180608UL //Access:RW   DataWidth:0x3    // The weight of the input Msem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define TCM_REG_DORQ_WEIGHT                                                                                  0x1180610UL //Access:RW   DataWidth:0x3    // The weight of the input Dorq in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define TCM_REG_PBF_WEIGHT                                                                                   0x1180614UL //Access:RW   DataWidth:0x3    // The weight of the input Pbf in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define TCM_REG_PRS_WEIGHT_BB_K2                                                                             0x1180618UL //Access:RW   DataWidth:0x3    // The weight of the input PRS in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define TCM_REG_GRC_WEIGHT                                                                                   0x118061cUL //Access:RW   DataWidth:0x3    // The weight of the GRC input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define TCM_REG_QM_P_WEIGHT                                                                                  0x1180624UL //Access:RW   DataWidth:0x3    // The weight of the QM (primary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define TCM_REG_QM_S_WEIGHT                                                                                  0x1180628UL //Access:RW   DataWidth:0x3    // The weight of the QM (secondary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define TCM_REG_TM_WEIGHT                                                                                    0x118062cUL //Access:RW   DataWidth:0x3    // The weight of the Timers input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define TCM_REG_IA_GROUP_PR0                                                                                 0x1180630UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: ia_group_pr0 is the highest priority; ia_group_pr5 is the lowest priority.
+#define TCM_REG_IA_GROUP_PR1                                                                                 0x1180634UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define TCM_REG_IA_GROUP_PR2                                                                                 0x1180638UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define TCM_REG_IA_GROUP_PR3                                                                                 0x118063cUL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define TCM_REG_IA_GROUP_PR4                                                                                 0x1180640UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define TCM_REG_IA_GROUP_PR5                                                                                 0x1180644UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define TCM_REG_IA_ARB_SP_TIMEOUT                                                                            0x1180648UL //Access:RW   DataWidth:0x8    // Input Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8'h0 - constant RR; 8'h80 - constant strict priority. In all other cases the following is true: Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance.
+#define TCM_REG_STORM_FRWRD_MODE                                                                             0x118064cUL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define TCM_REG_MSEM_FRWRD_MODE                                                                              0x1180654UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define TCM_REG_DORQ_FRWRD_MODE                                                                              0x118065cUL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define TCM_REG_PBF_FRWRD_MODE                                                                               0x1180660UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define TCM_REG_SDM_ERR_HANDLE_EN                                                                            0x1180664UL //Access:RW   DataWidth:0x1    // 0 - disable error handling in SDM message; 1 - enable error handling in SDM message.
+#define TCM_REG_DIR_BYP_EN                                                                                   0x1180668UL //Access:RW   DataWidth:0x1    // Direct bypass enable.
+#define TCM_REG_FI_DESC_INPUT_VIOLATE                                                                        0x118066cUL //Access:R    DataWidth:0xf    // Input message first descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0  then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL  then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation:  Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation:  TaskExist==0 -> XxLockCmd != XX_UNLOCK_CID_TID and XxLockCmd != XX_LOCK_CID_TID_BYPASS;  [12] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0;[13] - Violation: Agg message: Loader done with error then SmCtxLdStFlg==0; [14] - Violation: XxBypass message in PCM block;
+#define TCM_REG_SE_DESC_INPUT_VIOLATE                                                                        0x1180670UL //Access:R    DataWidth:0xc    // Input message second descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0  then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL  then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation:  Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0; Read only register.
+#define TCM_REG_IA_AGG_CON_PART_FILL_LVL                                                                     0x1180674UL //Access:R    DataWidth:0x3    // Input Arbiter Aggregation Connection part FIFO fill level (in messages).
+#define TCM_REG_IA_SM_CON_PART_FILL_LVL                                                                      0x1180678UL //Access:R    DataWidth:0x3    // Input Arbiter Storm Connection part FIFO fill level (in messages).
+#define TCM_REG_IA_AGG_TASK_PART_FILL_LVL                                                                    0x118067cUL //Access:R    DataWidth:0x3    // Input Arbiter Aggregation Task part FIFO fill level (in messages).
+#define TCM_REG_IA_SM_TASK_PART_FILL_LVL                                                                     0x1180680UL //Access:R    DataWidth:0x3    // Input Arbiter Storm Task part FIFO fill level (in messages).
+#define TCM_REG_IA_TRANS_PART_FILL_LVL                                                                       0x1180684UL //Access:R    DataWidth:0x3    // Input Arbiter Transparent part FIFO fill level (in messages).
+#define TCM_REG_EXT_RD_FILL_LVL_E5                                                                           0x1180688UL //Access:R    DataWidth:0x2    // External read buffer FIFO fill level (in FIFO entries).
+#define TCM_REG_XX_MSG_UP_BND                                                                                0x1180704UL //Access:RW   DataWidth:0x7    // The maximum number of Xx RAM messages; which may be stored in XX protection. Is restricted by Xx Messages RAM size and the size of Xx protected message CM_REGISTERS_XX_MSG_SIZE.XX_MSG_SIZE
+#define TCM_REG_XX_MSG_SIZE                                                                                  0x1180708UL //Access:RW   DataWidth:0x5    // The size of Xx protected message in Xx Messages RAM in QREGs. Upper rounded to 4 and multiplied by CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND should not exceed XxMessagesRam size which is: MCM: 0d1792 PCM: 0d176 TCM: 0d1536 UCM: 0d1792 XCM: 0d256 YCM: 0d1536
+#define TCM_REG_XX_LCID_CAM_UP_BND                                                                           0x118070cUL //Access:RW   DataWidth:0x7    // The maximum number of connections in the XX protection LCID CAM.
+#define TCM_REG_XX_FREE_CNT                                                                                  0x1180710UL //Access:R    DataWidth:0x7    // Used to read the XX protection Free counter. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND
+#define TCM_REG_XX_LCID_CAM_FILL_LVL                                                                         0x1180714UL //Access:R    DataWidth:0x7    // Used to read XX protection LCID CAM fill level. Fill level is calculated as the number of locked LCIDs, i.e. LCIDs that have at least one Xx locked message or LCIDs that have no Xx locked messages but haven't been unlocked yet from LCID CAM. Simple saying it calculates for number of valid entries in LCID CAM.
+#define TCM_REG_XX_LCID_CAM_ST_STAT                                                                          0x1180718UL //Access:RC   DataWidth:0x7    // CAM occupancy sticky status. The write to the register is performed by the XX internal circuitry.
+#define TCM_REG_XX_IA_GROUP_PR0                                                                              0x118071cUL //Access:RW   DataWidth:0x1    // Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
+#define TCM_REG_XX_IA_GROUP_PR1                                                                              0x1180720UL //Access:RW   DataWidth:0x1    // Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
+#define TCM_REG_XX_NON_LOCK_LCID_THR                                                                         0x1180724UL //Access:RW   DataWidth:0x7    // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decision of Xx Input Arbiter non-locked group.
+#define TCM_REG_XX_LOCK_LCID_THR                                                                             0x1180728UL //Access:RW   DataWidth:0x7    // Xx locked LCIDs threshold (maximum value). Participates in Xx Bypass global enable decision.
+#define TCM_REG_XX_IA_ARB_SP_TIMEOUT                                                                         0x118072cUL //Access:RW   DataWidth:0x8    // Xx Input Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. E.g. bits[6:0]=0; bit[7]=0 - always strict priority; bits[6:0]=1; bit[7]=0 - strict priority; then RR; bits[6:0]=3; bit[7]=0 - 3 times strict priority; then RR.
+#define TCM_REG_XX_FREE_HEAD_PTR                                                                             0x1180730UL //Access:R    DataWidth:0x6    // Xx Free Head Pointer.
+#define TCM_REG_XX_FREE_TAIL_PTR                                                                             0x1180734UL //Access:R    DataWidth:0x6    // Xx Free Tail Pointer. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND
+#define TCM_REG_XX_NON_LOCK_CNT                                                                              0x1180738UL //Access:R    DataWidth:0x7    // Xx NonLock Counter.
+#define TCM_REG_XX_LOCK_CNT                                                                                  0x118073cUL //Access:R    DataWidth:0x7    // Xx Lock Counter.
+#define TCM_REG_XX_LCID_ARB_GROUP_PR0                                                                        0x1180740UL //Access:RW   DataWidth:0x2    // Xx LCID Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.
+#define TCM_REG_XX_LCID_ARB_GROUP_PR1                                                                        0x1180744UL //Access:RW   DataWidth:0x2    // Xx LCID Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.
+#define TCM_REG_XX_LCID_ARB_GROUP_PR2                                                                        0x1180748UL //Access:RW   DataWidth:0x2    // Xx LCID Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.
+#define TCM_REG_XX_LCID_ARB_SP_TIMEOUT                                                                       0x118074cUL //Access:RW   DataWidth:0x8    // Xx LCID Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. E.g. bits[6:0]=0; bit[7]=0 - always strict priority; bits[6:0]=1; bit[7]=0 - strict priority; then RR; bits[6:0]=3; bit[7]=0 - 3 times strict priority; then RR.
+#define TCM_REG_XX_FREE_THR_HIGH                                                                             0x1180750UL //Access:RW   DataWidth:0x7    // Xx free messages threshold high. Used in Xx Bypass global enable condition.
+#define TCM_REG_XX_FREE_THR_LOW                                                                              0x1180754UL //Access:RW   DataWidth:0x7    // Xx free messages threshold low Used in Xx Bypass global enable condition.
+#define TCM_REG_XX_CBYP_TBL_FILL_LVL                                                                         0x1180758UL //Access:R    DataWidth:0x4    // Xx Connection Bypass Table fill level (in connections).
+#define TCM_REG_XX_CBYP_TBL_ST_STAT                                                                          0x118075cUL //Access:RC   DataWidth:0x4    // Xx Connection Bypass Table sticky status. Reset on read.
+#define TCM_REG_XX_CBYP_TBL_UP_BND                                                                           0x1180760UL //Access:RW   DataWidth:0x4    // Xx Bypass Table (Connection) maximum fill level.
+#define TCM_REG_XX_TBYP_TBL_FILL_LVL                                                                         0x1180764UL //Access:R    DataWidth:0x7    // Xx Task Bypass Table fill level (in tasks).
+#define TCM_REG_XX_TBYP_TBL_ST_STAT                                                                          0x1180768UL //Access:RC   DataWidth:0x7    // Xx Task Bypass Table sticky status. Reset on read.
+#define TCM_REG_XX_TBYP_TBL_UP_BND                                                                           0x118076cUL //Access:RW   DataWidth:0x7    // Xx Bypass Table (Task) maximum fill level.
+#define TCM_REG_XX_BYP_LOCK_MSG_THR                                                                          0x1180790UL //Access:RW   DataWidth:0x6    // Xx Bypass messages lock threshold. The number of locked messages per LCID is above this threshold is one of conditions to start XxBypass for this LCID.
+#define TCM_REG_XX_PREF_DIR_FILL_LVL                                                                         0x1180794UL //Access:R    DataWidth:0x5    // Xx LCID Arbiter direct prefetch FIFO fill level (in entries).
+#define TCM_REG_XX_PREF_AGGST_FILL_LVL                                                                       0x1180798UL //Access:R    DataWidth:0x5    // Xx LCID Arbiter aggregation store prefetch FIFO fill level (in entries).
+#define TCM_REG_XX_PREF_BYP_FILL_LVL                                                                         0x118079cUL //Access:R    DataWidth:0x5    // Xx LCID Arbiter bypass prefetch FIFO fill level (in entries).
+#define TCM_REG_UNLOCK_MISS                                                                                  0x11807a0UL //Access:RC   DataWidth:0x1    // Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM.
+#define TCM_REG_ERR_AFFINITY_TYPE_E5                                                                         0x11807a4UL //Access:RW   DataWidth:0x2    // Affinity type in case of input message error.
+#define TCM_REG_ERR_EXCLUSIVE_FLG_E5                                                                         0x11807a8UL //Access:RW   DataWidth:0x1    // Exclusive type in case of input message error.
+#define TCM_REG_ERR_SRC_AFFINITY_E5                                                                          0x11807acUL //Access:RW   DataWidth:0x3    // Source affinity in case of input message error.
+#define TCM_REG_XX_BYP_MSG_UP_BND_0_BB_K2                                                                    0x1180770UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define TCM_REG_XX_BYP_MSG_UP_BND_0_E5                                                                       0x11807b0UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define TCM_REG_XX_BYP_MSG_UP_BND_1_BB_K2                                                                    0x1180774UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define TCM_REG_XX_BYP_MSG_UP_BND_1_E5                                                                       0x11807b4UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define TCM_REG_XX_BYP_MSG_UP_BND_2_BB_K2                                                                    0x1180778UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define TCM_REG_XX_BYP_MSG_UP_BND_2_E5                                                                       0x11807b8UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define TCM_REG_XX_BYP_MSG_UP_BND_3_BB_K2                                                                    0x118077cUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define TCM_REG_XX_BYP_MSG_UP_BND_3_E5                                                                       0x11807bcUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define TCM_REG_XX_BYP_MSG_UP_BND_4_BB_K2                                                                    0x1180780UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define TCM_REG_XX_BYP_MSG_UP_BND_4_E5                                                                       0x11807c0UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define TCM_REG_XX_BYP_MSG_UP_BND_5_BB_K2                                                                    0x1180784UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define TCM_REG_XX_BYP_MSG_UP_BND_5_E5                                                                       0x11807c4UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define TCM_REG_XX_BYP_MSG_UP_BND_6_BB_K2                                                                    0x1180788UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define TCM_REG_XX_BYP_MSG_UP_BND_6_E5                                                                       0x11807c8UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define TCM_REG_XX_BYP_MSG_UP_BND_7_BB_K2                                                                    0x118078cUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define TCM_REG_XX_BYP_MSG_UP_BND_7_E5                                                                       0x11807ccUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define TCM_REG_XX_BYP_MSG_UP_BND_8_E5                                                                       0x11807d0UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define TCM_REG_XX_BYP_MSG_UP_BND_9_E5                                                                       0x11807d4UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define TCM_REG_XX_BYP_MSG_UP_BND_10_E5                                                                      0x11807d8UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define TCM_REG_XX_BYP_MSG_UP_BND_11_E5                                                                      0x11807dcUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define TCM_REG_XX_BYP_MSG_UP_BND_12_E5                                                                      0x11807e0UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define TCM_REG_XX_BYP_MSG_UP_BND_13_E5                                                                      0x11807e4UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define TCM_REG_XX_BYP_MSG_UP_BND_14_E5                                                                      0x11807e8UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define TCM_REG_XX_BYP_MSG_UP_BND_15_E5                                                                      0x11807ecUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define TCM_REG_PRCS_AGG_CON_CURR_ST                                                                         0x1180804UL //Access:R    DataWidth:0x4    // Aggregation Connection Processor FSM.
+#define TCM_REG_PRCS_SM_CON_CURR_ST                                                                          0x1180808UL //Access:R    DataWidth:0x2    // STORM Connection Processor FSM.
+#define TCM_REG_PRCS_AGG_TASK_CURR_ST                                                                        0x118080cUL //Access:R    DataWidth:0x4    // Aggregation Task Processor FSM.
+#define TCM_REG_PRCS_SM_TASK_CURR_ST                                                                         0x1180810UL //Access:R    DataWidth:0x2    // STORM Task Processor FSM.
+#define TCM_REG_N_SM_TASK_CTX_LD_0                                                                           0x1180834UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define TCM_REG_N_SM_TASK_CTX_LD_1                                                                           0x1180838UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define TCM_REG_N_SM_TASK_CTX_LD_2                                                                           0x118083cUL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define TCM_REG_N_SM_TASK_CTX_LD_3                                                                           0x1180840UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define TCM_REG_N_SM_TASK_CTX_LD_4                                                                           0x1180844UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define TCM_REG_N_SM_TASK_CTX_LD_5                                                                           0x1180848UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define TCM_REG_N_SM_TASK_CTX_LD_6                                                                           0x118084cUL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define TCM_REG_N_SM_TASK_CTX_LD_7                                                                           0x1180850UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define TCM_REG_AGG_CON_FIC_BUF_FILL_LVL                                                                     0x1180854UL //Access:R    DataWidth:0x3    // Aggregation Connection FIC buffer fill level (in messages).
+#define TCM_REG_SM_CON_FIC_BUF_FILL_LVL                                                                      0x1180858UL //Access:R    DataWidth:0x5    // Storm Connection FIC buffer fill level (in messages).
+#define TCM_REG_AGG_CON_FIC_BUF_CRD                                                                          0x118085cUL //Access:RW   DataWidth:0x2    // Aggregation Connection FIC buffer credit (in full message out parts).
+#define TCM_REG_SM_CON_FIC_BUF_CRD                                                                           0x1180860UL //Access:RW   DataWidth:0x2    // Storm Connection FIC buffer credit (in full message out parts).
+#define TCM_REG_AGG_CON_BUF_CRD_AGG                                                                          0x1180864UL //Access:RW   DataWidth:0x3    // Aggregation Connection buffer (data or command) credit (Aggregation group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than Agregation Connection data buffer size=4. In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST and CM_REGISTERS_AGG_CON_CMD_BUF_CRD_DIR.AGG_CON_CMD_BUF_CRD_DIR need be no more than Agregation Connection command buffer size=6.
+#define TCM_REG_AGG_CON_BUF_CRD_AGGST                                                                        0x1180868UL //Access:RW   DataWidth:0x3    // Aggregation Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG need be no more than Agregation Connection data buffer size=4. In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG and CM_REGISTERS_AGG_CON_CMD_BUF_CRD_DIR.AGG_CON_CMD_BUF_CRD_DIR need be no more than Agregation Connection command buffer size=6.
+#define TCM_REG_SM_CON_BUF_CRD_AGGST                                                                         0x118086cUL //Access:RW   DataWidth:0x1    // Storm Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_CON_CMD_BUF_CRD_DIR.SM_CON_CMD_BUF_CRD_DIR need be no more than Storm Connection command buffer size=3.
+#define TCM_REG_AGG_CON_CMD_BUF_CRD_DIR                                                                      0x1180870UL //Access:RW   DataWidth:0x2    // Aggregation Connection command buffer credit (Direct group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG and XCM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than Agregation Connection command buffer size=6.
+#define TCM_REG_SM_CON_CMD_BUF_CRD_DIR                                                                       0x1180874UL //Access:RW   DataWidth:0x2    // Storm Connection command buffer credit (Direct group). In sum with CM_REGISTERS_SM_CON_BUF_CRD_AGGST.SM_CON_BUF_CRD_AGGST need be no more than Storm Connection command buffer size=3.
+#define TCM_REG_AGG_TASK_FIC_BUF_FILL_LVL                                                                    0x1180878UL //Access:R    DataWidth:0x2    // Aggregation Task FIC buffer fill level (in messages).
+#define TCM_REG_SM_TASK_FIC_BUF_FILL_LVL                                                                     0x118087cUL //Access:R    DataWidth:0x4    // Storm Task FIC buffer fill level (in messages).
+#define TCM_REG_AGG_TASK_FIC_BUF_CRD                                                                         0x1180880UL //Access:RW   DataWidth:0x2    // Aggregation Task FIC buffer credit (in full message out parts).
+#define TCM_REG_SM_TASK_FIC_BUF_CRD                                                                          0x1180884UL //Access:RW   DataWidth:0x2    // Storm Task FIC buffer credit (in full message out parts).
+#define TCM_REG_AGG_TASK_BUF_CRD_AGG                                                                         0x1180888UL //Access:RW   DataWidth:0x3    // Aggregation Task buffer (data or command) credit (Aggregation group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST need be no more than Agregation Task data buffer size=4. In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST and CM_REGISTERS_AGG_TASK_CMD_BUF_CRD_DIR.AGG_TASK_CMD_BUF_CRD_DIR need be no more than Agregation Task command buffer size=6.
+#define TCM_REG_AGG_TASK_BUF_CRD_AGGST                                                                       0x118088cUL //Access:RW   DataWidth:0x3    // Aggregation Task buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG need be no more than Agregation Task data buffer size=4. In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG and CM_REGISTERS_AGG_TASK_CMD_BUF_CRD_DIR.AGG_TASK_CMD_BUF_CRD_DIR need be no more than Agregation Task command buffer size=6.
+#define TCM_REG_SM_TASK_BUF_CRD_AGGST                                                                        0x1180890UL //Access:RW   DataWidth:0x1    // Storm Task buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_TASK_CMD_BUF_CRD_DIR.SM_TASK_CMD_BUF_CRD_DIR need be no more than Storm Task command buffer size=3.
+#define TCM_REG_AGG_TASK_CMD_BUF_CRD_DIR                                                                     0x1180894UL //Access:RW   DataWidth:0x2    // Aggregation Task command buffer credit (Direct group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG and CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST need be no more than Agregation Task command buffer size=6.
+#define TCM_REG_SM_TASK_CMD_BUF_CRD_DIR                                                                      0x1180898UL //Access:RW   DataWidth:0x2    // Storm Task command buffer credit (Direct group). In sum with CM_REGISTERS_SM_TASK_BUF_CRD_AGGST.SM_TASK_BUF_CRD_AGGST need be no more than Storm Task command buffer size=3.
+#define TCM_REG_TRANS_DATA_BUF_CRD_DIR                                                                       0x118089cUL //Access:RW   DataWidth:0x2    // Transparent data buffer credit (Direct group).
+#define TCM_REG_AGG_TASK_CTX_SIZE_0                                                                          0x11808c0UL //Access:RW   DataWidth:0x2    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define TCM_REG_AGG_TASK_CTX_SIZE_1                                                                          0x11808c4UL //Access:RW   DataWidth:0x2    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define TCM_REG_AGG_TASK_CTX_SIZE_2                                                                          0x11808c8UL //Access:RW   DataWidth:0x2    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define TCM_REG_AGG_TASK_CTX_SIZE_3                                                                          0x11808ccUL //Access:RW   DataWidth:0x2    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define TCM_REG_AGG_TASK_CTX_SIZE_4                                                                          0x11808d0UL //Access:RW   DataWidth:0x2    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define TCM_REG_AGG_TASK_CTX_SIZE_5                                                                          0x11808d4UL //Access:RW   DataWidth:0x2    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define TCM_REG_AGG_TASK_CTX_SIZE_6                                                                          0x11808d8UL //Access:RW   DataWidth:0x2    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define TCM_REG_AGG_TASK_CTX_SIZE_7                                                                          0x11808dcUL //Access:RW   DataWidth:0x2    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define TCM_REG_SM_CON_CTX_SIZE                                                                              0x11808e0UL //Access:RW   DataWidth:0x5    // STORM Connnection context per LCID size (REGQ). Default context size of 16 (REGQ) complies to 320 LCIDs. Maximum context size per LCID is 26. Maximum number of LCIDs allowed at maximum context size per LCID is 196. If not at default value need to be 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER((320*INTEGER(16/2))/(26/2)).
+#define TCM_REG_SM_TASK_CTX_SIZE                                                                             0x11808e4UL //Access:RW   DataWidth:0x4    // STORM Task context per LTID size (REGQ). Default context size of 4 (REGQ) complies to 320 LTIDs. Maximum context size per LTID is 12. Maximum number of LTIDs allowed at maximum context size per LTID is 52. If not at default value need to be 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER((320*INTEGER(4/2))/(12/2)).
+#define TCM_REG_CON_PHY_Q0                                                                                   0x1180904UL //Access:RW   DataWidth:0x9    // Physical queue connection number (queue number 0).
+#define TCM_REG_CON_PHY_Q1                                                                                   0x1180908UL //Access:RW   DataWidth:0x9    // Physical queue connection number (queue number 1).
+#define TCM_REG_TASK_PHY_Q0                                                                                  0x118090cUL //Access:RW   DataWidth:0x7    // Physical queue task number (queue number 0).
+#define TCM_REG_TASK_PHY_Q1                                                                                  0x1180910UL //Access:RW   DataWidth:0x7    // Physical queue task number (queue number 1).
+#define TCM_REG_AGG_TASK_RULE0_Q                                                                             0x1180984UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_TASK_RULE1_Q                                                                             0x1180988UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_TASK_RULE2_Q                                                                             0x118098cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_TASK_RULE3_Q                                                                             0x1180990UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_TASK_RULE4_Q                                                                             0x1180994UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_TASK_RULE5_Q                                                                             0x1180998UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_CM_TASK_EVENT_ID_BWIDTH_0_E5                                                                 0x118099cUL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define TCM_REG_CM_TASK_EVENT_ID_BWIDTH_1_E5                                                                 0x11809a0UL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define TCM_REG_CM_TASK_EVENT_ID_BWIDTH_2_E5                                                                 0x11809a4UL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define TCM_REG_CM_TASK_EVENT_ID_BWIDTH_3_E5                                                                 0x11809a8UL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define TCM_REG_CM_TASK_EVENT_ID_BWIDTH_4_E5                                                                 0x11809acUL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define TCM_REG_CM_TASK_EVENT_ID_BWIDTH_5_E5                                                                 0x11809b0UL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define TCM_REG_CM_TASK_EVENT_ID_BWIDTH_6_E5                                                                 0x11809b4UL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define TCM_REG_CM_TASK_EVENT_ID_BWIDTH_7_E5                                                                 0x11809b8UL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define TCM_REG_IN_PRCS_TBL_CRD_AGG                                                                          0x1180a04UL //Access:RW   DataWidth:0x4    // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.IN_PRCS_TBL_CRD_AGGST need be no more than In-process table size=12.
+#define TCM_REG_IN_PRCS_TBL_CRD_AGGST                                                                        0x1180a08UL //Access:RW   DataWidth:0x4    // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGG.IN_PRCS_TBL_CRD_AGG need be no more than In-process table size=12.
+#define TCM_REG_IN_PRCS_TBL_FILL_LVL                                                                         0x1180a0cUL //Access:R    DataWidth:0x4    // In-process Table fill level  (in messages).
+#define TCM_REG_IN_PRCS_TBL_ALMOST_FULL                                                                      0x1180a10UL //Access:R    DataWidth:0x1    // In-process Table almost full.
+#define TCM_REG_QMCON_CURR_ST                                                                                0x1180a14UL //Access:R    DataWidth:0x3    // QM connection registration FSM current state.
+#define TCM_REG_QMTASK_CURR_ST                                                                               0x1180a18UL //Access:R    DataWidth:0x3    // QM task registration FSM current state.
+#define TCM_REG_TMCON_CURR_ST                                                                                0x1180a1cUL //Access:R    DataWidth:0x1    // TM connection output FSM current state.
+#define TCM_REG_TMTASK_CURR_ST                                                                               0x1180a20UL //Access:R    DataWidth:0x1    // TM task output FSM current state.
+#define TCM_REG_CCFC_CURR_ST                                                                                 0x1180a24UL //Access:R    DataWidth:0x1    // CFC connection output FSM current state.
+#define TCM_REG_TCFC_CURR_ST                                                                                 0x1180a28UL //Access:R    DataWidth:0x1    // CFC task output FSM current state.
+#define TCM_REG_CMPL_DIR_CURR_ST                                                                             0x1180a2cUL //Access:R    DataWidth:0x4    // Direct Completer FSM current state.
+#define TCM_REG_XX_BYP_CON_STATE_EVNT_ID_FLG                                                                 0x1180a30UL //Access:RW   DataWidth:0x1    // If set, Xx connection bypass state will be added in calculation of CM output Event ID.
+#define TCM_REG_XX_BYP_TASK_STATE_EVNT_ID_FLG                                                                0x1180a34UL //Access:RW   DataWidth:0x1    // If set, Xx task bypass state will be added in calculation of CM output Event ID.
+#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_0_E5                                                                  0x1180a38UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_1_E5                                                                  0x1180a3cUL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_2_E5                                                                  0x1180a40UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_3_E5                                                                  0x1180a44UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_4_E5                                                                  0x1180a48UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_5_E5                                                                  0x1180a4cUL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_6_E5                                                                  0x1180a50UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_7_E5                                                                  0x1180a54UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_8_E5                                                                  0x1180a58UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_9_E5                                                                  0x1180a5cUL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_10_E5                                                                 0x1180a60UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_11_E5                                                                 0x1180a64UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_12_E5                                                                 0x1180a68UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_13_E5                                                                 0x1180a6cUL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_14_E5                                                                 0x1180a70UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_15_E5                                                                 0x1180a74UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define TCM_REG_CCFC_INIT_CRD                                                                                0x1180a84UL //Access:RW   DataWidth:0x4    // CCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.
+#define TCM_REG_TCFC_INIT_CRD                                                                                0x1180a88UL //Access:RW   DataWidth:0x4    // TCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.
+#define TCM_REG_QM_INIT_CRD0                                                                                 0x1180a8cUL //Access:RW   DataWidth:0x5    // QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 16.Write writes the initial credit value; read returns the current value of the credit counter.
+#define TCM_REG_TM_INIT_CRD                                                                                  0x1180a90UL //Access:RW   DataWidth:0x4    // Timers output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.
+#define TCM_REG_FIC_INIT_CRD                                                                                 0x1180a94UL //Access:RW   DataWidth:0x6    // FIC output initial credit. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 44 at start-up.
+#define TCM_REG_DIR_BYP_MSG_CNT                                                                              0x1180aa4UL //Access:RC   DataWidth:0x20   // Counter of direct bypassed messages.
+#define TCM_REG_DORQ_LENGTH_MIS                                                                              0x1180aacUL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at the dorq interface.
+#define TCM_REG_PBF_LENGTH_MIS                                                                               0x1180ab0UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at PBF interface.
+#define TCM_REG_PRS_LENGTH_MIS_BB_K2                                                                         0x1180ab4UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at PRS interface.
+#define TCM_REG_GRC_BUF_EMPTY                                                                                0x1180ab8UL //Access:R    DataWidth:0x1    // Input Stage GRC buffer is empty.
+#define TCM_REG_GRC_BUF_STATUS                                                                               0x1180abcUL //Access:R    DataWidth:0x6    // Input Stage GRC buffer status.
+#define TCM_REG_STORM_MSG_CNTR                                                                               0x1180ac0UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the STORM input.
+#define TCM_REG_MSEM_MSG_CNTR                                                                                0x1180ac8UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input MSEM.
+#define TCM_REG_DORQ_MSG_CNTR                                                                                0x1180ad0UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at  input DORQ.
+#define TCM_REG_PBF_MSG_CNTR                                                                                 0x1180ad4UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at input PBF.
+#define TCM_REG_PRS_MSG_CNTR_BB_K2                                                                           0x1180ad8UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at input PRS.
+#define TCM_REG_QM_P_MSG_CNTR                                                                                0x1180adcUL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the QM input (primary).
+#define TCM_REG_QM_S_MSG_CNTR                                                                                0x1180ae0UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the QM input (secondary).
+#define TCM_REG_TM_MSG_CNTR                                                                                  0x1180ae4UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the Timers input.
+#define TCM_REG_IS_GRC                                                                                       0x1180ae8UL //Access:W    DataWidth:0x20   // Used to write the GRC message. Write only. To distinguish if the register can be accessed to write GRC message                           polling of CM_REGISTERS.GRC_BUF_EMPTY need to be done
+#define TCM_REG_IS_QM_P_FILL_LVL                                                                             0x1180aecUL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in QM Primary Input Stage (except of bypass).
+#define TCM_REG_IS_QM_S_FILL_LVL                                                                             0x1180af0UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in QM Secondary Input Stage (except of bypass).
+#define TCM_REG_IS_TM_FILL_LVL                                                                               0x1180af4UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in TM Input Stage.
+#define TCM_REG_IS_STORM_FILL_LVL                                                                            0x1180af8UL //Access:R    DataWidth:0x5    // Number of entries (2 QREGs each) of data in STORM Input Stage.
+#define TCM_REG_IS_MSEM_FILL_LVL                                                                             0x1180b00UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) in TCM, YCM or 2 QREGs (256b) in XCM of data in MSEM Input Stage.
+#define TCM_REG_IS_DORQ_FILL_LVL                                                                             0x1180b08UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in DORQ Input Stage.
+#define TCM_REG_IS_PBF_FILL_LVL                                                                              0x1180b0cUL //Access:R    DataWidth:0x4    // Number of QREGs (128b) of data in PBF Input Stage.
+#define TCM_REG_IS_PRS_FILL_LVL_BB_K2                                                                        0x1180b10UL //Access:R    DataWidth:0x4    // Number of QREGs (128b) of data in PRS Input Stage.
+#define TCM_REG_FIC_MSG_CNTR                                                                                 0x1180b44UL //Access:RC   DataWidth:0x1c   // Counter of the output messages at FIC interfaces.
+#define TCM_REG_QM_OUT_CNTR                                                                                  0x1180b48UL //Access:RC   DataWidth:0x1c   // Counter of the output QM commands.
+#define TCM_REG_TM_OUT_CNTR                                                                                  0x1180b4cUL //Access:RC   DataWidth:0x1c   // Counter of the output Timers commands.
+#define TCM_REG_DONE0_CNTR                                                                                   0x1180b50UL //Access:RC   DataWidth:0x1c   // Counter of the output Done0.
+#define TCM_REG_DONE2_CNTR                                                                                   0x1180b54UL //Access:RC   DataWidth:0x1c   // Counter of the output Done2.
+#define TCM_REG_CCFC_CNTR                                                                                    0x1180b58UL //Access:RC   DataWidth:0x1c   // Counter of the output CCFC.
+#define TCM_REG_TCFC_CNTR                                                                                    0x1180b5cUL //Access:RC   DataWidth:0x1c   // Counter of the output TCFC.
+#define TCM_REG_ECO_RESERVED                                                                                 0x1180b84UL //Access:RW   DataWidth:0x8    // Chicken bits.
+#define TCM_REG_IS_FOC_TSEM_NXT_INF_UNIT                                                                     0x1180b88UL //Access:R    DataWidth:0x5    // Debug read from TSEM Input stage buffer: number of reads to next information unit.
+#define TCM_REG_IS_FOC_MSEM_NXT_INF_UNIT                                                                     0x1180b8cUL //Access:R    DataWidth:0x6    // Debug read from MSEM Input stage buffer: number of reads to next information unit.
+#define TCM_REG_IS_FOC_PRS_NXT_INF_UNIT_BB_K2                                                                0x1180b94UL //Access:R    DataWidth:0x6    // Debug read from PRS Input stage buffer: number of reads to next information unit.
+#define TCM_REG_IS_FOC_PBF_NXT_INF_UNIT                                                                      0x1180b98UL //Access:R    DataWidth:0x6    // Debug read from PBF Input stage buffer: number of reads to next information unit.
+#define TCM_REG_IS_FOC_DORQ_NXT_INF_UNIT                                                                     0x1180b9cUL //Access:R    DataWidth:0x6    // Debug read from DORQ Input stage buffer: number of reads to next information unit.
+#define TCM_REG_IS_FOC_TSEM                                                                                  0x1180c00UL //Access:R    DataWidth:0x20   // Debug read from TSEM Input stage buffer with 32-bits granularity. Read only.
+#define TCM_REG_IS_FOC_TSEM_SIZE_BB_K2                                                                       180
+#define TCM_REG_IS_FOC_TSEM_SIZE_E5                                                                          184
+#define TCM_REG_IS_FOC_MSEM                                                                                  0x1181000UL //Access:R    DataWidth:0x20   // Debug read from MSEM Input stage buffer with 32-bits granularity. Read only.
+#define TCM_REG_IS_FOC_MSEM_SIZE                                                                             24
+#define TCM_REG_IS_FOC_PRS_BB_K2                                                                             0x1181200UL //Access:R    DataWidth:0x20   // Debug read from PRS Input stage buffer with 32-bits granularity. Read only.
+#define TCM_REG_IS_FOC_PRS_SIZE                                                                              44
+#define TCM_REG_IS_FOC_PBF                                                                                   0x1181300UL //Access:R    DataWidth:0x20   // Debug read from PBF Input stage buffer with 32-bits granularity. Read only.
+#define TCM_REG_IS_FOC_PBF_SIZE                                                                              44
+#define TCM_REG_IS_FOC_DORQ                                                                                  0x1181400UL //Access:R    DataWidth:0x20   // Debug read from DORQ Input stage buffer with 32-bits granularity. Read only.
+#define TCM_REG_IS_FOC_DORQ_SIZE                                                                             24
+#define TCM_REG_CTX_RBC_ACCS                                                                                 0x11814c0UL //Access:RW   DataWidth:0x10   // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - offset (in REGs (32b)) within LCID/LTID. The procedure to read context is: first define base address and offset; then read context with one of the following registers: CM_REGISTERS_AGG_CON_CTX.AGG_CON_CTX CM_REGISTERS_SM_CON_CTX.SM_CON_CTX CM_REGISTERS_AGG_TASK_CTX.AGG_TASK_CTX CM_REGISTERS_SM_TASK_CTX.SM_TASK_CTX
+#define TCM_REG_AGG_CON_CTX                                                                                  0x11814c4UL //Access:RW   DataWidth:0x20   // Access is allowed only on idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The address base (LCID) and offset within LCID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to Aggregation Connection context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.
+#define TCM_REG_AGG_TASK_CTX                                                                                 0x11814c8UL //Access:RW   DataWidth:0x20   // Access is allowed only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The address base (LTID) and offset within LTID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to Aggregation Task context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.
+#define TCM_REG_SM_CON_CTX                                                                                   0x11814ccUL //Access:RW   DataWidth:0x20   // Access is allowed only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The address base (LCID) and offset within LCID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to STORM Connection context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.
+#define TCM_REG_SM_TASK_CTX                                                                                  0x11814d0UL //Access:RW   DataWidth:0x20   // Access is allowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The address base (LTID) and offset within LTID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to STORM Task context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.
+#define TCM_REG_XX_CBYP_TBL                                                                                  0x11814e0UL //Access:R    DataWidth:0xf    // Xx Connection Bypass Table.
+#define TCM_REG_XX_CBYP_TBL_SIZE                                                                             8
+#define TCM_REG_XX_TBYP_TBL                                                                                  0x1181500UL //Access:R    DataWidth:0xf    // Xx Task Bypass Table.
+#define TCM_REG_XX_TBYP_TBL_SIZE_BB_K2                                                                       32
+#define TCM_REG_XX_TBYP_TBL_SIZE_E5                                                                          64
+#define TCM_REG_XX_LCID_CAM                                                                                  0x1181600UL //Access:R    DataWidth:0xa    // Debug only. Read only access to LCID CAM in XX protection mechanism.
+#define TCM_REG_XX_LCID_CAM_SIZE_BB_K2                                                                       32
+#define TCM_REG_XX_LCID_CAM_SIZE_E5                                                                          64
+#define TCM_REG_XX_TBL                                                                                       0x1181700UL //Access:R    DataWidth:0x18   // Indirect access to the XX table of the XX protection mechanism. The fields are: [0] - Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: PCM - [9:8]; M/T/U/X/YCM - [17:12]; Next pointer: PCM - [11:10]; M/T/U/X/YCM - [23:18];
+#define TCM_REG_XX_TBL_SIZE_BB_K2                                                                            32
+#define TCM_REG_XX_TBL_SIZE_E5                                                                               64
+#define TCM_REG_XX_DSCR_TBL                                                                                  0x1181800UL //Access:RW   DataWidth:0x1e   // Indirect access to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [13:9];PCM [14:9]; TCM [13:9]; UCM [13:9];XCM [10:9];YCM[13:9]); Next pointer (MCM [19:14]; PCM [16:15]; TCM[19:14]; UCM [19:14]; XCM [16:11]; YCM [19:14]); LTID (MCM [28:20]; PCM [25:17] - reserved; TCM[28:20]; UCM [28:20]; XCM [25:17] - reserved; YCM [28:20]). Task Domain Exist (MCM [29]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - reserved; YCM [29]). A free link list in the XX descriptor table should be build. This is done by writing the following values to all effective entries in the table:xx_descr_table[i].next_pointer = i+1 (i=0 - (xx_msg_up_bnd-2)); xx_descr_table[i].next_pointer= 0 (i=xx_msg_up_bnd-1). The value of i is between 0 to the configured (not default) value of (xx_msg_up_bnd-1). The not effective entries (those which succeed the last effective entry with index (xx_msg_up_bnd-1)) can be initialized to any value for initialization procedure simplicity seek.
+#define TCM_REG_XX_DSCR_TBL_SIZE                                                                             64
+#define TCM_REG_TM_CON_EVNT_ID_0_BB_K2                                                                       0x1180524UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define TCM_REG_TM_CON_EVNT_ID_0_E5                                                                          0x1181900UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define TCM_REG_TM_CON_EVNT_ID_1_BB_K2                                                                       0x1180528UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define TCM_REG_TM_CON_EVNT_ID_1_E5                                                                          0x1181904UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define TCM_REG_TM_CON_EVNT_ID_2_BB_K2                                                                       0x118052cUL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define TCM_REG_TM_CON_EVNT_ID_2_E5                                                                          0x1181908UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define TCM_REG_TM_CON_EVNT_ID_3_BB_K2                                                                       0x1180530UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define TCM_REG_TM_CON_EVNT_ID_3_E5                                                                          0x118190cUL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define TCM_REG_TM_CON_EVNT_ID_4_BB_K2                                                                       0x1180534UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define TCM_REG_TM_CON_EVNT_ID_4_E5                                                                          0x1181910UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define TCM_REG_TM_CON_EVNT_ID_5_BB_K2                                                                       0x1180538UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define TCM_REG_TM_CON_EVNT_ID_5_E5                                                                          0x1181914UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define TCM_REG_TM_CON_EVNT_ID_6_BB_K2                                                                       0x118053cUL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define TCM_REG_TM_CON_EVNT_ID_6_E5                                                                          0x1181918UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define TCM_REG_TM_CON_EVNT_ID_7_BB_K2                                                                       0x1180540UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.:
+#define TCM_REG_TM_CON_EVNT_ID_7_E5                                                                          0x118191cUL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.:
+#define TCM_REG_TM_CON_EVNT_ID_8_E5                                                                          0x1181920UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define TCM_REG_TM_CON_EVNT_ID_9_E5                                                                          0x1181924UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define TCM_REG_TM_CON_EVNT_ID_10_E5                                                                         0x1181928UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define TCM_REG_TM_CON_EVNT_ID_11_E5                                                                         0x118192cUL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define TCM_REG_TM_CON_EVNT_ID_12_E5                                                                         0x1181930UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define TCM_REG_TM_CON_EVNT_ID_13_E5                                                                         0x1181934UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define TCM_REG_TM_CON_EVNT_ID_14_E5                                                                         0x1181938UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define TCM_REG_TM_CON_EVNT_ID_15_E5                                                                         0x118193cUL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.:
+#define TCM_REG_N_SM_CON_CTX_LD_0_BB_K2                                                                      0x1180814UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define TCM_REG_N_SM_CON_CTX_LD_0_E5                                                                         0x1181940UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define TCM_REG_N_SM_CON_CTX_LD_1_BB_K2                                                                      0x1180818UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define TCM_REG_N_SM_CON_CTX_LD_1_E5                                                                         0x1181944UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define TCM_REG_N_SM_CON_CTX_LD_2_BB_K2                                                                      0x118081cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define TCM_REG_N_SM_CON_CTX_LD_2_E5                                                                         0x1181948UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define TCM_REG_N_SM_CON_CTX_LD_3_BB_K2                                                                      0x1180820UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define TCM_REG_N_SM_CON_CTX_LD_3_E5                                                                         0x118194cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define TCM_REG_N_SM_CON_CTX_LD_4_BB_K2                                                                      0x1180824UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define TCM_REG_N_SM_CON_CTX_LD_4_E5                                                                         0x1181950UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define TCM_REG_N_SM_CON_CTX_LD_5_BB_K2                                                                      0x1180828UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define TCM_REG_N_SM_CON_CTX_LD_5_E5                                                                         0x1181954UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define TCM_REG_N_SM_CON_CTX_LD_6_BB_K2                                                                      0x118082cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define TCM_REG_N_SM_CON_CTX_LD_6_E5                                                                         0x1181958UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define TCM_REG_N_SM_CON_CTX_LD_7_BB_K2                                                                      0x1180830UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define TCM_REG_N_SM_CON_CTX_LD_7_E5                                                                         0x118195cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define TCM_REG_N_SM_CON_CTX_LD_8_E5                                                                         0x1181960UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define TCM_REG_N_SM_CON_CTX_LD_9_E5                                                                         0x1181964UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define TCM_REG_N_SM_CON_CTX_LD_10_E5                                                                        0x1181968UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 10).
+#define TCM_REG_N_SM_CON_CTX_LD_11_E5                                                                        0x118196cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define TCM_REG_N_SM_CON_CTX_LD_12_E5                                                                        0x1181970UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define TCM_REG_N_SM_CON_CTX_LD_13_E5                                                                        0x1181974UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define TCM_REG_N_SM_CON_CTX_LD_14_E5                                                                        0x1181978UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define TCM_REG_N_SM_CON_CTX_LD_15_E5                                                                        0x118197cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define TCM_REG_AGG_CON_CTX_SIZE_0_BB_K2                                                                     0x11808a0UL //Access:RW   DataWidth:0x3    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less or 3.
+#define TCM_REG_AGG_CON_CTX_SIZE_0_E5                                                                        0x1181980UL //Access:RW   DataWidth:0x3    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define TCM_REG_AGG_CON_CTX_SIZE_1_BB_K2                                                                     0x11808a4UL //Access:RW   DataWidth:0x3    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define TCM_REG_AGG_CON_CTX_SIZE_1_E5                                                                        0x1181984UL //Access:RW   DataWidth:0x3    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define TCM_REG_AGG_CON_CTX_SIZE_2_BB_K2                                                                     0x11808a8UL //Access:RW   DataWidth:0x3    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define TCM_REG_AGG_CON_CTX_SIZE_2_E5                                                                        0x1181988UL //Access:RW   DataWidth:0x3    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define TCM_REG_AGG_CON_CTX_SIZE_3_BB_K2                                                                     0x11808acUL //Access:RW   DataWidth:0x3    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define TCM_REG_AGG_CON_CTX_SIZE_3_E5                                                                        0x118198cUL //Access:RW   DataWidth:0x3    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define TCM_REG_AGG_CON_CTX_SIZE_4_BB_K2                                                                     0x11808b0UL //Access:RW   DataWidth:0x3    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define TCM_REG_AGG_CON_CTX_SIZE_4_E5                                                                        0x1181990UL //Access:RW   DataWidth:0x3    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define TCM_REG_AGG_CON_CTX_SIZE_5_BB_K2                                                                     0x11808b4UL //Access:RW   DataWidth:0x3    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define TCM_REG_AGG_CON_CTX_SIZE_5_E5                                                                        0x1181994UL //Access:RW   DataWidth:0x3    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define TCM_REG_AGG_CON_CTX_SIZE_6_BB_K2                                                                     0x11808b8UL //Access:RW   DataWidth:0x3    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define TCM_REG_AGG_CON_CTX_SIZE_6_E5                                                                        0x1181998UL //Access:RW   DataWidth:0x3    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define TCM_REG_AGG_CON_CTX_SIZE_7_BB_K2                                                                     0x11808bcUL //Access:RW   DataWidth:0x3    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define TCM_REG_AGG_CON_CTX_SIZE_7_E5                                                                        0x118199cUL //Access:RW   DataWidth:0x3    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define TCM_REG_AGG_CON_CTX_SIZE_8_E5                                                                        0x11819a0UL //Access:RW   DataWidth:0x3    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less or 3.
+#define TCM_REG_AGG_CON_CTX_SIZE_9_E5                                                                        0x11819a4UL //Access:RW   DataWidth:0x3    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define TCM_REG_AGG_CON_CTX_SIZE_10_E5                                                                       0x11819a8UL //Access:RW   DataWidth:0x3    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define TCM_REG_AGG_CON_CTX_SIZE_11_E5                                                                       0x11819acUL //Access:RW   DataWidth:0x3    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define TCM_REG_AGG_CON_CTX_SIZE_12_E5                                                                       0x11819b0UL //Access:RW   DataWidth:0x3    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define TCM_REG_AGG_CON_CTX_SIZE_13_E5                                                                       0x11819b4UL //Access:RW   DataWidth:0x3    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define TCM_REG_AGG_CON_CTX_SIZE_14_E5                                                                       0x11819b8UL //Access:RW   DataWidth:0x3    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define TCM_REG_AGG_CON_CTX_SIZE_15_E5                                                                       0x11819bcUL //Access:RW   DataWidth:0x3    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define TCM_REG_QM_CON_BASE_EVNT_ID_0_BB_K2                                                                  0x1180404UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define TCM_REG_QM_CON_BASE_EVNT_ID_0_E5                                                                     0x11819c0UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define TCM_REG_QM_CON_BASE_EVNT_ID_1_BB_K2                                                                  0x1180408UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define TCM_REG_QM_CON_BASE_EVNT_ID_1_E5                                                                     0x11819c4UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define TCM_REG_QM_CON_BASE_EVNT_ID_2_BB_K2                                                                  0x118040cUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define TCM_REG_QM_CON_BASE_EVNT_ID_2_E5                                                                     0x11819c8UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define TCM_REG_QM_CON_BASE_EVNT_ID_3_BB_K2                                                                  0x1180410UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define TCM_REG_QM_CON_BASE_EVNT_ID_3_E5                                                                     0x11819ccUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define TCM_REG_QM_CON_BASE_EVNT_ID_4_BB_K2                                                                  0x1180414UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define TCM_REG_QM_CON_BASE_EVNT_ID_4_E5                                                                     0x11819d0UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define TCM_REG_QM_CON_BASE_EVNT_ID_5_BB_K2                                                                  0x1180418UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define TCM_REG_QM_CON_BASE_EVNT_ID_5_E5                                                                     0x11819d4UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define TCM_REG_QM_CON_BASE_EVNT_ID_6_BB_K2                                                                  0x118041cUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define TCM_REG_QM_CON_BASE_EVNT_ID_6_E5                                                                     0x11819d8UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define TCM_REG_QM_CON_BASE_EVNT_ID_7_BB_K2                                                                  0x1180420UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define TCM_REG_QM_CON_BASE_EVNT_ID_7_E5                                                                     0x11819dcUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define TCM_REG_QM_CON_BASE_EVNT_ID_8_E5                                                                     0x11819e0UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define TCM_REG_QM_CON_BASE_EVNT_ID_9_E5                                                                     0x11819e4UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define TCM_REG_QM_CON_BASE_EVNT_ID_10_E5                                                                    0x11819e8UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define TCM_REG_QM_CON_BASE_EVNT_ID_11_E5                                                                    0x11819ecUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define TCM_REG_QM_CON_BASE_EVNT_ID_12_E5                                                                    0x11819f0UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define TCM_REG_QM_CON_BASE_EVNT_ID_13_E5                                                                    0x11819f4UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define TCM_REG_QM_CON_BASE_EVNT_ID_14_E5                                                                    0x11819f8UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define TCM_REG_QM_CON_BASE_EVNT_ID_15_E5                                                                    0x11819fcUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_0_BB_K2                                                             0x1180444UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_0_E5                                                                0x1181a00UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_1_BB_K2                                                             0x1180448UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_1_E5                                                                0x1181a04UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_2_BB_K2                                                             0x118044cUL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_2_E5                                                                0x1181a08UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_3_BB_K2                                                             0x1180450UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_3_E5                                                                0x1181a0cUL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_4_BB_K2                                                             0x1180454UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_4_E5                                                                0x1181a10UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_5_BB_K2                                                             0x1180458UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_5_E5                                                                0x1181a14UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_6_BB_K2                                                             0x118045cUL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_6_E5                                                                0x1181a18UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_7_BB_K2                                                             0x1180460UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_7_E5                                                                0x1181a1cUL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_8_E5                                                                0x1181a20UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_9_E5                                                                0x1181a24UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_10_E5                                                               0x1181a28UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_11_E5                                                               0x1181a2cUL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_12_E5                                                               0x1181a30UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_13_E5                                                               0x1181a34UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_14_E5                                                               0x1181a38UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_15_E5                                                               0x1181a3cUL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define TCM_REG_QM_XXLOCK_CMD_0_BB_K2                                                                        0x11804c4UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define TCM_REG_QM_XXLOCK_CMD_0_E5                                                                           0x1181a40UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define TCM_REG_QM_XXLOCK_CMD_1_BB_K2                                                                        0x11804c8UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define TCM_REG_QM_XXLOCK_CMD_1_E5                                                                           0x1181a44UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define TCM_REG_QM_XXLOCK_CMD_2_BB_K2                                                                        0x11804ccUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define TCM_REG_QM_XXLOCK_CMD_2_E5                                                                           0x1181a48UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define TCM_REG_QM_XXLOCK_CMD_3_BB_K2                                                                        0x11804d0UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define TCM_REG_QM_XXLOCK_CMD_3_E5                                                                           0x1181a4cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define TCM_REG_QM_XXLOCK_CMD_4_BB_K2                                                                        0x11804d4UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define TCM_REG_QM_XXLOCK_CMD_4_E5                                                                           0x1181a50UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define TCM_REG_QM_XXLOCK_CMD_5_BB_K2                                                                        0x11804d8UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define TCM_REG_QM_XXLOCK_CMD_5_E5                                                                           0x1181a54UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define TCM_REG_QM_XXLOCK_CMD_6_BB_K2                                                                        0x11804dcUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define TCM_REG_QM_XXLOCK_CMD_6_E5                                                                           0x1181a58UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define TCM_REG_QM_XXLOCK_CMD_7_BB_K2                                                                        0x11804e0UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define TCM_REG_QM_XXLOCK_CMD_7_E5                                                                           0x1181a5cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define TCM_REG_QM_XXLOCK_CMD_8_E5                                                                           0x1181a60UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define TCM_REG_QM_XXLOCK_CMD_9_E5                                                                           0x1181a64UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define TCM_REG_QM_XXLOCK_CMD_10_E5                                                                          0x1181a68UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define TCM_REG_QM_XXLOCK_CMD_11_E5                                                                          0x1181a6cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define TCM_REG_QM_XXLOCK_CMD_12_E5                                                                          0x1181a70UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define TCM_REG_QM_XXLOCK_CMD_13_E5                                                                          0x1181a74UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define TCM_REG_QM_XXLOCK_CMD_14_E5                                                                          0x1181a78UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define TCM_REG_QM_XXLOCK_CMD_15_E5                                                                          0x1181a7cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define TCM_REG_QM_CON_USE_ST_FLG_0_BB_K2                                                                    0x11804e4UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define TCM_REG_QM_CON_USE_ST_FLG_0_E5                                                                       0x1181a80UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define TCM_REG_QM_CON_USE_ST_FLG_1_BB_K2                                                                    0x11804e8UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define TCM_REG_QM_CON_USE_ST_FLG_1_E5                                                                       0x1181a84UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define TCM_REG_QM_CON_USE_ST_FLG_2_BB_K2                                                                    0x11804ecUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define TCM_REG_QM_CON_USE_ST_FLG_2_E5                                                                       0x1181a88UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define TCM_REG_QM_CON_USE_ST_FLG_3_BB_K2                                                                    0x11804f0UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define TCM_REG_QM_CON_USE_ST_FLG_3_E5                                                                       0x1181a8cUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define TCM_REG_QM_CON_USE_ST_FLG_4_BB_K2                                                                    0x11804f4UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define TCM_REG_QM_CON_USE_ST_FLG_4_E5                                                                       0x1181a90UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define TCM_REG_QM_CON_USE_ST_FLG_5_BB_K2                                                                    0x11804f8UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define TCM_REG_QM_CON_USE_ST_FLG_5_E5                                                                       0x1181a94UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define TCM_REG_QM_CON_USE_ST_FLG_6_BB_K2                                                                    0x11804fcUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define TCM_REG_QM_CON_USE_ST_FLG_6_E5                                                                       0x1181a98UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define TCM_REG_QM_CON_USE_ST_FLG_7_BB_K2                                                                    0x1180500UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define TCM_REG_QM_CON_USE_ST_FLG_7_E5                                                                       0x1181a9cUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define TCM_REG_QM_CON_USE_ST_FLG_8_E5                                                                       0x1181aa0UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define TCM_REG_QM_CON_USE_ST_FLG_9_E5                                                                       0x1181aa4UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define TCM_REG_QM_CON_USE_ST_FLG_10_E5                                                                      0x1181aa8UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define TCM_REG_QM_CON_USE_ST_FLG_11_E5                                                                      0x1181aacUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define TCM_REG_QM_CON_USE_ST_FLG_12_E5                                                                      0x1181ab0UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define TCM_REG_QM_CON_USE_ST_FLG_13_E5                                                                      0x1181ab4UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define TCM_REG_QM_CON_USE_ST_FLG_14_E5                                                                      0x1181ab8UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define TCM_REG_QM_CON_USE_ST_FLG_15_E5                                                                      0x1181abcUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define TCM_REG_QM_SM_CON_CTX_LDST_FLG_0_BB_K2                                                               0x1180464UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define TCM_REG_QM_SM_CON_CTX_LDST_FLG_0_E5                                                                  0x1181ac0UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define TCM_REG_QM_SM_CON_CTX_LDST_FLG_1_BB_K2                                                               0x1180468UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define TCM_REG_QM_SM_CON_CTX_LDST_FLG_1_E5                                                                  0x1181ac4UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define TCM_REG_QM_SM_CON_CTX_LDST_FLG_2_BB_K2                                                               0x118046cUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define TCM_REG_QM_SM_CON_CTX_LDST_FLG_2_E5                                                                  0x1181ac8UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define TCM_REG_QM_SM_CON_CTX_LDST_FLG_3_BB_K2                                                               0x1180470UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define TCM_REG_QM_SM_CON_CTX_LDST_FLG_3_E5                                                                  0x1181accUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define TCM_REG_QM_SM_CON_CTX_LDST_FLG_4_BB_K2                                                               0x1180474UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define TCM_REG_QM_SM_CON_CTX_LDST_FLG_4_E5                                                                  0x1181ad0UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define TCM_REG_QM_SM_CON_CTX_LDST_FLG_5_BB_K2                                                               0x1180478UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define TCM_REG_QM_SM_CON_CTX_LDST_FLG_5_E5                                                                  0x1181ad4UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define TCM_REG_QM_SM_CON_CTX_LDST_FLG_6_BB_K2                                                               0x118047cUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define TCM_REG_QM_SM_CON_CTX_LDST_FLG_6_E5                                                                  0x1181ad8UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define TCM_REG_QM_SM_CON_CTX_LDST_FLG_7_BB_K2                                                               0x1180480UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define TCM_REG_QM_SM_CON_CTX_LDST_FLG_7_E5                                                                  0x1181adcUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define TCM_REG_QM_SM_CON_CTX_LDST_FLG_8_E5                                                                  0x1181ae0UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define TCM_REG_QM_SM_CON_CTX_LDST_FLG_9_E5                                                                  0x1181ae4UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define TCM_REG_QM_SM_CON_CTX_LDST_FLG_10_E5                                                                 0x1181ae8UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define TCM_REG_QM_SM_CON_CTX_LDST_FLG_11_E5                                                                 0x1181aecUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define TCM_REG_QM_SM_CON_CTX_LDST_FLG_12_E5                                                                 0x1181af0UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define TCM_REG_QM_SM_CON_CTX_LDST_FLG_13_E5                                                                 0x1181af4UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define TCM_REG_QM_SM_CON_CTX_LDST_FLG_14_E5                                                                 0x1181af8UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define TCM_REG_QM_SM_CON_CTX_LDST_FLG_15_E5                                                                 0x1181afcUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define TCM_REG_TSDM_WEIGHT_BB_K2                                                                            0x1180620UL //Access:RW   DataWidth:0x3    // The weight of the input TSDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define TCM_REG_TSDM_WEIGHT_E5                                                                               0x1181b00UL //Access:RW   DataWidth:0x3    // The weight of the input TSDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define TCM_REG_TSDM_FRWRD_MODE_BB_K2                                                                        0x1180650UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define TCM_REG_TSDM_FRWRD_MODE_E5                                                                           0x1181b04UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define TCM_REG_TSDM_LENGTH_MIS_BB_K2                                                                        0x1180aa8UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at TSDM interface.
+#define TCM_REG_TSDM_LENGTH_MIS_E5                                                                           0x1181b08UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at TSDM interface.
+#define TCM_REG_TSDM_MSG_CNTR_BB_K2                                                                          0x1180ac4UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input TSDM.
+#define TCM_REG_TSDM_MSG_CNTR_E5                                                                             0x1181b0cUL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input TSDM.
+#define TCM_REG_IS_TSDM_FILL_LVL_BB_K2                                                                       0x1180afcUL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in TSDM Input Stage.
+#define TCM_REG_IS_TSDM_FILL_LVL_E5                                                                          0x1181b10UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in TSDM Input Stage.
+#define TCM_REG_IS_FOC_TSDM_NXT_INF_UNIT_BB_K2                                                               0x1180ba0UL //Access:R    DataWidth:0x6    // Debug read from TSDM Input stage buffer: number of reads to next information unit.
+#define TCM_REG_IS_FOC_TSDM_NXT_INF_UNIT_E5                                                                  0x1181b14UL //Access:R    DataWidth:0x6    // Debug read from TSDM Input stage buffer: number of reads to next information unit.
+#define TCM_REG_IS_FOC_TSDM_BB_K2                                                                            0x1181480UL //Access:R    DataWidth:0x20   // Debug read from TSDM Input stage buffer with 32-bits granularity. Read only.
+#define TCM_REG_IS_FOC_TSDM_E5                                                                               0x1181b40UL //Access:R    DataWidth:0x20   // Debug read from TSDM Input stage buffer with 32-bits granularity. Read only.
+#define TCM_REG_IS_FOC_TSDM_SIZE                                                                             16
+#define TCM_REG_PSDM_WEIGHT_E5                                                                               0x1181b80UL //Access:RW   DataWidth:0x3    // The weight of the input PSDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define TCM_REG_PSDM_FRWRD_MODE_E5                                                                           0x1181b84UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define TCM_REG_PSDM_LENGTH_MIS_E5                                                                           0x1181b88UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at PSDM interface.
+#define TCM_REG_PSDM_MSG_CNTR_E5                                                                             0x1181b8cUL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input PSDM.
+#define TCM_REG_IS_PSDM_FILL_LVL_E5                                                                          0x1181b90UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in PSDM Input Stage.
+#define TCM_REG_IS_FOC_PSDM_NXT_INF_UNIT_E5                                                                  0x1181b94UL //Access:R    DataWidth:0x6    // Debug read from PSDM Input stage buffer: number of reads to next information unit.
+#define TCM_REG_IS_FOC_PSDM_E5                                                                               0x1181bc0UL //Access:R    DataWidth:0x20   // Debug read from PSDM Input stage buffer with 32-bits granularity. Read only.
+#define TCM_REG_IS_FOC_PSDM_SIZE                                                                             16
+#define TCM_REG_MSDM_WEIGHT_E5                                                                               0x1181c00UL //Access:RW   DataWidth:0x3    // The weight of the input MSDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define TCM_REG_MSDM_FRWRD_MODE_E5                                                                           0x1181c04UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define TCM_REG_MSDM_LENGTH_MIS_E5                                                                           0x1181c08UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at MSDM interface.
+#define TCM_REG_MSDM_MSG_CNTR_E5                                                                             0x1181c0cUL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input MSDM.
+#define TCM_REG_IS_MSDM_FILL_LVL_E5                                                                          0x1181c10UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in MSDM Input Stage.
+#define TCM_REG_IS_FOC_MSDM_NXT_INF_UNIT_E5                                                                  0x1181c14UL //Access:R    DataWidth:0x6    // Debug read from MSDM Input stage buffer: number of reads to next information unit.
+#define TCM_REG_IS_FOC_MSDM_E5                                                                               0x1181c40UL //Access:R    DataWidth:0x20   // Debug read from MSDM Input stage buffer with 32-bits granularity. Read only.
+#define TCM_REG_IS_FOC_MSDM_SIZE                                                                             16
+#define TCM_REG_YSEM_WEIGHT_BB_K2                                                                            0x118060cUL //Access:RW   DataWidth:0x3    // The weight of the input Ysem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define TCM_REG_YSEM_WEIGHT_E5                                                                               0x1181c80UL //Access:RW   DataWidth:0x3    // The weight of the input Ysem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define TCM_REG_YSEM_FRWRD_MODE_BB_K2                                                                        0x1180658UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define TCM_REG_YSEM_FRWRD_MODE_E5                                                                           0x1181c84UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define TCM_REG_YSEM_MSG_CNTR_BB_K2                                                                          0x1180accUL //Access:RC   DataWidth:0x1c   // Counter of the input messages at input Ysem.
+#define TCM_REG_YSEM_MSG_CNTR_E5                                                                             0x1181c88UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at input Ysem.
+#define TCM_REG_IS_YSEM_FILL_LVL_BB_K2                                                                       0x1180b04UL //Access:R    DataWidth:0x4    // Number of QREGs (128b) of data in YSEM Input Stage.
+#define TCM_REG_IS_YSEM_FILL_LVL_E5                                                                          0x1181c8cUL //Access:R    DataWidth:0x4    // Number of QREGs (128b) for TCM, XCM or 2 QREGs (256b) for MCM of data in YSEM Input Stage.
+#define TCM_REG_IS_FOC_YSEM_NXT_INF_UNIT_BB_K2                                                               0x1180b90UL //Access:R    DataWidth:0x6    // Debug read from YSEM Input stage buffer: number of reads to next information unit.
+#define TCM_REG_IS_FOC_YSEM_NXT_INF_UNIT_E5                                                                  0x1181c90UL //Access:R    DataWidth:0x6    // Debug read from YSEM Input stage buffer: number of reads to next information unit.
+#define TCM_REG_IS_FOC_YSEM_BB_K2                                                                            0x1181100UL //Access:R    DataWidth:0x20   // Debug read from YSEM Input stage buffer with 32-bits granularity. Read only.
+#define TCM_REG_IS_FOC_YSEM_E5                                                                               0x1181d00UL //Access:R    DataWidth:0x20   // Debug read from YSEM Input stage buffer with 32-bits granularity. Read only.
+#define TCM_REG_IS_FOC_YSEM_SIZE                                                                             60
+#define TCM_REG_PTLD_WEIGHT_E5                                                                               0x1181e00UL //Access:RW   DataWidth:0x3    // The weight of the input PTLD in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define TCM_REG_PTLD_LENGTH_MIS_E5                                                                           0x1181e04UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at PTLD interface.
+#define TCM_REG_PTLD_MSG_CNTR_E5                                                                             0x1181e08UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at input PTLD.
+#define TCM_REG_IS_PTLD_FILL_LVL_E5                                                                          0x1181e0cUL //Access:R    DataWidth:0x6    // Number of QREGs (128b) of data in PTLD Input Stage.
+#define TCM_REG_IS_FOC_PTLD_NXT_INF_UNIT_E5                                                                  0x1181e10UL //Access:R    DataWidth:0x5    // Debug read from PTLD Input stage buffer: number of reads to next information unit.
+#define TCM_REG_IS_FOC_PTLD_E5                                                                               0x1182000UL //Access:R    DataWidth:0x20   // Debug read from PTLD Input stage buffer with 32-bits granularity. Read only.
+#define TCM_REG_IS_FOC_PTLD_SIZE                                                                             280
+#define TCM_REG_AGG_TASK_CF0_Q_BB_K2                                                                         0x1180964UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_TASK_CF0_Q_E5                                                                            0x1182800UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_TASK_CF1_Q_BB_K2                                                                         0x1180968UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_TASK_CF1_Q_E5                                                                            0x1182804UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_TASK_CF2_Q_BB_K2                                                                         0x118096cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_TASK_CF2_Q_E5                                                                            0x1182808UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_TASK_CF3_Q_BB_K2                                                                         0x1180970UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_TASK_CF3_Q_E5                                                                            0x118280cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_TASK_CF4_Q_BB_K2                                                                         0x1180974UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_TASK_CF4_Q_E5                                                                            0x1182810UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_TASK_CF5_Q_BB_K2                                                                         0x1180978UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_TASK_CF5_Q_E5                                                                            0x1182814UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_TASK_CF6_Q_BB_K2                                                                         0x118097cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_TASK_CF6_Q_E5                                                                            0x1182818UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_TASK_CF7_Q_BB_K2                                                                         0x1180980UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_AGG_TASK_CF7_Q_E5                                                                            0x118281cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define TCM_REG_XX_MSG_RAM                                                                                   0x1188000UL //Access:R    DataWidth:0x20   // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
+#define TCM_REG_XX_MSG_RAM_SIZE_BB_K2                                                                        5632
+#define TCM_REG_XX_MSG_RAM_SIZE_E5                                                                           6144
+#define MCM_REG_INIT                                                                                         0x1200000UL //Access:RW   DataWidth:0x1    // Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
+#define MCM_REG_DBG_SELECT                                                                                   0x1200040UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define MCM_REG_DBG_DWORD_ENABLE                                                                             0x1200044UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define MCM_REG_DBG_SHIFT                                                                                    0x1200048UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define MCM_REG_DBG_FORCE_VALID                                                                              0x120004cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define MCM_REG_DBG_FORCE_FRAME                                                                              0x1200050UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define MCM_REG_DBG_OUT_DATA                                                                                 0x1200060UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define MCM_REG_DBG_OUT_DATA_SIZE                                                                            8
+#define MCM_REG_DBG_OUT_VALID                                                                                0x1200080UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define MCM_REG_DBG_OUT_FRAME                                                                                0x1200084UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define MCM_REG_AFFINITY_TYPE_0_E5                                                                           0x1200088UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define MCM_REG_AFFINITY_TYPE_1_E5                                                                           0x120008cUL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define MCM_REG_AFFINITY_TYPE_2_E5                                                                           0x1200090UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define MCM_REG_AFFINITY_TYPE_3_E5                                                                           0x1200094UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define MCM_REG_AFFINITY_TYPE_4_E5                                                                           0x1200098UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define MCM_REG_AFFINITY_TYPE_5_E5                                                                           0x120009cUL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define MCM_REG_AFFINITY_TYPE_6_E5                                                                           0x12000a0UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define MCM_REG_AFFINITY_TYPE_7_E5                                                                           0x12000a4UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define MCM_REG_AFFINITY_TYPE_8_E5                                                                           0x12000a8UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define MCM_REG_AFFINITY_TYPE_9_E5                                                                           0x12000acUL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define MCM_REG_AFFINITY_TYPE_10_E5                                                                          0x12000b0UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define MCM_REG_AFFINITY_TYPE_11_E5                                                                          0x12000b4UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define MCM_REG_AFFINITY_TYPE_12_E5                                                                          0x12000b8UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define MCM_REG_AFFINITY_TYPE_13_E5                                                                          0x12000bcUL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define MCM_REG_AFFINITY_TYPE_14_E5                                                                          0x12000c0UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define MCM_REG_AFFINITY_TYPE_15_E5                                                                          0x12000c4UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define MCM_REG_EXCLUSIVE_FLG_0_E5                                                                           0x12000c8UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define MCM_REG_EXCLUSIVE_FLG_1_E5                                                                           0x12000ccUL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define MCM_REG_EXCLUSIVE_FLG_2_E5                                                                           0x12000d0UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define MCM_REG_EXCLUSIVE_FLG_3_E5                                                                           0x12000d4UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define MCM_REG_EXCLUSIVE_FLG_4_E5                                                                           0x12000d8UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define MCM_REG_EXCLUSIVE_FLG_5_E5                                                                           0x12000dcUL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define MCM_REG_EXCLUSIVE_FLG_6_E5                                                                           0x12000e0UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define MCM_REG_EXCLUSIVE_FLG_7_E5                                                                           0x12000e4UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define MCM_REG_EXCLUSIVE_FLG_8_E5                                                                           0x12000e8UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define MCM_REG_EXCLUSIVE_FLG_9_E5                                                                           0x12000ecUL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define MCM_REG_EXCLUSIVE_FLG_10_E5                                                                          0x12000f0UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define MCM_REG_EXCLUSIVE_FLG_11_E5                                                                          0x12000f4UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define MCM_REG_EXCLUSIVE_FLG_12_E5                                                                          0x12000f8UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define MCM_REG_EXCLUSIVE_FLG_13_E5                                                                          0x12000fcUL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define MCM_REG_EXCLUSIVE_FLG_14_E5                                                                          0x1200100UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define MCM_REG_EXCLUSIVE_FLG_15_E5                                                                          0x1200104UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define MCM_REG_AGG_CON_CF0_Q_BB_K2                                                                          0x1200914UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define MCM_REG_AGG_CON_CF0_Q_E5                                                                             0x1200108UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define MCM_REG_AGG_CON_CF1_Q_BB_K2                                                                          0x1200918UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define MCM_REG_AGG_CON_CF1_Q_E5                                                                             0x120010cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define MCM_REG_AGG_CON_CF2_Q_BB_K2                                                                          0x120091cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define MCM_REG_AGG_CON_CF2_Q_E5                                                                             0x1200110UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define MCM_REG_INT_STS_0                                                                                    0x1200180UL //Access:R    DataWidth:0x16   // Multi Field Register.
+  #define MCM_REG_INT_STS_0_ADDRESS_ERROR                                                                    (0x1<<0) // Signals an unknown address to the rf module.
+  #define MCM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                              0
+  #define MCM_REG_INT_STS_0_IS_STORM_OVFL_ERR                                                                (0x1<<1) // Write to full STORM input buffer.
+  #define MCM_REG_INT_STS_0_IS_STORM_OVFL_ERR_SHIFT                                                          1
+  #define MCM_REG_INT_STS_0_IS_STORM_UNDER_ERR                                                               (0x1<<2) // Read from empty  STORM input buffer.
+  #define MCM_REG_INT_STS_0_IS_STORM_UNDER_ERR_SHIFT                                                         2
+  #define MCM_REG_INT_STS_0_IS_MSDM_OVFL_ERR                                                                 (0x1<<3) // Write to full MSDM input buffer.
+  #define MCM_REG_INT_STS_0_IS_MSDM_OVFL_ERR_SHIFT                                                           3
+  #define MCM_REG_INT_STS_0_IS_MSDM_UNDER_ERR                                                                (0x1<<4) // Read from empty MSDM input buffer.
+  #define MCM_REG_INT_STS_0_IS_MSDM_UNDER_ERR_SHIFT                                                          4
+  #define MCM_REG_INT_STS_0_IS_YSDM_OVFL_ERR                                                                 (0x1<<5) // Write to full YSDM input buffer.
+  #define MCM_REG_INT_STS_0_IS_YSDM_OVFL_ERR_SHIFT                                                           5
+  #define MCM_REG_INT_STS_0_IS_YSDM_UNDER_ERR                                                                (0x1<<6) // Read from empty  YSDM input buffer.
+  #define MCM_REG_INT_STS_0_IS_YSDM_UNDER_ERR_SHIFT                                                          6
+  #define MCM_REG_INT_STS_0_IS_TSDM_OVFL_ERR_E5                                                              (0x1<<7) // Write to full TSDM input buffer.
+  #define MCM_REG_INT_STS_0_IS_TSDM_OVFL_ERR_E5_SHIFT                                                        7
+  #define MCM_REG_INT_STS_0_IS_TSDM_UNDER_ERR_E5                                                             (0x1<<8) // Read from empty TSDM input buffer.
+  #define MCM_REG_INT_STS_0_IS_TSDM_UNDER_ERR_E5_SHIFT                                                       8
+  #define MCM_REG_INT_STS_0_IS_PSDM_OVFL_ERR_E5                                                              (0x1<<9) // Write to full PSDM input buffer.
+  #define MCM_REG_INT_STS_0_IS_PSDM_OVFL_ERR_E5_SHIFT                                                        9
+  #define MCM_REG_INT_STS_0_IS_PSDM_UNDER_ERR_E5                                                             (0x1<<10) // Read from empty PSDM input buffer.
+  #define MCM_REG_INT_STS_0_IS_PSDM_UNDER_ERR_E5_SHIFT                                                       10
+  #define MCM_REG_INT_STS_0_IS_USDM_OVFL_ERR_BB_K2                                                           (0x1<<7) // Write to full USDM input buffer.
+  #define MCM_REG_INT_STS_0_IS_USDM_OVFL_ERR_BB_K2_SHIFT                                                     7
+  #define MCM_REG_INT_STS_0_IS_USDM_OVFL_ERR_E5                                                              (0x1<<11) // Write to full USDM input buffer.
+  #define MCM_REG_INT_STS_0_IS_USDM_OVFL_ERR_E5_SHIFT                                                        11
+  #define MCM_REG_INT_STS_0_IS_USDM_UNDER_ERR_BB_K2                                                          (0x1<<8) // Read from empty USDM input buffer.
+  #define MCM_REG_INT_STS_0_IS_USDM_UNDER_ERR_BB_K2_SHIFT                                                    8
+  #define MCM_REG_INT_STS_0_IS_USDM_UNDER_ERR_E5                                                             (0x1<<12) // Read from empty USDM input buffer.
+  #define MCM_REG_INT_STS_0_IS_USDM_UNDER_ERR_E5_SHIFT                                                       12
+  #define MCM_REG_INT_STS_0_IS_TMLD_OVFL_ERR_BB_K2                                                           (0x1<<9) // Write to full TMLD input buffer.
+  #define MCM_REG_INT_STS_0_IS_TMLD_OVFL_ERR_BB_K2_SHIFT                                                     9
+  #define MCM_REG_INT_STS_0_IS_TMLD_OVFL_ERR_E5                                                              (0x1<<13) // Write to full TMLD input buffer.
+  #define MCM_REG_INT_STS_0_IS_TMLD_OVFL_ERR_E5_SHIFT                                                        13
+  #define MCM_REG_INT_STS_0_IS_TMLD_UNDER_ERR_BB_K2                                                          (0x1<<10) // Read from empty TMLD input buffer.
+  #define MCM_REG_INT_STS_0_IS_TMLD_UNDER_ERR_BB_K2_SHIFT                                                    10
+  #define MCM_REG_INT_STS_0_IS_TMLD_UNDER_ERR_E5                                                             (0x1<<14) // Read from empty TMLD input buffer.
+  #define MCM_REG_INT_STS_0_IS_TMLD_UNDER_ERR_E5_SHIFT                                                       14
+  #define MCM_REG_INT_STS_0_IS_USEM_OVFL_ERR_BB_K2                                                           (0x1<<11) // Write to full Usem input buffer.
+  #define MCM_REG_INT_STS_0_IS_USEM_OVFL_ERR_BB_K2_SHIFT                                                     11
+  #define MCM_REG_INT_STS_0_IS_USEM_OVFL_ERR_E5                                                              (0x1<<15) // Write to full Usem input buffer.
+  #define MCM_REG_INT_STS_0_IS_USEM_OVFL_ERR_E5_SHIFT                                                        15
+  #define MCM_REG_INT_STS_0_IS_USEM_UNDER_ERR_BB_K2                                                          (0x1<<12) // Read from empty Usem input buffer.
+  #define MCM_REG_INT_STS_0_IS_USEM_UNDER_ERR_BB_K2_SHIFT                                                    12
+  #define MCM_REG_INT_STS_0_IS_USEM_UNDER_ERR_E5                                                             (0x1<<16) // Read from empty Usem input buffer.
+  #define MCM_REG_INT_STS_0_IS_USEM_UNDER_ERR_E5_SHIFT                                                       16
+  #define MCM_REG_INT_STS_0_IS_YSEM_OVFL_ERR_BB_K2                                                           (0x1<<13) // Write to full Ysem input buffer.
+  #define MCM_REG_INT_STS_0_IS_YSEM_OVFL_ERR_BB_K2_SHIFT                                                     13
+  #define MCM_REG_INT_STS_0_IS_YSEM_OVFL_ERR_E5                                                              (0x1<<17) // Write to full Ysem input buffer.
+  #define MCM_REG_INT_STS_0_IS_YSEM_OVFL_ERR_E5_SHIFT                                                        17
+  #define MCM_REG_INT_STS_0_EXT_LD_UNDER_ERR_E5                                                              (0x1<<18) // Read from empty External read buffer.
+  #define MCM_REG_INT_STS_0_EXT_LD_UNDER_ERR_E5_SHIFT                                                        18
+  #define MCM_REG_INT_STS_0_EXT_LD_OVFL_ERR_E5                                                               (0x1<<19) // Write to fully External read buffer.
+  #define MCM_REG_INT_STS_0_EXT_LD_OVFL_ERR_E5_SHIFT                                                         19
+  #define MCM_REG_INT_STS_0_AFFINITY_TYPE_NO_CON_E5                                                          (0x1<<20) // Affinity type = 2 (connection based) but connection doesn't exist.
+  #define MCM_REG_INT_STS_0_AFFINITY_TYPE_NO_CON_E5_SHIFT                                                    20
+  #define MCM_REG_INT_STS_0_AFFINITY_TYPE_NO_TASK_E5                                                         (0x1<<21) // Affinity type = 3 (task based) but task doesn't exist.
+  #define MCM_REG_INT_STS_0_AFFINITY_TYPE_NO_TASK_E5_SHIFT                                                   21
+#define MCM_REG_INT_MASK_0                                                                                   0x1200184UL //Access:RW   DataWidth:0x16   // Multi Field Register.
+  #define MCM_REG_INT_MASK_0_ADDRESS_ERROR                                                                   (0x1<<0) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.ADDRESS_ERROR .
+  #define MCM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                             0
+  #define MCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR                                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_STORM_OVFL_ERR .
+  #define MCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR_SHIFT                                                         1
+  #define MCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR                                                              (0x1<<2) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_STORM_UNDER_ERR .
+  #define MCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR_SHIFT                                                        2
+  #define MCM_REG_INT_MASK_0_IS_MSDM_OVFL_ERR                                                                (0x1<<3) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_MSDM_OVFL_ERR .
+  #define MCM_REG_INT_MASK_0_IS_MSDM_OVFL_ERR_SHIFT                                                          3
+  #define MCM_REG_INT_MASK_0_IS_MSDM_UNDER_ERR                                                               (0x1<<4) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_MSDM_UNDER_ERR .
+  #define MCM_REG_INT_MASK_0_IS_MSDM_UNDER_ERR_SHIFT                                                         4
+  #define MCM_REG_INT_MASK_0_IS_YSDM_OVFL_ERR                                                                (0x1<<5) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_YSDM_OVFL_ERR .
+  #define MCM_REG_INT_MASK_0_IS_YSDM_OVFL_ERR_SHIFT                                                          5
+  #define MCM_REG_INT_MASK_0_IS_YSDM_UNDER_ERR                                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_YSDM_UNDER_ERR .
+  #define MCM_REG_INT_MASK_0_IS_YSDM_UNDER_ERR_SHIFT                                                         6
+  #define MCM_REG_INT_MASK_0_IS_TSDM_OVFL_ERR_E5                                                             (0x1<<7) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_TSDM_OVFL_ERR .
+  #define MCM_REG_INT_MASK_0_IS_TSDM_OVFL_ERR_E5_SHIFT                                                       7
+  #define MCM_REG_INT_MASK_0_IS_TSDM_UNDER_ERR_E5                                                            (0x1<<8) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_TSDM_UNDER_ERR .
+  #define MCM_REG_INT_MASK_0_IS_TSDM_UNDER_ERR_E5_SHIFT                                                      8
+  #define MCM_REG_INT_MASK_0_IS_PSDM_OVFL_ERR_E5                                                             (0x1<<9) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_PSDM_OVFL_ERR .
+  #define MCM_REG_INT_MASK_0_IS_PSDM_OVFL_ERR_E5_SHIFT                                                       9
+  #define MCM_REG_INT_MASK_0_IS_PSDM_UNDER_ERR_E5                                                            (0x1<<10) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_PSDM_UNDER_ERR .
+  #define MCM_REG_INT_MASK_0_IS_PSDM_UNDER_ERR_E5_SHIFT                                                      10
+  #define MCM_REG_INT_MASK_0_IS_USDM_OVFL_ERR_BB_K2                                                          (0x1<<7) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_USDM_OVFL_ERR .
+  #define MCM_REG_INT_MASK_0_IS_USDM_OVFL_ERR_BB_K2_SHIFT                                                    7
+  #define MCM_REG_INT_MASK_0_IS_USDM_OVFL_ERR_E5                                                             (0x1<<11) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_USDM_OVFL_ERR .
+  #define MCM_REG_INT_MASK_0_IS_USDM_OVFL_ERR_E5_SHIFT                                                       11
+  #define MCM_REG_INT_MASK_0_IS_USDM_UNDER_ERR_BB_K2                                                         (0x1<<8) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_USDM_UNDER_ERR .
+  #define MCM_REG_INT_MASK_0_IS_USDM_UNDER_ERR_BB_K2_SHIFT                                                   8
+  #define MCM_REG_INT_MASK_0_IS_USDM_UNDER_ERR_E5                                                            (0x1<<12) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_USDM_UNDER_ERR .
+  #define MCM_REG_INT_MASK_0_IS_USDM_UNDER_ERR_E5_SHIFT                                                      12
+  #define MCM_REG_INT_MASK_0_IS_TMLD_OVFL_ERR_BB_K2                                                          (0x1<<9) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_TMLD_OVFL_ERR .
+  #define MCM_REG_INT_MASK_0_IS_TMLD_OVFL_ERR_BB_K2_SHIFT                                                    9
+  #define MCM_REG_INT_MASK_0_IS_TMLD_OVFL_ERR_E5                                                             (0x1<<13) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_TMLD_OVFL_ERR .
+  #define MCM_REG_INT_MASK_0_IS_TMLD_OVFL_ERR_E5_SHIFT                                                       13
+  #define MCM_REG_INT_MASK_0_IS_TMLD_UNDER_ERR_BB_K2                                                         (0x1<<10) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_TMLD_UNDER_ERR .
+  #define MCM_REG_INT_MASK_0_IS_TMLD_UNDER_ERR_BB_K2_SHIFT                                                   10
+  #define MCM_REG_INT_MASK_0_IS_TMLD_UNDER_ERR_E5                                                            (0x1<<14) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_TMLD_UNDER_ERR .
+  #define MCM_REG_INT_MASK_0_IS_TMLD_UNDER_ERR_E5_SHIFT                                                      14
+  #define MCM_REG_INT_MASK_0_IS_USEM_OVFL_ERR_BB_K2                                                          (0x1<<11) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_USEM_OVFL_ERR .
+  #define MCM_REG_INT_MASK_0_IS_USEM_OVFL_ERR_BB_K2_SHIFT                                                    11
+  #define MCM_REG_INT_MASK_0_IS_USEM_OVFL_ERR_E5                                                             (0x1<<15) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_USEM_OVFL_ERR .
+  #define MCM_REG_INT_MASK_0_IS_USEM_OVFL_ERR_E5_SHIFT                                                       15
+  #define MCM_REG_INT_MASK_0_IS_USEM_UNDER_ERR_BB_K2                                                         (0x1<<12) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_USEM_UNDER_ERR .
+  #define MCM_REG_INT_MASK_0_IS_USEM_UNDER_ERR_BB_K2_SHIFT                                                   12
+  #define MCM_REG_INT_MASK_0_IS_USEM_UNDER_ERR_E5                                                            (0x1<<16) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_USEM_UNDER_ERR .
+  #define MCM_REG_INT_MASK_0_IS_USEM_UNDER_ERR_E5_SHIFT                                                      16
+  #define MCM_REG_INT_MASK_0_IS_YSEM_OVFL_ERR_BB_K2                                                          (0x1<<13) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_YSEM_OVFL_ERR .
+  #define MCM_REG_INT_MASK_0_IS_YSEM_OVFL_ERR_BB_K2_SHIFT                                                    13
+  #define MCM_REG_INT_MASK_0_IS_YSEM_OVFL_ERR_E5                                                             (0x1<<17) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_YSEM_OVFL_ERR .
+  #define MCM_REG_INT_MASK_0_IS_YSEM_OVFL_ERR_E5_SHIFT                                                       17
+  #define MCM_REG_INT_MASK_0_EXT_LD_UNDER_ERR_E5                                                             (0x1<<18) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.EXT_LD_UNDER_ERR .
+  #define MCM_REG_INT_MASK_0_EXT_LD_UNDER_ERR_E5_SHIFT                                                       18
+  #define MCM_REG_INT_MASK_0_EXT_LD_OVFL_ERR_E5                                                              (0x1<<19) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.EXT_LD_OVFL_ERR .
+  #define MCM_REG_INT_MASK_0_EXT_LD_OVFL_ERR_E5_SHIFT                                                        19
+  #define MCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_CON_E5                                                         (0x1<<20) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.AFFINITY_TYPE_NO_CON .
+  #define MCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_CON_E5_SHIFT                                                   20
+  #define MCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_TASK_E5                                                        (0x1<<21) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.AFFINITY_TYPE_NO_TASK .
+  #define MCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_TASK_E5_SHIFT                                                  21
+#define MCM_REG_INT_STS_WR_0                                                                                 0x1200188UL //Access:WR   DataWidth:0x16   // Multi Field Register.
+  #define MCM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define MCM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                           0
+  #define MCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR                                                             (0x1<<1) // Write to full STORM input buffer.
+  #define MCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR_SHIFT                                                       1
+  #define MCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR                                                            (0x1<<2) // Read from empty  STORM input buffer.
+  #define MCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR_SHIFT                                                      2
+  #define MCM_REG_INT_STS_WR_0_IS_MSDM_OVFL_ERR                                                              (0x1<<3) // Write to full MSDM input buffer.
+  #define MCM_REG_INT_STS_WR_0_IS_MSDM_OVFL_ERR_SHIFT                                                        3
+  #define MCM_REG_INT_STS_WR_0_IS_MSDM_UNDER_ERR                                                             (0x1<<4) // Read from empty MSDM input buffer.
+  #define MCM_REG_INT_STS_WR_0_IS_MSDM_UNDER_ERR_SHIFT                                                       4
+  #define MCM_REG_INT_STS_WR_0_IS_YSDM_OVFL_ERR                                                              (0x1<<5) // Write to full YSDM input buffer.
+  #define MCM_REG_INT_STS_WR_0_IS_YSDM_OVFL_ERR_SHIFT                                                        5
+  #define MCM_REG_INT_STS_WR_0_IS_YSDM_UNDER_ERR                                                             (0x1<<6) // Read from empty  YSDM input buffer.
+  #define MCM_REG_INT_STS_WR_0_IS_YSDM_UNDER_ERR_SHIFT                                                       6
+  #define MCM_REG_INT_STS_WR_0_IS_TSDM_OVFL_ERR_E5                                                           (0x1<<7) // Write to full TSDM input buffer.
+  #define MCM_REG_INT_STS_WR_0_IS_TSDM_OVFL_ERR_E5_SHIFT                                                     7
+  #define MCM_REG_INT_STS_WR_0_IS_TSDM_UNDER_ERR_E5                                                          (0x1<<8) // Read from empty TSDM input buffer.
+  #define MCM_REG_INT_STS_WR_0_IS_TSDM_UNDER_ERR_E5_SHIFT                                                    8
+  #define MCM_REG_INT_STS_WR_0_IS_PSDM_OVFL_ERR_E5                                                           (0x1<<9) // Write to full PSDM input buffer.
+  #define MCM_REG_INT_STS_WR_0_IS_PSDM_OVFL_ERR_E5_SHIFT                                                     9
+  #define MCM_REG_INT_STS_WR_0_IS_PSDM_UNDER_ERR_E5                                                          (0x1<<10) // Read from empty PSDM input buffer.
+  #define MCM_REG_INT_STS_WR_0_IS_PSDM_UNDER_ERR_E5_SHIFT                                                    10
+  #define MCM_REG_INT_STS_WR_0_IS_USDM_OVFL_ERR_BB_K2                                                        (0x1<<7) // Write to full USDM input buffer.
+  #define MCM_REG_INT_STS_WR_0_IS_USDM_OVFL_ERR_BB_K2_SHIFT                                                  7
+  #define MCM_REG_INT_STS_WR_0_IS_USDM_OVFL_ERR_E5                                                           (0x1<<11) // Write to full USDM input buffer.
+  #define MCM_REG_INT_STS_WR_0_IS_USDM_OVFL_ERR_E5_SHIFT                                                     11
+  #define MCM_REG_INT_STS_WR_0_IS_USDM_UNDER_ERR_BB_K2                                                       (0x1<<8) // Read from empty USDM input buffer.
+  #define MCM_REG_INT_STS_WR_0_IS_USDM_UNDER_ERR_BB_K2_SHIFT                                                 8
+  #define MCM_REG_INT_STS_WR_0_IS_USDM_UNDER_ERR_E5                                                          (0x1<<12) // Read from empty USDM input buffer.
+  #define MCM_REG_INT_STS_WR_0_IS_USDM_UNDER_ERR_E5_SHIFT                                                    12
+  #define MCM_REG_INT_STS_WR_0_IS_TMLD_OVFL_ERR_BB_K2                                                        (0x1<<9) // Write to full TMLD input buffer.
+  #define MCM_REG_INT_STS_WR_0_IS_TMLD_OVFL_ERR_BB_K2_SHIFT                                                  9
+  #define MCM_REG_INT_STS_WR_0_IS_TMLD_OVFL_ERR_E5                                                           (0x1<<13) // Write to full TMLD input buffer.
+  #define MCM_REG_INT_STS_WR_0_IS_TMLD_OVFL_ERR_E5_SHIFT                                                     13
+  #define MCM_REG_INT_STS_WR_0_IS_TMLD_UNDER_ERR_BB_K2                                                       (0x1<<10) // Read from empty TMLD input buffer.
+  #define MCM_REG_INT_STS_WR_0_IS_TMLD_UNDER_ERR_BB_K2_SHIFT                                                 10
+  #define MCM_REG_INT_STS_WR_0_IS_TMLD_UNDER_ERR_E5                                                          (0x1<<14) // Read from empty TMLD input buffer.
+  #define MCM_REG_INT_STS_WR_0_IS_TMLD_UNDER_ERR_E5_SHIFT                                                    14
+  #define MCM_REG_INT_STS_WR_0_IS_USEM_OVFL_ERR_BB_K2                                                        (0x1<<11) // Write to full Usem input buffer.
+  #define MCM_REG_INT_STS_WR_0_IS_USEM_OVFL_ERR_BB_K2_SHIFT                                                  11
+  #define MCM_REG_INT_STS_WR_0_IS_USEM_OVFL_ERR_E5                                                           (0x1<<15) // Write to full Usem input buffer.
+  #define MCM_REG_INT_STS_WR_0_IS_USEM_OVFL_ERR_E5_SHIFT                                                     15
+  #define MCM_REG_INT_STS_WR_0_IS_USEM_UNDER_ERR_BB_K2                                                       (0x1<<12) // Read from empty Usem input buffer.
+  #define MCM_REG_INT_STS_WR_0_IS_USEM_UNDER_ERR_BB_K2_SHIFT                                                 12
+  #define MCM_REG_INT_STS_WR_0_IS_USEM_UNDER_ERR_E5                                                          (0x1<<16) // Read from empty Usem input buffer.
+  #define MCM_REG_INT_STS_WR_0_IS_USEM_UNDER_ERR_E5_SHIFT                                                    16
+  #define MCM_REG_INT_STS_WR_0_IS_YSEM_OVFL_ERR_BB_K2                                                        (0x1<<13) // Write to full Ysem input buffer.
+  #define MCM_REG_INT_STS_WR_0_IS_YSEM_OVFL_ERR_BB_K2_SHIFT                                                  13
+  #define MCM_REG_INT_STS_WR_0_IS_YSEM_OVFL_ERR_E5                                                           (0x1<<17) // Write to full Ysem input buffer.
+  #define MCM_REG_INT_STS_WR_0_IS_YSEM_OVFL_ERR_E5_SHIFT                                                     17
+  #define MCM_REG_INT_STS_WR_0_EXT_LD_UNDER_ERR_E5                                                           (0x1<<18) // Read from empty External read buffer.
+  #define MCM_REG_INT_STS_WR_0_EXT_LD_UNDER_ERR_E5_SHIFT                                                     18
+  #define MCM_REG_INT_STS_WR_0_EXT_LD_OVFL_ERR_E5                                                            (0x1<<19) // Write to fully External read buffer.
+  #define MCM_REG_INT_STS_WR_0_EXT_LD_OVFL_ERR_E5_SHIFT                                                      19
+  #define MCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_CON_E5                                                       (0x1<<20) // Affinity type = 2 (connection based) but connection doesn't exist.
+  #define MCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_CON_E5_SHIFT                                                 20
+  #define MCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_TASK_E5                                                      (0x1<<21) // Affinity type = 3 (task based) but task doesn't exist.
+  #define MCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_TASK_E5_SHIFT                                                21
+#define MCM_REG_INT_STS_CLR_0                                                                                0x120018cUL //Access:RC   DataWidth:0x16   // Multi Field Register.
+  #define MCM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define MCM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                          0
+  #define MCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR                                                            (0x1<<1) // Write to full STORM input buffer.
+  #define MCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR_SHIFT                                                      1
+  #define MCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR                                                           (0x1<<2) // Read from empty  STORM input buffer.
+  #define MCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR_SHIFT                                                     2
+  #define MCM_REG_INT_STS_CLR_0_IS_MSDM_OVFL_ERR                                                             (0x1<<3) // Write to full MSDM input buffer.
+  #define MCM_REG_INT_STS_CLR_0_IS_MSDM_OVFL_ERR_SHIFT                                                       3
+  #define MCM_REG_INT_STS_CLR_0_IS_MSDM_UNDER_ERR                                                            (0x1<<4) // Read from empty MSDM input buffer.
+  #define MCM_REG_INT_STS_CLR_0_IS_MSDM_UNDER_ERR_SHIFT                                                      4
+  #define MCM_REG_INT_STS_CLR_0_IS_YSDM_OVFL_ERR                                                             (0x1<<5) // Write to full YSDM input buffer.
+  #define MCM_REG_INT_STS_CLR_0_IS_YSDM_OVFL_ERR_SHIFT                                                       5
+  #define MCM_REG_INT_STS_CLR_0_IS_YSDM_UNDER_ERR                                                            (0x1<<6) // Read from empty  YSDM input buffer.
+  #define MCM_REG_INT_STS_CLR_0_IS_YSDM_UNDER_ERR_SHIFT                                                      6
+  #define MCM_REG_INT_STS_CLR_0_IS_TSDM_OVFL_ERR_E5                                                          (0x1<<7) // Write to full TSDM input buffer.
+  #define MCM_REG_INT_STS_CLR_0_IS_TSDM_OVFL_ERR_E5_SHIFT                                                    7
+  #define MCM_REG_INT_STS_CLR_0_IS_TSDM_UNDER_ERR_E5                                                         (0x1<<8) // Read from empty TSDM input buffer.
+  #define MCM_REG_INT_STS_CLR_0_IS_TSDM_UNDER_ERR_E5_SHIFT                                                   8
+  #define MCM_REG_INT_STS_CLR_0_IS_PSDM_OVFL_ERR_E5                                                          (0x1<<9) // Write to full PSDM input buffer.
+  #define MCM_REG_INT_STS_CLR_0_IS_PSDM_OVFL_ERR_E5_SHIFT                                                    9
+  #define MCM_REG_INT_STS_CLR_0_IS_PSDM_UNDER_ERR_E5                                                         (0x1<<10) // Read from empty PSDM input buffer.
+  #define MCM_REG_INT_STS_CLR_0_IS_PSDM_UNDER_ERR_E5_SHIFT                                                   10
+  #define MCM_REG_INT_STS_CLR_0_IS_USDM_OVFL_ERR_BB_K2                                                       (0x1<<7) // Write to full USDM input buffer.
+  #define MCM_REG_INT_STS_CLR_0_IS_USDM_OVFL_ERR_BB_K2_SHIFT                                                 7
+  #define MCM_REG_INT_STS_CLR_0_IS_USDM_OVFL_ERR_E5                                                          (0x1<<11) // Write to full USDM input buffer.
+  #define MCM_REG_INT_STS_CLR_0_IS_USDM_OVFL_ERR_E5_SHIFT                                                    11
+  #define MCM_REG_INT_STS_CLR_0_IS_USDM_UNDER_ERR_BB_K2                                                      (0x1<<8) // Read from empty USDM input buffer.
+  #define MCM_REG_INT_STS_CLR_0_IS_USDM_UNDER_ERR_BB_K2_SHIFT                                                8
+  #define MCM_REG_INT_STS_CLR_0_IS_USDM_UNDER_ERR_E5                                                         (0x1<<12) // Read from empty USDM input buffer.
+  #define MCM_REG_INT_STS_CLR_0_IS_USDM_UNDER_ERR_E5_SHIFT                                                   12
+  #define MCM_REG_INT_STS_CLR_0_IS_TMLD_OVFL_ERR_BB_K2                                                       (0x1<<9) // Write to full TMLD input buffer.
+  #define MCM_REG_INT_STS_CLR_0_IS_TMLD_OVFL_ERR_BB_K2_SHIFT                                                 9
+  #define MCM_REG_INT_STS_CLR_0_IS_TMLD_OVFL_ERR_E5                                                          (0x1<<13) // Write to full TMLD input buffer.
+  #define MCM_REG_INT_STS_CLR_0_IS_TMLD_OVFL_ERR_E5_SHIFT                                                    13
+  #define MCM_REG_INT_STS_CLR_0_IS_TMLD_UNDER_ERR_BB_K2                                                      (0x1<<10) // Read from empty TMLD input buffer.
+  #define MCM_REG_INT_STS_CLR_0_IS_TMLD_UNDER_ERR_BB_K2_SHIFT                                                10
+  #define MCM_REG_INT_STS_CLR_0_IS_TMLD_UNDER_ERR_E5                                                         (0x1<<14) // Read from empty TMLD input buffer.
+  #define MCM_REG_INT_STS_CLR_0_IS_TMLD_UNDER_ERR_E5_SHIFT                                                   14
+  #define MCM_REG_INT_STS_CLR_0_IS_USEM_OVFL_ERR_BB_K2                                                       (0x1<<11) // Write to full Usem input buffer.
+  #define MCM_REG_INT_STS_CLR_0_IS_USEM_OVFL_ERR_BB_K2_SHIFT                                                 11
+  #define MCM_REG_INT_STS_CLR_0_IS_USEM_OVFL_ERR_E5                                                          (0x1<<15) // Write to full Usem input buffer.
+  #define MCM_REG_INT_STS_CLR_0_IS_USEM_OVFL_ERR_E5_SHIFT                                                    15
+  #define MCM_REG_INT_STS_CLR_0_IS_USEM_UNDER_ERR_BB_K2                                                      (0x1<<12) // Read from empty Usem input buffer.
+  #define MCM_REG_INT_STS_CLR_0_IS_USEM_UNDER_ERR_BB_K2_SHIFT                                                12
+  #define MCM_REG_INT_STS_CLR_0_IS_USEM_UNDER_ERR_E5                                                         (0x1<<16) // Read from empty Usem input buffer.
+  #define MCM_REG_INT_STS_CLR_0_IS_USEM_UNDER_ERR_E5_SHIFT                                                   16
+  #define MCM_REG_INT_STS_CLR_0_IS_YSEM_OVFL_ERR_BB_K2                                                       (0x1<<13) // Write to full Ysem input buffer.
+  #define MCM_REG_INT_STS_CLR_0_IS_YSEM_OVFL_ERR_BB_K2_SHIFT                                                 13
+  #define MCM_REG_INT_STS_CLR_0_IS_YSEM_OVFL_ERR_E5                                                          (0x1<<17) // Write to full Ysem input buffer.
+  #define MCM_REG_INT_STS_CLR_0_IS_YSEM_OVFL_ERR_E5_SHIFT                                                    17
+  #define MCM_REG_INT_STS_CLR_0_EXT_LD_UNDER_ERR_E5                                                          (0x1<<18) // Read from empty External read buffer.
+  #define MCM_REG_INT_STS_CLR_0_EXT_LD_UNDER_ERR_E5_SHIFT                                                    18
+  #define MCM_REG_INT_STS_CLR_0_EXT_LD_OVFL_ERR_E5                                                           (0x1<<19) // Write to fully External read buffer.
+  #define MCM_REG_INT_STS_CLR_0_EXT_LD_OVFL_ERR_E5_SHIFT                                                     19
+  #define MCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_CON_E5                                                      (0x1<<20) // Affinity type = 2 (connection based) but connection doesn't exist.
+  #define MCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_CON_E5_SHIFT                                                20
+  #define MCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_TASK_E5                                                     (0x1<<21) // Affinity type = 3 (task based) but task doesn't exist.
+  #define MCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_TASK_E5_SHIFT                                               21
+#define MCM_REG_INT_STS_1                                                                                    0x1200190UL //Access:R    DataWidth:0x1a   // Multi Field Register.
+  #define MCM_REG_INT_STS_1_IS_YSEM_UNDER_ERR                                                                (0x1<<0) // Read from empty  Ysem input buffer.
+  #define MCM_REG_INT_STS_1_IS_YSEM_UNDER_ERR_SHIFT                                                          0
+  #define MCM_REG_INT_STS_1_IS_PBF_OVFL_ERR                                                                  (0x1<<1) // Write to full Pbf input buffer.
+  #define MCM_REG_INT_STS_1_IS_PBF_OVFL_ERR_SHIFT                                                            1
+  #define MCM_REG_INT_STS_1_IS_PBF_UNDER_ERR                                                                 (0x1<<2) // Read from empty Pbf input buffer.
+  #define MCM_REG_INT_STS_1_IS_PBF_UNDER_ERR_SHIFT                                                           2
+  #define MCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR                                                                 (0x1<<3) // Write to full QM input buffer.
+  #define MCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR_SHIFT                                                           3
+  #define MCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR                                                                (0x1<<4) // Read from empty QM input buffer.
+  #define MCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR_SHIFT                                                          4
+  #define MCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR                                                                 (0x1<<5) // Write to full QM input buffer.
+  #define MCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR_SHIFT                                                           5
+  #define MCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR                                                                (0x1<<6) // Read from empty QM input buffer.
+  #define MCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR_SHIFT                                                          6
+  #define MCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0                                                                 (0x1<<7) // Write to full GRC input buffer bits [31:0].
+  #define MCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0_SHIFT                                                           7
+  #define MCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0                                                                (0x1<<8) // Read from empty  GRC input buffer bits [31:0].
+  #define MCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0_SHIFT                                                          8
+  #define MCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1                                                                 (0x1<<9) // Write to full GRC input buffer bits [63:32].
+  #define MCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1_SHIFT                                                           9
+  #define MCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1                                                                (0x1<<10) // Read from empty  GRC input buffer bits [63:32].
+  #define MCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1_SHIFT                                                          10
+  #define MCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2                                                                 (0x1<<11) // Write to full GRC input buffer bits [95:64].
+  #define MCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2_SHIFT                                                           11
+  #define MCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2                                                                (0x1<<12) // Read from empty  GRC input buffer bits [95:64].
+  #define MCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2_SHIFT                                                          12
+  #define MCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3                                                                 (0x1<<13) // Write to full GRC input buffer bits [127:96].
+  #define MCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3_SHIFT                                                           13
+  #define MCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3                                                                (0x1<<14) // Read from empty  GRC input buffer bits [127:96].
+  #define MCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3_SHIFT                                                          14
+  #define MCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL                                                                 (0x1<<15) // In-process Table overflow.
+  #define MCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL_SHIFT                                                           15
+  #define MCM_REG_INT_STS_1_AGG_CON_DATA_BUF_OVFL                                                            (0x1<<16) // Message Processor Aggregation Connection Data buffer overflow.
+  #define MCM_REG_INT_STS_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                                      16
+  #define MCM_REG_INT_STS_1_AGG_CON_CMD_BUF_OVFL                                                             (0x1<<17) // Message Processor Aggregation Connection Command buffer overflow.
+  #define MCM_REG_INT_STS_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                                       17
+  #define MCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL                                                             (0x1<<18) // Message Processor Storm Connection Data buffer overflow.
+  #define MCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL_SHIFT                                                       18
+  #define MCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL                                                              (0x1<<19) // Message Processor Storm Connection Command buffer overflow.
+  #define MCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL_SHIFT                                                        19
+  #define MCM_REG_INT_STS_1_AGG_TASK_DATA_BUF_OVFL                                                           (0x1<<20) // Message Processor Aggregation Task Data buffer overflow.
+  #define MCM_REG_INT_STS_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                                     20
+  #define MCM_REG_INT_STS_1_AGG_TASK_CMD_BUF_OVFL                                                            (0x1<<21) // Message Processor Aggregation Task Command buffer overflow.
+  #define MCM_REG_INT_STS_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                                      21
+  #define MCM_REG_INT_STS_1_SM_TASK_DATA_BUF_OVFL                                                            (0x1<<22) // Message Processor Storm Task Data buffer overflow.
+  #define MCM_REG_INT_STS_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                                      22
+  #define MCM_REG_INT_STS_1_SM_TASK_CMD_BUF_OVFL                                                             (0x1<<23) // Message Processor Storm Task Command buffer overflow.
+  #define MCM_REG_INT_STS_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                                       23
+  #define MCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE                                                            (0x1<<24) // Input message first descriptor fields violation.
+  #define MCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE_SHIFT                                                      24
+  #define MCM_REG_INT_STS_1_SE_DESC_INPUT_VIOLATE                                                            (0x1<<25) // Input message second descriptor fields violation.
+  #define MCM_REG_INT_STS_1_SE_DESC_INPUT_VIOLATE_SHIFT                                                      25
+#define MCM_REG_INT_MASK_1                                                                                   0x1200194UL //Access:RW   DataWidth:0x1a   // Multi Field Register.
+  #define MCM_REG_INT_MASK_1_IS_YSEM_UNDER_ERR                                                               (0x1<<0) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_YSEM_UNDER_ERR .
+  #define MCM_REG_INT_MASK_1_IS_YSEM_UNDER_ERR_SHIFT                                                         0
+  #define MCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR                                                                 (0x1<<1) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_PBF_OVFL_ERR .
+  #define MCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR_SHIFT                                                           1
+  #define MCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR                                                                (0x1<<2) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_PBF_UNDER_ERR .
+  #define MCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR_SHIFT                                                          2
+  #define MCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR                                                                (0x1<<3) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_QM_P_OVFL_ERR .
+  #define MCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR_SHIFT                                                          3
+  #define MCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR                                                               (0x1<<4) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_QM_P_UNDER_ERR .
+  #define MCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR_SHIFT                                                         4
+  #define MCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR                                                                (0x1<<5) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_QM_S_OVFL_ERR .
+  #define MCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR_SHIFT                                                          5
+  #define MCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR                                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_QM_S_UNDER_ERR .
+  #define MCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR_SHIFT                                                         6
+  #define MCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0                                                                (0x1<<7) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_GRC_OVFL_ERR0 .
+  #define MCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0_SHIFT                                                          7
+  #define MCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0                                                               (0x1<<8) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_GRC_UNDER_ERR0 .
+  #define MCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0_SHIFT                                                         8
+  #define MCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1                                                                (0x1<<9) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_GRC_OVFL_ERR1 .
+  #define MCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1_SHIFT                                                          9
+  #define MCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1                                                               (0x1<<10) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_GRC_UNDER_ERR1 .
+  #define MCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1_SHIFT                                                         10
+  #define MCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2                                                                (0x1<<11) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_GRC_OVFL_ERR2 .
+  #define MCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2_SHIFT                                                          11
+  #define MCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2                                                               (0x1<<12) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_GRC_UNDER_ERR2 .
+  #define MCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2_SHIFT                                                         12
+  #define MCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3                                                                (0x1<<13) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_GRC_OVFL_ERR3 .
+  #define MCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3_SHIFT                                                          13
+  #define MCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3                                                               (0x1<<14) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_GRC_UNDER_ERR3 .
+  #define MCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3_SHIFT                                                         14
+  #define MCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL                                                                (0x1<<15) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IN_PRCS_TBL_OVFL .
+  #define MCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL_SHIFT                                                          15
+  #define MCM_REG_INT_MASK_1_AGG_CON_DATA_BUF_OVFL                                                           (0x1<<16) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.AGG_CON_DATA_BUF_OVFL .
+  #define MCM_REG_INT_MASK_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                                     16
+  #define MCM_REG_INT_MASK_1_AGG_CON_CMD_BUF_OVFL                                                            (0x1<<17) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.AGG_CON_CMD_BUF_OVFL .
+  #define MCM_REG_INT_MASK_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                                      17
+  #define MCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL                                                            (0x1<<18) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.SM_CON_DATA_BUF_OVFL .
+  #define MCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL_SHIFT                                                      18
+  #define MCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL                                                             (0x1<<19) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.SM_CON_CMD_BUF_OVFL .
+  #define MCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL_SHIFT                                                       19
+  #define MCM_REG_INT_MASK_1_AGG_TASK_DATA_BUF_OVFL                                                          (0x1<<20) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.AGG_TASK_DATA_BUF_OVFL .
+  #define MCM_REG_INT_MASK_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                                    20
+  #define MCM_REG_INT_MASK_1_AGG_TASK_CMD_BUF_OVFL                                                           (0x1<<21) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.AGG_TASK_CMD_BUF_OVFL .
+  #define MCM_REG_INT_MASK_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                                     21
+  #define MCM_REG_INT_MASK_1_SM_TASK_DATA_BUF_OVFL                                                           (0x1<<22) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.SM_TASK_DATA_BUF_OVFL .
+  #define MCM_REG_INT_MASK_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                                     22
+  #define MCM_REG_INT_MASK_1_SM_TASK_CMD_BUF_OVFL                                                            (0x1<<23) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.SM_TASK_CMD_BUF_OVFL .
+  #define MCM_REG_INT_MASK_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                                      23
+  #define MCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE                                                           (0x1<<24) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.FI_DESC_INPUT_VIOLATE .
+  #define MCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE_SHIFT                                                     24
+  #define MCM_REG_INT_MASK_1_SE_DESC_INPUT_VIOLATE                                                           (0x1<<25) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.SE_DESC_INPUT_VIOLATE .
+  #define MCM_REG_INT_MASK_1_SE_DESC_INPUT_VIOLATE_SHIFT                                                     25
+#define MCM_REG_INT_STS_WR_1                                                                                 0x1200198UL //Access:WR   DataWidth:0x1a   // Multi Field Register.
+  #define MCM_REG_INT_STS_WR_1_IS_YSEM_UNDER_ERR                                                             (0x1<<0) // Read from empty  Ysem input buffer.
+  #define MCM_REG_INT_STS_WR_1_IS_YSEM_UNDER_ERR_SHIFT                                                       0
+  #define MCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR                                                               (0x1<<1) // Write to full Pbf input buffer.
+  #define MCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR_SHIFT                                                         1
+  #define MCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR                                                              (0x1<<2) // Read from empty Pbf input buffer.
+  #define MCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR_SHIFT                                                        2
+  #define MCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR                                                              (0x1<<3) // Write to full QM input buffer.
+  #define MCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR_SHIFT                                                        3
+  #define MCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR                                                             (0x1<<4) // Read from empty QM input buffer.
+  #define MCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR_SHIFT                                                       4
+  #define MCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR                                                              (0x1<<5) // Write to full QM input buffer.
+  #define MCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR_SHIFT                                                        5
+  #define MCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR                                                             (0x1<<6) // Read from empty QM input buffer.
+  #define MCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR_SHIFT                                                       6
+  #define MCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0                                                              (0x1<<7) // Write to full GRC input buffer bits [31:0].
+  #define MCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0_SHIFT                                                        7
+  #define MCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0                                                             (0x1<<8) // Read from empty  GRC input buffer bits [31:0].
+  #define MCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0_SHIFT                                                       8
+  #define MCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1                                                              (0x1<<9) // Write to full GRC input buffer bits [63:32].
+  #define MCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1_SHIFT                                                        9
+  #define MCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1                                                             (0x1<<10) // Read from empty  GRC input buffer bits [63:32].
+  #define MCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1_SHIFT                                                       10
+  #define MCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2                                                              (0x1<<11) // Write to full GRC input buffer bits [95:64].
+  #define MCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2_SHIFT                                                        11
+  #define MCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2                                                             (0x1<<12) // Read from empty  GRC input buffer bits [95:64].
+  #define MCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2_SHIFT                                                       12
+  #define MCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3                                                              (0x1<<13) // Write to full GRC input buffer bits [127:96].
+  #define MCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3_SHIFT                                                        13
+  #define MCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3                                                             (0x1<<14) // Read from empty  GRC input buffer bits [127:96].
+  #define MCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3_SHIFT                                                       14
+  #define MCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL                                                              (0x1<<15) // In-process Table overflow.
+  #define MCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL_SHIFT                                                        15
+  #define MCM_REG_INT_STS_WR_1_AGG_CON_DATA_BUF_OVFL                                                         (0x1<<16) // Message Processor Aggregation Connection Data buffer overflow.
+  #define MCM_REG_INT_STS_WR_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                                   16
+  #define MCM_REG_INT_STS_WR_1_AGG_CON_CMD_BUF_OVFL                                                          (0x1<<17) // Message Processor Aggregation Connection Command buffer overflow.
+  #define MCM_REG_INT_STS_WR_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                                    17
+  #define MCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL                                                          (0x1<<18) // Message Processor Storm Connection Data buffer overflow.
+  #define MCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL_SHIFT                                                    18
+  #define MCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL                                                           (0x1<<19) // Message Processor Storm Connection Command buffer overflow.
+  #define MCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL_SHIFT                                                     19
+  #define MCM_REG_INT_STS_WR_1_AGG_TASK_DATA_BUF_OVFL                                                        (0x1<<20) // Message Processor Aggregation Task Data buffer overflow.
+  #define MCM_REG_INT_STS_WR_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                                  20
+  #define MCM_REG_INT_STS_WR_1_AGG_TASK_CMD_BUF_OVFL                                                         (0x1<<21) // Message Processor Aggregation Task Command buffer overflow.
+  #define MCM_REG_INT_STS_WR_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                                   21
+  #define MCM_REG_INT_STS_WR_1_SM_TASK_DATA_BUF_OVFL                                                         (0x1<<22) // Message Processor Storm Task Data buffer overflow.
+  #define MCM_REG_INT_STS_WR_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                                   22
+  #define MCM_REG_INT_STS_WR_1_SM_TASK_CMD_BUF_OVFL                                                          (0x1<<23) // Message Processor Storm Task Command buffer overflow.
+  #define MCM_REG_INT_STS_WR_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                                    23
+  #define MCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE                                                         (0x1<<24) // Input message first descriptor fields violation.
+  #define MCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE_SHIFT                                                   24
+  #define MCM_REG_INT_STS_WR_1_SE_DESC_INPUT_VIOLATE                                                         (0x1<<25) // Input message second descriptor fields violation.
+  #define MCM_REG_INT_STS_WR_1_SE_DESC_INPUT_VIOLATE_SHIFT                                                   25
+#define MCM_REG_INT_STS_CLR_1                                                                                0x120019cUL //Access:RC   DataWidth:0x1a   // Multi Field Register.
+  #define MCM_REG_INT_STS_CLR_1_IS_YSEM_UNDER_ERR                                                            (0x1<<0) // Read from empty  Ysem input buffer.
+  #define MCM_REG_INT_STS_CLR_1_IS_YSEM_UNDER_ERR_SHIFT                                                      0
+  #define MCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR                                                              (0x1<<1) // Write to full Pbf input buffer.
+  #define MCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR_SHIFT                                                        1
+  #define MCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR                                                             (0x1<<2) // Read from empty Pbf input buffer.
+  #define MCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR_SHIFT                                                       2
+  #define MCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR                                                             (0x1<<3) // Write to full QM input buffer.
+  #define MCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR_SHIFT                                                       3
+  #define MCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR                                                            (0x1<<4) // Read from empty QM input buffer.
+  #define MCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR_SHIFT                                                      4
+  #define MCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR                                                             (0x1<<5) // Write to full QM input buffer.
+  #define MCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR_SHIFT                                                       5
+  #define MCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR                                                            (0x1<<6) // Read from empty QM input buffer.
+  #define MCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR_SHIFT                                                      6
+  #define MCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0                                                             (0x1<<7) // Write to full GRC input buffer bits [31:0].
+  #define MCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0_SHIFT                                                       7
+  #define MCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0                                                            (0x1<<8) // Read from empty  GRC input buffer bits [31:0].
+  #define MCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0_SHIFT                                                      8
+  #define MCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1                                                             (0x1<<9) // Write to full GRC input buffer bits [63:32].
+  #define MCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1_SHIFT                                                       9
+  #define MCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1                                                            (0x1<<10) // Read from empty  GRC input buffer bits [63:32].
+  #define MCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1_SHIFT                                                      10
+  #define MCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2                                                             (0x1<<11) // Write to full GRC input buffer bits [95:64].
+  #define MCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2_SHIFT                                                       11
+  #define MCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2                                                            (0x1<<12) // Read from empty  GRC input buffer bits [95:64].
+  #define MCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2_SHIFT                                                      12
+  #define MCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3                                                             (0x1<<13) // Write to full GRC input buffer bits [127:96].
+  #define MCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3_SHIFT                                                       13
+  #define MCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3                                                            (0x1<<14) // Read from empty  GRC input buffer bits [127:96].
+  #define MCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3_SHIFT                                                      14
+  #define MCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL                                                             (0x1<<15) // In-process Table overflow.
+  #define MCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL_SHIFT                                                       15
+  #define MCM_REG_INT_STS_CLR_1_AGG_CON_DATA_BUF_OVFL                                                        (0x1<<16) // Message Processor Aggregation Connection Data buffer overflow.
+  #define MCM_REG_INT_STS_CLR_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                                  16
+  #define MCM_REG_INT_STS_CLR_1_AGG_CON_CMD_BUF_OVFL                                                         (0x1<<17) // Message Processor Aggregation Connection Command buffer overflow.
+  #define MCM_REG_INT_STS_CLR_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                                   17
+  #define MCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL                                                         (0x1<<18) // Message Processor Storm Connection Data buffer overflow.
+  #define MCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL_SHIFT                                                   18
+  #define MCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL                                                          (0x1<<19) // Message Processor Storm Connection Command buffer overflow.
+  #define MCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL_SHIFT                                                    19
+  #define MCM_REG_INT_STS_CLR_1_AGG_TASK_DATA_BUF_OVFL                                                       (0x1<<20) // Message Processor Aggregation Task Data buffer overflow.
+  #define MCM_REG_INT_STS_CLR_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                                 20
+  #define MCM_REG_INT_STS_CLR_1_AGG_TASK_CMD_BUF_OVFL                                                        (0x1<<21) // Message Processor Aggregation Task Command buffer overflow.
+  #define MCM_REG_INT_STS_CLR_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                                  21
+  #define MCM_REG_INT_STS_CLR_1_SM_TASK_DATA_BUF_OVFL                                                        (0x1<<22) // Message Processor Storm Task Data buffer overflow.
+  #define MCM_REG_INT_STS_CLR_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                                  22
+  #define MCM_REG_INT_STS_CLR_1_SM_TASK_CMD_BUF_OVFL                                                         (0x1<<23) // Message Processor Storm Task Command buffer overflow.
+  #define MCM_REG_INT_STS_CLR_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                                   23
+  #define MCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE                                                        (0x1<<24) // Input message first descriptor fields violation.
+  #define MCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE_SHIFT                                                  24
+  #define MCM_REG_INT_STS_CLR_1_SE_DESC_INPUT_VIOLATE                                                        (0x1<<25) // Input message second descriptor fields violation.
+  #define MCM_REG_INT_STS_CLR_1_SE_DESC_INPUT_VIOLATE_SHIFT                                                  25
+#define MCM_REG_INT_STS_2                                                                                    0x12001a0UL //Access:R    DataWidth:0x1    // Multi Field Register.
+  #define MCM_REG_INT_STS_2_QMREG_MORE4                                                                      (0x1<<0) // More than 4 QM registrations.
+  #define MCM_REG_INT_STS_2_QMREG_MORE4_SHIFT                                                                0
+#define MCM_REG_INT_MASK_2                                                                                   0x12001a4UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define MCM_REG_INT_MASK_2_QMREG_MORE4                                                                     (0x1<<0) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_2.QMREG_MORE4 .
+  #define MCM_REG_INT_MASK_2_QMREG_MORE4_SHIFT                                                               0
+#define MCM_REG_INT_STS_WR_2                                                                                 0x12001a8UL //Access:WR   DataWidth:0x1    // Multi Field Register.
+  #define MCM_REG_INT_STS_WR_2_QMREG_MORE4                                                                   (0x1<<0) // More than 4 QM registrations.
+  #define MCM_REG_INT_STS_WR_2_QMREG_MORE4_SHIFT                                                             0
+#define MCM_REG_INT_STS_CLR_2                                                                                0x12001acUL //Access:RC   DataWidth:0x1    // Multi Field Register.
+  #define MCM_REG_INT_STS_CLR_2_QMREG_MORE4                                                                  (0x1<<0) // More than 4 QM registrations.
+  #define MCM_REG_INT_STS_CLR_2_QMREG_MORE4_SHIFT                                                            0
+#define MCM_REG_PRTY_MASK_H_0_BB_K2                                                                          0x1200204UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define MCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_RF_INT_BB_K2                                                    (0x1<<0) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM028_I_ECC_RF_INT .
+  #define MCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_RF_INT_BB_K2_SHIFT                                              0
+  #define MCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_BB_K2                                                    (0x1<<1) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
+  #define MCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_BB_K2_SHIFT                                              1
+  #define MCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_0_RF_INT_BB_K2                                                  (0x1<<2) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM023_I_ECC_0_RF_INT .
+  #define MCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_0_RF_INT_BB_K2_SHIFT                                            2
+  #define MCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_1_RF_INT_BB_K2                                                  (0x1<<3) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM023_I_ECC_1_RF_INT .
+  #define MCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_1_RF_INT_BB_K2_SHIFT                                            3
+  #define MCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_BB_K2                                                  (0x1<<4) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
+  #define MCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_BB_K2_SHIFT                                            4
+  #define MCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_K2                                                  (0x1<<5) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
+  #define MCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_K2_SHIFT                                            5
+  #define MCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_0_RF_INT_BB_K2                                                  (0x1<<6) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM025_I_ECC_0_RF_INT .
+  #define MCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_0_RF_INT_BB_K2_SHIFT                                            6
+  #define MCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_1_RF_INT_BB_K2                                                  (0x1<<7) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM025_I_ECC_1_RF_INT .
+  #define MCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_1_RF_INT_BB_K2_SHIFT                                            7
+  #define MCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_BB_K2                                                    (0x1<<8) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM026_I_ECC_RF_INT .
+  #define MCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_BB_K2_SHIFT                                              8
+  #define MCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_K2                                                      (0x1<<9) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
+  #define MCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_K2_SHIFT                                                9
+  #define MCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_K2                                                      (0x1<<10) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
+  #define MCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_K2_SHIFT                                                10
+  #define MCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_K2                                                      (0x1<<11) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
+  #define MCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_K2_SHIFT                                                11
+  #define MCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_K2                                                      (0x1<<12) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
+  #define MCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_K2_SHIFT                                                12
+  #define MCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_K2                                                      (0x1<<13) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
+  #define MCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_K2_SHIFT                                                13
+  #define MCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB_K2                                                      (0x1<<14) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
+  #define MCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB_K2_SHIFT                                                14
+  #define MCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_K2                                                      (0x1<<15) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
+  #define MCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_K2_SHIFT                                                15
+  #define MCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_K2                                                      (0x1<<16) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
+  #define MCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_K2_SHIFT                                                16
+  #define MCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_K2                                                      (0x1<<17) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
+  #define MCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_K2_SHIFT                                                17
+  #define MCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_K2                                                      (0x1<<18) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
+  #define MCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_K2_SHIFT                                                18
+  #define MCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_K2                                                      (0x1<<19) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
+  #define MCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_K2_SHIFT                                                19
+  #define MCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_K2                                                      (0x1<<20) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
+  #define MCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_K2_SHIFT                                                20
+  #define MCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_K2                                                      (0x1<<21) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
+  #define MCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_K2_SHIFT                                                21
+  #define MCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_K2                                                      (0x1<<22) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
+  #define MCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_K2_SHIFT                                                22
+  #define MCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                      (0x1<<23) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define MCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                                23
+  #define MCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB_K2                                                      (0x1<<24) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
+  #define MCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB_K2_SHIFT                                                24
+  #define MCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2                                                      (0x1<<25) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define MCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2_SHIFT                                                25
+  #define MCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_K2                                                      (0x1<<26) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
+  #define MCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_K2_SHIFT                                                26
+  #define MCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_K2                                                      (0x1<<27) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
+  #define MCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_K2_SHIFT                                                27
+  #define MCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_BB_K2                                                    (0x1<<28) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_0 .
+  #define MCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_BB_K2_SHIFT                                              28
+  #define MCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_BB_K2                                                    (0x1<<29) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_1 .
+  #define MCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_BB_K2_SHIFT                                              29
+  #define MCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2                                                      (0x1<<30) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
+  #define MCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2_SHIFT                                                30
+#define MCM_REG_PRTY_MASK_H_1_BB_K2                                                                          0x1200214UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define MCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_BB_K2                                                      (0x1<<0) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY .
+  #define MCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_BB_K2_SHIFT                                                0
+  #define MCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB_K2                                                      (0x1<<1) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
+  #define MCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB_K2_SHIFT                                                1
+  #define MCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_K2                                                      (0x1<<2) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
+  #define MCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                                2
+  #define MCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_K2                                                      (0x1<<3) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
+  #define MCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                                3
+#define MCM_REG_MEM023_RF_ECC_ERROR_CONNECT_0_BB_K2                                                          0x1200220UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: mcm.i_sm_con_ctx.rf_ecc_error_connect_0 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define MCM_REG_MEM023_RF_ECC_ERROR_CONNECT_1_BB_K2                                                          0x1200224UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: mcm.i_sm_con_ctx.rf_ecc_error_connect_1 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define MCM_REG_MEM_ECC_ENABLE_0_BB_K2                                                                       0x1200228UL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define MCM_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_EN_BB_K2                                                     (0x1<<0) // Enable ECC for memory ecc instance mcm.i_xx_msg_ram.i_ecc in module mcm_mem_xx_msg_ram
+  #define MCM_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_EN_BB_K2_SHIFT                                               0
+  #define MCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_BB_K2                                                     (0x1<<1) // Enable ECC for memory ecc instance mcm.i_agg_con_ctx.i_ecc in module mcm_mem_agg_con_ctx
+  #define MCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_BB_K2_SHIFT                                               1
+  #define MCM_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_0_EN_BB_K2                                                   (0x1<<2) // Enable ECC for memory ecc instance mcm.i_sm_con_ctx.i_ecc_0 in module mcm_mem_sm_con_ctx
+  #define MCM_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_0_EN_BB_K2_SHIFT                                             2
+  #define MCM_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_1_EN_BB_K2                                                   (0x1<<3) // Enable ECC for memory ecc instance mcm.i_sm_con_ctx.i_ecc_1 in module mcm_mem_sm_con_ctx
+  #define MCM_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_1_EN_BB_K2_SHIFT                                             3
+  #define MCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN_BB_K2                                                   (0x1<<4) // Enable ECC for memory ecc instance mcm.i_agg_task_ctx.i_ecc_0 in module mcm_mem_agg_task_ctx
+  #define MCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN_BB_K2_SHIFT                                             4
+  #define MCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_BB_K2                                                   (0x1<<5) // Enable ECC for memory ecc instance mcm.i_agg_task_ctx.i_ecc_1 in module mcm_mem_agg_task_ctx
+  #define MCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_BB_K2_SHIFT                                             5
+  #define MCM_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_0_EN_BB_K2                                                   (0x1<<6) // Enable ECC for memory ecc instance mcm.i_sm_task_ctx_0_5.i_ecc_0 in module mcm_mem_sm_task_ctx_0_5
+  #define MCM_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_0_EN_BB_K2_SHIFT                                             6
+  #define MCM_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_1_EN_BB_K2                                                   (0x1<<7) // Enable ECC for memory ecc instance mcm.i_sm_task_ctx_0_5.i_ecc_1 in module mcm_mem_sm_task_ctx_0_5
+  #define MCM_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_1_EN_BB_K2_SHIFT                                             7
+  #define MCM_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_EN_BB_K2                                                     (0x1<<8) // Enable ECC for memory ecc instance mcm.i_sm_task_ctx_6.i_ecc in module mcm_mem_sm_task_ctx_6
+  #define MCM_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_EN_BB_K2_SHIFT                                               8
+#define MCM_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                  0x120022cUL //Access:RW   DataWidth:0x9    // Multi Field Register.
+  #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_PRTY_BB_K2                                              (0x1<<0) // Set parity only for memory ecc instance mcm.i_xx_msg_ram.i_ecc in module mcm_mem_xx_msg_ram
+  #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_PRTY_BB_K2_SHIFT                                        0
+  #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_BB_K2                                              (0x1<<1) // Set parity only for memory ecc instance mcm.i_agg_con_ctx.i_ecc in module mcm_mem_agg_con_ctx
+  #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_BB_K2_SHIFT                                        1
+  #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_0_PRTY_BB_K2                                            (0x1<<2) // Set parity only for memory ecc instance mcm.i_sm_con_ctx.i_ecc_0 in module mcm_mem_sm_con_ctx
+  #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_0_PRTY_BB_K2_SHIFT                                      2
+  #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_1_PRTY_BB_K2                                            (0x1<<3) // Set parity only for memory ecc instance mcm.i_sm_con_ctx.i_ecc_1 in module mcm_mem_sm_con_ctx
+  #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_1_PRTY_BB_K2_SHIFT                                      3
+  #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY_BB_K2                                            (0x1<<4) // Set parity only for memory ecc instance mcm.i_agg_task_ctx.i_ecc_0 in module mcm_mem_agg_task_ctx
+  #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY_BB_K2_SHIFT                                      4
+  #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_BB_K2                                            (0x1<<5) // Set parity only for memory ecc instance mcm.i_agg_task_ctx.i_ecc_1 in module mcm_mem_agg_task_ctx
+  #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_BB_K2_SHIFT                                      5
+  #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_0_PRTY_BB_K2                                            (0x1<<6) // Set parity only for memory ecc instance mcm.i_sm_task_ctx_0_5.i_ecc_0 in module mcm_mem_sm_task_ctx_0_5
+  #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_0_PRTY_BB_K2_SHIFT                                      6
+  #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_1_PRTY_BB_K2                                            (0x1<<7) // Set parity only for memory ecc instance mcm.i_sm_task_ctx_0_5.i_ecc_1 in module mcm_mem_sm_task_ctx_0_5
+  #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_1_PRTY_BB_K2_SHIFT                                      7
+  #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_PRTY_BB_K2                                              (0x1<<8) // Set parity only for memory ecc instance mcm.i_sm_task_ctx_6.i_ecc in module mcm_mem_sm_task_ctx_6
+  #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_PRTY_BB_K2_SHIFT                                        8
+#define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                              0x1200230UL //Access:RC   DataWidth:0x9    // Multi Field Register.
+  #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_CORRECT_BB_K2                                       (0x1<<0) // Record if a correctable error occurred on memory ecc instance mcm.i_xx_msg_ram.i_ecc in module mcm_mem_xx_msg_ram
+  #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_CORRECT_BB_K2_SHIFT                                 0
+  #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_BB_K2                                       (0x1<<1) // Record if a correctable error occurred on memory ecc instance mcm.i_agg_con_ctx.i_ecc in module mcm_mem_agg_con_ctx
+  #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_BB_K2_SHIFT                                 1
+  #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_0_CORRECT_BB_K2                                     (0x1<<2) // Record if a correctable error occurred on memory ecc instance mcm.i_sm_con_ctx.i_ecc_0 in module mcm_mem_sm_con_ctx
+  #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_0_CORRECT_BB_K2_SHIFT                               2
+  #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_1_CORRECT_BB_K2                                     (0x1<<3) // Record if a correctable error occurred on memory ecc instance mcm.i_sm_con_ctx.i_ecc_1 in module mcm_mem_sm_con_ctx
+  #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_1_CORRECT_BB_K2_SHIFT                               3
+  #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT_BB_K2                                     (0x1<<4) // Record if a correctable error occurred on memory ecc instance mcm.i_agg_task_ctx.i_ecc_0 in module mcm_mem_agg_task_ctx
+  #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT_BB_K2_SHIFT                               4
+  #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_BB_K2                                     (0x1<<5) // Record if a correctable error occurred on memory ecc instance mcm.i_agg_task_ctx.i_ecc_1 in module mcm_mem_agg_task_ctx
+  #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_BB_K2_SHIFT                               5
+  #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_0_CORRECT_BB_K2                                     (0x1<<6) // Record if a correctable error occurred on memory ecc instance mcm.i_sm_task_ctx_0_5.i_ecc_0 in module mcm_mem_sm_task_ctx_0_5
+  #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_0_CORRECT_BB_K2_SHIFT                               6
+  #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_1_CORRECT_BB_K2                                     (0x1<<7) // Record if a correctable error occurred on memory ecc instance mcm.i_sm_task_ctx_0_5.i_ecc_1 in module mcm_mem_sm_task_ctx_0_5
+  #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_1_CORRECT_BB_K2_SHIFT                               7
+  #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM026_I_ECC_CORRECT_BB_K2                                       (0x1<<8) // Record if a correctable error occurred on memory ecc instance mcm.i_sm_task_ctx_6.i_ecc in module mcm_mem_sm_task_ctx_6
+  #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM026_I_ECC_CORRECT_BB_K2_SHIFT                                 8
+#define MCM_REG_MEM_ECC_EVENTS_BB_K2                                                                         0x1200234UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define MCM_REG_IFEN                                                                                         0x1200400UL //Access:RW   DataWidth:0x1    // Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
+#define MCM_REG_QM_TASK_BASE_EVNT_ID_0                                                                       0x1200424UL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define MCM_REG_QM_TASK_BASE_EVNT_ID_1                                                                       0x1200428UL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define MCM_REG_QM_TASK_BASE_EVNT_ID_2                                                                       0x120042cUL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define MCM_REG_QM_TASK_BASE_EVNT_ID_3                                                                       0x1200430UL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define MCM_REG_QM_TASK_BASE_EVNT_ID_4                                                                       0x1200434UL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define MCM_REG_QM_TASK_BASE_EVNT_ID_5                                                                       0x1200438UL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define MCM_REG_QM_TASK_BASE_EVNT_ID_6                                                                       0x120043cUL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define MCM_REG_QM_TASK_BASE_EVNT_ID_7                                                                       0x1200440UL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define MCM_REG_QM_AGG_TASK_CTX_PART_SIZE_0                                                                  0x1200484UL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define MCM_REG_QM_AGG_TASK_CTX_PART_SIZE_1                                                                  0x1200488UL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define MCM_REG_QM_AGG_TASK_CTX_PART_SIZE_2                                                                  0x120048cUL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define MCM_REG_QM_AGG_TASK_CTX_PART_SIZE_3                                                                  0x1200490UL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define MCM_REG_QM_AGG_TASK_CTX_PART_SIZE_4                                                                  0x1200494UL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define MCM_REG_QM_AGG_TASK_CTX_PART_SIZE_5                                                                  0x1200498UL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define MCM_REG_QM_AGG_TASK_CTX_PART_SIZE_6                                                                  0x120049cUL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define MCM_REG_QM_AGG_TASK_CTX_PART_SIZE_7                                                                  0x12004a0UL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define MCM_REG_QM_SM_TASK_CTX_LDST_FLG_0                                                                    0x12004a4UL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define MCM_REG_QM_SM_TASK_CTX_LDST_FLG_1                                                                    0x12004a8UL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define MCM_REG_QM_SM_TASK_CTX_LDST_FLG_2                                                                    0x12004acUL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define MCM_REG_QM_SM_TASK_CTX_LDST_FLG_3                                                                    0x12004b0UL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define MCM_REG_QM_SM_TASK_CTX_LDST_FLG_4                                                                    0x12004b4UL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define MCM_REG_QM_SM_TASK_CTX_LDST_FLG_5                                                                    0x12004b8UL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define MCM_REG_QM_SM_TASK_CTX_LDST_FLG_6                                                                    0x12004bcUL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define MCM_REG_QM_SM_TASK_CTX_LDST_FLG_7                                                                    0x12004c0UL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define MCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_0                                                                    0x12004c4UL //Access:RW   DataWidth:0x4    // TCFC Lock UC Update value per task type.
+#define MCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_1                                                                    0x12004c8UL //Access:RW   DataWidth:0x4    // TCFC Lock UC Update value per task type.
+#define MCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_2                                                                    0x12004ccUL //Access:RW   DataWidth:0x4    // TCFC Lock UC Update value per task type.
+#define MCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_3                                                                    0x12004d0UL //Access:RW   DataWidth:0x4    // TCFC Lock UC Update value per task type.
+#define MCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_4                                                                    0x12004d4UL //Access:RW   DataWidth:0x4    // TCFC Lock UC Update value per task type.
+#define MCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_5                                                                    0x12004d8UL //Access:RW   DataWidth:0x4    // TCFC Lock UC Update value per task type.
+#define MCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_6                                                                    0x12004dcUL //Access:RW   DataWidth:0x4    // TCFC Lock UC Update value per task type.
+#define MCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_7                                                                    0x12004e0UL //Access:RW   DataWidth:0x4    // TCFC Lock UC Update value per task type.
+#define MCM_REG_QM_TCFC_XXLOCK_CMD_0                                                                         0x12004e4UL //Access:RW   DataWidth:0x3    // TCFC Lock UC xxLock command per task type.
+#define MCM_REG_QM_TCFC_XXLOCK_CMD_1                                                                         0x12004e8UL //Access:RW   DataWidth:0x3    // TCFC Lock UC xxLock command per task type.
+#define MCM_REG_QM_TCFC_XXLOCK_CMD_2                                                                         0x12004ecUL //Access:RW   DataWidth:0x3    // TCFC Lock UC xxLock command per task type.
+#define MCM_REG_QM_TCFC_XXLOCK_CMD_3                                                                         0x12004f0UL //Access:RW   DataWidth:0x3    // TCFC Lock UC xxLock command per task type.
+#define MCM_REG_QM_TCFC_XXLOCK_CMD_4                                                                         0x12004f4UL //Access:RW   DataWidth:0x3    // TCFC Lock UC xxLock command per task type.
+#define MCM_REG_QM_TCFC_XXLOCK_CMD_5                                                                         0x12004f8UL //Access:RW   DataWidth:0x3    // TCFC Lock UC xxLock command per task type.
+#define MCM_REG_QM_TCFC_XXLOCK_CMD_6                                                                         0x12004fcUL //Access:RW   DataWidth:0x3    // TCFC Lock UC xxLock command per task type.
+#define MCM_REG_QM_TCFC_XXLOCK_CMD_7                                                                         0x1200500UL //Access:RW   DataWidth:0x3    // TCFC Lock UC xxLock command per task type.
+#define MCM_REG_QM_TASK_USE_ST_FLG_0                                                                         0x1200544UL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define MCM_REG_QM_TASK_USE_ST_FLG_1                                                                         0x1200548UL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define MCM_REG_QM_TASK_USE_ST_FLG_2                                                                         0x120054cUL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define MCM_REG_QM_TASK_USE_ST_FLG_3                                                                         0x1200550UL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define MCM_REG_QM_TASK_USE_ST_FLG_4                                                                         0x1200554UL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define MCM_REG_QM_TASK_USE_ST_FLG_5                                                                         0x1200558UL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define MCM_REG_QM_TASK_USE_ST_FLG_6                                                                         0x120055cUL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define MCM_REG_QM_TASK_USE_ST_FLG_7                                                                         0x1200560UL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM.
+#define MCM_REG_ERR_EVNT_ID                                                                                  0x1200564UL //Access:RW   DataWidth:0x8    // The Event ID in case one of errors is set in QM input message.
+#define MCM_REG_AGG_CON_RULE0_Q_BB_K2                                                                        0x1200920UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define MCM_REG_AGG_CON_RULE0_Q_E5                                                                           0x1200568UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define MCM_REG_AGG_CON_RULE1_Q_BB_K2                                                                        0x1200924UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define MCM_REG_AGG_CON_RULE1_Q_E5                                                                           0x120056cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define MCM_REG_AGG_CON_RULE2_Q_BB_K2                                                                        0x1200928UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define MCM_REG_AGG_CON_RULE2_Q_E5                                                                           0x1200570UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define MCM_REG_AGG_CON_RULE3_Q_BB_K2                                                                        0x120092cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define MCM_REG_AGG_CON_RULE3_Q_E5                                                                           0x1200574UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define MCM_REG_AGG_CON_RULE4_Q_BB_K2                                                                        0x1200930UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define MCM_REG_AGG_CON_RULE4_Q_E5                                                                           0x1200578UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define MCM_REG_STORM_WEIGHT                                                                                 0x1200604UL //Access:RW   DataWidth:0x3    // The weight of the local Storm input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define MCM_REG_USEM_WEIGHT                                                                                  0x1200608UL //Access:RW   DataWidth:0x3    // The weight of the input Usem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define MCM_REG_PBF_WEIGHT                                                                                   0x1200610UL //Access:RW   DataWidth:0x3    // The weight of the input Pbf in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define MCM_REG_GRC_WEIGHT                                                                                   0x1200614UL //Access:RW   DataWidth:0x3    // The weight of the GRC input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define MCM_REG_YSDM_WEIGHT                                                                                  0x120061cUL //Access:RW   DataWidth:0x3    // The weight of the YSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define MCM_REG_USDM_WEIGHT                                                                                  0x1200620UL //Access:RW   DataWidth:0x3    // The weight of the input USDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define MCM_REG_TMLD_WEIGHT                                                                                  0x1200624UL //Access:RW   DataWidth:0x3    // The weight of the input TMLD in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define MCM_REG_QM_P_WEIGHT                                                                                  0x1200628UL //Access:RW   DataWidth:0x3    // The weight of the QM (primary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define MCM_REG_QM_S_WEIGHT                                                                                  0x120062cUL //Access:RW   DataWidth:0x3    // The weight of the QM (secondary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define MCM_REG_IA_GROUP_PR0                                                                                 0x1200630UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: ia_group_pr0 is the highest priority; ia_group_pr5 is the lowest priority.
+#define MCM_REG_IA_GROUP_PR1                                                                                 0x1200634UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define MCM_REG_IA_GROUP_PR2                                                                                 0x1200638UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define MCM_REG_IA_GROUP_PR3                                                                                 0x120063cUL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define MCM_REG_IA_GROUP_PR4                                                                                 0x1200640UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define MCM_REG_IA_GROUP_PR5                                                                                 0x1200644UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define MCM_REG_IA_ARB_SP_TIMEOUT                                                                            0x1200648UL //Access:RW   DataWidth:0x8    // Input Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8'h0 - constant RR; 8'h80 - constant strict priority. In all other cases the following is true: Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance.
+#define MCM_REG_STORM_FRWRD_MODE                                                                             0x120064cUL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define MCM_REG_YSDM_FRWRD_MODE                                                                              0x1200654UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define MCM_REG_USDM_FRWRD_MODE                                                                              0x1200658UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define MCM_REG_TMLD_FRWRD_MODE                                                                              0x120065cUL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define MCM_REG_USEM_FRWRD_MODE                                                                              0x1200660UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define MCM_REG_PBF_FRWRD_MODE                                                                               0x1200668UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define MCM_REG_SDM_ERR_HANDLE_EN                                                                            0x120066cUL //Access:RW   DataWidth:0x1    // 0 - disable error handling in SDM message; 1 - enable error handling in SDM message.
+#define MCM_REG_DIR_BYP_EN                                                                                   0x1200670UL //Access:RW   DataWidth:0x1    // Direct bypass enable.
+#define MCM_REG_FI_DESC_INPUT_VIOLATE                                                                        0x1200674UL //Access:R    DataWidth:0xf    // Input message first descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0  then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL  then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation:  Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation:  TaskExist==0 -> XxLockCmd != XX_UNLOCK_CID_TID and XxLockCmd != XX_LOCK_CID_TID_BYPASS;  [12] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0;[13] - Violation: Agg message: Loader done with error then SmCtxLdStFlg==0; [14] - Violation: XxBypass message in PCM block;
+#define MCM_REG_SE_DESC_INPUT_VIOLATE                                                                        0x1200678UL //Access:R    DataWidth:0xc    // Input message second descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0  then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL  then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation:  Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0; Read only register.
+#define MCM_REG_IA_AGG_CON_PART_FILL_LVL                                                                     0x120067cUL //Access:R    DataWidth:0x3    // Input Arbiter Aggregation Connection part FIFO fill level (in messages).
+#define MCM_REG_IA_SM_CON_PART_FILL_LVL                                                                      0x1200680UL //Access:R    DataWidth:0x3    // Input Arbiter Storm Connection part FIFO fill level (in messages).
+#define MCM_REG_IA_AGG_TASK_PART_FILL_LVL                                                                    0x1200684UL //Access:R    DataWidth:0x3    // Input Arbiter Aggregation Task part FIFO fill level (in messages).
+#define MCM_REG_IA_SM_TASK_PART_FILL_LVL                                                                     0x1200688UL //Access:R    DataWidth:0x3    // Input Arbiter Storm Task part FIFO fill level (in messages).
+#define MCM_REG_IA_TRANS_PART_FILL_LVL                                                                       0x120068cUL //Access:R    DataWidth:0x3    // Input Arbiter Transparent part FIFO fill level (in messages).
+#define MCM_REG_EXT_RD_FILL_LVL_E5                                                                           0x1200690UL //Access:R    DataWidth:0x2    // External read buffer FIFO fill level (in FIFO entries).
+#define MCM_REG_XX_MSG_UP_BND                                                                                0x1200704UL //Access:RW   DataWidth:0x7    // The maximum number of Xx RAM messages; which may be stored in XX protection. Is restricted by Xx Messages RAM size and the size of Xx protected message CM_REGISTERS_XX_MSG_SIZE.XX_MSG_SIZE
+#define MCM_REG_XX_MSG_SIZE                                                                                  0x1200708UL //Access:RW   DataWidth:0x5    // The size of Xx protected message in Xx Messages RAM in QREGs. Upper rounded to 4 and multiplied by CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND should not exceed XxMessagesRam size which is: MCM: 0d1792 PCM: 0d176 TCM: 0d1536 UCM: 0d1792 XCM: 0d256 YCM: 0d1536
+#define MCM_REG_XX_LCID_CAM_UP_BND                                                                           0x120070cUL //Access:RW   DataWidth:0x7    // The maximum number of connections in the XX protection LCID CAM.
+#define MCM_REG_XX_FREE_CNT                                                                                  0x1200710UL //Access:R    DataWidth:0x7    // Used to read the XX protection Free counter. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND
+#define MCM_REG_XX_LCID_CAM_FILL_LVL                                                                         0x1200714UL //Access:R    DataWidth:0x7    // Used to read XX protection LCID CAM fill level. Fill level is calculated as the number of locked LCIDs, i.e. LCIDs that have at least one Xx locked message or LCIDs that have no Xx locked messages but haven't been unlocked yet from LCID CAM. Simple saying it calculates for number of valid entries in LCID CAM.
+#define MCM_REG_XX_LCID_CAM_ST_STAT                                                                          0x1200718UL //Access:RC   DataWidth:0x7    // CAM occupancy sticky status. The write to the register is performed by the XX internal circuitry.
+#define MCM_REG_XX_IA_GROUP_PR0                                                                              0x120071cUL //Access:RW   DataWidth:0x1    // Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
+#define MCM_REG_XX_IA_GROUP_PR1                                                                              0x1200720UL //Access:RW   DataWidth:0x1    // Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
+#define MCM_REG_XX_NON_LOCK_LCID_THR                                                                         0x1200724UL //Access:RW   DataWidth:0x7    // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decision of Xx Input Arbiter non-locked group.
+#define MCM_REG_XX_LOCK_LCID_THR                                                                             0x1200728UL //Access:RW   DataWidth:0x7    // Xx locked LCIDs threshold (maximum value). Participates in Xx Bypass global enable decision.
+#define MCM_REG_XX_IA_ARB_SP_TIMEOUT                                                                         0x120072cUL //Access:RW   DataWidth:0x8    // Xx Input Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. E.g. bits[6:0]=0; bit[7]=0 - always strict priority; bits[6:0]=1; bit[7]=0 - strict priority; then RR; bits[6:0]=3; bit[7]=0 - 3 times strict priority; then RR.
+#define MCM_REG_XX_FREE_HEAD_PTR                                                                             0x1200730UL //Access:R    DataWidth:0x6    // Xx Free Head Pointer.
+#define MCM_REG_XX_FREE_TAIL_PTR                                                                             0x1200734UL //Access:R    DataWidth:0x6    // Xx Free Tail Pointer. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND
+#define MCM_REG_XX_NON_LOCK_CNT                                                                              0x1200738UL //Access:R    DataWidth:0x7    // Xx NonLock Counter.
+#define MCM_REG_XX_LOCK_CNT                                                                                  0x120073cUL //Access:R    DataWidth:0x7    // Xx Lock Counter.
+#define MCM_REG_XX_LCID_ARB_GROUP_PR0                                                                        0x1200740UL //Access:RW   DataWidth:0x2    // Xx LCID Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.
+#define MCM_REG_XX_LCID_ARB_GROUP_PR1                                                                        0x1200744UL //Access:RW   DataWidth:0x2    // Xx LCID Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.
+#define MCM_REG_XX_LCID_ARB_GROUP_PR2                                                                        0x1200748UL //Access:RW   DataWidth:0x2    // Xx LCID Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.
+#define MCM_REG_XX_LCID_ARB_SP_TIMEOUT                                                                       0x120074cUL //Access:RW   DataWidth:0x8    // Xx LCID Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. E.g. bits[6:0]=0; bit[7]=0 - always strict priority; bits[6:0]=1; bit[7]=0 - strict priority; then RR; bits[6:0]=3; bit[7]=0 - 3 times strict priority; then RR.
+#define MCM_REG_XX_FREE_THR_HIGH                                                                             0x1200750UL //Access:RW   DataWidth:0x7    // Xx free messages threshold high. Used in Xx Bypass global enable condition.
+#define MCM_REG_XX_FREE_THR_LOW                                                                              0x1200754UL //Access:RW   DataWidth:0x7    // Xx free messages threshold low Used in Xx Bypass global enable condition.
+#define MCM_REG_XX_CBYP_TBL_FILL_LVL                                                                         0x1200758UL //Access:R    DataWidth:0x4    // Xx Connection Bypass Table fill level (in connections).
+#define MCM_REG_XX_CBYP_TBL_ST_STAT                                                                          0x120075cUL //Access:RC   DataWidth:0x4    // Xx Connection Bypass Table sticky status. Reset on read.
+#define MCM_REG_XX_CBYP_TBL_UP_BND                                                                           0x1200760UL //Access:RW   DataWidth:0x4    // Xx Bypass Table (Connection) maximum fill level.
+#define MCM_REG_XX_TBYP_TBL_FILL_LVL                                                                         0x1200764UL //Access:R    DataWidth:0x7    // Xx Task Bypass Table fill level (in tasks).
+#define MCM_REG_XX_TBYP_TBL_ST_STAT                                                                          0x1200768UL //Access:RC   DataWidth:0x7    // Xx Task Bypass Table sticky status. Reset on read.
+#define MCM_REG_XX_TBYP_TBL_UP_BND                                                                           0x120076cUL //Access:RW   DataWidth:0x7    // Xx Bypass Table (Task) maximum fill level.
+#define MCM_REG_XX_BYP_LOCK_MSG_THR                                                                          0x1200790UL //Access:RW   DataWidth:0x6    // Xx Bypass messages lock threshold. The number of locked messages per LCID is above this threshold is one of conditions to start XxBypass for this LCID.
+#define MCM_REG_XX_PREF_DIR_FILL_LVL                                                                         0x1200794UL //Access:R    DataWidth:0x5    // Xx LCID Arbiter direct prefetch FIFO fill level (in entries).
+#define MCM_REG_XX_PREF_AGGST_FILL_LVL                                                                       0x1200798UL //Access:R    DataWidth:0x5    // Xx LCID Arbiter aggregation store prefetch FIFO fill level (in entries).
+#define MCM_REG_XX_PREF_BYP_FILL_LVL                                                                         0x120079cUL //Access:R    DataWidth:0x5    // Xx LCID Arbiter bypass prefetch FIFO fill level (in entries).
+#define MCM_REG_UNLOCK_MISS                                                                                  0x12007a0UL //Access:RC   DataWidth:0x1    // Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM.
+#define MCM_REG_ERR_AFFINITY_TYPE_E5                                                                         0x12007a4UL //Access:RW   DataWidth:0x2    // Affinity type in case of input message error.
+#define MCM_REG_ERR_EXCLUSIVE_FLG_E5                                                                         0x12007a8UL //Access:RW   DataWidth:0x1    // Exclusive type in case of input message error.
+#define MCM_REG_ERR_SRC_AFFINITY_E5                                                                          0x12007acUL //Access:RW   DataWidth:0x3    // Source affinity in case of input message error.
+#define MCM_REG_XX_BYP_MSG_UP_BND_0_BB_K2                                                                    0x1200770UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define MCM_REG_XX_BYP_MSG_UP_BND_0_E5                                                                       0x12007b0UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define MCM_REG_XX_BYP_MSG_UP_BND_1_BB_K2                                                                    0x1200774UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define MCM_REG_XX_BYP_MSG_UP_BND_1_E5                                                                       0x12007b4UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define MCM_REG_XX_BYP_MSG_UP_BND_2_BB_K2                                                                    0x1200778UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define MCM_REG_XX_BYP_MSG_UP_BND_2_E5                                                                       0x12007b8UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define MCM_REG_XX_BYP_MSG_UP_BND_3_BB_K2                                                                    0x120077cUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define MCM_REG_XX_BYP_MSG_UP_BND_3_E5                                                                       0x12007bcUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define MCM_REG_XX_BYP_MSG_UP_BND_4_BB_K2                                                                    0x1200780UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define MCM_REG_XX_BYP_MSG_UP_BND_4_E5                                                                       0x12007c0UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define MCM_REG_XX_BYP_MSG_UP_BND_5_BB_K2                                                                    0x1200784UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define MCM_REG_XX_BYP_MSG_UP_BND_5_E5                                                                       0x12007c4UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define MCM_REG_XX_BYP_MSG_UP_BND_6_BB_K2                                                                    0x1200788UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define MCM_REG_XX_BYP_MSG_UP_BND_6_E5                                                                       0x12007c8UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define MCM_REG_XX_BYP_MSG_UP_BND_7_BB_K2                                                                    0x120078cUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define MCM_REG_XX_BYP_MSG_UP_BND_7_E5                                                                       0x12007ccUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define MCM_REG_XX_BYP_MSG_UP_BND_8_E5                                                                       0x12007d0UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define MCM_REG_XX_BYP_MSG_UP_BND_9_E5                                                                       0x12007d4UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define MCM_REG_XX_BYP_MSG_UP_BND_10_E5                                                                      0x12007d8UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define MCM_REG_XX_BYP_MSG_UP_BND_11_E5                                                                      0x12007dcUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define MCM_REG_XX_BYP_MSG_UP_BND_12_E5                                                                      0x12007e0UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define MCM_REG_XX_BYP_MSG_UP_BND_13_E5                                                                      0x12007e4UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define MCM_REG_XX_BYP_MSG_UP_BND_14_E5                                                                      0x12007e8UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define MCM_REG_XX_BYP_MSG_UP_BND_15_E5                                                                      0x12007ecUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define MCM_REG_PRCS_AGG_CON_CURR_ST                                                                         0x1200804UL //Access:R    DataWidth:0x4    // Aggregation Connection Processor FSM.
+#define MCM_REG_PRCS_SM_CON_CURR_ST                                                                          0x1200808UL //Access:R    DataWidth:0x2    // STORM Connection Processor FSM.
+#define MCM_REG_PRCS_AGG_TASK_CURR_ST                                                                        0x120080cUL //Access:R    DataWidth:0x4    // Aggregation Task Processor FSM.
+#define MCM_REG_PRCS_SM_TASK_CURR_ST                                                                         0x1200810UL //Access:R    DataWidth:0x2    // STORM Task Processor FSM.
+#define MCM_REG_N_SM_TASK_CTX_LD_0                                                                           0x1200834UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define MCM_REG_N_SM_TASK_CTX_LD_1                                                                           0x1200838UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define MCM_REG_N_SM_TASK_CTX_LD_2                                                                           0x120083cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define MCM_REG_N_SM_TASK_CTX_LD_3                                                                           0x1200840UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define MCM_REG_N_SM_TASK_CTX_LD_4                                                                           0x1200844UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define MCM_REG_N_SM_TASK_CTX_LD_5                                                                           0x1200848UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define MCM_REG_N_SM_TASK_CTX_LD_6                                                                           0x120084cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define MCM_REG_N_SM_TASK_CTX_LD_7                                                                           0x1200850UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define MCM_REG_AGG_CON_FIC_BUF_FILL_LVL                                                                     0x1200854UL //Access:R    DataWidth:0x1    // Aggregation Connection FIC buffer fill level (in messages).
+#define MCM_REG_SM_CON_FIC_BUF_FILL_LVL                                                                      0x1200858UL //Access:R    DataWidth:0x5    // Storm Connection FIC buffer fill level (in messages).
+#define MCM_REG_AGG_CON_FIC_BUF_CRD                                                                          0x120085cUL //Access:RW   DataWidth:0x2    // Aggregation Connection FIC buffer credit (in full message out parts).
+#define MCM_REG_SM_CON_FIC_BUF_CRD                                                                           0x1200860UL //Access:RW   DataWidth:0x2    // Storm Connection FIC buffer credit (in full message out parts).
+#define MCM_REG_AGG_CON_BUF_CRD_AGG                                                                          0x1200864UL //Access:RW   DataWidth:0x3    // Aggregation Connection buffer (data or command) credit (Aggregation group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than Agregation Connection data buffer size=4. In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST and CM_REGISTERS_AGG_CON_CMD_BUF_CRD_DIR.AGG_CON_CMD_BUF_CRD_DIR need be no more than Agregation Connection command buffer size=6.
+#define MCM_REG_AGG_CON_BUF_CRD_AGGST                                                                        0x1200868UL //Access:RW   DataWidth:0x3    // Aggregation Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG need be no more than Agregation Connection data buffer size=4. In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG and CM_REGISTERS_AGG_CON_CMD_BUF_CRD_DIR.AGG_CON_CMD_BUF_CRD_DIR need be no more than Agregation Connection command buffer size=6.
+#define MCM_REG_SM_CON_BUF_CRD_AGGST                                                                         0x120086cUL //Access:RW   DataWidth:0x1    // Storm Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_CON_CMD_BUF_CRD_DIR.SM_CON_CMD_BUF_CRD_DIR need be no more than Storm Connection command buffer size=3.
+#define MCM_REG_AGG_CON_CMD_BUF_CRD_DIR                                                                      0x1200870UL //Access:RW   DataWidth:0x2    // Aggregation Connection command buffer credit (Direct group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG and XCM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than Agregation Connection command buffer size=6.
+#define MCM_REG_SM_CON_CMD_BUF_CRD_DIR                                                                       0x1200874UL //Access:RW   DataWidth:0x2    // Storm Connection command buffer credit (Direct group). In sum with CM_REGISTERS_SM_CON_BUF_CRD_AGGST.SM_CON_BUF_CRD_AGGST need be no more than Storm Connection command buffer size=3.
+#define MCM_REG_AGG_TASK_FIC_BUF_FILL_LVL                                                                    0x1200878UL //Access:R    DataWidth:0x2    // Aggregation Task FIC buffer fill level (in messages).
+#define MCM_REG_SM_TASK_FIC_BUF_FILL_LVL                                                                     0x120087cUL //Access:R    DataWidth:0x5    // Storm Task FIC buffer fill level (in messages).
+#define MCM_REG_AGG_TASK_FIC_BUF_CRD                                                                         0x1200880UL //Access:RW   DataWidth:0x2    // Aggregation Task FIC buffer credit (in full message out parts).
+#define MCM_REG_SM_TASK_FIC_BUF_CRD                                                                          0x1200884UL //Access:RW   DataWidth:0x2    // Storm Task FIC buffer credit (in full message out parts).
+#define MCM_REG_AGG_TASK_BUF_CRD_AGG                                                                         0x1200888UL //Access:RW   DataWidth:0x3    // Aggregation Task buffer (data or command) credit (Aggregation group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST need be no more than Agregation Task data buffer size=4. In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST and CM_REGISTERS_AGG_TASK_CMD_BUF_CRD_DIR.AGG_TASK_CMD_BUF_CRD_DIR need be no more than Agregation Task command buffer size=6.
+#define MCM_REG_AGG_TASK_BUF_CRD_AGGST                                                                       0x120088cUL //Access:RW   DataWidth:0x3    // Aggregation Task buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG need be no more than Agregation Task data buffer size=4. In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG and CM_REGISTERS_AGG_TASK_CMD_BUF_CRD_DIR.AGG_TASK_CMD_BUF_CRD_DIR need be no more than Agregation Task command buffer size=6.
+#define MCM_REG_SM_TASK_BUF_CRD_AGGST                                                                        0x1200890UL //Access:RW   DataWidth:0x1    // Storm Task buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_TASK_CMD_BUF_CRD_DIR.SM_TASK_CMD_BUF_CRD_DIR need be no more than Storm Task command buffer size=3.
+#define MCM_REG_AGG_TASK_CMD_BUF_CRD_DIR                                                                     0x1200894UL //Access:RW   DataWidth:0x2    // Aggregation Task command buffer credit (Direct group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG and CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST need be no more than Agregation Task command buffer size=6.
+#define MCM_REG_SM_TASK_CMD_BUF_CRD_DIR                                                                      0x1200898UL //Access:RW   DataWidth:0x2    // Storm Task command buffer credit (Direct group). In sum with CM_REGISTERS_SM_TASK_BUF_CRD_AGGST.SM_TASK_BUF_CRD_AGGST need be no more than Storm Task command buffer size=3.
+#define MCM_REG_TRANS_DATA_BUF_CRD_DIR                                                                       0x120089cUL //Access:RW   DataWidth:0x2    // Transparent data buffer credit (Direct group).
+#define MCM_REG_AGG_TASK_CTX_SIZE_0                                                                          0x12008c0UL //Access:RW   DataWidth:0x2    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define MCM_REG_AGG_TASK_CTX_SIZE_1                                                                          0x12008c4UL //Access:RW   DataWidth:0x2    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define MCM_REG_AGG_TASK_CTX_SIZE_2                                                                          0x12008c8UL //Access:RW   DataWidth:0x2    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define MCM_REG_AGG_TASK_CTX_SIZE_3                                                                          0x12008ccUL //Access:RW   DataWidth:0x2    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define MCM_REG_AGG_TASK_CTX_SIZE_4                                                                          0x12008d0UL //Access:RW   DataWidth:0x2    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define MCM_REG_AGG_TASK_CTX_SIZE_5                                                                          0x12008d4UL //Access:RW   DataWidth:0x2    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define MCM_REG_AGG_TASK_CTX_SIZE_6                                                                          0x12008d8UL //Access:RW   DataWidth:0x2    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define MCM_REG_AGG_TASK_CTX_SIZE_7                                                                          0x12008dcUL //Access:RW   DataWidth:0x2    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define MCM_REG_SM_CON_CTX_SIZE                                                                              0x12008e0UL //Access:RW   DataWidth:0x5    // STORM Connnection context per LCID size (REGQ). Default context size of 10 (REGQ) complies to 320 LCIDs. Maximum context size per LCID is 20. Maximum number of LCIDs allowed at maximum context size per LCID is 160. If not at default value need to be 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER((320*INTEGER(10/2))/(20/2)).
+#define MCM_REG_SM_TASK_CTX_SIZE                                                                             0x12008e4UL //Access:RW   DataWidth:0x5    // STORM Task context per LTID size (REGQ). Default context size of 7 (REGQ) complies to 320 LTIDs. Maximum context size per LTID is 20. Maximum number of LTIDs allowed at maximum context size per LTID is 64. If not at default value need to be 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER((320*INTEGER(7/2))/(20/2)).
+#define MCM_REG_CON_PHY_Q0                                                                                   0x1200904UL //Access:RW   DataWidth:0x9    // Physical queue connection number (queue number 0).
+#define MCM_REG_CON_PHY_Q1                                                                                   0x1200908UL //Access:RW   DataWidth:0x9    // Physical queue connection number (queue number 1).
+#define MCM_REG_TASK_PHY_Q0                                                                                  0x120090cUL //Access:RW   DataWidth:0x7    // Physical queue task number (queue number 0).
+#define MCM_REG_TASK_PHY_Q1                                                                                  0x1200910UL //Access:RW   DataWidth:0x7    // Physical queue task number (queue number 1).
+#define MCM_REG_AGG_TASK_RULE0_Q                                                                             0x1200940UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define MCM_REG_AGG_TASK_RULE1_Q                                                                             0x1200944UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define MCM_REG_AGG_TASK_RULE2_Q                                                                             0x1200948UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define MCM_REG_AGG_TASK_RULE3_Q                                                                             0x120094cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define MCM_REG_AGG_TASK_RULE4_Q                                                                             0x1200950UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define MCM_REG_AGG_TASK_RULE5_Q                                                                             0x1200954UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define MCM_REG_AGG_TASK_RULE6_Q                                                                             0x1200958UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define MCM_REG_AGG_TASK_RULE7_Q_E5                                                                          0x120095cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define MCM_REG_CM_TASK_EVENT_ID_BWIDTH_0_E5                                                                 0x1200960UL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define MCM_REG_CM_TASK_EVENT_ID_BWIDTH_1_E5                                                                 0x1200964UL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define MCM_REG_CM_TASK_EVENT_ID_BWIDTH_2_E5                                                                 0x1200968UL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define MCM_REG_CM_TASK_EVENT_ID_BWIDTH_3_E5                                                                 0x120096cUL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define MCM_REG_CM_TASK_EVENT_ID_BWIDTH_4_E5                                                                 0x1200970UL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define MCM_REG_CM_TASK_EVENT_ID_BWIDTH_5_E5                                                                 0x1200974UL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define MCM_REG_CM_TASK_EVENT_ID_BWIDTH_6_E5                                                                 0x1200978UL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define MCM_REG_CM_TASK_EVENT_ID_BWIDTH_7_E5                                                                 0x120097cUL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define MCM_REG_IN_PRCS_TBL_CRD_AGG                                                                          0x1200a04UL //Access:RW   DataWidth:0x4    // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.IN_PRCS_TBL_CRD_AGGST need be no more than In-process table size=12.
+#define MCM_REG_IN_PRCS_TBL_CRD_AGGST                                                                        0x1200a08UL //Access:RW   DataWidth:0x4    // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGG.IN_PRCS_TBL_CRD_AGG need be no more than In-process table size=12.
+#define MCM_REG_IN_PRCS_TBL_FILL_LVL                                                                         0x1200a0cUL //Access:R    DataWidth:0x4    // In-process Table fill level  (in messages).
+#define MCM_REG_IN_PRCS_TBL_ALMOST_FULL                                                                      0x1200a10UL //Access:R    DataWidth:0x1    // In-process Table almost full.
+#define MCM_REG_QMCON_CURR_ST                                                                                0x1200a14UL //Access:R    DataWidth:0x3    // QM connection registration FSM current state.
+#define MCM_REG_QMTASK_CURR_ST                                                                               0x1200a18UL //Access:R    DataWidth:0x3    // QM task registration FSM current state.
+#define MCM_REG_CCFC_CURR_ST                                                                                 0x1200a1cUL //Access:R    DataWidth:0x1    // CFC connection output FSM current state.
+#define MCM_REG_TCFC_CURR_ST                                                                                 0x1200a20UL //Access:R    DataWidth:0x1    // CFC task output FSM current state.
+#define MCM_REG_CMPL_DIR_CURR_ST                                                                             0x1200a24UL //Access:R    DataWidth:0x4    // Direct Completer FSM current state.
+#define MCM_REG_XX_BYP_CON_STATE_EVNT_ID_FLG                                                                 0x1200a28UL //Access:RW   DataWidth:0x1    // If set, Xx connection bypass state will be added in calculation of CM output Event ID.
+#define MCM_REG_XX_BYP_TASK_STATE_EVNT_ID_FLG                                                                0x1200a2cUL //Access:RW   DataWidth:0x1    // If set, Xx task bypass state will be added in calculation of CM output Event ID.
+#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_0_E5                                                                  0x1200a30UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_1_E5                                                                  0x1200a34UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_2_E5                                                                  0x1200a38UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_3_E5                                                                  0x1200a3cUL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_4_E5                                                                  0x1200a40UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_5_E5                                                                  0x1200a44UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_6_E5                                                                  0x1200a48UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_7_E5                                                                  0x1200a4cUL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_8_E5                                                                  0x1200a50UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_9_E5                                                                  0x1200a54UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_10_E5                                                                 0x1200a58UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_11_E5                                                                 0x1200a5cUL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_12_E5                                                                 0x1200a60UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_13_E5                                                                 0x1200a64UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_14_E5                                                                 0x1200a68UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_15_E5                                                                 0x1200a6cUL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define MCM_REG_CCFC_INIT_CRD                                                                                0x1200a84UL //Access:RW   DataWidth:0x4    // CCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.
+#define MCM_REG_TCFC_INIT_CRD                                                                                0x1200a88UL //Access:RW   DataWidth:0x4    // TCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.
+#define MCM_REG_QM_INIT_CRD0                                                                                 0x1200a8cUL //Access:RW   DataWidth:0x5    // QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 16.Write writes the initial credit value; read returns the current value of the credit counter.
+#define MCM_REG_TCFC_INCLOCK_INIT_CRD                                                                        0x1200a90UL //Access:RW   DataWidth:0x1    // TCFC UC Inc/Lock Update output initial credit. Max credit available - 1.Write writes the initial credit value; read returns the current value of the credit counter.
+#define MCM_REG_TCFC_DEC_INIT_CRD                                                                            0x1200a94UL //Access:RW   DataWidth:0x3    // TCFC UC Dec Update output initial credit. Max credit available - 7.Write writes the initial credit value; read returns the current value of the credit counter.
+#define MCM_REG_FIC_INIT_CRD                                                                                 0x1200a98UL //Access:RW   DataWidth:0x6    // FIC output initial credit. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 44 at start-up.
+#define MCM_REG_DIR_BYP_MSG_CNT                                                                              0x1200aa4UL //Access:RC   DataWidth:0x20   // Counter of direct bypassed messages.
+#define MCM_REG_YSDM_LENGTH_MIS                                                                              0x1200aacUL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at YSDM interface.
+#define MCM_REG_USDM_LENGTH_MIS                                                                              0x1200ab0UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at USDM interface.
+#define MCM_REG_PBF_LENGTH_MIS                                                                               0x1200ab4UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at PBF interface.
+#define MCM_REG_TMLD_LENGTH_MIS                                                                              0x1200ab8UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at TMLD interface.
+#define MCM_REG_GRC_BUF_EMPTY                                                                                0x1200abcUL //Access:R    DataWidth:0x1    // Input Stage GRC buffer is empty.
+#define MCM_REG_GRC_BUF_STATUS                                                                               0x1200ac0UL //Access:R    DataWidth:0x6    // Input Stage GRC buffer status.
+#define MCM_REG_STORM_MSG_CNTR                                                                               0x1200ac4UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the STORM input.
+#define MCM_REG_YSDM_MSG_CNTR                                                                                0x1200accUL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input YSDM.
+#define MCM_REG_USDM_MSG_CNTR                                                                                0x1200ad0UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input USDM.
+#define MCM_REG_TMLD_MSG_CNTR                                                                                0x1200ad4UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input TMLD.
+#define MCM_REG_USEM_MSG_CNTR                                                                                0x1200ad8UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at input USEM.
+#define MCM_REG_PBF_MSG_CNTR                                                                                 0x1200ae0UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at input PBF.
+#define MCM_REG_QM_P_MSG_CNTR                                                                                0x1200ae4UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the QM input (primary).
+#define MCM_REG_QM_S_MSG_CNTR                                                                                0x1200ae8UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the QM input (secondary).
+#define MCM_REG_IS_GRC                                                                                       0x1200aecUL //Access:W    DataWidth:0x20   // Used to write the GRC message. Write only. To distinguish if the register can be accessed to write GRC message                           polling of CM_REGISTERS.GRC_BUF_EMPTY need to be done
+#define MCM_REG_IS_QM_P_FILL_LVL                                                                             0x1200af0UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in QM Primary Input Stage (except of bypass).
+#define MCM_REG_IS_QM_S_FILL_LVL                                                                             0x1200af4UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in QM Secondary Input Stage (except of bypass).
+#define MCM_REG_IS_STORM_FILL_LVL                                                                            0x1200af8UL //Access:R    DataWidth:0x5    // Number of entries (2 QREGs each) of data in STORM Input Stage.
+#define MCM_REG_IS_YSDM_FILL_LVL                                                                             0x1200b00UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in YSDM Input Stage.
+#define MCM_REG_IS_USDM_FILL_LVL                                                                             0x1200b04UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in USDM Input Stage.
+#define MCM_REG_IS_TMLD_FILL_LVL                                                                             0x1200b08UL //Access:R    DataWidth:0x6    // Number of 2 QREGs (256b) of data in TMLD Input Stage.
+#define MCM_REG_IS_USEM_FILL_LVL                                                                             0x1200b0cUL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in USEM Input Stage.
+#define MCM_REG_IS_PBF_FILL_LVL                                                                              0x1200b14UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in PBF Input Stage.
+#define MCM_REG_FIC_MSG_CNTR                                                                                 0x1200b44UL //Access:RC   DataWidth:0x1c   // Counter of the output messages at FIC interfaces.
+#define MCM_REG_QM_OUT_CNTR                                                                                  0x1200b48UL //Access:RC   DataWidth:0x1c   // Counter of the output QM commands.
+#define MCM_REG_DONE0_CNTR                                                                                   0x1200b4cUL //Access:RC   DataWidth:0x1c   // Counter of the output Done0.
+#define MCM_REG_DONE1_CNTR                                                                                   0x1200b50UL //Access:RC   DataWidth:0x1c   // Counter of the output Done1.
+#define MCM_REG_DONE2_CNTR                                                                                   0x1200b54UL //Access:RC   DataWidth:0x1c   // Counter of the output Done2.
+#define MCM_REG_CCFC_CNTR                                                                                    0x1200b58UL //Access:RC   DataWidth:0x1c   // Counter of the output CCFC.
+#define MCM_REG_TCFC_CNTR                                                                                    0x1200b5cUL //Access:RC   DataWidth:0x1c   // Counter of the output TCFC.
+#define MCM_REG_ECO_RESERVED                                                                                 0x1200b84UL //Access:RW   DataWidth:0x8    // Chicken bits.
+#define MCM_REG_IS_FOC_MSEM_NXT_INF_UNIT                                                                     0x1200b88UL //Access:R    DataWidth:0x5    // Debug read from MSEM Input stage buffer: number of reads to next information unit.
+#define MCM_REG_IS_FOC_USEM_NXT_INF_UNIT                                                                     0x1200b8cUL //Access:R    DataWidth:0x6    // Debug read from USEM Input stage buffer: number of reads to next information unit.
+#define MCM_REG_IS_FOC_PBF_NXT_INF_UNIT                                                                      0x1200b94UL //Access:R    DataWidth:0x6    // Debug read from PBF Input stage buffer: number of reads to next information unit.
+#define MCM_REG_IS_FOC_USDM_NXT_INF_UNIT                                                                     0x1200b9cUL //Access:R    DataWidth:0x6    // Debug read from USDM Input stage buffer: number of reads to next information unit.
+#define MCM_REG_IS_FOC_YSDM_NXT_INF_UNIT                                                                     0x1200ba0UL //Access:R    DataWidth:0x6    // Debug read from YSDM Input stage buffer: number of reads to next information unit.
+#define MCM_REG_IS_FOC_TMLD_NXT_INF_UNIT                                                                     0x1200ba4UL //Access:R    DataWidth:0x5    // Debug read from TMLD Input stage buffer: number of reads to next information unit.
+#define MCM_REG_IS_FOC_MSEM                                                                                  0x1200c00UL //Access:R    DataWidth:0x20   // Debug read from MSEM Input stage buffer with 32-bits granularity. Read only.
+#define MCM_REG_IS_FOC_MSEM_SIZE_BB_K2                                                                       180
+#define MCM_REG_IS_FOC_MSEM_SIZE_E5                                                                          184
+#define MCM_REG_IS_FOC_USEM                                                                                  0x1201000UL //Access:R    DataWidth:0x20   // Debug read from USEM Input stage buffer with 32-bits granularity. Read only.
+#define MCM_REG_IS_FOC_USEM_SIZE                                                                             24
+#define MCM_REG_IS_FOC_PBF                                                                                   0x1201400UL //Access:R    DataWidth:0x20   // Debug read from PBF Input stage buffer with 32-bits granularity. Read only.
+#define MCM_REG_IS_FOC_PBF_SIZE                                                                              24
+#define MCM_REG_IS_FOC_USDM                                                                                  0x1201500UL //Access:R    DataWidth:0x20   // Debug read from USDM Input stage buffer with 32-bits granularity. Read only.
+#define MCM_REG_IS_FOC_USDM_SIZE                                                                             28
+#define MCM_REG_IS_FOC_YSDM                                                                                  0x1201580UL //Access:R    DataWidth:0x20   // Debug read from YSDM Input stage buffer with 32-bits granularity. Read only.
+#define MCM_REG_IS_FOC_YSDM_SIZE                                                                             12
+#define MCM_REG_CTX_RBC_ACCS                                                                                 0x1201800UL //Access:RW   DataWidth:0x10   // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - offset (in REGs (32b)) within LCID/LTID. The procedure to read context is: first define base address and offset; then read context with one of the following registers: CM_REGISTERS_AGG_CON_CTX.AGG_CON_CTX CM_REGISTERS_SM_CON_CTX.SM_CON_CTX CM_REGISTERS_AGG_TASK_CTX.AGG_TASK_CTX CM_REGISTERS_SM_TASK_CTX.SM_TASK_CTX
+#define MCM_REG_AGG_CON_CTX                                                                                  0x1201804UL //Access:RW   DataWidth:0x20   // Access is allowed only on idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The address base (LCID) and offset within LCID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to Aggregation Connection context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.
+#define MCM_REG_AGG_TASK_CTX                                                                                 0x1201808UL //Access:RW   DataWidth:0x20   // Access is allowed only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The address base (LTID) and offset within LTID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to Aggregation Task context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.
+#define MCM_REG_SM_CON_CTX                                                                                   0x120180cUL //Access:RW   DataWidth:0x20   // Access is allowed only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The address base (LCID) and offset within LCID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to STORM Connection context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.
+#define MCM_REG_SM_TASK_CTX                                                                                  0x1201810UL //Access:RW   DataWidth:0x20   // Access is allowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The address base (LTID) and offset within LTID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to STORM Task context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.
+#define MCM_REG_XX_CBYP_TBL                                                                                  0x1201820UL //Access:R    DataWidth:0xf    // Xx Connection Bypass Table.
+#define MCM_REG_XX_CBYP_TBL_SIZE                                                                             8
+#define MCM_REG_XX_TBYP_TBL                                                                                  0x1201900UL //Access:R    DataWidth:0xf    // Xx Task Bypass Table.
+#define MCM_REG_XX_TBYP_TBL_SIZE_BB_K2                                                                       22
+#define MCM_REG_XX_TBYP_TBL_SIZE_E5                                                                          64
+#define MCM_REG_XX_LCID_CAM                                                                                  0x1201a00UL //Access:R    DataWidth:0xa    // Debug only. Read only access to LCID CAM in XX protection mechanism.
+#define MCM_REG_XX_LCID_CAM_SIZE_BB_K2                                                                       22
+#define MCM_REG_XX_LCID_CAM_SIZE_E5                                                                          64
+#define MCM_REG_XX_TBL                                                                                       0x1201b00UL //Access:R    DataWidth:0x18   // Indirect access to the XX table of the XX protection mechanism. The fields are: [0] - Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: PCM - [9:8]; M/T/U/X/YCM - [17:12]; Next pointer: PCM - [11:10]; M/T/U/X/YCM - [23:18];
+#define MCM_REG_XX_TBL_SIZE_BB_K2                                                                            22
+#define MCM_REG_XX_TBL_SIZE_E5                                                                               64
+#define MCM_REG_XX_DSCR_TBL                                                                                  0x1201c00UL //Access:RW   DataWidth:0x1e   // Indirect access to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [13:9];PCM [14:9]; TCM [13:9]; UCM [13:9];XCM [10:9];YCM[13:9]); Next pointer (MCM [19:14]; PCM [16:15]; TCM[19:14]; UCM [19:14]; XCM [16:11]; YCM [19:14]); LTID (MCM [28:20]; PCM [25:17] - reserved; TCM[28:20]; UCM [28:20]; XCM [25:17] - reserved; YCM [28:20]). Task Domain Exist (MCM [29]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - reserved; YCM [29]). A free link list in the XX descriptor table should be build. This is done by writing the following values to all effective entries in the table:xx_descr_table[i].next_pointer = i+1 (i=0 - (xx_msg_up_bnd-2)); xx_descr_table[i].next_pointer= 0 (i=xx_msg_up_bnd-1). The value of i is between 0 to the configured (not default) value of (xx_msg_up_bnd-1). The not effective entries (those which succeed the last effective entry with index (xx_msg_up_bnd-1)) can be initialized to any value for initialization procedure simplicity seek.
+#define MCM_REG_XX_DSCR_TBL_SIZE                                                                             64
+#define MCM_REG_N_SM_CON_CTX_LD_0_BB_K2                                                                      0x1200814UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define MCM_REG_N_SM_CON_CTX_LD_0_E5                                                                         0x1201d00UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define MCM_REG_N_SM_CON_CTX_LD_1_BB_K2                                                                      0x1200818UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define MCM_REG_N_SM_CON_CTX_LD_1_E5                                                                         0x1201d04UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define MCM_REG_N_SM_CON_CTX_LD_2_BB_K2                                                                      0x120081cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define MCM_REG_N_SM_CON_CTX_LD_2_E5                                                                         0x1201d08UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define MCM_REG_N_SM_CON_CTX_LD_3_BB_K2                                                                      0x1200820UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define MCM_REG_N_SM_CON_CTX_LD_3_E5                                                                         0x1201d0cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define MCM_REG_N_SM_CON_CTX_LD_4_BB_K2                                                                      0x1200824UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define MCM_REG_N_SM_CON_CTX_LD_4_E5                                                                         0x1201d10UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define MCM_REG_N_SM_CON_CTX_LD_5_BB_K2                                                                      0x1200828UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define MCM_REG_N_SM_CON_CTX_LD_5_E5                                                                         0x1201d14UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define MCM_REG_N_SM_CON_CTX_LD_6_BB_K2                                                                      0x120082cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define MCM_REG_N_SM_CON_CTX_LD_6_E5                                                                         0x1201d18UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define MCM_REG_N_SM_CON_CTX_LD_7_BB_K2                                                                      0x1200830UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define MCM_REG_N_SM_CON_CTX_LD_7_E5                                                                         0x1201d1cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define MCM_REG_N_SM_CON_CTX_LD_8_E5                                                                         0x1201d20UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define MCM_REG_N_SM_CON_CTX_LD_9_E5                                                                         0x1201d24UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define MCM_REG_N_SM_CON_CTX_LD_10_E5                                                                        0x1201d28UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 10).
+#define MCM_REG_N_SM_CON_CTX_LD_11_E5                                                                        0x1201d2cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define MCM_REG_N_SM_CON_CTX_LD_12_E5                                                                        0x1201d30UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define MCM_REG_N_SM_CON_CTX_LD_13_E5                                                                        0x1201d34UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define MCM_REG_N_SM_CON_CTX_LD_14_E5                                                                        0x1201d38UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define MCM_REG_N_SM_CON_CTX_LD_15_E5                                                                        0x1201d3cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define MCM_REG_AGG_CON_CTX_SIZE_0_BB_K2                                                                     0x12008a0UL //Access:RW   DataWidth:0x1    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less or 1.
+#define MCM_REG_AGG_CON_CTX_SIZE_0_E5                                                                        0x1201d40UL //Access:RW   DataWidth:0x1    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
+#define MCM_REG_AGG_CON_CTX_SIZE_1_BB_K2                                                                     0x12008a4UL //Access:RW   DataWidth:0x1    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
+#define MCM_REG_AGG_CON_CTX_SIZE_1_E5                                                                        0x1201d44UL //Access:RW   DataWidth:0x1    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
+#define MCM_REG_AGG_CON_CTX_SIZE_2_BB_K2                                                                     0x12008a8UL //Access:RW   DataWidth:0x1    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
+#define MCM_REG_AGG_CON_CTX_SIZE_2_E5                                                                        0x1201d48UL //Access:RW   DataWidth:0x1    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
+#define MCM_REG_AGG_CON_CTX_SIZE_3_BB_K2                                                                     0x12008acUL //Access:RW   DataWidth:0x1    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
+#define MCM_REG_AGG_CON_CTX_SIZE_3_E5                                                                        0x1201d4cUL //Access:RW   DataWidth:0x1    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
+#define MCM_REG_AGG_CON_CTX_SIZE_4_BB_K2                                                                     0x12008b0UL //Access:RW   DataWidth:0x1    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
+#define MCM_REG_AGG_CON_CTX_SIZE_4_E5                                                                        0x1201d50UL //Access:RW   DataWidth:0x1    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
+#define MCM_REG_AGG_CON_CTX_SIZE_5_BB_K2                                                                     0x12008b4UL //Access:RW   DataWidth:0x1    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
+#define MCM_REG_AGG_CON_CTX_SIZE_5_E5                                                                        0x1201d54UL //Access:RW   DataWidth:0x1    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
+#define MCM_REG_AGG_CON_CTX_SIZE_6_BB_K2                                                                     0x12008b8UL //Access:RW   DataWidth:0x1    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
+#define MCM_REG_AGG_CON_CTX_SIZE_6_E5                                                                        0x1201d58UL //Access:RW   DataWidth:0x1    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
+#define MCM_REG_AGG_CON_CTX_SIZE_7_BB_K2                                                                     0x12008bcUL //Access:RW   DataWidth:0x1    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
+#define MCM_REG_AGG_CON_CTX_SIZE_7_E5                                                                        0x1201d5cUL //Access:RW   DataWidth:0x1    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
+#define MCM_REG_AGG_CON_CTX_SIZE_8_E5                                                                        0x1201d60UL //Access:RW   DataWidth:0x1    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less or 1.
+#define MCM_REG_AGG_CON_CTX_SIZE_9_E5                                                                        0x1201d64UL //Access:RW   DataWidth:0x1    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
+#define MCM_REG_AGG_CON_CTX_SIZE_10_E5                                                                       0x1201d68UL //Access:RW   DataWidth:0x1    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
+#define MCM_REG_AGG_CON_CTX_SIZE_11_E5                                                                       0x1201d6cUL //Access:RW   DataWidth:0x1    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
+#define MCM_REG_AGG_CON_CTX_SIZE_12_E5                                                                       0x1201d70UL //Access:RW   DataWidth:0x1    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
+#define MCM_REG_AGG_CON_CTX_SIZE_13_E5                                                                       0x1201d74UL //Access:RW   DataWidth:0x1    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
+#define MCM_REG_AGG_CON_CTX_SIZE_14_E5                                                                       0x1201d78UL //Access:RW   DataWidth:0x1    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
+#define MCM_REG_AGG_CON_CTX_SIZE_15_E5                                                                       0x1201d7cUL //Access:RW   DataWidth:0x1    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
+#define MCM_REG_QM_CON_BASE_EVNT_ID_0_BB_K2                                                                  0x1200404UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define MCM_REG_QM_CON_BASE_EVNT_ID_0_E5                                                                     0x1201d80UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define MCM_REG_QM_CON_BASE_EVNT_ID_1_BB_K2                                                                  0x1200408UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define MCM_REG_QM_CON_BASE_EVNT_ID_1_E5                                                                     0x1201d84UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define MCM_REG_QM_CON_BASE_EVNT_ID_2_BB_K2                                                                  0x120040cUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define MCM_REG_QM_CON_BASE_EVNT_ID_2_E5                                                                     0x1201d88UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define MCM_REG_QM_CON_BASE_EVNT_ID_3_BB_K2                                                                  0x1200410UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define MCM_REG_QM_CON_BASE_EVNT_ID_3_E5                                                                     0x1201d8cUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define MCM_REG_QM_CON_BASE_EVNT_ID_4_BB_K2                                                                  0x1200414UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define MCM_REG_QM_CON_BASE_EVNT_ID_4_E5                                                                     0x1201d90UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define MCM_REG_QM_CON_BASE_EVNT_ID_5_BB_K2                                                                  0x1200418UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define MCM_REG_QM_CON_BASE_EVNT_ID_5_E5                                                                     0x1201d94UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define MCM_REG_QM_CON_BASE_EVNT_ID_6_BB_K2                                                                  0x120041cUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define MCM_REG_QM_CON_BASE_EVNT_ID_6_E5                                                                     0x1201d98UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define MCM_REG_QM_CON_BASE_EVNT_ID_7_BB_K2                                                                  0x1200420UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define MCM_REG_QM_CON_BASE_EVNT_ID_7_E5                                                                     0x1201d9cUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define MCM_REG_QM_CON_BASE_EVNT_ID_8_E5                                                                     0x1201da0UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define MCM_REG_QM_CON_BASE_EVNT_ID_9_E5                                                                     0x1201da4UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define MCM_REG_QM_CON_BASE_EVNT_ID_10_E5                                                                    0x1201da8UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define MCM_REG_QM_CON_BASE_EVNT_ID_11_E5                                                                    0x1201dacUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define MCM_REG_QM_CON_BASE_EVNT_ID_12_E5                                                                    0x1201db0UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define MCM_REG_QM_CON_BASE_EVNT_ID_13_E5                                                                    0x1201db4UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define MCM_REG_QM_CON_BASE_EVNT_ID_14_E5                                                                    0x1201db8UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define MCM_REG_QM_CON_BASE_EVNT_ID_15_E5                                                                    0x1201dbcUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_0_BB_K2                                                             0x1200444UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_0_E5                                                                0x1201dc0UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_1_BB_K2                                                             0x1200448UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_1_E5                                                                0x1201dc4UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_2_BB_K2                                                             0x120044cUL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_2_E5                                                                0x1201dc8UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_3_BB_K2                                                             0x1200450UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_3_E5                                                                0x1201dccUL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_4_BB_K2                                                             0x1200454UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_4_E5                                                                0x1201dd0UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_5_BB_K2                                                             0x1200458UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_5_E5                                                                0x1201dd4UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_6_BB_K2                                                             0x120045cUL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_6_E5                                                                0x1201dd8UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_7_BB_K2                                                             0x1200460UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_7_E5                                                                0x1201ddcUL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_8_E5                                                                0x1201de0UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_9_E5                                                                0x1201de4UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_10_E5                                                               0x1201de8UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_11_E5                                                               0x1201decUL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_12_E5                                                               0x1201df0UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_13_E5                                                               0x1201df4UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_14_E5                                                               0x1201df8UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_15_E5                                                               0x1201dfcUL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define MCM_REG_QM_XXLOCK_CMD_0_BB_K2                                                                        0x1200504UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define MCM_REG_QM_XXLOCK_CMD_0_E5                                                                           0x1201e00UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define MCM_REG_QM_XXLOCK_CMD_1_BB_K2                                                                        0x1200508UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define MCM_REG_QM_XXLOCK_CMD_1_E5                                                                           0x1201e04UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define MCM_REG_QM_XXLOCK_CMD_2_BB_K2                                                                        0x120050cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define MCM_REG_QM_XXLOCK_CMD_2_E5                                                                           0x1201e08UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define MCM_REG_QM_XXLOCK_CMD_3_BB_K2                                                                        0x1200510UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define MCM_REG_QM_XXLOCK_CMD_3_E5                                                                           0x1201e0cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define MCM_REG_QM_XXLOCK_CMD_4_BB_K2                                                                        0x1200514UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define MCM_REG_QM_XXLOCK_CMD_4_E5                                                                           0x1201e10UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define MCM_REG_QM_XXLOCK_CMD_5_BB_K2                                                                        0x1200518UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define MCM_REG_QM_XXLOCK_CMD_5_E5                                                                           0x1201e14UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define MCM_REG_QM_XXLOCK_CMD_6_BB_K2                                                                        0x120051cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define MCM_REG_QM_XXLOCK_CMD_6_E5                                                                           0x1201e18UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define MCM_REG_QM_XXLOCK_CMD_7_BB_K2                                                                        0x1200520UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define MCM_REG_QM_XXLOCK_CMD_7_E5                                                                           0x1201e1cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define MCM_REG_QM_XXLOCK_CMD_8_E5                                                                           0x1201e20UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define MCM_REG_QM_XXLOCK_CMD_9_E5                                                                           0x1201e24UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define MCM_REG_QM_XXLOCK_CMD_10_E5                                                                          0x1201e28UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define MCM_REG_QM_XXLOCK_CMD_11_E5                                                                          0x1201e2cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define MCM_REG_QM_XXLOCK_CMD_12_E5                                                                          0x1201e30UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define MCM_REG_QM_XXLOCK_CMD_13_E5                                                                          0x1201e34UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define MCM_REG_QM_XXLOCK_CMD_14_E5                                                                          0x1201e38UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define MCM_REG_QM_XXLOCK_CMD_15_E5                                                                          0x1201e3cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define MCM_REG_QM_CON_USE_ST_FLG_0_BB_K2                                                                    0x1200524UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define MCM_REG_QM_CON_USE_ST_FLG_0_E5                                                                       0x1201e40UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define MCM_REG_QM_CON_USE_ST_FLG_1_BB_K2                                                                    0x1200528UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define MCM_REG_QM_CON_USE_ST_FLG_1_E5                                                                       0x1201e44UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define MCM_REG_QM_CON_USE_ST_FLG_2_BB_K2                                                                    0x120052cUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define MCM_REG_QM_CON_USE_ST_FLG_2_E5                                                                       0x1201e48UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define MCM_REG_QM_CON_USE_ST_FLG_3_BB_K2                                                                    0x1200530UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define MCM_REG_QM_CON_USE_ST_FLG_3_E5                                                                       0x1201e4cUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define MCM_REG_QM_CON_USE_ST_FLG_4_BB_K2                                                                    0x1200534UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define MCM_REG_QM_CON_USE_ST_FLG_4_E5                                                                       0x1201e50UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define MCM_REG_QM_CON_USE_ST_FLG_5_BB_K2                                                                    0x1200538UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define MCM_REG_QM_CON_USE_ST_FLG_5_E5                                                                       0x1201e54UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define MCM_REG_QM_CON_USE_ST_FLG_6_BB_K2                                                                    0x120053cUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define MCM_REG_QM_CON_USE_ST_FLG_6_E5                                                                       0x1201e58UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define MCM_REG_QM_CON_USE_ST_FLG_7_BB_K2                                                                    0x1200540UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define MCM_REG_QM_CON_USE_ST_FLG_7_E5                                                                       0x1201e5cUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define MCM_REG_QM_CON_USE_ST_FLG_8_E5                                                                       0x1201e60UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define MCM_REG_QM_CON_USE_ST_FLG_9_E5                                                                       0x1201e64UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define MCM_REG_QM_CON_USE_ST_FLG_10_E5                                                                      0x1201e68UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define MCM_REG_QM_CON_USE_ST_FLG_11_E5                                                                      0x1201e6cUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define MCM_REG_QM_CON_USE_ST_FLG_12_E5                                                                      0x1201e70UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define MCM_REG_QM_CON_USE_ST_FLG_13_E5                                                                      0x1201e74UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define MCM_REG_QM_CON_USE_ST_FLG_14_E5                                                                      0x1201e78UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define MCM_REG_QM_CON_USE_ST_FLG_15_E5                                                                      0x1201e7cUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define MCM_REG_QM_SM_CON_CTX_LDST_FLG_0_BB_K2                                                               0x1200464UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define MCM_REG_QM_SM_CON_CTX_LDST_FLG_0_E5                                                                  0x1201e80UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define MCM_REG_QM_SM_CON_CTX_LDST_FLG_1_BB_K2                                                               0x1200468UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define MCM_REG_QM_SM_CON_CTX_LDST_FLG_1_E5                                                                  0x1201e84UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define MCM_REG_QM_SM_CON_CTX_LDST_FLG_2_BB_K2                                                               0x120046cUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define MCM_REG_QM_SM_CON_CTX_LDST_FLG_2_E5                                                                  0x1201e88UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define MCM_REG_QM_SM_CON_CTX_LDST_FLG_3_BB_K2                                                               0x1200470UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define MCM_REG_QM_SM_CON_CTX_LDST_FLG_3_E5                                                                  0x1201e8cUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define MCM_REG_QM_SM_CON_CTX_LDST_FLG_4_BB_K2                                                               0x1200474UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define MCM_REG_QM_SM_CON_CTX_LDST_FLG_4_E5                                                                  0x1201e90UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define MCM_REG_QM_SM_CON_CTX_LDST_FLG_5_BB_K2                                                               0x1200478UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define MCM_REG_QM_SM_CON_CTX_LDST_FLG_5_E5                                                                  0x1201e94UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define MCM_REG_QM_SM_CON_CTX_LDST_FLG_6_BB_K2                                                               0x120047cUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define MCM_REG_QM_SM_CON_CTX_LDST_FLG_6_E5                                                                  0x1201e98UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define MCM_REG_QM_SM_CON_CTX_LDST_FLG_7_BB_K2                                                               0x1200480UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define MCM_REG_QM_SM_CON_CTX_LDST_FLG_7_E5                                                                  0x1201e9cUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define MCM_REG_QM_SM_CON_CTX_LDST_FLG_8_E5                                                                  0x1201ea0UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define MCM_REG_QM_SM_CON_CTX_LDST_FLG_9_E5                                                                  0x1201ea4UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define MCM_REG_QM_SM_CON_CTX_LDST_FLG_10_E5                                                                 0x1201ea8UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define MCM_REG_QM_SM_CON_CTX_LDST_FLG_11_E5                                                                 0x1201eacUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define MCM_REG_QM_SM_CON_CTX_LDST_FLG_12_E5                                                                 0x1201eb0UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define MCM_REG_QM_SM_CON_CTX_LDST_FLG_13_E5                                                                 0x1201eb4UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define MCM_REG_QM_SM_CON_CTX_LDST_FLG_14_E5                                                                 0x1201eb8UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define MCM_REG_QM_SM_CON_CTX_LDST_FLG_15_E5                                                                 0x1201ebcUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define MCM_REG_IS_FOC_TMLD_BB_K2                                                                            0x1201600UL //Access:R    DataWidth:0x20   // Debug read from TMLD Input stage buffer with 32-bits granularity. Read only.
+#define MCM_REG_IS_FOC_TMLD_E5                                                                               0x1202000UL //Access:R    DataWidth:0x20   // Debug read from TMLD Input stage buffer with 32-bits granularity. Read only.
+#define MCM_REG_IS_FOC_TMLD_SIZE_BB_K2                                                                       124
+#define MCM_REG_IS_FOC_TMLD_SIZE_E5                                                                          280
+#define MCM_REG_TSDM_WEIGHT_E5                                                                               0x1202800UL //Access:RW   DataWidth:0x3    // The weight of the input TSDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define MCM_REG_TSDM_FRWRD_MODE_E5                                                                           0x1202804UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define MCM_REG_TSDM_LENGTH_MIS_E5                                                                           0x1202808UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at TSDM interface.
+#define MCM_REG_TSDM_MSG_CNTR_E5                                                                             0x120280cUL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input TSDM.
+#define MCM_REG_IS_TSDM_FILL_LVL_E5                                                                          0x1202810UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in TSDM Input Stage.
+#define MCM_REG_IS_FOC_TSDM_NXT_INF_UNIT_E5                                                                  0x1202814UL //Access:R    DataWidth:0x6    // Debug read from TSDM Input stage buffer: number of reads to next information unit.
+#define MCM_REG_IS_FOC_TSDM_E5                                                                               0x1202840UL //Access:R    DataWidth:0x20   // Debug read from TSDM Input stage buffer with 32-bits granularity. Read only.
+#define MCM_REG_IS_FOC_TSDM_SIZE                                                                             16
+#define MCM_REG_PSDM_WEIGHT_E5                                                                               0x1202880UL //Access:RW   DataWidth:0x3    // The weight of the input PSDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define MCM_REG_PSDM_FRWRD_MODE_E5                                                                           0x1202884UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define MCM_REG_PSDM_LENGTH_MIS_E5                                                                           0x1202888UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at PSDM interface.
+#define MCM_REG_PSDM_MSG_CNTR_E5                                                                             0x120288cUL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input PSDM.
+#define MCM_REG_IS_PSDM_FILL_LVL_E5                                                                          0x1202890UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in PSDM Input Stage.
+#define MCM_REG_IS_FOC_PSDM_NXT_INF_UNIT_E5                                                                  0x1202894UL //Access:R    DataWidth:0x6    // Debug read from PSDM Input stage buffer: number of reads to next information unit.
+#define MCM_REG_IS_FOC_PSDM_E5                                                                               0x12028c0UL //Access:R    DataWidth:0x20   // Debug read from PSDM Input stage buffer with 32-bits granularity. Read only.
+#define MCM_REG_IS_FOC_PSDM_SIZE                                                                             16
+#define MCM_REG_MSDM_WEIGHT_BB_K2                                                                            0x1200618UL //Access:RW   DataWidth:0x3    // The weight of the MSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define MCM_REG_MSDM_WEIGHT_E5                                                                               0x1202900UL //Access:RW   DataWidth:0x3    // The weight of the input MSDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define MCM_REG_MSDM_FRWRD_MODE_BB_K2                                                                        0x1200650UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define MCM_REG_MSDM_FRWRD_MODE_E5                                                                           0x1202904UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define MCM_REG_MSDM_LENGTH_MIS_BB_K2                                                                        0x1200aa8UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at MSDM interface.
+#define MCM_REG_MSDM_LENGTH_MIS_E5                                                                           0x1202908UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at MSDM interface.
+#define MCM_REG_MSDM_MSG_CNTR_BB_K2                                                                          0x1200ac8UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input MSDM.
+#define MCM_REG_MSDM_MSG_CNTR_E5                                                                             0x120290cUL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input MSDM.
+#define MCM_REG_IS_MSDM_FILL_LVL_BB_K2                                                                       0x1200afcUL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in MSDM Input Stage.
+#define MCM_REG_IS_MSDM_FILL_LVL_E5                                                                          0x1202910UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in MSDM Input Stage.
+#define MCM_REG_IS_FOC_MSDM_NXT_INF_UNIT_BB_K2                                                               0x1200b98UL //Access:R    DataWidth:0x6    // Debug read from MSDM Input stage buffer: number of reads to next information unit.
+#define MCM_REG_IS_FOC_MSDM_NXT_INF_UNIT_E5                                                                  0x1202914UL //Access:R    DataWidth:0x6    // Debug read from MSDM Input stage buffer: number of reads to next information unit.
+#define MCM_REG_IS_FOC_MSDM_BB_K2                                                                            0x1201480UL //Access:R    DataWidth:0x20   // Debug read from MSDM Input stage buffer with 32-bits granularity. Read only.
+#define MCM_REG_IS_FOC_MSDM_E5                                                                               0x1202980UL //Access:R    DataWidth:0x20   // Debug read from MSDM Input stage buffer with 32-bits granularity. Read only.
+#define MCM_REG_IS_FOC_MSDM_SIZE                                                                             20
+#define MCM_REG_YSEM_WEIGHT_BB_K2                                                                            0x120060cUL //Access:RW   DataWidth:0x3    // The weight of the input Ysem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define MCM_REG_YSEM_WEIGHT_E5                                                                               0x1202a00UL //Access:RW   DataWidth:0x3    // The weight of the input Ysem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define MCM_REG_YSEM_FRWRD_MODE_BB_K2                                                                        0x1200664UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define MCM_REG_YSEM_FRWRD_MODE_E5                                                                           0x1202a04UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define MCM_REG_YSEM_MSG_CNTR_BB_K2                                                                          0x1200adcUL //Access:RC   DataWidth:0x1c   // Counter of the input messages at input Ysem.
+#define MCM_REG_YSEM_MSG_CNTR_E5                                                                             0x1202a08UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at input Ysem.
+#define MCM_REG_IS_YSEM_FILL_LVL_BB_K2                                                                       0x1200b10UL //Access:R    DataWidth:0x5    // Number of QREGs (128b) of data in YSEM Input Stage.
+#define MCM_REG_IS_YSEM_FILL_LVL_E5                                                                          0x1202a0cUL //Access:R    DataWidth:0x4    // Number of QREGs (128b) for TCM, XCM or 2 QREGs (256b) for MCM of data in YSEM Input Stage.
+#define MCM_REG_IS_FOC_YSEM_NXT_INF_UNIT_BB_K2                                                               0x1200b90UL //Access:R    DataWidth:0x6    // Debug read from YSEM Input stage buffer: number of reads to next information unit.
+#define MCM_REG_IS_FOC_YSEM_NXT_INF_UNIT_E5                                                                  0x1202a10UL //Access:R    DataWidth:0x5    // Debug read from YSEM Input stage buffer: number of reads to next information unit.
+#define MCM_REG_IS_FOC_YSEM_BB_K2                                                                            0x1201200UL //Access:R    DataWidth:0x20   // Debug read from YSEM Input stage buffer with 32-bits granularity. Read only.
+#define MCM_REG_IS_FOC_YSEM_E5                                                                               0x1202c00UL //Access:R    DataWidth:0x20   // Debug read from YSEM Input stage buffer with 32-bits granularity. Read only.
+#define MCM_REG_IS_FOC_YSEM_SIZE_BB_K2                                                                       108
+#define MCM_REG_IS_FOC_YSEM_SIZE_E5                                                                          112
+#define MCM_REG_AGG_TASK_CF0_Q_BB_K2                                                                         0x1200934UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define MCM_REG_AGG_TASK_CF0_Q_E5                                                                            0x1202e00UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define MCM_REG_AGG_TASK_CF1_Q_BB_K2                                                                         0x1200938UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define MCM_REG_AGG_TASK_CF1_Q_E5                                                                            0x1202e04UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define MCM_REG_AGG_TASK_CF2_Q_BB_K2                                                                         0x120093cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define MCM_REG_AGG_TASK_CF2_Q_E5                                                                            0x1202e08UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define MCM_REG_AGG_TASK_CF3_Q_E5                                                                            0x1202e0cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define MCM_REG_AGG_TASK_CF4_Q_E5                                                                            0x1202e10UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define MCM_REG_XX_MSG_RAM                                                                                   0x1208000UL //Access:R    DataWidth:0x20   // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
+#define MCM_REG_XX_MSG_RAM_SIZE_BB_K2                                                                        6656
+#define MCM_REG_XX_MSG_RAM_SIZE_E5                                                                           7168
+#define UCM_REG_INIT                                                                                         0x1280000UL //Access:RW   DataWidth:0x1    // Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
+#define UCM_REG_MEMCTRL_WR_RD_N_BB                                                                           0x1280040UL //Access:RW   DataWidth:0x1    // wr/rd indication to CPU BIST
+#define UCM_REG_MEMCTRL_CMD_BB                                                                               0x1280044UL //Access:RW   DataWidth:0x8    // command to CPU BIST
+#define UCM_REG_MEMCTRL_ADDRESS_BB                                                                           0x1280048UL //Access:RW   DataWidth:0x8    // address to CPU BIST
+#define UCM_REG_MEMCTRL_STATUS                                                                               0x128004cUL //Access:R    DataWidth:0x20   // status from CPU BIST
+#define UCM_REG_DBG_SELECT                                                                                   0x1280050UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define UCM_REG_DBG_DWORD_ENABLE                                                                             0x1280054UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define UCM_REG_DBG_SHIFT                                                                                    0x1280058UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define UCM_REG_DBG_FORCE_VALID                                                                              0x128005cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define UCM_REG_DBG_FORCE_FRAME                                                                              0x1280060UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define UCM_REG_DBG_OUT_DATA                                                                                 0x1280080UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define UCM_REG_DBG_OUT_DATA_SIZE                                                                            8
+#define UCM_REG_DBG_OUT_VALID                                                                                0x12800a0UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define UCM_REG_DBG_OUT_FRAME                                                                                0x12800a4UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define UCM_REG_AFFINITY_TYPE_0_E5                                                                           0x12800a8UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define UCM_REG_AFFINITY_TYPE_1_E5                                                                           0x12800acUL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define UCM_REG_AFFINITY_TYPE_2_E5                                                                           0x12800b0UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define UCM_REG_AFFINITY_TYPE_3_E5                                                                           0x12800b4UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define UCM_REG_AFFINITY_TYPE_4_E5                                                                           0x12800b8UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define UCM_REG_AFFINITY_TYPE_5_E5                                                                           0x12800bcUL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define UCM_REG_AFFINITY_TYPE_6_E5                                                                           0x12800c0UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define UCM_REG_AFFINITY_TYPE_7_E5                                                                           0x12800c4UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define UCM_REG_AFFINITY_TYPE_8_E5                                                                           0x12800c8UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define UCM_REG_AFFINITY_TYPE_9_E5                                                                           0x12800ccUL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define UCM_REG_AFFINITY_TYPE_10_E5                                                                          0x12800d0UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define UCM_REG_AFFINITY_TYPE_11_E5                                                                          0x12800d4UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define UCM_REG_AFFINITY_TYPE_12_E5                                                                          0x12800d8UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define UCM_REG_AFFINITY_TYPE_13_E5                                                                          0x12800dcUL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define UCM_REG_AFFINITY_TYPE_14_E5                                                                          0x12800e0UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define UCM_REG_AFFINITY_TYPE_15_E5                                                                          0x12800e4UL //Access:RW   DataWidth:0x2    // Afinity type per connection type.
+#define UCM_REG_EXCLUSIVE_FLG_0_E5                                                                           0x12800e8UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define UCM_REG_EXCLUSIVE_FLG_1_E5                                                                           0x12800ecUL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define UCM_REG_EXCLUSIVE_FLG_2_E5                                                                           0x12800f0UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define UCM_REG_EXCLUSIVE_FLG_3_E5                                                                           0x12800f4UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define UCM_REG_EXCLUSIVE_FLG_4_E5                                                                           0x12800f8UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define UCM_REG_EXCLUSIVE_FLG_5_E5                                                                           0x12800fcUL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define UCM_REG_EXCLUSIVE_FLG_6_E5                                                                           0x1280100UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define UCM_REG_EXCLUSIVE_FLG_7_E5                                                                           0x1280104UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define UCM_REG_EXCLUSIVE_FLG_8_E5                                                                           0x1280108UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define UCM_REG_EXCLUSIVE_FLG_9_E5                                                                           0x128010cUL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define UCM_REG_EXCLUSIVE_FLG_10_E5                                                                          0x1280110UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define UCM_REG_EXCLUSIVE_FLG_11_E5                                                                          0x1280114UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define UCM_REG_EXCLUSIVE_FLG_12_E5                                                                          0x1280118UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define UCM_REG_EXCLUSIVE_FLG_13_E5                                                                          0x128011cUL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define UCM_REG_EXCLUSIVE_FLG_14_E5                                                                          0x1280120UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define UCM_REG_EXCLUSIVE_FLG_15_E5                                                                          0x1280124UL //Access:RW   DataWidth:0x1    // Exclusive flag per connection type.
+#define UCM_REG_AGG_CON_CF0_Q_BB_K2                                                                          0x1280914UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_CON_CF0_Q_E5                                                                             0x1280128UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define UCM_REG_AGG_CON_CF1_Q_BB_K2                                                                          0x1280918UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_CON_CF1_Q_E5                                                                             0x128012cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define UCM_REG_AGG_CON_CF2_Q_BB_K2                                                                          0x128091cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_CON_CF2_Q_E5                                                                             0x1280130UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define UCM_REG_AGG_CON_CF3_Q_BB_K2                                                                          0x1280920UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_CON_CF3_Q_E5                                                                             0x1280134UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define UCM_REG_AGG_CON_CF4_Q_BB_K2                                                                          0x1280924UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_CON_CF4_Q_E5                                                                             0x1280138UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define UCM_REG_AGG_CON_CF5_Q_BB_K2                                                                          0x1280928UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_CON_CF5_Q_E5                                                                             0x128013cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define UCM_REG_AGG_CON_CF6_Q_BB_K2                                                                          0x128092cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_CON_CF6_Q_E5                                                                             0x1280140UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define UCM_REG_AGG_CON_CF7_Q_E5                                                                             0x1280144UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define UCM_REG_AGG_CON_CF8_Q_E5                                                                             0x1280148UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define UCM_REG_INT_STS_0                                                                                    0x1280180UL //Access:R    DataWidth:0x14   // Multi Field Register.
+  #define UCM_REG_INT_STS_0_ADDRESS_ERROR                                                                    (0x1<<0) // Signals an unknown address to the rf module.
+  #define UCM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                              0
+  #define UCM_REG_INT_STS_0_IS_STORM_OVFL_ERR                                                                (0x1<<1) // Write to full STORM input buffer.
+  #define UCM_REG_INT_STS_0_IS_STORM_OVFL_ERR_SHIFT                                                          1
+  #define UCM_REG_INT_STS_0_IS_STORM_UNDER_ERR                                                               (0x1<<2) // Read from empty  STORM input buffer.
+  #define UCM_REG_INT_STS_0_IS_STORM_UNDER_ERR_SHIFT                                                         2
+  #define UCM_REG_INT_STS_0_IS_XSDM_OVFL_ERR                                                                 (0x1<<3) // Write to full XSDM input buffer.
+  #define UCM_REG_INT_STS_0_IS_XSDM_OVFL_ERR_SHIFT                                                           3
+  #define UCM_REG_INT_STS_0_IS_XSDM_UNDER_ERR                                                                (0x1<<4) // Read from empty XSDM input buffer.
+  #define UCM_REG_INT_STS_0_IS_XSDM_UNDER_ERR_SHIFT                                                          4
+  #define UCM_REG_INT_STS_0_IS_YSDM_OVFL_ERR                                                                 (0x1<<5) // Write to full YSDM input buffer.
+  #define UCM_REG_INT_STS_0_IS_YSDM_OVFL_ERR_SHIFT                                                           5
+  #define UCM_REG_INT_STS_0_IS_YSDM_UNDER_ERR                                                                (0x1<<6) // Read from empty  YSDM input buffer.
+  #define UCM_REG_INT_STS_0_IS_YSDM_UNDER_ERR_SHIFT                                                          6
+  #define UCM_REG_INT_STS_0_IS_USDM_OVFL_ERR                                                                 (0x1<<7) // Write to full USDM input buffer.
+  #define UCM_REG_INT_STS_0_IS_USDM_OVFL_ERR_SHIFT                                                           7
+  #define UCM_REG_INT_STS_0_IS_USDM_UNDER_ERR                                                                (0x1<<8) // Read from empty USDM input buffer.
+  #define UCM_REG_INT_STS_0_IS_USDM_UNDER_ERR_SHIFT                                                          8
+  #define UCM_REG_INT_STS_0_IS_RDIF_OVFL_ERR                                                                 (0x1<<9) // Write to full RDIF input buffer.
+  #define UCM_REG_INT_STS_0_IS_RDIF_OVFL_ERR_SHIFT                                                           9
+  #define UCM_REG_INT_STS_0_IS_RDIF_UNDER_ERR                                                                (0x1<<10) // Read from empty RDIF input buffer.
+  #define UCM_REG_INT_STS_0_IS_RDIF_UNDER_ERR_SHIFT                                                          10
+  #define UCM_REG_INT_STS_0_IS_TDIF_OVFL_ERR                                                                 (0x1<<11) // Write to full TDIF input buffer.
+  #define UCM_REG_INT_STS_0_IS_TDIF_OVFL_ERR_SHIFT                                                           11
+  #define UCM_REG_INT_STS_0_IS_TDIF_UNDER_ERR                                                                (0x1<<12) // Read from empty TDIF input buffer.
+  #define UCM_REG_INT_STS_0_IS_TDIF_UNDER_ERR_SHIFT                                                          12
+  #define UCM_REG_INT_STS_0_IS_MULD_OVFL_ERR                                                                 (0x1<<13) // Write to full MULD input buffer.
+  #define UCM_REG_INT_STS_0_IS_MULD_OVFL_ERR_SHIFT                                                           13
+  #define UCM_REG_INT_STS_0_IS_MULD_UNDER_ERR                                                                (0x1<<14) // Read from empty MULD input buffer.
+  #define UCM_REG_INT_STS_0_IS_MULD_UNDER_ERR_SHIFT                                                          14
+  #define UCM_REG_INT_STS_0_IS_YSEM_OVFL_ERR_E5                                                              (0x1<<15) // Write to full Ysem input buffer.
+  #define UCM_REG_INT_STS_0_IS_YSEM_OVFL_ERR_E5_SHIFT                                                        15
+  #define UCM_REG_INT_STS_0_EXT_LD_UNDER_ERR_E5                                                              (0x1<<16) // Read from empty External read buffer.
+  #define UCM_REG_INT_STS_0_EXT_LD_UNDER_ERR_E5_SHIFT                                                        16
+  #define UCM_REG_INT_STS_0_EXT_LD_OVFL_ERR_E5                                                               (0x1<<17) // Write to fully External read buffer.
+  #define UCM_REG_INT_STS_0_EXT_LD_OVFL_ERR_E5_SHIFT                                                         17
+  #define UCM_REG_INT_STS_0_AFFINITY_TYPE_NO_CON_E5                                                          (0x1<<18) // Affinity type = 2 (connection based) but connection doesn't exist.
+  #define UCM_REG_INT_STS_0_AFFINITY_TYPE_NO_CON_E5_SHIFT                                                    18
+  #define UCM_REG_INT_STS_0_AFFINITY_TYPE_NO_TASK_E5                                                         (0x1<<19) // Affinity type = 3 (task based) but task doesn't exist.
+  #define UCM_REG_INT_STS_0_AFFINITY_TYPE_NO_TASK_E5_SHIFT                                                   19
+  #define UCM_REG_INT_STS_0_IS_YULD_OVFL_ERR_BB_K2                                                           (0x1<<15) // Write to full YULD input buffer.
+  #define UCM_REG_INT_STS_0_IS_YULD_OVFL_ERR_BB_K2_SHIFT                                                     15
+  #define UCM_REG_INT_STS_0_IS_YULD_UNDER_ERR_BB_K2                                                          (0x1<<16) // Read from empty YULD input buffer.
+  #define UCM_REG_INT_STS_0_IS_YULD_UNDER_ERR_BB_K2_SHIFT                                                    16
+#define UCM_REG_INT_MASK_0                                                                                   0x1280184UL //Access:RW   DataWidth:0x14   // Multi Field Register.
+  #define UCM_REG_INT_MASK_0_ADDRESS_ERROR                                                                   (0x1<<0) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.ADDRESS_ERROR .
+  #define UCM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                             0
+  #define UCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR                                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_STORM_OVFL_ERR .
+  #define UCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR_SHIFT                                                         1
+  #define UCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR                                                              (0x1<<2) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_STORM_UNDER_ERR .
+  #define UCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR_SHIFT                                                        2
+  #define UCM_REG_INT_MASK_0_IS_XSDM_OVFL_ERR                                                                (0x1<<3) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_XSDM_OVFL_ERR .
+  #define UCM_REG_INT_MASK_0_IS_XSDM_OVFL_ERR_SHIFT                                                          3
+  #define UCM_REG_INT_MASK_0_IS_XSDM_UNDER_ERR                                                               (0x1<<4) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_XSDM_UNDER_ERR .
+  #define UCM_REG_INT_MASK_0_IS_XSDM_UNDER_ERR_SHIFT                                                         4
+  #define UCM_REG_INT_MASK_0_IS_YSDM_OVFL_ERR                                                                (0x1<<5) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_YSDM_OVFL_ERR .
+  #define UCM_REG_INT_MASK_0_IS_YSDM_OVFL_ERR_SHIFT                                                          5
+  #define UCM_REG_INT_MASK_0_IS_YSDM_UNDER_ERR                                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_YSDM_UNDER_ERR .
+  #define UCM_REG_INT_MASK_0_IS_YSDM_UNDER_ERR_SHIFT                                                         6
+  #define UCM_REG_INT_MASK_0_IS_USDM_OVFL_ERR                                                                (0x1<<7) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_USDM_OVFL_ERR .
+  #define UCM_REG_INT_MASK_0_IS_USDM_OVFL_ERR_SHIFT                                                          7
+  #define UCM_REG_INT_MASK_0_IS_USDM_UNDER_ERR                                                               (0x1<<8) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_USDM_UNDER_ERR .
+  #define UCM_REG_INT_MASK_0_IS_USDM_UNDER_ERR_SHIFT                                                         8
+  #define UCM_REG_INT_MASK_0_IS_RDIF_OVFL_ERR                                                                (0x1<<9) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_RDIF_OVFL_ERR .
+  #define UCM_REG_INT_MASK_0_IS_RDIF_OVFL_ERR_SHIFT                                                          9
+  #define UCM_REG_INT_MASK_0_IS_RDIF_UNDER_ERR                                                               (0x1<<10) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_RDIF_UNDER_ERR .
+  #define UCM_REG_INT_MASK_0_IS_RDIF_UNDER_ERR_SHIFT                                                         10
+  #define UCM_REG_INT_MASK_0_IS_TDIF_OVFL_ERR                                                                (0x1<<11) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_TDIF_OVFL_ERR .
+  #define UCM_REG_INT_MASK_0_IS_TDIF_OVFL_ERR_SHIFT                                                          11
+  #define UCM_REG_INT_MASK_0_IS_TDIF_UNDER_ERR                                                               (0x1<<12) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_TDIF_UNDER_ERR .
+  #define UCM_REG_INT_MASK_0_IS_TDIF_UNDER_ERR_SHIFT                                                         12
+  #define UCM_REG_INT_MASK_0_IS_MULD_OVFL_ERR                                                                (0x1<<13) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_MULD_OVFL_ERR .
+  #define UCM_REG_INT_MASK_0_IS_MULD_OVFL_ERR_SHIFT                                                          13
+  #define UCM_REG_INT_MASK_0_IS_MULD_UNDER_ERR                                                               (0x1<<14) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_MULD_UNDER_ERR .
+  #define UCM_REG_INT_MASK_0_IS_MULD_UNDER_ERR_SHIFT                                                         14
+  #define UCM_REG_INT_MASK_0_IS_YSEM_OVFL_ERR_E5                                                             (0x1<<15) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_YSEM_OVFL_ERR .
+  #define UCM_REG_INT_MASK_0_IS_YSEM_OVFL_ERR_E5_SHIFT                                                       15
+  #define UCM_REG_INT_MASK_0_EXT_LD_UNDER_ERR_E5                                                             (0x1<<16) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.EXT_LD_UNDER_ERR .
+  #define UCM_REG_INT_MASK_0_EXT_LD_UNDER_ERR_E5_SHIFT                                                       16
+  #define UCM_REG_INT_MASK_0_EXT_LD_OVFL_ERR_E5                                                              (0x1<<17) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.EXT_LD_OVFL_ERR .
+  #define UCM_REG_INT_MASK_0_EXT_LD_OVFL_ERR_E5_SHIFT                                                        17
+  #define UCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_CON_E5                                                         (0x1<<18) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.AFFINITY_TYPE_NO_CON .
+  #define UCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_CON_E5_SHIFT                                                   18
+  #define UCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_TASK_E5                                                        (0x1<<19) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.AFFINITY_TYPE_NO_TASK .
+  #define UCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_TASK_E5_SHIFT                                                  19
+  #define UCM_REG_INT_MASK_0_IS_YULD_OVFL_ERR_BB_K2                                                          (0x1<<15) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_YULD_OVFL_ERR .
+  #define UCM_REG_INT_MASK_0_IS_YULD_OVFL_ERR_BB_K2_SHIFT                                                    15
+  #define UCM_REG_INT_MASK_0_IS_YULD_UNDER_ERR_BB_K2                                                         (0x1<<16) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_YULD_UNDER_ERR .
+  #define UCM_REG_INT_MASK_0_IS_YULD_UNDER_ERR_BB_K2_SHIFT                                                   16
+#define UCM_REG_INT_STS_WR_0                                                                                 0x1280188UL //Access:WR   DataWidth:0x14   // Multi Field Register.
+  #define UCM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                                 (0x1<<0) // Signals an unknown address to the rf module.
+  #define UCM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                           0
+  #define UCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR                                                             (0x1<<1) // Write to full STORM input buffer.
+  #define UCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR_SHIFT                                                       1
+  #define UCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR                                                            (0x1<<2) // Read from empty  STORM input buffer.
+  #define UCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR_SHIFT                                                      2
+  #define UCM_REG_INT_STS_WR_0_IS_XSDM_OVFL_ERR                                                              (0x1<<3) // Write to full XSDM input buffer.
+  #define UCM_REG_INT_STS_WR_0_IS_XSDM_OVFL_ERR_SHIFT                                                        3
+  #define UCM_REG_INT_STS_WR_0_IS_XSDM_UNDER_ERR                                                             (0x1<<4) // Read from empty XSDM input buffer.
+  #define UCM_REG_INT_STS_WR_0_IS_XSDM_UNDER_ERR_SHIFT                                                       4
+  #define UCM_REG_INT_STS_WR_0_IS_YSDM_OVFL_ERR                                                              (0x1<<5) // Write to full YSDM input buffer.
+  #define UCM_REG_INT_STS_WR_0_IS_YSDM_OVFL_ERR_SHIFT                                                        5
+  #define UCM_REG_INT_STS_WR_0_IS_YSDM_UNDER_ERR                                                             (0x1<<6) // Read from empty  YSDM input buffer.
+  #define UCM_REG_INT_STS_WR_0_IS_YSDM_UNDER_ERR_SHIFT                                                       6
+  #define UCM_REG_INT_STS_WR_0_IS_USDM_OVFL_ERR                                                              (0x1<<7) // Write to full USDM input buffer.
+  #define UCM_REG_INT_STS_WR_0_IS_USDM_OVFL_ERR_SHIFT                                                        7
+  #define UCM_REG_INT_STS_WR_0_IS_USDM_UNDER_ERR                                                             (0x1<<8) // Read from empty USDM input buffer.
+  #define UCM_REG_INT_STS_WR_0_IS_USDM_UNDER_ERR_SHIFT                                                       8
+  #define UCM_REG_INT_STS_WR_0_IS_RDIF_OVFL_ERR                                                              (0x1<<9) // Write to full RDIF input buffer.
+  #define UCM_REG_INT_STS_WR_0_IS_RDIF_OVFL_ERR_SHIFT                                                        9
+  #define UCM_REG_INT_STS_WR_0_IS_RDIF_UNDER_ERR                                                             (0x1<<10) // Read from empty RDIF input buffer.
+  #define UCM_REG_INT_STS_WR_0_IS_RDIF_UNDER_ERR_SHIFT                                                       10
+  #define UCM_REG_INT_STS_WR_0_IS_TDIF_OVFL_ERR                                                              (0x1<<11) // Write to full TDIF input buffer.
+  #define UCM_REG_INT_STS_WR_0_IS_TDIF_OVFL_ERR_SHIFT                                                        11
+  #define UCM_REG_INT_STS_WR_0_IS_TDIF_UNDER_ERR                                                             (0x1<<12) // Read from empty TDIF input buffer.
+  #define UCM_REG_INT_STS_WR_0_IS_TDIF_UNDER_ERR_SHIFT                                                       12
+  #define UCM_REG_INT_STS_WR_0_IS_MULD_OVFL_ERR                                                              (0x1<<13) // Write to full MULD input buffer.
+  #define UCM_REG_INT_STS_WR_0_IS_MULD_OVFL_ERR_SHIFT                                                        13
+  #define UCM_REG_INT_STS_WR_0_IS_MULD_UNDER_ERR                                                             (0x1<<14) // Read from empty MULD input buffer.
+  #define UCM_REG_INT_STS_WR_0_IS_MULD_UNDER_ERR_SHIFT                                                       14
+  #define UCM_REG_INT_STS_WR_0_IS_YSEM_OVFL_ERR_E5                                                           (0x1<<15) // Write to full Ysem input buffer.
+  #define UCM_REG_INT_STS_WR_0_IS_YSEM_OVFL_ERR_E5_SHIFT                                                     15
+  #define UCM_REG_INT_STS_WR_0_EXT_LD_UNDER_ERR_E5                                                           (0x1<<16) // Read from empty External read buffer.
+  #define UCM_REG_INT_STS_WR_0_EXT_LD_UNDER_ERR_E5_SHIFT                                                     16
+  #define UCM_REG_INT_STS_WR_0_EXT_LD_OVFL_ERR_E5                                                            (0x1<<17) // Write to fully External read buffer.
+  #define UCM_REG_INT_STS_WR_0_EXT_LD_OVFL_ERR_E5_SHIFT                                                      17
+  #define UCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_CON_E5                                                       (0x1<<18) // Affinity type = 2 (connection based) but connection doesn't exist.
+  #define UCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_CON_E5_SHIFT                                                 18
+  #define UCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_TASK_E5                                                      (0x1<<19) // Affinity type = 3 (task based) but task doesn't exist.
+  #define UCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_TASK_E5_SHIFT                                                19
+  #define UCM_REG_INT_STS_WR_0_IS_YULD_OVFL_ERR_BB_K2                                                        (0x1<<15) // Write to full YULD input buffer.
+  #define UCM_REG_INT_STS_WR_0_IS_YULD_OVFL_ERR_BB_K2_SHIFT                                                  15
+  #define UCM_REG_INT_STS_WR_0_IS_YULD_UNDER_ERR_BB_K2                                                       (0x1<<16) // Read from empty YULD input buffer.
+  #define UCM_REG_INT_STS_WR_0_IS_YULD_UNDER_ERR_BB_K2_SHIFT                                                 16
+#define UCM_REG_INT_STS_CLR_0                                                                                0x128018cUL //Access:RC   DataWidth:0x14   // Multi Field Register.
+  #define UCM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define UCM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                          0
+  #define UCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR                                                            (0x1<<1) // Write to full STORM input buffer.
+  #define UCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR_SHIFT                                                      1
+  #define UCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR                                                           (0x1<<2) // Read from empty  STORM input buffer.
+  #define UCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR_SHIFT                                                     2
+  #define UCM_REG_INT_STS_CLR_0_IS_XSDM_OVFL_ERR                                                             (0x1<<3) // Write to full XSDM input buffer.
+  #define UCM_REG_INT_STS_CLR_0_IS_XSDM_OVFL_ERR_SHIFT                                                       3
+  #define UCM_REG_INT_STS_CLR_0_IS_XSDM_UNDER_ERR                                                            (0x1<<4) // Read from empty XSDM input buffer.
+  #define UCM_REG_INT_STS_CLR_0_IS_XSDM_UNDER_ERR_SHIFT                                                      4
+  #define UCM_REG_INT_STS_CLR_0_IS_YSDM_OVFL_ERR                                                             (0x1<<5) // Write to full YSDM input buffer.
+  #define UCM_REG_INT_STS_CLR_0_IS_YSDM_OVFL_ERR_SHIFT                                                       5
+  #define UCM_REG_INT_STS_CLR_0_IS_YSDM_UNDER_ERR                                                            (0x1<<6) // Read from empty  YSDM input buffer.
+  #define UCM_REG_INT_STS_CLR_0_IS_YSDM_UNDER_ERR_SHIFT                                                      6
+  #define UCM_REG_INT_STS_CLR_0_IS_USDM_OVFL_ERR                                                             (0x1<<7) // Write to full USDM input buffer.
+  #define UCM_REG_INT_STS_CLR_0_IS_USDM_OVFL_ERR_SHIFT                                                       7
+  #define UCM_REG_INT_STS_CLR_0_IS_USDM_UNDER_ERR                                                            (0x1<<8) // Read from empty USDM input buffer.
+  #define UCM_REG_INT_STS_CLR_0_IS_USDM_UNDER_ERR_SHIFT                                                      8
+  #define UCM_REG_INT_STS_CLR_0_IS_RDIF_OVFL_ERR                                                             (0x1<<9) // Write to full RDIF input buffer.
+  #define UCM_REG_INT_STS_CLR_0_IS_RDIF_OVFL_ERR_SHIFT                                                       9
+  #define UCM_REG_INT_STS_CLR_0_IS_RDIF_UNDER_ERR                                                            (0x1<<10) // Read from empty RDIF input buffer.
+  #define UCM_REG_INT_STS_CLR_0_IS_RDIF_UNDER_ERR_SHIFT                                                      10
+  #define UCM_REG_INT_STS_CLR_0_IS_TDIF_OVFL_ERR                                                             (0x1<<11) // Write to full TDIF input buffer.
+  #define UCM_REG_INT_STS_CLR_0_IS_TDIF_OVFL_ERR_SHIFT                                                       11
+  #define UCM_REG_INT_STS_CLR_0_IS_TDIF_UNDER_ERR                                                            (0x1<<12) // Read from empty TDIF input buffer.
+  #define UCM_REG_INT_STS_CLR_0_IS_TDIF_UNDER_ERR_SHIFT                                                      12
+  #define UCM_REG_INT_STS_CLR_0_IS_MULD_OVFL_ERR                                                             (0x1<<13) // Write to full MULD input buffer.
+  #define UCM_REG_INT_STS_CLR_0_IS_MULD_OVFL_ERR_SHIFT                                                       13
+  #define UCM_REG_INT_STS_CLR_0_IS_MULD_UNDER_ERR                                                            (0x1<<14) // Read from empty MULD input buffer.
+  #define UCM_REG_INT_STS_CLR_0_IS_MULD_UNDER_ERR_SHIFT                                                      14
+  #define UCM_REG_INT_STS_CLR_0_IS_YSEM_OVFL_ERR_E5                                                          (0x1<<15) // Write to full Ysem input buffer.
+  #define UCM_REG_INT_STS_CLR_0_IS_YSEM_OVFL_ERR_E5_SHIFT                                                    15
+  #define UCM_REG_INT_STS_CLR_0_EXT_LD_UNDER_ERR_E5                                                          (0x1<<16) // Read from empty External read buffer.
+  #define UCM_REG_INT_STS_CLR_0_EXT_LD_UNDER_ERR_E5_SHIFT                                                    16
+  #define UCM_REG_INT_STS_CLR_0_EXT_LD_OVFL_ERR_E5                                                           (0x1<<17) // Write to fully External read buffer.
+  #define UCM_REG_INT_STS_CLR_0_EXT_LD_OVFL_ERR_E5_SHIFT                                                     17
+  #define UCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_CON_E5                                                      (0x1<<18) // Affinity type = 2 (connection based) but connection doesn't exist.
+  #define UCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_CON_E5_SHIFT                                                18
+  #define UCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_TASK_E5                                                     (0x1<<19) // Affinity type = 3 (task based) but task doesn't exist.
+  #define UCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_TASK_E5_SHIFT                                               19
+  #define UCM_REG_INT_STS_CLR_0_IS_YULD_OVFL_ERR_BB_K2                                                       (0x1<<15) // Write to full YULD input buffer.
+  #define UCM_REG_INT_STS_CLR_0_IS_YULD_OVFL_ERR_BB_K2_SHIFT                                                 15
+  #define UCM_REG_INT_STS_CLR_0_IS_YULD_UNDER_ERR_BB_K2                                                      (0x1<<16) // Read from empty YULD input buffer.
+  #define UCM_REG_INT_STS_CLR_0_IS_YULD_UNDER_ERR_BB_K2_SHIFT                                                16
+#define UCM_REG_INT_STS_1                                                                                    0x1280190UL //Access:R    DataWidth:0x1e   // Multi Field Register.
+  #define UCM_REG_INT_STS_1_IS_YSEM_UNDER_ERR_E5                                                             (0x1<<0) // Read from empty  Ysem input buffer.
+  #define UCM_REG_INT_STS_1_IS_YSEM_UNDER_ERR_E5_SHIFT                                                       0
+  #define UCM_REG_INT_STS_1_IS_DORQ_OVFL_ERR_BB_K2                                                           (0x1<<0) // Write to full Dorq input buffer.
+  #define UCM_REG_INT_STS_1_IS_DORQ_OVFL_ERR_BB_K2_SHIFT                                                     0
+  #define UCM_REG_INT_STS_1_IS_DORQ_OVFL_ERR_E5                                                              (0x1<<1) // Write to full Dorq input buffer.
+  #define UCM_REG_INT_STS_1_IS_DORQ_OVFL_ERR_E5_SHIFT                                                        1
+  #define UCM_REG_INT_STS_1_IS_DORQ_UNDER_ERR_BB_K2                                                          (0x1<<1) // Read from empty  Dorq input buffer.
+  #define UCM_REG_INT_STS_1_IS_DORQ_UNDER_ERR_BB_K2_SHIFT                                                    1
+  #define UCM_REG_INT_STS_1_IS_DORQ_UNDER_ERR_E5                                                             (0x1<<2) // Read from empty  Dorq input buffer.
+  #define UCM_REG_INT_STS_1_IS_DORQ_UNDER_ERR_E5_SHIFT                                                       2
+  #define UCM_REG_INT_STS_1_IS_PBF_OVFL_ERR_BB_K2                                                            (0x1<<2) // Write to full Pbf input buffer.
+  #define UCM_REG_INT_STS_1_IS_PBF_OVFL_ERR_BB_K2_SHIFT                                                      2
+  #define UCM_REG_INT_STS_1_IS_PBF_OVFL_ERR_E5                                                               (0x1<<3) // Write to full Pbf input buffer.
+  #define UCM_REG_INT_STS_1_IS_PBF_OVFL_ERR_E5_SHIFT                                                         3
+  #define UCM_REG_INT_STS_1_IS_PBF_UNDER_ERR_BB_K2                                                           (0x1<<3) // Read from empty Pbf input buffer.
+  #define UCM_REG_INT_STS_1_IS_PBF_UNDER_ERR_BB_K2_SHIFT                                                     3
+  #define UCM_REG_INT_STS_1_IS_PBF_UNDER_ERR_E5                                                              (0x1<<4) // Read from empty Pbf input buffer.
+  #define UCM_REG_INT_STS_1_IS_PBF_UNDER_ERR_E5_SHIFT                                                        4
+  #define UCM_REG_INT_STS_1_IS_TM_OVFL_ERR_BB_K2                                                             (0x1<<4) // Write to full TM input buffer.
+  #define UCM_REG_INT_STS_1_IS_TM_OVFL_ERR_BB_K2_SHIFT                                                       4
+  #define UCM_REG_INT_STS_1_IS_TM_OVFL_ERR_E5                                                                (0x1<<5) // Write to full TM input buffer.
+  #define UCM_REG_INT_STS_1_IS_TM_OVFL_ERR_E5_SHIFT                                                          5
+  #define UCM_REG_INT_STS_1_IS_TM_UNDER_ERR_BB_K2                                                            (0x1<<5) // Read from empty TM input buffer.
+  #define UCM_REG_INT_STS_1_IS_TM_UNDER_ERR_BB_K2_SHIFT                                                      5
+  #define UCM_REG_INT_STS_1_IS_TM_UNDER_ERR_E5                                                               (0x1<<6) // Read from empty TM input buffer.
+  #define UCM_REG_INT_STS_1_IS_TM_UNDER_ERR_E5_SHIFT                                                         6
+  #define UCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR_BB_K2                                                           (0x1<<6) // Write to full QM input buffer.
+  #define UCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR_BB_K2_SHIFT                                                     6
+  #define UCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR_E5                                                              (0x1<<7) // Write to full QM input buffer.
+  #define UCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR_E5_SHIFT                                                        7
+  #define UCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR_BB_K2                                                          (0x1<<7) // Read from empty QM input buffer.
+  #define UCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR_BB_K2_SHIFT                                                    7
+  #define UCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR_E5                                                             (0x1<<8) // Read from empty QM input buffer.
+  #define UCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR_E5_SHIFT                                                       8
+  #define UCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR_BB_K2                                                           (0x1<<8) // Write to full QM input buffer.
+  #define UCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR_BB_K2_SHIFT                                                     8
+  #define UCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR_E5                                                              (0x1<<9) // Write to full QM input buffer.
+  #define UCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR_E5_SHIFT                                                        9
+  #define UCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR_BB_K2                                                          (0x1<<9) // Read from empty QM input buffer.
+  #define UCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR_BB_K2_SHIFT                                                    9
+  #define UCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR_E5                                                             (0x1<<10) // Read from empty QM input buffer.
+  #define UCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR_E5_SHIFT                                                       10
+  #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0_BB_K2                                                           (0x1<<10) // Write to full GRC input buffer bits [31:0].
+  #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0_BB_K2_SHIFT                                                     10
+  #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0_E5                                                              (0x1<<11) // Write to full GRC input buffer bits [31:0].
+  #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0_E5_SHIFT                                                        11
+  #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0_BB_K2                                                          (0x1<<11) // Read from empty  GRC input buffer bits [31:0].
+  #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0_BB_K2_SHIFT                                                    11
+  #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0_E5                                                             (0x1<<12) // Read from empty  GRC input buffer bits [31:0].
+  #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0_E5_SHIFT                                                       12
+  #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1_BB_K2                                                           (0x1<<12) // Write to full GRC input buffer bits [63:32].
+  #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1_BB_K2_SHIFT                                                     12
+  #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1_E5                                                              (0x1<<13) // Write to full GRC input buffer bits [63:32].
+  #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1_E5_SHIFT                                                        13
+  #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1_BB_K2                                                          (0x1<<13) // Read from empty  GRC input buffer bits [63:32].
+  #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1_BB_K2_SHIFT                                                    13
+  #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1_E5                                                             (0x1<<14) // Read from empty  GRC input buffer bits [63:32].
+  #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1_E5_SHIFT                                                       14
+  #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2_BB_K2                                                           (0x1<<14) // Write to full GRC input buffer bits [95:64].
+  #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2_BB_K2_SHIFT                                                     14
+  #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2_E5                                                              (0x1<<15) // Write to full GRC input buffer bits [95:64].
+  #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2_E5_SHIFT                                                        15
+  #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2_BB_K2                                                          (0x1<<15) // Read from empty  GRC input buffer bits [95:64].
+  #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2_BB_K2_SHIFT                                                    15
+  #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2_E5                                                             (0x1<<16) // Read from empty  GRC input buffer bits [95:64].
+  #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2_E5_SHIFT                                                       16
+  #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3_BB_K2                                                           (0x1<<16) // Write to full GRC input buffer bits [127:96].
+  #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3_BB_K2_SHIFT                                                     16
+  #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3_E5                                                              (0x1<<17) // Write to full GRC input buffer bits [127:96].
+  #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3_E5_SHIFT                                                        17
+  #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3_BB_K2                                                          (0x1<<17) // Read from empty  GRC input buffer bits [127:96].
+  #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3_BB_K2_SHIFT                                                    17
+  #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3_E5                                                             (0x1<<18) // Read from empty  GRC input buffer bits [127:96].
+  #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3_E5_SHIFT                                                       18
+  #define UCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL_BB_K2                                                           (0x1<<18) // In-process Table overflow.
+  #define UCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL_BB_K2_SHIFT                                                     18
+  #define UCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL_E5                                                              (0x1<<19) // In-process Table overflow.
+  #define UCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL_E5_SHIFT                                                        19
+  #define UCM_REG_INT_STS_1_AGG_CON_DATA_BUF_OVFL_BB_K2                                                      (0x1<<19) // Message Processor Aggregation Connection Data buffer overflow.
+  #define UCM_REG_INT_STS_1_AGG_CON_DATA_BUF_OVFL_BB_K2_SHIFT                                                19
+  #define UCM_REG_INT_STS_1_AGG_CON_DATA_BUF_OVFL_E5                                                         (0x1<<20) // Message Processor Aggregation Connection Data buffer overflow.
+  #define UCM_REG_INT_STS_1_AGG_CON_DATA_BUF_OVFL_E5_SHIFT                                                   20
+  #define UCM_REG_INT_STS_1_AGG_CON_CMD_BUF_OVFL_BB_K2                                                       (0x1<<20) // Message Processor Aggregation Connection Command buffer overflow.
+  #define UCM_REG_INT_STS_1_AGG_CON_CMD_BUF_OVFL_BB_K2_SHIFT                                                 20
+  #define UCM_REG_INT_STS_1_AGG_CON_CMD_BUF_OVFL_E5                                                          (0x1<<21) // Message Processor Aggregation Connection Command buffer overflow.
+  #define UCM_REG_INT_STS_1_AGG_CON_CMD_BUF_OVFL_E5_SHIFT                                                    21
+  #define UCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL_BB_K2                                                       (0x1<<21) // Message Processor Storm Connection Data buffer overflow.
+  #define UCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL_BB_K2_SHIFT                                                 21
+  #define UCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL_E5                                                          (0x1<<22) // Message Processor Storm Connection Data buffer overflow.
+  #define UCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL_E5_SHIFT                                                    22
+  #define UCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL_BB_K2                                                        (0x1<<22) // Message Processor Storm Connection Command buffer overflow.
+  #define UCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL_BB_K2_SHIFT                                                  22
+  #define UCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL_E5                                                           (0x1<<23) // Message Processor Storm Connection Command buffer overflow.
+  #define UCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL_E5_SHIFT                                                     23
+  #define UCM_REG_INT_STS_1_AGG_TASK_DATA_BUF_OVFL_BB_K2                                                     (0x1<<23) // Message Processor Aggregation Task Data buffer overflow.
+  #define UCM_REG_INT_STS_1_AGG_TASK_DATA_BUF_OVFL_BB_K2_SHIFT                                               23
+  #define UCM_REG_INT_STS_1_AGG_TASK_DATA_BUF_OVFL_E5                                                        (0x1<<24) // Message Processor Aggregation Task Data buffer overflow.
+  #define UCM_REG_INT_STS_1_AGG_TASK_DATA_BUF_OVFL_E5_SHIFT                                                  24
+  #define UCM_REG_INT_STS_1_AGG_TASK_CMD_BUF_OVFL_BB_K2                                                      (0x1<<24) // Message Processor Aggregation Task Command buffer overflow.
+  #define UCM_REG_INT_STS_1_AGG_TASK_CMD_BUF_OVFL_BB_K2_SHIFT                                                24
+  #define UCM_REG_INT_STS_1_AGG_TASK_CMD_BUF_OVFL_E5                                                         (0x1<<25) // Message Processor Aggregation Task Command buffer overflow.
+  #define UCM_REG_INT_STS_1_AGG_TASK_CMD_BUF_OVFL_E5_SHIFT                                                   25
+  #define UCM_REG_INT_STS_1_SM_TASK_DATA_BUF_OVFL_BB_K2                                                      (0x1<<25) // Message Processor Storm Task Data buffer overflow.
+  #define UCM_REG_INT_STS_1_SM_TASK_DATA_BUF_OVFL_BB_K2_SHIFT                                                25
+  #define UCM_REG_INT_STS_1_SM_TASK_DATA_BUF_OVFL_E5                                                         (0x1<<26) // Message Processor Storm Task Data buffer overflow.
+  #define UCM_REG_INT_STS_1_SM_TASK_DATA_BUF_OVFL_E5_SHIFT                                                   26
+  #define UCM_REG_INT_STS_1_SM_TASK_CMD_BUF_OVFL_BB_K2                                                       (0x1<<26) // Message Processor Storm Task Command buffer overflow.
+  #define UCM_REG_INT_STS_1_SM_TASK_CMD_BUF_OVFL_BB_K2_SHIFT                                                 26
+  #define UCM_REG_INT_STS_1_SM_TASK_CMD_BUF_OVFL_E5                                                          (0x1<<27) // Message Processor Storm Task Command buffer overflow.
+  #define UCM_REG_INT_STS_1_SM_TASK_CMD_BUF_OVFL_E5_SHIFT                                                    27
+  #define UCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE_BB_K2                                                      (0x1<<27) // Input message first descriptor fields violation.
+  #define UCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE_BB_K2_SHIFT                                                27
+  #define UCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE_E5                                                         (0x1<<28) // Input message first descriptor fields violation.
+  #define UCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE_E5_SHIFT                                                   28
+  #define UCM_REG_INT_STS_1_SE_DESC_INPUT_VIOLATE_BB_K2                                                      (0x1<<28) // Input message second descriptor fields violation.
+  #define UCM_REG_INT_STS_1_SE_DESC_INPUT_VIOLATE_BB_K2_SHIFT                                                28
+  #define UCM_REG_INT_STS_1_SE_DESC_INPUT_VIOLATE_E5                                                         (0x1<<29) // Input message second descriptor fields violation.
+  #define UCM_REG_INT_STS_1_SE_DESC_INPUT_VIOLATE_E5_SHIFT                                                   29
+#define UCM_REG_INT_MASK_1                                                                                   0x1280194UL //Access:RW   DataWidth:0x1e   // Multi Field Register.
+  #define UCM_REG_INT_MASK_1_IS_YSEM_UNDER_ERR_E5                                                            (0x1<<0) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_YSEM_UNDER_ERR .
+  #define UCM_REG_INT_MASK_1_IS_YSEM_UNDER_ERR_E5_SHIFT                                                      0
+  #define UCM_REG_INT_MASK_1_IS_DORQ_OVFL_ERR_BB_K2                                                          (0x1<<0) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_DORQ_OVFL_ERR .
+  #define UCM_REG_INT_MASK_1_IS_DORQ_OVFL_ERR_BB_K2_SHIFT                                                    0
+  #define UCM_REG_INT_MASK_1_IS_DORQ_OVFL_ERR_E5                                                             (0x1<<1) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_DORQ_OVFL_ERR .
+  #define UCM_REG_INT_MASK_1_IS_DORQ_OVFL_ERR_E5_SHIFT                                                       1
+  #define UCM_REG_INT_MASK_1_IS_DORQ_UNDER_ERR_BB_K2                                                         (0x1<<1) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_DORQ_UNDER_ERR .
+  #define UCM_REG_INT_MASK_1_IS_DORQ_UNDER_ERR_BB_K2_SHIFT                                                   1
+  #define UCM_REG_INT_MASK_1_IS_DORQ_UNDER_ERR_E5                                                            (0x1<<2) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_DORQ_UNDER_ERR .
+  #define UCM_REG_INT_MASK_1_IS_DORQ_UNDER_ERR_E5_SHIFT                                                      2
+  #define UCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR_BB_K2                                                           (0x1<<2) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_PBF_OVFL_ERR .
+  #define UCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR_BB_K2_SHIFT                                                     2
+  #define UCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR_E5                                                              (0x1<<3) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_PBF_OVFL_ERR .
+  #define UCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR_E5_SHIFT                                                        3
+  #define UCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR_BB_K2                                                          (0x1<<3) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_PBF_UNDER_ERR .
+  #define UCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR_BB_K2_SHIFT                                                    3
+  #define UCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR_E5                                                             (0x1<<4) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_PBF_UNDER_ERR .
+  #define UCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR_E5_SHIFT                                                       4
+  #define UCM_REG_INT_MASK_1_IS_TM_OVFL_ERR_BB_K2                                                            (0x1<<4) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_TM_OVFL_ERR .
+  #define UCM_REG_INT_MASK_1_IS_TM_OVFL_ERR_BB_K2_SHIFT                                                      4
+  #define UCM_REG_INT_MASK_1_IS_TM_OVFL_ERR_E5                                                               (0x1<<5) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_TM_OVFL_ERR .
+  #define UCM_REG_INT_MASK_1_IS_TM_OVFL_ERR_E5_SHIFT                                                         5
+  #define UCM_REG_INT_MASK_1_IS_TM_UNDER_ERR_BB_K2                                                           (0x1<<5) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_TM_UNDER_ERR .
+  #define UCM_REG_INT_MASK_1_IS_TM_UNDER_ERR_BB_K2_SHIFT                                                     5
+  #define UCM_REG_INT_MASK_1_IS_TM_UNDER_ERR_E5                                                              (0x1<<6) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_TM_UNDER_ERR .
+  #define UCM_REG_INT_MASK_1_IS_TM_UNDER_ERR_E5_SHIFT                                                        6
+  #define UCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR_BB_K2                                                          (0x1<<6) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_QM_P_OVFL_ERR .
+  #define UCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR_BB_K2_SHIFT                                                    6
+  #define UCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR_E5                                                             (0x1<<7) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_QM_P_OVFL_ERR .
+  #define UCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR_E5_SHIFT                                                       7
+  #define UCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR_BB_K2                                                         (0x1<<7) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_QM_P_UNDER_ERR .
+  #define UCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR_BB_K2_SHIFT                                                   7
+  #define UCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR_E5                                                            (0x1<<8) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_QM_P_UNDER_ERR .
+  #define UCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR_E5_SHIFT                                                      8
+  #define UCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR_BB_K2                                                          (0x1<<8) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_QM_S_OVFL_ERR .
+  #define UCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR_BB_K2_SHIFT                                                    8
+  #define UCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR_E5                                                             (0x1<<9) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_QM_S_OVFL_ERR .
+  #define UCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR_E5_SHIFT                                                       9
+  #define UCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR_BB_K2                                                         (0x1<<9) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_QM_S_UNDER_ERR .
+  #define UCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR_BB_K2_SHIFT                                                   9
+  #define UCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR_E5                                                            (0x1<<10) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_QM_S_UNDER_ERR .
+  #define UCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR_E5_SHIFT                                                      10
+  #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0_BB_K2                                                          (0x1<<10) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_OVFL_ERR0 .
+  #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0_BB_K2_SHIFT                                                    10
+  #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0_E5                                                             (0x1<<11) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_OVFL_ERR0 .
+  #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0_E5_SHIFT                                                       11
+  #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0_BB_K2                                                         (0x1<<11) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_UNDER_ERR0 .
+  #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0_BB_K2_SHIFT                                                   11
+  #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0_E5                                                            (0x1<<12) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_UNDER_ERR0 .
+  #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0_E5_SHIFT                                                      12
+  #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1_BB_K2                                                          (0x1<<12) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_OVFL_ERR1 .
+  #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1_BB_K2_SHIFT                                                    12
+  #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1_E5                                                             (0x1<<13) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_OVFL_ERR1 .
+  #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1_E5_SHIFT                                                       13
+  #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1_BB_K2                                                         (0x1<<13) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_UNDER_ERR1 .
+  #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1_BB_K2_SHIFT                                                   13
+  #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1_E5                                                            (0x1<<14) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_UNDER_ERR1 .
+  #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1_E5_SHIFT                                                      14
+  #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2_BB_K2                                                          (0x1<<14) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_OVFL_ERR2 .
+  #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2_BB_K2_SHIFT                                                    14
+  #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2_E5                                                             (0x1<<15) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_OVFL_ERR2 .
+  #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2_E5_SHIFT                                                       15
+  #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2_BB_K2                                                         (0x1<<15) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_UNDER_ERR2 .
+  #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2_BB_K2_SHIFT                                                   15
+  #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2_E5                                                            (0x1<<16) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_UNDER_ERR2 .
+  #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2_E5_SHIFT                                                      16
+  #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3_BB_K2                                                          (0x1<<16) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_OVFL_ERR3 .
+  #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3_BB_K2_SHIFT                                                    16
+  #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3_E5                                                             (0x1<<17) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_OVFL_ERR3 .
+  #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3_E5_SHIFT                                                       17
+  #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3_BB_K2                                                         (0x1<<17) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_UNDER_ERR3 .
+  #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3_BB_K2_SHIFT                                                   17
+  #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3_E5                                                            (0x1<<18) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_UNDER_ERR3 .
+  #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3_E5_SHIFT                                                      18
+  #define UCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL_BB_K2                                                          (0x1<<18) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IN_PRCS_TBL_OVFL .
+  #define UCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL_BB_K2_SHIFT                                                    18
+  #define UCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL_E5                                                             (0x1<<19) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IN_PRCS_TBL_OVFL .
+  #define UCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL_E5_SHIFT                                                       19
+  #define UCM_REG_INT_MASK_1_AGG_CON_DATA_BUF_OVFL_BB_K2                                                     (0x1<<19) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.AGG_CON_DATA_BUF_OVFL .
+  #define UCM_REG_INT_MASK_1_AGG_CON_DATA_BUF_OVFL_BB_K2_SHIFT                                               19
+  #define UCM_REG_INT_MASK_1_AGG_CON_DATA_BUF_OVFL_E5                                                        (0x1<<20) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.AGG_CON_DATA_BUF_OVFL .
+  #define UCM_REG_INT_MASK_1_AGG_CON_DATA_BUF_OVFL_E5_SHIFT                                                  20
+  #define UCM_REG_INT_MASK_1_AGG_CON_CMD_BUF_OVFL_BB_K2                                                      (0x1<<20) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.AGG_CON_CMD_BUF_OVFL .
+  #define UCM_REG_INT_MASK_1_AGG_CON_CMD_BUF_OVFL_BB_K2_SHIFT                                                20
+  #define UCM_REG_INT_MASK_1_AGG_CON_CMD_BUF_OVFL_E5                                                         (0x1<<21) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.AGG_CON_CMD_BUF_OVFL .
+  #define UCM_REG_INT_MASK_1_AGG_CON_CMD_BUF_OVFL_E5_SHIFT                                                   21
+  #define UCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL_BB_K2                                                      (0x1<<21) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.SM_CON_DATA_BUF_OVFL .
+  #define UCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL_BB_K2_SHIFT                                                21
+  #define UCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL_E5                                                         (0x1<<22) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.SM_CON_DATA_BUF_OVFL .
+  #define UCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL_E5_SHIFT                                                   22
+  #define UCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL_BB_K2                                                       (0x1<<22) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.SM_CON_CMD_BUF_OVFL .
+  #define UCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL_BB_K2_SHIFT                                                 22
+  #define UCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL_E5                                                          (0x1<<23) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.SM_CON_CMD_BUF_OVFL .
+  #define UCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL_E5_SHIFT                                                    23
+  #define UCM_REG_INT_MASK_1_AGG_TASK_DATA_BUF_OVFL_BB_K2                                                    (0x1<<23) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.AGG_TASK_DATA_BUF_OVFL .
+  #define UCM_REG_INT_MASK_1_AGG_TASK_DATA_BUF_OVFL_BB_K2_SHIFT                                              23
+  #define UCM_REG_INT_MASK_1_AGG_TASK_DATA_BUF_OVFL_E5                                                       (0x1<<24) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.AGG_TASK_DATA_BUF_OVFL .
+  #define UCM_REG_INT_MASK_1_AGG_TASK_DATA_BUF_OVFL_E5_SHIFT                                                 24
+  #define UCM_REG_INT_MASK_1_AGG_TASK_CMD_BUF_OVFL_BB_K2                                                     (0x1<<24) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.AGG_TASK_CMD_BUF_OVFL .
+  #define UCM_REG_INT_MASK_1_AGG_TASK_CMD_BUF_OVFL_BB_K2_SHIFT                                               24
+  #define UCM_REG_INT_MASK_1_AGG_TASK_CMD_BUF_OVFL_E5                                                        (0x1<<25) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.AGG_TASK_CMD_BUF_OVFL .
+  #define UCM_REG_INT_MASK_1_AGG_TASK_CMD_BUF_OVFL_E5_SHIFT                                                  25
+  #define UCM_REG_INT_MASK_1_SM_TASK_DATA_BUF_OVFL_BB_K2                                                     (0x1<<25) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.SM_TASK_DATA_BUF_OVFL .
+  #define UCM_REG_INT_MASK_1_SM_TASK_DATA_BUF_OVFL_BB_K2_SHIFT                                               25
+  #define UCM_REG_INT_MASK_1_SM_TASK_DATA_BUF_OVFL_E5                                                        (0x1<<26) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.SM_TASK_DATA_BUF_OVFL .
+  #define UCM_REG_INT_MASK_1_SM_TASK_DATA_BUF_OVFL_E5_SHIFT                                                  26
+  #define UCM_REG_INT_MASK_1_SM_TASK_CMD_BUF_OVFL_BB_K2                                                      (0x1<<26) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.SM_TASK_CMD_BUF_OVFL .
+  #define UCM_REG_INT_MASK_1_SM_TASK_CMD_BUF_OVFL_BB_K2_SHIFT                                                26
+  #define UCM_REG_INT_MASK_1_SM_TASK_CMD_BUF_OVFL_E5                                                         (0x1<<27) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.SM_TASK_CMD_BUF_OVFL .
+  #define UCM_REG_INT_MASK_1_SM_TASK_CMD_BUF_OVFL_E5_SHIFT                                                   27
+  #define UCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE_BB_K2                                                     (0x1<<27) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.FI_DESC_INPUT_VIOLATE .
+  #define UCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE_BB_K2_SHIFT                                               27
+  #define UCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE_E5                                                        (0x1<<28) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.FI_DESC_INPUT_VIOLATE .
+  #define UCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE_E5_SHIFT                                                  28
+  #define UCM_REG_INT_MASK_1_SE_DESC_INPUT_VIOLATE_BB_K2                                                     (0x1<<28) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.SE_DESC_INPUT_VIOLATE .
+  #define UCM_REG_INT_MASK_1_SE_DESC_INPUT_VIOLATE_BB_K2_SHIFT                                               28
+  #define UCM_REG_INT_MASK_1_SE_DESC_INPUT_VIOLATE_E5                                                        (0x1<<29) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.SE_DESC_INPUT_VIOLATE .
+  #define UCM_REG_INT_MASK_1_SE_DESC_INPUT_VIOLATE_E5_SHIFT                                                  29
+#define UCM_REG_INT_STS_WR_1                                                                                 0x1280198UL //Access:WR   DataWidth:0x1e   // Multi Field Register.
+  #define UCM_REG_INT_STS_WR_1_IS_YSEM_UNDER_ERR_E5                                                          (0x1<<0) // Read from empty  Ysem input buffer.
+  #define UCM_REG_INT_STS_WR_1_IS_YSEM_UNDER_ERR_E5_SHIFT                                                    0
+  #define UCM_REG_INT_STS_WR_1_IS_DORQ_OVFL_ERR_BB_K2                                                        (0x1<<0) // Write to full Dorq input buffer.
+  #define UCM_REG_INT_STS_WR_1_IS_DORQ_OVFL_ERR_BB_K2_SHIFT                                                  0
+  #define UCM_REG_INT_STS_WR_1_IS_DORQ_OVFL_ERR_E5                                                           (0x1<<1) // Write to full Dorq input buffer.
+  #define UCM_REG_INT_STS_WR_1_IS_DORQ_OVFL_ERR_E5_SHIFT                                                     1
+  #define UCM_REG_INT_STS_WR_1_IS_DORQ_UNDER_ERR_BB_K2                                                       (0x1<<1) // Read from empty  Dorq input buffer.
+  #define UCM_REG_INT_STS_WR_1_IS_DORQ_UNDER_ERR_BB_K2_SHIFT                                                 1
+  #define UCM_REG_INT_STS_WR_1_IS_DORQ_UNDER_ERR_E5                                                          (0x1<<2) // Read from empty  Dorq input buffer.
+  #define UCM_REG_INT_STS_WR_1_IS_DORQ_UNDER_ERR_E5_SHIFT                                                    2
+  #define UCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR_BB_K2                                                         (0x1<<2) // Write to full Pbf input buffer.
+  #define UCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR_BB_K2_SHIFT                                                   2
+  #define UCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR_E5                                                            (0x1<<3) // Write to full Pbf input buffer.
+  #define UCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR_E5_SHIFT                                                      3
+  #define UCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR_BB_K2                                                        (0x1<<3) // Read from empty Pbf input buffer.
+  #define UCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR_BB_K2_SHIFT                                                  3
+  #define UCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR_E5                                                           (0x1<<4) // Read from empty Pbf input buffer.
+  #define UCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR_E5_SHIFT                                                     4
+  #define UCM_REG_INT_STS_WR_1_IS_TM_OVFL_ERR_BB_K2                                                          (0x1<<4) // Write to full TM input buffer.
+  #define UCM_REG_INT_STS_WR_1_IS_TM_OVFL_ERR_BB_K2_SHIFT                                                    4
+  #define UCM_REG_INT_STS_WR_1_IS_TM_OVFL_ERR_E5                                                             (0x1<<5) // Write to full TM input buffer.
+  #define UCM_REG_INT_STS_WR_1_IS_TM_OVFL_ERR_E5_SHIFT                                                       5
+  #define UCM_REG_INT_STS_WR_1_IS_TM_UNDER_ERR_BB_K2                                                         (0x1<<5) // Read from empty TM input buffer.
+  #define UCM_REG_INT_STS_WR_1_IS_TM_UNDER_ERR_BB_K2_SHIFT                                                   5
+  #define UCM_REG_INT_STS_WR_1_IS_TM_UNDER_ERR_E5                                                            (0x1<<6) // Read from empty TM input buffer.
+  #define UCM_REG_INT_STS_WR_1_IS_TM_UNDER_ERR_E5_SHIFT                                                      6
+  #define UCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR_BB_K2                                                        (0x1<<6) // Write to full QM input buffer.
+  #define UCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR_BB_K2_SHIFT                                                  6
+  #define UCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR_E5                                                           (0x1<<7) // Write to full QM input buffer.
+  #define UCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR_E5_SHIFT                                                     7
+  #define UCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR_BB_K2                                                       (0x1<<7) // Read from empty QM input buffer.
+  #define UCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR_BB_K2_SHIFT                                                 7
+  #define UCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR_E5                                                          (0x1<<8) // Read from empty QM input buffer.
+  #define UCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR_E5_SHIFT                                                    8
+  #define UCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR_BB_K2                                                        (0x1<<8) // Write to full QM input buffer.
+  #define UCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR_BB_K2_SHIFT                                                  8
+  #define UCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR_E5                                                           (0x1<<9) // Write to full QM input buffer.
+  #define UCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR_E5_SHIFT                                                     9
+  #define UCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR_BB_K2                                                       (0x1<<9) // Read from empty QM input buffer.
+  #define UCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR_BB_K2_SHIFT                                                 9
+  #define UCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR_E5                                                          (0x1<<10) // Read from empty QM input buffer.
+  #define UCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR_E5_SHIFT                                                    10
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0_BB_K2                                                        (0x1<<10) // Write to full GRC input buffer bits [31:0].
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0_BB_K2_SHIFT                                                  10
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0_E5                                                           (0x1<<11) // Write to full GRC input buffer bits [31:0].
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0_E5_SHIFT                                                     11
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0_BB_K2                                                       (0x1<<11) // Read from empty  GRC input buffer bits [31:0].
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0_BB_K2_SHIFT                                                 11
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0_E5                                                          (0x1<<12) // Read from empty  GRC input buffer bits [31:0].
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0_E5_SHIFT                                                    12
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1_BB_K2                                                        (0x1<<12) // Write to full GRC input buffer bits [63:32].
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1_BB_K2_SHIFT                                                  12
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1_E5                                                           (0x1<<13) // Write to full GRC input buffer bits [63:32].
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1_E5_SHIFT                                                     13
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1_BB_K2                                                       (0x1<<13) // Read from empty  GRC input buffer bits [63:32].
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1_BB_K2_SHIFT                                                 13
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1_E5                                                          (0x1<<14) // Read from empty  GRC input buffer bits [63:32].
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1_E5_SHIFT                                                    14
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2_BB_K2                                                        (0x1<<14) // Write to full GRC input buffer bits [95:64].
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2_BB_K2_SHIFT                                                  14
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2_E5                                                           (0x1<<15) // Write to full GRC input buffer bits [95:64].
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2_E5_SHIFT                                                     15
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2_BB_K2                                                       (0x1<<15) // Read from empty  GRC input buffer bits [95:64].
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2_BB_K2_SHIFT                                                 15
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2_E5                                                          (0x1<<16) // Read from empty  GRC input buffer bits [95:64].
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2_E5_SHIFT                                                    16
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3_BB_K2                                                        (0x1<<16) // Write to full GRC input buffer bits [127:96].
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3_BB_K2_SHIFT                                                  16
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3_E5                                                           (0x1<<17) // Write to full GRC input buffer bits [127:96].
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3_E5_SHIFT                                                     17
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3_BB_K2                                                       (0x1<<17) // Read from empty  GRC input buffer bits [127:96].
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3_BB_K2_SHIFT                                                 17
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3_E5                                                          (0x1<<18) // Read from empty  GRC input buffer bits [127:96].
+  #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3_E5_SHIFT                                                    18
+  #define UCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL_BB_K2                                                        (0x1<<18) // In-process Table overflow.
+  #define UCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL_BB_K2_SHIFT                                                  18
+  #define UCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL_E5                                                           (0x1<<19) // In-process Table overflow.
+  #define UCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL_E5_SHIFT                                                     19
+  #define UCM_REG_INT_STS_WR_1_AGG_CON_DATA_BUF_OVFL_BB_K2                                                   (0x1<<19) // Message Processor Aggregation Connection Data buffer overflow.
+  #define UCM_REG_INT_STS_WR_1_AGG_CON_DATA_BUF_OVFL_BB_K2_SHIFT                                             19
+  #define UCM_REG_INT_STS_WR_1_AGG_CON_DATA_BUF_OVFL_E5                                                      (0x1<<20) // Message Processor Aggregation Connection Data buffer overflow.
+  #define UCM_REG_INT_STS_WR_1_AGG_CON_DATA_BUF_OVFL_E5_SHIFT                                                20
+  #define UCM_REG_INT_STS_WR_1_AGG_CON_CMD_BUF_OVFL_BB_K2                                                    (0x1<<20) // Message Processor Aggregation Connection Command buffer overflow.
+  #define UCM_REG_INT_STS_WR_1_AGG_CON_CMD_BUF_OVFL_BB_K2_SHIFT                                              20
+  #define UCM_REG_INT_STS_WR_1_AGG_CON_CMD_BUF_OVFL_E5                                                       (0x1<<21) // Message Processor Aggregation Connection Command buffer overflow.
+  #define UCM_REG_INT_STS_WR_1_AGG_CON_CMD_BUF_OVFL_E5_SHIFT                                                 21
+  #define UCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL_BB_K2                                                    (0x1<<21) // Message Processor Storm Connection Data buffer overflow.
+  #define UCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL_BB_K2_SHIFT                                              21
+  #define UCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL_E5                                                       (0x1<<22) // Message Processor Storm Connection Data buffer overflow.
+  #define UCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL_E5_SHIFT                                                 22
+  #define UCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL_BB_K2                                                     (0x1<<22) // Message Processor Storm Connection Command buffer overflow.
+  #define UCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL_BB_K2_SHIFT                                               22
+  #define UCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL_E5                                                        (0x1<<23) // Message Processor Storm Connection Command buffer overflow.
+  #define UCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL_E5_SHIFT                                                  23
+  #define UCM_REG_INT_STS_WR_1_AGG_TASK_DATA_BUF_OVFL_BB_K2                                                  (0x1<<23) // Message Processor Aggregation Task Data buffer overflow.
+  #define UCM_REG_INT_STS_WR_1_AGG_TASK_DATA_BUF_OVFL_BB_K2_SHIFT                                            23
+  #define UCM_REG_INT_STS_WR_1_AGG_TASK_DATA_BUF_OVFL_E5                                                     (0x1<<24) // Message Processor Aggregation Task Data buffer overflow.
+  #define UCM_REG_INT_STS_WR_1_AGG_TASK_DATA_BUF_OVFL_E5_SHIFT                                               24
+  #define UCM_REG_INT_STS_WR_1_AGG_TASK_CMD_BUF_OVFL_BB_K2                                                   (0x1<<24) // Message Processor Aggregation Task Command buffer overflow.
+  #define UCM_REG_INT_STS_WR_1_AGG_TASK_CMD_BUF_OVFL_BB_K2_SHIFT                                             24
+  #define UCM_REG_INT_STS_WR_1_AGG_TASK_CMD_BUF_OVFL_E5                                                      (0x1<<25) // Message Processor Aggregation Task Command buffer overflow.
+  #define UCM_REG_INT_STS_WR_1_AGG_TASK_CMD_BUF_OVFL_E5_SHIFT                                                25
+  #define UCM_REG_INT_STS_WR_1_SM_TASK_DATA_BUF_OVFL_BB_K2                                                   (0x1<<25) // Message Processor Storm Task Data buffer overflow.
+  #define UCM_REG_INT_STS_WR_1_SM_TASK_DATA_BUF_OVFL_BB_K2_SHIFT                                             25
+  #define UCM_REG_INT_STS_WR_1_SM_TASK_DATA_BUF_OVFL_E5                                                      (0x1<<26) // Message Processor Storm Task Data buffer overflow.
+  #define UCM_REG_INT_STS_WR_1_SM_TASK_DATA_BUF_OVFL_E5_SHIFT                                                26
+  #define UCM_REG_INT_STS_WR_1_SM_TASK_CMD_BUF_OVFL_BB_K2                                                    (0x1<<26) // Message Processor Storm Task Command buffer overflow.
+  #define UCM_REG_INT_STS_WR_1_SM_TASK_CMD_BUF_OVFL_BB_K2_SHIFT                                              26
+  #define UCM_REG_INT_STS_WR_1_SM_TASK_CMD_BUF_OVFL_E5                                                       (0x1<<27) // Message Processor Storm Task Command buffer overflow.
+  #define UCM_REG_INT_STS_WR_1_SM_TASK_CMD_BUF_OVFL_E5_SHIFT                                                 27
+  #define UCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE_BB_K2                                                   (0x1<<27) // Input message first descriptor fields violation.
+  #define UCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE_BB_K2_SHIFT                                             27
+  #define UCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE_E5                                                      (0x1<<28) // Input message first descriptor fields violation.
+  #define UCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE_E5_SHIFT                                                28
+  #define UCM_REG_INT_STS_WR_1_SE_DESC_INPUT_VIOLATE_BB_K2                                                   (0x1<<28) // Input message second descriptor fields violation.
+  #define UCM_REG_INT_STS_WR_1_SE_DESC_INPUT_VIOLATE_BB_K2_SHIFT                                             28
+  #define UCM_REG_INT_STS_WR_1_SE_DESC_INPUT_VIOLATE_E5                                                      (0x1<<29) // Input message second descriptor fields violation.
+  #define UCM_REG_INT_STS_WR_1_SE_DESC_INPUT_VIOLATE_E5_SHIFT                                                29
+#define UCM_REG_INT_STS_CLR_1                                                                                0x128019cUL //Access:RC   DataWidth:0x1e   // Multi Field Register.
+  #define UCM_REG_INT_STS_CLR_1_IS_YSEM_UNDER_ERR_E5                                                         (0x1<<0) // Read from empty  Ysem input buffer.
+  #define UCM_REG_INT_STS_CLR_1_IS_YSEM_UNDER_ERR_E5_SHIFT                                                   0
+  #define UCM_REG_INT_STS_CLR_1_IS_DORQ_OVFL_ERR_BB_K2                                                       (0x1<<0) // Write to full Dorq input buffer.
+  #define UCM_REG_INT_STS_CLR_1_IS_DORQ_OVFL_ERR_BB_K2_SHIFT                                                 0
+  #define UCM_REG_INT_STS_CLR_1_IS_DORQ_OVFL_ERR_E5                                                          (0x1<<1) // Write to full Dorq input buffer.
+  #define UCM_REG_INT_STS_CLR_1_IS_DORQ_OVFL_ERR_E5_SHIFT                                                    1
+  #define UCM_REG_INT_STS_CLR_1_IS_DORQ_UNDER_ERR_BB_K2                                                      (0x1<<1) // Read from empty  Dorq input buffer.
+  #define UCM_REG_INT_STS_CLR_1_IS_DORQ_UNDER_ERR_BB_K2_SHIFT                                                1
+  #define UCM_REG_INT_STS_CLR_1_IS_DORQ_UNDER_ERR_E5                                                         (0x1<<2) // Read from empty  Dorq input buffer.
+  #define UCM_REG_INT_STS_CLR_1_IS_DORQ_UNDER_ERR_E5_SHIFT                                                   2
+  #define UCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR_BB_K2                                                        (0x1<<2) // Write to full Pbf input buffer.
+  #define UCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR_BB_K2_SHIFT                                                  2
+  #define UCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR_E5                                                           (0x1<<3) // Write to full Pbf input buffer.
+  #define UCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR_E5_SHIFT                                                     3
+  #define UCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR_BB_K2                                                       (0x1<<3) // Read from empty Pbf input buffer.
+  #define UCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR_BB_K2_SHIFT                                                 3
+  #define UCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR_E5                                                          (0x1<<4) // Read from empty Pbf input buffer.
+  #define UCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR_E5_SHIFT                                                    4
+  #define UCM_REG_INT_STS_CLR_1_IS_TM_OVFL_ERR_BB_K2                                                         (0x1<<4) // Write to full TM input buffer.
+  #define UCM_REG_INT_STS_CLR_1_IS_TM_OVFL_ERR_BB_K2_SHIFT                                                   4
+  #define UCM_REG_INT_STS_CLR_1_IS_TM_OVFL_ERR_E5                                                            (0x1<<5) // Write to full TM input buffer.
+  #define UCM_REG_INT_STS_CLR_1_IS_TM_OVFL_ERR_E5_SHIFT                                                      5
+  #define UCM_REG_INT_STS_CLR_1_IS_TM_UNDER_ERR_BB_K2                                                        (0x1<<5) // Read from empty TM input buffer.
+  #define UCM_REG_INT_STS_CLR_1_IS_TM_UNDER_ERR_BB_K2_SHIFT                                                  5
+  #define UCM_REG_INT_STS_CLR_1_IS_TM_UNDER_ERR_E5                                                           (0x1<<6) // Read from empty TM input buffer.
+  #define UCM_REG_INT_STS_CLR_1_IS_TM_UNDER_ERR_E5_SHIFT                                                     6
+  #define UCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR_BB_K2                                                       (0x1<<6) // Write to full QM input buffer.
+  #define UCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR_BB_K2_SHIFT                                                 6
+  #define UCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR_E5                                                          (0x1<<7) // Write to full QM input buffer.
+  #define UCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR_E5_SHIFT                                                    7
+  #define UCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR_BB_K2                                                      (0x1<<7) // Read from empty QM input buffer.
+  #define UCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR_BB_K2_SHIFT                                                7
+  #define UCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR_E5                                                         (0x1<<8) // Read from empty QM input buffer.
+  #define UCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR_E5_SHIFT                                                   8
+  #define UCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR_BB_K2                                                       (0x1<<8) // Write to full QM input buffer.
+  #define UCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR_BB_K2_SHIFT                                                 8
+  #define UCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR_E5                                                          (0x1<<9) // Write to full QM input buffer.
+  #define UCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR_E5_SHIFT                                                    9
+  #define UCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR_BB_K2                                                      (0x1<<9) // Read from empty QM input buffer.
+  #define UCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR_BB_K2_SHIFT                                                9
+  #define UCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR_E5                                                         (0x1<<10) // Read from empty QM input buffer.
+  #define UCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR_E5_SHIFT                                                   10
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0_BB_K2                                                       (0x1<<10) // Write to full GRC input buffer bits [31:0].
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0_BB_K2_SHIFT                                                 10
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0_E5                                                          (0x1<<11) // Write to full GRC input buffer bits [31:0].
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0_E5_SHIFT                                                    11
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0_BB_K2                                                      (0x1<<11) // Read from empty  GRC input buffer bits [31:0].
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0_BB_K2_SHIFT                                                11
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0_E5                                                         (0x1<<12) // Read from empty  GRC input buffer bits [31:0].
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0_E5_SHIFT                                                   12
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1_BB_K2                                                       (0x1<<12) // Write to full GRC input buffer bits [63:32].
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1_BB_K2_SHIFT                                                 12
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1_E5                                                          (0x1<<13) // Write to full GRC input buffer bits [63:32].
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1_E5_SHIFT                                                    13
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1_BB_K2                                                      (0x1<<13) // Read from empty  GRC input buffer bits [63:32].
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1_BB_K2_SHIFT                                                13
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1_E5                                                         (0x1<<14) // Read from empty  GRC input buffer bits [63:32].
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1_E5_SHIFT                                                   14
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2_BB_K2                                                       (0x1<<14) // Write to full GRC input buffer bits [95:64].
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2_BB_K2_SHIFT                                                 14
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2_E5                                                          (0x1<<15) // Write to full GRC input buffer bits [95:64].
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2_E5_SHIFT                                                    15
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2_BB_K2                                                      (0x1<<15) // Read from empty  GRC input buffer bits [95:64].
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2_BB_K2_SHIFT                                                15
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2_E5                                                         (0x1<<16) // Read from empty  GRC input buffer bits [95:64].
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2_E5_SHIFT                                                   16
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3_BB_K2                                                       (0x1<<16) // Write to full GRC input buffer bits [127:96].
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3_BB_K2_SHIFT                                                 16
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3_E5                                                          (0x1<<17) // Write to full GRC input buffer bits [127:96].
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3_E5_SHIFT                                                    17
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3_BB_K2                                                      (0x1<<17) // Read from empty  GRC input buffer bits [127:96].
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3_BB_K2_SHIFT                                                17
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3_E5                                                         (0x1<<18) // Read from empty  GRC input buffer bits [127:96].
+  #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3_E5_SHIFT                                                   18
+  #define UCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL_BB_K2                                                       (0x1<<18) // In-process Table overflow.
+  #define UCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL_BB_K2_SHIFT                                                 18
+  #define UCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL_E5                                                          (0x1<<19) // In-process Table overflow.
+  #define UCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL_E5_SHIFT                                                    19
+  #define UCM_REG_INT_STS_CLR_1_AGG_CON_DATA_BUF_OVFL_BB_K2                                                  (0x1<<19) // Message Processor Aggregation Connection Data buffer overflow.
+  #define UCM_REG_INT_STS_CLR_1_AGG_CON_DATA_BUF_OVFL_BB_K2_SHIFT                                            19
+  #define UCM_REG_INT_STS_CLR_1_AGG_CON_DATA_BUF_OVFL_E5                                                     (0x1<<20) // Message Processor Aggregation Connection Data buffer overflow.
+  #define UCM_REG_INT_STS_CLR_1_AGG_CON_DATA_BUF_OVFL_E5_SHIFT                                               20
+  #define UCM_REG_INT_STS_CLR_1_AGG_CON_CMD_BUF_OVFL_BB_K2                                                   (0x1<<20) // Message Processor Aggregation Connection Command buffer overflow.
+  #define UCM_REG_INT_STS_CLR_1_AGG_CON_CMD_BUF_OVFL_BB_K2_SHIFT                                             20
+  #define UCM_REG_INT_STS_CLR_1_AGG_CON_CMD_BUF_OVFL_E5                                                      (0x1<<21) // Message Processor Aggregation Connection Command buffer overflow.
+  #define UCM_REG_INT_STS_CLR_1_AGG_CON_CMD_BUF_OVFL_E5_SHIFT                                                21
+  #define UCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL_BB_K2                                                   (0x1<<21) // Message Processor Storm Connection Data buffer overflow.
+  #define UCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL_BB_K2_SHIFT                                             21
+  #define UCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL_E5                                                      (0x1<<22) // Message Processor Storm Connection Data buffer overflow.
+  #define UCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL_E5_SHIFT                                                22
+  #define UCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL_BB_K2                                                    (0x1<<22) // Message Processor Storm Connection Command buffer overflow.
+  #define UCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL_BB_K2_SHIFT                                              22
+  #define UCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL_E5                                                       (0x1<<23) // Message Processor Storm Connection Command buffer overflow.
+  #define UCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL_E5_SHIFT                                                 23
+  #define UCM_REG_INT_STS_CLR_1_AGG_TASK_DATA_BUF_OVFL_BB_K2                                                 (0x1<<23) // Message Processor Aggregation Task Data buffer overflow.
+  #define UCM_REG_INT_STS_CLR_1_AGG_TASK_DATA_BUF_OVFL_BB_K2_SHIFT                                           23
+  #define UCM_REG_INT_STS_CLR_1_AGG_TASK_DATA_BUF_OVFL_E5                                                    (0x1<<24) // Message Processor Aggregation Task Data buffer overflow.
+  #define UCM_REG_INT_STS_CLR_1_AGG_TASK_DATA_BUF_OVFL_E5_SHIFT                                              24
+  #define UCM_REG_INT_STS_CLR_1_AGG_TASK_CMD_BUF_OVFL_BB_K2                                                  (0x1<<24) // Message Processor Aggregation Task Command buffer overflow.
+  #define UCM_REG_INT_STS_CLR_1_AGG_TASK_CMD_BUF_OVFL_BB_K2_SHIFT                                            24
+  #define UCM_REG_INT_STS_CLR_1_AGG_TASK_CMD_BUF_OVFL_E5                                                     (0x1<<25) // Message Processor Aggregation Task Command buffer overflow.
+  #define UCM_REG_INT_STS_CLR_1_AGG_TASK_CMD_BUF_OVFL_E5_SHIFT                                               25
+  #define UCM_REG_INT_STS_CLR_1_SM_TASK_DATA_BUF_OVFL_BB_K2                                                  (0x1<<25) // Message Processor Storm Task Data buffer overflow.
+  #define UCM_REG_INT_STS_CLR_1_SM_TASK_DATA_BUF_OVFL_BB_K2_SHIFT                                            25
+  #define UCM_REG_INT_STS_CLR_1_SM_TASK_DATA_BUF_OVFL_E5                                                     (0x1<<26) // Message Processor Storm Task Data buffer overflow.
+  #define UCM_REG_INT_STS_CLR_1_SM_TASK_DATA_BUF_OVFL_E5_SHIFT                                               26
+  #define UCM_REG_INT_STS_CLR_1_SM_TASK_CMD_BUF_OVFL_BB_K2                                                   (0x1<<26) // Message Processor Storm Task Command buffer overflow.
+  #define UCM_REG_INT_STS_CLR_1_SM_TASK_CMD_BUF_OVFL_BB_K2_SHIFT                                             26
+  #define UCM_REG_INT_STS_CLR_1_SM_TASK_CMD_BUF_OVFL_E5                                                      (0x1<<27) // Message Processor Storm Task Command buffer overflow.
+  #define UCM_REG_INT_STS_CLR_1_SM_TASK_CMD_BUF_OVFL_E5_SHIFT                                                27
+  #define UCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE_BB_K2                                                  (0x1<<27) // Input message first descriptor fields violation.
+  #define UCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE_BB_K2_SHIFT                                            27
+  #define UCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE_E5                                                     (0x1<<28) // Input message first descriptor fields violation.
+  #define UCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE_E5_SHIFT                                               28
+  #define UCM_REG_INT_STS_CLR_1_SE_DESC_INPUT_VIOLATE_BB_K2                                                  (0x1<<28) // Input message second descriptor fields violation.
+  #define UCM_REG_INT_STS_CLR_1_SE_DESC_INPUT_VIOLATE_BB_K2_SHIFT                                            28
+  #define UCM_REG_INT_STS_CLR_1_SE_DESC_INPUT_VIOLATE_E5                                                     (0x1<<29) // Input message second descriptor fields violation.
+  #define UCM_REG_INT_STS_CLR_1_SE_DESC_INPUT_VIOLATE_E5_SHIFT                                               29
+#define UCM_REG_INT_STS_2                                                                                    0x12801a0UL //Access:R    DataWidth:0x1    // Multi Field Register.
+  #define UCM_REG_INT_STS_2_QMREG_MORE4                                                                      (0x1<<0) // More than 4 QM registrations.
+  #define UCM_REG_INT_STS_2_QMREG_MORE4_SHIFT                                                                0
+#define UCM_REG_INT_MASK_2                                                                                   0x12801a4UL //Access:RW   DataWidth:0x1    // Multi Field Register.
+  #define UCM_REG_INT_MASK_2_QMREG_MORE4                                                                     (0x1<<0) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_2.QMREG_MORE4 .
+  #define UCM_REG_INT_MASK_2_QMREG_MORE4_SHIFT                                                               0
+#define UCM_REG_INT_STS_WR_2                                                                                 0x12801a8UL //Access:WR   DataWidth:0x1    // Multi Field Register.
+  #define UCM_REG_INT_STS_WR_2_QMREG_MORE4                                                                   (0x1<<0) // More than 4 QM registrations.
+  #define UCM_REG_INT_STS_WR_2_QMREG_MORE4_SHIFT                                                             0
+#define UCM_REG_INT_STS_CLR_2                                                                                0x12801acUL //Access:RC   DataWidth:0x1    // Multi Field Register.
+  #define UCM_REG_INT_STS_CLR_2_QMREG_MORE4                                                                  (0x1<<0) // More than 4 QM registrations.
+  #define UCM_REG_INT_STS_CLR_2_QMREG_MORE4_SHIFT                                                            0
+#define UCM_REG_PRTY_MASK_H_0_BB_K2                                                                          0x1280204UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define UCM_REG_PRTY_MASK_H_0_MEM030_I_ECC_RF_INT_BB_K2                                                    (0x1<<0) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM030_I_ECC_RF_INT .
+  #define UCM_REG_PRTY_MASK_H_0_MEM030_I_ECC_RF_INT_BB_K2_SHIFT                                              0
+  #define UCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_BB_K2                                                  (0x1<<1) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
+  #define UCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_BB_K2_SHIFT                                            1
+  #define UCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_K2                                                  (0x1<<2) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
+  #define UCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_K2_SHIFT                                            2
+  #define UCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_0_RF_INT_BB_K2                                                  (0x1<<3) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM024_I_ECC_0_RF_INT .
+  #define UCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_0_RF_INT_BB_K2_SHIFT                                            3
+  #define UCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_1_RF_INT_BB_K2                                                  (0x1<<4) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM024_I_ECC_1_RF_INT .
+  #define UCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_1_RF_INT_BB_K2_SHIFT                                            4
+  #define UCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_RF_INT_BB_K2                                                    (0x1<<5) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM025_I_ECC_RF_INT .
+  #define UCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_RF_INT_BB_K2_SHIFT                                              5
+  #define UCM_REG_PRTY_MASK_H_0_MEM007_I_ECC_0_RF_INT_BB_K2                                                  (0x1<<6) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM007_I_ECC_0_RF_INT .
+  #define UCM_REG_PRTY_MASK_H_0_MEM007_I_ECC_0_RF_INT_BB_K2_SHIFT                                            6
+  #define UCM_REG_PRTY_MASK_H_0_MEM007_I_ECC_1_RF_INT_BB_K2                                                  (0x1<<7) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM007_I_ECC_1_RF_INT .
+  #define UCM_REG_PRTY_MASK_H_0_MEM007_I_ECC_1_RF_INT_BB_K2_SHIFT                                            7
+  #define UCM_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT_BB_K2                                                    (0x1<<8) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM008_I_ECC_RF_INT .
+  #define UCM_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT_BB_K2_SHIFT                                              8
+  #define UCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_0_RF_INT_BB_K2                                                  (0x1<<9) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM027_I_ECC_0_RF_INT .
+  #define UCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_0_RF_INT_BB_K2_SHIFT                                            9
+  #define UCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_1_RF_INT_BB_K2                                                  (0x1<<10) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM027_I_ECC_1_RF_INT .
+  #define UCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_1_RF_INT_BB_K2_SHIFT                                            10
+  #define UCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_RF_INT_BB_K2                                                    (0x1<<11) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM028_I_ECC_RF_INT .
+  #define UCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_RF_INT_BB_K2_SHIFT                                              11
+  #define UCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_K2                                                      (0x1<<12) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
+  #define UCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_K2_SHIFT                                                12
+  #define UCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB_K2                                                      (0x1<<13) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
+  #define UCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB_K2_SHIFT                                                13
+  #define UCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_K2                                                      (0x1<<14) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
+  #define UCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_K2_SHIFT                                                14
+  #define UCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_K2                                                      (0x1<<15) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
+  #define UCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_K2_SHIFT                                                15
+  #define UCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_K2                                                      (0x1<<16) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
+  #define UCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_K2_SHIFT                                                16
+  #define UCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_K2                                                      (0x1<<17) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
+  #define UCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_K2_SHIFT                                                17
+  #define UCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_K2                                                      (0x1<<18) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
+  #define UCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_K2_SHIFT                                                18
+  #define UCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_K2                                                      (0x1<<19) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
+  #define UCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_K2_SHIFT                                                19
+  #define UCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_K2                                                      (0x1<<20) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
+  #define UCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_K2_SHIFT                                                20
+  #define UCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_K2                                                      (0x1<<21) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
+  #define UCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_K2_SHIFT                                                21
+  #define UCM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_BB_K2                                                      (0x1<<22) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
+  #define UCM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_BB_K2_SHIFT                                                22
+  #define UCM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_K2                                                      (0x1<<23) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
+  #define UCM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_K2_SHIFT                                                23
+  #define UCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_K2                                                      (0x1<<24) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
+  #define UCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_K2_SHIFT                                                24
+  #define UCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2                                                      (0x1<<25) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
+  #define UCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2_SHIFT                                                25
+  #define UCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_K2                                                      (0x1<<26) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
+  #define UCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_K2_SHIFT                                                26
+  #define UCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2                                                      (0x1<<27) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
+  #define UCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2_SHIFT                                                27
+  #define UCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_K2                                                      (0x1<<28) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
+  #define UCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_K2_SHIFT                                                28
+  #define UCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_K2                                                      (0x1<<29) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
+  #define UCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_K2_SHIFT                                                29
+  #define UCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_0_BB_K2                                                    (0x1<<30) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY_0 .
+  #define UCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_0_BB_K2_SHIFT                                              30
+#define UCM_REG_PRTY_MASK_H_1_BB_K2                                                                          0x1280214UL //Access:RW   DataWidth:0x7    // Multi Field Register.
+  #define UCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_1_BB_K2                                                    (0x1<<0) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY_1 .
+  #define UCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_1_BB_K2_SHIFT                                              0
+  #define UCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_BB_K2                                                      (0x1<<1) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY .
+  #define UCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_BB_K2_SHIFT                                                1
+  #define UCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_BB_K2                                                      (0x1<<2) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM012_I_MEM_PRTY .
+  #define UCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_BB_K2_SHIFT                                                2
+  #define UCM_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY_BB_K2                                                      (0x1<<3) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM003_I_MEM_PRTY .
+  #define UCM_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                                3
+  #define UCM_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_BB_K2                                                      (0x1<<4) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM004_I_MEM_PRTY .
+  #define UCM_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                                4
+  #define UCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_K2                                                      (0x1<<5) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
+  #define UCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                                5
+  #define UCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_K2                                                      (0x1<<6) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
+  #define UCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                                6
+#define UCM_REG_MEM024_RF_ECC_ERROR_CONNECT_0_BB_K2                                                          0x1280220UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: ucm.i_sm_con_ctx_0_11.rf_ecc_error_connect_0 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define UCM_REG_MEM024_RF_ECC_ERROR_CONNECT_1_BB_K2                                                          0x1280224UL //Access:W    DataWidth:0x12   // Register to generate up to two ECC errors on the next write to memory: ucm.i_sm_con_ctx_0_11.rf_ecc_error_connect_1 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write.
+#define UCM_REG_MEM_ECC_ENABLE_0_BB_K2                                                                       0x1280228UL //Access:RW   DataWidth:0xc    // Multi Field Register.
+  #define UCM_REG_MEM_ECC_ENABLE_0_MEM030_I_ECC_EN_BB_K2                                                     (0x1<<0) // Enable ECC for memory ecc instance ucm.i_xx_msg_ram.i_ecc in module ucm_mem_xx_msg_ram
+  #define UCM_REG_MEM_ECC_ENABLE_0_MEM030_I_ECC_EN_BB_K2_SHIFT                                               0
+  #define UCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN_BB_K2                                                   (0x1<<1) // Enable ECC for memory ecc instance ucm.i_agg_con_ctx.i_ecc_0 in module ucm_mem_agg_con_ctx
+  #define UCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN_BB_K2_SHIFT                                             1
+  #define UCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_BB_K2                                                   (0x1<<2) // Enable ECC for memory ecc instance ucm.i_agg_con_ctx.i_ecc_1 in module ucm_mem_agg_con_ctx
+  #define UCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_BB_K2_SHIFT                                             2
+  #define UCM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_0_EN_BB_K2                                                   (0x1<<3) // Enable ECC for memory ecc instance ucm.i_sm_con_ctx_0_11.i_ecc_0 in module ucm_mem_sm_con_ctx_0_11
+  #define UCM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_0_EN_BB_K2_SHIFT                                             3
+  #define UCM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_1_EN_BB_K2                                                   (0x1<<4) // Enable ECC for memory ecc instance ucm.i_sm_con_ctx_0_11.i_ecc_1 in module ucm_mem_sm_con_ctx_0_11
+  #define UCM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_1_EN_BB_K2_SHIFT                                             4
+  #define UCM_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_EN_BB_K2                                                     (0x1<<5) // Enable ECC for memory ecc instance ucm.i_sm_con_ctx_12.i_ecc in module ucm_mem_sm_con_ctx_12
+  #define UCM_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_EN_BB_K2_SHIFT                                               5
+  #define UCM_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_0_EN_BB_K2                                                   (0x1<<6) // Enable ECC for memory ecc instance ucm.i_agg_task_ctx_0_1.i_ecc_0 in module ucm_mem_agg_task_ctx_0_1
+  #define UCM_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_0_EN_BB_K2_SHIFT                                             6
+  #define UCM_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_1_EN_BB_K2                                                   (0x1<<7) // Enable ECC for memory ecc instance ucm.i_agg_task_ctx_0_1.i_ecc_1 in module ucm_mem_agg_task_ctx_0_1
+  #define UCM_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_1_EN_BB_K2_SHIFT                                             7
+  #define UCM_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_EN_BB_K2                                                     (0x1<<8) // Enable ECC for memory ecc instance ucm.i_agg_task_ctx_2.i_ecc in module ucm_mem_agg_task_ctx_2
+  #define UCM_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_EN_BB_K2_SHIFT                                               8
+  #define UCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_0_EN_BB_K2                                                   (0x1<<9) // Enable ECC for memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_0 in module ucm_mem_sm_task_ctx_0_1
+  #define UCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_0_EN_BB_K2_SHIFT                                             9
+  #define UCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_1_EN_BB_K2                                                   (0x1<<10) // Enable ECC for memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_1 in module ucm_mem_sm_task_ctx_0_1
+  #define UCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_1_EN_BB_K2_SHIFT                                             10
+  #define UCM_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_EN_BB_K2                                                     (0x1<<11) // Enable ECC for memory ecc instance ucm.i_sm_task_ctx_2.i_ecc in module ucm_mem_sm_task_ctx_2
+  #define UCM_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_EN_BB_K2_SHIFT                                               11
+#define UCM_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                  0x128022cUL //Access:RW   DataWidth:0xc    // Multi Field Register.
+  #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM030_I_ECC_PRTY_BB_K2                                              (0x1<<0) // Set parity only for memory ecc instance ucm.i_xx_msg_ram.i_ecc in module ucm_mem_xx_msg_ram
+  #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM030_I_ECC_PRTY_BB_K2_SHIFT                                        0
+  #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY_BB_K2                                            (0x1<<1) // Set parity only for memory ecc instance ucm.i_agg_con_ctx.i_ecc_0 in module ucm_mem_agg_con_ctx
+  #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY_BB_K2_SHIFT                                      1
+  #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_BB_K2                                            (0x1<<2) // Set parity only for memory ecc instance ucm.i_agg_con_ctx.i_ecc_1 in module ucm_mem_agg_con_ctx
+  #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_BB_K2_SHIFT                                      2
+  #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_0_PRTY_BB_K2                                            (0x1<<3) // Set parity only for memory ecc instance ucm.i_sm_con_ctx_0_11.i_ecc_0 in module ucm_mem_sm_con_ctx_0_11
+  #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_0_PRTY_BB_K2_SHIFT                                      3
+  #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_1_PRTY_BB_K2                                            (0x1<<4) // Set parity only for memory ecc instance ucm.i_sm_con_ctx_0_11.i_ecc_1 in module ucm_mem_sm_con_ctx_0_11
+  #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_1_PRTY_BB_K2_SHIFT                                      4
+  #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_PRTY_BB_K2                                              (0x1<<5) // Set parity only for memory ecc instance ucm.i_sm_con_ctx_12.i_ecc in module ucm_mem_sm_con_ctx_12
+  #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_PRTY_BB_K2_SHIFT                                        5
+  #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_0_PRTY_BB_K2                                            (0x1<<6) // Set parity only for memory ecc instance ucm.i_agg_task_ctx_0_1.i_ecc_0 in module ucm_mem_agg_task_ctx_0_1
+  #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_0_PRTY_BB_K2_SHIFT                                      6
+  #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_1_PRTY_BB_K2                                            (0x1<<7) // Set parity only for memory ecc instance ucm.i_agg_task_ctx_0_1.i_ecc_1 in module ucm_mem_agg_task_ctx_0_1
+  #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_1_PRTY_BB_K2_SHIFT                                      7
+  #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_PRTY_BB_K2                                              (0x1<<8) // Set parity only for memory ecc instance ucm.i_agg_task_ctx_2.i_ecc in module ucm_mem_agg_task_ctx_2
+  #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_PRTY_BB_K2_SHIFT                                        8
+  #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_0_PRTY_BB_K2                                            (0x1<<9) // Set parity only for memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_0 in module ucm_mem_sm_task_ctx_0_1
+  #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_0_PRTY_BB_K2_SHIFT                                      9
+  #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_1_PRTY_BB_K2                                            (0x1<<10) // Set parity only for memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_1 in module ucm_mem_sm_task_ctx_0_1
+  #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_1_PRTY_BB_K2_SHIFT                                      10
+  #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_PRTY_BB_K2                                              (0x1<<11) // Set parity only for memory ecc instance ucm.i_sm_task_ctx_2.i_ecc in module ucm_mem_sm_task_ctx_2
+  #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_PRTY_BB_K2_SHIFT                                        11
+#define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                              0x1280230UL //Access:RC   DataWidth:0xc    // Multi Field Register.
+  #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM030_I_ECC_CORRECT_BB_K2                                       (0x1<<0) // Record if a correctable error occurred on memory ecc instance ucm.i_xx_msg_ram.i_ecc in module ucm_mem_xx_msg_ram
+  #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM030_I_ECC_CORRECT_BB_K2_SHIFT                                 0
+  #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT_BB_K2                                     (0x1<<1) // Record if a correctable error occurred on memory ecc instance ucm.i_agg_con_ctx.i_ecc_0 in module ucm_mem_agg_con_ctx
+  #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT_BB_K2_SHIFT                               1
+  #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_BB_K2                                     (0x1<<2) // Record if a correctable error occurred on memory ecc instance ucm.i_agg_con_ctx.i_ecc_1 in module ucm_mem_agg_con_ctx
+  #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_BB_K2_SHIFT                               2
+  #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_0_CORRECT_BB_K2                                     (0x1<<3) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_con_ctx_0_11.i_ecc_0 in module ucm_mem_sm_con_ctx_0_11
+  #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_0_CORRECT_BB_K2_SHIFT                               3
+  #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_1_CORRECT_BB_K2                                     (0x1<<4) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_con_ctx_0_11.i_ecc_1 in module ucm_mem_sm_con_ctx_0_11
+  #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_1_CORRECT_BB_K2_SHIFT                               4
+  #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_CORRECT_BB_K2                                       (0x1<<5) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_con_ctx_12.i_ecc in module ucm_mem_sm_con_ctx_12
+  #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_CORRECT_BB_K2_SHIFT                                 5
+  #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_0_CORRECT_BB_K2                                     (0x1<<6) // Record if a correctable error occurred on memory ecc instance ucm.i_agg_task_ctx_0_1.i_ecc_0 in module ucm_mem_agg_task_ctx_0_1
+  #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_0_CORRECT_BB_K2_SHIFT                               6
+  #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_1_CORRECT_BB_K2                                     (0x1<<7) // Record if a correctable error occurred on memory ecc instance ucm.i_agg_task_ctx_0_1.i_ecc_1 in module ucm_mem_agg_task_ctx_0_1
+  #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_1_CORRECT_BB_K2_SHIFT                               7
+  #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_CORRECT_BB_K2                                       (0x1<<8) // Record if a correctable error occurred on memory ecc instance ucm.i_agg_task_ctx_2.i_ecc in module ucm_mem_agg_task_ctx_2
+  #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_CORRECT_BB_K2_SHIFT                                 8
+  #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_0_CORRECT_BB_K2                                     (0x1<<9) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_0 in module ucm_mem_sm_task_ctx_0_1
+  #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_0_CORRECT_BB_K2_SHIFT                               9
+  #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_1_CORRECT_BB_K2                                     (0x1<<10) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_1 in module ucm_mem_sm_task_ctx_0_1
+  #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_1_CORRECT_BB_K2_SHIFT                               10
+  #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_CORRECT_BB_K2                                       (0x1<<11) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_task_ctx_2.i_ecc in module ucm_mem_sm_task_ctx_2
+  #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_CORRECT_BB_K2_SHIFT                                 11
+#define UCM_REG_MEM_ECC_EVENTS_BB_K2                                                                         0x1280234UL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define UCM_REG_IFEN                                                                                         0x1280400UL //Access:RW   DataWidth:0x1    // Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
+#define UCM_REG_QM_TASK_BASE_EVNT_ID_0                                                                       0x1280424UL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define UCM_REG_QM_TASK_BASE_EVNT_ID_1                                                                       0x1280428UL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define UCM_REG_QM_TASK_BASE_EVNT_ID_2                                                                       0x128042cUL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define UCM_REG_QM_TASK_BASE_EVNT_ID_3                                                                       0x1280430UL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define UCM_REG_QM_TASK_BASE_EVNT_ID_4                                                                       0x1280434UL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define UCM_REG_QM_TASK_BASE_EVNT_ID_5                                                                       0x1280438UL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define UCM_REG_QM_TASK_BASE_EVNT_ID_6                                                                       0x128043cUL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define UCM_REG_QM_TASK_BASE_EVNT_ID_7                                                                       0x1280440UL //Access:RW   DataWidth:0x8    // QM task base Event ID per connection type.
+#define UCM_REG_QM_AGG_TASK_CTX_PART_SIZE_0                                                                  0x1280484UL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define UCM_REG_QM_AGG_TASK_CTX_PART_SIZE_1                                                                  0x1280488UL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define UCM_REG_QM_AGG_TASK_CTX_PART_SIZE_2                                                                  0x128048cUL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define UCM_REG_QM_AGG_TASK_CTX_PART_SIZE_3                                                                  0x1280490UL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define UCM_REG_QM_AGG_TASK_CTX_PART_SIZE_4                                                                  0x1280494UL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define UCM_REG_QM_AGG_TASK_CTX_PART_SIZE_5                                                                  0x1280498UL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define UCM_REG_QM_AGG_TASK_CTX_PART_SIZE_6                                                                  0x128049cUL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define UCM_REG_QM_AGG_TASK_CTX_PART_SIZE_7                                                                  0x12804a0UL //Access:RW   DataWidth:0x4    // QM aggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
+#define UCM_REG_QM_SM_TASK_CTX_LDST_FLG_0                                                                    0x12804a4UL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define UCM_REG_QM_SM_TASK_CTX_LDST_FLG_1                                                                    0x12804a8UL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define UCM_REG_QM_SM_TASK_CTX_LDST_FLG_2                                                                    0x12804acUL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define UCM_REG_QM_SM_TASK_CTX_LDST_FLG_3                                                                    0x12804b0UL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define UCM_REG_QM_SM_TASK_CTX_LDST_FLG_4                                                                    0x12804b4UL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define UCM_REG_QM_SM_TASK_CTX_LDST_FLG_5                                                                    0x12804b8UL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define UCM_REG_QM_SM_TASK_CTX_LDST_FLG_6                                                                    0x12804bcUL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define UCM_REG_QM_SM_TASK_CTX_LDST_FLG_7                                                                    0x12804c0UL //Access:RW   DataWidth:0x1    // QM storm task context load_store per task type.
+#define UCM_REG_QM_TASK_USE_ST_FLG_0                                                                         0x1280504UL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define UCM_REG_QM_TASK_USE_ST_FLG_1                                                                         0x1280508UL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define UCM_REG_QM_TASK_USE_ST_FLG_2                                                                         0x128050cUL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define UCM_REG_QM_TASK_USE_ST_FLG_3                                                                         0x1280510UL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define UCM_REG_QM_TASK_USE_ST_FLG_4                                                                         0x1280514UL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define UCM_REG_QM_TASK_USE_ST_FLG_5                                                                         0x1280518UL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define UCM_REG_QM_TASK_USE_ST_FLG_6                                                                         0x128051cUL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
+#define UCM_REG_QM_TASK_USE_ST_FLG_7                                                                         0x1280520UL //Access:RW   DataWidth:0x1    // QM Task use state flag per connection type. Should be all 0 for PCM and XCM.
+#define UCM_REG_TM_TASK_EVNT_ID_0                                                                            0x1280544UL //Access:RW   DataWidth:0x8    // TM task Event ID per connection type.
+#define UCM_REG_TM_TASK_EVNT_ID_1                                                                            0x1280548UL //Access:RW   DataWidth:0x8    // TM task Event ID per connection type.
+#define UCM_REG_TM_TASK_EVNT_ID_2                                                                            0x128054cUL //Access:RW   DataWidth:0x8    // TM task Event ID per connection type.
+#define UCM_REG_TM_TASK_EVNT_ID_3                                                                            0x1280550UL //Access:RW   DataWidth:0x8    // TM task Event ID per connection type.
+#define UCM_REG_TM_TASK_EVNT_ID_4                                                                            0x1280554UL //Access:RW   DataWidth:0x8    // TM task Event ID per connection type.
+#define UCM_REG_TM_TASK_EVNT_ID_5                                                                            0x1280558UL //Access:RW   DataWidth:0x8    // TM task Event ID per connection type.
+#define UCM_REG_TM_TASK_EVNT_ID_6                                                                            0x128055cUL //Access:RW   DataWidth:0x8    // TM task Event ID per connection type.
+#define UCM_REG_TM_TASK_EVNT_ID_7                                                                            0x1280560UL //Access:RW   DataWidth:0x8    // TM task Event ID per connection type.
+#define UCM_REG_ERR_EVNT_ID                                                                                  0x1280564UL //Access:RW   DataWidth:0x8    // The Event ID in case one of errors is set in QM input message.
+#define UCM_REG_STORM_WEIGHT                                                                                 0x1280604UL //Access:RW   DataWidth:0x3    // The weight of the local Storm input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define UCM_REG_DORQ_WEIGHT                                                                                  0x1280608UL //Access:RW   DataWidth:0x3    // The weight of the input Dorq in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define UCM_REG_PBF_WEIGHT                                                                                   0x128060cUL //Access:RW   DataWidth:0x3    // The weight of the input Pbf in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define UCM_REG_GRC_WEIGHT                                                                                   0x1280610UL //Access:RW   DataWidth:0x3    // The weight of the GRC input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define UCM_REG_XSDM_WEIGHT                                                                                  0x1280614UL //Access:RW   DataWidth:0x3    // The weight of the XSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define UCM_REG_YSDM_WEIGHT                                                                                  0x1280618UL //Access:RW   DataWidth:0x3    // The weight of the YSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define UCM_REG_USDM_WEIGHT                                                                                  0x128061cUL //Access:RW   DataWidth:0x3    // The weight of the input USDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define UCM_REG_RDIF_WEIGHT                                                                                  0x1280620UL //Access:RW   DataWidth:0x3    // The weight of the input RDIF in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define UCM_REG_TDIF_WEIGHT                                                                                  0x1280624UL //Access:RW   DataWidth:0x3    // The weight of the input RDIF in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define UCM_REG_MULD_WEIGHT                                                                                  0x1280628UL //Access:RW   DataWidth:0x3    // The weight of the input MULD in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.:
+#define UCM_REG_YULD_WEIGHT_BB_K2                                                                            0x128062cUL //Access:RW   DataWidth:0x3    // The weight of the input YULD in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define UCM_REG_QM_P_WEIGHT                                                                                  0x1280630UL //Access:RW   DataWidth:0x3    // The weight of the QM (primary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define UCM_REG_QM_S_WEIGHT                                                                                  0x1280634UL //Access:RW   DataWidth:0x3    // The weight of the QM (secondary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define UCM_REG_TM_WEIGHT                                                                                    0x1280638UL //Access:RW   DataWidth:0x3    // The weight of the Timers input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define UCM_REG_IA_GROUP_PR0                                                                                 0x128063cUL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: ia_group_pr0 is the highest priority; ia_group_pr5 is the lowest priority.
+#define UCM_REG_IA_GROUP_PR1                                                                                 0x1280640UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define UCM_REG_IA_GROUP_PR2                                                                                 0x1280644UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define UCM_REG_IA_GROUP_PR3                                                                                 0x1280648UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define UCM_REG_IA_GROUP_PR4                                                                                 0x128064cUL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define UCM_REG_IA_GROUP_PR5                                                                                 0x1280650UL //Access:RW   DataWidth:0x3    // Input Arbiter group client corresponding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.
+#define UCM_REG_IA_ARB_SP_TIMEOUT                                                                            0x1280654UL //Access:RW   DataWidth:0x8    // Input Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8'h0 - constant RR; 8'h80 - constant strict priority. In all other cases the following is true: Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance.
+#define UCM_REG_STORM_FRWRD_MODE                                                                             0x1280658UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define UCM_REG_XSDM_FRWRD_MODE                                                                              0x128065cUL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define UCM_REG_YSDM_FRWRD_MODE                                                                              0x1280660UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define UCM_REG_PSDM_FRWRD_MODE_BB_K2                                                                        0x1280664UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define UCM_REG_USDM_FRWRD_MODE                                                                              0x1280668UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define UCM_REG_RDIF_FRWRD_MODE                                                                              0x128066cUL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define UCM_REG_TDIF_FRWRD_MODE                                                                              0x1280670UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define UCM_REG_MULD_FRWRD_MODE                                                                              0x1280674UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define UCM_REG_YULD_FRWRD_MODE_BB_K2                                                                        0x1280678UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define UCM_REG_DORQ_FRWRD_MODE                                                                              0x128067cUL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define UCM_REG_PBF_FRWRD_MODE                                                                               0x1280680UL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define UCM_REG_SDM_ERR_HANDLE_EN                                                                            0x1280684UL //Access:RW   DataWidth:0x1    // 0 - disable error handling in SDM message; 1 - enable error handling in SDM message.
+#define UCM_REG_DIR_BYP_EN                                                                                   0x1280688UL //Access:RW   DataWidth:0x1    // Direct bypass enable.
+#define UCM_REG_FI_DESC_INPUT_VIOLATE                                                                        0x128068cUL //Access:R    DataWidth:0xf    // Input message first descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0  then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL  then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation:  Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation:  TaskExist==0 -> XxLockCmd != XX_UNLOCK_CID_TID and XxLockCmd != XX_LOCK_CID_TID_BYPASS;  [12] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0;[13] - Violation: Agg message: Loader done with error then SmCtxLdStFlg==0; [14] - Violation: XxBypass message in PCM block;
+#define UCM_REG_SE_DESC_INPUT_VIOLATE                                                                        0x1280690UL //Access:R    DataWidth:0xc    // Input message second descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0  then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL  then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation:  Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0; Read only register.
+#define UCM_REG_IA_AGG_CON_PART_FILL_LVL                                                                     0x1280694UL //Access:R    DataWidth:0x3    // Input Arbiter Aggregation Connection part FIFO fill level (in messages).
+#define UCM_REG_IA_SM_CON_PART_FILL_LVL                                                                      0x1280698UL //Access:R    DataWidth:0x3    // Input Arbiter Storm Connection part FIFO fill level (in messages).
+#define UCM_REG_IA_AGG_TASK_PART_FILL_LVL                                                                    0x128069cUL //Access:R    DataWidth:0x3    // Input Arbiter Aggregation Task part FIFO fill level (in messages).
+#define UCM_REG_IA_SM_TASK_PART_FILL_LVL                                                                     0x12806a0UL //Access:R    DataWidth:0x3    // Input Arbiter Storm Task part FIFO fill level (in messages).
+#define UCM_REG_IA_TRANS_PART_FILL_LVL                                                                       0x12806a4UL //Access:R    DataWidth:0x3    // Input Arbiter Transparent part FIFO fill level (in messages).
+#define UCM_REG_EXT_RD_FILL_LVL_E5                                                                           0x12806a8UL //Access:R    DataWidth:0x2    // External read buffer FIFO fill level (in FIFO entries).
+#define UCM_REG_XX_MSG_UP_BND                                                                                0x1280704UL //Access:RW   DataWidth:0x7    // The maximum number of Xx RAM messages; which may be stored in XX protection. Is restricted by Xx Messages RAM size and the size of Xx protected message CM_REGISTERS_XX_MSG_SIZE.XX_MSG_SIZE
+#define UCM_REG_XX_MSG_SIZE                                                                                  0x1280708UL //Access:RW   DataWidth:0x5    // The size of Xx protected message in Xx Messages RAM in QREGs. Upper rounded to 4 and multiplied by CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND should not exceed XxMessagesRam size which is: MCM: 0d1792 PCM: 0d176 TCM: 0d1536 UCM: 0d1792 XCM: 0d256 YCM: 0d1536
+#define UCM_REG_XX_LCID_CAM_UP_BND                                                                           0x128070cUL //Access:RW   DataWidth:0x7    // The maximum number of connections in the XX protection LCID CAM.
+#define UCM_REG_XX_FREE_CNT                                                                                  0x1280710UL //Access:R    DataWidth:0x7    // Used to read the XX protection Free counter. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND
+#define UCM_REG_XX_LCID_CAM_FILL_LVL                                                                         0x1280714UL //Access:R    DataWidth:0x7    // Used to read XX protection LCID CAM fill level. Fill level is calculated as the number of locked LCIDs, i.e. LCIDs that have at least one Xx locked message or LCIDs that have no Xx locked messages but haven't been unlocked yet from LCID CAM. Simple saying it calculates for number of valid entries in LCID CAM.
+#define UCM_REG_XX_LCID_CAM_ST_STAT                                                                          0x1280718UL //Access:RC   DataWidth:0x7    // CAM occupancy sticky status. The write to the register is performed by the XX internal circuitry.
+#define UCM_REG_XX_IA_GROUP_PR0                                                                              0x128071cUL //Access:RW   DataWidth:0x1    // Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
+#define UCM_REG_XX_IA_GROUP_PR1                                                                              0x1280720UL //Access:RW   DataWidth:0x1    // Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
+#define UCM_REG_XX_NON_LOCK_LCID_THR                                                                         0x1280724UL //Access:RW   DataWidth:0x7    // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decision of Xx Input Arbiter non-locked group.
+#define UCM_REG_XX_LOCK_LCID_THR                                                                             0x1280728UL //Access:RW   DataWidth:0x7    // Xx locked LCIDs threshold (maximum value). Participates in Xx Bypass global enable decision.
+#define UCM_REG_XX_IA_ARB_SP_TIMEOUT                                                                         0x128072cUL //Access:RW   DataWidth:0x8    // Xx Input Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. E.g. bits[6:0]=0; bit[7]=0 - always strict priority; bits[6:0]=1; bit[7]=0 - strict priority; then RR; bits[6:0]=3; bit[7]=0 - 3 times strict priority; then RR.
+#define UCM_REG_XX_FREE_HEAD_PTR                                                                             0x1280730UL //Access:R    DataWidth:0x6    // Xx Free Head Pointer.
+#define UCM_REG_XX_FREE_TAIL_PTR                                                                             0x1280734UL //Access:R    DataWidth:0x6    // Xx Free Tail Pointer. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND
+#define UCM_REG_XX_NON_LOCK_CNT                                                                              0x1280738UL //Access:R    DataWidth:0x7    // Xx NonLock Counter.
+#define UCM_REG_XX_LOCK_CNT                                                                                  0x128073cUL //Access:R    DataWidth:0x7    // Xx Lock Counter.
+#define UCM_REG_XX_LCID_ARB_GROUP_PR0                                                                        0x1280740UL //Access:RW   DataWidth:0x2    // Xx LCID Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.
+#define UCM_REG_XX_LCID_ARB_GROUP_PR1                                                                        0x1280744UL //Access:RW   DataWidth:0x2    // Xx LCID Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.
+#define UCM_REG_XX_LCID_ARB_GROUP_PR2                                                                        0x1280748UL //Access:RW   DataWidth:0x2    // Xx LCID Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.
+#define UCM_REG_XX_LCID_ARB_SP_TIMEOUT                                                                       0x128074cUL //Access:RW   DataWidth:0x8    // Xx LCID Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. E.g. bits[6:0]=0; bit[7]=0 - always strict priority; bits[6:0]=1; bit[7]=0 - strict priority; then RR; bits[6:0]=3; bit[7]=0 - 3 times strict priority; then RR.
+#define UCM_REG_XX_FREE_THR_HIGH                                                                             0x1280750UL //Access:RW   DataWidth:0x7    // Xx free messages threshold high. Used in Xx Bypass global enable condition.
+#define UCM_REG_XX_FREE_THR_LOW                                                                              0x1280754UL //Access:RW   DataWidth:0x7    // Xx free messages threshold low Used in Xx Bypass global enable condition.
+#define UCM_REG_XX_CBYP_TBL_FILL_LVL                                                                         0x1280758UL //Access:R    DataWidth:0x4    // Xx Connection Bypass Table fill level (in connections).
+#define UCM_REG_XX_CBYP_TBL_ST_STAT                                                                          0x128075cUL //Access:RC   DataWidth:0x4    // Xx Connection Bypass Table sticky status. Reset on read.
+#define UCM_REG_XX_CBYP_TBL_UP_BND                                                                           0x1280760UL //Access:RW   DataWidth:0x4    // Xx Bypass Table (Connection) maximum fill level.
+#define UCM_REG_XX_TBYP_TBL_FILL_LVL                                                                         0x1280764UL //Access:R    DataWidth:0x7    // Xx Task Bypass Table fill level (in tasks).
+#define UCM_REG_XX_TBYP_TBL_ST_STAT                                                                          0x1280768UL //Access:RC   DataWidth:0x7    // Xx Task Bypass Table sticky status. Reset on read.
+#define UCM_REG_XX_TBYP_TBL_UP_BND                                                                           0x128076cUL //Access:RW   DataWidth:0x7    // Xx Bypass Table (Task) maximum fill level.
+#define UCM_REG_XX_BYP_LOCK_MSG_THR                                                                          0x1280790UL //Access:RW   DataWidth:0x6    // Xx Bypass messages lock threshold. The number of locked messages per LCID is above this threshold is one of conditions to start XxBypass for this LCID.
+#define UCM_REG_XX_PREF_DIR_FILL_LVL                                                                         0x1280794UL //Access:R    DataWidth:0x5    // Xx LCID Arbiter direct prefetch FIFO fill level (in entries).
+#define UCM_REG_XX_PREF_AGGST_FILL_LVL                                                                       0x1280798UL //Access:R    DataWidth:0x5    // Xx LCID Arbiter aggregation store prefetch FIFO fill level (in entries).
+#define UCM_REG_XX_PREF_BYP_FILL_LVL                                                                         0x128079cUL //Access:R    DataWidth:0x5    // Xx LCID Arbiter bypass prefetch FIFO fill level (in entries).
+#define UCM_REG_UNLOCK_MISS                                                                                  0x12807a0UL //Access:RC   DataWidth:0x1    // Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM.
+#define UCM_REG_ERR_AFFINITY_TYPE_E5                                                                         0x12807a4UL //Access:RW   DataWidth:0x2    // Affinity type in case of input message error.
+#define UCM_REG_ERR_EXCLUSIVE_FLG_E5                                                                         0x12807a8UL //Access:RW   DataWidth:0x1    // Exclusive type in case of input message error.
+#define UCM_REG_ERR_SRC_AFFINITY_E5                                                                          0x12807acUL //Access:RW   DataWidth:0x3    // Source affinity in case of input message error.
+#define UCM_REG_XX_BYP_MSG_UP_BND_0_BB_K2                                                                    0x1280770UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define UCM_REG_XX_BYP_MSG_UP_BND_0_E5                                                                       0x12807b0UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define UCM_REG_XX_BYP_MSG_UP_BND_1_BB_K2                                                                    0x1280774UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define UCM_REG_XX_BYP_MSG_UP_BND_1_E5                                                                       0x12807b4UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define UCM_REG_XX_BYP_MSG_UP_BND_2_BB_K2                                                                    0x1280778UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define UCM_REG_XX_BYP_MSG_UP_BND_2_E5                                                                       0x12807b8UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define UCM_REG_XX_BYP_MSG_UP_BND_3_BB_K2                                                                    0x128077cUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define UCM_REG_XX_BYP_MSG_UP_BND_3_E5                                                                       0x12807bcUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define UCM_REG_XX_BYP_MSG_UP_BND_4_BB_K2                                                                    0x1280780UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define UCM_REG_XX_BYP_MSG_UP_BND_4_E5                                                                       0x12807c0UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define UCM_REG_XX_BYP_MSG_UP_BND_5_BB_K2                                                                    0x1280784UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define UCM_REG_XX_BYP_MSG_UP_BND_5_E5                                                                       0x12807c4UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define UCM_REG_XX_BYP_MSG_UP_BND_6_BB_K2                                                                    0x1280788UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define UCM_REG_XX_BYP_MSG_UP_BND_6_E5                                                                       0x12807c8UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define UCM_REG_XX_BYP_MSG_UP_BND_7_BB_K2                                                                    0x128078cUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define UCM_REG_XX_BYP_MSG_UP_BND_7_E5                                                                       0x12807ccUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define UCM_REG_XX_BYP_MSG_UP_BND_8_E5                                                                       0x12807d0UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define UCM_REG_XX_BYP_MSG_UP_BND_9_E5                                                                       0x12807d4UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define UCM_REG_XX_BYP_MSG_UP_BND_10_E5                                                                      0x12807d8UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define UCM_REG_XX_BYP_MSG_UP_BND_11_E5                                                                      0x12807dcUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define UCM_REG_XX_BYP_MSG_UP_BND_12_E5                                                                      0x12807e0UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define UCM_REG_XX_BYP_MSG_UP_BND_13_E5                                                                      0x12807e4UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define UCM_REG_XX_BYP_MSG_UP_BND_14_E5                                                                      0x12807e8UL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define UCM_REG_XX_BYP_MSG_UP_BND_15_E5                                                                      0x12807ecUL //Access:RW   DataWidth:0x5    // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.
+#define UCM_REG_PRCS_AGG_CON_CURR_ST                                                                         0x1280804UL //Access:R    DataWidth:0x4    // Aggregation Connection Processor FSM.
+#define UCM_REG_PRCS_SM_CON_CURR_ST                                                                          0x1280808UL //Access:R    DataWidth:0x2    // STORM Connection Processor FSM.
+#define UCM_REG_PRCS_AGG_TASK_CURR_ST                                                                        0x128080cUL //Access:R    DataWidth:0x4    // Aggregation Task Processor FSM.
+#define UCM_REG_PRCS_SM_TASK_CURR_ST                                                                         0x1280810UL //Access:R    DataWidth:0x2    // STORM Task Processor FSM.
+#define UCM_REG_N_SM_TASK_CTX_LD_0                                                                           0x1280834UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define UCM_REG_N_SM_TASK_CTX_LD_1                                                                           0x1280838UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define UCM_REG_N_SM_TASK_CTX_LD_2                                                                           0x128083cUL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define UCM_REG_N_SM_TASK_CTX_LD_3                                                                           0x1280840UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define UCM_REG_N_SM_TASK_CTX_LD_4                                                                           0x1280844UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define UCM_REG_N_SM_TASK_CTX_LD_5                                                                           0x1280848UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define UCM_REG_N_SM_TASK_CTX_LD_6                                                                           0x128084cUL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define UCM_REG_N_SM_TASK_CTX_LD_7                                                                           0x1280850UL //Access:RW   DataWidth:0x4    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific task type. The offset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
+#define UCM_REG_AGG_CON_FIC_BUF_FILL_LVL                                                                     0x1280854UL //Access:R    DataWidth:0x2    // Aggregation Connection FIC buffer fill level (in messages).
+#define UCM_REG_SM_CON_FIC_BUF_FILL_LVL                                                                      0x1280858UL //Access:R    DataWidth:0x5    // Storm Connection FIC buffer fill level (in messages).
+#define UCM_REG_AGG_CON_FIC_BUF_CRD                                                                          0x128085cUL //Access:RW   DataWidth:0x2    // Aggregation Connection FIC buffer credit (in full message out parts).
+#define UCM_REG_SM_CON_FIC_BUF_CRD                                                                           0x1280860UL //Access:RW   DataWidth:0x2    // Storm Connection FIC buffer credit (in full message out parts).
+#define UCM_REG_AGG_CON_BUF_CRD_AGG                                                                          0x1280864UL //Access:RW   DataWidth:0x3    // Aggregation Connection buffer (data or command) credit (Aggregation group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than Agregation Connection data buffer size=4. In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST and CM_REGISTERS_AGG_CON_CMD_BUF_CRD_DIR.AGG_CON_CMD_BUF_CRD_DIR need be no more than Agregation Connection command buffer size=6.
+#define UCM_REG_AGG_CON_BUF_CRD_AGGST                                                                        0x1280868UL //Access:RW   DataWidth:0x3    // Aggregation Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG need be no more than Agregation Connection data buffer size=4. In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG and CM_REGISTERS_AGG_CON_CMD_BUF_CRD_DIR.AGG_CON_CMD_BUF_CRD_DIR need be no more than Agregation Connection command buffer size=6.
+#define UCM_REG_SM_CON_BUF_CRD_AGGST                                                                         0x128086cUL //Access:RW   DataWidth:0x1    // Storm Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_CON_CMD_BUF_CRD_DIR.SM_CON_CMD_BUF_CRD_DIR need be no more than Storm Connection command buffer size=3.
+#define UCM_REG_AGG_CON_CMD_BUF_CRD_DIR                                                                      0x1280870UL //Access:RW   DataWidth:0x2    // Aggregation Connection command buffer credit (Direct group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG and XCM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than Agregation Connection command buffer size=6.
+#define UCM_REG_SM_CON_CMD_BUF_CRD_DIR                                                                       0x1280874UL //Access:RW   DataWidth:0x2    // Storm Connection command buffer credit (Direct group). In sum with CM_REGISTERS_SM_CON_BUF_CRD_AGGST.SM_CON_BUF_CRD_AGGST need be no more than Storm Connection command buffer size=3.
+#define UCM_REG_AGG_TASK_FIC_BUF_FILL_LVL                                                                    0x1280878UL //Access:R    DataWidth:0x3    // Aggregation Task FIC buffer fill level (in messages).
+#define UCM_REG_SM_TASK_FIC_BUF_FILL_LVL                                                                     0x128087cUL //Access:R    DataWidth:0x4    // Storm Task FIC buffer fill level (in messages).
+#define UCM_REG_AGG_TASK_FIC_BUF_CRD                                                                         0x1280880UL //Access:RW   DataWidth:0x2    // Aggregation Task FIC buffer credit (in full message out parts).
+#define UCM_REG_SM_TASK_FIC_BUF_CRD                                                                          0x1280884UL //Access:RW   DataWidth:0x2    // Storm Task FIC buffer credit (in full message out parts).
+#define UCM_REG_AGG_TASK_BUF_CRD_AGG                                                                         0x1280888UL //Access:RW   DataWidth:0x3    // Aggregation Task buffer (data or command) credit (Aggregation group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST need be no more than Agregation Task data buffer size=4. In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST and CM_REGISTERS_AGG_TASK_CMD_BUF_CRD_DIR.AGG_TASK_CMD_BUF_CRD_DIR need be no more than Agregation Task command buffer size=6.
+#define UCM_REG_AGG_TASK_BUF_CRD_AGGST                                                                       0x128088cUL //Access:RW   DataWidth:0x3    // Aggregation Task buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG need be no more than Agregation Task data buffer size=4. In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG and CM_REGISTERS_AGG_TASK_CMD_BUF_CRD_DIR.AGG_TASK_CMD_BUF_CRD_DIR need be no more than Agregation Task command buffer size=6.
+#define UCM_REG_SM_TASK_BUF_CRD_AGGST                                                                        0x1280890UL //Access:RW   DataWidth:0x1    // Storm Task buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_TASK_CMD_BUF_CRD_DIR.SM_TASK_CMD_BUF_CRD_DIR need be no more than Storm Task command buffer size=3.
+#define UCM_REG_AGG_TASK_CMD_BUF_CRD_DIR                                                                     0x1280894UL //Access:RW   DataWidth:0x2    // Aggregation Task command buffer credit (Direct group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG and CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST need be no more than Agregation Task command buffer size=6.
+#define UCM_REG_SM_TASK_CMD_BUF_CRD_DIR                                                                      0x1280898UL //Access:RW   DataWidth:0x2    // Storm Task command buffer credit (Direct group). In sum with CM_REGISTERS_SM_TASK_BUF_CRD_AGGST.SM_TASK_BUF_CRD_AGGST need be no more than Storm Task command buffer size=3.
+#define UCM_REG_TRANS_DATA_BUF_CRD_DIR                                                                       0x128089cUL //Access:RW   DataWidth:0x2    // Transparent data buffer credit (Direct group).
+#define UCM_REG_AGG_TASK_CTX_SIZE_0                                                                          0x12808c0UL //Access:RW   DataWidth:0x3    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define UCM_REG_AGG_TASK_CTX_SIZE_1                                                                          0x12808c4UL //Access:RW   DataWidth:0x3    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define UCM_REG_AGG_TASK_CTX_SIZE_2                                                                          0x12808c8UL //Access:RW   DataWidth:0x3    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define UCM_REG_AGG_TASK_CTX_SIZE_3                                                                          0x12808ccUL //Access:RW   DataWidth:0x3    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define UCM_REG_AGG_TASK_CTX_SIZE_4                                                                          0x12808d0UL //Access:RW   DataWidth:0x3    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define UCM_REG_AGG_TASK_CTX_SIZE_5                                                                          0x12808d4UL //Access:RW   DataWidth:0x3    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define UCM_REG_AGG_TASK_CTX_SIZE_6                                                                          0x12808d8UL //Access:RW   DataWidth:0x3    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define UCM_REG_AGG_TASK_CTX_SIZE_7                                                                          0x12808dcUL //Access:RW   DataWidth:0x3    // Aggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: 2 REGQ aligned or 3 aligned whichever is less, or 3.
+#define UCM_REG_SM_CON_CTX_SIZE                                                                              0x12808e0UL //Access:RW   DataWidth:0x5    // STORM Connnection context per LCID size (REGQ). Default context size of 13 (REGQ) complies to 320 LCIDs. Maximum context size per LCID is 24. Maximum number of LCIDs allowed at maximum context size per LCID is 160. If not at default value need to be 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER((320*INTEGER(13/2))/(24/2)).
+#define UCM_REG_SM_TASK_CTX_SIZE                                                                             0x12808e4UL //Access:RW   DataWidth:0x4    // STORM Task context per LTID size (REGQ). Default context size of 3 (REGQ) complies to 320 LTIDs. Maximum context size per LTID is 12. Maximum number of LTIDs allowed at maximum context size per LTID is 52. If not at default value need to be 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER((320*INTEGER(3/2))/(12/2)).
+#define UCM_REG_CON_PHY_Q0                                                                                   0x1280904UL //Access:RW   DataWidth:0x9    // Physical queue connection number (queue number 0).
+#define UCM_REG_CON_PHY_Q1                                                                                   0x1280908UL //Access:RW   DataWidth:0x9    // Physical queue connection number (queue number 1).
+#define UCM_REG_TASK_PHY_Q0                                                                                  0x128090cUL //Access:RW   DataWidth:0x7    // Physical queue task number (queue number 0).
+#define UCM_REG_TASK_PHY_Q1                                                                                  0x1280910UL //Access:RW   DataWidth:0x7    // Physical queue task number (queue number 1).
+#define UCM_REG_AGG_CON_RULE0_Q                                                                              0x1280930UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define UCM_REG_AGG_CON_RULE1_Q                                                                              0x1280934UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define UCM_REG_AGG_CON_RULE2_Q                                                                              0x1280938UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define UCM_REG_AGG_CON_RULE3_Q                                                                              0x128093cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define UCM_REG_AGG_CON_RULE4_Q                                                                              0x1280940UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define UCM_REG_AGG_CON_RULE5_Q                                                                              0x1280944UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define UCM_REG_AGG_CON_RULE6_Q                                                                              0x1280948UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define UCM_REG_AGG_CON_RULE7_Q                                                                              0x128094cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define UCM_REG_AGG_CON_RULE8_Q                                                                              0x1280950UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). In XCM only if value is 4, then special merge routine is fulfilled: If 'en_qindex_20_merge" is 0 then Queue index 0 is enable. If 'en_qindex_20_merge" is 1 then Queue index 2 is enable.
+#define UCM_REG_AGG_TASK_RULE0_Q                                                                             0x1280968UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_TASK_RULE1_Q                                                                             0x128096cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_TASK_RULE2_Q                                                                             0x1280970UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_TASK_RULE3_Q                                                                             0x1280974UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_TASK_RULE4_Q                                                                             0x1280978UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_TASK_RULE5_Q                                                                             0x128097cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_TASK_RULE6_Q                                                                             0x1280980UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_TASK_RULE7_Q_E5                                                                          0x1280984UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_TASK_RULE8_Q_E5                                                                          0x1280988UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_CM_TASK_EVENT_ID_BWIDTH_0_E5                                                                 0x128098cUL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define UCM_REG_CM_TASK_EVENT_ID_BWIDTH_1_E5                                                                 0x1280990UL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define UCM_REG_CM_TASK_EVENT_ID_BWIDTH_2_E5                                                                 0x1280994UL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define UCM_REG_CM_TASK_EVENT_ID_BWIDTH_3_E5                                                                 0x1280998UL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define UCM_REG_CM_TASK_EVENT_ID_BWIDTH_4_E5                                                                 0x128099cUL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define UCM_REG_CM_TASK_EVENT_ID_BWIDTH_5_E5                                                                 0x12809a0UL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define UCM_REG_CM_TASK_EVENT_ID_BWIDTH_6_E5                                                                 0x12809a4UL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define UCM_REG_CM_TASK_EVENT_ID_BWIDTH_7_E5                                                                 0x12809a8UL //Access:RW   DataWidth:0x3    // EventID bit width per task type.
+#define UCM_REG_IN_PRCS_TBL_CRD_AGG                                                                          0x1280a04UL //Access:RW   DataWidth:0x4    // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.IN_PRCS_TBL_CRD_AGGST need be no more than In-process table size=12.
+#define UCM_REG_IN_PRCS_TBL_CRD_AGGST                                                                        0x1280a08UL //Access:RW   DataWidth:0x4    // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGG.IN_PRCS_TBL_CRD_AGG need be no more than In-process table size=12.
+#define UCM_REG_IN_PRCS_TBL_FILL_LVL                                                                         0x1280a0cUL //Access:R    DataWidth:0x4    // In-process Table fill level  (in messages).
+#define UCM_REG_IN_PRCS_TBL_ALMOST_FULL                                                                      0x1280a10UL //Access:R    DataWidth:0x1    // In-process Table almost full.
+#define UCM_REG_QMCON_CURR_ST                                                                                0x1280a14UL //Access:R    DataWidth:0x3    // QM connection registration FSM current state.
+#define UCM_REG_QMTASK_CURR_ST                                                                               0x1280a18UL //Access:R    DataWidth:0x3    // QM task registration FSM current state.
+#define UCM_REG_TMCON_CURR_ST                                                                                0x1280a1cUL //Access:R    DataWidth:0x1    // TM connection output FSM current state.
+#define UCM_REG_TMTASK_CURR_ST                                                                               0x1280a20UL //Access:R    DataWidth:0x1    // TM task output FSM current state.
+#define UCM_REG_CCFC_CURR_ST                                                                                 0x1280a24UL //Access:R    DataWidth:0x1    // CFC connection output FSM current state.
+#define UCM_REG_TCFC_CURR_ST                                                                                 0x1280a28UL //Access:R    DataWidth:0x1    // CFC task output FSM current state.
+#define UCM_REG_CMPL_DIR_CURR_ST                                                                             0x1280a2cUL //Access:R    DataWidth:0x4    // Direct Completer FSM current state.
+#define UCM_REG_XX_BYP_CON_STATE_EVNT_ID_FLG                                                                 0x1280a30UL //Access:RW   DataWidth:0x1    // If set, Xx connection bypass state will be added in calculation of CM output Event ID.
+#define UCM_REG_XX_BYP_TASK_STATE_EVNT_ID_FLG                                                                0x1280a34UL //Access:RW   DataWidth:0x1    // If set, Xx task bypass state will be added in calculation of CM output Event ID.
+#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_0_E5                                                                  0x1280a38UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_1_E5                                                                  0x1280a3cUL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_2_E5                                                                  0x1280a40UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_3_E5                                                                  0x1280a44UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_4_E5                                                                  0x1280a48UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_5_E5                                                                  0x1280a4cUL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_6_E5                                                                  0x1280a50UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_7_E5                                                                  0x1280a54UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_8_E5                                                                  0x1280a58UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_9_E5                                                                  0x1280a5cUL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_10_E5                                                                 0x1280a60UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_11_E5                                                                 0x1280a64UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_12_E5                                                                 0x1280a68UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_13_E5                                                                 0x1280a6cUL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_14_E5                                                                 0x1280a70UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_15_E5                                                                 0x1280a74UL //Access:RW   DataWidth:0x3    // EventID bit width per connection type.
+#define UCM_REG_CCFC_INIT_CRD                                                                                0x1280a84UL //Access:RW   DataWidth:0x4    // CCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.
+#define UCM_REG_TCFC_INIT_CRD                                                                                0x1280a88UL //Access:RW   DataWidth:0x4    // TCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.
+#define UCM_REG_QM_INIT_CRD0                                                                                 0x1280a8cUL //Access:RW   DataWidth:0x5    // QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 16.Write writes the initial credit value; read returns the current value of the credit counter.
+#define UCM_REG_TM_INIT_CRD                                                                                  0x1280a90UL //Access:RW   DataWidth:0x4    // Timers output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.
+#define UCM_REG_FIC_INIT_CRD                                                                                 0x1280a94UL //Access:RW   DataWidth:0x6    // FIC output initial credit. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 44 at start-up.
+#define UCM_REG_DIR_BYP_MSG_CNT                                                                              0x1280aa4UL //Access:RC   DataWidth:0x20   // Counter of direct bypassed messages.
+#define UCM_REG_XSDM_LENGTH_MIS                                                                              0x1280aa8UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at XSDM interface.
+#define UCM_REG_YSDM_LENGTH_MIS                                                                              0x1280aacUL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at YSDM interface.
+#define UCM_REG_USDM_LENGTH_MIS                                                                              0x1280ab0UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at USDM interface.
+#define UCM_REG_DORQ_LENGTH_MIS                                                                              0x1280ab4UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at the dorq interface.
+#define UCM_REG_PBF_LENGTH_MIS                                                                               0x1280ab8UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at PBF interface.
+#define UCM_REG_RDIF_LENGTH_MIS                                                                              0x1280abcUL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at RDIF interface.
+#define UCM_REG_TDIF_LENGTH_MIS                                                                              0x1280ac0UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at TDIF interface.
+#define UCM_REG_MULD_LENGTH_MIS                                                                              0x1280ac4UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at MULD interface.
+#define UCM_REG_YULD_LENGTH_MIS_BB_K2                                                                        0x1280ac8UL //Access:RC   DataWidth:0x1    // Set at message length mismatch (relative to last indication) at YULD interface.
+#define UCM_REG_GRC_BUF_EMPTY                                                                                0x1280accUL //Access:R    DataWidth:0x1    // Input Stage GRC buffer is empty.
+#define UCM_REG_GRC_BUF_STATUS                                                                               0x1280ad0UL //Access:R    DataWidth:0x6    // Input Stage GRC buffer status.
+#define UCM_REG_STORM_MSG_CNTR                                                                               0x1280ad4UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the STORM input.
+#define UCM_REG_XSDM_MSG_CNTR                                                                                0x1280ad8UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input XSDM.
+#define UCM_REG_YSDM_MSG_CNTR                                                                                0x1280adcUL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input YSDM.
+#define UCM_REG_USDM_MSG_CNTR                                                                                0x1280ae0UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input USDM.
+#define UCM_REG_RDIF_MSG_CNTR                                                                                0x1280ae4UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input RDIF.
+#define UCM_REG_TDIF_MSG_CNTR                                                                                0x1280ae8UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input TDIF.
+#define UCM_REG_MULD_MSG_CNTR                                                                                0x1280aecUL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input MULD.
+#define UCM_REG_YULD_MSG_CNTR_BB_K2                                                                          0x1280af0UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the input YULD.
+#define UCM_REG_DORQ_MSG_CNTR                                                                                0x1280af4UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at  input DORQ.
+#define UCM_REG_PBF_MSG_CNTR                                                                                 0x1280af8UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at input PBF.
+#define UCM_REG_QM_P_MSG_CNTR                                                                                0x1280afcUL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the QM input (primary).
+#define UCM_REG_QM_S_MSG_CNTR                                                                                0x1280b00UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the QM input (secondary).
+#define UCM_REG_TM_MSG_CNTR                                                                                  0x1280b04UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at the Timers input.
+#define UCM_REG_IS_GRC                                                                                       0x1280b08UL //Access:W    DataWidth:0x20   // Used to write the GRC message. Write only. To distinguish if the register can be accessed to write GRC message                           polling of CM_REGISTERS.GRC_BUF_EMPTY need to be done
+#define UCM_REG_IS_QM_P_FILL_LVL                                                                             0x1280b0cUL //Access:R    DataWidth:0x5    // Number of QREGs (128b) of data in QM Primary Input Stage (except of bypass).
+#define UCM_REG_IS_QM_S_FILL_LVL                                                                             0x1280b10UL //Access:R    DataWidth:0x5    // Number of QREGs (128b) of data in QM Secondary Input Stage (except of bypass).
+#define UCM_REG_IS_TM_FILL_LVL                                                                               0x1280b14UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in TM Input Stage.
+#define UCM_REG_IS_STORM_FILL_LVL                                                                            0x1280b18UL //Access:R    DataWidth:0x5    // Number of entries (2 QREGs each) of data in STORM Input Stage.
+#define UCM_REG_IS_XSDM_FILL_LVL                                                                             0x1280b1cUL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in XSDM Input Stage.
+#define UCM_REG_IS_YSDM_FILL_LVL                                                                             0x1280b20UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in YSDM Input Stage.
+#define UCM_REG_IS_USDM_FILL_LVL                                                                             0x1280b24UL //Access:R    DataWidth:0x4    // Number of QREGs (128b) of data in USDM Input Stage.
+#define UCM_REG_IS_RDIF_FILL_LVL                                                                             0x1280b28UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in RDIF Input Stage.
+#define UCM_REG_IS_TDIF_FILL_LVL                                                                             0x1280b2cUL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in TDIF Input Stage.
+#define UCM_REG_IS_MULD_FILL_LVL                                                                             0x1280b30UL //Access:R    DataWidth:0x6    // Number of QREGs (128b) of data in MULD Input Stage.
+#define UCM_REG_IS_YULD_FILL_LVL_BB_K2                                                                       0x1280b34UL //Access:R    DataWidth:0x4    // Number of QREGs (128b) of data in YULD Input Stage.
+#define UCM_REG_IS_DORQ_FILL_LVL                                                                             0x1280b38UL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in DORQ Input Stage.
+#define UCM_REG_IS_PBF_FILL_LVL                                                                              0x1280b3cUL //Access:R    DataWidth:0x3    // Number of QREGs (128b) of data in PBF Input Stage.
+#define UCM_REG_FIC_MSG_CNTR                                                                                 0x1280b44UL //Access:RC   DataWidth:0x1c   // Counter of the output messages at FIC interfaces.
+#define UCM_REG_QM_OUT_CNTR                                                                                  0x1280b48UL //Access:RC   DataWidth:0x1c   // Counter of the output QM commands.
+#define UCM_REG_TM_OUT_CNTR                                                                                  0x1280b4cUL //Access:RC   DataWidth:0x1c   // Counter of the output Timers commands.
+#define UCM_REG_DONE0_CNTR                                                                                   0x1280b50UL //Access:RC   DataWidth:0x1c   // Counter of the output Done0.
+#define UCM_REG_DONE1_CNTR                                                                                   0x1280b54UL //Access:RC   DataWidth:0x1c   // Counter of the output Done1.
+#define UCM_REG_DONE2_CNTR                                                                                   0x1280b58UL //Access:RC   DataWidth:0x1c   // Counter of the output Done2.
+#define UCM_REG_DONE3_CNTR                                                                                   0x1280b5cUL //Access:RC   DataWidth:0x1c   // Counter of the output Done3.
+#define UCM_REG_CCFC_CNTR                                                                                    0x1280b60UL //Access:RC   DataWidth:0x1c   // Counter of the output CCFC.
+#define UCM_REG_TCFC_CNTR                                                                                    0x1280b64UL //Access:RC   DataWidth:0x1c   // Counter of the output TCFC.
+#define UCM_REG_ECO_RESERVED                                                                                 0x1280b84UL //Access:RW   DataWidth:0x8    // Chicken bits.
+#define UCM_REG_IS_FOC_USEM_NXT_INF_UNIT                                                                     0x1280b88UL //Access:R    DataWidth:0x5    // Debug read from USEM Input stage buffer: number of reads to next information unit.
+#define UCM_REG_IS_FOC_PBF_NXT_INF_UNIT                                                                      0x1280b8cUL //Access:R    DataWidth:0x6    // Debug read from PBF Input stage buffer: number of reads to next information unit.
+#define UCM_REG_IS_FOC_DORQ_NXT_INF_UNIT                                                                     0x1280b90UL //Access:R    DataWidth:0x6    // Debug read from DORQ Input stage buffer: number of reads to next information unit.
+#define UCM_REG_IS_FOC_RDIF_NXT_INF_UNIT                                                                     0x1280b94UL //Access:R    DataWidth:0x6    // Debug read from RDIF Input stage buffer: number of reads to next information unit.
+#define UCM_REG_IS_FOC_TDIF_NXT_INF_UNIT                                                                     0x1280b98UL //Access:R    DataWidth:0x6    // Debug read from TDIF Input stage buffer: number of reads to next information unit.
+#define UCM_REG_IS_FOC_USDM_NXT_INF_UNIT                                                                     0x1280b9cUL //Access:R    DataWidth:0x6    // Debug read from USDM Input stage buffer: number of reads to next information unit.
+#define UCM_REG_IS_FOC_XSDM_NXT_INF_UNIT                                                                     0x1280ba0UL //Access:R    DataWidth:0x6    // Debug read from XSDM Input stage buffer: number of reads to next information unit.
+#define UCM_REG_IS_FOC_YSDM_NXT_INF_UNIT                                                                     0x1280ba4UL //Access:R    DataWidth:0x6    // Debug read from YSDM Input stage buffer: number of reads to next information unit.
+#define UCM_REG_IS_FOC_MULD_NXT_INF_UNIT                                                                     0x1280ba8UL //Access:R    DataWidth:0x5    // Debug read from MULD Input stage buffer: number of reads to next information unit.
+#define UCM_REG_IS_FOC_YULD_NXT_INF_UNIT_BB_K2                                                               0x1280bacUL //Access:R    DataWidth:0x6    // Debug read from YULD Input stage buffer: number of reads to next information unit.
+#define UCM_REG_IS_FOC_USEM                                                                                  0x1280c00UL //Access:R    DataWidth:0x20   // Debug read from USEM Input stage buffer with 32-bits granularity. Read only.
+#define UCM_REG_IS_FOC_USEM_SIZE_BB_K2                                                                       204
+#define UCM_REG_IS_FOC_USEM_SIZE_E5                                                                          208
+#define UCM_REG_IS_FOC_PBF                                                                                   0x1281000UL //Access:R    DataWidth:0x20   // Debug read from PBF Input stage buffer with 32-bits granularity. Read only.
+#define UCM_REG_IS_FOC_PBF_SIZE                                                                              28
+#define UCM_REG_IS_FOC_DORQ                                                                                  0x1281080UL //Access:R    DataWidth:0x20   // Debug read from DORQ Input stage buffer with 32-bits granularity. Read only.
+#define UCM_REG_IS_FOC_DORQ_SIZE                                                                             24
+#define UCM_REG_IS_FOC_RDIF                                                                                  0x1281100UL //Access:R    DataWidth:0x20   // Debug read from RDIF Input stage buffer with 32-bits granularity. Read only.
+#define UCM_REG_IS_FOC_RDIF_SIZE                                                                             12
+#define UCM_REG_IS_FOC_TDIF                                                                                  0x1281140UL //Access:R    DataWidth:0x20   // Debug read from TDIF Input stage buffer with 32-bits granularity. Read only.
+#define UCM_REG_IS_FOC_TDIF_SIZE                                                                             12
+#define UCM_REG_IS_FOC_USDM                                                                                  0x1281200UL //Access:R    DataWidth:0x20   // Debug read from USDM Input stage buffer with 32-bits granularity. Read only.
+#define UCM_REG_IS_FOC_USDM_SIZE                                                                             36
+#define UCM_REG_IS_FOC_XSDM                                                                                  0x1281300UL //Access:R    DataWidth:0x20   // Debug read from XSDM Input stage buffer with 32-bits granularity. Read only.
+#define UCM_REG_IS_FOC_XSDM_SIZE                                                                             12
+#define UCM_REG_IS_FOC_YSDM                                                                                  0x1281340UL //Access:R    DataWidth:0x20   // Debug read from YSDM Input stage buffer with 32-bits granularity. Read only.
+#define UCM_REG_IS_FOC_YSDM_SIZE                                                                             12
+#define UCM_REG_IS_FOC_YULD_BB_K2                                                                            0x1281600UL //Access:R    DataWidth:0x20   // Debug read from YULD Input stage buffer with 32-bits granularity. Read only.
+#define UCM_REG_IS_FOC_YULD_SIZE                                                                             36
+#define UCM_REG_CTX_RBC_ACCS                                                                                 0x1281700UL //Access:RW   DataWidth:0x10   // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - offset (in REGs (32b)) within LCID/LTID. The procedure to read context is: first define base address and offset; then read context with one of the following registers: CM_REGISTERS_AGG_CON_CTX.AGG_CON_CTX CM_REGISTERS_SM_CON_CTX.SM_CON_CTX CM_REGISTERS_AGG_TASK_CTX.AGG_TASK_CTX CM_REGISTERS_SM_TASK_CTX.SM_TASK_CTX
+#define UCM_REG_AGG_CON_CTX                                                                                  0x1281704UL //Access:RW   DataWidth:0x20   // Access is allowed only on idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The address base (LCID) and offset within LCID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to Aggregation Connection context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.
+#define UCM_REG_AGG_TASK_CTX                                                                                 0x1281708UL //Access:RW   DataWidth:0x20   // Access is allowed only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The address base (LTID) and offset within LTID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to Aggregation Task context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.
+#define UCM_REG_SM_CON_CTX                                                                                   0x128170cUL //Access:RW   DataWidth:0x20   // Access is allowed only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The address base (LCID) and offset within LCID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to STORM Connection context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.
+#define UCM_REG_SM_TASK_CTX                                                                                  0x1281710UL //Access:RW   DataWidth:0x20   // Access is allowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The address base (LTID) and offset within LTID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to STORM Task context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.
+#define UCM_REG_XX_CBYP_TBL                                                                                  0x1281720UL //Access:R    DataWidth:0xf    // Xx Connection Bypass Table.
+#define UCM_REG_XX_CBYP_TBL_SIZE                                                                             8
+#define UCM_REG_XX_TBYP_TBL                                                                                  0x1281800UL //Access:R    DataWidth:0xf    // Xx Task Bypass Table.
+#define UCM_REG_XX_TBYP_TBL_SIZE_BB_K2                                                                       24
+#define UCM_REG_XX_TBYP_TBL_SIZE_E5                                                                          64
+#define UCM_REG_XX_LCID_CAM                                                                                  0x1281900UL //Access:R    DataWidth:0xa    // Debug only. Read only access to LCID CAM in XX protection mechanism.
+#define UCM_REG_XX_LCID_CAM_SIZE_BB_K2                                                                       24
+#define UCM_REG_XX_LCID_CAM_SIZE_E5                                                                          64
+#define UCM_REG_XX_TBL                                                                                       0x1281a00UL //Access:R    DataWidth:0x18   // Indirect access to the XX table of the XX protection mechanism. The fields are: [0] - Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: PCM - [9:8]; M/T/U/X/YCM - [17:12]; Next pointer: PCM - [11:10]; M/T/U/X/YCM - [23:18];
+#define UCM_REG_XX_TBL_SIZE_BB_K2                                                                            24
+#define UCM_REG_XX_TBL_SIZE_E5                                                                               64
+#define UCM_REG_XX_DSCR_TBL                                                                                  0x1281b00UL //Access:RW   DataWidth:0x1e   // Indirect access to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [13:9];PCM [14:9]; TCM [13:9]; UCM [13:9];XCM [10:9];YCM[13:9]); Next pointer (MCM [19:14]; PCM [16:15]; TCM[19:14]; UCM [19:14]; XCM [16:11]; YCM [19:14]); LTID (MCM [28:20]; PCM [25:17] - reserved; TCM[28:20]; UCM [28:20]; XCM [25:17] - reserved; YCM [28:20]). Task Domain Exist (MCM [29]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - reserved; YCM [29]). A free link list in the XX descriptor table should be build. This is done by writing the following values to all effective entries in the table:xx_descr_table[i].next_pointer = i+1 (i=0 - (xx_msg_up_bnd-2)); xx_descr_table[i].next_pointer= 0 (i=xx_msg_up_bnd-1). The value of i is between 0 to the configured (not default) value of (xx_msg_up_bnd-1). The not effective entries (those which succeed the last effective entry with index (xx_msg_up_bnd-1)) can be initialized to any value for initialization procedure simplicity seek.
+#define UCM_REG_XX_DSCR_TBL_SIZE                                                                             64
+#define UCM_REG_TM_CON_EVNT_ID_0_BB_K2                                                                       0x1280524UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define UCM_REG_TM_CON_EVNT_ID_0_E5                                                                          0x1281c00UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define UCM_REG_TM_CON_EVNT_ID_1_BB_K2                                                                       0x1280528UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define UCM_REG_TM_CON_EVNT_ID_1_E5                                                                          0x1281c04UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define UCM_REG_TM_CON_EVNT_ID_2_BB_K2                                                                       0x128052cUL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define UCM_REG_TM_CON_EVNT_ID_2_E5                                                                          0x1281c08UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define UCM_REG_TM_CON_EVNT_ID_3_BB_K2                                                                       0x1280530UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define UCM_REG_TM_CON_EVNT_ID_3_E5                                                                          0x1281c0cUL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define UCM_REG_TM_CON_EVNT_ID_4_BB_K2                                                                       0x1280534UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define UCM_REG_TM_CON_EVNT_ID_4_E5                                                                          0x1281c10UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define UCM_REG_TM_CON_EVNT_ID_5_BB_K2                                                                       0x1280538UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define UCM_REG_TM_CON_EVNT_ID_5_E5                                                                          0x1281c14UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define UCM_REG_TM_CON_EVNT_ID_6_BB_K2                                                                       0x128053cUL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define UCM_REG_TM_CON_EVNT_ID_6_E5                                                                          0x1281c18UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define UCM_REG_TM_CON_EVNT_ID_7_BB_K2                                                                       0x1280540UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.:
+#define UCM_REG_TM_CON_EVNT_ID_7_E5                                                                          0x1281c1cUL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.:
+#define UCM_REG_TM_CON_EVNT_ID_8_E5                                                                          0x1281c20UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define UCM_REG_TM_CON_EVNT_ID_9_E5                                                                          0x1281c24UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define UCM_REG_TM_CON_EVNT_ID_10_E5                                                                         0x1281c28UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define UCM_REG_TM_CON_EVNT_ID_11_E5                                                                         0x1281c2cUL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define UCM_REG_TM_CON_EVNT_ID_12_E5                                                                         0x1281c30UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define UCM_REG_TM_CON_EVNT_ID_13_E5                                                                         0x1281c34UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define UCM_REG_TM_CON_EVNT_ID_14_E5                                                                         0x1281c38UL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.
+#define UCM_REG_TM_CON_EVNT_ID_15_E5                                                                         0x1281c3cUL //Access:RW   DataWidth:0x8    // TM connection Event ID per connection type.:
+#define UCM_REG_N_SM_CON_CTX_LD_0_BB_K2                                                                      0x1280814UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define UCM_REG_N_SM_CON_CTX_LD_0_E5                                                                         0x1281c40UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define UCM_REG_N_SM_CON_CTX_LD_1_BB_K2                                                                      0x1280818UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define UCM_REG_N_SM_CON_CTX_LD_1_E5                                                                         0x1281c44UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define UCM_REG_N_SM_CON_CTX_LD_2_BB_K2                                                                      0x128081cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define UCM_REG_N_SM_CON_CTX_LD_2_E5                                                                         0x1281c48UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define UCM_REG_N_SM_CON_CTX_LD_3_BB_K2                                                                      0x1280820UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define UCM_REG_N_SM_CON_CTX_LD_3_E5                                                                         0x1281c4cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define UCM_REG_N_SM_CON_CTX_LD_4_BB_K2                                                                      0x1280824UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define UCM_REG_N_SM_CON_CTX_LD_4_E5                                                                         0x1281c50UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define UCM_REG_N_SM_CON_CTX_LD_5_BB_K2                                                                      0x1280828UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define UCM_REG_N_SM_CON_CTX_LD_5_E5                                                                         0x1281c54UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define UCM_REG_N_SM_CON_CTX_LD_6_BB_K2                                                                      0x128082cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define UCM_REG_N_SM_CON_CTX_LD_6_E5                                                                         0x1281c58UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define UCM_REG_N_SM_CON_CTX_LD_7_BB_K2                                                                      0x1280830UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define UCM_REG_N_SM_CON_CTX_LD_7_E5                                                                         0x1281c5cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
+#define UCM_REG_N_SM_CON_CTX_LD_8_E5                                                                         0x1281c60UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define UCM_REG_N_SM_CON_CTX_LD_9_E5                                                                         0x1281c64UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define UCM_REG_N_SM_CON_CTX_LD_10_E5                                                                        0x1281c68UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 10).
+#define UCM_REG_N_SM_CON_CTX_LD_11_E5                                                                        0x1281c6cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define UCM_REG_N_SM_CON_CTX_LD_12_E5                                                                        0x1281c70UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define UCM_REG_N_SM_CON_CTX_LD_13_E5                                                                        0x1281c74UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define UCM_REG_N_SM_CON_CTX_LD_14_E5                                                                        0x1281c78UL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define UCM_REG_N_SM_CON_CTX_LD_15_E5                                                                        0x1281c7cUL //Access:RW   DataWidth:0x5    // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16).
+#define UCM_REG_AGG_CON_CTX_SIZE_0_BB_K2                                                                     0x12808a0UL //Access:RW   DataWidth:0x2    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less or 2.
+#define UCM_REG_AGG_CON_CTX_SIZE_0_E5                                                                        0x1281c80UL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define UCM_REG_AGG_CON_CTX_SIZE_1_BB_K2                                                                     0x12808a4UL //Access:RW   DataWidth:0x2    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define UCM_REG_AGG_CON_CTX_SIZE_1_E5                                                                        0x1281c84UL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define UCM_REG_AGG_CON_CTX_SIZE_2_BB_K2                                                                     0x12808a8UL //Access:RW   DataWidth:0x2    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define UCM_REG_AGG_CON_CTX_SIZE_2_E5                                                                        0x1281c88UL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define UCM_REG_AGG_CON_CTX_SIZE_3_BB_K2                                                                     0x12808acUL //Access:RW   DataWidth:0x2    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define UCM_REG_AGG_CON_CTX_SIZE_3_E5                                                                        0x1281c8cUL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define UCM_REG_AGG_CON_CTX_SIZE_4_BB_K2                                                                     0x12808b0UL //Access:RW   DataWidth:0x2    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define UCM_REG_AGG_CON_CTX_SIZE_4_E5                                                                        0x1281c90UL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define UCM_REG_AGG_CON_CTX_SIZE_5_BB_K2                                                                     0x12808b4UL //Access:RW   DataWidth:0x2    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define UCM_REG_AGG_CON_CTX_SIZE_5_E5                                                                        0x1281c94UL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define UCM_REG_AGG_CON_CTX_SIZE_6_BB_K2                                                                     0x12808b8UL //Access:RW   DataWidth:0x2    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define UCM_REG_AGG_CON_CTX_SIZE_6_E5                                                                        0x1281c98UL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define UCM_REG_AGG_CON_CTX_SIZE_7_BB_K2                                                                     0x12808bcUL //Access:RW   DataWidth:0x2    // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define UCM_REG_AGG_CON_CTX_SIZE_7_E5                                                                        0x1281c9cUL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define UCM_REG_AGG_CON_CTX_SIZE_8_E5                                                                        0x1281ca0UL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less or 2.
+#define UCM_REG_AGG_CON_CTX_SIZE_9_E5                                                                        0x1281ca4UL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define UCM_REG_AGG_CON_CTX_SIZE_10_E5                                                                       0x1281ca8UL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define UCM_REG_AGG_CON_CTX_SIZE_11_E5                                                                       0x1281cacUL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define UCM_REG_AGG_CON_CTX_SIZE_12_E5                                                                       0x1281cb0UL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define UCM_REG_AGG_CON_CTX_SIZE_13_E5                                                                       0x1281cb4UL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define UCM_REG_AGG_CON_CTX_SIZE_14_E5                                                                       0x1281cb8UL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define UCM_REG_AGG_CON_CTX_SIZE_15_E5                                                                       0x1281cbcUL //Access:RW   DataWidth:0x2    // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.
+#define UCM_REG_QM_CON_BASE_EVNT_ID_0_BB_K2                                                                  0x1280404UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define UCM_REG_QM_CON_BASE_EVNT_ID_0_E5                                                                     0x1281cc0UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define UCM_REG_QM_CON_BASE_EVNT_ID_1_BB_K2                                                                  0x1280408UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define UCM_REG_QM_CON_BASE_EVNT_ID_1_E5                                                                     0x1281cc4UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define UCM_REG_QM_CON_BASE_EVNT_ID_2_BB_K2                                                                  0x128040cUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define UCM_REG_QM_CON_BASE_EVNT_ID_2_E5                                                                     0x1281cc8UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define UCM_REG_QM_CON_BASE_EVNT_ID_3_BB_K2                                                                  0x1280410UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define UCM_REG_QM_CON_BASE_EVNT_ID_3_E5                                                                     0x1281cccUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define UCM_REG_QM_CON_BASE_EVNT_ID_4_BB_K2                                                                  0x1280414UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define UCM_REG_QM_CON_BASE_EVNT_ID_4_E5                                                                     0x1281cd0UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define UCM_REG_QM_CON_BASE_EVNT_ID_5_BB_K2                                                                  0x1280418UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define UCM_REG_QM_CON_BASE_EVNT_ID_5_E5                                                                     0x1281cd4UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define UCM_REG_QM_CON_BASE_EVNT_ID_6_BB_K2                                                                  0x128041cUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define UCM_REG_QM_CON_BASE_EVNT_ID_6_E5                                                                     0x1281cd8UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define UCM_REG_QM_CON_BASE_EVNT_ID_7_BB_K2                                                                  0x1280420UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define UCM_REG_QM_CON_BASE_EVNT_ID_7_E5                                                                     0x1281cdcUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define UCM_REG_QM_CON_BASE_EVNT_ID_8_E5                                                                     0x1281ce0UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define UCM_REG_QM_CON_BASE_EVNT_ID_9_E5                                                                     0x1281ce4UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define UCM_REG_QM_CON_BASE_EVNT_ID_10_E5                                                                    0x1281ce8UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define UCM_REG_QM_CON_BASE_EVNT_ID_11_E5                                                                    0x1281cecUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define UCM_REG_QM_CON_BASE_EVNT_ID_12_E5                                                                    0x1281cf0UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define UCM_REG_QM_CON_BASE_EVNT_ID_13_E5                                                                    0x1281cf4UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define UCM_REG_QM_CON_BASE_EVNT_ID_14_E5                                                                    0x1281cf8UL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define UCM_REG_QM_CON_BASE_EVNT_ID_15_E5                                                                    0x1281cfcUL //Access:RW   DataWidth:0x8    // QM connection base Event ID per connection type.
+#define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_0_BB_K2                                                             0x1280444UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_0_E5                                                                0x1281d00UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_1_BB_K2                                                             0x1280448UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_1_E5                                                                0x1281d04UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_2_BB_K2                                                             0x128044cUL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_2_E5                                                                0x1281d08UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_3_BB_K2                                                             0x1280450UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_3_E5                                                                0x1281d0cUL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_4_BB_K2                                                             0x1280454UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_4_E5                                                                0x1281d10UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_5_BB_K2                                                             0x1280458UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_5_E5                                                                0x1281d14UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_6_BB_K2                                                             0x128045cUL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_6_E5                                                                0x1281d18UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_7_BB_K2                                                             0x1280460UL //Access:RW   DataWidth:0x4    // QM agggregation connection context part size per connection type.
+#define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_7_E5                                                                0x1281d1cUL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_8_E5                                                                0x1281d20UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_9_E5                                                                0x1281d24UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_10_E5                                                               0x1281d28UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_11_E5                                                               0x1281d2cUL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_12_E5                                                               0x1281d30UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_13_E5                                                               0x1281d34UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_14_E5                                                               0x1281d38UL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_15_E5                                                               0x1281d3cUL //Access:RW   DataWidth:0x4    // QM aggregation connection context part size per connection type.
+#define UCM_REG_QM_XXLOCK_CMD_0_BB_K2                                                                        0x12804c4UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define UCM_REG_QM_XXLOCK_CMD_0_E5                                                                           0x1281d40UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define UCM_REG_QM_XXLOCK_CMD_1_BB_K2                                                                        0x12804c8UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define UCM_REG_QM_XXLOCK_CMD_1_E5                                                                           0x1281d44UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define UCM_REG_QM_XXLOCK_CMD_2_BB_K2                                                                        0x12804ccUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define UCM_REG_QM_XXLOCK_CMD_2_E5                                                                           0x1281d48UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define UCM_REG_QM_XXLOCK_CMD_3_BB_K2                                                                        0x12804d0UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define UCM_REG_QM_XXLOCK_CMD_3_E5                                                                           0x1281d4cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define UCM_REG_QM_XXLOCK_CMD_4_BB_K2                                                                        0x12804d4UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define UCM_REG_QM_XXLOCK_CMD_4_E5                                                                           0x1281d50UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define UCM_REG_QM_XXLOCK_CMD_5_BB_K2                                                                        0x12804d8UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define UCM_REG_QM_XXLOCK_CMD_5_E5                                                                           0x1281d54UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define UCM_REG_QM_XXLOCK_CMD_6_BB_K2                                                                        0x12804dcUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define UCM_REG_QM_XXLOCK_CMD_6_E5                                                                           0x1281d58UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define UCM_REG_QM_XXLOCK_CMD_7_BB_K2                                                                        0x12804e0UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define UCM_REG_QM_XXLOCK_CMD_7_E5                                                                           0x1281d5cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define UCM_REG_QM_XXLOCK_CMD_8_E5                                                                           0x1281d60UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define UCM_REG_QM_XXLOCK_CMD_9_E5                                                                           0x1281d64UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define UCM_REG_QM_XXLOCK_CMD_10_E5                                                                          0x1281d68UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define UCM_REG_QM_XXLOCK_CMD_11_E5                                                                          0x1281d6cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define UCM_REG_QM_XXLOCK_CMD_12_E5                                                                          0x1281d70UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define UCM_REG_QM_XXLOCK_CMD_13_E5                                                                          0x1281d74UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define UCM_REG_QM_XXLOCK_CMD_14_E5                                                                          0x1281d78UL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define UCM_REG_QM_XXLOCK_CMD_15_E5                                                                          0x1281d7cUL //Access:RW   DataWidth:0x3    // QM XxLock command per connection type.
+#define UCM_REG_QM_CON_USE_ST_FLG_0_BB_K2                                                                    0x12804e4UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define UCM_REG_QM_CON_USE_ST_FLG_0_E5                                                                       0x1281d80UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define UCM_REG_QM_CON_USE_ST_FLG_1_BB_K2                                                                    0x12804e8UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define UCM_REG_QM_CON_USE_ST_FLG_1_E5                                                                       0x1281d84UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define UCM_REG_QM_CON_USE_ST_FLG_2_BB_K2                                                                    0x12804ecUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define UCM_REG_QM_CON_USE_ST_FLG_2_E5                                                                       0x1281d88UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define UCM_REG_QM_CON_USE_ST_FLG_3_BB_K2                                                                    0x12804f0UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define UCM_REG_QM_CON_USE_ST_FLG_3_E5                                                                       0x1281d8cUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define UCM_REG_QM_CON_USE_ST_FLG_4_BB_K2                                                                    0x12804f4UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define UCM_REG_QM_CON_USE_ST_FLG_4_E5                                                                       0x1281d90UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define UCM_REG_QM_CON_USE_ST_FLG_5_BB_K2                                                                    0x12804f8UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define UCM_REG_QM_CON_USE_ST_FLG_5_E5                                                                       0x1281d94UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define UCM_REG_QM_CON_USE_ST_FLG_6_BB_K2                                                                    0x12804fcUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define UCM_REG_QM_CON_USE_ST_FLG_6_E5                                                                       0x1281d98UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define UCM_REG_QM_CON_USE_ST_FLG_7_BB_K2                                                                    0x1280500UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define UCM_REG_QM_CON_USE_ST_FLG_7_E5                                                                       0x1281d9cUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define UCM_REG_QM_CON_USE_ST_FLG_8_E5                                                                       0x1281da0UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define UCM_REG_QM_CON_USE_ST_FLG_9_E5                                                                       0x1281da4UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define UCM_REG_QM_CON_USE_ST_FLG_10_E5                                                                      0x1281da8UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define UCM_REG_QM_CON_USE_ST_FLG_11_E5                                                                      0x1281dacUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define UCM_REG_QM_CON_USE_ST_FLG_12_E5                                                                      0x1281db0UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define UCM_REG_QM_CON_USE_ST_FLG_13_E5                                                                      0x1281db4UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define UCM_REG_QM_CON_USE_ST_FLG_14_E5                                                                      0x1281db8UL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define UCM_REG_QM_CON_USE_ST_FLG_15_E5                                                                      0x1281dbcUL //Access:RW   DataWidth:0x1    // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
+#define UCM_REG_QM_SM_CON_CTX_LDST_FLG_0_BB_K2                                                               0x1280464UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define UCM_REG_QM_SM_CON_CTX_LDST_FLG_0_E5                                                                  0x1281dc0UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define UCM_REG_QM_SM_CON_CTX_LDST_FLG_1_BB_K2                                                               0x1280468UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define UCM_REG_QM_SM_CON_CTX_LDST_FLG_1_E5                                                                  0x1281dc4UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define UCM_REG_QM_SM_CON_CTX_LDST_FLG_2_BB_K2                                                               0x128046cUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define UCM_REG_QM_SM_CON_CTX_LDST_FLG_2_E5                                                                  0x1281dc8UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define UCM_REG_QM_SM_CON_CTX_LDST_FLG_3_BB_K2                                                               0x1280470UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define UCM_REG_QM_SM_CON_CTX_LDST_FLG_3_E5                                                                  0x1281dccUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define UCM_REG_QM_SM_CON_CTX_LDST_FLG_4_BB_K2                                                               0x1280474UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define UCM_REG_QM_SM_CON_CTX_LDST_FLG_4_E5                                                                  0x1281dd0UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define UCM_REG_QM_SM_CON_CTX_LDST_FLG_5_BB_K2                                                               0x1280478UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define UCM_REG_QM_SM_CON_CTX_LDST_FLG_5_E5                                                                  0x1281dd4UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define UCM_REG_QM_SM_CON_CTX_LDST_FLG_6_BB_K2                                                               0x128047cUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define UCM_REG_QM_SM_CON_CTX_LDST_FLG_6_E5                                                                  0x1281dd8UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define UCM_REG_QM_SM_CON_CTX_LDST_FLG_7_BB_K2                                                               0x1280480UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define UCM_REG_QM_SM_CON_CTX_LDST_FLG_7_E5                                                                  0x1281ddcUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define UCM_REG_QM_SM_CON_CTX_LDST_FLG_8_E5                                                                  0x1281de0UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define UCM_REG_QM_SM_CON_CTX_LDST_FLG_9_E5                                                                  0x1281de4UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define UCM_REG_QM_SM_CON_CTX_LDST_FLG_10_E5                                                                 0x1281de8UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define UCM_REG_QM_SM_CON_CTX_LDST_FLG_11_E5                                                                 0x1281decUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define UCM_REG_QM_SM_CON_CTX_LDST_FLG_12_E5                                                                 0x1281df0UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define UCM_REG_QM_SM_CON_CTX_LDST_FLG_13_E5                                                                 0x1281df4UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define UCM_REG_QM_SM_CON_CTX_LDST_FLG_14_E5                                                                 0x1281df8UL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define UCM_REG_QM_SM_CON_CTX_LDST_FLG_15_E5                                                                 0x1281dfcUL //Access:RW   DataWidth:0x1    // QM storm connection context load_store per connection type.
+#define UCM_REG_IS_FOC_MULD_BB_K2                                                                            0x1281400UL //Access:R    DataWidth:0x20   // Debug read from MULD Input stage buffer with 32-bits granularity. Read only.
+#define UCM_REG_IS_FOC_MULD_E5                                                                               0x1282000UL //Access:R    DataWidth:0x20   // Debug read from MULD Input stage buffer with 32-bits granularity. Read only.
+#define UCM_REG_IS_FOC_MULD_SIZE_BB_K2                                                                       124
+#define UCM_REG_IS_FOC_MULD_SIZE_E5                                                                          280
+#define UCM_REG_RING_BASE_E5                                                                                 0x1282800UL //Access:RW   DataWidth:0x5    // UCM BD ring base address.
+#define UCM_REG_RING_LAST_E5                                                                                 0x1282804UL //Access:RW   DataWidth:0x5    // UCM BD ring last address.
+#define UCM_REG_YSEM_WEIGHT_E5                                                                               0x1282808UL //Access:RW   DataWidth:0x3    // The weight of the input Ysem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.
+#define UCM_REG_YSEM_FRWRD_MODE_E5                                                                           0x128280cUL //Access:RW   DataWidth:0x1    // Input message mode. If 0 - cut-through; if 1 - store-forward.
+#define UCM_REG_YSEM_MSG_CNTR_E5                                                                             0x1282810UL //Access:RC   DataWidth:0x1c   // Counter of the input messages at input Ysem.
+#define UCM_REG_IS_YSEM_FILL_LVL_E5                                                                          0x1282814UL //Access:R    DataWidth:0x4    // Number of QREGs (128b) for TCM, XCM or 2 QREGs (256b) for MCM of data in YSEM Input Stage.
+#define UCM_REG_IS_FOC_YSEM_NXT_INF_UNIT_E5                                                                  0x1282818UL //Access:R    DataWidth:0x6    // Debug read from YSEM Input stage buffer: number of reads to next information unit.
+#define UCM_REG_IS_FOC_YSEM_E5                                                                               0x1282900UL //Access:R    DataWidth:0x20   // Debug read from YSEM Input stage buffer with 32-bits granularity. Read only.
+#define UCM_REG_IS_FOC_YSEM_SIZE                                                                             36
+#define UCM_REG_AGG_TASK_CF0_Q_BB_K2                                                                         0x1280954UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_TASK_CF0_Q_E5                                                                            0x1282a00UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_TASK_CF1_Q_BB_K2                                                                         0x1280958UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_TASK_CF1_Q_E5                                                                            0x1282a04UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_TASK_CF2_Q_BB_K2                                                                         0x128095cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_TASK_CF2_Q_E5                                                                            0x1282a08UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_TASK_CF3_Q_BB_K2                                                                         0x1280960UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_TASK_CF3_Q_E5                                                                            0x1282a0cUL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_TASK_CF4_Q_BB_K2                                                                         0x1280964UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_TASK_CF4_Q_E5                                                                            0x1282a10UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_AGG_TASK_CF5_Q_E5                                                                            0x1282a14UL //Access:RW   DataWidth:0x2    // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).
+#define UCM_REG_XX_MSG_RAM                                                                                   0x1288000UL //Access:R    DataWidth:0x20   // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
+#define UCM_REG_XX_MSG_RAM_SIZE_BB_K2                                                                        6656
+#define UCM_REG_XX_MSG_RAM_SIZE_E5                                                                           7168
+#define XSEM_REG_ENABLE_IN_BB_K2                                                                             0x1400004UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define XSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN_BB_K2                                                        (0x1<<0) // Full input from external IF to LS input enable.
+  #define XSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN_BB_K2_SHIFT                                                  0
+  #define XSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN_BB_K2                                                     (0x1<<1) // Read data from external LS IF input enable.
+  #define XSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN_BB_K2_SHIFT                                               1
+  #define XSEM_REG_ENABLE_IN_FIC_ENABLE_IN_BB_K2                                                             (0x1<<2) // FIC input enable bit used to enable/disable messages from being received on all FIC interfaces.
+  #define XSEM_REG_ENABLE_IN_FIC_ENABLE_IN_BB_K2_SHIFT                                                       2
+  #define XSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN_BB_K2                                                         (0x1<<3) // FOC acknowledge input enable bit used to enable/disable acknowledge response from being received on any of the FOC interfaces.
+  #define XSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN_BB_K2_SHIFT                                                   3
+  #define XSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN_BB_K2                                                         (0x1<<4) // General interface input enable.
+  #define XSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN_BB_K2_SHIFT                                                   4
+  #define XSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN_BB_K2                                                         (0x1<<5) // External passive write input enable.
+  #define XSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN_BB_K2_SHIFT                                                   5
+  #define XSEM_REG_ENABLE_IN_RAM_ENABLE_IN_BB_K2                                                             (0x1<<6) // Data input enable to RAM.
+  #define XSEM_REG_ENABLE_IN_RAM_ENABLE_IN_BB_K2_SHIFT                                                       6
+  #define XSEM_REG_ENABLE_IN_STALL_ENABLE_IN_BB_K2                                                           (0x1<<7) // Enable for stall input from all external STORM instances.
+  #define XSEM_REG_ENABLE_IN_STALL_ENABLE_IN_BB_K2_SHIFT                                                     7
+  #define XSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN_BB_K2                                                      (0x1<<8) // Thread ready bus input enable.
+  #define XSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN_BB_K2_SHIFT                                                8
+  #define XSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN_BB_K2                                                      (0x1<<9) // Input enable for VF error indication from SDM to SEMI.
+  #define XSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN_BB_K2_SHIFT                                                9
+#define XSEM_REG_ENABLE_OUT_BB_K2                                                                            0x1400008UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define XSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT_BB_K2                                                    (0x1<<0) // Read request output enable from external LS IF.
+  #define XSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT_BB_K2_SHIFT                                              0
+  #define XSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT_BB_K2                                                    (0x1<<1) // Write request output enable from external LS IF.
+  #define XSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT_BB_K2_SHIFT                                              1
+  #define XSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT_BB_K2                                                           (0x1<<2) // FOC output otuput enable bit used to enable/disable messages from being sent out on any of the FOC interfaces.
+  #define XSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT_BB_K2_SHIFT                                                     2
+  #define XSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT_BB_K2                                                       (0x1<<3) // Passive full output enable.
+  #define XSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT_BB_K2_SHIFT                                                 3
+  #define XSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT_BB_K2                                                           (0x1<<4) // Data output enable to RAM.
+  #define XSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT_BB_K2_SHIFT                                                     4
+  #define XSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT_BB_K2                                                         (0x1<<5) // Stall output enable bit used to enable/disable the output stall signal toward all external Storm instances.
+  #define XSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT_BB_K2_SHIFT                                                   5
+#define XSEM_REG_FIC_DISABLE_BB_K2                                                                           0x140000cUL //Access:RW   DataWidth:0x1    // Disables input messages from all FIC interfaces.  May be updated during run_time by the microcode.
+#define XSEM_REG_PAS_DISABLE_BB_K2                                                                           0x1400010UL //Access:RW   DataWidth:0x1    // Disables input messages from the passive buffer  May be updated during run_time by the microcode.
+#define XSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_E5                                                         0x1400014UL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define XSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_FIC_WEIGHT_E5                                   (0xf<<0) // Passive Buffer write WRR weight value for FIC source.
+  #define XSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_FIC_WEIGHT_E5_SHIFT                             0
+  #define XSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_A_WEIGHT_E5                                 (0xf<<4) // Passive Buffer write WRR weight value for DRA RD A source.
+  #define XSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_A_WEIGHT_E5_SHIFT                           4
+  #define XSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_B_WEIGHT_E5                                 (0xf<<8) // Passive Buffer write WRR weight value for DRA RD B source.
+  #define XSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_B_WEIGHT_E5_SHIFT                           8
+  #define XSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_SDM_WEIGHT_E5                                   (0xf<<12) // Passive Buffer write WRR weight value for SDM source.
+  #define XSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_SDM_WEIGHT_E5_SHIFT                             12
+  #define XSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_EMPTY_CNT_E5                                    (0xf<<16) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define XSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_EMPTY_CNT_E5_SHIFT                              16
+  #define XSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_STRICT_SRC_E5                                      (0x7<<20) // This register defines if one of the source of the PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B, 100 - SDM.
+  #define XSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_STRICT_SRC_E5_SHIFT                                20
+#define XSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_E5                                                          0x1400018UL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define XSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_FOC_WEIGHT_E5                                    (0xf<<0) // Passive Buffer WRR weight value for FOC source.
+  #define XSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_FOC_WEIGHT_E5_SHIFT                              0
+  #define XSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_A_WEIGHT_E5                                  (0xf<<4) // Passive Buffer write WRR weight value for DRA WR A source.
+  #define XSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_A_WEIGHT_E5_SHIFT                            4
+  #define XSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_B_WEIGHT_E5                                  (0xf<<8) // Passive Buffer write WRR weight value for DRA WR B source.
+  #define XSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_B_WEIGHT_E5_SHIFT                            8
+  #define XSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_GRC_WEIGHT_E5                                    (0xf<<12) // Passive Buffer write WRR weight value for GRC source.
+  #define XSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_GRC_WEIGHT_E5_SHIFT                              12
+  #define XSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_EMPTY_CNT_E5                                     (0xf<<16) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define XSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_EMPTY_CNT_E5_SHIFT                               16
+  #define XSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_STRICT_SRC_E5                                       (0x7<<20) // This register defines if one of the source of the PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B, 100 - GRC.
+  #define XSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_STRICT_SRC_E5_SHIFT                                 20
+#define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_E5                                                            0x140001cUL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_FIC0_A_WEIGHT_E5                             (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_FIC0_A_WEIGHT_E5_SHIFT                       0
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_FIC1_A_WEIGHT_E5                             (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_FIC1_A_WEIGHT_E5_SHIFT                       4
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO0_A_WEIGHT_E5                            (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO0_A_WEIGHT_E5_SHIFT                      8
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO1_A_WEIGHT_E5                            (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO1_A_WEIGHT_E5_SHIFT                      12
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_EMPTY_CNT_E5                                 (0xf<<16) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_EMPTY_CNT_E5_SHIFT                           16
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_STRICT_SRC_E5                                   (0x7<<20) // This register defines if one of the source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - FIC1.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_STRICT_SRC_E5_SHIFT                             20
+#define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_E5                                                            0x1400020UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_FIC0_X_WEIGHT_E5                             (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_FIC0_X_WEIGHT_E5_SHIFT                       0
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO0_X_WEIGHT_E5                            (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO0_X_WEIGHT_E5_SHIFT                      4
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO1_X_WEIGHT_E5                            (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO1_X_WEIGHT_E5_SHIFT                      8
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_EMPTY_CNT_E5                                 (0xf<<12) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_EMPTY_CNT_E5_SHIFT                           12
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_STRICT_SRC_E5                                   (0x3<<16) // This register defines if one of the source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_STRICT_SRC_E5_SHIFT                             16
+#define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_E5                                                            0x1400024UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_FIC0_B_WEIGHT_E5                             (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_FIC0_B_WEIGHT_E5_SHIFT                       0
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO0_B_WEIGHT_E5                            (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO0_B_WEIGHT_E5_SHIFT                      4
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO1_B_WEIGHT_E5                            (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO1_B_WEIGHT_E5_SHIFT                      8
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_EMPTY_CNT_E5                                 (0xf<<12) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_EMPTY_CNT_E5_SHIFT                           12
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_STRICT_SRC_E5                                   (0x3<<16) // This register defines if one of the source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_STRICT_SRC_E5_SHIFT                             16
+#define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_E5                                                            0x1400028UL //Access:RW   DataWidth:0xe    // Multi Field Register.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_AFFIN_A_WEIGHT_E5                            (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for Affinity A source.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_AFFIN_A_WEIGHT_E5_SHIFT                      0
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_AFFIN_X_WEIGHT_E5                            (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for Affinity X source.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_AFFIN_X_WEIGHT_E5_SHIFT                      4
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_EMPTY_CNT_E5                                 (0xf<<8) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_EMPTY_CNT_E5_SHIFT                           8
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_STRICT_SRC_E5                                   (0x3<<12) // This register defines if one of the source of the PB WR arbiter should have strict priority: 0 - None, 1 - AFFINITY A, 2- AFFINITY X.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_STRICT_SRC_E5_SHIFT                             12
+#define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_E5                                                            0x140002cUL //Access:RW   DataWidth:0xc    // Multi Field Register.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_AFFIN_B_WEIGHT_E5                            (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for Affinity B source.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_AFFIN_B_WEIGHT_E5_SHIFT                      0
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_AFFIN_X_WEIGHT_E5                            (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for Affinity X source.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_AFFIN_X_WEIGHT_E5_SHIFT                      4
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_EMPTY_CNT_E5                                 (0xf<<8) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define XSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_EMPTY_CNT_E5_SHIFT                           8
+#define XSEM_REG_PASSIVE_BUFFER_DRA_WR_E5                                                                    0x1400030UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define XSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_A_E5                                                   (0x1<<0) // Enable DRA Write to transactions towards the SEM_PD Core A.
+  #define XSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_A_E5_SHIFT                                             0
+  #define XSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_B_E5                                                   (0x1<<1) // Enable DRA Write to transactions towards the SEM_PD Core B.
+  #define XSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_B_E5_SHIFT                                             1
+  #define XSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_PEND_BLOCK_EN_E5                                          (0x1<<2) // When set, there may only be a single thread pending to run for each storm.
+  #define XSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_PEND_BLOCK_EN_E5_SHIFT                                    2
+  #define XSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_AFFINITY_CORE_A_ONLY_E5                                          (0x1<<3) // When set, the Affintiy field of the thread is set to CoreA (regardless to the Afficnity received from CM).
+  #define XSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_AFFINITY_CORE_A_ONLY_E5_SHIFT                                    3
+#define XSEM_REG_INT_STS_0                                                                                   0x1400040UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define XSEM_REG_INT_STS_0_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define XSEM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                             0
+  #define XSEM_REG_INT_STS_0_FIC_LAST_ERROR                                                                  (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
+  #define XSEM_REG_INT_STS_0_FIC_LAST_ERROR_SHIFT                                                            1
+  #define XSEM_REG_INT_STS_0_FIC_LENGTH_ERROR                                                                (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
+  #define XSEM_REG_INT_STS_0_FIC_LENGTH_ERROR_SHIFT                                                          2
+  #define XSEM_REG_INT_STS_0_FIC_FIFO_ERROR                                                                  (0x1<<3) // Error in any one of the FIC FIFO is active.
+  #define XSEM_REG_INT_STS_0_FIC_FIFO_ERROR_SHIFT                                                            3
+  #define XSEM_REG_INT_STS_0_DRA_RD_A_LAST_ERROR_E5                                                          (0x1<<4) // DRA_RD_A last indication was unexpectedly received or was not received at expected time.
+  #define XSEM_REG_INT_STS_0_DRA_RD_A_LAST_ERROR_E5_SHIFT                                                    4
+  #define XSEM_REG_INT_STS_0_DRA_RD_B_LAST_ERROR_E5                                                          (0x1<<5) // DRA_RD_B last indication was unexpectedly received or was not received at expected time.
+  #define XSEM_REG_INT_STS_0_DRA_RD_B_LAST_ERROR_E5_SHIFT                                                    5
+  #define XSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_A_E5                                                   (0x1<<6) // Error in external store slow sync FIFO pop logic of Storm A.
+  #define XSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_A_E5_SHIFT                                             6
+  #define XSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_B_E5                                                   (0x1<<7) // Error in external store slow sync FIFO pop logic of Storm B.
+  #define XSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT                                             7
+  #define XSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5                                                   (0x1<<8) // Error in external load sync slow FIFO push logic.
+  #define XSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT                                             8
+  #define XSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5                                                   (0x1<<9) // Error in external load sync slow FIFO pop logic.
+  #define XSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5_SHIFT                                             9
+  #define XSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2                                                    (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
+  #define XSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2_SHIFT                                              22
+  #define XSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_E5                                                       (0x1<<10) // Error in slow LS_SYNC_PUSH FIFO.
+  #define XSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_E5_SHIFT                                                 10
+  #define XSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_BB_K2                                                     (0x1<<23) // Error in LS_SYNC_POP FIFO.
+  #define XSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_BB_K2_SHIFT                                               23
+  #define XSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_E5                                                        (0x1<<11) // Error in slow LS_SYNC_POP FIFO.
+  #define XSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_E5_SHIFT                                                  11
+  #define XSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2                                                    (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
+  #define XSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2_SHIFT                                              25
+  #define XSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_E5                                                       (0x1<<12) // Error in slow LS_SYNC_PUSH FIFO.
+  #define XSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_E5_SHIFT                                                 12
+  #define XSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_A_E5                                                         (0x1<<13) // Error in slow LS_SYNC_PUSH FIFO.
+  #define XSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_A_E5_SHIFT                                                   13
+  #define XSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_B_E5                                                         (0x1<<14) // Error in slow LS_SYNC_POP FIFO.
+  #define XSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_B_E5_SHIFT                                                   14
+  #define XSEM_REG_INT_STS_0_DBG_FIFO_ERROR_BB_K2                                                            (0x1<<28) // Error in slow debug fifo.
+  #define XSEM_REG_INT_STS_0_DBG_FIFO_ERROR_BB_K2_SHIFT                                                      28
+  #define XSEM_REG_INT_STS_0_DBG_FIFO_ERROR_E5                                                               (0x1<<15) // Error in slow debug fifo
+  #define XSEM_REG_INT_STS_0_DBG_FIFO_ERROR_E5_SHIFT                                                         15
+  #define XSEM_REG_INT_STS_0_EXT_THREAD_OOR_ERROR_E5                                                         (0x1<<16) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define XSEM_REG_INT_STS_0_EXT_THREAD_OOR_ERROR_E5_SHIFT                                                   16
+  #define XSEM_REG_INT_STS_0_EXT_STORE_TAG_ODER_ERROR_E5                                                     (0x1<<17) // Error detected in the ext Stroe interface internal TAG order ID.
+  #define XSEM_REG_INT_STS_0_EXT_STORE_TAG_ODER_ERROR_E5_SHIFT                                               17
+  #define XSEM_REG_INT_STS_0_FIC1_AFFINITY_FIELD_ERROR_E5                                                    (0x1<<18) // Indicates that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
+  #define XSEM_REG_INT_STS_0_FIC1_AFFINITY_FIELD_ERROR_E5_SHIFT                                              18
+  #define XSEM_REG_INT_STS_0_EXT_LD_LEN_ERROR_E5                                                             (0x1<<19) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define XSEM_REG_INT_STS_0_EXT_LD_LEN_ERROR_E5_SHIFT                                                       19
+  #define XSEM_REG_INT_STS_0_PB_QUE_ARB_THRD_RDY_ERROR_E5                                                    (0x1<<20) // Indicates that Passive Buffer State machine has unexpectedly received a ready indication in the following cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pending FOC" or "Ready FOC" state. b. Pending Ready indication is already asserted.
+  #define XSEM_REG_INT_STS_0_PB_QUE_ARB_THRD_RDY_ERROR_E5_SHIFT                                              20
+  #define XSEM_REG_INT_STS_0_SYNC_FOC_FIFO_ERROR_E5                                                          (0x1<<21) // Error indication on FOC sync FIFO.
+  #define XSEM_REG_INT_STS_0_SYNC_FOC_FIFO_ERROR_E5_SHIFT                                                    21
+  #define XSEM_REG_INT_STS_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                      (0x1<<22) // The error indicates on an error of one the threads READY queues.
+  #define XSEM_REG_INT_STS_0_PB_QUE_ARB_QUEUES_ERROR_E5_SHIFT                                                22
+  #define XSEM_REG_INT_STS_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5                                                (0x1<<23) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define XSEM_REG_INT_STS_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5_SHIFT                                          23
+  #define XSEM_REG_INT_STS_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5                                                (0x1<<24) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define XSEM_REG_INT_STS_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5_SHIFT                                          24
+  #define XSEM_REG_INT_STS_0_CREDIT_ERROR_FOC0_E5                                                            (0x1<<25) // FOC0 is out of credit.
+  #define XSEM_REG_INT_STS_0_CREDIT_ERROR_FOC0_E5_SHIFT                                                      25
+  #define XSEM_REG_INT_STS_0_CREDIT_ERROR_FOC1_E5                                                            (0x1<<26) // FOC1 is out of credit.
+  #define XSEM_REG_INT_STS_0_CREDIT_ERROR_FOC1_E5_SHIFT                                                      26
+  #define XSEM_REG_INT_STS_0_CREDIT_ERROR_FOC2_E5                                                            (0x1<<27) // FOC2 is out of credit.
+  #define XSEM_REG_INT_STS_0_CREDIT_ERROR_FOC2_E5_SHIFT                                                      27
+  #define XSEM_REG_INT_STS_0_CREDIT_ERROR_FOC3_E5                                                            (0x1<<28) // FOC3 is out of credit.
+  #define XSEM_REG_INT_STS_0_CREDIT_ERROR_FOC3_E5_SHIFT                                                      28
+  #define XSEM_REG_INT_STS_0_CREDIT_ERROR_FOC4_E5                                                            (0x1<<29) // FOC4 is out of credit.
+  #define XSEM_REG_INT_STS_0_CREDIT_ERROR_FOC4_E5_SHIFT                                                      29
+  #define XSEM_REG_INT_STS_0_CREDIT_ERROR_FOC5_E5                                                            (0x1<<30) // FOC5 is out of credit.
+  #define XSEM_REG_INT_STS_0_CREDIT_ERROR_FOC5_E5_SHIFT                                                      30
+  #define XSEM_REG_INT_STS_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                     (0x1<<31) // Error indication of foc pre_fetch fifo.
+  #define XSEM_REG_INT_STS_0_FOC_PRE_FETCH_FIFO_ERROR_E5_SHIFT                                               31
+  #define XSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR_BB_K2                                                        (0x1<<4) // Error in Ext PAS_FIFO is active.
+  #define XSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR_BB_K2_SHIFT                                                  4
+  #define XSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR_BB_K2                                                        (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
+  #define XSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR_BB_K2_SHIFT                                                  5
+  #define XSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2                                                    (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
+  #define XSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2_SHIFT                                              6
+  #define XSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR_BB_K2                                                     (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
+  #define XSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT                                               7
+  #define XSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2                                                    (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
+  #define XSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT                                              8
+  #define XSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR_BB_K2                                                     (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
+  #define XSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR_BB_K2_SHIFT                                               9
+  #define XSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR_BB_K2                                                       (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
+  #define XSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR_BB_K2_SHIFT                                                 10
+  #define XSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR_BB_K2                                                    (0x1<<11) // Signals an unknown address in the fast-memory window.
+  #define XSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR_BB_K2_SHIFT                                              11
+  #define XSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO_BB_K2                                                          (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
+  #define XSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO_BB_K2_SHIFT                                                    12
+  #define XSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO_BB_K2                                                          (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
+  #define XSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO_BB_K2_SHIFT                                                    13
+  #define XSEM_REG_INT_STS_0_CAM_OUT_FIFO_BB_K2                                                              (0x1<<14) // Error in CAM_OUT fifo in cam block.
+  #define XSEM_REG_INT_STS_0_CAM_OUT_FIFO_BB_K2_SHIFT                                                        14
+  #define XSEM_REG_INT_STS_0_FIN_FIFO_BB_K2                                                                  (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
+  #define XSEM_REG_INT_STS_0_FIN_FIFO_BB_K2_SHIFT                                                            15
+  #define XSEM_REG_INT_STS_0_THREAD_FIFO_ERROR_BB_K2                                                         (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
+  #define XSEM_REG_INT_STS_0_THREAD_FIFO_ERROR_BB_K2_SHIFT                                                   16
+  #define XSEM_REG_INT_STS_0_THREAD_OVERRUN_BB_K2                                                            (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
+  #define XSEM_REG_INT_STS_0_THREAD_OVERRUN_BB_K2_SHIFT                                                      17
+  #define XSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2                                                 (0x1<<18) // Error in external store sync FIFO push logic.
+  #define XSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2_SHIFT                                           18
+  #define XSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_BB_K2                                                  (0x1<<19) // Error in external store sync FIFO pop logic.
+  #define XSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_BB_K2_SHIFT                                            19
+  #define XSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2                                                  (0x1<<20) // Error in external load sync FIFO push logic.
+  #define XSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2_SHIFT                                            20
+  #define XSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2                                                   (0x1<<21) // Error in external load sync FIFO pop logic.
+  #define XSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2_SHIFT                                             21
+  #define XSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR_BB_K2                                                     (0x1<<24) // Error in LS_SYNC_POP FIFO.
+  #define XSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR_BB_K2_SHIFT                                               24
+  #define XSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR_BB_K2                                                       (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
+  #define XSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR_BB_K2_SHIFT                                                 26
+  #define XSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_BB_K2                                                        (0x1<<27) // Error in LS_SYNC_POP FIFO.
+  #define XSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_BB_K2_SHIFT                                                  27
+  #define XSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO_BB_K2                                                         (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
+  #define XSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO_BB_K2_SHIFT                                                   29
+  #define XSEM_REG_INT_STS_0_VFC_INTERRUPT_BB_K2                                                             (0x1<<30) // Error interrupt in VFC block.
+  #define XSEM_REG_INT_STS_0_VFC_INTERRUPT_BB_K2_SHIFT                                                       30
+  #define XSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR_BB_K2                                                        (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
+  #define XSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR_BB_K2_SHIFT                                                  31
+#define XSEM_REG_INT_MASK_0                                                                                  0x1400044UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define XSEM_REG_INT_MASK_0_ADDRESS_ERROR                                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.ADDRESS_ERROR .
+  #define XSEM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                            0
+  #define XSEM_REG_INT_MASK_0_FIC_LAST_ERROR                                                                 (0x1<<1) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.FIC_LAST_ERROR .
+  #define XSEM_REG_INT_MASK_0_FIC_LAST_ERROR_SHIFT                                                           1
+  #define XSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR                                                               (0x1<<2) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.FIC_LENGTH_ERROR .
+  #define XSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR_SHIFT                                                         2
+  #define XSEM_REG_INT_MASK_0_FIC_FIFO_ERROR                                                                 (0x1<<3) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.FIC_FIFO_ERROR .
+  #define XSEM_REG_INT_MASK_0_FIC_FIFO_ERROR_SHIFT                                                           3
+  #define XSEM_REG_INT_MASK_0_DRA_RD_A_LAST_ERROR_E5                                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.DRA_RD_A_LAST_ERROR .
+  #define XSEM_REG_INT_MASK_0_DRA_RD_A_LAST_ERROR_E5_SHIFT                                                   4
+  #define XSEM_REG_INT_MASK_0_DRA_RD_B_LAST_ERROR_E5                                                         (0x1<<5) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.DRA_RD_B_LAST_ERROR .
+  #define XSEM_REG_INT_MASK_0_DRA_RD_B_LAST_ERROR_E5_SHIFT                                                   5
+  #define XSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_A_E5                                                  (0x1<<6) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR_A .
+  #define XSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_A_E5_SHIFT                                            6
+  #define XSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_B_E5                                                  (0x1<<7) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR_B .
+  #define XSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT                                            7
+  #define XSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5                                                  (0x1<<8) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR_A .
+  #define XSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT                                            8
+  #define XSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5                                                  (0x1<<9) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR_B .
+  #define XSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5_SHIFT                                            9
+  #define XSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2                                                   (0x1<<22) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_RAM_RD_PUSH_ERROR .
+  #define XSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2_SHIFT                                             22
+  #define XSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_E5                                                      (0x1<<10) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_RAM_RD_PUSH_ERROR .
+  #define XSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_E5_SHIFT                                                10
+  #define XSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_BB_K2                                                    (0x1<<23) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_RAM_RD_POP_ERROR .
+  #define XSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_BB_K2_SHIFT                                              23
+  #define XSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_E5                                                       (0x1<<11) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_RAM_RD_POP_ERROR .
+  #define XSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_E5_SHIFT                                                 11
+  #define XSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2                                                   (0x1<<25) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_RAM_WR_PUSH_ERROR .
+  #define XSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2_SHIFT                                             25
+  #define XSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_E5                                                      (0x1<<12) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_RAM_WR_PUSH_ERROR .
+  #define XSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_E5_SHIFT                                                12
+  #define XSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_A_E5                                                        (0x1<<13) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR_A .
+  #define XSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_A_E5_SHIFT                                                  13
+  #define XSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_B_E5                                                        (0x1<<14) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR_B .
+  #define XSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_B_E5_SHIFT                                                  14
+  #define XSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_BB_K2                                                           (0x1<<28) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.DBG_FIFO_ERROR .
+  #define XSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_BB_K2_SHIFT                                                     28
+  #define XSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_E5                                                              (0x1<<15) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.DBG_FIFO_ERROR .
+  #define XSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_E5_SHIFT                                                        15
+  #define XSEM_REG_INT_MASK_0_EXT_THREAD_OOR_ERROR_E5                                                        (0x1<<16) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.EXT_THREAD_OOR_ERROR .
+  #define XSEM_REG_INT_MASK_0_EXT_THREAD_OOR_ERROR_E5_SHIFT                                                  16
+  #define XSEM_REG_INT_MASK_0_EXT_STORE_TAG_ODER_ERROR_E5                                                    (0x1<<17) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.EXT_STORE_TAG_ODER_ERROR .
+  #define XSEM_REG_INT_MASK_0_EXT_STORE_TAG_ODER_ERROR_E5_SHIFT                                              17
+  #define XSEM_REG_INT_MASK_0_FIC1_AFFINITY_FIELD_ERROR_E5                                                   (0x1<<18) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.FIC1_AFFINITY_FIELD_ERROR .
+  #define XSEM_REG_INT_MASK_0_FIC1_AFFINITY_FIELD_ERROR_E5_SHIFT                                             18
+  #define XSEM_REG_INT_MASK_0_EXT_LD_LEN_ERROR_E5                                                            (0x1<<19) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.EXT_LD_LEN_ERROR .
+  #define XSEM_REG_INT_MASK_0_EXT_LD_LEN_ERROR_E5_SHIFT                                                      19
+  #define XSEM_REG_INT_MASK_0_PB_QUE_ARB_THRD_RDY_ERROR_E5                                                   (0x1<<20) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.PB_QUE_ARB_THRD_RDY_ERROR .
+  #define XSEM_REG_INT_MASK_0_PB_QUE_ARB_THRD_RDY_ERROR_E5_SHIFT                                             20
+  #define XSEM_REG_INT_MASK_0_SYNC_FOC_FIFO_ERROR_E5                                                         (0x1<<21) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_FOC_FIFO_ERROR .
+  #define XSEM_REG_INT_MASK_0_SYNC_FOC_FIFO_ERROR_E5_SHIFT                                                   21
+  #define XSEM_REG_INT_MASK_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                     (0x1<<22) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.PB_QUE_ARB_QUEUES_ERROR .
+  #define XSEM_REG_INT_MASK_0_PB_QUE_ARB_QUEUES_ERROR_E5_SHIFT                                               22
+  #define XSEM_REG_INT_MASK_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5                                               (0x1<<23) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.STORM_MOVRIND_USES_BAR_ATTN_A .
+  #define XSEM_REG_INT_MASK_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5_SHIFT                                         23
+  #define XSEM_REG_INT_MASK_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5                                               (0x1<<24) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.STORM_MOVRIND_USES_BAR_ATTN_B .
+  #define XSEM_REG_INT_MASK_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5_SHIFT                                         24
+  #define XSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC0_E5                                                           (0x1<<25) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.CREDIT_ERROR_FOC0 .
+  #define XSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC0_E5_SHIFT                                                     25
+  #define XSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC1_E5                                                           (0x1<<26) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.CREDIT_ERROR_FOC1 .
+  #define XSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC1_E5_SHIFT                                                     26
+  #define XSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC2_E5                                                           (0x1<<27) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.CREDIT_ERROR_FOC2 .
+  #define XSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC2_E5_SHIFT                                                     27
+  #define XSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC3_E5                                                           (0x1<<28) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.CREDIT_ERROR_FOC3 .
+  #define XSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC3_E5_SHIFT                                                     28
+  #define XSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC4_E5                                                           (0x1<<29) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.CREDIT_ERROR_FOC4 .
+  #define XSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC4_E5_SHIFT                                                     29
+  #define XSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC5_E5                                                           (0x1<<30) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.CREDIT_ERROR_FOC5 .
+  #define XSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC5_E5_SHIFT                                                     30
+  #define XSEM_REG_INT_MASK_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                    (0x1<<31) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.FOC_PRE_FETCH_FIFO_ERROR .
+  #define XSEM_REG_INT_MASK_0_FOC_PRE_FETCH_FIFO_ERROR_E5_SHIFT                                              31
+  #define XSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR_BB_K2                                                       (0x1<<4) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.PAS_BUF_FIFO_ERROR .
+  #define XSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR_BB_K2_SHIFT                                                 4
+  #define XSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR_BB_K2                                                       (0x1<<5) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_FIN_POP_ERROR .
+  #define XSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR_BB_K2_SHIFT                                                 5
+  #define XSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2                                                   (0x1<<6) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_DRA_WR_PUSH_ERROR .
+  #define XSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2_SHIFT                                             6
+  #define XSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR_BB_K2                                                    (0x1<<7) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_DRA_WR_POP_ERROR .
+  #define XSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT                                              7
+  #define XSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2                                                   (0x1<<8) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_DRA_RD_PUSH_ERROR .
+  #define XSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT                                             8
+  #define XSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR_BB_K2                                                    (0x1<<9) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_DRA_RD_POP_ERROR .
+  #define XSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR_BB_K2_SHIFT                                              9
+  #define XSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR_BB_K2                                                      (0x1<<10) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_FIN_PUSH_ERROR .
+  #define XSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR_BB_K2_SHIFT                                                10
+  #define XSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR_BB_K2                                                   (0x1<<11) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SEM_FAST_ADDRESS_ERROR .
+  #define XSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR_BB_K2_SHIFT                                             11
+  #define XSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO_BB_K2                                                         (0x1<<12) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.CAM_LSB_INP_FIFO .
+  #define XSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO_BB_K2_SHIFT                                                   12
+  #define XSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO_BB_K2                                                         (0x1<<13) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.CAM_MSB_INP_FIFO .
+  #define XSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO_BB_K2_SHIFT                                                   13
+  #define XSEM_REG_INT_MASK_0_CAM_OUT_FIFO_BB_K2                                                             (0x1<<14) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.CAM_OUT_FIFO .
+  #define XSEM_REG_INT_MASK_0_CAM_OUT_FIFO_BB_K2_SHIFT                                                       14
+  #define XSEM_REG_INT_MASK_0_FIN_FIFO_BB_K2                                                                 (0x1<<15) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.FIN_FIFO .
+  #define XSEM_REG_INT_MASK_0_FIN_FIFO_BB_K2_SHIFT                                                           15
+  #define XSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR_BB_K2                                                        (0x1<<16) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.THREAD_FIFO_ERROR .
+  #define XSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR_BB_K2_SHIFT                                                  16
+  #define XSEM_REG_INT_MASK_0_THREAD_OVERRUN_BB_K2                                                           (0x1<<17) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.THREAD_OVERRUN .
+  #define XSEM_REG_INT_MASK_0_THREAD_OVERRUN_BB_K2_SHIFT                                                     17
+  #define XSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2                                                (0x1<<18) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_EXT_STORE_PUSH_ERROR .
+  #define XSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2_SHIFT                                          18
+  #define XSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_BB_K2                                                 (0x1<<19) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR .
+  #define XSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_BB_K2_SHIFT                                           19
+  #define XSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2                                                 (0x1<<20) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR .
+  #define XSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2_SHIFT                                           20
+  #define XSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2                                                  (0x1<<21) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_EXT_LOAD_POP_ERROR .
+  #define XSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2_SHIFT                                            21
+  #define XSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR_BB_K2                                                    (0x1<<24) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_RAM_WR_POP_ERROR .
+  #define XSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR_BB_K2_SHIFT                                              24
+  #define XSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR_BB_K2                                                      (0x1<<26) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_DBG_PUSH_ERROR .
+  #define XSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR_BB_K2_SHIFT                                                26
+  #define XSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_BB_K2                                                       (0x1<<27) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR .
+  #define XSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_BB_K2_SHIFT                                                 27
+  #define XSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO_BB_K2                                                        (0x1<<29) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.CAM_MSB2_INP_FIFO .
+  #define XSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO_BB_K2_SHIFT                                                  29
+  #define XSEM_REG_INT_MASK_0_VFC_INTERRUPT_BB_K2                                                            (0x1<<30) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.VFC_INTERRUPT .
+  #define XSEM_REG_INT_MASK_0_VFC_INTERRUPT_BB_K2_SHIFT                                                      30
+  #define XSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR_BB_K2                                                       (0x1<<31) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.VFC_OUT_FIFO_ERROR .
+  #define XSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR_BB_K2_SHIFT                                                 31
+#define XSEM_REG_INT_STS_WR_0                                                                                0x1400048UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define XSEM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define XSEM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                          0
+  #define XSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR                                                               (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
+  #define XSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR_SHIFT                                                         1
+  #define XSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR                                                             (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
+  #define XSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR_SHIFT                                                       2
+  #define XSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR                                                               (0x1<<3) // Error in any one of the FIC FIFO is active.
+  #define XSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR_SHIFT                                                         3
+  #define XSEM_REG_INT_STS_WR_0_DRA_RD_A_LAST_ERROR_E5                                                       (0x1<<4) // DRA_RD_A last indication was unexpectedly received or was not received at expected time.
+  #define XSEM_REG_INT_STS_WR_0_DRA_RD_A_LAST_ERROR_E5_SHIFT                                                 4
+  #define XSEM_REG_INT_STS_WR_0_DRA_RD_B_LAST_ERROR_E5                                                       (0x1<<5) // DRA_RD_B last indication was unexpectedly received or was not received at expected time.
+  #define XSEM_REG_INT_STS_WR_0_DRA_RD_B_LAST_ERROR_E5_SHIFT                                                 5
+  #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_A_E5                                                (0x1<<6) // Error in external store slow sync FIFO pop logic of Storm A.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_A_E5_SHIFT                                          6
+  #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_B_E5                                                (0x1<<7) // Error in external store slow sync FIFO pop logic of Storm B.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT                                          7
+  #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5                                                (0x1<<8) // Error in external load sync slow FIFO push logic.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT                                          8
+  #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5                                                (0x1<<9) // Error in external load sync slow FIFO pop logic.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5_SHIFT                                          9
+  #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2                                                 (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2_SHIFT                                           22
+  #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_E5                                                    (0x1<<10) // Error in slow LS_SYNC_PUSH FIFO.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_E5_SHIFT                                              10
+  #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_BB_K2                                                  (0x1<<23) // Error in LS_SYNC_POP FIFO.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_BB_K2_SHIFT                                            23
+  #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_E5                                                     (0x1<<11) // Error in slow LS_SYNC_POP FIFO.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_E5_SHIFT                                               11
+  #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2                                                 (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2_SHIFT                                           25
+  #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_E5                                                    (0x1<<12) // Error in slow LS_SYNC_PUSH FIFO.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_E5_SHIFT                                              12
+  #define XSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_A_E5                                                      (0x1<<13) // Error in slow LS_SYNC_PUSH FIFO.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_A_E5_SHIFT                                                13
+  #define XSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_B_E5                                                      (0x1<<14) // Error in slow LS_SYNC_POP FIFO.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_B_E5_SHIFT                                                14
+  #define XSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_BB_K2                                                         (0x1<<28) // Error in slow debug fifo.
+  #define XSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_BB_K2_SHIFT                                                   28
+  #define XSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_E5                                                            (0x1<<15) // Error in slow debug fifo
+  #define XSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_E5_SHIFT                                                      15
+  #define XSEM_REG_INT_STS_WR_0_EXT_THREAD_OOR_ERROR_E5                                                      (0x1<<16) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define XSEM_REG_INT_STS_WR_0_EXT_THREAD_OOR_ERROR_E5_SHIFT                                                16
+  #define XSEM_REG_INT_STS_WR_0_EXT_STORE_TAG_ODER_ERROR_E5                                                  (0x1<<17) // Error detected in the ext Stroe interface internal TAG order ID.
+  #define XSEM_REG_INT_STS_WR_0_EXT_STORE_TAG_ODER_ERROR_E5_SHIFT                                            17
+  #define XSEM_REG_INT_STS_WR_0_FIC1_AFFINITY_FIELD_ERROR_E5                                                 (0x1<<18) // Indicates that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
+  #define XSEM_REG_INT_STS_WR_0_FIC1_AFFINITY_FIELD_ERROR_E5_SHIFT                                           18
+  #define XSEM_REG_INT_STS_WR_0_EXT_LD_LEN_ERROR_E5                                                          (0x1<<19) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define XSEM_REG_INT_STS_WR_0_EXT_LD_LEN_ERROR_E5_SHIFT                                                    19
+  #define XSEM_REG_INT_STS_WR_0_PB_QUE_ARB_THRD_RDY_ERROR_E5                                                 (0x1<<20) // Indicates that Passive Buffer State machine has unexpectedly received a ready indication in the following cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pending FOC" or "Ready FOC" state. b. Pending Ready indication is already asserted.
+  #define XSEM_REG_INT_STS_WR_0_PB_QUE_ARB_THRD_RDY_ERROR_E5_SHIFT                                           20
+  #define XSEM_REG_INT_STS_WR_0_SYNC_FOC_FIFO_ERROR_E5                                                       (0x1<<21) // Error indication on FOC sync FIFO.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_FOC_FIFO_ERROR_E5_SHIFT                                                 21
+  #define XSEM_REG_INT_STS_WR_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                   (0x1<<22) // The error indicates on an error of one the threads READY queues.
+  #define XSEM_REG_INT_STS_WR_0_PB_QUE_ARB_QUEUES_ERROR_E5_SHIFT                                             22
+  #define XSEM_REG_INT_STS_WR_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5                                             (0x1<<23) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define XSEM_REG_INT_STS_WR_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5_SHIFT                                       23
+  #define XSEM_REG_INT_STS_WR_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5                                             (0x1<<24) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define XSEM_REG_INT_STS_WR_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5_SHIFT                                       24
+  #define XSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC0_E5                                                         (0x1<<25) // FOC0 is out of credit.
+  #define XSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC0_E5_SHIFT                                                   25
+  #define XSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC1_E5                                                         (0x1<<26) // FOC1 is out of credit.
+  #define XSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC1_E5_SHIFT                                                   26
+  #define XSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC2_E5                                                         (0x1<<27) // FOC2 is out of credit.
+  #define XSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC2_E5_SHIFT                                                   27
+  #define XSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC3_E5                                                         (0x1<<28) // FOC3 is out of credit.
+  #define XSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC3_E5_SHIFT                                                   28
+  #define XSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC4_E5                                                         (0x1<<29) // FOC4 is out of credit.
+  #define XSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC4_E5_SHIFT                                                   29
+  #define XSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC5_E5                                                         (0x1<<30) // FOC5 is out of credit.
+  #define XSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC5_E5_SHIFT                                                   30
+  #define XSEM_REG_INT_STS_WR_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                  (0x1<<31) // Error indication of foc pre_fetch fifo.
+  #define XSEM_REG_INT_STS_WR_0_FOC_PRE_FETCH_FIFO_ERROR_E5_SHIFT                                            31
+  #define XSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR_BB_K2                                                     (0x1<<4) // Error in Ext PAS_FIFO is active.
+  #define XSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR_BB_K2_SHIFT                                               4
+  #define XSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR_BB_K2                                                     (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR_BB_K2_SHIFT                                               5
+  #define XSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2                                                 (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2_SHIFT                                           6
+  #define XSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR_BB_K2                                                  (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT                                            7
+  #define XSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2                                                 (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT                                           8
+  #define XSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR_BB_K2                                                  (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR_BB_K2_SHIFT                                            9
+  #define XSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR_BB_K2                                                    (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR_BB_K2_SHIFT                                              10
+  #define XSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR_BB_K2                                                 (0x1<<11) // Signals an unknown address in the fast-memory window.
+  #define XSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR_BB_K2_SHIFT                                           11
+  #define XSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO_BB_K2                                                       (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
+  #define XSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO_BB_K2_SHIFT                                                 12
+  #define XSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO_BB_K2                                                       (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
+  #define XSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO_BB_K2_SHIFT                                                 13
+  #define XSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO_BB_K2                                                           (0x1<<14) // Error in CAM_OUT fifo in cam block.
+  #define XSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO_BB_K2_SHIFT                                                     14
+  #define XSEM_REG_INT_STS_WR_0_FIN_FIFO_BB_K2                                                               (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
+  #define XSEM_REG_INT_STS_WR_0_FIN_FIFO_BB_K2_SHIFT                                                         15
+  #define XSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR_BB_K2                                                      (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
+  #define XSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR_BB_K2_SHIFT                                                16
+  #define XSEM_REG_INT_STS_WR_0_THREAD_OVERRUN_BB_K2                                                         (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
+  #define XSEM_REG_INT_STS_WR_0_THREAD_OVERRUN_BB_K2_SHIFT                                                   17
+  #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2                                              (0x1<<18) // Error in external store sync FIFO push logic.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2_SHIFT                                        18
+  #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_BB_K2                                               (0x1<<19) // Error in external store sync FIFO pop logic.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_BB_K2_SHIFT                                         19
+  #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2                                               (0x1<<20) // Error in external load sync FIFO push logic.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2_SHIFT                                         20
+  #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2                                                (0x1<<21) // Error in external load sync FIFO pop logic.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2_SHIFT                                          21
+  #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR_BB_K2                                                  (0x1<<24) // Error in LS_SYNC_POP FIFO.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR_BB_K2_SHIFT                                            24
+  #define XSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR_BB_K2                                                    (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR_BB_K2_SHIFT                                              26
+  #define XSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_BB_K2                                                     (0x1<<27) // Error in LS_SYNC_POP FIFO.
+  #define XSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_BB_K2_SHIFT                                               27
+  #define XSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO_BB_K2                                                      (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
+  #define XSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO_BB_K2_SHIFT                                                29
+  #define XSEM_REG_INT_STS_WR_0_VFC_INTERRUPT_BB_K2                                                          (0x1<<30) // Error interrupt in VFC block.
+  #define XSEM_REG_INT_STS_WR_0_VFC_INTERRUPT_BB_K2_SHIFT                                                    30
+  #define XSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR_BB_K2                                                     (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
+  #define XSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR_BB_K2_SHIFT                                               31
+#define XSEM_REG_INT_STS_CLR_0                                                                               0x140004cUL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define XSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                               (0x1<<0) // Signals an unknown address to the rf module.
+  #define XSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                         0
+  #define XSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR                                                              (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
+  #define XSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR_SHIFT                                                        1
+  #define XSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR                                                            (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
+  #define XSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR_SHIFT                                                      2
+  #define XSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR                                                              (0x1<<3) // Error in any one of the FIC FIFO is active.
+  #define XSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR_SHIFT                                                        3
+  #define XSEM_REG_INT_STS_CLR_0_DRA_RD_A_LAST_ERROR_E5                                                      (0x1<<4) // DRA_RD_A last indication was unexpectedly received or was not received at expected time.
+  #define XSEM_REG_INT_STS_CLR_0_DRA_RD_A_LAST_ERROR_E5_SHIFT                                                4
+  #define XSEM_REG_INT_STS_CLR_0_DRA_RD_B_LAST_ERROR_E5                                                      (0x1<<5) // DRA_RD_B last indication was unexpectedly received or was not received at expected time.
+  #define XSEM_REG_INT_STS_CLR_0_DRA_RD_B_LAST_ERROR_E5_SHIFT                                                5
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_A_E5                                               (0x1<<6) // Error in external store slow sync FIFO pop logic of Storm A.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_A_E5_SHIFT                                         6
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_B_E5                                               (0x1<<7) // Error in external store slow sync FIFO pop logic of Storm B.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT                                         7
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5                                               (0x1<<8) // Error in external load sync slow FIFO push logic.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT                                         8
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5                                               (0x1<<9) // Error in external load sync slow FIFO pop logic.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5_SHIFT                                         9
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2                                                (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2_SHIFT                                          22
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_E5                                                   (0x1<<10) // Error in slow LS_SYNC_PUSH FIFO.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_E5_SHIFT                                             10
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_BB_K2                                                 (0x1<<23) // Error in LS_SYNC_POP FIFO.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_BB_K2_SHIFT                                           23
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_E5                                                    (0x1<<11) // Error in slow LS_SYNC_POP FIFO.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_E5_SHIFT                                              11
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2                                                (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2_SHIFT                                          25
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_E5                                                   (0x1<<12) // Error in slow LS_SYNC_PUSH FIFO.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_E5_SHIFT                                             12
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_A_E5                                                     (0x1<<13) // Error in slow LS_SYNC_PUSH FIFO.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_A_E5_SHIFT                                               13
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_B_E5                                                     (0x1<<14) // Error in slow LS_SYNC_POP FIFO.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_B_E5_SHIFT                                               14
+  #define XSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_BB_K2                                                        (0x1<<28) // Error in slow debug fifo.
+  #define XSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_BB_K2_SHIFT                                                  28
+  #define XSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_E5                                                           (0x1<<15) // Error in slow debug fifo
+  #define XSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_E5_SHIFT                                                     15
+  #define XSEM_REG_INT_STS_CLR_0_EXT_THREAD_OOR_ERROR_E5                                                     (0x1<<16) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define XSEM_REG_INT_STS_CLR_0_EXT_THREAD_OOR_ERROR_E5_SHIFT                                               16
+  #define XSEM_REG_INT_STS_CLR_0_EXT_STORE_TAG_ODER_ERROR_E5                                                 (0x1<<17) // Error detected in the ext Stroe interface internal TAG order ID.
+  #define XSEM_REG_INT_STS_CLR_0_EXT_STORE_TAG_ODER_ERROR_E5_SHIFT                                           17
+  #define XSEM_REG_INT_STS_CLR_0_FIC1_AFFINITY_FIELD_ERROR_E5                                                (0x1<<18) // Indicates that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
+  #define XSEM_REG_INT_STS_CLR_0_FIC1_AFFINITY_FIELD_ERROR_E5_SHIFT                                          18
+  #define XSEM_REG_INT_STS_CLR_0_EXT_LD_LEN_ERROR_E5                                                         (0x1<<19) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define XSEM_REG_INT_STS_CLR_0_EXT_LD_LEN_ERROR_E5_SHIFT                                                   19
+  #define XSEM_REG_INT_STS_CLR_0_PB_QUE_ARB_THRD_RDY_ERROR_E5                                                (0x1<<20) // Indicates that Passive Buffer State machine has unexpectedly received a ready indication in the following cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pending FOC" or "Ready FOC" state. b. Pending Ready indication is already asserted.
+  #define XSEM_REG_INT_STS_CLR_0_PB_QUE_ARB_THRD_RDY_ERROR_E5_SHIFT                                          20
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_FOC_FIFO_ERROR_E5                                                      (0x1<<21) // Error indication on FOC sync FIFO.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_FOC_FIFO_ERROR_E5_SHIFT                                                21
+  #define XSEM_REG_INT_STS_CLR_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                  (0x1<<22) // The error indicates on an error of one the threads READY queues.
+  #define XSEM_REG_INT_STS_CLR_0_PB_QUE_ARB_QUEUES_ERROR_E5_SHIFT                                            22
+  #define XSEM_REG_INT_STS_CLR_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5                                            (0x1<<23) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define XSEM_REG_INT_STS_CLR_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5_SHIFT                                      23
+  #define XSEM_REG_INT_STS_CLR_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5                                            (0x1<<24) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define XSEM_REG_INT_STS_CLR_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5_SHIFT                                      24
+  #define XSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC0_E5                                                        (0x1<<25) // FOC0 is out of credit.
+  #define XSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC0_E5_SHIFT                                                  25
+  #define XSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC1_E5                                                        (0x1<<26) // FOC1 is out of credit.
+  #define XSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC1_E5_SHIFT                                                  26
+  #define XSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC2_E5                                                        (0x1<<27) // FOC2 is out of credit.
+  #define XSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC2_E5_SHIFT                                                  27
+  #define XSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC3_E5                                                        (0x1<<28) // FOC3 is out of credit.
+  #define XSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC3_E5_SHIFT                                                  28
+  #define XSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC4_E5                                                        (0x1<<29) // FOC4 is out of credit.
+  #define XSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC4_E5_SHIFT                                                  29
+  #define XSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC5_E5                                                        (0x1<<30) // FOC5 is out of credit.
+  #define XSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC5_E5_SHIFT                                                  30
+  #define XSEM_REG_INT_STS_CLR_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                 (0x1<<31) // Error indication of foc pre_fetch fifo.
+  #define XSEM_REG_INT_STS_CLR_0_FOC_PRE_FETCH_FIFO_ERROR_E5_SHIFT                                           31
+  #define XSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR_BB_K2                                                    (0x1<<4) // Error in Ext PAS_FIFO is active.
+  #define XSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR_BB_K2_SHIFT                                              4
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR_BB_K2                                                    (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR_BB_K2_SHIFT                                              5
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2                                                (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2_SHIFT                                          6
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR_BB_K2                                                 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT                                           7
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2                                                (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT                                          8
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR_BB_K2                                                 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR_BB_K2_SHIFT                                           9
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR_BB_K2                                                   (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR_BB_K2_SHIFT                                             10
+  #define XSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR_BB_K2                                                (0x1<<11) // Signals an unknown address in the fast-memory window.
+  #define XSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR_BB_K2_SHIFT                                          11
+  #define XSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO_BB_K2                                                      (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
+  #define XSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO_BB_K2_SHIFT                                                12
+  #define XSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO_BB_K2                                                      (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
+  #define XSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO_BB_K2_SHIFT                                                13
+  #define XSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO_BB_K2                                                          (0x1<<14) // Error in CAM_OUT fifo in cam block.
+  #define XSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO_BB_K2_SHIFT                                                    14
+  #define XSEM_REG_INT_STS_CLR_0_FIN_FIFO_BB_K2                                                              (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
+  #define XSEM_REG_INT_STS_CLR_0_FIN_FIFO_BB_K2_SHIFT                                                        15
+  #define XSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR_BB_K2                                                     (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
+  #define XSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR_BB_K2_SHIFT                                               16
+  #define XSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN_BB_K2                                                        (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
+  #define XSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN_BB_K2_SHIFT                                                  17
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2                                             (0x1<<18) // Error in external store sync FIFO push logic.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2_SHIFT                                       18
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_BB_K2                                              (0x1<<19) // Error in external store sync FIFO pop logic.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_BB_K2_SHIFT                                        19
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2                                              (0x1<<20) // Error in external load sync FIFO push logic.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2_SHIFT                                        20
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2                                               (0x1<<21) // Error in external load sync FIFO pop logic.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2_SHIFT                                         21
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR_BB_K2                                                 (0x1<<24) // Error in LS_SYNC_POP FIFO.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR_BB_K2_SHIFT                                           24
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR_BB_K2                                                   (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR_BB_K2_SHIFT                                             26
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_BB_K2                                                    (0x1<<27) // Error in LS_SYNC_POP FIFO.
+  #define XSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_BB_K2_SHIFT                                              27
+  #define XSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO_BB_K2                                                     (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
+  #define XSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO_BB_K2_SHIFT                                               29
+  #define XSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT_BB_K2                                                         (0x1<<30) // Error interrupt in VFC block.
+  #define XSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT_BB_K2_SHIFT                                                   30
+  #define XSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR_BB_K2                                                    (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
+  #define XSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR_BB_K2_SHIFT                                              31
+#define XSEM_REG_INT_STS_1                                                                                   0x1400050UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define XSEM_REG_INT_STS_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5                                              (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
+  #define XSEM_REG_INT_STS_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5_SHIFT                                        0
+  #define XSEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_A_E5                                                  (0x1<<1) // Fast external store FIFO error of Storm_A
+  #define XSEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT                                            1
+  #define XSEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_B_E5                                                  (0x1<<2) // Fast external store FIFO error of Storm_B
+  #define XSEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_B_E5_SHIFT                                            2
+  #define XSEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_A_E5                                                    (0x1<<3) // fast external load FIFO error of Storm_A
+  #define XSEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT                                              3
+  #define XSEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_B_E5                                                    (0x1<<4) // fast external load FIFO error of Storm_B
+  #define XSEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_B_E5_SHIFT                                              4
+  #define XSEM_REG_INT_STS_1_FAST_RAM_WR_POP_ERROR_E5                                                        (0x1<<5) // Internal RAM pop error
+  #define XSEM_REG_INT_STS_1_FAST_RAM_WR_POP_ERROR_E5_SHIFT                                                  5
+  #define XSEM_REG_INT_STS_1_FAST_RAM_RD_PUSH_ERROR_E5                                                       (0x1<<6) // Internal RAM write error
+  #define XSEM_REG_INT_STS_1_FAST_RAM_RD_PUSH_ERROR_E5_SHIFT                                                 6
+  #define XSEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_A_E5                                                     (0x1<<7) // DRA RD FIFO error of Storm A
+  #define XSEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT                                               7
+  #define XSEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_B_E5                                                     (0x1<<8) // DRA RD FIFO error of Storm B
+  #define XSEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT                                               8
+  #define XSEM_REG_INT_STS_1_FAST_DRA_WR_POP_ERROR_A_E5                                                      (0x1<<9) // DRA RD FIFO error of Storm A
+  #define XSEM_REG_INT_STS_1_FAST_DRA_WR_POP_ERROR_A_E5_SHIFT                                                9
+  #define XSEM_REG_INT_STS_1_FAST_DRA_WR_POP_ERROR_B_E5                                                      (0x1<<10) // DRA RD FIFO error of Storm B
+  #define XSEM_REG_INT_STS_1_FAST_DRA_WR_POP_ERROR_B_E5_SHIFT                                                10
+  #define XSEM_REG_INT_STS_1_SEM_FAST_INVLD_ADDR_ERR_E5                                                      (0x1<<11) // Fast invalid address error
+  #define XSEM_REG_INT_STS_1_SEM_FAST_INVLD_ADDR_ERR_E5_SHIFT                                                11
+  #define XSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_A_E5                                                        (0x1<<12) // Storm A stack_uf_attn interrupt
+  #define XSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_A_E5_SHIFT                                                  12
+  #define XSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_B_E5                                                        (0x1<<13) // Storm B stack_uf_attn interrupt
+  #define XSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_B_E5_SHIFT                                                  13
+  #define XSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_A_E5                                                        (0x1<<14) // Storm A stack_of_attn interrupt
+  #define XSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_A_E5_SHIFT                                                  14
+  #define XSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_B_E5                                                        (0x1<<15) // Storm B stack_of_attn interrupt
+  #define XSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_B_E5_SHIFT                                                  15
+  #define XSEM_REG_INT_STS_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5                                                 (0x1<<16) // Storm A ldst_addr_ovflw_attn interrupt
+  #define XSEM_REG_INT_STS_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5_SHIFT                                           16
+  #define XSEM_REG_INT_STS_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5                                                 (0x1<<17) // Storm B ldst_addr_ovflw_attn interrupt
+  #define XSEM_REG_INT_STS_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5_SHIFT                                           17
+  #define XSEM_REG_INT_STS_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5                                              (0x1<<18) // Storm A non_aligned_access_attn interrupt
+  #define XSEM_REG_INT_STS_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5_SHIFT                                        18
+  #define XSEM_REG_INT_STS_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5                                              (0x1<<19) // Storm B non_aligned_access_attn interrupt
+  #define XSEM_REG_INT_STS_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5_SHIFT                                        19
+  #define XSEM_REG_INT_STS_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5                                                (0x1<<20) // Storm A division_by_zero_attn interrupt
+  #define XSEM_REG_INT_STS_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5_SHIFT                                          20
+  #define XSEM_REG_INT_STS_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5                                                (0x1<<21) // Storm B division_by_zero_attn interrupt
+  #define XSEM_REG_INT_STS_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5_SHIFT                                          21
+  #define XSEM_REG_INT_STS_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5                                           (0x1<<22) // Storm A illegal_runtime_value_attn interrupt
+  #define XSEM_REG_INT_STS_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5_SHIFT                                     22
+  #define XSEM_REG_INT_STS_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5                                           (0x1<<23) // Storm B illegal_runtime_value_attn interrupt
+  #define XSEM_REG_INT_STS_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5_SHIFT                                     23
+  #define XSEM_REG_INT_STS_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5                                            (0x1<<24) // load request is made while previous is still active; not fully read, Storm A
+  #define XSEM_REG_INT_STS_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5_SHIFT                                      24
+  #define XSEM_REG_INT_STS_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5                                            (0x1<<25) // load request is made while previous is still active; not fully read, Storm B
+  #define XSEM_REG_INT_STS_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5_SHIFT                                      25
+  #define XSEM_REG_INT_STS_1_CAM_RBC_FAST_OUT_ERROR_A_E5                                                     (0x1<<26) // Error in CAM_OUT fifo in cam block of STORM A
+  #define XSEM_REG_INT_STS_1_CAM_RBC_FAST_OUT_ERROR_A_E5_SHIFT                                               26
+  #define XSEM_REG_INT_STS_1_CAM_RBC_FAST_OUT_ERROR_B_E5                                                     (0x1<<27) // Error in CAM_OUT fifo in cam block of STORM B
+  #define XSEM_REG_INT_STS_1_CAM_RBC_FAST_OUT_ERROR_B_E5_SHIFT                                               27
+  #define XSEM_REG_INT_STS_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5                                                 (0x1<<28) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define XSEM_REG_INT_STS_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5_SHIFT                                           28
+  #define XSEM_REG_INT_STS_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5                                                 (0x1<<29) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define XSEM_REG_INT_STS_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5_SHIFT                                           29
+  #define XSEM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5                                                 (0x1<<30) // Error in CAM_LSB_INP fifo in cam block of STORM A
+  #define XSEM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT                                           30
+  #define XSEM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5                                                 (0x1<<31) // Error in CAM_LSB_INP fifo in cam block of STORM B.
+  #define XSEM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5_SHIFT                                           31
+  #define XSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_BB_K2                                                       (0x1<<0) // An underflow error was detected in the Storm stack.
+  #define XSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_BB_K2_SHIFT                                                 0
+  #define XSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_BB_K2                                                       (0x1<<1) // An overflow error was detected in the Storm stack.
+  #define XSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT                                                 1
+  #define XSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR_BB_K2                                                       (0x1<<2) // The Storm detected an illegal runtime value.
+  #define XSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR_BB_K2_SHIFT                                                 2
+  #define XSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR_BB_K2                                                    (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
+  #define XSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT                                              3
+  #define XSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR_BB_K2                                                     (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
+  #define XSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR_BB_K2_SHIFT                                               4
+  #define XSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR_BB_K2                                                     (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
+  #define XSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR_BB_K2_SHIFT                                               5
+  #define XSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR_BB_K2                                                      (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
+  #define XSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR_BB_K2_SHIFT                                                6
+  #define XSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR_BB_K2                                                      (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define XSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT                                                7
+  #define XSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR_BB_K2                                                         (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
+  #define XSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT                                                   8
+  #define XSEM_REG_INT_STS_1_INVLD_FOC_ERROR_BB_K2                                                           (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
+  #define XSEM_REG_INT_STS_1_INVLD_FOC_ERROR_BB_K2_SHIFT                                                     9
+  #define XSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR_BB_K2                                                          (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define XSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR_BB_K2_SHIFT                                                    10
+  #define XSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR_BB_K2                                                       (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
+  #define XSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR_BB_K2_SHIFT                                                 11
+  #define XSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR_BB_K2                                                      (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
+  #define XSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR_BB_K2_SHIFT                                                12
+#define XSEM_REG_INT_MASK_1                                                                                  0x1400054UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define XSEM_REG_INT_MASK_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5                                             (0x1<<0) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.RBC_COMMON_ACCESS_COL_VFC_ERROR .
+  #define XSEM_REG_INT_MASK_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5_SHIFT                                       0
+  #define XSEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_A_E5                                                 (0x1<<1) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.FAST_EXT_STORE_PUSH_ERROR_A .
+  #define XSEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT                                           1
+  #define XSEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_B_E5                                                 (0x1<<2) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.FAST_EXT_STORE_PUSH_ERROR_B .
+  #define XSEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_B_E5_SHIFT                                           2
+  #define XSEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_A_E5                                                   (0x1<<3) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.FAST_EXT_LOAD_POP_ERROR_A .
+  #define XSEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT                                             3
+  #define XSEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_B_E5                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.FAST_EXT_LOAD_POP_ERROR_B .
+  #define XSEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_B_E5_SHIFT                                             4
+  #define XSEM_REG_INT_MASK_1_FAST_RAM_WR_POP_ERROR_E5                                                       (0x1<<5) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.FAST_RAM_WR_POP_ERROR .
+  #define XSEM_REG_INT_MASK_1_FAST_RAM_WR_POP_ERROR_E5_SHIFT                                                 5
+  #define XSEM_REG_INT_MASK_1_FAST_RAM_RD_PUSH_ERROR_E5                                                      (0x1<<6) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.FAST_RAM_RD_PUSH_ERROR .
+  #define XSEM_REG_INT_MASK_1_FAST_RAM_RD_PUSH_ERROR_E5_SHIFT                                                6
+  #define XSEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_A_E5                                                    (0x1<<7) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.FAST_DRA_RD_PUSH_ERROR_A .
+  #define XSEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT                                              7
+  #define XSEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_B_E5                                                    (0x1<<8) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.FAST_DRA_RD_PUSH_ERROR_B .
+  #define XSEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT                                              8
+  #define XSEM_REG_INT_MASK_1_FAST_DRA_WR_POP_ERROR_A_E5                                                     (0x1<<9) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.FAST_DRA_WR_POP_ERROR_A .
+  #define XSEM_REG_INT_MASK_1_FAST_DRA_WR_POP_ERROR_A_E5_SHIFT                                               9
+  #define XSEM_REG_INT_MASK_1_FAST_DRA_WR_POP_ERROR_B_E5                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.FAST_DRA_WR_POP_ERROR_B .
+  #define XSEM_REG_INT_MASK_1_FAST_DRA_WR_POP_ERROR_B_E5_SHIFT                                               10
+  #define XSEM_REG_INT_MASK_1_SEM_FAST_INVLD_ADDR_ERR_E5                                                     (0x1<<11) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.SEM_FAST_INVLD_ADDR_ERR .
+  #define XSEM_REG_INT_MASK_1_SEM_FAST_INVLD_ADDR_ERR_E5_SHIFT                                               11
+  #define XSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_A_E5                                                       (0x1<<12) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN_A .
+  #define XSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_A_E5_SHIFT                                                 12
+  #define XSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_B_E5                                                       (0x1<<13) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN_B .
+  #define XSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_B_E5_SHIFT                                                 13
+  #define XSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_A_E5                                                       (0x1<<14) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN_A .
+  #define XSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_A_E5_SHIFT                                                 14
+  #define XSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_B_E5                                                       (0x1<<15) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN_B .
+  #define XSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_B_E5_SHIFT                                                 15
+  #define XSEM_REG_INT_MASK_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5                                                (0x1<<16) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.STORM_LDST_ADDR_OVFLW_ATTN_A .
+  #define XSEM_REG_INT_MASK_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5_SHIFT                                          16
+  #define XSEM_REG_INT_MASK_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5                                                (0x1<<17) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.STORM_LDST_ADDR_OVFLW_ATTN_B .
+  #define XSEM_REG_INT_MASK_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5_SHIFT                                          17
+  #define XSEM_REG_INT_MASK_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5                                             (0x1<<18) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.STORM_NON_ALIGNED_ACCESS_ATTN_A .
+  #define XSEM_REG_INT_MASK_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5_SHIFT                                       18
+  #define XSEM_REG_INT_MASK_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5                                             (0x1<<19) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.STORM_NON_ALIGNED_ACCESS_ATTN_B .
+  #define XSEM_REG_INT_MASK_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5_SHIFT                                       19
+  #define XSEM_REG_INT_MASK_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5                                               (0x1<<20) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.STORM_DIVISION_BY_ZERO_ATTN_A .
+  #define XSEM_REG_INT_MASK_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5_SHIFT                                         20
+  #define XSEM_REG_INT_MASK_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5                                               (0x1<<21) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.STORM_DIVISION_BY_ZERO_ATTN_B .
+  #define XSEM_REG_INT_MASK_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5_SHIFT                                         21
+  #define XSEM_REG_INT_MASK_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5                                          (0x1<<22) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A .
+  #define XSEM_REG_INT_MASK_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5_SHIFT                                    22
+  #define XSEM_REG_INT_MASK_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5                                          (0x1<<23) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B .
+  #define XSEM_REG_INT_MASK_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5_SHIFT                                    23
+  #define XSEM_REG_INT_MASK_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5                                           (0x1<<24) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A .
+  #define XSEM_REG_INT_MASK_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5_SHIFT                                     24
+  #define XSEM_REG_INT_MASK_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5                                           (0x1<<25) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B .
+  #define XSEM_REG_INT_MASK_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5_SHIFT                                     25
+  #define XSEM_REG_INT_MASK_1_CAM_RBC_FAST_OUT_ERROR_A_E5                                                    (0x1<<26) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.CAM_RBC_FAST_OUT_ERROR_A .
+  #define XSEM_REG_INT_MASK_1_CAM_RBC_FAST_OUT_ERROR_A_E5_SHIFT                                              26
+  #define XSEM_REG_INT_MASK_1_CAM_RBC_FAST_OUT_ERROR_B_E5                                                    (0x1<<27) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.CAM_RBC_FAST_OUT_ERROR_B .
+  #define XSEM_REG_INT_MASK_1_CAM_RBC_FAST_OUT_ERROR_B_E5_SHIFT                                              27
+  #define XSEM_REG_INT_MASK_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5                                                (0x1<<28) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.CAM_RBC_FAST_MSB_INP_ERROR_A .
+  #define XSEM_REG_INT_MASK_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5_SHIFT                                          28
+  #define XSEM_REG_INT_MASK_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5                                                (0x1<<29) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.CAM_RBC_FAST_MSB_INP_ERROR_B .
+  #define XSEM_REG_INT_MASK_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5_SHIFT                                          29
+  #define XSEM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5                                                (0x1<<30) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.CAM_RBC_FAST_LSB_INP_ERROR_A .
+  #define XSEM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT                                          30
+  #define XSEM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5                                                (0x1<<31) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.CAM_RBC_FAST_LSB_INP_ERROR_B .
+  #define XSEM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5_SHIFT                                          31
+  #define XSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_BB_K2                                                      (0x1<<0) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN .
+  #define XSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_BB_K2_SHIFT                                                0
+  #define XSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_BB_K2                                                      (0x1<<1) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN .
+  #define XSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT                                                1
+  #define XSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR_BB_K2                                                      (0x1<<2) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.STORM_RUNTIME_ERROR .
+  #define XSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR_BB_K2_SHIFT                                                2
+  #define XSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR_BB_K2                                                   (0x1<<3) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.EXT_LOAD_PEND_WR_ERROR .
+  #define XSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT                                             3
+  #define XSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR_BB_K2                                                    (0x1<<4) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.THREAD_RLS_ORUN_ERROR .
+  #define XSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR_BB_K2_SHIFT                                              4
+  #define XSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR_BB_K2                                                    (0x1<<5) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.THREAD_RLS_ALOC_ERROR .
+  #define XSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR_BB_K2_SHIFT                                              5
+  #define XSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR_BB_K2                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.THREAD_RLS_VLD_ERROR .
+  #define XSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR_BB_K2_SHIFT                                               6
+  #define XSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR_BB_K2                                                     (0x1<<7) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.EXT_THREAD_OOR_ERROR .
+  #define XSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT                                               7
+  #define XSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR_BB_K2                                                        (0x1<<8) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.ORD_ID_FIFO_ERROR .
+  #define XSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT                                                  8
+  #define XSEM_REG_INT_MASK_1_INVLD_FOC_ERROR_BB_K2                                                          (0x1<<9) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.INVLD_FOC_ERROR .
+  #define XSEM_REG_INT_MASK_1_INVLD_FOC_ERROR_BB_K2_SHIFT                                                    9
+  #define XSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR_BB_K2                                                         (0x1<<10) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.EXT_LD_LEN_ERROR .
+  #define XSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR_BB_K2_SHIFT                                                   10
+  #define XSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR_BB_K2                                                      (0x1<<11) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.THRD_ORD_FIFO_ERROR .
+  #define XSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR_BB_K2_SHIFT                                                11
+  #define XSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR_BB_K2                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.INVLD_THRD_ORD_ERROR .
+  #define XSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR_BB_K2_SHIFT                                               12
+#define XSEM_REG_INT_STS_WR_1                                                                                0x1400058UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define XSEM_REG_INT_STS_WR_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5                                           (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
+  #define XSEM_REG_INT_STS_WR_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5_SHIFT                                     0
+  #define XSEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5                                               (0x1<<1) // Fast external store FIFO error of Storm_A
+  #define XSEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT                                         1
+  #define XSEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_B_E5                                               (0x1<<2) // Fast external store FIFO error of Storm_B
+  #define XSEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_B_E5_SHIFT                                         2
+  #define XSEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_A_E5                                                 (0x1<<3) // fast external load FIFO error of Storm_A
+  #define XSEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT                                           3
+  #define XSEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_B_E5                                                 (0x1<<4) // fast external load FIFO error of Storm_B
+  #define XSEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_B_E5_SHIFT                                           4
+  #define XSEM_REG_INT_STS_WR_1_FAST_RAM_WR_POP_ERROR_E5                                                     (0x1<<5) // Internal RAM pop error
+  #define XSEM_REG_INT_STS_WR_1_FAST_RAM_WR_POP_ERROR_E5_SHIFT                                               5
+  #define XSEM_REG_INT_STS_WR_1_FAST_RAM_RD_PUSH_ERROR_E5                                                    (0x1<<6) // Internal RAM write error
+  #define XSEM_REG_INT_STS_WR_1_FAST_RAM_RD_PUSH_ERROR_E5_SHIFT                                              6
+  #define XSEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_A_E5                                                  (0x1<<7) // DRA RD FIFO error of Storm A
+  #define XSEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT                                            7
+  #define XSEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_B_E5                                                  (0x1<<8) // DRA RD FIFO error of Storm B
+  #define XSEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT                                            8
+  #define XSEM_REG_INT_STS_WR_1_FAST_DRA_WR_POP_ERROR_A_E5                                                   (0x1<<9) // DRA RD FIFO error of Storm A
+  #define XSEM_REG_INT_STS_WR_1_FAST_DRA_WR_POP_ERROR_A_E5_SHIFT                                             9
+  #define XSEM_REG_INT_STS_WR_1_FAST_DRA_WR_POP_ERROR_B_E5                                                   (0x1<<10) // DRA RD FIFO error of Storm B
+  #define XSEM_REG_INT_STS_WR_1_FAST_DRA_WR_POP_ERROR_B_E5_SHIFT                                             10
+  #define XSEM_REG_INT_STS_WR_1_SEM_FAST_INVLD_ADDR_ERR_E5                                                   (0x1<<11) // Fast invalid address error
+  #define XSEM_REG_INT_STS_WR_1_SEM_FAST_INVLD_ADDR_ERR_E5_SHIFT                                             11
+  #define XSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_A_E5                                                     (0x1<<12) // Storm A stack_uf_attn interrupt
+  #define XSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_A_E5_SHIFT                                               12
+  #define XSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_B_E5                                                     (0x1<<13) // Storm B stack_uf_attn interrupt
+  #define XSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_B_E5_SHIFT                                               13
+  #define XSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_A_E5                                                     (0x1<<14) // Storm A stack_of_attn interrupt
+  #define XSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_A_E5_SHIFT                                               14
+  #define XSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_B_E5                                                     (0x1<<15) // Storm B stack_of_attn interrupt
+  #define XSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_B_E5_SHIFT                                               15
+  #define XSEM_REG_INT_STS_WR_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5                                              (0x1<<16) // Storm A ldst_addr_ovflw_attn interrupt
+  #define XSEM_REG_INT_STS_WR_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5_SHIFT                                        16
+  #define XSEM_REG_INT_STS_WR_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5                                              (0x1<<17) // Storm B ldst_addr_ovflw_attn interrupt
+  #define XSEM_REG_INT_STS_WR_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5_SHIFT                                        17
+  #define XSEM_REG_INT_STS_WR_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5                                           (0x1<<18) // Storm A non_aligned_access_attn interrupt
+  #define XSEM_REG_INT_STS_WR_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5_SHIFT                                     18
+  #define XSEM_REG_INT_STS_WR_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5                                           (0x1<<19) // Storm B non_aligned_access_attn interrupt
+  #define XSEM_REG_INT_STS_WR_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5_SHIFT                                     19
+  #define XSEM_REG_INT_STS_WR_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5                                             (0x1<<20) // Storm A division_by_zero_attn interrupt
+  #define XSEM_REG_INT_STS_WR_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5_SHIFT                                       20
+  #define XSEM_REG_INT_STS_WR_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5                                             (0x1<<21) // Storm B division_by_zero_attn interrupt
+  #define XSEM_REG_INT_STS_WR_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5_SHIFT                                       21
+  #define XSEM_REG_INT_STS_WR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5                                        (0x1<<22) // Storm A illegal_runtime_value_attn interrupt
+  #define XSEM_REG_INT_STS_WR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5_SHIFT                                  22
+  #define XSEM_REG_INT_STS_WR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5                                        (0x1<<23) // Storm B illegal_runtime_value_attn interrupt
+  #define XSEM_REG_INT_STS_WR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5_SHIFT                                  23
+  #define XSEM_REG_INT_STS_WR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5                                         (0x1<<24) // load request is made while previous is still active; not fully read, Storm A
+  #define XSEM_REG_INT_STS_WR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5_SHIFT                                   24
+  #define XSEM_REG_INT_STS_WR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5                                         (0x1<<25) // load request is made while previous is still active; not fully read, Storm B
+  #define XSEM_REG_INT_STS_WR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5_SHIFT                                   25
+  #define XSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_OUT_ERROR_A_E5                                                  (0x1<<26) // Error in CAM_OUT fifo in cam block of STORM A
+  #define XSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_OUT_ERROR_A_E5_SHIFT                                            26
+  #define XSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_OUT_ERROR_B_E5                                                  (0x1<<27) // Error in CAM_OUT fifo in cam block of STORM B
+  #define XSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_OUT_ERROR_B_E5_SHIFT                                            27
+  #define XSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5                                              (0x1<<28) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define XSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5_SHIFT                                        28
+  #define XSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5                                              (0x1<<29) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define XSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5_SHIFT                                        29
+  #define XSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5                                              (0x1<<30) // Error in CAM_LSB_INP fifo in cam block of STORM A
+  #define XSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT                                        30
+  #define XSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5                                              (0x1<<31) // Error in CAM_LSB_INP fifo in cam block of STORM B.
+  #define XSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5_SHIFT                                        31
+  #define XSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_BB_K2                                                    (0x1<<0) // An underflow error was detected in the Storm stack.
+  #define XSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_BB_K2_SHIFT                                              0
+  #define XSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_BB_K2                                                    (0x1<<1) // An overflow error was detected in the Storm stack.
+  #define XSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT                                              1
+  #define XSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR_BB_K2                                                    (0x1<<2) // The Storm detected an illegal runtime value.
+  #define XSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR_BB_K2_SHIFT                                              2
+  #define XSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2                                                 (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
+  #define XSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT                                           3
+  #define XSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR_BB_K2                                                  (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
+  #define XSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR_BB_K2_SHIFT                                            4
+  #define XSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR_BB_K2                                                  (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
+  #define XSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR_BB_K2_SHIFT                                            5
+  #define XSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR_BB_K2                                                   (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
+  #define XSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR_BB_K2_SHIFT                                             6
+  #define XSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR_BB_K2                                                   (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define XSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT                                             7
+  #define XSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR_BB_K2                                                      (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
+  #define XSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT                                                8
+  #define XSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR_BB_K2                                                        (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
+  #define XSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR_BB_K2_SHIFT                                                  9
+  #define XSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR_BB_K2                                                       (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define XSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR_BB_K2_SHIFT                                                 10
+  #define XSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR_BB_K2                                                    (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
+  #define XSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR_BB_K2_SHIFT                                              11
+  #define XSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR_BB_K2                                                   (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
+  #define XSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR_BB_K2_SHIFT                                             12
+#define XSEM_REG_INT_STS_CLR_1                                                                               0x140005cUL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define XSEM_REG_INT_STS_CLR_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5                                          (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
+  #define XSEM_REG_INT_STS_CLR_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5_SHIFT                                    0
+  #define XSEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5                                              (0x1<<1) // Fast external store FIFO error of Storm_A
+  #define XSEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT                                        1
+  #define XSEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_B_E5                                              (0x1<<2) // Fast external store FIFO error of Storm_B
+  #define XSEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_B_E5_SHIFT                                        2
+  #define XSEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_A_E5                                                (0x1<<3) // fast external load FIFO error of Storm_A
+  #define XSEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT                                          3
+  #define XSEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_B_E5                                                (0x1<<4) // fast external load FIFO error of Storm_B
+  #define XSEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_B_E5_SHIFT                                          4
+  #define XSEM_REG_INT_STS_CLR_1_FAST_RAM_WR_POP_ERROR_E5                                                    (0x1<<5) // Internal RAM pop error
+  #define XSEM_REG_INT_STS_CLR_1_FAST_RAM_WR_POP_ERROR_E5_SHIFT                                              5
+  #define XSEM_REG_INT_STS_CLR_1_FAST_RAM_RD_PUSH_ERROR_E5                                                   (0x1<<6) // Internal RAM write error
+  #define XSEM_REG_INT_STS_CLR_1_FAST_RAM_RD_PUSH_ERROR_E5_SHIFT                                             6
+  #define XSEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_A_E5                                                 (0x1<<7) // DRA RD FIFO error of Storm A
+  #define XSEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT                                           7
+  #define XSEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_B_E5                                                 (0x1<<8) // DRA RD FIFO error of Storm B
+  #define XSEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT                                           8
+  #define XSEM_REG_INT_STS_CLR_1_FAST_DRA_WR_POP_ERROR_A_E5                                                  (0x1<<9) // DRA RD FIFO error of Storm A
+  #define XSEM_REG_INT_STS_CLR_1_FAST_DRA_WR_POP_ERROR_A_E5_SHIFT                                            9
+  #define XSEM_REG_INT_STS_CLR_1_FAST_DRA_WR_POP_ERROR_B_E5                                                  (0x1<<10) // DRA RD FIFO error of Storm B
+  #define XSEM_REG_INT_STS_CLR_1_FAST_DRA_WR_POP_ERROR_B_E5_SHIFT                                            10
+  #define XSEM_REG_INT_STS_CLR_1_SEM_FAST_INVLD_ADDR_ERR_E5                                                  (0x1<<11) // Fast invalid address error
+  #define XSEM_REG_INT_STS_CLR_1_SEM_FAST_INVLD_ADDR_ERR_E5_SHIFT                                            11
+  #define XSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_A_E5                                                    (0x1<<12) // Storm A stack_uf_attn interrupt
+  #define XSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_A_E5_SHIFT                                              12
+  #define XSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_B_E5                                                    (0x1<<13) // Storm B stack_uf_attn interrupt
+  #define XSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_B_E5_SHIFT                                              13
+  #define XSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_A_E5                                                    (0x1<<14) // Storm A stack_of_attn interrupt
+  #define XSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_A_E5_SHIFT                                              14
+  #define XSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_B_E5                                                    (0x1<<15) // Storm B stack_of_attn interrupt
+  #define XSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_B_E5_SHIFT                                              15
+  #define XSEM_REG_INT_STS_CLR_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5                                             (0x1<<16) // Storm A ldst_addr_ovflw_attn interrupt
+  #define XSEM_REG_INT_STS_CLR_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5_SHIFT                                       16
+  #define XSEM_REG_INT_STS_CLR_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5                                             (0x1<<17) // Storm B ldst_addr_ovflw_attn interrupt
+  #define XSEM_REG_INT_STS_CLR_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5_SHIFT                                       17
+  #define XSEM_REG_INT_STS_CLR_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5                                          (0x1<<18) // Storm A non_aligned_access_attn interrupt
+  #define XSEM_REG_INT_STS_CLR_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5_SHIFT                                    18
+  #define XSEM_REG_INT_STS_CLR_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5                                          (0x1<<19) // Storm B non_aligned_access_attn interrupt
+  #define XSEM_REG_INT_STS_CLR_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5_SHIFT                                    19
+  #define XSEM_REG_INT_STS_CLR_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5                                            (0x1<<20) // Storm A division_by_zero_attn interrupt
+  #define XSEM_REG_INT_STS_CLR_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5_SHIFT                                      20
+  #define XSEM_REG_INT_STS_CLR_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5                                            (0x1<<21) // Storm B division_by_zero_attn interrupt
+  #define XSEM_REG_INT_STS_CLR_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5_SHIFT                                      21
+  #define XSEM_REG_INT_STS_CLR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5                                       (0x1<<22) // Storm A illegal_runtime_value_attn interrupt
+  #define XSEM_REG_INT_STS_CLR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5_SHIFT                                 22
+  #define XSEM_REG_INT_STS_CLR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5                                       (0x1<<23) // Storm B illegal_runtime_value_attn interrupt
+  #define XSEM_REG_INT_STS_CLR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5_SHIFT                                 23
+  #define XSEM_REG_INT_STS_CLR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5                                        (0x1<<24) // load request is made while previous is still active; not fully read, Storm A
+  #define XSEM_REG_INT_STS_CLR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5_SHIFT                                  24
+  #define XSEM_REG_INT_STS_CLR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5                                        (0x1<<25) // load request is made while previous is still active; not fully read, Storm B
+  #define XSEM_REG_INT_STS_CLR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5_SHIFT                                  25
+  #define XSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_OUT_ERROR_A_E5                                                 (0x1<<26) // Error in CAM_OUT fifo in cam block of STORM A
+  #define XSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_OUT_ERROR_A_E5_SHIFT                                           26
+  #define XSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_OUT_ERROR_B_E5                                                 (0x1<<27) // Error in CAM_OUT fifo in cam block of STORM B
+  #define XSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_OUT_ERROR_B_E5_SHIFT                                           27
+  #define XSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5                                             (0x1<<28) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define XSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5_SHIFT                                       28
+  #define XSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5                                             (0x1<<29) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define XSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5_SHIFT                                       29
+  #define XSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5                                             (0x1<<30) // Error in CAM_LSB_INP fifo in cam block of STORM A
+  #define XSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT                                       30
+  #define XSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5                                             (0x1<<31) // Error in CAM_LSB_INP fifo in cam block of STORM B.
+  #define XSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5_SHIFT                                       31
+  #define XSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_BB_K2                                                   (0x1<<0) // An underflow error was detected in the Storm stack.
+  #define XSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_BB_K2_SHIFT                                             0
+  #define XSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_BB_K2                                                   (0x1<<1) // An overflow error was detected in the Storm stack.
+  #define XSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT                                             1
+  #define XSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR_BB_K2                                                   (0x1<<2) // The Storm detected an illegal runtime value.
+  #define XSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR_BB_K2_SHIFT                                             2
+  #define XSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2                                                (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
+  #define XSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT                                          3
+  #define XSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR_BB_K2                                                 (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
+  #define XSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR_BB_K2_SHIFT                                           4
+  #define XSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR_BB_K2                                                 (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
+  #define XSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR_BB_K2_SHIFT                                           5
+  #define XSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR_BB_K2                                                  (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
+  #define XSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR_BB_K2_SHIFT                                            6
+  #define XSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR_BB_K2                                                  (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define XSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT                                            7
+  #define XSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR_BB_K2                                                     (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
+  #define XSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT                                               8
+  #define XSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR_BB_K2                                                       (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
+  #define XSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR_BB_K2_SHIFT                                                 9
+  #define XSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR_BB_K2                                                      (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define XSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR_BB_K2_SHIFT                                                10
+  #define XSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR_BB_K2                                                   (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
+  #define XSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR_BB_K2_SHIFT                                             11
+  #define XSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR_BB_K2                                                  (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
+  #define XSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR_BB_K2_SHIFT                                            12
+#define XSEM_REG_INT_STS_2_E5                                                                                0x1400060UL //Access:R    DataWidth:0x1f   // Multi Field Register.
+  #define XSEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5                                                 (0x1<<0) // Fast FIN FIFO error of Storm A.
+  #define XSEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5_SHIFT                                           0
+  #define XSEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5                                                 (0x1<<1) // Fast FIN FIFO error of Storm B
+  #define XSEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT                                           1
+  #define XSEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5                                               (0x1<<2) // Fast Debug FIFO error of Storm A
+  #define XSEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5_SHIFT                                         2
+  #define XSEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5                                               (0x1<<3) // Fast Debug FIFO error of Storm B
+  #define XSEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT                                         3
+  #define XSEM_REG_INT_STS_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5                                                (0x1<<4) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define XSEM_REG_INT_STS_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5_SHIFT                                          4
+  #define XSEM_REG_INT_STS_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5                                                (0x1<<5) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define XSEM_REG_INT_STS_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5_SHIFT                                          5
+  #define XSEM_REG_INT_STS_2_VFC_INTERRUPT_E5                                                                (0x1<<6) // interrupt from VFC block
+  #define XSEM_REG_INT_STS_2_VFC_INTERRUPT_E5_SHIFT                                                          6
+  #define XSEM_REG_INT_STS_2_MUX_RBC_VFC_FIFO_ERROR_E5                                                       (0x1<<7) // VFC FIFO error
+  #define XSEM_REG_INT_STS_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT                                                 7
+  #define XSEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_A_E5                                                    (0x1<<8) // Error in FOC error of Storm A.
+  #define XSEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT                                              8
+  #define XSEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_B_E5                                                    (0x1<<9) // Error in FOC error of Storm B.
+  #define XSEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_B_E5_SHIFT                                              9
+  #define XSEM_REG_INT_STS_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5                                                  (0x1<<10) // Invalid allocated thread request with partial FIN of Storm A.
+  #define XSEM_REG_INT_STS_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5_SHIFT                                            10
+  #define XSEM_REG_INT_STS_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5                                                  (0x1<<11) // Invalid allocated thread request with partial FIN of Storm B.
+  #define XSEM_REG_INT_STS_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5_SHIFT                                            11
+  #define XSEM_REG_INT_STS_2_CAM_RBC_INPUT_FIFO_ERROR_E5                                                     (0x1<<12) // Cam input FIFO error
+  #define XSEM_REG_INT_STS_2_CAM_RBC_INPUT_FIFO_ERROR_E5_SHIFT                                               12
+  #define XSEM_REG_INT_STS_2_ARB_RBC_FIFO_ERROR_A_E5                                                         (0x1<<13) // Pre-fetch FIFO error of Storm A.
+  #define XSEM_REG_INT_STS_2_ARB_RBC_FIFO_ERROR_A_E5_SHIFT                                                   13
+  #define XSEM_REG_INT_STS_2_ARB_RBC_FIFO_ERROR_B_E5                                                         (0x1<<14) // Pre-fetch FIFO error of Storm B.
+  #define XSEM_REG_INT_STS_2_ARB_RBC_FIFO_ERROR_B_E5_SHIFT                                                   14
+  #define XSEM_REG_INT_STS_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5                                                 (0x1<<15) // Lock is acquired more than maximum configured time.
+  #define XSEM_REG_INT_STS_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5_SHIFT                                           15
+  #define XSEM_REG_INT_STS_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                                  (0x1<<16) // Ilegal assetion commands towards lock block.
+  #define XSEM_REG_INT_STS_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5_SHIFT                                            16
+  #define XSEM_REG_INT_STS_2_LOCK_RBC_REQ_RELEASE_ERROR_E5                                                   (0x1<<17) // Error when trying to release a lock which is not acquired (key does not match any lock)
+  #define XSEM_REG_INT_STS_2_LOCK_RBC_REQ_RELEASE_ERROR_E5_SHIFT                                             17
+  #define XSEM_REG_INT_STS_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5                                                 (0x1<<18) // Trying to acquire a lock which is already acquired.
+  #define XSEM_REG_INT_STS_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5_SHIFT                                           18
+  #define XSEM_REG_INT_STS_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5                                                (0x1<<19) // Trying to relinquish a key which does not exist.
+  #define XSEM_REG_INT_STS_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5_SHIFT                                          19
+  #define XSEM_REG_INT_STS_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5                                                (0x1<<20) // A lock acquired requrest is issued when all locks are used.
+  #define XSEM_REG_INT_STS_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5_SHIFT                                          20
+  #define XSEM_REG_INT_STS_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5                                                (0x1<<21) // Error when both Storm are stalled due to lock block (may indicate a dead lock).
+  #define XSEM_REG_INT_STS_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5_SHIFT                                          21
+  #define XSEM_REG_INT_STS_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5                                            (0x1<<22) // Fin done with remainning allocated threads STORM_A.
+  #define XSEM_REG_INT_STS_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5_SHIFT                                      22
+  #define XSEM_REG_INT_STS_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5                                            (0x1<<23) // Fin done with remainning allocated threads STORM_B.
+  #define XSEM_REG_INT_STS_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5_SHIFT                                      23
+  #define XSEM_REG_INT_STS_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5                                            (0x1<<24) // Fin new thread request when no thread is allocated for handler of Storm A.
+  #define XSEM_REG_INT_STS_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5_SHIFT                                      24
+  #define XSEM_REG_INT_STS_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5                                            (0x1<<25) // Fin new thread request when no thread is allocated for handler of Storm B.
+  #define XSEM_REG_INT_STS_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5_SHIFT                                      25
+  #define XSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5                                      (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same range.
+  #define XSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5_SHIFT                                26
+  #define XSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5                                      (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same range.
+  #define XSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5_SHIFT                                27
+  #define XSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5                                         (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
+  #define XSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5_SHIFT                                   28
+  #define XSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5                                         (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
+  #define XSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5_SHIFT                                   29
+  #define XSEM_REG_INT_STS_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5                                          (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
+  #define XSEM_REG_INT_STS_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT                                    30
+#define XSEM_REG_INT_MASK_2_E5                                                                               0x1400064UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define XSEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5                                                (0x1<<0) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.RD_RBC_FAST_FIN_FIFO_ERROR_A .
+  #define XSEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5_SHIFT                                          0
+  #define XSEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5                                                (0x1<<1) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.RD_RBC_FAST_FIN_FIFO_ERROR_B .
+  #define XSEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT                                          1
+  #define XSEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5                                              (0x1<<2) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.SYNC_RBC_FAST_DBG_PUSH_ERROR_A .
+  #define XSEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5_SHIFT                                        2
+  #define XSEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5                                              (0x1<<3) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.SYNC_RBC_FAST_DBG_PUSH_ERROR_B .
+  #define XSEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT                                        3
+  #define XSEM_REG_INT_MASK_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5                                               (0x1<<4) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.CAM_RBC_FAST_MSB2_INP_ERROR_A .
+  #define XSEM_REG_INT_MASK_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5_SHIFT                                         4
+  #define XSEM_REG_INT_MASK_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5                                               (0x1<<5) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.CAM_RBC_FAST_MSB2_INP_ERROR_B .
+  #define XSEM_REG_INT_MASK_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5_SHIFT                                         5
+  #define XSEM_REG_INT_MASK_2_VFC_INTERRUPT_E5                                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.VFC_INTERRUPT .
+  #define XSEM_REG_INT_MASK_2_VFC_INTERRUPT_E5_SHIFT                                                         6
+  #define XSEM_REG_INT_MASK_2_MUX_RBC_VFC_FIFO_ERROR_E5                                                      (0x1<<7) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.MUX_RBC_VFC_FIFO_ERROR .
+  #define XSEM_REG_INT_MASK_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT                                                7
+  #define XSEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_A_E5                                                   (0x1<<8) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.FIN_RBC_INVLD_FOC_ERROR_A .
+  #define XSEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT                                             8
+  #define XSEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_B_E5                                                   (0x1<<9) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.FIN_RBC_INVLD_FOC_ERROR_B .
+  #define XSEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_B_E5_SHIFT                                             9
+  #define XSEM_REG_INT_MASK_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5                                                 (0x1<<10) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.FIN_RBC_INVLD_ALLOC_ERROR_A .
+  #define XSEM_REG_INT_MASK_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5_SHIFT                                           10
+  #define XSEM_REG_INT_MASK_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5                                                 (0x1<<11) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.FIN_RBC_INVLD_ALLOC_ERROR_B .
+  #define XSEM_REG_INT_MASK_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5_SHIFT                                           11
+  #define XSEM_REG_INT_MASK_2_CAM_RBC_INPUT_FIFO_ERROR_E5                                                    (0x1<<12) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.CAM_RBC_INPUT_FIFO_ERROR .
+  #define XSEM_REG_INT_MASK_2_CAM_RBC_INPUT_FIFO_ERROR_E5_SHIFT                                              12
+  #define XSEM_REG_INT_MASK_2_ARB_RBC_FIFO_ERROR_A_E5                                                        (0x1<<13) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.ARB_RBC_FIFO_ERROR_A .
+  #define XSEM_REG_INT_MASK_2_ARB_RBC_FIFO_ERROR_A_E5_SHIFT                                                  13
+  #define XSEM_REG_INT_MASK_2_ARB_RBC_FIFO_ERROR_B_E5                                                        (0x1<<14) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.ARB_RBC_FIFO_ERROR_B .
+  #define XSEM_REG_INT_MASK_2_ARB_RBC_FIFO_ERROR_B_E5_SHIFT                                                  14
+  #define XSEM_REG_INT_MASK_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5                                                (0x1<<15) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.LOCK_RBC_REQ_MAX_STALL_ERROR .
+  #define XSEM_REG_INT_MASK_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5_SHIFT                                          15
+  #define XSEM_REG_INT_MASK_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                                 (0x1<<16) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.LOCK_RBC_REQ_CMD_RATE_ERROR .
+  #define XSEM_REG_INT_MASK_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5_SHIFT                                           16
+  #define XSEM_REG_INT_MASK_2_LOCK_RBC_REQ_RELEASE_ERROR_E5                                                  (0x1<<17) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.LOCK_RBC_REQ_RELEASE_ERROR .
+  #define XSEM_REG_INT_MASK_2_LOCK_RBC_REQ_RELEASE_ERROR_E5_SHIFT                                            17
+  #define XSEM_REG_INT_MASK_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5                                                (0x1<<18) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.LOCK_RBC_REQ_REDUNDENT_ERROR .
+  #define XSEM_REG_INT_MASK_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5_SHIFT                                          18
+  #define XSEM_REG_INT_MASK_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5                                               (0x1<<19) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.LOCK_RBC_REQ_RELINQUISH_ERROR .
+  #define XSEM_REG_INT_MASK_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5_SHIFT                                         19
+  #define XSEM_REG_INT_MASK_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5                                               (0x1<<20) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.LOCK_RBC_REQ_STALL_FULL_ERROR .
+  #define XSEM_REG_INT_MASK_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5_SHIFT                                         20
+  #define XSEM_REG_INT_MASK_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5                                               (0x1<<21) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.LOCK_RBC_REQ_DUAL_STALL_ERROR .
+  #define XSEM_REG_INT_MASK_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5_SHIFT                                         21
+  #define XSEM_REG_INT_MASK_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5                                           (0x1<<22) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A .
+  #define XSEM_REG_INT_MASK_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5_SHIFT                                     22
+  #define XSEM_REG_INT_MASK_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5                                           (0x1<<23) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B .
+  #define XSEM_REG_INT_MASK_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5_SHIFT                                     23
+  #define XSEM_REG_INT_MASK_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5                                           (0x1<<24) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.DRA_INT_GRC_NON_FREE_THRD_ERROR_A .
+  #define XSEM_REG_INT_MASK_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5_SHIFT                                     24
+  #define XSEM_REG_INT_MASK_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5                                           (0x1<<25) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.DRA_INT_GRC_NON_FREE_THRD_ERROR_B .
+  #define XSEM_REG_INT_MASK_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5_SHIFT                                     25
+  #define XSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5                                     (0x1<<26) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A .
+  #define XSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5_SHIFT                               26
+  #define XSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5                                     (0x1<<27) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B .
+  #define XSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5_SHIFT                               27
+  #define XSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5                                        (0x1<<28) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A .
+  #define XSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5_SHIFT                                  28
+  #define XSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5                                        (0x1<<29) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B .
+  #define XSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5_SHIFT                                  29
+  #define XSEM_REG_INT_MASK_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5                                         (0x1<<30) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR .
+  #define XSEM_REG_INT_MASK_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT                                   30
+#define XSEM_REG_INT_STS_WR_2_E5                                                                             0x1400068UL //Access:WR   DataWidth:0x1f   // Multi Field Register.
+  #define XSEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5                                              (0x1<<0) // Fast FIN FIFO error of Storm A.
+  #define XSEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5_SHIFT                                        0
+  #define XSEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5                                              (0x1<<1) // Fast FIN FIFO error of Storm B
+  #define XSEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT                                        1
+  #define XSEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5                                            (0x1<<2) // Fast Debug FIFO error of Storm A
+  #define XSEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5_SHIFT                                      2
+  #define XSEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5                                            (0x1<<3) // Fast Debug FIFO error of Storm B
+  #define XSEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT                                      3
+  #define XSEM_REG_INT_STS_WR_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5                                             (0x1<<4) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define XSEM_REG_INT_STS_WR_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5_SHIFT                                       4
+  #define XSEM_REG_INT_STS_WR_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5                                             (0x1<<5) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define XSEM_REG_INT_STS_WR_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5_SHIFT                                       5
+  #define XSEM_REG_INT_STS_WR_2_VFC_INTERRUPT_E5                                                             (0x1<<6) // interrupt from VFC block
+  #define XSEM_REG_INT_STS_WR_2_VFC_INTERRUPT_E5_SHIFT                                                       6
+  #define XSEM_REG_INT_STS_WR_2_MUX_RBC_VFC_FIFO_ERROR_E5                                                    (0x1<<7) // VFC FIFO error
+  #define XSEM_REG_INT_STS_WR_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT                                              7
+  #define XSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5                                                 (0x1<<8) // Error in FOC error of Storm A.
+  #define XSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT                                           8
+  #define XSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_B_E5                                                 (0x1<<9) // Error in FOC error of Storm B.
+  #define XSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_B_E5_SHIFT                                           9
+  #define XSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5                                               (0x1<<10) // Invalid allocated thread request with partial FIN of Storm A.
+  #define XSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5_SHIFT                                         10
+  #define XSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5                                               (0x1<<11) // Invalid allocated thread request with partial FIN of Storm B.
+  #define XSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5_SHIFT                                         11
+  #define XSEM_REG_INT_STS_WR_2_CAM_RBC_INPUT_FIFO_ERROR_E5                                                  (0x1<<12) // Cam input FIFO error
+  #define XSEM_REG_INT_STS_WR_2_CAM_RBC_INPUT_FIFO_ERROR_E5_SHIFT                                            12
+  #define XSEM_REG_INT_STS_WR_2_ARB_RBC_FIFO_ERROR_A_E5                                                      (0x1<<13) // Pre-fetch FIFO error of Storm A.
+  #define XSEM_REG_INT_STS_WR_2_ARB_RBC_FIFO_ERROR_A_E5_SHIFT                                                13
+  #define XSEM_REG_INT_STS_WR_2_ARB_RBC_FIFO_ERROR_B_E5                                                      (0x1<<14) // Pre-fetch FIFO error of Storm B.
+  #define XSEM_REG_INT_STS_WR_2_ARB_RBC_FIFO_ERROR_B_E5_SHIFT                                                14
+  #define XSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5                                              (0x1<<15) // Lock is acquired more than maximum configured time.
+  #define XSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5_SHIFT                                        15
+  #define XSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                               (0x1<<16) // Ilegal assetion commands towards lock block.
+  #define XSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5_SHIFT                                         16
+  #define XSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_RELEASE_ERROR_E5                                                (0x1<<17) // Error when trying to release a lock which is not acquired (key does not match any lock)
+  #define XSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_RELEASE_ERROR_E5_SHIFT                                          17
+  #define XSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5                                              (0x1<<18) // Trying to acquire a lock which is already acquired.
+  #define XSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5_SHIFT                                        18
+  #define XSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5                                             (0x1<<19) // Trying to relinquish a key which does not exist.
+  #define XSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5_SHIFT                                       19
+  #define XSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5                                             (0x1<<20) // A lock acquired requrest is issued when all locks are used.
+  #define XSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5_SHIFT                                       20
+  #define XSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5                                             (0x1<<21) // Error when both Storm are stalled due to lock block (may indicate a dead lock).
+  #define XSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5_SHIFT                                       21
+  #define XSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5                                         (0x1<<22) // Fin done with remainning allocated threads STORM_A.
+  #define XSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5_SHIFT                                   22
+  #define XSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5                                         (0x1<<23) // Fin done with remainning allocated threads STORM_B.
+  #define XSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5_SHIFT                                   23
+  #define XSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5                                         (0x1<<24) // Fin new thread request when no thread is allocated for handler of Storm A.
+  #define XSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5_SHIFT                                   24
+  #define XSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5                                         (0x1<<25) // Fin new thread request when no thread is allocated for handler of Storm B.
+  #define XSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5_SHIFT                                   25
+  #define XSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5                                   (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same range.
+  #define XSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5_SHIFT                             26
+  #define XSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5                                   (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same range.
+  #define XSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5_SHIFT                             27
+  #define XSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5                                      (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
+  #define XSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5_SHIFT                                28
+  #define XSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5                                      (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
+  #define XSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5_SHIFT                                29
+  #define XSEM_REG_INT_STS_WR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5                                       (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
+  #define XSEM_REG_INT_STS_WR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT                                 30
+#define XSEM_REG_INT_STS_CLR_2_E5                                                                            0x140006cUL //Access:RC   DataWidth:0x1f   // Multi Field Register.
+  #define XSEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5                                             (0x1<<0) // Fast FIN FIFO error of Storm A.
+  #define XSEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5_SHIFT                                       0
+  #define XSEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5                                             (0x1<<1) // Fast FIN FIFO error of Storm B
+  #define XSEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT                                       1
+  #define XSEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5                                           (0x1<<2) // Fast Debug FIFO error of Storm A
+  #define XSEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5_SHIFT                                     2
+  #define XSEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5                                           (0x1<<3) // Fast Debug FIFO error of Storm B
+  #define XSEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT                                     3
+  #define XSEM_REG_INT_STS_CLR_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5                                            (0x1<<4) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define XSEM_REG_INT_STS_CLR_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5_SHIFT                                      4
+  #define XSEM_REG_INT_STS_CLR_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5                                            (0x1<<5) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define XSEM_REG_INT_STS_CLR_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5_SHIFT                                      5
+  #define XSEM_REG_INT_STS_CLR_2_VFC_INTERRUPT_E5                                                            (0x1<<6) // interrupt from VFC block
+  #define XSEM_REG_INT_STS_CLR_2_VFC_INTERRUPT_E5_SHIFT                                                      6
+  #define XSEM_REG_INT_STS_CLR_2_MUX_RBC_VFC_FIFO_ERROR_E5                                                   (0x1<<7) // VFC FIFO error
+  #define XSEM_REG_INT_STS_CLR_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT                                             7
+  #define XSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5                                                (0x1<<8) // Error in FOC error of Storm A.
+  #define XSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT                                          8
+  #define XSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_B_E5                                                (0x1<<9) // Error in FOC error of Storm B.
+  #define XSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_B_E5_SHIFT                                          9
+  #define XSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5                                              (0x1<<10) // Invalid allocated thread request with partial FIN of Storm A.
+  #define XSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5_SHIFT                                        10
+  #define XSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5                                              (0x1<<11) // Invalid allocated thread request with partial FIN of Storm B.
+  #define XSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5_SHIFT                                        11
+  #define XSEM_REG_INT_STS_CLR_2_CAM_RBC_INPUT_FIFO_ERROR_E5                                                 (0x1<<12) // Cam input FIFO error
+  #define XSEM_REG_INT_STS_CLR_2_CAM_RBC_INPUT_FIFO_ERROR_E5_SHIFT                                           12
+  #define XSEM_REG_INT_STS_CLR_2_ARB_RBC_FIFO_ERROR_A_E5                                                     (0x1<<13) // Pre-fetch FIFO error of Storm A.
+  #define XSEM_REG_INT_STS_CLR_2_ARB_RBC_FIFO_ERROR_A_E5_SHIFT                                               13
+  #define XSEM_REG_INT_STS_CLR_2_ARB_RBC_FIFO_ERROR_B_E5                                                     (0x1<<14) // Pre-fetch FIFO error of Storm B.
+  #define XSEM_REG_INT_STS_CLR_2_ARB_RBC_FIFO_ERROR_B_E5_SHIFT                                               14
+  #define XSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5                                             (0x1<<15) // Lock is acquired more than maximum configured time.
+  #define XSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5_SHIFT                                       15
+  #define XSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                              (0x1<<16) // Ilegal assetion commands towards lock block.
+  #define XSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5_SHIFT                                        16
+  #define XSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_RELEASE_ERROR_E5                                               (0x1<<17) // Error when trying to release a lock which is not acquired (key does not match any lock)
+  #define XSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_RELEASE_ERROR_E5_SHIFT                                         17
+  #define XSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5                                             (0x1<<18) // Trying to acquire a lock which is already acquired.
+  #define XSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5_SHIFT                                       18
+  #define XSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5                                            (0x1<<19) // Trying to relinquish a key which does not exist.
+  #define XSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5_SHIFT                                      19
+  #define XSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5                                            (0x1<<20) // A lock acquired requrest is issued when all locks are used.
+  #define XSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5_SHIFT                                      20
+  #define XSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5                                            (0x1<<21) // Error when both Storm are stalled due to lock block (may indicate a dead lock).
+  #define XSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5_SHIFT                                      21
+  #define XSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5                                        (0x1<<22) // Fin done with remainning allocated threads STORM_A.
+  #define XSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5_SHIFT                                  22
+  #define XSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5                                        (0x1<<23) // Fin done with remainning allocated threads STORM_B.
+  #define XSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5_SHIFT                                  23
+  #define XSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5                                        (0x1<<24) // Fin new thread request when no thread is allocated for handler of Storm A.
+  #define XSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5_SHIFT                                  24
+  #define XSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5                                        (0x1<<25) // Fin new thread request when no thread is allocated for handler of Storm B.
+  #define XSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5_SHIFT                                  25
+  #define XSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5                                  (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same range.
+  #define XSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5_SHIFT                            26
+  #define XSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5                                  (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same range.
+  #define XSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5_SHIFT                            27
+  #define XSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5                                     (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
+  #define XSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5_SHIFT                               28
+  #define XSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5                                     (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
+  #define XSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5_SHIFT                               29
+  #define XSEM_REG_INT_STS_CLR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5                                      (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
+  #define XSEM_REG_INT_STS_CLR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT                                30
+#define XSEM_REG_PRTY_MASK                                                                                   0x14000ccUL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define XSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR                                                            (0x1<<0) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS.VFC_RBC_PARITY_ERROR .
+  #define XSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR_SHIFT                                                      0
+  #define XSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR                                                           (0x1<<1) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS.STORM_RF_PARITY_ERROR .
+  #define XSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR_SHIFT                                                     1
+  #define XSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR                                                            (0x1<<2) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS.REG_GEN_PARITY_ERROR .
+  #define XSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR_SHIFT                                                      2
+#define XSEM_REG_PRTY_MASK_H_0_BB_K2                                                                         0x1400204UL //Access:RW   DataWidth:0x7    // Multi Field Register.
+  #define XSEM_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT_BB_K2                                                 (0x1<<0) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS_H_0.MEM006_I_ECC_0_RF_INT .
+  #define XSEM_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT_BB_K2_SHIFT                                           0
+  #define XSEM_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT_BB_K2                                                 (0x1<<1) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS_H_0.MEM006_I_ECC_1_RF_INT .
+  #define XSEM_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT_BB_K2_SHIFT                                           1
+  #define XSEM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2                                                     (0x1<<2) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define XSEM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT                                               2
+  #define XSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                     (0x1<<3) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define XSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                               3
+  #define XSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                     (0x1<<4) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define XSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                               4
+  #define XSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                     (0x1<<5) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define XSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                               5
+  #define XSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                     (0x1<<6) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define XSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                               6
+#define XSEM_REG_MEM_ECC_ENABLE_0_BB_K2                                                                      0x1400210UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define XSEM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_0_EN_BB_K2                                                  (0x1<<0) // Enable ECC for memory ecc instance xsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_0 in module sem_slow_pas_buf_ram
+  #define XSEM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_0_EN_BB_K2_SHIFT                                            0
+  #define XSEM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_1_EN_BB_K2                                                  (0x1<<1) // Enable ECC for memory ecc instance xsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_1 in module sem_slow_pas_buf_ram
+  #define XSEM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_1_EN_BB_K2_SHIFT                                            1
+#define XSEM_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                 0x1400214UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define XSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_0_PRTY_BB_K2                                           (0x1<<0) // Set parity only for memory ecc instance xsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_0 in module sem_slow_pas_buf_ram
+  #define XSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_0_PRTY_BB_K2_SHIFT                                     0
+  #define XSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_1_PRTY_BB_K2                                           (0x1<<1) // Set parity only for memory ecc instance xsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_1 in module sem_slow_pas_buf_ram
+  #define XSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_1_PRTY_BB_K2_SHIFT                                     1
+#define XSEM_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                             0x1400218UL //Access:RC   DataWidth:0x2    // Multi Field Register.
+  #define XSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_0_CORRECT_BB_K2                                    (0x1<<0) // Record if a correctable error occurred on memory ecc instance xsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_0 in module sem_slow_pas_buf_ram
+  #define XSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_0_CORRECT_BB_K2_SHIFT                              0
+  #define XSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_1_CORRECT_BB_K2                                    (0x1<<1) // Record if a correctable error occurred on memory ecc instance xsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_1 in module sem_slow_pas_buf_ram
+  #define XSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_1_CORRECT_BB_K2_SHIFT                              1
+#define XSEM_REG_MEM_ECC_EVENTS_BB_K2                                                                        0x140021cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define XSEM_REG_ARB_CYCLE_SIZE_BB_K2                                                                        0x1400400UL //Access:RW   DataWidth:0x5    // The number of time_slots in the arbitration cycle.
+#define XSEM_REG_VF_ERROR                                                                                    0x1400408UL //Access:WR   DataWidth:0x1    // This VF-split register provides read/clear access to the VF error received from the SDM for a DMA transfer. Reading this register will return the VF Error for value for the corresponding VF. Writing a 1 to this register will clear the error for the corresponding VF.
+#define XSEM_REG_PF_ERROR                                                                                    0x140040cUL //Access:WR   DataWidth:0x1    // This PF-split register provides read/clear access to the PF error received from the SDM for a DMA transfer. Reading this register will return the PF Error for value for the corresponding PF. Writing a 1 to this register will clear the error for the corresponding PF.
+#define XSEM_REG_VF_ERR_VECTOR                                                                               0x1400420UL //Access:WB_R DataWidth:0xf0   // This read-only register provides a vector of bits having an error indication per VF where the Bit position corresponds to the VFID.
+#define XSEM_REG_VF_ERR_VECTOR_SIZE_BB                                                                       4
+#define XSEM_REG_VF_ERR_VECTOR_SIZE_K2_E5                                                                    8
+#define XSEM_REG_PF_ERR_VECTOR                                                                               0x1400440UL //Access:R    DataWidth:0x10   // This read-only register provides a vector of bits having an error indication per PF where the Bit position corresponds to the PFID.
+#define XSEM_REG_CLEAR_STALL                                                                                 0x1400444UL //Access:RW   DataWidth:0x1    // Clear stall signal sent from local storm to external storms.
+#define XSEM_REG_EXCEPTION_INT                                                                               0x1400448UL //Access:RW   DataWidth:0x10   // Provides a default PRAM address to be used for the handler in the event that the PRAM address retrieved from the interrupt table is out of range with regard to the actual PRAM size provided in the SEMI instance.
+#define XSEM_REG_EXT_STORE_FREE_ENTRIES_BB_K2                                                                0x140044cUL //Access:R    DataWidth:0x6    // Number of free entries in the external STORE sync FIFO.
+#define XSEM_REG_GPI_DATA_A_E5                                                                               0x1400450UL //Access:R    DataWidth:0x20   // Used to read the GPI input signals of Storm A.
+#define XSEM_REG_GPI_DATA_BB_K2                                                                              0x1400450UL //Access:R    DataWidth:0x20   // Used to read the GPI input signals.
+#define XSEM_REG_GPRE_SAMP_PERIOD_BB_K2                                                                      0x1400454UL //Access:RW   DataWidth:0x4    // Defines the number of system clocks from one sample of GPRE sync data and the next.
+#define XSEM_REG_ALLOW_LP_SLEEP_THRD                                                                         0x1400458UL //Access:RW   DataWidth:0x1    // When set, this bit is used to allow low-power mode to be activated while threads are sleeping in the passive buffer, as long as the SEMI/Storm remains idle.
+#define XSEM_REG_ECO_RESERVED                                                                                0x140045cUL //Access:RW   DataWidth:0x20   // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
+#define XSEM_REG_PB_WR_SDM_DMA_MODE_E5                                                                       0x1400460UL //Access:RW   DataWidth:0x2    // This register can set the mode of the SDM DMA write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use regardless write mode. 11 - Disable write mode.
+#define XSEM_REG_PB_WR_DRA_RD_CUT_THROUGH_MODE_E5                                                            0x1400464UL //Access:RW   DataWidth:0x1    // This register set the DRA RD block cut through mode in which write to a thread address section passive buffer may occur simultaneously with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut through mode active.
+#define XSEM_REG_GPI_DATA_B_E5                                                                               0x1400468UL //Access:R    DataWidth:0x20   // Used to read the GPI input signals of Storm B.
+#define XSEM_REG_FIC_FIFO_BB_K2                                                                              0x1400580UL //Access:WB_R DataWidth:0x80   // Used for debugging to read/write to/from the FIC FIFOs. The address selects which FIFO should be accessed.
+#define XSEM_REG_FIC_FIFO_SIZE                                                                               8
+#define XSEM_REG_FIC_MIN_MSG_BB_K2                                                                           0x1400600UL //Access:RW   DataWidth:0x6    // Per-FIC interface register array defines minimum number of cycles in the FIC interfaces after which the message can be sent to the passive register_file.
+#define XSEM_REG_FIC_MIN_MSG_SIZE                                                                            2
+#define XSEM_REG_FIC_EMPTY_CT_MODE_BB_K2                                                                     0x1400620UL //Access:RW   DataWidth:0x1    // When set, enables the "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require that the available ("go") counter is non-zero before making a transfer request to the DRA arbiter and starting a transfer.
+#define XSEM_REG_FIC_EMPTY_CT_CNT_BB_K2                                                                      0x1400624UL //Access:RC   DataWidth:0x18   // Statistics counter used to count the number of FIC messages that have been received on any FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
+#define XSEM_REG_FOC_CREDIT                                                                                  0x1400680UL //Access:RW   DataWidth:0x8    // Array of registers provides the initial credits on each of the associatef FOC interfaces. Reading from this register provides the current FOR credit value.
+#define XSEM_REG_FOC_CREDIT_SIZE                                                                             2
+#define XSEM_REG_FULL_FOC_DRA_STRT_EN_BB_K2                                                                  0x14006c0UL //Access:RW   DataWidth:0x1    // When set, this bit allows the DRA read operation to start even when there are not enough credits on all the participating FOC interfaces to complete the entire transaction. The transfer will stall only when a transfer cycle is reached in which there are no interface credits, at which time the DRA transfer will remain stalled until the FOC destination(s) has at least a single credit. When this configuration is cleared, the DRA read transfer will not begin until there are enough credits on all the participating FOC interfaces for the entire transfer.
+#define XSEM_REG_FIN_COMMAND_BB_K2                                                                           0x1400700UL //Access:WB_R DataWidth:0x164  // Last fin command that was read from fifo. Its spelling in FIN_FIFO register.
+#define XSEM_REG_FIN_COMMAND_SIZE                                                                            16
+#define XSEM_REG_FIN_FIFO_BB_K2                                                                              0x1400800UL //Access:WB_R DataWidth:0x164  // READ ONLY FOR DEBUGGING! [5:0]   start_rp_foc3; [11:6] start_rp_foc2;  [17:12]   start_rp_foc1; [23:18] start_rp_foc0;  [29:24]   end_rp_foc3; [35:30] end_rp_foc2; [41:36]   end_rp_foc1; [47:42]   end_rp_foc0; [53:48]   lowest rp; [59:54]   highest rp; [65:60]   store start rp; [71:66]   store end rp; [77:72]   load start rp; [83:78]   load end rp; [85:84]   priority; [101:86]  pram address; [102] pas; [103] foc3; [104] foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:0] is valid.
+#define XSEM_REG_FIN_FIFO_SIZE                                                                               16
+#define XSEM_REG_INVLD_PAS_WR_EN_BB_K2                                                                       0x1400900UL //Access:RW   DataWidth:0x1    // When set, an attempt to write to the passive buffer over the external passive interface will be enabled even if the partition being written is owned by a thread whose valid bit is not set. Otherwise if cleared, the transfer will be stalled.
+#define XSEM_REG_ARBITER_REQUEST_BB_K2                                                                       0x1400980UL //Access:R    DataWidth:0x5    // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2.
+#define XSEM_REG_ARBITER_SELECT_BB_K2                                                                        0x1400984UL //Access:R    DataWidth:0x5    // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2.
+#define XSEM_REG_ARBITER_SLOT_BB_K2                                                                          0x1400988UL //Access:R    DataWidth:0x5    // Dra arbiter last slot.
+#define XSEM_REG_ARB_AS_DEF_BB_K2                                                                            0x1400a00UL //Access:RW   DataWidth:0x3    // Two-dimensional register array is used to define each of four arbitration schemes used by the main DRA arbiter. For this, bits 4:3 of the offset are used to select the arbitration scheme 0-3. Bits 2:0 of the offset are used to define the five priority sources for the selected scheme, where for each priority (0-4), an arbiter source is assigned. Valid values for these configurations are the source enumerations, where FIC0=0x0, FIC1=0x1, wake priority0=0x2, wake priority1=0x3 and wake priority2=0x4. Note that there are holes in the indirect offset address which always return zero when read. These exist at offsets 0x5-0x7, 0xd-0xf, 0x15-0x17 and 0x1d-0x1f.
+#define XSEM_REG_ARB_AS_DEF_SIZE                                                                             32
+#define XSEM_REG_ARB_TS_AS_BB_K2                                                                             0x1400a80UL //Access:RW   DataWidth:0x2    // Register array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
+#define XSEM_REG_ARB_TS_AS_SIZE                                                                              20
+#define XSEM_REG_NUM_OF_THREADS                                                                              0x1400b00UL //Access:R    DataWidth:0x8    // The number of currently free threads (in invalid state).
+#define XSEM_REG_THREAD_ERROR_LOW_E5                                                                         0x1400b04UL //Access:R    DataWidth:0x20   // Thread error low indication. Represents threads 31 -0
+#define XSEM_REG_THREAD_ERROR_BB_K2                                                                          0x1400b04UL //Access:R    DataWidth:0x18   // Thread error indication.
+#define XSEM_REG_THREAD_RDY_BB_K2                                                                            0x1400b08UL //Access:R    DataWidth:0x18   // Thread ready indication.
+#define XSEM_REG_THREAD_SET_NUM                                                                              0x1400b0cUL //Access:W    DataWidth:0x6    // Thread ID. Write thread ID will set ready indication for this thread ID.
+#define XSEM_REG_THREAD_VALID_BB_K2                                                                          0x1400b10UL //Access:R    DataWidth:0x18   // Valid sleeping threads.
+#define XSEM_REG_THREADS_LIST_BB_K2                                                                          0x1400b14UL //Access:RW   DataWidth:0x18   // List of free threads.
+#define XSEM_REG_THREAD_NUMBER_E5                                                                            0x1400b18UL //Access:RW   DataWidth:0x8    // Defines the maixmum number of supported threads in SEMI.
+#define XSEM_REG_THREAD_ERROR_HIGH_E5                                                                        0x1400b1cUL //Access:R    DataWidth:0x18   // Thread error high indication. Represents threads  55-32
+#define XSEM_REG_FOC_MIN_MESSAGE_CREDIT_E5                                                                   0x1400b40UL //Access:RW   DataWidth:0x8    // This field defines for each FOC the minimum message reuired for the FOC transfer to start.
+#define XSEM_REG_FOC_MIN_MESSAGE_CREDIT_SIZE                                                                 2
+#define XSEM_REG_ORDER_HEAD_BB_K2                                                                            0x1400c00UL //Access:RW   DataWidth:0x5    // This (indirect) register array of registers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
+#define XSEM_REG_ORDER_HEAD_SIZE                                                                             8
+#define XSEM_REG_ORDER_TAIL_BB_K2                                                                            0x1400c80UL //Access:RW   DataWidth:0x5    // This (indirect) register array of registers provides read/write access to the tail pointers assigned to each of the thread ordering queues.
+#define XSEM_REG_ORDER_TAIL_SIZE                                                                             8
+#define XSEM_REG_ORDER_EMPTY_BB_K2                                                                           0x1400d00UL //Access:RW   DataWidth:0x1    // This vector provides read-only access to the empty bit assigned to each of the thread ordering queues.
+#define XSEM_REG_ORDER_EMPTY_SIZE                                                                            8
+#define XSEM_REG_ORDER_LL_REG_BB_K2                                                                          0x1400d80UL //Access:RW   DataWidth:0x5    // This array of registers provides read/write access to each entry of the linked-list array of the thread-ordering queue. Because the actual depth is based on the number of threads supported by the design, which is a Verilog parameter, a 64-entry window is reserved in the register address space. The valid entries start at the base of the window and extend through the number of threads supported. The value in each indirect register contains linked-list pointer to the next thread in the associated queue..
+#define XSEM_REG_ORDER_LL_REG_SIZE                                                                           24
+#define XSEM_REG_ORDER_POP_EN_BB_K2                                                                          0x1400e00UL //Access:RW   DataWidth:0x18   // Provides access to the thread ordering queue pop-enable vector.
+#define XSEM_REG_ORDER_WAKE_EN_BB_K2                                                                         0x1400e08UL //Access:RW   DataWidth:0x18   // Provides access to the thread ordering queue wake-enable vector.
+#define XSEM_REG_PF_NUM_ORDER_BASE_BB_K2                                                                     0x1400e10UL //Access:RW   DataWidth:0x3    // This field defines the base value for the ordering queue selection when the PFNum is chosen to control this selection. The value of this register is added to PFNum and the result is used to select one of 16 ordering queues.
+#define XSEM_REG_DBG_ALM_FULL                                                                                0x1401000UL //Access:RW   DataWidth:0x6    // Almost full for slow debug fifo.
+#define XSEM_REG_PASSIVE_ALM_FULL                                                                            0x1401004UL //Access:RW   DataWidth:0x5    // The number of free entries in the sync FIFO between the external HW and the passive buffer; below which the PassiveFull is asserted.
+#define XSEM_REG_SYNC_DRA_WR_ALM_FULL_BB_K2                                                                  0x1401008UL //Access:RW   DataWidth:0x5    // Almost full for sync dra_wr fifo (data from DRA to STORM).
+#define XSEM_REG_SYNC_RAM_WR_ALM_FULL                                                                        0x140100cUL //Access:RW   DataWidth:0x6    // Almost full for sync ram_wr fifo.
+#define XSEM_REG_SYNC_FOC_FIFO_WR_ALM_FULL_E5                                                                0x1401010UL //Access:RW   DataWidth:0x4    // Almost full for indication for FOC Sync FIFO.
+#define XSEM_REG_SYNC_SDM_READY_FIFO_WR_ALM_FULL_E5                                                          0x1401014UL //Access:RW   DataWidth:0x3    // Almost full for indication for SDM READY FIFO.
+#define XSEM_REG_SYNC_SDM_INC_FIFO_WR_ALM_FULL_E5                                                            0x1401018UL //Access:RW   DataWidth:0x3    // Almost full for indication for SDM Counter Increment FIFO.
+#define XSEM_REG_STALL_ON_INT_E5                                                                             0x140101cUL //Access:RW   DataWidth:0x2    // 00 - No stall. 01 - Both cluster Stroms will be stalled on any unmasked error occurrence. 10 - All Stroms will be stalled on any unmasked error occurrence.
+#define XSEM_REG_FIC0_A_MAX_THRDS_E5                                                                         0x1401020UL //Access:RW   DataWidth:0x6    // Defines the maximum supported threads that may be contained in FIC0 A queue. If FIC0 message  is received and number of threads equals to the configured value, FIC interface will be stalled untill number of queue threads drops below configured vlaue.
+#define XSEM_REG_FIC0_X_MAX_THRDS_E5                                                                         0x1401024UL //Access:RW   DataWidth:0x6    // Defines the maximum supported threads that may be contained in FIC0 X queue. If FIC0 message  is received and number of threads equals to the configured value, FIC interface will be stalled untill number of queue threads drops below configured vlaue.
+#define XSEM_REG_FIC0_B_MAX_THRDS_E5                                                                         0x1401028UL //Access:RW   DataWidth:0x6    // Defines the maximum supported threads that may be contained in FIC0 B queue. If FIC0 message  is received and number of threads equals to the configured value, FIC interface will be stalled untill number of queue threads drops below configured vlaue.
+#define XSEM_REG_FIC1_A_MAX_THRDS_E5                                                                         0x140102cUL //Access:RW   DataWidth:0x6    // Defines the maximum supported threads that may be contained in FIC1 A queue. If FIC1 message is received and number of threads equals to the configured value, FIC interface will be stalled untill number of queue threads drops below configured vlaue.
+#define XSEM_REG_DRA_EMPTY_BB_K2                                                                             0x1401100UL //Access:R    DataWidth:0x1    // Dra_empty.
+#define XSEM_REG_EXT_PAS_EMPTY                                                                               0x1401104UL //Access:R    DataWidth:0x1    // EXT_PAS FIFO empty in sem_slow.
+#define XSEM_REG_FIC_EMPTY                                                                                   0x1401120UL //Access:R    DataWidth:0x1    // Array of registers reflects associated FIC FIFO empty in sem_slow_fic.
+#define XSEM_REG_FIC_EMPTY_SIZE                                                                              2
+#define XSEM_REG_SLOW_DBG_EMPTY_BB_K2                                                                        0x1401140UL //Access:R    DataWidth:0x1    // DBG FIFO is empty in sem_slow_ls_dbg.
+#define XSEM_REG_SLOW_DRA_FIN_EMPTY_BB_K2                                                                    0x1401144UL //Access:R    DataWidth:0x1    // FIN fifo is empty in sem_slow_dra_sync.
+#define XSEM_REG_SLOW_DRA_RD_EMPTY_BB_K2                                                                     0x1401148UL //Access:R    DataWidth:0x1    // DRA_RD pop fifo is empty in sem_slow_dra_sync.
+#define XSEM_REG_SLOW_DRA_WR_EMPTY_BB_K2                                                                     0x140114cUL //Access:R    DataWidth:0x1    // DRA_WR push fifo is empty in sem_slow_dra_sync.
+#define XSEM_REG_SLOW_EXT_STORE_EMPTY                                                                        0x1401150UL //Access:R    DataWidth:0x1    // EXT_STORE FIFO is empty in sem_slow_ls_ext.
+#define XSEM_REG_SLOW_EXT_LOAD_EMPTY                                                                         0x1401154UL //Access:R    DataWidth:0x2    // EXT_LOAD FIFO is empty in sem_slow_ls_ext, bit 0 FIFO of Core A, bit 1 FIFO of Core B.
+#define XSEM_REG_SLOW_RAM_RD_EMPTY                                                                           0x1401158UL //Access:R    DataWidth:0x1    // EXT_RD_RAM FIFO is empty in sem_slow_ls_ext.
+#define XSEM_REG_SLOW_RAM_WR_EMPTY                                                                           0x140115cUL //Access:R    DataWidth:0x1    // EXT_WR_RAM FIFO is empty in sem_slow_ls_ext.
+#define XSEM_REG_SYNC_DBG_EMPTY                                                                              0x1401160UL //Access:R    DataWidth:0x2    // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR debug FIFO of Core B
+#define XSEM_REG_THREAD_FIFO_EMPTY_BB_K2                                                                     0x1401164UL //Access:R    DataWidth:0x1    // Indicates that the thread fifo is empty in sem_slow_dra_wr.
+#define XSEM_REG_ORD_ID_FIFO_EMPTY_BB_K2                                                                     0x1401168UL //Access:R    DataWidth:0x1    // Indicates that the order ID fifo is empty in sem_slow_dra_wr.
+#define XSEM_REG_PB_QUEUE_EMPTY_E5                                                                           0x140116cUL //Access:R    DataWidth:0xb    // If 1, the correspongding Queue is empty. Queues numeration: FOC_FIFO_IF - 0,  FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - 5,  WAKE_FIFO_PRIO_X - 6, WAKE_FIFO_PRI1_X - 7,FIC0_FIFO_B - 8, WAKE_FIFO_PRIO_B - 9,  WAKE_FIFO_PRI1_B - 10.
+#define XSEM_REG_SYNC_FOC_FIFO_EMPTY_E5                                                                      0x1401170UL //Access:R    DataWidth:0x1    // FOC FIFO empty indication.
+#define XSEM_REG_SYNC_FOC_PRE_FETCH_FIFO_EMPTY_E5                                                            0x1401174UL //Access:R    DataWidth:0x1    // FOC pre fetch FIFO empty indication.
+#define XSEM_REG_EXT_PAS_FULL                                                                                0x1401200UL //Access:R    DataWidth:0x1    // EXT_PAS FIFO Full in sem_slow.
+#define XSEM_REG_EXT_STORE_IF_FULL                                                                           0x1401204UL //Access:R    DataWidth:0x1    // EXT_STORE IF is full in sem_slow_ls_ext.
+#define XSEM_REG_FIC_FULL                                                                                    0x1401220UL //Access:R    DataWidth:0x1    // Array of registers reflects associated FIC FIFO full in sem_slow_fic.
+#define XSEM_REG_FIC_FULL_SIZE                                                                               2
+#define XSEM_REG_PAS_IF_FULL_BB_K2                                                                           0x1401240UL //Access:R    DataWidth:0x1    // Full from passive buffer asserted toward SDM.
+#define XSEM_REG_RAM_IF_FULL                                                                                 0x1401244UL //Access:R    DataWidth:0x1    // EXT_RAM IF is full in sem_slow_ls_ram.
+#define XSEM_REG_SLOW_DBG_ALM_FULL_BB_K2                                                                     0x1401248UL //Access:R    DataWidth:0x1    // DBG FIFO is almost full in sem_slow_ls_dbg according to the full threshold configuration.
+#define XSEM_REG_SLOW_DBG_FULL_BB_K2                                                                         0x140124cUL //Access:R    DataWidth:0x1    // DBG FIFO is full in sem_slow_ls_dbg.
+#define XSEM_REG_SLOW_DRA_FIN_FULL_BB_K2                                                                     0x1401250UL //Access:R    DataWidth:0x1    // FIN fifo is full in sem_slow_dra_sync (never may be active).
+#define XSEM_REG_SLOW_DRA_RD_FULL_BB_K2                                                                      0x1401254UL //Access:R    DataWidth:0x1    // DRA_RD pop fifo is full in sem_slow_dra_sync.
+#define XSEM_REG_SLOW_DRA_WR_FULL_BB_K2                                                                      0x1401258UL //Access:R    DataWidth:0x1    // DRA_WR push fifo is full in sem_slow_dra_sync.
+#define XSEM_REG_SLOW_EXT_STORE_FULL                                                                         0x140125cUL //Access:R    DataWidth:0x2    // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIFO.
+#define XSEM_REG_SLOW_EXT_LOAD_FULL                                                                          0x1401260UL //Access:R    DataWidth:0x2    // EXT_LOAD FIFO is full in sem_slow_ls_ext, bit 0 for Core A and bit 1 for Core B.
+#define XSEM_REG_SLOW_RAM_RD_FULL                                                                            0x1401264UL //Access:R    DataWidth:0x1    // EXT_RD_RAM FIFO is full in sem_slow_ls_ext.
+#define XSEM_REG_SLOW_RAM_WR_ALM_FULL                                                                        0x1401268UL //Access:R    DataWidth:0x1    // EXT_WR_RAM FIFO is almost full in sem_slow_ls_ext.
+#define XSEM_REG_SLOW_RAM_WR_FULL                                                                            0x140126cUL //Access:R    DataWidth:0x1    // EXT_WR_RAM FIFO is full in sem_slow_ls_ext.
+#define XSEM_REG_SYNC_DBG_FULL                                                                               0x1401270UL //Access:R    DataWidth:0x2    // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR debug FIFO of Core B.
+#define XSEM_REG_THREAD_FIFO_FULL_BB_K2                                                                      0x1401274UL //Access:R    DataWidth:0x1    // Indicates that the thread fifo is full in sem_slow_dra_wr.
+#define XSEM_REG_ORD_ID_FIFO_FULL_BB_K2                                                                      0x1401278UL //Access:R    DataWidth:0x1    // Indicates that the thread fifo is full in sem_slow_dra_wr.
+#define XSEM_REG_SYNC_READY_FIFO_FULL_E5                                                                     0x140127cUL //Access:R    DataWidth:0x1    // Ready sync FIFO full indication.
+#define XSEM_REG_SYNC_CNT_FIFO_FULL_E5                                                                       0x1401280UL //Access:R    DataWidth:0x1    // Counter increment sync FIFO full indication.
+#define XSEM_REG_SYNC_FOC_FIFO_FULL_E5                                                                       0x1401284UL //Access:R    DataWidth:0x1    // sync FOC FIFO full indication.
+#define XSEM_REG_THREAD_INTER_CNT_BB_K2                                                                      0x1401300UL //Access:RW   DataWidth:0x10   // Maximum value of threads interrupt counter; when it gets this value then interrupt to will be send if thread active from previous maximum value of this counter.
+#define XSEM_REG_THREAD_INTER_CNT_ENABLE_BB_K2                                                               0x1401304UL //Access:RW   DataWidth:0x1    // Enable for start count of thread_inter_cnt.
+#define XSEM_REG_THREAD_ORUN_NUM_BB_K2                                                                       0x1401308UL //Access:R    DataWidth:0x18   // Threads are sleeping in passive buffer more than thread_inter_cnt number of cycles.
+#define XSEM_REG_SLOW_DBG_ACTIVE_BB_K2                                                                       0x1401400UL //Access:RW   DataWidth:0x1    // Debug mode is active.
+#define XSEM_REG_SLOW_DBG_MODE_BB_K2                                                                         0x1401404UL //Access:RW   DataWidth:0x3    // Debug mode for slow debug bus.
+#define XSEM_REG_DBG_FRAME_MODE_BB_K2                                                                        0x1401408UL //Access:RW   DataWidth:0x2    // Debug frame mode control for the SEMI debug bus. The following values apply: "00" - indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mode-1, which means bits 127:64 belong to fast debug and bits 63:0 belong to slow debug. "10" - indicates mode-2, which means bits 127:96 belong to fast debug and bits 95:0 belong to slow debug. "11" - indicates mode-3, which means all four words are provided by the slow debug.
+#define XSEM_REG_DBG_EACH_CYLE_BB_K2                                                                         0x140140cUL //Access:RW   DataWidth:0x1    // 0=output every cycle; 1= output only when there is a change.
+#define XSEM_REG_DBG_GPRE_VECT_BB_K2                                                                         0x1401410UL //Access:RW   DataWidth:0x8    // This 8-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug channel when they are accessed for read by the Storm during mode-6 debug (handler trace). For this, bit-0 corresponds with GPRE[0-3] and bit-7 corresponds with GPRE[28-31].
+#define XSEM_REG_DBG_IF_FULL_BB_K2                                                                           0x1401414UL //Access:R    DataWidth:0x1    // DBG IF is full in sem_slow_ls_dbg.
+#define XSEM_REG_DBG_MODE0_CFG_BB_K2                                                                         0x1401418UL //Access:RW   DataWidth:0x1    // 0=all the message; 1=partial message.
+#define XSEM_REG_DBG_MODE0_CFG_CYCLE_BB_K2                                                                   0x140141cUL //Access:RW   DataWidth:0x5    // In case DebugMode0Config = 1; the additional cycles to extract to the debug bus.
+#define XSEM_REG_DBG_MODE1_CFG_BB_K2                                                                         0x1401420UL //Access:RW   DataWidth:0x1    // 0=without the data; 1=with the data.
+#define XSEM_REG_DBG_MSG_SRC_BB_K2                                                                           0x1401424UL //Access:RW   DataWidth:0x3    // This field is a mask used to enable (or filter) the various sources of DRA write debug packets. Setting a bit causes the corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1 and bit-2 corresponds with DRA writes from the passive buffer. This applicable only for debug mode=0.
+#define XSEM_REG_DBG_QUEUE_PEFORMANCE_MON_STAT_E5                                                            0x1401428UL //Access:RW   DataWidth:0x1    // If 0, the statistic report the maximum value between following reads (when using read clear). If 1, report the current value.
+#define XSEM_REG_PASSIVE_BUFFER_PERFORMANCE_MON_STAT_E5                                                      0x140142cUL //Access:RW   DataWidth:0x1    // Enable performance monitor statistics sent to SEM_PD.
+#define XSEM_REG_DBG_QUEUE_FIC_MON_CNT_E5                                                                    0x1401430UL //Access:RC   DataWidth:0x20   // Report the number of received FIC transaction between two of the following register reads. The counter is incremanted only for the event IDs which have Debug Monitor event indication set.
+#define XSEM_REG_DBG_QUEUE_FOC_MAX_VALUE_E5                                                                  0x1401434UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FOC queue.
+#define XSEM_REG_DBG_QUEUE_FIC0_A_MAX_VALUE_E5                                                               0x1401438UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 A queue.
+#define XSEM_REG_DBG_QUEUE_FIC1_A_MAX_VALUE_E5                                                               0x140143cUL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC1 A queue.
+#define XSEM_REG_DBG_QUEUE_PRIO0_A_MAX_VALUE_E5                                                              0x1401440UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 A queue.
+#define XSEM_REG_DBG_QUEUE_PRIO1_A_MAX_VALUE_E5                                                              0x1401444UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 A queue.
+#define XSEM_REG_DBG_QUEUE_FIC0_X_MAX_VALUE_E5                                                               0x1401448UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 X queue.
+#define XSEM_REG_DBG_QUEUE_PRIO0_X_MAX_VALUE_E5                                                              0x140144cUL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 X queue.
+#define XSEM_REG_DBG_QUEUE_PRIO1_X_MAX_VALUE_E5                                                              0x1401450UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 X queue.
+#define XSEM_REG_DBG_QUEUE_FIC0_B_MAX_VALUE_E5                                                               0x1401454UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 B queue.
+#define XSEM_REG_DBG_QUEUE_PRIO0_B_MAX_VALUE_E5                                                              0x1401458UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 B queue.
+#define XSEM_REG_DBG_QUEUE_PRIO1_B_MAX_VALUE_E5                                                              0x140145cUL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 B queue.
+#define XSEM_REG_DBG_QUEUE_MAX_THREAD_VALUE_E5                                                               0x1401460UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of allocated threads in the system.
+#define XSEM_REG_DBG_QUEUE_MAX_SLEEP_VALUE_E5                                                                0x1401464UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does not include the threads pending in the queues.
+#define XSEM_REG_DBG_OUT_DATA                                                                                0x1401500UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define XSEM_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define XSEM_REG_DBG_OUT_VALID                                                                               0x1401520UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define XSEM_REG_DBG_OUT_FRAME                                                                               0x1401524UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define XSEM_REG_DBG_SELECT                                                                                  0x1401528UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define XSEM_REG_DBG_DWORD_ENABLE                                                                            0x140152cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define XSEM_REG_DBG_SHIFT                                                                                   0x1401530UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define XSEM_REG_DBG_FORCE_VALID                                                                             0x1401534UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define XSEM_REG_DBG_FORCE_FRAME                                                                             0x1401538UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define XSEM_REG_EXT_PAS_FIFO_BB_K2                                                                          0x1408000UL //Access:WB_R DataWidth:0x4d   // Provides read-only access of the external passive FIFO. Intended for debug purposes.
+#define XSEM_REG_EXT_PAS_FIFO_SIZE                                                                           76
+#define XSEM_REG_INT_TABLE                                                                                   0x1410000UL //Access:RW   DataWidth:0x1e   // Interrupt table read/write access. This register is intended to be written only when the system is idle. The fields of the interrupt table are as follows. int_table[29] = Allocated per child;  int_table[28] = Increment type; int_table[27:23] = Counter select; int_table[22] = Counter insert; int_table[21:17] = GapSel; int_table[16] = Monitor enable; int_table[15:0] = PRAM Address;
+#define XSEM_REG_INT_TABLE_SIZE                                                                              256
+#define XSEM_REG_FIC_COUNTER_GROUP_E5                                                                        0x1411000UL //Access:RW   DataWidth:0x8    // This field enables a RD/WR access to the 24 counters of the "FIC Counters".
+#define XSEM_REG_FIC_COUNTER_GROUP_SIZE                                                                      24
+#define XSEM_REG_PB_THRD_STM_GROUP_E5                                                                        0x1412000UL //Access:R    DataWidth:0x17   // Read the State mahcine state of teh trheads. 0:4 - state. 5 - pending ready. 7:6 - Affinity type. 8 - Destination FOC. 9 - Destination Storm. 10 - counter increment ready. 15:11 - counter index. 16 - Debug monitor enable. 17 - Exlucsive. 22:18 - DRA size.
+#define XSEM_REG_PB_THRD_STM_GROUP_SIZE                                                                      56
+#define XSEM_REG_PASSIVE_BUFFER                                                                              0x1420000UL //Access:R    DataWidth:0x20   // Passive buffer memory read only.
+#define XSEM_REG_PASSIVE_BUFFER_SIZE_BB_K2                                                                   4320
+#define XSEM_REG_PASSIVE_BUFFER_SIZE_E5                                                                      12544
+#define XSEM_REG_FIC_GAP_VECT_BB_K2                                                                          0x1400500UL //Access:WB   DataWidth:0x2c   // This array of nine 44-bit vectors provides a bit per register-quad, used to define the register-quad locations that should be included in gaps (discontinuities) within the DRA transfer, where bit-0 corresponds with IORs 0-3, and so on. To indicate a gap, the corresponding bit should be cleared. These gaps have a granularity of a register- quad (four IORs). For each DRA write transfer from whom the FIC is the source, one of nine gap vectors (or a default-gap vector) will be selected, based on the GapSelect field of the corresponding interrupt table entry. Any unused upper bits of the vector will be ignored and thus, can be written with any value.
+#define XSEM_REG_FIC_GAP_VECT_E5                                                                             0x1430000UL //Access:WB   DataWidth:0x34   // This array of 24 x 52-bit vectors provides a bit per register-quad, used to define the register-quad locations that should be included in gaps (discontinuities) within the DRA transfer, where bit-0 corresponds with IORs 0-3, and so on. To indicate a gap, the corresponding bit should be cleared. These gaps have a granularity of a register- quad (four IORs). For each DRA write transfer from whom the FIC is the source, one of nine gap vectors (or a default-gap vector) will be selected, based on the GapSelect field of the corresponding interrupt table entry. Any unused upper bits of the vector will be ignored and thus, can be written with any value.
+#define XSEM_REG_FIC_GAP_VECT_SIZE_BB_K2                                                                     18
+#define XSEM_REG_FIC_GAP_VECT_SIZE_E5                                                                        48
+#define XSEM_REG_FAST_MEMORY                                                                                 0x1440000UL //Access:RW   DataWidth:0x20   // See sem_fast.xls for its description.
+#define XSEM_REG_FAST_MEMORY_SIZE                                                                            65536
+#define XSEM_REG_PRAM                                                                                        0x1480000UL //Access:WB   DataWidth:0x30   // Pram memory.
+#define XSEM_REG_PRAM_SIZE_BB_K2                                                                             73728
+#define XSEM_REG_PRAM_SIZE_E5                                                                                92160
+#define YSEM_REG_ENABLE_IN_BB_K2                                                                             0x1500004UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define YSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN_BB_K2                                                        (0x1<<0) // Full input from external IF to LS input enable.
+  #define YSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN_BB_K2_SHIFT                                                  0
+  #define YSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN_BB_K2                                                     (0x1<<1) // Read data from external LS IF input enable.
+  #define YSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN_BB_K2_SHIFT                                               1
+  #define YSEM_REG_ENABLE_IN_FIC_ENABLE_IN_BB_K2                                                             (0x1<<2) // FIC input enable bit used to enable/disable messages from being received on all FIC interfaces.
+  #define YSEM_REG_ENABLE_IN_FIC_ENABLE_IN_BB_K2_SHIFT                                                       2
+  #define YSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN_BB_K2                                                         (0x1<<3) // FOC acknowledge input enable bit used to enable/disable acknowledge response from being received on any of the FOC interfaces.
+  #define YSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN_BB_K2_SHIFT                                                   3
+  #define YSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN_BB_K2                                                         (0x1<<4) // General interface input enable.
+  #define YSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN_BB_K2_SHIFT                                                   4
+  #define YSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN_BB_K2                                                         (0x1<<5) // External passive write input enable.
+  #define YSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN_BB_K2_SHIFT                                                   5
+  #define YSEM_REG_ENABLE_IN_RAM_ENABLE_IN_BB_K2                                                             (0x1<<6) // Data input enable to RAM.
+  #define YSEM_REG_ENABLE_IN_RAM_ENABLE_IN_BB_K2_SHIFT                                                       6
+  #define YSEM_REG_ENABLE_IN_STALL_ENABLE_IN_BB_K2                                                           (0x1<<7) // Enable for stall input from all external STORM instances.
+  #define YSEM_REG_ENABLE_IN_STALL_ENABLE_IN_BB_K2_SHIFT                                                     7
+  #define YSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN_BB_K2                                                      (0x1<<8) // Thread ready bus input enable.
+  #define YSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN_BB_K2_SHIFT                                                8
+  #define YSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN_BB_K2                                                      (0x1<<9) // Input enable for VF error indication from SDM to SEMI.
+  #define YSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN_BB_K2_SHIFT                                                9
+#define YSEM_REG_ENABLE_OUT_BB_K2                                                                            0x1500008UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define YSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT_BB_K2                                                    (0x1<<0) // Read request output enable from external LS IF.
+  #define YSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT_BB_K2_SHIFT                                              0
+  #define YSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT_BB_K2                                                    (0x1<<1) // Write request output enable from external LS IF.
+  #define YSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT_BB_K2_SHIFT                                              1
+  #define YSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT_BB_K2                                                           (0x1<<2) // FOC output otuput enable bit used to enable/disable messages from being sent out on any of the FOC interfaces.
+  #define YSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT_BB_K2_SHIFT                                                     2
+  #define YSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT_BB_K2                                                       (0x1<<3) // Passive full output enable.
+  #define YSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT_BB_K2_SHIFT                                                 3
+  #define YSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT_BB_K2                                                           (0x1<<4) // Data output enable to RAM.
+  #define YSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT_BB_K2_SHIFT                                                     4
+  #define YSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT_BB_K2                                                         (0x1<<5) // Stall output enable bit used to enable/disable the output stall signal toward all external Storm instances.
+  #define YSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT_BB_K2_SHIFT                                                   5
+#define YSEM_REG_FIC_DISABLE_BB_K2                                                                           0x150000cUL //Access:RW   DataWidth:0x1    // Disables input messages from all FIC interfaces.  May be updated during run_time by the microcode.
+#define YSEM_REG_PAS_DISABLE_BB_K2                                                                           0x1500010UL //Access:RW   DataWidth:0x1    // Disables input messages from the passive buffer  May be updated during run_time by the microcode.
+#define YSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_E5                                                         0x1500014UL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define YSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_FIC_WEIGHT_E5                                   (0xf<<0) // Passive Buffer write WRR weight value for FIC source.
+  #define YSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_FIC_WEIGHT_E5_SHIFT                             0
+  #define YSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_A_WEIGHT_E5                                 (0xf<<4) // Passive Buffer write WRR weight value for DRA RD A source.
+  #define YSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_A_WEIGHT_E5_SHIFT                           4
+  #define YSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_B_WEIGHT_E5                                 (0xf<<8) // Passive Buffer write WRR weight value for DRA RD B source.
+  #define YSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_B_WEIGHT_E5_SHIFT                           8
+  #define YSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_SDM_WEIGHT_E5                                   (0xf<<12) // Passive Buffer write WRR weight value for SDM source.
+  #define YSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_SDM_WEIGHT_E5_SHIFT                             12
+  #define YSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_EMPTY_CNT_E5                                    (0xf<<16) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define YSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_EMPTY_CNT_E5_SHIFT                              16
+  #define YSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_STRICT_SRC_E5                                      (0x7<<20) // This register defines if one of the source of the PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B, 100 - SDM.
+  #define YSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_STRICT_SRC_E5_SHIFT                                20
+#define YSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_E5                                                          0x1500018UL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define YSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_FOC_WEIGHT_E5                                    (0xf<<0) // Passive Buffer WRR weight value for FOC source.
+  #define YSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_FOC_WEIGHT_E5_SHIFT                              0
+  #define YSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_A_WEIGHT_E5                                  (0xf<<4) // Passive Buffer write WRR weight value for DRA WR A source.
+  #define YSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_A_WEIGHT_E5_SHIFT                            4
+  #define YSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_B_WEIGHT_E5                                  (0xf<<8) // Passive Buffer write WRR weight value for DRA WR B source.
+  #define YSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_B_WEIGHT_E5_SHIFT                            8
+  #define YSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_GRC_WEIGHT_E5                                    (0xf<<12) // Passive Buffer write WRR weight value for GRC source.
+  #define YSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_GRC_WEIGHT_E5_SHIFT                              12
+  #define YSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_EMPTY_CNT_E5                                     (0xf<<16) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define YSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_EMPTY_CNT_E5_SHIFT                               16
+  #define YSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_STRICT_SRC_E5                                       (0x7<<20) // This register defines if one of the source of the PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B, 100 - GRC.
+  #define YSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_STRICT_SRC_E5_SHIFT                                 20
+#define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_E5                                                            0x150001cUL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_FIC0_A_WEIGHT_E5                             (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_FIC0_A_WEIGHT_E5_SHIFT                       0
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_FIC1_A_WEIGHT_E5                             (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_FIC1_A_WEIGHT_E5_SHIFT                       4
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO0_A_WEIGHT_E5                            (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO0_A_WEIGHT_E5_SHIFT                      8
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO1_A_WEIGHT_E5                            (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO1_A_WEIGHT_E5_SHIFT                      12
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_EMPTY_CNT_E5                                 (0xf<<16) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_EMPTY_CNT_E5_SHIFT                           16
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_STRICT_SRC_E5                                   (0x7<<20) // This register defines if one of the source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - FIC1.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_STRICT_SRC_E5_SHIFT                             20
+#define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_E5                                                            0x1500020UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_FIC0_X_WEIGHT_E5                             (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_FIC0_X_WEIGHT_E5_SHIFT                       0
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO0_X_WEIGHT_E5                            (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO0_X_WEIGHT_E5_SHIFT                      4
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO1_X_WEIGHT_E5                            (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO1_X_WEIGHT_E5_SHIFT                      8
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_EMPTY_CNT_E5                                 (0xf<<12) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_EMPTY_CNT_E5_SHIFT                           12
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_STRICT_SRC_E5                                   (0x3<<16) // This register defines if one of the source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_STRICT_SRC_E5_SHIFT                             16
+#define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_E5                                                            0x1500024UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_FIC0_B_WEIGHT_E5                             (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_FIC0_B_WEIGHT_E5_SHIFT                       0
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO0_B_WEIGHT_E5                            (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO0_B_WEIGHT_E5_SHIFT                      4
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO1_B_WEIGHT_E5                            (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO1_B_WEIGHT_E5_SHIFT                      8
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_EMPTY_CNT_E5                                 (0xf<<12) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_EMPTY_CNT_E5_SHIFT                           12
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_STRICT_SRC_E5                                   (0x3<<16) // This register defines if one of the source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_STRICT_SRC_E5_SHIFT                             16
+#define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_E5                                                            0x1500028UL //Access:RW   DataWidth:0xe    // Multi Field Register.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_AFFIN_A_WEIGHT_E5                            (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for Affinity A source.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_AFFIN_A_WEIGHT_E5_SHIFT                      0
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_AFFIN_X_WEIGHT_E5                            (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for Affinity X source.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_AFFIN_X_WEIGHT_E5_SHIFT                      4
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_EMPTY_CNT_E5                                 (0xf<<8) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_EMPTY_CNT_E5_SHIFT                           8
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_STRICT_SRC_E5                                   (0x3<<12) // This register defines if one of the source of the PB WR arbiter should have strict priority: 0 - None, 1 - AFFINITY A, 2- AFFINITY X.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_STRICT_SRC_E5_SHIFT                             12
+#define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_E5                                                            0x150002cUL //Access:RW   DataWidth:0xc    // Multi Field Register.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_AFFIN_B_WEIGHT_E5                            (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for Affinity B source.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_AFFIN_B_WEIGHT_E5_SHIFT                      0
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_AFFIN_X_WEIGHT_E5                            (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for Affinity X source.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_AFFIN_X_WEIGHT_E5_SHIFT                      4
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_EMPTY_CNT_E5                                 (0xf<<8) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define YSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_EMPTY_CNT_E5_SHIFT                           8
+#define YSEM_REG_PASSIVE_BUFFER_DRA_WR_E5                                                                    0x1500030UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define YSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_A_E5                                                   (0x1<<0) // Enable DRA Write to transactions towards the SEM_PD Core A.
+  #define YSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_A_E5_SHIFT                                             0
+  #define YSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_B_E5                                                   (0x1<<1) // Enable DRA Write to transactions towards the SEM_PD Core B.
+  #define YSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_B_E5_SHIFT                                             1
+  #define YSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_PEND_BLOCK_EN_E5                                          (0x1<<2) // When set, there may only be a single thread pending to run for each storm.
+  #define YSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_PEND_BLOCK_EN_E5_SHIFT                                    2
+  #define YSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_AFFINITY_CORE_A_ONLY_E5                                          (0x1<<3) // When set, the Affintiy field of the thread is set to CoreA (regardless to the Afficnity received from CM).
+  #define YSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_AFFINITY_CORE_A_ONLY_E5_SHIFT                                    3
+#define YSEM_REG_INT_STS_0                                                                                   0x1500040UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define YSEM_REG_INT_STS_0_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define YSEM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                             0
+  #define YSEM_REG_INT_STS_0_FIC_LAST_ERROR                                                                  (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
+  #define YSEM_REG_INT_STS_0_FIC_LAST_ERROR_SHIFT                                                            1
+  #define YSEM_REG_INT_STS_0_FIC_LENGTH_ERROR                                                                (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
+  #define YSEM_REG_INT_STS_0_FIC_LENGTH_ERROR_SHIFT                                                          2
+  #define YSEM_REG_INT_STS_0_FIC_FIFO_ERROR                                                                  (0x1<<3) // Error in any one of the FIC FIFO is active.
+  #define YSEM_REG_INT_STS_0_FIC_FIFO_ERROR_SHIFT                                                            3
+  #define YSEM_REG_INT_STS_0_DRA_RD_A_LAST_ERROR_E5                                                          (0x1<<4) // DRA_RD_A last indication was unexpectedly received or was not received at expected time.
+  #define YSEM_REG_INT_STS_0_DRA_RD_A_LAST_ERROR_E5_SHIFT                                                    4
+  #define YSEM_REG_INT_STS_0_DRA_RD_B_LAST_ERROR_E5                                                          (0x1<<5) // DRA_RD_B last indication was unexpectedly received or was not received at expected time.
+  #define YSEM_REG_INT_STS_0_DRA_RD_B_LAST_ERROR_E5_SHIFT                                                    5
+  #define YSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_A_E5                                                   (0x1<<6) // Error in external store slow sync FIFO pop logic of Storm A.
+  #define YSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_A_E5_SHIFT                                             6
+  #define YSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_B_E5                                                   (0x1<<7) // Error in external store slow sync FIFO pop logic of Storm B.
+  #define YSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT                                             7
+  #define YSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5                                                   (0x1<<8) // Error in external load sync slow FIFO push logic.
+  #define YSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT                                             8
+  #define YSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5                                                   (0x1<<9) // Error in external load sync slow FIFO pop logic.
+  #define YSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5_SHIFT                                             9
+  #define YSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2                                                    (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
+  #define YSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2_SHIFT                                              22
+  #define YSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_E5                                                       (0x1<<10) // Error in slow LS_SYNC_PUSH FIFO.
+  #define YSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_E5_SHIFT                                                 10
+  #define YSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_BB_K2                                                     (0x1<<23) // Error in LS_SYNC_POP FIFO.
+  #define YSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_BB_K2_SHIFT                                               23
+  #define YSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_E5                                                        (0x1<<11) // Error in slow LS_SYNC_POP FIFO.
+  #define YSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_E5_SHIFT                                                  11
+  #define YSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2                                                    (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
+  #define YSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2_SHIFT                                              25
+  #define YSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_E5                                                       (0x1<<12) // Error in slow LS_SYNC_PUSH FIFO.
+  #define YSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_E5_SHIFT                                                 12
+  #define YSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_A_E5                                                         (0x1<<13) // Error in slow LS_SYNC_PUSH FIFO.
+  #define YSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_A_E5_SHIFT                                                   13
+  #define YSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_B_E5                                                         (0x1<<14) // Error in slow LS_SYNC_POP FIFO.
+  #define YSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_B_E5_SHIFT                                                   14
+  #define YSEM_REG_INT_STS_0_DBG_FIFO_ERROR_BB_K2                                                            (0x1<<28) // Error in slow debug fifo.
+  #define YSEM_REG_INT_STS_0_DBG_FIFO_ERROR_BB_K2_SHIFT                                                      28
+  #define YSEM_REG_INT_STS_0_DBG_FIFO_ERROR_E5                                                               (0x1<<15) // Error in slow debug fifo
+  #define YSEM_REG_INT_STS_0_DBG_FIFO_ERROR_E5_SHIFT                                                         15
+  #define YSEM_REG_INT_STS_0_EXT_THREAD_OOR_ERROR_E5                                                         (0x1<<16) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define YSEM_REG_INT_STS_0_EXT_THREAD_OOR_ERROR_E5_SHIFT                                                   16
+  #define YSEM_REG_INT_STS_0_EXT_STORE_TAG_ODER_ERROR_E5                                                     (0x1<<17) // Error detected in the ext Stroe interface internal TAG order ID.
+  #define YSEM_REG_INT_STS_0_EXT_STORE_TAG_ODER_ERROR_E5_SHIFT                                               17
+  #define YSEM_REG_INT_STS_0_FIC1_AFFINITY_FIELD_ERROR_E5                                                    (0x1<<18) // Indicates that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
+  #define YSEM_REG_INT_STS_0_FIC1_AFFINITY_FIELD_ERROR_E5_SHIFT                                              18
+  #define YSEM_REG_INT_STS_0_EXT_LD_LEN_ERROR_E5                                                             (0x1<<19) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define YSEM_REG_INT_STS_0_EXT_LD_LEN_ERROR_E5_SHIFT                                                       19
+  #define YSEM_REG_INT_STS_0_PB_QUE_ARB_THRD_RDY_ERROR_E5                                                    (0x1<<20) // Indicates that Passive Buffer State machine has unexpectedly received a ready indication in the following cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pending FOC" or "Ready FOC" state. b. Pending Ready indication is already asserted.
+  #define YSEM_REG_INT_STS_0_PB_QUE_ARB_THRD_RDY_ERROR_E5_SHIFT                                              20
+  #define YSEM_REG_INT_STS_0_SYNC_FOC_FIFO_ERROR_E5                                                          (0x1<<21) // Error indication on FOC sync FIFO.
+  #define YSEM_REG_INT_STS_0_SYNC_FOC_FIFO_ERROR_E5_SHIFT                                                    21
+  #define YSEM_REG_INT_STS_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                      (0x1<<22) // The error indicates on an error of one the threads READY queues.
+  #define YSEM_REG_INT_STS_0_PB_QUE_ARB_QUEUES_ERROR_E5_SHIFT                                                22
+  #define YSEM_REG_INT_STS_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5                                                (0x1<<23) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define YSEM_REG_INT_STS_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5_SHIFT                                          23
+  #define YSEM_REG_INT_STS_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5                                                (0x1<<24) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define YSEM_REG_INT_STS_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5_SHIFT                                          24
+  #define YSEM_REG_INT_STS_0_CREDIT_ERROR_FOC0_E5                                                            (0x1<<25) // FOC0 is out of credit.
+  #define YSEM_REG_INT_STS_0_CREDIT_ERROR_FOC0_E5_SHIFT                                                      25
+  #define YSEM_REG_INT_STS_0_CREDIT_ERROR_FOC1_E5                                                            (0x1<<26) // FOC1 is out of credit.
+  #define YSEM_REG_INT_STS_0_CREDIT_ERROR_FOC1_E5_SHIFT                                                      26
+  #define YSEM_REG_INT_STS_0_CREDIT_ERROR_FOC2_E5                                                            (0x1<<27) // FOC2 is out of credit.
+  #define YSEM_REG_INT_STS_0_CREDIT_ERROR_FOC2_E5_SHIFT                                                      27
+  #define YSEM_REG_INT_STS_0_CREDIT_ERROR_FOC3_E5                                                            (0x1<<28) // FOC3 is out of credit.
+  #define YSEM_REG_INT_STS_0_CREDIT_ERROR_FOC3_E5_SHIFT                                                      28
+  #define YSEM_REG_INT_STS_0_CREDIT_ERROR_FOC4_E5                                                            (0x1<<29) // FOC4 is out of credit.
+  #define YSEM_REG_INT_STS_0_CREDIT_ERROR_FOC4_E5_SHIFT                                                      29
+  #define YSEM_REG_INT_STS_0_CREDIT_ERROR_FOC5_E5                                                            (0x1<<30) // FOC5 is out of credit.
+  #define YSEM_REG_INT_STS_0_CREDIT_ERROR_FOC5_E5_SHIFT                                                      30
+  #define YSEM_REG_INT_STS_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                     (0x1<<31) // Error indication of foc pre_fetch fifo.
+  #define YSEM_REG_INT_STS_0_FOC_PRE_FETCH_FIFO_ERROR_E5_SHIFT                                               31
+  #define YSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR_BB_K2                                                        (0x1<<4) // Error in Ext PAS_FIFO is active.
+  #define YSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR_BB_K2_SHIFT                                                  4
+  #define YSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR_BB_K2                                                        (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
+  #define YSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR_BB_K2_SHIFT                                                  5
+  #define YSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2                                                    (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
+  #define YSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2_SHIFT                                              6
+  #define YSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR_BB_K2                                                     (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
+  #define YSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT                                               7
+  #define YSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2                                                    (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
+  #define YSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT                                              8
+  #define YSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR_BB_K2                                                     (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
+  #define YSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR_BB_K2_SHIFT                                               9
+  #define YSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR_BB_K2                                                       (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
+  #define YSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR_BB_K2_SHIFT                                                 10
+  #define YSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR_BB_K2                                                    (0x1<<11) // Signals an unknown address in the fast-memory window.
+  #define YSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR_BB_K2_SHIFT                                              11
+  #define YSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO_BB_K2                                                          (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
+  #define YSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO_BB_K2_SHIFT                                                    12
+  #define YSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO_BB_K2                                                          (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
+  #define YSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO_BB_K2_SHIFT                                                    13
+  #define YSEM_REG_INT_STS_0_CAM_OUT_FIFO_BB_K2                                                              (0x1<<14) // Error in CAM_OUT fifo in cam block.
+  #define YSEM_REG_INT_STS_0_CAM_OUT_FIFO_BB_K2_SHIFT                                                        14
+  #define YSEM_REG_INT_STS_0_FIN_FIFO_BB_K2                                                                  (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
+  #define YSEM_REG_INT_STS_0_FIN_FIFO_BB_K2_SHIFT                                                            15
+  #define YSEM_REG_INT_STS_0_THREAD_FIFO_ERROR_BB_K2                                                         (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
+  #define YSEM_REG_INT_STS_0_THREAD_FIFO_ERROR_BB_K2_SHIFT                                                   16
+  #define YSEM_REG_INT_STS_0_THREAD_OVERRUN_BB_K2                                                            (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
+  #define YSEM_REG_INT_STS_0_THREAD_OVERRUN_BB_K2_SHIFT                                                      17
+  #define YSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2                                                 (0x1<<18) // Error in external store sync FIFO push logic.
+  #define YSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2_SHIFT                                           18
+  #define YSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_BB_K2                                                  (0x1<<19) // Error in external store sync FIFO pop logic.
+  #define YSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_BB_K2_SHIFT                                            19
+  #define YSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2                                                  (0x1<<20) // Error in external load sync FIFO push logic.
+  #define YSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2_SHIFT                                            20
+  #define YSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2                                                   (0x1<<21) // Error in external load sync FIFO pop logic.
+  #define YSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2_SHIFT                                             21
+  #define YSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR_BB_K2                                                     (0x1<<24) // Error in LS_SYNC_POP FIFO.
+  #define YSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR_BB_K2_SHIFT                                               24
+  #define YSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR_BB_K2                                                       (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
+  #define YSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR_BB_K2_SHIFT                                                 26
+  #define YSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_BB_K2                                                        (0x1<<27) // Error in LS_SYNC_POP FIFO.
+  #define YSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_BB_K2_SHIFT                                                  27
+  #define YSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO_BB_K2                                                         (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
+  #define YSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO_BB_K2_SHIFT                                                   29
+  #define YSEM_REG_INT_STS_0_VFC_INTERRUPT_BB_K2                                                             (0x1<<30) // Error interrupt in VFC block.
+  #define YSEM_REG_INT_STS_0_VFC_INTERRUPT_BB_K2_SHIFT                                                       30
+  #define YSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR_BB_K2                                                        (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
+  #define YSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR_BB_K2_SHIFT                                                  31
+#define YSEM_REG_INT_MASK_0                                                                                  0x1500044UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define YSEM_REG_INT_MASK_0_ADDRESS_ERROR                                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.ADDRESS_ERROR .
+  #define YSEM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                            0
+  #define YSEM_REG_INT_MASK_0_FIC_LAST_ERROR                                                                 (0x1<<1) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.FIC_LAST_ERROR .
+  #define YSEM_REG_INT_MASK_0_FIC_LAST_ERROR_SHIFT                                                           1
+  #define YSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR                                                               (0x1<<2) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.FIC_LENGTH_ERROR .
+  #define YSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR_SHIFT                                                         2
+  #define YSEM_REG_INT_MASK_0_FIC_FIFO_ERROR                                                                 (0x1<<3) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.FIC_FIFO_ERROR .
+  #define YSEM_REG_INT_MASK_0_FIC_FIFO_ERROR_SHIFT                                                           3
+  #define YSEM_REG_INT_MASK_0_DRA_RD_A_LAST_ERROR_E5                                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.DRA_RD_A_LAST_ERROR .
+  #define YSEM_REG_INT_MASK_0_DRA_RD_A_LAST_ERROR_E5_SHIFT                                                   4
+  #define YSEM_REG_INT_MASK_0_DRA_RD_B_LAST_ERROR_E5                                                         (0x1<<5) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.DRA_RD_B_LAST_ERROR .
+  #define YSEM_REG_INT_MASK_0_DRA_RD_B_LAST_ERROR_E5_SHIFT                                                   5
+  #define YSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_A_E5                                                  (0x1<<6) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR_A .
+  #define YSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_A_E5_SHIFT                                            6
+  #define YSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_B_E5                                                  (0x1<<7) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR_B .
+  #define YSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT                                            7
+  #define YSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5                                                  (0x1<<8) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR_A .
+  #define YSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT                                            8
+  #define YSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5                                                  (0x1<<9) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR_B .
+  #define YSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5_SHIFT                                            9
+  #define YSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2                                                   (0x1<<22) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_RAM_RD_PUSH_ERROR .
+  #define YSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2_SHIFT                                             22
+  #define YSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_E5                                                      (0x1<<10) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_RAM_RD_PUSH_ERROR .
+  #define YSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_E5_SHIFT                                                10
+  #define YSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_BB_K2                                                    (0x1<<23) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_RAM_RD_POP_ERROR .
+  #define YSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_BB_K2_SHIFT                                              23
+  #define YSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_E5                                                       (0x1<<11) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_RAM_RD_POP_ERROR .
+  #define YSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_E5_SHIFT                                                 11
+  #define YSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2                                                   (0x1<<25) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_RAM_WR_PUSH_ERROR .
+  #define YSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2_SHIFT                                             25
+  #define YSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_E5                                                      (0x1<<12) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_RAM_WR_PUSH_ERROR .
+  #define YSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_E5_SHIFT                                                12
+  #define YSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_A_E5                                                        (0x1<<13) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR_A .
+  #define YSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_A_E5_SHIFT                                                  13
+  #define YSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_B_E5                                                        (0x1<<14) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR_B .
+  #define YSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_B_E5_SHIFT                                                  14
+  #define YSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_BB_K2                                                           (0x1<<28) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.DBG_FIFO_ERROR .
+  #define YSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_BB_K2_SHIFT                                                     28
+  #define YSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_E5                                                              (0x1<<15) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.DBG_FIFO_ERROR .
+  #define YSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_E5_SHIFT                                                        15
+  #define YSEM_REG_INT_MASK_0_EXT_THREAD_OOR_ERROR_E5                                                        (0x1<<16) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.EXT_THREAD_OOR_ERROR .
+  #define YSEM_REG_INT_MASK_0_EXT_THREAD_OOR_ERROR_E5_SHIFT                                                  16
+  #define YSEM_REG_INT_MASK_0_EXT_STORE_TAG_ODER_ERROR_E5                                                    (0x1<<17) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.EXT_STORE_TAG_ODER_ERROR .
+  #define YSEM_REG_INT_MASK_0_EXT_STORE_TAG_ODER_ERROR_E5_SHIFT                                              17
+  #define YSEM_REG_INT_MASK_0_FIC1_AFFINITY_FIELD_ERROR_E5                                                   (0x1<<18) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.FIC1_AFFINITY_FIELD_ERROR .
+  #define YSEM_REG_INT_MASK_0_FIC1_AFFINITY_FIELD_ERROR_E5_SHIFT                                             18
+  #define YSEM_REG_INT_MASK_0_EXT_LD_LEN_ERROR_E5                                                            (0x1<<19) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.EXT_LD_LEN_ERROR .
+  #define YSEM_REG_INT_MASK_0_EXT_LD_LEN_ERROR_E5_SHIFT                                                      19
+  #define YSEM_REG_INT_MASK_0_PB_QUE_ARB_THRD_RDY_ERROR_E5                                                   (0x1<<20) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.PB_QUE_ARB_THRD_RDY_ERROR .
+  #define YSEM_REG_INT_MASK_0_PB_QUE_ARB_THRD_RDY_ERROR_E5_SHIFT                                             20
+  #define YSEM_REG_INT_MASK_0_SYNC_FOC_FIFO_ERROR_E5                                                         (0x1<<21) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_FOC_FIFO_ERROR .
+  #define YSEM_REG_INT_MASK_0_SYNC_FOC_FIFO_ERROR_E5_SHIFT                                                   21
+  #define YSEM_REG_INT_MASK_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                     (0x1<<22) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.PB_QUE_ARB_QUEUES_ERROR .
+  #define YSEM_REG_INT_MASK_0_PB_QUE_ARB_QUEUES_ERROR_E5_SHIFT                                               22
+  #define YSEM_REG_INT_MASK_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5                                               (0x1<<23) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.STORM_MOVRIND_USES_BAR_ATTN_A .
+  #define YSEM_REG_INT_MASK_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5_SHIFT                                         23
+  #define YSEM_REG_INT_MASK_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5                                               (0x1<<24) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.STORM_MOVRIND_USES_BAR_ATTN_B .
+  #define YSEM_REG_INT_MASK_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5_SHIFT                                         24
+  #define YSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC0_E5                                                           (0x1<<25) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.CREDIT_ERROR_FOC0 .
+  #define YSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC0_E5_SHIFT                                                     25
+  #define YSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC1_E5                                                           (0x1<<26) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.CREDIT_ERROR_FOC1 .
+  #define YSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC1_E5_SHIFT                                                     26
+  #define YSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC2_E5                                                           (0x1<<27) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.CREDIT_ERROR_FOC2 .
+  #define YSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC2_E5_SHIFT                                                     27
+  #define YSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC3_E5                                                           (0x1<<28) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.CREDIT_ERROR_FOC3 .
+  #define YSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC3_E5_SHIFT                                                     28
+  #define YSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC4_E5                                                           (0x1<<29) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.CREDIT_ERROR_FOC4 .
+  #define YSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC4_E5_SHIFT                                                     29
+  #define YSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC5_E5                                                           (0x1<<30) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.CREDIT_ERROR_FOC5 .
+  #define YSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC5_E5_SHIFT                                                     30
+  #define YSEM_REG_INT_MASK_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                    (0x1<<31) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.FOC_PRE_FETCH_FIFO_ERROR .
+  #define YSEM_REG_INT_MASK_0_FOC_PRE_FETCH_FIFO_ERROR_E5_SHIFT                                              31
+  #define YSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR_BB_K2                                                       (0x1<<4) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.PAS_BUF_FIFO_ERROR .
+  #define YSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR_BB_K2_SHIFT                                                 4
+  #define YSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR_BB_K2                                                       (0x1<<5) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_FIN_POP_ERROR .
+  #define YSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR_BB_K2_SHIFT                                                 5
+  #define YSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2                                                   (0x1<<6) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_DRA_WR_PUSH_ERROR .
+  #define YSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2_SHIFT                                             6
+  #define YSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR_BB_K2                                                    (0x1<<7) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_DRA_WR_POP_ERROR .
+  #define YSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT                                              7
+  #define YSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2                                                   (0x1<<8) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_DRA_RD_PUSH_ERROR .
+  #define YSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT                                             8
+  #define YSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR_BB_K2                                                    (0x1<<9) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_DRA_RD_POP_ERROR .
+  #define YSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR_BB_K2_SHIFT                                              9
+  #define YSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR_BB_K2                                                      (0x1<<10) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_FIN_PUSH_ERROR .
+  #define YSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR_BB_K2_SHIFT                                                10
+  #define YSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR_BB_K2                                                   (0x1<<11) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SEM_FAST_ADDRESS_ERROR .
+  #define YSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR_BB_K2_SHIFT                                             11
+  #define YSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO_BB_K2                                                         (0x1<<12) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.CAM_LSB_INP_FIFO .
+  #define YSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO_BB_K2_SHIFT                                                   12
+  #define YSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO_BB_K2                                                         (0x1<<13) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.CAM_MSB_INP_FIFO .
+  #define YSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO_BB_K2_SHIFT                                                   13
+  #define YSEM_REG_INT_MASK_0_CAM_OUT_FIFO_BB_K2                                                             (0x1<<14) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.CAM_OUT_FIFO .
+  #define YSEM_REG_INT_MASK_0_CAM_OUT_FIFO_BB_K2_SHIFT                                                       14
+  #define YSEM_REG_INT_MASK_0_FIN_FIFO_BB_K2                                                                 (0x1<<15) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.FIN_FIFO .
+  #define YSEM_REG_INT_MASK_0_FIN_FIFO_BB_K2_SHIFT                                                           15
+  #define YSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR_BB_K2                                                        (0x1<<16) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.THREAD_FIFO_ERROR .
+  #define YSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR_BB_K2_SHIFT                                                  16
+  #define YSEM_REG_INT_MASK_0_THREAD_OVERRUN_BB_K2                                                           (0x1<<17) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.THREAD_OVERRUN .
+  #define YSEM_REG_INT_MASK_0_THREAD_OVERRUN_BB_K2_SHIFT                                                     17
+  #define YSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2                                                (0x1<<18) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_EXT_STORE_PUSH_ERROR .
+  #define YSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2_SHIFT                                          18
+  #define YSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_BB_K2                                                 (0x1<<19) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR .
+  #define YSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_BB_K2_SHIFT                                           19
+  #define YSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2                                                 (0x1<<20) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR .
+  #define YSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2_SHIFT                                           20
+  #define YSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2                                                  (0x1<<21) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_EXT_LOAD_POP_ERROR .
+  #define YSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2_SHIFT                                            21
+  #define YSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR_BB_K2                                                    (0x1<<24) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_RAM_WR_POP_ERROR .
+  #define YSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR_BB_K2_SHIFT                                              24
+  #define YSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR_BB_K2                                                      (0x1<<26) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_DBG_PUSH_ERROR .
+  #define YSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR_BB_K2_SHIFT                                                26
+  #define YSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_BB_K2                                                       (0x1<<27) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR .
+  #define YSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_BB_K2_SHIFT                                                 27
+  #define YSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO_BB_K2                                                        (0x1<<29) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.CAM_MSB2_INP_FIFO .
+  #define YSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO_BB_K2_SHIFT                                                  29
+  #define YSEM_REG_INT_MASK_0_VFC_INTERRUPT_BB_K2                                                            (0x1<<30) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.VFC_INTERRUPT .
+  #define YSEM_REG_INT_MASK_0_VFC_INTERRUPT_BB_K2_SHIFT                                                      30
+  #define YSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR_BB_K2                                                       (0x1<<31) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.VFC_OUT_FIFO_ERROR .
+  #define YSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR_BB_K2_SHIFT                                                 31
+#define YSEM_REG_INT_STS_WR_0                                                                                0x1500048UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define YSEM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define YSEM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                          0
+  #define YSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR                                                               (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
+  #define YSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR_SHIFT                                                         1
+  #define YSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR                                                             (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
+  #define YSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR_SHIFT                                                       2
+  #define YSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR                                                               (0x1<<3) // Error in any one of the FIC FIFO is active.
+  #define YSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR_SHIFT                                                         3
+  #define YSEM_REG_INT_STS_WR_0_DRA_RD_A_LAST_ERROR_E5                                                       (0x1<<4) // DRA_RD_A last indication was unexpectedly received or was not received at expected time.
+  #define YSEM_REG_INT_STS_WR_0_DRA_RD_A_LAST_ERROR_E5_SHIFT                                                 4
+  #define YSEM_REG_INT_STS_WR_0_DRA_RD_B_LAST_ERROR_E5                                                       (0x1<<5) // DRA_RD_B last indication was unexpectedly received or was not received at expected time.
+  #define YSEM_REG_INT_STS_WR_0_DRA_RD_B_LAST_ERROR_E5_SHIFT                                                 5
+  #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_A_E5                                                (0x1<<6) // Error in external store slow sync FIFO pop logic of Storm A.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_A_E5_SHIFT                                          6
+  #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_B_E5                                                (0x1<<7) // Error in external store slow sync FIFO pop logic of Storm B.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT                                          7
+  #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5                                                (0x1<<8) // Error in external load sync slow FIFO push logic.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT                                          8
+  #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5                                                (0x1<<9) // Error in external load sync slow FIFO pop logic.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5_SHIFT                                          9
+  #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2                                                 (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2_SHIFT                                           22
+  #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_E5                                                    (0x1<<10) // Error in slow LS_SYNC_PUSH FIFO.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_E5_SHIFT                                              10
+  #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_BB_K2                                                  (0x1<<23) // Error in LS_SYNC_POP FIFO.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_BB_K2_SHIFT                                            23
+  #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_E5                                                     (0x1<<11) // Error in slow LS_SYNC_POP FIFO.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_E5_SHIFT                                               11
+  #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2                                                 (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2_SHIFT                                           25
+  #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_E5                                                    (0x1<<12) // Error in slow LS_SYNC_PUSH FIFO.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_E5_SHIFT                                              12
+  #define YSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_A_E5                                                      (0x1<<13) // Error in slow LS_SYNC_PUSH FIFO.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_A_E5_SHIFT                                                13
+  #define YSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_B_E5                                                      (0x1<<14) // Error in slow LS_SYNC_POP FIFO.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_B_E5_SHIFT                                                14
+  #define YSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_BB_K2                                                         (0x1<<28) // Error in slow debug fifo.
+  #define YSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_BB_K2_SHIFT                                                   28
+  #define YSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_E5                                                            (0x1<<15) // Error in slow debug fifo
+  #define YSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_E5_SHIFT                                                      15
+  #define YSEM_REG_INT_STS_WR_0_EXT_THREAD_OOR_ERROR_E5                                                      (0x1<<16) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define YSEM_REG_INT_STS_WR_0_EXT_THREAD_OOR_ERROR_E5_SHIFT                                                16
+  #define YSEM_REG_INT_STS_WR_0_EXT_STORE_TAG_ODER_ERROR_E5                                                  (0x1<<17) // Error detected in the ext Stroe interface internal TAG order ID.
+  #define YSEM_REG_INT_STS_WR_0_EXT_STORE_TAG_ODER_ERROR_E5_SHIFT                                            17
+  #define YSEM_REG_INT_STS_WR_0_FIC1_AFFINITY_FIELD_ERROR_E5                                                 (0x1<<18) // Indicates that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
+  #define YSEM_REG_INT_STS_WR_0_FIC1_AFFINITY_FIELD_ERROR_E5_SHIFT                                           18
+  #define YSEM_REG_INT_STS_WR_0_EXT_LD_LEN_ERROR_E5                                                          (0x1<<19) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define YSEM_REG_INT_STS_WR_0_EXT_LD_LEN_ERROR_E5_SHIFT                                                    19
+  #define YSEM_REG_INT_STS_WR_0_PB_QUE_ARB_THRD_RDY_ERROR_E5                                                 (0x1<<20) // Indicates that Passive Buffer State machine has unexpectedly received a ready indication in the following cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pending FOC" or "Ready FOC" state. b. Pending Ready indication is already asserted.
+  #define YSEM_REG_INT_STS_WR_0_PB_QUE_ARB_THRD_RDY_ERROR_E5_SHIFT                                           20
+  #define YSEM_REG_INT_STS_WR_0_SYNC_FOC_FIFO_ERROR_E5                                                       (0x1<<21) // Error indication on FOC sync FIFO.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_FOC_FIFO_ERROR_E5_SHIFT                                                 21
+  #define YSEM_REG_INT_STS_WR_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                   (0x1<<22) // The error indicates on an error of one the threads READY queues.
+  #define YSEM_REG_INT_STS_WR_0_PB_QUE_ARB_QUEUES_ERROR_E5_SHIFT                                             22
+  #define YSEM_REG_INT_STS_WR_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5                                             (0x1<<23) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define YSEM_REG_INT_STS_WR_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5_SHIFT                                       23
+  #define YSEM_REG_INT_STS_WR_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5                                             (0x1<<24) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define YSEM_REG_INT_STS_WR_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5_SHIFT                                       24
+  #define YSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC0_E5                                                         (0x1<<25) // FOC0 is out of credit.
+  #define YSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC0_E5_SHIFT                                                   25
+  #define YSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC1_E5                                                         (0x1<<26) // FOC1 is out of credit.
+  #define YSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC1_E5_SHIFT                                                   26
+  #define YSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC2_E5                                                         (0x1<<27) // FOC2 is out of credit.
+  #define YSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC2_E5_SHIFT                                                   27
+  #define YSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC3_E5                                                         (0x1<<28) // FOC3 is out of credit.
+  #define YSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC3_E5_SHIFT                                                   28
+  #define YSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC4_E5                                                         (0x1<<29) // FOC4 is out of credit.
+  #define YSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC4_E5_SHIFT                                                   29
+  #define YSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC5_E5                                                         (0x1<<30) // FOC5 is out of credit.
+  #define YSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC5_E5_SHIFT                                                   30
+  #define YSEM_REG_INT_STS_WR_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                  (0x1<<31) // Error indication of foc pre_fetch fifo.
+  #define YSEM_REG_INT_STS_WR_0_FOC_PRE_FETCH_FIFO_ERROR_E5_SHIFT                                            31
+  #define YSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR_BB_K2                                                     (0x1<<4) // Error in Ext PAS_FIFO is active.
+  #define YSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR_BB_K2_SHIFT                                               4
+  #define YSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR_BB_K2                                                     (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR_BB_K2_SHIFT                                               5
+  #define YSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2                                                 (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2_SHIFT                                           6
+  #define YSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR_BB_K2                                                  (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT                                            7
+  #define YSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2                                                 (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT                                           8
+  #define YSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR_BB_K2                                                  (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR_BB_K2_SHIFT                                            9
+  #define YSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR_BB_K2                                                    (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR_BB_K2_SHIFT                                              10
+  #define YSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR_BB_K2                                                 (0x1<<11) // Signals an unknown address in the fast-memory window.
+  #define YSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR_BB_K2_SHIFT                                           11
+  #define YSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO_BB_K2                                                       (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
+  #define YSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO_BB_K2_SHIFT                                                 12
+  #define YSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO_BB_K2                                                       (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
+  #define YSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO_BB_K2_SHIFT                                                 13
+  #define YSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO_BB_K2                                                           (0x1<<14) // Error in CAM_OUT fifo in cam block.
+  #define YSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO_BB_K2_SHIFT                                                     14
+  #define YSEM_REG_INT_STS_WR_0_FIN_FIFO_BB_K2                                                               (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
+  #define YSEM_REG_INT_STS_WR_0_FIN_FIFO_BB_K2_SHIFT                                                         15
+  #define YSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR_BB_K2                                                      (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
+  #define YSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR_BB_K2_SHIFT                                                16
+  #define YSEM_REG_INT_STS_WR_0_THREAD_OVERRUN_BB_K2                                                         (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
+  #define YSEM_REG_INT_STS_WR_0_THREAD_OVERRUN_BB_K2_SHIFT                                                   17
+  #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2                                              (0x1<<18) // Error in external store sync FIFO push logic.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2_SHIFT                                        18
+  #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_BB_K2                                               (0x1<<19) // Error in external store sync FIFO pop logic.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_BB_K2_SHIFT                                         19
+  #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2                                               (0x1<<20) // Error in external load sync FIFO push logic.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2_SHIFT                                         20
+  #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2                                                (0x1<<21) // Error in external load sync FIFO pop logic.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2_SHIFT                                          21
+  #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR_BB_K2                                                  (0x1<<24) // Error in LS_SYNC_POP FIFO.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR_BB_K2_SHIFT                                            24
+  #define YSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR_BB_K2                                                    (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR_BB_K2_SHIFT                                              26
+  #define YSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_BB_K2                                                     (0x1<<27) // Error in LS_SYNC_POP FIFO.
+  #define YSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_BB_K2_SHIFT                                               27
+  #define YSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO_BB_K2                                                      (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
+  #define YSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO_BB_K2_SHIFT                                                29
+  #define YSEM_REG_INT_STS_WR_0_VFC_INTERRUPT_BB_K2                                                          (0x1<<30) // Error interrupt in VFC block.
+  #define YSEM_REG_INT_STS_WR_0_VFC_INTERRUPT_BB_K2_SHIFT                                                    30
+  #define YSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR_BB_K2                                                     (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
+  #define YSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR_BB_K2_SHIFT                                               31
+#define YSEM_REG_INT_STS_CLR_0                                                                               0x150004cUL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define YSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                               (0x1<<0) // Signals an unknown address to the rf module.
+  #define YSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                         0
+  #define YSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR                                                              (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
+  #define YSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR_SHIFT                                                        1
+  #define YSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR                                                            (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
+  #define YSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR_SHIFT                                                      2
+  #define YSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR                                                              (0x1<<3) // Error in any one of the FIC FIFO is active.
+  #define YSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR_SHIFT                                                        3
+  #define YSEM_REG_INT_STS_CLR_0_DRA_RD_A_LAST_ERROR_E5                                                      (0x1<<4) // DRA_RD_A last indication was unexpectedly received or was not received at expected time.
+  #define YSEM_REG_INT_STS_CLR_0_DRA_RD_A_LAST_ERROR_E5_SHIFT                                                4
+  #define YSEM_REG_INT_STS_CLR_0_DRA_RD_B_LAST_ERROR_E5                                                      (0x1<<5) // DRA_RD_B last indication was unexpectedly received or was not received at expected time.
+  #define YSEM_REG_INT_STS_CLR_0_DRA_RD_B_LAST_ERROR_E5_SHIFT                                                5
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_A_E5                                               (0x1<<6) // Error in external store slow sync FIFO pop logic of Storm A.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_A_E5_SHIFT                                         6
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_B_E5                                               (0x1<<7) // Error in external store slow sync FIFO pop logic of Storm B.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT                                         7
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5                                               (0x1<<8) // Error in external load sync slow FIFO push logic.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT                                         8
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5                                               (0x1<<9) // Error in external load sync slow FIFO pop logic.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5_SHIFT                                         9
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2                                                (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2_SHIFT                                          22
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_E5                                                   (0x1<<10) // Error in slow LS_SYNC_PUSH FIFO.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_E5_SHIFT                                             10
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_BB_K2                                                 (0x1<<23) // Error in LS_SYNC_POP FIFO.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_BB_K2_SHIFT                                           23
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_E5                                                    (0x1<<11) // Error in slow LS_SYNC_POP FIFO.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_E5_SHIFT                                              11
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2                                                (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2_SHIFT                                          25
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_E5                                                   (0x1<<12) // Error in slow LS_SYNC_PUSH FIFO.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_E5_SHIFT                                             12
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_A_E5                                                     (0x1<<13) // Error in slow LS_SYNC_PUSH FIFO.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_A_E5_SHIFT                                               13
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_B_E5                                                     (0x1<<14) // Error in slow LS_SYNC_POP FIFO.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_B_E5_SHIFT                                               14
+  #define YSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_BB_K2                                                        (0x1<<28) // Error in slow debug fifo.
+  #define YSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_BB_K2_SHIFT                                                  28
+  #define YSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_E5                                                           (0x1<<15) // Error in slow debug fifo
+  #define YSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_E5_SHIFT                                                     15
+  #define YSEM_REG_INT_STS_CLR_0_EXT_THREAD_OOR_ERROR_E5                                                     (0x1<<16) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define YSEM_REG_INT_STS_CLR_0_EXT_THREAD_OOR_ERROR_E5_SHIFT                                               16
+  #define YSEM_REG_INT_STS_CLR_0_EXT_STORE_TAG_ODER_ERROR_E5                                                 (0x1<<17) // Error detected in the ext Stroe interface internal TAG order ID.
+  #define YSEM_REG_INT_STS_CLR_0_EXT_STORE_TAG_ODER_ERROR_E5_SHIFT                                           17
+  #define YSEM_REG_INT_STS_CLR_0_FIC1_AFFINITY_FIELD_ERROR_E5                                                (0x1<<18) // Indicates that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
+  #define YSEM_REG_INT_STS_CLR_0_FIC1_AFFINITY_FIELD_ERROR_E5_SHIFT                                          18
+  #define YSEM_REG_INT_STS_CLR_0_EXT_LD_LEN_ERROR_E5                                                         (0x1<<19) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define YSEM_REG_INT_STS_CLR_0_EXT_LD_LEN_ERROR_E5_SHIFT                                                   19
+  #define YSEM_REG_INT_STS_CLR_0_PB_QUE_ARB_THRD_RDY_ERROR_E5                                                (0x1<<20) // Indicates that Passive Buffer State machine has unexpectedly received a ready indication in the following cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pending FOC" or "Ready FOC" state. b. Pending Ready indication is already asserted.
+  #define YSEM_REG_INT_STS_CLR_0_PB_QUE_ARB_THRD_RDY_ERROR_E5_SHIFT                                          20
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_FOC_FIFO_ERROR_E5                                                      (0x1<<21) // Error indication on FOC sync FIFO.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_FOC_FIFO_ERROR_E5_SHIFT                                                21
+  #define YSEM_REG_INT_STS_CLR_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                  (0x1<<22) // The error indicates on an error of one the threads READY queues.
+  #define YSEM_REG_INT_STS_CLR_0_PB_QUE_ARB_QUEUES_ERROR_E5_SHIFT                                            22
+  #define YSEM_REG_INT_STS_CLR_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5                                            (0x1<<23) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define YSEM_REG_INT_STS_CLR_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5_SHIFT                                      23
+  #define YSEM_REG_INT_STS_CLR_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5                                            (0x1<<24) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define YSEM_REG_INT_STS_CLR_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5_SHIFT                                      24
+  #define YSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC0_E5                                                        (0x1<<25) // FOC0 is out of credit.
+  #define YSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC0_E5_SHIFT                                                  25
+  #define YSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC1_E5                                                        (0x1<<26) // FOC1 is out of credit.
+  #define YSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC1_E5_SHIFT                                                  26
+  #define YSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC2_E5                                                        (0x1<<27) // FOC2 is out of credit.
+  #define YSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC2_E5_SHIFT                                                  27
+  #define YSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC3_E5                                                        (0x1<<28) // FOC3 is out of credit.
+  #define YSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC3_E5_SHIFT                                                  28
+  #define YSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC4_E5                                                        (0x1<<29) // FOC4 is out of credit.
+  #define YSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC4_E5_SHIFT                                                  29
+  #define YSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC5_E5                                                        (0x1<<30) // FOC5 is out of credit.
+  #define YSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC5_E5_SHIFT                                                  30
+  #define YSEM_REG_INT_STS_CLR_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                 (0x1<<31) // Error indication of foc pre_fetch fifo.
+  #define YSEM_REG_INT_STS_CLR_0_FOC_PRE_FETCH_FIFO_ERROR_E5_SHIFT                                           31
+  #define YSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR_BB_K2                                                    (0x1<<4) // Error in Ext PAS_FIFO is active.
+  #define YSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR_BB_K2_SHIFT                                              4
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR_BB_K2                                                    (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR_BB_K2_SHIFT                                              5
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2                                                (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2_SHIFT                                          6
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR_BB_K2                                                 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT                                           7
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2                                                (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT                                          8
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR_BB_K2                                                 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR_BB_K2_SHIFT                                           9
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR_BB_K2                                                   (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR_BB_K2_SHIFT                                             10
+  #define YSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR_BB_K2                                                (0x1<<11) // Signals an unknown address in the fast-memory window.
+  #define YSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR_BB_K2_SHIFT                                          11
+  #define YSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO_BB_K2                                                      (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
+  #define YSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO_BB_K2_SHIFT                                                12
+  #define YSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO_BB_K2                                                      (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
+  #define YSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO_BB_K2_SHIFT                                                13
+  #define YSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO_BB_K2                                                          (0x1<<14) // Error in CAM_OUT fifo in cam block.
+  #define YSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO_BB_K2_SHIFT                                                    14
+  #define YSEM_REG_INT_STS_CLR_0_FIN_FIFO_BB_K2                                                              (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
+  #define YSEM_REG_INT_STS_CLR_0_FIN_FIFO_BB_K2_SHIFT                                                        15
+  #define YSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR_BB_K2                                                     (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
+  #define YSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR_BB_K2_SHIFT                                               16
+  #define YSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN_BB_K2                                                        (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
+  #define YSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN_BB_K2_SHIFT                                                  17
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2                                             (0x1<<18) // Error in external store sync FIFO push logic.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2_SHIFT                                       18
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_BB_K2                                              (0x1<<19) // Error in external store sync FIFO pop logic.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_BB_K2_SHIFT                                        19
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2                                              (0x1<<20) // Error in external load sync FIFO push logic.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2_SHIFT                                        20
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2                                               (0x1<<21) // Error in external load sync FIFO pop logic.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2_SHIFT                                         21
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR_BB_K2                                                 (0x1<<24) // Error in LS_SYNC_POP FIFO.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR_BB_K2_SHIFT                                           24
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR_BB_K2                                                   (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR_BB_K2_SHIFT                                             26
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_BB_K2                                                    (0x1<<27) // Error in LS_SYNC_POP FIFO.
+  #define YSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_BB_K2_SHIFT                                              27
+  #define YSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO_BB_K2                                                     (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
+  #define YSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO_BB_K2_SHIFT                                               29
+  #define YSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT_BB_K2                                                         (0x1<<30) // Error interrupt in VFC block.
+  #define YSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT_BB_K2_SHIFT                                                   30
+  #define YSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR_BB_K2                                                    (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
+  #define YSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR_BB_K2_SHIFT                                              31
+#define YSEM_REG_INT_STS_1                                                                                   0x1500050UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define YSEM_REG_INT_STS_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5                                              (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
+  #define YSEM_REG_INT_STS_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5_SHIFT                                        0
+  #define YSEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_A_E5                                                  (0x1<<1) // Fast external store FIFO error of Storm_A
+  #define YSEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT                                            1
+  #define YSEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_B_E5                                                  (0x1<<2) // Fast external store FIFO error of Storm_B
+  #define YSEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_B_E5_SHIFT                                            2
+  #define YSEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_A_E5                                                    (0x1<<3) // fast external load FIFO error of Storm_A
+  #define YSEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT                                              3
+  #define YSEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_B_E5                                                    (0x1<<4) // fast external load FIFO error of Storm_B
+  #define YSEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_B_E5_SHIFT                                              4
+  #define YSEM_REG_INT_STS_1_FAST_RAM_WR_POP_ERROR_E5                                                        (0x1<<5) // Internal RAM pop error
+  #define YSEM_REG_INT_STS_1_FAST_RAM_WR_POP_ERROR_E5_SHIFT                                                  5
+  #define YSEM_REG_INT_STS_1_FAST_RAM_RD_PUSH_ERROR_E5                                                       (0x1<<6) // Internal RAM write error
+  #define YSEM_REG_INT_STS_1_FAST_RAM_RD_PUSH_ERROR_E5_SHIFT                                                 6
+  #define YSEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_A_E5                                                     (0x1<<7) // DRA RD FIFO error of Storm A
+  #define YSEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT                                               7
+  #define YSEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_B_E5                                                     (0x1<<8) // DRA RD FIFO error of Storm B
+  #define YSEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT                                               8
+  #define YSEM_REG_INT_STS_1_FAST_DRA_WR_POP_ERROR_A_E5                                                      (0x1<<9) // DRA RD FIFO error of Storm A
+  #define YSEM_REG_INT_STS_1_FAST_DRA_WR_POP_ERROR_A_E5_SHIFT                                                9
+  #define YSEM_REG_INT_STS_1_FAST_DRA_WR_POP_ERROR_B_E5                                                      (0x1<<10) // DRA RD FIFO error of Storm B
+  #define YSEM_REG_INT_STS_1_FAST_DRA_WR_POP_ERROR_B_E5_SHIFT                                                10
+  #define YSEM_REG_INT_STS_1_SEM_FAST_INVLD_ADDR_ERR_E5                                                      (0x1<<11) // Fast invalid address error
+  #define YSEM_REG_INT_STS_1_SEM_FAST_INVLD_ADDR_ERR_E5_SHIFT                                                11
+  #define YSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_A_E5                                                        (0x1<<12) // Storm A stack_uf_attn interrupt
+  #define YSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_A_E5_SHIFT                                                  12
+  #define YSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_B_E5                                                        (0x1<<13) // Storm B stack_uf_attn interrupt
+  #define YSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_B_E5_SHIFT                                                  13
+  #define YSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_A_E5                                                        (0x1<<14) // Storm A stack_of_attn interrupt
+  #define YSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_A_E5_SHIFT                                                  14
+  #define YSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_B_E5                                                        (0x1<<15) // Storm B stack_of_attn interrupt
+  #define YSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_B_E5_SHIFT                                                  15
+  #define YSEM_REG_INT_STS_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5                                                 (0x1<<16) // Storm A ldst_addr_ovflw_attn interrupt
+  #define YSEM_REG_INT_STS_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5_SHIFT                                           16
+  #define YSEM_REG_INT_STS_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5                                                 (0x1<<17) // Storm B ldst_addr_ovflw_attn interrupt
+  #define YSEM_REG_INT_STS_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5_SHIFT                                           17
+  #define YSEM_REG_INT_STS_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5                                              (0x1<<18) // Storm A non_aligned_access_attn interrupt
+  #define YSEM_REG_INT_STS_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5_SHIFT                                        18
+  #define YSEM_REG_INT_STS_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5                                              (0x1<<19) // Storm B non_aligned_access_attn interrupt
+  #define YSEM_REG_INT_STS_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5_SHIFT                                        19
+  #define YSEM_REG_INT_STS_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5                                                (0x1<<20) // Storm A division_by_zero_attn interrupt
+  #define YSEM_REG_INT_STS_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5_SHIFT                                          20
+  #define YSEM_REG_INT_STS_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5                                                (0x1<<21) // Storm B division_by_zero_attn interrupt
+  #define YSEM_REG_INT_STS_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5_SHIFT                                          21
+  #define YSEM_REG_INT_STS_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5                                           (0x1<<22) // Storm A illegal_runtime_value_attn interrupt
+  #define YSEM_REG_INT_STS_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5_SHIFT                                     22
+  #define YSEM_REG_INT_STS_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5                                           (0x1<<23) // Storm B illegal_runtime_value_attn interrupt
+  #define YSEM_REG_INT_STS_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5_SHIFT                                     23
+  #define YSEM_REG_INT_STS_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5                                            (0x1<<24) // load request is made while previous is still active; not fully read, Storm A
+  #define YSEM_REG_INT_STS_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5_SHIFT                                      24
+  #define YSEM_REG_INT_STS_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5                                            (0x1<<25) // load request is made while previous is still active; not fully read, Storm B
+  #define YSEM_REG_INT_STS_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5_SHIFT                                      25
+  #define YSEM_REG_INT_STS_1_CAM_RBC_FAST_OUT_ERROR_A_E5                                                     (0x1<<26) // Error in CAM_OUT fifo in cam block of STORM A
+  #define YSEM_REG_INT_STS_1_CAM_RBC_FAST_OUT_ERROR_A_E5_SHIFT                                               26
+  #define YSEM_REG_INT_STS_1_CAM_RBC_FAST_OUT_ERROR_B_E5                                                     (0x1<<27) // Error in CAM_OUT fifo in cam block of STORM B
+  #define YSEM_REG_INT_STS_1_CAM_RBC_FAST_OUT_ERROR_B_E5_SHIFT                                               27
+  #define YSEM_REG_INT_STS_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5                                                 (0x1<<28) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define YSEM_REG_INT_STS_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5_SHIFT                                           28
+  #define YSEM_REG_INT_STS_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5                                                 (0x1<<29) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define YSEM_REG_INT_STS_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5_SHIFT                                           29
+  #define YSEM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5                                                 (0x1<<30) // Error in CAM_LSB_INP fifo in cam block of STORM A
+  #define YSEM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT                                           30
+  #define YSEM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5                                                 (0x1<<31) // Error in CAM_LSB_INP fifo in cam block of STORM B.
+  #define YSEM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5_SHIFT                                           31
+  #define YSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_BB_K2                                                       (0x1<<0) // An underflow error was detected in the Storm stack.
+  #define YSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_BB_K2_SHIFT                                                 0
+  #define YSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_BB_K2                                                       (0x1<<1) // An overflow error was detected in the Storm stack.
+  #define YSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT                                                 1
+  #define YSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR_BB_K2                                                       (0x1<<2) // The Storm detected an illegal runtime value.
+  #define YSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR_BB_K2_SHIFT                                                 2
+  #define YSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR_BB_K2                                                    (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
+  #define YSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT                                              3
+  #define YSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR_BB_K2                                                     (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
+  #define YSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR_BB_K2_SHIFT                                               4
+  #define YSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR_BB_K2                                                     (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
+  #define YSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR_BB_K2_SHIFT                                               5
+  #define YSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR_BB_K2                                                      (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
+  #define YSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR_BB_K2_SHIFT                                                6
+  #define YSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR_BB_K2                                                      (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define YSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT                                                7
+  #define YSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR_BB_K2                                                         (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
+  #define YSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT                                                   8
+  #define YSEM_REG_INT_STS_1_INVLD_FOC_ERROR_BB_K2                                                           (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
+  #define YSEM_REG_INT_STS_1_INVLD_FOC_ERROR_BB_K2_SHIFT                                                     9
+  #define YSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR_BB_K2                                                          (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define YSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR_BB_K2_SHIFT                                                    10
+  #define YSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR_BB_K2                                                       (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
+  #define YSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR_BB_K2_SHIFT                                                 11
+  #define YSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR_BB_K2                                                      (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
+  #define YSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR_BB_K2_SHIFT                                                12
+#define YSEM_REG_INT_MASK_1                                                                                  0x1500054UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define YSEM_REG_INT_MASK_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5                                             (0x1<<0) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.RBC_COMMON_ACCESS_COL_VFC_ERROR .
+  #define YSEM_REG_INT_MASK_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5_SHIFT                                       0
+  #define YSEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_A_E5                                                 (0x1<<1) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.FAST_EXT_STORE_PUSH_ERROR_A .
+  #define YSEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT                                           1
+  #define YSEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_B_E5                                                 (0x1<<2) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.FAST_EXT_STORE_PUSH_ERROR_B .
+  #define YSEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_B_E5_SHIFT                                           2
+  #define YSEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_A_E5                                                   (0x1<<3) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.FAST_EXT_LOAD_POP_ERROR_A .
+  #define YSEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT                                             3
+  #define YSEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_B_E5                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.FAST_EXT_LOAD_POP_ERROR_B .
+  #define YSEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_B_E5_SHIFT                                             4
+  #define YSEM_REG_INT_MASK_1_FAST_RAM_WR_POP_ERROR_E5                                                       (0x1<<5) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.FAST_RAM_WR_POP_ERROR .
+  #define YSEM_REG_INT_MASK_1_FAST_RAM_WR_POP_ERROR_E5_SHIFT                                                 5
+  #define YSEM_REG_INT_MASK_1_FAST_RAM_RD_PUSH_ERROR_E5                                                      (0x1<<6) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.FAST_RAM_RD_PUSH_ERROR .
+  #define YSEM_REG_INT_MASK_1_FAST_RAM_RD_PUSH_ERROR_E5_SHIFT                                                6
+  #define YSEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_A_E5                                                    (0x1<<7) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.FAST_DRA_RD_PUSH_ERROR_A .
+  #define YSEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT                                              7
+  #define YSEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_B_E5                                                    (0x1<<8) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.FAST_DRA_RD_PUSH_ERROR_B .
+  #define YSEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT                                              8
+  #define YSEM_REG_INT_MASK_1_FAST_DRA_WR_POP_ERROR_A_E5                                                     (0x1<<9) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.FAST_DRA_WR_POP_ERROR_A .
+  #define YSEM_REG_INT_MASK_1_FAST_DRA_WR_POP_ERROR_A_E5_SHIFT                                               9
+  #define YSEM_REG_INT_MASK_1_FAST_DRA_WR_POP_ERROR_B_E5                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.FAST_DRA_WR_POP_ERROR_B .
+  #define YSEM_REG_INT_MASK_1_FAST_DRA_WR_POP_ERROR_B_E5_SHIFT                                               10
+  #define YSEM_REG_INT_MASK_1_SEM_FAST_INVLD_ADDR_ERR_E5                                                     (0x1<<11) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.SEM_FAST_INVLD_ADDR_ERR .
+  #define YSEM_REG_INT_MASK_1_SEM_FAST_INVLD_ADDR_ERR_E5_SHIFT                                               11
+  #define YSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_A_E5                                                       (0x1<<12) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN_A .
+  #define YSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_A_E5_SHIFT                                                 12
+  #define YSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_B_E5                                                       (0x1<<13) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN_B .
+  #define YSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_B_E5_SHIFT                                                 13
+  #define YSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_A_E5                                                       (0x1<<14) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN_A .
+  #define YSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_A_E5_SHIFT                                                 14
+  #define YSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_B_E5                                                       (0x1<<15) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN_B .
+  #define YSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_B_E5_SHIFT                                                 15
+  #define YSEM_REG_INT_MASK_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5                                                (0x1<<16) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.STORM_LDST_ADDR_OVFLW_ATTN_A .
+  #define YSEM_REG_INT_MASK_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5_SHIFT                                          16
+  #define YSEM_REG_INT_MASK_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5                                                (0x1<<17) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.STORM_LDST_ADDR_OVFLW_ATTN_B .
+  #define YSEM_REG_INT_MASK_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5_SHIFT                                          17
+  #define YSEM_REG_INT_MASK_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5                                             (0x1<<18) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.STORM_NON_ALIGNED_ACCESS_ATTN_A .
+  #define YSEM_REG_INT_MASK_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5_SHIFT                                       18
+  #define YSEM_REG_INT_MASK_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5                                             (0x1<<19) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.STORM_NON_ALIGNED_ACCESS_ATTN_B .
+  #define YSEM_REG_INT_MASK_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5_SHIFT                                       19
+  #define YSEM_REG_INT_MASK_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5                                               (0x1<<20) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.STORM_DIVISION_BY_ZERO_ATTN_A .
+  #define YSEM_REG_INT_MASK_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5_SHIFT                                         20
+  #define YSEM_REG_INT_MASK_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5                                               (0x1<<21) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.STORM_DIVISION_BY_ZERO_ATTN_B .
+  #define YSEM_REG_INT_MASK_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5_SHIFT                                         21
+  #define YSEM_REG_INT_MASK_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5                                          (0x1<<22) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A .
+  #define YSEM_REG_INT_MASK_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5_SHIFT                                    22
+  #define YSEM_REG_INT_MASK_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5                                          (0x1<<23) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B .
+  #define YSEM_REG_INT_MASK_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5_SHIFT                                    23
+  #define YSEM_REG_INT_MASK_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5                                           (0x1<<24) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A .
+  #define YSEM_REG_INT_MASK_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5_SHIFT                                     24
+  #define YSEM_REG_INT_MASK_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5                                           (0x1<<25) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B .
+  #define YSEM_REG_INT_MASK_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5_SHIFT                                     25
+  #define YSEM_REG_INT_MASK_1_CAM_RBC_FAST_OUT_ERROR_A_E5                                                    (0x1<<26) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.CAM_RBC_FAST_OUT_ERROR_A .
+  #define YSEM_REG_INT_MASK_1_CAM_RBC_FAST_OUT_ERROR_A_E5_SHIFT                                              26
+  #define YSEM_REG_INT_MASK_1_CAM_RBC_FAST_OUT_ERROR_B_E5                                                    (0x1<<27) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.CAM_RBC_FAST_OUT_ERROR_B .
+  #define YSEM_REG_INT_MASK_1_CAM_RBC_FAST_OUT_ERROR_B_E5_SHIFT                                              27
+  #define YSEM_REG_INT_MASK_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5                                                (0x1<<28) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.CAM_RBC_FAST_MSB_INP_ERROR_A .
+  #define YSEM_REG_INT_MASK_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5_SHIFT                                          28
+  #define YSEM_REG_INT_MASK_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5                                                (0x1<<29) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.CAM_RBC_FAST_MSB_INP_ERROR_B .
+  #define YSEM_REG_INT_MASK_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5_SHIFT                                          29
+  #define YSEM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5                                                (0x1<<30) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.CAM_RBC_FAST_LSB_INP_ERROR_A .
+  #define YSEM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT                                          30
+  #define YSEM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5                                                (0x1<<31) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.CAM_RBC_FAST_LSB_INP_ERROR_B .
+  #define YSEM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5_SHIFT                                          31
+  #define YSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_BB_K2                                                      (0x1<<0) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN .
+  #define YSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_BB_K2_SHIFT                                                0
+  #define YSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_BB_K2                                                      (0x1<<1) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN .
+  #define YSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT                                                1
+  #define YSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR_BB_K2                                                      (0x1<<2) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.STORM_RUNTIME_ERROR .
+  #define YSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR_BB_K2_SHIFT                                                2
+  #define YSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR_BB_K2                                                   (0x1<<3) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.EXT_LOAD_PEND_WR_ERROR .
+  #define YSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT                                             3
+  #define YSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR_BB_K2                                                    (0x1<<4) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.THREAD_RLS_ORUN_ERROR .
+  #define YSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR_BB_K2_SHIFT                                              4
+  #define YSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR_BB_K2                                                    (0x1<<5) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.THREAD_RLS_ALOC_ERROR .
+  #define YSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR_BB_K2_SHIFT                                              5
+  #define YSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR_BB_K2                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.THREAD_RLS_VLD_ERROR .
+  #define YSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR_BB_K2_SHIFT                                               6
+  #define YSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR_BB_K2                                                     (0x1<<7) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.EXT_THREAD_OOR_ERROR .
+  #define YSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT                                               7
+  #define YSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR_BB_K2                                                        (0x1<<8) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.ORD_ID_FIFO_ERROR .
+  #define YSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT                                                  8
+  #define YSEM_REG_INT_MASK_1_INVLD_FOC_ERROR_BB_K2                                                          (0x1<<9) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.INVLD_FOC_ERROR .
+  #define YSEM_REG_INT_MASK_1_INVLD_FOC_ERROR_BB_K2_SHIFT                                                    9
+  #define YSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR_BB_K2                                                         (0x1<<10) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.EXT_LD_LEN_ERROR .
+  #define YSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR_BB_K2_SHIFT                                                   10
+  #define YSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR_BB_K2                                                      (0x1<<11) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.THRD_ORD_FIFO_ERROR .
+  #define YSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR_BB_K2_SHIFT                                                11
+  #define YSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR_BB_K2                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.INVLD_THRD_ORD_ERROR .
+  #define YSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR_BB_K2_SHIFT                                               12
+#define YSEM_REG_INT_STS_WR_1                                                                                0x1500058UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define YSEM_REG_INT_STS_WR_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5                                           (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
+  #define YSEM_REG_INT_STS_WR_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5_SHIFT                                     0
+  #define YSEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5                                               (0x1<<1) // Fast external store FIFO error of Storm_A
+  #define YSEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT                                         1
+  #define YSEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_B_E5                                               (0x1<<2) // Fast external store FIFO error of Storm_B
+  #define YSEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_B_E5_SHIFT                                         2
+  #define YSEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_A_E5                                                 (0x1<<3) // fast external load FIFO error of Storm_A
+  #define YSEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT                                           3
+  #define YSEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_B_E5                                                 (0x1<<4) // fast external load FIFO error of Storm_B
+  #define YSEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_B_E5_SHIFT                                           4
+  #define YSEM_REG_INT_STS_WR_1_FAST_RAM_WR_POP_ERROR_E5                                                     (0x1<<5) // Internal RAM pop error
+  #define YSEM_REG_INT_STS_WR_1_FAST_RAM_WR_POP_ERROR_E5_SHIFT                                               5
+  #define YSEM_REG_INT_STS_WR_1_FAST_RAM_RD_PUSH_ERROR_E5                                                    (0x1<<6) // Internal RAM write error
+  #define YSEM_REG_INT_STS_WR_1_FAST_RAM_RD_PUSH_ERROR_E5_SHIFT                                              6
+  #define YSEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_A_E5                                                  (0x1<<7) // DRA RD FIFO error of Storm A
+  #define YSEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT                                            7
+  #define YSEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_B_E5                                                  (0x1<<8) // DRA RD FIFO error of Storm B
+  #define YSEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT                                            8
+  #define YSEM_REG_INT_STS_WR_1_FAST_DRA_WR_POP_ERROR_A_E5                                                   (0x1<<9) // DRA RD FIFO error of Storm A
+  #define YSEM_REG_INT_STS_WR_1_FAST_DRA_WR_POP_ERROR_A_E5_SHIFT                                             9
+  #define YSEM_REG_INT_STS_WR_1_FAST_DRA_WR_POP_ERROR_B_E5                                                   (0x1<<10) // DRA RD FIFO error of Storm B
+  #define YSEM_REG_INT_STS_WR_1_FAST_DRA_WR_POP_ERROR_B_E5_SHIFT                                             10
+  #define YSEM_REG_INT_STS_WR_1_SEM_FAST_INVLD_ADDR_ERR_E5                                                   (0x1<<11) // Fast invalid address error
+  #define YSEM_REG_INT_STS_WR_1_SEM_FAST_INVLD_ADDR_ERR_E5_SHIFT                                             11
+  #define YSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_A_E5                                                     (0x1<<12) // Storm A stack_uf_attn interrupt
+  #define YSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_A_E5_SHIFT                                               12
+  #define YSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_B_E5                                                     (0x1<<13) // Storm B stack_uf_attn interrupt
+  #define YSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_B_E5_SHIFT                                               13
+  #define YSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_A_E5                                                     (0x1<<14) // Storm A stack_of_attn interrupt
+  #define YSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_A_E5_SHIFT                                               14
+  #define YSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_B_E5                                                     (0x1<<15) // Storm B stack_of_attn interrupt
+  #define YSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_B_E5_SHIFT                                               15
+  #define YSEM_REG_INT_STS_WR_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5                                              (0x1<<16) // Storm A ldst_addr_ovflw_attn interrupt
+  #define YSEM_REG_INT_STS_WR_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5_SHIFT                                        16
+  #define YSEM_REG_INT_STS_WR_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5                                              (0x1<<17) // Storm B ldst_addr_ovflw_attn interrupt
+  #define YSEM_REG_INT_STS_WR_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5_SHIFT                                        17
+  #define YSEM_REG_INT_STS_WR_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5                                           (0x1<<18) // Storm A non_aligned_access_attn interrupt
+  #define YSEM_REG_INT_STS_WR_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5_SHIFT                                     18
+  #define YSEM_REG_INT_STS_WR_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5                                           (0x1<<19) // Storm B non_aligned_access_attn interrupt
+  #define YSEM_REG_INT_STS_WR_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5_SHIFT                                     19
+  #define YSEM_REG_INT_STS_WR_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5                                             (0x1<<20) // Storm A division_by_zero_attn interrupt
+  #define YSEM_REG_INT_STS_WR_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5_SHIFT                                       20
+  #define YSEM_REG_INT_STS_WR_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5                                             (0x1<<21) // Storm B division_by_zero_attn interrupt
+  #define YSEM_REG_INT_STS_WR_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5_SHIFT                                       21
+  #define YSEM_REG_INT_STS_WR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5                                        (0x1<<22) // Storm A illegal_runtime_value_attn interrupt
+  #define YSEM_REG_INT_STS_WR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5_SHIFT                                  22
+  #define YSEM_REG_INT_STS_WR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5                                        (0x1<<23) // Storm B illegal_runtime_value_attn interrupt
+  #define YSEM_REG_INT_STS_WR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5_SHIFT                                  23
+  #define YSEM_REG_INT_STS_WR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5                                         (0x1<<24) // load request is made while previous is still active; not fully read, Storm A
+  #define YSEM_REG_INT_STS_WR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5_SHIFT                                   24
+  #define YSEM_REG_INT_STS_WR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5                                         (0x1<<25) // load request is made while previous is still active; not fully read, Storm B
+  #define YSEM_REG_INT_STS_WR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5_SHIFT                                   25
+  #define YSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_OUT_ERROR_A_E5                                                  (0x1<<26) // Error in CAM_OUT fifo in cam block of STORM A
+  #define YSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_OUT_ERROR_A_E5_SHIFT                                            26
+  #define YSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_OUT_ERROR_B_E5                                                  (0x1<<27) // Error in CAM_OUT fifo in cam block of STORM B
+  #define YSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_OUT_ERROR_B_E5_SHIFT                                            27
+  #define YSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5                                              (0x1<<28) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define YSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5_SHIFT                                        28
+  #define YSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5                                              (0x1<<29) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define YSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5_SHIFT                                        29
+  #define YSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5                                              (0x1<<30) // Error in CAM_LSB_INP fifo in cam block of STORM A
+  #define YSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT                                        30
+  #define YSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5                                              (0x1<<31) // Error in CAM_LSB_INP fifo in cam block of STORM B.
+  #define YSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5_SHIFT                                        31
+  #define YSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_BB_K2                                                    (0x1<<0) // An underflow error was detected in the Storm stack.
+  #define YSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_BB_K2_SHIFT                                              0
+  #define YSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_BB_K2                                                    (0x1<<1) // An overflow error was detected in the Storm stack.
+  #define YSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT                                              1
+  #define YSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR_BB_K2                                                    (0x1<<2) // The Storm detected an illegal runtime value.
+  #define YSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR_BB_K2_SHIFT                                              2
+  #define YSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2                                                 (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
+  #define YSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT                                           3
+  #define YSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR_BB_K2                                                  (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
+  #define YSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR_BB_K2_SHIFT                                            4
+  #define YSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR_BB_K2                                                  (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
+  #define YSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR_BB_K2_SHIFT                                            5
+  #define YSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR_BB_K2                                                   (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
+  #define YSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR_BB_K2_SHIFT                                             6
+  #define YSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR_BB_K2                                                   (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define YSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT                                             7
+  #define YSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR_BB_K2                                                      (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
+  #define YSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT                                                8
+  #define YSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR_BB_K2                                                        (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
+  #define YSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR_BB_K2_SHIFT                                                  9
+  #define YSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR_BB_K2                                                       (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define YSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR_BB_K2_SHIFT                                                 10
+  #define YSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR_BB_K2                                                    (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
+  #define YSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR_BB_K2_SHIFT                                              11
+  #define YSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR_BB_K2                                                   (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
+  #define YSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR_BB_K2_SHIFT                                             12
+#define YSEM_REG_INT_STS_CLR_1                                                                               0x150005cUL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define YSEM_REG_INT_STS_CLR_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5                                          (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
+  #define YSEM_REG_INT_STS_CLR_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5_SHIFT                                    0
+  #define YSEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5                                              (0x1<<1) // Fast external store FIFO error of Storm_A
+  #define YSEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT                                        1
+  #define YSEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_B_E5                                              (0x1<<2) // Fast external store FIFO error of Storm_B
+  #define YSEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_B_E5_SHIFT                                        2
+  #define YSEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_A_E5                                                (0x1<<3) // fast external load FIFO error of Storm_A
+  #define YSEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT                                          3
+  #define YSEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_B_E5                                                (0x1<<4) // fast external load FIFO error of Storm_B
+  #define YSEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_B_E5_SHIFT                                          4
+  #define YSEM_REG_INT_STS_CLR_1_FAST_RAM_WR_POP_ERROR_E5                                                    (0x1<<5) // Internal RAM pop error
+  #define YSEM_REG_INT_STS_CLR_1_FAST_RAM_WR_POP_ERROR_E5_SHIFT                                              5
+  #define YSEM_REG_INT_STS_CLR_1_FAST_RAM_RD_PUSH_ERROR_E5                                                   (0x1<<6) // Internal RAM write error
+  #define YSEM_REG_INT_STS_CLR_1_FAST_RAM_RD_PUSH_ERROR_E5_SHIFT                                             6
+  #define YSEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_A_E5                                                 (0x1<<7) // DRA RD FIFO error of Storm A
+  #define YSEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT                                           7
+  #define YSEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_B_E5                                                 (0x1<<8) // DRA RD FIFO error of Storm B
+  #define YSEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT                                           8
+  #define YSEM_REG_INT_STS_CLR_1_FAST_DRA_WR_POP_ERROR_A_E5                                                  (0x1<<9) // DRA RD FIFO error of Storm A
+  #define YSEM_REG_INT_STS_CLR_1_FAST_DRA_WR_POP_ERROR_A_E5_SHIFT                                            9
+  #define YSEM_REG_INT_STS_CLR_1_FAST_DRA_WR_POP_ERROR_B_E5                                                  (0x1<<10) // DRA RD FIFO error of Storm B
+  #define YSEM_REG_INT_STS_CLR_1_FAST_DRA_WR_POP_ERROR_B_E5_SHIFT                                            10
+  #define YSEM_REG_INT_STS_CLR_1_SEM_FAST_INVLD_ADDR_ERR_E5                                                  (0x1<<11) // Fast invalid address error
+  #define YSEM_REG_INT_STS_CLR_1_SEM_FAST_INVLD_ADDR_ERR_E5_SHIFT                                            11
+  #define YSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_A_E5                                                    (0x1<<12) // Storm A stack_uf_attn interrupt
+  #define YSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_A_E5_SHIFT                                              12
+  #define YSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_B_E5                                                    (0x1<<13) // Storm B stack_uf_attn interrupt
+  #define YSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_B_E5_SHIFT                                              13
+  #define YSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_A_E5                                                    (0x1<<14) // Storm A stack_of_attn interrupt
+  #define YSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_A_E5_SHIFT                                              14
+  #define YSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_B_E5                                                    (0x1<<15) // Storm B stack_of_attn interrupt
+  #define YSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_B_E5_SHIFT                                              15
+  #define YSEM_REG_INT_STS_CLR_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5                                             (0x1<<16) // Storm A ldst_addr_ovflw_attn interrupt
+  #define YSEM_REG_INT_STS_CLR_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5_SHIFT                                       16
+  #define YSEM_REG_INT_STS_CLR_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5                                             (0x1<<17) // Storm B ldst_addr_ovflw_attn interrupt
+  #define YSEM_REG_INT_STS_CLR_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5_SHIFT                                       17
+  #define YSEM_REG_INT_STS_CLR_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5                                          (0x1<<18) // Storm A non_aligned_access_attn interrupt
+  #define YSEM_REG_INT_STS_CLR_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5_SHIFT                                    18
+  #define YSEM_REG_INT_STS_CLR_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5                                          (0x1<<19) // Storm B non_aligned_access_attn interrupt
+  #define YSEM_REG_INT_STS_CLR_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5_SHIFT                                    19
+  #define YSEM_REG_INT_STS_CLR_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5                                            (0x1<<20) // Storm A division_by_zero_attn interrupt
+  #define YSEM_REG_INT_STS_CLR_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5_SHIFT                                      20
+  #define YSEM_REG_INT_STS_CLR_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5                                            (0x1<<21) // Storm B division_by_zero_attn interrupt
+  #define YSEM_REG_INT_STS_CLR_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5_SHIFT                                      21
+  #define YSEM_REG_INT_STS_CLR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5                                       (0x1<<22) // Storm A illegal_runtime_value_attn interrupt
+  #define YSEM_REG_INT_STS_CLR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5_SHIFT                                 22
+  #define YSEM_REG_INT_STS_CLR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5                                       (0x1<<23) // Storm B illegal_runtime_value_attn interrupt
+  #define YSEM_REG_INT_STS_CLR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5_SHIFT                                 23
+  #define YSEM_REG_INT_STS_CLR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5                                        (0x1<<24) // load request is made while previous is still active; not fully read, Storm A
+  #define YSEM_REG_INT_STS_CLR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5_SHIFT                                  24
+  #define YSEM_REG_INT_STS_CLR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5                                        (0x1<<25) // load request is made while previous is still active; not fully read, Storm B
+  #define YSEM_REG_INT_STS_CLR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5_SHIFT                                  25
+  #define YSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_OUT_ERROR_A_E5                                                 (0x1<<26) // Error in CAM_OUT fifo in cam block of STORM A
+  #define YSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_OUT_ERROR_A_E5_SHIFT                                           26
+  #define YSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_OUT_ERROR_B_E5                                                 (0x1<<27) // Error in CAM_OUT fifo in cam block of STORM B
+  #define YSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_OUT_ERROR_B_E5_SHIFT                                           27
+  #define YSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5                                             (0x1<<28) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define YSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5_SHIFT                                       28
+  #define YSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5                                             (0x1<<29) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define YSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5_SHIFT                                       29
+  #define YSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5                                             (0x1<<30) // Error in CAM_LSB_INP fifo in cam block of STORM A
+  #define YSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT                                       30
+  #define YSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5                                             (0x1<<31) // Error in CAM_LSB_INP fifo in cam block of STORM B.
+  #define YSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5_SHIFT                                       31
+  #define YSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_BB_K2                                                   (0x1<<0) // An underflow error was detected in the Storm stack.
+  #define YSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_BB_K2_SHIFT                                             0
+  #define YSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_BB_K2                                                   (0x1<<1) // An overflow error was detected in the Storm stack.
+  #define YSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT                                             1
+  #define YSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR_BB_K2                                                   (0x1<<2) // The Storm detected an illegal runtime value.
+  #define YSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR_BB_K2_SHIFT                                             2
+  #define YSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2                                                (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
+  #define YSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT                                          3
+  #define YSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR_BB_K2                                                 (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
+  #define YSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR_BB_K2_SHIFT                                           4
+  #define YSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR_BB_K2                                                 (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
+  #define YSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR_BB_K2_SHIFT                                           5
+  #define YSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR_BB_K2                                                  (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
+  #define YSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR_BB_K2_SHIFT                                            6
+  #define YSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR_BB_K2                                                  (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define YSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT                                            7
+  #define YSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR_BB_K2                                                     (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
+  #define YSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT                                               8
+  #define YSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR_BB_K2                                                       (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
+  #define YSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR_BB_K2_SHIFT                                                 9
+  #define YSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR_BB_K2                                                      (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define YSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR_BB_K2_SHIFT                                                10
+  #define YSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR_BB_K2                                                   (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
+  #define YSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR_BB_K2_SHIFT                                             11
+  #define YSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR_BB_K2                                                  (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
+  #define YSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR_BB_K2_SHIFT                                            12
+#define YSEM_REG_INT_STS_2_E5                                                                                0x1500060UL //Access:R    DataWidth:0x1f   // Multi Field Register.
+  #define YSEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5                                                 (0x1<<0) // Fast FIN FIFO error of Storm A.
+  #define YSEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5_SHIFT                                           0
+  #define YSEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5                                                 (0x1<<1) // Fast FIN FIFO error of Storm B
+  #define YSEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT                                           1
+  #define YSEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5                                               (0x1<<2) // Fast Debug FIFO error of Storm A
+  #define YSEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5_SHIFT                                         2
+  #define YSEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5                                               (0x1<<3) // Fast Debug FIFO error of Storm B
+  #define YSEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT                                         3
+  #define YSEM_REG_INT_STS_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5                                                (0x1<<4) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define YSEM_REG_INT_STS_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5_SHIFT                                          4
+  #define YSEM_REG_INT_STS_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5                                                (0x1<<5) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define YSEM_REG_INT_STS_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5_SHIFT                                          5
+  #define YSEM_REG_INT_STS_2_VFC_INTERRUPT_E5                                                                (0x1<<6) // interrupt from VFC block
+  #define YSEM_REG_INT_STS_2_VFC_INTERRUPT_E5_SHIFT                                                          6
+  #define YSEM_REG_INT_STS_2_MUX_RBC_VFC_FIFO_ERROR_E5                                                       (0x1<<7) // VFC FIFO error
+  #define YSEM_REG_INT_STS_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT                                                 7
+  #define YSEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_A_E5                                                    (0x1<<8) // Error in FOC error of Storm A.
+  #define YSEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT                                              8
+  #define YSEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_B_E5                                                    (0x1<<9) // Error in FOC error of Storm B.
+  #define YSEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_B_E5_SHIFT                                              9
+  #define YSEM_REG_INT_STS_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5                                                  (0x1<<10) // Invalid allocated thread request with partial FIN of Storm A.
+  #define YSEM_REG_INT_STS_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5_SHIFT                                            10
+  #define YSEM_REG_INT_STS_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5                                                  (0x1<<11) // Invalid allocated thread request with partial FIN of Storm B.
+  #define YSEM_REG_INT_STS_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5_SHIFT                                            11
+  #define YSEM_REG_INT_STS_2_CAM_RBC_INPUT_FIFO_ERROR_E5                                                     (0x1<<12) // Cam input FIFO error
+  #define YSEM_REG_INT_STS_2_CAM_RBC_INPUT_FIFO_ERROR_E5_SHIFT                                               12
+  #define YSEM_REG_INT_STS_2_ARB_RBC_FIFO_ERROR_A_E5                                                         (0x1<<13) // Pre-fetch FIFO error of Storm A.
+  #define YSEM_REG_INT_STS_2_ARB_RBC_FIFO_ERROR_A_E5_SHIFT                                                   13
+  #define YSEM_REG_INT_STS_2_ARB_RBC_FIFO_ERROR_B_E5                                                         (0x1<<14) // Pre-fetch FIFO error of Storm B.
+  #define YSEM_REG_INT_STS_2_ARB_RBC_FIFO_ERROR_B_E5_SHIFT                                                   14
+  #define YSEM_REG_INT_STS_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5                                                 (0x1<<15) // Lock is acquired more than maximum configured time.
+  #define YSEM_REG_INT_STS_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5_SHIFT                                           15
+  #define YSEM_REG_INT_STS_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                                  (0x1<<16) // Ilegal assetion commands towards lock block.
+  #define YSEM_REG_INT_STS_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5_SHIFT                                            16
+  #define YSEM_REG_INT_STS_2_LOCK_RBC_REQ_RELEASE_ERROR_E5                                                   (0x1<<17) // Error when trying to release a lock which is not acquired (key does not match any lock)
+  #define YSEM_REG_INT_STS_2_LOCK_RBC_REQ_RELEASE_ERROR_E5_SHIFT                                             17
+  #define YSEM_REG_INT_STS_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5                                                 (0x1<<18) // Trying to acquire a lock which is already acquired.
+  #define YSEM_REG_INT_STS_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5_SHIFT                                           18
+  #define YSEM_REG_INT_STS_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5                                                (0x1<<19) // Trying to relinquish a key which does not exist.
+  #define YSEM_REG_INT_STS_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5_SHIFT                                          19
+  #define YSEM_REG_INT_STS_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5                                                (0x1<<20) // A lock acquired requrest is issued when all locks are used.
+  #define YSEM_REG_INT_STS_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5_SHIFT                                          20
+  #define YSEM_REG_INT_STS_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5                                                (0x1<<21) // Error when both Storm are stalled due to lock block (may indicate a dead lock).
+  #define YSEM_REG_INT_STS_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5_SHIFT                                          21
+  #define YSEM_REG_INT_STS_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5                                            (0x1<<22) // Fin done with remainning allocated threads STORM_A.
+  #define YSEM_REG_INT_STS_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5_SHIFT                                      22
+  #define YSEM_REG_INT_STS_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5                                            (0x1<<23) // Fin done with remainning allocated threads STORM_B.
+  #define YSEM_REG_INT_STS_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5_SHIFT                                      23
+  #define YSEM_REG_INT_STS_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5                                            (0x1<<24) // Fin new thread request when no thread is allocated for handler of Storm A.
+  #define YSEM_REG_INT_STS_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5_SHIFT                                      24
+  #define YSEM_REG_INT_STS_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5                                            (0x1<<25) // Fin new thread request when no thread is allocated for handler of Storm B.
+  #define YSEM_REG_INT_STS_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5_SHIFT                                      25
+  #define YSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5                                      (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same range.
+  #define YSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5_SHIFT                                26
+  #define YSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5                                      (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same range.
+  #define YSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5_SHIFT                                27
+  #define YSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5                                         (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
+  #define YSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5_SHIFT                                   28
+  #define YSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5                                         (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
+  #define YSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5_SHIFT                                   29
+  #define YSEM_REG_INT_STS_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5                                          (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
+  #define YSEM_REG_INT_STS_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT                                    30
+#define YSEM_REG_INT_MASK_2_E5                                                                               0x1500064UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define YSEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5                                                (0x1<<0) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.RD_RBC_FAST_FIN_FIFO_ERROR_A .
+  #define YSEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5_SHIFT                                          0
+  #define YSEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5                                                (0x1<<1) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.RD_RBC_FAST_FIN_FIFO_ERROR_B .
+  #define YSEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT                                          1
+  #define YSEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5                                              (0x1<<2) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.SYNC_RBC_FAST_DBG_PUSH_ERROR_A .
+  #define YSEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5_SHIFT                                        2
+  #define YSEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5                                              (0x1<<3) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.SYNC_RBC_FAST_DBG_PUSH_ERROR_B .
+  #define YSEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT                                        3
+  #define YSEM_REG_INT_MASK_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5                                               (0x1<<4) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.CAM_RBC_FAST_MSB2_INP_ERROR_A .
+  #define YSEM_REG_INT_MASK_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5_SHIFT                                         4
+  #define YSEM_REG_INT_MASK_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5                                               (0x1<<5) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.CAM_RBC_FAST_MSB2_INP_ERROR_B .
+  #define YSEM_REG_INT_MASK_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5_SHIFT                                         5
+  #define YSEM_REG_INT_MASK_2_VFC_INTERRUPT_E5                                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.VFC_INTERRUPT .
+  #define YSEM_REG_INT_MASK_2_VFC_INTERRUPT_E5_SHIFT                                                         6
+  #define YSEM_REG_INT_MASK_2_MUX_RBC_VFC_FIFO_ERROR_E5                                                      (0x1<<7) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.MUX_RBC_VFC_FIFO_ERROR .
+  #define YSEM_REG_INT_MASK_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT                                                7
+  #define YSEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_A_E5                                                   (0x1<<8) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.FIN_RBC_INVLD_FOC_ERROR_A .
+  #define YSEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT                                             8
+  #define YSEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_B_E5                                                   (0x1<<9) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.FIN_RBC_INVLD_FOC_ERROR_B .
+  #define YSEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_B_E5_SHIFT                                             9
+  #define YSEM_REG_INT_MASK_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5                                                 (0x1<<10) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.FIN_RBC_INVLD_ALLOC_ERROR_A .
+  #define YSEM_REG_INT_MASK_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5_SHIFT                                           10
+  #define YSEM_REG_INT_MASK_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5                                                 (0x1<<11) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.FIN_RBC_INVLD_ALLOC_ERROR_B .
+  #define YSEM_REG_INT_MASK_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5_SHIFT                                           11
+  #define YSEM_REG_INT_MASK_2_CAM_RBC_INPUT_FIFO_ERROR_E5                                                    (0x1<<12) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.CAM_RBC_INPUT_FIFO_ERROR .
+  #define YSEM_REG_INT_MASK_2_CAM_RBC_INPUT_FIFO_ERROR_E5_SHIFT                                              12
+  #define YSEM_REG_INT_MASK_2_ARB_RBC_FIFO_ERROR_A_E5                                                        (0x1<<13) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.ARB_RBC_FIFO_ERROR_A .
+  #define YSEM_REG_INT_MASK_2_ARB_RBC_FIFO_ERROR_A_E5_SHIFT                                                  13
+  #define YSEM_REG_INT_MASK_2_ARB_RBC_FIFO_ERROR_B_E5                                                        (0x1<<14) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.ARB_RBC_FIFO_ERROR_B .
+  #define YSEM_REG_INT_MASK_2_ARB_RBC_FIFO_ERROR_B_E5_SHIFT                                                  14
+  #define YSEM_REG_INT_MASK_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5                                                (0x1<<15) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.LOCK_RBC_REQ_MAX_STALL_ERROR .
+  #define YSEM_REG_INT_MASK_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5_SHIFT                                          15
+  #define YSEM_REG_INT_MASK_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                                 (0x1<<16) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.LOCK_RBC_REQ_CMD_RATE_ERROR .
+  #define YSEM_REG_INT_MASK_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5_SHIFT                                           16
+  #define YSEM_REG_INT_MASK_2_LOCK_RBC_REQ_RELEASE_ERROR_E5                                                  (0x1<<17) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.LOCK_RBC_REQ_RELEASE_ERROR .
+  #define YSEM_REG_INT_MASK_2_LOCK_RBC_REQ_RELEASE_ERROR_E5_SHIFT                                            17
+  #define YSEM_REG_INT_MASK_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5                                                (0x1<<18) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.LOCK_RBC_REQ_REDUNDENT_ERROR .
+  #define YSEM_REG_INT_MASK_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5_SHIFT                                          18
+  #define YSEM_REG_INT_MASK_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5                                               (0x1<<19) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.LOCK_RBC_REQ_RELINQUISH_ERROR .
+  #define YSEM_REG_INT_MASK_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5_SHIFT                                         19
+  #define YSEM_REG_INT_MASK_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5                                               (0x1<<20) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.LOCK_RBC_REQ_STALL_FULL_ERROR .
+  #define YSEM_REG_INT_MASK_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5_SHIFT                                         20
+  #define YSEM_REG_INT_MASK_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5                                               (0x1<<21) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.LOCK_RBC_REQ_DUAL_STALL_ERROR .
+  #define YSEM_REG_INT_MASK_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5_SHIFT                                         21
+  #define YSEM_REG_INT_MASK_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5                                           (0x1<<22) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A .
+  #define YSEM_REG_INT_MASK_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5_SHIFT                                     22
+  #define YSEM_REG_INT_MASK_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5                                           (0x1<<23) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B .
+  #define YSEM_REG_INT_MASK_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5_SHIFT                                     23
+  #define YSEM_REG_INT_MASK_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5                                           (0x1<<24) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.DRA_INT_GRC_NON_FREE_THRD_ERROR_A .
+  #define YSEM_REG_INT_MASK_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5_SHIFT                                     24
+  #define YSEM_REG_INT_MASK_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5                                           (0x1<<25) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.DRA_INT_GRC_NON_FREE_THRD_ERROR_B .
+  #define YSEM_REG_INT_MASK_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5_SHIFT                                     25
+  #define YSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5                                     (0x1<<26) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A .
+  #define YSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5_SHIFT                               26
+  #define YSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5                                     (0x1<<27) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B .
+  #define YSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5_SHIFT                               27
+  #define YSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5                                        (0x1<<28) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A .
+  #define YSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5_SHIFT                                  28
+  #define YSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5                                        (0x1<<29) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B .
+  #define YSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5_SHIFT                                  29
+  #define YSEM_REG_INT_MASK_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5                                         (0x1<<30) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_2.SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR .
+  #define YSEM_REG_INT_MASK_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT                                   30
+#define YSEM_REG_INT_STS_WR_2_E5                                                                             0x1500068UL //Access:WR   DataWidth:0x1f   // Multi Field Register.
+  #define YSEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5                                              (0x1<<0) // Fast FIN FIFO error of Storm A.
+  #define YSEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5_SHIFT                                        0
+  #define YSEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5                                              (0x1<<1) // Fast FIN FIFO error of Storm B
+  #define YSEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT                                        1
+  #define YSEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5                                            (0x1<<2) // Fast Debug FIFO error of Storm A
+  #define YSEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5_SHIFT                                      2
+  #define YSEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5                                            (0x1<<3) // Fast Debug FIFO error of Storm B
+  #define YSEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT                                      3
+  #define YSEM_REG_INT_STS_WR_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5                                             (0x1<<4) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define YSEM_REG_INT_STS_WR_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5_SHIFT                                       4
+  #define YSEM_REG_INT_STS_WR_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5                                             (0x1<<5) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define YSEM_REG_INT_STS_WR_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5_SHIFT                                       5
+  #define YSEM_REG_INT_STS_WR_2_VFC_INTERRUPT_E5                                                             (0x1<<6) // interrupt from VFC block
+  #define YSEM_REG_INT_STS_WR_2_VFC_INTERRUPT_E5_SHIFT                                                       6
+  #define YSEM_REG_INT_STS_WR_2_MUX_RBC_VFC_FIFO_ERROR_E5                                                    (0x1<<7) // VFC FIFO error
+  #define YSEM_REG_INT_STS_WR_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT                                              7
+  #define YSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5                                                 (0x1<<8) // Error in FOC error of Storm A.
+  #define YSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT                                           8
+  #define YSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_B_E5                                                 (0x1<<9) // Error in FOC error of Storm B.
+  #define YSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_B_E5_SHIFT                                           9
+  #define YSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5                                               (0x1<<10) // Invalid allocated thread request with partial FIN of Storm A.
+  #define YSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5_SHIFT                                         10
+  #define YSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5                                               (0x1<<11) // Invalid allocated thread request with partial FIN of Storm B.
+  #define YSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5_SHIFT                                         11
+  #define YSEM_REG_INT_STS_WR_2_CAM_RBC_INPUT_FIFO_ERROR_E5                                                  (0x1<<12) // Cam input FIFO error
+  #define YSEM_REG_INT_STS_WR_2_CAM_RBC_INPUT_FIFO_ERROR_E5_SHIFT                                            12
+  #define YSEM_REG_INT_STS_WR_2_ARB_RBC_FIFO_ERROR_A_E5                                                      (0x1<<13) // Pre-fetch FIFO error of Storm A.
+  #define YSEM_REG_INT_STS_WR_2_ARB_RBC_FIFO_ERROR_A_E5_SHIFT                                                13
+  #define YSEM_REG_INT_STS_WR_2_ARB_RBC_FIFO_ERROR_B_E5                                                      (0x1<<14) // Pre-fetch FIFO error of Storm B.
+  #define YSEM_REG_INT_STS_WR_2_ARB_RBC_FIFO_ERROR_B_E5_SHIFT                                                14
+  #define YSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5                                              (0x1<<15) // Lock is acquired more than maximum configured time.
+  #define YSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5_SHIFT                                        15
+  #define YSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                               (0x1<<16) // Ilegal assetion commands towards lock block.
+  #define YSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5_SHIFT                                         16
+  #define YSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_RELEASE_ERROR_E5                                                (0x1<<17) // Error when trying to release a lock which is not acquired (key does not match any lock)
+  #define YSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_RELEASE_ERROR_E5_SHIFT                                          17
+  #define YSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5                                              (0x1<<18) // Trying to acquire a lock which is already acquired.
+  #define YSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5_SHIFT                                        18
+  #define YSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5                                             (0x1<<19) // Trying to relinquish a key which does not exist.
+  #define YSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5_SHIFT                                       19
+  #define YSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5                                             (0x1<<20) // A lock acquired requrest is issued when all locks are used.
+  #define YSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5_SHIFT                                       20
+  #define YSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5                                             (0x1<<21) // Error when both Storm are stalled due to lock block (may indicate a dead lock).
+  #define YSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5_SHIFT                                       21
+  #define YSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5                                         (0x1<<22) // Fin done with remainning allocated threads STORM_A.
+  #define YSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5_SHIFT                                   22
+  #define YSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5                                         (0x1<<23) // Fin done with remainning allocated threads STORM_B.
+  #define YSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5_SHIFT                                   23
+  #define YSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5                                         (0x1<<24) // Fin new thread request when no thread is allocated for handler of Storm A.
+  #define YSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5_SHIFT                                   24
+  #define YSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5                                         (0x1<<25) // Fin new thread request when no thread is allocated for handler of Storm B.
+  #define YSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5_SHIFT                                   25
+  #define YSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5                                   (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same range.
+  #define YSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5_SHIFT                             26
+  #define YSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5                                   (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same range.
+  #define YSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5_SHIFT                             27
+  #define YSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5                                      (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
+  #define YSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5_SHIFT                                28
+  #define YSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5                                      (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
+  #define YSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5_SHIFT                                29
+  #define YSEM_REG_INT_STS_WR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5                                       (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
+  #define YSEM_REG_INT_STS_WR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT                                 30
+#define YSEM_REG_INT_STS_CLR_2_E5                                                                            0x150006cUL //Access:RC   DataWidth:0x1f   // Multi Field Register.
+  #define YSEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5                                             (0x1<<0) // Fast FIN FIFO error of Storm A.
+  #define YSEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5_SHIFT                                       0
+  #define YSEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5                                             (0x1<<1) // Fast FIN FIFO error of Storm B
+  #define YSEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT                                       1
+  #define YSEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5                                           (0x1<<2) // Fast Debug FIFO error of Storm A
+  #define YSEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5_SHIFT                                     2
+  #define YSEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5                                           (0x1<<3) // Fast Debug FIFO error of Storm B
+  #define YSEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT                                     3
+  #define YSEM_REG_INT_STS_CLR_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5                                            (0x1<<4) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define YSEM_REG_INT_STS_CLR_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5_SHIFT                                      4
+  #define YSEM_REG_INT_STS_CLR_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5                                            (0x1<<5) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define YSEM_REG_INT_STS_CLR_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5_SHIFT                                      5
+  #define YSEM_REG_INT_STS_CLR_2_VFC_INTERRUPT_E5                                                            (0x1<<6) // interrupt from VFC block
+  #define YSEM_REG_INT_STS_CLR_2_VFC_INTERRUPT_E5_SHIFT                                                      6
+  #define YSEM_REG_INT_STS_CLR_2_MUX_RBC_VFC_FIFO_ERROR_E5                                                   (0x1<<7) // VFC FIFO error
+  #define YSEM_REG_INT_STS_CLR_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT                                             7
+  #define YSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5                                                (0x1<<8) // Error in FOC error of Storm A.
+  #define YSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT                                          8
+  #define YSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_B_E5                                                (0x1<<9) // Error in FOC error of Storm B.
+  #define YSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_B_E5_SHIFT                                          9
+  #define YSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5                                              (0x1<<10) // Invalid allocated thread request with partial FIN of Storm A.
+  #define YSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5_SHIFT                                        10
+  #define YSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5                                              (0x1<<11) // Invalid allocated thread request with partial FIN of Storm B.
+  #define YSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5_SHIFT                                        11
+  #define YSEM_REG_INT_STS_CLR_2_CAM_RBC_INPUT_FIFO_ERROR_E5                                                 (0x1<<12) // Cam input FIFO error
+  #define YSEM_REG_INT_STS_CLR_2_CAM_RBC_INPUT_FIFO_ERROR_E5_SHIFT                                           12
+  #define YSEM_REG_INT_STS_CLR_2_ARB_RBC_FIFO_ERROR_A_E5                                                     (0x1<<13) // Pre-fetch FIFO error of Storm A.
+  #define YSEM_REG_INT_STS_CLR_2_ARB_RBC_FIFO_ERROR_A_E5_SHIFT                                               13
+  #define YSEM_REG_INT_STS_CLR_2_ARB_RBC_FIFO_ERROR_B_E5                                                     (0x1<<14) // Pre-fetch FIFO error of Storm B.
+  #define YSEM_REG_INT_STS_CLR_2_ARB_RBC_FIFO_ERROR_B_E5_SHIFT                                               14
+  #define YSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5                                             (0x1<<15) // Lock is acquired more than maximum configured time.
+  #define YSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5_SHIFT                                       15
+  #define YSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                              (0x1<<16) // Ilegal assetion commands towards lock block.
+  #define YSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5_SHIFT                                        16
+  #define YSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_RELEASE_ERROR_E5                                               (0x1<<17) // Error when trying to release a lock which is not acquired (key does not match any lock)
+  #define YSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_RELEASE_ERROR_E5_SHIFT                                         17
+  #define YSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5                                             (0x1<<18) // Trying to acquire a lock which is already acquired.
+  #define YSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5_SHIFT                                       18
+  #define YSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5                                            (0x1<<19) // Trying to relinquish a key which does not exist.
+  #define YSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5_SHIFT                                      19
+  #define YSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5                                            (0x1<<20) // A lock acquired requrest is issued when all locks are used.
+  #define YSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5_SHIFT                                      20
+  #define YSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5                                            (0x1<<21) // Error when both Storm are stalled due to lock block (may indicate a dead lock).
+  #define YSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5_SHIFT                                      21
+  #define YSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5                                        (0x1<<22) // Fin done with remainning allocated threads STORM_A.
+  #define YSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5_SHIFT                                  22
+  #define YSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5                                        (0x1<<23) // Fin done with remainning allocated threads STORM_B.
+  #define YSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5_SHIFT                                  23
+  #define YSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5                                        (0x1<<24) // Fin new thread request when no thread is allocated for handler of Storm A.
+  #define YSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5_SHIFT                                  24
+  #define YSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5                                        (0x1<<25) // Fin new thread request when no thread is allocated for handler of Storm B.
+  #define YSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5_SHIFT                                  25
+  #define YSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5                                  (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same range.
+  #define YSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5_SHIFT                            26
+  #define YSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5                                  (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same range.
+  #define YSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5_SHIFT                            27
+  #define YSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5                                     (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
+  #define YSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5_SHIFT                               28
+  #define YSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5                                     (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
+  #define YSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5_SHIFT                               29
+  #define YSEM_REG_INT_STS_CLR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5                                      (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
+  #define YSEM_REG_INT_STS_CLR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT                                30
+#define YSEM_REG_PRTY_MASK                                                                                   0x15000ccUL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define YSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR                                                            (0x1<<0) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS.VFC_RBC_PARITY_ERROR .
+  #define YSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR_SHIFT                                                      0
+  #define YSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR                                                           (0x1<<1) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS.STORM_RF_PARITY_ERROR .
+  #define YSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR_SHIFT                                                     1
+  #define YSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR                                                            (0x1<<2) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS.REG_GEN_PARITY_ERROR .
+  #define YSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR_SHIFT                                                      2
+#define YSEM_REG_PRTY_MASK_H_0_BB_K2                                                                         0x1500204UL //Access:RW   DataWidth:0x7    // Multi Field Register.
+  #define YSEM_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT_BB_K2                                                 (0x1<<0) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS_H_0.MEM006_I_ECC_0_RF_INT .
+  #define YSEM_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT_BB_K2_SHIFT                                           0
+  #define YSEM_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT_BB_K2                                                 (0x1<<1) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS_H_0.MEM006_I_ECC_1_RF_INT .
+  #define YSEM_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT_BB_K2_SHIFT                                           1
+  #define YSEM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2                                                     (0x1<<2) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
+  #define YSEM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT                                               2
+  #define YSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                     (0x1<<3) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define YSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                               3
+  #define YSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                     (0x1<<4) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define YSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                               4
+  #define YSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                     (0x1<<5) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define YSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                               5
+  #define YSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                     (0x1<<6) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define YSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                               6
+#define YSEM_REG_MEM_ECC_ENABLE_0_BB_K2                                                                      0x1500210UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define YSEM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_0_EN_BB_K2                                                  (0x1<<0) // Enable ECC for memory ecc instance ysem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.YSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_ysem.i_ecc_0 in module sem_slow_pas_buf_ram_ysem
+  #define YSEM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_0_EN_BB_K2_SHIFT                                            0
+  #define YSEM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_1_EN_BB_K2                                                  (0x1<<1) // Enable ECC for memory ecc instance ysem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.YSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_ysem.i_ecc_1 in module sem_slow_pas_buf_ram_ysem
+  #define YSEM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_1_EN_BB_K2_SHIFT                                            1
+#define YSEM_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                 0x1500214UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define YSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_0_PRTY_BB_K2                                           (0x1<<0) // Set parity only for memory ecc instance ysem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.YSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_ysem.i_ecc_0 in module sem_slow_pas_buf_ram_ysem
+  #define YSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_0_PRTY_BB_K2_SHIFT                                     0
+  #define YSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_1_PRTY_BB_K2                                           (0x1<<1) // Set parity only for memory ecc instance ysem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.YSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_ysem.i_ecc_1 in module sem_slow_pas_buf_ram_ysem
+  #define YSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_1_PRTY_BB_K2_SHIFT                                     1
+#define YSEM_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                             0x1500218UL //Access:RC   DataWidth:0x2    // Multi Field Register.
+  #define YSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_0_CORRECT_BB_K2                                    (0x1<<0) // Record if a correctable error occurred on memory ecc instance ysem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.YSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_ysem.i_ecc_0 in module sem_slow_pas_buf_ram_ysem
+  #define YSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_0_CORRECT_BB_K2_SHIFT                              0
+  #define YSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_1_CORRECT_BB_K2                                    (0x1<<1) // Record if a correctable error occurred on memory ecc instance ysem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.YSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_ysem.i_ecc_1 in module sem_slow_pas_buf_ram_ysem
+  #define YSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_1_CORRECT_BB_K2_SHIFT                              1
+#define YSEM_REG_MEM_ECC_EVENTS_BB_K2                                                                        0x150021cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define YSEM_REG_ARB_CYCLE_SIZE_BB_K2                                                                        0x1500400UL //Access:RW   DataWidth:0x5    // The number of time_slots in the arbitration cycle.
+#define YSEM_REG_VF_ERROR                                                                                    0x1500408UL //Access:WR   DataWidth:0x1    // This VF-split register provides read/clear access to the VF error received from the SDM for a DMA transfer. Reading this register will return the VF Error for value for the corresponding VF. Writing a 1 to this register will clear the error for the corresponding VF.
+#define YSEM_REG_PF_ERROR                                                                                    0x150040cUL //Access:WR   DataWidth:0x1    // This PF-split register provides read/clear access to the PF error received from the SDM for a DMA transfer. Reading this register will return the PF Error for value for the corresponding PF. Writing a 1 to this register will clear the error for the corresponding PF.
+#define YSEM_REG_VF_ERR_VECTOR                                                                               0x1500420UL //Access:WB_R DataWidth:0xf0   // This read-only register provides a vector of bits having an error indication per VF where the Bit position corresponds to the VFID.
+#define YSEM_REG_VF_ERR_VECTOR_SIZE_BB                                                                       4
+#define YSEM_REG_VF_ERR_VECTOR_SIZE_K2_E5                                                                    8
+#define YSEM_REG_PF_ERR_VECTOR                                                                               0x1500440UL //Access:R    DataWidth:0x10   // This read-only register provides a vector of bits having an error indication per PF where the Bit position corresponds to the PFID.
+#define YSEM_REG_CLEAR_STALL                                                                                 0x1500444UL //Access:RW   DataWidth:0x1    // Clear stall signal sent from local storm to external storms.
+#define YSEM_REG_EXCEPTION_INT                                                                               0x1500448UL //Access:RW   DataWidth:0x10   // Provides a default PRAM address to be used for the handler in the event that the PRAM address retrieved from the interrupt table is out of range with regard to the actual PRAM size provided in the SEMI instance.
+#define YSEM_REG_EXT_STORE_FREE_ENTRIES_BB_K2                                                                0x150044cUL //Access:R    DataWidth:0x6    // Number of free entries in the external STORE sync FIFO.
+#define YSEM_REG_GPI_DATA_A_E5                                                                               0x1500450UL //Access:R    DataWidth:0x20   // Used to read the GPI input signals of Storm A.
+#define YSEM_REG_GPI_DATA_BB_K2                                                                              0x1500450UL //Access:R    DataWidth:0x20   // Used to read the GPI input signals.
+#define YSEM_REG_GPRE_SAMP_PERIOD_BB_K2                                                                      0x1500454UL //Access:RW   DataWidth:0x4    // Defines the number of system clocks from one sample of GPRE sync data and the next.
+#define YSEM_REG_ALLOW_LP_SLEEP_THRD                                                                         0x1500458UL //Access:RW   DataWidth:0x1    // When set, this bit is used to allow low-power mode to be activated while threads are sleeping in the passive buffer, as long as the SEMI/Storm remains idle.
+#define YSEM_REG_ECO_RESERVED                                                                                0x150045cUL //Access:RW   DataWidth:0x20   // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
+#define YSEM_REG_PB_WR_SDM_DMA_MODE_E5                                                                       0x1500460UL //Access:RW   DataWidth:0x2    // This register can set the mode of the SDM DMA write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use regardless write mode. 11 - Disable write mode.
+#define YSEM_REG_PB_WR_DRA_RD_CUT_THROUGH_MODE_E5                                                            0x1500464UL //Access:RW   DataWidth:0x1    // This register set the DRA RD block cut through mode in which write to a thread address section passive buffer may occur simultaneously with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut through mode active.
+#define YSEM_REG_GPI_DATA_B_E5                                                                               0x1500468UL //Access:R    DataWidth:0x20   // Used to read the GPI input signals of Storm B.
+#define YSEM_REG_FIC_FIFO_BB_K2                                                                              0x1500580UL //Access:WB_R DataWidth:0x80   // Used for debugging to read/write to/from the FIC FIFOs. The address selects which FIFO should be accessed.
+#define YSEM_REG_FIC_FIFO_SIZE                                                                               8
+#define YSEM_REG_FIC_MIN_MSG_BB_K2                                                                           0x1500600UL //Access:RW   DataWidth:0x6    // Per-FIC interface register array defines minimum number of cycles in the FIC interfaces after which the message can be sent to the passive register_file.
+#define YSEM_REG_FIC_MIN_MSG_SIZE                                                                            2
+#define YSEM_REG_FIC_EMPTY_CT_MODE_BB_K2                                                                     0x1500620UL //Access:RW   DataWidth:0x1    // When set, enables the "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require that the available ("go") counter is non-zero before making a transfer request to the DRA arbiter and starting a transfer.
+#define YSEM_REG_FIC_EMPTY_CT_CNT_BB_K2                                                                      0x1500624UL //Access:RC   DataWidth:0x18   // Statistics counter used to count the number of FIC messages that have been received on any FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
+#define YSEM_REG_FOC_CREDIT                                                                                  0x1500680UL //Access:RW   DataWidth:0x8    // Array of registers provides the initial credits on each of the associatef FOC interfaces. Reading from this register provides the current FOR credit value.
+#define YSEM_REG_FOC_CREDIT_SIZE                                                                             6
+#define YSEM_REG_FULL_FOC_DRA_STRT_EN_BB_K2                                                                  0x15006c0UL //Access:RW   DataWidth:0x1    // When set, this bit allows the DRA read operation to start even when there are not enough credits on all the participating FOC interfaces to complete the entire transaction. The transfer will stall only when a transfer cycle is reached in which there are no interface credits, at which time the DRA transfer will remain stalled until the FOC destination(s) has at least a single credit. When this configuration is cleared, the DRA read transfer will not begin until there are enough credits on all the participating FOC interfaces for the entire transfer.
+#define YSEM_REG_FIN_COMMAND_BB_K2                                                                           0x1500700UL //Access:WB_R DataWidth:0x164  // Last fin command that was read from fifo. Its spelling in FIN_FIFO register.
+#define YSEM_REG_FIN_COMMAND_SIZE                                                                            16
+#define YSEM_REG_FIN_FIFO_BB_K2                                                                              0x1500800UL //Access:WB_R DataWidth:0x164  // READ ONLY FOR DEBUGGING! [5:0]   start_rp_foc3; [11:6] start_rp_foc2;  [17:12]   start_rp_foc1; [23:18] start_rp_foc0;  [29:24]   end_rp_foc3; [35:30] end_rp_foc2; [41:36]   end_rp_foc1; [47:42]   end_rp_foc0; [53:48]   lowest rp; [59:54]   highest rp; [65:60]   store start rp; [71:66]   store end rp; [77:72]   load start rp; [83:78]   load end rp; [85:84]   priority; [101:86]  pram address; [102] pas; [103] foc3; [104] foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:0] is valid.
+#define YSEM_REG_FIN_FIFO_SIZE                                                                               16
+#define YSEM_REG_INVLD_PAS_WR_EN_BB_K2                                                                       0x1500900UL //Access:RW   DataWidth:0x1    // When set, an attempt to write to the passive buffer over the external passive interface will be enabled even if the partition being written is owned by a thread whose valid bit is not set. Otherwise if cleared, the transfer will be stalled.
+#define YSEM_REG_ARBITER_REQUEST_BB_K2                                                                       0x1500980UL //Access:R    DataWidth:0x5    // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2.
+#define YSEM_REG_ARBITER_SELECT_BB_K2                                                                        0x1500984UL //Access:R    DataWidth:0x5    // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2.
+#define YSEM_REG_ARBITER_SLOT_BB_K2                                                                          0x1500988UL //Access:R    DataWidth:0x5    // Dra arbiter last slot.
+#define YSEM_REG_ARB_AS_DEF_BB_K2                                                                            0x1500a00UL //Access:RW   DataWidth:0x3    // Two-dimensional register array is used to define each of four arbitration schemes used by the main DRA arbiter. For this, bits 4:3 of the offset are used to select the arbitration scheme 0-3. Bits 2:0 of the offset are used to define the five priority sources for the selected scheme, where for each priority (0-4), an arbiter source is assigned. Valid values for these configurations are the source enumerations, where FIC0=0x0, FIC1=0x1, wake priority0=0x2, wake priority1=0x3 and wake priority2=0x4. Note that there are holes in the indirect offset address which always return zero when read. These exist at offsets 0x5-0x7, 0xd-0xf, 0x15-0x17 and 0x1d-0x1f.
+#define YSEM_REG_ARB_AS_DEF_SIZE                                                                             32
+#define YSEM_REG_ARB_TS_AS_BB_K2                                                                             0x1500a80UL //Access:RW   DataWidth:0x2    // Register array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
+#define YSEM_REG_ARB_TS_AS_SIZE                                                                              20
+#define YSEM_REG_NUM_OF_THREADS                                                                              0x1500b00UL //Access:R    DataWidth:0x8    // The number of currently free threads (in invalid state).
+#define YSEM_REG_THREAD_ERROR_LOW_E5                                                                         0x1500b04UL //Access:R    DataWidth:0x20   // Thread error low indication. Represents threads 31 -0
+#define YSEM_REG_THREAD_ERROR_BB_K2                                                                          0x1500b04UL //Access:R    DataWidth:0xe    // Thread error indication.
+#define YSEM_REG_THREAD_RDY_BB_K2                                                                            0x1500b08UL //Access:R    DataWidth:0xe    // Thread ready indication.
+#define YSEM_REG_THREAD_SET_NUM                                                                              0x1500b0cUL //Access:W    DataWidth:0x6    // Thread ID. Write thread ID will set ready indication for this thread ID.
+#define YSEM_REG_THREAD_VALID_BB_K2                                                                          0x1500b10UL //Access:R    DataWidth:0xe    // Valid sleeping threads.
+#define YSEM_REG_THREADS_LIST_BB_K2                                                                          0x1500b14UL //Access:RW   DataWidth:0xe    // List of free threads.
+#define YSEM_REG_THREAD_NUMBER_E5                                                                            0x1500b18UL //Access:RW   DataWidth:0x8    // Defines the maixmum number of supported threads in SEMI.
+#define YSEM_REG_THREAD_ERROR_HIGH_E5                                                                        0x1500b1cUL //Access:R    DataWidth:0x18   // Thread error high indication. Represents threads  55-32
+#define YSEM_REG_FOC_MIN_MESSAGE_CREDIT_E5                                                                   0x1500b40UL //Access:RW   DataWidth:0x8    // This field defines for each FOC the minimum message reuired for the FOC transfer to start.
+#define YSEM_REG_FOC_MIN_MESSAGE_CREDIT_SIZE                                                                 6
+#define YSEM_REG_ORDER_HEAD_BB_K2                                                                            0x1500c00UL //Access:RW   DataWidth:0x4    // This (indirect) register array of registers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
+#define YSEM_REG_ORDER_HEAD_SIZE                                                                             16
+#define YSEM_REG_ORDER_TAIL_BB_K2                                                                            0x1500c80UL //Access:RW   DataWidth:0x4    // This (indirect) register array of registers provides read/write access to the tail pointers assigned to each of the thread ordering queues.
+#define YSEM_REG_ORDER_TAIL_SIZE                                                                             16
+#define YSEM_REG_ORDER_EMPTY_BB_K2                                                                           0x1500d00UL //Access:RW   DataWidth:0x1    // This vector provides read-only access to the empty bit assigned to each of the thread ordering queues.
+#define YSEM_REG_ORDER_EMPTY_SIZE                                                                            16
+#define YSEM_REG_ORDER_LL_REG_BB_K2                                                                          0x1500d80UL //Access:RW   DataWidth:0x4    // This array of registers provides read/write access to each entry of the linked-list array of the thread-ordering queue. Because the actual depth is based on the number of threads supported by the design, which is a Verilog parameter, a 64-entry window is reserved in the register address space. The valid entries start at the base of the window and extend through the number of threads supported. The value in each indirect register contains linked-list pointer to the next thread in the associated queue..
+#define YSEM_REG_ORDER_LL_REG_SIZE                                                                           14
+#define YSEM_REG_ORDER_POP_EN_BB_K2                                                                          0x1500e00UL //Access:RW   DataWidth:0xe    // Provides access to the thread ordering queue pop-enable vector.
+#define YSEM_REG_ORDER_WAKE_EN_BB_K2                                                                         0x1500e08UL //Access:RW   DataWidth:0xe    // Provides access to the thread ordering queue wake-enable vector.
+#define YSEM_REG_PF_NUM_ORDER_BASE_BB_K2                                                                     0x1500e10UL //Access:RW   DataWidth:0x4    // This field defines the base value for the ordering queue selection when the PFNum is chosen to control this selection. The value of this register is added to PFNum and the result is used to select one of 16 ordering queues.
+#define YSEM_REG_DBG_ALM_FULL                                                                                0x1501000UL //Access:RW   DataWidth:0x6    // Almost full for slow debug fifo.
+#define YSEM_REG_PASSIVE_ALM_FULL                                                                            0x1501004UL //Access:RW   DataWidth:0x5    // The number of free entries in the sync FIFO between the external HW and the passive buffer; below which the PassiveFull is asserted.
+#define YSEM_REG_SYNC_DRA_WR_ALM_FULL_BB_K2                                                                  0x1501008UL //Access:RW   DataWidth:0x5    // Almost full for sync dra_wr fifo (data from DRA to STORM).
+#define YSEM_REG_SYNC_RAM_WR_ALM_FULL                                                                        0x150100cUL //Access:RW   DataWidth:0x6    // Almost full for sync ram_wr fifo.
+#define YSEM_REG_SYNC_FOC_FIFO_WR_ALM_FULL_E5                                                                0x1501010UL //Access:RW   DataWidth:0x4    // Almost full for indication for FOC Sync FIFO.
+#define YSEM_REG_SYNC_SDM_READY_FIFO_WR_ALM_FULL_E5                                                          0x1501014UL //Access:RW   DataWidth:0x3    // Almost full for indication for SDM READY FIFO.
+#define YSEM_REG_SYNC_SDM_INC_FIFO_WR_ALM_FULL_E5                                                            0x1501018UL //Access:RW   DataWidth:0x3    // Almost full for indication for SDM Counter Increment FIFO.
+#define YSEM_REG_STALL_ON_INT_E5                                                                             0x150101cUL //Access:RW   DataWidth:0x2    // 00 - No stall. 01 - Both cluster Stroms will be stalled on any unmasked error occurrence. 10 - All Stroms will be stalled on any unmasked error occurrence.
+#define YSEM_REG_FIC0_A_MAX_THRDS_E5                                                                         0x1501020UL //Access:RW   DataWidth:0x6    // Defines the maximum supported threads that may be contained in FIC0 A queue. If FIC0 message  is received and number of threads equals to the configured value, FIC interface will be stalled untill number of queue threads drops below configured vlaue.
+#define YSEM_REG_FIC0_X_MAX_THRDS_E5                                                                         0x1501024UL //Access:RW   DataWidth:0x6    // Defines the maximum supported threads that may be contained in FIC0 X queue. If FIC0 message  is received and number of threads equals to the configured value, FIC interface will be stalled untill number of queue threads drops below configured vlaue.
+#define YSEM_REG_FIC0_B_MAX_THRDS_E5                                                                         0x1501028UL //Access:RW   DataWidth:0x6    // Defines the maximum supported threads that may be contained in FIC0 B queue. If FIC0 message  is received and number of threads equals to the configured value, FIC interface will be stalled untill number of queue threads drops below configured vlaue.
+#define YSEM_REG_FIC1_A_MAX_THRDS_E5                                                                         0x150102cUL //Access:RW   DataWidth:0x6    // Defines the maximum supported threads that may be contained in FIC1 A queue. If FIC1 message is received and number of threads equals to the configured value, FIC interface will be stalled untill number of queue threads drops below configured vlaue.
+#define YSEM_REG_DRA_EMPTY_BB_K2                                                                             0x1501100UL //Access:R    DataWidth:0x1    // Dra_empty.
+#define YSEM_REG_EXT_PAS_EMPTY                                                                               0x1501104UL //Access:R    DataWidth:0x1    // EXT_PAS FIFO empty in sem_slow.
+#define YSEM_REG_FIC_EMPTY                                                                                   0x1501120UL //Access:R    DataWidth:0x1    // Array of registers reflects associated FIC FIFO empty in sem_slow_fic.
+#define YSEM_REG_FIC_EMPTY_SIZE                                                                              2
+#define YSEM_REG_SLOW_DBG_EMPTY_BB_K2                                                                        0x1501140UL //Access:R    DataWidth:0x1    // DBG FIFO is empty in sem_slow_ls_dbg.
+#define YSEM_REG_SLOW_DRA_FIN_EMPTY_BB_K2                                                                    0x1501144UL //Access:R    DataWidth:0x1    // FIN fifo is empty in sem_slow_dra_sync.
+#define YSEM_REG_SLOW_DRA_RD_EMPTY_BB_K2                                                                     0x1501148UL //Access:R    DataWidth:0x1    // DRA_RD pop fifo is empty in sem_slow_dra_sync.
+#define YSEM_REG_SLOW_DRA_WR_EMPTY_BB_K2                                                                     0x150114cUL //Access:R    DataWidth:0x1    // DRA_WR push fifo is empty in sem_slow_dra_sync.
+#define YSEM_REG_SLOW_EXT_STORE_EMPTY                                                                        0x1501150UL //Access:R    DataWidth:0x1    // EXT_STORE FIFO is empty in sem_slow_ls_ext.
+#define YSEM_REG_SLOW_EXT_LOAD_EMPTY                                                                         0x1501154UL //Access:R    DataWidth:0x2    // EXT_LOAD FIFO is empty in sem_slow_ls_ext, bit 0 FIFO of Core A, bit 1 FIFO of Core B.
+#define YSEM_REG_SLOW_RAM_RD_EMPTY                                                                           0x1501158UL //Access:R    DataWidth:0x1    // EXT_RD_RAM FIFO is empty in sem_slow_ls_ext.
+#define YSEM_REG_SLOW_RAM_WR_EMPTY                                                                           0x150115cUL //Access:R    DataWidth:0x1    // EXT_WR_RAM FIFO is empty in sem_slow_ls_ext.
+#define YSEM_REG_SYNC_DBG_EMPTY                                                                              0x1501160UL //Access:R    DataWidth:0x2    // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR debug FIFO of Core B
+#define YSEM_REG_THREAD_FIFO_EMPTY_BB_K2                                                                     0x1501164UL //Access:R    DataWidth:0x1    // Indicates that the thread fifo is empty in sem_slow_dra_wr.
+#define YSEM_REG_ORD_ID_FIFO_EMPTY_BB_K2                                                                     0x1501168UL //Access:R    DataWidth:0x1    // Indicates that the order ID fifo is empty in sem_slow_dra_wr.
+#define YSEM_REG_PB_QUEUE_EMPTY_E5                                                                           0x150116cUL //Access:R    DataWidth:0xb    // If 1, the correspongding Queue is empty. Queues numeration: FOC_FIFO_IF - 0,  FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - 5,  WAKE_FIFO_PRIO_X - 6, WAKE_FIFO_PRI1_X - 7,FIC0_FIFO_B - 8, WAKE_FIFO_PRIO_B - 9,  WAKE_FIFO_PRI1_B - 10.
+#define YSEM_REG_SYNC_FOC_FIFO_EMPTY_E5                                                                      0x1501170UL //Access:R    DataWidth:0x1    // FOC FIFO empty indication.
+#define YSEM_REG_SYNC_FOC_PRE_FETCH_FIFO_EMPTY_E5                                                            0x1501174UL //Access:R    DataWidth:0x1    // FOC pre fetch FIFO empty indication.
+#define YSEM_REG_EXT_PAS_FULL                                                                                0x1501200UL //Access:R    DataWidth:0x1    // EXT_PAS FIFO Full in sem_slow.
+#define YSEM_REG_EXT_STORE_IF_FULL                                                                           0x1501204UL //Access:R    DataWidth:0x1    // EXT_STORE IF is full in sem_slow_ls_ext.
+#define YSEM_REG_FIC_FULL                                                                                    0x1501220UL //Access:R    DataWidth:0x1    // Array of registers reflects associated FIC FIFO full in sem_slow_fic.
+#define YSEM_REG_FIC_FULL_SIZE                                                                               2
+#define YSEM_REG_PAS_IF_FULL_BB_K2                                                                           0x1501240UL //Access:R    DataWidth:0x1    // Full from passive buffer asserted toward SDM.
+#define YSEM_REG_RAM_IF_FULL                                                                                 0x1501244UL //Access:R    DataWidth:0x1    // EXT_RAM IF is full in sem_slow_ls_ram.
+#define YSEM_REG_SLOW_DBG_ALM_FULL_BB_K2                                                                     0x1501248UL //Access:R    DataWidth:0x1    // DBG FIFO is almost full in sem_slow_ls_dbg according to the full threshold configuration.
+#define YSEM_REG_SLOW_DBG_FULL_BB_K2                                                                         0x150124cUL //Access:R    DataWidth:0x1    // DBG FIFO is full in sem_slow_ls_dbg.
+#define YSEM_REG_SLOW_DRA_FIN_FULL_BB_K2                                                                     0x1501250UL //Access:R    DataWidth:0x1    // FIN fifo is full in sem_slow_dra_sync (never may be active).
+#define YSEM_REG_SLOW_DRA_RD_FULL_BB_K2                                                                      0x1501254UL //Access:R    DataWidth:0x1    // DRA_RD pop fifo is full in sem_slow_dra_sync.
+#define YSEM_REG_SLOW_DRA_WR_FULL_BB_K2                                                                      0x1501258UL //Access:R    DataWidth:0x1    // DRA_WR push fifo is full in sem_slow_dra_sync.
+#define YSEM_REG_SLOW_EXT_STORE_FULL                                                                         0x150125cUL //Access:R    DataWidth:0x2    // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIFO.
+#define YSEM_REG_SLOW_EXT_LOAD_FULL                                                                          0x1501260UL //Access:R    DataWidth:0x2    // EXT_LOAD FIFO is full in sem_slow_ls_ext, bit 0 for Core A and bit 1 for Core B.
+#define YSEM_REG_SLOW_RAM_RD_FULL                                                                            0x1501264UL //Access:R    DataWidth:0x1    // EXT_RD_RAM FIFO is full in sem_slow_ls_ext.
+#define YSEM_REG_SLOW_RAM_WR_ALM_FULL                                                                        0x1501268UL //Access:R    DataWidth:0x1    // EXT_WR_RAM FIFO is almost full in sem_slow_ls_ext.
+#define YSEM_REG_SLOW_RAM_WR_FULL                                                                            0x150126cUL //Access:R    DataWidth:0x1    // EXT_WR_RAM FIFO is full in sem_slow_ls_ext.
+#define YSEM_REG_SYNC_DBG_FULL                                                                               0x1501270UL //Access:R    DataWidth:0x2    // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR debug FIFO of Core B.
+#define YSEM_REG_THREAD_FIFO_FULL_BB_K2                                                                      0x1501274UL //Access:R    DataWidth:0x1    // Indicates that the thread fifo is full in sem_slow_dra_wr.
+#define YSEM_REG_ORD_ID_FIFO_FULL_BB_K2                                                                      0x1501278UL //Access:R    DataWidth:0x1    // Indicates that the thread fifo is full in sem_slow_dra_wr.
+#define YSEM_REG_SYNC_READY_FIFO_FULL_E5                                                                     0x150127cUL //Access:R    DataWidth:0x1    // Ready sync FIFO full indication.
+#define YSEM_REG_SYNC_CNT_FIFO_FULL_E5                                                                       0x1501280UL //Access:R    DataWidth:0x1    // Counter increment sync FIFO full indication.
+#define YSEM_REG_SYNC_FOC_FIFO_FULL_E5                                                                       0x1501284UL //Access:R    DataWidth:0x1    // sync FOC FIFO full indication.
+#define YSEM_REG_THREAD_INTER_CNT_BB_K2                                                                      0x1501300UL //Access:RW   DataWidth:0x10   // Maximum value of threads interrupt counter; when it gets this value then interrupt to will be send if thread active from previous maximum value of this counter.
+#define YSEM_REG_THREAD_INTER_CNT_ENABLE_BB_K2                                                               0x1501304UL //Access:RW   DataWidth:0x1    // Enable for start count of thread_inter_cnt.
+#define YSEM_REG_THREAD_ORUN_NUM_BB_K2                                                                       0x1501308UL //Access:R    DataWidth:0xe    // Threads are sleeping in passive buffer more than thread_inter_cnt number of cycles.
+#define YSEM_REG_SLOW_DBG_ACTIVE_BB_K2                                                                       0x1501400UL //Access:RW   DataWidth:0x1    // Debug mode is active.
+#define YSEM_REG_SLOW_DBG_MODE_BB_K2                                                                         0x1501404UL //Access:RW   DataWidth:0x3    // Debug mode for slow debug bus.
+#define YSEM_REG_DBG_FRAME_MODE_BB_K2                                                                        0x1501408UL //Access:RW   DataWidth:0x2    // Debug frame mode control for the SEMI debug bus. The following values apply: "00" - indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mode-1, which means bits 127:64 belong to fast debug and bits 63:0 belong to slow debug. "10" - indicates mode-2, which means bits 127:96 belong to fast debug and bits 95:0 belong to slow debug. "11" - indicates mode-3, which means all four words are provided by the slow debug.
+#define YSEM_REG_DBG_EACH_CYLE_BB_K2                                                                         0x150140cUL //Access:RW   DataWidth:0x1    // 0=output every cycle; 1= output only when there is a change.
+#define YSEM_REG_DBG_GPRE_VECT_BB_K2                                                                         0x1501410UL //Access:RW   DataWidth:0x8    // This 8-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug channel when they are accessed for read by the Storm during mode-6 debug (handler trace). For this, bit-0 corresponds with GPRE[0-3] and bit-7 corresponds with GPRE[28-31].
+#define YSEM_REG_DBG_IF_FULL_BB_K2                                                                           0x1501414UL //Access:R    DataWidth:0x1    // DBG IF is full in sem_slow_ls_dbg.
+#define YSEM_REG_DBG_MODE0_CFG_BB_K2                                                                         0x1501418UL //Access:RW   DataWidth:0x1    // 0=all the message; 1=partial message.
+#define YSEM_REG_DBG_MODE0_CFG_CYCLE_BB_K2                                                                   0x150141cUL //Access:RW   DataWidth:0x5    // In case DebugMode0Config = 1; the additional cycles to extract to the debug bus.
+#define YSEM_REG_DBG_MODE1_CFG_BB_K2                                                                         0x1501420UL //Access:RW   DataWidth:0x1    // 0=without the data; 1=with the data.
+#define YSEM_REG_DBG_MSG_SRC_BB_K2                                                                           0x1501424UL //Access:RW   DataWidth:0x3    // This field is a mask used to enable (or filter) the various sources of DRA write debug packets. Setting a bit causes the corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1 and bit-2 corresponds with DRA writes from the passive buffer. This applicable only for debug mode=0.
+#define YSEM_REG_DBG_QUEUE_PEFORMANCE_MON_STAT_E5                                                            0x1501428UL //Access:RW   DataWidth:0x1    // If 0, the statistic report the maximum value between following reads (when using read clear). If 1, report the current value.
+#define YSEM_REG_PASSIVE_BUFFER_PERFORMANCE_MON_STAT_E5                                                      0x150142cUL //Access:RW   DataWidth:0x1    // Enable performance monitor statistics sent to SEM_PD.
+#define YSEM_REG_DBG_QUEUE_FIC_MON_CNT_E5                                                                    0x1501430UL //Access:RC   DataWidth:0x20   // Report the number of received FIC transaction between two of the following register reads. The counter is incremanted only for the event IDs which have Debug Monitor event indication set.
+#define YSEM_REG_DBG_QUEUE_FOC_MAX_VALUE_E5                                                                  0x1501434UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FOC queue.
+#define YSEM_REG_DBG_QUEUE_FIC0_A_MAX_VALUE_E5                                                               0x1501438UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 A queue.
+#define YSEM_REG_DBG_QUEUE_FIC1_A_MAX_VALUE_E5                                                               0x150143cUL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC1 A queue.
+#define YSEM_REG_DBG_QUEUE_PRIO0_A_MAX_VALUE_E5                                                              0x1501440UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 A queue.
+#define YSEM_REG_DBG_QUEUE_PRIO1_A_MAX_VALUE_E5                                                              0x1501444UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 A queue.
+#define YSEM_REG_DBG_QUEUE_FIC0_X_MAX_VALUE_E5                                                               0x1501448UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 X queue.
+#define YSEM_REG_DBG_QUEUE_PRIO0_X_MAX_VALUE_E5                                                              0x150144cUL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 X queue.
+#define YSEM_REG_DBG_QUEUE_PRIO1_X_MAX_VALUE_E5                                                              0x1501450UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 X queue.
+#define YSEM_REG_DBG_QUEUE_FIC0_B_MAX_VALUE_E5                                                               0x1501454UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 B queue.
+#define YSEM_REG_DBG_QUEUE_PRIO0_B_MAX_VALUE_E5                                                              0x1501458UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 B queue.
+#define YSEM_REG_DBG_QUEUE_PRIO1_B_MAX_VALUE_E5                                                              0x150145cUL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 B queue.
+#define YSEM_REG_DBG_QUEUE_MAX_THREAD_VALUE_E5                                                               0x1501460UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of allocated threads in the system.
+#define YSEM_REG_DBG_QUEUE_MAX_SLEEP_VALUE_E5                                                                0x1501464UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does not include the threads pending in the queues.
+#define YSEM_REG_DBG_OUT_DATA                                                                                0x1501500UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define YSEM_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define YSEM_REG_DBG_OUT_VALID                                                                               0x1501520UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define YSEM_REG_DBG_OUT_FRAME                                                                               0x1501524UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define YSEM_REG_DBG_SELECT                                                                                  0x1501528UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define YSEM_REG_DBG_DWORD_ENABLE                                                                            0x150152cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define YSEM_REG_DBG_SHIFT                                                                                   0x1501530UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define YSEM_REG_DBG_FORCE_VALID                                                                             0x1501534UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define YSEM_REG_DBG_FORCE_FRAME                                                                             0x1501538UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define YSEM_REG_EXT_PAS_FIFO_BB_K2                                                                          0x1508000UL //Access:WB_R DataWidth:0x4c   // Provides read-only access of the external passive FIFO. Intended for debug purposes.
+#define YSEM_REG_EXT_PAS_FIFO_SIZE                                                                           76
+#define YSEM_REG_INT_TABLE                                                                                   0x1510000UL //Access:RW   DataWidth:0x1e   // Interrupt table read/write access. This register is intended to be written only when the system is idle. The fields of the interrupt table are as follows. int_table[29] = Allocated per child;  int_table[28] = Increment type; int_table[27:23] = Counter select; int_table[22] = Counter insert; int_table[21:17] = GapSel; int_table[16] = Monitor enable; int_table[15:0] = PRAM Address;
+#define YSEM_REG_INT_TABLE_SIZE                                                                              256
+#define YSEM_REG_FIC_COUNTER_GROUP_E5                                                                        0x1511000UL //Access:RW   DataWidth:0x8    // This field enables a RD/WR access to the 24 counters of the "FIC Counters".
+#define YSEM_REG_FIC_COUNTER_GROUP_SIZE                                                                      24
+#define YSEM_REG_PB_THRD_STM_GROUP_E5                                                                        0x1512000UL //Access:R    DataWidth:0x17   // Read the State mahcine state of teh trheads. 0:4 - state. 5 - pending ready. 7:6 - Affinity type. 8 - Destination FOC. 9 - Destination Storm. 10 - counter increment ready. 15:11 - counter index. 16 - Debug monitor enable. 17 - Exlucsive. 22:18 - DRA size.
+#define YSEM_REG_PB_THRD_STM_GROUP_SIZE                                                                      56
+#define YSEM_REG_PASSIVE_BUFFER                                                                              0x1520000UL //Access:R    DataWidth:0x20   // Passive buffer memory read only.
+#define YSEM_REG_PASSIVE_BUFFER_SIZE_BB_K2                                                                   2520
+#define YSEM_REG_PASSIVE_BUFFER_SIZE_E5                                                                      12544
+#define YSEM_REG_FIC_GAP_VECT_BB_K2                                                                          0x1500500UL //Access:WB   DataWidth:0x2c   // This array of nine 44-bit vectors provides a bit per register-quad, used to define the register-quad locations that should be included in gaps (discontinuities) within the DRA transfer, where bit-0 corresponds with IORs 0-3, and so on. To indicate a gap, the corresponding bit should be cleared. These gaps have a granularity of a register- quad (four IORs). For each DRA write transfer from whom the FIC is the source, one of nine gap vectors (or a default-gap vector) will be selected, based on the GapSelect field of the corresponding interrupt table entry. Any unused upper bits of the vector will be ignored and thus, can be written with any value.
+#define YSEM_REG_FIC_GAP_VECT_E5                                                                             0x1530000UL //Access:WB   DataWidth:0x34   // This array of 24 x 52-bit vectors provides a bit per register-quad, used to define the register-quad locations that should be included in gaps (discontinuities) within the DRA transfer, where bit-0 corresponds with IORs 0-3, and so on. To indicate a gap, the corresponding bit should be cleared. These gaps have a granularity of a register- quad (four IORs). For each DRA write transfer from whom the FIC is the source, one of nine gap vectors (or a default-gap vector) will be selected, based on the GapSelect field of the corresponding interrupt table entry. Any unused upper bits of the vector will be ignored and thus, can be written with any value.
+#define YSEM_REG_FIC_GAP_VECT_SIZE_BB_K2                                                                     18
+#define YSEM_REG_FIC_GAP_VECT_SIZE_E5                                                                        48
+#define YSEM_REG_FAST_MEMORY                                                                                 0x1540000UL //Access:RW   DataWidth:0x20   // See sem_fast.xls for its description.
+#define YSEM_REG_FAST_MEMORY_SIZE                                                                            65536
+#define YSEM_REG_PRAM                                                                                        0x1580000UL //Access:WB   DataWidth:0x30   // Pram memory.
+#define YSEM_REG_PRAM_SIZE_BB                                                                                49152
+#define YSEM_REG_PRAM_SIZE_K2                                                                                73728
+#define YSEM_REG_PRAM_SIZE_E5                                                                                92160
+#define PSEM_REG_ENABLE_IN_BB_K2                                                                             0x1600004UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define PSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN_BB_K2                                                        (0x1<<0) // Full input from external IF to LS input enable.
+  #define PSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN_BB_K2_SHIFT                                                  0
+  #define PSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN_BB_K2                                                     (0x1<<1) // Read data from external LS IF input enable.
+  #define PSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN_BB_K2_SHIFT                                               1
+  #define PSEM_REG_ENABLE_IN_FIC_ENABLE_IN_BB_K2                                                             (0x1<<2) // FIC input enable bit used to enable/disable messages from being received on all FIC interfaces.
+  #define PSEM_REG_ENABLE_IN_FIC_ENABLE_IN_BB_K2_SHIFT                                                       2
+  #define PSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN_BB_K2                                                         (0x1<<3) // FOC acknowledge input enable bit used to enable/disable acknowledge response from being received on any of the FOC interfaces.
+  #define PSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN_BB_K2_SHIFT                                                   3
+  #define PSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN_BB_K2                                                         (0x1<<4) // General interface input enable.
+  #define PSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN_BB_K2_SHIFT                                                   4
+  #define PSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN_BB_K2                                                         (0x1<<5) // External passive write input enable.
+  #define PSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN_BB_K2_SHIFT                                                   5
+  #define PSEM_REG_ENABLE_IN_RAM_ENABLE_IN_BB_K2                                                             (0x1<<6) // Data input enable to RAM.
+  #define PSEM_REG_ENABLE_IN_RAM_ENABLE_IN_BB_K2_SHIFT                                                       6
+  #define PSEM_REG_ENABLE_IN_STALL_ENABLE_IN_BB_K2                                                           (0x1<<7) // Enable for stall input from all external STORM instances.
+  #define PSEM_REG_ENABLE_IN_STALL_ENABLE_IN_BB_K2_SHIFT                                                     7
+  #define PSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN_BB_K2                                                      (0x1<<8) // Thread ready bus input enable.
+  #define PSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN_BB_K2_SHIFT                                                8
+  #define PSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN_BB_K2                                                      (0x1<<9) // Input enable for VF error indication from SDM to SEMI.
+  #define PSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN_BB_K2_SHIFT                                                9
+#define PSEM_REG_ENABLE_OUT_BB_K2                                                                            0x1600008UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define PSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT_BB_K2                                                    (0x1<<0) // Read request output enable from external LS IF.
+  #define PSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT_BB_K2_SHIFT                                              0
+  #define PSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT_BB_K2                                                    (0x1<<1) // Write request output enable from external LS IF.
+  #define PSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT_BB_K2_SHIFT                                              1
+  #define PSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT_BB_K2                                                           (0x1<<2) // FOC output otuput enable bit used to enable/disable messages from being sent out on any of the FOC interfaces.
+  #define PSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT_BB_K2_SHIFT                                                     2
+  #define PSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT_BB_K2                                                       (0x1<<3) // Passive full output enable.
+  #define PSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT_BB_K2_SHIFT                                                 3
+  #define PSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT_BB_K2                                                           (0x1<<4) // Data output enable to RAM.
+  #define PSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT_BB_K2_SHIFT                                                     4
+  #define PSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT_BB_K2                                                         (0x1<<5) // Stall output enable bit used to enable/disable the output stall signal toward all external Storm instances.
+  #define PSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT_BB_K2_SHIFT                                                   5
+#define PSEM_REG_FIC_DISABLE_BB_K2                                                                           0x160000cUL //Access:RW   DataWidth:0x1    // Disables input messages from all FIC interfaces.  May be updated during run_time by the microcode.
+#define PSEM_REG_PAS_DISABLE_BB_K2                                                                           0x1600010UL //Access:RW   DataWidth:0x1    // Disables input messages from the passive buffer  May be updated during run_time by the microcode.
+#define PSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_E5                                                         0x1600014UL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define PSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_FIC_WEIGHT_E5                                   (0xf<<0) // Passive Buffer write WRR weight value for FIC source.
+  #define PSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_FIC_WEIGHT_E5_SHIFT                             0
+  #define PSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_A_WEIGHT_E5                                 (0xf<<4) // Passive Buffer write WRR weight value for DRA RD A source.
+  #define PSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_A_WEIGHT_E5_SHIFT                           4
+  #define PSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_B_WEIGHT_E5                                 (0xf<<8) // Passive Buffer write WRR weight value for DRA RD B source.
+  #define PSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_B_WEIGHT_E5_SHIFT                           8
+  #define PSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_SDM_WEIGHT_E5                                   (0xf<<12) // Passive Buffer write WRR weight value for SDM source.
+  #define PSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_SDM_WEIGHT_E5_SHIFT                             12
+  #define PSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_EMPTY_CNT_E5                                    (0xf<<16) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define PSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_EMPTY_CNT_E5_SHIFT                              16
+  #define PSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_STRICT_SRC_E5                                      (0x7<<20) // This register defines if one of the source of the PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B, 100 - SDM.
+  #define PSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_STRICT_SRC_E5_SHIFT                                20
+#define PSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_E5                                                          0x1600018UL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define PSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_FOC_WEIGHT_E5                                    (0xf<<0) // Passive Buffer WRR weight value for FOC source.
+  #define PSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_FOC_WEIGHT_E5_SHIFT                              0
+  #define PSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_A_WEIGHT_E5                                  (0xf<<4) // Passive Buffer write WRR weight value for DRA WR A source.
+  #define PSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_A_WEIGHT_E5_SHIFT                            4
+  #define PSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_B_WEIGHT_E5                                  (0xf<<8) // Passive Buffer write WRR weight value for DRA WR B source.
+  #define PSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_B_WEIGHT_E5_SHIFT                            8
+  #define PSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_GRC_WEIGHT_E5                                    (0xf<<12) // Passive Buffer write WRR weight value for GRC source.
+  #define PSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_GRC_WEIGHT_E5_SHIFT                              12
+  #define PSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_EMPTY_CNT_E5                                     (0xf<<16) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define PSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_EMPTY_CNT_E5_SHIFT                               16
+  #define PSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_STRICT_SRC_E5                                       (0x7<<20) // This register defines if one of the source of the PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B, 100 - GRC.
+  #define PSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_STRICT_SRC_E5_SHIFT                                 20
+#define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_E5                                                            0x160001cUL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_FIC0_A_WEIGHT_E5                             (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_FIC0_A_WEIGHT_E5_SHIFT                       0
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_FIC1_A_WEIGHT_E5                             (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_FIC1_A_WEIGHT_E5_SHIFT                       4
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO0_A_WEIGHT_E5                            (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO0_A_WEIGHT_E5_SHIFT                      8
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO1_A_WEIGHT_E5                            (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO1_A_WEIGHT_E5_SHIFT                      12
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_EMPTY_CNT_E5                                 (0xf<<16) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_EMPTY_CNT_E5_SHIFT                           16
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_STRICT_SRC_E5                                   (0x7<<20) // This register defines if one of the source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - FIC1.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_STRICT_SRC_E5_SHIFT                             20
+#define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_E5                                                            0x1600020UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_FIC0_X_WEIGHT_E5                             (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_FIC0_X_WEIGHT_E5_SHIFT                       0
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO0_X_WEIGHT_E5                            (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO0_X_WEIGHT_E5_SHIFT                      4
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO1_X_WEIGHT_E5                            (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO1_X_WEIGHT_E5_SHIFT                      8
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_EMPTY_CNT_E5                                 (0xf<<12) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_EMPTY_CNT_E5_SHIFT                           12
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_STRICT_SRC_E5                                   (0x3<<16) // This register defines if one of the source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_STRICT_SRC_E5_SHIFT                             16
+#define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_E5                                                            0x1600024UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_FIC0_B_WEIGHT_E5                             (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_FIC0_B_WEIGHT_E5_SHIFT                       0
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO0_B_WEIGHT_E5                            (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO0_B_WEIGHT_E5_SHIFT                      4
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO1_B_WEIGHT_E5                            (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO1_B_WEIGHT_E5_SHIFT                      8
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_EMPTY_CNT_E5                                 (0xf<<12) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_EMPTY_CNT_E5_SHIFT                           12
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_STRICT_SRC_E5                                   (0x3<<16) // This register defines if one of the source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_STRICT_SRC_E5_SHIFT                             16
+#define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_E5                                                            0x1600028UL //Access:RW   DataWidth:0xe    // Multi Field Register.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_AFFIN_A_WEIGHT_E5                            (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for Affinity A source.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_AFFIN_A_WEIGHT_E5_SHIFT                      0
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_AFFIN_X_WEIGHT_E5                            (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for Affinity X source.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_AFFIN_X_WEIGHT_E5_SHIFT                      4
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_EMPTY_CNT_E5                                 (0xf<<8) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_EMPTY_CNT_E5_SHIFT                           8
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_STRICT_SRC_E5                                   (0x3<<12) // This register defines if one of the source of the PB WR arbiter should have strict priority: 0 - None, 1 - AFFINITY A, 2- AFFINITY X.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_STRICT_SRC_E5_SHIFT                             12
+#define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_E5                                                            0x160002cUL //Access:RW   DataWidth:0xc    // Multi Field Register.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_AFFIN_B_WEIGHT_E5                            (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for Affinity B source.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_AFFIN_B_WEIGHT_E5_SHIFT                      0
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_AFFIN_X_WEIGHT_E5                            (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for Affinity X source.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_AFFIN_X_WEIGHT_E5_SHIFT                      4
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_EMPTY_CNT_E5                                 (0xf<<8) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define PSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_EMPTY_CNT_E5_SHIFT                           8
+#define PSEM_REG_PASSIVE_BUFFER_DRA_WR_E5                                                                    0x1600030UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define PSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_A_E5                                                   (0x1<<0) // Enable DRA Write to transactions towards the SEM_PD Core A.
+  #define PSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_A_E5_SHIFT                                             0
+  #define PSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_B_E5                                                   (0x1<<1) // Enable DRA Write to transactions towards the SEM_PD Core B.
+  #define PSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_B_E5_SHIFT                                             1
+  #define PSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_PEND_BLOCK_EN_E5                                          (0x1<<2) // When set, there may only be a single thread pending to run for each storm.
+  #define PSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_PEND_BLOCK_EN_E5_SHIFT                                    2
+  #define PSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_AFFINITY_CORE_A_ONLY_E5                                          (0x1<<3) // When set, the Affintiy field of the thread is set to CoreA (regardless to the Afficnity received from CM).
+  #define PSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_AFFINITY_CORE_A_ONLY_E5_SHIFT                                    3
+#define PSEM_REG_INT_STS_0                                                                                   0x1600040UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PSEM_REG_INT_STS_0_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSEM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                             0
+  #define PSEM_REG_INT_STS_0_FIC_LAST_ERROR                                                                  (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
+  #define PSEM_REG_INT_STS_0_FIC_LAST_ERROR_SHIFT                                                            1
+  #define PSEM_REG_INT_STS_0_FIC_LENGTH_ERROR                                                                (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
+  #define PSEM_REG_INT_STS_0_FIC_LENGTH_ERROR_SHIFT                                                          2
+  #define PSEM_REG_INT_STS_0_FIC_FIFO_ERROR                                                                  (0x1<<3) // Error in any one of the FIC FIFO is active.
+  #define PSEM_REG_INT_STS_0_FIC_FIFO_ERROR_SHIFT                                                            3
+  #define PSEM_REG_INT_STS_0_DRA_RD_A_LAST_ERROR_E5                                                          (0x1<<4) // DRA_RD_A last indication was unexpectedly received or was not received at expected time.
+  #define PSEM_REG_INT_STS_0_DRA_RD_A_LAST_ERROR_E5_SHIFT                                                    4
+  #define PSEM_REG_INT_STS_0_DRA_RD_B_LAST_ERROR_E5                                                          (0x1<<5) // DRA_RD_B last indication was unexpectedly received or was not received at expected time.
+  #define PSEM_REG_INT_STS_0_DRA_RD_B_LAST_ERROR_E5_SHIFT                                                    5
+  #define PSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_A_E5                                                   (0x1<<6) // Error in external store slow sync FIFO pop logic of Storm A.
+  #define PSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_A_E5_SHIFT                                             6
+  #define PSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_B_E5                                                   (0x1<<7) // Error in external store slow sync FIFO pop logic of Storm B.
+  #define PSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT                                             7
+  #define PSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5                                                   (0x1<<8) // Error in external load sync slow FIFO push logic.
+  #define PSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT                                             8
+  #define PSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5                                                   (0x1<<9) // Error in external load sync slow FIFO pop logic.
+  #define PSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5_SHIFT                                             9
+  #define PSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2                                                    (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
+  #define PSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2_SHIFT                                              22
+  #define PSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_E5                                                       (0x1<<10) // Error in slow LS_SYNC_PUSH FIFO.
+  #define PSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_E5_SHIFT                                                 10
+  #define PSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_BB_K2                                                     (0x1<<23) // Error in LS_SYNC_POP FIFO.
+  #define PSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_BB_K2_SHIFT                                               23
+  #define PSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_E5                                                        (0x1<<11) // Error in slow LS_SYNC_POP FIFO.
+  #define PSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_E5_SHIFT                                                  11
+  #define PSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2                                                    (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
+  #define PSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2_SHIFT                                              25
+  #define PSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_E5                                                       (0x1<<12) // Error in slow LS_SYNC_PUSH FIFO.
+  #define PSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_E5_SHIFT                                                 12
+  #define PSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_A_E5                                                         (0x1<<13) // Error in slow LS_SYNC_PUSH FIFO.
+  #define PSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_A_E5_SHIFT                                                   13
+  #define PSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_B_E5                                                         (0x1<<14) // Error in slow LS_SYNC_POP FIFO.
+  #define PSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_B_E5_SHIFT                                                   14
+  #define PSEM_REG_INT_STS_0_DBG_FIFO_ERROR_BB_K2                                                            (0x1<<28) // Error in slow debug fifo.
+  #define PSEM_REG_INT_STS_0_DBG_FIFO_ERROR_BB_K2_SHIFT                                                      28
+  #define PSEM_REG_INT_STS_0_DBG_FIFO_ERROR_E5                                                               (0x1<<15) // Error in slow debug fifo
+  #define PSEM_REG_INT_STS_0_DBG_FIFO_ERROR_E5_SHIFT                                                         15
+  #define PSEM_REG_INT_STS_0_EXT_THREAD_OOR_ERROR_E5                                                         (0x1<<16) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define PSEM_REG_INT_STS_0_EXT_THREAD_OOR_ERROR_E5_SHIFT                                                   16
+  #define PSEM_REG_INT_STS_0_EXT_STORE_TAG_ODER_ERROR_E5                                                     (0x1<<17) // Error detected in the ext Stroe interface internal TAG order ID.
+  #define PSEM_REG_INT_STS_0_EXT_STORE_TAG_ODER_ERROR_E5_SHIFT                                               17
+  #define PSEM_REG_INT_STS_0_FIC1_AFFINITY_FIELD_ERROR_E5                                                    (0x1<<18) // Indicates that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
+  #define PSEM_REG_INT_STS_0_FIC1_AFFINITY_FIELD_ERROR_E5_SHIFT                                              18
+  #define PSEM_REG_INT_STS_0_EXT_LD_LEN_ERROR_E5                                                             (0x1<<19) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define PSEM_REG_INT_STS_0_EXT_LD_LEN_ERROR_E5_SHIFT                                                       19
+  #define PSEM_REG_INT_STS_0_PB_QUE_ARB_THRD_RDY_ERROR_E5                                                    (0x1<<20) // Indicates that Passive Buffer State machine has unexpectedly received a ready indication in the following cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pending FOC" or "Ready FOC" state. b. Pending Ready indication is already asserted.
+  #define PSEM_REG_INT_STS_0_PB_QUE_ARB_THRD_RDY_ERROR_E5_SHIFT                                              20
+  #define PSEM_REG_INT_STS_0_SYNC_FOC_FIFO_ERROR_E5                                                          (0x1<<21) // Error indication on FOC sync FIFO.
+  #define PSEM_REG_INT_STS_0_SYNC_FOC_FIFO_ERROR_E5_SHIFT                                                    21
+  #define PSEM_REG_INT_STS_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                      (0x1<<22) // The error indicates on an error of one the threads READY queues.
+  #define PSEM_REG_INT_STS_0_PB_QUE_ARB_QUEUES_ERROR_E5_SHIFT                                                22
+  #define PSEM_REG_INT_STS_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5                                                (0x1<<23) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define PSEM_REG_INT_STS_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5_SHIFT                                          23
+  #define PSEM_REG_INT_STS_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5                                                (0x1<<24) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define PSEM_REG_INT_STS_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5_SHIFT                                          24
+  #define PSEM_REG_INT_STS_0_CREDIT_ERROR_FOC0_E5                                                            (0x1<<25) // FOC0 is out of credit.
+  #define PSEM_REG_INT_STS_0_CREDIT_ERROR_FOC0_E5_SHIFT                                                      25
+  #define PSEM_REG_INT_STS_0_CREDIT_ERROR_FOC1_E5                                                            (0x1<<26) // FOC1 is out of credit.
+  #define PSEM_REG_INT_STS_0_CREDIT_ERROR_FOC1_E5_SHIFT                                                      26
+  #define PSEM_REG_INT_STS_0_CREDIT_ERROR_FOC2_E5                                                            (0x1<<27) // FOC2 is out of credit.
+  #define PSEM_REG_INT_STS_0_CREDIT_ERROR_FOC2_E5_SHIFT                                                      27
+  #define PSEM_REG_INT_STS_0_CREDIT_ERROR_FOC3_E5                                                            (0x1<<28) // FOC3 is out of credit.
+  #define PSEM_REG_INT_STS_0_CREDIT_ERROR_FOC3_E5_SHIFT                                                      28
+  #define PSEM_REG_INT_STS_0_CREDIT_ERROR_FOC4_E5                                                            (0x1<<29) // FOC4 is out of credit.
+  #define PSEM_REG_INT_STS_0_CREDIT_ERROR_FOC4_E5_SHIFT                                                      29
+  #define PSEM_REG_INT_STS_0_CREDIT_ERROR_FOC5_E5                                                            (0x1<<30) // FOC5 is out of credit.
+  #define PSEM_REG_INT_STS_0_CREDIT_ERROR_FOC5_E5_SHIFT                                                      30
+  #define PSEM_REG_INT_STS_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                     (0x1<<31) // Error indication of foc pre_fetch fifo.
+  #define PSEM_REG_INT_STS_0_FOC_PRE_FETCH_FIFO_ERROR_E5_SHIFT                                               31
+  #define PSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR_BB_K2                                                        (0x1<<4) // Error in Ext PAS_FIFO is active.
+  #define PSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR_BB_K2_SHIFT                                                  4
+  #define PSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR_BB_K2                                                        (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
+  #define PSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR_BB_K2_SHIFT                                                  5
+  #define PSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2                                                    (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
+  #define PSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2_SHIFT                                              6
+  #define PSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR_BB_K2                                                     (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
+  #define PSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT                                               7
+  #define PSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2                                                    (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
+  #define PSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT                                              8
+  #define PSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR_BB_K2                                                     (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
+  #define PSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR_BB_K2_SHIFT                                               9
+  #define PSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR_BB_K2                                                       (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
+  #define PSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR_BB_K2_SHIFT                                                 10
+  #define PSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR_BB_K2                                                    (0x1<<11) // Signals an unknown address in the fast-memory window.
+  #define PSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR_BB_K2_SHIFT                                              11
+  #define PSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO_BB_K2                                                          (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
+  #define PSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO_BB_K2_SHIFT                                                    12
+  #define PSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO_BB_K2                                                          (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
+  #define PSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO_BB_K2_SHIFT                                                    13
+  #define PSEM_REG_INT_STS_0_CAM_OUT_FIFO_BB_K2                                                              (0x1<<14) // Error in CAM_OUT fifo in cam block.
+  #define PSEM_REG_INT_STS_0_CAM_OUT_FIFO_BB_K2_SHIFT                                                        14
+  #define PSEM_REG_INT_STS_0_FIN_FIFO_BB_K2                                                                  (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
+  #define PSEM_REG_INT_STS_0_FIN_FIFO_BB_K2_SHIFT                                                            15
+  #define PSEM_REG_INT_STS_0_THREAD_FIFO_ERROR_BB_K2                                                         (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
+  #define PSEM_REG_INT_STS_0_THREAD_FIFO_ERROR_BB_K2_SHIFT                                                   16
+  #define PSEM_REG_INT_STS_0_THREAD_OVERRUN_BB_K2                                                            (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
+  #define PSEM_REG_INT_STS_0_THREAD_OVERRUN_BB_K2_SHIFT                                                      17
+  #define PSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2                                                 (0x1<<18) // Error in external store sync FIFO push logic.
+  #define PSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2_SHIFT                                           18
+  #define PSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_BB_K2                                                  (0x1<<19) // Error in external store sync FIFO pop logic.
+  #define PSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_BB_K2_SHIFT                                            19
+  #define PSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2                                                  (0x1<<20) // Error in external load sync FIFO push logic.
+  #define PSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2_SHIFT                                            20
+  #define PSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2                                                   (0x1<<21) // Error in external load sync FIFO pop logic.
+  #define PSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2_SHIFT                                             21
+  #define PSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR_BB_K2                                                     (0x1<<24) // Error in LS_SYNC_POP FIFO.
+  #define PSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR_BB_K2_SHIFT                                               24
+  #define PSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR_BB_K2                                                       (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
+  #define PSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR_BB_K2_SHIFT                                                 26
+  #define PSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_BB_K2                                                        (0x1<<27) // Error in LS_SYNC_POP FIFO.
+  #define PSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_BB_K2_SHIFT                                                  27
+  #define PSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO_BB_K2                                                         (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
+  #define PSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO_BB_K2_SHIFT                                                   29
+  #define PSEM_REG_INT_STS_0_VFC_INTERRUPT_BB_K2                                                             (0x1<<30) // Error interrupt in VFC block.
+  #define PSEM_REG_INT_STS_0_VFC_INTERRUPT_BB_K2_SHIFT                                                       30
+  #define PSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR_BB_K2                                                        (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
+  #define PSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR_BB_K2_SHIFT                                                  31
+#define PSEM_REG_INT_MASK_0                                                                                  0x1600044UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PSEM_REG_INT_MASK_0_ADDRESS_ERROR                                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.ADDRESS_ERROR .
+  #define PSEM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                            0
+  #define PSEM_REG_INT_MASK_0_FIC_LAST_ERROR                                                                 (0x1<<1) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.FIC_LAST_ERROR .
+  #define PSEM_REG_INT_MASK_0_FIC_LAST_ERROR_SHIFT                                                           1
+  #define PSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR                                                               (0x1<<2) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.FIC_LENGTH_ERROR .
+  #define PSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR_SHIFT                                                         2
+  #define PSEM_REG_INT_MASK_0_FIC_FIFO_ERROR                                                                 (0x1<<3) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.FIC_FIFO_ERROR .
+  #define PSEM_REG_INT_MASK_0_FIC_FIFO_ERROR_SHIFT                                                           3
+  #define PSEM_REG_INT_MASK_0_DRA_RD_A_LAST_ERROR_E5                                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.DRA_RD_A_LAST_ERROR .
+  #define PSEM_REG_INT_MASK_0_DRA_RD_A_LAST_ERROR_E5_SHIFT                                                   4
+  #define PSEM_REG_INT_MASK_0_DRA_RD_B_LAST_ERROR_E5                                                         (0x1<<5) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.DRA_RD_B_LAST_ERROR .
+  #define PSEM_REG_INT_MASK_0_DRA_RD_B_LAST_ERROR_E5_SHIFT                                                   5
+  #define PSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_A_E5                                                  (0x1<<6) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR_A .
+  #define PSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_A_E5_SHIFT                                            6
+  #define PSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_B_E5                                                  (0x1<<7) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR_B .
+  #define PSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT                                            7
+  #define PSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5                                                  (0x1<<8) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR_A .
+  #define PSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT                                            8
+  #define PSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5                                                  (0x1<<9) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR_B .
+  #define PSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5_SHIFT                                            9
+  #define PSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2                                                   (0x1<<22) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_RAM_RD_PUSH_ERROR .
+  #define PSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2_SHIFT                                             22
+  #define PSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_E5                                                      (0x1<<10) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_RAM_RD_PUSH_ERROR .
+  #define PSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_E5_SHIFT                                                10
+  #define PSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_BB_K2                                                    (0x1<<23) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_RAM_RD_POP_ERROR .
+  #define PSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_BB_K2_SHIFT                                              23
+  #define PSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_E5                                                       (0x1<<11) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_RAM_RD_POP_ERROR .
+  #define PSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_E5_SHIFT                                                 11
+  #define PSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2                                                   (0x1<<25) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_RAM_WR_PUSH_ERROR .
+  #define PSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2_SHIFT                                             25
+  #define PSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_E5                                                      (0x1<<12) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_RAM_WR_PUSH_ERROR .
+  #define PSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_E5_SHIFT                                                12
+  #define PSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_A_E5                                                        (0x1<<13) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR_A .
+  #define PSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_A_E5_SHIFT                                                  13
+  #define PSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_B_E5                                                        (0x1<<14) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR_B .
+  #define PSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_B_E5_SHIFT                                                  14
+  #define PSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_BB_K2                                                           (0x1<<28) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.DBG_FIFO_ERROR .
+  #define PSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_BB_K2_SHIFT                                                     28
+  #define PSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_E5                                                              (0x1<<15) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.DBG_FIFO_ERROR .
+  #define PSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_E5_SHIFT                                                        15
+  #define PSEM_REG_INT_MASK_0_EXT_THREAD_OOR_ERROR_E5                                                        (0x1<<16) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.EXT_THREAD_OOR_ERROR .
+  #define PSEM_REG_INT_MASK_0_EXT_THREAD_OOR_ERROR_E5_SHIFT                                                  16
+  #define PSEM_REG_INT_MASK_0_EXT_STORE_TAG_ODER_ERROR_E5                                                    (0x1<<17) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.EXT_STORE_TAG_ODER_ERROR .
+  #define PSEM_REG_INT_MASK_0_EXT_STORE_TAG_ODER_ERROR_E5_SHIFT                                              17
+  #define PSEM_REG_INT_MASK_0_FIC1_AFFINITY_FIELD_ERROR_E5                                                   (0x1<<18) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.FIC1_AFFINITY_FIELD_ERROR .
+  #define PSEM_REG_INT_MASK_0_FIC1_AFFINITY_FIELD_ERROR_E5_SHIFT                                             18
+  #define PSEM_REG_INT_MASK_0_EXT_LD_LEN_ERROR_E5                                                            (0x1<<19) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.EXT_LD_LEN_ERROR .
+  #define PSEM_REG_INT_MASK_0_EXT_LD_LEN_ERROR_E5_SHIFT                                                      19
+  #define PSEM_REG_INT_MASK_0_PB_QUE_ARB_THRD_RDY_ERROR_E5                                                   (0x1<<20) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.PB_QUE_ARB_THRD_RDY_ERROR .
+  #define PSEM_REG_INT_MASK_0_PB_QUE_ARB_THRD_RDY_ERROR_E5_SHIFT                                             20
+  #define PSEM_REG_INT_MASK_0_SYNC_FOC_FIFO_ERROR_E5                                                         (0x1<<21) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_FOC_FIFO_ERROR .
+  #define PSEM_REG_INT_MASK_0_SYNC_FOC_FIFO_ERROR_E5_SHIFT                                                   21
+  #define PSEM_REG_INT_MASK_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                     (0x1<<22) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.PB_QUE_ARB_QUEUES_ERROR .
+  #define PSEM_REG_INT_MASK_0_PB_QUE_ARB_QUEUES_ERROR_E5_SHIFT                                               22
+  #define PSEM_REG_INT_MASK_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5                                               (0x1<<23) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.STORM_MOVRIND_USES_BAR_ATTN_A .
+  #define PSEM_REG_INT_MASK_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5_SHIFT                                         23
+  #define PSEM_REG_INT_MASK_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5                                               (0x1<<24) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.STORM_MOVRIND_USES_BAR_ATTN_B .
+  #define PSEM_REG_INT_MASK_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5_SHIFT                                         24
+  #define PSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC0_E5                                                           (0x1<<25) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.CREDIT_ERROR_FOC0 .
+  #define PSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC0_E5_SHIFT                                                     25
+  #define PSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC1_E5                                                           (0x1<<26) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.CREDIT_ERROR_FOC1 .
+  #define PSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC1_E5_SHIFT                                                     26
+  #define PSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC2_E5                                                           (0x1<<27) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.CREDIT_ERROR_FOC2 .
+  #define PSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC2_E5_SHIFT                                                     27
+  #define PSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC3_E5                                                           (0x1<<28) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.CREDIT_ERROR_FOC3 .
+  #define PSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC3_E5_SHIFT                                                     28
+  #define PSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC4_E5                                                           (0x1<<29) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.CREDIT_ERROR_FOC4 .
+  #define PSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC4_E5_SHIFT                                                     29
+  #define PSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC5_E5                                                           (0x1<<30) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.CREDIT_ERROR_FOC5 .
+  #define PSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC5_E5_SHIFT                                                     30
+  #define PSEM_REG_INT_MASK_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                    (0x1<<31) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.FOC_PRE_FETCH_FIFO_ERROR .
+  #define PSEM_REG_INT_MASK_0_FOC_PRE_FETCH_FIFO_ERROR_E5_SHIFT                                              31
+  #define PSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR_BB_K2                                                       (0x1<<4) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.PAS_BUF_FIFO_ERROR .
+  #define PSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR_BB_K2_SHIFT                                                 4
+  #define PSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR_BB_K2                                                       (0x1<<5) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_FIN_POP_ERROR .
+  #define PSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR_BB_K2_SHIFT                                                 5
+  #define PSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2                                                   (0x1<<6) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_DRA_WR_PUSH_ERROR .
+  #define PSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2_SHIFT                                             6
+  #define PSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR_BB_K2                                                    (0x1<<7) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_DRA_WR_POP_ERROR .
+  #define PSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT                                              7
+  #define PSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2                                                   (0x1<<8) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_DRA_RD_PUSH_ERROR .
+  #define PSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT                                             8
+  #define PSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR_BB_K2                                                    (0x1<<9) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_DRA_RD_POP_ERROR .
+  #define PSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR_BB_K2_SHIFT                                              9
+  #define PSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR_BB_K2                                                      (0x1<<10) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_FIN_PUSH_ERROR .
+  #define PSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR_BB_K2_SHIFT                                                10
+  #define PSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR_BB_K2                                                   (0x1<<11) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SEM_FAST_ADDRESS_ERROR .
+  #define PSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR_BB_K2_SHIFT                                             11
+  #define PSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO_BB_K2                                                         (0x1<<12) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.CAM_LSB_INP_FIFO .
+  #define PSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO_BB_K2_SHIFT                                                   12
+  #define PSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO_BB_K2                                                         (0x1<<13) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.CAM_MSB_INP_FIFO .
+  #define PSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO_BB_K2_SHIFT                                                   13
+  #define PSEM_REG_INT_MASK_0_CAM_OUT_FIFO_BB_K2                                                             (0x1<<14) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.CAM_OUT_FIFO .
+  #define PSEM_REG_INT_MASK_0_CAM_OUT_FIFO_BB_K2_SHIFT                                                       14
+  #define PSEM_REG_INT_MASK_0_FIN_FIFO_BB_K2                                                                 (0x1<<15) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.FIN_FIFO .
+  #define PSEM_REG_INT_MASK_0_FIN_FIFO_BB_K2_SHIFT                                                           15
+  #define PSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR_BB_K2                                                        (0x1<<16) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.THREAD_FIFO_ERROR .
+  #define PSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR_BB_K2_SHIFT                                                  16
+  #define PSEM_REG_INT_MASK_0_THREAD_OVERRUN_BB_K2                                                           (0x1<<17) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.THREAD_OVERRUN .
+  #define PSEM_REG_INT_MASK_0_THREAD_OVERRUN_BB_K2_SHIFT                                                     17
+  #define PSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2                                                (0x1<<18) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_EXT_STORE_PUSH_ERROR .
+  #define PSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2_SHIFT                                          18
+  #define PSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_BB_K2                                                 (0x1<<19) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR .
+  #define PSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_BB_K2_SHIFT                                           19
+  #define PSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2                                                 (0x1<<20) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR .
+  #define PSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2_SHIFT                                           20
+  #define PSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2                                                  (0x1<<21) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_EXT_LOAD_POP_ERROR .
+  #define PSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2_SHIFT                                            21
+  #define PSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR_BB_K2                                                    (0x1<<24) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_RAM_WR_POP_ERROR .
+  #define PSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR_BB_K2_SHIFT                                              24
+  #define PSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR_BB_K2                                                      (0x1<<26) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_DBG_PUSH_ERROR .
+  #define PSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR_BB_K2_SHIFT                                                26
+  #define PSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_BB_K2                                                       (0x1<<27) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR .
+  #define PSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_BB_K2_SHIFT                                                 27
+  #define PSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO_BB_K2                                                        (0x1<<29) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.CAM_MSB2_INP_FIFO .
+  #define PSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO_BB_K2_SHIFT                                                  29
+  #define PSEM_REG_INT_MASK_0_VFC_INTERRUPT_BB_K2                                                            (0x1<<30) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.VFC_INTERRUPT .
+  #define PSEM_REG_INT_MASK_0_VFC_INTERRUPT_BB_K2_SHIFT                                                      30
+  #define PSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR_BB_K2                                                       (0x1<<31) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.VFC_OUT_FIFO_ERROR .
+  #define PSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR_BB_K2_SHIFT                                                 31
+#define PSEM_REG_INT_STS_WR_0                                                                                0x1600048UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define PSEM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSEM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                          0
+  #define PSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR                                                               (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
+  #define PSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR_SHIFT                                                         1
+  #define PSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR                                                             (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
+  #define PSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR_SHIFT                                                       2
+  #define PSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR                                                               (0x1<<3) // Error in any one of the FIC FIFO is active.
+  #define PSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR_SHIFT                                                         3
+  #define PSEM_REG_INT_STS_WR_0_DRA_RD_A_LAST_ERROR_E5                                                       (0x1<<4) // DRA_RD_A last indication was unexpectedly received or was not received at expected time.
+  #define PSEM_REG_INT_STS_WR_0_DRA_RD_A_LAST_ERROR_E5_SHIFT                                                 4
+  #define PSEM_REG_INT_STS_WR_0_DRA_RD_B_LAST_ERROR_E5                                                       (0x1<<5) // DRA_RD_B last indication was unexpectedly received or was not received at expected time.
+  #define PSEM_REG_INT_STS_WR_0_DRA_RD_B_LAST_ERROR_E5_SHIFT                                                 5
+  #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_A_E5                                                (0x1<<6) // Error in external store slow sync FIFO pop logic of Storm A.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_A_E5_SHIFT                                          6
+  #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_B_E5                                                (0x1<<7) // Error in external store slow sync FIFO pop logic of Storm B.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT                                          7
+  #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5                                                (0x1<<8) // Error in external load sync slow FIFO push logic.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT                                          8
+  #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5                                                (0x1<<9) // Error in external load sync slow FIFO pop logic.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5_SHIFT                                          9
+  #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2                                                 (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2_SHIFT                                           22
+  #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_E5                                                    (0x1<<10) // Error in slow LS_SYNC_PUSH FIFO.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_E5_SHIFT                                              10
+  #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_BB_K2                                                  (0x1<<23) // Error in LS_SYNC_POP FIFO.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_BB_K2_SHIFT                                            23
+  #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_E5                                                     (0x1<<11) // Error in slow LS_SYNC_POP FIFO.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_E5_SHIFT                                               11
+  #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2                                                 (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2_SHIFT                                           25
+  #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_E5                                                    (0x1<<12) // Error in slow LS_SYNC_PUSH FIFO.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_E5_SHIFT                                              12
+  #define PSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_A_E5                                                      (0x1<<13) // Error in slow LS_SYNC_PUSH FIFO.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_A_E5_SHIFT                                                13
+  #define PSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_B_E5                                                      (0x1<<14) // Error in slow LS_SYNC_POP FIFO.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_B_E5_SHIFT                                                14
+  #define PSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_BB_K2                                                         (0x1<<28) // Error in slow debug fifo.
+  #define PSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_BB_K2_SHIFT                                                   28
+  #define PSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_E5                                                            (0x1<<15) // Error in slow debug fifo
+  #define PSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_E5_SHIFT                                                      15
+  #define PSEM_REG_INT_STS_WR_0_EXT_THREAD_OOR_ERROR_E5                                                      (0x1<<16) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define PSEM_REG_INT_STS_WR_0_EXT_THREAD_OOR_ERROR_E5_SHIFT                                                16
+  #define PSEM_REG_INT_STS_WR_0_EXT_STORE_TAG_ODER_ERROR_E5                                                  (0x1<<17) // Error detected in the ext Stroe interface internal TAG order ID.
+  #define PSEM_REG_INT_STS_WR_0_EXT_STORE_TAG_ODER_ERROR_E5_SHIFT                                            17
+  #define PSEM_REG_INT_STS_WR_0_FIC1_AFFINITY_FIELD_ERROR_E5                                                 (0x1<<18) // Indicates that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
+  #define PSEM_REG_INT_STS_WR_0_FIC1_AFFINITY_FIELD_ERROR_E5_SHIFT                                           18
+  #define PSEM_REG_INT_STS_WR_0_EXT_LD_LEN_ERROR_E5                                                          (0x1<<19) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define PSEM_REG_INT_STS_WR_0_EXT_LD_LEN_ERROR_E5_SHIFT                                                    19
+  #define PSEM_REG_INT_STS_WR_0_PB_QUE_ARB_THRD_RDY_ERROR_E5                                                 (0x1<<20) // Indicates that Passive Buffer State machine has unexpectedly received a ready indication in the following cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pending FOC" or "Ready FOC" state. b. Pending Ready indication is already asserted.
+  #define PSEM_REG_INT_STS_WR_0_PB_QUE_ARB_THRD_RDY_ERROR_E5_SHIFT                                           20
+  #define PSEM_REG_INT_STS_WR_0_SYNC_FOC_FIFO_ERROR_E5                                                       (0x1<<21) // Error indication on FOC sync FIFO.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_FOC_FIFO_ERROR_E5_SHIFT                                                 21
+  #define PSEM_REG_INT_STS_WR_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                   (0x1<<22) // The error indicates on an error of one the threads READY queues.
+  #define PSEM_REG_INT_STS_WR_0_PB_QUE_ARB_QUEUES_ERROR_E5_SHIFT                                             22
+  #define PSEM_REG_INT_STS_WR_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5                                             (0x1<<23) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define PSEM_REG_INT_STS_WR_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5_SHIFT                                       23
+  #define PSEM_REG_INT_STS_WR_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5                                             (0x1<<24) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define PSEM_REG_INT_STS_WR_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5_SHIFT                                       24
+  #define PSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC0_E5                                                         (0x1<<25) // FOC0 is out of credit.
+  #define PSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC0_E5_SHIFT                                                   25
+  #define PSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC1_E5                                                         (0x1<<26) // FOC1 is out of credit.
+  #define PSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC1_E5_SHIFT                                                   26
+  #define PSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC2_E5                                                         (0x1<<27) // FOC2 is out of credit.
+  #define PSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC2_E5_SHIFT                                                   27
+  #define PSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC3_E5                                                         (0x1<<28) // FOC3 is out of credit.
+  #define PSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC3_E5_SHIFT                                                   28
+  #define PSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC4_E5                                                         (0x1<<29) // FOC4 is out of credit.
+  #define PSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC4_E5_SHIFT                                                   29
+  #define PSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC5_E5                                                         (0x1<<30) // FOC5 is out of credit.
+  #define PSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC5_E5_SHIFT                                                   30
+  #define PSEM_REG_INT_STS_WR_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                  (0x1<<31) // Error indication of foc pre_fetch fifo.
+  #define PSEM_REG_INT_STS_WR_0_FOC_PRE_FETCH_FIFO_ERROR_E5_SHIFT                                            31
+  #define PSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR_BB_K2                                                     (0x1<<4) // Error in Ext PAS_FIFO is active.
+  #define PSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR_BB_K2_SHIFT                                               4
+  #define PSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR_BB_K2                                                     (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR_BB_K2_SHIFT                                               5
+  #define PSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2                                                 (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2_SHIFT                                           6
+  #define PSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR_BB_K2                                                  (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT                                            7
+  #define PSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2                                                 (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT                                           8
+  #define PSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR_BB_K2                                                  (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR_BB_K2_SHIFT                                            9
+  #define PSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR_BB_K2                                                    (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR_BB_K2_SHIFT                                              10
+  #define PSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR_BB_K2                                                 (0x1<<11) // Signals an unknown address in the fast-memory window.
+  #define PSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR_BB_K2_SHIFT                                           11
+  #define PSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO_BB_K2                                                       (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
+  #define PSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO_BB_K2_SHIFT                                                 12
+  #define PSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO_BB_K2                                                       (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
+  #define PSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO_BB_K2_SHIFT                                                 13
+  #define PSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO_BB_K2                                                           (0x1<<14) // Error in CAM_OUT fifo in cam block.
+  #define PSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO_BB_K2_SHIFT                                                     14
+  #define PSEM_REG_INT_STS_WR_0_FIN_FIFO_BB_K2                                                               (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
+  #define PSEM_REG_INT_STS_WR_0_FIN_FIFO_BB_K2_SHIFT                                                         15
+  #define PSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR_BB_K2                                                      (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
+  #define PSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR_BB_K2_SHIFT                                                16
+  #define PSEM_REG_INT_STS_WR_0_THREAD_OVERRUN_BB_K2                                                         (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
+  #define PSEM_REG_INT_STS_WR_0_THREAD_OVERRUN_BB_K2_SHIFT                                                   17
+  #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2                                              (0x1<<18) // Error in external store sync FIFO push logic.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2_SHIFT                                        18
+  #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_BB_K2                                               (0x1<<19) // Error in external store sync FIFO pop logic.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_BB_K2_SHIFT                                         19
+  #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2                                               (0x1<<20) // Error in external load sync FIFO push logic.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2_SHIFT                                         20
+  #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2                                                (0x1<<21) // Error in external load sync FIFO pop logic.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2_SHIFT                                          21
+  #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR_BB_K2                                                  (0x1<<24) // Error in LS_SYNC_POP FIFO.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR_BB_K2_SHIFT                                            24
+  #define PSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR_BB_K2                                                    (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR_BB_K2_SHIFT                                              26
+  #define PSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_BB_K2                                                     (0x1<<27) // Error in LS_SYNC_POP FIFO.
+  #define PSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_BB_K2_SHIFT                                               27
+  #define PSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO_BB_K2                                                      (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
+  #define PSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO_BB_K2_SHIFT                                                29
+  #define PSEM_REG_INT_STS_WR_0_VFC_INTERRUPT_BB_K2                                                          (0x1<<30) // Error interrupt in VFC block.
+  #define PSEM_REG_INT_STS_WR_0_VFC_INTERRUPT_BB_K2_SHIFT                                                    30
+  #define PSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR_BB_K2                                                     (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
+  #define PSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR_BB_K2_SHIFT                                               31
+#define PSEM_REG_INT_STS_CLR_0                                                                               0x160004cUL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define PSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                               (0x1<<0) // Signals an unknown address to the rf module.
+  #define PSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                         0
+  #define PSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR                                                              (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
+  #define PSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR_SHIFT                                                        1
+  #define PSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR                                                            (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
+  #define PSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR_SHIFT                                                      2
+  #define PSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR                                                              (0x1<<3) // Error in any one of the FIC FIFO is active.
+  #define PSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR_SHIFT                                                        3
+  #define PSEM_REG_INT_STS_CLR_0_DRA_RD_A_LAST_ERROR_E5                                                      (0x1<<4) // DRA_RD_A last indication was unexpectedly received or was not received at expected time.
+  #define PSEM_REG_INT_STS_CLR_0_DRA_RD_A_LAST_ERROR_E5_SHIFT                                                4
+  #define PSEM_REG_INT_STS_CLR_0_DRA_RD_B_LAST_ERROR_E5                                                      (0x1<<5) // DRA_RD_B last indication was unexpectedly received or was not received at expected time.
+  #define PSEM_REG_INT_STS_CLR_0_DRA_RD_B_LAST_ERROR_E5_SHIFT                                                5
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_A_E5                                               (0x1<<6) // Error in external store slow sync FIFO pop logic of Storm A.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_A_E5_SHIFT                                         6
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_B_E5                                               (0x1<<7) // Error in external store slow sync FIFO pop logic of Storm B.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT                                         7
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5                                               (0x1<<8) // Error in external load sync slow FIFO push logic.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT                                         8
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5                                               (0x1<<9) // Error in external load sync slow FIFO pop logic.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5_SHIFT                                         9
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2                                                (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2_SHIFT                                          22
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_E5                                                   (0x1<<10) // Error in slow LS_SYNC_PUSH FIFO.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_E5_SHIFT                                             10
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_BB_K2                                                 (0x1<<23) // Error in LS_SYNC_POP FIFO.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_BB_K2_SHIFT                                           23
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_E5                                                    (0x1<<11) // Error in slow LS_SYNC_POP FIFO.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_E5_SHIFT                                              11
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2                                                (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2_SHIFT                                          25
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_E5                                                   (0x1<<12) // Error in slow LS_SYNC_PUSH FIFO.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_E5_SHIFT                                             12
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_A_E5                                                     (0x1<<13) // Error in slow LS_SYNC_PUSH FIFO.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_A_E5_SHIFT                                               13
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_B_E5                                                     (0x1<<14) // Error in slow LS_SYNC_POP FIFO.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_B_E5_SHIFT                                               14
+  #define PSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_BB_K2                                                        (0x1<<28) // Error in slow debug fifo.
+  #define PSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_BB_K2_SHIFT                                                  28
+  #define PSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_E5                                                           (0x1<<15) // Error in slow debug fifo
+  #define PSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_E5_SHIFT                                                     15
+  #define PSEM_REG_INT_STS_CLR_0_EXT_THREAD_OOR_ERROR_E5                                                     (0x1<<16) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define PSEM_REG_INT_STS_CLR_0_EXT_THREAD_OOR_ERROR_E5_SHIFT                                               16
+  #define PSEM_REG_INT_STS_CLR_0_EXT_STORE_TAG_ODER_ERROR_E5                                                 (0x1<<17) // Error detected in the ext Stroe interface internal TAG order ID.
+  #define PSEM_REG_INT_STS_CLR_0_EXT_STORE_TAG_ODER_ERROR_E5_SHIFT                                           17
+  #define PSEM_REG_INT_STS_CLR_0_FIC1_AFFINITY_FIELD_ERROR_E5                                                (0x1<<18) // Indicates that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
+  #define PSEM_REG_INT_STS_CLR_0_FIC1_AFFINITY_FIELD_ERROR_E5_SHIFT                                          18
+  #define PSEM_REG_INT_STS_CLR_0_EXT_LD_LEN_ERROR_E5                                                         (0x1<<19) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define PSEM_REG_INT_STS_CLR_0_EXT_LD_LEN_ERROR_E5_SHIFT                                                   19
+  #define PSEM_REG_INT_STS_CLR_0_PB_QUE_ARB_THRD_RDY_ERROR_E5                                                (0x1<<20) // Indicates that Passive Buffer State machine has unexpectedly received a ready indication in the following cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pending FOC" or "Ready FOC" state. b. Pending Ready indication is already asserted.
+  #define PSEM_REG_INT_STS_CLR_0_PB_QUE_ARB_THRD_RDY_ERROR_E5_SHIFT                                          20
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_FOC_FIFO_ERROR_E5                                                      (0x1<<21) // Error indication on FOC sync FIFO.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_FOC_FIFO_ERROR_E5_SHIFT                                                21
+  #define PSEM_REG_INT_STS_CLR_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                  (0x1<<22) // The error indicates on an error of one the threads READY queues.
+  #define PSEM_REG_INT_STS_CLR_0_PB_QUE_ARB_QUEUES_ERROR_E5_SHIFT                                            22
+  #define PSEM_REG_INT_STS_CLR_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5                                            (0x1<<23) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define PSEM_REG_INT_STS_CLR_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5_SHIFT                                      23
+  #define PSEM_REG_INT_STS_CLR_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5                                            (0x1<<24) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define PSEM_REG_INT_STS_CLR_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5_SHIFT                                      24
+  #define PSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC0_E5                                                        (0x1<<25) // FOC0 is out of credit.
+  #define PSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC0_E5_SHIFT                                                  25
+  #define PSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC1_E5                                                        (0x1<<26) // FOC1 is out of credit.
+  #define PSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC1_E5_SHIFT                                                  26
+  #define PSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC2_E5                                                        (0x1<<27) // FOC2 is out of credit.
+  #define PSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC2_E5_SHIFT                                                  27
+  #define PSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC3_E5                                                        (0x1<<28) // FOC3 is out of credit.
+  #define PSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC3_E5_SHIFT                                                  28
+  #define PSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC4_E5                                                        (0x1<<29) // FOC4 is out of credit.
+  #define PSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC4_E5_SHIFT                                                  29
+  #define PSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC5_E5                                                        (0x1<<30) // FOC5 is out of credit.
+  #define PSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC5_E5_SHIFT                                                  30
+  #define PSEM_REG_INT_STS_CLR_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                 (0x1<<31) // Error indication of foc pre_fetch fifo.
+  #define PSEM_REG_INT_STS_CLR_0_FOC_PRE_FETCH_FIFO_ERROR_E5_SHIFT                                           31
+  #define PSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR_BB_K2                                                    (0x1<<4) // Error in Ext PAS_FIFO is active.
+  #define PSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR_BB_K2_SHIFT                                              4
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR_BB_K2                                                    (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR_BB_K2_SHIFT                                              5
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2                                                (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2_SHIFT                                          6
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR_BB_K2                                                 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT                                           7
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2                                                (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT                                          8
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR_BB_K2                                                 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR_BB_K2_SHIFT                                           9
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR_BB_K2                                                   (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR_BB_K2_SHIFT                                             10
+  #define PSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR_BB_K2                                                (0x1<<11) // Signals an unknown address in the fast-memory window.
+  #define PSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR_BB_K2_SHIFT                                          11
+  #define PSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO_BB_K2                                                      (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
+  #define PSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO_BB_K2_SHIFT                                                12
+  #define PSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO_BB_K2                                                      (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
+  #define PSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO_BB_K2_SHIFT                                                13
+  #define PSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO_BB_K2                                                          (0x1<<14) // Error in CAM_OUT fifo in cam block.
+  #define PSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO_BB_K2_SHIFT                                                    14
+  #define PSEM_REG_INT_STS_CLR_0_FIN_FIFO_BB_K2                                                              (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
+  #define PSEM_REG_INT_STS_CLR_0_FIN_FIFO_BB_K2_SHIFT                                                        15
+  #define PSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR_BB_K2                                                     (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
+  #define PSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR_BB_K2_SHIFT                                               16
+  #define PSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN_BB_K2                                                        (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
+  #define PSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN_BB_K2_SHIFT                                                  17
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2                                             (0x1<<18) // Error in external store sync FIFO push logic.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2_SHIFT                                       18
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_BB_K2                                              (0x1<<19) // Error in external store sync FIFO pop logic.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_BB_K2_SHIFT                                        19
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2                                              (0x1<<20) // Error in external load sync FIFO push logic.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2_SHIFT                                        20
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2                                               (0x1<<21) // Error in external load sync FIFO pop logic.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2_SHIFT                                         21
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR_BB_K2                                                 (0x1<<24) // Error in LS_SYNC_POP FIFO.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR_BB_K2_SHIFT                                           24
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR_BB_K2                                                   (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR_BB_K2_SHIFT                                             26
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_BB_K2                                                    (0x1<<27) // Error in LS_SYNC_POP FIFO.
+  #define PSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_BB_K2_SHIFT                                              27
+  #define PSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO_BB_K2                                                     (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
+  #define PSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO_BB_K2_SHIFT                                               29
+  #define PSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT_BB_K2                                                         (0x1<<30) // Error interrupt in VFC block.
+  #define PSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT_BB_K2_SHIFT                                                   30
+  #define PSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR_BB_K2                                                    (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
+  #define PSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR_BB_K2_SHIFT                                              31
+#define PSEM_REG_INT_STS_1                                                                                   0x1600050UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define PSEM_REG_INT_STS_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5                                              (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
+  #define PSEM_REG_INT_STS_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5_SHIFT                                        0
+  #define PSEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_A_E5                                                  (0x1<<1) // Fast external store FIFO error of Storm_A
+  #define PSEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT                                            1
+  #define PSEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_B_E5                                                  (0x1<<2) // Fast external store FIFO error of Storm_B
+  #define PSEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_B_E5_SHIFT                                            2
+  #define PSEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_A_E5                                                    (0x1<<3) // fast external load FIFO error of Storm_A
+  #define PSEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT                                              3
+  #define PSEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_B_E5                                                    (0x1<<4) // fast external load FIFO error of Storm_B
+  #define PSEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_B_E5_SHIFT                                              4
+  #define PSEM_REG_INT_STS_1_FAST_RAM_WR_POP_ERROR_E5                                                        (0x1<<5) // Internal RAM pop error
+  #define PSEM_REG_INT_STS_1_FAST_RAM_WR_POP_ERROR_E5_SHIFT                                                  5
+  #define PSEM_REG_INT_STS_1_FAST_RAM_RD_PUSH_ERROR_E5                                                       (0x1<<6) // Internal RAM write error
+  #define PSEM_REG_INT_STS_1_FAST_RAM_RD_PUSH_ERROR_E5_SHIFT                                                 6
+  #define PSEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_A_E5                                                     (0x1<<7) // DRA RD FIFO error of Storm A
+  #define PSEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT                                               7
+  #define PSEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_B_E5                                                     (0x1<<8) // DRA RD FIFO error of Storm B
+  #define PSEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT                                               8
+  #define PSEM_REG_INT_STS_1_FAST_DRA_WR_POP_ERROR_A_E5                                                      (0x1<<9) // DRA RD FIFO error of Storm A
+  #define PSEM_REG_INT_STS_1_FAST_DRA_WR_POP_ERROR_A_E5_SHIFT                                                9
+  #define PSEM_REG_INT_STS_1_FAST_DRA_WR_POP_ERROR_B_E5                                                      (0x1<<10) // DRA RD FIFO error of Storm B
+  #define PSEM_REG_INT_STS_1_FAST_DRA_WR_POP_ERROR_B_E5_SHIFT                                                10
+  #define PSEM_REG_INT_STS_1_SEM_FAST_INVLD_ADDR_ERR_E5                                                      (0x1<<11) // Fast invalid address error
+  #define PSEM_REG_INT_STS_1_SEM_FAST_INVLD_ADDR_ERR_E5_SHIFT                                                11
+  #define PSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_A_E5                                                        (0x1<<12) // Storm A stack_uf_attn interrupt
+  #define PSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_A_E5_SHIFT                                                  12
+  #define PSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_B_E5                                                        (0x1<<13) // Storm B stack_uf_attn interrupt
+  #define PSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_B_E5_SHIFT                                                  13
+  #define PSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_A_E5                                                        (0x1<<14) // Storm A stack_of_attn interrupt
+  #define PSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_A_E5_SHIFT                                                  14
+  #define PSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_B_E5                                                        (0x1<<15) // Storm B stack_of_attn interrupt
+  #define PSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_B_E5_SHIFT                                                  15
+  #define PSEM_REG_INT_STS_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5                                                 (0x1<<16) // Storm A ldst_addr_ovflw_attn interrupt
+  #define PSEM_REG_INT_STS_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5_SHIFT                                           16
+  #define PSEM_REG_INT_STS_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5                                                 (0x1<<17) // Storm B ldst_addr_ovflw_attn interrupt
+  #define PSEM_REG_INT_STS_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5_SHIFT                                           17
+  #define PSEM_REG_INT_STS_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5                                              (0x1<<18) // Storm A non_aligned_access_attn interrupt
+  #define PSEM_REG_INT_STS_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5_SHIFT                                        18
+  #define PSEM_REG_INT_STS_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5                                              (0x1<<19) // Storm B non_aligned_access_attn interrupt
+  #define PSEM_REG_INT_STS_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5_SHIFT                                        19
+  #define PSEM_REG_INT_STS_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5                                                (0x1<<20) // Storm A division_by_zero_attn interrupt
+  #define PSEM_REG_INT_STS_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5_SHIFT                                          20
+  #define PSEM_REG_INT_STS_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5                                                (0x1<<21) // Storm B division_by_zero_attn interrupt
+  #define PSEM_REG_INT_STS_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5_SHIFT                                          21
+  #define PSEM_REG_INT_STS_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5                                           (0x1<<22) // Storm A illegal_runtime_value_attn interrupt
+  #define PSEM_REG_INT_STS_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5_SHIFT                                     22
+  #define PSEM_REG_INT_STS_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5                                           (0x1<<23) // Storm B illegal_runtime_value_attn interrupt
+  #define PSEM_REG_INT_STS_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5_SHIFT                                     23
+  #define PSEM_REG_INT_STS_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5                                            (0x1<<24) // load request is made while previous is still active; not fully read, Storm A
+  #define PSEM_REG_INT_STS_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5_SHIFT                                      24
+  #define PSEM_REG_INT_STS_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5                                            (0x1<<25) // load request is made while previous is still active; not fully read, Storm B
+  #define PSEM_REG_INT_STS_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5_SHIFT                                      25
+  #define PSEM_REG_INT_STS_1_CAM_RBC_FAST_OUT_ERROR_A_E5                                                     (0x1<<26) // Error in CAM_OUT fifo in cam block of STORM A
+  #define PSEM_REG_INT_STS_1_CAM_RBC_FAST_OUT_ERROR_A_E5_SHIFT                                               26
+  #define PSEM_REG_INT_STS_1_CAM_RBC_FAST_OUT_ERROR_B_E5                                                     (0x1<<27) // Error in CAM_OUT fifo in cam block of STORM B
+  #define PSEM_REG_INT_STS_1_CAM_RBC_FAST_OUT_ERROR_B_E5_SHIFT                                               27
+  #define PSEM_REG_INT_STS_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5                                                 (0x1<<28) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define PSEM_REG_INT_STS_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5_SHIFT                                           28
+  #define PSEM_REG_INT_STS_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5                                                 (0x1<<29) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define PSEM_REG_INT_STS_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5_SHIFT                                           29
+  #define PSEM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5                                                 (0x1<<30) // Error in CAM_LSB_INP fifo in cam block of STORM A
+  #define PSEM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT                                           30
+  #define PSEM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5                                                 (0x1<<31) // Error in CAM_LSB_INP fifo in cam block of STORM B.
+  #define PSEM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5_SHIFT                                           31
+  #define PSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_BB_K2                                                       (0x1<<0) // An underflow error was detected in the Storm stack.
+  #define PSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_BB_K2_SHIFT                                                 0
+  #define PSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_BB_K2                                                       (0x1<<1) // An overflow error was detected in the Storm stack.
+  #define PSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT                                                 1
+  #define PSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR_BB_K2                                                       (0x1<<2) // The Storm detected an illegal runtime value.
+  #define PSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR_BB_K2_SHIFT                                                 2
+  #define PSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR_BB_K2                                                    (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
+  #define PSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT                                              3
+  #define PSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR_BB_K2                                                     (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
+  #define PSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR_BB_K2_SHIFT                                               4
+  #define PSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR_BB_K2                                                     (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
+  #define PSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR_BB_K2_SHIFT                                               5
+  #define PSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR_BB_K2                                                      (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
+  #define PSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR_BB_K2_SHIFT                                                6
+  #define PSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR_BB_K2                                                      (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define PSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT                                                7
+  #define PSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR_BB_K2                                                         (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
+  #define PSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT                                                   8
+  #define PSEM_REG_INT_STS_1_INVLD_FOC_ERROR_BB_K2                                                           (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
+  #define PSEM_REG_INT_STS_1_INVLD_FOC_ERROR_BB_K2_SHIFT                                                     9
+  #define PSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR_BB_K2                                                          (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define PSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR_BB_K2_SHIFT                                                    10
+  #define PSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR_BB_K2                                                       (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
+  #define PSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR_BB_K2_SHIFT                                                 11
+  #define PSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR_BB_K2                                                      (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
+  #define PSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR_BB_K2_SHIFT                                                12
+#define PSEM_REG_INT_MASK_1                                                                                  0x1600054UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define PSEM_REG_INT_MASK_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5                                             (0x1<<0) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.RBC_COMMON_ACCESS_COL_VFC_ERROR .
+  #define PSEM_REG_INT_MASK_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5_SHIFT                                       0
+  #define PSEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_A_E5                                                 (0x1<<1) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.FAST_EXT_STORE_PUSH_ERROR_A .
+  #define PSEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT                                           1
+  #define PSEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_B_E5                                                 (0x1<<2) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.FAST_EXT_STORE_PUSH_ERROR_B .
+  #define PSEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_B_E5_SHIFT                                           2
+  #define PSEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_A_E5                                                   (0x1<<3) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.FAST_EXT_LOAD_POP_ERROR_A .
+  #define PSEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT                                             3
+  #define PSEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_B_E5                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.FAST_EXT_LOAD_POP_ERROR_B .
+  #define PSEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_B_E5_SHIFT                                             4
+  #define PSEM_REG_INT_MASK_1_FAST_RAM_WR_POP_ERROR_E5                                                       (0x1<<5) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.FAST_RAM_WR_POP_ERROR .
+  #define PSEM_REG_INT_MASK_1_FAST_RAM_WR_POP_ERROR_E5_SHIFT                                                 5
+  #define PSEM_REG_INT_MASK_1_FAST_RAM_RD_PUSH_ERROR_E5                                                      (0x1<<6) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.FAST_RAM_RD_PUSH_ERROR .
+  #define PSEM_REG_INT_MASK_1_FAST_RAM_RD_PUSH_ERROR_E5_SHIFT                                                6
+  #define PSEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_A_E5                                                    (0x1<<7) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.FAST_DRA_RD_PUSH_ERROR_A .
+  #define PSEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT                                              7
+  #define PSEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_B_E5                                                    (0x1<<8) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.FAST_DRA_RD_PUSH_ERROR_B .
+  #define PSEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT                                              8
+  #define PSEM_REG_INT_MASK_1_FAST_DRA_WR_POP_ERROR_A_E5                                                     (0x1<<9) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.FAST_DRA_WR_POP_ERROR_A .
+  #define PSEM_REG_INT_MASK_1_FAST_DRA_WR_POP_ERROR_A_E5_SHIFT                                               9
+  #define PSEM_REG_INT_MASK_1_FAST_DRA_WR_POP_ERROR_B_E5                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.FAST_DRA_WR_POP_ERROR_B .
+  #define PSEM_REG_INT_MASK_1_FAST_DRA_WR_POP_ERROR_B_E5_SHIFT                                               10
+  #define PSEM_REG_INT_MASK_1_SEM_FAST_INVLD_ADDR_ERR_E5                                                     (0x1<<11) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.SEM_FAST_INVLD_ADDR_ERR .
+  #define PSEM_REG_INT_MASK_1_SEM_FAST_INVLD_ADDR_ERR_E5_SHIFT                                               11
+  #define PSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_A_E5                                                       (0x1<<12) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN_A .
+  #define PSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_A_E5_SHIFT                                                 12
+  #define PSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_B_E5                                                       (0x1<<13) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN_B .
+  #define PSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_B_E5_SHIFT                                                 13
+  #define PSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_A_E5                                                       (0x1<<14) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN_A .
+  #define PSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_A_E5_SHIFT                                                 14
+  #define PSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_B_E5                                                       (0x1<<15) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN_B .
+  #define PSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_B_E5_SHIFT                                                 15
+  #define PSEM_REG_INT_MASK_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5                                                (0x1<<16) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.STORM_LDST_ADDR_OVFLW_ATTN_A .
+  #define PSEM_REG_INT_MASK_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5_SHIFT                                          16
+  #define PSEM_REG_INT_MASK_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5                                                (0x1<<17) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.STORM_LDST_ADDR_OVFLW_ATTN_B .
+  #define PSEM_REG_INT_MASK_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5_SHIFT                                          17
+  #define PSEM_REG_INT_MASK_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5                                             (0x1<<18) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.STORM_NON_ALIGNED_ACCESS_ATTN_A .
+  #define PSEM_REG_INT_MASK_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5_SHIFT                                       18
+  #define PSEM_REG_INT_MASK_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5                                             (0x1<<19) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.STORM_NON_ALIGNED_ACCESS_ATTN_B .
+  #define PSEM_REG_INT_MASK_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5_SHIFT                                       19
+  #define PSEM_REG_INT_MASK_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5                                               (0x1<<20) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.STORM_DIVISION_BY_ZERO_ATTN_A .
+  #define PSEM_REG_INT_MASK_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5_SHIFT                                         20
+  #define PSEM_REG_INT_MASK_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5                                               (0x1<<21) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.STORM_DIVISION_BY_ZERO_ATTN_B .
+  #define PSEM_REG_INT_MASK_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5_SHIFT                                         21
+  #define PSEM_REG_INT_MASK_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5                                          (0x1<<22) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A .
+  #define PSEM_REG_INT_MASK_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5_SHIFT                                    22
+  #define PSEM_REG_INT_MASK_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5                                          (0x1<<23) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B .
+  #define PSEM_REG_INT_MASK_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5_SHIFT                                    23
+  #define PSEM_REG_INT_MASK_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5                                           (0x1<<24) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A .
+  #define PSEM_REG_INT_MASK_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5_SHIFT                                     24
+  #define PSEM_REG_INT_MASK_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5                                           (0x1<<25) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B .
+  #define PSEM_REG_INT_MASK_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5_SHIFT                                     25
+  #define PSEM_REG_INT_MASK_1_CAM_RBC_FAST_OUT_ERROR_A_E5                                                    (0x1<<26) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.CAM_RBC_FAST_OUT_ERROR_A .
+  #define PSEM_REG_INT_MASK_1_CAM_RBC_FAST_OUT_ERROR_A_E5_SHIFT                                              26
+  #define PSEM_REG_INT_MASK_1_CAM_RBC_FAST_OUT_ERROR_B_E5                                                    (0x1<<27) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.CAM_RBC_FAST_OUT_ERROR_B .
+  #define PSEM_REG_INT_MASK_1_CAM_RBC_FAST_OUT_ERROR_B_E5_SHIFT                                              27
+  #define PSEM_REG_INT_MASK_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5                                                (0x1<<28) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.CAM_RBC_FAST_MSB_INP_ERROR_A .
+  #define PSEM_REG_INT_MASK_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5_SHIFT                                          28
+  #define PSEM_REG_INT_MASK_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5                                                (0x1<<29) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.CAM_RBC_FAST_MSB_INP_ERROR_B .
+  #define PSEM_REG_INT_MASK_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5_SHIFT                                          29
+  #define PSEM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5                                                (0x1<<30) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.CAM_RBC_FAST_LSB_INP_ERROR_A .
+  #define PSEM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT                                          30
+  #define PSEM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5                                                (0x1<<31) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.CAM_RBC_FAST_LSB_INP_ERROR_B .
+  #define PSEM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5_SHIFT                                          31
+  #define PSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_BB_K2                                                      (0x1<<0) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN .
+  #define PSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_BB_K2_SHIFT                                                0
+  #define PSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_BB_K2                                                      (0x1<<1) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN .
+  #define PSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT                                                1
+  #define PSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR_BB_K2                                                      (0x1<<2) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.STORM_RUNTIME_ERROR .
+  #define PSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR_BB_K2_SHIFT                                                2
+  #define PSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR_BB_K2                                                   (0x1<<3) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.EXT_LOAD_PEND_WR_ERROR .
+  #define PSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT                                             3
+  #define PSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR_BB_K2                                                    (0x1<<4) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.THREAD_RLS_ORUN_ERROR .
+  #define PSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR_BB_K2_SHIFT                                              4
+  #define PSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR_BB_K2                                                    (0x1<<5) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.THREAD_RLS_ALOC_ERROR .
+  #define PSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR_BB_K2_SHIFT                                              5
+  #define PSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR_BB_K2                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.THREAD_RLS_VLD_ERROR .
+  #define PSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR_BB_K2_SHIFT                                               6
+  #define PSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR_BB_K2                                                     (0x1<<7) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.EXT_THREAD_OOR_ERROR .
+  #define PSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT                                               7
+  #define PSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR_BB_K2                                                        (0x1<<8) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.ORD_ID_FIFO_ERROR .
+  #define PSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT                                                  8
+  #define PSEM_REG_INT_MASK_1_INVLD_FOC_ERROR_BB_K2                                                          (0x1<<9) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.INVLD_FOC_ERROR .
+  #define PSEM_REG_INT_MASK_1_INVLD_FOC_ERROR_BB_K2_SHIFT                                                    9
+  #define PSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR_BB_K2                                                         (0x1<<10) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.EXT_LD_LEN_ERROR .
+  #define PSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR_BB_K2_SHIFT                                                   10
+  #define PSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR_BB_K2                                                      (0x1<<11) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.THRD_ORD_FIFO_ERROR .
+  #define PSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR_BB_K2_SHIFT                                                11
+  #define PSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR_BB_K2                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.INVLD_THRD_ORD_ERROR .
+  #define PSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR_BB_K2_SHIFT                                               12
+#define PSEM_REG_INT_STS_WR_1                                                                                0x1600058UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define PSEM_REG_INT_STS_WR_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5                                           (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
+  #define PSEM_REG_INT_STS_WR_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5_SHIFT                                     0
+  #define PSEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5                                               (0x1<<1) // Fast external store FIFO error of Storm_A
+  #define PSEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT                                         1
+  #define PSEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_B_E5                                               (0x1<<2) // Fast external store FIFO error of Storm_B
+  #define PSEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_B_E5_SHIFT                                         2
+  #define PSEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_A_E5                                                 (0x1<<3) // fast external load FIFO error of Storm_A
+  #define PSEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT                                           3
+  #define PSEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_B_E5                                                 (0x1<<4) // fast external load FIFO error of Storm_B
+  #define PSEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_B_E5_SHIFT                                           4
+  #define PSEM_REG_INT_STS_WR_1_FAST_RAM_WR_POP_ERROR_E5                                                     (0x1<<5) // Internal RAM pop error
+  #define PSEM_REG_INT_STS_WR_1_FAST_RAM_WR_POP_ERROR_E5_SHIFT                                               5
+  #define PSEM_REG_INT_STS_WR_1_FAST_RAM_RD_PUSH_ERROR_E5                                                    (0x1<<6) // Internal RAM write error
+  #define PSEM_REG_INT_STS_WR_1_FAST_RAM_RD_PUSH_ERROR_E5_SHIFT                                              6
+  #define PSEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_A_E5                                                  (0x1<<7) // DRA RD FIFO error of Storm A
+  #define PSEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT                                            7
+  #define PSEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_B_E5                                                  (0x1<<8) // DRA RD FIFO error of Storm B
+  #define PSEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT                                            8
+  #define PSEM_REG_INT_STS_WR_1_FAST_DRA_WR_POP_ERROR_A_E5                                                   (0x1<<9) // DRA RD FIFO error of Storm A
+  #define PSEM_REG_INT_STS_WR_1_FAST_DRA_WR_POP_ERROR_A_E5_SHIFT                                             9
+  #define PSEM_REG_INT_STS_WR_1_FAST_DRA_WR_POP_ERROR_B_E5                                                   (0x1<<10) // DRA RD FIFO error of Storm B
+  #define PSEM_REG_INT_STS_WR_1_FAST_DRA_WR_POP_ERROR_B_E5_SHIFT                                             10
+  #define PSEM_REG_INT_STS_WR_1_SEM_FAST_INVLD_ADDR_ERR_E5                                                   (0x1<<11) // Fast invalid address error
+  #define PSEM_REG_INT_STS_WR_1_SEM_FAST_INVLD_ADDR_ERR_E5_SHIFT                                             11
+  #define PSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_A_E5                                                     (0x1<<12) // Storm A stack_uf_attn interrupt
+  #define PSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_A_E5_SHIFT                                               12
+  #define PSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_B_E5                                                     (0x1<<13) // Storm B stack_uf_attn interrupt
+  #define PSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_B_E5_SHIFT                                               13
+  #define PSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_A_E5                                                     (0x1<<14) // Storm A stack_of_attn interrupt
+  #define PSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_A_E5_SHIFT                                               14
+  #define PSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_B_E5                                                     (0x1<<15) // Storm B stack_of_attn interrupt
+  #define PSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_B_E5_SHIFT                                               15
+  #define PSEM_REG_INT_STS_WR_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5                                              (0x1<<16) // Storm A ldst_addr_ovflw_attn interrupt
+  #define PSEM_REG_INT_STS_WR_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5_SHIFT                                        16
+  #define PSEM_REG_INT_STS_WR_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5                                              (0x1<<17) // Storm B ldst_addr_ovflw_attn interrupt
+  #define PSEM_REG_INT_STS_WR_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5_SHIFT                                        17
+  #define PSEM_REG_INT_STS_WR_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5                                           (0x1<<18) // Storm A non_aligned_access_attn interrupt
+  #define PSEM_REG_INT_STS_WR_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5_SHIFT                                     18
+  #define PSEM_REG_INT_STS_WR_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5                                           (0x1<<19) // Storm B non_aligned_access_attn interrupt
+  #define PSEM_REG_INT_STS_WR_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5_SHIFT                                     19
+  #define PSEM_REG_INT_STS_WR_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5                                             (0x1<<20) // Storm A division_by_zero_attn interrupt
+  #define PSEM_REG_INT_STS_WR_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5_SHIFT                                       20
+  #define PSEM_REG_INT_STS_WR_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5                                             (0x1<<21) // Storm B division_by_zero_attn interrupt
+  #define PSEM_REG_INT_STS_WR_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5_SHIFT                                       21
+  #define PSEM_REG_INT_STS_WR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5                                        (0x1<<22) // Storm A illegal_runtime_value_attn interrupt
+  #define PSEM_REG_INT_STS_WR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5_SHIFT                                  22
+  #define PSEM_REG_INT_STS_WR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5                                        (0x1<<23) // Storm B illegal_runtime_value_attn interrupt
+  #define PSEM_REG_INT_STS_WR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5_SHIFT                                  23
+  #define PSEM_REG_INT_STS_WR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5                                         (0x1<<24) // load request is made while previous is still active; not fully read, Storm A
+  #define PSEM_REG_INT_STS_WR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5_SHIFT                                   24
+  #define PSEM_REG_INT_STS_WR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5                                         (0x1<<25) // load request is made while previous is still active; not fully read, Storm B
+  #define PSEM_REG_INT_STS_WR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5_SHIFT                                   25
+  #define PSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_OUT_ERROR_A_E5                                                  (0x1<<26) // Error in CAM_OUT fifo in cam block of STORM A
+  #define PSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_OUT_ERROR_A_E5_SHIFT                                            26
+  #define PSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_OUT_ERROR_B_E5                                                  (0x1<<27) // Error in CAM_OUT fifo in cam block of STORM B
+  #define PSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_OUT_ERROR_B_E5_SHIFT                                            27
+  #define PSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5                                              (0x1<<28) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define PSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5_SHIFT                                        28
+  #define PSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5                                              (0x1<<29) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define PSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5_SHIFT                                        29
+  #define PSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5                                              (0x1<<30) // Error in CAM_LSB_INP fifo in cam block of STORM A
+  #define PSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT                                        30
+  #define PSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5                                              (0x1<<31) // Error in CAM_LSB_INP fifo in cam block of STORM B.
+  #define PSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5_SHIFT                                        31
+  #define PSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_BB_K2                                                    (0x1<<0) // An underflow error was detected in the Storm stack.
+  #define PSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_BB_K2_SHIFT                                              0
+  #define PSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_BB_K2                                                    (0x1<<1) // An overflow error was detected in the Storm stack.
+  #define PSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT                                              1
+  #define PSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR_BB_K2                                                    (0x1<<2) // The Storm detected an illegal runtime value.
+  #define PSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR_BB_K2_SHIFT                                              2
+  #define PSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2                                                 (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
+  #define PSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT                                           3
+  #define PSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR_BB_K2                                                  (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
+  #define PSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR_BB_K2_SHIFT                                            4
+  #define PSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR_BB_K2                                                  (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
+  #define PSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR_BB_K2_SHIFT                                            5
+  #define PSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR_BB_K2                                                   (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
+  #define PSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR_BB_K2_SHIFT                                             6
+  #define PSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR_BB_K2                                                   (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define PSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT                                             7
+  #define PSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR_BB_K2                                                      (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
+  #define PSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT                                                8
+  #define PSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR_BB_K2                                                        (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
+  #define PSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR_BB_K2_SHIFT                                                  9
+  #define PSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR_BB_K2                                                       (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define PSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR_BB_K2_SHIFT                                                 10
+  #define PSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR_BB_K2                                                    (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
+  #define PSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR_BB_K2_SHIFT                                              11
+  #define PSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR_BB_K2                                                   (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
+  #define PSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR_BB_K2_SHIFT                                             12
+#define PSEM_REG_INT_STS_CLR_1                                                                               0x160005cUL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define PSEM_REG_INT_STS_CLR_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5                                          (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
+  #define PSEM_REG_INT_STS_CLR_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5_SHIFT                                    0
+  #define PSEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5                                              (0x1<<1) // Fast external store FIFO error of Storm_A
+  #define PSEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT                                        1
+  #define PSEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_B_E5                                              (0x1<<2) // Fast external store FIFO error of Storm_B
+  #define PSEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_B_E5_SHIFT                                        2
+  #define PSEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_A_E5                                                (0x1<<3) // fast external load FIFO error of Storm_A
+  #define PSEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT                                          3
+  #define PSEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_B_E5                                                (0x1<<4) // fast external load FIFO error of Storm_B
+  #define PSEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_B_E5_SHIFT                                          4
+  #define PSEM_REG_INT_STS_CLR_1_FAST_RAM_WR_POP_ERROR_E5                                                    (0x1<<5) // Internal RAM pop error
+  #define PSEM_REG_INT_STS_CLR_1_FAST_RAM_WR_POP_ERROR_E5_SHIFT                                              5
+  #define PSEM_REG_INT_STS_CLR_1_FAST_RAM_RD_PUSH_ERROR_E5                                                   (0x1<<6) // Internal RAM write error
+  #define PSEM_REG_INT_STS_CLR_1_FAST_RAM_RD_PUSH_ERROR_E5_SHIFT                                             6
+  #define PSEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_A_E5                                                 (0x1<<7) // DRA RD FIFO error of Storm A
+  #define PSEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT                                           7
+  #define PSEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_B_E5                                                 (0x1<<8) // DRA RD FIFO error of Storm B
+  #define PSEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT                                           8
+  #define PSEM_REG_INT_STS_CLR_1_FAST_DRA_WR_POP_ERROR_A_E5                                                  (0x1<<9) // DRA RD FIFO error of Storm A
+  #define PSEM_REG_INT_STS_CLR_1_FAST_DRA_WR_POP_ERROR_A_E5_SHIFT                                            9
+  #define PSEM_REG_INT_STS_CLR_1_FAST_DRA_WR_POP_ERROR_B_E5                                                  (0x1<<10) // DRA RD FIFO error of Storm B
+  #define PSEM_REG_INT_STS_CLR_1_FAST_DRA_WR_POP_ERROR_B_E5_SHIFT                                            10
+  #define PSEM_REG_INT_STS_CLR_1_SEM_FAST_INVLD_ADDR_ERR_E5                                                  (0x1<<11) // Fast invalid address error
+  #define PSEM_REG_INT_STS_CLR_1_SEM_FAST_INVLD_ADDR_ERR_E5_SHIFT                                            11
+  #define PSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_A_E5                                                    (0x1<<12) // Storm A stack_uf_attn interrupt
+  #define PSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_A_E5_SHIFT                                              12
+  #define PSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_B_E5                                                    (0x1<<13) // Storm B stack_uf_attn interrupt
+  #define PSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_B_E5_SHIFT                                              13
+  #define PSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_A_E5                                                    (0x1<<14) // Storm A stack_of_attn interrupt
+  #define PSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_A_E5_SHIFT                                              14
+  #define PSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_B_E5                                                    (0x1<<15) // Storm B stack_of_attn interrupt
+  #define PSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_B_E5_SHIFT                                              15
+  #define PSEM_REG_INT_STS_CLR_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5                                             (0x1<<16) // Storm A ldst_addr_ovflw_attn interrupt
+  #define PSEM_REG_INT_STS_CLR_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5_SHIFT                                       16
+  #define PSEM_REG_INT_STS_CLR_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5                                             (0x1<<17) // Storm B ldst_addr_ovflw_attn interrupt
+  #define PSEM_REG_INT_STS_CLR_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5_SHIFT                                       17
+  #define PSEM_REG_INT_STS_CLR_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5                                          (0x1<<18) // Storm A non_aligned_access_attn interrupt
+  #define PSEM_REG_INT_STS_CLR_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5_SHIFT                                    18
+  #define PSEM_REG_INT_STS_CLR_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5                                          (0x1<<19) // Storm B non_aligned_access_attn interrupt
+  #define PSEM_REG_INT_STS_CLR_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5_SHIFT                                    19
+  #define PSEM_REG_INT_STS_CLR_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5                                            (0x1<<20) // Storm A division_by_zero_attn interrupt
+  #define PSEM_REG_INT_STS_CLR_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5_SHIFT                                      20
+  #define PSEM_REG_INT_STS_CLR_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5                                            (0x1<<21) // Storm B division_by_zero_attn interrupt
+  #define PSEM_REG_INT_STS_CLR_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5_SHIFT                                      21
+  #define PSEM_REG_INT_STS_CLR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5                                       (0x1<<22) // Storm A illegal_runtime_value_attn interrupt
+  #define PSEM_REG_INT_STS_CLR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5_SHIFT                                 22
+  #define PSEM_REG_INT_STS_CLR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5                                       (0x1<<23) // Storm B illegal_runtime_value_attn interrupt
+  #define PSEM_REG_INT_STS_CLR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5_SHIFT                                 23
+  #define PSEM_REG_INT_STS_CLR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5                                        (0x1<<24) // load request is made while previous is still active; not fully read, Storm A
+  #define PSEM_REG_INT_STS_CLR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5_SHIFT                                  24
+  #define PSEM_REG_INT_STS_CLR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5                                        (0x1<<25) // load request is made while previous is still active; not fully read, Storm B
+  #define PSEM_REG_INT_STS_CLR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5_SHIFT                                  25
+  #define PSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_OUT_ERROR_A_E5                                                 (0x1<<26) // Error in CAM_OUT fifo in cam block of STORM A
+  #define PSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_OUT_ERROR_A_E5_SHIFT                                           26
+  #define PSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_OUT_ERROR_B_E5                                                 (0x1<<27) // Error in CAM_OUT fifo in cam block of STORM B
+  #define PSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_OUT_ERROR_B_E5_SHIFT                                           27
+  #define PSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5                                             (0x1<<28) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define PSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5_SHIFT                                       28
+  #define PSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5                                             (0x1<<29) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define PSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5_SHIFT                                       29
+  #define PSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5                                             (0x1<<30) // Error in CAM_LSB_INP fifo in cam block of STORM A
+  #define PSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT                                       30
+  #define PSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5                                             (0x1<<31) // Error in CAM_LSB_INP fifo in cam block of STORM B.
+  #define PSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5_SHIFT                                       31
+  #define PSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_BB_K2                                                   (0x1<<0) // An underflow error was detected in the Storm stack.
+  #define PSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_BB_K2_SHIFT                                             0
+  #define PSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_BB_K2                                                   (0x1<<1) // An overflow error was detected in the Storm stack.
+  #define PSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT                                             1
+  #define PSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR_BB_K2                                                   (0x1<<2) // The Storm detected an illegal runtime value.
+  #define PSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR_BB_K2_SHIFT                                             2
+  #define PSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2                                                (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
+  #define PSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT                                          3
+  #define PSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR_BB_K2                                                 (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
+  #define PSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR_BB_K2_SHIFT                                           4
+  #define PSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR_BB_K2                                                 (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
+  #define PSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR_BB_K2_SHIFT                                           5
+  #define PSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR_BB_K2                                                  (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
+  #define PSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR_BB_K2_SHIFT                                            6
+  #define PSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR_BB_K2                                                  (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define PSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT                                            7
+  #define PSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR_BB_K2                                                     (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
+  #define PSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT                                               8
+  #define PSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR_BB_K2                                                       (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
+  #define PSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR_BB_K2_SHIFT                                                 9
+  #define PSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR_BB_K2                                                      (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define PSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR_BB_K2_SHIFT                                                10
+  #define PSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR_BB_K2                                                   (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
+  #define PSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR_BB_K2_SHIFT                                             11
+  #define PSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR_BB_K2                                                  (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
+  #define PSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR_BB_K2_SHIFT                                            12
+#define PSEM_REG_INT_STS_2_E5                                                                                0x1600060UL //Access:R    DataWidth:0x1f   // Multi Field Register.
+  #define PSEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5                                                 (0x1<<0) // Fast FIN FIFO error of Storm A.
+  #define PSEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5_SHIFT                                           0
+  #define PSEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5                                                 (0x1<<1) // Fast FIN FIFO error of Storm B
+  #define PSEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT                                           1
+  #define PSEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5                                               (0x1<<2) // Fast Debug FIFO error of Storm A
+  #define PSEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5_SHIFT                                         2
+  #define PSEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5                                               (0x1<<3) // Fast Debug FIFO error of Storm B
+  #define PSEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT                                         3
+  #define PSEM_REG_INT_STS_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5                                                (0x1<<4) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define PSEM_REG_INT_STS_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5_SHIFT                                          4
+  #define PSEM_REG_INT_STS_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5                                                (0x1<<5) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define PSEM_REG_INT_STS_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5_SHIFT                                          5
+  #define PSEM_REG_INT_STS_2_VFC_INTERRUPT_E5                                                                (0x1<<6) // interrupt from VFC block
+  #define PSEM_REG_INT_STS_2_VFC_INTERRUPT_E5_SHIFT                                                          6
+  #define PSEM_REG_INT_STS_2_MUX_RBC_VFC_FIFO_ERROR_E5                                                       (0x1<<7) // VFC FIFO error
+  #define PSEM_REG_INT_STS_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT                                                 7
+  #define PSEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_A_E5                                                    (0x1<<8) // Error in FOC error of Storm A.
+  #define PSEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT                                              8
+  #define PSEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_B_E5                                                    (0x1<<9) // Error in FOC error of Storm B.
+  #define PSEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_B_E5_SHIFT                                              9
+  #define PSEM_REG_INT_STS_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5                                                  (0x1<<10) // Invalid allocated thread request with partial FIN of Storm A.
+  #define PSEM_REG_INT_STS_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5_SHIFT                                            10
+  #define PSEM_REG_INT_STS_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5                                                  (0x1<<11) // Invalid allocated thread request with partial FIN of Storm B.
+  #define PSEM_REG_INT_STS_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5_SHIFT                                            11
+  #define PSEM_REG_INT_STS_2_CAM_RBC_INPUT_FIFO_ERROR_E5                                                     (0x1<<12) // Cam input FIFO error
+  #define PSEM_REG_INT_STS_2_CAM_RBC_INPUT_FIFO_ERROR_E5_SHIFT                                               12
+  #define PSEM_REG_INT_STS_2_ARB_RBC_FIFO_ERROR_A_E5                                                         (0x1<<13) // Pre-fetch FIFO error of Storm A.
+  #define PSEM_REG_INT_STS_2_ARB_RBC_FIFO_ERROR_A_E5_SHIFT                                                   13
+  #define PSEM_REG_INT_STS_2_ARB_RBC_FIFO_ERROR_B_E5                                                         (0x1<<14) // Pre-fetch FIFO error of Storm B.
+  #define PSEM_REG_INT_STS_2_ARB_RBC_FIFO_ERROR_B_E5_SHIFT                                                   14
+  #define PSEM_REG_INT_STS_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5                                                 (0x1<<15) // Lock is acquired more than maximum configured time.
+  #define PSEM_REG_INT_STS_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5_SHIFT                                           15
+  #define PSEM_REG_INT_STS_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                                  (0x1<<16) // Ilegal assetion commands towards lock block.
+  #define PSEM_REG_INT_STS_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5_SHIFT                                            16
+  #define PSEM_REG_INT_STS_2_LOCK_RBC_REQ_RELEASE_ERROR_E5                                                   (0x1<<17) // Error when trying to release a lock which is not acquired (key does not match any lock)
+  #define PSEM_REG_INT_STS_2_LOCK_RBC_REQ_RELEASE_ERROR_E5_SHIFT                                             17
+  #define PSEM_REG_INT_STS_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5                                                 (0x1<<18) // Trying to acquire a lock which is already acquired.
+  #define PSEM_REG_INT_STS_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5_SHIFT                                           18
+  #define PSEM_REG_INT_STS_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5                                                (0x1<<19) // Trying to relinquish a key which does not exist.
+  #define PSEM_REG_INT_STS_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5_SHIFT                                          19
+  #define PSEM_REG_INT_STS_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5                                                (0x1<<20) // A lock acquired requrest is issued when all locks are used.
+  #define PSEM_REG_INT_STS_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5_SHIFT                                          20
+  #define PSEM_REG_INT_STS_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5                                                (0x1<<21) // Error when both Storm are stalled due to lock block (may indicate a dead lock).
+  #define PSEM_REG_INT_STS_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5_SHIFT                                          21
+  #define PSEM_REG_INT_STS_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5                                            (0x1<<22) // Fin done with remainning allocated threads STORM_A.
+  #define PSEM_REG_INT_STS_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5_SHIFT                                      22
+  #define PSEM_REG_INT_STS_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5                                            (0x1<<23) // Fin done with remainning allocated threads STORM_B.
+  #define PSEM_REG_INT_STS_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5_SHIFT                                      23
+  #define PSEM_REG_INT_STS_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5                                            (0x1<<24) // Fin new thread request when no thread is allocated for handler of Storm A.
+  #define PSEM_REG_INT_STS_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5_SHIFT                                      24
+  #define PSEM_REG_INT_STS_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5                                            (0x1<<25) // Fin new thread request when no thread is allocated for handler of Storm B.
+  #define PSEM_REG_INT_STS_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5_SHIFT                                      25
+  #define PSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5                                      (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same range.
+  #define PSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5_SHIFT                                26
+  #define PSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5                                      (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same range.
+  #define PSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5_SHIFT                                27
+  #define PSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5                                         (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
+  #define PSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5_SHIFT                                   28
+  #define PSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5                                         (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
+  #define PSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5_SHIFT                                   29
+  #define PSEM_REG_INT_STS_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5                                          (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
+  #define PSEM_REG_INT_STS_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT                                    30
+#define PSEM_REG_INT_MASK_2_E5                                                                               0x1600064UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define PSEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5                                                (0x1<<0) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.RD_RBC_FAST_FIN_FIFO_ERROR_A .
+  #define PSEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5_SHIFT                                          0
+  #define PSEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5                                                (0x1<<1) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.RD_RBC_FAST_FIN_FIFO_ERROR_B .
+  #define PSEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT                                          1
+  #define PSEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5                                              (0x1<<2) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.SYNC_RBC_FAST_DBG_PUSH_ERROR_A .
+  #define PSEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5_SHIFT                                        2
+  #define PSEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5                                              (0x1<<3) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.SYNC_RBC_FAST_DBG_PUSH_ERROR_B .
+  #define PSEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT                                        3
+  #define PSEM_REG_INT_MASK_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5                                               (0x1<<4) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.CAM_RBC_FAST_MSB2_INP_ERROR_A .
+  #define PSEM_REG_INT_MASK_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5_SHIFT                                         4
+  #define PSEM_REG_INT_MASK_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5                                               (0x1<<5) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.CAM_RBC_FAST_MSB2_INP_ERROR_B .
+  #define PSEM_REG_INT_MASK_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5_SHIFT                                         5
+  #define PSEM_REG_INT_MASK_2_VFC_INTERRUPT_E5                                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.VFC_INTERRUPT .
+  #define PSEM_REG_INT_MASK_2_VFC_INTERRUPT_E5_SHIFT                                                         6
+  #define PSEM_REG_INT_MASK_2_MUX_RBC_VFC_FIFO_ERROR_E5                                                      (0x1<<7) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.MUX_RBC_VFC_FIFO_ERROR .
+  #define PSEM_REG_INT_MASK_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT                                                7
+  #define PSEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_A_E5                                                   (0x1<<8) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.FIN_RBC_INVLD_FOC_ERROR_A .
+  #define PSEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT                                             8
+  #define PSEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_B_E5                                                   (0x1<<9) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.FIN_RBC_INVLD_FOC_ERROR_B .
+  #define PSEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_B_E5_SHIFT                                             9
+  #define PSEM_REG_INT_MASK_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5                                                 (0x1<<10) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.FIN_RBC_INVLD_ALLOC_ERROR_A .
+  #define PSEM_REG_INT_MASK_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5_SHIFT                                           10
+  #define PSEM_REG_INT_MASK_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5                                                 (0x1<<11) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.FIN_RBC_INVLD_ALLOC_ERROR_B .
+  #define PSEM_REG_INT_MASK_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5_SHIFT                                           11
+  #define PSEM_REG_INT_MASK_2_CAM_RBC_INPUT_FIFO_ERROR_E5                                                    (0x1<<12) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.CAM_RBC_INPUT_FIFO_ERROR .
+  #define PSEM_REG_INT_MASK_2_CAM_RBC_INPUT_FIFO_ERROR_E5_SHIFT                                              12
+  #define PSEM_REG_INT_MASK_2_ARB_RBC_FIFO_ERROR_A_E5                                                        (0x1<<13) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.ARB_RBC_FIFO_ERROR_A .
+  #define PSEM_REG_INT_MASK_2_ARB_RBC_FIFO_ERROR_A_E5_SHIFT                                                  13
+  #define PSEM_REG_INT_MASK_2_ARB_RBC_FIFO_ERROR_B_E5                                                        (0x1<<14) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.ARB_RBC_FIFO_ERROR_B .
+  #define PSEM_REG_INT_MASK_2_ARB_RBC_FIFO_ERROR_B_E5_SHIFT                                                  14
+  #define PSEM_REG_INT_MASK_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5                                                (0x1<<15) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.LOCK_RBC_REQ_MAX_STALL_ERROR .
+  #define PSEM_REG_INT_MASK_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5_SHIFT                                          15
+  #define PSEM_REG_INT_MASK_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                                 (0x1<<16) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.LOCK_RBC_REQ_CMD_RATE_ERROR .
+  #define PSEM_REG_INT_MASK_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5_SHIFT                                           16
+  #define PSEM_REG_INT_MASK_2_LOCK_RBC_REQ_RELEASE_ERROR_E5                                                  (0x1<<17) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.LOCK_RBC_REQ_RELEASE_ERROR .
+  #define PSEM_REG_INT_MASK_2_LOCK_RBC_REQ_RELEASE_ERROR_E5_SHIFT                                            17
+  #define PSEM_REG_INT_MASK_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5                                                (0x1<<18) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.LOCK_RBC_REQ_REDUNDENT_ERROR .
+  #define PSEM_REG_INT_MASK_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5_SHIFT                                          18
+  #define PSEM_REG_INT_MASK_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5                                               (0x1<<19) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.LOCK_RBC_REQ_RELINQUISH_ERROR .
+  #define PSEM_REG_INT_MASK_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5_SHIFT                                         19
+  #define PSEM_REG_INT_MASK_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5                                               (0x1<<20) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.LOCK_RBC_REQ_STALL_FULL_ERROR .
+  #define PSEM_REG_INT_MASK_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5_SHIFT                                         20
+  #define PSEM_REG_INT_MASK_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5                                               (0x1<<21) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.LOCK_RBC_REQ_DUAL_STALL_ERROR .
+  #define PSEM_REG_INT_MASK_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5_SHIFT                                         21
+  #define PSEM_REG_INT_MASK_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5                                           (0x1<<22) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A .
+  #define PSEM_REG_INT_MASK_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5_SHIFT                                     22
+  #define PSEM_REG_INT_MASK_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5                                           (0x1<<23) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B .
+  #define PSEM_REG_INT_MASK_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5_SHIFT                                     23
+  #define PSEM_REG_INT_MASK_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5                                           (0x1<<24) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.DRA_INT_GRC_NON_FREE_THRD_ERROR_A .
+  #define PSEM_REG_INT_MASK_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5_SHIFT                                     24
+  #define PSEM_REG_INT_MASK_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5                                           (0x1<<25) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.DRA_INT_GRC_NON_FREE_THRD_ERROR_B .
+  #define PSEM_REG_INT_MASK_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5_SHIFT                                     25
+  #define PSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5                                     (0x1<<26) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A .
+  #define PSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5_SHIFT                               26
+  #define PSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5                                     (0x1<<27) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B .
+  #define PSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5_SHIFT                               27
+  #define PSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5                                        (0x1<<28) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A .
+  #define PSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5_SHIFT                                  28
+  #define PSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5                                        (0x1<<29) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B .
+  #define PSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5_SHIFT                                  29
+  #define PSEM_REG_INT_MASK_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5                                         (0x1<<30) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_2.SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR .
+  #define PSEM_REG_INT_MASK_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT                                   30
+#define PSEM_REG_INT_STS_WR_2_E5                                                                             0x1600068UL //Access:WR   DataWidth:0x1f   // Multi Field Register.
+  #define PSEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5                                              (0x1<<0) // Fast FIN FIFO error of Storm A.
+  #define PSEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5_SHIFT                                        0
+  #define PSEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5                                              (0x1<<1) // Fast FIN FIFO error of Storm B
+  #define PSEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT                                        1
+  #define PSEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5                                            (0x1<<2) // Fast Debug FIFO error of Storm A
+  #define PSEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5_SHIFT                                      2
+  #define PSEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5                                            (0x1<<3) // Fast Debug FIFO error of Storm B
+  #define PSEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT                                      3
+  #define PSEM_REG_INT_STS_WR_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5                                             (0x1<<4) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define PSEM_REG_INT_STS_WR_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5_SHIFT                                       4
+  #define PSEM_REG_INT_STS_WR_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5                                             (0x1<<5) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define PSEM_REG_INT_STS_WR_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5_SHIFT                                       5
+  #define PSEM_REG_INT_STS_WR_2_VFC_INTERRUPT_E5                                                             (0x1<<6) // interrupt from VFC block
+  #define PSEM_REG_INT_STS_WR_2_VFC_INTERRUPT_E5_SHIFT                                                       6
+  #define PSEM_REG_INT_STS_WR_2_MUX_RBC_VFC_FIFO_ERROR_E5                                                    (0x1<<7) // VFC FIFO error
+  #define PSEM_REG_INT_STS_WR_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT                                              7
+  #define PSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5                                                 (0x1<<8) // Error in FOC error of Storm A.
+  #define PSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT                                           8
+  #define PSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_B_E5                                                 (0x1<<9) // Error in FOC error of Storm B.
+  #define PSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_B_E5_SHIFT                                           9
+  #define PSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5                                               (0x1<<10) // Invalid allocated thread request with partial FIN of Storm A.
+  #define PSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5_SHIFT                                         10
+  #define PSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5                                               (0x1<<11) // Invalid allocated thread request with partial FIN of Storm B.
+  #define PSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5_SHIFT                                         11
+  #define PSEM_REG_INT_STS_WR_2_CAM_RBC_INPUT_FIFO_ERROR_E5                                                  (0x1<<12) // Cam input FIFO error
+  #define PSEM_REG_INT_STS_WR_2_CAM_RBC_INPUT_FIFO_ERROR_E5_SHIFT                                            12
+  #define PSEM_REG_INT_STS_WR_2_ARB_RBC_FIFO_ERROR_A_E5                                                      (0x1<<13) // Pre-fetch FIFO error of Storm A.
+  #define PSEM_REG_INT_STS_WR_2_ARB_RBC_FIFO_ERROR_A_E5_SHIFT                                                13
+  #define PSEM_REG_INT_STS_WR_2_ARB_RBC_FIFO_ERROR_B_E5                                                      (0x1<<14) // Pre-fetch FIFO error of Storm B.
+  #define PSEM_REG_INT_STS_WR_2_ARB_RBC_FIFO_ERROR_B_E5_SHIFT                                                14
+  #define PSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5                                              (0x1<<15) // Lock is acquired more than maximum configured time.
+  #define PSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5_SHIFT                                        15
+  #define PSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                               (0x1<<16) // Ilegal assetion commands towards lock block.
+  #define PSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5_SHIFT                                         16
+  #define PSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_RELEASE_ERROR_E5                                                (0x1<<17) // Error when trying to release a lock which is not acquired (key does not match any lock)
+  #define PSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_RELEASE_ERROR_E5_SHIFT                                          17
+  #define PSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5                                              (0x1<<18) // Trying to acquire a lock which is already acquired.
+  #define PSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5_SHIFT                                        18
+  #define PSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5                                             (0x1<<19) // Trying to relinquish a key which does not exist.
+  #define PSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5_SHIFT                                       19
+  #define PSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5                                             (0x1<<20) // A lock acquired requrest is issued when all locks are used.
+  #define PSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5_SHIFT                                       20
+  #define PSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5                                             (0x1<<21) // Error when both Storm are stalled due to lock block (may indicate a dead lock).
+  #define PSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5_SHIFT                                       21
+  #define PSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5                                         (0x1<<22) // Fin done with remainning allocated threads STORM_A.
+  #define PSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5_SHIFT                                   22
+  #define PSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5                                         (0x1<<23) // Fin done with remainning allocated threads STORM_B.
+  #define PSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5_SHIFT                                   23
+  #define PSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5                                         (0x1<<24) // Fin new thread request when no thread is allocated for handler of Storm A.
+  #define PSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5_SHIFT                                   24
+  #define PSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5                                         (0x1<<25) // Fin new thread request when no thread is allocated for handler of Storm B.
+  #define PSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5_SHIFT                                   25
+  #define PSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5                                   (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same range.
+  #define PSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5_SHIFT                             26
+  #define PSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5                                   (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same range.
+  #define PSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5_SHIFT                             27
+  #define PSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5                                      (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
+  #define PSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5_SHIFT                                28
+  #define PSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5                                      (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
+  #define PSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5_SHIFT                                29
+  #define PSEM_REG_INT_STS_WR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5                                       (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
+  #define PSEM_REG_INT_STS_WR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT                                 30
+#define PSEM_REG_INT_STS_CLR_2_E5                                                                            0x160006cUL //Access:RC   DataWidth:0x1f   // Multi Field Register.
+  #define PSEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5                                             (0x1<<0) // Fast FIN FIFO error of Storm A.
+  #define PSEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5_SHIFT                                       0
+  #define PSEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5                                             (0x1<<1) // Fast FIN FIFO error of Storm B
+  #define PSEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT                                       1
+  #define PSEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5                                           (0x1<<2) // Fast Debug FIFO error of Storm A
+  #define PSEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5_SHIFT                                     2
+  #define PSEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5                                           (0x1<<3) // Fast Debug FIFO error of Storm B
+  #define PSEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT                                     3
+  #define PSEM_REG_INT_STS_CLR_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5                                            (0x1<<4) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define PSEM_REG_INT_STS_CLR_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5_SHIFT                                      4
+  #define PSEM_REG_INT_STS_CLR_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5                                            (0x1<<5) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define PSEM_REG_INT_STS_CLR_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5_SHIFT                                      5
+  #define PSEM_REG_INT_STS_CLR_2_VFC_INTERRUPT_E5                                                            (0x1<<6) // interrupt from VFC block
+  #define PSEM_REG_INT_STS_CLR_2_VFC_INTERRUPT_E5_SHIFT                                                      6
+  #define PSEM_REG_INT_STS_CLR_2_MUX_RBC_VFC_FIFO_ERROR_E5                                                   (0x1<<7) // VFC FIFO error
+  #define PSEM_REG_INT_STS_CLR_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT                                             7
+  #define PSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5                                                (0x1<<8) // Error in FOC error of Storm A.
+  #define PSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT                                          8
+  #define PSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_B_E5                                                (0x1<<9) // Error in FOC error of Storm B.
+  #define PSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_B_E5_SHIFT                                          9
+  #define PSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5                                              (0x1<<10) // Invalid allocated thread request with partial FIN of Storm A.
+  #define PSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5_SHIFT                                        10
+  #define PSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5                                              (0x1<<11) // Invalid allocated thread request with partial FIN of Storm B.
+  #define PSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5_SHIFT                                        11
+  #define PSEM_REG_INT_STS_CLR_2_CAM_RBC_INPUT_FIFO_ERROR_E5                                                 (0x1<<12) // Cam input FIFO error
+  #define PSEM_REG_INT_STS_CLR_2_CAM_RBC_INPUT_FIFO_ERROR_E5_SHIFT                                           12
+  #define PSEM_REG_INT_STS_CLR_2_ARB_RBC_FIFO_ERROR_A_E5                                                     (0x1<<13) // Pre-fetch FIFO error of Storm A.
+  #define PSEM_REG_INT_STS_CLR_2_ARB_RBC_FIFO_ERROR_A_E5_SHIFT                                               13
+  #define PSEM_REG_INT_STS_CLR_2_ARB_RBC_FIFO_ERROR_B_E5                                                     (0x1<<14) // Pre-fetch FIFO error of Storm B.
+  #define PSEM_REG_INT_STS_CLR_2_ARB_RBC_FIFO_ERROR_B_E5_SHIFT                                               14
+  #define PSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5                                             (0x1<<15) // Lock is acquired more than maximum configured time.
+  #define PSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5_SHIFT                                       15
+  #define PSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                              (0x1<<16) // Ilegal assetion commands towards lock block.
+  #define PSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5_SHIFT                                        16
+  #define PSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_RELEASE_ERROR_E5                                               (0x1<<17) // Error when trying to release a lock which is not acquired (key does not match any lock)
+  #define PSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_RELEASE_ERROR_E5_SHIFT                                         17
+  #define PSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5                                             (0x1<<18) // Trying to acquire a lock which is already acquired.
+  #define PSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5_SHIFT                                       18
+  #define PSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5                                            (0x1<<19) // Trying to relinquish a key which does not exist.
+  #define PSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5_SHIFT                                      19
+  #define PSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5                                            (0x1<<20) // A lock acquired requrest is issued when all locks are used.
+  #define PSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5_SHIFT                                      20
+  #define PSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5                                            (0x1<<21) // Error when both Storm are stalled due to lock block (may indicate a dead lock).
+  #define PSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5_SHIFT                                      21
+  #define PSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5                                        (0x1<<22) // Fin done with remainning allocated threads STORM_A.
+  #define PSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5_SHIFT                                  22
+  #define PSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5                                        (0x1<<23) // Fin done with remainning allocated threads STORM_B.
+  #define PSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5_SHIFT                                  23
+  #define PSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5                                        (0x1<<24) // Fin new thread request when no thread is allocated for handler of Storm A.
+  #define PSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5_SHIFT                                  24
+  #define PSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5                                        (0x1<<25) // Fin new thread request when no thread is allocated for handler of Storm B.
+  #define PSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5_SHIFT                                  25
+  #define PSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5                                  (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same range.
+  #define PSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5_SHIFT                            26
+  #define PSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5                                  (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same range.
+  #define PSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5_SHIFT                            27
+  #define PSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5                                     (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
+  #define PSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5_SHIFT                               28
+  #define PSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5                                     (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
+  #define PSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5_SHIFT                               29
+  #define PSEM_REG_INT_STS_CLR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5                                      (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
+  #define PSEM_REG_INT_STS_CLR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT                                30
+#define PSEM_REG_PRTY_MASK                                                                                   0x16000ccUL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define PSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR                                                            (0x1<<0) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS.VFC_RBC_PARITY_ERROR .
+  #define PSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR_SHIFT                                                      0
+  #define PSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR                                                           (0x1<<1) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS.STORM_RF_PARITY_ERROR .
+  #define PSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR_SHIFT                                                     1
+  #define PSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR                                                            (0x1<<2) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS.REG_GEN_PARITY_ERROR .
+  #define PSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR_SHIFT                                                      2
+#define PSEM_REG_PRTY_MASK_H_0_BB_K2                                                                         0x1600204UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define PSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_BB_K2                                                 (0x1<<0) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
+  #define PSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_BB_K2_SHIFT                                           0
+  #define PSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_K2                                                 (0x1<<1) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
+  #define PSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_K2_SHIFT                                           1
+  #define PSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                     (0x1<<2) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define PSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                               2
+  #define PSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                     (0x1<<3) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define PSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                               3
+  #define PSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                     (0x1<<4) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define PSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                               4
+  #define PSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                     (0x1<<5) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define PSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                               5
+#define PSEM_REG_MEM_ECC_ENABLE_0_BB_K2                                                                      0x1600210UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PSEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN_BB_K2                                                  (0x1<<0) // Enable ECC for memory ecc instance psem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.PSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_psem.i_ecc_0 in module sem_slow_pas_buf_ram_psem
+  #define PSEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN_BB_K2_SHIFT                                            0
+  #define PSEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_BB_K2                                                  (0x1<<1) // Enable ECC for memory ecc instance psem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.PSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_psem.i_ecc_1 in module sem_slow_pas_buf_ram_psem
+  #define PSEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_BB_K2_SHIFT                                            1
+#define PSEM_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                 0x1600214UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define PSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY_BB_K2                                           (0x1<<0) // Set parity only for memory ecc instance psem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.PSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_psem.i_ecc_0 in module sem_slow_pas_buf_ram_psem
+  #define PSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY_BB_K2_SHIFT                                     0
+  #define PSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_BB_K2                                           (0x1<<1) // Set parity only for memory ecc instance psem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.PSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_psem.i_ecc_1 in module sem_slow_pas_buf_ram_psem
+  #define PSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_BB_K2_SHIFT                                     1
+#define PSEM_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                             0x1600218UL //Access:RC   DataWidth:0x2    // Multi Field Register.
+  #define PSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT_BB_K2                                    (0x1<<0) // Record if a correctable error occurred on memory ecc instance psem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.PSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_psem.i_ecc_0 in module sem_slow_pas_buf_ram_psem
+  #define PSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT_BB_K2_SHIFT                              0
+  #define PSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_BB_K2                                    (0x1<<1) // Record if a correctable error occurred on memory ecc instance psem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.PSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_psem.i_ecc_1 in module sem_slow_pas_buf_ram_psem
+  #define PSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_BB_K2_SHIFT                              1
+#define PSEM_REG_MEM_ECC_EVENTS_BB_K2                                                                        0x160021cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define PSEM_REG_ARB_CYCLE_SIZE_BB_K2                                                                        0x1600400UL //Access:RW   DataWidth:0x5    // The number of time_slots in the arbitration cycle.
+#define PSEM_REG_VF_ERROR                                                                                    0x1600408UL //Access:WR   DataWidth:0x1    // This VF-split register provides read/clear access to the VF error received from the SDM for a DMA transfer. Reading this register will return the VF Error for value for the corresponding VF. Writing a 1 to this register will clear the error for the corresponding VF.
+#define PSEM_REG_PF_ERROR                                                                                    0x160040cUL //Access:WR   DataWidth:0x1    // This PF-split register provides read/clear access to the PF error received from the SDM for a DMA transfer. Reading this register will return the PF Error for value for the corresponding PF. Writing a 1 to this register will clear the error for the corresponding PF.
+#define PSEM_REG_VF_ERR_VECTOR                                                                               0x1600420UL //Access:WB_R DataWidth:0xf0   // This read-only register provides a vector of bits having an error indication per VF where the Bit position corresponds to the VFID.
+#define PSEM_REG_VF_ERR_VECTOR_SIZE_BB                                                                       4
+#define PSEM_REG_VF_ERR_VECTOR_SIZE_K2_E5                                                                    8
+#define PSEM_REG_PF_ERR_VECTOR                                                                               0x1600440UL //Access:R    DataWidth:0x10   // This read-only register provides a vector of bits having an error indication per PF where the Bit position corresponds to the PFID.
+#define PSEM_REG_CLEAR_STALL                                                                                 0x1600444UL //Access:RW   DataWidth:0x1    // Clear stall signal sent from local storm to external storms.
+#define PSEM_REG_EXCEPTION_INT                                                                               0x1600448UL //Access:RW   DataWidth:0x10   // Provides a default PRAM address to be used for the handler in the event that the PRAM address retrieved from the interrupt table is out of range with regard to the actual PRAM size provided in the SEMI instance.
+#define PSEM_REG_EXT_STORE_FREE_ENTRIES_BB_K2                                                                0x160044cUL //Access:R    DataWidth:0x6    // Number of free entries in the external STORE sync FIFO.
+#define PSEM_REG_GPI_DATA_A_E5                                                                               0x1600450UL //Access:R    DataWidth:0x20   // Used to read the GPI input signals of Storm A.
+#define PSEM_REG_GPI_DATA_BB_K2                                                                              0x1600450UL //Access:R    DataWidth:0x20   // Used to read the GPI input signals.
+#define PSEM_REG_GPRE_SAMP_PERIOD_BB_K2                                                                      0x1600454UL //Access:RW   DataWidth:0x4    // Defines the number of system clocks from one sample of GPRE sync data and the next.
+#define PSEM_REG_ALLOW_LP_SLEEP_THRD                                                                         0x1600458UL //Access:RW   DataWidth:0x1    // When set, this bit is used to allow low-power mode to be activated while threads are sleeping in the passive buffer, as long as the SEMI/Storm remains idle.
+#define PSEM_REG_ECO_RESERVED                                                                                0x160045cUL //Access:RW   DataWidth:0x20   // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
+#define PSEM_REG_PB_WR_SDM_DMA_MODE_E5                                                                       0x1600460UL //Access:RW   DataWidth:0x2    // This register can set the mode of the SDM DMA write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use regardless write mode. 11 - Disable write mode.
+#define PSEM_REG_PB_WR_DRA_RD_CUT_THROUGH_MODE_E5                                                            0x1600464UL //Access:RW   DataWidth:0x1    // This register set the DRA RD block cut through mode in which write to a thread address section passive buffer may occur simultaneously with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut through mode active.
+#define PSEM_REG_GPI_DATA_B_E5                                                                               0x1600468UL //Access:R    DataWidth:0x20   // Used to read the GPI input signals of Storm B.
+#define PSEM_REG_FIC_FIFO_BB_K2                                                                              0x1600580UL //Access:WB_R DataWidth:0x80   // Used for debugging to read/write to/from the FIC FIFOs. The address selects which FIFO should be accessed.
+#define PSEM_REG_FIC_FIFO_SIZE                                                                               4
+#define PSEM_REG_FIC_MIN_MSG_BB_K2                                                                           0x1600600UL //Access:RW   DataWidth:0x6    // Per-FIC interface register array defines minimum number of cycles in the FIC interfaces after which the message can be sent to the passive register_file.
+#define PSEM_REG_FIC_EMPTY_CT_MODE_BB_K2                                                                     0x1600620UL //Access:RW   DataWidth:0x1    // When set, enables the "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require that the available ("go") counter is non-zero before making a transfer request to the DRA arbiter and starting a transfer.
+#define PSEM_REG_FIC_EMPTY_CT_CNT_BB_K2                                                                      0x1600624UL //Access:RC   DataWidth:0x18   // Statistics counter used to count the number of FIC messages that have been received on any FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
+#define PSEM_REG_FOC_CREDIT                                                                                  0x1600680UL //Access:RW   DataWidth:0x8    // Array of registers provides the initial credits on each of the associatef FOC interfaces. Reading from this register provides the current FOR credit value.
+#define PSEM_REG_FOC_CREDIT_SIZE                                                                             2
+#define PSEM_REG_FULL_FOC_DRA_STRT_EN_BB_K2                                                                  0x16006c0UL //Access:RW   DataWidth:0x1    // When set, this bit allows the DRA read operation to start even when there are not enough credits on all the participating FOC interfaces to complete the entire transaction. The transfer will stall only when a transfer cycle is reached in which there are no interface credits, at which time the DRA transfer will remain stalled until the FOC destination(s) has at least a single credit. When this configuration is cleared, the DRA read transfer will not begin until there are enough credits on all the participating FOC interfaces for the entire transfer.
+#define PSEM_REG_FIN_COMMAND_BB_K2                                                                           0x1600700UL //Access:WB_R DataWidth:0x164  // Last fin command that was read from fifo. Its spelling in FIN_FIFO register.
+#define PSEM_REG_FIN_COMMAND_SIZE                                                                            16
+#define PSEM_REG_FIN_FIFO_BB_K2                                                                              0x1600800UL //Access:WB_R DataWidth:0x164  // READ ONLY FOR DEBUGGING! [5:0]   start_rp_foc3; [11:6] start_rp_foc2;  [17:12]   start_rp_foc1; [23:18] start_rp_foc0;  [29:24]   end_rp_foc3; [35:30] end_rp_foc2; [41:36]   end_rp_foc1; [47:42]   end_rp_foc0; [53:48]   lowest rp; [59:54]   highest rp; [65:60]   store start rp; [71:66]   store end rp; [77:72]   load start rp; [83:78]   load end rp; [85:84]   priority; [101:86]  pram address; [102] pas; [103] foc3; [104] foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:0] is valid.
+#define PSEM_REG_FIN_FIFO_SIZE                                                                               16
+#define PSEM_REG_INVLD_PAS_WR_EN_BB_K2                                                                       0x1600900UL //Access:RW   DataWidth:0x1    // When set, an attempt to write to the passive buffer over the external passive interface will be enabled even if the partition being written is owned by a thread whose valid bit is not set. Otherwise if cleared, the transfer will be stalled.
+#define PSEM_REG_ARBITER_REQUEST_BB_K2                                                                       0x1600980UL //Access:R    DataWidth:0x5    // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2.
+#define PSEM_REG_ARBITER_SELECT_BB_K2                                                                        0x1600984UL //Access:R    DataWidth:0x5    // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2.
+#define PSEM_REG_ARBITER_SLOT_BB_K2                                                                          0x1600988UL //Access:R    DataWidth:0x5    // Dra arbiter last slot.
+#define PSEM_REG_ARB_AS_DEF_BB_K2                                                                            0x1600a00UL //Access:RW   DataWidth:0x3    // Two-dimensional register array is used to define each of four arbitration schemes used by the main DRA arbiter. For this, bits 4:3 of the offset are used to select the arbitration scheme 0-3. Bits 2:0 of the offset are used to define the five priority sources for the selected scheme, where for each priority (0-4), an arbiter source is assigned. Valid values for these configurations are the source enumerations, where FIC0=0x0, FIC1=0x1, wake priority0=0x2, wake priority1=0x3 and wake priority2=0x4. Note that there are holes in the indirect offset address which always return zero when read. These exist at offsets 0x5-0x7, 0xd-0xf, 0x15-0x17 and 0x1d-0x1f.
+#define PSEM_REG_ARB_AS_DEF_SIZE                                                                             32
+#define PSEM_REG_ARB_TS_AS_BB_K2                                                                             0x1600a80UL //Access:RW   DataWidth:0x2    // Register array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
+#define PSEM_REG_ARB_TS_AS_SIZE                                                                              20
+#define PSEM_REG_NUM_OF_THREADS                                                                              0x1600b00UL //Access:R    DataWidth:0x8    // The number of currently free threads (in invalid state).
+#define PSEM_REG_THREAD_ERROR_LOW_E5                                                                         0x1600b04UL //Access:R    DataWidth:0x20   // Thread error low indication. Represents threads 31 -0
+#define PSEM_REG_THREAD_ERROR_BB_K2                                                                          0x1600b04UL //Access:R    DataWidth:0x4    // Thread error indication.
+#define PSEM_REG_THREAD_RDY_BB_K2                                                                            0x1600b08UL //Access:R    DataWidth:0x4    // Thread ready indication.
+#define PSEM_REG_THREAD_SET_NUM                                                                              0x1600b0cUL //Access:W    DataWidth:0x6    // Thread ID. Write thread ID will set ready indication for this thread ID.
+#define PSEM_REG_THREAD_VALID_BB_K2                                                                          0x1600b10UL //Access:R    DataWidth:0x4    // Valid sleeping threads.
+#define PSEM_REG_THREADS_LIST_BB_K2                                                                          0x1600b14UL //Access:RW   DataWidth:0x4    // List of free threads.
+#define PSEM_REG_THREAD_NUMBER_E5                                                                            0x1600b18UL //Access:RW   DataWidth:0x8    // Defines the maixmum number of supported threads in SEMI.
+#define PSEM_REG_THREAD_ERROR_HIGH_E5                                                                        0x1600b1cUL //Access:R    DataWidth:0x18   // Thread error high indication. Represents threads  55-32
+#define PSEM_REG_FOC_MIN_MESSAGE_CREDIT_E5                                                                   0x1600b40UL //Access:RW   DataWidth:0x8    // This field defines for each FOC the minimum message reuired for the FOC transfer to start.
+#define PSEM_REG_FOC_MIN_MESSAGE_CREDIT_SIZE                                                                 2
+#define PSEM_REG_ORDER_HEAD_BB_K2                                                                            0x1600c00UL //Access:RW   DataWidth:0x2    // This (indirect) register array of registers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
+#define PSEM_REG_ORDER_HEAD_SIZE                                                                             2
+#define PSEM_REG_ORDER_TAIL_BB_K2                                                                            0x1600c80UL //Access:RW   DataWidth:0x2    // This (indirect) register array of registers provides read/write access to the tail pointers assigned to each of the thread ordering queues.
+#define PSEM_REG_ORDER_TAIL_SIZE                                                                             2
+#define PSEM_REG_ORDER_EMPTY_BB_K2                                                                           0x1600d00UL //Access:RW   DataWidth:0x1    // This vector provides read-only access to the empty bit assigned to each of the thread ordering queues.
+#define PSEM_REG_ORDER_EMPTY_SIZE                                                                            2
+#define PSEM_REG_ORDER_LL_REG_BB_K2                                                                          0x1600d80UL //Access:RW   DataWidth:0x2    // This array of registers provides read/write access to each entry of the linked-list array of the thread-ordering queue. Because the actual depth is based on the number of threads supported by the design, which is a Verilog parameter, a 64-entry window is reserved in the register address space. The valid entries start at the base of the window and extend through the number of threads supported. The value in each indirect register contains linked-list pointer to the next thread in the associated queue..
+#define PSEM_REG_ORDER_LL_REG_SIZE                                                                           4
+#define PSEM_REG_ORDER_POP_EN_BB_K2                                                                          0x1600e00UL //Access:RW   DataWidth:0x4    // Provides access to the thread ordering queue pop-enable vector.
+#define PSEM_REG_ORDER_WAKE_EN_BB_K2                                                                         0x1600e08UL //Access:RW   DataWidth:0x4    // Provides access to the thread ordering queue wake-enable vector.
+#define PSEM_REG_PF_NUM_ORDER_BASE_BB_K2                                                                     0x1600e10UL //Access:RW   DataWidth:0x1    // This field defines the base value for the ordering queue selection when the PFNum is chosen to control this selection. The value of this register is added to PFNum and the result is used to select one of 16 ordering queues.
+#define PSEM_REG_DBG_ALM_FULL                                                                                0x1601000UL //Access:RW   DataWidth:0x6    // Almost full for slow debug fifo.
+#define PSEM_REG_PASSIVE_ALM_FULL                                                                            0x1601004UL //Access:RW   DataWidth:0x5    // The number of free entries in the sync FIFO between the external HW and the passive buffer; below which the PassiveFull is asserted.
+#define PSEM_REG_SYNC_DRA_WR_ALM_FULL_BB_K2                                                                  0x1601008UL //Access:RW   DataWidth:0x5    // Almost full for sync dra_wr fifo (data from DRA to STORM).
+#define PSEM_REG_SYNC_RAM_WR_ALM_FULL                                                                        0x160100cUL //Access:RW   DataWidth:0x6    // Almost full for sync ram_wr fifo.
+#define PSEM_REG_SYNC_FOC_FIFO_WR_ALM_FULL_E5                                                                0x1601010UL //Access:RW   DataWidth:0x4    // Almost full for indication for FOC Sync FIFO.
+#define PSEM_REG_SYNC_SDM_READY_FIFO_WR_ALM_FULL_E5                                                          0x1601014UL //Access:RW   DataWidth:0x3    // Almost full for indication for SDM READY FIFO.
+#define PSEM_REG_SYNC_SDM_INC_FIFO_WR_ALM_FULL_E5                                                            0x1601018UL //Access:RW   DataWidth:0x3    // Almost full for indication for SDM Counter Increment FIFO.
+#define PSEM_REG_STALL_ON_INT_E5                                                                             0x160101cUL //Access:RW   DataWidth:0x2    // 00 - No stall. 01 - Both cluster Stroms will be stalled on any unmasked error occurrence. 10 - All Stroms will be stalled on any unmasked error occurrence.
+#define PSEM_REG_FIC0_A_MAX_THRDS_E5                                                                         0x1601020UL //Access:RW   DataWidth:0x6    // Defines the maximum supported threads that may be contained in FIC0 A queue. If FIC0 message  is received and number of threads equals to the configured value, FIC interface will be stalled untill number of queue threads drops below configured vlaue.
+#define PSEM_REG_FIC0_X_MAX_THRDS_E5                                                                         0x1601024UL //Access:RW   DataWidth:0x6    // Defines the maximum supported threads that may be contained in FIC0 X queue. If FIC0 message  is received and number of threads equals to the configured value, FIC interface will be stalled untill number of queue threads drops below configured vlaue.
+#define PSEM_REG_FIC0_B_MAX_THRDS_E5                                                                         0x1601028UL //Access:RW   DataWidth:0x6    // Defines the maximum supported threads that may be contained in FIC0 B queue. If FIC0 message  is received and number of threads equals to the configured value, FIC interface will be stalled untill number of queue threads drops below configured vlaue.
+#define PSEM_REG_FIC1_A_MAX_THRDS_E5                                                                         0x160102cUL //Access:RW   DataWidth:0x6    // Defines the maximum supported threads that may be contained in FIC1 A queue. If FIC1 message is received and number of threads equals to the configured value, FIC interface will be stalled untill number of queue threads drops below configured vlaue.
+#define PSEM_REG_DRA_EMPTY_BB_K2                                                                             0x1601100UL //Access:R    DataWidth:0x1    // Dra_empty.
+#define PSEM_REG_EXT_PAS_EMPTY                                                                               0x1601104UL //Access:R    DataWidth:0x1    // EXT_PAS FIFO empty in sem_slow.
+#define PSEM_REG_FIC_EMPTY                                                                                   0x1601120UL //Access:R    DataWidth:0x1    // Array of registers reflects associated FIC FIFO empty in sem_slow_fic.
+#define PSEM_REG_SLOW_DBG_EMPTY_BB_K2                                                                        0x1601140UL //Access:R    DataWidth:0x1    // DBG FIFO is empty in sem_slow_ls_dbg.
+#define PSEM_REG_SLOW_DRA_FIN_EMPTY_BB_K2                                                                    0x1601144UL //Access:R    DataWidth:0x1    // FIN fifo is empty in sem_slow_dra_sync.
+#define PSEM_REG_SLOW_DRA_RD_EMPTY_BB_K2                                                                     0x1601148UL //Access:R    DataWidth:0x1    // DRA_RD pop fifo is empty in sem_slow_dra_sync.
+#define PSEM_REG_SLOW_DRA_WR_EMPTY_BB_K2                                                                     0x160114cUL //Access:R    DataWidth:0x1    // DRA_WR push fifo is empty in sem_slow_dra_sync.
+#define PSEM_REG_SLOW_EXT_STORE_EMPTY                                                                        0x1601150UL //Access:R    DataWidth:0x1    // EXT_STORE FIFO is empty in sem_slow_ls_ext.
+#define PSEM_REG_SLOW_EXT_LOAD_EMPTY                                                                         0x1601154UL //Access:R    DataWidth:0x2    // EXT_LOAD FIFO is empty in sem_slow_ls_ext, bit 0 FIFO of Core A, bit 1 FIFO of Core B.
+#define PSEM_REG_SLOW_RAM_RD_EMPTY                                                                           0x1601158UL //Access:R    DataWidth:0x1    // EXT_RD_RAM FIFO is empty in sem_slow_ls_ext.
+#define PSEM_REG_SLOW_RAM_WR_EMPTY                                                                           0x160115cUL //Access:R    DataWidth:0x1    // EXT_WR_RAM FIFO is empty in sem_slow_ls_ext.
+#define PSEM_REG_SYNC_DBG_EMPTY                                                                              0x1601160UL //Access:R    DataWidth:0x2    // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR debug FIFO of Core B
+#define PSEM_REG_THREAD_FIFO_EMPTY_BB_K2                                                                     0x1601164UL //Access:R    DataWidth:0x1    // Indicates that the thread fifo is empty in sem_slow_dra_wr.
+#define PSEM_REG_ORD_ID_FIFO_EMPTY_BB_K2                                                                     0x1601168UL //Access:R    DataWidth:0x1    // Indicates that the order ID fifo is empty in sem_slow_dra_wr.
+#define PSEM_REG_PB_QUEUE_EMPTY_E5                                                                           0x160116cUL //Access:R    DataWidth:0xb    // If 1, the correspongding Queue is empty. Queues numeration: FOC_FIFO_IF - 0,  FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - 5,  WAKE_FIFO_PRIO_X - 6, WAKE_FIFO_PRI1_X - 7,FIC0_FIFO_B - 8, WAKE_FIFO_PRIO_B - 9,  WAKE_FIFO_PRI1_B - 10.
+#define PSEM_REG_SYNC_FOC_FIFO_EMPTY_E5                                                                      0x1601170UL //Access:R    DataWidth:0x1    // FOC FIFO empty indication.
+#define PSEM_REG_SYNC_FOC_PRE_FETCH_FIFO_EMPTY_E5                                                            0x1601174UL //Access:R    DataWidth:0x1    // FOC pre fetch FIFO empty indication.
+#define PSEM_REG_EXT_PAS_FULL                                                                                0x1601200UL //Access:R    DataWidth:0x1    // EXT_PAS FIFO Full in sem_slow.
+#define PSEM_REG_EXT_STORE_IF_FULL                                                                           0x1601204UL //Access:R    DataWidth:0x1    // EXT_STORE IF is full in sem_slow_ls_ext.
+#define PSEM_REG_FIC_FULL                                                                                    0x1601220UL //Access:R    DataWidth:0x1    // Array of registers reflects associated FIC FIFO full in sem_slow_fic.
+#define PSEM_REG_PAS_IF_FULL_BB_K2                                                                           0x1601240UL //Access:R    DataWidth:0x1    // Full from passive buffer asserted toward SDM.
+#define PSEM_REG_RAM_IF_FULL                                                                                 0x1601244UL //Access:R    DataWidth:0x1    // EXT_RAM IF is full in sem_slow_ls_ram.
+#define PSEM_REG_SLOW_DBG_ALM_FULL_BB_K2                                                                     0x1601248UL //Access:R    DataWidth:0x1    // DBG FIFO is almost full in sem_slow_ls_dbg according to the full threshold configuration.
+#define PSEM_REG_SLOW_DBG_FULL_BB_K2                                                                         0x160124cUL //Access:R    DataWidth:0x1    // DBG FIFO is full in sem_slow_ls_dbg.
+#define PSEM_REG_SLOW_DRA_FIN_FULL_BB_K2                                                                     0x1601250UL //Access:R    DataWidth:0x1    // FIN fifo is full in sem_slow_dra_sync (never may be active).
+#define PSEM_REG_SLOW_DRA_RD_FULL_BB_K2                                                                      0x1601254UL //Access:R    DataWidth:0x1    // DRA_RD pop fifo is full in sem_slow_dra_sync.
+#define PSEM_REG_SLOW_DRA_WR_FULL_BB_K2                                                                      0x1601258UL //Access:R    DataWidth:0x1    // DRA_WR push fifo is full in sem_slow_dra_sync.
+#define PSEM_REG_SLOW_EXT_STORE_FULL                                                                         0x160125cUL //Access:R    DataWidth:0x2    // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIFO.
+#define PSEM_REG_SLOW_EXT_LOAD_FULL                                                                          0x1601260UL //Access:R    DataWidth:0x2    // EXT_LOAD FIFO is full in sem_slow_ls_ext, bit 0 for Core A and bit 1 for Core B.
+#define PSEM_REG_SLOW_RAM_RD_FULL                                                                            0x1601264UL //Access:R    DataWidth:0x1    // EXT_RD_RAM FIFO is full in sem_slow_ls_ext.
+#define PSEM_REG_SLOW_RAM_WR_ALM_FULL                                                                        0x1601268UL //Access:R    DataWidth:0x1    // EXT_WR_RAM FIFO is almost full in sem_slow_ls_ext.
+#define PSEM_REG_SLOW_RAM_WR_FULL                                                                            0x160126cUL //Access:R    DataWidth:0x1    // EXT_WR_RAM FIFO is full in sem_slow_ls_ext.
+#define PSEM_REG_SYNC_DBG_FULL                                                                               0x1601270UL //Access:R    DataWidth:0x2    // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR debug FIFO of Core B.
+#define PSEM_REG_THREAD_FIFO_FULL_BB_K2                                                                      0x1601274UL //Access:R    DataWidth:0x1    // Indicates that the thread fifo is full in sem_slow_dra_wr.
+#define PSEM_REG_ORD_ID_FIFO_FULL_BB_K2                                                                      0x1601278UL //Access:R    DataWidth:0x1    // Indicates that the thread fifo is full in sem_slow_dra_wr.
+#define PSEM_REG_SYNC_READY_FIFO_FULL_E5                                                                     0x160127cUL //Access:R    DataWidth:0x1    // Ready sync FIFO full indication.
+#define PSEM_REG_SYNC_CNT_FIFO_FULL_E5                                                                       0x1601280UL //Access:R    DataWidth:0x1    // Counter increment sync FIFO full indication.
+#define PSEM_REG_SYNC_FOC_FIFO_FULL_E5                                                                       0x1601284UL //Access:R    DataWidth:0x1    // sync FOC FIFO full indication.
+#define PSEM_REG_THREAD_INTER_CNT_BB_K2                                                                      0x1601300UL //Access:RW   DataWidth:0x10   // Maximum value of threads interrupt counter; when it gets this value then interrupt to will be send if thread active from previous maximum value of this counter.
+#define PSEM_REG_THREAD_INTER_CNT_ENABLE_BB_K2                                                               0x1601304UL //Access:RW   DataWidth:0x1    // Enable for start count of thread_inter_cnt.
+#define PSEM_REG_THREAD_ORUN_NUM_BB_K2                                                                       0x1601308UL //Access:R    DataWidth:0x4    // Threads are sleeping in passive buffer more than thread_inter_cnt number of cycles.
+#define PSEM_REG_SLOW_DBG_ACTIVE_BB_K2                                                                       0x1601400UL //Access:RW   DataWidth:0x1    // Debug mode is active.
+#define PSEM_REG_SLOW_DBG_MODE_BB_K2                                                                         0x1601404UL //Access:RW   DataWidth:0x3    // Debug mode for slow debug bus.
+#define PSEM_REG_DBG_FRAME_MODE_BB_K2                                                                        0x1601408UL //Access:RW   DataWidth:0x2    // Debug frame mode control for the SEMI debug bus. The following values apply: "00" - indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mode-1, which means bits 127:64 belong to fast debug and bits 63:0 belong to slow debug. "10" - indicates mode-2, which means bits 127:96 belong to fast debug and bits 95:0 belong to slow debug. "11" - indicates mode-3, which means all four words are provided by the slow debug.
+#define PSEM_REG_DBG_EACH_CYLE_BB_K2                                                                         0x160140cUL //Access:RW   DataWidth:0x1    // 0=output every cycle; 1= output only when there is a change.
+#define PSEM_REG_DBG_GPRE_VECT_BB_K2                                                                         0x1601410UL //Access:RW   DataWidth:0x8    // This 8-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug channel when they are accessed for read by the Storm during mode-6 debug (handler trace). For this, bit-0 corresponds with GPRE[0-3] and bit-7 corresponds with GPRE[28-31].
+#define PSEM_REG_DBG_IF_FULL_BB_K2                                                                           0x1601414UL //Access:R    DataWidth:0x1    // DBG IF is full in sem_slow_ls_dbg.
+#define PSEM_REG_DBG_MODE0_CFG_BB_K2                                                                         0x1601418UL //Access:RW   DataWidth:0x1    // 0=all the message; 1=partial message.
+#define PSEM_REG_DBG_MODE0_CFG_CYCLE_BB_K2                                                                   0x160141cUL //Access:RW   DataWidth:0x5    // In case DebugMode0Config = 1; the additional cycles to extract to the debug bus.
+#define PSEM_REG_DBG_MODE1_CFG_BB_K2                                                                         0x1601420UL //Access:RW   DataWidth:0x1    // 0=without the data; 1=with the data.
+#define PSEM_REG_DBG_MSG_SRC_BB_K2                                                                           0x1601424UL //Access:RW   DataWidth:0x3    // This field is a mask used to enable (or filter) the various sources of DRA write debug packets. Setting a bit causes the corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1 and bit-2 corresponds with DRA writes from the passive buffer. This applicable only for debug mode=0.
+#define PSEM_REG_DBG_QUEUE_PEFORMANCE_MON_STAT_E5                                                            0x1601428UL //Access:RW   DataWidth:0x1    // If 0, the statistic report the maximum value between following reads (when using read clear). If 1, report the current value.
+#define PSEM_REG_PASSIVE_BUFFER_PERFORMANCE_MON_STAT_E5                                                      0x160142cUL //Access:RW   DataWidth:0x1    // Enable performance monitor statistics sent to SEM_PD.
+#define PSEM_REG_DBG_QUEUE_FIC_MON_CNT_E5                                                                    0x1601430UL //Access:RC   DataWidth:0x20   // Report the number of received FIC transaction between two of the following register reads. The counter is incremanted only for the event IDs which have Debug Monitor event indication set.
+#define PSEM_REG_DBG_QUEUE_FOC_MAX_VALUE_E5                                                                  0x1601434UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FOC queue.
+#define PSEM_REG_DBG_QUEUE_FIC0_A_MAX_VALUE_E5                                                               0x1601438UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 A queue.
+#define PSEM_REG_DBG_QUEUE_FIC1_A_MAX_VALUE_E5                                                               0x160143cUL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC1 A queue.
+#define PSEM_REG_DBG_QUEUE_PRIO0_A_MAX_VALUE_E5                                                              0x1601440UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 A queue.
+#define PSEM_REG_DBG_QUEUE_PRIO1_A_MAX_VALUE_E5                                                              0x1601444UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 A queue.
+#define PSEM_REG_DBG_QUEUE_FIC0_X_MAX_VALUE_E5                                                               0x1601448UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 X queue.
+#define PSEM_REG_DBG_QUEUE_PRIO0_X_MAX_VALUE_E5                                                              0x160144cUL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 X queue.
+#define PSEM_REG_DBG_QUEUE_PRIO1_X_MAX_VALUE_E5                                                              0x1601450UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 X queue.
+#define PSEM_REG_DBG_QUEUE_FIC0_B_MAX_VALUE_E5                                                               0x1601454UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 B queue.
+#define PSEM_REG_DBG_QUEUE_PRIO0_B_MAX_VALUE_E5                                                              0x1601458UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 B queue.
+#define PSEM_REG_DBG_QUEUE_PRIO1_B_MAX_VALUE_E5                                                              0x160145cUL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 B queue.
+#define PSEM_REG_DBG_QUEUE_MAX_THREAD_VALUE_E5                                                               0x1601460UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of allocated threads in the system.
+#define PSEM_REG_DBG_QUEUE_MAX_SLEEP_VALUE_E5                                                                0x1601464UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does not include the threads pending in the queues.
+#define PSEM_REG_DBG_OUT_DATA                                                                                0x1601500UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define PSEM_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define PSEM_REG_DBG_OUT_VALID                                                                               0x1601520UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define PSEM_REG_DBG_OUT_FRAME                                                                               0x1601524UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define PSEM_REG_DBG_SELECT                                                                                  0x1601528UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define PSEM_REG_DBG_DWORD_ENABLE                                                                            0x160152cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define PSEM_REG_DBG_SHIFT                                                                                   0x1601530UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define PSEM_REG_DBG_FORCE_VALID                                                                             0x1601534UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PSEM_REG_DBG_FORCE_FRAME                                                                             0x1601538UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define PSEM_REG_EXT_PAS_FIFO_BB_K2                                                                          0x1608000UL //Access:WB_R DataWidth:0x4a   // Provides read-only access of the external passive FIFO. Intended for debug purposes.
+#define PSEM_REG_EXT_PAS_FIFO_SIZE                                                                           76
+#define PSEM_REG_INT_TABLE                                                                                   0x1610000UL //Access:RW   DataWidth:0x1e   // Interrupt table read/write access. This register is intended to be written only when the system is idle. The fields of the interrupt table are as follows. int_table[29] = Allocated per child;  int_table[28] = Increment type; int_table[27:23] = Counter select; int_table[22] = Counter insert; int_table[21:17] = GapSel; int_table[16] = Monitor enable; int_table[15:0] = PRAM Address;
+#define PSEM_REG_INT_TABLE_SIZE                                                                              256
+#define PSEM_REG_FIC_COUNTER_GROUP_E5                                                                        0x1611000UL //Access:RW   DataWidth:0x8    // This field enables a RD/WR access to the 24 counters of the "FIC Counters".
+#define PSEM_REG_FIC_COUNTER_GROUP_SIZE                                                                      24
+#define PSEM_REG_PB_THRD_STM_GROUP_E5                                                                        0x1612000UL //Access:R    DataWidth:0x17   // Read the State mahcine state of teh trheads. 0:4 - state. 5 - pending ready. 7:6 - Affinity type. 8 - Destination FOC. 9 - Destination Storm. 10 - counter increment ready. 15:11 - counter index. 16 - Debug monitor enable. 17 - Exlucsive. 22:18 - DRA size.
+#define PSEM_REG_PB_THRD_STM_GROUP_SIZE                                                                      56
+#define PSEM_REG_PASSIVE_BUFFER                                                                              0x1620000UL //Access:R    DataWidth:0x20   // Passive buffer memory read only.
+#define PSEM_REG_PASSIVE_BUFFER_SIZE_BB_K2                                                                   720
+#define PSEM_REG_PASSIVE_BUFFER_SIZE_E5                                                                      12544
+#define PSEM_REG_FIC_GAP_VECT_BB_K2                                                                          0x1600500UL //Access:WB   DataWidth:0x2c   // This array of nine 44-bit vectors provides a bit per register-quad, used to define the register-quad locations that should be included in gaps (discontinuities) within the DRA transfer, where bit-0 corresponds with IORs 0-3, and so on. To indicate a gap, the corresponding bit should be cleared. These gaps have a granularity of a register- quad (four IORs). For each DRA write transfer from whom the FIC is the source, one of nine gap vectors (or a default-gap vector) will be selected, based on the GapSelect field of the corresponding interrupt table entry. Any unused upper bits of the vector will be ignored and thus, can be written with any value.
+#define PSEM_REG_FIC_GAP_VECT_E5                                                                             0x1630000UL //Access:WB   DataWidth:0x34   // This array of 24 x 52-bit vectors provides a bit per register-quad, used to define the register-quad locations that should be included in gaps (discontinuities) within the DRA transfer, where bit-0 corresponds with IORs 0-3, and so on. To indicate a gap, the corresponding bit should be cleared. These gaps have a granularity of a register- quad (four IORs). For each DRA write transfer from whom the FIC is the source, one of nine gap vectors (or a default-gap vector) will be selected, based on the GapSelect field of the corresponding interrupt table entry. Any unused upper bits of the vector will be ignored and thus, can be written with any value.
+#define PSEM_REG_FIC_GAP_VECT_SIZE_BB_K2                                                                     18
+#define PSEM_REG_FIC_GAP_VECT_SIZE_E5                                                                        48
+#define PSEM_REG_FAST_MEMORY                                                                                 0x1640000UL //Access:RW   DataWidth:0x20   // See sem_fast.xls for its description.
+#define PSEM_REG_FAST_MEMORY_SIZE                                                                            65536
+#define PSEM_REG_PRAM                                                                                        0x1680000UL //Access:WB   DataWidth:0x30   // Pram memory.
+#define PSEM_REG_PRAM_SIZE_BB                                                                                49152
+#define PSEM_REG_PRAM_SIZE_K2                                                                                73728
+#define PSEM_REG_PRAM_SIZE_E5                                                                                92160
+#define TSEM_REG_ENABLE_IN_BB_K2                                                                             0x1700004UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define TSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN_BB_K2                                                        (0x1<<0) // Full input from external IF to LS input enable.
+  #define TSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN_BB_K2_SHIFT                                                  0
+  #define TSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN_BB_K2                                                     (0x1<<1) // Read data from external LS IF input enable.
+  #define TSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN_BB_K2_SHIFT                                               1
+  #define TSEM_REG_ENABLE_IN_FIC_ENABLE_IN_BB_K2                                                             (0x1<<2) // FIC input enable bit used to enable/disable messages from being received on all FIC interfaces.
+  #define TSEM_REG_ENABLE_IN_FIC_ENABLE_IN_BB_K2_SHIFT                                                       2
+  #define TSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN_BB_K2                                                         (0x1<<3) // FOC acknowledge input enable bit used to enable/disable acknowledge response from being received on any of the FOC interfaces.
+  #define TSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN_BB_K2_SHIFT                                                   3
+  #define TSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN_BB_K2                                                         (0x1<<4) // General interface input enable.
+  #define TSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN_BB_K2_SHIFT                                                   4
+  #define TSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN_BB_K2                                                         (0x1<<5) // External passive write input enable.
+  #define TSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN_BB_K2_SHIFT                                                   5
+  #define TSEM_REG_ENABLE_IN_RAM_ENABLE_IN_BB_K2                                                             (0x1<<6) // Data input enable to RAM.
+  #define TSEM_REG_ENABLE_IN_RAM_ENABLE_IN_BB_K2_SHIFT                                                       6
+  #define TSEM_REG_ENABLE_IN_STALL_ENABLE_IN_BB_K2                                                           (0x1<<7) // Enable for stall input from all external STORM instances.
+  #define TSEM_REG_ENABLE_IN_STALL_ENABLE_IN_BB_K2_SHIFT                                                     7
+  #define TSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN_BB_K2                                                      (0x1<<8) // Thread ready bus input enable.
+  #define TSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN_BB_K2_SHIFT                                                8
+  #define TSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN_BB_K2                                                      (0x1<<9) // Input enable for VF error indication from SDM to SEMI.
+  #define TSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN_BB_K2_SHIFT                                                9
+#define TSEM_REG_ENABLE_OUT_BB_K2                                                                            0x1700008UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define TSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT_BB_K2                                                    (0x1<<0) // Read request output enable from external LS IF.
+  #define TSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT_BB_K2_SHIFT                                              0
+  #define TSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT_BB_K2                                                    (0x1<<1) // Write request output enable from external LS IF.
+  #define TSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT_BB_K2_SHIFT                                              1
+  #define TSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT_BB_K2                                                           (0x1<<2) // FOC output otuput enable bit used to enable/disable messages from being sent out on any of the FOC interfaces.
+  #define TSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT_BB_K2_SHIFT                                                     2
+  #define TSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT_BB_K2                                                       (0x1<<3) // Passive full output enable.
+  #define TSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT_BB_K2_SHIFT                                                 3
+  #define TSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT_BB_K2                                                           (0x1<<4) // Data output enable to RAM.
+  #define TSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT_BB_K2_SHIFT                                                     4
+  #define TSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT_BB_K2                                                         (0x1<<5) // Stall output enable bit used to enable/disable the output stall signal toward all external Storm instances.
+  #define TSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT_BB_K2_SHIFT                                                   5
+#define TSEM_REG_FIC_DISABLE_BB_K2                                                                           0x170000cUL //Access:RW   DataWidth:0x1    // Disables input messages from all FIC interfaces.  May be updated during run_time by the microcode.
+#define TSEM_REG_PAS_DISABLE_BB_K2                                                                           0x1700010UL //Access:RW   DataWidth:0x1    // Disables input messages from the passive buffer  May be updated during run_time by the microcode.
+#define TSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_E5                                                         0x1700014UL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define TSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_FIC_WEIGHT_E5                                   (0xf<<0) // Passive Buffer write WRR weight value for FIC source.
+  #define TSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_FIC_WEIGHT_E5_SHIFT                             0
+  #define TSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_A_WEIGHT_E5                                 (0xf<<4) // Passive Buffer write WRR weight value for DRA RD A source.
+  #define TSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_A_WEIGHT_E5_SHIFT                           4
+  #define TSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_B_WEIGHT_E5                                 (0xf<<8) // Passive Buffer write WRR weight value for DRA RD B source.
+  #define TSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_B_WEIGHT_E5_SHIFT                           8
+  #define TSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_SDM_WEIGHT_E5                                   (0xf<<12) // Passive Buffer write WRR weight value for SDM source.
+  #define TSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_SDM_WEIGHT_E5_SHIFT                             12
+  #define TSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_EMPTY_CNT_E5                                    (0xf<<16) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define TSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_EMPTY_CNT_E5_SHIFT                              16
+  #define TSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_STRICT_SRC_E5                                      (0x7<<20) // This register defines if one of the source of the PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B, 100 - SDM.
+  #define TSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_STRICT_SRC_E5_SHIFT                                20
+#define TSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_E5                                                          0x1700018UL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define TSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_FOC_WEIGHT_E5                                    (0xf<<0) // Passive Buffer WRR weight value for FOC source.
+  #define TSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_FOC_WEIGHT_E5_SHIFT                              0
+  #define TSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_A_WEIGHT_E5                                  (0xf<<4) // Passive Buffer write WRR weight value for DRA WR A source.
+  #define TSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_A_WEIGHT_E5_SHIFT                            4
+  #define TSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_B_WEIGHT_E5                                  (0xf<<8) // Passive Buffer write WRR weight value for DRA WR B source.
+  #define TSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_B_WEIGHT_E5_SHIFT                            8
+  #define TSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_GRC_WEIGHT_E5                                    (0xf<<12) // Passive Buffer write WRR weight value for GRC source.
+  #define TSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_GRC_WEIGHT_E5_SHIFT                              12
+  #define TSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_EMPTY_CNT_E5                                     (0xf<<16) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define TSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_EMPTY_CNT_E5_SHIFT                               16
+  #define TSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_STRICT_SRC_E5                                       (0x7<<20) // This register defines if one of the source of the PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B, 100 - GRC.
+  #define TSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_STRICT_SRC_E5_SHIFT                                 20
+#define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_E5                                                            0x170001cUL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_FIC0_A_WEIGHT_E5                             (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_FIC0_A_WEIGHT_E5_SHIFT                       0
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_FIC1_A_WEIGHT_E5                             (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_FIC1_A_WEIGHT_E5_SHIFT                       4
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO0_A_WEIGHT_E5                            (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO0_A_WEIGHT_E5_SHIFT                      8
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO1_A_WEIGHT_E5                            (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO1_A_WEIGHT_E5_SHIFT                      12
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_EMPTY_CNT_E5                                 (0xf<<16) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_EMPTY_CNT_E5_SHIFT                           16
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_STRICT_SRC_E5                                   (0x7<<20) // This register defines if one of the source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - FIC1.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_STRICT_SRC_E5_SHIFT                             20
+#define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_E5                                                            0x1700020UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_FIC0_X_WEIGHT_E5                             (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_FIC0_X_WEIGHT_E5_SHIFT                       0
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO0_X_WEIGHT_E5                            (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO0_X_WEIGHT_E5_SHIFT                      4
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO1_X_WEIGHT_E5                            (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO1_X_WEIGHT_E5_SHIFT                      8
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_EMPTY_CNT_E5                                 (0xf<<12) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_EMPTY_CNT_E5_SHIFT                           12
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_STRICT_SRC_E5                                   (0x3<<16) // This register defines if one of the source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_STRICT_SRC_E5_SHIFT                             16
+#define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_E5                                                            0x1700024UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_FIC0_B_WEIGHT_E5                             (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_FIC0_B_WEIGHT_E5_SHIFT                       0
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO0_B_WEIGHT_E5                            (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO0_B_WEIGHT_E5_SHIFT                      4
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO1_B_WEIGHT_E5                            (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO1_B_WEIGHT_E5_SHIFT                      8
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_EMPTY_CNT_E5                                 (0xf<<12) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_EMPTY_CNT_E5_SHIFT                           12
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_STRICT_SRC_E5                                   (0x3<<16) // This register defines if one of the source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_STRICT_SRC_E5_SHIFT                             16
+#define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_E5                                                            0x1700028UL //Access:RW   DataWidth:0xe    // Multi Field Register.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_AFFIN_A_WEIGHT_E5                            (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for Affinity A source.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_AFFIN_A_WEIGHT_E5_SHIFT                      0
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_AFFIN_X_WEIGHT_E5                            (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for Affinity X source.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_AFFIN_X_WEIGHT_E5_SHIFT                      4
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_EMPTY_CNT_E5                                 (0xf<<8) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_EMPTY_CNT_E5_SHIFT                           8
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_STRICT_SRC_E5                                   (0x3<<12) // This register defines if one of the source of the PB WR arbiter should have strict priority: 0 - None, 1 - AFFINITY A, 2- AFFINITY X.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_STRICT_SRC_E5_SHIFT                             12
+#define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_E5                                                            0x170002cUL //Access:RW   DataWidth:0xc    // Multi Field Register.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_AFFIN_B_WEIGHT_E5                            (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for Affinity B source.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_AFFIN_B_WEIGHT_E5_SHIFT                      0
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_AFFIN_X_WEIGHT_E5                            (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for Affinity X source.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_AFFIN_X_WEIGHT_E5_SHIFT                      4
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_EMPTY_CNT_E5                                 (0xf<<8) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define TSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_EMPTY_CNT_E5_SHIFT                           8
+#define TSEM_REG_PASSIVE_BUFFER_DRA_WR_E5                                                                    0x1700030UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define TSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_A_E5                                                   (0x1<<0) // Enable DRA Write to transactions towards the SEM_PD Core A.
+  #define TSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_A_E5_SHIFT                                             0
+  #define TSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_B_E5                                                   (0x1<<1) // Enable DRA Write to transactions towards the SEM_PD Core B.
+  #define TSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_B_E5_SHIFT                                             1
+  #define TSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_PEND_BLOCK_EN_E5                                          (0x1<<2) // When set, there may only be a single thread pending to run for each storm.
+  #define TSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_PEND_BLOCK_EN_E5_SHIFT                                    2
+  #define TSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_AFFINITY_CORE_A_ONLY_E5                                          (0x1<<3) // When set, the Affintiy field of the thread is set to CoreA (regardless to the Afficnity received from CM).
+  #define TSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_AFFINITY_CORE_A_ONLY_E5_SHIFT                                    3
+#define TSEM_REG_INT_STS_0                                                                                   0x1700040UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define TSEM_REG_INT_STS_0_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define TSEM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                             0
+  #define TSEM_REG_INT_STS_0_FIC_LAST_ERROR                                                                  (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
+  #define TSEM_REG_INT_STS_0_FIC_LAST_ERROR_SHIFT                                                            1
+  #define TSEM_REG_INT_STS_0_FIC_LENGTH_ERROR                                                                (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
+  #define TSEM_REG_INT_STS_0_FIC_LENGTH_ERROR_SHIFT                                                          2
+  #define TSEM_REG_INT_STS_0_FIC_FIFO_ERROR                                                                  (0x1<<3) // Error in any one of the FIC FIFO is active.
+  #define TSEM_REG_INT_STS_0_FIC_FIFO_ERROR_SHIFT                                                            3
+  #define TSEM_REG_INT_STS_0_DRA_RD_A_LAST_ERROR_E5                                                          (0x1<<4) // DRA_RD_A last indication was unexpectedly received or was not received at expected time.
+  #define TSEM_REG_INT_STS_0_DRA_RD_A_LAST_ERROR_E5_SHIFT                                                    4
+  #define TSEM_REG_INT_STS_0_DRA_RD_B_LAST_ERROR_E5                                                          (0x1<<5) // DRA_RD_B last indication was unexpectedly received or was not received at expected time.
+  #define TSEM_REG_INT_STS_0_DRA_RD_B_LAST_ERROR_E5_SHIFT                                                    5
+  #define TSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_A_E5                                                   (0x1<<6) // Error in external store slow sync FIFO pop logic of Storm A.
+  #define TSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_A_E5_SHIFT                                             6
+  #define TSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_B_E5                                                   (0x1<<7) // Error in external store slow sync FIFO pop logic of Storm B.
+  #define TSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT                                             7
+  #define TSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5                                                   (0x1<<8) // Error in external load sync slow FIFO push logic.
+  #define TSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT                                             8
+  #define TSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5                                                   (0x1<<9) // Error in external load sync slow FIFO pop logic.
+  #define TSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5_SHIFT                                             9
+  #define TSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2                                                    (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
+  #define TSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2_SHIFT                                              22
+  #define TSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_E5                                                       (0x1<<10) // Error in slow LS_SYNC_PUSH FIFO.
+  #define TSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_E5_SHIFT                                                 10
+  #define TSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_BB_K2                                                     (0x1<<23) // Error in LS_SYNC_POP FIFO.
+  #define TSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_BB_K2_SHIFT                                               23
+  #define TSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_E5                                                        (0x1<<11) // Error in slow LS_SYNC_POP FIFO.
+  #define TSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_E5_SHIFT                                                  11
+  #define TSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2                                                    (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
+  #define TSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2_SHIFT                                              25
+  #define TSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_E5                                                       (0x1<<12) // Error in slow LS_SYNC_PUSH FIFO.
+  #define TSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_E5_SHIFT                                                 12
+  #define TSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_A_E5                                                         (0x1<<13) // Error in slow LS_SYNC_PUSH FIFO.
+  #define TSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_A_E5_SHIFT                                                   13
+  #define TSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_B_E5                                                         (0x1<<14) // Error in slow LS_SYNC_POP FIFO.
+  #define TSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_B_E5_SHIFT                                                   14
+  #define TSEM_REG_INT_STS_0_DBG_FIFO_ERROR_BB_K2                                                            (0x1<<28) // Error in slow debug fifo.
+  #define TSEM_REG_INT_STS_0_DBG_FIFO_ERROR_BB_K2_SHIFT                                                      28
+  #define TSEM_REG_INT_STS_0_DBG_FIFO_ERROR_E5                                                               (0x1<<15) // Error in slow debug fifo
+  #define TSEM_REG_INT_STS_0_DBG_FIFO_ERROR_E5_SHIFT                                                         15
+  #define TSEM_REG_INT_STS_0_EXT_THREAD_OOR_ERROR_E5                                                         (0x1<<16) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define TSEM_REG_INT_STS_0_EXT_THREAD_OOR_ERROR_E5_SHIFT                                                   16
+  #define TSEM_REG_INT_STS_0_EXT_STORE_TAG_ODER_ERROR_E5                                                     (0x1<<17) // Error detected in the ext Stroe interface internal TAG order ID.
+  #define TSEM_REG_INT_STS_0_EXT_STORE_TAG_ODER_ERROR_E5_SHIFT                                               17
+  #define TSEM_REG_INT_STS_0_FIC1_AFFINITY_FIELD_ERROR_E5                                                    (0x1<<18) // Indicates that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
+  #define TSEM_REG_INT_STS_0_FIC1_AFFINITY_FIELD_ERROR_E5_SHIFT                                              18
+  #define TSEM_REG_INT_STS_0_EXT_LD_LEN_ERROR_E5                                                             (0x1<<19) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define TSEM_REG_INT_STS_0_EXT_LD_LEN_ERROR_E5_SHIFT                                                       19
+  #define TSEM_REG_INT_STS_0_PB_QUE_ARB_THRD_RDY_ERROR_E5                                                    (0x1<<20) // Indicates that Passive Buffer State machine has unexpectedly received a ready indication in the following cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pending FOC" or "Ready FOC" state. b. Pending Ready indication is already asserted.
+  #define TSEM_REG_INT_STS_0_PB_QUE_ARB_THRD_RDY_ERROR_E5_SHIFT                                              20
+  #define TSEM_REG_INT_STS_0_SYNC_FOC_FIFO_ERROR_E5                                                          (0x1<<21) // Error indication on FOC sync FIFO.
+  #define TSEM_REG_INT_STS_0_SYNC_FOC_FIFO_ERROR_E5_SHIFT                                                    21
+  #define TSEM_REG_INT_STS_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                      (0x1<<22) // The error indicates on an error of one the threads READY queues.
+  #define TSEM_REG_INT_STS_0_PB_QUE_ARB_QUEUES_ERROR_E5_SHIFT                                                22
+  #define TSEM_REG_INT_STS_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5                                                (0x1<<23) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define TSEM_REG_INT_STS_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5_SHIFT                                          23
+  #define TSEM_REG_INT_STS_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5                                                (0x1<<24) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define TSEM_REG_INT_STS_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5_SHIFT                                          24
+  #define TSEM_REG_INT_STS_0_CREDIT_ERROR_FOC0_E5                                                            (0x1<<25) // FOC0 is out of credit.
+  #define TSEM_REG_INT_STS_0_CREDIT_ERROR_FOC0_E5_SHIFT                                                      25
+  #define TSEM_REG_INT_STS_0_CREDIT_ERROR_FOC1_E5                                                            (0x1<<26) // FOC1 is out of credit.
+  #define TSEM_REG_INT_STS_0_CREDIT_ERROR_FOC1_E5_SHIFT                                                      26
+  #define TSEM_REG_INT_STS_0_CREDIT_ERROR_FOC2_E5                                                            (0x1<<27) // FOC2 is out of credit.
+  #define TSEM_REG_INT_STS_0_CREDIT_ERROR_FOC2_E5_SHIFT                                                      27
+  #define TSEM_REG_INT_STS_0_CREDIT_ERROR_FOC3_E5                                                            (0x1<<28) // FOC3 is out of credit.
+  #define TSEM_REG_INT_STS_0_CREDIT_ERROR_FOC3_E5_SHIFT                                                      28
+  #define TSEM_REG_INT_STS_0_CREDIT_ERROR_FOC4_E5                                                            (0x1<<29) // FOC4 is out of credit.
+  #define TSEM_REG_INT_STS_0_CREDIT_ERROR_FOC4_E5_SHIFT                                                      29
+  #define TSEM_REG_INT_STS_0_CREDIT_ERROR_FOC5_E5                                                            (0x1<<30) // FOC5 is out of credit.
+  #define TSEM_REG_INT_STS_0_CREDIT_ERROR_FOC5_E5_SHIFT                                                      30
+  #define TSEM_REG_INT_STS_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                     (0x1<<31) // Error indication of foc pre_fetch fifo.
+  #define TSEM_REG_INT_STS_0_FOC_PRE_FETCH_FIFO_ERROR_E5_SHIFT                                               31
+  #define TSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR_BB_K2                                                        (0x1<<4) // Error in Ext PAS_FIFO is active.
+  #define TSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR_BB_K2_SHIFT                                                  4
+  #define TSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR_BB_K2                                                        (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
+  #define TSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR_BB_K2_SHIFT                                                  5
+  #define TSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2                                                    (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
+  #define TSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2_SHIFT                                              6
+  #define TSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR_BB_K2                                                     (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
+  #define TSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT                                               7
+  #define TSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2                                                    (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
+  #define TSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT                                              8
+  #define TSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR_BB_K2                                                     (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
+  #define TSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR_BB_K2_SHIFT                                               9
+  #define TSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR_BB_K2                                                       (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
+  #define TSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR_BB_K2_SHIFT                                                 10
+  #define TSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR_BB_K2                                                    (0x1<<11) // Signals an unknown address in the fast-memory window.
+  #define TSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR_BB_K2_SHIFT                                              11
+  #define TSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO_BB_K2                                                          (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
+  #define TSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO_BB_K2_SHIFT                                                    12
+  #define TSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO_BB_K2                                                          (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
+  #define TSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO_BB_K2_SHIFT                                                    13
+  #define TSEM_REG_INT_STS_0_CAM_OUT_FIFO_BB_K2                                                              (0x1<<14) // Error in CAM_OUT fifo in cam block.
+  #define TSEM_REG_INT_STS_0_CAM_OUT_FIFO_BB_K2_SHIFT                                                        14
+  #define TSEM_REG_INT_STS_0_FIN_FIFO_BB_K2                                                                  (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
+  #define TSEM_REG_INT_STS_0_FIN_FIFO_BB_K2_SHIFT                                                            15
+  #define TSEM_REG_INT_STS_0_THREAD_FIFO_ERROR_BB_K2                                                         (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
+  #define TSEM_REG_INT_STS_0_THREAD_FIFO_ERROR_BB_K2_SHIFT                                                   16
+  #define TSEM_REG_INT_STS_0_THREAD_OVERRUN_BB_K2                                                            (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
+  #define TSEM_REG_INT_STS_0_THREAD_OVERRUN_BB_K2_SHIFT                                                      17
+  #define TSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2                                                 (0x1<<18) // Error in external store sync FIFO push logic.
+  #define TSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2_SHIFT                                           18
+  #define TSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_BB_K2                                                  (0x1<<19) // Error in external store sync FIFO pop logic.
+  #define TSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_BB_K2_SHIFT                                            19
+  #define TSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2                                                  (0x1<<20) // Error in external load sync FIFO push logic.
+  #define TSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2_SHIFT                                            20
+  #define TSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2                                                   (0x1<<21) // Error in external load sync FIFO pop logic.
+  #define TSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2_SHIFT                                             21
+  #define TSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR_BB_K2                                                     (0x1<<24) // Error in LS_SYNC_POP FIFO.
+  #define TSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR_BB_K2_SHIFT                                               24
+  #define TSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR_BB_K2                                                       (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
+  #define TSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR_BB_K2_SHIFT                                                 26
+  #define TSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_BB_K2                                                        (0x1<<27) // Error in LS_SYNC_POP FIFO.
+  #define TSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_BB_K2_SHIFT                                                  27
+  #define TSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO_BB_K2                                                         (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
+  #define TSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO_BB_K2_SHIFT                                                   29
+  #define TSEM_REG_INT_STS_0_VFC_INTERRUPT_BB_K2                                                             (0x1<<30) // Error interrupt in VFC block.
+  #define TSEM_REG_INT_STS_0_VFC_INTERRUPT_BB_K2_SHIFT                                                       30
+  #define TSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR_BB_K2                                                        (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
+  #define TSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR_BB_K2_SHIFT                                                  31
+#define TSEM_REG_INT_MASK_0                                                                                  0x1700044UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define TSEM_REG_INT_MASK_0_ADDRESS_ERROR                                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.ADDRESS_ERROR .
+  #define TSEM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                            0
+  #define TSEM_REG_INT_MASK_0_FIC_LAST_ERROR                                                                 (0x1<<1) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.FIC_LAST_ERROR .
+  #define TSEM_REG_INT_MASK_0_FIC_LAST_ERROR_SHIFT                                                           1
+  #define TSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR                                                               (0x1<<2) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.FIC_LENGTH_ERROR .
+  #define TSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR_SHIFT                                                         2
+  #define TSEM_REG_INT_MASK_0_FIC_FIFO_ERROR                                                                 (0x1<<3) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.FIC_FIFO_ERROR .
+  #define TSEM_REG_INT_MASK_0_FIC_FIFO_ERROR_SHIFT                                                           3
+  #define TSEM_REG_INT_MASK_0_DRA_RD_A_LAST_ERROR_E5                                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.DRA_RD_A_LAST_ERROR .
+  #define TSEM_REG_INT_MASK_0_DRA_RD_A_LAST_ERROR_E5_SHIFT                                                   4
+  #define TSEM_REG_INT_MASK_0_DRA_RD_B_LAST_ERROR_E5                                                         (0x1<<5) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.DRA_RD_B_LAST_ERROR .
+  #define TSEM_REG_INT_MASK_0_DRA_RD_B_LAST_ERROR_E5_SHIFT                                                   5
+  #define TSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_A_E5                                                  (0x1<<6) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR_A .
+  #define TSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_A_E5_SHIFT                                            6
+  #define TSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_B_E5                                                  (0x1<<7) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR_B .
+  #define TSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT                                            7
+  #define TSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5                                                  (0x1<<8) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR_A .
+  #define TSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT                                            8
+  #define TSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5                                                  (0x1<<9) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR_B .
+  #define TSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5_SHIFT                                            9
+  #define TSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2                                                   (0x1<<22) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_RAM_RD_PUSH_ERROR .
+  #define TSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2_SHIFT                                             22
+  #define TSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_E5                                                      (0x1<<10) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_RAM_RD_PUSH_ERROR .
+  #define TSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_E5_SHIFT                                                10
+  #define TSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_BB_K2                                                    (0x1<<23) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_RAM_RD_POP_ERROR .
+  #define TSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_BB_K2_SHIFT                                              23
+  #define TSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_E5                                                       (0x1<<11) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_RAM_RD_POP_ERROR .
+  #define TSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_E5_SHIFT                                                 11
+  #define TSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2                                                   (0x1<<25) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_RAM_WR_PUSH_ERROR .
+  #define TSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2_SHIFT                                             25
+  #define TSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_E5                                                      (0x1<<12) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_RAM_WR_PUSH_ERROR .
+  #define TSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_E5_SHIFT                                                12
+  #define TSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_A_E5                                                        (0x1<<13) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR_A .
+  #define TSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_A_E5_SHIFT                                                  13
+  #define TSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_B_E5                                                        (0x1<<14) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR_B .
+  #define TSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_B_E5_SHIFT                                                  14
+  #define TSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_BB_K2                                                           (0x1<<28) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.DBG_FIFO_ERROR .
+  #define TSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_BB_K2_SHIFT                                                     28
+  #define TSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_E5                                                              (0x1<<15) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.DBG_FIFO_ERROR .
+  #define TSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_E5_SHIFT                                                        15
+  #define TSEM_REG_INT_MASK_0_EXT_THREAD_OOR_ERROR_E5                                                        (0x1<<16) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.EXT_THREAD_OOR_ERROR .
+  #define TSEM_REG_INT_MASK_0_EXT_THREAD_OOR_ERROR_E5_SHIFT                                                  16
+  #define TSEM_REG_INT_MASK_0_EXT_STORE_TAG_ODER_ERROR_E5                                                    (0x1<<17) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.EXT_STORE_TAG_ODER_ERROR .
+  #define TSEM_REG_INT_MASK_0_EXT_STORE_TAG_ODER_ERROR_E5_SHIFT                                              17
+  #define TSEM_REG_INT_MASK_0_FIC1_AFFINITY_FIELD_ERROR_E5                                                   (0x1<<18) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.FIC1_AFFINITY_FIELD_ERROR .
+  #define TSEM_REG_INT_MASK_0_FIC1_AFFINITY_FIELD_ERROR_E5_SHIFT                                             18
+  #define TSEM_REG_INT_MASK_0_EXT_LD_LEN_ERROR_E5                                                            (0x1<<19) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.EXT_LD_LEN_ERROR .
+  #define TSEM_REG_INT_MASK_0_EXT_LD_LEN_ERROR_E5_SHIFT                                                      19
+  #define TSEM_REG_INT_MASK_0_PB_QUE_ARB_THRD_RDY_ERROR_E5                                                   (0x1<<20) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.PB_QUE_ARB_THRD_RDY_ERROR .
+  #define TSEM_REG_INT_MASK_0_PB_QUE_ARB_THRD_RDY_ERROR_E5_SHIFT                                             20
+  #define TSEM_REG_INT_MASK_0_SYNC_FOC_FIFO_ERROR_E5                                                         (0x1<<21) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_FOC_FIFO_ERROR .
+  #define TSEM_REG_INT_MASK_0_SYNC_FOC_FIFO_ERROR_E5_SHIFT                                                   21
+  #define TSEM_REG_INT_MASK_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                     (0x1<<22) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.PB_QUE_ARB_QUEUES_ERROR .
+  #define TSEM_REG_INT_MASK_0_PB_QUE_ARB_QUEUES_ERROR_E5_SHIFT                                               22
+  #define TSEM_REG_INT_MASK_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5                                               (0x1<<23) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.STORM_MOVRIND_USES_BAR_ATTN_A .
+  #define TSEM_REG_INT_MASK_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5_SHIFT                                         23
+  #define TSEM_REG_INT_MASK_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5                                               (0x1<<24) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.STORM_MOVRIND_USES_BAR_ATTN_B .
+  #define TSEM_REG_INT_MASK_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5_SHIFT                                         24
+  #define TSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC0_E5                                                           (0x1<<25) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.CREDIT_ERROR_FOC0 .
+  #define TSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC0_E5_SHIFT                                                     25
+  #define TSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC1_E5                                                           (0x1<<26) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.CREDIT_ERROR_FOC1 .
+  #define TSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC1_E5_SHIFT                                                     26
+  #define TSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC2_E5                                                           (0x1<<27) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.CREDIT_ERROR_FOC2 .
+  #define TSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC2_E5_SHIFT                                                     27
+  #define TSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC3_E5                                                           (0x1<<28) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.CREDIT_ERROR_FOC3 .
+  #define TSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC3_E5_SHIFT                                                     28
+  #define TSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC4_E5                                                           (0x1<<29) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.CREDIT_ERROR_FOC4 .
+  #define TSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC4_E5_SHIFT                                                     29
+  #define TSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC5_E5                                                           (0x1<<30) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.CREDIT_ERROR_FOC5 .
+  #define TSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC5_E5_SHIFT                                                     30
+  #define TSEM_REG_INT_MASK_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                    (0x1<<31) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.FOC_PRE_FETCH_FIFO_ERROR .
+  #define TSEM_REG_INT_MASK_0_FOC_PRE_FETCH_FIFO_ERROR_E5_SHIFT                                              31
+  #define TSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR_BB_K2                                                       (0x1<<4) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.PAS_BUF_FIFO_ERROR .
+  #define TSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR_BB_K2_SHIFT                                                 4
+  #define TSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR_BB_K2                                                       (0x1<<5) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_FIN_POP_ERROR .
+  #define TSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR_BB_K2_SHIFT                                                 5
+  #define TSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2                                                   (0x1<<6) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_DRA_WR_PUSH_ERROR .
+  #define TSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2_SHIFT                                             6
+  #define TSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR_BB_K2                                                    (0x1<<7) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_DRA_WR_POP_ERROR .
+  #define TSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT                                              7
+  #define TSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2                                                   (0x1<<8) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_DRA_RD_PUSH_ERROR .
+  #define TSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT                                             8
+  #define TSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR_BB_K2                                                    (0x1<<9) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_DRA_RD_POP_ERROR .
+  #define TSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR_BB_K2_SHIFT                                              9
+  #define TSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR_BB_K2                                                      (0x1<<10) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_FIN_PUSH_ERROR .
+  #define TSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR_BB_K2_SHIFT                                                10
+  #define TSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR_BB_K2                                                   (0x1<<11) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SEM_FAST_ADDRESS_ERROR .
+  #define TSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR_BB_K2_SHIFT                                             11
+  #define TSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO_BB_K2                                                         (0x1<<12) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.CAM_LSB_INP_FIFO .
+  #define TSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO_BB_K2_SHIFT                                                   12
+  #define TSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO_BB_K2                                                         (0x1<<13) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.CAM_MSB_INP_FIFO .
+  #define TSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO_BB_K2_SHIFT                                                   13
+  #define TSEM_REG_INT_MASK_0_CAM_OUT_FIFO_BB_K2                                                             (0x1<<14) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.CAM_OUT_FIFO .
+  #define TSEM_REG_INT_MASK_0_CAM_OUT_FIFO_BB_K2_SHIFT                                                       14
+  #define TSEM_REG_INT_MASK_0_FIN_FIFO_BB_K2                                                                 (0x1<<15) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.FIN_FIFO .
+  #define TSEM_REG_INT_MASK_0_FIN_FIFO_BB_K2_SHIFT                                                           15
+  #define TSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR_BB_K2                                                        (0x1<<16) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.THREAD_FIFO_ERROR .
+  #define TSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR_BB_K2_SHIFT                                                  16
+  #define TSEM_REG_INT_MASK_0_THREAD_OVERRUN_BB_K2                                                           (0x1<<17) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.THREAD_OVERRUN .
+  #define TSEM_REG_INT_MASK_0_THREAD_OVERRUN_BB_K2_SHIFT                                                     17
+  #define TSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2                                                (0x1<<18) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_EXT_STORE_PUSH_ERROR .
+  #define TSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2_SHIFT                                          18
+  #define TSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_BB_K2                                                 (0x1<<19) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR .
+  #define TSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_BB_K2_SHIFT                                           19
+  #define TSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2                                                 (0x1<<20) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR .
+  #define TSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2_SHIFT                                           20
+  #define TSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2                                                  (0x1<<21) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_EXT_LOAD_POP_ERROR .
+  #define TSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2_SHIFT                                            21
+  #define TSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR_BB_K2                                                    (0x1<<24) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_RAM_WR_POP_ERROR .
+  #define TSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR_BB_K2_SHIFT                                              24
+  #define TSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR_BB_K2                                                      (0x1<<26) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_DBG_PUSH_ERROR .
+  #define TSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR_BB_K2_SHIFT                                                26
+  #define TSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_BB_K2                                                       (0x1<<27) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR .
+  #define TSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_BB_K2_SHIFT                                                 27
+  #define TSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO_BB_K2                                                        (0x1<<29) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.CAM_MSB2_INP_FIFO .
+  #define TSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO_BB_K2_SHIFT                                                  29
+  #define TSEM_REG_INT_MASK_0_VFC_INTERRUPT_BB_K2                                                            (0x1<<30) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.VFC_INTERRUPT .
+  #define TSEM_REG_INT_MASK_0_VFC_INTERRUPT_BB_K2_SHIFT                                                      30
+  #define TSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR_BB_K2                                                       (0x1<<31) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.VFC_OUT_FIFO_ERROR .
+  #define TSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR_BB_K2_SHIFT                                                 31
+#define TSEM_REG_INT_STS_WR_0                                                                                0x1700048UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define TSEM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define TSEM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                          0
+  #define TSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR                                                               (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
+  #define TSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR_SHIFT                                                         1
+  #define TSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR                                                             (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
+  #define TSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR_SHIFT                                                       2
+  #define TSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR                                                               (0x1<<3) // Error in any one of the FIC FIFO is active.
+  #define TSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR_SHIFT                                                         3
+  #define TSEM_REG_INT_STS_WR_0_DRA_RD_A_LAST_ERROR_E5                                                       (0x1<<4) // DRA_RD_A last indication was unexpectedly received or was not received at expected time.
+  #define TSEM_REG_INT_STS_WR_0_DRA_RD_A_LAST_ERROR_E5_SHIFT                                                 4
+  #define TSEM_REG_INT_STS_WR_0_DRA_RD_B_LAST_ERROR_E5                                                       (0x1<<5) // DRA_RD_B last indication was unexpectedly received or was not received at expected time.
+  #define TSEM_REG_INT_STS_WR_0_DRA_RD_B_LAST_ERROR_E5_SHIFT                                                 5
+  #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_A_E5                                                (0x1<<6) // Error in external store slow sync FIFO pop logic of Storm A.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_A_E5_SHIFT                                          6
+  #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_B_E5                                                (0x1<<7) // Error in external store slow sync FIFO pop logic of Storm B.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT                                          7
+  #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5                                                (0x1<<8) // Error in external load sync slow FIFO push logic.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT                                          8
+  #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5                                                (0x1<<9) // Error in external load sync slow FIFO pop logic.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5_SHIFT                                          9
+  #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2                                                 (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2_SHIFT                                           22
+  #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_E5                                                    (0x1<<10) // Error in slow LS_SYNC_PUSH FIFO.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_E5_SHIFT                                              10
+  #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_BB_K2                                                  (0x1<<23) // Error in LS_SYNC_POP FIFO.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_BB_K2_SHIFT                                            23
+  #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_E5                                                     (0x1<<11) // Error in slow LS_SYNC_POP FIFO.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_E5_SHIFT                                               11
+  #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2                                                 (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2_SHIFT                                           25
+  #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_E5                                                    (0x1<<12) // Error in slow LS_SYNC_PUSH FIFO.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_E5_SHIFT                                              12
+  #define TSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_A_E5                                                      (0x1<<13) // Error in slow LS_SYNC_PUSH FIFO.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_A_E5_SHIFT                                                13
+  #define TSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_B_E5                                                      (0x1<<14) // Error in slow LS_SYNC_POP FIFO.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_B_E5_SHIFT                                                14
+  #define TSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_BB_K2                                                         (0x1<<28) // Error in slow debug fifo.
+  #define TSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_BB_K2_SHIFT                                                   28
+  #define TSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_E5                                                            (0x1<<15) // Error in slow debug fifo
+  #define TSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_E5_SHIFT                                                      15
+  #define TSEM_REG_INT_STS_WR_0_EXT_THREAD_OOR_ERROR_E5                                                      (0x1<<16) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define TSEM_REG_INT_STS_WR_0_EXT_THREAD_OOR_ERROR_E5_SHIFT                                                16
+  #define TSEM_REG_INT_STS_WR_0_EXT_STORE_TAG_ODER_ERROR_E5                                                  (0x1<<17) // Error detected in the ext Stroe interface internal TAG order ID.
+  #define TSEM_REG_INT_STS_WR_0_EXT_STORE_TAG_ODER_ERROR_E5_SHIFT                                            17
+  #define TSEM_REG_INT_STS_WR_0_FIC1_AFFINITY_FIELD_ERROR_E5                                                 (0x1<<18) // Indicates that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
+  #define TSEM_REG_INT_STS_WR_0_FIC1_AFFINITY_FIELD_ERROR_E5_SHIFT                                           18
+  #define TSEM_REG_INT_STS_WR_0_EXT_LD_LEN_ERROR_E5                                                          (0x1<<19) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define TSEM_REG_INT_STS_WR_0_EXT_LD_LEN_ERROR_E5_SHIFT                                                    19
+  #define TSEM_REG_INT_STS_WR_0_PB_QUE_ARB_THRD_RDY_ERROR_E5                                                 (0x1<<20) // Indicates that Passive Buffer State machine has unexpectedly received a ready indication in the following cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pending FOC" or "Ready FOC" state. b. Pending Ready indication is already asserted.
+  #define TSEM_REG_INT_STS_WR_0_PB_QUE_ARB_THRD_RDY_ERROR_E5_SHIFT                                           20
+  #define TSEM_REG_INT_STS_WR_0_SYNC_FOC_FIFO_ERROR_E5                                                       (0x1<<21) // Error indication on FOC sync FIFO.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_FOC_FIFO_ERROR_E5_SHIFT                                                 21
+  #define TSEM_REG_INT_STS_WR_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                   (0x1<<22) // The error indicates on an error of one the threads READY queues.
+  #define TSEM_REG_INT_STS_WR_0_PB_QUE_ARB_QUEUES_ERROR_E5_SHIFT                                             22
+  #define TSEM_REG_INT_STS_WR_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5                                             (0x1<<23) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define TSEM_REG_INT_STS_WR_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5_SHIFT                                       23
+  #define TSEM_REG_INT_STS_WR_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5                                             (0x1<<24) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define TSEM_REG_INT_STS_WR_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5_SHIFT                                       24
+  #define TSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC0_E5                                                         (0x1<<25) // FOC0 is out of credit.
+  #define TSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC0_E5_SHIFT                                                   25
+  #define TSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC1_E5                                                         (0x1<<26) // FOC1 is out of credit.
+  #define TSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC1_E5_SHIFT                                                   26
+  #define TSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC2_E5                                                         (0x1<<27) // FOC2 is out of credit.
+  #define TSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC2_E5_SHIFT                                                   27
+  #define TSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC3_E5                                                         (0x1<<28) // FOC3 is out of credit.
+  #define TSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC3_E5_SHIFT                                                   28
+  #define TSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC4_E5                                                         (0x1<<29) // FOC4 is out of credit.
+  #define TSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC4_E5_SHIFT                                                   29
+  #define TSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC5_E5                                                         (0x1<<30) // FOC5 is out of credit.
+  #define TSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC5_E5_SHIFT                                                   30
+  #define TSEM_REG_INT_STS_WR_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                  (0x1<<31) // Error indication of foc pre_fetch fifo.
+  #define TSEM_REG_INT_STS_WR_0_FOC_PRE_FETCH_FIFO_ERROR_E5_SHIFT                                            31
+  #define TSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR_BB_K2                                                     (0x1<<4) // Error in Ext PAS_FIFO is active.
+  #define TSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR_BB_K2_SHIFT                                               4
+  #define TSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR_BB_K2                                                     (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR_BB_K2_SHIFT                                               5
+  #define TSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2                                                 (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2_SHIFT                                           6
+  #define TSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR_BB_K2                                                  (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT                                            7
+  #define TSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2                                                 (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT                                           8
+  #define TSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR_BB_K2                                                  (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR_BB_K2_SHIFT                                            9
+  #define TSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR_BB_K2                                                    (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR_BB_K2_SHIFT                                              10
+  #define TSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR_BB_K2                                                 (0x1<<11) // Signals an unknown address in the fast-memory window.
+  #define TSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR_BB_K2_SHIFT                                           11
+  #define TSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO_BB_K2                                                       (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
+  #define TSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO_BB_K2_SHIFT                                                 12
+  #define TSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO_BB_K2                                                       (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
+  #define TSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO_BB_K2_SHIFT                                                 13
+  #define TSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO_BB_K2                                                           (0x1<<14) // Error in CAM_OUT fifo in cam block.
+  #define TSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO_BB_K2_SHIFT                                                     14
+  #define TSEM_REG_INT_STS_WR_0_FIN_FIFO_BB_K2                                                               (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
+  #define TSEM_REG_INT_STS_WR_0_FIN_FIFO_BB_K2_SHIFT                                                         15
+  #define TSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR_BB_K2                                                      (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
+  #define TSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR_BB_K2_SHIFT                                                16
+  #define TSEM_REG_INT_STS_WR_0_THREAD_OVERRUN_BB_K2                                                         (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
+  #define TSEM_REG_INT_STS_WR_0_THREAD_OVERRUN_BB_K2_SHIFT                                                   17
+  #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2                                              (0x1<<18) // Error in external store sync FIFO push logic.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2_SHIFT                                        18
+  #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_BB_K2                                               (0x1<<19) // Error in external store sync FIFO pop logic.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_BB_K2_SHIFT                                         19
+  #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2                                               (0x1<<20) // Error in external load sync FIFO push logic.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2_SHIFT                                         20
+  #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2                                                (0x1<<21) // Error in external load sync FIFO pop logic.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2_SHIFT                                          21
+  #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR_BB_K2                                                  (0x1<<24) // Error in LS_SYNC_POP FIFO.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR_BB_K2_SHIFT                                            24
+  #define TSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR_BB_K2                                                    (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR_BB_K2_SHIFT                                              26
+  #define TSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_BB_K2                                                     (0x1<<27) // Error in LS_SYNC_POP FIFO.
+  #define TSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_BB_K2_SHIFT                                               27
+  #define TSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO_BB_K2                                                      (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
+  #define TSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO_BB_K2_SHIFT                                                29
+  #define TSEM_REG_INT_STS_WR_0_VFC_INTERRUPT_BB_K2                                                          (0x1<<30) // Error interrupt in VFC block.
+  #define TSEM_REG_INT_STS_WR_0_VFC_INTERRUPT_BB_K2_SHIFT                                                    30
+  #define TSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR_BB_K2                                                     (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
+  #define TSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR_BB_K2_SHIFT                                               31
+#define TSEM_REG_INT_STS_CLR_0                                                                               0x170004cUL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define TSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                               (0x1<<0) // Signals an unknown address to the rf module.
+  #define TSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                         0
+  #define TSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR                                                              (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
+  #define TSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR_SHIFT                                                        1
+  #define TSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR                                                            (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
+  #define TSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR_SHIFT                                                      2
+  #define TSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR                                                              (0x1<<3) // Error in any one of the FIC FIFO is active.
+  #define TSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR_SHIFT                                                        3
+  #define TSEM_REG_INT_STS_CLR_0_DRA_RD_A_LAST_ERROR_E5                                                      (0x1<<4) // DRA_RD_A last indication was unexpectedly received or was not received at expected time.
+  #define TSEM_REG_INT_STS_CLR_0_DRA_RD_A_LAST_ERROR_E5_SHIFT                                                4
+  #define TSEM_REG_INT_STS_CLR_0_DRA_RD_B_LAST_ERROR_E5                                                      (0x1<<5) // DRA_RD_B last indication was unexpectedly received or was not received at expected time.
+  #define TSEM_REG_INT_STS_CLR_0_DRA_RD_B_LAST_ERROR_E5_SHIFT                                                5
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_A_E5                                               (0x1<<6) // Error in external store slow sync FIFO pop logic of Storm A.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_A_E5_SHIFT                                         6
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_B_E5                                               (0x1<<7) // Error in external store slow sync FIFO pop logic of Storm B.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT                                         7
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5                                               (0x1<<8) // Error in external load sync slow FIFO push logic.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT                                         8
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5                                               (0x1<<9) // Error in external load sync slow FIFO pop logic.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5_SHIFT                                         9
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2                                                (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2_SHIFT                                          22
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_E5                                                   (0x1<<10) // Error in slow LS_SYNC_PUSH FIFO.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_E5_SHIFT                                             10
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_BB_K2                                                 (0x1<<23) // Error in LS_SYNC_POP FIFO.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_BB_K2_SHIFT                                           23
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_E5                                                    (0x1<<11) // Error in slow LS_SYNC_POP FIFO.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_E5_SHIFT                                              11
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2                                                (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2_SHIFT                                          25
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_E5                                                   (0x1<<12) // Error in slow LS_SYNC_PUSH FIFO.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_E5_SHIFT                                             12
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_A_E5                                                     (0x1<<13) // Error in slow LS_SYNC_PUSH FIFO.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_A_E5_SHIFT                                               13
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_B_E5                                                     (0x1<<14) // Error in slow LS_SYNC_POP FIFO.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_B_E5_SHIFT                                               14
+  #define TSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_BB_K2                                                        (0x1<<28) // Error in slow debug fifo.
+  #define TSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_BB_K2_SHIFT                                                  28
+  #define TSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_E5                                                           (0x1<<15) // Error in slow debug fifo
+  #define TSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_E5_SHIFT                                                     15
+  #define TSEM_REG_INT_STS_CLR_0_EXT_THREAD_OOR_ERROR_E5                                                     (0x1<<16) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define TSEM_REG_INT_STS_CLR_0_EXT_THREAD_OOR_ERROR_E5_SHIFT                                               16
+  #define TSEM_REG_INT_STS_CLR_0_EXT_STORE_TAG_ODER_ERROR_E5                                                 (0x1<<17) // Error detected in the ext Stroe interface internal TAG order ID.
+  #define TSEM_REG_INT_STS_CLR_0_EXT_STORE_TAG_ODER_ERROR_E5_SHIFT                                           17
+  #define TSEM_REG_INT_STS_CLR_0_FIC1_AFFINITY_FIELD_ERROR_E5                                                (0x1<<18) // Indicates that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
+  #define TSEM_REG_INT_STS_CLR_0_FIC1_AFFINITY_FIELD_ERROR_E5_SHIFT                                          18
+  #define TSEM_REG_INT_STS_CLR_0_EXT_LD_LEN_ERROR_E5                                                         (0x1<<19) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define TSEM_REG_INT_STS_CLR_0_EXT_LD_LEN_ERROR_E5_SHIFT                                                   19
+  #define TSEM_REG_INT_STS_CLR_0_PB_QUE_ARB_THRD_RDY_ERROR_E5                                                (0x1<<20) // Indicates that Passive Buffer State machine has unexpectedly received a ready indication in the following cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pending FOC" or "Ready FOC" state. b. Pending Ready indication is already asserted.
+  #define TSEM_REG_INT_STS_CLR_0_PB_QUE_ARB_THRD_RDY_ERROR_E5_SHIFT                                          20
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_FOC_FIFO_ERROR_E5                                                      (0x1<<21) // Error indication on FOC sync FIFO.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_FOC_FIFO_ERROR_E5_SHIFT                                                21
+  #define TSEM_REG_INT_STS_CLR_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                  (0x1<<22) // The error indicates on an error of one the threads READY queues.
+  #define TSEM_REG_INT_STS_CLR_0_PB_QUE_ARB_QUEUES_ERROR_E5_SHIFT                                            22
+  #define TSEM_REG_INT_STS_CLR_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5                                            (0x1<<23) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define TSEM_REG_INT_STS_CLR_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5_SHIFT                                      23
+  #define TSEM_REG_INT_STS_CLR_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5                                            (0x1<<24) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define TSEM_REG_INT_STS_CLR_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5_SHIFT                                      24
+  #define TSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC0_E5                                                        (0x1<<25) // FOC0 is out of credit.
+  #define TSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC0_E5_SHIFT                                                  25
+  #define TSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC1_E5                                                        (0x1<<26) // FOC1 is out of credit.
+  #define TSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC1_E5_SHIFT                                                  26
+  #define TSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC2_E5                                                        (0x1<<27) // FOC2 is out of credit.
+  #define TSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC2_E5_SHIFT                                                  27
+  #define TSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC3_E5                                                        (0x1<<28) // FOC3 is out of credit.
+  #define TSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC3_E5_SHIFT                                                  28
+  #define TSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC4_E5                                                        (0x1<<29) // FOC4 is out of credit.
+  #define TSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC4_E5_SHIFT                                                  29
+  #define TSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC5_E5                                                        (0x1<<30) // FOC5 is out of credit.
+  #define TSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC5_E5_SHIFT                                                  30
+  #define TSEM_REG_INT_STS_CLR_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                 (0x1<<31) // Error indication of foc pre_fetch fifo.
+  #define TSEM_REG_INT_STS_CLR_0_FOC_PRE_FETCH_FIFO_ERROR_E5_SHIFT                                           31
+  #define TSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR_BB_K2                                                    (0x1<<4) // Error in Ext PAS_FIFO is active.
+  #define TSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR_BB_K2_SHIFT                                              4
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR_BB_K2                                                    (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR_BB_K2_SHIFT                                              5
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2                                                (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2_SHIFT                                          6
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR_BB_K2                                                 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT                                           7
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2                                                (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT                                          8
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR_BB_K2                                                 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR_BB_K2_SHIFT                                           9
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR_BB_K2                                                   (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR_BB_K2_SHIFT                                             10
+  #define TSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR_BB_K2                                                (0x1<<11) // Signals an unknown address in the fast-memory window.
+  #define TSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR_BB_K2_SHIFT                                          11
+  #define TSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO_BB_K2                                                      (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
+  #define TSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO_BB_K2_SHIFT                                                12
+  #define TSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO_BB_K2                                                      (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
+  #define TSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO_BB_K2_SHIFT                                                13
+  #define TSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO_BB_K2                                                          (0x1<<14) // Error in CAM_OUT fifo in cam block.
+  #define TSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO_BB_K2_SHIFT                                                    14
+  #define TSEM_REG_INT_STS_CLR_0_FIN_FIFO_BB_K2                                                              (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
+  #define TSEM_REG_INT_STS_CLR_0_FIN_FIFO_BB_K2_SHIFT                                                        15
+  #define TSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR_BB_K2                                                     (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
+  #define TSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR_BB_K2_SHIFT                                               16
+  #define TSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN_BB_K2                                                        (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
+  #define TSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN_BB_K2_SHIFT                                                  17
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2                                             (0x1<<18) // Error in external store sync FIFO push logic.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2_SHIFT                                       18
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_BB_K2                                              (0x1<<19) // Error in external store sync FIFO pop logic.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_BB_K2_SHIFT                                        19
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2                                              (0x1<<20) // Error in external load sync FIFO push logic.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2_SHIFT                                        20
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2                                               (0x1<<21) // Error in external load sync FIFO pop logic.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2_SHIFT                                         21
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR_BB_K2                                                 (0x1<<24) // Error in LS_SYNC_POP FIFO.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR_BB_K2_SHIFT                                           24
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR_BB_K2                                                   (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR_BB_K2_SHIFT                                             26
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_BB_K2                                                    (0x1<<27) // Error in LS_SYNC_POP FIFO.
+  #define TSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_BB_K2_SHIFT                                              27
+  #define TSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO_BB_K2                                                     (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
+  #define TSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO_BB_K2_SHIFT                                               29
+  #define TSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT_BB_K2                                                         (0x1<<30) // Error interrupt in VFC block.
+  #define TSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT_BB_K2_SHIFT                                                   30
+  #define TSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR_BB_K2                                                    (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
+  #define TSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR_BB_K2_SHIFT                                              31
+#define TSEM_REG_INT_STS_1                                                                                   0x1700050UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define TSEM_REG_INT_STS_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5                                              (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
+  #define TSEM_REG_INT_STS_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5_SHIFT                                        0
+  #define TSEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_A_E5                                                  (0x1<<1) // Fast external store FIFO error of Storm_A
+  #define TSEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT                                            1
+  #define TSEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_B_E5                                                  (0x1<<2) // Fast external store FIFO error of Storm_B
+  #define TSEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_B_E5_SHIFT                                            2
+  #define TSEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_A_E5                                                    (0x1<<3) // fast external load FIFO error of Storm_A
+  #define TSEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT                                              3
+  #define TSEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_B_E5                                                    (0x1<<4) // fast external load FIFO error of Storm_B
+  #define TSEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_B_E5_SHIFT                                              4
+  #define TSEM_REG_INT_STS_1_FAST_RAM_WR_POP_ERROR_E5                                                        (0x1<<5) // Internal RAM pop error
+  #define TSEM_REG_INT_STS_1_FAST_RAM_WR_POP_ERROR_E5_SHIFT                                                  5
+  #define TSEM_REG_INT_STS_1_FAST_RAM_RD_PUSH_ERROR_E5                                                       (0x1<<6) // Internal RAM write error
+  #define TSEM_REG_INT_STS_1_FAST_RAM_RD_PUSH_ERROR_E5_SHIFT                                                 6
+  #define TSEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_A_E5                                                     (0x1<<7) // DRA RD FIFO error of Storm A
+  #define TSEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT                                               7
+  #define TSEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_B_E5                                                     (0x1<<8) // DRA RD FIFO error of Storm B
+  #define TSEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT                                               8
+  #define TSEM_REG_INT_STS_1_FAST_DRA_WR_POP_ERROR_A_E5                                                      (0x1<<9) // DRA RD FIFO error of Storm A
+  #define TSEM_REG_INT_STS_1_FAST_DRA_WR_POP_ERROR_A_E5_SHIFT                                                9
+  #define TSEM_REG_INT_STS_1_FAST_DRA_WR_POP_ERROR_B_E5                                                      (0x1<<10) // DRA RD FIFO error of Storm B
+  #define TSEM_REG_INT_STS_1_FAST_DRA_WR_POP_ERROR_B_E5_SHIFT                                                10
+  #define TSEM_REG_INT_STS_1_SEM_FAST_INVLD_ADDR_ERR_E5                                                      (0x1<<11) // Fast invalid address error
+  #define TSEM_REG_INT_STS_1_SEM_FAST_INVLD_ADDR_ERR_E5_SHIFT                                                11
+  #define TSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_A_E5                                                        (0x1<<12) // Storm A stack_uf_attn interrupt
+  #define TSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_A_E5_SHIFT                                                  12
+  #define TSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_B_E5                                                        (0x1<<13) // Storm B stack_uf_attn interrupt
+  #define TSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_B_E5_SHIFT                                                  13
+  #define TSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_A_E5                                                        (0x1<<14) // Storm A stack_of_attn interrupt
+  #define TSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_A_E5_SHIFT                                                  14
+  #define TSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_B_E5                                                        (0x1<<15) // Storm B stack_of_attn interrupt
+  #define TSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_B_E5_SHIFT                                                  15
+  #define TSEM_REG_INT_STS_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5                                                 (0x1<<16) // Storm A ldst_addr_ovflw_attn interrupt
+  #define TSEM_REG_INT_STS_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5_SHIFT                                           16
+  #define TSEM_REG_INT_STS_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5                                                 (0x1<<17) // Storm B ldst_addr_ovflw_attn interrupt
+  #define TSEM_REG_INT_STS_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5_SHIFT                                           17
+  #define TSEM_REG_INT_STS_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5                                              (0x1<<18) // Storm A non_aligned_access_attn interrupt
+  #define TSEM_REG_INT_STS_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5_SHIFT                                        18
+  #define TSEM_REG_INT_STS_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5                                              (0x1<<19) // Storm B non_aligned_access_attn interrupt
+  #define TSEM_REG_INT_STS_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5_SHIFT                                        19
+  #define TSEM_REG_INT_STS_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5                                                (0x1<<20) // Storm A division_by_zero_attn interrupt
+  #define TSEM_REG_INT_STS_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5_SHIFT                                          20
+  #define TSEM_REG_INT_STS_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5                                                (0x1<<21) // Storm B division_by_zero_attn interrupt
+  #define TSEM_REG_INT_STS_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5_SHIFT                                          21
+  #define TSEM_REG_INT_STS_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5                                           (0x1<<22) // Storm A illegal_runtime_value_attn interrupt
+  #define TSEM_REG_INT_STS_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5_SHIFT                                     22
+  #define TSEM_REG_INT_STS_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5                                           (0x1<<23) // Storm B illegal_runtime_value_attn interrupt
+  #define TSEM_REG_INT_STS_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5_SHIFT                                     23
+  #define TSEM_REG_INT_STS_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5                                            (0x1<<24) // load request is made while previous is still active; not fully read, Storm A
+  #define TSEM_REG_INT_STS_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5_SHIFT                                      24
+  #define TSEM_REG_INT_STS_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5                                            (0x1<<25) // load request is made while previous is still active; not fully read, Storm B
+  #define TSEM_REG_INT_STS_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5_SHIFT                                      25
+  #define TSEM_REG_INT_STS_1_CAM_RBC_FAST_OUT_ERROR_A_E5                                                     (0x1<<26) // Error in CAM_OUT fifo in cam block of STORM A
+  #define TSEM_REG_INT_STS_1_CAM_RBC_FAST_OUT_ERROR_A_E5_SHIFT                                               26
+  #define TSEM_REG_INT_STS_1_CAM_RBC_FAST_OUT_ERROR_B_E5                                                     (0x1<<27) // Error in CAM_OUT fifo in cam block of STORM B
+  #define TSEM_REG_INT_STS_1_CAM_RBC_FAST_OUT_ERROR_B_E5_SHIFT                                               27
+  #define TSEM_REG_INT_STS_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5                                                 (0x1<<28) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define TSEM_REG_INT_STS_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5_SHIFT                                           28
+  #define TSEM_REG_INT_STS_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5                                                 (0x1<<29) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define TSEM_REG_INT_STS_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5_SHIFT                                           29
+  #define TSEM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5                                                 (0x1<<30) // Error in CAM_LSB_INP fifo in cam block of STORM A
+  #define TSEM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT                                           30
+  #define TSEM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5                                                 (0x1<<31) // Error in CAM_LSB_INP fifo in cam block of STORM B.
+  #define TSEM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5_SHIFT                                           31
+  #define TSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_BB_K2                                                       (0x1<<0) // An underflow error was detected in the Storm stack.
+  #define TSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_BB_K2_SHIFT                                                 0
+  #define TSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_BB_K2                                                       (0x1<<1) // An overflow error was detected in the Storm stack.
+  #define TSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT                                                 1
+  #define TSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR_BB_K2                                                       (0x1<<2) // The Storm detected an illegal runtime value.
+  #define TSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR_BB_K2_SHIFT                                                 2
+  #define TSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR_BB_K2                                                    (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
+  #define TSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT                                              3
+  #define TSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR_BB_K2                                                     (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
+  #define TSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR_BB_K2_SHIFT                                               4
+  #define TSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR_BB_K2                                                     (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
+  #define TSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR_BB_K2_SHIFT                                               5
+  #define TSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR_BB_K2                                                      (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
+  #define TSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR_BB_K2_SHIFT                                                6
+  #define TSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR_BB_K2                                                      (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define TSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT                                                7
+  #define TSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR_BB_K2                                                         (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
+  #define TSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT                                                   8
+  #define TSEM_REG_INT_STS_1_INVLD_FOC_ERROR_BB_K2                                                           (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
+  #define TSEM_REG_INT_STS_1_INVLD_FOC_ERROR_BB_K2_SHIFT                                                     9
+  #define TSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR_BB_K2                                                          (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define TSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR_BB_K2_SHIFT                                                    10
+  #define TSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR_BB_K2                                                       (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
+  #define TSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR_BB_K2_SHIFT                                                 11
+  #define TSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR_BB_K2                                                      (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
+  #define TSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR_BB_K2_SHIFT                                                12
+#define TSEM_REG_INT_MASK_1                                                                                  0x1700054UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define TSEM_REG_INT_MASK_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5                                             (0x1<<0) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.RBC_COMMON_ACCESS_COL_VFC_ERROR .
+  #define TSEM_REG_INT_MASK_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5_SHIFT                                       0
+  #define TSEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_A_E5                                                 (0x1<<1) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.FAST_EXT_STORE_PUSH_ERROR_A .
+  #define TSEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT                                           1
+  #define TSEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_B_E5                                                 (0x1<<2) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.FAST_EXT_STORE_PUSH_ERROR_B .
+  #define TSEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_B_E5_SHIFT                                           2
+  #define TSEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_A_E5                                                   (0x1<<3) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.FAST_EXT_LOAD_POP_ERROR_A .
+  #define TSEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT                                             3
+  #define TSEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_B_E5                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.FAST_EXT_LOAD_POP_ERROR_B .
+  #define TSEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_B_E5_SHIFT                                             4
+  #define TSEM_REG_INT_MASK_1_FAST_RAM_WR_POP_ERROR_E5                                                       (0x1<<5) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.FAST_RAM_WR_POP_ERROR .
+  #define TSEM_REG_INT_MASK_1_FAST_RAM_WR_POP_ERROR_E5_SHIFT                                                 5
+  #define TSEM_REG_INT_MASK_1_FAST_RAM_RD_PUSH_ERROR_E5                                                      (0x1<<6) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.FAST_RAM_RD_PUSH_ERROR .
+  #define TSEM_REG_INT_MASK_1_FAST_RAM_RD_PUSH_ERROR_E5_SHIFT                                                6
+  #define TSEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_A_E5                                                    (0x1<<7) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.FAST_DRA_RD_PUSH_ERROR_A .
+  #define TSEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT                                              7
+  #define TSEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_B_E5                                                    (0x1<<8) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.FAST_DRA_RD_PUSH_ERROR_B .
+  #define TSEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT                                              8
+  #define TSEM_REG_INT_MASK_1_FAST_DRA_WR_POP_ERROR_A_E5                                                     (0x1<<9) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.FAST_DRA_WR_POP_ERROR_A .
+  #define TSEM_REG_INT_MASK_1_FAST_DRA_WR_POP_ERROR_A_E5_SHIFT                                               9
+  #define TSEM_REG_INT_MASK_1_FAST_DRA_WR_POP_ERROR_B_E5                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.FAST_DRA_WR_POP_ERROR_B .
+  #define TSEM_REG_INT_MASK_1_FAST_DRA_WR_POP_ERROR_B_E5_SHIFT                                               10
+  #define TSEM_REG_INT_MASK_1_SEM_FAST_INVLD_ADDR_ERR_E5                                                     (0x1<<11) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.SEM_FAST_INVLD_ADDR_ERR .
+  #define TSEM_REG_INT_MASK_1_SEM_FAST_INVLD_ADDR_ERR_E5_SHIFT                                               11
+  #define TSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_A_E5                                                       (0x1<<12) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN_A .
+  #define TSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_A_E5_SHIFT                                                 12
+  #define TSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_B_E5                                                       (0x1<<13) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN_B .
+  #define TSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_B_E5_SHIFT                                                 13
+  #define TSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_A_E5                                                       (0x1<<14) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN_A .
+  #define TSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_A_E5_SHIFT                                                 14
+  #define TSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_B_E5                                                       (0x1<<15) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN_B .
+  #define TSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_B_E5_SHIFT                                                 15
+  #define TSEM_REG_INT_MASK_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5                                                (0x1<<16) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.STORM_LDST_ADDR_OVFLW_ATTN_A .
+  #define TSEM_REG_INT_MASK_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5_SHIFT                                          16
+  #define TSEM_REG_INT_MASK_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5                                                (0x1<<17) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.STORM_LDST_ADDR_OVFLW_ATTN_B .
+  #define TSEM_REG_INT_MASK_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5_SHIFT                                          17
+  #define TSEM_REG_INT_MASK_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5                                             (0x1<<18) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.STORM_NON_ALIGNED_ACCESS_ATTN_A .
+  #define TSEM_REG_INT_MASK_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5_SHIFT                                       18
+  #define TSEM_REG_INT_MASK_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5                                             (0x1<<19) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.STORM_NON_ALIGNED_ACCESS_ATTN_B .
+  #define TSEM_REG_INT_MASK_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5_SHIFT                                       19
+  #define TSEM_REG_INT_MASK_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5                                               (0x1<<20) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.STORM_DIVISION_BY_ZERO_ATTN_A .
+  #define TSEM_REG_INT_MASK_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5_SHIFT                                         20
+  #define TSEM_REG_INT_MASK_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5                                               (0x1<<21) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.STORM_DIVISION_BY_ZERO_ATTN_B .
+  #define TSEM_REG_INT_MASK_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5_SHIFT                                         21
+  #define TSEM_REG_INT_MASK_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5                                          (0x1<<22) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A .
+  #define TSEM_REG_INT_MASK_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5_SHIFT                                    22
+  #define TSEM_REG_INT_MASK_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5                                          (0x1<<23) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B .
+  #define TSEM_REG_INT_MASK_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5_SHIFT                                    23
+  #define TSEM_REG_INT_MASK_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5                                           (0x1<<24) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A .
+  #define TSEM_REG_INT_MASK_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5_SHIFT                                     24
+  #define TSEM_REG_INT_MASK_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5                                           (0x1<<25) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B .
+  #define TSEM_REG_INT_MASK_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5_SHIFT                                     25
+  #define TSEM_REG_INT_MASK_1_CAM_RBC_FAST_OUT_ERROR_A_E5                                                    (0x1<<26) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.CAM_RBC_FAST_OUT_ERROR_A .
+  #define TSEM_REG_INT_MASK_1_CAM_RBC_FAST_OUT_ERROR_A_E5_SHIFT                                              26
+  #define TSEM_REG_INT_MASK_1_CAM_RBC_FAST_OUT_ERROR_B_E5                                                    (0x1<<27) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.CAM_RBC_FAST_OUT_ERROR_B .
+  #define TSEM_REG_INT_MASK_1_CAM_RBC_FAST_OUT_ERROR_B_E5_SHIFT                                              27
+  #define TSEM_REG_INT_MASK_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5                                                (0x1<<28) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.CAM_RBC_FAST_MSB_INP_ERROR_A .
+  #define TSEM_REG_INT_MASK_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5_SHIFT                                          28
+  #define TSEM_REG_INT_MASK_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5                                                (0x1<<29) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.CAM_RBC_FAST_MSB_INP_ERROR_B .
+  #define TSEM_REG_INT_MASK_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5_SHIFT                                          29
+  #define TSEM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5                                                (0x1<<30) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.CAM_RBC_FAST_LSB_INP_ERROR_A .
+  #define TSEM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT                                          30
+  #define TSEM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5                                                (0x1<<31) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.CAM_RBC_FAST_LSB_INP_ERROR_B .
+  #define TSEM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5_SHIFT                                          31
+  #define TSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_BB_K2                                                      (0x1<<0) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN .
+  #define TSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_BB_K2_SHIFT                                                0
+  #define TSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_BB_K2                                                      (0x1<<1) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN .
+  #define TSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT                                                1
+  #define TSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR_BB_K2                                                      (0x1<<2) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.STORM_RUNTIME_ERROR .
+  #define TSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR_BB_K2_SHIFT                                                2
+  #define TSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR_BB_K2                                                   (0x1<<3) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.EXT_LOAD_PEND_WR_ERROR .
+  #define TSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT                                             3
+  #define TSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR_BB_K2                                                    (0x1<<4) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.THREAD_RLS_ORUN_ERROR .
+  #define TSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR_BB_K2_SHIFT                                              4
+  #define TSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR_BB_K2                                                    (0x1<<5) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.THREAD_RLS_ALOC_ERROR .
+  #define TSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR_BB_K2_SHIFT                                              5
+  #define TSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR_BB_K2                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.THREAD_RLS_VLD_ERROR .
+  #define TSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR_BB_K2_SHIFT                                               6
+  #define TSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR_BB_K2                                                     (0x1<<7) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.EXT_THREAD_OOR_ERROR .
+  #define TSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT                                               7
+  #define TSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR_BB_K2                                                        (0x1<<8) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.ORD_ID_FIFO_ERROR .
+  #define TSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT                                                  8
+  #define TSEM_REG_INT_MASK_1_INVLD_FOC_ERROR_BB_K2                                                          (0x1<<9) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.INVLD_FOC_ERROR .
+  #define TSEM_REG_INT_MASK_1_INVLD_FOC_ERROR_BB_K2_SHIFT                                                    9
+  #define TSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR_BB_K2                                                         (0x1<<10) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.EXT_LD_LEN_ERROR .
+  #define TSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR_BB_K2_SHIFT                                                   10
+  #define TSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR_BB_K2                                                      (0x1<<11) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.THRD_ORD_FIFO_ERROR .
+  #define TSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR_BB_K2_SHIFT                                                11
+  #define TSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR_BB_K2                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.INVLD_THRD_ORD_ERROR .
+  #define TSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR_BB_K2_SHIFT                                               12
+#define TSEM_REG_INT_STS_WR_1                                                                                0x1700058UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define TSEM_REG_INT_STS_WR_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5                                           (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
+  #define TSEM_REG_INT_STS_WR_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5_SHIFT                                     0
+  #define TSEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5                                               (0x1<<1) // Fast external store FIFO error of Storm_A
+  #define TSEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT                                         1
+  #define TSEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_B_E5                                               (0x1<<2) // Fast external store FIFO error of Storm_B
+  #define TSEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_B_E5_SHIFT                                         2
+  #define TSEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_A_E5                                                 (0x1<<3) // fast external load FIFO error of Storm_A
+  #define TSEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT                                           3
+  #define TSEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_B_E5                                                 (0x1<<4) // fast external load FIFO error of Storm_B
+  #define TSEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_B_E5_SHIFT                                           4
+  #define TSEM_REG_INT_STS_WR_1_FAST_RAM_WR_POP_ERROR_E5                                                     (0x1<<5) // Internal RAM pop error
+  #define TSEM_REG_INT_STS_WR_1_FAST_RAM_WR_POP_ERROR_E5_SHIFT                                               5
+  #define TSEM_REG_INT_STS_WR_1_FAST_RAM_RD_PUSH_ERROR_E5                                                    (0x1<<6) // Internal RAM write error
+  #define TSEM_REG_INT_STS_WR_1_FAST_RAM_RD_PUSH_ERROR_E5_SHIFT                                              6
+  #define TSEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_A_E5                                                  (0x1<<7) // DRA RD FIFO error of Storm A
+  #define TSEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT                                            7
+  #define TSEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_B_E5                                                  (0x1<<8) // DRA RD FIFO error of Storm B
+  #define TSEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT                                            8
+  #define TSEM_REG_INT_STS_WR_1_FAST_DRA_WR_POP_ERROR_A_E5                                                   (0x1<<9) // DRA RD FIFO error of Storm A
+  #define TSEM_REG_INT_STS_WR_1_FAST_DRA_WR_POP_ERROR_A_E5_SHIFT                                             9
+  #define TSEM_REG_INT_STS_WR_1_FAST_DRA_WR_POP_ERROR_B_E5                                                   (0x1<<10) // DRA RD FIFO error of Storm B
+  #define TSEM_REG_INT_STS_WR_1_FAST_DRA_WR_POP_ERROR_B_E5_SHIFT                                             10
+  #define TSEM_REG_INT_STS_WR_1_SEM_FAST_INVLD_ADDR_ERR_E5                                                   (0x1<<11) // Fast invalid address error
+  #define TSEM_REG_INT_STS_WR_1_SEM_FAST_INVLD_ADDR_ERR_E5_SHIFT                                             11
+  #define TSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_A_E5                                                     (0x1<<12) // Storm A stack_uf_attn interrupt
+  #define TSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_A_E5_SHIFT                                               12
+  #define TSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_B_E5                                                     (0x1<<13) // Storm B stack_uf_attn interrupt
+  #define TSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_B_E5_SHIFT                                               13
+  #define TSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_A_E5                                                     (0x1<<14) // Storm A stack_of_attn interrupt
+  #define TSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_A_E5_SHIFT                                               14
+  #define TSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_B_E5                                                     (0x1<<15) // Storm B stack_of_attn interrupt
+  #define TSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_B_E5_SHIFT                                               15
+  #define TSEM_REG_INT_STS_WR_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5                                              (0x1<<16) // Storm A ldst_addr_ovflw_attn interrupt
+  #define TSEM_REG_INT_STS_WR_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5_SHIFT                                        16
+  #define TSEM_REG_INT_STS_WR_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5                                              (0x1<<17) // Storm B ldst_addr_ovflw_attn interrupt
+  #define TSEM_REG_INT_STS_WR_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5_SHIFT                                        17
+  #define TSEM_REG_INT_STS_WR_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5                                           (0x1<<18) // Storm A non_aligned_access_attn interrupt
+  #define TSEM_REG_INT_STS_WR_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5_SHIFT                                     18
+  #define TSEM_REG_INT_STS_WR_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5                                           (0x1<<19) // Storm B non_aligned_access_attn interrupt
+  #define TSEM_REG_INT_STS_WR_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5_SHIFT                                     19
+  #define TSEM_REG_INT_STS_WR_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5                                             (0x1<<20) // Storm A division_by_zero_attn interrupt
+  #define TSEM_REG_INT_STS_WR_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5_SHIFT                                       20
+  #define TSEM_REG_INT_STS_WR_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5                                             (0x1<<21) // Storm B division_by_zero_attn interrupt
+  #define TSEM_REG_INT_STS_WR_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5_SHIFT                                       21
+  #define TSEM_REG_INT_STS_WR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5                                        (0x1<<22) // Storm A illegal_runtime_value_attn interrupt
+  #define TSEM_REG_INT_STS_WR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5_SHIFT                                  22
+  #define TSEM_REG_INT_STS_WR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5                                        (0x1<<23) // Storm B illegal_runtime_value_attn interrupt
+  #define TSEM_REG_INT_STS_WR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5_SHIFT                                  23
+  #define TSEM_REG_INT_STS_WR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5                                         (0x1<<24) // load request is made while previous is still active; not fully read, Storm A
+  #define TSEM_REG_INT_STS_WR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5_SHIFT                                   24
+  #define TSEM_REG_INT_STS_WR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5                                         (0x1<<25) // load request is made while previous is still active; not fully read, Storm B
+  #define TSEM_REG_INT_STS_WR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5_SHIFT                                   25
+  #define TSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_OUT_ERROR_A_E5                                                  (0x1<<26) // Error in CAM_OUT fifo in cam block of STORM A
+  #define TSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_OUT_ERROR_A_E5_SHIFT                                            26
+  #define TSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_OUT_ERROR_B_E5                                                  (0x1<<27) // Error in CAM_OUT fifo in cam block of STORM B
+  #define TSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_OUT_ERROR_B_E5_SHIFT                                            27
+  #define TSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5                                              (0x1<<28) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define TSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5_SHIFT                                        28
+  #define TSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5                                              (0x1<<29) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define TSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5_SHIFT                                        29
+  #define TSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5                                              (0x1<<30) // Error in CAM_LSB_INP fifo in cam block of STORM A
+  #define TSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT                                        30
+  #define TSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5                                              (0x1<<31) // Error in CAM_LSB_INP fifo in cam block of STORM B.
+  #define TSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5_SHIFT                                        31
+  #define TSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_BB_K2                                                    (0x1<<0) // An underflow error was detected in the Storm stack.
+  #define TSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_BB_K2_SHIFT                                              0
+  #define TSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_BB_K2                                                    (0x1<<1) // An overflow error was detected in the Storm stack.
+  #define TSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT                                              1
+  #define TSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR_BB_K2                                                    (0x1<<2) // The Storm detected an illegal runtime value.
+  #define TSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR_BB_K2_SHIFT                                              2
+  #define TSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2                                                 (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
+  #define TSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT                                           3
+  #define TSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR_BB_K2                                                  (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
+  #define TSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR_BB_K2_SHIFT                                            4
+  #define TSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR_BB_K2                                                  (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
+  #define TSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR_BB_K2_SHIFT                                            5
+  #define TSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR_BB_K2                                                   (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
+  #define TSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR_BB_K2_SHIFT                                             6
+  #define TSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR_BB_K2                                                   (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define TSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT                                             7
+  #define TSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR_BB_K2                                                      (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
+  #define TSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT                                                8
+  #define TSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR_BB_K2                                                        (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
+  #define TSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR_BB_K2_SHIFT                                                  9
+  #define TSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR_BB_K2                                                       (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define TSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR_BB_K2_SHIFT                                                 10
+  #define TSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR_BB_K2                                                    (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
+  #define TSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR_BB_K2_SHIFT                                              11
+  #define TSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR_BB_K2                                                   (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
+  #define TSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR_BB_K2_SHIFT                                             12
+#define TSEM_REG_INT_STS_CLR_1                                                                               0x170005cUL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define TSEM_REG_INT_STS_CLR_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5                                          (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
+  #define TSEM_REG_INT_STS_CLR_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5_SHIFT                                    0
+  #define TSEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5                                              (0x1<<1) // Fast external store FIFO error of Storm_A
+  #define TSEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT                                        1
+  #define TSEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_B_E5                                              (0x1<<2) // Fast external store FIFO error of Storm_B
+  #define TSEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_B_E5_SHIFT                                        2
+  #define TSEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_A_E5                                                (0x1<<3) // fast external load FIFO error of Storm_A
+  #define TSEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT                                          3
+  #define TSEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_B_E5                                                (0x1<<4) // fast external load FIFO error of Storm_B
+  #define TSEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_B_E5_SHIFT                                          4
+  #define TSEM_REG_INT_STS_CLR_1_FAST_RAM_WR_POP_ERROR_E5                                                    (0x1<<5) // Internal RAM pop error
+  #define TSEM_REG_INT_STS_CLR_1_FAST_RAM_WR_POP_ERROR_E5_SHIFT                                              5
+  #define TSEM_REG_INT_STS_CLR_1_FAST_RAM_RD_PUSH_ERROR_E5                                                   (0x1<<6) // Internal RAM write error
+  #define TSEM_REG_INT_STS_CLR_1_FAST_RAM_RD_PUSH_ERROR_E5_SHIFT                                             6
+  #define TSEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_A_E5                                                 (0x1<<7) // DRA RD FIFO error of Storm A
+  #define TSEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT                                           7
+  #define TSEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_B_E5                                                 (0x1<<8) // DRA RD FIFO error of Storm B
+  #define TSEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT                                           8
+  #define TSEM_REG_INT_STS_CLR_1_FAST_DRA_WR_POP_ERROR_A_E5                                                  (0x1<<9) // DRA RD FIFO error of Storm A
+  #define TSEM_REG_INT_STS_CLR_1_FAST_DRA_WR_POP_ERROR_A_E5_SHIFT                                            9
+  #define TSEM_REG_INT_STS_CLR_1_FAST_DRA_WR_POP_ERROR_B_E5                                                  (0x1<<10) // DRA RD FIFO error of Storm B
+  #define TSEM_REG_INT_STS_CLR_1_FAST_DRA_WR_POP_ERROR_B_E5_SHIFT                                            10
+  #define TSEM_REG_INT_STS_CLR_1_SEM_FAST_INVLD_ADDR_ERR_E5                                                  (0x1<<11) // Fast invalid address error
+  #define TSEM_REG_INT_STS_CLR_1_SEM_FAST_INVLD_ADDR_ERR_E5_SHIFT                                            11
+  #define TSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_A_E5                                                    (0x1<<12) // Storm A stack_uf_attn interrupt
+  #define TSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_A_E5_SHIFT                                              12
+  #define TSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_B_E5                                                    (0x1<<13) // Storm B stack_uf_attn interrupt
+  #define TSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_B_E5_SHIFT                                              13
+  #define TSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_A_E5                                                    (0x1<<14) // Storm A stack_of_attn interrupt
+  #define TSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_A_E5_SHIFT                                              14
+  #define TSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_B_E5                                                    (0x1<<15) // Storm B stack_of_attn interrupt
+  #define TSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_B_E5_SHIFT                                              15
+  #define TSEM_REG_INT_STS_CLR_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5                                             (0x1<<16) // Storm A ldst_addr_ovflw_attn interrupt
+  #define TSEM_REG_INT_STS_CLR_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5_SHIFT                                       16
+  #define TSEM_REG_INT_STS_CLR_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5                                             (0x1<<17) // Storm B ldst_addr_ovflw_attn interrupt
+  #define TSEM_REG_INT_STS_CLR_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5_SHIFT                                       17
+  #define TSEM_REG_INT_STS_CLR_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5                                          (0x1<<18) // Storm A non_aligned_access_attn interrupt
+  #define TSEM_REG_INT_STS_CLR_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5_SHIFT                                    18
+  #define TSEM_REG_INT_STS_CLR_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5                                          (0x1<<19) // Storm B non_aligned_access_attn interrupt
+  #define TSEM_REG_INT_STS_CLR_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5_SHIFT                                    19
+  #define TSEM_REG_INT_STS_CLR_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5                                            (0x1<<20) // Storm A division_by_zero_attn interrupt
+  #define TSEM_REG_INT_STS_CLR_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5_SHIFT                                      20
+  #define TSEM_REG_INT_STS_CLR_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5                                            (0x1<<21) // Storm B division_by_zero_attn interrupt
+  #define TSEM_REG_INT_STS_CLR_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5_SHIFT                                      21
+  #define TSEM_REG_INT_STS_CLR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5                                       (0x1<<22) // Storm A illegal_runtime_value_attn interrupt
+  #define TSEM_REG_INT_STS_CLR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5_SHIFT                                 22
+  #define TSEM_REG_INT_STS_CLR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5                                       (0x1<<23) // Storm B illegal_runtime_value_attn interrupt
+  #define TSEM_REG_INT_STS_CLR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5_SHIFT                                 23
+  #define TSEM_REG_INT_STS_CLR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5                                        (0x1<<24) // load request is made while previous is still active; not fully read, Storm A
+  #define TSEM_REG_INT_STS_CLR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5_SHIFT                                  24
+  #define TSEM_REG_INT_STS_CLR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5                                        (0x1<<25) // load request is made while previous is still active; not fully read, Storm B
+  #define TSEM_REG_INT_STS_CLR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5_SHIFT                                  25
+  #define TSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_OUT_ERROR_A_E5                                                 (0x1<<26) // Error in CAM_OUT fifo in cam block of STORM A
+  #define TSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_OUT_ERROR_A_E5_SHIFT                                           26
+  #define TSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_OUT_ERROR_B_E5                                                 (0x1<<27) // Error in CAM_OUT fifo in cam block of STORM B
+  #define TSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_OUT_ERROR_B_E5_SHIFT                                           27
+  #define TSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5                                             (0x1<<28) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define TSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5_SHIFT                                       28
+  #define TSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5                                             (0x1<<29) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define TSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5_SHIFT                                       29
+  #define TSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5                                             (0x1<<30) // Error in CAM_LSB_INP fifo in cam block of STORM A
+  #define TSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT                                       30
+  #define TSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5                                             (0x1<<31) // Error in CAM_LSB_INP fifo in cam block of STORM B.
+  #define TSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5_SHIFT                                       31
+  #define TSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_BB_K2                                                   (0x1<<0) // An underflow error was detected in the Storm stack.
+  #define TSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_BB_K2_SHIFT                                             0
+  #define TSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_BB_K2                                                   (0x1<<1) // An overflow error was detected in the Storm stack.
+  #define TSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT                                             1
+  #define TSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR_BB_K2                                                   (0x1<<2) // The Storm detected an illegal runtime value.
+  #define TSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR_BB_K2_SHIFT                                             2
+  #define TSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2                                                (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
+  #define TSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT                                          3
+  #define TSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR_BB_K2                                                 (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
+  #define TSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR_BB_K2_SHIFT                                           4
+  #define TSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR_BB_K2                                                 (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
+  #define TSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR_BB_K2_SHIFT                                           5
+  #define TSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR_BB_K2                                                  (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
+  #define TSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR_BB_K2_SHIFT                                            6
+  #define TSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR_BB_K2                                                  (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define TSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT                                            7
+  #define TSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR_BB_K2                                                     (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
+  #define TSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT                                               8
+  #define TSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR_BB_K2                                                       (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
+  #define TSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR_BB_K2_SHIFT                                                 9
+  #define TSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR_BB_K2                                                      (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define TSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR_BB_K2_SHIFT                                                10
+  #define TSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR_BB_K2                                                   (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
+  #define TSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR_BB_K2_SHIFT                                             11
+  #define TSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR_BB_K2                                                  (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
+  #define TSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR_BB_K2_SHIFT                                            12
+#define TSEM_REG_INT_STS_2_E5                                                                                0x1700060UL //Access:R    DataWidth:0x1f   // Multi Field Register.
+  #define TSEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5                                                 (0x1<<0) // Fast FIN FIFO error of Storm A.
+  #define TSEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5_SHIFT                                           0
+  #define TSEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5                                                 (0x1<<1) // Fast FIN FIFO error of Storm B
+  #define TSEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT                                           1
+  #define TSEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5                                               (0x1<<2) // Fast Debug FIFO error of Storm A
+  #define TSEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5_SHIFT                                         2
+  #define TSEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5                                               (0x1<<3) // Fast Debug FIFO error of Storm B
+  #define TSEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT                                         3
+  #define TSEM_REG_INT_STS_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5                                                (0x1<<4) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define TSEM_REG_INT_STS_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5_SHIFT                                          4
+  #define TSEM_REG_INT_STS_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5                                                (0x1<<5) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define TSEM_REG_INT_STS_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5_SHIFT                                          5
+  #define TSEM_REG_INT_STS_2_VFC_INTERRUPT_E5                                                                (0x1<<6) // interrupt from VFC block
+  #define TSEM_REG_INT_STS_2_VFC_INTERRUPT_E5_SHIFT                                                          6
+  #define TSEM_REG_INT_STS_2_MUX_RBC_VFC_FIFO_ERROR_E5                                                       (0x1<<7) // VFC FIFO error
+  #define TSEM_REG_INT_STS_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT                                                 7
+  #define TSEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_A_E5                                                    (0x1<<8) // Error in FOC error of Storm A.
+  #define TSEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT                                              8
+  #define TSEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_B_E5                                                    (0x1<<9) // Error in FOC error of Storm B.
+  #define TSEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_B_E5_SHIFT                                              9
+  #define TSEM_REG_INT_STS_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5                                                  (0x1<<10) // Invalid allocated thread request with partial FIN of Storm A.
+  #define TSEM_REG_INT_STS_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5_SHIFT                                            10
+  #define TSEM_REG_INT_STS_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5                                                  (0x1<<11) // Invalid allocated thread request with partial FIN of Storm B.
+  #define TSEM_REG_INT_STS_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5_SHIFT                                            11
+  #define TSEM_REG_INT_STS_2_CAM_RBC_INPUT_FIFO_ERROR_E5                                                     (0x1<<12) // Cam input FIFO error
+  #define TSEM_REG_INT_STS_2_CAM_RBC_INPUT_FIFO_ERROR_E5_SHIFT                                               12
+  #define TSEM_REG_INT_STS_2_ARB_RBC_FIFO_ERROR_A_E5                                                         (0x1<<13) // Pre-fetch FIFO error of Storm A.
+  #define TSEM_REG_INT_STS_2_ARB_RBC_FIFO_ERROR_A_E5_SHIFT                                                   13
+  #define TSEM_REG_INT_STS_2_ARB_RBC_FIFO_ERROR_B_E5                                                         (0x1<<14) // Pre-fetch FIFO error of Storm B.
+  #define TSEM_REG_INT_STS_2_ARB_RBC_FIFO_ERROR_B_E5_SHIFT                                                   14
+  #define TSEM_REG_INT_STS_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5                                                 (0x1<<15) // Lock is acquired more than maximum configured time.
+  #define TSEM_REG_INT_STS_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5_SHIFT                                           15
+  #define TSEM_REG_INT_STS_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                                  (0x1<<16) // Ilegal assetion commands towards lock block.
+  #define TSEM_REG_INT_STS_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5_SHIFT                                            16
+  #define TSEM_REG_INT_STS_2_LOCK_RBC_REQ_RELEASE_ERROR_E5                                                   (0x1<<17) // Error when trying to release a lock which is not acquired (key does not match any lock)
+  #define TSEM_REG_INT_STS_2_LOCK_RBC_REQ_RELEASE_ERROR_E5_SHIFT                                             17
+  #define TSEM_REG_INT_STS_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5                                                 (0x1<<18) // Trying to acquire a lock which is already acquired.
+  #define TSEM_REG_INT_STS_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5_SHIFT                                           18
+  #define TSEM_REG_INT_STS_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5                                                (0x1<<19) // Trying to relinquish a key which does not exist.
+  #define TSEM_REG_INT_STS_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5_SHIFT                                          19
+  #define TSEM_REG_INT_STS_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5                                                (0x1<<20) // A lock acquired requrest is issued when all locks are used.
+  #define TSEM_REG_INT_STS_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5_SHIFT                                          20
+  #define TSEM_REG_INT_STS_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5                                                (0x1<<21) // Error when both Storm are stalled due to lock block (may indicate a dead lock).
+  #define TSEM_REG_INT_STS_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5_SHIFT                                          21
+  #define TSEM_REG_INT_STS_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5                                            (0x1<<22) // Fin done with remainning allocated threads STORM_A.
+  #define TSEM_REG_INT_STS_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5_SHIFT                                      22
+  #define TSEM_REG_INT_STS_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5                                            (0x1<<23) // Fin done with remainning allocated threads STORM_B.
+  #define TSEM_REG_INT_STS_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5_SHIFT                                      23
+  #define TSEM_REG_INT_STS_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5                                            (0x1<<24) // Fin new thread request when no thread is allocated for handler of Storm A.
+  #define TSEM_REG_INT_STS_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5_SHIFT                                      24
+  #define TSEM_REG_INT_STS_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5                                            (0x1<<25) // Fin new thread request when no thread is allocated for handler of Storm B.
+  #define TSEM_REG_INT_STS_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5_SHIFT                                      25
+  #define TSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5                                      (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same range.
+  #define TSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5_SHIFT                                26
+  #define TSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5                                      (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same range.
+  #define TSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5_SHIFT                                27
+  #define TSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5                                         (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
+  #define TSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5_SHIFT                                   28
+  #define TSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5                                         (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
+  #define TSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5_SHIFT                                   29
+  #define TSEM_REG_INT_STS_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5                                          (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
+  #define TSEM_REG_INT_STS_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT                                    30
+#define TSEM_REG_INT_MASK_2_E5                                                                               0x1700064UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define TSEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5                                                (0x1<<0) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.RD_RBC_FAST_FIN_FIFO_ERROR_A .
+  #define TSEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5_SHIFT                                          0
+  #define TSEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5                                                (0x1<<1) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.RD_RBC_FAST_FIN_FIFO_ERROR_B .
+  #define TSEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT                                          1
+  #define TSEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5                                              (0x1<<2) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.SYNC_RBC_FAST_DBG_PUSH_ERROR_A .
+  #define TSEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5_SHIFT                                        2
+  #define TSEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5                                              (0x1<<3) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.SYNC_RBC_FAST_DBG_PUSH_ERROR_B .
+  #define TSEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT                                        3
+  #define TSEM_REG_INT_MASK_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5                                               (0x1<<4) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.CAM_RBC_FAST_MSB2_INP_ERROR_A .
+  #define TSEM_REG_INT_MASK_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5_SHIFT                                         4
+  #define TSEM_REG_INT_MASK_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5                                               (0x1<<5) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.CAM_RBC_FAST_MSB2_INP_ERROR_B .
+  #define TSEM_REG_INT_MASK_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5_SHIFT                                         5
+  #define TSEM_REG_INT_MASK_2_VFC_INTERRUPT_E5                                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.VFC_INTERRUPT .
+  #define TSEM_REG_INT_MASK_2_VFC_INTERRUPT_E5_SHIFT                                                         6
+  #define TSEM_REG_INT_MASK_2_MUX_RBC_VFC_FIFO_ERROR_E5                                                      (0x1<<7) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.MUX_RBC_VFC_FIFO_ERROR .
+  #define TSEM_REG_INT_MASK_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT                                                7
+  #define TSEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_A_E5                                                   (0x1<<8) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.FIN_RBC_INVLD_FOC_ERROR_A .
+  #define TSEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT                                             8
+  #define TSEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_B_E5                                                   (0x1<<9) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.FIN_RBC_INVLD_FOC_ERROR_B .
+  #define TSEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_B_E5_SHIFT                                             9
+  #define TSEM_REG_INT_MASK_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5                                                 (0x1<<10) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.FIN_RBC_INVLD_ALLOC_ERROR_A .
+  #define TSEM_REG_INT_MASK_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5_SHIFT                                           10
+  #define TSEM_REG_INT_MASK_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5                                                 (0x1<<11) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.FIN_RBC_INVLD_ALLOC_ERROR_B .
+  #define TSEM_REG_INT_MASK_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5_SHIFT                                           11
+  #define TSEM_REG_INT_MASK_2_CAM_RBC_INPUT_FIFO_ERROR_E5                                                    (0x1<<12) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.CAM_RBC_INPUT_FIFO_ERROR .
+  #define TSEM_REG_INT_MASK_2_CAM_RBC_INPUT_FIFO_ERROR_E5_SHIFT                                              12
+  #define TSEM_REG_INT_MASK_2_ARB_RBC_FIFO_ERROR_A_E5                                                        (0x1<<13) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.ARB_RBC_FIFO_ERROR_A .
+  #define TSEM_REG_INT_MASK_2_ARB_RBC_FIFO_ERROR_A_E5_SHIFT                                                  13
+  #define TSEM_REG_INT_MASK_2_ARB_RBC_FIFO_ERROR_B_E5                                                        (0x1<<14) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.ARB_RBC_FIFO_ERROR_B .
+  #define TSEM_REG_INT_MASK_2_ARB_RBC_FIFO_ERROR_B_E5_SHIFT                                                  14
+  #define TSEM_REG_INT_MASK_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5                                                (0x1<<15) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.LOCK_RBC_REQ_MAX_STALL_ERROR .
+  #define TSEM_REG_INT_MASK_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5_SHIFT                                          15
+  #define TSEM_REG_INT_MASK_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                                 (0x1<<16) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.LOCK_RBC_REQ_CMD_RATE_ERROR .
+  #define TSEM_REG_INT_MASK_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5_SHIFT                                           16
+  #define TSEM_REG_INT_MASK_2_LOCK_RBC_REQ_RELEASE_ERROR_E5                                                  (0x1<<17) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.LOCK_RBC_REQ_RELEASE_ERROR .
+  #define TSEM_REG_INT_MASK_2_LOCK_RBC_REQ_RELEASE_ERROR_E5_SHIFT                                            17
+  #define TSEM_REG_INT_MASK_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5                                                (0x1<<18) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.LOCK_RBC_REQ_REDUNDENT_ERROR .
+  #define TSEM_REG_INT_MASK_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5_SHIFT                                          18
+  #define TSEM_REG_INT_MASK_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5                                               (0x1<<19) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.LOCK_RBC_REQ_RELINQUISH_ERROR .
+  #define TSEM_REG_INT_MASK_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5_SHIFT                                         19
+  #define TSEM_REG_INT_MASK_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5                                               (0x1<<20) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.LOCK_RBC_REQ_STALL_FULL_ERROR .
+  #define TSEM_REG_INT_MASK_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5_SHIFT                                         20
+  #define TSEM_REG_INT_MASK_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5                                               (0x1<<21) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.LOCK_RBC_REQ_DUAL_STALL_ERROR .
+  #define TSEM_REG_INT_MASK_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5_SHIFT                                         21
+  #define TSEM_REG_INT_MASK_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5                                           (0x1<<22) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A .
+  #define TSEM_REG_INT_MASK_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5_SHIFT                                     22
+  #define TSEM_REG_INT_MASK_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5                                           (0x1<<23) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B .
+  #define TSEM_REG_INT_MASK_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5_SHIFT                                     23
+  #define TSEM_REG_INT_MASK_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5                                           (0x1<<24) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.DRA_INT_GRC_NON_FREE_THRD_ERROR_A .
+  #define TSEM_REG_INT_MASK_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5_SHIFT                                     24
+  #define TSEM_REG_INT_MASK_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5                                           (0x1<<25) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.DRA_INT_GRC_NON_FREE_THRD_ERROR_B .
+  #define TSEM_REG_INT_MASK_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5_SHIFT                                     25
+  #define TSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5                                     (0x1<<26) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A .
+  #define TSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5_SHIFT                               26
+  #define TSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5                                     (0x1<<27) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B .
+  #define TSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5_SHIFT                               27
+  #define TSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5                                        (0x1<<28) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A .
+  #define TSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5_SHIFT                                  28
+  #define TSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5                                        (0x1<<29) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B .
+  #define TSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5_SHIFT                                  29
+  #define TSEM_REG_INT_MASK_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5                                         (0x1<<30) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_2.SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR .
+  #define TSEM_REG_INT_MASK_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT                                   30
+#define TSEM_REG_INT_STS_WR_2_E5                                                                             0x1700068UL //Access:WR   DataWidth:0x1f   // Multi Field Register.
+  #define TSEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5                                              (0x1<<0) // Fast FIN FIFO error of Storm A.
+  #define TSEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5_SHIFT                                        0
+  #define TSEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5                                              (0x1<<1) // Fast FIN FIFO error of Storm B
+  #define TSEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT                                        1
+  #define TSEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5                                            (0x1<<2) // Fast Debug FIFO error of Storm A
+  #define TSEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5_SHIFT                                      2
+  #define TSEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5                                            (0x1<<3) // Fast Debug FIFO error of Storm B
+  #define TSEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT                                      3
+  #define TSEM_REG_INT_STS_WR_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5                                             (0x1<<4) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define TSEM_REG_INT_STS_WR_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5_SHIFT                                       4
+  #define TSEM_REG_INT_STS_WR_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5                                             (0x1<<5) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define TSEM_REG_INT_STS_WR_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5_SHIFT                                       5
+  #define TSEM_REG_INT_STS_WR_2_VFC_INTERRUPT_E5                                                             (0x1<<6) // interrupt from VFC block
+  #define TSEM_REG_INT_STS_WR_2_VFC_INTERRUPT_E5_SHIFT                                                       6
+  #define TSEM_REG_INT_STS_WR_2_MUX_RBC_VFC_FIFO_ERROR_E5                                                    (0x1<<7) // VFC FIFO error
+  #define TSEM_REG_INT_STS_WR_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT                                              7
+  #define TSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5                                                 (0x1<<8) // Error in FOC error of Storm A.
+  #define TSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT                                           8
+  #define TSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_B_E5                                                 (0x1<<9) // Error in FOC error of Storm B.
+  #define TSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_B_E5_SHIFT                                           9
+  #define TSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5                                               (0x1<<10) // Invalid allocated thread request with partial FIN of Storm A.
+  #define TSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5_SHIFT                                         10
+  #define TSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5                                               (0x1<<11) // Invalid allocated thread request with partial FIN of Storm B.
+  #define TSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5_SHIFT                                         11
+  #define TSEM_REG_INT_STS_WR_2_CAM_RBC_INPUT_FIFO_ERROR_E5                                                  (0x1<<12) // Cam input FIFO error
+  #define TSEM_REG_INT_STS_WR_2_CAM_RBC_INPUT_FIFO_ERROR_E5_SHIFT                                            12
+  #define TSEM_REG_INT_STS_WR_2_ARB_RBC_FIFO_ERROR_A_E5                                                      (0x1<<13) // Pre-fetch FIFO error of Storm A.
+  #define TSEM_REG_INT_STS_WR_2_ARB_RBC_FIFO_ERROR_A_E5_SHIFT                                                13
+  #define TSEM_REG_INT_STS_WR_2_ARB_RBC_FIFO_ERROR_B_E5                                                      (0x1<<14) // Pre-fetch FIFO error of Storm B.
+  #define TSEM_REG_INT_STS_WR_2_ARB_RBC_FIFO_ERROR_B_E5_SHIFT                                                14
+  #define TSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5                                              (0x1<<15) // Lock is acquired more than maximum configured time.
+  #define TSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5_SHIFT                                        15
+  #define TSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                               (0x1<<16) // Ilegal assetion commands towards lock block.
+  #define TSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5_SHIFT                                         16
+  #define TSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_RELEASE_ERROR_E5                                                (0x1<<17) // Error when trying to release a lock which is not acquired (key does not match any lock)
+  #define TSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_RELEASE_ERROR_E5_SHIFT                                          17
+  #define TSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5                                              (0x1<<18) // Trying to acquire a lock which is already acquired.
+  #define TSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5_SHIFT                                        18
+  #define TSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5                                             (0x1<<19) // Trying to relinquish a key which does not exist.
+  #define TSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5_SHIFT                                       19
+  #define TSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5                                             (0x1<<20) // A lock acquired requrest is issued when all locks are used.
+  #define TSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5_SHIFT                                       20
+  #define TSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5                                             (0x1<<21) // Error when both Storm are stalled due to lock block (may indicate a dead lock).
+  #define TSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5_SHIFT                                       21
+  #define TSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5                                         (0x1<<22) // Fin done with remainning allocated threads STORM_A.
+  #define TSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5_SHIFT                                   22
+  #define TSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5                                         (0x1<<23) // Fin done with remainning allocated threads STORM_B.
+  #define TSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5_SHIFT                                   23
+  #define TSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5                                         (0x1<<24) // Fin new thread request when no thread is allocated for handler of Storm A.
+  #define TSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5_SHIFT                                   24
+  #define TSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5                                         (0x1<<25) // Fin new thread request when no thread is allocated for handler of Storm B.
+  #define TSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5_SHIFT                                   25
+  #define TSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5                                   (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same range.
+  #define TSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5_SHIFT                             26
+  #define TSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5                                   (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same range.
+  #define TSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5_SHIFT                             27
+  #define TSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5                                      (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
+  #define TSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5_SHIFT                                28
+  #define TSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5                                      (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
+  #define TSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5_SHIFT                                29
+  #define TSEM_REG_INT_STS_WR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5                                       (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
+  #define TSEM_REG_INT_STS_WR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT                                 30
+#define TSEM_REG_INT_STS_CLR_2_E5                                                                            0x170006cUL //Access:RC   DataWidth:0x1f   // Multi Field Register.
+  #define TSEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5                                             (0x1<<0) // Fast FIN FIFO error of Storm A.
+  #define TSEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5_SHIFT                                       0
+  #define TSEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5                                             (0x1<<1) // Fast FIN FIFO error of Storm B
+  #define TSEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT                                       1
+  #define TSEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5                                           (0x1<<2) // Fast Debug FIFO error of Storm A
+  #define TSEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5_SHIFT                                     2
+  #define TSEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5                                           (0x1<<3) // Fast Debug FIFO error of Storm B
+  #define TSEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT                                     3
+  #define TSEM_REG_INT_STS_CLR_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5                                            (0x1<<4) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define TSEM_REG_INT_STS_CLR_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5_SHIFT                                      4
+  #define TSEM_REG_INT_STS_CLR_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5                                            (0x1<<5) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define TSEM_REG_INT_STS_CLR_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5_SHIFT                                      5
+  #define TSEM_REG_INT_STS_CLR_2_VFC_INTERRUPT_E5                                                            (0x1<<6) // interrupt from VFC block
+  #define TSEM_REG_INT_STS_CLR_2_VFC_INTERRUPT_E5_SHIFT                                                      6
+  #define TSEM_REG_INT_STS_CLR_2_MUX_RBC_VFC_FIFO_ERROR_E5                                                   (0x1<<7) // VFC FIFO error
+  #define TSEM_REG_INT_STS_CLR_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT                                             7
+  #define TSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5                                                (0x1<<8) // Error in FOC error of Storm A.
+  #define TSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT                                          8
+  #define TSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_B_E5                                                (0x1<<9) // Error in FOC error of Storm B.
+  #define TSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_B_E5_SHIFT                                          9
+  #define TSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5                                              (0x1<<10) // Invalid allocated thread request with partial FIN of Storm A.
+  #define TSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5_SHIFT                                        10
+  #define TSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5                                              (0x1<<11) // Invalid allocated thread request with partial FIN of Storm B.
+  #define TSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5_SHIFT                                        11
+  #define TSEM_REG_INT_STS_CLR_2_CAM_RBC_INPUT_FIFO_ERROR_E5                                                 (0x1<<12) // Cam input FIFO error
+  #define TSEM_REG_INT_STS_CLR_2_CAM_RBC_INPUT_FIFO_ERROR_E5_SHIFT                                           12
+  #define TSEM_REG_INT_STS_CLR_2_ARB_RBC_FIFO_ERROR_A_E5                                                     (0x1<<13) // Pre-fetch FIFO error of Storm A.
+  #define TSEM_REG_INT_STS_CLR_2_ARB_RBC_FIFO_ERROR_A_E5_SHIFT                                               13
+  #define TSEM_REG_INT_STS_CLR_2_ARB_RBC_FIFO_ERROR_B_E5                                                     (0x1<<14) // Pre-fetch FIFO error of Storm B.
+  #define TSEM_REG_INT_STS_CLR_2_ARB_RBC_FIFO_ERROR_B_E5_SHIFT                                               14
+  #define TSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5                                             (0x1<<15) // Lock is acquired more than maximum configured time.
+  #define TSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5_SHIFT                                       15
+  #define TSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                              (0x1<<16) // Ilegal assetion commands towards lock block.
+  #define TSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5_SHIFT                                        16
+  #define TSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_RELEASE_ERROR_E5                                               (0x1<<17) // Error when trying to release a lock which is not acquired (key does not match any lock)
+  #define TSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_RELEASE_ERROR_E5_SHIFT                                         17
+  #define TSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5                                             (0x1<<18) // Trying to acquire a lock which is already acquired.
+  #define TSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5_SHIFT                                       18
+  #define TSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5                                            (0x1<<19) // Trying to relinquish a key which does not exist.
+  #define TSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5_SHIFT                                      19
+  #define TSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5                                            (0x1<<20) // A lock acquired requrest is issued when all locks are used.
+  #define TSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5_SHIFT                                      20
+  #define TSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5                                            (0x1<<21) // Error when both Storm are stalled due to lock block (may indicate a dead lock).
+  #define TSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5_SHIFT                                      21
+  #define TSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5                                        (0x1<<22) // Fin done with remainning allocated threads STORM_A.
+  #define TSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5_SHIFT                                  22
+  #define TSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5                                        (0x1<<23) // Fin done with remainning allocated threads STORM_B.
+  #define TSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5_SHIFT                                  23
+  #define TSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5                                        (0x1<<24) // Fin new thread request when no thread is allocated for handler of Storm A.
+  #define TSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5_SHIFT                                  24
+  #define TSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5                                        (0x1<<25) // Fin new thread request when no thread is allocated for handler of Storm B.
+  #define TSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5_SHIFT                                  25
+  #define TSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5                                  (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same range.
+  #define TSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5_SHIFT                            26
+  #define TSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5                                  (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same range.
+  #define TSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5_SHIFT                            27
+  #define TSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5                                     (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
+  #define TSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5_SHIFT                               28
+  #define TSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5                                     (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
+  #define TSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5_SHIFT                               29
+  #define TSEM_REG_INT_STS_CLR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5                                      (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
+  #define TSEM_REG_INT_STS_CLR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT                                30
+#define TSEM_REG_PRTY_MASK                                                                                   0x17000ccUL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define TSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR                                                            (0x1<<0) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS.VFC_RBC_PARITY_ERROR .
+  #define TSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR_SHIFT                                                      0
+  #define TSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR                                                           (0x1<<1) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS.STORM_RF_PARITY_ERROR .
+  #define TSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR_SHIFT                                                     1
+  #define TSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR                                                            (0x1<<2) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS.REG_GEN_PARITY_ERROR .
+  #define TSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR_SHIFT                                                      2
+#define TSEM_REG_PRTY_MASK_H_0_BB_K2                                                                         0x1700204UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define TSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_BB_K2                                                 (0x1<<0) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
+  #define TSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_BB_K2_SHIFT                                           0
+  #define TSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_K2                                                 (0x1<<1) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
+  #define TSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_K2_SHIFT                                           1
+  #define TSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                     (0x1<<2) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define TSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                               2
+  #define TSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                     (0x1<<3) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define TSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                               3
+  #define TSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                     (0x1<<4) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define TSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                               4
+  #define TSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                     (0x1<<5) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define TSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                               5
+#define TSEM_REG_MEM_ECC_ENABLE_0_BB_K2                                                                      0x1700210UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define TSEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN_BB_K2                                                  (0x1<<0) // Enable ECC for memory ecc instance tsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_0 in module sem_slow_pas_buf_ram
+  #define TSEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN_BB_K2_SHIFT                                            0
+  #define TSEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_BB_K2                                                  (0x1<<1) // Enable ECC for memory ecc instance tsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_1 in module sem_slow_pas_buf_ram
+  #define TSEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_BB_K2_SHIFT                                            1
+#define TSEM_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                 0x1700214UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define TSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY_BB_K2                                           (0x1<<0) // Set parity only for memory ecc instance tsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_0 in module sem_slow_pas_buf_ram
+  #define TSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY_BB_K2_SHIFT                                     0
+  #define TSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_BB_K2                                           (0x1<<1) // Set parity only for memory ecc instance tsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_1 in module sem_slow_pas_buf_ram
+  #define TSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_BB_K2_SHIFT                                     1
+#define TSEM_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                             0x1700218UL //Access:RC   DataWidth:0x2    // Multi Field Register.
+  #define TSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT_BB_K2                                    (0x1<<0) // Record if a correctable error occurred on memory ecc instance tsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_0 in module sem_slow_pas_buf_ram
+  #define TSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT_BB_K2_SHIFT                              0
+  #define TSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_BB_K2                                    (0x1<<1) // Record if a correctable error occurred on memory ecc instance tsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_1 in module sem_slow_pas_buf_ram
+  #define TSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_BB_K2_SHIFT                              1
+#define TSEM_REG_MEM_ECC_EVENTS_BB_K2                                                                        0x170021cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define TSEM_REG_ARB_CYCLE_SIZE_BB_K2                                                                        0x1700400UL //Access:RW   DataWidth:0x5    // The number of time_slots in the arbitration cycle.
+#define TSEM_REG_VF_ERROR                                                                                    0x1700408UL //Access:WR   DataWidth:0x1    // This VF-split register provides read/clear access to the VF error received from the SDM for a DMA transfer. Reading this register will return the VF Error for value for the corresponding VF. Writing a 1 to this register will clear the error for the corresponding VF.
+#define TSEM_REG_PF_ERROR                                                                                    0x170040cUL //Access:WR   DataWidth:0x1    // This PF-split register provides read/clear access to the PF error received from the SDM for a DMA transfer. Reading this register will return the PF Error for value for the corresponding PF. Writing a 1 to this register will clear the error for the corresponding PF.
+#define TSEM_REG_VF_ERR_VECTOR                                                                               0x1700420UL //Access:WB_R DataWidth:0xf0   // This read-only register provides a vector of bits having an error indication per VF where the Bit position corresponds to the VFID.
+#define TSEM_REG_VF_ERR_VECTOR_SIZE_BB                                                                       4
+#define TSEM_REG_VF_ERR_VECTOR_SIZE_K2_E5                                                                    8
+#define TSEM_REG_PF_ERR_VECTOR                                                                               0x1700440UL //Access:R    DataWidth:0x10   // This read-only register provides a vector of bits having an error indication per PF where the Bit position corresponds to the PFID.
+#define TSEM_REG_CLEAR_STALL                                                                                 0x1700444UL //Access:RW   DataWidth:0x1    // Clear stall signal sent from local storm to external storms.
+#define TSEM_REG_EXCEPTION_INT                                                                               0x1700448UL //Access:RW   DataWidth:0x10   // Provides a default PRAM address to be used for the handler in the event that the PRAM address retrieved from the interrupt table is out of range with regard to the actual PRAM size provided in the SEMI instance.
+#define TSEM_REG_EXT_STORE_FREE_ENTRIES_BB_K2                                                                0x170044cUL //Access:R    DataWidth:0x6    // Number of free entries in the external STORE sync FIFO.
+#define TSEM_REG_GPI_DATA_A_E5                                                                               0x1700450UL //Access:R    DataWidth:0x20   // Used to read the GPI input signals of Storm A.
+#define TSEM_REG_GPI_DATA_BB_K2                                                                              0x1700450UL //Access:R    DataWidth:0x20   // Used to read the GPI input signals.
+#define TSEM_REG_GPRE_SAMP_PERIOD_BB_K2                                                                      0x1700454UL //Access:RW   DataWidth:0x4    // Defines the number of system clocks from one sample of GPRE sync data and the next.
+#define TSEM_REG_ALLOW_LP_SLEEP_THRD                                                                         0x1700458UL //Access:RW   DataWidth:0x1    // When set, this bit is used to allow low-power mode to be activated while threads are sleeping in the passive buffer, as long as the SEMI/Storm remains idle.
+#define TSEM_REG_ECO_RESERVED                                                                                0x170045cUL //Access:RW   DataWidth:0x20   // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
+#define TSEM_REG_PB_WR_SDM_DMA_MODE_E5                                                                       0x1700460UL //Access:RW   DataWidth:0x2    // This register can set the mode of the SDM DMA write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use regardless write mode. 11 - Disable write mode.
+#define TSEM_REG_PB_WR_DRA_RD_CUT_THROUGH_MODE_E5                                                            0x1700464UL //Access:RW   DataWidth:0x1    // This register set the DRA RD block cut through mode in which write to a thread address section passive buffer may occur simultaneously with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut through mode active.
+#define TSEM_REG_GPI_DATA_B_E5                                                                               0x1700468UL //Access:R    DataWidth:0x20   // Used to read the GPI input signals of Storm B.
+#define TSEM_REG_FIC_FIFO_BB_K2                                                                              0x1700580UL //Access:WB_R DataWidth:0x80   // Used for debugging to read/write to/from the FIC FIFOs. The address selects which FIFO should be accessed.
+#define TSEM_REG_FIC_FIFO_SIZE                                                                               4
+#define TSEM_REG_FIC_MIN_MSG_BB_K2                                                                           0x1700600UL //Access:RW   DataWidth:0x6    // Per-FIC interface register array defines minimum number of cycles in the FIC interfaces after which the message can be sent to the passive register_file.
+#define TSEM_REG_FIC_EMPTY_CT_MODE_BB_K2                                                                     0x1700620UL //Access:RW   DataWidth:0x1    // When set, enables the "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require that the available ("go") counter is non-zero before making a transfer request to the DRA arbiter and starting a transfer.
+#define TSEM_REG_FIC_EMPTY_CT_CNT_BB_K2                                                                      0x1700624UL //Access:RC   DataWidth:0x18   // Statistics counter used to count the number of FIC messages that have been received on any FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
+#define TSEM_REG_FOC_CREDIT                                                                                  0x1700680UL //Access:RW   DataWidth:0x8    // Array of registers provides the initial credits on each of the associatef FOC interfaces. Reading from this register provides the current FOR credit value.
+#define TSEM_REG_FOC_CREDIT_SIZE                                                                             2
+#define TSEM_REG_FULL_FOC_DRA_STRT_EN_BB_K2                                                                  0x17006c0UL //Access:RW   DataWidth:0x1    // When set, this bit allows the DRA read operation to start even when there are not enough credits on all the participating FOC interfaces to complete the entire transaction. The transfer will stall only when a transfer cycle is reached in which there are no interface credits, at which time the DRA transfer will remain stalled until the FOC destination(s) has at least a single credit. When this configuration is cleared, the DRA read transfer will not begin until there are enough credits on all the participating FOC interfaces for the entire transfer.
+#define TSEM_REG_FIN_COMMAND_BB_K2                                                                           0x1700700UL //Access:WB_R DataWidth:0x164  // Last fin command that was read from fifo. Its spelling in FIN_FIFO register.
+#define TSEM_REG_FIN_COMMAND_SIZE                                                                            16
+#define TSEM_REG_FIN_FIFO_BB_K2                                                                              0x1700800UL //Access:WB_R DataWidth:0x164  // READ ONLY FOR DEBUGGING! [5:0]   start_rp_foc3; [11:6] start_rp_foc2;  [17:12]   start_rp_foc1; [23:18] start_rp_foc0;  [29:24]   end_rp_foc3; [35:30] end_rp_foc2; [41:36]   end_rp_foc1; [47:42]   end_rp_foc0; [53:48]   lowest rp; [59:54]   highest rp; [65:60]   store start rp; [71:66]   store end rp; [77:72]   load start rp; [83:78]   load end rp; [85:84]   priority; [101:86]  pram address; [102] pas; [103] foc3; [104] foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:0] is valid.
+#define TSEM_REG_FIN_FIFO_SIZE                                                                               16
+#define TSEM_REG_INVLD_PAS_WR_EN_BB_K2                                                                       0x1700900UL //Access:RW   DataWidth:0x1    // When set, an attempt to write to the passive buffer over the external passive interface will be enabled even if the partition being written is owned by a thread whose valid bit is not set. Otherwise if cleared, the transfer will be stalled.
+#define TSEM_REG_ARBITER_REQUEST_BB_K2                                                                       0x1700980UL //Access:R    DataWidth:0x5    // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2.
+#define TSEM_REG_ARBITER_SELECT_BB_K2                                                                        0x1700984UL //Access:R    DataWidth:0x5    // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2.
+#define TSEM_REG_ARBITER_SLOT_BB_K2                                                                          0x1700988UL //Access:R    DataWidth:0x5    // Dra arbiter last slot.
+#define TSEM_REG_ARB_AS_DEF_BB_K2                                                                            0x1700a00UL //Access:RW   DataWidth:0x3    // Two-dimensional register array is used to define each of four arbitration schemes used by the main DRA arbiter. For this, bits 4:3 of the offset are used to select the arbitration scheme 0-3. Bits 2:0 of the offset are used to define the five priority sources for the selected scheme, where for each priority (0-4), an arbiter source is assigned. Valid values for these configurations are the source enumerations, where FIC0=0x0, FIC1=0x1, wake priority0=0x2, wake priority1=0x3 and wake priority2=0x4. Note that there are holes in the indirect offset address which always return zero when read. These exist at offsets 0x5-0x7, 0xd-0xf, 0x15-0x17 and 0x1d-0x1f.
+#define TSEM_REG_ARB_AS_DEF_SIZE                                                                             32
+#define TSEM_REG_ARB_TS_AS_BB_K2                                                                             0x1700a80UL //Access:RW   DataWidth:0x2    // Register array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
+#define TSEM_REG_ARB_TS_AS_SIZE                                                                              20
+#define TSEM_REG_NUM_OF_THREADS                                                                              0x1700b00UL //Access:R    DataWidth:0x8    // The number of currently free threads (in invalid state).
+#define TSEM_REG_THREAD_ERROR_LOW_E5                                                                         0x1700b04UL //Access:R    DataWidth:0x20   // Thread error low indication. Represents threads 31 -0
+#define TSEM_REG_THREAD_ERROR_BB_K2                                                                          0x1700b04UL //Access:R    DataWidth:0x18   // Thread error indication.
+#define TSEM_REG_THREAD_RDY_BB_K2                                                                            0x1700b08UL //Access:R    DataWidth:0x18   // Thread ready indication.
+#define TSEM_REG_THREAD_SET_NUM                                                                              0x1700b0cUL //Access:W    DataWidth:0x6    // Thread ID. Write thread ID will set ready indication for this thread ID.
+#define TSEM_REG_THREAD_VALID_BB_K2                                                                          0x1700b10UL //Access:R    DataWidth:0x18   // Valid sleeping threads.
+#define TSEM_REG_THREADS_LIST_BB_K2                                                                          0x1700b14UL //Access:RW   DataWidth:0x18   // List of free threads.
+#define TSEM_REG_THREAD_NUMBER_E5                                                                            0x1700b18UL //Access:RW   DataWidth:0x8    // Defines the maixmum number of supported threads in SEMI.
+#define TSEM_REG_THREAD_ERROR_HIGH_E5                                                                        0x1700b1cUL //Access:R    DataWidth:0x18   // Thread error high indication. Represents threads  55-32
+#define TSEM_REG_FOC_MIN_MESSAGE_CREDIT_E5                                                                   0x1700b40UL //Access:RW   DataWidth:0x8    // This field defines for each FOC the minimum message reuired for the FOC transfer to start.
+#define TSEM_REG_FOC_MIN_MESSAGE_CREDIT_SIZE                                                                 2
+#define TSEM_REG_ORDER_HEAD_BB_K2                                                                            0x1700c00UL //Access:RW   DataWidth:0x5    // This (indirect) register array of registers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
+#define TSEM_REG_ORDER_HEAD_SIZE                                                                             24
+#define TSEM_REG_ORDER_TAIL_BB_K2                                                                            0x1700c80UL //Access:RW   DataWidth:0x5    // This (indirect) register array of registers provides read/write access to the tail pointers assigned to each of the thread ordering queues.
+#define TSEM_REG_ORDER_TAIL_SIZE                                                                             24
+#define TSEM_REG_ORDER_EMPTY_BB_K2                                                                           0x1700d00UL //Access:RW   DataWidth:0x1    // This vector provides read-only access to the empty bit assigned to each of the thread ordering queues.
+#define TSEM_REG_ORDER_EMPTY_SIZE                                                                            24
+#define TSEM_REG_ORDER_LL_REG_BB_K2                                                                          0x1700d80UL //Access:RW   DataWidth:0x5    // This array of registers provides read/write access to each entry of the linked-list array of the thread-ordering queue. Because the actual depth is based on the number of threads supported by the design, which is a Verilog parameter, a 64-entry window is reserved in the register address space. The valid entries start at the base of the window and extend through the number of threads supported. The value in each indirect register contains linked-list pointer to the next thread in the associated queue..
+#define TSEM_REG_ORDER_LL_REG_SIZE                                                                           24
+#define TSEM_REG_ORDER_POP_EN_BB_K2                                                                          0x1700e00UL //Access:RW   DataWidth:0x18   // Provides access to the thread ordering queue pop-enable vector.
+#define TSEM_REG_ORDER_WAKE_EN_BB_K2                                                                         0x1700e08UL //Access:RW   DataWidth:0x18   // Provides access to the thread ordering queue wake-enable vector.
+#define TSEM_REG_PF_NUM_ORDER_BASE_BB_K2                                                                     0x1700e10UL //Access:RW   DataWidth:0x5    // This field defines the base value for the ordering queue selection when the PFNum is chosen to control this selection. The value of this register is added to PFNum and the result is used to select one of 16 ordering queues.
+#define TSEM_REG_DBG_ALM_FULL                                                                                0x1701000UL //Access:RW   DataWidth:0x6    // Almost full for slow debug fifo.
+#define TSEM_REG_PASSIVE_ALM_FULL                                                                            0x1701004UL //Access:RW   DataWidth:0x5    // The number of free entries in the sync FIFO between the external HW and the passive buffer; below which the PassiveFull is asserted.
+#define TSEM_REG_SYNC_DRA_WR_ALM_FULL_BB_K2                                                                  0x1701008UL //Access:RW   DataWidth:0x5    // Almost full for sync dra_wr fifo (data from DRA to STORM).
+#define TSEM_REG_SYNC_RAM_WR_ALM_FULL                                                                        0x170100cUL //Access:RW   DataWidth:0x6    // Almost full for sync ram_wr fifo.
+#define TSEM_REG_SYNC_FOC_FIFO_WR_ALM_FULL_E5                                                                0x1701010UL //Access:RW   DataWidth:0x4    // Almost full for indication for FOC Sync FIFO.
+#define TSEM_REG_SYNC_SDM_READY_FIFO_WR_ALM_FULL_E5                                                          0x1701014UL //Access:RW   DataWidth:0x3    // Almost full for indication for SDM READY FIFO.
+#define TSEM_REG_SYNC_SDM_INC_FIFO_WR_ALM_FULL_E5                                                            0x1701018UL //Access:RW   DataWidth:0x3    // Almost full for indication for SDM Counter Increment FIFO.
+#define TSEM_REG_STALL_ON_INT_E5                                                                             0x170101cUL //Access:RW   DataWidth:0x2    // 00 - No stall. 01 - Both cluster Stroms will be stalled on any unmasked error occurrence. 10 - All Stroms will be stalled on any unmasked error occurrence.
+#define TSEM_REG_FIC0_A_MAX_THRDS_E5                                                                         0x1701020UL //Access:RW   DataWidth:0x6    // Defines the maximum supported threads that may be contained in FIC0 A queue. If FIC0 message  is received and number of threads equals to the configured value, FIC interface will be stalled untill number of queue threads drops below configured vlaue.
+#define TSEM_REG_FIC0_X_MAX_THRDS_E5                                                                         0x1701024UL //Access:RW   DataWidth:0x6    // Defines the maximum supported threads that may be contained in FIC0 X queue. If FIC0 message  is received and number of threads equals to the configured value, FIC interface will be stalled untill number of queue threads drops below configured vlaue.
+#define TSEM_REG_FIC0_B_MAX_THRDS_E5                                                                         0x1701028UL //Access:RW   DataWidth:0x6    // Defines the maximum supported threads that may be contained in FIC0 B queue. If FIC0 message  is received and number of threads equals to the configured value, FIC interface will be stalled untill number of queue threads drops below configured vlaue.
+#define TSEM_REG_FIC1_A_MAX_THRDS_E5                                                                         0x170102cUL //Access:RW   DataWidth:0x6    // Defines the maximum supported threads that may be contained in FIC1 A queue. If FIC1 message is received and number of threads equals to the configured value, FIC interface will be stalled untill number of queue threads drops below configured vlaue.
+#define TSEM_REG_DRA_EMPTY_BB_K2                                                                             0x1701100UL //Access:R    DataWidth:0x1    // Dra_empty.
+#define TSEM_REG_EXT_PAS_EMPTY                                                                               0x1701104UL //Access:R    DataWidth:0x1    // EXT_PAS FIFO empty in sem_slow.
+#define TSEM_REG_FIC_EMPTY                                                                                   0x1701120UL //Access:R    DataWidth:0x1    // Array of registers reflects associated FIC FIFO empty in sem_slow_fic.
+#define TSEM_REG_SLOW_DBG_EMPTY_BB_K2                                                                        0x1701140UL //Access:R    DataWidth:0x1    // DBG FIFO is empty in sem_slow_ls_dbg.
+#define TSEM_REG_SLOW_DRA_FIN_EMPTY_BB_K2                                                                    0x1701144UL //Access:R    DataWidth:0x1    // FIN fifo is empty in sem_slow_dra_sync.
+#define TSEM_REG_SLOW_DRA_RD_EMPTY_BB_K2                                                                     0x1701148UL //Access:R    DataWidth:0x1    // DRA_RD pop fifo is empty in sem_slow_dra_sync.
+#define TSEM_REG_SLOW_DRA_WR_EMPTY_BB_K2                                                                     0x170114cUL //Access:R    DataWidth:0x1    // DRA_WR push fifo is empty in sem_slow_dra_sync.
+#define TSEM_REG_SLOW_EXT_STORE_EMPTY                                                                        0x1701150UL //Access:R    DataWidth:0x1    // EXT_STORE FIFO is empty in sem_slow_ls_ext.
+#define TSEM_REG_SLOW_EXT_LOAD_EMPTY                                                                         0x1701154UL //Access:R    DataWidth:0x2    // EXT_LOAD FIFO is empty in sem_slow_ls_ext, bit 0 FIFO of Core A, bit 1 FIFO of Core B.
+#define TSEM_REG_SLOW_RAM_RD_EMPTY                                                                           0x1701158UL //Access:R    DataWidth:0x1    // EXT_RD_RAM FIFO is empty in sem_slow_ls_ext.
+#define TSEM_REG_SLOW_RAM_WR_EMPTY                                                                           0x170115cUL //Access:R    DataWidth:0x1    // EXT_WR_RAM FIFO is empty in sem_slow_ls_ext.
+#define TSEM_REG_SYNC_DBG_EMPTY                                                                              0x1701160UL //Access:R    DataWidth:0x2    // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR debug FIFO of Core B
+#define TSEM_REG_THREAD_FIFO_EMPTY_BB_K2                                                                     0x1701164UL //Access:R    DataWidth:0x1    // Indicates that the thread fifo is empty in sem_slow_dra_wr.
+#define TSEM_REG_ORD_ID_FIFO_EMPTY_BB_K2                                                                     0x1701168UL //Access:R    DataWidth:0x1    // Indicates that the order ID fifo is empty in sem_slow_dra_wr.
+#define TSEM_REG_PB_QUEUE_EMPTY_E5                                                                           0x170116cUL //Access:R    DataWidth:0xb    // If 1, the correspongding Queue is empty. Queues numeration: FOC_FIFO_IF - 0,  FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - 5,  WAKE_FIFO_PRIO_X - 6, WAKE_FIFO_PRI1_X - 7,FIC0_FIFO_B - 8, WAKE_FIFO_PRIO_B - 9,  WAKE_FIFO_PRI1_B - 10.
+#define TSEM_REG_SYNC_FOC_FIFO_EMPTY_E5                                                                      0x1701170UL //Access:R    DataWidth:0x1    // FOC FIFO empty indication.
+#define TSEM_REG_SYNC_FOC_PRE_FETCH_FIFO_EMPTY_E5                                                            0x1701174UL //Access:R    DataWidth:0x1    // FOC pre fetch FIFO empty indication.
+#define TSEM_REG_EXT_PAS_FULL                                                                                0x1701200UL //Access:R    DataWidth:0x1    // EXT_PAS FIFO Full in sem_slow.
+#define TSEM_REG_EXT_STORE_IF_FULL                                                                           0x1701204UL //Access:R    DataWidth:0x1    // EXT_STORE IF is full in sem_slow_ls_ext.
+#define TSEM_REG_FIC_FULL                                                                                    0x1701220UL //Access:R    DataWidth:0x1    // Array of registers reflects associated FIC FIFO full in sem_slow_fic.
+#define TSEM_REG_PAS_IF_FULL_BB_K2                                                                           0x1701240UL //Access:R    DataWidth:0x1    // Full from passive buffer asserted toward SDM.
+#define TSEM_REG_RAM_IF_FULL                                                                                 0x1701244UL //Access:R    DataWidth:0x1    // EXT_RAM IF is full in sem_slow_ls_ram.
+#define TSEM_REG_SLOW_DBG_ALM_FULL_BB_K2                                                                     0x1701248UL //Access:R    DataWidth:0x1    // DBG FIFO is almost full in sem_slow_ls_dbg according to the full threshold configuration.
+#define TSEM_REG_SLOW_DBG_FULL_BB_K2                                                                         0x170124cUL //Access:R    DataWidth:0x1    // DBG FIFO is full in sem_slow_ls_dbg.
+#define TSEM_REG_SLOW_DRA_FIN_FULL_BB_K2                                                                     0x1701250UL //Access:R    DataWidth:0x1    // FIN fifo is full in sem_slow_dra_sync (never may be active).
+#define TSEM_REG_SLOW_DRA_RD_FULL_BB_K2                                                                      0x1701254UL //Access:R    DataWidth:0x1    // DRA_RD pop fifo is full in sem_slow_dra_sync.
+#define TSEM_REG_SLOW_DRA_WR_FULL_BB_K2                                                                      0x1701258UL //Access:R    DataWidth:0x1    // DRA_WR push fifo is full in sem_slow_dra_sync.
+#define TSEM_REG_SLOW_EXT_STORE_FULL                                                                         0x170125cUL //Access:R    DataWidth:0x2    // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIFO.
+#define TSEM_REG_SLOW_EXT_LOAD_FULL                                                                          0x1701260UL //Access:R    DataWidth:0x2    // EXT_LOAD FIFO is full in sem_slow_ls_ext, bit 0 for Core A and bit 1 for Core B.
+#define TSEM_REG_SLOW_RAM_RD_FULL                                                                            0x1701264UL //Access:R    DataWidth:0x1    // EXT_RD_RAM FIFO is full in sem_slow_ls_ext.
+#define TSEM_REG_SLOW_RAM_WR_ALM_FULL                                                                        0x1701268UL //Access:R    DataWidth:0x1    // EXT_WR_RAM FIFO is almost full in sem_slow_ls_ext.
+#define TSEM_REG_SLOW_RAM_WR_FULL                                                                            0x170126cUL //Access:R    DataWidth:0x1    // EXT_WR_RAM FIFO is full in sem_slow_ls_ext.
+#define TSEM_REG_SYNC_DBG_FULL                                                                               0x1701270UL //Access:R    DataWidth:0x2    // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR debug FIFO of Core B.
+#define TSEM_REG_THREAD_FIFO_FULL_BB_K2                                                                      0x1701274UL //Access:R    DataWidth:0x1    // Indicates that the thread fifo is full in sem_slow_dra_wr.
+#define TSEM_REG_ORD_ID_FIFO_FULL_BB_K2                                                                      0x1701278UL //Access:R    DataWidth:0x1    // Indicates that the thread fifo is full in sem_slow_dra_wr.
+#define TSEM_REG_SYNC_READY_FIFO_FULL_E5                                                                     0x170127cUL //Access:R    DataWidth:0x1    // Ready sync FIFO full indication.
+#define TSEM_REG_SYNC_CNT_FIFO_FULL_E5                                                                       0x1701280UL //Access:R    DataWidth:0x1    // Counter increment sync FIFO full indication.
+#define TSEM_REG_SYNC_FOC_FIFO_FULL_E5                                                                       0x1701284UL //Access:R    DataWidth:0x1    // sync FOC FIFO full indication.
+#define TSEM_REG_THREAD_INTER_CNT_BB_K2                                                                      0x1701300UL //Access:RW   DataWidth:0x10   // Maximum value of threads interrupt counter; when it gets this value then interrupt to will be send if thread active from previous maximum value of this counter.
+#define TSEM_REG_THREAD_INTER_CNT_ENABLE_BB_K2                                                               0x1701304UL //Access:RW   DataWidth:0x1    // Enable for start count of thread_inter_cnt.
+#define TSEM_REG_THREAD_ORUN_NUM_BB_K2                                                                       0x1701308UL //Access:R    DataWidth:0x18   // Threads are sleeping in passive buffer more than thread_inter_cnt number of cycles.
+#define TSEM_REG_SLOW_DBG_ACTIVE_BB_K2                                                                       0x1701400UL //Access:RW   DataWidth:0x1    // Debug mode is active.
+#define TSEM_REG_SLOW_DBG_MODE_BB_K2                                                                         0x1701404UL //Access:RW   DataWidth:0x3    // Debug mode for slow debug bus.
+#define TSEM_REG_DBG_FRAME_MODE_BB_K2                                                                        0x1701408UL //Access:RW   DataWidth:0x2    // Debug frame mode control for the SEMI debug bus. The following values apply: "00" - indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mode-1, which means bits 127:64 belong to fast debug and bits 63:0 belong to slow debug. "10" - indicates mode-2, which means bits 127:96 belong to fast debug and bits 95:0 belong to slow debug. "11" - indicates mode-3, which means all four words are provided by the slow debug.
+#define TSEM_REG_DBG_EACH_CYLE_BB_K2                                                                         0x170140cUL //Access:RW   DataWidth:0x1    // 0=output every cycle; 1= output only when there is a change.
+#define TSEM_REG_DBG_GPRE_VECT_BB_K2                                                                         0x1701410UL //Access:RW   DataWidth:0x8    // This 8-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug channel when they are accessed for read by the Storm during mode-6 debug (handler trace). For this, bit-0 corresponds with GPRE[0-3] and bit-7 corresponds with GPRE[28-31].
+#define TSEM_REG_DBG_IF_FULL_BB_K2                                                                           0x1701414UL //Access:R    DataWidth:0x1    // DBG IF is full in sem_slow_ls_dbg.
+#define TSEM_REG_DBG_MODE0_CFG_BB_K2                                                                         0x1701418UL //Access:RW   DataWidth:0x1    // 0=all the message; 1=partial message.
+#define TSEM_REG_DBG_MODE0_CFG_CYCLE_BB_K2                                                                   0x170141cUL //Access:RW   DataWidth:0x5    // In case DebugMode0Config = 1; the additional cycles to extract to the debug bus.
+#define TSEM_REG_DBG_MODE1_CFG_BB_K2                                                                         0x1701420UL //Access:RW   DataWidth:0x1    // 0=without the data; 1=with the data.
+#define TSEM_REG_DBG_MSG_SRC_BB_K2                                                                           0x1701424UL //Access:RW   DataWidth:0x3    // This field is a mask used to enable (or filter) the various sources of DRA write debug packets. Setting a bit causes the corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1 and bit-2 corresponds with DRA writes from the passive buffer. This applicable only for debug mode=0.
+#define TSEM_REG_DBG_QUEUE_PEFORMANCE_MON_STAT_E5                                                            0x1701428UL //Access:RW   DataWidth:0x1    // If 0, the statistic report the maximum value between following reads (when using read clear). If 1, report the current value.
+#define TSEM_REG_PASSIVE_BUFFER_PERFORMANCE_MON_STAT_E5                                                      0x170142cUL //Access:RW   DataWidth:0x1    // Enable performance monitor statistics sent to SEM_PD.
+#define TSEM_REG_DBG_QUEUE_FIC_MON_CNT_E5                                                                    0x1701430UL //Access:RC   DataWidth:0x20   // Report the number of received FIC transaction between two of the following register reads. The counter is incremanted only for the event IDs which have Debug Monitor event indication set.
+#define TSEM_REG_DBG_QUEUE_FOC_MAX_VALUE_E5                                                                  0x1701434UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FOC queue.
+#define TSEM_REG_DBG_QUEUE_FIC0_A_MAX_VALUE_E5                                                               0x1701438UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 A queue.
+#define TSEM_REG_DBG_QUEUE_FIC1_A_MAX_VALUE_E5                                                               0x170143cUL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC1 A queue.
+#define TSEM_REG_DBG_QUEUE_PRIO0_A_MAX_VALUE_E5                                                              0x1701440UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 A queue.
+#define TSEM_REG_DBG_QUEUE_PRIO1_A_MAX_VALUE_E5                                                              0x1701444UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 A queue.
+#define TSEM_REG_DBG_QUEUE_FIC0_X_MAX_VALUE_E5                                                               0x1701448UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 X queue.
+#define TSEM_REG_DBG_QUEUE_PRIO0_X_MAX_VALUE_E5                                                              0x170144cUL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 X queue.
+#define TSEM_REG_DBG_QUEUE_PRIO1_X_MAX_VALUE_E5                                                              0x1701450UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 X queue.
+#define TSEM_REG_DBG_QUEUE_FIC0_B_MAX_VALUE_E5                                                               0x1701454UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 B queue.
+#define TSEM_REG_DBG_QUEUE_PRIO0_B_MAX_VALUE_E5                                                              0x1701458UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 B queue.
+#define TSEM_REG_DBG_QUEUE_PRIO1_B_MAX_VALUE_E5                                                              0x170145cUL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 B queue.
+#define TSEM_REG_DBG_QUEUE_MAX_THREAD_VALUE_E5                                                               0x1701460UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of allocated threads in the system.
+#define TSEM_REG_DBG_QUEUE_MAX_SLEEP_VALUE_E5                                                                0x1701464UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does not include the threads pending in the queues.
+#define TSEM_REG_DBG_OUT_DATA                                                                                0x1701500UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define TSEM_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define TSEM_REG_DBG_OUT_VALID                                                                               0x1701520UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define TSEM_REG_DBG_OUT_FRAME                                                                               0x1701524UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define TSEM_REG_DBG_SELECT                                                                                  0x1701528UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define TSEM_REG_DBG_DWORD_ENABLE                                                                            0x170152cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define TSEM_REG_DBG_SHIFT                                                                                   0x1701530UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define TSEM_REG_DBG_FORCE_VALID                                                                             0x1701534UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define TSEM_REG_DBG_FORCE_FRAME                                                                             0x1701538UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define TSEM_REG_EXT_PAS_FIFO_BB_K2                                                                          0x1708000UL //Access:WB_R DataWidth:0x4d   // Provides read-only access of the external passive FIFO. Intended for debug purposes.
+#define TSEM_REG_EXT_PAS_FIFO_SIZE                                                                           76
+#define TSEM_REG_INT_TABLE                                                                                   0x1710000UL //Access:RW   DataWidth:0x1e   // Interrupt table read/write access. This register is intended to be written only when the system is idle. The fields of the interrupt table are as follows. int_table[29] = Allocated per child;  int_table[28] = Increment type; int_table[27:23] = Counter select; int_table[22] = Counter insert; int_table[21:17] = GapSel; int_table[16] = Monitor enable; int_table[15:0] = PRAM Address;
+#define TSEM_REG_INT_TABLE_SIZE                                                                              256
+#define TSEM_REG_FIC_COUNTER_GROUP_E5                                                                        0x1711000UL //Access:RW   DataWidth:0x8    // This field enables a RD/WR access to the 24 counters of the "FIC Counters".
+#define TSEM_REG_FIC_COUNTER_GROUP_SIZE                                                                      24
+#define TSEM_REG_PB_THRD_STM_GROUP_E5                                                                        0x1712000UL //Access:R    DataWidth:0x17   // Read the State mahcine state of teh trheads. 0:4 - state. 5 - pending ready. 7:6 - Affinity type. 8 - Destination FOC. 9 - Destination Storm. 10 - counter increment ready. 15:11 - counter index. 16 - Debug monitor enable. 17 - Exlucsive. 22:18 - DRA size.
+#define TSEM_REG_PB_THRD_STM_GROUP_SIZE                                                                      56
+#define TSEM_REG_PASSIVE_BUFFER                                                                              0x1720000UL //Access:R    DataWidth:0x20   // Passive buffer memory read only.
+#define TSEM_REG_PASSIVE_BUFFER_SIZE_BB_K2                                                                   4320
+#define TSEM_REG_PASSIVE_BUFFER_SIZE_E5                                                                      12544
+#define TSEM_REG_FIC_GAP_VECT_BB_K2                                                                          0x1700500UL //Access:WB   DataWidth:0x2c   // This array of nine 44-bit vectors provides a bit per register-quad, used to define the register-quad locations that should be included in gaps (discontinuities) within the DRA transfer, where bit-0 corresponds with IORs 0-3, and so on. To indicate a gap, the corresponding bit should be cleared. These gaps have a granularity of a register- quad (four IORs). For each DRA write transfer from whom the FIC is the source, one of nine gap vectors (or a default-gap vector) will be selected, based on the GapSelect field of the corresponding interrupt table entry. Any unused upper bits of the vector will be ignored and thus, can be written with any value.
+#define TSEM_REG_FIC_GAP_VECT_E5                                                                             0x1730000UL //Access:WB   DataWidth:0x34   // This array of 24 x 52-bit vectors provides a bit per register-quad, used to define the register-quad locations that should be included in gaps (discontinuities) within the DRA transfer, where bit-0 corresponds with IORs 0-3, and so on. To indicate a gap, the corresponding bit should be cleared. These gaps have a granularity of a register- quad (four IORs). For each DRA write transfer from whom the FIC is the source, one of nine gap vectors (or a default-gap vector) will be selected, based on the GapSelect field of the corresponding interrupt table entry. Any unused upper bits of the vector will be ignored and thus, can be written with any value.
+#define TSEM_REG_FIC_GAP_VECT_SIZE_BB_K2                                                                     18
+#define TSEM_REG_FIC_GAP_VECT_SIZE_E5                                                                        48
+#define TSEM_REG_FAST_MEMORY                                                                                 0x1740000UL //Access:RW   DataWidth:0x20   // See sem_fast.xls for its description.
+#define TSEM_REG_FAST_MEMORY_SIZE                                                                            65536
+#define TSEM_REG_PRAM                                                                                        0x1780000UL //Access:WB   DataWidth:0x30   // Pram memory.
+#define TSEM_REG_PRAM_SIZE_BB_K2                                                                             73728
+#define TSEM_REG_PRAM_SIZE_E5                                                                                92160
+#define MSEM_REG_ENABLE_IN_BB_K2                                                                             0x1800004UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define MSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN_BB_K2                                                        (0x1<<0) // Full input from external IF to LS input enable.
+  #define MSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN_BB_K2_SHIFT                                                  0
+  #define MSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN_BB_K2                                                     (0x1<<1) // Read data from external LS IF input enable.
+  #define MSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN_BB_K2_SHIFT                                               1
+  #define MSEM_REG_ENABLE_IN_FIC_ENABLE_IN_BB_K2                                                             (0x1<<2) // FIC input enable bit used to enable/disable messages from being received on all FIC interfaces.
+  #define MSEM_REG_ENABLE_IN_FIC_ENABLE_IN_BB_K2_SHIFT                                                       2
+  #define MSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN_BB_K2                                                         (0x1<<3) // FOC acknowledge input enable bit used to enable/disable acknowledge response from being received on any of the FOC interfaces.
+  #define MSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN_BB_K2_SHIFT                                                   3
+  #define MSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN_BB_K2                                                         (0x1<<4) // General interface input enable.
+  #define MSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN_BB_K2_SHIFT                                                   4
+  #define MSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN_BB_K2                                                         (0x1<<5) // External passive write input enable.
+  #define MSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN_BB_K2_SHIFT                                                   5
+  #define MSEM_REG_ENABLE_IN_RAM_ENABLE_IN_BB_K2                                                             (0x1<<6) // Data input enable to RAM.
+  #define MSEM_REG_ENABLE_IN_RAM_ENABLE_IN_BB_K2_SHIFT                                                       6
+  #define MSEM_REG_ENABLE_IN_STALL_ENABLE_IN_BB_K2                                                           (0x1<<7) // Enable for stall input from all external STORM instances.
+  #define MSEM_REG_ENABLE_IN_STALL_ENABLE_IN_BB_K2_SHIFT                                                     7
+  #define MSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN_BB_K2                                                      (0x1<<8) // Thread ready bus input enable.
+  #define MSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN_BB_K2_SHIFT                                                8
+  #define MSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN_BB_K2                                                      (0x1<<9) // Input enable for VF error indication from SDM to SEMI.
+  #define MSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN_BB_K2_SHIFT                                                9
+#define MSEM_REG_ENABLE_OUT_BB_K2                                                                            0x1800008UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define MSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT_BB_K2                                                    (0x1<<0) // Read request output enable from external LS IF.
+  #define MSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT_BB_K2_SHIFT                                              0
+  #define MSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT_BB_K2                                                    (0x1<<1) // Write request output enable from external LS IF.
+  #define MSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT_BB_K2_SHIFT                                              1
+  #define MSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT_BB_K2                                                           (0x1<<2) // FOC output otuput enable bit used to enable/disable messages from being sent out on any of the FOC interfaces.
+  #define MSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT_BB_K2_SHIFT                                                     2
+  #define MSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT_BB_K2                                                       (0x1<<3) // Passive full output enable.
+  #define MSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT_BB_K2_SHIFT                                                 3
+  #define MSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT_BB_K2                                                           (0x1<<4) // Data output enable to RAM.
+  #define MSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT_BB_K2_SHIFT                                                     4
+  #define MSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT_BB_K2                                                         (0x1<<5) // Stall output enable bit used to enable/disable the output stall signal toward all external Storm instances.
+  #define MSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT_BB_K2_SHIFT                                                   5
+#define MSEM_REG_FIC_DISABLE_BB_K2                                                                           0x180000cUL //Access:RW   DataWidth:0x1    // Disables input messages from all FIC interfaces.  May be updated during run_time by the microcode.
+#define MSEM_REG_PAS_DISABLE_BB_K2                                                                           0x1800010UL //Access:RW   DataWidth:0x1    // Disables input messages from the passive buffer  May be updated during run_time by the microcode.
+#define MSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_E5                                                         0x1800014UL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define MSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_FIC_WEIGHT_E5                                   (0xf<<0) // Passive Buffer write WRR weight value for FIC source.
+  #define MSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_FIC_WEIGHT_E5_SHIFT                             0
+  #define MSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_A_WEIGHT_E5                                 (0xf<<4) // Passive Buffer write WRR weight value for DRA RD A source.
+  #define MSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_A_WEIGHT_E5_SHIFT                           4
+  #define MSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_B_WEIGHT_E5                                 (0xf<<8) // Passive Buffer write WRR weight value for DRA RD B source.
+  #define MSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_B_WEIGHT_E5_SHIFT                           8
+  #define MSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_SDM_WEIGHT_E5                                   (0xf<<12) // Passive Buffer write WRR weight value for SDM source.
+  #define MSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_SDM_WEIGHT_E5_SHIFT                             12
+  #define MSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_EMPTY_CNT_E5                                    (0xf<<16) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define MSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_EMPTY_CNT_E5_SHIFT                              16
+  #define MSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_STRICT_SRC_E5                                      (0x7<<20) // This register defines if one of the source of the PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B, 100 - SDM.
+  #define MSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_STRICT_SRC_E5_SHIFT                                20
+#define MSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_E5                                                          0x1800018UL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define MSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_FOC_WEIGHT_E5                                    (0xf<<0) // Passive Buffer WRR weight value for FOC source.
+  #define MSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_FOC_WEIGHT_E5_SHIFT                              0
+  #define MSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_A_WEIGHT_E5                                  (0xf<<4) // Passive Buffer write WRR weight value for DRA WR A source.
+  #define MSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_A_WEIGHT_E5_SHIFT                            4
+  #define MSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_B_WEIGHT_E5                                  (0xf<<8) // Passive Buffer write WRR weight value for DRA WR B source.
+  #define MSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_B_WEIGHT_E5_SHIFT                            8
+  #define MSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_GRC_WEIGHT_E5                                    (0xf<<12) // Passive Buffer write WRR weight value for GRC source.
+  #define MSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_GRC_WEIGHT_E5_SHIFT                              12
+  #define MSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_EMPTY_CNT_E5                                     (0xf<<16) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define MSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_EMPTY_CNT_E5_SHIFT                               16
+  #define MSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_STRICT_SRC_E5                                       (0x7<<20) // This register defines if one of the source of the PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B, 100 - GRC.
+  #define MSEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_STRICT_SRC_E5_SHIFT                                 20
+#define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_E5                                                            0x180001cUL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_FIC0_A_WEIGHT_E5                             (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_FIC0_A_WEIGHT_E5_SHIFT                       0
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_FIC1_A_WEIGHT_E5                             (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_FIC1_A_WEIGHT_E5_SHIFT                       4
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO0_A_WEIGHT_E5                            (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO0_A_WEIGHT_E5_SHIFT                      8
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO1_A_WEIGHT_E5                            (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO1_A_WEIGHT_E5_SHIFT                      12
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_EMPTY_CNT_E5                                 (0xf<<16) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_EMPTY_CNT_E5_SHIFT                           16
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_STRICT_SRC_E5                                   (0x7<<20) // This register defines if one of the source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - FIC1.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_STRICT_SRC_E5_SHIFT                             20
+#define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_E5                                                            0x1800020UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_FIC0_X_WEIGHT_E5                             (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_FIC0_X_WEIGHT_E5_SHIFT                       0
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO0_X_WEIGHT_E5                            (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO0_X_WEIGHT_E5_SHIFT                      4
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO1_X_WEIGHT_E5                            (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO1_X_WEIGHT_E5_SHIFT                      8
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_EMPTY_CNT_E5                                 (0xf<<12) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_EMPTY_CNT_E5_SHIFT                           12
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_STRICT_SRC_E5                                   (0x3<<16) // This register defines if one of the source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_STRICT_SRC_E5_SHIFT                             16
+#define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_E5                                                            0x1800024UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_FIC0_B_WEIGHT_E5                             (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_FIC0_B_WEIGHT_E5_SHIFT                       0
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO0_B_WEIGHT_E5                            (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO0_B_WEIGHT_E5_SHIFT                      4
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO1_B_WEIGHT_E5                            (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO1_B_WEIGHT_E5_SHIFT                      8
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_EMPTY_CNT_E5                                 (0xf<<12) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_EMPTY_CNT_E5_SHIFT                           12
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_STRICT_SRC_E5                                   (0x3<<16) // This register defines if one of the source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_STRICT_SRC_E5_SHIFT                             16
+#define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_E5                                                            0x1800028UL //Access:RW   DataWidth:0xe    // Multi Field Register.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_AFFIN_A_WEIGHT_E5                            (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for Affinity A source.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_AFFIN_A_WEIGHT_E5_SHIFT                      0
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_AFFIN_X_WEIGHT_E5                            (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for Affinity X source.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_AFFIN_X_WEIGHT_E5_SHIFT                      4
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_EMPTY_CNT_E5                                 (0xf<<8) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_EMPTY_CNT_E5_SHIFT                           8
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_STRICT_SRC_E5                                   (0x3<<12) // This register defines if one of the source of the PB WR arbiter should have strict priority: 0 - None, 1 - AFFINITY A, 2- AFFINITY X.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_STRICT_SRC_E5_SHIFT                             12
+#define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_E5                                                            0x180002cUL //Access:RW   DataWidth:0xc    // Multi Field Register.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_AFFIN_B_WEIGHT_E5                            (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for Affinity B source.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_AFFIN_B_WEIGHT_E5_SHIFT                      0
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_AFFIN_X_WEIGHT_E5                            (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for Affinity X source.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_AFFIN_X_WEIGHT_E5_SHIFT                      4
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_EMPTY_CNT_E5                                 (0xf<<8) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define MSEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_EMPTY_CNT_E5_SHIFT                           8
+#define MSEM_REG_PASSIVE_BUFFER_DRA_WR_E5                                                                    0x1800030UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define MSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_A_E5                                                   (0x1<<0) // Enable DRA Write to transactions towards the SEM_PD Core A.
+  #define MSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_A_E5_SHIFT                                             0
+  #define MSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_B_E5                                                   (0x1<<1) // Enable DRA Write to transactions towards the SEM_PD Core B.
+  #define MSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_B_E5_SHIFT                                             1
+  #define MSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_PEND_BLOCK_EN_E5                                          (0x1<<2) // When set, there may only be a single thread pending to run for each storm.
+  #define MSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_PEND_BLOCK_EN_E5_SHIFT                                    2
+  #define MSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_AFFINITY_CORE_A_ONLY_E5                                          (0x1<<3) // When set, the Affintiy field of the thread is set to CoreA (regardless to the Afficnity received from CM).
+  #define MSEM_REG_PASSIVE_BUFFER_DRA_WR_PB_AFFINITY_CORE_A_ONLY_E5_SHIFT                                    3
+#define MSEM_REG_INT_STS_0                                                                                   0x1800040UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define MSEM_REG_INT_STS_0_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define MSEM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                             0
+  #define MSEM_REG_INT_STS_0_FIC_LAST_ERROR                                                                  (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
+  #define MSEM_REG_INT_STS_0_FIC_LAST_ERROR_SHIFT                                                            1
+  #define MSEM_REG_INT_STS_0_FIC_LENGTH_ERROR                                                                (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
+  #define MSEM_REG_INT_STS_0_FIC_LENGTH_ERROR_SHIFT                                                          2
+  #define MSEM_REG_INT_STS_0_FIC_FIFO_ERROR                                                                  (0x1<<3) // Error in any one of the FIC FIFO is active.
+  #define MSEM_REG_INT_STS_0_FIC_FIFO_ERROR_SHIFT                                                            3
+  #define MSEM_REG_INT_STS_0_DRA_RD_A_LAST_ERROR_E5                                                          (0x1<<4) // DRA_RD_A last indication was unexpectedly received or was not received at expected time.
+  #define MSEM_REG_INT_STS_0_DRA_RD_A_LAST_ERROR_E5_SHIFT                                                    4
+  #define MSEM_REG_INT_STS_0_DRA_RD_B_LAST_ERROR_E5                                                          (0x1<<5) // DRA_RD_B last indication was unexpectedly received or was not received at expected time.
+  #define MSEM_REG_INT_STS_0_DRA_RD_B_LAST_ERROR_E5_SHIFT                                                    5
+  #define MSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_A_E5                                                   (0x1<<6) // Error in external store slow sync FIFO pop logic of Storm A.
+  #define MSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_A_E5_SHIFT                                             6
+  #define MSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_B_E5                                                   (0x1<<7) // Error in external store slow sync FIFO pop logic of Storm B.
+  #define MSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT                                             7
+  #define MSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5                                                   (0x1<<8) // Error in external load sync slow FIFO push logic.
+  #define MSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT                                             8
+  #define MSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5                                                   (0x1<<9) // Error in external load sync slow FIFO pop logic.
+  #define MSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5_SHIFT                                             9
+  #define MSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2                                                    (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
+  #define MSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2_SHIFT                                              22
+  #define MSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_E5                                                       (0x1<<10) // Error in slow LS_SYNC_PUSH FIFO.
+  #define MSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_E5_SHIFT                                                 10
+  #define MSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_BB_K2                                                     (0x1<<23) // Error in LS_SYNC_POP FIFO.
+  #define MSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_BB_K2_SHIFT                                               23
+  #define MSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_E5                                                        (0x1<<11) // Error in slow LS_SYNC_POP FIFO.
+  #define MSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_E5_SHIFT                                                  11
+  #define MSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2                                                    (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
+  #define MSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2_SHIFT                                              25
+  #define MSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_E5                                                       (0x1<<12) // Error in slow LS_SYNC_PUSH FIFO.
+  #define MSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_E5_SHIFT                                                 12
+  #define MSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_A_E5                                                         (0x1<<13) // Error in slow LS_SYNC_PUSH FIFO.
+  #define MSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_A_E5_SHIFT                                                   13
+  #define MSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_B_E5                                                         (0x1<<14) // Error in slow LS_SYNC_POP FIFO.
+  #define MSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_B_E5_SHIFT                                                   14
+  #define MSEM_REG_INT_STS_0_DBG_FIFO_ERROR_BB_K2                                                            (0x1<<28) // Error in slow debug fifo.
+  #define MSEM_REG_INT_STS_0_DBG_FIFO_ERROR_BB_K2_SHIFT                                                      28
+  #define MSEM_REG_INT_STS_0_DBG_FIFO_ERROR_E5                                                               (0x1<<15) // Error in slow debug fifo
+  #define MSEM_REG_INT_STS_0_DBG_FIFO_ERROR_E5_SHIFT                                                         15
+  #define MSEM_REG_INT_STS_0_EXT_THREAD_OOR_ERROR_E5                                                         (0x1<<16) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define MSEM_REG_INT_STS_0_EXT_THREAD_OOR_ERROR_E5_SHIFT                                                   16
+  #define MSEM_REG_INT_STS_0_EXT_STORE_TAG_ODER_ERROR_E5                                                     (0x1<<17) // Error detected in the ext Stroe interface internal TAG order ID.
+  #define MSEM_REG_INT_STS_0_EXT_STORE_TAG_ODER_ERROR_E5_SHIFT                                               17
+  #define MSEM_REG_INT_STS_0_FIC1_AFFINITY_FIELD_ERROR_E5                                                    (0x1<<18) // Indicates that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
+  #define MSEM_REG_INT_STS_0_FIC1_AFFINITY_FIELD_ERROR_E5_SHIFT                                              18
+  #define MSEM_REG_INT_STS_0_EXT_LD_LEN_ERROR_E5                                                             (0x1<<19) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define MSEM_REG_INT_STS_0_EXT_LD_LEN_ERROR_E5_SHIFT                                                       19
+  #define MSEM_REG_INT_STS_0_PB_QUE_ARB_THRD_RDY_ERROR_E5                                                    (0x1<<20) // Indicates that Passive Buffer State machine has unexpectedly received a ready indication in the following cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pending FOC" or "Ready FOC" state. b. Pending Ready indication is already asserted.
+  #define MSEM_REG_INT_STS_0_PB_QUE_ARB_THRD_RDY_ERROR_E5_SHIFT                                              20
+  #define MSEM_REG_INT_STS_0_SYNC_FOC_FIFO_ERROR_E5                                                          (0x1<<21) // Error indication on FOC sync FIFO.
+  #define MSEM_REG_INT_STS_0_SYNC_FOC_FIFO_ERROR_E5_SHIFT                                                    21
+  #define MSEM_REG_INT_STS_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                      (0x1<<22) // The error indicates on an error of one the threads READY queues.
+  #define MSEM_REG_INT_STS_0_PB_QUE_ARB_QUEUES_ERROR_E5_SHIFT                                                22
+  #define MSEM_REG_INT_STS_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5                                                (0x1<<23) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define MSEM_REG_INT_STS_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5_SHIFT                                          23
+  #define MSEM_REG_INT_STS_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5                                                (0x1<<24) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define MSEM_REG_INT_STS_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5_SHIFT                                          24
+  #define MSEM_REG_INT_STS_0_CREDIT_ERROR_FOC0_E5                                                            (0x1<<25) // FOC0 is out of credit.
+  #define MSEM_REG_INT_STS_0_CREDIT_ERROR_FOC0_E5_SHIFT                                                      25
+  #define MSEM_REG_INT_STS_0_CREDIT_ERROR_FOC1_E5                                                            (0x1<<26) // FOC1 is out of credit.
+  #define MSEM_REG_INT_STS_0_CREDIT_ERROR_FOC1_E5_SHIFT                                                      26
+  #define MSEM_REG_INT_STS_0_CREDIT_ERROR_FOC2_E5                                                            (0x1<<27) // FOC2 is out of credit.
+  #define MSEM_REG_INT_STS_0_CREDIT_ERROR_FOC2_E5_SHIFT                                                      27
+  #define MSEM_REG_INT_STS_0_CREDIT_ERROR_FOC3_E5                                                            (0x1<<28) // FOC3 is out of credit.
+  #define MSEM_REG_INT_STS_0_CREDIT_ERROR_FOC3_E5_SHIFT                                                      28
+  #define MSEM_REG_INT_STS_0_CREDIT_ERROR_FOC4_E5                                                            (0x1<<29) // FOC4 is out of credit.
+  #define MSEM_REG_INT_STS_0_CREDIT_ERROR_FOC4_E5_SHIFT                                                      29
+  #define MSEM_REG_INT_STS_0_CREDIT_ERROR_FOC5_E5                                                            (0x1<<30) // FOC5 is out of credit.
+  #define MSEM_REG_INT_STS_0_CREDIT_ERROR_FOC5_E5_SHIFT                                                      30
+  #define MSEM_REG_INT_STS_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                     (0x1<<31) // Error indication of foc pre_fetch fifo.
+  #define MSEM_REG_INT_STS_0_FOC_PRE_FETCH_FIFO_ERROR_E5_SHIFT                                               31
+  #define MSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR_BB_K2                                                        (0x1<<4) // Error in Ext PAS_FIFO is active.
+  #define MSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR_BB_K2_SHIFT                                                  4
+  #define MSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR_BB_K2                                                        (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
+  #define MSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR_BB_K2_SHIFT                                                  5
+  #define MSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2                                                    (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
+  #define MSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2_SHIFT                                              6
+  #define MSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR_BB_K2                                                     (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
+  #define MSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT                                               7
+  #define MSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2                                                    (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
+  #define MSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT                                              8
+  #define MSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR_BB_K2                                                     (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
+  #define MSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR_BB_K2_SHIFT                                               9
+  #define MSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR_BB_K2                                                       (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
+  #define MSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR_BB_K2_SHIFT                                                 10
+  #define MSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR_BB_K2                                                    (0x1<<11) // Signals an unknown address in the fast-memory window.
+  #define MSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR_BB_K2_SHIFT                                              11
+  #define MSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO_BB_K2                                                          (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
+  #define MSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO_BB_K2_SHIFT                                                    12
+  #define MSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO_BB_K2                                                          (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
+  #define MSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO_BB_K2_SHIFT                                                    13
+  #define MSEM_REG_INT_STS_0_CAM_OUT_FIFO_BB_K2                                                              (0x1<<14) // Error in CAM_OUT fifo in cam block.
+  #define MSEM_REG_INT_STS_0_CAM_OUT_FIFO_BB_K2_SHIFT                                                        14
+  #define MSEM_REG_INT_STS_0_FIN_FIFO_BB_K2                                                                  (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
+  #define MSEM_REG_INT_STS_0_FIN_FIFO_BB_K2_SHIFT                                                            15
+  #define MSEM_REG_INT_STS_0_THREAD_FIFO_ERROR_BB_K2                                                         (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
+  #define MSEM_REG_INT_STS_0_THREAD_FIFO_ERROR_BB_K2_SHIFT                                                   16
+  #define MSEM_REG_INT_STS_0_THREAD_OVERRUN_BB_K2                                                            (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
+  #define MSEM_REG_INT_STS_0_THREAD_OVERRUN_BB_K2_SHIFT                                                      17
+  #define MSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2                                                 (0x1<<18) // Error in external store sync FIFO push logic.
+  #define MSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2_SHIFT                                           18
+  #define MSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_BB_K2                                                  (0x1<<19) // Error in external store sync FIFO pop logic.
+  #define MSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_BB_K2_SHIFT                                            19
+  #define MSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2                                                  (0x1<<20) // Error in external load sync FIFO push logic.
+  #define MSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2_SHIFT                                            20
+  #define MSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2                                                   (0x1<<21) // Error in external load sync FIFO pop logic.
+  #define MSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2_SHIFT                                             21
+  #define MSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR_BB_K2                                                     (0x1<<24) // Error in LS_SYNC_POP FIFO.
+  #define MSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR_BB_K2_SHIFT                                               24
+  #define MSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR_BB_K2                                                       (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
+  #define MSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR_BB_K2_SHIFT                                                 26
+  #define MSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_BB_K2                                                        (0x1<<27) // Error in LS_SYNC_POP FIFO.
+  #define MSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_BB_K2_SHIFT                                                  27
+  #define MSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO_BB_K2                                                         (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
+  #define MSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO_BB_K2_SHIFT                                                   29
+  #define MSEM_REG_INT_STS_0_VFC_INTERRUPT_BB_K2                                                             (0x1<<30) // Error interrupt in VFC block.
+  #define MSEM_REG_INT_STS_0_VFC_INTERRUPT_BB_K2_SHIFT                                                       30
+  #define MSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR_BB_K2                                                        (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
+  #define MSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR_BB_K2_SHIFT                                                  31
+#define MSEM_REG_INT_MASK_0                                                                                  0x1800044UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MSEM_REG_INT_MASK_0_ADDRESS_ERROR                                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.ADDRESS_ERROR .
+  #define MSEM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                            0
+  #define MSEM_REG_INT_MASK_0_FIC_LAST_ERROR                                                                 (0x1<<1) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.FIC_LAST_ERROR .
+  #define MSEM_REG_INT_MASK_0_FIC_LAST_ERROR_SHIFT                                                           1
+  #define MSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR                                                               (0x1<<2) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.FIC_LENGTH_ERROR .
+  #define MSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR_SHIFT                                                         2
+  #define MSEM_REG_INT_MASK_0_FIC_FIFO_ERROR                                                                 (0x1<<3) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.FIC_FIFO_ERROR .
+  #define MSEM_REG_INT_MASK_0_FIC_FIFO_ERROR_SHIFT                                                           3
+  #define MSEM_REG_INT_MASK_0_DRA_RD_A_LAST_ERROR_E5                                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.DRA_RD_A_LAST_ERROR .
+  #define MSEM_REG_INT_MASK_0_DRA_RD_A_LAST_ERROR_E5_SHIFT                                                   4
+  #define MSEM_REG_INT_MASK_0_DRA_RD_B_LAST_ERROR_E5                                                         (0x1<<5) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.DRA_RD_B_LAST_ERROR .
+  #define MSEM_REG_INT_MASK_0_DRA_RD_B_LAST_ERROR_E5_SHIFT                                                   5
+  #define MSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_A_E5                                                  (0x1<<6) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR_A .
+  #define MSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_A_E5_SHIFT                                            6
+  #define MSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_B_E5                                                  (0x1<<7) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR_B .
+  #define MSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT                                            7
+  #define MSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5                                                  (0x1<<8) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR_A .
+  #define MSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT                                            8
+  #define MSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5                                                  (0x1<<9) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR_B .
+  #define MSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5_SHIFT                                            9
+  #define MSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2                                                   (0x1<<22) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_RAM_RD_PUSH_ERROR .
+  #define MSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2_SHIFT                                             22
+  #define MSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_E5                                                      (0x1<<10) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_RAM_RD_PUSH_ERROR .
+  #define MSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_E5_SHIFT                                                10
+  #define MSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_BB_K2                                                    (0x1<<23) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_RAM_RD_POP_ERROR .
+  #define MSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_BB_K2_SHIFT                                              23
+  #define MSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_E5                                                       (0x1<<11) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_RAM_RD_POP_ERROR .
+  #define MSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_E5_SHIFT                                                 11
+  #define MSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2                                                   (0x1<<25) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_RAM_WR_PUSH_ERROR .
+  #define MSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2_SHIFT                                             25
+  #define MSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_E5                                                      (0x1<<12) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_RAM_WR_PUSH_ERROR .
+  #define MSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_E5_SHIFT                                                12
+  #define MSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_A_E5                                                        (0x1<<13) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR_A .
+  #define MSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_A_E5_SHIFT                                                  13
+  #define MSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_B_E5                                                        (0x1<<14) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR_B .
+  #define MSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_B_E5_SHIFT                                                  14
+  #define MSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_BB_K2                                                           (0x1<<28) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.DBG_FIFO_ERROR .
+  #define MSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_BB_K2_SHIFT                                                     28
+  #define MSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_E5                                                              (0x1<<15) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.DBG_FIFO_ERROR .
+  #define MSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_E5_SHIFT                                                        15
+  #define MSEM_REG_INT_MASK_0_EXT_THREAD_OOR_ERROR_E5                                                        (0x1<<16) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.EXT_THREAD_OOR_ERROR .
+  #define MSEM_REG_INT_MASK_0_EXT_THREAD_OOR_ERROR_E5_SHIFT                                                  16
+  #define MSEM_REG_INT_MASK_0_EXT_STORE_TAG_ODER_ERROR_E5                                                    (0x1<<17) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.EXT_STORE_TAG_ODER_ERROR .
+  #define MSEM_REG_INT_MASK_0_EXT_STORE_TAG_ODER_ERROR_E5_SHIFT                                              17
+  #define MSEM_REG_INT_MASK_0_FIC1_AFFINITY_FIELD_ERROR_E5                                                   (0x1<<18) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.FIC1_AFFINITY_FIELD_ERROR .
+  #define MSEM_REG_INT_MASK_0_FIC1_AFFINITY_FIELD_ERROR_E5_SHIFT                                             18
+  #define MSEM_REG_INT_MASK_0_EXT_LD_LEN_ERROR_E5                                                            (0x1<<19) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.EXT_LD_LEN_ERROR .
+  #define MSEM_REG_INT_MASK_0_EXT_LD_LEN_ERROR_E5_SHIFT                                                      19
+  #define MSEM_REG_INT_MASK_0_PB_QUE_ARB_THRD_RDY_ERROR_E5                                                   (0x1<<20) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.PB_QUE_ARB_THRD_RDY_ERROR .
+  #define MSEM_REG_INT_MASK_0_PB_QUE_ARB_THRD_RDY_ERROR_E5_SHIFT                                             20
+  #define MSEM_REG_INT_MASK_0_SYNC_FOC_FIFO_ERROR_E5                                                         (0x1<<21) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_FOC_FIFO_ERROR .
+  #define MSEM_REG_INT_MASK_0_SYNC_FOC_FIFO_ERROR_E5_SHIFT                                                   21
+  #define MSEM_REG_INT_MASK_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                     (0x1<<22) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.PB_QUE_ARB_QUEUES_ERROR .
+  #define MSEM_REG_INT_MASK_0_PB_QUE_ARB_QUEUES_ERROR_E5_SHIFT                                               22
+  #define MSEM_REG_INT_MASK_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5                                               (0x1<<23) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.STORM_MOVRIND_USES_BAR_ATTN_A .
+  #define MSEM_REG_INT_MASK_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5_SHIFT                                         23
+  #define MSEM_REG_INT_MASK_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5                                               (0x1<<24) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.STORM_MOVRIND_USES_BAR_ATTN_B .
+  #define MSEM_REG_INT_MASK_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5_SHIFT                                         24
+  #define MSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC0_E5                                                           (0x1<<25) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.CREDIT_ERROR_FOC0 .
+  #define MSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC0_E5_SHIFT                                                     25
+  #define MSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC1_E5                                                           (0x1<<26) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.CREDIT_ERROR_FOC1 .
+  #define MSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC1_E5_SHIFT                                                     26
+  #define MSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC2_E5                                                           (0x1<<27) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.CREDIT_ERROR_FOC2 .
+  #define MSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC2_E5_SHIFT                                                     27
+  #define MSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC3_E5                                                           (0x1<<28) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.CREDIT_ERROR_FOC3 .
+  #define MSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC3_E5_SHIFT                                                     28
+  #define MSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC4_E5                                                           (0x1<<29) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.CREDIT_ERROR_FOC4 .
+  #define MSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC4_E5_SHIFT                                                     29
+  #define MSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC5_E5                                                           (0x1<<30) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.CREDIT_ERROR_FOC5 .
+  #define MSEM_REG_INT_MASK_0_CREDIT_ERROR_FOC5_E5_SHIFT                                                     30
+  #define MSEM_REG_INT_MASK_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                    (0x1<<31) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.FOC_PRE_FETCH_FIFO_ERROR .
+  #define MSEM_REG_INT_MASK_0_FOC_PRE_FETCH_FIFO_ERROR_E5_SHIFT                                              31
+  #define MSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR_BB_K2                                                       (0x1<<4) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.PAS_BUF_FIFO_ERROR .
+  #define MSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR_BB_K2_SHIFT                                                 4
+  #define MSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR_BB_K2                                                       (0x1<<5) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_FIN_POP_ERROR .
+  #define MSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR_BB_K2_SHIFT                                                 5
+  #define MSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2                                                   (0x1<<6) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_DRA_WR_PUSH_ERROR .
+  #define MSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2_SHIFT                                             6
+  #define MSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR_BB_K2                                                    (0x1<<7) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_DRA_WR_POP_ERROR .
+  #define MSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT                                              7
+  #define MSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2                                                   (0x1<<8) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_DRA_RD_PUSH_ERROR .
+  #define MSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT                                             8
+  #define MSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR_BB_K2                                                    (0x1<<9) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_DRA_RD_POP_ERROR .
+  #define MSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR_BB_K2_SHIFT                                              9
+  #define MSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR_BB_K2                                                      (0x1<<10) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_FIN_PUSH_ERROR .
+  #define MSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR_BB_K2_SHIFT                                                10
+  #define MSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR_BB_K2                                                   (0x1<<11) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SEM_FAST_ADDRESS_ERROR .
+  #define MSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR_BB_K2_SHIFT                                             11
+  #define MSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO_BB_K2                                                         (0x1<<12) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.CAM_LSB_INP_FIFO .
+  #define MSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO_BB_K2_SHIFT                                                   12
+  #define MSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO_BB_K2                                                         (0x1<<13) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.CAM_MSB_INP_FIFO .
+  #define MSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO_BB_K2_SHIFT                                                   13
+  #define MSEM_REG_INT_MASK_0_CAM_OUT_FIFO_BB_K2                                                             (0x1<<14) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.CAM_OUT_FIFO .
+  #define MSEM_REG_INT_MASK_0_CAM_OUT_FIFO_BB_K2_SHIFT                                                       14
+  #define MSEM_REG_INT_MASK_0_FIN_FIFO_BB_K2                                                                 (0x1<<15) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.FIN_FIFO .
+  #define MSEM_REG_INT_MASK_0_FIN_FIFO_BB_K2_SHIFT                                                           15
+  #define MSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR_BB_K2                                                        (0x1<<16) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.THREAD_FIFO_ERROR .
+  #define MSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR_BB_K2_SHIFT                                                  16
+  #define MSEM_REG_INT_MASK_0_THREAD_OVERRUN_BB_K2                                                           (0x1<<17) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.THREAD_OVERRUN .
+  #define MSEM_REG_INT_MASK_0_THREAD_OVERRUN_BB_K2_SHIFT                                                     17
+  #define MSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2                                                (0x1<<18) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_EXT_STORE_PUSH_ERROR .
+  #define MSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2_SHIFT                                          18
+  #define MSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_BB_K2                                                 (0x1<<19) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR .
+  #define MSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_BB_K2_SHIFT                                           19
+  #define MSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2                                                 (0x1<<20) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR .
+  #define MSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2_SHIFT                                           20
+  #define MSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2                                                  (0x1<<21) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_EXT_LOAD_POP_ERROR .
+  #define MSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2_SHIFT                                            21
+  #define MSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR_BB_K2                                                    (0x1<<24) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_RAM_WR_POP_ERROR .
+  #define MSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR_BB_K2_SHIFT                                              24
+  #define MSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR_BB_K2                                                      (0x1<<26) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_DBG_PUSH_ERROR .
+  #define MSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR_BB_K2_SHIFT                                                26
+  #define MSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_BB_K2                                                       (0x1<<27) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR .
+  #define MSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_BB_K2_SHIFT                                                 27
+  #define MSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO_BB_K2                                                        (0x1<<29) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.CAM_MSB2_INP_FIFO .
+  #define MSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO_BB_K2_SHIFT                                                  29
+  #define MSEM_REG_INT_MASK_0_VFC_INTERRUPT_BB_K2                                                            (0x1<<30) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.VFC_INTERRUPT .
+  #define MSEM_REG_INT_MASK_0_VFC_INTERRUPT_BB_K2_SHIFT                                                      30
+  #define MSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR_BB_K2                                                       (0x1<<31) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.VFC_OUT_FIFO_ERROR .
+  #define MSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR_BB_K2_SHIFT                                                 31
+#define MSEM_REG_INT_STS_WR_0                                                                                0x1800048UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define MSEM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define MSEM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                          0
+  #define MSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR                                                               (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
+  #define MSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR_SHIFT                                                         1
+  #define MSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR                                                             (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
+  #define MSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR_SHIFT                                                       2
+  #define MSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR                                                               (0x1<<3) // Error in any one of the FIC FIFO is active.
+  #define MSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR_SHIFT                                                         3
+  #define MSEM_REG_INT_STS_WR_0_DRA_RD_A_LAST_ERROR_E5                                                       (0x1<<4) // DRA_RD_A last indication was unexpectedly received or was not received at expected time.
+  #define MSEM_REG_INT_STS_WR_0_DRA_RD_A_LAST_ERROR_E5_SHIFT                                                 4
+  #define MSEM_REG_INT_STS_WR_0_DRA_RD_B_LAST_ERROR_E5                                                       (0x1<<5) // DRA_RD_B last indication was unexpectedly received or was not received at expected time.
+  #define MSEM_REG_INT_STS_WR_0_DRA_RD_B_LAST_ERROR_E5_SHIFT                                                 5
+  #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_A_E5                                                (0x1<<6) // Error in external store slow sync FIFO pop logic of Storm A.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_A_E5_SHIFT                                          6
+  #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_B_E5                                                (0x1<<7) // Error in external store slow sync FIFO pop logic of Storm B.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT                                          7
+  #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5                                                (0x1<<8) // Error in external load sync slow FIFO push logic.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT                                          8
+  #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5                                                (0x1<<9) // Error in external load sync slow FIFO pop logic.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5_SHIFT                                          9
+  #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2                                                 (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2_SHIFT                                           22
+  #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_E5                                                    (0x1<<10) // Error in slow LS_SYNC_PUSH FIFO.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_E5_SHIFT                                              10
+  #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_BB_K2                                                  (0x1<<23) // Error in LS_SYNC_POP FIFO.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_BB_K2_SHIFT                                            23
+  #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_E5                                                     (0x1<<11) // Error in slow LS_SYNC_POP FIFO.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_E5_SHIFT                                               11
+  #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2                                                 (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2_SHIFT                                           25
+  #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_E5                                                    (0x1<<12) // Error in slow LS_SYNC_PUSH FIFO.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_E5_SHIFT                                              12
+  #define MSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_A_E5                                                      (0x1<<13) // Error in slow LS_SYNC_PUSH FIFO.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_A_E5_SHIFT                                                13
+  #define MSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_B_E5                                                      (0x1<<14) // Error in slow LS_SYNC_POP FIFO.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_B_E5_SHIFT                                                14
+  #define MSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_BB_K2                                                         (0x1<<28) // Error in slow debug fifo.
+  #define MSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_BB_K2_SHIFT                                                   28
+  #define MSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_E5                                                            (0x1<<15) // Error in slow debug fifo
+  #define MSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_E5_SHIFT                                                      15
+  #define MSEM_REG_INT_STS_WR_0_EXT_THREAD_OOR_ERROR_E5                                                      (0x1<<16) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define MSEM_REG_INT_STS_WR_0_EXT_THREAD_OOR_ERROR_E5_SHIFT                                                16
+  #define MSEM_REG_INT_STS_WR_0_EXT_STORE_TAG_ODER_ERROR_E5                                                  (0x1<<17) // Error detected in the ext Stroe interface internal TAG order ID.
+  #define MSEM_REG_INT_STS_WR_0_EXT_STORE_TAG_ODER_ERROR_E5_SHIFT                                            17
+  #define MSEM_REG_INT_STS_WR_0_FIC1_AFFINITY_FIELD_ERROR_E5                                                 (0x1<<18) // Indicates that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
+  #define MSEM_REG_INT_STS_WR_0_FIC1_AFFINITY_FIELD_ERROR_E5_SHIFT                                           18
+  #define MSEM_REG_INT_STS_WR_0_EXT_LD_LEN_ERROR_E5                                                          (0x1<<19) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define MSEM_REG_INT_STS_WR_0_EXT_LD_LEN_ERROR_E5_SHIFT                                                    19
+  #define MSEM_REG_INT_STS_WR_0_PB_QUE_ARB_THRD_RDY_ERROR_E5                                                 (0x1<<20) // Indicates that Passive Buffer State machine has unexpectedly received a ready indication in the following cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pending FOC" or "Ready FOC" state. b. Pending Ready indication is already asserted.
+  #define MSEM_REG_INT_STS_WR_0_PB_QUE_ARB_THRD_RDY_ERROR_E5_SHIFT                                           20
+  #define MSEM_REG_INT_STS_WR_0_SYNC_FOC_FIFO_ERROR_E5                                                       (0x1<<21) // Error indication on FOC sync FIFO.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_FOC_FIFO_ERROR_E5_SHIFT                                                 21
+  #define MSEM_REG_INT_STS_WR_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                   (0x1<<22) // The error indicates on an error of one the threads READY queues.
+  #define MSEM_REG_INT_STS_WR_0_PB_QUE_ARB_QUEUES_ERROR_E5_SHIFT                                             22
+  #define MSEM_REG_INT_STS_WR_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5                                             (0x1<<23) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define MSEM_REG_INT_STS_WR_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5_SHIFT                                       23
+  #define MSEM_REG_INT_STS_WR_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5                                             (0x1<<24) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define MSEM_REG_INT_STS_WR_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5_SHIFT                                       24
+  #define MSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC0_E5                                                         (0x1<<25) // FOC0 is out of credit.
+  #define MSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC0_E5_SHIFT                                                   25
+  #define MSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC1_E5                                                         (0x1<<26) // FOC1 is out of credit.
+  #define MSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC1_E5_SHIFT                                                   26
+  #define MSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC2_E5                                                         (0x1<<27) // FOC2 is out of credit.
+  #define MSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC2_E5_SHIFT                                                   27
+  #define MSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC3_E5                                                         (0x1<<28) // FOC3 is out of credit.
+  #define MSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC3_E5_SHIFT                                                   28
+  #define MSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC4_E5                                                         (0x1<<29) // FOC4 is out of credit.
+  #define MSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC4_E5_SHIFT                                                   29
+  #define MSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC5_E5                                                         (0x1<<30) // FOC5 is out of credit.
+  #define MSEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC5_E5_SHIFT                                                   30
+  #define MSEM_REG_INT_STS_WR_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                  (0x1<<31) // Error indication of foc pre_fetch fifo.
+  #define MSEM_REG_INT_STS_WR_0_FOC_PRE_FETCH_FIFO_ERROR_E5_SHIFT                                            31
+  #define MSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR_BB_K2                                                     (0x1<<4) // Error in Ext PAS_FIFO is active.
+  #define MSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR_BB_K2_SHIFT                                               4
+  #define MSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR_BB_K2                                                     (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR_BB_K2_SHIFT                                               5
+  #define MSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2                                                 (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2_SHIFT                                           6
+  #define MSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR_BB_K2                                                  (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT                                            7
+  #define MSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2                                                 (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT                                           8
+  #define MSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR_BB_K2                                                  (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR_BB_K2_SHIFT                                            9
+  #define MSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR_BB_K2                                                    (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR_BB_K2_SHIFT                                              10
+  #define MSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR_BB_K2                                                 (0x1<<11) // Signals an unknown address in the fast-memory window.
+  #define MSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR_BB_K2_SHIFT                                           11
+  #define MSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO_BB_K2                                                       (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
+  #define MSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO_BB_K2_SHIFT                                                 12
+  #define MSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO_BB_K2                                                       (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
+  #define MSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO_BB_K2_SHIFT                                                 13
+  #define MSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO_BB_K2                                                           (0x1<<14) // Error in CAM_OUT fifo in cam block.
+  #define MSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO_BB_K2_SHIFT                                                     14
+  #define MSEM_REG_INT_STS_WR_0_FIN_FIFO_BB_K2                                                               (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
+  #define MSEM_REG_INT_STS_WR_0_FIN_FIFO_BB_K2_SHIFT                                                         15
+  #define MSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR_BB_K2                                                      (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
+  #define MSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR_BB_K2_SHIFT                                                16
+  #define MSEM_REG_INT_STS_WR_0_THREAD_OVERRUN_BB_K2                                                         (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
+  #define MSEM_REG_INT_STS_WR_0_THREAD_OVERRUN_BB_K2_SHIFT                                                   17
+  #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2                                              (0x1<<18) // Error in external store sync FIFO push logic.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2_SHIFT                                        18
+  #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_BB_K2                                               (0x1<<19) // Error in external store sync FIFO pop logic.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_BB_K2_SHIFT                                         19
+  #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2                                               (0x1<<20) // Error in external load sync FIFO push logic.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2_SHIFT                                         20
+  #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2                                                (0x1<<21) // Error in external load sync FIFO pop logic.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2_SHIFT                                          21
+  #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR_BB_K2                                                  (0x1<<24) // Error in LS_SYNC_POP FIFO.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR_BB_K2_SHIFT                                            24
+  #define MSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR_BB_K2                                                    (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR_BB_K2_SHIFT                                              26
+  #define MSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_BB_K2                                                     (0x1<<27) // Error in LS_SYNC_POP FIFO.
+  #define MSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_BB_K2_SHIFT                                               27
+  #define MSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO_BB_K2                                                      (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
+  #define MSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO_BB_K2_SHIFT                                                29
+  #define MSEM_REG_INT_STS_WR_0_VFC_INTERRUPT_BB_K2                                                          (0x1<<30) // Error interrupt in VFC block.
+  #define MSEM_REG_INT_STS_WR_0_VFC_INTERRUPT_BB_K2_SHIFT                                                    30
+  #define MSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR_BB_K2                                                     (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
+  #define MSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR_BB_K2_SHIFT                                               31
+#define MSEM_REG_INT_STS_CLR_0                                                                               0x180004cUL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define MSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                               (0x1<<0) // Signals an unknown address to the rf module.
+  #define MSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                         0
+  #define MSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR                                                              (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
+  #define MSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR_SHIFT                                                        1
+  #define MSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR                                                            (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
+  #define MSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR_SHIFT                                                      2
+  #define MSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR                                                              (0x1<<3) // Error in any one of the FIC FIFO is active.
+  #define MSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR_SHIFT                                                        3
+  #define MSEM_REG_INT_STS_CLR_0_DRA_RD_A_LAST_ERROR_E5                                                      (0x1<<4) // DRA_RD_A last indication was unexpectedly received or was not received at expected time.
+  #define MSEM_REG_INT_STS_CLR_0_DRA_RD_A_LAST_ERROR_E5_SHIFT                                                4
+  #define MSEM_REG_INT_STS_CLR_0_DRA_RD_B_LAST_ERROR_E5                                                      (0x1<<5) // DRA_RD_B last indication was unexpectedly received or was not received at expected time.
+  #define MSEM_REG_INT_STS_CLR_0_DRA_RD_B_LAST_ERROR_E5_SHIFT                                                5
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_A_E5                                               (0x1<<6) // Error in external store slow sync FIFO pop logic of Storm A.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_A_E5_SHIFT                                         6
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_B_E5                                               (0x1<<7) // Error in external store slow sync FIFO pop logic of Storm B.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT                                         7
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5                                               (0x1<<8) // Error in external load sync slow FIFO push logic.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT                                         8
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5                                               (0x1<<9) // Error in external load sync slow FIFO pop logic.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5_SHIFT                                         9
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2                                                (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2_SHIFT                                          22
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_E5                                                   (0x1<<10) // Error in slow LS_SYNC_PUSH FIFO.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_E5_SHIFT                                             10
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_BB_K2                                                 (0x1<<23) // Error in LS_SYNC_POP FIFO.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_BB_K2_SHIFT                                           23
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_E5                                                    (0x1<<11) // Error in slow LS_SYNC_POP FIFO.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_E5_SHIFT                                              11
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2                                                (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2_SHIFT                                          25
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_E5                                                   (0x1<<12) // Error in slow LS_SYNC_PUSH FIFO.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_E5_SHIFT                                             12
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_A_E5                                                     (0x1<<13) // Error in slow LS_SYNC_PUSH FIFO.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_A_E5_SHIFT                                               13
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_B_E5                                                     (0x1<<14) // Error in slow LS_SYNC_POP FIFO.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_B_E5_SHIFT                                               14
+  #define MSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_BB_K2                                                        (0x1<<28) // Error in slow debug fifo.
+  #define MSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_BB_K2_SHIFT                                                  28
+  #define MSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_E5                                                           (0x1<<15) // Error in slow debug fifo
+  #define MSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_E5_SHIFT                                                     15
+  #define MSEM_REG_INT_STS_CLR_0_EXT_THREAD_OOR_ERROR_E5                                                     (0x1<<16) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define MSEM_REG_INT_STS_CLR_0_EXT_THREAD_OOR_ERROR_E5_SHIFT                                               16
+  #define MSEM_REG_INT_STS_CLR_0_EXT_STORE_TAG_ODER_ERROR_E5                                                 (0x1<<17) // Error detected in the ext Stroe interface internal TAG order ID.
+  #define MSEM_REG_INT_STS_CLR_0_EXT_STORE_TAG_ODER_ERROR_E5_SHIFT                                           17
+  #define MSEM_REG_INT_STS_CLR_0_FIC1_AFFINITY_FIELD_ERROR_E5                                                (0x1<<18) // Indicates that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
+  #define MSEM_REG_INT_STS_CLR_0_FIC1_AFFINITY_FIELD_ERROR_E5_SHIFT                                          18
+  #define MSEM_REG_INT_STS_CLR_0_EXT_LD_LEN_ERROR_E5                                                         (0x1<<19) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define MSEM_REG_INT_STS_CLR_0_EXT_LD_LEN_ERROR_E5_SHIFT                                                   19
+  #define MSEM_REG_INT_STS_CLR_0_PB_QUE_ARB_THRD_RDY_ERROR_E5                                                (0x1<<20) // Indicates that Passive Buffer State machine has unexpectedly received a ready indication in the following cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pending FOC" or "Ready FOC" state. b. Pending Ready indication is already asserted.
+  #define MSEM_REG_INT_STS_CLR_0_PB_QUE_ARB_THRD_RDY_ERROR_E5_SHIFT                                          20
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_FOC_FIFO_ERROR_E5                                                      (0x1<<21) // Error indication on FOC sync FIFO.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_FOC_FIFO_ERROR_E5_SHIFT                                                21
+  #define MSEM_REG_INT_STS_CLR_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                  (0x1<<22) // The error indicates on an error of one the threads READY queues.
+  #define MSEM_REG_INT_STS_CLR_0_PB_QUE_ARB_QUEUES_ERROR_E5_SHIFT                                            22
+  #define MSEM_REG_INT_STS_CLR_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5                                            (0x1<<23) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define MSEM_REG_INT_STS_CLR_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5_SHIFT                                      23
+  #define MSEM_REG_INT_STS_CLR_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5                                            (0x1<<24) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define MSEM_REG_INT_STS_CLR_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5_SHIFT                                      24
+  #define MSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC0_E5                                                        (0x1<<25) // FOC0 is out of credit.
+  #define MSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC0_E5_SHIFT                                                  25
+  #define MSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC1_E5                                                        (0x1<<26) // FOC1 is out of credit.
+  #define MSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC1_E5_SHIFT                                                  26
+  #define MSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC2_E5                                                        (0x1<<27) // FOC2 is out of credit.
+  #define MSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC2_E5_SHIFT                                                  27
+  #define MSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC3_E5                                                        (0x1<<28) // FOC3 is out of credit.
+  #define MSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC3_E5_SHIFT                                                  28
+  #define MSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC4_E5                                                        (0x1<<29) // FOC4 is out of credit.
+  #define MSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC4_E5_SHIFT                                                  29
+  #define MSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC5_E5                                                        (0x1<<30) // FOC5 is out of credit.
+  #define MSEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC5_E5_SHIFT                                                  30
+  #define MSEM_REG_INT_STS_CLR_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                 (0x1<<31) // Error indication of foc pre_fetch fifo.
+  #define MSEM_REG_INT_STS_CLR_0_FOC_PRE_FETCH_FIFO_ERROR_E5_SHIFT                                           31
+  #define MSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR_BB_K2                                                    (0x1<<4) // Error in Ext PAS_FIFO is active.
+  #define MSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR_BB_K2_SHIFT                                              4
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR_BB_K2                                                    (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR_BB_K2_SHIFT                                              5
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2                                                (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2_SHIFT                                          6
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR_BB_K2                                                 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT                                           7
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2                                                (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT                                          8
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR_BB_K2                                                 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR_BB_K2_SHIFT                                           9
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR_BB_K2                                                   (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR_BB_K2_SHIFT                                             10
+  #define MSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR_BB_K2                                                (0x1<<11) // Signals an unknown address in the fast-memory window.
+  #define MSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR_BB_K2_SHIFT                                          11
+  #define MSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO_BB_K2                                                      (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
+  #define MSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO_BB_K2_SHIFT                                                12
+  #define MSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO_BB_K2                                                      (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
+  #define MSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO_BB_K2_SHIFT                                                13
+  #define MSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO_BB_K2                                                          (0x1<<14) // Error in CAM_OUT fifo in cam block.
+  #define MSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO_BB_K2_SHIFT                                                    14
+  #define MSEM_REG_INT_STS_CLR_0_FIN_FIFO_BB_K2                                                              (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
+  #define MSEM_REG_INT_STS_CLR_0_FIN_FIFO_BB_K2_SHIFT                                                        15
+  #define MSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR_BB_K2                                                     (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
+  #define MSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR_BB_K2_SHIFT                                               16
+  #define MSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN_BB_K2                                                        (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
+  #define MSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN_BB_K2_SHIFT                                                  17
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2                                             (0x1<<18) // Error in external store sync FIFO push logic.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2_SHIFT                                       18
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_BB_K2                                              (0x1<<19) // Error in external store sync FIFO pop logic.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_BB_K2_SHIFT                                        19
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2                                              (0x1<<20) // Error in external load sync FIFO push logic.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2_SHIFT                                        20
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2                                               (0x1<<21) // Error in external load sync FIFO pop logic.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2_SHIFT                                         21
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR_BB_K2                                                 (0x1<<24) // Error in LS_SYNC_POP FIFO.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR_BB_K2_SHIFT                                           24
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR_BB_K2                                                   (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR_BB_K2_SHIFT                                             26
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_BB_K2                                                    (0x1<<27) // Error in LS_SYNC_POP FIFO.
+  #define MSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_BB_K2_SHIFT                                              27
+  #define MSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO_BB_K2                                                     (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
+  #define MSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO_BB_K2_SHIFT                                               29
+  #define MSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT_BB_K2                                                         (0x1<<30) // Error interrupt in VFC block.
+  #define MSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT_BB_K2_SHIFT                                                   30
+  #define MSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR_BB_K2                                                    (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
+  #define MSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR_BB_K2_SHIFT                                              31
+#define MSEM_REG_INT_STS_1                                                                                   0x1800050UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define MSEM_REG_INT_STS_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5                                              (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
+  #define MSEM_REG_INT_STS_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5_SHIFT                                        0
+  #define MSEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_A_E5                                                  (0x1<<1) // Fast external store FIFO error of Storm_A
+  #define MSEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT                                            1
+  #define MSEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_B_E5                                                  (0x1<<2) // Fast external store FIFO error of Storm_B
+  #define MSEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_B_E5_SHIFT                                            2
+  #define MSEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_A_E5                                                    (0x1<<3) // fast external load FIFO error of Storm_A
+  #define MSEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT                                              3
+  #define MSEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_B_E5                                                    (0x1<<4) // fast external load FIFO error of Storm_B
+  #define MSEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_B_E5_SHIFT                                              4
+  #define MSEM_REG_INT_STS_1_FAST_RAM_WR_POP_ERROR_E5                                                        (0x1<<5) // Internal RAM pop error
+  #define MSEM_REG_INT_STS_1_FAST_RAM_WR_POP_ERROR_E5_SHIFT                                                  5
+  #define MSEM_REG_INT_STS_1_FAST_RAM_RD_PUSH_ERROR_E5                                                       (0x1<<6) // Internal RAM write error
+  #define MSEM_REG_INT_STS_1_FAST_RAM_RD_PUSH_ERROR_E5_SHIFT                                                 6
+  #define MSEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_A_E5                                                     (0x1<<7) // DRA RD FIFO error of Storm A
+  #define MSEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT                                               7
+  #define MSEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_B_E5                                                     (0x1<<8) // DRA RD FIFO error of Storm B
+  #define MSEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT                                               8
+  #define MSEM_REG_INT_STS_1_FAST_DRA_WR_POP_ERROR_A_E5                                                      (0x1<<9) // DRA RD FIFO error of Storm A
+  #define MSEM_REG_INT_STS_1_FAST_DRA_WR_POP_ERROR_A_E5_SHIFT                                                9
+  #define MSEM_REG_INT_STS_1_FAST_DRA_WR_POP_ERROR_B_E5                                                      (0x1<<10) // DRA RD FIFO error of Storm B
+  #define MSEM_REG_INT_STS_1_FAST_DRA_WR_POP_ERROR_B_E5_SHIFT                                                10
+  #define MSEM_REG_INT_STS_1_SEM_FAST_INVLD_ADDR_ERR_E5                                                      (0x1<<11) // Fast invalid address error
+  #define MSEM_REG_INT_STS_1_SEM_FAST_INVLD_ADDR_ERR_E5_SHIFT                                                11
+  #define MSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_A_E5                                                        (0x1<<12) // Storm A stack_uf_attn interrupt
+  #define MSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_A_E5_SHIFT                                                  12
+  #define MSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_B_E5                                                        (0x1<<13) // Storm B stack_uf_attn interrupt
+  #define MSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_B_E5_SHIFT                                                  13
+  #define MSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_A_E5                                                        (0x1<<14) // Storm A stack_of_attn interrupt
+  #define MSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_A_E5_SHIFT                                                  14
+  #define MSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_B_E5                                                        (0x1<<15) // Storm B stack_of_attn interrupt
+  #define MSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_B_E5_SHIFT                                                  15
+  #define MSEM_REG_INT_STS_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5                                                 (0x1<<16) // Storm A ldst_addr_ovflw_attn interrupt
+  #define MSEM_REG_INT_STS_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5_SHIFT                                           16
+  #define MSEM_REG_INT_STS_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5                                                 (0x1<<17) // Storm B ldst_addr_ovflw_attn interrupt
+  #define MSEM_REG_INT_STS_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5_SHIFT                                           17
+  #define MSEM_REG_INT_STS_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5                                              (0x1<<18) // Storm A non_aligned_access_attn interrupt
+  #define MSEM_REG_INT_STS_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5_SHIFT                                        18
+  #define MSEM_REG_INT_STS_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5                                              (0x1<<19) // Storm B non_aligned_access_attn interrupt
+  #define MSEM_REG_INT_STS_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5_SHIFT                                        19
+  #define MSEM_REG_INT_STS_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5                                                (0x1<<20) // Storm A division_by_zero_attn interrupt
+  #define MSEM_REG_INT_STS_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5_SHIFT                                          20
+  #define MSEM_REG_INT_STS_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5                                                (0x1<<21) // Storm B division_by_zero_attn interrupt
+  #define MSEM_REG_INT_STS_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5_SHIFT                                          21
+  #define MSEM_REG_INT_STS_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5                                           (0x1<<22) // Storm A illegal_runtime_value_attn interrupt
+  #define MSEM_REG_INT_STS_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5_SHIFT                                     22
+  #define MSEM_REG_INT_STS_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5                                           (0x1<<23) // Storm B illegal_runtime_value_attn interrupt
+  #define MSEM_REG_INT_STS_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5_SHIFT                                     23
+  #define MSEM_REG_INT_STS_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5                                            (0x1<<24) // load request is made while previous is still active; not fully read, Storm A
+  #define MSEM_REG_INT_STS_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5_SHIFT                                      24
+  #define MSEM_REG_INT_STS_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5                                            (0x1<<25) // load request is made while previous is still active; not fully read, Storm B
+  #define MSEM_REG_INT_STS_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5_SHIFT                                      25
+  #define MSEM_REG_INT_STS_1_CAM_RBC_FAST_OUT_ERROR_A_E5                                                     (0x1<<26) // Error in CAM_OUT fifo in cam block of STORM A
+  #define MSEM_REG_INT_STS_1_CAM_RBC_FAST_OUT_ERROR_A_E5_SHIFT                                               26
+  #define MSEM_REG_INT_STS_1_CAM_RBC_FAST_OUT_ERROR_B_E5                                                     (0x1<<27) // Error in CAM_OUT fifo in cam block of STORM B
+  #define MSEM_REG_INT_STS_1_CAM_RBC_FAST_OUT_ERROR_B_E5_SHIFT                                               27
+  #define MSEM_REG_INT_STS_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5                                                 (0x1<<28) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define MSEM_REG_INT_STS_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5_SHIFT                                           28
+  #define MSEM_REG_INT_STS_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5                                                 (0x1<<29) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define MSEM_REG_INT_STS_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5_SHIFT                                           29
+  #define MSEM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5                                                 (0x1<<30) // Error in CAM_LSB_INP fifo in cam block of STORM A
+  #define MSEM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT                                           30
+  #define MSEM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5                                                 (0x1<<31) // Error in CAM_LSB_INP fifo in cam block of STORM B.
+  #define MSEM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5_SHIFT                                           31
+  #define MSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_BB_K2                                                       (0x1<<0) // An underflow error was detected in the Storm stack.
+  #define MSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_BB_K2_SHIFT                                                 0
+  #define MSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_BB_K2                                                       (0x1<<1) // An overflow error was detected in the Storm stack.
+  #define MSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT                                                 1
+  #define MSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR_BB_K2                                                       (0x1<<2) // The Storm detected an illegal runtime value.
+  #define MSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR_BB_K2_SHIFT                                                 2
+  #define MSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR_BB_K2                                                    (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
+  #define MSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT                                              3
+  #define MSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR_BB_K2                                                     (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
+  #define MSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR_BB_K2_SHIFT                                               4
+  #define MSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR_BB_K2                                                     (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
+  #define MSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR_BB_K2_SHIFT                                               5
+  #define MSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR_BB_K2                                                      (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
+  #define MSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR_BB_K2_SHIFT                                                6
+  #define MSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR_BB_K2                                                      (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define MSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT                                                7
+  #define MSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR_BB_K2                                                         (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
+  #define MSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT                                                   8
+  #define MSEM_REG_INT_STS_1_INVLD_FOC_ERROR_BB_K2                                                           (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
+  #define MSEM_REG_INT_STS_1_INVLD_FOC_ERROR_BB_K2_SHIFT                                                     9
+  #define MSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR_BB_K2                                                          (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define MSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR_BB_K2_SHIFT                                                    10
+  #define MSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR_BB_K2                                                       (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
+  #define MSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR_BB_K2_SHIFT                                                 11
+  #define MSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR_BB_K2                                                      (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
+  #define MSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR_BB_K2_SHIFT                                                12
+#define MSEM_REG_INT_MASK_1                                                                                  0x1800054UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define MSEM_REG_INT_MASK_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5                                             (0x1<<0) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.RBC_COMMON_ACCESS_COL_VFC_ERROR .
+  #define MSEM_REG_INT_MASK_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5_SHIFT                                       0
+  #define MSEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_A_E5                                                 (0x1<<1) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.FAST_EXT_STORE_PUSH_ERROR_A .
+  #define MSEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT                                           1
+  #define MSEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_B_E5                                                 (0x1<<2) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.FAST_EXT_STORE_PUSH_ERROR_B .
+  #define MSEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_B_E5_SHIFT                                           2
+  #define MSEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_A_E5                                                   (0x1<<3) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.FAST_EXT_LOAD_POP_ERROR_A .
+  #define MSEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT                                             3
+  #define MSEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_B_E5                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.FAST_EXT_LOAD_POP_ERROR_B .
+  #define MSEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_B_E5_SHIFT                                             4
+  #define MSEM_REG_INT_MASK_1_FAST_RAM_WR_POP_ERROR_E5                                                       (0x1<<5) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.FAST_RAM_WR_POP_ERROR .
+  #define MSEM_REG_INT_MASK_1_FAST_RAM_WR_POP_ERROR_E5_SHIFT                                                 5
+  #define MSEM_REG_INT_MASK_1_FAST_RAM_RD_PUSH_ERROR_E5                                                      (0x1<<6) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.FAST_RAM_RD_PUSH_ERROR .
+  #define MSEM_REG_INT_MASK_1_FAST_RAM_RD_PUSH_ERROR_E5_SHIFT                                                6
+  #define MSEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_A_E5                                                    (0x1<<7) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.FAST_DRA_RD_PUSH_ERROR_A .
+  #define MSEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT                                              7
+  #define MSEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_B_E5                                                    (0x1<<8) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.FAST_DRA_RD_PUSH_ERROR_B .
+  #define MSEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT                                              8
+  #define MSEM_REG_INT_MASK_1_FAST_DRA_WR_POP_ERROR_A_E5                                                     (0x1<<9) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.FAST_DRA_WR_POP_ERROR_A .
+  #define MSEM_REG_INT_MASK_1_FAST_DRA_WR_POP_ERROR_A_E5_SHIFT                                               9
+  #define MSEM_REG_INT_MASK_1_FAST_DRA_WR_POP_ERROR_B_E5                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.FAST_DRA_WR_POP_ERROR_B .
+  #define MSEM_REG_INT_MASK_1_FAST_DRA_WR_POP_ERROR_B_E5_SHIFT                                               10
+  #define MSEM_REG_INT_MASK_1_SEM_FAST_INVLD_ADDR_ERR_E5                                                     (0x1<<11) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.SEM_FAST_INVLD_ADDR_ERR .
+  #define MSEM_REG_INT_MASK_1_SEM_FAST_INVLD_ADDR_ERR_E5_SHIFT                                               11
+  #define MSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_A_E5                                                       (0x1<<12) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN_A .
+  #define MSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_A_E5_SHIFT                                                 12
+  #define MSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_B_E5                                                       (0x1<<13) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN_B .
+  #define MSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_B_E5_SHIFT                                                 13
+  #define MSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_A_E5                                                       (0x1<<14) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN_A .
+  #define MSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_A_E5_SHIFT                                                 14
+  #define MSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_B_E5                                                       (0x1<<15) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN_B .
+  #define MSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_B_E5_SHIFT                                                 15
+  #define MSEM_REG_INT_MASK_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5                                                (0x1<<16) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.STORM_LDST_ADDR_OVFLW_ATTN_A .
+  #define MSEM_REG_INT_MASK_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5_SHIFT                                          16
+  #define MSEM_REG_INT_MASK_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5                                                (0x1<<17) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.STORM_LDST_ADDR_OVFLW_ATTN_B .
+  #define MSEM_REG_INT_MASK_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5_SHIFT                                          17
+  #define MSEM_REG_INT_MASK_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5                                             (0x1<<18) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.STORM_NON_ALIGNED_ACCESS_ATTN_A .
+  #define MSEM_REG_INT_MASK_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5_SHIFT                                       18
+  #define MSEM_REG_INT_MASK_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5                                             (0x1<<19) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.STORM_NON_ALIGNED_ACCESS_ATTN_B .
+  #define MSEM_REG_INT_MASK_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5_SHIFT                                       19
+  #define MSEM_REG_INT_MASK_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5                                               (0x1<<20) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.STORM_DIVISION_BY_ZERO_ATTN_A .
+  #define MSEM_REG_INT_MASK_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5_SHIFT                                         20
+  #define MSEM_REG_INT_MASK_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5                                               (0x1<<21) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.STORM_DIVISION_BY_ZERO_ATTN_B .
+  #define MSEM_REG_INT_MASK_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5_SHIFT                                         21
+  #define MSEM_REG_INT_MASK_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5                                          (0x1<<22) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A .
+  #define MSEM_REG_INT_MASK_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5_SHIFT                                    22
+  #define MSEM_REG_INT_MASK_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5                                          (0x1<<23) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B .
+  #define MSEM_REG_INT_MASK_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5_SHIFT                                    23
+  #define MSEM_REG_INT_MASK_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5                                           (0x1<<24) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A .
+  #define MSEM_REG_INT_MASK_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5_SHIFT                                     24
+  #define MSEM_REG_INT_MASK_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5                                           (0x1<<25) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B .
+  #define MSEM_REG_INT_MASK_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5_SHIFT                                     25
+  #define MSEM_REG_INT_MASK_1_CAM_RBC_FAST_OUT_ERROR_A_E5                                                    (0x1<<26) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.CAM_RBC_FAST_OUT_ERROR_A .
+  #define MSEM_REG_INT_MASK_1_CAM_RBC_FAST_OUT_ERROR_A_E5_SHIFT                                              26
+  #define MSEM_REG_INT_MASK_1_CAM_RBC_FAST_OUT_ERROR_B_E5                                                    (0x1<<27) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.CAM_RBC_FAST_OUT_ERROR_B .
+  #define MSEM_REG_INT_MASK_1_CAM_RBC_FAST_OUT_ERROR_B_E5_SHIFT                                              27
+  #define MSEM_REG_INT_MASK_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5                                                (0x1<<28) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.CAM_RBC_FAST_MSB_INP_ERROR_A .
+  #define MSEM_REG_INT_MASK_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5_SHIFT                                          28
+  #define MSEM_REG_INT_MASK_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5                                                (0x1<<29) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.CAM_RBC_FAST_MSB_INP_ERROR_B .
+  #define MSEM_REG_INT_MASK_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5_SHIFT                                          29
+  #define MSEM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5                                                (0x1<<30) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.CAM_RBC_FAST_LSB_INP_ERROR_A .
+  #define MSEM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT                                          30
+  #define MSEM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5                                                (0x1<<31) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.CAM_RBC_FAST_LSB_INP_ERROR_B .
+  #define MSEM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5_SHIFT                                          31
+  #define MSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_BB_K2                                                      (0x1<<0) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN .
+  #define MSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_BB_K2_SHIFT                                                0
+  #define MSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_BB_K2                                                      (0x1<<1) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN .
+  #define MSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT                                                1
+  #define MSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR_BB_K2                                                      (0x1<<2) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.STORM_RUNTIME_ERROR .
+  #define MSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR_BB_K2_SHIFT                                                2
+  #define MSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR_BB_K2                                                   (0x1<<3) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.EXT_LOAD_PEND_WR_ERROR .
+  #define MSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT                                             3
+  #define MSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR_BB_K2                                                    (0x1<<4) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.THREAD_RLS_ORUN_ERROR .
+  #define MSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR_BB_K2_SHIFT                                              4
+  #define MSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR_BB_K2                                                    (0x1<<5) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.THREAD_RLS_ALOC_ERROR .
+  #define MSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR_BB_K2_SHIFT                                              5
+  #define MSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR_BB_K2                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.THREAD_RLS_VLD_ERROR .
+  #define MSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR_BB_K2_SHIFT                                               6
+  #define MSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR_BB_K2                                                     (0x1<<7) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.EXT_THREAD_OOR_ERROR .
+  #define MSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT                                               7
+  #define MSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR_BB_K2                                                        (0x1<<8) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.ORD_ID_FIFO_ERROR .
+  #define MSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT                                                  8
+  #define MSEM_REG_INT_MASK_1_INVLD_FOC_ERROR_BB_K2                                                          (0x1<<9) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.INVLD_FOC_ERROR .
+  #define MSEM_REG_INT_MASK_1_INVLD_FOC_ERROR_BB_K2_SHIFT                                                    9
+  #define MSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR_BB_K2                                                         (0x1<<10) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.EXT_LD_LEN_ERROR .
+  #define MSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR_BB_K2_SHIFT                                                   10
+  #define MSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR_BB_K2                                                      (0x1<<11) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.THRD_ORD_FIFO_ERROR .
+  #define MSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR_BB_K2_SHIFT                                                11
+  #define MSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR_BB_K2                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.INVLD_THRD_ORD_ERROR .
+  #define MSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR_BB_K2_SHIFT                                               12
+#define MSEM_REG_INT_STS_WR_1                                                                                0x1800058UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define MSEM_REG_INT_STS_WR_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5                                           (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
+  #define MSEM_REG_INT_STS_WR_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5_SHIFT                                     0
+  #define MSEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5                                               (0x1<<1) // Fast external store FIFO error of Storm_A
+  #define MSEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT                                         1
+  #define MSEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_B_E5                                               (0x1<<2) // Fast external store FIFO error of Storm_B
+  #define MSEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_B_E5_SHIFT                                         2
+  #define MSEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_A_E5                                                 (0x1<<3) // fast external load FIFO error of Storm_A
+  #define MSEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT                                           3
+  #define MSEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_B_E5                                                 (0x1<<4) // fast external load FIFO error of Storm_B
+  #define MSEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_B_E5_SHIFT                                           4
+  #define MSEM_REG_INT_STS_WR_1_FAST_RAM_WR_POP_ERROR_E5                                                     (0x1<<5) // Internal RAM pop error
+  #define MSEM_REG_INT_STS_WR_1_FAST_RAM_WR_POP_ERROR_E5_SHIFT                                               5
+  #define MSEM_REG_INT_STS_WR_1_FAST_RAM_RD_PUSH_ERROR_E5                                                    (0x1<<6) // Internal RAM write error
+  #define MSEM_REG_INT_STS_WR_1_FAST_RAM_RD_PUSH_ERROR_E5_SHIFT                                              6
+  #define MSEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_A_E5                                                  (0x1<<7) // DRA RD FIFO error of Storm A
+  #define MSEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT                                            7
+  #define MSEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_B_E5                                                  (0x1<<8) // DRA RD FIFO error of Storm B
+  #define MSEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT                                            8
+  #define MSEM_REG_INT_STS_WR_1_FAST_DRA_WR_POP_ERROR_A_E5                                                   (0x1<<9) // DRA RD FIFO error of Storm A
+  #define MSEM_REG_INT_STS_WR_1_FAST_DRA_WR_POP_ERROR_A_E5_SHIFT                                             9
+  #define MSEM_REG_INT_STS_WR_1_FAST_DRA_WR_POP_ERROR_B_E5                                                   (0x1<<10) // DRA RD FIFO error of Storm B
+  #define MSEM_REG_INT_STS_WR_1_FAST_DRA_WR_POP_ERROR_B_E5_SHIFT                                             10
+  #define MSEM_REG_INT_STS_WR_1_SEM_FAST_INVLD_ADDR_ERR_E5                                                   (0x1<<11) // Fast invalid address error
+  #define MSEM_REG_INT_STS_WR_1_SEM_FAST_INVLD_ADDR_ERR_E5_SHIFT                                             11
+  #define MSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_A_E5                                                     (0x1<<12) // Storm A stack_uf_attn interrupt
+  #define MSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_A_E5_SHIFT                                               12
+  #define MSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_B_E5                                                     (0x1<<13) // Storm B stack_uf_attn interrupt
+  #define MSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_B_E5_SHIFT                                               13
+  #define MSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_A_E5                                                     (0x1<<14) // Storm A stack_of_attn interrupt
+  #define MSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_A_E5_SHIFT                                               14
+  #define MSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_B_E5                                                     (0x1<<15) // Storm B stack_of_attn interrupt
+  #define MSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_B_E5_SHIFT                                               15
+  #define MSEM_REG_INT_STS_WR_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5                                              (0x1<<16) // Storm A ldst_addr_ovflw_attn interrupt
+  #define MSEM_REG_INT_STS_WR_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5_SHIFT                                        16
+  #define MSEM_REG_INT_STS_WR_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5                                              (0x1<<17) // Storm B ldst_addr_ovflw_attn interrupt
+  #define MSEM_REG_INT_STS_WR_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5_SHIFT                                        17
+  #define MSEM_REG_INT_STS_WR_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5                                           (0x1<<18) // Storm A non_aligned_access_attn interrupt
+  #define MSEM_REG_INT_STS_WR_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5_SHIFT                                     18
+  #define MSEM_REG_INT_STS_WR_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5                                           (0x1<<19) // Storm B non_aligned_access_attn interrupt
+  #define MSEM_REG_INT_STS_WR_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5_SHIFT                                     19
+  #define MSEM_REG_INT_STS_WR_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5                                             (0x1<<20) // Storm A division_by_zero_attn interrupt
+  #define MSEM_REG_INT_STS_WR_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5_SHIFT                                       20
+  #define MSEM_REG_INT_STS_WR_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5                                             (0x1<<21) // Storm B division_by_zero_attn interrupt
+  #define MSEM_REG_INT_STS_WR_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5_SHIFT                                       21
+  #define MSEM_REG_INT_STS_WR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5                                        (0x1<<22) // Storm A illegal_runtime_value_attn interrupt
+  #define MSEM_REG_INT_STS_WR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5_SHIFT                                  22
+  #define MSEM_REG_INT_STS_WR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5                                        (0x1<<23) // Storm B illegal_runtime_value_attn interrupt
+  #define MSEM_REG_INT_STS_WR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5_SHIFT                                  23
+  #define MSEM_REG_INT_STS_WR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5                                         (0x1<<24) // load request is made while previous is still active; not fully read, Storm A
+  #define MSEM_REG_INT_STS_WR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5_SHIFT                                   24
+  #define MSEM_REG_INT_STS_WR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5                                         (0x1<<25) // load request is made while previous is still active; not fully read, Storm B
+  #define MSEM_REG_INT_STS_WR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5_SHIFT                                   25
+  #define MSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_OUT_ERROR_A_E5                                                  (0x1<<26) // Error in CAM_OUT fifo in cam block of STORM A
+  #define MSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_OUT_ERROR_A_E5_SHIFT                                            26
+  #define MSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_OUT_ERROR_B_E5                                                  (0x1<<27) // Error in CAM_OUT fifo in cam block of STORM B
+  #define MSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_OUT_ERROR_B_E5_SHIFT                                            27
+  #define MSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5                                              (0x1<<28) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define MSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5_SHIFT                                        28
+  #define MSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5                                              (0x1<<29) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define MSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5_SHIFT                                        29
+  #define MSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5                                              (0x1<<30) // Error in CAM_LSB_INP fifo in cam block of STORM A
+  #define MSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT                                        30
+  #define MSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5                                              (0x1<<31) // Error in CAM_LSB_INP fifo in cam block of STORM B.
+  #define MSEM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5_SHIFT                                        31
+  #define MSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_BB_K2                                                    (0x1<<0) // An underflow error was detected in the Storm stack.
+  #define MSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_BB_K2_SHIFT                                              0
+  #define MSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_BB_K2                                                    (0x1<<1) // An overflow error was detected in the Storm stack.
+  #define MSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT                                              1
+  #define MSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR_BB_K2                                                    (0x1<<2) // The Storm detected an illegal runtime value.
+  #define MSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR_BB_K2_SHIFT                                              2
+  #define MSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2                                                 (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
+  #define MSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT                                           3
+  #define MSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR_BB_K2                                                  (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
+  #define MSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR_BB_K2_SHIFT                                            4
+  #define MSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR_BB_K2                                                  (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
+  #define MSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR_BB_K2_SHIFT                                            5
+  #define MSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR_BB_K2                                                   (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
+  #define MSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR_BB_K2_SHIFT                                             6
+  #define MSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR_BB_K2                                                   (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define MSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT                                             7
+  #define MSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR_BB_K2                                                      (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
+  #define MSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT                                                8
+  #define MSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR_BB_K2                                                        (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
+  #define MSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR_BB_K2_SHIFT                                                  9
+  #define MSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR_BB_K2                                                       (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define MSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR_BB_K2_SHIFT                                                 10
+  #define MSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR_BB_K2                                                    (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
+  #define MSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR_BB_K2_SHIFT                                              11
+  #define MSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR_BB_K2                                                   (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
+  #define MSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR_BB_K2_SHIFT                                             12
+#define MSEM_REG_INT_STS_CLR_1                                                                               0x180005cUL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define MSEM_REG_INT_STS_CLR_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5                                          (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
+  #define MSEM_REG_INT_STS_CLR_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5_SHIFT                                    0
+  #define MSEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5                                              (0x1<<1) // Fast external store FIFO error of Storm_A
+  #define MSEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT                                        1
+  #define MSEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_B_E5                                              (0x1<<2) // Fast external store FIFO error of Storm_B
+  #define MSEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_B_E5_SHIFT                                        2
+  #define MSEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_A_E5                                                (0x1<<3) // fast external load FIFO error of Storm_A
+  #define MSEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT                                          3
+  #define MSEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_B_E5                                                (0x1<<4) // fast external load FIFO error of Storm_B
+  #define MSEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_B_E5_SHIFT                                          4
+  #define MSEM_REG_INT_STS_CLR_1_FAST_RAM_WR_POP_ERROR_E5                                                    (0x1<<5) // Internal RAM pop error
+  #define MSEM_REG_INT_STS_CLR_1_FAST_RAM_WR_POP_ERROR_E5_SHIFT                                              5
+  #define MSEM_REG_INT_STS_CLR_1_FAST_RAM_RD_PUSH_ERROR_E5                                                   (0x1<<6) // Internal RAM write error
+  #define MSEM_REG_INT_STS_CLR_1_FAST_RAM_RD_PUSH_ERROR_E5_SHIFT                                             6
+  #define MSEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_A_E5                                                 (0x1<<7) // DRA RD FIFO error of Storm A
+  #define MSEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT                                           7
+  #define MSEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_B_E5                                                 (0x1<<8) // DRA RD FIFO error of Storm B
+  #define MSEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT                                           8
+  #define MSEM_REG_INT_STS_CLR_1_FAST_DRA_WR_POP_ERROR_A_E5                                                  (0x1<<9) // DRA RD FIFO error of Storm A
+  #define MSEM_REG_INT_STS_CLR_1_FAST_DRA_WR_POP_ERROR_A_E5_SHIFT                                            9
+  #define MSEM_REG_INT_STS_CLR_1_FAST_DRA_WR_POP_ERROR_B_E5                                                  (0x1<<10) // DRA RD FIFO error of Storm B
+  #define MSEM_REG_INT_STS_CLR_1_FAST_DRA_WR_POP_ERROR_B_E5_SHIFT                                            10
+  #define MSEM_REG_INT_STS_CLR_1_SEM_FAST_INVLD_ADDR_ERR_E5                                                  (0x1<<11) // Fast invalid address error
+  #define MSEM_REG_INT_STS_CLR_1_SEM_FAST_INVLD_ADDR_ERR_E5_SHIFT                                            11
+  #define MSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_A_E5                                                    (0x1<<12) // Storm A stack_uf_attn interrupt
+  #define MSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_A_E5_SHIFT                                              12
+  #define MSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_B_E5                                                    (0x1<<13) // Storm B stack_uf_attn interrupt
+  #define MSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_B_E5_SHIFT                                              13
+  #define MSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_A_E5                                                    (0x1<<14) // Storm A stack_of_attn interrupt
+  #define MSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_A_E5_SHIFT                                              14
+  #define MSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_B_E5                                                    (0x1<<15) // Storm B stack_of_attn interrupt
+  #define MSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_B_E5_SHIFT                                              15
+  #define MSEM_REG_INT_STS_CLR_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5                                             (0x1<<16) // Storm A ldst_addr_ovflw_attn interrupt
+  #define MSEM_REG_INT_STS_CLR_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5_SHIFT                                       16
+  #define MSEM_REG_INT_STS_CLR_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5                                             (0x1<<17) // Storm B ldst_addr_ovflw_attn interrupt
+  #define MSEM_REG_INT_STS_CLR_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5_SHIFT                                       17
+  #define MSEM_REG_INT_STS_CLR_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5                                          (0x1<<18) // Storm A non_aligned_access_attn interrupt
+  #define MSEM_REG_INT_STS_CLR_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5_SHIFT                                    18
+  #define MSEM_REG_INT_STS_CLR_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5                                          (0x1<<19) // Storm B non_aligned_access_attn interrupt
+  #define MSEM_REG_INT_STS_CLR_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5_SHIFT                                    19
+  #define MSEM_REG_INT_STS_CLR_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5                                            (0x1<<20) // Storm A division_by_zero_attn interrupt
+  #define MSEM_REG_INT_STS_CLR_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5_SHIFT                                      20
+  #define MSEM_REG_INT_STS_CLR_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5                                            (0x1<<21) // Storm B division_by_zero_attn interrupt
+  #define MSEM_REG_INT_STS_CLR_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5_SHIFT                                      21
+  #define MSEM_REG_INT_STS_CLR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5                                       (0x1<<22) // Storm A illegal_runtime_value_attn interrupt
+  #define MSEM_REG_INT_STS_CLR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5_SHIFT                                 22
+  #define MSEM_REG_INT_STS_CLR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5                                       (0x1<<23) // Storm B illegal_runtime_value_attn interrupt
+  #define MSEM_REG_INT_STS_CLR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5_SHIFT                                 23
+  #define MSEM_REG_INT_STS_CLR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5                                        (0x1<<24) // load request is made while previous is still active; not fully read, Storm A
+  #define MSEM_REG_INT_STS_CLR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5_SHIFT                                  24
+  #define MSEM_REG_INT_STS_CLR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5                                        (0x1<<25) // load request is made while previous is still active; not fully read, Storm B
+  #define MSEM_REG_INT_STS_CLR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5_SHIFT                                  25
+  #define MSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_OUT_ERROR_A_E5                                                 (0x1<<26) // Error in CAM_OUT fifo in cam block of STORM A
+  #define MSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_OUT_ERROR_A_E5_SHIFT                                           26
+  #define MSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_OUT_ERROR_B_E5                                                 (0x1<<27) // Error in CAM_OUT fifo in cam block of STORM B
+  #define MSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_OUT_ERROR_B_E5_SHIFT                                           27
+  #define MSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5                                             (0x1<<28) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define MSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5_SHIFT                                       28
+  #define MSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5                                             (0x1<<29) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define MSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5_SHIFT                                       29
+  #define MSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5                                             (0x1<<30) // Error in CAM_LSB_INP fifo in cam block of STORM A
+  #define MSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT                                       30
+  #define MSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5                                             (0x1<<31) // Error in CAM_LSB_INP fifo in cam block of STORM B.
+  #define MSEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5_SHIFT                                       31
+  #define MSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_BB_K2                                                   (0x1<<0) // An underflow error was detected in the Storm stack.
+  #define MSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_BB_K2_SHIFT                                             0
+  #define MSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_BB_K2                                                   (0x1<<1) // An overflow error was detected in the Storm stack.
+  #define MSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT                                             1
+  #define MSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR_BB_K2                                                   (0x1<<2) // The Storm detected an illegal runtime value.
+  #define MSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR_BB_K2_SHIFT                                             2
+  #define MSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2                                                (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
+  #define MSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT                                          3
+  #define MSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR_BB_K2                                                 (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
+  #define MSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR_BB_K2_SHIFT                                           4
+  #define MSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR_BB_K2                                                 (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
+  #define MSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR_BB_K2_SHIFT                                           5
+  #define MSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR_BB_K2                                                  (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
+  #define MSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR_BB_K2_SHIFT                                            6
+  #define MSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR_BB_K2                                                  (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define MSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT                                            7
+  #define MSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR_BB_K2                                                     (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
+  #define MSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT                                               8
+  #define MSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR_BB_K2                                                       (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
+  #define MSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR_BB_K2_SHIFT                                                 9
+  #define MSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR_BB_K2                                                      (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define MSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR_BB_K2_SHIFT                                                10
+  #define MSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR_BB_K2                                                   (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
+  #define MSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR_BB_K2_SHIFT                                             11
+  #define MSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR_BB_K2                                                  (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
+  #define MSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR_BB_K2_SHIFT                                            12
+#define MSEM_REG_INT_STS_2_E5                                                                                0x1800060UL //Access:R    DataWidth:0x1f   // Multi Field Register.
+  #define MSEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5                                                 (0x1<<0) // Fast FIN FIFO error of Storm A.
+  #define MSEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5_SHIFT                                           0
+  #define MSEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5                                                 (0x1<<1) // Fast FIN FIFO error of Storm B
+  #define MSEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT                                           1
+  #define MSEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5                                               (0x1<<2) // Fast Debug FIFO error of Storm A
+  #define MSEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5_SHIFT                                         2
+  #define MSEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5                                               (0x1<<3) // Fast Debug FIFO error of Storm B
+  #define MSEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT                                         3
+  #define MSEM_REG_INT_STS_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5                                                (0x1<<4) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define MSEM_REG_INT_STS_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5_SHIFT                                          4
+  #define MSEM_REG_INT_STS_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5                                                (0x1<<5) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define MSEM_REG_INT_STS_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5_SHIFT                                          5
+  #define MSEM_REG_INT_STS_2_VFC_INTERRUPT_E5                                                                (0x1<<6) // interrupt from VFC block
+  #define MSEM_REG_INT_STS_2_VFC_INTERRUPT_E5_SHIFT                                                          6
+  #define MSEM_REG_INT_STS_2_MUX_RBC_VFC_FIFO_ERROR_E5                                                       (0x1<<7) // VFC FIFO error
+  #define MSEM_REG_INT_STS_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT                                                 7
+  #define MSEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_A_E5                                                    (0x1<<8) // Error in FOC error of Storm A.
+  #define MSEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT                                              8
+  #define MSEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_B_E5                                                    (0x1<<9) // Error in FOC error of Storm B.
+  #define MSEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_B_E5_SHIFT                                              9
+  #define MSEM_REG_INT_STS_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5                                                  (0x1<<10) // Invalid allocated thread request with partial FIN of Storm A.
+  #define MSEM_REG_INT_STS_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5_SHIFT                                            10
+  #define MSEM_REG_INT_STS_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5                                                  (0x1<<11) // Invalid allocated thread request with partial FIN of Storm B.
+  #define MSEM_REG_INT_STS_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5_SHIFT                                            11
+  #define MSEM_REG_INT_STS_2_CAM_RBC_INPUT_FIFO_ERROR_E5                                                     (0x1<<12) // Cam input FIFO error
+  #define MSEM_REG_INT_STS_2_CAM_RBC_INPUT_FIFO_ERROR_E5_SHIFT                                               12
+  #define MSEM_REG_INT_STS_2_ARB_RBC_FIFO_ERROR_A_E5                                                         (0x1<<13) // Pre-fetch FIFO error of Storm A.
+  #define MSEM_REG_INT_STS_2_ARB_RBC_FIFO_ERROR_A_E5_SHIFT                                                   13
+  #define MSEM_REG_INT_STS_2_ARB_RBC_FIFO_ERROR_B_E5                                                         (0x1<<14) // Pre-fetch FIFO error of Storm B.
+  #define MSEM_REG_INT_STS_2_ARB_RBC_FIFO_ERROR_B_E5_SHIFT                                                   14
+  #define MSEM_REG_INT_STS_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5                                                 (0x1<<15) // Lock is acquired more than maximum configured time.
+  #define MSEM_REG_INT_STS_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5_SHIFT                                           15
+  #define MSEM_REG_INT_STS_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                                  (0x1<<16) // Ilegal assetion commands towards lock block.
+  #define MSEM_REG_INT_STS_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5_SHIFT                                            16
+  #define MSEM_REG_INT_STS_2_LOCK_RBC_REQ_RELEASE_ERROR_E5                                                   (0x1<<17) // Error when trying to release a lock which is not acquired (key does not match any lock)
+  #define MSEM_REG_INT_STS_2_LOCK_RBC_REQ_RELEASE_ERROR_E5_SHIFT                                             17
+  #define MSEM_REG_INT_STS_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5                                                 (0x1<<18) // Trying to acquire a lock which is already acquired.
+  #define MSEM_REG_INT_STS_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5_SHIFT                                           18
+  #define MSEM_REG_INT_STS_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5                                                (0x1<<19) // Trying to relinquish a key which does not exist.
+  #define MSEM_REG_INT_STS_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5_SHIFT                                          19
+  #define MSEM_REG_INT_STS_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5                                                (0x1<<20) // A lock acquired requrest is issued when all locks are used.
+  #define MSEM_REG_INT_STS_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5_SHIFT                                          20
+  #define MSEM_REG_INT_STS_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5                                                (0x1<<21) // Error when both Storm are stalled due to lock block (may indicate a dead lock).
+  #define MSEM_REG_INT_STS_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5_SHIFT                                          21
+  #define MSEM_REG_INT_STS_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5                                            (0x1<<22) // Fin done with remainning allocated threads STORM_A.
+  #define MSEM_REG_INT_STS_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5_SHIFT                                      22
+  #define MSEM_REG_INT_STS_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5                                            (0x1<<23) // Fin done with remainning allocated threads STORM_B.
+  #define MSEM_REG_INT_STS_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5_SHIFT                                      23
+  #define MSEM_REG_INT_STS_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5                                            (0x1<<24) // Fin new thread request when no thread is allocated for handler of Storm A.
+  #define MSEM_REG_INT_STS_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5_SHIFT                                      24
+  #define MSEM_REG_INT_STS_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5                                            (0x1<<25) // Fin new thread request when no thread is allocated for handler of Storm B.
+  #define MSEM_REG_INT_STS_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5_SHIFT                                      25
+  #define MSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5                                      (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same range.
+  #define MSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5_SHIFT                                26
+  #define MSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5                                      (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same range.
+  #define MSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5_SHIFT                                27
+  #define MSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5                                         (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
+  #define MSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5_SHIFT                                   28
+  #define MSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5                                         (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
+  #define MSEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5_SHIFT                                   29
+  #define MSEM_REG_INT_STS_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5                                          (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
+  #define MSEM_REG_INT_STS_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT                                    30
+#define MSEM_REG_INT_MASK_2_E5                                                                               0x1800064UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define MSEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5                                                (0x1<<0) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.RD_RBC_FAST_FIN_FIFO_ERROR_A .
+  #define MSEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5_SHIFT                                          0
+  #define MSEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5                                                (0x1<<1) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.RD_RBC_FAST_FIN_FIFO_ERROR_B .
+  #define MSEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT                                          1
+  #define MSEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5                                              (0x1<<2) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.SYNC_RBC_FAST_DBG_PUSH_ERROR_A .
+  #define MSEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5_SHIFT                                        2
+  #define MSEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5                                              (0x1<<3) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.SYNC_RBC_FAST_DBG_PUSH_ERROR_B .
+  #define MSEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT                                        3
+  #define MSEM_REG_INT_MASK_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5                                               (0x1<<4) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.CAM_RBC_FAST_MSB2_INP_ERROR_A .
+  #define MSEM_REG_INT_MASK_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5_SHIFT                                         4
+  #define MSEM_REG_INT_MASK_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5                                               (0x1<<5) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.CAM_RBC_FAST_MSB2_INP_ERROR_B .
+  #define MSEM_REG_INT_MASK_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5_SHIFT                                         5
+  #define MSEM_REG_INT_MASK_2_VFC_INTERRUPT_E5                                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.VFC_INTERRUPT .
+  #define MSEM_REG_INT_MASK_2_VFC_INTERRUPT_E5_SHIFT                                                         6
+  #define MSEM_REG_INT_MASK_2_MUX_RBC_VFC_FIFO_ERROR_E5                                                      (0x1<<7) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.MUX_RBC_VFC_FIFO_ERROR .
+  #define MSEM_REG_INT_MASK_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT                                                7
+  #define MSEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_A_E5                                                   (0x1<<8) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.FIN_RBC_INVLD_FOC_ERROR_A .
+  #define MSEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT                                             8
+  #define MSEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_B_E5                                                   (0x1<<9) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.FIN_RBC_INVLD_FOC_ERROR_B .
+  #define MSEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_B_E5_SHIFT                                             9
+  #define MSEM_REG_INT_MASK_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5                                                 (0x1<<10) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.FIN_RBC_INVLD_ALLOC_ERROR_A .
+  #define MSEM_REG_INT_MASK_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5_SHIFT                                           10
+  #define MSEM_REG_INT_MASK_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5                                                 (0x1<<11) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.FIN_RBC_INVLD_ALLOC_ERROR_B .
+  #define MSEM_REG_INT_MASK_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5_SHIFT                                           11
+  #define MSEM_REG_INT_MASK_2_CAM_RBC_INPUT_FIFO_ERROR_E5                                                    (0x1<<12) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.CAM_RBC_INPUT_FIFO_ERROR .
+  #define MSEM_REG_INT_MASK_2_CAM_RBC_INPUT_FIFO_ERROR_E5_SHIFT                                              12
+  #define MSEM_REG_INT_MASK_2_ARB_RBC_FIFO_ERROR_A_E5                                                        (0x1<<13) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.ARB_RBC_FIFO_ERROR_A .
+  #define MSEM_REG_INT_MASK_2_ARB_RBC_FIFO_ERROR_A_E5_SHIFT                                                  13
+  #define MSEM_REG_INT_MASK_2_ARB_RBC_FIFO_ERROR_B_E5                                                        (0x1<<14) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.ARB_RBC_FIFO_ERROR_B .
+  #define MSEM_REG_INT_MASK_2_ARB_RBC_FIFO_ERROR_B_E5_SHIFT                                                  14
+  #define MSEM_REG_INT_MASK_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5                                                (0x1<<15) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.LOCK_RBC_REQ_MAX_STALL_ERROR .
+  #define MSEM_REG_INT_MASK_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5_SHIFT                                          15
+  #define MSEM_REG_INT_MASK_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                                 (0x1<<16) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.LOCK_RBC_REQ_CMD_RATE_ERROR .
+  #define MSEM_REG_INT_MASK_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5_SHIFT                                           16
+  #define MSEM_REG_INT_MASK_2_LOCK_RBC_REQ_RELEASE_ERROR_E5                                                  (0x1<<17) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.LOCK_RBC_REQ_RELEASE_ERROR .
+  #define MSEM_REG_INT_MASK_2_LOCK_RBC_REQ_RELEASE_ERROR_E5_SHIFT                                            17
+  #define MSEM_REG_INT_MASK_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5                                                (0x1<<18) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.LOCK_RBC_REQ_REDUNDENT_ERROR .
+  #define MSEM_REG_INT_MASK_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5_SHIFT                                          18
+  #define MSEM_REG_INT_MASK_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5                                               (0x1<<19) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.LOCK_RBC_REQ_RELINQUISH_ERROR .
+  #define MSEM_REG_INT_MASK_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5_SHIFT                                         19
+  #define MSEM_REG_INT_MASK_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5                                               (0x1<<20) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.LOCK_RBC_REQ_STALL_FULL_ERROR .
+  #define MSEM_REG_INT_MASK_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5_SHIFT                                         20
+  #define MSEM_REG_INT_MASK_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5                                               (0x1<<21) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.LOCK_RBC_REQ_DUAL_STALL_ERROR .
+  #define MSEM_REG_INT_MASK_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5_SHIFT                                         21
+  #define MSEM_REG_INT_MASK_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5                                           (0x1<<22) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A .
+  #define MSEM_REG_INT_MASK_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5_SHIFT                                     22
+  #define MSEM_REG_INT_MASK_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5                                           (0x1<<23) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B .
+  #define MSEM_REG_INT_MASK_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5_SHIFT                                     23
+  #define MSEM_REG_INT_MASK_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5                                           (0x1<<24) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.DRA_INT_GRC_NON_FREE_THRD_ERROR_A .
+  #define MSEM_REG_INT_MASK_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5_SHIFT                                     24
+  #define MSEM_REG_INT_MASK_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5                                           (0x1<<25) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.DRA_INT_GRC_NON_FREE_THRD_ERROR_B .
+  #define MSEM_REG_INT_MASK_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5_SHIFT                                     25
+  #define MSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5                                     (0x1<<26) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A .
+  #define MSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5_SHIFT                               26
+  #define MSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5                                     (0x1<<27) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B .
+  #define MSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5_SHIFT                               27
+  #define MSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5                                        (0x1<<28) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A .
+  #define MSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5_SHIFT                                  28
+  #define MSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5                                        (0x1<<29) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B .
+  #define MSEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5_SHIFT                                  29
+  #define MSEM_REG_INT_MASK_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5                                         (0x1<<30) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_2.SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR .
+  #define MSEM_REG_INT_MASK_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT                                   30
+#define MSEM_REG_INT_STS_WR_2_E5                                                                             0x1800068UL //Access:WR   DataWidth:0x1f   // Multi Field Register.
+  #define MSEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5                                              (0x1<<0) // Fast FIN FIFO error of Storm A.
+  #define MSEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5_SHIFT                                        0
+  #define MSEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5                                              (0x1<<1) // Fast FIN FIFO error of Storm B
+  #define MSEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT                                        1
+  #define MSEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5                                            (0x1<<2) // Fast Debug FIFO error of Storm A
+  #define MSEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5_SHIFT                                      2
+  #define MSEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5                                            (0x1<<3) // Fast Debug FIFO error of Storm B
+  #define MSEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT                                      3
+  #define MSEM_REG_INT_STS_WR_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5                                             (0x1<<4) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define MSEM_REG_INT_STS_WR_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5_SHIFT                                       4
+  #define MSEM_REG_INT_STS_WR_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5                                             (0x1<<5) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define MSEM_REG_INT_STS_WR_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5_SHIFT                                       5
+  #define MSEM_REG_INT_STS_WR_2_VFC_INTERRUPT_E5                                                             (0x1<<6) // interrupt from VFC block
+  #define MSEM_REG_INT_STS_WR_2_VFC_INTERRUPT_E5_SHIFT                                                       6
+  #define MSEM_REG_INT_STS_WR_2_MUX_RBC_VFC_FIFO_ERROR_E5                                                    (0x1<<7) // VFC FIFO error
+  #define MSEM_REG_INT_STS_WR_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT                                              7
+  #define MSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5                                                 (0x1<<8) // Error in FOC error of Storm A.
+  #define MSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT                                           8
+  #define MSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_B_E5                                                 (0x1<<9) // Error in FOC error of Storm B.
+  #define MSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_B_E5_SHIFT                                           9
+  #define MSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5                                               (0x1<<10) // Invalid allocated thread request with partial FIN of Storm A.
+  #define MSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5_SHIFT                                         10
+  #define MSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5                                               (0x1<<11) // Invalid allocated thread request with partial FIN of Storm B.
+  #define MSEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5_SHIFT                                         11
+  #define MSEM_REG_INT_STS_WR_2_CAM_RBC_INPUT_FIFO_ERROR_E5                                                  (0x1<<12) // Cam input FIFO error
+  #define MSEM_REG_INT_STS_WR_2_CAM_RBC_INPUT_FIFO_ERROR_E5_SHIFT                                            12
+  #define MSEM_REG_INT_STS_WR_2_ARB_RBC_FIFO_ERROR_A_E5                                                      (0x1<<13) // Pre-fetch FIFO error of Storm A.
+  #define MSEM_REG_INT_STS_WR_2_ARB_RBC_FIFO_ERROR_A_E5_SHIFT                                                13
+  #define MSEM_REG_INT_STS_WR_2_ARB_RBC_FIFO_ERROR_B_E5                                                      (0x1<<14) // Pre-fetch FIFO error of Storm B.
+  #define MSEM_REG_INT_STS_WR_2_ARB_RBC_FIFO_ERROR_B_E5_SHIFT                                                14
+  #define MSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5                                              (0x1<<15) // Lock is acquired more than maximum configured time.
+  #define MSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5_SHIFT                                        15
+  #define MSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                               (0x1<<16) // Ilegal assetion commands towards lock block.
+  #define MSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5_SHIFT                                         16
+  #define MSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_RELEASE_ERROR_E5                                                (0x1<<17) // Error when trying to release a lock which is not acquired (key does not match any lock)
+  #define MSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_RELEASE_ERROR_E5_SHIFT                                          17
+  #define MSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5                                              (0x1<<18) // Trying to acquire a lock which is already acquired.
+  #define MSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5_SHIFT                                        18
+  #define MSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5                                             (0x1<<19) // Trying to relinquish a key which does not exist.
+  #define MSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5_SHIFT                                       19
+  #define MSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5                                             (0x1<<20) // A lock acquired requrest is issued when all locks are used.
+  #define MSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5_SHIFT                                       20
+  #define MSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5                                             (0x1<<21) // Error when both Storm are stalled due to lock block (may indicate a dead lock).
+  #define MSEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5_SHIFT                                       21
+  #define MSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5                                         (0x1<<22) // Fin done with remainning allocated threads STORM_A.
+  #define MSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5_SHIFT                                   22
+  #define MSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5                                         (0x1<<23) // Fin done with remainning allocated threads STORM_B.
+  #define MSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5_SHIFT                                   23
+  #define MSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5                                         (0x1<<24) // Fin new thread request when no thread is allocated for handler of Storm A.
+  #define MSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5_SHIFT                                   24
+  #define MSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5                                         (0x1<<25) // Fin new thread request when no thread is allocated for handler of Storm B.
+  #define MSEM_REG_INT_STS_WR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5_SHIFT                                   25
+  #define MSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5                                   (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same range.
+  #define MSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5_SHIFT                             26
+  #define MSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5                                   (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same range.
+  #define MSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5_SHIFT                             27
+  #define MSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5                                      (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
+  #define MSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5_SHIFT                                28
+  #define MSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5                                      (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
+  #define MSEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5_SHIFT                                29
+  #define MSEM_REG_INT_STS_WR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5                                       (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
+  #define MSEM_REG_INT_STS_WR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT                                 30
+#define MSEM_REG_INT_STS_CLR_2_E5                                                                            0x180006cUL //Access:RC   DataWidth:0x1f   // Multi Field Register.
+  #define MSEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5                                             (0x1<<0) // Fast FIN FIFO error of Storm A.
+  #define MSEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5_SHIFT                                       0
+  #define MSEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5                                             (0x1<<1) // Fast FIN FIFO error of Storm B
+  #define MSEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT                                       1
+  #define MSEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5                                           (0x1<<2) // Fast Debug FIFO error of Storm A
+  #define MSEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5_SHIFT                                     2
+  #define MSEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5                                           (0x1<<3) // Fast Debug FIFO error of Storm B
+  #define MSEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT                                     3
+  #define MSEM_REG_INT_STS_CLR_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5                                            (0x1<<4) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define MSEM_REG_INT_STS_CLR_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5_SHIFT                                      4
+  #define MSEM_REG_INT_STS_CLR_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5                                            (0x1<<5) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define MSEM_REG_INT_STS_CLR_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5_SHIFT                                      5
+  #define MSEM_REG_INT_STS_CLR_2_VFC_INTERRUPT_E5                                                            (0x1<<6) // interrupt from VFC block
+  #define MSEM_REG_INT_STS_CLR_2_VFC_INTERRUPT_E5_SHIFT                                                      6
+  #define MSEM_REG_INT_STS_CLR_2_MUX_RBC_VFC_FIFO_ERROR_E5                                                   (0x1<<7) // VFC FIFO error
+  #define MSEM_REG_INT_STS_CLR_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT                                             7
+  #define MSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5                                                (0x1<<8) // Error in FOC error of Storm A.
+  #define MSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT                                          8
+  #define MSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_B_E5                                                (0x1<<9) // Error in FOC error of Storm B.
+  #define MSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_B_E5_SHIFT                                          9
+  #define MSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5                                              (0x1<<10) // Invalid allocated thread request with partial FIN of Storm A.
+  #define MSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5_SHIFT                                        10
+  #define MSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5                                              (0x1<<11) // Invalid allocated thread request with partial FIN of Storm B.
+  #define MSEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5_SHIFT                                        11
+  #define MSEM_REG_INT_STS_CLR_2_CAM_RBC_INPUT_FIFO_ERROR_E5                                                 (0x1<<12) // Cam input FIFO error
+  #define MSEM_REG_INT_STS_CLR_2_CAM_RBC_INPUT_FIFO_ERROR_E5_SHIFT                                           12
+  #define MSEM_REG_INT_STS_CLR_2_ARB_RBC_FIFO_ERROR_A_E5                                                     (0x1<<13) // Pre-fetch FIFO error of Storm A.
+  #define MSEM_REG_INT_STS_CLR_2_ARB_RBC_FIFO_ERROR_A_E5_SHIFT                                               13
+  #define MSEM_REG_INT_STS_CLR_2_ARB_RBC_FIFO_ERROR_B_E5                                                     (0x1<<14) // Pre-fetch FIFO error of Storm B.
+  #define MSEM_REG_INT_STS_CLR_2_ARB_RBC_FIFO_ERROR_B_E5_SHIFT                                               14
+  #define MSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5                                             (0x1<<15) // Lock is acquired more than maximum configured time.
+  #define MSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5_SHIFT                                       15
+  #define MSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                              (0x1<<16) // Ilegal assetion commands towards lock block.
+  #define MSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5_SHIFT                                        16
+  #define MSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_RELEASE_ERROR_E5                                               (0x1<<17) // Error when trying to release a lock which is not acquired (key does not match any lock)
+  #define MSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_RELEASE_ERROR_E5_SHIFT                                         17
+  #define MSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5                                             (0x1<<18) // Trying to acquire a lock which is already acquired.
+  #define MSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5_SHIFT                                       18
+  #define MSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5                                            (0x1<<19) // Trying to relinquish a key which does not exist.
+  #define MSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5_SHIFT                                      19
+  #define MSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5                                            (0x1<<20) // A lock acquired requrest is issued when all locks are used.
+  #define MSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5_SHIFT                                      20
+  #define MSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5                                            (0x1<<21) // Error when both Storm are stalled due to lock block (may indicate a dead lock).
+  #define MSEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5_SHIFT                                      21
+  #define MSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5                                        (0x1<<22) // Fin done with remainning allocated threads STORM_A.
+  #define MSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5_SHIFT                                  22
+  #define MSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5                                        (0x1<<23) // Fin done with remainning allocated threads STORM_B.
+  #define MSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5_SHIFT                                  23
+  #define MSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5                                        (0x1<<24) // Fin new thread request when no thread is allocated for handler of Storm A.
+  #define MSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5_SHIFT                                  24
+  #define MSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5                                        (0x1<<25) // Fin new thread request when no thread is allocated for handler of Storm B.
+  #define MSEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5_SHIFT                                  25
+  #define MSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5                                  (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same range.
+  #define MSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5_SHIFT                            26
+  #define MSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5                                  (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same range.
+  #define MSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5_SHIFT                            27
+  #define MSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5                                     (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
+  #define MSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5_SHIFT                               28
+  #define MSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5                                     (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
+  #define MSEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5_SHIFT                               29
+  #define MSEM_REG_INT_STS_CLR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5                                      (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
+  #define MSEM_REG_INT_STS_CLR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT                                30
+#define MSEM_REG_PRTY_MASK                                                                                   0x18000ccUL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define MSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR                                                            (0x1<<0) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS.VFC_RBC_PARITY_ERROR .
+  #define MSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR_SHIFT                                                      0
+  #define MSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR                                                           (0x1<<1) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS.STORM_RF_PARITY_ERROR .
+  #define MSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR_SHIFT                                                     1
+  #define MSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR                                                            (0x1<<2) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS.REG_GEN_PARITY_ERROR .
+  #define MSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR_SHIFT                                                      2
+#define MSEM_REG_PRTY_MASK_H_0_BB_K2                                                                         0x1800204UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define MSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_BB_K2                                                 (0x1<<0) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
+  #define MSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_BB_K2_SHIFT                                           0
+  #define MSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_K2                                                 (0x1<<1) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
+  #define MSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_K2_SHIFT                                           1
+  #define MSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                     (0x1<<2) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define MSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                               2
+  #define MSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                     (0x1<<3) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define MSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                               3
+  #define MSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                     (0x1<<4) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define MSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                               4
+  #define MSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                     (0x1<<5) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define MSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                               5
+#define MSEM_REG_MEM_ECC_ENABLE_0_BB_K2                                                                      0x1800210UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define MSEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN_BB_K2                                                  (0x1<<0) // Enable ECC for memory ecc instance msem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_0 in module sem_slow_pas_buf_ram
+  #define MSEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN_BB_K2_SHIFT                                            0
+  #define MSEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_BB_K2                                                  (0x1<<1) // Enable ECC for memory ecc instance msem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_1 in module sem_slow_pas_buf_ram
+  #define MSEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_BB_K2_SHIFT                                            1
+#define MSEM_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                 0x1800214UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define MSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY_BB_K2                                           (0x1<<0) // Set parity only for memory ecc instance msem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_0 in module sem_slow_pas_buf_ram
+  #define MSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY_BB_K2_SHIFT                                     0
+  #define MSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_BB_K2                                           (0x1<<1) // Set parity only for memory ecc instance msem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_1 in module sem_slow_pas_buf_ram
+  #define MSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_BB_K2_SHIFT                                     1
+#define MSEM_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                             0x1800218UL //Access:RC   DataWidth:0x2    // Multi Field Register.
+  #define MSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT_BB_K2                                    (0x1<<0) // Record if a correctable error occurred on memory ecc instance msem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_0 in module sem_slow_pas_buf_ram
+  #define MSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT_BB_K2_SHIFT                              0
+  #define MSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_BB_K2                                    (0x1<<1) // Record if a correctable error occurred on memory ecc instance msem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_1 in module sem_slow_pas_buf_ram
+  #define MSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_BB_K2_SHIFT                              1
+#define MSEM_REG_MEM_ECC_EVENTS_BB_K2                                                                        0x180021cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define MSEM_REG_ARB_CYCLE_SIZE_BB_K2                                                                        0x1800400UL //Access:RW   DataWidth:0x5    // The number of time_slots in the arbitration cycle.
+#define MSEM_REG_VF_ERROR                                                                                    0x1800408UL //Access:WR   DataWidth:0x1    // This VF-split register provides read/clear access to the VF error received from the SDM for a DMA transfer. Reading this register will return the VF Error for value for the corresponding VF. Writing a 1 to this register will clear the error for the corresponding VF.
+#define MSEM_REG_PF_ERROR                                                                                    0x180040cUL //Access:WR   DataWidth:0x1    // This PF-split register provides read/clear access to the PF error received from the SDM for a DMA transfer. Reading this register will return the PF Error for value for the corresponding PF. Writing a 1 to this register will clear the error for the corresponding PF.
+#define MSEM_REG_VF_ERR_VECTOR                                                                               0x1800420UL //Access:WB_R DataWidth:0xf0   // This read-only register provides a vector of bits having an error indication per VF where the Bit position corresponds to the VFID.
+#define MSEM_REG_VF_ERR_VECTOR_SIZE_BB                                                                       4
+#define MSEM_REG_VF_ERR_VECTOR_SIZE_K2_E5                                                                    8
+#define MSEM_REG_PF_ERR_VECTOR                                                                               0x1800440UL //Access:R    DataWidth:0x10   // This read-only register provides a vector of bits having an error indication per PF where the Bit position corresponds to the PFID.
+#define MSEM_REG_CLEAR_STALL                                                                                 0x1800444UL //Access:RW   DataWidth:0x1    // Clear stall signal sent from local storm to external storms.
+#define MSEM_REG_EXCEPTION_INT                                                                               0x1800448UL //Access:RW   DataWidth:0x10   // Provides a default PRAM address to be used for the handler in the event that the PRAM address retrieved from the interrupt table is out of range with regard to the actual PRAM size provided in the SEMI instance.
+#define MSEM_REG_EXT_STORE_FREE_ENTRIES_BB_K2                                                                0x180044cUL //Access:R    DataWidth:0x6    // Number of free entries in the external STORE sync FIFO.
+#define MSEM_REG_GPI_DATA_A_E5                                                                               0x1800450UL //Access:R    DataWidth:0x20   // Used to read the GPI input signals of Storm A.
+#define MSEM_REG_GPI_DATA_BB_K2                                                                              0x1800450UL //Access:R    DataWidth:0x20   // Used to read the GPI input signals.
+#define MSEM_REG_GPRE_SAMP_PERIOD_BB_K2                                                                      0x1800454UL //Access:RW   DataWidth:0x4    // Defines the number of system clocks from one sample of GPRE sync data and the next.
+#define MSEM_REG_ALLOW_LP_SLEEP_THRD                                                                         0x1800458UL //Access:RW   DataWidth:0x1    // When set, this bit is used to allow low-power mode to be activated while threads are sleeping in the passive buffer, as long as the SEMI/Storm remains idle.
+#define MSEM_REG_ECO_RESERVED                                                                                0x180045cUL //Access:RW   DataWidth:0x20   // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
+#define MSEM_REG_PB_WR_SDM_DMA_MODE_E5                                                                       0x1800460UL //Access:RW   DataWidth:0x2    // This register can set the mode of the SDM DMA write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use regardless write mode. 11 - Disable write mode.
+#define MSEM_REG_PB_WR_DRA_RD_CUT_THROUGH_MODE_E5                                                            0x1800464UL //Access:RW   DataWidth:0x1    // This register set the DRA RD block cut through mode in which write to a thread address section passive buffer may occur simultaneously with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut through mode active.
+#define MSEM_REG_GPI_DATA_B_E5                                                                               0x1800468UL //Access:R    DataWidth:0x20   // Used to read the GPI input signals of Storm B.
+#define MSEM_REG_FIC_FIFO_BB_K2                                                                              0x1800580UL //Access:WB_R DataWidth:0x80   // Used for debugging to read/write to/from the FIC FIFOs. The address selects which FIFO should be accessed.
+#define MSEM_REG_FIC_FIFO_SIZE                                                                               4
+#define MSEM_REG_FIC_MIN_MSG_BB_K2                                                                           0x1800600UL //Access:RW   DataWidth:0x6    // Per-FIC interface register array defines minimum number of cycles in the FIC interfaces after which the message can be sent to the passive register_file.
+#define MSEM_REG_FIC_EMPTY_CT_MODE_BB_K2                                                                     0x1800620UL //Access:RW   DataWidth:0x1    // When set, enables the "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require that the available ("go") counter is non-zero before making a transfer request to the DRA arbiter and starting a transfer.
+#define MSEM_REG_FIC_EMPTY_CT_CNT_BB_K2                                                                      0x1800624UL //Access:RC   DataWidth:0x18   // Statistics counter used to count the number of FIC messages that have been received on any FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
+#define MSEM_REG_FOC_CREDIT                                                                                  0x1800680UL //Access:RW   DataWidth:0x8    // Array of registers provides the initial credits on each of the associatef FOC interfaces. Reading from this register provides the current FOR credit value.
+#define MSEM_REG_FOC_CREDIT_SIZE                                                                             6
+#define MSEM_REG_FULL_FOC_DRA_STRT_EN_BB_K2                                                                  0x18006c0UL //Access:RW   DataWidth:0x1    // When set, this bit allows the DRA read operation to start even when there are not enough credits on all the participating FOC interfaces to complete the entire transaction. The transfer will stall only when a transfer cycle is reached in which there are no interface credits, at which time the DRA transfer will remain stalled until the FOC destination(s) has at least a single credit. When this configuration is cleared, the DRA read transfer will not begin until there are enough credits on all the participating FOC interfaces for the entire transfer.
+#define MSEM_REG_FIN_COMMAND_BB_K2                                                                           0x1800700UL //Access:WB_R DataWidth:0x164  // Last fin command that was read from fifo. Its spelling in FIN_FIFO register.
+#define MSEM_REG_FIN_COMMAND_SIZE                                                                            16
+#define MSEM_REG_FIN_FIFO_BB_K2                                                                              0x1800800UL //Access:WB_R DataWidth:0x164  // READ ONLY FOR DEBUGGING! [5:0]   start_rp_foc3; [11:6] start_rp_foc2;  [17:12]   start_rp_foc1; [23:18] start_rp_foc0;  [29:24]   end_rp_foc3; [35:30] end_rp_foc2; [41:36]   end_rp_foc1; [47:42]   end_rp_foc0; [53:48]   lowest rp; [59:54]   highest rp; [65:60]   store start rp; [71:66]   store end rp; [77:72]   load start rp; [83:78]   load end rp; [85:84]   priority; [101:86]  pram address; [102] pas; [103] foc3; [104] foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:0] is valid.
+#define MSEM_REG_FIN_FIFO_SIZE                                                                               16
+#define MSEM_REG_INVLD_PAS_WR_EN_BB_K2                                                                       0x1800900UL //Access:RW   DataWidth:0x1    // When set, an attempt to write to the passive buffer over the external passive interface will be enabled even if the partition being written is owned by a thread whose valid bit is not set. Otherwise if cleared, the transfer will be stalled.
+#define MSEM_REG_ARBITER_REQUEST_BB_K2                                                                       0x1800980UL //Access:R    DataWidth:0x5    // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2.
+#define MSEM_REG_ARBITER_SELECT_BB_K2                                                                        0x1800984UL //Access:R    DataWidth:0x5    // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2.
+#define MSEM_REG_ARBITER_SLOT_BB_K2                                                                          0x1800988UL //Access:R    DataWidth:0x5    // Dra arbiter last slot.
+#define MSEM_REG_ARB_AS_DEF_BB_K2                                                                            0x1800a00UL //Access:RW   DataWidth:0x3    // Two-dimensional register array is used to define each of four arbitration schemes used by the main DRA arbiter. For this, bits 4:3 of the offset are used to select the arbitration scheme 0-3. Bits 2:0 of the offset are used to define the five priority sources for the selected scheme, where for each priority (0-4), an arbiter source is assigned. Valid values for these configurations are the source enumerations, where FIC0=0x0, FIC1=0x1, wake priority0=0x2, wake priority1=0x3 and wake priority2=0x4. Note that there are holes in the indirect offset address which always return zero when read. These exist at offsets 0x5-0x7, 0xd-0xf, 0x15-0x17 and 0x1d-0x1f.
+#define MSEM_REG_ARB_AS_DEF_SIZE                                                                             32
+#define MSEM_REG_ARB_TS_AS_BB_K2                                                                             0x1800a80UL //Access:RW   DataWidth:0x2    // Register array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
+#define MSEM_REG_ARB_TS_AS_SIZE                                                                              20
+#define MSEM_REG_NUM_OF_THREADS                                                                              0x1800b00UL //Access:R    DataWidth:0x8    // The number of currently free threads (in invalid state).
+#define MSEM_REG_THREAD_ERROR_LOW_E5                                                                         0x1800b04UL //Access:R    DataWidth:0x20   // Thread error low indication. Represents threads 31 -0
+#define MSEM_REG_THREAD_ERROR_BB_K2                                                                          0x1800b04UL //Access:R    DataWidth:0x18   // Thread error indication.
+#define MSEM_REG_THREAD_RDY_BB_K2                                                                            0x1800b08UL //Access:R    DataWidth:0x18   // Thread ready indication.
+#define MSEM_REG_THREAD_SET_NUM                                                                              0x1800b0cUL //Access:W    DataWidth:0x6    // Thread ID. Write thread ID will set ready indication for this thread ID.
+#define MSEM_REG_THREAD_VALID_BB_K2                                                                          0x1800b10UL //Access:R    DataWidth:0x18   // Valid sleeping threads.
+#define MSEM_REG_THREADS_LIST_BB_K2                                                                          0x1800b14UL //Access:RW   DataWidth:0x18   // List of free threads.
+#define MSEM_REG_THREAD_NUMBER_E5                                                                            0x1800b18UL //Access:RW   DataWidth:0x8    // Defines the maixmum number of supported threads in SEMI.
+#define MSEM_REG_THREAD_ERROR_HIGH_E5                                                                        0x1800b1cUL //Access:R    DataWidth:0x18   // Thread error high indication. Represents threads  55-32
+#define MSEM_REG_FOC_MIN_MESSAGE_CREDIT_E5                                                                   0x1800b40UL //Access:RW   DataWidth:0x8    // This field defines for each FOC the minimum message reuired for the FOC transfer to start.
+#define MSEM_REG_FOC_MIN_MESSAGE_CREDIT_SIZE                                                                 6
+#define MSEM_REG_ORDER_HEAD_BB_K2                                                                            0x1800c00UL //Access:RW   DataWidth:0x5    // This (indirect) register array of registers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
+#define MSEM_REG_ORDER_HEAD_SIZE                                                                             24
+#define MSEM_REG_ORDER_TAIL_BB_K2                                                                            0x1800c80UL //Access:RW   DataWidth:0x5    // This (indirect) register array of registers provides read/write access to the tail pointers assigned to each of the thread ordering queues.
+#define MSEM_REG_ORDER_TAIL_SIZE                                                                             24
+#define MSEM_REG_ORDER_EMPTY_BB_K2                                                                           0x1800d00UL //Access:RW   DataWidth:0x1    // This vector provides read-only access to the empty bit assigned to each of the thread ordering queues.
+#define MSEM_REG_ORDER_EMPTY_SIZE                                                                            24
+#define MSEM_REG_ORDER_LL_REG_BB_K2                                                                          0x1800d80UL //Access:RW   DataWidth:0x5    // This array of registers provides read/write access to each entry of the linked-list array of the thread-ordering queue. Because the actual depth is based on the number of threads supported by the design, which is a Verilog parameter, a 64-entry window is reserved in the register address space. The valid entries start at the base of the window and extend through the number of threads supported. The value in each indirect register contains linked-list pointer to the next thread in the associated queue..
+#define MSEM_REG_ORDER_LL_REG_SIZE                                                                           24
+#define MSEM_REG_ORDER_POP_EN_BB_K2                                                                          0x1800e00UL //Access:RW   DataWidth:0x18   // Provides access to the thread ordering queue pop-enable vector.
+#define MSEM_REG_ORDER_WAKE_EN_BB_K2                                                                         0x1800e08UL //Access:RW   DataWidth:0x18   // Provides access to the thread ordering queue wake-enable vector.
+#define MSEM_REG_PF_NUM_ORDER_BASE_BB_K2                                                                     0x1800e10UL //Access:RW   DataWidth:0x5    // This field defines the base value for the ordering queue selection when the PFNum is chosen to control this selection. The value of this register is added to PFNum and the result is used to select one of 16 ordering queues.
+#define MSEM_REG_DBG_ALM_FULL                                                                                0x1801000UL //Access:RW   DataWidth:0x6    // Almost full for slow debug fifo.
+#define MSEM_REG_PASSIVE_ALM_FULL                                                                            0x1801004UL //Access:RW   DataWidth:0x5    // The number of free entries in the sync FIFO between the external HW and the passive buffer; below which the PassiveFull is asserted.
+#define MSEM_REG_SYNC_DRA_WR_ALM_FULL_BB_K2                                                                  0x1801008UL //Access:RW   DataWidth:0x5    // Almost full for sync dra_wr fifo (data from DRA to STORM).
+#define MSEM_REG_SYNC_RAM_WR_ALM_FULL                                                                        0x180100cUL //Access:RW   DataWidth:0x6    // Almost full for sync ram_wr fifo.
+#define MSEM_REG_SYNC_FOC_FIFO_WR_ALM_FULL_E5                                                                0x1801010UL //Access:RW   DataWidth:0x4    // Almost full for indication for FOC Sync FIFO.
+#define MSEM_REG_SYNC_SDM_READY_FIFO_WR_ALM_FULL_E5                                                          0x1801014UL //Access:RW   DataWidth:0x3    // Almost full for indication for SDM READY FIFO.
+#define MSEM_REG_SYNC_SDM_INC_FIFO_WR_ALM_FULL_E5                                                            0x1801018UL //Access:RW   DataWidth:0x3    // Almost full for indication for SDM Counter Increment FIFO.
+#define MSEM_REG_STALL_ON_INT_E5                                                                             0x180101cUL //Access:RW   DataWidth:0x2    // 00 - No stall. 01 - Both cluster Stroms will be stalled on any unmasked error occurrence. 10 - All Stroms will be stalled on any unmasked error occurrence.
+#define MSEM_REG_FIC0_A_MAX_THRDS_E5                                                                         0x1801020UL //Access:RW   DataWidth:0x6    // Defines the maximum supported threads that may be contained in FIC0 A queue. If FIC0 message  is received and number of threads equals to the configured value, FIC interface will be stalled untill number of queue threads drops below configured vlaue.
+#define MSEM_REG_FIC0_X_MAX_THRDS_E5                                                                         0x1801024UL //Access:RW   DataWidth:0x6    // Defines the maximum supported threads that may be contained in FIC0 X queue. If FIC0 message  is received and number of threads equals to the configured value, FIC interface will be stalled untill number of queue threads drops below configured vlaue.
+#define MSEM_REG_FIC0_B_MAX_THRDS_E5                                                                         0x1801028UL //Access:RW   DataWidth:0x6    // Defines the maximum supported threads that may be contained in FIC0 B queue. If FIC0 message  is received and number of threads equals to the configured value, FIC interface will be stalled untill number of queue threads drops below configured vlaue.
+#define MSEM_REG_FIC1_A_MAX_THRDS_E5                                                                         0x180102cUL //Access:RW   DataWidth:0x6    // Defines the maximum supported threads that may be contained in FIC1 A queue. If FIC1 message is received and number of threads equals to the configured value, FIC interface will be stalled untill number of queue threads drops below configured vlaue.
+#define MSEM_REG_DRA_EMPTY_BB_K2                                                                             0x1801100UL //Access:R    DataWidth:0x1    // Dra_empty.
+#define MSEM_REG_EXT_PAS_EMPTY                                                                               0x1801104UL //Access:R    DataWidth:0x1    // EXT_PAS FIFO empty in sem_slow.
+#define MSEM_REG_FIC_EMPTY                                                                                   0x1801120UL //Access:R    DataWidth:0x1    // Array of registers reflects associated FIC FIFO empty in sem_slow_fic.
+#define MSEM_REG_SLOW_DBG_EMPTY_BB_K2                                                                        0x1801140UL //Access:R    DataWidth:0x1    // DBG FIFO is empty in sem_slow_ls_dbg.
+#define MSEM_REG_SLOW_DRA_FIN_EMPTY_BB_K2                                                                    0x1801144UL //Access:R    DataWidth:0x1    // FIN fifo is empty in sem_slow_dra_sync.
+#define MSEM_REG_SLOW_DRA_RD_EMPTY_BB_K2                                                                     0x1801148UL //Access:R    DataWidth:0x1    // DRA_RD pop fifo is empty in sem_slow_dra_sync.
+#define MSEM_REG_SLOW_DRA_WR_EMPTY_BB_K2                                                                     0x180114cUL //Access:R    DataWidth:0x1    // DRA_WR push fifo is empty in sem_slow_dra_sync.
+#define MSEM_REG_SLOW_EXT_STORE_EMPTY                                                                        0x1801150UL //Access:R    DataWidth:0x1    // EXT_STORE FIFO is empty in sem_slow_ls_ext.
+#define MSEM_REG_SLOW_EXT_LOAD_EMPTY                                                                         0x1801154UL //Access:R    DataWidth:0x2    // EXT_LOAD FIFO is empty in sem_slow_ls_ext, bit 0 FIFO of Core A, bit 1 FIFO of Core B.
+#define MSEM_REG_SLOW_RAM_RD_EMPTY                                                                           0x1801158UL //Access:R    DataWidth:0x1    // EXT_RD_RAM FIFO is empty in sem_slow_ls_ext.
+#define MSEM_REG_SLOW_RAM_WR_EMPTY                                                                           0x180115cUL //Access:R    DataWidth:0x1    // EXT_WR_RAM FIFO is empty in sem_slow_ls_ext.
+#define MSEM_REG_SYNC_DBG_EMPTY                                                                              0x1801160UL //Access:R    DataWidth:0x2    // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR debug FIFO of Core B
+#define MSEM_REG_THREAD_FIFO_EMPTY_BB_K2                                                                     0x1801164UL //Access:R    DataWidth:0x1    // Indicates that the thread fifo is empty in sem_slow_dra_wr.
+#define MSEM_REG_ORD_ID_FIFO_EMPTY_BB_K2                                                                     0x1801168UL //Access:R    DataWidth:0x1    // Indicates that the order ID fifo is empty in sem_slow_dra_wr.
+#define MSEM_REG_PB_QUEUE_EMPTY_E5                                                                           0x180116cUL //Access:R    DataWidth:0xb    // If 1, the correspongding Queue is empty. Queues numeration: FOC_FIFO_IF - 0,  FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - 5,  WAKE_FIFO_PRIO_X - 6, WAKE_FIFO_PRI1_X - 7,FIC0_FIFO_B - 8, WAKE_FIFO_PRIO_B - 9,  WAKE_FIFO_PRI1_B - 10.
+#define MSEM_REG_SYNC_FOC_FIFO_EMPTY_E5                                                                      0x1801170UL //Access:R    DataWidth:0x1    // FOC FIFO empty indication.
+#define MSEM_REG_SYNC_FOC_PRE_FETCH_FIFO_EMPTY_E5                                                            0x1801174UL //Access:R    DataWidth:0x1    // FOC pre fetch FIFO empty indication.
+#define MSEM_REG_EXT_PAS_FULL                                                                                0x1801200UL //Access:R    DataWidth:0x1    // EXT_PAS FIFO Full in sem_slow.
+#define MSEM_REG_EXT_STORE_IF_FULL                                                                           0x1801204UL //Access:R    DataWidth:0x1    // EXT_STORE IF is full in sem_slow_ls_ext.
+#define MSEM_REG_FIC_FULL                                                                                    0x1801220UL //Access:R    DataWidth:0x1    // Array of registers reflects associated FIC FIFO full in sem_slow_fic.
+#define MSEM_REG_PAS_IF_FULL_BB_K2                                                                           0x1801240UL //Access:R    DataWidth:0x1    // Full from passive buffer asserted toward SDM.
+#define MSEM_REG_RAM_IF_FULL                                                                                 0x1801244UL //Access:R    DataWidth:0x1    // EXT_RAM IF is full in sem_slow_ls_ram.
+#define MSEM_REG_SLOW_DBG_ALM_FULL_BB_K2                                                                     0x1801248UL //Access:R    DataWidth:0x1    // DBG FIFO is almost full in sem_slow_ls_dbg according to the full threshold configuration.
+#define MSEM_REG_SLOW_DBG_FULL_BB_K2                                                                         0x180124cUL //Access:R    DataWidth:0x1    // DBG FIFO is full in sem_slow_ls_dbg.
+#define MSEM_REG_SLOW_DRA_FIN_FULL_BB_K2                                                                     0x1801250UL //Access:R    DataWidth:0x1    // FIN fifo is full in sem_slow_dra_sync (never may be active).
+#define MSEM_REG_SLOW_DRA_RD_FULL_BB_K2                                                                      0x1801254UL //Access:R    DataWidth:0x1    // DRA_RD pop fifo is full in sem_slow_dra_sync.
+#define MSEM_REG_SLOW_DRA_WR_FULL_BB_K2                                                                      0x1801258UL //Access:R    DataWidth:0x1    // DRA_WR push fifo is full in sem_slow_dra_sync.
+#define MSEM_REG_SLOW_EXT_STORE_FULL                                                                         0x180125cUL //Access:R    DataWidth:0x2    // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIFO.
+#define MSEM_REG_SLOW_EXT_LOAD_FULL                                                                          0x1801260UL //Access:R    DataWidth:0x2    // EXT_LOAD FIFO is full in sem_slow_ls_ext, bit 0 for Core A and bit 1 for Core B.
+#define MSEM_REG_SLOW_RAM_RD_FULL                                                                            0x1801264UL //Access:R    DataWidth:0x1    // EXT_RD_RAM FIFO is full in sem_slow_ls_ext.
+#define MSEM_REG_SLOW_RAM_WR_ALM_FULL                                                                        0x1801268UL //Access:R    DataWidth:0x1    // EXT_WR_RAM FIFO is almost full in sem_slow_ls_ext.
+#define MSEM_REG_SLOW_RAM_WR_FULL                                                                            0x180126cUL //Access:R    DataWidth:0x1    // EXT_WR_RAM FIFO is full in sem_slow_ls_ext.
+#define MSEM_REG_SYNC_DBG_FULL                                                                               0x1801270UL //Access:R    DataWidth:0x2    // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR debug FIFO of Core B.
+#define MSEM_REG_THREAD_FIFO_FULL_BB_K2                                                                      0x1801274UL //Access:R    DataWidth:0x1    // Indicates that the thread fifo is full in sem_slow_dra_wr.
+#define MSEM_REG_ORD_ID_FIFO_FULL_BB_K2                                                                      0x1801278UL //Access:R    DataWidth:0x1    // Indicates that the thread fifo is full in sem_slow_dra_wr.
+#define MSEM_REG_SYNC_READY_FIFO_FULL_E5                                                                     0x180127cUL //Access:R    DataWidth:0x1    // Ready sync FIFO full indication.
+#define MSEM_REG_SYNC_CNT_FIFO_FULL_E5                                                                       0x1801280UL //Access:R    DataWidth:0x1    // Counter increment sync FIFO full indication.
+#define MSEM_REG_SYNC_FOC_FIFO_FULL_E5                                                                       0x1801284UL //Access:R    DataWidth:0x1    // sync FOC FIFO full indication.
+#define MSEM_REG_THREAD_INTER_CNT_BB_K2                                                                      0x1801300UL //Access:RW   DataWidth:0x10   // Maximum value of threads interrupt counter; when it gets this value then interrupt to will be send if thread active from previous maximum value of this counter.
+#define MSEM_REG_THREAD_INTER_CNT_ENABLE_BB_K2                                                               0x1801304UL //Access:RW   DataWidth:0x1    // Enable for start count of thread_inter_cnt.
+#define MSEM_REG_THREAD_ORUN_NUM_BB_K2                                                                       0x1801308UL //Access:R    DataWidth:0x18   // Threads are sleeping in passive buffer more than thread_inter_cnt number of cycles.
+#define MSEM_REG_SLOW_DBG_ACTIVE_BB_K2                                                                       0x1801400UL //Access:RW   DataWidth:0x1    // Debug mode is active.
+#define MSEM_REG_SLOW_DBG_MODE_BB_K2                                                                         0x1801404UL //Access:RW   DataWidth:0x3    // Debug mode for slow debug bus.
+#define MSEM_REG_DBG_FRAME_MODE_BB_K2                                                                        0x1801408UL //Access:RW   DataWidth:0x2    // Debug frame mode control for the SEMI debug bus. The following values apply: "00" - indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mode-1, which means bits 127:64 belong to fast debug and bits 63:0 belong to slow debug. "10" - indicates mode-2, which means bits 127:96 belong to fast debug and bits 95:0 belong to slow debug. "11" - indicates mode-3, which means all four words are provided by the slow debug.
+#define MSEM_REG_DBG_EACH_CYLE_BB_K2                                                                         0x180140cUL //Access:RW   DataWidth:0x1    // 0=output every cycle; 1= output only when there is a change.
+#define MSEM_REG_DBG_GPRE_VECT_BB_K2                                                                         0x1801410UL //Access:RW   DataWidth:0x8    // This 8-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug channel when they are accessed for read by the Storm during mode-6 debug (handler trace). For this, bit-0 corresponds with GPRE[0-3] and bit-7 corresponds with GPRE[28-31].
+#define MSEM_REG_DBG_IF_FULL_BB_K2                                                                           0x1801414UL //Access:R    DataWidth:0x1    // DBG IF is full in sem_slow_ls_dbg.
+#define MSEM_REG_DBG_MODE0_CFG_BB_K2                                                                         0x1801418UL //Access:RW   DataWidth:0x1    // 0=all the message; 1=partial message.
+#define MSEM_REG_DBG_MODE0_CFG_CYCLE_BB_K2                                                                   0x180141cUL //Access:RW   DataWidth:0x5    // In case DebugMode0Config = 1; the additional cycles to extract to the debug bus.
+#define MSEM_REG_DBG_MODE1_CFG_BB_K2                                                                         0x1801420UL //Access:RW   DataWidth:0x1    // 0=without the data; 1=with the data.
+#define MSEM_REG_DBG_MSG_SRC_BB_K2                                                                           0x1801424UL //Access:RW   DataWidth:0x3    // This field is a mask used to enable (or filter) the various sources of DRA write debug packets. Setting a bit causes the corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1 and bit-2 corresponds with DRA writes from the passive buffer. This applicable only for debug mode=0.
+#define MSEM_REG_DBG_QUEUE_PEFORMANCE_MON_STAT_E5                                                            0x1801428UL //Access:RW   DataWidth:0x1    // If 0, the statistic report the maximum value between following reads (when using read clear). If 1, report the current value.
+#define MSEM_REG_PASSIVE_BUFFER_PERFORMANCE_MON_STAT_E5                                                      0x180142cUL //Access:RW   DataWidth:0x1    // Enable performance monitor statistics sent to SEM_PD.
+#define MSEM_REG_DBG_QUEUE_FIC_MON_CNT_E5                                                                    0x1801430UL //Access:RC   DataWidth:0x20   // Report the number of received FIC transaction between two of the following register reads. The counter is incremanted only for the event IDs which have Debug Monitor event indication set.
+#define MSEM_REG_DBG_QUEUE_FOC_MAX_VALUE_E5                                                                  0x1801434UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FOC queue.
+#define MSEM_REG_DBG_QUEUE_FIC0_A_MAX_VALUE_E5                                                               0x1801438UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 A queue.
+#define MSEM_REG_DBG_QUEUE_FIC1_A_MAX_VALUE_E5                                                               0x180143cUL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC1 A queue.
+#define MSEM_REG_DBG_QUEUE_PRIO0_A_MAX_VALUE_E5                                                              0x1801440UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 A queue.
+#define MSEM_REG_DBG_QUEUE_PRIO1_A_MAX_VALUE_E5                                                              0x1801444UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 A queue.
+#define MSEM_REG_DBG_QUEUE_FIC0_X_MAX_VALUE_E5                                                               0x1801448UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 X queue.
+#define MSEM_REG_DBG_QUEUE_PRIO0_X_MAX_VALUE_E5                                                              0x180144cUL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 X queue.
+#define MSEM_REG_DBG_QUEUE_PRIO1_X_MAX_VALUE_E5                                                              0x1801450UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 X queue.
+#define MSEM_REG_DBG_QUEUE_FIC0_B_MAX_VALUE_E5                                                               0x1801454UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 B queue.
+#define MSEM_REG_DBG_QUEUE_PRIO0_B_MAX_VALUE_E5                                                              0x1801458UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 B queue.
+#define MSEM_REG_DBG_QUEUE_PRIO1_B_MAX_VALUE_E5                                                              0x180145cUL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 B queue.
+#define MSEM_REG_DBG_QUEUE_MAX_THREAD_VALUE_E5                                                               0x1801460UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of allocated threads in the system.
+#define MSEM_REG_DBG_QUEUE_MAX_SLEEP_VALUE_E5                                                                0x1801464UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does not include the threads pending in the queues.
+#define MSEM_REG_DBG_OUT_DATA                                                                                0x1801500UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define MSEM_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define MSEM_REG_DBG_OUT_VALID                                                                               0x1801520UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define MSEM_REG_DBG_OUT_FRAME                                                                               0x1801524UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define MSEM_REG_DBG_SELECT                                                                                  0x1801528UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define MSEM_REG_DBG_DWORD_ENABLE                                                                            0x180152cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define MSEM_REG_DBG_SHIFT                                                                                   0x1801530UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define MSEM_REG_DBG_FORCE_VALID                                                                             0x1801534UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define MSEM_REG_DBG_FORCE_FRAME                                                                             0x1801538UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define MSEM_REG_EXT_PAS_FIFO_BB_K2                                                                          0x1808000UL //Access:WB_R DataWidth:0x4d   // Provides read-only access of the external passive FIFO. Intended for debug purposes.
+#define MSEM_REG_EXT_PAS_FIFO_SIZE                                                                           76
+#define MSEM_REG_INT_TABLE                                                                                   0x1810000UL //Access:RW   DataWidth:0x1e   // Interrupt table read/write access. This register is intended to be written only when the system is idle. The fields of the interrupt table are as follows. int_table[29] = Allocated per child;  int_table[28] = Increment type; int_table[27:23] = Counter select; int_table[22] = Counter insert; int_table[21:17] = GapSel; int_table[16] = Monitor enable; int_table[15:0] = PRAM Address;
+#define MSEM_REG_INT_TABLE_SIZE                                                                              256
+#define MSEM_REG_FIC_COUNTER_GROUP_E5                                                                        0x1811000UL //Access:RW   DataWidth:0x8    // This field enables a RD/WR access to the 24 counters of the "FIC Counters".
+#define MSEM_REG_FIC_COUNTER_GROUP_SIZE                                                                      24
+#define MSEM_REG_PB_THRD_STM_GROUP_E5                                                                        0x1812000UL //Access:R    DataWidth:0x17   // Read the State mahcine state of teh trheads. 0:4 - state. 5 - pending ready. 7:6 - Affinity type. 8 - Destination FOC. 9 - Destination Storm. 10 - counter increment ready. 15:11 - counter index. 16 - Debug monitor enable. 17 - Exlucsive. 22:18 - DRA size.
+#define MSEM_REG_PB_THRD_STM_GROUP_SIZE                                                                      56
+#define MSEM_REG_PASSIVE_BUFFER                                                                              0x1820000UL //Access:R    DataWidth:0x20   // Passive buffer memory read only.
+#define MSEM_REG_PASSIVE_BUFFER_SIZE_BB_K2                                                                   4320
+#define MSEM_REG_PASSIVE_BUFFER_SIZE_E5                                                                      12544
+#define MSEM_REG_FIC_GAP_VECT_BB_K2                                                                          0x1800500UL //Access:WB   DataWidth:0x2c   // This array of nine 44-bit vectors provides a bit per register-quad, used to define the register-quad locations that should be included in gaps (discontinuities) within the DRA transfer, where bit-0 corresponds with IORs 0-3, and so on. To indicate a gap, the corresponding bit should be cleared. These gaps have a granularity of a register- quad (four IORs). For each DRA write transfer from whom the FIC is the source, one of nine gap vectors (or a default-gap vector) will be selected, based on the GapSelect field of the corresponding interrupt table entry. Any unused upper bits of the vector will be ignored and thus, can be written with any value.
+#define MSEM_REG_FIC_GAP_VECT_E5                                                                             0x1830000UL //Access:WB   DataWidth:0x34   // This array of 24 x 52-bit vectors provides a bit per register-quad, used to define the register-quad locations that should be included in gaps (discontinuities) within the DRA transfer, where bit-0 corresponds with IORs 0-3, and so on. To indicate a gap, the corresponding bit should be cleared. These gaps have a granularity of a register- quad (four IORs). For each DRA write transfer from whom the FIC is the source, one of nine gap vectors (or a default-gap vector) will be selected, based on the GapSelect field of the corresponding interrupt table entry. Any unused upper bits of the vector will be ignored and thus, can be written with any value.
+#define MSEM_REG_FIC_GAP_VECT_SIZE_BB_K2                                                                     18
+#define MSEM_REG_FIC_GAP_VECT_SIZE_E5                                                                        48
+#define MSEM_REG_FAST_MEMORY                                                                                 0x1840000UL //Access:RW   DataWidth:0x20   // See sem_fast.xls for its description.
+#define MSEM_REG_FAST_MEMORY_SIZE                                                                            65536
+#define MSEM_REG_PRAM                                                                                        0x1880000UL //Access:WB   DataWidth:0x30   // Pram memory.
+#define MSEM_REG_PRAM_SIZE_BB                                                                                49152
+#define MSEM_REG_PRAM_SIZE_K2                                                                                73728
+#define MSEM_REG_PRAM_SIZE_E5                                                                                92160
+#define USEM_REG_ENABLE_IN_BB_K2                                                                             0x1900004UL //Access:RW   DataWidth:0xa    // Multi Field Register.
+  #define USEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN_BB_K2                                                        (0x1<<0) // Full input from external IF to LS input enable.
+  #define USEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN_BB_K2_SHIFT                                                  0
+  #define USEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN_BB_K2                                                     (0x1<<1) // Read data from external LS IF input enable.
+  #define USEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN_BB_K2_SHIFT                                               1
+  #define USEM_REG_ENABLE_IN_FIC_ENABLE_IN_BB_K2                                                             (0x1<<2) // FIC input enable bit used to enable/disable messages from being received on all FIC interfaces.
+  #define USEM_REG_ENABLE_IN_FIC_ENABLE_IN_BB_K2_SHIFT                                                       2
+  #define USEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN_BB_K2                                                         (0x1<<3) // FOC acknowledge input enable bit used to enable/disable acknowledge response from being received on any of the FOC interfaces.
+  #define USEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN_BB_K2_SHIFT                                                   3
+  #define USEM_REG_ENABLE_IN_GENERAL_ENABLE_IN_BB_K2                                                         (0x1<<4) // General interface input enable.
+  #define USEM_REG_ENABLE_IN_GENERAL_ENABLE_IN_BB_K2_SHIFT                                                   4
+  #define USEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN_BB_K2                                                         (0x1<<5) // External passive write input enable.
+  #define USEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN_BB_K2_SHIFT                                                   5
+  #define USEM_REG_ENABLE_IN_RAM_ENABLE_IN_BB_K2                                                             (0x1<<6) // Data input enable to RAM.
+  #define USEM_REG_ENABLE_IN_RAM_ENABLE_IN_BB_K2_SHIFT                                                       6
+  #define USEM_REG_ENABLE_IN_STALL_ENABLE_IN_BB_K2                                                           (0x1<<7) // Enable for stall input from all external STORM instances.
+  #define USEM_REG_ENABLE_IN_STALL_ENABLE_IN_BB_K2_SHIFT                                                     7
+  #define USEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN_BB_K2                                                      (0x1<<8) // Thread ready bus input enable.
+  #define USEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN_BB_K2_SHIFT                                                8
+  #define USEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN_BB_K2                                                      (0x1<<9) // Input enable for VF error indication from SDM to SEMI.
+  #define USEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN_BB_K2_SHIFT                                                9
+#define USEM_REG_ENABLE_OUT_BB_K2                                                                            0x1900008UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define USEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT_BB_K2                                                    (0x1<<0) // Read request output enable from external LS IF.
+  #define USEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT_BB_K2_SHIFT                                              0
+  #define USEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT_BB_K2                                                    (0x1<<1) // Write request output enable from external LS IF.
+  #define USEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT_BB_K2_SHIFT                                              1
+  #define USEM_REG_ENABLE_OUT_FOC_ENABLE_OUT_BB_K2                                                           (0x1<<2) // FOC output otuput enable bit used to enable/disable messages from being sent out on any of the FOC interfaces.
+  #define USEM_REG_ENABLE_OUT_FOC_ENABLE_OUT_BB_K2_SHIFT                                                     2
+  #define USEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT_BB_K2                                                       (0x1<<3) // Passive full output enable.
+  #define USEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT_BB_K2_SHIFT                                                 3
+  #define USEM_REG_ENABLE_OUT_RAM_ENABLE_OUT_BB_K2                                                           (0x1<<4) // Data output enable to RAM.
+  #define USEM_REG_ENABLE_OUT_RAM_ENABLE_OUT_BB_K2_SHIFT                                                     4
+  #define USEM_REG_ENABLE_OUT_STALL_ENABLE_OUT_BB_K2                                                         (0x1<<5) // Stall output enable bit used to enable/disable the output stall signal toward all external Storm instances.
+  #define USEM_REG_ENABLE_OUT_STALL_ENABLE_OUT_BB_K2_SHIFT                                                   5
+#define USEM_REG_FIC_DISABLE_BB_K2                                                                           0x190000cUL //Access:RW   DataWidth:0x1    // Disables input messages from all FIC interfaces.  May be updated during run_time by the microcode.
+#define USEM_REG_PAS_DISABLE_BB_K2                                                                           0x1900010UL //Access:RW   DataWidth:0x1    // Disables input messages from the passive buffer  May be updated during run_time by the microcode.
+#define USEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_E5                                                         0x1900014UL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define USEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_FIC_WEIGHT_E5                                   (0xf<<0) // Passive Buffer write WRR weight value for FIC source.
+  #define USEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_FIC_WEIGHT_E5_SHIFT                             0
+  #define USEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_A_WEIGHT_E5                                 (0xf<<4) // Passive Buffer write WRR weight value for DRA RD A source.
+  #define USEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_A_WEIGHT_E5_SHIFT                           4
+  #define USEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_B_WEIGHT_E5                                 (0xf<<8) // Passive Buffer write WRR weight value for DRA RD B source.
+  #define USEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_B_WEIGHT_E5_SHIFT                           8
+  #define USEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_SDM_WEIGHT_E5                                   (0xf<<12) // Passive Buffer write WRR weight value for SDM source.
+  #define USEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_SDM_WEIGHT_E5_SHIFT                             12
+  #define USEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_EMPTY_CNT_E5                                    (0xf<<16) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define USEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_EMPTY_CNT_E5_SHIFT                              16
+  #define USEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_STRICT_SRC_E5                                      (0x7<<20) // This register defines if one of the source of the PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B, 100 - SDM.
+  #define USEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_STRICT_SRC_E5_SHIFT                                20
+#define USEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_E5                                                          0x1900018UL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define USEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_FOC_WEIGHT_E5                                    (0xf<<0) // Passive Buffer WRR weight value for FOC source.
+  #define USEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_FOC_WEIGHT_E5_SHIFT                              0
+  #define USEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_A_WEIGHT_E5                                  (0xf<<4) // Passive Buffer write WRR weight value for DRA WR A source.
+  #define USEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_A_WEIGHT_E5_SHIFT                            4
+  #define USEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_B_WEIGHT_E5                                  (0xf<<8) // Passive Buffer write WRR weight value for DRA WR B source.
+  #define USEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_B_WEIGHT_E5_SHIFT                            8
+  #define USEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_GRC_WEIGHT_E5                                    (0xf<<12) // Passive Buffer write WRR weight value for GRC source.
+  #define USEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_GRC_WEIGHT_E5_SHIFT                              12
+  #define USEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_EMPTY_CNT_E5                                     (0xf<<16) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define USEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_EMPTY_CNT_E5_SHIFT                               16
+  #define USEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_STRICT_SRC_E5                                       (0x7<<20) // This register defines if one of the source of the PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B, 100 - GRC.
+  #define USEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_STRICT_SRC_E5_SHIFT                                 20
+#define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_E5                                                            0x190001cUL //Access:RW   DataWidth:0x17   // Multi Field Register.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_FIC0_A_WEIGHT_E5                             (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_FIC0_A_WEIGHT_E5_SHIFT                       0
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_FIC1_A_WEIGHT_E5                             (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_FIC1_A_WEIGHT_E5_SHIFT                       4
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO0_A_WEIGHT_E5                            (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO0_A_WEIGHT_E5_SHIFT                      8
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO1_A_WEIGHT_E5                            (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO1_A_WEIGHT_E5_SHIFT                      12
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_EMPTY_CNT_E5                                 (0xf<<16) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_EMPTY_CNT_E5_SHIFT                           16
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_STRICT_SRC_E5                                   (0x7<<20) // This register defines if one of the source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - FIC1.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_STRICT_SRC_E5_SHIFT                             20
+#define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_E5                                                            0x1900020UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_FIC0_X_WEIGHT_E5                             (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_FIC0_X_WEIGHT_E5_SHIFT                       0
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO0_X_WEIGHT_E5                            (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO0_X_WEIGHT_E5_SHIFT                      4
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO1_X_WEIGHT_E5                            (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO1_X_WEIGHT_E5_SHIFT                      8
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_EMPTY_CNT_E5                                 (0xf<<12) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_EMPTY_CNT_E5_SHIFT                           12
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_STRICT_SRC_E5                                   (0x3<<16) // This register defines if one of the source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_STRICT_SRC_E5_SHIFT                             16
+#define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_E5                                                            0x1900024UL //Access:RW   DataWidth:0x12   // Multi Field Register.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_FIC0_B_WEIGHT_E5                             (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_FIC0_B_WEIGHT_E5_SHIFT                       0
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO0_B_WEIGHT_E5                            (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO0_B_WEIGHT_E5_SHIFT                      4
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO1_B_WEIGHT_E5                            (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO1_B_WEIGHT_E5_SHIFT                      8
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_EMPTY_CNT_E5                                 (0xf<<12) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_EMPTY_CNT_E5_SHIFT                           12
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_STRICT_SRC_E5                                   (0x3<<16) // This register defines if one of the source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_STRICT_SRC_E5_SHIFT                             16
+#define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_E5                                                            0x1900028UL //Access:RW   DataWidth:0xe    // Multi Field Register.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_AFFIN_A_WEIGHT_E5                            (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for Affinity A source.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_AFFIN_A_WEIGHT_E5_SHIFT                      0
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_AFFIN_X_WEIGHT_E5                            (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for Affinity X source.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_AFFIN_X_WEIGHT_E5_SHIFT                      4
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_EMPTY_CNT_E5                                 (0xf<<8) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_RR_EMPTY_CNT_E5_SHIFT                           8
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_STRICT_SRC_E5                                   (0x3<<12) // This register defines if one of the source of the PB WR arbiter should have strict priority: 0 - None, 1 - AFFINITY A, 2- AFFINITY X.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_STRICT_SRC_E5_SHIFT                             12
+#define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_E5                                                            0x190002cUL //Access:RW   DataWidth:0xc    // Multi Field Register.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_AFFIN_B_WEIGHT_E5                            (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for Affinity B source.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_AFFIN_B_WEIGHT_E5_SHIFT                      0
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_AFFIN_X_WEIGHT_E5                            (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for Affinity X source.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_AFFIN_X_WEIGHT_E5_SHIFT                      4
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_EMPTY_CNT_E5                                 (0xf<<8) // This register defines the number of cycles the WRR arbiter source should not have a request for its weight to be decremented.
+  #define USEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_RR_EMPTY_CNT_E5_SHIFT                           8
+#define USEM_REG_PASSIVE_BUFFER_DRA_WR_E5                                                                    0x1900030UL //Access:RW   DataWidth:0x4    // Multi Field Register.
+  #define USEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_A_E5                                                   (0x1<<0) // Enable DRA Write to transactions towards the SEM_PD Core A.
+  #define USEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_A_E5_SHIFT                                             0
+  #define USEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_B_E5                                                   (0x1<<1) // Enable DRA Write to transactions towards the SEM_PD Core B.
+  #define USEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_B_E5_SHIFT                                             1
+  #define USEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_PEND_BLOCK_EN_E5                                          (0x1<<2) // When set, there may only be a single thread pending to run for each storm.
+  #define USEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_PEND_BLOCK_EN_E5_SHIFT                                    2
+  #define USEM_REG_PASSIVE_BUFFER_DRA_WR_PB_AFFINITY_CORE_A_ONLY_E5                                          (0x1<<3) // When set, the Affintiy field of the thread is set to CoreA (regardless to the Afficnity received from CM).
+  #define USEM_REG_PASSIVE_BUFFER_DRA_WR_PB_AFFINITY_CORE_A_ONLY_E5_SHIFT                                    3
+#define USEM_REG_INT_STS_0                                                                                   0x1900040UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define USEM_REG_INT_STS_0_ADDRESS_ERROR                                                                   (0x1<<0) // Signals an unknown address to the rf module.
+  #define USEM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                             0
+  #define USEM_REG_INT_STS_0_FIC_LAST_ERROR                                                                  (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
+  #define USEM_REG_INT_STS_0_FIC_LAST_ERROR_SHIFT                                                            1
+  #define USEM_REG_INT_STS_0_FIC_LENGTH_ERROR                                                                (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
+  #define USEM_REG_INT_STS_0_FIC_LENGTH_ERROR_SHIFT                                                          2
+  #define USEM_REG_INT_STS_0_FIC_FIFO_ERROR                                                                  (0x1<<3) // Error in any one of the FIC FIFO is active.
+  #define USEM_REG_INT_STS_0_FIC_FIFO_ERROR_SHIFT                                                            3
+  #define USEM_REG_INT_STS_0_DRA_RD_A_LAST_ERROR_E5                                                          (0x1<<4) // DRA_RD_A last indication was unexpectedly received or was not received at expected time.
+  #define USEM_REG_INT_STS_0_DRA_RD_A_LAST_ERROR_E5_SHIFT                                                    4
+  #define USEM_REG_INT_STS_0_DRA_RD_B_LAST_ERROR_E5                                                          (0x1<<5) // DRA_RD_B last indication was unexpectedly received or was not received at expected time.
+  #define USEM_REG_INT_STS_0_DRA_RD_B_LAST_ERROR_E5_SHIFT                                                    5
+  #define USEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_A_E5                                                   (0x1<<6) // Error in external store slow sync FIFO pop logic of Storm A.
+  #define USEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_A_E5_SHIFT                                             6
+  #define USEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_B_E5                                                   (0x1<<7) // Error in external store slow sync FIFO pop logic of Storm B.
+  #define USEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT                                             7
+  #define USEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5                                                   (0x1<<8) // Error in external load sync slow FIFO push logic.
+  #define USEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT                                             8
+  #define USEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5                                                   (0x1<<9) // Error in external load sync slow FIFO pop logic.
+  #define USEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5_SHIFT                                             9
+  #define USEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2                                                    (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
+  #define USEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2_SHIFT                                              22
+  #define USEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_E5                                                       (0x1<<10) // Error in slow LS_SYNC_PUSH FIFO.
+  #define USEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_E5_SHIFT                                                 10
+  #define USEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_BB_K2                                                     (0x1<<23) // Error in LS_SYNC_POP FIFO.
+  #define USEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_BB_K2_SHIFT                                               23
+  #define USEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_E5                                                        (0x1<<11) // Error in slow LS_SYNC_POP FIFO.
+  #define USEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_E5_SHIFT                                                  11
+  #define USEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2                                                    (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
+  #define USEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2_SHIFT                                              25
+  #define USEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_E5                                                       (0x1<<12) // Error in slow LS_SYNC_PUSH FIFO.
+  #define USEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_E5_SHIFT                                                 12
+  #define USEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_A_E5                                                         (0x1<<13) // Error in slow LS_SYNC_PUSH FIFO.
+  #define USEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_A_E5_SHIFT                                                   13
+  #define USEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_B_E5                                                         (0x1<<14) // Error in slow LS_SYNC_POP FIFO.
+  #define USEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_B_E5_SHIFT                                                   14
+  #define USEM_REG_INT_STS_0_DBG_FIFO_ERROR_BB_K2                                                            (0x1<<28) // Error in slow debug fifo.
+  #define USEM_REG_INT_STS_0_DBG_FIFO_ERROR_BB_K2_SHIFT                                                      28
+  #define USEM_REG_INT_STS_0_DBG_FIFO_ERROR_E5                                                               (0x1<<15) // Error in slow debug fifo
+  #define USEM_REG_INT_STS_0_DBG_FIFO_ERROR_E5_SHIFT                                                         15
+  #define USEM_REG_INT_STS_0_EXT_THREAD_OOR_ERROR_E5                                                         (0x1<<16) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define USEM_REG_INT_STS_0_EXT_THREAD_OOR_ERROR_E5_SHIFT                                                   16
+  #define USEM_REG_INT_STS_0_EXT_STORE_TAG_ODER_ERROR_E5                                                     (0x1<<17) // Error detected in the ext Stroe interface internal TAG order ID.
+  #define USEM_REG_INT_STS_0_EXT_STORE_TAG_ODER_ERROR_E5_SHIFT                                               17
+  #define USEM_REG_INT_STS_0_FIC1_AFFINITY_FIELD_ERROR_E5                                                    (0x1<<18) // Indicates that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
+  #define USEM_REG_INT_STS_0_FIC1_AFFINITY_FIELD_ERROR_E5_SHIFT                                              18
+  #define USEM_REG_INT_STS_0_EXT_LD_LEN_ERROR_E5                                                             (0x1<<19) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define USEM_REG_INT_STS_0_EXT_LD_LEN_ERROR_E5_SHIFT                                                       19
+  #define USEM_REG_INT_STS_0_PB_QUE_ARB_THRD_RDY_ERROR_E5                                                    (0x1<<20) // Indicates that Passive Buffer State machine has unexpectedly received a ready indication in the following cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pending FOC" or "Ready FOC" state. b. Pending Ready indication is already asserted.
+  #define USEM_REG_INT_STS_0_PB_QUE_ARB_THRD_RDY_ERROR_E5_SHIFT                                              20
+  #define USEM_REG_INT_STS_0_SYNC_FOC_FIFO_ERROR_E5                                                          (0x1<<21) // Error indication on FOC sync FIFO.
+  #define USEM_REG_INT_STS_0_SYNC_FOC_FIFO_ERROR_E5_SHIFT                                                    21
+  #define USEM_REG_INT_STS_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                      (0x1<<22) // The error indicates on an error of one the threads READY queues.
+  #define USEM_REG_INT_STS_0_PB_QUE_ARB_QUEUES_ERROR_E5_SHIFT                                                22
+  #define USEM_REG_INT_STS_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5                                                (0x1<<23) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define USEM_REG_INT_STS_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5_SHIFT                                          23
+  #define USEM_REG_INT_STS_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5                                                (0x1<<24) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define USEM_REG_INT_STS_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5_SHIFT                                          24
+  #define USEM_REG_INT_STS_0_CREDIT_ERROR_FOC0_E5                                                            (0x1<<25) // FOC0 is out of credit.
+  #define USEM_REG_INT_STS_0_CREDIT_ERROR_FOC0_E5_SHIFT                                                      25
+  #define USEM_REG_INT_STS_0_CREDIT_ERROR_FOC1_E5                                                            (0x1<<26) // FOC1 is out of credit.
+  #define USEM_REG_INT_STS_0_CREDIT_ERROR_FOC1_E5_SHIFT                                                      26
+  #define USEM_REG_INT_STS_0_CREDIT_ERROR_FOC2_E5                                                            (0x1<<27) // FOC2 is out of credit.
+  #define USEM_REG_INT_STS_0_CREDIT_ERROR_FOC2_E5_SHIFT                                                      27
+  #define USEM_REG_INT_STS_0_CREDIT_ERROR_FOC3_E5                                                            (0x1<<28) // FOC3 is out of credit.
+  #define USEM_REG_INT_STS_0_CREDIT_ERROR_FOC3_E5_SHIFT                                                      28
+  #define USEM_REG_INT_STS_0_CREDIT_ERROR_FOC4_E5                                                            (0x1<<29) // FOC4 is out of credit.
+  #define USEM_REG_INT_STS_0_CREDIT_ERROR_FOC4_E5_SHIFT                                                      29
+  #define USEM_REG_INT_STS_0_CREDIT_ERROR_FOC5_E5                                                            (0x1<<30) // FOC5 is out of credit.
+  #define USEM_REG_INT_STS_0_CREDIT_ERROR_FOC5_E5_SHIFT                                                      30
+  #define USEM_REG_INT_STS_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                     (0x1<<31) // Error indication of foc pre_fetch fifo.
+  #define USEM_REG_INT_STS_0_FOC_PRE_FETCH_FIFO_ERROR_E5_SHIFT                                               31
+  #define USEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR_BB_K2                                                        (0x1<<4) // Error in Ext PAS_FIFO is active.
+  #define USEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR_BB_K2_SHIFT                                                  4
+  #define USEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR_BB_K2                                                        (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
+  #define USEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR_BB_K2_SHIFT                                                  5
+  #define USEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2                                                    (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
+  #define USEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2_SHIFT                                              6
+  #define USEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR_BB_K2                                                     (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
+  #define USEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT                                               7
+  #define USEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2                                                    (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
+  #define USEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT                                              8
+  #define USEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR_BB_K2                                                     (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
+  #define USEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR_BB_K2_SHIFT                                               9
+  #define USEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR_BB_K2                                                       (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
+  #define USEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR_BB_K2_SHIFT                                                 10
+  #define USEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR_BB_K2                                                    (0x1<<11) // Signals an unknown address in the fast-memory window.
+  #define USEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR_BB_K2_SHIFT                                              11
+  #define USEM_REG_INT_STS_0_CAM_LSB_INP_FIFO_BB_K2                                                          (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
+  #define USEM_REG_INT_STS_0_CAM_LSB_INP_FIFO_BB_K2_SHIFT                                                    12
+  #define USEM_REG_INT_STS_0_CAM_MSB_INP_FIFO_BB_K2                                                          (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
+  #define USEM_REG_INT_STS_0_CAM_MSB_INP_FIFO_BB_K2_SHIFT                                                    13
+  #define USEM_REG_INT_STS_0_CAM_OUT_FIFO_BB_K2                                                              (0x1<<14) // Error in CAM_OUT fifo in cam block.
+  #define USEM_REG_INT_STS_0_CAM_OUT_FIFO_BB_K2_SHIFT                                                        14
+  #define USEM_REG_INT_STS_0_FIN_FIFO_BB_K2                                                                  (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
+  #define USEM_REG_INT_STS_0_FIN_FIFO_BB_K2_SHIFT                                                            15
+  #define USEM_REG_INT_STS_0_THREAD_FIFO_ERROR_BB_K2                                                         (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
+  #define USEM_REG_INT_STS_0_THREAD_FIFO_ERROR_BB_K2_SHIFT                                                   16
+  #define USEM_REG_INT_STS_0_THREAD_OVERRUN_BB_K2                                                            (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
+  #define USEM_REG_INT_STS_0_THREAD_OVERRUN_BB_K2_SHIFT                                                      17
+  #define USEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2                                                 (0x1<<18) // Error in external store sync FIFO push logic.
+  #define USEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2_SHIFT                                           18
+  #define USEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_BB_K2                                                  (0x1<<19) // Error in external store sync FIFO pop logic.
+  #define USEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_BB_K2_SHIFT                                            19
+  #define USEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2                                                  (0x1<<20) // Error in external load sync FIFO push logic.
+  #define USEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2_SHIFT                                            20
+  #define USEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2                                                   (0x1<<21) // Error in external load sync FIFO pop logic.
+  #define USEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2_SHIFT                                             21
+  #define USEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR_BB_K2                                                     (0x1<<24) // Error in LS_SYNC_POP FIFO.
+  #define USEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR_BB_K2_SHIFT                                               24
+  #define USEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR_BB_K2                                                       (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
+  #define USEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR_BB_K2_SHIFT                                                 26
+  #define USEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_BB_K2                                                        (0x1<<27) // Error in LS_SYNC_POP FIFO.
+  #define USEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_BB_K2_SHIFT                                                  27
+  #define USEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO_BB_K2                                                         (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
+  #define USEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO_BB_K2_SHIFT                                                   29
+  #define USEM_REG_INT_STS_0_VFC_INTERRUPT_BB_K2                                                             (0x1<<30) // Error interrupt in VFC block.
+  #define USEM_REG_INT_STS_0_VFC_INTERRUPT_BB_K2_SHIFT                                                       30
+  #define USEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR_BB_K2                                                        (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
+  #define USEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR_BB_K2_SHIFT                                                  31
+#define USEM_REG_INT_MASK_0                                                                                  0x1900044UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define USEM_REG_INT_MASK_0_ADDRESS_ERROR                                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.ADDRESS_ERROR .
+  #define USEM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                            0
+  #define USEM_REG_INT_MASK_0_FIC_LAST_ERROR                                                                 (0x1<<1) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.FIC_LAST_ERROR .
+  #define USEM_REG_INT_MASK_0_FIC_LAST_ERROR_SHIFT                                                           1
+  #define USEM_REG_INT_MASK_0_FIC_LENGTH_ERROR                                                               (0x1<<2) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.FIC_LENGTH_ERROR .
+  #define USEM_REG_INT_MASK_0_FIC_LENGTH_ERROR_SHIFT                                                         2
+  #define USEM_REG_INT_MASK_0_FIC_FIFO_ERROR                                                                 (0x1<<3) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.FIC_FIFO_ERROR .
+  #define USEM_REG_INT_MASK_0_FIC_FIFO_ERROR_SHIFT                                                           3
+  #define USEM_REG_INT_MASK_0_DRA_RD_A_LAST_ERROR_E5                                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.DRA_RD_A_LAST_ERROR .
+  #define USEM_REG_INT_MASK_0_DRA_RD_A_LAST_ERROR_E5_SHIFT                                                   4
+  #define USEM_REG_INT_MASK_0_DRA_RD_B_LAST_ERROR_E5                                                         (0x1<<5) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.DRA_RD_B_LAST_ERROR .
+  #define USEM_REG_INT_MASK_0_DRA_RD_B_LAST_ERROR_E5_SHIFT                                                   5
+  #define USEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_A_E5                                                  (0x1<<6) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR_A .
+  #define USEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_A_E5_SHIFT                                            6
+  #define USEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_B_E5                                                  (0x1<<7) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR_B .
+  #define USEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT                                            7
+  #define USEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5                                                  (0x1<<8) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR_A .
+  #define USEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT                                            8
+  #define USEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5                                                  (0x1<<9) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR_B .
+  #define USEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5_SHIFT                                            9
+  #define USEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2                                                   (0x1<<22) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_RAM_RD_PUSH_ERROR .
+  #define USEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2_SHIFT                                             22
+  #define USEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_E5                                                      (0x1<<10) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_RAM_RD_PUSH_ERROR .
+  #define USEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_E5_SHIFT                                                10
+  #define USEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_BB_K2                                                    (0x1<<23) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_RAM_RD_POP_ERROR .
+  #define USEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_BB_K2_SHIFT                                              23
+  #define USEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_E5                                                       (0x1<<11) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_RAM_RD_POP_ERROR .
+  #define USEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_E5_SHIFT                                                 11
+  #define USEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2                                                   (0x1<<25) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_RAM_WR_PUSH_ERROR .
+  #define USEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2_SHIFT                                             25
+  #define USEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_E5                                                      (0x1<<12) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_RAM_WR_PUSH_ERROR .
+  #define USEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_E5_SHIFT                                                12
+  #define USEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_A_E5                                                        (0x1<<13) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR_A .
+  #define USEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_A_E5_SHIFT                                                  13
+  #define USEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_B_E5                                                        (0x1<<14) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR_B .
+  #define USEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_B_E5_SHIFT                                                  14
+  #define USEM_REG_INT_MASK_0_DBG_FIFO_ERROR_BB_K2                                                           (0x1<<28) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.DBG_FIFO_ERROR .
+  #define USEM_REG_INT_MASK_0_DBG_FIFO_ERROR_BB_K2_SHIFT                                                     28
+  #define USEM_REG_INT_MASK_0_DBG_FIFO_ERROR_E5                                                              (0x1<<15) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.DBG_FIFO_ERROR .
+  #define USEM_REG_INT_MASK_0_DBG_FIFO_ERROR_E5_SHIFT                                                        15
+  #define USEM_REG_INT_MASK_0_EXT_THREAD_OOR_ERROR_E5                                                        (0x1<<16) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.EXT_THREAD_OOR_ERROR .
+  #define USEM_REG_INT_MASK_0_EXT_THREAD_OOR_ERROR_E5_SHIFT                                                  16
+  #define USEM_REG_INT_MASK_0_EXT_STORE_TAG_ODER_ERROR_E5                                                    (0x1<<17) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.EXT_STORE_TAG_ODER_ERROR .
+  #define USEM_REG_INT_MASK_0_EXT_STORE_TAG_ODER_ERROR_E5_SHIFT                                              17
+  #define USEM_REG_INT_MASK_0_FIC1_AFFINITY_FIELD_ERROR_E5                                                   (0x1<<18) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.FIC1_AFFINITY_FIELD_ERROR .
+  #define USEM_REG_INT_MASK_0_FIC1_AFFINITY_FIELD_ERROR_E5_SHIFT                                             18
+  #define USEM_REG_INT_MASK_0_EXT_LD_LEN_ERROR_E5                                                            (0x1<<19) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.EXT_LD_LEN_ERROR .
+  #define USEM_REG_INT_MASK_0_EXT_LD_LEN_ERROR_E5_SHIFT                                                      19
+  #define USEM_REG_INT_MASK_0_PB_QUE_ARB_THRD_RDY_ERROR_E5                                                   (0x1<<20) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.PB_QUE_ARB_THRD_RDY_ERROR .
+  #define USEM_REG_INT_MASK_0_PB_QUE_ARB_THRD_RDY_ERROR_E5_SHIFT                                             20
+  #define USEM_REG_INT_MASK_0_SYNC_FOC_FIFO_ERROR_E5                                                         (0x1<<21) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_FOC_FIFO_ERROR .
+  #define USEM_REG_INT_MASK_0_SYNC_FOC_FIFO_ERROR_E5_SHIFT                                                   21
+  #define USEM_REG_INT_MASK_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                     (0x1<<22) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.PB_QUE_ARB_QUEUES_ERROR .
+  #define USEM_REG_INT_MASK_0_PB_QUE_ARB_QUEUES_ERROR_E5_SHIFT                                               22
+  #define USEM_REG_INT_MASK_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5                                               (0x1<<23) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.STORM_MOVRIND_USES_BAR_ATTN_A .
+  #define USEM_REG_INT_MASK_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5_SHIFT                                         23
+  #define USEM_REG_INT_MASK_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5                                               (0x1<<24) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.STORM_MOVRIND_USES_BAR_ATTN_B .
+  #define USEM_REG_INT_MASK_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5_SHIFT                                         24
+  #define USEM_REG_INT_MASK_0_CREDIT_ERROR_FOC0_E5                                                           (0x1<<25) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.CREDIT_ERROR_FOC0 .
+  #define USEM_REG_INT_MASK_0_CREDIT_ERROR_FOC0_E5_SHIFT                                                     25
+  #define USEM_REG_INT_MASK_0_CREDIT_ERROR_FOC1_E5                                                           (0x1<<26) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.CREDIT_ERROR_FOC1 .
+  #define USEM_REG_INT_MASK_0_CREDIT_ERROR_FOC1_E5_SHIFT                                                     26
+  #define USEM_REG_INT_MASK_0_CREDIT_ERROR_FOC2_E5                                                           (0x1<<27) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.CREDIT_ERROR_FOC2 .
+  #define USEM_REG_INT_MASK_0_CREDIT_ERROR_FOC2_E5_SHIFT                                                     27
+  #define USEM_REG_INT_MASK_0_CREDIT_ERROR_FOC3_E5                                                           (0x1<<28) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.CREDIT_ERROR_FOC3 .
+  #define USEM_REG_INT_MASK_0_CREDIT_ERROR_FOC3_E5_SHIFT                                                     28
+  #define USEM_REG_INT_MASK_0_CREDIT_ERROR_FOC4_E5                                                           (0x1<<29) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.CREDIT_ERROR_FOC4 .
+  #define USEM_REG_INT_MASK_0_CREDIT_ERROR_FOC4_E5_SHIFT                                                     29
+  #define USEM_REG_INT_MASK_0_CREDIT_ERROR_FOC5_E5                                                           (0x1<<30) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.CREDIT_ERROR_FOC5 .
+  #define USEM_REG_INT_MASK_0_CREDIT_ERROR_FOC5_E5_SHIFT                                                     30
+  #define USEM_REG_INT_MASK_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                    (0x1<<31) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.FOC_PRE_FETCH_FIFO_ERROR .
+  #define USEM_REG_INT_MASK_0_FOC_PRE_FETCH_FIFO_ERROR_E5_SHIFT                                              31
+  #define USEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR_BB_K2                                                       (0x1<<4) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.PAS_BUF_FIFO_ERROR .
+  #define USEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR_BB_K2_SHIFT                                                 4
+  #define USEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR_BB_K2                                                       (0x1<<5) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_FIN_POP_ERROR .
+  #define USEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR_BB_K2_SHIFT                                                 5
+  #define USEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2                                                   (0x1<<6) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_DRA_WR_PUSH_ERROR .
+  #define USEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2_SHIFT                                             6
+  #define USEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR_BB_K2                                                    (0x1<<7) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_DRA_WR_POP_ERROR .
+  #define USEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT                                              7
+  #define USEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2                                                   (0x1<<8) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_DRA_RD_PUSH_ERROR .
+  #define USEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT                                             8
+  #define USEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR_BB_K2                                                    (0x1<<9) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_DRA_RD_POP_ERROR .
+  #define USEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR_BB_K2_SHIFT                                              9
+  #define USEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR_BB_K2                                                      (0x1<<10) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_FIN_PUSH_ERROR .
+  #define USEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR_BB_K2_SHIFT                                                10
+  #define USEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR_BB_K2                                                   (0x1<<11) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SEM_FAST_ADDRESS_ERROR .
+  #define USEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR_BB_K2_SHIFT                                             11
+  #define USEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO_BB_K2                                                         (0x1<<12) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.CAM_LSB_INP_FIFO .
+  #define USEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO_BB_K2_SHIFT                                                   12
+  #define USEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO_BB_K2                                                         (0x1<<13) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.CAM_MSB_INP_FIFO .
+  #define USEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO_BB_K2_SHIFT                                                   13
+  #define USEM_REG_INT_MASK_0_CAM_OUT_FIFO_BB_K2                                                             (0x1<<14) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.CAM_OUT_FIFO .
+  #define USEM_REG_INT_MASK_0_CAM_OUT_FIFO_BB_K2_SHIFT                                                       14
+  #define USEM_REG_INT_MASK_0_FIN_FIFO_BB_K2                                                                 (0x1<<15) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.FIN_FIFO .
+  #define USEM_REG_INT_MASK_0_FIN_FIFO_BB_K2_SHIFT                                                           15
+  #define USEM_REG_INT_MASK_0_THREAD_FIFO_ERROR_BB_K2                                                        (0x1<<16) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.THREAD_FIFO_ERROR .
+  #define USEM_REG_INT_MASK_0_THREAD_FIFO_ERROR_BB_K2_SHIFT                                                  16
+  #define USEM_REG_INT_MASK_0_THREAD_OVERRUN_BB_K2                                                           (0x1<<17) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.THREAD_OVERRUN .
+  #define USEM_REG_INT_MASK_0_THREAD_OVERRUN_BB_K2_SHIFT                                                     17
+  #define USEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2                                                (0x1<<18) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_EXT_STORE_PUSH_ERROR .
+  #define USEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2_SHIFT                                          18
+  #define USEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_BB_K2                                                 (0x1<<19) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR .
+  #define USEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_BB_K2_SHIFT                                           19
+  #define USEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2                                                 (0x1<<20) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR .
+  #define USEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2_SHIFT                                           20
+  #define USEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2                                                  (0x1<<21) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_EXT_LOAD_POP_ERROR .
+  #define USEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2_SHIFT                                            21
+  #define USEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR_BB_K2                                                    (0x1<<24) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_RAM_WR_POP_ERROR .
+  #define USEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR_BB_K2_SHIFT                                              24
+  #define USEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR_BB_K2                                                      (0x1<<26) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_DBG_PUSH_ERROR .
+  #define USEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR_BB_K2_SHIFT                                                26
+  #define USEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_BB_K2                                                       (0x1<<27) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR .
+  #define USEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_BB_K2_SHIFT                                                 27
+  #define USEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO_BB_K2                                                        (0x1<<29) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.CAM_MSB2_INP_FIFO .
+  #define USEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO_BB_K2_SHIFT                                                  29
+  #define USEM_REG_INT_MASK_0_VFC_INTERRUPT_BB_K2                                                            (0x1<<30) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.VFC_INTERRUPT .
+  #define USEM_REG_INT_MASK_0_VFC_INTERRUPT_BB_K2_SHIFT                                                      30
+  #define USEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR_BB_K2                                                       (0x1<<31) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.VFC_OUT_FIFO_ERROR .
+  #define USEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR_BB_K2_SHIFT                                                 31
+#define USEM_REG_INT_STS_WR_0                                                                                0x1900048UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define USEM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                                (0x1<<0) // Signals an unknown address to the rf module.
+  #define USEM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                          0
+  #define USEM_REG_INT_STS_WR_0_FIC_LAST_ERROR                                                               (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
+  #define USEM_REG_INT_STS_WR_0_FIC_LAST_ERROR_SHIFT                                                         1
+  #define USEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR                                                             (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
+  #define USEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR_SHIFT                                                       2
+  #define USEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR                                                               (0x1<<3) // Error in any one of the FIC FIFO is active.
+  #define USEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR_SHIFT                                                         3
+  #define USEM_REG_INT_STS_WR_0_DRA_RD_A_LAST_ERROR_E5                                                       (0x1<<4) // DRA_RD_A last indication was unexpectedly received or was not received at expected time.
+  #define USEM_REG_INT_STS_WR_0_DRA_RD_A_LAST_ERROR_E5_SHIFT                                                 4
+  #define USEM_REG_INT_STS_WR_0_DRA_RD_B_LAST_ERROR_E5                                                       (0x1<<5) // DRA_RD_B last indication was unexpectedly received or was not received at expected time.
+  #define USEM_REG_INT_STS_WR_0_DRA_RD_B_LAST_ERROR_E5_SHIFT                                                 5
+  #define USEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_A_E5                                                (0x1<<6) // Error in external store slow sync FIFO pop logic of Storm A.
+  #define USEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_A_E5_SHIFT                                          6
+  #define USEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_B_E5                                                (0x1<<7) // Error in external store slow sync FIFO pop logic of Storm B.
+  #define USEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT                                          7
+  #define USEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5                                                (0x1<<8) // Error in external load sync slow FIFO push logic.
+  #define USEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT                                          8
+  #define USEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5                                                (0x1<<9) // Error in external load sync slow FIFO pop logic.
+  #define USEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5_SHIFT                                          9
+  #define USEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2                                                 (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
+  #define USEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2_SHIFT                                           22
+  #define USEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_E5                                                    (0x1<<10) // Error in slow LS_SYNC_PUSH FIFO.
+  #define USEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_E5_SHIFT                                              10
+  #define USEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_BB_K2                                                  (0x1<<23) // Error in LS_SYNC_POP FIFO.
+  #define USEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_BB_K2_SHIFT                                            23
+  #define USEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_E5                                                     (0x1<<11) // Error in slow LS_SYNC_POP FIFO.
+  #define USEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_E5_SHIFT                                               11
+  #define USEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2                                                 (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
+  #define USEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2_SHIFT                                           25
+  #define USEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_E5                                                    (0x1<<12) // Error in slow LS_SYNC_PUSH FIFO.
+  #define USEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_E5_SHIFT                                              12
+  #define USEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_A_E5                                                      (0x1<<13) // Error in slow LS_SYNC_PUSH FIFO.
+  #define USEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_A_E5_SHIFT                                                13
+  #define USEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_B_E5                                                      (0x1<<14) // Error in slow LS_SYNC_POP FIFO.
+  #define USEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_B_E5_SHIFT                                                14
+  #define USEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_BB_K2                                                         (0x1<<28) // Error in slow debug fifo.
+  #define USEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_BB_K2_SHIFT                                                   28
+  #define USEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_E5                                                            (0x1<<15) // Error in slow debug fifo
+  #define USEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_E5_SHIFT                                                      15
+  #define USEM_REG_INT_STS_WR_0_EXT_THREAD_OOR_ERROR_E5                                                      (0x1<<16) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define USEM_REG_INT_STS_WR_0_EXT_THREAD_OOR_ERROR_E5_SHIFT                                                16
+  #define USEM_REG_INT_STS_WR_0_EXT_STORE_TAG_ODER_ERROR_E5                                                  (0x1<<17) // Error detected in the ext Stroe interface internal TAG order ID.
+  #define USEM_REG_INT_STS_WR_0_EXT_STORE_TAG_ODER_ERROR_E5_SHIFT                                            17
+  #define USEM_REG_INT_STS_WR_0_FIC1_AFFINITY_FIELD_ERROR_E5                                                 (0x1<<18) // Indicates that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
+  #define USEM_REG_INT_STS_WR_0_FIC1_AFFINITY_FIELD_ERROR_E5_SHIFT                                           18
+  #define USEM_REG_INT_STS_WR_0_EXT_LD_LEN_ERROR_E5                                                          (0x1<<19) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define USEM_REG_INT_STS_WR_0_EXT_LD_LEN_ERROR_E5_SHIFT                                                    19
+  #define USEM_REG_INT_STS_WR_0_PB_QUE_ARB_THRD_RDY_ERROR_E5                                                 (0x1<<20) // Indicates that Passive Buffer State machine has unexpectedly received a ready indication in the following cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pending FOC" or "Ready FOC" state. b. Pending Ready indication is already asserted.
+  #define USEM_REG_INT_STS_WR_0_PB_QUE_ARB_THRD_RDY_ERROR_E5_SHIFT                                           20
+  #define USEM_REG_INT_STS_WR_0_SYNC_FOC_FIFO_ERROR_E5                                                       (0x1<<21) // Error indication on FOC sync FIFO.
+  #define USEM_REG_INT_STS_WR_0_SYNC_FOC_FIFO_ERROR_E5_SHIFT                                                 21
+  #define USEM_REG_INT_STS_WR_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                   (0x1<<22) // The error indicates on an error of one the threads READY queues.
+  #define USEM_REG_INT_STS_WR_0_PB_QUE_ARB_QUEUES_ERROR_E5_SHIFT                                             22
+  #define USEM_REG_INT_STS_WR_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5                                             (0x1<<23) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define USEM_REG_INT_STS_WR_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5_SHIFT                                       23
+  #define USEM_REG_INT_STS_WR_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5                                             (0x1<<24) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define USEM_REG_INT_STS_WR_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5_SHIFT                                       24
+  #define USEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC0_E5                                                         (0x1<<25) // FOC0 is out of credit.
+  #define USEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC0_E5_SHIFT                                                   25
+  #define USEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC1_E5                                                         (0x1<<26) // FOC1 is out of credit.
+  #define USEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC1_E5_SHIFT                                                   26
+  #define USEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC2_E5                                                         (0x1<<27) // FOC2 is out of credit.
+  #define USEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC2_E5_SHIFT                                                   27
+  #define USEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC3_E5                                                         (0x1<<28) // FOC3 is out of credit.
+  #define USEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC3_E5_SHIFT                                                   28
+  #define USEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC4_E5                                                         (0x1<<29) // FOC4 is out of credit.
+  #define USEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC4_E5_SHIFT                                                   29
+  #define USEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC5_E5                                                         (0x1<<30) // FOC5 is out of credit.
+  #define USEM_REG_INT_STS_WR_0_CREDIT_ERROR_FOC5_E5_SHIFT                                                   30
+  #define USEM_REG_INT_STS_WR_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                  (0x1<<31) // Error indication of foc pre_fetch fifo.
+  #define USEM_REG_INT_STS_WR_0_FOC_PRE_FETCH_FIFO_ERROR_E5_SHIFT                                            31
+  #define USEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR_BB_K2                                                     (0x1<<4) // Error in Ext PAS_FIFO is active.
+  #define USEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR_BB_K2_SHIFT                                               4
+  #define USEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR_BB_K2                                                     (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
+  #define USEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR_BB_K2_SHIFT                                               5
+  #define USEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2                                                 (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
+  #define USEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2_SHIFT                                           6
+  #define USEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR_BB_K2                                                  (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
+  #define USEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT                                            7
+  #define USEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2                                                 (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
+  #define USEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT                                           8
+  #define USEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR_BB_K2                                                  (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
+  #define USEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR_BB_K2_SHIFT                                            9
+  #define USEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR_BB_K2                                                    (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
+  #define USEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR_BB_K2_SHIFT                                              10
+  #define USEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR_BB_K2                                                 (0x1<<11) // Signals an unknown address in the fast-memory window.
+  #define USEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR_BB_K2_SHIFT                                           11
+  #define USEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO_BB_K2                                                       (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
+  #define USEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO_BB_K2_SHIFT                                                 12
+  #define USEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO_BB_K2                                                       (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
+  #define USEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO_BB_K2_SHIFT                                                 13
+  #define USEM_REG_INT_STS_WR_0_CAM_OUT_FIFO_BB_K2                                                           (0x1<<14) // Error in CAM_OUT fifo in cam block.
+  #define USEM_REG_INT_STS_WR_0_CAM_OUT_FIFO_BB_K2_SHIFT                                                     14
+  #define USEM_REG_INT_STS_WR_0_FIN_FIFO_BB_K2                                                               (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
+  #define USEM_REG_INT_STS_WR_0_FIN_FIFO_BB_K2_SHIFT                                                         15
+  #define USEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR_BB_K2                                                      (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
+  #define USEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR_BB_K2_SHIFT                                                16
+  #define USEM_REG_INT_STS_WR_0_THREAD_OVERRUN_BB_K2                                                         (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
+  #define USEM_REG_INT_STS_WR_0_THREAD_OVERRUN_BB_K2_SHIFT                                                   17
+  #define USEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2                                              (0x1<<18) // Error in external store sync FIFO push logic.
+  #define USEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2_SHIFT                                        18
+  #define USEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_BB_K2                                               (0x1<<19) // Error in external store sync FIFO pop logic.
+  #define USEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_BB_K2_SHIFT                                         19
+  #define USEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2                                               (0x1<<20) // Error in external load sync FIFO push logic.
+  #define USEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2_SHIFT                                         20
+  #define USEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2                                                (0x1<<21) // Error in external load sync FIFO pop logic.
+  #define USEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2_SHIFT                                          21
+  #define USEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR_BB_K2                                                  (0x1<<24) // Error in LS_SYNC_POP FIFO.
+  #define USEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR_BB_K2_SHIFT                                            24
+  #define USEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR_BB_K2                                                    (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
+  #define USEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR_BB_K2_SHIFT                                              26
+  #define USEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_BB_K2                                                     (0x1<<27) // Error in LS_SYNC_POP FIFO.
+  #define USEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_BB_K2_SHIFT                                               27
+  #define USEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO_BB_K2                                                      (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
+  #define USEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO_BB_K2_SHIFT                                                29
+  #define USEM_REG_INT_STS_WR_0_VFC_INTERRUPT_BB_K2                                                          (0x1<<30) // Error interrupt in VFC block.
+  #define USEM_REG_INT_STS_WR_0_VFC_INTERRUPT_BB_K2_SHIFT                                                    30
+  #define USEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR_BB_K2                                                     (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
+  #define USEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR_BB_K2_SHIFT                                               31
+#define USEM_REG_INT_STS_CLR_0                                                                               0x190004cUL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define USEM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                               (0x1<<0) // Signals an unknown address to the rf module.
+  #define USEM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                         0
+  #define USEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR                                                              (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
+  #define USEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR_SHIFT                                                        1
+  #define USEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR                                                            (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
+  #define USEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR_SHIFT                                                      2
+  #define USEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR                                                              (0x1<<3) // Error in any one of the FIC FIFO is active.
+  #define USEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR_SHIFT                                                        3
+  #define USEM_REG_INT_STS_CLR_0_DRA_RD_A_LAST_ERROR_E5                                                      (0x1<<4) // DRA_RD_A last indication was unexpectedly received or was not received at expected time.
+  #define USEM_REG_INT_STS_CLR_0_DRA_RD_A_LAST_ERROR_E5_SHIFT                                                4
+  #define USEM_REG_INT_STS_CLR_0_DRA_RD_B_LAST_ERROR_E5                                                      (0x1<<5) // DRA_RD_B last indication was unexpectedly received or was not received at expected time.
+  #define USEM_REG_INT_STS_CLR_0_DRA_RD_B_LAST_ERROR_E5_SHIFT                                                5
+  #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_A_E5                                               (0x1<<6) // Error in external store slow sync FIFO pop logic of Storm A.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_A_E5_SHIFT                                         6
+  #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_B_E5                                               (0x1<<7) // Error in external store slow sync FIFO pop logic of Storm B.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT                                         7
+  #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5                                               (0x1<<8) // Error in external load sync slow FIFO push logic.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT                                         8
+  #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5                                               (0x1<<9) // Error in external load sync slow FIFO pop logic.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_B_E5_SHIFT                                         9
+  #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2                                                (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_BB_K2_SHIFT                                          22
+  #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_E5                                                   (0x1<<10) // Error in slow LS_SYNC_PUSH FIFO.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_E5_SHIFT                                             10
+  #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_BB_K2                                                 (0x1<<23) // Error in LS_SYNC_POP FIFO.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_BB_K2_SHIFT                                           23
+  #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_E5                                                    (0x1<<11) // Error in slow LS_SYNC_POP FIFO.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_E5_SHIFT                                              11
+  #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2                                                (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_BB_K2_SHIFT                                          25
+  #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_E5                                                   (0x1<<12) // Error in slow LS_SYNC_PUSH FIFO.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_E5_SHIFT                                             12
+  #define USEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_A_E5                                                     (0x1<<13) // Error in slow LS_SYNC_PUSH FIFO.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_A_E5_SHIFT                                               13
+  #define USEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_B_E5                                                     (0x1<<14) // Error in slow LS_SYNC_POP FIFO.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_B_E5_SHIFT                                               14
+  #define USEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_BB_K2                                                        (0x1<<28) // Error in slow debug fifo.
+  #define USEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_BB_K2_SHIFT                                                  28
+  #define USEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_E5                                                           (0x1<<15) // Error in slow debug fifo
+  #define USEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_E5_SHIFT                                                     15
+  #define USEM_REG_INT_STS_CLR_0_EXT_THREAD_OOR_ERROR_E5                                                     (0x1<<16) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define USEM_REG_INT_STS_CLR_0_EXT_THREAD_OOR_ERROR_E5_SHIFT                                               16
+  #define USEM_REG_INT_STS_CLR_0_EXT_STORE_TAG_ODER_ERROR_E5                                                 (0x1<<17) // Error detected in the ext Stroe interface internal TAG order ID.
+  #define USEM_REG_INT_STS_CLR_0_EXT_STORE_TAG_ODER_ERROR_E5_SHIFT                                           17
+  #define USEM_REG_INT_STS_CLR_0_FIC1_AFFINITY_FIELD_ERROR_E5                                                (0x1<<18) // Indicates that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
+  #define USEM_REG_INT_STS_CLR_0_FIC1_AFFINITY_FIELD_ERROR_E5_SHIFT                                          18
+  #define USEM_REG_INT_STS_CLR_0_EXT_LD_LEN_ERROR_E5                                                         (0x1<<19) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define USEM_REG_INT_STS_CLR_0_EXT_LD_LEN_ERROR_E5_SHIFT                                                   19
+  #define USEM_REG_INT_STS_CLR_0_PB_QUE_ARB_THRD_RDY_ERROR_E5                                                (0x1<<20) // Indicates that Passive Buffer State machine has unexpectedly received a ready indication in the following cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pending FOC" or "Ready FOC" state. b. Pending Ready indication is already asserted.
+  #define USEM_REG_INT_STS_CLR_0_PB_QUE_ARB_THRD_RDY_ERROR_E5_SHIFT                                          20
+  #define USEM_REG_INT_STS_CLR_0_SYNC_FOC_FIFO_ERROR_E5                                                      (0x1<<21) // Error indication on FOC sync FIFO.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_FOC_FIFO_ERROR_E5_SHIFT                                                21
+  #define USEM_REG_INT_STS_CLR_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                  (0x1<<22) // The error indicates on an error of one the threads READY queues.
+  #define USEM_REG_INT_STS_CLR_0_PB_QUE_ARB_QUEUES_ERROR_E5_SHIFT                                            22
+  #define USEM_REG_INT_STS_CLR_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5                                            (0x1<<23) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define USEM_REG_INT_STS_CLR_0_STORM_MOVRIND_USES_BAR_ATTN_A_E5_SHIFT                                      23
+  #define USEM_REG_INT_STS_CLR_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5                                            (0x1<<24) // Marks that the indirect register of MOVRIND is located in the storm bar region.
+  #define USEM_REG_INT_STS_CLR_0_STORM_MOVRIND_USES_BAR_ATTN_B_E5_SHIFT                                      24
+  #define USEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC0_E5                                                        (0x1<<25) // FOC0 is out of credit.
+  #define USEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC0_E5_SHIFT                                                  25
+  #define USEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC1_E5                                                        (0x1<<26) // FOC1 is out of credit.
+  #define USEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC1_E5_SHIFT                                                  26
+  #define USEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC2_E5                                                        (0x1<<27) // FOC2 is out of credit.
+  #define USEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC2_E5_SHIFT                                                  27
+  #define USEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC3_E5                                                        (0x1<<28) // FOC3 is out of credit.
+  #define USEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC3_E5_SHIFT                                                  28
+  #define USEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC4_E5                                                        (0x1<<29) // FOC4 is out of credit.
+  #define USEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC4_E5_SHIFT                                                  29
+  #define USEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC5_E5                                                        (0x1<<30) // FOC5 is out of credit.
+  #define USEM_REG_INT_STS_CLR_0_CREDIT_ERROR_FOC5_E5_SHIFT                                                  30
+  #define USEM_REG_INT_STS_CLR_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                 (0x1<<31) // Error indication of foc pre_fetch fifo.
+  #define USEM_REG_INT_STS_CLR_0_FOC_PRE_FETCH_FIFO_ERROR_E5_SHIFT                                           31
+  #define USEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR_BB_K2                                                    (0x1<<4) // Error in Ext PAS_FIFO is active.
+  #define USEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR_BB_K2_SHIFT                                              4
+  #define USEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR_BB_K2                                                    (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR_BB_K2_SHIFT                                              5
+  #define USEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2                                                (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR_BB_K2_SHIFT                                          6
+  #define USEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR_BB_K2                                                 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT                                           7
+  #define USEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2                                                (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT                                          8
+  #define USEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR_BB_K2                                                 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR_BB_K2_SHIFT                                           9
+  #define USEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR_BB_K2                                                   (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR_BB_K2_SHIFT                                             10
+  #define USEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR_BB_K2                                                (0x1<<11) // Signals an unknown address in the fast-memory window.
+  #define USEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR_BB_K2_SHIFT                                          11
+  #define USEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO_BB_K2                                                      (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
+  #define USEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO_BB_K2_SHIFT                                                12
+  #define USEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO_BB_K2                                                      (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
+  #define USEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO_BB_K2_SHIFT                                                13
+  #define USEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO_BB_K2                                                          (0x1<<14) // Error in CAM_OUT fifo in cam block.
+  #define USEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO_BB_K2_SHIFT                                                    14
+  #define USEM_REG_INT_STS_CLR_0_FIN_FIFO_BB_K2                                                              (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
+  #define USEM_REG_INT_STS_CLR_0_FIN_FIFO_BB_K2_SHIFT                                                        15
+  #define USEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR_BB_K2                                                     (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
+  #define USEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR_BB_K2_SHIFT                                               16
+  #define USEM_REG_INT_STS_CLR_0_THREAD_OVERRUN_BB_K2                                                        (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
+  #define USEM_REG_INT_STS_CLR_0_THREAD_OVERRUN_BB_K2_SHIFT                                                  17
+  #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2                                             (0x1<<18) // Error in external store sync FIFO push logic.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR_BB_K2_SHIFT                                       18
+  #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_BB_K2                                              (0x1<<19) // Error in external store sync FIFO pop logic.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_BB_K2_SHIFT                                        19
+  #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2                                              (0x1<<20) // Error in external load sync FIFO push logic.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_BB_K2_SHIFT                                        20
+  #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2                                               (0x1<<21) // Error in external load sync FIFO pop logic.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR_BB_K2_SHIFT                                         21
+  #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR_BB_K2                                                 (0x1<<24) // Error in LS_SYNC_POP FIFO.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR_BB_K2_SHIFT                                           24
+  #define USEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR_BB_K2                                                   (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR_BB_K2_SHIFT                                             26
+  #define USEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_BB_K2                                                    (0x1<<27) // Error in LS_SYNC_POP FIFO.
+  #define USEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_BB_K2_SHIFT                                              27
+  #define USEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO_BB_K2                                                     (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
+  #define USEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO_BB_K2_SHIFT                                               29
+  #define USEM_REG_INT_STS_CLR_0_VFC_INTERRUPT_BB_K2                                                         (0x1<<30) // Error interrupt in VFC block.
+  #define USEM_REG_INT_STS_CLR_0_VFC_INTERRUPT_BB_K2_SHIFT                                                   30
+  #define USEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR_BB_K2                                                    (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
+  #define USEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR_BB_K2_SHIFT                                              31
+#define USEM_REG_INT_STS_1                                                                                   0x1900050UL //Access:R    DataWidth:0x20   // Multi Field Register.
+  #define USEM_REG_INT_STS_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5                                              (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
+  #define USEM_REG_INT_STS_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5_SHIFT                                        0
+  #define USEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_A_E5                                                  (0x1<<1) // Fast external store FIFO error of Storm_A
+  #define USEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT                                            1
+  #define USEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_B_E5                                                  (0x1<<2) // Fast external store FIFO error of Storm_B
+  #define USEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_B_E5_SHIFT                                            2
+  #define USEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_A_E5                                                    (0x1<<3) // fast external load FIFO error of Storm_A
+  #define USEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT                                              3
+  #define USEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_B_E5                                                    (0x1<<4) // fast external load FIFO error of Storm_B
+  #define USEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_B_E5_SHIFT                                              4
+  #define USEM_REG_INT_STS_1_FAST_RAM_WR_POP_ERROR_E5                                                        (0x1<<5) // Internal RAM pop error
+  #define USEM_REG_INT_STS_1_FAST_RAM_WR_POP_ERROR_E5_SHIFT                                                  5
+  #define USEM_REG_INT_STS_1_FAST_RAM_RD_PUSH_ERROR_E5                                                       (0x1<<6) // Internal RAM write error
+  #define USEM_REG_INT_STS_1_FAST_RAM_RD_PUSH_ERROR_E5_SHIFT                                                 6
+  #define USEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_A_E5                                                     (0x1<<7) // DRA RD FIFO error of Storm A
+  #define USEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT                                               7
+  #define USEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_B_E5                                                     (0x1<<8) // DRA RD FIFO error of Storm B
+  #define USEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT                                               8
+  #define USEM_REG_INT_STS_1_FAST_DRA_WR_POP_ERROR_A_E5                                                      (0x1<<9) // DRA RD FIFO error of Storm A
+  #define USEM_REG_INT_STS_1_FAST_DRA_WR_POP_ERROR_A_E5_SHIFT                                                9
+  #define USEM_REG_INT_STS_1_FAST_DRA_WR_POP_ERROR_B_E5                                                      (0x1<<10) // DRA RD FIFO error of Storm B
+  #define USEM_REG_INT_STS_1_FAST_DRA_WR_POP_ERROR_B_E5_SHIFT                                                10
+  #define USEM_REG_INT_STS_1_SEM_FAST_INVLD_ADDR_ERR_E5                                                      (0x1<<11) // Fast invalid address error
+  #define USEM_REG_INT_STS_1_SEM_FAST_INVLD_ADDR_ERR_E5_SHIFT                                                11
+  #define USEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_A_E5                                                        (0x1<<12) // Storm A stack_uf_attn interrupt
+  #define USEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_A_E5_SHIFT                                                  12
+  #define USEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_B_E5                                                        (0x1<<13) // Storm B stack_uf_attn interrupt
+  #define USEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_B_E5_SHIFT                                                  13
+  #define USEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_A_E5                                                        (0x1<<14) // Storm A stack_of_attn interrupt
+  #define USEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_A_E5_SHIFT                                                  14
+  #define USEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_B_E5                                                        (0x1<<15) // Storm B stack_of_attn interrupt
+  #define USEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_B_E5_SHIFT                                                  15
+  #define USEM_REG_INT_STS_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5                                                 (0x1<<16) // Storm A ldst_addr_ovflw_attn interrupt
+  #define USEM_REG_INT_STS_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5_SHIFT                                           16
+  #define USEM_REG_INT_STS_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5                                                 (0x1<<17) // Storm B ldst_addr_ovflw_attn interrupt
+  #define USEM_REG_INT_STS_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5_SHIFT                                           17
+  #define USEM_REG_INT_STS_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5                                              (0x1<<18) // Storm A non_aligned_access_attn interrupt
+  #define USEM_REG_INT_STS_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5_SHIFT                                        18
+  #define USEM_REG_INT_STS_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5                                              (0x1<<19) // Storm B non_aligned_access_attn interrupt
+  #define USEM_REG_INT_STS_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5_SHIFT                                        19
+  #define USEM_REG_INT_STS_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5                                                (0x1<<20) // Storm A division_by_zero_attn interrupt
+  #define USEM_REG_INT_STS_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5_SHIFT                                          20
+  #define USEM_REG_INT_STS_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5                                                (0x1<<21) // Storm B division_by_zero_attn interrupt
+  #define USEM_REG_INT_STS_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5_SHIFT                                          21
+  #define USEM_REG_INT_STS_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5                                           (0x1<<22) // Storm A illegal_runtime_value_attn interrupt
+  #define USEM_REG_INT_STS_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5_SHIFT                                     22
+  #define USEM_REG_INT_STS_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5                                           (0x1<<23) // Storm B illegal_runtime_value_attn interrupt
+  #define USEM_REG_INT_STS_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5_SHIFT                                     23
+  #define USEM_REG_INT_STS_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5                                            (0x1<<24) // load request is made while previous is still active; not fully read, Storm A
+  #define USEM_REG_INT_STS_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5_SHIFT                                      24
+  #define USEM_REG_INT_STS_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5                                            (0x1<<25) // load request is made while previous is still active; not fully read, Storm B
+  #define USEM_REG_INT_STS_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5_SHIFT                                      25
+  #define USEM_REG_INT_STS_1_CAM_RBC_FAST_OUT_ERROR_A_E5                                                     (0x1<<26) // Error in CAM_OUT fifo in cam block of STORM A
+  #define USEM_REG_INT_STS_1_CAM_RBC_FAST_OUT_ERROR_A_E5_SHIFT                                               26
+  #define USEM_REG_INT_STS_1_CAM_RBC_FAST_OUT_ERROR_B_E5                                                     (0x1<<27) // Error in CAM_OUT fifo in cam block of STORM B
+  #define USEM_REG_INT_STS_1_CAM_RBC_FAST_OUT_ERROR_B_E5_SHIFT                                               27
+  #define USEM_REG_INT_STS_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5                                                 (0x1<<28) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define USEM_REG_INT_STS_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5_SHIFT                                           28
+  #define USEM_REG_INT_STS_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5                                                 (0x1<<29) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define USEM_REG_INT_STS_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5_SHIFT                                           29
+  #define USEM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5                                                 (0x1<<30) // Error in CAM_LSB_INP fifo in cam block of STORM A
+  #define USEM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT                                           30
+  #define USEM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5                                                 (0x1<<31) // Error in CAM_LSB_INP fifo in cam block of STORM B.
+  #define USEM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5_SHIFT                                           31
+  #define USEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_BB_K2                                                       (0x1<<0) // An underflow error was detected in the Storm stack.
+  #define USEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_BB_K2_SHIFT                                                 0
+  #define USEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_BB_K2                                                       (0x1<<1) // An overflow error was detected in the Storm stack.
+  #define USEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT                                                 1
+  #define USEM_REG_INT_STS_1_STORM_RUNTIME_ERROR_BB_K2                                                       (0x1<<2) // The Storm detected an illegal runtime value.
+  #define USEM_REG_INT_STS_1_STORM_RUNTIME_ERROR_BB_K2_SHIFT                                                 2
+  #define USEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR_BB_K2                                                    (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
+  #define USEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT                                              3
+  #define USEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR_BB_K2                                                     (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
+  #define USEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR_BB_K2_SHIFT                                               4
+  #define USEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR_BB_K2                                                     (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
+  #define USEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR_BB_K2_SHIFT                                               5
+  #define USEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR_BB_K2                                                      (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
+  #define USEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR_BB_K2_SHIFT                                                6
+  #define USEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR_BB_K2                                                      (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define USEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT                                                7
+  #define USEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR_BB_K2                                                         (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
+  #define USEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT                                                   8
+  #define USEM_REG_INT_STS_1_INVLD_FOC_ERROR_BB_K2                                                           (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
+  #define USEM_REG_INT_STS_1_INVLD_FOC_ERROR_BB_K2_SHIFT                                                     9
+  #define USEM_REG_INT_STS_1_EXT_LD_LEN_ERROR_BB_K2                                                          (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define USEM_REG_INT_STS_1_EXT_LD_LEN_ERROR_BB_K2_SHIFT                                                    10
+  #define USEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR_BB_K2                                                       (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
+  #define USEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR_BB_K2_SHIFT                                                 11
+  #define USEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR_BB_K2                                                      (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
+  #define USEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR_BB_K2_SHIFT                                                12
+#define USEM_REG_INT_MASK_1                                                                                  0x1900054UL //Access:RW   DataWidth:0x20   // Multi Field Register.
+  #define USEM_REG_INT_MASK_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5                                             (0x1<<0) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.RBC_COMMON_ACCESS_COL_VFC_ERROR .
+  #define USEM_REG_INT_MASK_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5_SHIFT                                       0
+  #define USEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_A_E5                                                 (0x1<<1) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.FAST_EXT_STORE_PUSH_ERROR_A .
+  #define USEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT                                           1
+  #define USEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_B_E5                                                 (0x1<<2) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.FAST_EXT_STORE_PUSH_ERROR_B .
+  #define USEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_B_E5_SHIFT                                           2
+  #define USEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_A_E5                                                   (0x1<<3) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.FAST_EXT_LOAD_POP_ERROR_A .
+  #define USEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT                                             3
+  #define USEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_B_E5                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.FAST_EXT_LOAD_POP_ERROR_B .
+  #define USEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_B_E5_SHIFT                                             4
+  #define USEM_REG_INT_MASK_1_FAST_RAM_WR_POP_ERROR_E5                                                       (0x1<<5) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.FAST_RAM_WR_POP_ERROR .
+  #define USEM_REG_INT_MASK_1_FAST_RAM_WR_POP_ERROR_E5_SHIFT                                                 5
+  #define USEM_REG_INT_MASK_1_FAST_RAM_RD_PUSH_ERROR_E5                                                      (0x1<<6) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.FAST_RAM_RD_PUSH_ERROR .
+  #define USEM_REG_INT_MASK_1_FAST_RAM_RD_PUSH_ERROR_E5_SHIFT                                                6
+  #define USEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_A_E5                                                    (0x1<<7) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.FAST_DRA_RD_PUSH_ERROR_A .
+  #define USEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT                                              7
+  #define USEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_B_E5                                                    (0x1<<8) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.FAST_DRA_RD_PUSH_ERROR_B .
+  #define USEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT                                              8
+  #define USEM_REG_INT_MASK_1_FAST_DRA_WR_POP_ERROR_A_E5                                                     (0x1<<9) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.FAST_DRA_WR_POP_ERROR_A .
+  #define USEM_REG_INT_MASK_1_FAST_DRA_WR_POP_ERROR_A_E5_SHIFT                                               9
+  #define USEM_REG_INT_MASK_1_FAST_DRA_WR_POP_ERROR_B_E5                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.FAST_DRA_WR_POP_ERROR_B .
+  #define USEM_REG_INT_MASK_1_FAST_DRA_WR_POP_ERROR_B_E5_SHIFT                                               10
+  #define USEM_REG_INT_MASK_1_SEM_FAST_INVLD_ADDR_ERR_E5                                                     (0x1<<11) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.SEM_FAST_INVLD_ADDR_ERR .
+  #define USEM_REG_INT_MASK_1_SEM_FAST_INVLD_ADDR_ERR_E5_SHIFT                                               11
+  #define USEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_A_E5                                                       (0x1<<12) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.STORM_STACK_UF_ATTN_A .
+  #define USEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_A_E5_SHIFT                                                 12
+  #define USEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_B_E5                                                       (0x1<<13) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.STORM_STACK_UF_ATTN_B .
+  #define USEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_B_E5_SHIFT                                                 13
+  #define USEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_A_E5                                                       (0x1<<14) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.STORM_STACK_OF_ATTN_A .
+  #define USEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_A_E5_SHIFT                                                 14
+  #define USEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_B_E5                                                       (0x1<<15) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.STORM_STACK_OF_ATTN_B .
+  #define USEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_B_E5_SHIFT                                                 15
+  #define USEM_REG_INT_MASK_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5                                                (0x1<<16) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.STORM_LDST_ADDR_OVFLW_ATTN_A .
+  #define USEM_REG_INT_MASK_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5_SHIFT                                          16
+  #define USEM_REG_INT_MASK_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5                                                (0x1<<17) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.STORM_LDST_ADDR_OVFLW_ATTN_B .
+  #define USEM_REG_INT_MASK_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5_SHIFT                                          17
+  #define USEM_REG_INT_MASK_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5                                             (0x1<<18) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.STORM_NON_ALIGNED_ACCESS_ATTN_A .
+  #define USEM_REG_INT_MASK_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5_SHIFT                                       18
+  #define USEM_REG_INT_MASK_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5                                             (0x1<<19) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.STORM_NON_ALIGNED_ACCESS_ATTN_B .
+  #define USEM_REG_INT_MASK_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5_SHIFT                                       19
+  #define USEM_REG_INT_MASK_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5                                               (0x1<<20) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.STORM_DIVISION_BY_ZERO_ATTN_A .
+  #define USEM_REG_INT_MASK_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5_SHIFT                                         20
+  #define USEM_REG_INT_MASK_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5                                               (0x1<<21) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.STORM_DIVISION_BY_ZERO_ATTN_B .
+  #define USEM_REG_INT_MASK_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5_SHIFT                                         21
+  #define USEM_REG_INT_MASK_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5                                          (0x1<<22) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A .
+  #define USEM_REG_INT_MASK_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5_SHIFT                                    22
+  #define USEM_REG_INT_MASK_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5                                          (0x1<<23) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B .
+  #define USEM_REG_INT_MASK_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5_SHIFT                                    23
+  #define USEM_REG_INT_MASK_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5                                           (0x1<<24) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A .
+  #define USEM_REG_INT_MASK_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5_SHIFT                                     24
+  #define USEM_REG_INT_MASK_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5                                           (0x1<<25) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B .
+  #define USEM_REG_INT_MASK_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5_SHIFT                                     25
+  #define USEM_REG_INT_MASK_1_CAM_RBC_FAST_OUT_ERROR_A_E5                                                    (0x1<<26) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.CAM_RBC_FAST_OUT_ERROR_A .
+  #define USEM_REG_INT_MASK_1_CAM_RBC_FAST_OUT_ERROR_A_E5_SHIFT                                              26
+  #define USEM_REG_INT_MASK_1_CAM_RBC_FAST_OUT_ERROR_B_E5                                                    (0x1<<27) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.CAM_RBC_FAST_OUT_ERROR_B .
+  #define USEM_REG_INT_MASK_1_CAM_RBC_FAST_OUT_ERROR_B_E5_SHIFT                                              27
+  #define USEM_REG_INT_MASK_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5                                                (0x1<<28) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.CAM_RBC_FAST_MSB_INP_ERROR_A .
+  #define USEM_REG_INT_MASK_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5_SHIFT                                          28
+  #define USEM_REG_INT_MASK_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5                                                (0x1<<29) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.CAM_RBC_FAST_MSB_INP_ERROR_B .
+  #define USEM_REG_INT_MASK_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5_SHIFT                                          29
+  #define USEM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5                                                (0x1<<30) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.CAM_RBC_FAST_LSB_INP_ERROR_A .
+  #define USEM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT                                          30
+  #define USEM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5                                                (0x1<<31) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.CAM_RBC_FAST_LSB_INP_ERROR_B .
+  #define USEM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5_SHIFT                                          31
+  #define USEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_BB_K2                                                      (0x1<<0) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.STORM_STACK_UF_ATTN .
+  #define USEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_BB_K2_SHIFT                                                0
+  #define USEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_BB_K2                                                      (0x1<<1) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.STORM_STACK_OF_ATTN .
+  #define USEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT                                                1
+  #define USEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR_BB_K2                                                      (0x1<<2) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.STORM_RUNTIME_ERROR .
+  #define USEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR_BB_K2_SHIFT                                                2
+  #define USEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR_BB_K2                                                   (0x1<<3) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.EXT_LOAD_PEND_WR_ERROR .
+  #define USEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT                                             3
+  #define USEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR_BB_K2                                                    (0x1<<4) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.THREAD_RLS_ORUN_ERROR .
+  #define USEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR_BB_K2_SHIFT                                              4
+  #define USEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR_BB_K2                                                    (0x1<<5) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.THREAD_RLS_ALOC_ERROR .
+  #define USEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR_BB_K2_SHIFT                                              5
+  #define USEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR_BB_K2                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.THREAD_RLS_VLD_ERROR .
+  #define USEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR_BB_K2_SHIFT                                               6
+  #define USEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR_BB_K2                                                     (0x1<<7) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.EXT_THREAD_OOR_ERROR .
+  #define USEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT                                               7
+  #define USEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR_BB_K2                                                        (0x1<<8) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.ORD_ID_FIFO_ERROR .
+  #define USEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT                                                  8
+  #define USEM_REG_INT_MASK_1_INVLD_FOC_ERROR_BB_K2                                                          (0x1<<9) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.INVLD_FOC_ERROR .
+  #define USEM_REG_INT_MASK_1_INVLD_FOC_ERROR_BB_K2_SHIFT                                                    9
+  #define USEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR_BB_K2                                                         (0x1<<10) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.EXT_LD_LEN_ERROR .
+  #define USEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR_BB_K2_SHIFT                                                   10
+  #define USEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR_BB_K2                                                      (0x1<<11) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.THRD_ORD_FIFO_ERROR .
+  #define USEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR_BB_K2_SHIFT                                                11
+  #define USEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR_BB_K2                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.INVLD_THRD_ORD_ERROR .
+  #define USEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR_BB_K2_SHIFT                                               12
+#define USEM_REG_INT_STS_WR_1                                                                                0x1900058UL //Access:WR   DataWidth:0x20   // Multi Field Register.
+  #define USEM_REG_INT_STS_WR_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5                                           (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
+  #define USEM_REG_INT_STS_WR_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5_SHIFT                                     0
+  #define USEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5                                               (0x1<<1) // Fast external store FIFO error of Storm_A
+  #define USEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT                                         1
+  #define USEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_B_E5                                               (0x1<<2) // Fast external store FIFO error of Storm_B
+  #define USEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_B_E5_SHIFT                                         2
+  #define USEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_A_E5                                                 (0x1<<3) // fast external load FIFO error of Storm_A
+  #define USEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT                                           3
+  #define USEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_B_E5                                                 (0x1<<4) // fast external load FIFO error of Storm_B
+  #define USEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_B_E5_SHIFT                                           4
+  #define USEM_REG_INT_STS_WR_1_FAST_RAM_WR_POP_ERROR_E5                                                     (0x1<<5) // Internal RAM pop error
+  #define USEM_REG_INT_STS_WR_1_FAST_RAM_WR_POP_ERROR_E5_SHIFT                                               5
+  #define USEM_REG_INT_STS_WR_1_FAST_RAM_RD_PUSH_ERROR_E5                                                    (0x1<<6) // Internal RAM write error
+  #define USEM_REG_INT_STS_WR_1_FAST_RAM_RD_PUSH_ERROR_E5_SHIFT                                              6
+  #define USEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_A_E5                                                  (0x1<<7) // DRA RD FIFO error of Storm A
+  #define USEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT                                            7
+  #define USEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_B_E5                                                  (0x1<<8) // DRA RD FIFO error of Storm B
+  #define USEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT                                            8
+  #define USEM_REG_INT_STS_WR_1_FAST_DRA_WR_POP_ERROR_A_E5                                                   (0x1<<9) // DRA RD FIFO error of Storm A
+  #define USEM_REG_INT_STS_WR_1_FAST_DRA_WR_POP_ERROR_A_E5_SHIFT                                             9
+  #define USEM_REG_INT_STS_WR_1_FAST_DRA_WR_POP_ERROR_B_E5                                                   (0x1<<10) // DRA RD FIFO error of Storm B
+  #define USEM_REG_INT_STS_WR_1_FAST_DRA_WR_POP_ERROR_B_E5_SHIFT                                             10
+  #define USEM_REG_INT_STS_WR_1_SEM_FAST_INVLD_ADDR_ERR_E5                                                   (0x1<<11) // Fast invalid address error
+  #define USEM_REG_INT_STS_WR_1_SEM_FAST_INVLD_ADDR_ERR_E5_SHIFT                                             11
+  #define USEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_A_E5                                                     (0x1<<12) // Storm A stack_uf_attn interrupt
+  #define USEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_A_E5_SHIFT                                               12
+  #define USEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_B_E5                                                     (0x1<<13) // Storm B stack_uf_attn interrupt
+  #define USEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_B_E5_SHIFT                                               13
+  #define USEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_A_E5                                                     (0x1<<14) // Storm A stack_of_attn interrupt
+  #define USEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_A_E5_SHIFT                                               14
+  #define USEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_B_E5                                                     (0x1<<15) // Storm B stack_of_attn interrupt
+  #define USEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_B_E5_SHIFT                                               15
+  #define USEM_REG_INT_STS_WR_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5                                              (0x1<<16) // Storm A ldst_addr_ovflw_attn interrupt
+  #define USEM_REG_INT_STS_WR_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5_SHIFT                                        16
+  #define USEM_REG_INT_STS_WR_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5                                              (0x1<<17) // Storm B ldst_addr_ovflw_attn interrupt
+  #define USEM_REG_INT_STS_WR_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5_SHIFT                                        17
+  #define USEM_REG_INT_STS_WR_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5                                           (0x1<<18) // Storm A non_aligned_access_attn interrupt
+  #define USEM_REG_INT_STS_WR_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5_SHIFT                                     18
+  #define USEM_REG_INT_STS_WR_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5                                           (0x1<<19) // Storm B non_aligned_access_attn interrupt
+  #define USEM_REG_INT_STS_WR_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5_SHIFT                                     19
+  #define USEM_REG_INT_STS_WR_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5                                             (0x1<<20) // Storm A division_by_zero_attn interrupt
+  #define USEM_REG_INT_STS_WR_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5_SHIFT                                       20
+  #define USEM_REG_INT_STS_WR_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5                                             (0x1<<21) // Storm B division_by_zero_attn interrupt
+  #define USEM_REG_INT_STS_WR_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5_SHIFT                                       21
+  #define USEM_REG_INT_STS_WR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5                                        (0x1<<22) // Storm A illegal_runtime_value_attn interrupt
+  #define USEM_REG_INT_STS_WR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5_SHIFT                                  22
+  #define USEM_REG_INT_STS_WR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5                                        (0x1<<23) // Storm B illegal_runtime_value_attn interrupt
+  #define USEM_REG_INT_STS_WR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5_SHIFT                                  23
+  #define USEM_REG_INT_STS_WR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5                                         (0x1<<24) // load request is made while previous is still active; not fully read, Storm A
+  #define USEM_REG_INT_STS_WR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5_SHIFT                                   24
+  #define USEM_REG_INT_STS_WR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5                                         (0x1<<25) // load request is made while previous is still active; not fully read, Storm B
+  #define USEM_REG_INT_STS_WR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5_SHIFT                                   25
+  #define USEM_REG_INT_STS_WR_1_CAM_RBC_FAST_OUT_ERROR_A_E5                                                  (0x1<<26) // Error in CAM_OUT fifo in cam block of STORM A
+  #define USEM_REG_INT_STS_WR_1_CAM_RBC_FAST_OUT_ERROR_A_E5_SHIFT                                            26
+  #define USEM_REG_INT_STS_WR_1_CAM_RBC_FAST_OUT_ERROR_B_E5                                                  (0x1<<27) // Error in CAM_OUT fifo in cam block of STORM B
+  #define USEM_REG_INT_STS_WR_1_CAM_RBC_FAST_OUT_ERROR_B_E5_SHIFT                                            27
+  #define USEM_REG_INT_STS_WR_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5                                              (0x1<<28) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define USEM_REG_INT_STS_WR_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5_SHIFT                                        28
+  #define USEM_REG_INT_STS_WR_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5                                              (0x1<<29) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define USEM_REG_INT_STS_WR_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5_SHIFT                                        29
+  #define USEM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5                                              (0x1<<30) // Error in CAM_LSB_INP fifo in cam block of STORM A
+  #define USEM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT                                        30
+  #define USEM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5                                              (0x1<<31) // Error in CAM_LSB_INP fifo in cam block of STORM B.
+  #define USEM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5_SHIFT                                        31
+  #define USEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_BB_K2                                                    (0x1<<0) // An underflow error was detected in the Storm stack.
+  #define USEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_BB_K2_SHIFT                                              0
+  #define USEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_BB_K2                                                    (0x1<<1) // An overflow error was detected in the Storm stack.
+  #define USEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT                                              1
+  #define USEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR_BB_K2                                                    (0x1<<2) // The Storm detected an illegal runtime value.
+  #define USEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR_BB_K2_SHIFT                                              2
+  #define USEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2                                                 (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
+  #define USEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT                                           3
+  #define USEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR_BB_K2                                                  (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
+  #define USEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR_BB_K2_SHIFT                                            4
+  #define USEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR_BB_K2                                                  (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
+  #define USEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR_BB_K2_SHIFT                                            5
+  #define USEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR_BB_K2                                                   (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
+  #define USEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR_BB_K2_SHIFT                                             6
+  #define USEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR_BB_K2                                                   (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define USEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT                                             7
+  #define USEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR_BB_K2                                                      (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
+  #define USEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT                                                8
+  #define USEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR_BB_K2                                                        (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
+  #define USEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR_BB_K2_SHIFT                                                  9
+  #define USEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR_BB_K2                                                       (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define USEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR_BB_K2_SHIFT                                                 10
+  #define USEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR_BB_K2                                                    (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
+  #define USEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR_BB_K2_SHIFT                                              11
+  #define USEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR_BB_K2                                                   (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
+  #define USEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR_BB_K2_SHIFT                                             12
+#define USEM_REG_INT_STS_CLR_1                                                                               0x190005cUL //Access:RC   DataWidth:0x20   // Multi Field Register.
+  #define USEM_REG_INT_STS_CLR_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5                                          (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
+  #define USEM_REG_INT_STS_CLR_1_RBC_COMMON_ACCESS_COL_VFC_ERROR_E5_SHIFT                                    0
+  #define USEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5                                              (0x1<<1) // Fast external store FIFO error of Storm_A
+  #define USEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT                                        1
+  #define USEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_B_E5                                              (0x1<<2) // Fast external store FIFO error of Storm_B
+  #define USEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_B_E5_SHIFT                                        2
+  #define USEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_A_E5                                                (0x1<<3) // fast external load FIFO error of Storm_A
+  #define USEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT                                          3
+  #define USEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_B_E5                                                (0x1<<4) // fast external load FIFO error of Storm_B
+  #define USEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_B_E5_SHIFT                                          4
+  #define USEM_REG_INT_STS_CLR_1_FAST_RAM_WR_POP_ERROR_E5                                                    (0x1<<5) // Internal RAM pop error
+  #define USEM_REG_INT_STS_CLR_1_FAST_RAM_WR_POP_ERROR_E5_SHIFT                                              5
+  #define USEM_REG_INT_STS_CLR_1_FAST_RAM_RD_PUSH_ERROR_E5                                                   (0x1<<6) // Internal RAM write error
+  #define USEM_REG_INT_STS_CLR_1_FAST_RAM_RD_PUSH_ERROR_E5_SHIFT                                             6
+  #define USEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_A_E5                                                 (0x1<<7) // DRA RD FIFO error of Storm A
+  #define USEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT                                           7
+  #define USEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_B_E5                                                 (0x1<<8) // DRA RD FIFO error of Storm B
+  #define USEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT                                           8
+  #define USEM_REG_INT_STS_CLR_1_FAST_DRA_WR_POP_ERROR_A_E5                                                  (0x1<<9) // DRA RD FIFO error of Storm A
+  #define USEM_REG_INT_STS_CLR_1_FAST_DRA_WR_POP_ERROR_A_E5_SHIFT                                            9
+  #define USEM_REG_INT_STS_CLR_1_FAST_DRA_WR_POP_ERROR_B_E5                                                  (0x1<<10) // DRA RD FIFO error of Storm B
+  #define USEM_REG_INT_STS_CLR_1_FAST_DRA_WR_POP_ERROR_B_E5_SHIFT                                            10
+  #define USEM_REG_INT_STS_CLR_1_SEM_FAST_INVLD_ADDR_ERR_E5                                                  (0x1<<11) // Fast invalid address error
+  #define USEM_REG_INT_STS_CLR_1_SEM_FAST_INVLD_ADDR_ERR_E5_SHIFT                                            11
+  #define USEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_A_E5                                                    (0x1<<12) // Storm A stack_uf_attn interrupt
+  #define USEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_A_E5_SHIFT                                              12
+  #define USEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_B_E5                                                    (0x1<<13) // Storm B stack_uf_attn interrupt
+  #define USEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_B_E5_SHIFT                                              13
+  #define USEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_A_E5                                                    (0x1<<14) // Storm A stack_of_attn interrupt
+  #define USEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_A_E5_SHIFT                                              14
+  #define USEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_B_E5                                                    (0x1<<15) // Storm B stack_of_attn interrupt
+  #define USEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_B_E5_SHIFT                                              15
+  #define USEM_REG_INT_STS_CLR_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5                                             (0x1<<16) // Storm A ldst_addr_ovflw_attn interrupt
+  #define USEM_REG_INT_STS_CLR_1_STORM_LDST_ADDR_OVFLW_ATTN_A_E5_SHIFT                                       16
+  #define USEM_REG_INT_STS_CLR_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5                                             (0x1<<17) // Storm B ldst_addr_ovflw_attn interrupt
+  #define USEM_REG_INT_STS_CLR_1_STORM_LDST_ADDR_OVFLW_ATTN_B_E5_SHIFT                                       17
+  #define USEM_REG_INT_STS_CLR_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5                                          (0x1<<18) // Storm A non_aligned_access_attn interrupt
+  #define USEM_REG_INT_STS_CLR_1_STORM_NON_ALIGNED_ACCESS_ATTN_A_E5_SHIFT                                    18
+  #define USEM_REG_INT_STS_CLR_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5                                          (0x1<<19) // Storm B non_aligned_access_attn interrupt
+  #define USEM_REG_INT_STS_CLR_1_STORM_NON_ALIGNED_ACCESS_ATTN_B_E5_SHIFT                                    19
+  #define USEM_REG_INT_STS_CLR_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5                                            (0x1<<20) // Storm A division_by_zero_attn interrupt
+  #define USEM_REG_INT_STS_CLR_1_STORM_DIVISION_BY_ZERO_ATTN_A_E5_SHIFT                                      20
+  #define USEM_REG_INT_STS_CLR_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5                                            (0x1<<21) // Storm B division_by_zero_attn interrupt
+  #define USEM_REG_INT_STS_CLR_1_STORM_DIVISION_BY_ZERO_ATTN_B_E5_SHIFT                                      21
+  #define USEM_REG_INT_STS_CLR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5                                       (0x1<<22) // Storm A illegal_runtime_value_attn interrupt
+  #define USEM_REG_INT_STS_CLR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_A_E5_SHIFT                                 22
+  #define USEM_REG_INT_STS_CLR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5                                       (0x1<<23) // Storm B illegal_runtime_value_attn interrupt
+  #define USEM_REG_INT_STS_CLR_1_STORM_ILLEGAL_RUNTIME_VALUE_ATTN_B_E5_SHIFT                                 23
+  #define USEM_REG_INT_STS_CLR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5                                        (0x1<<24) // load request is made while previous is still active; not fully read, Storm A
+  #define USEM_REG_INT_STS_CLR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_A_E5_SHIFT                                  24
+  #define USEM_REG_INT_STS_CLR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5                                        (0x1<<25) // load request is made while previous is still active; not fully read, Storm B
+  #define USEM_REG_INT_STS_CLR_1_MUX_RBC_FAST_LOAD_PEND_WR_ERROR_B_E5_SHIFT                                  25
+  #define USEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_OUT_ERROR_A_E5                                                 (0x1<<26) // Error in CAM_OUT fifo in cam block of STORM A
+  #define USEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_OUT_ERROR_A_E5_SHIFT                                           26
+  #define USEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_OUT_ERROR_B_E5                                                 (0x1<<27) // Error in CAM_OUT fifo in cam block of STORM B
+  #define USEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_OUT_ERROR_B_E5_SHIFT                                           27
+  #define USEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5                                             (0x1<<28) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define USEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_MSB_INP_ERROR_A_E5_SHIFT                                       28
+  #define USEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5                                             (0x1<<29) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define USEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_MSB_INP_ERROR_B_E5_SHIFT                                       29
+  #define USEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5                                             (0x1<<30) // Error in CAM_LSB_INP fifo in cam block of STORM A
+  #define USEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT                                       30
+  #define USEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5                                             (0x1<<31) // Error in CAM_LSB_INP fifo in cam block of STORM B.
+  #define USEM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_B_E5_SHIFT                                       31
+  #define USEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_BB_K2                                                   (0x1<<0) // An underflow error was detected in the Storm stack.
+  #define USEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_BB_K2_SHIFT                                             0
+  #define USEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_BB_K2                                                   (0x1<<1) // An overflow error was detected in the Storm stack.
+  #define USEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT                                             1
+  #define USEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR_BB_K2                                                   (0x1<<2) // The Storm detected an illegal runtime value.
+  #define USEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR_BB_K2_SHIFT                                             2
+  #define USEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2                                                (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
+  #define USEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT                                          3
+  #define USEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR_BB_K2                                                 (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
+  #define USEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR_BB_K2_SHIFT                                           4
+  #define USEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR_BB_K2                                                 (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
+  #define USEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR_BB_K2_SHIFT                                           5
+  #define USEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR_BB_K2                                                  (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
+  #define USEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR_BB_K2_SHIFT                                            6
+  #define USEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR_BB_K2                                                  (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
+  #define USEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT                                            7
+  #define USEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR_BB_K2                                                     (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
+  #define USEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT                                               8
+  #define USEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR_BB_K2                                                       (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
+  #define USEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR_BB_K2_SHIFT                                                 9
+  #define USEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR_BB_K2                                                      (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
+  #define USEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR_BB_K2_SHIFT                                                10
+  #define USEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR_BB_K2                                                   (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
+  #define USEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR_BB_K2_SHIFT                                             11
+  #define USEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR_BB_K2                                                  (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
+  #define USEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR_BB_K2_SHIFT                                            12
+#define USEM_REG_INT_STS_2_E5                                                                                0x1900060UL //Access:R    DataWidth:0x1f   // Multi Field Register.
+  #define USEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5                                                 (0x1<<0) // Fast FIN FIFO error of Storm A.
+  #define USEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5_SHIFT                                           0
+  #define USEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5                                                 (0x1<<1) // Fast FIN FIFO error of Storm B
+  #define USEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT                                           1
+  #define USEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5                                               (0x1<<2) // Fast Debug FIFO error of Storm A
+  #define USEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5_SHIFT                                         2
+  #define USEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5                                               (0x1<<3) // Fast Debug FIFO error of Storm B
+  #define USEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT                                         3
+  #define USEM_REG_INT_STS_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5                                                (0x1<<4) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define USEM_REG_INT_STS_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5_SHIFT                                          4
+  #define USEM_REG_INT_STS_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5                                                (0x1<<5) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define USEM_REG_INT_STS_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5_SHIFT                                          5
+  #define USEM_REG_INT_STS_2_VFC_INTERRUPT_E5                                                                (0x1<<6) // interrupt from VFC block
+  #define USEM_REG_INT_STS_2_VFC_INTERRUPT_E5_SHIFT                                                          6
+  #define USEM_REG_INT_STS_2_MUX_RBC_VFC_FIFO_ERROR_E5                                                       (0x1<<7) // VFC FIFO error
+  #define USEM_REG_INT_STS_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT                                                 7
+  #define USEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_A_E5                                                    (0x1<<8) // Error in FOC error of Storm A.
+  #define USEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT                                              8
+  #define USEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_B_E5                                                    (0x1<<9) // Error in FOC error of Storm B.
+  #define USEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_B_E5_SHIFT                                              9
+  #define USEM_REG_INT_STS_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5                                                  (0x1<<10) // Invalid allocated thread request with partial FIN of Storm A.
+  #define USEM_REG_INT_STS_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5_SHIFT                                            10
+  #define USEM_REG_INT_STS_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5                                                  (0x1<<11) // Invalid allocated thread request with partial FIN of Storm B.
+  #define USEM_REG_INT_STS_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5_SHIFT                                            11
+  #define USEM_REG_INT_STS_2_CAM_RBC_INPUT_FIFO_ERROR_E5                                                     (0x1<<12) // Cam input FIFO error
+  #define USEM_REG_INT_STS_2_CAM_RBC_INPUT_FIFO_ERROR_E5_SHIFT                                               12
+  #define USEM_REG_INT_STS_2_ARB_RBC_FIFO_ERROR_A_E5                                                         (0x1<<13) // Pre-fetch FIFO error of Storm A.
+  #define USEM_REG_INT_STS_2_ARB_RBC_FIFO_ERROR_A_E5_SHIFT                                                   13
+  #define USEM_REG_INT_STS_2_ARB_RBC_FIFO_ERROR_B_E5                                                         (0x1<<14) // Pre-fetch FIFO error of Storm B.
+  #define USEM_REG_INT_STS_2_ARB_RBC_FIFO_ERROR_B_E5_SHIFT                                                   14
+  #define USEM_REG_INT_STS_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5                                                 (0x1<<15) // Lock is acquired more than maximum configured time.
+  #define USEM_REG_INT_STS_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5_SHIFT                                           15
+  #define USEM_REG_INT_STS_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                                  (0x1<<16) // Ilegal assetion commands towards lock block.
+  #define USEM_REG_INT_STS_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5_SHIFT                                            16
+  #define USEM_REG_INT_STS_2_LOCK_RBC_REQ_RELEASE_ERROR_E5                                                   (0x1<<17) // Error when trying to release a lock which is not acquired (key does not match any lock)
+  #define USEM_REG_INT_STS_2_LOCK_RBC_REQ_RELEASE_ERROR_E5_SHIFT                                             17
+  #define USEM_REG_INT_STS_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5                                                 (0x1<<18) // Trying to acquire a lock which is already acquired.
+  #define USEM_REG_INT_STS_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5_SHIFT                                           18
+  #define USEM_REG_INT_STS_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5                                                (0x1<<19) // Trying to relinquish a key which does not exist.
+  #define USEM_REG_INT_STS_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5_SHIFT                                          19
+  #define USEM_REG_INT_STS_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5                                                (0x1<<20) // A lock acquired requrest is issued when all locks are used.
+  #define USEM_REG_INT_STS_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5_SHIFT                                          20
+  #define USEM_REG_INT_STS_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5                                                (0x1<<21) // Error when both Storm are stalled due to lock block (may indicate a dead lock).
+  #define USEM_REG_INT_STS_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5_SHIFT                                          21
+  #define USEM_REG_INT_STS_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5                                            (0x1<<22) // Fin done with remainning allocated threads STORM_A.
+  #define USEM_REG_INT_STS_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5_SHIFT                                      22
+  #define USEM_REG_INT_STS_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5                                            (0x1<<23) // Fin done with remainning allocated threads STORM_B.
+  #define USEM_REG_INT_STS_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5_SHIFT                                      23
+  #define USEM_REG_INT_STS_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5                                            (0x1<<24) // Fin new thread request when no thread is allocated for handler of Storm A.
+  #define USEM_REG_INT_STS_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5_SHIFT                                      24
+  #define USEM_REG_INT_STS_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5                                            (0x1<<25) // Fin new thread request when no thread is allocated for handler of Storm B.
+  #define USEM_REG_INT_STS_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5_SHIFT                                      25
+  #define USEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5                                      (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same range.
+  #define USEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5_SHIFT                                26
+  #define USEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5                                      (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same range.
+  #define USEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5_SHIFT                                27
+  #define USEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5                                         (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
+  #define USEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5_SHIFT                                   28
+  #define USEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5                                         (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
+  #define USEM_REG_INT_STS_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5_SHIFT                                   29
+  #define USEM_REG_INT_STS_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5                                          (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
+  #define USEM_REG_INT_STS_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT                                    30
+#define USEM_REG_INT_MASK_2_E5                                                                               0x1900064UL //Access:RW   DataWidth:0x1f   // Multi Field Register.
+  #define USEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5                                                (0x1<<0) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.RD_RBC_FAST_FIN_FIFO_ERROR_A .
+  #define USEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5_SHIFT                                          0
+  #define USEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5                                                (0x1<<1) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.RD_RBC_FAST_FIN_FIFO_ERROR_B .
+  #define USEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT                                          1
+  #define USEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5                                              (0x1<<2) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.SYNC_RBC_FAST_DBG_PUSH_ERROR_A .
+  #define USEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5_SHIFT                                        2
+  #define USEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5                                              (0x1<<3) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.SYNC_RBC_FAST_DBG_PUSH_ERROR_B .
+  #define USEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT                                        3
+  #define USEM_REG_INT_MASK_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5                                               (0x1<<4) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.CAM_RBC_FAST_MSB2_INP_ERROR_A .
+  #define USEM_REG_INT_MASK_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5_SHIFT                                         4
+  #define USEM_REG_INT_MASK_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5                                               (0x1<<5) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.CAM_RBC_FAST_MSB2_INP_ERROR_B .
+  #define USEM_REG_INT_MASK_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5_SHIFT                                         5
+  #define USEM_REG_INT_MASK_2_VFC_INTERRUPT_E5                                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.VFC_INTERRUPT .
+  #define USEM_REG_INT_MASK_2_VFC_INTERRUPT_E5_SHIFT                                                         6
+  #define USEM_REG_INT_MASK_2_MUX_RBC_VFC_FIFO_ERROR_E5                                                      (0x1<<7) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.MUX_RBC_VFC_FIFO_ERROR .
+  #define USEM_REG_INT_MASK_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT                                                7
+  #define USEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_A_E5                                                   (0x1<<8) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.FIN_RBC_INVLD_FOC_ERROR_A .
+  #define USEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT                                             8
+  #define USEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_B_E5                                                   (0x1<<9) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.FIN_RBC_INVLD_FOC_ERROR_B .
+  #define USEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_B_E5_SHIFT                                             9
+  #define USEM_REG_INT_MASK_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5                                                 (0x1<<10) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.FIN_RBC_INVLD_ALLOC_ERROR_A .
+  #define USEM_REG_INT_MASK_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5_SHIFT                                           10
+  #define USEM_REG_INT_MASK_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5                                                 (0x1<<11) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.FIN_RBC_INVLD_ALLOC_ERROR_B .
+  #define USEM_REG_INT_MASK_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5_SHIFT                                           11
+  #define USEM_REG_INT_MASK_2_CAM_RBC_INPUT_FIFO_ERROR_E5                                                    (0x1<<12) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.CAM_RBC_INPUT_FIFO_ERROR .
+  #define USEM_REG_INT_MASK_2_CAM_RBC_INPUT_FIFO_ERROR_E5_SHIFT                                              12
+  #define USEM_REG_INT_MASK_2_ARB_RBC_FIFO_ERROR_A_E5                                                        (0x1<<13) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.ARB_RBC_FIFO_ERROR_A .
+  #define USEM_REG_INT_MASK_2_ARB_RBC_FIFO_ERROR_A_E5_SHIFT                                                  13
+  #define USEM_REG_INT_MASK_2_ARB_RBC_FIFO_ERROR_B_E5                                                        (0x1<<14) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.ARB_RBC_FIFO_ERROR_B .
+  #define USEM_REG_INT_MASK_2_ARB_RBC_FIFO_ERROR_B_E5_SHIFT                                                  14
+  #define USEM_REG_INT_MASK_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5                                                (0x1<<15) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.LOCK_RBC_REQ_MAX_STALL_ERROR .
+  #define USEM_REG_INT_MASK_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5_SHIFT                                          15
+  #define USEM_REG_INT_MASK_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                                 (0x1<<16) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.LOCK_RBC_REQ_CMD_RATE_ERROR .
+  #define USEM_REG_INT_MASK_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5_SHIFT                                           16
+  #define USEM_REG_INT_MASK_2_LOCK_RBC_REQ_RELEASE_ERROR_E5                                                  (0x1<<17) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.LOCK_RBC_REQ_RELEASE_ERROR .
+  #define USEM_REG_INT_MASK_2_LOCK_RBC_REQ_RELEASE_ERROR_E5_SHIFT                                            17
+  #define USEM_REG_INT_MASK_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5                                                (0x1<<18) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.LOCK_RBC_REQ_REDUNDENT_ERROR .
+  #define USEM_REG_INT_MASK_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5_SHIFT                                          18
+  #define USEM_REG_INT_MASK_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5                                               (0x1<<19) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.LOCK_RBC_REQ_RELINQUISH_ERROR .
+  #define USEM_REG_INT_MASK_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5_SHIFT                                         19
+  #define USEM_REG_INT_MASK_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5                                               (0x1<<20) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.LOCK_RBC_REQ_STALL_FULL_ERROR .
+  #define USEM_REG_INT_MASK_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5_SHIFT                                         20
+  #define USEM_REG_INT_MASK_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5                                               (0x1<<21) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.LOCK_RBC_REQ_DUAL_STALL_ERROR .
+  #define USEM_REG_INT_MASK_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5_SHIFT                                         21
+  #define USEM_REG_INT_MASK_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5                                           (0x1<<22) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A .
+  #define USEM_REG_INT_MASK_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5_SHIFT                                     22
+  #define USEM_REG_INT_MASK_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5                                           (0x1<<23) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B .
+  #define USEM_REG_INT_MASK_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5_SHIFT                                     23
+  #define USEM_REG_INT_MASK_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5                                           (0x1<<24) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.DRA_INT_GRC_NON_FREE_THRD_ERROR_A .
+  #define USEM_REG_INT_MASK_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5_SHIFT                                     24
+  #define USEM_REG_INT_MASK_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5                                           (0x1<<25) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.DRA_INT_GRC_NON_FREE_THRD_ERROR_B .
+  #define USEM_REG_INT_MASK_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5_SHIFT                                     25
+  #define USEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5                                     (0x1<<26) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A .
+  #define USEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5_SHIFT                               26
+  #define USEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5                                     (0x1<<27) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B .
+  #define USEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5_SHIFT                               27
+  #define USEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5                                        (0x1<<28) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A .
+  #define USEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5_SHIFT                                  28
+  #define USEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5                                        (0x1<<29) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B .
+  #define USEM_REG_INT_MASK_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5_SHIFT                                  29
+  #define USEM_REG_INT_MASK_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5                                         (0x1<<30) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_2.SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR .
+  #define USEM_REG_INT_MASK_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT                                   30
+#define USEM_REG_INT_STS_WR_2_E5                                                                             0x1900068UL //Access:WR   DataWidth:0x1f   // Multi Field Register.
+  #define USEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5                                              (0x1<<0) // Fast FIN FIFO error of Storm A.
+  #define USEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5_SHIFT                                        0
+  #define USEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5                                              (0x1<<1) // Fast FIN FIFO error of Storm B
+  #define USEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT                                        1
+  #define USEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5                                            (0x1<<2) // Fast Debug FIFO error of Storm A
+  #define USEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5_SHIFT                                      2
+  #define USEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5                                            (0x1<<3) // Fast Debug FIFO error of Storm B
+  #define USEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT                                      3
+  #define USEM_REG_INT_STS_WR_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5                                             (0x1<<4) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define USEM_REG_INT_STS_WR_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5_SHIFT                                       4
+  #define USEM_REG_INT_STS_WR_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5                                             (0x1<<5) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define USEM_REG_INT_STS_WR_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5_SHIFT                                       5
+  #define USEM_REG_INT_STS_WR_2_VFC_INTERRUPT_E5                                                             (0x1<<6) // interrupt from VFC block
+  #define USEM_REG_INT_STS_WR_2_VFC_INTERRUPT_E5_SHIFT                                                       6
+  #define USEM_REG_INT_STS_WR_2_MUX_RBC_VFC_FIFO_ERROR_E5                                                    (0x1<<7) // VFC FIFO error
+  #define USEM_REG_INT_STS_WR_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT                                              7
+  #define USEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5                                                 (0x1<<8) // Error in FOC error of Storm A.
+  #define USEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT                                           8
+  #define USEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_B_E5                                                 (0x1<<9) // Error in FOC error of Storm B.
+  #define USEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_B_E5_SHIFT                                           9
+  #define USEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5                                               (0x1<<10) // Invalid allocated thread request with partial FIN of Storm A.
+  #define USEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5_SHIFT                                         10
+  #define USEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5                                               (0x1<<11) // Invalid allocated thread request with partial FIN of Storm B.
+  #define USEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5_SHIFT                                         11
+  #define USEM_REG_INT_STS_WR_2_CAM_RBC_INPUT_FIFO_ERROR_E5                                                  (0x1<<12) // Cam input FIFO error
+  #define USEM_REG_INT_STS_WR_2_CAM_RBC_INPUT_FIFO_ERROR_E5_SHIFT                                            12
+  #define USEM_REG_INT_STS_WR_2_ARB_RBC_FIFO_ERROR_A_E5                                                      (0x1<<13) // Pre-fetch FIFO error of Storm A.
+  #define USEM_REG_INT_STS_WR_2_ARB_RBC_FIFO_ERROR_A_E5_SHIFT                                                13
+  #define USEM_REG_INT_STS_WR_2_ARB_RBC_FIFO_ERROR_B_E5                                                      (0x1<<14) // Pre-fetch FIFO error of Storm B.
+  #define USEM_REG_INT_STS_WR_2_ARB_RBC_FIFO_ERROR_B_E5_SHIFT                                                14
+  #define USEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5                                              (0x1<<15) // Lock is acquired more than maximum configured time.
+  #define USEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5_SHIFT                                        15
+  #define USEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                               (0x1<<16) // Ilegal assetion commands towards lock block.
+  #define USEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5_SHIFT                                         16
+  #define USEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_RELEASE_ERROR_E5                                                (0x1<<17) // Error when trying to release a lock which is not acquired (key does not match any lock)
+  #define USEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_RELEASE_ERROR_E5_SHIFT                                          17
+  #define USEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5                                              (0x1<<18) // Trying to acquire a lock which is already acquired.
+  #define USEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5_SHIFT                                        18
+  #define USEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5                                             (0x1<<19) // Trying to relinquish a key which does not exist.
+  #define USEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5_SHIFT                                       19
+  #define USEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5                                             (0x1<<20) // A lock acquired requrest is issued when all locks are used.
+  #define USEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5_SHIFT                                       20
+  #define USEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5                                             (0x1<<21) // Error when both Storm are stalled due to lock block (may indicate a dead lock).
+  #define USEM_REG_INT_STS_WR_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5_SHIFT                                       21
+  #define USEM_REG_INT_STS_WR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5                                         (0x1<<22) // Fin done with remainning allocated threads STORM_A.
+  #define USEM_REG_INT_STS_WR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5_SHIFT                                   22
+  #define USEM_REG_INT_STS_WR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5                                         (0x1<<23) // Fin done with remainning allocated threads STORM_B.
+  #define USEM_REG_INT_STS_WR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5_SHIFT                                   23
+  #define USEM_REG_INT_STS_WR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5                                         (0x1<<24) // Fin new thread request when no thread is allocated for handler of Storm A.
+  #define USEM_REG_INT_STS_WR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5_SHIFT                                   24
+  #define USEM_REG_INT_STS_WR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5                                         (0x1<<25) // Fin new thread request when no thread is allocated for handler of Storm B.
+  #define USEM_REG_INT_STS_WR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5_SHIFT                                   25
+  #define USEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5                                   (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same range.
+  #define USEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5_SHIFT                             26
+  #define USEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5                                   (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same range.
+  #define USEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5_SHIFT                             27
+  #define USEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5                                      (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
+  #define USEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5_SHIFT                                28
+  #define USEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5                                      (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
+  #define USEM_REG_INT_STS_WR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5_SHIFT                                29
+  #define USEM_REG_INT_STS_WR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5                                       (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
+  #define USEM_REG_INT_STS_WR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT                                 30
+#define USEM_REG_INT_STS_CLR_2_E5                                                                            0x190006cUL //Access:RC   DataWidth:0x1f   // Multi Field Register.
+  #define USEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5                                             (0x1<<0) // Fast FIN FIFO error of Storm A.
+  #define USEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_A_E5_SHIFT                                       0
+  #define USEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5                                             (0x1<<1) // Fast FIN FIFO error of Storm B
+  #define USEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT                                       1
+  #define USEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5                                           (0x1<<2) // Fast Debug FIFO error of Storm A
+  #define USEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_A_E5_SHIFT                                     2
+  #define USEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5                                           (0x1<<3) // Fast Debug FIFO error of Storm B
+  #define USEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT                                     3
+  #define USEM_REG_INT_STS_CLR_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5                                            (0x1<<4) // Error in CAM_MSB_INP fifo in cam block of STORM A
+  #define USEM_REG_INT_STS_CLR_2_CAM_RBC_FAST_MSB2_INP_ERROR_A_E5_SHIFT                                      4
+  #define USEM_REG_INT_STS_CLR_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5                                            (0x1<<5) // Error in CAM_MSB_INP fifo in cam block of STORM B
+  #define USEM_REG_INT_STS_CLR_2_CAM_RBC_FAST_MSB2_INP_ERROR_B_E5_SHIFT                                      5
+  #define USEM_REG_INT_STS_CLR_2_VFC_INTERRUPT_E5                                                            (0x1<<6) // interrupt from VFC block
+  #define USEM_REG_INT_STS_CLR_2_VFC_INTERRUPT_E5_SHIFT                                                      6
+  #define USEM_REG_INT_STS_CLR_2_MUX_RBC_VFC_FIFO_ERROR_E5                                                   (0x1<<7) // VFC FIFO error
+  #define USEM_REG_INT_STS_CLR_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT                                             7
+  #define USEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5                                                (0x1<<8) // Error in FOC error of Storm A.
+  #define USEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT                                          8
+  #define USEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_B_E5                                                (0x1<<9) // Error in FOC error of Storm B.
+  #define USEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_B_E5_SHIFT                                          9
+  #define USEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5                                              (0x1<<10) // Invalid allocated thread request with partial FIN of Storm A.
+  #define USEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_ALLOC_ERROR_A_E5_SHIFT                                        10
+  #define USEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5                                              (0x1<<11) // Invalid allocated thread request with partial FIN of Storm B.
+  #define USEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_ALLOC_ERROR_B_E5_SHIFT                                        11
+  #define USEM_REG_INT_STS_CLR_2_CAM_RBC_INPUT_FIFO_ERROR_E5                                                 (0x1<<12) // Cam input FIFO error
+  #define USEM_REG_INT_STS_CLR_2_CAM_RBC_INPUT_FIFO_ERROR_E5_SHIFT                                           12
+  #define USEM_REG_INT_STS_CLR_2_ARB_RBC_FIFO_ERROR_A_E5                                                     (0x1<<13) // Pre-fetch FIFO error of Storm A.
+  #define USEM_REG_INT_STS_CLR_2_ARB_RBC_FIFO_ERROR_A_E5_SHIFT                                               13
+  #define USEM_REG_INT_STS_CLR_2_ARB_RBC_FIFO_ERROR_B_E5                                                     (0x1<<14) // Pre-fetch FIFO error of Storm B.
+  #define USEM_REG_INT_STS_CLR_2_ARB_RBC_FIFO_ERROR_B_E5_SHIFT                                               14
+  #define USEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5                                             (0x1<<15) // Lock is acquired more than maximum configured time.
+  #define USEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_MAX_STALL_ERROR_E5_SHIFT                                       15
+  #define USEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                              (0x1<<16) // Ilegal assetion commands towards lock block.
+  #define USEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5_SHIFT                                        16
+  #define USEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_RELEASE_ERROR_E5                                               (0x1<<17) // Error when trying to release a lock which is not acquired (key does not match any lock)
+  #define USEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_RELEASE_ERROR_E5_SHIFT                                         17
+  #define USEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5                                             (0x1<<18) // Trying to acquire a lock which is already acquired.
+  #define USEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_REDUNDENT_ERROR_E5_SHIFT                                       18
+  #define USEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5                                            (0x1<<19) // Trying to relinquish a key which does not exist.
+  #define USEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_RELINQUISH_ERROR_E5_SHIFT                                      19
+  #define USEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5                                            (0x1<<20) // A lock acquired requrest is issued when all locks are used.
+  #define USEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_STALL_FULL_ERROR_E5_SHIFT                                      20
+  #define USEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5                                            (0x1<<21) // Error when both Storm are stalled due to lock block (may indicate a dead lock).
+  #define USEM_REG_INT_STS_CLR_2_LOCK_RBC_REQ_DUAL_STALL_ERROR_E5_SHIFT                                      21
+  #define USEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5                                        (0x1<<22) // Fin done with remainning allocated threads STORM_A.
+  #define USEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_A_E5_SHIFT                                  22
+  #define USEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5                                        (0x1<<23) // Fin done with remainning allocated threads STORM_B.
+  #define USEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NO_ALLOC_THRD_ERROR_B_E5_SHIFT                                  23
+  #define USEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5                                        (0x1<<24) // Fin new thread request when no thread is allocated for handler of Storm A.
+  #define USEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_A_E5_SHIFT                                  24
+  #define USEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5                                        (0x1<<25) // Fin new thread request when no thread is allocated for handler of Storm B.
+  #define USEM_REG_INT_STS_CLR_2_DRA_INT_GRC_NON_FREE_THRD_ERROR_B_E5_SHIFT                                  25
+  #define USEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5                                  (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same range.
+  #define USEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_A_E5_SHIFT                            26
+  #define USEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5                                  (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same range.
+  #define USEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_RANGE_INTERSECT_ERROR_B_E5_SHIFT                            27
+  #define USEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5                                     (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
+  #define USEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_A_E5_SHIFT                               28
+  #define USEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5                                     (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
+  #define USEM_REG_INT_STS_CLR_2_FIN_GRC_IOR_MAP_OUT_OF_RANGE_ERROR_B_E5_SHIFT                               29
+  #define USEM_REG_INT_STS_CLR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5                                      (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
+  #define USEM_REG_INT_STS_CLR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT                                30
+#define USEM_REG_PRTY_MASK                                                                                   0x19000ccUL //Access:RW   DataWidth:0x3    // Multi Field Register.
+  #define USEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR                                                            (0x1<<0) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS.VFC_RBC_PARITY_ERROR .
+  #define USEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR_SHIFT                                                      0
+  #define USEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR                                                           (0x1<<1) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS.STORM_RF_PARITY_ERROR .
+  #define USEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR_SHIFT                                                     1
+  #define USEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR                                                            (0x1<<2) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS.REG_GEN_PARITY_ERROR .
+  #define USEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR_SHIFT                                                      2
+#define USEM_REG_PRTY_MASK_H_0_BB_K2                                                                         0x1900204UL //Access:RW   DataWidth:0x6    // Multi Field Register.
+  #define USEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_BB_K2                                                 (0x1<<0) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
+  #define USEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_BB_K2_SHIFT                                           0
+  #define USEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_K2                                                 (0x1<<1) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
+  #define USEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_K2_SHIFT                                           1
+  #define USEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2                                                     (0x1<<2) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
+  #define USEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT                                               2
+  #define USEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2                                                     (0x1<<3) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
+  #define USEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT                                               3
+  #define USEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2                                                     (0x1<<4) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
+  #define USEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT                                               4
+  #define USEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2                                                     (0x1<<5) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
+  #define USEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT                                               5
+#define USEM_REG_MEM_ECC_ENABLE_0_BB_K2                                                                      0x1900210UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define USEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN_BB_K2                                                  (0x1<<0) // Enable ECC for memory ecc instance usem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.USEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_usem.i_ecc_0 in module sem_slow_pas_buf_ram_usem
+  #define USEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN_BB_K2_SHIFT                                            0
+  #define USEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_BB_K2                                                  (0x1<<1) // Enable ECC for memory ecc instance usem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.USEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_usem.i_ecc_1 in module sem_slow_pas_buf_ram_usem
+  #define USEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_BB_K2_SHIFT                                            1
+#define USEM_REG_MEM_ECC_PARITY_ONLY_0_BB_K2                                                                 0x1900214UL //Access:RW   DataWidth:0x2    // Multi Field Register.
+  #define USEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY_BB_K2                                           (0x1<<0) // Set parity only for memory ecc instance usem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.USEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_usem.i_ecc_0 in module sem_slow_pas_buf_ram_usem
+  #define USEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY_BB_K2_SHIFT                                     0
+  #define USEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_BB_K2                                           (0x1<<1) // Set parity only for memory ecc instance usem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.USEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_usem.i_ecc_1 in module sem_slow_pas_buf_ram_usem
+  #define USEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_BB_K2_SHIFT                                     1
+#define USEM_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2                                                             0x1900218UL //Access:RC   DataWidth:0x2    // Multi Field Register.
+  #define USEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT_BB_K2                                    (0x1<<0) // Record if a correctable error occurred on memory ecc instance usem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.USEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_usem.i_ecc_0 in module sem_slow_pas_buf_ram_usem
+  #define USEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT_BB_K2_SHIFT                              0
+  #define USEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_BB_K2                                    (0x1<<1) // Record if a correctable error occurred on memory ecc instance usem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.USEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_usem.i_ecc_1 in module sem_slow_pas_buf_ram_usem
+  #define USEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_BB_K2_SHIFT                              1
+#define USEM_REG_MEM_ECC_EVENTS_BB_K2                                                                        0x190021cUL //Access:RC   DataWidth:0x20   // Count all the block memories ECC events.
+#define USEM_REG_ARB_CYCLE_SIZE_BB_K2                                                                        0x1900400UL //Access:RW   DataWidth:0x5    // The number of time_slots in the arbitration cycle.
+#define USEM_REG_VF_ERROR                                                                                    0x1900408UL //Access:WR   DataWidth:0x1    // This VF-split register provides read/clear access to the VF error received from the SDM for a DMA transfer. Reading this register will return the VF Error for value for the corresponding VF. Writing a 1 to this register will clear the error for the corresponding VF.
+#define USEM_REG_PF_ERROR                                                                                    0x190040cUL //Access:WR   DataWidth:0x1    // This PF-split register provides read/clear access to the PF error received from the SDM for a DMA transfer. Reading this register will return the PF Error for value for the corresponding PF. Writing a 1 to this register will clear the error for the corresponding PF.
+#define USEM_REG_VF_ERR_VECTOR                                                                               0x1900420UL //Access:WB_R DataWidth:0xf0   // This read-only register provides a vector of bits having an error indication per VF where the Bit position corresponds to the VFID.
+#define USEM_REG_VF_ERR_VECTOR_SIZE_BB                                                                       4
+#define USEM_REG_VF_ERR_VECTOR_SIZE_K2_E5                                                                    8
+#define USEM_REG_PF_ERR_VECTOR                                                                               0x1900440UL //Access:R    DataWidth:0x10   // This read-only register provides a vector of bits having an error indication per PF where the Bit position corresponds to the PFID.
+#define USEM_REG_CLEAR_STALL                                                                                 0x1900444UL //Access:RW   DataWidth:0x1    // Clear stall signal sent from local storm to external storms.
+#define USEM_REG_EXCEPTION_INT                                                                               0x1900448UL //Access:RW   DataWidth:0x10   // Provides a default PRAM address to be used for the handler in the event that the PRAM address retrieved from the interrupt table is out of range with regard to the actual PRAM size provided in the SEMI instance.
+#define USEM_REG_EXT_STORE_FREE_ENTRIES_BB_K2                                                                0x190044cUL //Access:R    DataWidth:0x6    // Number of free entries in the external STORE sync FIFO.
+#define USEM_REG_GPI_DATA_A_E5                                                                               0x1900450UL //Access:R    DataWidth:0x20   // Used to read the GPI input signals of Storm A.
+#define USEM_REG_GPI_DATA_BB_K2                                                                              0x1900450UL //Access:R    DataWidth:0x20   // Used to read the GPI input signals.
+#define USEM_REG_GPRE_SAMP_PERIOD_BB_K2                                                                      0x1900454UL //Access:RW   DataWidth:0x4    // Defines the number of system clocks from one sample of GPRE sync data and the next.
+#define USEM_REG_ALLOW_LP_SLEEP_THRD                                                                         0x1900458UL //Access:RW   DataWidth:0x1    // When set, this bit is used to allow low-power mode to be activated while threads are sleeping in the passive buffer, as long as the SEMI/Storm remains idle.
+#define USEM_REG_ECO_RESERVED                                                                                0x190045cUL //Access:RW   DataWidth:0x20   // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
+#define USEM_REG_PB_WR_SDM_DMA_MODE_E5                                                                       0x1900460UL //Access:RW   DataWidth:0x2    // This register can set the mode of the SDM DMA write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use regardless write mode. 11 - Disable write mode.
+#define USEM_REG_PB_WR_DRA_RD_CUT_THROUGH_MODE_E5                                                            0x1900464UL //Access:RW   DataWidth:0x1    // This register set the DRA RD block cut through mode in which write to a thread address section passive buffer may occur simultaneously with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut through mode active.
+#define USEM_REG_GPI_DATA_B_E5                                                                               0x1900468UL //Access:R    DataWidth:0x20   // Used to read the GPI input signals of Storm B.
+#define USEM_REG_FIC_FIFO_BB_K2                                                                              0x1900580UL //Access:WB_R DataWidth:0x80   // Used for debugging to read/write to/from the FIC FIFOs. The address selects which FIFO should be accessed.
+#define USEM_REG_FIC_FIFO_SIZE                                                                               4
+#define USEM_REG_FIC_MIN_MSG_BB_K2                                                                           0x1900600UL //Access:RW   DataWidth:0x6    // Per-FIC interface register array defines minimum number of cycles in the FIC interfaces after which the message can be sent to the passive register_file.
+#define USEM_REG_FIC_EMPTY_CT_MODE_BB_K2                                                                     0x1900620UL //Access:RW   DataWidth:0x1    // When set, enables the "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require that the available ("go") counter is non-zero before making a transfer request to the DRA arbiter and starting a transfer.
+#define USEM_REG_FIC_EMPTY_CT_CNT_BB_K2                                                                      0x1900624UL //Access:RC   DataWidth:0x18   // Statistics counter used to count the number of FIC messages that have been received on any FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
+#define USEM_REG_FOC_CREDIT                                                                                  0x1900680UL //Access:RW   DataWidth:0x8    // Array of registers provides the initial credits on each of the associatef FOC interfaces. Reading from this register provides the current FOR credit value.
+#define USEM_REG_FOC_CREDIT_SIZE                                                                             5
+#define USEM_REG_FULL_FOC_DRA_STRT_EN_BB_K2                                                                  0x19006c0UL //Access:RW   DataWidth:0x1    // When set, this bit allows the DRA read operation to start even when there are not enough credits on all the participating FOC interfaces to complete the entire transaction. The transfer will stall only when a transfer cycle is reached in which there are no interface credits, at which time the DRA transfer will remain stalled until the FOC destination(s) has at least a single credit. When this configuration is cleared, the DRA read transfer will not begin until there are enough credits on all the participating FOC interfaces for the entire transfer.
+#define USEM_REG_FIN_COMMAND_BB_K2                                                                           0x1900700UL //Access:WB_R DataWidth:0x164  // Last fin command that was read from fifo. Its spelling in FIN_FIFO register.
+#define USEM_REG_FIN_COMMAND_SIZE                                                                            16
+#define USEM_REG_FIN_FIFO_BB_K2                                                                              0x1900800UL //Access:WB_R DataWidth:0x164  // READ ONLY FOR DEBUGGING! [5:0]   start_rp_foc3; [11:6] start_rp_foc2;  [17:12]   start_rp_foc1; [23:18] start_rp_foc0;  [29:24]   end_rp_foc3; [35:30] end_rp_foc2; [41:36]   end_rp_foc1; [47:42]   end_rp_foc0; [53:48]   lowest rp; [59:54]   highest rp; [65:60]   store start rp; [71:66]   store end rp; [77:72]   load start rp; [83:78]   load end rp; [85:84]   priority; [101:86]  pram address; [102] pas; [103] foc3; [104] foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:0] is valid.
+#define USEM_REG_FIN_FIFO_SIZE                                                                               16
+#define USEM_REG_INVLD_PAS_WR_EN_BB_K2                                                                       0x1900900UL //Access:RW   DataWidth:0x1    // When set, an attempt to write to the passive buffer over the external passive interface will be enabled even if the partition being written is owned by a thread whose valid bit is not set. Otherwise if cleared, the transfer will be stalled.
+#define USEM_REG_ARBITER_REQUEST_BB_K2                                                                       0x1900980UL //Access:R    DataWidth:0x5    // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2.
+#define USEM_REG_ARBITER_SELECT_BB_K2                                                                        0x1900984UL //Access:R    DataWidth:0x5    // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2.
+#define USEM_REG_ARBITER_SLOT_BB_K2                                                                          0x1900988UL //Access:R    DataWidth:0x5    // Dra arbiter last slot.
+#define USEM_REG_ARB_AS_DEF_BB_K2                                                                            0x1900a00UL //Access:RW   DataWidth:0x3    // Two-dimensional register array is used to define each of four arbitration schemes used by the main DRA arbiter. For this, bits 4:3 of the offset are used to select the arbitration scheme 0-3. Bits 2:0 of the offset are used to define the five priority sources for the selected scheme, where for each priority (0-4), an arbiter source is assigned. Valid values for these configurations are the source enumerations, where FIC0=0x0, FIC1=0x1, wake priority0=0x2, wake priority1=0x3 and wake priority2=0x4. Note that there are holes in the indirect offset address which always return zero when read. These exist at offsets 0x5-0x7, 0xd-0xf, 0x15-0x17 and 0x1d-0x1f.
+#define USEM_REG_ARB_AS_DEF_SIZE                                                                             32
+#define USEM_REG_ARB_TS_AS_BB_K2                                                                             0x1900a80UL //Access:RW   DataWidth:0x2    // Register array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
+#define USEM_REG_ARB_TS_AS_SIZE                                                                              20
+#define USEM_REG_NUM_OF_THREADS                                                                              0x1900b00UL //Access:R    DataWidth:0x8    // The number of currently free threads (in invalid state).
+#define USEM_REG_THREAD_ERROR_LOW_E5                                                                         0x1900b04UL //Access:R    DataWidth:0x20   // Thread error low indication. Represents threads 31 -0
+#define USEM_REG_THREAD_ERROR_BB_K2                                                                          0x1900b04UL //Access:R    DataWidth:0x10   // Thread error indication.
+#define USEM_REG_THREAD_RDY_BB_K2                                                                            0x1900b08UL //Access:R    DataWidth:0x10   // Thread ready indication.
+#define USEM_REG_THREAD_SET_NUM                                                                              0x1900b0cUL //Access:W    DataWidth:0x6    // Thread ID. Write thread ID will set ready indication for this thread ID.
+#define USEM_REG_THREAD_VALID_BB_K2                                                                          0x1900b10UL //Access:R    DataWidth:0x10   // Valid sleeping threads.
+#define USEM_REG_THREADS_LIST_BB_K2                                                                          0x1900b14UL //Access:RW   DataWidth:0x10   // List of free threads.
+#define USEM_REG_THREAD_NUMBER_E5                                                                            0x1900b18UL //Access:RW   DataWidth:0x8    // Defines the maixmum number of supported threads in SEMI.
+#define USEM_REG_THREAD_ERROR_HIGH_E5                                                                        0x1900b1cUL //Access:R    DataWidth:0x18   // Thread error high indication. Represents threads  55-32
+#define USEM_REG_FOC_MIN_MESSAGE_CREDIT_E5                                                                   0x1900b40UL //Access:RW   DataWidth:0x8    // This field defines for each FOC the minimum message reuired for the FOC transfer to start.
+#define USEM_REG_FOC_MIN_MESSAGE_CREDIT_SIZE                                                                 5
+#define USEM_REG_ORDER_HEAD_BB_K2                                                                            0x1900c00UL //Access:RW   DataWidth:0x4    // This (indirect) register array of registers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
+#define USEM_REG_ORDER_HEAD_SIZE                                                                             16
+#define USEM_REG_ORDER_TAIL_BB_K2                                                                            0x1900c80UL //Access:RW   DataWidth:0x4    // This (indirect) register array of registers provides read/write access to the tail pointers assigned to each of the thread ordering queues.
+#define USEM_REG_ORDER_TAIL_SIZE                                                                             16
+#define USEM_REG_ORDER_EMPTY_BB_K2                                                                           0x1900d00UL //Access:RW   DataWidth:0x1    // This vector provides read-only access to the empty bit assigned to each of the thread ordering queues.
+#define USEM_REG_ORDER_EMPTY_SIZE                                                                            16
+#define USEM_REG_ORDER_LL_REG_BB_K2                                                                          0x1900d80UL //Access:RW   DataWidth:0x4    // This array of registers provides read/write access to each entry of the linked-list array of the thread-ordering queue. Because the actual depth is based on the number of threads supported by the design, which is a Verilog parameter, a 64-entry window is reserved in the register address space. The valid entries start at the base of the window and extend through the number of threads supported. The value in each indirect register contains linked-list pointer to the next thread in the associated queue..
+#define USEM_REG_ORDER_LL_REG_SIZE                                                                           16
+#define USEM_REG_ORDER_POP_EN_BB_K2                                                                          0x1900e00UL //Access:RW   DataWidth:0x10   // Provides access to the thread ordering queue pop-enable vector.
+#define USEM_REG_ORDER_WAKE_EN_BB_K2                                                                         0x1900e08UL //Access:RW   DataWidth:0x10   // Provides access to the thread ordering queue wake-enable vector.
+#define USEM_REG_PF_NUM_ORDER_BASE_BB_K2                                                                     0x1900e10UL //Access:RW   DataWidth:0x4    // This field defines the base value for the ordering queue selection when the PFNum is chosen to control this selection. The value of this register is added to PFNum and the result is used to select one of 16 ordering queues.
+#define USEM_REG_DBG_ALM_FULL                                                                                0x1901000UL //Access:RW   DataWidth:0x6    // Almost full for slow debug fifo.
+#define USEM_REG_PASSIVE_ALM_FULL                                                                            0x1901004UL //Access:RW   DataWidth:0x5    // The number of free entries in the sync FIFO between the external HW and the passive buffer; below which the PassiveFull is asserted.
+#define USEM_REG_SYNC_DRA_WR_ALM_FULL_BB_K2                                                                  0x1901008UL //Access:RW   DataWidth:0x5    // Almost full for sync dra_wr fifo (data from DRA to STORM).
+#define USEM_REG_SYNC_RAM_WR_ALM_FULL                                                                        0x190100cUL //Access:RW   DataWidth:0x6    // Almost full for sync ram_wr fifo.
+#define USEM_REG_SYNC_FOC_FIFO_WR_ALM_FULL_E5                                                                0x1901010UL //Access:RW   DataWidth:0x4    // Almost full for indication for FOC Sync FIFO.
+#define USEM_REG_SYNC_SDM_READY_FIFO_WR_ALM_FULL_E5                                                          0x1901014UL //Access:RW   DataWidth:0x3    // Almost full for indication for SDM READY FIFO.
+#define USEM_REG_SYNC_SDM_INC_FIFO_WR_ALM_FULL_E5                                                            0x1901018UL //Access:RW   DataWidth:0x3    // Almost full for indication for SDM Counter Increment FIFO.
+#define USEM_REG_STALL_ON_INT_E5                                                                             0x190101cUL //Access:RW   DataWidth:0x2    // 00 - No stall. 01 - Both cluster Stroms will be stalled on any unmasked error occurrence. 10 - All Stroms will be stalled on any unmasked error occurrence.
+#define USEM_REG_FIC0_A_MAX_THRDS_E5                                                                         0x1901020UL //Access:RW   DataWidth:0x6    // Defines the maximum supported threads that may be contained in FIC0 A queue. If FIC0 message  is received and number of threads equals to the configured value, FIC interface will be stalled untill number of queue threads drops below configured vlaue.
+#define USEM_REG_FIC0_X_MAX_THRDS_E5                                                                         0x1901024UL //Access:RW   DataWidth:0x6    // Defines the maximum supported threads that may be contained in FIC0 X queue. If FIC0 message  is received and number of threads equals to the configured value, FIC interface will be stalled untill number of queue threads drops below configured vlaue.
+#define USEM_REG_FIC0_B_MAX_THRDS_E5                                                                         0x1901028UL //Access:RW   DataWidth:0x6    // Defines the maximum supported threads that may be contained in FIC0 B queue. If FIC0 message  is received and number of threads equals to the configured value, FIC interface will be stalled untill number of queue threads drops below configured vlaue.
+#define USEM_REG_FIC1_A_MAX_THRDS_E5                                                                         0x190102cUL //Access:RW   DataWidth:0x6    // Defines the maximum supported threads that may be contained in FIC1 A queue. If FIC1 message is received and number of threads equals to the configured value, FIC interface will be stalled untill number of queue threads drops below configured vlaue.
+#define USEM_REG_DRA_EMPTY_BB_K2                                                                             0x1901100UL //Access:R    DataWidth:0x1    // Dra_empty.
+#define USEM_REG_EXT_PAS_EMPTY                                                                               0x1901104UL //Access:R    DataWidth:0x1    // EXT_PAS FIFO empty in sem_slow.
+#define USEM_REG_FIC_EMPTY                                                                                   0x1901120UL //Access:R    DataWidth:0x1    // Array of registers reflects associated FIC FIFO empty in sem_slow_fic.
+#define USEM_REG_SLOW_DBG_EMPTY_BB_K2                                                                        0x1901140UL //Access:R    DataWidth:0x1    // DBG FIFO is empty in sem_slow_ls_dbg.
+#define USEM_REG_SLOW_DRA_FIN_EMPTY_BB_K2                                                                    0x1901144UL //Access:R    DataWidth:0x1    // FIN fifo is empty in sem_slow_dra_sync.
+#define USEM_REG_SLOW_DRA_RD_EMPTY_BB_K2                                                                     0x1901148UL //Access:R    DataWidth:0x1    // DRA_RD pop fifo is empty in sem_slow_dra_sync.
+#define USEM_REG_SLOW_DRA_WR_EMPTY_BB_K2                                                                     0x190114cUL //Access:R    DataWidth:0x1    // DRA_WR push fifo is empty in sem_slow_dra_sync.
+#define USEM_REG_SLOW_EXT_STORE_EMPTY                                                                        0x1901150UL //Access:R    DataWidth:0x1    // EXT_STORE FIFO is empty in sem_slow_ls_ext.
+#define USEM_REG_SLOW_EXT_LOAD_EMPTY                                                                         0x1901154UL //Access:R    DataWidth:0x2    // EXT_LOAD FIFO is empty in sem_slow_ls_ext, bit 0 FIFO of Core A, bit 1 FIFO of Core B.
+#define USEM_REG_SLOW_RAM_RD_EMPTY                                                                           0x1901158UL //Access:R    DataWidth:0x1    // EXT_RD_RAM FIFO is empty in sem_slow_ls_ext.
+#define USEM_REG_SLOW_RAM_WR_EMPTY                                                                           0x190115cUL //Access:R    DataWidth:0x1    // EXT_WR_RAM FIFO is empty in sem_slow_ls_ext.
+#define USEM_REG_SYNC_DBG_EMPTY                                                                              0x1901160UL //Access:R    DataWidth:0x2    // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR debug FIFO of Core B
+#define USEM_REG_THREAD_FIFO_EMPTY_BB_K2                                                                     0x1901164UL //Access:R    DataWidth:0x1    // Indicates that the thread fifo is empty in sem_slow_dra_wr.
+#define USEM_REG_ORD_ID_FIFO_EMPTY_BB_K2                                                                     0x1901168UL //Access:R    DataWidth:0x1    // Indicates that the order ID fifo is empty in sem_slow_dra_wr.
+#define USEM_REG_PB_QUEUE_EMPTY_E5                                                                           0x190116cUL //Access:R    DataWidth:0xb    // If 1, the correspongding Queue is empty. Queues numeration: FOC_FIFO_IF - 0,  FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - 5,  WAKE_FIFO_PRIO_X - 6, WAKE_FIFO_PRI1_X - 7,FIC0_FIFO_B - 8, WAKE_FIFO_PRIO_B - 9,  WAKE_FIFO_PRI1_B - 10.
+#define USEM_REG_SYNC_FOC_FIFO_EMPTY_E5                                                                      0x1901170UL //Access:R    DataWidth:0x1    // FOC FIFO empty indication.
+#define USEM_REG_SYNC_FOC_PRE_FETCH_FIFO_EMPTY_E5                                                            0x1901174UL //Access:R    DataWidth:0x1    // FOC pre fetch FIFO empty indication.
+#define USEM_REG_EXT_PAS_FULL                                                                                0x1901200UL //Access:R    DataWidth:0x1    // EXT_PAS FIFO Full in sem_slow.
+#define USEM_REG_EXT_STORE_IF_FULL                                                                           0x1901204UL //Access:R    DataWidth:0x1    // EXT_STORE IF is full in sem_slow_ls_ext.
+#define USEM_REG_FIC_FULL                                                                                    0x1901220UL //Access:R    DataWidth:0x1    // Array of registers reflects associated FIC FIFO full in sem_slow_fic.
+#define USEM_REG_PAS_IF_FULL_BB_K2                                                                           0x1901240UL //Access:R    DataWidth:0x1    // Full from passive buffer asserted toward SDM.
+#define USEM_REG_RAM_IF_FULL                                                                                 0x1901244UL //Access:R    DataWidth:0x1    // EXT_RAM IF is full in sem_slow_ls_ram.
+#define USEM_REG_SLOW_DBG_ALM_FULL_BB_K2                                                                     0x1901248UL //Access:R    DataWidth:0x1    // DBG FIFO is almost full in sem_slow_ls_dbg according to the full threshold configuration.
+#define USEM_REG_SLOW_DBG_FULL_BB_K2                                                                         0x190124cUL //Access:R    DataWidth:0x1    // DBG FIFO is full in sem_slow_ls_dbg.
+#define USEM_REG_SLOW_DRA_FIN_FULL_BB_K2                                                                     0x1901250UL //Access:R    DataWidth:0x1    // FIN fifo is full in sem_slow_dra_sync (never may be active).
+#define USEM_REG_SLOW_DRA_RD_FULL_BB_K2                                                                      0x1901254UL //Access:R    DataWidth:0x1    // DRA_RD pop fifo is full in sem_slow_dra_sync.
+#define USEM_REG_SLOW_DRA_WR_FULL_BB_K2                                                                      0x1901258UL //Access:R    DataWidth:0x1    // DRA_WR push fifo is full in sem_slow_dra_sync.
+#define USEM_REG_SLOW_EXT_STORE_FULL                                                                         0x190125cUL //Access:R    DataWidth:0x2    // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIFO.
+#define USEM_REG_SLOW_EXT_LOAD_FULL                                                                          0x1901260UL //Access:R    DataWidth:0x2    // EXT_LOAD FIFO is full in sem_slow_ls_ext, bit 0 for Core A and bit 1 for Core B.
+#define USEM_REG_SLOW_RAM_RD_FULL                                                                            0x1901264UL //Access:R    DataWidth:0x1    // EXT_RD_RAM FIFO is full in sem_slow_ls_ext.
+#define USEM_REG_SLOW_RAM_WR_ALM_FULL                                                                        0x1901268UL //Access:R    DataWidth:0x1    // EXT_WR_RAM FIFO is almost full in sem_slow_ls_ext.
+#define USEM_REG_SLOW_RAM_WR_FULL                                                                            0x190126cUL //Access:R    DataWidth:0x1    // EXT_WR_RAM FIFO is full in sem_slow_ls_ext.
+#define USEM_REG_SYNC_DBG_FULL                                                                               0x1901270UL //Access:R    DataWidth:0x2    // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR debug FIFO of Core B.
+#define USEM_REG_THREAD_FIFO_FULL_BB_K2                                                                      0x1901274UL //Access:R    DataWidth:0x1    // Indicates that the thread fifo is full in sem_slow_dra_wr.
+#define USEM_REG_ORD_ID_FIFO_FULL_BB_K2                                                                      0x1901278UL //Access:R    DataWidth:0x1    // Indicates that the thread fifo is full in sem_slow_dra_wr.
+#define USEM_REG_SYNC_READY_FIFO_FULL_E5                                                                     0x190127cUL //Access:R    DataWidth:0x1    // Ready sync FIFO full indication.
+#define USEM_REG_SYNC_CNT_FIFO_FULL_E5                                                                       0x1901280UL //Access:R    DataWidth:0x1    // Counter increment sync FIFO full indication.
+#define USEM_REG_SYNC_FOC_FIFO_FULL_E5                                                                       0x1901284UL //Access:R    DataWidth:0x1    // sync FOC FIFO full indication.
+#define USEM_REG_THREAD_INTER_CNT_BB_K2                                                                      0x1901300UL //Access:RW   DataWidth:0x10   // Maximum value of threads interrupt counter; when it gets this value then interrupt to will be send if thread active from previous maximum value of this counter.
+#define USEM_REG_THREAD_INTER_CNT_ENABLE_BB_K2                                                               0x1901304UL //Access:RW   DataWidth:0x1    // Enable for start count of thread_inter_cnt.
+#define USEM_REG_THREAD_ORUN_NUM_BB_K2                                                                       0x1901308UL //Access:R    DataWidth:0x10   // Threads are sleeping in passive buffer more than thread_inter_cnt number of cycles.
+#define USEM_REG_SLOW_DBG_ACTIVE_BB_K2                                                                       0x1901400UL //Access:RW   DataWidth:0x1    // Debug mode is active.
+#define USEM_REG_SLOW_DBG_MODE_BB_K2                                                                         0x1901404UL //Access:RW   DataWidth:0x3    // Debug mode for slow debug bus.
+#define USEM_REG_DBG_FRAME_MODE_BB_K2                                                                        0x1901408UL //Access:RW   DataWidth:0x2    // Debug frame mode control for the SEMI debug bus. The following values apply: "00" - indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mode-1, which means bits 127:64 belong to fast debug and bits 63:0 belong to slow debug. "10" - indicates mode-2, which means bits 127:96 belong to fast debug and bits 95:0 belong to slow debug. "11" - indicates mode-3, which means all four words are provided by the slow debug.
+#define USEM_REG_DBG_EACH_CYLE_BB_K2                                                                         0x190140cUL //Access:RW   DataWidth:0x1    // 0=output every cycle; 1= output only when there is a change.
+#define USEM_REG_DBG_GPRE_VECT_BB_K2                                                                         0x1901410UL //Access:RW   DataWidth:0x8    // This 8-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug channel when they are accessed for read by the Storm during mode-6 debug (handler trace). For this, bit-0 corresponds with GPRE[0-3] and bit-7 corresponds with GPRE[28-31].
+#define USEM_REG_DBG_IF_FULL_BB_K2                                                                           0x1901414UL //Access:R    DataWidth:0x1    // DBG IF is full in sem_slow_ls_dbg.
+#define USEM_REG_DBG_MODE0_CFG_BB_K2                                                                         0x1901418UL //Access:RW   DataWidth:0x1    // 0=all the message; 1=partial message.
+#define USEM_REG_DBG_MODE0_CFG_CYCLE_BB_K2                                                                   0x190141cUL //Access:RW   DataWidth:0x5    // In case DebugMode0Config = 1; the additional cycles to extract to the debug bus.
+#define USEM_REG_DBG_MODE1_CFG_BB_K2                                                                         0x1901420UL //Access:RW   DataWidth:0x1    // 0=without the data; 1=with the data.
+#define USEM_REG_DBG_MSG_SRC_BB_K2                                                                           0x1901424UL //Access:RW   DataWidth:0x3    // This field is a mask used to enable (or filter) the various sources of DRA write debug packets. Setting a bit causes the corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1 and bit-2 corresponds with DRA writes from the passive buffer. This applicable only for debug mode=0.
+#define USEM_REG_DBG_QUEUE_PEFORMANCE_MON_STAT_E5                                                            0x1901428UL //Access:RW   DataWidth:0x1    // If 0, the statistic report the maximum value between following reads (when using read clear). If 1, report the current value.
+#define USEM_REG_PASSIVE_BUFFER_PERFORMANCE_MON_STAT_E5                                                      0x190142cUL //Access:RW   DataWidth:0x1    // Enable performance monitor statistics sent to SEM_PD.
+#define USEM_REG_DBG_QUEUE_FIC_MON_CNT_E5                                                                    0x1901430UL //Access:RC   DataWidth:0x20   // Report the number of received FIC transaction between two of the following register reads. The counter is incremanted only for the event IDs which have Debug Monitor event indication set.
+#define USEM_REG_DBG_QUEUE_FOC_MAX_VALUE_E5                                                                  0x1901434UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FOC queue.
+#define USEM_REG_DBG_QUEUE_FIC0_A_MAX_VALUE_E5                                                               0x1901438UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 A queue.
+#define USEM_REG_DBG_QUEUE_FIC1_A_MAX_VALUE_E5                                                               0x190143cUL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC1 A queue.
+#define USEM_REG_DBG_QUEUE_PRIO0_A_MAX_VALUE_E5                                                              0x1901440UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 A queue.
+#define USEM_REG_DBG_QUEUE_PRIO1_A_MAX_VALUE_E5                                                              0x1901444UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 A queue.
+#define USEM_REG_DBG_QUEUE_FIC0_X_MAX_VALUE_E5                                                               0x1901448UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 X queue.
+#define USEM_REG_DBG_QUEUE_PRIO0_X_MAX_VALUE_E5                                                              0x190144cUL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 X queue.
+#define USEM_REG_DBG_QUEUE_PRIO1_X_MAX_VALUE_E5                                                              0x1901450UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 X queue.
+#define USEM_REG_DBG_QUEUE_FIC0_B_MAX_VALUE_E5                                                               0x1901454UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 B queue.
+#define USEM_REG_DBG_QUEUE_PRIO0_B_MAX_VALUE_E5                                                              0x1901458UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 B queue.
+#define USEM_REG_DBG_QUEUE_PRIO1_B_MAX_VALUE_E5                                                              0x190145cUL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 B queue.
+#define USEM_REG_DBG_QUEUE_MAX_THREAD_VALUE_E5                                                               0x1901460UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of allocated threads in the system.
+#define USEM_REG_DBG_QUEUE_MAX_SLEEP_VALUE_E5                                                                0x1901464UL //Access:RC   DataWidth:0x6    // Report maximum/current value (according to passive_buffer_performance_mon_stat value) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does not include the threads pending in the queues.
+#define USEM_REG_DBG_OUT_DATA                                                                                0x1901500UL //Access:WB_R DataWidth:0x100  // Dbgmux output data
+#define USEM_REG_DBG_OUT_DATA_SIZE                                                                           8
+#define USEM_REG_DBG_OUT_VALID                                                                               0x1901520UL //Access:R    DataWidth:0x8    // Dbgmux output valid per Dword
+#define USEM_REG_DBG_OUT_FRAME                                                                               0x1901524UL //Access:R    DataWidth:0x8    // Dbgmux output frame per Dword
+#define USEM_REG_DBG_SELECT                                                                                  0x1901528UL //Access:RW   DataWidth:0x8    // DBMUX register for selecting a line to output
+#define USEM_REG_DBG_DWORD_ENABLE                                                                            0x190152cUL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output
+#define USEM_REG_DBG_SHIFT                                                                                   0x1901530UL //Access:RW   DataWidth:0x2    // DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).
+#define USEM_REG_DBG_FORCE_VALID                                                                             0x1901534UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define USEM_REG_DBG_FORCE_FRAME                                                                             0x1901538UL //Access:RW   DataWidth:0x4    // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).
+#define USEM_REG_EXT_PAS_FIFO_BB_K2                                                                          0x1908000UL //Access:WB_R DataWidth:0x4c   // Provides read-only access of the external passive FIFO. Intended for debug purposes.
+#define USEM_REG_EXT_PAS_FIFO_SIZE                                                                           76
+#define USEM_REG_INT_TABLE                                                                                   0x1910000UL //Access:RW   DataWidth:0x1e   // Interrupt table read/write access. This register is intended to be written only when the system is idle. The fields of the interrupt table are as follows. int_table[29] = Allocated per child;  int_table[28] = Increment type; int_table[27:23] = Counter select; int_table[22] = Counter insert; int_table[21:17] = GapSel; int_table[16] = Monitor enable; int_table[15:0] = PRAM Address;
+#define USEM_REG_INT_TABLE_SIZE                                                                              256
+#define USEM_REG_FIC_COUNTER_GROUP_E5                                                                        0x1911000UL //Access:RW   DataWidth:0x8    // This field enables a RD/WR access to the 24 counters of the "FIC Counters".
+#define USEM_REG_FIC_COUNTER_GROUP_SIZE                                                                      24
+#define USEM_REG_PB_THRD_STM_GROUP_E5                                                                        0x1912000UL //Access:R    DataWidth:0x17   // Read the State mahcine state of teh trheads. 0:4 - state. 5 - pending ready. 7:6 - Affinity type. 8 - Destination FOC. 9 - Destination Storm. 10 - counter increment ready. 15:11 - counter index. 16 - Debug monitor enable. 17 - Exlucsive. 22:18 - DRA size.
+#define USEM_REG_PB_THRD_STM_GROUP_SIZE                                                                      56
+#define USEM_REG_PASSIVE_BUFFER                                                                              0x1920000UL //Access:R    DataWidth:0x20   // Passive buffer memory read only.
+#define USEM_REG_PASSIVE_BUFFER_SIZE_BB_K2                                                                   2880
+#define USEM_REG_PASSIVE_BUFFER_SIZE_E5                                                                      12544
+#define USEM_REG_FIC_GAP_VECT_BB_K2                                                                          0x1900500UL //Access:WB   DataWidth:0x2c   // This array of nine 44-bit vectors provides a bit per register-quad, used to define the register-quad locations that should be included in gaps (discontinuities) within the DRA transfer, where bit-0 corresponds with IORs 0-3, and so on. To indicate a gap, the corresponding bit should be cleared. These gaps have a granularity of a register- quad (four IORs). For each DRA write transfer from whom the FIC is the source, one of nine gap vectors (or a default-gap vector) will be selected, based on the GapSelect field of the corresponding interrupt table entry. Any unused upper bits of the vector will be ignored and thus, can be written with any value.
+#define USEM_REG_FIC_GAP_VECT_E5                                                                             0x1930000UL //Access:WB   DataWidth:0x34   // This array of 24 x 52-bit vectors provides a bit per register-quad, used to define the register-quad locations that should be included in gaps (discontinuities) within the DRA transfer, where bit-0 corresponds with IORs 0-3, and so on. To indicate a gap, the corresponding bit should be cleared. These gaps have a granularity of a register- quad (four IORs). For each DRA write transfer from whom the FIC is the source, one of nine gap vectors (or a default-gap vector) will be selected, based on the GapSelect field of the corresponding interrupt table entry. Any unused upper bits of the vector will be ignored and thus, can be written with any value.
+#define USEM_REG_FIC_GAP_VECT_SIZE_BB_K2                                                                     18
+#define USEM_REG_FIC_GAP_VECT_SIZE_E5                                                                        48
+#define USEM_REG_FAST_MEMORY                                                                                 0x1940000UL //Access:RW   DataWidth:0x20   // See sem_fast.xls for its description.
+#define USEM_REG_FAST_MEMORY_SIZE                                                                            65536
+#define USEM_REG_PRAM                                                                                        0x1980000UL //Access:WB   DataWidth:0x30   // Pram memory.
+#define USEM_REG_PRAM_SIZE_BB                                                                                49152
+#define USEM_REG_PRAM_SIZE_K2                                                                                73728
+#define USEM_REG_PRAM_SIZE_E5                                                                                92160
+#define BAR0_MAP_REG_MSIX_TABLE                                                                              0x1c00000UL //Access:RW   DataWidth:0x20   // MSIX table
+#define BAR0_MAP_REG_MSIX_TABLE_SIZE                                                                         2048
+#define BAR0_MAP_REG_IGU_CMD                                                                                 0x1c02000UL //Access:RW   DataWidth:0x20   // IGU command memory
+#define BAR0_MAP_REG_IGU_CMD_SIZE                                                                            57344
+#define BAR0_MAP_REG_TSDM_RAM                                                                                0x1c80000UL //Access:RW   DataWidth:0x20   // TSDM RAM
+#define BAR0_MAP_REG_TSDM_RAM_SIZE                                                                           131072
+#define BAR0_MAP_REG_MSDM_RAM                                                                                0x1d00000UL //Access:RW   DataWidth:0x20   // MSDM RAM
+#define BAR0_MAP_REG_MSDM_RAM_SIZE                                                                           131072
+#define BAR0_MAP_REG_USDM_RAM                                                                                0x1d80000UL //Access:RW   DataWidth:0x20   // USDM RAM
+#define BAR0_MAP_REG_USDM_RAM_SIZE                                                                           131072
+#define BAR0_MAP_REG_XSDM_RAM                                                                                0x1e00000UL //Access:RW   DataWidth:0x20   // XSDM RAM
+#define BAR0_MAP_REG_XSDM_RAM_SIZE                                                                           131072
+#define BAR0_MAP_REG_YSDM_RAM                                                                                0x1e80000UL //Access:RW   DataWidth:0x20   // YSDM RAM
+#define BAR0_MAP_REG_YSDM_RAM_SIZE                                                                           131072
+#define BAR0_MAP_REG_PSDM_RAM                                                                                0x1f00000UL //Access:RW   DataWidth:0x20   // PSDM RAM
+#define BAR0_MAP_REG_PSDM_RAM_SIZE                                                                           131072
+
+#endif
